Put comments in the code that give a reference to people who think that setting BASE_...

git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@1772 1d2547de-c912-0410-9cb9-b8ca96c0e9e2

diff --git a/FreeRTOS/Source/portable/GCC/ARM_CM3/portmacro.h b/FreeRTOS/Source/portable/GCC/ARM_CM3/portmacro.h
index a0c3e94c00e60cca0696770a470ee5d0c3435f86..80e2d67c54ca5365a5f60bfbbea88af96a563025 100644 (file)
--- a/FreeRTOS/Source/portable/GCC/ARM_CM3/portmacro.h
+++ b/FreeRTOS/Source/portable/GCC/ARM_CM3/portmacro.h
@@ -132,7 +132,8 @@ extern void vPortYieldFromISR( void );
        \r
 /*\r
  * Set basepri back to 0 without effective other registers.\r
- * r0 is clobbered.\r
+ * r0 is clobbered.  FAQ:  Setting BASEPRI to 0 is not a bug.  Please see \r
+ * http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html before disagreeing.\r
  */\r
 #define portCLEAR_INTERRUPT_MASK()                     \\r
        __asm volatile                                                  \\r
@@ -142,6 +143,9 @@ extern void vPortYieldFromISR( void );
                :::"r0"                                                         \\r
        )\r
 \r
+/* FAQ:  Setting BASEPRI to 0 in portCLEAR_INTERRUPT_MASK_FROM_ISR() is not a \r
+bug.  Please see http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html before \r
+disagreeing. */\r
 #define portSET_INTERRUPT_MASK_FROM_ISR()              0;portSET_INTERRUPT_MASK()\r
 #define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)   portCLEAR_INTERRUPT_MASK();(void)x\r
 \r

diff --git a/FreeRTOS/Source/portable/GCC/ARM_CM3_MPU/portmacro.h b/FreeRTOS/Source/portable/GCC/ARM_CM3_MPU/portmacro.h
index 164619574ef43843322e56977c1ade04085d64bc..7b15dcce740d45775ad341c5a0fa3a14e5b33007 100644 (file)
--- a/FreeRTOS/Source/portable/GCC/ARM_CM3_MPU/portmacro.h
+++ b/FreeRTOS/Source/portable/GCC/ARM_CM3_MPU/portmacro.h
@@ -173,7 +173,8 @@ typedef struct MPU_SETTINGS
 \r
 /*\r
  * Set basepri back to 0 without effective other registers.\r
- * r0 is clobbered.\r
+ * r0 is clobbered.  FAQ:  Setting BASEPRI to 0 is not a bug.  Please see \r
+ * http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html before disagreeing.\r
  */\r
 #define portCLEAR_INTERRUPT_MASK()                     \\r
        __asm volatile                                                  \\r
@@ -183,6 +184,8 @@ typedef struct MPU_SETTINGS
                :::"r0"                                                         \\r
        )\r
 \r
+/* FAQ:  Setting BASEPRI to 0 is not a bug.  Please see \r
+http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html before disagreeing. */\r
 #define portSET_INTERRUPT_MASK_FROM_ISR()              0;portSET_INTERRUPT_MASK()\r
 #define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)   portCLEAR_INTERRUPT_MASK();(void)x\r
 \r

diff --git a/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h b/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h
index ddb14071ea96ee7631fb5b31a5b5dad544df2c82..798be5e0931070b1181efd113656e8cac4ebfc4d 100644 (file)
--- a/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h
+++ b/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h
@@ -132,7 +132,8 @@ extern void vPortYieldFromISR( void );
        \r
 /*\r
  * Set basepri back to 0 without effective other registers.\r
- * r0 is clobbered.\r
+ * r0 is clobbered.  FAQ:  Setting BASEPRI to 0 is not a bug.  Please see \r
+ * http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html before disagreeing.\r
  */\r
 #define portCLEAR_INTERRUPT_MASK()                     \\r
        __asm volatile                                                  \\r
@@ -142,6 +143,9 @@ extern void vPortYieldFromISR( void );
                :::"r0"                                                         \\r
        )\r
 \r
+/* FAQ:  Setting BASEPRI to 0 in portCLEAR_INTERRUPT_MASK_FROM_ISR() is not a \r
+bug.  Please see http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html before \r
+disagreeing. */\r
 #define portSET_INTERRUPT_MASK_FROM_ISR()              0;portSET_INTERRUPT_MASK()\r
 #define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)   portCLEAR_INTERRUPT_MASK();(void)x\r
 \r

diff --git a/FreeRTOS/Source/portable/IAR/ARM_CM3/portasm.s b/FreeRTOS/Source/portable/IAR/ARM_CM3/portasm.s
index e6f0221f1fe6ddb6865fa45e26b54724ca3321b0..c9e0bb3caf370eea6d3f33746b00b834631d1270 100644 (file)
--- a/FreeRTOS/Source/portable/IAR/ARM_CM3/portasm.s
+++ b/FreeRTOS/Source/portable/IAR/ARM_CM3/portasm.s
@@ -123,20 +123,18 @@ xPortPendSVHandler:
 /*-----------------------------------------------------------*/\r
 \r
 vPortSetInterruptMask:\r
-       push { r0 }\r
-       mov R0, #configMAX_SYSCALL_INTERRUPT_PRIORITY\r
-       msr BASEPRI, R0\r
-       pop { R0 }\r
+       mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY\r
+       msr BASEPRI, r0\r
 \r
        bx r14\r
        \r
 /*-----------------------------------------------------------*/\r
 \r
 vPortClearInterruptMask:\r
-       PUSH { r0 }\r
-       MOV R0, #0\r
-       MSR BASEPRI, R0\r
-       POP      { R0 }\r
+       /* FAQ:  Setting BASEPRI to 0 is not a bug.  Please see \r
+       http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html before disagreeing. */\r
+       mov r0, #0\r
+       msr BASEPRI, r0\r
 \r
        bx r14\r
 \r

diff --git a/FreeRTOS/Source/portable/IAR/ARM_CM3/portmacro.h b/FreeRTOS/Source/portable/IAR/ARM_CM3/portmacro.h
index f8bbd460048b1c7a9849420d01aeb7d941a09e30..939b640b530d6379ac37d3f3208012089be0586a 100644 (file)
--- a/FreeRTOS/Source/portable/IAR/ARM_CM3/portmacro.h
+++ b/FreeRTOS/Source/portable/IAR/ARM_CM3/portmacro.h
@@ -127,6 +127,9 @@ extern void vPortClearInterruptMask( void );
 #define portENABLE_INTERRUPTS()                vPortClearInterruptMask()\r
 #define portENTER_CRITICAL()                                   vPortEnterCritical()\r
 #define portEXIT_CRITICAL()                                            vPortExitCritical()\r
+\r
+/* FAQ:  Setting BASEPRI to 0 is not a bug.  Please see \r
+http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html before disagreeing. */\r
 #define portSET_INTERRUPT_MASK_FROM_ISR()              0;vPortSetInterruptMask()\r
 #define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)   vPortClearInterruptMask();(void)x\r
 \r

diff --git a/FreeRTOS/Source/portable/IAR/ARM_CM4F/portasm.s b/FreeRTOS/Source/portable/IAR/ARM_CM4F/portasm.s
index 94ac95c215ece0b68f2fc7c53b5c3bb673537f52..26eb6267e98350bfbc03691fc564be6138d673a7 100644 (file)
--- a/FreeRTOS/Source/portable/IAR/ARM_CM4F/portasm.s
+++ b/FreeRTOS/Source/portable/IAR/ARM_CM4F/portasm.s
@@ -136,6 +136,8 @@ vPortSetInterruptMask:
 /*-----------------------------------------------------------*/\r
 \r
 vPortClearInterruptMask:\r
+       /* FAQ:  Setting BASEPRI to 0 is not a bug.  Please see \r
+       http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html before disagreeing. */\r
        mov r0, #0\r
        msr BASEPRI, r0\r
 \r

diff --git a/FreeRTOS/Source/portable/IAR/ARM_CM4F/portmacro.h b/FreeRTOS/Source/portable/IAR/ARM_CM4F/portmacro.h
index d4ec8c1e9b86b471346e169a6b1511d851a8ef50..b88474d2ba53a42f944570730ce8a8a7ce116fbd 100644 (file)
--- a/FreeRTOS/Source/portable/IAR/ARM_CM4F/portmacro.h
+++ b/FreeRTOS/Source/portable/IAR/ARM_CM4F/portmacro.h
@@ -127,6 +127,9 @@ extern void vPortClearInterruptMask( void );
 #define portENABLE_INTERRUPTS()                vPortClearInterruptMask()\r
 #define portENTER_CRITICAL()                                   vPortEnterCritical()\r
 #define portEXIT_CRITICAL()                                            vPortExitCritical()\r
+\r
+/* FAQ:  Setting BASEPRI to 0 is not a bug.  Please see \r
+http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html before disagreeing. */\r
 #define portSET_INTERRUPT_MASK_FROM_ISR()              0;vPortSetInterruptMask()\r
 #define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)   vPortClearInterruptMask();(void)x\r
 \r

diff --git a/FreeRTOS/Source/portable/RVDS/ARM_CM3/port.c b/FreeRTOS/Source/portable/RVDS/ARM_CM3/port.c
index 20a2fce4300c52e72b6a7ae16be74022bef3ce80..d109cecd3932af1faa0ebe7d145a3d1eb2f31f9d 100644 (file)
--- a/FreeRTOS/Source/portable/RVDS/ARM_CM3/port.c
+++ b/FreeRTOS/Source/portable/RVDS/ARM_CM3/port.c
@@ -294,10 +294,8 @@ __asm void vPortSetInterruptMask( void )
 {\r
        PRESERVE8\r
 \r
-       push { r0 }\r
        mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY\r
        msr basepri, r0\r
-       pop { r0 }\r
        bx r14\r
 }\r
 \r
@@ -307,9 +305,9 @@ __asm void vPortClearInterruptMask( void )
 {\r
        PRESERVE8\r
 \r
-       push { r0 }\r
+       /* FAQ:  Setting BASEPRI to 0 is not a bug.  Please see \r
+       http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html before disagreeing. */\r
        mov r0, #0\r
        msr basepri, r0\r
-       pop { r0 }\r
        bx r14\r
 }\r

diff --git a/FreeRTOS/Source/portable/RVDS/ARM_CM3/portmacro.h b/FreeRTOS/Source/portable/RVDS/ARM_CM3/portmacro.h
index e784875519a4e6ddf8cc4f289f7b55bbc3625e5d..0b60eb20273cfb4f3be5d3576337fd807592fef7 100644 (file)
--- a/FreeRTOS/Source/portable/RVDS/ARM_CM3/portmacro.h
+++ b/FreeRTOS/Source/portable/RVDS/ARM_CM3/portmacro.h
@@ -127,6 +127,9 @@ extern void vPortExitCritical( void );
 #define portENABLE_INTERRUPTS()                                        vPortClearInterruptMask()\r
 #define portENTER_CRITICAL()                                   vPortEnterCritical()\r
 #define portEXIT_CRITICAL()                                            vPortExitCritical()\r
+\r
+/* FAQ:  Setting BASEPRI to 0 is not a bug.  Please see \r
+http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html before disagreeing. */\r
 #define portSET_INTERRUPT_MASK_FROM_ISR()              0;vPortSetInterruptMask()\r
 #define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)   vPortClearInterruptMask();(void)x\r
 \r

diff --git a/FreeRTOS/Source/portable/RVDS/ARM_CM4F/port.c b/FreeRTOS/Source/portable/RVDS/ARM_CM4F/port.c
index 42d56df9c99a0d7326b1a3274649769d258d0e63..a8fdad6868f72c8642958f5528da3a858dbbab30 100644 (file)
--- a/FreeRTOS/Source/portable/RVDS/ARM_CM4F/port.c
+++ b/FreeRTOS/Source/portable/RVDS/ARM_CM4F/port.c
@@ -369,6 +369,8 @@ __asm void vPortClearInterruptMask( void )
 {\r
        PRESERVE8\r
 \r
+       /* FAQ:  Setting BASEPRI to 0 is not a bug.  Please see \r
+       http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html before disagreeing. */\r
        mov r0, #0\r
        msr basepri, r0\r
        bx r14\r

diff --git a/FreeRTOS/Source/portable/RVDS/ARM_CM4F/portmacro.h b/FreeRTOS/Source/portable/RVDS/ARM_CM4F/portmacro.h
index 5b55a9c53c09af8e94c56f06b12f1a15e1a113be..e3b86b0edcc2600d2b0717fde8f8b90aec9e8bb2 100644 (file)
--- a/FreeRTOS/Source/portable/RVDS/ARM_CM4F/portmacro.h
+++ b/FreeRTOS/Source/portable/RVDS/ARM_CM4F/portmacro.h
@@ -127,6 +127,9 @@ extern void vPortExitCritical( void );
 #define portENABLE_INTERRUPTS()                                        vPortClearInterruptMask()\r
 #define portENTER_CRITICAL()                                   vPortEnterCritical()\r
 #define portEXIT_CRITICAL()                                            vPortExitCritical()\r
+\r
+/* FAQ:  Setting BASEPRI to 0 is not a bug.  Please see \r
+http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html before disagreeing. */\r
 #define portSET_INTERRUPT_MASK_FROM_ISR()              0;vPortSetInterruptMask()\r
 #define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)   vPortClearInterruptMask();(void)x\r
 \r

diff --git a/FreeRTOS/Source/portable/Tasking/ARM_CM4F/portmacro.h b/FreeRTOS/Source/portable/Tasking/ARM_CM4F/portmacro.h
index 5766789a1b73fe83dea16ba1452e38a502d2f3eb..ea1e8786a2d9c1ef6e86483aa2b4965c004377be 100644 (file)
--- a/FreeRTOS/Source/portable/Tasking/ARM_CM4F/portmacro.h
+++ b/FreeRTOS/Source/portable/Tasking/ARM_CM4F/portmacro.h
@@ -126,10 +126,13 @@ extern void vPortYieldFromISR( void );
        \r
 /*\r
  * Set basepri back to 0 without effective other registers.\r
- * r0 is clobbered.\r
+ * r0 is clobbered.  FAQ:  Setting BASEPRI to 0 is not a bug.  Please see \r
+ * http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html before disagreeing.\r
  */\r
 #define portCLEAR_INTERRUPT_MASK() __set_BASEPRI( 0 )\r
 \r
+/* FAQ:  Setting BASEPRI to 0 is not a bug.  Please see \r
+http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html before disagreeing. */\r
 #define portSET_INTERRUPT_MASK_FROM_ISR()              0;portSET_INTERRUPT_MASK()\r
 #define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)   portCLEAR_INTERRUPT_MASK();(void)x\r
 \r