nb = (2 << (8 - size)) * page_size;
/* There are 4 pages per row */
- command_print(CMD_CTX, "Bootloader size is %u bytes (%u rows)",
- nb, nb / (page_size * 4));
+ command_print(CMD_CTX, "Bootloader size is %" PRIu32 " bytes (%" PRIu32 " rows)",
+ nb, (uint32_t)(nb / (page_size * 4)));
}
}
}
break;
default:
- LOG_ERROR("BUG: unknown Part ID encountered: 0x%x", part_id);
+ LOG_ERROR("BUG: unknown Part ID encountered: 0x%" PRIx32, part_id);
exit(-1);
}
status = get_lpc2000_part_id(bank, &part_id);
if (status == LPC2000_CMD_SUCCESS)
LOG_INFO("If auto-detection fails for this part, please email "
- "openocd-devel@lists.sourceforge.net, citing part id 0x%x.\n", part_id);
+ "openocd-devel@lists.sourceforge.net, citing part id 0x%" PRIx32 ".\n", part_id);
}
lpc2000_build_sector_list(bank);
LOG_DEBUG("Erasing page at 0x%"PRIx32, sector->offset);
if (sector->is_protected) {
- LOG_ERROR("Cannot erase protected sector at 0x%x", sector->offset);
+ LOG_ERROR("Cannot erase protected sector at 0x%" PRIx32, sector->offset);
return ERROR_FAIL;
}
"for padding buffer");
return ERROR_FAIL;
}
- LOG_INFO("odd number of bytes to write (%d), extending to %d "
- "and padding with 0xff", old_count, count);
+ LOG_INFO("odd number of bytes to write (%" PRIu32 "), extending to %" PRIu32
+ " and padding with 0xff", old_count, count);
new_buffer[count - 1] = 0xff;
buffer = memcpy(new_buffer, buffer, old_count);
printed = snprintf(buf,
buf_size,
"did1: 0x%8.8" PRIx32 ", arch: 0x%4.4" PRIx32
- ", eproc: %s, ramsize: %ik, flashsize: %ik\n",
+ ", eproc: %s, ramsize: %" PRIu32 "k, flashsize: %" PRIu32 "k\n",
stellaris_info->did1,
stellaris_info->did1,
"ARMv7M",
stellaris_info->sramsiz,
- stellaris_info->num_pages * stellaris_info->pagesize / 1024);
+ (uint32_t)(stellaris_info->num_pages * stellaris_info->pagesize / 1024));
buf += printed;
buf_size -= printed;
uint32_t c_cid0, c_cid1, c_cid2, c_cid3;
uint32_t c_pid0, c_pid1, c_pid2, c_pid3, c_pid4;
uint32_t component_base;
- unsigned part_num;
+ uint32_t part_num;
const char *type, *full;
component_base = (dbgbase & 0xFFFFF000) + (romentry & 0xFFFFF000);
the registers in the Core Power Domain */
retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap,
armv7a->debug_base + CPUDBG_PRSR, &dbg_osreg);
- LOG_DEBUG("target->coreid %d DBGPRSR 0x%x ", target->coreid, dbg_osreg);
+ LOG_DEBUG("target->coreid %" PRId32 " DBGPRSR 0x%" PRIx32, target->coreid, dbg_osreg);
if (retval != ERROR_OK)
return retval;
if (retval != ERROR_OK)
return retval;
- LOG_DEBUG("target->coreid %d DBGPRSR 0x%" PRIx32, target->coreid, dbg_osreg);
+ LOG_DEBUG("target->coreid %" PRId32 " DBGPRSR 0x%" PRIx32, target->coreid, dbg_osreg);
armv7a->arm.core_type = ARM_MODE_MON;
retval = cortex_a_dpm_setup(cortex_a, didr);
EJTAG_IMP_HAS(EJTAG_V20_IMP_NOPB) ? " noPB" : " PB",
EJTAG_IMP_HAS(EJTAG_V20_IMP_NODB) ? " noDB" : " DB",
EJTAG_IMP_HAS(EJTAG_V20_IMP_NOIB) ? " noIB" : " IB");
- LOG_DEBUG("EJTAG v2.0: Break Channels: %i",
- (ejtag_info->impcode >> EJTAG_V20_IMP_BCHANNELS_SHIFT) &
- EJTAG_V20_IMP_BCHANNELS_MASK);
+ LOG_DEBUG("EJTAG v2.0: Break Channels: %" PRIu8,
+ (uint8_t)((ejtag_info->impcode >> EJTAG_V20_IMP_BCHANNELS_SHIFT) &
+ EJTAG_V20_IMP_BCHANNELS_MASK));
}
static void ejtag_v26_print_imp(struct mips_ejtag *ejtag_info)