ARM: rename armv4_5_state_* as arm_state_*

And make arm_state_strings[] be const.

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>

diff --git a/src/target/arm720t.c b/src/target/arm720t.c
index a4d274ea3f4de834897f400ad68d0696a0fe2402..48cfdf01ce1742776e07ea2ee655af9659919f47 100644 (file)
--- a/src/target/arm720t.c
+++ b/src/target/arm720t.c
@@ -237,7 +237,7 @@ static int arm720t_arch_state(struct target *target)
        LOG_USER("target halted in %s state due to %s, current mode: %s\n"
                        "cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "\n"
                        "MMU: %s, Cache: %s",
-                        armv4_5_state_strings[armv4_5->core_state],
+                        arm_state_strings[armv4_5->core_state],
                         Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name ,
                         arm_mode_name(armv4_5->core_mode),
                         buf_get_u32(armv4_5->cpsr->value, 0, 32),

diff --git a/src/target/arm920t.c b/src/target/arm920t.c
index e8c1950fa37cf997a767d69c0483cf22e3fa3bdc..6a5faffdc7ba98b1c1bb9d06afde14665701764e 100644 (file)
--- a/src/target/arm920t.c
+++ b/src/target/arm920t.c
@@ -451,7 +451,7 @@ int arm920t_arch_state(struct target *target)
        LOG_USER("target halted in %s state due to %s, current mode: %s\n"
                        "cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "\n"
                        "MMU: %s, D-Cache: %s, I-Cache: %s",
-                        armv4_5_state_strings[armv4_5->core_state],
+                        arm_state_strings[armv4_5->core_state],
                         Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name,
                         arm_mode_name(armv4_5->core_mode),
                         buf_get_u32(armv4_5->cpsr->value, 0, 32),

diff --git a/src/target/arm926ejs.c b/src/target/arm926ejs.c
index 4dec23da79872a9926e5d8ee3e00d3d76d33a5f1..cacb94286bd5cc3ea650cab8356286c0e914d4be 100644 (file)
--- a/src/target/arm926ejs.c
+++ b/src/target/arm926ejs.c
@@ -507,7 +507,7 @@ int arm926ejs_arch_state(struct target *target)
        LOG_USER("target halted in %s state due to %s, current mode: %s\n"
                        "cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "\n"
                        "MMU: %s, D-Cache: %s, I-Cache: %s",
-                        armv4_5_state_strings[armv4_5->core_state],
+                        arm_state_strings[armv4_5->core_state],
                         Jim_Nvp_value2name_simple(nvp_target_debug_reason,target->debug_reason)->name,
                         arm_mode_name(armv4_5->core_mode),
                         buf_get_u32(armv4_5->cpsr->value, 0, 32),

diff --git a/src/target/arm_simulator.c b/src/target/arm_simulator.c
index c252b444e878d6e97b01f30c9d6e76425d12438d..cb1f65180aa4ecedfd2653d8b42b38170df75d3c 100644 (file)
--- a/src/target/arm_simulator.c
+++ b/src/target/arm_simulator.c
@@ -824,14 +824,14 @@ static uint32_t armv4_5_get_cpsr(struct arm_sim_interface *sim, int pos, int bit
        return buf_get_u32(armv4_5->cpsr->value, pos, bits);
 }
 
-static enum armv4_5_state armv4_5_get_state(struct arm_sim_interface *sim)
+static enum arm_state armv4_5_get_state(struct arm_sim_interface *sim)
 {
        struct arm *armv4_5 = (struct arm *)sim->user_data;
 
        return armv4_5->core_state;
 }
 
-static void armv4_5_set_state(struct arm_sim_interface *sim, enum armv4_5_state mode)
+static void armv4_5_set_state(struct arm_sim_interface *sim, enum arm_state mode)
 {
        struct arm *armv4_5 = (struct arm *)sim->user_data;
 

diff --git a/src/target/arm_simulator.h b/src/target/arm_simulator.h
index ae3afada7936470e1ed69a26a56db9f983b0791b..bd5458e409b1244fb50486c7f8f54b7e784cd1c6 100644 (file)
--- a/src/target/arm_simulator.h
+++ b/src/target/arm_simulator.h
@@ -32,8 +32,8 @@ struct arm_sim_interface
        uint32_t (*get_reg_mode)(struct arm_sim_interface *sim, int reg);
        void (*set_reg_mode)(struct arm_sim_interface *sim, int reg, uint32_t value);
        uint32_t (*get_cpsr)(struct arm_sim_interface *sim, int pos, int bits);
-       enum armv4_5_state (*get_state)(struct arm_sim_interface *sim);
-       void (*set_state)(struct arm_sim_interface *sim, enum armv4_5_state mode);
+       enum arm_state (*get_state)(struct arm_sim_interface *sim);
+       void (*set_state)(struct arm_sim_interface *sim, enum arm_state mode);
        enum arm_mode (*get_mode)(struct arm_sim_interface *sim);
 };
 

diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c
index 15c0a7f47f6c761aba0e759c05a4c46109d10437..102913b560f9d7ea143df75617301be865c3376a 100644 (file)
--- a/src/target/armv4_5.c
+++ b/src/target/armv4_5.c
@@ -216,7 +216,7 @@ enum arm_mode armv4_5_number_to_mode(int number)
        }
 }
 
-char* armv4_5_state_strings[] =
+const char *arm_state_strings[] =
 {
        "ARM", "Thumb", "Jazelle", "ThumbEE",
 };
@@ -374,7 +374,7 @@ void arm_set_cpsr(struct arm *arm, uint32_t cpsr)
                        : arm->core_cache->reg_list + arm->map[16];
 
        /* Older ARMs won't have the J bit */
-       enum armv4_5_state state;
+       enum arm_state state;
 
        if (cpsr & (1 << 5)) {  /* T */
                if (cpsr & (1 << 24)) { /* J */
@@ -393,7 +393,7 @@ void arm_set_cpsr(struct arm *arm, uint32_t cpsr)
 
        LOG_DEBUG("set CPSR %#8.8x: %s mode, %s state", (unsigned) cpsr,
                        arm_mode_name(mode),
-                       armv4_5_state_strings[arm->core_state]);
+                       arm_state_strings[arm->core_state]);
 }
 
 /**
@@ -593,7 +593,7 @@ int armv4_5_arch_state(struct target *target)
 
        LOG_USER("target halted in %s state due to %s, current mode: %s\n"
                        "cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "%s",
-                        armv4_5_state_strings[armv4_5->core_state],
+                        arm_state_strings[armv4_5->core_state],
                         Jim_Nvp_value2name_simple(nvp_target_debug_reason,
                                        target->debug_reason)->name,
                         arm_mode_name(armv4_5->core_mode),
@@ -718,7 +718,7 @@ COMMAND_HANDLER(handle_armv4_5_core_state_command)
                }
        }
 
-       command_print(CMD_CTX, "core state: %s", armv4_5_state_strings[armv4_5->core_state]);
+       command_print(CMD_CTX, "core state: %s", arm_state_strings[armv4_5->core_state]);
 
        return ERROR_OK;
 }
@@ -1038,7 +1038,7 @@ int armv4_5_run_algorithm_inner(struct target *target,
 {
        struct arm *armv4_5 = target_to_armv4_5(target);
        struct armv4_5_algorithm *armv4_5_algorithm_info = arch_info;
-       enum armv4_5_state core_state = armv4_5->core_state;
+       enum arm_state core_state = armv4_5->core_state;
        uint32_t context[17];
        uint32_t cpsr;
        int exit_breakpoint_size = 0;

diff --git a/src/target/armv4_5.h b/src/target/armv4_5.h
index e2b7b5a5c420819aed5e9e8a0454e904d983d9b5..5d58aa356179d18303f4076ebc97dfb16318934a 100644 (file)
--- a/src/target/armv4_5.h
+++ b/src/target/armv4_5.h
@@ -49,15 +49,15 @@ bool is_arm_mode(unsigned psr_mode);
 int arm_mode_to_number(enum arm_mode mode);
 enum arm_mode armv4_5_number_to_mode(int number);
 
-typedef enum armv4_5_state
+typedef enum arm_state
 {
        ARM_STATE_ARM,
        ARM_STATE_THUMB,
        ARM_STATE_JAZELLE,
        ARM_STATE_THUMB_EE,
-} armv4_5_state_t;
+} arm_state_t;
 
-extern char* armv4_5_state_strings[];
+extern const char *arm_state_strings[];
 
 extern const int armv4_5_core_reg_map[8][17];
 
@@ -98,7 +98,7 @@ struct arm
        enum arm_mode core_type;
 
        enum arm_mode core_mode;
-       enum armv4_5_state core_state;
+       enum arm_state core_state;
 
        /** Flag reporting unavailability of the BKPT instruction. */
        bool is_armv4;
@@ -159,7 +159,7 @@ struct armv4_5_algorithm
        int common_magic;
 
        enum arm_mode core_mode;
-       enum armv4_5_state core_state;
+       enum arm_state core_state;
 };
 
 struct arm_reg

diff --git a/src/target/armv7a.h b/src/target/armv7a.h
index ad1f094b6052d2676fd0cc1a5d5ca1519cc00350..24ec8198588adb4048f888d516bb1f7f21c619db 100644 (file)
--- a/src/target/armv7a.h
+++ b/src/target/armv7a.h
@@ -119,7 +119,7 @@ struct armv7a_algorithm
        int common_magic;
 
        enum arm_mode core_mode;
-       enum armv4_5_state core_state;
+       enum arm_state core_state;
 };
 
 struct armv7a_core_reg

diff --git a/src/target/etm.h b/src/target/etm.h
index 656e04b7ea93b8e261c6d966bd1463b92def297d..92df0bf318ee3eec7851bf4d22026517f1c9042e 100644 (file)
--- a/src/target/etm.h
+++ b/src/target/etm.h
@@ -164,7 +164,7 @@ struct etm_context
        uint32_t trace_depth;           /* number of cycles to be analyzed, 0 if no data available */
        etm_portmode_t portmode;        /* normal, multiplexed or demultiplexed */
        etmv1_tracemode_t tracemode;    /* type of info trace contains */
-       int /*armv4_5_state_t*/ core_state;     /* current core state */
+       int /*arm_state_t*/ core_state; /* current core state */
        struct image *image;            /* source for target opcodes */
        uint32_t pipe_index;            /* current trace cycle */
        uint32_t data_index;            /* cycle holding next data packet */

diff --git a/src/target/feroceon.c b/src/target/feroceon.c
index 2644560bc4dfe94022a86bb940682d37003fbe32..1c701540c71d6db56b5ea254dd94babb32875e2e 100644 (file)
--- a/src/target/feroceon.c
+++ b/src/target/feroceon.c
@@ -455,7 +455,7 @@ int feroceon_bulk_write_memory(struct target *target, uint32_t address, uint32_t
        int retval;
        struct arm *armv4_5 = target->arch_info;
        struct arm7_9_common *arm7_9 = armv4_5->arch_info;
-       enum armv4_5_state core_state = armv4_5->core_state;
+       enum arm_state core_state = armv4_5->core_state;
        uint32_t x, flip, shift, save[7];
        uint32_t i;
 

diff --git a/src/target/xscale.c b/src/target/xscale.c
index 45692b82f36ca0dfd2d7eb21264cf80c81383bc9..253decbdfa6eb58913a7e19e20c329d0cab0980a 100644 (file)
--- a/src/target/xscale.c
+++ b/src/target/xscale.c
@@ -867,7 +867,7 @@ static int xscale_arch_state(struct target *target)
                        "cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "\n"
                        "MMU: %s, D-Cache: %s, I-Cache: %s"
                        "%s",
-                        armv4_5_state_strings[armv4_5->core_state],
+                        arm_state_strings[armv4_5->core_state],
                         Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name ,
                         arm_mode_name(armv4_5->core_mode),
                         buf_get_u32(armv4_5->cpsr->value, 0, 32),

diff --git a/src/target/xscale.h b/src/target/xscale.h
index 6f8117855de815fbb9c53c2ad422fe1f51cfa48d..2bb2ba5ea14dee84dd66456bdc7ad747511c4543 100644 (file)
--- a/src/target/xscale.h
+++ b/src/target/xscale.h
@@ -79,7 +79,7 @@ struct xscale_trace
        int buffer_fill;                                /* maximum number of trace runs to read (-1 for wrap-around) */
        int pc_ok;
        uint32_t current_pc;
-       armv4_5_state_t core_state;             /* current core state (ARM, Thumb, Jazelle) */
+       arm_state_t core_state;         /* current core state (ARM, Thumb, Jazelle) */
 };
 
 struct xscale_common