; I/O: MMU
MMU_CR = $FF00
-CC65_MMU_CFG = $0E ; Bank 0 with kernal ROM
+MMU_CFG_CC65 = %00001110 ; Bank 0 with kernal ROM
+MMU_CFG_RAM0 = %00111111 ; Bank 0 full RAM
+
; ---------------------------------------------------------------------------
; Super CPU
lda MMU_CR ; Get current memory configuration...
pha ; ...and save it for later
- lda #CC65_MMU_CFG ; Bank0 with kernal ROM
+ lda #MMU_CFG_CC65 ; Bank0 with kernal ROM
sta MMU_CR
; Save the zero page locations we need
cld ; Just to be sure
lda MMU_CR ; Get old register value
pha ; And save on stack
- lda #CC65_MMU_CFG ; Bank 0 with kernal ROM
+ lda #MMU_CFG_CC65 ; Bank 0 with kernal ROM
sta MMU_CR
ldy #<(__IRQFUNC_COUNT__*2)
lda #<__IRQFUNC_TABLE__
.segment "LOWCODE"
NmiHandler:
- lda #CC65_MMU_CFG ;(2)
+ lda #MMU_CFG_CC65 ;(2)
sta MMU_CR ;(4)
lda ACIA+RegStatus ;(4) ;status ;check for byte received
and #$08 ;(2)