Add MB91460 port and demo files.

git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@153 1d2547de-c912-0410-9cb9-b8ca96c0e9e2

diff --git a/Demo/MB91460_Softune/91460_template_91467d.dat b/Demo/MB91460_Softune/91460_template_91467d.dat
new file mode 100644 (file)
index 0000000..5132520
--- /dev/null
+++ b/Demo/MB91460_Softune/91460_template_91467d.dat
@@ -0,0 +1,182 @@
+$CPUSERIES-911\r
+$Prj-STANDALONE\r
+$0\r
+-g\r
+-w 1\r
+-INF LIST\r
+-I ".\SRC"\r
+-I ".\SRC\watchdog"\r
+-I "..\Common\include"\r
+-I "..\..\Source\include"\r
+-I "..\..\Source\portable\Softune\MB91460"\r
+-O 0\r
+-K SHORTADDRESS\r
+-B\r
+-K NOSCHEDULE\r
+-K A1\r
+-K SARG\r
+-Xdof\r
+-INF STACK\r
+-x vTaskIncrementTick,vTaskSwitchContext\r
+-K NOEOPT\r
+-K NOLIB\r
+-K NOUNROLL\r
+$other\r
+-Xalign\r
+-D__91467D\r
+$time\r
+1202156592\r
+$end\r
+$1\r
+-g\r
+-w 2\r
+-O 0\r
+-linf ON\r
+-lsrc ON\r
+-lsec ON\r
+-lcros OFF\r
+-linc ON\r
+-lexp OBJ\r
+-pl 60\r
+-pw 100\r
+-tab 8\r
+-Xdof\r
+$other\r
+$time\r
+1119939829\r
+$end\r
+$2\r
+-g\r
+-AL 2\r
+-ra D_RAM=0x00028100/0x0002FFFF\r
+-ra ID_RAM=0x00030000/0x00037FFF\r
+-ro ROM_AREA=0x00040000/0x0014FFFF\r
+-sc SSTACK/Stack+USTACK/Data+INIT/Data+DATA/Data=D_RAM\r
+-sc IRAM/Code=ID_RAM\r
+-sc CODE+@INIT+@IRAM+CONST=ROM_AREA\r
+-sc CODE_START/Code=0x000F4000\r
+-sc INTVECT/Const=0x000FFC00\r
+-check_locate\r
+-m\r
+-mmi\r
+-xlf\r
+-slf\r
+-mlf\r
+-pl 60\r
+-pw 132\r
+-Xals\r
+-Xalr\r
+-na\r
+-w 1\r
+-Xdof\r
+$other\r
+$time\r
+1201699972\r
+$end\r
+$3\r
+-dt s,d,r,a\r
+-pl 60\r
+-pw 132\r
+-g\r
+-Xdof\r
+$other\r
+$time\r
+1201699972\r
+$end\r
+$4\r
+-Xdof\r
+$other\r
+$time\r
+1119274137\r
+$end\r
+$5\r
+$other\r
+$time\r
+1119274137\r
+$end\r
+$Prjend\r
+$Prj-MONDEB_INTERNAL\r
+$0\r
+-g\r
+-w 1\r
+-O 4\r
+-K SPEED\r
+-K LONGADDRESS\r
+-B\r
+-K SCHEDULE\r
+-K A1\r
+-K SARG\r
+-Xdof\r
+-K EOPT\r
+-K LIB\r
+-K UNROLL\r
+$other\r
+-Xalign\r
+$time\r
+1161331678\r
+$end\r
+$1\r
+-g\r
+-w 2\r
+-O 0\r
+-linf ON\r
+-lsrc ON\r
+-lsec ON\r
+-lcros OFF\r
+-linc ON\r
+-lexp OBJ\r
+-pl 60\r
+-pw 100\r
+-tab 8\r
+-Xdof\r
+$other\r
+$time\r
+1142592435\r
+$end\r
+$2\r
+-g\r
+-AL 2\r
+-ra D_RAM=0x00029000/0x0002FFFF\r
+-ra ID_RAM=0x00030000/0x00037FFF\r
+-ro ROM_AREA=0x00840000/0x0094FFFF\r
+-ro SECURITY_AREA=0x00148000/0x0014800F\r
+-sc DATA/Data+INIT/Data+SSTACK/Data+USTACK/Data=D_RAM\r
+-sc IRAM/Code=ID_RAM\r
+-sc CODE+@INIT+@IRAM+CONST=ROM_AREA\r
+-sc CODE_START/Code=0x008F4000\r
+-check_locate\r
+-m\r
+-pl 60\r
+-pw 132\r
+-Xals\r
+-Xalr\r
+-na\r
+-w 1\r
+-Xdof\r
+$other\r
+$time\r
+1201109020\r
+$end\r
+$3\r
+-dt s,d,r,a\r
+-pl 60\r
+-pw 132\r
+-g\r
+-Xdof\r
+$other\r
+$time\r
+1201109020\r
+$end\r
+$4\r
+-Xdof\r
+$other\r
+$time\r
+1130252218\r
+$end\r
+$5\r
+$other\r
+$time\r
+1130252218\r
+$end\r
+$Prjend\r
+$CPUSERIESEND\r

diff --git a/Demo/MB91460_Softune/91467d_FreeRTOS.prj b/Demo/MB91460_Softune/91467d_FreeRTOS.prj
new file mode 100644 (file)
index 0000000..ce35271
--- /dev/null
+++ b/Demo/MB91460_Softune/91467d_FreeRTOS.prj
@@ -0,0 +1,606 @@
+[Version]\r
+DLLVer=02.5007.00.1\r
+PRJVer=1\r
+\r
+[PRJKIND]\r
+mode=1\r
+\r
+[CPUTYPE]\r
+CpuSerise=911\r
+\r
+[DirInfo]\r
+PRJ=C:\E\Dev\_FreeRTOS\Demo\MB91460_Softune\\r
+\r
+[PrjInfo]\r
+Count=2\r
+PrjInfo-0=STANDALONE\r
+PrjInfo-1=MONDEB_INTERNAL\r
+Active=STANDALONE\r
+\r
+[MEMBER]\r
+F0=44\r
+F1=0 f Source Files\r
+F2=0 c SRC\MAIN.c\r
+F3=0 a SRC\mb91467d.asm\r
+F4=0 a SRC\Start91460.asm\r
+F5=0 c SRC\vectors.c\r
+F6=0 f Source Files\portable\r
+F7=0 c ..\..\Source\portable\Softune\MB91460\__STD_LIB_sbrk.c\r
+F8=0 c ..\..\Source\portable\Softune\MB91460\port.c\r
+F9=0 f Source Files\FreeRTOS\r
+F10=0 c ..\..\Source\croutine.c\r
+F11=0 c ..\..\Source\list.c\r
+F12=0 c ..\..\Source\queue.c\r
+F13=0 c ..\..\Source\tasks.c\r
+F14=0 f Source Files\Minimal\r
+F15=0 c ..\Common\Minimal\AltBlckQ.c\r
+F16=0 c ..\Common\Minimal\AltBlock.c\r
+F17=0 c ..\Common\Minimal\AltPollQ.c\r
+F18=0 c ..\Common\Minimal\AltQTest.c\r
+F19=0 c ..\Common\Minimal\BlockQ.c\r
+F20=0 c ..\Common\Minimal\blocktim.c\r
+F21=0 c ..\Common\Minimal\comtest.c\r
+F22=0 c ..\Common\Minimal\countsem.c\r
+F23=0 c ..\Common\Minimal\crflash.c\r
+F24=0 c ..\Common\Minimal\crhook.c\r
+F25=0 c ..\Common\Minimal\death.c\r
+F26=0 c ..\Common\Minimal\dynamic.c\r
+F27=0 c ..\Common\Minimal\flash.c\r
+F28=0 c ..\Common\Minimal\flop.c\r
+F29=0 c ..\Common\Minimal\GenQTest.c\r
+F30=0 c ..\Common\Minimal\integer.c\r
+F31=0 c ..\Common\Minimal\PollQ.c\r
+F32=0 c ..\Common\Minimal\QPeek.c\r
+F33=0 c ..\Common\Minimal\semtest.c\r
+F34=0 f Source Files\MemMang\r
+F35=0 c ..\..\Source\portable\MemMang\heap_1.c\r
+F36=0 c ..\..\Source\portable\MemMang\heap_2.c\r
+F37=0 c ..\..\Source\portable\MemMang\heap_3.c\r
+F38=0 f Source Files\serial\r
+F39=0 c SRC\serial\serial.c\r
+F40=0 f Source Files\watchdog\r
+F41=0 c SRC\watchdog\watchdog.c\r
+F42=0 f Source Files\utility\r
+F43=0 c SRC\utility\taskutility.c\r
+F44=0 f Include Files\r
+\r
+[OPTIONFILE]\r
+FILE=91460_template_91467d.dat\r
+\r
+[CPUTYPE-STANDALONE]\r
+CsvFile=Lib\911\911.csv\r
+CpuName=MB91F467D\r
+ChgChipInfo-0=12@16:0:17:1:18:2:19:3:20:4:21:5:22:6:23:7:24:8:25:9:26:10:27:11:28:12:29:13:30:14:31:15:32:16:33:17:34:18:35:19:36:20:37:21:38:22:39:23:40:24:41:25:42:26:43:27:44:28:45:29:46:30:47:31:48:32:49:33:50:34:51:35:52:36:53:37:54:38:55:39:56:40:57:41:58:42:59:43:60:44:61:45:62:46:63:47:64:48:65:49:66:50:67:51:68:52:69:53:70:54:71:55:72:56:73:57:74:58:75:59:76:60:77:61:78:62:79:63\r
+Count=1\r
+BusMode=2\r
+BusWidth=2\r
+\r
+[DirInfo-STANDALONE]\r
+CONFIG=STANDALONE\\r
+OBJ=STANDALONE\OBJ\\r
+LST=STANDALONE\LST\\r
+OPT=STANDALONE\OPT\\r
+\r
+[MEMBER-STANDALONE]\r
+F0=36\r
+F1=0 m 1 STANDALONE\ABS\91467d_FreeRTOS.abs\r
+F2=9 c 1 ..\..\Source\portable\Softune\MB91460\port.c\r
+F2-1=- ..\..\Source\include\FreeRTOS.h\r
+F2-2=- ..\..\Source\include\projdefs.h\r
+F2-3=- SRC\FreeRTOSConfig.h\r
+F2-4=- ..\..\Source\include\portable.h\r
+F2-5=- SRC\mb91467d.h\r
+F2-6=- ..\..\Source\include\task.h\r
+F2-7=- ..\..\Source\include\list.h\r
+F2-8=- ..\..\..\..\..\devtools\Softune6\LIB\911\INCLUDE\stddef.h\r
+F2-9=- ..\..\Source\portable\Softune\MB91460\portmacro.h\r
+F3=3 c 1 ..\..\Source\portable\Softune\MB91460\__STD_LIB_sbrk.c\r
+F3-1=- SRC\FreeRTOSConfig.h\r
+F3-2=- ..\..\..\..\..\devtools\Softune6\LIB\911\INCLUDE\stdlib.h\r
+F3-3=- ..\..\..\..\..\devtools\Softune6\LIB\911\INCLUDE\stddef.h\r
+F4=10 c 1 ..\..\Source\croutine.c\r
+F4-1=- ..\..\Source\include\FreeRTOS.h\r
+F4-2=- ..\..\Source\include\projdefs.h\r
+F4-3=- SRC\FreeRTOSConfig.h\r
+F4-4=- ..\..\Source\include\portable.h\r
+F4-5=- ..\..\Source\include\task.h\r
+F4-6=- ..\..\Source\include\list.h\r
+F4-7=- ..\..\Source\include\croutine.h\r
+F4-8=- ..\..\..\..\..\devtools\Softune6\LIB\911\INCLUDE\stddef.h\r
+F4-9=- ..\..\Source\portable\Softune\MB91460\portmacro.h\r
+F4-10=- SRC\mb91467d.h\r
+F5=9 c 1 ..\..\Source\list.c\r
+F5-1=- ..\..\Source\include\FreeRTOS.h\r
+F5-2=- ..\..\Source\include\projdefs.h\r
+F5-3=- SRC\FreeRTOSConfig.h\r
+F5-4=- ..\..\Source\include\portable.h\r
+F5-5=- ..\..\Source\include\list.h\r
+F5-6=- ..\..\..\..\..\devtools\Softune6\LIB\911\INCLUDE\stdlib.h\r
+F5-7=- ..\..\..\..\..\devtools\Softune6\LIB\911\INCLUDE\stddef.h\r
+F5-8=- ..\..\Source\portable\Softune\MB91460\portmacro.h\r
+F5-9=- SRC\mb91467d.h\r
+F6=12 c 1 ..\..\Source\queue.c\r
+F6-1=- ..\..\Source\include\FreeRTOS.h\r
+F6-2=- ..\..\Source\include\projdefs.h\r
+F6-3=- SRC\FreeRTOSConfig.h\r
+F6-4=- ..\..\Source\include\portable.h\r
+F6-5=- ..\..\Source\portable\Softune\MB91460\portmacro.h\r
+F6-6=- SRC\mb91467d.h\r
+F6-7=- ..\..\Source\include\task.h\r
+F6-8=- ..\..\Source\include\list.h\r
+F6-9=- ..\..\Source\include\croutine.h\r
+F6-10=- ..\..\..\..\..\devtools\Softune6\LIB\911\INCLUDE\stdlib.h\r
+F6-11=- ..\..\..\..\..\devtools\Softune6\LIB\911\INCLUDE\stddef.h\r
+F6-12=- ..\..\..\..\..\devtools\Softune6\LIB\911\INCLUDE\string.h\r
+F7=13 c 1 ..\..\Source\tasks.c\r
+F7-1=- ..\..\Source\include\FreeRTOS.h\r
+F7-2=- ..\..\Source\include\projdefs.h\r
+F7-3=- SRC\FreeRTOSConfig.h\r
+F7-4=- ..\..\Source\include\portable.h\r
+F7-5=- ..\..\Source\portable\Softune\MB91460\portmacro.h\r
+F7-6=- SRC\mb91467d.h\r
+F7-7=- ..\..\Source\include\task.h\r
+F7-8=- ..\..\Source\include\list.h\r
+F7-9=- ..\..\..\..\..\devtools\Softune6\LIB\911\INCLUDE\stdio.h\r
+F7-10=- ..\..\..\..\..\devtools\Softune6\LIB\911\INCLUDE\stddef.h\r
+F7-11=- ..\..\..\..\..\devtools\Softune6\LIB\911\INCLUDE\stdarg.h\r
+F7-12=- ..\..\..\..\..\devtools\Softune6\LIB\911\INCLUDE\stdlib.h\r
+F7-13=- ..\..\..\..\..\devtools\Softune6\LIB\911\INCLUDE\string.h\r
+F8=11 c 1 SRC\MAIN.c\r
+F8-1=- SRC\mb91467d.h\r
+F8-2=- SRC\vectors.h\r
+F8-3=- ..\..\Source\include\FreeRTOS.h\r
+F8-4=- ..\..\Source\include\projdefs.h\r
+F8-5=- SRC\FreeRTOSConfig.h\r
+F8-6=- ..\..\Source\include\portable.h\r
+F8-7=- ..\..\Source\portable\Softune\MB91460\portmacro.h\r
+F8-8=- ..\..\Source\include\task.h\r
+F8-9=- ..\..\Source\include\list.h\r
+F8-10=- SRC\watchdog\watchdog.h\r
+F8-11=- ..\..\..\..\..\devtools\Softune6\LIB\911\INCLUDE\stddef.h\r
+F9=2 c 1 SRC\vectors.c\r
+F9-1=- SRC\mb91467d.h\r
+F9-2=- SRC\watchdog\watchdog.h\r
+F10=1 a 1 SRC\mb91467d.asm\r
+F10-1=- SRC\mb91467d.h\r
+F11=0 a 1 SRC\Start91460.asm\r
+F12=12 c 0 ..\Common\Minimal\AltBlckQ.c\r
+F12-1=- ..\..\..\..\..\..\..\..\SoftuneV6_32bit_REV600008\LIB\911\INCLUDE\stdlib.h\r
+F12-2=- ..\..\..\..\..\..\..\..\SoftuneV6_32bit_REV600008\LIB\911\INCLUDE\stddef.h\r
+F12-3=- ..\..\Source\include\FreeRTOS.h\r
+F12-4=- ..\..\Source\include\projdefs.h\r
+F12-5=- SRC\FreeRTOSConfig.h\r
+F12-6=- ..\..\Source\include\portable.h\r
+F12-7=- ..\..\Source\portable\Softune\MB91460\portmacro.h\r
+F12-8=- SRC\mb91467d.h\r
+F12-9=- ..\..\Source\include\task.h\r
+F12-10=- ..\..\Source\include\list.h\r
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+F13-1=- ..\..\Source\include\FreeRTOS.h\r
+F13-2=- ..\..\..\..\..\..\..\..\SoftuneV6_32bit_REV600008\LIB\911\INCLUDE\stddef.h\r
+F13-3=- ..\..\Source\include\projdefs.h\r
+F13-4=- SRC\FreeRTOSConfig.h\r
+F13-5=- ..\..\Source\include\portable.h\r
+F13-6=- ..\..\Source\portable\Softune\MB91460\portmacro.h\r
+F13-7=- SRC\mb91467d.h\r
+F13-8=- ..\..\Source\include\task.h\r
+F13-9=- ..\..\Source\include\list.h\r
+F13-10=- ..\..\Source\include\queue.h\r
+F13-11=- ..\Common\include\AltBlock.h\r
+F14=12 c 0 ..\Common\Minimal\AltPollQ.c\r
+F14-1=- ..\..\..\..\..\..\..\..\SoftuneV6_32bit_REV600008\LIB\911\INCLUDE\stdlib.h\r
+F14-2=- ..\..\..\..\..\..\..\..\SoftuneV6_32bit_REV600008\LIB\911\INCLUDE\stddef.h\r
+F14-3=- ..\..\Source\include\FreeRTOS.h\r
+F14-4=- ..\..\Source\include\projdefs.h\r
+F14-5=- SRC\FreeRTOSConfig.h\r
+F14-6=- ..\..\Source\include\portable.h\r
+F14-7=- ..\..\Source\portable\Softune\MB91460\portmacro.h\r
+F14-8=- SRC\mb91467d.h\r
+F14-9=- ..\..\Source\include\task.h\r
+F14-10=- ..\..\Source\include\list.h\r
+F14-11=- ..\..\Source\include\queue.h\r
+F14-12=- ..\Common\include\AltPollQ.h\r
+F15=13 c 0 ..\Common\Minimal\AltQTest.c\r
+F15-1=- ..\..\..\..\..\..\..\..\SoftuneV6_32bit_REV600008\LIB\911\INCLUDE\stdlib.h\r
+F15-2=- ..\..\..\..\..\..\..\..\SoftuneV6_32bit_REV600008\LIB\911\INCLUDE\stddef.h\r
+F15-3=- ..\..\Source\include\FreeRTOS.h\r
+F15-4=- ..\..\Source\include\projdefs.h\r
+F15-5=- SRC\FreeRTOSConfig.h\r
+F15-6=- ..\..\Source\include\portable.h\r
+F15-7=- ..\..\Source\portable\Softune\MB91460\portmacro.h\r
+F15-8=- SRC\mb91467d.h\r
+F15-9=- ..\..\Source\include\task.h\r
+F15-10=- ..\..\Source\include\list.h\r
+F15-11=- ..\..\Source\include\queue.h\r
+F15-12=- ..\..\Source\include\semphr.h\r
+F15-13=- ..\Common\include\AltQTest.h\r
+F16=12 c 1 ..\Common\Minimal\BlockQ.c\r
+F16-1=- ..\..\Source\include\FreeRTOS.h\r
+F16-2=- ..\..\Source\include\projdefs.h\r
+F16-3=- SRC\FreeRTOSConfig.h\r
+F16-4=- ..\..\Source\include\portable.h\r
+F16-5=- ..\..\Source\portable\Softune\MB91460\portmacro.h\r
+F16-6=- SRC\mb91467d.h\r
+F16-7=- ..\..\Source\include\task.h\r
+F16-8=- ..\..\Source\include\list.h\r
+F16-9=- ..\..\Source\include\queue.h\r
+F16-10=- ..\Common\include\BlockQ.h\r
+F16-11=- ..\..\..\..\..\devtools\Softune6\LIB\911\INCLUDE\stdlib.h\r
+F16-12=- ..\..\..\..\..\devtools\Softune6\LIB\911\INCLUDE\stddef.h\r
+F17=11 c 1 ..\Common\Minimal\blocktim.c\r
+F17-1=- ..\..\Source\include\FreeRTOS.h\r
+F17-2=- ..\..\Source\include\projdefs.h\r
+F17-3=- SRC\FreeRTOSConfig.h\r
+F17-4=- ..\..\Source\include\portable.h\r
+F17-5=- ..\..\Source\portable\Softune\MB91460\portmacro.h\r
+F17-6=- SRC\mb91467d.h\r
+F17-7=- ..\..\Source\include\task.h\r
+F17-8=- ..\..\Source\include\list.h\r
+F17-9=- ..\..\Source\include\queue.h\r
+F17-10=- ..\Common\include\blocktim.h\r
+F17-11=- ..\..\..\..\..\devtools\Softune6\LIB\911\INCLUDE\stddef.h\r
+F18=13 c 1 ..\Common\Minimal\comtest.c\r
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+F18-2=- ..\..\Source\include\projdefs.h\r
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+F18-4=- ..\..\Source\include\portable.h\r
+F18-5=- ..\..\Source\portable\Softune\MB91460\portmacro.h\r
+F18-6=- SRC\mb91467d.h\r
+F18-7=- ..\..\Source\include\task.h\r
+F18-8=- ..\..\Source\include\list.h\r
+F18-9=- ..\Common\include\serial.h\r
+F18-10=- ..\Common\include\comtest.h\r
+F18-11=- ..\Common\include\partest.h\r
+F18-12=- ..\..\..\..\..\devtools\Softune6\LIB\911\INCLUDE\stdlib.h\r
+F18-13=- ..\..\..\..\..\devtools\Softune6\LIB\911\INCLUDE\stddef.h\r
+F19=12 c 0 ..\Common\Minimal\countsem.c\r
+F19-1=- ..\..\Source\include\FreeRTOS.h\r
+F19-2=- ..\..\..\..\..\..\..\..\SoftuneV6_32bit_REV600008\LIB\911\INCLUDE\stddef.h\r
+F19-3=- ..\..\Source\include\projdefs.h\r
+F19-4=- SRC\FreeRTOSConfig.h\r
+F19-5=- ..\..\Source\include\portable.h\r
+F19-6=- ..\..\Source\portable\Softune\MB91460\portmacro.h\r
+F19-7=- SRC\mb91467d.h\r
+F19-8=- ..\..\Source\include\task.h\r
+F19-9=- ..\..\Source\include\list.h\r
+F19-10=- ..\..\Source\include\semphr.h\r
+F19-11=- ..\..\Source\include\queue.h\r
+F19-12=- ..\Common\include\countsem.h\r
+F20=12 c 1 ..\Common\Minimal\crflash.c\r
+F20-1=- ..\..\Source\include\FreeRTOS.h\r
+F20-2=- ..\..\Source\include\projdefs.h\r
+F20-3=- SRC\FreeRTOSConfig.h\r
+F20-4=- ..\..\Source\include\portable.h\r
+F20-5=- ..\..\Source\portable\Softune\MB91460\portmacro.h\r
+F20-6=- SRC\mb91467d.h\r
+F20-7=- ..\..\Source\include\croutine.h\r
+F20-8=- ..\..\Source\include\list.h\r
+F20-9=- ..\..\Source\include\queue.h\r
+F20-10=- ..\Common\include\partest.h\r
+F20-11=- ..\Common\include\crflash.h\r
+F20-12=- ..\..\..\..\..\devtools\Softune6\LIB\911\INCLUDE\stddef.h\r
+F21=11 c 1 ..\Common\Minimal\crhook.c\r
+F21-1=- ..\..\Source\include\FreeRTOS.h\r
+F21-2=- ..\..\Source\include\projdefs.h\r
+F21-3=- SRC\FreeRTOSConfig.h\r
+F21-4=- ..\..\Source\include\portable.h\r
+F21-5=- ..\..\Source\portable\Softune\MB91460\portmacro.h\r
+F21-6=- SRC\mb91467d.h\r
+F21-7=- ..\..\Source\include\croutine.h\r
+F21-8=- ..\..\Source\include\list.h\r
+F21-9=- ..\..\Source\include\queue.h\r
+F21-10=- ..\Common\include\crhook.h\r
+F21-11=- ..\..\..\..\..\devtools\Softune6\LIB\911\INCLUDE\stddef.h\r
+F22=11 c 1 ..\Common\Minimal\death.c\r
+F22-1=- ..\..\Source\include\FreeRTOS.h\r
+F22-2=- ..\..\Source\include\projdefs.h\r
+F22-3=- SRC\FreeRTOSConfig.h\r
+F22-4=- ..\..\Source\include\portable.h\r
+F22-5=- ..\..\Source\portable\Softune\MB91460\portmacro.h\r
+F22-6=- SRC\mb91467d.h\r
+F22-7=- ..\..\Source\include\task.h\r
+F22-8=- ..\..\Source\include\list.h\r
+F22-9=- ..\Common\include\death.h\r
+F22-10=- ..\..\..\..\..\devtools\Softune6\LIB\911\INCLUDE\stdlib.h\r
+F22-11=- ..\..\..\..\..\devtools\Softune6\LIB\911\INCLUDE\stddef.h\r
+F23=13 c 1 ..\Common\Minimal\dynamic.c\r
+F23-1=- ..\..\Source\include\FreeRTOS.h\r
+F23-2=- ..\..\Source\include\projdefs.h\r
+F23-3=- SRC\FreeRTOSConfig.h\r
+F23-4=- ..\..\Source\include\portable.h\r
+F23-5=- ..\..\Source\portable\Softune\MB91460\portmacro.h\r
+F23-6=- SRC\mb91467d.h\r
+F23-7=- ..\..\Source\include\task.h\r
+F23-8=- ..\..\Source\include\list.h\r
+F23-9=- ..\..\Source\include\queue.h\r
+F23-10=- ..\Common\include\dynamic.h\r
+F23-11=- ..\..\..\..\..\devtools\Softune6\LIB\911\INCLUDE\stdlib.h\r
+F23-12=- ..\..\..\..\..\devtools\Softune6\LIB\911\INCLUDE\stddef.h\r
+F23-13=- ..\Common\Minimal\semphr.h\r
+F24=12 c 1 ..\Common\Minimal\flash.c\r
+F24-1=- ..\..\Source\include\FreeRTOS.h\r
+F24-2=- ..\..\Source\include\projdefs.h\r
+F24-3=- SRC\FreeRTOSConfig.h\r
+F24-4=- ..\..\Source\include\portable.h\r
+F24-5=- ..\..\Source\portable\Softune\MB91460\portmacro.h\r
+F24-6=- SRC\mb91467d.h\r
+F24-7=- ..\..\Source\include\task.h\r
+F24-8=- ..\..\Source\include\list.h\r
+F24-9=- ..\Common\include\partest.h\r
+F24-10=- ..\Common\include\flash.h\r
+F24-11=- ..\..\..\..\..\devtools\Softune6\LIB\911\INCLUDE\stdlib.h\r
+F24-12=- ..\..\..\..\..\devtools\Softune6\LIB\911\INCLUDE\stddef.h\r
+F25=13 c 1 ..\Common\Minimal\flop.c\r
+F25-1=- ..\..\Source\include\FreeRTOS.h\r
+F25-2=- ..\..\Source\include\projdefs.h\r
+F25-3=- SRC\FreeRTOSConfig.h\r
+F25-4=- ..\..\Source\include\portable.h\r
+F25-5=- ..\..\Source\portable\Softune\MB91460\portmacro.h\r
+F25-6=- SRC\mb91467d.h\r
+F25-7=- ..\..\Source\include\task.h\r
+F25-8=- ..\..\Source\include\list.h\r
+F25-9=- ..\Common\include\flop.h\r
+F25-10=- ..\..\..\..\..\devtools\Softune6\LIB\911\INCLUDE\stdlib.h\r
+F25-11=- ..\..\..\..\..\devtools\Softune6\LIB\911\INCLUDE\stddef.h\r
+F25-12=- ..\..\..\..\..\devtools\Softune6\LIB\911\INCLUDE\math.h\r
+F25-13=- ..\..\..\..\..\devtools\Softune6\LIB\911\INCLUDE\errno.h\r
+F26=13 c 1 ..\Common\Minimal\GenQTest.c\r
+F26-1=- ..\..\Source\include\FreeRTOS.h\r
+F26-2=- ..\..\Source\include\projdefs.h\r
+F26-3=- SRC\FreeRTOSConfig.h\r
+F26-4=- ..\..\Source\include\portable.h\r
+F26-5=- ..\..\Source\portable\Softune\MB91460\portmacro.h\r
+F26-6=- SRC\mb91467d.h\r
+F26-7=- ..\..\Source\include\task.h\r
+F26-8=- ..\..\Source\include\list.h\r
+F26-9=- ..\..\Source\include\queue.h\r
+F26-10=- ..\Common\include\GenQTest.h\r
+F26-11=- ..\..\..\..\..\devtools\Softune6\LIB\911\INCLUDE\stdlib.h\r
+F26-12=- ..\..\..\..\..\devtools\Softune6\LIB\911\INCLUDE\stddef.h\r
+F26-13=- ..\Common\Minimal\semphr.h\r
+F27=11 c 1 ..\Common\Minimal\integer.c\r
+F27-1=- ..\..\Source\include\FreeRTOS.h\r
+F27-2=- ..\..\Source\include\projdefs.h\r
+F27-3=- SRC\FreeRTOSConfig.h\r
+F27-4=- ..\..\Source\include\portable.h\r
+F27-5=- ..\..\Source\portable\Softune\MB91460\portmacro.h\r
+F27-6=- SRC\mb91467d.h\r
+F27-7=- ..\..\Source\include\task.h\r
+F27-8=- ..\..\Source\include\list.h\r
+F27-9=- ..\Common\include\integer.h\r
+F27-10=- ..\..\..\..\..\devtools\Softune6\LIB\911\INCLUDE\stdlib.h\r
+F27-11=- ..\..\..\..\..\devtools\Softune6\LIB\911\INCLUDE\stddef.h\r
+F28=12 c 1 ..\Common\Minimal\PollQ.c\r
+F28-1=- ..\..\Source\include\FreeRTOS.h\r
+F28-2=- ..\..\Source\include\projdefs.h\r
+F28-3=- SRC\FreeRTOSConfig.h\r
+F28-4=- ..\..\Source\include\portable.h\r
+F28-5=- ..\..\Source\portable\Softune\MB91460\portmacro.h\r
+F28-6=- SRC\mb91467d.h\r
+F28-7=- ..\..\Source\include\task.h\r
+F28-8=- ..\..\Source\include\list.h\r
+F28-9=- ..\..\Source\include\queue.h\r
+F28-10=- ..\Common\include\PollQ.h\r
+F28-11=- ..\..\..\..\..\devtools\Softune6\LIB\911\INCLUDE\stdlib.h\r
+F28-12=- ..\..\..\..\..\devtools\Softune6\LIB\911\INCLUDE\stddef.h\r
+F29=13 c 1 ..\Common\Minimal\QPeek.c\r
+F29-1=- ..\..\Source\include\FreeRTOS.h\r
+F29-2=- ..\..\Source\include\projdefs.h\r
+F29-3=- SRC\FreeRTOSConfig.h\r
+F29-4=- ..\..\Source\include\portable.h\r
+F29-5=- ..\..\Source\portable\Softune\MB91460\portmacro.h\r
+F29-6=- SRC\mb91467d.h\r
+F29-7=- ..\..\Source\include\task.h\r
+F29-8=- ..\..\Source\include\list.h\r
+F29-9=- ..\..\Source\include\queue.h\r
+F29-10=- ..\Common\include\QPeek.h\r
+F29-11=- ..\..\..\..\..\devtools\Softune6\LIB\911\INCLUDE\stdlib.h\r
+F29-12=- ..\..\..\..\..\devtools\Softune6\LIB\911\INCLUDE\stddef.h\r
+F29-13=- ..\Common\Minimal\semphr.h\r
+F30=13 c 1 ..\Common\Minimal\semtest.c\r
+F30-1=- ..\..\Source\include\FreeRTOS.h\r
+F30-2=- ..\..\Source\include\projdefs.h\r
+F30-3=- SRC\FreeRTOSConfig.h\r
+F30-4=- ..\..\Source\include\portable.h\r
+F30-5=- ..\..\Source\portable\Softune\MB91460\portmacro.h\r
+F30-6=- SRC\mb91467d.h\r
+F30-7=- ..\..\Source\include\task.h\r
+F30-8=- ..\..\Source\include\list.h\r
+F30-9=- ..\..\Source\include\queue.h\r
+F30-10=- ..\Common\include\semtest.h\r
+F30-11=- ..\..\..\..\..\devtools\Softune6\LIB\911\INCLUDE\stdlib.h\r
+F30-12=- ..\..\..\..\..\devtools\Softune6\LIB\911\INCLUDE\stddef.h\r
+F30-13=- ..\Common\Minimal\semphr.h\r
+F31=10 c 1 ..\..\Source\portable\MemMang\heap_3.c\r
+F31-1=- ..\..\Source\include\FreeRTOS.h\r
+F31-2=- ..\..\Source\include\projdefs.h\r
+F31-3=- SRC\FreeRTOSConfig.h\r
+F31-4=- ..\..\Source\include\portable.h\r
+F31-5=- ..\..\Source\portable\Softune\MB91460\portmacro.h\r
+F31-6=- SRC\mb91467d.h\r
+F31-7=- ..\..\Source\include\task.h\r
+F31-8=- ..\..\Source\include\list.h\r
+F31-9=- ..\..\..\..\..\devtools\Softune6\LIB\911\INCLUDE\stdlib.h\r
+F31-10=- ..\..\..\..\..\devtools\Softune6\LIB\911\INCLUDE\stddef.h\r
+F32=10 c 0 ..\..\Source\portable\MemMang\heap_1.c\r
+F32-1=- ..\..\Source\include\FreeRTOS.h\r
+F32-2=- ..\..\Source\include\projdefs.h\r
+F32-3=- SRC\FreeRTOSConfig.h\r
+F32-4=- ..\..\Source\include\portable.h\r
+F32-5=- ..\..\Source\portable\Softune\MB91460\portmacro.h\r
+F32-6=- SRC\mb91467d.h\r
+F32-7=- ..\..\Source\include\task.h\r
+F32-8=- ..\..\Source\include\list.h\r
+F32-9=- ..\..\..\..\..\SoftuneV6_32bit_REV600008\LIB\911\INCLUDE\stdlib.h\r
+F32-10=- ..\..\..\..\..\SoftuneV6_32bit_REV600008\LIB\911\INCLUDE\stddef.h\r
+F33=10 c 0 ..\..\Source\portable\MemMang\heap_2.c\r
+F33-1=- ..\..\Source\include\FreeRTOS.h\r
+F33-2=- ..\..\Source\include\projdefs.h\r
+F33-3=- SRC\FreeRTOSConfig.h\r
+F33-4=- ..\..\Source\include\portable.h\r
+F33-5=- ..\..\Source\portable\Softune\MB91460\portmacro.h\r
+F33-6=- SRC\mb91467d.h\r
+F33-7=- ..\..\Source\include\task.h\r
+F33-8=- ..\..\Source\include\list.h\r
+F33-9=- ..\..\..\..\..\SoftuneV6_32bit_REV600008\LIB\911\INCLUDE\stdlib.h\r
+F33-10=- ..\..\..\..\..\SoftuneV6_32bit_REV600008\LIB\911\INCLUDE\stddef.h\r
+F34=12 c 1 SRC\serial\serial.c\r
+F34-1=- ..\..\Source\include\FreeRTOS.h\r
+F34-2=- ..\..\Source\include\projdefs.h\r
+F34-3=- SRC\FreeRTOSConfig.h\r
+F34-4=- ..\..\Source\include\portable.h\r
+F34-5=- ..\..\Source\portable\Softune\MB91460\portmacro.h\r
+F34-6=- SRC\mb91467d.h\r
+F34-7=- ..\..\Source\include\queue.h\r
+F34-8=- ..\..\Source\include\task.h\r
+F34-9=- ..\..\Source\include\list.h\r
+F34-10=- ..\Common\include\serial.h\r
+F34-11=- ..\..\..\..\..\devtools\Softune6\LIB\911\INCLUDE\stdlib.h\r
+F34-12=- ..\..\..\..\..\devtools\Softune6\LIB\911\INCLUDE\stddef.h\r
+F35=10 c 1 SRC\watchdog\watchdog.c\r
+F35-1=- SRC\mb91467d.h\r
+F35-2=- ..\..\Source\include\FreeRTOS.h\r
+F35-3=- ..\..\Source\include\projdefs.h\r
+F35-4=- SRC\FreeRTOSConfig.h\r
+F35-5=- ..\..\Source\include\portable.h\r
+F35-6=- ..\..\Source\portable\Softune\MB91460\portmacro.h\r
+F35-7=- ..\..\Source\include\task.h\r
+F35-8=- ..\..\Source\include\list.h\r
+F35-9=- SRC\watchdog\watchdog.h\r
+F35-10=- ..\..\..\..\..\devtools\Softune6\LIB\911\INCLUDE\stddef.h\r
+F36=10 c 1 SRC\utility\taskutility.c\r
+F36-1=- SRC\mb91467d.h\r
+F36-2=- SRC\vectors.h\r
+F36-3=- ..\..\Source\include\FreeRTOS.h\r
+F36-4=- ..\..\Source\include\projdefs.h\r
+F36-5=- SRC\FreeRTOSConfig.h\r
+F36-6=- ..\..\Source\include\portable.h\r
+F36-7=- ..\..\Source\portable\Softune\MB91460\portmacro.h\r
+F36-8=- ..\..\Source\include\task.h\r
+F36-9=- ..\..\Source\include\list.h\r
+F36-10=- ..\..\..\..\..\devtools\Softune6\LIB\911\INCLUDE\stddef.h\r
+\r
+[BUILDMODE-STANDALONE]\r
+kernel=1\r
+\r
+[RUNSET-STANDALONE]\r
+CONVERT=1\r
+CONVERTKIND=0\r
+\r
+[DebState-STANDALONE]\r
+SupCount=6\r
+Supfile-0=STANDALONE\Simulator.sup\r
+Supfile-1=STANDALONE\MB2198-01-USB.sup\r
+Supfile-2=STANDALONE\MB2198-01-COM1.sup\r
+Supfile-3=STANDALONE\MB2198-01-LAN.sup\r
+Supfile-4=STANDALONE\Mondeb_57K6_com1.sup\r
+Supfile-5=STANDALONE\Mondeb_57K6_com2.sup\r
+Current=Mondeb_57K6_com1.sup\r
+AliasFile=\r
+CPURunMode=\r
+\r
+[CPUTYPE-MONDEB_INTERNAL]\r
+CsvFile=Lib\911\911.csv\r
+CpuName=MB91F467D\r
+Count=0\r
+BusMode=3\r
+BusWidth=2\r
+\r
+[DirInfo-MONDEB_INTERNAL]\r
+CONFIG=MONDEB_INTERNAL\\r
+OBJ=MONDEB_INTERNAL\OBJ\\r
+LST=MONDEB_INTERNAL\LST\\r
+OPT=MONDEB_INTERNAL\OPT\\r
+\r
+[MEMBER-MONDEB_INTERNAL]\r
+F0=36\r
+F1=0 m 1 MONDEB_INTERNAL\ABS\91467d_FreeRTOS.abs\r
+F2=0 c 1 ..\..\Source\portable\Softune\MB91460\port.c\r
+F3=0 c 1 ..\..\Source\portable\Softune\MB91460\__STD_LIB_sbrk.c\r
+F4=0 c 1 ..\..\Source\croutine.c\r
+F5=0 c 1 ..\..\Source\list.c\r
+F6=0 c 1 ..\..\Source\queue.c\r
+F7=0 c 1 ..\..\Source\tasks.c\r
+F8=0 c 1 SRC\MAIN.c\r
+F9=0 c 1 SRC\vectors.c\r
+F10=0 a 1 SRC\mb91467d.asm\r
+F11=0 a 1 SRC\Start91460.asm\r
+F12=0 c 1 ..\Common\Minimal\AltBlckQ.c\r
+F13=0 c 1 ..\Common\Minimal\AltBlock.c\r
+F14=0 c 1 ..\Common\Minimal\AltPollQ.c\r
+F15=0 c 1 ..\Common\Minimal\AltQTest.c\r
+F16=0 c 1 ..\Common\Minimal\BlockQ.c\r
+F17=0 c 1 ..\Common\Minimal\blocktim.c\r
+F18=0 c 1 ..\Common\Minimal\comtest.c\r
+F19=0 c 1 ..\Common\Minimal\countsem.c\r
+F20=0 c 1 ..\Common\Minimal\crflash.c\r
+F21=0 c 1 ..\Common\Minimal\crhook.c\r
+F22=0 c 1 ..\Common\Minimal\death.c\r
+F23=0 c 1 ..\Common\Minimal\dynamic.c\r
+F24=0 c 1 ..\Common\Minimal\flash.c\r
+F25=0 c 1 ..\Common\Minimal\flop.c\r
+F26=0 c 1 ..\Common\Minimal\GenQTest.c\r
+F27=0 c 1 ..\Common\Minimal\integer.c\r
+F28=0 c 1 ..\Common\Minimal\PollQ.c\r
+F29=0 c 1 ..\Common\Minimal\QPeek.c\r
+F30=0 c 1 ..\Common\Minimal\semtest.c\r
+F31=0 c 1 ..\..\Source\portable\MemMang\heap_3.c\r
+F32=0 c 1 ..\..\Source\portable\MemMang\heap_1.c\r
+F33=0 c 1 ..\..\Source\portable\MemMang\heap_2.c\r
+F34=0 c 1 SRC\serial\serial.c\r
+F35=0 c 1 SRC\watchdog\watchdog.c\r
+F36=0 c 1 SRC\utility\taskutility.c\r
+\r
+[BUILDMODE-MONDEB_INTERNAL]\r
+kernel=1\r
+\r
+[RUNSET-MONDEB_INTERNAL]\r
+CONVERT=1\r
+CONVERTKIND=0\r
+\r
+[DebState-MONDEB_INTERNAL]\r
+SupCount=2\r
+Supfile-0=MONDEB_INTERNAL\Mondeb_57K6_com1.sup\r
+Supfile-1=MONDEB_INTERNAL\Mondeb_57K6_com2.sup\r
+Current=Mondeb_57K6_com1.sup\r
+AliasFile=\r
+CPURunMode=\r
+\r
+[AsmBefore]\r
+Count=0\r
+\r
+[AsmAfter]\r
+Count=0\r
+\r
+[CcBefore]\r
+Count=0\r
+\r
+[CcAfter]\r
+Count=0\r
+\r
+[LnkBefore]\r
+Count=0\r
+\r
+[LnkAfter]\r
+Count=0\r
+\r
+[LibBefore]\r
+Count=0\r
+\r
+[LibAfter]\r
+Count=0\r
+\r
+[CnvBefore]\r
+Count=0\r
+\r
+[CnvAfter]\r
+Count=0\r
+\r
+[ConfigBefore]\r
+Count=0\r
+\r
+[ConfigAfter]\r
+Count=0\r
+\r

diff --git a/Demo/MB91460_Softune/91467d_FreeRTOS.wsp b/Demo/MB91460_Softune/91467d_FreeRTOS.wsp
new file mode 100644 (file)
index 0000000..8350794
--- /dev/null
+++ b/Demo/MB91460_Softune/91467d_FreeRTOS.wsp
@@ -0,0 +1,23 @@
+[CPUTYPE]\r
+CpuSerise=911\r
+\r
+[PrjFile]\r
+Count=1\r
+FILE-0=91467d_FreeRTOS.prj\r
+ActivePrj=91467d_FreeRTOS.prj\r
+\r
+[SubPrj-91467d_FreeRTOS.prj]\r
+Count=0\r
+\r
+[DebState]\r
+AutoSave=1\r
+Exec=0\r
+AutoLoad=1\r
+\r
+[DirInfo]\r
+WSP=E:\FreeRTOS\FR\91467d_FreeRTOS\91467d_FreeRTOS\Demo\MB91460_Softune\\r
+\r
+[EditState]\r
+STATE-1=SRC\MAIN.c:1\r
+Count=1\r
+\r

diff --git a/Demo/MB91460_Softune/PRC/set_MONITOR.prc b/Demo/MB91460_Softune/PRC/set_MONITOR.prc
new file mode 100644 (file)
index 0000000..88927c7
--- /dev/null
+++ b/Demo/MB91460_Softune/PRC/set_MONITOR.prc
@@ -0,0 +1,53 @@
+# THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */\r
+# MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */\r
+# ELIGIBILITY FOR ANY PURPOSES.                                             */\r
+#                 (C) Fujitsu Microelectronics Europe GmbH                  */\r
+\r
+# Environment and memory manioulation after program upload\r
+\r
+\r
+# Settings\r
+SET VARIABLE abortIRQ0 = 0x1\r
+SET VARIABLE intVectorMonitorDebugger = 0x10FFC00\r
+\r
+\r
+\r
+\r
+# Disable all Interrupts\r
+SET REGISTER I = 0x0\r
+\r
+# Set Table Base Register\r
+SET REGISTER TBR = intVectorMonitorDebugger\r
+\r
+# Run to smd_tbr and save TBR of Application\r
+go ,Start91460\smd_tbr\r
+SET VARIABLE intVectorApllication  = %r0\r
+SET REGISTER TBR = intVectorApllication  \r
+\r
+# Copy required vector table entries of monitor debugger in vector table of application\r
+MOVE intVectorMonitorDebugger + 0x3C0..intVectorMonitorDebugger + 0x3FF, intVectorApllication + 0x3C0\r
+    \r
+# Prepare Entries for INT0\r
+IF %abortIRQ0 == 1\r
+  MOVE intVectorMonitorDebugger + 0x3C0..intVectorMonitorDebugger + 0x3C3, intVectorApllication + 0x3BC\r
+  SET MEMORY/BYTE 0x32 = 0x3\r
+  SET MEMORY/BYTE 0x30 = 0x0\r
+  SET MEMORY/BYTE 0x31 = 0x1\r
+  SET MEMORY/BYTE 0x440 = 0x10\r
+  SET REGISTER ILM = 0x1E\r
+ENDIF\r
+\r
+# Setting indicates software reset, which leads to that the clock settings are not changed.\r
+SET REGISTER R4 = 0x8\r
+\r
+\r
+# Set TBR to Vector table of application\r
+SET REGISTER TBR = intVectorApllication \r
+\r
+\r
+# Run to smd_c and let the CS enabled\r
+go noClockStartup,Start91460\smd_cs\r
+set register r2 = %r2|0x3\r
+\r
+# Run to main()\r
+go ,main\r

diff --git a/Demo/MB91460_Softune/PRC/set_MONITOR_INTERNAL.prc b/Demo/MB91460_Softune/PRC/set_MONITOR_INTERNAL.prc
new file mode 100644 (file)
index 0000000..480cf02
--- /dev/null
+++ b/Demo/MB91460_Softune/PRC/set_MONITOR_INTERNAL.prc
@@ -0,0 +1,56 @@
+# THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */\r
+# MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */\r
+# ELIGIBILITY FOR ANY PURPOSES.                                             */\r
+#                 (C) Fujitsu Microelectronics Europe GmbH                  */\r
+\r
+# Environment and memory manioulation after program upload\r
+\r
+\r
+# Settings\r
+\r
+SET VARIABLE abortIRQ0 = 0x1\r
+SET VARIABLE intVectorMonitorDebugger = 0xFFC00\r
+\r
+\r
+\r
+\r
+# Disable all Interrupts\r
+SET REGISTER I = 0x0\r
+\r
+# Set Table Base Register\r
+SET REGISTER TBR = intVectorMonitorDebugger\r
+\r
+\r
+# Run to smd_tbr and save TBR of Application\r
+go ,Start91460\smd_tbr\r
+SET VARIABLE intVectorApllication  = %r0\r
+SET REGISTER TBR = intVectorApllication  \r
+\r
+# Copy required vector table entries of monitor debugger in vector table of application\r
+MOVE intVectorMonitorDebugger + 0x3C0..intVectorMonitorDebugger + 0x3FF, intVectorApllication + 0x3C0\r
+    \r
+\r
+# Prepare Entries for INT0\r
+IF %abortIRQ0 == 0x1\r
+  MOVE intVectorMonitorDebugger + 0x3C0..intVectorMonitorDebugger + 0x3C3, intVectorApllication + 0x3BC\r
+  SET MEMORY/BYTE 0x32 = 0x3\r
+  SET MEMORY/BYTE 0x30 = 0x0\r
+  SET MEMORY/BYTE 0x31 = 0x1\r
+  SET MEMORY/BYTE 0x440 = 0x10\r
+  SET REGISTER ILM = 0x1E\r
+ENDIF\r
+\r
+\r
+# Setting indicates software reset, which leads to that the clock settings are not changed.\r
+SET REGISTER R4 = 0x8\r
+\r
+\r
+# Set TBR to Vector table of application\r
+SET REGISTER TBR = intVectorApllication \r
+\r
+# Run to smd_c and let the CS enabled\r
+go noClockStartup,Start91460\smd_cs\r
+set register r2 = %r2|0x2\r
+\r
+# Run to main()\r
+go ,main
\ No newline at end of file

diff --git a/Demo/MB91460_Softune/PRC/set_RESET.prc b/Demo/MB91460_Softune/PRC/set_RESET.prc
new file mode 100644 (file)
index 0000000..95972c0
--- /dev/null
+++ b/Demo/MB91460_Softune/PRC/set_RESET.prc
@@ -0,0 +1,16 @@
+# THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU\r
+# MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR\r
+# ELIGIBILITY FOR ANY PURPOSES.                                            \r
+#                 (C) Fujitsu Microelectronics Europe GmbH                 \r
+# set_ROMS.prc\r
+# ===========\r
+#\r
+# Procedurefile for the FR-Emulator - Target : MB91F467D.\r
+# Should be executed before loading any target-file into\r
+# the RAM of the emulator (use the debug settings).\r
+# The procedure checks sets the ROM Select Register to allow\r
+# the emulation of the whole ROM Area of the MB91F467D\r
+\r
+RESET\r
+\r
+SET MEMORY/HALFWORD 0x390 = 0xFF00
\ No newline at end of file

diff --git a/Demo/MB91460_Softune/PRC/set_ROMS.prc b/Demo/MB91460_Softune/PRC/set_ROMS.prc
new file mode 100644 (file)
index 0000000..6bb9ae3
--- /dev/null
+++ b/Demo/MB91460_Softune/PRC/set_ROMS.prc
@@ -0,0 +1,15 @@
+# THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU\r
+# MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR\r
+# ELIGIBILITY FOR ANY PURPOSES.                                            \r
+#                 (C) Fujitsu Microelectronics Europe GmbH                 \r
+# set_ROMS.prc\r
+# ===========\r
+#\r
+# Procedurefile for the FR-Emulator - Target : MB91F467D.\r
+# Should be executed before loading any target-file into\r
+# the RAM of the emulator (use the debug settings).\r
+# The procedure checks sets the ROM Select Register to allow\r
+# the emulation of the whole ROM Area of the MB91F467D\r
+\r
+\r
+SET MEMORY/HALFWORD 0x390 = 0xFF00\r

diff --git a/Demo/MB91460_Softune/PRC/set_SIMULATE.prc b/Demo/MB91460_Softune/PRC/set_SIMULATE.prc
new file mode 100644 (file)
index 0000000..fe0c271
--- /dev/null
+++ b/Demo/MB91460_Softune/PRC/set_SIMULATE.prc
@@ -0,0 +1,13 @@
+# THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */\r
+# MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */\r
+# ELIGIBILITY FOR ANY PURPOSES.                                             */\r
+#                 (C) Fujitsu Microelectronics Europe GmbH                  */\r
+\r
+# Environment and memory manioulation after program upload\r
+\r
+\r
+\r
+\r
+print "patch reset vector to \"__start\"\n";\r
+SET MEMORY/WORD 0xFFFFC=__start\r
+  \r

diff --git a/Demo/MB91460_Softune/SRC/FreeRTOSConfig.h b/Demo/MB91460_Softune/SRC/FreeRTOSConfig.h
new file mode 100644 (file)
index 0000000..c6fa576
--- /dev/null
+++ b/Demo/MB91460_Softune/SRC/FreeRTOSConfig.h
@@ -0,0 +1,81 @@
+/*\r
+       FreeRTOS.org V4.4.0 - Copyright (C) 2003-2007 Richard Barry.\r
+\r
+       This file is part of the FreeRTOS.org distribution.\r
+\r
+       FreeRTOS.org is free software; you can redistribute it and/or modify\r
+       it under the terms of the GNU General Public License as published by\r
+       the Free Software Foundation; either version 2 of the License, or\r
+       (at your option) any later version.\r
+\r
+       FreeRTOS.org is distributed in the hope that it will be useful,\r
+       but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+       MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\r
+       GNU General Public License for more details.\r
+\r
+       You should have received a copy of the GNU General Public License\r
+       along with FreeRTOS.org; if not, write to the Free Software\r
+       Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA\r
+\r
+       A special exception to the GPL can be applied should you wish to distribute\r
+       a combined work that includes FreeRTOS.org, without being obliged to provide\r
+       the source code for any proprietary components.  See the licensing section \r
+       of http://www.FreeRTOS.org for full details of how and when the exception\r
+       can be applied.\r
+\r
+       ***************************************************************************\r
+       See http://www.FreeRTOS.org for documentation, latest information, license \r
+       and contact details.  Please ensure to read the configuration and relevant \r
+       port sections of the online documentation.\r
+\r
+       Also see http://www.SafeRTOS.com for an IEC 61508 compliant version along\r
+       with commercial development and support options.\r
+       ***************************************************************************\r
+*/\r
+\r
+#ifndef FREERTOS_CONFIG_H\r
+#define FREERTOS_CONFIG_H\r
+\r
+/*-----------------------------------------------------------\r
+ * Application specific definitions.\r
+ *\r
+ * These definitions should be adjusted for your particular hardware and\r
+ * application requirements.\r
+ *\r
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\r
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. \r
+ *----------------------------------------------------------*/\r
+\r
+#define configUSE_PREEMPTION           1\r
+#define configUSE_IDLE_HOOK                    1\r
+#define configUSE_TICK_HOOK                    1\r
+#define configTICK_RATE_HZ                     ( ( portTickType ) 100 )\r
+#define configCPU_CLOCK_HZ                     ( ( unsigned portLONG ) 64000000 )  /* Clock setup from start91460.asm in the demo application. */\r
+#define configPER_CLOCK_HZ                     ( ( unsigned portLONG ) 16000000 )  /* Clock setup from start91460.asm in the demo application. */\r
+#define configMAX_PRIORITIES           ( ( unsigned portBASE_TYPE ) 6 )\r
+#define configMINIMAL_STACK_SIZE       ( ( unsigned portSHORT ) 70 )\r
+#define configTOTAL_HEAP_SIZE          ( ( size_t ) ( 32768 - 4192 ) )\r
+#define configMAX_TASK_NAME_LEN                ( 20 )\r
+#define configUSE_TRACE_FACILITY       1\r
+#define configUSE_16_BIT_TICKS         0\r
+#define configIDLE_SHOULD_YIELD                1\r
+#define configUSE_MUTEXES           1\r
+\r
+/* Co-routine definitions. */\r
+#define configUSE_CO_ROUTINES          1\r
+#define configMAX_CO_ROUTINE_PRIORITIES ( 4 )\r
+\r
+\r
+/* Set the following definitions to 1 to include the API function, or zero\r
+to exclude the API function. */\r
+\r
+#define INCLUDE_vTaskPrioritySet               1\r
+#define INCLUDE_uxTaskPriorityGet              1\r
+#define INCLUDE_vTaskDelete                            1\r
+#define INCLUDE_vTaskCleanUpResources  0\r
+#define INCLUDE_vTaskSuspend                   1\r
+#define INCLUDE_vTaskDelayUntil                        1\r
+#define INCLUDE_vTaskDelay                             1\r
+#define INCLUDE_vResumeFromISR          1\r
+\r
+#endif /* FREERTOS_CONFIG_H */\r

diff --git a/Demo/MB91460_Softune/SRC/MAIN.c b/Demo/MB91460_Softune/SRC/MAIN.c
new file mode 100644 (file)
index 0000000..dbb48e2
--- /dev/null
+++ b/Demo/MB91460_Softune/SRC/MAIN.c
@@ -0,0 +1,372 @@
+/* THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */\r
+/* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */\r
+/* ELIGIBILITY FOR ANY PURPOSES.                                             */\r
+/*                 (C) Fujitsu Microelectronics Europe GmbH                  */\r
+/*------------------------------------------------------------------------\r
+  MAIN.C\r
+  - description\r
+  - See README.TXT for project description and disclaimer.\r
+-------------------------------------------------------------------------*/\r
+/*************************@INCLUDE_START************************/\r
+#include "mb91467d.h"\r
+#include "vectors.h"\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "watchdog.h"\r
+\r
+/* Demo task priorities. */\r
+#define WTC_TASK_PRIORITY                              ( tskIDLE_PRIORITY + 5 )\r
+#define mainCHECK_TASK_PRIORITY                        ( tskIDLE_PRIORITY + 4 )\r
+#define TASK_UTILITY_PRIORITY                  ( tskIDLE_PRIORITY + 3 )\r
+#define mainSEM_TEST_PRIORITY                  ( tskIDLE_PRIORITY + 3 )\r
+#define mainCOM_TEST_PRIORITY                  ( tskIDLE_PRIORITY + 2 )\r
+#define mainQUEUE_POLL_PRIORITY                        ( tskIDLE_PRIORITY + 2 )\r
+#define mainQUEUE_BLOCK_PRIORITY               ( tskIDLE_PRIORITY + 2 )\r
+#define mainDEATH_PRIORITY                             ( tskIDLE_PRIORITY + 1 )\r
+#define mainLED_TASK_PRIORITY                  ( tskIDLE_PRIORITY + 1 )\r
+#define mainGENERIC_QUEUE_PRIORITY             ( tskIDLE_PRIORITY )\r
+\r
+/* Baud rate used by the COM test tasks. */\r
+#define mainCOM_TEST_BAUD_RATE                 ( ( unsigned portLONG ) 19200 )\r
+\r
+/* The frequency at which the 'Check' tasks executes.  See the comments at the \r
+top of the page.  When the system is operating error free the 'Check' task\r
+toggles an LED every three seconds.  If an error is discovered in any task the\r
+rate is increased to 500 milliseconds.  [in this case the '*' characters on the \r
+LCD represent LED's]*/\r
+#define mainNO_ERROR_CHECK_DELAY               ( ( portTickType ) 3000 / portTICK_RATE_MS  )\r
+#define mainERROR_CHECK_DELAY                  ( ( portTickType ) 500 / portTICK_RATE_MS  )\r
+\r
+/*---------------------------------------------------------------------------*/\r
+#define ledNUMBER_OF_LEDS              8\r
+#define mainCOM_TEST_LED               0x05\r
+#define mainCHECK_TEST_LED             0x07\r
+/*---------------------------------------------------------------------------*/\r
+/* \r
+ * The function that implements the Check task.  See the comments at the head\r
+ * of the page for implementation details.\r
+ */ \r
+static void vErrorChecks( void *pvParameters );\r
+\r
+/*\r
+ * Called by the Check task.  Returns pdPASS if all the other tasks are found\r
+ * to be operating without error - otherwise returns pdFAIL.\r
+ */\r
+static portSHORT prvCheckOtherTasksAreStillRunning( void );\r
+\r
+/*---------------------------------------------------------------------------*/\r
+\r
+static unsigned portSHORT sState[ledNUMBER_OF_LEDS] = {pdFALSE};\r
+static unsigned portSHORT sState1[ledNUMBER_OF_LEDS] = {pdFALSE};\r
+\r
+/*---------------------------------------------------------------------------\r
+ * The below callback function is called from Tick ISR if configUSE_TICK_HOOK \r
+ * is configured as 1. This function needs to be uncommented if the crhook.c\r
+ * is not used, since the crhook.c has also defined vApplicationTickHook(). \r
+ *---------------------------------------------------------------------------*/  \r
+/*void vApplicationTickHook ( void )\r
+{\r
+#if WATCHDOG == WTC_IN_TICK\r
+       Kick_Watchdog();\r
+#endif\r
+}*/\r
+/*---------------------------------------------------------------------------\r
+ * The below callback function is called from Delayed ISR if configUSE_IDLE_HOOK \r
+ * is configured as 1.\r
+ *---------------------------------------------------------------------------*/  \r
+void vApplicationIdleHook ( void )\r
+{\r
+#if WATCHDOG == WTC_IN_IDLE\r
+       Kick_Watchdog();\r
+#endif\r
+       \r
+       vCoRoutineSchedule();\r
+}\r
+\r
+/*---------------------------------------------------------------------------\r
+ * Initialize Port 00\r
+ *---------------------------------------------------------------------------*/\r
+static void prvInitPort( void )\r
+{\r
+       DDR16=0xFF;\r
+    DDR25=0xFF;\r
+}\r
+/*---------------------------------------------------------------------------\r
+ * Setup the hardware\r
+ *---------------------------------------------------------------------------*/\r
+static void prvSetupHardware( void )\r
+{\r
+       prvInitPort();\r
+#if WATCHDOG != WTC_NONE       \r
+       InitWatchdog();\r
+#endif\r
+}\r
+\r
+\r
+/*********************@FUNCTION_HEADER_START*********************\r
+*@FUNCTION NAME:    main()                                      *\r
+*                                                               *\r
+*@DESCRIPTION:      The main function controls the program flow *\r
+*                                                               *\r
+*@PARAMETER:        none                                        *\r
+*                                                               *\r
+*@RETURN:           none                                        *\r
+*                                                               *\r
+***********************@FUNCTION_HEADER_END*********************/\r
+\r
+void main(void)\r
+{\r
+       __set_il(31);       /* allow all levels */\r
+       InitIrqLevels();    /* init interrupts */\r
+       \r
+       prvSetupHardware();\r
+       \r
+#if WATCHDOG == WTC_IN_TASK    \r
+       vStartWatchdogTask( WTC_TASK_PRIORITY );\r
+#endif         \r
+\r
+       /* Start the standard demo application tasks. */\r
+       vStartLEDFlashTasks( mainLED_TASK_PRIORITY );\r
+       \r
+       vStartIntegerMathTasks( tskIDLE_PRIORITY );\r
+\r
+       vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED - 1 );\r
+\r
+       vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );\r
+\r
+       vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );\r
+\r
+       vStartBlockingQueueTasks ( mainQUEUE_BLOCK_PRIORITY );\r
+       \r
+       vStartDynamicPriorityTasks();\r
+       \r
+       vStartMathTasks( tskIDLE_PRIORITY );\r
+       \r
+       vStartFlashCoRoutines(ledNUMBER_OF_LEDS);\r
+       \r
+       vStartHookCoRoutines();\r
+       \r
+       /* Start the 'Check' task which is defined in this file. */\r
+       xTaskCreate( vErrorChecks, ( signed portCHAR * ) "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );      \r
+\r
+       vStartGenericQueueTasks( mainGENERIC_QUEUE_PRIORITY );\r
+       \r
+       vStartQueuePeekTasks();\r
+       \r
+       vTraceListTasks( TASK_UTILITY_PRIORITY );\r
+       \r
+       vCreateBlockTimeTasks();\r
+       \r
+       vCreateSuicidalTasks( mainDEATH_PRIORITY );\r
+       \r
+       vTaskStartScheduler( );\r
+       \r
+       /* Should not reach here */\r
+       while (1)\r
+       {\r
+               __asm(" NOP "); // \r
+       }\r
+}\r
+\r
+/*-----------------------------------------------------------*/\r
+void vParTestToggleLED( unsigned portBASE_TYPE uxLED )\r
+{\r
+       if (uxLED < ledNUMBER_OF_LEDS)\r
+       {\r
+               vTaskSuspendAll();\r
+               \r
+               /* Toggle the state of the single genuine on board LED. */\r
+               if( sState[uxLED])      \r
+               {\r
+                       PDR25 |= (1 << uxLED);\r
+               }\r
+               else\r
+               {\r
+                       PDR25 &= ~(1 << uxLED);\r
+               }\r
+       \r
+               sState[uxLED] = !(sState[uxLED]);\r
+               \r
+               xTaskResumeAll();\r
+       }\r
+       else\r
+       {\r
+               uxLED -= ledNUMBER_OF_LEDS;\r
+               \r
+               vTaskSuspendAll();\r
+               \r
+               /* Toggle the state of the single genuine on board LED. */\r
+               if( sState1[uxLED])     \r
+               {\r
+                       PDR16 |= (1 << uxLED);\r
+               }\r
+               else\r
+               {\r
+                       PDR16 &= ~(1 << uxLED);\r
+               }\r
+       \r
+               sState1[uxLED] = !(sState1[uxLED]);\r
+               \r
+               xTaskResumeAll();\r
+       }\r
+}\r
+/*-----------------------------------------------------------*/\r
+void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue )\r
+{\r
+       /* Set or clear the output [in this case show or hide the '*' character. */\r
+       if( uxLED < ledNUMBER_OF_LEDS )\r
+       {\r
+               vTaskSuspendAll();\r
+               {\r
+                       if( xValue )\r
+                       {\r
+                               PDR25 |= (1 << uxLED);\r
+                               sState[uxLED] = 1;\r
+                       }\r
+                       else\r
+                       {\r
+                               PDR25 &= ~(1 << uxLED);\r
+                               sState[uxLED] = 0;\r
+                       }\r
+               }\r
+               xTaskResumeAll();\r
+       }\r
+       else \r
+       {\r
+               uxLED -= ledNUMBER_OF_LEDS;\r
+               vTaskSuspendAll();\r
+               {\r
+                       if( xValue )\r
+                       {\r
+                               PDR16 |= (1 << uxLED);\r
+                               sState1[uxLED] = 1;\r
+                       }\r
+                       else\r
+                       {\r
+                               PDR16 &= ~(1 << uxLED);\r
+                               sState1[uxLED] = 0;\r
+                       }\r
+               }\r
+               xTaskResumeAll();\r
+       }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void vErrorChecks( void *pvParameters )\r
+{\r
+static volatile unsigned portLONG ulDummyVariable = 3UL;\r
+portTickType xDelayPeriod = mainNO_ERROR_CHECK_DELAY;\r
+\r
+       /* Cycle for ever, delaying then checking all the other tasks are still\r
+       operating without error. */\r
+       for( ;; )\r
+       {\r
+               /* Wait until it is time to check again.  The time we wait here depends\r
+               on whether an error has been detected or not.  When an error is \r
+               detected the time is shortened resulting in a faster LED flash rate. */\r
+               vTaskDelay( xDelayPeriod );\r
+\r
+               /* Perform a bit of 32bit maths to ensure the registers used by the \r
+               integer tasks get some exercise outside of the integer tasks \r
+               themselves. The result here is not important we are just deliberately\r
+               changing registers used by other tasks to ensure that their context\r
+               switch is operating as required. - see the demo application \r
+               documentation for more info. */\r
+               ulDummyVariable *= 3UL;\r
+               \r
+               /* See if the other tasks are all ok. */\r
+               if( prvCheckOtherTasksAreStillRunning() != pdPASS )\r
+               {\r
+                       /* An error occurred in one of the tasks so shorten the delay \r
+                       period - which has the effect of increasing the frequency of the\r
+                       LED toggle. */\r
+                       xDelayPeriod = mainERROR_CHECK_DELAY;\r
+               }\r
+\r
+               /* Flash! */\r
+               vParTestToggleLED(mainCHECK_TEST_LED);\r
+       }\r
+}\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+static portSHORT prvCheckOtherTasksAreStillRunning( void )\r
+{\r
+static portSHORT sNoErrorFound = pdTRUE;\r
+\r
+       /* The demo tasks maintain a count that increments every cycle of the task\r
+       provided that the task has never encountered an error.  This function \r
+       checks the counts maintained by the tasks to ensure they are still being\r
+       incremented.  A count remaining at the same value between calls therefore\r
+       indicates that an error has been detected.  Only tasks that do not flash\r
+       an LED are checked. */\r
+\r
+       if( xAreIntegerMathsTaskStillRunning() != pdTRUE )\r
+       {\r
+               sNoErrorFound = pdFALSE;\r
+       }\r
+\r
+       if( xArePollingQueuesStillRunning() != pdTRUE )\r
+       {\r
+               sNoErrorFound = pdFALSE;\r
+       }\r
+\r
+       if( xAreComTestTasksStillRunning() != pdTRUE )\r
+       {\r
+               sNoErrorFound = pdFALSE;\r
+       }\r
+       \r
+       if( xAreSemaphoreTasksStillRunning() != pdTRUE )\r
+       {\r
+               sNoErrorFound = pdFALSE;\r
+       }\r
+       \r
+       if( xAreBlockingQueuesStillRunning() != pdTRUE )\r
+       {\r
+               sNoErrorFound = pdFALSE;\r
+       }\r
+       \r
+       if( xAreDynamicPriorityTasksStillRunning() != pdTRUE )\r
+       {\r
+               sNoErrorFound = pdFALSE;\r
+       }\r
+       \r
+       if( xAreMathsTaskStillRunning() != pdTRUE )\r
+       {\r
+               sNoErrorFound = pdFALSE;\r
+       }\r
+       \r
+       if( xAreFlashCoRoutinesStillRunning() != pdTRUE ) \r
+       {\r
+               sNoErrorFound = pdFALSE;\r
+       }\r
+       \r
+       if( xAreHookCoRoutinesStillRunning() != pdTRUE )\r
+       {\r
+               sNoErrorFound = pdFALSE;\r
+       }\r
+       \r
+       if( xIsCreateTaskStillRunning() != pdTRUE )\r
+    {\r
+       sNoErrorFound = pdFALSE;\r
+    }\r
+       \r
+       if( xAreBlockTimeTestTasksStillRunning() != pdTRUE )\r
+       {\r
+               sNoErrorFound = pdFALSE;\r
+    }\r
+    \r
+    if ( xAreGenericQueueTasksStillRunning() != pdTRUE )\r
+    {\r
+       sNoErrorFound = pdFALSE;\r
+    }\r
+    \r
+    if ( xAreQueuePeekTasksStillRunning() != pdTRUE )\r
+    {\r
+       sNoErrorFound = pdFALSE;\r
+    }\r
+    \r
+       return sNoErrorFound;\r
+}\r
+\r
+/********************@FUNCTION_DECLARATION_END******************/\r

diff --git a/Demo/MB91460_Softune/SRC/Start91460.asm b/Demo/MB91460_Softune/SRC/Start91460.asm
new file mode 100644 (file)
index 0000000..bf5de40
--- /dev/null
+++ b/Demo/MB91460_Softune/SRC/Start91460.asm
@@ -0,0 +1,2533 @@
+/*      THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU       */\r
+/*      MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR       */\r
+/*      ELIGIBILITY FOR ANY PURPOSES.                                                   */\r
+/*      (C) 2007,2008 Fujitsu Microelectronics Europe GmbH                              */\r
+;=========================================================================================\r
+; 1  Contents\r
+;=========================================================================================\r
+; 1       Contents\r
+; 2       Disclaimer\r
+;\r
+; 3       History\r
+;\r
+; 4       Settings\r
+; 4.1     Controller device\r
+; 4.2     Boot / flash security \r
+; 4.3     Stack type and stack size\r
+; 4.4     Copy code from flash to I-RAM\r
+; 4.5     C++ start-up \r
+; 4.6     Low-level library interface\r
+; 4.7     Clock Configuration\r
+; 4.7.1   Clock selection\r
+; 4.7.2   Select Clock Modulator\r
+; 4.8     External bus interface\r
+; 4.8.1   Select chipselect \r
+; 4.8.2   Set memory addressing for chipselects\r
+; 4.8.3   Configure chipselect area\r
+; 4.8.4   Set wait cycles for chipselects\r
+; 4.8.5   Configure chipselects SDRAM memory only \r
+; 4.8.6   Referesh control register RCR \r
+; 4.8.7   Terminal and timing control register\r
+; 4.8.8   Enable / disable I-cache\r
+; 4.8.9   Enable CACHE for chipselect\r
+; 4.8.10  Select external bus mode (data lines)\r
+; 4.8.11  Select external bus mode (address lines)\r
+; 4.8.12  Select external bus mode (control signals)\r
+;\r
+; 5       Definitions of Configurations\r
+;\r
+; 6       Section and data declaration\r
+; 6.1     Define stack size\r
+; 6.2     Define sections\r
+;\r
+; 7.      S T A R T \r
+; 7.1     Initialise stack pointer and table base register\r
+; 7.2     Check for CSV reset and set CSV\r
+; 7.3     Check clock condition\r
+; 7.4     Restore default settings after reset\r
+; 7.4.1   Disable clock modulator\r
+; 7.4.2   Check if running on sub clock, change to main clock\r
+; 7.4.3   Disable sub clock\r
+; 7.4.4   Check if running on PLL, gear down PLL\r
+; 7.4.5   Disable PLL\r
+; 7.4.6   Set to main clock\r
+; 7.5     Set memory controller\r
+; 7.6     Clock startup\r
+; 7.6.1   Set Voltage Regulator Settings\r
+; 7.6.2   Power on clock modulator - clock modulator part I\r
+; 7.6.3   Set CLKR register w/o clock mode\r
+; 7.6.4   Start PLLs \r
+; 7.6.5   Wait for PLL oscillation stabilisation\r
+; 7.6.6   Set clocks \r
+; 7.6.6.1 Set CPU and peripheral clock\r
+; 7.6.6.2 Set external bus interface clock\r
+; 7.6.6.3 Set CAN clock prescaler\r
+; 7.6.6.4 Switch main clock mode\r
+; 7.6.6.5 Switch sub clock mode\r
+; 7.6.6.6 Switch to PLL mode\r
+; 7.6.7   Enable frequncy modulation - clock modulator part II\r
+; 7.7     Set BusInterface\r
+; 7.7.1   Disable all CS\r
+; 7.7.2   Clear TCR register\r
+; 7.7.3   Set CS0 \r
+; 7.7.4   Set CS1 \r
+; 7.7.5   Set CS2  \r
+; 7.7.6   Set CS3\r
+; 7.7.7   Set CS4\r
+; 7.7.8   Set CS5 \r
+; 7.7.9   Set CS6\r
+; 7.7.10  Set CS7  \r
+; 7.7.11  Set special SDRAM config register  \r
+; 7.7.12  set Port function register\r
+; 7.7.13  Set TCR register\r
+; 7.7.14  Enable cache for selected CS\r
+; 7.7.15  Set SDRAM referesh control register\r
+; 7.7.16  Enable used CS\r
+; 7.7.17  I-cache on/off\r
+; 7.7.18  Set port function register to general as I/O-port\r
+; 7.8     Copy code from flash to I-RAM\r
+; 7.9     Fill stacks\r
+; 7.10    Clear data \r
+; 7.11    Copy Init section from ROM to RAM\r
+; 7.12    C library initialization\r
+; 7.13    Call C++ constructors\r
+; 7.14    Call main routine\r
+; 7.15    Return from main function\r
+;\r
+;=========================================================================================\r
+; 2  Disclaimer\r
+;=========================================================================================\r
+;                    Fujitsu Microelectronics Europe GmbH                       \r
+;                http://emea.fujitsu.com/microelectronics \r
+;                                                              \r
+;    The  following  software  is for  demonstration  purposes only. It  is not fully  \r
+;    tested, nor  validated  in order to fullfill its task under  all  circumstances.  \r
+;    Therefore,  this software or  any part of it must only  be used in an evaluation \r
+;    laboratory environment.                        \r
+;    This  software  is  subject to  the  rules of  our  standard DISCLAIMER, that is\r
+;    delivered with our  SW-tools on  the  Fujitsu  Microcontrollers  CD/DVD (V3.4 or \r
+;    higher "\START.HTM") or on our Internet Pages:                                   \r
+;    http://www.fme.gsdc.de/gsdc.htm\r
+;    http://emea.fujitsu.com/microelectronics \r
+;\r
+;=========================================================================================\r
+; 3  History\r
+;=========================================================================================\r
+;\r
+;=========================================================================================\r
+;       MB914xx (FR60 CORE ONLY) Series C Compiler's \r
+;\r
+;       Startup file for memory and basic controller initialisation\r
+;=========================================================================================\r
+;History:\r
+;\r
+; 2005-04-18 V1.0 UMa  Release first version\r
+; 2005-06-17 V1.1 UMa  Added bus interface, modified c++ startup\r
+; 2005-06-28 V1.2 UMa  minor changes\r
+; 2005-07-27 V1.3 UMa  default values changed\r
+; 2005-10-04 V1.4 UMa  changed code 'Call main Routine'\r
+;                      Added secutiy section for MB91F467D  \r
+;                      Added Flash Access Read Timing setting section;\r
+; 2005-10-04 V1.5 UMa  Added Flash Controller Section\r
+; 2005-10-28 V1.6 UMa  Check for CSV reset\r
+; 2005-11.16 V1.7 UMa  Monitor Debugger support added: Copy of intvect Table\r
+;                      Ext. Int 0 as abort function\r
+;                      Changed PLL-Startup, Reset HWWD added\r
+; 2005-11-16 V1.7 UMa  Examples for MUL_G changed\r
+; 2006-02-14 V1.8 UMa  mb91464a added\r
+;                      Settings for Clock Spervisor added\r
+;                      Name of Section SECURITY changed to SECURITY_VECTORS\r
+;                      Example values for gear-up changed\r
+; 2006-03-17 V1.9 UMa  Changed Startup for Monitor Debugger\r
+; 2006-04-24 v2.0 UMa  Added MB91465K and MB91469G\r
+; 2006-05-03 v2.1 UMa  Added MB91461R; removed MB91V460A\r
+;                      Added settings for the external bus-interface\r
+; 2006-07-28 v2.2 UMa  Added I-RAM copy function (ROM -> IRAM)\r
+;                      Added default settings for FLASH Access Read Timing \r
+;                      Settings \r
+;                      Changed default settings for FLASH cache configuration \r
+;                      Register\r
+;                      Changed check for clock startup\r
+; 2006-08-16 v2.3 MVo  Corrected Boot Security Sector Addresses for MB91469G\r
+; 2006-10-06 v2.4 UMa  Added new devices\r
+;                      Corrected typo in I_RAM to flash copy function\r
+;                      Changed default settings for flash cache configuration\r
+;                      Changed comments for SDRAM bus interface configuration\r
+;                      Changed comments and default setting of CAN Prescaler\r
+;                      Added Stack filler\r
+;                      Added Settings for REGSEL Register\r
+; 2007-02-13 v2.5 UMa  Introduction of default configurations\r
+;                      Changed I_RAM to flash copy function                    \r
+;\r
+;\r
+;=========================================================================================\r
+; 4  Settings\r
+;=========================================================================================\r
+;\r
+; CHECK ALL OPTIONS WHETHER THEY FIT TO THE APPLICATION;\r
+;\r
+; Configure this startup file in the "Settings" section. Search for\r
+; comments with leading "; <<<". This points to the items to be set.\r
+;=========================================================================================\r
+;\r
+#set    OFF             0\r
+#set    ON              1\r
+#set    DEFAULT         2\r
+#set    LOW_PRIOR       31\r
+;\r
+;=========================================================================================\r
+; 4.1  Controller Device\r
+;=========================================================================================\r
+#set    MB91464A        2                       ; MB91460 series\r
+;\r
+#set    MB91467B       10                       ; MB91460 series\r
+;\r
+#set    MB91467C       11                       ; MB91460 series\r
+;\r
+#set    MB91467D        4                       ; MB91460 series\r
+;\r
+#set    MB91469G        6                       ; MB91460 series\r
+;\r
+#set    MB91465K        3                       ; MB91460 series\r
+;\r
+#set    MB91463N        8                       ; MB91460 series\r
+;\r
+#set    MB91461R        1                       ; MB91460 series\r
+#set    MB91467R        5                       ; MB91460 series\r
+;\r
+#set    MB91465X        9                       ; MB91460 series\r
+;\r
+#set    others          7                       ; MB91460 series\r
+;\r
+;\r
+;\r
+#set    DEVICE          MB91467D                ; <<< select device\r
+;\r
+;=========================================================================================\r
+; 4.2  Boot / Flash Security \r
+;=========================================================================================\r
+;\r
+#set    BOOT_FLASH_SEC  OFF                     ; <<< BOOT and Flash Security Vector    \r
+;\r
+; The flash devices have two flash and two boot security vectors.  It is important to set\r
+; the four vectors correctly.  Otherwise it might be possible,  that the flash device is \r
+; not accessible any more via the bootrom. Please read carefully the hardware manual.\r
+; \r
+; OFF:  The security feature is switch off. The section SECURITY_VECTORS is reserved and\r
+;       the vectors are set.\r
+; ON:   IMPORTANT! The  security vectors are  not set. But the  section SECURITY_VECTORS \r
+;       is reserved.  \r
+;\r
+; Note: This feature is not supported by every device. Please check the data sheet. This \r
+;       feature is not available on MB91461R.\r
+;\r
+;=========================================================================================\r
+; 4.3  Stack Type and Stack Size\r
+;=========================================================================================\r
+;\r
+#set    USRSTACK        0                       ; user stack:   for main program\r
+#set    SYSSTACK        1                       ; system stack: for main program and \r
+;                                               ;               interrupts\r
+;\r
+;\r
+#set    STACKUSE        SYSSTACK                ; <<< set active stack\r
+;\r
+#set    STACK_RESERVE   ON                      ; <<< reserve stack area in \r
+;                                               ;     this module\r
+#set    STACK_SYS_SIZE  2000                   ; <<< byte size of System stack\r
+#set    STACK_USR_SIZE  4                       ; <<< byte size of User stack \r
+;\r
+#set    STACK_FILL      ON                     ; <<< fills the stack area with pattern\r
+#set    STACK_PATTERN   0x55AA55AA              ; <<< the pattern to write to stack\r
+;\r
+; - If the active stack is set to SYSSTACK,  it is used for main program and interrupts. \r
+;   In this case,  the user stack  could be set to a dummy size.  If the active stack is \r
+;   set  to  user  stack,  it is  used  for the  main  program  but the  system stack is \r
+;   automatically activated,  if an interrupt is serviced.  Both stack areas must have a \r
+;   reasonable size.\r
+; - If STACK_RESERVE is ON,  the sections USTACK and SSTACK are reserved in this module. \r
+;   Otherwise, they have to be reserved in other modules.  If STACK_RESERVE is OFF,  the \r
+;   size definitions STACK_SYS_SIZE and STACK_USR_SIZE have no meaning.\r
+; - Even if  they  are reverved  in other modules,  they are  still initialised  in this \r
+;   start-up file.\r
+;\r
+; Note: Several library functions require quite a big stack (due to ANSI). \r
+;       Check the stack information files (*.stk) in the LIB\911 directory.\r
+;\r
+;=========================================================================================\r
+; 4.4  Copy code from Flash to I-RAM\r
+;=========================================================================================\r
+;\r
+#set    I_RAM           OFF                     ; <<< select  if  code  in  section IRAM\r
+;                                                     should be copied\r
+;\r
+; If this option is activated code located in the  section IRAM is copied during startup \r
+; from ROM to the instruction-RAM. The code is linked for the instruction-RAM.\r
+;\r
+;=========================================================================================\r
+; 4.5  Low-Level Library Interface\r
+;=========================================================================================\r
+;\r
+#set    CLIBINIT        OFF                     ; <<< select ext. libray usage\r
+;\r
+; This option has only to be set,  if  stream-IO/standard-IO function  of the C-libraray \r
+; have to be used (printf(), fopen()...).  This also requires  low-level functions to be \r
+; defined by the application software.\r
+; For other library functions like (e.g. sprintf()) all this is not necessary.  However, \r
+; several functions consume a large amount of stack.\r
+;\r
+;=========================================================================================\r
+; 4.6  C++ start-up \r
+;=========================================================================================\r
+;\r
+#set    CPLUSPLUS       OFF                     ; <<< activate if c++ files are used\r
+;\r
+; In the  C++ specifications,  when external  or static objects are used,  a constructor \r
+; must be called followed by  the main function.  Because four-byte pointers to the main \r
+; function are stored in the EXT_CTOR_DTOR section, call a constructor sequentially from\r
+; the  lower  address  of  the four  addresses  in that  section.  If using C++ sources, \r
+; activate this function to create the section EXT_CTOR_DTOR. \r
+;\r
+;=========================================================================================\r
+; 4.7  Clock Configuration\r
+;=========================================================================================\r
+;=========================================================================================\r
+; 4.7.1  Clock Selection\r
+;=========================================================================================\r
+;\r
+; No clock settings\r
+#set    NO_CLOCK                                               0x01\r
+;\r
+; Sub-oscillation input: 32 kHz \r
+#set    SUB_32KHZ_CPU__32KHZ_PER_32KHZ_EXT_32KHZ_CAN__2MHZ     0x11\r
+;\r
+; Oscillation input: 4 MHz \r
+#set    MAIN_4MHZ_CPU___2MHZ_PER__1MHZ_EXT__1MHZ_CAN__2MHZ     0x21\r
+#set    PLL_4MHZ__CPU__48MHZ_PER_16MHZ_EXT_24MHZ_CAN_16MHZ     0x22\r
+#set    PLL_4MHZ__CPU__64MHZ_PER_16MHZ_EXT_32MHZ_CAN_16MHZ     0x23\r
+#set    PLL_4MHZ__CPU__80MHZ_PER_20MHZ_EXT_27MHZ_CAN_20MHZ     0x24\r
+#set    PLL_4MHZ__CPU__80MHZ_PER_20MHZ_EXT_40MHZ_CAN_20MHZ     0x25\r
+#set    PLL_4MHZ__CPU__96MHZ_PER_16MHZ_EXT_48MHZ_CAN_16MHZ     0x26  ;not MB91V460, ...\r
+#set    PLL_4MHZ__CPU_100MHZ_PER_20MHZ_EXT_50MHZ_CAN_20MHZ     0x27  ;not MB91V460, ...\r
+;\r
+; MB91461R only: Oscillation input: 10 MHz\r
+#set    PLL_10MHZ_CPU__60MHZ_PER_20MHZ_EXT_30MHZ_CAN_20MHZ     0x41\r
+;\r
+; MB91461R only: Oscillation input: 20 MHz\r
+#set    PLL_20MHZ_CPU__60MHZ_PER_20MHZ_EXT_30MHZ_CAN_20MHZ     0x51\r
+;\r
+; User settings\r
+#set    CLOCK_USER                                             0x61\r
+;\r
+;\r
+;\r
+#set    CLOCKSPEED      PLL_4MHZ__CPU__64MHZ_PER_16MHZ_EXT_32MHZ_CAN_16MHZ\r
+;                                               ; <<< Select clock configuration \r
+;\r
+; There are different default configurations available, where all necessary settings for \r
+; clocks and the related  registers are made.  Beside this configurations,  there is the\r
+; possibility   to  define  a  user   configuration   in  the  chapter   "Definition  of \r
+; Configurations"\r
+; \r
+; - NO_CLOCK means: \r
+;   The clock registers are not set by the start-up file.\r
+;\r
+; - PLL_4MHZ__CPU__64MHZ_PER_16MHZ_EXT_32MHZ_CAN_16MHZ means:\r
+;   Main oszillation        =  4 MHz, PLL is activated\r
+;   CPU clock (CLKB)        = 64 MHZ\r
+;   Peripheral clock (CLKP) = 16 MHZ\r
+;   Ext. bus clock (CLKT)   = 32 MHZ\r
+;   CAN clock (CLKCAN)      = 16 MHz, using PLLx \r
+;\r
+; - CLOCK_USER: \r
+;   The user configuration definded in the chapter "Definition of Configurations" is set.\r
+;\r
+; Note: Not all  frequencies  are supported  by every device.  Please see  the  hardware \r
+;       manual.\r
+;\r
+;=========================================================================================\r
+; 4.7.2  Select Clock Modulator  \r
+;=========================================================================================\r
+;\r
+#set    CLOMO           OFF                     ; <<< Enable /disable clock modulator      \r
+;\r
+#set    CMPR            0x026F                  ; <<< Ref. to the data sheet, CMPR\r
+; \r
+; Please  refer  to the data sheet  of the device  if you  enable clock modulation.  The \r
+; register CMPR dependant on the PLL-Clock.\r
+;\r
+; Note: If the CLKCAN source is set either to main oscillator or to PLL  output then the\r
+;       clock  for  the CAN  is not influenced by  the clock  modulation.  If the CLKCAN \r
+;       source is set CPU clock (CLKB) then the clock for the CAN is also modulated  (if \r
+;       the clock modulator is enabled).\r
+;\r
+; Note: If the clock modulator is enabled,  the wait states  of the  internal flash wait \r
+;       states  must  be  adapted  to  maximum frequency.  Please check the  wait states \r
+;       settings.\r
+;\r
+; Note: This feature  is not supported by every device,  e.g. MB91461.  Please check the \r
+;       data sheet.\r
+;\r
+;=========================================================================================\r
+; 4.8  External Bus Interface\r
+;\r
+;      The rest of the configuration is only applicable for devices with an external bus \r
+;      interface.\r
+;\r
+;      If the device does not offer an external bus interface,  the configuration can be \r
+;      stoped at this point.\r
+;\r
+;=========================================================================================\r
+;\r
+#set    EXTBUS          DEFAULT                 ; <<< Ext. Bus on/off\r
+;\r
+;                       ON      - The ext. bus interface is enabled and is configured as\r
+;                                 set below. \r
+;                             \r
+;                       OFF     - The ext. bus interface is  diabled.  The port function \r
+;                                 registers  are set to  general I/O.  The registers  of \r
+;                                 ext. bus interface will not be touched by the start-up \r
+;                                 file.  \r
+;                                 Be aware, that the device  might be conifgured in ext.\r
+;                                 bus mode by default after reset.\r
+;\r
+;                       DEFAULT - Neither the register nor the respective  port function\r
+;                                 registers are touched by the start-up file.\r
+;                                 Be aware, that the device  might be conifgured in ext. \r
+;                                 bus mode by default after reset.\r
+;\r
+;\r
+; Note: This feature is not supported by every device. Please check the data sheet.  The \r
+;       following devices for example do not offer an external bus interface:  MB91464A, \r
+;       MB91467C, MB91465K, MB91463N, MB91465X.\r
+;\r
+;=========================================================================================\r
+; 4.8.1  Select Chipselect (Only EXTBUS == ON)\r
+;=========================================================================================\r
+;\r
+#set    CS0             OFF                     ; <<< select CS (ON/OFF)\r
+#set    CS1             OFF                     ; <<< select CS (ON/OFF)\r
+#set    CS2             OFF                     ; <<< select CS (ON/OFF)\r
+#set    CS3             OFF                     ; <<< select CS (ON/OFF)\r
+#set    CS4             OFF                     ; <<< select CS (ON/OFF)\r
+#set    CS5             OFF                     ; <<< select CS (ON/OFF)\r
+#set    CS6             OFF                     ; <<< select CS (ON/OFF)\r
+#set    CS7             OFF                     ; <<< select CS (ON/OFF)\r
+#set    SDRAM           OFF                     ; <<< select if a SDRAM is connected \r
+;\r
+;\r
+#set    ENACSX          B'00000000              ; <<< set CS, ENACSX\r
+;                         ||||||||\r
+;                         ||||||||__ CS0 bit, enable/disable CS0 (1/0)\r
+;                         |||||||___ CS1 bit, enable/disable CS1 (1/0)\r
+;                         ||||||____ CS2 bit, enable/disable CS2 (1/0)\r
+;                         |||||_____ CS3 bit, enable/disable CS3 (1/0)\r
+;                         ||||______ CS4 bit, enable/disable CS4 (1/0)\r
+;                         |||_______ CS5 bit, enable/disable CS5 (1/0) \r
+;                         ||________ CS6 bit, enable/disable CS6 (1/0)\r
+;                         |_________ CS7 bit, enable/disable CS7 (1/0)\r
+;\r
+; Note: If the SWB Monitor Debugger is used,  set the CS1 (external RAM only) or CS0 and \r
+;       CS 1 (external RAM and flash) to off.\r
+;\r
+; Note: Not all Chipselects  are supported by  the different devices.  Please check  the \r
+;       data sheet.\r
+;\r
+;=========================================================================================\r
+; 4.8.2  Set memory addressing for Chipselects (only EXTBUS == ON)\r
+;=========================================================================================\r
+;\r
+#set    AREASEL0        0x0000                  ; <<< set start add. for CS0, ASR0  \r
+#set    AREASEL1        0x0000                  ; <<< set start add. for CS1, ASR1           \r
+#set    AREASEL2        0x0000                  ; <<< set start add. for CS2, ASR2 \r
+#set    AREASEL3        0x0000                  ; <<< set start add. for CS3, ASR3 \r
+#set    AREASEL4        0x0000                  ; <<< set start add. for CS4, ASR4 \r
+#set    AREASEL5        0x0000                  ; <<< set start add. for CS5, ASR5 \r
+#set    AREASEL6        0x0000                  ; <<< set start add. for CS6, ASR6 \r
+#set    AREASEL7        0x0000                  ; <<< set start add. for CS7, ASR7 \r
+;\r
+; Configure the starting address of each used Chipselect. Chipselects which are not used\r
+; (not set to ON in "Select Chipselect") need not be set (setting ignored).\r
+;\r
+; NOTE: Just  the upper 16-bit  of the start address must be set,  e.g. when using start \r
+;       address 0x00080000 set 0x0008.\r
+;\r
+;=========================================================================================\r
+; 4.8.3  Configure Chipselect Area (only EXTBUS == ON)\r
+;=========================================================================================\r
+;\r
+#set    CONFIGCS0       B'0000000000000000      ; <<< Config. CS0, ACR0\r
+#set    CONFIGCS1       B'0000000000000000      ; <<< Config. CS1, ACR1 \r
+#set    CONFIGCS2       B'0000000000000000      ; <<< Config. CS2, ACR2 \r
+#set    CONFIGCS3       B'0000000000000000      ; <<< Config. CS3, ACR3 \r
+#set    CONFIGCS4       B'0000000000000000      ; <<< Config. CS4, ACR4  \r
+#set    CONFIGCS5       B'0000000000000000      ; <<< Config. CS5, ACR5  \r
+#set    CONFIGCS6       B'0000000000000000      ; <<< Config. CS6, ACR6  \r
+#set    CONFIGCS7       B'0000000000000000      ; <<< Config. CS7, ACR7  \r
+;                         ||||||||||||||||\r
+;                         ||||||||||||||||__ TYP0 bit, TYP0-4 bits select access type\r
+;                         |||||||||||||||___ TYP1 bit\r
+;                         ||||||||||||||____ TYP2 bit\r
+;                         |||||||||||||_____ TYP3 bit\r
+;                         ||||||||||||______ LEND bit, select little '1' or big endian '0'\r
+;                         |||||||||||_______ WREN bit, en-/disable (1/0) Write access\r
+;                         ||||||||||________ PFEN bit, en-/disable (1/0) pre-fetch\r
+;                         |||||||||_________ SREN bit, en-/disable (1/0) share of BRQ & BGRNTX\r
+;                         ||||||||__________ BST0 bit, BSTx bits select burst size\r
+;                         |||||||___________ BST1 bit\r
+;                         ||||||____________ DBW0 bit, DBWx select data bus width\r
+;                         |||||_____________ DBW1 bit\r
+;                         ||||______________ ASZ0 bit, ASZx bits select address size of CS\r
+;                         |||_______________ ASZ1 bit\r
+;                         ||________________ ASZ2 bit\r
+;                         |_________________ ASZ3 bit\r
+;\r
+; Bit description:\r
+;\r
+; TYP3 TYP2 TYP1 TYP0  : Select access type of each CS\r
+; 0    0    X    X     : Normal access (asynchronous SRAM, I/O, \r
+;                        single/page/busrt-ROM/FLASH) \r
+; 0    1    X    X     : Address/data multiplexed (8bit / 16bit bus width only)\r
+; 0    X    X    0     : WAIT insertion by RDY disabled\r
+; 0    X    X    1     : WAIT insertion by RDY enabled\r
+; 0    X    0    X     : The WR0X pin to the WR3X pin are used as write strobes \r
+;                        (WRX is fixed at H-Level)\r
+; 0    X    1    X     : The WRX pin is used as write strobe \r
+; 1    0    0    0     : Memory type A: SDRAM/FCRAM (Auto pre-charge used)  \r
+; 1    0    0    1     : Memory type B: FCRAM (Auto pre-charge used)  \r
+; 1    0    1    0     : setting not allowed\r
+; 1    0    1    1     : setting not allowed\r
+; 1    1    0    0     : setting not allowed\r
+; 1    1    0    1     : setting not allowed\r
+; 1    1    1    0     : setting not allowed\r
+; 1    1    1    1     : mask area setting\r
+;\r
+;               LEND   : select BYTE ordering \r
+;                0     : Big endian\r
+;                1     : Little endian\r
+;\r
+;               WREN   : enable or disable write access \r
+;                0     : disabled \r
+;                1     : enabled,    \r
+;\r
+;               PFEN   : Enable or disable the pre-fetch\r
+;                0     : disabled \r
+;                1     : enabled,    \r
+;\r
+;               SREN   : Enable or disable the sharing of BRQ and BGRNTX \r
+;                0     : disabled \r
+;                1     : enabled (CSx pin High-Z)\r
+;\r
+;          BST1 BST0   : set burst size of chip select area\r
+;            0   0     : 1 burst (single access)\r
+;            0   1     : 2 bursts (Address boundary 1 bit) \r
+;            1   0     : 4 bursts (Address boundary 2 bit)\r
+;            1   1     : 8 bursts (Address boundary 3 bit)\r
+;\r
+;          DBW1 DBW0   : Set data bus width\r
+;            0   0     : 8-bit (BYTE access) \r
+;            0   1     : 16-bit (HALF-WORD access) \r
+;            1   0     : 32-bit (WORD access) \r
+;            1   1     : Reserved  \r
+;\r
+; ASZ3 ASZ2 ASZ1 ASZ0  :  Select memory size of each chipselect \r
+; 0    0    0    0     : 64 Kbyte  (0x01.0000 bytes; use ASR A[31:16] bits) \r
+; 0    0    0    1     : 128 Kbyte (0x02.0000 bytes; use ASR A[31:17] bits)\r
+; 0    0    1    0     : 256 Kbyte (0x04.0000 bytes; use ASR A[31:18] bits)\r
+; 0    0    1    1     : 512 Kbyte (0x08.0000 bytes; use ASR A[31:19] bits)\r
+; 0    1    0    0     : 1 Mbyte   (0x10.0000 bytes; use ASR A[31:20] bits)\r
+; 0    1    0    1     : 2 Mbyte   (0x20.0000 bytes; use ASR A[31:21] bits)\r
+; 0    1    1    0     : 4 Mbyte   (0x40.0000 bytes; use ASR A[31:22] bits)\r
+; 0    1    1    1     : 8 Mbyte   (0x80.0000 bytes; use ASR A[31:23] bits)\r
+; 1    0    0    0     : 16 Mbyte  (0x100.0000 bytes; use ASR A[31:24] bits)\r
+; 1    0    0    1     : 32 Mbyte  (0x200.0000 bytes; use ASR A[31:25] bits)\r
+; 1    0    1    0     : 64 Mbyte  (0x400.0000 bytes; use ASR A[31:26] bits)\r
+; 1    0    1    1     : 128 Mbyte (0x800.0000 bytes; use ASR A[31:27] bits)\r
+; 1    1    0    0     : 256 Mbyte (0x1000.0000 bytes; use ASR A[31:28] bits)\r
+; 1    1    0    1     : 512 Mbyte (0x2000.0000 bytes; use ASR A[31:29] bits)\r
+; 1    1    1    0     : 1024 Mbyte(0x4000.0000 bytes; use ASR A[31:30] bits)\r
+; 1    1    1    1     : 2048 Mbyte(0x8000.0000 bytes; use ASR A[31] bit)\r
+;\r
+;=========================================================================================\r
+; 4.8.4  Set Wait cycles for Chipselects for ordinary businterface (only EXTBUS == ON)\r
+;=========================================================================================\r
+;\r
+; Ordinary bus interface (w/o SDRAM and FRAM) (ACRx_Type = 0xxx)\r
+;\r
+#set    WAITREG0        B'0000000000000000      ; <<< CS0 Waitstates, AWR0  \r
+#set    WAITREG1        B'0000000000000000      ; <<< CS1 Waitstates, AWR1  \r
+#set    WAITREG2        B'0000000000000000      ; <<< CS2 Waitstates, AWR2 \r
+#set    WAITREG3        B'0000000000000000      ; <<< CS3 Waitstates, AWR3 \r
+#set    WAITREG4        B'0000000000000000      ; <<< CS4 Waitstates, AWR4 \r
+#set    WAITREG5        B'0000000000000000      ; <<< CS5 Waitstates, AWR5 \r
+;                         ||||||||||||||||\r
+;                         ||||||||||||||||__ W00 bit, RDY/WRY-> CSX hold cycle\r
+;                         |||||||||||||||___ W01 bit, CSX->RDX/WRX setup extension cycle\r
+;                         ||||||||||||||____ W02 bit, Address -> CSX Delay selection\r
+;                         |||||||||||||_____ W03 bit, WR0X to WR3X/WRX outout timing \r
+;                         ||||||||||||______ W04 bit, W04/W05 Write recovery cycle\r
+;                         |||||||||||_______ W05 bit  \r
+;                         ||||||||||________ W06 bit, W06/07 Read -> Write idle cycle \r
+;                         |||||||||_________ W07 bit          selection\r
+;                         ||||||||__________ W08 bit, W08-W11 Intra-page access cycle \r
+;                         |||||||___________ W09 bit          select (0-15 cycles)\r
+;                         ||||||____________ W10 bit \r
+;                         |||||_____________ W11 bit\r
+;                         ||||______________ W12 bit, W12-W15 First access wait cycle  \r
+;                         |||_______________ W13 bit          select (0-15 cycles)\r
+;                         ||________________ W14 bit\r
+;                         |_________________ W15 bit\r
+;\r
+;\r
+; SDRAM and FRAM bus interface (ACRx_Type = 100x) \r
+;\r
+#set    WAITREG6        B'0000000000000000      ; <<< CS6 Waitstates, AWR6 \r
+#set    WAITREG7        B'0000000000000000      ; <<< CS7 Waitstates, AWR7\r
+;                         ||||||||||||||||\r
+;                         ||||||||||||||||__ W00 bit, W0-W1 RAS precharge cycles\r
+;                         |||||||||||||||___ W01 bit\r
+;                         ||||||||||||||____ W02 bit, W2-W3 RAS active Time\r
+;                         |||||||||||||_____ W03 bit\r
+;                         ||||||||||||______ W04 bit, W4-W5 Write recovery cycle\r
+;                         |||||||||||_______ W05 bit \r
+;                         ||||||||||________ W06 bit, W6-W7 Read->Write idle cycle\r
+;                         |||||||||_________ W07 bit\r
+;                         ||||||||__________ W08 bit, W8-W10 CAS latency \r
+;                         |||||||___________ W09 bit\r
+;                         ||||||____________ W10 bit \r
+;                         |||||_____________ W11 bit, reserved\r
+;                         ||||______________ W12 bit, W12-W16 RAS-CAS delay \r
+;                         |||_______________ W13 bit\r
+;                         ||________________ W14 bit  \r
+;                         |_________________ W15 bit, reserved\r
+;\r
+;\r
+; The bit meaning depends on the configured bus interface type. The bus interface can be \r
+; configured for different memory types. Depending on the memory type, the wait register \r
+; bits have a differnt meaning.  CS0-5 should  be configurable as ordinary bus interface \r
+; (w/o SDRAM and FRAM)  and CS6-7 should be configurable as  SDRAM and FRAM.  It is also \r
+; possible and for some devices neccessary to configure  other two chip selects as SDRAM \r
+; or FRAM interface. In such a case be aware of the bit meanings.\r
+;\r
+;\r
+; Ordinary bus interface (w/o SDRAM and FRAM) (ACRx_Type = 0xxx)\r
+; --------------------------------------------------------------\r
+;\r
+; Bit description:\r
+;\r
+;                W00   : RDY/WRX -> CSX hold extension cycle\r
+;                0     : 0 cycle\r
+;                1     : 1 cycle\r
+;\r
+;                W01   : CSX -> RDX/WRX setup extention cycle\r
+;                0     : 0 cycle\r
+;                1     : 1 cycle\r
+;\r
+;                W02   : Address -> CSX Delay selection\r
+;                0     : no delay selected\r
+;                1     : delay selected\r
+;\r
+;                W03   : WR0X to WR3X/WRX outout timing selection\r
+;                0     : MCLK synchronous write output enable (ASX=L)\r
+;                1     : Asynchronous write strobe output (norma operation)\r
+;\r
+;           W05  W04   : select Write recovery cycle\r
+;           0    0     : 0 cycle\r
+;           0    1     : 1 cycle\r
+;           1    0     : 2 cycles\r
+;           1    1     : 3 cycles\r
+;\r
+;           W07  W06   : Read -> Write idle cycle selection\r
+;           0    0     : 0 cycle\r
+;           0    1     : 1 cycle\r
+;           1    0     : 2 cycles\r
+;           1    1     : 3 cycles\r
+; \r
+; W11  W10  W09  W08   :  Intra-page access cycle select (0-15 cycles)\r
+; 0    0    0    0     :  0 Wait state\r
+; 0    0    0    1     :  1 Auto-wait cycle\r
+; 0    0    1    0     :  2 Auto-wait cycle\r
+; ....\r
+; 1    1    1    1     :  15 Auto wait cycles\r
+;\r
+; W15  W14  W13  W12   :  First access wait cycle can be set (0-15 cycles)\r
+; 0    0    0    0     :  0 Wait state\r
+; 0    0    0    1     :  1 Auto-wait cycle\r
+; 0    0    1    0     :  2 Auto-wait cycle\r
+; ....\r
+; 1    1    1    1     :  15 Auto wait cycles\r
+;  \r
+;\r
+;\r
+; SDRAM and FRAM bus interface (ACRx_Type = 100x)\r
+; -----------------------------------------------\r
+;\r
+; Bit description:\r
+;\r
+;           W01  W00   : RAS precharge cycles.\r
+;           0    0     : 1 cycle\r
+;           0    1     : 2 cycles\r
+;           1    0     : 5 cycles\r
+;           1    1     : 6 cycles\r
+;\r
+;           W03  W02   : RAS active Time\r
+;           0    0     : 1 cycle\r
+;           0    1     : 2 cycles\r
+;           1    0     : 5 cycles\r
+;           1    1     : 6 cycles\r
+;\r
+;           W05  W04   : set Write recovery cycle (1 - 4 cycles)\r
+;           0    0     : Prohibited\r
+;           0    1     : 2 cycles\r
+;           1    0     : 3 cycles\r
+;           1    1     : 4 cycles\r
+;\r
+;           W07  W06   : set Read -> Write idle Cycle (1 - 4 cycles)\r
+;           0    0     : 1 cycle\r
+;           0    1     : 2 cycles\r
+;           1    0     : 3 cycles\r
+;           1    1     : 4 cycles\r
+;\r
+;      W10  W09  W08   : set CAS latency (1 - 8 cycles)\r
+;      0    0    0     : 1 cycle\r
+;      0    0    1     : 2 cycle\r
+;      ...\r
+;      1    1    1     : 8 cycle\r
+;\r
+;                W11   : RESERVED, ALWAYS WRITE 0 !\r
+;\r
+;      W14  W13  W12   : set RAS-CAS delay (1 - 8 cycles)\r
+;      0    0    0     : 1 cycle\r
+;      0    0    1     : 2 cycle\r
+;      ...\r
+;      1    1    1     : 8 cycle\r
+;\r
+;                W15   : RESERVED, ALWAYS WRITE 0 !\r
+;\r
+\r
+; The bit meaning depends on the configured bus interface type\r
+;\r
+;=========================================================================================\r
+; 4.8.5  Configure Chipselects for SDRAM memory only (only EXTBUS == ON and SDRAM)\r
+;=========================================================================================\r
+;\r
+#set    MEMCON           B'00000111             ; <<< set special SDRAM register, MCRA\r
+;                          ||||||||\r
+;                          ||||||||__ ABS0 bit, set max. active banks (ABS1,0)\r
+;                          |||||||___ ABS1 bit\r
+;                          ||||||____ BANK bit, set number of banks connected to CS\r
+;                          |||||_____ WBST bit, Write burst enable/disable\r
+;                          ||||______ PSZ0 bit, Set page size (PSZ2-0)\r
+;                          |||_______ PSZ1 bit \r
+;                          ||________ PSZ2 bit\r
+;                          |_________ reserved, always write 0 \r
+;\r
+; When connecting  SDRAM/FCRAM TYP3-0=1000  in ACRx register the following register must  \r
+; be setup.\r
+;\r
+; Bit description:\r
+;\r
+;           ABS1  ABS0 : Set maximum number of bank, active at same time\r
+;            0     0   : 1 bank\r
+;            0     1   : 2 banks\r
+;            1     0   : 3 banks\r
+;            1     1   : 4 banks\r
+;\r
+;                 BANK : Set number of connected SDRAM banks\r
+;                  0   : 2 banks\r
+;                  1   : 4 banks\r
+;\r
+;                 WBST : Write burst enable\r
+;                  0   : Single Write\r
+;                  1   : Busrt Write\r
+;\r
+;      PSZ2  PSZ1  PS0 : Select page size of connected memory\r
+;      0     0     0   : 8-bit column address = A0 to A7 \r
+;      0     0     1   : 9-bit column address = A0 to A8 \r
+;      0     1     0   : 10-bit column address = A0 to A9 \r
+;      0     1     1   : 11-bit column address = A0 to A9, A11 \r
+;      1     X     X   : setting disabled\r
+;\r
+;\r
+;=========================================================================================\r
+; 4.8.6  Referesh Control Register RCR (only EXTBUS == ON and SDRAM)\r
+;=========================================================================================\r
+;\r
+#set    REFRESH         B'1110001001000111      ; <<< set Refresh Control Register, RCR\r
+;                         ||||||||||||||||\r
+;                         ||||||||||||||||__ TRC0 bit, set refresh cycle (TRC2-0)\r
+;                         |||||||||||||||___ TRC1 bit\r
+;                         ||||||||||||||____ TRC2 bit\r
+;                         |||||||||||||_____ PON bit, set power-on control\r
+;                         ||||||||||||______ RFC0 bit, set refresh count (RFC2-0)\r
+;                         |||||||||||_______ RFC1 bit \r
+;                         ||||||||||________ RFC2 bit \r
+;                         |||||||||_________ BRST bit, set burst refresh control \r
+;                         ||||||||__________ RFINT0 bit, set auto refresh interval\r
+;                         |||||||___________ RFINT1 bit, (RFINT5-0)\r
+;                         ||||||____________ RFINT2 bit\r
+;                         |||||_____________ RFINT3 bit\r
+;                         ||||______________ RFINT4 bit\r
+;                         |||_______________ RFINT5 bit\r
+;                         ||________________ RRLD bit, counter refresh strat control\r
+;                         |_________________ SELF bit, self refresh control\r
+;\r
+;\r
+; This register sets various SDRAM refresh controls.  When SDRAM control is not set  for \r
+; any area, the setting of this register is meaningless,  but do not change the register \r
+; value  at  initial   state.   When  a  read is  performed   using  a read-modify-write \r
+; instruction, 0 always returns from the SELF, RRLD, and PON bits.\r
+;\r
+; Bit description:\r
+;\r
+;\r
+;    TRC2  TRC1  TRC0  : Refresh Cycle \r
+;      0     0     0   : 4\r
+;      0     0     1   : 5\r
+;      0     1     0   : 6\r
+;      0     1     1   : 7\r
+;      1     0     0   : 8\r
+;      1     0     1   : 9\r
+;      1     1     0   : 10\r
+;      1     1     1   : 11\r
+;\r
+;                 PON  : Power-on control\r
+;                  0   : disabled\r
+;                  1   : power-on sequence started\r
+;\r
+;     RFC2  RFC1  RFC0 : Refresh Count\r
+;      0     0     0   : 256\r
+;      0     0     1   : 512\r
+;      0     1     0   : 1024\r
+;      0     1     1   : 2048\r
+;      1     0     0   : 4096\r
+;      1     0     1   : 8192\r
+;      1     1     0   : Setting disabled\r
+;      1     1     1   : Refresh disabled\r
+;\r
+;                 BRST : Burst refresh control\r
+;                  0   : Decentralised refresh \r
+;                  1   : burst refresh\r
+; \r
+;           RFINT[5-0] : auto refresh interval\r
+;\r
+;                 RRLD : Refresh counter Activation Control\r
+;                  0   : Disabled,  \r
+;                  1   : Autorefresh performed once, then value of RFINT reloaded\r
+;\r
+;                 SELF : Self refresh control\r
+;                  0   : auto refresh or power down\r
+;                  1   : Transitions to self-refresch mode\r
+;\r
+; NOTE: PON bit is set after the above setting. Do not set PON bit to 1 in the \r
+;       above setting. Otherwise the settings are not correct set.\r
+;\r
+;=========================================================================================\r
+; 4.8.7  Terminal and Timing Control Register (only EXTBUS == ON)\r
+;=========================================================================================\r
+;\r
+#set    TIMECONTR        B'00000000             ; <<< set TCR register, TCR\r
+;                          ||||||||\r
+;                          ||||||||__ RDW0 bit, set wait cycle reduction (RDW0,1)\r
+;                          |||||||___ RDW1 bit\r
+;                          ||||||____ OHT0 bit, set output hold delay (OHT1,0)\r
+;                          |||||_____ OHT1 bit\r
+;                          ||||______ reserved, always write 0 \r
+;                          |||_______ PCLR bit, prefetch buffer clear \r
+;                          ||________ PSUS bit, prefetch suspend\r
+;                          |_________ BREN bit, BRQ input enable \r
+;\r
+; This register controls the general functions  of the external bus interface controller \r
+; such as the common-pin function setting and timing control.\r
+;\r
+; Bit description:\r
+;\r
+;          RDW1  RDW0  : Wait cycle reduction \r
+;            0     0   : Normal Wait (AWR0 - 7 setting)\r
+;            0     1   : 1/2 of AWR0 - 7 setting value\r
+;            1     0   : 1/4 of AWR0 - 7 setting value\r
+;            1     1   : 1/8 of AWR0 - 7 setting value\r
+;\r
+;          OHT1  OHT0  : Output hold selection bit\r
+;            0     0   : Output performed at falling edge of SYSCLK/MCLK\r
+;            0     1   : Output performed about 3ns after falling edge of SYSCLK/MCLK\r
+;            1     0   : Output performed about 4ns after falling edge of SYSCLK/MCLK\r
+;            1     1   : Output performed about 5ns after falling edge of SYSCLK/MCLK\r
+;\r
+;                PCLR  : Prefetch buffer all clear\r
+;                  0   : normal state\r
+;                  1   : Prefetch buffer cleared\r
+;\r
+;                PSUS  : prefetch suspension bit \r
+;                  0   : Prefetch enabled\r
+;                  1   : Prefetch disabled\r
+;\r
+;                BREN  : BRQ input enable\r
+;                  0   : disabled, \r
+;                  1   : enabled, Bus sharing of BRQ/BGRNTX performed\r
+;\r
+; Note: This function is used to prevent an  excessive access cycle wait while operating \r
+;       at  a low-speed  clock  (such as  while  base  clock  operating at low  speed or \r
+;       high frequency division rate for external bus clock).\r
+;\r
+;=========================================================================================\r
+; 4.8.8  Enable/Disable I-CACHE (only EXTBUS == ON)\r
+;=========================================================================================\r
+;\r
+#set    C1024           1                       ; CACHE Size: 1024 BYTE\r
+#set    C2048           2                       ; CACHE Size: 2048 BYTE\r
+#set    C4096           3                       ; CACHE Size: 4096 BYTE\r
+;\r
+;\r
+#set    CACHE           OFF                     ; <<< Select use of cache \r
+#set    CACHE_SIZE      C4096                   ; <<< Select size of cache, ISIZE\r
+;\r
+; It is possible  to use cache  functionality on  the I-Bus on  several devices.  Please \r
+; check the  corresponidng data sheet  if this feature is  available on a certain device \r
+; and for the size of the cache. This is the general cache configuration. It is possible \r
+; to configure for each CS area, if the cache should be used.\r
+;\r
+; Note: This feature is not supported by every device. Please check the data  sheet. The \r
+;       feature is for example supported by MB91461R, MB91469G.\r
+;\r
+;=========================================================================================\r
+; 4.8.9  Enable CACHE for chipselect (only EXTBUS == ON)\r
+;=========================================================================================\r
+;\r
+#set    CHEENA          B'11111111              ; <<< en-/disable cache, CHER\r
+;                         ||||||||\r
+;                         ||||||||__ CHE0 bit, CS0 area\r
+;                         |||||||___ CHE1 bit, CS1 area\r
+;                         ||||||____ CHE2 bit, CS2 area\r
+;                         |||||_____ CHE3 bit, CS3 area\r
+;                         ||||______ CHE4 bit, CS4 area \r
+;                         |||_______ CHE5 bit, CS5 area \r
+;                         ||________ CHE6 bit, CS6 area\r
+;                         |_________ CHE7 bit, CS7 area \r
+;\r
+; Additional to  the general cache enable setting,  select which CS  area should be used \r
+; with cache functionality.\r
+;\r
+; Note: Not all  Chipselects are  supported by the  different devices.  Please check the \r
+;       data sheet.\r
+;\r
+; Note: This feature is not supported by every device.  Please check the data sheet. The \r
+;       Feature is supported by MB91461R, MB91469G.\r
+;\r
+;=========================================================================================\r
+; 4.8.10  Select External bus mode (Data lines) (only EXTBUS == ON)\r
+;=========================================================================================\r
+;\r
+#set    PFUNC0          B'11111111              ;<<< Data lines or GIO, PFR00\r
+;                         ||||||||\r
+;                         ||||||||__ D24 / P00_0\r
+;                         |||||||___ D25 / P00_1\r
+;                         ||||||____ D26 / P00_2\r
+;                         |||||_____ D27 / P00_3\r
+;                         ||||______ D28 / P00_4\r
+;                         |||_______ D29 / P00_5\r
+;                         ||________ D30 / P00_6\r
+;                         |_________ D31 / P00_7\r
+;\r
+#set    PFUNC1          B'11111111              ;<<< Data lines or GIO, PFR01\r
+;                         ||||||||\r
+;                         ||||||||__ D16 / P01_0\r
+;                         |||||||___ D17 / P01_1\r
+;                         ||||||____ D18 / P01_2\r
+;                         |||||_____ D19 / P01_3\r
+;                         ||||______ D20 / P01_4\r
+;                         |||_______ D21 / P01_5\r
+;                         ||________ D22 / P01_6\r
+;                         |_________ D23 / P01_7\r
+;\r
+#set    PFUNC2          B'11111111              ;<<< Data lines or GIO, PFR02\r
+;                         ||||||||\r
+;                         ||||||||__ D8 / P02_0\r
+;                         |||||||___ D9 / P02_1\r
+;                         ||||||____ D10 / P02_2\r
+;                         |||||_____ D11 / P02_3\r
+;                         ||||______ D12 / P02_4\r
+;                         |||_______ D13 / P02_5\r
+;                         ||________ D14 / P02_6\r
+;                         |_________ D15 / P02_7\r
+;\r
+#set    PFUNC3          B'11111111              ;<<< Data lines or GIO, PFR03\r
+;                         ||||||||\r
+;                         ||||||||__ D0 / P03_0\r
+;                         |||||||___ D1 / P03_1\r
+;                         ||||||____ D2 / P03_2\r
+;                         |||||_____ D3 / P03_3\r
+;                         ||||______ D4 / P03_4\r
+;                         |||_______ D5 / P03_5\r
+;                         ||________ D6 / P03_6\r
+;                         |_________ D7 / P03_7\r
+;\r
+; Select if the ports are set to\r
+;                  1   : External bus mode, I/O for data lines or\r
+;                  0   : General I/O port (GIO)\r
+;\r
+; Note: Not all data-lines are supported by the different devices. Please check the data\r
+;       sheet.\r
+;\r
+;=========================================================================================\r
+; 4.8.11  Select External bus mode (Address lines) (only EXTBUS == ON)\r
+;=========================================================================================\r
+;\r
+#set    PFUNC4          B'11111111              ;<<< Address lines or GIO, PFR04\r
+;                         ||||||||\r
+;                         ||||||||__ A24 / P04_0\r
+;                         |||||||___ A25 / P04_1\r
+;                         ||||||____ A26 / P04_2\r
+;                         |||||_____ A27 / P04_3\r
+;                         ||||______ A28 / P04_4\r
+;                         |||_______ A29 / P04_5\r
+;                         ||________ A30 / P04_6\r
+;                         |_________ A31 / P04_7\r
+;\r
+#set    PFUNC5          B'11111111              ;<<< Address lines or GIO, PFR05\r
+;                         ||||||||\r
+;                         ||||||||__ A16 / P05_0\r
+;                         |||||||___ A17 / P05_1\r
+;                         ||||||____ A18 / P05_2\r
+;                         |||||_____ A19 / P05_3\r
+;                         ||||______ A20 / P05_4\r
+;                         |||_______ A21 / P05_5\r
+;                         ||________ A22 / P05_6\r
+;                         |_________ A23 / P05_7\r
+;\r
+#set    PFUNC6          B'11111111              ;<<< Address lines or GIO, PFR06\r
+;                         ||||||||\r
+;                         ||||||||__ A8 / P06_0\r
+;                         |||||||___ A9 / P06_1\r
+;                         ||||||____ A10 / P06_2\r
+;                         |||||_____ A11 / P06_3\r
+;                         ||||______ A12 / P06_4\r
+;                         |||_______ A13 / P06_5\r
+;                         ||________ A14 / P06_6\r
+;                         |_________ A15 / P06_7\r
+;\r
+#set    PFUNC7          B'11111111              ;<<< Address lines or GIO, PFR07\r
+;                         ||||||||\r
+;                         ||||||||__ A0 / P07_0\r
+;                         |||||||___ A1 / P07_1\r
+;                         ||||||____ A2 / P07_2\r
+;                         |||||_____ A3 / P07_3\r
+;                         ||||______ A4 / P07_4\r
+;                         |||_______ A5 / P07_5\r
+;                         ||________ A6 / P07_6\r
+;                         |_________ A7 / P07_7\r
+;\r
+; Select if the ports are set to\r
+;                  1   : External bus mode, I/O for address lines or\r
+;                  0   : General I/O port (GIO)\r
+;\r
+; Note: Not all address-lines are supported  by the different devices.  Please check the\r
+;       data sheet.\r
+;\r
+;=========================================================================================\r
+; 4.8.12  Select External bus mode (Control signals) (only EXTBUS == ON)\r
+;=========================================================================================\r
+;\r
+#set    PFUNC8          B'11111111              ;<<< Control signals or GIO, PFR08\r
+;                         ||||||||\r
+;                         ||||||||__ WRX0 / P08_0\r
+;                         |||||||___ WRX1 / P08_1\r
+;                         ||||||____ WRX2 / P08_2\r
+;                         |||||_____ WRX3 / P08_3\r
+;                         ||||______ RDX / P08_4\r
+;                         |||_______ BGRNTX / P08_5\r
+;                         ||________ BRQ / P08_6\r
+;                         |_________ RDY / P08_7\r
+;\r
+#set    PFUNC9          B'11111111              ;<<< Control signals or GIO, PFR09\r
+;                         ||||||||\r
+;                         ||||||||__ CSX0 / P09_0\r
+;                         |||||||___ CSX1 / P09_1\r
+;                         ||||||____ CSX2 / P09_2\r
+;                         |||||_____ CSX3 / P09_3\r
+;                         ||||______ CSX4 / P09_4\r
+;                         |||_______ CSX5 / P09_5\r
+;                         ||________ CSX6 / P09_6\r
+;                         |_________ CSX7 / P09_7\r
+;\r
+#set    PFUNC10         B'01011111              ;<<< Control signals or GIO, PFR10\r
+;                         ||||||||\r
+;                         ||||||||__ SYSCLK or !SYSCLK / P10_0 \r
+;                         |||||||___ ASX / P10_1 \r
+;                         ||||||____ BAAX / P10_2 \r
+;                         |||||_____ WEX / P10_3 \r
+;                         ||||______ MCLKO or !MCLKO / P10_4 \r
+;                         |||_______ MCLKI or !MCLKI/ P10_5 \r
+;                         ||________ MCLKE / P10_6\r
+;                         |_________ - \r
+;\r
+#set    EPFUNC10        B'00000000              ;<<< Control signals or GIO, EPFR10\r
+;                         ||||||||\r
+;                         ||||||||__ 0:SYSCLK / 1:!SYSCLK\r
+;                         |||||||___ - \r
+;                         ||||||____ -\r
+;                         |||||_____ -\r
+;                         ||||______ 0:MCLKO / 1:!MCLKO\r
+;                         |||_______ 0:MCLKI / 1:!MCLKI\r
+;                         ||________ 0:MCLKI / 1:!MCLKI\r
+;                         |_________ -\r
+;\r
+;\r
+; Select if the ports are set to\r
+;                  1   : External bus mode, I/O for control lines or\r
+;                  0   : General I/O port (GIO)\r
+;\r
+; Note: Not all control-lines are supported  by the different devices.  Please check the\r
+;       data sheet.\r
+;\r
+;=========================================================================================\r
+; 5  Definition of Configurations\r
+;=========================================================================================\r
+;\r
+#set    NOCLOCK         0                       ; do not touch CKSCR register\r
+#set    MAINCLOCK       1                       ; select main clock \r
+;                                               ; MB91461R : 1/4 of oscillation input\r
+;                                               ; Others:    1/2 of oscillation input\r
+#set    MAINPLLCLOCK    2                       ; select main clock with PLL\r
+#set    SUBCLOCK        3                       ; select subclock (if available)\r
+;\r
+#set    PSCLOCK_CLKB    0x00                    ; select core clock (initial)\r
+#set    PSCLOCK_PLL     0x10                    ; select PLL output (x)\r
+#set    PSCLOCK_MAIN    0x30                    ; select Main Oscillation\r
+;\r
+;=========================================================================================\r
+; 5.1  CLOCKSPEED == CLOCK_USER <<<\r
+;=========================================================================================\r
+; Must be configured only in the case of CLOCKSPEED is set to CLOCK_USER. Please see the \r
+; corresponding application note.\r
+;\r
+#if (CLOCKSPEED == CLOCK_USER )\r
+  #set  CLOCKSOURCE     MAINPLLCLOCK            ; <<< Clocksource\r
+  #set  ENABLE_SUBCLOCK OFF                     ; <<< Subclock: ON/OFF\r
+  #set  PLLSPEED        0x010F                  ; <<< 0x48Ch, 0x48Dh: PLLDIVM/N ; 64 MHz\r
+  #set  DIV_G           0x0F                    ; <<< 0x48Eh: PLLDIVG; \r
+  #set  MUL_G           0x0F                    ; <<< 0x48Fh: PLLMULG;     \r
+  ; Clock Divider\r
+  #set  CPUCLOCK        0x00                    ; <<< 0x486h: DIV0R_B;   => /1  ; 64 MHz       \r
+  #set  PERCLOCK        0x03                    ; <<< 0x486h: DIV0R_P;   => /4  ; 16 MHz \r
+  #set  EXTBUSCLOCK     0x01                    ; <<< 0x487h: DIV1R_T;   => /2  ; 32 MHz \r
+  ; CAN Clock\r
+  #set  PSCLOCKSOURCE   PSCLOCK_PLL             ; <<< 0x4C0h: CANPRE;    => PLLx;128 MHz\r
+  #set  PSDVC           0x07                    ; <<< 0x4C0h: CANPRE_DVC;=> /8  ; 16 MHz\r
+  #set  CANCLOCK        0x00                    ; <<< 0x4C1h: CANCKD;    \r
+  ; Voltage Regulator \r
+  #set  REGULATORSEL    0x06                    ; <<< 0x4CEh: REGSEL;\r
+  #set  REGULATORCTRL   0x00                    ; <<< 0x4CFh: REGCTR;\r
+  ; Memory Controller\r
+  #set  FLASHCONTROL    0x032                   ; <<< 0x7002h: FCHCR;\r
+  #set  FLASHREADT      0xC413                  ; <<< 0x7004h: FMWT;\r
+  #set  FLASHMWT2       0x10                    ; <<< 0x7006h: FMWT2;\r
+#endif  \r
+;\r
+;=========================================================================================\r
+; 5.2  CLOCKSPEED == NO_CLOCK\r
+;=========================================================================================\r
+;\r
+#if (CLOCKSPEED == NO_CLOCK )\r
+    #set CLOCKSOURCE       NOCLOCK \r
+#endif      \r
+;\r
+;=========================================================================================\r
+; 5.2  CLOCKSPEED == SUB_32KHZ_CPU__32KHZ_PER_32KHZ_EXT_32KHZ_CAN__2MHZ \r
+;=========================================================================================\r
+;\r
+#if (CLOCKSPEED == SUB_32KHZ_CPU__32KHZ_PER_32KHZ_EXT_32KHZ_CAN__2MHZ )\r
+;\r
+; Start restriction; Maximum frequency\r
+  #if (DEVICE == MB91463N) || (DEVICE == MB91461R) \r
+     #error: Frequency is not supported by this device.\r
+  #endif \r
+; End restriction\r
+;\r
+  #set  CLOCKSOURCE     SUBCLOCK                ; Clocksource\r
+  #set  ENABLE_SUBCLOCK ON                      ; Subclock: ON/OFF\r
+  #set  PLLSPEED        0x010F                  ; 0x48Ch, 0x48Dh: PLLDIVM/N    ;   n. a.\r
+  #set  DIV_G           0x0F                    ; 0x48Eh: PLLDIVG; \r
+  #set  MUL_G           0x0F                    ; 0x48Fh: PLLMULG;     \r
+  ; Clock Divider\r
+  #set  CPUCLOCK        0x00                    ; 0x486h: DIV0R_B;    => /1    ;  32 KHz       \r
+  #set  PERCLOCK        0x00                    ; 0x486h: DIV0R_P;    => /1    ;  32 KHz  \r
+  #set  EXTBUSCLOCK     0x00                    ; 0x487h: DIV1R_T;    => /1    ;  32 KHz  \r
+  ; CAN Clock\r
+  #set  PSCLOCKSOURCE   PSCLOCK_MAIN            ; 0x4C0h: CANPRE;     => MAIN  ;   4 MHz\r
+  #set  PSDVC           0x01                    ; 0x4C0h: CANPRE_DVC; => /2    ;   2 MHz\r
+  #set  CANCLOCK        0x00                    ; 0x4C1h: CANCKD; all CAN Clocks enabled\r
+  ; Voltage Regulator \r
+  #set  REGULATORSEL    0x06                    ; 0x4CEh: REGSEL;\r
+  #set  REGULATORCTRL   0x00                    ; 0x4CFh: REGCTR;\r
+  ; Memory Controller\r
+  #set  FLASHCONTROL    0x032                   ; 0x7002h: FCHCR;\r
+  #set  FLASHREADT      0xC100                  ; 0x7004h: FMWT; \r
+  #set  FLASHMWT2       0x00                    ; 0x7006h: FMWT2;\r
+#endif \r
+;\r
+;=========================================================================================\r
+; 5.3  CLOCKSPEED == MAIN__4MHZ_CPU___2MHZ_PER__1MHZ_EXT__1MHZ_CAN__2MHZ \r
+;=========================================================================================\r
+;\r
+#if (CLOCKSPEED == MAIN_4MHZ_CPU___2MHZ_PER__1MHZ_EXT__1MHZ_CAN__2MHZ )\r
+;\r
+; Start restriction; Maximum frequency\r
+  #if (DEVICE == MB91461R) \r
+     #error: Frequency is not supported by this device.\r
+  #endif \r
+; End restriction\r
+;\r
+  #set  CLOCKSOURCE     MAINCLOCK               ; Clocksource\r
+  #set  ENABLE_SUBCLOCK OFF                     ; Subclock: ON/OFF\r
+  #set  PLLSPEED        0x010F                  ; 0x48Ch, 0x48Dh: PLLDIVM/N    ;   n. a.\r
+  #set  DIV_G           0x0F                    ; 0x48Eh: PLLDIVG; \r
+  #set  MUL_G           0x0F                    ; 0x48Fh: PLLMULG;     \r
+  ; Clock Divider\r
+  #set  CPUCLOCK        0x00                    ; 0x486h: DIV0R_B;    => /1    ;   2 MHz       \r
+  #set  PERCLOCK        0x01                    ; 0x486h: DIV0R_P;    => /2    ;   1 MHz \r
+  #set  EXTBUSCLOCK     0x01                    ; 0x487h: DIV1R_T;    => /2    ;   1 MHz \r
+  ; CAN Clock\r
+  #set  PSCLOCKSOURCE   PSCLOCK_MAIN            ; 0x4C0h: CANPRE;     => PLLx  ;   4 MHz\r
+  #set  PSDVC           0x01                    ; 0x4C0h: CANPRE_DVC; => /2    ;   2 MHz\r
+  #set  CANCLOCK        0x00                    ; 0x4C1h: CANCKD; all CAN Clocks enabled\r
+  ; Voltage Regulator \r
+  #set  REGULATORSEL    0x06                    ; 0x4CEh: REGSEL;\r
+  #set  REGULATORCTRL   0x00                    ; 0x4CFh: REGCTR;\r
+  ; Memory Controller\r
+  #set  FLASHCONTROL    0x032                   ; 0x7002h: FCHCR;\r
+  #set  FLASHREADT      0xC100                  ; 0x7004h: FMWT;\r
+  #set  FLASHMWT2       0x00                    ; 0x7006h: FMWT2;  \r
+#endif           \r
+;\r
+;=========================================================================================\r
+; 5.4  CLOCKSPEED == PLL_4MHZ__CPU__48MHZ_PER_16MHZ_EXT_24MHZ_CAN_16MHZ \r
+;=========================================================================================\r
+;\r
+#if (CLOCKSPEED == PLL_4MHZ__CPU__48MHZ_PER_16MHZ_EXT_24MHZ_CAN_16MHZ )\r
+;\r
+; Start restriction; Maximum frequency\r
+  #if (DEVICE == MB91461R) \r
+     #error: Frequency is not supported by this device.\r
+  #endif \r
+; End restriction\r
+;\r
+  #set  CLOCKSOURCE     MAINPLLCLOCK            ; Clocksource\r
+  #set  ENABLE_SUBCLOCK OFF                     ; Subclock: ON/OFF\r
+  #set  PLLSPEED        0x010B                  ; 0x48Ch, 0x48Dh: PLLDIVM/N    ;  48 MHz\r
+  #set  DIV_G           0x0F                    ; 0x48Eh: PLLDIVG; \r
+  #set  MUL_G           0x0B                    ; 0x48Fh: PLLMULG;     \r
+  ; Clock Divider\r
+  #set  CPUCLOCK        0x00                    ; 0x486h: DIV0R_B;    => /1    ;  48 MHz       \r
+  #set  PERCLOCK        0x02                    ; 0x486h: DIV0R_P;    => /3    ;  16 MHz \r
+  #set  EXTBUSCLOCK     0x01                    ; 0x487h: DIV1R_T;    => /2    ;  24 MHz \r
+  ; CAN Clock\r
+  #set  PSCLOCKSOURCE   PSCLOCK_PLL             ; 0x4C0h: CANPRE;     => PLLx  ;  96 MHz\r
+  #set  PSDVC           0x05                    ; 0x4C0h: CANPRE_DVC; => /6    ;  16 MHz\r
+  #set  CANCLOCK        0x00                    ; 0x4C1h: CANCKD; all CAN Clocks enabled\r
+  ; Voltage Regulator \r
+  #if (DEVICE == MB91469G) \r
+   #set REGULATORSEL    0x36                    ; 0x4CEh: REGSEL;\r
+  #else\r
+   #set REGULATORSEL    0x06                    ; 0x4CEh: REGSEL;\r
+  #endif    \r
+  #set REGULATORCTRL    0x00                    ; 0x4CFh: REGCTR;    \r
+   ; Memory Controller\r
+  #set  FLASHCONTROL    0x032                   ; 0x7002h: FCHCR;\r
+  #set  FLASHREADT      0xC201                  ; 0x7004h: FMWT;\r
+  #set  FLASHMWT2       0x00                    ; 0x7006h: FMWT2;   \r
+#endif        \r
+;\r
+;=========================================================================================\r
+; 5.5  CLOCKSPEED == PLL_4MHZ__CPU__64MHZ_PER_16MHZ_EXT_32MHZ_CAN_16MHZ \r
+;=========================================================================================\r
+;\r
+#if (CLOCKSPEED == PLL_4MHZ__CPU__64MHZ_PER_16MHZ_EXT_32MHZ_CAN_16MHZ )\r
+;\r
+; Start restriction; Maximum frequency\r
+  #if (DEVICE == MB91461R) \r
+     #error: Frequency is not supported by this device.\r
+  #endif \r
+; End restriction\r
+;\r
+  #set  CLOCKSOURCE     MAINPLLCLOCK            ; Clocksource\r
+  #set  ENABLE_SUBCLOCK OFF                     ; Subclock: ON/OFF\r
+  #set  PLLSPEED        0x010F                  ; 0x48Ch, 0x48Dh: PLLDIVM/N    ;  64 MHz\r
+  #set  DIV_G           0x0F                    ; 0x48Eh: PLLDIVG; \r
+  #set  MUL_G           0x0F                    ; 0x48Fh: PLLMULG;     \r
+  ; Clock Divider\r
+  #set  CPUCLOCK        0x00                    ; 0x486h: DIV0R_B;    => /1    ;  64 MHz       \r
+  #set  PERCLOCK        0x03                    ; 0x486h: DIV0R_P;    => /4    ;  16 MHz \r
+  #set  EXTBUSCLOCK     0x01                    ; 0x487h: DIV1R_T;    => /2    ;  32 MHz \r
+  ; CAN Clock\r
+  #set  PSCLOCKSOURCE   PSCLOCK_PLL             ; 0x4C0h: CANPRE;     => PLLx  ; 128 MHz\r
+  #set  PSDVC           0x07                    ; 0x4C0h: CANPRE_DVC; => /8    ;  16 MHz\r
+  #set  CANCLOCK        0x00                    ; 0x4C1h: CANCKD; all CAN Clocks enabled\r
+  ; Voltage Regulator \r
+  #set  REGULATORSEL    0x06                    ; 0x4CEh: REGSEL;\r
+  #set  REGULATORCTRL   0x00                    ; 0x4CFh: REGCTR;\r
+  ; Memory Controller\r
+  #set  FLASHCONTROL    0x032                   ; 0x7002h: FCHCR;\r
+  #set  FLASHREADT      0xC413                  ; 0x7004h: FMWT;\r
+  #set  FLASHMWT2       0x10                    ; 0x7006h: FMWT2;\r
+#endif  \r
+;\r
+;=========================================================================================\r
+; 5.6  CLOCKSPEED == PLL_4MHZ__CPU__80MHZ_PER_20MHZ_EXT_27MHZ_CAN_20MHZ \r
+;=========================================================================================\r
+;\r
+#if (CLOCKSPEED == PLL_4MHZ__CPU__80MHZ_PER_20MHZ_EXT_27MHZ_CAN_20MHZ )\r
+;\r
+; Start restriction; Maximum frequency\r
+  #if (DEVICE == MB91461R) \r
+     #error: Frequency is not supported by this device.\r
+  #endif \r
+; End restriction\r
+;\r
+  #set  CLOCKSOURCE     MAINPLLCLOCK            ; Clocksource\r
+  #set  ENABLE_SUBCLOCK OFF                     ; Subclock: ON/OFF\r
+  #set  PLLSPEED        0x0113                  ; 0x48Ch, 0x48Dh: PLLDIVM/N    ;  80 MHz\r
+  #set  DIV_G           0x0F                    ; 0x48Eh: PLLDIVG; \r
+  #set  MUL_G           0x13                    ; 0x48Fh: PLLMULG;     \r
+  ; Clock Divider\r
+  #set  CPUCLOCK        0x00                    ; 0x486h: DIV0R_B;    => /1    ;  80 MHz       \r
+  #set  PERCLOCK        0x03                    ; 0x486h: DIV0R_P;    => /4    ;  20 MHz \r
+  #set  EXTBUSCLOCK     0x02                    ; 0x487h: DIV1R_T;    => /3    ;  27 MHz \r
+  ; CAN Clock\r
+  #set  PSCLOCKSOURCE   PSCLOCK_PLL             ; 0x4C0h: CANPRE;     => PLLx  ; 160 MHz\r
+  #set  PSDVC           0x07                    ; 0x4C0h: CANPRE_DVC; => /8    ;   8 MHz\r
+  #set  CANCLOCK        0x00                    ; 0x4C1h: CANCKD; all CAN Clocks enabled\r
+  ; Voltage Regulator \r
+  #set  REGULATORSEL    0x06                    ; 0x4CEh: REGSEL;\r
+  #set  REGULATORCTRL   0x00                    ; 0x4CFh: REGCTR;\r
+  ; Memory Controller\r
+  #set  FLASHCONTROL    0x032                   ; 0x7002h: FCHCR;\r
+  #set  FLASHREADT      0xC413                  ; 0x7004h: FMWT;\r
+  #set  FLASHMWT2       0x10                    ; 0x7006h: FMWT2;\r
+#endif      \r
+;\r
+;=========================================================================================\r
+; 5.7  CLOCKSPEED == PLL_4MHZ__CPU__80MHZ_PER_20MHZ_EXT_40MHZ_CAN_20MHZ \r
+;=========================================================================================\r
+;\r
+#if (CLOCKSPEED == PLL_4MHZ__CPU__80MHZ_PER_20MHZ_EXT_40MHZ_CAN_20MHZ )\r
+;\r
+; Start restriction; Maximum frequency\r
+  #if (DEVICE == MB91461R) \r
+     #error: Frequency is not supported by this device.\r
+  #endif \r
+; End restriction\r
+;\r
+  #set  CLOCKSOURCE     MAINPLLCLOCK            ; Clocksource\r
+  #set  ENABLE_SUBCLOCK OFF                     ; Subclock: ON/OFF\r
+  #set  PLLSPEED        0x0113                  ; 0x48Ch, 0x48Dh: PLLDIVM/N    ;  80 MHz\r
+  #set  DIV_G           0x0F                    ; 0x48Eh: PLLDIVG; \r
+  #set  MUL_G           0x13                    ; 0x48Fh: PLLMULG;     \r
+  ; Clock Divider\r
+  #set  CPUCLOCK        0x00                    ; 0x486h: DIV0R_B;    => /1    ;  80 MHz       \r
+  #set  PERCLOCK        0x03                    ; 0x486h: DIV0R_P;    => /4    ;  20 MHz \r
+  #set  EXTBUSCLOCK     0x01                    ; 0x487h: DIV1R_T;    => /2    ;  40 MHz \r
+  ; CAN Clock\r
+  #set  PSCLOCKSOURCE   PSCLOCK_PLL             ; 0x4C0h: CANPRE;     => PLLx  ; 160 MHz\r
+  #set  PSDVC           0x07                    ; 0x4C0h: CANPRE_DVC; => /8    ;   8 MHz\r
+  #set  CANCLOCK        0x00                    ; 0x4C1h: CANCKD; all CAN Clocks enabled\r
+  ; Voltage Regulator \r
+  #set  REGULATORSEL    0x06                    ; 0x4CEh: REGSEL;\r
+  #set  REGULATORCTRL   0x00                    ; 0x4CFh: REGCTR;\r
+  ; Memory Controller\r
+  #set  FLASHCONTROL    0x032                   ; 0x7002h: FCHCR;\r
+  #set  FLASHREADT      0xC413                  ; 0x7004h: FMWT;\r
+  #set  FLASHMWT2       0x10                    ; 0x7006h: FMWT2;\r
+#endif      \r
+;\r
+;=========================================================================================\r
+; 5.8  CLOCKSPEED == PLL_4MHZ__CPU__96MHZ_PER_16MHZ_EXT_48MHZ_CAN_16MHZ \r
+;=========================================================================================\r
+;\r
+#if (CLOCKSPEED == PLL_4MHZ__CPU__96MHZ_PER_16MHZ_EXT_48MHZ_CAN_16MHZ )\r
+;\r
+; Start restriction; Maximum frequency\r
+  #if (DEVICE == MB91464A) || (DEVICE == MB91465K) || (DEVICE == MB91463N) ||\\r
+      (DEVICE == MB91461R) || (DEVICE == MB91467R)\r
+     #error: Frequency is not supported by this device.\r
+  #endif \r
+; End restriction\r
+;\r
+  #set  CLOCKSOURCE     MAINPLLCLOCK            ; Clocksource\r
+  #set  ENABLE_SUBCLOCK OFF                     ; Subclock: ON/OFF\r
+  #set  PLLSPEED        0x0117                  ; 0x48Ch, 0x48Dh: PLLDIVM/N    ;  96 MHz\r
+  #set  DIV_G           0x0F                    ; 0x48Eh: PLLDIVG; \r
+  #set  MUL_G           0x17                    ; 0x48Fh: PLLMULG;     \r
+  ; Clock Divider\r
+  #set  CPUCLOCK        0x00                    ; 0x486h: DIV0R_B;    => /1    ;  64 MHz       \r
+  #set  PERCLOCK        0x05                    ; 0x486h: DIV0R_P;    => /6    ;  16 MHz \r
+  #set  EXTBUSCLOCK     0x01                    ; 0x487h: DIV1R_T;    => /2    ;  32 MHz \r
+  ; CAN Clock\r
+  #set  PSCLOCKSOURCE   PSCLOCK_PLL             ; 0x4C0h: CANPRE;     => PLLx  ; 192 MHz\r
+  #set  PSDVC           0x0B                    ; 0x4C0h: CANPRE_DVC; => /12   ;  16 MHz\r
+  #set  CANCLOCK        0x00                    ; 0x4C1h: CANCKD; all CAN Clocks enabled\r
+  ; Voltage Regulator \r
+  #if (DEVICE == MB91469G) \r
+   #set REGULATORSEL    0x36                    ; 0x4CEh: REGSEL;\r
+  #else\r
+   #set REGULATORSEL    0x06                    ; 0x4CEh: REGSEL;\r
+  #endif    \r
+  #set REGULATORCTRL    0x00                    ; 0x4CFh: REGCTR;    \r
+  ; Memory Controller\r
+  #set FLASHCONTROL     0x032                   ; 0x7002h: FCHCR;\r
+  #set FLASHREADT       0xC413                  ; 0x7004h: FMWT;\r
+  #set FLASHMWT2        0x10                    ; 0x7006h: FMWT2;\r
+#endif        \r
+;\r
+;=========================================================================================\r
+; 5.9  CLOCKSPEED == PLL_4MHZ__CPU_100MHZ_PER_20MHZ_EXT_50MHZ_CAN_20MHZ \r
+;=========================================================================================\r
+;\r
+#if (CLOCKSPEED == PLL_4MHZ__CPU_100MHZ_PER_20MHZ_EXT_50MHZ_CAN_20MHZ )\r
+;\r
+; Start restriction; Maximum frequency\r
+  #if (DEVICE == MB91464A) || (DEVICE == MB91465K) || (DEVICE == MB91463N) ||\\r
+      (DEVICE == MB91461R) || (DEVICE == MB91467R) || (DEVICE == MB91467D)\r
+     #error: Frequency is not supported by this device.\r
+  #endif \r
+; End restriction\r
+;\r
+  #set  CLOCKSOURCE     MAINPLLCLOCK            ; Clocksource\r
+  #set  ENABLE_SUBCLOCK OFF                     ; Subclock: ON/OFF\r
+  #set  PLLSPEED        0x0118                  ; 0x48Ch, 0x48Dh: PLLDIVM/N    ; 100 MHz\r
+  #set  DIV_G           0x0F                    ; 0x48Eh: PLLDIVG; \r
+  #set  MUL_G           0x17                    ; 0x48Fh: PLLMULG;     \r
+  ; Clock Divider\r
+  #set  CPUCLOCK        0x00                    ; 0x486h: DIV0R_B;    => /1    ; 100 MHz       \r
+  #set  PERCLOCK        0x04                    ; 0x486h: DIV0R_P;    => /5    ;  20 MHz \r
+  #set  EXTBUSCLOCK     0x01                    ; 0x487h: DIV1R_T;    => /2    ;  50 MHz \r
+  ; CAN Clock\r
+  #set  PSCLOCKSOURCE   PSCLOCK_PLL             ; 0x4C0h: CANPRE;     => PLLx  ; 200 MHz\r
+  #set  PSDVC           0x09                    ; 0x4C0h: CANPRE_DVC; => /10   ;  20 MHz\r
+  #set  CANCLOCK        0x00                    ; 0x4C1h: CANCKD; all CAN Clocks enabled\r
+  ; Voltage Regulator \r
+  #if (DEVICE == MB91469G) \r
+   #set REGULATORSEL    0x36                    ; 0x4CEh: REGSEL;\r
+  #else\r
+   #set REGULATORSEL    0x06                    ; 0x4CEh: REGSEL;\r
+  #endif    \r
+  #set  REGULATORCTRL   0x00                    ; 0x4CFh: REGCTR;    \r
+  ; Memory Controller\r
+  #set  FLASHCONTROL    0x032                   ; 0x7002h: FCHCR;\r
+  #set  FLASHREADT      0xC413                  ; 0x7004h: FMWT;\r
+  #set  FLASHMWT2       0x10                    ; 0x7006h: FMWT2;\r
+#endif        \r
+;\r
+;=========================================================================================\r
+; 5.10  CLOCKSPEED == PLL_10MHZ_CPU__60MHZ_PER_20MHZ_EXT_30MHZ_CAN_20MHZ \r
+;=========================================================================================\r
+;\r
+#if (CLOCKSPEED == PLL_10MHZ_CPU__60MHZ_PER_20MHZ_EXT_30MHZ_CAN_20MHZ )\r
+;\r
+; Start restriction; Maximum frequency\r
+  #if (DEVICE == MB91464A) || (DEVICE == MB91467B) || (DEVICE == MB91467C) ||\\r
+      (DEVICE == MB91467D) || (DEVICE == MB91469G) || (DEVICE == MB91465K) ||\\r
+      (DEVICE == MB91463N) || (DEVICE == MB91467R) || (DEVICE == MB91465X) \r
+     #error: Frequency is not supported by this device.\r
+  #endif \r
+; End restriction\r
+;\r
+  #set  CLOCKSOURCE     MAINPLLCLOCK            ; Clocksource\r
+  #set  ENABLE_SUBCLOCK OFF                     ; Subclock: ON/OFF\r
+  #set  PLLSPEED        0x0105                  ; 0x48Ch, 0x48Dh: PLLDIVM/N    ;  60 MHz\r
+  #set  DIV_G           0x0B                    ; 0x48Eh: PLLDIVG; \r
+  #set  MUL_G           0x1F                    ; 0x48Fh: PLLMULG;     \r
+  ; Clock Divider\r
+  #set  CPUCLOCK        0x00                    ; 0x486h: DIV0R_B;    => /1    ;  60 MHz       \r
+  #set  PERCLOCK        0x02                    ; 0x486h: DIV0R_P;    => /3    ;  20 MHz \r
+  #set  EXTBUSCLOCK     0x01                    ; 0x487h: DIV1R_T;    => /2    ;  30 MHz \r
+  ; CAN Clock\r
+  #set  PSCLOCKSOURCE   PSCLOCK_PLL             ; 0x4C0h: CANPRE;     => PLLx  ; 120 MHz\r
+  #set  PSDVC           0x05                    ; 0x4C0h: CANPRE_DVC; => /6    ;  20 MHz\r
+  #set  CANCLOCK        0x00                    ; 0x4C1h: CANCKD; all CAN Clocks enabled\r
+  ; Voltage Regulator \r
+  ; -\r
+  ; Memory Controller\r
+  ; -\r
+#endif        \r
+;\r
+;=========================================================================================\r
+; 5.11  CLOCKSPEED == PLL_20MHZ_CPU__60MHZ_PER_20MHZ_EXT_30MHZ_CAN_20MHZ \r
+;=========================================================================================\r
+;\r
+#if (CLOCKSPEED == PLL_20MHZ_CPU__60MHZ_PER_20MHZ_EXT_30MHZ_CAN_20MHZ )\r
+;\r
+; Start restriction; Maximum frequency\r
+  #if (DEVICE == MB91464A) || (DEVICE == MB91467B) || (DEVICE == MB91467C) ||\\r
+      (DEVICE == MB91467D) || (DEVICE == MB91469G) || (DEVICE == MB91465K) ||\\r
+      (DEVICE == MB91463N) || (DEVICE == MB91467R) || (DEVICE == MB91465X) \r
+     #error: Frequency is not supported by this device.\r
+  #endif \r
+; End restriction\r
+;\r
+  #set  CLOCKSOURCE     MAINPLLCLOCK            ; Clocksource\r
+  #set  ENABLE_SUBCLOCK OFF                     ; Subclock: ON/OFF\r
+  #set  PLLSPEED        0x0102                  ; 0x48Ch, 0x48Dh: PLLDIVM/N    ; 60 MHz\r
+  #set  DIV_G           0x0F                    ; 0x48Eh: PLLDIVG; \r
+  #set  MUL_G           0x1F                    ; 0x48Fh: PLLMULG;     \r
+  ; Clock Divider\r
+  #set  CPUCLOCK        0x00                    ; 0x486h: DIV0R_B;    => /1    ;  60 MHz       \r
+  #set  PERCLOCK        0x02                    ; 0x486h: DIV0R_P;    => /3    ;  20 MHz \r
+  #set  EXTBUSCLOCK     0x01                    ; 0x487h: DIV1R_T;    => /2    ;  30 MHz \r
+  ; CAN Clock\r
+  #set  PSCLOCKSOURCE   PSCLOCK_PLL             ; 0x4C0h: CANPRE;     => PLLx  ; 120 MHz\r
+  #set  PSDVC           0x05                    ; 0x4C0h: CANPRE_DVC; => /6    ;  20 MHz\r
+  #set  CANCLOCK        0x00                    ; 0x4C1h: CANCKD; all CAN Clocks enabled\r
+  ; Voltage Regulator \r
+  ; -\r
+  ; Memory Controller\r
+  ; -\r
+#endif  \r
+;      \r
+;=========================================================================================\r
+; 6  Section and Data Declaration\r
+;=========================================================================================\r
+\r
+        .export __start             \r
+        .import _main\r
+        .import _RAM_INIT\r
+        .import _ROM_INIT\r
+        \r
+#if CLIBINIT == ON    \r
+        .export __exit \r
+        .import _exit\r
+        .import __stream_init\r
+#endif\r
+\r
+#if CPLUSPLUS == ON\r
+        .export __abort\r
+        .import ___call_dtors\r
+        .import _atexit\r
+#endif\r
+;=========================================================================================\r
+; 6.1  Define Stack Size\r
+;=========================================================================================\r
+ .SECTION  SSTACK, STACK, ALIGN=4\r
+#if STACK_RESERVE == ON\r
+        .EXPORT         __systemstack, __systemstack_top\r
+ __systemstack:\r
+        .RES.B          STACK_SYS_SIZE\r
+ __systemstack_top: \r
+#endif\r
+ \r
+        .SECTION  USTACK, STACK, ALIGN=4\r
+#if STACK_RESERVE == ON\r
+         .EXPORT        __userstack, __userstack_top\r
+ __userstack:\r
+        .RES.B          STACK_USR_SIZE\r
+ __userstack_top:\r
+ \r
+#endif\r
+;=========================================================================================\r
+; 6.2  Define Sections\r
+;=========================================================================================\r
+        .section        DATA,  data,  align=4\r
+        .section        INIT,  data,  align=4\r
+        .section        IRAM,  code,  align=4\r
+        .section        CONST, const, align=4\r
+        .section        INTVECT, const, align=4 \r
+        \r
+#if I_RAM \r
+        .import _RAM_IRAM\r
+        .import _ROM_IRAM\r
+#endif\r
+                    \r
+#if (DEVICE != MB91461R)\r
+    #if (DEVICE == MB91469G)\r
+        .section        SECURITY_VECTORS, code, locate = 0x248000\r
+    #else \r
+        .section        SECURITY_VECTORS, code, locate = 0x148000\r
+    #endif\r
+    \r
+    #if (BOOT_FLASH_SEC == OFF)        \r
+        .data.w 0xFFFFFFFF\r
+        .data.w 0xFFFFFFFF\r
+        .data.w 0xFFFFFFFF\r
+        .data.w 0xFFFFFFFF       \r
+    #else\r
+        .res.w          4\r
+    #endif         \r
+#endif     \r
+   \r
+#if CPLUSPLUS == ON\r
+        .section        EXT_CTOR_DTOR, const, align=4  ; C++ constructors\r
+#endif        \r
+       \r
+;-----------------------------------------------------------------------------------------\r
+; MACRO Clear RC Watchdog\r
+;-----------------------------------------------------------------------------------------\r
+#macro  ClearRCwatchdog\r
+        LDI             #0x4C7,R7               ; clear RC watchdog\r
+        BANDL           #0x7,@R7\r
+#endm\r
+;-----------------------------------------------------------------------------------------\r
+; MACRO WAIT_LOOP\r
+;-----------------------------------------------------------------------------------------\r
+#macro wait_loop loop_number\r
+#local _wait64_loop\r
+        LDI             #loop_number, R0\r
+_wait64_loop:\r
+        ADD             #-1, R0\r
+        BNE             _wait64_loop\r
+#endm\r
+        .section        CODE, code, align=4\r
+        .section        CODE_START, code, align=4\r
+\r
+\r
+;=========================================================================================\r
+; 7.  S T A R T \r
+;=========================================================================================\r
+__start:                                        ; start point   \r
+startnop: \r
+        NOP       \r
+;   \r
+        ANDCCR          #0xEF                   ; disable interrupts   \r
+        STILM           #LOW_PRIOR              ; set interrupt level to low prior\r
+        ClearRCwatchdog                         ; clear harware watchdog\r
+\r
+;=========================================================================================\r
+; 7.1  Initialise Stack Pointer and Table Base Register\r
+;=========================================================================================\r
+#if STACKUSE == SYSSTACK       \r
+        ORCCR           #0x20\r
+        LDI             #__userstack_top, SP    ; initialize SP\r
+        ANDCCR          #0xDF\r
+        LDI             #__systemstack_top, SP  ; initialize SP\r
+#endif\r
+\r
+#if STACKUSE == USRSTACK\r
+        ANDCCR          #0xDF\r
+        LDI             #__systemstack_top, SP  ; initialize SP\r
+        ORCCR           #0x20\r
+        LDI             #__userstack_top, SP    ; initialize SP\r
+#endif\r
+\r
+        LDI             #INTVECT, R0            ; set Table Base\r
+smd_tbr: \r
+        MOV             R0, TBR         \r
+\r
+#if (CLOCKSOURCE != NOCLOCK)                                          \r
+;=========================================================================================\r
+; 7.2  Check for CSV reset and set CSV\r
+;=========================================================================================\r
+; Start restriction; No clock supervisor (CSV)\r
+#if (DEVICE != MB91461R) && (DEVICE != MB91467R) && (DEVICE != MB91463N)\r
+; End restriction\r
+        LDI:20          #0x04AD, R0             ; CSVCR\r
+        BORL            #0x8, @R0               ; Enable Main Osc CSV\r
+        BTSTH           #0x4, @R0               ; Check for Main Osc missing\r
+        BEQ             NoMAINCSVreset          ; Main osc available -> branch \r
+                                                ;   to NoCSVreset\r
+        BANDL           #0x7, @R0               ; Disable Main Osc CSV\r
+        \r
+        LDI             #noClockStartup, R0     ; Main Clock missing -> no\r
+        JMP             @R0                     ; clock startup\r
+                                                \r
+NoMAINCSVreset: \r
+\r
+\r
+        BORL            #0x4, @R0               ; Enable Sub Osc CSV\r
+        BTSTH           #0x2, @R0               ; Check for Sub Osc missing\r
+        BEQ             NoSUBCSVreset           ; Sub osc available -> branch \r
+                                                ;   to NoCSVreset\r
+        BANDL           #0xB, @R0               ; Disable Sub Osc SCSV\r
+#if (CLOCKSOURCE == SUBCLOCK)\r
+        LDI             #noClockStartup, R0     ; Sub Clock missing -> no\r
+        JMP             @R0                     ; clock startup\r
+#endif                                                \r
+NoSUBCSVreset:       \r
+#endif        \r
+;=========================================================================================\r
+; 7.3  Check Clock Condition\r
+;=========================================================================================\r
+        LDI             #0x484, R0              ; Check for Default Values\r
+        LDI             #0x0F, R1               \r
+        ANDB            R1, @R0\r
+        BEQ             clock_startup \r
+\r
+;=========================================================================================\r
+; 7.4  Restore Default Settings after Reset\r
+;=========================================================================================\r
+;=========================================================================================\r
+; 7.4.1  Disable Clock Modulator\r
+;=========================================================================================\r
+        LDI             #0x04BB, R0             ; Clock Modulator Control Reg\r
+        BANDL           #0xD, @R0               ; Disable Frequency modulation\r
+FMODwait:        \r
+        BTSTL           #8, @R0                 ; Wait until Frequency modulation\r
+        BNE             FMODwait                ; is disabled\r
+        \r
+        BANDL           #0xE, @R0               ; Power down clock modulator\r
+\r
+;=========================================================================================\r
+; 7.4.2  Check if running on Sub Clock, change to Main Clock\r
+;=========================================================================================\r
+        LDI:20          #0x0484,R12             ; Check if running on sub clock\r
+        LDUB            @R12,R0\r
+        LDI:8           #0x3,R1\r
+        AND             R1,R0\r
+        CMP             #0x3,R0\r
+        BNE             notOnSubClock\r
+        \r
+        LDI:20          #0x04CC,R12             ; Check if Main Clock is stopped\r
+        BTSTL           #1, @R12\r
+        BEQ             mainNotStopped\r
+\r
+        BANDL           #0xE, @R12              ; Start Main Oscillation\r
+                        \r
+        LDI             #0x4C8, R0              ; Main Stabilisation Wait Time\r
+        LDI             #0x04, R1               ; 32.7 ms\r
+        AND             R1, @R0  \r
+        BORH            #0x02, @R0      \r
+        \r
+        mainStabTime:                           ; Wait for stabilisation time\r
+        ClearRCwatchdog                         ; clear harware watchdog\r
+        BTSTH           #8, @R0\r
+        BEQ             mainStabTime\r
+        LDI             #0x0, R1\r
+        STB             R1, @R0\r
+\r
+mainNotStopped:        \r
+        LDI:20          #0x0484, R12            ; disable sub clock as source\r
+        BANDL           #0xD, @R12              ; Clock source = 0x01 (Main/2)  \r
+                                                       \r
+notOnSubClock:\r
+;=========================================================================================\r
+; 7.4.3  Disable Sub Clock\r
+;=========================================================================================\r
+#if ENABLE_SUBCLOCK != ON\r
+        LDI             #0x0484, R0             ; Clock source control reg CLKR\r
+        BANDL           #0x7, @R0               ; Disable PLL\r
+#endif       \r
+\r
+;=========================================================================================\r
+; 7.4.4  Check if running on PLL, Gear Down PLL\r
+;=========================================================================================\r
+        LDI:20          #0x0484,R12             ; Check if running on PLL\r
+        LDUB            @R12,R0\r
+        LDI:8           #0x3,R1\r
+        AND             R1,R0\r
+        CMP             #0x2,R0\r
+        BNE             notOnPll\r
+                    \r
+        LDI:20          #0x0490, R11            ; clear flags  \r
+        LDI:8           #0x0,R1        \r
+        STB             R1, @R11\r
+        LDI             #0x04,R1\r
+        STB             R1, @R11                ; Set Flag for Simulator; no Effekt on\r
+                                                ; Emulator      \r
+\r
+        BANDL           #0xC, @R12              ; disable PLL as clock source  \r
+                                                ; Clock Source = 0x00 (Main/2)\r
+                                                    \r
+        LDI:20          #0x048E,R12             ; check if DivG != 0\r
+        LDUB            @R12, R0\r
+        LDI:8           #0xFF,R1\r
+        AND             R1,R0\r
+        BEQ             notOnPll\r
+                                                                                          \r
+gearDownLoop:    \r
+        ClearRCwatchdog                         ; clear harware watchdog\r
+        BTSTL           #4, @R11                ; Gear Down\r
+        BEQ             gearDownLoop            ; \r
+ \r
+        LDI             #0x00,R1                ; Clear Flags\r
+        STB             R1, @R11                ;       \r
+        \r
+notOnPll:\r
+;=========================================================================================\r
+; 7.4.5  Disable PLL\r
+;=========================================================================================\r
+        LDI             #0x0484, R0             ; Clock source control reg CLKR\r
+        BANDL           #0xB, @R0               ; Disable PLL\r
+        \r
+;=========================================================================================\r
+; 7.4.6  Set to Main Clock\r
+;=========================================================================================\r
+        LDI:20          #0x0484,R12             ; Check if running on PLL\r
+        BANDL           #0xC, @R12              ; disable PLL as clock source  \r
+                                                ; Clock Source = 0x00 (Main/2)\r
+\r
+clock_startup:\r
+;=========================================================================================\r
+; 7.5  Set Memory Controller\r
+;=========================================================================================\r
+; Start restriction; No embedded flash\r
+#if DEVICE != MB91461R\r
+; End restriction\r
+        LDI             #0x7002, R1             ; FLASH Controller Reg.\r
+        LDI             #FLASHCONTROL, R2       ; Flash Controller Settings\r
+        STH             R2, @R1                 ; set register\r
+        LDI             #0x7004, R1             ; FLASH Memory Wait Timing Reg.\r
+        LDI             #FLASHREADT, R2         ; wait settings\r
+        STH             R2, @R1                 ; set register\r
+        LDI             #0x7006, R1             ; FLASH Memory Wait Timing Reg.\r
+        LDI             #FLASHMWT2, R2          ; wait settings\r
+        STB             R2, @R1                 ; set register               \r
+#endif                \r
+        ClearRCwatchdog   \r
+                                                       \r
+;=========================================================================================\r
+; 7.6  Clock startup\r
+;=========================================================================================\r
+;=========================================================================================\r
+; 7.6.1  Set Voltage Regulator Settings\r
+;=========================================================================================\r
+; Start restriction; No regulator settings\r
+#if DEVICE != MB91461R\r
+; End restriction\r
+        LDI             #0x04CF, R0             ; REGCTR\r
+        LDI             #REGULATORCTRL, R1\r
+        STB             R1, @R0\r
+\r
+        LDI             #0x04CE, R0             ; REGSEL\r
+        LDI             #REGULATORSEL, R1\r
+        STB             R1, @R0\r
+#endif\r
+\r
+;=========================================================================================\r
+; 7.6.2  Power on Clock Modulator - Clock Modulator Part I\r
+;=========================================================================================\r
+#if CLOMO == ON \r
+        LDI             #0x04BB, R0             ; Clock Modulator Control Reg\r
+        LDI             #0x11, R1               ; Load value to Power on CM\r
+        ORB             R1, @R0                 ; Power on clock modulaor\r
+#endif\r
+\r
+;=========================================================================================\r
+; 7.6.3  Set CLKR Register w/o Clock Mode\r
+;=========================================================================================\r
+; Set Clock source (Base Clock) for the three clock tree selections\r
+; This select Base clock is used to select afterwards the 3\r
+; Clocks for the diffenrent internal trees.\r
+; When PLL is used, first pll multiplication ratio is set and PLL is\r
+; enabled. After waiting the PLL stabilisation time via timebase\r
+; timer, PLL clock is selected as clock source. \r
+        LDI             #0x048C, R0             ; PLL Cntl Reg. PLLDIVM/N\r
+        LDI:20          #PLLSPEED, R1\r
+        STH             R1, @R0\r
+\r
+        LDI             #0x048E, R0             ; PLL Cntl Reg. PLLDIVG\r
+        LDI             #DIV_G, R1\r
+        STB             R1, @R0\r
+\r
+        LDI             #0x048F, R0             ; PLL Cntl Reg. PLLMULG\r
+        LDI             #MUL_G, R1\r
+        STB             R1, @R0\r
+\r
+;=========================================================================================\r
+; 7.6.4  Start PLL \r
+;=========================================================================================\r
+#if ( ( CLOCKSOURCE == MAINPLLCLOCK ) || ( PSCLOCKSOURCE == PSCLOCK_PLL ) )\r
+        LDI             #0x0484, R0             ; Clock source control reg CLKR\r
+        LDI             #0x04, R1               ; Use PLL x1, enable PLL \r
+        ORB             R1, @R0                 ; store data to CLKR register\r
+#endif\r
+       \r
+       \r
+#if ENABLE_SUBCLOCK == ON\r
+        LDI             #0x0484, R0             ; Clock source control reg CLKR\r
+        LDI             #0x08, R1               ; enable subclock operation\r
+        ORB             R1, @R0                 ; store data to CLKR register\r
+        LDI             #0x4CA, R0              ; Sub Clock oszilation \r
+        LDI             #0x00, R1               ; stabilitsation time = 32 ms\r
+        AND             R1, @R0  \r
+        BORH            #0x02, @R0      \r
+#endif      \r
+      \r
+;=========================================================================================\r
+; 7.6.5  Wait for PLL oscillation stabilisation\r
+;=========================================================================================\r
+#if ((CLOCKSOURCE==MAINPLLCLOCK)||(PSCLOCKSOURCE==PSCLOCK_PLL))\r
+        LDI             #0x0482, R12            ; TimeBaseTimer TBCR\r
+        LDI             #0x00, R1               ; set 1024 us @ 2 MHz \r
+        STB             R1, @R12\r
+\r
+        BANDH           #7, @R12                ; clear interrupt flag\r
+        \r
+        LDI             #0x0483, R0             ; clearTimeBaseTimer CTBR\r
+        LDI             #0xA5, R1                 \r
+        STB             R1, @R0\r
+        LDI             #0x5A, R1                 \r
+        STB             R1, @R0\r
+        \r
+        BANDH           #7, @R12                ; clear interrupt flag\r
+        BORH            #8, @R12                ; set interrupt flag for simulator\r
+\r
+PLLwait:        \r
+        ClearRCwatchdog                         ; clear harware watchdog\r
+        BTSTH           #8, @R12\r
+        BEQ             PLLwait\r
+#endif\r
+\r
+;=========================================================================================\r
+; 7.6.6  Set clocks \r
+;=========================================================================================\r
+;=========================================================================================\r
+; 7.6.6.1  Set CPU and peripheral clock \r
+;=========================================================================================\r
+; CPU and peripheral clock are set in one register\r
+        LDI             #0x0486, R2             ; Set DIVR0 (CPU-clock (CLKB)  \r
+        LDI             #((CPUCLOCK << 4) + PERCLOCK), R3 ; Load CPU clock setting\r
+        STB             R3, @R2               \r
+;=========================================================================================\r
+; 7.6.6.2  Set External Bus interface clock\r
+;=========================================================================================\r
+; set External Bus clock\r
+; Be aware to do smooth clock setting, to avoid wrong clock setting\r
+; Take care, always write 0 to the lower 4 bits of DIVR1 register\r
+        LDI             #0x0487, R2             ; Set DIVR1  \r
+        LDI             #(EXTBUSCLOCK << 4), R3 ; Load Peripheral clock setting\r
+        STB             R3, @R2 \r
+        \r
+;=========================================================================================\r
+; 7.6.6.3  Set CAN clock prescaler\r
+;=========================================================================================\r
+; Set CAN Prescaler, only clock relevant parameter \r
+        LDI             #0x04C0, R0             ; Set CAN ClockParameter Register\r
+        LDI             #(PSCLOCKSOURCE + PSDVC), R1     ; Load Divider\r
+        STB             R1, @R0                          ; Set Divider\r
+; enable CAN clocks\r
+        LDI             #0x04c1, R0             ; Set CAN Clock enable Register\r
+        LDI             #CANCLOCK, R1           ; Load CANCLOCK\r
+        STB             R1, @R0                 ; set CANCLOCK\r
+\r
+;=========================================================================================\r
+; 7.6.6.4  Switch Main Clock Mode\r
+;=========================================================================================\r
+#if CLOCKSOURCE == MAINCLOCK\r
+\r
+;=========================================================================================\r
+; 7.6.6.5  Switch Subclock Mode\r
+;=========================================================================================\r
+#elif ( (CLOCKSOURCE == SUBCLOCK) )\r
+    #if ENABLE_SUBCLOCK == ON\r
+        LDI             #0x4CA, R12\r
+subStabTime:        \r
+        ClearRCwatchdog                         ; clear harware watchdog\r
+        BTSTH           #8, @R12                ; wait until sub clock stabilisation\r
+        BEQ             subStabTime             ; time is over\r
+        LDI             #0x0, R1\r
+        STB             R1, @R12\r
+\r
+        LDI             #0x0484, R0             ; Clock source control reg CLKR\r
+        LDI             #0x01, R1               ; load value to select main clock\r
+        ORB             R1, @R0                 ; enable main clock (1/2 external)        \r
+        LDI             #0x03, R1               ; load value to select subclock\r
+        ORB             R1, @R0                 ; enable subclock as clock source       \r
+    #else\r
+        #error: Wrong setting! The clock source is subclock, but the subclock is disabled.\r
+    #endif\r
+\r
+;=========================================================================================\r
+; 7.6.7  Switch to PLL Mode\r
+;=========================================================================================\r
+#elif ( (CLOCKSOURCE == MAINPLLCLOCK) )\r
+\r
+#if (DIV_G != 0x00)\r
+        LDI             #0x0490, R0             ; PLL Ctrl Register   \r
+        LDI             #0x00,R1\r
+        STB             R1, @R0                 ; Clear Flag\r
+        LDI             #0x01,R1\r
+        STB             R1, @R0                 ; Set Flag for Simulator; no Effekt on\r
+#endif                                                ; Emulator\r
+ \r
+        LDI             #0x0484, R3             ; Clock source control reg CLKR\r
+        BORL            #0x2, @R3               ; enable PLL as clock source                                               \r
+                                                \r
+#if (DIV_G != 0x00)                                                \r
+gearUpLoop:    \r
+        ClearRCwatchdog                         ; clear harware watchdog\r
+        LDUB            @R0, R2                 ; LOAD PLLCTR to R2\r
+        AND             R1, R2                  ; GRUP, counter reach 0\r
+        BEQ             gearUpLoop\r
+\r
+        LDI             #0x00,R1\r
+        STB             R1, @R0                 ; Clear Gear-Up Flag\r
+#endif         \r
+     \r
+#endif\r
+\r
+;=========================================================================================\r
+; 7.6.8  Enable Frequncy Modulation - Clock Modulator Part II\r
+;=========================================================================================\r
+#if CLOMO == ON                                 ; Only applicable if Modulator is on\r
+        LDI             #0x04B8, R0             ; Clock Modulation Parameter Reg\r
+        LDI             #CMPR, R1               ; Load CMP value\r
+        STH             R1, @R0                 ; Store CMP value in CMPR\r
+\r
+        LDI             #0x04BB, R0             ; Clock Modulator Control Reg\r
+        LDI             #0x13, R1               ; Load value to FM on CM\r
+        ORB             R1, @R0                 ; FM on \r
+#endif\r
+\r
+#endif\r
+noClockStartup:\r
+\r
+;=========================================================================================\r
+; 7.7  Set BusInterface\r
+;=========================================================================================\r
+; Start restriction; No ext. bus interface\r
+#if (DEVICE != MB91464A) && (DEVICE != MB91467C) && (DEVICE != MB91465K) &&  \\r
+    (DEVICE != MB91463N) && (DEVICE != MB91465X)\r
+; End restriction\r
+#if (EXTBUS == ON) \r
+;=========================================================================================\r
+; 7.7.1  Disable all CS\r
+;=========================================================================================\r
+; Start restriction; Flashless device\r
+#if(DEVICE != MB91461R)\r
+; End restriction\r
+        LDI             #0x0680, R3             ; chip select enable register CSER\r
+        LDI             #(0x00), R2             ; load disable settings                                                    \r
+smd_cs:                                                    \r
+        ANDB            R2, @R3                 ; set register          \r
+#endif        \r
+\r
+;=========================================================================================\r
+; 7.7.2  Clear TCR Register\r
+;=========================================================================================\r
+        LDI             #0x0683, R1             ; Pin/Timing Control Register TCR\r
+        BORH            #0x6,@R1                ; load timing settings \r
+\r
+;=========================================================================================\r
+; 7.7.3  Set CS0\r
+;=========================================================================================\r
+#if CS0\r
+        LDI             #0x0640, R1             ; area select reg ASR0, ACR0      \r
+        LDI             #(AREASEL0<<16)+CONFIGCS0, R0  ; load settings\r
+        ST              R0, @R1                 ; set registers\r
+ \r
+        LDI             #0x660, R1              ; area wait register awr0\r
+        LDI             #WAITREG0, R2           ; wait settings\r
+        STH             R2, @R1                 ; set register\r
+#endif\r
+\r
+;=========================================================================================\r
+; 7.7.4  Set CS1  \r
+;=========================================================================================\r
+#if CS1  \r
+        LDI             #0x0644, R1             ; area select reg ASR1, ACR1      \r
+        LDI             #(AREASEL1<<16)+CONFIGCS1, R0  ; load settings\r
+        ST              R0, @R1                 ; set registers\r
+\r
+        LDI             #0x662, R1              ; area wait register awr1\r
+        LDI             #WAITREG1, R2           ; wait settings\r
+        STH             R2, @R1                 ; set register\r
+#endif\r
+smd_cs_mb91461r:\r
+;=========================================================================================\r
+; 7.7.5  Set CS2  \r
+;=========================================================================================\r
+#if CS2\r
+        LDI             #0x0648, R1             ; area select reg ASR2, ACR2      \r
+        LDI             #(AREASEL2<<16)+CONFIGCS2, R0  ; load settings\r
+        ST              R0, @R1                 ; set registers\r
+        LDI             #0x664, R1              ; area wait register awr2\r
+        LDI             #WAITREG2, R2           ; wait settings\r
+        STH             R2, @R1                 ; set register\r
+#endif\r
+;=========================================================================================\r
+; 7.7.6  Set CS3  \r
+;=========================================================================================\r
+#if CS3\r
+        LDI             #0x064C, R1             ; area select reg ASR3, ACR3      \r
+        LDI             #(AREASEL3<<16)+CONFIGCS3, R0  ; load settings\r
+        ST              R0, @R1                 ; set registers\r
+        LDI             #0x666, R1              ; area wait register awr3\r
+        LDI             #WAITREG3, R2           ; wait settings\r
+        STH             R2, @R1                 ; set register\r
+#endif\r
+;=========================================================================================\r
+; 7.7.7  Set CS4  \r
+;=========================================================================================\r
+#if CS4\r
+        LDI             #0x0650, R1             ; area select reg ASR4, ACR4      \r
+        LDI             #(AREASEL4<<16)+CONFIGCS4, R0  ; load settings\r
+        ST              R0, @R1                 ; set registers\r
+        LDI             #0x668, R1              ; area wait register awr4\r
+        LDI             #WAITREG4, R2           ; wait settings\r
+        STH             R2, @R1                 ; set register\r
+#endif\r
+;=========================================================================================\r
+; 7.7.8  Set CS5  \r
+;=========================================================================================\r
+#if CS5\r
+        LDI             #0x0654, R1             ; area select reg ASR5, ACR5      \r
+        LDI             #(AREASEL5<<16)+CONFIGCS5, R0  ; load settings\r
+        ST              R0, @R1                 ; set registers\r
+        LDI             #0x66A, R1              ; area wait register awr5\r
+        LDI             #WAITREG5, R2           ; wait settings\r
+        STH             R2, @R1                 ; set register\r
+#endif\r
+;=========================================================================================\r
+; 7.7.9  Set CS6\r
+;=========================================================================================\r
+#if (CS6)  \r
+        LDI             #0x0658, R1             ; area select reg ASR6, ACR6      \r
+        LDI             #(AREASEL6<<16)+CONFIGCS6, R0  ; load settings\r
+        ST              R0, @R1                 ; set registers\r
+        LDI             #0x66C, R1              ; area wait register awr6\r
+        LDI             #WAITREG6, R2           ; wait settings\r
+        STH             R2, @R1                 ; set register\r
+#endif\r
+;=========================================================================================\r
+; 7.7.10  Set CS7  \r
+;=========================================================================================\r
+#if CS7\r
+        LDI             #0x065C, R1             ; area select reg ASR7, ACR7     \r
+        LDI             #(AREASEL7<<16)+CONFIGCS7, R0  ; load settings\r
+        ST              R0, @R1                 ; set registers\r
+        LDI             #0x66E, R1              ; area wait register awr7\r
+        LDI             #WAITREG7, R2           ; wait settings\r
+        STH             R2, @R1                 ; set register\r
+#endif             \r
+;=========================================================================================\r
+; 7.7.11  Set special SDRAM config register  \r
+;=========================================================================================\r
+#if (SDRAM)\r
+        LDI             #0x670, R1              ; SDRAM memory config register\r
+        LDI             #MEMCON, R2             ; wait settings\r
+        STB             R2, @R1                 ; set register\r
+#endif\r
+\r
+;=========================================================================================\r
+; 7.7.12  set Port Function Register\r
+;=========================================================================================\r
+;=========================================================================================\r
+; 7.7.12.1  set PFR00 Register. External bus mode (D[24-31]) or General purpose port\r
+;=========================================================================================\r
+        LDI             #0x0D80, R1             ; Port Function Register 0, (PFR00)\r
+        LDI             #PFUNC0, R0             ; load port settings \r
+        STB             R0, @R1                 ; set register    \r
+;=========================================================================================\r
+; 7.7.12.2  set PFR01 Register. External bus mode (D[16-23]) or General purpose port\r
+;=========================================================================================\r
+        LDI             #0x0D81, R1             ; Port Function Register 1, (PFR01)\r
+        LDI             #PFUNC1, R0             ; load port settings \r
+        STB             R0, @R1                 ; set register \r
+;=========================================================================================\r
+; 7.7.12.3  set PFR02 Register. External bus mode (D[8-15]) or General purpose port\r
+;=========================================================================================\r
+        LDI             #0x0D82, R1             ; Port Function Register 2, (PFR02)\r
+        LDI             #PFUNC2, R0             ; load port settings \r
+        STB             R0, @R1                 ; set register \r
+;=========================================================================================\r
+; 7.7.12.4  set PFR03 Register. External bus mode (D[0-7]) or General purpose port\r
+;=========================================================================================\r
+        LDI             #0x0D83, R1             ; Port Function Register 3, (PFR03)\r
+        LDI             #PFUNC3, R0             ; load port settings \r
+        STB             R0, @R1                 ; set register \r
+;=========================================================================================\r
+; 7.7.12.5  set PFR04 Register. External bus mode (Adr[24-31]) or General purpose port\r
+;=========================================================================================\r
+        LDI             #0x0D84, R1             ; Port Function Register 4, (PFR04)\r
+        LDI             #PFUNC4, R0             ; load port settings \r
+        STB             R0, @R1                 ; set register \r
+;=========================================================================================\r
+; 7.7.12.6  set PFR05 Register. External bus mode (Adr[16-23]) or General purpose port\r
+;=========================================================================================\r
+        LDI             #0x0D85, R1             ; Port Function Register 5, (PFR05)\r
+        LDI             #PFUNC5, R0             ; load port settings \r
+        STB             R0, @R1                 ; set register \r
+;=========================================================================================\r
+; 7.7.12.7  set PFR06 Register. External bus mode (Adr[8-15]) or General purpose port\r
+;=========================================================================================\r
+        LDI             #0x0D86, R1             ; Port Function Register 6, (PFR06)\r
+        LDI             #PFUNC6, R0             ; load port settings \r
+        STB             R0, @R1                 ; set register \r
+;=========================================================================================\r
+; 7.7.12.8  set PFR07 Register. External bus mode (Adr[0-7]) or General purpose port\r
+;=========================================================================================\r
+        LDI             #0x0D87, R1             ; Port Function Register 7, (PFR07)\r
+        LDI             #PFUNC7, R0             ; load port settings \r
+        STB             R0, @R1                 ; set register \r
+;=========================================================================================\r
+; 7.7.12.9  set PFR08 Register. External bus mode (Control Signals) or GIO port\r
+;=========================================================================================\r
+        LDI             #0x0D88, R1             ; Port Function Register 8, (PFR08)\r
+        LDI             #PFUNC8, R0             ; load port settings \r
+        STB             R0, @R1                 ; set register \r
+;=========================================================================================\r
+; 7.7.12.10  set PFR09 Register. External bus mode (Control Signals) or GIO port\r
+;=========================================================================================\r
+        LDI             #0x0D89, R1             ; Port Function Register 9, (PFR09)\r
+        LDI             #PFUNC9, R0             ; load port settings \r
+        STB             R0, @R1                 ; set register \r
+;=========================================================================================\r
+; 7.7.12.11  set PFR10 Register. External bus mode (Control Signals) or GIO port\r
+;=========================================================================================\r
+        LDI             #0x0D8A, R1             ; Port Function Register 10, (PFR10)\r
+        LDI             #PFUNC10, R0            ; load port settings \r
+        STB             R0, @R1                 ; set register \r
+;=========================================================================================\r
+; 7.7.12.12  set EPFR10 Register. External bus mode (Control Signals) or GIO port\r
+;=========================================================================================\r
+        LDI             #0x0DCA, R1             ; Extended PFR 10, (EPFR10)\r
+        LDI             #EPFUNC10, R0           ; load port settings \r
+        STB             R0, @R1                 ; set register \r
+;=========================================================================================\r
+; 7.7.13  Set TCR Register\r
+;=========================================================================================\r
+        LDI             #0x0683, R1             ; Pin/Timing Control Register TCR\r
+        LDI             #TIMECONTR, R0          ; load timing settings \r
+        STB             R0, @R1                 ; set register\r
+;=========================================================================================\r
+; 7.7.14  Enable CACHE for selected CS\r
+;=========================================================================================\r
+        LDI             #0x0681, R3             ; chip select enable register CSER\r
+        LDI             #CHEENA, R2 \r
+        ORB             R2, @R3      \r
+;=========================================================================================\r
+; 7.7.15 set SDRAM  Referesh Control Register\r
+;=========================================================================================\r
+#if (SDRAM)\r
+        LDI             #0x0684, R1             ; Refresh Control Register RCR\r
+        LDI             #REFRESH, R0            ; load refresh settings \r
+        STH             R0, @R1                 ; set register    \r
+        LDI             #0x0008, R2\r
+        OR              R2, R0                  ; Set PON bit to 1     \r
+        STH             R0, @R1                 ; set register \r
+#endif\r
+;=========================================================================================\r
+; 7.7.16  Enable used CS\r
+;=========================================================================================\r
+        LDI             #0x0680, R3             ; chip select enable register CSER\r
+        LDI             #ENACSX, R2 \r
+; Start restriction; Flashless device\r
+#if (DEVICE == MB91461R)\r
+; End restriction\r
+emu_sram_cs_mb91461r:    \r
+        ANDB            R2, @R3                 ; set register\r
+#else    \r
+        ORB             R2, @R3\r
+#endif   \r
+;=========================================================================================\r
+; 7.7.17  I-cache on/off\r
+;=========================================================================================\r
+; Start restriction; No cache\r
+#if (DEVICE == MB91461R) || (DEVICE == MB91469G) || (DEVICE == others)         \r
+; End restriction\r
+    #if CACHE\r
+        #if CACHE_SIZE  == C1024\r
+        LDI             #0x03C7, R1             ; Cache size register ISIZE\r
+        LDI             #0x00, R2\r
+        STB             R2, @R1\r
+        LDI             #0x03E7, R1             ; Cache control reg   ICHCR\r
+        LDI             #0x07, R2               ; Release entry locks, flush and enable \r
+        STB             R2, @R1                 ; cache  \r
+        #elif CACHE_SIZE  == C2048\r
+        LDI             #0x03C7, R1             ; Cache size register ISIZE\r
+        LDI             #0x01, R2\r
+        STB             R2, @R1\r
+        LDI             #0x03E7, R1             ; Cache control reg   ICHCR\r
+        LDI             #0x07, R2               ; Release entry locks, flush and enable \r
+        STB             R2, @R1                 ; cache\r
+        #elif CACHE_SIZE  == C4096\r
+        LDI             #0x03C7, R1             ; Cache size register ISIZE\r
+        LDI             #0x02, R2\r
+        STB             R2, @R1\r
+        LDI             #0x03E7, R1             ; Cache control reg   ICHCR\r
+        LDI             #0x07, R2               ; Release entry locks, flush and enable \r
+        STB             R2, @R1                 ; cache\r
+        #else    \r
+        #error: Wrong Cache size selected!\r
+        #endif          \r
+     #else\r
+        LDI             #0x03E7, R1             ; Cache control reg   ICHCR\r
+        LDI             #0x06, R2               ; Release entry locks, flush and disable\r
+        STB             R2, @R1                 ; cache\r
+    #endif\r
+#endif\r
+#elif (EXTBUS == OFF) \r
+;=========================================================================================\r
+; 7.7.18  set Port Function Register to general as I/O-Port\r
+;=========================================================================================\r
+;=========================================================================================\r
+; 7.7.18.1  set PFR00 Register. External bus mode as General purpose port\r
+;=========================================================================================\r
+        LDI             #0x0D80, R1             ; Port Function Register 0, (PFR00)\r
+        LDI             #0x00, R0               ; load port settings \r
+        STB             R0, @R1                 ; set register    \r
+;=========================================================================================\r
+; 7.7.18.2  set PFR01 Register. External bus mode as General purpose port\r
+;=========================================================================================\r
+        LDI             #0x0D81, R1             ; Port Function Register 1, (PFR01)\r
+        LDI             #0x00, R0               ; load port settings \r
+        STB             R0, @R1                 ; set register \r
+;=========================================================================================\r
+; 7.7.18.3  set PFR02 Register. External bus mode as General purpose port\r
+;=========================================================================================\r
+        LDI             #0x0D82, R1             ; Port Function Register 2, (PFR02)\r
+        LDI             #0x00, R0               ; load port settings \r
+        STB             R0, @R1                 ; set register \r
+;=========================================================================================\r
+; 7.7.18.4  set PFR03 Register. External bus mode as General purpose port\r
+;=========================================================================================\r
+        LDI             #0x0D83, R1             ; Port Function Register 3, (PFR03)\r
+        LDI             #0x00, R0               ; load port settings \r
+        STB             R0, @R1                 ; set register \r
+;=========================================================================================\r
+; 7.7.18.5  set PFR04 Register. External bus mode as General purpose port\r
+;=========================================================================================\r
+        LDI             #0x0D84, R1             ; Port Function Register 4, (PFR04)\r
+        LDI             #0x00, R0               ; load port settings \r
+        STB             R0, @R1                 ; set register \r
+;=========================================================================================\r
+; 7.7.18.6  set PFR05 Register. External bus mode as General purpose port\r
+;=========================================================================================\r
+        LDI             #0x0D85, R1             ; Port Function Register 5, (PFR05)\r
+        LDI             #0x00, R0               ; load port settings \r
+        STB             R0, @R1                 ; set register \r
+;=========================================================================================\r
+; 7.7.18.7  set PFR06 Register. External bus mode as General purpose port\r
+;=========================================================================================\r
+        LDI             #0x0D86, R1             ; Port Function Register 6, (PFR06)\r
+        LDI             #0x00, R0               ; load port settings \r
+        STB             R0, @R1                 ; set register \r
+;=========================================================================================\r
+; 7.7.18.8  set PFR07 Register. External bus mode as General purpose port\r
+;=========================================================================================\r
+        LDI             #0x0D87, R1             ; Port Function Register 7, (PFR07)\r
+        LDI             #0x00, R0               ; load port settings \r
+        STB             R0, @R1                 ; set register \r
+;=========================================================================================\r
+; 7.7.18.9  set PFR08 Register. External bus mode as General purpose port\r
+;=========================================================================================\r
+        LDI             #0x0D88, R1             ; Port Function Register 8, (PFR08)\r
+        LDI             #0x00, R0               ; load port settings \r
+        STB             R0, @R1                 ; set register \r
+;=========================================================================================\r
+; 7.7.18.10  set PFR09 Register. External bus mode as General purpose port\r
+;=========================================================================================\r
+        LDI             #0x0D89, R1             ; Port Function Register 9, (PFR09)\r
+        LDI             #0x00, R0               ; load port settings \r
+        STB             R0, @R1                 ; set register \r
+;=========================================================================================\r
+; 7.7.18.11  set PFR10 Register. External bus mode as General purpose port\r
+;=========================================================================================\r
+        LDI             #0x0D8A, R1             ; Port Function Register 10, (PFR10)\r
+        LDI             #0x00, R0               ; load port settings \r
+        STB             R0, @R1                 ; set register \r
+;=========================================================================================\r
+; 7.7.18.12  set EPFR10 Register. External bus mode as General purpose port\r
+;=========================================================================================\r
+        LDI             #0x0DCA, R1             ; Extended PFR10, (EPFR10)\r
+        LDI             #0x00, R0               ; load port settings \r
+        STB             R0, @R1                 ; set register \r
+;=========================================================================================\r
+\r
+#elif (EXTBUS == DEFAULT)\r
+        NOP\r
+smd_cs_mb91461r:\r
+emu_sram_cs_mb91461r:\r
+smd_cs:\r
+#endif                                          ; #endif (EXTBUS)\r
+#endif                                          ; #endif (excl. devices)\r
+        ClearRCwatchdog\r
+\r
+;=========================================================================================\r
+; 7.8  Copy code from Flash to I-RAM \r
+;=========================================================================================\r
+#if I_RAM == ON\r
+        LDI             #_RAM_IRAM, R0\r
+        LDI             #_ROM_IRAM, R1\r
+        LDI             #sizeof(IRAM), R13\r
+        CMP             #0, R13\r
+        BEQ             copy_iram_end\r
+copy_iram1: \r
+        ADD             #-1, R13\r
+        LDUB            @(R13, R1), R12\r
+        BNE:D           copy_iram1\r
+        STB             R12, @(R13, R0)\r
+copy_iram_end: \r
+        ClearRCwatchdog\r
+#endif\r
+\r
+;=========================================================================================\r
+; 7.9  Fill stacks\r
+;=========================================================================================\r
+#if STACK_FILL == ON\r
+        LDI             #STACK_PATTERN, R0\r
+        LDI             #SSTACK, R1\r
+        LDI             #sizeof(SSTACK), R2\r
+        CMP             #0, R2\r
+        BEQ:D           fill_sstack_end\r
+        MOV             R2, R13\r
+        LDI             #3, R12\r
+        AND             R2, R12\r
+        BEQ:D           fill_sstack2\r
+        MOV             R2, R3\r
+        SUB             R12, R3\r
+        LDI             #0x3, R4\r
+        SUB             R12, R4\r
+        LSL             #0x3, R4 \r
+        LDI             #STACK_PATTERN, R5\r
+        LSR             R4, R5 \r
+        LDI             #0x8, R4\r
+fill_sstack1:\r
+        ADD             #-1, R13\r
+        LSR             R4, R5 \r
+        CMP             R3, R13\r
+        BHI:D           fill_sstack1\r
+        STB             R5, @(R13, R1)\r
+        CMP             #0, R3\r
+        BEQ:D           fill_sstack_end\r
+fill_sstack2:\r
+        ADD             #-4, R13\r
+        BGT:D           fill_sstack2\r
+        ST              R0, @(R13, R1)\r
+fill_sstack_end:\r
+\r
+        LDI             #STACK_PATTERN, R0\r
+        LDI             #USTACK, R1\r
+        LDI             #sizeof(USTACK), R2\r
+        CMP             #0, R2\r
+        BEQ:D           fill_ustack_end\r
+        MOV             R2, R13\r
+        LDI             #3, R12\r
+        AND             R2, R12\r
+        BEQ:D           fill_ustack2\r
+        MOV             R2, R3\r
+        SUB             R12, R3\r
+        LDI             #0x3, R4\r
+        SUB             R12, R4\r
+        LSL             #0x3, R4 \r
+        LDI             #STACK_PATTERN, R5\r
+        LSR             R4, R5 \r
+        LDI             #0x8, R4\r
+fill_ustack1:\r
+        ADD             #-1, R13\r
+        LSR             R4, R5 \r
+        CMP             R3, R13\r
+        BHI:D           fill_ustack1\r
+        STB             R5, @(R13, R1)\r
+        CMP             #0, R3\r
+        BEQ:D           fill_ustack_end\r
+fill_ustack2:\r
+        ADD             #-4, R13\r
+        BGT:D           fill_ustack2\r
+        ST              R0, @(R13, R1)\r
+fill_ustack_end:\r
+        ClearRCwatchdog\r
+#endif \r
+\r
+;=========================================================================================\r
+; Standard C startup\r
+;=========================================================================================\r
+;=========================================================================================\r
+; 7.10  Clear data \r
+;=========================================================================================\r
+; clear DATA section\r
+; According to ANSI, the DATA section must be cleared during start-up\r
+        LDI:8           #0, R0\r
+        LDI             #sizeof DATA &~0x3, R1\r
+        LDI             #DATA, R13\r
+        CMP             #0, R1\r
+        BEQ             data_clr1\r
+data_clr0:\r
+        ADD2            #-4, R1\r
+        BNE:D           data_clr0\r
+        ST              R0, @(R13, R1)\r
+data_clr1:\r
+        LDI:8           #sizeof DATA & 0x3, R1\r
+        LDI             #DATA + (sizeof DATA & ~0x3), R13\r
+\r
+        CMP             #0, R1\r
+        BEQ             data_clr_end\r
+data_clr2:\r
+        ADD2            #-1, R1\r
+        BNE:D           data_clr2\r
+        STB             R0, @(R13, R1)\r
+data_clr_end:\r
+        ClearRCwatchdog\r
+        \r
+;=========================================================================================\r
+; 7.11  Copy Init section from ROM to RAM\r
+;=========================================================================================\r
+; copy rom\r
+; All initialised data's (e.g. int i=1) must be stored in ROM/FLASH area. \r
+; (start value)\r
+; The Application must copy the Section (Init) into the RAM area.\r
+        LDI             #_RAM_INIT, R0\r
+        LDI             #_ROM_INIT, R1\r
+        LDI             #sizeof(INIT), R2\r
+        CMP             #0, R2\r
+        BEQ:D           copy_rom_end\r
+        LDI             #3, R12\r
+        AND             R2, R12\r
+        BEQ:D           copy_rom2\r
+        MOV             R2, R13\r
+        MOV             R2, R3\r
+        SUB             R12, R3\r
+copy_rom1:\r
+        ADD             #-1, R13\r
+        LDUB            @(R13, R1), R12\r
+        CMP             R3, R13\r
+        BHI:D           copy_rom1\r
+        STB             R12, @(R13, R0)\r
+        CMP             #0, R3\r
+        BEQ:D           copy_rom_end\r
+copy_rom2:\r
+        ADD             #-4, R13\r
+        LD              @(R13, R1), R12\r
+        BGT:D           copy_rom2\r
+        ST              R12, @(R13, R0)\r
+copy_rom_end:\r
+        ClearRCwatchdog\r
+\r
+;=========================================================================================\r
+; 7.12 C library initialization\r
+;=========================================================================================\r
+#if CLIBINIT == ON\r
+       CALL32          __stream_init, r12         ; initialise library \r
+#endif\r
+;=========================================================================================\r
+; 7.13  call C++ constructors\r
+;=========================================================================================\r
+#if CPLUSPLUS == ON\r
+       LDI              #___call_dtors, r4\r
+       CALL32           _atexit, r12\r
+\r
+       LDI              #EXT_CTOR_DTOR, r8\r
+       LDI              #EXT_CTOR_DTOR + sizeof(EXT_CTOR_DTOR), r9\r
+       CMP              r9, r8\r
+       BEQ              L1\r
+L0:\r
+       LD               @r8, r10\r
+       CALL:D           @r10\r
+       ADD              #4, r8\r
+       CMP              r9, r8\r
+       BC               L0\r
+L1:\r
+#endif\r
+\r
+start_main:\r
+;=========================================================================================\r
+; 7.14  call main routine\r
+;=========================================================================================\r
+       ClearRCwatchdog                            ; clear harware watchdog\r
+       LDI:8            #0, r4                    ; Set the 1st parameter for main to 0.\r
+       CALL32:d         _main, r12\r
+       LDI:8            #0, r5                    ; Set the 2nd parameter for main to 0.\r
+#if CLIBINIT == ON\r
+       CALL32           _exit, r12\r
+       __exit:\r
+#endif\r
+\r
+#if CPLUSPLUS == ON\r
+       __abort:\r
+#endif\r
+\r
+;=========================================================================================\r
+; 7.15  Return from main function\r
+;=========================================================================================\r
+end: \r
+        BRA            end  \r
+        .end            __start\r
+        \r

diff --git a/Demo/MB91460_Softune/SRC/mb91467d.asm b/Demo/MB91460_Softune/SRC/mb91467d.asm
new file mode 100644 (file)
index 0000000..e7eb07a
--- /dev/null
+++ b/Demo/MB91460_Softune/SRC/mb91467d.asm
@@ -0,0 +1,14 @@
+/* THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */\r
+/* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */\r
+/* ELIGIBILITY FOR ANY PURPOSES.                                             */\r
+/*                 (C) Fujitsu Microelectronics Europe GmbH                  */\r
+/*---------------------------------------------------------------------------\r
+  mb91467d.asm\r
+\r
+\r
+            1.00   UMa    Initial Version\r
+-----------------------------------------------------------------------------*/\r
+\r
+\r
+#define __IO_DEFINE\r
+#include "mb91467d.h"\r

diff --git a/Demo/MB91460_Softune/SRC/mb91467d.h b/Demo/MB91460_Softune/SRC/mb91467d.h
new file mode 100644 (file)
index 0000000..7b2661f
--- /dev/null
+++ b/Demo/MB91460_Softune/SRC/mb91467d.h
@@ -0,0 +1,24806 @@
+/*  FR IO-MAP HEADER FILE      */\r
+/*  =====================      */\r
+/* CREATED BY IO-WIZARD V2.27    */\r
+/* THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU     */\r
+/* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR     */\r
+/* ELIGIBILITY FOR ANY PURPOSES.                                                 */\r
+/*                 (C) Fujitsu Microelectronics Europe GmbH                      */\r
+/*  */\r
+/* ************************************************************************* */\r
+/*                   Fujitsu Microelectronics Europe GmbH                        */\r
+/*                 http://emea.fujitsu.com/microelectronics  */\r
+/*                                                                           */\r
+/* THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */\r
+/* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */\r
+/* ELIGIBILITY FOR ANY PURPOSES                                              */\r
+/*                 (C) Fujitsu Microelectronics Europe GmbH                  */\r
+/* ************************************************************************* */\r
+/* ---------------------------------------------------------------------- */\r
+/* $Id: mb91467D.h,v 1.13 2007/08/08 10:56:26 mwilla Exp $ */\r
+/* ---------------------------------------------------------------------- */\r
+/*                      */\r
+/* Id: mb91467D.iow,v 1.1 2005/10/14 11:25:42 umarke Exp  */\r
+/*      - Initial Version based on mb91V460A, v1.1 */\r
+/* Id: mb91467D.iow,v 1.2 2005/10/14 09:47:18 umarke Exp   */\r
+/*      - Littel Endian IFxDTA_SWP_yz added     */\r
+/* Id: mb91467D.iow,v 1.3 2005/11/18 06:55:29 umarke Exp   */\r
+/*      - No. of port register reduced to the no. of registers in MB91467D */\r
+/*      - Registers added: FMWT2, FMCR */\r
+/*      - Addapted Bit Names of Register FMCS     */\r
+/* Id: mb91467D.iow,v 1.4 2005/11/18 06:55:29 umarke Exp   */\r
+/*      - OCS01 and OCS23 added         */\r
+/* Id: mb91467D.iow,v 1.6 2006/01/13 08:58:51 umarke Exp  */\r
+/*      - Bitnames of  CLKR changed                                                    */\r
+/* Id: mb91467D.iow,v 1.7 2006/01/26 15:42:05 umarke Exp   */\r
+/*      - REGSEL, BRPERx added */\r
+/*      - REGCTR added   */\r
+/*      - LVSEL added  */\r
+/*      - Old Bitname of CLKR added                             */\r
+/* Id: mb91467D.iow,v 1.8 2006/02/27 10:31:28 umarke Exp   */\r
+/*      - BGR10x und BGR00x added  */\r
+/*      - PCNx, ITBAx, ITMKx, IDARx_D7 added    */\r
+/*      - SGCRH, SGCRL added */\r
+/*      - Bit ACSR_MD added */\r
+/*      - Bit CSCFG_PLLLOCK and CSCFG_RCSEL          */\r
+/*      - CUCR: Bits shifted to correct position    */\r
+/*      - CUTR1 & CUTR2 bits renamed to TDR14 instead of TR14     */\r
+/*      - CMCR_RUN renamed to CMCR_FMODRUN and shifted               */\r
+/*      - Bitnames of OSCCx and OSCRx added */\r
+/*      - FSVx, BSVx and FSCRx added */\r
+/*      - RBSYNC, CBSYNCx  */\r
+/* Id: mb91467D.iow,v 1.9 2006/02/27 11:56:23 umarke Exp  */\r
+/*      - changed Adress of REGSEL */\r
+/* $Id: mb91467D.h,v 1.13 2007/08/08 10:56:26 mwilla Exp $  */\r
+/*      - Grouped CANPRE_CPCKS */\r
+/*      - Bitdescription of HLRC added */\r
+\r
+/* ASSEMBLER DEFINITIONS : */\r
+\r
+#ifdef  __IO_DEFINE\r
+#define __IO_EXTERN\r
+#else\r
+#define __IO_EXTERN    extern volatile\r
+#endif\r
+#ifdef __IO_DEFINE\r
+#pragma asm\r
+ .GLOBAL _pdr00,    _pdr01,    _pdr02,    _pdr03,    _pdr04,    _pdr05\r
+ .GLOBAL _pdr06,    _pdr07,    _pdr08,    _pdr09,    _pdr10,    _pdr13\r
+ .GLOBAL _pdr14,    _pdr15,    _pdr16,    _pdr17,    _pdr18,    _pdr19\r
+ .GLOBAL _pdr20,    _pdr22,    _pdr23,    _pdr24,    _pdr25,    _pdr26\r
+ .GLOBAL _pdr27,    _pdr29,    _eirr0,    _enir0,    _elvr0,    _eirr1\r
+ .GLOBAL _enir1,    _elvr1,    _dicr,     _hrcl,     _rbsync,   _scr02\r
+ .GLOBAL _smr02,    _ssr02,    _rdr02,    _tdr02,    _escr02,   _eccr02\r
+ .GLOBAL _scr04,    _smr04,    _ssr04,    _rdr04,    _tdr04,    _escr04\r
+ .GLOBAL _eccr04,   _fsr04,    _fcr04,    _scr05,    _smr05,    _ssr05\r
+ .GLOBAL _rdr05,    _tdr05,    _escr05,   _eccr05,   _fsr05,    _fcr05\r
+ .GLOBAL _scr06,    _smr06,    _ssr06,    _rdr06,    _tdr06,    _escr06\r
+ .GLOBAL _eccr06,   _fsr06,    _fcr06,    _scr07,    _smr07,    _ssr07\r
+ .GLOBAL _rdr07,    _tdr07,    _escr07,   _eccr07,   _fsr07,    _fcr07\r
+ .GLOBAL _bgr02,    _bgr102,   _bgr002,   _bgr04,    _bgr104,   _bgr004\r
+ .GLOBAL _bgr05,    _bgr105,   _bgr005,   _bgr06,    _bgr106,   _bgr006\r
+ .GLOBAL _bgr07,    _bgr107,   _bgr007,   _pwc20,    _pwc10,    _pws20\r
+ .GLOBAL _pws10,    _pwc21,    _pwc11,    _pws21,    _pws11,    _pwc22\r
+ .GLOBAL _pwc12,    _pws22,    _pws12,    _pwc23,    _pwc13,    _pws23\r
+ .GLOBAL _pws13,    _pwc24,    _pwc14,    _pws24,    _pws14,    _pwc25\r
+ .GLOBAL _pwc15,    _pws25,    _pws15,    _pwc0,     _pwc1,     _pwc2\r
+ .GLOBAL _pwc3,     _pwc4,     _pwc5,     _ibcr0,    _ibsr0,    _itba0\r
+ .GLOBAL _itbah0,   _itbal0,   _itmk0,    _itmkh0,   _itmkl0,   _ismk0\r
+ .GLOBAL _isba0,    _idar0,    _iccr0,    _gcn11,    _gcn21,    _gcn12\r
+ .GLOBAL _gcn22,    _ptmr04,   _pcsr04,   _pdut04,   _pcn04,    _pcnh04\r
+ .GLOBAL _pcnl04,   _ptmr05,   _pcsr05,   _pdut05,   _pcn05,    _pcnh05\r
+ .GLOBAL _pcnl05,   _ptmr06,   _pcsr06,   _pdut06,   _pcn06,    _pcnh06\r
+ .GLOBAL _pcnl06,   _ptmr07,   _pcsr07,   _pdut07,   _pcn07,    _pcnh07\r
+ .GLOBAL _pcnl07,   _ptmr08,   _pcsr08,   _pdut08,   _pcn08,    _pcnh08\r
+ .GLOBAL _pcnl08,   _ptmr09,   _pcsr09,   _pdut09,   _pcn09,    _pcnh09\r
+ .GLOBAL _pcnl09,   _ptmr10,   _pcsr10,   _pdut10,   _pcn10,    _pcnh10\r
+ .GLOBAL _pcnl10,   _ptmr11,   _pcsr11,   _pdut11,   _pcn11,    _pcnh11\r
+ .GLOBAL _pcnl11,   _p0tmcsr,  _p0tmcsrh, _p0tmcsrl, _p1tmcsr,  _p1tmcsrh\r
+ .GLOBAL _p1tmcsrl, _p0tmrlr,  _p0tmr,    _p1tmrlr,  _p1tmr,    _ics01\r
+ .GLOBAL _ics23,    _ipcp0,    _ipcp1,    _ipcp2,    _ipcp3,    _ocs01\r
+ .GLOBAL _ocs23,    _occp0,    _occp1,    _occp2,    _occp3,    _sgcr\r
+ .GLOBAL _sgcrh,    _sgcrl,    _sgfr,     _sgar,     _sgtr,     _sgdr\r
+ .GLOBAL _aderh,    _aderl,    _ader,     _adcs1,    _adcs0,    _adcs\r
+ .GLOBAL _adcr1,    _adcr0,    _adcr,     _adct1,    _adct0,    _adct\r
+ .GLOBAL _adsch,    _adech,    _acsr0,    _tmrlr0,   _tmr0,     _tmcsr0\r
+ .GLOBAL _tmcsrh0,  _tmcsrl0,  _tmrlr1,   _tmr1,     _tmcsr1,   _tmcsrh1\r
+ .GLOBAL _tmcsrl1,  _tmrlr2,   _tmr2,     _tmcsr2,   _tmcsrh2,  _tmcsrl2\r
+ .GLOBAL _tmrlr3,   _tmr3,     _tmcsr3,   _tmcsrh3,  _tmcsrl3,  _tmrlr4\r
+ .GLOBAL _tmr4,     _tmcsr4,   _tmcsrh4,  _tmcsrl4,  _tmrlr5,   _tmr5\r
+ .GLOBAL _tmcsr5,   _tmcsrh5,  _tmcsrl5,  _tmrlr6,   _tmr6,     _tmcsr6\r
+ .GLOBAL _tmcsrh6,  _tmcsrl6,  _tmrlr7,   _tmr7,     _tmcsr7,   _tmcsrh7\r
+ .GLOBAL _tmcsrl7,  _tcdt0,    _tccs0,    _tcdt1,    _tccs1,    _tcdt2\r
+ .GLOBAL _tccs2,    _tcdt3,    _tccs3,    _dmaca0,   _dmacb0,   _dmaca1\r
+ .GLOBAL _dmacb1,   _dmaca2,   _dmacb2,   _dmaca3,   _dmacb3,   _dmaca4\r
+ .GLOBAL _dmacb4,   _dmacr,    _ics45,    _ics67,    _ipcp4,    _ipcp5\r
+ .GLOBAL _ipcp6,    _ipcp7,    _tcdt4,    _tccs4,    _tcdt5,    _tccs5\r
+ .GLOBAL _tcdt6,    _tccs6,    _tcdt7,    _tccs7,    _udrc10,   _udrc1\r
+ .GLOBAL _udrc0,    _udcr10,   _udcr1,    _udcr0,    _udcc0,    _udcch0\r
+ .GLOBAL _udccl0,   _udcs0,    _udcc1,    _udcch1,   _udccl1,   _udcs1\r
+ .GLOBAL _udrc32,   _udrc3,    _udrc2,    _udcr32,   _udcr3,    _udcr2\r
+ .GLOBAL _udcc2,    _udcch2,   _udccl2,   _udcs2,    _udcc3,    _udcch3\r
+ .GLOBAL _udccl3,   _udcs3,    _gcn13,    _gcn23,    _ptmr12,   _pcsr12\r
+ .GLOBAL _pdut12,   _pcn12,    _pcnh12,   _pcnl12,   _ptmr13,   _pcsr13\r
+ .GLOBAL _pdut13,   _pcn13,    _pcnh13,   _pcnl13,   _ptmr14,   _pcsr14\r
+ .GLOBAL _pdut14,   _pcn14,    _pcnh14,   _pcnl14,   _ptmr15,   _pcsr15\r
+ .GLOBAL _pdut15,   _pcn15,    _pcnh15,   _pcnl15,   _ibcr2,    _ibsr2\r
+ .GLOBAL _itba2,    _itbah2,   _itbal2,   _itmk2,    _itmkh2,   _itmkl2\r
+ .GLOBAL _ismk2,    _isba2,    _idar2,    _iccr2,    _ibcr3,    _ibsr3\r
+ .GLOBAL _itba3,    _itbah3,   _itbal3,   _itmk3,    _itmkh3,   _itmkl3\r
+ .GLOBAL _ismk3,    _isba3,    _idar3,    _iccr3,    _roms,     _bsd0\r
+ .GLOBAL _bsd1,     _bsdc,     _bsrr,     _icr00,    _icr01,    _icr02\r
+ .GLOBAL _icr03,    _icr04,    _icr05,    _icr06,    _icr07,    _icr08\r
+ .GLOBAL _icr09,    _icr10,    _icr11,    _icr12,    _icr13,    _icr14\r
+ .GLOBAL _icr15,    _icr16,    _icr17,    _icr18,    _icr19,    _icr20\r
+ .GLOBAL _icr21,    _icr22,    _icr23,    _icr24,    _icr25,    _icr26\r
+ .GLOBAL _icr27,    _icr28,    _icr29,    _icr30,    _icr31,    _icr32\r
+ .GLOBAL _icr33,    _icr34,    _icr35,    _icr36,    _icr37,    _icr38\r
+ .GLOBAL _icr39,    _icr40,    _icr41,    _icr42,    _icr43,    _icr44\r
+ .GLOBAL _icr45,    _icr46,    _icr47,    _icr48,    _icr49,    _icr50\r
+ .GLOBAL _icr51,    _icr52,    _icr53,    _icr54,    _icr55,    _icr56\r
+ .GLOBAL _icr57,    _icr58,    _icr59,    _icr60,    _icr61,    _icr62\r
+ .GLOBAL _icr63,    _rsrr,     _stcr,     _tbcr,     _ctbr,     _clkr\r
+ .GLOBAL _wpr,      _divr0,    _divr1,    _plldivm,  _plldivn,  _plldivg\r
+ .GLOBAL _pllmulg,  _pllctrl,  _oscc1,    _oscs1,    _oscc2,    _oscs2\r
+ .GLOBAL _porten,   _wtcer,    _wtcr,     _wtbr,     _wthr,     _wtmr\r
+ .GLOBAL _wtsr,     _csvtr,    _csvcr,    _cscfg,    _cmcfg,    _cucr\r
+ .GLOBAL _cutd,     _cutr1,    _cutr2,    _cmpr,     _cmcr,     _cmt1\r
+ .GLOBAL _cmt2,     _canpre,   _canckd,   _lvsel,    _lvdet,    _hwwde\r
+ .GLOBAL _hwwd,     _oscrh,    _oscrl,    _wpcrh,    _wpcrl,    _osccr\r
+ .GLOBAL _regsel,   _regctr,   _asr0,     _acr0,     _asr1,     _acr1\r
+ .GLOBAL _asr2,     _acr2,     _asr3,     _acr3,     _asr4,     _acr4\r
+ .GLOBAL _asr5,     _acr5,     _asr6,     _acr6,     _asr7,     _acr7\r
+ .GLOBAL _awr0,     _awr1,     _awr2,     _awr3,     _awr4,     _awr5\r
+ .GLOBAL _awr6,     _awr7,     _mcra,     _mcrb,     _iowr0,    _iowr1\r
+ .GLOBAL _iowr2,    _iowr3,    _cser,     _cher,     _tcr,      _rcr\r
+ .GLOBAL _modr,     _pdrd00,   _pdrd01,   _pdrd02,   _pdrd03,   _pdrd04\r
+ .GLOBAL _pdrd05,   _pdrd06,   _pdrd07,   _pdrd08,   _pdrd09,   _pdrd10\r
+ .GLOBAL _pdrd13,   _pdrd14,   _pdrd15,   _pdrd16,   _pdrd17,   _pdrd18\r
+ .GLOBAL _pdrd19,   _pdrd20,   _pdrd22,   _pdrd23,   _pdrd24,   _pdrd25\r
+ .GLOBAL _pdrd26,   _pdrd27,   _pdrd29,   _ddr00,    _ddr01,    _ddr02\r
+ .GLOBAL _ddr03,    _ddr04,    _ddr05,    _ddr06,    _ddr07,    _ddr08\r
+ .GLOBAL _ddr09,    _ddr10,    _ddr13,    _ddr14,    _ddr15,    _ddr16\r
+ .GLOBAL _ddr17,    _ddr18,    _ddr19,    _ddr20,    _ddr22,    _ddr23\r
+ .GLOBAL _ddr24,    _ddr25,    _ddr26,    _ddr27,    _ddr29,    _pfr00\r
+ .GLOBAL _pfr01,    _pfr02,    _pfr03,    _pfr04,    _pfr05,    _pfr06\r
+ .GLOBAL _pfr07,    _pfr08,    _pfr09,    _pfr10,    _pfr13,    _pfr14\r
+ .GLOBAL _pfr15,    _pfr16,    _pfr17,    _pfr18,    _pfr19,    _pfr20\r
+ .GLOBAL _pfr22,    _pfr23,    _pfr24,    _pfr25,    _pfr26,    _pfr27\r
+ .GLOBAL _pfr29,    _epfr10,   _epfr13,   _epfr14,   _epfr15,   _epfr16\r
+ .GLOBAL _epfr18,   _epfr19,   _epfr20,   _epfr26,   _epfr27,   _podr00\r
+ .GLOBAL _podr01,   _podr02,   _podr03,   _podr04,   _podr05,   _podr06\r
+ .GLOBAL _podr07,   _podr08,   _podr09,   _podr10,   _podr13,   _podr14\r
+ .GLOBAL _podr15,   _podr16,   _podr17,   _podr18,   _podr19,   _podr20\r
+ .GLOBAL _podr22,   _podr23,   _podr24,   _podr25,   _podr26,   _podr27\r
+ .GLOBAL _podr29,   _pilr00,   _pilr01,   _pilr02,   _pilr03,   _pilr04\r
+ .GLOBAL _pilr05,   _pilr06,   _pilr07,   _pilr08,   _pilr09,   _pilr10\r
+ .GLOBAL _pilr13,   _pilr14,   _pilr15,   _pilr16,   _pilr17,   _pilr18\r
+ .GLOBAL _pilr19,   _pilr20,   _pilr22,   _pilr23,   _pilr24,   _pilr25\r
+ .GLOBAL _pilr26,   _pilr27,   _pilr29,   _epilr00,  _epilr01,  _epilr02\r
+ .GLOBAL _epilr03,  _epilr04,  _epilr05,  _epilr06,  _epilr07,  _epilr08\r
+ .GLOBAL _epilr09,  _epilr10,  _epilr13,  _epilr14,  _epilr15,  _epilr16\r
+ .GLOBAL _epilr17,  _epilr18,  _epilr19,  _epilr20,  _epilr22,  _epilr23\r
+ .GLOBAL _epilr24,  _epilr25,  _epilr26,  _epilr27,  _epilr29,  _pper00\r
+ .GLOBAL _pper01,   _pper02,   _pper03,   _pper04,   _pper05,   _pper06\r
+ .GLOBAL _pper07,   _pper08,   _pper09,   _pper10,   _pper13,   _pper14\r
+ .GLOBAL _pper15,   _pper16,   _pper17,   _pper18,   _pper19,   _pper20\r
+ .GLOBAL _pper22,   _pper23,   _pper24,   _pper25,   _pper26,   _pper27\r
+ .GLOBAL _pper29,   _ppcr00,   _ppcr01,   _ppcr02,   _ppcr03,   _ppcr04\r
+ .GLOBAL _ppcr05,   _ppcr06,   _ppcr07,   _ppcr08,   _ppcr09,   _ppcr10\r
+ .GLOBAL _ppcr13,   _ppcr14,   _ppcr15,   _ppcr16,   _ppcr17,   _ppcr18\r
+ .GLOBAL _ppcr19,   _ppcr20,   _ppcr22,   _ppcr23,   _ppcr24,   _ppcr25\r
+ .GLOBAL _ppcr26,   _ppcr27,   _ppcr29,   _dmasa0,   _dmada0,   _dmasa1\r
+ .GLOBAL _dmada1,   _dmasa2,   _dmada2,   _dmasa3,   _dmada3,   _dmasa4\r
+ .GLOBAL _dmada4,   _fmcs,     _fmcr,     _fchcr,    _fmwt,     _fmwt2\r
+ .GLOBAL _fmps,     _fmac,     _fcha0,    _fcha1,    _fscr0,    _fscr1\r
+ .GLOBAL _ctrlr0,   _statr0,   _errcnt0,  _btr0,     _intr0,    _testr0\r
+ .GLOBAL _brper0,   _brpe0,    _cbsync0,  _if1creq0, _if1cmsk0, _if1msk120\r
+ .GLOBAL _if1msk20, _if1msk10, _if1arb120, _if1arb20, _if1arb10, _if1mctr0\r
+ .GLOBAL _if1dta120, _if1dta10, _if1dta20, _if1dtb120, _if1dtb10, _if1dtb20\r
+ .GLOBAL _if1dta_swp120, _if1dta_swp20, _if1dta_swp10, _if1dtb_swp120, _if1dtb_swp20, _if1dtb_swp10\r
+ .GLOBAL _if2creq0, _if2cmsk0, _if2msk120, _if2msk20, _if2msk10, _if2arb120\r
+ .GLOBAL _if2arb20, _if2arb10, _if2mctr0, _if2dta120, _if2dta10, _if2dta20\r
+ .GLOBAL _if2dtb120, _if2dtb10, _if2dtb20, _if2dta_swp120, _if2dta_swp20, _if2dta_swp10\r
+ .GLOBAL _if2dtb_swp120, _if2dtb_swp20, _if2dtb_swp10, _treqr120, _treqr20,  _treqr10\r
+ .GLOBAL _newdt120, _newdt20,  _newdt10,  _intpnd120, _intpnd20, _intpnd10\r
+ .GLOBAL _msgval120, _msgval20, _msgval10, _msgval340, _ctrlr1,   _statr1\r
+ .GLOBAL _errcnt1,  _btr1,     _intr1,    _testr1,   _brper1,   _brpe1\r
+ .GLOBAL _cbsync1,  _if1creq1, _if1cmsk1, _if1msk121, _if1msk21, _if1msk11\r
+ .GLOBAL _if1arb121, _if1arb21, _if1arb11, _if1mctr1, _if1dta121, _if1dta11\r
+ .GLOBAL _if1dta21, _if1dtb121, _if1dtb11, _if1dtb21, _if1dta_swp121, _if1dta_swp21\r
+ .GLOBAL _if1dta_swp11, _if1dtb_swp121, _if1dtb_swp21, _if1dtb_swp11, _if2creq1, _if2cmsk1\r
+ .GLOBAL _if2msk121, _if2msk21, _if2msk11, _if2arb121, _if2arb21, _if2arb11\r
+ .GLOBAL _if2mctr1, _if2dta121, _if2dta11, _if2dta21, _if2dtb121, _if2dtb11\r
+ .GLOBAL _if2dtb21, _if2dta_swp121, _if2dta_swp21, _if2dta_swp11, _if2dtb_swp121, _if2dtb_swp21\r
+ .GLOBAL _if2dtb_swp11, _treqr121, _treqr21,  _treqr11,  _newdt121, _newdt21\r
+ .GLOBAL _newdt11,  _intpnd121, _intpnd21, _intpnd11, _msgval121, _msgval21\r
+ .GLOBAL _msgval11, _ctrlr2,   _statr2,   _errcnt2,  _btr2,     _intr2\r
+ .GLOBAL _testr2,   _brper2,   _brpe2,    _cbsync2,  _if1creq2, _if1cmsk2\r
+ .GLOBAL _if1msk122, _if1msk22, _if1msk12, _if1arb122, _if1arb22, _if1arb12\r
+ .GLOBAL _if1mctr2, _if1dta122, _if1dta12, _if1dta22, _if1dtb122, _if1dtb12\r
+ .GLOBAL _if1dtb22, _if1dta_swp122, _if1dta_swp22, _if1dta_swp12, _if1dtb_swp122, _if1dtb_swp22\r
+ .GLOBAL _if1dtb_swp12, _if2creq2, _if2cmsk2, _if2msk122, _if2msk22, _if2msk12\r
+ .GLOBAL _if2arb122, _if2arb22, _if2arb12, _if2mctr2, _if2dta122, _if2dta12\r
+ .GLOBAL _if2dta22, _if2dtb122, _if2dtb12, _if2dtb22, _if2dta_swp122, _if2dta_swp22\r
+ .GLOBAL _if2dta_swp12, _if2dtb_swp122, _if2dtb_swp22, _if2dtb_swp12, _treqr122, _treqr22\r
+ .GLOBAL _treqr12,  _newdt122, _newdt22,  _newdt12,  _intpnd122, _intpnd22\r
+ .GLOBAL _intpnd12, _msgval122, _msgval22, _msgval12, _bctrl,    _bstat\r
+ .GLOBAL _biac,     _boac,     _birq,     _bcr0,     _bcr1,     _bcr2\r
+ .GLOBAL _bcr3,     _bcr4,     _bcr5,     _bcr6,     _bcr7,     _bad0\r
+ .GLOBAL _bad1,     _bad2,     _bad3,     _bad4,     _bad5,     _bad6\r
+ .GLOBAL _bad7,     _bad8,     _bad9,     _bad10,    _bad11,    _bad12\r
+ .GLOBAL _bad13,    _bad14,    _bad15,    _fsv1,     _bsv1,     _fsv2\r
+ .GLOBAL _bsv2\r
+\r
+_pdr00     .EQU 0x000000\r
+PDR00      .EQU 0x000000 /* Port Data Register */\r
+_pdr01     .EQU 0x000001\r
+PDR01      .EQU 0x000001\r
+_pdr02     .EQU 0x000002\r
+PDR02      .EQU 0x000002\r
+_pdr03     .EQU 0x000003\r
+PDR03      .EQU 0x000003\r
+_pdr04     .EQU 0x000004\r
+PDR04      .EQU 0x000004\r
+_pdr05     .EQU 0x000005\r
+PDR05      .EQU 0x000005\r
+_pdr06     .EQU 0x000006\r
+PDR06      .EQU 0x000006\r
+_pdr07     .EQU 0x000007\r
+PDR07      .EQU 0x000007\r
+_pdr08     .EQU 0x000008\r
+PDR08      .EQU 0x000008\r
+_pdr09     .EQU 0x000009\r
+PDR09      .EQU 0x000009\r
+_pdr10     .EQU 0x00000A\r
+PDR10      .EQU 0x00000A\r
+_pdr13     .EQU 0x00000D\r
+PDR13      .EQU 0x00000D\r
+_pdr14     .EQU 0x00000E\r
+PDR14      .EQU 0x00000E\r
+_pdr15     .EQU 0x00000F\r
+PDR15      .EQU 0x00000F\r
+_pdr16     .EQU 0x000010\r
+PDR16      .EQU 0x000010\r
+_pdr17     .EQU 0x000011\r
+PDR17      .EQU 0x000011\r
+_pdr18     .EQU 0x000012\r
+PDR18      .EQU 0x000012\r
+_pdr19     .EQU 0x000013\r
+PDR19      .EQU 0x000013\r
+_pdr20     .EQU 0x000014\r
+PDR20      .EQU 0x000014\r
+_pdr22     .EQU 0x000016\r
+PDR22      .EQU 0x000016\r
+_pdr23     .EQU 0x000017\r
+PDR23      .EQU 0x000017\r
+_pdr24     .EQU 0x000018\r
+PDR24      .EQU 0x000018\r
+_pdr25     .EQU 0x000019\r
+PDR25      .EQU 0x000019\r
+_pdr26     .EQU 0x00001A\r
+PDR26      .EQU 0x00001A\r
+_pdr27     .EQU 0x00001B\r
+PDR27      .EQU 0x00001B\r
+_pdr29     .EQU 0x00001D\r
+PDR29      .EQU 0x00001D\r
+_eirr0     .EQU 0x000030\r
+EIRR0      .EQU 0x000030 /* External Interrupt 0-7 */\r
+_enir0     .EQU 0x000031\r
+ENIR0      .EQU 0x000031\r
+_elvr0     .EQU 0x000032\r
+ELVR0      .EQU 0x000032\r
+_eirr1     .EQU 0x000034\r
+EIRR1      .EQU 0x000034 /* External Interrupt 8-15 */\r
+_enir1     .EQU 0x000035\r
+ENIR1      .EQU 0x000035\r
+_elvr1     .EQU 0x000036\r
+ELVR1      .EQU 0x000036\r
+_dicr      .EQU 0x000038\r
+DICR       .EQU 0x000038 /* DLYI/I-unit */\r
+_hrcl      .EQU 0x000039\r
+HRCL       .EQU 0x000039\r
+_rbsync    .EQU 0x00003A\r
+RBSYNC     .EQU 0x00003A /* R-Bus Sync */\r
+_scr02     .EQU 0x000050\r
+SCR02      .EQU 0x000050 /* USART (LIN) 2 */\r
+_smr02     .EQU 0x000051\r
+SMR02      .EQU 0x000051\r
+_ssr02     .EQU 0x000052\r
+SSR02      .EQU 0x000052\r
+_rdr02     .EQU 0x000053\r
+RDR02      .EQU 0x000053\r
+_tdr02     .EQU 0x000053\r
+TDR02      .EQU 0x000053\r
+_escr02    .EQU 0x000054\r
+ESCR02     .EQU 0x000054\r
+_eccr02    .EQU 0x000055\r
+ECCR02     .EQU 0x000055\r
+_scr04     .EQU 0x000060\r
+SCR04      .EQU 0x000060 /* USART (LIN) 4 with FIFO */\r
+_smr04     .EQU 0x000061\r
+SMR04      .EQU 0x000061\r
+_ssr04     .EQU 0x000062\r
+SSR04      .EQU 0x000062\r
+_rdr04     .EQU 0x000063\r
+RDR04      .EQU 0x000063\r
+_tdr04     .EQU 0x000063\r
+TDR04      .EQU 0x000063\r
+_escr04    .EQU 0x000064\r
+ESCR04     .EQU 0x000064\r
+_eccr04    .EQU 0x000065\r
+ECCR04     .EQU 0x000065\r
+_fsr04     .EQU 0x000066\r
+FSR04      .EQU 0x000066\r
+_fcr04     .EQU 0x000067\r
+FCR04      .EQU 0x000067\r
+_scr05     .EQU 0x000068\r
+SCR05      .EQU 0x000068 /* USART (LIN) 5 with FIFO */\r
+_smr05     .EQU 0x000069\r
+SMR05      .EQU 0x000069\r
+_ssr05     .EQU 0x00006A\r
+SSR05      .EQU 0x00006A\r
+_rdr05     .EQU 0x00006B\r
+RDR05      .EQU 0x00006B\r
+_tdr05     .EQU 0x00006B\r
+TDR05      .EQU 0x00006B\r
+_escr05    .EQU 0x00006C\r
+ESCR05     .EQU 0x00006C\r
+_eccr05    .EQU 0x00006D\r
+ECCR05     .EQU 0x00006D\r
+_fsr05     .EQU 0x00006E\r
+FSR05      .EQU 0x00006E\r
+_fcr05     .EQU 0x00006F\r
+FCR05      .EQU 0x00006F\r
+_scr06     .EQU 0x000070\r
+SCR06      .EQU 0x000070 /* USART (LIN) 6 with FIFO */\r
+_smr06     .EQU 0x000071\r
+SMR06      .EQU 0x000071\r
+_ssr06     .EQU 0x000072\r
+SSR06      .EQU 0x000072\r
+_rdr06     .EQU 0x000073\r
+RDR06      .EQU 0x000073\r
+_tdr06     .EQU 0x000073\r
+TDR06      .EQU 0x000073\r
+_escr06    .EQU 0x000074\r
+ESCR06     .EQU 0x000074\r
+_eccr06    .EQU 0x000075\r
+ECCR06     .EQU 0x000075\r
+_fsr06     .EQU 0x000076\r
+FSR06      .EQU 0x000076\r
+_fcr06     .EQU 0x000077\r
+FCR06      .EQU 0x000077\r
+_scr07     .EQU 0x000078\r
+SCR07      .EQU 0x000078 /* USART (LIN) 7 with FIFO */\r
+_smr07     .EQU 0x000079\r
+SMR07      .EQU 0x000079\r
+_ssr07     .EQU 0x00007A\r
+SSR07      .EQU 0x00007A\r
+_rdr07     .EQU 0x00007B\r
+RDR07      .EQU 0x00007B\r
+_tdr07     .EQU 0x00007B\r
+TDR07      .EQU 0x00007B\r
+_escr07    .EQU 0x00007C\r
+ESCR07     .EQU 0x00007C\r
+_eccr07    .EQU 0x00007D\r
+ECCR07     .EQU 0x00007D\r
+_fsr07     .EQU 0x00007E\r
+FSR07      .EQU 0x00007E\r
+_fcr07     .EQU 0x00007F\r
+FCR07      .EQU 0x00007F\r
+_bgr02     .EQU 0x000084\r
+BGR02      .EQU 0x000084 /* Bauderate Generator USART (LIN) 2,4-7 */\r
+_bgr102    .EQU 0x000084\r
+BGR102     .EQU 0x000084\r
+_bgr002    .EQU 0x000085\r
+BGR002     .EQU 0x000085\r
+_bgr04     .EQU 0x000088\r
+BGR04      .EQU 0x000088\r
+_bgr104    .EQU 0x000088\r
+BGR104     .EQU 0x000088\r
+_bgr004    .EQU 0x000089\r
+BGR004     .EQU 0x000089\r
+_bgr05     .EQU 0x00008A\r
+BGR05      .EQU 0x00008A\r
+_bgr105    .EQU 0x00008A\r
+BGR105     .EQU 0x00008A\r
+_bgr005    .EQU 0x00008B\r
+BGR005     .EQU 0x00008B\r
+_bgr06     .EQU 0x00008C\r
+BGR06      .EQU 0x00008C\r
+_bgr106    .EQU 0x00008C\r
+BGR106     .EQU 0x00008C\r
+_bgr006    .EQU 0x00008D\r
+BGR006     .EQU 0x00008D\r
+_bgr07     .EQU 0x00008E\r
+BGR07      .EQU 0x00008E\r
+_bgr107    .EQU 0x00008E\r
+BGR107     .EQU 0x00008E\r
+_bgr007    .EQU 0x00008F\r
+BGR007     .EQU 0x00008F\r
+_pwc20     .EQU 0x000090\r
+PWC20      .EQU 0x000090 /* Stepper Motor 0 */\r
+_pwc10     .EQU 0x000092\r
+PWC10      .EQU 0x000092\r
+_pws20     .EQU 0x000096\r
+PWS20      .EQU 0x000096\r
+_pws10     .EQU 0x000097\r
+PWS10      .EQU 0x000097\r
+_pwc21     .EQU 0x000098\r
+PWC21      .EQU 0x000098 /* Stepper Motor 1 */\r
+_pwc11     .EQU 0x00009A\r
+PWC11      .EQU 0x00009A\r
+_pws21     .EQU 0x00009E\r
+PWS21      .EQU 0x00009E\r
+_pws11     .EQU 0x00009F\r
+PWS11      .EQU 0x00009F\r
+_pwc22     .EQU 0x0000A0\r
+PWC22      .EQU 0x0000A0 /* Stepper Motor 2 */\r
+_pwc12     .EQU 0x0000A2\r
+PWC12      .EQU 0x0000A2\r
+_pws22     .EQU 0x0000A6\r
+PWS22      .EQU 0x0000A6\r
+_pws12     .EQU 0x0000A7\r
+PWS12      .EQU 0x0000A7\r
+_pwc23     .EQU 0x0000A8\r
+PWC23      .EQU 0x0000A8 /* Stepper Motor 3 */\r
+_pwc13     .EQU 0x0000AA\r
+PWC13      .EQU 0x0000AA\r
+_pws23     .EQU 0x0000AE\r
+PWS23      .EQU 0x0000AE\r
+_pws13     .EQU 0x0000AF\r
+PWS13      .EQU 0x0000AF\r
+_pwc24     .EQU 0x0000B0\r
+PWC24      .EQU 0x0000B0 /* Stepper Motor 4 */\r
+_pwc14     .EQU 0x0000B2\r
+PWC14      .EQU 0x0000B2\r
+_pws24     .EQU 0x0000B6\r
+PWS24      .EQU 0x0000B6\r
+_pws14     .EQU 0x0000B7\r
+PWS14      .EQU 0x0000B7\r
+_pwc25     .EQU 0x0000B8\r
+PWC25      .EQU 0x0000B8 /* Stepper Motor 5 */\r
+_pwc15     .EQU 0x0000BA\r
+PWC15      .EQU 0x0000BA\r
+_pws25     .EQU 0x0000BE\r
+PWS25      .EQU 0x0000BE\r
+_pws15     .EQU 0x0000BF\r
+PWS15      .EQU 0x0000BF\r
+_pwc0      .EQU 0x0000C1\r
+PWC0       .EQU 0x0000C1 /* Stepper Motor Control 0-5 */\r
+_pwc1      .EQU 0x0000C3\r
+PWC1       .EQU 0x0000C3\r
+_pwc2      .EQU 0x0000C5\r
+PWC2       .EQU 0x0000C5\r
+_pwc3      .EQU 0x0000C7\r
+PWC3       .EQU 0x0000C7\r
+_pwc4      .EQU 0x0000C9\r
+PWC4       .EQU 0x0000C9\r
+_pwc5      .EQU 0x0000CB\r
+PWC5       .EQU 0x0000CB\r
+_ibcr0     .EQU 0x0000D0\r
+IBCR0      .EQU 0x0000D0 /* I2C 0 */\r
+_ibsr0     .EQU 0x0000D1\r
+IBSR0      .EQU 0x0000D1\r
+_itba0     .EQU 0x0000D2\r
+ITBA0      .EQU 0x0000D2\r
+_itbah0    .EQU 0x0000D2\r
+ITBAH0     .EQU 0x0000D2\r
+_itbal0    .EQU 0x0000D3\r
+ITBAL0     .EQU 0x0000D3\r
+_itmk0     .EQU 0x0000D4\r
+ITMK0      .EQU 0x0000D4\r
+_itmkh0    .EQU 0x0000D4\r
+ITMKH0     .EQU 0x0000D4\r
+_itmkl0    .EQU 0x0000D5\r
+ITMKL0     .EQU 0x0000D5\r
+_ismk0     .EQU 0x0000D6\r
+ISMK0      .EQU 0x0000D6\r
+_isba0     .EQU 0x0000D7\r
+ISBA0      .EQU 0x0000D7\r
+_idar0     .EQU 0x0000D9\r
+IDAR0      .EQU 0x0000D9\r
+_iccr0     .EQU 0x0000DA\r
+ICCR0      .EQU 0x0000DA\r
+_gcn11     .EQU 0x000104\r
+GCN11      .EQU 0x000104 /* PPG Control 4-7 */\r
+_gcn21     .EQU 0x000107\r
+GCN21      .EQU 0x000107\r
+_gcn12     .EQU 0x000108\r
+GCN12      .EQU 0x000108 /* PPG Control 8-11 */\r
+_gcn22     .EQU 0x00010B\r
+GCN22      .EQU 0x00010B\r
+_ptmr04    .EQU 0x000130\r
+PTMR04     .EQU 0x000130 /* PPG 4 */\r
+_pcsr04    .EQU 0x000132\r
+PCSR04     .EQU 0x000132\r
+_pdut04    .EQU 0x000134\r
+PDUT04     .EQU 0x000134\r
+_pcn04     .EQU 0x000136\r
+PCN04      .EQU 0x000136\r
+_pcnh04    .EQU 0x000136\r
+PCNH04     .EQU 0x000136\r
+_pcnl04    .EQU 0x000137\r
+PCNL04     .EQU 0x000137\r
+_ptmr05    .EQU 0x000138\r
+PTMR05     .EQU 0x000138 /* PPG 5 */\r
+_pcsr05    .EQU 0x00013A\r
+PCSR05     .EQU 0x00013A\r
+_pdut05    .EQU 0x00013C\r
+PDUT05     .EQU 0x00013C\r
+_pcn05     .EQU 0x00013E\r
+PCN05      .EQU 0x00013E\r
+_pcnh05    .EQU 0x00013E\r
+PCNH05     .EQU 0x00013E\r
+_pcnl05    .EQU 0x00013F\r
+PCNL05     .EQU 0x00013F\r
+_ptmr06    .EQU 0x000140\r
+PTMR06     .EQU 0x000140 /* PPG 6 */\r
+_pcsr06    .EQU 0x000142\r
+PCSR06     .EQU 0x000142\r
+_pdut06    .EQU 0x000144\r
+PDUT06     .EQU 0x000144\r
+_pcn06     .EQU 0x000146\r
+PCN06      .EQU 0x000146\r
+_pcnh06    .EQU 0x000146\r
+PCNH06     .EQU 0x000146\r
+_pcnl06    .EQU 0x000147\r
+PCNL06     .EQU 0x000147\r
+_ptmr07    .EQU 0x000148\r
+PTMR07     .EQU 0x000148 /* PPG 7 */\r
+_pcsr07    .EQU 0x00014A\r
+PCSR07     .EQU 0x00014A\r
+_pdut07    .EQU 0x00014C\r
+PDUT07     .EQU 0x00014C\r
+_pcn07     .EQU 0x00014E\r
+PCN07      .EQU 0x00014E\r
+_pcnh07    .EQU 0x00014E\r
+PCNH07     .EQU 0x00014E\r
+_pcnl07    .EQU 0x00014F\r
+PCNL07     .EQU 0x00014F\r
+_ptmr08    .EQU 0x000150\r
+PTMR08     .EQU 0x000150 /* PPG 8 */\r
+_pcsr08    .EQU 0x000152\r
+PCSR08     .EQU 0x000152\r
+_pdut08    .EQU 0x000154\r
+PDUT08     .EQU 0x000154\r
+_pcn08     .EQU 0x000156\r
+PCN08      .EQU 0x000156\r
+_pcnh08    .EQU 0x000156\r
+PCNH08     .EQU 0x000156\r
+_pcnl08    .EQU 0x000157\r
+PCNL08     .EQU 0x000157\r
+_ptmr09    .EQU 0x000158\r
+PTMR09     .EQU 0x000158 /* PPG 9 */\r
+_pcsr09    .EQU 0x00015A\r
+PCSR09     .EQU 0x00015A\r
+_pdut09    .EQU 0x00015C\r
+PDUT09     .EQU 0x00015C\r
+_pcn09     .EQU 0x00015E\r
+PCN09      .EQU 0x00015E\r
+_pcnh09    .EQU 0x00015E\r
+PCNH09     .EQU 0x00015E\r
+_pcnl09    .EQU 0x00015F\r
+PCNL09     .EQU 0x00015F\r
+_ptmr10    .EQU 0x000160\r
+PTMR10     .EQU 0x000160 /* PPG 10 */\r
+_pcsr10    .EQU 0x000162\r
+PCSR10     .EQU 0x000162\r
+_pdut10    .EQU 0x000164\r
+PDUT10     .EQU 0x000164\r
+_pcn10     .EQU 0x000166\r
+PCN10      .EQU 0x000166\r
+_pcnh10    .EQU 0x000166\r
+PCNH10     .EQU 0x000166\r
+_pcnl10    .EQU 0x000167\r
+PCNL10     .EQU 0x000167\r
+_ptmr11    .EQU 0x000168\r
+PTMR11     .EQU 0x000168 /* PPG 11 */\r
+_pcsr11    .EQU 0x00016A\r
+PCSR11     .EQU 0x00016A\r
+_pdut11    .EQU 0x00016C\r
+PDUT11     .EQU 0x00016C\r
+_pcn11     .EQU 0x00016E\r
+PCN11      .EQU 0x00016E\r
+_pcnh11    .EQU 0x00016E\r
+PCNH11     .EQU 0x00016E\r
+_pcnl11    .EQU 0x00016F\r
+PCNL11     .EQU 0x00016F\r
+_p0tmcsr   .EQU 0x000170\r
+P0TMCSR    .EQU 0x000170 /* Pulse Frequency Modulator (PFM) */\r
+_p0tmcsrh  .EQU 0x000170\r
+P0TMCSRH   .EQU 0x000170\r
+_p0tmcsrl  .EQU 0x000171\r
+P0TMCSRL   .EQU 0x000171\r
+_p1tmcsr   .EQU 0x000172\r
+P1TMCSR    .EQU 0x000172\r
+_p1tmcsrh  .EQU 0x000172\r
+P1TMCSRH   .EQU 0x000172\r
+_p1tmcsrl  .EQU 0x000173\r
+P1TMCSRL   .EQU 0x000173\r
+_p0tmrlr   .EQU 0x000174\r
+P0TMRLR    .EQU 0x000174\r
+_p0tmr     .EQU 0x000176\r
+P0TMR      .EQU 0x000176\r
+_p1tmrlr   .EQU 0x000178\r
+P1TMRLR    .EQU 0x000178\r
+_p1tmr     .EQU 0x00017A\r
+P1TMR      .EQU 0x00017A\r
+_ics01     .EQU 0x000181\r
+ICS01      .EQU 0x000181 /* Input Capture 0-3 */\r
+_ics23     .EQU 0x000183\r
+ICS23      .EQU 0x000183\r
+_ipcp0     .EQU 0x000184\r
+IPCP0      .EQU 0x000184\r
+_ipcp1     .EQU 0x000186\r
+IPCP1      .EQU 0x000186\r
+_ipcp2     .EQU 0x000188\r
+IPCP2      .EQU 0x000188\r
+_ipcp3     .EQU 0x00018A\r
+IPCP3      .EQU 0x00018A\r
+_ocs01     .EQU 0x00018C\r
+OCS01      .EQU 0x00018C /* Output Compare 0-3 */\r
+_ocs23     .EQU 0x00018E\r
+OCS23      .EQU 0x00018E\r
+_occp0     .EQU 0x000190\r
+OCCP0      .EQU 0x000190\r
+_occp1     .EQU 0x000192\r
+OCCP1      .EQU 0x000192\r
+_occp2     .EQU 0x000194\r
+OCCP2      .EQU 0x000194\r
+_occp3     .EQU 0x000196\r
+OCCP3      .EQU 0x000196\r
+_sgcr      .EQU 0x000198\r
+SGCR       .EQU 0x000198 /* Sound Generator */\r
+_sgcrh     .EQU 0x000198\r
+SGCRH      .EQU 0x000198\r
+_sgcrl     .EQU 0x000199\r
+SGCRL      .EQU 0x000199\r
+_sgfr      .EQU 0x00019A\r
+SGFR       .EQU 0x00019A\r
+_sgar      .EQU 0x00019C\r
+SGAR       .EQU 0x00019C\r
+_sgtr      .EQU 0x00019E\r
+SGTR       .EQU 0x00019E\r
+_sgdr      .EQU 0x00019F\r
+SGDR       .EQU 0x00019F\r
+_aderh     .EQU 0x0001A0\r
+ADERH      .EQU 0x0001A0 /* ADC */\r
+_aderl     .EQU 0x0001A2\r
+ADERL      .EQU 0x0001A2\r
+_ader  .EQU 0x0001A0\r
+ADER   .EQU 0x0001A0\r
+_adcs1     .EQU 0x0001A4\r
+ADCS1      .EQU 0x0001A4\r
+_adcs0     .EQU 0x0001A5\r
+ADCS0      .EQU 0x0001A5\r
+_adcs  .EQU 0x0001A4\r
+ADCS   .EQU 0x0001A4\r
+_adcr1     .EQU 0x0001A6\r
+ADCR1      .EQU 0x0001A6\r
+_adcr0     .EQU 0x0001A7\r
+ADCR0      .EQU 0x0001A7\r
+_adcr  .EQU 0x0001A6\r
+ADCR   .EQU 0x0001A6\r
+_adct1     .EQU 0x0001A8\r
+ADCT1      .EQU 0x0001A8\r
+_adct0     .EQU 0x0001A9\r
+ADCT0      .EQU 0x0001A9\r
+_adct  .EQU 0x0001A8\r
+ADCT   .EQU 0x0001A8\r
+_adsch     .EQU 0x0001AA\r
+ADSCH      .EQU 0x0001AA\r
+_adech     .EQU 0x0001AB\r
+ADECH      .EQU 0x0001AB\r
+_acsr0     .EQU 0x0001AD\r
+ACSR0      .EQU 0x0001AD /* Alarm Comparator 0-1 */\r
+_tmrlr0    .EQU 0x0001B0\r
+TMRLR0     .EQU 0x0001B0 /* Reload Timer 0 */\r
+_tmr0      .EQU 0x0001B2\r
+TMR0       .EQU 0x0001B2\r
+_tmcsr0    .EQU 0x0001B6\r
+TMCSR0     .EQU 0x0001B6\r
+_tmcsrh0  .EQU 0x0001B6\r
+TMCSRH0   .EQU 0x0001B6\r
+_tmcsrl0  .EQU 0x0001B7\r
+TMCSRL0   .EQU 0x0001B7\r
+_tmrlr1    .EQU 0x0001B8\r
+TMRLR1     .EQU 0x0001B8 /* Reload Timer 1 */\r
+_tmr1      .EQU 0x0001BA\r
+TMR1       .EQU 0x0001BA\r
+_tmcsr1    .EQU 0x0001BE\r
+TMCSR1     .EQU 0x0001BE\r
+_tmcsrh1  .EQU 0x0001BE\r
+TMCSRH1   .EQU 0x0001BE\r
+_tmcsrl1  .EQU 0x0001BF\r
+TMCSRL1   .EQU 0x0001BF\r
+_tmrlr2    .EQU 0x0001C0\r
+TMRLR2     .EQU 0x0001C0 /* Reload Timer 2 */\r
+_tmr2      .EQU 0x0001C2\r
+TMR2       .EQU 0x0001C2\r
+_tmcsr2    .EQU 0x0001C6\r
+TMCSR2     .EQU 0x0001C6\r
+_tmcsrh2  .EQU 0x0001C6\r
+TMCSRH2   .EQU 0x0001C6\r
+_tmcsrl2  .EQU 0x0001C7\r
+TMCSRL2   .EQU 0x0001C7\r
+_tmrlr3    .EQU 0x0001C8\r
+TMRLR3     .EQU 0x0001C8 /* Reload Timer 3 */\r
+_tmr3      .EQU 0x0001CA\r
+TMR3       .EQU 0x0001CA\r
+_tmcsr3    .EQU 0x0001CE\r
+TMCSR3     .EQU 0x0001CE\r
+_tmcsrh3  .EQU 0x0001CE\r
+TMCSRH3   .EQU 0x0001CE\r
+_tmcsrl3  .EQU 0x0001CF\r
+TMCSRL3   .EQU 0x0001CF\r
+_tmrlr4    .EQU 0x0001D0\r
+TMRLR4     .EQU 0x0001D0 /* Reload Timer 4 */\r
+_tmr4      .EQU 0x0001D2\r
+TMR4       .EQU 0x0001D2\r
+_tmcsr4    .EQU 0x0001D6\r
+TMCSR4     .EQU 0x0001D6\r
+_tmcsrh4  .EQU 0x0001D6\r
+TMCSRH4   .EQU 0x0001D6\r
+_tmcsrl4  .EQU 0x0001D7\r
+TMCSRL4   .EQU 0x0001D7\r
+_tmrlr5    .EQU 0x0001D8\r
+TMRLR5     .EQU 0x0001D8 /* Reload Timer 5 */\r
+_tmr5      .EQU 0x0001DA\r
+TMR5       .EQU 0x0001DA\r
+_tmcsr5    .EQU 0x0001DE\r
+TMCSR5     .EQU 0x0001DE\r
+_tmcsrh5  .EQU 0x0001DE\r
+TMCSRH5   .EQU 0x0001DE\r
+_tmcsrl5  .EQU 0x0001DF\r
+TMCSRL5   .EQU 0x0001DF\r
+_tmrlr6    .EQU 0x0001E0\r
+TMRLR6     .EQU 0x0001E0 /* Reload Timer 6 */\r
+_tmr6      .EQU 0x0001E2\r
+TMR6       .EQU 0x0001E2\r
+_tmcsr6    .EQU 0x0001E6\r
+TMCSR6     .EQU 0x0001E6\r
+_tmcsrh6  .EQU 0x0001E6\r
+TMCSRH6   .EQU 0x0001E6\r
+_tmcsrl6  .EQU 0x0001E7\r
+TMCSRL6   .EQU 0x0001E7\r
+_tmrlr7    .EQU 0x0001E8\r
+TMRLR7     .EQU 0x0001E8 /* Reload Timer 7 */\r
+_tmr7      .EQU 0x0001EA\r
+TMR7       .EQU 0x0001EA\r
+_tmcsr7    .EQU 0x0001EE\r
+TMCSR7     .EQU 0x0001EE\r
+_tmcsrh7  .EQU 0x0001EE\r
+TMCSRH7   .EQU 0x0001EE\r
+_tmcsrl7  .EQU 0x0001EF\r
+TMCSRL7   .EQU 0x0001EF\r
+_tcdt0     .EQU 0x0001F0\r
+TCDT0      .EQU 0x0001F0 /* Free Running Timer0 */\r
+_tccs0     .EQU 0x0001F3\r
+TCCS0      .EQU 0x0001F3\r
+_tcdt1     .EQU 0x0001F4\r
+TCDT1      .EQU 0x0001F4 /* Free Running Timer1 */\r
+_tccs1     .EQU 0x0001F7\r
+TCCS1      .EQU 0x0001F7\r
+_tcdt2     .EQU 0x0001F8\r
+TCDT2      .EQU 0x0001F8 /* Free Running Timer2 */\r
+_tccs2     .EQU 0x0001FB\r
+TCCS2      .EQU 0x0001FB\r
+_tcdt3     .EQU 0x0001FC\r
+TCDT3      .EQU 0x0001FC /* Free Running Timer3 */\r
+_tccs3     .EQU 0x0001FF\r
+TCCS3      .EQU 0x0001FF\r
+_dmaca0    .EQU 0x000200\r
+DMACA0     .EQU 0x000200 /* DMAC */\r
+_dmacb0    .EQU 0x000204\r
+DMACB0     .EQU 0x000204\r
+_dmaca1    .EQU 0x000208\r
+DMACA1     .EQU 0x000208\r
+_dmacb1    .EQU 0x00020C\r
+DMACB1     .EQU 0x00020C\r
+_dmaca2    .EQU 0x000210\r
+DMACA2     .EQU 0x000210\r
+_dmacb2    .EQU 0x000214\r
+DMACB2     .EQU 0x000214\r
+_dmaca3    .EQU 0x000218\r
+DMACA3     .EQU 0x000218\r
+_dmacb3    .EQU 0x00021C\r
+DMACB3     .EQU 0x00021C\r
+_dmaca4    .EQU 0x000220\r
+DMACA4     .EQU 0x000220\r
+_dmacb4    .EQU 0x000224\r
+DMACB4     .EQU 0x000224\r
+_dmacr     .EQU 0x000240\r
+DMACR      .EQU 0x000240\r
+_ics45     .EQU 0x0002D1\r
+ICS45      .EQU 0x0002D1 /* Input Capture 4-7 */\r
+_ics67     .EQU 0x0002D3\r
+ICS67      .EQU 0x0002D3\r
+_ipcp4     .EQU 0x0002D4\r
+IPCP4      .EQU 0x0002D4\r
+_ipcp5     .EQU 0x0002D6\r
+IPCP5      .EQU 0x0002D6\r
+_ipcp6     .EQU 0x0002D8\r
+IPCP6      .EQU 0x0002D8\r
+_ipcp7     .EQU 0x0002DA\r
+IPCP7      .EQU 0x0002DA\r
+_tcdt4     .EQU 0x0002F0\r
+TCDT4      .EQU 0x0002F0 /* Free Running Timer4 */\r
+_tccs4     .EQU 0x0002F3\r
+TCCS4      .EQU 0x0002F3\r
+_tcdt5     .EQU 0x0002F4\r
+TCDT5      .EQU 0x0002F4 /* Free Running Timer5 */\r
+_tccs5     .EQU 0x0002F7\r
+TCCS5      .EQU 0x0002F7\r
+_tcdt6     .EQU 0x0002F8\r
+TCDT6      .EQU 0x0002F8 /* Free Running Timer6 */\r
+_tccs6     .EQU 0x0002FB\r
+TCCS6      .EQU 0x0002FB\r
+_tcdt7     .EQU 0x0002FC\r
+TCDT7      .EQU 0x0002FC /* Free Running Timer7 */\r
+_tccs7     .EQU 0x0002FF\r
+TCCS7      .EQU 0x0002FF\r
+_udrc10    .EQU 0x000300\r
+UDRC10     .EQU 0x000300 /* Up/Down Counter 0-1 */\r
+_udrc1     .EQU 0x000300\r
+UDRC1      .EQU 0x000300\r
+_udrc0     .EQU 0x000301\r
+UDRC0      .EQU 0x000301\r
+_udcr10    .EQU 0x000302\r
+UDCR10     .EQU 0x000302\r
+_udcr1     .EQU 0x000302\r
+UDCR1      .EQU 0x000302\r
+_udcr0     .EQU 0x000303\r
+UDCR0      .EQU 0x000303\r
+_udcc0     .EQU 0x000304\r
+UDCC0      .EQU 0x000304\r
+_udcch0  .EQU 0x000304\r
+UDCCH0   .EQU 0x000304\r
+_udccl0  .EQU 0x000305\r
+UDCCL0   .EQU 0x000305\r
+_udcs0     .EQU 0x000307\r
+UDCS0      .EQU 0x000307\r
+_udcc1     .EQU 0x000308\r
+UDCC1      .EQU 0x000308\r
+_udcch1  .EQU 0x000308\r
+UDCCH1   .EQU 0x000308\r
+_udccl1  .EQU 0x000309\r
+UDCCL1   .EQU 0x000309\r
+_udcs1     .EQU 0x00030B\r
+UDCS1      .EQU 0x00030B\r
+_udrc32    .EQU 0x000310\r
+UDRC32     .EQU 0x000310 /* Up/Down Counter 2-3 */\r
+_udrc3     .EQU 0x000310\r
+UDRC3      .EQU 0x000310\r
+_udrc2     .EQU 0x000311\r
+UDRC2      .EQU 0x000311\r
+_udcr32    .EQU 0x000312\r
+UDCR32     .EQU 0x000312\r
+_udcr3     .EQU 0x000312\r
+UDCR3      .EQU 0x000312\r
+_udcr2     .EQU 0x000313\r
+UDCR2      .EQU 0x000313\r
+_udcc2     .EQU 0x000314\r
+UDCC2      .EQU 0x000314\r
+_udcch2  .EQU 0x000314\r
+UDCCH2   .EQU 0x000314\r
+_udccl2  .EQU 0x000315\r
+UDCCL2   .EQU 0x000315\r
+_udcs2     .EQU 0x000317\r
+UDCS2      .EQU 0x000317\r
+_udcc3     .EQU 0x000318\r
+UDCC3      .EQU 0x000318\r
+_udcch3  .EQU 0x000318\r
+UDCCH3   .EQU 0x000318\r
+_udccl3  .EQU 0x000319\r
+UDCCL3   .EQU 0x000319\r
+_udcs3     .EQU 0x00031B\r
+UDCS3      .EQU 0x00031B\r
+_gcn13     .EQU 0x000320\r
+GCN13      .EQU 0x000320 /* PPG Control 12-15 */\r
+_gcn23     .EQU 0x000323\r
+GCN23      .EQU 0x000323\r
+_ptmr12    .EQU 0x000330\r
+PTMR12     .EQU 0x000330 /* PPG 12 */\r
+_pcsr12    .EQU 0x000332\r
+PCSR12     .EQU 0x000332\r
+_pdut12    .EQU 0x000334\r
+PDUT12     .EQU 0x000334\r
+_pcn12     .EQU 0x000336\r
+PCN12      .EQU 0x000336\r
+_pcnh12    .EQU 0x000336\r
+PCNH12     .EQU 0x000336\r
+_pcnl12    .EQU 0x000337\r
+PCNL12     .EQU 0x000337\r
+_ptmr13    .EQU 0x000338\r
+PTMR13     .EQU 0x000338 /* PPG 13 */\r
+_pcsr13    .EQU 0x00033A\r
+PCSR13     .EQU 0x00033A\r
+_pdut13    .EQU 0x00033C\r
+PDUT13     .EQU 0x00033C\r
+_pcn13     .EQU 0x00033E\r
+PCN13      .EQU 0x00033E\r
+_pcnh13    .EQU 0x00033E\r
+PCNH13     .EQU 0x00033E\r
+_pcnl13    .EQU 0x00033F\r
+PCNL13     .EQU 0x00033F\r
+_ptmr14    .EQU 0x000340\r
+PTMR14     .EQU 0x000340 /* PPG 14 */\r
+_pcsr14    .EQU 0x000342\r
+PCSR14     .EQU 0x000342\r
+_pdut14    .EQU 0x000344\r
+PDUT14     .EQU 0x000344\r
+_pcn14     .EQU 0x000346\r
+PCN14      .EQU 0x000346\r
+_pcnh14    .EQU 0x000346\r
+PCNH14     .EQU 0x000346\r
+_pcnl14    .EQU 0x000347\r
+PCNL14     .EQU 0x000347\r
+_ptmr15    .EQU 0x000348\r
+PTMR15     .EQU 0x000348 /* PPG 15 */\r
+_pcsr15    .EQU 0x00034A\r
+PCSR15     .EQU 0x00034A\r
+_pdut15    .EQU 0x00034C\r
+PDUT15     .EQU 0x00034C\r
+_pcn15     .EQU 0x00034E\r
+PCN15      .EQU 0x00034E\r
+_pcnh15    .EQU 0x00034E\r
+PCNH15     .EQU 0x00034E\r
+_pcnl15    .EQU 0x00034F\r
+PCNL15     .EQU 0x00034F\r
+_ibcr2     .EQU 0x000368\r
+IBCR2      .EQU 0x000368 /* I2C 2 */\r
+_ibsr2     .EQU 0x000369\r
+IBSR2      .EQU 0x000369\r
+_itba2     .EQU 0x00036A\r
+ITBA2      .EQU 0x00036A\r
+_itbah2    .EQU 0x00036A\r
+ITBAH2     .EQU 0x00036A\r
+_itbal2    .EQU 0x00036B\r
+ITBAL2     .EQU 0x00036B\r
+_itmk2     .EQU 0x00036C\r
+ITMK2      .EQU 0x00036C\r
+_itmkh2    .EQU 0x00036C\r
+ITMKH2     .EQU 0x00036C\r
+_itmkl2    .EQU 0x00036D\r
+ITMKL2     .EQU 0x00036D\r
+_ismk2     .EQU 0x00036E\r
+ISMK2      .EQU 0x00036E\r
+_isba2     .EQU 0x00036F\r
+ISBA2      .EQU 0x00036F\r
+_idar2     .EQU 0x000371\r
+IDAR2      .EQU 0x000371\r
+_iccr2     .EQU 0x000372\r
+ICCR2      .EQU 0x000372\r
+_ibcr3     .EQU 0x000374\r
+IBCR3      .EQU 0x000374 /* I2C 3 */\r
+_ibsr3     .EQU 0x000375\r
+IBSR3      .EQU 0x000375\r
+_itba3     .EQU 0x000376\r
+ITBA3      .EQU 0x000376\r
+_itbah3    .EQU 0x000376\r
+ITBAH3     .EQU 0x000376\r
+_itbal3    .EQU 0x000377\r
+ITBAL3     .EQU 0x000377\r
+_itmk3     .EQU 0x000378\r
+ITMK3      .EQU 0x000378\r
+_itmkh3    .EQU 0x000378\r
+ITMKH3     .EQU 0x000378\r
+_itmkl3    .EQU 0x000379\r
+ITMKL3     .EQU 0x000379\r
+_ismk3     .EQU 0x00037A\r
+ISMK3      .EQU 0x00037A\r
+_isba3     .EQU 0x00037B\r
+ISBA3      .EQU 0x00037B\r
+_idar3     .EQU 0x00037D\r
+IDAR3      .EQU 0x00037D\r
+_iccr3     .EQU 0x00037E\r
+ICCR3      .EQU 0x00037E\r
+_roms      .EQU 0x000390\r
+ROMS       .EQU 0x000390 /* ROM Select Register */\r
+_bsd0      .EQU 0x0003F0\r
+BSD0       .EQU 0x0003F0 /* Bit Search Module */\r
+_bsd1      .EQU 0x0003F4\r
+BSD1       .EQU 0x0003F4\r
+_bsdc      .EQU 0x0003F8\r
+BSDC       .EQU 0x0003F8\r
+_bsrr      .EQU 0x0003FC\r
+BSRR       .EQU 0x0003FC\r
+_icr00     .EQU 0x000440\r
+ICR00      .EQU 0x000440 /* Interrupt Control Unit */\r
+_icr01     .EQU 0x000441\r
+ICR01      .EQU 0x000441\r
+_icr02     .EQU 0x000442\r
+ICR02      .EQU 0x000442\r
+_icr03     .EQU 0x000443\r
+ICR03      .EQU 0x000443\r
+_icr04     .EQU 0x000444\r
+ICR04      .EQU 0x000444\r
+_icr05     .EQU 0x000445\r
+ICR05      .EQU 0x000445\r
+_icr06     .EQU 0x000446\r
+ICR06      .EQU 0x000446\r
+_icr07     .EQU 0x000447\r
+ICR07      .EQU 0x000447\r
+_icr08     .EQU 0x000448\r
+ICR08      .EQU 0x000448\r
+_icr09     .EQU 0x000449\r
+ICR09      .EQU 0x000449\r
+_icr10     .EQU 0x00044A\r
+ICR10      .EQU 0x00044A\r
+_icr11     .EQU 0x00044B\r
+ICR11      .EQU 0x00044B\r
+_icr12     .EQU 0x00044C\r
+ICR12      .EQU 0x00044C\r
+_icr13     .EQU 0x00044D\r
+ICR13      .EQU 0x00044D\r
+_icr14     .EQU 0x00044E\r
+ICR14      .EQU 0x00044E\r
+_icr15     .EQU 0x00044F\r
+ICR15      .EQU 0x00044F\r
+_icr16     .EQU 0x000450\r
+ICR16      .EQU 0x000450\r
+_icr17     .EQU 0x000451\r
+ICR17      .EQU 0x000451\r
+_icr18     .EQU 0x000452\r
+ICR18      .EQU 0x000452\r
+_icr19     .EQU 0x000453\r
+ICR19      .EQU 0x000453\r
+_icr20     .EQU 0x000454\r
+ICR20      .EQU 0x000454\r
+_icr21     .EQU 0x000455\r
+ICR21      .EQU 0x000455\r
+_icr22     .EQU 0x000456\r
+ICR22      .EQU 0x000456\r
+_icr23     .EQU 0x000457\r
+ICR23      .EQU 0x000457\r
+_icr24     .EQU 0x000458\r
+ICR24      .EQU 0x000458\r
+_icr25     .EQU 0x000459\r
+ICR25      .EQU 0x000459\r
+_icr26     .EQU 0x00045A\r
+ICR26      .EQU 0x00045A\r
+_icr27     .EQU 0x00045B\r
+ICR27      .EQU 0x00045B\r
+_icr28     .EQU 0x00045C\r
+ICR28      .EQU 0x00045C\r
+_icr29     .EQU 0x00045D\r
+ICR29      .EQU 0x00045D\r
+_icr30     .EQU 0x00045E\r
+ICR30      .EQU 0x00045E\r
+_icr31     .EQU 0x00045F\r
+ICR31      .EQU 0x00045F\r
+_icr32     .EQU 0x000460\r
+ICR32      .EQU 0x000460\r
+_icr33     .EQU 0x000461\r
+ICR33      .EQU 0x000461\r
+_icr34     .EQU 0x000462\r
+ICR34      .EQU 0x000462\r
+_icr35     .EQU 0x000463\r
+ICR35      .EQU 0x000463\r
+_icr36     .EQU 0x000464\r
+ICR36      .EQU 0x000464\r
+_icr37     .EQU 0x000465\r
+ICR37      .EQU 0x000465\r
+_icr38     .EQU 0x000466\r
+ICR38      .EQU 0x000466\r
+_icr39     .EQU 0x000467\r
+ICR39      .EQU 0x000467\r
+_icr40     .EQU 0x000468\r
+ICR40      .EQU 0x000468\r
+_icr41     .EQU 0x000469\r
+ICR41      .EQU 0x000469\r
+_icr42     .EQU 0x00046A\r
+ICR42      .EQU 0x00046A\r
+_icr43     .EQU 0x00046B\r
+ICR43      .EQU 0x00046B\r
+_icr44     .EQU 0x00046C\r
+ICR44      .EQU 0x00046C\r
+_icr45     .EQU 0x00046D\r
+ICR45      .EQU 0x00046D\r
+_icr46     .EQU 0x00046E\r
+ICR46      .EQU 0x00046E\r
+_icr47     .EQU 0x00046F\r
+ICR47      .EQU 0x00046F\r
+_icr48     .EQU 0x000470\r
+ICR48      .EQU 0x000470\r
+_icr49     .EQU 0x000471\r
+ICR49      .EQU 0x000471\r
+_icr50     .EQU 0x000472\r
+ICR50      .EQU 0x000472\r
+_icr51     .EQU 0x000473\r
+ICR51      .EQU 0x000473\r
+_icr52     .EQU 0x000474\r
+ICR52      .EQU 0x000474\r
+_icr53     .EQU 0x000475\r
+ICR53      .EQU 0x000475\r
+_icr54     .EQU 0x000476\r
+ICR54      .EQU 0x000476\r
+_icr55     .EQU 0x000477\r
+ICR55      .EQU 0x000477\r
+_icr56     .EQU 0x000478\r
+ICR56      .EQU 0x000478\r
+_icr57     .EQU 0x000479\r
+ICR57      .EQU 0x000479\r
+_icr58     .EQU 0x00047A\r
+ICR58      .EQU 0x00047A\r
+_icr59     .EQU 0x00047B\r
+ICR59      .EQU 0x00047B\r
+_icr60     .EQU 0x00047C\r
+ICR60      .EQU 0x00047C\r
+_icr61     .EQU 0x00047D\r
+ICR61      .EQU 0x00047D\r
+_icr62     .EQU 0x00047E\r
+ICR62      .EQU 0x00047E\r
+_icr63     .EQU 0x00047F\r
+ICR63      .EQU 0x00047F\r
+_rsrr      .EQU 0x000480\r
+RSRR       .EQU 0x000480 /* Clock Control Unit */\r
+_stcr      .EQU 0x000481\r
+STCR       .EQU 0x000481\r
+_tbcr      .EQU 0x000482\r
+TBCR       .EQU 0x000482\r
+_ctbr      .EQU 0x000483\r
+CTBR       .EQU 0x000483\r
+_clkr      .EQU 0x000484\r
+CLKR       .EQU 0x000484\r
+_wpr       .EQU 0x000485\r
+WPR        .EQU 0x000485\r
+_divr0     .EQU 0x000486\r
+DIVR0      .EQU 0x000486\r
+_divr1     .EQU 0x000487\r
+DIVR1      .EQU 0x000487\r
+_plldivm   .EQU 0x00048C\r
+PLLDIVM    .EQU 0x00048C /* PLL - Clock Gear Unit: */\r
+_plldivn   .EQU 0x00048D\r
+PLLDIVN    .EQU 0x00048D\r
+_plldivg   .EQU 0x00048E\r
+PLLDIVG    .EQU 0x00048E\r
+_pllmulg   .EQU 0x00048F\r
+PLLMULG    .EQU 0x00048F\r
+_pllctrl   .EQU 0x000490\r
+PLLCTRL    .EQU 0x000490\r
+_oscc1     .EQU 0x000494\r
+OSCC1      .EQU 0x000494 /* Main/Sub Oscillator Control */\r
+_oscs1     .EQU 0x000495\r
+OSCS1      .EQU 0x000495\r
+_oscc2     .EQU 0x000496\r
+OSCC2      .EQU 0x000496\r
+_oscs2     .EQU 0x000497\r
+OSCS2      .EQU 0x000497\r
+_porten  .EQU 0x000498\r
+PORTEN   .EQU 0x000498 /* Port Input Enable Control */\r
+_wtcer     .EQU 0x0004A1\r
+WTCER      .EQU 0x0004A1 /* Real Time Clock (Watch Timer) */\r
+_wtcr      .EQU 0x0004A2\r
+WTCR       .EQU 0x0004A2\r
+_wtbr      .EQU 0x0004A4\r
+WTBR       .EQU 0x0004A4\r
+_wthr      .EQU 0x0004A8\r
+WTHR       .EQU 0x0004A8\r
+_wtmr      .EQU 0x0004A9\r
+WTMR       .EQU 0x0004A9\r
+_wtsr      .EQU 0x0004AA\r
+WTSR       .EQU 0x0004AA\r
+_csvtr     .EQU 0x0004AC\r
+CSVTR      .EQU 0x0004AC /* Clock-Supervisor / Selecor / Monitor */\r
+_csvcr     .EQU 0x0004AD\r
+CSVCR      .EQU 0x0004AD\r
+_cscfg  .EQU 0x0004AE\r
+CSCFG   .EQU 0x0004AE\r
+_cmcfg  .EQU 0x0004AF\r
+CMCFG   .EQU 0x0004AF\r
+_cucr      .EQU 0x0004B0\r
+CUCR       .EQU 0x0004B0 /* Calibration Unit of Sub Oszillation */\r
+_cutd      .EQU 0x0004B2\r
+CUTD       .EQU 0x0004B2\r
+_cutr1     .EQU 0x0004B4\r
+CUTR1      .EQU 0x0004B4\r
+_cutr2     .EQU 0x0004B6\r
+CUTR2      .EQU 0x0004B6\r
+_cmpr      .EQU 0x0004B8\r
+CMPR       .EQU 0x0004B8 /* Clock Modulator */\r
+_cmcr  .EQU 0x0004BB\r
+CMCR   .EQU 0x0004BB\r
+_cmt1      .EQU 0x0004BC\r
+CMT1       .EQU 0x0004BC\r
+_cmt2      .EQU 0x0004BE\r
+CMT2       .EQU 0x0004BE\r
+_canpre  .EQU 0x0004C0\r
+CANPRE   .EQU 0x0004C0 /* CAN clock control */\r
+_canckd  .EQU 0x0004C1\r
+CANCKD   .EQU 0x0004C1\r
+_lvsel  .EQU 0x0004C4\r
+LVSEL   .EQU 0x0004C4 /* LV Detection / Hardware-Watchdog */\r
+_lvdet     .EQU 0x0004C5\r
+LVDET      .EQU 0x0004C5\r
+_hwwde     .EQU 0x0004C6\r
+HWWDE      .EQU 0x0004C6\r
+_hwwd      .EQU 0x0004C7\r
+HWWD       .EQU 0x0004C7\r
+_oscrh     .EQU 0x0004C8\r
+OSCRH      .EQU 0x0004C8 /* Main-/Sub-Oscillatio Stabilization Timer */\r
+_oscrl     .EQU 0x0004C9\r
+OSCRL      .EQU 0x0004C9\r
+_wpcrh     .EQU 0x0004CA\r
+WPCRH      .EQU 0x0004CA\r
+_wpcrl     .EQU 0x0004CB\r
+WPCRL      .EQU 0x0004CB\r
+_osccr     .EQU 0x0004CC\r
+OSCCR      .EQU 0x0004CC /* Main-/Sub-Oscillatio Standby Control */\r
+_regsel  .EQU 0x0004CE\r
+REGSEL   .EQU 0x0004CE\r
+_regctr  .EQU 0x0004CF\r
+REGCTR   .EQU 0x0004CF\r
+_asr0      .EQU 0x000640\r
+ASR0       .EQU 0x000640 /* External Bus/Chip Select Registers */\r
+_acr0      .EQU 0x000642\r
+ACR0       .EQU 0x000642\r
+_asr1      .EQU 0x000644\r
+ASR1       .EQU 0x000644\r
+_acr1      .EQU 0x000646\r
+ACR1       .EQU 0x000646\r
+_asr2      .EQU 0x000648\r
+ASR2       .EQU 0x000648\r
+_acr2      .EQU 0x00064A\r
+ACR2       .EQU 0x00064A\r
+_asr3      .EQU 0x00064C\r
+ASR3       .EQU 0x00064C\r
+_acr3      .EQU 0x00064E\r
+ACR3       .EQU 0x00064E\r
+_asr4      .EQU 0x000650\r
+ASR4       .EQU 0x000650\r
+_acr4      .EQU 0x000652\r
+ACR4       .EQU 0x000652\r
+_asr5      .EQU 0x000654\r
+ASR5       .EQU 0x000654\r
+_acr5      .EQU 0x000656\r
+ACR5       .EQU 0x000656\r
+_asr6      .EQU 0x000658\r
+ASR6       .EQU 0x000658\r
+_acr6      .EQU 0x00065A\r
+ACR6       .EQU 0x00065A\r
+_asr7      .EQU 0x00065C\r
+ASR7       .EQU 0x00065C\r
+_acr7      .EQU 0x00065E\r
+ACR7       .EQU 0x00065E\r
+_awr0      .EQU 0x000660\r
+AWR0       .EQU 0x000660\r
+_awr1      .EQU 0x000662\r
+AWR1       .EQU 0x000662\r
+_awr2      .EQU 0x000664\r
+AWR2       .EQU 0x000664\r
+_awr3      .EQU 0x000666\r
+AWR3       .EQU 0x000666\r
+_awr4      .EQU 0x000668\r
+AWR4       .EQU 0x000668\r
+_awr5      .EQU 0x00066A\r
+AWR5       .EQU 0x00066A\r
+_awr6      .EQU 0x00066C\r
+AWR6       .EQU 0x00066C\r
+_awr7      .EQU 0x00066E\r
+AWR7       .EQU 0x00066E\r
+_mcra      .EQU 0x000670\r
+MCRA       .EQU 0x000670\r
+_mcrb      .EQU 0x000671\r
+MCRB       .EQU 0x000671\r
+_iowr0     .EQU 0x000678\r
+IOWR0      .EQU 0x000678\r
+_iowr1     .EQU 0x000679\r
+IOWR1      .EQU 0x000679\r
+_iowr2     .EQU 0x00067A\r
+IOWR2      .EQU 0x00067A\r
+_iowr3     .EQU 0x00067B\r
+IOWR3      .EQU 0x00067B\r
+_cser      .EQU 0x000680\r
+CSER       .EQU 0x000680\r
+_cher      .EQU 0x000681\r
+CHER       .EQU 0x000681\r
+_tcr       .EQU 0x000683\r
+TCR        .EQU 0x000683\r
+_rcr  .EQU 0x000684\r
+RCR   .EQU 0x000684\r
+_modr      .EQU 0x0007FD\r
+MODR       .EQU 0x0007FD /* Mode Register */\r
+_pdrd00    .EQU 0x000D00\r
+PDRD00     .EQU 0x000D00 /* R-bus Port Data Direct Read Register */\r
+_pdrd01    .EQU 0x000D01\r
+PDRD01     .EQU 0x000D01\r
+_pdrd02    .EQU 0x000D02\r
+PDRD02     .EQU 0x000D02\r
+_pdrd03    .EQU 0x000D03\r
+PDRD03     .EQU 0x000D03\r
+_pdrd04    .EQU 0x000D04\r
+PDRD04     .EQU 0x000D04\r
+_pdrd05    .EQU 0x000D05\r
+PDRD05     .EQU 0x000D05\r
+_pdrd06    .EQU 0x000D06\r
+PDRD06     .EQU 0x000D06\r
+_pdrd07    .EQU 0x000D07\r
+PDRD07     .EQU 0x000D07\r
+_pdrd08    .EQU 0x000D08\r
+PDRD08     .EQU 0x000D08\r
+_pdrd09    .EQU 0x000D09\r
+PDRD09     .EQU 0x000D09\r
+_pdrd10    .EQU 0x000D0A\r
+PDRD10     .EQU 0x000D0A\r
+_pdrd13    .EQU 0x000D0D\r
+PDRD13     .EQU 0x000D0D\r
+_pdrd14    .EQU 0x000D0E\r
+PDRD14     .EQU 0x000D0E\r
+_pdrd15    .EQU 0x000D0F\r
+PDRD15     .EQU 0x000D0F\r
+_pdrd16    .EQU 0x000D10\r
+PDRD16     .EQU 0x000D10\r
+_pdrd17    .EQU 0x000D11\r
+PDRD17     .EQU 0x000D11\r
+_pdrd18    .EQU 0x000D12\r
+PDRD18     .EQU 0x000D12\r
+_pdrd19    .EQU 0x000D13\r
+PDRD19     .EQU 0x000D13\r
+_pdrd20    .EQU 0x000D14\r
+PDRD20     .EQU 0x000D14\r
+_pdrd22    .EQU 0x000D16\r
+PDRD22     .EQU 0x000D16\r
+_pdrd23    .EQU 0x000D17\r
+PDRD23     .EQU 0x000D17\r
+_pdrd24    .EQU 0x000D18\r
+PDRD24     .EQU 0x000D18\r
+_pdrd25    .EQU 0x000D19\r
+PDRD25     .EQU 0x000D19\r
+_pdrd26    .EQU 0x000D1A\r
+PDRD26     .EQU 0x000D1A\r
+_pdrd27    .EQU 0x000D1B\r
+PDRD27     .EQU 0x000D1B\r
+_pdrd29    .EQU 0x000D1D\r
+PDRD29     .EQU 0x000D1D\r
+_ddr00     .EQU 0x000D40\r
+DDR00      .EQU 0x000D40 /* R-bus Port Direction Register */\r
+_ddr01     .EQU 0x000D41\r
+DDR01      .EQU 0x000D41\r
+_ddr02     .EQU 0x000D42\r
+DDR02      .EQU 0x000D42\r
+_ddr03     .EQU 0x000D43\r
+DDR03      .EQU 0x000D43\r
+_ddr04     .EQU 0x000D44\r
+DDR04      .EQU 0x000D44\r
+_ddr05     .EQU 0x000D45\r
+DDR05      .EQU 0x000D45\r
+_ddr06     .EQU 0x000D46\r
+DDR06      .EQU 0x000D46\r
+_ddr07     .EQU 0x000D47\r
+DDR07      .EQU 0x000D47\r
+_ddr08     .EQU 0x000D48\r
+DDR08      .EQU 0x000D48\r
+_ddr09     .EQU 0x000D49\r
+DDR09      .EQU 0x000D49\r
+_ddr10     .EQU 0x000D4A\r
+DDR10      .EQU 0x000D4A\r
+_ddr13     .EQU 0x000D4D\r
+DDR13      .EQU 0x000D4D\r
+_ddr14     .EQU 0x000D4E\r
+DDR14      .EQU 0x000D4E\r
+_ddr15     .EQU 0x000D4F\r
+DDR15      .EQU 0x000D4F\r
+_ddr16     .EQU 0x000D50\r
+DDR16      .EQU 0x000D50\r
+_ddr17     .EQU 0x000D51\r
+DDR17      .EQU 0x000D51\r
+_ddr18     .EQU 0x000D52\r
+DDR18      .EQU 0x000D52\r
+_ddr19     .EQU 0x000D53\r
+DDR19      .EQU 0x000D53\r
+_ddr20     .EQU 0x000D54\r
+DDR20      .EQU 0x000D54\r
+_ddr22     .EQU 0x000D56\r
+DDR22      .EQU 0x000D56\r
+_ddr23     .EQU 0x000D57\r
+DDR23      .EQU 0x000D57\r
+_ddr24     .EQU 0x000D58\r
+DDR24      .EQU 0x000D58\r
+_ddr25     .EQU 0x000D59\r
+DDR25      .EQU 0x000D59\r
+_ddr26     .EQU 0x000D5A\r
+DDR26      .EQU 0x000D5A\r
+_ddr27     .EQU 0x000D5B\r
+DDR27      .EQU 0x000D5B\r
+_ddr29     .EQU 0x000D5D\r
+DDR29      .EQU 0x000D5D\r
+_pfr00     .EQU 0x000D80\r
+PFR00      .EQU 0x000D80 /* R-bus Port Function Register */\r
+_pfr01     .EQU 0x000D81\r
+PFR01      .EQU 0x000D81\r
+_pfr02     .EQU 0x000D82\r
+PFR02      .EQU 0x000D82\r
+_pfr03     .EQU 0x000D83\r
+PFR03      .EQU 0x000D83\r
+_pfr04     .EQU 0x000D84\r
+PFR04      .EQU 0x000D84\r
+_pfr05     .EQU 0x000D85\r
+PFR05      .EQU 0x000D85\r
+_pfr06     .EQU 0x000D86\r
+PFR06      .EQU 0x000D86\r
+_pfr07     .EQU 0x000D87\r
+PFR07      .EQU 0x000D87\r
+_pfr08     .EQU 0x000D88\r
+PFR08      .EQU 0x000D88\r
+_pfr09     .EQU 0x000D89\r
+PFR09      .EQU 0x000D89\r
+_pfr10     .EQU 0x000D8A\r
+PFR10      .EQU 0x000D8A\r
+_pfr13     .EQU 0x000D8D\r
+PFR13      .EQU 0x000D8D\r
+_pfr14     .EQU 0x000D8E\r
+PFR14      .EQU 0x000D8E\r
+_pfr15     .EQU 0x000D8F\r
+PFR15      .EQU 0x000D8F\r
+_pfr16     .EQU 0x000D90\r
+PFR16      .EQU 0x000D90\r
+_pfr17     .EQU 0x000D91\r
+PFR17      .EQU 0x000D91\r
+_pfr18     .EQU 0x000D92\r
+PFR18      .EQU 0x000D92\r
+_pfr19     .EQU 0x000D93\r
+PFR19      .EQU 0x000D93\r
+_pfr20     .EQU 0x000D94\r
+PFR20      .EQU 0x000D94\r
+_pfr22     .EQU 0x000D96\r
+PFR22      .EQU 0x000D96\r
+_pfr23     .EQU 0x000D97\r
+PFR23      .EQU 0x000D97\r
+_pfr24     .EQU 0x000D98\r
+PFR24      .EQU 0x000D98\r
+_pfr25     .EQU 0x000D99\r
+PFR25      .EQU 0x000D99\r
+_pfr26     .EQU 0x000D9A\r
+PFR26      .EQU 0x000D9A\r
+_pfr27     .EQU 0x000D9B\r
+PFR27      .EQU 0x000D9B\r
+_pfr29     .EQU 0x000D9D\r
+PFR29      .EQU 0x000D9D\r
+_epfr10    .EQU 0x000DCA\r
+EPFR10     .EQU 0x000DCA /* R-bus Port Extra Function Register */\r
+_epfr13    .EQU 0x000DCD\r
+EPFR13     .EQU 0x000DCD\r
+_epfr14    .EQU 0x000DCE\r
+EPFR14     .EQU 0x000DCE\r
+_epfr15    .EQU 0x000DCF\r
+EPFR15     .EQU 0x000DCF\r
+_epfr16    .EQU 0x000DD0\r
+EPFR16     .EQU 0x000DD0\r
+_epfr18    .EQU 0x000DD2\r
+EPFR18     .EQU 0x000DD2\r
+_epfr19    .EQU 0x000DD3\r
+EPFR19     .EQU 0x000DD3\r
+_epfr20    .EQU 0x000DD4\r
+EPFR20     .EQU 0x000DD4\r
+_epfr26    .EQU 0x000DDA\r
+EPFR26     .EQU 0x000DDA\r
+_epfr27    .EQU 0x000DDB\r
+EPFR27     .EQU 0x000DDB\r
+_podr00    .EQU 0x000E00\r
+PODR00     .EQU 0x000E00 /* R-bus Port Output Drive Select Register */\r
+_podr01    .EQU 0x000E01\r
+PODR01     .EQU 0x000E01\r
+_podr02    .EQU 0x000E02\r
+PODR02     .EQU 0x000E02\r
+_podr03    .EQU 0x000E03\r
+PODR03     .EQU 0x000E03\r
+_podr04    .EQU 0x000E04\r
+PODR04     .EQU 0x000E04\r
+_podr05    .EQU 0x000E05\r
+PODR05     .EQU 0x000E05\r
+_podr06    .EQU 0x000E06\r
+PODR06     .EQU 0x000E06\r
+_podr07    .EQU 0x000E07\r
+PODR07     .EQU 0x000E07\r
+_podr08    .EQU 0x000E08\r
+PODR08     .EQU 0x000E08\r
+_podr09    .EQU 0x000E09\r
+PODR09     .EQU 0x000E09\r
+_podr10    .EQU 0x000E0A\r
+PODR10     .EQU 0x000E0A\r
+_podr13    .EQU 0x000E0D\r
+PODR13     .EQU 0x000E0D\r
+_podr14    .EQU 0x000E0E\r
+PODR14     .EQU 0x000E0E\r
+_podr15    .EQU 0x000E0F\r
+PODR15     .EQU 0x000E0F\r
+_podr16    .EQU 0x000E10\r
+PODR16     .EQU 0x000E10\r
+_podr17    .EQU 0x000E11\r
+PODR17     .EQU 0x000E11\r
+_podr18    .EQU 0x000E12\r
+PODR18     .EQU 0x000E12\r
+_podr19    .EQU 0x000E13\r
+PODR19     .EQU 0x000E13\r
+_podr20    .EQU 0x000E14\r
+PODR20     .EQU 0x000E14\r
+_podr22    .EQU 0x000E16\r
+PODR22     .EQU 0x000E16\r
+_podr23    .EQU 0x000E17\r
+PODR23     .EQU 0x000E17\r
+_podr24    .EQU 0x000E18\r
+PODR24     .EQU 0x000E18\r
+_podr25    .EQU 0x000E19\r
+PODR25     .EQU 0x000E19\r
+_podr26    .EQU 0x000E1A\r
+PODR26     .EQU 0x000E1A\r
+_podr27    .EQU 0x000E1B\r
+PODR27     .EQU 0x000E1B\r
+_podr29    .EQU 0x000E1D\r
+PODR29     .EQU 0x000E1D\r
+_pilr00    .EQU 0x000E40\r
+PILR00     .EQU 0x000E40 /* R-bus Port Input Level Select Register */\r
+_pilr01    .EQU 0x000E41\r
+PILR01     .EQU 0x000E41\r
+_pilr02    .EQU 0x000E42\r
+PILR02     .EQU 0x000E42\r
+_pilr03    .EQU 0x000E43\r
+PILR03     .EQU 0x000E43\r
+_pilr04    .EQU 0x000E44\r
+PILR04     .EQU 0x000E44\r
+_pilr05    .EQU 0x000E45\r
+PILR05     .EQU 0x000E45\r
+_pilr06    .EQU 0x000E46\r
+PILR06     .EQU 0x000E46\r
+_pilr07    .EQU 0x000E47\r
+PILR07     .EQU 0x000E47\r
+_pilr08    .EQU 0x000E48\r
+PILR08     .EQU 0x000E48\r
+_pilr09    .EQU 0x000E49\r
+PILR09     .EQU 0x000E49\r
+_pilr10    .EQU 0x000E4A\r
+PILR10     .EQU 0x000E4A\r
+_pilr13    .EQU 0x000E4D\r
+PILR13     .EQU 0x000E4D\r
+_pilr14    .EQU 0x000E4E\r
+PILR14     .EQU 0x000E4E\r
+_pilr15    .EQU 0x000E4F\r
+PILR15     .EQU 0x000E4F\r
+_pilr16    .EQU 0x000E50\r
+PILR16     .EQU 0x000E50\r
+_pilr17    .EQU 0x000E51\r
+PILR17     .EQU 0x000E51\r
+_pilr18    .EQU 0x000E52\r
+PILR18     .EQU 0x000E52\r
+_pilr19    .EQU 0x000E53\r
+PILR19     .EQU 0x000E53\r
+_pilr20    .EQU 0x000E54\r
+PILR20     .EQU 0x000E54\r
+_pilr22    .EQU 0x000E56\r
+PILR22     .EQU 0x000E56\r
+_pilr23    .EQU 0x000E57\r
+PILR23     .EQU 0x000E57\r
+_pilr24    .EQU 0x000E58\r
+PILR24     .EQU 0x000E58\r
+_pilr25    .EQU 0x000E59\r
+PILR25     .EQU 0x000E59\r
+_pilr26    .EQU 0x000E5A\r
+PILR26     .EQU 0x000E5A\r
+_pilr27    .EQU 0x000E5B\r
+PILR27     .EQU 0x000E5B\r
+_pilr29    .EQU 0x000E5D\r
+PILR29     .EQU 0x000E5D\r
+_epilr00   .EQU 0x000E80\r
+EPILR00    .EQU 0x000E80 /* R-bus Port Extra Input Level Select Register */\r
+_epilr01   .EQU 0x000E81\r
+EPILR01    .EQU 0x000E81\r
+_epilr02   .EQU 0x000E82\r
+EPILR02    .EQU 0x000E82\r
+_epilr03   .EQU 0x000E83\r
+EPILR03    .EQU 0x000E83\r
+_epilr04   .EQU 0x000E84\r
+EPILR04    .EQU 0x000E84\r
+_epilr05   .EQU 0x000E85\r
+EPILR05    .EQU 0x000E85\r
+_epilr06   .EQU 0x000E86\r
+EPILR06    .EQU 0x000E86\r
+_epilr07   .EQU 0x000E87\r
+EPILR07    .EQU 0x000E87\r
+_epilr08   .EQU 0x000E88\r
+EPILR08    .EQU 0x000E88\r
+_epilr09   .EQU 0x000E89\r
+EPILR09    .EQU 0x000E89\r
+_epilr10   .EQU 0x000E8A\r
+EPILR10    .EQU 0x000E8A\r
+_epilr13   .EQU 0x000E8D\r
+EPILR13    .EQU 0x000E8D\r
+_epilr14   .EQU 0x000E8E\r
+EPILR14    .EQU 0x000E8E\r
+_epilr15   .EQU 0x000E8F\r
+EPILR15    .EQU 0x000E8F\r
+_epilr16   .EQU 0x000E80\r
+EPILR16    .EQU 0x000E80\r
+_epilr17   .EQU 0x000E81\r
+EPILR17    .EQU 0x000E81\r
+_epilr18   .EQU 0x000E82\r
+EPILR18    .EQU 0x000E82\r
+_epilr19   .EQU 0x000E83\r
+EPILR19    .EQU 0x000E83\r
+_epilr20   .EQU 0x000E84\r
+EPILR20    .EQU 0x000E84\r
+_epilr22   .EQU 0x000E86\r
+EPILR22    .EQU 0x000E86\r
+_epilr23   .EQU 0x000E87\r
+EPILR23    .EQU 0x000E87\r
+_epilr24   .EQU 0x000E88\r
+EPILR24    .EQU 0x000E88\r
+_epilr25   .EQU 0x000E89\r
+EPILR25    .EQU 0x000E89\r
+_epilr26   .EQU 0x000E8A\r
+EPILR26    .EQU 0x000E8A\r
+_epilr27   .EQU 0x000E8B\r
+EPILR27    .EQU 0x000E8B\r
+_epilr29   .EQU 0x000E8D\r
+EPILR29    .EQU 0x000E8D\r
+_pper00    .EQU 0x000EC0\r
+PPER00     .EQU 0x000EC0 /* R-bus Port Pull-Up/Down  Enable Register */\r
+_pper01    .EQU 0x000EC1\r
+PPER01     .EQU 0x000EC1\r
+_pper02    .EQU 0x000EC2\r
+PPER02     .EQU 0x000EC2\r
+_pper03    .EQU 0x000EC3\r
+PPER03     .EQU 0x000EC3\r
+_pper04    .EQU 0x000EC4\r
+PPER04     .EQU 0x000EC4\r
+_pper05    .EQU 0x000EC5\r
+PPER05     .EQU 0x000EC5\r
+_pper06    .EQU 0x000EC6\r
+PPER06     .EQU 0x000EC6\r
+_pper07    .EQU 0x000EC7\r
+PPER07     .EQU 0x000EC7\r
+_pper08    .EQU 0x000EC8\r
+PPER08     .EQU 0x000EC8\r
+_pper09    .EQU 0x000EC9\r
+PPER09     .EQU 0x000EC9\r
+_pper10    .EQU 0x000ECA\r
+PPER10     .EQU 0x000ECA\r
+_pper13    .EQU 0x000ECD\r
+PPER13     .EQU 0x000ECD\r
+_pper14    .EQU 0x000ECE\r
+PPER14     .EQU 0x000ECE\r
+_pper15    .EQU 0x000ECF\r
+PPER15     .EQU 0x000ECF\r
+_pper16    .EQU 0x000ED0\r
+PPER16     .EQU 0x000ED0\r
+_pper17    .EQU 0x000ED1\r
+PPER17     .EQU 0x000ED1\r
+_pper18    .EQU 0x000ED2\r
+PPER18     .EQU 0x000ED2\r
+_pper19    .EQU 0x000ED3\r
+PPER19     .EQU 0x000ED3\r
+_pper20    .EQU 0x000ED4\r
+PPER20     .EQU 0x000ED4\r
+_pper22    .EQU 0x000ED6\r
+PPER22     .EQU 0x000ED6\r
+_pper23    .EQU 0x000ED7\r
+PPER23     .EQU 0x000ED7\r
+_pper24    .EQU 0x000ED8\r
+PPER24     .EQU 0x000ED8\r
+_pper25    .EQU 0x000ED9\r
+PPER25     .EQU 0x000ED9\r
+_pper26    .EQU 0x000EDA\r
+PPER26     .EQU 0x000EDA\r
+_pper27    .EQU 0x000EDB\r
+PPER27     .EQU 0x000EDB\r
+_pper29    .EQU 0x000EDD\r
+PPER29     .EQU 0x000EDD\r
+_ppcr00    .EQU 0x000F00\r
+PPCR00     .EQU 0x000F00 /* R-bus Port Pull-Up/Down Control Register */\r
+_ppcr01    .EQU 0x000F01\r
+PPCR01     .EQU 0x000F01\r
+_ppcr02    .EQU 0x000F02\r
+PPCR02     .EQU 0x000F02\r
+_ppcr03    .EQU 0x000F03\r
+PPCR03     .EQU 0x000F03\r
+_ppcr04    .EQU 0x000F04\r
+PPCR04     .EQU 0x000F04\r
+_ppcr05    .EQU 0x000F05\r
+PPCR05     .EQU 0x000F05\r
+_ppcr06    .EQU 0x000F06\r
+PPCR06     .EQU 0x000F06\r
+_ppcr07    .EQU 0x000F07\r
+PPCR07     .EQU 0x000F07\r
+_ppcr08    .EQU 0x000F08\r
+PPCR08     .EQU 0x000F08\r
+_ppcr09    .EQU 0x000F09\r
+PPCR09     .EQU 0x000F09\r
+_ppcr10    .EQU 0x000F0A\r
+PPCR10     .EQU 0x000F0A\r
+_ppcr13    .EQU 0x000F0D\r
+PPCR13     .EQU 0x000F0D\r
+_ppcr14    .EQU 0x000F0E\r
+PPCR14     .EQU 0x000F0E\r
+_ppcr15    .EQU 0x000F0F\r
+PPCR15     .EQU 0x000F0F\r
+_ppcr16    .EQU 0x000F10\r
+PPCR16     .EQU 0x000F10\r
+_ppcr17    .EQU 0x000F11\r
+PPCR17     .EQU 0x000F11\r
+_ppcr18    .EQU 0x000F12\r
+PPCR18     .EQU 0x000F12\r
+_ppcr19    .EQU 0x000F13\r
+PPCR19     .EQU 0x000F13\r
+_ppcr20    .EQU 0x000F14\r
+PPCR20     .EQU 0x000F14\r
+_ppcr22    .EQU 0x000F16\r
+PPCR22     .EQU 0x000F16\r
+_ppcr23    .EQU 0x000F17\r
+PPCR23     .EQU 0x000F17\r
+_ppcr24    .EQU 0x000F18\r
+PPCR24     .EQU 0x000F18\r
+_ppcr25    .EQU 0x000F19\r
+PPCR25     .EQU 0x000F19\r
+_ppcr26    .EQU 0x000F1A\r
+PPCR26     .EQU 0x000F1A\r
+_ppcr27    .EQU 0x000F1B\r
+PPCR27     .EQU 0x000F1B\r
+_ppcr29    .EQU 0x000F1D\r
+PPCR29     .EQU 0x000F1D\r
+_dmasa0    .EQU 0x001000\r
+DMASA0     .EQU 0x001000 /* DMAC */\r
+_dmada0    .EQU 0x001004\r
+DMADA0     .EQU 0x001004\r
+_dmasa1    .EQU 0x001008\r
+DMASA1     .EQU 0x001008\r
+_dmada1    .EQU 0x00100C\r
+DMADA1     .EQU 0x00100C\r
+_dmasa2    .EQU 0x001010\r
+DMASA2     .EQU 0x001010\r
+_dmada2    .EQU 0x001014\r
+DMADA2     .EQU 0x001014\r
+_dmasa3    .EQU 0x001018\r
+DMASA3     .EQU 0x001018\r
+_dmada3    .EQU 0x00101C\r
+DMADA3     .EQU 0x00101C\r
+_dmasa4    .EQU 0x001020\r
+DMASA4     .EQU 0x001020\r
+_dmada4    .EQU 0x001024\r
+DMADA4     .EQU 0x001024\r
+_fmcs      .EQU 0x007000\r
+FMCS       .EQU 0x007000 /* Flash Memory/I-Cache Control Register */\r
+_fmcr      .EQU 0x007001\r
+FMCR       .EQU 0x007001\r
+_fchcr     .EQU 0x007002\r
+FCHCR      .EQU 0x007002\r
+_fmwt      .EQU 0x007004\r
+FMWT       .EQU 0x007004\r
+_fmwt2     .EQU 0x007006\r
+FMWT2      .EQU 0x007006\r
+_fmps      .EQU 0x007007\r
+FMPS       .EQU 0x007007\r
+_fmac      .EQU 0x007008\r
+FMAC       .EQU 0x007008\r
+_fcha0     .EQU 0x00700C\r
+FCHA0      .EQU 0x00700C /* I_Cache Nonchachable area settings Register */\r
+_fcha1     .EQU 0x007010\r
+FCHA1      .EQU 0x007010\r
+_fscr0     .EQU 0x007100\r
+FSCR0      .EQU 0x007100 /* Flash Security Control Register */\r
+_fscr1     .EQU 0x007104\r
+FSCR1      .EQU 0x007104\r
+_ctrlr0    .EQU 0x00C000\r
+CTRLR0     .EQU 0x00C000 /* CAN 0 Control Register */\r
+_statr0    .EQU 0x00C002\r
+STATR0     .EQU 0x00C002\r
+_errcnt0   .EQU 0x00C004\r
+ERRCNT0    .EQU 0x00C004\r
+_btr0  .EQU 0x00C006\r
+BTR0   .EQU 0x00C006\r
+_intr0     .EQU 0x00C008\r
+INTR0      .EQU 0x00C008\r
+_testr0    .EQU 0x00C00A\r
+TESTR0     .EQU 0x00C00A\r
+_brper0    .EQU 0x00C00C\r
+BRPER0     .EQU 0x00C00C\r
+_brpe0     .EQU 0x00C00C\r
+BRPE0      .EQU 0x00C00C\r
+_cbsync0   .EQU 0x00C00E\r
+CBSYNC0    .EQU 0x00C00E\r
+_if1creq0  .EQU 0x00C010\r
+IF1CREQ0   .EQU 0x00C010 /* CAN 0 IF 1 */\r
+_if1cmsk0  .EQU 0x00C012\r
+IF1CMSK0   .EQU 0x00C012\r
+_if1msk120  .EQU 0x00C014\r
+IF1MSK120   .EQU 0x00C014\r
+_if1msk20  .EQU 0x00C014\r
+IF1MSK20   .EQU 0x00C014\r
+_if1msk10  .EQU 0x00C016\r
+IF1MSK10   .EQU 0x00C016\r
+_if1arb120  .EQU 0x00C018\r
+IF1ARB120   .EQU 0x00C018\r
+_if1arb20  .EQU 0x00C018\r
+IF1ARB20   .EQU 0x00C018\r
+_if1arb10  .EQU 0x00C01A\r
+IF1ARB10   .EQU 0x00C01A\r
+_if1mctr0  .EQU 0x00C01C\r
+IF1MCTR0   .EQU 0x00C01C\r
+_if1dta120  .EQU 0x00C020\r
+IF1DTA120   .EQU 0x00C020\r
+_if1dta10  .EQU 0x00C020\r
+IF1DTA10   .EQU 0x00C020\r
+_if1dta20  .EQU 0x00C022\r
+IF1DTA20   .EQU 0x00C022\r
+_if1dtb120  .EQU 0x00C024\r
+IF1DTB120   .EQU 0x00C024\r
+_if1dtb10  .EQU 0x00C024\r
+IF1DTB10   .EQU 0x00C024\r
+_if1dtb20  .EQU 0x00C026\r
+IF1DTB20   .EQU 0x00C026\r
+_if1dta_swp120  .EQU 0x00C030\r
+IF1DTA_SWP120   .EQU 0x00C030\r
+_if1dta_swp20  .EQU 0x00C030\r
+IF1DTA_SWP20   .EQU 0x00C030\r
+_if1dta_swp10  .EQU 0x00C032\r
+IF1DTA_SWP10   .EQU 0x00C032\r
+_if1dtb_swp120  .EQU 0x00C034\r
+IF1DTB_SWP120   .EQU 0x00C034\r
+_if1dtb_swp20  .EQU 0x00C034\r
+IF1DTB_SWP20   .EQU 0x00C034\r
+_if1dtb_swp10  .EQU 0x00C036\r
+IF1DTB_SWP10   .EQU 0x00C036\r
+_if2creq0  .EQU 0x00C040\r
+IF2CREQ0   .EQU 0x00C040 /* CAN 0 IF 2 */\r
+_if2cmsk0  .EQU 0x00C042\r
+IF2CMSK0   .EQU 0x00C042\r
+_if2msk120  .EQU 0x00C044\r
+IF2MSK120   .EQU 0x00C044\r
+_if2msk20  .EQU 0x00C044\r
+IF2MSK20   .EQU 0x00C044\r
+_if2msk10  .EQU 0x00C046\r
+IF2MSK10   .EQU 0x00C046\r
+_if2arb120  .EQU 0x00C048\r
+IF2ARB120   .EQU 0x00C048\r
+_if2arb20  .EQU 0x00C048\r
+IF2ARB20   .EQU 0x00C048\r
+_if2arb10  .EQU 0x00C04A\r
+IF2ARB10   .EQU 0x00C04A\r
+_if2mctr0  .EQU 0x00C04C\r
+IF2MCTR0   .EQU 0x00C04C\r
+_if2dta120  .EQU 0x00C050\r
+IF2DTA120   .EQU 0x00C050\r
+_if2dta10  .EQU 0x00C050\r
+IF2DTA10   .EQU 0x00C050\r
+_if2dta20  .EQU 0x00C052\r
+IF2DTA20   .EQU 0x00C052\r
+_if2dtb120  .EQU 0x00C054\r
+IF2DTB120   .EQU 0x00C054\r
+_if2dtb10  .EQU 0x00C054\r
+IF2DTB10   .EQU 0x00C054\r
+_if2dtb20  .EQU 0x00C056\r
+IF2DTB20   .EQU 0x00C056\r
+_if2dta_swp120  .EQU 0x00C060\r
+IF2DTA_SWP120   .EQU 0x00C060\r
+_if2dta_swp20  .EQU 0x00C060\r
+IF2DTA_SWP20   .EQU 0x00C060\r
+_if2dta_swp10  .EQU 0x00C062\r
+IF2DTA_SWP10   .EQU 0x00C062\r
+_if2dtb_swp120  .EQU 0x00C064\r
+IF2DTB_SWP120   .EQU 0x00C064\r
+_if2dtb_swp20  .EQU 0x00C064\r
+IF2DTB_SWP20   .EQU 0x00C064\r
+_if2dtb_swp10  .EQU 0x00C066\r
+IF2DTB_SWP10   .EQU 0x00C066\r
+_treqr120  .EQU 0x00C080\r
+TREQR120   .EQU 0x00C080 /* CAN 0 Status Flags */\r
+_treqr20   .EQU 0x00C080\r
+TREQR20    .EQU 0x00C080\r
+_treqr10   .EQU 0x00C082\r
+TREQR10    .EQU 0x00C082\r
+_newdt120  .EQU 0x00C090\r
+NEWDT120   .EQU 0x00C090\r
+_newdt20   .EQU 0x00C090\r
+NEWDT20    .EQU 0x00C090\r
+_newdt10   .EQU 0x00C092\r
+NEWDT10    .EQU 0x00C092\r
+_intpnd120  .EQU 0x00C0A0\r
+INTPND120   .EQU 0x00C0A0\r
+_intpnd20  .EQU 0x00C0A0\r
+INTPND20   .EQU 0x00C0A0\r
+_intpnd10  .EQU 0x00C0A2\r
+INTPND10   .EQU 0x00C0A2\r
+_msgval120  .EQU 0x00C0B0\r
+MSGVAL120   .EQU 0x00C0B0\r
+_msgval20  .EQU 0x00C0B0\r
+MSGVAL20   .EQU 0x00C0B0\r
+_msgval10  .EQU 0x00C0B2\r
+MSGVAL10   .EQU 0x00C0B2\r
+_msgval340  .EQU 0x00C0B4\r
+MSGVAL340   .EQU 0x00C0B4\r
+_ctrlr1    .EQU 0x00C100\r
+CTRLR1     .EQU 0x00C100 /* CAN 1 Control Register */\r
+_statr1    .EQU 0x00C102\r
+STATR1     .EQU 0x00C102\r
+_errcnt1   .EQU 0x00C104\r
+ERRCNT1    .EQU 0x00C104\r
+_btr1  .EQU 0x00C106\r
+BTR1   .EQU 0x00C106\r
+_intr1     .EQU 0x00C108\r
+INTR1      .EQU 0x00C108\r
+_testr1    .EQU 0x00C10A\r
+TESTR1     .EQU 0x00C10A\r
+_brper1    .EQU 0x00C10C\r
+BRPER1     .EQU 0x00C10C\r
+_brpe1     .EQU 0x00C10C\r
+BRPE1      .EQU 0x00C10C\r
+_cbsync1   .EQU 0x00C10E\r
+CBSYNC1    .EQU 0x00C10E\r
+_if1creq1  .EQU 0x00C110\r
+IF1CREQ1   .EQU 0x00C110 /* CAN 1 IF 1 */\r
+_if1cmsk1  .EQU 0x00C112\r
+IF1CMSK1   .EQU 0x00C112\r
+_if1msk121  .EQU 0x00C114\r
+IF1MSK121   .EQU 0x00C114\r
+_if1msk21  .EQU 0x00C114\r
+IF1MSK21   .EQU 0x00C114\r
+_if1msk11  .EQU 0x00C116\r
+IF1MSK11   .EQU 0x00C116\r
+_if1arb121  .EQU 0x00C118\r
+IF1ARB121   .EQU 0x00C118\r
+_if1arb21  .EQU 0x00C118\r
+IF1ARB21   .EQU 0x00C118\r
+_if1arb11  .EQU 0x00C11A\r
+IF1ARB11   .EQU 0x00C11A\r
+_if1mctr1  .EQU 0x00C11C\r
+IF1MCTR1   .EQU 0x00C11C\r
+_if1dta121  .EQU 0x00C120\r
+IF1DTA121   .EQU 0x00C120\r
+_if1dta11  .EQU 0x00C120\r
+IF1DTA11   .EQU 0x00C120\r
+_if1dta21  .EQU 0x00C122\r
+IF1DTA21   .EQU 0x00C122\r
+_if1dtb121  .EQU 0x00C124\r
+IF1DTB121   .EQU 0x00C124\r
+_if1dtb11  .EQU 0x00C124\r
+IF1DTB11   .EQU 0x00C124\r
+_if1dtb21  .EQU 0x00C126\r
+IF1DTB21   .EQU 0x00C126\r
+_if1dta_swp121  .EQU 0x00C130\r
+IF1DTA_SWP121   .EQU 0x00C130\r
+_if1dta_swp21  .EQU 0x00C130\r
+IF1DTA_SWP21   .EQU 0x00C130\r
+_if1dta_swp11  .EQU 0x00C132\r
+IF1DTA_SWP11   .EQU 0x00C132\r
+_if1dtb_swp121  .EQU 0x00C134\r
+IF1DTB_SWP121   .EQU 0x00C134\r
+_if1dtb_swp21  .EQU 0x00C134\r
+IF1DTB_SWP21   .EQU 0x00C134\r
+_if1dtb_swp11  .EQU 0x00C136\r
+IF1DTB_SWP11   .EQU 0x00C136\r
+_if2creq1  .EQU 0x00C140\r
+IF2CREQ1   .EQU 0x00C140 /* CAN 1 IF 2 */\r
+_if2cmsk1  .EQU 0x00C142\r
+IF2CMSK1   .EQU 0x00C142\r
+_if2msk121  .EQU 0x00C144\r
+IF2MSK121   .EQU 0x00C144\r
+_if2msk21  .EQU 0x00C144\r
+IF2MSK21   .EQU 0x00C144\r
+_if2msk11  .EQU 0x00C146\r
+IF2MSK11   .EQU 0x00C146\r
+_if2arb121  .EQU 0x00C148\r
+IF2ARB121   .EQU 0x00C148\r
+_if2arb21  .EQU 0x00C148\r
+IF2ARB21   .EQU 0x00C148\r
+_if2arb11  .EQU 0x00C14A\r
+IF2ARB11   .EQU 0x00C14A\r
+_if2mctr1  .EQU 0x00C14C\r
+IF2MCTR1   .EQU 0x00C14C\r
+_if2dta121  .EQU 0x00C150\r
+IF2DTA121   .EQU 0x00C150\r
+_if2dta11  .EQU 0x00C150\r
+IF2DTA11   .EQU 0x00C150\r
+_if2dta21  .EQU 0x00C152\r
+IF2DTA21   .EQU 0x00C152\r
+_if2dtb121  .EQU 0x00C154\r
+IF2DTB121   .EQU 0x00C154\r
+_if2dtb11  .EQU 0x00C154\r
+IF2DTB11   .EQU 0x00C154\r
+_if2dtb21  .EQU 0x00C156\r
+IF2DTB21   .EQU 0x00C156\r
+_if2dta_swp121  .EQU 0x00C160\r
+IF2DTA_SWP121   .EQU 0x00C160\r
+_if2dta_swp21  .EQU 0x00C160\r
+IF2DTA_SWP21   .EQU 0x00C160\r
+_if2dta_swp11  .EQU 0x00C162\r
+IF2DTA_SWP11   .EQU 0x00C162\r
+_if2dtb_swp121  .EQU 0x00C164\r
+IF2DTB_SWP121   .EQU 0x00C164\r
+_if2dtb_swp21  .EQU 0x00C164\r
+IF2DTB_SWP21   .EQU 0x00C164\r
+_if2dtb_swp11  .EQU 0x00C166\r
+IF2DTB_SWP11   .EQU 0x00C166\r
+_treqr121  .EQU 0x00C180\r
+TREQR121   .EQU 0x00C180 /* CAN 1 Status Flags */\r
+_treqr21   .EQU 0x00C180\r
+TREQR21    .EQU 0x00C180\r
+_treqr11   .EQU 0x00C182\r
+TREQR11    .EQU 0x00C182\r
+_newdt121  .EQU 0x00C190\r
+NEWDT121   .EQU 0x00C190\r
+_newdt21   .EQU 0x00C190\r
+NEWDT21    .EQU 0x00C190\r
+_newdt11   .EQU 0x00C192\r
+NEWDT11    .EQU 0x00C192\r
+_intpnd121  .EQU 0x00C1A0\r
+INTPND121   .EQU 0x00C1A0\r
+_intpnd21  .EQU 0x00C1A0\r
+INTPND21   .EQU 0x00C1A0\r
+_intpnd11  .EQU 0x00C1A2\r
+INTPND11   .EQU 0x00C1A2\r
+_msgval121  .EQU 0x00C1B0\r
+MSGVAL121   .EQU 0x00C1B0\r
+_msgval21  .EQU 0x00C1B0\r
+MSGVAL21   .EQU 0x00C1B0\r
+_msgval11  .EQU 0x00C1B2\r
+MSGVAL11   .EQU 0x00C1B2\r
+_ctrlr2    .EQU 0x00C200\r
+CTRLR2     .EQU 0x00C200 /* CAN 2 Control Register */\r
+_statr2    .EQU 0x00C202\r
+STATR2     .EQU 0x00C202\r
+_errcnt2   .EQU 0x00C204\r
+ERRCNT2    .EQU 0x00C204\r
+_btr2  .EQU 0x00C206\r
+BTR2   .EQU 0x00C206\r
+_intr2     .EQU 0x00C208\r
+INTR2      .EQU 0x00C208\r
+_testr2    .EQU 0x00C20A\r
+TESTR2     .EQU 0x00C20A\r
+_brper2    .EQU 0x00C20C\r
+BRPER2     .EQU 0x00C20C\r
+_brpe2     .EQU 0x00C20C\r
+BRPE2      .EQU 0x00C20C\r
+_cbsync2   .EQU 0x00C20E\r
+CBSYNC2    .EQU 0x00C20E\r
+_if1creq2  .EQU 0x00C210\r
+IF1CREQ2   .EQU 0x00C210 /* CAN 2 IF 1 */\r
+_if1cmsk2  .EQU 0x00C212\r
+IF1CMSK2   .EQU 0x00C212\r
+_if1msk122  .EQU 0x00C214\r
+IF1MSK122   .EQU 0x00C214\r
+_if1msk22  .EQU 0x00C214\r
+IF1MSK22   .EQU 0x00C214\r
+_if1msk12  .EQU 0x00C216\r
+IF1MSK12   .EQU 0x00C216\r
+_if1arb122  .EQU 0x00C218\r
+IF1ARB122   .EQU 0x00C218\r
+_if1arb22  .EQU 0x00C218\r
+IF1ARB22   .EQU 0x00C218\r
+_if1arb12  .EQU 0x00C21A\r
+IF1ARB12   .EQU 0x00C21A\r
+_if1mctr2  .EQU 0x00C21C\r
+IF1MCTR2   .EQU 0x00C21C\r
+_if1dta122  .EQU 0x00C220\r
+IF1DTA122   .EQU 0x00C220\r
+_if1dta12  .EQU 0x00C220\r
+IF1DTA12   .EQU 0x00C220\r
+_if1dta22  .EQU 0x00C222\r
+IF1DTA22   .EQU 0x00C222\r
+_if1dtb122  .EQU 0x00C224\r
+IF1DTB122   .EQU 0x00C224\r
+_if1dtb12  .EQU 0x00C224\r
+IF1DTB12   .EQU 0x00C224\r
+_if1dtb22  .EQU 0x00C226\r
+IF1DTB22   .EQU 0x00C226\r
+_if1dta_swp122  .EQU 0x00C230\r
+IF1DTA_SWP122   .EQU 0x00C230\r
+_if1dta_swp22  .EQU 0x00C230\r
+IF1DTA_SWP22   .EQU 0x00C230\r
+_if1dta_swp12  .EQU 0x00C232\r
+IF1DTA_SWP12   .EQU 0x00C232\r
+_if1dtb_swp122  .EQU 0x00C234\r
+IF1DTB_SWP122   .EQU 0x00C234\r
+_if1dtb_swp22  .EQU 0x00C234\r
+IF1DTB_SWP22   .EQU 0x00C234\r
+_if1dtb_swp12  .EQU 0x00C236\r
+IF1DTB_SWP12   .EQU 0x00C236\r
+_if2creq2  .EQU 0x00C240\r
+IF2CREQ2   .EQU 0x00C240 /* CAN 2 IF 2 */\r
+_if2cmsk2  .EQU 0x00C242\r
+IF2CMSK2   .EQU 0x00C242\r
+_if2msk122  .EQU 0x00C244\r
+IF2MSK122   .EQU 0x00C244\r
+_if2msk22  .EQU 0x00C244\r
+IF2MSK22   .EQU 0x00C244\r
+_if2msk12  .EQU 0x00C246\r
+IF2MSK12   .EQU 0x00C246\r
+_if2arb122  .EQU 0x00C248\r
+IF2ARB122   .EQU 0x00C248\r
+_if2arb22  .EQU 0x00C248\r
+IF2ARB22   .EQU 0x00C248\r
+_if2arb12  .EQU 0x00C24A\r
+IF2ARB12   .EQU 0x00C24A\r
+_if2mctr2  .EQU 0x00C24C\r
+IF2MCTR2   .EQU 0x00C24C\r
+_if2dta122  .EQU 0x00C250\r
+IF2DTA122   .EQU 0x00C250\r
+_if2dta12  .EQU 0x00C250\r
+IF2DTA12   .EQU 0x00C250\r
+_if2dta22  .EQU 0x00C252\r
+IF2DTA22   .EQU 0x00C252\r
+_if2dtb122  .EQU 0x00C254\r
+IF2DTB122   .EQU 0x00C254\r
+_if2dtb12  .EQU 0x00C254\r
+IF2DTB12   .EQU 0x00C254\r
+_if2dtb22  .EQU 0x00C256\r
+IF2DTB22   .EQU 0x00C256\r
+_if2dta_swp122  .EQU 0x00C260\r
+IF2DTA_SWP122   .EQU 0x00C260\r
+_if2dta_swp22  .EQU 0x00C260\r
+IF2DTA_SWP22   .EQU 0x00C260\r
+_if2dta_swp12  .EQU 0x00C262\r
+IF2DTA_SWP12   .EQU 0x00C262\r
+_if2dtb_swp122  .EQU 0x00C264\r
+IF2DTB_SWP122   .EQU 0x00C264\r
+_if2dtb_swp22  .EQU 0x00C264\r
+IF2DTB_SWP22   .EQU 0x00C264\r
+_if2dtb_swp12  .EQU 0x00C266\r
+IF2DTB_SWP12   .EQU 0x00C266\r
+_treqr122  .EQU 0x00C280\r
+TREQR122   .EQU 0x00C280 /* CAN 2 Status Flags */\r
+_treqr22   .EQU 0x00C280\r
+TREQR22    .EQU 0x00C280\r
+_treqr12   .EQU 0x00C282\r
+TREQR12    .EQU 0x00C282\r
+_newdt122  .EQU 0x00C290\r
+NEWDT122   .EQU 0x00C290\r
+_newdt22   .EQU 0x00C290\r
+NEWDT22    .EQU 0x00C290\r
+_newdt12   .EQU 0x00C292\r
+NEWDT12    .EQU 0x00C292\r
+_intpnd122  .EQU 0x00C2A0\r
+INTPND122   .EQU 0x00C2A0\r
+_intpnd22  .EQU 0x00C2A0\r
+INTPND22   .EQU 0x00C2A0\r
+_intpnd12  .EQU 0x00C2A2\r
+INTPND12   .EQU 0x00C2A2\r
+_msgval122  .EQU 0x00C2B0\r
+MSGVAL122   .EQU 0x00C2B0\r
+_msgval22  .EQU 0x00C2B0\r
+MSGVAL22   .EQU 0x00C2B0\r
+_msgval12  .EQU 0x00C2B2\r
+MSGVAL12   .EQU 0x00C2B2\r
+_bctrl     .EQU 0x00F000\r
+BCTRL      .EQU 0x00F000 /* EDSU/MPU Registers */\r
+_bstat     .EQU 0x00F004\r
+BSTAT      .EQU 0x00F004\r
+_biac      .EQU 0x00F008\r
+BIAC       .EQU 0x00F008\r
+_boac      .EQU 0x00F00C\r
+BOAC       .EQU 0x00F00C\r
+_birq      .EQU 0x00F010\r
+BIRQ       .EQU 0x00F010\r
+_bcr0      .EQU 0x00F020\r
+BCR0       .EQU 0x00F020\r
+_bcr1      .EQU 0x00F024\r
+BCR1       .EQU 0x00F024\r
+_bcr2      .EQU 0x00F028\r
+BCR2       .EQU 0x00F028\r
+_bcr3      .EQU 0x00F02C\r
+BCR3       .EQU 0x00F02C\r
+_bcr4      .EQU 0x00F030\r
+BCR4       .EQU 0x00F030\r
+_bcr5      .EQU 0x00F034\r
+BCR5       .EQU 0x00F034\r
+_bcr6      .EQU 0x00F038\r
+BCR6       .EQU 0x00F038\r
+_bcr7      .EQU 0x00F03C\r
+BCR7       .EQU 0x00F03C\r
+_bad0      .EQU 0x00F080\r
+BAD0       .EQU 0x00F080\r
+_bad1      .EQU 0x00F084\r
+BAD1       .EQU 0x00F084\r
+_bad2      .EQU 0x00F088\r
+BAD2       .EQU 0x00F088\r
+_bad3      .EQU 0x00F08C\r
+BAD3       .EQU 0x00F08C\r
+_bad4      .EQU 0x00F090\r
+BAD4       .EQU 0x00F090\r
+_bad5      .EQU 0x00F094\r
+BAD5       .EQU 0x00F094\r
+_bad6      .EQU 0x00F098\r
+BAD6       .EQU 0x00F098\r
+_bad7      .EQU 0x00F09C\r
+BAD7       .EQU 0x00F09C\r
+_bad8      .EQU 0x00F0A0\r
+BAD8       .EQU 0x00F0A0\r
+_bad9      .EQU 0x00F0A4\r
+BAD9       .EQU 0x00F0A4\r
+_bad10     .EQU 0x00F0A8\r
+BAD10      .EQU 0x00F0A8\r
+_bad11     .EQU 0x00F0AC\r
+BAD11      .EQU 0x00F0AC\r
+_bad12     .EQU 0x00F0B0\r
+BAD12      .EQU 0x00F0B0\r
+_bad13     .EQU 0x00F0B4\r
+BAD13      .EQU 0x00F0B4\r
+_bad14     .EQU 0x00F0B8\r
+BAD14      .EQU 0x00F0B8\r
+_bad15     .EQU 0x00F0BC\r
+BAD15      .EQU 0x00F0BC\r
+_fsv1      .EQU 0x148000\r
+FSV1       .EQU 0x148000 /* FSV & BSV Registers */\r
+_bsv1      .EQU 0x148004\r
+BSV1       .EQU 0x148004\r
+_fsv2      .EQU 0x148008\r
+FSV2       .EQU 0x148008\r
+_bsv2      .EQU 0x14800C\r
+BSV2       .EQU 0x14800C\r
+#pragma endasm\r
+#else\r
+\r
+#ifndef _MB91XXX_H\r
+#define _MB91XXX_H\r
+\r
+#ifdef  __FASM__ \r
+#pragma asm\r
+ .IMPORT _pdr00,    _pdr01,    _pdr02,    _pdr03,    _pdr04,    _pdr05\r
+ .IMPORT _pdr06,    _pdr07,    _pdr08,    _pdr09,    _pdr10,    _pdr13\r
+ .IMPORT _pdr14,    _pdr15,    _pdr16,    _pdr17,    _pdr18,    _pdr19\r
+ .IMPORT _pdr20,    _pdr22,    _pdr23,    _pdr24,    _pdr25,    _pdr26\r
+ .IMPORT _pdr27,    _pdr29,    _eirr0,    _enir0,    _elvr0,    _eirr1\r
+ .IMPORT _enir1,    _elvr1,    _dicr,     _hrcl,     _rbsync,   _scr02\r
+ .IMPORT _smr02,    _ssr02,    _rdr02,    _tdr02,    _escr02,   _eccr02\r
+ .IMPORT _scr04,    _smr04,    _ssr04,    _rdr04,    _tdr04,    _escr04\r
+ .IMPORT _eccr04,   _fsr04,    _fcr04,    _scr05,    _smr05,    _ssr05\r
+ .IMPORT _rdr05,    _tdr05,    _escr05,   _eccr05,   _fsr05,    _fcr05\r
+ .IMPORT _scr06,    _smr06,    _ssr06,    _rdr06,    _tdr06,    _escr06\r
+ .IMPORT _eccr06,   _fsr06,    _fcr06,    _scr07,    _smr07,    _ssr07\r
+ .IMPORT _rdr07,    _tdr07,    _escr07,   _eccr07,   _fsr07,    _fcr07\r
+ .IMPORT _bgr02,    _bgr102,   _bgr002,   _bgr04,    _bgr104,   _bgr004\r
+ .IMPORT _bgr05,    _bgr105,   _bgr005,   _bgr06,    _bgr106,   _bgr006\r
+ .IMPORT _bgr07,    _bgr107,   _bgr007,   _pwc20,    _pwc10,    _pws20\r
+ .IMPORT _pws10,    _pwc21,    _pwc11,    _pws21,    _pws11,    _pwc22\r
+ .IMPORT _pwc12,    _pws22,    _pws12,    _pwc23,    _pwc13,    _pws23\r
+ .IMPORT _pws13,    _pwc24,    _pwc14,    _pws24,    _pws14,    _pwc25\r
+ .IMPORT _pwc15,    _pws25,    _pws15,    _pwc0,     _pwc1,     _pwc2\r
+ .IMPORT _pwc3,     _pwc4,     _pwc5,     _ibcr0,    _ibsr0,    _itba0\r
+ .IMPORT _itbah0,   _itbal0,   _itmk0,    _itmkh0,   _itmkl0,   _ismk0\r
+ .IMPORT _isba0,    _idar0,    _iccr0,    _gcn11,    _gcn21,    _gcn12\r
+ .IMPORT _gcn22,    _ptmr04,   _pcsr04,   _pdut04,   _pcn04,    _pcnh04\r
+ .IMPORT _pcnl04,   _ptmr05,   _pcsr05,   _pdut05,   _pcn05,    _pcnh05\r
+ .IMPORT _pcnl05,   _ptmr06,   _pcsr06,   _pdut06,   _pcn06,    _pcnh06\r
+ .IMPORT _pcnl06,   _ptmr07,   _pcsr07,   _pdut07,   _pcn07,    _pcnh07\r
+ .IMPORT _pcnl07,   _ptmr08,   _pcsr08,   _pdut08,   _pcn08,    _pcnh08\r
+ .IMPORT _pcnl08,   _ptmr09,   _pcsr09,   _pdut09,   _pcn09,    _pcnh09\r
+ .IMPORT _pcnl09,   _ptmr10,   _pcsr10,   _pdut10,   _pcn10,    _pcnh10\r
+ .IMPORT _pcnl10,   _ptmr11,   _pcsr11,   _pdut11,   _pcn11,    _pcnh11\r
+ .IMPORT _pcnl11,   _p0tmcsr,  _p0tmcsrh, _p0tmcsrl, _p1tmcsr,  _p1tmcsrh\r
+ .IMPORT _p1tmcsrl, _p0tmrlr,  _p0tmr,    _p1tmrlr,  _p1tmr,    _ics01\r
+ .IMPORT _ics23,    _ipcp0,    _ipcp1,    _ipcp2,    _ipcp3,    _ocs01\r
+ .IMPORT _ocs23,    _occp0,    _occp1,    _occp2,    _occp3,    _sgcr\r
+ .IMPORT _sgcrh,    _sgcrl,    _sgfr,     _sgar,     _sgtr,     _sgdr\r
+ .IMPORT _aderh,    _aderl,    _ader,     _adcs1,    _adcs0,    _adcs\r
+ .IMPORT _adcr1,    _adcr0,    _adcr,     _adct1,    _adct0,    _adct\r
+ .IMPORT _adsch,    _adech,    _acsr0,    _tmrlr0,   _tmr0,     _tmcsr0\r
+ .IMPORT _tmcsrh0,  _tmcsrl0,  _tmrlr1,   _tmr1,     _tmcsr1,   _tmcsrh1\r
+ .IMPORT _tmcsrl1,  _tmrlr2,   _tmr2,     _tmcsr2,   _tmcsrh2,  _tmcsrl2\r
+ .IMPORT _tmrlr3,   _tmr3,     _tmcsr3,   _tmcsrh3,  _tmcsrl3,  _tmrlr4\r
+ .IMPORT _tmr4,     _tmcsr4,   _tmcsrh4,  _tmcsrl4,  _tmrlr5,   _tmr5\r
+ .IMPORT _tmcsr5,   _tmcsrh5,  _tmcsrl5,  _tmrlr6,   _tmr6,     _tmcsr6\r
+ .IMPORT _tmcsrh6,  _tmcsrl6,  _tmrlr7,   _tmr7,     _tmcsr7,   _tmcsrh7\r
+ .IMPORT _tmcsrl7,  _tcdt0,    _tccs0,    _tcdt1,    _tccs1,    _tcdt2\r
+ .IMPORT _tccs2,    _tcdt3,    _tccs3,    _dmaca0,   _dmacb0,   _dmaca1\r
+ .IMPORT _dmacb1,   _dmaca2,   _dmacb2,   _dmaca3,   _dmacb3,   _dmaca4\r
+ .IMPORT _dmacb4,   _dmacr,    _ics45,    _ics67,    _ipcp4,    _ipcp5\r
+ .IMPORT _ipcp6,    _ipcp7,    _tcdt4,    _tccs4,    _tcdt5,    _tccs5\r
+ .IMPORT _tcdt6,    _tccs6,    _tcdt7,    _tccs7,    _udrc10,   _udrc1\r
+ .IMPORT _udrc0,    _udcr10,   _udcr1,    _udcr0,    _udcc0,    _udcch0\r
+ .IMPORT _udccl0,   _udcs0,    _udcc1,    _udcch1,   _udccl1,   _udcs1\r
+ .IMPORT _udrc32,   _udrc3,    _udrc2,    _udcr32,   _udcr3,    _udcr2\r
+ .IMPORT _udcc2,    _udcch2,   _udccl2,   _udcs2,    _udcc3,    _udcch3\r
+ .IMPORT _udccl3,   _udcs3,    _gcn13,    _gcn23,    _ptmr12,   _pcsr12\r
+ .IMPORT _pdut12,   _pcn12,    _pcnh12,   _pcnl12,   _ptmr13,   _pcsr13\r
+ .IMPORT _pdut13,   _pcn13,    _pcnh13,   _pcnl13,   _ptmr14,   _pcsr14\r
+ .IMPORT _pdut14,   _pcn14,    _pcnh14,   _pcnl14,   _ptmr15,   _pcsr15\r
+ .IMPORT _pdut15,   _pcn15,    _pcnh15,   _pcnl15,   _ibcr2,    _ibsr2\r
+ .IMPORT _itba2,    _itbah2,   _itbal2,   _itmk2,    _itmkh2,   _itmkl2\r
+ .IMPORT _ismk2,    _isba2,    _idar2,    _iccr2,    _ibcr3,    _ibsr3\r
+ .IMPORT _itba3,    _itbah3,   _itbal3,   _itmk3,    _itmkh3,   _itmkl3\r
+ .IMPORT _ismk3,    _isba3,    _idar3,    _iccr3,    _roms,     _bsd0\r
+ .IMPORT _bsd1,     _bsdc,     _bsrr,     _icr00,    _icr01,    _icr02\r
+ .IMPORT _icr03,    _icr04,    _icr05,    _icr06,    _icr07,    _icr08\r
+ .IMPORT _icr09,    _icr10,    _icr11,    _icr12,    _icr13,    _icr14\r
+ .IMPORT _icr15,    _icr16,    _icr17,    _icr18,    _icr19,    _icr20\r
+ .IMPORT _icr21,    _icr22,    _icr23,    _icr24,    _icr25,    _icr26\r
+ .IMPORT _icr27,    _icr28,    _icr29,    _icr30,    _icr31,    _icr32\r
+ .IMPORT _icr33,    _icr34,    _icr35,    _icr36,    _icr37,    _icr38\r
+ .IMPORT _icr39,    _icr40,    _icr41,    _icr42,    _icr43,    _icr44\r
+ .IMPORT _icr45,    _icr46,    _icr47,    _icr48,    _icr49,    _icr50\r
+ .IMPORT _icr51,    _icr52,    _icr53,    _icr54,    _icr55,    _icr56\r
+ .IMPORT _icr57,    _icr58,    _icr59,    _icr60,    _icr61,    _icr62\r
+ .IMPORT _icr63,    _rsrr,     _stcr,     _tbcr,     _ctbr,     _clkr\r
+ .IMPORT _wpr,      _divr0,    _divr1,    _plldivm,  _plldivn,  _plldivg\r
+ .IMPORT _pllmulg,  _pllctrl,  _oscc1,    _oscs1,    _oscc2,    _oscs2\r
+ .IMPORT _porten,   _wtcer,    _wtcr,     _wtbr,     _wthr,     _wtmr\r
+ .IMPORT _wtsr,     _csvtr,    _csvcr,    _cscfg,    _cmcfg,    _cucr\r
+ .IMPORT _cutd,     _cutr1,    _cutr2,    _cmpr,     _cmcr,     _cmt1\r
+ .IMPORT _cmt2,     _canpre,   _canckd,   _lvsel,    _lvdet,    _hwwde\r
+ .IMPORT _hwwd,     _oscrh,    _oscrl,    _wpcrh,    _wpcrl,    _osccr\r
+ .IMPORT _regsel,   _regctr,   _asr0,     _acr0,     _asr1,     _acr1\r
+ .IMPORT _asr2,     _acr2,     _asr3,     _acr3,     _asr4,     _acr4\r
+ .IMPORT _asr5,     _acr5,     _asr6,     _acr6,     _asr7,     _acr7\r
+ .IMPORT _awr0,     _awr1,     _awr2,     _awr3,     _awr4,     _awr5\r
+ .IMPORT _awr6,     _awr7,     _mcra,     _mcrb,     _iowr0,    _iowr1\r
+ .IMPORT _iowr2,    _iowr3,    _cser,     _cher,     _tcr,      _rcr\r
+ .IMPORT _modr,     _pdrd00,   _pdrd01,   _pdrd02,   _pdrd03,   _pdrd04\r
+ .IMPORT _pdrd05,   _pdrd06,   _pdrd07,   _pdrd08,   _pdrd09,   _pdrd10\r
+ .IMPORT _pdrd13,   _pdrd14,   _pdrd15,   _pdrd16,   _pdrd17,   _pdrd18\r
+ .IMPORT _pdrd19,   _pdrd20,   _pdrd22,   _pdrd23,   _pdrd24,   _pdrd25\r
+ .IMPORT _pdrd26,   _pdrd27,   _pdrd29,   _ddr00,    _ddr01,    _ddr02\r
+ .IMPORT _ddr03,    _ddr04,    _ddr05,    _ddr06,    _ddr07,    _ddr08\r
+ .IMPORT _ddr09,    _ddr10,    _ddr13,    _ddr14,    _ddr15,    _ddr16\r
+ .IMPORT _ddr17,    _ddr18,    _ddr19,    _ddr20,    _ddr22,    _ddr23\r
+ .IMPORT _ddr24,    _ddr25,    _ddr26,    _ddr27,    _ddr29,    _pfr00\r
+ .IMPORT _pfr01,    _pfr02,    _pfr03,    _pfr04,    _pfr05,    _pfr06\r
+ .IMPORT _pfr07,    _pfr08,    _pfr09,    _pfr10,    _pfr13,    _pfr14\r
+ .IMPORT _pfr15,    _pfr16,    _pfr17,    _pfr18,    _pfr19,    _pfr20\r
+ .IMPORT _pfr22,    _pfr23,    _pfr24,    _pfr25,    _pfr26,    _pfr27\r
+ .IMPORT _pfr29,    _epfr10,   _epfr13,   _epfr14,   _epfr15,   _epfr16\r
+ .IMPORT _epfr18,   _epfr19,   _epfr20,   _epfr26,   _epfr27,   _podr00\r
+ .IMPORT _podr01,   _podr02,   _podr03,   _podr04,   _podr05,   _podr06\r
+ .IMPORT _podr07,   _podr08,   _podr09,   _podr10,   _podr13,   _podr14\r
+ .IMPORT _podr15,   _podr16,   _podr17,   _podr18,   _podr19,   _podr20\r
+ .IMPORT _podr22,   _podr23,   _podr24,   _podr25,   _podr26,   _podr27\r
+ .IMPORT _podr29,   _pilr00,   _pilr01,   _pilr02,   _pilr03,   _pilr04\r
+ .IMPORT _pilr05,   _pilr06,   _pilr07,   _pilr08,   _pilr09,   _pilr10\r
+ .IMPORT _pilr13,   _pilr14,   _pilr15,   _pilr16,   _pilr17,   _pilr18\r
+ .IMPORT _pilr19,   _pilr20,   _pilr22,   _pilr23,   _pilr24,   _pilr25\r
+ .IMPORT _pilr26,   _pilr27,   _pilr29,   _epilr00,  _epilr01,  _epilr02\r
+ .IMPORT _epilr03,  _epilr04,  _epilr05,  _epilr06,  _epilr07,  _epilr08\r
+ .IMPORT _epilr09,  _epilr10,  _epilr13,  _epilr14,  _epilr15,  _epilr16\r
+ .IMPORT _epilr17,  _epilr18,  _epilr19,  _epilr20,  _epilr22,  _epilr23\r
+ .IMPORT _epilr24,  _epilr25,  _epilr26,  _epilr27,  _epilr29,  _pper00\r
+ .IMPORT _pper01,   _pper02,   _pper03,   _pper04,   _pper05,   _pper06\r
+ .IMPORT _pper07,   _pper08,   _pper09,   _pper10,   _pper13,   _pper14\r
+ .IMPORT _pper15,   _pper16,   _pper17,   _pper18,   _pper19,   _pper20\r
+ .IMPORT _pper22,   _pper23,   _pper24,   _pper25,   _pper26,   _pper27\r
+ .IMPORT _pper29,   _ppcr00,   _ppcr01,   _ppcr02,   _ppcr03,   _ppcr04\r
+ .IMPORT _ppcr05,   _ppcr06,   _ppcr07,   _ppcr08,   _ppcr09,   _ppcr10\r
+ .IMPORT _ppcr13,   _ppcr14,   _ppcr15,   _ppcr16,   _ppcr17,   _ppcr18\r
+ .IMPORT _ppcr19,   _ppcr20,   _ppcr22,   _ppcr23,   _ppcr24,   _ppcr25\r
+ .IMPORT _ppcr26,   _ppcr27,   _ppcr29,   _dmasa0,   _dmada0,   _dmasa1\r
+ .IMPORT _dmada1,   _dmasa2,   _dmada2,   _dmasa3,   _dmada3,   _dmasa4\r
+ .IMPORT _dmada4,   _fmcs,     _fmcr,     _fchcr,    _fmwt,     _fmwt2\r
+ .IMPORT _fmps,     _fmac,     _fcha0,    _fcha1,    _fscr0,    _fscr1\r
+ .IMPORT _ctrlr0,   _statr0,   _errcnt0,  _btr0,     _intr0,    _testr0\r
+ .IMPORT _brper0,   _brpe0,    _cbsync0,  _if1creq0, _if1cmsk0, _if1msk120\r
+ .IMPORT _if1msk20, _if1msk10, _if1arb120, _if1arb20, _if1arb10, _if1mctr0\r
+ .IMPORT _if1dta120, _if1dta10, _if1dta20, _if1dtb120, _if1dtb10, _if1dtb20\r
+ .IMPORT _if1dta_swp120, _if1dta_swp20, _if1dta_swp10, _if1dtb_swp120, _if1dtb_swp20, _if1dtb_swp10\r
+ .IMPORT _if2creq0, _if2cmsk0, _if2msk120, _if2msk20, _if2msk10, _if2arb120\r
+ .IMPORT _if2arb20, _if2arb10, _if2mctr0, _if2dta120, _if2dta10, _if2dta20\r
+ .IMPORT _if2dtb120, _if2dtb10, _if2dtb20, _if2dta_swp120, _if2dta_swp20, _if2dta_swp10\r
+ .IMPORT _if2dtb_swp120, _if2dtb_swp20, _if2dtb_swp10, _treqr120, _treqr20,  _treqr10\r
+ .IMPORT _newdt120, _newdt20,  _newdt10,  _intpnd120, _intpnd20, _intpnd10\r
+ .IMPORT _msgval120, _msgval20, _msgval10, _msgval340, _ctrlr1,   _statr1\r
+ .IMPORT _errcnt1,  _btr1,     _intr1,    _testr1,   _brper1,   _brpe1\r
+ .IMPORT _cbsync1,  _if1creq1, _if1cmsk1, _if1msk121, _if1msk21, _if1msk11\r
+ .IMPORT _if1arb121, _if1arb21, _if1arb11, _if1mctr1, _if1dta121, _if1dta11\r
+ .IMPORT _if1dta21, _if1dtb121, _if1dtb11, _if1dtb21, _if1dta_swp121, _if1dta_swp21\r
+ .IMPORT _if1dta_swp11, _if1dtb_swp121, _if1dtb_swp21, _if1dtb_swp11, _if2creq1, _if2cmsk1\r
+ .IMPORT _if2msk121, _if2msk21, _if2msk11, _if2arb121, _if2arb21, _if2arb11\r
+ .IMPORT _if2mctr1, _if2dta121, _if2dta11, _if2dta21, _if2dtb121, _if2dtb11\r
+ .IMPORT _if2dtb21, _if2dta_swp121, _if2dta_swp21, _if2dta_swp11, _if2dtb_swp121, _if2dtb_swp21\r
+ .IMPORT _if2dtb_swp11, _treqr121, _treqr21,  _treqr11,  _newdt121, _newdt21\r
+ .IMPORT _newdt11,  _intpnd121, _intpnd21, _intpnd11, _msgval121, _msgval21\r
+ .IMPORT _msgval11, _ctrlr2,   _statr2,   _errcnt2,  _btr2,     _intr2\r
+ .IMPORT _testr2,   _brper2,   _brpe2,    _cbsync2,  _if1creq2, _if1cmsk2\r
+ .IMPORT _if1msk122, _if1msk22, _if1msk12, _if1arb122, _if1arb22, _if1arb12\r
+ .IMPORT _if1mctr2, _if1dta122, _if1dta12, _if1dta22, _if1dtb122, _if1dtb12\r
+ .IMPORT _if1dtb22, _if1dta_swp122, _if1dta_swp22, _if1dta_swp12, _if1dtb_swp122, _if1dtb_swp22\r
+ .IMPORT _if1dtb_swp12, _if2creq2, _if2cmsk2, _if2msk122, _if2msk22, _if2msk12\r
+ .IMPORT _if2arb122, _if2arb22, _if2arb12, _if2mctr2, _if2dta122, _if2dta12\r
+ .IMPORT _if2dta22, _if2dtb122, _if2dtb12, _if2dtb22, _if2dta_swp122, _if2dta_swp22\r
+ .IMPORT _if2dta_swp12, _if2dtb_swp122, _if2dtb_swp22, _if2dtb_swp12, _treqr122, _treqr22\r
+ .IMPORT _treqr12,  _newdt122, _newdt22,  _newdt12,  _intpnd122, _intpnd22\r
+ .IMPORT _intpnd12, _msgval122, _msgval22, _msgval12, _bctrl,    _bstat\r
+ .IMPORT _biac,     _boac,     _birq,     _bcr0,     _bcr1,     _bcr2\r
+ .IMPORT _bcr3,     _bcr4,     _bcr5,     _bcr6,     _bcr7,     _bad0\r
+ .IMPORT _bad1,     _bad2,     _bad3,     _bad4,     _bad5,     _bad6\r
+ .IMPORT _bad7,     _bad8,     _bad9,     _bad10,    _bad11,    _bad12\r
+ .IMPORT _bad13,    _bad14,    _bad15,    _fsv1,     _bsv1,     _fsv2\r
+ .IMPORT _bsv2\r
+#pragma endasm\r
+#else  /* __FASM__  */ \r
+/* THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU     */\r
+/* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR     */\r
+/* ELIGIBILITY FOR ANY PURPOSES.                                                 */\r
+/*                 (C) Fujitsu Microelectronics Europe GmbH                      */\r
+/*  */\r
+/* ************************************************************************* */\r
+/*                   Fujitsu Microelectronics Europe GmbH                        */\r
+/*                 http://emea.fujitsu.com/microelectronics  */\r
+/*                                                                           */\r
+/* THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */\r
+/* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */\r
+/* ELIGIBILITY FOR ANY PURPOSES                                              */\r
+/*                 (C) Fujitsu Microelectronics Europe GmbH                  */\r
+/* ************************************************************************* */\r
+/* ---------------------------------------------------------------------- */\r
+/* $Id: mb91467D.h,v 1.13 2007/08/08 10:56:26 mwilla Exp $ */\r
+/* ---------------------------------------------------------------------- */\r
+/*                      */\r
+/* Id: mb91467D.iow,v 1.1 2005/10/14 11:25:42 umarke Exp  */\r
+/*      - Initial Version based on mb91V460A, v1.1 */\r
+/* Id: mb91467D.iow,v 1.2 2005/10/14 09:47:18 umarke Exp   */\r
+/*      - Littel Endian IFxDTA_SWP_yz added     */\r
+/* Id: mb91467D.iow,v 1.3 2005/11/18 06:55:29 umarke Exp   */\r
+/*      - No. of port register reduced to the no. of registers in MB91467D */\r
+/*      - Registers added: FMWT2, FMCR */\r
+/*      - Addapted Bit Names of Register FMCS     */\r
+/* Id: mb91467D.iow,v 1.4 2005/11/18 06:55:29 umarke Exp   */\r
+/*      - OCS01 and OCS23 added         */\r
+/* Id: mb91467D.iow,v 1.6 2006/01/13 08:58:51 umarke Exp  */\r
+/*      - Bitnames of  CLKR changed                                                    */\r
+/* Id: mb91467D.iow,v 1.7 2006/01/26 15:42:05 umarke Exp   */\r
+/*      - REGSEL, BRPERx added */\r
+/*      - REGCTR added   */\r
+/*      - LVSEL added  */\r
+/*      - Old Bitname of CLKR added                             */\r
+/* Id: mb91467D.iow,v 1.8 2006/02/27 10:31:28 umarke Exp   */\r
+/*      - BGR10x und BGR00x added  */\r
+/*      - PCNx, ITBAx, ITMKx, IDARx_D7 added    */\r
+/*      - SGCRH, SGCRL added */\r
+/*      - Bit ACSR_MD added */\r
+/*      - Bit CSCFG_PLLLOCK and CSCFG_RCSEL          */\r
+/*      - CUCR: Bits shifted to correct position    */\r
+/*      - CUTR1 & CUTR2 bits renamed to TDR14 instead of TR14     */\r
+/*      - CMCR_RUN renamed to CMCR_FMODRUN and shifted               */\r
+/*      - Bitnames of OSCCx and OSCRx added */\r
+/*      - FSVx, BSVx and FSCRx added */\r
+/*      - RBSYNC, CBSYNCx  */\r
+/* Id: mb91467D.iow,v 1.9 2006/02/27 11:56:23 umarke Exp  */\r
+/*      - changed Adress of REGSEL */\r
+/* $Id: mb91467D.h,v 1.13 2007/08/08 10:56:26 mwilla Exp $  */\r
+/*      - Grouped CANPRE_CPCKS */\r
+/*      - Bitdescription of HLRC added */\r
+/* BIT-STRUCTURE-DEFINITIONS */\r
+\r
+typedef unsigned char          IO_BYTE;\r
+typedef unsigned short         IO_WORD;\r
+typedef unsigned long          IO_LWORD;\r
+typedef const unsigned short   IO_WORD_READ;\r
+\r
+typedef union{   /* Port Data Register */\r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PDR00STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PDR01STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PDR02STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PDR03STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PDR04STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PDR05STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PDR06STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PDR07STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PDR08STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PDR09STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE  :1;\r
+  }bit;\r
+ }PDR10STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PDR13STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PDR14STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PDR15STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PDR16STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+  }bit;\r
+ }PDR17STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PDR18STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PDR19STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PDR20STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PDR22STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PDR23STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PDR24STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PDR25STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PDR26STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PDR27STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PDR29STR;\r
+typedef union{   /* External Interrupt 0-7 */\r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _ER7 :1;\r
+    IO_BYTE _ER6 :1;\r
+    IO_BYTE _ER5 :1;\r
+    IO_BYTE _ER4 :1;\r
+    IO_BYTE _ER3 :1;\r
+    IO_BYTE _ER2 :1;\r
+    IO_BYTE _ER1 :1;\r
+    IO_BYTE _ER0 :1;\r
+  }bit;\r
+ }EIRR0STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _EN7 :1;\r
+    IO_BYTE _EN6 :1;\r
+    IO_BYTE _EN5 :1;\r
+    IO_BYTE _EN4 :1;\r
+    IO_BYTE _EN3 :1;\r
+    IO_BYTE _EN2 :1;\r
+    IO_BYTE _EN1 :1;\r
+    IO_BYTE _EN0 :1;\r
+  }bit;\r
+ }ENIR0STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _LB7 :1;\r
+    IO_WORD _LA7 :1;\r
+    IO_WORD _LB6 :1;\r
+    IO_WORD _LA6 :1;\r
+    IO_WORD _LB5 :1;\r
+    IO_WORD _LA5 :1;\r
+    IO_WORD _LB4 :1;\r
+    IO_WORD _LA4 :1;\r
+    IO_WORD _LB3 :1;\r
+    IO_WORD _LA3 :1;\r
+    IO_WORD _LB2 :1;\r
+    IO_WORD _LA2 :1;\r
+    IO_WORD _LB1 :1;\r
+    IO_WORD _LA1 :1;\r
+    IO_WORD _LB0 :1;\r
+    IO_WORD _LA0 :1;\r
+  }bit;\r
+ }ELVR0STR;\r
+typedef union{   /* External Interrupt 8-15 */\r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _ER15 :1;\r
+    IO_BYTE _ER14 :1;\r
+    IO_BYTE _ER13 :1;\r
+    IO_BYTE _ER12 :1;\r
+    IO_BYTE _ER11 :1;\r
+    IO_BYTE _ER10 :1;\r
+    IO_BYTE _ER9 :1;\r
+    IO_BYTE _ER8 :1;\r
+  }bit;\r
+ }EIRR1STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _EN15 :1;\r
+    IO_BYTE _EN14 :1;\r
+    IO_BYTE _EN13 :1;\r
+    IO_BYTE _EN12 :1;\r
+    IO_BYTE _EN11 :1;\r
+    IO_BYTE _EN10 :1;\r
+    IO_BYTE _EN9 :1;\r
+    IO_BYTE _EN8 :1;\r
+  }bit;\r
+ }ENIR1STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _LB15 :1;\r
+    IO_WORD _LA15 :1;\r
+    IO_WORD _LB14 :1;\r
+    IO_WORD _LA14 :1;\r
+    IO_WORD _LB13 :1;\r
+    IO_WORD _LA13 :1;\r
+    IO_WORD _LB12 :1;\r
+    IO_WORD _LA12 :1;\r
+    IO_WORD _LB11 :1;\r
+    IO_WORD _LA11 :1;\r
+    IO_WORD _LB10 :1;\r
+    IO_WORD _LA10 :1;\r
+    IO_WORD _LB9 :1;\r
+    IO_WORD _LA9 :1;\r
+    IO_WORD _LB8 :1;\r
+    IO_WORD _LA8 :1;\r
+  }bit;\r
+ }ELVR1STR;\r
+typedef union{   /* DLYI/I-unit */\r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _DLYI :1;\r
+  }bit;\r
+ }DICRSTR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _MHALTI :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _LVL4 :1;\r
+    IO_BYTE _LVL3 :1;\r
+    IO_BYTE _LVL2 :1;\r
+    IO_BYTE _LVL1 :1;\r
+    IO_BYTE _LVL0 :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE _LVL :5;\r
+  }bitc;\r
+ }HRCLSTR;\r
+typedef union{   /* USART (LIN) 2 */\r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _PEN :1;\r
+    IO_BYTE _P :1;\r
+    IO_BYTE _SBL :1;\r
+    IO_BYTE _CL :1;\r
+    IO_BYTE _AD :1;\r
+    IO_BYTE _CRE :1;\r
+    IO_BYTE _RXE :1;\r
+    IO_BYTE _TXE :1;\r
+  }bit;\r
+ }SCR02STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _MD1 :1;\r
+    IO_BYTE _MD0 :1;\r
+    IO_BYTE _OTO :1;\r
+    IO_BYTE _EXT :1;\r
+    IO_BYTE _REST :1;\r
+    IO_BYTE _UPCL :1;\r
+    IO_BYTE _SCKE :1;\r
+    IO_BYTE _SOE :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE _MD :2;\r
+  }bitc;\r
+ }SMR02STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _PE :1;\r
+    IO_BYTE _ORE :1;\r
+    IO_BYTE _FRE :1;\r
+    IO_BYTE _RDRF :1;\r
+    IO_BYTE _TDRE :1;\r
+    IO_BYTE _BDS :1;\r
+    IO_BYTE _RIE :1;\r
+    IO_BYTE _TIE :1;\r
+  }bit;\r
+ }SSR02STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _LBIE :1;\r
+    IO_BYTE _LBD :1;\r
+    IO_BYTE _LBL1 :1;\r
+    IO_BYTE _LBL0 :1;\r
+    IO_BYTE _SOPE :1;\r
+    IO_BYTE _SIOP :1;\r
+    IO_BYTE _CCO :1;\r
+    IO_BYTE _SCES :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE _LBL :2;\r
+  }bitc;\r
+ }ESCR02STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _INV :1;\r
+    IO_BYTE _LBR :1;\r
+    IO_BYTE _MS :1;\r
+    IO_BYTE _SCDE :1;\r
+    IO_BYTE _SSM :1;\r
+    IO_BYTE _BIE :1;\r
+    IO_BYTE _RBI :1;\r
+    IO_BYTE _TBI :1;\r
+  }bit;\r
+ }ECCR02STR;\r
+typedef union{   /* USART (LIN) 4 with FIFO */\r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _PEN :1;\r
+    IO_BYTE _P :1;\r
+    IO_BYTE _SBL :1;\r
+    IO_BYTE _CL :1;\r
+    IO_BYTE _AD :1;\r
+    IO_BYTE _CRE :1;\r
+    IO_BYTE _RXE :1;\r
+    IO_BYTE _TXE :1;\r
+  }bit;\r
+ }SCR04STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _MD1 :1;\r
+    IO_BYTE _MD0 :1;\r
+    IO_BYTE _OTO :1;\r
+    IO_BYTE _EXT :1;\r
+    IO_BYTE _REST :1;\r
+    IO_BYTE _UPCL :1;\r
+    IO_BYTE _SCKE :1;\r
+    IO_BYTE _SOE :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE _MD :2;\r
+  }bitc;\r
+ }SMR04STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _PE :1;\r
+    IO_BYTE _ORE :1;\r
+    IO_BYTE _FRE :1;\r
+    IO_BYTE _RDRF :1;\r
+    IO_BYTE _TDRE :1;\r
+    IO_BYTE _BDS :1;\r
+    IO_BYTE _RIE :1;\r
+    IO_BYTE _TIE :1;\r
+  }bit;\r
+ }SSR04STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _LBIE :1;\r
+    IO_BYTE _LBD :1;\r
+    IO_BYTE _LBL1 :1;\r
+    IO_BYTE _LBL0 :1;\r
+    IO_BYTE _SOPE :1;\r
+    IO_BYTE _SIOP :1;\r
+    IO_BYTE _CCO :1;\r
+    IO_BYTE _SCES :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE _LBL :2;\r
+  }bitc;\r
+ }ESCR04STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _INV :1;\r
+    IO_BYTE _LBR :1;\r
+    IO_BYTE _MS :1;\r
+    IO_BYTE _SCDE :1;\r
+    IO_BYTE _SSM :1;\r
+    IO_BYTE _BIE :1;\r
+    IO_BYTE _RBI :1;\r
+    IO_BYTE _TBI :1;\r
+  }bit;\r
+ }ECCR04STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _RXL3 :1;\r
+    IO_BYTE _RXL2 :1;\r
+    IO_BYTE _RXL1 :1;\r
+    IO_BYTE _RXL0 :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _ERX :1;\r
+    IO_BYTE _ETX :1;\r
+    IO_BYTE _SVD :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE _RXL :4;\r
+  }bitc;\r
+ }FCR04STR;\r
+typedef union{   /* USART (LIN) 5 with FIFO */\r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _PEN :1;\r
+    IO_BYTE _P :1;\r
+    IO_BYTE _SBL :1;\r
+    IO_BYTE _CL :1;\r
+    IO_BYTE _AD :1;\r
+    IO_BYTE _CRE :1;\r
+    IO_BYTE _RXE :1;\r
+    IO_BYTE _TXE :1;\r
+  }bit;\r
+ }SCR05STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _MD1 :1;\r
+    IO_BYTE _MD0 :1;\r
+    IO_BYTE _OTO :1;\r
+    IO_BYTE _EXT :1;\r
+    IO_BYTE _REST :1;\r
+    IO_BYTE _UPCL :1;\r
+    IO_BYTE _SCKE :1;\r
+    IO_BYTE _SOE :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE _MD :2;\r
+  }bitc;\r
+ }SMR05STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _PE :1;\r
+    IO_BYTE _ORE :1;\r
+    IO_BYTE _FRE :1;\r
+    IO_BYTE _RDRF :1;\r
+    IO_BYTE _TDRE :1;\r
+    IO_BYTE _BDS :1;\r
+    IO_BYTE _RIE :1;\r
+    IO_BYTE _TIE :1;\r
+  }bit;\r
+ }SSR05STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _LBIE :1;\r
+    IO_BYTE _LBD :1;\r
+    IO_BYTE _LBL1 :1;\r
+    IO_BYTE _LBL0 :1;\r
+    IO_BYTE _SOPE :1;\r
+    IO_BYTE _SIOP :1;\r
+    IO_BYTE _CCO :1;\r
+    IO_BYTE _SCES :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE _LBL :2;\r
+  }bitc;\r
+ }ESCR05STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _INV :1;\r
+    IO_BYTE _LBR :1;\r
+    IO_BYTE _MS :1;\r
+    IO_BYTE _SCDE :1;\r
+    IO_BYTE _SSM :1;\r
+    IO_BYTE _BIE :1;\r
+    IO_BYTE _RBI :1;\r
+    IO_BYTE _TBI :1;\r
+  }bit;\r
+ }ECCR05STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _RXL3 :1;\r
+    IO_BYTE _RXL2 :1;\r
+    IO_BYTE _RXL1 :1;\r
+    IO_BYTE _RXL0 :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _ERX :1;\r
+    IO_BYTE _ETX :1;\r
+    IO_BYTE _SVD :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE _RXL :4;\r
+  }bitc;\r
+ }FCR05STR;\r
+typedef union{   /* USART (LIN) 6 with FIFO */\r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _PEN :1;\r
+    IO_BYTE _P :1;\r
+    IO_BYTE _SBL :1;\r
+    IO_BYTE _CL :1;\r
+    IO_BYTE _AD :1;\r
+    IO_BYTE _CRE :1;\r
+    IO_BYTE _RXE :1;\r
+    IO_BYTE _TXE :1;\r
+  }bit;\r
+ }SCR06STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _MD1 :1;\r
+    IO_BYTE _MD0 :1;\r
+    IO_BYTE _OTO :1;\r
+    IO_BYTE _EXT :1;\r
+    IO_BYTE _REST :1;\r
+    IO_BYTE _UPCL :1;\r
+    IO_BYTE _SCKE :1;\r
+    IO_BYTE _SOE :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE _MD :2;\r
+  }bitc;\r
+ }SMR06STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _PE :1;\r
+    IO_BYTE _ORE :1;\r
+    IO_BYTE _FRE :1;\r
+    IO_BYTE _RDRF :1;\r
+    IO_BYTE _TDRE :1;\r
+    IO_BYTE _BDS :1;\r
+    IO_BYTE _RIE :1;\r
+    IO_BYTE _TIE :1;\r
+  }bit;\r
+ }SSR06STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _LBIE :1;\r
+    IO_BYTE _LBD :1;\r
+    IO_BYTE _LBL1 :1;\r
+    IO_BYTE _LBL0 :1;\r
+    IO_BYTE _SOPE :1;\r
+    IO_BYTE _SIOP :1;\r
+    IO_BYTE _CCO :1;\r
+    IO_BYTE _SCES :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE _LBL :2;\r
+  }bitc;\r
+ }ESCR06STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _INV :1;\r
+    IO_BYTE _LBR :1;\r
+    IO_BYTE _MS :1;\r
+    IO_BYTE _SCDE :1;\r
+    IO_BYTE _SSM :1;\r
+    IO_BYTE _BIE :1;\r
+    IO_BYTE _RBI :1;\r
+    IO_BYTE _TBI :1;\r
+  }bit;\r
+ }ECCR06STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _RXL3 :1;\r
+    IO_BYTE _RXL2 :1;\r
+    IO_BYTE _RXL1 :1;\r
+    IO_BYTE _RXL0 :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _ERX :1;\r
+    IO_BYTE _ETX :1;\r
+    IO_BYTE _SVD :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE _RXL :4;\r
+  }bitc;\r
+ }FCR06STR;\r
+typedef union{   /* USART (LIN) 7 with FIFO */\r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _PEN :1;\r
+    IO_BYTE _P :1;\r
+    IO_BYTE _SBL :1;\r
+    IO_BYTE _CL :1;\r
+    IO_BYTE _AD :1;\r
+    IO_BYTE _CRE :1;\r
+    IO_BYTE _RXE :1;\r
+    IO_BYTE _TXE :1;\r
+  }bit;\r
+ }SCR07STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _MD1 :1;\r
+    IO_BYTE _MD0 :1;\r
+    IO_BYTE _OTO :1;\r
+    IO_BYTE _EXT :1;\r
+    IO_BYTE _REST :1;\r
+    IO_BYTE _UPCL :1;\r
+    IO_BYTE _SCKE :1;\r
+    IO_BYTE _SOE :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE _MD :2;\r
+  }bitc;\r
+ }SMR07STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _PE :1;\r
+    IO_BYTE _ORE :1;\r
+    IO_BYTE _FRE :1;\r
+    IO_BYTE _RDRF :1;\r
+    IO_BYTE _TDRE :1;\r
+    IO_BYTE _BDS :1;\r
+    IO_BYTE _RIE :1;\r
+    IO_BYTE _TIE :1;\r
+  }bit;\r
+ }SSR07STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _LBIE :1;\r
+    IO_BYTE _LBD :1;\r
+    IO_BYTE _LBL1 :1;\r
+    IO_BYTE _LBL0 :1;\r
+    IO_BYTE _SOPE :1;\r
+    IO_BYTE _SIOP :1;\r
+    IO_BYTE _CCO :1;\r
+    IO_BYTE _SCES :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE _LBL :2;\r
+  }bitc;\r
+ }ESCR07STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _INV :1;\r
+    IO_BYTE _LBR :1;\r
+    IO_BYTE _MS :1;\r
+    IO_BYTE _SCDE :1;\r
+    IO_BYTE _SSM :1;\r
+    IO_BYTE _BIE :1;\r
+    IO_BYTE _RBI :1;\r
+    IO_BYTE _TBI :1;\r
+  }bit;\r
+ }ECCR07STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _RXL3 :1;\r
+    IO_BYTE _RXL2 :1;\r
+    IO_BYTE _RXL1 :1;\r
+    IO_BYTE _RXL0 :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _ERX :1;\r
+    IO_BYTE _ETX :1;\r
+    IO_BYTE _SVD :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE _RXL :4;\r
+  }bitc;\r
+ }FCR07STR;\r
+typedef union{   /* Stepper Motor 0 */\r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD _D9 :1;\r
+    IO_WORD _D8 :1;\r
+    IO_WORD _D7 :1;\r
+    IO_WORD _D6 :1;\r
+    IO_WORD _D5 :1;\r
+    IO_WORD _D4 :1;\r
+    IO_WORD _D3 :1;\r
+    IO_WORD _D2 :1;\r
+    IO_WORD _D1 :1;\r
+    IO_WORD _D0 :1;\r
+  }bit;\r
+ }PWC20STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD _D9 :1;\r
+    IO_WORD _D8 :1;\r
+    IO_WORD _D7 :1;\r
+    IO_WORD _D6 :1;\r
+    IO_WORD _D5 :1;\r
+    IO_WORD _D4 :1;\r
+    IO_WORD _D3 :1;\r
+    IO_WORD _D2 :1;\r
+    IO_WORD _D1 :1;\r
+    IO_WORD _D0 :1;\r
+  }bit;\r
+ }PWC10STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE _BS :1;\r
+    IO_BYTE _P2 :1;\r
+    IO_BYTE _P1 :1;\r
+    IO_BYTE _P0 :1;\r
+    IO_BYTE _M2 :1;\r
+    IO_BYTE _M1 :1;\r
+    IO_BYTE _M0 :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE _P :3;\r
+    IO_BYTE _M :3;\r
+  }bitc;\r
+ }PWS20STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _P2 :1;\r
+    IO_BYTE _P1 :1;\r
+    IO_BYTE _P0 :1;\r
+    IO_BYTE _M2 :1;\r
+    IO_BYTE _M1 :1;\r
+    IO_BYTE _M0 :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE _P :3;\r
+    IO_BYTE _M :3;\r
+  }bitc;\r
+ }PWS10STR;\r
+typedef union{   /* Stepper Motor 1 */\r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD _D9 :1;\r
+    IO_WORD _D8 :1;\r
+    IO_WORD _D7 :1;\r
+    IO_WORD _D6 :1;\r
+    IO_WORD _D5 :1;\r
+    IO_WORD _D4 :1;\r
+    IO_WORD _D3 :1;\r
+    IO_WORD _D2 :1;\r
+    IO_WORD _D1 :1;\r
+    IO_WORD _D0 :1;\r
+  }bit;\r
+ }PWC21STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD _D9 :1;\r
+    IO_WORD _D8 :1;\r
+    IO_WORD _D7 :1;\r
+    IO_WORD _D6 :1;\r
+    IO_WORD _D5 :1;\r
+    IO_WORD _D4 :1;\r
+    IO_WORD _D3 :1;\r
+    IO_WORD _D2 :1;\r
+    IO_WORD _D1 :1;\r
+    IO_WORD _D0 :1;\r
+  }bit;\r
+ }PWC11STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE _BS :1;\r
+    IO_BYTE _P2 :1;\r
+    IO_BYTE _P1 :1;\r
+    IO_BYTE _P0 :1;\r
+    IO_BYTE _M2 :1;\r
+    IO_BYTE _M1 :1;\r
+    IO_BYTE _M0 :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE _P :3;\r
+    IO_BYTE _M :3;\r
+  }bitc;\r
+ }PWS21STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _P2 :1;\r
+    IO_BYTE _P1 :1;\r
+    IO_BYTE _P0 :1;\r
+    IO_BYTE _M2 :1;\r
+    IO_BYTE _M1 :1;\r
+    IO_BYTE _M0 :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE _P :3;\r
+    IO_BYTE _M :3;\r
+  }bitc;\r
+ }PWS11STR;\r
+typedef union{   /* Stepper Motor 2 */\r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD _D9 :1;\r
+    IO_WORD _D8 :1;\r
+    IO_WORD _D7 :1;\r
+    IO_WORD _D6 :1;\r
+    IO_WORD _D5 :1;\r
+    IO_WORD _D4 :1;\r
+    IO_WORD _D3 :1;\r
+    IO_WORD _D2 :1;\r
+    IO_WORD _D1 :1;\r
+    IO_WORD _D0 :1;\r
+  }bit;\r
+ }PWC22STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD _D9 :1;\r
+    IO_WORD _D8 :1;\r
+    IO_WORD _D7 :1;\r
+    IO_WORD _D6 :1;\r
+    IO_WORD _D5 :1;\r
+    IO_WORD _D4 :1;\r
+    IO_WORD _D3 :1;\r
+    IO_WORD _D2 :1;\r
+    IO_WORD _D1 :1;\r
+    IO_WORD _D0 :1;\r
+  }bit;\r
+ }PWC12STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE _BS :1;\r
+    IO_BYTE _P2 :1;\r
+    IO_BYTE _P1 :1;\r
+    IO_BYTE _P0 :1;\r
+    IO_BYTE _M2 :1;\r
+    IO_BYTE _M1 :1;\r
+    IO_BYTE _M0 :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE _P :3;\r
+    IO_BYTE _M :3;\r
+  }bitc;\r
+ }PWS22STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _P2 :1;\r
+    IO_BYTE _P1 :1;\r
+    IO_BYTE _P0 :1;\r
+    IO_BYTE _M2 :1;\r
+    IO_BYTE _M1 :1;\r
+    IO_BYTE _M0 :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE _P :3;\r
+    IO_BYTE _M :3;\r
+  }bitc;\r
+ }PWS12STR;\r
+typedef union{   /* Stepper Motor 3 */\r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD _D9 :1;\r
+    IO_WORD _D8 :1;\r
+    IO_WORD _D7 :1;\r
+    IO_WORD _D6 :1;\r
+    IO_WORD _D5 :1;\r
+    IO_WORD _D4 :1;\r
+    IO_WORD _D3 :1;\r
+    IO_WORD _D2 :1;\r
+    IO_WORD _D1 :1;\r
+    IO_WORD _D0 :1;\r
+  }bit;\r
+ }PWC23STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD _D9 :1;\r
+    IO_WORD _D8 :1;\r
+    IO_WORD _D7 :1;\r
+    IO_WORD _D6 :1;\r
+    IO_WORD _D5 :1;\r
+    IO_WORD _D4 :1;\r
+    IO_WORD _D3 :1;\r
+    IO_WORD _D2 :1;\r
+    IO_WORD _D1 :1;\r
+    IO_WORD _D0 :1;\r
+  }bit;\r
+ }PWC13STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE _BS :1;\r
+    IO_BYTE _P2 :1;\r
+    IO_BYTE _P1 :1;\r
+    IO_BYTE _P0 :1;\r
+    IO_BYTE _M2 :1;\r
+    IO_BYTE _M1 :1;\r
+    IO_BYTE _M0 :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE _P :3;\r
+    IO_BYTE _M :3;\r
+  }bitc;\r
+ }PWS23STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _P2 :1;\r
+    IO_BYTE _P1 :1;\r
+    IO_BYTE _P0 :1;\r
+    IO_BYTE _M2 :1;\r
+    IO_BYTE _M1 :1;\r
+    IO_BYTE _M0 :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE _P :3;\r
+    IO_BYTE _M :3;\r
+  }bitc;\r
+ }PWS13STR;\r
+typedef union{   /* Stepper Motor 4 */\r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD _D9 :1;\r
+    IO_WORD _D8 :1;\r
+    IO_WORD _D7 :1;\r
+    IO_WORD _D6 :1;\r
+    IO_WORD _D5 :1;\r
+    IO_WORD _D4 :1;\r
+    IO_WORD _D3 :1;\r
+    IO_WORD _D2 :1;\r
+    IO_WORD _D1 :1;\r
+    IO_WORD _D0 :1;\r
+  }bit;\r
+ }PWC24STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD _D9 :1;\r
+    IO_WORD _D8 :1;\r
+    IO_WORD _D7 :1;\r
+    IO_WORD _D6 :1;\r
+    IO_WORD _D5 :1;\r
+    IO_WORD _D4 :1;\r
+    IO_WORD _D3 :1;\r
+    IO_WORD _D2 :1;\r
+    IO_WORD _D1 :1;\r
+    IO_WORD _D0 :1;\r
+  }bit;\r
+ }PWC14STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE _BS :1;\r
+    IO_BYTE _P2 :1;\r
+    IO_BYTE _P1 :1;\r
+    IO_BYTE _P0 :1;\r
+    IO_BYTE _M2 :1;\r
+    IO_BYTE _M1 :1;\r
+    IO_BYTE _M0 :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE _P :3;\r
+    IO_BYTE _M :3;\r
+  }bitc;\r
+ }PWS24STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _P2 :1;\r
+    IO_BYTE _P1 :1;\r
+    IO_BYTE _P0 :1;\r
+    IO_BYTE _M2 :1;\r
+    IO_BYTE _M1 :1;\r
+    IO_BYTE _M0 :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE _P :3;\r
+    IO_BYTE _M :3;\r
+  }bitc;\r
+ }PWS14STR;\r
+typedef union{   /* Stepper Motor 5 */\r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD _D9 :1;\r
+    IO_WORD _D8 :1;\r
+    IO_WORD _D7 :1;\r
+    IO_WORD _D6 :1;\r
+    IO_WORD _D5 :1;\r
+    IO_WORD _D4 :1;\r
+    IO_WORD _D3 :1;\r
+    IO_WORD _D2 :1;\r
+    IO_WORD _D1 :1;\r
+    IO_WORD _D0 :1;\r
+  }bit;\r
+ }PWC25STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD _D9 :1;\r
+    IO_WORD _D8 :1;\r
+    IO_WORD _D7 :1;\r
+    IO_WORD _D6 :1;\r
+    IO_WORD _D5 :1;\r
+    IO_WORD _D4 :1;\r
+    IO_WORD _D3 :1;\r
+    IO_WORD _D2 :1;\r
+    IO_WORD _D1 :1;\r
+    IO_WORD _D0 :1;\r
+  }bit;\r
+ }PWC15STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE _BS :1;\r
+    IO_BYTE _P2 :1;\r
+    IO_BYTE _P1 :1;\r
+    IO_BYTE _P0 :1;\r
+    IO_BYTE _M2 :1;\r
+    IO_BYTE _M1 :1;\r
+    IO_BYTE _M0 :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE _P :3;\r
+    IO_BYTE _M :3;\r
+  }bitc;\r
+ }PWS25STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _P2 :1;\r
+    IO_BYTE _P1 :1;\r
+    IO_BYTE _P0 :1;\r
+    IO_BYTE _M2 :1;\r
+    IO_BYTE _M1 :1;\r
+    IO_BYTE _M0 :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE _P :3;\r
+    IO_BYTE _M :3;\r
+  }bitc;\r
+ }PWS15STR;\r
+typedef union{   /* Stepper Motor Control 0-5 */\r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _S2 :1;\r
+    IO_BYTE _P2 :1;\r
+    IO_BYTE _P1 :1;\r
+    IO_BYTE _P0 :1;\r
+    IO_BYTE _CE :1;\r
+    IO_BYTE _SC :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE :1;\r
+    IO_BYTE _P :3;\r
+  }bitc;\r
+ }PWC0STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _S2 :1;\r
+    IO_BYTE _P2 :1;\r
+    IO_BYTE _P1 :1;\r
+    IO_BYTE _P0 :1;\r
+    IO_BYTE _CE :1;\r
+    IO_BYTE _SC :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE :1;\r
+    IO_BYTE _P :3;\r
+  }bitc;\r
+ }PWC1STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _S2 :1;\r
+    IO_BYTE _P2 :1;\r
+    IO_BYTE _P1 :1;\r
+    IO_BYTE _P0 :1;\r
+    IO_BYTE _CE :1;\r
+    IO_BYTE _SC :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE :1;\r
+    IO_BYTE _P :3;\r
+  }bitc;\r
+ }PWC2STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _S2 :1;\r
+    IO_BYTE _P2 :1;\r
+    IO_BYTE _P1 :1;\r
+    IO_BYTE _P0 :1;\r
+    IO_BYTE _CE :1;\r
+    IO_BYTE _SC :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE :1;\r
+    IO_BYTE _P :3;\r
+  }bitc;\r
+ }PWC3STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _S2 :1;\r
+    IO_BYTE _P2 :1;\r
+    IO_BYTE _P1 :1;\r
+    IO_BYTE _P0 :1;\r
+    IO_BYTE _CE :1;\r
+    IO_BYTE _SC :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE :1;\r
+    IO_BYTE _P :3;\r
+  }bitc;\r
+ }PWC4STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _S2 :1;\r
+    IO_BYTE _P2 :1;\r
+    IO_BYTE _P1 :1;\r
+    IO_BYTE _P0 :1;\r
+    IO_BYTE _CE :1;\r
+    IO_BYTE _SC :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE :1;\r
+    IO_BYTE _P :3;\r
+  }bitc;\r
+ }PWC5STR;\r
+typedef union{   /* I2C 0 */\r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _BER :1;\r
+    IO_BYTE _BEIE :1;\r
+    IO_BYTE _SCC :1;\r
+    IO_BYTE _MSS :1;\r
+    IO_BYTE _ACK :1;\r
+    IO_BYTE _GCAA :1;\r
+    IO_BYTE _INTE :1;\r
+    IO_BYTE _INT :1;\r
+  }bit;\r
+ }IBCR0STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _BB :1;\r
+    IO_BYTE _RSC :1;\r
+    IO_BYTE _AL :1;\r
+    IO_BYTE _LRB :1;\r
+    IO_BYTE _TRX :1;\r
+    IO_BYTE _AAS :1;\r
+    IO_BYTE _GCA :1;\r
+    IO_BYTE _ADT :1;\r
+  }bit;\r
+ }IBSR0STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD _TA9 :1;\r
+    IO_WORD _TA8 :1;\r
+    IO_WORD _TA7 :1;\r
+    IO_WORD _TA6 :1;\r
+    IO_WORD _TA5 :1;\r
+    IO_WORD _TA4 :1;\r
+    IO_WORD _TA3 :1;\r
+    IO_WORD _TA2 :1;\r
+    IO_WORD _TA1 :1;\r
+    IO_WORD _TA0 :1;\r
+  }bit;\r
+ }ITBA0STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _TA9 :1;\r
+    IO_BYTE _TA8 :1;\r
+  }bit;\r
+ }ITBAH0STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _TA7 :1;\r
+    IO_BYTE _TA6 :1;\r
+    IO_BYTE _TA5 :1;\r
+    IO_BYTE _TA4 :1;\r
+    IO_BYTE _TA3 :1;\r
+    IO_BYTE _TA2 :1;\r
+    IO_BYTE _TA1 :1;\r
+    IO_BYTE _TA0 :1;\r
+  }bit;\r
+ }ITBAL0STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _ENTB :1;\r
+    IO_WORD _RAL :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD _TM9 :1;\r
+    IO_WORD _TM8 :1;\r
+    IO_WORD _TM7 :1;\r
+    IO_WORD _TM6 :1;\r
+    IO_WORD _TM5 :1;\r
+    IO_WORD _TM4 :1;\r
+    IO_WORD _TM3 :1;\r
+    IO_WORD _TM2 :1;\r
+    IO_WORD _TM1 :1;\r
+    IO_WORD _TM0 :1;\r
+  }bit;\r
+ }ITMK0STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _ENTB :1;\r
+    IO_BYTE _RAL :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _TM9 :1;\r
+    IO_BYTE _TM8 :1;\r
+  }bit;\r
+ }ITMKH0STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _TM7 :1;\r
+    IO_BYTE _TM6 :1;\r
+    IO_BYTE _TM5 :1;\r
+    IO_BYTE _TM4 :1;\r
+    IO_BYTE _TM3 :1;\r
+    IO_BYTE _TM2 :1;\r
+    IO_BYTE _TM1 :1;\r
+    IO_BYTE _TM0 :1;\r
+  }bit;\r
+ }ITMKL0STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _ENSB :1;\r
+    IO_BYTE _SM6 :1;\r
+    IO_BYTE _SM5 :1;\r
+    IO_BYTE _SM4 :1;\r
+    IO_BYTE _SM3 :1;\r
+    IO_BYTE _SM2 :1;\r
+    IO_BYTE _SM1 :1;\r
+    IO_BYTE _SM0 :1;\r
+  }bit;\r
+ }ISMK0STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE _SA6 :1;\r
+    IO_BYTE _SA5 :1;\r
+    IO_BYTE _SA4 :1;\r
+    IO_BYTE _SA3 :1;\r
+    IO_BYTE _SA2 :1;\r
+    IO_BYTE _SA1 :1;\r
+    IO_BYTE _SA0 :1;\r
+  }bit;\r
+ }ISBA0STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }IDAR0STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE _NSF :1;\r
+    IO_BYTE _EN :1;\r
+    IO_BYTE _CS4 :1;\r
+    IO_BYTE _CS3 :1;\r
+    IO_BYTE _CS2 :1;\r
+    IO_BYTE _CS1 :1;\r
+    IO_BYTE _CS0 :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE _CS :5;\r
+  }bitc;\r
+ }ICCR0STR;\r
+typedef union{   /* PPG Control 4-7 */\r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _TSEL33 :1;\r
+    IO_WORD _TSEL32 :1;\r
+    IO_WORD _TSEL31 :1;\r
+    IO_WORD _TSEL30 :1;\r
+    IO_WORD _TSEL23 :1;\r
+    IO_WORD _TSEL22 :1;\r
+    IO_WORD _TSEL21 :1;\r
+    IO_WORD _TSEL20 :1;\r
+    IO_WORD _TSEL13 :1;\r
+    IO_WORD _TSEL12 :1;\r
+    IO_WORD _TSEL11 :1;\r
+    IO_WORD _TSEL10 :1;\r
+    IO_WORD _TSEL03 :1;\r
+    IO_WORD _TSEL02 :1;\r
+    IO_WORD _TSEL01 :1;\r
+    IO_WORD _TSEL00 :1;\r
+  }bit;\r
+ }GCN11STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _EN3 :1;\r
+    IO_BYTE _EN2 :1;\r
+    IO_BYTE _EN1 :1;\r
+    IO_BYTE _EN0 :1;\r
+  }bit;\r
+ }GCN21STR;\r
+typedef union{   /* PPG Control 8-11 */\r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _TSEL33 :1;\r
+    IO_WORD _TSEL32 :1;\r
+    IO_WORD _TSEL31 :1;\r
+    IO_WORD _TSEL30 :1;\r
+    IO_WORD _TSEL23 :1;\r
+    IO_WORD _TSEL22 :1;\r
+    IO_WORD _TSEL21 :1;\r
+    IO_WORD _TSEL20 :1;\r
+    IO_WORD _TSEL13 :1;\r
+    IO_WORD _TSEL12 :1;\r
+    IO_WORD _TSEL11 :1;\r
+    IO_WORD _TSEL10 :1;\r
+    IO_WORD _TSEL03 :1;\r
+    IO_WORD _TSEL02 :1;\r
+    IO_WORD _TSEL01 :1;\r
+    IO_WORD _TSEL00 :1;\r
+  }bit;\r
+ }GCN12STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _EN3 :1;\r
+    IO_BYTE _EN2 :1;\r
+    IO_BYTE _EN1 :1;\r
+    IO_BYTE _EN0 :1;\r
+  }bit;\r
+ }GCN22STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _CNTE :1;\r
+    IO_WORD _STGR :1;\r
+    IO_WORD _MDSE :1;\r
+    IO_WORD _RTRG :1;\r
+    IO_WORD _CKS1 :1;\r
+    IO_WORD _CKS0 :1;\r
+    IO_WORD _PGMS :1;\r
+    IO_WORD  :1;\r
+    IO_WORD _EGS1 :1;\r
+    IO_WORD _EGS0 :1;\r
+    IO_WORD _IREN :1;\r
+    IO_WORD _IRQF :1;\r
+    IO_WORD _IRS1 :1;\r
+    IO_WORD _IRS0 :1;\r
+    IO_WORD  :1;\r
+    IO_WORD _OSEL :1;\r
+  }bit;\r
+  struct{\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD _CKS :2;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD _EGS :2;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD _IRS :2;\r
+  }bitc;\r
+ }PCN04STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _CNTE :1;\r
+    IO_BYTE _STGR :1;\r
+    IO_BYTE _MDSE :1;\r
+    IO_BYTE _RTRG :1;\r
+    IO_BYTE _CKS1 :1;\r
+    IO_BYTE _CKS0 :1;\r
+    IO_BYTE _PGMS :1;\r
+    IO_BYTE  :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE _CKS :2;\r
+  }bitc;\r
+ }PCNH04STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _EGS1 :1;\r
+    IO_BYTE _EGS0 :1;\r
+    IO_BYTE _IREN :1;\r
+    IO_BYTE _IRQF :1;\r
+    IO_BYTE _IRS1 :1;\r
+    IO_BYTE _IRS0 :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _OSEL :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE _EGS :2;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE _IRS :2;\r
+  }bitc;\r
+ }PCNL04STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _CNTE :1;\r
+    IO_WORD _STGR :1;\r
+    IO_WORD _MDSE :1;\r
+    IO_WORD _RTRG :1;\r
+    IO_WORD _CKS1 :1;\r
+    IO_WORD _CKS0 :1;\r
+    IO_WORD _PGMS :1;\r
+    IO_WORD  :1;\r
+    IO_WORD _EGS1 :1;\r
+    IO_WORD _EGS0 :1;\r
+    IO_WORD _IREN :1;\r
+    IO_WORD _IRQF :1;\r
+    IO_WORD _IRS1 :1;\r
+    IO_WORD _IRS0 :1;\r
+    IO_WORD  :1;\r
+    IO_WORD _OSEL :1;\r
+  }bit;\r
+  struct{\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD _CKS :2;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD _EGS :2;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD _IRS :2;\r
+  }bitc;\r
+ }PCN05STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _CNTE :1;\r
+    IO_BYTE _STGR :1;\r
+    IO_BYTE _MDSE :1;\r
+    IO_BYTE _RTRG :1;\r
+    IO_BYTE _CKS1 :1;\r
+    IO_BYTE _CKS0 :1;\r
+    IO_BYTE _PGMS :1;\r
+    IO_BYTE  :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE _CKS :2;\r
+  }bitc;\r
+ }PCNH05STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _EGS1 :1;\r
+    IO_BYTE _EGS0 :1;\r
+    IO_BYTE _IREN :1;\r
+    IO_BYTE _IRQF :1;\r
+    IO_BYTE _IRS1 :1;\r
+    IO_BYTE _IRS0 :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _OSEL :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE _EGS :2;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE _IRS :2;\r
+  }bitc;\r
+ }PCNL05STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _CNTE :1;\r
+    IO_WORD _STGR :1;\r
+    IO_WORD _MDSE :1;\r
+    IO_WORD _RTRG :1;\r
+    IO_WORD _CKS1 :1;\r
+    IO_WORD _CKS0 :1;\r
+    IO_WORD _PGMS :1;\r
+    IO_WORD  :1;\r
+    IO_WORD _EGS1 :1;\r
+    IO_WORD _EGS0 :1;\r
+    IO_WORD _IREN :1;\r
+    IO_WORD _IRQF :1;\r
+    IO_WORD _IRS1 :1;\r
+    IO_WORD _IRS0 :1;\r
+    IO_WORD  :1;\r
+    IO_WORD _OSEL :1;\r
+  }bit;\r
+  struct{\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD _CKS :2;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD _EGS :2;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD _IRS :2;\r
+  }bitc;\r
+ }PCN06STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _CNTE :1;\r
+    IO_BYTE _STGR :1;\r
+    IO_BYTE _MDSE :1;\r
+    IO_BYTE _RTRG :1;\r
+    IO_BYTE _CKS1 :1;\r
+    IO_BYTE _CKS0 :1;\r
+    IO_BYTE _PGMS :1;\r
+    IO_BYTE  :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE _CKS :2;\r
+  }bitc;\r
+ }PCNH06STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _EGS1 :1;\r
+    IO_BYTE _EGS0 :1;\r
+    IO_BYTE _IREN :1;\r
+    IO_BYTE _IRQF :1;\r
+    IO_BYTE _IRS1 :1;\r
+    IO_BYTE _IRS0 :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _OSEL :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE _EGS :2;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE _IRS :2;\r
+  }bitc;\r
+ }PCNL06STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _CNTE :1;\r
+    IO_WORD _STGR :1;\r
+    IO_WORD _MDSE :1;\r
+    IO_WORD _RTRG :1;\r
+    IO_WORD _CKS1 :1;\r
+    IO_WORD _CKS0 :1;\r
+    IO_WORD _PGMS :1;\r
+    IO_WORD  :1;\r
+    IO_WORD _EGS1 :1;\r
+    IO_WORD _EGS0 :1;\r
+    IO_WORD _IREN :1;\r
+    IO_WORD _IRQF :1;\r
+    IO_WORD _IRS1 :1;\r
+    IO_WORD _IRS0 :1;\r
+    IO_WORD  :1;\r
+    IO_WORD _OSEL :1;\r
+  }bit;\r
+  struct{\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD _CKS :2;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD _EGS :2;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD _IRS :2;\r
+  }bitc;\r
+ }PCN07STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _CNTE :1;\r
+    IO_BYTE _STGR :1;\r
+    IO_BYTE _MDSE :1;\r
+    IO_BYTE _RTRG :1;\r
+    IO_BYTE _CKS1 :1;\r
+    IO_BYTE _CKS0 :1;\r
+    IO_BYTE _PGMS :1;\r
+    IO_BYTE  :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE _CKS :2;\r
+  }bitc;\r
+ }PCNH07STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _EGS1 :1;\r
+    IO_BYTE _EGS0 :1;\r
+    IO_BYTE _IREN :1;\r
+    IO_BYTE _IRQF :1;\r
+    IO_BYTE _IRS1 :1;\r
+    IO_BYTE _IRS0 :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _OSEL :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE _EGS :2;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE _IRS :2;\r
+  }bitc;\r
+ }PCNL07STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _CNTE :1;\r
+    IO_WORD _STGR :1;\r
+    IO_WORD _MDSE :1;\r
+    IO_WORD _RTRG :1;\r
+    IO_WORD _CKS1 :1;\r
+    IO_WORD _CKS0 :1;\r
+    IO_WORD _PGMS :1;\r
+    IO_WORD  :1;\r
+    IO_WORD _EGS1 :1;\r
+    IO_WORD _EGS0 :1;\r
+    IO_WORD _IREN :1;\r
+    IO_WORD _IRQF :1;\r
+    IO_WORD _IRS1 :1;\r
+    IO_WORD _IRS0 :1;\r
+    IO_WORD  :1;\r
+    IO_WORD _OSEL :1;\r
+  }bit;\r
+  struct{\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD _CKS :2;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD _EGS :2;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD _IRS :2;\r
+  }bitc;\r
+ }PCN08STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _CNTE :1;\r
+    IO_BYTE _STGR :1;\r
+    IO_BYTE _MDSE :1;\r
+    IO_BYTE _RTRG :1;\r
+    IO_BYTE _CKS1 :1;\r
+    IO_BYTE _CKS0 :1;\r
+    IO_BYTE _PGMS :1;\r
+    IO_BYTE  :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE _CKS :2;\r
+  }bitc;\r
+ }PCNH08STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _EGS1 :1;\r
+    IO_BYTE _EGS0 :1;\r
+    IO_BYTE _IREN :1;\r
+    IO_BYTE _IRQF :1;\r
+    IO_BYTE _IRS1 :1;\r
+    IO_BYTE _IRS0 :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _OSEL :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE _EGS :2;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE _IRS :2;\r
+  }bitc;\r
+ }PCNL08STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _CNTE :1;\r
+    IO_WORD _STGR :1;\r
+    IO_WORD _MDSE :1;\r
+    IO_WORD _RTRG :1;\r
+    IO_WORD _CKS1 :1;\r
+    IO_WORD _CKS0 :1;\r
+    IO_WORD _PGMS :1;\r
+    IO_WORD  :1;\r
+    IO_WORD _EGS1 :1;\r
+    IO_WORD _EGS0 :1;\r
+    IO_WORD _IREN :1;\r
+    IO_WORD _IRQF :1;\r
+    IO_WORD _IRS1 :1;\r
+    IO_WORD _IRS0 :1;\r
+    IO_WORD  :1;\r
+    IO_WORD _OSEL :1;\r
+  }bit;\r
+  struct{\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD _CKS :2;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD _EGS :2;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD _IRS :2;\r
+  }bitc;\r
+ }PCN09STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _CNTE :1;\r
+    IO_BYTE _STGR :1;\r
+    IO_BYTE _MDSE :1;\r
+    IO_BYTE _RTRG :1;\r
+    IO_BYTE _CKS1 :1;\r
+    IO_BYTE _CKS0 :1;\r
+    IO_BYTE _PGMS :1;\r
+    IO_BYTE  :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE _CKS :2;\r
+  }bitc;\r
+ }PCNH09STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _EGS1 :1;\r
+    IO_BYTE _EGS0 :1;\r
+    IO_BYTE _IREN :1;\r
+    IO_BYTE _IRQF :1;\r
+    IO_BYTE _IRS1 :1;\r
+    IO_BYTE _IRS0 :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _OSEL :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE _EGS :2;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE _IRS :2;\r
+  }bitc;\r
+ }PCNL09STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _CNTE :1;\r
+    IO_WORD _STGR :1;\r
+    IO_WORD _MDSE :1;\r
+    IO_WORD _RTRG :1;\r
+    IO_WORD _CKS1 :1;\r
+    IO_WORD _CKS0 :1;\r
+    IO_WORD _PGMS :1;\r
+    IO_WORD  :1;\r
+    IO_WORD _EGS1 :1;\r
+    IO_WORD _EGS0 :1;\r
+    IO_WORD _IREN :1;\r
+    IO_WORD _IRQF :1;\r
+    IO_WORD _IRS1 :1;\r
+    IO_WORD _IRS0 :1;\r
+    IO_WORD  :1;\r
+    IO_WORD _OSEL :1;\r
+  }bit;\r
+  struct{\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD _CKS :2;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD _EGS :2;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD _IRS :2;\r
+  }bitc;\r
+ }PCN10STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _CNTE :1;\r
+    IO_BYTE _STGR :1;\r
+    IO_BYTE _MDSE :1;\r
+    IO_BYTE _RTRG :1;\r
+    IO_BYTE _CKS1 :1;\r
+    IO_BYTE _CKS0 :1;\r
+    IO_BYTE _PGMS :1;\r
+    IO_BYTE  :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE _CKS :2;\r
+  }bitc;\r
+ }PCNH10STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _EGS1 :1;\r
+    IO_BYTE _EGS0 :1;\r
+    IO_BYTE _IREN :1;\r
+    IO_BYTE _IRQF :1;\r
+    IO_BYTE _IRS1 :1;\r
+    IO_BYTE _IRS0 :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _OSEL :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE _EGS :2;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE _IRS :2;\r
+  }bitc;\r
+ }PCNL10STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _CNTE :1;\r
+    IO_WORD _STGR :1;\r
+    IO_WORD _MDSE :1;\r
+    IO_WORD _RTRG :1;\r
+    IO_WORD _CKS1 :1;\r
+    IO_WORD _CKS0 :1;\r
+    IO_WORD _PGMS :1;\r
+    IO_WORD  :1;\r
+    IO_WORD _EGS1 :1;\r
+    IO_WORD _EGS0 :1;\r
+    IO_WORD _IREN :1;\r
+    IO_WORD _IRQF :1;\r
+    IO_WORD _IRS1 :1;\r
+    IO_WORD _IRS0 :1;\r
+    IO_WORD  :1;\r
+    IO_WORD _OSEL :1;\r
+  }bit;\r
+  struct{\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD _CKS :2;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD _EGS :2;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD _IRS :2;\r
+  }bitc;\r
+ }PCN11STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _CNTE :1;\r
+    IO_BYTE _STGR :1;\r
+    IO_BYTE _MDSE :1;\r
+    IO_BYTE _RTRG :1;\r
+    IO_BYTE _CKS1 :1;\r
+    IO_BYTE _CKS0 :1;\r
+    IO_BYTE _PGMS :1;\r
+    IO_BYTE  :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE _CKS :2;\r
+  }bitc;\r
+ }PCNH11STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _EGS1 :1;\r
+    IO_BYTE _EGS0 :1;\r
+    IO_BYTE _IREN :1;\r
+    IO_BYTE _IRQF :1;\r
+    IO_BYTE _IRS1 :1;\r
+    IO_BYTE _IRS0 :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _OSEL :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE _EGS :2;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE _IRS :2;\r
+  }bitc;\r
+ }PCNL11STR;\r
+typedef union{   /* Pulse Frequency Modulator (PFM) */\r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD  :1;\r
+    IO_WORD _INV :1;\r
+    IO_WORD  :1;\r
+    IO_WORD _CSL2 :1;\r
+    IO_WORD _CSL1 :1;\r
+    IO_WORD _CSL0 :1;\r
+    IO_WORD  :1;\r
+    IO_WORD _MOD1 :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD _RELD :1;\r
+    IO_WORD _INTE :1;\r
+    IO_WORD _UF :1;\r
+    IO_WORD _CNTE :1;\r
+    IO_WORD _TRG :1;\r
+  }bit;\r
+  struct{\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD _CSL :3;\r
+  }bitc;\r
+ }P0TMCSRSTR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE _INV :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _CSL2 :1;\r
+    IO_BYTE _CSL1 :1;\r
+    IO_BYTE _CSL0 :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _MOD1 :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE :3;\r
+    IO_BYTE _CSL :3;\r
+  }bitc;\r
+ }P0TMCSRHSTR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _RELD :1;\r
+    IO_BYTE _INTE :1;\r
+    IO_BYTE _UF :1;\r
+    IO_BYTE _CNTE :1;\r
+    IO_BYTE _TRG :1;\r
+  }bit;\r
+ }P0TMCSRLSTR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD  :1;\r
+    IO_WORD _INV :1;\r
+    IO_WORD  :1;\r
+    IO_WORD _CSL2 :1;\r
+    IO_WORD _CSL1 :1;\r
+    IO_WORD _CSL0 :1;\r
+    IO_WORD  :1;\r
+    IO_WORD _MOD1 :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD _RELD :1;\r
+    IO_WORD _INTE :1;\r
+    IO_WORD _UF :1;\r
+    IO_WORD _CNTE :1;\r
+    IO_WORD _TRG :1;\r
+  }bit;\r
+  struct{\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD _CSL :3;\r
+  }bitc;\r
+ }P1TMCSRSTR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE _INV :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _CSL2 :1;\r
+    IO_BYTE _CSL1 :1;\r
+    IO_BYTE _CSL0 :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _MOD1 :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE :3;\r
+    IO_BYTE _CSL :3;\r
+  }bitc;\r
+ }P1TMCSRHSTR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _RELD :1;\r
+    IO_BYTE _INTE :1;\r
+    IO_BYTE _UF :1;\r
+    IO_BYTE _CNTE :1;\r
+    IO_BYTE _TRG :1;\r
+  }bit;\r
+ }P1TMCSRLSTR;\r
+typedef union{   /* Input Capture 0-3 */\r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _ICP1 :1;\r
+    IO_BYTE _ICP0 :1;\r
+    IO_BYTE _ICE1 :1;\r
+    IO_BYTE _ICE0 :1;\r
+    IO_BYTE _EG11 :1;\r
+    IO_BYTE _EG10 :1;\r
+    IO_BYTE _EG01 :1;\r
+    IO_BYTE _EG00 :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE _EG1 :2;\r
+    IO_BYTE _EG0 :2;\r
+  }bitc;\r
+ }ICS01STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _ICP3 :1;\r
+    IO_BYTE _ICP2 :1;\r
+    IO_BYTE _ICE3 :1;\r
+    IO_BYTE _ICE2 :1;\r
+    IO_BYTE _EG31 :1;\r
+    IO_BYTE _EG30 :1;\r
+    IO_BYTE _EG21 :1;\r
+    IO_BYTE _EG20 :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE _EG3 :2;\r
+    IO_BYTE _EG2 :2;\r
+  }bitc;\r
+ }ICS23STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _CP15 :1;\r
+    IO_WORD _CP14 :1;\r
+    IO_WORD _CP13 :1;\r
+    IO_WORD _CP12 :1;\r
+    IO_WORD _CP11 :1;\r
+    IO_WORD _CP10 :1;\r
+    IO_WORD _CP9 :1;\r
+    IO_WORD _CP8 :1;\r
+    IO_WORD _CP7 :1;\r
+    IO_WORD _CP6 :1;\r
+    IO_WORD _CP5 :1;\r
+    IO_WORD _CP4 :1;\r
+    IO_WORD _CP3 :1;\r
+    IO_WORD _CP2 :1;\r
+    IO_WORD _CP1 :1;\r
+    IO_WORD _CP0 :1;\r
+  }bit;\r
+ }IPCP0STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _CP15 :1;\r
+    IO_WORD _CP14 :1;\r
+    IO_WORD _CP13 :1;\r
+    IO_WORD _CP12 :1;\r
+    IO_WORD _CP11 :1;\r
+    IO_WORD _CP10 :1;\r
+    IO_WORD _CP9 :1;\r
+    IO_WORD _CP8 :1;\r
+    IO_WORD _CP7 :1;\r
+    IO_WORD _CP6 :1;\r
+    IO_WORD _CP5 :1;\r
+    IO_WORD _CP4 :1;\r
+    IO_WORD _CP3 :1;\r
+    IO_WORD _CP2 :1;\r
+    IO_WORD _CP1 :1;\r
+    IO_WORD _CP0 :1;\r
+  }bit;\r
+ }IPCP1STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _CP15 :1;\r
+    IO_WORD _CP14 :1;\r
+    IO_WORD _CP13 :1;\r
+    IO_WORD _CP12 :1;\r
+    IO_WORD _CP11 :1;\r
+    IO_WORD _CP10 :1;\r
+    IO_WORD _CP9 :1;\r
+    IO_WORD _CP8 :1;\r
+    IO_WORD _CP7 :1;\r
+    IO_WORD _CP6 :1;\r
+    IO_WORD _CP5 :1;\r
+    IO_WORD _CP4 :1;\r
+    IO_WORD _CP3 :1;\r
+    IO_WORD _CP2 :1;\r
+    IO_WORD _CP1 :1;\r
+    IO_WORD _CP0 :1;\r
+  }bit;\r
+ }IPCP2STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _CP15 :1;\r
+    IO_WORD _CP14 :1;\r
+    IO_WORD _CP13 :1;\r
+    IO_WORD _CP12 :1;\r
+    IO_WORD _CP11 :1;\r
+    IO_WORD _CP10 :1;\r
+    IO_WORD _CP9 :1;\r
+    IO_WORD _CP8 :1;\r
+    IO_WORD _CP7 :1;\r
+    IO_WORD _CP6 :1;\r
+    IO_WORD _CP5 :1;\r
+    IO_WORD _CP4 :1;\r
+    IO_WORD _CP3 :1;\r
+    IO_WORD _CP2 :1;\r
+    IO_WORD _CP1 :1;\r
+    IO_WORD _CP0 :1;\r
+  }bit;\r
+ }IPCP3STR;\r
+typedef union{   /* Output Compare 0-3 */\r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD _CMOD :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD _OTD1 :1;\r
+    IO_WORD _OTD0 :1;\r
+    IO_WORD _ICP1 :1;\r
+    IO_WORD _ICP0 :1;\r
+    IO_WORD _ICE1 :1;\r
+    IO_WORD _ICE0 :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD _CST1 :1;\r
+    IO_WORD _CST0 :1;\r
+  }bit;\r
+ }OCS01STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD _CMOD :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD _OTD3 :1;\r
+    IO_WORD _OTD2 :1;\r
+    IO_WORD _ICP3 :1;\r
+    IO_WORD _ICP2 :1;\r
+    IO_WORD _ICE3 :1;\r
+    IO_WORD _ICE2 :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD _CST3 :1;\r
+    IO_WORD _CST2 :1;\r
+  }bit;\r
+ }OCS23STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _C15 :1;\r
+    IO_WORD _C14 :1;\r
+    IO_WORD _C13 :1;\r
+    IO_WORD _C12 :1;\r
+    IO_WORD _C11 :1;\r
+    IO_WORD _C10 :1;\r
+    IO_WORD _C9 :1;\r
+    IO_WORD _C8 :1;\r
+    IO_WORD _C7 :1;\r
+    IO_WORD _C6 :1;\r
+    IO_WORD _C5 :1;\r
+    IO_WORD _C4 :1;\r
+    IO_WORD _C3 :1;\r
+    IO_WORD _C2 :1;\r
+    IO_WORD _C1 :1;\r
+    IO_WORD _C0 :1;\r
+  }bit;\r
+ }OCCP0STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _C15 :1;\r
+    IO_WORD _C14 :1;\r
+    IO_WORD _C13 :1;\r
+    IO_WORD _C12 :1;\r
+    IO_WORD _C11 :1;\r
+    IO_WORD _C10 :1;\r
+    IO_WORD _C9 :1;\r
+    IO_WORD _C8 :1;\r
+    IO_WORD _C7 :1;\r
+    IO_WORD _C6 :1;\r
+    IO_WORD _C5 :1;\r
+    IO_WORD _C4 :1;\r
+    IO_WORD _C3 :1;\r
+    IO_WORD _C2 :1;\r
+    IO_WORD _C1 :1;\r
+    IO_WORD _C0 :1;\r
+  }bit;\r
+ }OCCP1STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _C15 :1;\r
+    IO_WORD _C14 :1;\r
+    IO_WORD _C13 :1;\r
+    IO_WORD _C12 :1;\r
+    IO_WORD _C11 :1;\r
+    IO_WORD _C10 :1;\r
+    IO_WORD _C9 :1;\r
+    IO_WORD _C8 :1;\r
+    IO_WORD _C7 :1;\r
+    IO_WORD _C6 :1;\r
+    IO_WORD _C5 :1;\r
+    IO_WORD _C4 :1;\r
+    IO_WORD _C3 :1;\r
+    IO_WORD _C2 :1;\r
+    IO_WORD _C1 :1;\r
+    IO_WORD _C0 :1;\r
+  }bit;\r
+ }OCCP2STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _C15 :1;\r
+    IO_WORD _C14 :1;\r
+    IO_WORD _C13 :1;\r
+    IO_WORD _C12 :1;\r
+    IO_WORD _C11 :1;\r
+    IO_WORD _C10 :1;\r
+    IO_WORD _C9 :1;\r
+    IO_WORD _C8 :1;\r
+    IO_WORD _C7 :1;\r
+    IO_WORD _C6 :1;\r
+    IO_WORD _C5 :1;\r
+    IO_WORD _C4 :1;\r
+    IO_WORD _C3 :1;\r
+    IO_WORD _C2 :1;\r
+    IO_WORD _C1 :1;\r
+    IO_WORD _C0 :1;\r
+  }bit;\r
+ }OCCP3STR;\r
+typedef union{   /* Sound Generator */\r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _TST :1;\r
+    IO_WORD _S2 :1;\r
+    IO_WORD _S1 :1;\r
+    IO_WORD _S0 :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD _BUSY :1;\r
+    IO_WORD _DEC :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD _TONE :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD _INTE :1;\r
+    IO_WORD _INT :1;\r
+    IO_WORD _ST :1;\r
+  }bit;\r
+  struct{\r
+    IO_WORD :1;\r
+    IO_WORD _S :3;\r
+  }bitc;\r
+ }SGCRSTR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _TST :1;\r
+    IO_BYTE _S2 :1;\r
+    IO_BYTE _S1 :1;\r
+    IO_BYTE _S0 :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _BUSY :1;\r
+    IO_BYTE _DEC :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE :1;\r
+    IO_BYTE _S :3;\r
+  }bitc;\r
+ }SGCRHSTR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _TONE :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _INTE :1;\r
+    IO_BYTE _INT :1;\r
+    IO_BYTE _ST :1;\r
+  }bit;\r
+ }SGCRLSTR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _D15 :1;\r
+    IO_WORD _D14 :1;\r
+    IO_WORD _D13 :1;\r
+    IO_WORD _D12 :1;\r
+    IO_WORD _D11 :1;\r
+    IO_WORD _D10 :1;\r
+    IO_WORD _D9 :1;\r
+    IO_WORD _D8 :1;\r
+    IO_WORD _D7 :1;\r
+    IO_WORD _D6 :1;\r
+    IO_WORD _D5 :1;\r
+    IO_WORD _D4 :1;\r
+    IO_WORD _D3 :1;\r
+    IO_WORD _D2 :1;\r
+    IO_WORD _D1 :1;\r
+    IO_WORD _D0 :1;\r
+  }bit;\r
+ }SGFRSTR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }SGARSTR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }SGTRSTR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }SGDRSTR;\r
+typedef union{   /* ADC */\r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _ADE31 :1;\r
+    IO_WORD _ADE30 :1;\r
+    IO_WORD _ADE29 :1;\r
+    IO_WORD _ADE28 :1;\r
+    IO_WORD _ADE27 :1;\r
+    IO_WORD _ADE26 :1;\r
+    IO_WORD _ADE25 :1;\r
+    IO_WORD _ADE24 :1;\r
+    IO_WORD _ADE23 :1;\r
+    IO_WORD _ADE22 :1;\r
+    IO_WORD _ADE21 :1;\r
+    IO_WORD _ADE20 :1;\r
+    IO_WORD _ADE19 :1;\r
+    IO_WORD _ADE18 :1;\r
+    IO_WORD _ADE17 :1;\r
+    IO_WORD _ADE16 :1;\r
+  }bit;\r
+ }ADERHSTR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _ADE15 :1;\r
+    IO_WORD _ADE14 :1;\r
+    IO_WORD _ADE13 :1;\r
+    IO_WORD _ADE12 :1;\r
+    IO_WORD _ADE11 :1;\r
+    IO_WORD _ADE10 :1;\r
+    IO_WORD _ADE9 :1;\r
+    IO_WORD _ADE8 :1;\r
+    IO_WORD _ADE7 :1;\r
+    IO_WORD _ADE6 :1;\r
+    IO_WORD _ADE5 :1;\r
+    IO_WORD _ADE4 :1;\r
+    IO_WORD _ADE3 :1;\r
+    IO_WORD _ADE2 :1;\r
+    IO_WORD _ADE1 :1;\r
+    IO_WORD _ADE0 :1;\r
+  }bit;\r
+ }ADERLSTR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _BUSY :1;\r
+    IO_BYTE _INT :1;\r
+    IO_BYTE _INTE :1;\r
+    IO_BYTE _PAUS :1;\r
+    IO_BYTE _STS1 :1;\r
+    IO_BYTE _STS0 :1;\r
+    IO_BYTE _STRT :1;\r
+    IO_BYTE  :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE _STS :2;\r
+  }bitc;\r
+ }ADCS1STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _MD1 :1;\r
+    IO_BYTE _MD0 :1;\r
+    IO_BYTE _S10 :1;\r
+    IO_BYTE _ACH4 :1;\r
+    IO_BYTE _ACH3 :1;\r
+    IO_BYTE _ACH2 :1;\r
+    IO_BYTE _ACH1 :1;\r
+    IO_BYTE _ACH0 :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE _MD :2;\r
+    IO_BYTE :1;\r
+    IO_BYTE _ACH :5;\r
+  }bitc;\r
+ }ADCS0STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _D9 :1;\r
+    IO_BYTE _D8 :1;\r
+  }bit;\r
+ }ADCR1STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }ADCR0STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _CT5 :1;\r
+    IO_BYTE _CT4 :1;\r
+    IO_BYTE _CT3 :1;\r
+    IO_BYTE _CT2 :1;\r
+    IO_BYTE _CT1 :1;\r
+    IO_BYTE _CT0 :1;\r
+    IO_BYTE _ST9 :1;\r
+    IO_BYTE _ST8 :1;\r
+  }bit;\r
+ }ADCT1STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _ST7 :1;\r
+    IO_BYTE _ST6 :1;\r
+    IO_BYTE _ST5 :1;\r
+    IO_BYTE _ST4 :1;\r
+    IO_BYTE _ST3 :1;\r
+    IO_BYTE _ST2 :1;\r
+    IO_BYTE _ST1 :1;\r
+    IO_BYTE _ST0 :1;\r
+  }bit;\r
+ }ADCT0STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _ANS4 :1;\r
+    IO_BYTE _ANS3 :1;\r
+    IO_BYTE _ANS2 :1;\r
+    IO_BYTE _ANS1 :1;\r
+    IO_BYTE _ASN0 :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE _ANS :5;\r
+  }bitc;\r
+ }ADSCHSTR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _ANE4 :1;\r
+    IO_BYTE _ANE3 :1;\r
+    IO_BYTE _ANE2 :1;\r
+    IO_BYTE _ANE1 :1;\r
+    IO_BYTE _ANE0 :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE _ANE :5;\r
+  }bitc;\r
+ }ADECHSTR;\r
+typedef union{   /* Alarm Comparator 0-1 */\r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _MD :1;\r
+    IO_BYTE _OV_EN :1;\r
+    IO_BYTE _UV_EN :1;\r
+    IO_BYTE _OUT2 :1;\r
+    IO_BYTE _OUT1 :1;\r
+    IO_BYTE _IRQ :1;\r
+    IO_BYTE _IEN :1;\r
+    IO_BYTE _PD :1;\r
+  }bit;\r
+ }ACSR0STR;\r
+typedef union{   /* Reload Timer 0 */\r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _D15 :1;\r
+    IO_WORD _D14 :1;\r
+    IO_WORD _D13 :1;\r
+    IO_WORD _D12 :1;\r
+    IO_WORD _D11 :1;\r
+    IO_WORD _D10 :1;\r
+    IO_WORD _D9 :1;\r
+    IO_WORD _D8 :1;\r
+    IO_WORD _D7 :1;\r
+    IO_WORD _D6 :1;\r
+    IO_WORD _D5 :1;\r
+    IO_WORD _D4 :1;\r
+    IO_WORD _D3 :1;\r
+    IO_WORD _D2 :1;\r
+    IO_WORD _D1 :1;\r
+    IO_WORD _D0 :1;\r
+  }bit;\r
+ }TMRLR0STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _D15 :1;\r
+    IO_WORD _D14 :1;\r
+    IO_WORD _D13 :1;\r
+    IO_WORD _D12 :1;\r
+    IO_WORD _D11 :1;\r
+    IO_WORD _D10 :1;\r
+    IO_WORD _D9 :1;\r
+    IO_WORD _D8 :1;\r
+    IO_WORD _D7 :1;\r
+    IO_WORD _D6 :1;\r
+    IO_WORD _D5 :1;\r
+    IO_WORD _D4 :1;\r
+    IO_WORD _D3 :1;\r
+    IO_WORD _D2 :1;\r
+    IO_WORD _D1 :1;\r
+    IO_WORD _D0 :1;\r
+  }bit;\r
+ }TMR0STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD _CSL2 :1;\r
+    IO_WORD _CSL1 :1;\r
+    IO_WORD _CSL0 :1;\r
+    IO_WORD _MOD2 :1;\r
+    IO_WORD _MOD1 :1;\r
+    IO_WORD _MOD0 :1;\r
+    IO_WORD  :1;\r
+    IO_WORD _OUTL :1;\r
+    IO_WORD _RELD :1;\r
+    IO_WORD _INTE :1;\r
+    IO_WORD _UF :1;\r
+    IO_WORD _CNTE :1;\r
+    IO_WORD _TRG :1;\r
+  }bit;\r
+  struct{\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD _CSL :3;\r
+    IO_WORD _MOD :3;\r
+  }bitc;\r
+ }TMCSR0STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _CSL2 :1;\r
+    IO_BYTE _CSL1 :1;\r
+    IO_BYTE _CSL0 :1;\r
+    IO_BYTE _MOD2 :1;\r
+    IO_BYTE _MOD1 :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE :3;\r
+    IO_BYTE _CSL :3;\r
+  }bitc;\r
+ }TMCSRH0STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _MOD0 :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _OUTL :1;\r
+    IO_BYTE _RELD :1;\r
+    IO_BYTE _INTE :1;\r
+    IO_BYTE _UF :1;\r
+    IO_BYTE _CNTE :1;\r
+    IO_BYTE _TRG :1;\r
+  }bit;\r
+ }TMCSRL0STR;\r
+typedef union{   /* Reload Timer 1 */\r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _D15 :1;\r
+    IO_WORD _D14 :1;\r
+    IO_WORD _D13 :1;\r
+    IO_WORD _D12 :1;\r
+    IO_WORD _D11 :1;\r
+    IO_WORD _D10 :1;\r
+    IO_WORD _D9 :1;\r
+    IO_WORD _D8 :1;\r
+    IO_WORD _D7 :1;\r
+    IO_WORD _D6 :1;\r
+    IO_WORD _D5 :1;\r
+    IO_WORD _D4 :1;\r
+    IO_WORD _D3 :1;\r
+    IO_WORD _D2 :1;\r
+    IO_WORD _D1 :1;\r
+    IO_WORD _D0 :1;\r
+  }bit;\r
+ }TMRLR1STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _D15 :1;\r
+    IO_WORD _D14 :1;\r
+    IO_WORD _D13 :1;\r
+    IO_WORD _D12 :1;\r
+    IO_WORD _D11 :1;\r
+    IO_WORD _D10 :1;\r
+    IO_WORD _D9 :1;\r
+    IO_WORD _D8 :1;\r
+    IO_WORD _D7 :1;\r
+    IO_WORD _D6 :1;\r
+    IO_WORD _D5 :1;\r
+    IO_WORD _D4 :1;\r
+    IO_WORD _D3 :1;\r
+    IO_WORD _D2 :1;\r
+    IO_WORD _D1 :1;\r
+    IO_WORD _D0 :1;\r
+  }bit;\r
+ }TMR1STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD _CSL2 :1;\r
+    IO_WORD _CSL1 :1;\r
+    IO_WORD _CSL0 :1;\r
+    IO_WORD _MOD2 :1;\r
+    IO_WORD _MOD1 :1;\r
+    IO_WORD _MOD0 :1;\r
+    IO_WORD  :1;\r
+    IO_WORD _OUTL :1;\r
+    IO_WORD _RELD :1;\r
+    IO_WORD _INTE :1;\r
+    IO_WORD _UF :1;\r
+    IO_WORD _CNTE :1;\r
+    IO_WORD _TRG :1;\r
+  }bit;\r
+  struct{\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD _CSL :3;\r
+    IO_WORD _MOD :3;\r
+  }bitc;\r
+ }TMCSR1STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _CSL2 :1;\r
+    IO_BYTE _CSL1 :1;\r
+    IO_BYTE _CSL0 :1;\r
+    IO_BYTE _MOD2 :1;\r
+    IO_BYTE _MOD1 :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE :3;\r
+    IO_BYTE _CSL :3;\r
+  }bitc;\r
+ }TMCSRH1STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _MOD0 :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _OUTL :1;\r
+    IO_BYTE _RELD :1;\r
+    IO_BYTE _INTE :1;\r
+    IO_BYTE _UF :1;\r
+    IO_BYTE _CNTE :1;\r
+    IO_BYTE _TRG :1;\r
+  }bit;\r
+ }TMCSRL1STR;\r
+typedef union{   /* Reload Timer 2 */\r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _D15 :1;\r
+    IO_WORD _D14 :1;\r
+    IO_WORD _D13 :1;\r
+    IO_WORD _D12 :1;\r
+    IO_WORD _D11 :1;\r
+    IO_WORD _D10 :1;\r
+    IO_WORD _D9 :1;\r
+    IO_WORD _D8 :1;\r
+    IO_WORD _D7 :1;\r
+    IO_WORD _D6 :1;\r
+    IO_WORD _D5 :1;\r
+    IO_WORD _D4 :1;\r
+    IO_WORD _D3 :1;\r
+    IO_WORD _D2 :1;\r
+    IO_WORD _D1 :1;\r
+    IO_WORD _D0 :1;\r
+  }bit;\r
+ }TMRLR2STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _D15 :1;\r
+    IO_WORD _D14 :1;\r
+    IO_WORD _D13 :1;\r
+    IO_WORD _D12 :1;\r
+    IO_WORD _D11 :1;\r
+    IO_WORD _D10 :1;\r
+    IO_WORD _D9 :1;\r
+    IO_WORD _D8 :1;\r
+    IO_WORD _D7 :1;\r
+    IO_WORD _D6 :1;\r
+    IO_WORD _D5 :1;\r
+    IO_WORD _D4 :1;\r
+    IO_WORD _D3 :1;\r
+    IO_WORD _D2 :1;\r
+    IO_WORD _D1 :1;\r
+    IO_WORD _D0 :1;\r
+  }bit;\r
+ }TMR2STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD _CSL2 :1;\r
+    IO_WORD _CSL1 :1;\r
+    IO_WORD _CSL0 :1;\r
+    IO_WORD _MOD2 :1;\r
+    IO_WORD _MOD1 :1;\r
+    IO_WORD _MOD0 :1;\r
+    IO_WORD  :1;\r
+    IO_WORD _OUTL :1;\r
+    IO_WORD _RELD :1;\r
+    IO_WORD _INTE :1;\r
+    IO_WORD _UF :1;\r
+    IO_WORD _CNTE :1;\r
+    IO_WORD _TRG :1;\r
+  }bit;\r
+  struct{\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD _CSL :3;\r
+    IO_WORD _MOD :3;\r
+  }bitc;\r
+ }TMCSR2STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _CSL2 :1;\r
+    IO_BYTE _CSL1 :1;\r
+    IO_BYTE _CSL0 :1;\r
+    IO_BYTE _MOD2 :1;\r
+    IO_BYTE _MOD1 :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE :3;\r
+    IO_BYTE _CSL :3;\r
+  }bitc;\r
+ }TMCSRH2STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _MOD0 :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _OUTL :1;\r
+    IO_BYTE _RELD :1;\r
+    IO_BYTE _INTE :1;\r
+    IO_BYTE _UF :1;\r
+    IO_BYTE _CNTE :1;\r
+    IO_BYTE _TRG :1;\r
+  }bit;\r
+ }TMCSRL2STR;\r
+typedef union{   /* Reload Timer 3 */\r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _D15 :1;\r
+    IO_WORD _D14 :1;\r
+    IO_WORD _D13 :1;\r
+    IO_WORD _D12 :1;\r
+    IO_WORD _D11 :1;\r
+    IO_WORD _D10 :1;\r
+    IO_WORD _D9 :1;\r
+    IO_WORD _D8 :1;\r
+    IO_WORD _D7 :1;\r
+    IO_WORD _D6 :1;\r
+    IO_WORD _D5 :1;\r
+    IO_WORD _D4 :1;\r
+    IO_WORD _D3 :1;\r
+    IO_WORD _D2 :1;\r
+    IO_WORD _D1 :1;\r
+    IO_WORD _D0 :1;\r
+  }bit;\r
+ }TMRLR3STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _D15 :1;\r
+    IO_WORD _D14 :1;\r
+    IO_WORD _D13 :1;\r
+    IO_WORD _D12 :1;\r
+    IO_WORD _D11 :1;\r
+    IO_WORD _D10 :1;\r
+    IO_WORD _D9 :1;\r
+    IO_WORD _D8 :1;\r
+    IO_WORD _D7 :1;\r
+    IO_WORD _D6 :1;\r
+    IO_WORD _D5 :1;\r
+    IO_WORD _D4 :1;\r
+    IO_WORD _D3 :1;\r
+    IO_WORD _D2 :1;\r
+    IO_WORD _D1 :1;\r
+    IO_WORD _D0 :1;\r
+  }bit;\r
+ }TMR3STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD _CSL2 :1;\r
+    IO_WORD _CSL1 :1;\r
+    IO_WORD _CSL0 :1;\r
+    IO_WORD _MOD2 :1;\r
+    IO_WORD _MOD1 :1;\r
+    IO_WORD _MOD0 :1;\r
+    IO_WORD  :1;\r
+    IO_WORD _OUTL :1;\r
+    IO_WORD _RELD :1;\r
+    IO_WORD _INTE :1;\r
+    IO_WORD _UF :1;\r
+    IO_WORD _CNTE :1;\r
+    IO_WORD _TRG :1;\r
+  }bit;\r
+  struct{\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD _CSL :3;\r
+    IO_WORD _MOD :3;\r
+  }bitc;\r
+ }TMCSR3STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _CSL2 :1;\r
+    IO_BYTE _CSL1 :1;\r
+    IO_BYTE _CSL0 :1;\r
+    IO_BYTE _MOD2 :1;\r
+    IO_BYTE _MOD1 :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE :3;\r
+    IO_BYTE _CSL :3;\r
+  }bitc;\r
+ }TMCSRH3STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _MOD0 :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _OUTL :1;\r
+    IO_BYTE _RELD :1;\r
+    IO_BYTE _INTE :1;\r
+    IO_BYTE _UF :1;\r
+    IO_BYTE _CNTE :1;\r
+    IO_BYTE _TRG :1;\r
+  }bit;\r
+ }TMCSRL3STR;\r
+typedef union{   /* Reload Timer 4 */\r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _D15 :1;\r
+    IO_WORD _D14 :1;\r
+    IO_WORD _D13 :1;\r
+    IO_WORD _D12 :1;\r
+    IO_WORD _D11 :1;\r
+    IO_WORD _D10 :1;\r
+    IO_WORD _D9 :1;\r
+    IO_WORD _D8 :1;\r
+    IO_WORD _D7 :1;\r
+    IO_WORD _D6 :1;\r
+    IO_WORD _D5 :1;\r
+    IO_WORD _D4 :1;\r
+    IO_WORD _D3 :1;\r
+    IO_WORD _D2 :1;\r
+    IO_WORD _D1 :1;\r
+    IO_WORD _D0 :1;\r
+  }bit;\r
+ }TMRLR4STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _D15 :1;\r
+    IO_WORD _D14 :1;\r
+    IO_WORD _D13 :1;\r
+    IO_WORD _D12 :1;\r
+    IO_WORD _D11 :1;\r
+    IO_WORD _D10 :1;\r
+    IO_WORD _D9 :1;\r
+    IO_WORD _D8 :1;\r
+    IO_WORD _D7 :1;\r
+    IO_WORD _D6 :1;\r
+    IO_WORD _D5 :1;\r
+    IO_WORD _D4 :1;\r
+    IO_WORD _D3 :1;\r
+    IO_WORD _D2 :1;\r
+    IO_WORD _D1 :1;\r
+    IO_WORD _D0 :1;\r
+  }bit;\r
+ }TMR4STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD _CSL2 :1;\r
+    IO_WORD _CSL1 :1;\r
+    IO_WORD _CSL0 :1;\r
+    IO_WORD _MOD2 :1;\r
+    IO_WORD _MOD1 :1;\r
+    IO_WORD _MOD0 :1;\r
+    IO_WORD  :1;\r
+    IO_WORD _OUTL :1;\r
+    IO_WORD _RELD :1;\r
+    IO_WORD _INTE :1;\r
+    IO_WORD _UF :1;\r
+    IO_WORD _CNTE :1;\r
+    IO_WORD _TRG :1;\r
+  }bit;\r
+  struct{\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD _CSL :3;\r
+    IO_WORD _MOD :3;\r
+  }bitc;\r
+ }TMCSR4STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _CSL2 :1;\r
+    IO_BYTE _CSL1 :1;\r
+    IO_BYTE _CSL0 :1;\r
+    IO_BYTE _MOD2 :1;\r
+    IO_BYTE _MOD1 :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE :3;\r
+    IO_BYTE _CSL :3;\r
+  }bitc;\r
+ }TMCSRH4STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _MOD0 :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _OUTL :1;\r
+    IO_BYTE _RELD :1;\r
+    IO_BYTE _INTE :1;\r
+    IO_BYTE _UF :1;\r
+    IO_BYTE _CNTE :1;\r
+    IO_BYTE _TRG :1;\r
+  }bit;\r
+ }TMCSRL4STR;\r
+typedef union{   /* Reload Timer 5 */\r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _D15 :1;\r
+    IO_WORD _D14 :1;\r
+    IO_WORD _D13 :1;\r
+    IO_WORD _D12 :1;\r
+    IO_WORD _D11 :1;\r
+    IO_WORD _D10 :1;\r
+    IO_WORD _D9 :1;\r
+    IO_WORD _D8 :1;\r
+    IO_WORD _D7 :1;\r
+    IO_WORD _D6 :1;\r
+    IO_WORD _D5 :1;\r
+    IO_WORD _D4 :1;\r
+    IO_WORD _D3 :1;\r
+    IO_WORD _D2 :1;\r
+    IO_WORD _D1 :1;\r
+    IO_WORD _D0 :1;\r
+  }bit;\r
+ }TMRLR5STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _D15 :1;\r
+    IO_WORD _D14 :1;\r
+    IO_WORD _D13 :1;\r
+    IO_WORD _D12 :1;\r
+    IO_WORD _D11 :1;\r
+    IO_WORD _D10 :1;\r
+    IO_WORD _D9 :1;\r
+    IO_WORD _D8 :1;\r
+    IO_WORD _D7 :1;\r
+    IO_WORD _D6 :1;\r
+    IO_WORD _D5 :1;\r
+    IO_WORD _D4 :1;\r
+    IO_WORD _D3 :1;\r
+    IO_WORD _D2 :1;\r
+    IO_WORD _D1 :1;\r
+    IO_WORD _D0 :1;\r
+  }bit;\r
+ }TMR5STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD _CSL2 :1;\r
+    IO_WORD _CSL1 :1;\r
+    IO_WORD _CSL0 :1;\r
+    IO_WORD _MOD2 :1;\r
+    IO_WORD _MOD1 :1;\r
+    IO_WORD _MOD0 :1;\r
+    IO_WORD  :1;\r
+    IO_WORD _OUTL :1;\r
+    IO_WORD _RELD :1;\r
+    IO_WORD _INTE :1;\r
+    IO_WORD _UF :1;\r
+    IO_WORD _CNTE :1;\r
+    IO_WORD _TRG :1;\r
+  }bit;\r
+  struct{\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD _CSL :3;\r
+    IO_WORD _MOD :3;\r
+  }bitc;\r
+ }TMCSR5STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _CSL2 :1;\r
+    IO_BYTE _CSL1 :1;\r
+    IO_BYTE _CSL0 :1;\r
+    IO_BYTE _MOD2 :1;\r
+    IO_BYTE _MOD1 :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE :3;\r
+    IO_BYTE _CSL :3;\r
+  }bitc;\r
+ }TMCSRH5STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _MOD0 :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _OUTL :1;\r
+    IO_BYTE _RELD :1;\r
+    IO_BYTE _INTE :1;\r
+    IO_BYTE _UF :1;\r
+    IO_BYTE _CNTE :1;\r
+    IO_BYTE _TRG :1;\r
+  }bit;\r
+ }TMCSRL5STR;\r
+typedef union{   /* Reload Timer 6 */\r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _D15 :1;\r
+    IO_WORD _D14 :1;\r
+    IO_WORD _D13 :1;\r
+    IO_WORD _D12 :1;\r
+    IO_WORD _D11 :1;\r
+    IO_WORD _D10 :1;\r
+    IO_WORD _D9 :1;\r
+    IO_WORD _D8 :1;\r
+    IO_WORD _D7 :1;\r
+    IO_WORD _D6 :1;\r
+    IO_WORD _D5 :1;\r
+    IO_WORD _D4 :1;\r
+    IO_WORD _D3 :1;\r
+    IO_WORD _D2 :1;\r
+    IO_WORD _D1 :1;\r
+    IO_WORD _D0 :1;\r
+  }bit;\r
+ }TMRLR6STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _D15 :1;\r
+    IO_WORD _D14 :1;\r
+    IO_WORD _D13 :1;\r
+    IO_WORD _D12 :1;\r
+    IO_WORD _D11 :1;\r
+    IO_WORD _D10 :1;\r
+    IO_WORD _D9 :1;\r
+    IO_WORD _D8 :1;\r
+    IO_WORD _D7 :1;\r
+    IO_WORD _D6 :1;\r
+    IO_WORD _D5 :1;\r
+    IO_WORD _D4 :1;\r
+    IO_WORD _D3 :1;\r
+    IO_WORD _D2 :1;\r
+    IO_WORD _D1 :1;\r
+    IO_WORD _D0 :1;\r
+  }bit;\r
+ }TMR6STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD _CSL2 :1;\r
+    IO_WORD _CSL1 :1;\r
+    IO_WORD _CSL0 :1;\r
+    IO_WORD _MOD2 :1;\r
+    IO_WORD _MOD1 :1;\r
+    IO_WORD _MOD0 :1;\r
+    IO_WORD  :1;\r
+    IO_WORD _OUTL :1;\r
+    IO_WORD _RELD :1;\r
+    IO_WORD _INTE :1;\r
+    IO_WORD _UF :1;\r
+    IO_WORD _CNTE :1;\r
+    IO_WORD _TRG :1;\r
+  }bit;\r
+  struct{\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD _CSL :3;\r
+    IO_WORD _MOD :3;\r
+  }bitc;\r
+ }TMCSR6STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _CSL2 :1;\r
+    IO_BYTE _CSL1 :1;\r
+    IO_BYTE _CSL0 :1;\r
+    IO_BYTE _MOD2 :1;\r
+    IO_BYTE _MOD1 :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE :3;\r
+    IO_BYTE _CSL :3;\r
+  }bitc;\r
+ }TMCSRH6STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _MOD0 :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _OUTL :1;\r
+    IO_BYTE _RELD :1;\r
+    IO_BYTE _INTE :1;\r
+    IO_BYTE _UF :1;\r
+    IO_BYTE _CNTE :1;\r
+    IO_BYTE _TRG :1;\r
+  }bit;\r
+ }TMCSRL6STR;\r
+typedef union{   /* Reload Timer 7 */\r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _D15 :1;\r
+    IO_WORD _D14 :1;\r
+    IO_WORD _D13 :1;\r
+    IO_WORD _D12 :1;\r
+    IO_WORD _D11 :1;\r
+    IO_WORD _D10 :1;\r
+    IO_WORD _D9 :1;\r
+    IO_WORD _D8 :1;\r
+    IO_WORD _D7 :1;\r
+    IO_WORD _D6 :1;\r
+    IO_WORD _D5 :1;\r
+    IO_WORD _D4 :1;\r
+    IO_WORD _D3 :1;\r
+    IO_WORD _D2 :1;\r
+    IO_WORD _D1 :1;\r
+    IO_WORD _D0 :1;\r
+  }bit;\r
+ }TMRLR7STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _D15 :1;\r
+    IO_WORD _D14 :1;\r
+    IO_WORD _D13 :1;\r
+    IO_WORD _D12 :1;\r
+    IO_WORD _D11 :1;\r
+    IO_WORD _D10 :1;\r
+    IO_WORD _D9 :1;\r
+    IO_WORD _D8 :1;\r
+    IO_WORD _D7 :1;\r
+    IO_WORD _D6 :1;\r
+    IO_WORD _D5 :1;\r
+    IO_WORD _D4 :1;\r
+    IO_WORD _D3 :1;\r
+    IO_WORD _D2 :1;\r
+    IO_WORD _D1 :1;\r
+    IO_WORD _D0 :1;\r
+  }bit;\r
+ }TMR7STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD _CSL2 :1;\r
+    IO_WORD _CSL1 :1;\r
+    IO_WORD _CSL0 :1;\r
+    IO_WORD _MOD2 :1;\r
+    IO_WORD _MOD1 :1;\r
+    IO_WORD _MOD0 :1;\r
+    IO_WORD  :1;\r
+    IO_WORD _OUTL :1;\r
+    IO_WORD _RELD :1;\r
+    IO_WORD _INTE :1;\r
+    IO_WORD _UF :1;\r
+    IO_WORD _CNTE :1;\r
+    IO_WORD _TRG :1;\r
+  }bit;\r
+  struct{\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD _CSL :3;\r
+    IO_WORD _MOD :3;\r
+  }bitc;\r
+ }TMCSR7STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _CSL2 :1;\r
+    IO_BYTE _CSL1 :1;\r
+    IO_BYTE _CSL0 :1;\r
+    IO_BYTE _MOD2 :1;\r
+    IO_BYTE _MOD1 :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE :3;\r
+    IO_BYTE _CSL :3;\r
+  }bitc;\r
+ }TMCSRH7STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _MOD0 :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _OUTL :1;\r
+    IO_BYTE _RELD :1;\r
+    IO_BYTE _INTE :1;\r
+    IO_BYTE _UF :1;\r
+    IO_BYTE _CNTE :1;\r
+    IO_BYTE _TRG :1;\r
+  }bit;\r
+ }TMCSRL7STR;\r
+typedef union{   /* Free Running Timer0 */\r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _T15 :1;\r
+    IO_WORD _T14 :1;\r
+    IO_WORD _T13 :1;\r
+    IO_WORD _T12 :1;\r
+    IO_WORD _T11 :1;\r
+    IO_WORD _T10 :1;\r
+    IO_WORD _T9 :1;\r
+    IO_WORD _T8 :1;\r
+    IO_WORD _T7 :1;\r
+    IO_WORD _T6 :1;\r
+    IO_WORD _T5 :1;\r
+    IO_WORD _T4 :1;\r
+    IO_WORD _T3 :1;\r
+    IO_WORD _T2 :1;\r
+    IO_WORD _T1 :1;\r
+    IO_WORD _T0 :1;\r
+  }bit;\r
+ }TCDT0STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _ECLK :1;\r
+    IO_BYTE _IVF :1;\r
+    IO_BYTE _IVFE :1;\r
+    IO_BYTE _STOP :1;\r
+    IO_BYTE _MODE :1;\r
+    IO_BYTE _CLR :1;\r
+    IO_BYTE _CLK1 :1;\r
+    IO_BYTE _CLK0 :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE _CLK :2;\r
+  }bitc;\r
+ }TCCS0STR;\r
+typedef union{   /* Free Running Timer1 */\r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _T15 :1;\r
+    IO_WORD _T14 :1;\r
+    IO_WORD _T13 :1;\r
+    IO_WORD _T12 :1;\r
+    IO_WORD _T11 :1;\r
+    IO_WORD _T10 :1;\r
+    IO_WORD _T9 :1;\r
+    IO_WORD _T8 :1;\r
+    IO_WORD _T7 :1;\r
+    IO_WORD _T6 :1;\r
+    IO_WORD _T5 :1;\r
+    IO_WORD _T4 :1;\r
+    IO_WORD _T3 :1;\r
+    IO_WORD _T2 :1;\r
+    IO_WORD _T1 :1;\r
+    IO_WORD _T0 :1;\r
+  }bit;\r
+ }TCDT1STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _ECLK :1;\r
+    IO_BYTE _IVF :1;\r
+    IO_BYTE _IVFE :1;\r
+    IO_BYTE _STOP :1;\r
+    IO_BYTE _MODE :1;\r
+    IO_BYTE _CLR :1;\r
+    IO_BYTE _CLK1 :1;\r
+    IO_BYTE _CLK0 :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE _CLK :2;\r
+  }bitc;\r
+ }TCCS1STR;\r
+typedef union{   /* Free Running Timer2 */\r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _T15 :1;\r
+    IO_WORD _T14 :1;\r
+    IO_WORD _T13 :1;\r
+    IO_WORD _T12 :1;\r
+    IO_WORD _T11 :1;\r
+    IO_WORD _T10 :1;\r
+    IO_WORD _T9 :1;\r
+    IO_WORD _T8 :1;\r
+    IO_WORD _T7 :1;\r
+    IO_WORD _T6 :1;\r
+    IO_WORD _T5 :1;\r
+    IO_WORD _T4 :1;\r
+    IO_WORD _T3 :1;\r
+    IO_WORD _T2 :1;\r
+    IO_WORD _T1 :1;\r
+    IO_WORD _T0 :1;\r
+  }bit;\r
+ }TCDT2STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _ECLK :1;\r
+    IO_BYTE _IVF :1;\r
+    IO_BYTE _IVFE :1;\r
+    IO_BYTE _STOP :1;\r
+    IO_BYTE _MODE :1;\r
+    IO_BYTE _CLR :1;\r
+    IO_BYTE _CLK1 :1;\r
+    IO_BYTE _CLK0 :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE _CLK :2;\r
+  }bitc;\r
+ }TCCS2STR;\r
+typedef union{   /* Free Running Timer3 */\r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _T15 :1;\r
+    IO_WORD _T14 :1;\r
+    IO_WORD _T13 :1;\r
+    IO_WORD _T12 :1;\r
+    IO_WORD _T11 :1;\r
+    IO_WORD _T10 :1;\r
+    IO_WORD _T9 :1;\r
+    IO_WORD _T8 :1;\r
+    IO_WORD _T7 :1;\r
+    IO_WORD _T6 :1;\r
+    IO_WORD _T5 :1;\r
+    IO_WORD _T4 :1;\r
+    IO_WORD _T3 :1;\r
+    IO_WORD _T2 :1;\r
+    IO_WORD _T1 :1;\r
+    IO_WORD _T0 :1;\r
+  }bit;\r
+ }TCDT3STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _ECLK :1;\r
+    IO_BYTE _IVF :1;\r
+    IO_BYTE _IVFE :1;\r
+    IO_BYTE _STOP :1;\r
+    IO_BYTE _MODE :1;\r
+    IO_BYTE _CLR :1;\r
+    IO_BYTE _CLK1 :1;\r
+    IO_BYTE _CLK0 :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE _CLK :2;\r
+  }bitc;\r
+ }TCCS3STR;\r
+typedef union{   /* DMAC */\r
+    IO_LWORD   lword;\r
+    struct{   \r
+    IO_LWORD _DENB :1;\r
+    IO_LWORD _PAUS :1;\r
+    IO_LWORD _STRG :1;\r
+    IO_LWORD _IS4 :1;\r
+    IO_LWORD _IS3 :1;\r
+    IO_LWORD _IS2 :1;\r
+    IO_LWORD _IS1 :1;\r
+    IO_LWORD _IS0 :1;\r
+    IO_LWORD _EIS3 :1;\r
+    IO_LWORD _EIS2 :1;\r
+    IO_LWORD _EIS1 :1;\r
+    IO_LWORD _EIS0 :1;\r
+    IO_LWORD _BLK3 :1;\r
+    IO_LWORD _BLK2 :1;\r
+    IO_LWORD _BLK1 :1;\r
+    IO_LWORD _BLK0 :1;\r
+    IO_LWORD _DTCF :1;\r
+    IO_LWORD _DTCE :1;\r
+    IO_LWORD _DTCD :1;\r
+    IO_LWORD _DTCC :1;\r
+    IO_LWORD _DTCB :1;\r
+    IO_LWORD _DTCA :1;\r
+    IO_LWORD _DTC9 :1;\r
+    IO_LWORD _DTC8 :1;\r
+    IO_LWORD _DTC7 :1;\r
+    IO_LWORD _DTC6 :1;\r
+    IO_LWORD _DTC5 :1;\r
+    IO_LWORD _DTC4 :1;\r
+    IO_LWORD _DTC3 :1;\r
+    IO_LWORD _DTC2 :1;\r
+    IO_LWORD _DTC1 :1;\r
+    IO_LWORD _DTC0 :1;\r
+  }bit;\r
+  struct{\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD _IS :5;\r
+    IO_LWORD _EIS :4;\r
+    IO_LWORD _BLK :4;\r
+    IO_LWORD _DTC :16;\r
+  }bitc;\r
+ }DMACA0STR;\r
+typedef union{  \r
+    IO_LWORD   lword;\r
+    struct{   \r
+    IO_LWORD _TYPE1 :1;\r
+    IO_LWORD _TYPE0 :1;\r
+    IO_LWORD _MOD1 :1;\r
+    IO_LWORD _MOD0 :1;\r
+    IO_LWORD _WS1 :1;\r
+    IO_LWORD _WS0 :1;\r
+    IO_LWORD _SADM :1;\r
+    IO_LWORD _DADM :1;\r
+    IO_LWORD _DTCR :1;\r
+    IO_LWORD _SADR :1;\r
+    IO_LWORD _DADR :1;\r
+    IO_LWORD _ERIE :1;\r
+    IO_LWORD _EDIE :1;\r
+    IO_LWORD _DSS2 :1;\r
+    IO_LWORD _DSS1 :1;\r
+    IO_LWORD _DSS0 :1;\r
+    IO_LWORD _SASZ7 :1;\r
+    IO_LWORD _SASZ6 :1;\r
+    IO_LWORD _SASZ5 :1;\r
+    IO_LWORD _SASZ4 :1;\r
+    IO_LWORD _SASZ3 :1;\r
+    IO_LWORD _SASZ2 :1;\r
+    IO_LWORD _SASZ1 :1;\r
+    IO_LWORD _SASZ0 :1;\r
+    IO_LWORD _DASZ7 :1;\r
+    IO_LWORD _DASZ6 :1;\r
+    IO_LWORD _DASZ5 :1;\r
+    IO_LWORD _DASZ4 :1;\r
+    IO_LWORD _DASZ3 :1;\r
+    IO_LWORD _DASZ2 :1;\r
+    IO_LWORD _DASZ1 :1;\r
+    IO_LWORD _DASZ0 :1;\r
+  }bit;\r
+  struct{\r
+    IO_LWORD _TYPE :2;\r
+    IO_LWORD _MOD :2;\r
+    IO_LWORD _WS :2;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD _DSS :3;\r
+    IO_LWORD _SASZ :8;\r
+    IO_LWORD _DASZ :8;\r
+  }bitc;\r
+ }DMACB0STR;\r
+typedef union{  \r
+    IO_LWORD   lword;\r
+    struct{   \r
+    IO_LWORD _DENB :1;\r
+    IO_LWORD _PAUS :1;\r
+    IO_LWORD _STRG :1;\r
+    IO_LWORD _IS4 :1;\r
+    IO_LWORD _IS3 :1;\r
+    IO_LWORD _IS2 :1;\r
+    IO_LWORD _IS1 :1;\r
+    IO_LWORD _IS0 :1;\r
+    IO_LWORD _EIS3 :1;\r
+    IO_LWORD _EIS2 :1;\r
+    IO_LWORD _EIS1 :1;\r
+    IO_LWORD _EIS0 :1;\r
+    IO_LWORD _BLK3 :1;\r
+    IO_LWORD _BLK2 :1;\r
+    IO_LWORD _BLK1 :1;\r
+    IO_LWORD _BLK0 :1;\r
+    IO_LWORD _DTCF :1;\r
+    IO_LWORD _DTCE :1;\r
+    IO_LWORD _DTCD :1;\r
+    IO_LWORD _DTCC :1;\r
+    IO_LWORD _DTCB :1;\r
+    IO_LWORD _DTCA :1;\r
+    IO_LWORD _DTC9 :1;\r
+    IO_LWORD _DTC8 :1;\r
+    IO_LWORD _DTC7 :1;\r
+    IO_LWORD _DTC6 :1;\r
+    IO_LWORD _DTC5 :1;\r
+    IO_LWORD _DTC4 :1;\r
+    IO_LWORD _DTC3 :1;\r
+    IO_LWORD _DTC2 :1;\r
+    IO_LWORD _DTC1 :1;\r
+    IO_LWORD _DTC0 :1;\r
+  }bit;\r
+  struct{\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD _IS :5;\r
+    IO_LWORD _EIS :4;\r
+    IO_LWORD _BLK :4;\r
+    IO_LWORD _DTC :16;\r
+  }bitc;\r
+ }DMACA1STR;\r
+typedef union{  \r
+    IO_LWORD   lword;\r
+    struct{   \r
+    IO_LWORD _TYPE1 :1;\r
+    IO_LWORD _TYPE0 :1;\r
+    IO_LWORD _MOD1 :1;\r
+    IO_LWORD _MOD0 :1;\r
+    IO_LWORD _WS1 :1;\r
+    IO_LWORD _WS0 :1;\r
+    IO_LWORD _SADM :1;\r
+    IO_LWORD _DADM :1;\r
+    IO_LWORD _DTCR :1;\r
+    IO_LWORD _SADR :1;\r
+    IO_LWORD _DADR :1;\r
+    IO_LWORD _ERIE :1;\r
+    IO_LWORD _EDIE :1;\r
+    IO_LWORD _DSS2 :1;\r
+    IO_LWORD _DSS1 :1;\r
+    IO_LWORD _DSS0 :1;\r
+    IO_LWORD _SASZ7 :1;\r
+    IO_LWORD _SASZ6 :1;\r
+    IO_LWORD _SASZ5 :1;\r
+    IO_LWORD _SASZ4 :1;\r
+    IO_LWORD _SASZ3 :1;\r
+    IO_LWORD _SASZ2 :1;\r
+    IO_LWORD _SASZ1 :1;\r
+    IO_LWORD _SASZ0 :1;\r
+    IO_LWORD _DASZ7 :1;\r
+    IO_LWORD _DASZ6 :1;\r
+    IO_LWORD _DASZ5 :1;\r
+    IO_LWORD _DASZ4 :1;\r
+    IO_LWORD _DASZ3 :1;\r
+    IO_LWORD _DASZ2 :1;\r
+    IO_LWORD _DASZ1 :1;\r
+    IO_LWORD _DASZ0 :1;\r
+  }bit;\r
+  struct{\r
+    IO_LWORD _TYPE :2;\r
+    IO_LWORD _MOD :2;\r
+    IO_LWORD _WS :2;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD _DSS :3;\r
+    IO_LWORD _SASZ :8;\r
+    IO_LWORD _DASZ :8;\r
+  }bitc;\r
+ }DMACB1STR;\r
+typedef union{  \r
+    IO_LWORD   lword;\r
+    struct{   \r
+    IO_LWORD _DENB :1;\r
+    IO_LWORD _PAUS :1;\r
+    IO_LWORD _STRG :1;\r
+    IO_LWORD _IS4 :1;\r
+    IO_LWORD _IS3 :1;\r
+    IO_LWORD _IS2 :1;\r
+    IO_LWORD _IS1 :1;\r
+    IO_LWORD _IS0 :1;\r
+    IO_LWORD _EIS3 :1;\r
+    IO_LWORD _EIS2 :1;\r
+    IO_LWORD _EIS1 :1;\r
+    IO_LWORD _EIS0 :1;\r
+    IO_LWORD _BLK3 :1;\r
+    IO_LWORD _BLK2 :1;\r
+    IO_LWORD _BLK1 :1;\r
+    IO_LWORD _BLK0 :1;\r
+    IO_LWORD _DTCF :1;\r
+    IO_LWORD _DTCE :1;\r
+    IO_LWORD _DTCD :1;\r
+    IO_LWORD _DTCC :1;\r
+    IO_LWORD _DTCB :1;\r
+    IO_LWORD _DTCA :1;\r
+    IO_LWORD _DTC9 :1;\r
+    IO_LWORD _DTC8 :1;\r
+    IO_LWORD _DTC7 :1;\r
+    IO_LWORD _DTC6 :1;\r
+    IO_LWORD _DTC5 :1;\r
+    IO_LWORD _DTC4 :1;\r
+    IO_LWORD _DTC3 :1;\r
+    IO_LWORD _DTC2 :1;\r
+    IO_LWORD _DTC1 :1;\r
+    IO_LWORD _DTC0 :1;\r
+  }bit;\r
+  struct{\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD _IS :5;\r
+    IO_LWORD _EIS :4;\r
+    IO_LWORD _BLK :4;\r
+    IO_LWORD _DTC :16;\r
+  }bitc;\r
+ }DMACA2STR;\r
+typedef union{  \r
+    IO_LWORD   lword;\r
+    struct{   \r
+    IO_LWORD _TYPE1 :1;\r
+    IO_LWORD _TYPE0 :1;\r
+    IO_LWORD _MOD1 :1;\r
+    IO_LWORD _MOD0 :1;\r
+    IO_LWORD _WS1 :1;\r
+    IO_LWORD _WS0 :1;\r
+    IO_LWORD _SADM :1;\r
+    IO_LWORD _DADM :1;\r
+    IO_LWORD _DTCR :1;\r
+    IO_LWORD _SADR :1;\r
+    IO_LWORD _DADR :1;\r
+    IO_LWORD _ERIE :1;\r
+    IO_LWORD _EDIE :1;\r
+    IO_LWORD _DSS2 :1;\r
+    IO_LWORD _DSS1 :1;\r
+    IO_LWORD _DSS0 :1;\r
+    IO_LWORD _SASZ7 :1;\r
+    IO_LWORD _SASZ6 :1;\r
+    IO_LWORD _SASZ5 :1;\r
+    IO_LWORD _SASZ4 :1;\r
+    IO_LWORD _SASZ3 :1;\r
+    IO_LWORD _SASZ2 :1;\r
+    IO_LWORD _SASZ1 :1;\r
+    IO_LWORD _SASZ0 :1;\r
+    IO_LWORD _DASZ7 :1;\r
+    IO_LWORD _DASZ6 :1;\r
+    IO_LWORD _DASZ5 :1;\r
+    IO_LWORD _DASZ4 :1;\r
+    IO_LWORD _DASZ3 :1;\r
+    IO_LWORD _DASZ2 :1;\r
+    IO_LWORD _DASZ1 :1;\r
+    IO_LWORD _DASZ0 :1;\r
+  }bit;\r
+  struct{\r
+    IO_LWORD _TYPE :2;\r
+    IO_LWORD _MOD :2;\r
+    IO_LWORD _WS :2;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD _DSS :3;\r
+    IO_LWORD _SASZ :8;\r
+    IO_LWORD _DASZ :8;\r
+  }bitc;\r
+ }DMACB2STR;\r
+typedef union{  \r
+    IO_LWORD   lword;\r
+    struct{   \r
+    IO_LWORD _DENB :1;\r
+    IO_LWORD _PAUS :1;\r
+    IO_LWORD _STRG :1;\r
+    IO_LWORD _IS4 :1;\r
+    IO_LWORD _IS3 :1;\r
+    IO_LWORD _IS2 :1;\r
+    IO_LWORD _IS1 :1;\r
+    IO_LWORD _IS0 :1;\r
+    IO_LWORD _EIS3 :1;\r
+    IO_LWORD _EIS2 :1;\r
+    IO_LWORD _EIS1 :1;\r
+    IO_LWORD _EIS0 :1;\r
+    IO_LWORD _BLK3 :1;\r
+    IO_LWORD _BLK2 :1;\r
+    IO_LWORD _BLK1 :1;\r
+    IO_LWORD _BLK0 :1;\r
+    IO_LWORD _DTCF :1;\r
+    IO_LWORD _DTCE :1;\r
+    IO_LWORD _DTCD :1;\r
+    IO_LWORD _DTCC :1;\r
+    IO_LWORD _DTCB :1;\r
+    IO_LWORD _DTCA :1;\r
+    IO_LWORD _DTC9 :1;\r
+    IO_LWORD _DTC8 :1;\r
+    IO_LWORD _DTC7 :1;\r
+    IO_LWORD _DTC6 :1;\r
+    IO_LWORD _DTC5 :1;\r
+    IO_LWORD _DTC4 :1;\r
+    IO_LWORD _DTC3 :1;\r
+    IO_LWORD _DTC2 :1;\r
+    IO_LWORD _DTC1 :1;\r
+    IO_LWORD _DTC0 :1;\r
+  }bit;\r
+  struct{\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD _IS :5;\r
+    IO_LWORD _EIS :4;\r
+    IO_LWORD _BLK :4;\r
+    IO_LWORD _DTC :16;\r
+  }bitc;\r
+ }DMACA3STR;\r
+typedef union{  \r
+    IO_LWORD   lword;\r
+    struct{   \r
+    IO_LWORD _TYPE1 :1;\r
+    IO_LWORD _TYPE0 :1;\r
+    IO_LWORD _MOD1 :1;\r
+    IO_LWORD _MOD0 :1;\r
+    IO_LWORD _WS1 :1;\r
+    IO_LWORD _WS0 :1;\r
+    IO_LWORD _SADM :1;\r
+    IO_LWORD _DADM :1;\r
+    IO_LWORD _DTCR :1;\r
+    IO_LWORD _SADR :1;\r
+    IO_LWORD _DADR :1;\r
+    IO_LWORD _ERIE :1;\r
+    IO_LWORD _EDIE :1;\r
+    IO_LWORD _DSS2 :1;\r
+    IO_LWORD _DSS1 :1;\r
+    IO_LWORD _DSS0 :1;\r
+    IO_LWORD _SASZ7 :1;\r
+    IO_LWORD _SASZ6 :1;\r
+    IO_LWORD _SASZ5 :1;\r
+    IO_LWORD _SASZ4 :1;\r
+    IO_LWORD _SASZ3 :1;\r
+    IO_LWORD _SASZ2 :1;\r
+    IO_LWORD _SASZ1 :1;\r
+    IO_LWORD _SASZ0 :1;\r
+    IO_LWORD _DASZ7 :1;\r
+    IO_LWORD _DASZ6 :1;\r
+    IO_LWORD _DASZ5 :1;\r
+    IO_LWORD _DASZ4 :1;\r
+    IO_LWORD _DASZ3 :1;\r
+    IO_LWORD _DASZ2 :1;\r
+    IO_LWORD _DASZ1 :1;\r
+    IO_LWORD _DASZ0 :1;\r
+  }bit;\r
+  struct{\r
+    IO_LWORD _TYPE :2;\r
+    IO_LWORD _MOD :2;\r
+    IO_LWORD _WS :2;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD _DSS :3;\r
+    IO_LWORD _SASZ :8;\r
+    IO_LWORD _DASZ :8;\r
+  }bitc;\r
+ }DMACB3STR;\r
+typedef union{  \r
+    IO_LWORD   lword;\r
+    struct{   \r
+    IO_LWORD _DENB :1;\r
+    IO_LWORD _PAUS :1;\r
+    IO_LWORD _STRG :1;\r
+    IO_LWORD _IS4 :1;\r
+    IO_LWORD _IS3 :1;\r
+    IO_LWORD _IS2 :1;\r
+    IO_LWORD _IS1 :1;\r
+    IO_LWORD _IS0 :1;\r
+    IO_LWORD _EIS3 :1;\r
+    IO_LWORD _EIS2 :1;\r
+    IO_LWORD _EIS1 :1;\r
+    IO_LWORD _EIS0 :1;\r
+    IO_LWORD _BLK3 :1;\r
+    IO_LWORD _BLK2 :1;\r
+    IO_LWORD _BLK1 :1;\r
+    IO_LWORD _BLK0 :1;\r
+    IO_LWORD _DTCF :1;\r
+    IO_LWORD _DTCE :1;\r
+    IO_LWORD _DTCD :1;\r
+    IO_LWORD _DTCC :1;\r
+    IO_LWORD _DTCB :1;\r
+    IO_LWORD _DTCA :1;\r
+    IO_LWORD _DTC9 :1;\r
+    IO_LWORD _DTC8 :1;\r
+    IO_LWORD _DTC7 :1;\r
+    IO_LWORD _DTC6 :1;\r
+    IO_LWORD _DTC5 :1;\r
+    IO_LWORD _DTC4 :1;\r
+    IO_LWORD _DTC3 :1;\r
+    IO_LWORD _DTC2 :1;\r
+    IO_LWORD _DTC1 :1;\r
+    IO_LWORD _DTC0 :1;\r
+  }bit;\r
+  struct{\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD _IS :5;\r
+    IO_LWORD _EIS :4;\r
+    IO_LWORD _BLK :4;\r
+    IO_LWORD _DTC :16;\r
+  }bitc;\r
+ }DMACA4STR;\r
+typedef union{  \r
+    IO_LWORD   lword;\r
+    struct{   \r
+    IO_LWORD _TYPE1 :1;\r
+    IO_LWORD _TYPE0 :1;\r
+    IO_LWORD _MOD1 :1;\r
+    IO_LWORD _MOD0 :1;\r
+    IO_LWORD _WS1 :1;\r
+    IO_LWORD _WS0 :1;\r
+    IO_LWORD _SADM :1;\r
+    IO_LWORD _DADM :1;\r
+    IO_LWORD _DTCR :1;\r
+    IO_LWORD _SADR :1;\r
+    IO_LWORD _DADR :1;\r
+    IO_LWORD _ERIE :1;\r
+    IO_LWORD _EDIE :1;\r
+    IO_LWORD _DSS2 :1;\r
+    IO_LWORD _DSS1 :1;\r
+    IO_LWORD _DSS0 :1;\r
+    IO_LWORD _SASZ7 :1;\r
+    IO_LWORD _SASZ6 :1;\r
+    IO_LWORD _SASZ5 :1;\r
+    IO_LWORD _SASZ4 :1;\r
+    IO_LWORD _SASZ3 :1;\r
+    IO_LWORD _SASZ2 :1;\r
+    IO_LWORD _SASZ1 :1;\r
+    IO_LWORD _SASZ0 :1;\r
+    IO_LWORD _DASZ7 :1;\r
+    IO_LWORD _DASZ6 :1;\r
+    IO_LWORD _DASZ5 :1;\r
+    IO_LWORD _DASZ4 :1;\r
+    IO_LWORD _DASZ3 :1;\r
+    IO_LWORD _DASZ2 :1;\r
+    IO_LWORD _DASZ1 :1;\r
+    IO_LWORD _DASZ0 :1;\r
+  }bit;\r
+  struct{\r
+    IO_LWORD _TYPE :2;\r
+    IO_LWORD _MOD :2;\r
+    IO_LWORD _WS :2;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD _DSS :3;\r
+    IO_LWORD _SASZ :8;\r
+    IO_LWORD _DASZ :8;\r
+  }bitc;\r
+ }DMACB4STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _DMAE :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _PM01 :1;\r
+    IO_BYTE _DMAH3 :1;\r
+    IO_BYTE _DMAH2 :1;\r
+    IO_BYTE _DMAH1 :1;\r
+    IO_BYTE _DMAH0 :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE _DMAH :4;\r
+  }bitc;\r
+ }DMACRSTR;\r
+typedef union{   /* Input Capture 4-7 */\r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _ICP5 :1;\r
+    IO_BYTE _ICP4 :1;\r
+    IO_BYTE _ICE5 :1;\r
+    IO_BYTE _ICE4 :1;\r
+    IO_BYTE _EG51 :1;\r
+    IO_BYTE _EG50 :1;\r
+    IO_BYTE _EG41 :1;\r
+    IO_BYTE _EG40 :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE _EG5 :2;\r
+    IO_BYTE _EG4 :2;\r
+  }bitc;\r
+ }ICS45STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _ICP7 :1;\r
+    IO_BYTE _ICP6 :1;\r
+    IO_BYTE _ICE7 :1;\r
+    IO_BYTE _ICE6 :1;\r
+    IO_BYTE _EG71 :1;\r
+    IO_BYTE _EG70 :1;\r
+    IO_BYTE _EG61 :1;\r
+    IO_BYTE _EG60 :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE _EG7 :2;\r
+    IO_BYTE _EG6 :2;\r
+  }bitc;\r
+ }ICS67STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _CP15 :1;\r
+    IO_WORD _CP14 :1;\r
+    IO_WORD _CP13 :1;\r
+    IO_WORD _CP12 :1;\r
+    IO_WORD _CP11 :1;\r
+    IO_WORD _CP10 :1;\r
+    IO_WORD _CP9 :1;\r
+    IO_WORD _CP8 :1;\r
+    IO_WORD _CP7 :1;\r
+    IO_WORD _CP6 :1;\r
+    IO_WORD _CP5 :1;\r
+    IO_WORD _CP4 :1;\r
+    IO_WORD _CP3 :1;\r
+    IO_WORD _CP2 :1;\r
+    IO_WORD _CP1 :1;\r
+    IO_WORD _CP0 :1;\r
+  }bit;\r
+ }IPCP4STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _CP15 :1;\r
+    IO_WORD _CP14 :1;\r
+    IO_WORD _CP13 :1;\r
+    IO_WORD _CP12 :1;\r
+    IO_WORD _CP11 :1;\r
+    IO_WORD _CP10 :1;\r
+    IO_WORD _CP9 :1;\r
+    IO_WORD _CP8 :1;\r
+    IO_WORD _CP7 :1;\r
+    IO_WORD _CP6 :1;\r
+    IO_WORD _CP5 :1;\r
+    IO_WORD _CP4 :1;\r
+    IO_WORD _CP3 :1;\r
+    IO_WORD _CP2 :1;\r
+    IO_WORD _CP1 :1;\r
+    IO_WORD _CP0 :1;\r
+  }bit;\r
+ }IPCP5STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _CP15 :1;\r
+    IO_WORD _CP14 :1;\r
+    IO_WORD _CP13 :1;\r
+    IO_WORD _CP12 :1;\r
+    IO_WORD _CP11 :1;\r
+    IO_WORD _CP10 :1;\r
+    IO_WORD _CP9 :1;\r
+    IO_WORD _CP8 :1;\r
+    IO_WORD _CP7 :1;\r
+    IO_WORD _CP6 :1;\r
+    IO_WORD _CP5 :1;\r
+    IO_WORD _CP4 :1;\r
+    IO_WORD _CP3 :1;\r
+    IO_WORD _CP2 :1;\r
+    IO_WORD _CP1 :1;\r
+    IO_WORD _CP0 :1;\r
+  }bit;\r
+ }IPCP6STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _CP15 :1;\r
+    IO_WORD _CP14 :1;\r
+    IO_WORD _CP13 :1;\r
+    IO_WORD _CP12 :1;\r
+    IO_WORD _CP11 :1;\r
+    IO_WORD _CP10 :1;\r
+    IO_WORD _CP9 :1;\r
+    IO_WORD _CP8 :1;\r
+    IO_WORD _CP7 :1;\r
+    IO_WORD _CP6 :1;\r
+    IO_WORD _CP5 :1;\r
+    IO_WORD _CP4 :1;\r
+    IO_WORD _CP3 :1;\r
+    IO_WORD _CP2 :1;\r
+    IO_WORD _CP1 :1;\r
+    IO_WORD _CP0 :1;\r
+  }bit;\r
+ }IPCP7STR;\r
+typedef union{   /* Free Running Timer4 */\r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _T15 :1;\r
+    IO_WORD _T14 :1;\r
+    IO_WORD _T13 :1;\r
+    IO_WORD _T12 :1;\r
+    IO_WORD _T11 :1;\r
+    IO_WORD _T10 :1;\r
+    IO_WORD _T9 :1;\r
+    IO_WORD _T8 :1;\r
+    IO_WORD _T7 :1;\r
+    IO_WORD _T6 :1;\r
+    IO_WORD _T5 :1;\r
+    IO_WORD _T4 :1;\r
+    IO_WORD _T3 :1;\r
+    IO_WORD _T2 :1;\r
+    IO_WORD _T1 :1;\r
+    IO_WORD _T0 :1;\r
+  }bit;\r
+ }TCDT4STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _ECLK :1;\r
+    IO_BYTE _IVF :1;\r
+    IO_BYTE _IVFE :1;\r
+    IO_BYTE _STOP :1;\r
+    IO_BYTE _MODE :1;\r
+    IO_BYTE _CLR :1;\r
+    IO_BYTE _CLK1 :1;\r
+    IO_BYTE _CLK0 :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE _CLK :2;\r
+  }bitc;\r
+ }TCCS4STR;\r
+typedef union{   /* Free Running Timer5 */\r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _T15 :1;\r
+    IO_WORD _T14 :1;\r
+    IO_WORD _T13 :1;\r
+    IO_WORD _T12 :1;\r
+    IO_WORD _T11 :1;\r
+    IO_WORD _T10 :1;\r
+    IO_WORD _T9 :1;\r
+    IO_WORD _T8 :1;\r
+    IO_WORD _T7 :1;\r
+    IO_WORD _T6 :1;\r
+    IO_WORD _T5 :1;\r
+    IO_WORD _T4 :1;\r
+    IO_WORD _T3 :1;\r
+    IO_WORD _T2 :1;\r
+    IO_WORD _T1 :1;\r
+    IO_WORD _T0 :1;\r
+  }bit;\r
+ }TCDT5STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _ECLK :1;\r
+    IO_BYTE _IVF :1;\r
+    IO_BYTE _IVFE :1;\r
+    IO_BYTE _STOP :1;\r
+    IO_BYTE _MODE :1;\r
+    IO_BYTE _CLR :1;\r
+    IO_BYTE _CLK1 :1;\r
+    IO_BYTE _CLK0 :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE _CLK :2;\r
+  }bitc;\r
+ }TCCS5STR;\r
+typedef union{   /* Free Running Timer6 */\r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _T15 :1;\r
+    IO_WORD _T14 :1;\r
+    IO_WORD _T13 :1;\r
+    IO_WORD _T12 :1;\r
+    IO_WORD _T11 :1;\r
+    IO_WORD _T10 :1;\r
+    IO_WORD _T9 :1;\r
+    IO_WORD _T8 :1;\r
+    IO_WORD _T7 :1;\r
+    IO_WORD _T6 :1;\r
+    IO_WORD _T5 :1;\r
+    IO_WORD _T4 :1;\r
+    IO_WORD _T3 :1;\r
+    IO_WORD _T2 :1;\r
+    IO_WORD _T1 :1;\r
+    IO_WORD _T0 :1;\r
+  }bit;\r
+ }TCDT6STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _ECLK :1;\r
+    IO_BYTE _IVF :1;\r
+    IO_BYTE _IVFE :1;\r
+    IO_BYTE _STOP :1;\r
+    IO_BYTE _MODE :1;\r
+    IO_BYTE _CLR :1;\r
+    IO_BYTE _CLK1 :1;\r
+    IO_BYTE _CLK0 :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE _CLK :2;\r
+  }bitc;\r
+ }TCCS6STR;\r
+typedef union{   /* Free Running Timer7 */\r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _T15 :1;\r
+    IO_WORD _T14 :1;\r
+    IO_WORD _T13 :1;\r
+    IO_WORD _T12 :1;\r
+    IO_WORD _T11 :1;\r
+    IO_WORD _T10 :1;\r
+    IO_WORD _T9 :1;\r
+    IO_WORD _T8 :1;\r
+    IO_WORD _T7 :1;\r
+    IO_WORD _T6 :1;\r
+    IO_WORD _T5 :1;\r
+    IO_WORD _T4 :1;\r
+    IO_WORD _T3 :1;\r
+    IO_WORD _T2 :1;\r
+    IO_WORD _T1 :1;\r
+    IO_WORD _T0 :1;\r
+  }bit;\r
+ }TCDT7STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _ECLK :1;\r
+    IO_BYTE _IVF :1;\r
+    IO_BYTE _IVFE :1;\r
+    IO_BYTE _STOP :1;\r
+    IO_BYTE _MODE :1;\r
+    IO_BYTE _CLR :1;\r
+    IO_BYTE _CLK1 :1;\r
+    IO_BYTE _CLK0 :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE _CLK :2;\r
+  }bitc;\r
+ }TCCS7STR;\r
+typedef union{   /* Up/Down Counter 0-1 */\r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _D15 :1;\r
+    IO_WORD _D14 :1;\r
+    IO_WORD _D13 :1;\r
+    IO_WORD _D12 :1;\r
+    IO_WORD _D11 :1;\r
+    IO_WORD _D10 :1;\r
+    IO_WORD _D9 :1;\r
+    IO_WORD _D8 :1;\r
+    IO_WORD _D7 :1;\r
+    IO_WORD _D6 :1;\r
+    IO_WORD _D5 :1;\r
+    IO_WORD _D4 :1;\r
+    IO_WORD _D3 :1;\r
+    IO_WORD _D2 :1;\r
+    IO_WORD _D1 :1;\r
+    IO_WORD _D0 :1;\r
+  }bit;\r
+ }UDRC10STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }UDRC1STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }UDRC0STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _D15 :1;\r
+    IO_WORD _D14 :1;\r
+    IO_WORD _D13 :1;\r
+    IO_WORD _D12 :1;\r
+    IO_WORD _D11 :1;\r
+    IO_WORD _D10 :1;\r
+    IO_WORD _D9 :1;\r
+    IO_WORD _D8 :1;\r
+    IO_WORD _D7 :1;\r
+    IO_WORD _D6 :1;\r
+    IO_WORD _D5 :1;\r
+    IO_WORD _D4 :1;\r
+    IO_WORD _D3 :1;\r
+    IO_WORD _D2 :1;\r
+    IO_WORD _D1 :1;\r
+    IO_WORD _D0 :1;\r
+  }bit;\r
+ }UDCR10STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }UDCR1STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }UDCR0STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _M16E :1;\r
+    IO_WORD _CDCF :1;\r
+    IO_WORD _CFIE :1;\r
+    IO_WORD _CLKS :1;\r
+    IO_WORD _CMS1 :1;\r
+    IO_WORD _CMS0 :1;\r
+    IO_WORD _CES1 :1;\r
+    IO_WORD _CES0 :1;\r
+    IO_WORD  :1;\r
+    IO_WORD _CTUT :1;\r
+    IO_WORD _UCRE :1;\r
+    IO_WORD _RLDE :1;\r
+    IO_WORD _UDCLR :1;\r
+    IO_WORD _CGSC :1;\r
+    IO_WORD _CGE1 :1;\r
+    IO_WORD _CGE0 :1;\r
+  }bit;\r
+  struct{\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD _CMS :2;\r
+    IO_WORD _CES :2;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD _CGE :2;\r
+  }bitc;\r
+ }UDCC0STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _M16E :1;\r
+    IO_BYTE _CDCF :1;\r
+    IO_BYTE _CFIE :1;\r
+    IO_BYTE _CLKS :1;\r
+    IO_BYTE _CMS1 :1;\r
+    IO_BYTE _CMS0 :1;\r
+    IO_BYTE _CES1 :1;\r
+    IO_BYTE _CES0 :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE :4;\r
+    IO_BYTE _CMS :2;\r
+    IO_BYTE _CES :2;\r
+  }bitc;\r
+ }UDCCH0STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE _CTUT :1;\r
+    IO_BYTE _UCRE :1;\r
+    IO_BYTE _RLDE :1;\r
+    IO_BYTE _UDCLR :1;\r
+    IO_BYTE _CGSC :1;\r
+    IO_BYTE _CGE1 :1;\r
+    IO_BYTE _CGE0 :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE :6;\r
+    IO_BYTE _CGE :2;\r
+  }bitc;\r
+ }UDCCL0STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _CSTR :1;\r
+    IO_BYTE _CITE :1;\r
+    IO_BYTE _UDIE :1;\r
+    IO_BYTE _CMPF :1;\r
+    IO_BYTE _OVFF :1;\r
+    IO_BYTE _UDFF :1;\r
+    IO_BYTE _UDF1 :1;\r
+    IO_BYTE _UDF0 :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE _UDF :2;\r
+  }bitc;\r
+ }UDCS0STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _RESV15 :1;\r
+    IO_WORD _CDCF :1;\r
+    IO_WORD _CFIE :1;\r
+    IO_WORD _CLKS :1;\r
+    IO_WORD _CMS1 :1;\r
+    IO_WORD _CMS0 :1;\r
+    IO_WORD _CES1 :1;\r
+    IO_WORD _CES0 :1;\r
+    IO_WORD  :1;\r
+    IO_WORD _CTUT :1;\r
+    IO_WORD _UCRE :1;\r
+    IO_WORD _RLDE :1;\r
+    IO_WORD _UDCLR :1;\r
+    IO_WORD _CGSC :1;\r
+    IO_WORD _CGE1 :1;\r
+    IO_WORD _CGE0 :1;\r
+  }bit;\r
+  struct{\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD _CMS :2;\r
+    IO_WORD _CES :2;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD _CGE :2;\r
+  }bitc;\r
+ }UDCC1STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _RESV15 :1;\r
+    IO_BYTE _CDCF :1;\r
+    IO_BYTE _CFIE :1;\r
+    IO_BYTE _CLKS :1;\r
+    IO_BYTE _CMS1 :1;\r
+    IO_BYTE _CMS0 :1;\r
+    IO_BYTE _CES1 :1;\r
+    IO_BYTE _CES0 :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE :4;\r
+    IO_BYTE _CMS :2;\r
+    IO_BYTE _CES :2;\r
+  }bitc;\r
+ }UDCCH1STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE _CTUT :1;\r
+    IO_BYTE _UCRE :1;\r
+    IO_BYTE _RLDE :1;\r
+    IO_BYTE _UDCLR :1;\r
+    IO_BYTE _CGSC :1;\r
+    IO_BYTE _CGE1 :1;\r
+    IO_BYTE _CGE0 :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE :6;\r
+    IO_BYTE _CGE :2;\r
+  }bitc;\r
+ }UDCCL1STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _CSTR :1;\r
+    IO_BYTE _CITE :1;\r
+    IO_BYTE _UDIE :1;\r
+    IO_BYTE _CMPF :1;\r
+    IO_BYTE _OVFF :1;\r
+    IO_BYTE _UDFF :1;\r
+    IO_BYTE _UDF1 :1;\r
+    IO_BYTE _UDF0 :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE _UDF :2;\r
+  }bitc;\r
+ }UDCS1STR;\r
+typedef union{   /* Up/Down Counter 2-3 */\r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _D15 :1;\r
+    IO_WORD _D14 :1;\r
+    IO_WORD _D13 :1;\r
+    IO_WORD _D12 :1;\r
+    IO_WORD _D11 :1;\r
+    IO_WORD _D10 :1;\r
+    IO_WORD _D9 :1;\r
+    IO_WORD _D8 :1;\r
+    IO_WORD _D7 :1;\r
+    IO_WORD _D6 :1;\r
+    IO_WORD _D5 :1;\r
+    IO_WORD _D4 :1;\r
+    IO_WORD _D3 :1;\r
+    IO_WORD _D2 :1;\r
+    IO_WORD _D1 :1;\r
+    IO_WORD _D0 :1;\r
+  }bit;\r
+ }UDRC32STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }UDRC3STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }UDRC2STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _D15 :1;\r
+    IO_WORD _D14 :1;\r
+    IO_WORD _D13 :1;\r
+    IO_WORD _D12 :1;\r
+    IO_WORD _D11 :1;\r
+    IO_WORD _D10 :1;\r
+    IO_WORD _D9 :1;\r
+    IO_WORD _D8 :1;\r
+    IO_WORD _D7 :1;\r
+    IO_WORD _D6 :1;\r
+    IO_WORD _D5 :1;\r
+    IO_WORD _D4 :1;\r
+    IO_WORD _D3 :1;\r
+    IO_WORD _D2 :1;\r
+    IO_WORD _D1 :1;\r
+    IO_WORD _D0 :1;\r
+  }bit;\r
+ }UDCR32STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }UDCR3STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }UDCR2STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _M16E :1;\r
+    IO_WORD _CDCF :1;\r
+    IO_WORD _CFIE :1;\r
+    IO_WORD _CLKS :1;\r
+    IO_WORD _CMS1 :1;\r
+    IO_WORD _CMS0 :1;\r
+    IO_WORD _CES1 :1;\r
+    IO_WORD _CES0 :1;\r
+    IO_WORD  :1;\r
+    IO_WORD _CTUT :1;\r
+    IO_WORD _UCRE :1;\r
+    IO_WORD _RLDE :1;\r
+    IO_WORD _UDCLR :1;\r
+    IO_WORD _CGSC :1;\r
+    IO_WORD _CGE1 :1;\r
+    IO_WORD _CGE0 :1;\r
+  }bit;\r
+  struct{\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD _CMS :2;\r
+    IO_WORD _CES :2;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD _CGE :2;\r
+  }bitc;\r
+ }UDCC2STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _M16E :1;\r
+    IO_BYTE _CDCF :1;\r
+    IO_BYTE _CFIE :1;\r
+    IO_BYTE _CLKS :1;\r
+    IO_BYTE _CMS1 :1;\r
+    IO_BYTE _CMS0 :1;\r
+    IO_BYTE _CES1 :1;\r
+    IO_BYTE _CES0 :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE :4;\r
+    IO_BYTE _CMS :2;\r
+    IO_BYTE _CES :2;\r
+  }bitc;\r
+ }UDCCH2STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE _CTUT :1;\r
+    IO_BYTE _UCRE :1;\r
+    IO_BYTE _RLDE :1;\r
+    IO_BYTE _UDCLR :1;\r
+    IO_BYTE _CGSC :1;\r
+    IO_BYTE _CGE1 :1;\r
+    IO_BYTE _CGE0 :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE :6;\r
+    IO_BYTE _CGE :2;\r
+  }bitc;\r
+ }UDCCL2STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _CSTR :1;\r
+    IO_BYTE _CITE :1;\r
+    IO_BYTE _UDIE :1;\r
+    IO_BYTE _CMPF :1;\r
+    IO_BYTE _OVFF :1;\r
+    IO_BYTE _UDFF :1;\r
+    IO_BYTE _UDF1 :1;\r
+    IO_BYTE _UDF0 :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE _UDF :2;\r
+  }bitc;\r
+ }UDCS2STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _RESV15 :1;\r
+    IO_WORD _CDCF :1;\r
+    IO_WORD _CFIE :1;\r
+    IO_WORD _CLKS :1;\r
+    IO_WORD _CMS1 :1;\r
+    IO_WORD _CMS0 :1;\r
+    IO_WORD _CES1 :1;\r
+    IO_WORD _CES0 :1;\r
+    IO_WORD  :1;\r
+    IO_WORD _CTUT :1;\r
+    IO_WORD _UCRE :1;\r
+    IO_WORD _RLDE :1;\r
+    IO_WORD _UDCLR :1;\r
+    IO_WORD _CGSC :1;\r
+    IO_WORD _CGE1 :1;\r
+    IO_WORD _CGE0 :1;\r
+  }bit;\r
+  struct{\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD _CMS :2;\r
+    IO_WORD _CES :2;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD _CGE :2;\r
+  }bitc;\r
+ }UDCC3STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _RESV15 :1;\r
+    IO_BYTE _CDCF :1;\r
+    IO_BYTE _CFIE :1;\r
+    IO_BYTE _CLKS :1;\r
+    IO_BYTE _CMS1 :1;\r
+    IO_BYTE _CMS0 :1;\r
+    IO_BYTE _CES1 :1;\r
+    IO_BYTE _CES0 :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE :4;\r
+    IO_BYTE _CMS :2;\r
+    IO_BYTE _CES :2;\r
+  }bitc;\r
+ }UDCCH3STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE _CTUT :1;\r
+    IO_BYTE _UCRE :1;\r
+    IO_BYTE _RLDE :1;\r
+    IO_BYTE _UDCLR :1;\r
+    IO_BYTE _CGSC :1;\r
+    IO_BYTE _CGE1 :1;\r
+    IO_BYTE _CGE0 :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE :6;\r
+    IO_BYTE _CGE :2;\r
+  }bitc;\r
+ }UDCCL3STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _CSTR :1;\r
+    IO_BYTE _CITE :1;\r
+    IO_BYTE _UDIE :1;\r
+    IO_BYTE _CMPF :1;\r
+    IO_BYTE _OVFF :1;\r
+    IO_BYTE _UDFF :1;\r
+    IO_BYTE _UDF1 :1;\r
+    IO_BYTE _UDF0 :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE _UDF :2;\r
+  }bitc;\r
+ }UDCS3STR;\r
+typedef union{   /* PPG Control 12-15 */\r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _TSEL33 :1;\r
+    IO_WORD _TSEL32 :1;\r
+    IO_WORD _TSEL31 :1;\r
+    IO_WORD _TSEL30 :1;\r
+    IO_WORD _TSEL23 :1;\r
+    IO_WORD _TSEL22 :1;\r
+    IO_WORD _TSEL21 :1;\r
+    IO_WORD _TSEL20 :1;\r
+    IO_WORD _TSEL13 :1;\r
+    IO_WORD _TSEL12 :1;\r
+    IO_WORD _TSEL11 :1;\r
+    IO_WORD _TSEL10 :1;\r
+    IO_WORD _TSEL03 :1;\r
+    IO_WORD _TSEL02 :1;\r
+    IO_WORD _TSEL01 :1;\r
+    IO_WORD _TSEL00 :1;\r
+  }bit;\r
+ }GCN13STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _EN3 :1;\r
+    IO_BYTE _EN2 :1;\r
+    IO_BYTE _EN1 :1;\r
+    IO_BYTE _EN0 :1;\r
+  }bit;\r
+ }GCN23STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _CNTE :1;\r
+    IO_WORD _STGR :1;\r
+    IO_WORD _MDSE :1;\r
+    IO_WORD _RTRG :1;\r
+    IO_WORD _CKS1 :1;\r
+    IO_WORD _CKS0 :1;\r
+    IO_WORD _PGMS :1;\r
+    IO_WORD  :1;\r
+    IO_WORD _EGS1 :1;\r
+    IO_WORD _EGS0 :1;\r
+    IO_WORD _IREN :1;\r
+    IO_WORD _IRQF :1;\r
+    IO_WORD _IRS1 :1;\r
+    IO_WORD _IRS0 :1;\r
+    IO_WORD  :1;\r
+    IO_WORD _OSEL :1;\r
+  }bit;\r
+  struct{\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD _CKS :2;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD _EGS :2;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD _IRS :2;\r
+  }bitc;\r
+ }PCN12STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _CNTE :1;\r
+    IO_BYTE _STGR :1;\r
+    IO_BYTE _MDSE :1;\r
+    IO_BYTE _RTRG :1;\r
+    IO_BYTE _CKS1 :1;\r
+    IO_BYTE _CKS0 :1;\r
+    IO_BYTE _PGMS :1;\r
+    IO_BYTE  :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE _CKS :2;\r
+  }bitc;\r
+ }PCNH12STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _EGS1 :1;\r
+    IO_BYTE _EGS0 :1;\r
+    IO_BYTE _IREN :1;\r
+    IO_BYTE _IRQF :1;\r
+    IO_BYTE _IRS1 :1;\r
+    IO_BYTE _IRS0 :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _OSEL :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE _EGS :2;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE _IRS :2;\r
+  }bitc;\r
+ }PCNL12STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _CNTE :1;\r
+    IO_WORD _STGR :1;\r
+    IO_WORD _MDSE :1;\r
+    IO_WORD _RTRG :1;\r
+    IO_WORD _CKS1 :1;\r
+    IO_WORD _CKS0 :1;\r
+    IO_WORD _PGMS :1;\r
+    IO_WORD  :1;\r
+    IO_WORD _EGS1 :1;\r
+    IO_WORD _EGS0 :1;\r
+    IO_WORD _IREN :1;\r
+    IO_WORD _IRQF :1;\r
+    IO_WORD _IRS1 :1;\r
+    IO_WORD _IRS0 :1;\r
+    IO_WORD  :1;\r
+    IO_WORD _OSEL :1;\r
+  }bit;\r
+  struct{\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD _CKS :2;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD _EGS :2;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD _IRS :2;\r
+  }bitc;\r
+ }PCN13STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _CNTE :1;\r
+    IO_BYTE _STGR :1;\r
+    IO_BYTE _MDSE :1;\r
+    IO_BYTE _RTRG :1;\r
+    IO_BYTE _CKS1 :1;\r
+    IO_BYTE _CKS0 :1;\r
+    IO_BYTE _PGMS :1;\r
+    IO_BYTE  :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE _CKS :2;\r
+  }bitc;\r
+ }PCNH13STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _EGS1 :1;\r
+    IO_BYTE _EGS0 :1;\r
+    IO_BYTE _IREN :1;\r
+    IO_BYTE _IRQF :1;\r
+    IO_BYTE _IRS1 :1;\r
+    IO_BYTE _IRS0 :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _OSEL :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE _EGS :2;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE _IRS :2;\r
+  }bitc;\r
+ }PCNL13STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _CNTE :1;\r
+    IO_WORD _STGR :1;\r
+    IO_WORD _MDSE :1;\r
+    IO_WORD _RTRG :1;\r
+    IO_WORD _CKS1 :1;\r
+    IO_WORD _CKS0 :1;\r
+    IO_WORD _PGMS :1;\r
+    IO_WORD  :1;\r
+    IO_WORD _EGS1 :1;\r
+    IO_WORD _EGS0 :1;\r
+    IO_WORD _IREN :1;\r
+    IO_WORD _IRQF :1;\r
+    IO_WORD _IRS1 :1;\r
+    IO_WORD _IRS0 :1;\r
+    IO_WORD  :1;\r
+    IO_WORD _OSEL :1;\r
+  }bit;\r
+  struct{\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD _CKS :2;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD _EGS :2;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD _IRS :2;\r
+  }bitc;\r
+ }PCN14STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _CNTE :1;\r
+    IO_BYTE _STGR :1;\r
+    IO_BYTE _MDSE :1;\r
+    IO_BYTE _RTRG :1;\r
+    IO_BYTE _CKS1 :1;\r
+    IO_BYTE _CKS0 :1;\r
+    IO_BYTE _PGMS :1;\r
+    IO_BYTE  :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE _CKS :2;\r
+  }bitc;\r
+ }PCNH14STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _EGS1 :1;\r
+    IO_BYTE _EGS0 :1;\r
+    IO_BYTE _IREN :1;\r
+    IO_BYTE _IRQF :1;\r
+    IO_BYTE _IRS1 :1;\r
+    IO_BYTE _IRS0 :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _OSEL :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE _EGS :2;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE _IRS :2;\r
+  }bitc;\r
+ }PCNL14STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _CNTE :1;\r
+    IO_WORD _STGR :1;\r
+    IO_WORD _MDSE :1;\r
+    IO_WORD _RTRG :1;\r
+    IO_WORD _CKS1 :1;\r
+    IO_WORD _CKS0 :1;\r
+    IO_WORD _PGMS :1;\r
+    IO_WORD  :1;\r
+    IO_WORD _EGS1 :1;\r
+    IO_WORD _EGS0 :1;\r
+    IO_WORD _IREN :1;\r
+    IO_WORD _IRQF :1;\r
+    IO_WORD _IRS1 :1;\r
+    IO_WORD _IRS0 :1;\r
+    IO_WORD  :1;\r
+    IO_WORD _OSEL :1;\r
+  }bit;\r
+  struct{\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD _CKS :2;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD _EGS :2;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD _IRS :2;\r
+  }bitc;\r
+ }PCN15STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _CNTE :1;\r
+    IO_BYTE _STGR :1;\r
+    IO_BYTE _MDSE :1;\r
+    IO_BYTE _RTRG :1;\r
+    IO_BYTE _CKS1 :1;\r
+    IO_BYTE _CKS0 :1;\r
+    IO_BYTE _PGMS :1;\r
+    IO_BYTE  :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE _CKS :2;\r
+  }bitc;\r
+ }PCNH15STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _EGS1 :1;\r
+    IO_BYTE _EGS0 :1;\r
+    IO_BYTE _IREN :1;\r
+    IO_BYTE _IRQF :1;\r
+    IO_BYTE _IRS1 :1;\r
+    IO_BYTE _IRS0 :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _OSEL :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE _EGS :2;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE _IRS :2;\r
+  }bitc;\r
+ }PCNL15STR;\r
+typedef union{   /* I2C 2 */\r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _BER :1;\r
+    IO_BYTE _BEIE :1;\r
+    IO_BYTE _SCC :1;\r
+    IO_BYTE _MSS :1;\r
+    IO_BYTE _ACK :1;\r
+    IO_BYTE _GCAA :1;\r
+    IO_BYTE _INTE :1;\r
+    IO_BYTE _INT :1;\r
+  }bit;\r
+ }IBCR2STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _BB :1;\r
+    IO_BYTE _RSC :1;\r
+    IO_BYTE _AL :1;\r
+    IO_BYTE _LRB :1;\r
+    IO_BYTE _TRX :1;\r
+    IO_BYTE _AAS :1;\r
+    IO_BYTE _GCA :1;\r
+    IO_BYTE _ADT :1;\r
+  }bit;\r
+ }IBSR2STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD _TA9 :1;\r
+    IO_WORD _TA8 :1;\r
+    IO_WORD _TA7 :1;\r
+    IO_WORD _TA6 :1;\r
+    IO_WORD _TA5 :1;\r
+    IO_WORD _TA4 :1;\r
+    IO_WORD _TA3 :1;\r
+    IO_WORD _TA2 :1;\r
+    IO_WORD _TA1 :1;\r
+    IO_WORD _TA0 :1;\r
+  }bit;\r
+ }ITBA2STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _TA9 :1;\r
+    IO_BYTE _TA8 :1;\r
+  }bit;\r
+ }ITBAH2STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _TA7 :1;\r
+    IO_BYTE _TA6 :1;\r
+    IO_BYTE _TA5 :1;\r
+    IO_BYTE _TA4 :1;\r
+    IO_BYTE _TA3 :1;\r
+    IO_BYTE _TA2 :1;\r
+    IO_BYTE _TA1 :1;\r
+    IO_BYTE _TA0 :1;\r
+  }bit;\r
+ }ITBAL2STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _ENTB :1;\r
+    IO_WORD _RAL :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD _TM9 :1;\r
+    IO_WORD _TM8 :1;\r
+    IO_WORD _TM7 :1;\r
+    IO_WORD _TM6 :1;\r
+    IO_WORD _TM5 :1;\r
+    IO_WORD _TM4 :1;\r
+    IO_WORD _TM3 :1;\r
+    IO_WORD _TM2 :1;\r
+    IO_WORD _TM1 :1;\r
+    IO_WORD _TM0 :1;\r
+  }bit;\r
+ }ITMK2STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _ENTB :1;\r
+    IO_BYTE _RAL :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _TM9 :1;\r
+    IO_BYTE _TM8 :1;\r
+  }bit;\r
+ }ITMKH2STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _TM7 :1;\r
+    IO_BYTE _TM6 :1;\r
+    IO_BYTE _TM5 :1;\r
+    IO_BYTE _TM4 :1;\r
+    IO_BYTE _TM3 :1;\r
+    IO_BYTE _TM2 :1;\r
+    IO_BYTE _TM1 :1;\r
+    IO_BYTE _TM0 :1;\r
+  }bit;\r
+ }ITMKL2STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _ENSB :1;\r
+    IO_BYTE _SM6 :1;\r
+    IO_BYTE _SM5 :1;\r
+    IO_BYTE _SM4 :1;\r
+    IO_BYTE _SM3 :1;\r
+    IO_BYTE _SM2 :1;\r
+    IO_BYTE _SM1 :1;\r
+    IO_BYTE _SM0 :1;\r
+  }bit;\r
+ }ISMK2STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE _SA6 :1;\r
+    IO_BYTE _SA5 :1;\r
+    IO_BYTE _SA4 :1;\r
+    IO_BYTE _SA3 :1;\r
+    IO_BYTE _SA2 :1;\r
+    IO_BYTE _SA1 :1;\r
+    IO_BYTE _SA0 :1;\r
+  }bit;\r
+ }ISBA2STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }IDAR2STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE _NSF :1;\r
+    IO_BYTE _EN :1;\r
+    IO_BYTE _CS4 :1;\r
+    IO_BYTE _CS3 :1;\r
+    IO_BYTE _CS2 :1;\r
+    IO_BYTE _CS1 :1;\r
+    IO_BYTE _CS0 :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE _CS :5;\r
+  }bitc;\r
+ }ICCR2STR;\r
+typedef union{   /* I2C 3 */\r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _BER :1;\r
+    IO_BYTE _BEIE :1;\r
+    IO_BYTE _SCC :1;\r
+    IO_BYTE _MSS :1;\r
+    IO_BYTE _ACK :1;\r
+    IO_BYTE _GCAA :1;\r
+    IO_BYTE _INTE :1;\r
+    IO_BYTE _INT :1;\r
+  }bit;\r
+ }IBCR3STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _BB :1;\r
+    IO_BYTE _RSC :1;\r
+    IO_BYTE _AL :1;\r
+    IO_BYTE _LRB :1;\r
+    IO_BYTE _TRX :1;\r
+    IO_BYTE _AAS :1;\r
+    IO_BYTE _GCA :1;\r
+    IO_BYTE _ADT :1;\r
+  }bit;\r
+ }IBSR3STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD _TA9 :1;\r
+    IO_WORD _TA8 :1;\r
+    IO_WORD _TA7 :1;\r
+    IO_WORD _TA6 :1;\r
+    IO_WORD _TA5 :1;\r
+    IO_WORD _TA4 :1;\r
+    IO_WORD _TA3 :1;\r
+    IO_WORD _TA2 :1;\r
+    IO_WORD _TA1 :1;\r
+    IO_WORD _TA0 :1;\r
+  }bit;\r
+ }ITBA3STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _TA9 :1;\r
+    IO_BYTE _TA8 :1;\r
+  }bit;\r
+ }ITBAH3STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _TA7 :1;\r
+    IO_BYTE _TA6 :1;\r
+    IO_BYTE _TA5 :1;\r
+    IO_BYTE _TA4 :1;\r
+    IO_BYTE _TA3 :1;\r
+    IO_BYTE _TA2 :1;\r
+    IO_BYTE _TA1 :1;\r
+    IO_BYTE _TA0 :1;\r
+  }bit;\r
+ }ITBAL3STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _ENTB :1;\r
+    IO_WORD _RAL :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD _TM9 :1;\r
+    IO_WORD _TM8 :1;\r
+    IO_WORD _TM7 :1;\r
+    IO_WORD _TM6 :1;\r
+    IO_WORD _TM5 :1;\r
+    IO_WORD _TM4 :1;\r
+    IO_WORD _TM3 :1;\r
+    IO_WORD _TM2 :1;\r
+    IO_WORD _TM1 :1;\r
+    IO_WORD _TM0 :1;\r
+  }bit;\r
+ }ITMK3STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _ENTB :1;\r
+    IO_BYTE _RAL :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _TM9 :1;\r
+    IO_BYTE _TM8 :1;\r
+  }bit;\r
+ }ITMKH3STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _TM7 :1;\r
+    IO_BYTE _TM6 :1;\r
+    IO_BYTE _TM5 :1;\r
+    IO_BYTE _TM4 :1;\r
+    IO_BYTE _TM3 :1;\r
+    IO_BYTE _TM2 :1;\r
+    IO_BYTE _TM1 :1;\r
+    IO_BYTE _TM0 :1;\r
+  }bit;\r
+ }ITMKL3STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _ENSB :1;\r
+    IO_BYTE _SM6 :1;\r
+    IO_BYTE _SM5 :1;\r
+    IO_BYTE _SM4 :1;\r
+    IO_BYTE _SM3 :1;\r
+    IO_BYTE _SM2 :1;\r
+    IO_BYTE _SM1 :1;\r
+    IO_BYTE _SM0 :1;\r
+  }bit;\r
+ }ISMK3STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE _SA6 :1;\r
+    IO_BYTE _SA5 :1;\r
+    IO_BYTE _SA4 :1;\r
+    IO_BYTE _SA3 :1;\r
+    IO_BYTE _SA2 :1;\r
+    IO_BYTE _SA1 :1;\r
+    IO_BYTE _SA0 :1;\r
+  }bit;\r
+ }ISBA3STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }IDAR3STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE _NSF :1;\r
+    IO_BYTE _EN :1;\r
+    IO_BYTE _CS4 :1;\r
+    IO_BYTE _CS3 :1;\r
+    IO_BYTE _CS2 :1;\r
+    IO_BYTE _CS1 :1;\r
+    IO_BYTE _CS0 :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE _CS :5;\r
+  }bitc;\r
+ }ICCR3STR;\r
+typedef union{   /* ROM Select Register */\r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _D15 :1;\r
+    IO_WORD _D14 :1;\r
+    IO_WORD _D13 :1;\r
+    IO_WORD _D12 :1;\r
+    IO_WORD _D11 :1;\r
+    IO_WORD _D10 :1;\r
+    IO_WORD _D9 :1;\r
+    IO_WORD _D8 :1;\r
+    IO_WORD _D7 :1;\r
+    IO_WORD _D6 :1;\r
+    IO_WORD _D5 :1;\r
+    IO_WORD _D4 :1;\r
+    IO_WORD _D3 :1;\r
+    IO_WORD _D2 :1;\r
+    IO_WORD _D1 :1;\r
+    IO_WORD _D0 :1;\r
+  }bit;\r
+ }ROMSSTR;\r
+typedef union{   /* Interrupt Control Unit */\r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _ICR4 :1;\r
+    IO_BYTE _ICR3 :1;\r
+    IO_BYTE _ICR2 :1;\r
+    IO_BYTE _ICR1 :1;\r
+    IO_BYTE _ICR0 :1;\r
+  }bit;\r
+ }ICR00STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _ICR4 :1;\r
+    IO_BYTE _ICR3 :1;\r
+    IO_BYTE _ICR2 :1;\r
+    IO_BYTE _ICR1 :1;\r
+    IO_BYTE _ICR0 :1;\r
+  }bit;\r
+ }ICR01STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _ICR4 :1;\r
+    IO_BYTE _ICR3 :1;\r
+    IO_BYTE _ICR2 :1;\r
+    IO_BYTE _ICR1 :1;\r
+    IO_BYTE _ICR0 :1;\r
+  }bit;\r
+ }ICR02STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _ICR4 :1;\r
+    IO_BYTE _ICR3 :1;\r
+    IO_BYTE _ICR2 :1;\r
+    IO_BYTE _ICR1 :1;\r
+    IO_BYTE _ICR0 :1;\r
+  }bit;\r
+ }ICR03STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _ICR4 :1;\r
+    IO_BYTE _ICR3 :1;\r
+    IO_BYTE _ICR2 :1;\r
+    IO_BYTE _ICR1 :1;\r
+    IO_BYTE _ICR0 :1;\r
+  }bit;\r
+ }ICR04STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _ICR4 :1;\r
+    IO_BYTE _ICR3 :1;\r
+    IO_BYTE _ICR2 :1;\r
+    IO_BYTE _ICR1 :1;\r
+    IO_BYTE _ICR0 :1;\r
+  }bit;\r
+ }ICR05STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _ICR4 :1;\r
+    IO_BYTE _ICR3 :1;\r
+    IO_BYTE _ICR2 :1;\r
+    IO_BYTE _ICR1 :1;\r
+    IO_BYTE _ICR0 :1;\r
+  }bit;\r
+ }ICR06STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _ICR4 :1;\r
+    IO_BYTE _ICR3 :1;\r
+    IO_BYTE _ICR2 :1;\r
+    IO_BYTE _ICR1 :1;\r
+    IO_BYTE _ICR0 :1;\r
+  }bit;\r
+ }ICR07STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _ICR4 :1;\r
+    IO_BYTE _ICR3 :1;\r
+    IO_BYTE _ICR2 :1;\r
+    IO_BYTE _ICR1 :1;\r
+    IO_BYTE _ICR0 :1;\r
+  }bit;\r
+ }ICR08STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _ICR4 :1;\r
+    IO_BYTE _ICR3 :1;\r
+    IO_BYTE _ICR2 :1;\r
+    IO_BYTE _ICR1 :1;\r
+    IO_BYTE _ICR0 :1;\r
+  }bit;\r
+ }ICR09STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _ICR4 :1;\r
+    IO_BYTE _ICR3 :1;\r
+    IO_BYTE _ICR2 :1;\r
+    IO_BYTE _ICR1 :1;\r
+    IO_BYTE _ICR0 :1;\r
+  }bit;\r
+ }ICR10STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _ICR4 :1;\r
+    IO_BYTE _ICR3 :1;\r
+    IO_BYTE _ICR2 :1;\r
+    IO_BYTE _ICR1 :1;\r
+    IO_BYTE _ICR0 :1;\r
+  }bit;\r
+ }ICR11STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _ICR4 :1;\r
+    IO_BYTE _ICR3 :1;\r
+    IO_BYTE _ICR2 :1;\r
+    IO_BYTE _ICR1 :1;\r
+    IO_BYTE _ICR0 :1;\r
+  }bit;\r
+ }ICR12STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _ICR4 :1;\r
+    IO_BYTE _ICR3 :1;\r
+    IO_BYTE _ICR2 :1;\r
+    IO_BYTE _ICR1 :1;\r
+    IO_BYTE _ICR0 :1;\r
+  }bit;\r
+ }ICR13STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _ICR4 :1;\r
+    IO_BYTE _ICR3 :1;\r
+    IO_BYTE _ICR2 :1;\r
+    IO_BYTE _ICR1 :1;\r
+    IO_BYTE _ICR0 :1;\r
+  }bit;\r
+ }ICR14STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _ICR4 :1;\r
+    IO_BYTE _ICR3 :1;\r
+    IO_BYTE _ICR2 :1;\r
+    IO_BYTE _ICR1 :1;\r
+    IO_BYTE _ICR0 :1;\r
+  }bit;\r
+ }ICR15STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _ICR4 :1;\r
+    IO_BYTE _ICR3 :1;\r
+    IO_BYTE _ICR2 :1;\r
+    IO_BYTE _ICR1 :1;\r
+    IO_BYTE _ICR0 :1;\r
+  }bit;\r
+ }ICR16STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _ICR4 :1;\r
+    IO_BYTE _ICR3 :1;\r
+    IO_BYTE _ICR2 :1;\r
+    IO_BYTE _ICR1 :1;\r
+    IO_BYTE _ICR0 :1;\r
+  }bit;\r
+ }ICR17STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _ICR4 :1;\r
+    IO_BYTE _ICR3 :1;\r
+    IO_BYTE _ICR2 :1;\r
+    IO_BYTE _ICR1 :1;\r
+    IO_BYTE _ICR0 :1;\r
+  }bit;\r
+ }ICR18STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _ICR4 :1;\r
+    IO_BYTE _ICR3 :1;\r
+    IO_BYTE _ICR2 :1;\r
+    IO_BYTE _ICR1 :1;\r
+    IO_BYTE _ICR0 :1;\r
+  }bit;\r
+ }ICR19STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _ICR4 :1;\r
+    IO_BYTE _ICR3 :1;\r
+    IO_BYTE _ICR2 :1;\r
+    IO_BYTE _ICR1 :1;\r
+    IO_BYTE _ICR0 :1;\r
+  }bit;\r
+ }ICR20STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _ICR4 :1;\r
+    IO_BYTE _ICR3 :1;\r
+    IO_BYTE _ICR2 :1;\r
+    IO_BYTE _ICR1 :1;\r
+    IO_BYTE _ICR0 :1;\r
+  }bit;\r
+ }ICR21STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _ICR4 :1;\r
+    IO_BYTE _ICR3 :1;\r
+    IO_BYTE _ICR2 :1;\r
+    IO_BYTE _ICR1 :1;\r
+    IO_BYTE _ICR0 :1;\r
+  }bit;\r
+ }ICR22STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _ICR4 :1;\r
+    IO_BYTE _ICR3 :1;\r
+    IO_BYTE _ICR2 :1;\r
+    IO_BYTE _ICR1 :1;\r
+    IO_BYTE _ICR0 :1;\r
+  }bit;\r
+ }ICR23STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _ICR4 :1;\r
+    IO_BYTE _ICR3 :1;\r
+    IO_BYTE _ICR2 :1;\r
+    IO_BYTE _ICR1 :1;\r
+    IO_BYTE _ICR0 :1;\r
+  }bit;\r
+ }ICR24STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _ICR4 :1;\r
+    IO_BYTE _ICR3 :1;\r
+    IO_BYTE _ICR2 :1;\r
+    IO_BYTE _ICR1 :1;\r
+    IO_BYTE _ICR0 :1;\r
+  }bit;\r
+ }ICR25STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _ICR4 :1;\r
+    IO_BYTE _ICR3 :1;\r
+    IO_BYTE _ICR2 :1;\r
+    IO_BYTE _ICR1 :1;\r
+    IO_BYTE _ICR0 :1;\r
+  }bit;\r
+ }ICR26STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _ICR4 :1;\r
+    IO_BYTE _ICR3 :1;\r
+    IO_BYTE _ICR2 :1;\r
+    IO_BYTE _ICR1 :1;\r
+    IO_BYTE _ICR0 :1;\r
+  }bit;\r
+ }ICR27STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _ICR4 :1;\r
+    IO_BYTE _ICR3 :1;\r
+    IO_BYTE _ICR2 :1;\r
+    IO_BYTE _ICR1 :1;\r
+    IO_BYTE _ICR0 :1;\r
+  }bit;\r
+ }ICR28STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _ICR4 :1;\r
+    IO_BYTE _ICR3 :1;\r
+    IO_BYTE _ICR2 :1;\r
+    IO_BYTE _ICR1 :1;\r
+    IO_BYTE _ICR0 :1;\r
+  }bit;\r
+ }ICR29STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _ICR4 :1;\r
+    IO_BYTE _ICR3 :1;\r
+    IO_BYTE _ICR2 :1;\r
+    IO_BYTE _ICR1 :1;\r
+    IO_BYTE _ICR0 :1;\r
+  }bit;\r
+ }ICR30STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _ICR4 :1;\r
+    IO_BYTE _ICR3 :1;\r
+    IO_BYTE _ICR2 :1;\r
+    IO_BYTE _ICR1 :1;\r
+    IO_BYTE _ICR0 :1;\r
+  }bit;\r
+ }ICR31STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _ICR4 :1;\r
+    IO_BYTE _ICR3 :1;\r
+    IO_BYTE _ICR2 :1;\r
+    IO_BYTE _ICR1 :1;\r
+    IO_BYTE _ICR0 :1;\r
+  }bit;\r
+ }ICR32STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _ICR4 :1;\r
+    IO_BYTE _ICR3 :1;\r
+    IO_BYTE _ICR2 :1;\r
+    IO_BYTE _ICR1 :1;\r
+    IO_BYTE _ICR0 :1;\r
+  }bit;\r
+ }ICR33STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _ICR4 :1;\r
+    IO_BYTE _ICR3 :1;\r
+    IO_BYTE _ICR2 :1;\r
+    IO_BYTE _ICR1 :1;\r
+    IO_BYTE _ICR0 :1;\r
+  }bit;\r
+ }ICR34STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _ICR4 :1;\r
+    IO_BYTE _ICR3 :1;\r
+    IO_BYTE _ICR2 :1;\r
+    IO_BYTE _ICR1 :1;\r
+    IO_BYTE _ICR0 :1;\r
+  }bit;\r
+ }ICR35STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _ICR4 :1;\r
+    IO_BYTE _ICR3 :1;\r
+    IO_BYTE _ICR2 :1;\r
+    IO_BYTE _ICR1 :1;\r
+    IO_BYTE _ICR0 :1;\r
+  }bit;\r
+ }ICR36STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _ICR4 :1;\r
+    IO_BYTE _ICR3 :1;\r
+    IO_BYTE _ICR2 :1;\r
+    IO_BYTE _ICR1 :1;\r
+    IO_BYTE _ICR0 :1;\r
+  }bit;\r
+ }ICR37STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _ICR4 :1;\r
+    IO_BYTE _ICR3 :1;\r
+    IO_BYTE _ICR2 :1;\r
+    IO_BYTE _ICR1 :1;\r
+    IO_BYTE _ICR0 :1;\r
+  }bit;\r
+ }ICR38STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _ICR4 :1;\r
+    IO_BYTE _ICR3 :1;\r
+    IO_BYTE _ICR2 :1;\r
+    IO_BYTE _ICR1 :1;\r
+    IO_BYTE _ICR0 :1;\r
+  }bit;\r
+ }ICR39STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _ICR4 :1;\r
+    IO_BYTE _ICR3 :1;\r
+    IO_BYTE _ICR2 :1;\r
+    IO_BYTE _ICR1 :1;\r
+    IO_BYTE _ICR0 :1;\r
+  }bit;\r
+ }ICR40STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _ICR4 :1;\r
+    IO_BYTE _ICR3 :1;\r
+    IO_BYTE _ICR2 :1;\r
+    IO_BYTE _ICR1 :1;\r
+    IO_BYTE _ICR0 :1;\r
+  }bit;\r
+ }ICR41STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _ICR4 :1;\r
+    IO_BYTE _ICR3 :1;\r
+    IO_BYTE _ICR2 :1;\r
+    IO_BYTE _ICR1 :1;\r
+    IO_BYTE _ICR0 :1;\r
+  }bit;\r
+ }ICR42STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _ICR4 :1;\r
+    IO_BYTE _ICR3 :1;\r
+    IO_BYTE _ICR2 :1;\r
+    IO_BYTE _ICR1 :1;\r
+    IO_BYTE _ICR0 :1;\r
+  }bit;\r
+ }ICR43STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _ICR4 :1;\r
+    IO_BYTE _ICR3 :1;\r
+    IO_BYTE _ICR2 :1;\r
+    IO_BYTE _ICR1 :1;\r
+    IO_BYTE _ICR0 :1;\r
+  }bit;\r
+ }ICR44STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _ICR4 :1;\r
+    IO_BYTE _ICR3 :1;\r
+    IO_BYTE _ICR2 :1;\r
+    IO_BYTE _ICR1 :1;\r
+    IO_BYTE _ICR0 :1;\r
+  }bit;\r
+ }ICR45STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _ICR4 :1;\r
+    IO_BYTE _ICR3 :1;\r
+    IO_BYTE _ICR2 :1;\r
+    IO_BYTE _ICR1 :1;\r
+    IO_BYTE _ICR0 :1;\r
+  }bit;\r
+ }ICR46STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _ICR4 :1;\r
+    IO_BYTE _ICR3 :1;\r
+    IO_BYTE _ICR2 :1;\r
+    IO_BYTE _ICR1 :1;\r
+    IO_BYTE _ICR0 :1;\r
+  }bit;\r
+ }ICR47STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _ICR4 :1;\r
+    IO_BYTE _ICR3 :1;\r
+    IO_BYTE _ICR2 :1;\r
+    IO_BYTE _ICR1 :1;\r
+    IO_BYTE _ICR0 :1;\r
+  }bit;\r
+ }ICR48STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _ICR4 :1;\r
+    IO_BYTE _ICR3 :1;\r
+    IO_BYTE _ICR2 :1;\r
+    IO_BYTE _ICR1 :1;\r
+    IO_BYTE _ICR0 :1;\r
+  }bit;\r
+ }ICR49STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _ICR4 :1;\r
+    IO_BYTE _ICR3 :1;\r
+    IO_BYTE _ICR2 :1;\r
+    IO_BYTE _ICR1 :1;\r
+    IO_BYTE _ICR0 :1;\r
+  }bit;\r
+ }ICR50STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _ICR4 :1;\r
+    IO_BYTE _ICR3 :1;\r
+    IO_BYTE _ICR2 :1;\r
+    IO_BYTE _ICR1 :1;\r
+    IO_BYTE _ICR0 :1;\r
+  }bit;\r
+ }ICR51STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _ICR4 :1;\r
+    IO_BYTE _ICR3 :1;\r
+    IO_BYTE _ICR2 :1;\r
+    IO_BYTE _ICR1 :1;\r
+    IO_BYTE _ICR0 :1;\r
+  }bit;\r
+ }ICR52STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _ICR4 :1;\r
+    IO_BYTE _ICR3 :1;\r
+    IO_BYTE _ICR2 :1;\r
+    IO_BYTE _ICR1 :1;\r
+    IO_BYTE _ICR0 :1;\r
+  }bit;\r
+ }ICR53STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _ICR4 :1;\r
+    IO_BYTE _ICR3 :1;\r
+    IO_BYTE _ICR2 :1;\r
+    IO_BYTE _ICR1 :1;\r
+    IO_BYTE _ICR0 :1;\r
+  }bit;\r
+ }ICR54STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _ICR4 :1;\r
+    IO_BYTE _ICR3 :1;\r
+    IO_BYTE _ICR2 :1;\r
+    IO_BYTE _ICR1 :1;\r
+    IO_BYTE _ICR0 :1;\r
+  }bit;\r
+ }ICR55STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _ICR4 :1;\r
+    IO_BYTE _ICR3 :1;\r
+    IO_BYTE _ICR2 :1;\r
+    IO_BYTE _ICR1 :1;\r
+    IO_BYTE _ICR0 :1;\r
+  }bit;\r
+ }ICR56STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _ICR4 :1;\r
+    IO_BYTE _ICR3 :1;\r
+    IO_BYTE _ICR2 :1;\r
+    IO_BYTE _ICR1 :1;\r
+    IO_BYTE _ICR0 :1;\r
+  }bit;\r
+ }ICR57STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _ICR4 :1;\r
+    IO_BYTE _ICR3 :1;\r
+    IO_BYTE _ICR2 :1;\r
+    IO_BYTE _ICR1 :1;\r
+    IO_BYTE _ICR0 :1;\r
+  }bit;\r
+ }ICR58STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _ICR4 :1;\r
+    IO_BYTE _ICR3 :1;\r
+    IO_BYTE _ICR2 :1;\r
+    IO_BYTE _ICR1 :1;\r
+    IO_BYTE _ICR0 :1;\r
+  }bit;\r
+ }ICR59STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _ICR4 :1;\r
+    IO_BYTE _ICR3 :1;\r
+    IO_BYTE _ICR2 :1;\r
+    IO_BYTE _ICR1 :1;\r
+    IO_BYTE _ICR0 :1;\r
+  }bit;\r
+ }ICR60STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _ICR4 :1;\r
+    IO_BYTE _ICR3 :1;\r
+    IO_BYTE _ICR2 :1;\r
+    IO_BYTE _ICR1 :1;\r
+    IO_BYTE _ICR0 :1;\r
+  }bit;\r
+ }ICR61STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _ICR4 :1;\r
+    IO_BYTE _ICR3 :1;\r
+    IO_BYTE _ICR2 :1;\r
+    IO_BYTE _ICR1 :1;\r
+    IO_BYTE _ICR0 :1;\r
+  }bit;\r
+ }ICR62STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _ICR4 :1;\r
+    IO_BYTE _ICR3 :1;\r
+    IO_BYTE _ICR2 :1;\r
+    IO_BYTE _ICR1 :1;\r
+    IO_BYTE _ICR0 :1;\r
+  }bit;\r
+ }ICR63STR;\r
+typedef union{   /* Clock Control Unit */\r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _INIT :1;\r
+    IO_BYTE _HSTB :1;\r
+    IO_BYTE _WDOG :1;\r
+    IO_BYTE _ERST :1;\r
+    IO_BYTE _SRST :1;\r
+    IO_BYTE _LINIT :1;\r
+    IO_BYTE _WT1 :1;\r
+    IO_BYTE _WT0 :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE _WT :2;\r
+  }bitc;\r
+ }RSRRSTR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _STOP :1;\r
+    IO_BYTE _SLEEP :1;\r
+    IO_BYTE _HIZ :1;\r
+    IO_BYTE _SRST :1;\r
+    IO_BYTE _OS1 :1;\r
+    IO_BYTE _OS0 :1;\r
+    IO_BYTE _OSCD2 :1;\r
+    IO_BYTE _OSCD1 :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE _OS :2;\r
+    IO_BYTE _OSCD :2;\r
+  }bitc;\r
+ }STCRSTR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _TBIF :1;\r
+    IO_BYTE _TBIE :1;\r
+    IO_BYTE _TBC2 :1;\r
+    IO_BYTE _TBC1 :1;\r
+    IO_BYTE _TBC0 :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _SYNCR :1;\r
+    IO_BYTE _SYNCS :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE _TBC :3;\r
+  }bitc;\r
+ }TBCRSTR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }CTBRSTR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _SCKEN :1;\r
+    IO_BYTE _PLL1EN :1;\r
+    IO_BYTE _CLKS1 :1;\r
+    IO_BYTE _CLKS0 :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE _CLKS :2;\r
+  }bitc;\r
+ }CLKRSTR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }WPRSTR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _B3 :1;\r
+    IO_BYTE _B2 :1;\r
+    IO_BYTE _B1 :1;\r
+    IO_BYTE _B0 :1;\r
+    IO_BYTE _P3 :1;\r
+    IO_BYTE _P2 :1;\r
+    IO_BYTE _P1 :1;\r
+    IO_BYTE _P0 :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE _B :4;\r
+    IO_BYTE _P :4;\r
+  }bitc;\r
+ }DIVR0STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _T3 :1;\r
+    IO_BYTE _T2 :1;\r
+    IO_BYTE _T1 :1;\r
+    IO_BYTE _T0 :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE _T :4;\r
+  }bitc;\r
+ }DIVR1STR;\r
+typedef union{   /* PLL - Clock Gear Unit: */\r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _DVM3 :1;\r
+    IO_BYTE _DVM2 :1;\r
+    IO_BYTE _DVM1 :1;\r
+    IO_BYTE _DVM0 :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE _DVM :4;\r
+  }bitc;\r
+ }PLLDIVMSTR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _DVN5 :1;\r
+    IO_BYTE _DVN4 :1;\r
+    IO_BYTE _DVN3 :1;\r
+    IO_BYTE _DVN2 :1;\r
+    IO_BYTE _DVN1 :1;\r
+    IO_BYTE _DVN0 :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE _DVN :6;\r
+  }bitc;\r
+ }PLLDIVNSTR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _DVG3 :1;\r
+    IO_BYTE _DVG2 :1;\r
+    IO_BYTE _DVG1 :1;\r
+    IO_BYTE _DVG0 :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE _DVG :4;\r
+  }bitc;\r
+ }PLLDIVGSTR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _MLG7 :1;\r
+    IO_BYTE _MLG6 :1;\r
+    IO_BYTE _MLG5 :1;\r
+    IO_BYTE _MLG4 :1;\r
+    IO_BYTE _MLG3 :1;\r
+    IO_BYTE _MLG2 :1;\r
+    IO_BYTE _MLG1 :1;\r
+    IO_BYTE _MLG0 :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE _MLG :8;\r
+  }bitc;\r
+ }PLLMULGSTR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _IEDN :1;\r
+    IO_BYTE _GRDN :1;\r
+    IO_BYTE _IEUP :1;\r
+    IO_BYTE _GRUP :1;\r
+  }bit;\r
+ }PLLCTRLSTR;\r
+typedef union{   /* Main/Sub Oscillator Control */\r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _FCI :1;\r
+    IO_BYTE _RFBEN :1;\r
+    IO_BYTE _OSCR :1;\r
+  }bit;\r
+ }OSCC1STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _OSCS7 :1;\r
+    IO_BYTE _OSCS6 :1;\r
+    IO_BYTE _OSCS5 :1;\r
+    IO_BYTE _OSCS4 :1;\r
+    IO_BYTE _OSCS3 :1;\r
+    IO_BYTE _OSCS2 :1;\r
+    IO_BYTE _OSCS1 :1;\r
+    IO_BYTE _OSCS0 :1;\r
+  }bit;\r
+ }OSCS1STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _FCI :1;\r
+    IO_BYTE _RFBEN :1;\r
+    IO_BYTE _OSCR :1;\r
+  }bit;\r
+ }OSCC2STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _OSCS7 :1;\r
+    IO_BYTE _OSCS6 :1;\r
+    IO_BYTE _OSCS5 :1;\r
+    IO_BYTE _OSCS4 :1;\r
+    IO_BYTE _OSCS3 :1;\r
+    IO_BYTE _OSCS2 :1;\r
+    IO_BYTE _OSCS1 :1;\r
+    IO_BYTE _OSCS0 :1;\r
+  }bit;\r
+ }OSCS2STR;\r
+typedef union{   /* Port Input Enable Control */\r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _CPORTEN :1;\r
+    IO_BYTE _GPORTEN :1;\r
+  }bit;\r
+ }PORTENSTR;\r
+typedef union{   /* Real Time Clock (Watch Timer) */\r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _INTE4 :1;\r
+    IO_BYTE _INT4 :1;\r
+  }bit;\r
+ }WTCERSTR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _INTE3 :1;\r
+    IO_WORD _INT3 :1;\r
+    IO_WORD _INTE2 :1;\r
+    IO_WORD _INT2 :1;\r
+    IO_WORD _INTE1 :1;\r
+    IO_WORD _INT1 :1;\r
+    IO_WORD _INTE0 :1;\r
+    IO_WORD _INT0 :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD _RUN :1;\r
+    IO_WORD _UPDT :1;\r
+    IO_WORD  :1;\r
+    IO_WORD _ST :1;\r
+  }bit;\r
+ }WTCRSTR;\r
+typedef union{  \r
+    IO_LWORD   lword;\r
+    struct{   \r
+    IO_LWORD  :1;\r
+    IO_LWORD  :1;\r
+    IO_LWORD  :1;\r
+    IO_LWORD  :1;\r
+    IO_LWORD  :1;\r
+    IO_LWORD  :1;\r
+    IO_LWORD  :1;\r
+    IO_LWORD  :1;\r
+    IO_LWORD  :1;\r
+    IO_LWORD  :1;\r
+    IO_LWORD  :1;\r
+    IO_LWORD _D20 :1;\r
+    IO_LWORD _D19 :1;\r
+    IO_LWORD _D18 :1;\r
+    IO_LWORD _D17 :1;\r
+    IO_LWORD _D16 :1;\r
+    IO_LWORD _D15 :1;\r
+    IO_LWORD _D14 :1;\r
+    IO_LWORD _D13 :1;\r
+    IO_LWORD _D12 :1;\r
+    IO_LWORD _D11 :1;\r
+    IO_LWORD _D10 :1;\r
+    IO_LWORD _D9 :1;\r
+    IO_LWORD _D8 :1;\r
+    IO_LWORD _D7 :1;\r
+    IO_LWORD _D6 :1;\r
+    IO_LWORD _D5 :1;\r
+    IO_LWORD _D4 :1;\r
+    IO_LWORD _D3 :1;\r
+    IO_LWORD _D2 :1;\r
+    IO_LWORD _D1 :1;\r
+    IO_LWORD _D0 :1;\r
+  }bit;\r
+ }WTBRSTR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _H4 :1;\r
+    IO_BYTE _H3 :1;\r
+    IO_BYTE _H2 :1;\r
+    IO_BYTE _H1 :1;\r
+    IO_BYTE _H0 :1;\r
+  }bit;\r
+ }WTHRSTR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _M5 :1;\r
+    IO_BYTE _M4 :1;\r
+    IO_BYTE _M3 :1;\r
+    IO_BYTE _M2 :1;\r
+    IO_BYTE _M1 :1;\r
+    IO_BYTE _M0 :1;\r
+  }bit;\r
+ }WTMRSTR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _S5 :1;\r
+    IO_BYTE _S4 :1;\r
+    IO_BYTE _S3 :1;\r
+    IO_BYTE _S2 :1;\r
+    IO_BYTE _S1 :1;\r
+    IO_BYTE _S0 :1;\r
+  }bit;\r
+ }WTSRSTR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _SCKS :1;\r
+    IO_BYTE _MM :1;\r
+    IO_BYTE _SM :1;\r
+    IO_BYTE _RCE :1;\r
+    IO_BYTE _MSVE :1;\r
+    IO_BYTE _SSVE :1;\r
+    IO_BYTE _SRST :1;\r
+    IO_BYTE _OUTE :1;\r
+  }bit;\r
+ }CSVCRSTR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _EDSUEN :1;\r
+    IO_BYTE _PLLLOCK :1;\r
+    IO_BYTE _RCSEL :1;\r
+    IO_BYTE _MONCKI :1;\r
+    IO_BYTE _CSC3 :1;\r
+    IO_BYTE _CSC2 :1;\r
+    IO_BYTE _CSC1 :1;\r
+    IO_BYTE _CSC0 :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE :4;\r
+    IO_BYTE _CSC :4;\r
+  }bitc;\r
+ }CSCFGSTR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _CMPRE3 :1;\r
+    IO_BYTE _CMPRE2 :1;\r
+    IO_BYTE _CMPRE1 :1;\r
+    IO_BYTE _CMPRE0 :1;\r
+    IO_BYTE _CMSEL3 :1;\r
+    IO_BYTE _CMSEL2 :1;\r
+    IO_BYTE _CMSEL1 :1;\r
+    IO_BYTE _CMSEL0 :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE _CMPRE :4;\r
+    IO_BYTE _CMSEL :4;\r
+  }bitc;\r
+ }CMCFGSTR;\r
+typedef union{   /* Calibration Unit of Sub Oszillation */\r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD _STRT :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD _INT :1;\r
+    IO_WORD _INTEN :1;\r
+  }bit;\r
+ }CUCRSTR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _TDD15 :1;\r
+    IO_WORD _TDD14 :1;\r
+    IO_WORD _TDD13 :1;\r
+    IO_WORD _TDD12 :1;\r
+    IO_WORD _TDD11 :1;\r
+    IO_WORD _TDD10 :1;\r
+    IO_WORD _TDD9 :1;\r
+    IO_WORD _TDD8 :1;\r
+    IO_WORD _TDD7 :1;\r
+    IO_WORD _TDD6 :1;\r
+    IO_WORD _TDD5 :1;\r
+    IO_WORD _TDD4 :1;\r
+    IO_WORD _TDD3 :1;\r
+    IO_WORD _TDD2 :1;\r
+    IO_WORD _TDD1 :1;\r
+    IO_WORD _TDD0 :1;\r
+  }bit;\r
+ }CUTDSTR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD _TDR23 :1;\r
+    IO_WORD _TDR22 :1;\r
+    IO_WORD _TDR21 :1;\r
+    IO_WORD _TDR20 :1;\r
+    IO_WORD _TDR19 :1;\r
+    IO_WORD _TDR18 :1;\r
+    IO_WORD _TDR17 :1;\r
+    IO_WORD _TDR16 :1;\r
+  }bit;\r
+ }CUTR1STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _TDR15 :1;\r
+    IO_WORD _TDR14 :1;\r
+    IO_WORD _TDR13 :1;\r
+    IO_WORD _TDR12 :1;\r
+    IO_WORD _TDR11 :1;\r
+    IO_WORD _TDR10 :1;\r
+    IO_WORD _TDR9 :1;\r
+    IO_WORD _TDR8 :1;\r
+    IO_WORD _TDR7 :1;\r
+    IO_WORD _TDR6 :1;\r
+    IO_WORD _TDR5 :1;\r
+    IO_WORD _TDR4 :1;\r
+    IO_WORD _TDR3 :1;\r
+    IO_WORD _TDR2 :1;\r
+    IO_WORD _TDR1 :1;\r
+    IO_WORD _TDR0 :1;\r
+  }bit;\r
+ }CUTR2STR;\r
+typedef union{   /* Clock Modulator */\r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD _MP13 :1;\r
+    IO_WORD _MP12 :1;\r
+    IO_WORD _MP11 :1;\r
+    IO_WORD _MP10 :1;\r
+    IO_WORD _MP9 :1;\r
+    IO_WORD _MP8 :1;\r
+    IO_WORD _MP7 :1;\r
+    IO_WORD _MP6 :1;\r
+    IO_WORD _MP5 :1;\r
+    IO_WORD _MP4 :1;\r
+    IO_WORD _MP3 :1;\r
+    IO_WORD _MP2 :1;\r
+    IO_WORD _MP1 :1;\r
+    IO_WORD _MP0 :1;\r
+  }bit;\r
+ }CMPRSTR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _FMODRUN :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _FMOD :1;\r
+    IO_BYTE _PDX :1;\r
+  }bit;\r
+ }CMCRSTR;\r
+typedef union{   /* CAN clock control */\r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _CPCKS1 :1;\r
+    IO_BYTE _CPCKS0 :1;\r
+    IO_BYTE _DVC3 :1;\r
+    IO_BYTE _DVC2 :1;\r
+    IO_BYTE _DVC1 :1;\r
+    IO_BYTE _DVC0 :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE :2;\r
+    IO_BYTE _CPCKS :2;\r
+    IO_BYTE _DVC :4;\r
+  }bitc;\r
+ }CANPRESTR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _CANCKD5 :1;\r
+    IO_BYTE _CANCKD4 :1;\r
+    IO_BYTE _CANCKD3 :1;\r
+    IO_BYTE _CANCKD2 :1;\r
+    IO_BYTE _CANCKD1 :1;\r
+    IO_BYTE _CANCKD0 :1;\r
+  }bit;\r
+ }CANCKDSTR;\r
+typedef union{   /* LV Detection / Hardware-Watchdog */\r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _LVESEL3 :1;\r
+    IO_BYTE _LVESEL2 :1;\r
+    IO_BYTE _LVESEL1 :1;\r
+    IO_BYTE _LVESEL0 :1;\r
+    IO_BYTE _LVISEL3 :1;\r
+    IO_BYTE _LVISEL2 :1;\r
+    IO_BYTE _LVISEL1 :1;\r
+    IO_BYTE _LVISEL0 :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE _LVESEL :4;\r
+    IO_BYTE _LVISEL :4;\r
+  }bitc;\r
+ }LVSELSTR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE _LVSEL :1;\r
+    IO_BYTE _LVEPD :1;\r
+    IO_BYTE _LVIPD :1;\r
+    IO_BYTE _LVREN :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _LVIEN :1;\r
+    IO_BYTE _LVIRQ :1;\r
+  }bit;\r
+ }LVDETSTR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _ED1 :1;\r
+    IO_BYTE _ED0 :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE _ED :2;\r
+  }bitc;\r
+ }HWWDESTR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _CL :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _CPUF :1;\r
+  }bit;\r
+ }HWWDSTR;\r
+typedef union{   /* Main-/Sub-Oscillatio Stabilization Timer */\r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _WIF :1;\r
+    IO_BYTE _WIE :1;\r
+    IO_BYTE _WEN :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _WS1 :1;\r
+    IO_BYTE _WS0 :1;\r
+    IO_BYTE _WCL :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE _WS :2;\r
+  }bitc;\r
+ }OSCRHSTR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _WIF :1;\r
+    IO_BYTE _WIE :1;\r
+    IO_BYTE _WEN :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _WS1 :1;\r
+    IO_BYTE _WS0 :1;\r
+    IO_BYTE _WCL :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE _WS :2;\r
+  }bitc;\r
+ }WPCRHSTR;\r
+typedef union{   /* Main-/Sub-Oscillatio Standby Control */\r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _OSCDS1 :1;\r
+  }bit;\r
+ }OSCCRSTR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _FLASHSEL :1;\r
+    IO_BYTE _MAINSEL :1;\r
+    IO_BYTE _SUBSEL3 :1;\r
+    IO_BYTE _SUBSEL2 :1;\r
+    IO_BYTE _SUBSEL1 :1;\r
+    IO_BYTE _SUBSEL0 :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE :4;\r
+    IO_BYTE _SUBSEL :4;\r
+  }bitc;\r
+ }REGSELSTR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _MSTBO :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _MAINKPEN :1;\r
+    IO_BYTE _MAINDSBL :1;\r
+  }bit;\r
+ }REGCTRSTR;\r
+typedef union{   /* External Bus/Chip Select Registers */\r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _A31 :1;\r
+    IO_WORD _A30 :1;\r
+    IO_WORD _A29 :1;\r
+    IO_WORD _A28 :1;\r
+    IO_WORD _A27 :1;\r
+    IO_WORD _A26 :1;\r
+    IO_WORD _A25 :1;\r
+    IO_WORD _A24 :1;\r
+    IO_WORD _A23 :1;\r
+    IO_WORD _A22 :1;\r
+    IO_WORD _A21 :1;\r
+    IO_WORD _A20 :1;\r
+    IO_WORD _A19 :1;\r
+    IO_WORD _A18 :1;\r
+    IO_WORD _A17 :1;\r
+    IO_WORD _A16 :1;\r
+  }bit;\r
+ }ASR0STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _ASZ3 :1;\r
+    IO_WORD _ASZ2 :1;\r
+    IO_WORD _ASZ1 :1;\r
+    IO_WORD _ASZ0 :1;\r
+    IO_WORD _DBW1 :1;\r
+    IO_WORD _DBW0 :1;\r
+    IO_WORD _BST1 :1;\r
+    IO_WORD _BST0 :1;\r
+    IO_WORD _SREN :1;\r
+    IO_WORD _PFEN :1;\r
+    IO_WORD _WREN :1;\r
+    IO_WORD  :1;\r
+    IO_WORD _TYP3 :1;\r
+    IO_WORD _TYP2 :1;\r
+    IO_WORD _TYP1 :1;\r
+    IO_WORD _TYP0 :1;\r
+  }bit;\r
+  struct{\r
+    IO_WORD _ASZ :4;\r
+    IO_WORD _DBW :2;\r
+    IO_WORD _BST :2;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD _TYP :4;\r
+  }bitc;\r
+ }ACR0STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _A31 :1;\r
+    IO_WORD _A30 :1;\r
+    IO_WORD _A29 :1;\r
+    IO_WORD _A28 :1;\r
+    IO_WORD _A27 :1;\r
+    IO_WORD _A26 :1;\r
+    IO_WORD _A25 :1;\r
+    IO_WORD _A24 :1;\r
+    IO_WORD _A23 :1;\r
+    IO_WORD _A22 :1;\r
+    IO_WORD _A21 :1;\r
+    IO_WORD _A20 :1;\r
+    IO_WORD _A19 :1;\r
+    IO_WORD _A18 :1;\r
+    IO_WORD _A17 :1;\r
+    IO_WORD _A16 :1;\r
+  }bit;\r
+ }ASR1STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _ASZ3 :1;\r
+    IO_WORD _ASZ2 :1;\r
+    IO_WORD _ASZ1 :1;\r
+    IO_WORD _ASZ0 :1;\r
+    IO_WORD _DBW1 :1;\r
+    IO_WORD _DBW0 :1;\r
+    IO_WORD _BST1 :1;\r
+    IO_WORD _BST0 :1;\r
+    IO_WORD _SREN :1;\r
+    IO_WORD _PFEN :1;\r
+    IO_WORD _WREN :1;\r
+    IO_WORD _LEND :1;\r
+    IO_WORD _TYP3 :1;\r
+    IO_WORD _TYP2 :1;\r
+    IO_WORD _TYP1 :1;\r
+    IO_WORD _TYP0 :1;\r
+  }bit;\r
+  struct{\r
+    IO_WORD _ASZ :4;\r
+    IO_WORD _DBW :2;\r
+    IO_WORD _BST :2;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD _TYP :4;\r
+  }bitc;\r
+ }ACR1STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _A31 :1;\r
+    IO_WORD _A30 :1;\r
+    IO_WORD _A29 :1;\r
+    IO_WORD _A28 :1;\r
+    IO_WORD _A27 :1;\r
+    IO_WORD _A26 :1;\r
+    IO_WORD _A25 :1;\r
+    IO_WORD _A24 :1;\r
+    IO_WORD _A23 :1;\r
+    IO_WORD _A22 :1;\r
+    IO_WORD _A21 :1;\r
+    IO_WORD _A20 :1;\r
+    IO_WORD _A19 :1;\r
+    IO_WORD _A18 :1;\r
+    IO_WORD _A17 :1;\r
+    IO_WORD _A16 :1;\r
+  }bit;\r
+ }ASR2STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _ASZ3 :1;\r
+    IO_WORD _ASZ2 :1;\r
+    IO_WORD _ASZ1 :1;\r
+    IO_WORD _ASZ0 :1;\r
+    IO_WORD _DBW1 :1;\r
+    IO_WORD _DBW0 :1;\r
+    IO_WORD _BST1 :1;\r
+    IO_WORD _BST0 :1;\r
+    IO_WORD _SREN :1;\r
+    IO_WORD _PFEN :1;\r
+    IO_WORD _WREN :1;\r
+    IO_WORD _LEND :1;\r
+    IO_WORD _TYP3 :1;\r
+    IO_WORD _TYP2 :1;\r
+    IO_WORD _TYP1 :1;\r
+    IO_WORD _TYP0 :1;\r
+  }bit;\r
+  struct{\r
+    IO_WORD _ASZ :4;\r
+    IO_WORD _DBW :2;\r
+    IO_WORD _BST :2;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD _TYP :4;\r
+  }bitc;\r
+ }ACR2STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _A31 :1;\r
+    IO_WORD _A30 :1;\r
+    IO_WORD _A29 :1;\r
+    IO_WORD _A28 :1;\r
+    IO_WORD _A27 :1;\r
+    IO_WORD _A26 :1;\r
+    IO_WORD _A25 :1;\r
+    IO_WORD _A24 :1;\r
+    IO_WORD _A23 :1;\r
+    IO_WORD _A22 :1;\r
+    IO_WORD _A21 :1;\r
+    IO_WORD _A20 :1;\r
+    IO_WORD _A19 :1;\r
+    IO_WORD _A18 :1;\r
+    IO_WORD _A17 :1;\r
+    IO_WORD _A16 :1;\r
+  }bit;\r
+ }ASR3STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _ASZ3 :1;\r
+    IO_WORD _ASZ2 :1;\r
+    IO_WORD _ASZ1 :1;\r
+    IO_WORD _ASZ0 :1;\r
+    IO_WORD _DBW1 :1;\r
+    IO_WORD _DBW0 :1;\r
+    IO_WORD _BST1 :1;\r
+    IO_WORD _BST0 :1;\r
+    IO_WORD _SREN :1;\r
+    IO_WORD _PFEN :1;\r
+    IO_WORD _WREN :1;\r
+    IO_WORD _LEND :1;\r
+    IO_WORD _TYP3 :1;\r
+    IO_WORD _TYP2 :1;\r
+    IO_WORD _TYP1 :1;\r
+    IO_WORD _TYP0 :1;\r
+  }bit;\r
+  struct{\r
+    IO_WORD _ASZ :4;\r
+    IO_WORD _DBW :2;\r
+    IO_WORD _BST :2;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD _TYP :4;\r
+  }bitc;\r
+ }ACR3STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _A31 :1;\r
+    IO_WORD _A30 :1;\r
+    IO_WORD _A29 :1;\r
+    IO_WORD _A28 :1;\r
+    IO_WORD _A27 :1;\r
+    IO_WORD _A26 :1;\r
+    IO_WORD _A25 :1;\r
+    IO_WORD _A24 :1;\r
+    IO_WORD _A23 :1;\r
+    IO_WORD _A22 :1;\r
+    IO_WORD _A21 :1;\r
+    IO_WORD _A20 :1;\r
+    IO_WORD _A19 :1;\r
+    IO_WORD _A18 :1;\r
+    IO_WORD _A17 :1;\r
+    IO_WORD _A16 :1;\r
+  }bit;\r
+ }ASR4STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _ASZ3 :1;\r
+    IO_WORD _ASZ2 :1;\r
+    IO_WORD _ASZ1 :1;\r
+    IO_WORD _ASZ0 :1;\r
+    IO_WORD _DBW1 :1;\r
+    IO_WORD _DBW0 :1;\r
+    IO_WORD _BST1 :1;\r
+    IO_WORD _BST0 :1;\r
+    IO_WORD _SREN :1;\r
+    IO_WORD _PFEN :1;\r
+    IO_WORD _WREN :1;\r
+    IO_WORD _LEND :1;\r
+    IO_WORD _TYP3 :1;\r
+    IO_WORD _TYP2 :1;\r
+    IO_WORD _TYP1 :1;\r
+    IO_WORD _TYP0 :1;\r
+  }bit;\r
+  struct{\r
+    IO_WORD _ASZ :4;\r
+    IO_WORD _DBW :2;\r
+    IO_WORD _BST :2;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD _TYP :4;\r
+  }bitc;\r
+ }ACR4STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _A31 :1;\r
+    IO_WORD _A30 :1;\r
+    IO_WORD _A29 :1;\r
+    IO_WORD _A28 :1;\r
+    IO_WORD _A27 :1;\r
+    IO_WORD _A26 :1;\r
+    IO_WORD _A25 :1;\r
+    IO_WORD _A24 :1;\r
+    IO_WORD _A23 :1;\r
+    IO_WORD _A22 :1;\r
+    IO_WORD _A21 :1;\r
+    IO_WORD _A20 :1;\r
+    IO_WORD _A19 :1;\r
+    IO_WORD _A18 :1;\r
+    IO_WORD _A17 :1;\r
+    IO_WORD _A16 :1;\r
+  }bit;\r
+ }ASR5STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _ASZ3 :1;\r
+    IO_WORD _ASZ2 :1;\r
+    IO_WORD _ASZ1 :1;\r
+    IO_WORD _ASZ0 :1;\r
+    IO_WORD _DBW1 :1;\r
+    IO_WORD _DBW0 :1;\r
+    IO_WORD _BST1 :1;\r
+    IO_WORD _BST0 :1;\r
+    IO_WORD _SREN :1;\r
+    IO_WORD _PFEN :1;\r
+    IO_WORD _WREN :1;\r
+    IO_WORD _LEND :1;\r
+    IO_WORD _TYP3 :1;\r
+    IO_WORD _TYP2 :1;\r
+    IO_WORD _TYP1 :1;\r
+    IO_WORD _TYP0 :1;\r
+  }bit;\r
+  struct{\r
+    IO_WORD _ASZ :4;\r
+    IO_WORD _DBW :2;\r
+    IO_WORD _BST :2;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD _TYP :4;\r
+  }bitc;\r
+ }ACR5STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _A31 :1;\r
+    IO_WORD _A30 :1;\r
+    IO_WORD _A29 :1;\r
+    IO_WORD _A28 :1;\r
+    IO_WORD _A27 :1;\r
+    IO_WORD _A26 :1;\r
+    IO_WORD _A25 :1;\r
+    IO_WORD _A24 :1;\r
+    IO_WORD _A23 :1;\r
+    IO_WORD _A22 :1;\r
+    IO_WORD _A21 :1;\r
+    IO_WORD _A20 :1;\r
+    IO_WORD _A19 :1;\r
+    IO_WORD _A18 :1;\r
+    IO_WORD _A17 :1;\r
+    IO_WORD _A16 :1;\r
+  }bit;\r
+ }ASR6STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _ASZ3 :1;\r
+    IO_WORD _ASZ2 :1;\r
+    IO_WORD _ASZ1 :1;\r
+    IO_WORD _ASZ0 :1;\r
+    IO_WORD _DBW1 :1;\r
+    IO_WORD _DBW0 :1;\r
+    IO_WORD _BST1 :1;\r
+    IO_WORD _BST0 :1;\r
+    IO_WORD _SREN :1;\r
+    IO_WORD _PFEN :1;\r
+    IO_WORD _WREN :1;\r
+    IO_WORD _LEND :1;\r
+    IO_WORD _TYP3 :1;\r
+    IO_WORD _TYP2 :1;\r
+    IO_WORD _TYP1 :1;\r
+    IO_WORD _TYP0 :1;\r
+  }bit;\r
+  struct{\r
+    IO_WORD _ASZ :4;\r
+    IO_WORD _DBW :2;\r
+    IO_WORD _BST :2;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD _TYP :4;\r
+  }bitc;\r
+ }ACR6STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _A31 :1;\r
+    IO_WORD _A30 :1;\r
+    IO_WORD _A29 :1;\r
+    IO_WORD _A28 :1;\r
+    IO_WORD _A27 :1;\r
+    IO_WORD _A26 :1;\r
+    IO_WORD _A25 :1;\r
+    IO_WORD _A24 :1;\r
+    IO_WORD _A23 :1;\r
+    IO_WORD _A22 :1;\r
+    IO_WORD _A21 :1;\r
+    IO_WORD _A20 :1;\r
+    IO_WORD _A19 :1;\r
+    IO_WORD _A18 :1;\r
+    IO_WORD _A17 :1;\r
+    IO_WORD _A16 :1;\r
+  }bit;\r
+ }ASR7STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _ASZ3 :1;\r
+    IO_WORD _ASZ2 :1;\r
+    IO_WORD _ASZ1 :1;\r
+    IO_WORD _ASZ0 :1;\r
+    IO_WORD _DBW1 :1;\r
+    IO_WORD _DBW0 :1;\r
+    IO_WORD _BST1 :1;\r
+    IO_WORD _BST0 :1;\r
+    IO_WORD _SREN :1;\r
+    IO_WORD _PFEN :1;\r
+    IO_WORD _WREN :1;\r
+    IO_WORD _LEND :1;\r
+    IO_WORD _TYP3 :1;\r
+    IO_WORD _TYP2 :1;\r
+    IO_WORD _TYP1 :1;\r
+    IO_WORD _TYP0 :1;\r
+  }bit;\r
+  struct{\r
+    IO_WORD _ASZ :4;\r
+    IO_WORD _DBW :2;\r
+    IO_WORD _BST :2;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD _TYP :4;\r
+  }bitc;\r
+ }ACR7STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _W15 :1;\r
+    IO_WORD _W14 :1;\r
+    IO_WORD _W13 :1;\r
+    IO_WORD _W12 :1;\r
+    IO_WORD _W11 :1;\r
+    IO_WORD _W10 :1;\r
+    IO_WORD _W9 :1;\r
+    IO_WORD _W8 :1;\r
+    IO_WORD _W7 :1;\r
+    IO_WORD _W6 :1;\r
+    IO_WORD _W5 :1;\r
+    IO_WORD _W4 :1;\r
+    IO_WORD _W3 :1;\r
+    IO_WORD _W2 :1;\r
+    IO_WORD _W1 :1;\r
+    IO_WORD _W0 :1;\r
+  }bit;\r
+ }AWR0STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _W15 :1;\r
+    IO_WORD _W14 :1;\r
+    IO_WORD _W13 :1;\r
+    IO_WORD _W12 :1;\r
+    IO_WORD _W11 :1;\r
+    IO_WORD _W10 :1;\r
+    IO_WORD _W9 :1;\r
+    IO_WORD _W8 :1;\r
+    IO_WORD _W7 :1;\r
+    IO_WORD _W6 :1;\r
+    IO_WORD _W5 :1;\r
+    IO_WORD _W4 :1;\r
+    IO_WORD _W3 :1;\r
+    IO_WORD _W2 :1;\r
+    IO_WORD _W1 :1;\r
+    IO_WORD _W0 :1;\r
+  }bit;\r
+ }AWR1STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _W15 :1;\r
+    IO_WORD _W14 :1;\r
+    IO_WORD _W13 :1;\r
+    IO_WORD _W12 :1;\r
+    IO_WORD _W11 :1;\r
+    IO_WORD _W10 :1;\r
+    IO_WORD _W9 :1;\r
+    IO_WORD _W8 :1;\r
+    IO_WORD _W7 :1;\r
+    IO_WORD _W6 :1;\r
+    IO_WORD _W5 :1;\r
+    IO_WORD _W4 :1;\r
+    IO_WORD _W3 :1;\r
+    IO_WORD _W2 :1;\r
+    IO_WORD _W1 :1;\r
+    IO_WORD _W0 :1;\r
+  }bit;\r
+ }AWR2STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _W15 :1;\r
+    IO_WORD _W14 :1;\r
+    IO_WORD _W13 :1;\r
+    IO_WORD _W12 :1;\r
+    IO_WORD _W11 :1;\r
+    IO_WORD _W10 :1;\r
+    IO_WORD _W9 :1;\r
+    IO_WORD _W8 :1;\r
+    IO_WORD _W7 :1;\r
+    IO_WORD _W6 :1;\r
+    IO_WORD _W5 :1;\r
+    IO_WORD _W4 :1;\r
+    IO_WORD _W3 :1;\r
+    IO_WORD _W2 :1;\r
+    IO_WORD _W1 :1;\r
+    IO_WORD _W0 :1;\r
+  }bit;\r
+ }AWR3STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _W15 :1;\r
+    IO_WORD _W14 :1;\r
+    IO_WORD _W13 :1;\r
+    IO_WORD _W12 :1;\r
+    IO_WORD _W11 :1;\r
+    IO_WORD _W10 :1;\r
+    IO_WORD _W9 :1;\r
+    IO_WORD _W8 :1;\r
+    IO_WORD _W7 :1;\r
+    IO_WORD _W6 :1;\r
+    IO_WORD _W5 :1;\r
+    IO_WORD _W4 :1;\r
+    IO_WORD _W3 :1;\r
+    IO_WORD _W2 :1;\r
+    IO_WORD _W1 :1;\r
+    IO_WORD _W0 :1;\r
+  }bit;\r
+ }AWR4STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _W15 :1;\r
+    IO_WORD _W14 :1;\r
+    IO_WORD _W13 :1;\r
+    IO_WORD _W12 :1;\r
+    IO_WORD _W11 :1;\r
+    IO_WORD _W10 :1;\r
+    IO_WORD _W9 :1;\r
+    IO_WORD _W8 :1;\r
+    IO_WORD _W7 :1;\r
+    IO_WORD _W6 :1;\r
+    IO_WORD _W5 :1;\r
+    IO_WORD _W4 :1;\r
+    IO_WORD _W3 :1;\r
+    IO_WORD _W2 :1;\r
+    IO_WORD _W1 :1;\r
+    IO_WORD _W0 :1;\r
+  }bit;\r
+ }AWR5STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _W15 :1;\r
+    IO_WORD _W14 :1;\r
+    IO_WORD _W13 :1;\r
+    IO_WORD _W12 :1;\r
+    IO_WORD _W11 :1;\r
+    IO_WORD _W10 :1;\r
+    IO_WORD _W9 :1;\r
+    IO_WORD _W8 :1;\r
+    IO_WORD _W7 :1;\r
+    IO_WORD _W6 :1;\r
+    IO_WORD _W5 :1;\r
+    IO_WORD _W4 :1;\r
+    IO_WORD _W3 :1;\r
+    IO_WORD _W2 :1;\r
+    IO_WORD _W1 :1;\r
+    IO_WORD _W0 :1;\r
+  }bit;\r
+ }AWR6STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _W15 :1;\r
+    IO_WORD _W14 :1;\r
+    IO_WORD _W13 :1;\r
+    IO_WORD _W12 :1;\r
+    IO_WORD _W11 :1;\r
+    IO_WORD _W10 :1;\r
+    IO_WORD _W9 :1;\r
+    IO_WORD _W8 :1;\r
+    IO_WORD _W7 :1;\r
+    IO_WORD _W6 :1;\r
+    IO_WORD _W5 :1;\r
+    IO_WORD _W4 :1;\r
+    IO_WORD _W3 :1;\r
+    IO_WORD _W2 :1;\r
+    IO_WORD _W1 :1;\r
+    IO_WORD _W0 :1;\r
+  }bit;\r
+ }AWR7STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE _PSZ2 :1;\r
+    IO_BYTE _PSZ1 :1;\r
+    IO_BYTE _PSZ0 :1;\r
+    IO_BYTE _WBST :1;\r
+    IO_BYTE _BANK :1;\r
+    IO_BYTE _ABS1 :1;\r
+    IO_BYTE _ABS0 :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE :1;\r
+    IO_BYTE _PSZ :3;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE _ABS :2;\r
+  }bitc;\r
+ }MCRASTR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE _PSZ2 :1;\r
+    IO_BYTE _PSZ1 :1;\r
+    IO_BYTE _PSZ0 :1;\r
+    IO_BYTE _WBST :1;\r
+    IO_BYTE _BANK :1;\r
+    IO_BYTE _ABS1 :1;\r
+    IO_BYTE _ABS0 :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE :1;\r
+    IO_BYTE _PSZ :3;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE _ABS :2;\r
+  }bitc;\r
+ }MCRBSTR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _RYE0 :1;\r
+    IO_BYTE _HLD0 :1;\r
+    IO_BYTE _WR01 :1;\r
+    IO_BYTE _WR00 :1;\r
+    IO_BYTE _IW03 :1;\r
+    IO_BYTE _IW02 :1;\r
+    IO_BYTE _IW01 :1;\r
+    IO_BYTE _IW00 :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE _WR0 :2;\r
+    IO_BYTE _IW0 :4;\r
+  }bitc;\r
+ }IOWR0STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _RYE1 :1;\r
+    IO_BYTE _HLD1 :1;\r
+    IO_BYTE _WR11 :1;\r
+    IO_BYTE _WR10 :1;\r
+    IO_BYTE _IW13 :1;\r
+    IO_BYTE _IW12 :1;\r
+    IO_BYTE _IW11 :1;\r
+    IO_BYTE _IW10 :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE _WR1 :2;\r
+    IO_BYTE _IW1 :4;\r
+  }bitc;\r
+ }IOWR1STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _RYE2 :1;\r
+    IO_BYTE _HLD2 :1;\r
+    IO_BYTE _WR21 :1;\r
+    IO_BYTE _WR20 :1;\r
+    IO_BYTE _IW23 :1;\r
+    IO_BYTE _IW22 :1;\r
+    IO_BYTE _IW21 :1;\r
+    IO_BYTE _IW20 :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE _WR2 :2;\r
+    IO_BYTE _IW2 :4;\r
+  }bitc;\r
+ }IOWR2STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _RYE3 :1;\r
+    IO_BYTE _HLD3 :1;\r
+    IO_BYTE _WR31 :1;\r
+    IO_BYTE _WR30 :1;\r
+    IO_BYTE _IW33 :1;\r
+    IO_BYTE _IW32 :1;\r
+    IO_BYTE _IW31 :1;\r
+    IO_BYTE _IW30 :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE _WR3 :2;\r
+    IO_BYTE _IW3 :4;\r
+  }bitc;\r
+ }IOWR3STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _CSE7 :1;\r
+    IO_BYTE _CSE6 :1;\r
+    IO_BYTE _CSE5 :1;\r
+    IO_BYTE _CSE4 :1;\r
+    IO_BYTE _CSE3 :1;\r
+    IO_BYTE _CSE2 :1;\r
+    IO_BYTE _CSE1 :1;\r
+    IO_BYTE _CSE0 :1;\r
+  }bit;\r
+ }CSERSTR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _CHE7 :1;\r
+    IO_BYTE _CHE6 :1;\r
+    IO_BYTE _CHE5 :1;\r
+    IO_BYTE _CHE4 :1;\r
+    IO_BYTE _CHE3 :1;\r
+    IO_BYTE _CHE2 :1;\r
+    IO_BYTE _CHE1 :1;\r
+    IO_BYTE _CHE0 :1;\r
+  }bit;\r
+ }CHERSTR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _BREN :1;\r
+    IO_BYTE _PSUS :1;\r
+    IO_BYTE _PCLR :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _RDW1 :1;\r
+    IO_BYTE _RDW0 :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE _RDW :2;\r
+  }bitc;\r
+ }TCRSTR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _SELF :1;\r
+    IO_WORD _RRLD :1;\r
+    IO_WORD _RFINT5 :1;\r
+    IO_WORD _RFINT4 :1;\r
+    IO_WORD _RDINT3 :1;\r
+    IO_WORD _RFINT2 :1;\r
+    IO_WORD _RFINT1 :1;\r
+    IO_WORD _RFINT0 :1;\r
+    IO_WORD _BRST :1;\r
+    IO_WORD _RFC2 :1;\r
+    IO_WORD _RFC1 :1;\r
+    IO_WORD _RFC0 :1;\r
+    IO_WORD _PON :1;\r
+    IO_WORD _TRC2 :1;\r
+    IO_WORD _TRC1 :1;\r
+    IO_WORD _TRC0 :1;\r
+  }bit;\r
+  struct{\r
+    IO_WORD :2;\r
+    IO_WORD _RFINT :6;\r
+    IO_WORD :1;\r
+    IO_WORD _RFC :3;\r
+    IO_WORD :1;\r
+    IO_WORD _TRC :3;\r
+  }bitc;\r
+ }RCRSTR;\r
+typedef union{   /* Mode Register */\r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _ROMA :1;\r
+    IO_BYTE _WTH1 :1;\r
+    IO_BYTE _WTH0 :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE _WTH :2;\r
+  }bitc;\r
+ }MODRSTR;\r
+typedef union{   /* R-bus Port Data Direct Read Register */\r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PDRD00STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PDRD01STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PDRD02STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PDRD03STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PDRD04STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PDRD05STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PDRD06STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PDRD07STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PDRD08STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PDRD09STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE  :1;\r
+  }bit;\r
+ }PDRD10STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PDRD13STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PDRD14STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PDRD15STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PDRD16STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+  }bit;\r
+ }PDRD17STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PDRD18STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PDRD19STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PDRD20STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PDRD22STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PDRD23STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PDRD24STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PDRD25STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PDRD26STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PDRD27STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PDRD29STR;\r
+typedef union{   /* R-bus Port Direction Register */\r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }DDR00STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }DDR01STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }DDR02STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }DDR03STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }DDR04STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }DDR05STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }DDR06STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }DDR07STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }DDR08STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }DDR09STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE  :1;\r
+  }bit;\r
+ }DDR10STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }DDR13STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }DDR14STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }DDR15STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }DDR16STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+  }bit;\r
+ }DDR17STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }DDR18STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }DDR19STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }DDR20STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }DDR22STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }DDR23STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }DDR24STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }DDR25STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }DDR26STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }DDR27STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }DDR29STR;\r
+typedef union{   /* R-bus Port Function Register */\r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PFR00STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PFR01STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PFR02STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PFR03STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PFR04STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PFR05STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PFR06STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PFR07STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PFR08STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PFR09STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE  :1;\r
+  }bit;\r
+ }PFR10STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PFR13STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PFR14STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PFR15STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PFR16STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+  }bit;\r
+ }PFR17STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PFR18STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PFR19STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PFR20STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PFR22STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PFR23STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PFR24STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PFR25STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PFR26STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PFR27STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PFR29STR;\r
+typedef union{   /* R-bus Port Extra Function Register */\r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+  }bit;\r
+ }EPFR10STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+  }bit;\r
+ }EPFR13STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }EPFR14STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }EPFR15STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+  }bit;\r
+ }EPFR16STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }EPFR18STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+  }bit;\r
+ }EPFR19STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }EPFR20STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }EPFR26STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }EPFR27STR;\r
+typedef union{   /* R-bus Port Output Drive Select Register */\r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PODR00STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PODR01STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PODR02STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PODR03STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PODR04STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PODR05STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PODR06STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PODR07STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PODR08STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PODR09STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE  :1;\r
+  }bit;\r
+ }PODR10STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PODR13STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PODR14STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PODR15STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PODR16STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+  }bit;\r
+ }PODR17STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PODR18STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PODR19STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PODR20STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PODR22STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PODR23STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PODR24STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PODR25STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PODR26STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PODR27STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PODR29STR;\r
+typedef union{   /* R-bus Port Input Level Select Register */\r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PILR00STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PILR01STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PILR02STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PILR03STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PILR04STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PILR05STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PILR06STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PILR07STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PILR08STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PILR09STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE  :1;\r
+  }bit;\r
+ }PILR10STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PILR13STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PILR14STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PILR15STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PILR16STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+  }bit;\r
+ }PILR17STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PILR18STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PILR19STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PILR20STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PILR22STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PILR23STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PILR24STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PILR25STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PILR26STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PILR27STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PILR29STR;\r
+typedef union{   /* R-bus Port Extra Input Level Select Register */\r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }EPILR00STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }EPILR01STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }EPILR02STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }EPILR03STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }EPILR04STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }EPILR05STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }EPILR06STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }EPILR07STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }EPILR08STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }EPILR09STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE  :1;\r
+  }bit;\r
+ }EPILR10STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }EPILR13STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }EPILR14STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }EPILR15STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }EPILR16STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+  }bit;\r
+ }EPILR17STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }EPILR18STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }EPILR19STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }EPILR20STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }EPILR22STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }EPILR23STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }EPILR24STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }EPILR25STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }EPILR26STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }EPILR27STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }EPILR29STR;\r
+typedef union{   /* R-bus Port Pull-Up/Down  Enable Register */\r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PPER00STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PPER01STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PPER02STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PPER03STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PPER04STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PPER05STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PPER06STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PPER07STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PPER08STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PPER09STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE  :1;\r
+  }bit;\r
+ }PPER10STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PPER13STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PPER14STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PPER15STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PPER16STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+  }bit;\r
+ }PPER17STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PPER18STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PPER19STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PPER20STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PPER22STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PPER23STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PPER24STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PPER25STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PPER26STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PPER27STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PPER29STR;\r
+typedef union{   /* R-bus Port Pull-Up/Down Control Register */\r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PPCR00STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PPCR01STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PPCR02STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PPCR03STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PPCR04STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PPCR05STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PPCR06STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PPCR07STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PPCR08STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PPCR09STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE  :1;\r
+  }bit;\r
+ }PPCR10STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PPCR13STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PPCR14STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PPCR15STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PPCR16STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+  }bit;\r
+ }PPCR17STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PPCR18STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PPCR19STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PPCR20STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PPCR22STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PPCR23STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PPCR24STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PPCR25STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PPCR26STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PPCR27STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _D7 :1;\r
+    IO_BYTE _D6 :1;\r
+    IO_BYTE _D5 :1;\r
+    IO_BYTE _D4 :1;\r
+    IO_BYTE _D3 :1;\r
+    IO_BYTE _D2 :1;\r
+    IO_BYTE _D1 :1;\r
+    IO_BYTE _D0 :1;\r
+  }bit;\r
+ }PPCR29STR;\r
+typedef union{   /* Flash Memory/I-Cache Control Register */\r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE _ASYNC :1;\r
+    IO_BYTE _FIXE :1;\r
+    IO_BYTE _BIRE :1;\r
+    IO_BYTE _RDYEG :1;\r
+    IO_BYTE _RDY :1;\r
+    IO_BYTE _RDYI :1;\r
+    IO_BYTE _RW16 :1;\r
+    IO_BYTE _LPM :1;\r
+  }bit;\r
+ }FMCSSTR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _LOCK :1;\r
+    IO_BYTE _PHASE :1;\r
+    IO_BYTE _PF2I :1;\r
+    IO_BYTE _RD64 :1;\r
+  }bit;\r
+ }FMCRSTR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD _REN :1;\r
+    IO_WORD _TAGE :1;\r
+    IO_WORD _FLUSH :1;\r
+    IO_WORD _DBEN :1;\r
+    IO_WORD _PFEN :1;\r
+    IO_WORD _PFMC :1;\r
+    IO_WORD _LOCK :1;\r
+    IO_WORD _ENAB :1;\r
+    IO_WORD _SIZE1 :1;\r
+    IO_WORD _SIZE0 :1;\r
+  }bit;\r
+  struct{\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD _SIZE :2;\r
+  }bitc;\r
+ }FCHCRSTR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _WTP1 :1;\r
+    IO_WORD _WTP0 :1;\r
+    IO_WORD _WEXH1 :1;\r
+    IO_WORD _WEXH0 :1;\r
+    IO_WORD _WTC3 :1;\r
+    IO_WORD _WTC2 :1;\r
+    IO_WORD _WTC1 :1;\r
+    IO_WORD _WTC0 :1;\r
+    IO_WORD _FRAM :1;\r
+    IO_WORD _ATD2 :1;\r
+    IO_WORD _ATD1 :1;\r
+    IO_WORD _ATD0 :1;\r
+    IO_WORD _EQ3 :1;\r
+    IO_WORD _EQ2 :1;\r
+    IO_WORD _EQ1 :1;\r
+    IO_WORD _EQ0 :1;\r
+  }bit;\r
+  struct{\r
+    IO_WORD _WTP :2;\r
+    IO_WORD _WEXH :2;\r
+    IO_WORD _WTC :4;\r
+    IO_WORD :1;\r
+    IO_WORD _ATD :3;\r
+    IO_WORD _EQ :4;\r
+  }bitc;\r
+ }FMWTSTR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE _ALEH2 :1;\r
+    IO_BYTE _ALEH1 :1;\r
+    IO_BYTE _ALEH0 :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE :1;\r
+    IO_BYTE _ALEH :3;\r
+  }bitc;\r
+ }FMWT2STR;\r
+typedef union{  \r
+    IO_BYTE    byte;\r
+    struct{   \r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE  :1;\r
+    IO_BYTE _PS2 :1;\r
+    IO_BYTE _PS1 :1;\r
+    IO_BYTE _PS0 :1;\r
+  }bit;\r
+  struct{\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE :1;\r
+    IO_BYTE _PS :3;\r
+  }bitc;\r
+ }FMPSSTR;\r
+typedef union{   /* Flash Security Control Register */\r
+    IO_LWORD   lword;\r
+    struct{   \r
+    IO_LWORD _CRC31 :1;\r
+    IO_LWORD _CRC30 :1;\r
+    IO_LWORD _CRC29 :1;\r
+    IO_LWORD _CRC28 :1;\r
+    IO_LWORD _CRC27 :1;\r
+    IO_LWORD _CRC26 :1;\r
+    IO_LWORD _CRC25 :1;\r
+    IO_LWORD _CRC24 :1;\r
+    IO_LWORD _CRC23 :1;\r
+    IO_LWORD _CRC22 :1;\r
+    IO_LWORD _CRC21 :1;\r
+    IO_LWORD _CRC20 :1;\r
+    IO_LWORD _CRC19 :1;\r
+    IO_LWORD _CRC18 :1;\r
+    IO_LWORD _CRC17 :1;\r
+    IO_LWORD _CRC16 :1;\r
+    IO_LWORD _CRC15 :1;\r
+    IO_LWORD _CRC14 :1;\r
+    IO_LWORD _CRC13 :1;\r
+    IO_LWORD _CRC12 :1;\r
+    IO_LWORD _CRC11 :1;\r
+    IO_LWORD _CRC10 :1;\r
+    IO_LWORD _CRC9 :1;\r
+    IO_LWORD _CRC8 :1;\r
+    IO_LWORD _CRC7 :1;\r
+    IO_LWORD _CRC6 :1;\r
+    IO_LWORD _CRC5 :1;\r
+    IO_LWORD _CRC4 :1;\r
+    IO_LWORD _CRC3 :1;\r
+    IO_LWORD _CRC2 :1;\r
+    IO_LWORD _CRC1 :1;\r
+    IO_LWORD _CRC0 :1;\r
+  }bit;\r
+ }FSCR0STR;\r
+typedef union{  \r
+    IO_LWORD   lword;\r
+    struct{   \r
+    IO_LWORD  :1;\r
+    IO_LWORD  :1;\r
+    IO_LWORD  :1;\r
+    IO_LWORD  :1;\r
+    IO_LWORD  :1;\r
+    IO_LWORD  :1;\r
+    IO_LWORD  :1;\r
+    IO_LWORD _RDY :1;\r
+    IO_LWORD  :1;\r
+    IO_LWORD  :1;\r
+    IO_LWORD  :1;\r
+    IO_LWORD  :1;\r
+    IO_LWORD _CSZ3 :1;\r
+    IO_LWORD _CSZ2 :1;\r
+    IO_LWORD _CSZ1 :1;\r
+    IO_LWORD _CSZ0 :1;\r
+    IO_LWORD _CSA15 :1;\r
+    IO_LWORD _CSA14 :1;\r
+    IO_LWORD _CSA13 :1;\r
+    IO_LWORD _CSA12 :1;\r
+    IO_LWORD _CSA11 :1;\r
+    IO_LWORD _CSA10 :1;\r
+    IO_LWORD _CSA9 :1;\r
+    IO_LWORD _CSA8 :1;\r
+    IO_LWORD _CSA7 :1;\r
+    IO_LWORD _CSA6 :1;\r
+    IO_LWORD _CSA5 :1;\r
+    IO_LWORD _CSA4 :1;\r
+    IO_LWORD _CSA3 :1;\r
+    IO_LWORD _CSA2 :1;\r
+    IO_LWORD _CSA1 :1;\r
+    IO_LWORD _CSA0 :1;\r
+  }bit;\r
+  struct{\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD _CSZ :4;\r
+  }bitc;\r
+ }FSCR1STR;\r
+typedef union{   /* CAN 0 Control Register */\r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD _Test :1;\r
+    IO_WORD _CCE :1;\r
+    IO_WORD _DAR :1;\r
+    IO_WORD  :1;\r
+    IO_WORD _EIE :1;\r
+    IO_WORD _SIE :1;\r
+    IO_WORD _IE :1;\r
+    IO_WORD _Init :1;\r
+  }bit;\r
+ }CTRLR0STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD _BOff :1;\r
+    IO_WORD _EWarn :1;\r
+    IO_WORD _EPass :1;\r
+    IO_WORD _RxOK :1;\r
+    IO_WORD _TxOK :1;\r
+    IO_WORD _LEC2 :1;\r
+    IO_WORD _LEC1 :1;\r
+    IO_WORD _LEC0 :1;\r
+  }bit;\r
+  struct{\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD _LEC :3;\r
+  }bitc;\r
+ }STATR0STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _RP :1;\r
+    IO_WORD _REC6 :1;\r
+    IO_WORD _REC5 :1;\r
+    IO_WORD _REC4 :1;\r
+    IO_WORD _REC3 :1;\r
+    IO_WORD _REC2 :1;\r
+    IO_WORD _REC1 :1;\r
+    IO_WORD _REC0 :1;\r
+    IO_WORD _TEC7 :1;\r
+    IO_WORD _TEC6 :1;\r
+    IO_WORD _TEC5 :1;\r
+    IO_WORD _TEC4 :1;\r
+    IO_WORD _TEC3 :1;\r
+    IO_WORD _TEC2 :1;\r
+    IO_WORD _TEC1 :1;\r
+    IO_WORD _TEC0 :1;\r
+  }bit;\r
+  struct{\r
+    IO_WORD :1;\r
+    IO_WORD _REC :7;\r
+    IO_WORD _TEC :8;\r
+  }bitc;\r
+ }ERRCNT0STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD  :1;\r
+    IO_WORD _Tseg22 :1;\r
+    IO_WORD _Tseg21 :1;\r
+    IO_WORD _Tseg20 :1;\r
+    IO_WORD _Tseg13 :1;\r
+    IO_WORD _Tseg12 :1;\r
+    IO_WORD _Tseg11 :1;\r
+    IO_WORD _Tseg10 :1;\r
+    IO_WORD _SJW1 :1;\r
+    IO_WORD _SJW0 :1;\r
+    IO_WORD _BRP5 :1;\r
+    IO_WORD _BRP4 :1;\r
+    IO_WORD _BRP3 :1;\r
+    IO_WORD _BRP2 :1;\r
+    IO_WORD _BRP1 :1;\r
+    IO_WORD _BRP0 :1;\r
+  }bit;\r
+  struct{\r
+    IO_WORD :1;\r
+    IO_WORD _Tseg2 :3;\r
+    IO_WORD _Tseg1 :4;\r
+    IO_WORD _SJW :2;\r
+    IO_WORD _BRP :6;\r
+  }bitc;\r
+ }BTR0STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD _Rx :1;\r
+    IO_WORD _Tx1 :1;\r
+    IO_WORD _Tx0 :1;\r
+    IO_WORD _LBack :1;\r
+    IO_WORD _Silent :1;\r
+    IO_WORD _Basic :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+  }bit;\r
+  struct{\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD _Tx :2;\r
+  }bitc;\r
+ }TESTR0STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD _BRPE3 :1;\r
+    IO_WORD _BRPE2 :1;\r
+    IO_WORD _BRPE1 :1;\r
+    IO_WORD _BRPE0 :1;\r
+  }bit;\r
+  struct{\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD _BRPE :4;\r
+  }bitc;\r
+ }BRPER0STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+  }bit;\r
+ }BRPE0STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+  }bit;\r
+ }CBSYNC0STR;\r
+typedef union{   /* CAN 0 IF 1 */\r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _Busy :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD _MN5 :1;\r
+    IO_WORD _MN4 :1;\r
+    IO_WORD _MN3 :1;\r
+    IO_WORD _MN2 :1;\r
+    IO_WORD _MN1 :1;\r
+    IO_WORD _MN0 :1;\r
+  }bit;\r
+  struct{\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD _MN :6;\r
+  }bitc;\r
+ }IF1CREQ0STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD _WR :1;\r
+    IO_WORD _Mask :1;\r
+    IO_WORD _Arb :1;\r
+    IO_WORD _Control :1;\r
+    IO_WORD _CIP :1;\r
+    IO_WORD _TxReq :1;\r
+    IO_WORD _DataA :1;\r
+    IO_WORD _DataB :1;\r
+  }bit;\r
+ }IF1CMSK0STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _MXtd :1;\r
+    IO_WORD _MDir :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+  }bit;\r
+ }IF1MSK20STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _MsgVal :1;\r
+    IO_WORD _Xtd :1;\r
+    IO_WORD _DIR :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+  }bit;\r
+ }IF1ARB20STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _NewDat :1;\r
+    IO_WORD _MsgLst :1;\r
+    IO_WORD _IntPnd :1;\r
+    IO_WORD _UMask :1;\r
+    IO_WORD _TxIE :1;\r
+    IO_WORD _RxIE :1;\r
+    IO_WORD _RmtEn :1;\r
+    IO_WORD _TxRqst :1;\r
+    IO_WORD _EoB :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD _DLC3 :1;\r
+    IO_WORD _DLC2 :1;\r
+    IO_WORD _DLC1 :1;\r
+    IO_WORD _DLC0 :1;\r
+  }bit;\r
+  struct{\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD _DLC :4;\r
+  }bitc;\r
+ }IF1MCTR0STR;\r
+typedef union{   /* CAN 0 IF 2 */\r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _Busy :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD _MN5 :1;\r
+    IO_WORD _MN4 :1;\r
+    IO_WORD _MN3 :1;\r
+    IO_WORD _MN2 :1;\r
+    IO_WORD _MN1 :1;\r
+    IO_WORD _MN0 :1;\r
+  }bit;\r
+  struct{\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD _MN :6;\r
+  }bitc;\r
+ }IF2CREQ0STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD _WR :1;\r
+    IO_WORD _Mask :1;\r
+    IO_WORD _Arb :1;\r
+    IO_WORD _Control :1;\r
+    IO_WORD _CIP :1;\r
+    IO_WORD _TxReq :1;\r
+    IO_WORD _DataA :1;\r
+    IO_WORD _DataB :1;\r
+  }bit;\r
+ }IF2CMSK0STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _MXtd :1;\r
+    IO_WORD _MDir :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+  }bit;\r
+ }IF2MSK20STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _MsgVal :1;\r
+    IO_WORD _Xtd :1;\r
+    IO_WORD _DIR :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+  }bit;\r
+ }IF2ARB20STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _NewDat :1;\r
+    IO_WORD _MsgLst :1;\r
+    IO_WORD _IntPnd :1;\r
+    IO_WORD _UMask :1;\r
+    IO_WORD _TxIE :1;\r
+    IO_WORD _RxIE :1;\r
+    IO_WORD _RmtEn :1;\r
+    IO_WORD _TxRqst :1;\r
+    IO_WORD _EoB :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD _DLC3 :1;\r
+    IO_WORD _DLC2 :1;\r
+    IO_WORD _DLC1 :1;\r
+    IO_WORD _DLC0 :1;\r
+  }bit;\r
+  struct{\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD _DLC :4;\r
+  }bitc;\r
+ }IF2MCTR0STR;\r
+typedef union{   /* CAN 1 Control Register */\r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD _Test :1;\r
+    IO_WORD _CCE :1;\r
+    IO_WORD _DAR :1;\r
+    IO_WORD  :1;\r
+    IO_WORD _EIE :1;\r
+    IO_WORD _SIE :1;\r
+    IO_WORD _IE :1;\r
+    IO_WORD _Init :1;\r
+  }bit;\r
+ }CTRLR1STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD _BOff :1;\r
+    IO_WORD _EWarn :1;\r
+    IO_WORD _EPass :1;\r
+    IO_WORD _RxOK :1;\r
+    IO_WORD _TxOK :1;\r
+    IO_WORD _LEC2 :1;\r
+    IO_WORD _LEC1 :1;\r
+    IO_WORD _LEC0 :1;\r
+  }bit;\r
+  struct{\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD _LEC :3;\r
+  }bitc;\r
+ }STATR1STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _RP :1;\r
+    IO_WORD _REC6 :1;\r
+    IO_WORD _REC5 :1;\r
+    IO_WORD _REC4 :1;\r
+    IO_WORD _REC3 :1;\r
+    IO_WORD _REC2 :1;\r
+    IO_WORD _REC1 :1;\r
+    IO_WORD _REC0 :1;\r
+    IO_WORD _TEC7 :1;\r
+    IO_WORD _TEC6 :1;\r
+    IO_WORD _TEC5 :1;\r
+    IO_WORD _TEC4 :1;\r
+    IO_WORD _TEC3 :1;\r
+    IO_WORD _TEC2 :1;\r
+    IO_WORD _TEC1 :1;\r
+    IO_WORD _TEC0 :1;\r
+  }bit;\r
+  struct{\r
+    IO_WORD :1;\r
+    IO_WORD _REC :7;\r
+    IO_WORD _TEC :8;\r
+  }bitc;\r
+ }ERRCNT1STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD  :1;\r
+    IO_WORD _Tseg22 :1;\r
+    IO_WORD _Tseg21 :1;\r
+    IO_WORD _Tseg20 :1;\r
+    IO_WORD _Tseg13 :1;\r
+    IO_WORD _Tseg12 :1;\r
+    IO_WORD _Tseg11 :1;\r
+    IO_WORD _Tseg10 :1;\r
+    IO_WORD _SJW1 :1;\r
+    IO_WORD _SJW0 :1;\r
+    IO_WORD _BRP5 :1;\r
+    IO_WORD _BRP4 :1;\r
+    IO_WORD _BRP3 :1;\r
+    IO_WORD _BRP2 :1;\r
+    IO_WORD _BRP1 :1;\r
+    IO_WORD _BRP0 :1;\r
+  }bit;\r
+  struct{\r
+    IO_WORD :1;\r
+    IO_WORD _Tseg2 :3;\r
+    IO_WORD _Tseg1 :4;\r
+    IO_WORD _SJW :2;\r
+    IO_WORD _BRP :6;\r
+  }bitc;\r
+ }BTR1STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD _Rx :1;\r
+    IO_WORD _Tx1 :1;\r
+    IO_WORD _Tx0 :1;\r
+    IO_WORD _LBack :1;\r
+    IO_WORD _Silent :1;\r
+    IO_WORD _Basic :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+  }bit;\r
+  struct{\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD _Tx :2;\r
+  }bitc;\r
+ }TESTR1STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD _BRPE3 :1;\r
+    IO_WORD _BRPE2 :1;\r
+    IO_WORD _BRPE1 :1;\r
+    IO_WORD _BRPE0 :1;\r
+  }bit;\r
+  struct{\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD _BRPE :4;\r
+  }bitc;\r
+ }BRPER1STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+  }bit;\r
+ }BRPE1STR;\r
+typedef union{   /* CAN 1 IF 1 */\r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _Busy :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD _MN5 :1;\r
+    IO_WORD _MN4 :1;\r
+    IO_WORD _MN3 :1;\r
+    IO_WORD _MN2 :1;\r
+    IO_WORD _MN1 :1;\r
+    IO_WORD _MN0 :1;\r
+  }bit;\r
+  struct{\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD _MN :6;\r
+  }bitc;\r
+ }IF1CREQ1STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD _WR :1;\r
+    IO_WORD _Mask :1;\r
+    IO_WORD _Arb :1;\r
+    IO_WORD _Control :1;\r
+    IO_WORD _CIP :1;\r
+    IO_WORD _TxReq :1;\r
+    IO_WORD _DataA :1;\r
+    IO_WORD _DataB :1;\r
+  }bit;\r
+ }IF1CMSK1STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _MXtd :1;\r
+    IO_WORD _MDir :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+  }bit;\r
+ }IF1MSK21STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _MsgVal :1;\r
+    IO_WORD _Xtd :1;\r
+    IO_WORD _DIR :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+  }bit;\r
+ }IF1ARB21STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _NewDat :1;\r
+    IO_WORD _MsgLst :1;\r
+    IO_WORD _IntPnd :1;\r
+    IO_WORD _UMask :1;\r
+    IO_WORD _TxIE :1;\r
+    IO_WORD _RxIE :1;\r
+    IO_WORD _RmtEn :1;\r
+    IO_WORD _TxRqst :1;\r
+    IO_WORD _EoB :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD _DLC3 :1;\r
+    IO_WORD _DLC2 :1;\r
+    IO_WORD _DLC1 :1;\r
+    IO_WORD _DLC0 :1;\r
+  }bit;\r
+  struct{\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD _DLC :4;\r
+  }bitc;\r
+ }IF1MCTR1STR;\r
+typedef union{   /* CAN 1 IF 2 */\r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _Busy :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD _MN5 :1;\r
+    IO_WORD _MN4 :1;\r
+    IO_WORD _MN3 :1;\r
+    IO_WORD _MN2 :1;\r
+    IO_WORD _MN1 :1;\r
+    IO_WORD _MN0 :1;\r
+  }bit;\r
+  struct{\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD _MN :6;\r
+  }bitc;\r
+ }IF2CREQ1STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD _WR :1;\r
+    IO_WORD _Mask :1;\r
+    IO_WORD _Arb :1;\r
+    IO_WORD _Control :1;\r
+    IO_WORD _CIP :1;\r
+    IO_WORD _TxReq :1;\r
+    IO_WORD _DataA :1;\r
+    IO_WORD _DataB :1;\r
+  }bit;\r
+ }IF2CMSK1STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _MXtd :1;\r
+    IO_WORD _MDir :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+  }bit;\r
+ }IF2MSK21STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _MsgVal :1;\r
+    IO_WORD _Xtd :1;\r
+    IO_WORD _DIR :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+  }bit;\r
+ }IF2ARB21STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _NewDat :1;\r
+    IO_WORD _MsgLst :1;\r
+    IO_WORD _IntPnd :1;\r
+    IO_WORD _UMask :1;\r
+    IO_WORD _TxIE :1;\r
+    IO_WORD _RxIE :1;\r
+    IO_WORD _RmtEn :1;\r
+    IO_WORD _TxRqst :1;\r
+    IO_WORD _EoB :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD _DLC3 :1;\r
+    IO_WORD _DLC2 :1;\r
+    IO_WORD _DLC1 :1;\r
+    IO_WORD _DLC0 :1;\r
+  }bit;\r
+  struct{\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD _DLC :4;\r
+  }bitc;\r
+ }IF2MCTR1STR;\r
+typedef union{   /* CAN 2 Control Register */\r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD _Test :1;\r
+    IO_WORD _CCE :1;\r
+    IO_WORD _DAR :1;\r
+    IO_WORD  :1;\r
+    IO_WORD _EIE :1;\r
+    IO_WORD _SIE :1;\r
+    IO_WORD _IE :1;\r
+    IO_WORD _Init :1;\r
+  }bit;\r
+ }CTRLR2STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD _BOff :1;\r
+    IO_WORD _EWarn :1;\r
+    IO_WORD _EPass :1;\r
+    IO_WORD _RxOK :1;\r
+    IO_WORD _TxOK :1;\r
+    IO_WORD _LEC2 :1;\r
+    IO_WORD _LEC1 :1;\r
+    IO_WORD _LEC0 :1;\r
+  }bit;\r
+  struct{\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD _LEC :3;\r
+  }bitc;\r
+ }STATR2STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _RP :1;\r
+    IO_WORD _REC6 :1;\r
+    IO_WORD _REC5 :1;\r
+    IO_WORD _REC4 :1;\r
+    IO_WORD _REC3 :1;\r
+    IO_WORD _REC2 :1;\r
+    IO_WORD _REC1 :1;\r
+    IO_WORD _REC0 :1;\r
+    IO_WORD _TEC7 :1;\r
+    IO_WORD _TEC6 :1;\r
+    IO_WORD _TEC5 :1;\r
+    IO_WORD _TEC4 :1;\r
+    IO_WORD _TEC3 :1;\r
+    IO_WORD _TEC2 :1;\r
+    IO_WORD _TEC1 :1;\r
+    IO_WORD _TEC0 :1;\r
+  }bit;\r
+  struct{\r
+    IO_WORD :1;\r
+    IO_WORD _REC :7;\r
+    IO_WORD _TEC :8;\r
+  }bitc;\r
+ }ERRCNT2STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD  :1;\r
+    IO_WORD _Tseg22 :1;\r
+    IO_WORD _Tseg21 :1;\r
+    IO_WORD _Tseg20 :1;\r
+    IO_WORD _Tseg13 :1;\r
+    IO_WORD _Tseg12 :1;\r
+    IO_WORD _Tseg11 :1;\r
+    IO_WORD _Tseg10 :1;\r
+    IO_WORD _SJW1 :1;\r
+    IO_WORD _SJW0 :1;\r
+    IO_WORD _BRP5 :1;\r
+    IO_WORD _BRP4 :1;\r
+    IO_WORD _BRP3 :1;\r
+    IO_WORD _BRP2 :1;\r
+    IO_WORD _BRP1 :1;\r
+    IO_WORD _BRP0 :1;\r
+  }bit;\r
+  struct{\r
+    IO_WORD :1;\r
+    IO_WORD _Tseg2 :3;\r
+    IO_WORD _Tseg1 :4;\r
+    IO_WORD _SJW :2;\r
+    IO_WORD _BRP :6;\r
+  }bitc;\r
+ }BTR2STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD _Rx :1;\r
+    IO_WORD _Tx1 :1;\r
+    IO_WORD _Tx0 :1;\r
+    IO_WORD _LBack :1;\r
+    IO_WORD _Silent :1;\r
+    IO_WORD _Basic :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+  }bit;\r
+  struct{\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD _Tx :2;\r
+  }bitc;\r
+ }TESTR2STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD _BRPE3 :1;\r
+    IO_WORD _BRPE2 :1;\r
+    IO_WORD _BRPE1 :1;\r
+    IO_WORD _BRPE0 :1;\r
+  }bit;\r
+  struct{\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD _BRPE :4;\r
+  }bitc;\r
+ }BRPER2STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+  }bit;\r
+ }BRPE2STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+  }bit;\r
+ }CBSYNC2STR;\r
+typedef union{   /* CAN 2 IF 1 */\r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _Busy :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD _MN5 :1;\r
+    IO_WORD _MN4 :1;\r
+    IO_WORD _MN3 :1;\r
+    IO_WORD _MN2 :1;\r
+    IO_WORD _MN1 :1;\r
+    IO_WORD _MN0 :1;\r
+  }bit;\r
+  struct{\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD _MN :6;\r
+  }bitc;\r
+ }IF1CREQ2STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD _WR :1;\r
+    IO_WORD _Mask :1;\r
+    IO_WORD _Arb :1;\r
+    IO_WORD _Control :1;\r
+    IO_WORD _CIP :1;\r
+    IO_WORD _TxReq :1;\r
+    IO_WORD _DataA :1;\r
+    IO_WORD _DataB :1;\r
+  }bit;\r
+ }IF1CMSK2STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _MXtd :1;\r
+    IO_WORD _MDir :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+  }bit;\r
+ }IF1MSK22STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _MsgVal :1;\r
+    IO_WORD _Xtd :1;\r
+    IO_WORD _DIR :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+  }bit;\r
+ }IF1ARB22STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _NewDat :1;\r
+    IO_WORD _MsgLst :1;\r
+    IO_WORD _IntPnd :1;\r
+    IO_WORD _UMask :1;\r
+    IO_WORD _TxIE :1;\r
+    IO_WORD _RxIE :1;\r
+    IO_WORD _RmtEn :1;\r
+    IO_WORD _TxRqst :1;\r
+    IO_WORD _EoB :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD _DLC3 :1;\r
+    IO_WORD _DLC2 :1;\r
+    IO_WORD _DLC1 :1;\r
+    IO_WORD _DLC0 :1;\r
+  }bit;\r
+  struct{\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD _DLC :4;\r
+  }bitc;\r
+ }IF1MCTR2STR;\r
+typedef union{   /* CAN 2 IF 2 */\r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _Busy :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD _MN5 :1;\r
+    IO_WORD _MN4 :1;\r
+    IO_WORD _MN3 :1;\r
+    IO_WORD _MN2 :1;\r
+    IO_WORD _MN1 :1;\r
+    IO_WORD _MN0 :1;\r
+  }bit;\r
+  struct{\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD _MN :6;\r
+  }bitc;\r
+ }IF2CREQ2STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD _WR :1;\r
+    IO_WORD _Mask :1;\r
+    IO_WORD _Arb :1;\r
+    IO_WORD _Control :1;\r
+    IO_WORD _CIP :1;\r
+    IO_WORD _TxReq :1;\r
+    IO_WORD _DataA :1;\r
+    IO_WORD _DataB :1;\r
+  }bit;\r
+ }IF2CMSK2STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _MXtd :1;\r
+    IO_WORD _MDir :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+  }bit;\r
+ }IF2MSK22STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _MsgVal :1;\r
+    IO_WORD _Xtd :1;\r
+    IO_WORD _DIR :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+  }bit;\r
+ }IF2ARB22STR;\r
+typedef union{  \r
+    IO_WORD    word;\r
+    struct{   \r
+    IO_WORD _NewDat :1;\r
+    IO_WORD _MsgLst :1;\r
+    IO_WORD _IntPnd :1;\r
+    IO_WORD _UMask :1;\r
+    IO_WORD _TxIE :1;\r
+    IO_WORD _RxIE :1;\r
+    IO_WORD _RmtEn :1;\r
+    IO_WORD _TxRqst :1;\r
+    IO_WORD _EoB :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD  :1;\r
+    IO_WORD _DLC3 :1;\r
+    IO_WORD _DLC2 :1;\r
+    IO_WORD _DLC1 :1;\r
+    IO_WORD _DLC0 :1;\r
+  }bit;\r
+  struct{\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD :1;\r
+    IO_WORD _DLC :4;\r
+  }bitc;\r
+ }IF2MCTR2STR;\r
+typedef union{   /* EDSU/MPU Registers */\r
+    IO_LWORD   lword;\r
+    struct{   \r
+    IO_LWORD  :1;\r
+    IO_LWORD  :1;\r
+    IO_LWORD  :1;\r
+    IO_LWORD  :1;\r
+    IO_LWORD  :1;\r
+    IO_LWORD  :1;\r
+    IO_LWORD  :1;\r
+    IO_LWORD  :1;\r
+    IO_LWORD  :1;\r
+    IO_LWORD  :1;\r
+    IO_LWORD  :1;\r
+    IO_LWORD  :1;\r
+    IO_LWORD  :1;\r
+    IO_LWORD  :1;\r
+    IO_LWORD  :1;\r
+    IO_LWORD  :1;\r
+    IO_LWORD _SR :1;\r
+    IO_LWORD _SW :1;\r
+    IO_LWORD _SX :1;\r
+    IO_LWORD _UR :1;\r
+    IO_LWORD _UW :1;\r
+    IO_LWORD _UX :1;\r
+    IO_LWORD _FCPU :1;\r
+    IO_LWORD _FDMA :1;\r
+    IO_LWORD _EEMM :1;\r
+    IO_LWORD _PFD :1;\r
+    IO_LWORD _SINT1 :1;\r
+    IO_LWORD _SINT0 :1;\r
+    IO_LWORD _EINT1 :1;\r
+    IO_LWORD _EINT0 :1;\r
+    IO_LWORD _EINTT :1;\r
+    IO_LWORD _EINTR :1;\r
+  }bit;\r
+  struct{\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD _SINT :2;\r
+    IO_LWORD _EINT :2;\r
+  }bitc;\r
+ }BCTRLSTR;\r
+typedef union{  \r
+    IO_LWORD   lword;\r
+    struct{   \r
+    IO_LWORD  :1;\r
+    IO_LWORD  :1;\r
+    IO_LWORD  :1;\r
+    IO_LWORD  :1;\r
+    IO_LWORD  :1;\r
+    IO_LWORD  :1;\r
+    IO_LWORD  :1;\r
+    IO_LWORD  :1;\r
+    IO_LWORD  :1;\r
+    IO_LWORD  :1;\r
+    IO_LWORD  :1;\r
+    IO_LWORD  :1;\r
+    IO_LWORD  :1;\r
+    IO_LWORD  :1;\r
+    IO_LWORD  :1;\r
+    IO_LWORD  :1;\r
+    IO_LWORD _IDX4 :1;\r
+    IO_LWORD _IDX3 :1;\r
+    IO_LWORD _IDX2 :1;\r
+    IO_LWORD _IDX1 :1;\r
+    IO_LWORD _IDX0 :1;\r
+    IO_LWORD _CDMA :1;\r
+    IO_LWORD _CSZ1 :1;\r
+    IO_LWORD _CSZ0 :1;\r
+    IO_LWORD _CRW1 :1;\r
+    IO_LWORD _CRW0 :1;\r
+    IO_LWORD _PV :1;\r
+    IO_LWORD _RST :1;\r
+    IO_LWORD _INT1 :1;\r
+    IO_LWORD _INT0 :1;\r
+    IO_LWORD _INTT :1;\r
+    IO_LWORD _INTR :1;\r
+  }bit;\r
+  struct{\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD _IDX :5;\r
+    IO_LWORD :1;\r
+    IO_LWORD _CSZ :2;\r
+    IO_LWORD _CRW :2;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD _INT :2;\r
+  }bitc;\r
+ }BSTATSTR;\r
+typedef union{  \r
+    IO_LWORD   lword;\r
+    struct{   \r
+    IO_LWORD _BD31 :1;\r
+    IO_LWORD _BD30 :1;\r
+    IO_LWORD _BD29 :1;\r
+    IO_LWORD _BD28 :1;\r
+    IO_LWORD _BD27 :1;\r
+    IO_LWORD _BD26 :1;\r
+    IO_LWORD _BD25 :1;\r
+    IO_LWORD _BD24 :1;\r
+    IO_LWORD _BD23 :1;\r
+    IO_LWORD _BD22 :1;\r
+    IO_LWORD _BD21 :1;\r
+    IO_LWORD _BD20 :1;\r
+    IO_LWORD _BD19 :1;\r
+    IO_LWORD _BD18 :1;\r
+    IO_LWORD _BD17 :1;\r
+    IO_LWORD _BD16 :1;\r
+    IO_LWORD _BD15 :1;\r
+    IO_LWORD _BD14 :1;\r
+    IO_LWORD _BD13 :1;\r
+    IO_LWORD _BD12 :1;\r
+    IO_LWORD _BD11 :1;\r
+    IO_LWORD _BD10 :1;\r
+    IO_LWORD _BD9 :1;\r
+    IO_LWORD _BD8 :1;\r
+    IO_LWORD _BD7 :1;\r
+    IO_LWORD _BD6 :1;\r
+    IO_LWORD _BD5 :1;\r
+    IO_LWORD _BD4 :1;\r
+    IO_LWORD _BD3 :1;\r
+    IO_LWORD _BD2 :1;\r
+    IO_LWORD _BD1 :1;\r
+    IO_LWORD _BD0 :1;\r
+  }bit;\r
+ }BIRQSTR;\r
+typedef union{  \r
+    IO_LWORD   lword;\r
+    struct{   \r
+    IO_LWORD  :1;\r
+    IO_LWORD  :1;\r
+    IO_LWORD  :1;\r
+    IO_LWORD  :1;\r
+    IO_LWORD  :1;\r
+    IO_LWORD  :1;\r
+    IO_LWORD  :1;\r
+    IO_LWORD  :1;\r
+    IO_LWORD _SRX1 :1;\r
+    IO_LWORD _SW1 :1;\r
+    IO_LWORD _SRX0 :1;\r
+    IO_LWORD _SW0 :1;\r
+    IO_LWORD _URX1 :1;\r
+    IO_LWORD _UW1 :1;\r
+    IO_LWORD _URX0 :1;\r
+    IO_LWORD _UW0 :1;\r
+    IO_LWORD _MPE :1;\r
+    IO_LWORD _COMB :1;\r
+    IO_LWORD _CTC1 :1;\r
+    IO_LWORD _CTC0 :1;\r
+    IO_LWORD _OBS1 :1;\r
+    IO_LWORD _OBS0 :1;\r
+    IO_LWORD _OBT1 :1;\r
+    IO_LWORD _OBT0 :1;\r
+    IO_LWORD _EP3 :1;\r
+    IO_LWORD _EP2 :1;\r
+    IO_LWORD _EP1 :1;\r
+    IO_LWORD _EP0 :1;\r
+    IO_LWORD _EM1 :1;\r
+    IO_LWORD _EM0 :1;\r
+    IO_LWORD _ER1 :1;\r
+    IO_LWORD _ER0 :1;\r
+  }bit;\r
+  struct{\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD _CTC :2;\r
+    IO_LWORD _OBS :2;\r
+    IO_LWORD _OBT :2;\r
+    IO_LWORD _EP :4;\r
+    IO_LWORD _EM :2;\r
+    IO_LWORD _ER :2;\r
+  }bitc;\r
+ }BCR0STR;\r
+typedef union{  \r
+    IO_LWORD   lword;\r
+    struct{   \r
+    IO_LWORD  :1;\r
+    IO_LWORD  :1;\r
+    IO_LWORD  :1;\r
+    IO_LWORD  :1;\r
+    IO_LWORD  :1;\r
+    IO_LWORD  :1;\r
+    IO_LWORD  :1;\r
+    IO_LWORD  :1;\r
+    IO_LWORD _SRX1 :1;\r
+    IO_LWORD _SW1 :1;\r
+    IO_LWORD _SRX0 :1;\r
+    IO_LWORD _SW0 :1;\r
+    IO_LWORD _URX1 :1;\r
+    IO_LWORD _UW1 :1;\r
+    IO_LWORD _URX0 :1;\r
+    IO_LWORD _UW0 :1;\r
+    IO_LWORD _MPE :1;\r
+    IO_LWORD _COMB :1;\r
+    IO_LWORD _CTC1 :1;\r
+    IO_LWORD _CTC0 :1;\r
+    IO_LWORD _OBS1 :1;\r
+    IO_LWORD _OBS0 :1;\r
+    IO_LWORD _OBT1 :1;\r
+    IO_LWORD _OBT0 :1;\r
+    IO_LWORD _EP3 :1;\r
+    IO_LWORD _EP2 :1;\r
+    IO_LWORD _EP1 :1;\r
+    IO_LWORD _EP0 :1;\r
+    IO_LWORD _EM1 :1;\r
+    IO_LWORD _EM0 :1;\r
+    IO_LWORD _ER1 :1;\r
+    IO_LWORD _ER0 :1;\r
+  }bit;\r
+  struct{\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD _CTC :2;\r
+    IO_LWORD _OBS :2;\r
+    IO_LWORD _OBT :2;\r
+    IO_LWORD _EP :4;\r
+    IO_LWORD _EM :2;\r
+    IO_LWORD _ER :2;\r
+  }bitc;\r
+ }BCR1STR;\r
+typedef union{  \r
+    IO_LWORD   lword;\r
+    struct{   \r
+    IO_LWORD  :1;\r
+    IO_LWORD  :1;\r
+    IO_LWORD  :1;\r
+    IO_LWORD  :1;\r
+    IO_LWORD  :1;\r
+    IO_LWORD  :1;\r
+    IO_LWORD  :1;\r
+    IO_LWORD  :1;\r
+    IO_LWORD _SRX1 :1;\r
+    IO_LWORD _SW1 :1;\r
+    IO_LWORD _SRX0 :1;\r
+    IO_LWORD _SW0 :1;\r
+    IO_LWORD _URX1 :1;\r
+    IO_LWORD _UW1 :1;\r
+    IO_LWORD _URX0 :1;\r
+    IO_LWORD _UW0 :1;\r
+    IO_LWORD _MPE :1;\r
+    IO_LWORD _COMB :1;\r
+    IO_LWORD _CTC1 :1;\r
+    IO_LWORD _CTC0 :1;\r
+    IO_LWORD _OBS1 :1;\r
+    IO_LWORD _OBS0 :1;\r
+    IO_LWORD _OBT1 :1;\r
+    IO_LWORD _OBT0 :1;\r
+    IO_LWORD _EP3 :1;\r
+    IO_LWORD _EP2 :1;\r
+    IO_LWORD _EP1 :1;\r
+    IO_LWORD _EP0 :1;\r
+    IO_LWORD _EM1 :1;\r
+    IO_LWORD _EM0 :1;\r
+    IO_LWORD _ER1 :1;\r
+    IO_LWORD _ER0 :1;\r
+  }bit;\r
+  struct{\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD _CTC :2;\r
+    IO_LWORD _OBS :2;\r
+    IO_LWORD _OBT :2;\r
+    IO_LWORD _EP :4;\r
+    IO_LWORD _EM :2;\r
+    IO_LWORD _ER :2;\r
+  }bitc;\r
+ }BCR2STR;\r
+typedef union{  \r
+    IO_LWORD   lword;\r
+    struct{   \r
+    IO_LWORD  :1;\r
+    IO_LWORD  :1;\r
+    IO_LWORD  :1;\r
+    IO_LWORD  :1;\r
+    IO_LWORD  :1;\r
+    IO_LWORD  :1;\r
+    IO_LWORD  :1;\r
+    IO_LWORD  :1;\r
+    IO_LWORD _SRX1 :1;\r
+    IO_LWORD _SW1 :1;\r
+    IO_LWORD _SRX0 :1;\r
+    IO_LWORD _SW0 :1;\r
+    IO_LWORD _URX1 :1;\r
+    IO_LWORD _UW1 :1;\r
+    IO_LWORD _URX0 :1;\r
+    IO_LWORD _UW0 :1;\r
+    IO_LWORD _MPE :1;\r
+    IO_LWORD _COMB :1;\r
+    IO_LWORD _CTC1 :1;\r
+    IO_LWORD _CTC0 :1;\r
+    IO_LWORD _OBS1 :1;\r
+    IO_LWORD _OBS0 :1;\r
+    IO_LWORD _OBT1 :1;\r
+    IO_LWORD _OBT0 :1;\r
+    IO_LWORD _EP3 :1;\r
+    IO_LWORD _EP2 :1;\r
+    IO_LWORD _EP1 :1;\r
+    IO_LWORD _EP0 :1;\r
+    IO_LWORD _EM1 :1;\r
+    IO_LWORD _EM0 :1;\r
+    IO_LWORD _ER1 :1;\r
+    IO_LWORD _ER0 :1;\r
+  }bit;\r
+  struct{\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD _CTC :2;\r
+    IO_LWORD _OBS :2;\r
+    IO_LWORD _OBT :2;\r
+    IO_LWORD _EP :4;\r
+    IO_LWORD _EM :2;\r
+    IO_LWORD _ER :2;\r
+  }bitc;\r
+ }BCR3STR;\r
+typedef union{  \r
+    IO_LWORD   lword;\r
+    struct{   \r
+    IO_LWORD  :1;\r
+    IO_LWORD  :1;\r
+    IO_LWORD  :1;\r
+    IO_LWORD  :1;\r
+    IO_LWORD  :1;\r
+    IO_LWORD  :1;\r
+    IO_LWORD  :1;\r
+    IO_LWORD  :1;\r
+    IO_LWORD _SRX1 :1;\r
+    IO_LWORD _SW1 :1;\r
+    IO_LWORD _SRX0 :1;\r
+    IO_LWORD _SW0 :1;\r
+    IO_LWORD _URX1 :1;\r
+    IO_LWORD _UW1 :1;\r
+    IO_LWORD _URX0 :1;\r
+    IO_LWORD _UW0 :1;\r
+    IO_LWORD _MPE :1;\r
+    IO_LWORD _COMB :1;\r
+    IO_LWORD _CTC1 :1;\r
+    IO_LWORD _CTC0 :1;\r
+    IO_LWORD _OBS1 :1;\r
+    IO_LWORD _OBS0 :1;\r
+    IO_LWORD _OBT1 :1;\r
+    IO_LWORD _OBT0 :1;\r
+    IO_LWORD _EP3 :1;\r
+    IO_LWORD _EP2 :1;\r
+    IO_LWORD _EP1 :1;\r
+    IO_LWORD _EP0 :1;\r
+    IO_LWORD _EM1 :1;\r
+    IO_LWORD _EM0 :1;\r
+    IO_LWORD _ER1 :1;\r
+    IO_LWORD _ER0 :1;\r
+  }bit;\r
+  struct{\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD _CTC :2;\r
+    IO_LWORD _OBS :2;\r
+    IO_LWORD _OBT :2;\r
+    IO_LWORD _EP :4;\r
+    IO_LWORD _EM :2;\r
+    IO_LWORD _ER :2;\r
+  }bitc;\r
+ }BCR4STR;\r
+typedef union{  \r
+    IO_LWORD   lword;\r
+    struct{   \r
+    IO_LWORD  :1;\r
+    IO_LWORD  :1;\r
+    IO_LWORD  :1;\r
+    IO_LWORD  :1;\r
+    IO_LWORD  :1;\r
+    IO_LWORD  :1;\r
+    IO_LWORD  :1;\r
+    IO_LWORD  :1;\r
+    IO_LWORD _SRX1 :1;\r
+    IO_LWORD _SW1 :1;\r
+    IO_LWORD _SRX0 :1;\r
+    IO_LWORD _SW0 :1;\r
+    IO_LWORD _URX1 :1;\r
+    IO_LWORD _UW1 :1;\r
+    IO_LWORD _URX0 :1;\r
+    IO_LWORD _UW0 :1;\r
+    IO_LWORD _MPE :1;\r
+    IO_LWORD _COMB :1;\r
+    IO_LWORD _CTC1 :1;\r
+    IO_LWORD _CTC0 :1;\r
+    IO_LWORD _OBS1 :1;\r
+    IO_LWORD _OBS0 :1;\r
+    IO_LWORD _OBT1 :1;\r
+    IO_LWORD _OBT0 :1;\r
+    IO_LWORD _EP3 :1;\r
+    IO_LWORD _EP2 :1;\r
+    IO_LWORD _EP1 :1;\r
+    IO_LWORD _EP0 :1;\r
+    IO_LWORD _EM1 :1;\r
+    IO_LWORD _EM0 :1;\r
+    IO_LWORD _ER1 :1;\r
+    IO_LWORD _ER0 :1;\r
+  }bit;\r
+  struct{\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD _CTC :2;\r
+    IO_LWORD _OBS :2;\r
+    IO_LWORD _OBT :2;\r
+    IO_LWORD _EP :4;\r
+    IO_LWORD _EM :2;\r
+    IO_LWORD _ER :2;\r
+  }bitc;\r
+ }BCR5STR;\r
+typedef union{  \r
+    IO_LWORD   lword;\r
+    struct{   \r
+    IO_LWORD  :1;\r
+    IO_LWORD  :1;\r
+    IO_LWORD  :1;\r
+    IO_LWORD  :1;\r
+    IO_LWORD  :1;\r
+    IO_LWORD  :1;\r
+    IO_LWORD  :1;\r
+    IO_LWORD  :1;\r
+    IO_LWORD _SRX1 :1;\r
+    IO_LWORD _SW1 :1;\r
+    IO_LWORD _SRX0 :1;\r
+    IO_LWORD _SW0 :1;\r
+    IO_LWORD _URX1 :1;\r
+    IO_LWORD _UW1 :1;\r
+    IO_LWORD _URX0 :1;\r
+    IO_LWORD _UW0 :1;\r
+    IO_LWORD _MPE :1;\r
+    IO_LWORD _COMB :1;\r
+    IO_LWORD _CTC1 :1;\r
+    IO_LWORD _CTC0 :1;\r
+    IO_LWORD _OBS1 :1;\r
+    IO_LWORD _OBS0 :1;\r
+    IO_LWORD _OBT1 :1;\r
+    IO_LWORD _OBT0 :1;\r
+    IO_LWORD _EP3 :1;\r
+    IO_LWORD _EP2 :1;\r
+    IO_LWORD _EP1 :1;\r
+    IO_LWORD _EP0 :1;\r
+    IO_LWORD _EM1 :1;\r
+    IO_LWORD _EM0 :1;\r
+    IO_LWORD _ER1 :1;\r
+    IO_LWORD _ER0 :1;\r
+  }bit;\r
+  struct{\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD _CTC :2;\r
+    IO_LWORD _OBS :2;\r
+    IO_LWORD _OBT :2;\r
+    IO_LWORD _EP :4;\r
+    IO_LWORD _EM :2;\r
+    IO_LWORD _ER :2;\r
+  }bitc;\r
+ }BCR6STR;\r
+typedef union{  \r
+    IO_LWORD   lword;\r
+    struct{   \r
+    IO_LWORD  :1;\r
+    IO_LWORD  :1;\r
+    IO_LWORD  :1;\r
+    IO_LWORD  :1;\r
+    IO_LWORD  :1;\r
+    IO_LWORD  :1;\r
+    IO_LWORD  :1;\r
+    IO_LWORD  :1;\r
+    IO_LWORD _SRX1 :1;\r
+    IO_LWORD _SW1 :1;\r
+    IO_LWORD _SRX0 :1;\r
+    IO_LWORD _SW0 :1;\r
+    IO_LWORD _URX1 :1;\r
+    IO_LWORD _UW1 :1;\r
+    IO_LWORD _URX0 :1;\r
+    IO_LWORD _UW0 :1;\r
+    IO_LWORD _MPE :1;\r
+    IO_LWORD _COMB :1;\r
+    IO_LWORD _CTC1 :1;\r
+    IO_LWORD _CTC0 :1;\r
+    IO_LWORD _OBS1 :1;\r
+    IO_LWORD _OBS0 :1;\r
+    IO_LWORD _OBT1 :1;\r
+    IO_LWORD _OBT0 :1;\r
+    IO_LWORD _EP3 :1;\r
+    IO_LWORD _EP2 :1;\r
+    IO_LWORD _EP1 :1;\r
+    IO_LWORD _EP0 :1;\r
+    IO_LWORD _EM1 :1;\r
+    IO_LWORD _EM0 :1;\r
+    IO_LWORD _ER1 :1;\r
+    IO_LWORD _ER0 :1;\r
+  }bit;\r
+  struct{\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD :1;\r
+    IO_LWORD _CTC :2;\r
+    IO_LWORD _OBS :2;\r
+    IO_LWORD _OBT :2;\r
+    IO_LWORD _EP :4;\r
+    IO_LWORD _EM :2;\r
+    IO_LWORD _ER :2;\r
+  }bitc;\r
+ }BCR7STR;\r
+\r
+/* C-DECLARATIONS */\r
+\r
+__IO_EXTERN __io PDR00STR pdr00;   /* Port Data Register */\r
+#define PDR00 pdr00.byte\r
+#define PDR00_D7 pdr00.bit._D7\r
+#define PDR00_D6 pdr00.bit._D6\r
+#define PDR00_D5 pdr00.bit._D5\r
+#define PDR00_D4 pdr00.bit._D4\r
+#define PDR00_D3 pdr00.bit._D3\r
+#define PDR00_D2 pdr00.bit._D2\r
+#define PDR00_D1 pdr00.bit._D1\r
+#define PDR00_D0 pdr00.bit._D0\r
+__IO_EXTERN __io PDR01STR pdr01;  \r
+#define PDR01 pdr01.byte\r
+#define PDR01_D7 pdr01.bit._D7\r
+#define PDR01_D6 pdr01.bit._D6\r
+#define PDR01_D5 pdr01.bit._D5\r
+#define PDR01_D4 pdr01.bit._D4\r
+#define PDR01_D3 pdr01.bit._D3\r
+#define PDR01_D2 pdr01.bit._D2\r
+#define PDR01_D1 pdr01.bit._D1\r
+#define PDR01_D0 pdr01.bit._D0\r
+__IO_EXTERN __io PDR02STR pdr02;  \r
+#define PDR02 pdr02.byte\r
+#define PDR02_D7 pdr02.bit._D7\r
+#define PDR02_D6 pdr02.bit._D6\r
+#define PDR02_D5 pdr02.bit._D5\r
+#define PDR02_D4 pdr02.bit._D4\r
+#define PDR02_D3 pdr02.bit._D3\r
+#define PDR02_D2 pdr02.bit._D2\r
+#define PDR02_D1 pdr02.bit._D1\r
+#define PDR02_D0 pdr02.bit._D0\r
+__IO_EXTERN __io PDR03STR pdr03;  \r
+#define PDR03 pdr03.byte\r
+#define PDR03_D7 pdr03.bit._D7\r
+#define PDR03_D6 pdr03.bit._D6\r
+#define PDR03_D5 pdr03.bit._D5\r
+#define PDR03_D4 pdr03.bit._D4\r
+#define PDR03_D3 pdr03.bit._D3\r
+#define PDR03_D2 pdr03.bit._D2\r
+#define PDR03_D1 pdr03.bit._D1\r
+#define PDR03_D0 pdr03.bit._D0\r
+__IO_EXTERN __io PDR04STR pdr04;  \r
+#define PDR04 pdr04.byte\r
+#define PDR04_D1 pdr04.bit._D1\r
+#define PDR04_D0 pdr04.bit._D0\r
+__IO_EXTERN __io PDR05STR pdr05;  \r
+#define PDR05 pdr05.byte\r
+#define PDR05_D7 pdr05.bit._D7\r
+#define PDR05_D6 pdr05.bit._D6\r
+#define PDR05_D5 pdr05.bit._D5\r
+#define PDR05_D4 pdr05.bit._D4\r
+#define PDR05_D3 pdr05.bit._D3\r
+#define PDR05_D2 pdr05.bit._D2\r
+#define PDR05_D1 pdr05.bit._D1\r
+#define PDR05_D0 pdr05.bit._D0\r
+__IO_EXTERN __io PDR06STR pdr06;  \r
+#define PDR06 pdr06.byte\r
+#define PDR06_D7 pdr06.bit._D7\r
+#define PDR06_D6 pdr06.bit._D6\r
+#define PDR06_D5 pdr06.bit._D5\r
+#define PDR06_D4 pdr06.bit._D4\r
+#define PDR06_D3 pdr06.bit._D3\r
+#define PDR06_D2 pdr06.bit._D2\r
+#define PDR06_D1 pdr06.bit._D1\r
+#define PDR06_D0 pdr06.bit._D0\r
+__IO_EXTERN __io PDR07STR pdr07;  \r
+#define PDR07 pdr07.byte\r
+#define PDR07_D7 pdr07.bit._D7\r
+#define PDR07_D6 pdr07.bit._D6\r
+#define PDR07_D5 pdr07.bit._D5\r
+#define PDR07_D4 pdr07.bit._D4\r
+#define PDR07_D3 pdr07.bit._D3\r
+#define PDR07_D2 pdr07.bit._D2\r
+#define PDR07_D1 pdr07.bit._D1\r
+#define PDR07_D0 pdr07.bit._D0\r
+__IO_EXTERN __io PDR08STR pdr08;  \r
+#define PDR08 pdr08.byte\r
+#define PDR08_D7 pdr08.bit._D7\r
+#define PDR08_D6 pdr08.bit._D6\r
+#define PDR08_D5 pdr08.bit._D5\r
+#define PDR08_D4 pdr08.bit._D4\r
+#define PDR08_D3 pdr08.bit._D3\r
+#define PDR08_D2 pdr08.bit._D2\r
+#define PDR08_D1 pdr08.bit._D1\r
+#define PDR08_D0 pdr08.bit._D0\r
+__IO_EXTERN __io PDR09STR pdr09;  \r
+#define PDR09 pdr09.byte\r
+#define PDR09_D7 pdr09.bit._D7\r
+#define PDR09_D6 pdr09.bit._D6\r
+#define PDR09_D3 pdr09.bit._D3\r
+#define PDR09_D2 pdr09.bit._D2\r
+#define PDR09_D1 pdr09.bit._D1\r
+#define PDR09_D0 pdr09.bit._D0\r
+__IO_EXTERN __io PDR10STR pdr10;  \r
+#define PDR10 pdr10.byte\r
+#define PDR10_D6 pdr10.bit._D6\r
+#define PDR10_D5 pdr10.bit._D5\r
+#define PDR10_D4 pdr10.bit._D4\r
+#define PDR10_D3 pdr10.bit._D3\r
+#define PDR10_D2 pdr10.bit._D2\r
+#define PDR10_D1 pdr10.bit._D1\r
+__IO_EXTERN __io PDR13STR pdr13;  \r
+#define PDR13 pdr13.byte\r
+#define PDR13_D2 pdr13.bit._D2\r
+#define PDR13_D1 pdr13.bit._D1\r
+#define PDR13_D0 pdr13.bit._D0\r
+__IO_EXTERN __io PDR14STR pdr14;  \r
+#define PDR14 pdr14.byte\r
+#define PDR14_D7 pdr14.bit._D7\r
+#define PDR14_D6 pdr14.bit._D6\r
+#define PDR14_D5 pdr14.bit._D5\r
+#define PDR14_D4 pdr14.bit._D4\r
+#define PDR14_D3 pdr14.bit._D3\r
+#define PDR14_D2 pdr14.bit._D2\r
+#define PDR14_D1 pdr14.bit._D1\r
+#define PDR14_D0 pdr14.bit._D0\r
+__IO_EXTERN __io PDR15STR pdr15;  \r
+#define PDR15 pdr15.byte\r
+#define PDR15_D3 pdr15.bit._D3\r
+#define PDR15_D2 pdr15.bit._D2\r
+#define PDR15_D1 pdr15.bit._D1\r
+#define PDR15_D0 pdr15.bit._D0\r
+__IO_EXTERN __io PDR16STR pdr16;  \r
+#define PDR16 pdr16.byte\r
+#define PDR16_D7 pdr16.bit._D7\r
+#define PDR16_D6 pdr16.bit._D6\r
+#define PDR16_D5 pdr16.bit._D5\r
+#define PDR16_D4 pdr16.bit._D4\r
+#define PDR16_D3 pdr16.bit._D3\r
+#define PDR16_D2 pdr16.bit._D2\r
+#define PDR16_D1 pdr16.bit._D1\r
+#define PDR16_D0 pdr16.bit._D0\r
+__IO_EXTERN __io PDR17STR pdr17;  \r
+#define PDR17 pdr17.byte\r
+#define PDR17_D7 pdr17.bit._D7\r
+#define PDR17_D6 pdr17.bit._D6\r
+#define PDR17_D5 pdr17.bit._D5\r
+#define PDR17_D4 pdr17.bit._D4\r
+__IO_EXTERN __io PDR18STR pdr18;  \r
+#define PDR18 pdr18.byte\r
+#define PDR18_D6 pdr18.bit._D6\r
+#define PDR18_D5 pdr18.bit._D5\r
+#define PDR18_D4 pdr18.bit._D4\r
+#define PDR18_D2 pdr18.bit._D2\r
+#define PDR18_D1 pdr18.bit._D1\r
+#define PDR18_D0 pdr18.bit._D0\r
+__IO_EXTERN __io PDR19STR pdr19;  \r
+#define PDR19 pdr19.byte\r
+#define PDR19_D6 pdr19.bit._D6\r
+#define PDR19_D5 pdr19.bit._D5\r
+#define PDR19_D4 pdr19.bit._D4\r
+#define PDR19_D2 pdr19.bit._D2\r
+#define PDR19_D1 pdr19.bit._D1\r
+#define PDR19_D0 pdr19.bit._D0\r
+__IO_EXTERN __io PDR20STR pdr20;  \r
+#define PDR20 pdr20.byte\r
+#define PDR20_D2 pdr20.bit._D2\r
+#define PDR20_D1 pdr20.bit._D1\r
+#define PDR20_D0 pdr20.bit._D0\r
+__IO_EXTERN __io PDR22STR pdr22;  \r
+#define PDR22 pdr22.byte\r
+#define PDR22_D5 pdr22.bit._D5\r
+#define PDR22_D4 pdr22.bit._D4\r
+#define PDR22_D2 pdr22.bit._D2\r
+#define PDR22_D0 pdr22.bit._D0\r
+__IO_EXTERN __io PDR23STR pdr23;  \r
+#define PDR23 pdr23.byte\r
+#define PDR23_D5 pdr23.bit._D5\r
+#define PDR23_D4 pdr23.bit._D4\r
+#define PDR23_D3 pdr23.bit._D3\r
+#define PDR23_D2 pdr23.bit._D2\r
+#define PDR23_D1 pdr23.bit._D1\r
+#define PDR23_D0 pdr23.bit._D0\r
+__IO_EXTERN __io PDR24STR pdr24;  \r
+#define PDR24 pdr24.byte\r
+#define PDR24_D7 pdr24.bit._D7\r
+#define PDR24_D6 pdr24.bit._D6\r
+#define PDR24_D5 pdr24.bit._D5\r
+#define PDR24_D4 pdr24.bit._D4\r
+#define PDR24_D3 pdr24.bit._D3\r
+#define PDR24_D2 pdr24.bit._D2\r
+#define PDR24_D1 pdr24.bit._D1\r
+#define PDR24_D0 pdr24.bit._D0\r
+__IO_EXTERN __io PDR25STR pdr25;  \r
+#define PDR25 pdr25.byte\r
+#define PDR25_D7 pdr25.bit._D7\r
+#define PDR25_D6 pdr25.bit._D6\r
+#define PDR25_D5 pdr25.bit._D5\r
+#define PDR25_D4 pdr25.bit._D4\r
+#define PDR25_D3 pdr25.bit._D3\r
+#define PDR25_D2 pdr25.bit._D2\r
+#define PDR25_D1 pdr25.bit._D1\r
+#define PDR25_D0 pdr25.bit._D0\r
+__IO_EXTERN __io PDR26STR pdr26;  \r
+#define PDR26 pdr26.byte\r
+#define PDR26_D7 pdr26.bit._D7\r
+#define PDR26_D6 pdr26.bit._D6\r
+#define PDR26_D5 pdr26.bit._D5\r
+#define PDR26_D4 pdr26.bit._D4\r
+#define PDR26_D3 pdr26.bit._D3\r
+#define PDR26_D2 pdr26.bit._D2\r
+#define PDR26_D1 pdr26.bit._D1\r
+#define PDR26_D0 pdr26.bit._D0\r
+__IO_EXTERN __io PDR27STR pdr27;  \r
+#define PDR27 pdr27.byte\r
+#define PDR27_D7 pdr27.bit._D7\r
+#define PDR27_D6 pdr27.bit._D6\r
+#define PDR27_D5 pdr27.bit._D5\r
+#define PDR27_D4 pdr27.bit._D4\r
+#define PDR27_D3 pdr27.bit._D3\r
+#define PDR27_D2 pdr27.bit._D2\r
+#define PDR27_D1 pdr27.bit._D1\r
+#define PDR27_D0 pdr27.bit._D0\r
+__IO_EXTERN __io PDR29STR pdr29;  \r
+#define PDR29 pdr29.byte\r
+#define PDR29_D7 pdr29.bit._D7\r
+#define PDR29_D6 pdr29.bit._D6\r
+#define PDR29_D5 pdr29.bit._D5\r
+#define PDR29_D4 pdr29.bit._D4\r
+#define PDR29_D3 pdr29.bit._D3\r
+#define PDR29_D2 pdr29.bit._D2\r
+#define PDR29_D1 pdr29.bit._D1\r
+#define PDR29_D0 pdr29.bit._D0\r
+__IO_EXTERN __io EIRR0STR eirr0;   /* External Interrupt 0-7 */\r
+#define EIRR0 eirr0.byte\r
+#define EIRR0_ER7 eirr0.bit._ER7\r
+#define EIRR0_ER6 eirr0.bit._ER6\r
+#define EIRR0_ER5 eirr0.bit._ER5\r
+#define EIRR0_ER4 eirr0.bit._ER4\r
+#define EIRR0_ER3 eirr0.bit._ER3\r
+#define EIRR0_ER2 eirr0.bit._ER2\r
+#define EIRR0_ER1 eirr0.bit._ER1\r
+#define EIRR0_ER0 eirr0.bit._ER0\r
+__IO_EXTERN __io ENIR0STR enir0;  \r
+#define ENIR0 enir0.byte\r
+#define ENIR0_EN7 enir0.bit._EN7\r
+#define ENIR0_EN6 enir0.bit._EN6\r
+#define ENIR0_EN5 enir0.bit._EN5\r
+#define ENIR0_EN4 enir0.bit._EN4\r
+#define ENIR0_EN3 enir0.bit._EN3\r
+#define ENIR0_EN2 enir0.bit._EN2\r
+#define ENIR0_EN1 enir0.bit._EN1\r
+#define ENIR0_EN0 enir0.bit._EN0\r
+__IO_EXTERN __io ELVR0STR elvr0;  \r
+#define ELVR0 elvr0.word\r
+#define ELVR0_LB7 elvr0.bit._LB7\r
+#define ELVR0_LA7 elvr0.bit._LA7\r
+#define ELVR0_LB6 elvr0.bit._LB6\r
+#define ELVR0_LA6 elvr0.bit._LA6\r
+#define ELVR0_LB5 elvr0.bit._LB5\r
+#define ELVR0_LA5 elvr0.bit._LA5\r
+#define ELVR0_LB4 elvr0.bit._LB4\r
+#define ELVR0_LA4 elvr0.bit._LA4\r
+#define ELVR0_LB3 elvr0.bit._LB3\r
+#define ELVR0_LA3 elvr0.bit._LA3\r
+#define ELVR0_LB2 elvr0.bit._LB2\r
+#define ELVR0_LA2 elvr0.bit._LA2\r
+#define ELVR0_LB1 elvr0.bit._LB1\r
+#define ELVR0_LA1 elvr0.bit._LA1\r
+#define ELVR0_LB0 elvr0.bit._LB0\r
+#define ELVR0_LA0 elvr0.bit._LA0\r
+__IO_EXTERN __io EIRR1STR eirr1;   /* External Interrupt 8-15 */\r
+#define EIRR1 eirr1.byte\r
+#define EIRR1_ER15 eirr1.bit._ER15\r
+#define EIRR1_ER14 eirr1.bit._ER14\r
+#define EIRR1_ER13 eirr1.bit._ER13\r
+#define EIRR1_ER12 eirr1.bit._ER12\r
+#define EIRR1_ER11 eirr1.bit._ER11\r
+#define EIRR1_ER10 eirr1.bit._ER10\r
+#define EIRR1_ER9 eirr1.bit._ER9\r
+#define EIRR1_ER8 eirr1.bit._ER8\r
+__IO_EXTERN __io ENIR1STR enir1;  \r
+#define ENIR1 enir1.byte\r
+#define ENIR1_EN15 enir1.bit._EN15\r
+#define ENIR1_EN14 enir1.bit._EN14\r
+#define ENIR1_EN13 enir1.bit._EN13\r
+#define ENIR1_EN12 enir1.bit._EN12\r
+#define ENIR1_EN11 enir1.bit._EN11\r
+#define ENIR1_EN10 enir1.bit._EN10\r
+#define ENIR1_EN9 enir1.bit._EN9\r
+#define ENIR1_EN8 enir1.bit._EN8\r
+__IO_EXTERN __io ELVR1STR elvr1;  \r
+#define ELVR1 elvr1.word\r
+#define ELVR1_LB15 elvr1.bit._LB15\r
+#define ELVR1_LA15 elvr1.bit._LA15\r
+#define ELVR1_LB14 elvr1.bit._LB14\r
+#define ELVR1_LA14 elvr1.bit._LA14\r
+#define ELVR1_LB13 elvr1.bit._LB13\r
+#define ELVR1_LA13 elvr1.bit._LA13\r
+#define ELVR1_LB12 elvr1.bit._LB12\r
+#define ELVR1_LA12 elvr1.bit._LA12\r
+#define ELVR1_LB11 elvr1.bit._LB11\r
+#define ELVR1_LA11 elvr1.bit._LA11\r
+#define ELVR1_LB10 elvr1.bit._LB10\r
+#define ELVR1_LA10 elvr1.bit._LA10\r
+#define ELVR1_LB9 elvr1.bit._LB9\r
+#define ELVR1_LA9 elvr1.bit._LA9\r
+#define ELVR1_LB8 elvr1.bit._LB8\r
+#define ELVR1_LA8 elvr1.bit._LA8\r
+__IO_EXTERN __io DICRSTR dicr;   /* DLYI/I-unit */\r
+#define DICR dicr.byte\r
+#define DICR_DLYI dicr.bit._DLYI\r
+__IO_EXTERN __io HRCLSTR hrcl;  \r
+#define HRCL hrcl.byte\r
+#define HRCL_MHALTI hrcl.bit._MHALTI\r
+#define HRCL_LVL4 hrcl.bit._LVL4\r
+#define HRCL_LVL3 hrcl.bit._LVL3\r
+#define HRCL_LVL2 hrcl.bit._LVL2\r
+#define HRCL_LVL1 hrcl.bit._LVL1\r
+#define HRCL_LVL0 hrcl.bit._LVL0\r
+#define HRCL_LVL hrcl.bitc._LVL\r
+__IO_EXTERN __io IO_WORD rbsync;   /* R-Bus Sync */\r
+#define RBSYNC rbsync\r
+__IO_EXTERN __io SCR02STR scr02;   /* USART (LIN) 2 */\r
+#define SCR02 scr02.byte\r
+#define SCR02_PEN scr02.bit._PEN\r
+#define SCR02_P scr02.bit._P\r
+#define SCR02_SBL scr02.bit._SBL\r
+#define SCR02_CL scr02.bit._CL\r
+#define SCR02_AD scr02.bit._AD\r
+#define SCR02_CRE scr02.bit._CRE\r
+#define SCR02_RXE scr02.bit._RXE\r
+#define SCR02_TXE scr02.bit._TXE\r
+__IO_EXTERN __io SMR02STR smr02;  \r
+#define SMR02 smr02.byte\r
+#define SMR02_MD1 smr02.bit._MD1\r
+#define SMR02_MD0 smr02.bit._MD0\r
+#define SMR02_OTO smr02.bit._OTO\r
+#define SMR02_EXT smr02.bit._EXT\r
+#define SMR02_REST smr02.bit._REST\r
+#define SMR02_UPCL smr02.bit._UPCL\r
+#define SMR02_SCKE smr02.bit._SCKE\r
+#define SMR02_SOE smr02.bit._SOE\r
+#define SMR02_MD smr02.bitc._MD\r
+__IO_EXTERN __io SSR02STR ssr02;  \r
+#define SSR02 ssr02.byte\r
+#define SSR02_PE ssr02.bit._PE\r
+#define SSR02_ORE ssr02.bit._ORE\r
+#define SSR02_FRE ssr02.bit._FRE\r
+#define SSR02_RDRF ssr02.bit._RDRF\r
+#define SSR02_TDRE ssr02.bit._TDRE\r
+#define SSR02_BDS ssr02.bit._BDS\r
+#define SSR02_RIE ssr02.bit._RIE\r
+#define SSR02_TIE ssr02.bit._TIE\r
+__IO_EXTERN __io IO_BYTE rdr02;  \r
+#define RDR02 rdr02\r
+__IO_EXTERN __io IO_BYTE tdr02;  \r
+#define TDR02 tdr02\r
+__IO_EXTERN __io ESCR02STR escr02;  \r
+#define ESCR02 escr02.byte\r
+#define ESCR02_LBIE escr02.bit._LBIE\r
+#define ESCR02_LBD escr02.bit._LBD\r
+#define ESCR02_LBL1 escr02.bit._LBL1\r
+#define ESCR02_LBL0 escr02.bit._LBL0\r
+#define ESCR02_SOPE escr02.bit._SOPE\r
+#define ESCR02_SIOP escr02.bit._SIOP\r
+#define ESCR02_CCO escr02.bit._CCO\r
+#define ESCR02_SCES escr02.bit._SCES\r
+#define ESCR02_LBL escr02.bitc._LBL\r
+__IO_EXTERN __io ECCR02STR eccr02;  \r
+#define ECCR02 eccr02.byte\r
+#define ECCR02_INV eccr02.bit._INV\r
+#define ECCR02_LBR eccr02.bit._LBR\r
+#define ECCR02_MS eccr02.bit._MS\r
+#define ECCR02_SCDE eccr02.bit._SCDE\r
+#define ECCR02_SSM eccr02.bit._SSM\r
+#define ECCR02_BIE eccr02.bit._BIE\r
+#define ECCR02_RBI eccr02.bit._RBI\r
+#define ECCR02_TBI eccr02.bit._TBI\r
+__IO_EXTERN __io SCR04STR scr04;   /* USART (LIN) 4 with FIFO */\r
+#define SCR04 scr04.byte\r
+#define SCR04_PEN scr04.bit._PEN\r
+#define SCR04_P scr04.bit._P\r
+#define SCR04_SBL scr04.bit._SBL\r
+#define SCR04_CL scr04.bit._CL\r
+#define SCR04_AD scr04.bit._AD\r
+#define SCR04_CRE scr04.bit._CRE\r
+#define SCR04_RXE scr04.bit._RXE\r
+#define SCR04_TXE scr04.bit._TXE\r
+__IO_EXTERN __io SMR04STR smr04;  \r
+#define SMR04 smr04.byte\r
+#define SMR04_MD1 smr04.bit._MD1\r
+#define SMR04_MD0 smr04.bit._MD0\r
+#define SMR04_OTO smr04.bit._OTO\r
+#define SMR04_EXT smr04.bit._EXT\r
+#define SMR04_REST smr04.bit._REST\r
+#define SMR04_UPCL smr04.bit._UPCL\r
+#define SMR04_SCKE smr04.bit._SCKE\r
+#define SMR04_SOE smr04.bit._SOE\r
+#define SMR04_MD smr04.bitc._MD\r
+__IO_EXTERN __io SSR04STR ssr04;  \r
+#define SSR04 ssr04.byte\r
+#define SSR04_PE ssr04.bit._PE\r
+#define SSR04_ORE ssr04.bit._ORE\r
+#define SSR04_FRE ssr04.bit._FRE\r
+#define SSR04_RDRF ssr04.bit._RDRF\r
+#define SSR04_TDRE ssr04.bit._TDRE\r
+#define SSR04_BDS ssr04.bit._BDS\r
+#define SSR04_RIE ssr04.bit._RIE\r
+#define SSR04_TIE ssr04.bit._TIE\r
+__IO_EXTERN __io IO_BYTE rdr04;  \r
+#define RDR04 rdr04\r
+__IO_EXTERN __io IO_BYTE tdr04;  \r
+#define TDR04 tdr04\r
+__IO_EXTERN __io ESCR04STR escr04;  \r
+#define ESCR04 escr04.byte\r
+#define ESCR04_LBIE escr04.bit._LBIE\r
+#define ESCR04_LBD escr04.bit._LBD\r
+#define ESCR04_LBL1 escr04.bit._LBL1\r
+#define ESCR04_LBL0 escr04.bit._LBL0\r
+#define ESCR04_SOPE escr04.bit._SOPE\r
+#define ESCR04_SIOP escr04.bit._SIOP\r
+#define ESCR04_CCO escr04.bit._CCO\r
+#define ESCR04_SCES escr04.bit._SCES\r
+#define ESCR04_LBL escr04.bitc._LBL\r
+__IO_EXTERN __io ECCR04STR eccr04;  \r
+#define ECCR04 eccr04.byte\r
+#define ECCR04_INV eccr04.bit._INV\r
+#define ECCR04_LBR eccr04.bit._LBR\r
+#define ECCR04_MS eccr04.bit._MS\r
+#define ECCR04_SCDE eccr04.bit._SCDE\r
+#define ECCR04_SSM eccr04.bit._SSM\r
+#define ECCR04_BIE eccr04.bit._BIE\r
+#define ECCR04_RBI eccr04.bit._RBI\r
+#define ECCR04_TBI eccr04.bit._TBI\r
+__IO_EXTERN __io IO_BYTE fsr04;  \r
+#define FSR04 fsr04\r
+__IO_EXTERN __io FCR04STR fcr04;  \r
+#define FCR04 fcr04.byte\r
+#define FCR04_RXL3 fcr04.bit._RXL3\r
+#define FCR04_RXL2 fcr04.bit._RXL2\r
+#define FCR04_RXL1 fcr04.bit._RXL1\r
+#define FCR04_RXL0 fcr04.bit._RXL0\r
+#define FCR04_ERX fcr04.bit._ERX\r
+#define FCR04_ETX fcr04.bit._ETX\r
+#define FCR04_SVD fcr04.bit._SVD\r
+#define FCR04_RXL fcr04.bitc._RXL\r
+__IO_EXTERN __io SCR05STR scr05;   /* USART (LIN) 5 with FIFO */\r
+#define SCR05 scr05.byte\r
+#define SCR05_PEN scr05.bit._PEN\r
+#define SCR05_P scr05.bit._P\r
+#define SCR05_SBL scr05.bit._SBL\r
+#define SCR05_CL scr05.bit._CL\r
+#define SCR05_AD scr05.bit._AD\r
+#define SCR05_CRE scr05.bit._CRE\r
+#define SCR05_RXE scr05.bit._RXE\r
+#define SCR05_TXE scr05.bit._TXE\r
+__IO_EXTERN __io SMR05STR smr05;  \r
+#define SMR05 smr05.byte\r
+#define SMR05_MD1 smr05.bit._MD1\r
+#define SMR05_MD0 smr05.bit._MD0\r
+#define SMR05_OTO smr05.bit._OTO\r
+#define SMR05_EXT smr05.bit._EXT\r
+#define SMR05_REST smr05.bit._REST\r
+#define SMR05_UPCL smr05.bit._UPCL\r
+#define SMR05_SCKE smr05.bit._SCKE\r
+#define SMR05_SOE smr05.bit._SOE\r
+#define SMR05_MD smr05.bitc._MD\r
+__IO_EXTERN __io SSR05STR ssr05;  \r
+#define SSR05 ssr05.byte\r
+#define SSR05_PE ssr05.bit._PE\r
+#define SSR05_ORE ssr05.bit._ORE\r
+#define SSR05_FRE ssr05.bit._FRE\r
+#define SSR05_RDRF ssr05.bit._RDRF\r
+#define SSR05_TDRE ssr05.bit._TDRE\r
+#define SSR05_BDS ssr05.bit._BDS\r
+#define SSR05_RIE ssr05.bit._RIE\r
+#define SSR05_TIE ssr05.bit._TIE\r
+__IO_EXTERN __io IO_BYTE rdr05;  \r
+#define RDR05 rdr05\r
+__IO_EXTERN __io IO_BYTE tdr05;  \r
+#define TDR05 tdr05\r
+__IO_EXTERN __io ESCR05STR escr05;  \r
+#define ESCR05 escr05.byte\r
+#define ESCR05_LBIE escr05.bit._LBIE\r
+#define ESCR05_LBD escr05.bit._LBD\r
+#define ESCR05_LBL1 escr05.bit._LBL1\r
+#define ESCR05_LBL0 escr05.bit._LBL0\r
+#define ESCR05_SOPE escr05.bit._SOPE\r
+#define ESCR05_SIOP escr05.bit._SIOP\r
+#define ESCR05_CCO escr05.bit._CCO\r
+#define ESCR05_SCES escr05.bit._SCES\r
+#define ESCR05_LBL escr05.bitc._LBL\r
+__IO_EXTERN __io ECCR05STR eccr05;  \r
+#define ECCR05 eccr05.byte\r
+#define ECCR05_INV eccr05.bit._INV\r
+#define ECCR05_LBR eccr05.bit._LBR\r
+#define ECCR05_MS eccr05.bit._MS\r
+#define ECCR05_SCDE eccr05.bit._SCDE\r
+#define ECCR05_SSM eccr05.bit._SSM\r
+#define ECCR05_BIE eccr05.bit._BIE\r
+#define ECCR05_RBI eccr05.bit._RBI\r
+#define ECCR05_TBI eccr05.bit._TBI\r
+__IO_EXTERN __io IO_BYTE fsr05;  \r
+#define FSR05 fsr05\r
+__IO_EXTERN __io FCR05STR fcr05;  \r
+#define FCR05 fcr05.byte\r
+#define FCR05_RXL3 fcr05.bit._RXL3\r
+#define FCR05_RXL2 fcr05.bit._RXL2\r
+#define FCR05_RXL1 fcr05.bit._RXL1\r
+#define FCR05_RXL0 fcr05.bit._RXL0\r
+#define FCR05_ERX fcr05.bit._ERX\r
+#define FCR05_ETX fcr05.bit._ETX\r
+#define FCR05_SVD fcr05.bit._SVD\r
+#define FCR05_RXL fcr05.bitc._RXL\r
+__IO_EXTERN __io SCR06STR scr06;   /* USART (LIN) 6 with FIFO */\r
+#define SCR06 scr06.byte\r
+#define SCR06_PEN scr06.bit._PEN\r
+#define SCR06_P scr06.bit._P\r
+#define SCR06_SBL scr06.bit._SBL\r
+#define SCR06_CL scr06.bit._CL\r
+#define SCR06_AD scr06.bit._AD\r
+#define SCR06_CRE scr06.bit._CRE\r
+#define SCR06_RXE scr06.bit._RXE\r
+#define SCR06_TXE scr06.bit._TXE\r
+__IO_EXTERN __io SMR06STR smr06;  \r
+#define SMR06 smr06.byte\r
+#define SMR06_MD1 smr06.bit._MD1\r
+#define SMR06_MD0 smr06.bit._MD0\r
+#define SMR06_OTO smr06.bit._OTO\r
+#define SMR06_EXT smr06.bit._EXT\r
+#define SMR06_REST smr06.bit._REST\r
+#define SMR06_UPCL smr06.bit._UPCL\r
+#define SMR06_SCKE smr06.bit._SCKE\r
+#define SMR06_SOE smr06.bit._SOE\r
+#define SMR06_MD smr06.bitc._MD\r
+__IO_EXTERN __io SSR06STR ssr06;  \r
+#define SSR06 ssr06.byte\r
+#define SSR06_PE ssr06.bit._PE\r
+#define SSR06_ORE ssr06.bit._ORE\r
+#define SSR06_FRE ssr06.bit._FRE\r
+#define SSR06_RDRF ssr06.bit._RDRF\r
+#define SSR06_TDRE ssr06.bit._TDRE\r
+#define SSR06_BDS ssr06.bit._BDS\r
+#define SSR06_RIE ssr06.bit._RIE\r
+#define SSR06_TIE ssr06.bit._TIE\r
+__IO_EXTERN __io IO_BYTE rdr06;  \r
+#define RDR06 rdr06\r
+__IO_EXTERN __io IO_BYTE tdr06;  \r
+#define TDR06 tdr06\r
+__IO_EXTERN __io ESCR06STR escr06;  \r
+#define ESCR06 escr06.byte\r
+#define ESCR06_LBIE escr06.bit._LBIE\r
+#define ESCR06_LBD escr06.bit._LBD\r
+#define ESCR06_LBL1 escr06.bit._LBL1\r
+#define ESCR06_LBL0 escr06.bit._LBL0\r
+#define ESCR06_SOPE escr06.bit._SOPE\r
+#define ESCR06_SIOP escr06.bit._SIOP\r
+#define ESCR06_CCO escr06.bit._CCO\r
+#define ESCR06_SCES escr06.bit._SCES\r
+#define ESCR06_LBL escr06.bitc._LBL\r
+__IO_EXTERN __io ECCR06STR eccr06;  \r
+#define ECCR06 eccr06.byte\r
+#define ECCR06_INV eccr06.bit._INV\r
+#define ECCR06_LBR eccr06.bit._LBR\r
+#define ECCR06_MS eccr06.bit._MS\r
+#define ECCR06_SCDE eccr06.bit._SCDE\r
+#define ECCR06_SSM eccr06.bit._SSM\r
+#define ECCR06_BIE eccr06.bit._BIE\r
+#define ECCR06_RBI eccr06.bit._RBI\r
+#define ECCR06_TBI eccr06.bit._TBI\r
+__IO_EXTERN __io IO_BYTE fsr06;  \r
+#define FSR06 fsr06\r
+__IO_EXTERN __io FCR06STR fcr06;  \r
+#define FCR06 fcr06.byte\r
+#define FCR06_RXL3 fcr06.bit._RXL3\r
+#define FCR06_RXL2 fcr06.bit._RXL2\r
+#define FCR06_RXL1 fcr06.bit._RXL1\r
+#define FCR06_RXL0 fcr06.bit._RXL0\r
+#define FCR06_ERX fcr06.bit._ERX\r
+#define FCR06_ETX fcr06.bit._ETX\r
+#define FCR06_SVD fcr06.bit._SVD\r
+#define FCR06_RXL fcr06.bitc._RXL\r
+__IO_EXTERN __io SCR07STR scr07;   /* USART (LIN) 7 with FIFO */\r
+#define SCR07 scr07.byte\r
+#define SCR07_PEN scr07.bit._PEN\r
+#define SCR07_P scr07.bit._P\r
+#define SCR07_SBL scr07.bit._SBL\r
+#define SCR07_CL scr07.bit._CL\r
+#define SCR07_AD scr07.bit._AD\r
+#define SCR07_CRE scr07.bit._CRE\r
+#define SCR07_RXE scr07.bit._RXE\r
+#define SCR07_TXE scr07.bit._TXE\r
+__IO_EXTERN __io SMR07STR smr07;  \r
+#define SMR07 smr07.byte\r
+#define SMR07_MD1 smr07.bit._MD1\r
+#define SMR07_MD0 smr07.bit._MD0\r
+#define SMR07_OTO smr07.bit._OTO\r
+#define SMR07_EXT smr07.bit._EXT\r
+#define SMR07_REST smr07.bit._REST\r
+#define SMR07_UPCL smr07.bit._UPCL\r
+#define SMR07_SCKE smr07.bit._SCKE\r
+#define SMR07_SOE smr07.bit._SOE\r
+#define SMR07_MD smr07.bitc._MD\r
+__IO_EXTERN __io SSR07STR ssr07;  \r
+#define SSR07 ssr07.byte\r
+#define SSR07_PE ssr07.bit._PE\r
+#define SSR07_ORE ssr07.bit._ORE\r
+#define SSR07_FRE ssr07.bit._FRE\r
+#define SSR07_RDRF ssr07.bit._RDRF\r
+#define SSR07_TDRE ssr07.bit._TDRE\r
+#define SSR07_BDS ssr07.bit._BDS\r
+#define SSR07_RIE ssr07.bit._RIE\r
+#define SSR07_TIE ssr07.bit._TIE\r
+__IO_EXTERN __io IO_BYTE rdr07;  \r
+#define RDR07 rdr07\r
+__IO_EXTERN __io IO_BYTE tdr07;  \r
+#define TDR07 tdr07\r
+__IO_EXTERN __io ESCR07STR escr07;  \r
+#define ESCR07 escr07.byte\r
+#define ESCR07_LBIE escr07.bit._LBIE\r
+#define ESCR07_LBD escr07.bit._LBD\r
+#define ESCR07_LBL1 escr07.bit._LBL1\r
+#define ESCR07_LBL0 escr07.bit._LBL0\r
+#define ESCR07_SOPE escr07.bit._SOPE\r
+#define ESCR07_SIOP escr07.bit._SIOP\r
+#define ESCR07_CCO escr07.bit._CCO\r
+#define ESCR07_SCES escr07.bit._SCES\r
+#define ESCR07_LBL escr07.bitc._LBL\r
+__IO_EXTERN __io ECCR07STR eccr07;  \r
+#define ECCR07 eccr07.byte\r
+#define ECCR07_INV eccr07.bit._INV\r
+#define ECCR07_LBR eccr07.bit._LBR\r
+#define ECCR07_MS eccr07.bit._MS\r
+#define ECCR07_SCDE eccr07.bit._SCDE\r
+#define ECCR07_SSM eccr07.bit._SSM\r
+#define ECCR07_BIE eccr07.bit._BIE\r
+#define ECCR07_RBI eccr07.bit._RBI\r
+#define ECCR07_TBI eccr07.bit._TBI\r
+__IO_EXTERN __io IO_BYTE fsr07;  \r
+#define FSR07 fsr07\r
+__IO_EXTERN __io FCR07STR fcr07;  \r
+#define FCR07 fcr07.byte\r
+#define FCR07_RXL3 fcr07.bit._RXL3\r
+#define FCR07_RXL2 fcr07.bit._RXL2\r
+#define FCR07_RXL1 fcr07.bit._RXL1\r
+#define FCR07_RXL0 fcr07.bit._RXL0\r
+#define FCR07_ERX fcr07.bit._ERX\r
+#define FCR07_ETX fcr07.bit._ETX\r
+#define FCR07_SVD fcr07.bit._SVD\r
+#define FCR07_RXL fcr07.bitc._RXL\r
+__IO_EXTERN __io IO_WORD bgr02;   /* Bauderate Generator USART (LIN) 2,4-7 */\r
+#define BGR02 bgr02\r
+__IO_EXTERN __io IO_BYTE bgr102;  \r
+#define BGR102 bgr102\r
+__IO_EXTERN __io IO_BYTE bgr002;  \r
+#define BGR002 bgr002\r
+__IO_EXTERN __io IO_WORD bgr04;  \r
+#define BGR04 bgr04\r
+__IO_EXTERN __io IO_BYTE bgr104;  \r
+#define BGR104 bgr104\r
+__IO_EXTERN __io IO_BYTE bgr004;  \r
+#define BGR004 bgr004\r
+__IO_EXTERN __io IO_WORD bgr05;  \r
+#define BGR05 bgr05\r
+__IO_EXTERN __io IO_BYTE bgr105;  \r
+#define BGR105 bgr105\r
+__IO_EXTERN __io IO_BYTE bgr005;  \r
+#define BGR005 bgr005\r
+__IO_EXTERN __io IO_WORD bgr06;  \r
+#define BGR06 bgr06\r
+__IO_EXTERN __io IO_BYTE bgr106;  \r
+#define BGR106 bgr106\r
+__IO_EXTERN __io IO_BYTE bgr006;  \r
+#define BGR006 bgr006\r
+__IO_EXTERN __io IO_WORD bgr07;  \r
+#define BGR07 bgr07\r
+__IO_EXTERN __io IO_BYTE bgr107;  \r
+#define BGR107 bgr107\r
+__IO_EXTERN __io IO_BYTE bgr007;  \r
+#define BGR007 bgr007\r
+__IO_EXTERN __io PWC20STR pwc20;   /* Stepper Motor 0 */\r
+#define PWC20 pwc20.word\r
+#define PWC20_D9 pwc20.bit._D9\r
+#define PWC20_D8 pwc20.bit._D8\r
+#define PWC20_D7 pwc20.bit._D7\r
+#define PWC20_D6 pwc20.bit._D6\r
+#define PWC20_D5 pwc20.bit._D5\r
+#define PWC20_D4 pwc20.bit._D4\r
+#define PWC20_D3 pwc20.bit._D3\r
+#define PWC20_D2 pwc20.bit._D2\r
+#define PWC20_D1 pwc20.bit._D1\r
+#define PWC20_D0 pwc20.bit._D0\r
+__IO_EXTERN __io PWC10STR pwc10;  \r
+#define PWC10 pwc10.word\r
+#define PWC10_D9 pwc10.bit._D9\r
+#define PWC10_D8 pwc10.bit._D8\r
+#define PWC10_D7 pwc10.bit._D7\r
+#define PWC10_D6 pwc10.bit._D6\r
+#define PWC10_D5 pwc10.bit._D5\r
+#define PWC10_D4 pwc10.bit._D4\r
+#define PWC10_D3 pwc10.bit._D3\r
+#define PWC10_D2 pwc10.bit._D2\r
+#define PWC10_D1 pwc10.bit._D1\r
+#define PWC10_D0 pwc10.bit._D0\r
+__IO_EXTERN __io PWS20STR pws20;  \r
+#define PWS20 pws20.byte\r
+#define PWS20_BS pws20.bit._BS\r
+#define PWS20_P2 pws20.bit._P2\r
+#define PWS20_P1 pws20.bit._P1\r
+#define PWS20_P0 pws20.bit._P0\r
+#define PWS20_M2 pws20.bit._M2\r
+#define PWS20_M1 pws20.bit._M1\r
+#define PWS20_M0 pws20.bit._M0\r
+#define PWS20_P pws20.bitc._P\r
+#define PWS20_M pws20.bitc._M\r
+__IO_EXTERN __io PWS10STR pws10;  \r
+#define PWS10 pws10.byte\r
+#define PWS10_P2 pws10.bit._P2\r
+#define PWS10_P1 pws10.bit._P1\r
+#define PWS10_P0 pws10.bit._P0\r
+#define PWS10_M2 pws10.bit._M2\r
+#define PWS10_M1 pws10.bit._M1\r
+#define PWS10_M0 pws10.bit._M0\r
+#define PWS10_P pws10.bitc._P\r
+#define PWS10_M pws10.bitc._M\r
+__IO_EXTERN __io PWC21STR pwc21;   /* Stepper Motor 1 */\r
+#define PWC21 pwc21.word\r
+#define PWC21_D9 pwc21.bit._D9\r
+#define PWC21_D8 pwc21.bit._D8\r
+#define PWC21_D7 pwc21.bit._D7\r
+#define PWC21_D6 pwc21.bit._D6\r
+#define PWC21_D5 pwc21.bit._D5\r
+#define PWC21_D4 pwc21.bit._D4\r
+#define PWC21_D3 pwc21.bit._D3\r
+#define PWC21_D2 pwc21.bit._D2\r
+#define PWC21_D1 pwc21.bit._D1\r
+#define PWC21_D0 pwc21.bit._D0\r
+__IO_EXTERN __io PWC11STR pwc11;  \r
+#define PWC11 pwc11.word\r
+#define PWC11_D9 pwc11.bit._D9\r
+#define PWC11_D8 pwc11.bit._D8\r
+#define PWC11_D7 pwc11.bit._D7\r
+#define PWC11_D6 pwc11.bit._D6\r
+#define PWC11_D5 pwc11.bit._D5\r
+#define PWC11_D4 pwc11.bit._D4\r
+#define PWC11_D3 pwc11.bit._D3\r
+#define PWC11_D2 pwc11.bit._D2\r
+#define PWC11_D1 pwc11.bit._D1\r
+#define PWC11_D0 pwc11.bit._D0\r
+__IO_EXTERN __io PWS21STR pws21;  \r
+#define PWS21 pws21.byte\r
+#define PWS21_BS pws21.bit._BS\r
+#define PWS21_P2 pws21.bit._P2\r
+#define PWS21_P1 pws21.bit._P1\r
+#define PWS21_P0 pws21.bit._P0\r
+#define PWS21_M2 pws21.bit._M2\r
+#define PWS21_M1 pws21.bit._M1\r
+#define PWS21_M0 pws21.bit._M0\r
+#define PWS21_P pws21.bitc._P\r
+#define PWS21_M pws21.bitc._M\r
+__IO_EXTERN __io PWS11STR pws11;  \r
+#define PWS11 pws11.byte\r
+#define PWS11_P2 pws11.bit._P2\r
+#define PWS11_P1 pws11.bit._P1\r
+#define PWS11_P0 pws11.bit._P0\r
+#define PWS11_M2 pws11.bit._M2\r
+#define PWS11_M1 pws11.bit._M1\r
+#define PWS11_M0 pws11.bit._M0\r
+#define PWS11_P pws11.bitc._P\r
+#define PWS11_M pws11.bitc._M\r
+__IO_EXTERN __io PWC22STR pwc22;   /* Stepper Motor 2 */\r
+#define PWC22 pwc22.word\r
+#define PWC22_D9 pwc22.bit._D9\r
+#define PWC22_D8 pwc22.bit._D8\r
+#define PWC22_D7 pwc22.bit._D7\r
+#define PWC22_D6 pwc22.bit._D6\r
+#define PWC22_D5 pwc22.bit._D5\r
+#define PWC22_D4 pwc22.bit._D4\r
+#define PWC22_D3 pwc22.bit._D3\r
+#define PWC22_D2 pwc22.bit._D2\r
+#define PWC22_D1 pwc22.bit._D1\r
+#define PWC22_D0 pwc22.bit._D0\r
+__IO_EXTERN __io PWC12STR pwc12;  \r
+#define PWC12 pwc12.word\r
+#define PWC12_D9 pwc12.bit._D9\r
+#define PWC12_D8 pwc12.bit._D8\r
+#define PWC12_D7 pwc12.bit._D7\r
+#define PWC12_D6 pwc12.bit._D6\r
+#define PWC12_D5 pwc12.bit._D5\r
+#define PWC12_D4 pwc12.bit._D4\r
+#define PWC12_D3 pwc12.bit._D3\r
+#define PWC12_D2 pwc12.bit._D2\r
+#define PWC12_D1 pwc12.bit._D1\r
+#define PWC12_D0 pwc12.bit._D0\r
+__IO_EXTERN __io PWS22STR pws22;  \r
+#define PWS22 pws22.byte\r
+#define PWS22_BS pws22.bit._BS\r
+#define PWS22_P2 pws22.bit._P2\r
+#define PWS22_P1 pws22.bit._P1\r
+#define PWS22_P0 pws22.bit._P0\r
+#define PWS22_M2 pws22.bit._M2\r
+#define PWS22_M1 pws22.bit._M1\r
+#define PWS22_M0 pws22.bit._M0\r
+#define PWS22_P pws22.bitc._P\r
+#define PWS22_M pws22.bitc._M\r
+__IO_EXTERN __io PWS12STR pws12;  \r
+#define PWS12 pws12.byte\r
+#define PWS12_P2 pws12.bit._P2\r
+#define PWS12_P1 pws12.bit._P1\r
+#define PWS12_P0 pws12.bit._P0\r
+#define PWS12_M2 pws12.bit._M2\r
+#define PWS12_M1 pws12.bit._M1\r
+#define PWS12_M0 pws12.bit._M0\r
+#define PWS12_P pws12.bitc._P\r
+#define PWS12_M pws12.bitc._M\r
+__IO_EXTERN __io PWC23STR pwc23;   /* Stepper Motor 3 */\r
+#define PWC23 pwc23.word\r
+#define PWC23_D9 pwc23.bit._D9\r
+#define PWC23_D8 pwc23.bit._D8\r
+#define PWC23_D7 pwc23.bit._D7\r
+#define PWC23_D6 pwc23.bit._D6\r
+#define PWC23_D5 pwc23.bit._D5\r
+#define PWC23_D4 pwc23.bit._D4\r
+#define PWC23_D3 pwc23.bit._D3\r
+#define PWC23_D2 pwc23.bit._D2\r
+#define PWC23_D1 pwc23.bit._D1\r
+#define PWC23_D0 pwc23.bit._D0\r
+__IO_EXTERN __io PWC13STR pwc13;  \r
+#define PWC13 pwc13.word\r
+#define PWC13_D9 pwc13.bit._D9\r
+#define PWC13_D8 pwc13.bit._D8\r
+#define PWC13_D7 pwc13.bit._D7\r
+#define PWC13_D6 pwc13.bit._D6\r
+#define PWC13_D5 pwc13.bit._D5\r
+#define PWC13_D4 pwc13.bit._D4\r
+#define PWC13_D3 pwc13.bit._D3\r
+#define PWC13_D2 pwc13.bit._D2\r
+#define PWC13_D1 pwc13.bit._D1\r
+#define PWC13_D0 pwc13.bit._D0\r
+__IO_EXTERN __io PWS23STR pws23;  \r
+#define PWS23 pws23.byte\r
+#define PWS23_BS pws23.bit._BS\r
+#define PWS23_P2 pws23.bit._P2\r
+#define PWS23_P1 pws23.bit._P1\r
+#define PWS23_P0 pws23.bit._P0\r
+#define PWS23_M2 pws23.bit._M2\r
+#define PWS23_M1 pws23.bit._M1\r
+#define PWS23_M0 pws23.bit._M0\r
+#define PWS23_P pws23.bitc._P\r
+#define PWS23_M pws23.bitc._M\r
+__IO_EXTERN __io PWS13STR pws13;  \r
+#define PWS13 pws13.byte\r
+#define PWS13_P2 pws13.bit._P2\r
+#define PWS13_P1 pws13.bit._P1\r
+#define PWS13_P0 pws13.bit._P0\r
+#define PWS13_M2 pws13.bit._M2\r
+#define PWS13_M1 pws13.bit._M1\r
+#define PWS13_M0 pws13.bit._M0\r
+#define PWS13_P pws13.bitc._P\r
+#define PWS13_M pws13.bitc._M\r
+__IO_EXTERN __io PWC24STR pwc24;   /* Stepper Motor 4 */\r
+#define PWC24 pwc24.word\r
+#define PWC24_D9 pwc24.bit._D9\r
+#define PWC24_D8 pwc24.bit._D8\r
+#define PWC24_D7 pwc24.bit._D7\r
+#define PWC24_D6 pwc24.bit._D6\r
+#define PWC24_D5 pwc24.bit._D5\r
+#define PWC24_D4 pwc24.bit._D4\r
+#define PWC24_D3 pwc24.bit._D3\r
+#define PWC24_D2 pwc24.bit._D2\r
+#define PWC24_D1 pwc24.bit._D1\r
+#define PWC24_D0 pwc24.bit._D0\r
+__IO_EXTERN __io PWC14STR pwc14;  \r
+#define PWC14 pwc14.word\r
+#define PWC14_D9 pwc14.bit._D9\r
+#define PWC14_D8 pwc14.bit._D8\r
+#define PWC14_D7 pwc14.bit._D7\r
+#define PWC14_D6 pwc14.bit._D6\r
+#define PWC14_D5 pwc14.bit._D5\r
+#define PWC14_D4 pwc14.bit._D4\r
+#define PWC14_D3 pwc14.bit._D3\r
+#define PWC14_D2 pwc14.bit._D2\r
+#define PWC14_D1 pwc14.bit._D1\r
+#define PWC14_D0 pwc14.bit._D0\r
+__IO_EXTERN __io PWS24STR pws24;  \r
+#define PWS24 pws24.byte\r
+#define PWS24_BS pws24.bit._BS\r
+#define PWS24_P2 pws24.bit._P2\r
+#define PWS24_P1 pws24.bit._P1\r
+#define PWS24_P0 pws24.bit._P0\r
+#define PWS24_M2 pws24.bit._M2\r
+#define PWS24_M1 pws24.bit._M1\r
+#define PWS24_M0 pws24.bit._M0\r
+#define PWS24_P pws24.bitc._P\r
+#define PWS24_M pws24.bitc._M\r
+__IO_EXTERN __io PWS14STR pws14;  \r
+#define PWS14 pws14.byte\r
+#define PWS14_P2 pws14.bit._P2\r
+#define PWS14_P1 pws14.bit._P1\r
+#define PWS14_P0 pws14.bit._P0\r
+#define PWS14_M2 pws14.bit._M2\r
+#define PWS14_M1 pws14.bit._M1\r
+#define PWS14_M0 pws14.bit._M0\r
+#define PWS14_P pws14.bitc._P\r
+#define PWS14_M pws14.bitc._M\r
+__IO_EXTERN __io PWC25STR pwc25;   /* Stepper Motor 5 */\r
+#define PWC25 pwc25.word\r
+#define PWC25_D9 pwc25.bit._D9\r
+#define PWC25_D8 pwc25.bit._D8\r
+#define PWC25_D7 pwc25.bit._D7\r
+#define PWC25_D6 pwc25.bit._D6\r
+#define PWC25_D5 pwc25.bit._D5\r
+#define PWC25_D4 pwc25.bit._D4\r
+#define PWC25_D3 pwc25.bit._D3\r
+#define PWC25_D2 pwc25.bit._D2\r
+#define PWC25_D1 pwc25.bit._D1\r
+#define PWC25_D0 pwc25.bit._D0\r
+__IO_EXTERN __io PWC15STR pwc15;  \r
+#define PWC15 pwc15.word\r
+#define PWC15_D9 pwc15.bit._D9\r
+#define PWC15_D8 pwc15.bit._D8\r
+#define PWC15_D7 pwc15.bit._D7\r
+#define PWC15_D6 pwc15.bit._D6\r
+#define PWC15_D5 pwc15.bit._D5\r
+#define PWC15_D4 pwc15.bit._D4\r
+#define PWC15_D3 pwc15.bit._D3\r
+#define PWC15_D2 pwc15.bit._D2\r
+#define PWC15_D1 pwc15.bit._D1\r
+#define PWC15_D0 pwc15.bit._D0\r
+__IO_EXTERN __io PWS25STR pws25;  \r
+#define PWS25 pws25.byte\r
+#define PWS25_BS pws25.bit._BS\r
+#define PWS25_P2 pws25.bit._P2\r
+#define PWS25_P1 pws25.bit._P1\r
+#define PWS25_P0 pws25.bit._P0\r
+#define PWS25_M2 pws25.bit._M2\r
+#define PWS25_M1 pws25.bit._M1\r
+#define PWS25_M0 pws25.bit._M0\r
+#define PWS25_P pws25.bitc._P\r
+#define PWS25_M pws25.bitc._M\r
+__IO_EXTERN __io PWS15STR pws15;  \r
+#define PWS15 pws15.byte\r
+#define PWS15_P2 pws15.bit._P2\r
+#define PWS15_P1 pws15.bit._P1\r
+#define PWS15_P0 pws15.bit._P0\r
+#define PWS15_M2 pws15.bit._M2\r
+#define PWS15_M1 pws15.bit._M1\r
+#define PWS15_M0 pws15.bit._M0\r
+#define PWS15_P pws15.bitc._P\r
+#define PWS15_M pws15.bitc._M\r
+__IO_EXTERN __io PWC0STR pwc0;   /* Stepper Motor Control 0-5 */\r
+#define PWC0 pwc0.byte\r
+#define PWC0_S2 pwc0.bit._S2\r
+#define PWC0_P2 pwc0.bit._P2\r
+#define PWC0_P1 pwc0.bit._P1\r
+#define PWC0_P0 pwc0.bit._P0\r
+#define PWC0_CE pwc0.bit._CE\r
+#define PWC0_SC pwc0.bit._SC\r
+#define PWC0_P pwc0.bitc._P\r
+__IO_EXTERN __io PWC1STR pwc1;  \r
+#define PWC1 pwc1.byte\r
+#define PWC1_S2 pwc1.bit._S2\r
+#define PWC1_P2 pwc1.bit._P2\r
+#define PWC1_P1 pwc1.bit._P1\r
+#define PWC1_P0 pwc1.bit._P0\r
+#define PWC1_CE pwc1.bit._CE\r
+#define PWC1_SC pwc1.bit._SC\r
+#define PWC1_P pwc1.bitc._P\r
+__IO_EXTERN __io PWC2STR pwc2;  \r
+#define PWC2 pwc2.byte\r
+#define PWC2_S2 pwc2.bit._S2\r
+#define PWC2_P2 pwc2.bit._P2\r
+#define PWC2_P1 pwc2.bit._P1\r
+#define PWC2_P0 pwc2.bit._P0\r
+#define PWC2_CE pwc2.bit._CE\r
+#define PWC2_SC pwc2.bit._SC\r
+#define PWC2_P pwc2.bitc._P\r
+__IO_EXTERN __io PWC3STR pwc3;  \r
+#define PWC3 pwc3.byte\r
+#define PWC3_S2 pwc3.bit._S2\r
+#define PWC3_P2 pwc3.bit._P2\r
+#define PWC3_P1 pwc3.bit._P1\r
+#define PWC3_P0 pwc3.bit._P0\r
+#define PWC3_CE pwc3.bit._CE\r
+#define PWC3_SC pwc3.bit._SC\r
+#define PWC3_P pwc3.bitc._P\r
+__IO_EXTERN __io PWC4STR pwc4;  \r
+#define PWC4 pwc4.byte\r
+#define PWC4_S2 pwc4.bit._S2\r
+#define PWC4_P2 pwc4.bit._P2\r
+#define PWC4_P1 pwc4.bit._P1\r
+#define PWC4_P0 pwc4.bit._P0\r
+#define PWC4_CE pwc4.bit._CE\r
+#define PWC4_SC pwc4.bit._SC\r
+#define PWC4_P pwc4.bitc._P\r
+__IO_EXTERN __io PWC5STR pwc5;  \r
+#define PWC5 pwc5.byte\r
+#define PWC5_S2 pwc5.bit._S2\r
+#define PWC5_P2 pwc5.bit._P2\r
+#define PWC5_P1 pwc5.bit._P1\r
+#define PWC5_P0 pwc5.bit._P0\r
+#define PWC5_CE pwc5.bit._CE\r
+#define PWC5_SC pwc5.bit._SC\r
+#define PWC5_P pwc5.bitc._P\r
+__IO_EXTERN __io IBCR0STR ibcr0;   /* I2C 0 */\r
+#define IBCR0 ibcr0.byte\r
+#define IBCR0_BER ibcr0.bit._BER\r
+#define IBCR0_BEIE ibcr0.bit._BEIE\r
+#define IBCR0_SCC ibcr0.bit._SCC\r
+#define IBCR0_MSS ibcr0.bit._MSS\r
+#define IBCR0_ACK ibcr0.bit._ACK\r
+#define IBCR0_GCAA ibcr0.bit._GCAA\r
+#define IBCR0_INTE ibcr0.bit._INTE\r
+#define IBCR0_INT ibcr0.bit._INT\r
+__IO_EXTERN __io IBSR0STR ibsr0;  \r
+#define IBSR0 ibsr0.byte\r
+#define IBSR0_BB ibsr0.bit._BB\r
+#define IBSR0_RSC ibsr0.bit._RSC\r
+#define IBSR0_AL ibsr0.bit._AL\r
+#define IBSR0_LRB ibsr0.bit._LRB\r
+#define IBSR0_TRX ibsr0.bit._TRX\r
+#define IBSR0_AAS ibsr0.bit._AAS\r
+#define IBSR0_GCA ibsr0.bit._GCA\r
+#define IBSR0_ADT ibsr0.bit._ADT\r
+__IO_EXTERN __io ITBA0STR itba0;  \r
+#define ITBA0 itba0.word\r
+#define ITBA0_TA9 itba0.bit._TA9\r
+#define ITBA0_TA8 itba0.bit._TA8\r
+#define ITBA0_TA7 itba0.bit._TA7\r
+#define ITBA0_TA6 itba0.bit._TA6\r
+#define ITBA0_TA5 itba0.bit._TA5\r
+#define ITBA0_TA4 itba0.bit._TA4\r
+#define ITBA0_TA3 itba0.bit._TA3\r
+#define ITBA0_TA2 itba0.bit._TA2\r
+#define ITBA0_TA1 itba0.bit._TA1\r
+#define ITBA0_TA0 itba0.bit._TA0\r
+__IO_EXTERN __io ITBAH0STR itbah0;  \r
+#define ITBAH0 itbah0.byte\r
+#define ITBAH0_TA9 itbah0.bit._TA9\r
+#define ITBAH0_TA8 itbah0.bit._TA8\r
+__IO_EXTERN __io ITBAL0STR itbal0;  \r
+#define ITBAL0 itbal0.byte\r
+#define ITBAL0_TA7 itbal0.bit._TA7\r
+#define ITBAL0_TA6 itbal0.bit._TA6\r
+#define ITBAL0_TA5 itbal0.bit._TA5\r
+#define ITBAL0_TA4 itbal0.bit._TA4\r
+#define ITBAL0_TA3 itbal0.bit._TA3\r
+#define ITBAL0_TA2 itbal0.bit._TA2\r
+#define ITBAL0_TA1 itbal0.bit._TA1\r
+#define ITBAL0_TA0 itbal0.bit._TA0\r
+__IO_EXTERN __io ITMK0STR itmk0;  \r
+#define ITMK0 itmk0.word\r
+#define ITMK0_ENTB itmk0.bit._ENTB\r
+#define ITMK0_RAL itmk0.bit._RAL\r
+#define ITMK0_TM9 itmk0.bit._TM9\r
+#define ITMK0_TM8 itmk0.bit._TM8\r
+#define ITMK0_TM7 itmk0.bit._TM7\r
+#define ITMK0_TM6 itmk0.bit._TM6\r
+#define ITMK0_TM5 itmk0.bit._TM5\r
+#define ITMK0_TM4 itmk0.bit._TM4\r
+#define ITMK0_TM3 itmk0.bit._TM3\r
+#define ITMK0_TM2 itmk0.bit._TM2\r
+#define ITMK0_TM1 itmk0.bit._TM1\r
+#define ITMK0_TM0 itmk0.bit._TM0\r
+__IO_EXTERN __io ITMKH0STR itmkh0;  \r
+#define ITMKH0 itmkh0.byte\r
+#define ITMKH0_ENTB itmkh0.bit._ENTB\r
+#define ITMKH0_RAL itmkh0.bit._RAL\r
+#define ITMKH0_TM9 itmkh0.bit._TM9\r
+#define ITMKH0_TM8 itmkh0.bit._TM8\r
+__IO_EXTERN __io ITMKL0STR itmkl0;  \r
+#define ITMKL0 itmkl0.byte\r
+#define ITMKL0_TM7 itmkl0.bit._TM7\r
+#define ITMKL0_TM6 itmkl0.bit._TM6\r
+#define ITMKL0_TM5 itmkl0.bit._TM5\r
+#define ITMKL0_TM4 itmkl0.bit._TM4\r
+#define ITMKL0_TM3 itmkl0.bit._TM3\r
+#define ITMKL0_TM2 itmkl0.bit._TM2\r
+#define ITMKL0_TM1 itmkl0.bit._TM1\r
+#define ITMKL0_TM0 itmkl0.bit._TM0\r
+__IO_EXTERN __io ISMK0STR ismk0;  \r
+#define ISMK0 ismk0.byte\r
+#define ISMK0_ENSB ismk0.bit._ENSB\r
+#define ISMK0_SM6 ismk0.bit._SM6\r
+#define ISMK0_SM5 ismk0.bit._SM5\r
+#define ISMK0_SM4 ismk0.bit._SM4\r
+#define ISMK0_SM3 ismk0.bit._SM3\r
+#define ISMK0_SM2 ismk0.bit._SM2\r
+#define ISMK0_SM1 ismk0.bit._SM1\r
+#define ISMK0_SM0 ismk0.bit._SM0\r
+__IO_EXTERN __io ISBA0STR isba0;  \r
+#define ISBA0 isba0.byte\r
+#define ISBA0_SA6 isba0.bit._SA6\r
+#define ISBA0_SA5 isba0.bit._SA5\r
+#define ISBA0_SA4 isba0.bit._SA4\r
+#define ISBA0_SA3 isba0.bit._SA3\r
+#define ISBA0_SA2 isba0.bit._SA2\r
+#define ISBA0_SA1 isba0.bit._SA1\r
+#define ISBA0_SA0 isba0.bit._SA0\r
+__IO_EXTERN __io IDAR0STR idar0;  \r
+#define IDAR0 idar0.byte\r
+#define IDAR0_D7 idar0.bit._D7\r
+#define IDAR0_D6 idar0.bit._D6\r
+#define IDAR0_D5 idar0.bit._D5\r
+#define IDAR0_D4 idar0.bit._D4\r
+#define IDAR0_D3 idar0.bit._D3\r
+#define IDAR0_D2 idar0.bit._D2\r
+#define IDAR0_D1 idar0.bit._D1\r
+#define IDAR0_D0 idar0.bit._D0\r
+__IO_EXTERN __io ICCR0STR iccr0;  \r
+#define ICCR0 iccr0.byte\r
+#define ICCR0_NSF iccr0.bit._NSF\r
+#define ICCR0_EN iccr0.bit._EN\r
+#define ICCR0_CS4 iccr0.bit._CS4\r
+#define ICCR0_CS3 iccr0.bit._CS3\r
+#define ICCR0_CS2 iccr0.bit._CS2\r
+#define ICCR0_CS1 iccr0.bit._CS1\r
+#define ICCR0_CS0 iccr0.bit._CS0\r
+#define ICCR0_CS iccr0.bitc._CS\r
+__IO_EXTERN GCN11STR gcn11;   /* PPG Control 4-7 */\r
+#define GCN11 gcn11.word\r
+#define GCN11_TSEL33 gcn11.bit._TSEL33\r
+#define GCN11_TSEL32 gcn11.bit._TSEL32\r
+#define GCN11_TSEL31 gcn11.bit._TSEL31\r
+#define GCN11_TSEL30 gcn11.bit._TSEL30\r
+#define GCN11_TSEL23 gcn11.bit._TSEL23\r
+#define GCN11_TSEL22 gcn11.bit._TSEL22\r
+#define GCN11_TSEL21 gcn11.bit._TSEL21\r
+#define GCN11_TSEL20 gcn11.bit._TSEL20\r
+#define GCN11_TSEL13 gcn11.bit._TSEL13\r
+#define GCN11_TSEL12 gcn11.bit._TSEL12\r
+#define GCN11_TSEL11 gcn11.bit._TSEL11\r
+#define GCN11_TSEL10 gcn11.bit._TSEL10\r
+#define GCN11_TSEL03 gcn11.bit._TSEL03\r
+#define GCN11_TSEL02 gcn11.bit._TSEL02\r
+#define GCN11_TSEL01 gcn11.bit._TSEL01\r
+#define GCN11_TSEL00 gcn11.bit._TSEL00\r
+__IO_EXTERN GCN21STR gcn21;  \r
+#define GCN21 gcn21.byte\r
+#define GCN21_EN3 gcn21.bit._EN3\r
+#define GCN21_EN2 gcn21.bit._EN2\r
+#define GCN21_EN1 gcn21.bit._EN1\r
+#define GCN21_EN0 gcn21.bit._EN0\r
+__IO_EXTERN GCN12STR gcn12;   /* PPG Control 8-11 */\r
+#define GCN12 gcn12.word\r
+#define GCN12_TSEL33 gcn12.bit._TSEL33\r
+#define GCN12_TSEL32 gcn12.bit._TSEL32\r
+#define GCN12_TSEL31 gcn12.bit._TSEL31\r
+#define GCN12_TSEL30 gcn12.bit._TSEL30\r
+#define GCN12_TSEL23 gcn12.bit._TSEL23\r
+#define GCN12_TSEL22 gcn12.bit._TSEL22\r
+#define GCN12_TSEL21 gcn12.bit._TSEL21\r
+#define GCN12_TSEL20 gcn12.bit._TSEL20\r
+#define GCN12_TSEL13 gcn12.bit._TSEL13\r
+#define GCN12_TSEL12 gcn12.bit._TSEL12\r
+#define GCN12_TSEL11 gcn12.bit._TSEL11\r
+#define GCN12_TSEL10 gcn12.bit._TSEL10\r
+#define GCN12_TSEL03 gcn12.bit._TSEL03\r
+#define GCN12_TSEL02 gcn12.bit._TSEL02\r
+#define GCN12_TSEL01 gcn12.bit._TSEL01\r
+#define GCN12_TSEL00 gcn12.bit._TSEL00\r
+__IO_EXTERN GCN22STR gcn22;  \r
+#define GCN22 gcn22.byte\r
+#define GCN22_EN3 gcn22.bit._EN3\r
+#define GCN22_EN2 gcn22.bit._EN2\r
+#define GCN22_EN1 gcn22.bit._EN1\r
+#define GCN22_EN0 gcn22.bit._EN0\r
+__IO_EXTERN IO_WORD ptmr04;   /* PPG 4 */\r
+#define PTMR04 ptmr04\r
+__IO_EXTERN IO_WORD pcsr04;  \r
+#define PCSR04 pcsr04\r
+__IO_EXTERN IO_WORD pdut04;  \r
+#define PDUT04 pdut04\r
+__IO_EXTERN PCN04STR pcn04;  \r
+#define PCN04 pcn04.word\r
+#define PCN04_CNTE pcn04.bit._CNTE\r
+#define PCN04_STGR pcn04.bit._STGR\r
+#define PCN04_MDSE pcn04.bit._MDSE\r
+#define PCN04_RTRG pcn04.bit._RTRG\r
+#define PCN04_CKS1 pcn04.bit._CKS1\r
+#define PCN04_CKS0 pcn04.bit._CKS0\r
+#define PCN04_PGMS pcn04.bit._PGMS\r
+#define PCN04_EGS1 pcn04.bit._EGS1\r
+#define PCN04_EGS0 pcn04.bit._EGS0\r
+#define PCN04_IREN pcn04.bit._IREN\r
+#define PCN04_IRQF pcn04.bit._IRQF\r
+#define PCN04_IRS1 pcn04.bit._IRS1\r
+#define PCN04_IRS0 pcn04.bit._IRS0\r
+#define PCN04_OSEL pcn04.bit._OSEL\r
+#define PCN04_CKS pcn04.bitc._CKS\r
+#define PCN04_EGS pcn04.bitc._EGS\r
+#define PCN04_IRS pcn04.bitc._IRS\r
+__IO_EXTERN PCNH04STR pcnh04;  \r
+#define PCNH04 pcnh04.byte\r
+#define PCNH04_CNTE pcnh04.bit._CNTE\r
+#define PCNH04_STGR pcnh04.bit._STGR\r
+#define PCNH04_MDSE pcnh04.bit._MDSE\r
+#define PCNH04_RTRG pcnh04.bit._RTRG\r
+#define PCNH04_CKS1 pcnh04.bit._CKS1\r
+#define PCNH04_CKS0 pcnh04.bit._CKS0\r
+#define PCNH04_PGMS pcnh04.bit._PGMS\r
+#define PCNH04_CKS pcnh04.bitc._CKS\r
+__IO_EXTERN PCNL04STR pcnl04;  \r
+#define PCNL04 pcnl04.byte\r
+#define PCNL04_EGS1 pcnl04.bit._EGS1\r
+#define PCNL04_EGS0 pcnl04.bit._EGS0\r
+#define PCNL04_IREN pcnl04.bit._IREN\r
+#define PCNL04_IRQF pcnl04.bit._IRQF\r
+#define PCNL04_IRS1 pcnl04.bit._IRS1\r
+#define PCNL04_IRS0 pcnl04.bit._IRS0\r
+#define PCNL04_OSEL pcnl04.bit._OSEL\r
+#define PCNL04_EGS pcnl04.bitc._EGS\r
+#define PCNL04_IRS pcnl04.bitc._IRS\r
+__IO_EXTERN IO_WORD ptmr05;   /* PPG 5 */\r
+#define PTMR05 ptmr05\r
+__IO_EXTERN IO_WORD pcsr05;  \r
+#define PCSR05 pcsr05\r
+__IO_EXTERN IO_WORD pdut05;  \r
+#define PDUT05 pdut05\r
+__IO_EXTERN PCN05STR pcn05;  \r
+#define PCN05 pcn05.word\r
+#define PCN05_CNTE pcn05.bit._CNTE\r
+#define PCN05_STGR pcn05.bit._STGR\r
+#define PCN05_MDSE pcn05.bit._MDSE\r
+#define PCN05_RTRG pcn05.bit._RTRG\r
+#define PCN05_CKS1 pcn05.bit._CKS1\r
+#define PCN05_CKS0 pcn05.bit._CKS0\r
+#define PCN05_PGMS pcn05.bit._PGMS\r
+#define PCN05_EGS1 pcn05.bit._EGS1\r
+#define PCN05_EGS0 pcn05.bit._EGS0\r
+#define PCN05_IREN pcn05.bit._IREN\r
+#define PCN05_IRQF pcn05.bit._IRQF\r
+#define PCN05_IRS1 pcn05.bit._IRS1\r
+#define PCN05_IRS0 pcn05.bit._IRS0\r
+#define PCN05_OSEL pcn05.bit._OSEL\r
+#define PCN05_CKS pcn05.bitc._CKS\r
+#define PCN05_EGS pcn05.bitc._EGS\r
+#define PCN05_IRS pcn05.bitc._IRS\r
+__IO_EXTERN PCNH05STR pcnh05;  \r
+#define PCNH05 pcnh05.byte\r
+#define PCNH05_CNTE pcnh05.bit._CNTE\r
+#define PCNH05_STGR pcnh05.bit._STGR\r
+#define PCNH05_MDSE pcnh05.bit._MDSE\r
+#define PCNH05_RTRG pcnh05.bit._RTRG\r
+#define PCNH05_CKS1 pcnh05.bit._CKS1\r
+#define PCNH05_CKS0 pcnh05.bit._CKS0\r
+#define PCNH05_PGMS pcnh05.bit._PGMS\r
+#define PCNH05_CKS pcnh05.bitc._CKS\r
+__IO_EXTERN PCNL05STR pcnl05;  \r
+#define PCNL05 pcnl05.byte\r
+#define PCNL05_EGS1 pcnl05.bit._EGS1\r
+#define PCNL05_EGS0 pcnl05.bit._EGS0\r
+#define PCNL05_IREN pcnl05.bit._IREN\r
+#define PCNL05_IRQF pcnl05.bit._IRQF\r
+#define PCNL05_IRS1 pcnl05.bit._IRS1\r
+#define PCNL05_IRS0 pcnl05.bit._IRS0\r
+#define PCNL05_OSEL pcnl05.bit._OSEL\r
+#define PCNL05_EGS pcnl05.bitc._EGS\r
+#define PCNL05_IRS pcnl05.bitc._IRS\r
+__IO_EXTERN IO_WORD ptmr06;   /* PPG 6 */\r
+#define PTMR06 ptmr06\r
+__IO_EXTERN IO_WORD pcsr06;  \r
+#define PCSR06 pcsr06\r
+__IO_EXTERN IO_WORD pdut06;  \r
+#define PDUT06 pdut06\r
+__IO_EXTERN PCN06STR pcn06;  \r
+#define PCN06 pcn06.word\r
+#define PCN06_CNTE pcn06.bit._CNTE\r
+#define PCN06_STGR pcn06.bit._STGR\r
+#define PCN06_MDSE pcn06.bit._MDSE\r
+#define PCN06_RTRG pcn06.bit._RTRG\r
+#define PCN06_CKS1 pcn06.bit._CKS1\r
+#define PCN06_CKS0 pcn06.bit._CKS0\r
+#define PCN06_PGMS pcn06.bit._PGMS\r
+#define PCN06_EGS1 pcn06.bit._EGS1\r
+#define PCN06_EGS0 pcn06.bit._EGS0\r
+#define PCN06_IREN pcn06.bit._IREN\r
+#define PCN06_IRQF pcn06.bit._IRQF\r
+#define PCN06_IRS1 pcn06.bit._IRS1\r
+#define PCN06_IRS0 pcn06.bit._IRS0\r
+#define PCN06_OSEL pcn06.bit._OSEL\r
+#define PCN06_CKS pcn06.bitc._CKS\r
+#define PCN06_EGS pcn06.bitc._EGS\r
+#define PCN06_IRS pcn06.bitc._IRS\r
+__IO_EXTERN PCNH06STR pcnh06;  \r
+#define PCNH06 pcnh06.byte\r
+#define PCNH06_CNTE pcnh06.bit._CNTE\r
+#define PCNH06_STGR pcnh06.bit._STGR\r
+#define PCNH06_MDSE pcnh06.bit._MDSE\r
+#define PCNH06_RTRG pcnh06.bit._RTRG\r
+#define PCNH06_CKS1 pcnh06.bit._CKS1\r
+#define PCNH06_CKS0 pcnh06.bit._CKS0\r
+#define PCNH06_PGMS pcnh06.bit._PGMS\r
+#define PCNH06_CKS pcnh06.bitc._CKS\r
+__IO_EXTERN PCNL06STR pcnl06;  \r
+#define PCNL06 pcnl06.byte\r
+#define PCNL06_EGS1 pcnl06.bit._EGS1\r
+#define PCNL06_EGS0 pcnl06.bit._EGS0\r
+#define PCNL06_IREN pcnl06.bit._IREN\r
+#define PCNL06_IRQF pcnl06.bit._IRQF\r
+#define PCNL06_IRS1 pcnl06.bit._IRS1\r
+#define PCNL06_IRS0 pcnl06.bit._IRS0\r
+#define PCNL06_OSEL pcnl06.bit._OSEL\r
+#define PCNL06_EGS pcnl06.bitc._EGS\r
+#define PCNL06_IRS pcnl06.bitc._IRS\r
+__IO_EXTERN IO_WORD ptmr07;   /* PPG 7 */\r
+#define PTMR07 ptmr07\r
+__IO_EXTERN IO_WORD pcsr07;  \r
+#define PCSR07 pcsr07\r
+__IO_EXTERN IO_WORD pdut07;  \r
+#define PDUT07 pdut07\r
+__IO_EXTERN PCN07STR pcn07;  \r
+#define PCN07 pcn07.word\r
+#define PCN07_CNTE pcn07.bit._CNTE\r
+#define PCN07_STGR pcn07.bit._STGR\r
+#define PCN07_MDSE pcn07.bit._MDSE\r
+#define PCN07_RTRG pcn07.bit._RTRG\r
+#define PCN07_CKS1 pcn07.bit._CKS1\r
+#define PCN07_CKS0 pcn07.bit._CKS0\r
+#define PCN07_PGMS pcn07.bit._PGMS\r
+#define PCN07_EGS1 pcn07.bit._EGS1\r
+#define PCN07_EGS0 pcn07.bit._EGS0\r
+#define PCN07_IREN pcn07.bit._IREN\r
+#define PCN07_IRQF pcn07.bit._IRQF\r
+#define PCN07_IRS1 pcn07.bit._IRS1\r
+#define PCN07_IRS0 pcn07.bit._IRS0\r
+#define PCN07_OSEL pcn07.bit._OSEL\r
+#define PCN07_CKS pcn07.bitc._CKS\r
+#define PCN07_EGS pcn07.bitc._EGS\r
+#define PCN07_IRS pcn07.bitc._IRS\r
+__IO_EXTERN PCNH07STR pcnh07;  \r
+#define PCNH07 pcnh07.byte\r
+#define PCNH07_CNTE pcnh07.bit._CNTE\r
+#define PCNH07_STGR pcnh07.bit._STGR\r
+#define PCNH07_MDSE pcnh07.bit._MDSE\r
+#define PCNH07_RTRG pcnh07.bit._RTRG\r
+#define PCNH07_CKS1 pcnh07.bit._CKS1\r
+#define PCNH07_CKS0 pcnh07.bit._CKS0\r
+#define PCNH07_PGMS pcnh07.bit._PGMS\r
+#define PCNH07_CKS pcnh07.bitc._CKS\r
+__IO_EXTERN PCNL07STR pcnl07;  \r
+#define PCNL07 pcnl07.byte\r
+#define PCNL07_EGS1 pcnl07.bit._EGS1\r
+#define PCNL07_EGS0 pcnl07.bit._EGS0\r
+#define PCNL07_IREN pcnl07.bit._IREN\r
+#define PCNL07_IRQF pcnl07.bit._IRQF\r
+#define PCNL07_IRS1 pcnl07.bit._IRS1\r
+#define PCNL07_IRS0 pcnl07.bit._IRS0\r
+#define PCNL07_OSEL pcnl07.bit._OSEL\r
+#define PCNL07_EGS pcnl07.bitc._EGS\r
+#define PCNL07_IRS pcnl07.bitc._IRS\r
+__IO_EXTERN IO_WORD ptmr08;   /* PPG 8 */\r
+#define PTMR08 ptmr08\r
+__IO_EXTERN IO_WORD pcsr08;  \r
+#define PCSR08 pcsr08\r
+__IO_EXTERN IO_WORD pdut08;  \r
+#define PDUT08 pdut08\r
+__IO_EXTERN PCN08STR pcn08;  \r
+#define PCN08 pcn08.word\r
+#define PCN08_CNTE pcn08.bit._CNTE\r
+#define PCN08_STGR pcn08.bit._STGR\r
+#define PCN08_MDSE pcn08.bit._MDSE\r
+#define PCN08_RTRG pcn08.bit._RTRG\r
+#define PCN08_CKS1 pcn08.bit._CKS1\r
+#define PCN08_CKS0 pcn08.bit._CKS0\r
+#define PCN08_PGMS pcn08.bit._PGMS\r
+#define PCN08_EGS1 pcn08.bit._EGS1\r
+#define PCN08_EGS0 pcn08.bit._EGS0\r
+#define PCN08_IREN pcn08.bit._IREN\r
+#define PCN08_IRQF pcn08.bit._IRQF\r
+#define PCN08_IRS1 pcn08.bit._IRS1\r
+#define PCN08_IRS0 pcn08.bit._IRS0\r
+#define PCN08_OSEL pcn08.bit._OSEL\r
+#define PCN08_CKS pcn08.bitc._CKS\r
+#define PCN08_EGS pcn08.bitc._EGS\r
+#define PCN08_IRS pcn08.bitc._IRS\r
+__IO_EXTERN PCNH08STR pcnh08;  \r
+#define PCNH08 pcnh08.byte\r
+#define PCNH08_CNTE pcnh08.bit._CNTE\r
+#define PCNH08_STGR pcnh08.bit._STGR\r
+#define PCNH08_MDSE pcnh08.bit._MDSE\r
+#define PCNH08_RTRG pcnh08.bit._RTRG\r
+#define PCNH08_CKS1 pcnh08.bit._CKS1\r
+#define PCNH08_CKS0 pcnh08.bit._CKS0\r
+#define PCNH08_PGMS pcnh08.bit._PGMS\r
+#define PCNH08_CKS pcnh08.bitc._CKS\r
+__IO_EXTERN PCNL08STR pcnl08;  \r
+#define PCNL08 pcnl08.byte\r
+#define PCNL08_EGS1 pcnl08.bit._EGS1\r
+#define PCNL08_EGS0 pcnl08.bit._EGS0\r
+#define PCNL08_IREN pcnl08.bit._IREN\r
+#define PCNL08_IRQF pcnl08.bit._IRQF\r
+#define PCNL08_IRS1 pcnl08.bit._IRS1\r
+#define PCNL08_IRS0 pcnl08.bit._IRS0\r
+#define PCNL08_OSEL pcnl08.bit._OSEL\r
+#define PCNL08_EGS pcnl08.bitc._EGS\r
+#define PCNL08_IRS pcnl08.bitc._IRS\r
+__IO_EXTERN IO_WORD ptmr09;   /* PPG 9 */\r
+#define PTMR09 ptmr09\r
+__IO_EXTERN IO_WORD pcsr09;  \r
+#define PCSR09 pcsr09\r
+__IO_EXTERN IO_WORD pdut09;  \r
+#define PDUT09 pdut09\r
+__IO_EXTERN PCN09STR pcn09;  \r
+#define PCN09 pcn09.word\r
+#define PCN09_CNTE pcn09.bit._CNTE\r
+#define PCN09_STGR pcn09.bit._STGR\r
+#define PCN09_MDSE pcn09.bit._MDSE\r
+#define PCN09_RTRG pcn09.bit._RTRG\r
+#define PCN09_CKS1 pcn09.bit._CKS1\r
+#define PCN09_CKS0 pcn09.bit._CKS0\r
+#define PCN09_PGMS pcn09.bit._PGMS\r
+#define PCN09_EGS1 pcn09.bit._EGS1\r
+#define PCN09_EGS0 pcn09.bit._EGS0\r
+#define PCN09_IREN pcn09.bit._IREN\r
+#define PCN09_IRQF pcn09.bit._IRQF\r
+#define PCN09_IRS1 pcn09.bit._IRS1\r
+#define PCN09_IRS0 pcn09.bit._IRS0\r
+#define PCN09_OSEL pcn09.bit._OSEL\r
+#define PCN09_CKS pcn09.bitc._CKS\r
+#define PCN09_EGS pcn09.bitc._EGS\r
+#define PCN09_IRS pcn09.bitc._IRS\r
+__IO_EXTERN PCNH09STR pcnh09;  \r
+#define PCNH09 pcnh09.byte\r
+#define PCNH09_CNTE pcnh09.bit._CNTE\r
+#define PCNH09_STGR pcnh09.bit._STGR\r
+#define PCNH09_MDSE pcnh09.bit._MDSE\r
+#define PCNH09_RTRG pcnh09.bit._RTRG\r
+#define PCNH09_CKS1 pcnh09.bit._CKS1\r
+#define PCNH09_CKS0 pcnh09.bit._CKS0\r
+#define PCNH09_PGMS pcnh09.bit._PGMS\r
+#define PCNH09_CKS pcnh09.bitc._CKS\r
+__IO_EXTERN PCNL09STR pcnl09;  \r
+#define PCNL09 pcnl09.byte\r
+#define PCNL09_EGS1 pcnl09.bit._EGS1\r
+#define PCNL09_EGS0 pcnl09.bit._EGS0\r
+#define PCNL09_IREN pcnl09.bit._IREN\r
+#define PCNL09_IRQF pcnl09.bit._IRQF\r
+#define PCNL09_IRS1 pcnl09.bit._IRS1\r
+#define PCNL09_IRS0 pcnl09.bit._IRS0\r
+#define PCNL09_OSEL pcnl09.bit._OSEL\r
+#define PCNL09_EGS pcnl09.bitc._EGS\r
+#define PCNL09_IRS pcnl09.bitc._IRS\r
+__IO_EXTERN IO_WORD ptmr10;   /* PPG 10 */\r
+#define PTMR10 ptmr10\r
+__IO_EXTERN IO_WORD pcsr10;  \r
+#define PCSR10 pcsr10\r
+__IO_EXTERN IO_WORD pdut10;  \r
+#define PDUT10 pdut10\r
+__IO_EXTERN PCN10STR pcn10;  \r
+#define PCN10 pcn10.word\r
+#define PCN10_CNTE pcn10.bit._CNTE\r
+#define PCN10_STGR pcn10.bit._STGR\r
+#define PCN10_MDSE pcn10.bit._MDSE\r
+#define PCN10_RTRG pcn10.bit._RTRG\r
+#define PCN10_CKS1 pcn10.bit._CKS1\r
+#define PCN10_CKS0 pcn10.bit._CKS0\r
+#define PCN10_PGMS pcn10.bit._PGMS\r
+#define PCN10_EGS1 pcn10.bit._EGS1\r
+#define PCN10_EGS0 pcn10.bit._EGS0\r
+#define PCN10_IREN pcn10.bit._IREN\r
+#define PCN10_IRQF pcn10.bit._IRQF\r
+#define PCN10_IRS1 pcn10.bit._IRS1\r
+#define PCN10_IRS0 pcn10.bit._IRS0\r
+#define PCN10_OSEL pcn10.bit._OSEL\r
+#define PCN10_CKS pcn10.bitc._CKS\r
+#define PCN10_EGS pcn10.bitc._EGS\r
+#define PCN10_IRS pcn10.bitc._IRS\r
+__IO_EXTERN PCNH10STR pcnh10;  \r
+#define PCNH10 pcnh10.byte\r
+#define PCNH10_CNTE pcnh10.bit._CNTE\r
+#define PCNH10_STGR pcnh10.bit._STGR\r
+#define PCNH10_MDSE pcnh10.bit._MDSE\r
+#define PCNH10_RTRG pcnh10.bit._RTRG\r
+#define PCNH10_CKS1 pcnh10.bit._CKS1\r
+#define PCNH10_CKS0 pcnh10.bit._CKS0\r
+#define PCNH10_PGMS pcnh10.bit._PGMS\r
+#define PCNH10_CKS pcnh10.bitc._CKS\r
+__IO_EXTERN PCNL10STR pcnl10;  \r
+#define PCNL10 pcnl10.byte\r
+#define PCNL10_EGS1 pcnl10.bit._EGS1\r
+#define PCNL10_EGS0 pcnl10.bit._EGS0\r
+#define PCNL10_IREN pcnl10.bit._IREN\r
+#define PCNL10_IRQF pcnl10.bit._IRQF\r
+#define PCNL10_IRS1 pcnl10.bit._IRS1\r
+#define PCNL10_IRS0 pcnl10.bit._IRS0\r
+#define PCNL10_OSEL pcnl10.bit._OSEL\r
+#define PCNL10_EGS pcnl10.bitc._EGS\r
+#define PCNL10_IRS pcnl10.bitc._IRS\r
+__IO_EXTERN IO_WORD ptmr11;   /* PPG 11 */\r
+#define PTMR11 ptmr11\r
+__IO_EXTERN IO_WORD pcsr11;  \r
+#define PCSR11 pcsr11\r
+__IO_EXTERN IO_WORD pdut11;  \r
+#define PDUT11 pdut11\r
+__IO_EXTERN PCN11STR pcn11;  \r
+#define PCN11 pcn11.word\r
+#define PCN11_CNTE pcn11.bit._CNTE\r
+#define PCN11_STGR pcn11.bit._STGR\r
+#define PCN11_MDSE pcn11.bit._MDSE\r
+#define PCN11_RTRG pcn11.bit._RTRG\r
+#define PCN11_CKS1 pcn11.bit._CKS1\r
+#define PCN11_CKS0 pcn11.bit._CKS0\r
+#define PCN11_PGMS pcn11.bit._PGMS\r
+#define PCN11_EGS1 pcn11.bit._EGS1\r
+#define PCN11_EGS0 pcn11.bit._EGS0\r
+#define PCN11_IREN pcn11.bit._IREN\r
+#define PCN11_IRQF pcn11.bit._IRQF\r
+#define PCN11_IRS1 pcn11.bit._IRS1\r
+#define PCN11_IRS0 pcn11.bit._IRS0\r
+#define PCN11_OSEL pcn11.bit._OSEL\r
+#define PCN11_CKS pcn11.bitc._CKS\r
+#define PCN11_EGS pcn11.bitc._EGS\r
+#define PCN11_IRS pcn11.bitc._IRS\r
+__IO_EXTERN PCNH11STR pcnh11;  \r
+#define PCNH11 pcnh11.byte\r
+#define PCNH11_CNTE pcnh11.bit._CNTE\r
+#define PCNH11_STGR pcnh11.bit._STGR\r
+#define PCNH11_MDSE pcnh11.bit._MDSE\r
+#define PCNH11_RTRG pcnh11.bit._RTRG\r
+#define PCNH11_CKS1 pcnh11.bit._CKS1\r
+#define PCNH11_CKS0 pcnh11.bit._CKS0\r
+#define PCNH11_PGMS pcnh11.bit._PGMS\r
+#define PCNH11_CKS pcnh11.bitc._CKS\r
+__IO_EXTERN PCNL11STR pcnl11;  \r
+#define PCNL11 pcnl11.byte\r
+#define PCNL11_EGS1 pcnl11.bit._EGS1\r
+#define PCNL11_EGS0 pcnl11.bit._EGS0\r
+#define PCNL11_IREN pcnl11.bit._IREN\r
+#define PCNL11_IRQF pcnl11.bit._IRQF\r
+#define PCNL11_IRS1 pcnl11.bit._IRS1\r
+#define PCNL11_IRS0 pcnl11.bit._IRS0\r
+#define PCNL11_OSEL pcnl11.bit._OSEL\r
+#define PCNL11_EGS pcnl11.bitc._EGS\r
+#define PCNL11_IRS pcnl11.bitc._IRS\r
+__IO_EXTERN P0TMCSRSTR p0tmcsr;   /* Pulse Frequency Modulator (PFM) */\r
+#define P0TMCSR p0tmcsr.word\r
+#define P0TMCSR_INV p0tmcsr.bit._INV\r
+#define P0TMCSR_CSL2 p0tmcsr.bit._CSL2\r
+#define P0TMCSR_CSL1 p0tmcsr.bit._CSL1\r
+#define P0TMCSR_CSL0 p0tmcsr.bit._CSL0\r
+#define P0TMCSR_MOD1 p0tmcsr.bit._MOD1\r
+#define P0TMCSR_RELD p0tmcsr.bit._RELD\r
+#define P0TMCSR_INTE p0tmcsr.bit._INTE\r
+#define P0TMCSR_UF p0tmcsr.bit._UF\r
+#define P0TMCSR_CNTE p0tmcsr.bit._CNTE\r
+#define P0TMCSR_TRG p0tmcsr.bit._TRG\r
+#define P0TMCSR_CSL p0tmcsr.bitc._CSL\r
+__IO_EXTERN P0TMCSRHSTR p0tmcsrh;  \r
+#define P0TMCSRH p0tmcsrh.byte\r
+#define P0TMCSRH_INV p0tmcsrh.bit._INV\r
+#define P0TMCSRH_CSL2 p0tmcsrh.bit._CSL2\r
+#define P0TMCSRH_CSL1 p0tmcsrh.bit._CSL1\r
+#define P0TMCSRH_CSL0 p0tmcsrh.bit._CSL0\r
+#define P0TMCSRH_MOD1 p0tmcsrh.bit._MOD1\r
+#define P0TMCSRH_CSL p0tmcsrh.bitc._CSL\r
+__IO_EXTERN P0TMCSRLSTR p0tmcsrl;  \r
+#define P0TMCSRL p0tmcsrl.byte\r
+#define P0TMCSRL_RELD p0tmcsrl.bit._RELD\r
+#define P0TMCSRL_INTE p0tmcsrl.bit._INTE\r
+#define P0TMCSRL_UF p0tmcsrl.bit._UF\r
+#define P0TMCSRL_CNTE p0tmcsrl.bit._CNTE\r
+#define P0TMCSRL_TRG p0tmcsrl.bit._TRG\r
+__IO_EXTERN P1TMCSRSTR p1tmcsr;  \r
+#define P1TMCSR p1tmcsr.word\r
+#define P1TMCSR_INV p1tmcsr.bit._INV\r
+#define P1TMCSR_CSL2 p1tmcsr.bit._CSL2\r
+#define P1TMCSR_CSL1 p1tmcsr.bit._CSL1\r
+#define P1TMCSR_CSL0 p1tmcsr.bit._CSL0\r
+#define P1TMCSR_MOD1 p1tmcsr.bit._MOD1\r
+#define P1TMCSR_RELD p1tmcsr.bit._RELD\r
+#define P1TMCSR_INTE p1tmcsr.bit._INTE\r
+#define P1TMCSR_UF p1tmcsr.bit._UF\r
+#define P1TMCSR_CNTE p1tmcsr.bit._CNTE\r
+#define P1TMCSR_TRG p1tmcsr.bit._TRG\r
+#define P1TMCSR_CSL p1tmcsr.bitc._CSL\r
+__IO_EXTERN P1TMCSRHSTR p1tmcsrh;  \r
+#define P1TMCSRH p1tmcsrh.byte\r
+#define P1TMCSRH_INV p1tmcsrh.bit._INV\r
+#define P1TMCSRH_CSL2 p1tmcsrh.bit._CSL2\r
+#define P1TMCSRH_CSL1 p1tmcsrh.bit._CSL1\r
+#define P1TMCSRH_CSL0 p1tmcsrh.bit._CSL0\r
+#define P1TMCSRH_MOD1 p1tmcsrh.bit._MOD1\r
+#define P1TMCSRH_CSL p1tmcsrh.bitc._CSL\r
+__IO_EXTERN P1TMCSRLSTR p1tmcsrl;  \r
+#define P1TMCSRL p1tmcsrl.byte\r
+#define P1TMCSRL_RELD p1tmcsrl.bit._RELD\r
+#define P1TMCSRL_INTE p1tmcsrl.bit._INTE\r
+#define P1TMCSRL_UF p1tmcsrl.bit._UF\r
+#define P1TMCSRL_CNTE p1tmcsrl.bit._CNTE\r
+#define P1TMCSRL_TRG p1tmcsrl.bit._TRG\r
+__IO_EXTERN IO_WORD p0tmrlr;  \r
+#define P0TMRLR p0tmrlr\r
+__IO_EXTERN IO_WORD p0tmr;  \r
+#define P0TMR p0tmr\r
+__IO_EXTERN IO_WORD p1tmrlr;  \r
+#define P1TMRLR p1tmrlr\r
+__IO_EXTERN IO_WORD p1tmr;  \r
+#define P1TMR p1tmr\r
+__IO_EXTERN ICS01STR ics01;   /* Input Capture 0-3 */\r
+#define ICS01 ics01.byte\r
+#define ICS01_ICP1 ics01.bit._ICP1\r
+#define ICS01_ICP0 ics01.bit._ICP0\r
+#define ICS01_ICE1 ics01.bit._ICE1\r
+#define ICS01_ICE0 ics01.bit._ICE0\r
+#define ICS01_EG11 ics01.bit._EG11\r
+#define ICS01_EG10 ics01.bit._EG10\r
+#define ICS01_EG01 ics01.bit._EG01\r
+#define ICS01_EG00 ics01.bit._EG00\r
+#define ICS01_EG1 ics01.bitc._EG1\r
+#define ICS01_EG0 ics01.bitc._EG0\r
+__IO_EXTERN ICS23STR ics23;  \r
+#define ICS23 ics23.byte\r
+#define ICS23_ICP3 ics23.bit._ICP3\r
+#define ICS23_ICP2 ics23.bit._ICP2\r
+#define ICS23_ICE3 ics23.bit._ICE3\r
+#define ICS23_ICE2 ics23.bit._ICE2\r
+#define ICS23_EG31 ics23.bit._EG31\r
+#define ICS23_EG30 ics23.bit._EG30\r
+#define ICS23_EG21 ics23.bit._EG21\r
+#define ICS23_EG20 ics23.bit._EG20\r
+#define ICS23_EG3 ics23.bitc._EG3\r
+#define ICS23_EG2 ics23.bitc._EG2\r
+__IO_EXTERN IPCP0STR ipcp0;  \r
+#define IPCP0 ipcp0.word\r
+#define IPCP0_CP15 ipcp0.bit._CP15\r
+#define IPCP0_CP14 ipcp0.bit._CP14\r
+#define IPCP0_CP13 ipcp0.bit._CP13\r
+#define IPCP0_CP12 ipcp0.bit._CP12\r
+#define IPCP0_CP11 ipcp0.bit._CP11\r
+#define IPCP0_CP10 ipcp0.bit._CP10\r
+#define IPCP0_CP9 ipcp0.bit._CP9\r
+#define IPCP0_CP8 ipcp0.bit._CP8\r
+#define IPCP0_CP7 ipcp0.bit._CP7\r
+#define IPCP0_CP6 ipcp0.bit._CP6\r
+#define IPCP0_CP5 ipcp0.bit._CP5\r
+#define IPCP0_CP4 ipcp0.bit._CP4\r
+#define IPCP0_CP3 ipcp0.bit._CP3\r
+#define IPCP0_CP2 ipcp0.bit._CP2\r
+#define IPCP0_CP1 ipcp0.bit._CP1\r
+#define IPCP0_CP0 ipcp0.bit._CP0\r
+__IO_EXTERN IPCP1STR ipcp1;  \r
+#define IPCP1 ipcp1.word\r
+#define IPCP1_CP15 ipcp1.bit._CP15\r
+#define IPCP1_CP14 ipcp1.bit._CP14\r
+#define IPCP1_CP13 ipcp1.bit._CP13\r
+#define IPCP1_CP12 ipcp1.bit._CP12\r
+#define IPCP1_CP11 ipcp1.bit._CP11\r
+#define IPCP1_CP10 ipcp1.bit._CP10\r
+#define IPCP1_CP9 ipcp1.bit._CP9\r
+#define IPCP1_CP8 ipcp1.bit._CP8\r
+#define IPCP1_CP7 ipcp1.bit._CP7\r
+#define IPCP1_CP6 ipcp1.bit._CP6\r
+#define IPCP1_CP5 ipcp1.bit._CP5\r
+#define IPCP1_CP4 ipcp1.bit._CP4\r
+#define IPCP1_CP3 ipcp1.bit._CP3\r
+#define IPCP1_CP2 ipcp1.bit._CP2\r
+#define IPCP1_CP1 ipcp1.bit._CP1\r
+#define IPCP1_CP0 ipcp1.bit._CP0\r
+__IO_EXTERN IPCP2STR ipcp2;  \r
+#define IPCP2 ipcp2.word\r
+#define IPCP2_CP15 ipcp2.bit._CP15\r
+#define IPCP2_CP14 ipcp2.bit._CP14\r
+#define IPCP2_CP13 ipcp2.bit._CP13\r
+#define IPCP2_CP12 ipcp2.bit._CP12\r
+#define IPCP2_CP11 ipcp2.bit._CP11\r
+#define IPCP2_CP10 ipcp2.bit._CP10\r
+#define IPCP2_CP9 ipcp2.bit._CP9\r
+#define IPCP2_CP8 ipcp2.bit._CP8\r
+#define IPCP2_CP7 ipcp2.bit._CP7\r
+#define IPCP2_CP6 ipcp2.bit._CP6\r
+#define IPCP2_CP5 ipcp2.bit._CP5\r
+#define IPCP2_CP4 ipcp2.bit._CP4\r
+#define IPCP2_CP3 ipcp2.bit._CP3\r
+#define IPCP2_CP2 ipcp2.bit._CP2\r
+#define IPCP2_CP1 ipcp2.bit._CP1\r
+#define IPCP2_CP0 ipcp2.bit._CP0\r
+__IO_EXTERN IPCP3STR ipcp3;  \r
+#define IPCP3 ipcp3.word\r
+#define IPCP3_CP15 ipcp3.bit._CP15\r
+#define IPCP3_CP14 ipcp3.bit._CP14\r
+#define IPCP3_CP13 ipcp3.bit._CP13\r
+#define IPCP3_CP12 ipcp3.bit._CP12\r
+#define IPCP3_CP11 ipcp3.bit._CP11\r
+#define IPCP3_CP10 ipcp3.bit._CP10\r
+#define IPCP3_CP9 ipcp3.bit._CP9\r
+#define IPCP3_CP8 ipcp3.bit._CP8\r
+#define IPCP3_CP7 ipcp3.bit._CP7\r
+#define IPCP3_CP6 ipcp3.bit._CP6\r
+#define IPCP3_CP5 ipcp3.bit._CP5\r
+#define IPCP3_CP4 ipcp3.bit._CP4\r
+#define IPCP3_CP3 ipcp3.bit._CP3\r
+#define IPCP3_CP2 ipcp3.bit._CP2\r
+#define IPCP3_CP1 ipcp3.bit._CP1\r
+#define IPCP3_CP0 ipcp3.bit._CP0\r
+__IO_EXTERN OCS01STR ocs01;   /* Output Compare 0-3 */\r
+#define OCS01 ocs01.word\r
+#define OCS01_CMOD ocs01.bit._CMOD\r
+#define OCS01_OTD1 ocs01.bit._OTD1\r
+#define OCS01_OTD0 ocs01.bit._OTD0\r
+#define OCS01_ICP1 ocs01.bit._ICP1\r
+#define OCS01_ICP0 ocs01.bit._ICP0\r
+#define OCS01_ICE1 ocs01.bit._ICE1\r
+#define OCS01_ICE0 ocs01.bit._ICE0\r
+#define OCS01_CST1 ocs01.bit._CST1\r
+#define OCS01_CST0 ocs01.bit._CST0\r
+__IO_EXTERN OCS23STR ocs23;  \r
+#define OCS23 ocs23.word\r
+#define OCS23_CMOD ocs23.bit._CMOD\r
+#define OCS23_OTD3 ocs23.bit._OTD3\r
+#define OCS23_OTD2 ocs23.bit._OTD2\r
+#define OCS23_ICP3 ocs23.bit._ICP3\r
+#define OCS23_ICP2 ocs23.bit._ICP2\r
+#define OCS23_ICE3 ocs23.bit._ICE3\r
+#define OCS23_ICE2 ocs23.bit._ICE2\r
+#define OCS23_CST3 ocs23.bit._CST3\r
+#define OCS23_CST2 ocs23.bit._CST2\r
+__IO_EXTERN OCCP0STR occp0;  \r
+#define OCCP0 occp0.word\r
+#define OCCP0_C15 occp0.bit._C15\r
+#define OCCP0_C14 occp0.bit._C14\r
+#define OCCP0_C13 occp0.bit._C13\r
+#define OCCP0_C12 occp0.bit._C12\r
+#define OCCP0_C11 occp0.bit._C11\r
+#define OCCP0_C10 occp0.bit._C10\r
+#define OCCP0_C9 occp0.bit._C9\r
+#define OCCP0_C8 occp0.bit._C8\r
+#define OCCP0_C7 occp0.bit._C7\r
+#define OCCP0_C6 occp0.bit._C6\r
+#define OCCP0_C5 occp0.bit._C5\r
+#define OCCP0_C4 occp0.bit._C4\r
+#define OCCP0_C3 occp0.bit._C3\r
+#define OCCP0_C2 occp0.bit._C2\r
+#define OCCP0_C1 occp0.bit._C1\r
+#define OCCP0_C0 occp0.bit._C0\r
+__IO_EXTERN OCCP1STR occp1;  \r
+#define OCCP1 occp1.word\r
+#define OCCP1_C15 occp1.bit._C15\r
+#define OCCP1_C14 occp1.bit._C14\r
+#define OCCP1_C13 occp1.bit._C13\r
+#define OCCP1_C12 occp1.bit._C12\r
+#define OCCP1_C11 occp1.bit._C11\r
+#define OCCP1_C10 occp1.bit._C10\r
+#define OCCP1_C9 occp1.bit._C9\r
+#define OCCP1_C8 occp1.bit._C8\r
+#define OCCP1_C7 occp1.bit._C7\r
+#define OCCP1_C6 occp1.bit._C6\r
+#define OCCP1_C5 occp1.bit._C5\r
+#define OCCP1_C4 occp1.bit._C4\r
+#define OCCP1_C3 occp1.bit._C3\r
+#define OCCP1_C2 occp1.bit._C2\r
+#define OCCP1_C1 occp1.bit._C1\r
+#define OCCP1_C0 occp1.bit._C0\r
+__IO_EXTERN OCCP2STR occp2;  \r
+#define OCCP2 occp2.word\r
+#define OCCP2_C15 occp2.bit._C15\r
+#define OCCP2_C14 occp2.bit._C14\r
+#define OCCP2_C13 occp2.bit._C13\r
+#define OCCP2_C12 occp2.bit._C12\r
+#define OCCP2_C11 occp2.bit._C11\r
+#define OCCP2_C10 occp2.bit._C10\r
+#define OCCP2_C9 occp2.bit._C9\r
+#define OCCP2_C8 occp2.bit._C8\r
+#define OCCP2_C7 occp2.bit._C7\r
+#define OCCP2_C6 occp2.bit._C6\r
+#define OCCP2_C5 occp2.bit._C5\r
+#define OCCP2_C4 occp2.bit._C4\r
+#define OCCP2_C3 occp2.bit._C3\r
+#define OCCP2_C2 occp2.bit._C2\r
+#define OCCP2_C1 occp2.bit._C1\r
+#define OCCP2_C0 occp2.bit._C0\r
+__IO_EXTERN OCCP3STR occp3;  \r
+#define OCCP3 occp3.word\r
+#define OCCP3_C15 occp3.bit._C15\r
+#define OCCP3_C14 occp3.bit._C14\r
+#define OCCP3_C13 occp3.bit._C13\r
+#define OCCP3_C12 occp3.bit._C12\r
+#define OCCP3_C11 occp3.bit._C11\r
+#define OCCP3_C10 occp3.bit._C10\r
+#define OCCP3_C9 occp3.bit._C9\r
+#define OCCP3_C8 occp3.bit._C8\r
+#define OCCP3_C7 occp3.bit._C7\r
+#define OCCP3_C6 occp3.bit._C6\r
+#define OCCP3_C5 occp3.bit._C5\r
+#define OCCP3_C4 occp3.bit._C4\r
+#define OCCP3_C3 occp3.bit._C3\r
+#define OCCP3_C2 occp3.bit._C2\r
+#define OCCP3_C1 occp3.bit._C1\r
+#define OCCP3_C0 occp3.bit._C0\r
+__IO_EXTERN SGCRSTR sgcr;   /* Sound Generator */\r
+#define SGCR sgcr.word\r
+#define SGCR_TST sgcr.bit._TST\r
+#define SGCR_S2 sgcr.bit._S2\r
+#define SGCR_S1 sgcr.bit._S1\r
+#define SGCR_S0 sgcr.bit._S0\r
+#define SGCR_BUSY sgcr.bit._BUSY\r
+#define SGCR_DEC sgcr.bit._DEC\r
+#define SGCR_TONE sgcr.bit._TONE\r
+#define SGCR_INTE sgcr.bit._INTE\r
+#define SGCR_INT sgcr.bit._INT\r
+#define SGCR_ST sgcr.bit._ST\r
+#define SGCR_S sgcr.bitc._S\r
+__IO_EXTERN SGCRHSTR sgcrh;  \r
+#define SGCRH sgcrh.byte\r
+#define SGCRH_TST sgcrh.bit._TST\r
+#define SGCRH_S2 sgcrh.bit._S2\r
+#define SGCRH_S1 sgcrh.bit._S1\r
+#define SGCRH_S0 sgcrh.bit._S0\r
+#define SGCRH_BUSY sgcrh.bit._BUSY\r
+#define SGCRH_DEC sgcrh.bit._DEC\r
+#define SGCRH_S sgcrh.bitc._S\r
+__IO_EXTERN SGCRLSTR sgcrl;  \r
+#define SGCRL sgcrl.byte\r
+#define SGCRL_TONE sgcrl.bit._TONE\r
+#define SGCRL_INTE sgcrl.bit._INTE\r
+#define SGCRL_INT sgcrl.bit._INT\r
+#define SGCRL_ST sgcrl.bit._ST\r
+__IO_EXTERN SGFRSTR sgfr;  \r
+#define SGFR sgfr.word\r
+#define SGFR_D15 sgfr.bit._D15\r
+#define SGFR_D14 sgfr.bit._D14\r
+#define SGFR_D13 sgfr.bit._D13\r
+#define SGFR_D12 sgfr.bit._D12\r
+#define SGFR_D11 sgfr.bit._D11\r
+#define SGFR_D10 sgfr.bit._D10\r
+#define SGFR_D9 sgfr.bit._D9\r
+#define SGFR_D8 sgfr.bit._D8\r
+#define SGFR_D7 sgfr.bit._D7\r
+#define SGFR_D6 sgfr.bit._D6\r
+#define SGFR_D5 sgfr.bit._D5\r
+#define SGFR_D4 sgfr.bit._D4\r
+#define SGFR_D3 sgfr.bit._D3\r
+#define SGFR_D2 sgfr.bit._D2\r
+#define SGFR_D1 sgfr.bit._D1\r
+#define SGFR_D0 sgfr.bit._D0\r
+__IO_EXTERN SGARSTR sgar;  \r
+#define SGAR sgar.byte\r
+#define SGAR_D7 sgar.bit._D7\r
+#define SGAR_D6 sgar.bit._D6\r
+#define SGAR_D5 sgar.bit._D5\r
+#define SGAR_D4 sgar.bit._D4\r
+#define SGAR_D3 sgar.bit._D3\r
+#define SGAR_D2 sgar.bit._D2\r
+#define SGAR_D1 sgar.bit._D1\r
+#define SGAR_D0 sgar.bit._D0\r
+__IO_EXTERN SGTRSTR sgtr;  \r
+#define SGTR sgtr.byte\r
+#define SGTR_D7 sgtr.bit._D7\r
+#define SGTR_D6 sgtr.bit._D6\r
+#define SGTR_D5 sgtr.bit._D5\r
+#define SGTR_D4 sgtr.bit._D4\r
+#define SGTR_D3 sgtr.bit._D3\r
+#define SGTR_D2 sgtr.bit._D2\r
+#define SGTR_D1 sgtr.bit._D1\r
+#define SGTR_D0 sgtr.bit._D0\r
+__IO_EXTERN SGDRSTR sgdr;  \r
+#define SGDR sgdr.byte\r
+#define SGDR_D7 sgdr.bit._D7\r
+#define SGDR_D6 sgdr.bit._D6\r
+#define SGDR_D5 sgdr.bit._D5\r
+#define SGDR_D4 sgdr.bit._D4\r
+#define SGDR_D3 sgdr.bit._D3\r
+#define SGDR_D2 sgdr.bit._D2\r
+#define SGDR_D1 sgdr.bit._D1\r
+#define SGDR_D0 sgdr.bit._D0\r
+__IO_EXTERN ADERHSTR aderh;   /* ADC */\r
+#define ADERH aderh.word\r
+#define ADERH_ADE31 aderh.bit._ADE31\r
+#define ADERH_ADE30 aderh.bit._ADE30\r
+#define ADERH_ADE29 aderh.bit._ADE29\r
+#define ADERH_ADE28 aderh.bit._ADE28\r
+#define ADERH_ADE27 aderh.bit._ADE27\r
+#define ADERH_ADE26 aderh.bit._ADE26\r
+#define ADERH_ADE25 aderh.bit._ADE25\r
+#define ADERH_ADE24 aderh.bit._ADE24\r
+#define ADERH_ADE23 aderh.bit._ADE23\r
+#define ADERH_ADE22 aderh.bit._ADE22\r
+#define ADERH_ADE21 aderh.bit._ADE21\r
+#define ADERH_ADE20 aderh.bit._ADE20\r
+#define ADERH_ADE19 aderh.bit._ADE19\r
+#define ADERH_ADE18 aderh.bit._ADE18\r
+#define ADERH_ADE17 aderh.bit._ADE17\r
+#define ADERH_ADE16 aderh.bit._ADE16\r
+__IO_EXTERN ADERLSTR aderl;  \r
+#define ADERL aderl.word\r
+#define ADERL_ADE15 aderl.bit._ADE15\r
+#define ADERL_ADE14 aderl.bit._ADE14\r
+#define ADERL_ADE13 aderl.bit._ADE13\r
+#define ADERL_ADE12 aderl.bit._ADE12\r
+#define ADERL_ADE11 aderl.bit._ADE11\r
+#define ADERL_ADE10 aderl.bit._ADE10\r
+#define ADERL_ADE9 aderl.bit._ADE9\r
+#define ADERL_ADE8 aderl.bit._ADE8\r
+#define ADERL_ADE7 aderl.bit._ADE7\r
+#define ADERL_ADE6 aderl.bit._ADE6\r
+#define ADERL_ADE5 aderl.bit._ADE5\r
+#define ADERL_ADE4 aderl.bit._ADE4\r
+#define ADERL_ADE3 aderl.bit._ADE3\r
+#define ADERL_ADE2 aderl.bit._ADE2\r
+#define ADERL_ADE1 aderl.bit._ADE1\r
+#define ADERL_ADE0 aderl.bit._ADE0\r
+__IO_EXTERN IO_LWORD ader;  \r
+#define ADER ader\r
+__IO_EXTERN ADCS1STR adcs1;  \r
+#define ADCS1 adcs1.byte\r
+#define ADCS1_BUSY adcs1.bit._BUSY\r
+#define ADCS1_INT adcs1.bit._INT\r
+#define ADCS1_INTE adcs1.bit._INTE\r
+#define ADCS1_PAUS adcs1.bit._PAUS\r
+#define ADCS1_STS1 adcs1.bit._STS1\r
+#define ADCS1_STS0 adcs1.bit._STS0\r
+#define ADCS1_STRT adcs1.bit._STRT\r
+#define ADCS1_STS adcs1.bitc._STS\r
+__IO_EXTERN ADCS0STR adcs0;  \r
+#define ADCS0 adcs0.byte\r
+#define ADCS0_MD1 adcs0.bit._MD1\r
+#define ADCS0_MD0 adcs0.bit._MD0\r
+#define ADCS0_S10 adcs0.bit._S10\r
+#define ADCS0_ACH4 adcs0.bit._ACH4\r
+#define ADCS0_ACH3 adcs0.bit._ACH3\r
+#define ADCS0_ACH2 adcs0.bit._ACH2\r
+#define ADCS0_ACH1 adcs0.bit._ACH1\r
+#define ADCS0_ACH0 adcs0.bit._ACH0\r
+#define ADCS0_MD adcs0.bitc._MD\r
+#define ADCS0_ACH adcs0.bitc._ACH\r
+__IO_EXTERN IO_WORD adcs;  \r
+#define ADCS adcs\r
+__IO_EXTERN ADCR1STR adcr1;  \r
+#define ADCR1 adcr1.byte\r
+#define ADCR1_D9 adcr1.bit._D9\r
+#define ADCR1_D8 adcr1.bit._D8\r
+__IO_EXTERN ADCR0STR adcr0;  \r
+#define ADCR0 adcr0.byte\r
+#define ADCR0_D7 adcr0.bit._D7\r
+#define ADCR0_D6 adcr0.bit._D6\r
+#define ADCR0_D5 adcr0.bit._D5\r
+#define ADCR0_D4 adcr0.bit._D4\r
+#define ADCR0_D3 adcr0.bit._D3\r
+#define ADCR0_D2 adcr0.bit._D2\r
+#define ADCR0_D1 adcr0.bit._D1\r
+#define ADCR0_D0 adcr0.bit._D0\r
+__IO_EXTERN IO_WORD adcr;  \r
+#define ADCR adcr\r
+__IO_EXTERN ADCT1STR adct1;  \r
+#define ADCT1 adct1.byte\r
+#define ADCT1_CT5 adct1.bit._CT5\r
+#define ADCT1_CT4 adct1.bit._CT4\r
+#define ADCT1_CT3 adct1.bit._CT3\r
+#define ADCT1_CT2 adct1.bit._CT2\r
+#define ADCT1_CT1 adct1.bit._CT1\r
+#define ADCT1_CT0 adct1.bit._CT0\r
+#define ADCT1_ST9 adct1.bit._ST9\r
+#define ADCT1_ST8 adct1.bit._ST8\r
+__IO_EXTERN ADCT0STR adct0;  \r
+#define ADCT0 adct0.byte\r
+#define ADCT0_ST7 adct0.bit._ST7\r
+#define ADCT0_ST6 adct0.bit._ST6\r
+#define ADCT0_ST5 adct0.bit._ST5\r
+#define ADCT0_ST4 adct0.bit._ST4\r
+#define ADCT0_ST3 adct0.bit._ST3\r
+#define ADCT0_ST2 adct0.bit._ST2\r
+#define ADCT0_ST1 adct0.bit._ST1\r
+#define ADCT0_ST0 adct0.bit._ST0\r
+__IO_EXTERN IO_WORD adct;  \r
+#define ADCT adct\r
+__IO_EXTERN ADSCHSTR adsch;  \r
+#define ADSCH adsch.byte\r
+#define ADSCH_ANS4 adsch.bit._ANS4\r
+#define ADSCH_ANS3 adsch.bit._ANS3\r
+#define ADSCH_ANS2 adsch.bit._ANS2\r
+#define ADSCH_ANS1 adsch.bit._ANS1\r
+#define ADSCH_ASN0 adsch.bit._ASN0\r
+#define ADSCH_ANS adsch.bitc._ANS\r
+__IO_EXTERN ADECHSTR adech;  \r
+#define ADECH adech.byte\r
+#define ADECH_ANE4 adech.bit._ANE4\r
+#define ADECH_ANE3 adech.bit._ANE3\r
+#define ADECH_ANE2 adech.bit._ANE2\r
+#define ADECH_ANE1 adech.bit._ANE1\r
+#define ADECH_ANE0 adech.bit._ANE0\r
+#define ADECH_ANE adech.bitc._ANE\r
+__IO_EXTERN ACSR0STR acsr0;   /* Alarm Comparator 0-1 */\r
+#define ACSR0 acsr0.byte\r
+#define ACSR0_MD acsr0.bit._MD\r
+#define ACSR0_OV_EN acsr0.bit._OV_EN\r
+#define ACSR0_UV_EN acsr0.bit._UV_EN\r
+#define ACSR0_OUT2 acsr0.bit._OUT2\r
+#define ACSR0_OUT1 acsr0.bit._OUT1\r
+#define ACSR0_IRQ acsr0.bit._IRQ\r
+#define ACSR0_IEN acsr0.bit._IEN\r
+#define ACSR0_PD acsr0.bit._PD\r
+__IO_EXTERN TMRLR0STR tmrlr0;   /* Reload Timer 0 */\r
+#define TMRLR0 tmrlr0.word\r
+#define TMRLR0_D15 tmrlr0.bit._D15\r
+#define TMRLR0_D14 tmrlr0.bit._D14\r
+#define TMRLR0_D13 tmrlr0.bit._D13\r
+#define TMRLR0_D12 tmrlr0.bit._D12\r
+#define TMRLR0_D11 tmrlr0.bit._D11\r
+#define TMRLR0_D10 tmrlr0.bit._D10\r
+#define TMRLR0_D9 tmrlr0.bit._D9\r
+#define TMRLR0_D8 tmrlr0.bit._D8\r
+#define TMRLR0_D7 tmrlr0.bit._D7\r
+#define TMRLR0_D6 tmrlr0.bit._D6\r
+#define TMRLR0_D5 tmrlr0.bit._D5\r
+#define TMRLR0_D4 tmrlr0.bit._D4\r
+#define TMRLR0_D3 tmrlr0.bit._D3\r
+#define TMRLR0_D2 tmrlr0.bit._D2\r
+#define TMRLR0_D1 tmrlr0.bit._D1\r
+#define TMRLR0_D0 tmrlr0.bit._D0\r
+__IO_EXTERN TMR0STR tmr0;  \r
+#define TMR0 tmr0.word\r
+#define TMR0_D15 tmr0.bit._D15\r
+#define TMR0_D14 tmr0.bit._D14\r
+#define TMR0_D13 tmr0.bit._D13\r
+#define TMR0_D12 tmr0.bit._D12\r
+#define TMR0_D11 tmr0.bit._D11\r
+#define TMR0_D10 tmr0.bit._D10\r
+#define TMR0_D9 tmr0.bit._D9\r
+#define TMR0_D8 tmr0.bit._D8\r
+#define TMR0_D7 tmr0.bit._D7\r
+#define TMR0_D6 tmr0.bit._D6\r
+#define TMR0_D5 tmr0.bit._D5\r
+#define TMR0_D4 tmr0.bit._D4\r
+#define TMR0_D3 tmr0.bit._D3\r
+#define TMR0_D2 tmr0.bit._D2\r
+#define TMR0_D1 tmr0.bit._D1\r
+#define TMR0_D0 tmr0.bit._D0\r
+__IO_EXTERN TMCSR0STR tmcsr0;  \r
+#define TMCSR0 tmcsr0.word\r
+#define TMCSR0_CSL2 tmcsr0.bit._CSL2\r
+#define TMCSR0_CSL1 tmcsr0.bit._CSL1\r
+#define TMCSR0_CSL0 tmcsr0.bit._CSL0\r
+#define TMCSR0_MOD2 tmcsr0.bit._MOD2\r
+#define TMCSR0_MOD1 tmcsr0.bit._MOD1\r
+#define TMCSR0_MOD0 tmcsr0.bit._MOD0\r
+#define TMCSR0_OUTL tmcsr0.bit._OUTL\r
+#define TMCSR0_RELD tmcsr0.bit._RELD\r
+#define TMCSR0_INTE tmcsr0.bit._INTE\r
+#define TMCSR0_UF tmcsr0.bit._UF\r
+#define TMCSR0_CNTE tmcsr0.bit._CNTE\r
+#define TMCSR0_TRG tmcsr0.bit._TRG\r
+#define TMCSR0_CSL tmcsr0.bitc._CSL\r
+#define TMCSR0_MOD tmcsr0.bitc._MOD\r
+__IO_EXTERN TMCSRH0STR tmcsrh0;  \r
+#define TMCSRH0 tmcsrh0.byte\r
+#define TMCSRH0_CSL2 tmcsrh0.bit._CSL2\r
+#define TMCSRH0_CSL1 tmcsrh0.bit._CSL1\r
+#define TMCSRH0_CSL0 tmcsrh0.bit._CSL0\r
+#define TMCSRH0_MOD2 tmcsrh0.bit._MOD2\r
+#define TMCSRH0_MOD1 tmcsrh0.bit._MOD1\r
+#define TMCSRH0_CSL tmcsrh0.bitc._CSL\r
+__IO_EXTERN TMCSRL0STR tmcsrl0;  \r
+#define TMCSRL0 tmcsrl0.byte\r
+#define TMCSRL0_MOD0 tmcsrl0.bit._MOD0\r
+#define TMCSRL0_OUTL tmcsrl0.bit._OUTL\r
+#define TMCSRL0_RELD tmcsrl0.bit._RELD\r
+#define TMCSRL0_INTE tmcsrl0.bit._INTE\r
+#define TMCSRL0_UF tmcsrl0.bit._UF\r
+#define TMCSRL0_CNTE tmcsrl0.bit._CNTE\r
+#define TMCSRL0_TRG tmcsrl0.bit._TRG\r
+__IO_EXTERN TMRLR1STR tmrlr1;   /* Reload Timer 1 */\r
+#define TMRLR1 tmrlr1.word\r
+#define TMRLR1_D15 tmrlr1.bit._D15\r
+#define TMRLR1_D14 tmrlr1.bit._D14\r
+#define TMRLR1_D13 tmrlr1.bit._D13\r
+#define TMRLR1_D12 tmrlr1.bit._D12\r
+#define TMRLR1_D11 tmrlr1.bit._D11\r
+#define TMRLR1_D10 tmrlr1.bit._D10\r
+#define TMRLR1_D9 tmrlr1.bit._D9\r
+#define TMRLR1_D8 tmrlr1.bit._D8\r
+#define TMRLR1_D7 tmrlr1.bit._D7\r
+#define TMRLR1_D6 tmrlr1.bit._D6\r
+#define TMRLR1_D5 tmrlr1.bit._D5\r
+#define TMRLR1_D4 tmrlr1.bit._D4\r
+#define TMRLR1_D3 tmrlr1.bit._D3\r
+#define TMRLR1_D2 tmrlr1.bit._D2\r
+#define TMRLR1_D1 tmrlr1.bit._D1\r
+#define TMRLR1_D0 tmrlr1.bit._D0\r
+__IO_EXTERN TMR1STR tmr1;  \r
+#define TMR1 tmr1.word\r
+#define TMR1_D15 tmr1.bit._D15\r
+#define TMR1_D14 tmr1.bit._D14\r
+#define TMR1_D13 tmr1.bit._D13\r
+#define TMR1_D12 tmr1.bit._D12\r
+#define TMR1_D11 tmr1.bit._D11\r
+#define TMR1_D10 tmr1.bit._D10\r
+#define TMR1_D9 tmr1.bit._D9\r
+#define TMR1_D8 tmr1.bit._D8\r
+#define TMR1_D7 tmr1.bit._D7\r
+#define TMR1_D6 tmr1.bit._D6\r
+#define TMR1_D5 tmr1.bit._D5\r
+#define TMR1_D4 tmr1.bit._D4\r
+#define TMR1_D3 tmr1.bit._D3\r
+#define TMR1_D2 tmr1.bit._D2\r
+#define TMR1_D1 tmr1.bit._D1\r
+#define TMR1_D0 tmr1.bit._D0\r
+__IO_EXTERN TMCSR1STR tmcsr1;  \r
+#define TMCSR1 tmcsr1.word\r
+#define TMCSR1_CSL2 tmcsr1.bit._CSL2\r
+#define TMCSR1_CSL1 tmcsr1.bit._CSL1\r
+#define TMCSR1_CSL0 tmcsr1.bit._CSL0\r
+#define TMCSR1_MOD2 tmcsr1.bit._MOD2\r
+#define TMCSR1_MOD1 tmcsr1.bit._MOD1\r
+#define TMCSR1_MOD0 tmcsr1.bit._MOD0\r
+#define TMCSR1_OUTL tmcsr1.bit._OUTL\r
+#define TMCSR1_RELD tmcsr1.bit._RELD\r
+#define TMCSR1_INTE tmcsr1.bit._INTE\r
+#define TMCSR1_UF tmcsr1.bit._UF\r
+#define TMCSR1_CNTE tmcsr1.bit._CNTE\r
+#define TMCSR1_TRG tmcsr1.bit._TRG\r
+#define TMCSR1_CSL tmcsr1.bitc._CSL\r
+#define TMCSR1_MOD tmcsr1.bitc._MOD\r
+__IO_EXTERN TMCSRH1STR tmcsrh1;  \r
+#define TMCSRH1 tmcsrh1.byte\r
+#define TMCSRH1_CSL2 tmcsrh1.bit._CSL2\r
+#define TMCSRH1_CSL1 tmcsrh1.bit._CSL1\r
+#define TMCSRH1_CSL0 tmcsrh1.bit._CSL0\r
+#define TMCSRH1_MOD2 tmcsrh1.bit._MOD2\r
+#define TMCSRH1_MOD1 tmcsrh1.bit._MOD1\r
+#define TMCSRH1_CSL tmcsrh1.bitc._CSL\r
+__IO_EXTERN TMCSRL1STR tmcsrl1;  \r
+#define TMCSRL1 tmcsrl1.byte\r
+#define TMCSRL1_MOD0 tmcsrl1.bit._MOD0\r
+#define TMCSRL1_OUTL tmcsrl1.bit._OUTL\r
+#define TMCSRL1_RELD tmcsrl1.bit._RELD\r
+#define TMCSRL1_INTE tmcsrl1.bit._INTE\r
+#define TMCSRL1_UF tmcsrl1.bit._UF\r
+#define TMCSRL1_CNTE tmcsrl1.bit._CNTE\r
+#define TMCSRL1_TRG tmcsrl1.bit._TRG\r
+__IO_EXTERN TMRLR2STR tmrlr2;   /* Reload Timer 2 */\r
+#define TMRLR2 tmrlr2.word\r
+#define TMRLR2_D15 tmrlr2.bit._D15\r
+#define TMRLR2_D14 tmrlr2.bit._D14\r
+#define TMRLR2_D13 tmrlr2.bit._D13\r
+#define TMRLR2_D12 tmrlr2.bit._D12\r
+#define TMRLR2_D11 tmrlr2.bit._D11\r
+#define TMRLR2_D10 tmrlr2.bit._D10\r
+#define TMRLR2_D9 tmrlr2.bit._D9\r
+#define TMRLR2_D8 tmrlr2.bit._D8\r
+#define TMRLR2_D7 tmrlr2.bit._D7\r
+#define TMRLR2_D6 tmrlr2.bit._D6\r
+#define TMRLR2_D5 tmrlr2.bit._D5\r
+#define TMRLR2_D4 tmrlr2.bit._D4\r
+#define TMRLR2_D3 tmrlr2.bit._D3\r
+#define TMRLR2_D2 tmrlr2.bit._D2\r
+#define TMRLR2_D1 tmrlr2.bit._D1\r
+#define TMRLR2_D0 tmrlr2.bit._D0\r
+__IO_EXTERN TMR2STR tmr2;  \r
+#define TMR2 tmr2.word\r
+#define TMR2_D15 tmr2.bit._D15\r
+#define TMR2_D14 tmr2.bit._D14\r
+#define TMR2_D13 tmr2.bit._D13\r
+#define TMR2_D12 tmr2.bit._D12\r
+#define TMR2_D11 tmr2.bit._D11\r
+#define TMR2_D10 tmr2.bit._D10\r
+#define TMR2_D9 tmr2.bit._D9\r
+#define TMR2_D8 tmr2.bit._D8\r
+#define TMR2_D7 tmr2.bit._D7\r
+#define TMR2_D6 tmr2.bit._D6\r
+#define TMR2_D5 tmr2.bit._D5\r
+#define TMR2_D4 tmr2.bit._D4\r
+#define TMR2_D3 tmr2.bit._D3\r
+#define TMR2_D2 tmr2.bit._D2\r
+#define TMR2_D1 tmr2.bit._D1\r
+#define TMR2_D0 tmr2.bit._D0\r
+__IO_EXTERN TMCSR2STR tmcsr2;  \r
+#define TMCSR2 tmcsr2.word\r
+#define TMCSR2_CSL2 tmcsr2.bit._CSL2\r
+#define TMCSR2_CSL1 tmcsr2.bit._CSL1\r
+#define TMCSR2_CSL0 tmcsr2.bit._CSL0\r
+#define TMCSR2_MOD2 tmcsr2.bit._MOD2\r
+#define TMCSR2_MOD1 tmcsr2.bit._MOD1\r
+#define TMCSR2_MOD0 tmcsr2.bit._MOD0\r
+#define TMCSR2_OUTL tmcsr2.bit._OUTL\r
+#define TMCSR2_RELD tmcsr2.bit._RELD\r
+#define TMCSR2_INTE tmcsr2.bit._INTE\r
+#define TMCSR2_UF tmcsr2.bit._UF\r
+#define TMCSR2_CNTE tmcsr2.bit._CNTE\r
+#define TMCSR2_TRG tmcsr2.bit._TRG\r
+#define TMCSR2_CSL tmcsr2.bitc._CSL\r
+#define TMCSR2_MOD tmcsr2.bitc._MOD\r
+__IO_EXTERN TMCSRH2STR tmcsrh2;  \r
+#define TMCSRH2 tmcsrh2.byte\r
+#define TMCSRH2_CSL2 tmcsrh2.bit._CSL2\r
+#define TMCSRH2_CSL1 tmcsrh2.bit._CSL1\r
+#define TMCSRH2_CSL0 tmcsrh2.bit._CSL0\r
+#define TMCSRH2_MOD2 tmcsrh2.bit._MOD2\r
+#define TMCSRH2_MOD1 tmcsrh2.bit._MOD1\r
+#define TMCSRH2_CSL tmcsrh2.bitc._CSL\r
+__IO_EXTERN TMCSRL2STR tmcsrl2;  \r
+#define TMCSRL2 tmcsrl2.byte\r
+#define TMCSRL2_MOD0 tmcsrl2.bit._MOD0\r
+#define TMCSRL2_OUTL tmcsrl2.bit._OUTL\r
+#define TMCSRL2_RELD tmcsrl2.bit._RELD\r
+#define TMCSRL2_INTE tmcsrl2.bit._INTE\r
+#define TMCSRL2_UF tmcsrl2.bit._UF\r
+#define TMCSRL2_CNTE tmcsrl2.bit._CNTE\r
+#define TMCSRL2_TRG tmcsrl2.bit._TRG\r
+__IO_EXTERN TMRLR3STR tmrlr3;   /* Reload Timer 3 */\r
+#define TMRLR3 tmrlr3.word\r
+#define TMRLR3_D15 tmrlr3.bit._D15\r
+#define TMRLR3_D14 tmrlr3.bit._D14\r
+#define TMRLR3_D13 tmrlr3.bit._D13\r
+#define TMRLR3_D12 tmrlr3.bit._D12\r
+#define TMRLR3_D11 tmrlr3.bit._D11\r
+#define TMRLR3_D10 tmrlr3.bit._D10\r
+#define TMRLR3_D9 tmrlr3.bit._D9\r
+#define TMRLR3_D8 tmrlr3.bit._D8\r
+#define TMRLR3_D7 tmrlr3.bit._D7\r
+#define TMRLR3_D6 tmrlr3.bit._D6\r
+#define TMRLR3_D5 tmrlr3.bit._D5\r
+#define TMRLR3_D4 tmrlr3.bit._D4\r
+#define TMRLR3_D3 tmrlr3.bit._D3\r
+#define TMRLR3_D2 tmrlr3.bit._D2\r
+#define TMRLR3_D1 tmrlr3.bit._D1\r
+#define TMRLR3_D0 tmrlr3.bit._D0\r
+__IO_EXTERN TMR3STR tmr3;  \r
+#define TMR3 tmr3.word\r
+#define TMR3_D15 tmr3.bit._D15\r
+#define TMR3_D14 tmr3.bit._D14\r
+#define TMR3_D13 tmr3.bit._D13\r
+#define TMR3_D12 tmr3.bit._D12\r
+#define TMR3_D11 tmr3.bit._D11\r
+#define TMR3_D10 tmr3.bit._D10\r
+#define TMR3_D9 tmr3.bit._D9\r
+#define TMR3_D8 tmr3.bit._D8\r
+#define TMR3_D7 tmr3.bit._D7\r
+#define TMR3_D6 tmr3.bit._D6\r
+#define TMR3_D5 tmr3.bit._D5\r
+#define TMR3_D4 tmr3.bit._D4\r
+#define TMR3_D3 tmr3.bit._D3\r
+#define TMR3_D2 tmr3.bit._D2\r
+#define TMR3_D1 tmr3.bit._D1\r
+#define TMR3_D0 tmr3.bit._D0\r
+__IO_EXTERN TMCSR3STR tmcsr3;  \r
+#define TMCSR3 tmcsr3.word\r
+#define TMCSR3_CSL2 tmcsr3.bit._CSL2\r
+#define TMCSR3_CSL1 tmcsr3.bit._CSL1\r
+#define TMCSR3_CSL0 tmcsr3.bit._CSL0\r
+#define TMCSR3_MOD2 tmcsr3.bit._MOD2\r
+#define TMCSR3_MOD1 tmcsr3.bit._MOD1\r
+#define TMCSR3_MOD0 tmcsr3.bit._MOD0\r
+#define TMCSR3_OUTL tmcsr3.bit._OUTL\r
+#define TMCSR3_RELD tmcsr3.bit._RELD\r
+#define TMCSR3_INTE tmcsr3.bit._INTE\r
+#define TMCSR3_UF tmcsr3.bit._UF\r
+#define TMCSR3_CNTE tmcsr3.bit._CNTE\r
+#define TMCSR3_TRG tmcsr3.bit._TRG\r
+#define TMCSR3_CSL tmcsr3.bitc._CSL\r
+#define TMCSR3_MOD tmcsr3.bitc._MOD\r
+__IO_EXTERN TMCSRH3STR tmcsrh3;  \r
+#define TMCSRH3 tmcsrh3.byte\r
+#define TMCSRH3_CSL2 tmcsrh3.bit._CSL2\r
+#define TMCSRH3_CSL1 tmcsrh3.bit._CSL1\r
+#define TMCSRH3_CSL0 tmcsrh3.bit._CSL0\r
+#define TMCSRH3_MOD2 tmcsrh3.bit._MOD2\r
+#define TMCSRH3_MOD1 tmcsrh3.bit._MOD1\r
+#define TMCSRH3_CSL tmcsrh3.bitc._CSL\r
+__IO_EXTERN TMCSRL3STR tmcsrl3;  \r
+#define TMCSRL3 tmcsrl3.byte\r
+#define TMCSRL3_MOD0 tmcsrl3.bit._MOD0\r
+#define TMCSRL3_OUTL tmcsrl3.bit._OUTL\r
+#define TMCSRL3_RELD tmcsrl3.bit._RELD\r
+#define TMCSRL3_INTE tmcsrl3.bit._INTE\r
+#define TMCSRL3_UF tmcsrl3.bit._UF\r
+#define TMCSRL3_CNTE tmcsrl3.bit._CNTE\r
+#define TMCSRL3_TRG tmcsrl3.bit._TRG\r
+__IO_EXTERN TMRLR4STR tmrlr4;   /* Reload Timer 4 */\r
+#define TMRLR4 tmrlr4.word\r
+#define TMRLR4_D15 tmrlr4.bit._D15\r
+#define TMRLR4_D14 tmrlr4.bit._D14\r
+#define TMRLR4_D13 tmrlr4.bit._D13\r
+#define TMRLR4_D12 tmrlr4.bit._D12\r
+#define TMRLR4_D11 tmrlr4.bit._D11\r
+#define TMRLR4_D10 tmrlr4.bit._D10\r
+#define TMRLR4_D9 tmrlr4.bit._D9\r
+#define TMRLR4_D8 tmrlr4.bit._D8\r
+#define TMRLR4_D7 tmrlr4.bit._D7\r
+#define TMRLR4_D6 tmrlr4.bit._D6\r
+#define TMRLR4_D5 tmrlr4.bit._D5\r
+#define TMRLR4_D4 tmrlr4.bit._D4\r
+#define TMRLR4_D3 tmrlr4.bit._D3\r
+#define TMRLR4_D2 tmrlr4.bit._D2\r
+#define TMRLR4_D1 tmrlr4.bit._D1\r
+#define TMRLR4_D0 tmrlr4.bit._D0\r
+__IO_EXTERN TMR4STR tmr4;  \r
+#define TMR4 tmr4.word\r
+#define TMR4_D15 tmr4.bit._D15\r
+#define TMR4_D14 tmr4.bit._D14\r
+#define TMR4_D13 tmr4.bit._D13\r
+#define TMR4_D12 tmr4.bit._D12\r
+#define TMR4_D11 tmr4.bit._D11\r
+#define TMR4_D10 tmr4.bit._D10\r
+#define TMR4_D9 tmr4.bit._D9\r
+#define TMR4_D8 tmr4.bit._D8\r
+#define TMR4_D7 tmr4.bit._D7\r
+#define TMR4_D6 tmr4.bit._D6\r
+#define TMR4_D5 tmr4.bit._D5\r
+#define TMR4_D4 tmr4.bit._D4\r
+#define TMR4_D3 tmr4.bit._D3\r
+#define TMR4_D2 tmr4.bit._D2\r
+#define TMR4_D1 tmr4.bit._D1\r
+#define TMR4_D0 tmr4.bit._D0\r
+__IO_EXTERN TMCSR4STR tmcsr4;  \r
+#define TMCSR4 tmcsr4.word\r
+#define TMCSR4_CSL2 tmcsr4.bit._CSL2\r
+#define TMCSR4_CSL1 tmcsr4.bit._CSL1\r
+#define TMCSR4_CSL0 tmcsr4.bit._CSL0\r
+#define TMCSR4_MOD2 tmcsr4.bit._MOD2\r
+#define TMCSR4_MOD1 tmcsr4.bit._MOD1\r
+#define TMCSR4_MOD0 tmcsr4.bit._MOD0\r
+#define TMCSR4_OUTL tmcsr4.bit._OUTL\r
+#define TMCSR4_RELD tmcsr4.bit._RELD\r
+#define TMCSR4_INTE tmcsr4.bit._INTE\r
+#define TMCSR4_UF tmcsr4.bit._UF\r
+#define TMCSR4_CNTE tmcsr4.bit._CNTE\r
+#define TMCSR4_TRG tmcsr4.bit._TRG\r
+#define TMCSR4_CSL tmcsr4.bitc._CSL\r
+#define TMCSR4_MOD tmcsr4.bitc._MOD\r
+__IO_EXTERN TMCSRH4STR tmcsrh4;  \r
+#define TMCSRH4 tmcsrh4.byte\r
+#define TMCSRH4_CSL2 tmcsrh4.bit._CSL2\r
+#define TMCSRH4_CSL1 tmcsrh4.bit._CSL1\r
+#define TMCSRH4_CSL0 tmcsrh4.bit._CSL0\r
+#define TMCSRH4_MOD2 tmcsrh4.bit._MOD2\r
+#define TMCSRH4_MOD1 tmcsrh4.bit._MOD1\r
+#define TMCSRH4_CSL tmcsrh4.bitc._CSL\r
+__IO_EXTERN TMCSRL4STR tmcsrl4;  \r
+#define TMCSRL4 tmcsrl4.byte\r
+#define TMCSRL4_MOD0 tmcsrl4.bit._MOD0\r
+#define TMCSRL4_OUTL tmcsrl4.bit._OUTL\r
+#define TMCSRL4_RELD tmcsrl4.bit._RELD\r
+#define TMCSRL4_INTE tmcsrl4.bit._INTE\r
+#define TMCSRL4_UF tmcsrl4.bit._UF\r
+#define TMCSRL4_CNTE tmcsrl4.bit._CNTE\r
+#define TMCSRL4_TRG tmcsrl4.bit._TRG\r
+__IO_EXTERN TMRLR5STR tmrlr5;   /* Reload Timer 5 */\r
+#define TMRLR5 tmrlr5.word\r
+#define TMRLR5_D15 tmrlr5.bit._D15\r
+#define TMRLR5_D14 tmrlr5.bit._D14\r
+#define TMRLR5_D13 tmrlr5.bit._D13\r
+#define TMRLR5_D12 tmrlr5.bit._D12\r
+#define TMRLR5_D11 tmrlr5.bit._D11\r
+#define TMRLR5_D10 tmrlr5.bit._D10\r
+#define TMRLR5_D9 tmrlr5.bit._D9\r
+#define TMRLR5_D8 tmrlr5.bit._D8\r
+#define TMRLR5_D7 tmrlr5.bit._D7\r
+#define TMRLR5_D6 tmrlr5.bit._D6\r
+#define TMRLR5_D5 tmrlr5.bit._D5\r
+#define TMRLR5_D4 tmrlr5.bit._D4\r
+#define TMRLR5_D3 tmrlr5.bit._D3\r
+#define TMRLR5_D2 tmrlr5.bit._D2\r
+#define TMRLR5_D1 tmrlr5.bit._D1\r
+#define TMRLR5_D0 tmrlr5.bit._D0\r
+__IO_EXTERN TMR5STR tmr5;  \r
+#define TMR5 tmr5.word\r
+#define TMR5_D15 tmr5.bit._D15\r
+#define TMR5_D14 tmr5.bit._D14\r
+#define TMR5_D13 tmr5.bit._D13\r
+#define TMR5_D12 tmr5.bit._D12\r
+#define TMR5_D11 tmr5.bit._D11\r
+#define TMR5_D10 tmr5.bit._D10\r
+#define TMR5_D9 tmr5.bit._D9\r
+#define TMR5_D8 tmr5.bit._D8\r
+#define TMR5_D7 tmr5.bit._D7\r
+#define TMR5_D6 tmr5.bit._D6\r
+#define TMR5_D5 tmr5.bit._D5\r
+#define TMR5_D4 tmr5.bit._D4\r
+#define TMR5_D3 tmr5.bit._D3\r
+#define TMR5_D2 tmr5.bit._D2\r
+#define TMR5_D1 tmr5.bit._D1\r
+#define TMR5_D0 tmr5.bit._D0\r
+__IO_EXTERN TMCSR5STR tmcsr5;  \r
+#define TMCSR5 tmcsr5.word\r
+#define TMCSR5_CSL2 tmcsr5.bit._CSL2\r
+#define TMCSR5_CSL1 tmcsr5.bit._CSL1\r
+#define TMCSR5_CSL0 tmcsr5.bit._CSL0\r
+#define TMCSR5_MOD2 tmcsr5.bit._MOD2\r
+#define TMCSR5_MOD1 tmcsr5.bit._MOD1\r
+#define TMCSR5_MOD0 tmcsr5.bit._MOD0\r
+#define TMCSR5_OUTL tmcsr5.bit._OUTL\r
+#define TMCSR5_RELD tmcsr5.bit._RELD\r
+#define TMCSR5_INTE tmcsr5.bit._INTE\r
+#define TMCSR5_UF tmcsr5.bit._UF\r
+#define TMCSR5_CNTE tmcsr5.bit._CNTE\r
+#define TMCSR5_TRG tmcsr5.bit._TRG\r
+#define TMCSR5_CSL tmcsr5.bitc._CSL\r
+#define TMCSR5_MOD tmcsr5.bitc._MOD\r
+__IO_EXTERN TMCSRH5STR tmcsrh5;  \r
+#define TMCSRH5 tmcsrh5.byte\r
+#define TMCSRH5_CSL2 tmcsrh5.bit._CSL2\r
+#define TMCSRH5_CSL1 tmcsrh5.bit._CSL1\r
+#define TMCSRH5_CSL0 tmcsrh5.bit._CSL0\r
+#define TMCSRH5_MOD2 tmcsrh5.bit._MOD2\r
+#define TMCSRH5_MOD1 tmcsrh5.bit._MOD1\r
+#define TMCSRH5_CSL tmcsrh5.bitc._CSL\r
+__IO_EXTERN TMCSRL5STR tmcsrl5;  \r
+#define TMCSRL5 tmcsrl5.byte\r
+#define TMCSRL5_MOD0 tmcsrl5.bit._MOD0\r
+#define TMCSRL5_OUTL tmcsrl5.bit._OUTL\r
+#define TMCSRL5_RELD tmcsrl5.bit._RELD\r
+#define TMCSRL5_INTE tmcsrl5.bit._INTE\r
+#define TMCSRL5_UF tmcsrl5.bit._UF\r
+#define TMCSRL5_CNTE tmcsrl5.bit._CNTE\r
+#define TMCSRL5_TRG tmcsrl5.bit._TRG\r
+__IO_EXTERN TMRLR6STR tmrlr6;   /* Reload Timer 6 */\r
+#define TMRLR6 tmrlr6.word\r
+#define TMRLR6_D15 tmrlr6.bit._D15\r
+#define TMRLR6_D14 tmrlr6.bit._D14\r
+#define TMRLR6_D13 tmrlr6.bit._D13\r
+#define TMRLR6_D12 tmrlr6.bit._D12\r
+#define TMRLR6_D11 tmrlr6.bit._D11\r
+#define TMRLR6_D10 tmrlr6.bit._D10\r
+#define TMRLR6_D9 tmrlr6.bit._D9\r
+#define TMRLR6_D8 tmrlr6.bit._D8\r
+#define TMRLR6_D7 tmrlr6.bit._D7\r
+#define TMRLR6_D6 tmrlr6.bit._D6\r
+#define TMRLR6_D5 tmrlr6.bit._D5\r
+#define TMRLR6_D4 tmrlr6.bit._D4\r
+#define TMRLR6_D3 tmrlr6.bit._D3\r
+#define TMRLR6_D2 tmrlr6.bit._D2\r
+#define TMRLR6_D1 tmrlr6.bit._D1\r
+#define TMRLR6_D0 tmrlr6.bit._D0\r
+__IO_EXTERN TMR6STR tmr6;  \r
+#define TMR6 tmr6.word\r
+#define TMR6_D15 tmr6.bit._D15\r
+#define TMR6_D14 tmr6.bit._D14\r
+#define TMR6_D13 tmr6.bit._D13\r
+#define TMR6_D12 tmr6.bit._D12\r
+#define TMR6_D11 tmr6.bit._D11\r
+#define TMR6_D10 tmr6.bit._D10\r
+#define TMR6_D9 tmr6.bit._D9\r
+#define TMR6_D8 tmr6.bit._D8\r
+#define TMR6_D7 tmr6.bit._D7\r
+#define TMR6_D6 tmr6.bit._D6\r
+#define TMR6_D5 tmr6.bit._D5\r
+#define TMR6_D4 tmr6.bit._D4\r
+#define TMR6_D3 tmr6.bit._D3\r
+#define TMR6_D2 tmr6.bit._D2\r
+#define TMR6_D1 tmr6.bit._D1\r
+#define TMR6_D0 tmr6.bit._D0\r
+__IO_EXTERN TMCSR6STR tmcsr6;  \r
+#define TMCSR6 tmcsr6.word\r
+#define TMCSR6_CSL2 tmcsr6.bit._CSL2\r
+#define TMCSR6_CSL1 tmcsr6.bit._CSL1\r
+#define TMCSR6_CSL0 tmcsr6.bit._CSL0\r
+#define TMCSR6_MOD2 tmcsr6.bit._MOD2\r
+#define TMCSR6_MOD1 tmcsr6.bit._MOD1\r
+#define TMCSR6_MOD0 tmcsr6.bit._MOD0\r
+#define TMCSR6_OUTL tmcsr6.bit._OUTL\r
+#define TMCSR6_RELD tmcsr6.bit._RELD\r
+#define TMCSR6_INTE tmcsr6.bit._INTE\r
+#define TMCSR6_UF tmcsr6.bit._UF\r
+#define TMCSR6_CNTE tmcsr6.bit._CNTE\r
+#define TMCSR6_TRG tmcsr6.bit._TRG\r
+#define TMCSR6_CSL tmcsr6.bitc._CSL\r
+#define TMCSR6_MOD tmcsr6.bitc._MOD\r
+__IO_EXTERN TMCSRH6STR tmcsrh6;  \r
+#define TMCSRH6 tmcsrh6.byte\r
+#define TMCSRH6_CSL2 tmcsrh6.bit._CSL2\r
+#define TMCSRH6_CSL1 tmcsrh6.bit._CSL1\r
+#define TMCSRH6_CSL0 tmcsrh6.bit._CSL0\r
+#define TMCSRH6_MOD2 tmcsrh6.bit._MOD2\r
+#define TMCSRH6_MOD1 tmcsrh6.bit._MOD1\r
+#define TMCSRH6_CSL tmcsrh6.bitc._CSL\r
+__IO_EXTERN TMCSRL6STR tmcsrl6;  \r
+#define TMCSRL6 tmcsrl6.byte\r
+#define TMCSRL6_MOD0 tmcsrl6.bit._MOD0\r
+#define TMCSRL6_OUTL tmcsrl6.bit._OUTL\r
+#define TMCSRL6_RELD tmcsrl6.bit._RELD\r
+#define TMCSRL6_INTE tmcsrl6.bit._INTE\r
+#define TMCSRL6_UF tmcsrl6.bit._UF\r
+#define TMCSRL6_CNTE tmcsrl6.bit._CNTE\r
+#define TMCSRL6_TRG tmcsrl6.bit._TRG\r
+__IO_EXTERN TMRLR7STR tmrlr7;   /* Reload Timer 7 */\r
+#define TMRLR7 tmrlr7.word\r
+#define TMRLR7_D15 tmrlr7.bit._D15\r
+#define TMRLR7_D14 tmrlr7.bit._D14\r
+#define TMRLR7_D13 tmrlr7.bit._D13\r
+#define TMRLR7_D12 tmrlr7.bit._D12\r
+#define TMRLR7_D11 tmrlr7.bit._D11\r
+#define TMRLR7_D10 tmrlr7.bit._D10\r
+#define TMRLR7_D9 tmrlr7.bit._D9\r
+#define TMRLR7_D8 tmrlr7.bit._D8\r
+#define TMRLR7_D7 tmrlr7.bit._D7\r
+#define TMRLR7_D6 tmrlr7.bit._D6\r
+#define TMRLR7_D5 tmrlr7.bit._D5\r
+#define TMRLR7_D4 tmrlr7.bit._D4\r
+#define TMRLR7_D3 tmrlr7.bit._D3\r
+#define TMRLR7_D2 tmrlr7.bit._D2\r
+#define TMRLR7_D1 tmrlr7.bit._D1\r
+#define TMRLR7_D0 tmrlr7.bit._D0\r
+__IO_EXTERN TMR7STR tmr7;  \r
+#define TMR7 tmr7.word\r
+#define TMR7_D15 tmr7.bit._D15\r
+#define TMR7_D14 tmr7.bit._D14\r
+#define TMR7_D13 tmr7.bit._D13\r
+#define TMR7_D12 tmr7.bit._D12\r
+#define TMR7_D11 tmr7.bit._D11\r
+#define TMR7_D10 tmr7.bit._D10\r
+#define TMR7_D9 tmr7.bit._D9\r
+#define TMR7_D8 tmr7.bit._D8\r
+#define TMR7_D7 tmr7.bit._D7\r
+#define TMR7_D6 tmr7.bit._D6\r
+#define TMR7_D5 tmr7.bit._D5\r
+#define TMR7_D4 tmr7.bit._D4\r
+#define TMR7_D3 tmr7.bit._D3\r
+#define TMR7_D2 tmr7.bit._D2\r
+#define TMR7_D1 tmr7.bit._D1\r
+#define TMR7_D0 tmr7.bit._D0\r
+__IO_EXTERN TMCSR7STR tmcsr7;  \r
+#define TMCSR7 tmcsr7.word\r
+#define TMCSR7_CSL2 tmcsr7.bit._CSL2\r
+#define TMCSR7_CSL1 tmcsr7.bit._CSL1\r
+#define TMCSR7_CSL0 tmcsr7.bit._CSL0\r
+#define TMCSR7_MOD2 tmcsr7.bit._MOD2\r
+#define TMCSR7_MOD1 tmcsr7.bit._MOD1\r
+#define TMCSR7_MOD0 tmcsr7.bit._MOD0\r
+#define TMCSR7_OUTL tmcsr7.bit._OUTL\r
+#define TMCSR7_RELD tmcsr7.bit._RELD\r
+#define TMCSR7_INTE tmcsr7.bit._INTE\r
+#define TMCSR7_UF tmcsr7.bit._UF\r
+#define TMCSR7_CNTE tmcsr7.bit._CNTE\r
+#define TMCSR7_TRG tmcsr7.bit._TRG\r
+#define TMCSR7_CSL tmcsr7.bitc._CSL\r
+#define TMCSR7_MOD tmcsr7.bitc._MOD\r
+__IO_EXTERN TMCSRH7STR tmcsrh7;  \r
+#define TMCSRH7 tmcsrh7.byte\r
+#define TMCSRH7_CSL2 tmcsrh7.bit._CSL2\r
+#define TMCSRH7_CSL1 tmcsrh7.bit._CSL1\r
+#define TMCSRH7_CSL0 tmcsrh7.bit._CSL0\r
+#define TMCSRH7_MOD2 tmcsrh7.bit._MOD2\r
+#define TMCSRH7_MOD1 tmcsrh7.bit._MOD1\r
+#define TMCSRH7_CSL tmcsrh7.bitc._CSL\r
+__IO_EXTERN TMCSRL7STR tmcsrl7;  \r
+#define TMCSRL7 tmcsrl7.byte\r
+#define TMCSRL7_MOD0 tmcsrl7.bit._MOD0\r
+#define TMCSRL7_OUTL tmcsrl7.bit._OUTL\r
+#define TMCSRL7_RELD tmcsrl7.bit._RELD\r
+#define TMCSRL7_INTE tmcsrl7.bit._INTE\r
+#define TMCSRL7_UF tmcsrl7.bit._UF\r
+#define TMCSRL7_CNTE tmcsrl7.bit._CNTE\r
+#define TMCSRL7_TRG tmcsrl7.bit._TRG\r
+__IO_EXTERN TCDT0STR tcdt0;   /* Free Running Timer0 */\r
+#define TCDT0 tcdt0.word\r
+#define TCDT0_T15 tcdt0.bit._T15\r
+#define TCDT0_T14 tcdt0.bit._T14\r
+#define TCDT0_T13 tcdt0.bit._T13\r
+#define TCDT0_T12 tcdt0.bit._T12\r
+#define TCDT0_T11 tcdt0.bit._T11\r
+#define TCDT0_T10 tcdt0.bit._T10\r
+#define TCDT0_T9 tcdt0.bit._T9\r
+#define TCDT0_T8 tcdt0.bit._T8\r
+#define TCDT0_T7 tcdt0.bit._T7\r
+#define TCDT0_T6 tcdt0.bit._T6\r
+#define TCDT0_T5 tcdt0.bit._T5\r
+#define TCDT0_T4 tcdt0.bit._T4\r
+#define TCDT0_T3 tcdt0.bit._T3\r
+#define TCDT0_T2 tcdt0.bit._T2\r
+#define TCDT0_T1 tcdt0.bit._T1\r
+#define TCDT0_T0 tcdt0.bit._T0\r
+__IO_EXTERN TCCS0STR tccs0;  \r
+#define TCCS0 tccs0.byte\r
+#define TCCS0_ECLK tccs0.bit._ECLK\r
+#define TCCS0_IVF tccs0.bit._IVF\r
+#define TCCS0_IVFE tccs0.bit._IVFE\r
+#define TCCS0_STOP tccs0.bit._STOP\r
+#define TCCS0_MODE tccs0.bit._MODE\r
+#define TCCS0_CLR tccs0.bit._CLR\r
+#define TCCS0_CLK1 tccs0.bit._CLK1\r
+#define TCCS0_CLK0 tccs0.bit._CLK0\r
+#define TCCS0_CLK tccs0.bitc._CLK\r
+__IO_EXTERN TCDT1STR tcdt1;   /* Free Running Timer1 */\r
+#define TCDT1 tcdt1.word\r
+#define TCDT1_T15 tcdt1.bit._T15\r
+#define TCDT1_T14 tcdt1.bit._T14\r
+#define TCDT1_T13 tcdt1.bit._T13\r
+#define TCDT1_T12 tcdt1.bit._T12\r
+#define TCDT1_T11 tcdt1.bit._T11\r
+#define TCDT1_T10 tcdt1.bit._T10\r
+#define TCDT1_T9 tcdt1.bit._T9\r
+#define TCDT1_T8 tcdt1.bit._T8\r
+#define TCDT1_T7 tcdt1.bit._T7\r
+#define TCDT1_T6 tcdt1.bit._T6\r
+#define TCDT1_T5 tcdt1.bit._T5\r
+#define TCDT1_T4 tcdt1.bit._T4\r
+#define TCDT1_T3 tcdt1.bit._T3\r
+#define TCDT1_T2 tcdt1.bit._T2\r
+#define TCDT1_T1 tcdt1.bit._T1\r
+#define TCDT1_T0 tcdt1.bit._T0\r
+__IO_EXTERN TCCS1STR tccs1;  \r
+#define TCCS1 tccs1.byte\r
+#define TCCS1_ECLK tccs1.bit._ECLK\r
+#define TCCS1_IVF tccs1.bit._IVF\r
+#define TCCS1_IVFE tccs1.bit._IVFE\r
+#define TCCS1_STOP tccs1.bit._STOP\r
+#define TCCS1_MODE tccs1.bit._MODE\r
+#define TCCS1_CLR tccs1.bit._CLR\r
+#define TCCS1_CLK1 tccs1.bit._CLK1\r
+#define TCCS1_CLK0 tccs1.bit._CLK0\r
+#define TCCS1_CLK tccs1.bitc._CLK\r
+__IO_EXTERN TCDT2STR tcdt2;   /* Free Running Timer2 */\r
+#define TCDT2 tcdt2.word\r
+#define TCDT2_T15 tcdt2.bit._T15\r
+#define TCDT2_T14 tcdt2.bit._T14\r
+#define TCDT2_T13 tcdt2.bit._T13\r
+#define TCDT2_T12 tcdt2.bit._T12\r
+#define TCDT2_T11 tcdt2.bit._T11\r
+#define TCDT2_T10 tcdt2.bit._T10\r
+#define TCDT2_T9 tcdt2.bit._T9\r
+#define TCDT2_T8 tcdt2.bit._T8\r
+#define TCDT2_T7 tcdt2.bit._T7\r
+#define TCDT2_T6 tcdt2.bit._T6\r
+#define TCDT2_T5 tcdt2.bit._T5\r
+#define TCDT2_T4 tcdt2.bit._T4\r
+#define TCDT2_T3 tcdt2.bit._T3\r
+#define TCDT2_T2 tcdt2.bit._T2\r
+#define TCDT2_T1 tcdt2.bit._T1\r
+#define TCDT2_T0 tcdt2.bit._T0\r
+__IO_EXTERN TCCS2STR tccs2;  \r
+#define TCCS2 tccs2.byte\r
+#define TCCS2_ECLK tccs2.bit._ECLK\r
+#define TCCS2_IVF tccs2.bit._IVF\r
+#define TCCS2_IVFE tccs2.bit._IVFE\r
+#define TCCS2_STOP tccs2.bit._STOP\r
+#define TCCS2_MODE tccs2.bit._MODE\r
+#define TCCS2_CLR tccs2.bit._CLR\r
+#define TCCS2_CLK1 tccs2.bit._CLK1\r
+#define TCCS2_CLK0 tccs2.bit._CLK0\r
+#define TCCS2_CLK tccs2.bitc._CLK\r
+__IO_EXTERN TCDT3STR tcdt3;   /* Free Running Timer3 */\r
+#define TCDT3 tcdt3.word\r
+#define TCDT3_T15 tcdt3.bit._T15\r
+#define TCDT3_T14 tcdt3.bit._T14\r
+#define TCDT3_T13 tcdt3.bit._T13\r
+#define TCDT3_T12 tcdt3.bit._T12\r
+#define TCDT3_T11 tcdt3.bit._T11\r
+#define TCDT3_T10 tcdt3.bit._T10\r
+#define TCDT3_T9 tcdt3.bit._T9\r
+#define TCDT3_T8 tcdt3.bit._T8\r
+#define TCDT3_T7 tcdt3.bit._T7\r
+#define TCDT3_T6 tcdt3.bit._T6\r
+#define TCDT3_T5 tcdt3.bit._T5\r
+#define TCDT3_T4 tcdt3.bit._T4\r
+#define TCDT3_T3 tcdt3.bit._T3\r
+#define TCDT3_T2 tcdt3.bit._T2\r
+#define TCDT3_T1 tcdt3.bit._T1\r
+#define TCDT3_T0 tcdt3.bit._T0\r
+__IO_EXTERN TCCS3STR tccs3;  \r
+#define TCCS3 tccs3.byte\r
+#define TCCS3_ECLK tccs3.bit._ECLK\r
+#define TCCS3_IVF tccs3.bit._IVF\r
+#define TCCS3_IVFE tccs3.bit._IVFE\r
+#define TCCS3_STOP tccs3.bit._STOP\r
+#define TCCS3_MODE tccs3.bit._MODE\r
+#define TCCS3_CLR tccs3.bit._CLR\r
+#define TCCS3_CLK1 tccs3.bit._CLK1\r
+#define TCCS3_CLK0 tccs3.bit._CLK0\r
+#define TCCS3_CLK tccs3.bitc._CLK\r
+__IO_EXTERN DMACA0STR dmaca0;   /* DMAC */\r
+#define DMACA0 dmaca0.lword\r
+#define DMACA0_DENB dmaca0.bit._DENB\r
+#define DMACA0_PAUS dmaca0.bit._PAUS\r
+#define DMACA0_STRG dmaca0.bit._STRG\r
+#define DMACA0_IS4 dmaca0.bit._IS4\r
+#define DMACA0_IS3 dmaca0.bit._IS3\r
+#define DMACA0_IS2 dmaca0.bit._IS2\r
+#define DMACA0_IS1 dmaca0.bit._IS1\r
+#define DMACA0_IS0 dmaca0.bit._IS0\r
+#define DMACA0_EIS3 dmaca0.bit._EIS3\r
+#define DMACA0_EIS2 dmaca0.bit._EIS2\r
+#define DMACA0_EIS1 dmaca0.bit._EIS1\r
+#define DMACA0_EIS0 dmaca0.bit._EIS0\r
+#define DMACA0_BLK3 dmaca0.bit._BLK3\r
+#define DMACA0_BLK2 dmaca0.bit._BLK2\r
+#define DMACA0_BLK1 dmaca0.bit._BLK1\r
+#define DMACA0_BLK0 dmaca0.bit._BLK0\r
+#define DMACA0_DTCF dmaca0.bit._DTCF\r
+#define DMACA0_DTCE dmaca0.bit._DTCE\r
+#define DMACA0_DTCD dmaca0.bit._DTCD\r
+#define DMACA0_DTCC dmaca0.bit._DTCC\r
+#define DMACA0_DTCB dmaca0.bit._DTCB\r
+#define DMACA0_DTCA dmaca0.bit._DTCA\r
+#define DMACA0_DTC9 dmaca0.bit._DTC9\r
+#define DMACA0_DTC8 dmaca0.bit._DTC8\r
+#define DMACA0_DTC7 dmaca0.bit._DTC7\r
+#define DMACA0_DTC6 dmaca0.bit._DTC6\r
+#define DMACA0_DTC5 dmaca0.bit._DTC5\r
+#define DMACA0_DTC4 dmaca0.bit._DTC4\r
+#define DMACA0_DTC3 dmaca0.bit._DTC3\r
+#define DMACA0_DTC2 dmaca0.bit._DTC2\r
+#define DMACA0_DTC1 dmaca0.bit._DTC1\r
+#define DMACA0_DTC0 dmaca0.bit._DTC0\r
+#define DMACA0_IS dmaca0.bitc._IS\r
+#define DMACA0_EIS dmaca0.bitc._EIS\r
+#define DMACA0_BLK dmaca0.bitc._BLK\r
+#define DMACA0_DTC dmaca0.bitc._DTC\r
+__IO_EXTERN DMACB0STR dmacb0;  \r
+#define DMACB0 dmacb0.lword\r
+#define DMACB0_TYPE1 dmacb0.bit._TYPE1\r
+#define DMACB0_TYPE0 dmacb0.bit._TYPE0\r
+#define DMACB0_MOD1 dmacb0.bit._MOD1\r
+#define DMACB0_MOD0 dmacb0.bit._MOD0\r
+#define DMACB0_WS1 dmacb0.bit._WS1\r
+#define DMACB0_WS0 dmacb0.bit._WS0\r
+#define DMACB0_SADM dmacb0.bit._SADM\r
+#define DMACB0_DADM dmacb0.bit._DADM\r
+#define DMACB0_DTCR dmacb0.bit._DTCR\r
+#define DMACB0_SADR dmacb0.bit._SADR\r
+#define DMACB0_DADR dmacb0.bit._DADR\r
+#define DMACB0_ERIE dmacb0.bit._ERIE\r
+#define DMACB0_EDIE dmacb0.bit._EDIE\r
+#define DMACB0_DSS2 dmacb0.bit._DSS2\r
+#define DMACB0_DSS1 dmacb0.bit._DSS1\r
+#define DMACB0_DSS0 dmacb0.bit._DSS0\r
+#define DMACB0_SASZ7 dmacb0.bit._SASZ7\r
+#define DMACB0_SASZ6 dmacb0.bit._SASZ6\r
+#define DMACB0_SASZ5 dmacb0.bit._SASZ5\r
+#define DMACB0_SASZ4 dmacb0.bit._SASZ4\r
+#define DMACB0_SASZ3 dmacb0.bit._SASZ3\r
+#define DMACB0_SASZ2 dmacb0.bit._SASZ2\r
+#define DMACB0_SASZ1 dmacb0.bit._SASZ1\r
+#define DMACB0_SASZ0 dmacb0.bit._SASZ0\r
+#define DMACB0_DASZ7 dmacb0.bit._DASZ7\r
+#define DMACB0_DASZ6 dmacb0.bit._DASZ6\r
+#define DMACB0_DASZ5 dmacb0.bit._DASZ5\r
+#define DMACB0_DASZ4 dmacb0.bit._DASZ4\r
+#define DMACB0_DASZ3 dmacb0.bit._DASZ3\r
+#define DMACB0_DASZ2 dmacb0.bit._DASZ2\r
+#define DMACB0_DASZ1 dmacb0.bit._DASZ1\r
+#define DMACB0_DASZ0 dmacb0.bit._DASZ0\r
+#define DMACB0_TYPE dmacb0.bitc._TYPE\r
+#define DMACB0_MOD dmacb0.bitc._MOD\r
+#define DMACB0_WS dmacb0.bitc._WS\r
+#define DMACB0_DSS dmacb0.bitc._DSS\r
+#define DMACB0_SASZ dmacb0.bitc._SASZ\r
+#define DMACB0_DASZ dmacb0.bitc._DASZ\r
+__IO_EXTERN DMACA1STR dmaca1;  \r
+#define DMACA1 dmaca1.lword\r
+#define DMACA1_DENB dmaca1.bit._DENB\r
+#define DMACA1_PAUS dmaca1.bit._PAUS\r
+#define DMACA1_STRG dmaca1.bit._STRG\r
+#define DMACA1_IS4 dmaca1.bit._IS4\r
+#define DMACA1_IS3 dmaca1.bit._IS3\r
+#define DMACA1_IS2 dmaca1.bit._IS2\r
+#define DMACA1_IS1 dmaca1.bit._IS1\r
+#define DMACA1_IS0 dmaca1.bit._IS0\r
+#define DMACA1_EIS3 dmaca1.bit._EIS3\r
+#define DMACA1_EIS2 dmaca1.bit._EIS2\r
+#define DMACA1_EIS1 dmaca1.bit._EIS1\r
+#define DMACA1_EIS0 dmaca1.bit._EIS0\r
+#define DMACA1_BLK3 dmaca1.bit._BLK3\r
+#define DMACA1_BLK2 dmaca1.bit._BLK2\r
+#define DMACA1_BLK1 dmaca1.bit._BLK1\r
+#define DMACA1_BLK0 dmaca1.bit._BLK0\r
+#define DMACA1_DTCF dmaca1.bit._DTCF\r
+#define DMACA1_DTCE dmaca1.bit._DTCE\r
+#define DMACA1_DTCD dmaca1.bit._DTCD\r
+#define DMACA1_DTCC dmaca1.bit._DTCC\r
+#define DMACA1_DTCB dmaca1.bit._DTCB\r
+#define DMACA1_DTCA dmaca1.bit._DTCA\r
+#define DMACA1_DTC9 dmaca1.bit._DTC9\r
+#define DMACA1_DTC8 dmaca1.bit._DTC8\r
+#define DMACA1_DTC7 dmaca1.bit._DTC7\r
+#define DMACA1_DTC6 dmaca1.bit._DTC6\r
+#define DMACA1_DTC5 dmaca1.bit._DTC5\r
+#define DMACA1_DTC4 dmaca1.bit._DTC4\r
+#define DMACA1_DTC3 dmaca1.bit._DTC3\r
+#define DMACA1_DTC2 dmaca1.bit._DTC2\r
+#define DMACA1_DTC1 dmaca1.bit._DTC1\r
+#define DMACA1_DTC0 dmaca1.bit._DTC0\r
+#define DMACA1_IS dmaca1.bitc._IS\r
+#define DMACA1_EIS dmaca1.bitc._EIS\r
+#define DMACA1_BLK dmaca1.bitc._BLK\r
+#define DMACA1_DTC dmaca1.bitc._DTC\r
+__IO_EXTERN DMACB1STR dmacb1;  \r
+#define DMACB1 dmacb1.lword\r
+#define DMACB1_TYPE1 dmacb1.bit._TYPE1\r
+#define DMACB1_TYPE0 dmacb1.bit._TYPE0\r
+#define DMACB1_MOD1 dmacb1.bit._MOD1\r
+#define DMACB1_MOD0 dmacb1.bit._MOD0\r
+#define DMACB1_WS1 dmacb1.bit._WS1\r
+#define DMACB1_WS0 dmacb1.bit._WS0\r
+#define DMACB1_SADM dmacb1.bit._SADM\r
+#define DMACB1_DADM dmacb1.bit._DADM\r
+#define DMACB1_DTCR dmacb1.bit._DTCR\r
+#define DMACB1_SADR dmacb1.bit._SADR\r
+#define DMACB1_DADR dmacb1.bit._DADR\r
+#define DMACB1_ERIE dmacb1.bit._ERIE\r
+#define DMACB1_EDIE dmacb1.bit._EDIE\r
+#define DMACB1_DSS2 dmacb1.bit._DSS2\r
+#define DMACB1_DSS1 dmacb1.bit._DSS1\r
+#define DMACB1_DSS0 dmacb1.bit._DSS0\r
+#define DMACB1_SASZ7 dmacb1.bit._SASZ7\r
+#define DMACB1_SASZ6 dmacb1.bit._SASZ6\r
+#define DMACB1_SASZ5 dmacb1.bit._SASZ5\r
+#define DMACB1_SASZ4 dmacb1.bit._SASZ4\r
+#define DMACB1_SASZ3 dmacb1.bit._SASZ3\r
+#define DMACB1_SASZ2 dmacb1.bit._SASZ2\r
+#define DMACB1_SASZ1 dmacb1.bit._SASZ1\r
+#define DMACB1_SASZ0 dmacb1.bit._SASZ0\r
+#define DMACB1_DASZ7 dmacb1.bit._DASZ7\r
+#define DMACB1_DASZ6 dmacb1.bit._DASZ6\r
+#define DMACB1_DASZ5 dmacb1.bit._DASZ5\r
+#define DMACB1_DASZ4 dmacb1.bit._DASZ4\r
+#define DMACB1_DASZ3 dmacb1.bit._DASZ3\r
+#define DMACB1_DASZ2 dmacb1.bit._DASZ2\r
+#define DMACB1_DASZ1 dmacb1.bit._DASZ1\r
+#define DMACB1_DASZ0 dmacb1.bit._DASZ0\r
+#define DMACB1_TYPE dmacb1.bitc._TYPE\r
+#define DMACB1_MOD dmacb1.bitc._MOD\r
+#define DMACB1_WS dmacb1.bitc._WS\r
+#define DMACB1_DSS dmacb1.bitc._DSS\r
+#define DMACB1_SASZ dmacb1.bitc._SASZ\r
+#define DMACB1_DASZ dmacb1.bitc._DASZ\r
+__IO_EXTERN DMACA2STR dmaca2;  \r
+#define DMACA2 dmaca2.lword\r
+#define DMACA2_DENB dmaca2.bit._DENB\r
+#define DMACA2_PAUS dmaca2.bit._PAUS\r
+#define DMACA2_STRG dmaca2.bit._STRG\r
+#define DMACA2_IS4 dmaca2.bit._IS4\r
+#define DMACA2_IS3 dmaca2.bit._IS3\r
+#define DMACA2_IS2 dmaca2.bit._IS2\r
+#define DMACA2_IS1 dmaca2.bit._IS1\r
+#define DMACA2_IS0 dmaca2.bit._IS0\r
+#define DMACA2_EIS3 dmaca2.bit._EIS3\r
+#define DMACA2_EIS2 dmaca2.bit._EIS2\r
+#define DMACA2_EIS1 dmaca2.bit._EIS1\r
+#define DMACA2_EIS0 dmaca2.bit._EIS0\r
+#define DMACA2_BLK3 dmaca2.bit._BLK3\r
+#define DMACA2_BLK2 dmaca2.bit._BLK2\r
+#define DMACA2_BLK1 dmaca2.bit._BLK1\r
+#define DMACA2_BLK0 dmaca2.bit._BLK0\r
+#define DMACA2_DTCF dmaca2.bit._DTCF\r
+#define DMACA2_DTCE dmaca2.bit._DTCE\r
+#define DMACA2_DTCD dmaca2.bit._DTCD\r
+#define DMACA2_DTCC dmaca2.bit._DTCC\r
+#define DMACA2_DTCB dmaca2.bit._DTCB\r
+#define DMACA2_DTCA dmaca2.bit._DTCA\r
+#define DMACA2_DTC9 dmaca2.bit._DTC9\r
+#define DMACA2_DTC8 dmaca2.bit._DTC8\r
+#define DMACA2_DTC7 dmaca2.bit._DTC7\r
+#define DMACA2_DTC6 dmaca2.bit._DTC6\r
+#define DMACA2_DTC5 dmaca2.bit._DTC5\r
+#define DMACA2_DTC4 dmaca2.bit._DTC4\r
+#define DMACA2_DTC3 dmaca2.bit._DTC3\r
+#define DMACA2_DTC2 dmaca2.bit._DTC2\r
+#define DMACA2_DTC1 dmaca2.bit._DTC1\r
+#define DMACA2_DTC0 dmaca2.bit._DTC0\r
+#define DMACA2_IS dmaca2.bitc._IS\r
+#define DMACA2_EIS dmaca2.bitc._EIS\r
+#define DMACA2_BLK dmaca2.bitc._BLK\r
+#define DMACA2_DTC dmaca2.bitc._DTC\r
+__IO_EXTERN DMACB2STR dmacb2;  \r
+#define DMACB2 dmacb2.lword\r
+#define DMACB2_TYPE1 dmacb2.bit._TYPE1\r
+#define DMACB2_TYPE0 dmacb2.bit._TYPE0\r
+#define DMACB2_MOD1 dmacb2.bit._MOD1\r
+#define DMACB2_MOD0 dmacb2.bit._MOD0\r
+#define DMACB2_WS1 dmacb2.bit._WS1\r
+#define DMACB2_WS0 dmacb2.bit._WS0\r
+#define DMACB2_SADM dmacb2.bit._SADM\r
+#define DMACB2_DADM dmacb2.bit._DADM\r
+#define DMACB2_DTCR dmacb2.bit._DTCR\r
+#define DMACB2_SADR dmacb2.bit._SADR\r
+#define DMACB2_DADR dmacb2.bit._DADR\r
+#define DMACB2_ERIE dmacb2.bit._ERIE\r
+#define DMACB2_EDIE dmacb2.bit._EDIE\r
+#define DMACB2_DSS2 dmacb2.bit._DSS2\r
+#define DMACB2_DSS1 dmacb2.bit._DSS1\r
+#define DMACB2_DSS0 dmacb2.bit._DSS0\r
+#define DMACB2_SASZ7 dmacb2.bit._SASZ7\r
+#define DMACB2_SASZ6 dmacb2.bit._SASZ6\r
+#define DMACB2_SASZ5 dmacb2.bit._SASZ5\r
+#define DMACB2_SASZ4 dmacb2.bit._SASZ4\r
+#define DMACB2_SASZ3 dmacb2.bit._SASZ3\r
+#define DMACB2_SASZ2 dmacb2.bit._SASZ2\r
+#define DMACB2_SASZ1 dmacb2.bit._SASZ1\r
+#define DMACB2_SASZ0 dmacb2.bit._SASZ0\r
+#define DMACB2_DASZ7 dmacb2.bit._DASZ7\r
+#define DMACB2_DASZ6 dmacb2.bit._DASZ6\r
+#define DMACB2_DASZ5 dmacb2.bit._DASZ5\r
+#define DMACB2_DASZ4 dmacb2.bit._DASZ4\r
+#define DMACB2_DASZ3 dmacb2.bit._DASZ3\r
+#define DMACB2_DASZ2 dmacb2.bit._DASZ2\r
+#define DMACB2_DASZ1 dmacb2.bit._DASZ1\r
+#define DMACB2_DASZ0 dmacb2.bit._DASZ0\r
+#define DMACB2_TYPE dmacb2.bitc._TYPE\r
+#define DMACB2_MOD dmacb2.bitc._MOD\r
+#define DMACB2_WS dmacb2.bitc._WS\r
+#define DMACB2_DSS dmacb2.bitc._DSS\r
+#define DMACB2_SASZ dmacb2.bitc._SASZ\r
+#define DMACB2_DASZ dmacb2.bitc._DASZ\r
+__IO_EXTERN DMACA3STR dmaca3;  \r
+#define DMACA3 dmaca3.lword\r
+#define DMACA3_DENB dmaca3.bit._DENB\r
+#define DMACA3_PAUS dmaca3.bit._PAUS\r
+#define DMACA3_STRG dmaca3.bit._STRG\r
+#define DMACA3_IS4 dmaca3.bit._IS4\r
+#define DMACA3_IS3 dmaca3.bit._IS3\r
+#define DMACA3_IS2 dmaca3.bit._IS2\r
+#define DMACA3_IS1 dmaca3.bit._IS1\r
+#define DMACA3_IS0 dmaca3.bit._IS0\r
+#define DMACA3_EIS3 dmaca3.bit._EIS3\r
+#define DMACA3_EIS2 dmaca3.bit._EIS2\r
+#define DMACA3_EIS1 dmaca3.bit._EIS1\r
+#define DMACA3_EIS0 dmaca3.bit._EIS0\r
+#define DMACA3_BLK3 dmaca3.bit._BLK3\r
+#define DMACA3_BLK2 dmaca3.bit._BLK2\r
+#define DMACA3_BLK1 dmaca3.bit._BLK1\r
+#define DMACA3_BLK0 dmaca3.bit._BLK0\r
+#define DMACA3_DTCF dmaca3.bit._DTCF\r
+#define DMACA3_DTCE dmaca3.bit._DTCE\r
+#define DMACA3_DTCD dmaca3.bit._DTCD\r
+#define DMACA3_DTCC dmaca3.bit._DTCC\r
+#define DMACA3_DTCB dmaca3.bit._DTCB\r
+#define DMACA3_DTCA dmaca3.bit._DTCA\r
+#define DMACA3_DTC9 dmaca3.bit._DTC9\r
+#define DMACA3_DTC8 dmaca3.bit._DTC8\r
+#define DMACA3_DTC7 dmaca3.bit._DTC7\r
+#define DMACA3_DTC6 dmaca3.bit._DTC6\r
+#define DMACA3_DTC5 dmaca3.bit._DTC5\r
+#define DMACA3_DTC4 dmaca3.bit._DTC4\r
+#define DMACA3_DTC3 dmaca3.bit._DTC3\r
+#define DMACA3_DTC2 dmaca3.bit._DTC2\r
+#define DMACA3_DTC1 dmaca3.bit._DTC1\r
+#define DMACA3_DTC0 dmaca3.bit._DTC0\r
+#define DMACA3_IS dmaca3.bitc._IS\r
+#define DMACA3_EIS dmaca3.bitc._EIS\r
+#define DMACA3_BLK dmaca3.bitc._BLK\r
+#define DMACA3_DTC dmaca3.bitc._DTC\r
+__IO_EXTERN DMACB3STR dmacb3;  \r
+#define DMACB3 dmacb3.lword\r
+#define DMACB3_TYPE1 dmacb3.bit._TYPE1\r
+#define DMACB3_TYPE0 dmacb3.bit._TYPE0\r
+#define DMACB3_MOD1 dmacb3.bit._MOD1\r
+#define DMACB3_MOD0 dmacb3.bit._MOD0\r
+#define DMACB3_WS1 dmacb3.bit._WS1\r
+#define DMACB3_WS0 dmacb3.bit._WS0\r
+#define DMACB3_SADM dmacb3.bit._SADM\r
+#define DMACB3_DADM dmacb3.bit._DADM\r
+#define DMACB3_DTCR dmacb3.bit._DTCR\r
+#define DMACB3_SADR dmacb3.bit._SADR\r
+#define DMACB3_DADR dmacb3.bit._DADR\r
+#define DMACB3_ERIE dmacb3.bit._ERIE\r
+#define DMACB3_EDIE dmacb3.bit._EDIE\r
+#define DMACB3_DSS2 dmacb3.bit._DSS2\r
+#define DMACB3_DSS1 dmacb3.bit._DSS1\r
+#define DMACB3_DSS0 dmacb3.bit._DSS0\r
+#define DMACB3_SASZ7 dmacb3.bit._SASZ7\r
+#define DMACB3_SASZ6 dmacb3.bit._SASZ6\r
+#define DMACB3_SASZ5 dmacb3.bit._SASZ5\r
+#define DMACB3_SASZ4 dmacb3.bit._SASZ4\r
+#define DMACB3_SASZ3 dmacb3.bit._SASZ3\r
+#define DMACB3_SASZ2 dmacb3.bit._SASZ2\r
+#define DMACB3_SASZ1 dmacb3.bit._SASZ1\r
+#define DMACB3_SASZ0 dmacb3.bit._SASZ0\r
+#define DMACB3_DASZ7 dmacb3.bit._DASZ7\r
+#define DMACB3_DASZ6 dmacb3.bit._DASZ6\r
+#define DMACB3_DASZ5 dmacb3.bit._DASZ5\r
+#define DMACB3_DASZ4 dmacb3.bit._DASZ4\r
+#define DMACB3_DASZ3 dmacb3.bit._DASZ3\r
+#define DMACB3_DASZ2 dmacb3.bit._DASZ2\r
+#define DMACB3_DASZ1 dmacb3.bit._DASZ1\r
+#define DMACB3_DASZ0 dmacb3.bit._DASZ0\r
+#define DMACB3_TYPE dmacb3.bitc._TYPE\r
+#define DMACB3_MOD dmacb3.bitc._MOD\r
+#define DMACB3_WS dmacb3.bitc._WS\r
+#define DMACB3_DSS dmacb3.bitc._DSS\r
+#define DMACB3_SASZ dmacb3.bitc._SASZ\r
+#define DMACB3_DASZ dmacb3.bitc._DASZ\r
+__IO_EXTERN DMACA4STR dmaca4;  \r
+#define DMACA4 dmaca4.lword\r
+#define DMACA4_DENB dmaca4.bit._DENB\r
+#define DMACA4_PAUS dmaca4.bit._PAUS\r
+#define DMACA4_STRG dmaca4.bit._STRG\r
+#define DMACA4_IS4 dmaca4.bit._IS4\r
+#define DMACA4_IS3 dmaca4.bit._IS3\r
+#define DMACA4_IS2 dmaca4.bit._IS2\r
+#define DMACA4_IS1 dmaca4.bit._IS1\r
+#define DMACA4_IS0 dmaca4.bit._IS0\r
+#define DMACA4_EIS3 dmaca4.bit._EIS3\r
+#define DMACA4_EIS2 dmaca4.bit._EIS2\r
+#define DMACA4_EIS1 dmaca4.bit._EIS1\r
+#define DMACA4_EIS0 dmaca4.bit._EIS0\r
+#define DMACA4_BLK3 dmaca4.bit._BLK3\r
+#define DMACA4_BLK2 dmaca4.bit._BLK2\r
+#define DMACA4_BLK1 dmaca4.bit._BLK1\r
+#define DMACA4_BLK0 dmaca4.bit._BLK0\r
+#define DMACA4_DTCF dmaca4.bit._DTCF\r
+#define DMACA4_DTCE dmaca4.bit._DTCE\r
+#define DMACA4_DTCD dmaca4.bit._DTCD\r
+#define DMACA4_DTCC dmaca4.bit._DTCC\r
+#define DMACA4_DTCB dmaca4.bit._DTCB\r
+#define DMACA4_DTCA dmaca4.bit._DTCA\r
+#define DMACA4_DTC9 dmaca4.bit._DTC9\r
+#define DMACA4_DTC8 dmaca4.bit._DTC8\r
+#define DMACA4_DTC7 dmaca4.bit._DTC7\r
+#define DMACA4_DTC6 dmaca4.bit._DTC6\r
+#define DMACA4_DTC5 dmaca4.bit._DTC5\r
+#define DMACA4_DTC4 dmaca4.bit._DTC4\r
+#define DMACA4_DTC3 dmaca4.bit._DTC3\r
+#define DMACA4_DTC2 dmaca4.bit._DTC2\r
+#define DMACA4_DTC1 dmaca4.bit._DTC1\r
+#define DMACA4_DTC0 dmaca4.bit._DTC0\r
+#define DMACA4_IS dmaca4.bitc._IS\r
+#define DMACA4_EIS dmaca4.bitc._EIS\r
+#define DMACA4_BLK dmaca4.bitc._BLK\r
+#define DMACA4_DTC dmaca4.bitc._DTC\r
+__IO_EXTERN DMACB4STR dmacb4;  \r
+#define DMACB4 dmacb4.lword\r
+#define DMACB4_TYPE1 dmacb4.bit._TYPE1\r
+#define DMACB4_TYPE0 dmacb4.bit._TYPE0\r
+#define DMACB4_MOD1 dmacb4.bit._MOD1\r
+#define DMACB4_MOD0 dmacb4.bit._MOD0\r
+#define DMACB4_WS1 dmacb4.bit._WS1\r
+#define DMACB4_WS0 dmacb4.bit._WS0\r
+#define DMACB4_SADM dmacb4.bit._SADM\r
+#define DMACB4_DADM dmacb4.bit._DADM\r
+#define DMACB4_DTCR dmacb4.bit._DTCR\r
+#define DMACB4_SADR dmacb4.bit._SADR\r
+#define DMACB4_DADR dmacb4.bit._DADR\r
+#define DMACB4_ERIE dmacb4.bit._ERIE\r
+#define DMACB4_EDIE dmacb4.bit._EDIE\r
+#define DMACB4_DSS2 dmacb4.bit._DSS2\r
+#define DMACB4_DSS1 dmacb4.bit._DSS1\r
+#define DMACB4_DSS0 dmacb4.bit._DSS0\r
+#define DMACB4_SASZ7 dmacb4.bit._SASZ7\r
+#define DMACB4_SASZ6 dmacb4.bit._SASZ6\r
+#define DMACB4_SASZ5 dmacb4.bit._SASZ5\r
+#define DMACB4_SASZ4 dmacb4.bit._SASZ4\r
+#define DMACB4_SASZ3 dmacb4.bit._SASZ3\r
+#define DMACB4_SASZ2 dmacb4.bit._SASZ2\r
+#define DMACB4_SASZ1 dmacb4.bit._SASZ1\r
+#define DMACB4_SASZ0 dmacb4.bit._SASZ0\r
+#define DMACB4_DASZ7 dmacb4.bit._DASZ7\r
+#define DMACB4_DASZ6 dmacb4.bit._DASZ6\r
+#define DMACB4_DASZ5 dmacb4.bit._DASZ5\r
+#define DMACB4_DASZ4 dmacb4.bit._DASZ4\r
+#define DMACB4_DASZ3 dmacb4.bit._DASZ3\r
+#define DMACB4_DASZ2 dmacb4.bit._DASZ2\r
+#define DMACB4_DASZ1 dmacb4.bit._DASZ1\r
+#define DMACB4_DASZ0 dmacb4.bit._DASZ0\r
+#define DMACB4_TYPE dmacb4.bitc._TYPE\r
+#define DMACB4_MOD dmacb4.bitc._MOD\r
+#define DMACB4_WS dmacb4.bitc._WS\r
+#define DMACB4_DSS dmacb4.bitc._DSS\r
+#define DMACB4_SASZ dmacb4.bitc._SASZ\r
+#define DMACB4_DASZ dmacb4.bitc._DASZ\r
+__IO_EXTERN DMACRSTR dmacr;  \r
+#define DMACR dmacr.byte\r
+#define DMACR_DMAE dmacr.bit._DMAE\r
+#define DMACR_PM01 dmacr.bit._PM01\r
+#define DMACR_DMAH3 dmacr.bit._DMAH3\r
+#define DMACR_DMAH2 dmacr.bit._DMAH2\r
+#define DMACR_DMAH1 dmacr.bit._DMAH1\r
+#define DMACR_DMAH0 dmacr.bit._DMAH0\r
+#define DMACR_DMAH dmacr.bitc._DMAH\r
+/* include : INC460_DMAC.INC */\r
+/*-------------------------------------------------------------------*/\r
+/* INC460.DMAC :  Old bit name of DMACx */\r
+\r
+/* alias macro definition for DMACx */\r
+#define DMACB0_MD dmacb0.bitc._MOD\r
+#define DMACB0_MD1 dmacb0.bit._MOD1\r
+#define DMACB0_MD0 dmacb0.bit._MOD0\r
+#define DMACB1_MD dmacb1.bitc._MOD\r
+#define DMACB1_MD1 dmacb1.bit._MOD1\r
+#define DMACB1_MD0 dmacb1.bit._MOD0\r
+#define DMACB2_MD dmacb2.bitc._MOD\r
+#define DMACB2_MD1 dmacb2.bit._MOD1\r
+#define DMACB2_MD0 dmacb2.bit._MOD0\r
+#define DMACB3_MD dmacb3.bitc._MOD\r
+#define DMACB3_MD1 dmacb3.bit._MOD1\r
+#define DMACB3_MD0 dmacb3.bit._MOD0\r
+#define DMACB4_MD dmacb4.bitc._MOD\r
+#define DMACB4_MD1 dmacb4.bit._MOD1\r
+#define DMACB4_MD0 dmacb4.bit._MOD0\r
+/*-------------------------------------------------------------------*/\r
+__IO_EXTERN ICS45STR ics45;   /* Input Capture 4-7 */\r
+#define ICS45 ics45.byte\r
+#define ICS45_ICP5 ics45.bit._ICP5\r
+#define ICS45_ICP4 ics45.bit._ICP4\r
+#define ICS45_ICE5 ics45.bit._ICE5\r
+#define ICS45_ICE4 ics45.bit._ICE4\r
+#define ICS45_EG51 ics45.bit._EG51\r
+#define ICS45_EG50 ics45.bit._EG50\r
+#define ICS45_EG41 ics45.bit._EG41\r
+#define ICS45_EG40 ics45.bit._EG40\r
+#define ICS45_EG5 ics45.bitc._EG5\r
+#define ICS45_EG4 ics45.bitc._EG4\r
+__IO_EXTERN ICS67STR ics67;  \r
+#define ICS67 ics67.byte\r
+#define ICS67_ICP7 ics67.bit._ICP7\r
+#define ICS67_ICP6 ics67.bit._ICP6\r
+#define ICS67_ICE7 ics67.bit._ICE7\r
+#define ICS67_ICE6 ics67.bit._ICE6\r
+#define ICS67_EG71 ics67.bit._EG71\r
+#define ICS67_EG70 ics67.bit._EG70\r
+#define ICS67_EG61 ics67.bit._EG61\r
+#define ICS67_EG60 ics67.bit._EG60\r
+#define ICS67_EG7 ics67.bitc._EG7\r
+#define ICS67_EG6 ics67.bitc._EG6\r
+__IO_EXTERN IPCP4STR ipcp4;  \r
+#define IPCP4 ipcp4.word\r
+#define IPCP4_CP15 ipcp4.bit._CP15\r
+#define IPCP4_CP14 ipcp4.bit._CP14\r
+#define IPCP4_CP13 ipcp4.bit._CP13\r
+#define IPCP4_CP12 ipcp4.bit._CP12\r
+#define IPCP4_CP11 ipcp4.bit._CP11\r
+#define IPCP4_CP10 ipcp4.bit._CP10\r
+#define IPCP4_CP9 ipcp4.bit._CP9\r
+#define IPCP4_CP8 ipcp4.bit._CP8\r
+#define IPCP4_CP7 ipcp4.bit._CP7\r
+#define IPCP4_CP6 ipcp4.bit._CP6\r
+#define IPCP4_CP5 ipcp4.bit._CP5\r
+#define IPCP4_CP4 ipcp4.bit._CP4\r
+#define IPCP4_CP3 ipcp4.bit._CP3\r
+#define IPCP4_CP2 ipcp4.bit._CP2\r
+#define IPCP4_CP1 ipcp4.bit._CP1\r
+#define IPCP4_CP0 ipcp4.bit._CP0\r
+__IO_EXTERN IPCP5STR ipcp5;  \r
+#define IPCP5 ipcp5.word\r
+#define IPCP5_CP15 ipcp5.bit._CP15\r
+#define IPCP5_CP14 ipcp5.bit._CP14\r
+#define IPCP5_CP13 ipcp5.bit._CP13\r
+#define IPCP5_CP12 ipcp5.bit._CP12\r
+#define IPCP5_CP11 ipcp5.bit._CP11\r
+#define IPCP5_CP10 ipcp5.bit._CP10\r
+#define IPCP5_CP9 ipcp5.bit._CP9\r
+#define IPCP5_CP8 ipcp5.bit._CP8\r
+#define IPCP5_CP7 ipcp5.bit._CP7\r
+#define IPCP5_CP6 ipcp5.bit._CP6\r
+#define IPCP5_CP5 ipcp5.bit._CP5\r
+#define IPCP5_CP4 ipcp5.bit._CP4\r
+#define IPCP5_CP3 ipcp5.bit._CP3\r
+#define IPCP5_CP2 ipcp5.bit._CP2\r
+#define IPCP5_CP1 ipcp5.bit._CP1\r
+#define IPCP5_CP0 ipcp5.bit._CP0\r
+__IO_EXTERN IPCP6STR ipcp6;  \r
+#define IPCP6 ipcp6.word\r
+#define IPCP6_CP15 ipcp6.bit._CP15\r
+#define IPCP6_CP14 ipcp6.bit._CP14\r
+#define IPCP6_CP13 ipcp6.bit._CP13\r
+#define IPCP6_CP12 ipcp6.bit._CP12\r
+#define IPCP6_CP11 ipcp6.bit._CP11\r
+#define IPCP6_CP10 ipcp6.bit._CP10\r
+#define IPCP6_CP9 ipcp6.bit._CP9\r
+#define IPCP6_CP8 ipcp6.bit._CP8\r
+#define IPCP6_CP7 ipcp6.bit._CP7\r
+#define IPCP6_CP6 ipcp6.bit._CP6\r
+#define IPCP6_CP5 ipcp6.bit._CP5\r
+#define IPCP6_CP4 ipcp6.bit._CP4\r
+#define IPCP6_CP3 ipcp6.bit._CP3\r
+#define IPCP6_CP2 ipcp6.bit._CP2\r
+#define IPCP6_CP1 ipcp6.bit._CP1\r
+#define IPCP6_CP0 ipcp6.bit._CP0\r
+__IO_EXTERN IPCP7STR ipcp7;  \r
+#define IPCP7 ipcp7.word\r
+#define IPCP7_CP15 ipcp7.bit._CP15\r
+#define IPCP7_CP14 ipcp7.bit._CP14\r
+#define IPCP7_CP13 ipcp7.bit._CP13\r
+#define IPCP7_CP12 ipcp7.bit._CP12\r
+#define IPCP7_CP11 ipcp7.bit._CP11\r
+#define IPCP7_CP10 ipcp7.bit._CP10\r
+#define IPCP7_CP9 ipcp7.bit._CP9\r
+#define IPCP7_CP8 ipcp7.bit._CP8\r
+#define IPCP7_CP7 ipcp7.bit._CP7\r
+#define IPCP7_CP6 ipcp7.bit._CP6\r
+#define IPCP7_CP5 ipcp7.bit._CP5\r
+#define IPCP7_CP4 ipcp7.bit._CP4\r
+#define IPCP7_CP3 ipcp7.bit._CP3\r
+#define IPCP7_CP2 ipcp7.bit._CP2\r
+#define IPCP7_CP1 ipcp7.bit._CP1\r
+#define IPCP7_CP0 ipcp7.bit._CP0\r
+__IO_EXTERN TCDT4STR tcdt4;   /* Free Running Timer4 */\r
+#define TCDT4 tcdt4.word\r
+#define TCDT4_T15 tcdt4.bit._T15\r
+#define TCDT4_T14 tcdt4.bit._T14\r
+#define TCDT4_T13 tcdt4.bit._T13\r
+#define TCDT4_T12 tcdt4.bit._T12\r
+#define TCDT4_T11 tcdt4.bit._T11\r
+#define TCDT4_T10 tcdt4.bit._T10\r
+#define TCDT4_T9 tcdt4.bit._T9\r
+#define TCDT4_T8 tcdt4.bit._T8\r
+#define TCDT4_T7 tcdt4.bit._T7\r
+#define TCDT4_T6 tcdt4.bit._T6\r
+#define TCDT4_T5 tcdt4.bit._T5\r
+#define TCDT4_T4 tcdt4.bit._T4\r
+#define TCDT4_T3 tcdt4.bit._T3\r
+#define TCDT4_T2 tcdt4.bit._T2\r
+#define TCDT4_T1 tcdt4.bit._T1\r
+#define TCDT4_T0 tcdt4.bit._T0\r
+__IO_EXTERN TCCS4STR tccs4;  \r
+#define TCCS4 tccs4.byte\r
+#define TCCS4_ECLK tccs4.bit._ECLK\r
+#define TCCS4_IVF tccs4.bit._IVF\r
+#define TCCS4_IVFE tccs4.bit._IVFE\r
+#define TCCS4_STOP tccs4.bit._STOP\r
+#define TCCS4_MODE tccs4.bit._MODE\r
+#define TCCS4_CLR tccs4.bit._CLR\r
+#define TCCS4_CLK1 tccs4.bit._CLK1\r
+#define TCCS4_CLK0 tccs4.bit._CLK0\r
+#define TCCS4_CLK tccs4.bitc._CLK\r
+__IO_EXTERN TCDT5STR tcdt5;   /* Free Running Timer5 */\r
+#define TCDT5 tcdt5.word\r
+#define TCDT5_T15 tcdt5.bit._T15\r
+#define TCDT5_T14 tcdt5.bit._T14\r
+#define TCDT5_T13 tcdt5.bit._T13\r
+#define TCDT5_T12 tcdt5.bit._T12\r
+#define TCDT5_T11 tcdt5.bit._T11\r
+#define TCDT5_T10 tcdt5.bit._T10\r
+#define TCDT5_T9 tcdt5.bit._T9\r
+#define TCDT5_T8 tcdt5.bit._T8\r
+#define TCDT5_T7 tcdt5.bit._T7\r
+#define TCDT5_T6 tcdt5.bit._T6\r
+#define TCDT5_T5 tcdt5.bit._T5\r
+#define TCDT5_T4 tcdt5.bit._T4\r
+#define TCDT5_T3 tcdt5.bit._T3\r
+#define TCDT5_T2 tcdt5.bit._T2\r
+#define TCDT5_T1 tcdt5.bit._T1\r
+#define TCDT5_T0 tcdt5.bit._T0\r
+__IO_EXTERN TCCS5STR tccs5;  \r
+#define TCCS5 tccs5.byte\r
+#define TCCS5_ECLK tccs5.bit._ECLK\r
+#define TCCS5_IVF tccs5.bit._IVF\r
+#define TCCS5_IVFE tccs5.bit._IVFE\r
+#define TCCS5_STOP tccs5.bit._STOP\r
+#define TCCS5_MODE tccs5.bit._MODE\r
+#define TCCS5_CLR tccs5.bit._CLR\r
+#define TCCS5_CLK1 tccs5.bit._CLK1\r
+#define TCCS5_CLK0 tccs5.bit._CLK0\r
+#define TCCS5_CLK tccs5.bitc._CLK\r
+__IO_EXTERN TCDT6STR tcdt6;   /* Free Running Timer6 */\r
+#define TCDT6 tcdt6.word\r
+#define TCDT6_T15 tcdt6.bit._T15\r
+#define TCDT6_T14 tcdt6.bit._T14\r
+#define TCDT6_T13 tcdt6.bit._T13\r
+#define TCDT6_T12 tcdt6.bit._T12\r
+#define TCDT6_T11 tcdt6.bit._T11\r
+#define TCDT6_T10 tcdt6.bit._T10\r
+#define TCDT6_T9 tcdt6.bit._T9\r
+#define TCDT6_T8 tcdt6.bit._T8\r
+#define TCDT6_T7 tcdt6.bit._T7\r
+#define TCDT6_T6 tcdt6.bit._T6\r
+#define TCDT6_T5 tcdt6.bit._T5\r
+#define TCDT6_T4 tcdt6.bit._T4\r
+#define TCDT6_T3 tcdt6.bit._T3\r
+#define TCDT6_T2 tcdt6.bit._T2\r
+#define TCDT6_T1 tcdt6.bit._T1\r
+#define TCDT6_T0 tcdt6.bit._T0\r
+__IO_EXTERN TCCS6STR tccs6;  \r
+#define TCCS6 tccs6.byte\r
+#define TCCS6_ECLK tccs6.bit._ECLK\r
+#define TCCS6_IVF tccs6.bit._IVF\r
+#define TCCS6_IVFE tccs6.bit._IVFE\r
+#define TCCS6_STOP tccs6.bit._STOP\r
+#define TCCS6_MODE tccs6.bit._MODE\r
+#define TCCS6_CLR tccs6.bit._CLR\r
+#define TCCS6_CLK1 tccs6.bit._CLK1\r
+#define TCCS6_CLK0 tccs6.bit._CLK0\r
+#define TCCS6_CLK tccs6.bitc._CLK\r
+__IO_EXTERN TCDT7STR tcdt7;   /* Free Running Timer7 */\r
+#define TCDT7 tcdt7.word\r
+#define TCDT7_T15 tcdt7.bit._T15\r
+#define TCDT7_T14 tcdt7.bit._T14\r
+#define TCDT7_T13 tcdt7.bit._T13\r
+#define TCDT7_T12 tcdt7.bit._T12\r
+#define TCDT7_T11 tcdt7.bit._T11\r
+#define TCDT7_T10 tcdt7.bit._T10\r
+#define TCDT7_T9 tcdt7.bit._T9\r
+#define TCDT7_T8 tcdt7.bit._T8\r
+#define TCDT7_T7 tcdt7.bit._T7\r
+#define TCDT7_T6 tcdt7.bit._T6\r
+#define TCDT7_T5 tcdt7.bit._T5\r
+#define TCDT7_T4 tcdt7.bit._T4\r
+#define TCDT7_T3 tcdt7.bit._T3\r
+#define TCDT7_T2 tcdt7.bit._T2\r
+#define TCDT7_T1 tcdt7.bit._T1\r
+#define TCDT7_T0 tcdt7.bit._T0\r
+__IO_EXTERN TCCS7STR tccs7;  \r
+#define TCCS7 tccs7.byte\r
+#define TCCS7_ECLK tccs7.bit._ECLK\r
+#define TCCS7_IVF tccs7.bit._IVF\r
+#define TCCS7_IVFE tccs7.bit._IVFE\r
+#define TCCS7_STOP tccs7.bit._STOP\r
+#define TCCS7_MODE tccs7.bit._MODE\r
+#define TCCS7_CLR tccs7.bit._CLR\r
+#define TCCS7_CLK1 tccs7.bit._CLK1\r
+#define TCCS7_CLK0 tccs7.bit._CLK0\r
+#define TCCS7_CLK tccs7.bitc._CLK\r
+__IO_EXTERN UDRC10STR udrc10;   /* Up/Down Counter 0-1 */\r
+#define UDRC10 udrc10.word\r
+#define UDRC10_D15 udrc10.bit._D15\r
+#define UDRC10_D14 udrc10.bit._D14\r
+#define UDRC10_D13 udrc10.bit._D13\r
+#define UDRC10_D12 udrc10.bit._D12\r
+#define UDRC10_D11 udrc10.bit._D11\r
+#define UDRC10_D10 udrc10.bit._D10\r
+#define UDRC10_D9 udrc10.bit._D9\r
+#define UDRC10_D8 udrc10.bit._D8\r
+#define UDRC10_D7 udrc10.bit._D7\r
+#define UDRC10_D6 udrc10.bit._D6\r
+#define UDRC10_D5 udrc10.bit._D5\r
+#define UDRC10_D4 udrc10.bit._D4\r
+#define UDRC10_D3 udrc10.bit._D3\r
+#define UDRC10_D2 udrc10.bit._D2\r
+#define UDRC10_D1 udrc10.bit._D1\r
+#define UDRC10_D0 udrc10.bit._D0\r
+__IO_EXTERN UDRC1STR udrc1;  \r
+#define UDRC1 udrc1.byte\r
+#define UDRC1_D7 udrc1.bit._D7\r
+#define UDRC1_D6 udrc1.bit._D6\r
+#define UDRC1_D5 udrc1.bit._D5\r
+#define UDRC1_D4 udrc1.bit._D4\r
+#define UDRC1_D3 udrc1.bit._D3\r
+#define UDRC1_D2 udrc1.bit._D2\r
+#define UDRC1_D1 udrc1.bit._D1\r
+#define UDRC1_D0 udrc1.bit._D0\r
+__IO_EXTERN UDRC0STR udrc0;  \r
+#define UDRC0 udrc0.byte\r
+#define UDRC0_D7 udrc0.bit._D7\r
+#define UDRC0_D6 udrc0.bit._D6\r
+#define UDRC0_D5 udrc0.bit._D5\r
+#define UDRC0_D4 udrc0.bit._D4\r
+#define UDRC0_D3 udrc0.bit._D3\r
+#define UDRC0_D2 udrc0.bit._D2\r
+#define UDRC0_D1 udrc0.bit._D1\r
+#define UDRC0_D0 udrc0.bit._D0\r
+__IO_EXTERN UDCR10STR udcr10;  \r
+#define UDCR10 udcr10.word\r
+#define UDCR10_D15 udcr10.bit._D15\r
+#define UDCR10_D14 udcr10.bit._D14\r
+#define UDCR10_D13 udcr10.bit._D13\r
+#define UDCR10_D12 udcr10.bit._D12\r
+#define UDCR10_D11 udcr10.bit._D11\r
+#define UDCR10_D10 udcr10.bit._D10\r
+#define UDCR10_D9 udcr10.bit._D9\r
+#define UDCR10_D8 udcr10.bit._D8\r
+#define UDCR10_D7 udcr10.bit._D7\r
+#define UDCR10_D6 udcr10.bit._D6\r
+#define UDCR10_D5 udcr10.bit._D5\r
+#define UDCR10_D4 udcr10.bit._D4\r
+#define UDCR10_D3 udcr10.bit._D3\r
+#define UDCR10_D2 udcr10.bit._D2\r
+#define UDCR10_D1 udcr10.bit._D1\r
+#define UDCR10_D0 udcr10.bit._D0\r
+__IO_EXTERN UDCR1STR udcr1;  \r
+#define UDCR1 udcr1.byte\r
+#define UDCR1_D7 udcr1.bit._D7\r
+#define UDCR1_D6 udcr1.bit._D6\r
+#define UDCR1_D5 udcr1.bit._D5\r
+#define UDCR1_D4 udcr1.bit._D4\r
+#define UDCR1_D3 udcr1.bit._D3\r
+#define UDCR1_D2 udcr1.bit._D2\r
+#define UDCR1_D1 udcr1.bit._D1\r
+#define UDCR1_D0 udcr1.bit._D0\r
+__IO_EXTERN UDCR0STR udcr0;  \r
+#define UDCR0 udcr0.byte\r
+#define UDCR0_D7 udcr0.bit._D7\r
+#define UDCR0_D6 udcr0.bit._D6\r
+#define UDCR0_D5 udcr0.bit._D5\r
+#define UDCR0_D4 udcr0.bit._D4\r
+#define UDCR0_D3 udcr0.bit._D3\r
+#define UDCR0_D2 udcr0.bit._D2\r
+#define UDCR0_D1 udcr0.bit._D1\r
+#define UDCR0_D0 udcr0.bit._D0\r
+__IO_EXTERN UDCC0STR udcc0;  \r
+#define UDCC0 udcc0.word\r
+#define UDCC0_M16E udcc0.bit._M16E\r
+#define UDCC0_CDCF udcc0.bit._CDCF\r
+#define UDCC0_CFIE udcc0.bit._CFIE\r
+#define UDCC0_CLKS udcc0.bit._CLKS\r
+#define UDCC0_CMS1 udcc0.bit._CMS1\r
+#define UDCC0_CMS0 udcc0.bit._CMS0\r
+#define UDCC0_CES1 udcc0.bit._CES1\r
+#define UDCC0_CES0 udcc0.bit._CES0\r
+#define UDCC0_CTUT udcc0.bit._CTUT\r
+#define UDCC0_UCRE udcc0.bit._UCRE\r
+#define UDCC0_RLDE udcc0.bit._RLDE\r
+#define UDCC0_UDCLR udcc0.bit._UDCLR\r
+#define UDCC0_CGSC udcc0.bit._CGSC\r
+#define UDCC0_CGE1 udcc0.bit._CGE1\r
+#define UDCC0_CGE0 udcc0.bit._CGE0\r
+#define UDCC0_CMS udcc0.bitc._CMS\r
+#define UDCC0_CES udcc0.bitc._CES\r
+#define UDCC0_CGE udcc0.bitc._CGE\r
+__IO_EXTERN UDCCH0STR udcch0;  \r
+#define UDCCH0 udcch0.byte\r
+#define UDCCH0_M16E udcch0.bit._M16E\r
+#define UDCCH0_CDCF udcch0.bit._CDCF\r
+#define UDCCH0_CFIE udcch0.bit._CFIE\r
+#define UDCCH0_CLKS udcch0.bit._CLKS\r
+#define UDCCH0_CMS1 udcch0.bit._CMS1\r
+#define UDCCH0_CMS0 udcch0.bit._CMS0\r
+#define UDCCH0_CES1 udcch0.bit._CES1\r
+#define UDCCH0_CES0 udcch0.bit._CES0\r
+#define UDCCH0_CMS udcch0.bitc._CMS\r
+#define UDCCH0_CES udcch0.bitc._CES\r
+__IO_EXTERN UDCCL0STR udccl0;  \r
+#define UDCCL0 udccl0.byte\r
+#define UDCCL0_CTUT udccl0.bit._CTUT\r
+#define UDCCL0_UCRE udccl0.bit._UCRE\r
+#define UDCCL0_RLDE udccl0.bit._RLDE\r
+#define UDCCL0_UDCLR udccl0.bit._UDCLR\r
+#define UDCCL0_CGSC udccl0.bit._CGSC\r
+#define UDCCL0_CGE1 udccl0.bit._CGE1\r
+#define UDCCL0_CGE0 udccl0.bit._CGE0\r
+#define UDCCL0_CGE udccl0.bitc._CGE\r
+__IO_EXTERN UDCS0STR udcs0;  \r
+#define UDCS0 udcs0.byte\r
+#define UDCS0_CSTR udcs0.bit._CSTR\r
+#define UDCS0_CITE udcs0.bit._CITE\r
+#define UDCS0_UDIE udcs0.bit._UDIE\r
+#define UDCS0_CMPF udcs0.bit._CMPF\r
+#define UDCS0_OVFF udcs0.bit._OVFF\r
+#define UDCS0_UDFF udcs0.bit._UDFF\r
+#define UDCS0_UDF1 udcs0.bit._UDF1\r
+#define UDCS0_UDF0 udcs0.bit._UDF0\r
+#define UDCS0_UDF udcs0.bitc._UDF\r
+__IO_EXTERN UDCC1STR udcc1;  \r
+#define UDCC1 udcc1.word\r
+#define UDCC1_RESV15 udcc1.bit._RESV15\r
+#define UDCC1_CDCF udcc1.bit._CDCF\r
+#define UDCC1_CFIE udcc1.bit._CFIE\r
+#define UDCC1_CLKS udcc1.bit._CLKS\r
+#define UDCC1_CMS1 udcc1.bit._CMS1\r
+#define UDCC1_CMS0 udcc1.bit._CMS0\r
+#define UDCC1_CES1 udcc1.bit._CES1\r
+#define UDCC1_CES0 udcc1.bit._CES0\r
+#define UDCC1_CTUT udcc1.bit._CTUT\r
+#define UDCC1_UCRE udcc1.bit._UCRE\r
+#define UDCC1_RLDE udcc1.bit._RLDE\r
+#define UDCC1_UDCLR udcc1.bit._UDCLR\r
+#define UDCC1_CGSC udcc1.bit._CGSC\r
+#define UDCC1_CGE1 udcc1.bit._CGE1\r
+#define UDCC1_CGE0 udcc1.bit._CGE0\r
+#define UDCC1_CMS udcc1.bitc._CMS\r
+#define UDCC1_CES udcc1.bitc._CES\r
+#define UDCC1_CGE udcc1.bitc._CGE\r
+__IO_EXTERN UDCCH1STR udcch1;  \r
+#define UDCCH1 udcch1.byte\r
+#define UDCCH1_RESV15 udcch1.bit._RESV15\r
+#define UDCCH1_CDCF udcch1.bit._CDCF\r
+#define UDCCH1_CFIE udcch1.bit._CFIE\r
+#define UDCCH1_CLKS udcch1.bit._CLKS\r
+#define UDCCH1_CMS1 udcch1.bit._CMS1\r
+#define UDCCH1_CMS0 udcch1.bit._CMS0\r
+#define UDCCH1_CES1 udcch1.bit._CES1\r
+#define UDCCH1_CES0 udcch1.bit._CES0\r
+#define UDCCH1_CMS udcch1.bitc._CMS\r
+#define UDCCH1_CES udcch1.bitc._CES\r
+__IO_EXTERN UDCCL1STR udccl1;  \r
+#define UDCCL1 udccl1.byte\r
+#define UDCCL1_CTUT udccl1.bit._CTUT\r
+#define UDCCL1_UCRE udccl1.bit._UCRE\r
+#define UDCCL1_RLDE udccl1.bit._RLDE\r
+#define UDCCL1_UDCLR udccl1.bit._UDCLR\r
+#define UDCCL1_CGSC udccl1.bit._CGSC\r
+#define UDCCL1_CGE1 udccl1.bit._CGE1\r
+#define UDCCL1_CGE0 udccl1.bit._CGE0\r
+#define UDCCL1_CGE udccl1.bitc._CGE\r
+__IO_EXTERN UDCS1STR udcs1;  \r
+#define UDCS1 udcs1.byte\r
+#define UDCS1_CSTR udcs1.bit._CSTR\r
+#define UDCS1_CITE udcs1.bit._CITE\r
+#define UDCS1_UDIE udcs1.bit._UDIE\r
+#define UDCS1_CMPF udcs1.bit._CMPF\r
+#define UDCS1_OVFF udcs1.bit._OVFF\r
+#define UDCS1_UDFF udcs1.bit._UDFF\r
+#define UDCS1_UDF1 udcs1.bit._UDF1\r
+#define UDCS1_UDF0 udcs1.bit._UDF0\r
+#define UDCS1_UDF udcs1.bitc._UDF\r
+__IO_EXTERN UDRC32STR udrc32;   /* Up/Down Counter 2-3 */\r
+#define UDRC32 udrc32.word\r
+#define UDRC32_D15 udrc32.bit._D15\r
+#define UDRC32_D14 udrc32.bit._D14\r
+#define UDRC32_D13 udrc32.bit._D13\r
+#define UDRC32_D12 udrc32.bit._D12\r
+#define UDRC32_D11 udrc32.bit._D11\r
+#define UDRC32_D10 udrc32.bit._D10\r
+#define UDRC32_D9 udrc32.bit._D9\r
+#define UDRC32_D8 udrc32.bit._D8\r
+#define UDRC32_D7 udrc32.bit._D7\r
+#define UDRC32_D6 udrc32.bit._D6\r
+#define UDRC32_D5 udrc32.bit._D5\r
+#define UDRC32_D4 udrc32.bit._D4\r
+#define UDRC32_D3 udrc32.bit._D3\r
+#define UDRC32_D2 udrc32.bit._D2\r
+#define UDRC32_D1 udrc32.bit._D1\r
+#define UDRC32_D0 udrc32.bit._D0\r
+__IO_EXTERN UDRC3STR udrc3;  \r
+#define UDRC3 udrc3.byte\r
+#define UDRC3_D7 udrc3.bit._D7\r
+#define UDRC3_D6 udrc3.bit._D6\r
+#define UDRC3_D5 udrc3.bit._D5\r
+#define UDRC3_D4 udrc3.bit._D4\r
+#define UDRC3_D3 udrc3.bit._D3\r
+#define UDRC3_D2 udrc3.bit._D2\r
+#define UDRC3_D1 udrc3.bit._D1\r
+#define UDRC3_D0 udrc3.bit._D0\r
+__IO_EXTERN UDRC2STR udrc2;  \r
+#define UDRC2 udrc2.byte\r
+#define UDRC2_D7 udrc2.bit._D7\r
+#define UDRC2_D6 udrc2.bit._D6\r
+#define UDRC2_D5 udrc2.bit._D5\r
+#define UDRC2_D4 udrc2.bit._D4\r
+#define UDRC2_D3 udrc2.bit._D3\r
+#define UDRC2_D2 udrc2.bit._D2\r
+#define UDRC2_D1 udrc2.bit._D1\r
+#define UDRC2_D0 udrc2.bit._D0\r
+__IO_EXTERN UDCR32STR udcr32;  \r
+#define UDCR32 udcr32.word\r
+#define UDCR32_D15 udcr32.bit._D15\r
+#define UDCR32_D14 udcr32.bit._D14\r
+#define UDCR32_D13 udcr32.bit._D13\r
+#define UDCR32_D12 udcr32.bit._D12\r
+#define UDCR32_D11 udcr32.bit._D11\r
+#define UDCR32_D10 udcr32.bit._D10\r
+#define UDCR32_D9 udcr32.bit._D9\r
+#define UDCR32_D8 udcr32.bit._D8\r
+#define UDCR32_D7 udcr32.bit._D7\r
+#define UDCR32_D6 udcr32.bit._D6\r
+#define UDCR32_D5 udcr32.bit._D5\r
+#define UDCR32_D4 udcr32.bit._D4\r
+#define UDCR32_D3 udcr32.bit._D3\r
+#define UDCR32_D2 udcr32.bit._D2\r
+#define UDCR32_D1 udcr32.bit._D1\r
+#define UDCR32_D0 udcr32.bit._D0\r
+__IO_EXTERN UDCR3STR udcr3;  \r
+#define UDCR3 udcr3.byte\r
+#define UDCR3_D7 udcr3.bit._D7\r
+#define UDCR3_D6 udcr3.bit._D6\r
+#define UDCR3_D5 udcr3.bit._D5\r
+#define UDCR3_D4 udcr3.bit._D4\r
+#define UDCR3_D3 udcr3.bit._D3\r
+#define UDCR3_D2 udcr3.bit._D2\r
+#define UDCR3_D1 udcr3.bit._D1\r
+#define UDCR3_D0 udcr3.bit._D0\r
+__IO_EXTERN UDCR2STR udcr2;  \r
+#define UDCR2 udcr2.byte\r
+#define UDCR2_D7 udcr2.bit._D7\r
+#define UDCR2_D6 udcr2.bit._D6\r
+#define UDCR2_D5 udcr2.bit._D5\r
+#define UDCR2_D4 udcr2.bit._D4\r
+#define UDCR2_D3 udcr2.bit._D3\r
+#define UDCR2_D2 udcr2.bit._D2\r
+#define UDCR2_D1 udcr2.bit._D1\r
+#define UDCR2_D0 udcr2.bit._D0\r
+__IO_EXTERN UDCC2STR udcc2;  \r
+#define UDCC2 udcc2.word\r
+#define UDCC2_M16E udcc2.bit._M16E\r
+#define UDCC2_CDCF udcc2.bit._CDCF\r
+#define UDCC2_CFIE udcc2.bit._CFIE\r
+#define UDCC2_CLKS udcc2.bit._CLKS\r
+#define UDCC2_CMS1 udcc2.bit._CMS1\r
+#define UDCC2_CMS0 udcc2.bit._CMS0\r
+#define UDCC2_CES1 udcc2.bit._CES1\r
+#define UDCC2_CES0 udcc2.bit._CES0\r
+#define UDCC2_CTUT udcc2.bit._CTUT\r
+#define UDCC2_UCRE udcc2.bit._UCRE\r
+#define UDCC2_RLDE udcc2.bit._RLDE\r
+#define UDCC2_UDCLR udcc2.bit._UDCLR\r
+#define UDCC2_CGSC udcc2.bit._CGSC\r
+#define UDCC2_CGE1 udcc2.bit._CGE1\r
+#define UDCC2_CGE0 udcc2.bit._CGE0\r
+#define UDCC2_CMS udcc2.bitc._CMS\r
+#define UDCC2_CES udcc2.bitc._CES\r
+#define UDCC2_CGE udcc2.bitc._CGE\r
+__IO_EXTERN UDCCH2STR udcch2;  \r
+#define UDCCH2 udcch2.byte\r
+#define UDCCH2_M16E udcch2.bit._M16E\r
+#define UDCCH2_CDCF udcch2.bit._CDCF\r
+#define UDCCH2_CFIE udcch2.bit._CFIE\r
+#define UDCCH2_CLKS udcch2.bit._CLKS\r
+#define UDCCH2_CMS1 udcch2.bit._CMS1\r
+#define UDCCH2_CMS0 udcch2.bit._CMS0\r
+#define UDCCH2_CES1 udcch2.bit._CES1\r
+#define UDCCH2_CES0 udcch2.bit._CES0\r
+#define UDCCH2_CMS udcch2.bitc._CMS\r
+#define UDCCH2_CES udcch2.bitc._CES\r
+__IO_EXTERN UDCCL2STR udccl2;  \r
+#define UDCCL2 udccl2.byte\r
+#define UDCCL2_CTUT udccl2.bit._CTUT\r
+#define UDCCL2_UCRE udccl2.bit._UCRE\r
+#define UDCCL2_RLDE udccl2.bit._RLDE\r
+#define UDCCL2_UDCLR udccl2.bit._UDCLR\r
+#define UDCCL2_CGSC udccl2.bit._CGSC\r
+#define UDCCL2_CGE1 udccl2.bit._CGE1\r
+#define UDCCL2_CGE0 udccl2.bit._CGE0\r
+#define UDCCL2_CGE udccl2.bitc._CGE\r
+__IO_EXTERN UDCS2STR udcs2;  \r
+#define UDCS2 udcs2.byte\r
+#define UDCS2_CSTR udcs2.bit._CSTR\r
+#define UDCS2_CITE udcs2.bit._CITE\r
+#define UDCS2_UDIE udcs2.bit._UDIE\r
+#define UDCS2_CMPF udcs2.bit._CMPF\r
+#define UDCS2_OVFF udcs2.bit._OVFF\r
+#define UDCS2_UDFF udcs2.bit._UDFF\r
+#define UDCS2_UDF1 udcs2.bit._UDF1\r
+#define UDCS2_UDF0 udcs2.bit._UDF0\r
+#define UDCS2_UDF udcs2.bitc._UDF\r
+__IO_EXTERN UDCC3STR udcc3;  \r
+#define UDCC3 udcc3.word\r
+#define UDCC3_RESV15 udcc3.bit._RESV15\r
+#define UDCC3_CDCF udcc3.bit._CDCF\r
+#define UDCC3_CFIE udcc3.bit._CFIE\r
+#define UDCC3_CLKS udcc3.bit._CLKS\r
+#define UDCC3_CMS1 udcc3.bit._CMS1\r
+#define UDCC3_CMS0 udcc3.bit._CMS0\r
+#define UDCC3_CES1 udcc3.bit._CES1\r
+#define UDCC3_CES0 udcc3.bit._CES0\r
+#define UDCC3_CTUT udcc3.bit._CTUT\r
+#define UDCC3_UCRE udcc3.bit._UCRE\r
+#define UDCC3_RLDE udcc3.bit._RLDE\r
+#define UDCC3_UDCLR udcc3.bit._UDCLR\r
+#define UDCC3_CGSC udcc3.bit._CGSC\r
+#define UDCC3_CGE1 udcc3.bit._CGE1\r
+#define UDCC3_CGE0 udcc3.bit._CGE0\r
+#define UDCC3_CMS udcc3.bitc._CMS\r
+#define UDCC3_CES udcc3.bitc._CES\r
+#define UDCC3_CGE udcc3.bitc._CGE\r
+__IO_EXTERN UDCCH3STR udcch3;  \r
+#define UDCCH3 udcch3.byte\r
+#define UDCCH3_RESV15 udcch3.bit._RESV15\r
+#define UDCCH3_CDCF udcch3.bit._CDCF\r
+#define UDCCH3_CFIE udcch3.bit._CFIE\r
+#define UDCCH3_CLKS udcch3.bit._CLKS\r
+#define UDCCH3_CMS1 udcch3.bit._CMS1\r
+#define UDCCH3_CMS0 udcch3.bit._CMS0\r
+#define UDCCH3_CES1 udcch3.bit._CES1\r
+#define UDCCH3_CES0 udcch3.bit._CES0\r
+#define UDCCH3_CMS udcch3.bitc._CMS\r
+#define UDCCH3_CES udcch3.bitc._CES\r
+__IO_EXTERN UDCCL3STR udccl3;  \r
+#define UDCCL3 udccl3.byte\r
+#define UDCCL3_CTUT udccl3.bit._CTUT\r
+#define UDCCL3_UCRE udccl3.bit._UCRE\r
+#define UDCCL3_RLDE udccl3.bit._RLDE\r
+#define UDCCL3_UDCLR udccl3.bit._UDCLR\r
+#define UDCCL3_CGSC udccl3.bit._CGSC\r
+#define UDCCL3_CGE1 udccl3.bit._CGE1\r
+#define UDCCL3_CGE0 udccl3.bit._CGE0\r
+#define UDCCL3_CGE udccl3.bitc._CGE\r
+__IO_EXTERN UDCS3STR udcs3;  \r
+#define UDCS3 udcs3.byte\r
+#define UDCS3_CSTR udcs3.bit._CSTR\r
+#define UDCS3_CITE udcs3.bit._CITE\r
+#define UDCS3_UDIE udcs3.bit._UDIE\r
+#define UDCS3_CMPF udcs3.bit._CMPF\r
+#define UDCS3_OVFF udcs3.bit._OVFF\r
+#define UDCS3_UDFF udcs3.bit._UDFF\r
+#define UDCS3_UDF1 udcs3.bit._UDF1\r
+#define UDCS3_UDF0 udcs3.bit._UDF0\r
+#define UDCS3_UDF udcs3.bitc._UDF\r
+__IO_EXTERN GCN13STR gcn13;   /* PPG Control 12-15 */\r
+#define GCN13 gcn13.word\r
+#define GCN13_TSEL33 gcn13.bit._TSEL33\r
+#define GCN13_TSEL32 gcn13.bit._TSEL32\r
+#define GCN13_TSEL31 gcn13.bit._TSEL31\r
+#define GCN13_TSEL30 gcn13.bit._TSEL30\r
+#define GCN13_TSEL23 gcn13.bit._TSEL23\r
+#define GCN13_TSEL22 gcn13.bit._TSEL22\r
+#define GCN13_TSEL21 gcn13.bit._TSEL21\r
+#define GCN13_TSEL20 gcn13.bit._TSEL20\r
+#define GCN13_TSEL13 gcn13.bit._TSEL13\r
+#define GCN13_TSEL12 gcn13.bit._TSEL12\r
+#define GCN13_TSEL11 gcn13.bit._TSEL11\r
+#define GCN13_TSEL10 gcn13.bit._TSEL10\r
+#define GCN13_TSEL03 gcn13.bit._TSEL03\r
+#define GCN13_TSEL02 gcn13.bit._TSEL02\r
+#define GCN13_TSEL01 gcn13.bit._TSEL01\r
+#define GCN13_TSEL00 gcn13.bit._TSEL00\r
+__IO_EXTERN GCN23STR gcn23;  \r
+#define GCN23 gcn23.byte\r
+#define GCN23_EN3 gcn23.bit._EN3\r
+#define GCN23_EN2 gcn23.bit._EN2\r
+#define GCN23_EN1 gcn23.bit._EN1\r
+#define GCN23_EN0 gcn23.bit._EN0\r
+__IO_EXTERN IO_WORD ptmr12;   /* PPG 12 */\r
+#define PTMR12 ptmr12\r
+__IO_EXTERN IO_WORD pcsr12;  \r
+#define PCSR12 pcsr12\r
+__IO_EXTERN IO_WORD pdut12;  \r
+#define PDUT12 pdut12\r
+__IO_EXTERN PCN12STR pcn12;  \r
+#define PCN12 pcn12.word\r
+#define PCN12_CNTE pcn12.bit._CNTE\r
+#define PCN12_STGR pcn12.bit._STGR\r
+#define PCN12_MDSE pcn12.bit._MDSE\r
+#define PCN12_RTRG pcn12.bit._RTRG\r
+#define PCN12_CKS1 pcn12.bit._CKS1\r
+#define PCN12_CKS0 pcn12.bit._CKS0\r
+#define PCN12_PGMS pcn12.bit._PGMS\r
+#define PCN12_EGS1 pcn12.bit._EGS1\r
+#define PCN12_EGS0 pcn12.bit._EGS0\r
+#define PCN12_IREN pcn12.bit._IREN\r
+#define PCN12_IRQF pcn12.bit._IRQF\r
+#define PCN12_IRS1 pcn12.bit._IRS1\r
+#define PCN12_IRS0 pcn12.bit._IRS0\r
+#define PCN12_OSEL pcn12.bit._OSEL\r
+#define PCN12_CKS pcn12.bitc._CKS\r
+#define PCN12_EGS pcn12.bitc._EGS\r
+#define PCN12_IRS pcn12.bitc._IRS\r
+__IO_EXTERN PCNH12STR pcnh12;  \r
+#define PCNH12 pcnh12.byte\r
+#define PCNH12_CNTE pcnh12.bit._CNTE\r
+#define PCNH12_STGR pcnh12.bit._STGR\r
+#define PCNH12_MDSE pcnh12.bit._MDSE\r
+#define PCNH12_RTRG pcnh12.bit._RTRG\r
+#define PCNH12_CKS1 pcnh12.bit._CKS1\r
+#define PCNH12_CKS0 pcnh12.bit._CKS0\r
+#define PCNH12_PGMS pcnh12.bit._PGMS\r
+#define PCNH12_CKS pcnh12.bitc._CKS\r
+__IO_EXTERN PCNL12STR pcnl12;  \r
+#define PCNL12 pcnl12.byte\r
+#define PCNL12_EGS1 pcnl12.bit._EGS1\r
+#define PCNL12_EGS0 pcnl12.bit._EGS0\r
+#define PCNL12_IREN pcnl12.bit._IREN\r
+#define PCNL12_IRQF pcnl12.bit._IRQF\r
+#define PCNL12_IRS1 pcnl12.bit._IRS1\r
+#define PCNL12_IRS0 pcnl12.bit._IRS0\r
+#define PCNL12_OSEL pcnl12.bit._OSEL\r
+#define PCNL12_EGS pcnl12.bitc._EGS\r
+#define PCNL12_IRS pcnl12.bitc._IRS\r
+__IO_EXTERN IO_WORD ptmr13;   /* PPG 13 */\r
+#define PTMR13 ptmr13\r
+__IO_EXTERN IO_WORD pcsr13;  \r
+#define PCSR13 pcsr13\r
+__IO_EXTERN IO_WORD pdut13;  \r
+#define PDUT13 pdut13\r
+__IO_EXTERN PCN13STR pcn13;  \r
+#define PCN13 pcn13.word\r
+#define PCN13_CNTE pcn13.bit._CNTE\r
+#define PCN13_STGR pcn13.bit._STGR\r
+#define PCN13_MDSE pcn13.bit._MDSE\r
+#define PCN13_RTRG pcn13.bit._RTRG\r
+#define PCN13_CKS1 pcn13.bit._CKS1\r
+#define PCN13_CKS0 pcn13.bit._CKS0\r
+#define PCN13_PGMS pcn13.bit._PGMS\r
+#define PCN13_EGS1 pcn13.bit._EGS1\r
+#define PCN13_EGS0 pcn13.bit._EGS0\r
+#define PCN13_IREN pcn13.bit._IREN\r
+#define PCN13_IRQF pcn13.bit._IRQF\r
+#define PCN13_IRS1 pcn13.bit._IRS1\r
+#define PCN13_IRS0 pcn13.bit._IRS0\r
+#define PCN13_OSEL pcn13.bit._OSEL\r
+#define PCN13_CKS pcn13.bitc._CKS\r
+#define PCN13_EGS pcn13.bitc._EGS\r
+#define PCN13_IRS pcn13.bitc._IRS\r
+__IO_EXTERN PCNH13STR pcnh13;  \r
+#define PCNH13 pcnh13.byte\r
+#define PCNH13_CNTE pcnh13.bit._CNTE\r
+#define PCNH13_STGR pcnh13.bit._STGR\r
+#define PCNH13_MDSE pcnh13.bit._MDSE\r
+#define PCNH13_RTRG pcnh13.bit._RTRG\r
+#define PCNH13_CKS1 pcnh13.bit._CKS1\r
+#define PCNH13_CKS0 pcnh13.bit._CKS0\r
+#define PCNH13_PGMS pcnh13.bit._PGMS\r
+#define PCNH13_CKS pcnh13.bitc._CKS\r
+__IO_EXTERN PCNL13STR pcnl13;  \r
+#define PCNL13 pcnl13.byte\r
+#define PCNL13_EGS1 pcnl13.bit._EGS1\r
+#define PCNL13_EGS0 pcnl13.bit._EGS0\r
+#define PCNL13_IREN pcnl13.bit._IREN\r
+#define PCNL13_IRQF pcnl13.bit._IRQF\r
+#define PCNL13_IRS1 pcnl13.bit._IRS1\r
+#define PCNL13_IRS0 pcnl13.bit._IRS0\r
+#define PCNL13_OSEL pcnl13.bit._OSEL\r
+#define PCNL13_EGS pcnl13.bitc._EGS\r
+#define PCNL13_IRS pcnl13.bitc._IRS\r
+__IO_EXTERN IO_WORD ptmr14;   /* PPG 14 */\r
+#define PTMR14 ptmr14\r
+__IO_EXTERN IO_WORD pcsr14;  \r
+#define PCSR14 pcsr14\r
+__IO_EXTERN IO_WORD pdut14;  \r
+#define PDUT14 pdut14\r
+__IO_EXTERN PCN14STR pcn14;  \r
+#define PCN14 pcn14.word\r
+#define PCN14_CNTE pcn14.bit._CNTE\r
+#define PCN14_STGR pcn14.bit._STGR\r
+#define PCN14_MDSE pcn14.bit._MDSE\r
+#define PCN14_RTRG pcn14.bit._RTRG\r
+#define PCN14_CKS1 pcn14.bit._CKS1\r
+#define PCN14_CKS0 pcn14.bit._CKS0\r
+#define PCN14_PGMS pcn14.bit._PGMS\r
+#define PCN14_EGS1 pcn14.bit._EGS1\r
+#define PCN14_EGS0 pcn14.bit._EGS0\r
+#define PCN14_IREN pcn14.bit._IREN\r
+#define PCN14_IRQF pcn14.bit._IRQF\r
+#define PCN14_IRS1 pcn14.bit._IRS1\r
+#define PCN14_IRS0 pcn14.bit._IRS0\r
+#define PCN14_OSEL pcn14.bit._OSEL\r
+#define PCN14_CKS pcn14.bitc._CKS\r
+#define PCN14_EGS pcn14.bitc._EGS\r
+#define PCN14_IRS pcn14.bitc._IRS\r
+__IO_EXTERN PCNH14STR pcnh14;  \r
+#define PCNH14 pcnh14.byte\r
+#define PCNH14_CNTE pcnh14.bit._CNTE\r
+#define PCNH14_STGR pcnh14.bit._STGR\r
+#define PCNH14_MDSE pcnh14.bit._MDSE\r
+#define PCNH14_RTRG pcnh14.bit._RTRG\r
+#define PCNH14_CKS1 pcnh14.bit._CKS1\r
+#define PCNH14_CKS0 pcnh14.bit._CKS0\r
+#define PCNH14_PGMS pcnh14.bit._PGMS\r
+#define PCNH14_CKS pcnh14.bitc._CKS\r
+__IO_EXTERN PCNL14STR pcnl14;  \r
+#define PCNL14 pcnl14.byte\r
+#define PCNL14_EGS1 pcnl14.bit._EGS1\r
+#define PCNL14_EGS0 pcnl14.bit._EGS0\r
+#define PCNL14_IREN pcnl14.bit._IREN\r
+#define PCNL14_IRQF pcnl14.bit._IRQF\r
+#define PCNL14_IRS1 pcnl14.bit._IRS1\r
+#define PCNL14_IRS0 pcnl14.bit._IRS0\r
+#define PCNL14_OSEL pcnl14.bit._OSEL\r
+#define PCNL14_EGS pcnl14.bitc._EGS\r
+#define PCNL14_IRS pcnl14.bitc._IRS\r
+__IO_EXTERN IO_WORD ptmr15;   /* PPG 15 */\r
+#define PTMR15 ptmr15\r
+__IO_EXTERN IO_WORD pcsr15;  \r
+#define PCSR15 pcsr15\r
+__IO_EXTERN IO_WORD pdut15;  \r
+#define PDUT15 pdut15\r
+__IO_EXTERN PCN15STR pcn15;  \r
+#define PCN15 pcn15.word\r
+#define PCN15_CNTE pcn15.bit._CNTE\r
+#define PCN15_STGR pcn15.bit._STGR\r
+#define PCN15_MDSE pcn15.bit._MDSE\r
+#define PCN15_RTRG pcn15.bit._RTRG\r
+#define PCN15_CKS1 pcn15.bit._CKS1\r
+#define PCN15_CKS0 pcn15.bit._CKS0\r
+#define PCN15_PGMS pcn15.bit._PGMS\r
+#define PCN15_EGS1 pcn15.bit._EGS1\r
+#define PCN15_EGS0 pcn15.bit._EGS0\r
+#define PCN15_IREN pcn15.bit._IREN\r
+#define PCN15_IRQF pcn15.bit._IRQF\r
+#define PCN15_IRS1 pcn15.bit._IRS1\r
+#define PCN15_IRS0 pcn15.bit._IRS0\r
+#define PCN15_OSEL pcn15.bit._OSEL\r
+#define PCN15_CKS pcn15.bitc._CKS\r
+#define PCN15_EGS pcn15.bitc._EGS\r
+#define PCN15_IRS pcn15.bitc._IRS\r
+__IO_EXTERN PCNH15STR pcnh15;  \r
+#define PCNH15 pcnh15.byte\r
+#define PCNH15_CNTE pcnh15.bit._CNTE\r
+#define PCNH15_STGR pcnh15.bit._STGR\r
+#define PCNH15_MDSE pcnh15.bit._MDSE\r
+#define PCNH15_RTRG pcnh15.bit._RTRG\r
+#define PCNH15_CKS1 pcnh15.bit._CKS1\r
+#define PCNH15_CKS0 pcnh15.bit._CKS0\r
+#define PCNH15_PGMS pcnh15.bit._PGMS\r
+#define PCNH15_CKS pcnh15.bitc._CKS\r
+__IO_EXTERN PCNL15STR pcnl15;  \r
+#define PCNL15 pcnl15.byte\r
+#define PCNL15_EGS1 pcnl15.bit._EGS1\r
+#define PCNL15_EGS0 pcnl15.bit._EGS0\r
+#define PCNL15_IREN pcnl15.bit._IREN\r
+#define PCNL15_IRQF pcnl15.bit._IRQF\r
+#define PCNL15_IRS1 pcnl15.bit._IRS1\r
+#define PCNL15_IRS0 pcnl15.bit._IRS0\r
+#define PCNL15_OSEL pcnl15.bit._OSEL\r
+#define PCNL15_EGS pcnl15.bitc._EGS\r
+#define PCNL15_IRS pcnl15.bitc._IRS\r
+__IO_EXTERN IBCR2STR ibcr2;   /* I2C 2 */\r
+#define IBCR2 ibcr2.byte\r
+#define IBCR2_BER ibcr2.bit._BER\r
+#define IBCR2_BEIE ibcr2.bit._BEIE\r
+#define IBCR2_SCC ibcr2.bit._SCC\r
+#define IBCR2_MSS ibcr2.bit._MSS\r
+#define IBCR2_ACK ibcr2.bit._ACK\r
+#define IBCR2_GCAA ibcr2.bit._GCAA\r
+#define IBCR2_INTE ibcr2.bit._INTE\r
+#define IBCR2_INT ibcr2.bit._INT\r
+__IO_EXTERN IBSR2STR ibsr2;  \r
+#define IBSR2 ibsr2.byte\r
+#define IBSR2_BB ibsr2.bit._BB\r
+#define IBSR2_RSC ibsr2.bit._RSC\r
+#define IBSR2_AL ibsr2.bit._AL\r
+#define IBSR2_LRB ibsr2.bit._LRB\r
+#define IBSR2_TRX ibsr2.bit._TRX\r
+#define IBSR2_AAS ibsr2.bit._AAS\r
+#define IBSR2_GCA ibsr2.bit._GCA\r
+#define IBSR2_ADT ibsr2.bit._ADT\r
+__IO_EXTERN ITBA2STR itba2;  \r
+#define ITBA2 itba2.word\r
+#define ITBA2_TA9 itba2.bit._TA9\r
+#define ITBA2_TA8 itba2.bit._TA8\r
+#define ITBA2_TA7 itba2.bit._TA7\r
+#define ITBA2_TA6 itba2.bit._TA6\r
+#define ITBA2_TA5 itba2.bit._TA5\r
+#define ITBA2_TA4 itba2.bit._TA4\r
+#define ITBA2_TA3 itba2.bit._TA3\r
+#define ITBA2_TA2 itba2.bit._TA2\r
+#define ITBA2_TA1 itba2.bit._TA1\r
+#define ITBA2_TA0 itba2.bit._TA0\r
+__IO_EXTERN ITBAH2STR itbah2;  \r
+#define ITBAH2 itbah2.byte\r
+#define ITBAH2_TA9 itbah2.bit._TA9\r
+#define ITBAH2_TA8 itbah2.bit._TA8\r
+__IO_EXTERN ITBAL2STR itbal2;  \r
+#define ITBAL2 itbal2.byte\r
+#define ITBAL2_TA7 itbal2.bit._TA7\r
+#define ITBAL2_TA6 itbal2.bit._TA6\r
+#define ITBAL2_TA5 itbal2.bit._TA5\r
+#define ITBAL2_TA4 itbal2.bit._TA4\r
+#define ITBAL2_TA3 itbal2.bit._TA3\r
+#define ITBAL2_TA2 itbal2.bit._TA2\r
+#define ITBAL2_TA1 itbal2.bit._TA1\r
+#define ITBAL2_TA0 itbal2.bit._TA0\r
+__IO_EXTERN ITMK2STR itmk2;  \r
+#define ITMK2 itmk2.word\r
+#define ITMK2_ENTB itmk2.bit._ENTB\r
+#define ITMK2_RAL itmk2.bit._RAL\r
+#define ITMK2_TM9 itmk2.bit._TM9\r
+#define ITMK2_TM8 itmk2.bit._TM8\r
+#define ITMK2_TM7 itmk2.bit._TM7\r
+#define ITMK2_TM6 itmk2.bit._TM6\r
+#define ITMK2_TM5 itmk2.bit._TM5\r
+#define ITMK2_TM4 itmk2.bit._TM4\r
+#define ITMK2_TM3 itmk2.bit._TM3\r
+#define ITMK2_TM2 itmk2.bit._TM2\r
+#define ITMK2_TM1 itmk2.bit._TM1\r
+#define ITMK2_TM0 itmk2.bit._TM0\r
+__IO_EXTERN ITMKH2STR itmkh2;  \r
+#define ITMKH2 itmkh2.byte\r
+#define ITMKH2_ENTB itmkh2.bit._ENTB\r
+#define ITMKH2_RAL itmkh2.bit._RAL\r
+#define ITMKH2_TM9 itmkh2.bit._TM9\r
+#define ITMKH2_TM8 itmkh2.bit._TM8\r
+__IO_EXTERN ITMKL2STR itmkl2;  \r
+#define ITMKL2 itmkl2.byte\r
+#define ITMKL2_TM7 itmkl2.bit._TM7\r
+#define ITMKL2_TM6 itmkl2.bit._TM6\r
+#define ITMKL2_TM5 itmkl2.bit._TM5\r
+#define ITMKL2_TM4 itmkl2.bit._TM4\r
+#define ITMKL2_TM3 itmkl2.bit._TM3\r
+#define ITMKL2_TM2 itmkl2.bit._TM2\r
+#define ITMKL2_TM1 itmkl2.bit._TM1\r
+#define ITMKL2_TM0 itmkl2.bit._TM0\r
+__IO_EXTERN ISMK2STR ismk2;  \r
+#define ISMK2 ismk2.byte\r
+#define ISMK2_ENSB ismk2.bit._ENSB\r
+#define ISMK2_SM6 ismk2.bit._SM6\r
+#define ISMK2_SM5 ismk2.bit._SM5\r
+#define ISMK2_SM4 ismk2.bit._SM4\r
+#define ISMK2_SM3 ismk2.bit._SM3\r
+#define ISMK2_SM2 ismk2.bit._SM2\r
+#define ISMK2_SM1 ismk2.bit._SM1\r
+#define ISMK2_SM0 ismk2.bit._SM0\r
+__IO_EXTERN ISBA2STR isba2;  \r
+#define ISBA2 isba2.byte\r
+#define ISBA2_SA6 isba2.bit._SA6\r
+#define ISBA2_SA5 isba2.bit._SA5\r
+#define ISBA2_SA4 isba2.bit._SA4\r
+#define ISBA2_SA3 isba2.bit._SA3\r
+#define ISBA2_SA2 isba2.bit._SA2\r
+#define ISBA2_SA1 isba2.bit._SA1\r
+#define ISBA2_SA0 isba2.bit._SA0\r
+__IO_EXTERN IDAR2STR idar2;  \r
+#define IDAR2 idar2.byte\r
+#define IDAR2_D7 idar2.bit._D7\r
+#define IDAR2_D6 idar2.bit._D6\r
+#define IDAR2_D5 idar2.bit._D5\r
+#define IDAR2_D4 idar2.bit._D4\r
+#define IDAR2_D3 idar2.bit._D3\r
+#define IDAR2_D2 idar2.bit._D2\r
+#define IDAR2_D1 idar2.bit._D1\r
+#define IDAR2_D0 idar2.bit._D0\r
+__IO_EXTERN ICCR2STR iccr2;  \r
+#define ICCR2 iccr2.byte\r
+#define ICCR2_NSF iccr2.bit._NSF\r
+#define ICCR2_EN iccr2.bit._EN\r
+#define ICCR2_CS4 iccr2.bit._CS4\r
+#define ICCR2_CS3 iccr2.bit._CS3\r
+#define ICCR2_CS2 iccr2.bit._CS2\r
+#define ICCR2_CS1 iccr2.bit._CS1\r
+#define ICCR2_CS0 iccr2.bit._CS0\r
+#define ICCR2_CS iccr2.bitc._CS\r
+__IO_EXTERN IBCR3STR ibcr3;   /* I2C 3 */\r
+#define IBCR3 ibcr3.byte\r
+#define IBCR3_BER ibcr3.bit._BER\r
+#define IBCR3_BEIE ibcr3.bit._BEIE\r
+#define IBCR3_SCC ibcr3.bit._SCC\r
+#define IBCR3_MSS ibcr3.bit._MSS\r
+#define IBCR3_ACK ibcr3.bit._ACK\r
+#define IBCR3_GCAA ibcr3.bit._GCAA\r
+#define IBCR3_INTE ibcr3.bit._INTE\r
+#define IBCR3_INT ibcr3.bit._INT\r
+__IO_EXTERN IBSR3STR ibsr3;  \r
+#define IBSR3 ibsr3.byte\r
+#define IBSR3_BB ibsr3.bit._BB\r
+#define IBSR3_RSC ibsr3.bit._RSC\r
+#define IBSR3_AL ibsr3.bit._AL\r
+#define IBSR3_LRB ibsr3.bit._LRB\r
+#define IBSR3_TRX ibsr3.bit._TRX\r
+#define IBSR3_AAS ibsr3.bit._AAS\r
+#define IBSR3_GCA ibsr3.bit._GCA\r
+#define IBSR3_ADT ibsr3.bit._ADT\r
+__IO_EXTERN ITBA3STR itba3;  \r
+#define ITBA3 itba3.word\r
+#define ITBA3_TA9 itba3.bit._TA9\r
+#define ITBA3_TA8 itba3.bit._TA8\r
+#define ITBA3_TA7 itba3.bit._TA7\r
+#define ITBA3_TA6 itba3.bit._TA6\r
+#define ITBA3_TA5 itba3.bit._TA5\r
+#define ITBA3_TA4 itba3.bit._TA4\r
+#define ITBA3_TA3 itba3.bit._TA3\r
+#define ITBA3_TA2 itba3.bit._TA2\r
+#define ITBA3_TA1 itba3.bit._TA1\r
+#define ITBA3_TA0 itba3.bit._TA0\r
+__IO_EXTERN ITBAH3STR itbah3;  \r
+#define ITBAH3 itbah3.byte\r
+#define ITBAH3_TA9 itbah3.bit._TA9\r
+#define ITBAH3_TA8 itbah3.bit._TA8\r
+__IO_EXTERN ITBAL3STR itbal3;  \r
+#define ITBAL3 itbal3.byte\r
+#define ITBAL3_TA7 itbal3.bit._TA7\r
+#define ITBAL3_TA6 itbal3.bit._TA6\r
+#define ITBAL3_TA5 itbal3.bit._TA5\r
+#define ITBAL3_TA4 itbal3.bit._TA4\r
+#define ITBAL3_TA3 itbal3.bit._TA3\r
+#define ITBAL3_TA2 itbal3.bit._TA2\r
+#define ITBAL3_TA1 itbal3.bit._TA1\r
+#define ITBAL3_TA0 itbal3.bit._TA0\r
+__IO_EXTERN ITMK3STR itmk3;  \r
+#define ITMK3 itmk3.word\r
+#define ITMK3_ENTB itmk3.bit._ENTB\r
+#define ITMK3_RAL itmk3.bit._RAL\r
+#define ITMK3_TM9 itmk3.bit._TM9\r
+#define ITMK3_TM8 itmk3.bit._TM8\r
+#define ITMK3_TM7 itmk3.bit._TM7\r
+#define ITMK3_TM6 itmk3.bit._TM6\r
+#define ITMK3_TM5 itmk3.bit._TM5\r
+#define ITMK3_TM4 itmk3.bit._TM4\r
+#define ITMK3_TM3 itmk3.bit._TM3\r
+#define ITMK3_TM2 itmk3.bit._TM2\r
+#define ITMK3_TM1 itmk3.bit._TM1\r
+#define ITMK3_TM0 itmk3.bit._TM0\r
+__IO_EXTERN ITMKH3STR itmkh3;  \r
+#define ITMKH3 itmkh3.byte\r
+#define ITMKH3_ENTB itmkh3.bit._ENTB\r
+#define ITMKH3_RAL itmkh3.bit._RAL\r
+#define ITMKH3_TM9 itmkh3.bit._TM9\r
+#define ITMKH3_TM8 itmkh3.bit._TM8\r
+__IO_EXTERN ITMKL3STR itmkl3;  \r
+#define ITMKL3 itmkl3.byte\r
+#define ITMKL3_TM7 itmkl3.bit._TM7\r
+#define ITMKL3_TM6 itmkl3.bit._TM6\r
+#define ITMKL3_TM5 itmkl3.bit._TM5\r
+#define ITMKL3_TM4 itmkl3.bit._TM4\r
+#define ITMKL3_TM3 itmkl3.bit._TM3\r
+#define ITMKL3_TM2 itmkl3.bit._TM2\r
+#define ITMKL3_TM1 itmkl3.bit._TM1\r
+#define ITMKL3_TM0 itmkl3.bit._TM0\r
+__IO_EXTERN ISMK3STR ismk3;  \r
+#define ISMK3 ismk3.byte\r
+#define ISMK3_ENSB ismk3.bit._ENSB\r
+#define ISMK3_SM6 ismk3.bit._SM6\r
+#define ISMK3_SM5 ismk3.bit._SM5\r
+#define ISMK3_SM4 ismk3.bit._SM4\r
+#define ISMK3_SM3 ismk3.bit._SM3\r
+#define ISMK3_SM2 ismk3.bit._SM2\r
+#define ISMK3_SM1 ismk3.bit._SM1\r
+#define ISMK3_SM0 ismk3.bit._SM0\r
+__IO_EXTERN ISBA3STR isba3;  \r
+#define ISBA3 isba3.byte\r
+#define ISBA3_SA6 isba3.bit._SA6\r
+#define ISBA3_SA5 isba3.bit._SA5\r
+#define ISBA3_SA4 isba3.bit._SA4\r
+#define ISBA3_SA3 isba3.bit._SA3\r
+#define ISBA3_SA2 isba3.bit._SA2\r
+#define ISBA3_SA1 isba3.bit._SA1\r
+#define ISBA3_SA0 isba3.bit._SA0\r
+__IO_EXTERN IDAR3STR idar3;  \r
+#define IDAR3 idar3.byte\r
+#define IDAR3_D7 idar3.bit._D7\r
+#define IDAR3_D6 idar3.bit._D6\r
+#define IDAR3_D5 idar3.bit._D5\r
+#define IDAR3_D4 idar3.bit._D4\r
+#define IDAR3_D3 idar3.bit._D3\r
+#define IDAR3_D2 idar3.bit._D2\r
+#define IDAR3_D1 idar3.bit._D1\r
+#define IDAR3_D0 idar3.bit._D0\r
+__IO_EXTERN ICCR3STR iccr3;  \r
+#define ICCR3 iccr3.byte\r
+#define ICCR3_NSF iccr3.bit._NSF\r
+#define ICCR3_EN iccr3.bit._EN\r
+#define ICCR3_CS4 iccr3.bit._CS4\r
+#define ICCR3_CS3 iccr3.bit._CS3\r
+#define ICCR3_CS2 iccr3.bit._CS2\r
+#define ICCR3_CS1 iccr3.bit._CS1\r
+#define ICCR3_CS0 iccr3.bit._CS0\r
+#define ICCR3_CS iccr3.bitc._CS\r
+__IO_EXTERN ROMSSTR roms;   /* ROM Select Register */\r
+#define ROMS roms.word\r
+#define ROMS_D15 roms.bit._D15\r
+#define ROMS_D14 roms.bit._D14\r
+#define ROMS_D13 roms.bit._D13\r
+#define ROMS_D12 roms.bit._D12\r
+#define ROMS_D11 roms.bit._D11\r
+#define ROMS_D10 roms.bit._D10\r
+#define ROMS_D9 roms.bit._D9\r
+#define ROMS_D8 roms.bit._D8\r
+#define ROMS_D7 roms.bit._D7\r
+#define ROMS_D6 roms.bit._D6\r
+#define ROMS_D5 roms.bit._D5\r
+#define ROMS_D4 roms.bit._D4\r
+#define ROMS_D3 roms.bit._D3\r
+#define ROMS_D2 roms.bit._D2\r
+#define ROMS_D1 roms.bit._D1\r
+#define ROMS_D0 roms.bit._D0\r
+__IO_EXTERN IO_LWORD bsd0;   /* Bit Search Module */\r
+#define BSD0 bsd0\r
+__IO_EXTERN IO_LWORD bsd1;  \r
+#define BSD1 bsd1\r
+__IO_EXTERN IO_LWORD bsdc;  \r
+#define BSDC bsdc\r
+__IO_EXTERN IO_LWORD bsrr;  \r
+#define BSRR bsrr\r
+__IO_EXTERN ICR00STR icr00;   /* Interrupt Control Unit */\r
+#define ICR00 icr00.byte\r
+#define ICR00_ICR4 icr00.bit._ICR4\r
+#define ICR00_ICR3 icr00.bit._ICR3\r
+#define ICR00_ICR2 icr00.bit._ICR2\r
+#define ICR00_ICR1 icr00.bit._ICR1\r
+#define ICR00_ICR0 icr00.bit._ICR0\r
+__IO_EXTERN ICR01STR icr01;  \r
+#define ICR01 icr01.byte\r
+#define ICR01_ICR4 icr01.bit._ICR4\r
+#define ICR01_ICR3 icr01.bit._ICR3\r
+#define ICR01_ICR2 icr01.bit._ICR2\r
+#define ICR01_ICR1 icr01.bit._ICR1\r
+#define ICR01_ICR0 icr01.bit._ICR0\r
+__IO_EXTERN ICR02STR icr02;  \r
+#define ICR02 icr02.byte\r
+#define ICR02_ICR4 icr02.bit._ICR4\r
+#define ICR02_ICR3 icr02.bit._ICR3\r
+#define ICR02_ICR2 icr02.bit._ICR2\r
+#define ICR02_ICR1 icr02.bit._ICR1\r
+#define ICR02_ICR0 icr02.bit._ICR0\r
+__IO_EXTERN ICR03STR icr03;  \r
+#define ICR03 icr03.byte\r
+#define ICR03_ICR4 icr03.bit._ICR4\r
+#define ICR03_ICR3 icr03.bit._ICR3\r
+#define ICR03_ICR2 icr03.bit._ICR2\r
+#define ICR03_ICR1 icr03.bit._ICR1\r
+#define ICR03_ICR0 icr03.bit._ICR0\r
+__IO_EXTERN ICR04STR icr04;  \r
+#define ICR04 icr04.byte\r
+#define ICR04_ICR4 icr04.bit._ICR4\r
+#define ICR04_ICR3 icr04.bit._ICR3\r
+#define ICR04_ICR2 icr04.bit._ICR2\r
+#define ICR04_ICR1 icr04.bit._ICR1\r
+#define ICR04_ICR0 icr04.bit._ICR0\r
+__IO_EXTERN ICR05STR icr05;  \r
+#define ICR05 icr05.byte\r
+#define ICR05_ICR4 icr05.bit._ICR4\r
+#define ICR05_ICR3 icr05.bit._ICR3\r
+#define ICR05_ICR2 icr05.bit._ICR2\r
+#define ICR05_ICR1 icr05.bit._ICR1\r
+#define ICR05_ICR0 icr05.bit._ICR0\r
+__IO_EXTERN ICR06STR icr06;  \r
+#define ICR06 icr06.byte\r
+#define ICR06_ICR4 icr06.bit._ICR4\r
+#define ICR06_ICR3 icr06.bit._ICR3\r
+#define ICR06_ICR2 icr06.bit._ICR2\r
+#define ICR06_ICR1 icr06.bit._ICR1\r
+#define ICR06_ICR0 icr06.bit._ICR0\r
+__IO_EXTERN ICR07STR icr07;  \r
+#define ICR07 icr07.byte\r
+#define ICR07_ICR4 icr07.bit._ICR4\r
+#define ICR07_ICR3 icr07.bit._ICR3\r
+#define ICR07_ICR2 icr07.bit._ICR2\r
+#define ICR07_ICR1 icr07.bit._ICR1\r
+#define ICR07_ICR0 icr07.bit._ICR0\r
+__IO_EXTERN ICR08STR icr08;  \r
+#define ICR08 icr08.byte\r
+#define ICR08_ICR4 icr08.bit._ICR4\r
+#define ICR08_ICR3 icr08.bit._ICR3\r
+#define ICR08_ICR2 icr08.bit._ICR2\r
+#define ICR08_ICR1 icr08.bit._ICR1\r
+#define ICR08_ICR0 icr08.bit._ICR0\r
+__IO_EXTERN ICR09STR icr09;  \r
+#define ICR09 icr09.byte\r
+#define ICR09_ICR4 icr09.bit._ICR4\r
+#define ICR09_ICR3 icr09.bit._ICR3\r
+#define ICR09_ICR2 icr09.bit._ICR2\r
+#define ICR09_ICR1 icr09.bit._ICR1\r
+#define ICR09_ICR0 icr09.bit._ICR0\r
+__IO_EXTERN ICR10STR icr10;  \r
+#define ICR10 icr10.byte\r
+#define ICR10_ICR4 icr10.bit._ICR4\r
+#define ICR10_ICR3 icr10.bit._ICR3\r
+#define ICR10_ICR2 icr10.bit._ICR2\r
+#define ICR10_ICR1 icr10.bit._ICR1\r
+#define ICR10_ICR0 icr10.bit._ICR0\r
+__IO_EXTERN ICR11STR icr11;  \r
+#define ICR11 icr11.byte\r
+#define ICR11_ICR4 icr11.bit._ICR4\r
+#define ICR11_ICR3 icr11.bit._ICR3\r
+#define ICR11_ICR2 icr11.bit._ICR2\r
+#define ICR11_ICR1 icr11.bit._ICR1\r
+#define ICR11_ICR0 icr11.bit._ICR0\r
+__IO_EXTERN ICR12STR icr12;  \r
+#define ICR12 icr12.byte\r
+#define ICR12_ICR4 icr12.bit._ICR4\r
+#define ICR12_ICR3 icr12.bit._ICR3\r
+#define ICR12_ICR2 icr12.bit._ICR2\r
+#define ICR12_ICR1 icr12.bit._ICR1\r
+#define ICR12_ICR0 icr12.bit._ICR0\r
+__IO_EXTERN ICR13STR icr13;  \r
+#define ICR13 icr13.byte\r
+#define ICR13_ICR4 icr13.bit._ICR4\r
+#define ICR13_ICR3 icr13.bit._ICR3\r
+#define ICR13_ICR2 icr13.bit._ICR2\r
+#define ICR13_ICR1 icr13.bit._ICR1\r
+#define ICR13_ICR0 icr13.bit._ICR0\r
+__IO_EXTERN ICR14STR icr14;  \r
+#define ICR14 icr14.byte\r
+#define ICR14_ICR4 icr14.bit._ICR4\r
+#define ICR14_ICR3 icr14.bit._ICR3\r
+#define ICR14_ICR2 icr14.bit._ICR2\r
+#define ICR14_ICR1 icr14.bit._ICR1\r
+#define ICR14_ICR0 icr14.bit._ICR0\r
+__IO_EXTERN ICR15STR icr15;  \r
+#define ICR15 icr15.byte\r
+#define ICR15_ICR4 icr15.bit._ICR4\r
+#define ICR15_ICR3 icr15.bit._ICR3\r
+#define ICR15_ICR2 icr15.bit._ICR2\r
+#define ICR15_ICR1 icr15.bit._ICR1\r
+#define ICR15_ICR0 icr15.bit._ICR0\r
+__IO_EXTERN ICR16STR icr16;  \r
+#define ICR16 icr16.byte\r
+#define ICR16_ICR4 icr16.bit._ICR4\r
+#define ICR16_ICR3 icr16.bit._ICR3\r
+#define ICR16_ICR2 icr16.bit._ICR2\r
+#define ICR16_ICR1 icr16.bit._ICR1\r
+#define ICR16_ICR0 icr16.bit._ICR0\r
+__IO_EXTERN ICR17STR icr17;  \r
+#define ICR17 icr17.byte\r
+#define ICR17_ICR4 icr17.bit._ICR4\r
+#define ICR17_ICR3 icr17.bit._ICR3\r
+#define ICR17_ICR2 icr17.bit._ICR2\r
+#define ICR17_ICR1 icr17.bit._ICR1\r
+#define ICR17_ICR0 icr17.bit._ICR0\r
+__IO_EXTERN ICR18STR icr18;  \r
+#define ICR18 icr18.byte\r
+#define ICR18_ICR4 icr18.bit._ICR4\r
+#define ICR18_ICR3 icr18.bit._ICR3\r
+#define ICR18_ICR2 icr18.bit._ICR2\r
+#define ICR18_ICR1 icr18.bit._ICR1\r
+#define ICR18_ICR0 icr18.bit._ICR0\r
+__IO_EXTERN ICR19STR icr19;  \r
+#define ICR19 icr19.byte\r
+#define ICR19_ICR4 icr19.bit._ICR4\r
+#define ICR19_ICR3 icr19.bit._ICR3\r
+#define ICR19_ICR2 icr19.bit._ICR2\r
+#define ICR19_ICR1 icr19.bit._ICR1\r
+#define ICR19_ICR0 icr19.bit._ICR0\r
+__IO_EXTERN ICR20STR icr20;  \r
+#define ICR20 icr20.byte\r
+#define ICR20_ICR4 icr20.bit._ICR4\r
+#define ICR20_ICR3 icr20.bit._ICR3\r
+#define ICR20_ICR2 icr20.bit._ICR2\r
+#define ICR20_ICR1 icr20.bit._ICR1\r
+#define ICR20_ICR0 icr20.bit._ICR0\r
+__IO_EXTERN ICR21STR icr21;  \r
+#define ICR21 icr21.byte\r
+#define ICR21_ICR4 icr21.bit._ICR4\r
+#define ICR21_ICR3 icr21.bit._ICR3\r
+#define ICR21_ICR2 icr21.bit._ICR2\r
+#define ICR21_ICR1 icr21.bit._ICR1\r
+#define ICR21_ICR0 icr21.bit._ICR0\r
+__IO_EXTERN ICR22STR icr22;  \r
+#define ICR22 icr22.byte\r
+#define ICR22_ICR4 icr22.bit._ICR4\r
+#define ICR22_ICR3 icr22.bit._ICR3\r
+#define ICR22_ICR2 icr22.bit._ICR2\r
+#define ICR22_ICR1 icr22.bit._ICR1\r
+#define ICR22_ICR0 icr22.bit._ICR0\r
+__IO_EXTERN ICR23STR icr23;  \r
+#define ICR23 icr23.byte\r
+#define ICR23_ICR4 icr23.bit._ICR4\r
+#define ICR23_ICR3 icr23.bit._ICR3\r
+#define ICR23_ICR2 icr23.bit._ICR2\r
+#define ICR23_ICR1 icr23.bit._ICR1\r
+#define ICR23_ICR0 icr23.bit._ICR0\r
+__IO_EXTERN ICR24STR icr24;  \r
+#define ICR24 icr24.byte\r
+#define ICR24_ICR4 icr24.bit._ICR4\r
+#define ICR24_ICR3 icr24.bit._ICR3\r
+#define ICR24_ICR2 icr24.bit._ICR2\r
+#define ICR24_ICR1 icr24.bit._ICR1\r
+#define ICR24_ICR0 icr24.bit._ICR0\r
+__IO_EXTERN ICR25STR icr25;  \r
+#define ICR25 icr25.byte\r
+#define ICR25_ICR4 icr25.bit._ICR4\r
+#define ICR25_ICR3 icr25.bit._ICR3\r
+#define ICR25_ICR2 icr25.bit._ICR2\r
+#define ICR25_ICR1 icr25.bit._ICR1\r
+#define ICR25_ICR0 icr25.bit._ICR0\r
+__IO_EXTERN ICR26STR icr26;  \r
+#define ICR26 icr26.byte\r
+#define ICR26_ICR4 icr26.bit._ICR4\r
+#define ICR26_ICR3 icr26.bit._ICR3\r
+#define ICR26_ICR2 icr26.bit._ICR2\r
+#define ICR26_ICR1 icr26.bit._ICR1\r
+#define ICR26_ICR0 icr26.bit._ICR0\r
+__IO_EXTERN ICR27STR icr27;  \r
+#define ICR27 icr27.byte\r
+#define ICR27_ICR4 icr27.bit._ICR4\r
+#define ICR27_ICR3 icr27.bit._ICR3\r
+#define ICR27_ICR2 icr27.bit._ICR2\r
+#define ICR27_ICR1 icr27.bit._ICR1\r
+#define ICR27_ICR0 icr27.bit._ICR0\r
+__IO_EXTERN ICR28STR icr28;  \r
+#define ICR28 icr28.byte\r
+#define ICR28_ICR4 icr28.bit._ICR4\r
+#define ICR28_ICR3 icr28.bit._ICR3\r
+#define ICR28_ICR2 icr28.bit._ICR2\r
+#define ICR28_ICR1 icr28.bit._ICR1\r
+#define ICR28_ICR0 icr28.bit._ICR0\r
+__IO_EXTERN ICR29STR icr29;  \r
+#define ICR29 icr29.byte\r
+#define ICR29_ICR4 icr29.bit._ICR4\r
+#define ICR29_ICR3 icr29.bit._ICR3\r
+#define ICR29_ICR2 icr29.bit._ICR2\r
+#define ICR29_ICR1 icr29.bit._ICR1\r
+#define ICR29_ICR0 icr29.bit._ICR0\r
+__IO_EXTERN ICR30STR icr30;  \r
+#define ICR30 icr30.byte\r
+#define ICR30_ICR4 icr30.bit._ICR4\r
+#define ICR30_ICR3 icr30.bit._ICR3\r
+#define ICR30_ICR2 icr30.bit._ICR2\r
+#define ICR30_ICR1 icr30.bit._ICR1\r
+#define ICR30_ICR0 icr30.bit._ICR0\r
+__IO_EXTERN ICR31STR icr31;  \r
+#define ICR31 icr31.byte\r
+#define ICR31_ICR4 icr31.bit._ICR4\r
+#define ICR31_ICR3 icr31.bit._ICR3\r
+#define ICR31_ICR2 icr31.bit._ICR2\r
+#define ICR31_ICR1 icr31.bit._ICR1\r
+#define ICR31_ICR0 icr31.bit._ICR0\r
+__IO_EXTERN ICR32STR icr32;  \r
+#define ICR32 icr32.byte\r
+#define ICR32_ICR4 icr32.bit._ICR4\r
+#define ICR32_ICR3 icr32.bit._ICR3\r
+#define ICR32_ICR2 icr32.bit._ICR2\r
+#define ICR32_ICR1 icr32.bit._ICR1\r
+#define ICR32_ICR0 icr32.bit._ICR0\r
+__IO_EXTERN ICR33STR icr33;  \r
+#define ICR33 icr33.byte\r
+#define ICR33_ICR4 icr33.bit._ICR4\r
+#define ICR33_ICR3 icr33.bit._ICR3\r
+#define ICR33_ICR2 icr33.bit._ICR2\r
+#define ICR33_ICR1 icr33.bit._ICR1\r
+#define ICR33_ICR0 icr33.bit._ICR0\r
+__IO_EXTERN ICR34STR icr34;  \r
+#define ICR34 icr34.byte\r
+#define ICR34_ICR4 icr34.bit._ICR4\r
+#define ICR34_ICR3 icr34.bit._ICR3\r
+#define ICR34_ICR2 icr34.bit._ICR2\r
+#define ICR34_ICR1 icr34.bit._ICR1\r
+#define ICR34_ICR0 icr34.bit._ICR0\r
+__IO_EXTERN ICR35STR icr35;  \r
+#define ICR35 icr35.byte\r
+#define ICR35_ICR4 icr35.bit._ICR4\r
+#define ICR35_ICR3 icr35.bit._ICR3\r
+#define ICR35_ICR2 icr35.bit._ICR2\r
+#define ICR35_ICR1 icr35.bit._ICR1\r
+#define ICR35_ICR0 icr35.bit._ICR0\r
+__IO_EXTERN ICR36STR icr36;  \r
+#define ICR36 icr36.byte\r
+#define ICR36_ICR4 icr36.bit._ICR4\r
+#define ICR36_ICR3 icr36.bit._ICR3\r
+#define ICR36_ICR2 icr36.bit._ICR2\r
+#define ICR36_ICR1 icr36.bit._ICR1\r
+#define ICR36_ICR0 icr36.bit._ICR0\r
+__IO_EXTERN ICR37STR icr37;  \r
+#define ICR37 icr37.byte\r
+#define ICR37_ICR4 icr37.bit._ICR4\r
+#define ICR37_ICR3 icr37.bit._ICR3\r
+#define ICR37_ICR2 icr37.bit._ICR2\r
+#define ICR37_ICR1 icr37.bit._ICR1\r
+#define ICR37_ICR0 icr37.bit._ICR0\r
+__IO_EXTERN ICR38STR icr38;  \r
+#define ICR38 icr38.byte\r
+#define ICR38_ICR4 icr38.bit._ICR4\r
+#define ICR38_ICR3 icr38.bit._ICR3\r
+#define ICR38_ICR2 icr38.bit._ICR2\r
+#define ICR38_ICR1 icr38.bit._ICR1\r
+#define ICR38_ICR0 icr38.bit._ICR0\r
+__IO_EXTERN ICR39STR icr39;  \r
+#define ICR39 icr39.byte\r
+#define ICR39_ICR4 icr39.bit._ICR4\r
+#define ICR39_ICR3 icr39.bit._ICR3\r
+#define ICR39_ICR2 icr39.bit._ICR2\r
+#define ICR39_ICR1 icr39.bit._ICR1\r
+#define ICR39_ICR0 icr39.bit._ICR0\r
+__IO_EXTERN ICR40STR icr40;  \r
+#define ICR40 icr40.byte\r
+#define ICR40_ICR4 icr40.bit._ICR4\r
+#define ICR40_ICR3 icr40.bit._ICR3\r
+#define ICR40_ICR2 icr40.bit._ICR2\r
+#define ICR40_ICR1 icr40.bit._ICR1\r
+#define ICR40_ICR0 icr40.bit._ICR0\r
+__IO_EXTERN ICR41STR icr41;  \r
+#define ICR41 icr41.byte\r
+#define ICR41_ICR4 icr41.bit._ICR4\r
+#define ICR41_ICR3 icr41.bit._ICR3\r
+#define ICR41_ICR2 icr41.bit._ICR2\r
+#define ICR41_ICR1 icr41.bit._ICR1\r
+#define ICR41_ICR0 icr41.bit._ICR0\r
+__IO_EXTERN ICR42STR icr42;  \r
+#define ICR42 icr42.byte\r
+#define ICR42_ICR4 icr42.bit._ICR4\r
+#define ICR42_ICR3 icr42.bit._ICR3\r
+#define ICR42_ICR2 icr42.bit._ICR2\r
+#define ICR42_ICR1 icr42.bit._ICR1\r
+#define ICR42_ICR0 icr42.bit._ICR0\r
+__IO_EXTERN ICR43STR icr43;  \r
+#define ICR43 icr43.byte\r
+#define ICR43_ICR4 icr43.bit._ICR4\r
+#define ICR43_ICR3 icr43.bit._ICR3\r
+#define ICR43_ICR2 icr43.bit._ICR2\r
+#define ICR43_ICR1 icr43.bit._ICR1\r
+#define ICR43_ICR0 icr43.bit._ICR0\r
+__IO_EXTERN ICR44STR icr44;  \r
+#define ICR44 icr44.byte\r
+#define ICR44_ICR4 icr44.bit._ICR4\r
+#define ICR44_ICR3 icr44.bit._ICR3\r
+#define ICR44_ICR2 icr44.bit._ICR2\r
+#define ICR44_ICR1 icr44.bit._ICR1\r
+#define ICR44_ICR0 icr44.bit._ICR0\r
+__IO_EXTERN ICR45STR icr45;  \r
+#define ICR45 icr45.byte\r
+#define ICR45_ICR4 icr45.bit._ICR4\r
+#define ICR45_ICR3 icr45.bit._ICR3\r
+#define ICR45_ICR2 icr45.bit._ICR2\r
+#define ICR45_ICR1 icr45.bit._ICR1\r
+#define ICR45_ICR0 icr45.bit._ICR0\r
+__IO_EXTERN ICR46STR icr46;  \r
+#define ICR46 icr46.byte\r
+#define ICR46_ICR4 icr46.bit._ICR4\r
+#define ICR46_ICR3 icr46.bit._ICR3\r
+#define ICR46_ICR2 icr46.bit._ICR2\r
+#define ICR46_ICR1 icr46.bit._ICR1\r
+#define ICR46_ICR0 icr46.bit._ICR0\r
+__IO_EXTERN ICR47STR icr47;  \r
+#define ICR47 icr47.byte\r
+#define ICR47_ICR4 icr47.bit._ICR4\r
+#define ICR47_ICR3 icr47.bit._ICR3\r
+#define ICR47_ICR2 icr47.bit._ICR2\r
+#define ICR47_ICR1 icr47.bit._ICR1\r
+#define ICR47_ICR0 icr47.bit._ICR0\r
+__IO_EXTERN ICR48STR icr48;  \r
+#define ICR48 icr48.byte\r
+#define ICR48_ICR4 icr48.bit._ICR4\r
+#define ICR48_ICR3 icr48.bit._ICR3\r
+#define ICR48_ICR2 icr48.bit._ICR2\r
+#define ICR48_ICR1 icr48.bit._ICR1\r
+#define ICR48_ICR0 icr48.bit._ICR0\r
+__IO_EXTERN ICR49STR icr49;  \r
+#define ICR49 icr49.byte\r
+#define ICR49_ICR4 icr49.bit._ICR4\r
+#define ICR49_ICR3 icr49.bit._ICR3\r
+#define ICR49_ICR2 icr49.bit._ICR2\r
+#define ICR49_ICR1 icr49.bit._ICR1\r
+#define ICR49_ICR0 icr49.bit._ICR0\r
+__IO_EXTERN ICR50STR icr50;  \r
+#define ICR50 icr50.byte\r
+#define ICR50_ICR4 icr50.bit._ICR4\r
+#define ICR50_ICR3 icr50.bit._ICR3\r
+#define ICR50_ICR2 icr50.bit._ICR2\r
+#define ICR50_ICR1 icr50.bit._ICR1\r
+#define ICR50_ICR0 icr50.bit._ICR0\r
+__IO_EXTERN ICR51STR icr51;  \r
+#define ICR51 icr51.byte\r
+#define ICR51_ICR4 icr51.bit._ICR4\r
+#define ICR51_ICR3 icr51.bit._ICR3\r
+#define ICR51_ICR2 icr51.bit._ICR2\r
+#define ICR51_ICR1 icr51.bit._ICR1\r
+#define ICR51_ICR0 icr51.bit._ICR0\r
+__IO_EXTERN ICR52STR icr52;  \r
+#define ICR52 icr52.byte\r
+#define ICR52_ICR4 icr52.bit._ICR4\r
+#define ICR52_ICR3 icr52.bit._ICR3\r
+#define ICR52_ICR2 icr52.bit._ICR2\r
+#define ICR52_ICR1 icr52.bit._ICR1\r
+#define ICR52_ICR0 icr52.bit._ICR0\r
+__IO_EXTERN ICR53STR icr53;  \r
+#define ICR53 icr53.byte\r
+#define ICR53_ICR4 icr53.bit._ICR4\r
+#define ICR53_ICR3 icr53.bit._ICR3\r
+#define ICR53_ICR2 icr53.bit._ICR2\r
+#define ICR53_ICR1 icr53.bit._ICR1\r
+#define ICR53_ICR0 icr53.bit._ICR0\r
+__IO_EXTERN ICR54STR icr54;  \r
+#define ICR54 icr54.byte\r
+#define ICR54_ICR4 icr54.bit._ICR4\r
+#define ICR54_ICR3 icr54.bit._ICR3\r
+#define ICR54_ICR2 icr54.bit._ICR2\r
+#define ICR54_ICR1 icr54.bit._ICR1\r
+#define ICR54_ICR0 icr54.bit._ICR0\r
+__IO_EXTERN ICR55STR icr55;  \r
+#define ICR55 icr55.byte\r
+#define ICR55_ICR4 icr55.bit._ICR4\r
+#define ICR55_ICR3 icr55.bit._ICR3\r
+#define ICR55_ICR2 icr55.bit._ICR2\r
+#define ICR55_ICR1 icr55.bit._ICR1\r
+#define ICR55_ICR0 icr55.bit._ICR0\r
+__IO_EXTERN ICR56STR icr56;  \r
+#define ICR56 icr56.byte\r
+#define ICR56_ICR4 icr56.bit._ICR4\r
+#define ICR56_ICR3 icr56.bit._ICR3\r
+#define ICR56_ICR2 icr56.bit._ICR2\r
+#define ICR56_ICR1 icr56.bit._ICR1\r
+#define ICR56_ICR0 icr56.bit._ICR0\r
+__IO_EXTERN ICR57STR icr57;  \r
+#define ICR57 icr57.byte\r
+#define ICR57_ICR4 icr57.bit._ICR4\r
+#define ICR57_ICR3 icr57.bit._ICR3\r
+#define ICR57_ICR2 icr57.bit._ICR2\r
+#define ICR57_ICR1 icr57.bit._ICR1\r
+#define ICR57_ICR0 icr57.bit._ICR0\r
+__IO_EXTERN ICR58STR icr58;  \r
+#define ICR58 icr58.byte\r
+#define ICR58_ICR4 icr58.bit._ICR4\r
+#define ICR58_ICR3 icr58.bit._ICR3\r
+#define ICR58_ICR2 icr58.bit._ICR2\r
+#define ICR58_ICR1 icr58.bit._ICR1\r
+#define ICR58_ICR0 icr58.bit._ICR0\r
+__IO_EXTERN ICR59STR icr59;  \r
+#define ICR59 icr59.byte\r
+#define ICR59_ICR4 icr59.bit._ICR4\r
+#define ICR59_ICR3 icr59.bit._ICR3\r
+#define ICR59_ICR2 icr59.bit._ICR2\r
+#define ICR59_ICR1 icr59.bit._ICR1\r
+#define ICR59_ICR0 icr59.bit._ICR0\r
+__IO_EXTERN ICR60STR icr60;  \r
+#define ICR60 icr60.byte\r
+#define ICR60_ICR4 icr60.bit._ICR4\r
+#define ICR60_ICR3 icr60.bit._ICR3\r
+#define ICR60_ICR2 icr60.bit._ICR2\r
+#define ICR60_ICR1 icr60.bit._ICR1\r
+#define ICR60_ICR0 icr60.bit._ICR0\r
+__IO_EXTERN ICR61STR icr61;  \r
+#define ICR61 icr61.byte\r
+#define ICR61_ICR4 icr61.bit._ICR4\r
+#define ICR61_ICR3 icr61.bit._ICR3\r
+#define ICR61_ICR2 icr61.bit._ICR2\r
+#define ICR61_ICR1 icr61.bit._ICR1\r
+#define ICR61_ICR0 icr61.bit._ICR0\r
+__IO_EXTERN ICR62STR icr62;  \r
+#define ICR62 icr62.byte\r
+#define ICR62_ICR4 icr62.bit._ICR4\r
+#define ICR62_ICR3 icr62.bit._ICR3\r
+#define ICR62_ICR2 icr62.bit._ICR2\r
+#define ICR62_ICR1 icr62.bit._ICR1\r
+#define ICR62_ICR0 icr62.bit._ICR0\r
+__IO_EXTERN ICR63STR icr63;  \r
+#define ICR63 icr63.byte\r
+#define ICR63_ICR4 icr63.bit._ICR4\r
+#define ICR63_ICR3 icr63.bit._ICR3\r
+#define ICR63_ICR2 icr63.bit._ICR2\r
+#define ICR63_ICR1 icr63.bit._ICR1\r
+#define ICR63_ICR0 icr63.bit._ICR0\r
+__IO_EXTERN RSRRSTR rsrr;   /* Clock Control Unit */\r
+#define RSRR rsrr.byte\r
+#define RSRR_INIT rsrr.bit._INIT\r
+#define RSRR_HSTB rsrr.bit._HSTB\r
+#define RSRR_WDOG rsrr.bit._WDOG\r
+#define RSRR_ERST rsrr.bit._ERST\r
+#define RSRR_SRST rsrr.bit._SRST\r
+#define RSRR_LINIT rsrr.bit._LINIT\r
+#define RSRR_WT1 rsrr.bit._WT1\r
+#define RSRR_WT0 rsrr.bit._WT0\r
+#define RSRR_WT rsrr.bitc._WT\r
+__IO_EXTERN STCRSTR stcr;  \r
+#define STCR stcr.byte\r
+#define STCR_STOP stcr.bit._STOP\r
+#define STCR_SLEEP stcr.bit._SLEEP\r
+#define STCR_HIZ stcr.bit._HIZ\r
+#define STCR_SRST stcr.bit._SRST\r
+#define STCR_OS1 stcr.bit._OS1\r
+#define STCR_OS0 stcr.bit._OS0\r
+#define STCR_OSCD2 stcr.bit._OSCD2\r
+#define STCR_OSCD1 stcr.bit._OSCD1\r
+#define STCR_OS stcr.bitc._OS\r
+#define STCR_OSCD stcr.bitc._OSCD\r
+__IO_EXTERN TBCRSTR tbcr;  \r
+#define TBCR tbcr.byte\r
+#define TBCR_TBIF tbcr.bit._TBIF\r
+#define TBCR_TBIE tbcr.bit._TBIE\r
+#define TBCR_TBC2 tbcr.bit._TBC2\r
+#define TBCR_TBC1 tbcr.bit._TBC1\r
+#define TBCR_TBC0 tbcr.bit._TBC0\r
+#define TBCR_SYNCR tbcr.bit._SYNCR\r
+#define TBCR_SYNCS tbcr.bit._SYNCS\r
+#define TBCR_TBC tbcr.bitc._TBC\r
+__IO_EXTERN CTBRSTR ctbr;  \r
+#define CTBR ctbr.byte\r
+#define CTBR_D7 ctbr.bit._D7\r
+#define CTBR_D6 ctbr.bit._D6\r
+#define CTBR_D5 ctbr.bit._D5\r
+#define CTBR_D4 ctbr.bit._D4\r
+#define CTBR_D3 ctbr.bit._D3\r
+#define CTBR_D2 ctbr.bit._D2\r
+#define CTBR_D1 ctbr.bit._D1\r
+#define CTBR_D0 ctbr.bit._D0\r
+__IO_EXTERN CLKRSTR clkr;  \r
+#define CLKR clkr.byte\r
+#define CLKR_SCKEN clkr.bit._SCKEN\r
+#define CLKR_PLL1EN clkr.bit._PLL1EN\r
+#define CLKR_CLKS1 clkr.bit._CLKS1\r
+#define CLKR_CLKS0 clkr.bit._CLKS0\r
+#define CLKR_CLKS clkr.bitc._CLKS\r
+/* include : INC460_CLKR.INC */\r
+/*-------------------------------------------------------------------*/\r
+/* INC460.INC :  Old bit name of CLKR */\r
+\r
+/* alias macro definition for CLKR*/\r
+#define CLKR_PLL2EN clkr.bit._SCKEN\r
+/*-------------------------------------------------------------------*/\r
+__IO_EXTERN WPRSTR wpr;  \r
+#define WPR wpr.byte\r
+#define WPR_D7 wpr.bit._D7\r
+#define WPR_D6 wpr.bit._D6\r
+#define WPR_D5 wpr.bit._D5\r
+#define WPR_D4 wpr.bit._D4\r
+#define WPR_D3 wpr.bit._D3\r
+#define WPR_D2 wpr.bit._D2\r
+#define WPR_D1 wpr.bit._D1\r
+#define WPR_D0 wpr.bit._D0\r
+__IO_EXTERN DIVR0STR divr0;  \r
+#define DIVR0 divr0.byte\r
+#define DIVR0_B3 divr0.bit._B3\r
+#define DIVR0_B2 divr0.bit._B2\r
+#define DIVR0_B1 divr0.bit._B1\r
+#define DIVR0_B0 divr0.bit._B0\r
+#define DIVR0_P3 divr0.bit._P3\r
+#define DIVR0_P2 divr0.bit._P2\r
+#define DIVR0_P1 divr0.bit._P1\r
+#define DIVR0_P0 divr0.bit._P0\r
+#define DIVR0_B divr0.bitc._B\r
+#define DIVR0_P divr0.bitc._P\r
+__IO_EXTERN DIVR1STR divr1;  \r
+#define DIVR1 divr1.byte\r
+#define DIVR1_T3 divr1.bit._T3\r
+#define DIVR1_T2 divr1.bit._T2\r
+#define DIVR1_T1 divr1.bit._T1\r
+#define DIVR1_T0 divr1.bit._T0\r
+#define DIVR1_T divr1.bitc._T\r
+__IO_EXTERN PLLDIVMSTR plldivm;   /* PLL - Clock Gear Unit: */\r
+#define PLLDIVM plldivm.byte\r
+#define PLLDIVM_DVM3 plldivm.bit._DVM3\r
+#define PLLDIVM_DVM2 plldivm.bit._DVM2\r
+#define PLLDIVM_DVM1 plldivm.bit._DVM1\r
+#define PLLDIVM_DVM0 plldivm.bit._DVM0\r
+#define PLLDIVM_DVM plldivm.bitc._DVM\r
+__IO_EXTERN PLLDIVNSTR plldivn;  \r
+#define PLLDIVN plldivn.byte\r
+#define PLLDIVN_DVN5 plldivn.bit._DVN5\r
+#define PLLDIVN_DVN4 plldivn.bit._DVN4\r
+#define PLLDIVN_DVN3 plldivn.bit._DVN3\r
+#define PLLDIVN_DVN2 plldivn.bit._DVN2\r
+#define PLLDIVN_DVN1 plldivn.bit._DVN1\r
+#define PLLDIVN_DVN0 plldivn.bit._DVN0\r
+#define PLLDIVN_DVN plldivn.bitc._DVN\r
+__IO_EXTERN PLLDIVGSTR plldivg;  \r
+#define PLLDIVG plldivg.byte\r
+#define PLLDIVG_DVG3 plldivg.bit._DVG3\r
+#define PLLDIVG_DVG2 plldivg.bit._DVG2\r
+#define PLLDIVG_DVG1 plldivg.bit._DVG1\r
+#define PLLDIVG_DVG0 plldivg.bit._DVG0\r
+#define PLLDIVG_DVG plldivg.bitc._DVG\r
+__IO_EXTERN PLLMULGSTR pllmulg;  \r
+#define PLLMULG pllmulg.byte\r
+#define PLLMULG_MLG7 pllmulg.bit._MLG7\r
+#define PLLMULG_MLG6 pllmulg.bit._MLG6\r
+#define PLLMULG_MLG5 pllmulg.bit._MLG5\r
+#define PLLMULG_MLG4 pllmulg.bit._MLG4\r
+#define PLLMULG_MLG3 pllmulg.bit._MLG3\r
+#define PLLMULG_MLG2 pllmulg.bit._MLG2\r
+#define PLLMULG_MLG1 pllmulg.bit._MLG1\r
+#define PLLMULG_MLG0 pllmulg.bit._MLG0\r
+#define PLLMULG_MLG pllmulg.bitc._MLG\r
+__IO_EXTERN PLLCTRLSTR pllctrl;  \r
+#define PLLCTRL pllctrl.byte\r
+#define PLLCTRL_IEDN pllctrl.bit._IEDN\r
+#define PLLCTRL_GRDN pllctrl.bit._GRDN\r
+#define PLLCTRL_IEUP pllctrl.bit._IEUP\r
+#define PLLCTRL_GRUP pllctrl.bit._GRUP\r
+__IO_EXTERN OSCC1STR oscc1;   /* Main/Sub Oscillator Control */\r
+#define OSCC1 oscc1.byte\r
+#define OSCC1_FCI oscc1.bit._FCI\r
+#define OSCC1_RFBEN oscc1.bit._RFBEN\r
+#define OSCC1_OSCR oscc1.bit._OSCR\r
+__IO_EXTERN OSCS1STR oscs1;  \r
+#define OSCS1 oscs1.byte\r
+#define OSCS1_OSCS7 oscs1.bit._OSCS7\r
+#define OSCS1_OSCS6 oscs1.bit._OSCS6\r
+#define OSCS1_OSCS5 oscs1.bit._OSCS5\r
+#define OSCS1_OSCS4 oscs1.bit._OSCS4\r
+#define OSCS1_OSCS3 oscs1.bit._OSCS3\r
+#define OSCS1_OSCS2 oscs1.bit._OSCS2\r
+#define OSCS1_OSCS1 oscs1.bit._OSCS1\r
+#define OSCS1_OSCS0 oscs1.bit._OSCS0\r
+__IO_EXTERN OSCC2STR oscc2;  \r
+#define OSCC2 oscc2.byte\r
+#define OSCC2_FCI oscc2.bit._FCI\r
+#define OSCC2_RFBEN oscc2.bit._RFBEN\r
+#define OSCC2_OSCR oscc2.bit._OSCR\r
+__IO_EXTERN OSCS2STR oscs2;  \r
+#define OSCS2 oscs2.byte\r
+#define OSCS2_OSCS7 oscs2.bit._OSCS7\r
+#define OSCS2_OSCS6 oscs2.bit._OSCS6\r
+#define OSCS2_OSCS5 oscs2.bit._OSCS5\r
+#define OSCS2_OSCS4 oscs2.bit._OSCS4\r
+#define OSCS2_OSCS3 oscs2.bit._OSCS3\r
+#define OSCS2_OSCS2 oscs2.bit._OSCS2\r
+#define OSCS2_OSCS1 oscs2.bit._OSCS1\r
+#define OSCS2_OSCS0 oscs2.bit._OSCS0\r
+__IO_EXTERN PORTENSTR porten;   /* Port Input Enable Control */\r
+#define PORTEN porten.byte\r
+#define PORTEN_CPORTEN porten.bit._CPORTEN\r
+#define PORTEN_GPORTEN porten.bit._GPORTEN\r
+__IO_EXTERN WTCERSTR wtcer;   /* Real Time Clock (Watch Timer) */\r
+#define WTCER wtcer.byte\r
+#define WTCER_INTE4 wtcer.bit._INTE4\r
+#define WTCER_INT4 wtcer.bit._INT4\r
+__IO_EXTERN WTCRSTR wtcr;  \r
+#define WTCR wtcr.word\r
+#define WTCR_INTE3 wtcr.bit._INTE3\r
+#define WTCR_INT3 wtcr.bit._INT3\r
+#define WTCR_INTE2 wtcr.bit._INTE2\r
+#define WTCR_INT2 wtcr.bit._INT2\r
+#define WTCR_INTE1 wtcr.bit._INTE1\r
+#define WTCR_INT1 wtcr.bit._INT1\r
+#define WTCR_INTE0 wtcr.bit._INTE0\r
+#define WTCR_INT0 wtcr.bit._INT0\r
+#define WTCR_RUN wtcr.bit._RUN\r
+#define WTCR_UPDT wtcr.bit._UPDT\r
+#define WTCR_ST wtcr.bit._ST\r
+__IO_EXTERN WTBRSTR wtbr;  \r
+#define WTBR wtbr.lword\r
+#define WTBR_D20 wtbr.bit._D20\r
+#define WTBR_D19 wtbr.bit._D19\r
+#define WTBR_D18 wtbr.bit._D18\r
+#define WTBR_D17 wtbr.bit._D17\r
+#define WTBR_D16 wtbr.bit._D16\r
+#define WTBR_D15 wtbr.bit._D15\r
+#define WTBR_D14 wtbr.bit._D14\r
+#define WTBR_D13 wtbr.bit._D13\r
+#define WTBR_D12 wtbr.bit._D12\r
+#define WTBR_D11 wtbr.bit._D11\r
+#define WTBR_D10 wtbr.bit._D10\r
+#define WTBR_D9 wtbr.bit._D9\r
+#define WTBR_D8 wtbr.bit._D8\r
+#define WTBR_D7 wtbr.bit._D7\r
+#define WTBR_D6 wtbr.bit._D6\r
+#define WTBR_D5 wtbr.bit._D5\r
+#define WTBR_D4 wtbr.bit._D4\r
+#define WTBR_D3 wtbr.bit._D3\r
+#define WTBR_D2 wtbr.bit._D2\r
+#define WTBR_D1 wtbr.bit._D1\r
+#define WTBR_D0 wtbr.bit._D0\r
+__IO_EXTERN WTHRSTR wthr;  \r
+#define WTHR wthr.byte\r
+#define WTHR_H4 wthr.bit._H4\r
+#define WTHR_H3 wthr.bit._H3\r
+#define WTHR_H2 wthr.bit._H2\r
+#define WTHR_H1 wthr.bit._H1\r
+#define WTHR_H0 wthr.bit._H0\r
+__IO_EXTERN WTMRSTR wtmr;  \r
+#define WTMR wtmr.byte\r
+#define WTMR_M5 wtmr.bit._M5\r
+#define WTMR_M4 wtmr.bit._M4\r
+#define WTMR_M3 wtmr.bit._M3\r
+#define WTMR_M2 wtmr.bit._M2\r
+#define WTMR_M1 wtmr.bit._M1\r
+#define WTMR_M0 wtmr.bit._M0\r
+__IO_EXTERN WTSRSTR wtsr;  \r
+#define WTSR wtsr.byte\r
+#define WTSR_S5 wtsr.bit._S5\r
+#define WTSR_S4 wtsr.bit._S4\r
+#define WTSR_S3 wtsr.bit._S3\r
+#define WTSR_S2 wtsr.bit._S2\r
+#define WTSR_S1 wtsr.bit._S1\r
+#define WTSR_S0 wtsr.bit._S0\r
+__IO_EXTERN IO_BYTE csvtr;   /* Clock-Supervisor / Selecor / Monitor */\r
+#define CSVTR csvtr\r
+__IO_EXTERN CSVCRSTR csvcr;  \r
+#define CSVCR csvcr.byte\r
+#define CSVCR_SCKS csvcr.bit._SCKS\r
+#define CSVCR_MM csvcr.bit._MM\r
+#define CSVCR_SM csvcr.bit._SM\r
+#define CSVCR_RCE csvcr.bit._RCE\r
+#define CSVCR_MSVE csvcr.bit._MSVE\r
+#define CSVCR_SSVE csvcr.bit._SSVE\r
+#define CSVCR_SRST csvcr.bit._SRST\r
+#define CSVCR_OUTE csvcr.bit._OUTE\r
+__IO_EXTERN CSCFGSTR cscfg;  \r
+#define CSCFG cscfg.byte\r
+#define CSCFG_EDSUEN cscfg.bit._EDSUEN\r
+#define CSCFG_PLLLOCK cscfg.bit._PLLLOCK\r
+#define CSCFG_RCSEL cscfg.bit._RCSEL\r
+#define CSCFG_MONCKI cscfg.bit._MONCKI\r
+#define CSCFG_CSC3 cscfg.bit._CSC3\r
+#define CSCFG_CSC2 cscfg.bit._CSC2\r
+#define CSCFG_CSC1 cscfg.bit._CSC1\r
+#define CSCFG_CSC0 cscfg.bit._CSC0\r
+#define CSCFG_CSC cscfg.bitc._CSC\r
+__IO_EXTERN CMCFGSTR cmcfg;  \r
+#define CMCFG cmcfg.byte\r
+#define CMCFG_CMPRE3 cmcfg.bit._CMPRE3\r
+#define CMCFG_CMPRE2 cmcfg.bit._CMPRE2\r
+#define CMCFG_CMPRE1 cmcfg.bit._CMPRE1\r
+#define CMCFG_CMPRE0 cmcfg.bit._CMPRE0\r
+#define CMCFG_CMSEL3 cmcfg.bit._CMSEL3\r
+#define CMCFG_CMSEL2 cmcfg.bit._CMSEL2\r
+#define CMCFG_CMSEL1 cmcfg.bit._CMSEL1\r
+#define CMCFG_CMSEL0 cmcfg.bit._CMSEL0\r
+#define CMCFG_CMPRE cmcfg.bitc._CMPRE\r
+#define CMCFG_CMSEL cmcfg.bitc._CMSEL\r
+/* include : INC460_CSV.INC */\r
+/*-------------------------------------------------------------------*/\r
+/* INC460.DMAC :  Old bit name of CSV */\r
+ \r
+/* alias macro definition for CSV */\r
+#define CSVCR_MS csvcr.bit._SM\r
+#define CSVCR_REC csvcr.bit._RCE\r
+/*-------------------------------------------------------------------*/\r
+__IO_EXTERN CUCRSTR cucr;   /* Calibration Unit of Sub Oszillation */\r
+#define CUCR cucr.word\r
+#define CUCR_STRT cucr.bit._STRT\r
+#define CUCR_INT cucr.bit._INT\r
+#define CUCR_INTEN cucr.bit._INTEN\r
+__IO_EXTERN CUTDSTR cutd;  \r
+#define CUTD cutd.word\r
+#define CUTD_TDD15 cutd.bit._TDD15\r
+#define CUTD_TDD14 cutd.bit._TDD14\r
+#define CUTD_TDD13 cutd.bit._TDD13\r
+#define CUTD_TDD12 cutd.bit._TDD12\r
+#define CUTD_TDD11 cutd.bit._TDD11\r
+#define CUTD_TDD10 cutd.bit._TDD10\r
+#define CUTD_TDD9 cutd.bit._TDD9\r
+#define CUTD_TDD8 cutd.bit._TDD8\r
+#define CUTD_TDD7 cutd.bit._TDD7\r
+#define CUTD_TDD6 cutd.bit._TDD6\r
+#define CUTD_TDD5 cutd.bit._TDD5\r
+#define CUTD_TDD4 cutd.bit._TDD4\r
+#define CUTD_TDD3 cutd.bit._TDD3\r
+#define CUTD_TDD2 cutd.bit._TDD2\r
+#define CUTD_TDD1 cutd.bit._TDD1\r
+#define CUTD_TDD0 cutd.bit._TDD0\r
+__IO_EXTERN CUTR1STR cutr1;  \r
+#define CUTR1 cutr1.word\r
+#define CUTR1_TDR23 cutr1.bit._TDR23\r
+#define CUTR1_TDR22 cutr1.bit._TDR22\r
+#define CUTR1_TDR21 cutr1.bit._TDR21\r
+#define CUTR1_TDR20 cutr1.bit._TDR20\r
+#define CUTR1_TDR19 cutr1.bit._TDR19\r
+#define CUTR1_TDR18 cutr1.bit._TDR18\r
+#define CUTR1_TDR17 cutr1.bit._TDR17\r
+#define CUTR1_TDR16 cutr1.bit._TDR16\r
+__IO_EXTERN CUTR2STR cutr2;  \r
+#define CUTR2 cutr2.word\r
+#define CUTR2_TDR15 cutr2.bit._TDR15\r
+#define CUTR2_TDR14 cutr2.bit._TDR14\r
+#define CUTR2_TDR13 cutr2.bit._TDR13\r
+#define CUTR2_TDR12 cutr2.bit._TDR12\r
+#define CUTR2_TDR11 cutr2.bit._TDR11\r
+#define CUTR2_TDR10 cutr2.bit._TDR10\r
+#define CUTR2_TDR9 cutr2.bit._TDR9\r
+#define CUTR2_TDR8 cutr2.bit._TDR8\r
+#define CUTR2_TDR7 cutr2.bit._TDR7\r
+#define CUTR2_TDR6 cutr2.bit._TDR6\r
+#define CUTR2_TDR5 cutr2.bit._TDR5\r
+#define CUTR2_TDR4 cutr2.bit._TDR4\r
+#define CUTR2_TDR3 cutr2.bit._TDR3\r
+#define CUTR2_TDR2 cutr2.bit._TDR2\r
+#define CUTR2_TDR1 cutr2.bit._TDR1\r
+#define CUTR2_TDR0 cutr2.bit._TDR0\r
+__IO_EXTERN CMPRSTR cmpr;   /* Clock Modulator */\r
+#define CMPR cmpr.word\r
+#define CMPR_MP13 cmpr.bit._MP13\r
+#define CMPR_MP12 cmpr.bit._MP12\r
+#define CMPR_MP11 cmpr.bit._MP11\r
+#define CMPR_MP10 cmpr.bit._MP10\r
+#define CMPR_MP9 cmpr.bit._MP9\r
+#define CMPR_MP8 cmpr.bit._MP8\r
+#define CMPR_MP7 cmpr.bit._MP7\r
+#define CMPR_MP6 cmpr.bit._MP6\r
+#define CMPR_MP5 cmpr.bit._MP5\r
+#define CMPR_MP4 cmpr.bit._MP4\r
+#define CMPR_MP3 cmpr.bit._MP3\r
+#define CMPR_MP2 cmpr.bit._MP2\r
+#define CMPR_MP1 cmpr.bit._MP1\r
+#define CMPR_MP0 cmpr.bit._MP0\r
+__IO_EXTERN CMCRSTR cmcr;  \r
+#define CMCR cmcr.byte\r
+#define CMCR_FMODRUN cmcr.bit._FMODRUN\r
+#define CMCR_FMOD cmcr.bit._FMOD\r
+#define CMCR_PDX cmcr.bit._PDX\r
+__IO_EXTERN IO_WORD cmt1;  \r
+#define CMT1 cmt1\r
+__IO_EXTERN IO_WORD cmt2;  \r
+#define CMT2 cmt2\r
+__IO_EXTERN CANPRESTR canpre;   /* CAN clock control */\r
+#define CANPRE canpre.byte\r
+#define CANPRE_CPCKS1 canpre.bit._CPCKS1\r
+#define CANPRE_CPCKS0 canpre.bit._CPCKS0\r
+#define CANPRE_DVC3 canpre.bit._DVC3\r
+#define CANPRE_DVC2 canpre.bit._DVC2\r
+#define CANPRE_DVC1 canpre.bit._DVC1\r
+#define CANPRE_DVC0 canpre.bit._DVC0\r
+#define CANPRE_CPCKS canpre.bitc._CPCKS\r
+#define CANPRE_DVC canpre.bitc._DVC\r
+__IO_EXTERN CANCKDSTR canckd;  \r
+#define CANCKD canckd.byte\r
+#define CANCKD_CANCKD5 canckd.bit._CANCKD5\r
+#define CANCKD_CANCKD4 canckd.bit._CANCKD4\r
+#define CANCKD_CANCKD3 canckd.bit._CANCKD3\r
+#define CANCKD_CANCKD2 canckd.bit._CANCKD2\r
+#define CANCKD_CANCKD1 canckd.bit._CANCKD1\r
+#define CANCKD_CANCKD0 canckd.bit._CANCKD0\r
+__IO_EXTERN LVSELSTR lvsel;   /* LV Detection / Hardware-Watchdog */\r
+#define LVSEL lvsel.byte\r
+#define LVSEL_LVESEL3 lvsel.bit._LVESEL3\r
+#define LVSEL_LVESEL2 lvsel.bit._LVESEL2\r
+#define LVSEL_LVESEL1 lvsel.bit._LVESEL1\r
+#define LVSEL_LVESEL0 lvsel.bit._LVESEL0\r
+#define LVSEL_LVISEL3 lvsel.bit._LVISEL3\r
+#define LVSEL_LVISEL2 lvsel.bit._LVISEL2\r
+#define LVSEL_LVISEL1 lvsel.bit._LVISEL1\r
+#define LVSEL_LVISEL0 lvsel.bit._LVISEL0\r
+#define LVSEL_LVESEL lvsel.bitc._LVESEL\r
+#define LVSEL_LVISEL lvsel.bitc._LVISEL\r
+__IO_EXTERN LVDETSTR lvdet;  \r
+#define LVDET lvdet.byte\r
+#define LVDET_LVSEL lvdet.bit._LVSEL\r
+#define LVDET_LVEPD lvdet.bit._LVEPD\r
+#define LVDET_LVIPD lvdet.bit._LVIPD\r
+#define LVDET_LVREN lvdet.bit._LVREN\r
+#define LVDET_LVIEN lvdet.bit._LVIEN\r
+#define LVDET_LVIRQ lvdet.bit._LVIRQ\r
+__IO_EXTERN HWWDESTR hwwde;  \r
+#define HWWDE hwwde.byte\r
+#define HWWDE_ED1 hwwde.bit._ED1\r
+#define HWWDE_ED0 hwwde.bit._ED0\r
+#define HWWDE_ED hwwde.bitc._ED\r
+__IO_EXTERN HWWDSTR hwwd;  \r
+#define HWWD hwwd.byte\r
+#define HWWD_CL hwwd.bit._CL\r
+#define HWWD_CPUF hwwd.bit._CPUF\r
+__IO_EXTERN OSCRHSTR oscrh;   /* Main-/Sub-Oscillatio Stabilization Timer */\r
+#define OSCRH oscrh.byte\r
+#define OSCRH_WIF oscrh.bit._WIF\r
+#define OSCRH_WIE oscrh.bit._WIE\r
+#define OSCRH_WEN oscrh.bit._WEN\r
+#define OSCRH_WS1 oscrh.bit._WS1\r
+#define OSCRH_WS0 oscrh.bit._WS0\r
+#define OSCRH_WCL oscrh.bit._WCL\r
+#define OSCRH_WS oscrh.bitc._WS\r
+__IO_EXTERN IO_BYTE oscrl;  \r
+#define OSCRL oscrl\r
+__IO_EXTERN WPCRHSTR wpcrh;  \r
+#define WPCRH wpcrh.byte\r
+#define WPCRH_WIF wpcrh.bit._WIF\r
+#define WPCRH_WIE wpcrh.bit._WIE\r
+#define WPCRH_WEN wpcrh.bit._WEN\r
+#define WPCRH_WS1 wpcrh.bit._WS1\r
+#define WPCRH_WS0 wpcrh.bit._WS0\r
+#define WPCRH_WCL wpcrh.bit._WCL\r
+#define WPCRH_WS wpcrh.bitc._WS\r
+__IO_EXTERN IO_BYTE wpcrl;  \r
+#define WPCRL wpcrl\r
+__IO_EXTERN OSCCRSTR osccr;   /* Main-/Sub-Oscillatio Standby Control */\r
+#define OSCCR osccr.byte\r
+#define OSCCR_OSCDS1 osccr.bit._OSCDS1\r
+__IO_EXTERN REGSELSTR regsel;  \r
+#define REGSEL regsel.byte\r
+#define REGSEL_FLASHSEL regsel.bit._FLASHSEL\r
+#define REGSEL_MAINSEL regsel.bit._MAINSEL\r
+#define REGSEL_SUBSEL3 regsel.bit._SUBSEL3\r
+#define REGSEL_SUBSEL2 regsel.bit._SUBSEL2\r
+#define REGSEL_SUBSEL1 regsel.bit._SUBSEL1\r
+#define REGSEL_SUBSEL0 regsel.bit._SUBSEL0\r
+#define REGSEL_SUBSEL regsel.bitc._SUBSEL\r
+__IO_EXTERN REGCTRSTR regctr;  \r
+#define REGCTR regctr.byte\r
+#define REGCTR_MSTBO regctr.bit._MSTBO\r
+#define REGCTR_MAINKPEN regctr.bit._MAINKPEN\r
+#define REGCTR_MAINDSBL regctr.bit._MAINDSBL\r
+__IO_EXTERN ASR0STR asr0;   /* External Bus/Chip Select Registers */\r
+#define ASR0 asr0.word\r
+#define ASR0_A31 asr0.bit._A31\r
+#define ASR0_A30 asr0.bit._A30\r
+#define ASR0_A29 asr0.bit._A29\r
+#define ASR0_A28 asr0.bit._A28\r
+#define ASR0_A27 asr0.bit._A27\r
+#define ASR0_A26 asr0.bit._A26\r
+#define ASR0_A25 asr0.bit._A25\r
+#define ASR0_A24 asr0.bit._A24\r
+#define ASR0_A23 asr0.bit._A23\r
+#define ASR0_A22 asr0.bit._A22\r
+#define ASR0_A21 asr0.bit._A21\r
+#define ASR0_A20 asr0.bit._A20\r
+#define ASR0_A19 asr0.bit._A19\r
+#define ASR0_A18 asr0.bit._A18\r
+#define ASR0_A17 asr0.bit._A17\r
+#define ASR0_A16 asr0.bit._A16\r
+__IO_EXTERN ACR0STR acr0;  \r
+#define ACR0 acr0.word\r
+#define ACR0_ASZ3 acr0.bit._ASZ3\r
+#define ACR0_ASZ2 acr0.bit._ASZ2\r
+#define ACR0_ASZ1 acr0.bit._ASZ1\r
+#define ACR0_ASZ0 acr0.bit._ASZ0\r
+#define ACR0_DBW1 acr0.bit._DBW1\r
+#define ACR0_DBW0 acr0.bit._DBW0\r
+#define ACR0_BST1 acr0.bit._BST1\r
+#define ACR0_BST0 acr0.bit._BST0\r
+#define ACR0_SREN acr0.bit._SREN\r
+#define ACR0_PFEN acr0.bit._PFEN\r
+#define ACR0_WREN acr0.bit._WREN\r
+#define ACR0_TYP3 acr0.bit._TYP3\r
+#define ACR0_TYP2 acr0.bit._TYP2\r
+#define ACR0_TYP1 acr0.bit._TYP1\r
+#define ACR0_TYP0 acr0.bit._TYP0\r
+#define ACR0_ASZ acr0.bitc._ASZ\r
+#define ACR0_DBW acr0.bitc._DBW\r
+#define ACR0_BST acr0.bitc._BST\r
+#define ACR0_TYP acr0.bitc._TYP\r
+__IO_EXTERN ASR1STR asr1;  \r
+#define ASR1 asr1.word\r
+#define ASR1_A31 asr1.bit._A31\r
+#define ASR1_A30 asr1.bit._A30\r
+#define ASR1_A29 asr1.bit._A29\r
+#define ASR1_A28 asr1.bit._A28\r
+#define ASR1_A27 asr1.bit._A27\r
+#define ASR1_A26 asr1.bit._A26\r
+#define ASR1_A25 asr1.bit._A25\r
+#define ASR1_A24 asr1.bit._A24\r
+#define ASR1_A23 asr1.bit._A23\r
+#define ASR1_A22 asr1.bit._A22\r
+#define ASR1_A21 asr1.bit._A21\r
+#define ASR1_A20 asr1.bit._A20\r
+#define ASR1_A19 asr1.bit._A19\r
+#define ASR1_A18 asr1.bit._A18\r
+#define ASR1_A17 asr1.bit._A17\r
+#define ASR1_A16 asr1.bit._A16\r
+__IO_EXTERN ACR1STR acr1;  \r
+#define ACR1 acr1.word\r
+#define ACR1_ASZ3 acr1.bit._ASZ3\r
+#define ACR1_ASZ2 acr1.bit._ASZ2\r
+#define ACR1_ASZ1 acr1.bit._ASZ1\r
+#define ACR1_ASZ0 acr1.bit._ASZ0\r
+#define ACR1_DBW1 acr1.bit._DBW1\r
+#define ACR1_DBW0 acr1.bit._DBW0\r
+#define ACR1_BST1 acr1.bit._BST1\r
+#define ACR1_BST0 acr1.bit._BST0\r
+#define ACR1_SREN acr1.bit._SREN\r
+#define ACR1_PFEN acr1.bit._PFEN\r
+#define ACR1_WREN acr1.bit._WREN\r
+#define ACR1_LEND acr1.bit._LEND\r
+#define ACR1_TYP3 acr1.bit._TYP3\r
+#define ACR1_TYP2 acr1.bit._TYP2\r
+#define ACR1_TYP1 acr1.bit._TYP1\r
+#define ACR1_TYP0 acr1.bit._TYP0\r
+#define ACR1_ASZ acr1.bitc._ASZ\r
+#define ACR1_DBW acr1.bitc._DBW\r
+#define ACR1_BST acr1.bitc._BST\r
+#define ACR1_TYP acr1.bitc._TYP\r
+__IO_EXTERN ASR2STR asr2;  \r
+#define ASR2 asr2.word\r
+#define ASR2_A31 asr2.bit._A31\r
+#define ASR2_A30 asr2.bit._A30\r
+#define ASR2_A29 asr2.bit._A29\r
+#define ASR2_A28 asr2.bit._A28\r
+#define ASR2_A27 asr2.bit._A27\r
+#define ASR2_A26 asr2.bit._A26\r
+#define ASR2_A25 asr2.bit._A25\r
+#define ASR2_A24 asr2.bit._A24\r
+#define ASR2_A23 asr2.bit._A23\r
+#define ASR2_A22 asr2.bit._A22\r
+#define ASR2_A21 asr2.bit._A21\r
+#define ASR2_A20 asr2.bit._A20\r
+#define ASR2_A19 asr2.bit._A19\r
+#define ASR2_A18 asr2.bit._A18\r
+#define ASR2_A17 asr2.bit._A17\r
+#define ASR2_A16 asr2.bit._A16\r
+__IO_EXTERN ACR2STR acr2;  \r
+#define ACR2 acr2.word\r
+#define ACR2_ASZ3 acr2.bit._ASZ3\r
+#define ACR2_ASZ2 acr2.bit._ASZ2\r
+#define ACR2_ASZ1 acr2.bit._ASZ1\r
+#define ACR2_ASZ0 acr2.bit._ASZ0\r
+#define ACR2_DBW1 acr2.bit._DBW1\r
+#define ACR2_DBW0 acr2.bit._DBW0\r
+#define ACR2_BST1 acr2.bit._BST1\r
+#define ACR2_BST0 acr2.bit._BST0\r
+#define ACR2_SREN acr2.bit._SREN\r
+#define ACR2_PFEN acr2.bit._PFEN\r
+#define ACR2_WREN acr2.bit._WREN\r
+#define ACR2_LEND acr2.bit._LEND\r
+#define ACR2_TYP3 acr2.bit._TYP3\r
+#define ACR2_TYP2 acr2.bit._TYP2\r
+#define ACR2_TYP1 acr2.bit._TYP1\r
+#define ACR2_TYP0 acr2.bit._TYP0\r
+#define ACR2_ASZ acr2.bitc._ASZ\r
+#define ACR2_DBW acr2.bitc._DBW\r
+#define ACR2_BST acr2.bitc._BST\r
+#define ACR2_TYP acr2.bitc._TYP\r
+__IO_EXTERN ASR3STR asr3;  \r
+#define ASR3 asr3.word\r
+#define ASR3_A31 asr3.bit._A31\r
+#define ASR3_A30 asr3.bit._A30\r
+#define ASR3_A29 asr3.bit._A29\r
+#define ASR3_A28 asr3.bit._A28\r
+#define ASR3_A27 asr3.bit._A27\r
+#define ASR3_A26 asr3.bit._A26\r
+#define ASR3_A25 asr3.bit._A25\r
+#define ASR3_A24 asr3.bit._A24\r
+#define ASR3_A23 asr3.bit._A23\r
+#define ASR3_A22 asr3.bit._A22\r
+#define ASR3_A21 asr3.bit._A21\r
+#define ASR3_A20 asr3.bit._A20\r
+#define ASR3_A19 asr3.bit._A19\r
+#define ASR3_A18 asr3.bit._A18\r
+#define ASR3_A17 asr3.bit._A17\r
+#define ASR3_A16 asr3.bit._A16\r
+__IO_EXTERN ACR3STR acr3;  \r
+#define ACR3 acr3.word\r
+#define ACR3_ASZ3 acr3.bit._ASZ3\r
+#define ACR3_ASZ2 acr3.bit._ASZ2\r
+#define ACR3_ASZ1 acr3.bit._ASZ1\r
+#define ACR3_ASZ0 acr3.bit._ASZ0\r
+#define ACR3_DBW1 acr3.bit._DBW1\r
+#define ACR3_DBW0 acr3.bit._DBW0\r
+#define ACR3_BST1 acr3.bit._BST1\r
+#define ACR3_BST0 acr3.bit._BST0\r
+#define ACR3_SREN acr3.bit._SREN\r
+#define ACR3_PFEN acr3.bit._PFEN\r
+#define ACR3_WREN acr3.bit._WREN\r
+#define ACR3_LEND acr3.bit._LEND\r
+#define ACR3_TYP3 acr3.bit._TYP3\r
+#define ACR3_TYP2 acr3.bit._TYP2\r
+#define ACR3_TYP1 acr3.bit._TYP1\r
+#define ACR3_TYP0 acr3.bit._TYP0\r
+#define ACR3_ASZ acr3.bitc._ASZ\r
+#define ACR3_DBW acr3.bitc._DBW\r
+#define ACR3_BST acr3.bitc._BST\r
+#define ACR3_TYP acr3.bitc._TYP\r
+__IO_EXTERN ASR4STR asr4;  \r
+#define ASR4 asr4.word\r
+#define ASR4_A31 asr4.bit._A31\r
+#define ASR4_A30 asr4.bit._A30\r
+#define ASR4_A29 asr4.bit._A29\r
+#define ASR4_A28 asr4.bit._A28\r
+#define ASR4_A27 asr4.bit._A27\r
+#define ASR4_A26 asr4.bit._A26\r
+#define ASR4_A25 asr4.bit._A25\r
+#define ASR4_A24 asr4.bit._A24\r
+#define ASR4_A23 asr4.bit._A23\r
+#define ASR4_A22 asr4.bit._A22\r
+#define ASR4_A21 asr4.bit._A21\r
+#define ASR4_A20 asr4.bit._A20\r
+#define ASR4_A19 asr4.bit._A19\r
+#define ASR4_A18 asr4.bit._A18\r
+#define ASR4_A17 asr4.bit._A17\r
+#define ASR4_A16 asr4.bit._A16\r
+__IO_EXTERN ACR4STR acr4;  \r
+#define ACR4 acr4.word\r
+#define ACR4_ASZ3 acr4.bit._ASZ3\r
+#define ACR4_ASZ2 acr4.bit._ASZ2\r
+#define ACR4_ASZ1 acr4.bit._ASZ1\r
+#define ACR4_ASZ0 acr4.bit._ASZ0\r
+#define ACR4_DBW1 acr4.bit._DBW1\r
+#define ACR4_DBW0 acr4.bit._DBW0\r
+#define ACR4_BST1 acr4.bit._BST1\r
+#define ACR4_BST0 acr4.bit._BST0\r
+#define ACR4_SREN acr4.bit._SREN\r
+#define ACR4_PFEN acr4.bit._PFEN\r
+#define ACR4_WREN acr4.bit._WREN\r
+#define ACR4_LEND acr4.bit._LEND\r
+#define ACR4_TYP3 acr4.bit._TYP3\r
+#define ACR4_TYP2 acr4.bit._TYP2\r
+#define ACR4_TYP1 acr4.bit._TYP1\r
+#define ACR4_TYP0 acr4.bit._TYP0\r
+#define ACR4_ASZ acr4.bitc._ASZ\r
+#define ACR4_DBW acr4.bitc._DBW\r
+#define ACR4_BST acr4.bitc._BST\r
+#define ACR4_TYP acr4.bitc._TYP\r
+__IO_EXTERN ASR5STR asr5;  \r
+#define ASR5 asr5.word\r
+#define ASR5_A31 asr5.bit._A31\r
+#define ASR5_A30 asr5.bit._A30\r
+#define ASR5_A29 asr5.bit._A29\r
+#define ASR5_A28 asr5.bit._A28\r
+#define ASR5_A27 asr5.bit._A27\r
+#define ASR5_A26 asr5.bit._A26\r
+#define ASR5_A25 asr5.bit._A25\r
+#define ASR5_A24 asr5.bit._A24\r
+#define ASR5_A23 asr5.bit._A23\r
+#define ASR5_A22 asr5.bit._A22\r
+#define ASR5_A21 asr5.bit._A21\r
+#define ASR5_A20 asr5.bit._A20\r
+#define ASR5_A19 asr5.bit._A19\r
+#define ASR5_A18 asr5.bit._A18\r
+#define ASR5_A17 asr5.bit._A17\r
+#define ASR5_A16 asr5.bit._A16\r
+__IO_EXTERN ACR5STR acr5;  \r
+#define ACR5 acr5.word\r
+#define ACR5_ASZ3 acr5.bit._ASZ3\r
+#define ACR5_ASZ2 acr5.bit._ASZ2\r
+#define ACR5_ASZ1 acr5.bit._ASZ1\r
+#define ACR5_ASZ0 acr5.bit._ASZ0\r
+#define ACR5_DBW1 acr5.bit._DBW1\r
+#define ACR5_DBW0 acr5.bit._DBW0\r
+#define ACR5_BST1 acr5.bit._BST1\r
+#define ACR5_BST0 acr5.bit._BST0\r
+#define ACR5_SREN acr5.bit._SREN\r
+#define ACR5_PFEN acr5.bit._PFEN\r
+#define ACR5_WREN acr5.bit._WREN\r
+#define ACR5_LEND acr5.bit._LEND\r
+#define ACR5_TYP3 acr5.bit._TYP3\r
+#define ACR5_TYP2 acr5.bit._TYP2\r
+#define ACR5_TYP1 acr5.bit._TYP1\r
+#define ACR5_TYP0 acr5.bit._TYP0\r
+#define ACR5_ASZ acr5.bitc._ASZ\r
+#define ACR5_DBW acr5.bitc._DBW\r
+#define ACR5_BST acr5.bitc._BST\r
+#define ACR5_TYP acr5.bitc._TYP\r
+__IO_EXTERN ASR6STR asr6;  \r
+#define ASR6 asr6.word\r
+#define ASR6_A31 asr6.bit._A31\r
+#define ASR6_A30 asr6.bit._A30\r
+#define ASR6_A29 asr6.bit._A29\r
+#define ASR6_A28 asr6.bit._A28\r
+#define ASR6_A27 asr6.bit._A27\r
+#define ASR6_A26 asr6.bit._A26\r
+#define ASR6_A25 asr6.bit._A25\r
+#define ASR6_A24 asr6.bit._A24\r
+#define ASR6_A23 asr6.bit._A23\r
+#define ASR6_A22 asr6.bit._A22\r
+#define ASR6_A21 asr6.bit._A21\r
+#define ASR6_A20 asr6.bit._A20\r
+#define ASR6_A19 asr6.bit._A19\r
+#define ASR6_A18 asr6.bit._A18\r
+#define ASR6_A17 asr6.bit._A17\r
+#define ASR6_A16 asr6.bit._A16\r
+__IO_EXTERN ACR6STR acr6;  \r
+#define ACR6 acr6.word\r
+#define ACR6_ASZ3 acr6.bit._ASZ3\r
+#define ACR6_ASZ2 acr6.bit._ASZ2\r
+#define ACR6_ASZ1 acr6.bit._ASZ1\r
+#define ACR6_ASZ0 acr6.bit._ASZ0\r
+#define ACR6_DBW1 acr6.bit._DBW1\r
+#define ACR6_DBW0 acr6.bit._DBW0\r
+#define ACR6_BST1 acr6.bit._BST1\r
+#define ACR6_BST0 acr6.bit._BST0\r
+#define ACR6_SREN acr6.bit._SREN\r
+#define ACR6_PFEN acr6.bit._PFEN\r
+#define ACR6_WREN acr6.bit._WREN\r
+#define ACR6_LEND acr6.bit._LEND\r
+#define ACR6_TYP3 acr6.bit._TYP3\r
+#define ACR6_TYP2 acr6.bit._TYP2\r
+#define ACR6_TYP1 acr6.bit._TYP1\r
+#define ACR6_TYP0 acr6.bit._TYP0\r
+#define ACR6_ASZ acr6.bitc._ASZ\r
+#define ACR6_DBW acr6.bitc._DBW\r
+#define ACR6_BST acr6.bitc._BST\r
+#define ACR6_TYP acr6.bitc._TYP\r
+__IO_EXTERN ASR7STR asr7;  \r
+#define ASR7 asr7.word\r
+#define ASR7_A31 asr7.bit._A31\r
+#define ASR7_A30 asr7.bit._A30\r
+#define ASR7_A29 asr7.bit._A29\r
+#define ASR7_A28 asr7.bit._A28\r
+#define ASR7_A27 asr7.bit._A27\r
+#define ASR7_A26 asr7.bit._A26\r
+#define ASR7_A25 asr7.bit._A25\r
+#define ASR7_A24 asr7.bit._A24\r
+#define ASR7_A23 asr7.bit._A23\r
+#define ASR7_A22 asr7.bit._A22\r
+#define ASR7_A21 asr7.bit._A21\r
+#define ASR7_A20 asr7.bit._A20\r
+#define ASR7_A19 asr7.bit._A19\r
+#define ASR7_A18 asr7.bit._A18\r
+#define ASR7_A17 asr7.bit._A17\r
+#define ASR7_A16 asr7.bit._A16\r
+__IO_EXTERN ACR7STR acr7;  \r
+#define ACR7 acr7.word\r
+#define ACR7_ASZ3 acr7.bit._ASZ3\r
+#define ACR7_ASZ2 acr7.bit._ASZ2\r
+#define ACR7_ASZ1 acr7.bit._ASZ1\r
+#define ACR7_ASZ0 acr7.bit._ASZ0\r
+#define ACR7_DBW1 acr7.bit._DBW1\r
+#define ACR7_DBW0 acr7.bit._DBW0\r
+#define ACR7_BST1 acr7.bit._BST1\r
+#define ACR7_BST0 acr7.bit._BST0\r
+#define ACR7_SREN acr7.bit._SREN\r
+#define ACR7_PFEN acr7.bit._PFEN\r
+#define ACR7_WREN acr7.bit._WREN\r
+#define ACR7_LEND acr7.bit._LEND\r
+#define ACR7_TYP3 acr7.bit._TYP3\r
+#define ACR7_TYP2 acr7.bit._TYP2\r
+#define ACR7_TYP1 acr7.bit._TYP1\r
+#define ACR7_TYP0 acr7.bit._TYP0\r
+#define ACR7_ASZ acr7.bitc._ASZ\r
+#define ACR7_DBW acr7.bitc._DBW\r
+#define ACR7_BST acr7.bitc._BST\r
+#define ACR7_TYP acr7.bitc._TYP\r
+__IO_EXTERN AWR0STR awr0;  \r
+#define AWR0 awr0.word\r
+#define AWR0_W15 awr0.bit._W15\r
+#define AWR0_W14 awr0.bit._W14\r
+#define AWR0_W13 awr0.bit._W13\r
+#define AWR0_W12 awr0.bit._W12\r
+#define AWR0_W11 awr0.bit._W11\r
+#define AWR0_W10 awr0.bit._W10\r
+#define AWR0_W9 awr0.bit._W9\r
+#define AWR0_W8 awr0.bit._W8\r
+#define AWR0_W7 awr0.bit._W7\r
+#define AWR0_W6 awr0.bit._W6\r
+#define AWR0_W5 awr0.bit._W5\r
+#define AWR0_W4 awr0.bit._W4\r
+#define AWR0_W3 awr0.bit._W3\r
+#define AWR0_W2 awr0.bit._W2\r
+#define AWR0_W1 awr0.bit._W1\r
+#define AWR0_W0 awr0.bit._W0\r
+__IO_EXTERN AWR1STR awr1;  \r
+#define AWR1 awr1.word\r
+#define AWR1_W15 awr1.bit._W15\r
+#define AWR1_W14 awr1.bit._W14\r
+#define AWR1_W13 awr1.bit._W13\r
+#define AWR1_W12 awr1.bit._W12\r
+#define AWR1_W11 awr1.bit._W11\r
+#define AWR1_W10 awr1.bit._W10\r
+#define AWR1_W9 awr1.bit._W9\r
+#define AWR1_W8 awr1.bit._W8\r
+#define AWR1_W7 awr1.bit._W7\r
+#define AWR1_W6 awr1.bit._W6\r
+#define AWR1_W5 awr1.bit._W5\r
+#define AWR1_W4 awr1.bit._W4\r
+#define AWR1_W3 awr1.bit._W3\r
+#define AWR1_W2 awr1.bit._W2\r
+#define AWR1_W1 awr1.bit._W1\r
+#define AWR1_W0 awr1.bit._W0\r
+__IO_EXTERN AWR2STR awr2;  \r
+#define AWR2 awr2.word\r
+#define AWR2_W15 awr2.bit._W15\r
+#define AWR2_W14 awr2.bit._W14\r
+#define AWR2_W13 awr2.bit._W13\r
+#define AWR2_W12 awr2.bit._W12\r
+#define AWR2_W11 awr2.bit._W11\r
+#define AWR2_W10 awr2.bit._W10\r
+#define AWR2_W9 awr2.bit._W9\r
+#define AWR2_W8 awr2.bit._W8\r
+#define AWR2_W7 awr2.bit._W7\r
+#define AWR2_W6 awr2.bit._W6\r
+#define AWR2_W5 awr2.bit._W5\r
+#define AWR2_W4 awr2.bit._W4\r
+#define AWR2_W3 awr2.bit._W3\r
+#define AWR2_W2 awr2.bit._W2\r
+#define AWR2_W1 awr2.bit._W1\r
+#define AWR2_W0 awr2.bit._W0\r
+__IO_EXTERN AWR3STR awr3;  \r
+#define AWR3 awr3.word\r
+#define AWR3_W15 awr3.bit._W15\r
+#define AWR3_W14 awr3.bit._W14\r
+#define AWR3_W13 awr3.bit._W13\r
+#define AWR3_W12 awr3.bit._W12\r
+#define AWR3_W11 awr3.bit._W11\r
+#define AWR3_W10 awr3.bit._W10\r
+#define AWR3_W9 awr3.bit._W9\r
+#define AWR3_W8 awr3.bit._W8\r
+#define AWR3_W7 awr3.bit._W7\r
+#define AWR3_W6 awr3.bit._W6\r
+#define AWR3_W5 awr3.bit._W5\r
+#define AWR3_W4 awr3.bit._W4\r
+#define AWR3_W3 awr3.bit._W3\r
+#define AWR3_W2 awr3.bit._W2\r
+#define AWR3_W1 awr3.bit._W1\r
+#define AWR3_W0 awr3.bit._W0\r
+__IO_EXTERN AWR4STR awr4;  \r
+#define AWR4 awr4.word\r
+#define AWR4_W15 awr4.bit._W15\r
+#define AWR4_W14 awr4.bit._W14\r
+#define AWR4_W13 awr4.bit._W13\r
+#define AWR4_W12 awr4.bit._W12\r
+#define AWR4_W11 awr4.bit._W11\r
+#define AWR4_W10 awr4.bit._W10\r
+#define AWR4_W9 awr4.bit._W9\r
+#define AWR4_W8 awr4.bit._W8\r
+#define AWR4_W7 awr4.bit._W7\r
+#define AWR4_W6 awr4.bit._W6\r
+#define AWR4_W5 awr4.bit._W5\r
+#define AWR4_W4 awr4.bit._W4\r
+#define AWR4_W3 awr4.bit._W3\r
+#define AWR4_W2 awr4.bit._W2\r
+#define AWR4_W1 awr4.bit._W1\r
+#define AWR4_W0 awr4.bit._W0\r
+__IO_EXTERN AWR5STR awr5;  \r
+#define AWR5 awr5.word\r
+#define AWR5_W15 awr5.bit._W15\r
+#define AWR5_W14 awr5.bit._W14\r
+#define AWR5_W13 awr5.bit._W13\r
+#define AWR5_W12 awr5.bit._W12\r
+#define AWR5_W11 awr5.bit._W11\r
+#define AWR5_W10 awr5.bit._W10\r
+#define AWR5_W9 awr5.bit._W9\r
+#define AWR5_W8 awr5.bit._W8\r
+#define AWR5_W7 awr5.bit._W7\r
+#define AWR5_W6 awr5.bit._W6\r
+#define AWR5_W5 awr5.bit._W5\r
+#define AWR5_W4 awr5.bit._W4\r
+#define AWR5_W3 awr5.bit._W3\r
+#define AWR5_W2 awr5.bit._W2\r
+#define AWR5_W1 awr5.bit._W1\r
+#define AWR5_W0 awr5.bit._W0\r
+__IO_EXTERN AWR6STR awr6;  \r
+#define AWR6 awr6.word\r
+#define AWR6_W15 awr6.bit._W15\r
+#define AWR6_W14 awr6.bit._W14\r
+#define AWR6_W13 awr6.bit._W13\r
+#define AWR6_W12 awr6.bit._W12\r
+#define AWR6_W11 awr6.bit._W11\r
+#define AWR6_W10 awr6.bit._W10\r
+#define AWR6_W9 awr6.bit._W9\r
+#define AWR6_W8 awr6.bit._W8\r
+#define AWR6_W7 awr6.bit._W7\r
+#define AWR6_W6 awr6.bit._W6\r
+#define AWR6_W5 awr6.bit._W5\r
+#define AWR6_W4 awr6.bit._W4\r
+#define AWR6_W3 awr6.bit._W3\r
+#define AWR6_W2 awr6.bit._W2\r
+#define AWR6_W1 awr6.bit._W1\r
+#define AWR6_W0 awr6.bit._W0\r
+__IO_EXTERN AWR7STR awr7;  \r
+#define AWR7 awr7.word\r
+#define AWR7_W15 awr7.bit._W15\r
+#define AWR7_W14 awr7.bit._W14\r
+#define AWR7_W13 awr7.bit._W13\r
+#define AWR7_W12 awr7.bit._W12\r
+#define AWR7_W11 awr7.bit._W11\r
+#define AWR7_W10 awr7.bit._W10\r
+#define AWR7_W9 awr7.bit._W9\r
+#define AWR7_W8 awr7.bit._W8\r
+#define AWR7_W7 awr7.bit._W7\r
+#define AWR7_W6 awr7.bit._W6\r
+#define AWR7_W5 awr7.bit._W5\r
+#define AWR7_W4 awr7.bit._W4\r
+#define AWR7_W3 awr7.bit._W3\r
+#define AWR7_W2 awr7.bit._W2\r
+#define AWR7_W1 awr7.bit._W1\r
+#define AWR7_W0 awr7.bit._W0\r
+__IO_EXTERN MCRASTR mcra;  \r
+#define MCRA mcra.byte\r
+#define MCRA_PSZ2 mcra.bit._PSZ2\r
+#define MCRA_PSZ1 mcra.bit._PSZ1\r
+#define MCRA_PSZ0 mcra.bit._PSZ0\r
+#define MCRA_WBST mcra.bit._WBST\r
+#define MCRA_BANK mcra.bit._BANK\r
+#define MCRA_ABS1 mcra.bit._ABS1\r
+#define MCRA_ABS0 mcra.bit._ABS0\r
+#define MCRA_PSZ mcra.bitc._PSZ\r
+#define MCRA_ABS mcra.bitc._ABS\r
+__IO_EXTERN MCRBSTR mcrb;  \r
+#define MCRB mcrb.byte\r
+#define MCRB_PSZ2 mcrb.bit._PSZ2\r
+#define MCRB_PSZ1 mcrb.bit._PSZ1\r
+#define MCRB_PSZ0 mcrb.bit._PSZ0\r
+#define MCRB_WBST mcrb.bit._WBST\r
+#define MCRB_BANK mcrb.bit._BANK\r
+#define MCRB_ABS1 mcrb.bit._ABS1\r
+#define MCRB_ABS0 mcrb.bit._ABS0\r
+#define MCRB_PSZ mcrb.bitc._PSZ\r
+#define MCRB_ABS mcrb.bitc._ABS\r
+__IO_EXTERN IOWR0STR iowr0;  \r
+#define IOWR0 iowr0.byte\r
+#define IOWR0_RYE0 iowr0.bit._RYE0\r
+#define IOWR0_HLD0 iowr0.bit._HLD0\r
+#define IOWR0_WR01 iowr0.bit._WR01\r
+#define IOWR0_WR00 iowr0.bit._WR00\r
+#define IOWR0_IW03 iowr0.bit._IW03\r
+#define IOWR0_IW02 iowr0.bit._IW02\r
+#define IOWR0_IW01 iowr0.bit._IW01\r
+#define IOWR0_IW00 iowr0.bit._IW00\r
+#define IOWR0_WR0 iowr0.bitc._WR0\r
+#define IOWR0_IW0 iowr0.bitc._IW0\r
+__IO_EXTERN IOWR1STR iowr1;  \r
+#define IOWR1 iowr1.byte\r
+#define IOWR1_RYE1 iowr1.bit._RYE1\r
+#define IOWR1_HLD1 iowr1.bit._HLD1\r
+#define IOWR1_WR11 iowr1.bit._WR11\r
+#define IOWR1_WR10 iowr1.bit._WR10\r
+#define IOWR1_IW13 iowr1.bit._IW13\r
+#define IOWR1_IW12 iowr1.bit._IW12\r
+#define IOWR1_IW11 iowr1.bit._IW11\r
+#define IOWR1_IW10 iowr1.bit._IW10\r
+#define IOWR1_WR1 iowr1.bitc._WR1\r
+#define IOWR1_IW1 iowr1.bitc._IW1\r
+__IO_EXTERN IOWR2STR iowr2;  \r
+#define IOWR2 iowr2.byte\r
+#define IOWR2_RYE2 iowr2.bit._RYE2\r
+#define IOWR2_HLD2 iowr2.bit._HLD2\r
+#define IOWR2_WR21 iowr2.bit._WR21\r
+#define IOWR2_WR20 iowr2.bit._WR20\r
+#define IOWR2_IW23 iowr2.bit._IW23\r
+#define IOWR2_IW22 iowr2.bit._IW22\r
+#define IOWR2_IW21 iowr2.bit._IW21\r
+#define IOWR2_IW20 iowr2.bit._IW20\r
+#define IOWR2_WR2 iowr2.bitc._WR2\r
+#define IOWR2_IW2 iowr2.bitc._IW2\r
+__IO_EXTERN IOWR3STR iowr3;  \r
+#define IOWR3 iowr3.byte\r
+#define IOWR3_RYE3 iowr3.bit._RYE3\r
+#define IOWR3_HLD3 iowr3.bit._HLD3\r
+#define IOWR3_WR31 iowr3.bit._WR31\r
+#define IOWR3_WR30 iowr3.bit._WR30\r
+#define IOWR3_IW33 iowr3.bit._IW33\r
+#define IOWR3_IW32 iowr3.bit._IW32\r
+#define IOWR3_IW31 iowr3.bit._IW31\r
+#define IOWR3_IW30 iowr3.bit._IW30\r
+#define IOWR3_WR3 iowr3.bitc._WR3\r
+#define IOWR3_IW3 iowr3.bitc._IW3\r
+__IO_EXTERN CSERSTR cser;  \r
+#define CSER cser.byte\r
+#define CSER_CSE7 cser.bit._CSE7\r
+#define CSER_CSE6 cser.bit._CSE6\r
+#define CSER_CSE5 cser.bit._CSE5\r
+#define CSER_CSE4 cser.bit._CSE4\r
+#define CSER_CSE3 cser.bit._CSE3\r
+#define CSER_CSE2 cser.bit._CSE2\r
+#define CSER_CSE1 cser.bit._CSE1\r
+#define CSER_CSE0 cser.bit._CSE0\r
+__IO_EXTERN CHERSTR cher;  \r
+#define CHER cher.byte\r
+#define CHER_CHE7 cher.bit._CHE7\r
+#define CHER_CHE6 cher.bit._CHE6\r
+#define CHER_CHE5 cher.bit._CHE5\r
+#define CHER_CHE4 cher.bit._CHE4\r
+#define CHER_CHE3 cher.bit._CHE3\r
+#define CHER_CHE2 cher.bit._CHE2\r
+#define CHER_CHE1 cher.bit._CHE1\r
+#define CHER_CHE0 cher.bit._CHE0\r
+__IO_EXTERN TCRSTR tcr;  \r
+#define TCR tcr.byte\r
+#define TCR_BREN tcr.bit._BREN\r
+#define TCR_PSUS tcr.bit._PSUS\r
+#define TCR_PCLR tcr.bit._PCLR\r
+#define TCR_RDW1 tcr.bit._RDW1\r
+#define TCR_RDW0 tcr.bit._RDW0\r
+#define TCR_RDW tcr.bitc._RDW\r
+__IO_EXTERN RCRSTR rcr;  \r
+#define RCR rcr.word\r
+#define RCR_SELF rcr.bit._SELF\r
+#define RCR_RRLD rcr.bit._RRLD\r
+#define RCR_RFINT5 rcr.bit._RFINT5\r
+#define RCR_RFINT4 rcr.bit._RFINT4\r
+#define RCR_RDINT3 rcr.bit._RDINT3\r
+#define RCR_RFINT2 rcr.bit._RFINT2\r
+#define RCR_RFINT1 rcr.bit._RFINT1\r
+#define RCR_RFINT0 rcr.bit._RFINT0\r
+#define RCR_BRST rcr.bit._BRST\r
+#define RCR_RFC2 rcr.bit._RFC2\r
+#define RCR_RFC1 rcr.bit._RFC1\r
+#define RCR_RFC0 rcr.bit._RFC0\r
+#define RCR_PON rcr.bit._PON\r
+#define RCR_TRC2 rcr.bit._TRC2\r
+#define RCR_TRC1 rcr.bit._TRC1\r
+#define RCR_TRC0 rcr.bit._TRC0\r
+#define RCR_RFINT rcr.bitc._RFINT\r
+#define RCR_RFC rcr.bitc._RFC\r
+#define RCR_TRC rcr.bitc._TRC\r
+__IO_EXTERN MODRSTR modr;   /* Mode Register */\r
+#define MODR modr.byte\r
+#define MODR_ROMA modr.bit._ROMA\r
+#define MODR_WTH1 modr.bit._WTH1\r
+#define MODR_WTH0 modr.bit._WTH0\r
+#define MODR_WTH modr.bitc._WTH\r
+__IO_EXTERN PDRD00STR pdrd00;   /* R-bus Port Data Direct Read Register */\r
+#define PDRD00 pdrd00.byte\r
+#define PDRD00_D7 pdrd00.bit._D7\r
+#define PDRD00_D6 pdrd00.bit._D6\r
+#define PDRD00_D5 pdrd00.bit._D5\r
+#define PDRD00_D4 pdrd00.bit._D4\r
+#define PDRD00_D3 pdrd00.bit._D3\r
+#define PDRD00_D2 pdrd00.bit._D2\r
+#define PDRD00_D1 pdrd00.bit._D1\r
+#define PDRD00_D0 pdrd00.bit._D0\r
+__IO_EXTERN PDRD01STR pdrd01;  \r
+#define PDRD01 pdrd01.byte\r
+#define PDRD01_D7 pdrd01.bit._D7\r
+#define PDRD01_D6 pdrd01.bit._D6\r
+#define PDRD01_D5 pdrd01.bit._D5\r
+#define PDRD01_D4 pdrd01.bit._D4\r
+#define PDRD01_D3 pdrd01.bit._D3\r
+#define PDRD01_D2 pdrd01.bit._D2\r
+#define PDRD01_D1 pdrd01.bit._D1\r
+#define PDRD01_D0 pdrd01.bit._D0\r
+__IO_EXTERN PDRD02STR pdrd02;  \r
+#define PDRD02 pdrd02.byte\r
+#define PDRD02_D7 pdrd02.bit._D7\r
+#define PDRD02_D6 pdrd02.bit._D6\r
+#define PDRD02_D5 pdrd02.bit._D5\r
+#define PDRD02_D4 pdrd02.bit._D4\r
+#define PDRD02_D3 pdrd02.bit._D3\r
+#define PDRD02_D2 pdrd02.bit._D2\r
+#define PDRD02_D1 pdrd02.bit._D1\r
+#define PDRD02_D0 pdrd02.bit._D0\r
+__IO_EXTERN PDRD03STR pdrd03;  \r
+#define PDRD03 pdrd03.byte\r
+#define PDRD03_D7 pdrd03.bit._D7\r
+#define PDRD03_D6 pdrd03.bit._D6\r
+#define PDRD03_D5 pdrd03.bit._D5\r
+#define PDRD03_D4 pdrd03.bit._D4\r
+#define PDRD03_D3 pdrd03.bit._D3\r
+#define PDRD03_D2 pdrd03.bit._D2\r
+#define PDRD03_D1 pdrd03.bit._D1\r
+#define PDRD03_D0 pdrd03.bit._D0\r
+__IO_EXTERN PDRD04STR pdrd04;  \r
+#define PDRD04 pdrd04.byte\r
+#define PDRD04_D1 pdrd04.bit._D1\r
+#define PDRD04_D0 pdrd04.bit._D0\r
+__IO_EXTERN PDRD05STR pdrd05;  \r
+#define PDRD05 pdrd05.byte\r
+#define PDRD05_D7 pdrd05.bit._D7\r
+#define PDRD05_D6 pdrd05.bit._D6\r
+#define PDRD05_D5 pdrd05.bit._D5\r
+#define PDRD05_D4 pdrd05.bit._D4\r
+#define PDRD05_D3 pdrd05.bit._D3\r
+#define PDRD05_D2 pdrd05.bit._D2\r
+#define PDRD05_D1 pdrd05.bit._D1\r
+#define PDRD05_D0 pdrd05.bit._D0\r
+__IO_EXTERN PDRD06STR pdrd06;  \r
+#define PDRD06 pdrd06.byte\r
+#define PDRD06_D7 pdrd06.bit._D7\r
+#define PDRD06_D6 pdrd06.bit._D6\r
+#define PDRD06_D5 pdrd06.bit._D5\r
+#define PDRD06_D4 pdrd06.bit._D4\r
+#define PDRD06_D3 pdrd06.bit._D3\r
+#define PDRD06_D2 pdrd06.bit._D2\r
+#define PDRD06_D1 pdrd06.bit._D1\r
+#define PDRD06_D0 pdrd06.bit._D0\r
+__IO_EXTERN PDRD07STR pdrd07;  \r
+#define PDRD07 pdrd07.byte\r
+#define PDRD07_D7 pdrd07.bit._D7\r
+#define PDRD07_D6 pdrd07.bit._D6\r
+#define PDRD07_D5 pdrd07.bit._D5\r
+#define PDRD07_D4 pdrd07.bit._D4\r
+#define PDRD07_D3 pdrd07.bit._D3\r
+#define PDRD07_D2 pdrd07.bit._D2\r
+#define PDRD07_D1 pdrd07.bit._D1\r
+#define PDRD07_D0 pdrd07.bit._D0\r
+__IO_EXTERN PDRD08STR pdrd08;  \r
+#define PDRD08 pdrd08.byte\r
+#define PDRD08_D7 pdrd08.bit._D7\r
+#define PDRD08_D6 pdrd08.bit._D6\r
+#define PDRD08_D5 pdrd08.bit._D5\r
+#define PDRD08_D4 pdrd08.bit._D4\r
+#define PDRD08_D3 pdrd08.bit._D3\r
+#define PDRD08_D2 pdrd08.bit._D2\r
+#define PDRD08_D1 pdrd08.bit._D1\r
+#define PDRD08_D0 pdrd08.bit._D0\r
+__IO_EXTERN PDRD09STR pdrd09;  \r
+#define PDRD09 pdrd09.byte\r
+#define PDRD09_D7 pdrd09.bit._D7\r
+#define PDRD09_D6 pdrd09.bit._D6\r
+#define PDRD09_D3 pdrd09.bit._D3\r
+#define PDRD09_D2 pdrd09.bit._D2\r
+#define PDRD09_D1 pdrd09.bit._D1\r
+#define PDRD09_D0 pdrd09.bit._D0\r
+__IO_EXTERN PDRD10STR pdrd10;  \r
+#define PDRD10 pdrd10.byte\r
+#define PDRD10_D6 pdrd10.bit._D6\r
+#define PDRD10_D5 pdrd10.bit._D5\r
+#define PDRD10_D4 pdrd10.bit._D4\r
+#define PDRD10_D3 pdrd10.bit._D3\r
+#define PDRD10_D2 pdrd10.bit._D2\r
+#define PDRD10_D1 pdrd10.bit._D1\r
+__IO_EXTERN PDRD13STR pdrd13;  \r
+#define PDRD13 pdrd13.byte\r
+#define PDRD13_D2 pdrd13.bit._D2\r
+#define PDRD13_D1 pdrd13.bit._D1\r
+#define PDRD13_D0 pdrd13.bit._D0\r
+__IO_EXTERN PDRD14STR pdrd14;  \r
+#define PDRD14 pdrd14.byte\r
+#define PDRD14_D7 pdrd14.bit._D7\r
+#define PDRD14_D6 pdrd14.bit._D6\r
+#define PDRD14_D5 pdrd14.bit._D5\r
+#define PDRD14_D4 pdrd14.bit._D4\r
+#define PDRD14_D3 pdrd14.bit._D3\r
+#define PDRD14_D2 pdrd14.bit._D2\r
+#define PDRD14_D1 pdrd14.bit._D1\r
+#define PDRD14_D0 pdrd14.bit._D0\r
+__IO_EXTERN PDRD15STR pdrd15;  \r
+#define PDRD15 pdrd15.byte\r
+#define PDRD15_D3 pdrd15.bit._D3\r
+#define PDRD15_D2 pdrd15.bit._D2\r
+#define PDRD15_D1 pdrd15.bit._D1\r
+#define PDRD15_D0 pdrd15.bit._D0\r
+__IO_EXTERN PDRD16STR pdrd16;  \r
+#define PDRD16 pdrd16.byte\r
+#define PDRD16_D7 pdrd16.bit._D7\r
+#define PDRD16_D6 pdrd16.bit._D6\r
+#define PDRD16_D5 pdrd16.bit._D5\r
+#define PDRD16_D4 pdrd16.bit._D4\r
+#define PDRD16_D3 pdrd16.bit._D3\r
+#define PDRD16_D2 pdrd16.bit._D2\r
+#define PDRD16_D1 pdrd16.bit._D1\r
+#define PDRD16_D0 pdrd16.bit._D0\r
+__IO_EXTERN PDRD17STR pdrd17;  \r
+#define PDRD17 pdrd17.byte\r
+#define PDRD17_D7 pdrd17.bit._D7\r
+#define PDRD17_D6 pdrd17.bit._D6\r
+#define PDRD17_D5 pdrd17.bit._D5\r
+#define PDRD17_D4 pdrd17.bit._D4\r
+__IO_EXTERN PDRD18STR pdrd18;  \r
+#define PDRD18 pdrd18.byte\r
+#define PDRD18_D6 pdrd18.bit._D6\r
+#define PDRD18_D5 pdrd18.bit._D5\r
+#define PDRD18_D4 pdrd18.bit._D4\r
+#define PDRD18_D2 pdrd18.bit._D2\r
+#define PDRD18_D1 pdrd18.bit._D1\r
+#define PDRD18_D0 pdrd18.bit._D0\r
+__IO_EXTERN PDRD19STR pdrd19;  \r
+#define PDRD19 pdrd19.byte\r
+#define PDRD19_D6 pdrd19.bit._D6\r
+#define PDRD19_D5 pdrd19.bit._D5\r
+#define PDRD19_D4 pdrd19.bit._D4\r
+#define PDRD19_D2 pdrd19.bit._D2\r
+#define PDRD19_D1 pdrd19.bit._D1\r
+#define PDRD19_D0 pdrd19.bit._D0\r
+__IO_EXTERN PDRD20STR pdrd20;  \r
+#define PDRD20 pdrd20.byte\r
+#define PDRD20_D2 pdrd20.bit._D2\r
+#define PDRD20_D1 pdrd20.bit._D1\r
+#define PDRD20_D0 pdrd20.bit._D0\r
+__IO_EXTERN PDRD22STR pdrd22;  \r
+#define PDRD22 pdrd22.byte\r
+#define PDRD22_D5 pdrd22.bit._D5\r
+#define PDRD22_D4 pdrd22.bit._D4\r
+#define PDRD22_D2 pdrd22.bit._D2\r
+#define PDRD22_D0 pdrd22.bit._D0\r
+__IO_EXTERN PDRD23STR pdrd23;  \r
+#define PDRD23 pdrd23.byte\r
+#define PDRD23_D5 pdrd23.bit._D5\r
+#define PDRD23_D4 pdrd23.bit._D4\r
+#define PDRD23_D3 pdrd23.bit._D3\r
+#define PDRD23_D2 pdrd23.bit._D2\r
+#define PDRD23_D1 pdrd23.bit._D1\r
+#define PDRD23_D0 pdrd23.bit._D0\r
+__IO_EXTERN PDRD24STR pdrd24;  \r
+#define PDRD24 pdrd24.byte\r
+#define PDRD24_D7 pdrd24.bit._D7\r
+#define PDRD24_D6 pdrd24.bit._D6\r
+#define PDRD24_D5 pdrd24.bit._D5\r
+#define PDRD24_D4 pdrd24.bit._D4\r
+#define PDRD24_D3 pdrd24.bit._D3\r
+#define PDRD24_D2 pdrd24.bit._D2\r
+#define PDRD24_D1 pdrd24.bit._D1\r
+#define PDRD24_D0 pdrd24.bit._D0\r
+__IO_EXTERN PDRD25STR pdrd25;  \r
+#define PDRD25 pdrd25.byte\r
+#define PDRD25_D7 pdrd25.bit._D7\r
+#define PDRD25_D6 pdrd25.bit._D6\r
+#define PDRD25_D5 pdrd25.bit._D5\r
+#define PDRD25_D4 pdrd25.bit._D4\r
+#define PDRD25_D3 pdrd25.bit._D3\r
+#define PDRD25_D2 pdrd25.bit._D2\r
+#define PDRD25_D1 pdrd25.bit._D1\r
+#define PDRD25_D0 pdrd25.bit._D0\r
+__IO_EXTERN PDRD26STR pdrd26;  \r
+#define PDRD26 pdrd26.byte\r
+#define PDRD26_D7 pdrd26.bit._D7\r
+#define PDRD26_D6 pdrd26.bit._D6\r
+#define PDRD26_D5 pdrd26.bit._D5\r
+#define PDRD26_D4 pdrd26.bit._D4\r
+#define PDRD26_D3 pdrd26.bit._D3\r
+#define PDRD26_D2 pdrd26.bit._D2\r
+#define PDRD26_D1 pdrd26.bit._D1\r
+#define PDRD26_D0 pdrd26.bit._D0\r
+__IO_EXTERN PDRD27STR pdrd27;  \r
+#define PDRD27 pdrd27.byte\r
+#define PDRD27_D7 pdrd27.bit._D7\r
+#define PDRD27_D6 pdrd27.bit._D6\r
+#define PDRD27_D5 pdrd27.bit._D5\r
+#define PDRD27_D4 pdrd27.bit._D4\r
+#define PDRD27_D3 pdrd27.bit._D3\r
+#define PDRD27_D2 pdrd27.bit._D2\r
+#define PDRD27_D1 pdrd27.bit._D1\r
+#define PDRD27_D0 pdrd27.bit._D0\r
+__IO_EXTERN PDRD29STR pdrd29;  \r
+#define PDRD29 pdrd29.byte\r
+#define PDRD29_D7 pdrd29.bit._D7\r
+#define PDRD29_D6 pdrd29.bit._D6\r
+#define PDRD29_D5 pdrd29.bit._D5\r
+#define PDRD29_D4 pdrd29.bit._D4\r
+#define PDRD29_D3 pdrd29.bit._D3\r
+#define PDRD29_D2 pdrd29.bit._D2\r
+#define PDRD29_D1 pdrd29.bit._D1\r
+#define PDRD29_D0 pdrd29.bit._D0\r
+__IO_EXTERN DDR00STR ddr00;   /* R-bus Port Direction Register */\r
+#define DDR00 ddr00.byte\r
+#define DDR00_D7 ddr00.bit._D7\r
+#define DDR00_D6 ddr00.bit._D6\r
+#define DDR00_D5 ddr00.bit._D5\r
+#define DDR00_D4 ddr00.bit._D4\r
+#define DDR00_D3 ddr00.bit._D3\r
+#define DDR00_D2 ddr00.bit._D2\r
+#define DDR00_D1 ddr00.bit._D1\r
+#define DDR00_D0 ddr00.bit._D0\r
+__IO_EXTERN DDR01STR ddr01;  \r
+#define DDR01 ddr01.byte\r
+#define DDR01_D7 ddr01.bit._D7\r
+#define DDR01_D6 ddr01.bit._D6\r
+#define DDR01_D5 ddr01.bit._D5\r
+#define DDR01_D4 ddr01.bit._D4\r
+#define DDR01_D3 ddr01.bit._D3\r
+#define DDR01_D2 ddr01.bit._D2\r
+#define DDR01_D1 ddr01.bit._D1\r
+#define DDR01_D0 ddr01.bit._D0\r
+__IO_EXTERN DDR02STR ddr02;  \r
+#define DDR02 ddr02.byte\r
+#define DDR02_D7 ddr02.bit._D7\r
+#define DDR02_D6 ddr02.bit._D6\r
+#define DDR02_D5 ddr02.bit._D5\r
+#define DDR02_D4 ddr02.bit._D4\r
+#define DDR02_D3 ddr02.bit._D3\r
+#define DDR02_D2 ddr02.bit._D2\r
+#define DDR02_D1 ddr02.bit._D1\r
+#define DDR02_D0 ddr02.bit._D0\r
+__IO_EXTERN DDR03STR ddr03;  \r
+#define DDR03 ddr03.byte\r
+#define DDR03_D7 ddr03.bit._D7\r
+#define DDR03_D6 ddr03.bit._D6\r
+#define DDR03_D5 ddr03.bit._D5\r
+#define DDR03_D4 ddr03.bit._D4\r
+#define DDR03_D3 ddr03.bit._D3\r
+#define DDR03_D2 ddr03.bit._D2\r
+#define DDR03_D1 ddr03.bit._D1\r
+#define DDR03_D0 ddr03.bit._D0\r
+__IO_EXTERN DDR04STR ddr04;  \r
+#define DDR04 ddr04.byte\r
+#define DDR04_D1 ddr04.bit._D1\r
+#define DDR04_D0 ddr04.bit._D0\r
+__IO_EXTERN DDR05STR ddr05;  \r
+#define DDR05 ddr05.byte\r
+#define DDR05_D7 ddr05.bit._D7\r
+#define DDR05_D6 ddr05.bit._D6\r
+#define DDR05_D5 ddr05.bit._D5\r
+#define DDR05_D4 ddr05.bit._D4\r
+#define DDR05_D3 ddr05.bit._D3\r
+#define DDR05_D2 ddr05.bit._D2\r
+#define DDR05_D1 ddr05.bit._D1\r
+#define DDR05_D0 ddr05.bit._D0\r
+__IO_EXTERN DDR06STR ddr06;  \r
+#define DDR06 ddr06.byte\r
+#define DDR06_D7 ddr06.bit._D7\r
+#define DDR06_D6 ddr06.bit._D6\r
+#define DDR06_D5 ddr06.bit._D5\r
+#define DDR06_D4 ddr06.bit._D4\r
+#define DDR06_D3 ddr06.bit._D3\r
+#define DDR06_D2 ddr06.bit._D2\r
+#define DDR06_D1 ddr06.bit._D1\r
+#define DDR06_D0 ddr06.bit._D0\r
+__IO_EXTERN DDR07STR ddr07;  \r
+#define DDR07 ddr07.byte\r
+#define DDR07_D7 ddr07.bit._D7\r
+#define DDR07_D6 ddr07.bit._D6\r
+#define DDR07_D5 ddr07.bit._D5\r
+#define DDR07_D4 ddr07.bit._D4\r
+#define DDR07_D3 ddr07.bit._D3\r
+#define DDR07_D2 ddr07.bit._D2\r
+#define DDR07_D1 ddr07.bit._D1\r
+#define DDR07_D0 ddr07.bit._D0\r
+__IO_EXTERN DDR08STR ddr08;  \r
+#define DDR08 ddr08.byte\r
+#define DDR08_D7 ddr08.bit._D7\r
+#define DDR08_D6 ddr08.bit._D6\r
+#define DDR08_D5 ddr08.bit._D5\r
+#define DDR08_D4 ddr08.bit._D4\r
+#define DDR08_D3 ddr08.bit._D3\r
+#define DDR08_D2 ddr08.bit._D2\r
+#define DDR08_D1 ddr08.bit._D1\r
+#define DDR08_D0 ddr08.bit._D0\r
+__IO_EXTERN DDR09STR ddr09;  \r
+#define DDR09 ddr09.byte\r
+#define DDR09_D7 ddr09.bit._D7\r
+#define DDR09_D6 ddr09.bit._D6\r
+#define DDR09_D3 ddr09.bit._D3\r
+#define DDR09_D2 ddr09.bit._D2\r
+#define DDR09_D1 ddr09.bit._D1\r
+#define DDR09_D0 ddr09.bit._D0\r
+__IO_EXTERN DDR10STR ddr10;  \r
+#define DDR10 ddr10.byte\r
+#define DDR10_D6 ddr10.bit._D6\r
+#define DDR10_D5 ddr10.bit._D5\r
+#define DDR10_D4 ddr10.bit._D4\r
+#define DDR10_D3 ddr10.bit._D3\r
+#define DDR10_D2 ddr10.bit._D2\r
+#define DDR10_D1 ddr10.bit._D1\r
+__IO_EXTERN DDR13STR ddr13;  \r
+#define DDR13 ddr13.byte\r
+#define DDR13_D2 ddr13.bit._D2\r
+#define DDR13_D1 ddr13.bit._D1\r
+#define DDR13_D0 ddr13.bit._D0\r
+__IO_EXTERN DDR14STR ddr14;  \r
+#define DDR14 ddr14.byte\r
+#define DDR14_D7 ddr14.bit._D7\r
+#define DDR14_D6 ddr14.bit._D6\r
+#define DDR14_D5 ddr14.bit._D5\r
+#define DDR14_D4 ddr14.bit._D4\r
+#define DDR14_D3 ddr14.bit._D3\r
+#define DDR14_D2 ddr14.bit._D2\r
+#define DDR14_D1 ddr14.bit._D1\r
+#define DDR14_D0 ddr14.bit._D0\r
+__IO_EXTERN DDR15STR ddr15;  \r
+#define DDR15 ddr15.byte\r
+#define DDR15_D3 ddr15.bit._D3\r
+#define DDR15_D2 ddr15.bit._D2\r
+#define DDR15_D1 ddr15.bit._D1\r
+#define DDR15_D0 ddr15.bit._D0\r
+__IO_EXTERN DDR16STR ddr16;  \r
+#define DDR16 ddr16.byte\r
+#define DDR16_D7 ddr16.bit._D7\r
+#define DDR16_D6 ddr16.bit._D6\r
+#define DDR16_D5 ddr16.bit._D5\r
+#define DDR16_D4 ddr16.bit._D4\r
+#define DDR16_D3 ddr16.bit._D3\r
+#define DDR16_D2 ddr16.bit._D2\r
+#define DDR16_D1 ddr16.bit._D1\r
+#define DDR16_D0 ddr16.bit._D0\r
+__IO_EXTERN DDR17STR ddr17;  \r
+#define DDR17 ddr17.byte\r
+#define DDR17_D7 ddr17.bit._D7\r
+#define DDR17_D6 ddr17.bit._D6\r
+#define DDR17_D5 ddr17.bit._D5\r
+#define DDR17_D4 ddr17.bit._D4\r
+__IO_EXTERN DDR18STR ddr18;  \r
+#define DDR18 ddr18.byte\r
+#define DDR18_D6 ddr18.bit._D6\r
+#define DDR18_D5 ddr18.bit._D5\r
+#define DDR18_D4 ddr18.bit._D4\r
+#define DDR18_D2 ddr18.bit._D2\r
+#define DDR18_D1 ddr18.bit._D1\r
+#define DDR18_D0 ddr18.bit._D0\r
+__IO_EXTERN DDR19STR ddr19;  \r
+#define DDR19 ddr19.byte\r
+#define DDR19_D6 ddr19.bit._D6\r
+#define DDR19_D5 ddr19.bit._D5\r
+#define DDR19_D4 ddr19.bit._D4\r
+#define DDR19_D2 ddr19.bit._D2\r
+#define DDR19_D1 ddr19.bit._D1\r
+#define DDR19_D0 ddr19.bit._D0\r
+__IO_EXTERN DDR20STR ddr20;  \r
+#define DDR20 ddr20.byte\r
+#define DDR20_D2 ddr20.bit._D2\r
+#define DDR20_D1 ddr20.bit._D1\r
+#define DDR20_D0 ddr20.bit._D0\r
+__IO_EXTERN DDR22STR ddr22;  \r
+#define DDR22 ddr22.byte\r
+#define DDR22_D5 ddr22.bit._D5\r
+#define DDR22_D4 ddr22.bit._D4\r
+#define DDR22_D2 ddr22.bit._D2\r
+#define DDR22_D0 ddr22.bit._D0\r
+__IO_EXTERN DDR23STR ddr23;  \r
+#define DDR23 ddr23.byte\r
+#define DDR23_D5 ddr23.bit._D5\r
+#define DDR23_D4 ddr23.bit._D4\r
+#define DDR23_D3 ddr23.bit._D3\r
+#define DDR23_D2 ddr23.bit._D2\r
+#define DDR23_D1 ddr23.bit._D1\r
+#define DDR23_D0 ddr23.bit._D0\r
+__IO_EXTERN DDR24STR ddr24;  \r
+#define DDR24 ddr24.byte\r
+#define DDR24_D7 ddr24.bit._D7\r
+#define DDR24_D6 ddr24.bit._D6\r
+#define DDR24_D5 ddr24.bit._D5\r
+#define DDR24_D4 ddr24.bit._D4\r
+#define DDR24_D3 ddr24.bit._D3\r
+#define DDR24_D2 ddr24.bit._D2\r
+#define DDR24_D1 ddr24.bit._D1\r
+#define DDR24_D0 ddr24.bit._D0\r
+__IO_EXTERN DDR25STR ddr25;  \r
+#define DDR25 ddr25.byte\r
+#define DDR25_D7 ddr25.bit._D7\r
+#define DDR25_D6 ddr25.bit._D6\r
+#define DDR25_D5 ddr25.bit._D5\r
+#define DDR25_D4 ddr25.bit._D4\r
+#define DDR25_D3 ddr25.bit._D3\r
+#define DDR25_D2 ddr25.bit._D2\r
+#define DDR25_D1 ddr25.bit._D1\r
+#define DDR25_D0 ddr25.bit._D0\r
+__IO_EXTERN DDR26STR ddr26;  \r
+#define DDR26 ddr26.byte\r
+#define DDR26_D7 ddr26.bit._D7\r
+#define DDR26_D6 ddr26.bit._D6\r
+#define DDR26_D5 ddr26.bit._D5\r
+#define DDR26_D4 ddr26.bit._D4\r
+#define DDR26_D3 ddr26.bit._D3\r
+#define DDR26_D2 ddr26.bit._D2\r
+#define DDR26_D1 ddr26.bit._D1\r
+#define DDR26_D0 ddr26.bit._D0\r
+__IO_EXTERN DDR27STR ddr27;  \r
+#define DDR27 ddr27.byte\r
+#define DDR27_D7 ddr27.bit._D7\r
+#define DDR27_D6 ddr27.bit._D6\r
+#define DDR27_D5 ddr27.bit._D5\r
+#define DDR27_D4 ddr27.bit._D4\r
+#define DDR27_D3 ddr27.bit._D3\r
+#define DDR27_D2 ddr27.bit._D2\r
+#define DDR27_D1 ddr27.bit._D1\r
+#define DDR27_D0 ddr27.bit._D0\r
+__IO_EXTERN DDR29STR ddr29;  \r
+#define DDR29 ddr29.byte\r
+#define DDR29_D7 ddr29.bit._D7\r
+#define DDR29_D6 ddr29.bit._D6\r
+#define DDR29_D5 ddr29.bit._D5\r
+#define DDR29_D4 ddr29.bit._D4\r
+#define DDR29_D3 ddr29.bit._D3\r
+#define DDR29_D2 ddr29.bit._D2\r
+#define DDR29_D1 ddr29.bit._D1\r
+#define DDR29_D0 ddr29.bit._D0\r
+__IO_EXTERN PFR00STR pfr00;   /* R-bus Port Function Register */\r
+#define PFR00 pfr00.byte\r
+#define PFR00_D7 pfr00.bit._D7\r
+#define PFR00_D6 pfr00.bit._D6\r
+#define PFR00_D5 pfr00.bit._D5\r
+#define PFR00_D4 pfr00.bit._D4\r
+#define PFR00_D3 pfr00.bit._D3\r
+#define PFR00_D2 pfr00.bit._D2\r
+#define PFR00_D1 pfr00.bit._D1\r
+#define PFR00_D0 pfr00.bit._D0\r
+__IO_EXTERN PFR01STR pfr01;  \r
+#define PFR01 pfr01.byte\r
+#define PFR01_D7 pfr01.bit._D7\r
+#define PFR01_D6 pfr01.bit._D6\r
+#define PFR01_D5 pfr01.bit._D5\r
+#define PFR01_D4 pfr01.bit._D4\r
+#define PFR01_D3 pfr01.bit._D3\r
+#define PFR01_D2 pfr01.bit._D2\r
+#define PFR01_D1 pfr01.bit._D1\r
+#define PFR01_D0 pfr01.bit._D0\r
+__IO_EXTERN PFR02STR pfr02;  \r
+#define PFR02 pfr02.byte\r
+#define PFR02_D7 pfr02.bit._D7\r
+#define PFR02_D6 pfr02.bit._D6\r
+#define PFR02_D5 pfr02.bit._D5\r
+#define PFR02_D4 pfr02.bit._D4\r
+#define PFR02_D3 pfr02.bit._D3\r
+#define PFR02_D2 pfr02.bit._D2\r
+#define PFR02_D1 pfr02.bit._D1\r
+#define PFR02_D0 pfr02.bit._D0\r
+__IO_EXTERN PFR03STR pfr03;  \r
+#define PFR03 pfr03.byte\r
+#define PFR03_D7 pfr03.bit._D7\r
+#define PFR03_D6 pfr03.bit._D6\r
+#define PFR03_D5 pfr03.bit._D5\r
+#define PFR03_D4 pfr03.bit._D4\r
+#define PFR03_D3 pfr03.bit._D3\r
+#define PFR03_D2 pfr03.bit._D2\r
+#define PFR03_D1 pfr03.bit._D1\r
+#define PFR03_D0 pfr03.bit._D0\r
+__IO_EXTERN PFR04STR pfr04;  \r
+#define PFR04 pfr04.byte\r
+#define PFR04_D1 pfr04.bit._D1\r
+#define PFR04_D0 pfr04.bit._D0\r
+__IO_EXTERN PFR05STR pfr05;  \r
+#define PFR05 pfr05.byte\r
+#define PFR05_D7 pfr05.bit._D7\r
+#define PFR05_D6 pfr05.bit._D6\r
+#define PFR05_D5 pfr05.bit._D5\r
+#define PFR05_D4 pfr05.bit._D4\r
+#define PFR05_D3 pfr05.bit._D3\r
+#define PFR05_D2 pfr05.bit._D2\r
+#define PFR05_D1 pfr05.bit._D1\r
+#define PFR05_D0 pfr05.bit._D0\r
+__IO_EXTERN PFR06STR pfr06;  \r
+#define PFR06 pfr06.byte\r
+#define PFR06_D7 pfr06.bit._D7\r
+#define PFR06_D6 pfr06.bit._D6\r
+#define PFR06_D5 pfr06.bit._D5\r
+#define PFR06_D4 pfr06.bit._D4\r
+#define PFR06_D3 pfr06.bit._D3\r
+#define PFR06_D2 pfr06.bit._D2\r
+#define PFR06_D1 pfr06.bit._D1\r
+#define PFR06_D0 pfr06.bit._D0\r
+__IO_EXTERN PFR07STR pfr07;  \r
+#define PFR07 pfr07.byte\r
+#define PFR07_D7 pfr07.bit._D7\r
+#define PFR07_D6 pfr07.bit._D6\r
+#define PFR07_D5 pfr07.bit._D5\r
+#define PFR07_D4 pfr07.bit._D4\r
+#define PFR07_D3 pfr07.bit._D3\r
+#define PFR07_D2 pfr07.bit._D2\r
+#define PFR07_D1 pfr07.bit._D1\r
+#define PFR07_D0 pfr07.bit._D0\r
+__IO_EXTERN PFR08STR pfr08;  \r
+#define PFR08 pfr08.byte\r
+#define PFR08_D7 pfr08.bit._D7\r
+#define PFR08_D6 pfr08.bit._D6\r
+#define PFR08_D5 pfr08.bit._D5\r
+#define PFR08_D4 pfr08.bit._D4\r
+#define PFR08_D3 pfr08.bit._D3\r
+#define PFR08_D2 pfr08.bit._D2\r
+#define PFR08_D1 pfr08.bit._D1\r
+#define PFR08_D0 pfr08.bit._D0\r
+__IO_EXTERN PFR09STR pfr09;  \r
+#define PFR09 pfr09.byte\r
+#define PFR09_D7 pfr09.bit._D7\r
+#define PFR09_D6 pfr09.bit._D6\r
+#define PFR09_D3 pfr09.bit._D3\r
+#define PFR09_D2 pfr09.bit._D2\r
+#define PFR09_D1 pfr09.bit._D1\r
+#define PFR09_D0 pfr09.bit._D0\r
+__IO_EXTERN PFR10STR pfr10;  \r
+#define PFR10 pfr10.byte\r
+#define PFR10_D6 pfr10.bit._D6\r
+#define PFR10_D5 pfr10.bit._D5\r
+#define PFR10_D4 pfr10.bit._D4\r
+#define PFR10_D3 pfr10.bit._D3\r
+#define PFR10_D2 pfr10.bit._D2\r
+#define PFR10_D1 pfr10.bit._D1\r
+__IO_EXTERN PFR13STR pfr13;  \r
+#define PFR13 pfr13.byte\r
+#define PFR13_D2 pfr13.bit._D2\r
+#define PFR13_D1 pfr13.bit._D1\r
+#define PFR13_D0 pfr13.bit._D0\r
+__IO_EXTERN PFR14STR pfr14;  \r
+#define PFR14 pfr14.byte\r
+#define PFR14_D7 pfr14.bit._D7\r
+#define PFR14_D6 pfr14.bit._D6\r
+#define PFR14_D5 pfr14.bit._D5\r
+#define PFR14_D4 pfr14.bit._D4\r
+#define PFR14_D3 pfr14.bit._D3\r
+#define PFR14_D2 pfr14.bit._D2\r
+#define PFR14_D1 pfr14.bit._D1\r
+#define PFR14_D0 pfr14.bit._D0\r
+__IO_EXTERN PFR15STR pfr15;  \r
+#define PFR15 pfr15.byte\r
+#define PFR15_D3 pfr15.bit._D3\r
+#define PFR15_D2 pfr15.bit._D2\r
+#define PFR15_D1 pfr15.bit._D1\r
+#define PFR15_D0 pfr15.bit._D0\r
+__IO_EXTERN PFR16STR pfr16;  \r
+#define PFR16 pfr16.byte\r
+#define PFR16_D7 pfr16.bit._D7\r
+#define PFR16_D6 pfr16.bit._D6\r
+#define PFR16_D5 pfr16.bit._D5\r
+#define PFR16_D4 pfr16.bit._D4\r
+#define PFR16_D3 pfr16.bit._D3\r
+#define PFR16_D2 pfr16.bit._D2\r
+#define PFR16_D1 pfr16.bit._D1\r
+#define PFR16_D0 pfr16.bit._D0\r
+__IO_EXTERN PFR17STR pfr17;  \r
+#define PFR17 pfr17.byte\r
+#define PFR17_D7 pfr17.bit._D7\r
+#define PFR17_D6 pfr17.bit._D6\r
+#define PFR17_D5 pfr17.bit._D5\r
+#define PFR17_D4 pfr17.bit._D4\r
+__IO_EXTERN PFR18STR pfr18;  \r
+#define PFR18 pfr18.byte\r
+#define PFR18_D6 pfr18.bit._D6\r
+#define PFR18_D5 pfr18.bit._D5\r
+#define PFR18_D4 pfr18.bit._D4\r
+#define PFR18_D2 pfr18.bit._D2\r
+#define PFR18_D1 pfr18.bit._D1\r
+#define PFR18_D0 pfr18.bit._D0\r
+__IO_EXTERN PFR19STR pfr19;  \r
+#define PFR19 pfr19.byte\r
+#define PFR19_D6 pfr19.bit._D6\r
+#define PFR19_D5 pfr19.bit._D5\r
+#define PFR19_D4 pfr19.bit._D4\r
+#define PFR19_D2 pfr19.bit._D2\r
+#define PFR19_D1 pfr19.bit._D1\r
+#define PFR19_D0 pfr19.bit._D0\r
+__IO_EXTERN PFR20STR pfr20;  \r
+#define PFR20 pfr20.byte\r
+#define PFR20_D2 pfr20.bit._D2\r
+#define PFR20_D1 pfr20.bit._D1\r
+#define PFR20_D0 pfr20.bit._D0\r
+__IO_EXTERN PFR22STR pfr22;  \r
+#define PFR22 pfr22.byte\r
+#define PFR22_D5 pfr22.bit._D5\r
+#define PFR22_D4 pfr22.bit._D4\r
+#define PFR22_D2 pfr22.bit._D2\r
+#define PFR22_D0 pfr22.bit._D0\r
+__IO_EXTERN PFR23STR pfr23;  \r
+#define PFR23 pfr23.byte\r
+#define PFR23_D5 pfr23.bit._D5\r
+#define PFR23_D4 pfr23.bit._D4\r
+#define PFR23_D3 pfr23.bit._D3\r
+#define PFR23_D2 pfr23.bit._D2\r
+#define PFR23_D1 pfr23.bit._D1\r
+#define PFR23_D0 pfr23.bit._D0\r
+__IO_EXTERN PFR24STR pfr24;  \r
+#define PFR24 pfr24.byte\r
+#define PFR24_D7 pfr24.bit._D7\r
+#define PFR24_D6 pfr24.bit._D6\r
+#define PFR24_D5 pfr24.bit._D5\r
+#define PFR24_D4 pfr24.bit._D4\r
+#define PFR24_D3 pfr24.bit._D3\r
+#define PFR24_D2 pfr24.bit._D2\r
+#define PFR24_D1 pfr24.bit._D1\r
+#define PFR24_D0 pfr24.bit._D0\r
+__IO_EXTERN PFR25STR pfr25;  \r
+#define PFR25 pfr25.byte\r
+#define PFR25_D7 pfr25.bit._D7\r
+#define PFR25_D6 pfr25.bit._D6\r
+#define PFR25_D5 pfr25.bit._D5\r
+#define PFR25_D4 pfr25.bit._D4\r
+#define PFR25_D3 pfr25.bit._D3\r
+#define PFR25_D2 pfr25.bit._D2\r
+#define PFR25_D1 pfr25.bit._D1\r
+#define PFR25_D0 pfr25.bit._D0\r
+__IO_EXTERN PFR26STR pfr26;  \r
+#define PFR26 pfr26.byte\r
+#define PFR26_D7 pfr26.bit._D7\r
+#define PFR26_D6 pfr26.bit._D6\r
+#define PFR26_D5 pfr26.bit._D5\r
+#define PFR26_D4 pfr26.bit._D4\r
+#define PFR26_D3 pfr26.bit._D3\r
+#define PFR26_D2 pfr26.bit._D2\r
+#define PFR26_D1 pfr26.bit._D1\r
+#define PFR26_D0 pfr26.bit._D0\r
+__IO_EXTERN PFR27STR pfr27;  \r
+#define PFR27 pfr27.byte\r
+#define PFR27_D7 pfr27.bit._D7\r
+#define PFR27_D6 pfr27.bit._D6\r
+#define PFR27_D5 pfr27.bit._D5\r
+#define PFR27_D4 pfr27.bit._D4\r
+#define PFR27_D3 pfr27.bit._D3\r
+#define PFR27_D2 pfr27.bit._D2\r
+#define PFR27_D1 pfr27.bit._D1\r
+#define PFR27_D0 pfr27.bit._D0\r
+__IO_EXTERN PFR29STR pfr29;  \r
+#define PFR29 pfr29.byte\r
+#define PFR29_D7 pfr29.bit._D7\r
+#define PFR29_D6 pfr29.bit._D6\r
+#define PFR29_D5 pfr29.bit._D5\r
+#define PFR29_D4 pfr29.bit._D4\r
+#define PFR29_D3 pfr29.bit._D3\r
+#define PFR29_D2 pfr29.bit._D2\r
+#define PFR29_D1 pfr29.bit._D1\r
+#define PFR29_D0 pfr29.bit._D0\r
+__IO_EXTERN EPFR10STR epfr10;   /* R-bus Port Extra Function Register */\r
+#define EPFR10 epfr10.byte\r
+#define EPFR10_D5 epfr10.bit._D5\r
+#define EPFR10_D4 epfr10.bit._D4\r
+__IO_EXTERN EPFR13STR epfr13;  \r
+#define EPFR13 epfr13.byte\r
+#define EPFR13_D2 epfr13.bit._D2\r
+__IO_EXTERN EPFR14STR epfr14;  \r
+#define EPFR14 epfr14.byte\r
+#define EPFR14_D7 epfr14.bit._D7\r
+#define EPFR14_D6 epfr14.bit._D6\r
+#define EPFR14_D5 epfr14.bit._D5\r
+#define EPFR14_D4 epfr14.bit._D4\r
+#define EPFR14_D3 epfr14.bit._D3\r
+#define EPFR14_D2 epfr14.bit._D2\r
+#define EPFR14_D1 epfr14.bit._D1\r
+#define EPFR14_D0 epfr14.bit._D0\r
+__IO_EXTERN EPFR15STR epfr15;  \r
+#define EPFR15 epfr15.byte\r
+#define EPFR15_D3 epfr15.bit._D3\r
+#define EPFR15_D2 epfr15.bit._D2\r
+#define EPFR15_D1 epfr15.bit._D1\r
+#define EPFR15_D0 epfr15.bit._D0\r
+__IO_EXTERN EPFR16STR epfr16;  \r
+#define EPFR16 epfr16.byte\r
+#define EPFR16_D7 epfr16.bit._D7\r
+#define EPFR16_D6 epfr16.bit._D6\r
+#define EPFR16_D5 epfr16.bit._D5\r
+#define EPFR16_D4 epfr16.bit._D4\r
+__IO_EXTERN EPFR18STR epfr18;  \r
+#define EPFR18 epfr18.byte\r
+#define EPFR18_D6 epfr18.bit._D6\r
+#define EPFR18_D5 epfr18.bit._D5\r
+#define EPFR18_D4 epfr18.bit._D4\r
+#define EPFR18_D2 epfr18.bit._D2\r
+#define EPFR18_D1 epfr18.bit._D1\r
+#define EPFR18_D0 epfr18.bit._D0\r
+__IO_EXTERN EPFR19STR epfr19;  \r
+#define EPFR19 epfr19.byte\r
+#define EPFR19_D6 epfr19.bit._D6\r
+#define EPFR19_D2 epfr19.bit._D2\r
+__IO_EXTERN EPFR20STR epfr20;  \r
+#define EPFR20 epfr20.byte\r
+#define EPFR20_D2 epfr20.bit._D2\r
+#define EPFR20_D1 epfr20.bit._D1\r
+#define EPFR20_D0 epfr20.bit._D0\r
+__IO_EXTERN EPFR26STR epfr26;  \r
+#define EPFR26 epfr26.byte\r
+#define EPFR26_D7 epfr26.bit._D7\r
+#define EPFR26_D6 epfr26.bit._D6\r
+#define EPFR26_D5 epfr26.bit._D5\r
+#define EPFR26_D4 epfr26.bit._D4\r
+#define EPFR26_D3 epfr26.bit._D3\r
+#define EPFR26_D2 epfr26.bit._D2\r
+#define EPFR26_D1 epfr26.bit._D1\r
+#define EPFR26_D0 epfr26.bit._D0\r
+__IO_EXTERN EPFR27STR epfr27;  \r
+#define EPFR27 epfr27.byte\r
+#define EPFR27_D7 epfr27.bit._D7\r
+#define EPFR27_D6 epfr27.bit._D6\r
+#define EPFR27_D5 epfr27.bit._D5\r
+#define EPFR27_D4 epfr27.bit._D4\r
+#define EPFR27_D3 epfr27.bit._D3\r
+#define EPFR27_D2 epfr27.bit._D2\r
+#define EPFR27_D1 epfr27.bit._D1\r
+#define EPFR27_D0 epfr27.bit._D0\r
+__IO_EXTERN PODR00STR podr00;   /* R-bus Port Output Drive Select Register */\r
+#define PODR00 podr00.byte\r
+#define PODR00_D7 podr00.bit._D7\r
+#define PODR00_D6 podr00.bit._D6\r
+#define PODR00_D5 podr00.bit._D5\r
+#define PODR00_D4 podr00.bit._D4\r
+#define PODR00_D3 podr00.bit._D3\r
+#define PODR00_D2 podr00.bit._D2\r
+#define PODR00_D1 podr00.bit._D1\r
+#define PODR00_D0 podr00.bit._D0\r
+__IO_EXTERN PODR01STR podr01;  \r
+#define PODR01 podr01.byte\r
+#define PODR01_D7 podr01.bit._D7\r
+#define PODR01_D6 podr01.bit._D6\r
+#define PODR01_D5 podr01.bit._D5\r
+#define PODR01_D4 podr01.bit._D4\r
+#define PODR01_D3 podr01.bit._D3\r
+#define PODR01_D2 podr01.bit._D2\r
+#define PODR01_D1 podr01.bit._D1\r
+#define PODR01_D0 podr01.bit._D0\r
+__IO_EXTERN PODR02STR podr02;  \r
+#define PODR02 podr02.byte\r
+#define PODR02_D7 podr02.bit._D7\r
+#define PODR02_D6 podr02.bit._D6\r
+#define PODR02_D5 podr02.bit._D5\r
+#define PODR02_D4 podr02.bit._D4\r
+#define PODR02_D3 podr02.bit._D3\r
+#define PODR02_D2 podr02.bit._D2\r
+#define PODR02_D1 podr02.bit._D1\r
+#define PODR02_D0 podr02.bit._D0\r
+__IO_EXTERN PODR03STR podr03;  \r
+#define PODR03 podr03.byte\r
+#define PODR03_D7 podr03.bit._D7\r
+#define PODR03_D6 podr03.bit._D6\r
+#define PODR03_D5 podr03.bit._D5\r
+#define PODR03_D4 podr03.bit._D4\r
+#define PODR03_D3 podr03.bit._D3\r
+#define PODR03_D2 podr03.bit._D2\r
+#define PODR03_D1 podr03.bit._D1\r
+#define PODR03_D0 podr03.bit._D0\r
+__IO_EXTERN PODR04STR podr04;  \r
+#define PODR04 podr04.byte\r
+#define PODR04_D1 podr04.bit._D1\r
+#define PODR04_D0 podr04.bit._D0\r
+__IO_EXTERN PODR05STR podr05;  \r
+#define PODR05 podr05.byte\r
+#define PODR05_D7 podr05.bit._D7\r
+#define PODR05_D6 podr05.bit._D6\r
+#define PODR05_D5 podr05.bit._D5\r
+#define PODR05_D4 podr05.bit._D4\r
+#define PODR05_D3 podr05.bit._D3\r
+#define PODR05_D2 podr05.bit._D2\r
+#define PODR05_D1 podr05.bit._D1\r
+#define PODR05_D0 podr05.bit._D0\r
+__IO_EXTERN PODR06STR podr06;  \r
+#define PODR06 podr06.byte\r
+#define PODR06_D7 podr06.bit._D7\r
+#define PODR06_D6 podr06.bit._D6\r
+#define PODR06_D5 podr06.bit._D5\r
+#define PODR06_D4 podr06.bit._D4\r
+#define PODR06_D3 podr06.bit._D3\r
+#define PODR06_D2 podr06.bit._D2\r
+#define PODR06_D1 podr06.bit._D1\r
+#define PODR06_D0 podr06.bit._D0\r
+__IO_EXTERN PODR07STR podr07;  \r
+#define PODR07 podr07.byte\r
+#define PODR07_D7 podr07.bit._D7\r
+#define PODR07_D6 podr07.bit._D6\r
+#define PODR07_D5 podr07.bit._D5\r
+#define PODR07_D4 podr07.bit._D4\r
+#define PODR07_D3 podr07.bit._D3\r
+#define PODR07_D2 podr07.bit._D2\r
+#define PODR07_D1 podr07.bit._D1\r
+#define PODR07_D0 podr07.bit._D0\r
+__IO_EXTERN PODR08STR podr08;  \r
+#define PODR08 podr08.byte\r
+#define PODR08_D7 podr08.bit._D7\r
+#define PODR08_D6 podr08.bit._D6\r
+#define PODR08_D5 podr08.bit._D5\r
+#define PODR08_D4 podr08.bit._D4\r
+#define PODR08_D3 podr08.bit._D3\r
+#define PODR08_D2 podr08.bit._D2\r
+#define PODR08_D1 podr08.bit._D1\r
+#define PODR08_D0 podr08.bit._D0\r
+__IO_EXTERN PODR09STR podr09;  \r
+#define PODR09 podr09.byte\r
+#define PODR09_D7 podr09.bit._D7\r
+#define PODR09_D6 podr09.bit._D6\r
+#define PODR09_D3 podr09.bit._D3\r
+#define PODR09_D2 podr09.bit._D2\r
+#define PODR09_D1 podr09.bit._D1\r
+#define PODR09_D0 podr09.bit._D0\r
+__IO_EXTERN PODR10STR podr10;  \r
+#define PODR10 podr10.byte\r
+#define PODR10_D6 podr10.bit._D6\r
+#define PODR10_D5 podr10.bit._D5\r
+#define PODR10_D4 podr10.bit._D4\r
+#define PODR10_D3 podr10.bit._D3\r
+#define PODR10_D2 podr10.bit._D2\r
+#define PODR10_D1 podr10.bit._D1\r
+__IO_EXTERN PODR13STR podr13;  \r
+#define PODR13 podr13.byte\r
+#define PODR13_D2 podr13.bit._D2\r
+#define PODR13_D1 podr13.bit._D1\r
+#define PODR13_D0 podr13.bit._D0\r
+__IO_EXTERN PODR14STR podr14;  \r
+#define PODR14 podr14.byte\r
+#define PODR14_D7 podr14.bit._D7\r
+#define PODR14_D6 podr14.bit._D6\r
+#define PODR14_D5 podr14.bit._D5\r
+#define PODR14_D4 podr14.bit._D4\r
+#define PODR14_D3 podr14.bit._D3\r
+#define PODR14_D2 podr14.bit._D2\r
+#define PODR14_D1 podr14.bit._D1\r
+#define PODR14_D0 podr14.bit._D0\r
+__IO_EXTERN PODR15STR podr15;  \r
+#define PODR15 podr15.byte\r
+#define PODR15_D3 podr15.bit._D3\r
+#define PODR15_D2 podr15.bit._D2\r
+#define PODR15_D1 podr15.bit._D1\r
+#define PODR15_D0 podr15.bit._D0\r
+__IO_EXTERN PODR16STR podr16;  \r
+#define PODR16 podr16.byte\r
+#define PODR16_D7 podr16.bit._D7\r
+#define PODR16_D6 podr16.bit._D6\r
+#define PODR16_D5 podr16.bit._D5\r
+#define PODR16_D4 podr16.bit._D4\r
+#define PODR16_D3 podr16.bit._D3\r
+#define PODR16_D2 podr16.bit._D2\r
+#define PODR16_D1 podr16.bit._D1\r
+#define PODR16_D0 podr16.bit._D0\r
+__IO_EXTERN PODR17STR podr17;  \r
+#define PODR17 podr17.byte\r
+#define PODR17_D7 podr17.bit._D7\r
+#define PODR17_D6 podr17.bit._D6\r
+#define PODR17_D5 podr17.bit._D5\r
+#define PODR17_D4 podr17.bit._D4\r
+__IO_EXTERN PODR18STR podr18;  \r
+#define PODR18 podr18.byte\r
+#define PODR18_D6 podr18.bit._D6\r
+#define PODR18_D5 podr18.bit._D5\r
+#define PODR18_D4 podr18.bit._D4\r
+#define PODR18_D2 podr18.bit._D2\r
+#define PODR18_D1 podr18.bit._D1\r
+#define PODR18_D0 podr18.bit._D0\r
+__IO_EXTERN PODR19STR podr19;  \r
+#define PODR19 podr19.byte\r
+#define PODR19_D6 podr19.bit._D6\r
+#define PODR19_D5 podr19.bit._D5\r
+#define PODR19_D4 podr19.bit._D4\r
+#define PODR19_D2 podr19.bit._D2\r
+#define PODR19_D1 podr19.bit._D1\r
+#define PODR19_D0 podr19.bit._D0\r
+__IO_EXTERN PODR20STR podr20;  \r
+#define PODR20 podr20.byte\r
+#define PODR20_D2 podr20.bit._D2\r
+#define PODR20_D1 podr20.bit._D1\r
+#define PODR20_D0 podr20.bit._D0\r
+__IO_EXTERN PODR22STR podr22;  \r
+#define PODR22 podr22.byte\r
+#define PODR22_D5 podr22.bit._D5\r
+#define PODR22_D4 podr22.bit._D4\r
+#define PODR22_D2 podr22.bit._D2\r
+#define PODR22_D0 podr22.bit._D0\r
+__IO_EXTERN PODR23STR podr23;  \r
+#define PODR23 podr23.byte\r
+#define PODR23_D5 podr23.bit._D5\r
+#define PODR23_D4 podr23.bit._D4\r
+#define PODR23_D3 podr23.bit._D3\r
+#define PODR23_D2 podr23.bit._D2\r
+#define PODR23_D1 podr23.bit._D1\r
+#define PODR23_D0 podr23.bit._D0\r
+__IO_EXTERN PODR24STR podr24;  \r
+#define PODR24 podr24.byte\r
+#define PODR24_D7 podr24.bit._D7\r
+#define PODR24_D6 podr24.bit._D6\r
+#define PODR24_D5 podr24.bit._D5\r
+#define PODR24_D4 podr24.bit._D4\r
+#define PODR24_D3 podr24.bit._D3\r
+#define PODR24_D2 podr24.bit._D2\r
+#define PODR24_D1 podr24.bit._D1\r
+#define PODR24_D0 podr24.bit._D0\r
+__IO_EXTERN PODR25STR podr25;  \r
+#define PODR25 podr25.byte\r
+#define PODR25_D7 podr25.bit._D7\r
+#define PODR25_D6 podr25.bit._D6\r
+#define PODR25_D5 podr25.bit._D5\r
+#define PODR25_D4 podr25.bit._D4\r
+#define PODR25_D3 podr25.bit._D3\r
+#define PODR25_D2 podr25.bit._D2\r
+#define PODR25_D1 podr25.bit._D1\r
+#define PODR25_D0 podr25.bit._D0\r
+__IO_EXTERN PODR26STR podr26;  \r
+#define PODR26 podr26.byte\r
+#define PODR26_D7 podr26.bit._D7\r
+#define PODR26_D6 podr26.bit._D6\r
+#define PODR26_D5 podr26.bit._D5\r
+#define PODR26_D4 podr26.bit._D4\r
+#define PODR26_D3 podr26.bit._D3\r
+#define PODR26_D2 podr26.bit._D2\r
+#define PODR26_D1 podr26.bit._D1\r
+#define PODR26_D0 podr26.bit._D0\r
+__IO_EXTERN PODR27STR podr27;  \r
+#define PODR27 podr27.byte\r
+#define PODR27_D7 podr27.bit._D7\r
+#define PODR27_D6 podr27.bit._D6\r
+#define PODR27_D5 podr27.bit._D5\r
+#define PODR27_D4 podr27.bit._D4\r
+#define PODR27_D3 podr27.bit._D3\r
+#define PODR27_D2 podr27.bit._D2\r
+#define PODR27_D1 podr27.bit._D1\r
+#define PODR27_D0 podr27.bit._D0\r
+__IO_EXTERN PODR29STR podr29;  \r
+#define PODR29 podr29.byte\r
+#define PODR29_D7 podr29.bit._D7\r
+#define PODR29_D6 podr29.bit._D6\r
+#define PODR29_D5 podr29.bit._D5\r
+#define PODR29_D4 podr29.bit._D4\r
+#define PODR29_D3 podr29.bit._D3\r
+#define PODR29_D2 podr29.bit._D2\r
+#define PODR29_D1 podr29.bit._D1\r
+#define PODR29_D0 podr29.bit._D0\r
+__IO_EXTERN PILR00STR pilr00;   /* R-bus Port Input Level Select Register */\r
+#define PILR00 pilr00.byte\r
+#define PILR00_D7 pilr00.bit._D7\r
+#define PILR00_D6 pilr00.bit._D6\r
+#define PILR00_D5 pilr00.bit._D5\r
+#define PILR00_D4 pilr00.bit._D4\r
+#define PILR00_D3 pilr00.bit._D3\r
+#define PILR00_D2 pilr00.bit._D2\r
+#define PILR00_D1 pilr00.bit._D1\r
+#define PILR00_D0 pilr00.bit._D0\r
+__IO_EXTERN PILR01STR pilr01;  \r
+#define PILR01 pilr01.byte\r
+#define PILR01_D7 pilr01.bit._D7\r
+#define PILR01_D6 pilr01.bit._D6\r
+#define PILR01_D5 pilr01.bit._D5\r
+#define PILR01_D4 pilr01.bit._D4\r
+#define PILR01_D3 pilr01.bit._D3\r
+#define PILR01_D2 pilr01.bit._D2\r
+#define PILR01_D1 pilr01.bit._D1\r
+#define PILR01_D0 pilr01.bit._D0\r
+__IO_EXTERN PILR02STR pilr02;  \r
+#define PILR02 pilr02.byte\r
+#define PILR02_D7 pilr02.bit._D7\r
+#define PILR02_D6 pilr02.bit._D6\r
+#define PILR02_D5 pilr02.bit._D5\r
+#define PILR02_D4 pilr02.bit._D4\r
+#define PILR02_D3 pilr02.bit._D3\r
+#define PILR02_D2 pilr02.bit._D2\r
+#define PILR02_D1 pilr02.bit._D1\r
+#define PILR02_D0 pilr02.bit._D0\r
+__IO_EXTERN PILR03STR pilr03;  \r
+#define PILR03 pilr03.byte\r
+#define PILR03_D7 pilr03.bit._D7\r
+#define PILR03_D6 pilr03.bit._D6\r
+#define PILR03_D5 pilr03.bit._D5\r
+#define PILR03_D4 pilr03.bit._D4\r
+#define PILR03_D3 pilr03.bit._D3\r
+#define PILR03_D2 pilr03.bit._D2\r
+#define PILR03_D1 pilr03.bit._D1\r
+#define PILR03_D0 pilr03.bit._D0\r
+__IO_EXTERN PILR04STR pilr04;  \r
+#define PILR04 pilr04.byte\r
+#define PILR04_D1 pilr04.bit._D1\r
+#define PILR04_D0 pilr04.bit._D0\r
+__IO_EXTERN PILR05STR pilr05;  \r
+#define PILR05 pilr05.byte\r
+#define PILR05_D7 pilr05.bit._D7\r
+#define PILR05_D6 pilr05.bit._D6\r
+#define PILR05_D5 pilr05.bit._D5\r
+#define PILR05_D4 pilr05.bit._D4\r
+#define PILR05_D3 pilr05.bit._D3\r
+#define PILR05_D2 pilr05.bit._D2\r
+#define PILR05_D1 pilr05.bit._D1\r
+#define PILR05_D0 pilr05.bit._D0\r
+__IO_EXTERN PILR06STR pilr06;  \r
+#define PILR06 pilr06.byte\r
+#define PILR06_D7 pilr06.bit._D7\r
+#define PILR06_D6 pilr06.bit._D6\r
+#define PILR06_D5 pilr06.bit._D5\r
+#define PILR06_D4 pilr06.bit._D4\r
+#define PILR06_D3 pilr06.bit._D3\r
+#define PILR06_D2 pilr06.bit._D2\r
+#define PILR06_D1 pilr06.bit._D1\r
+#define PILR06_D0 pilr06.bit._D0\r
+__IO_EXTERN PILR07STR pilr07;  \r
+#define PILR07 pilr07.byte\r
+#define PILR07_D7 pilr07.bit._D7\r
+#define PILR07_D6 pilr07.bit._D6\r
+#define PILR07_D5 pilr07.bit._D5\r
+#define PILR07_D4 pilr07.bit._D4\r
+#define PILR07_D3 pilr07.bit._D3\r
+#define PILR07_D2 pilr07.bit._D2\r
+#define PILR07_D1 pilr07.bit._D1\r
+#define PILR07_D0 pilr07.bit._D0\r
+__IO_EXTERN PILR08STR pilr08;  \r
+#define PILR08 pilr08.byte\r
+#define PILR08_D7 pilr08.bit._D7\r
+#define PILR08_D6 pilr08.bit._D6\r
+#define PILR08_D5 pilr08.bit._D5\r
+#define PILR08_D4 pilr08.bit._D4\r
+#define PILR08_D3 pilr08.bit._D3\r
+#define PILR08_D2 pilr08.bit._D2\r
+#define PILR08_D1 pilr08.bit._D1\r
+#define PILR08_D0 pilr08.bit._D0\r
+__IO_EXTERN PILR09STR pilr09;  \r
+#define PILR09 pilr09.byte\r
+#define PILR09_D7 pilr09.bit._D7\r
+#define PILR09_D6 pilr09.bit._D6\r
+#define PILR09_D3 pilr09.bit._D3\r
+#define PILR09_D2 pilr09.bit._D2\r
+#define PILR09_D1 pilr09.bit._D1\r
+#define PILR09_D0 pilr09.bit._D0\r
+__IO_EXTERN PILR10STR pilr10;  \r
+#define PILR10 pilr10.byte\r
+#define PILR10_D6 pilr10.bit._D6\r
+#define PILR10_D5 pilr10.bit._D5\r
+#define PILR10_D4 pilr10.bit._D4\r
+#define PILR10_D3 pilr10.bit._D3\r
+#define PILR10_D2 pilr10.bit._D2\r
+#define PILR10_D1 pilr10.bit._D1\r
+__IO_EXTERN PILR13STR pilr13;  \r
+#define PILR13 pilr13.byte\r
+#define PILR13_D2 pilr13.bit._D2\r
+#define PILR13_D1 pilr13.bit._D1\r
+#define PILR13_D0 pilr13.bit._D0\r
+__IO_EXTERN PILR14STR pilr14;  \r
+#define PILR14 pilr14.byte\r
+#define PILR14_D7 pilr14.bit._D7\r
+#define PILR14_D6 pilr14.bit._D6\r
+#define PILR14_D5 pilr14.bit._D5\r
+#define PILR14_D4 pilr14.bit._D4\r
+#define PILR14_D3 pilr14.bit._D3\r
+#define PILR14_D2 pilr14.bit._D2\r
+#define PILR14_D1 pilr14.bit._D1\r
+#define PILR14_D0 pilr14.bit._D0\r
+__IO_EXTERN PILR15STR pilr15;  \r
+#define PILR15 pilr15.byte\r
+#define PILR15_D3 pilr15.bit._D3\r
+#define PILR15_D2 pilr15.bit._D2\r
+#define PILR15_D1 pilr15.bit._D1\r
+#define PILR15_D0 pilr15.bit._D0\r
+__IO_EXTERN PILR16STR pilr16;  \r
+#define PILR16 pilr16.byte\r
+#define PILR16_D7 pilr16.bit._D7\r
+#define PILR16_D6 pilr16.bit._D6\r
+#define PILR16_D5 pilr16.bit._D5\r
+#define PILR16_D4 pilr16.bit._D4\r
+#define PILR16_D3 pilr16.bit._D3\r
+#define PILR16_D2 pilr16.bit._D2\r
+#define PILR16_D1 pilr16.bit._D1\r
+#define PILR16_D0 pilr16.bit._D0\r
+__IO_EXTERN PILR17STR pilr17;  \r
+#define PILR17 pilr17.byte\r
+#define PILR17_D7 pilr17.bit._D7\r
+#define PILR17_D6 pilr17.bit._D6\r
+#define PILR17_D5 pilr17.bit._D5\r
+#define PILR17_D4 pilr17.bit._D4\r
+__IO_EXTERN PILR18STR pilr18;  \r
+#define PILR18 pilr18.byte\r
+#define PILR18_D6 pilr18.bit._D6\r
+#define PILR18_D5 pilr18.bit._D5\r
+#define PILR18_D4 pilr18.bit._D4\r
+#define PILR18_D2 pilr18.bit._D2\r
+#define PILR18_D1 pilr18.bit._D1\r
+#define PILR18_D0 pilr18.bit._D0\r
+__IO_EXTERN PILR19STR pilr19;  \r
+#define PILR19 pilr19.byte\r
+#define PILR19_D6 pilr19.bit._D6\r
+#define PILR19_D5 pilr19.bit._D5\r
+#define PILR19_D4 pilr19.bit._D4\r
+#define PILR19_D2 pilr19.bit._D2\r
+#define PILR19_D1 pilr19.bit._D1\r
+#define PILR19_D0 pilr19.bit._D0\r
+__IO_EXTERN PILR20STR pilr20;  \r
+#define PILR20 pilr20.byte\r
+#define PILR20_D2 pilr20.bit._D2\r
+#define PILR20_D1 pilr20.bit._D1\r
+#define PILR20_D0 pilr20.bit._D0\r
+__IO_EXTERN PILR22STR pilr22;  \r
+#define PILR22 pilr22.byte\r
+#define PILR22_D5 pilr22.bit._D5\r
+#define PILR22_D4 pilr22.bit._D4\r
+#define PILR22_D2 pilr22.bit._D2\r
+#define PILR22_D0 pilr22.bit._D0\r
+__IO_EXTERN PILR23STR pilr23;  \r
+#define PILR23 pilr23.byte\r
+#define PILR23_D5 pilr23.bit._D5\r
+#define PILR23_D4 pilr23.bit._D4\r
+#define PILR23_D3 pilr23.bit._D3\r
+#define PILR23_D2 pilr23.bit._D2\r
+#define PILR23_D1 pilr23.bit._D1\r
+#define PILR23_D0 pilr23.bit._D0\r
+__IO_EXTERN PILR24STR pilr24;  \r
+#define PILR24 pilr24.byte\r
+#define PILR24_D7 pilr24.bit._D7\r
+#define PILR24_D6 pilr24.bit._D6\r
+#define PILR24_D5 pilr24.bit._D5\r
+#define PILR24_D4 pilr24.bit._D4\r
+#define PILR24_D3 pilr24.bit._D3\r
+#define PILR24_D2 pilr24.bit._D2\r
+#define PILR24_D1 pilr24.bit._D1\r
+#define PILR24_D0 pilr24.bit._D0\r
+__IO_EXTERN PILR25STR pilr25;  \r
+#define PILR25 pilr25.byte\r
+#define PILR25_D7 pilr25.bit._D7\r
+#define PILR25_D6 pilr25.bit._D6\r
+#define PILR25_D5 pilr25.bit._D5\r
+#define PILR25_D4 pilr25.bit._D4\r
+#define PILR25_D3 pilr25.bit._D3\r
+#define PILR25_D2 pilr25.bit._D2\r
+#define PILR25_D1 pilr25.bit._D1\r
+#define PILR25_D0 pilr25.bit._D0\r
+__IO_EXTERN PILR26STR pilr26;  \r
+#define PILR26 pilr26.byte\r
+#define PILR26_D7 pilr26.bit._D7\r
+#define PILR26_D6 pilr26.bit._D6\r
+#define PILR26_D5 pilr26.bit._D5\r
+#define PILR26_D4 pilr26.bit._D4\r
+#define PILR26_D3 pilr26.bit._D3\r
+#define PILR26_D2 pilr26.bit._D2\r
+#define PILR26_D1 pilr26.bit._D1\r
+#define PILR26_D0 pilr26.bit._D0\r
+__IO_EXTERN PILR27STR pilr27;  \r
+#define PILR27 pilr27.byte\r
+#define PILR27_D7 pilr27.bit._D7\r
+#define PILR27_D6 pilr27.bit._D6\r
+#define PILR27_D5 pilr27.bit._D5\r
+#define PILR27_D4 pilr27.bit._D4\r
+#define PILR27_D3 pilr27.bit._D3\r
+#define PILR27_D2 pilr27.bit._D2\r
+#define PILR27_D1 pilr27.bit._D1\r
+#define PILR27_D0 pilr27.bit._D0\r
+__IO_EXTERN PILR29STR pilr29;  \r
+#define PILR29 pilr29.byte\r
+#define PILR29_D7 pilr29.bit._D7\r
+#define PILR29_D6 pilr29.bit._D6\r
+#define PILR29_D5 pilr29.bit._D5\r
+#define PILR29_D4 pilr29.bit._D4\r
+#define PILR29_D3 pilr29.bit._D3\r
+#define PILR29_D2 pilr29.bit._D2\r
+#define PILR29_D1 pilr29.bit._D1\r
+#define PILR29_D0 pilr29.bit._D0\r
+__IO_EXTERN EPILR00STR epilr00;   /* R-bus Port Extra Input Level Select Register */\r
+#define EPILR00 epilr00.byte\r
+#define EPILR00_D7 epilr00.bit._D7\r
+#define EPILR00_D6 epilr00.bit._D6\r
+#define EPILR00_D5 epilr00.bit._D5\r
+#define EPILR00_D4 epilr00.bit._D4\r
+#define EPILR00_D3 epilr00.bit._D3\r
+#define EPILR00_D2 epilr00.bit._D2\r
+#define EPILR00_D1 epilr00.bit._D1\r
+#define EPILR00_D0 epilr00.bit._D0\r
+__IO_EXTERN EPILR01STR epilr01;  \r
+#define EPILR01 epilr01.byte\r
+#define EPILR01_D7 epilr01.bit._D7\r
+#define EPILR01_D6 epilr01.bit._D6\r
+#define EPILR01_D5 epilr01.bit._D5\r
+#define EPILR01_D4 epilr01.bit._D4\r
+#define EPILR01_D3 epilr01.bit._D3\r
+#define EPILR01_D2 epilr01.bit._D2\r
+#define EPILR01_D1 epilr01.bit._D1\r
+#define EPILR01_D0 epilr01.bit._D0\r
+__IO_EXTERN EPILR02STR epilr02;  \r
+#define EPILR02 epilr02.byte\r
+#define EPILR02_D7 epilr02.bit._D7\r
+#define EPILR02_D6 epilr02.bit._D6\r
+#define EPILR02_D5 epilr02.bit._D5\r
+#define EPILR02_D4 epilr02.bit._D4\r
+#define EPILR02_D3 epilr02.bit._D3\r
+#define EPILR02_D2 epilr02.bit._D2\r
+#define EPILR02_D1 epilr02.bit._D1\r
+#define EPILR02_D0 epilr02.bit._D0\r
+__IO_EXTERN EPILR03STR epilr03;  \r
+#define EPILR03 epilr03.byte\r
+#define EPILR03_D7 epilr03.bit._D7\r
+#define EPILR03_D6 epilr03.bit._D6\r
+#define EPILR03_D5 epilr03.bit._D5\r
+#define EPILR03_D4 epilr03.bit._D4\r
+#define EPILR03_D3 epilr03.bit._D3\r
+#define EPILR03_D2 epilr03.bit._D2\r
+#define EPILR03_D1 epilr03.bit._D1\r
+#define EPILR03_D0 epilr03.bit._D0\r
+__IO_EXTERN EPILR04STR epilr04;  \r
+#define EPILR04 epilr04.byte\r
+#define EPILR04_D1 epilr04.bit._D1\r
+#define EPILR04_D0 epilr04.bit._D0\r
+__IO_EXTERN EPILR05STR epilr05;  \r
+#define EPILR05 epilr05.byte\r
+#define EPILR05_D7 epilr05.bit._D7\r
+#define EPILR05_D6 epilr05.bit._D6\r
+#define EPILR05_D5 epilr05.bit._D5\r
+#define EPILR05_D4 epilr05.bit._D4\r
+#define EPILR05_D3 epilr05.bit._D3\r
+#define EPILR05_D2 epilr05.bit._D2\r
+#define EPILR05_D1 epilr05.bit._D1\r
+#define EPILR05_D0 epilr05.bit._D0\r
+__IO_EXTERN EPILR06STR epilr06;  \r
+#define EPILR06 epilr06.byte\r
+#define EPILR06_D7 epilr06.bit._D7\r
+#define EPILR06_D6 epilr06.bit._D6\r
+#define EPILR06_D5 epilr06.bit._D5\r
+#define EPILR06_D4 epilr06.bit._D4\r
+#define EPILR06_D3 epilr06.bit._D3\r
+#define EPILR06_D2 epilr06.bit._D2\r
+#define EPILR06_D1 epilr06.bit._D1\r
+#define EPILR06_D0 epilr06.bit._D0\r
+__IO_EXTERN EPILR07STR epilr07;  \r
+#define EPILR07 epilr07.byte\r
+#define EPILR07_D7 epilr07.bit._D7\r
+#define EPILR07_D6 epilr07.bit._D6\r
+#define EPILR07_D5 epilr07.bit._D5\r
+#define EPILR07_D4 epilr07.bit._D4\r
+#define EPILR07_D3 epilr07.bit._D3\r
+#define EPILR07_D2 epilr07.bit._D2\r
+#define EPILR07_D1 epilr07.bit._D1\r
+#define EPILR07_D0 epilr07.bit._D0\r
+__IO_EXTERN EPILR08STR epilr08;  \r
+#define EPILR08 epilr08.byte\r
+#define EPILR08_D7 epilr08.bit._D7\r
+#define EPILR08_D6 epilr08.bit._D6\r
+#define EPILR08_D5 epilr08.bit._D5\r
+#define EPILR08_D4 epilr08.bit._D4\r
+#define EPILR08_D3 epilr08.bit._D3\r
+#define EPILR08_D2 epilr08.bit._D2\r
+#define EPILR08_D1 epilr08.bit._D1\r
+#define EPILR08_D0 epilr08.bit._D0\r
+__IO_EXTERN EPILR09STR epilr09;  \r
+#define EPILR09 epilr09.byte\r
+#define EPILR09_D7 epilr09.bit._D7\r
+#define EPILR09_D6 epilr09.bit._D6\r
+#define EPILR09_D3 epilr09.bit._D3\r
+#define EPILR09_D2 epilr09.bit._D2\r
+#define EPILR09_D1 epilr09.bit._D1\r
+#define EPILR09_D0 epilr09.bit._D0\r
+__IO_EXTERN EPILR10STR epilr10;  \r
+#define EPILR10 epilr10.byte\r
+#define EPILR10_D6 epilr10.bit._D6\r
+#define EPILR10_D5 epilr10.bit._D5\r
+#define EPILR10_D4 epilr10.bit._D4\r
+#define EPILR10_D3 epilr10.bit._D3\r
+#define EPILR10_D2 epilr10.bit._D2\r
+#define EPILR10_D1 epilr10.bit._D1\r
+__IO_EXTERN EPILR13STR epilr13;  \r
+#define EPILR13 epilr13.byte\r
+#define EPILR13_D2 epilr13.bit._D2\r
+#define EPILR13_D1 epilr13.bit._D1\r
+#define EPILR13_D0 epilr13.bit._D0\r
+__IO_EXTERN EPILR14STR epilr14;  \r
+#define EPILR14 epilr14.byte\r
+#define EPILR14_D7 epilr14.bit._D7\r
+#define EPILR14_D6 epilr14.bit._D6\r
+#define EPILR14_D5 epilr14.bit._D5\r
+#define EPILR14_D4 epilr14.bit._D4\r
+#define EPILR14_D3 epilr14.bit._D3\r
+#define EPILR14_D2 epilr14.bit._D2\r
+#define EPILR14_D1 epilr14.bit._D1\r
+#define EPILR14_D0 epilr14.bit._D0\r
+__IO_EXTERN EPILR15STR epilr15;  \r
+#define EPILR15 epilr15.byte\r
+#define EPILR15_D3 epilr15.bit._D3\r
+#define EPILR15_D2 epilr15.bit._D2\r
+#define EPILR15_D1 epilr15.bit._D1\r
+#define EPILR15_D0 epilr15.bit._D0\r
+__IO_EXTERN EPILR16STR epilr16;  \r
+#define EPILR16 epilr16.byte\r
+#define EPILR16_D7 epilr16.bit._D7\r
+#define EPILR16_D6 epilr16.bit._D6\r
+#define EPILR16_D5 epilr16.bit._D5\r
+#define EPILR16_D4 epilr16.bit._D4\r
+#define EPILR16_D3 epilr16.bit._D3\r
+#define EPILR16_D2 epilr16.bit._D2\r
+#define EPILR16_D1 epilr16.bit._D1\r
+#define EPILR16_D0 epilr16.bit._D0\r
+__IO_EXTERN EPILR17STR epilr17;  \r
+#define EPILR17 epilr17.byte\r
+#define EPILR17_D7 epilr17.bit._D7\r
+#define EPILR17_D6 epilr17.bit._D6\r
+#define EPILR17_D5 epilr17.bit._D5\r
+#define EPILR17_D4 epilr17.bit._D4\r
+__IO_EXTERN EPILR18STR epilr18;  \r
+#define EPILR18 epilr18.byte\r
+#define EPILR18_D6 epilr18.bit._D6\r
+#define EPILR18_D5 epilr18.bit._D5\r
+#define EPILR18_D4 epilr18.bit._D4\r
+#define EPILR18_D2 epilr18.bit._D2\r
+#define EPILR18_D1 epilr18.bit._D1\r
+#define EPILR18_D0 epilr18.bit._D0\r
+__IO_EXTERN EPILR19STR epilr19;  \r
+#define EPILR19 epilr19.byte\r
+#define EPILR19_D6 epilr19.bit._D6\r
+#define EPILR19_D5 epilr19.bit._D5\r
+#define EPILR19_D4 epilr19.bit._D4\r
+#define EPILR19_D2 epilr19.bit._D2\r
+#define EPILR19_D1 epilr19.bit._D1\r
+#define EPILR19_D0 epilr19.bit._D0\r
+__IO_EXTERN EPILR20STR epilr20;  \r
+#define EPILR20 epilr20.byte\r
+#define EPILR20_D2 epilr20.bit._D2\r
+#define EPILR20_D1 epilr20.bit._D1\r
+#define EPILR20_D0 epilr20.bit._D0\r
+__IO_EXTERN EPILR22STR epilr22;  \r
+#define EPILR22 epilr22.byte\r
+#define EPILR22_D5 epilr22.bit._D5\r
+#define EPILR22_D4 epilr22.bit._D4\r
+#define EPILR22_D2 epilr22.bit._D2\r
+#define EPILR22_D0 epilr22.bit._D0\r
+__IO_EXTERN EPILR23STR epilr23;  \r
+#define EPILR23 epilr23.byte\r
+#define EPILR23_D5 epilr23.bit._D5\r
+#define EPILR23_D4 epilr23.bit._D4\r
+#define EPILR23_D3 epilr23.bit._D3\r
+#define EPILR23_D2 epilr23.bit._D2\r
+#define EPILR23_D1 epilr23.bit._D1\r
+#define EPILR23_D0 epilr23.bit._D0\r
+__IO_EXTERN EPILR24STR epilr24;  \r
+#define EPILR24 epilr24.byte\r
+#define EPILR24_D7 epilr24.bit._D7\r
+#define EPILR24_D6 epilr24.bit._D6\r
+#define EPILR24_D5 epilr24.bit._D5\r
+#define EPILR24_D4 epilr24.bit._D4\r
+#define EPILR24_D3 epilr24.bit._D3\r
+#define EPILR24_D2 epilr24.bit._D2\r
+#define EPILR24_D1 epilr24.bit._D1\r
+#define EPILR24_D0 epilr24.bit._D0\r
+__IO_EXTERN EPILR25STR epilr25;  \r
+#define EPILR25 epilr25.byte\r
+#define EPILR25_D7 epilr25.bit._D7\r
+#define EPILR25_D6 epilr25.bit._D6\r
+#define EPILR25_D5 epilr25.bit._D5\r
+#define EPILR25_D4 epilr25.bit._D4\r
+#define EPILR25_D3 epilr25.bit._D3\r
+#define EPILR25_D2 epilr25.bit._D2\r
+#define EPILR25_D1 epilr25.bit._D1\r
+#define EPILR25_D0 epilr25.bit._D0\r
+__IO_EXTERN EPILR26STR epilr26;  \r
+#define EPILR26 epilr26.byte\r
+#define EPILR26_D7 epilr26.bit._D7\r
+#define EPILR26_D6 epilr26.bit._D6\r
+#define EPILR26_D5 epilr26.bit._D5\r
+#define EPILR26_D4 epilr26.bit._D4\r
+#define EPILR26_D3 epilr26.bit._D3\r
+#define EPILR26_D2 epilr26.bit._D2\r
+#define EPILR26_D1 epilr26.bit._D1\r
+#define EPILR26_D0 epilr26.bit._D0\r
+__IO_EXTERN EPILR27STR epilr27;  \r
+#define EPILR27 epilr27.byte\r
+#define EPILR27_D7 epilr27.bit._D7\r
+#define EPILR27_D6 epilr27.bit._D6\r
+#define EPILR27_D5 epilr27.bit._D5\r
+#define EPILR27_D4 epilr27.bit._D4\r
+#define EPILR27_D3 epilr27.bit._D3\r
+#define EPILR27_D2 epilr27.bit._D2\r
+#define EPILR27_D1 epilr27.bit._D1\r
+#define EPILR27_D0 epilr27.bit._D0\r
+__IO_EXTERN EPILR29STR epilr29;  \r
+#define EPILR29 epilr29.byte\r
+#define EPILR29_D7 epilr29.bit._D7\r
+#define EPILR29_D6 epilr29.bit._D6\r
+#define EPILR29_D5 epilr29.bit._D5\r
+#define EPILR29_D4 epilr29.bit._D4\r
+#define EPILR29_D3 epilr29.bit._D3\r
+#define EPILR29_D2 epilr29.bit._D2\r
+#define EPILR29_D1 epilr29.bit._D1\r
+#define EPILR29_D0 epilr29.bit._D0\r
+__IO_EXTERN PPER00STR pper00;   /* R-bus Port Pull-Up/Down  Enable Register */\r
+#define PPER00 pper00.byte\r
+#define PPER00_D7 pper00.bit._D7\r
+#define PPER00_D6 pper00.bit._D6\r
+#define PPER00_D5 pper00.bit._D5\r
+#define PPER00_D4 pper00.bit._D4\r
+#define PPER00_D3 pper00.bit._D3\r
+#define PPER00_D2 pper00.bit._D2\r
+#define PPER00_D1 pper00.bit._D1\r
+#define PPER00_D0 pper00.bit._D0\r
+__IO_EXTERN PPER01STR pper01;  \r
+#define PPER01 pper01.byte\r
+#define PPER01_D7 pper01.bit._D7\r
+#define PPER01_D6 pper01.bit._D6\r
+#define PPER01_D5 pper01.bit._D5\r
+#define PPER01_D4 pper01.bit._D4\r
+#define PPER01_D3 pper01.bit._D3\r
+#define PPER01_D2 pper01.bit._D2\r
+#define PPER01_D1 pper01.bit._D1\r
+#define PPER01_D0 pper01.bit._D0\r
+__IO_EXTERN PPER02STR pper02;  \r
+#define PPER02 pper02.byte\r
+#define PPER02_D7 pper02.bit._D7\r
+#define PPER02_D6 pper02.bit._D6\r
+#define PPER02_D5 pper02.bit._D5\r
+#define PPER02_D4 pper02.bit._D4\r
+#define PPER02_D3 pper02.bit._D3\r
+#define PPER02_D2 pper02.bit._D2\r
+#define PPER02_D1 pper02.bit._D1\r
+#define PPER02_D0 pper02.bit._D0\r
+__IO_EXTERN PPER03STR pper03;  \r
+#define PPER03 pper03.byte\r
+#define PPER03_D7 pper03.bit._D7\r
+#define PPER03_D6 pper03.bit._D6\r
+#define PPER03_D5 pper03.bit._D5\r
+#define PPER03_D4 pper03.bit._D4\r
+#define PPER03_D3 pper03.bit._D3\r
+#define PPER03_D2 pper03.bit._D2\r
+#define PPER03_D1 pper03.bit._D1\r
+#define PPER03_D0 pper03.bit._D0\r
+__IO_EXTERN PPER04STR pper04;  \r
+#define PPER04 pper04.byte\r
+#define PPER04_D1 pper04.bit._D1\r
+#define PPER04_D0 pper04.bit._D0\r
+__IO_EXTERN PPER05STR pper05;  \r
+#define PPER05 pper05.byte\r
+#define PPER05_D7 pper05.bit._D7\r
+#define PPER05_D6 pper05.bit._D6\r
+#define PPER05_D5 pper05.bit._D5\r
+#define PPER05_D4 pper05.bit._D4\r
+#define PPER05_D3 pper05.bit._D3\r
+#define PPER05_D2 pper05.bit._D2\r
+#define PPER05_D1 pper05.bit._D1\r
+#define PPER05_D0 pper05.bit._D0\r
+__IO_EXTERN PPER06STR pper06;  \r
+#define PPER06 pper06.byte\r
+#define PPER06_D7 pper06.bit._D7\r
+#define PPER06_D6 pper06.bit._D6\r
+#define PPER06_D5 pper06.bit._D5\r
+#define PPER06_D4 pper06.bit._D4\r
+#define PPER06_D3 pper06.bit._D3\r
+#define PPER06_D2 pper06.bit._D2\r
+#define PPER06_D1 pper06.bit._D1\r
+#define PPER06_D0 pper06.bit._D0\r
+__IO_EXTERN PPER07STR pper07;  \r
+#define PPER07 pper07.byte\r
+#define PPER07_D7 pper07.bit._D7\r
+#define PPER07_D6 pper07.bit._D6\r
+#define PPER07_D5 pper07.bit._D5\r
+#define PPER07_D4 pper07.bit._D4\r
+#define PPER07_D3 pper07.bit._D3\r
+#define PPER07_D2 pper07.bit._D2\r
+#define PPER07_D1 pper07.bit._D1\r
+#define PPER07_D0 pper07.bit._D0\r
+__IO_EXTERN PPER08STR pper08;  \r
+#define PPER08 pper08.byte\r
+#define PPER08_D7 pper08.bit._D7\r
+#define PPER08_D6 pper08.bit._D6\r
+#define PPER08_D5 pper08.bit._D5\r
+#define PPER08_D4 pper08.bit._D4\r
+#define PPER08_D3 pper08.bit._D3\r
+#define PPER08_D2 pper08.bit._D2\r
+#define PPER08_D1 pper08.bit._D1\r
+#define PPER08_D0 pper08.bit._D0\r
+__IO_EXTERN PPER09STR pper09;  \r
+#define PPER09 pper09.byte\r
+#define PPER09_D7 pper09.bit._D7\r
+#define PPER09_D6 pper09.bit._D6\r
+#define PPER09_D3 pper09.bit._D3\r
+#define PPER09_D2 pper09.bit._D2\r
+#define PPER09_D1 pper09.bit._D1\r
+#define PPER09_D0 pper09.bit._D0\r
+__IO_EXTERN PPER10STR pper10;  \r
+#define PPER10 pper10.byte\r
+#define PPER10_D6 pper10.bit._D6\r
+#define PPER10_D5 pper10.bit._D5\r
+#define PPER10_D4 pper10.bit._D4\r
+#define PPER10_D3 pper10.bit._D3\r
+#define PPER10_D2 pper10.bit._D2\r
+#define PPER10_D1 pper10.bit._D1\r
+__IO_EXTERN PPER13STR pper13;  \r
+#define PPER13 pper13.byte\r
+#define PPER13_D2 pper13.bit._D2\r
+#define PPER13_D1 pper13.bit._D1\r
+#define PPER13_D0 pper13.bit._D0\r
+__IO_EXTERN PPER14STR pper14;  \r
+#define PPER14 pper14.byte\r
+#define PPER14_D7 pper14.bit._D7\r
+#define PPER14_D6 pper14.bit._D6\r
+#define PPER14_D5 pper14.bit._D5\r
+#define PPER14_D4 pper14.bit._D4\r
+#define PPER14_D3 pper14.bit._D3\r
+#define PPER14_D2 pper14.bit._D2\r
+#define PPER14_D1 pper14.bit._D1\r
+#define PPER14_D0 pper14.bit._D0\r
+__IO_EXTERN PPER15STR pper15;  \r
+#define PPER15 pper15.byte\r
+#define PPER15_D3 pper15.bit._D3\r
+#define PPER15_D2 pper15.bit._D2\r
+#define PPER15_D1 pper15.bit._D1\r
+#define PPER15_D0 pper15.bit._D0\r
+__IO_EXTERN PPER16STR pper16;  \r
+#define PPER16 pper16.byte\r
+#define PPER16_D7 pper16.bit._D7\r
+#define PPER16_D6 pper16.bit._D6\r
+#define PPER16_D5 pper16.bit._D5\r
+#define PPER16_D4 pper16.bit._D4\r
+#define PPER16_D3 pper16.bit._D3\r
+#define PPER16_D2 pper16.bit._D2\r
+#define PPER16_D1 pper16.bit._D1\r
+#define PPER16_D0 pper16.bit._D0\r
+__IO_EXTERN PPER17STR pper17;  \r
+#define PPER17 pper17.byte\r
+#define PPER17_D7 pper17.bit._D7\r
+#define PPER17_D6 pper17.bit._D6\r
+#define PPER17_D5 pper17.bit._D5\r
+#define PPER17_D4 pper17.bit._D4\r
+__IO_EXTERN PPER18STR pper18;  \r
+#define PPER18 pper18.byte\r
+#define PPER18_D6 pper18.bit._D6\r
+#define PPER18_D5 pper18.bit._D5\r
+#define PPER18_D4 pper18.bit._D4\r
+#define PPER18_D2 pper18.bit._D2\r
+#define PPER18_D1 pper18.bit._D1\r
+#define PPER18_D0 pper18.bit._D0\r
+__IO_EXTERN PPER19STR pper19;  \r
+#define PPER19 pper19.byte\r
+#define PPER19_D6 pper19.bit._D6\r
+#define PPER19_D5 pper19.bit._D5\r
+#define PPER19_D4 pper19.bit._D4\r
+#define PPER19_D2 pper19.bit._D2\r
+#define PPER19_D1 pper19.bit._D1\r
+#define PPER19_D0 pper19.bit._D0\r
+__IO_EXTERN PPER20STR pper20;  \r
+#define PPER20 pper20.byte\r
+#define PPER20_D2 pper20.bit._D2\r
+#define PPER20_D1 pper20.bit._D1\r
+#define PPER20_D0 pper20.bit._D0\r
+__IO_EXTERN PPER22STR pper22;  \r
+#define PPER22 pper22.byte\r
+#define PPER22_D5 pper22.bit._D5\r
+#define PPER22_D4 pper22.bit._D4\r
+#define PPER22_D2 pper22.bit._D2\r
+#define PPER22_D0 pper22.bit._D0\r
+__IO_EXTERN PPER23STR pper23;  \r
+#define PPER23 pper23.byte\r
+#define PPER23_D5 pper23.bit._D5\r
+#define PPER23_D4 pper23.bit._D4\r
+#define PPER23_D3 pper23.bit._D3\r
+#define PPER23_D2 pper23.bit._D2\r
+#define PPER23_D1 pper23.bit._D1\r
+#define PPER23_D0 pper23.bit._D0\r
+__IO_EXTERN PPER24STR pper24;  \r
+#define PPER24 pper24.byte\r
+#define PPER24_D7 pper24.bit._D7\r
+#define PPER24_D6 pper24.bit._D6\r
+#define PPER24_D5 pper24.bit._D5\r
+#define PPER24_D4 pper24.bit._D4\r
+#define PPER24_D3 pper24.bit._D3\r
+#define PPER24_D2 pper24.bit._D2\r
+#define PPER24_D1 pper24.bit._D1\r
+#define PPER24_D0 pper24.bit._D0\r
+__IO_EXTERN PPER25STR pper25;  \r
+#define PPER25 pper25.byte\r
+#define PPER25_D7 pper25.bit._D7\r
+#define PPER25_D6 pper25.bit._D6\r
+#define PPER25_D5 pper25.bit._D5\r
+#define PPER25_D4 pper25.bit._D4\r
+#define PPER25_D3 pper25.bit._D3\r
+#define PPER25_D2 pper25.bit._D2\r
+#define PPER25_D1 pper25.bit._D1\r
+#define PPER25_D0 pper25.bit._D0\r
+__IO_EXTERN PPER26STR pper26;  \r
+#define PPER26 pper26.byte\r
+#define PPER26_D7 pper26.bit._D7\r
+#define PPER26_D6 pper26.bit._D6\r
+#define PPER26_D5 pper26.bit._D5\r
+#define PPER26_D4 pper26.bit._D4\r
+#define PPER26_D3 pper26.bit._D3\r
+#define PPER26_D2 pper26.bit._D2\r
+#define PPER26_D1 pper26.bit._D1\r
+#define PPER26_D0 pper26.bit._D0\r
+__IO_EXTERN PPER27STR pper27;  \r
+#define PPER27 pper27.byte\r
+#define PPER27_D7 pper27.bit._D7\r
+#define PPER27_D6 pper27.bit._D6\r
+#define PPER27_D5 pper27.bit._D5\r
+#define PPER27_D4 pper27.bit._D4\r
+#define PPER27_D3 pper27.bit._D3\r
+#define PPER27_D2 pper27.bit._D2\r
+#define PPER27_D1 pper27.bit._D1\r
+#define PPER27_D0 pper27.bit._D0\r
+__IO_EXTERN PPER29STR pper29;  \r
+#define PPER29 pper29.byte\r
+#define PPER29_D7 pper29.bit._D7\r
+#define PPER29_D6 pper29.bit._D6\r
+#define PPER29_D5 pper29.bit._D5\r
+#define PPER29_D4 pper29.bit._D4\r
+#define PPER29_D3 pper29.bit._D3\r
+#define PPER29_D2 pper29.bit._D2\r
+#define PPER29_D1 pper29.bit._D1\r
+#define PPER29_D0 pper29.bit._D0\r
+__IO_EXTERN PPCR00STR ppcr00;   /* R-bus Port Pull-Up/Down Control Register */\r
+#define PPCR00 ppcr00.byte\r
+#define PPCR00_D7 ppcr00.bit._D7\r
+#define PPCR00_D6 ppcr00.bit._D6\r
+#define PPCR00_D5 ppcr00.bit._D5\r
+#define PPCR00_D4 ppcr00.bit._D4\r
+#define PPCR00_D3 ppcr00.bit._D3\r
+#define PPCR00_D2 ppcr00.bit._D2\r
+#define PPCR00_D1 ppcr00.bit._D1\r
+#define PPCR00_D0 ppcr00.bit._D0\r
+__IO_EXTERN PPCR01STR ppcr01;  \r
+#define PPCR01 ppcr01.byte\r
+#define PPCR01_D7 ppcr01.bit._D7\r
+#define PPCR01_D6 ppcr01.bit._D6\r
+#define PPCR01_D5 ppcr01.bit._D5\r
+#define PPCR01_D4 ppcr01.bit._D4\r
+#define PPCR01_D3 ppcr01.bit._D3\r
+#define PPCR01_D2 ppcr01.bit._D2\r
+#define PPCR01_D1 ppcr01.bit._D1\r
+#define PPCR01_D0 ppcr01.bit._D0\r
+__IO_EXTERN PPCR02STR ppcr02;  \r
+#define PPCR02 ppcr02.byte\r
+#define PPCR02_D7 ppcr02.bit._D7\r
+#define PPCR02_D6 ppcr02.bit._D6\r
+#define PPCR02_D5 ppcr02.bit._D5\r
+#define PPCR02_D4 ppcr02.bit._D4\r
+#define PPCR02_D3 ppcr02.bit._D3\r
+#define PPCR02_D2 ppcr02.bit._D2\r
+#define PPCR02_D1 ppcr02.bit._D1\r
+#define PPCR02_D0 ppcr02.bit._D0\r
+__IO_EXTERN PPCR03STR ppcr03;  \r
+#define PPCR03 ppcr03.byte\r
+#define PPCR03_D7 ppcr03.bit._D7\r
+#define PPCR03_D6 ppcr03.bit._D6\r
+#define PPCR03_D5 ppcr03.bit._D5\r
+#define PPCR03_D4 ppcr03.bit._D4\r
+#define PPCR03_D3 ppcr03.bit._D3\r
+#define PPCR03_D2 ppcr03.bit._D2\r
+#define PPCR03_D1 ppcr03.bit._D1\r
+#define PPCR03_D0 ppcr03.bit._D0\r
+__IO_EXTERN PPCR04STR ppcr04;  \r
+#define PPCR04 ppcr04.byte\r
+#define PPCR04_D1 ppcr04.bit._D1\r
+#define PPCR04_D0 ppcr04.bit._D0\r
+__IO_EXTERN PPCR05STR ppcr05;  \r
+#define PPCR05 ppcr05.byte\r
+#define PPCR05_D7 ppcr05.bit._D7\r
+#define PPCR05_D6 ppcr05.bit._D6\r
+#define PPCR05_D5 ppcr05.bit._D5\r
+#define PPCR05_D4 ppcr05.bit._D4\r
+#define PPCR05_D3 ppcr05.bit._D3\r
+#define PPCR05_D2 ppcr05.bit._D2\r
+#define PPCR05_D1 ppcr05.bit._D1\r
+#define PPCR05_D0 ppcr05.bit._D0\r
+__IO_EXTERN PPCR06STR ppcr06;  \r
+#define PPCR06 ppcr06.byte\r
+#define PPCR06_D7 ppcr06.bit._D7\r
+#define PPCR06_D6 ppcr06.bit._D6\r
+#define PPCR06_D5 ppcr06.bit._D5\r
+#define PPCR06_D4 ppcr06.bit._D4\r
+#define PPCR06_D3 ppcr06.bit._D3\r
+#define PPCR06_D2 ppcr06.bit._D2\r
+#define PPCR06_D1 ppcr06.bit._D1\r
+#define PPCR06_D0 ppcr06.bit._D0\r
+__IO_EXTERN PPCR07STR ppcr07;  \r
+#define PPCR07 ppcr07.byte\r
+#define PPCR07_D7 ppcr07.bit._D7\r
+#define PPCR07_D6 ppcr07.bit._D6\r
+#define PPCR07_D5 ppcr07.bit._D5\r
+#define PPCR07_D4 ppcr07.bit._D4\r
+#define PPCR07_D3 ppcr07.bit._D3\r
+#define PPCR07_D2 ppcr07.bit._D2\r
+#define PPCR07_D1 ppcr07.bit._D1\r
+#define PPCR07_D0 ppcr07.bit._D0\r
+__IO_EXTERN PPCR08STR ppcr08;  \r
+#define PPCR08 ppcr08.byte\r
+#define PPCR08_D7 ppcr08.bit._D7\r
+#define PPCR08_D6 ppcr08.bit._D6\r
+#define PPCR08_D5 ppcr08.bit._D5\r
+#define PPCR08_D4 ppcr08.bit._D4\r
+#define PPCR08_D3 ppcr08.bit._D3\r
+#define PPCR08_D2 ppcr08.bit._D2\r
+#define PPCR08_D1 ppcr08.bit._D1\r
+#define PPCR08_D0 ppcr08.bit._D0\r
+__IO_EXTERN PPCR09STR ppcr09;  \r
+#define PPCR09 ppcr09.byte\r
+#define PPCR09_D7 ppcr09.bit._D7\r
+#define PPCR09_D6 ppcr09.bit._D6\r
+#define PPCR09_D3 ppcr09.bit._D3\r
+#define PPCR09_D2 ppcr09.bit._D2\r
+#define PPCR09_D1 ppcr09.bit._D1\r
+#define PPCR09_D0 ppcr09.bit._D0\r
+__IO_EXTERN PPCR10STR ppcr10;  \r
+#define PPCR10 ppcr10.byte\r
+#define PPCR10_D6 ppcr10.bit._D6\r
+#define PPCR10_D5 ppcr10.bit._D5\r
+#define PPCR10_D4 ppcr10.bit._D4\r
+#define PPCR10_D3 ppcr10.bit._D3\r
+#define PPCR10_D2 ppcr10.bit._D2\r
+#define PPCR10_D1 ppcr10.bit._D1\r
+__IO_EXTERN PPCR13STR ppcr13;  \r
+#define PPCR13 ppcr13.byte\r
+#define PPCR13_D2 ppcr13.bit._D2\r
+#define PPCR13_D1 ppcr13.bit._D1\r
+#define PPCR13_D0 ppcr13.bit._D0\r
+__IO_EXTERN PPCR14STR ppcr14;  \r
+#define PPCR14 ppcr14.byte\r
+#define PPCR14_D7 ppcr14.bit._D7\r
+#define PPCR14_D6 ppcr14.bit._D6\r
+#define PPCR14_D5 ppcr14.bit._D5\r
+#define PPCR14_D4 ppcr14.bit._D4\r
+#define PPCR14_D3 ppcr14.bit._D3\r
+#define PPCR14_D2 ppcr14.bit._D2\r
+#define PPCR14_D1 ppcr14.bit._D1\r
+#define PPCR14_D0 ppcr14.bit._D0\r
+__IO_EXTERN PPCR15STR ppcr15;  \r
+#define PPCR15 ppcr15.byte\r
+#define PPCR15_D3 ppcr15.bit._D3\r
+#define PPCR15_D2 ppcr15.bit._D2\r
+#define PPCR15_D1 ppcr15.bit._D1\r
+#define PPCR15_D0 ppcr15.bit._D0\r
+__IO_EXTERN PPCR16STR ppcr16;  \r
+#define PPCR16 ppcr16.byte\r
+#define PPCR16_D7 ppcr16.bit._D7\r
+#define PPCR16_D6 ppcr16.bit._D6\r
+#define PPCR16_D5 ppcr16.bit._D5\r
+#define PPCR16_D4 ppcr16.bit._D4\r
+#define PPCR16_D3 ppcr16.bit._D3\r
+#define PPCR16_D2 ppcr16.bit._D2\r
+#define PPCR16_D1 ppcr16.bit._D1\r
+#define PPCR16_D0 ppcr16.bit._D0\r
+__IO_EXTERN PPCR17STR ppcr17;  \r
+#define PPCR17 ppcr17.byte\r
+#define PPCR17_D7 ppcr17.bit._D7\r
+#define PPCR17_D6 ppcr17.bit._D6\r
+#define PPCR17_D5 ppcr17.bit._D5\r
+#define PPCR17_D4 ppcr17.bit._D4\r
+__IO_EXTERN PPCR18STR ppcr18;  \r
+#define PPCR18 ppcr18.byte\r
+#define PPCR18_D6 ppcr18.bit._D6\r
+#define PPCR18_D5 ppcr18.bit._D5\r
+#define PPCR18_D4 ppcr18.bit._D4\r
+#define PPCR18_D2 ppcr18.bit._D2\r
+#define PPCR18_D1 ppcr18.bit._D1\r
+#define PPCR18_D0 ppcr18.bit._D0\r
+__IO_EXTERN PPCR19STR ppcr19;  \r
+#define PPCR19 ppcr19.byte\r
+#define PPCR19_D6 ppcr19.bit._D6\r
+#define PPCR19_D5 ppcr19.bit._D5\r
+#define PPCR19_D4 ppcr19.bit._D4\r
+#define PPCR19_D2 ppcr19.bit._D2\r
+#define PPCR19_D1 ppcr19.bit._D1\r
+#define PPCR19_D0 ppcr19.bit._D0\r
+__IO_EXTERN PPCR20STR ppcr20;  \r
+#define PPCR20 ppcr20.byte\r
+#define PPCR20_D2 ppcr20.bit._D2\r
+#define PPCR20_D1 ppcr20.bit._D1\r
+#define PPCR20_D0 ppcr20.bit._D0\r
+__IO_EXTERN PPCR22STR ppcr22;  \r
+#define PPCR22 ppcr22.byte\r
+#define PPCR22_D5 ppcr22.bit._D5\r
+#define PPCR22_D4 ppcr22.bit._D4\r
+#define PPCR22_D2 ppcr22.bit._D2\r
+#define PPCR22_D0 ppcr22.bit._D0\r
+__IO_EXTERN PPCR23STR ppcr23;  \r
+#define PPCR23 ppcr23.byte\r
+#define PPCR23_D5 ppcr23.bit._D5\r
+#define PPCR23_D4 ppcr23.bit._D4\r
+#define PPCR23_D3 ppcr23.bit._D3\r
+#define PPCR23_D2 ppcr23.bit._D2\r
+#define PPCR23_D1 ppcr23.bit._D1\r
+#define PPCR23_D0 ppcr23.bit._D0\r
+__IO_EXTERN PPCR24STR ppcr24;  \r
+#define PPCR24 ppcr24.byte\r
+#define PPCR24_D7 ppcr24.bit._D7\r
+#define PPCR24_D6 ppcr24.bit._D6\r
+#define PPCR24_D5 ppcr24.bit._D5\r
+#define PPCR24_D4 ppcr24.bit._D4\r
+#define PPCR24_D3 ppcr24.bit._D3\r
+#define PPCR24_D2 ppcr24.bit._D2\r
+#define PPCR24_D1 ppcr24.bit._D1\r
+#define PPCR24_D0 ppcr24.bit._D0\r
+__IO_EXTERN PPCR25STR ppcr25;  \r
+#define PPCR25 ppcr25.byte\r
+#define PPCR25_D7 ppcr25.bit._D7\r
+#define PPCR25_D6 ppcr25.bit._D6\r
+#define PPCR25_D5 ppcr25.bit._D5\r
+#define PPCR25_D4 ppcr25.bit._D4\r
+#define PPCR25_D3 ppcr25.bit._D3\r
+#define PPCR25_D2 ppcr25.bit._D2\r
+#define PPCR25_D1 ppcr25.bit._D1\r
+#define PPCR25_D0 ppcr25.bit._D0\r
+__IO_EXTERN PPCR26STR ppcr26;  \r
+#define PPCR26 ppcr26.byte\r
+#define PPCR26_D7 ppcr26.bit._D7\r
+#define PPCR26_D6 ppcr26.bit._D6\r
+#define PPCR26_D5 ppcr26.bit._D5\r
+#define PPCR26_D4 ppcr26.bit._D4\r
+#define PPCR26_D3 ppcr26.bit._D3\r
+#define PPCR26_D2 ppcr26.bit._D2\r
+#define PPCR26_D1 ppcr26.bit._D1\r
+#define PPCR26_D0 ppcr26.bit._D0\r
+__IO_EXTERN PPCR27STR ppcr27;  \r
+#define PPCR27 ppcr27.byte\r
+#define PPCR27_D7 ppcr27.bit._D7\r
+#define PPCR27_D6 ppcr27.bit._D6\r
+#define PPCR27_D5 ppcr27.bit._D5\r
+#define PPCR27_D4 ppcr27.bit._D4\r
+#define PPCR27_D3 ppcr27.bit._D3\r
+#define PPCR27_D2 ppcr27.bit._D2\r
+#define PPCR27_D1 ppcr27.bit._D1\r
+#define PPCR27_D0 ppcr27.bit._D0\r
+__IO_EXTERN PPCR29STR ppcr29;  \r
+#define PPCR29 ppcr29.byte\r
+#define PPCR29_D7 ppcr29.bit._D7\r
+#define PPCR29_D6 ppcr29.bit._D6\r
+#define PPCR29_D5 ppcr29.bit._D5\r
+#define PPCR29_D4 ppcr29.bit._D4\r
+#define PPCR29_D3 ppcr29.bit._D3\r
+#define PPCR29_D2 ppcr29.bit._D2\r
+#define PPCR29_D1 ppcr29.bit._D1\r
+#define PPCR29_D0 ppcr29.bit._D0\r
+__IO_EXTERN IO_LWORD dmasa0;   /* DMAC */\r
+#define DMASA0 dmasa0\r
+__IO_EXTERN IO_LWORD dmada0;  \r
+#define DMADA0 dmada0\r
+__IO_EXTERN IO_LWORD dmasa1;  \r
+#define DMASA1 dmasa1\r
+__IO_EXTERN IO_LWORD dmada1;  \r
+#define DMADA1 dmada1\r
+__IO_EXTERN IO_LWORD dmasa2;  \r
+#define DMASA2 dmasa2\r
+__IO_EXTERN IO_LWORD dmada2;  \r
+#define DMADA2 dmada2\r
+__IO_EXTERN IO_LWORD dmasa3;  \r
+#define DMASA3 dmasa3\r
+__IO_EXTERN IO_LWORD dmada3;  \r
+#define DMADA3 dmada3\r
+__IO_EXTERN IO_LWORD dmasa4;  \r
+#define DMASA4 dmasa4\r
+__IO_EXTERN IO_LWORD dmada4;  \r
+#define DMADA4 dmada4\r
+__IO_EXTERN FMCSSTR fmcs;   /* Flash Memory/I-Cache Control Register */\r
+#define FMCS fmcs.byte\r
+#define FMCS_ASYNC fmcs.bit._ASYNC\r
+#define FMCS_FIXE fmcs.bit._FIXE\r
+#define FMCS_BIRE fmcs.bit._BIRE\r
+#define FMCS_RDYEG fmcs.bit._RDYEG\r
+#define FMCS_RDY fmcs.bit._RDY\r
+#define FMCS_RDYI fmcs.bit._RDYI\r
+#define FMCS_RW16 fmcs.bit._RW16\r
+#define FMCS_LPM fmcs.bit._LPM\r
+__IO_EXTERN FMCRSTR fmcr;  \r
+#define FMCR fmcr.byte\r
+#define FMCR_LOCK fmcr.bit._LOCK\r
+#define FMCR_PHASE fmcr.bit._PHASE\r
+#define FMCR_PF2I fmcr.bit._PF2I\r
+#define FMCR_RD64 fmcr.bit._RD64\r
+__IO_EXTERN FCHCRSTR fchcr;  \r
+#define FCHCR fchcr.word\r
+#define FCHCR_REN fchcr.bit._REN\r
+#define FCHCR_TAGE fchcr.bit._TAGE\r
+#define FCHCR_FLUSH fchcr.bit._FLUSH\r
+#define FCHCR_DBEN fchcr.bit._DBEN\r
+#define FCHCR_PFEN fchcr.bit._PFEN\r
+#define FCHCR_PFMC fchcr.bit._PFMC\r
+#define FCHCR_LOCK fchcr.bit._LOCK\r
+#define FCHCR_ENAB fchcr.bit._ENAB\r
+#define FCHCR_SIZE1 fchcr.bit._SIZE1\r
+#define FCHCR_SIZE0 fchcr.bit._SIZE0\r
+#define FCHCR_SIZE fchcr.bitc._SIZE\r
+__IO_EXTERN FMWTSTR fmwt;  \r
+#define FMWT fmwt.word\r
+#define FMWT_WTP1 fmwt.bit._WTP1\r
+#define FMWT_WTP0 fmwt.bit._WTP0\r
+#define FMWT_WEXH1 fmwt.bit._WEXH1\r
+#define FMWT_WEXH0 fmwt.bit._WEXH0\r
+#define FMWT_WTC3 fmwt.bit._WTC3\r
+#define FMWT_WTC2 fmwt.bit._WTC2\r
+#define FMWT_WTC1 fmwt.bit._WTC1\r
+#define FMWT_WTC0 fmwt.bit._WTC0\r
+#define FMWT_FRAM fmwt.bit._FRAM\r
+#define FMWT_ATD2 fmwt.bit._ATD2\r
+#define FMWT_ATD1 fmwt.bit._ATD1\r
+#define FMWT_ATD0 fmwt.bit._ATD0\r
+#define FMWT_EQ3 fmwt.bit._EQ3\r
+#define FMWT_EQ2 fmwt.bit._EQ2\r
+#define FMWT_EQ1 fmwt.bit._EQ1\r
+#define FMWT_EQ0 fmwt.bit._EQ0\r
+#define FMWT_WTP fmwt.bitc._WTP\r
+#define FMWT_WEXH fmwt.bitc._WEXH\r
+#define FMWT_WTC fmwt.bitc._WTC\r
+#define FMWT_ATD fmwt.bitc._ATD\r
+#define FMWT_EQ fmwt.bitc._EQ\r
+__IO_EXTERN FMWT2STR fmwt2;  \r
+#define FMWT2 fmwt2.byte\r
+#define FMWT2_ALEH2 fmwt2.bit._ALEH2\r
+#define FMWT2_ALEH1 fmwt2.bit._ALEH1\r
+#define FMWT2_ALEH0 fmwt2.bit._ALEH0\r
+#define FMWT2_ALEH fmwt2.bitc._ALEH\r
+__IO_EXTERN FMPSSTR fmps;  \r
+#define FMPS fmps.byte\r
+#define FMPS_PS2 fmps.bit._PS2\r
+#define FMPS_PS1 fmps.bit._PS1\r
+#define FMPS_PS0 fmps.bit._PS0\r
+#define FMPS_PS fmps.bitc._PS\r
+__IO_EXTERN IO_LWORD fmac;  \r
+#define FMAC fmac\r
+__IO_EXTERN IO_LWORD fcha0;   /* I_Cache Nonchachable area settings Register */\r
+#define FCHA0 fcha0\r
+__IO_EXTERN IO_LWORD fcha1;  \r
+#define FCHA1 fcha1\r
+__IO_EXTERN FSCR0STR fscr0;   /* Flash Security Control Register */\r
+#define FSCR0 fscr0.lword\r
+#define FSCR0_CRC31 fscr0.bit._CRC31\r
+#define FSCR0_CRC30 fscr0.bit._CRC30\r
+#define FSCR0_CRC29 fscr0.bit._CRC29\r
+#define FSCR0_CRC28 fscr0.bit._CRC28\r
+#define FSCR0_CRC27 fscr0.bit._CRC27\r
+#define FSCR0_CRC26 fscr0.bit._CRC26\r
+#define FSCR0_CRC25 fscr0.bit._CRC25\r
+#define FSCR0_CRC24 fscr0.bit._CRC24\r
+#define FSCR0_CRC23 fscr0.bit._CRC23\r
+#define FSCR0_CRC22 fscr0.bit._CRC22\r
+#define FSCR0_CRC21 fscr0.bit._CRC21\r
+#define FSCR0_CRC20 fscr0.bit._CRC20\r
+#define FSCR0_CRC19 fscr0.bit._CRC19\r
+#define FSCR0_CRC18 fscr0.bit._CRC18\r
+#define FSCR0_CRC17 fscr0.bit._CRC17\r
+#define FSCR0_CRC16 fscr0.bit._CRC16\r
+#define FSCR0_CRC15 fscr0.bit._CRC15\r
+#define FSCR0_CRC14 fscr0.bit._CRC14\r
+#define FSCR0_CRC13 fscr0.bit._CRC13\r
+#define FSCR0_CRC12 fscr0.bit._CRC12\r
+#define FSCR0_CRC11 fscr0.bit._CRC11\r
+#define FSCR0_CRC10 fscr0.bit._CRC10\r
+#define FSCR0_CRC9 fscr0.bit._CRC9\r
+#define FSCR0_CRC8 fscr0.bit._CRC8\r
+#define FSCR0_CRC7 fscr0.bit._CRC7\r
+#define FSCR0_CRC6 fscr0.bit._CRC6\r
+#define FSCR0_CRC5 fscr0.bit._CRC5\r
+#define FSCR0_CRC4 fscr0.bit._CRC4\r
+#define FSCR0_CRC3 fscr0.bit._CRC3\r
+#define FSCR0_CRC2 fscr0.bit._CRC2\r
+#define FSCR0_CRC1 fscr0.bit._CRC1\r
+#define FSCR0_CRC0 fscr0.bit._CRC0\r
+__IO_EXTERN FSCR1STR fscr1;  \r
+#define FSCR1 fscr1.lword\r
+#define FSCR1_RDY fscr1.bit._RDY\r
+#define FSCR1_CSZ3 fscr1.bit._CSZ3\r
+#define FSCR1_CSZ2 fscr1.bit._CSZ2\r
+#define FSCR1_CSZ1 fscr1.bit._CSZ1\r
+#define FSCR1_CSZ0 fscr1.bit._CSZ0\r
+#define FSCR1_CSA15 fscr1.bit._CSA15\r
+#define FSCR1_CSA14 fscr1.bit._CSA14\r
+#define FSCR1_CSA13 fscr1.bit._CSA13\r
+#define FSCR1_CSA12 fscr1.bit._CSA12\r
+#define FSCR1_CSA11 fscr1.bit._CSA11\r
+#define FSCR1_CSA10 fscr1.bit._CSA10\r
+#define FSCR1_CSA9 fscr1.bit._CSA9\r
+#define FSCR1_CSA8 fscr1.bit._CSA8\r
+#define FSCR1_CSA7 fscr1.bit._CSA7\r
+#define FSCR1_CSA6 fscr1.bit._CSA6\r
+#define FSCR1_CSA5 fscr1.bit._CSA5\r
+#define FSCR1_CSA4 fscr1.bit._CSA4\r
+#define FSCR1_CSA3 fscr1.bit._CSA3\r
+#define FSCR1_CSA2 fscr1.bit._CSA2\r
+#define FSCR1_CSA1 fscr1.bit._CSA1\r
+#define FSCR1_CSA0 fscr1.bit._CSA0\r
+#define FSCR1_CSZ fscr1.bitc._CSZ\r
+__IO_EXTERN CTRLR0STR ctrlr0;   /* CAN 0 Control Register */\r
+#define CTRLR0 ctrlr0.word\r
+#define CTRLR0_Test ctrlr0.bit._Test\r
+#define CTRLR0_CCE ctrlr0.bit._CCE\r
+#define CTRLR0_DAR ctrlr0.bit._DAR\r
+#define CTRLR0_EIE ctrlr0.bit._EIE\r
+#define CTRLR0_SIE ctrlr0.bit._SIE\r
+#define CTRLR0_IE ctrlr0.bit._IE\r
+#define CTRLR0_Init ctrlr0.bit._Init\r
+__IO_EXTERN STATR0STR statr0;  \r
+#define STATR0 statr0.word\r
+#define STATR0_BOff statr0.bit._BOff\r
+#define STATR0_EWarn statr0.bit._EWarn\r
+#define STATR0_EPass statr0.bit._EPass\r
+#define STATR0_RxOK statr0.bit._RxOK\r
+#define STATR0_TxOK statr0.bit._TxOK\r
+#define STATR0_LEC2 statr0.bit._LEC2\r
+#define STATR0_LEC1 statr0.bit._LEC1\r
+#define STATR0_LEC0 statr0.bit._LEC0\r
+#define STATR0_LEC statr0.bitc._LEC\r
+__IO_EXTERN ERRCNT0STR errcnt0;  \r
+#define ERRCNT0 errcnt0.word\r
+#define ERRCNT0_RP errcnt0.bit._RP\r
+#define ERRCNT0_REC6 errcnt0.bit._REC6\r
+#define ERRCNT0_REC5 errcnt0.bit._REC5\r
+#define ERRCNT0_REC4 errcnt0.bit._REC4\r
+#define ERRCNT0_REC3 errcnt0.bit._REC3\r
+#define ERRCNT0_REC2 errcnt0.bit._REC2\r
+#define ERRCNT0_REC1 errcnt0.bit._REC1\r
+#define ERRCNT0_REC0 errcnt0.bit._REC0\r
+#define ERRCNT0_TEC7 errcnt0.bit._TEC7\r
+#define ERRCNT0_TEC6 errcnt0.bit._TEC6\r
+#define ERRCNT0_TEC5 errcnt0.bit._TEC5\r
+#define ERRCNT0_TEC4 errcnt0.bit._TEC4\r
+#define ERRCNT0_TEC3 errcnt0.bit._TEC3\r
+#define ERRCNT0_TEC2 errcnt0.bit._TEC2\r
+#define ERRCNT0_TEC1 errcnt0.bit._TEC1\r
+#define ERRCNT0_TEC0 errcnt0.bit._TEC0\r
+#define ERRCNT0_REC errcnt0.bitc._REC\r
+#define ERRCNT0_TEC errcnt0.bitc._TEC\r
+__IO_EXTERN BTR0STR btr0;  \r
+#define BTR0 btr0.word\r
+#define BTR0_Tseg22 btr0.bit._Tseg22\r
+#define BTR0_Tseg21 btr0.bit._Tseg21\r
+#define BTR0_Tseg20 btr0.bit._Tseg20\r
+#define BTR0_Tseg13 btr0.bit._Tseg13\r
+#define BTR0_Tseg12 btr0.bit._Tseg12\r
+#define BTR0_Tseg11 btr0.bit._Tseg11\r
+#define BTR0_Tseg10 btr0.bit._Tseg10\r
+#define BTR0_SJW1 btr0.bit._SJW1\r
+#define BTR0_SJW0 btr0.bit._SJW0\r
+#define BTR0_BRP5 btr0.bit._BRP5\r
+#define BTR0_BRP4 btr0.bit._BRP4\r
+#define BTR0_BRP3 btr0.bit._BRP3\r
+#define BTR0_BRP2 btr0.bit._BRP2\r
+#define BTR0_BRP1 btr0.bit._BRP1\r
+#define BTR0_BRP0 btr0.bit._BRP0\r
+#define BTR0_Tseg2 btr0.bitc._Tseg2\r
+#define BTR0_Tseg1 btr0.bitc._Tseg1\r
+#define BTR0_SJW btr0.bitc._SJW\r
+#define BTR0_BRP btr0.bitc._BRP\r
+__IO_EXTERN IO_WORD intr0;  \r
+#define INTR0 intr0\r
+__IO_EXTERN TESTR0STR testr0;  \r
+#define TESTR0 testr0.word\r
+#define TESTR0_Rx testr0.bit._Rx\r
+#define TESTR0_Tx1 testr0.bit._Tx1\r
+#define TESTR0_Tx0 testr0.bit._Tx0\r
+#define TESTR0_LBack testr0.bit._LBack\r
+#define TESTR0_Silent testr0.bit._Silent\r
+#define TESTR0_Basic testr0.bit._Basic\r
+#define TESTR0_Tx testr0.bitc._Tx\r
+__IO_EXTERN BRPER0STR brper0;  \r
+#define BRPER0 brper0.word\r
+#define BRPER0_BRPE3 brper0.bit._BRPE3\r
+#define BRPER0_BRPE2 brper0.bit._BRPE2\r
+#define BRPER0_BRPE1 brper0.bit._BRPE1\r
+#define BRPER0_BRPE0 brper0.bit._BRPE0\r
+#define BRPER0_BRPE brper0.bitc._BRPE\r
+__IO_EXTERN BRPE0STR brpe0;  \r
+#define BRPE0 brpe0.word\r
+__IO_EXTERN CBSYNC0STR cbsync0;  \r
+#define CBSYNC0 cbsync0.word\r
+__IO_EXTERN IF1CREQ0STR if1creq0;   /* CAN 0 IF 1 */\r
+#define IF1CREQ0 if1creq0.word\r
+#define IF1CREQ0_Busy if1creq0.bit._Busy\r
+#define IF1CREQ0_MN5 if1creq0.bit._MN5\r
+#define IF1CREQ0_MN4 if1creq0.bit._MN4\r
+#define IF1CREQ0_MN3 if1creq0.bit._MN3\r
+#define IF1CREQ0_MN2 if1creq0.bit._MN2\r
+#define IF1CREQ0_MN1 if1creq0.bit._MN1\r
+#define IF1CREQ0_MN0 if1creq0.bit._MN0\r
+#define IF1CREQ0_MN if1creq0.bitc._MN\r
+__IO_EXTERN IF1CMSK0STR if1cmsk0;  \r
+#define IF1CMSK0 if1cmsk0.word\r
+#define IF1CMSK0_WR if1cmsk0.bit._WR\r
+#define IF1CMSK0_Mask if1cmsk0.bit._Mask\r
+#define IF1CMSK0_Arb if1cmsk0.bit._Arb\r
+#define IF1CMSK0_Control if1cmsk0.bit._Control\r
+#define IF1CMSK0_CIP if1cmsk0.bit._CIP\r
+#define IF1CMSK0_TxReq if1cmsk0.bit._TxReq\r
+#define IF1CMSK0_DataA if1cmsk0.bit._DataA\r
+#define IF1CMSK0_DataB if1cmsk0.bit._DataB\r
+__IO_EXTERN IO_LWORD if1msk120;  \r
+#define IF1MSK120 if1msk120\r
+__IO_EXTERN IF1MSK20STR if1msk20;  \r
+#define IF1MSK20 if1msk20.word\r
+#define IF1MSK20_MXtd if1msk20.bit._MXtd\r
+#define IF1MSK20_MDir if1msk20.bit._MDir\r
+__IO_EXTERN IO_WORD if1msk10;  \r
+#define IF1MSK10 if1msk10\r
+__IO_EXTERN IO_LWORD if1arb120;  \r
+#define IF1ARB120 if1arb120\r
+__IO_EXTERN IF1ARB20STR if1arb20;  \r
+#define IF1ARB20 if1arb20.word\r
+#define IF1ARB20_MsgVal if1arb20.bit._MsgVal\r
+#define IF1ARB20_Xtd if1arb20.bit._Xtd\r
+#define IF1ARB20_DIR if1arb20.bit._DIR\r
+__IO_EXTERN IO_WORD if1arb10;  \r
+#define IF1ARB10 if1arb10\r
+__IO_EXTERN IF1MCTR0STR if1mctr0;  \r
+#define IF1MCTR0 if1mctr0.word\r
+#define IF1MCTR0_NewDat if1mctr0.bit._NewDat\r
+#define IF1MCTR0_MsgLst if1mctr0.bit._MsgLst\r
+#define IF1MCTR0_IntPnd if1mctr0.bit._IntPnd\r
+#define IF1MCTR0_UMask if1mctr0.bit._UMask\r
+#define IF1MCTR0_TxIE if1mctr0.bit._TxIE\r
+#define IF1MCTR0_RxIE if1mctr0.bit._RxIE\r
+#define IF1MCTR0_RmtEn if1mctr0.bit._RmtEn\r
+#define IF1MCTR0_TxRqst if1mctr0.bit._TxRqst\r
+#define IF1MCTR0_EoB if1mctr0.bit._EoB\r
+#define IF1MCTR0_DLC3 if1mctr0.bit._DLC3\r
+#define IF1MCTR0_DLC2 if1mctr0.bit._DLC2\r
+#define IF1MCTR0_DLC1 if1mctr0.bit._DLC1\r
+#define IF1MCTR0_DLC0 if1mctr0.bit._DLC0\r
+#define IF1MCTR0_DLC if1mctr0.bitc._DLC\r
+__IO_EXTERN IO_LWORD if1dta120;  \r
+#define IF1DTA120 if1dta120\r
+__IO_EXTERN IO_WORD if1dta10;  \r
+#define IF1DTA10 if1dta10\r
+__IO_EXTERN IO_WORD if1dta20;  \r
+#define IF1DTA20 if1dta20\r
+__IO_EXTERN IO_LWORD if1dtb120;  \r
+#define IF1DTB120 if1dtb120\r
+__IO_EXTERN IO_WORD if1dtb10;  \r
+#define IF1DTB10 if1dtb10\r
+__IO_EXTERN IO_WORD if1dtb20;  \r
+#define IF1DTB20 if1dtb20\r
+__IO_EXTERN IO_LWORD if1dta_swp120;  \r
+#define IF1DTA_SWP120 if1dta_swp120\r
+__IO_EXTERN IO_WORD if1dta_swp20;  \r
+#define IF1DTA_SWP20 if1dta_swp20\r
+__IO_EXTERN IO_WORD if1dta_swp10;  \r
+#define IF1DTA_SWP10 if1dta_swp10\r
+__IO_EXTERN IO_LWORD if1dtb_swp120;  \r
+#define IF1DTB_SWP120 if1dtb_swp120\r
+__IO_EXTERN IO_WORD if1dtb_swp20;  \r
+#define IF1DTB_SWP20 if1dtb_swp20\r
+__IO_EXTERN IO_WORD if1dtb_swp10;  \r
+#define IF1DTB_SWP10 if1dtb_swp10\r
+__IO_EXTERN IF2CREQ0STR if2creq0;   /* CAN 0 IF 2 */\r
+#define IF2CREQ0 if2creq0.word\r
+#define IF2CREQ0_Busy if2creq0.bit._Busy\r
+#define IF2CREQ0_MN5 if2creq0.bit._MN5\r
+#define IF2CREQ0_MN4 if2creq0.bit._MN4\r
+#define IF2CREQ0_MN3 if2creq0.bit._MN3\r
+#define IF2CREQ0_MN2 if2creq0.bit._MN2\r
+#define IF2CREQ0_MN1 if2creq0.bit._MN1\r
+#define IF2CREQ0_MN0 if2creq0.bit._MN0\r
+#define IF2CREQ0_MN if2creq0.bitc._MN\r
+__IO_EXTERN IF2CMSK0STR if2cmsk0;  \r
+#define IF2CMSK0 if2cmsk0.word\r
+#define IF2CMSK0_WR if2cmsk0.bit._WR\r
+#define IF2CMSK0_Mask if2cmsk0.bit._Mask\r
+#define IF2CMSK0_Arb if2cmsk0.bit._Arb\r
+#define IF2CMSK0_Control if2cmsk0.bit._Control\r
+#define IF2CMSK0_CIP if2cmsk0.bit._CIP\r
+#define IF2CMSK0_TxReq if2cmsk0.bit._TxReq\r
+#define IF2CMSK0_DataA if2cmsk0.bit._DataA\r
+#define IF2CMSK0_DataB if2cmsk0.bit._DataB\r
+__IO_EXTERN IO_LWORD if2msk120;  \r
+#define IF2MSK120 if2msk120\r
+__IO_EXTERN IF2MSK20STR if2msk20;  \r
+#define IF2MSK20 if2msk20.word\r
+#define IF2MSK20_MXtd if2msk20.bit._MXtd\r
+#define IF2MSK20_MDir if2msk20.bit._MDir\r
+__IO_EXTERN IO_WORD if2msk10;  \r
+#define IF2MSK10 if2msk10\r
+__IO_EXTERN IO_LWORD if2arb120;  \r
+#define IF2ARB120 if2arb120\r
+__IO_EXTERN IF2ARB20STR if2arb20;  \r
+#define IF2ARB20 if2arb20.word\r
+#define IF2ARB20_MsgVal if2arb20.bit._MsgVal\r
+#define IF2ARB20_Xtd if2arb20.bit._Xtd\r
+#define IF2ARB20_DIR if2arb20.bit._DIR\r
+__IO_EXTERN IO_WORD if2arb10;  \r
+#define IF2ARB10 if2arb10\r
+__IO_EXTERN IF2MCTR0STR if2mctr0;  \r
+#define IF2MCTR0 if2mctr0.word\r
+#define IF2MCTR0_NewDat if2mctr0.bit._NewDat\r
+#define IF2MCTR0_MsgLst if2mctr0.bit._MsgLst\r
+#define IF2MCTR0_IntPnd if2mctr0.bit._IntPnd\r
+#define IF2MCTR0_UMask if2mctr0.bit._UMask\r
+#define IF2MCTR0_TxIE if2mctr0.bit._TxIE\r
+#define IF2MCTR0_RxIE if2mctr0.bit._RxIE\r
+#define IF2MCTR0_RmtEn if2mctr0.bit._RmtEn\r
+#define IF2MCTR0_TxRqst if2mctr0.bit._TxRqst\r
+#define IF2MCTR0_EoB if2mctr0.bit._EoB\r
+#define IF2MCTR0_DLC3 if2mctr0.bit._DLC3\r
+#define IF2MCTR0_DLC2 if2mctr0.bit._DLC2\r
+#define IF2MCTR0_DLC1 if2mctr0.bit._DLC1\r
+#define IF2MCTR0_DLC0 if2mctr0.bit._DLC0\r
+#define IF2MCTR0_DLC if2mctr0.bitc._DLC\r
+__IO_EXTERN IO_LWORD if2dta120;  \r
+#define IF2DTA120 if2dta120\r
+__IO_EXTERN IO_WORD if2dta10;  \r
+#define IF2DTA10 if2dta10\r
+__IO_EXTERN IO_WORD if2dta20;  \r
+#define IF2DTA20 if2dta20\r
+__IO_EXTERN IO_LWORD if2dtb120;  \r
+#define IF2DTB120 if2dtb120\r
+__IO_EXTERN IO_WORD if2dtb10;  \r
+#define IF2DTB10 if2dtb10\r
+__IO_EXTERN IO_WORD if2dtb20;  \r
+#define IF2DTB20 if2dtb20\r
+__IO_EXTERN IO_LWORD if2dta_swp120;  \r
+#define IF2DTA_SWP120 if2dta_swp120\r
+__IO_EXTERN IO_WORD if2dta_swp20;  \r
+#define IF2DTA_SWP20 if2dta_swp20\r
+__IO_EXTERN IO_WORD if2dta_swp10;  \r
+#define IF2DTA_SWP10 if2dta_swp10\r
+__IO_EXTERN IO_LWORD if2dtb_swp120;  \r
+#define IF2DTB_SWP120 if2dtb_swp120\r
+__IO_EXTERN IO_WORD if2dtb_swp20;  \r
+#define IF2DTB_SWP20 if2dtb_swp20\r
+__IO_EXTERN IO_WORD if2dtb_swp10;  \r
+#define IF2DTB_SWP10 if2dtb_swp10\r
+__IO_EXTERN IO_LWORD treqr120;   /* CAN 0 Status Flags */\r
+#define TREQR120 treqr120\r
+__IO_EXTERN IO_WORD treqr20;  \r
+#define TREQR20 treqr20\r
+__IO_EXTERN IO_WORD treqr10;  \r
+#define TREQR10 treqr10\r
+__IO_EXTERN IO_LWORD newdt120;  \r
+#define NEWDT120 newdt120\r
+__IO_EXTERN IO_WORD newdt20;  \r
+#define NEWDT20 newdt20\r
+__IO_EXTERN IO_WORD newdt10;  \r
+#define NEWDT10 newdt10\r
+__IO_EXTERN IO_LWORD intpnd120;  \r
+#define INTPND120 intpnd120\r
+__IO_EXTERN IO_WORD intpnd20;  \r
+#define INTPND20 intpnd20\r
+__IO_EXTERN IO_WORD intpnd10;  \r
+#define INTPND10 intpnd10\r
+__IO_EXTERN IO_LWORD msgval120;  \r
+#define MSGVAL120 msgval120\r
+__IO_EXTERN IO_WORD msgval20;  \r
+#define MSGVAL20 msgval20\r
+__IO_EXTERN IO_WORD msgval10;  \r
+#define MSGVAL10 msgval10\r
+__IO_EXTERN IO_LWORD msgval340;  \r
+#define MSGVAL340 msgval340\r
+__IO_EXTERN CTRLR1STR ctrlr1;   /* CAN 1 Control Register */\r
+#define CTRLR1 ctrlr1.word\r
+#define CTRLR1_Test ctrlr1.bit._Test\r
+#define CTRLR1_CCE ctrlr1.bit._CCE\r
+#define CTRLR1_DAR ctrlr1.bit._DAR\r
+#define CTRLR1_EIE ctrlr1.bit._EIE\r
+#define CTRLR1_SIE ctrlr1.bit._SIE\r
+#define CTRLR1_IE ctrlr1.bit._IE\r
+#define CTRLR1_Init ctrlr1.bit._Init\r
+__IO_EXTERN STATR1STR statr1;  \r
+#define STATR1 statr1.word\r
+#define STATR1_BOff statr1.bit._BOff\r
+#define STATR1_EWarn statr1.bit._EWarn\r
+#define STATR1_EPass statr1.bit._EPass\r
+#define STATR1_RxOK statr1.bit._RxOK\r
+#define STATR1_TxOK statr1.bit._TxOK\r
+#define STATR1_LEC2 statr1.bit._LEC2\r
+#define STATR1_LEC1 statr1.bit._LEC1\r
+#define STATR1_LEC0 statr1.bit._LEC0\r
+#define STATR1_LEC statr1.bitc._LEC\r
+__IO_EXTERN ERRCNT1STR errcnt1;  \r
+#define ERRCNT1 errcnt1.word\r
+#define ERRCNT1_RP errcnt1.bit._RP\r
+#define ERRCNT1_REC6 errcnt1.bit._REC6\r
+#define ERRCNT1_REC5 errcnt1.bit._REC5\r
+#define ERRCNT1_REC4 errcnt1.bit._REC4\r
+#define ERRCNT1_REC3 errcnt1.bit._REC3\r
+#define ERRCNT1_REC2 errcnt1.bit._REC2\r
+#define ERRCNT1_REC1 errcnt1.bit._REC1\r
+#define ERRCNT1_REC0 errcnt1.bit._REC0\r
+#define ERRCNT1_TEC7 errcnt1.bit._TEC7\r
+#define ERRCNT1_TEC6 errcnt1.bit._TEC6\r
+#define ERRCNT1_TEC5 errcnt1.bit._TEC5\r
+#define ERRCNT1_TEC4 errcnt1.bit._TEC4\r
+#define ERRCNT1_TEC3 errcnt1.bit._TEC3\r
+#define ERRCNT1_TEC2 errcnt1.bit._TEC2\r
+#define ERRCNT1_TEC1 errcnt1.bit._TEC1\r
+#define ERRCNT1_TEC0 errcnt1.bit._TEC0\r
+#define ERRCNT1_REC errcnt1.bitc._REC\r
+#define ERRCNT1_TEC errcnt1.bitc._TEC\r
+__IO_EXTERN BTR1STR btr1;  \r
+#define BTR1 btr1.word\r
+#define BTR1_Tseg22 btr1.bit._Tseg22\r
+#define BTR1_Tseg21 btr1.bit._Tseg21\r
+#define BTR1_Tseg20 btr1.bit._Tseg20\r
+#define BTR1_Tseg13 btr1.bit._Tseg13\r
+#define BTR1_Tseg12 btr1.bit._Tseg12\r
+#define BTR1_Tseg11 btr1.bit._Tseg11\r
+#define BTR1_Tseg10 btr1.bit._Tseg10\r
+#define BTR1_SJW1 btr1.bit._SJW1\r
+#define BTR1_SJW0 btr1.bit._SJW0\r
+#define BTR1_BRP5 btr1.bit._BRP5\r
+#define BTR1_BRP4 btr1.bit._BRP4\r
+#define BTR1_BRP3 btr1.bit._BRP3\r
+#define BTR1_BRP2 btr1.bit._BRP2\r
+#define BTR1_BRP1 btr1.bit._BRP1\r
+#define BTR1_BRP0 btr1.bit._BRP0\r
+#define BTR1_Tseg2 btr1.bitc._Tseg2\r
+#define BTR1_Tseg1 btr1.bitc._Tseg1\r
+#define BTR1_SJW btr1.bitc._SJW\r
+#define BTR1_BRP btr1.bitc._BRP\r
+__IO_EXTERN IO_WORD intr1;  \r
+#define INTR1 intr1\r
+__IO_EXTERN TESTR1STR testr1;  \r
+#define TESTR1 testr1.word\r
+#define TESTR1_Rx testr1.bit._Rx\r
+#define TESTR1_Tx1 testr1.bit._Tx1\r
+#define TESTR1_Tx0 testr1.bit._Tx0\r
+#define TESTR1_LBack testr1.bit._LBack\r
+#define TESTR1_Silent testr1.bit._Silent\r
+#define TESTR1_Basic testr1.bit._Basic\r
+#define TESTR1_Tx testr1.bitc._Tx\r
+__IO_EXTERN BRPER1STR brper1;  \r
+#define BRPER1 brper1.word\r
+#define BRPER1_BRPE3 brper1.bit._BRPE3\r
+#define BRPER1_BRPE2 brper1.bit._BRPE2\r
+#define BRPER1_BRPE1 brper1.bit._BRPE1\r
+#define BRPER1_BRPE0 brper1.bit._BRPE0\r
+#define BRPER1_BRPE brper1.bitc._BRPE\r
+__IO_EXTERN BRPE1STR brpe1;  \r
+#define BRPE1 brpe1.word\r
+__IO_EXTERN IO_WORD cbsync1;  \r
+#define CBSYNC1 cbsync1\r
+__IO_EXTERN IF1CREQ1STR if1creq1;   /* CAN 1 IF 1 */\r
+#define IF1CREQ1 if1creq1.word\r
+#define IF1CREQ1_Busy if1creq1.bit._Busy\r
+#define IF1CREQ1_MN5 if1creq1.bit._MN5\r
+#define IF1CREQ1_MN4 if1creq1.bit._MN4\r
+#define IF1CREQ1_MN3 if1creq1.bit._MN3\r
+#define IF1CREQ1_MN2 if1creq1.bit._MN2\r
+#define IF1CREQ1_MN1 if1creq1.bit._MN1\r
+#define IF1CREQ1_MN0 if1creq1.bit._MN0\r
+#define IF1CREQ1_MN if1creq1.bitc._MN\r
+__IO_EXTERN IF1CMSK1STR if1cmsk1;  \r
+#define IF1CMSK1 if1cmsk1.word\r
+#define IF1CMSK1_WR if1cmsk1.bit._WR\r
+#define IF1CMSK1_Mask if1cmsk1.bit._Mask\r
+#define IF1CMSK1_Arb if1cmsk1.bit._Arb\r
+#define IF1CMSK1_Control if1cmsk1.bit._Control\r
+#define IF1CMSK1_CIP if1cmsk1.bit._CIP\r
+#define IF1CMSK1_TxReq if1cmsk1.bit._TxReq\r
+#define IF1CMSK1_DataA if1cmsk1.bit._DataA\r
+#define IF1CMSK1_DataB if1cmsk1.bit._DataB\r
+__IO_EXTERN IO_LWORD if1msk121;  \r
+#define IF1MSK121 if1msk121\r
+__IO_EXTERN IF1MSK21STR if1msk21;  \r
+#define IF1MSK21 if1msk21.word\r
+#define IF1MSK21_MXtd if1msk21.bit._MXtd\r
+#define IF1MSK21_MDir if1msk21.bit._MDir\r
+__IO_EXTERN IO_WORD if1msk11;  \r
+#define IF1MSK11 if1msk11\r
+__IO_EXTERN IO_LWORD if1arb121;  \r
+#define IF1ARB121 if1arb121\r
+__IO_EXTERN IF1ARB21STR if1arb21;  \r
+#define IF1ARB21 if1arb21.word\r
+#define IF1ARB21_MsgVal if1arb21.bit._MsgVal\r
+#define IF1ARB21_Xtd if1arb21.bit._Xtd\r
+#define IF1ARB21_DIR if1arb21.bit._DIR\r
+__IO_EXTERN IO_WORD if1arb11;  \r
+#define IF1ARB11 if1arb11\r
+__IO_EXTERN IF1MCTR1STR if1mctr1;  \r
+#define IF1MCTR1 if1mctr1.word\r
+#define IF1MCTR1_NewDat if1mctr1.bit._NewDat\r
+#define IF1MCTR1_MsgLst if1mctr1.bit._MsgLst\r
+#define IF1MCTR1_IntPnd if1mctr1.bit._IntPnd\r
+#define IF1MCTR1_UMask if1mctr1.bit._UMask\r
+#define IF1MCTR1_TxIE if1mctr1.bit._TxIE\r
+#define IF1MCTR1_RxIE if1mctr1.bit._RxIE\r
+#define IF1MCTR1_RmtEn if1mctr1.bit._RmtEn\r
+#define IF1MCTR1_TxRqst if1mctr1.bit._TxRqst\r
+#define IF1MCTR1_EoB if1mctr1.bit._EoB\r
+#define IF1MCTR1_DLC3 if1mctr1.bit._DLC3\r
+#define IF1MCTR1_DLC2 if1mctr1.bit._DLC2\r
+#define IF1MCTR1_DLC1 if1mctr1.bit._DLC1\r
+#define IF1MCTR1_DLC0 if1mctr1.bit._DLC0\r
+#define IF1MCTR1_DLC if1mctr1.bitc._DLC\r
+__IO_EXTERN IO_LWORD if1dta121;  \r
+#define IF1DTA121 if1dta121\r
+__IO_EXTERN IO_WORD if1dta11;  \r
+#define IF1DTA11 if1dta11\r
+__IO_EXTERN IO_WORD if1dta21;  \r
+#define IF1DTA21 if1dta21\r
+__IO_EXTERN IO_LWORD if1dtb121;  \r
+#define IF1DTB121 if1dtb121\r
+__IO_EXTERN IO_WORD if1dtb11;  \r
+#define IF1DTB11 if1dtb11\r
+__IO_EXTERN IO_WORD if1dtb21;  \r
+#define IF1DTB21 if1dtb21\r
+__IO_EXTERN IO_LWORD if1dta_swp121;  \r
+#define IF1DTA_SWP121 if1dta_swp121\r
+__IO_EXTERN IO_WORD if1dta_swp21;  \r
+#define IF1DTA_SWP21 if1dta_swp21\r
+__IO_EXTERN IO_WORD if1dta_swp11;  \r
+#define IF1DTA_SWP11 if1dta_swp11\r
+__IO_EXTERN IO_LWORD if1dtb_swp121;  \r
+#define IF1DTB_SWP121 if1dtb_swp121\r
+__IO_EXTERN IO_WORD if1dtb_swp21;  \r
+#define IF1DTB_SWP21 if1dtb_swp21\r
+__IO_EXTERN IO_WORD if1dtb_swp11;  \r
+#define IF1DTB_SWP11 if1dtb_swp11\r
+__IO_EXTERN IF2CREQ1STR if2creq1;   /* CAN 1 IF 2 */\r
+#define IF2CREQ1 if2creq1.word\r
+#define IF2CREQ1_Busy if2creq1.bit._Busy\r
+#define IF2CREQ1_MN5 if2creq1.bit._MN5\r
+#define IF2CREQ1_MN4 if2creq1.bit._MN4\r
+#define IF2CREQ1_MN3 if2creq1.bit._MN3\r
+#define IF2CREQ1_MN2 if2creq1.bit._MN2\r
+#define IF2CREQ1_MN1 if2creq1.bit._MN1\r
+#define IF2CREQ1_MN0 if2creq1.bit._MN0\r
+#define IF2CREQ1_MN if2creq1.bitc._MN\r
+__IO_EXTERN IF2CMSK1STR if2cmsk1;  \r
+#define IF2CMSK1 if2cmsk1.word\r
+#define IF2CMSK1_WR if2cmsk1.bit._WR\r
+#define IF2CMSK1_Mask if2cmsk1.bit._Mask\r
+#define IF2CMSK1_Arb if2cmsk1.bit._Arb\r
+#define IF2CMSK1_Control if2cmsk1.bit._Control\r
+#define IF2CMSK1_CIP if2cmsk1.bit._CIP\r
+#define IF2CMSK1_TxReq if2cmsk1.bit._TxReq\r
+#define IF2CMSK1_DataA if2cmsk1.bit._DataA\r
+#define IF2CMSK1_DataB if2cmsk1.bit._DataB\r
+__IO_EXTERN IO_LWORD if2msk121;  \r
+#define IF2MSK121 if2msk121\r
+__IO_EXTERN IF2MSK21STR if2msk21;  \r
+#define IF2MSK21 if2msk21.word\r
+#define IF2MSK21_MXtd if2msk21.bit._MXtd\r
+#define IF2MSK21_MDir if2msk21.bit._MDir\r
+__IO_EXTERN IO_WORD if2msk11;  \r
+#define IF2MSK11 if2msk11\r
+__IO_EXTERN IO_LWORD if2arb121;  \r
+#define IF2ARB121 if2arb121\r
+__IO_EXTERN IF2ARB21STR if2arb21;  \r
+#define IF2ARB21 if2arb21.word\r
+#define IF2ARB21_MsgVal if2arb21.bit._MsgVal\r
+#define IF2ARB21_Xtd if2arb21.bit._Xtd\r
+#define IF2ARB21_DIR if2arb21.bit._DIR\r
+__IO_EXTERN IO_WORD if2arb11;  \r
+#define IF2ARB11 if2arb11\r
+__IO_EXTERN IF2MCTR1STR if2mctr1;  \r
+#define IF2MCTR1 if2mctr1.word\r
+#define IF2MCTR1_NewDat if2mctr1.bit._NewDat\r
+#define IF2MCTR1_MsgLst if2mctr1.bit._MsgLst\r
+#define IF2MCTR1_IntPnd if2mctr1.bit._IntPnd\r
+#define IF2MCTR1_UMask if2mctr1.bit._UMask\r
+#define IF2MCTR1_TxIE if2mctr1.bit._TxIE\r
+#define IF2MCTR1_RxIE if2mctr1.bit._RxIE\r
+#define IF2MCTR1_RmtEn if2mctr1.bit._RmtEn\r
+#define IF2MCTR1_TxRqst if2mctr1.bit._TxRqst\r
+#define IF2MCTR1_EoB if2mctr1.bit._EoB\r
+#define IF2MCTR1_DLC3 if2mctr1.bit._DLC3\r
+#define IF2MCTR1_DLC2 if2mctr1.bit._DLC2\r
+#define IF2MCTR1_DLC1 if2mctr1.bit._DLC1\r
+#define IF2MCTR1_DLC0 if2mctr1.bit._DLC0\r
+#define IF2MCTR1_DLC if2mctr1.bitc._DLC\r
+__IO_EXTERN IO_LWORD if2dta121;  \r
+#define IF2DTA121 if2dta121\r
+__IO_EXTERN IO_WORD if2dta11;  \r
+#define IF2DTA11 if2dta11\r
+__IO_EXTERN IO_WORD if2dta21;  \r
+#define IF2DTA21 if2dta21\r
+__IO_EXTERN IO_LWORD if2dtb121;  \r
+#define IF2DTB121 if2dtb121\r
+__IO_EXTERN IO_WORD if2dtb11;  \r
+#define IF2DTB11 if2dtb11\r
+__IO_EXTERN IO_WORD if2dtb21;  \r
+#define IF2DTB21 if2dtb21\r
+__IO_EXTERN IO_LWORD if2dta_swp121;  \r
+#define IF2DTA_SWP121 if2dta_swp121\r
+__IO_EXTERN IO_WORD if2dta_swp21;  \r
+#define IF2DTA_SWP21 if2dta_swp21\r
+__IO_EXTERN IO_WORD if2dta_swp11;  \r
+#define IF2DTA_SWP11 if2dta_swp11\r
+__IO_EXTERN IO_LWORD if2dtb_swp121;  \r
+#define IF2DTB_SWP121 if2dtb_swp121\r
+__IO_EXTERN IO_WORD if2dtb_swp21;  \r
+#define IF2DTB_SWP21 if2dtb_swp21\r
+__IO_EXTERN IO_WORD if2dtb_swp11;  \r
+#define IF2DTB_SWP11 if2dtb_swp11\r
+__IO_EXTERN IO_LWORD treqr121;   /* CAN 1 Status Flags */\r
+#define TREQR121 treqr121\r
+__IO_EXTERN IO_WORD treqr21;  \r
+#define TREQR21 treqr21\r
+__IO_EXTERN IO_WORD treqr11;  \r
+#define TREQR11 treqr11\r
+__IO_EXTERN IO_LWORD newdt121;  \r
+#define NEWDT121 newdt121\r
+__IO_EXTERN IO_WORD newdt21;  \r
+#define NEWDT21 newdt21\r
+__IO_EXTERN IO_WORD newdt11;  \r
+#define NEWDT11 newdt11\r
+__IO_EXTERN IO_LWORD intpnd121;  \r
+#define INTPND121 intpnd121\r
+__IO_EXTERN IO_WORD intpnd21;  \r
+#define INTPND21 intpnd21\r
+__IO_EXTERN IO_WORD intpnd11;  \r
+#define INTPND11 intpnd11\r
+__IO_EXTERN IO_LWORD msgval121;  \r
+#define MSGVAL121 msgval121\r
+__IO_EXTERN IO_WORD msgval21;  \r
+#define MSGVAL21 msgval21\r
+__IO_EXTERN IO_WORD msgval11;  \r
+#define MSGVAL11 msgval11\r
+__IO_EXTERN CTRLR2STR ctrlr2;   /* CAN 2 Control Register */\r
+#define CTRLR2 ctrlr2.word\r
+#define CTRLR2_Test ctrlr2.bit._Test\r
+#define CTRLR2_CCE ctrlr2.bit._CCE\r
+#define CTRLR2_DAR ctrlr2.bit._DAR\r
+#define CTRLR2_EIE ctrlr2.bit._EIE\r
+#define CTRLR2_SIE ctrlr2.bit._SIE\r
+#define CTRLR2_IE ctrlr2.bit._IE\r
+#define CTRLR2_Init ctrlr2.bit._Init\r
+__IO_EXTERN STATR2STR statr2;  \r
+#define STATR2 statr2.word\r
+#define STATR2_BOff statr2.bit._BOff\r
+#define STATR2_EWarn statr2.bit._EWarn\r
+#define STATR2_EPass statr2.bit._EPass\r
+#define STATR2_RxOK statr2.bit._RxOK\r
+#define STATR2_TxOK statr2.bit._TxOK\r
+#define STATR2_LEC2 statr2.bit._LEC2\r
+#define STATR2_LEC1 statr2.bit._LEC1\r
+#define STATR2_LEC0 statr2.bit._LEC0\r
+#define STATR2_LEC statr2.bitc._LEC\r
+__IO_EXTERN ERRCNT2STR errcnt2;  \r
+#define ERRCNT2 errcnt2.word\r
+#define ERRCNT2_RP errcnt2.bit._RP\r
+#define ERRCNT2_REC6 errcnt2.bit._REC6\r
+#define ERRCNT2_REC5 errcnt2.bit._REC5\r
+#define ERRCNT2_REC4 errcnt2.bit._REC4\r
+#define ERRCNT2_REC3 errcnt2.bit._REC3\r
+#define ERRCNT2_REC2 errcnt2.bit._REC2\r
+#define ERRCNT2_REC1 errcnt2.bit._REC1\r
+#define ERRCNT2_REC0 errcnt2.bit._REC0\r
+#define ERRCNT2_TEC7 errcnt2.bit._TEC7\r
+#define ERRCNT2_TEC6 errcnt2.bit._TEC6\r
+#define ERRCNT2_TEC5 errcnt2.bit._TEC5\r
+#define ERRCNT2_TEC4 errcnt2.bit._TEC4\r
+#define ERRCNT2_TEC3 errcnt2.bit._TEC3\r
+#define ERRCNT2_TEC2 errcnt2.bit._TEC2\r
+#define ERRCNT2_TEC1 errcnt2.bit._TEC1\r
+#define ERRCNT2_TEC0 errcnt2.bit._TEC0\r
+#define ERRCNT2_REC errcnt2.bitc._REC\r
+#define ERRCNT2_TEC errcnt2.bitc._TEC\r
+__IO_EXTERN BTR2STR btr2;  \r
+#define BTR2 btr2.word\r
+#define BTR2_Tseg22 btr2.bit._Tseg22\r
+#define BTR2_Tseg21 btr2.bit._Tseg21\r
+#define BTR2_Tseg20 btr2.bit._Tseg20\r
+#define BTR2_Tseg13 btr2.bit._Tseg13\r
+#define BTR2_Tseg12 btr2.bit._Tseg12\r
+#define BTR2_Tseg11 btr2.bit._Tseg11\r
+#define BTR2_Tseg10 btr2.bit._Tseg10\r
+#define BTR2_SJW1 btr2.bit._SJW1\r
+#define BTR2_SJW0 btr2.bit._SJW0\r
+#define BTR2_BRP5 btr2.bit._BRP5\r
+#define BTR2_BRP4 btr2.bit._BRP4\r
+#define BTR2_BRP3 btr2.bit._BRP3\r
+#define BTR2_BRP2 btr2.bit._BRP2\r
+#define BTR2_BRP1 btr2.bit._BRP1\r
+#define BTR2_BRP0 btr2.bit._BRP0\r
+#define BTR2_Tseg2 btr2.bitc._Tseg2\r
+#define BTR2_Tseg1 btr2.bitc._Tseg1\r
+#define BTR2_SJW btr2.bitc._SJW\r
+#define BTR2_BRP btr2.bitc._BRP\r
+__IO_EXTERN IO_WORD intr2;  \r
+#define INTR2 intr2\r
+__IO_EXTERN TESTR2STR testr2;  \r
+#define TESTR2 testr2.word\r
+#define TESTR2_Rx testr2.bit._Rx\r
+#define TESTR2_Tx1 testr2.bit._Tx1\r
+#define TESTR2_Tx0 testr2.bit._Tx0\r
+#define TESTR2_LBack testr2.bit._LBack\r
+#define TESTR2_Silent testr2.bit._Silent\r
+#define TESTR2_Basic testr2.bit._Basic\r
+#define TESTR2_Tx testr2.bitc._Tx\r
+__IO_EXTERN BRPER2STR brper2;  \r
+#define BRPER2 brper2.word\r
+#define BRPER2_BRPE3 brper2.bit._BRPE3\r
+#define BRPER2_BRPE2 brper2.bit._BRPE2\r
+#define BRPER2_BRPE1 brper2.bit._BRPE1\r
+#define BRPER2_BRPE0 brper2.bit._BRPE0\r
+#define BRPER2_BRPE brper2.bitc._BRPE\r
+__IO_EXTERN BRPE2STR brpe2;  \r
+#define BRPE2 brpe2.word\r
+__IO_EXTERN CBSYNC2STR cbsync2;  \r
+#define CBSYNC2 cbsync2.word\r
+__IO_EXTERN IF1CREQ2STR if1creq2;   /* CAN 2 IF 1 */\r
+#define IF1CREQ2 if1creq2.word\r
+#define IF1CREQ2_Busy if1creq2.bit._Busy\r
+#define IF1CREQ2_MN5 if1creq2.bit._MN5\r
+#define IF1CREQ2_MN4 if1creq2.bit._MN4\r
+#define IF1CREQ2_MN3 if1creq2.bit._MN3\r
+#define IF1CREQ2_MN2 if1creq2.bit._MN2\r
+#define IF1CREQ2_MN1 if1creq2.bit._MN1\r
+#define IF1CREQ2_MN0 if1creq2.bit._MN0\r
+#define IF1CREQ2_MN if1creq2.bitc._MN\r
+__IO_EXTERN IF1CMSK2STR if1cmsk2;  \r
+#define IF1CMSK2 if1cmsk2.word\r
+#define IF1CMSK2_WR if1cmsk2.bit._WR\r
+#define IF1CMSK2_Mask if1cmsk2.bit._Mask\r
+#define IF1CMSK2_Arb if1cmsk2.bit._Arb\r
+#define IF1CMSK2_Control if1cmsk2.bit._Control\r
+#define IF1CMSK2_CIP if1cmsk2.bit._CIP\r
+#define IF1CMSK2_TxReq if1cmsk2.bit._TxReq\r
+#define IF1CMSK2_DataA if1cmsk2.bit._DataA\r
+#define IF1CMSK2_DataB if1cmsk2.bit._DataB\r
+__IO_EXTERN IO_LWORD if1msk122;  \r
+#define IF1MSK122 if1msk122\r
+__IO_EXTERN IF1MSK22STR if1msk22;  \r
+#define IF1MSK22 if1msk22.word\r
+#define IF1MSK22_MXtd if1msk22.bit._MXtd\r
+#define IF1MSK22_MDir if1msk22.bit._MDir\r
+__IO_EXTERN IO_WORD if1msk12;  \r
+#define IF1MSK12 if1msk12\r
+__IO_EXTERN IO_LWORD if1arb122;  \r
+#define IF1ARB122 if1arb122\r
+__IO_EXTERN IF1ARB22STR if1arb22;  \r
+#define IF1ARB22 if1arb22.word\r
+#define IF1ARB22_MsgVal if1arb22.bit._MsgVal\r
+#define IF1ARB22_Xtd if1arb22.bit._Xtd\r
+#define IF1ARB22_DIR if1arb22.bit._DIR\r
+__IO_EXTERN IO_WORD if1arb12;  \r
+#define IF1ARB12 if1arb12\r
+__IO_EXTERN IF1MCTR2STR if1mctr2;  \r
+#define IF1MCTR2 if1mctr2.word\r
+#define IF1MCTR2_NewDat if1mctr2.bit._NewDat\r
+#define IF1MCTR2_MsgLst if1mctr2.bit._MsgLst\r
+#define IF1MCTR2_IntPnd if1mctr2.bit._IntPnd\r
+#define IF1MCTR2_UMask if1mctr2.bit._UMask\r
+#define IF1MCTR2_TxIE if1mctr2.bit._TxIE\r
+#define IF1MCTR2_RxIE if1mctr2.bit._RxIE\r
+#define IF1MCTR2_RmtEn if1mctr2.bit._RmtEn\r
+#define IF1MCTR2_TxRqst if1mctr2.bit._TxRqst\r
+#define IF1MCTR2_EoB if1mctr2.bit._EoB\r
+#define IF1MCTR2_DLC3 if1mctr2.bit._DLC3\r
+#define IF1MCTR2_DLC2 if1mctr2.bit._DLC2\r
+#define IF1MCTR2_DLC1 if1mctr2.bit._DLC1\r
+#define IF1MCTR2_DLC0 if1mctr2.bit._DLC0\r
+#define IF1MCTR2_DLC if1mctr2.bitc._DLC\r
+__IO_EXTERN IO_LWORD if1dta122;  \r
+#define IF1DTA122 if1dta122\r
+__IO_EXTERN IO_WORD if1dta12;  \r
+#define IF1DTA12 if1dta12\r
+__IO_EXTERN IO_WORD if1dta22;  \r
+#define IF1DTA22 if1dta22\r
+__IO_EXTERN IO_LWORD if1dtb122;  \r
+#define IF1DTB122 if1dtb122\r
+__IO_EXTERN IO_WORD if1dtb12;  \r
+#define IF1DTB12 if1dtb12\r
+__IO_EXTERN IO_WORD if1dtb22;  \r
+#define IF1DTB22 if1dtb22\r
+__IO_EXTERN IO_LWORD if1dta_swp122;  \r
+#define IF1DTA_SWP122 if1dta_swp122\r
+__IO_EXTERN IO_WORD if1dta_swp22;  \r
+#define IF1DTA_SWP22 if1dta_swp22\r
+__IO_EXTERN IO_WORD if1dta_swp12;  \r
+#define IF1DTA_SWP12 if1dta_swp12\r
+__IO_EXTERN IO_LWORD if1dtb_swp122;  \r
+#define IF1DTB_SWP122 if1dtb_swp122\r
+__IO_EXTERN IO_WORD if1dtb_swp22;  \r
+#define IF1DTB_SWP22 if1dtb_swp22\r
+__IO_EXTERN IO_WORD if1dtb_swp12;  \r
+#define IF1DTB_SWP12 if1dtb_swp12\r
+__IO_EXTERN IF2CREQ2STR if2creq2;   /* CAN 2 IF 2 */\r
+#define IF2CREQ2 if2creq2.word\r
+#define IF2CREQ2_Busy if2creq2.bit._Busy\r
+#define IF2CREQ2_MN5 if2creq2.bit._MN5\r
+#define IF2CREQ2_MN4 if2creq2.bit._MN4\r
+#define IF2CREQ2_MN3 if2creq2.bit._MN3\r
+#define IF2CREQ2_MN2 if2creq2.bit._MN2\r
+#define IF2CREQ2_MN1 if2creq2.bit._MN1\r
+#define IF2CREQ2_MN0 if2creq2.bit._MN0\r
+#define IF2CREQ2_MN if2creq2.bitc._MN\r
+__IO_EXTERN IF2CMSK2STR if2cmsk2;  \r
+#define IF2CMSK2 if2cmsk2.word\r
+#define IF2CMSK2_WR if2cmsk2.bit._WR\r
+#define IF2CMSK2_Mask if2cmsk2.bit._Mask\r
+#define IF2CMSK2_Arb if2cmsk2.bit._Arb\r
+#define IF2CMSK2_Control if2cmsk2.bit._Control\r
+#define IF2CMSK2_CIP if2cmsk2.bit._CIP\r
+#define IF2CMSK2_TxReq if2cmsk2.bit._TxReq\r
+#define IF2CMSK2_DataA if2cmsk2.bit._DataA\r
+#define IF2CMSK2_DataB if2cmsk2.bit._DataB\r
+__IO_EXTERN IO_LWORD if2msk122;  \r
+#define IF2MSK122 if2msk122\r
+__IO_EXTERN IF2MSK22STR if2msk22;  \r
+#define IF2MSK22 if2msk22.word\r
+#define IF2MSK22_MXtd if2msk22.bit._MXtd\r
+#define IF2MSK22_MDir if2msk22.bit._MDir\r
+__IO_EXTERN IO_WORD if2msk12;  \r
+#define IF2MSK12 if2msk12\r
+__IO_EXTERN IO_LWORD if2arb122;  \r
+#define IF2ARB122 if2arb122\r
+__IO_EXTERN IF2ARB22STR if2arb22;  \r
+#define IF2ARB22 if2arb22.word\r
+#define IF2ARB22_MsgVal if2arb22.bit._MsgVal\r
+#define IF2ARB22_Xtd if2arb22.bit._Xtd\r
+#define IF2ARB22_DIR if2arb22.bit._DIR\r
+__IO_EXTERN IO_WORD if2arb12;  \r
+#define IF2ARB12 if2arb12\r
+__IO_EXTERN IF2MCTR2STR if2mctr2;  \r
+#define IF2MCTR2 if2mctr2.word\r
+#define IF2MCTR2_NewDat if2mctr2.bit._NewDat\r
+#define IF2MCTR2_MsgLst if2mctr2.bit._MsgLst\r
+#define IF2MCTR2_IntPnd if2mctr2.bit._IntPnd\r
+#define IF2MCTR2_UMask if2mctr2.bit._UMask\r
+#define IF2MCTR2_TxIE if2mctr2.bit._TxIE\r
+#define IF2MCTR2_RxIE if2mctr2.bit._RxIE\r
+#define IF2MCTR2_RmtEn if2mctr2.bit._RmtEn\r
+#define IF2MCTR2_TxRqst if2mctr2.bit._TxRqst\r
+#define IF2MCTR2_EoB if2mctr2.bit._EoB\r
+#define IF2MCTR2_DLC3 if2mctr2.bit._DLC3\r
+#define IF2MCTR2_DLC2 if2mctr2.bit._DLC2\r
+#define IF2MCTR2_DLC1 if2mctr2.bit._DLC1\r
+#define IF2MCTR2_DLC0 if2mctr2.bit._DLC0\r
+#define IF2MCTR2_DLC if2mctr2.bitc._DLC\r
+__IO_EXTERN IO_LWORD if2dta122;  \r
+#define IF2DTA122 if2dta122\r
+__IO_EXTERN IO_WORD if2dta12;  \r
+#define IF2DTA12 if2dta12\r
+__IO_EXTERN IO_WORD if2dta22;  \r
+#define IF2DTA22 if2dta22\r
+__IO_EXTERN IO_LWORD if2dtb122;  \r
+#define IF2DTB122 if2dtb122\r
+__IO_EXTERN IO_WORD if2dtb12;  \r
+#define IF2DTB12 if2dtb12\r
+__IO_EXTERN IO_WORD if2dtb22;  \r
+#define IF2DTB22 if2dtb22\r
+__IO_EXTERN IO_LWORD if2dta_swp122;  \r
+#define IF2DTA_SWP122 if2dta_swp122\r
+__IO_EXTERN IO_WORD if2dta_swp22;  \r
+#define IF2DTA_SWP22 if2dta_swp22\r
+__IO_EXTERN IO_WORD if2dta_swp12;  \r
+#define IF2DTA_SWP12 if2dta_swp12\r
+__IO_EXTERN IO_LWORD if2dtb_swp122;  \r
+#define IF2DTB_SWP122 if2dtb_swp122\r
+__IO_EXTERN IO_WORD if2dtb_swp22;  \r
+#define IF2DTB_SWP22 if2dtb_swp22\r
+__IO_EXTERN IO_WORD if2dtb_swp12;  \r
+#define IF2DTB_SWP12 if2dtb_swp12\r
+__IO_EXTERN IO_LWORD treqr122;   /* CAN 2 Status Flags */\r
+#define TREQR122 treqr122\r
+__IO_EXTERN IO_WORD treqr22;  \r
+#define TREQR22 treqr22\r
+__IO_EXTERN IO_WORD treqr12;  \r
+#define TREQR12 treqr12\r
+__IO_EXTERN IO_LWORD newdt122;  \r
+#define NEWDT122 newdt122\r
+__IO_EXTERN IO_WORD newdt22;  \r
+#define NEWDT22 newdt22\r
+__IO_EXTERN IO_WORD newdt12;  \r
+#define NEWDT12 newdt12\r
+__IO_EXTERN IO_LWORD intpnd122;  \r
+#define INTPND122 intpnd122\r
+__IO_EXTERN IO_WORD intpnd22;  \r
+#define INTPND22 intpnd22\r
+__IO_EXTERN IO_WORD intpnd12;  \r
+#define INTPND12 intpnd12\r
+__IO_EXTERN IO_LWORD msgval122;  \r
+#define MSGVAL122 msgval122\r
+__IO_EXTERN IO_WORD msgval22;  \r
+#define MSGVAL22 msgval22\r
+__IO_EXTERN IO_WORD msgval12;  \r
+#define MSGVAL12 msgval12\r
+/* include : INC467_CAN.INC */\r
+/*-------------------------------------------------------------------*/\r
+/* INC467.CAN :  Old bit name of CAN Registers */\r
+\r
+/* alias macro definition for CAN Bits */\r
+#define BTR0_Tsg22 btr0.bit._Tseg22\r
+#define BTR0_Tsg21 btr0.bit._Tseg21\r
+#define BTR0_Tsg20 btr0.bit._Tseg20\r
+#define BTR0_Tsg2 btr0.bitc._Tseg2\r
+#define BTR0_Tsg13 btr0.bit._Tseg13\r
+#define BTR0_Tsg12 btr0.bit._Tseg12\r
+#define BTR0_Tsg11 btr0.bit._Tseg11\r
+#define BTR0_Tsg10 btr0.bit._Tseg10\r
+#define BTR0_Tsg1 btr0.bitc._Tseg1\r
+#define IF1CMSK0_Contr if1cmsk0.bit._Control\r
+#define IF2CMSK0_Contr if2cmsk0.bit._Control\r
+\r
+#define BTR1_Tsg22 btr1.bit._Tseg22\r
+#define BTR1_Tsg21 btr1.bit._Tseg21\r
+#define BTR1_Tsg20 btr1.bit._Tseg20\r
+#define BTR1_Tsg2 btr1.bitc._Tseg2\r
+#define BTR1_Tsg13 btr1.bit._Tseg13\r
+#define BTR1_Tsg12 btr1.bit._Tseg12\r
+#define BTR1_Tsg11 btr1.bit._Tseg11\r
+#define BTR1_Tsg10 btr1.bit._Tseg10\r
+#define BTR1_Tsg1 btr1.bitc._Tseg1\r
+#define IF1CMSK1_Contr if1cmsk1.bit._Control\r
+#define IF2CMSK1_Contr if2cmsk1.bit._Control\r
+\r
+#define BTR2_Tsg22 btr2.bit._Tseg22\r
+#define BTR2_Tsg21 btr2.bit._Tseg21\r
+#define BTR2_Tsg20 btr2.bit._Tseg20\r
+#define BTR2_Tsg2 btr2.bitc._Tseg2\r
+#define BTR2_Tsg13 btr2.bit._Tseg13\r
+#define BTR2_Tsg12 btr2.bit._Tseg12\r
+#define BTR2_Tsg11 btr2.bit._Tseg11\r
+#define BTR2_Tsg10 btr2.bit._Tseg10\r
+#define BTR2_Tsg1 btr2.bitc._Tseg1\r
+#define IF1CMSK2_Contr if1cmsk2.bit._Control\r
+#define IF2CMSK2_Contr if2cmsk2.bit._Control\r
+/*-------------------------------------------------------------------*/\r
+__IO_EXTERN BCTRLSTR bctrl;   /* EDSU/MPU Registers */\r
+#define BCTRL bctrl.lword\r
+#define BCTRL_SR bctrl.bit._SR\r
+#define BCTRL_SW bctrl.bit._SW\r
+#define BCTRL_SX bctrl.bit._SX\r
+#define BCTRL_UR bctrl.bit._UR\r
+#define BCTRL_UW bctrl.bit._UW\r
+#define BCTRL_UX bctrl.bit._UX\r
+#define BCTRL_FCPU bctrl.bit._FCPU\r
+#define BCTRL_FDMA bctrl.bit._FDMA\r
+#define BCTRL_EEMM bctrl.bit._EEMM\r
+#define BCTRL_PFD bctrl.bit._PFD\r
+#define BCTRL_SINT1 bctrl.bit._SINT1\r
+#define BCTRL_SINT0 bctrl.bit._SINT0\r
+#define BCTRL_EINT1 bctrl.bit._EINT1\r
+#define BCTRL_EINT0 bctrl.bit._EINT0\r
+#define BCTRL_EINTT bctrl.bit._EINTT\r
+#define BCTRL_EINTR bctrl.bit._EINTR\r
+#define BCTRL_SINT bctrl.bitc._SINT\r
+#define BCTRL_EINT bctrl.bitc._EINT\r
+__IO_EXTERN BSTATSTR bstat;  \r
+#define BSTAT bstat.lword\r
+#define BSTAT_IDX4 bstat.bit._IDX4\r
+#define BSTAT_IDX3 bstat.bit._IDX3\r
+#define BSTAT_IDX2 bstat.bit._IDX2\r
+#define BSTAT_IDX1 bstat.bit._IDX1\r
+#define BSTAT_IDX0 bstat.bit._IDX0\r
+#define BSTAT_CDMA bstat.bit._CDMA\r
+#define BSTAT_CSZ1 bstat.bit._CSZ1\r
+#define BSTAT_CSZ0 bstat.bit._CSZ0\r
+#define BSTAT_CRW1 bstat.bit._CRW1\r
+#define BSTAT_CRW0 bstat.bit._CRW0\r
+#define BSTAT_PV bstat.bit._PV\r
+#define BSTAT_RST bstat.bit._RST\r
+#define BSTAT_INT1 bstat.bit._INT1\r
+#define BSTAT_INT0 bstat.bit._INT0\r
+#define BSTAT_INTT bstat.bit._INTT\r
+#define BSTAT_INTR bstat.bit._INTR\r
+#define BSTAT_IDX bstat.bitc._IDX\r
+#define BSTAT_CSZ bstat.bitc._CSZ\r
+#define BSTAT_CRW bstat.bitc._CRW\r
+#define BSTAT_INT bstat.bitc._INT\r
+__IO_EXTERN IO_LWORD biac;  \r
+#define BIAC biac\r
+__IO_EXTERN IO_LWORD boac;  \r
+#define BOAC boac\r
+__IO_EXTERN BIRQSTR birq;  \r
+#define BIRQ birq.lword\r
+#define BIRQ_BD31 birq.bit._BD31\r
+#define BIRQ_BD30 birq.bit._BD30\r
+#define BIRQ_BD29 birq.bit._BD29\r
+#define BIRQ_BD28 birq.bit._BD28\r
+#define BIRQ_BD27 birq.bit._BD27\r
+#define BIRQ_BD26 birq.bit._BD26\r
+#define BIRQ_BD25 birq.bit._BD25\r
+#define BIRQ_BD24 birq.bit._BD24\r
+#define BIRQ_BD23 birq.bit._BD23\r
+#define BIRQ_BD22 birq.bit._BD22\r
+#define BIRQ_BD21 birq.bit._BD21\r
+#define BIRQ_BD20 birq.bit._BD20\r
+#define BIRQ_BD19 birq.bit._BD19\r
+#define BIRQ_BD18 birq.bit._BD18\r
+#define BIRQ_BD17 birq.bit._BD17\r
+#define BIRQ_BD16 birq.bit._BD16\r
+#define BIRQ_BD15 birq.bit._BD15\r
+#define BIRQ_BD14 birq.bit._BD14\r
+#define BIRQ_BD13 birq.bit._BD13\r
+#define BIRQ_BD12 birq.bit._BD12\r
+#define BIRQ_BD11 birq.bit._BD11\r
+#define BIRQ_BD10 birq.bit._BD10\r
+#define BIRQ_BD9 birq.bit._BD9\r
+#define BIRQ_BD8 birq.bit._BD8\r
+#define BIRQ_BD7 birq.bit._BD7\r
+#define BIRQ_BD6 birq.bit._BD6\r
+#define BIRQ_BD5 birq.bit._BD5\r
+#define BIRQ_BD4 birq.bit._BD4\r
+#define BIRQ_BD3 birq.bit._BD3\r
+#define BIRQ_BD2 birq.bit._BD2\r
+#define BIRQ_BD1 birq.bit._BD1\r
+#define BIRQ_BD0 birq.bit._BD0\r
+__IO_EXTERN BCR0STR bcr0;  \r
+#define BCR0 bcr0.lword\r
+#define BCR0_SRX1 bcr0.bit._SRX1\r
+#define BCR0_SW1 bcr0.bit._SW1\r
+#define BCR0_SRX0 bcr0.bit._SRX0\r
+#define BCR0_SW0 bcr0.bit._SW0\r
+#define BCR0_URX1 bcr0.bit._URX1\r
+#define BCR0_UW1 bcr0.bit._UW1\r
+#define BCR0_URX0 bcr0.bit._URX0\r
+#define BCR0_UW0 bcr0.bit._UW0\r
+#define BCR0_MPE bcr0.bit._MPE\r
+#define BCR0_COMB bcr0.bit._COMB\r
+#define BCR0_CTC1 bcr0.bit._CTC1\r
+#define BCR0_CTC0 bcr0.bit._CTC0\r
+#define BCR0_OBS1 bcr0.bit._OBS1\r
+#define BCR0_OBS0 bcr0.bit._OBS0\r
+#define BCR0_OBT1 bcr0.bit._OBT1\r
+#define BCR0_OBT0 bcr0.bit._OBT0\r
+#define BCR0_EP3 bcr0.bit._EP3\r
+#define BCR0_EP2 bcr0.bit._EP2\r
+#define BCR0_EP1 bcr0.bit._EP1\r
+#define BCR0_EP0 bcr0.bit._EP0\r
+#define BCR0_EM1 bcr0.bit._EM1\r
+#define BCR0_EM0 bcr0.bit._EM0\r
+#define BCR0_ER1 bcr0.bit._ER1\r
+#define BCR0_ER0 bcr0.bit._ER0\r
+#define BCR0_CTC bcr0.bitc._CTC\r
+#define BCR0_OBS bcr0.bitc._OBS\r
+#define BCR0_OBT bcr0.bitc._OBT\r
+#define BCR0_EP bcr0.bitc._EP\r
+#define BCR0_EM bcr0.bitc._EM\r
+#define BCR0_ER bcr0.bitc._ER\r
+__IO_EXTERN BCR1STR bcr1;  \r
+#define BCR1 bcr1.lword\r
+#define BCR1_SRX1 bcr1.bit._SRX1\r
+#define BCR1_SW1 bcr1.bit._SW1\r
+#define BCR1_SRX0 bcr1.bit._SRX0\r
+#define BCR1_SW0 bcr1.bit._SW0\r
+#define BCR1_URX1 bcr1.bit._URX1\r
+#define BCR1_UW1 bcr1.bit._UW1\r
+#define BCR1_URX0 bcr1.bit._URX0\r
+#define BCR1_UW0 bcr1.bit._UW0\r
+#define BCR1_MPE bcr1.bit._MPE\r
+#define BCR1_COMB bcr1.bit._COMB\r
+#define BCR1_CTC1 bcr1.bit._CTC1\r
+#define BCR1_CTC0 bcr1.bit._CTC0\r
+#define BCR1_OBS1 bcr1.bit._OBS1\r
+#define BCR1_OBS0 bcr1.bit._OBS0\r
+#define BCR1_OBT1 bcr1.bit._OBT1\r
+#define BCR1_OBT0 bcr1.bit._OBT0\r
+#define BCR1_EP3 bcr1.bit._EP3\r
+#define BCR1_EP2 bcr1.bit._EP2\r
+#define BCR1_EP1 bcr1.bit._EP1\r
+#define BCR1_EP0 bcr1.bit._EP0\r
+#define BCR1_EM1 bcr1.bit._EM1\r
+#define BCR1_EM0 bcr1.bit._EM0\r
+#define BCR1_ER1 bcr1.bit._ER1\r
+#define BCR1_ER0 bcr1.bit._ER0\r
+#define BCR1_CTC bcr1.bitc._CTC\r
+#define BCR1_OBS bcr1.bitc._OBS\r
+#define BCR1_OBT bcr1.bitc._OBT\r
+#define BCR1_EP bcr1.bitc._EP\r
+#define BCR1_EM bcr1.bitc._EM\r
+#define BCR1_ER bcr1.bitc._ER\r
+__IO_EXTERN BCR2STR bcr2;  \r
+#define BCR2 bcr2.lword\r
+#define BCR2_SRX1 bcr2.bit._SRX1\r
+#define BCR2_SW1 bcr2.bit._SW1\r
+#define BCR2_SRX0 bcr2.bit._SRX0\r
+#define BCR2_SW0 bcr2.bit._SW0\r
+#define BCR2_URX1 bcr2.bit._URX1\r
+#define BCR2_UW1 bcr2.bit._UW1\r
+#define BCR2_URX0 bcr2.bit._URX0\r
+#define BCR2_UW0 bcr2.bit._UW0\r
+#define BCR2_MPE bcr2.bit._MPE\r
+#define BCR2_COMB bcr2.bit._COMB\r
+#define BCR2_CTC1 bcr2.bit._CTC1\r
+#define BCR2_CTC0 bcr2.bit._CTC0\r
+#define BCR2_OBS1 bcr2.bit._OBS1\r
+#define BCR2_OBS0 bcr2.bit._OBS0\r
+#define BCR2_OBT1 bcr2.bit._OBT1\r
+#define BCR2_OBT0 bcr2.bit._OBT0\r
+#define BCR2_EP3 bcr2.bit._EP3\r
+#define BCR2_EP2 bcr2.bit._EP2\r
+#define BCR2_EP1 bcr2.bit._EP1\r
+#define BCR2_EP0 bcr2.bit._EP0\r
+#define BCR2_EM1 bcr2.bit._EM1\r
+#define BCR2_EM0 bcr2.bit._EM0\r
+#define BCR2_ER1 bcr2.bit._ER1\r
+#define BCR2_ER0 bcr2.bit._ER0\r
+#define BCR2_CTC bcr2.bitc._CTC\r
+#define BCR2_OBS bcr2.bitc._OBS\r
+#define BCR2_OBT bcr2.bitc._OBT\r
+#define BCR2_EP bcr2.bitc._EP\r
+#define BCR2_EM bcr2.bitc._EM\r
+#define BCR2_ER bcr2.bitc._ER\r
+__IO_EXTERN BCR3STR bcr3;  \r
+#define BCR3 bcr3.lword\r
+#define BCR3_SRX1 bcr3.bit._SRX1\r
+#define BCR3_SW1 bcr3.bit._SW1\r
+#define BCR3_SRX0 bcr3.bit._SRX0\r
+#define BCR3_SW0 bcr3.bit._SW0\r
+#define BCR3_URX1 bcr3.bit._URX1\r
+#define BCR3_UW1 bcr3.bit._UW1\r
+#define BCR3_URX0 bcr3.bit._URX0\r
+#define BCR3_UW0 bcr3.bit._UW0\r
+#define BCR3_MPE bcr3.bit._MPE\r
+#define BCR3_COMB bcr3.bit._COMB\r
+#define BCR3_CTC1 bcr3.bit._CTC1\r
+#define BCR3_CTC0 bcr3.bit._CTC0\r
+#define BCR3_OBS1 bcr3.bit._OBS1\r
+#define BCR3_OBS0 bcr3.bit._OBS0\r
+#define BCR3_OBT1 bcr3.bit._OBT1\r
+#define BCR3_OBT0 bcr3.bit._OBT0\r
+#define BCR3_EP3 bcr3.bit._EP3\r
+#define BCR3_EP2 bcr3.bit._EP2\r
+#define BCR3_EP1 bcr3.bit._EP1\r
+#define BCR3_EP0 bcr3.bit._EP0\r
+#define BCR3_EM1 bcr3.bit._EM1\r
+#define BCR3_EM0 bcr3.bit._EM0\r
+#define BCR3_ER1 bcr3.bit._ER1\r
+#define BCR3_ER0 bcr3.bit._ER0\r
+#define BCR3_CTC bcr3.bitc._CTC\r
+#define BCR3_OBS bcr3.bitc._OBS\r
+#define BCR3_OBT bcr3.bitc._OBT\r
+#define BCR3_EP bcr3.bitc._EP\r
+#define BCR3_EM bcr3.bitc._EM\r
+#define BCR3_ER bcr3.bitc._ER\r
+__IO_EXTERN BCR4STR bcr4;  \r
+#define BCR4 bcr4.lword\r
+#define BCR4_SRX1 bcr4.bit._SRX1\r
+#define BCR4_SW1 bcr4.bit._SW1\r
+#define BCR4_SRX0 bcr4.bit._SRX0\r
+#define BCR4_SW0 bcr4.bit._SW0\r
+#define BCR4_URX1 bcr4.bit._URX1\r
+#define BCR4_UW1 bcr4.bit._UW1\r
+#define BCR4_URX0 bcr4.bit._URX0\r
+#define BCR4_UW0 bcr4.bit._UW0\r
+#define BCR4_MPE bcr4.bit._MPE\r
+#define BCR4_COMB bcr4.bit._COMB\r
+#define BCR4_CTC1 bcr4.bit._CTC1\r
+#define BCR4_CTC0 bcr4.bit._CTC0\r
+#define BCR4_OBS1 bcr4.bit._OBS1\r
+#define BCR4_OBS0 bcr4.bit._OBS0\r
+#define BCR4_OBT1 bcr4.bit._OBT1\r
+#define BCR4_OBT0 bcr4.bit._OBT0\r
+#define BCR4_EP3 bcr4.bit._EP3\r
+#define BCR4_EP2 bcr4.bit._EP2\r
+#define BCR4_EP1 bcr4.bit._EP1\r
+#define BCR4_EP0 bcr4.bit._EP0\r
+#define BCR4_EM1 bcr4.bit._EM1\r
+#define BCR4_EM0 bcr4.bit._EM0\r
+#define BCR4_ER1 bcr4.bit._ER1\r
+#define BCR4_ER0 bcr4.bit._ER0\r
+#define BCR4_CTC bcr4.bitc._CTC\r
+#define BCR4_OBS bcr4.bitc._OBS\r
+#define BCR4_OBT bcr4.bitc._OBT\r
+#define BCR4_EP bcr4.bitc._EP\r
+#define BCR4_EM bcr4.bitc._EM\r
+#define BCR4_ER bcr4.bitc._ER\r
+__IO_EXTERN BCR5STR bcr5;  \r
+#define BCR5 bcr5.lword\r
+#define BCR5_SRX1 bcr5.bit._SRX1\r
+#define BCR5_SW1 bcr5.bit._SW1\r
+#define BCR5_SRX0 bcr5.bit._SRX0\r
+#define BCR5_SW0 bcr5.bit._SW0\r
+#define BCR5_URX1 bcr5.bit._URX1\r
+#define BCR5_UW1 bcr5.bit._UW1\r
+#define BCR5_URX0 bcr5.bit._URX0\r
+#define BCR5_UW0 bcr5.bit._UW0\r
+#define BCR5_MPE bcr5.bit._MPE\r
+#define BCR5_COMB bcr5.bit._COMB\r
+#define BCR5_CTC1 bcr5.bit._CTC1\r
+#define BCR5_CTC0 bcr5.bit._CTC0\r
+#define BCR5_OBS1 bcr5.bit._OBS1\r
+#define BCR5_OBS0 bcr5.bit._OBS0\r
+#define BCR5_OBT1 bcr5.bit._OBT1\r
+#define BCR5_OBT0 bcr5.bit._OBT0\r
+#define BCR5_EP3 bcr5.bit._EP3\r
+#define BCR5_EP2 bcr5.bit._EP2\r
+#define BCR5_EP1 bcr5.bit._EP1\r
+#define BCR5_EP0 bcr5.bit._EP0\r
+#define BCR5_EM1 bcr5.bit._EM1\r
+#define BCR5_EM0 bcr5.bit._EM0\r
+#define BCR5_ER1 bcr5.bit._ER1\r
+#define BCR5_ER0 bcr5.bit._ER0\r
+#define BCR5_CTC bcr5.bitc._CTC\r
+#define BCR5_OBS bcr5.bitc._OBS\r
+#define BCR5_OBT bcr5.bitc._OBT\r
+#define BCR5_EP bcr5.bitc._EP\r
+#define BCR5_EM bcr5.bitc._EM\r
+#define BCR5_ER bcr5.bitc._ER\r
+__IO_EXTERN BCR6STR bcr6;  \r
+#define BCR6 bcr6.lword\r
+#define BCR6_SRX1 bcr6.bit._SRX1\r
+#define BCR6_SW1 bcr6.bit._SW1\r
+#define BCR6_SRX0 bcr6.bit._SRX0\r
+#define BCR6_SW0 bcr6.bit._SW0\r
+#define BCR6_URX1 bcr6.bit._URX1\r
+#define BCR6_UW1 bcr6.bit._UW1\r
+#define BCR6_URX0 bcr6.bit._URX0\r
+#define BCR6_UW0 bcr6.bit._UW0\r
+#define BCR6_MPE bcr6.bit._MPE\r
+#define BCR6_COMB bcr6.bit._COMB\r
+#define BCR6_CTC1 bcr6.bit._CTC1\r
+#define BCR6_CTC0 bcr6.bit._CTC0\r
+#define BCR6_OBS1 bcr6.bit._OBS1\r
+#define BCR6_OBS0 bcr6.bit._OBS0\r
+#define BCR6_OBT1 bcr6.bit._OBT1\r
+#define BCR6_OBT0 bcr6.bit._OBT0\r
+#define BCR6_EP3 bcr6.bit._EP3\r
+#define BCR6_EP2 bcr6.bit._EP2\r
+#define BCR6_EP1 bcr6.bit._EP1\r
+#define BCR6_EP0 bcr6.bit._EP0\r
+#define BCR6_EM1 bcr6.bit._EM1\r
+#define BCR6_EM0 bcr6.bit._EM0\r
+#define BCR6_ER1 bcr6.bit._ER1\r
+#define BCR6_ER0 bcr6.bit._ER0\r
+#define BCR6_CTC bcr6.bitc._CTC\r
+#define BCR6_OBS bcr6.bitc._OBS\r
+#define BCR6_OBT bcr6.bitc._OBT\r
+#define BCR6_EP bcr6.bitc._EP\r
+#define BCR6_EM bcr6.bitc._EM\r
+#define BCR6_ER bcr6.bitc._ER\r
+__IO_EXTERN BCR7STR bcr7;  \r
+#define BCR7 bcr7.lword\r
+#define BCR7_SRX1 bcr7.bit._SRX1\r
+#define BCR7_SW1 bcr7.bit._SW1\r
+#define BCR7_SRX0 bcr7.bit._SRX0\r
+#define BCR7_SW0 bcr7.bit._SW0\r
+#define BCR7_URX1 bcr7.bit._URX1\r
+#define BCR7_UW1 bcr7.bit._UW1\r
+#define BCR7_URX0 bcr7.bit._URX0\r
+#define BCR7_UW0 bcr7.bit._UW0\r
+#define BCR7_MPE bcr7.bit._MPE\r
+#define BCR7_COMB bcr7.bit._COMB\r
+#define BCR7_CTC1 bcr7.bit._CTC1\r
+#define BCR7_CTC0 bcr7.bit._CTC0\r
+#define BCR7_OBS1 bcr7.bit._OBS1\r
+#define BCR7_OBS0 bcr7.bit._OBS0\r
+#define BCR7_OBT1 bcr7.bit._OBT1\r
+#define BCR7_OBT0 bcr7.bit._OBT0\r
+#define BCR7_EP3 bcr7.bit._EP3\r
+#define BCR7_EP2 bcr7.bit._EP2\r
+#define BCR7_EP1 bcr7.bit._EP1\r
+#define BCR7_EP0 bcr7.bit._EP0\r
+#define BCR7_EM1 bcr7.bit._EM1\r
+#define BCR7_EM0 bcr7.bit._EM0\r
+#define BCR7_ER1 bcr7.bit._ER1\r
+#define BCR7_ER0 bcr7.bit._ER0\r
+#define BCR7_CTC bcr7.bitc._CTC\r
+#define BCR7_OBS bcr7.bitc._OBS\r
+#define BCR7_OBT bcr7.bitc._OBT\r
+#define BCR7_EP bcr7.bitc._EP\r
+#define BCR7_EM bcr7.bitc._EM\r
+#define BCR7_ER bcr7.bitc._ER\r
+__IO_EXTERN IO_LWORD bad0;  \r
+#define BAD0 bad0\r
+__IO_EXTERN IO_LWORD bad1;  \r
+#define BAD1 bad1\r
+__IO_EXTERN IO_LWORD bad2;  \r
+#define BAD2 bad2\r
+__IO_EXTERN IO_LWORD bad3;  \r
+#define BAD3 bad3\r
+__IO_EXTERN IO_LWORD bad4;  \r
+#define BAD4 bad4\r
+__IO_EXTERN IO_LWORD bad5;  \r
+#define BAD5 bad5\r
+__IO_EXTERN IO_LWORD bad6;  \r
+#define BAD6 bad6\r
+__IO_EXTERN IO_LWORD bad7;  \r
+#define BAD7 bad7\r
+__IO_EXTERN IO_LWORD bad8;  \r
+#define BAD8 bad8\r
+__IO_EXTERN IO_LWORD bad9;  \r
+#define BAD9 bad9\r
+__IO_EXTERN IO_LWORD bad10;  \r
+#define BAD10 bad10\r
+__IO_EXTERN IO_LWORD bad11;  \r
+#define BAD11 bad11\r
+__IO_EXTERN IO_LWORD bad12;  \r
+#define BAD12 bad12\r
+__IO_EXTERN IO_LWORD bad13;  \r
+#define BAD13 bad13\r
+__IO_EXTERN IO_LWORD bad14;  \r
+#define BAD14 bad14\r
+__IO_EXTERN IO_LWORD bad15;  \r
+#define BAD15 bad15\r
+__IO_EXTERN IO_LWORD fsv1;   /* FSV & BSV Registers */\r
+#define FSV1 fsv1\r
+__IO_EXTERN IO_LWORD bsv1;  \r
+#define BSV1 bsv1\r
+__IO_EXTERN IO_LWORD fsv2;  \r
+#define FSV2 fsv2\r
+__IO_EXTERN IO_LWORD bsv2;  \r
+#define BSV2 bsv2\r
+/* include : INC467_BSYNC.INC */\r
+/*-------------------------------------------------------------------*/\r
+/* INC467.BSYNC :  Macros Bus Sync*/\r
+\r
+#define RB_SYNC if(RBSYNC)\r
+#define CB_SYNC0 if(CBSYNC0)\r
+#define CB_SYNC1 if(CBSYNC1)\r
+#define CB_SYNC2 if(CBSYNC2)\r
+/*-------------------------------------------------------------------*/\r
+#endif                   /* __FASM__    */\r
+#endif                   /* __MB91XXX_H */\r
+#endif                   /* __IO_DEFINE */\r

diff --git a/Demo/MB91460_Softune/SRC/serial/serial.c b/Demo/MB91460_Softune/SRC/serial/serial.c
new file mode 100644 (file)
index 0000000..5b400b1
--- /dev/null
+++ b/Demo/MB91460_Softune/SRC/serial/serial.c
@@ -0,0 +1,207 @@
+/*\r
+       FreeRTOS.org V4.7.0 - Copyright (C) 2003-2007 Richard Barry.\r
+\r
+       This file is part of the FreeRTOS.org distribution.\r
+\r
+       FreeRTOS.org is free software; you can redistribute it and/or modify\r
+       it under the terms of the GNU General Public License as published by\r
+       the Free Software Foundation; either version 2 of the License, or\r
+       (at your option) any later version.\r
+\r
+       FreeRTOS.org is distributed in the hope that it will be useful,\r
+       but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+       MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\r
+       GNU General Public License for more details.\r
+\r
+       You should have received a copy of the GNU General Public License\r
+       along with FreeRTOS.org; if not, write to the Free Software\r
+       Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA\r
+\r
+       A special exception to the GPL can be applied should you wish to distribute\r
+       a combined work that includes FreeRTOS.org, without being obliged to provide\r
+       the source code for any proprietary components.  See the licensing section \r
+       of http://www.FreeRTOS.org for full details of how and when the exception\r
+       can be applied.\r
+\r
+       ***************************************************************************\r
+       See http://www.FreeRTOS.org for documentation, latest information, license \r
+       and contact details.  Please ensure to read the configuration and relevant \r
+       port sections of the online documentation.\r
+\r
+       Also see http://www.SafeRTOS.com a version that has been certified for use\r
+       in safety critical systems, plus commercial licensing, development and\r
+       support options.\r
+       ***************************************************************************\r
+*/\r
+\r
+\r
+/* BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER.   \r
+ * \r
+ * This file only supports UART 2\r
+ */\r
+\r
+/* Standard includes. */\r
+#include <stdlib.h>\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "queue.h"\r
+#include "task.h"\r
+\r
+/* Demo application includes. */\r
+#include "serial.h"\r
+\r
+/* The queue used to hold received characters. */\r
+static xQueueHandle xRxedChars; \r
+\r
+/* The queue used to hold characters waiting transmission. */\r
+static xQueueHandle xCharsForTx; \r
+\r
+static volatile portSHORT sTHREEmpty;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength )\r
+{\r
+//unsigned portLONG ulBaudRateCount;\r
+\r
+       portENTER_CRITICAL();\r
+       {\r
+               /* Create the queues used by the com test task. */\r
+               xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) );\r
+               xCharsForTx = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) );\r
+\r
+                /* Initialize UART asynchronous mode */\r
+               BGR02 = configPER_CLOCK_HZ / ulWantedBaud;\r
+                 \r
+               SCR02 = 0x17;    /* 8N1 */\r
+               SMR02 = 0x0d;    /* enable SOT3, Reset, normal mode */\r
+               SSR02 = 0x02;    /* LSB first, enable receive interrupts */\r
+\r
+               PFR20_D0 = 1;    // enable UART\r
+               PFR20_D1 = 1;    // enable UART\r
+\r
+               EPFR20_D1 = 0;   // enable UART\r
+       }\r
+       portEXIT_CRITICAL();\r
+       \r
+       /* Unlike other ports, this serial code does not allow for more than one\r
+       com port.  We therefore don't return a pointer to a port structure and can\r
+       instead just return NULL. */\r
+       return NULL;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime )\r
+{\r
+       /* Get the next character from the buffer.  Return false if no characters\r
+       are available, or arrive before xBlockTime expires. */\r
+       if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) )\r
+       {\r
+               return pdTRUE;\r
+       }\r
+       else\r
+       {\r
+               return pdFALSE;\r
+       }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime )\r
+{\r
+signed portBASE_TYPE xReturn;\r
+\r
+       /* Transmit a character. */\r
+       portENTER_CRITICAL();\r
+       {\r
+               if( sTHREEmpty == pdTRUE )\r
+               {\r
+                       /* If sTHREEmpty is true then the UART Tx ISR has indicated that \r
+                       there are no characters queued to be transmitted - so we can\r
+                       write the character directly to the shift Tx register. */\r
+                       sTHREEmpty = pdFALSE;\r
+                       TDR02 = cOutChar;\r
+                       xReturn = pdPASS;\r
+               }\r
+               else\r
+               {\r
+                       /* sTHREEmpty is false, so there are still characters waiting to be\r
+                       transmitted.  We have to queue this character so it gets \r
+                       transmitted     in turn. */\r
+\r
+                       /* Return false if after the block time there is no room on the Tx \r
+                       queue.  It is ok to block inside a critical section as each task\r
+                       maintains it's own critical section status. */\r
+                       if (xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) == pdTRUE)\r
+                       {\r
+                               xReturn = pdPASS;\r
+                       }\r
+                       else\r
+                       {\r
+                               xReturn = pdFAIL;\r
+                       }\r
+               }\r
+               \r
+               if (pdPASS == xReturn)\r
+               {\r
+                       /* Turn on the Tx interrupt so the ISR will remove the character from the\r
+                       queue and send it.   This does not need to be in a critical section as\r
+                       if the interrupt has already removed the character the next interrupt\r
+                       will simply turn off the Tx interrupt again. */\r
+                       SSR02_TIE = 1;\r
+               }\r
+               \r
+       }\r
+       portEXIT_CRITICAL();\r
+\r
+       return pdPASS;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * UART RX interrupt service routine.\r
+ */\r
+ __interrupt void UART2_RxISR (void)\r
+{\r
+       signed portCHAR cChar;\r
+\r
+       /* Get the character from the UART and post it on the queue of Rxed \r
+       characters. */\r
+       cChar = RDR02;\r
+\r
+       if( xQueueSendFromISR( xRxedChars, &cChar, pdFALSE ) )\r
+       {\r
+               /*If the post causes a task to wake force a context switch \r
+               as the woken task may have a higher priority than the task we have \r
+               interrupted. */\r
+               portYIELDFromISR();\r
+       }\r
+}\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * UART Tx interrupt service routine.\r
+ */\r
+__interrupt void UART2_TxISR (void)\r
+{\r
+       signed portCHAR cChar;\r
+       signed portBASE_TYPE xTaskWoken;\r
+\r
+       /* The previous character has been transmitted.  See if there are any\r
+       further characters waiting transmission. */\r
+       if( xQueueReceiveFromISR( xCharsForTx, &cChar, &xTaskWoken ) == pdTRUE )\r
+       {\r
+               /* There was another character queued - transmit it now. */\r
+               TDR02 = cChar;\r
+       }\r
+       else\r
+       {\r
+               /* There were no other characters to transmit. */\r
+               sTHREEmpty = pdTRUE;\r
+               \r
+               /* Disable transmit interrupts */\r
+               SSR02_TIE = 0;\r
+       }\r
+}\r
+\r

diff --git a/Demo/MB91460_Softune/SRC/utility/taskutility.c b/Demo/MB91460_Softune/SRC/utility/taskutility.c
new file mode 100644 (file)
index 0000000..8b5a4b1
--- /dev/null
+++ b/Demo/MB91460_Softune/SRC/utility/taskutility.c
@@ -0,0 +1,189 @@
+/* THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */\r
+/* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */\r
+/* ELIGIBILITY FOR ANY PURPOSES.                                             */\r
+/*                 (C) Fujitsu Microelectronics Europe GmbH                  */\r
+/*------------------------------------------------------------------------\r
+  taskutility.C\r
+  - \r
+-------------------------------------------------------------------------*/\r
+\r
+ \r
+/*************************@INCLUDE_START************************/\r
+#include "mb91467d.h"\r
+#include "vectors.h"\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+\r
+static void vUART5Task( void *pvParameters );\r
+\r
+/**************************@INCLUDE_END*************************/\r
+/*********************@GLOBAL_VARIABLES_START*******************/\r
+const char ASCII[] = "0123456789ABCDEF";\r
+\r
+xTaskHandle UART_TaskHandle;\r
+\r
+void InitUart5(void)\r
+{\r
+       //Initialize UART asynchronous mode\r
+       BGR05 = 1666; //  9600 Baud @ 16MHz\r
+       \r
+       SCR05 = 0x17;    // 7N2\r
+       SMR05 = 0x0d;    // enable SOT3, Reset, normal mode\r
+       SSR05 = 0x00;    // LSB first\r
+       \r
+       PFR19_D4 = 1;    // enable UART\r
+       PFR19_D5 = 1;    // enable UART\r
+\r
+       //EPFR19 = 0x00;   // enable UART\r
+       \r
+       SSR05_RIE = 1;\r
+}\r
+\r
+void Putch5(char ch)         /* sends a char */\r
+{\r
+  while (SSR05_TDRE == 0);    /* wait for transmit buffer empty        */\r
+  TDR05 = ch;                 /* put ch into buffer                    */\r
+}\r
+\r
+char Getch5(void)            /* waits for and returns incomming char   */\r
+{\r
+  volatile unsigned ch;\r
+  \r
+  while(SSR05_RDRF == 0);       /* wait for data received      */\r
+  if (SSR05_ORE)              /* overrun error                 */\r
+  {\r
+    ch = RDR05;              /* reset error flags              */\r
+    return (char)(-1);\r
+  }\r
+  else\r
+  return (RDR05);            /* return char                    */\r
+}\r
+\r
+void Puts5(const char *Name5)  /* Puts a String to UART */\r
+{\r
+  volatile portSHORT i,len;\r
+  len = strlen(Name5);\r
+       \r
+  for (i=0; i<strlen(Name5); i++)   /* go through string                     */\r
+  {\r
+    if (Name5[i] == 10)\r
+      Putch5(13);\r
+    Putch5(Name5[i]);              /* send it out                           */\r
+  }\r
+}\r
+\r
+void Puthex5(unsigned long n, unsigned char digits)\r
+{\r
+   unsigned portCHAR digit=0,div=0,i;\r
+\r
+   div=(4*(digits-1)); /* init shift divisor */\r
+   for (i=0;i<digits;i++)\r
+   {\r
+     digit = ((n >> div)&0xF); /* get hex-digit value */\r
+        Putch5(digit + ((digit < 0xA) ? '0' : 'A' - 0xA));\r
+     div-=4;                   /* next digit shift */\r
+   }\r
+}\r
+\r
+void Putdec5(unsigned long x, int digits)\r
+{\r
+       portSHORT i;\r
+       portCHAR buf[10],sign=1;\r
+       \r
+       if (digits < 0) {     /* should be print of zero? */\r
+         digits *= (-1);\r
+         sign =1;\r
+       }  \r
+       buf[digits]='\0';                       /* end sign of string */\r
+       \r
+       for (i=digits; i>0; i--) {\r
+               buf[i-1] = ASCII[x % 10];\r
+               x = x/10;\r
+       }\r
+\r
+    if ( sign )\r
+    {\r
+         for (i=0; buf[i]=='0'; i++) { /* no print of zero */\r
+               if ( i<digits-1)\r
+                       buf[i] = ' ';\r
+         }             \r
+    }\r
+    \r
+       Puts5(buf);                                     /* send string */\r
+}\r
+\r
+void vTraceListTasks( unsigned portBASE_TYPE uxPriority )\r
+{\r
+       portENTER_CRITICAL();\r
+       InitUart5();\r
+       portENTER_CRITICAL();\r
+       xTaskCreate( vUART5Task , ( signed portCHAR * ) "UART4",  ( unsigned portSHORT ) 2048, ( void * ) NULL, uxPriority, &UART_TaskHandle );\r
+}\r
+\r
+static void vUART5Task( void *pvParameters )\r
+{\r
+       portCHAR tasklist_buff[512], trace_buff[512];\r
+       unsigned portLONG trace_len, j;\r
+       \r
+       unsigned portCHAR ch;   \r
+       \r
+       Puts5("\n -------------MB91467D FreeRTOS DEMO Task List and Trace Utility----------- \n");\r
+\r
+       for(;;)\r
+       {\r
+               Puts5("\n\rPress any of the following keys for the corresponding functionality: ");\r
+\r
+               Puts5("\n\r1: To call vTaskList() and display current task status ");\r
+\r
+               Puts5("\n\r2: To call vTaskStartTrace() and to display trace results once the trace ends");\r
+\r
+               SSR05_RIE=1;\r
+\r
+               vTaskSuspend(NULL);\r
+\r
+               ch=Getch5();\r
+\r
+               switch ( ch ) \r
+               {\r
+                       case '1':\r
+                               vTaskList( ( signed char * ) tasklist_buff );\r
+                               Puts5("\n\rThe current task list is as follows....");\r
+                               Puts5("\n\r----------------------------------------------");\r
+                               Puts5("\n\rName          State  Priority  Stack   Number");\r
+                               Puts5("\n\r----------------------------------------------");\r
+                               Puts5(tasklist_buff);\r
+                               Puts5("\r----------------------------------------------");\r
+                               break;\r
+\r
+                       case '2':\r
+                               vTaskStartTrace(( signed char * ) trace_buff, 512);\r
+                               Puts5("\n\rThe trace started!!");\r
+                               vTaskDelay( ( portTickType ) 450);\r
+                               trace_len = ulTaskEndTrace();\r
+                               Puts5("\n\rThe trace ended!!");\r
+                               Puts5("\n\rThe trace is as follows....");\r
+                               Puts5("\n\r--------------------------------------------------------");\r
+                               Puts5("\n\r  Tick     | Task Number  |     Tick     | Task Number  |");\r
+                               Puts5("\n\r--------------------------------------------------------\n\r");\r
+                               for( j = 0 ; j < trace_len ; j++ )\r
+                               {\r
+                                       Puthex5(trace_buff[j],2);\r
+                                       if(j%4==3) Puts5("   |   ");\r
+                                       if(j%16==15) Puts5("\n");\r
+                               }\r
+                               Puts5("\r--------------------------------------------------------");\r
+                               break;\r
+                               \r
+                       default:\r
+                               break;\r
+               }\r
+               Puts5("\n");\r
+       }\r
+}\r
+\r
+__interrupt void UART5_RxISR ( void )\r
+{\r
+       SSR05_RIE=0;\r
+       vTaskResume( UART_TaskHandle );\r
+}\r

diff --git a/Demo/MB91460_Softune/SRC/vectors.c b/Demo/MB91460_Softune/SRC/vectors.c
new file mode 100644 (file)
index 0000000..a98ca6c
--- /dev/null
+++ b/Demo/MB91460_Softune/SRC/vectors.c
@@ -0,0 +1,352 @@
+/* THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */\r
+/* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */\r
+/* ELIGIBILITY FOR ANY PURPOSES.                                             */\r
+/*                 (C) Fujitsu Microelectronics Europe GmbH                  */\r
+/*------------------------------------------------------------------------\r
+  VECTORS.C\r
+  - Interrupt level (priority) setting\r
+  - Interrupt vector definition\r
+\r
+  31.04.05  1.00   UMa    Initial Version\r
+  08.11.05  1.01   MSt    SWB Mondeb switch for ICR00 Register added\r
+  27.02.06  1.02   UMa    added comment in DefaultIRQHandler \r
+  17.03.06  1.03   UMa    comment out ICR01\r
+  28.07.06  1.04   UMa    changed comment\r
+  06.10.06  1.05   UMa    changed DefaultIRQHandler\r
+-------------------------------------------------------------------------*/\r
+\r
+#include "mb91467d.h"\r
+#include "watchdog.h"\r
+\r
+/*------------------------------------------------------------------------\r
+  InitIrqLevels()\r
+\r
+  This function  pre-sets all interrupt control registers. It can be used\r
+  to set all interrupt priorities in static applications. If this file\r
+  contains assignments to dedicated resources, verify  that the\r
+  appropriate controller is used. Not all devices of the MB91460 Series\r
+  offer all recources.\r
+\r
+  NOTE: value 31 disables the interrupt and value 16 sets highest priority.\r
+-------------------------------------------------------------------------*/\r
+void InitIrqLevels(void)\r
+{\r
+    /*  ICRxx */ \r
+/* Softune Workbench Monitor Debugger is using ext int0 for abort function */\r
+/*  ICR00 = 31;  *//* External Interrupt 0         */\r
+                   /* External Interrupt 1         */                 \r
+    ICR01 = 31;    /* External Interrupt 2         */\r
+                   /* External Interrupt 3         */\r
+    ICR02 = 31;    /* External Interrupt 4         */\r
+                   /* External Interrupt 5         */\r
+    ICR03 = 31;    /* External Interrupt 6         */\r
+                   /* External Interrupt 7         */\r
+    ICR04 = 31;    /* External Interrupt 8         */\r
+                   /* External Interrupt 9         */\r
+    ICR05 = 31;    /* External Interrupt 10        */\r
+                   /* External Interrupt 11        */\r
+    ICR06 = 31;    /* External Interrupt 12        */\r
+                   /* External Interrupt 13        */\r
+    ICR07 = 31;    /* External Interrupt 14        */\r
+                   /* External Interrupt 15        */\r
+    ICR08 = 23;    /* Reload Timer 0               */\r
+                   /* Reload Timer 1               */\r
+    ICR09 = 31;    /* Reload Timer 2               */\r
+                   /* Reload Timer 3               */\r
+    ICR10 = 31;    /* Reload Timer 4               */\r
+                   /* Reload Timer 5               */\r
+    ICR11 = 31;    /* Reload Timer 6               */\r
+                   /* Reload Timer 7               */\r
+    ICR12 = 31;    /* Free Run Timer 0             */\r
+                   /* Free Run Timer 1             */\r
+    ICR13 = 31;    /* Free Run Timer 2             */\r
+                   /* Free Run Timer 3             */\r
+    ICR14 = 31;    /* Free Run Timer 4             */\r
+                   /* Free Run Timer 5             */\r
+    ICR15 = 31;    /* Free Run Timer 6             */\r
+                   /* Free Run Timer 7             */\r
+    ICR16 = 31;    /* CAN 0                        */\r
+                   /* CAN 1                        */\r
+    ICR17 = 31;    /* CAN 2                        */\r
+                   /* CAN 3                        */\r
+    ICR18 = 31;    /* CAN 4                        */\r
+                   /* CAN 5                        */\r
+    ICR19 = 31;    /* USART (LIN) 0 RX             */\r
+                   /* USART (LIN) 0 TX             */\r
+    ICR20 = 31;    /* USART (LIN) 1 RX             */\r
+                   /* USART (LIN) 1 TX             */\r
+    ICR21 = 21;    /* USART (LIN) 2 RX             */\r
+                   /* USART (LIN) 2 TX             */\r
+    ICR22 = 31;    /* USART (LIN) 3 RX             */\r
+                   /* USART (LIN) 3 TX             */\r
+    ICR23 = 23;    /* System Reserved              */\r
+                   /* Delayed Interrupt            */\r
+    ICR24 = 31;    /* System Reserved              */\r
+                   /* System Reserved              */\r
+    ICR25 = 31;    /* USART (LIN, FIFO) 4 RX       */\r
+                   /* USART (LIN, FIFO) 4 TX       */\r
+    ICR26 = 21;    /* USART (LIN, FIFO) 5 RX       */\r
+                   /* USART (LIN, FIFO) 5 TX       */\r
+    ICR27 = 31;    /* USART (LIN, FIFO) 6 RX       */\r
+                   /* USART (LIN, FIFO) 6 TX       */\r
+    ICR28 = 31;    /* USART (LIN, FIFO) 7 RX       */\r
+                   /* USART (LIN, FIFO) 7 TX       */\r
+    ICR29 = 31;    /* I2C 0 / I2C 2                */\r
+                   /* I2C 1 / I2C 3                */\r
+    ICR30 = 31;    /* USART (LIN, FIFO) 8 RX       */\r
+                   /* USART (LIN, FIFO) 8 TX       */\r
+    ICR31 = 31;    /* USART (LIN, FIFO) 9 RX       */\r
+                   /* USART (LIN, FIFO) 9 TX       */\r
+    ICR32 = 31;    /* USART (LIN, FIFO) 10 RX      */\r
+                   /* USART (LIN, FIFO) 10 TX      */\r
+    ICR33 = 31;    /* USART (LIN, FIFO) 11 RX      */\r
+                   /* USART (LIN, FIFO) 11 TX      */\r
+    ICR34 = 31;    /* USART (LIN, FIFO) 12 RX      */\r
+                   /* USART (LIN, FIFO) 12 TX      */\r
+    ICR35 = 31;    /* USART (LIN, FIFO) 13 RX      */\r
+                   /* USART (LIN, FIFO) 13 TX      */\r
+    ICR36 = 31;    /* USART (LIN, FIFO) 14 RX      */\r
+                   /* USART (LIN, FIFO) 14 TX      */\r
+    ICR37 = 31;    /* USART (LIN, FIFO) 15 RX      */\r
+                   /* USART (LIN, FIFO) 15 TX      */\r
+    ICR38 = 31;    /* Input Capture 0              */\r
+                   /* Input Capture 1              */\r
+    ICR39 = 31;    /* Input Capture 2              */\r
+                   /* Input Capture 3              */\r
+    ICR40 = 31;    /* Input Capture 4              */\r
+                   /* Input Capture 5              */\r
+    ICR41 = 31;    /* Input Capture 6              */\r
+                   /* Input Capture 7              */\r
+    ICR42 = 31;    /* Output Compare 0             */\r
+                   /* Output Compare 1             */\r
+    ICR43 = 31;    /* Output Compare 2             */\r
+                   /* Output Compare 3             */\r
+    ICR44 = 31;    /* Output Compare 4             */\r
+                   /* Output Compare 5             */\r
+    ICR45 = 31;    /* Output Compare 6             */\r
+                   /* Output Compare 7             */\r
+    ICR46 = 31;    /* Sound Generator              */\r
+                   /* Phase Frequ. Modulator       */\r
+    ICR47 = 31;    /* System Reserved              */\r
+                   /* System Reserved              */\r
+    ICR48 = 31;    /* Prog. Pulse Gen. 0           */\r
+                   /* Prog. Pulse Gen. 1           */\r
+    ICR49 = 31;    /* Prog. Pulse Gen. 2           */\r
+                   /* Prog. Pulse Gen. 3           */\r
+    ICR50 = 31;    /* Prog. Pulse Gen. 4           */\r
+                   /* Prog. Pulse Gen. 5           */\r
+    ICR51 = 31;    /* Prog. Pulse Gen. 6           */\r
+                   /* Prog. Pulse Gen. 7           */\r
+    ICR52 = 31;    /* Prog. Pulse Gen. 8           */\r
+                   /* Prog. Pulse Gen. 9           */\r
+    ICR53 = 31;    /* Prog. Pulse Gen. 10          */\r
+                   /* Prog. Pulse Gen. 11          */\r
+    ICR54 = 31;    /* Prog. Pulse Gen. 12          */\r
+                   /* Prog. Pulse Gen. 13          */\r
+    ICR55 = 31;    /* Prog. Pulse Gen. 14          */\r
+                   /* Prog. Pulse Gen. 15          */\r
+    ICR56 = 31;    /* Up/Down Counter 0            */\r
+                   /* Up/Down Counter 1            */\r
+    ICR57 = 31;    /* Up/Down Counter 2            */\r
+                   /* Up/Down Counter 3            */\r
+    ICR58 = 31;    /* Real Time Clock              */\r
+                   /* Calibration Unit             */\r
+    ICR59 = 31;    /* A/D Converter 0              */\r
+                   /* -                            */\r
+    ICR60 = 31;    /* Alarm Comperator 0           */\r
+                   /* Alarm Comperator 1           */\r
+    ICR61 = 31;    /* Low Volage Detector          */\r
+                   /* SMC Zero Point 0-5           */\r
+    ICR62 = 31;    /* Timebase Overflow            */\r
+                   /* PLL Clock Gear               */\r
+    ICR63 = 31;    /* DMA Controller               */\r
+                   /* Main/Sub OSC stability wait  */\r
+}\r
+\r
+\r
+/*------------------------------------------------------------------------\r
+  Prototypes\r
+  \r
+  Add your own prototypes here. Each vector definition needs is proto-\r
+  type. Either do it here or include a header file containing them.\r
+-------------------------------------------------------------------------*/\r
+__interrupt void DefaultIRQHandler (void);\r
+extern __interrupt void ReloadTimer0_IRQHandler ( void );\r
+extern __interrupt void vPortYield ( void );\r
+extern __interrupt void vPortYieldDelayed (void);\r
+\r
+extern __interrupt void UART2_RxISR(void);\r
+extern __interrupt void UART2_TxISR(void);\r
+extern __interrupt void UART5_RxISR(void);\r
+\r
+/*------------------------------------------------------------------------\r
+   Vector definiton\r
+\r
+   Use following statements to define vectors. All resource related\r
+   vectors are predefined. Remaining software interrupts can be added here\r
+   as well.\r
+------------------------------------------------------------------------*/\r
+#pragma intvect 0xBFF8            0     /* (fixed) reset vector         */\r
+#pragma intvect 0x06000000        1     /* (fixed) Mode Byte            */\r
+\r
+#pragma intvect DefaultIRQHandler 15    /* Non Maskable Interrupt       */\r
+#pragma intvect DefaultIRQHandler 16    /* External Interrupt 0         */\r
+#pragma intvect DefaultIRQHandler 17    /* External Interrupt 1         */\r
+\r
+#pragma intvect DefaultIRQHandler 18    /* External Interrupt 2         */\r
+\r
+#pragma intvect DefaultIRQHandler 19    /* External Interrupt 3         */\r
+#pragma intvect DefaultIRQHandler 20    /* External Interrupt 4         */\r
+#pragma intvect DefaultIRQHandler 21    /* External Interrupt 5         */\r
+#pragma intvect DefaultIRQHandler 22    /* External Interrupt 6         */\r
+#pragma intvect DefaultIRQHandler 23    /* External Interrupt 7         */\r
+#pragma intvect DefaultIRQHandler 24    /* External Interrupt 8         */\r
+#pragma intvect DefaultIRQHandler 25    /* External Interrupt 9         */\r
+#pragma intvect DefaultIRQHandler 26    /* External Interrupt 10        */\r
+#pragma intvect DefaultIRQHandler 27    /* External Interrupt 11        */\r
+#pragma intvect DefaultIRQHandler 28    /* External Interrupt 12        */\r
+#pragma intvect DefaultIRQHandler 29    /* External Interrupt 13        */\r
+#pragma intvect DefaultIRQHandler 30    /* External Interrupt 14        */\r
+#pragma intvect DefaultIRQHandler 31    /* External Interrupt 15        */\r
+\r
+#pragma intvect ReloadTimer0_IRQHandler 32    /* Reload Timer 0               */\r
+\r
+#pragma intvect DefaultIRQHandler 33    /* Reload Timer 1               */\r
+#pragma intvect DefaultIRQHandler 34    /* Reload Timer 2               */\r
+#pragma intvect DefaultIRQHandler 35    /* Reload Timer 3               */\r
+#pragma intvect DefaultIRQHandler 36    /* Reload Timer 4               */\r
+#pragma intvect DefaultIRQHandler 37    /* Reload Timer 5               */\r
+#pragma intvect DefaultIRQHandler 38    /* Reload Timer 6               */\r
+#pragma intvect DefaultIRQHandler 39    /* Reload Timer 7               */\r
+#pragma intvect DefaultIRQHandler 40    /* Free Run Timer 0             */\r
+#pragma intvect DefaultIRQHandler 41    /* Free Run Timer 1             */\r
+#pragma intvect DefaultIRQHandler 42    /* Free Run Timer 2             */\r
+#pragma intvect DefaultIRQHandler 43    /* Free Run Timer 3             */\r
+#pragma intvect DefaultIRQHandler 44    /* Free Run Timer 4             */\r
+#pragma intvect DefaultIRQHandler 45    /* Free Run Timer 5             */\r
+#pragma intvect DefaultIRQHandler 46    /* Free Run Timer 6             */\r
+#pragma intvect DefaultIRQHandler 47    /* Free Run Timer 7             */\r
+#pragma intvect DefaultIRQHandler 48    /* CAN 0                        */\r
+#pragma intvect DefaultIRQHandler 49    /* CAN 1                        */\r
+#pragma intvect DefaultIRQHandler 50    /* CAN 2                        */\r
+#pragma intvect DefaultIRQHandler 51    /* CAN 3                        */\r
+#pragma intvect DefaultIRQHandler 52    /* CAN 4                        */\r
+#pragma intvect DefaultIRQHandler 53    /* CAN 5                        */\r
+#pragma intvect DefaultIRQHandler 54    /* USART (LIN) 0 RX             */\r
+#pragma intvect DefaultIRQHandler 55    /* USART (LIN) 0 TX             */\r
+#pragma intvect DefaultIRQHandler 56    /* USART (LIN) 1 RX             */\r
+#pragma intvect DefaultIRQHandler 57    /* USART (LIN) 1 TX             */\r
+\r
+#pragma intvect UART2_RxISR      58    /* USART (LIN) 2 RX             */\r
+#pragma intvect UART2_TxISR      59    /* USART (LIN) 2 TX             */\r
+\r
+#pragma intvect DefaultIRQHandler 60    /* USART (LIN) 3 RX             */\r
+#pragma intvect DefaultIRQHandler 61    /* USART (LIN) 3 TX             */\r
+#pragma intvect DefaultIRQHandler 62    /* System Reserved              */\r
+\r
+#pragma intvect vPortYieldDelayed 63    /* Delayed Interrupt            */\r
+\r
+#pragma intvect vPortYield        64    /* INT 64                       */\r
+\r
+#pragma intvect DefaultIRQHandler 65    /* System Reserved              */\r
+#pragma intvect DefaultIRQHandler 66    /* USART (LIN, FIFO) 4 RX       */\r
+#pragma intvect DefaultIRQHandler 67    /* USART (LIN, FIFO) 4 TX       */\r
+\r
+#pragma intvect UART5_RxISR       68    /* USART (LIN, FIFO) 5 RX       */\r
+\r
+#pragma intvect DefaultIRQHandler 69    /* USART (LIN, FIFO) 5 TX       */\r
+#pragma intvect DefaultIRQHandler 70    /* USART (LIN, FIFO) 6 RX       */\r
+#pragma intvect DefaultIRQHandler 71    /* USART (LIN, FIFO) 6 TX       */\r
+#pragma intvect DefaultIRQHandler 72    /* USART (LIN, FIFO) 7 RX       */\r
+#pragma intvect DefaultIRQHandler 73    /* USART (LIN, FIFO) 7 TX       */\r
+#pragma intvect DefaultIRQHandler 74    /* I2C 0 / I2C 2                */\r
+#pragma intvect DefaultIRQHandler 75    /* I2C 1 / I2C 3                */\r
+#pragma intvect DefaultIRQHandler 76    /* USART (LIN, FIFO) 8 RX       */\r
+#pragma intvect DefaultIRQHandler 77    /* USART (LIN, FIFO) 8 TX       */\r
+#pragma intvect DefaultIRQHandler 78    /* USART (LIN, FIFO) 9 RX       */\r
+#pragma intvect DefaultIRQHandler 79    /* USART (LIN, FIFO) 9 TX       */\r
+#pragma intvect DefaultIRQHandler 80    /* USART (LIN, FIFO) 10 RX      */\r
+#pragma intvect DefaultIRQHandler 81    /* USART (LIN, FIFO) 10 TX      */\r
+#pragma intvect DefaultIRQHandler 82    /* USART (LIN, FIFO) 11 RX      */\r
+#pragma intvect DefaultIRQHandler 83    /* USART (LIN, FIFO) 11 TX      */\r
+#pragma intvect DefaultIRQHandler 84    /* USART (LIN, FIFO) 12 RX      */\r
+#pragma intvect DefaultIRQHandler 85    /* USART (LIN, FIFO) 12 TX      */\r
+#pragma intvect DefaultIRQHandler 86    /* USART (LIN, FIFO) 13 RX      */\r
+#pragma intvect DefaultIRQHandler 87    /* USART (LIN, FIFO) 13 TX      */\r
+#pragma intvect DefaultIRQHandler 88    /* USART (LIN, FIFO) 14 RX      */\r
+#pragma intvect DefaultIRQHandler 89    /* USART (LIN, FIFO) 14 TX      */\r
+#pragma intvect DefaultIRQHandler 90    /* USART (LIN, FIFO) 15 RX      */\r
+#pragma intvect DefaultIRQHandler 91    /* USART (LIN, FIFO) 15 TX      */\r
+#pragma intvect DefaultIRQHandler 92    /* Input Capture 0              */\r
+#pragma intvect DefaultIRQHandler 93    /* Input Capture 1              */\r
+#pragma intvect DefaultIRQHandler 94    /* Input Capture 2              */\r
+#pragma intvect DefaultIRQHandler 95    /* Input Capture 3              */\r
+#pragma intvect DefaultIRQHandler 96    /* Input Capture 4              */\r
+#pragma intvect DefaultIRQHandler 97    /* Input Capture 5              */\r
+#pragma intvect DefaultIRQHandler 98    /* Input Capture 6              */\r
+#pragma intvect DefaultIRQHandler 99    /* Input Capture 7              */\r
+#pragma intvect DefaultIRQHandler 100   /* Output Compare 0             */\r
+#pragma intvect DefaultIRQHandler 101   /* Output Compare 1             */\r
+#pragma intvect DefaultIRQHandler 102   /* Output Compare 2             */\r
+#pragma intvect DefaultIRQHandler 103   /* Output Compare 3             */\r
+#pragma intvect DefaultIRQHandler 104   /* Output Compare 4             */\r
+#pragma intvect DefaultIRQHandler 105   /* Output Compare 5             */\r
+#pragma intvect DefaultIRQHandler 106   /* Output Compare 6             */\r
+#pragma intvect DefaultIRQHandler 107   /* Output Compare 7             */\r
+#pragma intvect DefaultIRQHandler 108   /* Sound Generator              */\r
+#pragma intvect DefaultIRQHandler 109   /* Phase Frequ. Modulator       */\r
+#pragma intvect DefaultIRQHandler 110   /* System Reserved              */\r
+#pragma intvect DefaultIRQHandler 111   /* System Reserved              */\r
+#pragma intvect DefaultIRQHandler 112   /* Prog. Pulse Gen. 0           */\r
+#pragma intvect DefaultIRQHandler 113   /* Prog. Pulse Gen. 1           */\r
+#pragma intvect DefaultIRQHandler 114   /* Prog. Pulse Gen. 2           */\r
+#pragma intvect DefaultIRQHandler 115   /* Prog. Pulse Gen. 3           */\r
+#pragma intvect DefaultIRQHandler 116   /* Prog. Pulse Gen. 4           */\r
+#pragma intvect DefaultIRQHandler 117   /* Prog. Pulse Gen. 5           */\r
+#pragma intvect DefaultIRQHandler 118   /* Prog. Pulse Gen. 6           */\r
+#pragma intvect DefaultIRQHandler 119   /* Prog. Pulse Gen. 7           */\r
+#pragma intvect DefaultIRQHandler 120   /* Prog. Pulse Gen. 8           */\r
+#pragma intvect DefaultIRQHandler 121   /* Prog. Pulse Gen. 9           */\r
+#pragma intvect DefaultIRQHandler 122   /* Prog. Pulse Gen. 10          */\r
+#pragma intvect DefaultIRQHandler 123   /* Prog. Pulse Gen. 11          */\r
+#pragma intvect DefaultIRQHandler 124   /* Prog. Pulse Gen. 12          */\r
+#pragma intvect DefaultIRQHandler 125   /* Prog. Pulse Gen. 13          */\r
+#pragma intvect DefaultIRQHandler 126   /* Prog. Pulse Gen. 14          */\r
+#pragma intvect DefaultIRQHandler 127   /* Prog. Pulse Gen. 15          */\r
+#pragma intvect DefaultIRQHandler 128   /* Up/Down Counter 0            */\r
+#pragma intvect DefaultIRQHandler 129   /* Up/Down Counter 1            */\r
+#pragma intvect DefaultIRQHandler 130   /* Up/Down Counter 2            */\r
+#pragma intvect DefaultIRQHandler 131   /* Up/Down Counter 3            */\r
+#pragma intvect DefaultIRQHandler 132   /* Real Time Clock              */\r
+#pragma intvect DefaultIRQHandler 133   /* Calibration Unit             */\r
+#pragma intvect DefaultIRQHandler 134   /* A/D Converter 0              */\r
+#pragma intvect DefaultIRQHandler 135   /* -                            */\r
+#pragma intvect DefaultIRQHandler 136   /* Alarm Comperator 0           */\r
+#pragma intvect DefaultIRQHandler 137   /* Alarm Comperator 1           */\r
+#pragma intvect DefaultIRQHandler 138   /* Low Volage Detector          */\r
+#pragma intvect DefaultIRQHandler 139   /* SMC Zero Point 0-5           */\r
+#pragma intvect DefaultIRQHandler 140   /* Timebase Overflow            */\r
+#pragma intvect DefaultIRQHandler 141   /* PLL Clock Gear               */\r
+#pragma intvect DefaultIRQHandler 142   /* DMA Controller               */\r
+#pragma intvect DefaultIRQHandler 143   /* Main/Sub OSC stability wait  */\r
+#pragma intvect 0xFFFFFFFF        144   /* Boot Sec. Vector (MB91V460A) */\r
+\r
+/*------------------------------------------------------------------------\r
+  DefaultIRQHandler()\r
+\r
+  This function is a placeholder for all vector definitions. Either use\r
+  your own placeholder or add necessary code here. \r
+-------------------------------------------------------------------------*/\r
+__interrupt \r
+void DefaultIRQHandler (void)\r
+{\r
+    /* RB_SYNC; */                      /* Synchronisation with R-Bus   */\r
+                                        /* May be required, if there is */\r
+                                        /* no R-Bus access after the    */\r
+                                        /* reset of the interrupt flag  */\r
+\r
+    __DI();                             /* disable interrupts           */\r
+    while(1)\r
+        Kick_Watchdog();                /* feed hardware watchdog       */\r
+                                        /* halt system */\r
+}\r

diff --git a/Demo/MB91460_Softune/SRC/vectors.h b/Demo/MB91460_Softune/SRC/vectors.h
new file mode 100644 (file)
index 0000000..058e000
--- /dev/null
+++ b/Demo/MB91460_Softune/SRC/vectors.h
@@ -0,0 +1,13 @@
+/* THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */\r
+/* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */\r
+/* ELIGIBILITY FOR ANY PURPOSES.                                             */\r
+/*                 (C) Fujitsu Microelectronics Europe GmbH                  */\r
+/*----------------------------------------------------------------------------\r
+  VECTORS.h\r
+\r
+\r
+  06.10.06  1.00   UMa    Initial Version\r
+-----------------------------------------------------------------------------*/\r
+\r
+\r
+void InitIrqLevels(void);\r

diff --git a/Demo/MB91460_Softune/SRC/watchdog/watchdog.c b/Demo/MB91460_Softune/SRC/watchdog/watchdog.c
new file mode 100644 (file)
index 0000000..77d7a85
--- /dev/null
+++ b/Demo/MB91460_Softune/SRC/watchdog/watchdog.c
@@ -0,0 +1,59 @@
+/* THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */\r
+/* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */\r
+/* ELIGIBILITY FOR ANY PURPOSES.                                             */\r
+/*                 (C) Fujitsu Microelectronics Europe GmbH                  */\r
+/*------------------------------------------------------------------------\r
+  watchdog.c\r
+  - This file contains the function deefinition for hardware watchdog.\r
+-------------------------------------------------------------------------*/\r
+\r
+#include "mb91467d.h"\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "watchdog.h"\r
+\r
+/*---------------------------------------------------------------------------\r
+ * Setup Watchdog\r
+ *---------------------------------------------------------------------------*/ \r
+#if WATCHDOG != WTC_NONE\r
+void InitWatchdog(void)\r
+{\r
+       HWWDE_ED = WTC_PER_2_16;        /* Set the watchdog period as 655.36 ms */\r
+}\r
+#endif\r
+\r
+/*---------------------------------------------------------------------------\r
+ * The below task clears the watchdog and blocks itself for WTC_CLR_PER ticks.\r
+ *---------------------------------------------------------------------------*/\r
+#if WATCHDOG == WTC_IN_TASK    \r
+static void prvWatchdogTask    ( void *pvParameters )\r
+{\r
+       const portTickType xFrequency = WTC_CLR_PER;\r
+    portTickType xLastWakeTime;\r
+\r
+       /* Get currrent tick count */ \r
+       xLastWakeTime = xTaskGetTickCount();\r
+       \r
+    for( ; ; )\r
+    {\r
+               /* Get currrent tick count */ \r
+           xLastWakeTime = xTaskGetTickCount();\r
+               \r
+               Kick_Watchdog();\r
+                          \r
+               /* Block the task for WTC_CLR_PER ticks (300 ms) at watchdog overflow \r
+               period of WTC_PER_2_16 CLKRC cycles (655.36 ms) */ \r
+               vTaskDelayUntil( &xLastWakeTime, xFrequency );\r
+       } \r
+}\r
+#endif\r
+\r
+/*---------------------------------------------------------------------------\r
+ * The below function creates hardware watchdog task.\r
+ *---------------------------------------------------------------------------*/ \r
+#if WATCHDOG == WTC_IN_TASK    \r
+void vStartWatchdogTask( unsigned portSHORT uxPriority )\r
+{\r
+       xTaskCreate( prvWatchdogTask , ( signed portCHAR * ) "KickWTC",   portMINIMAL_STACK_SIZE, ( void * ) NULL, uxPriority, ( xTaskHandle * ) NULL );        \r
+}\r
+#endif\r

diff --git a/Demo/MB91460_Softune/SRC/watchdog/watchdog.h b/Demo/MB91460_Softune/SRC/watchdog/watchdog.h
new file mode 100644 (file)
index 0000000..9f95d24
--- /dev/null
+++ b/Demo/MB91460_Softune/SRC/watchdog/watchdog.h
@@ -0,0 +1,46 @@
+/* THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */\r
+/* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */\r
+/* ELIGIBILITY FOR ANY PURPOSES.                                             */\r
+/*                 (C) Fujitsu Microelectronics Europe GmbH                  */\r
+/*------------------------------------------------------------------------\r
+  watchdog.h\r
+  - This file contains the defines and function declaration for hardware watchdog.\r
+-------------------------------------------------------------------------*/\r
+/* \r
+ * Clear watchdog defines \r
+ */\r
+#define        WTC_NONE        0               /* Don't initialize and clear watchdog */\r
+#define        WTC_IN_TASK     1               /* Clear Watchdog in dedicated task */\r
+#define        WTC_IN_TICK     2               /* Clear Watchdog in TICK Hook */\r
+#define        WTC_IN_IDLE     3               /* Clear Watchdog in Idle Hook */\r
+\r
+#define WATCHDOG WTC_IN_TASK   /* Clear Watchdog in vWatchdogTask() */\r
+/*------------------------------------------------------------------------*/\r
+/* \r
+ * Watchdog period defines\r
+ */\r
+#define        WTC_PER_2_16    0       /* The watchdog period is 2^16 CLKRC cycles */\r
+#define        WTC_PER_2_17    1       /* The watchdog period is 2^17 CLKRC cycles */\r
+#define        WTC_PER_2_18    2       /* The watchdog period is 2^18 CLKRC cycles */\r
+#define        WTC_PER_2_19    3       /* The watchdog period is 2^19 CLKRC cycles */\r
+/*------------------------------------------------------------------------*/\r
+/* \r
+ * After every WTC_CLR_PER ticks the watchdog would be cleared in the prvWatchdogTask(). \r
+ * This period needs to be chosen in accordance with the current CLKRC (100KHz or 2MHz)\r
+ * and the above setting WTC_PER_2_XX.\r
+ */\r
+#define        WTC_CLR_PER             30      /* The watchdog clear period in RTOS ticks */\r
+/*------------------------------------------------------------------------*/\r
+/* \r
+ * Kick_watchdog Macro to clear watchdog \r
+ */\r
+#define Kick_Watchdog()                                                        \\r
+       {               HWWD = 0x10;                                            \\r
+       }\r
+/*------------------------------------------------------------------------*/\r
+/* \r
+ * Watchdog function declarations \r
+ */\r
+void InitWatchdog (void);\r
+void vStartWatchdogTask(unsigned portSHORT);\r
+\r

diff --git a/Demo/MB91460_Softune/STANDALONE/MB2198-01-COM1.sup b/Demo/MB91460_Softune/STANDALONE/MB2198-01-COM1.sup
new file mode 100644 (file)
index 0000000..0745dbf
--- /dev/null
+++ b/Demo/MB91460_Softune/STANDALONE/MB2198-01-COM1.sup
@@ -0,0 +1,227 @@
+[Information]\r
+DebChangeFlag=0\r
+MCUChangeFlag=0\r
+[Version]\r
+Version=1\r
+Level=1\r
+Revision=0\r
+[Debug Type]\r
+Type=0\r
+Virtual CPU File=wv911e2.dll\r
+Monitor Load=1\r
+Monitor Load Condition=Enable\r
+Mode=FFFF\r
+Monitor Combination Version=10100\r
+Mcu Name=MB91F467D\r
+Monitor Select Count=1\r
+Monitor Connect Condition0=4\r
+Monitor Combination0=8/1/2:RealTimeMemory:,8/9/10:RAM Checker:C:48&1\r
+Core ID=0\r
+ChangeFlag=Disable\r
+[Device]\r
+Communication=RS COM1 115200 \r
+ProductID=0\r
+Protocol=3\r
+[Target]\r
+AutoLoad=Enable\r
+Before Batch File=PRC\set_ROMS.prc\r
+After Batch File=PRC\set_RESET.prc\r
+Non AutoMap=Enable\r
+Load DebInfo Only=Disable\r
+Ondemand Load Condition=Disable\r
+[Start]\r
+Batch File=\r
+[Window]\r
+Flag=Enable\r
+AssemblySize=458 4 878 244\r
+AssemblyState=0\r
+AssemblyFGColor=0 0 255\r
+RegisterSize=745 0 891 555\r
+RegisterState=0\r
+MemorySize=569 -3 836 574\r
+MemoryState=0\r
+Assembly Address=H'0000BFF8\r
+Memory Address=H'00000390\r
+Memory Mode=H'00000002\r
+Memory Ascii=H'00000001\r
+Memory SplitRow=0\r
+RMemory Address=H'00000000\r
+RMemory Mode=H'FFFFFFFF\r
+RMemory Ascii=H'00000001\r
+RMemory SplitRow=0\r
+Trace ViewMode=FFFFFFFF\r
+Command Max History=H'00000032\r
+Source Display Mode=Enable\r
+Source Multi Mode=Enable\r
+Source Ask Mode=Enable\r
+Source Active Mode=Enable\r
+Source PC Color=255 255 0\r
+Source Scope Color=255 0 255\r
+Source Back Trace=255 0 255\r
+Register Change Color=255 0 0\r
+Perfomance Mode=H'00000001\r
+Perfomance Scale=1 0 0.000000 0.000000\r
+RMemory Change Color=255 0 0\r
+RMemory Invalid Color=128 128 128\r
+CommandSize=3 299 423 470\r
+CommandState=0\r
+WatchSize=0 0 420 112\r
+WatchState=0\r
+Abs Sort Mode=H'00000001\r
+Register Select0=H'00000000\r
+Register Select1=H'00000001\r
+Register Select2=H'00000002\r
+Register Select3=H'00000003\r
+Register Select4=H'00000004\r
+Register Select5=H'00000005\r
+Register Select6=H'00000006\r
+Register Select7=H'00000007\r
+Register Select8=H'00000008\r
+Register Select9=H'00000009\r
+Register Select10=H'0000000A\r
+Register Select11=H'0000000B\r
+Register Select12=H'0000000C\r
+Register Select13=H'0000000D\r
+Register Select14=H'0000000E\r
+Register Select15=H'0000000F\r
+Register Select16=H'00000010\r
+Register Select17=H'00000011\r
+Register Select18=H'00000012\r
+Register Select19=H'00000013\r
+Register Select20=H'00000014\r
+Register Select21=H'00000015\r
+Register Select22=H'00000016\r
+Register Select23=H'00000017\r
+Register Select24=H'00000018\r
+Register Select25=H'00000019\r
+Register Select26=H'0000001A\r
+Register Select27=H'0000001B\r
+Register Select28=H'0000001C\r
+Register Select29=H'0000001D\r
+Register Select30=H'0000001E\r
+Register Select31=H'0000001F\r
+Register Select32=H'00000020\r
+Register Select33=H'00000021\r
+Register Select34=H'00000022\r
+Register Select35=H'00000027\r
+Layer0=2000,SRC\Start91460.asm\r
+Layer1=1002,\r
+Layer2=1007,\r
+Source0Name=SRC\Start91460.asm\r
+Source0Size=0 0 420 240\r
+Source0State=0\r
+Source0Line=698\r
+Source0Mode=2\r
+SymbolSize=0 0 420 128\r
+SymbolState=0\r
+Memory Line Byte=H'00000000\r
+Memory Change Color=255 0 0\r
+Memory Mark Color0=192 192 192\r
+Memory Mark Color1=192 0 0\r
+Memory Mark Color2=255 255 0\r
+Memory Mark Color3=0 255 0\r
+Memory Mark Color4=0 255 255\r
+Memory Mark Color5=0 128 192\r
+Memory Mark Color6=255 128 64\r
+Watch2Size=0 0 420 112\r
+Watch2State=0\r
+Watch3Size=0 0 420 112\r
+Watch3State=0\r
+[Path Environment]\r
+Flag=Enable\r
+Source=\r
+[Map]\r
+Flag=Enable\r
+[Radix Environment]\r
+Flag=Enable\r
+Mode=10\r
+Source=1\r
+[Watch Environment]\r
+Flag=Enable\r
+Size=0\r
+Mode=0\r
+MBuf=0\r
+Check=1\r
+CSiz=100\r
+[Exec Environment]\r
+Flag=Enable\r
+GoIntMask=0\r
+StepUnit=3\r
+StepIntMask=0\r
+StepIntpCtrl=4\r
+GoTrcCtrl=2\r
+OnTheFlyBreakAdmit=1\r
+[Break Environment]\r
+Flag=Enable\r
+EventCodeMode=0\r
+EventDataMode=0\r
+[Emulation Environment]\r
+Flag=Enable\r
+Verify=0\r
+TRIG Input=0\r
+RunMode=3\r
+ICache Auto Control=0\r
+DefaultBreak=1\r
+TraceLostBreak=0\r
+AlignmentErrorBreak=0\r
+RFCR Auto Control=On\r
+RFCR Execute=6810\r
+RFCR Break=F98\r
+Frequency=64\r
+AutoWait=3\r
+Limit Volt=6.6 2.0\r
+WatchDog=1\r
+Resource=1\r
+EventMode=0\r
+[Monitor Environment]\r
+Flag=Enable\r
+MemoryWindow=0\r
+WatchWindow=0\r
+ObjectWindow=0\r
+ElapseTime=3E8\r
+Unit=1\r
+Mode=0\r
+RealtimeMemoryWindow=0\r
+[Error]\r
+Flag=Enable\r
+GuiErrorOutput=2\r
+CommandErrorOutput=1\r
+BatchErrorOutput=1\r
+ErrorOutputLevel=0\r
+[Color]\r
+Flag=Enable\r
+[Tab Environment]\r
+TabSize=8\r
+[Communication]\r
+Send=4000\r
+Receive=4000\r
+[Trace Environment]\r
+Trace Break=0\r
+Trace Status=0\r
+[CS Memory]\r
+Flag=Disable\r
+Area=0\r
+Write Enable=Disable\r
+[IceMonitor Environment]\r
+[FLASH Environment]\r
+File Specified Area=00000001 00000000 00000000\r
+Environment Area=00000001 00000000 00000000\r
+MCU Number=MB91F464A\r
+EnvSectorInfo1=0 00000000 00000000\r
+EnvSectorInfo2=0 00000000 00000000\r
+EnvSectorInfo3=0 00000000 00000000\r
+EnvSectorInfo4=0 00000000 00000000\r
+EnvSectorInfo5=0 00000000 00000000\r
+EnvSectorInfo6=0 00000000 00000000\r
+EnvSectorInfo7=0 00000000 00000000\r
+EnvSectorInfo8=0 00000000 00000000\r
+EnvSectorSelectMode=0\r
+FileSectorInfo1=0 00000000 00000000\r
+FileSectorInfo2=0 00000000 00000000\r
+FileSectorInfo3=0 00000000 00000000\r
+FileSectorInfo4=0 00000000 00000000\r
+FileSectorInfo5=0 00000000 00000000\r
+FileSectorInfo6=0 00000000 00000000\r
+FileSectorInfo7=0 00000000 00000000\r
+FileSectorInfo8=0 00000000 00000000\r
+FileSectorSelectMode=0\r

diff --git a/Demo/MB91460_Softune/STANDALONE/MB2198-01-LAN.sup b/Demo/MB91460_Softune/STANDALONE/MB2198-01-LAN.sup
new file mode 100644 (file)
index 0000000..ee2b986
--- /dev/null
+++ b/Demo/MB91460_Softune/STANDALONE/MB2198-01-LAN.sup
@@ -0,0 +1,226 @@
+[Information]\r
+DebChangeFlag=0\r
+MCUChangeFlag=0\r
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+[Debug Type]\r
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+Virtual CPU File=wv911e2.dll\r
+Monitor Load=1\r
+Monitor Load Condition=Enable\r
+Mode=FFFF\r
+Monitor Combination Version=10100\r
+Mcu Name=MB91F467D\r
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+Core ID=0\r
+[Device]\r
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+After Batch File=PRC\set_RESET.prc\r
+Non AutoMap=Enable\r
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+Source PC Color=255 255 0\r
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+Abs Sort Mode=H'00000001\r
+Register Select0=H'00000000\r
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+Register Select6=H'00000006\r
+Register Select7=H'00000007\r
+Register Select8=H'00000008\r
+Register Select9=H'00000009\r
+Register Select10=H'0000000A\r
+Register Select11=H'0000000B\r
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+Register Select14=H'0000000E\r
+Register Select15=H'0000000F\r
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+Register Select24=H'00000018\r
+Register Select25=H'00000019\r
+Register Select26=H'0000001A\r
+Register Select27=H'0000001B\r
+Register Select28=H'0000001C\r
+Register Select29=H'0000001D\r
+Register Select30=H'0000001E\r
+Register Select31=H'0000001F\r
+Register Select32=H'00000020\r
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+Register Select34=H'00000022\r
+Register Select35=H'00000027\r
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+Memory Mark Color2=255 255 0\r
+Memory Mark Color3=0 255 0\r
+Memory Mark Color4=0 255 255\r
+Memory Mark Color5=0 128 192\r
+Memory Mark Color6=255 128 64\r
+Watch2Size=0 0 420 112\r
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+Watch3Size=0 0 420 112\r
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+[Path Environment]\r
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+[Radix Environment]\r
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+Mode=10\r
+Source=1\r
+[Watch Environment]\r
+Flag=Enable\r
+Size=0\r
+Mode=0\r
+MBuf=0\r
+Check=1\r
+CSiz=100\r
+[Exec Environment]\r
+Flag=Enable\r
+GoIntMask=0\r
+StepUnit=3\r
+StepIntMask=0\r
+StepIntpCtrl=4\r
+GoTrcCtrl=2\r
+OnTheFlyBreakAdmit=1\r
+[Break Environment]\r
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+[Emulation Environment]\r
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+Verify=0\r
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+RunMode=3\r
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+AlignmentErrorBreak=0\r
+RFCR Auto Control=On\r
+RFCR Execute=6780\r
+RFCR Break=F98\r
+Frequency=64\r
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+Limit Volt=6.6 2.0\r
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+Resource=1\r
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+[Monitor Environment]\r
+Flag=Enable\r
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+ObjectWindow=0\r
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+[Color]\r
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+Receive=32000\r
+[Trace Environment]\r
+Trace Break=0\r
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+[CS Memory]\r
+Flag=Disable\r
+Area=0\r
+Write Enable=Disable\r
+[IceMonitor Environment]\r
+[FLASH Environment]\r
+File Specified Area=00000001 00000000 00000000\r
+Environment Area=00000001 00000000 00000000\r
+MCU Number=MB91F464A\r
+EnvSectorInfo1=0 00000000 00000000\r
+EnvSectorInfo2=0 00000000 00000000\r
+EnvSectorInfo3=0 00000000 00000000\r
+EnvSectorInfo4=0 00000000 00000000\r
+EnvSectorInfo5=0 00000000 00000000\r
+EnvSectorInfo6=0 00000000 00000000\r
+EnvSectorInfo7=0 00000000 00000000\r
+EnvSectorInfo8=0 00000000 00000000\r
+EnvSectorSelectMode=0\r
+FileSectorInfo1=0 00000000 00000000\r
+FileSectorInfo2=0 00000000 00000000\r
+FileSectorInfo3=0 00000000 00000000\r
+FileSectorInfo4=0 00000000 00000000\r
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+FileSectorInfo6=0 00000000 00000000\r
+FileSectorInfo7=0 00000000 00000000\r
+FileSectorInfo8=0 00000000 00000000\r
+FileSectorSelectMode=0\r

diff --git a/Demo/MB91460_Softune/STANDALONE/MB2198-01-USB.sup b/Demo/MB91460_Softune/STANDALONE/MB2198-01-USB.sup
new file mode 100644 (file)
index 0000000..c8b74ad
--- /dev/null
+++ b/Demo/MB91460_Softune/STANDALONE/MB2198-01-USB.sup
@@ -0,0 +1,327 @@
+[Information]\r
+DebChangeFlag=0\r
+MCUChangeFlag=0\r
+[Version]\r
+Version=1\r
+Level=1\r
+Revision=0\r
+[Debug Type]\r
+Type=0\r
+Virtual CPU File=wv911e2.dll\r
+Monitor Load=1\r
+Monitor Load Condition=Enable\r
+Mode=FFFF\r
+Monitor Combination Version=10100\r
+Mcu Name=MB91F467D\r
+Monitor Select Count=1\r
+Monitor Connect Condition0=4\r
+Monitor Combination0=8/1/2:RealTimeMemory:,8/9/10:RAM Checker:C:48&1\r
+Core ID=0\r
+[Device]\r
+Communication=USB              \r
+ProductID=2002\r
+Protocol=3\r
+[Target]\r
+AutoLoad=Enable\r
+Before Batch File=PRC\set_ROMS.prc\r
+After Batch File=PRC\set_RESET.prc\r
+Non AutoMap=Enable\r
+Load DebInfo Only=Disable\r
+Ondemand Load Condition=Disable\r
+[Start]\r
+Batch File=\r
+[Window]\r
+Flag=Enable\r
+AssemblySize=0 435 256 580\r
+AssemblyState=2\r
+AssemblyFGColor=0 0 255\r
+RegisterSize=0 0 512 300\r
+RegisterState=0\r
+MemorySize=0 0 512 300\r
+MemoryState=0\r
+Assembly Address=H'0000BFF8\r
+Memory Address=H'00045858\r
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+Memory Ascii=H'00000000\r
+Memory SplitRow=0\r
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+Trace ViewMode=1\r
+Command Max History=H'00000032\r
+Source Display Mode=Enable\r
+Source Multi Mode=Enable\r
+Source Ask Mode=Enable\r
+Source Active Mode=Enable\r
+Source PC Color=255 255 0\r
+Source Scope Color=255 0 255\r
+Source Back Trace=255 0 255\r
+Register Change Color=255 0 0\r
+Perfomance Mode=H'00000001\r
+Perfomance Scale=1 0 0.000000 0.000000\r
+RMemory Change Color=255 0 0\r
+RMemory Invalid Color=128 128 128\r
+CommandSize=256 0 615 171\r
+CommandState=0\r
+WatchSize=512 0 1024 200\r
+WatchState=0\r
+Abs Sort Mode=H'00000001\r
+Register Select0=H'00000000\r
+Register Select1=H'00000001\r
+Register Select2=H'00000002\r
+Register Select3=H'00000003\r
+Register Select4=H'00000004\r
+Register Select5=H'00000005\r
+Register Select6=H'00000006\r
+Register Select7=H'00000007\r
+Register Select8=H'00000008\r
+Register Select9=H'00000009\r
+Register Select10=H'0000000A\r
+Register Select11=H'0000000B\r
+Register Select12=H'0000000C\r
+Register Select13=H'0000000D\r
+Register Select14=H'0000000E\r
+Register Select15=H'0000000F\r
+Register Select16=H'00000010\r
+Register Select17=H'00000011\r
+Register Select18=H'00000012\r
+Register Select19=H'00000013\r
+Register Select20=H'00000014\r
+Register Select21=H'00000015\r
+Register Select22=H'00000016\r
+Register Select23=H'00000017\r
+Register Select24=H'00000018\r
+Register Select25=H'00000019\r
+Register Select26=H'0000001A\r
+Register Select27=H'0000001B\r
+Register Select28=H'0000001C\r
+Register Select29=H'0000001D\r
+Register Select30=H'0000001E\r
+Register Select31=H'0000001F\r
+Register Select32=H'00000020\r
+Register Select33=H'00000021\r
+Register Select34=H'00000022\r
+Register Select35=H'00000027\r
+SymbolSize=0 0 450 475\r
+SymbolState=0\r
+Memory Line Byte=H'00000000\r
+Memory Change Color=255 0 0\r
+Memory Mark Color0=192 192 192\r
+Memory Mark Color1=192 0 0\r
+Memory Mark Color2=255 255 0\r
+Memory Mark Color3=0 255 0\r
+Memory Mark Color4=0 255 255\r
+Memory Mark Color5=0 128 192\r
+Memory Mark Color6=255 128 64\r
+Watch2Size=0 0 420 112\r
+Watch2State=0\r
+Watch3Size=0 0 420 112\r
+Watch3State=0\r
+TraceSize=492 0 738 145\r
+TraceState=0\r
+Layer0=1004,\r
+Layer1=1005,\r
+Layer2=1006,\r
+Source0Name=SRC\Minimal\blocktim.c\r
+Source0Size=512 400 1024 600\r
+Source0State=0\r
+Source0Line=195\r
+Source0Mode=2\r
+LocalSize=0 300 512 600\r
+LocalState=0\r
+Watch Variable0=[xTickCount],82030000,1,-1 -1\r
+Watch Variable1=[uxTopReadyPriority],80030000,1,-1 -1\r
+Watch Variable2=[tasks\uxCurrentNumberOfTasks],80030000,1,-1 -1\r
+Watch Variable3=[tasks\pxCurrentTCB],82040000,1,-1 -1\r
+Watch Variable4=[xTaskCheck],10010000,1,-1 -1\r
+Watch Variable5=[sCheckVariables],10010000,1,-1 -1\r
+Watch Variable6=[xSemaphoreParameters],10080000,1,-1 -1\r
+Watch Variable7=[sNextCheckVariable],92030000,1,-1 -1\r
+Command History0=cmd send\r
+Command History1=cmd send=60000\r
+Command History2=cmd send\r
+Command History3=cmd send=50000\r
+Command History4=cmd help\r
+Command History5=cmd send\r
+Command History6=cmd send\r
+Command History7=cmd send\r
+Command History8=cmd send\r
+Command History9=cmd help\r
+Command History10=cmd\r
+Command History11=cmd send\r
+Command History12=cmd send\r
+Command History13=cmd send=60000\r
+Command History14=cmd send\r
+Command History15=cmd send = 60000\r
+Command History16=cmd send\r
+Command History17=send\r
+Command History18=cmd send=50000\r
+Command History19=cmd send\r
+Command History20=cmd send\r
+Command History21=cmd send=60000\r
+Command History22=cmd send\r
+Command History23=cmd send=500\r
+Command History24=cmd send\r
+Command History25=load c:\CYGWIN\usr\cross\bin\test.mhx\r
+Command History26=load c:\CYGWIN\usr\cross\bin\test.mhx\r
+Command History27=load c:\CYGWIN\usr\cross\bin\test.mhx\r
+Layer3=2000,SRC\Minimal\blocktim.c\r
+Layer4=2000,SRC\Minimal\comtest.c\r
+Layer5=2000,SRC\taskutility.c\r
+Source1Name=SRC\MAIN.c\r
+Source1Size=512 200 1024 400\r
+Source1State=0\r
+Source1Line=9F\r
+Source1Mode=2\r
+Layer6=2000,SRC\FreeRTOSConfig.h\r
+Layer7=2000,SRC\os\queue.c\r
+Source2Name=SRC\FreeRTOSConfig.h\r
+Source2Size=110 110 936 513\r
+Source2State=0\r
+Source2Line=22\r
+Source2Mode=2\r
+Source3Name=SRC\Minimal\comtest.c\r
+Source3Size=154 154 984 561\r
+Source3State=0\r
+Source3Line=100\r
+Source3Mode=2\r
+Source4Name=SRC\Start91460.asm\r
+Source4Size=198 198 1028 605\r
+Source4State=0\r
+Source4Line=627\r
+Source4Mode=2\r
+Source5Name=SRC\taskutility.c\r
+Source5Size=0 0 830 407\r
+Source5State=0\r
+Source5Line=76\r
+Source5Mode=2\r
+Layer8=2000,SRC\Start91460.asm\r
+Layer9=1007,\r
+Layer10=2000,SRC\MAIN.c\r
+Layer11=1002,\r
+Watch Variable8=[xStart],10080000,1,-1 -1\r
+Watch Variable9=[xEnd],10080000,1,-1 -1\r
+Source6Name=SRC\os\queue.c\r
+Source6Size=154 154 1006 564\r
+Source6State=0\r
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+Source6Mode=2\r
+Watch Variable10=[xPrimaryCycles],90030000,1,-1 -1\r
+Watch Variable11=[xSecondaryCycles],80030000,1,-1 -1\r
+Command History28=load c:\CYGWIN\usr\cross\bin\test.mhx\r
+Command History29=load c:\CYGWIN\usr\cross\bin\test.mhx\r
+Command History30=load c:\CYGWIN\usr\cross\bin\test.mhx\r
+Command History31=load c:\CYGWIN\usr\cross\bin\test.mhx\r
+Command History32=load c:\CYGWIN\usr\cross\bin\test.mhx\r
+Command History33=load c:\CYGWIN\usr\cross\bin\test.mhx\r
+[Path Environment]\r
+Flag=Enable\r
+Source=\r
+[Map]\r
+Flag=Enable\r
+[Radix Environment]\r
+Flag=Enable\r
+Mode=10\r
+Source=1\r
+[Watch Environment]\r
+Flag=Enable\r
+Size=0\r
+Mode=0\r
+MBuf=0\r
+Check=1\r
+CSiz=100\r
+[Exec Environment]\r
+Flag=Enable\r
+GoIntMask=0\r
+StepUnit=3\r
+StepIntMask=0\r
+StepIntpCtrl=4\r
+GoTrcCtrl=2\r
+OnTheFlyBreakAdmit=1\r
+[Break Environment]\r
+Flag=Enable\r
+EventCodeMode=0\r
+EventDataMode=0\r
+Code0=00040302 1 1 1 0 0 MAIN.c$162  \r
+Debug File=C:\Fujitsu\FreeRTOS\FreeRTOS_Port_FR\91467d_FreeRTOS\STANDALONE\ABS\91467d_FreeRTOS.abs\r
+[Emulation Environment]\r
+Flag=Enable\r
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+RFCR Execute=5B50\r
+RFCR Break=F98\r
+Frequency=50\r
+AutoWait=3\r
+Limit Volt=6.6 2.0\r
+WatchDog=0\r
+Resource=1\r
+EventMode=0\r
+[Monitor Environment]\r
+Flag=Enable\r
+MemoryWindow=1\r
+WatchWindow=1\r
+ObjectWindow=0\r
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+[Error]\r
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+[Color]\r
+Flag=Enable\r
+[Tab Environment]\r
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+Receive=32000\r
+[Trace Environment]\r
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+[CS Memory]\r
+Flag=Disable\r
+Area=0\r
+Write Enable=Disable\r
+[IceMonitor Environment]\r
+Mode=FFFFFFFF\r
+[FLASH Environment]\r
+File Specified Area=00000001 00000000 00000000\r
+Environment Area=00000001 00000000 00000000\r
+MCU Number=MB91F467D\r
+EnvSectorInfo1=0 00000000 00000000\r
+EnvSectorInfo2=0 00000000 00000000\r
+EnvSectorInfo3=0 00000000 00000000\r
+EnvSectorInfo4=0 00000000 00000000\r
+EnvSectorInfo5=0 00000000 00000000\r
+EnvSectorInfo6=0 00000000 00000000\r
+EnvSectorInfo7=0 00000000 00000000\r
+EnvSectorInfo8=0 00000000 00000000\r
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+FileSectorInfo3=0 00000000 00000000\r
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+FileSectorInfo5=0 00000000 00000000\r
+FileSectorInfo6=0 00000000 00000000\r
+FileSectorInfo7=0 00000000 00000000\r
+FileSectorInfo8=0 00000000 00000000\r
+FileSectorSelectMode=0\r
+[Book Mark]\r
+BookMarkMem0=SystemStack,,6,H'00028000,H'000280FB\r
+BookMarkMem1=H'00028228,,1,H'00028228,H'0002837B\r
+BookMarkMem2=H'0002837C,,3,H'0002837C,H'000284CF\r
+BookMarkMem3=H'000284D0,,1,H'000284D0,H'00028623\r
+BookMarkMem4=(tasks\pxCurrentTCB)->pxTopOfStack,,6,H'00028624,H'00028627\r
+BookMarkMem5=*((tasks\pxCurrentTCB)->pxTopOfStack),,2,H'00028838,H'0002883B\r
+BookMarkMem6=\pxCurrentTCB,,7,H'0002892C,H'0002892F\r
+BookMarkMem7=UserStack,,4,H'0002894C,H'00028D47\r

diff --git a/Demo/MB91460_Softune/STANDALONE/Mondeb_57K6_com1.sup b/Demo/MB91460_Softune/STANDALONE/Mondeb_57K6_com1.sup
new file mode 100644 (file)
index 0000000..36de155
--- /dev/null
+++ b/Demo/MB91460_Softune/STANDALONE/Mondeb_57K6_com1.sup
@@ -0,0 +1,195 @@
+[Information]\r
+DebChangeFlag=0\r
+MCUChangeFlag=0\r
+[Version]\r
+Version=1\r
+Level=1\r
+Revision=0\r
+[Debug Type]\r
+Type=2\r
+Virtual CPU File=wv911r1.dll\r
+Monitor Load=0\r
+Monitor Load Condition=Disable\r
+[Device]\r
+Communication=RS COM1 57600\r
+ProductID=0\r
+Protocol=0\r
+[Target]\r
+AutoLoad=Enable\r
+Before Batch File=\r
+After Batch File=PRC\set_MONITOR.prc\r
+Non AutoMap=Enable\r
+Load DebInfo Only=Disable\r
+Ondemand Load Condition=Disable\r
+[Start]\r
+Batch File=\r
+[Window]\r
+Flag=Enable\r
+AssemblySize=189 109 609 349\r
+AssemblyState=0\r
+AssemblyFGColor=0 0 255\r
+CommandSize=337 424 757 744\r
+CommandState=0\r
+Assembly Address=H'00042B4A\r
+Memory Address=H'0002F038\r
+Memory Mode=H'00000003\r
+Memory Ascii=H'00000001\r
+Memory SplitRow=0\r
+RMemory Address=H'00000000\r
+RMemory Mode=H'FFFFFFFF\r
+RMemory Ascii=H'00000001\r
+RMemory SplitRow=0\r
+Trace ViewMode=FFFFFFFF\r
+Command Max History=H'00000032\r
+Source Display Mode=Enable\r
+Source Multi Mode=Enable\r
+Source Ask Mode=Enable\r
+Source Active Mode=Enable\r
+Source PC Color=255 255 0\r
+Source Scope Color=255 0 255\r
+Source Back Trace=255 0 255\r
+Register Change Color=255 0 0\r
+Abs Sort Mode=H'00000001\r
+Perfomance Mode=H'00000001\r
+Perfomance Scale=1 0 0.000000 0.000000\r
+RMemory Change Color=255 0 0\r
+RMemory Invalid Color=128 128 128\r
+Command History0=step\r
+Command History1=go ,main\r
+RegisterSize=0 300 512 600\r
+RegisterState=0\r
+Register Select0=H'00000000\r
+Register Select1=H'00000001\r
+Register Select2=H'00000002\r
+Register Select3=H'00000003\r
+Register Select4=H'00000004\r
+Register Select5=H'00000005\r
+Register Select6=H'00000006\r
+Register Select7=H'00000007\r
+Register Select8=H'00000008\r
+Register Select9=H'00000009\r
+Register Select10=H'0000000A\r
+Register Select11=H'0000000B\r
+Register Select12=H'0000000C\r
+Register Select13=H'0000000D\r
+Register Select14=H'0000000E\r
+Register Select15=H'0000000F\r
+Register Select16=H'00000010\r
+Register Select17=H'00000011\r
+Register Select18=H'00000012\r
+Register Select19=H'00000013\r
+Register Select20=H'00000014\r
+Register Select21=H'00000015\r
+Register Select22=H'00000016\r
+Register Select23=H'00000017\r
+Register Select24=H'00000018\r
+Register Select25=H'00000019\r
+Register Select26=H'0000001A\r
+Register Select27=H'0000001B\r
+Register Select28=H'0000001C\r
+Register Select29=H'0000001D\r
+Register Select30=H'0000001E\r
+Register Select31=H'0000001F\r
+Register Select32=H'00000020\r
+Register Select33=H'00000021\r
+Register Select34=H'00000022\r
+Register Select35=H'00000027\r
+MemorySize=512 0 1024 200\r
+MemoryState=0\r
+Layer0=1006,\r
+Layer1=1003,\r
+Layer2=1005,\r
+Source0Name=SRC\Start91460.asm\r
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+File Specified Area=00000001 00000000 00000000\r
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diff --git a/Demo/MB91460_Softune/STANDALONE/Mondeb_57K6_com2.sup b/Demo/MB91460_Softune/STANDALONE/Mondeb_57K6_com2.sup
new file mode 100644 (file)
index 0000000..c989e99
--- /dev/null
+++ b/Demo/MB91460_Softune/STANDALONE/Mondeb_57K6_com2.sup
@@ -0,0 +1,197 @@
+[Information]\r
+DebChangeFlag=0\r
+MCUChangeFlag=0\r
+[Version]\r
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+[Device]\r
+Communication=RS COM2 57600\r
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+[Target]\r
+AutoLoad=Enable\r
+Before Batch File=\r
+After Batch File=PRC\set_MONITOR.prc\r
+Non AutoMap=Enable\r
+Load DebInfo Only=Disable\r
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+[Start]\r
+Batch File=\r
+[Window]\r
+Flag=Enable\r
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+Assembly Address=H'00040DFC\r
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diff --git a/Demo/MB91460_Softune/STANDALONE/Simulator.sup b/Demo/MB91460_Softune/STANDALONE/Simulator.sup
new file mode 100644 (file)
index 0000000..f4196e5
--- /dev/null
+++ b/Demo/MB91460_Softune/STANDALONE/Simulator.sup
@@ -0,0 +1,291 @@
+[Information]\r
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+Command History8=load c:\CYGWIN\usr\cross\bin\test.mhx\r
+Command History9=load c:\CYGWIN\usr\cross\bin\test.mhx\r
+Command History10=load c:\CYGWIN\usr\cross\bin\test.mhx\r
+Command History11=load c:\CYGWIN\usr\cross\bin\test.mhx\r
+Command History12=load c:\CYGWIN\usr\cross\bin\test.mhx\r
+Command History13=load c:\CYGWIN\usr\cross\bin\test.mhx\r
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+Command History18=load c:\CYGWIN\usr\cross\bin\test.mhx\r
+Command History19=load c:\CYGWIN\usr\cross\bin\test.out\r
+Command History20=load c:\CYGWIN\usr\cross\bin\test.out\r
+Command History21=load c:\CYGWIN\usr\cross\bin\test.out\r
+Command History22=load c:\c:\CYGWIN\usr\cross\bin\test.out\r
+Command History23=load\r
+Command History24=open\r
+Command History25=go ,main\r
+Command History26=go noClockStartup,Start91460\smd_cs\r
+Command History27=go ,noClockStartup\r
+Command History28=go ,noClockStartup\r
+Command History29=go noClockStartup,Start91460\smd_cs\r
+Command History30=go ,noClockStartup\r
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+Command History36=SET MEMORY/WORD 0xFFFFC=__start\r
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diff --git a/Demo/MB91460_Softune/readme.txt b/Demo/MB91460_Softune/readme.txt
new file mode 100644 (file)
index 0000000..d74bd01
--- /dev/null
+++ b/Demo/MB91460_Softune/readme.txt
@@ -0,0 +1,114 @@
+\r
+==========================================================================\r
+                   Template Project for MB91F467D \r
+==========================================================================\r
+                   Fujitsu Microelectronics Europe GmbH                       \r
+                 http://emea.fujitsu.com/microelectronics \r
+                                                            \r
+The  following  software  is for  demonstration  purposes only.  It is not\r
+fully  tested, nor validated  in  order  to fullfill  its task  under  all\r
+circumstances.  Therefore,  this software  or  any part of it must only be\r
+used in an evaluation laboratory environment.                        \r
+This software is subject to  the rules of our standard DISCLAIMER, that is\r
+delivered  with  our  SW-tools  on  the  Fujitsu  Microcontrollers CD /DVD\r
+(V3.4 or higher "\START.HTM").\r
+==========================================================================\r
+               \r
+History\r
+Date        Ver     Author  Softune     Description\r
+2007-11-12  1.0     MPi     V60L06             original version\r
+2007-11-12  1.1     MPi     V60L06             Changed the version for consistency\r
+                                                                               with SVN\r
+2007-11-23  1.2     MPi     V60L06             Seperated Watchdog functionality\r
+                                                                               added watchdog.c and watchdog.h\r
+2007-12-13  1.3     MPi     V60L06             Tested with the FreeRTOS version 4.6.1.\r
+2007-12-13  1.4     MPi     V60L06             Tested with the FreeRTOS version 4.7.0.\r
+2007-01-07  1.5     MPi     V60L06             Removed watchdog.c, watchdog.h, port.c \r
+                                                                               and portmacro.h from directory\r
+                                                                               \FreeRTOS_Port_FR\91467d_FreeRTOS\SRC\r
+2007-01-18  1.6     MPi     V60L06             Tested with monitor debugger\r
+==========================================================================\r
+1.0.\r
+This is a project is to test the FreeRTOS port for FR (91467D) and the demo \r
+application which runs on SK-91F467-Felxray V1.1.\r
+\r
+1.1.\r
+This FreeRTOS port uses the Task Stack pointed by User Stack pointer (USP) for\r
+tasks and the system stack pointed by System Stack pointer (SSP) for everything\r
+else. \r
+\r
+1.2.\r
+In this port, the functionality is added to initialize and clear the watchdog in \r
+the dedicated task, Tick Hook or the Idle Hook. The place exactly where the \r
+watchdog can be cleared can be configured. Though Idle Hook is not an approproiate\r
+place to clear the watchdog, its done here for demonstration purpose only.\r
+\r
+Also from Main function vTaskStartScheduler() function is called instead of \r
+xPortStartScheduler(). After doing this change now no more IDLE task is required\r
+to be added seperately as vTaskStartScheduler() adds prvIdleTask() on its own.\r
+\r
+The System Stack required by each of the RLT0 and Delayed Interrupt ISR is around 100 \r
+bytes. This is considering no interrupts has higher priority than the RLT0 and Delayed \r
+interrupt (23). If an application has interrupt whose priority is higher than these \r
+interrupts, which is very likely, then for each such interrupt the user has to increase \r
+the stack size at least by 50 bytes, though this is not an optimum figure and very well \r
+depends upon the application.\r
+Hence though the STACK_SYS_SIZE is defined as 2000, its optimum value would be very well\r
+dependent on the application where the port would be used.\r
+\r
+1.3.\r
+Tested with the FreeRTOS version 4.6.1.\r
+\r
+Changed portBYTE_ALIGNMENT to 4 from 1.\r
+\r
+Added portYIELDFromISR() which uses delayed interrupt. This macro needs to be used from the\r
+application ISRs in order to force a context switch from them if required. It should be noted\r
+that the interrupt priority of such application ISRs MUST be always higher than the dealyed \r
+interrupt (currently 23) in order to perform the context switch correctly.\r
+\r
+It should be also noted that the RLT0 and Delayed Interrupt priority MUST be always same in order \r
+to assure correct working of this port.\r
+\r
+Now portYIELD() used software interrupt INT #40H instead of delayed interrupt.\r
+\r
+Now all the queue functions works ok.\r
+\r
+Tested with the heap_1.c, heap_2.c and heap_3.c.\r
+\r
+Added the __STD_LIB_sbrk.c file in order to define the *sbrk() function. This is required while using\r
+heap_3.c file which uses the dynamic memory allocation.\r
+\r
+Made changes to the demo application files crflash.c and crhook.c. Please refer those file\r
+and grep for "Added by MPi" to find the changes.\r
+\r
+Added taskutility.c file. This file contains vUART4Task() which calls vTaskList() and vTaskStartTrace()\r
+functions.\r
+\r
+If vCreateBlockTimeTasks() is not called then the LED at PDR25_D7 blinks at normal rate (3s).\r
+\r
+1.4.\r
+Tested with the FreeRTOS version 4.6.1.\r
+\r
+At one time, either of heap_1.c or heap_2.c or heap_3.c needs to be used. Hence the files those are not \r
+required to be used should be removed from the target of the build.\r
+\r
+1.5.\r
+Removed watchdog.c, watchdog.h, port.c and portmacro.h from directory \FreeRTOS_Port_FR\91467d_FreeRTOS\SRC, \r
+since they are moved to folders watchdog and port respectively.\r
+\r
+1.6.\r
+It should be noted that the readme, appnote and SVN tag version numbers may be different for the same release.\r
+\r
+Used relative path to include files instead of absolute.\r
+\r
+Created config, MemMang, serial and utility subdirectories and moved corresponding functionlaity there.\r
+\r
+Updated taskuitlity.c, vectors.c in oredr to use UART 5 instead of UART 4\r
+\r
+Updated flash.c to increase LEDs to 4 from 3.\r
+\r
+Clock settings:\r
+---------------\r
+Crystal:  4 MHz\r
+CPU:     64 MHz\r
+CLKP:    16 MHz\r

diff --git a/Source/include/portable.h b/Source/include/portable.h
index bcdd57ee3cd38e8f17770ce725a210e884e5e958..27cade3079c97e9b971df7a7293f883ced63e2a2 100644 (file)
--- a/Source/include/portable.h
+++ b/Source/include/portable.h
@@ -221,6 +221,12 @@
    #endif\r
 #endif\r
 \r
+#ifdef __91467D\r
+       #include "portmacro.h"\r
+       #include "mb91467d.h"\r
+       #include <stddef.h>\r
+#endif\r
+\r
 #ifdef __cplusplus\r
 extern "C" {\r
 #endif\r

diff --git a/Source/portable/Softune/MB91460/__STD_LIB_sbrk.c b/Source/portable/Softune/MB91460/__STD_LIB_sbrk.c
new file mode 100644 (file)
index 0000000..fe70d48
--- /dev/null
+++ b/Source/portable/Softune/MB91460/__STD_LIB_sbrk.c
@@ -0,0 +1,23 @@
+#include "FreeRTOSConfig.h"\r
+#include <stdlib.h>\r
+\r
+       static  long         brk_siz  =  0;\r
+//     #if  configTOTAL_HEAP_SIZE != 0\r
+       typedef int          _heep_t;\r
+       #define ROUNDUP(s)   (((s)+sizeof(_heep_t)-1)&~(sizeof(_heep_t)-1))\r
+       static  _heep_t      _heep[ROUNDUP(configTOTAL_HEAP_SIZE)/sizeof(_heep_t)];\r
+       #define              _heep_size      ROUNDUP(configTOTAL_HEAP_SIZE)\r
+/*     #else\r
+       extern  char        *_heep;\r
+       extern  long        _heep_size;\r
+       #endif\r
+*/     \r
+       extern  char  *sbrk(int  size)\r
+       {\r
+          if  (brk_siz  +  size  >  _heep_size  ||  brk_siz  +  size  <  0)\r
+\r
+          return((char*)-1);\r
+          brk_siz  +=  size;\r
+          return(  (char*)_heep  +  brk_siz  -  size);\r
+       }\r
+\r

diff --git a/Source/portable/Softune/MB91460/port.c b/Source/portable/Softune/MB91460/port.c
new file mode 100644 (file)
index 0000000..54c8398
--- /dev/null
+++ b/Source/portable/Softune/MB91460/port.c
@@ -0,0 +1,352 @@
+/*\r
+       FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry.\r
+\r
+       This file is part of the FreeRTOS.org distribution.\r
+\r
+       FreeRTOS.org is free software; you can redistribute it and/or modify\r
+       it under the terms of the GNU General Public License as published by\r
+       the Free Software Foundation; either version 2 of the License, or\r
+       (at your option) any later version.\r
+\r
+       FreeRTOS.org is distributed in the hope that it will be useful,\r
+       but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+       MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\r
+       GNU General Public License for more details.\r
+\r
+       You should have received a copy of the GNU General Public License\r
+       along with FreeRTOS.org; if not, write to the Free Software\r
+       Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA\r
+\r
+       A special exception to the GPL can be applied should you wish to distribute\r
+       a combined work that includes FreeRTOS.org, without being obliged to provide\r
+       the source code for any proprietary components.  See the licensing section\r
+       of http://www.FreeRTOS.org for full details of how and when the exception\r
+       can be applied.\r
+\r
+       ***************************************************************************\r
+\r
+       Please ensure to read the configuration and relevant port sections of the \r
+       online documentation.\r
+\r
+       +++ http://www.FreeRTOS.org +++\r
+       Documentation, latest information, license and contact details.  \r
+\r
+       +++ http://www.SafeRTOS.com +++\r
+       A version that is certified for use in safety critical systems.\r
+\r
+       +++ http://www.OpenRTOS.com +++\r
+       Commercial support, development, porting, licensing and training services.\r
+\r
+       ***************************************************************************\r
+*/\r
+\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "mb91467d.h"\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* We require the address of the pxCurrentTCB variable, but don't want to know\r
+any details of its type. */\r
+typedef void tskTCB;\r
+extern volatile tskTCB * volatile pxCurrentTCB;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+\r
+ \r
+#pragma asm\r
+#macro  SaveContext\r
+        ORCCR #0x20                                                            ;Switch to user stack\r
+        ST RP,@-R15                                                            ;Store RP\r
+        STM0 (R7,R6,R5,R4,R3,R2,R1,R0)                         ;Store R7-R0\r
+        STM1 (R14,R13,R12,R11,R10,R9,R8)                       ;Store R14-R8\r
+        ST MDH, @-R15                                                          ;Store MDH\r
+        ST MDL, @-R15                                                          ;Store MDL\r
+        \r
+        ANDCCR #0xDF                                                           ;Switch back to system stack\r
+        LD @R15+,R0                                                            ;Store PC to R0 \r
+        ORCCR #0x20                                                            ;Switch to user stack\r
+        ST R0,@-R15                                                            ;Store PC to User stack\r
+        \r
+        ANDCCR #0xDF                                                           ;Switch back to system stack\r
+        LD @R15+,R0                                                            ;Store PS to R0\r
+        ORCCR #0x20                                                            ;Switch to user stack\r
+        ST R0,@-R15                                                            ;Store PS to User stack\r
+        \r
+        LDI #_pxCurrentTCB, R0                                         ;Get pxCurrentTCB address\r
+        LD @R0, R0                                                                     ;Get the pxCurrentTCB->pxTopOfStack address\r
+        ST R15,@R0                                                                     ;Store USP to pxCurrentTCB->pxTopOfStack\r
+        \r
+        ANDCCR #0xDF                                                           ;Switch back to system stack for the rest of tick ISR\r
+#endm\r
+\r
+#macro RestoreContext\r
+        LDI #_pxCurrentTCB, R0                                         ;Get pxCurrentTCB address\r
+        LD @R0, R0                                                                     ;Get the pxCurrentTCB->pxTopOfStack address\r
+        ORCCR #0x20                                                            ;Switch to user stack\r
+        LD @R0, R15                                                            ;Restore USP from pxCurrentTCB->pxTopOfStack\r
+\r
+        LD @R15+,R0                                                            ;Store PS to R0\r
+        ANDCCR #0xDF                                                           ;Switch to system stack\r
+        ST R0,@-R15                                                            ;Store PS to system stack\r
+\r
+        ORCCR #0x20                                                            ;Switch to user stack\r
+        LD @R15+,R0                                                            ;Store PC to R0\r
+        ANDCCR #0xDF                                                           ;Switch to system stack\r
+        ST R0,@-R15                                                            ;Store PC to system stack\r
+\r
+        ORCCR #0x20                                                            ;Switch back to retreive the remaining context\r
+\r
+        LD @R15+, MDL                                                          ;Restore MDL\r
+        LD @R15+, MDH                                                          ;Restore MDH\r
+        LDM1 (R14,R13,R12,R11,R10,R9,R8)                       ;Restore R14-R8\r
+        LDM0 (R7,R6,R5,R4,R3,R2,R1,R0)                         ;Restore R7-R0\r
+        LD @R15+, RP                                                           ;Restore RP\r
+        \r
+        ANDCCR #0xDF                                                           ;Switch back to system stack for the rest of tick ISR\r
+#endm\r
+#pragma endasm\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Perform hardware setup to enable ticks from timer 1,\r
+ */\r
+static void prvSetupTimerInterrupt( void );\r
+/*-----------------------------------------------------------*/\r
+\r
+/* \r
+ * Initialise the stack of a task to look exactly as if a call to \r
+ * portSAVE_CONTEXT had been called.\r
+ * \r
+ * See the header file portable.h.\r
+ */\r
+portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )\r
+{\r
+unsigned portSHORT usAddress;\r
+\r
+       /* Place a few bytes of known values on the bottom of the stack. \r
+       This is just useful for debugging. */\r
+\r
+       *pxTopOfStack = 0x11111111;\r
+       pxTopOfStack--;\r
+       *pxTopOfStack = 0x22222222;\r
+       pxTopOfStack--;\r
+       *pxTopOfStack = 0x33333333;\r
+       pxTopOfStack--;\r
+\r
+       /* This is a redundant push to the stack, it may be required if in some implentation of the compiler\r
+       the parameter to the task is passed on to the stack rather than in R4 register*/\r
+       *pxTopOfStack = (portSTACK_TYPE)(pvParameters);\r
+       pxTopOfStack--;                  \r
+    \r
+       *pxTopOfStack = ( portSTACK_TYPE ) 0x00000000;  /* RP */\r
+       pxTopOfStack--;\r
+\r
+       *pxTopOfStack = ( portSTACK_TYPE ) 0x00007777;  /* R7 */\r
+       pxTopOfStack--;\r
+       *pxTopOfStack = ( portSTACK_TYPE ) 0x00006666;  /* R6 */\r
+       pxTopOfStack--;\r
+       *pxTopOfStack = ( portSTACK_TYPE ) 0x00005555;  /* R5 */\r
+       pxTopOfStack--;\r
+       \r
+       /* In the current implemention of the compiler the first parameter to the task(or function) is passed\r
+       via R4 parameter to the task, hennce the pvParameters pointer is copied in R4 regsiter. See compiler \r
+       manual section 4.6.2 for more information.*/\r
+       *pxTopOfStack = ( portSTACK_TYPE ) (pvParameters);      /* R4 */\r
+       pxTopOfStack--;\r
+       *pxTopOfStack = ( portSTACK_TYPE ) 0x00003333;  /* R3 */\r
+       pxTopOfStack--;\r
+       *pxTopOfStack = ( portSTACK_TYPE ) 0x00002222;  /* R2 */\r
+       pxTopOfStack--;\r
+       *pxTopOfStack = ( portSTACK_TYPE ) 0x00001111;  /* R1 */\r
+       pxTopOfStack--;\r
+       *pxTopOfStack = ( portSTACK_TYPE ) 0x00000001;  /* R0 */\r
+       pxTopOfStack--;\r
+       \r
+       *pxTopOfStack = ( portSTACK_TYPE ) 0x0000EEEE;  /* R14 */\r
+       pxTopOfStack--;\r
+       *pxTopOfStack = ( portSTACK_TYPE ) 0x0000DDDD;  /* R13 */\r
+       pxTopOfStack--;\r
+       *pxTopOfStack = ( portSTACK_TYPE ) 0x0000CCCC;  /* R12 */\r
+       pxTopOfStack--;\r
+       *pxTopOfStack = ( portSTACK_TYPE ) 0x0000BBBB;  /* R11 */\r
+       pxTopOfStack--;\r
+       *pxTopOfStack = ( portSTACK_TYPE ) 0x0000AAAA;  /* R10 */\r
+       pxTopOfStack--;\r
+       *pxTopOfStack = ( portSTACK_TYPE ) 0x00009999;  /* R9 */\r
+       pxTopOfStack--;\r
+       *pxTopOfStack = ( portSTACK_TYPE ) 0x00008888;  /* R8 */\r
+       pxTopOfStack--;\r
+       \r
+       *pxTopOfStack = ( portSTACK_TYPE ) 0x11110000;  /* MDH */\r
+       pxTopOfStack--;\r
+       *pxTopOfStack = ( portSTACK_TYPE ) 0x22220000;  /* MDL */\r
+       pxTopOfStack--;\r
+\r
+       usAddress = ( unsigned portSHORT ) pxCode;\r
+       *pxTopOfStack = ( portSTACK_TYPE ) usAddress ;  /* PC */\r
+       pxTopOfStack--;\r
+        \r
+    /* PS - User Mode, USP, ILM=31, Interrupts enabled */\r
+       *pxTopOfStack = ( portSTACK_TYPE ) 0x001F0030;  /* PS */\r
+\r
+       return pxTopOfStack;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+portBASE_TYPE xPortStartScheduler( void )\r
+{\r
+       /* Setup the hardware to generate the tick. */\r
+       prvSetupTimerInterrupt();\r
+\r
+       /* Restore the context of the first task that is going to run. */\r
+#pragma asm\r
+       RestoreContext\r
+#pragma endasm\r
+\r
+       /* Simulate a function call end as generated by the compiler.  We will now\r
+       jump to the start of the task the context of which we have just restored. */\r
+       \r
+       __asm(" reti ");\r
+\r
+\r
+       /* Should not get here. */\r
+       return pdTRUE;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortEndScheduler( void )\r
+{\r
+       /* It is unlikely that the AVR port will get stopped.  If required simply\r
+       disable the tick interrupt here. */\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Setup RLT0 to generate a tick interrupt.\r
+ */\r
+static void prvSetupTimerInterrupt( void )\r
+{\r
+\r
+       TMCSR0_CNTE=0;          /* Count Disable */\r
+    TMCSR0_CSL=0x2;            /* CLKP/32 */\r
+    TMCSR0_MOD=0;              /* Software trigger */\r
+    TMCSR0_RELD=1;             /* Reload */\r
+    \r
+    TMCSR0_UF=0;               /* Clear underflow flag */\r
+       //TMRLR0=0x1F3;         /* Tick = 1 ms*/ \r
+       TMRLR0=0x1387;          /* Tick = 10 ms*/ \r
+       TMCSR0_INTE=1;          /* Interrupt Enable */\r
+       TMCSR0_CNTE=1;          /* Count Enable */\r
+       TMCSR0_TRG=1;           /* Trigger */\r
+       \r
+    PORTEN = 0x3;              /* Port Enable */\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#if configUSE_PREEMPTION == 1\r
+\r
+       /* \r
+        * Tick ISR for preemptive scheduler. The tick count is incremented \r
+        * after the context is saved. Then the context is switched if required,\r
+        * at last the context of the task which is to be resume is restored.\r
+        */\r
+\r
+       #pragma asm\r
+\r
+       .global _ReloadTimer0_IRQHandler\r
+       _ReloadTimer0_IRQHandler:\r
+\r
+       ANDCCR #0xEF                                                    ;Disable Interrupts\r
+\r
+       SaveContext                                                             ;Save context\r
+\r
+       ORCCR #0x10                                                             ;Re-enable Interrupts\r
+\r
+       LDI #0xFFFB,R1\r
+       LDI #_tmcsr0, R0\r
+       AND R1,@R0                                                              ;Clear RLT0 interrupt flag\r
+\r
+       CALL32   _vTaskIncrementTick,R12                ;Increment Tick\r
+\r
+       CALL32   _vTaskSwitchContext,R12                ;Switch context if required\r
+\r
+       ANDCCR #0xEF                                                    ;Disable Interrupts\r
+\r
+       RestoreContext                                                  ;Restore context\r
+\r
+       ORCCR #0x10                                                             ;Re-enable Interrupts\r
+\r
+       RETI\r
+\r
+       #pragma endasm\r
+       \r
+#else\r
+       \r
+       /* \r
+        * Tick ISR for the cooperative scheduler.  All this does is increment the\r
+        * tick count.  We don't need to switch context, this can only be done by\r
+        * manual calls to taskYIELD();\r
+        */\r
+       __interrupt void ReloadTimer0_IRQHandler( void )\r
+       {\r
+               /* Clear RLT0 interrupt flag */\r
+               TMCSR0_UF = 0; \r
+               vTaskIncrementTick();\r
+       }\r
+\r
+#endif\r
+\r
+       /*\r
+        * Manual context switch. We can use a __nosavereg attribute  as the context \r
+        * would be saved by PortSAVE_CONTEXT().  The context is switched and then \r
+        * the context of the new task is restored saved. \r
+        */\r
+#pragma asm\r
+\r
+       .global _vPortYieldDelayed\r
+       _vPortYieldDelayed:\r
+\r
+       ANDCCR #0xEF                                                    ;Disable Interrupts\r
+\r
+       SaveContext                                                             ;Save context\r
+\r
+       ORCCR #0x10                                                             ;Re-enable Interrupts\r
+\r
+       LDI #_dicr, R0\r
+       BANDL #0x0E, @R0                                                ;Clear Delayed interrupt flag\r
+\r
+       CALL32   _vTaskSwitchContext,R12                ;Switch context if required\r
+\r
+       ANDCCR #0xEF                                                    ;Disable Interrupts\r
+\r
+       RestoreContext                                                  ;Restore context\r
+\r
+       ORCCR #0x10                                                             ;Re-enable Interrupts\r
+\r
+       RETI\r
+\r
+#pragma endasm\r
+\r
+       /*\r
+        * Manual context switch. We can use a __nosavereg attribute  as the context \r
+        * would be saved by PortSAVE_CONTEXT().  The context is switched and then \r
+        * the context of the new task is restored saved. \r
+        */\r
+        \r
+#pragma asm\r
+\r
+       .global _vPortYield\r
+       _vPortYield:\r
+\r
+       SaveContext                                                             ;Save context\r
+\r
+       CALL32   _vTaskSwitchContext,R12                ;Switch context if required\r
+\r
+       RestoreContext                                                  ;Restore context\r
+       \r
+       RETI\r
+\r
+#pragma endasm\r

diff --git a/Source/portable/Softune/MB91460/portmacro.h b/Source/portable/Softune/MB91460/portmacro.h
new file mode 100644 (file)
index 0000000..210f26d
--- /dev/null
+++ b/Source/portable/Softune/MB91460/portmacro.h
@@ -0,0 +1,116 @@
+/*\r
+       FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry.\r
+\r
+       This file is part of the FreeRTOS.org distribution.\r
+\r
+       FreeRTOS.org is free software; you can redistribute it and/or modify\r
+       it under the terms of the GNU General Public License as published by\r
+       the Free Software Foundation; either version 2 of the License, or\r
+       (at your option) any later version.\r
+\r
+       FreeRTOS.org is distributed in the hope that it will be useful,\r
+       but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+       MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\r
+       GNU General Public License for more details.\r
+\r
+       You should have received a copy of the GNU General Public License\r
+       along with FreeRTOS.org; if not, write to the Free Software\r
+       Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA\r
+\r
+       A special exception to the GPL can be applied should you wish to distribute\r
+       a combined work that includes FreeRTOS.org, without being obliged to provide\r
+       the source code for any proprietary components.  See the licensing section\r
+       of http://www.FreeRTOS.org for full details of how and when the exception\r
+       can be applied.\r
+\r
+       ***************************************************************************\r
+\r
+       Please ensure to read the configuration and relevant port sections of the \r
+       online documentation.\r
+\r
+       +++ http://www.FreeRTOS.org +++\r
+       Documentation, latest information, license and contact details.  \r
+\r
+       +++ http://www.SafeRTOS.com +++\r
+       A version that is certified for use in safety critical systems.\r
+\r
+       +++ http://www.OpenRTOS.com +++\r
+       Commercial support, development, porting, licensing and training services.\r
+\r
+       ***************************************************************************\r
+*/\r
+\r
+#ifndef PORTMACRO_H\r
+#define PORTMACRO_H\r
+\r
+/*-----------------------------------------------------------\r
+ * Port specific definitions.  \r
+ *\r
+ * The settings in this file configure FreeRTOS correctly for the\r
+ * given hardware and compiler.\r
+ *\r
+ * These settings should not be altered.\r
+ *-----------------------------------------------------------\r
+ */\r
+\r
+/* Type definitions. */\r
+#define portCHAR               char\r
+#define portFLOAT              float\r
+#define portDOUBLE             double\r
+#define portLONG               long\r
+#define portSHORT              int\r
+#define portSTACK_TYPE unsigned portSHORT\r
+#define portBASE_TYPE  char\r
+\r
+/* This is required since SOFTUNE doesn't support inline directive as is. */\r
+#define inline\r
+\r
+#if( configUSE_16_BIT_TICKS == 1 )\r
+       typedef unsigned portSHORT portTickType;\r
+       #define portMAX_DELAY ( portTickType ) 0xffff\r
+#else\r
+       typedef unsigned portLONG portTickType;\r
+       #define portMAX_DELAY ( portTickType ) 0xffffffff\r
+#endif\r
+/*-----------------------------------------------------------*/        \r
+\r
+/* Critical section management. */\r
+\r
+\r
+#define portENTER_CRITICAL() \\r
+       __asm(" ST PS,@-R15 "); \\r
+       __asm(" ANDCCR #0xef "); \\r
+\r
+\r
+#define portEXIT_CRITICAL()     \\r
+       __asm(" LD @R15+,PS "); \\r
+\r
+\r
+#define portDISABLE_INTERRUPTS()  __DI();\r
+\r
+#define portENABLE_INTERRUPTS()  __EI();\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Architecture specifics. */\r
+#define portSTACK_GROWTH                       ( -1 )\r
+#define portTICK_RATE_MS                       ( ( portTickType ) 1000 / configTICK_RATE_HZ )          \r
+#define portBYTE_ALIGNMENT                     4\r
+#define portNOP()                                      __asm( " nop " );\r
+/*-----------------------------------------------------------*/\r
+\r
+/* portYIELD() uses SW interrupt */\r
+#define portYIELD()                                    __asm( " INT #40H " );\r
+\r
+/* portYIELDFromISR() uses delayed interrupt */\r
+#define portYIELDFromISR()                     DICR_DLYI = 1;\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Task function macros as described on the FreeRTOS.org WEB site. */\r
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
+\r
+#define portMINIMAL_STACK_SIZE configMINIMAL_STACK_SIZE\r
+\r
+#endif /* PORTMACRO_H */\r
+\r