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--- /dev/null
+/*\r
+ FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd.\r
+ \r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ >>>NOTE<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ http://www.FreeRTOS.org - Documentation, latest information, license and\r
+ contact details.\r
+\r
+ http://www.SafeRTOS.com - A version that is certified for use in safety\r
+ critical systems.\r
+\r
+ http://www.OpenRTOS.com - Commercial support, development, porting,\r
+ licensing and training services.\r
+*/\r
+\r
+#ifndef FREERTOS_CONFIG_H\r
+#define FREERTOS_CONFIG_H\r
+\r
+/* Board specifics. */\r
+#include "rskrx630def.h"\r
+\r
+/*-----------------------------------------------------------\r
+ * Application specific definitions.\r
+ *\r
+ * These definitions should be adjusted for your particular hardware and\r
+ * application requirements.\r
+ *\r
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\r
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.\r
+ *\r
+ * See http://www.freertos.org/a00110.html.\r
+ *----------------------------------------------------------*/\r
+\r
+#define configUSE_PREEMPTION 1\r
+#define configUSE_IDLE_HOOK 0\r
+#define configUSE_TICK_HOOK 0\r
+#define configCPU_CLOCK_HZ ( ICLK_FREQUENCY ) /* Set in rskrx630def.h. */\r
+#define configPERIPHERAL_CLOCK_HZ ( PCLKB_FREQUENCY ) /* Set in rskrx630def.h. */\r
+#define configTICK_RATE_HZ ( ( portTickType ) 1000 )\r
+#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 140 )\r
+#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 45 * 1024 ) )\r
+#define configMAX_TASK_NAME_LEN ( 12 )\r
+#define configUSE_TRACE_FACILITY 1\r
+#define configUSE_16_BIT_TICKS 0\r
+#define configIDLE_SHOULD_YIELD 1\r
+#define configUSE_CO_ROUTINES 0\r
+#define configUSE_MUTEXES 1\r
+#define configGENERATE_RUN_TIME_STATS 1\r
+#define configCHECK_FOR_STACK_OVERFLOW 2\r
+#define configUSE_RECURSIVE_MUTEXES 1\r
+#define configQUEUE_REGISTRY_SIZE 0\r
+#define configUSE_MALLOC_FAILED_HOOK 1\r
+#define configUSE_APPLICATION_TASK_TAG 0\r
+\r
+#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 7 )\r
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )\r
+\r
+/* Software timer definitions. */\r
+#define configUSE_TIMERS 1\r
+#define configTIMER_TASK_PRIORITY ( 3 )\r
+#define configTIMER_QUEUE_LENGTH 5\r
+#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE )\r
+\r
+/* The interrupt priority used by the kernel itself for the tick interrupt and\r
+the pended interrupt. This would normally be the lowest priority. */\r
+#define configKERNEL_INTERRUPT_PRIORITY 1\r
+\r
+/* The maximum interrupt priority from which FreeRTOS API calls can be made.\r
+Interrupts that use a priority above this will not be effected by anything the\r
+kernel is doing. */\r
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY 4\r
+\r
+/* The peripheral used to generate the tick interrupt is configured as part of\r
+the application code. This constant should be set to the vector number of the\r
+peripheral chosen. As supplied this is CMT0. */\r
+#define configTICK_VECTOR _CMT0_CMI0\r
+\r
+/* Set the following definitions to 1 to include the API function, or zero\r
+to exclude the API function. */\r
+\r
+#define INCLUDE_vTaskPrioritySet 1\r
+#define INCLUDE_uxTaskPriorityGet 1\r
+#define INCLUDE_vTaskDelete 1\r
+#define INCLUDE_vTaskCleanUpResources 0\r
+#define INCLUDE_vTaskSuspend 1\r
+#define INCLUDE_vTaskDelayUntil 1\r
+#define INCLUDE_vTaskDelay 1\r
+#define INCLUDE_uxTaskGetStackHighWaterMark 1\r
+#define INCLUDE_xTaskGetSchedulerState 1\r
+\r
+#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); for( ;; ); } \r
+\r
+extern volatile unsigned long ulHighFrequencyTickCount;\r
+#define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() nop() /* Run time stats use the same timer as the high frequency timer test. */\r
+#define portGET_RUN_TIME_COUNTER_VALUE() ulHighFrequencyTickCount\r
+\r
+\r
+/* Override some of the priorities set in the common demo tasks. This is\r
+required to ensure flase positive timing errors are not reported. */\r
+#define bktPRIMARY_PRIORITY ( configMAX_PRIORITIES - 3 )\r
+#define bktSECONDARY_PRIORITY ( configMAX_PRIORITIES - 4 )\r
+#define intqHIGHER_PRIORITY ( configMAX_PRIORITIES - 3 )\r
+\r
+\r
+/*-----------------------------------------------------------\r
+ * Ethernet configuration.\r
+ *-----------------------------------------------------------*/\r
+\r
+/* MAC address configuration. */\r
+#define configMAC_ADDR0 0x00\r
+#define configMAC_ADDR1 0x12\r
+#define configMAC_ADDR2 0x13\r
+#define configMAC_ADDR3 0x10\r
+#define configMAC_ADDR4 0x15\r
+#define configMAC_ADDR5 0x11\r
+\r
+/* IP address configuration. */\r
+#define configIP_ADDR0 192\r
+#define configIP_ADDR1 168\r
+#define configIP_ADDR2 0\r
+#define configIP_ADDR3 200\r
+\r
+/* Netmask configuration. */\r
+#define configNET_MASK0 255\r
+#define configNET_MASK1 255\r
+#define configNET_MASK2 255\r
+#define configNET_MASK3 0\r
+\r
+#endif /* FREERTOS_CONFIG_H */\r
--- /dev/null
+/*\r
+ FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd.\r
+ \r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ >>>NOTE<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ http://www.FreeRTOS.org - Documentation, latest information, license and\r
+ contact details.\r
+\r
+ http://www.SafeRTOS.com - A version that is certified for use in safety\r
+ critical systems.\r
+\r
+ http://www.OpenRTOS.com - Commercial support, development, porting,\r
+ licensing and training services.\r
+*/\r
+\r
+/* \r
+ * High frequency timer test as described in main.c. \r
+ */\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+\r
+/* Hardware specifics. */\r
+#include "iodefine.h"\r
+\r
+/* The set frequency of the interrupt. Deviations from this are measured as\r
+the jitter. */\r
+#define timerINTERRUPT_FREQUENCY ( 20000UL )\r
+\r
+/* The expected time between each of the timer interrupts - if the jitter was\r
+zero. */\r
+#define timerEXPECTED_DIFFERENCE_VALUE ( ( unsigned short ) ( ( configPERIPHERAL_CLOCK_HZ / 8UL ) / timerINTERRUPT_FREQUENCY ) )\r
+\r
+/* The highest available interrupt priority. */\r
+#define timerHIGHEST_PRIORITY ( 15 )\r
+\r
+/* Misc defines. */\r
+#define timerTIMER_3_COUNT_VALUE ( *( ( unsigned short * ) 0x8801a ) ) /*( CMT3.CMCNT )*/\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Interrupt handler in which the jitter is measured. */\r
+static void prvTimer2IntHandler( void );\r
+\r
+/* Stores the value of the maximum recorded jitter between interrupts. This is\r
+displayed on one of the served web pages. */\r
+volatile unsigned short usMaxJitter = 0;\r
+\r
+/* Counts the number of high frequency interrupts - used to generate the run\r
+time stats. */\r
+volatile unsigned long ulHighFrequencyTickCount = 0UL;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void vSetupHighFrequencyTimer( void )\r
+{\r
+ /* Timer CMT2 is used to generate the interrupts, and CMT3 is used\r
+ to measure the jitter. */\r
+\r
+ /* Enable compare match timer 2 and 3. */\r
+ MSTP( CMT2 ) = 0;\r
+ MSTP( CMT3 ) = 0;\r
+ \r
+ /* Interrupt on compare match. */\r
+ CMT2.CMCR.BIT.CMIE = 1;\r
+ \r
+ /* Set the compare match value. */\r
+ CMT2.CMCOR = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / timerINTERRUPT_FREQUENCY ) -1 ) / 8 );\r
+ \r
+ /* Divide the PCLK by 8. */\r
+ CMT2.CMCR.BIT.CKS = 0;\r
+ CMT3.CMCR.BIT.CKS = 0;\r
+ \r
+ /* Enable the interrupt... */\r
+ _IEN( _CMT2_CMI2 ) = 1;\r
+ \r
+ /* ...and set its priority to the maximum possible, this is above the priority\r
+ set by configMAX_SYSCALL_INTERRUPT_PRIORITY so will nest. */\r
+ _IPR( _CMT2_CMI2 ) = timerHIGHEST_PRIORITY;\r
+ \r
+ /* Start the timers. */\r
+ CMT.CMSTR1.BIT.STR2 = 1;\r
+ CMT.CMSTR1.BIT.STR3 = 1;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#pragma interrupt ( prvTimer2IntHandler( vect = _VECT( _CMT2_CMI2 ), enable ) )\r
+static void prvTimer2IntHandler( void )\r
+{\r
+volatile unsigned short usCurrentCount;\r
+static unsigned short usMaxCount = 0;\r
+static unsigned long ulErrorCount = 0UL;\r
+\r
+ /* We use the timer 1 counter value to measure the clock cycles between\r
+ the timer 0 interrupts. First stop the clock. */\r
+ CMT.CMSTR1.BIT.STR3 = 0;\r
+ nop();\r
+ nop();\r
+ usCurrentCount = timerTIMER_3_COUNT_VALUE;\r
+\r
+ /* Is this the largest count we have measured yet? */\r
+ if( usCurrentCount > usMaxCount )\r
+ {\r
+ if( usCurrentCount > timerEXPECTED_DIFFERENCE_VALUE )\r
+ {\r
+ usMaxJitter = usCurrentCount - timerEXPECTED_DIFFERENCE_VALUE;\r
+ }\r
+ else\r
+ {\r
+ /* This should not happen! */\r
+ ulErrorCount++;\r
+ }\r
+ \r
+ usMaxCount = usCurrentCount;\r
+ }\r
+\r
+ /* Used to generate the run time stats. */\r
+ ulHighFrequencyTickCount++;\r
+ \r
+ /* Clear the timer. */\r
+ timerTIMER_3_COUNT_VALUE = 0;\r
+ \r
+ /* Then start the clock again. */\r
+ CMT.CMSTR1.BIT.STR3 = 1;\r
+}\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd.\r
+ \r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ >>>NOTE<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ http://www.FreeRTOS.org - Documentation, latest information, license and\r
+ contact details.\r
+\r
+ http://www.SafeRTOS.com - A version that is certified for use in safety\r
+ critical systems.\r
+\r
+ http://www.OpenRTOS.com - Commercial support, development, porting,\r
+ licensing and training services.\r
+*/\r
+\r
+/*\r
+ * This file contains the non-portable and therefore RX62N specific parts of\r
+ * the IntQueue standard demo task - namely the configuration of the timers\r
+ * that generate the interrupts and the interrupt entry points.\r
+ */\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Demo includes. */\r
+#include "IntQueueTimer.h"\r
+#include "IntQueue.h"\r
+\r
+/* Hardware specifics. */\r
+#include "iodefine.h"\r
+\r
+#define tmrTIMER_0_1_FREQUENCY ( 2000UL )\r
+#define tmrTIMER_2_3_FREQUENCY ( 2001UL )\r
+\r
+void vInitialiseTimerForIntQueueTest( void )\r
+{\r
+ /* Ensure interrupts do not start until full configuration is complete. */\r
+ portENTER_CRITICAL();\r
+ {\r
+ /* Cascade two 8bit timer channels to generate the interrupts. \r
+ 8bit timer unit 1 (TMR0 and TMR1) and 8bit timer unit 2 (TMR2 and TMR3 are\r
+ utilised for this test. */\r
+\r
+ /* Enable the timers. */\r
+ SYSTEM.MSTPCRA.BIT.MSTPA5 = 0;\r
+ SYSTEM.MSTPCRA.BIT.MSTPA4 = 0;\r
+\r
+ /* Enable compare match A interrupt request. */\r
+ TMR0.TCR.BIT.CMIEA = 1;\r
+ TMR2.TCR.BIT.CMIEA = 1;\r
+\r
+ /* Clear the timer on compare match A. */\r
+ TMR0.TCR.BIT.CCLR = 1;\r
+ TMR2.TCR.BIT.CCLR = 1;\r
+\r
+ /* Set the compare match value. */\r
+ TMR01.TCORA = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / tmrTIMER_0_1_FREQUENCY ) -1 ) / 8 );\r
+ TMR23.TCORA = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / tmrTIMER_0_1_FREQUENCY ) -1 ) / 8 );\r
+\r
+ /* 16 bit operation ( count from timer 1,2 ). */\r
+ TMR0.TCCR.BIT.CSS = 3;\r
+ TMR2.TCCR.BIT.CSS = 3;\r
+ \r
+ /* Use PCLK as the input. */\r
+ TMR1.TCCR.BIT.CSS = 1;\r
+ TMR3.TCCR.BIT.CSS = 1;\r
+ \r
+ /* Divide PCLK by 8. */\r
+ TMR1.TCCR.BIT.CKS = 2;\r
+ TMR3.TCCR.BIT.CKS = 2;\r
+ \r
+ /* Enable TMR 0, 2 interrupts. */\r
+ IEN( TMR0, CMIA0 ) = 1;\r
+ IEN( TMR2, CMIA2 ) = 1;\r
+\r
+ /* Set the timer interrupts to be above the kernel. The interrupts are\r
+ assigned different priorities so they nest with each other. */\r
+ IPR( TMR0, CMIA0 ) = configMAX_SYSCALL_INTERRUPT_PRIORITY - 1;\r
+ IPR( TMR2, CMIA2 ) = ( configMAX_SYSCALL_INTERRUPT_PRIORITY - 2 );\r
+ }\r
+ portEXIT_CRITICAL();\r
+ \r
+ /* Ensure the interrupts are clear as they are edge detected. */\r
+ IR( TMR0, CMIA0 ) = 0;\r
+ IR( TMR2, CMIA2 ) = 0;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#pragma interrupt ( vT0_1InterruptHandler( vect = VECT_TMR0_CMIA0, enable ) )\r
+void vT0_1InterruptHandler( void )\r
+{\r
+ portYIELD_FROM_ISR( xFirstTimerHandler() );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#pragma interrupt ( vT2_3InterruptHandler( vect = VECT_TMR2_CMIA2, enable ) )\r
+void vT2_3InterruptHandler( void )\r
+{\r
+ portYIELD_FROM_ISR( xSecondTimerHandler() );\r
+}\r
+\r
+\r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd.\r
+ \r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ >>>NOTE<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ http://www.FreeRTOS.org - Documentation, latest information, license and\r
+ contact details.\r
+\r
+ http://www.SafeRTOS.com - A version that is certified for use in safety\r
+ critical systems.\r
+\r
+ http://www.OpenRTOS.com - Commercial support, development, porting,\r
+ licensing and training services.\r
+*/\r
+\r
+/*-----------------------------------------------------------\r
+ * Simple IO routines to control the LEDs.\r
+ *-----------------------------------------------------------*/\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Demo includes. */\r
+#include "partest.h"\r
+\r
+/* Hardware specifics. */\r
+#include "iodefine.h"\r
+\r
+#define partestNUM_LEDS ( 4 )\r
+\r
+long lParTestGetLEDState( unsigned long ulLED );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestInitialise( void )\r
+{\r
+ /* Port pin configuration is done by the low level set up prior to this \r
+ function being called. */\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestSetLED( unsigned long ulLED, signed long xValue )\r
+{\r
+ if( ulLED < partestNUM_LEDS )\r
+ {\r
+ if( xValue != 0 )\r
+ {\r
+ /* Turn the LED on. */\r
+ taskENTER_CRITICAL();\r
+ {\r
+ switch( ulLED )\r
+ {\r
+ case 0: LED0 = LED_ON;\r
+ break;\r
+ case 1: LED1 = LED_ON;\r
+ break;\r
+ case 2: LED2 = LED_ON;\r
+ break;\r
+ case 3: LED3 = LED_ON;\r
+ break;\r
+ }\r
+ }\r
+ taskEXIT_CRITICAL();\r
+ }\r
+ else\r
+ {\r
+ /* Turn the LED off. */\r
+ taskENTER_CRITICAL();\r
+ {\r
+ switch( ulLED )\r
+ {\r
+ case 0: LED0 = LED_OFF;\r
+ break;\r
+ case 1: LED1 = LED_OFF;\r
+ break;\r
+ case 2: LED2 = LED_OFF;\r
+ break;\r
+ case 3: LED3 = LED_OFF;\r
+ break;\r
+ }\r
+\r
+ }\r
+ taskEXIT_CRITICAL();\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestToggleLED( unsigned long ulLED )\r
+{\r
+ if( ulLED < partestNUM_LEDS )\r
+ {\r
+ taskENTER_CRITICAL();\r
+ {\r
+ if( lParTestGetLEDState( ulLED ) != 0x00 )\r
+ {\r
+ vParTestSetLED( ulLED, 0 );\r
+ }\r
+ else\r
+ {\r
+ vParTestSetLED( ulLED, 1 );\r
+ }\r
+ }\r
+ taskEXIT_CRITICAL();\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+ \r
+long lParTestGetLEDState( unsigned long ulLED )\r
+{\r
+long lReturn = pdTRUE;\r
+\r
+ if( ulLED < partestNUM_LEDS )\r
+ {\r
+ switch( ulLED )\r
+ {\r
+ case 0 : if( LED0 != 0 )\r
+ {\r
+ lReturn = pdFALSE;\r
+ }\r
+ break; \r
+ case 1 : if( LED1 != 0 )\r
+ {\r
+ lReturn = pdFALSE;\r
+ }\r
+ break; \r
+ case 2 : if( LED2 != 0 )\r
+ {\r
+ lReturn = pdFALSE;\r
+ }\r
+ break; \r
+ case 3 : if( LED3 != 0 )\r
+ {\r
+ lReturn = pdFALSE;\r
+ }\r
+ break; \r
+ }\r
+ }\r
+ \r
+ return lReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+
\ No newline at end of file
--- /dev/null
+[HIMDBVersion]\r
+2.0\r
+[DATABASE_VERSION]\r
+"2.8" \r
+[PROJECT_DETAILS]\r
+"RTOSDemo" "C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX630-RSK_Renesas\RTOSDemo" "C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX630-RSK_Renesas\RTOSDemo\RTOSDemo.hwp" "RX" "Renesas RX Standard" "Application" "RX600" "Other" \r
+[INFORMATION]\r
+"No project information available" \r
+[TOOL_CHAIN]\r
+"Renesas RX Standard Toolchain" "1.1.0.0" \r
+[CONFIGURATIONS]\r
+"Blinky" "C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX630-RSK_Renesas\RTOSDemo\Blinky" \r
+"Debug" "C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX630-RSK_Renesas\RTOSDemo\Debug" \r
+"Debug_RX600_E1_E20_SYSTEM" "C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX630-RSK_Renesas\RTOSDemo\Debug_RX600_E1_E20_SYSTEM" \r
+"Debug_with_optimisation" "C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX630-RSK_Renesas\RTOSDemo\Debug_with_optimisation" \r
+"SimDebug_RX600" "C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX630-RSK_Renesas\RTOSDemo\SimDebug_RX600" \r
+[BUILD_PHASES]\r
+"Renesas OptLinker" 1 \r
+"Renesas RX Assembler" 1 \r
+"Renesas RX C/C++ Compiler" 1 \r
+"Renesas RX C/C++ Library Generator" 1 \r
+"Renesas RX Configurator" 1 \r
+[TOOL_ENVIRONMENT]\r
+[EXTENSIONS]\r
+"Absolute file" "ABS" \r
+"Assembly include file" "INC" \r
+"Assembly list file" "LST" \r
+"Assembly source file" "S" \r
+"Assembly source file" "SRC" \r
+"Binary file" "BIN" \r
+"C header file" "H" \r
+"C source file" "C" \r
+"C++ header file" "HPP" \r
+"C++ source file" "CC" \r
+"C++ source file" "CP" \r
+"C++ source file" "CPP" \r
+"CPU information file" "CPU" \r
+"Calling information file" "CAL" \r
+"Configuration file" "CFG" \r
+"Debug information file" "DBG" \r
+"Hex file" "HEX" \r
+"Library file" "LIB" \r
+"Library information file" "LBP" \r
+"Linkage map file" "MAP" \r
+"Linkage symbol file" "FSY" \r
+"Object file" "OBJ" \r
+"Optimize map file" "bls" \r
+"Preprocessed C source file" "P" \r
+"Preprocessed C++ source file" "PP" \r
+"Relocatable file" "REL" \r
+"Rts information file" "RTS" \r
+"S-Record file" "MOT" \r
+"Stack information file" "SNI" \r
+"TD include object file" "RTI" \r
+[FILE_GROUPS]\r
+"Absolute file" "BIN" "NONE" "" \r
+"Assembly include file" "TEXT" "EDITOR" "" \r
+"Assembly list file" "TEXT" "EDITOR" "" \r
+"Assembly source file" "TEXT" "EDITOR" "" \r
+"Binary file" "BIN" "NONE" "" \r
+"C header file" "TEXT" "EDITOR" "" \r
+"C source file" "TEXT" "EDITOR" "" \r
+"C++ header file" "TEXT" "EDITOR" "" \r
+"C++ source file" "TEXT" "EDITOR" "" \r
+"CPU information file" "BIN" "NONE" "" \r
+"Calling information file" "BIN" "NONE" "" \r
+"Configuration file" "TEXT" "EDITOR" "" \r
+"Debug information file" "BIN" "NONE" "" \r
+"Hex file" "TEXT" "EDITOR" "" \r
+"Library file" "BIN" "NONE" "" \r
+"Library information file" "TEXT" "EDITOR" "" \r
+"Linkage map file" "TEXT" "EDITOR" "" \r
+"Linkage symbol file" "TEXT" "EDITOR" "" \r
+"Object file" "BIN" "NONE" "" \r
+"Optimize map file" "BIN" "NONE" "" \r
+"Preprocessed C source file" "TEXT" "EDITOR" "" \r
+"Preprocessed C++ source file" "TEXT" "EDITOR" "" \r
+"Relocatable file" "BIN" "NONE" "" \r
+"Rts information file" "BIN" "NONE" "" \r
+"S-Record file" "TEXT" "EDITOR" "" \r
+"Stack information file" "BIN" "NONE" "" \r
+"TD include object file" "BIN" "NONE" "" \r
+[ASSOCIATED_APPLICATIONS]\r
+[TOOLCHAIN_PHASE]\r
+"Renesas OptLinker" \r
+"Renesas RX Assembler" \r
+"Renesas RX C/C++ Compiler" \r
+"Renesas RX C/C++ Library Generator" \r
+"Renesas RX Configurator" \r
+[UTILITY_PHASE]\r
+[CUSTOM_PHASES]\r
+[CUSTOM_PHASE_INPUT_GROUP]\r
+[CUSTOM_PHASE_OUTPUT_SYNTAX]\r
+[BUILD_ORDER]\r
+"Renesas RX C/C++ Library Generator" 1 \r
+"Renesas RX C/C++ Compiler" 1 \r
+"Renesas RX Assembler" 1 \r
+"Renesas OptLinker" 1 \r
+"Renesas RX Configurator" 0 \r
+[BUILD_PHASE_DETAILS]\r
+"Renesas OptLinker" "Object file|Library file|Relocatable file" 0 \r
+"Renesas RX Assembler" "Assembly source file|Linkage symbol file" 1 \r
+"Renesas RX C/C++ Compiler" "C source file|C++ source file" 1 \r
+"Renesas RX C/C++ Library Generator" "" 0 \r
+"Renesas RX Configurator" "Configuration file" 0 \r
+[BUILD_FILE_ORDER_Assembly source file]\r
+"Renesas RX Assembler" 1 \r
+[BUILD_FILE_ORDER_C source file]\r
+"Renesas RX C/C++ Compiler" 1 \r
+[BUILD_FILE_ORDER_C++ source file]\r
+"Renesas RX C/C++ Compiler" 1 \r
+[BUILD_FILE_ORDER_Linkage symbol file]\r
+"Renesas RX Assembler" 1 \r
+[SCRAP]\r
+"Project Generator Setup File" "" \r
+[MAPPINGS]\r
+"Assembly source file" "Renesas RX Assembler" "Renesas RX C/C++ Compiler" \r
+"Library file" "Renesas OptLinker" "Renesas RX C/C++ Library Generator" \r
+"Object file" "Renesas OptLinker" "Renesas RX Assembler" \r
+"Object file" "Renesas OptLinker" "Renesas RX C/C++ Compiler" \r
+[PROJECT_FILES]\r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\BlockQ.c" "User" "C source file|Common demo tasks" 2 \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\GenQTest.c" "User" "C source file|Common demo tasks" 2 \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\IntQueue.c" "User" "C source file|Common demo tasks" 2 \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\PollQ.c" "User" "C source file|Common demo tasks" 2 \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\QPeek.c" "User" "C source file|Common demo tasks" 2 \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\blocktim.c" "User" "C source file|Common demo tasks" 2 \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\death.c" "User" "C source file|Common demo tasks" 2 \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\flash.c" "User" "C source file|Common demo tasks" 2 \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\flop.c" "User" "C source file|Common demo tasks" 2 \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\integer.c" "User" "C source file|Common demo tasks" 2 \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\recmutex.c" "User" "C source file|Common demo tasks" 2 \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\semtest.c" "User" "C source file|Common demo tasks" 2 \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX630-RSK_Renesas\RTOSDemo\HighFrequencyTimerTest.c" "User" "C source file" 2 \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX630-RSK_Renesas\RTOSDemo\IntQueueTimer.c" "User" "C source file" 2 \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX630-RSK_Renesas\RTOSDemo\ParTest.c" "User" "C source file" 2 \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX630-RSK_Renesas\RTOSDemo\Renesas-Files\cgc.c" "User" "C source file|Renesas Files" 2 \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX630-RSK_Renesas\RTOSDemo\Renesas-Files\dbsct.c" "User" "C source file|Renesas Files" 2 \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX630-RSK_Renesas\RTOSDemo\Renesas-Files\hwsetup.c" "User" "C source file|Renesas Files" 2 \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX630-RSK_Renesas\RTOSDemo\Renesas-Files\intprg.c" "User" "C source file|Renesas Files" 2 \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX630-RSK_Renesas\RTOSDemo\Renesas-Files\lowlvl.src" "User" "C source file|Renesas Files" 2 \r
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+"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX630-RSK_Renesas\RTOSDemo\Renesas-Files\resetprg.c" "User" "C source file|Renesas Files" 2 \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX630-RSK_Renesas\RTOSDemo\Renesas-Files\sbrk.c" "User" "C source file|Renesas Files" 2 \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX630-RSK_Renesas\RTOSDemo\Renesas-Files\vecttbl.c" "User" "C source file|Renesas Files" 2 \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX630-RSK_Renesas\RTOSDemo\main-blinky.c" "User" "C source file" 2 \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX630-RSK_Renesas\RTOSDemo\main-full.c" "User" "C source file" 2 \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Source\list.c" "User" "C source file|FreeRTOS" 2 \r
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+"C:\E\Dev\FreeRTOS\WorkingCopy\Source\portable\Renesas\RX600\port_asm.src" "User" "C source file|FreeRTOS|Portable layer" 2 \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Source\queue.c" "User" "C source file|FreeRTOS" 2 \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Source\tasks.c" "User" "C source file|FreeRTOS" 2 \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Source\timers.c" "User" "C source file" 2 \r
+[FOLDER]\r
+"Assembly source file" "Assembly source file" \r
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+"C source file|FreeRTOS" "" \r
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+"C source file|Renesas Files" "" \r
+[GENERAL_DATA_PROJECT]\r
+"FDT_AutoConnect" "0" \r
+"FDT_BaseDevice" "" \r
+"FDT_BaudRate" "" \r
+"FDT_BlockLockConnect" "1" \r
+"FDT_BlockLockDisconnect" "1" \r
+"FDT_BootMode" "FALSE" \r
+"FDT_CKM" "0" \r
+"FDT_CKP" "0" \r
+"FDT_ClockMode" "0" \r
+"FDT_ClockSync" "00000000" \r
+"FDT_Comments" "" \r
+"FDT_ConnectionResetSuppression" "FFFFFFFF" \r
+"FDT_Device" "" \r
+"FDT_DoReadbackVerification" "" \r
+"FDT_DoSecurityProtection" "" \r
+"FDT_DoSecurityProtectionLevel" "" \r
+"FDT_Frequency" "0.0000" \r
+"FDT_Interface" "" \r
+"FDT_InternalClock" "FALSE" \r
+"FDT_KernelPath" "" \r
+"FDT_KernelResident" "FALSE" \r
+"FDT_McuId" "0" \r
+"FDT_MessageLevel" "0" \r
+"FDT_PinOutputs" "00000000" \r
+"FDT_PinSettings" "00000000" \r
+"FDT_Port" "" \r
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+"C:\E\Dev\FreeRTOS\WorkingCopy\Source\portable\MemMang\heap_2.c" "02d403988738cc10" 2 \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Source\portable\Renesas\RX600\port.c" "02d403988738cc10" 2 \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Source\queue.c" "02d403988738cc10" 2 \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Source\tasks.c" "02d403988738cc10" 2 \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Source\timers.c" "02d403988738cc10" 2 \r
+[OPTIONS_Debug_with_optimisation_Renesas RX C/C++ Library Generator]\r
+"Single Shot" "09dd6402da28cc10" 1 \r
+[OPTIONS_Debug_with_optimisation_Renesas RX Configurator]\r
+"Single Shot" "0bf59a677438cc10" 6 \r
+[OPTIONS_Debug_with_optimisation]\r
+"" 0 \r
+"[V|VERSION|1] [B|COMMAND|1] [S|SPEC|UITRON4] [S|OUTPUTPATH|^"$(CONFIGDIR)^"] [S|CPU|RX600] [S|ENDIAN|LITTLE] [S|FINT_REGISTER|0]" 6 \r
+"[V|VERSION|1] [B|SJIS|1] [B|DEBUG|1] [S|OUTPUTPATH|^"$(CONFIGDIR)\$(FILELEAF).obj^"] [S|CPU|RX600] [S|BASE|00000000=NONE] [B|SKIPDEPENDENCY|1]\r
+" 4 \r
+"[V|VERSION|1] [S|LANG|CPP] [B|SJIS|1] [S|INCLUDE|^"$(PROJDIR)\..\..\..\Source\portable\Renesas\RX600^"|^"$(PROJDIR)\..\..\..\Source\include^"|^"$(PROJDIR)\.^"|^"$(PROJDIR)\..\..\include^"|^"$(PROJDIR)\..\..\Common\include^"|^"$(PROJDIR)\.\include^"|^"$(PROJDIR)\Renesas-Files^"] [S|DEFINE|INCLUDE_HIGH_FREQUENCY_TIMER_TEST=1] [S|CHANGE_MESSAGE|INFORMATION|] [S|OUTPUTPATH|^"$(CONFIGDIR)\$(FILELEAF).obj^"] [B|DEBUG|1] [S|OPTIMIZE|MAX] [B|SIZE|1] [B|MAP|1] [S|MAPPATH|^"$(CONFIGDIR)\$(PROJECTNAME).bls^"] [I|INLINE|100] [I|LOOP|2] [S|MISRA2004_CHECK_RULE|ALL] [S|MISRA2004_RULE|1.1|3.4|4.1|5.2|5.3|5.4|5.5|5.6|5.7|6.1|6.2|6.3|6.4|6.5|7.1|8.1|8.2|8.3|8.5|8.6|8.7|8.8|8.11|8.12|9.2|9.3|10.1|10.2|10.3|10.4|10.5|10.6|11.1|11.2|11.3|11.4|11.5|12.1|12.2|12.3|12.4|12.5|12.6|12.7|12.8|12.9|12.10|12.11|12.12|12.13|13.1|13.2|13.3|13.4|13.7|14.1|14.2|14.3|14.4|14.5|14.6|14.7|14.8|14.9|14.10|15.1|15.2|15.3|15.4|15.5|16.1|16.2|16.3|16.4|16.5|16.6|16.8|16.9|17.3|17.4|17.5|17.6|18.1|18.2|18.4|19.1|20.2|20.4|20.5|20.7|20.8|20.9|20.10|20.11|20.12] [S|MISRA1998_CHECK_RULE|ALL] [S|MISRA1998_RULE|1|5|8|12|13|14|17|18|19|20|21|22|24|28|29|31|32|33|34|35|36|37|38|39|40|42|43|44|45|46|48|49|50|51|53|54|55|56|57|58|59|60|61|62|63|64|65|68|69|70|71|72|73|74|75|76|77|78|79|80|82|83|84|85|99|101|102|103|104|105|106|108|110|111|112|113|115|118|119|121|122|123|124|125|126|127] [S|MISRA_GROUP_FILE_PATH|^"$(PROJDIR)\$(PROJECTNAME).rde^"] [S|CPU|RX600] [S|BASE|00000000=NONE] [I|PID|16] [B|SKIPDEPENDENCY|1] [N|DEPENDSCAN|1]\r
+" 3 \r
+"[V|VERSION|1] [S|LANG|C] [B|SJIS|1] [S|INCLUDE|^"$(PROJDIR)\..\..\..\Source\portable\Renesas\RX600^"|^"$(PROJDIR)\..\..\..\Source\include^"|^"$(PROJDIR)\.^"|^"$(PROJDIR)\..\..\include^"|^"$(PROJDIR)\..\..\Common\include^"|^"$(PROJDIR)\.\include^"|^"$(PROJDIR)\Renesas-Files^"] [S|DEFINE|INCLUDE_HIGH_FREQUENCY_TIMER_TEST=1] [S|CHANGE_MESSAGE|INFORMATION|] [S|OUTPUTPATH|^"$(CONFIGDIR)\$(FILELEAF).obj^"] [B|DEBUG|1] [S|OPTIMIZE|MAX] [B|SIZE|1] [B|MAP|1] [S|MAPPATH|^"$(CONFIGDIR)\$(PROJECTNAME).bls^"] [I|INLINE|100] [I|LOOP|2] [S|MISRA2004_CHECK_RULE|ALL] [S|MISRA2004_RULE|1.1|3.4|4.1|5.2|5.3|5.4|5.5|5.6|5.7|6.1|6.2|6.3|6.4|6.5|7.1|8.1|8.2|8.3|8.5|8.6|8.7|8.8|8.11|8.12|9.2|9.3|10.1|10.2|10.3|10.4|10.5|10.6|11.1|11.2|11.3|11.4|11.5|12.1|12.2|12.3|12.4|12.5|12.6|12.7|12.8|12.9|12.10|12.11|12.12|12.13|13.1|13.2|13.3|13.4|13.7|14.1|14.2|14.3|14.4|14.5|14.6|14.7|14.8|14.9|14.10|15.1|15.2|15.3|15.4|15.5|16.1|16.2|16.3|16.4|16.5|16.6|16.8|16.9|17.3|17.4|17.5|17.6|18.1|18.2|18.4|19.1|20.2|20.4|20.5|20.7|20.8|20.9|20.10|20.11|20.12] [S|MISRA1998_CHECK_RULE|ALL] [S|MISRA1998_RULE|1|5|8|12|13|14|17|18|19|20|21|22|24|28|29|31|32|33|34|35|36|37|38|39|40|42|43|44|45|46|48|49|50|51|53|54|55|56|57|58|59|60|61|62|63|64|65|68|69|70|71|72|73|74|75|76|77|78|79|80|82|83|84|85|99|101|102|103|104|105|106|108|110|111|112|113|115|118|119|121|122|123|124|125|126|127] [S|MISRA_GROUP_FILE_PATH|^"$(PROJDIR)\$(PROJECTNAME).rde^"] [S|CPU|RX600] [S|BASE|00000000=NONE] [I|PID|16] [B|SKIPDEPENDENCY|1] [N|DEPENDSCAN|1]\r
+" 2 \r
+"[V|VERSION|1] [S|MODE|BUILD/CHANGED] [S|EXISTOUTPUTPATH|^"$(CONFIGDIR)\$(PROJECTNAME).lib^"] [B|RUNTIME|1] [B|MATH|1] [B|STDIO|1] [B|STDLIB|1] [B|STRING|1] [B|NOFLOAT|1] [S|OUTPUTPATH|^"$(CONFIGDIR)\$(PROJECTNAME).lib^"] [B|SIZE|1] [I|INLINE|100] [I|LOOP|2] [S|CPU|RX600] [S|BASE|00000000=NONE] [B|SKIPDEPENDENCY|1]\r
+" 1 \r
+"[V|VERSION|6] [S|FORM|STYPE] [S|BYTE_COUNT_VALUE|FF] [B|DEBUG|1] [S|ROM|(D,R)|(D_1,R_1)|(D_2,R_2)] [S|CRC|NONE|DEFAULT|00000000] [B|LIST|1] [S|LIST|^"$(CONFIGDIR)\$(PROJECTNAME).map^"] [S|SHOW|METHODCUSTOM|] [S|OUTPUT|^"$(CONFIGDIR)\$(PROJECTNAME).mot^"] [B|MAP|1] [S|MAPPATH|^"$(CONFIGDIR)\$(PROJECTNAME).bls^"] [I|SPACE|^"FF^"] [S|OPTIMIZEITEMS|SPEED] [S|START|B_RX_DESC,B_TX_DESC,B_ETHERNET_BUFFERS,B_1,R_1,B_2,R_2,B,R,SU,SI(00)|PResetPRG(0FFE00000)|C_1,C_2,C,C$*,D*,P,PIntPRG,W*,L(0FFE01000)|FIXEDVECT(0FFFFFFD0)] [B|SKIPDEPENDENCY|1]\r
+" 5 \r
+[EXCLUDED_FILES_Debug_with_optimisation]\r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX630-RSK_Renesas\RTOSDemo\main-blinky.c" \r
+[LINKAGE_ORDER_Debug_with_optimisation]\r
+[GENERAL_DATA_CONFIGURATION_Debug_with_optimisation]\r
+[OPTIONS_SimDebug_RX600_Renesas OptLinker]\r
+"Single Shot" "027615ed9738cc10" 5 \r
+[OPTIONS_SimDebug_RX600_Renesas RX Assembler]\r
+"Assembly source file" "07f86402da28cc10" 4 \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX630-RSK_Renesas\RTOSDemo\Renesas-Files\lowlvl.src" "07f86402da28cc10" 4 \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Source\portable\Renesas\RX600\port_asm.src" "07f86402da28cc10" 4 \r
+"Linkage symbol file" "07f86402da28cc10" 4 \r
+[OPTIONS_SimDebug_RX600_Renesas RX C/C++ Compiler]\r
+"C source file" "074935dc9738cc10" 2 \r
+"C++ source file" "074935dc9738cc10" 3 \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\BlockQ.c" "074935dc9738cc10" 2 \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\GenQTest.c" "074935dc9738cc10" 2 \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\IntQueue.c" "074935dc9738cc10" 2 \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\PollQ.c" "074935dc9738cc10" 2 \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\QPeek.c" "074935dc9738cc10" 2 \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\blocktim.c" "074935dc9738cc10" 2 \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\death.c" "074935dc9738cc10" 2 \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\flash.c" "074935dc9738cc10" 2 \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\flop.c" "074935dc9738cc10" 2 \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\integer.c" "074935dc9738cc10" 2 \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\recmutex.c" "074935dc9738cc10" 2 \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\semtest.c" "074935dc9738cc10" 2 \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX630-RSK_Renesas\RTOSDemo\HighFrequencyTimerTest.c" "074935dc9738cc10" 2 \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX630-RSK_Renesas\RTOSDemo\IntQueueTimer.c" "074935dc9738cc10" 2 \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX630-RSK_Renesas\RTOSDemo\ParTest.c" "074935dc9738cc10" 2 \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX630-RSK_Renesas\RTOSDemo\Renesas-Files\cgc.c" "074935dc9738cc10" 2 \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX630-RSK_Renesas\RTOSDemo\Renesas-Files\dbsct.c" "074935dc9738cc10" 2 \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX630-RSK_Renesas\RTOSDemo\Renesas-Files\hwsetup.c" "074935dc9738cc10" 2 \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX630-RSK_Renesas\RTOSDemo\Renesas-Files\intprg.c" "074935dc9738cc10" 2 \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX630-RSK_Renesas\RTOSDemo\Renesas-Files\lowsrc.c" "074935dc9738cc10" 2 \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX630-RSK_Renesas\RTOSDemo\Renesas-Files\resetprg.c" "074935dc9738cc10" 2 \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX630-RSK_Renesas\RTOSDemo\Renesas-Files\sbrk.c" "074935dc9738cc10" 2 \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX630-RSK_Renesas\RTOSDemo\Renesas-Files\vecttbl.c" "074935dc9738cc10" 2 \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX630-RSK_Renesas\RTOSDemo\main-blinky.c" "074935dc9738cc10" 2 \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX630-RSK_Renesas\RTOSDemo\main-full.c" "074935dc9738cc10" 2 \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Source\list.c" "074935dc9738cc10" 2 \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Source\portable\MemMang\heap_2.c" "074935dc9738cc10" 2 \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Source\portable\Renesas\RX600\port.c" "074935dc9738cc10" 2 \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Source\queue.c" "074935dc9738cc10" 2 \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Source\tasks.c" "074935dc9738cc10" 2 \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Source\timers.c" "074935dc9738cc10" 2 \r
+[OPTIONS_SimDebug_RX600_Renesas RX C/C++ Library Generator]\r
+"Single Shot" "0cd2772f9738cc10" 1 \r
+[OPTIONS_SimDebug_RX600_Renesas RX Configurator]\r
+"Single Shot" "0bf59a677438cc10" 6 \r
+[OPTIONS_SimDebug_RX600]\r
+"" 0 \r
+"[V|VERSION|1] [B|COMMAND|1] [S|SPEC|UITRON4] [S|OUTPUTPATH|^"$(CONFIGDIR)^"] [S|CPU|RX600] [S|ENDIAN|LITTLE] [S|FINT_REGISTER|0]" 6 \r
+"[V|VERSION|1] [B|DEBUG|1] [S|OUTPUTPATH|^"$(CONFIGDIR)\$(FILELEAF).obj^"] [B|LISTFILE|0] [S|CPU|RX600] [S|ENDIAN|LITTLE] [S|FINT_REGISTER|0]" 4 \r
+"[V|VERSION|1] [S|LANG|CPP] [B|SJIS|1] [S|INCLUDE|^"$(PROJDIR)\..\..\..\Source\portable\Renesas\RX600^"|^"$(PROJDIR)\..\..\..\Source\include^"|^"$(PROJDIR)^"|^"$(PROJDIR)\..\..\include^"|^"$(PROJDIR)\..\..\Common\include^"|^"$(PROJDIR)\.\include^"|^"$(PROJDIR)\Renesas-Files^"] [S|OUTPUTPATH|^"$(CONFIGDIR)\$(FILELEAF).obj^"] [B|DEBUG|1] [B|SIZE|1] [B|MAP|0] [I|INLINE|100] [I|LOOP|2] [S|MISRA2004_CHECK_RULE|ALL] [S|MISRA2004_RULE|1.1|3.4|4.1|5.2|5.3|5.4|5.5|5.6|5.7|6.1|6.2|6.3|6.4|6.5|7.1|8.1|8.2|8.3|8.5|8.6|8.7|8.8|8.11|8.12|9.2|9.3|10.1|10.2|10.3|10.4|10.5|10.6|11.1|11.2|11.3|11.4|11.5|12.1|12.2|12.3|12.4|12.5|12.6|12.7|12.8|12.9|12.10|12.11|12.12|12.13|13.1|13.2|13.3|13.4|13.7|14.1|14.2|14.3|14.4|14.5|14.6|14.7|14.8|14.9|14.10|15.1|15.2|15.3|15.4|15.5|16.1|16.2|16.3|16.4|16.5|16.6|16.8|16.9|17.3|17.4|17.5|17.6|18.1|18.2|18.4|19.1|20.2|20.4|20.5|20.7|20.8|20.9|20.10|20.11|20.12] [S|MISRA1998_CHECK_RULE|ALL] [S|MISRA1998_RULE|1|5|8|12|13|14|17|18|19|20|21|22|24|28|29|31|32|33|34|35|36|37|38|39|40|42|43|44|45|46|48|49|50|51|53|54|55|56|57|58|59|60|61|62|63|64|65|68|69|70|71|72|73|74|75|76|77|78|79|80|82|83|84|85|99|101|102|103|104|105|106|108|110|111|112|113|115|118|119|121|122|123|124|125|126|127] [S|MISRA_GROUP_FILE_PATH|^"$(PROJDIR)\$(PROJECTNAME).rde^"] [S|CPU|RX600] [S|BASE|00000000=NONE] [I|PID|16]\r
+" 3 \r
+"[V|VERSION|1] [S|LANG|C] [B|SJIS|1] [S|INCLUDE|^"$(PROJDIR)\..\..\..\Source\portable\Renesas\RX600^"|^"$(PROJDIR)\..\..\..\Source\include^"|^"$(PROJDIR)^"|^"$(PROJDIR)\..\..\include^"|^"$(PROJDIR)\..\..\Common\include^"|^"$(PROJDIR)\.\include^"|^"$(PROJDIR)\Renesas-Files^"] [S|OUTPUTPATH|^"$(CONFIGDIR)\$(FILELEAF).obj^"] [B|DEBUG|1] [B|SIZE|1] [B|MAP|0] [I|INLINE|100] [I|LOOP|2] [S|MISRA2004_CHECK_RULE|ALL] [S|MISRA2004_RULE|1.1|3.4|4.1|5.2|5.3|5.4|5.5|5.6|5.7|6.1|6.2|6.3|6.4|6.5|7.1|8.1|8.2|8.3|8.5|8.6|8.7|8.8|8.11|8.12|9.2|9.3|10.1|10.2|10.3|10.4|10.5|10.6|11.1|11.2|11.3|11.4|11.5|12.1|12.2|12.3|12.4|12.5|12.6|12.7|12.8|12.9|12.10|12.11|12.12|12.13|13.1|13.2|13.3|13.4|13.7|14.1|14.2|14.3|14.4|14.5|14.6|14.7|14.8|14.9|14.10|15.1|15.2|15.3|15.4|15.5|16.1|16.2|16.3|16.4|16.5|16.6|16.8|16.9|17.3|17.4|17.5|17.6|18.1|18.2|18.4|19.1|20.2|20.4|20.5|20.7|20.8|20.9|20.10|20.11|20.12] [S|MISRA1998_CHECK_RULE|ALL] [S|MISRA1998_RULE|1|5|8|12|13|14|17|18|19|20|21|22|24|28|29|31|32|33|34|35|36|37|38|39|40|42|43|44|45|46|48|49|50|51|53|54|55|56|57|58|59|60|61|62|63|64|65|68|69|70|71|72|73|74|75|76|77|78|79|80|82|83|84|85|99|101|102|103|104|105|106|108|110|111|112|113|115|118|119|121|122|123|124|125|126|127] [S|MISRA_GROUP_FILE_PATH|^"$(PROJDIR)\$(PROJECTNAME).rde^"] [S|CPU|RX600] [S|BASE|00000000=NONE] [I|PID|16]\r
+" 2 \r
+"[V|VERSION|1] [S|MODE|BUILD/CHANGED] [S|EXISTOUTPUTPATH|^"$(CONFIGDIR)\$(PROJECTNAME).lib^"] [B|RUNTIME|1] [B|MATH|1] [B|STDIO|1] [B|STDLIB|1] [B|STRING|1] [B|NEW|1] [S|OUTPUTPATH|^"$(CONFIGDIR)\$(PROJECTNAME).lib^"] [B|SIZE|1] [I|INLINE|100] [I|LOOP|2] [S|CPU|RX600] [S|BASE|00000000=NONE] [I|PID|16]\r
+" 1 \r
+"[V|VERSION|6] [S|FORM|STYPE] [S|BYTE_COUNT_VALUE|FF] [B|DEBUG|1] [S|ROM|(D,R)|(D_1,R_1)|(D_2,R_2)] [S|CRC|NONE|DEFAULT|00000000] [B|LIST|1] [S|LIST|^"$(CONFIGDIR)\$(PROJECTNAME).map^"] [S|SHOW|METHODCUSTOM|] [S|OUTPUT|^"$(CONFIGDIR)\$(PROJECTNAME).mot^"] [I|SPACE|^"FF^"] [B|OPTIMIZE|0] [S|START|B_1,R_1,B_2,R_2,B,R,SU,SI(00)|PResetPRG(0FFE00000)|C_1,C_2,C,C$*,D*,P,PIntPRG,W*,L(0FFE01000)|FIXEDVECT(0FFFFFFD0)]\r
+" 5 \r
+[EXCLUDED_FILES_SimDebug_RX600]\r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX630-RSK_Renesas\RTOSDemo\main-blinky.c" \r
+[LINKAGE_ORDER_SimDebug_RX600]\r
+[GENERAL_DATA_CONFIGURATION_SimDebug_RX600]\r
+[GENERAL_DATA_CONFIGURATION_SESSION_Blinky_DefaultSession]\r
+[SESSION_DATA_CONFIGURATION_SESSION_Blinky_DefaultSession]\r
+"MEMORY_MAPPING_OPTIONS" "" \r
+[GENERAL_DATA_CONFIGURATION_SESSION_Blinky_SessionRX600_E1_E20_SYSTEM]\r
+[SESSION_DATA_CONFIGURATION_SESSION_Blinky_SessionRX600_E1_E20_SYSTEM]\r
+"MEMORY_MAPPING_OPTIONS" "Unknown Options" \r
+[GENERAL_DATA_CONFIGURATION_SESSION_Blinky_SimSessionRX600]\r
+[SESSION_DATA_CONFIGURATION_SESSION_Blinky_SimSessionRX600]\r
+"MEMORY_MAPPING_OPTIONS" "[V|VERSION|1] [S|CPUTYPE|^"Other (RX600)^"] [S|MAP|^"0x00000000,0x0001FFFF,RAM,32,0101,2 0x00080000,0x000FFFFF,I/O,32,0101,2 0x00100000,0x00107FFF,ROM,32,0101,2 0x007F8000,0x007F9FFF,RAM,32,0101,2 0x007FC000,0x007FC4FF,I/O,32,0101,2 0x007FFC00,0x007FFFFF,I/O,32,0101,2 0x00E00000,0x00FFFFFF,ROM,32,0101,2 0xFEFFE000,0xFEFFFFFF,ROM,32,0101,2 0xFF7FC000,0xFF7FFFFF,ROM,32,0101,2 0xFFE00000,0xFFFFFFFF,ROM,32,0101,2^"] [S|RESOURCE|^"0x00000000,0x0001FFFF,R/W 0x00080000,0x000FFFFF,R/W 0x007FC000,0x007FC4FF,R/W 0x007FFC00,0x007FFFFF,R/W 0xFFFF8000,0xFFFFFFFF,R/W ^"] [B|SIMIOF|0] [I|SIMIOADR|0x0] [I|BUS_MODE|0] [S|ENDIAN|^"LITTLE^"] [S|PATCH|^"OFF^"]" \r
+[GENERAL_DATA_CONFIGURATION_SESSION_Debug_DefaultSession]\r
+[SESSION_DATA_CONFIGURATION_SESSION_Debug_DefaultSession]\r
+"MEMORY_MAPPING_OPTIONS" "" \r
+[GENERAL_DATA_CONFIGURATION_SESSION_Debug_SessionRX600_E1_E20_SYSTEM]\r
+[SESSION_DATA_CONFIGURATION_SESSION_Debug_SessionRX600_E1_E20_SYSTEM]\r
+"MEMORY_MAPPING_OPTIONS" "Unknown Options" \r
+[GENERAL_DATA_CONFIGURATION_SESSION_Debug_SimSessionRX600]\r
+[SESSION_DATA_CONFIGURATION_SESSION_Debug_SimSessionRX600]\r
+"MEMORY_MAPPING_OPTIONS" "[V|VERSION|1] [S|CPUTYPE|^"Other (RX600)^"] [S|MAP|^"0x00000000,0x0001FFFF,RAM,32,0101,2 0x00080000,0x000FFFFF,I/O,32,0101,2 0x00100000,0x00107FFF,ROM,32,0101,2 0x007F8000,0x007F9FFF,RAM,32,0101,2 0x007FC000,0x007FC4FF,I/O,32,0101,2 0x007FFC00,0x007FFFFF,I/O,32,0101,2 0x00E00000,0x00FFFFFF,ROM,32,0101,2 0xFEFFE000,0xFEFFFFFF,ROM,32,0101,2 0xFF7FC000,0xFF7FFFFF,ROM,32,0101,2 0xFFE00000,0xFFFFFFFF,ROM,32,0101,2^"] [S|RESOURCE|^"0x00000000,0x0001FFFF,R/W 0x00080000,0x000FFFFF,R/W 0x007FC000,0x007FC4FF,R/W 0x007FFC00,0x007FFFFF,R/W 0xFFFF8000,0xFFFFFFFF,R/W ^"] [B|SIMIOF|0] [I|SIMIOADR|0x0] [I|BUS_MODE|0] [S|ENDIAN|^"LITTLE^"] [S|PATCH|^"OFF^"]" \r
+[GENERAL_DATA_CONFIGURATION_SESSION_Debug_RX600_E1_E20_SYSTEM_DefaultSession]\r
+[SESSION_DATA_CONFIGURATION_SESSION_Debug_RX600_E1_E20_SYSTEM_DefaultSession]\r
+"MEMORY_MAPPING_OPTIONS" "" \r
+[GENERAL_DATA_CONFIGURATION_SESSION_Debug_RX600_E1_E20_SYSTEM_SessionRX600_E1_E20_SYSTEM]\r
+[SESSION_DATA_CONFIGURATION_SESSION_Debug_RX600_E1_E20_SYSTEM_SessionRX600_E1_E20_SYSTEM]\r
+"MEMORY_MAPPING_OPTIONS" "Unknown Options" \r
+[GENERAL_DATA_CONFIGURATION_SESSION_Debug_RX600_E1_E20_SYSTEM_SimSessionRX600]\r
+[SESSION_DATA_CONFIGURATION_SESSION_Debug_RX600_E1_E20_SYSTEM_SimSessionRX600]\r
+"MEMORY_MAPPING_OPTIONS" "[V|VERSION|1] [S|CPUTYPE|^"Other (RX600)^"] [S|MAP|^"0x00000000,0x0001FFFF,RAM,32,0101,2 0x00080000,0x000FFFFF,I/O,32,0101,2 0x00100000,0x00107FFF,ROM,32,0101,2 0x007F8000,0x007F9FFF,RAM,32,0101,2 0x007FC000,0x007FC4FF,I/O,32,0101,2 0x007FFC00,0x007FFFFF,I/O,32,0101,2 0x00E00000,0x00FFFFFF,ROM,32,0101,2 0xFEFFE000,0xFEFFFFFF,ROM,32,0101,2 0xFF7FC000,0xFF7FFFFF,ROM,32,0101,2 0xFFE00000,0xFFFFFFFF,ROM,32,0101,2^"] [S|RESOURCE|^"0x00000000,0x0001FFFF,R/W 0x00080000,0x000FFFFF,R/W 0x007FC000,0x007FC4FF,R/W 0x007FFC00,0x007FFFFF,R/W 0xFFFF8000,0xFFFFFFFF,R/W ^"] [B|SIMIOF|0] [I|SIMIOADR|0x0] [I|BUS_MODE|0] [S|ENDIAN|^"LITTLE^"] [S|PATCH|^"OFF^"]" \r
+[GENERAL_DATA_CONFIGURATION_SESSION_Debug_with_optimisation_DefaultSession]\r
+[SESSION_DATA_CONFIGURATION_SESSION_Debug_with_optimisation_DefaultSession]\r
+"MEMORY_MAPPING_OPTIONS" "" \r
+[GENERAL_DATA_CONFIGURATION_SESSION_Debug_with_optimisation_SessionRX600_E1_E20_SYSTEM]\r
+[SESSION_DATA_CONFIGURATION_SESSION_Debug_with_optimisation_SessionRX600_E1_E20_SYSTEM]\r
+"MEMORY_MAPPING_OPTIONS" "Unknown Options" \r
+[GENERAL_DATA_CONFIGURATION_SESSION_Debug_with_optimisation_SimSessionRX600]\r
+[SESSION_DATA_CONFIGURATION_SESSION_Debug_with_optimisation_SimSessionRX600]\r
+"MEMORY_MAPPING_OPTIONS" "[V|VERSION|1] [S|CPUTYPE|^"Other (RX600)^"] [S|MAP|^"0x00000000,0x0001FFFF,RAM,32,0101,2 0x00080000,0x000FFFFF,I/O,32,0101,2 0x00100000,0x00107FFF,ROM,32,0101,2 0x007F8000,0x007F9FFF,RAM,32,0101,2 0x007FC000,0x007FC4FF,I/O,32,0101,2 0x007FFC00,0x007FFFFF,I/O,32,0101,2 0x00E00000,0x00FFFFFF,ROM,32,0101,2 0xFEFFE000,0xFEFFFFFF,ROM,32,0101,2 0xFF7FC000,0xFF7FFFFF,ROM,32,0101,2 0xFFE00000,0xFFFFFFFF,ROM,32,0101,2^"] [S|RESOURCE|^"0x00000000,0x0001FFFF,R/W 0x00080000,0x000FFFFF,R/W 0x007FC000,0x007FC4FF,R/W 0x007FFC00,0x007FFFFF,R/W 0xFFFF8000,0xFFFFFFFF,R/W ^"] [B|SIMIOF|0] [I|SIMIOADR|0x0] [I|BUS_MODE|0] [S|ENDIAN|^"LITTLE^"] [S|PATCH|^"OFF^"]" \r
+[GENERAL_DATA_CONFIGURATION_SESSION_SimDebug_RX600_DefaultSession]\r
+[SESSION_DATA_CONFIGURATION_SESSION_SimDebug_RX600_DefaultSession]\r
+"MEMORY_MAPPING_OPTIONS" "" \r
+[GENERAL_DATA_CONFIGURATION_SESSION_SimDebug_RX600_SessionRX600_E1_E20_SYSTEM]\r
+[SESSION_DATA_CONFIGURATION_SESSION_SimDebug_RX600_SessionRX600_E1_E20_SYSTEM]\r
+"MEMORY_MAPPING_OPTIONS" "Unknown Options" \r
+[GENERAL_DATA_CONFIGURATION_SESSION_SimDebug_RX600_SimSessionRX600]\r
+[SESSION_DATA_CONFIGURATION_SESSION_SimDebug_RX600_SimSessionRX600]\r
+"MEMORY_MAPPING_OPTIONS" "[V|VERSION|1] [S|CPUTYPE|^"Other (RX600)^"] [S|MAP|^"0x00000000,0x0001FFFF,RAM,32,0101,2 0x00080000,0x000FFFFF,I/O,32,0101,2 0x00100000,0x00107FFF,ROM,32,0101,2 0x007F8000,0x007F9FFF,RAM,32,0101,2 0x007FC000,0x007FC4FF,I/O,32,0101,2 0x007FFC00,0x007FFFFF,I/O,32,0101,2 0x00E00000,0x00FFFFFF,ROM,32,0101,2 0xFEFFE000,0xFEFFFFFF,ROM,32,0101,2 0xFF7FC000,0xFF7FFFFF,ROM,32,0101,2 0xFFE00000,0xFFFFFFFF,ROM,32,0101,2^"] [S|RESOURCE|^"0x00000000,0x0001FFFF,R/W 0x00080000,0x000FFFFF,R/W 0x007FC000,0x007FC4FF,R/W 0x007FFC00,0x007FFFFF,R/W 0xFFFF8000,0xFFFFFFFF,R/W ^"] [B|SIMIOF|0] [I|SIMIOADR|0x0] [I|BUS_MODE|0] [S|ENDIAN|^"LITTLE^"] [S|PATCH|^"OFF^"]" \r
+[EXT_DEBUGGER_INFO]\r
+0 "" "" "" "" \r
+[END]\r
--- /dev/null
+[HIMDBVersion]\r
+2.0\r
+[DATABASE_VERSION]\r
+"1.1" \r
+[SESSIONS_]\r
+"DefaultSession" \r
+"SessionRX600_E1_E20_SYSTEM" \r
+"SimSessionRX600" \r
+[CONFIGURATIONS]\r
+"Blinky" \r
+"Debug" \r
+"Debug_RX600_E1_E20_SYSTEM" \r
+"Debug_with_optimisation" \r
+"SimDebug_RX600" \r
+[CURRENT_CONFIGURATION]\r
+"Debug" \r
+[CURRENT_SESSION]\r
+"SessionRX600_E1_E20_SYSTEM" \r
+[GENERAL_DATA_PROJECT]\r
+"FDT_UserBootAreaFiles" "" \r
+[GENERAL_DATA_CONFIGURATION_Blinky]\r
+"PROJECT_FILES_MODIFIED_DATA_TAG" "TRUE" \r
+[SESSIONS_Blinky]\r
+"DefaultSession" \r
+"SessionRX600_E1_E20_SYSTEM" \r
+"SimSessionRX600" \r
+[GENERAL_DATA_CONFIGURATION_Debug]\r
+"PROJECT_FILES_MODIFIED_DATA_TAG" "FALSE" \r
+[SESSIONS_Debug]\r
+"DefaultSession" \r
+"SessionRX600_E1_E20_SYSTEM" \r
+"SimSessionRX600" \r
+[GENERAL_DATA_CONFIGURATION_Debug_RX600_E1_E20_SYSTEM]\r
+"PROJECT_FILES_MODIFIED_DATA_TAG" "FALSE" \r
+[SESSIONS_Debug_RX600_E1_E20_SYSTEM]\r
+"DefaultSession" \r
+"SessionRX600_E1_E20_SYSTEM" \r
+"SimSessionRX600" \r
+[GENERAL_DATA_CONFIGURATION_Debug_with_optimisation]\r
+"PROJECT_FILES_MODIFIED_DATA_TAG" "FALSE" \r
+[SESSIONS_Debug_with_optimisation]\r
+"DefaultSession" \r
+"SessionRX600_E1_E20_SYSTEM" \r
+"SimSessionRX600" \r
+[GENERAL_DATA_CONFIGURATION_SimDebug_RX600]\r
+"PROJECT_FILES_MODIFIED_DATA_TAG" "FALSE" \r
+[SESSIONS_SimDebug_RX600]\r
+"DefaultSession" \r
+"SessionRX600_E1_E20_SYSTEM" \r
+"SimSessionRX600" \r
+[GENERAL_DATA_SESSION_SimSessionRX600]\r
+[GENERAL_DATA_SESSION_DefaultSession]\r
+[GENERAL_DATA_CONFIGURATION_SESSION_Debug_with_optimisation_SimSessionRX600]\r
+[GENERAL_DATA_CONFIGURATION_SESSION_Debug_RX600_E1_E20_SYSTEM_SimSessionRX600]\r
+[GENERAL_DATA_CONFIGURATION_SESSION_Blinky_SessionRX600_E1_E20_SYSTEM]\r
+[GENERAL_DATA_CONFIGURATION_SESSION_Blinky_DefaultSession]\r
+[GENERAL_DATA_CONFIGURATION_SESSION_Debug_RX600_E1_E20_SYSTEM_SessionRX600_E1_E20_SYSTEM]\r
+[GENERAL_DATA_CONFIGURATION_SESSION_Debug_DefaultSession]\r
+[GENERAL_DATA_CONFIGURATION_SESSION_SimDebug_RX600_SessionRX600_E1_E20_SYSTEM]\r
+[GENERAL_DATA_CONFIGURATION_SESSION_Debug_RX600_E1_E20_SYSTEM_DefaultSession]\r
+[GENERAL_DATA_CONFIGURATION_SESSION_SimDebug_RX600_DefaultSession]\r
+[GENERAL_DATA_CONFIGURATION_SESSION_Debug_SessionRX600_E1_E20_SYSTEM]\r
+[GENERAL_DATA_CONFIGURATION_SESSION_Debug_SimSessionRX600]\r
+[GENERAL_DATA_CONFIGURATION_SESSION_SimDebug_RX600_SimSessionRX600]\r
+[GENERAL_DATA_CONFIGURATION_SESSION_Debug_with_optimisation_DefaultSession]\r
+[GENERAL_DATA_CONFIGURATION_SESSION_Blinky_SimSessionRX600]\r
+[GENERAL_DATA_CONFIGURATION_SESSION_Debug_with_optimisation_SessionRX600_E1_E20_SYSTEM]\r
+[GENERAL_DATA_SESSION_SessionRX600_E1_E20_SYSTEM]\r
+[END]\r
--- /dev/null
+\r
+\r
+/*******************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only \r
+* intended for use with Renesas products. No other uses are authorized. This \r
+* software is owned by Renesas Electronics Corporation and is protected under\r
+* all applicable laws, including copyright laws.\r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING\r
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT\r
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE \r
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.\r
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS \r
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE \r
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR\r
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE\r
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software\r
+* and to discontinue the availability of this software. By using this software,\r
+* you agree to the additional terms and conditions found by accessing the \r
+* following link:\r
+* http://www.renesas.com/disclaimer\r
+*******************************************************************************/\r
+\r
+\r
+/*\r
+ * cgc.c\r
+ *\r
+ * Created on: 01 Oct 2011\r
+ * Author: RJW\r
+ * Reneses Electronics Europe Ltd\r
+ */\r
+\r
+\r
+/******************************************************************************\r
+ System Includes \r
+******************************************************************************/\r
+\r
+\r
+/******************************************************************************\r
+ User Includes \r
+******************************************************************************/\r
+#include "iodefine.h"\r
+#include "cgc.h"\r
+\r
+\r
+/*****************************************************************************/\r
+/* */\r
+/* Configure the CGC (Clock Generation Circuit) of the RX630 using the */\r
+/* using the 7 STEPS specified in cgc.h */\r
+/* */\r
+/*****************************************************************************/\r
+\r
+\r
+/******************************************************************************\r
+ Function : InitCGC\r
+ Description : Initialises the CGC registers based upon the settings\r
+ made in file cgc.h\r
+ Argument : none\r
+ Return value : none\r
+******************************************************************************/\r
+void InitCGC(void)\r
+{\r
+ unsigned long i;\r
+ \r
+#if (ENABLE_SUB)\r
+ SYSTEM.SOSCCR.BYTE = 0x00; /* Sub-clock oscillator ON */\r
+#else\r
+ SYSTEM.SOSCCR.BYTE = 0x01; /* Sub-clock oscillator OFF */\r
+#endif\r
+\r
+#if (ENABLE_HOCO) \r
+ SYSTEM.HOCOPCR.BYTE = 0x00; /* HOCO PSU ON */\r
+ SYSTEM.HOCOCR.BYTE = 0x00; /* HOCO ON */\r
+#else\r
+ SYSTEM.HOCOPCR.BYTE = 0x01; /* HOCO PSU OFF */\r
+ SYSTEM.HOCOCR.BYTE = 0x01; /* HOCO OFF */\r
+#endif\r
+\r
+\r
+\r
+#if (ENABLE_MAIN) \r
+ SYSTEM.MOSCWTCR.BYTE = 0x0e; /* Main Clock Oscillator Wait Control Register */\r
+ /* 262144 states */\r
+ SYSTEM.MOSCCR.BYTE = 0x00; /* EXTAL ON */\r
+#else\r
+ SYSTEM.MOSCCR.BYTE = 0x01; /* EXTAL OFF */\r
+#endif \r
+\r
+\r
+#if (ENABLE_PLL) \r
+ SYSTEM.MOSCWTCR.BYTE = 0x0e; /* Main Clock Oscillator Wait Control Register */\r
+ /* 262144 states */\r
+ SYSTEM.MOSCCR.BYTE = 0x00; /* EXTAL ON */\r
+ \r
+ SYSTEM.PLLWTCR.BYTE = 0x0e; /* PLL Wait Control Register */\r
+ /* 2097152 states */\r
+ \r
+ SYSTEM.PLLCR2.BYTE = 0x01; /* PLL OFF */\r
+ \r
+ #if (PLL_INPUT_FREQ_DIV == 1)\r
+ SYSTEM.PLLCR.BIT.PLIDIV = 0;\r
+ #elif (PLL_INPUT_FREQ_DIV == 2)\r
+ SYSTEM.PLLCR.BIT.PLIDIV = 1;\r
+ #elif (PLL_INPUT_FREQ_DIV == 4)\r
+ SYSTEM.PLLCR.BIT.PLIDIV = 2;\r
+ #else\r
+ SYSTEM.PLLCR.BIT.PLIDIV = 0;\r
+ #endif\r
+ SYSTEM.PLLCR.BIT.STC = (PLL_MUL - 1); \r
+\r
+ /* External oscillation input selection */\r
+ SYSTEM.PLLCR2.BYTE = 0x00; /* PLL ON */\r
+#else\r
+ SYSTEM.PLLCR2.BYTE = 0x01; /* PLL OFF */\r
+#endif\r
+ \r
+ for(i = 0; i<2500; i++) /* Wait for stabilisation of */\r
+ { /* HOCO, LOCO, PLL and main clock */\r
+ } /* = 20ms */\r
+ /* (2500 x 1/125kHz = 20ms) */\r
+ \r
+ \r
+ SYSTEM.SCKCR.LONG = FCLK_SCKCR | \r
+ ICLK_SCKCR |\r
+ PSTOP1_SCKCR |\r
+ BCLK_SCKCR |\r
+ PCLK1215_SCKCR |\r
+ PCLKB_SCKCR |\r
+ PCLK47_SCKCR |\r
+ PCLK03_SCKCR ;\r
+ \r
+ \r
+ SYSTEM.SCKCR2.WORD = UCK_SCKCR2 |\r
+ IEBCK_SCKCR2 ; \r
+\r
+\r
+ SYSTEM.SCKCR3.WORD = CLK_SOURCE;\r
+}
\ No newline at end of file
--- /dev/null
+\r
+\r
+/*******************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only \r
+* intended for use with Renesas products. No other uses are authorized. This \r
+* software is owned by Renesas Electronics Corporation and is protected under\r
+* all applicable laws, including copyright laws.\r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING\r
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT\r
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE \r
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.\r
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS \r
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE \r
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR\r
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE\r
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software\r
+* and to discontinue the availability of this software. By using this software,\r
+* you agree to the additional terms and conditions found by accessing the \r
+* following link:\r
+* http://www.renesas.com/disclaimer\r
+*******************************************************************************/\r
+\r
+\r
+/*\r
+ * cgc.h\r
+ *\r
+ * Created on: 01 Oct 2011\r
+ * Author: RJW\r
+ * Reneses Electronics Europe Ltd\r
+ */\r
+ \r
+\r
+#ifndef CGC_H_\r
+#define CGC_H_\r
+\r
+/******************************************************************************\r
+ Function Prototypes\r
+******************************************************************************/\r
+void InitCGC(void);\r
+\r
+\r
+/*****************************************************************************/\r
+/* */\r
+/* Set the CGC (Clock Generation Circuit of the RX630 using the */\r
+/* following 7 STEPS */\r
+/* */\r
+/*****************************************************************************/\r
+\r
+\r
+/*****************************************************************************/\r
+/* */\r
+/* STEP 1: System Clock Options */\r
+/* */\r
+/* Enter one of the CLK_SOURCE_ options into the */\r
+/* */\r
+/* #define CLK_SOURCE ( xxx ) */\r
+/* below. */\r
+/* This will be the clock source that the device will switch to as part of */\r
+/* HardwareSetup() */\r
+/* Extra clocks can be enabled in STEP 3. */\r
+/* */\r
+/* For example */\r
+/* #define CLK_SOURCE (CLK_SOURCE_MAIN) */\r
+/* */\r
+/*****************************************************************************/\r
+#define CLK_SOURCE_LOCO 0x0000\r
+#define CLK_SOURCE_HOCO 0x0100\r
+#define CLK_SOURCE_MAIN 0x0200\r
+#define CLK_SOURCE_SUB 0x0300\r
+#define CLK_SOURCE_PLL 0x0400\r
+\r
+#define CLK_SOURCE (CLK_SOURCE_PLL)\r
+\r
+\r
+/*****************************************************************************/\r
+/* */\r
+/* STEP 2: External XTAL values */\r
+/* */\r
+/* If using the CLK_SOURCE_MAIN, CLK_SOURCE_SUB, CLK_SOURCE_PLL */\r
+/* enter the MAIN XTAL and SUB XTAL values here. */\r
+/* */\r
+/* If using the PLL, enter the PLL multiplier and PLL frequency divder */\r
+/* Use the divider so that the input frequency into the PLL is in */\r
+/* the range of 4 MHz to 16 MHz. */\r
+/* */\r
+/* Use the multiplier so that the output frequency of the PLL is in */\r
+/* the range of 104MHz to 200Mhz */\r
+/* */\r
+/* The PLL frequency divider values are: */\r
+/* /1, /2, /4 */\r
+/* The PLL muliplier values are: */\r
+/* x8, x10, x12, x16, x20, x24, x25, x50 */\r
+/* */\r
+/* Example: */\r
+/* XTAL = 12MHz */\r
+/* PLL Divider = 1 */\r
+/* */\r
+/* Therefore, input into PLL = 12M / 1 */\r
+/* = 12M */\r
+/* PLL Multipler = 16 */\r
+/* */\r
+/* Therefore, ouput of PLL = 12M x 16 */\r
+/* = 192M */\r
+/* */\r
+/* NOTE: The maximum XTAL is 20MHz */\r
+/*****************************************************************************/\r
+#define XTAL_FREQUENCY (12000000L) \r
+#define PLL_MUL (16)\r
+#define PLL_INPUT_FREQ_DIV (1)\r
+\r
+#define SUB_FREQUENCY (32768L) \r
+\r
+\r
+/*****************************************************************************/\r
+/* */\r
+/* STEP 3: Enable the chosen clock source and any extra clock sources */\r
+/* Remeber to enable the clock source chosen in STEP 1. */\r
+/* Foe example, if CLK_SOURCE_PLL has been chosen, set */\r
+/* #define ENABLE_PLL (1) */\r
+/* */\r
+/*****************************************************************************/\r
+#define ENABLE_HOCO (1)\r
+#define ENABLE_SUB (0)\r
+#define ENABLE_MAIN (0)\r
+#define ENABLE_PLL (1)\r
+\r
+\r
+\r
+/*****************************************************************************/\r
+/* */\r
+/* STEP 4: */\r
+/* Enter the Clock Divders for */\r
+/* - FCLK_DIV, ICLK_DIV, BCLK_DIV, PCLKA_DIV, PCLKB_DIV */\r
+/* Valid values are 1, 2, 4, 8, 16, 32 and 64 */\r
+/* */\r
+/* The Clock Value being divided is: */\r
+/* If LOCO, 125kHz */\r
+/* If HOCO, 50MHz */\r
+/* If SUB, the value of SUB specified in STEP 2 */\r
+/* If MAIN, the value of XTAL specified in STEP 2 */\r
+/* If PLL, the result of the XTAL, PLL Div, PLL Mul specified in STEP 2 */\r
+/*****************************************************************************/\r
+#define FCLK_DIV (4)\r
+#define ICLK_DIV (2)\r
+#define BCLK_DIV (4)\r
+#define PCLK1215_DIV (2) /* Do not change this */\r
+#define PCLKB_DIV (4)\r
+#define PCLK47_DIV (2) /* Do not change this */\r
+#define PCLK03_DIV (2) /* Do not change this */\r
+\r
+\r
+/*****************************************************************************/\r
+/* */\r
+/* STEP 5: */\r
+/* Enter the Clock Divder for */\r
+/* - IEBCK_DIV */\r
+/* Valid values are 2, 4, 6, 8, 16, 32 and 64 */\r
+/* */\r
+/* The Clock Value being divided is: */\r
+/* If LOCO, 125kHz */\r
+/* If HOCO, 50MHz */\r
+/* If SUB, the value of SUB specified in STEP 2 */\r
+/* If MAIN, the value of XTAL specified in STEP 2 */\r
+/* If PLL, the result of the XTAL, PLL Div, PLL Mul specified in STEP 2 */\r
+/*****************************************************************************/\r
+#define IEBCK_DIV (2)\r
+\r
+\r
+/*****************************************************************************/\r
+/* */\r
+/* STEP 6: */\r
+/* Enter the Clock Divder for */\r
+/* - UCK_DIV */\r
+/* Valid values are 3, 4 */\r
+/* */\r
+/* The Clock Value being divided is: */\r
+/* If LOCO, 125kHz */\r
+/* If HOCO, 50MHz */\r
+/* If SUB, the value of SUB specified in STEP 2 */\r
+/* If MAIN, the value of XTAL specified in STEP 2 */\r
+/* If PLL, the result of the XTAL, PLL Div, PLL Mul specified in STEP 2 */\r
+/*****************************************************************************/\r
+#define UCK_DIV (3)\r
+\r
+\r
+/*****************************************************************************/\r
+/* */\r
+/* STEP 7: */\r
+/* Specify the use of BCLK pin */\r
+/* To ENABLE, set to (0) */\r
+/* To DISABLE, set to (1) */\r
+/* */\r
+/*****************************************************************************/\r
+#define BCLK_PIN (1)\r
+\r
+\r
+/*****************************************************************************/\r
+/* Clock configuration is now complete. */\r
+/*****************************************************************************/\r
+#include "cgc_set.h"\r
+#include "cgc_error.h"\r
+\r
+#endif
\ No newline at end of file
--- /dev/null
+#ifndef CGC_ERROR_H_\r
+#define CGC_ERROR_H_\r
+\r
+/* Error checking macros for the clock selction and clock enable defines */\r
+\r
+#if ( (CLK_SOURCE != CLK_SOURCE_LOCO) && \\r
+ (CLK_SOURCE != CLK_SOURCE_HOCO) && \\r
+ (CLK_SOURCE != CLK_SOURCE_MAIN) && \\r
+ (CLK_SOURCE != CLK_SOURCE_SUB) && \\r
+ (CLK_SOURCE != CLK_SOURCE_PLL) )\r
+ #error "No CLK_SOURCE specified. Please specify a valid CLK_SOURCE";\r
+#endif\r
+ \r
+\r
+#if (CLK_SOURCE == CLK_SOURCE_HOCO) && (ENABLE_HOCO == 0)\r
+ #error "HOCO has been specified as the CLK_SOURCE but ENABLE_HOCO is (0). Please set to (1) in file cgc.h"\r
+#endif\r
+\r
+#if (CLK_SOURCE == CLK_SOURCE_MAIN) && (ENABLE_MAIN == 0)\r
+ #error "HOCO has been specified as the CLK_SOURCE but ENABLE_HOCO is (0). Please set to (1) in file cgc.h"\r
+#endif\r
+\r
+#if (CLK_SOURCE == CLK_SOURCE_SUB) && (ENABLE_SUB == 0)\r
+ #error "HOCO has been specified as the CLK_SOURCE but ENABLE_HOCO is (0). Please set to (1) in file cgc.h"\r
+#endif\r
+\r
+#if (CLK_SOURCE == CLK_SOURCE_PLL) && (ENABLE_PLL == 0)\r
+ #error "PLL has been specified as the CLK_SOURCE but ENABLE_PLL is (0). Please set to (1) in file cgc.h"\r
+#endif\r
+\r
+#if ( FCLK_FREQUENCY > 50000000L )\r
+ #error "FCLK_FREQUENCY Error: Please enter a valid divider value"\r
+#endif\r
+\r
+#if ( ICLK_FREQUENCY > 100000000L )\r
+ #error "ICLK_FREQUENCY Error: Please enter a valid divider value"\r
+#endif\r
+\r
+#if ( BCLK_FREQUENCY > 100000000L )\r
+ #error "BCLK_FREQUENCY Error: Please enter a valid divider value"\r
+#endif\r
+ \r
+#if ( PCLKB_FREQUENCY > 50000000L ) \r
+ #error "PCLKB_FREQUENCY Error: Please enter a valid divider value"\r
+#endif\r
+ \r
+#endif
\ No newline at end of file
--- /dev/null
+#ifndef CGC_SET_VALUES_H_\r
+#define CGC_SET_VALUES_H_\r
+\r
+/* Do not modify these macros. These values are used to initialise \r
+ the SCKCR and SCKCR2 registers based upon the above values. */\r
+#if (FCLK_DIV == 64)\r
+ #define FCLK_SCKCR 0x60000000L\r
+#elif (FCLK_DIV == 32)\r
+ #define FCLK_SCKCR 0x50000000L\r
+#elif (FCLK_DIV == 16)\r
+ #define FCLK_SCKCR 0x40000000L\r
+#elif (FCLK_DIV == 8)\r
+ #define FCLK_SCKCR 0x30000000L\r
+#elif (FCLK_DIV == 4)\r
+ #define FCLK_SCKCR 0x20000000L\r
+#elif (FCLK_DIV == 2)\r
+ #define FCLK_SCKCR 0x10000000L\r
+#elif(FCLK_DIV == 1)\r
+ #define FCLK_SCKCR 0x00000000L\r
+#else\r
+ #define FCLK_SCKCR 0x10000000L\r
+#endif\r
+\r
+\r
+#if (ICLK_DIV == 64)\r
+ #define ICLK_SCKCR 0x06000000L\r
+#elif (ICLK_DIV == 32)\r
+ #define ICLK_SCKCR 0x05000000L\r
+#elif (ICLK_DIV == 16)\r
+ #define ICLK_SCKCR 0x04000000L\r
+#elif (ICLK_DIV == 8)\r
+ #define ICLK_SCKCR 0x03000000L\r
+#elif (ICLK_DIV == 4)\r
+ #define ICLK_SCKCR 0x02000000L\r
+#elif (ICLK_DIV == 2)\r
+ #define ICLK_SCKCR 0x01000000L\r
+#elif (ICLK_DIV == 1)\r
+ #define ICLK_SCKCR 0x00000000L\r
+#else\r
+ #define ICLK_SCKCR 0x01000000L\r
+#endif\r
+\r
+ \r
+#if (BCLK_PIN == 1)\r
+ #define PSTOP1_SCKCR 0x00800000L\r
+#elif \r
+ #define PSTOP1_SCKCR 0x00000000L\r
+#endif \r
+\r
+\r
+#if (BCLK_DIV == 64)\r
+ #define BCLK_SCKCR 0x00060000L\r
+#elif (BCLK_DIV == 32)\r
+ #define BCLK_SCKCR 0x00050000L\r
+#elif (BCLK_DIV == 16)\r
+ #define BCLK_SCKCR 0x00040000L\r
+#elif (BCLK_DIV == 8)\r
+ #define BCLK_SCKCR 0x00030000L\r
+#elif (BCLK_DIV == 4)\r
+ #define BCLK_SCKCR 0x00020000L\r
+#elif (BCLK_DIV == 2)\r
+ #define BCLK_SCKCR 0x00010000L\r
+#elif (BCLK_DIV == 1)\r
+ #define BCLK_SCKCR 0x00000000L\r
+#else\r
+ #define BCLK_SCKCR 0x00010000L\r
+#endif\r
+\r
+\r
+#if (PCLK1215_DIV == 64)\r
+ #define PCLK1215_SCKCR 0x00006000L\r
+#elif (PCLK1215_DIV == 32)\r
+ #define PCLK1215_SCKCR 0x00005000L\r
+#elif (PCLK1215_DIV == 16)\r
+ #define PCLK1215_SCKCR 0x00004000L\r
+#elif (PCLK1215_DIV == 8)\r
+ #define PCLK1215_SCKCR 0x00003000L\r
+#elif (PCLK1215_DIV == 4)\r
+ #define PCLK1215_SCKCR 0x00002000L\r
+#elif (PCLK1215_DIV == 2)\r
+ #define PCLK1215_SCKCR 0x00001000L\r
+#elif (PCLK1215_DIV == 1)\r
+ #define PCLK1215_SCKCR 0x00000000L\r
+#else\r
+ #define PCLK1215_SCKCR 0x00001000L\r
+#endif\r
+\r
+\r
+#if (PCLKB_DIV == 64)\r
+ #define PCLKB_SCKCR 0x00000600L\r
+#elif (PCLKB_DIV == 32)\r
+ #define PCLKB_SCKCR 0x00000500L\r
+#elif (PCLKB_DIV == 16)\r
+ #define PCLKB_SCKCR 0x00000400L\r
+#elif (PCLKB_DIV == 8)\r
+ #define PCLKB_SCKCR 0x00000300L\r
+#elif (PCLKB_DIV == 4)\r
+ #define PCLKB_SCKCR 0x00000200L\r
+#elif (PCLKB_DIV == 2)\r
+ #define PCLKB_SCKCR 0x00000100L\r
+#elif (PCLKB_DIV == 1)\r
+ #define PCLKB_SCKCR 0x00000000L\r
+#else\r
+ #define PCLKB_SCKCR 0x00000100L\r
+#endif\r
+\r
+\r
+#if (PCLK47_DIV == 64)\r
+ #define PCLK47_SCKCR 0x00000060L\r
+#elif (PCLK47_DIV == 32)\r
+ #define PCLK47_SCKCR 0x00000050L\r
+#elif (PCLK47_DIV == 16)\r
+ #define PCLK47_SCKCR 0x00000040L\r
+#elif (PCLK47_DIV == 8)\r
+ #define PCLK47_SCKCR 0x00000030L\r
+#elif (PCLK47_DIV == 4)\r
+ #define PCLK47_SCKCR 0x00000020L\r
+#elif (PCLK47_DIV == 2)\r
+ #define PCLK47_SCKCR 0x00000010L\r
+#elif (PCLK47_DIV == 1)\r
+ #define PCLK47_SCKCR 0x00000000L\r
+#else\r
+ #define PCLK47_SCKCR 0x00000010L \r
+#endif\r
+\r
+\r
+#if (PCLK03_DIV == 64)\r
+ #define PCLK03_SCKCR 0x00000006L\r
+#elif (PCLK03_DIV == 32)\r
+ #define PCLK03_SCKCR 0x00000005L\r
+#elif (PCLK03_DIV == 16)\r
+ #define PCLK03_SCKCR 0x00000004L\r
+#elif (PCLK03_DIV == 8)\r
+ #define PCLK03_SCKCR 0x00000003L\r
+#elif (PCLK03_DIV == 4)\r
+ #define PCLK03_SCKCR 0x00000002L\r
+#elif (PCLK03_DIV == 2)\r
+ #define PCLK03_SCKCR 0x00000001L\r
+#elif (PCLK03_DIV == 1)\r
+ #define PCLK03_SCKCR 0x00000000L\r
+#else\r
+ #define PCLK03_SCKCR 0x00000001L \r
+#endif\r
+\r
+\r
+#if (UCK_DIV == 6)\r
+ #define UCK_SCKCR2 0x00C0L\r
+#elif (UCK_DIV == 64)\r
+ #define UCK_SCKCR2 0x0060L\r
+#elif (UCK_DIV == 32)\r
+ #define UCK_SCKCR2 0x0050L\r
+#elif (UCK_DIV == 16)\r
+ #define UCK_SCKCR2 0x0040L\r
+#elif (UCK_DIV == 8)\r
+ #define UCK_SCKCR2 0x0030L\r
+#elif (UCK_DIV == 4)\r
+ #define UCK_SCKCR2 0x0020L\r
+#elif (UCK_DIV == 2)\r
+ #define UCK_SCKCR2 0x0010L\r
+#else\r
+ #define UCK_SCKCR2 0x0010L\r
+#endif\r
+\r
+\r
+#if (IEBCK_DIV == 3)\r
+ #define IEBCK_SCKCR2 0x00000020L\r
+#elif (IEBCK_DIV == 4)\r
+ #define IEBCK_SCKCR2 0x00000030L\r
+#else\r
+ #define IEBCK_SCKCR2 0x00000030L\r
+#endif\r
+\r
+\r
+#if (CLK_SOURCE == CLK_SOURCE_LOCO)\r
+/* Internal LOCO circuit - 125kHz*/\r
+#define CLK_FREQUENCY (125000L) \r
+#define FCLK_FREQUENCY (CLK_FREQUENCY / FCLK_DIV)\r
+#define ICLK_FREQUENCY (CLK_FREQUENCY / ICLK_DIV)\r
+#define BCLK_FREQUENCY (CLK_FREQUENCY / BCLK_DIV)\r
+#define PCLKA_FREQUENCY (CLK_FREQUENCY / PCLK1215_DIV)\r
+#define PCLKB_FREQUENCY (CLK_FREQUENCY / PCLKB_DIV)\r
+#define PCLK47_FREQUENCY (CLK_FREQUENCY / PCLK47_DIV)\r
+#define PCLK03_FREQUENCY (CLK_FREQUENCY / PCLK03_DIV)\r
+\r
+\r
+#elif (CLK_SOURCE == CLK_SOURCE_HOCO)\r
+/* Internal high speed on-chip oscillator (HOCO) */\r
+#define CLK_FREQUENCY (50000000L) \r
+#define FCLK_FREQUENCY (CLK_FREQUENCY / FCLK_DIV)\r
+#define ICLK_FREQUENCY (CLK_FREQUENCY / ICLK_DIV)\r
+#define BCLK_FREQUENCY (CLK_FREQUENCY / BCLK_DIV)\r
+#define PCLKA_FREQUENCY (CLK_FREQUENCY / PCLK1215_DIV)\r
+#define PCLKB_FREQUENCY (CLK_FREQUENCY / PCLKB_DIV)\r
+#define PCLK47_FREQUENCY (CLK_FREQUENCY / PCLK47_DIV)\r
+#define PCLK03_FREQUENCY (CLK_FREQUENCY / PCLK03_DIV)\r
+\r
+\r
+#elif (CLK_SOURCE == CLK_SOURCE_MAIN)\r
+/* External XTAL, but not via the PLL circuit */ \r
+#define FCLK_FREQUENCY (XTAL_FREQUENCY / FCLK_DIV)\r
+#define ICLK_FREQUENCY (XTAL_FREQUENCY / ICLK_DIV)\r
+#define BCLK_FREQUENCY (XTAL_FREQUENCY / BCLK_DIV)\r
+#define PCLKA_FREQUENCY (XTAL_FREQUENCY / PCLK1215_DIV)\r
+#define PCLKB_FREQUENCY (XTAL_FREQUENCY / PCLKB_DIV)\r
+#define PCLK47_FREQUENCY (XTAL_FREQUENCY / PCLK47_DIV)\r
+#define PCLK03_FREQUENCY (XTAL_FREQUENCY / PCLK03_DIV)\r
+\r
+\r
+#elif (CLK_SOURCE == CLK_SOURCE_SUB)\r
+/* External 32khZ XTAL */ \r
+#define FCLK_FREQUENCY (SUB_FREQUENCY / FCLK_DIV)\r
+#define ICLK_FREQUENCY (SUB_FREQUENCY / ICLK_DIV)\r
+#define BCLK_FREQUENCY (SUB_FREQUENCY / BCLK_DIV)\r
+#define PCLKA_FREQUENCY (SUB_FREQUENCY / PCLK1215_DIV)\r
+#define PCLKB_FREQUENCY (SUB_FREQUENCY / PCLKB_DIV)\r
+#define PCLK47_FREQUENCY (SUB_FREQUENCY / PCLK47_DIV)\r
+#define PCLK03_FREQUENCY (SUB_FREQUENCY / PCLK03_DIV)\r
+\r
+\r
+#elif (CLK_SOURCE == CLK_SOURCE_PLL)\r
+/* External XTAL, but using the PLL circuit */\r
+#define PLL_FREQUENCY (XTAL_FREQUENCY * (PLL_MUL / PLL_INPUT_FREQ_DIV)) \r
+#define FCLK_FREQUENCY (PLL_FREQUENCY / FCLK_DIV)\r
+#define ICLK_FREQUENCY (PLL_FREQUENCY / ICLK_DIV)\r
+#define BCLK_FREQUENCY (PLL_FREQUENCY / BCLK_DIV)\r
+#define PCLKA_FREQUENCY (PLL_FREQUENCY / PCLK1215_DIV)\r
+#define PCLKB_FREQUENCY (PLL_FREQUENCY / PCLKB_DIV)\r
+#define PCLK47_FREQUENCY (PLL_FREQUENCY / PCLK47_DIV)\r
+#define PCLK03_FREQUENCY (PLL_FREQUENCY / PCLK03_DIV)\r
+\r
+#endif\r
+\r
+#endif
\ No newline at end of file
--- /dev/null
+/***********************************************************************/\r
+/* */\r
+/* FILE :dbsct.c */\r
+/* DATE :Wed, Aug 11, 2010 */\r
+/* DESCRIPTION :Setting of B,R Section */\r
+/* CPU TYPE :Other */\r
+/* */\r
+/* This file is generated by Renesas Project Generator (Ver.4.50). */\r
+/* NOTE:THIS IS A TYPICAL EXAMPLE. */\r
+/* */\r
+/***********************************************************************/\r
+ \r
+\r
+/*********************************************************************\r
+*\r
+* Device : RX\r
+*\r
+* File Name : dbsct.c\r
+*\r
+* Abstract : Setting of B,R Section.\r
+*\r
+* History : 1.00 (2009-08-07)\r
+*\r
+* NOTE : THIS IS A TYPICAL EXAMPLE.\r
+*\r
+* Copyright(c) 2009 Renesas Technology Corp.\r
+* And Renesas Solutions Corp.,All Rights Reserved. \r
+*\r
+*********************************************************************/\r
+\r
+#include "typedefine.h"\r
+\r
+#pragma unpack\r
+\r
+#pragma section C C$DSEC\r
+extern const struct {\r
+ _UBYTE *rom_s; /* Start address of the initialized data section in ROM */\r
+ _UBYTE *rom_e; /* End address of the initialized data section in ROM */\r
+ _UBYTE *ram_s; /* Start address of the initialized data section in RAM */\r
+} _DTBL[] = {\r
+ { __sectop("D"), __secend("D"), __sectop("R") },\r
+ { __sectop("D_2"), __secend("D_2"), __sectop("R_2") },\r
+ { __sectop("D_1"), __secend("D_1"), __sectop("R_1") }\r
+};\r
+#pragma section C C$BSEC\r
+extern const struct {\r
+ _UBYTE *b_s; /* Start address of non-initialized data section */\r
+ _UBYTE *b_e; /* End address of non-initialized data section */\r
+} _BTBL[] = {\r
+ { __sectop("B"), __secend("B") },\r
+ { __sectop("B_2"), __secend("B_2") },\r
+ { __sectop("B_1"), __secend("B_1") }\r
+};\r
+\r
+#pragma section\r
+\r
+/*\r
+** CTBL prevents excessive output of L1100 messages when linking.\r
+** Even if CTBL is deleted, the operation of the program does not change.\r
+*/\r
+_UBYTE * const _CTBL[] = {\r
+ __sectop("C_1"), __sectop("C_2"), __sectop("C"),\r
+ __sectop("W_1"), __sectop("W_2"), __sectop("W")\r
+};\r
+\r
+#pragma packoption\r
--- /dev/null
+/******************************************************************************\r
+* DISCLAIMER\r
+\r
+* This software is supplied by Renesas Technology Corp. and is only \r
+* intended for use with Renesas products. No other uses are authorized.\r
+\r
+* This software is owned by Renesas Technology Corp. and is protected under \r
+* all applicable laws, including copyright laws.\r
+\r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES\r
+* REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, \r
+* INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A \r
+* PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY \r
+* DISCLAIMED.\r
+\r
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS \r
+* TECHNOLOGY CORP. NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE \r
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES \r
+* FOR ANY REASON RELATED TO THE THIS SOFTWARE, EVEN IF RENESAS OR ITS \r
+* AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+\r
+* Renesas reserves the right, without notice, to make changes to this \r
+* software and to discontinue the availability of this software. \r
+* By using this software, you agree to the additional terms and \r
+* conditions found by accessing the following link:\r
+* http://www.renesas.com/disclaimer\r
+******************************************************************************\r
+* Copyright (C) 2008. Renesas Technology Corp., All Rights Reserved.\r
+******************************************************************************* \r
+* File Name : hwsetup.c\r
+* Version : 1.00\r
+* Description : Power up hardware initializations\r
+******************************************************************************\r
+* History : DD.MM.YYYY Version Description\r
+* : 15.02.2010 1.00 First Release\r
+******************************************************************************/\r
+\r
+\r
+/******************************************************************************\r
+Includes <System Includes> , "Project Includes"\r
+******************************************************************************/\r
+#include <stdint.h>\r
+#include "iodefine.h"\r
+#include "cgc.h"\r
+#include "rskrx630def.h"\r
+\r
+/******************************************************************************\r
+Typedef definitions\r
+******************************************************************************/\r
+\r
+/******************************************************************************\r
+Macro definitions\r
+******************************************************************************/\r
+\r
+/******************************************************************************\r
+Imported global variables and functions (from other files)\r
+******************************************************************************/\r
+\r
+/******************************************************************************\r
+Exported global variables and functions (to be accessed by other files)\r
+******************************************************************************/\r
+\r
+/******************************************************************************\r
+Private global variables and functions\r
+******************************************************************************/\r
+void io_set_cpg(void);\r
+void ConfigurePortPins(void);\r
+void EnablePeripheralModules(void);\r
+\r
+/******************************************************************************\r
+* Function Name: HardwareSetup\r
+* Description : This function does initial setting for CPG port pins used in\r
+* : the Demo including the MII pins of the Ethernet PHY connection.\r
+* Arguments : none\r
+* Return Value : none\r
+******************************************************************************/\r
+void HardwareSetup(void)\r
+{\r
+ /* Gain access to the System control registers */\r
+ /* Refer to section 13 of the Hardware User Manual for further details */\r
+ SYSTEM.PRCR.WORD = 0xA503;\r
+ \r
+ /* Gain access to the Port Function Select Registers */\r
+ /* Refer to section 21 of the Hardware User Manual for further details */\r
+ MPC.PWPR.BIT.B0WI = 0;\r
+ MPC.PWPR.BIT.PFSWE = 1;\r
+ \r
+ /* CPG setting */\r
+ /* User defined values for XTAL, Clock Divders etc are set in cgc.h */\r
+ InitCGC();\r
+\r
+ /* Setup the port pins */\r
+ ConfigurePortPins();\r
+\r
+ /* Enables peripherals */\r
+ EnablePeripheralModules();\r
+\r
+#if INCLUDE_LCD == 1\r
+ /* Initialize display */\r
+ InitialiseDisplay();\r
+#endif\r
+}\r
+\r
+/******************************************************************************\r
+* Function Name: EnablePeripheralModules\r
+* Description : Enables Peripheral Modules before use\r
+* Arguments : none\r
+* Return Value : none\r
+******************************************************************************/\r
+void EnablePeripheralModules(void)\r
+{\r
+ /* Module standby clear */\r
+ SYSTEM.MSTPCRA.BIT.MSTPA15 = 0; /* CMT0 */\r
+}\r
+\r
+/******************************************************************************\r
+* Function Name: ConfigurePortPins\r
+* Description : Configures port pins.\r
+* Arguments : none\r
+* Return Value : none\r
+******************************************************************************/\r
+void ConfigurePortPins(void)\r
+{\r
+/* Port pins default to inputs. To ensure safe initialisation set the pin states\r
+before changing the data direction registers. This will avoid any unintentional\r
+state changes on the external ports.\r
+Many peripheral modules will override the setting of the port registers. Ensure\r
+that the state is safe for external devices if the internal peripheral module is\r
+disabled or powered down. */\r
+\r
+ /* Set initial LED pin state to off */\r
+ LED0 = 1; \r
+ LED1 = 1;\r
+ LED2 = 1;\r
+ LED3 = 1;\r
+ /* Configure LED 0-3 pin settings */\r
+ LED0_PDR = 1; \r
+ LED1_PDR = 1;\r
+ LED2_PDR = 1;\r
+ LED3_PDR = 1;\r
+\r
+ /* Configure SW 1-3 pin settings */\r
+ /* No need to configure inputs as they are inputs by default */\r
+\r
+#if INCLUDE_LCD == 1\r
+ /* Set LCD pins as outputs */\r
+ /* LCD-RS */\r
+ LCD_RS_PDR = 1;\r
+ /* LCD-EN */\r
+ LCD_EN = 1;\r
+ /*LCD-data */\r
+ LCD_DATA_PDR = 0xF0;\r
+#endif\r
+}\r
--- /dev/null
+/***********************************************************************/\r
+/* */\r
+/* FILE :intprg.c */\r
+/* DATE :Wed, Aug 11, 2010 */\r
+/* DESCRIPTION :Interrupt Program */\r
+/* CPU TYPE :Other */\r
+/* */\r
+/* This file is generated by Renesas Project Generator (Ver.4.50). */\r
+/* NOTE:THIS IS A TYPICAL EXAMPLE. */\r
+/* */\r
+/***********************************************************************/\r
+ \r
+\r
+\r
+/*********************************************************************\r
+*\r
+* Device : RX/RX600\r
+*\r
+* File Name : intprg.c\r
+*\r
+* Abstract : Interrupt Program.\r
+*\r
+* History : 1.00 (2009-08-07)\r
+*\r
+* NOTE : THIS IS A TYPICAL EXAMPLE.\r
+*\r
+* Copyright(c) 2009 Renesas Technology Corp.\r
+* And Renesas Solutions Corp.,All Rights Reserved. \r
+*\r
+*********************************************************************/\r
+\r
+#include <machine.h>\r
+#include "vect.h"\r
+#pragma section IntPRG\r
+\r
+// Exception(Supervisor Instruction)\r
+void Excep_SuperVisorInst(void){/* brk(); */}\r
+\r
+// Exception(Undefined Instruction)\r
+void Excep_UndefinedInst(void){/* brk(); */}\r
+\r
+// Exception(Floating Point)\r
+void Excep_FloatingPoint(void){/* brk(); */}\r
+\r
+// NMI\r
+void NonMaskableInterrupt(void){/* brk(); */}\r
+\r
+// Dummy\r
+void Dummy(void){/* brk(); */}\r
+\r
+// BRK\r
+void Excep_BRK(void){ wait(); }\r
+\r
--- /dev/null
+\r
+; Comment out the orginal code\r
+ .IF 0 \r
+\r
+;------------------------------------------------------------------------\r
+; |\r
+; FILE :lowlvl.src |\r
+; DATE :Wed, Jun 16, 2010 |\r
+; DESCRIPTION :Program of Low level |\r
+; CPU TYPE :Other |\r
+; |\r
+; This file is generated by Renesas Project Generator (Ver.4.50). |\r
+; NOTE:THIS IS A TYPICAL EXAMPLE. |\r
+; |\r
+;------------------------------------------------------------------------\r
+ \r
+\r
+ .GLB _charput\r
+ .GLB _charget\r
+\r
+SIM_IO .EQU 0h\r
+\r
+ .SECTION P,CODE\r
+;-----------------------------------------------------------------------\r
+; _charput:\r
+;-----------------------------------------------------------------------\r
+_charput:\r
+ MOV.L #IO_BUF,R2\r
+ MOV.B R1,[R2]\r
+ MOV.L #1220000h,R1\r
+ MOV.L #PARM,R3\r
+ MOV.L R2,[R3]\r
+ MOV.L R3,R2\r
+ MOV.L #SIM_IO,R3\r
+ JSR R3\r
+ RTS\r
+\r
+;-----------------------------------------------------------------------\r
+; _charget:\r
+;----------------------------------------------------------------------- \r
+_charget:\r
+ MOV.L #1210000h,R1\r
+ MOV.L #IO_BUF,R2\r
+ MOV.L #PARM,R3\r
+ MOV.L R2,[R3]\r
+ MOV.L R3,R2\r
+ MOV.L #SIM_IO,R3\r
+ JSR R3\r
+ MOV.L #IO_BUF,R2\r
+ MOVU.B [R2],R1\r
+ RTS\r
+\r
+;-----------------------------------------------------------------------\r
+; I/O Buffer\r
+;-----------------------------------------------------------------------\r
+ .SECTION B,DATA,ALIGN=4\r
+PARM: .BLKL 1\r
+ .SECTION B_1,DATA\r
+IO_BUF: .BLKB 1\r
+; .END ; Commented out for conditional assembly\r
+\r
+; Code below is for debug console\r
+ .ELSE \r
+\r
+;-----------------------------------------------------------------------\r
+;\r
+; FILE :lowlvl.src\r
+; DATE :Wed, Jul 01, 2009\r
+; DESCRIPTION :Program of Low level\r
+; CPU TYPE :RX\r
+;\r
+;-----------------------------------------------------------------------\r
+ .GLB _charput\r
+ .GLB _charget\r
+\r
+FC2E0 .EQU 00084080h\r
+FE2C0 .EQU 00084090h\r
+DBGSTAT .EQU 000840C0h\r
+RXFL0EN .EQU 00001000h\r
+TXFL0EN .EQU 00000100h\r
+\r
+ .SECTION P,CODE\r
+\r
+;-----------------------------------------------------------------------\r
+; _charput:\r
+;-----------------------------------------------------------------------\r
+_charput:\r
+ .STACK _charput = 00000000h\r
+__C2ESTART: MOV.L #TXFL0EN,R3\r
+ MOV.L #DBGSTAT,R4\r
+__TXLOOP: MOV.L [R4],R5\r
+ AND R3,R5\r
+ BNZ __TXLOOP\r
+__WRITEFC2E0: MOV.L #FC2E0,R2\r
+ MOV.L R1,[R2]\r
+__CHARPUTEXIT: RTS\r
+\r
+;-----------------------------------------------------------------------\r
+; _charget:\r
+;-----------------------------------------------------------------------\r
+_charget:\r
+ .STACK _charget = 00000000h\r
+__E2CSTART: MOV.L #RXFL0EN,R3\r
+ MOV.L #DBGSTAT,R4\r
+__RXLOOP: MOV.L [R4],R5\r
+ AND R3,R5\r
+ BZ __RXLOOP\r
+__READFE2C0: MOV.L #FE2C0,R2\r
+ MOV.L [R2],R1\r
+__CHARGETEXIT: RTS\r
+\r
+;-----------------------------------------------------------------------\r
+\r
+; End of conditional code\r
+ .ENDIF \r
+\r
+ .END\r
+\r
+\r
+\r
--- /dev/null
+/***********************************************************************/\r
+/* */\r
+/* FILE :lowsrc.c */\r
+/* DATE :Wed, Jun 16, 2010 */\r
+/* DESCRIPTION :Program of I/O Stream */\r
+/* CPU TYPE :Other */\r
+/* */\r
+/* This file is generated by Renesas Project Generator (Ver.4.50). */\r
+/* NOTE:THIS IS A TYPICAL EXAMPLE. */\r
+/* */\r
+/***********************************************************************/\r
+ \r
+\r
+\r
+/*********************************************************************\r
+*\r
+* Device : RX\r
+*\r
+* File Name : lowsrc.c\r
+*\r
+* Abstract : Program of I/O Stream.\r
+*\r
+* History : 1.00 (2009-08-07)\r
+*\r
+* NOTE : THIS IS A TYPICAL EXAMPLE.\r
+*\r
+* Copyright(c) 2009 Renesas Technology Corp.\r
+* And Renesas Solutions Corp.,All Rights Reserved. \r
+*\r
+*********************************************************************/\r
+\r
+#include <string.h>\r
+#include <stdio.h>\r
+#include <stddef.h>\r
+#include "lowsrc.h"\r
+\r
+/* file number */\r
+#define STDIN 0 /* Standard input (console) */\r
+#define STDOUT 1 /* Standard output (console) */\r
+#define STDERR 2 /* Standard error output (console) */\r
+\r
+#define FLMIN 0 /* Minimum file number */\r
+#define _MOPENR 0x1\r
+#define _MOPENW 0x2\r
+#define _MOPENA 0x4\r
+#define _MTRUNC 0x8\r
+#define _MCREAT 0x10\r
+#define _MBIN 0x20\r
+#define _MEXCL 0x40\r
+#define _MALBUF 0x40\r
+#define _MALFIL 0x80\r
+#define _MEOF 0x100\r
+#define _MERR 0x200\r
+#define _MLBF 0x400\r
+#define _MNBF 0x800\r
+#define _MREAD 0x1000\r
+#define _MWRITE 0x2000\r
+#define _MBYTE 0x4000\r
+#define _MWIDE 0x8000\r
+/* File Flags */\r
+#define O_RDONLY 0x0001 /* Read only */\r
+#define O_WRONLY 0x0002 /* Write only */\r
+#define O_RDWR 0x0004 /* Both read and Write */\r
+#define O_CREAT 0x0008 /* A file is created if it is not existed */\r
+#define O_TRUNC 0x0010 /* The file size is changed to 0 if it is existed. */\r
+#define O_APPEND 0x0020 /* The position is set for next reading/writing */\r
+ /* 0: Top of the file 1: End of file */\r
+\r
+/* Special character code */\r
+#define CR 0x0d /* Carriage return */\r
+#define LF 0x0a /* Line feed */\r
+\r
+#if defined( __RX )\r
+const long _nfiles = IOSTREAM; /* The number of files for input/output files */\r
+#else\r
+const int _nfiles = IOSTREAM; /* The number of files for input/output files */\r
+#endif\r
+char flmod[IOSTREAM]; /* The location for the mode of opened file. */\r
+\r
+unsigned char sml_buf[IOSTREAM];\r
+\r
+#define FPATH_STDIN "C:\\stdin"\r
+#define FPATH_STDOUT "C:\\stdout"\r
+#define FPATH_STDERR "C:\\stderr"\r
+\r
+/* H8 Normal mode ,SH and RX */\r
+#if defined( __2000N__ ) || defined( __2600N__ ) || defined( __300HN__ ) || defined( _SH )\r
+/* Output one character to standard output */\r
+extern void charput(char);\r
+/* Input one character from standard input */\r
+extern char charget(void);\r
+/* Output one character to the file */\r
+extern char fcharput(char, unsigned char);\r
+/* Input one character from the file */\r
+extern char fcharget(char*, unsigned char);\r
+/* Open the file */\r
+extern char fileopen(char*, unsigned char, unsigned char*);\r
+/* Close the file */\r
+extern char fileclose(unsigned char);\r
+/* Move the file offset */\r
+extern char fpseek(unsigned char, long, unsigned char);\r
+/* Get the file offset */\r
+extern char fptell(unsigned char, long*);\r
+\r
+/* RX */\r
+#elif defined( __RX )\r
+/* Output one character to standard output */\r
+extern void charput(unsigned char);\r
+/* Input one character from standard input */\r
+extern unsigned char charget(void);\r
+\r
+/* H8 Advanced mode */\r
+#elif defined( __2000A__ ) || defined( __2600A__ ) || defined( __300HA__ ) || defined( __H8SXN__ ) || defined( __H8SXA__ ) || defined( __H8SXM__ ) || defined( __H8SXX__ )\r
+/* Output one character to standard output */\r
+extern void charput(char);\r
+/* Input one character from standard input */\r
+extern char charget(void);\r
+/* Output one character to the file */\r
+extern char fcharput(char, unsigned char);\r
+/* Input one character from the file */\r
+extern char fcharget(char*, unsigned char);\r
+/* Open the file */\r
+/* Specified as the number of register which stored paramter is 3 */\r
+extern char __regparam3 fileopen(char*, unsigned char, unsigned char*);\r
+/* Close the file */\r
+extern char fileclose(unsigned char);\r
+/* Move the file offset */\r
+extern char fpseek(unsigned char, long, unsigned char);\r
+/* Get the file offset */\r
+extern char fptell(unsigned char, long*);\r
+\r
+/* H8300 and H8300L */\r
+#elif defined( __300__ ) || defined( __300L__ )\r
+/* Output one character to standard output */\r
+extern void charput(char);\r
+/* Input one character from standard input */\r
+extern char charget(void);\r
+/* Output one character to the file */\r
+extern char fcharput(char, unsigned char);\r
+/* Input one character from the file */\r
+extern char fcharget(char*, unsigned char);\r
+/* Open the file */\r
+/* Specified as the number of register which stored paramter is 3 */\r
+extern char __regparam3 fileopen(char*, unsigned char, unsigned char*);\r
+/* Close the file */\r
+extern char fileclose(unsigned char);\r
+/* Move the file offset */\r
+/* Move the file offset */\r
+extern char __regparam3 fpseek(unsigned char, long, unsigned char);\r
+/* Get the file offset */\r
+extern char fptell(unsigned char, long*);\r
+#endif\r
+\r
+#include <stdio.h>\r
+FILE *_Files[IOSTREAM]; // structure for FILE\r
+char *env_list[] = { // Array for environment variables(**environ)\r
+ "ENV1=temp01",\r
+ "ENV2=temp02",\r
+ "ENV9=end",\r
+ '\0' // Terminal for environment variables\r
+};\r
+\r
+char **environ = env_list;\r
+\r
+/****************************************************************************/\r
+/* _INIT_IOLIB */\r
+/* Initialize C library Functions, if necessary. */\r
+/* Define USES_SIMIO on Assembler Option. */\r
+/****************************************************************************/\r
+void _INIT_IOLIB( void )\r
+{\r
+ /* A file for standard input/output is opened or created. Each FILE */\r
+ /* structure members are initialized by the library. Each _Buf member */\r
+ /* in it is re-set the end of buffer pointer. */\r
+\r
+ /* Standard Input File */\r
+ if( freopen( FPATH_STDIN, "r", stdin ) == NULL )\r
+ stdin->_Mode = 0xffff; /* Not allow the access if it fails to open */\r
+ stdin->_Mode = _MOPENR; /* Read only attribute */\r
+ stdin->_Mode |= _MNBF; /* Non-buffering for data */\r
+ stdin->_Bend = stdin->_Buf + 1; /* Re-set pointer to the end of buffer */\r
+\r
+ /* Standard Output File */\r
+ if( freopen( FPATH_STDOUT, "w", stdout ) == NULL ) \r
+ stdout->_Mode = 0xffff; /* Not allow the access if it fails to open */\r
+ stdout->_Mode |= _MNBF; /* Non-buffering for data */\r
+ stdout->_Bend = stdout->_Buf + 1;/* Re-set pointer to the end of buffer */\r
+ \r
+ /* Standard Error File */\r
+ if( freopen( FPATH_STDERR, "w", stderr ) == NULL )\r
+ stderr->_Mode = 0xffff; /* Not allow the access if it fails to open */\r
+ stderr->_Mode |= _MNBF; /* Non-buffering for data */\r
+ stderr->_Bend = stderr->_Buf + 1;/* Re-set pointer to the end of buffer */\r
+}\r
+\r
+/****************************************************************************/\r
+/* _CLOSEALL */\r
+/****************************************************************************/\r
+void _CLOSEALL( void )\r
+{\r
+ long i;\r
+\r
+ for( i=0; i < _nfiles; i++ )\r
+ {\r
+ /* Checks if the file is opened or not */\r
+ if( _Files[i]->_Mode & (_MOPENR | _MOPENW | _MOPENA ) )\r
+ fclose( _Files[i] ); /* Closes the file */\r
+ }\r
+}\r
+\r
+/**************************************************************************/\r
+/* open:file open */\r
+/* Return value:File number (Pass) */\r
+/* -1 (Failure) */\r
+/**************************************************************************/\r
+#if defined( __RX )\r
+long open(const char *name, /* File name */\r
+ long mode, /* Open mode */\r
+ long flg) /* Open flag */\r
+#else\r
+int open(char *name, /* File name */\r
+ int mode, /* Open mode */\r
+ int flg) /* Open flag */\r
+#endif\r
+{\r
+\r
+\r
+ if( strcmp( name, FPATH_STDIN ) == 0 ) /* Standard Input file? */\r
+ {\r
+ if( ( mode & O_RDONLY ) == 0 ) return -1;\r
+ flmod[STDIN] = mode;\r
+ return STDIN;\r
+ }\r
+ else if( strcmp( name, FPATH_STDOUT ) == 0 )/* Standard Output file? */\r
+ {\r
+ if( ( mode & O_WRONLY ) == 0 ) return -1;\r
+ flmod[STDOUT] = mode;\r
+ return STDOUT;\r
+ }\r
+ else if(strcmp(name, FPATH_STDERR ) == 0 ) /* Standard Error file? */\r
+ {\r
+ if( ( mode & O_WRONLY ) == 0 ) return -1;\r
+ flmod[STDERR] = mode;\r
+ return STDERR;\r
+ }\r
+ else return -1; /*Others */\r
+}\r
+\r
+#if defined( __RX )\r
+long close( long fileno )\r
+#else\r
+int close( int fileno )\r
+#endif\r
+{\r
+ return 1;\r
+}\r
+\r
+/**************************************************************************/\r
+/* write:Data write */\r
+/* Return value:Number of write characters (Pass) */\r
+/* -1 (Failure) */\r
+/**************************************************************************/\r
+#if defined( __RX )\r
+long write(long fileno, /* File number */\r
+ const unsigned char *buf, /* The address of destination buffer */\r
+ long count) /* The number of chacter to write */\r
+#else\r
+int write(int fileno, /* File number */\r
+ char *buf, /* The address of destination buffer */\r
+ int count) /* The number of chacter to write */\r
+#endif\r
+{\r
+ long i; /* A variable for counter */\r
+ unsigned char c; /* An output character */\r
+\r
+ /* Checking the mode of file , output each character */\r
+ /* Checking the attribute for Write-Only, Read-Only or Read-Write */\r
+ if(flmod[fileno]&O_WRONLY || flmod[fileno]&O_RDWR)\r
+ {\r
+ if( fileno == STDIN ) return -1; /* Standard Input */\r
+ else if( (fileno == STDOUT) || (fileno == STDERR) ) \r
+ /* Standard Error/output */\r
+ {\r
+ for( i = count; i > 0; --i )\r
+ {\r
+ c = *buf++;\r
+ charput(c);\r
+ }\r
+ return count; /*Return the number of written characters */\r
+ }\r
+ else return -1; /* Incorrect file number */\r
+ }\r
+ else return -1; /* An error */\r
+}\r
+\r
+#if defined( __RX )\r
+long read( long fileno, unsigned char *buf, long count )\r
+#else\r
+int read( int fileno, char *buf, unsigned int count )\r
+#endif\r
+{\r
+ long i;\r
+\r
+ /* Checking the file mode with the file number, each character is input and stored the buffer */\r
+\r
+ if((flmod[fileno]&_MOPENR) || (flmod[fileno]&O_RDWR)){\r
+ for(i = count; i > 0; i--){\r
+ *buf = charget();\r
+ if(*buf==CR){ /* Replace the new line character */\r
+ *buf = LF;\r
+ }\r
+ buf++;\r
+ }\r
+ return count;\r
+ }\r
+ else {\r
+ return -1;\r
+ }\r
+}\r
+\r
+#if defined( __RX )\r
+long lseek( long fileno, long offset, long base )\r
+#else\r
+long lseek( int fileno, long offset, int base )\r
+#endif\r
+{\r
+ return -1L;\r
+}\r
+\r
--- /dev/null
+/***********************************************************************/\r
+/* */\r
+/* FILE :resetprg.c */\r
+/* DATE :Wed, Aug 11, 2010 */\r
+/* DESCRIPTION :Reset Program */\r
+/* CPU TYPE :Other */\r
+/* */\r
+/* This file is generated by Renesas Project Generator (Ver.4.50). */\r
+/* NOTE:THIS IS A TYPICAL EXAMPLE. */\r
+/* */\r
+/***********************************************************************/\r
+ \r
+\r
+\r
+/*********************************************************************\r
+*\r
+* Device : RX/RX600\r
+*\r
+* File Name : resetprg.c\r
+*\r
+* Abstract : Reset Program.\r
+*\r
+* History : 1.00 (2009-08-07)\r
+*\r
+* NOTE : THIS IS A TYPICAL EXAMPLE.\r
+*\r
+* Copyright(c) 2009 Renesas Technology Corp.\r
+* And Renesas Solutions Corp.,All Rights Reserved. \r
+*\r
+*********************************************************************/\r
+\r
+#include <machine.h>\r
+#include <_h_c_lib.h>\r
+//#include <stddef.h> // Remove the comment when you use errno\r
+//#include <stdlib.h> // Remove the comment when you use rand()\r
+#include "typedefine.h"\r
+#include "stacksct.h"\r
+\r
+#pragma inline_asm Change_PSW_PM_to_UserMode\r
+static void Change_PSW_PM_to_UserMode(void);\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+void PowerON_Reset_PC(void);\r
+void main(void);\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#ifdef __cplusplus // Use SIM I/O\r
+extern "C" {\r
+#endif\r
+extern void _INIT_IOLIB(void);\r
+extern void _CLOSEALL(void);\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#define PSW_init 0x00010000\r
+#define FPSW_init 0x00000100\r
+\r
+//extern void srand(_UINT); // Remove the comment when you use rand()\r
+//extern _SBYTE *_s1ptr; // Remove the comment when you use strtok()\r
+ \r
+//#ifdef __cplusplus // Use Hardware Setup\r
+//extern "C" {\r
+//#endif\r
+//extern void HardwareSetup(void);\r
+//#ifdef __cplusplus\r
+//}\r
+//#endif\r
+ \r
+//#ifdef __cplusplus // Remove the comment when you use global class object\r
+//extern "C" { // Sections C$INIT and C$END will be generated\r
+//#endif\r
+//extern void _CALL_INIT(void);\r
+//extern void _CALL_END(void);\r
+//#ifdef __cplusplus\r
+//}\r
+//#endif\r
+\r
+#pragma section ResetPRG\r
+\r
+#pragma entry PowerON_Reset_PC\r
+\r
+void PowerON_Reset_PC(void)\r
+{ \r
+ set_intb((unsigned long)__sectop("C$VECT"));\r
+ set_fpsw(FPSW_init);\r
+\r
+ _INITSCT();\r
+\r
+// _INIT_IOLIB(); // Remove the comment when you use SIM I/O\r
+\r
+// errno=0; // Remove the comment when you use errno\r
+// srand((_UINT)1); // Remove the comment when you use rand()\r
+// _s1ptr=NULL; // Remove the comment when you use strtok()\r
+ \r
+// HardwareSetup(); // Use Hardware Setup\r
+ nop();\r
+\r
+// _CALL_INIT(); // Remove the comment when you use global class object\r
+\r
+ set_psw(PSW_init); // Set Ubit & Ibit for PSW\r
+// Change_PSW_PM_to_UserMode(); // DO NOT CHANGE TO USER MODE IF USING FREERTOS!\r
+ ( void ) Change_PSW_PM_to_UserMode; // Just to avoid compiler warnings.\r
+\r
+ main();\r
+\r
+// _CLOSEALL(); // Use SIM I/O\r
+ \r
+// _CALL_END(); // Remove the comment when you use global class object\r
+\r
+ brk();\r
+}\r
+\r
+static void Change_PSW_PM_to_UserMode(void)\r
+{\r
+ MVFC PSW,R1\r
+ OR #00100000h,R1\r
+ PUSH.L R1\r
+ MVFC PC,R1\r
+ ADD #10,R1\r
+ PUSH.L R1\r
+ RTE\r
+ NOP\r
+ NOP\r
+}\r
--- /dev/null
+#include <stddef.h>\r
+#include <stdio.h>\r
+#define HEAPSIZE 0x400\r
+signed char *sbrk( size_t size );\r
+union HEAP_TYPE\r
+{\r
+ signed long dummy;\r
+ signed char heap[HEAPSIZE];\r
+};\r
+static union HEAP_TYPE heap_area;\r
+\r
+/* End address allocated by sbrk */\r
+static signed char *brk = ( signed char * ) &heap_area;\r
+signed char *sbrk( size_t size )\r
+{\r
+ signed char *p;\r
+ if( brk + size > heap_area.heap + HEAPSIZE )\r
+ {\r
+ p = ( signed char * ) - 1;\r
+ }\r
+ else\r
+ {\r
+ p = brk;\r
+ brk += size;\r
+ }\r
+\r
+ return p;\r
+}\r
--- /dev/null
+/***********************************************************************/\r
+/* */\r
+/* FILE :vecttbl.c */\r
+/* DATE :Wed, Aug 11, 2010 */\r
+/* DESCRIPTION :Initialize of Vector Table */\r
+/* CPU TYPE :Other */\r
+/* */\r
+/* This file is generated by Renesas Project Generator (Ver.4.50). */\r
+/* NOTE:THIS IS A TYPICAL EXAMPLE. */\r
+/* */\r
+/***********************************************************************/\r
+ \r
+\r
+\r
+/*********************************************************************\r
+*\r
+* Device : RX/RX600\r
+*\r
+* File Name : vecttbl.c\r
+*\r
+* Abstract : Initialize of Vector Table.\r
+*\r
+* History : 1.00 (2009-08-07)\r
+*\r
+* NOTE : THIS IS A TYPICAL EXAMPLE.\r
+*\r
+* Copyright(c) 2009 Renesas Technology Corp.\r
+* And Renesas Solutions Corp.,All Rights Reserved. \r
+*\r
+*********************************************************************/\r
+\r
+#include "vect.h"\r
+\r
+#pragma section C FIXEDVECT\r
+\r
+void* const Fixed_Vectors[] = {\r
+//;0xffffffd0 Exception(Supervisor Instruction)\r
+ (void*) Excep_SuperVisorInst,\r
+//;0xffffffd4 Reserved\r
+ Dummy,\r
+//;0xffffffd8 Reserved\r
+ Dummy,\r
+//;0xffffffdc Exception(Undefined Instruction)\r
+ (void*) Excep_UndefinedInst,\r
+//;0xffffffe0 Reserved\r
+ Dummy,\r
+//;0xffffffe4 Exception(Floating Point)\r
+ (void*) Excep_FloatingPoint,\r
+//;0xffffffe8 Reserved\r
+ Dummy,\r
+//;0xffffffec Reserved\r
+ Dummy,\r
+//;0xfffffff0 Reserved\r
+ Dummy,\r
+//;0xfffffff4 Reserved\r
+ Dummy,\r
+//;0xfffffff8 NMI\r
+ (void*) NonMaskableInterrupt,\r
+//;0xfffffffc RESET\r
+//;<<VECTOR DATA START (POWER ON RESET)>>\r
+//;Power On Reset PC\r
+PowerON_Reset_PC \r
+//;<<VECTOR DATA END (POWER ON RESET)>>\r
+};\r
--- /dev/null
+[HIMDBVersion]\r
+2.0\r
+[DATABASE_VERSION]\r
+"2.3" \r
+[SESSION_DETAILS]\r
+"" \r
+[INFORMATION]\r
+"" \r
+[GENERAL_DATA]\r
+"FIRST_CONNECTION_TAG" "NO" \r
+"MRULABELS_DATAMANAGER_KEY" "108a|FFFFFFFF|00000000|1054|fff8cd9e|1050|fff8c484|88218|000870B4|000870AE|88204|88208|18b8" \r
+"RESET_CPU_AFTER_DOWNLOAD_TAG" "VARIANT_TRUE_STORE_TAG" \r
+"{0AF60212-1285-4767-AB8A-73DB62CC8DBD}R_ECXOS_0ECXOS_OBJECT01" " " \r
+"{0AF60212-1285-4767-AB8A-73DB62CC8DBD}R_ECXOS_0ECXOS_OBJECT02" " " \r
+"{0AF60212-1285-4767-AB8A-73DB62CC8DBD}R_ECXOS_0ECXOS_OBJECT03" " " \r
+"{0AF60212-1285-4767-AB8A-73DB62CC8DBD}R_ECXOS_0ECXOS_OBJECT04" " " \r
+"{0AF60212-1285-4767-AB8A-73DB62CC8DBD}R_ECXOS_0ECXOS_OBJECT05" " " \r
+"{0AF60212-1285-4767-AB8A-73DB62CC8DBD}R_ECXOS_0ECXOS_OBJECT06" " " \r
+"{0AF60212-1285-4767-AB8A-73DB62CC8DBD}R_ECXOS_0ECXOS_OBJECT07" " " \r
+"{0AF60212-1285-4767-AB8A-73DB62CC8DBD}R_ECXOS_0ECXOS_OBJECT08" " " \r
+"{0AF60212-1285-4767-AB8A-73DB62CC8DBD}R_ECXOS_0ECXOS_OBJECT09" " " \r
+"{0AF60212-1285-4767-AB8A-73DB62CC8DBD}R_ECXOS_0ECXOS_OBJECT10" " " \r
+"{0AF60212-1285-4767-AB8A-73DB62CC8DBD}R_ECXOS_0ECXOS_OBJECT_DEFINE_FILE" "" \r
+"{0AF60212-1285-4767-AB8A-73DB62CC8DBD}R_ECXOS_0ECXOS_OBJECT_DEFINE_SELETCT" "1" \r
+"{0AF60212-1285-4767-AB8A-73DB62CC8DBD}R_ECXOS_0ECXOS_OBJECT_MODIFIED" "1" \r
+"{0AF60212-1285-4767-AB8A-73DB62CC8DBD}R_ECXOS_0ECXOS_OBJECT_NOREAD_OSOBJECT" "0" \r
+"{0AF60212-1285-4767-AB8A-73DB62CC8DBD}R_ECXOS_0ECXOS_OBJECT_SAMPLING_PERIOD" "100" \r
+"{228DB593-0AB2-4EBE-A098-A2CABF094E46}RamMonitorCtrlViews" "0" \r
+"{287A8023-99B5-49E1-A54E-4DDCA43D7959}MapCtrlECX_MAP_FIND_SYMBOL_LIST" "" \r
+"{287A8023-99B5-49E1-A54E-4DDCA43D7959}MapCtrlViews" "0" \r
+"{2BA6A3EE-6488-11D5-80D4-00C04F68EAD7}ECXLABEL_ADDDLG_ADDR" "" \r
+"{2BA6A3EE-6488-11D5-80D4-00C04F68EAD7}LabelCtrlSymbolFileDir" "" \r
+"{2BA6A3EE-6488-11D5-80D4-00C04F68EAD7}LabelCtrlSymbolFileName" "" \r
+"{2BA6A3EE-6488-11D5-80D4-00C04F68EAD7}LabelCtrlViews" "0" \r
+"{2BA6A3EF-6488-11D5-80D4-00C04F68EAD7}StatusCtrlViews" "0" \r
+"{313F4FC1-6566-11D5-8BBE-0004E2013C71}CmdLineCtrlBatchFileName" "" \r
+"{313F4FC1-6566-11D5-8BBE-0004E2013C71}CmdLineCtrlBreakpointFlag" "-1 " \r
+"{313F4FC1-6566-11D5-8BBE-0004E2013C71}CmdLineCtrlBreakpointStatus" "-1 " \r
+"{313F4FC1-6566-11D5-8BBE-0004E2013C71}CmdLineCtrlBrowseDirectory" "" \r
+"{313F4FC1-6566-11D5-8BBE-0004E2013C71}CmdLineCtrlLogFileName" "" \r
+"{313F4FC1-6566-11D5-8BBE-0004E2013C71}CmdLineCtrlSplitterPosition" "242" \r
+"{313F4FC1-6566-11D5-8BBE-0004E2013C71}CmdLineCtrlViews" "1" \r
+"{313F4FC1-6566-11D5-8BBE-0004E2013C71}CmdLineCtrlWindowProperties" "17" \r
+"{313F4FC1-6566-11D5-8BBE-0004E2013C71}CmdLineWndInstanceKey0" "{WK_00000001_CmdLine}" \r
+"{313F4FC1-6566-11D5-8BBE-0004E2013C71}TclTkCtrlLogFileName" "" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}ECX_MEMORY_COMPARE_END_ADDRESS" "" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}ECX_MEMORY_COMPARE_START_ADDRESS" "" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}ECX_MEMORY_DISPLAY_DEST_ADDRESS" "" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}ECX_MEMORY_DISPLAY_END_ADDRESS" "" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}ECX_MEMORY_DISPLAY_START_ADDRESS" "" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}ECX_MEMORY_FILL_END_ADDRESS" "" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}ECX_MEMORY_FILL_START_ADDRESS" "" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}ECX_MEMORY_MOVE_END_ADDRESS" "" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}ECX_MEMORY_MOVE_START_ADDRESS" "" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}ECX_MEMORY_SEARCH_END_ADDRESS" "" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}ECX_MEMORY_SEARCH_START_ADDRESS" "" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}ECX_MEMORY_SET_DEST_ADDRESS" "" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}ECX_MEMORY_TEST_END_ADDRESS" "" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}ECX_MEMORY_TEST_START_ADDRESS" "" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryCtrlViews" "0" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewA0AutoRefreshEnableTopPane" "0" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewA0AutoRefreshIntervalTopPane" "100" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewA0DataLength" "4" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewA0DispAddressTopPane" "4180" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewA0DispCode" "42208" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewA0DispColumnCount" "4" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewA0IsDispCode" "1" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewA0IsDispFloat" "0" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewA0IsDispLabel" "0" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewA0IsDispRegister" "0" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewA0IsRegFollowEnableTopPane" "0" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewA0LabelWidth" "96" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewA0Radix" "16" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewA0RegFollowRegTblIDTopPane" "0" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewA0RegisterWidth" "96" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewA0ScrollEndAddress" "-1" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewA0ScrollStartAddress" "0" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewA0StartUpSymbolTopPane" "" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewAInstanceKey0" "{WK_00000001_MEMORY}RTOSDemoSessionRX600_E1_E20_SYSTEM" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewB0AutoRefreshEnableTopPane" "0" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewB0AutoRefreshIntervalTopPane" "100" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewB0DataLength" "4" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewB0DispAddressTopPane" "4180" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewB0DispCode" "42208" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewB0DispColumnCount" "4" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewB0IsDispCode" "1" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewB0IsDispFloat" "0" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewB0IsDispLabel" "0" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewB0IsDispRegister" "0" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewB0IsRegFollowEnableTopPane" "0" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewB0LabelWidth" "96" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewB0Radix" "16" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewB0RegFollowRegTblIDTopPane" "0" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewB0RegisterWidth" "96" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewB0ScrollEndAddress" "-1" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewB0ScrollStartAddress" "0" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewB0StartUpSymbolTopPane" "" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewBInstanceKey0" "{WK_00000001_MEMORY}RTOSDemoSessionRX600_E1_E20_SYSTEMViewB" \r
+"{4F025ABC-BE66-4CB6-9CEE-06C61418278E}Trace2CtrlSaveFileDir" "" \r
+"{4F025ABC-BE66-4CB6-9CEE-06C61418278E}Trace2CtrlSaveFileName" "" \r
+"{4F025ABC-BE66-4CB6-9CEE-06C61418278E}Trace2CtrlViews" "0" \r
+"{5F75FDA0-6FF0-11D5-B7CE-00E029352378}PACtrlSaveFileDir" "" \r
+"{5F75FDA0-6FF0-11D5-B7CE-00E029352378}PACtrlSaveFileName" "" \r
+"{5F75FDA0-6FF0-11D5-B7CE-00E029352378}PACtrlViews" "0" \r
+"{64753FED-D387-4B8C-A91D-D3419C869C07}C_EVAL_DENORMAL_MODE" "16777216" \r
+"{64753FED-D387-4B8C-A91D-D3419C869C07}C_EVAL_ROUND_MODE" "768" \r
+"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_0" "0000000000007500" \r
+"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_1" "0000000000000000" \r
+"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_10" "00000000A5A5A5A5" \r
+"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_11" "00000000A5A5A5A5" \r
+"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_12" "00000000A5A5A5A5" \r
+"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_13" "00000000A5A5A5A5" \r
+"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_14" "00000000C4658E35" \r
+"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_15" "00000000A5A5A5A5" \r
+"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_16" "0000000000007500" \r
+"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_17" "000000000000C378" \r
+"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_18" "0000000000030000" \r
+"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_19" "00000000FFE02C63" \r
+"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_2" "00000000CA0A613B" \r
+"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_20" "00000000FFE01388" \r
+"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_21" "0000000000000000" \r
+"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_22" "0000000000000000" \r
+"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_23" "0000000000000000" \r
+"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_24" "0000000040000100" \r
+"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_25" "00008A613AE30000" \r
+"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_3" "00000000A5A5A5A5" \r
+"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_4" "000000000000FEEE" \r
+"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_5" "000000000000FEED" \r
+"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_6" "00000000A5A5A5A5" \r
+"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_7" "00000000A5A5A5A5" \r
+"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_8" "00000000A5A5A5A5" \r
+"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_9" "00000000A5A5A5A5" \r
+"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_COUNT" "26" \r
+"{6C4D5B81-FD67-46A9-A089-EA44DCDE47FD}RAMMonitorManagerCtrlBlockInfoFileDir" "" \r
+"{6C4D5B81-FD67-46A9-A089-EA44DCDE47FD}RAMMonitorManagerCtrlBlockInfoFileName" "" \r
+"{743E9BC2-6B9D-44A5-A5B6-F8C3FF2C1CAD}GraphCtrlViews" "0" \r
+"{743E9BC2-6B9D-44A5-A5B6-F8C3FF2C1CAD}GraphWnd_Close_Count" "0" \r
+"{743E9BC2-6B9D-44A5-A5B6-F8C3FF2C1CAD}GraphWnd_Mode" "1" \r
+"{743E9BC2-6B9D-44A5-A5B6-F8C3FF2C1CAD}GraphWnd_Trace_Mode" "0" \r
+"{7943C44E-7D44-422A-9140-4CF55C88F7D3}DifferenceCtrlViews" "0" \r
+"{855C64C3-E49C-4450-9BCA-C9822566D214}OSObjectCtrlViews" "0" \r
+"{8A898260-6F1D-11D5-8EB6-00004CC34E9D}ECX_WAVE" "00000000,00000000,0,0" \r
+"{8A898260-6F1D-11D5-8EB6-00004CC34E9D}ECX_WAVE_ADDRESS_NAME" "" \r
+"{8A898260-6F1D-11D5-8EB6-00004CC34E9D}ECX_WAVE_COMB_ADDRESS" ",,,," \r
+"{8A898260-6F1D-11D5-8EB6-00004CC34E9D}ECX_WAVE_COMB_BUFFER" ",,,," \r
+"{8A898260-6F1D-11D5-8EB6-00004CC34E9D}ECX_WAVE_SAMPLING_RATE" "1000" \r
+"{8A898260-6F1D-11D5-8EB6-00004CC34E9D}WaveformCtrlViews" "0" \r
+"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersCtrlViews" "0" \r
+"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersWnd0ColumnWidth" "47,153,35" \r
+"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersWnd0ECX_REGISTER_COUNT" "33" \r
+"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersWnd0ECX_REGISTER_DISPLAYED" "1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1" \r
+"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersWnd0HideFLAGs" "0" \r
+"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersWnd0HideRadix" "0" \r
+"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersWnd0LastFileName" "" \r
+"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersWnd0RadixList" "16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,2,16,16,16,16,16,16,16," \r
+"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersWndInstanceKey0" "{WK_00000001_REGISTERS}RTOSDemoSessionRX600_E1_E20_SYSTEM" \r
+"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersWndViewB0ColumnWidth" "47,153,35" \r
+"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersWndViewB0ECX_REGISTER_COUNT" "33" \r
+"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersWndViewB0ECX_REGISTER_DISPLAYED" "1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1" \r
+"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersWndViewB0HideFLAGs" "0" \r
+"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersWndViewB0HideRadix" "0" \r
+"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersWndViewB0LastFileName" "" \r
+"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersWndViewB0RadixList" "16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,2,16,16,16,16,16,16,16," \r
+"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersWndViewBInstanceKey0" "{WK_00000001_REGISTERS}RTOSDemoSessionRX600_E1_E20_SYSTEMViewB" \r
+"{AC411480-6F0A-11D5-8EB6-00004CC34E9D}ECX_IMAGE_ADDRESS_NAME" "" \r
+"{AC411480-6F0A-11D5-8EB6-00004CC34E9D}ECX_IMAGE_BUFFER" "00000000,00000000,0,0" \r
+"{AC411480-6F0A-11D5-8EB6-00004CC34E9D}ECX_IMAGE_COLOR" "0,0,0,0" \r
+"{AC411480-6F0A-11D5-8EB6-00004CC34E9D}ECX_IMAGE_COMB_ADDRESS" ",,,," \r
+"{AC411480-6F0A-11D5-8EB6-00004CC34E9D}ECX_IMAGE_COMB_PALETTE" ",,,," \r
+"{AC411480-6F0A-11D5-8EB6-00004CC34E9D}ECX_IMAGE_PALETTE_NAME" "" \r
+"{AC411480-6F0A-11D5-8EB6-00004CC34E9D}ECX_IMAGE_REDRAW_CONTINUOUSLY" "0,2" \r
+"{AC411480-6F0A-11D5-8EB6-00004CC34E9D}ECX_IMAGE_SAMPLEING_RATE" "1000" \r
+"{AC411480-6F0A-11D5-8EB6-00004CC34E9D}ECX_IMAGE_VIEW" "0,0,0,0,0,0" \r
+"{AC411480-6F0A-11D5-8EB6-00004CC34E9D}ImageCtrlViews" "0" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchCtrlViews" "0" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ColWidth0" "207" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ColWidth1" "182" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ColWidth12" "116" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ColWidth2" "89" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ColWidth3" "200" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ECX_WATCH_ITEM0000" "pxCurrentRxDesc, 10, 0, P, Col, Hex, N" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ECX_WATCH_ITEM0000_SCOPE" "Current Scope," \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ECX_WATCH_ITEM0001" "*, 11, 0, C0000, Exp, Hex, MN" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ECX_WATCH_ITEM0001_SCOPE" "Current Scope," \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ECX_WATCH_ITEM0002" "status, 2, 0, C0001, Col, Hex, MN" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ECX_WATCH_ITEM0002_SCOPE" "Current Scope," \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ECX_WATCH_ITEM0003" "size, 2, 0, C0001, Col, Hex, MN" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ECX_WATCH_ITEM0003_SCOPE" "Current Scope," \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ECX_WATCH_ITEM0004" "bufsize, 2, 0, C0001, Col, Hex, MN" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ECX_WATCH_ITEM0004_SCOPE" "Current Scope," \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ECX_WATCH_ITEM0005" "buf_p, 4, 0, C0001, Col, Hex, MN" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ECX_WATCH_ITEM0005_SCOPE" "Current Scope," \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ECX_WATCH_ITEM0006" "next, 4, 0, C0001, Col, Hex, MN" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ECX_WATCH_ITEMCnt" "1" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd1ColWidth0" "120" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd1ColWidth1" "150" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd1ColWidth12" "200" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd1ColWidth2" "120" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd1ColWidth3" "200" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd1ECX_WATCH_ITEMCnt" "0" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd2ColWidth0" "120" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd2ColWidth1" "150" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd2ColWidth12" "200" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd2ColWidth2" "120" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd2ColWidth3" "200" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd2ECX_WATCH_ITEMCnt" "0" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd3ColWidth0" "120" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd3ColWidth1" "150" \r
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+[WINDOW_POSITION_STATE_DATA_VD2]\r
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+[WINDOW_POSITION_STATE_DATA_VD4]\r
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+"{WK_TB00000028_RTOSDEBUG} TOOLBAR 0" \r
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+[STATUSBAR_DEBUGGER_PANESTATE_VD1]\r
+[STATUSBAR_DEBUGGER_PANESTATE_VD2]\r
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+[DEBUGGER_OPTIONS]\r
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+[DOWNLOAD_MODULES]\r
+"$(CONFIGDIR)\$(PROJECTNAME).abs" 0 "Elf/Dwarf2" 0 0 1 0 \r
+[CONNECT_ON_GO]\r
+"FALSE" \r
+[DOWNLOAD_MODULES_AFTER_BUILD]\r
+"TRUE" \r
+[REMOVE_BREAKPOINTS_ON_DOWNLOAD]\r
+"FALSE" \r
+[DISABLE_MEMORY_ACCESS_PRIOR_TO_COMMAND_FILE_EXECUTION]\r
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+"FALSE" \r
+[DISABLE_MEMORY_ACCESS_DURING_EXECUTION]\r
+"FALSE" \r
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+[BREAKPOINTS]\r
+"c:\work\rx\rx630\freertosv7.0.2\demo\rx600_rx630-rsk_renesas\rtosdemo\main-full.c" 447 -2081745 1 "{00000000-0000-0000-C000-000000000046}" "" \r
+[END]\r
--- /dev/null
+Project name : RTOSDemo\r\r
+\r\r
+Renesas RX Standard Toolchain 1.0.2.0 was upgraded to\r\r
+ Renesas RX Standard Toolchain 1.1.0.0.\r\r
+\r\r
--- /dev/null
+/*\r
+ FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd.\r
+ \r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ >>>NOTE<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ http://www.FreeRTOS.org - Documentation, latest information, license and\r
+ contact details.\r
+\r
+ http://www.SafeRTOS.com - A version that is certified for use in safety\r
+ critical systems.\r
+\r
+ http://www.OpenRTOS.com - Commercial support, development, porting,\r
+ licensing and training services.\r
+*/\r
+\r
+#ifndef INT_QUEUE_TIMER_H\r
+#define INT_QUEUE_TIMER_H\r
+\r
+void vInitialiseTimerForIntQueueTest( void );\r
+portBASE_TYPE xTimer0Handler( void );\r
+portBASE_TYPE xTimer1Handler( void );\r
+\r
+#endif\r
+\r
--- /dev/null
+ \r
+ \r
+ \r
+ \r
+ \r
+ \r
+ \r
+ \r
+ \r
+ \r
+ \r
+/************************************************************************\r
+*\r
+* Device : RX/RX600/RX630\r
+*\r
+* File Name : ioedfine.h\r
+*\r
+* Abstract : Definition of I/O Register.\r
+*\r
+* History : 0.50 (2011-03-28) [Hardware Manual Revision : 0.50]\r
+* : 0.10 (2010-10-06) [Hardware Manual Revision : 0.11]\r
+*\r
+* NOTE : THIS IS A TYPICAL EXAMPLE.\r
+*\r
+* Copyright (C) 2010(2011) Renesas Electronics Corporation\r
+* and Renesas Solutions Corp.\r
+*\r
+************************************************************************/\r
+/********************************************************************************/\r
+/* */\r
+/* DESCRIPTION : Definition of ICU Register */\r
+/* CPU TYPE : RX630 */\r
+/* */\r
+/* Usage : IR,DTCER,IER,IPR of ICU Register */\r
+/* The following IR, DTCE, IEN, IPR macro functions simplify usage. */\r
+/* The bit access operation is "Bit_Name(interrupt source,name)". */\r
+/* A part of the name can be omitted. */\r
+/* for example : */\r
+/* IR(TPU0,TGI0A) = 0; expands to : */\r
+/* ICU.IR[126].BIT.IR = 0; */\r
+/* */\r
+/* DTCE(ICU,IRQ0) = 1; expands to : */\r
+/* ICU.DTCER[64].BIT.DTCE = 1; */\r
+/* */\r
+/* IEN(CMT0,CMI0) = 1; expands to : */\r
+/* ICU.IER[0x03].BIT.IEN4 = 1; */\r
+/* */\r
+/* IPR(TPU0,TGI0A) = 2; expands to : */\r
+/* IPR(TPU0,TGI ) = 2; // TGI0A,TGI0B,TGI0C,TGI0D share IPR level. */\r
+/* ICU.IPR[126].BIT.IPR = 2; */\r
+/* */\r
+/* IPR(SCI0,RXI0) = 3; expands to : */\r
+/* IPR(SCI0, ) = 3; // SCI0 uses single IPR for all sources. */\r
+/* ICU.IPR[214].BIT.IPR = 3; */\r
+/* */\r
+/* Usage : #pragma interrupt Function_Identifier(vect=**) */\r
+/* The number of vector is "(interrupt source, name)". */\r
+/* for example : */\r
+/* #pragma interrupt INT_IRQ0(vect=VECT(ICU,IRQ0)) expands to : */\r
+/* #pragma interrupt INT_IRQ0(vect=64) */\r
+/* #pragma interrupt INT_CMT0_CMI0(vect=VECT(CMT0,CMI0)) expands to : */\r
+/* #pragma interrupt INT_CMT0_CMI0(vect=28) */\r
+/* #pragma interrupt INT_MTU0_TGIA0(vect=VECT(MTU0,TGIA0)) expands to : */\r
+/* #pragma interrupt INT_MTU0_TGIA0(vect=142) */\r
+/* #pragma interrupt INT_TPU0_TGI0A(vect=VECT(TPU0,TGI0A)) expands to : */\r
+/* #pragma interrupt INT_TPU0_TGI0A(vect=126) */\r
+/* */\r
+/* Usage : MSTPCRA,MSTPCRB,MSTPCRC of SYSTEM Register */\r
+/* The bit access operation is "MSTP(name)". */\r
+/* The name that can be used is a macro name defined with "iodefine.h". */\r
+/* for example : */\r
+/* MSTP(TMR2) = 0; // TMR2,TMR3,TMR23 expands to : */\r
+/* SYSTEM.MSTPCRA.BIT.MSTPA4 = 0; */\r
+/* MSTP(SCI0) = 0; // SCI0,SMCI0 expands to : */\r
+/* SYSTEM.MSTPCRB.BIT.MSTPB31 = 0; */\r
+/* MSTP(MTU4) = 0; // MTU,MTU0,MTU1,MTU2,MTU3,MTU4,MTU5 expands to : */\r
+/* SYSTEM.MSTPCRA.BIT.MSTPA9 = 0; */\r
+/* MSTP(TPU4) = 0; // TPU0,TPU1,TPU2,TPU3,TPU4,TPU5 expands to : */\r
+/* SYSTEM.MSTPCRA.BIT.MSTPA13 = 0; */\r
+/* MSTP(CMT3) = 0; // CMT2,CMT3 expands to : */\r
+/* SYSTEM.MSTPCRA.BIT.MSTPA14 = 0; */\r
+/* */\r
+/* */\r
+/********************************************************************************/\r
+#ifndef __RX630IODEFINE_HEADER__\r
+#define __RX630IODEFINE_HEADER__\r
+#pragma bit_order left\r
+#pragma unpack\r
+struct st_ad {\r
+ unsigned short ADDRA;\r
+ unsigned short ADDRB;\r
+ unsigned short ADDRC;\r
+ unsigned short ADDRD;\r
+ unsigned short ADDRE;\r
+ unsigned short ADDRF;\r
+ unsigned short ADDRG;\r
+ unsigned short ADDRH;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char ADIE:1;\r
+ unsigned char ADST:1;\r
+ unsigned char :2;\r
+ unsigned char CH:3;\r
+ } BIT;\r
+ } ADCSR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TRGS:3;\r
+ unsigned char :1;\r
+ unsigned char CKS:2;\r
+ unsigned char MODE:2;\r
+ } BIT;\r
+ } ADCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char DPSEL:1;\r
+ unsigned char EXOEN:1;\r
+ unsigned char EXSEL:2;\r
+ } BIT;\r
+ } ADCR2;\r
+ unsigned char ADSSTR;\r
+ char wk0[11];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :6;\r
+ unsigned char DIAG:2;\r
+ } BIT;\r
+ } ADDIAGR;\r
+};\r
+\r
+struct st_bsc {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char STSCLR:1;\r
+ } BIT;\r
+ } BERCLR;\r
+ char wk0[3];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :6;\r
+ unsigned char TOEN:1;\r
+ unsigned char IGAEN:1;\r
+ } BIT;\r
+ } BEREN;\r
+ char wk1[3];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char MST:3;\r
+ unsigned char :2;\r
+ unsigned char TO:1;\r
+ unsigned char IA:1;\r
+ } BIT;\r
+ } BERSR1;\r
+ char wk2[1];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short ADDR:13;\r
+ } BIT;\r
+ } BERSR2;\r
+ char wk3[4];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :2;\r
+ unsigned short BPEB:2;\r
+ unsigned short BPFB:2;\r
+ unsigned short :2;\r
+ unsigned short BPGB:2;\r
+ unsigned short BPIB:2;\r
+ unsigned short BPRO:2;\r
+ unsigned short BPRA:2;\r
+ } BIT;\r
+ } BUSPRI;\r
+ char wk4[7408];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short PRMOD:1;\r
+ unsigned short :5;\r
+ unsigned short PWENB:1;\r
+ unsigned short PRENB:1;\r
+ unsigned short :4;\r
+ unsigned short EWENB:1;\r
+ unsigned short :2;\r
+ unsigned short WRMOD:1;\r
+ } BIT;\r
+ } CS0MOD;\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned long :3;\r
+ unsigned long CSRWAIT:5;\r
+ unsigned long :3;\r
+ unsigned long CSWWAIT:5;\r
+ unsigned long :5;\r
+ unsigned long CSPRWAIT:3;\r
+ unsigned long :5;\r
+ unsigned long CSPWWAIT:3;\r
+ } BIT;\r
+ } CS0WCR1;\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned long :1;\r
+ unsigned long CSON:3;\r
+ unsigned long :1;\r
+ unsigned long WDON:3;\r
+ unsigned long :1;\r
+ unsigned long WRON:3;\r
+ unsigned long :1;\r
+ unsigned long RDON:3;\r
+ unsigned long :2;\r
+ unsigned long AWAIT:2;\r
+ unsigned long :1;\r
+ unsigned long WDOFF:3;\r
+ unsigned long :1;\r
+ unsigned long CSWOFF:3;\r
+ unsigned long :1;\r
+ unsigned long CSROFF:3;\r
+ } BIT;\r
+ } CS0WCR2;\r
+ char wk5[6];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short PRMOD:1;\r
+ unsigned short :5;\r
+ unsigned short PWENB:1;\r
+ unsigned short PRENB:1;\r
+ unsigned short :4;\r
+ unsigned short EWENB:1;\r
+ unsigned short :2;\r
+ unsigned short WRMOD:1;\r
+ } BIT;\r
+ } CS1MOD;\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned long :3;\r
+ unsigned long CSRWAIT:5;\r
+ unsigned long :3;\r
+ unsigned long CSWWAIT:5;\r
+ unsigned long :5;\r
+ unsigned long CSPRWAIT:3;\r
+ unsigned long :5;\r
+ unsigned long CSPWWAIT:3;\r
+ } BIT;\r
+ } CS1WCR1;\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned long :1;\r
+ unsigned long CSON:3;\r
+ unsigned long :1;\r
+ unsigned long WDON:3;\r
+ unsigned long :1;\r
+ unsigned long WRON:3;\r
+ unsigned long :1;\r
+ unsigned long RDON:3;\r
+ unsigned long :2;\r
+ unsigned long AWAIT:2;\r
+ unsigned long :1;\r
+ unsigned long WDOFF:3;\r
+ unsigned long :1;\r
+ unsigned long CSWOFF:3;\r
+ unsigned long :1;\r
+ unsigned long CSROFF:3;\r
+ } BIT;\r
+ } CS1WCR2;\r
+ char wk6[6];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short PRMOD:1;\r
+ unsigned short :5;\r
+ unsigned short PWENB:1;\r
+ unsigned short PRENB:1;\r
+ unsigned short :4;\r
+ unsigned short EWENB:1;\r
+ unsigned short :2;\r
+ unsigned short WRMOD:1;\r
+ } BIT;\r
+ } CS2MOD;\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned long :3;\r
+ unsigned long CSRWAIT:5;\r
+ unsigned long :3;\r
+ unsigned long CSWWAIT:5;\r
+ unsigned long :5;\r
+ unsigned long CSPRWAIT:3;\r
+ unsigned long :5;\r
+ unsigned long CSPWWAIT:3;\r
+ } BIT;\r
+ } CS2WCR1;\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned long :1;\r
+ unsigned long CSON:3;\r
+ unsigned long :1;\r
+ unsigned long WDON:3;\r
+ unsigned long :1;\r
+ unsigned long WRON:3;\r
+ unsigned long :1;\r
+ unsigned long RDON:3;\r
+ unsigned long :2;\r
+ unsigned long AWAIT:2;\r
+ unsigned long :1;\r
+ unsigned long WDOFF:3;\r
+ unsigned long :1;\r
+ unsigned long CSWOFF:3;\r
+ unsigned long :1;\r
+ unsigned long CSROFF:3;\r
+ } BIT;\r
+ } CS2WCR2;\r
+ char wk7[6];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short PRMOD:1;\r
+ unsigned short :5;\r
+ unsigned short PWENB:1;\r
+ unsigned short PRENB:1;\r
+ unsigned short :4;\r
+ unsigned short EWENB:1;\r
+ unsigned short :2;\r
+ unsigned short WRMOD:1;\r
+ } BIT;\r
+ } CS3MOD;\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned long :3;\r
+ unsigned long CSRWAIT:5;\r
+ unsigned long :3;\r
+ unsigned long CSWWAIT:5;\r
+ unsigned long :5;\r
+ unsigned long CSPRWAIT:3;\r
+ unsigned long :5;\r
+ unsigned long CSPWWAIT:3;\r
+ } BIT;\r
+ } CS3WCR1;\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned long :1;\r
+ unsigned long CSON:3;\r
+ unsigned long :1;\r
+ unsigned long WDON:3;\r
+ unsigned long :1;\r
+ unsigned long WRON:3;\r
+ unsigned long :1;\r
+ unsigned long RDON:3;\r
+ unsigned long :2;\r
+ unsigned long AWAIT:2;\r
+ unsigned long :1;\r
+ unsigned long WDOFF:3;\r
+ unsigned long :1;\r
+ unsigned long CSWOFF:3;\r
+ unsigned long :1;\r
+ unsigned long CSROFF:3;\r
+ } BIT;\r
+ } CS3WCR2;\r
+ char wk8[6];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short PRMOD:1;\r
+ unsigned short :5;\r
+ unsigned short PWENB:1;\r
+ unsigned short PRENB:1;\r
+ unsigned short :4;\r
+ unsigned short EWENB:1;\r
+ unsigned short :2;\r
+ unsigned short WRMOD:1;\r
+ } BIT;\r
+ } CS4MOD;\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned long :3;\r
+ unsigned long CSRWAIT:5;\r
+ unsigned long :3;\r
+ unsigned long CSWWAIT:5;\r
+ unsigned long :5;\r
+ unsigned long CSPRWAIT:3;\r
+ unsigned long :5;\r
+ unsigned long CSPWWAIT:3;\r
+ } BIT;\r
+ } CS4WCR1;\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned long :1;\r
+ unsigned long CSON:3;\r
+ unsigned long :1;\r
+ unsigned long WDON:3;\r
+ unsigned long :1;\r
+ unsigned long WRON:3;\r
+ unsigned long :1;\r
+ unsigned long RDON:3;\r
+ unsigned long :2;\r
+ unsigned long AWAIT:2;\r
+ unsigned long :1;\r
+ unsigned long WDOFF:3;\r
+ unsigned long :1;\r
+ unsigned long CSWOFF:3;\r
+ unsigned long :1;\r
+ unsigned long CSROFF:3;\r
+ } BIT;\r
+ } CS4WCR2;\r
+ char wk9[6];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short PRMOD:1;\r
+ unsigned short :5;\r
+ unsigned short PWENB:1;\r
+ unsigned short PRENB:1;\r
+ unsigned short :4;\r
+ unsigned short EWENB:1;\r
+ unsigned short :2;\r
+ unsigned short WRMOD:1;\r
+ } BIT;\r
+ } CS5MOD;\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned long :3;\r
+ unsigned long CSRWAIT:5;\r
+ unsigned long :3;\r
+ unsigned long CSWWAIT:5;\r
+ unsigned long :5;\r
+ unsigned long CSPRWAIT:3;\r
+ unsigned long :5;\r
+ unsigned long CSPWWAIT:3;\r
+ } BIT;\r
+ } CS5WCR1;\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned long :1;\r
+ unsigned long CSON:3;\r
+ unsigned long :1;\r
+ unsigned long WDON:3;\r
+ unsigned long :1;\r
+ unsigned long WRON:3;\r
+ unsigned long :1;\r
+ unsigned long RDON:3;\r
+ unsigned long :2;\r
+ unsigned long AWAIT:2;\r
+ unsigned long :1;\r
+ unsigned long WDOFF:3;\r
+ unsigned long :1;\r
+ unsigned long CSWOFF:3;\r
+ unsigned long :1;\r
+ unsigned long CSROFF:3;\r
+ } BIT;\r
+ } CS5WCR2;\r
+ char wk10[6];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short PRMOD:1;\r
+ unsigned short :5;\r
+ unsigned short PWENB:1;\r
+ unsigned short PRENB:1;\r
+ unsigned short :4;\r
+ unsigned short EWENB:1;\r
+ unsigned short :2;\r
+ unsigned short WRMOD:1;\r
+ } BIT;\r
+ } CS6MOD;\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned long :3;\r
+ unsigned long CSRWAIT:5;\r
+ unsigned long :3;\r
+ unsigned long CSWWAIT:5;\r
+ unsigned long :5;\r
+ unsigned long CSPRWAIT:3;\r
+ unsigned long :5;\r
+ unsigned long CSPWWAIT:3;\r
+ } BIT;\r
+ } CS6WCR1;\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned long :1;\r
+ unsigned long CSON:3;\r
+ unsigned long :1;\r
+ unsigned long WDON:3;\r
+ unsigned long :1;\r
+ unsigned long WRON:3;\r
+ unsigned long :1;\r
+ unsigned long RDON:3;\r
+ unsigned long :2;\r
+ unsigned long AWAIT:2;\r
+ unsigned long :1;\r
+ unsigned long WDOFF:3;\r
+ unsigned long :1;\r
+ unsigned long CSWOFF:3;\r
+ unsigned long :1;\r
+ unsigned long CSROFF:3;\r
+ } BIT;\r
+ } CS6WCR2;\r
+ char wk11[6];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short PRMOD:1;\r
+ unsigned short :5;\r
+ unsigned short PWENB:1;\r
+ unsigned short PRENB:1;\r
+ unsigned short :4;\r
+ unsigned short EWENB:1;\r
+ unsigned short :2;\r
+ unsigned short WRMOD:1;\r
+ } BIT;\r
+ } CS7MOD;\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned long :3;\r
+ unsigned long CSRWAIT:5;\r
+ unsigned long :3;\r
+ unsigned long CSWWAIT:5;\r
+ unsigned long :5;\r
+ unsigned long CSPRWAIT:3;\r
+ unsigned long :5;\r
+ unsigned long CSPWWAIT:3;\r
+ } BIT;\r
+ } CS7WCR1;\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned long :1;\r
+ unsigned long CSON:3;\r
+ unsigned long :1;\r
+ unsigned long WDON:3;\r
+ unsigned long :1;\r
+ unsigned long WRON:3;\r
+ unsigned long :1;\r
+ unsigned long RDON:3;\r
+ unsigned long :2;\r
+ unsigned long AWAIT:2;\r
+ unsigned long :1;\r
+ unsigned long WDOFF:3;\r
+ unsigned long :1;\r
+ unsigned long CSWOFF:3;\r
+ unsigned long :1;\r
+ unsigned long CSROFF:3;\r
+ } BIT;\r
+ } CS7WCR2;\r
+ char wk12[1926];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :3;\r
+ unsigned short MPXEN:1;\r
+ unsigned short :3;\r
+ unsigned short EMODE:1;\r
+ unsigned short :2;\r
+ unsigned short BSIZE:2;\r
+ unsigned short :3;\r
+ unsigned short EXENB:1;\r
+ } BIT;\r
+ } CS0CR;\r
+ char wk13[6];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :4;\r
+ unsigned short WRCV:4;\r
+ unsigned short :4;\r
+ unsigned short RRCV:4;\r
+ } BIT;\r
+ } CS0REC;\r
+ char wk14[6];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :3;\r
+ unsigned short MPXEN:1;\r
+ unsigned short :3;\r
+ unsigned short EMODE:1;\r
+ unsigned short :2;\r
+ unsigned short BSIZE:2;\r
+ unsigned short :3;\r
+ unsigned short EXENB:1;\r
+ } BIT;\r
+ } CS1CR;\r
+ char wk15[6];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :4;\r
+ unsigned short WRCV:4;\r
+ unsigned short :4;\r
+ unsigned short RRCV:4;\r
+ } BIT;\r
+ } CS1REC;\r
+ char wk16[6];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :3;\r
+ unsigned short MPXEN:1;\r
+ unsigned short :3;\r
+ unsigned short EMODE:1;\r
+ unsigned short :2;\r
+ unsigned short BSIZE:2;\r
+ unsigned short :3;\r
+ unsigned short EXENB:1;\r
+ } BIT;\r
+ } CS2CR;\r
+ char wk17[6];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :4;\r
+ unsigned short WRCV:4;\r
+ unsigned short :4;\r
+ unsigned short RRCV:4;\r
+ } BIT;\r
+ } CS2REC;\r
+ char wk18[6];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :3;\r
+ unsigned short MPXEN:1;\r
+ unsigned short :3;\r
+ unsigned short EMODE:1;\r
+ unsigned short :2;\r
+ unsigned short BSIZE:2;\r
+ unsigned short :3;\r
+ unsigned short EXENB:1;\r
+ } BIT;\r
+ } CS3CR;\r
+ char wk19[6];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :4;\r
+ unsigned short WRCV:4;\r
+ unsigned short :4;\r
+ unsigned short RRCV:4;\r
+ } BIT;\r
+ } CS3REC;\r
+ char wk20[6];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :3;\r
+ unsigned short MPXEN:1;\r
+ unsigned short :3;\r
+ unsigned short EMODE:1;\r
+ unsigned short :2;\r
+ unsigned short BSIZE:2;\r
+ unsigned short :3;\r
+ unsigned short EXENB:1;\r
+ } BIT;\r
+ } CS4CR;\r
+ char wk21[6];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :4;\r
+ unsigned short WRCV:4;\r
+ unsigned short :4;\r
+ unsigned short RRCV:4;\r
+ } BIT;\r
+ } CS4REC;\r
+ char wk22[6];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :3;\r
+ unsigned short MPXEN:1;\r
+ unsigned short :3;\r
+ unsigned short EMODE:1;\r
+ unsigned short :2;\r
+ unsigned short BSIZE:2;\r
+ unsigned short :3;\r
+ unsigned short EXENB:1;\r
+ } BIT;\r
+ } CS5CR;\r
+ char wk23[6];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :4;\r
+ unsigned short WRCV:4;\r
+ unsigned short :4;\r
+ unsigned short RRCV:4;\r
+ } BIT;\r
+ } CS5REC;\r
+ char wk24[6];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :3;\r
+ unsigned short MPXEN:1;\r
+ unsigned short :3;\r
+ unsigned short EMODE:1;\r
+ unsigned short :2;\r
+ unsigned short BSIZE:2;\r
+ unsigned short :3;\r
+ unsigned short EXENB:1;\r
+ } BIT;\r
+ } CS6CR;\r
+ char wk25[6];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :4;\r
+ unsigned short WRCV:4;\r
+ unsigned short :4;\r
+ unsigned short RRCV:4;\r
+ } BIT;\r
+ } CS6REC;\r
+ char wk26[6];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :3;\r
+ unsigned short MPXEN:1;\r
+ unsigned short :3;\r
+ unsigned short EMODE:1;\r
+ unsigned short :2;\r
+ unsigned short BSIZE:2;\r
+ unsigned short :3;\r
+ unsigned short EXENB:1;\r
+ } BIT;\r
+ } CS7CR;\r
+ char wk27[6];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :4;\r
+ unsigned short WRCV:4;\r
+ unsigned short :4;\r
+ unsigned short RRCV:4;\r
+ } BIT;\r
+ } CS7REC;\r
+ char wk28[4];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short RCVENM7:1;\r
+ unsigned short RCVENM6:1;\r
+ unsigned short RCVENM5:1;\r
+ unsigned short RCVENM4:1;\r
+ unsigned short RCVENM3:1;\r
+ unsigned short RCVENM2:1;\r
+ unsigned short RCVENM1:1;\r
+ unsigned short RCVENM0:1;\r
+ unsigned short RCVEN7:1;\r
+ unsigned short RCVEN6:1;\r
+ unsigned short RCVEN5:1;\r
+ unsigned short RCVEN4:1;\r
+ unsigned short RCVEN3:1;\r
+ unsigned short RCVEN2:1;\r
+ unsigned short RCVEN1:1;\r
+ unsigned short RCVEN0:1;\r
+ } BIT;\r
+ } CSRECEN;\r
+ char wk29[974];\r
+ unsigned char SDSR;\r
+};\r
+\r
+struct st_can {\r
+ struct {\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned short H;\r
+ unsigned short L;\r
+ } WORD;\r
+ struct {\r
+ unsigned char HH;\r
+ unsigned char HL;\r
+ unsigned char LH;\r
+ unsigned char LL;\r
+ } BYTE;\r
+ struct {\r
+ unsigned long IDE:1;\r
+ unsigned long RTR:1;\r
+ unsigned long :1;\r
+ unsigned long SID:11;\r
+ unsigned long EID:18;\r
+ } BIT;\r
+ } ID;\r
+ unsigned short DLC;\r
+ unsigned char DATA[8];\r
+ unsigned short TS;\r
+ } MB[32];\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned short H;\r
+ unsigned short L;\r
+ } WORD;\r
+ struct {\r
+ unsigned char HH;\r
+ unsigned char HL;\r
+ unsigned char LH;\r
+ unsigned char LL;\r
+ } BYTE;\r
+ struct {\r
+ unsigned long :3;\r
+ unsigned long SID:11;\r
+ unsigned long EID:18;\r
+ } BIT;\r
+ } MKR[8];\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned short H;\r
+ unsigned short L;\r
+ } WORD;\r
+ struct {\r
+ unsigned char HH;\r
+ unsigned char HL;\r
+ unsigned char LH;\r
+ unsigned char LL;\r
+ } BYTE;\r
+ struct {\r
+ unsigned long IDE:1;\r
+ unsigned long RTR:1;\r
+ unsigned long :1;\r
+ unsigned long SID:11;\r
+ unsigned long EID:18;\r
+ } BIT;\r
+ } FIDCR0;\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned short H;\r
+ unsigned short L;\r
+ } WORD;\r
+ struct {\r
+ unsigned char HH;\r
+ unsigned char HL;\r
+ unsigned char LH;\r
+ unsigned char LL;\r
+ } BYTE;\r
+ struct {\r
+ unsigned long IDE:1;\r
+ unsigned long RTR:1;\r
+ unsigned long :1;\r
+ unsigned long SID:11;\r
+ unsigned long EID:18;\r
+ } BIT;\r
+ } FIDCR1;\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned short H;\r
+ unsigned short L;\r
+ } WORD;\r
+ struct {\r
+ unsigned char HH;\r
+ unsigned char HL;\r
+ unsigned char LH;\r
+ unsigned char LL;\r
+ } BYTE;\r
+ struct {\r
+ unsigned char MB31:1;\r
+ unsigned char MB30:1;\r
+ unsigned char MB29:1;\r
+ unsigned char MB28:1;\r
+ unsigned char MB27:1;\r
+ unsigned char MB26:1;\r
+ unsigned char MB25:1;\r
+ unsigned char MB24:1;\r
+ unsigned char MB23:1;\r
+ unsigned char MB22:1;\r
+ unsigned char MB21:1;\r
+ unsigned char MB20:1;\r
+ unsigned char MB19:1;\r
+ unsigned char MB18:1;\r
+ unsigned char MB17:1;\r
+ unsigned char MB16:1;\r
+ unsigned char MB15:1;\r
+ unsigned char MB14:1;\r
+ unsigned char MB13:1;\r
+ unsigned char MB12:1;\r
+ unsigned char MB11:1;\r
+ unsigned char MB10:1;\r
+ unsigned char MB9:1;\r
+ unsigned char MB8:1;\r
+ unsigned char MB7:1;\r
+ unsigned char MB6:1;\r
+ unsigned char MB5:1;\r
+ unsigned char MB4:1;\r
+ unsigned char MB3:1;\r
+ unsigned char MB2:1;\r
+ unsigned char MB1:1;\r
+ unsigned char MB0:1;\r
+ } BIT;\r
+ } MKIVLR;\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned short H;\r
+ unsigned short L;\r
+ } WORD;\r
+ struct {\r
+ unsigned char HH;\r
+ unsigned char HL;\r
+ unsigned char LH;\r
+ unsigned char LL;\r
+ } BYTE;\r
+ struct {\r
+ unsigned char MB31:1;\r
+ unsigned char MB30:1;\r
+ unsigned char MB29:1;\r
+ unsigned char MB28:1;\r
+ unsigned char MB27:1;\r
+ unsigned char MB26:1;\r
+ unsigned char MB25:1;\r
+ unsigned char MB24:1;\r
+ unsigned char MB23:1;\r
+ unsigned char MB22:1;\r
+ unsigned char MB21:1;\r
+ unsigned char MB20:1;\r
+ unsigned char MB19:1;\r
+ unsigned char MB18:1;\r
+ unsigned char MB17:1;\r
+ unsigned char MB16:1;\r
+ unsigned char MB15:1;\r
+ unsigned char MB14:1;\r
+ unsigned char MB13:1;\r
+ unsigned char MB12:1;\r
+ unsigned char MB11:1;\r
+ unsigned char MB10:1;\r
+ unsigned char MB9:1;\r
+ unsigned char MB8:1;\r
+ unsigned char MB7:1;\r
+ unsigned char MB6:1;\r
+ unsigned char MB5:1;\r
+ unsigned char MB4:1;\r
+ unsigned char MB3:1;\r
+ unsigned char MB2:1;\r
+ unsigned char MB1:1;\r
+ unsigned char MB0:1;\r
+ } BIT;\r
+ } MIER;\r
+ char wk0[1008];\r
+ union {\r
+ unsigned char BYTE;\r
+ union {\r
+ struct {\r
+ unsigned char TRMREQ:1;\r
+ unsigned char RECREQ:1;\r
+ unsigned char :1;\r
+ unsigned char ONESHOT:1;\r
+ unsigned char :1;\r
+ unsigned char TRMABT:1;\r
+ unsigned char TRMACTIVE:1;\r
+ unsigned char SENTDATA:1;\r
+ } TX;\r
+ struct {\r
+ unsigned char TRMREQ:1;\r
+ unsigned char RECREQ:1;\r
+ unsigned char :1;\r
+ unsigned char ONESHOT:1;\r
+ unsigned char :1;\r
+ unsigned char MSGLOST:1;\r
+ unsigned char INVALDATA:1;\r
+ unsigned char NEWDATA:1;\r
+ } RX;\r
+ } BIT;\r
+ } MCTL[32];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned char H;\r
+ unsigned char L;\r
+ } BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char RBOC:1;\r
+ unsigned char BOM:2;\r
+ unsigned char SLPM:1;\r
+ unsigned char CANM:2;\r
+ unsigned char TSPS:2;\r
+ unsigned char TSRC:1;\r
+ unsigned char TPM:1;\r
+ unsigned char MLM:1;\r
+ unsigned char IDFM:2;\r
+ unsigned char MBM:1;\r
+ } BIT;\r
+ } CTLR;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned char H;\r
+ unsigned char L;\r
+ } BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char RECST:1;\r
+ unsigned char TRMST:1;\r
+ unsigned char BOST:1;\r
+ unsigned char EPST:1;\r
+ unsigned char SLPST:1;\r
+ unsigned char HLTST:1;\r
+ unsigned char RSTST:1;\r
+ unsigned char EST:1;\r
+ unsigned char TABST:1;\r
+ unsigned char FMLST:1;\r
+ unsigned char NMLST:1;\r
+ unsigned char TFST:1;\r
+ unsigned char RFST:1;\r
+ unsigned char SDST:1;\r
+ unsigned char NDST:1;\r
+ } BIT;\r
+ } STR;\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned short H;\r
+ unsigned short L;\r
+ } WORD;\r
+ struct {\r
+ unsigned char HH;\r
+ unsigned char HL;\r
+ unsigned char LH;\r
+ unsigned char LL;\r
+ } BYTE;\r
+ struct {\r
+ unsigned long TSEG1:4;\r
+ unsigned long :2;\r
+ unsigned long BRP:10;\r
+ unsigned long :2;\r
+ unsigned long SJW:2;\r
+ unsigned long :1;\r
+ unsigned long TSEG2:3;\r
+ unsigned long :7;\r
+ unsigned long CCLKS:1;\r
+ } BIT;\r
+ } BCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char RFEST:1;\r
+ unsigned char RFWST:1;\r
+ unsigned char RFFST:1;\r
+ unsigned char RFMLF:1;\r
+ unsigned char RFUST:3;\r
+ unsigned char RFE:1;\r
+ } BIT;\r
+ } RFCR;\r
+ unsigned char RFPCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TFEST:1;\r
+ unsigned char TFFST:1;\r
+ unsigned char :2;\r
+ unsigned char TFUST:3;\r
+ unsigned char TFE:1;\r
+ } BIT;\r
+ } TFCR;\r
+ unsigned char TFPCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char BLIE:1;\r
+ unsigned char OLIE:1;\r
+ unsigned char ORIE:1;\r
+ unsigned char BORIE:1;\r
+ unsigned char BOEIE:1;\r
+ unsigned char EPIE:1;\r
+ unsigned char EWIE:1;\r
+ unsigned char BEIE:1;\r
+ } BIT;\r
+ } EIER;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char BLIF:1;\r
+ unsigned char OLIF:1;\r
+ unsigned char ORIF:1;\r
+ unsigned char BORIF:1;\r
+ unsigned char BOEIF:1;\r
+ unsigned char EPIF:1;\r
+ unsigned char EWIF:1;\r
+ unsigned char BEIF:1;\r
+ } BIT;\r
+ } EIFR;\r
+ unsigned char RECR;\r
+ unsigned char TECR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char EDPM:1;\r
+ unsigned char ADEF:1;\r
+ unsigned char BE0F:1;\r
+ unsigned char BE1F:1;\r
+ unsigned char CEF:1;\r
+ unsigned char AEF:1;\r
+ unsigned char FEF:1;\r
+ unsigned char SEF:1;\r
+ } BIT;\r
+ } ECSR;\r
+ unsigned char CSSR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char SEST:1;\r
+ unsigned char :2;\r
+ unsigned char MBNST:5;\r
+ } BIT;\r
+ } MSSR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :6;\r
+ unsigned char MBSM:2;\r
+ } BIT;\r
+ } MSMR;\r
+ unsigned short TSR;\r
+ unsigned short AFSR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char TSTM:2;\r
+ unsigned char TSTE:1;\r
+ } BIT;\r
+ } TCR;\r
+};\r
+\r
+struct st_cmt {\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :14;\r
+ unsigned short STR1:1;\r
+ unsigned short STR0:1;\r
+ } BIT;\r
+ } CMSTR0;\r
+ char wk0[14];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :14;\r
+ unsigned short STR3:1;\r
+ unsigned short STR2:1;\r
+ } BIT;\r
+ } CMSTR1;\r
+};\r
+\r
+struct st_cmt0 {\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :9;\r
+ unsigned short CMIE:1;\r
+ unsigned short :4;\r
+ unsigned short CKS:2;\r
+ } BIT;\r
+ } CMCR;\r
+ unsigned short CMCNT;\r
+ unsigned short CMCOR;\r
+};\r
+\r
+struct st_crc {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char DORCLR:1;\r
+ unsigned char :4;\r
+ unsigned char LMS:1;\r
+ unsigned char GPS:2;\r
+ } BIT;\r
+ } CRCCR;\r
+ unsigned char CRCDIR;\r
+ unsigned short CRCDOR;\r
+};\r
+\r
+struct st_da {\r
+ unsigned short DADR0;\r
+ unsigned short DADR1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char DAOE1:1;\r
+ unsigned char DAOE0:1;\r
+ unsigned char DAE:1;\r
+ } BIT;\r
+ } DACR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char DPSEL:1;\r
+ } BIT;\r
+ } DADPR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char DAADST:1;\r
+ } BIT;\r
+ } DAADSCR;\r
+};\r
+\r
+struct st_dmac {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char DMST:1;\r
+ } BIT;\r
+ } DMAST;\r
+};\r
+\r
+struct st_dmac0 {\r
+ unsigned long DMSAR;\r
+ unsigned long DMDAR;\r
+ unsigned long DMCRA;\r
+ unsigned short DMCRB;\r
+ char wk0[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short MD:2;\r
+ unsigned short DTS:2;\r
+ unsigned short :2;\r
+ unsigned short SZ:2;\r
+ unsigned short :6;\r
+ unsigned short DCTG:2;\r
+ } BIT;\r
+ } DMTMD;\r
+ char wk1[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char DTIE:1;\r
+ unsigned char ESIE:1;\r
+ unsigned char RPTIE:1;\r
+ unsigned char SARIE:1;\r
+ unsigned char DARIE:1;\r
+ } BIT;\r
+ } DMINT;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short SM:2;\r
+ unsigned short :1;\r
+ unsigned short SARA:5;\r
+ unsigned short DM:2;\r
+ unsigned short :1;\r
+ unsigned short DARA:5;\r
+ } BIT;\r
+ } DMAMD;\r
+ char wk2[2];\r
+ unsigned long DMOFR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char DTE:1;\r
+ } BIT;\r
+ } DMCNT;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char CLRS:1;\r
+ unsigned char :3;\r
+ unsigned char SWREQ:1;\r
+ } BIT;\r
+ } DMREQ;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ACT:1;\r
+ unsigned char :2;\r
+ unsigned char DTIF:1;\r
+ unsigned char :3;\r
+ unsigned char ESIF:1;\r
+ } BIT;\r
+ } DMSTS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char DISEL:1;\r
+ } BIT;\r
+ } DMCSL;\r
+};\r
+\r
+struct st_dmac1 {\r
+ unsigned long DMSAR;\r
+ unsigned long DMDAR;\r
+ unsigned long DMCRA;\r
+ unsigned short DMCRB;\r
+ char wk0[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short MD:2;\r
+ unsigned short DTS:2;\r
+ unsigned short :2;\r
+ unsigned short SZ:2;\r
+ unsigned short :6;\r
+ unsigned short DCTG:2;\r
+ } BIT;\r
+ } DMTMD;\r
+ char wk1[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char DTIE:1;\r
+ unsigned char ESIE:1;\r
+ unsigned char RPTIE:1;\r
+ unsigned char SARIE:1;\r
+ unsigned char DARIE:1;\r
+ } BIT;\r
+ } DMINT;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short SM:2;\r
+ unsigned short :1;\r
+ unsigned short SARA:5;\r
+ unsigned short DM:2;\r
+ unsigned short :1;\r
+ unsigned short DARA:5;\r
+ } BIT;\r
+ } DMAMD;\r
+ char wk2[6];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char DTE:1;\r
+ } BIT;\r
+ } DMCNT;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char CLRS:1;\r
+ unsigned char :3;\r
+ unsigned char SWREQ:1;\r
+ } BIT;\r
+ } DMREQ;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ACT:1;\r
+ unsigned char :2;\r
+ unsigned char DTIF:1;\r
+ unsigned char :3;\r
+ unsigned char ESIF:1;\r
+ } BIT;\r
+ } DMSTS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char DISEL:1;\r
+ } BIT;\r
+ } DMCSL;\r
+};\r
+\r
+struct st_dtc {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char RRS:1;\r
+ } BIT;\r
+ } DTCCR;\r
+ char wk0[3];\r
+ unsigned long DTCVBR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char SHORT:1;\r
+ } BIT;\r
+ } DTCADMOD;\r
+ char wk1[3];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char DTCST:1;\r
+ } BIT;\r
+ } DTCST;\r
+ char wk2[1];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short ACT:1;\r
+ unsigned short :7;\r
+ unsigned short VECN:8;\r
+ } BIT;\r
+ } DTCSTS;\r
+};\r
+\r
+struct st_flash {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :6;\r
+ unsigned char FLWE:2;\r
+ } BIT;\r
+ } FWEPROR;\r
+ char wk0[7799147];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char FRDMD:1;\r
+ } BIT;\r
+ } FMODR;\r
+ char wk1[13];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ROMAE:1;\r
+ unsigned char :2;\r
+ unsigned char CMDLK:1;\r
+ unsigned char DFLAE:1;\r
+ unsigned char :1;\r
+ unsigned char DFLRPE:1;\r
+ unsigned char DFLWPE:1;\r
+ } BIT;\r
+ } FASTAT;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ROMAEIE:1;\r
+ unsigned char :2;\r
+ unsigned char CMDLKIE:1;\r
+ unsigned char DFLAEIE:1;\r
+ unsigned char :1;\r
+ unsigned char DFLRPEIE:1;\r
+ unsigned char DFLWPEIE:1;\r
+ } BIT;\r
+ } FAEINT;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char FRDYIE:1;\r
+ } BIT;\r
+ } FRDYIE;\r
+ char wk2[45];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short KEY:8;\r
+ unsigned short DBRE07:1;\r
+ unsigned short DBRE06:1;\r
+ unsigned short DBRE05:1;\r
+ unsigned short DBRE04:1;\r
+ unsigned short DBRE03:1;\r
+ unsigned short DBRE02:1;\r
+ unsigned short DBRE01:1;\r
+ unsigned short DBRE00:1;\r
+ } BIT;\r
+ } DFLRE0;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short KEY:8;\r
+ unsigned short DBRE15:1;\r
+ unsigned short DBRE14:1;\r
+ unsigned short DBRE13:1;\r
+ unsigned short DBRE12:1;\r
+ unsigned short DBRE11:1;\r
+ unsigned short DBRE10:1;\r
+ unsigned short DBRE09:1;\r
+ unsigned short DBRE08:1;\r
+ } BIT;\r
+ } DFLRE1;\r
+ char wk3[12];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short KEY:8;\r
+ unsigned short DBWE07:1;\r
+ unsigned short DBW006:1;\r
+ unsigned short DBWE05:1;\r
+ unsigned short DBWE04:1;\r
+ unsigned short DBWE03:1;\r
+ unsigned short DBWE02:1;\r
+ unsigned short DBWE01:1;\r
+ unsigned short DBWE00:1;\r
+ } BIT;\r
+ } DFLWE0;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short KEY:8;\r
+ unsigned short DBWE15:1;\r
+ unsigned short DBWE14:1;\r
+ unsigned short DBWE13:1;\r
+ unsigned short DBWE12:1;\r
+ unsigned short DBWE11:1;\r
+ unsigned short DBWE10:1;\r
+ unsigned short DBWE09:1;\r
+ unsigned short DBWE08:1;\r
+ } BIT;\r
+ } DFLWE1;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short KEY:8;\r
+ unsigned short :7;\r
+ unsigned short FCRME:1;\r
+ } BIT;\r
+ } FCURAME;\r
+ char wk4[15194];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char FRDY:1;\r
+ unsigned char ILGLERR:1;\r
+ unsigned char ERSERR:1;\r
+ unsigned char PRGERR:1;\r
+ unsigned char SUSRDY:1;\r
+ unsigned char :1;\r
+ unsigned char ERSSPD:1;\r
+ unsigned char PRGSPD:1;\r
+ } BIT;\r
+ } FSTATR0;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char FCUERR:1;\r
+ unsigned char :2;\r
+ unsigned char FLOCKST:1;\r
+ } BIT;\r
+ } FSTATR1;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short FEKEY:8;\r
+ unsigned short FENTRYD:1;\r
+ unsigned short :3;\r
+ unsigned short FENTRY3:1;\r
+ unsigned short FENTRY2:1;\r
+ unsigned short FENTRY1:1;\r
+ unsigned short FENTRY0:1;\r
+ } BIT;\r
+ } FENTRYR;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short FPKEY:8;\r
+ unsigned short :7;\r
+ unsigned short FPROTCN:1;\r
+ } BIT;\r
+ } FPROTR;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short FRKEY:8;\r
+ unsigned short :7;\r
+ unsigned short FRESET:1;\r
+ } BIT;\r
+ } FRESETR;\r
+ char wk5[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short CMDR:8;\r
+ unsigned short PCMDR:8;\r
+ } BIT;\r
+ } FCMDR;\r
+ char wk6[12];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :15;\r
+ unsigned short ESUSPMD:1;\r
+ } BIT;\r
+ } FCPSR;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short BCSIZE:1;\r
+ unsigned short :4;\r
+ unsigned short BCADR:11;\r
+ } BIT;\r
+ } DFLBCCNT;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :8;\r
+ unsigned short PEERRST:8;\r
+ } BIT;\r
+ } FPESTAT;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :15;\r
+ unsigned short BCST:1;\r
+ } BIT;\r
+ } DFLBCSTAT;\r
+ char wk7[24];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :8;\r
+ unsigned short PCKA:8;\r
+ } BIT;\r
+ } PCKAR;\r
+};\r
+\r
+struct st_icu {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char IR:1;\r
+ } BIT;\r
+ } IR[254];\r
+ char wk0[2];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char DTCE:1;\r
+ } BIT;\r
+ } DTCER[252];\r
+ char wk1[4];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char IEN7:1;\r
+ unsigned char IEN6:1;\r
+ unsigned char IEN5:1;\r
+ unsigned char IEN4:1;\r
+ unsigned char IEN3:1;\r
+ unsigned char IEN2:1;\r
+ unsigned char IEN1:1;\r
+ unsigned char IEN0:1;\r
+ } BIT;\r
+ } IER[32];\r
+ char wk2[192];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char SWINT:1;\r
+ } BIT;\r
+ } SWINTR;\r
+ char wk3[15];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short FIEN:1;\r
+ unsigned short :7;\r
+ unsigned short FVCT:8;\r
+ } BIT;\r
+ } FIR;\r
+ char wk4[14];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :4;\r
+ unsigned char IPR:4;\r
+ } BIT;\r
+ } IPR[254];\r
+ char wk5[2];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char DMRS:8;\r
+ } BIT;\r
+ } DMRSR0;\r
+ char wk6[3];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char DMRS:8;\r
+ } BIT;\r
+ } DMRSR1;\r
+ char wk7[3];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char DMRS:8;\r
+ } BIT;\r
+ } DMRSR2;\r
+ char wk8[3];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char DMRS:8;\r
+ } BIT;\r
+ } DMRSR3;\r
+ char wk9[243];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :4;\r
+ unsigned char IRQMD:2;\r
+ } BIT;\r
+ } IRQCR[16];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char FLTEN7:1;\r
+ unsigned char FLTEN6:1;\r
+ unsigned char FLTEN5:1;\r
+ unsigned char FLTEN4:1;\r
+ unsigned char FLTEN3:1;\r
+ unsigned char FLTEN2:1;\r
+ unsigned char FLTEN1:1;\r
+ unsigned char FLTEN0:1;\r
+ } BIT;\r
+ } IRQFLTE0;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char FLTEN15:1;\r
+ unsigned char FLTEN14:1;\r
+ unsigned char FLTEN13:1;\r
+ unsigned char FLTEN12:1;\r
+ unsigned char FLTEN11:1;\r
+ unsigned char FLTEN10:1;\r
+ unsigned char FLTEN9:1;\r
+ unsigned char FLTEN8:1;\r
+ } BIT;\r
+ } IRQFLTE1;\r
+ char wk10[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short FCLKSEL7:2;\r
+ unsigned short FCLKSEL6:2;\r
+ unsigned short FCLKSEL5:2;\r
+ unsigned short FCLKSEL4:2;\r
+ unsigned short FCLKSEL3:2;\r
+ unsigned short FCLKSEL2:2;\r
+ unsigned short FCLKSEL1:2;\r
+ unsigned short FCLKSEL0:2;\r
+ } BIT;\r
+ } IRQFLTC0;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short FCLKSEL15:2;\r
+ unsigned short FCLKSEL14:2;\r
+ unsigned short FCLKSEL13:2;\r
+ unsigned short FCLKSEL12:2;\r
+ unsigned short FCLKSEL11:2;\r
+ unsigned short FCLKSEL10:2;\r
+ unsigned short FCLKSEL9:2;\r
+ unsigned short FCLKSEL8:2;\r
+ } BIT;\r
+ } IRQFLTC1;\r
+ char wk11[104];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char LVD2ST:1;\r
+ unsigned char LVD1ST:1;\r
+ unsigned char IWDTST:1;\r
+ unsigned char WDTST:1;\r
+ unsigned char OSTST:1;\r
+ unsigned char NMIST:1;\r
+ } BIT;\r
+ } NMISR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char LVD2EN:1;\r
+ unsigned char LVD1EN:1;\r
+ unsigned char IWDTEN:1;\r
+ unsigned char WDTEN:1;\r
+ unsigned char OSTEN:1;\r
+ unsigned char NMIEN:1;\r
+ } BIT;\r
+ } NMIER;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char LVD2CLR:1;\r
+ unsigned char LVD1CLR:1;\r
+ unsigned char IWDTCLR:1;\r
+ unsigned char WDTCLR:1;\r
+ unsigned char OSTCLR:1;\r
+ unsigned char NMICLR:1;\r
+ } BIT;\r
+ } NMICLR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :4;\r
+ unsigned char NMIMD:1;\r
+ } BIT;\r
+ } NMICR;\r
+ char wk12[12];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char NFLTEN:1;\r
+ } BIT;\r
+ } NMIFLTE;\r
+ char wk13[3];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :6;\r
+ unsigned char NFCLKSEL:2;\r
+ } BIT;\r
+ } NMIFLTC;\r
+ char wk14[19819];\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned long :16;\r
+ unsigned long IS15:1;\r
+ unsigned long IS14:1;\r
+ unsigned long IS13:1;\r
+ unsigned long IS12:1;\r
+ unsigned long IS11:1;\r
+ unsigned long IS10:1;\r
+ unsigned long IS9:1;\r
+ unsigned long IS8:1;\r
+ unsigned long IS7:1;\r
+ unsigned long IS6:1;\r
+ unsigned long IS5:1;\r
+ unsigned long IS4:1;\r
+ unsigned long IS3:1;\r
+ unsigned long IS2:1;\r
+ unsigned long IS1:1;\r
+ unsigned long IS0:1;\r
+ } BIT;\r
+ } GRP[13];\r
+ char wk15[12];\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned long :16;\r
+ unsigned long EN15:1;\r
+ unsigned long EN14:1;\r
+ unsigned long EN13:1;\r
+ unsigned long EN12:1;\r
+ unsigned long EN11:1;\r
+ unsigned long EN10:1;\r
+ unsigned long EN9:1;\r
+ unsigned long EN8:1;\r
+ unsigned long EN7:1;\r
+ unsigned long EN6:1;\r
+ unsigned long EN5:1;\r
+ unsigned long EN4:1;\r
+ unsigned long EN3:1;\r
+ unsigned long EN2:1;\r
+ unsigned long EN1:1;\r
+ unsigned long EN0:1;\r
+ } BIT;\r
+ } GEN[13];\r
+ char wk16[12];\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned long :16;\r
+ unsigned long CLR15:1;\r
+ unsigned long CLR14:1;\r
+ unsigned long CLR13:1;\r
+ unsigned long CLR12:1;\r
+ unsigned long CLR11:1;\r
+ unsigned long CLR10:1;\r
+ unsigned long CLR9:1;\r
+ unsigned long CLR8:1;\r
+ unsigned long CLR7:1;\r
+ unsigned long CLR6:1;\r
+ unsigned long CLR5:1;\r
+ unsigned long CLR4:1;\r
+ unsigned long CLR3:1;\r
+ unsigned long CLR2:1;\r
+ unsigned long CLR1:1;\r
+ unsigned long CLR0:1;\r
+ } BIT;\r
+ } GCR[13];\r
+ char wk17[12];\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned long :26;\r
+ unsigned long CN5:1;\r
+ unsigned long CN4:1;\r
+ unsigned long CN3:1;\r
+ unsigned long CN2:1;\r
+ unsigned long CN1:1;\r
+ unsigned long CN0:1;\r
+ } BIT;\r
+ } SEL;\r
+};\r
+\r
+struct st_ieb {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char IOL:1;\r
+ unsigned char DEE:1;\r
+ unsigned char :1;\r
+ unsigned char RE:1;\r
+ } BIT;\r
+ } IECTR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char CMD:3;\r
+ } BIT;\r
+ } IECMR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char SS:1;\r
+ unsigned char RN:3;\r
+ unsigned char CTL:4;\r
+ } BIT;\r
+ } IEMCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char IARL4:4;\r
+ unsigned char IMD:2;\r
+ unsigned char :1;\r
+ unsigned char STE:1;\r
+ } BIT;\r
+ } IEAR1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char IARU8:8;\r
+ } BIT;\r
+ } IEAR2;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ISAL4:4;\r
+ } BIT;\r
+ } IESA1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ISAU8:8;\r
+ } BIT;\r
+ } IESA2;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char IBFL:8;\r
+ } BIT;\r
+ } IETBFL;\r
+ char wk0[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ISAL4:4;\r
+ } BIT;\r
+ } IEMA1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char IMAU8:8;\r
+ } BIT;\r
+ } IEMA2;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :4;\r
+ unsigned char RCTL:4;\r
+ } BIT;\r
+ } IERCTL;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char RBFL:8;\r
+ } BIT;\r
+ } IERBFL;\r
+ char wk1[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ILAL8:8;\r
+ } BIT;\r
+ } IELA1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :4;\r
+ unsigned char ILAU4:4;\r
+ } BIT;\r
+ } IELA2;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char CMX:1;\r
+ unsigned char MRQ:1;\r
+ unsigned char SRQ:1;\r
+ unsigned char SRE:1;\r
+ unsigned char LCK:1;\r
+ unsigned char :1;\r
+ unsigned char RSS:1;\r
+ unsigned char GG:1;\r
+ } BIT;\r
+ } IEFLG;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char TXS:1;\r
+ unsigned char TXF:1;\r
+ unsigned char :1;\r
+ unsigned char TXEAL:1;\r
+ unsigned char TXETTME:1;\r
+ unsigned char TXERO:1;\r
+ unsigned char TXEACK:1;\r
+ } BIT;\r
+ } IETSR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char TXSE:1;\r
+ unsigned char TXFE:1;\r
+ unsigned char :1;\r
+ unsigned char TXEALE:1;\r
+ unsigned char TXETTMEE:1;\r
+ unsigned char TXEROE:1;\r
+ unsigned char TXEACKE:1;\r
+ } BIT;\r
+ } IEIET;\r
+ char wk2[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char RXBSY:1;\r
+ unsigned char RXS:1;\r
+ unsigned char RXF:1;\r
+ unsigned char RXEDE:1;\r
+ unsigned char RXEOVE:1;\r
+ unsigned char RXERTME:1;\r
+ unsigned char RXEDLE:1;\r
+ unsigned char RXEPE:1;\r
+ } BIT;\r
+ } IERSR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char RXBSYE:1;\r
+ unsigned char RXSE:1;\r
+ unsigned char RXFE:1;\r
+ unsigned char RXEDEE:1;\r
+ unsigned char RXEOVEE:1;\r
+ unsigned char RXERTMEE:1;\r
+ unsigned char RXEDLEE:1;\r
+ unsigned char RXEPEE:1;\r
+ } BIT;\r
+ } IEIER;\r
+ char wk3[2];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char FLT:1;\r
+ unsigned char FCKS:2;\r
+ unsigned char CKS3:1;\r
+ unsigned char SRSTP:1;\r
+ unsigned char CKS:3;\r
+ } BIT;\r
+ } IECKSR;\r
+ char wk4[230];\r
+ unsigned char IETB[33];\r
+ char wk5[223];\r
+ unsigned char IERB[33];\r
+};\r
+\r
+struct st_iwdt {\r
+ unsigned char IWDTRR;\r
+ char wk0[1];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :2;\r
+ unsigned short RPSS:2;\r
+ unsigned short :2;\r
+ unsigned short RPES:2;\r
+ unsigned short CKS:4;\r
+ unsigned short :2;\r
+ unsigned short TOPS:2;\r
+ } BIT;\r
+ } IWDTCR;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short REFEF:1;\r
+ unsigned short UNDFF:1;\r
+ unsigned short CNTVAL:14;\r
+ } BIT;\r
+ } IWDTSR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char RSTIRQS:1;\r
+ } BIT;\r
+ } IWDTRCR;\r
+ char wk1[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char SLCSTP:1;\r
+ } BIT;\r
+ } IWDTCSTPR;\r
+};\r
+\r
+struct st_mpc {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char CS7E:1;\r
+ unsigned char CS6E:1;\r
+ unsigned char CS5E:1;\r
+ unsigned char CS4E:1;\r
+ unsigned char CS3E:1;\r
+ unsigned char CS2E:1;\r
+ unsigned char CS1E:1;\r
+ unsigned char CS0E:1;\r
+ } BIT;\r
+ } PFCSE;\r
+ char wk0[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char CS3S:2;\r
+ unsigned char CS2S:2;\r
+ unsigned char CS1S:2;\r
+ unsigned char :1;\r
+ unsigned char CS0S:1;\r
+ } BIT;\r
+ } PFCSS0;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char CS7S:2;\r
+ unsigned char CS6S:2;\r
+ unsigned char CS5S:2;\r
+ unsigned char CS4S:2;\r
+ } BIT;\r
+ } PFCSS1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char A15E:1;\r
+ unsigned char A14E:1;\r
+ unsigned char A13E:1;\r
+ unsigned char A12E:1;\r
+ unsigned char A11E:1;\r
+ unsigned char A10E:1;\r
+ unsigned char A9E:1;\r
+ unsigned char A8E:1;\r
+ } BIT;\r
+ } PFAOE0;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char A23E:1;\r
+ unsigned char A22E:1;\r
+ unsigned char A21E:1;\r
+ unsigned char A20E:1;\r
+ unsigned char A19E:1;\r
+ unsigned char A18E:1;\r
+ unsigned char A17E:1;\r
+ unsigned char A16E:1;\r
+ } BIT;\r
+ } PFAOE1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char WR32BC32E:1;\r
+ unsigned char WR1BC1E:1;\r
+ unsigned char DH32E:1;\r
+ unsigned char DHE:1;\r
+ unsigned char :2;\r
+ unsigned char ADRHMS:1;\r
+ unsigned char ADRLE:1;\r
+ } BIT;\r
+ } PFBCR0;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char ALEOE:1;\r
+ unsigned char WAITS:2;\r
+ } BIT;\r
+ } PFBCR1;\r
+ char wk1[12];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char PUPHZS:1;\r
+ } BIT;\r
+ } PFUSB0;\r
+ char wk2[10];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B0WI:1;\r
+ unsigned char PFSWE:1;\r
+ } BIT;\r
+ } PWPR;\r
+ char wk3[32];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ASEL:1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } P00PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ASEL:1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } P01PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ASEL:1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } P02PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ASEL:1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } P03PFS;\r
+ char wk4[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ASEL:1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } P05PFS;\r
+ char wk5[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } P07PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } P10PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } P11PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } P12PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } P13PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } P14PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } P15PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } P16PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } P17PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } P20PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } P21PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } P22PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } P23PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } P24PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } P25PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } P26PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } P27PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } P30PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } P31PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } P32PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } P33PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } P34PFS;\r
+ char wk6[3];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ASEL:1;\r
+ unsigned char ISEL:1;\r
+ } BIT;\r
+ } P40PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ASEL:1;\r
+ unsigned char ISEL:1;\r
+ } BIT;\r
+ } P41PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ASEL:1;\r
+ unsigned char ISEL:1;\r
+ } BIT;\r
+ } P42PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ASEL:1;\r
+ unsigned char ISEL:1;\r
+ } BIT;\r
+ } P43PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ASEL:1;\r
+ unsigned char ISEL:1;\r
+ } BIT;\r
+ } P44PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ASEL:1;\r
+ unsigned char ISEL:1;\r
+ } BIT;\r
+ } P45PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ASEL:1;\r
+ unsigned char ISEL:1;\r
+ } BIT;\r
+ } P46PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ASEL:1;\r
+ unsigned char ISEL:1;\r
+ } BIT;\r
+ } P47PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } P50PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } P51PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } P52PFS;\r
+ char wk7[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } P54PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } P55PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } P56PFS;\r
+ char wk8[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } P60PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } P61PFS;\r
+ char wk9[4];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } P66PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } P67PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } P70PFS;\r
+ char wk10[2];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } P73PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } P74PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } P75PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } P76PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } P77PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } P80PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } P81PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } P82PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } P83PFS;\r
+ char wk11[2];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } P86PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } P87PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ASEL:1;\r
+ unsigned char :2;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } P90PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ASEL:1;\r
+ unsigned char :2;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } P91PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ASEL:1;\r
+ unsigned char :2;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } P92PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ASEL:1;\r
+ unsigned char :2;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } P93PFS;\r
+ char wk12[4];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PA0PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PA1PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PA2PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PA3PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PA4PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PA5PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PA6PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PA7PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PB0PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PB1PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PB2PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PB3PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PB4PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PB5PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PB6PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PB7PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PC0PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PC1PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PC2PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PC3PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PC4PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PC5PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PC6PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PC7PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ASEL:1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PD0PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ASEL:1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PD1PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ASEL:1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PD2PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ASEL:1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PD3PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ASEL:1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PD4PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ASEL:1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PD5PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ASEL:1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PD6PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ASEL:1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PD7PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ASEL:1;\r
+ unsigned char :2;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PE0PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ASEL:1;\r
+ unsigned char :2;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PE1PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ASEL:1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PE2PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ASEL:1;\r
+ unsigned char :2;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PE3PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ASEL:1;\r
+ unsigned char :2;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PE4PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ASEL:1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PE5PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ASEL:1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PE6PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ASEL:1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PE7PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PF0PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PF1PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PF2PFS;\r
+ char wk13[2];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PF5PFS;\r
+ char wk14[21];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PJ3PFS;\r
+ char wk15[6];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PK2PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PK3PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PK4PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PK5PFS;\r
+};\r
+\r
+struct st_mtu {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char OE4D:1;\r
+ unsigned char OE4C:1;\r
+ unsigned char OE3D:1;\r
+ unsigned char OE4B:1;\r
+ unsigned char OE4A:1;\r
+ unsigned char OE3B:1;\r
+ } BIT;\r
+ } TOER;\r
+ char wk0[2];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char BDC:1;\r
+ unsigned char N:1;\r
+ unsigned char P:1;\r
+ unsigned char FB:1;\r
+ unsigned char WF:1;\r
+ unsigned char VF:1;\r
+ unsigned char UF:1;\r
+ } BIT;\r
+ } TGCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char PSYE:1;\r
+ unsigned char :2;\r
+ unsigned char TOCL:1;\r
+ unsigned char TOCS:1;\r
+ unsigned char OLSN:1;\r
+ unsigned char OLSP:1;\r
+ } BIT;\r
+ } TOCR1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char BF:2;\r
+ unsigned char OLS3N:1;\r
+ unsigned char OLS3P:1;\r
+ unsigned char OLS2N:1;\r
+ unsigned char OLS2P:1;\r
+ unsigned char OLS1N:1;\r
+ unsigned char OLS1P:1;\r
+ } BIT;\r
+ } TOCR2;\r
+ char wk1[4];\r
+ unsigned short TCDR;\r
+ unsigned short TDDR;\r
+ char wk2[8];\r
+ unsigned short TCNTS;\r
+ unsigned short TCBR;\r
+ char wk3[12];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char T3AEN:1;\r
+ unsigned char T3ACOR:3;\r
+ unsigned char T4VEN:1;\r
+ unsigned char T4VCOR:3;\r
+ } BIT;\r
+ } TITCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char T3ACNT:3;\r
+ unsigned char :1;\r
+ unsigned char T4VCNT:3;\r
+ } BIT;\r
+ } TITCNT;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :6;\r
+ unsigned char BTE:2;\r
+ } BIT;\r
+ } TBTER;\r
+ char wk4[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char TDER:1;\r
+ } BIT;\r
+ } TDER;\r
+ char wk5[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char OLS3N:1;\r
+ unsigned char OLS3P:1;\r
+ unsigned char OLS2N:1;\r
+ unsigned char OLS2P:1;\r
+ unsigned char OLS1N:1;\r
+ unsigned char OLS1P:1;\r
+ } BIT;\r
+ } TOLBR;\r
+ char wk6[41];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char CCE:1;\r
+ unsigned char :6;\r
+ unsigned char WRE:1;\r
+ } BIT;\r
+ } TWCR;\r
+ char wk7[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char CST4:1;\r
+ unsigned char CST3:1;\r
+ unsigned char :3;\r
+ unsigned char CST2:1;\r
+ unsigned char CST1:1;\r
+ unsigned char CST0:1;\r
+ } BIT;\r
+ } TSTR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char SYNC4:1;\r
+ unsigned char SYNC3:1;\r
+ unsigned char :3;\r
+ unsigned char SYNC2:1;\r
+ unsigned char SYNC1:1;\r
+ unsigned char SYNC0:1;\r
+ } BIT;\r
+ } TSYR;\r
+ char wk8[2];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char RWE:1;\r
+ } BIT;\r
+ } TRWER;\r
+};\r
+\r
+struct st_mtu0 {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char NFCS:2;\r
+ unsigned char NFDEN:1;\r
+ unsigned char NFCEN:1;\r
+ unsigned char NFBEN:1;\r
+ unsigned char NFAEN:1;\r
+ } BIT;\r
+ } NFCR;\r
+ char wk0[111];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char CCLR:3;\r
+ unsigned char CKEG:2;\r
+ unsigned char TPSC:3;\r
+ } BIT;\r
+ } TCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char BFE:1;\r
+ unsigned char BFB:1;\r
+ unsigned char BFA:1;\r
+ unsigned char MD:4;\r
+ } BIT;\r
+ } TMDR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char IOB:4;\r
+ unsigned char IOA:4;\r
+ } BIT;\r
+ } TIORH;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char IOD:4;\r
+ unsigned char IOC:4;\r
+ } BIT;\r
+ } TIORL;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TTGE:1;\r
+ unsigned char :2;\r
+ unsigned char TCIEV:1;\r
+ unsigned char TGIED:1;\r
+ unsigned char TGIEC:1;\r
+ unsigned char TGIEB:1;\r
+ unsigned char TGIEA:1;\r
+ } BIT;\r
+ } TIER;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TCFD:1;\r
+ } BIT;\r
+ } TSR;\r
+ unsigned short TCNT;\r
+ unsigned short TGRA;\r
+ unsigned short TGRB;\r
+ unsigned short TGRC;\r
+ unsigned short TGRD;\r
+ char wk1[16];\r
+ unsigned short TGRE;\r
+ unsigned short TGRF;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :6;\r
+ unsigned char TGIEF:1;\r
+ unsigned char TGIEE:1;\r
+ } BIT;\r
+ } TIER2;\r
+ char wk2[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char TTSE:1;\r
+ unsigned char TTSB:1;\r
+ unsigned char TTSA:1;\r
+ } BIT;\r
+ } TBTM;\r
+};\r
+\r
+struct st_mtu1 {\r
+ char wk0[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char NFCS:2;\r
+ unsigned char NFDEN:1;\r
+ unsigned char NFCEN:1;\r
+ unsigned char NFBEN:1;\r
+ unsigned char NFAEN:1;\r
+ } BIT;\r
+ } NFCR;\r
+ char wk1[238];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char CCLR:2;\r
+ unsigned char CKEG:2;\r
+ unsigned char TPSC:3;\r
+ } BIT;\r
+ } TCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :4;\r
+ unsigned char MD:4;\r
+ } BIT;\r
+ } TMDR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char IOB:4;\r
+ unsigned char IOA:4;\r
+ } BIT;\r
+ } TIOR;\r
+ char wk2[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TTGE:1;\r
+ unsigned char :1;\r
+ unsigned char TCIEU:1;\r
+ unsigned char TCIEV:1;\r
+ unsigned char :2;\r
+ unsigned char TGIEB:1;\r
+ unsigned char TGIEA:1;\r
+ } BIT;\r
+ } TIER;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TCFD:1;\r
+ } BIT;\r
+ } TSR;\r
+ unsigned short TCNT;\r
+ unsigned short TGRA;\r
+ unsigned short TGRB;\r
+ char wk3[4];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :4;\r
+ unsigned char I2BE:1;\r
+ unsigned char I2AE:1;\r
+ unsigned char I1BE:1;\r
+ unsigned char I1AE:1;\r
+ } BIT;\r
+ } TICCR;\r
+};\r
+\r
+struct st_mtu2 {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char NFCS:2;\r
+ unsigned char NFDEN:1;\r
+ unsigned char NFCEN:1;\r
+ unsigned char NFBEN:1;\r
+ unsigned char NFAEN:1;\r
+ } BIT;\r
+ } NFCR;\r
+ char wk0[365];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char CCLR:2;\r
+ unsigned char CKEG:2;\r
+ unsigned char TPSC:3;\r
+ } BIT;\r
+ } TCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :4;\r
+ unsigned char MD:4;\r
+ } BIT;\r
+ } TMDR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char IOB:4;\r
+ unsigned char IOA:4;\r
+ } BIT;\r
+ } TIOR;\r
+ char wk1[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TTGE:1;\r
+ unsigned char :1;\r
+ unsigned char TCIEU:1;\r
+ unsigned char TCIEV:1;\r
+ unsigned char :2;\r
+ unsigned char TGIEB:1;\r
+ unsigned char TGIEA:1;\r
+ } BIT;\r
+ } TIER;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TCFD:1;\r
+ } BIT;\r
+ } TSR;\r
+ unsigned short TCNT;\r
+ unsigned short TGRA;\r
+ unsigned short TGRB;\r
+};\r
+\r
+struct st_mtu3 {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char CCLR:3;\r
+ unsigned char CKEG:2;\r
+ unsigned char TPSC:3;\r
+ } BIT;\r
+ } TCR;\r
+ char wk0[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char BFB:1;\r
+ unsigned char BFA:1;\r
+ unsigned char MD:4;\r
+ } BIT;\r
+ } TMDR;\r
+ char wk1[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char IOB:4;\r
+ unsigned char IOA:4;\r
+ } BIT;\r
+ } TIORH;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char IOD:4;\r
+ unsigned char IOC:4;\r
+ } BIT;\r
+ } TIORL;\r
+ char wk2[2];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TTGE:1;\r
+ unsigned char :2;\r
+ unsigned char TCIEV:1;\r
+ unsigned char TGIED:1;\r
+ unsigned char TGIEC:1;\r
+ unsigned char TGIEB:1;\r
+ unsigned char TGIEA:1;\r
+ } BIT;\r
+ } TIER;\r
+ char wk3[7];\r
+ unsigned short TCNT;\r
+ char wk4[6];\r
+ unsigned short TGRA;\r
+ unsigned short TGRB;\r
+ char wk5[8];\r
+ unsigned short TGRC;\r
+ unsigned short TGRD;\r
+ char wk6[4];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TCFD:1;\r
+ } BIT;\r
+ } TSR;\r
+ char wk7[11];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char TTSE:1;\r
+ unsigned char TTSB:1;\r
+ unsigned char TTSA:1;\r
+ } BIT;\r
+ } TBTM;\r
+ char wk8[90];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char NFCS:2;\r
+ unsigned char NFDEN:1;\r
+ unsigned char NFCEN:1;\r
+ unsigned char NFBEN:1;\r
+ unsigned char NFAEN:1;\r
+ } BIT;\r
+ } NFCR;\r
+};\r
+\r
+struct st_mtu4 {\r
+ char wk0[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char CCLR:3;\r
+ unsigned char CKEG:2;\r
+ unsigned char TPSC:3;\r
+ } BIT;\r
+ } TCR;\r
+ char wk1[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char BFB:1;\r
+ unsigned char BFA:1;\r
+ unsigned char MD:4;\r
+ } BIT;\r
+ } TMDR;\r
+ char wk2[2];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char IOB:4;\r
+ unsigned char IOA:4;\r
+ } BIT;\r
+ } TIORH;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char IOD:4;\r
+ unsigned char IOC:4;\r
+ } BIT;\r
+ } TIORL;\r
+ char wk3[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TTGE:1;\r
+ unsigned char TTGE2:1;\r
+ unsigned char :1;\r
+ unsigned char TCIEV:1;\r
+ unsigned char TGIED:1;\r
+ unsigned char TGIEC:1;\r
+ unsigned char TGIEB:1;\r
+ unsigned char TGIEA:1;\r
+ } BIT;\r
+ } TIER;\r
+ char wk4[8];\r
+ unsigned short TCNT;\r
+ char wk5[8];\r
+ unsigned short TGRA;\r
+ unsigned short TGRB;\r
+ char wk6[8];\r
+ unsigned short TGRC;\r
+ unsigned short TGRD;\r
+ char wk7[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TCFD:1;\r
+ } BIT;\r
+ } TSR;\r
+ char wk8[11];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char TTSE:1;\r
+ unsigned char TTSB:1;\r
+ unsigned char TTSA:1;\r
+ } BIT;\r
+ } TBTM;\r
+ char wk9[6];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short BF:2;\r
+ unsigned short :6;\r
+ unsigned short UT4AE:1;\r
+ unsigned short DT4AE:1;\r
+ unsigned short UT4BE:1;\r
+ unsigned short DT4BE:1;\r
+ unsigned short ITA3AE:1;\r
+ unsigned short ITA4VE:1;\r
+ unsigned short ITB3AE:1;\r
+ unsigned short ITB4VE:1;\r
+ } BIT;\r
+ } TADCR;\r
+ char wk10[2];\r
+ unsigned short TADCORA;\r
+ unsigned short TADCORB;\r
+ unsigned short TADCOBRA;\r
+ unsigned short TADCOBRB;\r
+ char wk11[72];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char NFCS:2;\r
+ unsigned char NFDEN:1;\r
+ unsigned char NFCEN:1;\r
+ unsigned char NFBEN:1;\r
+ unsigned char NFAEN:1;\r
+ } BIT;\r
+ } NFCR;\r
+};\r
+\r
+struct st_mtu5 {\r
+ char wk0[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char NFCS:2;\r
+ unsigned char :1;\r
+ unsigned char NFWEN:1;\r
+ unsigned char NFVEN:1;\r
+ unsigned char NFUEN:1;\r
+ } BIT;\r
+ } NFCR;\r
+ char wk1[490];\r
+ unsigned short TCNTU;\r
+ unsigned short TGRU;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :6;\r
+ unsigned char TPSC:2;\r
+ } BIT;\r
+ } TCRU;\r
+ char wk2[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char IOC:5;\r
+ } BIT;\r
+ } TIORU;\r
+ char wk3[9];\r
+ unsigned short TCNTV;\r
+ unsigned short TGRV;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :6;\r
+ unsigned char TPSC:2;\r
+ } BIT;\r
+ } TCRV;\r
+ char wk4[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char IOC:5;\r
+ } BIT;\r
+ } TIORV;\r
+ char wk5[9];\r
+ unsigned short TCNTW;\r
+ unsigned short TGRW;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :6;\r
+ unsigned char TPSC:2;\r
+ } BIT;\r
+ } TCRW;\r
+ char wk6[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char IOC:5;\r
+ } BIT;\r
+ } TIORW;\r
+ char wk7[11];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char TGIE5U:1;\r
+ unsigned char TGIE5V:1;\r
+ unsigned char TGIE5W:1;\r
+ } BIT;\r
+ } TIER;\r
+ char wk8[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char CSTU5:1;\r
+ unsigned char CSTV5:1;\r
+ unsigned char CSTW5:1;\r
+ } BIT;\r
+ } TSTR;\r
+ char wk9[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char CMPCLR5U:1;\r
+ unsigned char CMPCLR5V:1;\r
+ unsigned char CMPCLR5W:1;\r
+ } BIT;\r
+ } TCNTCMPCLR;\r
+};\r
+\r
+struct st_poe {\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short POE3F:1;\r
+ unsigned short POE2F:1;\r
+ unsigned short POE1F:1;\r
+ unsigned short POE0F:1;\r
+ unsigned short :3;\r
+ unsigned short PIE1:1;\r
+ unsigned short POE3M:2;\r
+ unsigned short POE2M:2;\r
+ unsigned short POE1M:2;\r
+ unsigned short POE0M:2;\r
+ } BIT;\r
+ } ICSR1;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short OSF1:1;\r
+ unsigned short :5;\r
+ unsigned short OCE1:1;\r
+ unsigned short OIE1:1;\r
+ } BIT;\r
+ } OCSR1;\r
+ char wk0[4];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :3;\r
+ unsigned short POE8F:1;\r
+ unsigned short :2;\r
+ unsigned short POE8E:1;\r
+ unsigned short PIE2:1;\r
+ unsigned short :6;\r
+ unsigned short POE8M:2;\r
+ } BIT;\r
+ } ICSR2;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :6;\r
+ unsigned char CH0HIZ:1;\r
+ unsigned char CH34HIZ:1;\r
+ } BIT;\r
+ } SPOER;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :4;\r
+ unsigned char PE3ZE:1;\r
+ unsigned char PE2ZE:1;\r
+ unsigned char PE1ZE:1;\r
+ unsigned char PE0ZE:1;\r
+ } BIT;\r
+ } POECR1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char P1CZEA:1;\r
+ unsigned char P2CZEA:1;\r
+ unsigned char P3CZEA:1;\r
+ } BIT;\r
+ } POECR2;\r
+ char wk1[1];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :3;\r
+ unsigned short OSTSTF:1;\r
+ unsigned short :2;\r
+ unsigned short OSTSTE:1;\r
+ } BIT;\r
+ } ICSR3;\r
+};\r
+\r
+struct st_port0 {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char :1;\r
+ unsigned char B5:1;\r
+ unsigned char :1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PDR;\r
+ char wk0[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char :1;\r
+ unsigned char B5:1;\r
+ unsigned char :1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PODR;\r
+ char wk1[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char :1;\r
+ unsigned char B5:1;\r
+ unsigned char :1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PIDR;\r
+ char wk2[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char :1;\r
+ unsigned char B5:1;\r
+ unsigned char :1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PMR;\r
+ char wk3[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ unsigned char B4:1;\r
+ unsigned char :1;\r
+ unsigned char B2:1;\r
+ unsigned char :1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } ODR0;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :3;\r
+ unsigned char B2:1;\r
+ } BIT;\r
+ } ODR1;\r
+ char wk4[62];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char :1;\r
+ unsigned char B5:1;\r
+ unsigned char :1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PCR;\r
+ char wk5[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } DSCR;\r
+};\r
+\r
+struct st_port1 {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PDR;\r
+ char wk0[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PODR;\r
+ char wk1[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PIDR;\r
+ char wk2[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PMR;\r
+ char wk3[32];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ unsigned char B4:1;\r
+ unsigned char :1;\r
+ unsigned char B2:1;\r
+ unsigned char :1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } ODR0;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ unsigned char B4:1;\r
+ unsigned char :1;\r
+ unsigned char B2:1;\r
+ unsigned char :1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } ODR1;\r
+ char wk4[61];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PCR;\r
+};\r
+\r
+struct st_port2 {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PDR;\r
+ char wk0[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PODR;\r
+ char wk1[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PIDR;\r
+ char wk2[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PMR;\r
+ char wk3[33];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ unsigned char B4:1;\r
+ unsigned char :1;\r
+ unsigned char B2:1;\r
+ unsigned char :1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } ODR0;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ unsigned char B4:1;\r
+ unsigned char :1;\r
+ unsigned char B2:1;\r
+ unsigned char :1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } ODR1;\r
+ char wk4[60];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PCR;\r
+ char wk5[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ } BIT;\r
+ } DSCR;\r
+};\r
+\r
+struct st_port3 {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PDR;\r
+ char wk0[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PODR;\r
+ char wk1[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PIDR;\r
+ char wk2[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PMR;\r
+ char wk3[34];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ unsigned char B4:1;\r
+ unsigned char :1;\r
+ unsigned char B2:1;\r
+ unsigned char :1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } ODR0;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ unsigned char B4:1;\r
+ unsigned char :1;\r
+ unsigned char B2:1;\r
+ unsigned char :1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } ODR1;\r
+ char wk4[59];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PCR;\r
+};\r
+\r
+struct st_port4 {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PDR;\r
+ char wk0[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PODR;\r
+ char wk1[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PIDR;\r
+ char wk2[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PMR;\r
+ char wk3[35];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ unsigned char B4:1;\r
+ unsigned char :1;\r
+ unsigned char B2:1;\r
+ unsigned char :1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } ODR0;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ unsigned char B4:1;\r
+ unsigned char :1;\r
+ unsigned char B2:1;\r
+ unsigned char :1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } ODR1;\r
+ char wk4[58];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PCR;\r
+};\r
+\r
+struct st_port5 {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PDR;\r
+ char wk0[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PODR;\r
+ char wk1[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PIDR;\r
+ char wk2[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PMR;\r
+ char wk3[36];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ unsigned char B4:1;\r
+ unsigned char :1;\r
+ unsigned char B2:1;\r
+ unsigned char :1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } ODR0;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ unsigned char B4:1;\r
+ unsigned char :1;\r
+ unsigned char B2:1;\r
+ unsigned char :1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } ODR1;\r
+ char wk4[57];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PCR;\r
+ char wk5[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char :3;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } DSCR;\r
+};\r
+\r
+struct st_port6 {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PDR;\r
+ char wk0[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PODR;\r
+ char wk1[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PIDR;\r
+ char wk2[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PMR;\r
+ char wk3[37];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ unsigned char B4:1;\r
+ unsigned char :1;\r
+ unsigned char B2:1;\r
+ unsigned char :1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } ODR0;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ unsigned char B4:1;\r
+ unsigned char :1;\r
+ unsigned char B2:1;\r
+ unsigned char :1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } ODR1;\r
+ char wk4[56];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PCR;\r
+ char wk5[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } DSCR;\r
+};\r
+\r
+struct st_port7 {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PDR;\r
+ char wk0[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PODR;\r
+ char wk1[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PIDR;\r
+ char wk2[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PMR;\r
+ char wk3[38];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ unsigned char B4:1;\r
+ unsigned char :1;\r
+ unsigned char B2:1;\r
+ unsigned char :1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } ODR0;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ unsigned char B4:1;\r
+ unsigned char :1;\r
+ unsigned char B2:1;\r
+ unsigned char :1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } ODR1;\r
+ char wk4[55];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PCR;\r
+ char wk5[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } DSCR;\r
+};\r
+\r
+struct st_port8 {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PDR;\r
+ char wk0[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PODR;\r
+ char wk1[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PIDR;\r
+ char wk2[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PMR;\r
+ char wk3[39];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ unsigned char B4:1;\r
+ unsigned char :1;\r
+ unsigned char B2:1;\r
+ unsigned char :1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } ODR0;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ unsigned char B4:1;\r
+ unsigned char :1;\r
+ unsigned char B2:1;\r
+ unsigned char :1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } ODR1;\r
+ char wk4[54];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PCR;\r
+};\r
+\r
+struct st_port9 {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PDR;\r
+ char wk0[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PODR;\r
+ char wk1[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PIDR;\r
+ char wk2[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PMR;\r
+ char wk3[40];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ unsigned char B4:1;\r
+ unsigned char :1;\r
+ unsigned char B2:1;\r
+ unsigned char :1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } ODR0;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ unsigned char B4:1;\r
+ unsigned char :1;\r
+ unsigned char B2:1;\r
+ unsigned char :1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } ODR1;\r
+ char wk4[53];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PCR;\r
+ char wk5[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } DSCR;\r
+};\r
+\r
+struct st_porta {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PDR;\r
+ char wk0[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PODR;\r
+ char wk1[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PIDR;\r
+ char wk2[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PMR;\r
+ char wk3[41];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ unsigned char B4:1;\r
+ unsigned char :1;\r
+ unsigned char B2:1;\r
+ unsigned char :1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } ODR0;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ unsigned char B4:1;\r
+ unsigned char :1;\r
+ unsigned char B2:1;\r
+ unsigned char :1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } ODR1;\r
+ char wk4[52];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PCR;\r
+ char wk5[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } DSCR;\r
+};\r
+\r
+struct st_portb {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PDR;\r
+ char wk0[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PODR;\r
+ char wk1[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PIDR;\r
+ char wk2[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PMR;\r
+ char wk3[42];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ unsigned char B4:1;\r
+ unsigned char :1;\r
+ unsigned char B2:1;\r
+ unsigned char :1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } ODR0;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ unsigned char B4:1;\r
+ unsigned char :1;\r
+ unsigned char B2:1;\r
+ unsigned char :1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } ODR1;\r
+ char wk4[51];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PCR;\r
+ char wk5[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } DSCR;\r
+};\r
+\r
+struct st_portc {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PDR;\r
+ char wk0[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PODR;\r
+ char wk1[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PIDR;\r
+ char wk2[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PMR;\r
+ char wk3[43];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ unsigned char B4:1;\r
+ unsigned char :1;\r
+ unsigned char B2:1;\r
+ unsigned char :1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } ODR0;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ unsigned char B4:1;\r
+ unsigned char :1;\r
+ unsigned char B2:1;\r
+ unsigned char :1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } ODR1;\r
+ char wk4[50];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PCR;\r
+ char wk5[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } DSCR;\r
+};\r
+\r
+struct st_portd {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PDR;\r
+ char wk0[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PODR;\r
+ char wk1[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PIDR;\r
+ char wk2[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PMR;\r
+ char wk3[44];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ unsigned char B4:1;\r
+ unsigned char :1;\r
+ unsigned char B2:1;\r
+ unsigned char :1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } ODR0;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ unsigned char B4:1;\r
+ unsigned char :1;\r
+ unsigned char B2:1;\r
+ unsigned char :1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } ODR1;\r
+ char wk4[49];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PCR;\r
+ char wk5[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } DSCR;\r
+};\r
+\r
+struct st_porte {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PDR;\r
+ char wk0[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PODR;\r
+ char wk1[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PIDR;\r
+ char wk2[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PMR;\r
+ char wk3[45];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char :1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } ODR0;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ unsigned char B4:1;\r
+ unsigned char :1;\r
+ unsigned char B2:1;\r
+ unsigned char :1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } ODR1;\r
+ char wk4[48];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PCR;\r
+ char wk5[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } DSCR;\r
+};\r
+\r
+struct st_portf {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PDR;\r
+ char wk0[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PODR;\r
+ char wk1[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PIDR;\r
+ char wk2[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PMR;\r
+ char wk3[46];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ unsigned char B4:1;\r
+ unsigned char :1;\r
+ unsigned char B2:1;\r
+ unsigned char :1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } ODR0;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char B2:1;\r
+ unsigned char :1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } ODR1;\r
+ char wk4[47];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PCR;\r
+};\r
+\r
+struct st_portg {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PDR;\r
+ char wk0[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PODR;\r
+ char wk1[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PIDR;\r
+ char wk2[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PMR;\r
+ char wk3[47];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ unsigned char B4:1;\r
+ unsigned char :1;\r
+ unsigned char B2:1;\r
+ unsigned char :1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } ODR0;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ unsigned char B4:1;\r
+ unsigned char :1;\r
+ unsigned char B2:1;\r
+ unsigned char :1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } ODR1;\r
+ char wk4[46];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PCR;\r
+ char wk5[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :6;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } DSCR;\r
+};\r
+\r
+struct st_porth {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ } BIT;\r
+ } PDR;\r
+ char wk0[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ } BIT;\r
+ } PODR;\r
+ char wk1[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ } BIT;\r
+ } PIDR;\r
+ char wk2[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ } BIT;\r
+ } PMR;\r
+ char wk3[49];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char B2:1;\r
+ unsigned char :1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } ODR1;\r
+ char wk4[45];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ } BIT;\r
+ } PCR;\r
+};\r
+\r
+struct st_portj {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char B5:1;\r
+ unsigned char :1;\r
+ unsigned char B3:1;\r
+ } BIT;\r
+ } PDR;\r
+ char wk0[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char B5:1;\r
+ unsigned char :1;\r
+ unsigned char B3:1;\r
+ } BIT;\r
+ } PODR;\r
+ char wk1[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char B5:1;\r
+ unsigned char :1;\r
+ unsigned char B3:1;\r
+ } BIT;\r
+ } PIDR;\r
+ char wk2[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char B5:1;\r
+ unsigned char :1;\r
+ unsigned char B3:1;\r
+ } BIT;\r
+ } PMR;\r
+ char wk3[49];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ } BIT;\r
+ } ODR0;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char B2:1;\r
+ } BIT;\r
+ } ODR1;\r
+ char wk4[44];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char B5:1;\r
+ unsigned char :1;\r
+ unsigned char B3:1;\r
+ } BIT;\r
+ } PCR;\r
+};\r
+\r
+struct st_portk {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PDR;\r
+ char wk0[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PODR;\r
+ char wk1[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PIDR;\r
+ char wk2[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PMR;\r
+ char wk3[50];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ unsigned char B4:1;\r
+ unsigned char :1;\r
+ unsigned char B2:1;\r
+ unsigned char :1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } ODR0;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ unsigned char B4:1;\r
+ unsigned char :1;\r
+ unsigned char B2:1;\r
+ unsigned char :1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } ODR1;\r
+ char wk4[43];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PCR;\r
+};\r
+\r
+struct st_portl {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PDR;\r
+ char wk0[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PODR;\r
+ char wk1[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PIDR;\r
+ char wk2[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PMR;\r
+ char wk3[51];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ unsigned char B4:1;\r
+ unsigned char :1;\r
+ unsigned char B2:1;\r
+ unsigned char :1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } ODR0;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } ODR1;\r
+ char wk4[42];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PCR;\r
+};\r
+\r
+struct st_ppg0 {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char G3CMS:2;\r
+ unsigned char G2CMS:2;\r
+ unsigned char G1CMS:2;\r
+ unsigned char G0CMS:2;\r
+ } BIT;\r
+ } PCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char G3INV:1;\r
+ unsigned char G2INV:1;\r
+ unsigned char G1INV:1;\r
+ unsigned char G0INV:1;\r
+ unsigned char G3NOV:1;\r
+ unsigned char G2NOV:1;\r
+ unsigned char G1NOV:1;\r
+ unsigned char G0NOV:1;\r
+ } BIT;\r
+ } PMR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char NDER15:1;\r
+ unsigned char NDER14:1;\r
+ unsigned char NDER13:1;\r
+ unsigned char NDER12:1;\r
+ unsigned char NDER11:1;\r
+ unsigned char NDER10:1;\r
+ unsigned char NDER9:1;\r
+ unsigned char NDER8:1;\r
+ } BIT;\r
+ } NDERH;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char NDER7:1;\r
+ unsigned char NDER6:1;\r
+ unsigned char NDER5:1;\r
+ unsigned char NDER4:1;\r
+ unsigned char NDER3:1;\r
+ unsigned char NDER2:1;\r
+ unsigned char NDER1:1;\r
+ unsigned char NDER0:1;\r
+ } BIT;\r
+ } NDERL;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char POD15:1;\r
+ unsigned char POD14:1;\r
+ unsigned char POD13:1;\r
+ unsigned char POD12:1;\r
+ unsigned char POD11:1;\r
+ unsigned char POD10:1;\r
+ unsigned char POD9:1;\r
+ unsigned char POD8:1;\r
+ } BIT;\r
+ } PODRH;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char POD7:1;\r
+ unsigned char POD6:1;\r
+ unsigned char POD5:1;\r
+ unsigned char POD4:1;\r
+ unsigned char POD3:1;\r
+ unsigned char POD2:1;\r
+ unsigned char POD1:1;\r
+ unsigned char POD0:1;\r
+ } BIT;\r
+ } PODRL;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char NDR15:1;\r
+ unsigned char NDR14:1;\r
+ unsigned char NDR13:1;\r
+ unsigned char NDR12:1;\r
+ unsigned char NDR11:1;\r
+ unsigned char NDR10:1;\r
+ unsigned char NDR9:1;\r
+ unsigned char NDR8:1;\r
+ } BIT;\r
+ } NDRH;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char NDR7:1;\r
+ unsigned char NDR6:1;\r
+ unsigned char NDR5:1;\r
+ unsigned char NDR4:1;\r
+ unsigned char NDR3:1;\r
+ unsigned char NDR2:1;\r
+ unsigned char NDR1:1;\r
+ unsigned char NDR0:1;\r
+ } BIT;\r
+ } NDRL;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :4;\r
+ unsigned char NDR11:1;\r
+ unsigned char NDR10:1;\r
+ unsigned char NDR9:1;\r
+ unsigned char NDR8:1;\r
+ } BIT;\r
+ } NDRH2;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :4;\r
+ unsigned char NDR3:1;\r
+ unsigned char NDR2:1;\r
+ unsigned char NDR1:1;\r
+ unsigned char NDR0:1;\r
+ } BIT;\r
+ } NDRL2;\r
+};\r
+\r
+struct st_ppg1 {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char PTRSL:1;\r
+ } BIT;\r
+ } PTRSLR;\r
+ char wk0[5];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char G3CMS:2;\r
+ unsigned char G2CMS:2;\r
+ unsigned char G1CMS:2;\r
+ unsigned char G0CMS:2;\r
+ } BIT;\r
+ } PCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char G3INV:1;\r
+ unsigned char G2INV:1;\r
+ unsigned char G1INV:1;\r
+ unsigned char G0INV:1;\r
+ unsigned char G3NOV:1;\r
+ unsigned char G2NOV:1;\r
+ unsigned char G1NOV:1;\r
+ unsigned char G0NOV:1;\r
+ } BIT;\r
+ } PMR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char NDER31:1;\r
+ unsigned char NDER30:1;\r
+ unsigned char NDER29:1;\r
+ unsigned char NDER28:1;\r
+ unsigned char NDER27:1;\r
+ unsigned char NDER26:1;\r
+ unsigned char NDER25:1;\r
+ unsigned char NDER24:1;\r
+ } BIT;\r
+ } NDERH;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char NDER23:1;\r
+ unsigned char NDER22:1;\r
+ unsigned char NDER21:1;\r
+ unsigned char NDER20:1;\r
+ unsigned char NDER19:1;\r
+ unsigned char NDER18:1;\r
+ unsigned char NDER17:1;\r
+ unsigned char NDER16:1;\r
+ } BIT;\r
+ } NDERL;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char POD31:1;\r
+ unsigned char POD30:1;\r
+ unsigned char POD29:1;\r
+ unsigned char POD28:1;\r
+ unsigned char POD27:1;\r
+ unsigned char POD26:1;\r
+ unsigned char POD25:1;\r
+ unsigned char POD24:1;\r
+ } BIT;\r
+ } PODRH;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char POD23:1;\r
+ unsigned char POD22:1;\r
+ unsigned char POD21:1;\r
+ unsigned char POD20:1;\r
+ unsigned char POD19:1;\r
+ unsigned char POD18:1;\r
+ unsigned char POD17:1;\r
+ unsigned char POD16:1;\r
+ } BIT;\r
+ } PODRL;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char NDR31:1;\r
+ unsigned char NDR30:1;\r
+ unsigned char NDR29:1;\r
+ unsigned char NDR28:1;\r
+ unsigned char NDR27:1;\r
+ unsigned char NDR26:1;\r
+ unsigned char NDR25:1;\r
+ unsigned char NDR24:1;\r
+ } BIT;\r
+ } NDRH;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char NDR23:1;\r
+ unsigned char NDR22:1;\r
+ unsigned char NDR21:1;\r
+ unsigned char NDR20:1;\r
+ unsigned char NDR19:1;\r
+ unsigned char NDR18:1;\r
+ unsigned char NDR17:1;\r
+ unsigned char NDR16:1;\r
+ } BIT;\r
+ } NDRL;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :4;\r
+ unsigned char NDR27:1;\r
+ unsigned char NDR26:1;\r
+ unsigned char NDR25:1;\r
+ unsigned char NDR24:1;\r
+ } BIT;\r
+ } NDRH2;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :4;\r
+ unsigned char NDR19:1;\r
+ unsigned char NDR18:1;\r
+ unsigned char NDR17:1;\r
+ unsigned char NDR16:1;\r
+ } BIT;\r
+ } NDRL2;\r
+};\r
+\r
+struct st_riic0 {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ICE:1;\r
+ unsigned char IICRST:1;\r
+ unsigned char CLO:1;\r
+ unsigned char SOWP:1;\r
+ unsigned char SCLO:1;\r
+ unsigned char SDAO:1;\r
+ unsigned char SCLI:1;\r
+ unsigned char SDAI:1;\r
+ } BIT;\r
+ } ICCR1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char BBSY:1;\r
+ unsigned char MST:1;\r
+ unsigned char TRS:1;\r
+ unsigned char :1;\r
+ unsigned char SP:1;\r
+ unsigned char RS:1;\r
+ unsigned char ST:1;\r
+ } BIT;\r
+ } ICCR2;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char MTWP:1;\r
+ unsigned char CKS:3;\r
+ unsigned char BCWP:1;\r
+ unsigned char BC:3;\r
+ } BIT;\r
+ } ICMR1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char DLCS:1;\r
+ unsigned char SDDL:3;\r
+ unsigned char :1;\r
+ unsigned char TMOH:1;\r
+ unsigned char TMOL:1;\r
+ unsigned char TMOS:1;\r
+ } BIT;\r
+ } ICMR2;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char SMBS:1;\r
+ unsigned char WAIT:1;\r
+ unsigned char RDRFS:1;\r
+ unsigned char ACKWP:1;\r
+ unsigned char ACKBT:1;\r
+ unsigned char ACKBR:1;\r
+ unsigned char NF:2;\r
+ } BIT;\r
+ } ICMR3;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char FMPE:1;\r
+ unsigned char SCLE:1;\r
+ unsigned char NFE:1;\r
+ unsigned char NACKE:1;\r
+ unsigned char SALE:1;\r
+ unsigned char NALE:1;\r
+ unsigned char MALE:1;\r
+ unsigned char TMOE:1;\r
+ } BIT;\r
+ } ICFER;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char HOAE:1;\r
+ unsigned char :1;\r
+ unsigned char DIDE:1;\r
+ unsigned char :1;\r
+ unsigned char GCAE:1;\r
+ unsigned char SAR2E:1;\r
+ unsigned char SAR1E:1;\r
+ unsigned char SAR0E:1;\r
+ } BIT;\r
+ } ICSER;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TIE:1;\r
+ unsigned char TEIE:1;\r
+ unsigned char RIE:1;\r
+ unsigned char NAKIE:1;\r
+ unsigned char SPIE:1;\r
+ unsigned char STIE:1;\r
+ unsigned char ALIE:1;\r
+ unsigned char TMOIE:1;\r
+ } BIT;\r
+ } ICIER;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char HOA:1;\r
+ unsigned char :1;\r
+ unsigned char DID:1;\r
+ unsigned char :1;\r
+ unsigned char GCA:1;\r
+ unsigned char AAS2:1;\r
+ unsigned char AAS1:1;\r
+ unsigned char AAS0:1;\r
+ } BIT;\r
+ } ICSR1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TDRE:1;\r
+ unsigned char TEND:1;\r
+ unsigned char RDRF:1;\r
+ unsigned char NACKF:1;\r
+ unsigned char STOP:1;\r
+ unsigned char START:1;\r
+ unsigned char AL:1;\r
+ unsigned char TMOF:1;\r
+ } BIT;\r
+ } ICSR2;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char SVA:7;\r
+ unsigned char SVA0:1;\r
+ } BIT;\r
+ } SARL0;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char SVA:2;\r
+ unsigned char FS:1;\r
+ } BIT;\r
+ } SARU0;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char SVA:7;\r
+ unsigned char SVA0:1;\r
+ } BIT;\r
+ } SARL1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char SVA:2;\r
+ unsigned char FS:1;\r
+ } BIT;\r
+ } SARU1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char SVA:7;\r
+ unsigned char SVA0:1;\r
+ } BIT;\r
+ } SARL2;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char SVA:2;\r
+ unsigned char FS:1;\r
+ } BIT;\r
+ } SARU2;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char BRL:5;\r
+ } BIT;\r
+ } ICBRL;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char BRH:5;\r
+ } BIT;\r
+ } ICBRH;\r
+ unsigned char ICDRT;\r
+ unsigned char ICDRR;\r
+};\r
+\r
+struct st_riic1 {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ICE:1;\r
+ unsigned char IICRST:1;\r
+ unsigned char CLO:1;\r
+ unsigned char SOWP:1;\r
+ unsigned char SCLO:1;\r
+ unsigned char SDAO:1;\r
+ unsigned char SCLI:1;\r
+ unsigned char SDAI:1;\r
+ } BIT;\r
+ } ICCR1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char BBSY:1;\r
+ unsigned char MST:1;\r
+ unsigned char TRS:1;\r
+ unsigned char :1;\r
+ unsigned char SP:1;\r
+ unsigned char RS:1;\r
+ unsigned char ST:1;\r
+ } BIT;\r
+ } ICCR2;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char MTWP:1;\r
+ unsigned char CKS:3;\r
+ unsigned char BCWP:1;\r
+ unsigned char BC:3;\r
+ } BIT;\r
+ } ICMR1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char DLCS:1;\r
+ unsigned char SDDL:3;\r
+ unsigned char :1;\r
+ unsigned char TMOH:1;\r
+ unsigned char TMOL:1;\r
+ unsigned char TMOS:1;\r
+ } BIT;\r
+ } ICMR2;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char SMBS:1;\r
+ unsigned char WAIT:1;\r
+ unsigned char RDRFS:1;\r
+ unsigned char ACKWP:1;\r
+ unsigned char ACKBT:1;\r
+ unsigned char ACKBR:1;\r
+ unsigned char NF:2;\r
+ } BIT;\r
+ } ICMR3;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char SCLE:1;\r
+ unsigned char NFE:1;\r
+ unsigned char NACKE:1;\r
+ unsigned char SALE:1;\r
+ unsigned char NALE:1;\r
+ unsigned char MALE:1;\r
+ unsigned char TMOE:1;\r
+ } BIT;\r
+ } ICFER;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char HOAE:1;\r
+ unsigned char :1;\r
+ unsigned char DIDE:1;\r
+ unsigned char :1;\r
+ unsigned char GCAE:1;\r
+ unsigned char SAR2E:1;\r
+ unsigned char SAR1E:1;\r
+ unsigned char SAR0E:1;\r
+ } BIT;\r
+ } ICSER;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TIE:1;\r
+ unsigned char TEIE:1;\r
+ unsigned char RIE:1;\r
+ unsigned char NAKIE:1;\r
+ unsigned char SPIE:1;\r
+ unsigned char STIE:1;\r
+ unsigned char ALIE:1;\r
+ unsigned char TMOIE:1;\r
+ } BIT;\r
+ } ICIER;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char HOA:1;\r
+ unsigned char :1;\r
+ unsigned char DID:1;\r
+ unsigned char :1;\r
+ unsigned char GCA:1;\r
+ unsigned char AAS2:1;\r
+ unsigned char AAS1:1;\r
+ unsigned char AAS0:1;\r
+ } BIT;\r
+ } ICSR1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TDRE:1;\r
+ unsigned char TEND:1;\r
+ unsigned char RDRF:1;\r
+ unsigned char NACKF:1;\r
+ unsigned char STOP:1;\r
+ unsigned char START:1;\r
+ unsigned char AL:1;\r
+ unsigned char TMOF:1;\r
+ } BIT;\r
+ } ICSR2;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char SVA:7;\r
+ unsigned char SVA0:1;\r
+ } BIT;\r
+ } SARL0;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char SVA:2;\r
+ unsigned char FS:1;\r
+ } BIT;\r
+ } SARU0;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char SVA:7;\r
+ unsigned char SVA0:1;\r
+ } BIT;\r
+ } SARL1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char SVA:2;\r
+ unsigned char FS:1;\r
+ } BIT;\r
+ } SARU1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char SVA:7;\r
+ unsigned char SVA0:1;\r
+ } BIT;\r
+ } SARL2;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char SVA:2;\r
+ unsigned char FS:1;\r
+ } BIT;\r
+ } SARU2;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char BRL:5;\r
+ } BIT;\r
+ } ICBRL;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char BRH:5;\r
+ } BIT;\r
+ } ICBRH;\r
+ unsigned char ICDRT;\r
+ unsigned char ICDRR;\r
+};\r
+\r
+struct st_rspi {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char SPRIE:1;\r
+ unsigned char SPE:1;\r
+ unsigned char SPTIE:1;\r
+ unsigned char SPEIE:1;\r
+ unsigned char MSTR:1;\r
+ unsigned char MODFEN:1;\r
+ unsigned char TXMD:1;\r
+ unsigned char SPMS:1;\r
+ } BIT;\r
+ } SPCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :4;\r
+ unsigned char SSL3P:1;\r
+ unsigned char SSL2P:1;\r
+ unsigned char SSL1P:1;\r
+ unsigned char SSL0P:1;\r
+ } BIT;\r
+ } SSLP;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char MOIFE:1;\r
+ unsigned char MOIFV:1;\r
+ unsigned char :1;\r
+ unsigned char SPOM:1;\r
+ unsigned char SPLP2:1;\r
+ unsigned char SPLP:1;\r
+ } BIT;\r
+ } SPPCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :4;\r
+ unsigned char PERF:1;\r
+ unsigned char MODF:1;\r
+ unsigned char IDLNF:1;\r
+ unsigned char OVRF:1;\r
+ } BIT;\r
+ } SPSR;\r
+ unsigned long SPDR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char SPSLN:3;\r
+ } BIT;\r
+ } SPSCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char SPECM:3;\r
+ unsigned char :1;\r
+ unsigned char SPCP:3;\r
+ } BIT;\r
+ } SPSSR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char SPR7:1;\r
+ unsigned char SPR6:1;\r
+ unsigned char SPR5:1;\r
+ unsigned char SPR4:1;\r
+ unsigned char SPR3:1;\r
+ unsigned char SPR2:1;\r
+ unsigned char SPR1:1;\r
+ unsigned char SPR0:1;\r
+ } BIT;\r
+ } SPBR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char SPLW:1;\r
+ unsigned char SPRDTD:1;\r
+ unsigned char SLSEL:2;\r
+ unsigned char SPFC:2;\r
+ } BIT;\r
+ } SPDCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char SCKDL:3;\r
+ } BIT;\r
+ } SPCKD;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char SLNDL:3;\r
+ } BIT;\r
+ } SSLND;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char SPNDL:3;\r
+ } BIT;\r
+ } SPND;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :4;\r
+ unsigned char PTE:1;\r
+ unsigned char SPIIE:1;\r
+ unsigned char SPOE:1;\r
+ unsigned char SPPE:1;\r
+ } BIT;\r
+ } SPCR2;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short SCKDEN:1;\r
+ unsigned short SLNDEN:1;\r
+ unsigned short SPNDEN:1;\r
+ unsigned short LSBF:1;\r
+ unsigned short SPB:4;\r
+ unsigned short SSLKP:1;\r
+ unsigned short SSLA:3;\r
+ unsigned short BRDV:2;\r
+ unsigned short CPOL:1;\r
+ unsigned short CPHA:1;\r
+ } BIT;\r
+ } SPCMD0;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short SCKDEN:1;\r
+ unsigned short SLNDEN:1;\r
+ unsigned short SPNDEN:1;\r
+ unsigned short LSBF:1;\r
+ unsigned short SPB:4;\r
+ unsigned short SSLKP:1;\r
+ unsigned short SSLA:3;\r
+ unsigned short BRDV:2;\r
+ unsigned short CPOL:1;\r
+ unsigned short CPHA:1;\r
+ } BIT;\r
+ } SPCMD1;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short SCKDEN:1;\r
+ unsigned short SLNDEN:1;\r
+ unsigned short SPNDEN:1;\r
+ unsigned short LSBF:1;\r
+ unsigned short SPB:4;\r
+ unsigned short SSLKP:1;\r
+ unsigned short SSLA:3;\r
+ unsigned short BRDV:2;\r
+ unsigned short CPOL:1;\r
+ unsigned short CPHA:1;\r
+ } BIT;\r
+ } SPCMD2;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short SCKDEN:1;\r
+ unsigned short SLNDEN:1;\r
+ unsigned short SPNDEN:1;\r
+ unsigned short LSBF:1;\r
+ unsigned short SPB:4;\r
+ unsigned short SSLKP:1;\r
+ unsigned short SSLA:3;\r
+ unsigned short BRDV:2;\r
+ unsigned short CPOL:1;\r
+ unsigned short CPHA:1;\r
+ } BIT;\r
+ } SPCMD3;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short SCKDEN:1;\r
+ unsigned short SLNDEN:1;\r
+ unsigned short SPNDEN:1;\r
+ unsigned short LSBF:1;\r
+ unsigned short SPB:4;\r
+ unsigned short SSLKP:1;\r
+ unsigned short SSLA:3;\r
+ unsigned short BRDV:2;\r
+ unsigned short CPOL:1;\r
+ unsigned short CPHA:1;\r
+ } BIT;\r
+ } SPCMD4;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short SCKDEN:1;\r
+ unsigned short SLNDEN:1;\r
+ unsigned short SPNDEN:1;\r
+ unsigned short LSBF:1;\r
+ unsigned short SPB:4;\r
+ unsigned short SSLKP:1;\r
+ unsigned short SSLA:3;\r
+ unsigned short BRDV:2;\r
+ unsigned short CPOL:1;\r
+ unsigned short CPHA:1;\r
+ } BIT;\r
+ } SPCMD5;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short SCKDEN:1;\r
+ unsigned short SLNDEN:1;\r
+ unsigned short SPNDEN:1;\r
+ unsigned short LSBF:1;\r
+ unsigned short SPB:4;\r
+ unsigned short SSLKP:1;\r
+ unsigned short SSLA:3;\r
+ unsigned short BRDV:2;\r
+ unsigned short CPOL:1;\r
+ unsigned short CPHA:1;\r
+ } BIT;\r
+ } SPCMD6;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short SCKDEN:1;\r
+ unsigned short SLNDEN:1;\r
+ unsigned short SPNDEN:1;\r
+ unsigned short LSBF:1;\r
+ unsigned short SPB:4;\r
+ unsigned short SSLKP:1;\r
+ unsigned short SSLA:3;\r
+ unsigned short BRDV:2;\r
+ unsigned short CPOL:1;\r
+ unsigned short CPHA:1;\r
+ } BIT;\r
+ } SPCMD7;\r
+};\r
+\r
+struct st_rtc {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char F1HZ:1;\r
+ unsigned char F2HZ:1;\r
+ unsigned char F4HZ:1;\r
+ unsigned char F8HZ:1;\r
+ unsigned char F16HZ:1;\r
+ unsigned char F32HZ:1;\r
+ unsigned char F64HZ:1;\r
+ } BIT;\r
+ } R64CNT;\r
+ char wk0[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char SEC10:3;\r
+ unsigned char SEC1:4;\r
+ } BIT;\r
+ } RSECCNT;\r
+ char wk1[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char MIN10:3;\r
+ unsigned char MIN1:4;\r
+ } BIT;\r
+ } RMINCNT;\r
+ char wk2[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char PM:1;\r
+ unsigned char HR10:2;\r
+ unsigned char HR1:4;\r
+ } BIT;\r
+ } RHRCNT;\r
+ char wk3[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char DAYW:3;\r
+ } BIT;\r
+ } RWKCNT;\r
+ char wk4[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char DATE10:2;\r
+ unsigned char DATE1:4;\r
+ } BIT;\r
+ } RDAYCNT;\r
+ char wk5[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char MON10:1;\r
+ unsigned char MON1:4;\r
+ } BIT;\r
+ } RMONCNT;\r
+ char wk6[1];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :8;\r
+ unsigned short YR10:4;\r
+ unsigned short YR1:4;\r
+ } BIT;\r
+ } RYRCNT;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ENB:1;\r
+ unsigned char SEC10:3;\r
+ unsigned char SEC1:4;\r
+ } BIT;\r
+ } RSECAR;\r
+ char wk7[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ENB:1;\r
+ unsigned char MIN10:3;\r
+ unsigned char MIN1:4;\r
+ } BIT;\r
+ } RMINAR;\r
+ char wk8[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ENB:1;\r
+ unsigned char PM:1;\r
+ unsigned char HR10:2;\r
+ unsigned char HR1:4;\r
+ } BIT;\r
+ } RHRAR;\r
+ char wk9[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ENB:1;\r
+ unsigned char :4;\r
+ unsigned char DAYW:3;\r
+ } BIT;\r
+ } RWKAR;\r
+ char wk10[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ENB:1;\r
+ unsigned char :1;\r
+ unsigned char DATE10:2;\r
+ unsigned char DATE1:4;\r
+ } BIT;\r
+ } RDAYAR;\r
+ char wk11[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ENB:1;\r
+ unsigned char :2;\r
+ unsigned char MON10:1;\r
+ unsigned char MON1:4;\r
+ } BIT;\r
+ } RMONAR;\r
+ char wk12[1];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :8;\r
+ unsigned short YR10:4;\r
+ unsigned short YR1:4;\r
+ } BIT;\r
+ } RYRAR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ENB:1;\r
+ } BIT;\r
+ } RYRAREN;\r
+ char wk13[3];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char PES:4;\r
+ unsigned char :1;\r
+ unsigned char PIE:1;\r
+ unsigned char CIE:1;\r
+ unsigned char AIE:1;\r
+ } BIT;\r
+ } RCR1;\r
+ char wk14[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char HR24:1;\r
+ unsigned char AADJP:1;\r
+ unsigned char AADJE:1;\r
+ unsigned char RTCOE:1;\r
+ unsigned char ADJ30:1;\r
+ unsigned char RESET:1;\r
+ unsigned char START:1;\r
+ } BIT;\r
+ } RCR2;\r
+ char wk15[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char RTCEN:1;\r
+ } BIT;\r
+ } RCR3;\r
+ char wk16[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char RCKSEL:1;\r
+ } BIT;\r
+ } RCR4;\r
+ char wk17[1];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :15;\r
+ unsigned short RFC:1;\r
+ } BIT;\r
+ } RFRH;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short RFC:16;\r
+ } BIT;\r
+ } RFRL;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char PMADJ:2;\r
+ unsigned char ADJ:6;\r
+ } BIT;\r
+ } RADJ;\r
+ char wk18[17];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TCEN:1;\r
+ unsigned char :1;\r
+ unsigned char TCNF:2;\r
+ unsigned char :1;\r
+ unsigned char TCST:1;\r
+ unsigned char TCCT:2;\r
+ } BIT;\r
+ } RTCCR0;\r
+ char wk19[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TCEN:1;\r
+ unsigned char :1;\r
+ unsigned char TCNF:2;\r
+ unsigned char :1;\r
+ unsigned char TCST:1;\r
+ unsigned char TCCT:2;\r
+ } BIT;\r
+ } RTCCR1;\r
+ char wk20[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TCEN:1;\r
+ unsigned char :1;\r
+ unsigned char TCNF:2;\r
+ unsigned char :1;\r
+ unsigned char TCST:1;\r
+ unsigned char TCCT:2;\r
+ } BIT;\r
+ } RTCCR2;\r
+ char wk21[13];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char SEC10:3;\r
+ unsigned char SEC1:4;\r
+ } BIT;\r
+ } RSECCP0;\r
+ char wk22[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char MIN10:3;\r
+ unsigned char MIN1:4;\r
+ } BIT;\r
+ } RMINCP0;\r
+ char wk23[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char PM:1;\r
+ unsigned char HR10:2;\r
+ unsigned char HR1:4;\r
+ } BIT;\r
+ } RHRCP0;\r
+ char wk24[3];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char DATE10:3;\r
+ unsigned char DATE1:4;\r
+ } BIT;\r
+ } RDAYCP0;\r
+ char wk25[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char MON10:1;\r
+ unsigned char MON1:4;\r
+ } BIT;\r
+ } RMONCP0;\r
+ char wk26[5];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char SEC10:3;\r
+ unsigned char SEC1:4;\r
+ } BIT;\r
+ } RSECCP1;\r
+ char wk27[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char MIN10:3;\r
+ unsigned char MIN1:4;\r
+ } BIT;\r
+ } RMINCP1;\r
+ char wk28[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char PM:1;\r
+ unsigned char HR10:2;\r
+ unsigned char HR1:4;\r
+ } BIT;\r
+ } RHRCP1;\r
+ char wk29[3];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char DATE10:3;\r
+ unsigned char DATE1:4;\r
+ } BIT;\r
+ } RDAYCP1;\r
+ char wk30[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char MON10:1;\r
+ unsigned char MON1:4;\r
+ } BIT;\r
+ } RMONCP1;\r
+ char wk31[5];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char SEC10:3;\r
+ unsigned char SEC1:4;\r
+ } BIT;\r
+ } RSECCP2;\r
+ char wk32[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char MIN10:3;\r
+ unsigned char MIN1:4;\r
+ } BIT;\r
+ } RMINCP2;\r
+ char wk33[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char PM:1;\r
+ unsigned char HR10:2;\r
+ unsigned char HR1:4;\r
+ } BIT;\r
+ } RHRCP2;\r
+ char wk34[3];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char DATE10:3;\r
+ unsigned char DATE1:4;\r
+ } BIT;\r
+ } RDAYCP2;\r
+ char wk35[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char MON10:1;\r
+ unsigned char MON1:4;\r
+ } BIT;\r
+ } RMONCP2;\r
+};\r
+\r
+struct st_s12ad {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ADST:1;\r
+ unsigned char ADCS:1;\r
+ unsigned char :1;\r
+ unsigned char ADIE:1;\r
+ unsigned char CKS:2;\r
+ unsigned char TRGE:1;\r
+ unsigned char EXTRG:1;\r
+ } BIT;\r
+ } ADCSR;\r
+ char wk0[3];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short ANS0:16;\r
+ } BIT;\r
+ } ADANS0;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :11;\r
+ unsigned short ANS1:5;\r
+ } BIT;\r
+ } ADANS1;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short ADS0:16;\r
+ } BIT;\r
+ } ADADS0;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :11;\r
+ unsigned short ADS1:5;\r
+ } BIT;\r
+ } ADADS1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :6;\r
+ unsigned char ADC:2;\r
+ } BIT;\r
+ } ADADC;\r
+ char wk1[1];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short ADRFMT:1;\r
+ unsigned short :9;\r
+ unsigned short ACE:1;\r
+ } BIT;\r
+ } ADCER;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :4;\r
+ unsigned char ADSTRS:4;\r
+ } BIT;\r
+ } ADSTRGR;\r
+ char wk2[1];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :6;\r
+ unsigned short OCS:1;\r
+ unsigned short TSS:1;\r
+ unsigned short :6;\r
+ unsigned short OCSAD:1;\r
+ unsigned short TSSAD:1;\r
+ } BIT;\r
+ } ADEXICR;\r
+ char wk3[6];\r
+ unsigned short ADTSDR;\r
+ unsigned short ADOCDR;\r
+ char wk4[2];\r
+ unsigned short ADDR0;\r
+ unsigned short ADDR1;\r
+ unsigned short ADDR2;\r
+ unsigned short ADDR3;\r
+ unsigned short ADDR4;\r
+ unsigned short ADDR5;\r
+ unsigned short ADDR6;\r
+ unsigned short ADDR7;\r
+ unsigned short ADDR8;\r
+ unsigned short ADDR9;\r
+ unsigned short ADDR10;\r
+ unsigned short ADDR11;\r
+ unsigned short ADDR12;\r
+ unsigned short ADDR13;\r
+ unsigned short ADDR14;\r
+ unsigned short ADDR15;\r
+ unsigned short ADDR16;\r
+ unsigned short ADDR17;\r
+ unsigned short ADDR18;\r
+ unsigned short ADDR19;\r
+ unsigned short ADDR20;\r
+ char wk5[38];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short SST2:8;\r
+ } BIT;\r
+ } ADSSTR23;\r
+};\r
+\r
+struct st_sci0 {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char CM:1;\r
+ unsigned char CHR:1;\r
+ unsigned char PE:1;\r
+ unsigned char PM:1;\r
+ unsigned char STOP:1;\r
+ unsigned char MP:1;\r
+ unsigned char CKS:2;\r
+ } BIT;\r
+ } SMR;\r
+ unsigned char BRR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TIE:1;\r
+ unsigned char RIE:1;\r
+ unsigned char TE:1;\r
+ unsigned char RE:1;\r
+ unsigned char MPIE:1;\r
+ unsigned char TEIE:1;\r
+ unsigned char CKE:2;\r
+ } BIT;\r
+ } SCR;\r
+ unsigned char TDR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char ORER:1;\r
+ unsigned char FER:1;\r
+ unsigned char PER:1;\r
+ unsigned char TEND:1;\r
+ unsigned char MPB:1;\r
+ unsigned char MPBT:1;\r
+ } BIT;\r
+ } SSR;\r
+ unsigned char RDR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char BCP2:1;\r
+ unsigned char :3;\r
+ unsigned char SDIR:1;\r
+ unsigned char SINV:1;\r
+ unsigned char :1;\r
+ unsigned char SMIF:1;\r
+ } BIT;\r
+ } SCMR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char NFEN:1;\r
+ unsigned char ABCS:1;\r
+ unsigned char :3;\r
+ unsigned char ACS0:1;\r
+ } BIT;\r
+ } SEMR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char NFCS:3;\r
+ } BIT;\r
+ } SNFR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char IICDL:5;\r
+ unsigned char :2;\r
+ unsigned char IICM:1;\r
+ } BIT;\r
+ } SIMR1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char IICACKT:1;\r
+ unsigned char :3;\r
+ unsigned char IICCSC:1;\r
+ unsigned char IICINTM:1;\r
+ } BIT;\r
+ } SIMR2;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char IICSCLS:2;\r
+ unsigned char IICSDAS:2;\r
+ unsigned char IICSTIF:1;\r
+ unsigned char IICSTPREQ:1;\r
+ unsigned char IICRSTAREQ:1;\r
+ unsigned char IICSTAREQ:1;\r
+ } BIT;\r
+ } SIMR3;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char IICACKR:1;\r
+ } BIT;\r
+ } SISR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char CKPH:1;\r
+ unsigned char CKPOL:1;\r
+ unsigned char :1;\r
+ unsigned char MFF:1;\r
+ unsigned char :1;\r
+ unsigned char MSS:1;\r
+ unsigned char CTSE:1;\r
+ unsigned char SSE:1;\r
+ } BIT;\r
+ } SPMR;\r
+};\r
+\r
+struct st_sci7 {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char CM:1;\r
+ unsigned char CHR:1;\r
+ unsigned char PE:1;\r
+ unsigned char PM:1;\r
+ unsigned char STOP:1;\r
+ unsigned char MP:1;\r
+ unsigned char CKS:2;\r
+ } BIT;\r
+ } SMR;\r
+ unsigned char BRR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TIE:1;\r
+ unsigned char RIE:1;\r
+ unsigned char TE:1;\r
+ unsigned char RE:1;\r
+ unsigned char MPIE:1;\r
+ unsigned char TEIE:1;\r
+ unsigned char CKE:2;\r
+ } BIT;\r
+ } SCR;\r
+ unsigned char TDR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char ORER:1;\r
+ unsigned char FER:1;\r
+ unsigned char PER:1;\r
+ unsigned char TEND:1;\r
+ unsigned char MPB:1;\r
+ unsigned char MPBT:1;\r
+ } BIT;\r
+ } SSR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :6;\r
+ unsigned char MPB:1;\r
+ unsigned char MPBT:1;\r
+ } BIT;\r
+ } RDR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char BCP2:1;\r
+ unsigned char :3;\r
+ unsigned char SDIR:1;\r
+ unsigned char SINV:1;\r
+ unsigned char :1;\r
+ unsigned char SMIF:1;\r
+ } BIT;\r
+ } SCMR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char NFEN:1;\r
+ unsigned char ABCS:1;\r
+ unsigned char :3;\r
+ unsigned char ACS0:1;\r
+ } BIT;\r
+ } SEMR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char NFCS:3;\r
+ } BIT;\r
+ } SNFR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char IICDL:5;\r
+ unsigned char :2;\r
+ unsigned char IICM:1;\r
+ } BIT;\r
+ } SIMR1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char IICACKT:1;\r
+ unsigned char :3;\r
+ unsigned char IICCSC:1;\r
+ unsigned char IICINTM:1;\r
+ } BIT;\r
+ } SIMR2;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char IICSCLS:2;\r
+ unsigned char IICSDAS:2;\r
+ unsigned char IICSTIF:1;\r
+ unsigned char IICSTPREQ:1;\r
+ unsigned char IICRSTAREQ:1;\r
+ unsigned char IICSTAREQ:1;\r
+ } BIT;\r
+ } SIMR3;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char IICACKR:1;\r
+ } BIT;\r
+ } SISR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char CKPH:1;\r
+ unsigned char CKPOL:1;\r
+ unsigned char :1;\r
+ unsigned char MFF:1;\r
+ unsigned char :1;\r
+ unsigned char MSS:1;\r
+ unsigned char CTSE:1;\r
+ unsigned char SSE:1;\r
+ } BIT;\r
+ } SPMR;\r
+};\r
+\r
+struct st_sci12 {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char CM:1;\r
+ unsigned char CHR:1;\r
+ unsigned char PE:1;\r
+ unsigned char PM:1;\r
+ unsigned char STOP:1;\r
+ unsigned char MP:1;\r
+ unsigned char CKS:2;\r
+ } BIT;\r
+ } SMR;\r
+ unsigned char BRR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TIE:1;\r
+ unsigned char RIE:1;\r
+ unsigned char TE:1;\r
+ unsigned char RE:1;\r
+ unsigned char MPIE:1;\r
+ unsigned char TEIE:1;\r
+ unsigned char CKE:2;\r
+ } BIT;\r
+ } SCR;\r
+ unsigned char TDR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char ORER:1;\r
+ unsigned char FER:1;\r
+ unsigned char PER:1;\r
+ unsigned char TEND:1;\r
+ unsigned char MPB:1;\r
+ unsigned char MPBT:1;\r
+ } BIT;\r
+ } SSR;\r
+ unsigned char RDR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char BCP2:1;\r
+ unsigned char :3;\r
+ unsigned char SDIR:1;\r
+ unsigned char SINV:1;\r
+ unsigned char :1;\r
+ unsigned char SMIF:1;\r
+ } BIT;\r
+ } SCMR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char NFEN:1;\r
+ unsigned char ABCS:1;\r
+ unsigned char :3;\r
+ unsigned char ACS0:1;\r
+ } BIT;\r
+ } SEMR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char NFCS:3;\r
+ } BIT;\r
+ } SNFR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char IICDL:5;\r
+ unsigned char :2;\r
+ unsigned char IICM:1;\r
+ } BIT;\r
+ } SIMR1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char IICACKT:1;\r
+ unsigned char :3;\r
+ unsigned char IICCSC:1;\r
+ unsigned char IICINTM:1;\r
+ } BIT;\r
+ } SIMR2;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char IICSCLS:2;\r
+ unsigned char IICSDAS:2;\r
+ unsigned char IICSTIF:1;\r
+ unsigned char IICSTPREQ:1;\r
+ unsigned char IICRSTAREQ:1;\r
+ unsigned char IICSTAREQ:1;\r
+ } BIT;\r
+ } SIMR3;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char IICACKR:1;\r
+ } BIT;\r
+ } SISR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char CKPH:1;\r
+ unsigned char CKPOL:1;\r
+ unsigned char :1;\r
+ unsigned char MFF:1;\r
+ unsigned char :1;\r
+ unsigned char MSS:1;\r
+ unsigned char CTSE:1;\r
+ unsigned char SSE:1;\r
+ } BIT;\r
+ } SPMR;\r
+ char wk0[18];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char ESME:1;\r
+ } BIT;\r
+ } ESMER;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :4;\r
+ unsigned char BRME:1;\r
+ unsigned char RXDSF:1;\r
+ unsigned char SFSF:1;\r
+ } BIT;\r
+ } CR0;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char PIBS:3;\r
+ unsigned char PIBE:1;\r
+ unsigned char CF1DS:2;\r
+ unsigned char CF0RE:1;\r
+ unsigned char BFE:1;\r
+ } BIT;\r
+ } CR1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char RTS:2;\r
+ unsigned char BCCS:2;\r
+ unsigned char :1;\r
+ unsigned char DFCS:3;\r
+ } BIT;\r
+ } CR2;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char SDST:1;\r
+ } BIT;\r
+ } CR3;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char SHARPS:1;\r
+ unsigned char :2;\r
+ unsigned char RXDXPS:1;\r
+ unsigned char TXDXPS:1;\r
+ } BIT;\r
+ } PCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char AEDIE:1;\r
+ unsigned char BCDIE:1;\r
+ unsigned char PIBDIE:1;\r
+ unsigned char CF1MIE:1;\r
+ unsigned char CF0MIE:1;\r
+ unsigned char BFDIE:1;\r
+ } BIT;\r
+ } ICR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char AEDF:1;\r
+ unsigned char BCDF:1;\r
+ unsigned char PIBDF:1;\r
+ unsigned char CF1MF:1;\r
+ unsigned char CF0MF:1;\r
+ unsigned char BFDF:1;\r
+ } BIT;\r
+ } STR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char AEDCL:1;\r
+ unsigned char BCDCL:1;\r
+ unsigned char PIBDCL:1;\r
+ unsigned char CF1MCL:1;\r
+ unsigned char CF0MCL:1;\r
+ unsigned char BFDCL:1;\r
+ } BIT;\r
+ } STCR;\r
+ unsigned char CF0DR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char CF0CE7:1;\r
+ unsigned char CF0CE6:1;\r
+ unsigned char CF0CE5:1;\r
+ unsigned char CF0CE4:1;\r
+ unsigned char CF0CE3:1;\r
+ unsigned char CF0CE2:1;\r
+ unsigned char CF0CE1:1;\r
+ unsigned char CF0CE0:1;\r
+ } BIT;\r
+ } CF0CR;\r
+ unsigned char CF0RR;\r
+ unsigned char PCF1DR;\r
+ unsigned char SCF1DR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char CF1CE7:1;\r
+ unsigned char CF1CE6:1;\r
+ unsigned char CF1CE5:1;\r
+ unsigned char CF1CE4:1;\r
+ unsigned char CF1CE3:1;\r
+ unsigned char CF1CE2:1;\r
+ unsigned char CF1CE1:1;\r
+ unsigned char CF1CE0:1;\r
+ } BIT;\r
+ } CF1CR;\r
+ unsigned char CF1RR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char TCST:1;\r
+ } BIT;\r
+ } TCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char TCSS:3;\r
+ unsigned char TWRC:1;\r
+ unsigned char :1;\r
+ unsigned char TOMS:2;\r
+ } BIT;\r
+ } TMR;\r
+ unsigned char TPRE;\r
+ unsigned char TCNT;\r
+};\r
+\r
+struct st_smci0 {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char GM:1;\r
+ unsigned char BCLK:1;\r
+ unsigned char PE:1;\r
+ unsigned char PM:1;\r
+ unsigned char BCP:2;\r
+ unsigned char CKS:2;\r
+ } BIT;\r
+ } SMR;\r
+ unsigned char BRR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TIE:1;\r
+ unsigned char RIE:1;\r
+ unsigned char TE:1;\r
+ unsigned char RE:1;\r
+ unsigned char MPIE:1;\r
+ unsigned char TEIE:1;\r
+ unsigned char CKE:2;\r
+ } BIT;\r
+ } SCR;\r
+ unsigned char TDR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char ORER:1;\r
+ unsigned char ERS:1;\r
+ unsigned char PER:1;\r
+ unsigned char TEND:1;\r
+ unsigned char MPB:1;\r
+ unsigned char MPBT:1;\r
+ } BIT;\r
+ } SSR;\r
+ unsigned char RDR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char BCP2:1;\r
+ unsigned char :3;\r
+ unsigned char SDIR:1;\r
+ unsigned char SINV:1;\r
+ unsigned char :1;\r
+ unsigned char SMIF:1;\r
+ } BIT;\r
+ } SCMR;\r
+};\r
+\r
+struct st_smci7 {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char GM:1;\r
+ unsigned char BCLK:1;\r
+ unsigned char PE:1;\r
+ unsigned char PM:1;\r
+ unsigned char BCP:2;\r
+ unsigned char CKS:2;\r
+ } BIT;\r
+ } SMR;\r
+ unsigned char BRR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TIE:1;\r
+ unsigned char RIE:1;\r
+ unsigned char TE:1;\r
+ unsigned char RE:1;\r
+ unsigned char MPIE:1;\r
+ unsigned char TEIE:1;\r
+ unsigned char CKE:2;\r
+ } BIT;\r
+ } SCR;\r
+ unsigned char TDR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char ORER:1;\r
+ unsigned char ERS:1;\r
+ unsigned char PER:1;\r
+ unsigned char TEND:1;\r
+ } BIT;\r
+ } SSR;\r
+ unsigned char RDR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char BCP2:1;\r
+ unsigned char :3;\r
+ unsigned char SDIR:1;\r
+ unsigned char SINV:1;\r
+ unsigned char :1;\r
+ unsigned char SMIF:1;\r
+ } BIT;\r
+ } SCMR;\r
+};\r
+\r
+struct st_system {\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :15;\r
+ unsigned short MD:1;\r
+ } BIT;\r
+ } MDMONR;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :10;\r
+ unsigned short UBTS:1;\r
+ unsigned short BOTS:1;\r
+ unsigned short :2;\r
+ unsigned short EXB:1;\r
+ unsigned short IROM:1;\r
+ } BIT;\r
+ } MDSR;\r
+ char wk0[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short KEY:8;\r
+ unsigned short :6;\r
+ unsigned short EXBE:1;\r
+ unsigned short ROME:1;\r
+ } BIT;\r
+ } SYSCR0;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :15;\r
+ unsigned short RAME:1;\r
+ } BIT;\r
+ } SYSCR1;\r
+ char wk1[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short SSBY:1;\r
+ unsigned short OPE:1;\r
+ } BIT;\r
+ } SBYCR;\r
+ char wk2[2];\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned long ACSE:1;\r
+ unsigned long :1;\r
+ unsigned long MSTPA29:1;\r
+ unsigned long MSTPA28:1;\r
+ unsigned long MSTPA27:1;\r
+ unsigned long :2;\r
+ unsigned long MSTPA24:1;\r
+ unsigned long MSTPA23:1;\r
+ unsigned long :3;\r
+ unsigned long MSTPA19:1;\r
+ unsigned long :1;\r
+ unsigned long MSTPA17:1;\r
+ unsigned long :1;\r
+ unsigned long MSTPA15:1;\r
+ unsigned long MSTPA14:1;\r
+ unsigned long MSTPA13:1;\r
+ unsigned long MSTPA12:1;\r
+ unsigned long MSTPA11:1;\r
+ unsigned long MSTPA10:1;\r
+ unsigned long MSTPA9:1;\r
+ unsigned long :3;\r
+ unsigned long MSTPA5:1;\r
+ unsigned long MSTPA4:1;\r
+ } BIT;\r
+ } MSTPCRA;\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned long MSTPB31:1;\r
+ unsigned long MSTPB30:1;\r
+ unsigned long MSTPB29:1;\r
+ unsigned long MSTPB28:1;\r
+ unsigned long MSTPB27:1;\r
+ unsigned long MSTPB26:1;\r
+ unsigned long MSTPB25:1;\r
+ unsigned long MSTPB24:1;\r
+ unsigned long MSTPB23:1;\r
+ unsigned long :1;\r
+ unsigned long MSTPB21:1;\r
+ unsigned long MSTPB20:1;\r
+ unsigned long MSTPB19:1;\r
+ unsigned long :1;\r
+ unsigned long MSTPB17:1;\r
+ unsigned long MSTPB16:1;\r
+ unsigned long :7;\r
+ unsigned long MSTPB8:1;\r
+ unsigned long :3;\r
+ unsigned long MSTPB4:1;\r
+ unsigned long :1;\r
+ unsigned long MSTPB2:1;\r
+ unsigned long MSTPB1:1;\r
+ unsigned long MSTPB0:1;\r
+ } BIT;\r
+ } MSTPCRB;\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned long :4;\r
+ unsigned long MSTPC27:1;\r
+ unsigned long MSTPC26:1;\r
+ unsigned long MSTPC25:1;\r
+ unsigned long MSTPC24:1;\r
+ unsigned long :1;\r
+ unsigned long MSTPC22:1;\r
+ unsigned long :2;\r
+ unsigned long MSTPC19:1;\r
+ unsigned long MSTPC18:1;\r
+ unsigned long MSTPC17:1;\r
+ unsigned long MSTPC16:1;\r
+ unsigned long :14;\r
+ unsigned long MSTPC1:1;\r
+ unsigned long MSTPC0:1;\r
+ } BIT;\r
+ } MSTPCRC;\r
+ char wk3[4];\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned long FCK:4;\r
+ unsigned long ICK:4;\r
+ unsigned long PSTOP1:1;\r
+ unsigned long :3;\r
+ unsigned long BCK:4;\r
+ unsigned long :4;\r
+ unsigned long PCKB:4;\r
+ } BIT;\r
+ } SCKCR;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :8;\r
+ unsigned short UCK:4;\r
+ unsigned short IEBCK:4;\r
+ } BIT;\r
+ } SCKCR2;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :5;\r
+ unsigned short CKSEL:3;\r
+ } BIT;\r
+ } SCKCR3;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :2;\r
+ unsigned short STC:6;\r
+ unsigned short :6;\r
+ unsigned short PLIDIV:2;\r
+ } BIT;\r
+ } PLLCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char PLLEN:1;\r
+ } BIT;\r
+ } PLLCR2;\r
+ char wk4[5];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char BCLKDIV:1;\r
+ } BIT;\r
+ } BCKCR;\r
+ char wk5[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char MOSTP:1;\r
+ } BIT;\r
+ } MOSCCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char SOSTP:1;\r
+ } BIT;\r
+ } SOSCCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char LCSTP:1;\r
+ } BIT;\r
+ } LOCOCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char ILCSTP:1;\r
+ } BIT;\r
+ } ILOCOCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char HCSTP:1;\r
+ } BIT;\r
+ } HOCOCR;\r
+ char wk6[9];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char OSTDE:1;\r
+ unsigned char :6;\r
+ unsigned char OSTDIE:1;\r
+ } BIT;\r
+ } OSTDCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char OSTDF:1;\r
+ } BIT;\r
+ } OSTDSR;\r
+ char wk7[94];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char OPCMTSF:1;\r
+ unsigned char :1;\r
+ unsigned char OPCM:3;\r
+ } BIT;\r
+ } OPCCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char RSTCKEN:1;\r
+ unsigned char :4;\r
+ unsigned char RSTCKSEL:3;\r
+ } BIT;\r
+ } RSTCKCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char MSTS:5;\r
+ } BIT;\r
+ } MOSCWTCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char SSTS:5;\r
+ } BIT;\r
+ } SOSCWTCR;\r
+ char wk8[2];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSTS:5;\r
+ } BIT;\r
+ } PLLWTCR;\r
+ char wk9[25];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char SWRF:1;\r
+ unsigned char WDTRF:1;\r
+ unsigned char IWTDRF:1;\r
+ } BIT;\r
+ } RSTSR2;\r
+ char wk10[1];\r
+ unsigned short SWRR;\r
+ char wk11[28];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :6;\r
+ unsigned char LVD1IDTSEL:2;\r
+ } BIT;\r
+ } LVD1CR1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :6;\r
+ unsigned char LVD1MON:1;\r
+ unsigned char LVD1DET:1;\r
+ } BIT;\r
+ } LVD1SR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :6;\r
+ unsigned char LVD2IDTSEL:2;\r
+ } BIT;\r
+ } LVD2CR1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :6;\r
+ unsigned char LVD2MON:1;\r
+ unsigned char LVD2DET:1;\r
+ } BIT;\r
+ } LVD2SR;\r
+ char wk12[794];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short PRKEY:8;\r
+ unsigned short :4;\r
+ unsigned short PRC3:1;\r
+ unsigned short :1;\r
+ unsigned short PRC1:1;\r
+ unsigned short PRC0:1;\r
+ } BIT;\r
+ } PRCR;\r
+ char wk13[48768];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char DPSBY:1;\r
+ unsigned char IOKEEP:1;\r
+ unsigned char :4;\r
+ unsigned char DEEPCUT:2;\r
+ } BIT;\r
+ } DPSBYCR;\r
+ char wk14[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char DIRQ7E:1;\r
+ unsigned char DIRQ6E:1;\r
+ unsigned char DIRQ5E:1;\r
+ unsigned char DIRQ4E:1;\r
+ unsigned char DIRQ3E:1;\r
+ unsigned char DIRQ2E:1;\r
+ unsigned char DIRQ1E:1;\r
+ unsigned char DIRQ0E:1;\r
+ } BIT;\r
+ } DPSIER0;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char DIRQ15E:1;\r
+ unsigned char DIRQ14E:1;\r
+ unsigned char DIRQ13E:1;\r
+ unsigned char DIRQ12E:1;\r
+ unsigned char DIRQ11E:1;\r
+ unsigned char DIRQ10E:1;\r
+ unsigned char DIRQ9E:1;\r
+ unsigned char DIRQ8E:1;\r
+ } BIT;\r
+ } DPSIER1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char DUSBIE:1;\r
+ unsigned char DIICCIE:1;\r
+ unsigned char DIICDIE:1;\r
+ unsigned char DNMIE:1;\r
+ unsigned char DRTCAIE:1;\r
+ unsigned char DRTCIIE:1;\r
+ unsigned char DLVD2IE:1;\r
+ unsigned char DLVD1IE:1;\r
+ } BIT;\r
+ } DPSIER2;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char DCANIE:1;\r
+ } BIT;\r
+ } DPSIER3;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char DIRQ7F:1;\r
+ unsigned char DIRQ6F:1;\r
+ unsigned char DIRQ5F:1;\r
+ unsigned char DIRQ4F:1;\r
+ unsigned char DIRQ3F:1;\r
+ unsigned char DIRQ2F:1;\r
+ unsigned char DIRQ1F:1;\r
+ unsigned char DIRQ0F:1;\r
+ } BIT;\r
+ } DPSIFR0;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char DIRQ15F:1;\r
+ unsigned char DIRQ14F:1;\r
+ unsigned char DIRQ13F:1;\r
+ unsigned char DIRQ12F:1;\r
+ unsigned char DIRQ11F:1;\r
+ unsigned char DIRQ10F:1;\r
+ unsigned char DIRQ9F:1;\r
+ unsigned char DIRQ8F:1;\r
+ } BIT;\r
+ } DPSIFR1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char DUSBIF:1;\r
+ unsigned char DIICCIF:1;\r
+ unsigned char DIICDIF:1;\r
+ unsigned char DNMIF:1;\r
+ unsigned char DRTCAIF:1;\r
+ unsigned char DRTCIIF:1;\r
+ unsigned char DLVD2IF:1;\r
+ unsigned char DLVD1IF:1;\r
+ } BIT;\r
+ } DPSIFR2;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char DCANIF:1;\r
+ } BIT;\r
+ } DPSIFR3;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char DIRQ7EG:1;\r
+ unsigned char DIRQ6EG:1;\r
+ unsigned char DIRQ5EG:1;\r
+ unsigned char DIRQ4EG:1;\r
+ unsigned char DIRQ3EG:1;\r
+ unsigned char DIRQ2EG:1;\r
+ unsigned char DIRQ1EG:1;\r
+ unsigned char DIRQ0EG:1;\r
+ } BIT;\r
+ } DPSIEGR0;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char DIRQ15EG:1;\r
+ unsigned char DIRQ14EG:1;\r
+ unsigned char DIRQ13EG:1;\r
+ unsigned char DIRQ12EG:1;\r
+ unsigned char DIRQ11EG:1;\r
+ unsigned char DIRQ10EG:1;\r
+ unsigned char DIRQ9EG:1;\r
+ unsigned char DIRQ8EG:1;\r
+ } BIT;\r
+ } DPSIEGR1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char DIICCEG:1;\r
+ unsigned char DIICDEG:1;\r
+ unsigned char DNMIEG:1;\r
+ unsigned char :2;\r
+ unsigned char DLVD2EG:1;\r
+ unsigned char DLVD1EG:1;\r
+ } BIT;\r
+ } DPSIEGR2;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char DCANIEG:1;\r
+ } BIT;\r
+ } DPSIEGR3;\r
+ char wk15[2];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char DPSRSTF:1;\r
+ unsigned char :3;\r
+ unsigned char LVD2RF:1;\r
+ unsigned char LVD1RF:1;\r
+ unsigned char LVD0RF:1;\r
+ unsigned char PORF:1;\r
+ } BIT;\r
+ } RSTSR0;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char CWSF:1;\r
+ } BIT;\r
+ } RSTSR1;\r
+ char wk16[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char MOFXIN:1;\r
+ } BIT;\r
+ } MOFCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char HOCOPCNT:1;\r
+ } BIT;\r
+ } HOCOPCR;\r
+ char wk17[2];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char LVD2E:1;\r
+ unsigned char LVD1E:1;\r
+ } BIT;\r
+ } LVCMPCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char LVD2LVL:4;\r
+ unsigned char LVD1LVL:4;\r
+ } BIT;\r
+ } LVDLVLR;\r
+ char wk18[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char LVD1RN:1;\r
+ unsigned char LVD1RI:1;\r
+ unsigned char LVD1FSAMP:2;\r
+ unsigned char :1;\r
+ unsigned char LVD1CMPE:1;\r
+ unsigned char LVD1DFDIS:1;\r
+ unsigned char LVD1RIE:1;\r
+ } BIT;\r
+ } LVD1CR0;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char LVD2RN:1;\r
+ unsigned char LVD2RI:1;\r
+ unsigned char LVD2FSAMP:2;\r
+ unsigned char :1;\r
+ unsigned char LVD2CMPE:1;\r
+ unsigned char LVD2DFDIS:1;\r
+ unsigned char LVD2RIE:1;\r
+ } BIT;\r
+ } LVD2CR0;\r
+ char wk19[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char VBATTMNSEL:1;\r
+ } BIT;\r
+ } VBATTMNSELR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char VBATTMON:1;\r
+ } BIT;\r
+ } VBATTMONR;\r
+ char wk20[1];\r
+ unsigned char DPSBKR[32];\r
+ char wk21[1472];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :6;\r
+ unsigned char SCK:2;\r
+ } BIT;\r
+ } SCK1;\r
+ char wk22[15];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :6;\r
+ unsigned char SCK:2;\r
+ } BIT;\r
+ } SCK2;\r
+};\r
+\r
+struct st_temps {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TSEN:1;\r
+ unsigned char :2;\r
+ unsigned char TSOE:1;\r
+ } BIT;\r
+ } TSCR;\r
+};\r
+\r
+struct st_tmr0 {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char CMIEB:1;\r
+ unsigned char CMIEA:1;\r
+ unsigned char OVIE:1;\r
+ unsigned char CCLR:2;\r
+ } BIT;\r
+ } TCR;\r
+ char wk0[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char ADTE:1;\r
+ unsigned char OSB:2;\r
+ unsigned char OSA:2;\r
+ } BIT;\r
+ } TCSR;\r
+ char wk1[1];\r
+ unsigned char TCORA;\r
+ char wk2[1];\r
+ unsigned char TCORB;\r
+ char wk3[1];\r
+ unsigned char TCNT;\r
+ char wk4[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TMRIS:1;\r
+ unsigned char :2;\r
+ unsigned char CSS:2;\r
+ unsigned char CKS:3;\r
+ } BIT;\r
+ } TCCR;\r
+};\r
+\r
+struct st_tmr1 {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char CMIEB:1;\r
+ unsigned char CMIEA:1;\r
+ unsigned char OVIE:1;\r
+ unsigned char CCLR:2;\r
+ } BIT;\r
+ } TCR;\r
+ char wk0[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :4;\r
+ unsigned char OSB:2;\r
+ unsigned char OSA:2;\r
+ } BIT;\r
+ } TCSR;\r
+ char wk1[1];\r
+ unsigned char TCORA;\r
+ char wk2[1];\r
+ unsigned char TCORB;\r
+ char wk3[1];\r
+ unsigned char TCNT;\r
+ char wk4[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TMRIS:1;\r
+ unsigned char :2;\r
+ unsigned char CSS:2;\r
+ unsigned char CKS:3;\r
+ } BIT;\r
+ } TCCR;\r
+};\r
+\r
+struct st_tmr01 {\r
+ unsigned short TCORA;\r
+ unsigned short TCORB;\r
+ unsigned short TCNT;\r
+ unsigned short TCCR;\r
+};\r
+\r
+struct st_tpu0 {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char NFCS:2;\r
+ unsigned char NFDEN:1;\r
+ unsigned char NFCEN:1;\r
+ unsigned char NFBEN:1;\r
+ unsigned char NFAEN:1;\r
+ } BIT;\r
+ } NFCR;\r
+ char wk0[7];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char CCLR:3;\r
+ unsigned char CKEG:2;\r
+ unsigned char TPSC:3;\r
+ } BIT;\r
+ } TCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ICSELD:1;\r
+ unsigned char ICSELB:1;\r
+ unsigned char BFB:1;\r
+ unsigned char BFA:1;\r
+ unsigned char MD:4;\r
+ } BIT;\r
+ } TMDR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char IOB:4;\r
+ unsigned char IOA:4;\r
+ } BIT;\r
+ } TIORH;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char IOD:4;\r
+ unsigned char IOC:4;\r
+ } BIT;\r
+ } TIORL;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TTGE:1;\r
+ unsigned char :1;\r
+ unsigned char TCIEU:1;\r
+ unsigned char TCIEV:1;\r
+ unsigned char TGIED:1;\r
+ unsigned char TGIEC:1;\r
+ unsigned char TGIEB:1;\r
+ unsigned char TGIEA:1;\r
+ } BIT;\r
+ } TIER;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TCFD:1;\r
+ unsigned char :1;\r
+ unsigned char TCFU:1;\r
+ unsigned char TCFV:1;\r
+ unsigned char TGFD:1;\r
+ unsigned char TGFC:1;\r
+ unsigned char TGFB:1;\r
+ unsigned char TGFA:1;\r
+ } BIT;\r
+ } TSR;\r
+ unsigned short TCNT;\r
+ unsigned short TGRA;\r
+ unsigned short TGRB;\r
+ unsigned short TGRC;\r
+ unsigned short TGRD;\r
+};\r
+\r
+struct st_tpu1 {\r
+ char wk0[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char NFCS:2;\r
+ unsigned char NFDEN:1;\r
+ unsigned char NFCEN:1;\r
+ unsigned char NFBEN:1;\r
+ unsigned char NFAEN:1;\r
+ } BIT;\r
+ } NFCR;\r
+ char wk1[22];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char CCLR:3;\r
+ unsigned char CKEG:2;\r
+ unsigned char TPSC:3;\r
+ } BIT;\r
+ } TCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ICSELD:1;\r
+ unsigned char ICSELB:1;\r
+ unsigned char BFB:1;\r
+ unsigned char BFA:1;\r
+ unsigned char MD:4;\r
+ } BIT;\r
+ } TMDR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char IOB:4;\r
+ unsigned char IOA:4;\r
+ } BIT;\r
+ } TIOR;\r
+ char wk2[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TTGE:1;\r
+ unsigned char :1;\r
+ unsigned char TCIEU:1;\r
+ unsigned char TCIEV:1;\r
+ unsigned char TGIED:1;\r
+ unsigned char TGIEC:1;\r
+ unsigned char TGIEB:1;\r
+ unsigned char TGIEA:1;\r
+ } BIT;\r
+ } TIER;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TCFD:1;\r
+ unsigned char :1;\r
+ unsigned char TCFU:1;\r
+ unsigned char TCFV:1;\r
+ unsigned char TGFD:1;\r
+ unsigned char TGFC:1;\r
+ unsigned char TGFB:1;\r
+ unsigned char TGFA:1;\r
+ } BIT;\r
+ } TSR;\r
+ unsigned short TCNT;\r
+ unsigned short TGRA;\r
+ unsigned short TGRB;\r
+};\r
+\r
+struct st_tpu2 {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char NFCS:2;\r
+ unsigned char NFDEN:1;\r
+ unsigned char NFCEN:1;\r
+ unsigned char NFBEN:1;\r
+ unsigned char NFAEN:1;\r
+ } BIT;\r
+ } NFCR;\r
+ char wk0[37];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char CCLR:3;\r
+ unsigned char CKEG:2;\r
+ unsigned char TPSC:3;\r
+ } BIT;\r
+ } TCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ICSELD:1;\r
+ unsigned char ICSELB:1;\r
+ unsigned char BFB:1;\r
+ unsigned char BFA:1;\r
+ unsigned char MD:4;\r
+ } BIT;\r
+ } TMDR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char IOB:4;\r
+ unsigned char IOA:4;\r
+ } BIT;\r
+ } TIOR;\r
+ char wk1[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TTGE:1;\r
+ unsigned char :1;\r
+ unsigned char TCIEU:1;\r
+ unsigned char TCIEV:1;\r
+ unsigned char TGIED:1;\r
+ unsigned char TGIEC:1;\r
+ unsigned char TGIEB:1;\r
+ unsigned char TGIEA:1;\r
+ } BIT;\r
+ } TIER;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TCFD:1;\r
+ unsigned char :1;\r
+ unsigned char TCFU:1;\r
+ unsigned char TCFV:1;\r
+ unsigned char TGFD:1;\r
+ unsigned char TGFC:1;\r
+ unsigned char TGFB:1;\r
+ unsigned char TGFA:1;\r
+ } BIT;\r
+ } TSR;\r
+ unsigned short TCNT;\r
+ unsigned short TGRA;\r
+ unsigned short TGRB;\r
+};\r
+\r
+struct st_tpu3 {\r
+ char wk0[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char NFCS:2;\r
+ unsigned char NFDEN:1;\r
+ unsigned char NFCEN:1;\r
+ unsigned char NFBEN:1;\r
+ unsigned char NFAEN:1;\r
+ } BIT;\r
+ } NFCR;\r
+ char wk1[52];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char CCLR:3;\r
+ unsigned char CKEG:2;\r
+ unsigned char TPSC:3;\r
+ } BIT;\r
+ } TCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ICSELD:1;\r
+ unsigned char ICSELB:1;\r
+ unsigned char BFB:1;\r
+ unsigned char BFA:1;\r
+ unsigned char MD:4;\r
+ } BIT;\r
+ } TMDR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char IOB:4;\r
+ unsigned char IOA:4;\r
+ } BIT;\r
+ } TIORH;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char IOD:4;\r
+ unsigned char IOC:4;\r
+ } BIT;\r
+ } TIORL;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TTGE:1;\r
+ unsigned char :1;\r
+ unsigned char TCIEU:1;\r
+ unsigned char TCIEV:1;\r
+ unsigned char TGIED:1;\r
+ unsigned char TGIEC:1;\r
+ unsigned char TGIEB:1;\r
+ unsigned char TGIEA:1;\r
+ } BIT;\r
+ } TIER;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TCFD:1;\r
+ unsigned char :1;\r
+ unsigned char TCFU:1;\r
+ unsigned char TCFV:1;\r
+ unsigned char TGFD:1;\r
+ unsigned char TGFC:1;\r
+ unsigned char TGFB:1;\r
+ unsigned char TGFA:1;\r
+ } BIT;\r
+ } TSR;\r
+ unsigned short TCNT;\r
+ unsigned short TGRA;\r
+ unsigned short TGRB;\r
+ unsigned short TGRC;\r
+ unsigned short TGRD;\r
+};\r
+\r
+struct st_tpu4 {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char NFCS:2;\r
+ unsigned char NFDEN:1;\r
+ unsigned char NFCEN:1;\r
+ unsigned char NFBEN:1;\r
+ unsigned char NFAEN:1;\r
+ } BIT;\r
+ } NFCR;\r
+ char wk0[67];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char CCLR:3;\r
+ unsigned char CKEG:2;\r
+ unsigned char TPSC:3;\r
+ } BIT;\r
+ } TCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ICSELD:1;\r
+ unsigned char ICSELB:1;\r
+ unsigned char BFB:1;\r
+ unsigned char BFA:1;\r
+ unsigned char MD:4;\r
+ } BIT;\r
+ } TMDR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char IOB:4;\r
+ unsigned char IOA:4;\r
+ } BIT;\r
+ } TIOR;\r
+ char wk1[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TTGE:1;\r
+ unsigned char :1;\r
+ unsigned char TCIEU:1;\r
+ unsigned char TCIEV:1;\r
+ unsigned char TGIED:1;\r
+ unsigned char TGIEC:1;\r
+ unsigned char TGIEB:1;\r
+ unsigned char TGIEA:1;\r
+ } BIT;\r
+ } TIER;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TCFD:1;\r
+ unsigned char :1;\r
+ unsigned char TCFU:1;\r
+ unsigned char TCFV:1;\r
+ unsigned char TGFD:1;\r
+ unsigned char TGFC:1;\r
+ unsigned char TGFB:1;\r
+ unsigned char TGFA:1;\r
+ } BIT;\r
+ } TSR;\r
+ unsigned short TCNT;\r
+ unsigned short TGRA;\r
+ unsigned short TGRB;\r
+};\r
+\r
+struct st_tpu5 {\r
+ char wk0[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char NFCS:2;\r
+ unsigned char NFDEN:1;\r
+ unsigned char NFCEN:1;\r
+ unsigned char NFBEN:1;\r
+ unsigned char NFAEN:1;\r
+ } BIT;\r
+ } NFCR;\r
+ char wk1[82];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char CCLR:3;\r
+ unsigned char CKEG:2;\r
+ unsigned char TPSC:3;\r
+ } BIT;\r
+ } TCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ICSELD:1;\r
+ unsigned char ICSELB:1;\r
+ unsigned char BFB:1;\r
+ unsigned char BFA:1;\r
+ unsigned char MD:4;\r
+ } BIT;\r
+ } TMDR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char IOB:4;\r
+ unsigned char IOA:4;\r
+ } BIT;\r
+ } TIOR;\r
+ char wk2[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TTGE:1;\r
+ unsigned char :1;\r
+ unsigned char TCIEU:1;\r
+ unsigned char TCIEV:1;\r
+ unsigned char TGIED:1;\r
+ unsigned char TGIEC:1;\r
+ unsigned char TGIEB:1;\r
+ unsigned char TGIEA:1;\r
+ } BIT;\r
+ } TIER;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TCFD:1;\r
+ unsigned char :1;\r
+ unsigned char TCFU:1;\r
+ unsigned char TCFV:1;\r
+ unsigned char TGFD:1;\r
+ unsigned char TGFC:1;\r
+ unsigned char TGFB:1;\r
+ unsigned char TGFA:1;\r
+ } BIT;\r
+ } TSR;\r
+ unsigned short TCNT;\r
+ unsigned short TGRA;\r
+ unsigned short TGRB;\r
+};\r
+\r
+struct st_tpua {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char CST5:1;\r
+ unsigned char CST4:1;\r
+ unsigned char CST3:1;\r
+ unsigned char CST2:1;\r
+ unsigned char CST1:1;\r
+ unsigned char CST0:1;\r
+ } BIT;\r
+ } TSTR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char SYNC5:1;\r
+ unsigned char SYNC4:1;\r
+ unsigned char SYNC3:1;\r
+ unsigned char SYNC2:1;\r
+ unsigned char SYNC1:1;\r
+ unsigned char SYNC0:1;\r
+ } BIT;\r
+ } TSYR;\r
+};\r
+\r
+struct st_tpub {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char CST11:1;\r
+ unsigned char CST10:1;\r
+ unsigned char CST9:1;\r
+ unsigned char CST8:1;\r
+ unsigned char CST7:1;\r
+ unsigned char CST6:1;\r
+ } BIT;\r
+ } TSTR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char SYNC11:1;\r
+ unsigned char SYNC10:1;\r
+ unsigned char SYNC9:1;\r
+ unsigned char SYNC8:1;\r
+ unsigned char SYNC7:1;\r
+ unsigned char SYNC6:1;\r
+ } BIT;\r
+ } TSYR;\r
+};\r
+\r
+struct st_usb {\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned long :8;\r
+ unsigned long DVBSTS0:1;\r
+ unsigned long :5;\r
+ unsigned long DM0:1;\r
+ unsigned long DP0:1;\r
+ unsigned long :11;\r
+ unsigned long FIXPHY0:1;\r
+ unsigned long :3;\r
+ unsigned long SRPC0:1;\r
+ } BIT;\r
+ } DPUSR0R;\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned long :8;\r
+ unsigned long DVBINT0:1;\r
+ unsigned long :6;\r
+ unsigned long DPINT0:1;\r
+ unsigned long :8;\r
+ unsigned long DVBSE0:1;\r
+ unsigned long :6;\r
+ unsigned long DPINTE0:1;\r
+ } BIT;\r
+ } DPUSR1R;\r
+};\r
+\r
+struct st_usb0 {\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :5;\r
+ unsigned short SCKE:1;\r
+ unsigned short :5;\r
+ unsigned short DPRPU:1;\r
+ unsigned short :3;\r
+ unsigned short USBE:1;\r
+ } BIT;\r
+ } SYSCFG;\r
+ char wk0[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :14;\r
+ unsigned short LNST:2;\r
+ } BIT;\r
+ } SYSSTS0;\r
+ char wk1[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :7;\r
+ unsigned short WKUP:1;\r
+ unsigned short :5;\r
+ unsigned short RHST:3;\r
+ } BIT;\r
+ } DVSTCTR0;\r
+ char wk2[10];\r
+ unsigned short CFIFO;\r
+ char wk3[2];\r
+ unsigned short D0FIFO;\r
+ char wk4[2];\r
+ unsigned short D1FIFO;\r
+ char wk5[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short RCNT:1;\r
+ unsigned short REW:1;\r
+ unsigned short :3;\r
+ unsigned short MBW:1;\r
+ unsigned short :1;\r
+ unsigned short BIGEND:1;\r
+ unsigned short :2;\r
+ unsigned short ISEL:1;\r
+ unsigned short :1;\r
+ unsigned short CURPIPE:4;\r
+ } BIT;\r
+ } CFIFOSEL;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short BVAL:1;\r
+ unsigned short BCLR:1;\r
+ unsigned short FRDY:1;\r
+ unsigned short :4;\r
+ unsigned short DTLN:9;\r
+ } BIT;\r
+ } CFIFOCTR;\r
+ char wk6[4];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short RCNT:1;\r
+ unsigned short REW:1;\r
+ unsigned short DCLRM:1;\r
+ unsigned short DREQE:1;\r
+ unsigned short :1;\r
+ unsigned short MBW:1;\r
+ unsigned short :1;\r
+ unsigned short BIGEND:1;\r
+ unsigned short :4;\r
+ unsigned short CURPIPE:4;\r
+ } BIT;\r
+ } D0FIFOSEL;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short BVAL:1;\r
+ unsigned short BCLR:1;\r
+ unsigned short FRDY:1;\r
+ unsigned short :4;\r
+ unsigned short DTLN:9;\r
+ } BIT;\r
+ } D0FIFOCTR;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short RCNT:1;\r
+ unsigned short REW:1;\r
+ unsigned short DCLRM:1;\r
+ unsigned short DREQE:1;\r
+ unsigned short :1;\r
+ unsigned short MBW:1;\r
+ unsigned short :1;\r
+ unsigned short BIGEND:1;\r
+ unsigned short :4;\r
+ unsigned short CURPIPE:4;\r
+ } BIT;\r
+ } D1FIFOSEL;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short BVAL:1;\r
+ unsigned short BCLR:1;\r
+ unsigned short FRDY:1;\r
+ unsigned short :4;\r
+ unsigned short DTLN:9;\r
+ } BIT;\r
+ } D1FIFOCTR;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short VBSE:1;\r
+ unsigned short RSME:1;\r
+ unsigned short SOFE:1;\r
+ unsigned short DVSE:1;\r
+ unsigned short CTRE:1;\r
+ unsigned short BEMPE:1;\r
+ unsigned short NRDYE:1;\r
+ unsigned short BRDYE:1;\r
+ } BIT;\r
+ } INTENB0;\r
+ char wk7[4];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :6;\r
+ unsigned short PIPE9BRDYE:1;\r
+ unsigned short PIPE8BRDYE:1;\r
+ unsigned short PIPE7BRDYE:1;\r
+ unsigned short PIPE6BRDYE:1;\r
+ unsigned short PIPE5BRDYE:1;\r
+ unsigned short PIPE4BRDYE:1;\r
+ unsigned short PIPE3BRDYE:1;\r
+ unsigned short PIPE2BRDYE:1;\r
+ unsigned short PIPE1BRDYE:1;\r
+ unsigned short PIPE0BRDYE:1;\r
+ } BIT;\r
+ } BRDYENB;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :6;\r
+ unsigned short PIPE9NRDYE:1;\r
+ unsigned short PIPE8NRDYE:1;\r
+ unsigned short PIPE7NRDYE:1;\r
+ unsigned short PIPE6NRDYE:1;\r
+ unsigned short PIPE5NRDYE:1;\r
+ unsigned short PIPE4NRDYE:1;\r
+ unsigned short PIPE3NRDYE:1;\r
+ unsigned short PIPE2NRDYE:1;\r
+ unsigned short PIPE1NRDYE:1;\r
+ unsigned short PIPE0NRDYE:1;\r
+ } BIT;\r
+ } NRDYENB;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :6;\r
+ unsigned short PIPE9BEMPE:1;\r
+ unsigned short PIPE8BEMPE:1;\r
+ unsigned short PIPE7BEMPE:1;\r
+ unsigned short PIPE6BEMPE:1;\r
+ unsigned short PIPE5BEMPE:1;\r
+ unsigned short PIPE4BEMPE:1;\r
+ unsigned short PIPE3BEMPE:1;\r
+ unsigned short PIPE2BEMPE:1;\r
+ unsigned short PIPE1BEMPE:1;\r
+ unsigned short PIPE0BEMPE:1;\r
+ } BIT;\r
+ } BEMPENB;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :9;\r
+ unsigned short BRDYM:1;\r
+ unsigned short :1;\r
+ unsigned short EDGESTS:1;\r
+ } BIT;\r
+ } SOFCFG;\r
+ char wk8[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short VBINT:1;\r
+ unsigned short RESM:1;\r
+ unsigned short SOFR:1;\r
+ unsigned short DVST:1;\r
+ unsigned short CTRT:1;\r
+ unsigned short BEMP:1;\r
+ unsigned short NRDY:1;\r
+ unsigned short BRDY:1;\r
+ unsigned short VBSTS:1;\r
+ unsigned short DVSQ:3;\r
+ unsigned short VALID:1;\r
+ unsigned short CTSQ:3;\r
+ } BIT;\r
+ } INTSTS0;\r
+ char wk9[4];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :6;\r
+ unsigned short PIPE9BRDY:1;\r
+ unsigned short PIPE8BRDY:1;\r
+ unsigned short PIPE7BRDY:1;\r
+ unsigned short PIPE6BRDY:1;\r
+ unsigned short PIPE5BRDY:1;\r
+ unsigned short PIPE4BRDY:1;\r
+ unsigned short PIPE3BRDY:1;\r
+ unsigned short PIPE2BRDY:1;\r
+ unsigned short PIPE1BRDY:1;\r
+ unsigned short PIPE0BRDY:1;\r
+ } BIT;\r
+ } BRDYSTS;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :6;\r
+ unsigned short PIPE9NRDYE:1;\r
+ unsigned short PIPE8NRDYE:1;\r
+ unsigned short PIPE7NRDYE:1;\r
+ unsigned short PIPE6NRDYE:1;\r
+ unsigned short PIPE5NRDYE:1;\r
+ unsigned short PIPE4NRDYE:1;\r
+ unsigned short PIPE3NRDYE:1;\r
+ unsigned short PIPE2NRDYE:1;\r
+ unsigned short PIPE1NRDYE:1;\r
+ unsigned short PIPE0NRDYE:1;\r
+ } BIT;\r
+ } NRDYSTS;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :6;\r
+ unsigned short PIPE9BEMPE:1;\r
+ unsigned short PIPE8BEMPE:1;\r
+ unsigned short PIPE7BENP:1;\r
+ unsigned short PIPE6BENP:1;\r
+ unsigned short PIPE5BENP:1;\r
+ unsigned short PIPE4BENP:1;\r
+ unsigned short PIPE3BENP:1;\r
+ unsigned short PIPE2BENP:1;\r
+ unsigned short PIPE1BENP:1;\r
+ unsigned short PIPE0BENP:1;\r
+ } BIT;\r
+ } BEMPSTS;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short OVRN:1;\r
+ unsigned short CRCE:1;\r
+ unsigned short :3;\r
+ unsigned short FRNM:11;\r
+ } BIT;\r
+ } FRMNUM;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short DVCHG:1;\r
+ } BIT;\r
+ } DVCHGR;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :4;\r
+ unsigned short STSRECOV:4;\r
+ unsigned short :1;\r
+ unsigned short USBADDR:7;\r
+ } BIT;\r
+ } USBADDR;\r
+ char wk10[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short BREQUEST:8;\r
+ unsigned short BMREQUESTTYPE:8;\r
+ } BIT;\r
+ } USBREQ;\r
+ unsigned short USBVAL;\r
+ unsigned short USBINDX;\r
+ unsigned short USBLENG;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :8;\r
+ unsigned short SHTNAK:1;\r
+ } BIT;\r
+ } DCPCFG;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :9;\r
+ unsigned short MXPS:7;\r
+ } BIT;\r
+ } DCPMAXP;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short BSTS:1;\r
+ unsigned short :6;\r
+ unsigned short SQCLR:1;\r
+ unsigned short SQSET:1;\r
+ unsigned short SQMON:1;\r
+ unsigned short PBUSY:1;\r
+ unsigned short :2;\r
+ unsigned short CCPL:1;\r
+ unsigned short PID:2;\r
+ } BIT;\r
+ } DCPCTR;\r
+ char wk11[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :12;\r
+ unsigned short PIPESEL:4;\r
+ } BIT;\r
+ } PIPESEL;\r
+ char wk12[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short TYPE:2;\r
+ unsigned short :3;\r
+ unsigned short BFRE:1;\r
+ unsigned short DBLB:1;\r
+ unsigned short :1;\r
+ unsigned short SHTNAK:1;\r
+ unsigned short :2;\r
+ unsigned short DIR:1;\r
+ unsigned short EPNUM:4;\r
+ } BIT;\r
+ } PIPECFG;\r
+ char wk13[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :7;\r
+ unsigned short MXPS:9;\r
+ } BIT;\r
+ } PIPEMAXP;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :3;\r
+ unsigned short IFIS:1;\r
+ unsigned short :9;\r
+ unsigned short IITV:3;\r
+ } BIT;\r
+ } PIPEPERI;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short BSTS:1;\r
+ unsigned short INBUFM:1;\r
+ unsigned short :3;\r
+ unsigned short ATREPM:1;\r
+ unsigned short ACLRM:1;\r
+ unsigned short SQCLR:1;\r
+ unsigned short SQSET:1;\r
+ unsigned short SQMON:1;\r
+ unsigned short PBUSY:1;\r
+ unsigned short :3;\r
+ unsigned short PID:2;\r
+ } BIT;\r
+ } PIPE1CTR;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short BSTS:1;\r
+ unsigned short INBUFM:1;\r
+ unsigned short :3;\r
+ unsigned short ATREPM:1;\r
+ unsigned short ACLRM:1;\r
+ unsigned short SQCLR:1;\r
+ unsigned short SQSET:1;\r
+ unsigned short SQMON:1;\r
+ unsigned short PBUSY:1;\r
+ unsigned short :3;\r
+ unsigned short PID:2;\r
+ } BIT;\r
+ } PIPE2CTR;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short BSTS:1;\r
+ unsigned short INBUFM:1;\r
+ unsigned short :3;\r
+ unsigned short ATREPM:1;\r
+ unsigned short ACLRM:1;\r
+ unsigned short SQCLR:1;\r
+ unsigned short SQSET:1;\r
+ unsigned short SQMON:1;\r
+ unsigned short PBUSY:1;\r
+ unsigned short :3;\r
+ unsigned short PID:2;\r
+ } BIT;\r
+ } PIPE3CTR;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short BSTS:1;\r
+ unsigned short INBUFM:1;\r
+ unsigned short :3;\r
+ unsigned short ATREPM:1;\r
+ unsigned short ACLRM:1;\r
+ unsigned short SQCLR:1;\r
+ unsigned short SQSET:1;\r
+ unsigned short SQMON:1;\r
+ unsigned short PBUSY:1;\r
+ unsigned short :3;\r
+ unsigned short PID:2;\r
+ } BIT;\r
+ } PIPE4CTR;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short BSTS:1;\r
+ unsigned short INBUFM:1;\r
+ unsigned short :3;\r
+ unsigned short ATREPM:1;\r
+ unsigned short ACLRM:1;\r
+ unsigned short SQCLR:1;\r
+ unsigned short SQSET:1;\r
+ unsigned short SQMON:1;\r
+ unsigned short PBUSY:1;\r
+ unsigned short :3;\r
+ unsigned short PID:2;\r
+ } BIT;\r
+ } PIPE5CTR;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short BSTS:1;\r
+ unsigned short :5;\r
+ unsigned short ACLRM:1;\r
+ unsigned short SQCLR:1;\r
+ unsigned short SQSET:1;\r
+ unsigned short SQMON:1;\r
+ unsigned short PBUSY:1;\r
+ unsigned short :3;\r
+ unsigned short PID:2;\r
+ } BIT;\r
+ } PIPE6CTR;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short BSTS:1;\r
+ unsigned short :5;\r
+ unsigned short ACLRM:1;\r
+ unsigned short SQCLR:1;\r
+ unsigned short SQSET:1;\r
+ unsigned short SQMON:1;\r
+ unsigned short PBUSY:1;\r
+ unsigned short :3;\r
+ unsigned short PID:2;\r
+ } BIT;\r
+ } PIPE7CTR;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short BSTS:1;\r
+ unsigned short :5;\r
+ unsigned short ACLRM:1;\r
+ unsigned short SQCLR:1;\r
+ unsigned short SQSET:1;\r
+ unsigned short SQMON:1;\r
+ unsigned short PBUSY:1;\r
+ unsigned short :3;\r
+ unsigned short PID:2;\r
+ } BIT;\r
+ } PIPE8CTR;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short BSTS:1;\r
+ unsigned short :5;\r
+ unsigned short ACLRM:1;\r
+ unsigned short SQCLR:1;\r
+ unsigned short SQSET:1;\r
+ unsigned short SQMON:1;\r
+ unsigned short PBUSY:1;\r
+ unsigned short :3;\r
+ unsigned short PID:2;\r
+ } BIT;\r
+ } PIPE9CTR;\r
+ char wk14[14];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :6;\r
+ unsigned short TRENB:1;\r
+ unsigned short TRCLR:1;\r
+ } BIT;\r
+ } PIPE1TRE;\r
+ unsigned short PIPE1TRN;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :6;\r
+ unsigned short TRENB:1;\r
+ unsigned short TRCLR:1;\r
+ } BIT;\r
+ } PIPE2TRE;\r
+ unsigned short PIPE2TRN;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :6;\r
+ unsigned short TRENB:1;\r
+ unsigned short TRCLR:1;\r
+ } BIT;\r
+ } PIPE3TRE;\r
+ unsigned short PIPE3TRN;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :6;\r
+ unsigned short TRENB:1;\r
+ unsigned short TRCLR:1;\r
+ } BIT;\r
+ } PIPE4TRE;\r
+ unsigned short PIPE4TRN;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :6;\r
+ unsigned short TRENB:1;\r
+ unsigned short TRCLR:1;\r
+ } BIT;\r
+ } PIPE5TRE;\r
+ unsigned short PIPE5TRN;\r
+};\r
+\r
+struct st_wdt {\r
+ unsigned char WDTRR;\r
+ char wk0[1];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :2;\r
+ unsigned short RPSS:2;\r
+ unsigned short :2;\r
+ unsigned short RPES:2;\r
+ unsigned short CKS:4;\r
+ unsigned short :2;\r
+ unsigned short TOPS:2;\r
+ } BIT;\r
+ } WDTCR;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short REFEF:1;\r
+ unsigned short UNDFF:1;\r
+ unsigned short CNTVAL:14;\r
+ } BIT;\r
+ } WDTSR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char RSTIRQS:1;\r
+ } BIT;\r
+ } WDTRCR;\r
+};\r
+\r
+enum enum_ir {\r
+IR_BSC_BUSERR=16,IR_FCU_FIFERR=21,\r
+IR_ICU_SWINT=27,\r
+IR_CMT0_CMI0,\r
+IR_CMT1_CMI1,\r
+IR_CMT2_CMI2,\r
+IR_CMT3_CMI3,\r
+IR_USB0_D0FIFO0=33,IR_USB0_D1FIFO0,IR_USB0_USBI0,IR_USB0_D0FIFO1,IR_USB0_D1FIFO1,IR_USB0_USBI1,\r
+IR_RSPI0_SPRI0,IR_RSPI0_SPTI0,IR_RSPI0_SPII0,\r
+IR_RSPI1_SPRI1,IR_RSPI1_SPTI1,IR_RSPI1_SPII1,\r
+IR_RSPI2_SPRI2,IR_RSPI2_SPTI2,IR_RSPI2_SPII2,\r
+IR_CAN0_RXF0,IR_CAN0_TXF0,IR_CAN0_RXM0,IR_CAN0_TXM0,\r
+IR_CAN1_RXF1,IR_CAN1_TXF1,IR_CAN1_RXM1,IR_CAN1_TXM1,\r
+IR_CAN2_RXF2,IR_CAN2_TXF2,IR_CAN2_RXM2,IR_CAN2_TXM2,\r
+IR_RTC_COUNTUP=62,\r
+IR_ICU_IRQ0=64,IR_ICU_IRQ1,IR_ICU_IRQ2,IR_ICU_IRQ3,IR_ICU_IRQ4,IR_ICU_IRQ5,IR_ICU_IRQ6,IR_ICU_IRQ7,IR_ICU_IRQ8,IR_ICU_IRQ9,IR_ICU_IRQ10,IR_ICU_IRQ11,IR_ICU_IRQ12,IR_ICU_IRQ13,IR_ICU_IRQ14,IR_ICU_IRQ15,\r
+IR_USB_USBR0=90,\r
+IR_RTC_ALARM=92,IR_RTC_PRD,\r
+IR_AD0_ADI0=98,\r
+IR_S12AD0_S12ADI0=102,\r
+IR_ICU_GROUPE0=106,IR_ICU_GROUPE1,IR_ICU_GROUPE2,IR_ICU_GROUPE3,IR_ICU_GROUPE4,IR_ICU_GROUPE5,IR_ICU_GROUPE6,IR_ICU_GROUPL0=114,\r
+IR_SCIX_SCIX0=122,IR_SCIX_SCIX1,IR_SCIX_SCIX2,IR_SCIX_SCIX3,\r
+IR_TPU0_TGI0A,IR_TPU0_TGI0B,IR_TPU0_TGI0C,IR_TPU0_TGI0D,\r
+IR_TPU1_TGI1A,IR_TPU1_TGI1B,\r
+IR_TPU2_TGI2A,IR_TPU2_TGI2B,\r
+IR_TPU3_TGI3A,IR_TPU3_TGI3B,IR_TPU3_TGI3C,IR_TPU3_TGI3D,\r
+IR_TPU4_TGI4A,IR_TPU4_TGI4B,\r
+IR_TPU5_TGI5A,IR_TPU5_TGI5B,\r
+IR_TPU6_TGI6A,IR_TPU6_TGI6B,IR_TPU6_TGI6C,IR_TPU6_TGI6D,\r
+IR_MTU0_TGIA0=142,IR_MTU0_TGIB0,IR_MTU0_TGIC0,IR_MTU0_TGID0,IR_MTU0_TGIE0,IR_MTU0_TGIF0,\r
+IR_TPU7_TGI7A,IR_TPU7_TGI7B,\r
+IR_MTU1_TGIA1=148,IR_MTU1_TGIB1,\r
+IR_TPU8_TGI8A,IR_TPU8_TGI8B,\r
+IR_MTU2_TGIA2=150,IR_MTU2_TGIB2,\r
+IR_TPU9_TGI9A,IR_TPU9_TGI9B,IR_TPU9_TGI9C,IR_TPU9_TGI9D,\r
+IR_MTU3_TGIA3=152,IR_MTU3_TGIB3,IR_MTU3_TGIC3,IR_MTU3_TGID3,\r
+IR_TPU10_TGI10A,IR_TPU10_TGI10B,\r
+IR_MTU4_TGIA4=156,IR_MTU4_TGIB4,IR_MTU4_TGIC4,IR_MTU4_TGID4,IR_MTU4_TCIV4,\r
+IR_MTU5_TGIU5,IR_MTU5_TGIV5,IR_MTU5_TGIW5,\r
+IR_TPU11_TGI11A,IR_TPU11_TGI11B,\r
+IR_POE_OEI1,IR_POE_OEI2,\r
+IR_TMR0_CMIA0=170,IR_TMR0_CMIB0,IR_TMR0_OVI0,\r
+IR_TMR1_CMIA1,IR_TMR1_CMIB1,IR_TMR1_OVI1,\r
+IR_TMR2_CMIA2,IR_TMR2_CMIB2,IR_TMR2_OVI2,\r
+IR_TMR3_CMIA3,IR_TMR3_CMIB3,IR_TMR3_OVI3,\r
+IR_RIIC0_EEI0,IR_RIIC0_RXI0,IR_RIIC0_TXI0,IR_RIIC0_TEI0,\r
+IR_RIIC1_EEI1,IR_RIIC1_RXI1,IR_RIIC1_TXI1,IR_RIIC1_TEI1,\r
+IR_RIIC2_EEI2,IR_RIIC2_RXI2,IR_RIIC2_TXI2,IR_RIIC2_TEI2,\r
+IR_RIIC3_EEI3,IR_RIIC3_RXI3,IR_RIIC3_TXI3,IR_RIIC3_TEI3,\r
+IR_DMAC_DMAC0I,IR_DMAC_DMAC1I,IR_DMAC_DMAC2I,IR_DMAC_DMAC3I,\r
+IR_SCI0_RXI0=214,IR_SCI0_TXI0,IR_SCI0_TEI0,\r
+IR_SCI1_RXI1,IR_SCI1_TXI1,IR_SCI1_TEI1,\r
+IR_SCI2_RXI2,IR_SCI2_TXI2,IR_SCI2_TEI2,\r
+IR_SCI3_RXI3,IR_SCI3_TXI3,IR_SCI3_TEI3,\r
+IR_SCI4_RXI4,IR_SCI4_TXI4,IR_SCI4_TEI4,\r
+IR_SCI5_RXI5,IR_SCI5_TXI5,IR_SCI5_TEI5,\r
+IR_SCI6_RXI6,IR_SCI6_TXI6,IR_SCI6_TEI6,\r
+IR_SCI7_RXI7,IR_SCI7_TXI7,IR_SCI7_TEI7,\r
+IR_SCI8_RXI8,IR_SCI8_TXI8,IR_SCI8_TEI8,\r
+IR_SCI9_RXI9,IR_SCI9_TXI9,IR_SCI9_TEI9,\r
+IR_SCI10_RXI10,IR_SCI10_TXI10,IR_SCI10_TEI10,\r
+IR_SCI11_RXI11,IR_SCI11_TXI11,IR_SCI11_TEI11,\r
+IR_SCI12_RXI12,IR_SCI12_TXI12,IR_SCI12_TEI12,\r
+IR_IEB_IEBINT\r
+};\r
+\r
+enum enum_dtce {\r
+DTCE_ICU_SWINT=27,\r
+DTCE_CMT0_CMI0,\r
+DTCE_CMT1_CMI1,\r
+DTCE_CMT2_CMI2,\r
+DTCE_CMT3_CMI3,\r
+DTCE_USB0_D0FIFO0=33,DTCE_USB0_D1FIFO0,DTCE_USB0_D0FIFO1=36,DTCE_USB0_D1FIFO1,\r
+DTCE_RSPI0_SPRI0=39,DTCE_RSPI0_SPTI0,\r
+DTCE_RSPI1_SPRI1=42,DTCE_RSPI1_SPTI1,\r
+DTCE_RSPI2_SPRI2=45,DTCE_RSPI2_SPTI2,\r
+DTCE_ICU_IRQ0=64,DTCE_ICU_IRQ1,DTCE_ICU_IRQ2,DTCE_ICU_IRQ3,DTCE_ICU_IRQ4,DTCE_ICU_IRQ5,DTCE_ICU_IRQ6,DTCE_ICU_IRQ7,DTCE_ICU_IRQ8,DTCE_ICU_IRQ9,DTCE_ICU_IRQ10,DTCE_ICU_IRQ11,DTCE_ICU_IRQ12,DTCE_ICU_IRQ13,DTCE_ICU_IRQ14,DTCE_ICU_IRQ15,\r
+DTCE_AD0_ADI0=98,\r
+DTCE_S12AD0_S12ADI0=102,\r
+DTCE_TPU0_TGI0A=126,DTCE_TPU0_TGI0B,DTCE_TPU0_TGI0C,DTCE_TPU0_TGI0D,\r
+DTCE_TPU1_TGI1A,DTCE_TPU1_TGI1B,\r
+DTCE_TPU2_TGI2A,DTCE_TPU2_TGI2B,\r
+DTCE_TPU3_TGI3A,DTCE_TPU3_TGI3B,DTCE_TPU3_TGI3C,DTCE_TPU3_TGI3D,\r
+DTCE_TPU4_TGI4A,DTCE_TPU4_TGI4B,\r
+DTCE_TPU5_TGI5A,DTCE_TPU5_TGI5B,\r
+DTCE_TPU6_TGI6A,DTCE_TPU6_TGI6B,DTCE_TPU6_TGI6C,DTCE_TPU6_TGI6D,\r
+DTCE_MTU0_TGIA0=142,DTCE_MTU0_TGIB0,DTCE_MTU0_TGIC0,DTCE_MTU0_TGID0,\r
+DTCE_TPU7_TGI7A=148,DTCE_TPU7_TGI7B,\r
+DTCE_MTU1_TGIA1=148,DTCE_MTU1_TGIB1,\r
+DTCE_TPU8_TGI8A,DTCE_TPU8_TGI8B,\r
+DTCE_MTU2_TGIA2=150,DTCE_MTU2_TGIB2,\r
+DTCE_TPU9_TGI9A,DTCE_TPU9_TGI9B,DTCE_TPU9_TGI9C,DTCE_TPU9_TGI9D,\r
+DTCE_MTU3_TGIA3=152,DTCE_MTU3_TGIB3,DTCE_MTU3_TGIC3,DTCE_MTU3_TGID3,\r
+DTCE_TPU10_TGI10A,DTCE_TPU10_TGI10B,\r
+DTCE_MTU4_TGIA4=156,DTCE_MTU4_TGIB4,DTCE_MTU4_TGIC4,DTCE_MTU4_TGID4,DTCE_MTU4_TCIV4,\r
+DTCE_MTU5_TGIU5,DTCE_MTU5_TGIV5,DTCE_MTU5_TGIW5,\r
+DTCE_TPU11_TGI11A,DTCE_TPU11_TGI11B,\r
+DTCE_TMR0_CMIA0=170,DTCE_TMR0_CMIB0,\r
+DTCE_TMR1_CMIA1=173,DTCE_TMR1_CMIB1,\r
+DTCE_TMR2_CMIA2=176,DTCE_TMR2_CMIB2,\r
+DTCE_TMR3_CMIA3=179,DTCE_TMR3_CMIB3,\r
+DTCE_RIIC0_RXI0=183,DTCE_RIIC0_TXI0,\r
+DTCE_RIIC1_RXI1=187,DTCE_RIIC1_TXI1,\r
+DTCE_RIIC2_RXI2=191,DTCE_RIIC2_TXI2,\r
+DTCE_RIIC3_RXI3=195,DTCE_RIIC3_TXI3,\r
+DTCE_DMAC_DMAC0I=198,DTCE_DMAC_DMAC1I,DTCE_DMAC_DMAC2I,DTCE_DMAC_DMAC3I,\r
+DTCE_SCI0_RXI0=214,DTCE_SCI0_TXI0,\r
+DTCE_SCI1_RXI1=217,DTCE_SCI1_TXI1,\r
+DTCE_SCI2_RXI2=220,DTCE_SCI2_TXI2,\r
+DTCE_SCI3_RXI3=223,DTCE_SCI3_TXI3,\r
+DTCE_SCI4_RXI4=226,DTCE_SCI4_TXI4,\r
+DTCE_SCI5_RXI5=229,DTCE_SCI5_TXI5,\r
+DTCE_SCI6_RXI6=232,DTCE_SCI6_TXI6,\r
+DTCE_SCI7_RXI7=235,DTCE_SCI7_TXI7,\r
+DTCE_SCI8_RXI8=238,DTCE_SCI8_TXI8,\r
+DTCE_SCI9_RXI9=241,DTCE_SCI9_TXI9,\r
+DTCE_SCI10_RXI10=244,DTCE_SCI10_TXI10,\r
+DTCE_SCI11_RXI11=247,DTCE_SCI11_TXI11,\r
+DTCE_SCI12_RXI12=250,DTCE_SCI12_TXI12\r
+};\r
+\r
+enum enum_ier {\r
+IER_BSC_BUSERR=0x02,\r
+IER_FCU_FIFERR=0x02,IER_FCU_FRDYI=0x02,\r
+IER_ICU_SWINT=0x03,\r
+IER_CMT0_CMI0=0x03,\r
+IER_CMT1_CMI1=0x03,\r
+IER_CMT2_CMI2=0x03,\r
+IER_CMT3_CMI3=0x03,\r
+IER_USB0_D0FIFO0=0x04,IER_USB0_D1FIFO0=0x04,IER_USB0_USBI0=0x04,IER_USB0_D0FIFO1=0x04,IER_USB0_D1FIFO1=0x04,IER_USB0_USBI1=0x04,\r
+IER_RSPI0_SPRI0=0x04,IER_RSPI0_SPTI0=0x05,IER_RSPI0_SPII0=0x05,\r
+IER_RSPI1_SPRI1=0x05,IER_RSPI1_SPTI1=0x05,IER_RSPI1_SPII1=0x05,\r
+IER_RSPI2_SPRI2=0x05,IER_RSPI2_SPTI2=0x05,IER_RSPI2_SPII2=0x05,\r
+IER_CAN0_RXF0=0x06,IER_CAN0_TXF0=0x06,IER_CAN0_RXM0=0x06,IER_CAN0_TXM0=0x06,\r
+IER_CAN1_RXF1=0x06,IER_CAN1_TXF1=0x06,IER_CAN1_RXM1=0x06,IER_CAN1_TXM1=0x06,\r
+IER_CAN2_RXF2=0x07,IER_CAN2_TXF2=0x07,IER_CAN2_RXM2=0x07,IER_CAN2_TXM2=0x07,\r
+IER_RTC_COUNTUP=0x07,\r
+IER_ICU_IRQ0=0x08,IER_ICU_IRQ1=0x08,IER_ICU_IRQ2=0x08,IER_ICU_IRQ3=0x08,IER_ICU_IRQ4=0x08,IER_ICU_IRQ5=0x08,IER_ICU_IRQ6=0x08,IER_ICU_IRQ7=0x08,IER_ICU_IRQ8=0x09,IER_ICU_IRQ9=0x09,IER_ICU_IRQ10=0x09,IER_ICU_IRQ11=0x09,IER_ICU_IRQ12=0x09,IER_ICU_IRQ13=0x09,IER_ICU_IRQ14=0x09,IER_ICU_IRQ15=0x09,\r
+IER_USB_USBR0=0x0B,\r
+IER_RTC_ALARM=0x0B,IER_RTC_PRD=0x0B,\r
+IER_AD0_ADI0=0x0C,\r
+IER_S12AD0_S12ADI0=0x0C,\r
+IER_ICU_GROUPE0=0x0D,IER_ICU_GROUPE1=0x0D,IER_ICU_GROUPE2=0x0D,IER_ICU_GROUPE3=0x0D,IER_ICU_GROUPE4=0x0D,IER_ICU_GROUPE5=0x0D,IER_ICU_GROUPE6=0x0E,IER_ICU_GROUPL0=0x0E,\r
+IER_SCIX_SCIX0=0x0F,IER_SCIX_SCIX1=0x0F,IER_SCIX_SCIX2=0x0F,IER_SCIX_SCIX3=0x0F,\r
+IER_TPU0_TGI0A=0x0F,IER_TPU0_TGI0B=0x0F,IER_TPU0_TGI0C=0x10,IER_TPU0_TGI0D=0x10,\r
+IER_TPU1_TGI1A=0x10,IER_TPU1_TGI1B=0x10,\r
+IER_TPU2_TGI2A=0x10,IER_TPU2_TGI2B=0x10,\r
+IER_TPU3_TGI3A=0x10,IER_TPU3_TGI3B=0x10,IER_TPU3_TGI3C=0x11,IER_TPU3_TGI3D=0x11,\r
+IER_TPU4_TGI4A=0x11,IER_TPU4_TGI4B=0x11,\r
+IER_TPU5_TGI5A=0x11,IER_TPU5_TGI5B=0x11,\r
+IER_TPU6_TGI6A=0x11,IER_TPU6_TGI6B=0x11,IER_TPU6_TGI6C=0x12,IER_TPU6_TGI6D=0x12,\r
+IER_MTU0_TGIA0=0x11,IER_MTU0_TGIB0=0x11,IER_MTU0_TGIC0=0x12,IER_MTU0_TGID0=0x12,IER_MTU0_TGIE0=0x12,IER_MTU0_TGIF0=0x12,\r
+IER_TPU7_TGI7A=0x12,IER_TPU7_TGI7B=0x12,\r
+IER_MTU1_TGIA1=0x12,IER_MTU1_TGIB1=0x12,\r
+IER_TPU8_TGI8A=0x12,IER_TPU8_TGI8B=0x12,\r
+IER_MTU2_TGIA2=0x12,IER_MTU2_TGIB2=0x12,\r
+IER_TPU9_TGI9A=0x13,IER_TPU9_TGI9B=0x13,IER_TPU9_TGI9C=0x13,IER_TPU9_TGI9D=0x13,\r
+IER_MTU3_TGIA3=0x13,IER_MTU3_TGIB3=0x13,IER_MTU3_TGIC3=0x13,IER_MTU3_TGID3=0x13,\r
+IER_TPU10_TGI10A=0x13,IER_TPU10_TGI10B=0x13,\r
+IER_MTU4_TGIA4=0x13,IER_MTU4_TGIB4=0x13,IER_MTU4_TGIC4=0x13,IER_MTU4_TGID4=0x13,IER_MTU4_TCIV4=0x14,\r
+IER_MTU5_TGIU5=0x14,IER_MTU5_TGIV5=0x14,IER_MTU5_TGIW5=0x14,\r
+IER_TPU11_TGI11A=0x14,IER_TPU11_TGI11B=0x14,\r
+IER_POE_OEI1=0x14,IER_POE_OEI2=0x14,\r
+IER_TMR0_CMIA0=0x15,IER_TMR0_CMIB0=0x15,IER_TMR0_OVI0=0x15,\r
+IER_TMR1_CMIA1=0x15,IER_TMR1_CMIB1=0x15,IER_TMR1_OVI1=0x15,\r
+IER_TMR2_CMIA2=0x16,IER_TMR2_CMIB2=0x16,IER_TMR2_OVI2=0x16,\r
+IER_TMR3_CMIA3=0x16,IER_TMR3_CMIB3=0x16,IER_TMR3_OVI3=0x16,\r
+IER_RIIC0_EEI0=0x16,IER_RIIC0_RXI0=0x16,IER_RIIC0_TXI0=0x17,IER_RIIC0_TEI0=0x17,\r
+IER_RIIC1_EEI1=0x17,IER_RIIC1_RXI1=0x17,IER_RIIC1_TXI1=0x17,IER_RIIC1_TEI1=0x17,\r
+IER_RIIC2_EEI2=0x17,IER_RIIC2_RXI2=0x17,IER_RIIC2_TXI2=0x18,IER_RIIC2_TEI2=0x18,\r
+IER_RIIC3_EEI3=0x18,IER_RIIC3_RXI3=0x18,IER_RIIC3_TXI3=0x18,IER_RIIC3_TEI3=0x18,\r
+IER_DMAC_DMAC0I=0x18,IER_DMAC_DMAC1I=0x18,IER_DMAC_DMAC2I=0x19,IER_DMAC_DMAC3I=0x19,\r
+IER_SCI0_RXI0=0x1A,IER_SCI0_TXI0=0x1A,IER_SCI0_TEI0=0x1B,\r
+IER_SCI1_RXI1=0x1B,IER_SCI1_TXI1=0x1B,IER_SCI1_TEI1=0x1B,\r
+IER_SCI2_RXI2=0x1B,IER_SCI2_TXI2=0x1B,IER_SCI2_TEI2=0x1B,\r
+IER_SCI3_RXI3=0x1B,IER_SCI3_TXI3=0x1C,IER_SCI3_TEI3=0x1C,\r
+IER_SCI4_RXI4=0x1C,IER_SCI4_TXI4=0x1C,IER_SCI4_TEI4=0x1C,\r
+IER_SCI5_RXI5=0x1C,IER_SCI5_TXI5=0x1C,IER_SCI5_TEI5=0x1C,\r
+IER_SCI6_RXI6=0x1D,IER_SCI6_TXI6=0x1D,IER_SCI6_TEI6=0x1D,\r
+IER_SCI7_RXI7=0x1D,IER_SCI7_TXI7=0x1D,IER_SCI7_TEI7=0x1D,\r
+IER_SCI8_RXI8=0x1D,IER_SCI8_TXI8=0x1D,IER_SCI8_TEI8=0x1E,\r
+IER_SCI9_RXI9=0x1E,IER_SCI9_TXI9=0x1E,IER_SCI9_TEI9=0x1E,\r
+IER_SCI10_RXI10=0x1E,IER_SCI10_TXI10=0x1E,IER_SCI10_TEI10=0x1E,\r
+IER_SCI11_RXI11=0x1E,IER_SCI11_TXI11=0x1F,IER_SCI11_TEI11=0x1F,\r
+IER_SCI12_RXI12=0x1F,IER_SCI12_TXI12=0x1F,IER_SCI12_TEI12=0x1F,\r
+IER_IEB_IEBINT=0x1F\r
+};\r
+\r
+enum enum_ipr {\r
+IPR_BSC_BUSERR=0,\r
+IPR_FCU_FIFERR=1,IPR_FCU_FRDYI=2,\r
+IPR_ICU_SWINT=3,\r
+IPR_CMT0_CMI0=4,\r
+IPR_CMT1_CMI1=5,\r
+IPR_CMT2_CMI2=6,\r
+IPR_CMT3_CMI3=7,\r
+IPR_USB0_D0FIFO0=33,IPR_USB0_D1FIFO0=34,IPR_USB0_USBI0=35,IPR_USB0_D0FIFO1=36,IPR_USB0_D1FIFO1=37,IPR_USB0_USBI1=38,\r
+IPR_RSPI0_SPRI0=39,IPR_RSPI0_SPTI0=39,IPR_RSPI0_SPII0=39,\r
+IPR_RSPI1_SPRI1=42,IPR_RSPI1_SPTI1=42,IPR_RSPI1_SPII1=42,\r
+IPR_RSPI2_SPRI2=45,IPR_RSPI2_SPTI2=45,IPR_RSPI2_SPII2=45,\r
+IPR_CAN0_RXF0=48,IPR_CAN0_TXF0=48,IPR_CAN0_RXM0=48,IPR_CAN0_TXM0=48,\r
+IPR_CAN1_RXF1=52,IPR_CAN1_TXF1=52,IPR_CAN1_RXM1=52,IPR_CAN1_TXM1=52,\r
+IPR_CAN2_RXF2=56,IPR_CAN2_TXF2=56,IPR_CAN2_RXM2=56,IPR_CAN2_TXM2=56,\r
+IPR_RTC_COUNTUP=62,\r
+IPR_ICU_IRQ0=64,IPR_ICU_IRQ1=65,IPR_ICU_IRQ2=66,IPR_ICU_IRQ3=67,IPR_ICU_IRQ4=68,IPR_ICU_IRQ5=69,IPR_ICU_IRQ6=70,IPR_ICU_IRQ7=71,IPR_ICU_IRQ8=72,IPR_ICU_IRQ9=73,IPR_ICU_IRQ10=74,IPR_ICU_IRQ11=75,IPR_ICU_IRQ12=76,IPR_ICU_IRQ13=77,IPR_ICU_IRQ14=78,IPR_ICU_IRQ15=79,\r
+IPR_USB_USBR0=90,\r
+IPR_RTC_ALARM=92,IPR_RTC_PRD=93,\r
+IPR_AD0_ADI0=98,\r
+IPR_S12AD0_S12ADI0=102,\r
+IPR_ICU_GROUPE0=106,IPR_ICU_GROUPE1=107,IPR_ICU_GROUPE2=108,IPR_ICU_GROUPE3=109,IPR_ICU_GROUPE4=110,IPR_ICU_GROUPE5=111,IPR_ICU_GROUPE6=112,IPR_ICU_GROUPL0=114,\r
+IPR_SCIX_SCIX0=122,IPR_SCIX_SCIX1=122,IPR_SCIX_SCIX2=122,IPR_SCIX_SCIX3=122,\r
+IPR_TPU0_TGI0A=126,IPR_TPU0_TGI0B=126,IPR_TPU0_TGI0C=126,IPR_TPU0_TGI0D=126,\r
+IPR_TPU1_TGI1A=130,IPR_TPU1_TGI1B=130,\r
+IPR_TPU2_TGI2A=132,IPR_TPU2_TGI2B=132,\r
+IPR_TPU3_TGI3A=134,IPR_TPU3_TGI3B=134,IPR_TPU3_TGI3C=134,IPR_TPU3_TGI3D=134,\r
+IPR_TPU4_TGI4A=138,IPR_TPU4_TGI4B=138,\r
+IPR_TPU5_TGI5A=140,IPR_TPU5_TGI5B=140,\r
+IPR_TPU6_TGI6A=142,IPR_TPU6_TGI6B=142,IPR_TPU6_TGI6C=142,IPR_TPU6_TGI6D=142,\r
+IPR_MTU0_TGIA0=142,IPR_MTU0_TGIB0=142,IPR_MTU0_TGIC0=142,IPR_MTU0_TGID0=142,IPR_MTU0_TGIE0=146,IPR_MTU0_TGIF0=146,\r
+IPR_TPU7_TGI7A=148,IPR_TPU7_TGI7B=148,\r
+IPR_MTU1_TGIA1=148,IPR_MTU1_TGIB1=148,\r
+IPR_TPU8_TGI8A=150,IPR_TPU8_TGI8B=150,\r
+IPR_MTU2_TGIA2=150,IPR_MTU2_TGIB2=150,\r
+IPR_TPU9_TGI9A=152,IPR_TPU9_TGI9B=152,IPR_TPU9_TGI9C=152,IPR_TPU9_TGI9D=152,\r
+IPR_MTU3_TGIA3=152,IPR_MTU3_TGIB3=152,IPR_MTU3_TGIC3=152,IPR_MTU3_TGID3=152,\r
+IPR_TPU10_TGI10A=156,IPR_TPU10_TGI10B=156,\r
+IPR_MTU4_TGIA4=156,IPR_MTU4_TGIB4=156,IPR_MTU4_TGIC4=156,IPR_MTU4_TGID4=156,IPR_MTU4_TCIV4=160,\r
+IPR_MTU5_TGIU5=161,IPR_MTU5_TGIV5=161,IPR_MTU5_TGIW5=161,\r
+IPR_TPU11_TGI11A=164,IPR_TPU11_TGI11B=164,\r
+IPR_POE_OEI1=166,IPR_POE_OEI2=166,\r
+IPR_TMR0_CMIA0=170,IPR_TMR0_CMIB0=170,IPR_TMR0_OVI0=170,\r
+IPR_TMR1_CMIA1=173,IPR_TMR1_CMIB1=173,IPR_TMR1_OVI1=173,\r
+IPR_TMR2_CMIA2=176,IPR_TMR2_CMIB2=176,IPR_TMR2_OVI2=176,\r
+IPR_TMR3_CMIA3=179,IPR_TMR3_CMIB3=179,IPR_TMR3_OVI3=179,\r
+IPR_RIIC0_EEI0=182,IPR_RIIC0_RXI0=183,IPR_RIIC0_TXI0=184,IPR_RIIC0_TEI0=185,\r
+IPR_RIIC1_EEI1=186,IPR_RIIC1_RXI1=187,IPR_RIIC1_TXI1=188,IPR_RIIC1_TEI1=189,\r
+IPR_RIIC2_EEI2=190,IPR_RIIC2_RXI2=191,IPR_RIIC2_TXI2=192,IPR_RIIC2_TEI2=193,\r
+IPR_RIIC3_EEI3=194,IPR_RIIC3_RXI3=195,IPR_RIIC3_TXI3=196,IPR_RIIC3_TEI3=197,\r
+IPR_DMAC_DMAC0I=198,IPR_DMAC_DMAC1I=199,IPR_DMAC_DMAC2I=200,IPR_DMAC_DMAC3I=201,\r
+IPR_SCI0_RXI0=214,IPR_SCI0_TXI0=214,IPR_SCI0_TEI0=214,\r
+IPR_SCI1_RXI1=217,IPR_SCI1_TXI1=217,IPR_SCI1_TEI1=217,\r
+IPR_SCI2_RXI2=220,IPR_SCI2_TXI2=220,IPR_SCI2_TEI2=220,\r
+IPR_SCI3_RXI3=223,IPR_SCI3_TXI3=223,IPR_SCI3_TEI3=223,\r
+IPR_SCI4_RXI4=226,IPR_SCI4_TXI4=226,IPR_SCI4_TEI4=226,\r
+IPR_SCI5_RXI5=229,IPR_SCI5_TXI5=229,IPR_SCI5_TEI5=229,\r
+IPR_SCI6_RXI6=232,IPR_SCI6_TXI6=232,IPR_SCI6_TEI6=232,\r
+IPR_SCI7_RXI7=235,IPR_SCI7_TXI7=235,IPR_SCI7_TEI7=235,\r
+IPR_SCI8_RXI8=238,IPR_SCI8_TXI8=238,IPR_SCI8_TEI8=238,\r
+IPR_SCI9_RXI9=241,IPR_SCI9_TXI9=241,IPR_SCI9_TEI9=241,\r
+IPR_SCI10_RXI10=244,IPR_SCI10_TXI10=244,IPR_SCI10_TEI10=244,\r
+IPR_SCI11_RXI11=247,IPR_SCI11_TXI11=247,IPR_SCI11_TEI11=247,\r
+IPR_SCI12_RXI12=250,IPR_SCI12_TXI12=250,IPR_SCI12_TEI12=250,\r
+IPR_IEB_IEBINT=253,\r
+IPR_BSC_=0,\r
+IPR_CMT0_=4,\r
+IPR_CMT1_=5,\r
+IPR_CMT2_=6,\r
+IPR_CMT3_=7,\r
+IPR_RSPI0_=39,\r
+IPR_RSPI1_=42,\r
+IPR_RSPI2_=45,\r
+IPR_CAN0_=48,\r
+IPR_CAN1_=52,\r
+IPR_CAN2_=56,\r
+IPR_USB_=90,\r
+IPR_AD0_=98,\r
+IPR_S12AD0_=102,\r
+IPR_SCIX_=122,\r
+IPR_SCIX_SCI=122,\r
+IPR_TPU0_=126,\r
+IPR_TPU0_TGI=126,\r
+IPR_TPU1_=130,\r
+IPR_TPU1_TGI=130,\r
+IPR_TPU2_=132,\r
+IPR_TPU2_TGI=132,\r
+IPR_TPU3_=134,\r
+IPR_TPU3_TGI=134,\r
+IPR_TPU4_=138,\r
+IPR_TPU4_TGI=138,\r
+IPR_TPU5_=140,\r
+IPR_TPU5_TGI=140,\r
+IPR_MTU5_=161,\r
+IPR_MTU5_TGI=161,\r
+IPR_TPU11_=164,\r
+IPR_TPU11_TGI=164,\r
+IPR_POE_=166,\r
+IPR_POE_OEI=166,\r
+IPR_TMR0_=170,\r
+IPR_TMR1_=173,\r
+IPR_TMR2_=176,\r
+IPR_TMR3_=179,\r
+IPR_SCI0_=214,\r
+IPR_SCI1_=217,\r
+IPR_SCI2_=220,\r
+IPR_SCI3_=223,\r
+IPR_SCI4_=226,\r
+IPR_SCI5_=229,\r
+IPR_SCI6_=232,\r
+IPR_SCI7_=235,\r
+IPR_SCI8_=238,\r
+IPR_SCI9_=241,\r
+IPR_SCI10_=244,\r
+IPR_SCI11_=247,\r
+IPR_SCI12_=250,\r
+IPR_IEB_=253\r
+};\r
+\r
+enum enum_grp {\r
+GRP_CAN0_ERS0=0,GRP_CAN1_ERS1=0,GRP_CAN2_ERS2=0,\r
+GRP_MTU0_TCIV0=1,GRP_MTU1_TCIV1=1,GRP_MTU1_TCIU1=1,\r
+GRP_MTU2_TCIV2=2,GRP_MTU2_TCIU2=2,GRP_MTU3_TCIV3=2,\r
+GRP_TPU0_TCI0V=3,GRP_TPU1_TCI1V=3,GRP_TPU1_TCI1U=3,GRP_TPU5_TCI5V=3,GRP_TPU5_TCI5U=3,\r
+GRP_TPU2_TCI2V=4,GRP_TPU2_TCI2U=4,GRP_TPU3_TCI3V=4,GRP_TPU4_TCI4V=4,GRP_TPU4_TCI4U=4,\r
+GRP_TPU6_TCI6V=5,GRP_TPU7_TCI7V=5,GRP_TPU7_TCI7U=5,GRP_TPU11_TCI11V=5,GRP_TPU11_TCI11U=5,\r
+GRP_TPU8_TCI8V=6,GRP_TPU8_TCI8U=6,GRP_TPU9_TCI9V=6,GRP_TPU10_TCI10V=6,GRP_TPU10_TCI10U=6,\r
+GRP_SCI0_ERI0=12,GRP_SCI1_ERI1=12,GRP_SCI2_ERI2=12,GRP_SCI3_ERI3=12,GRP_SCI4_ERI4=12,GRP_SCI5_ERI5=12,GRP_SCI6_ERI6=12,\r
+GRP_SCI7_ERI7=12,GRP_SCI8_ERI8=12,GRP_SCI9_ERI9=12,GRP_SCI10_ERI10=12,GRP_SCI11_ERI11=12,GRP_SCI12_ERI12=12,\r
+GRP_RSPI0_SPEI0=12,GRP_RSPI1_SPEI1=12,GRP_RSPI2_SPEI2=12\r
+};\r
+\r
+enum enum_gen {\r
+GEN_CAN0_ERS0=0,GEN_CAN1_ERS1=0,GEN_CAN2_ERS2=0,\r
+GEN_MTU0_TCIV0=1,GEN_MTU1_TCIV1=1,GEN_MTU1_TCIU1=1,\r
+GEN_MTU2_TCIV2=2,GEN_MTU2_TCIU2=2,GEN_MTU3_TCIV3=2,\r
+GEN_TPU0_TCI0V=3,GEN_TPU1_TCI1V=3,GEN_TPU1_TCI1U=3,GEN_TPU5_TCI5V=3,GEN_TPU5_TCI5U=3,\r
+GEN_TPU2_TCI2V=4,GEN_TPU2_TCI2U=4,GEN_TPU3_TCI3V=4,GEN_TPU4_TCI4V=4,GEN_TPU4_TCI4U=4,\r
+GEN_TPU6_TCI6V=5,GEN_TPU7_TCI7V=5,GEN_TPU7_TCI7U=5,GEN_TPU11_TCI11V=5,GEN_TPU11_TCI11U=5,\r
+GEN_TPU8_TCI8V=6,GEN_TPU8_TCI8U=6,GEN_TPU9_TCI9V=6,GEN_TPU10_TCI10V=6,GEN_TPU10_TCI10U=6,\r
+GEN_SCI0_ERI0=12,GEN_SCI1_ERI1=12,GEN_SCI2_ERI2=12,GEN_SCI3_ERI3=12,GEN_SCI4_ERI4=12,GEN_SCI5_ERI5=12,GEN_SCI6_ERI6=12,\r
+GEN_SCI7_ERI7=12,GEN_SCI8_ERI8=12,GEN_SCI9_ERI9=12,GEN_SCI10_ERI10=12,GEN_SCI11_ERI11=12,GEN_SCI12_ERI12=12,\r
+GEN_RSPI0_SPEI0=12,GEN_RSPI1_SPEI1=12,GEN_RSPI2_SPEI2=12\r
+};\r
+\r
+enum enum_gcr {\r
+GCR_CAN0_ERS0=0,GCR_CAN1_ERS1=0,GCR_CAN2_ERS2=0,\r
+GCR_MTU0_TCIV0=1,GCR_MTU1_TCIV1=1,GCR_MTU1_TCIU1=1,\r
+GCR_MTU2_TCIV2=2,GCR_MTU2_TCIU2=2,GCR_MTU3_TCIV3=2,\r
+GCR_TPU0_TCI0V=3,GCR_TPU1_TCI1V=3,GCR_TPU1_TCI1U=3,GCR_TPU5_TCI5V=3,GCR_TPU5_TCI5U=3,\r
+GCR_TPU2_TCI2V=4,GCR_TPU2_TCI2U=4,GCR_TPU3_TCI3V=4,GCR_TPU4_TCI4V=4,GCR_TPU4_TCI4U=4,\r
+GCR_TPU6_TCI6V=5,GCR_TPU7_TCI7V=5,GCR_TPU7_TCI7U=5,GCR_TPU11_TCI11V=5,GCR_TPU11_TCI11U=5,\r
+GCR_TPU8_TCI8V=6,GCR_TPU8_TCI8U=6,GCR_TPU9_TCI9V=6,GCR_TPU10_TCI10V=6,GCR_TPU10_TCI10U=6,\r
+GCR_SCI0_ERI0=12,GCR_SCI1_ERI1=12,GCR_SCI2_ERI2=12,GCR_SCI3_ERI3=12,GCR_SCI4_ERI4=12,GCR_SCI5_ERI5=12,GCR_SCI6_ERI6=12,\r
+GCR_SCI7_ERI7=12,GCR_SCI8_ERI8=12,GCR_SCI9_ERI9=12,GCR_SCI10_ERI10=12,GCR_SCI11_ERI11=12,GCR_SCI12_ERI12=12,\r
+GCR_RSPI0_SPEI0=12,GCR_RSPI1_SPEI1=12,GCR_RSPI2_SPEI2=12\r
+};\r
+\r
+#define IEN_BSC_BUSERR IEN0\r
+#define IEN_FCU_FIFERR IEN5\r
+#define IEN_FCU_FRDYI IEN7\r
+#define IEN_ICU_SWINT IEN3\r
+#define IEN_CMT0_CMI0 IEN4\r
+#define IEN_CMT1_CMI1 IEN5\r
+#define IEN_CMT2_CMI2 IEN6\r
+#define IEN_CMT3_CMI3 IEN7\r
+#define IEN_USB0_D0FIFO0 IEN1\r
+#define IEN_USB0_D1FIFO0 IEN2\r
+#define IEN_USB0_USBI0 IEN3\r
+#define IEN_USB0_D0FIFO1 IEN4\r
+#define IEN_USB0_D1FIFO1 IEN5\r
+#define IEN_USB0_USBI1 IEN6\r
+#define IEN_RSPI0_SPRI0 IEN7\r
+#define IEN_RSPI0_SPTI0 IEN0\r
+#define IEN_RSPI0_SPII0 IEN1\r
+#define IEN_RSPI1_SPRI1 IEN2\r
+#define IEN_RSPI1_SPTI1 IEN3\r
+#define IEN_RSPI1_SPII1 IEN4\r
+#define IEN_RSPI2_SPRI2 IEN5\r
+#define IEN_RSPI2_SPTI2 IEN6\r
+#define IEN_RSPI2_SPII2 IEN7\r
+#define IEN_CAN0_RXF0 IEN0\r
+#define IEN_CAN0_TXF0 IEN1\r
+#define IEN_CAN0_RXM0 IEN2\r
+#define IEN_CAN0_TXM0 IEN3\r
+#define IEN_CAN1_RXF1 IEN4\r
+#define IEN_CAN1_TXF1 IEN5\r
+#define IEN_CAN1_RXM1 IEN6\r
+#define IEN_CAN1_TXM1 IEN7\r
+#define IEN_CAN2_RXF2 IEN0\r
+#define IEN_CAN2_TXF2 IEN1\r
+#define IEN_CAN2_RXM2 IEN2\r
+#define IEN_CAN2_TXM2 IEN3\r
+#define IEN_RTC_COUNTUP IEN6\r
+#define IEN_ICU_IRQ0 IEN0\r
+#define IEN_ICU_IRQ1 IEN1\r
+#define IEN_ICU_IRQ2 IEN2\r
+#define IEN_ICU_IRQ3 IEN3\r
+#define IEN_ICU_IRQ4 IEN4\r
+#define IEN_ICU_IRQ5 IEN5\r
+#define IEN_ICU_IRQ6 IEN6\r
+#define IEN_ICU_IRQ7 IEN7\r
+#define IEN_ICU_IRQ8 IEN0\r
+#define IEN_ICU_IRQ9 IEN1\r
+#define IEN_ICU_IRQ10 IEN2\r
+#define IEN_ICU_IRQ11 IEN3\r
+#define IEN_ICU_IRQ12 IEN4\r
+#define IEN_ICU_IRQ13 IEN5\r
+#define IEN_ICU_IRQ14 IEN6\r
+#define IEN_ICU_IRQ15 IEN7\r
+#define IEN_USB_USBR0 IEN2\r
+#define IEN_RTC_ALARM IEN4\r
+#define IEN_RTC_PRD IEN5\r
+#define IEN_AD0_ADI0 IEN2\r
+#define IEN_S12AD0_S12ADI0 IEN6\r
+#define IEN_ICU_GROUPE0 IEN2\r
+#define IEN_ICU_GROUPE1 IEN3\r
+#define IEN_ICU_GROUPE2 IEN4\r
+#define IEN_ICU_GROUPE3 IEN5\r
+#define IEN_ICU_GROUPE4 IEN6\r
+#define IEN_ICU_GROUPE5 IEN7\r
+#define IEN_ICU_GROUPE6 IEN0\r
+#define IEN_ICU_GROUPL0 IEN2\r
+#define IEN_SCIX_SCIX0 IEN2\r
+#define IEN_SCIX_SCIX1 IEN3\r
+#define IEN_SCIX_SCIX2 IEN4\r
+#define IEN_SCIX_SCIX3 IEN5\r
+#define IEN_TPU0_TGI0A IEN6\r
+#define IEN_TPU0_TGI0B IEN7\r
+#define IEN_TPU0_TGI0C IEN0\r
+#define IEN_TPU0_TGI0D IEN1\r
+#define IEN_TPU1_TGI1A IEN2\r
+#define IEN_TPU1_TGI1B IEN3\r
+#define IEN_TPU2_TGI2A IEN4\r
+#define IEN_TPU2_TGI2B IEN5\r
+#define IEN_TPU3_TGI3A IEN6\r
+#define IEN_TPU3_TGI3B IEN7\r
+#define IEN_TPU3_TGI3C IEN0\r
+#define IEN_TPU3_TGI3D IEN1\r
+#define IEN_TPU4_TGI4A IEN2\r
+#define IEN_TPU4_TGI4B IEN3\r
+#define IEN_TPU5_TGI5A IEN4\r
+#define IEN_TPU5_TGI5B IEN5\r
+#define IEN_TPU6_TGI6A IEN6\r
+#define IEN_TPU6_TGI6B IEN7\r
+#define IEN_TPU6_TGI6C IEN0\r
+#define IEN_TPU6_TGI6D IEN1\r
+#define IEN_MTU0_TGIA0 IEN6\r
+#define IEN_MTU0_TGIB0 IEN7\r
+#define IEN_MTU0_TGIC0 IEN0\r
+#define IEN_MTU0_TGID0 IEN1\r
+#define IEN_MTU0_TGIE0 IEN2\r
+#define IEN_MTU0_TGIF0 IEN3\r
+#define IEN_TPU7_TGI7A IEN4\r
+#define IEN_TPU7_TGI7B IEN5\r
+#define IEN_MTU1_TGIA1 IEN4\r
+#define IEN_MTU1_TGIB1 IEN5\r
+#define IEN_TPU8_TGI8A IEN6\r
+#define IEN_TPU8_TGI8B IEN7\r
+#define IEN_MTU2_TGIA2 IEN6\r
+#define IEN_MTU2_TGIB2 IEN7\r
+#define IEN_TPU9_TGI9A IEN0\r
+#define IEN_TPU9_TGI9B IEN1\r
+#define IEN_TPU9_TGI9C IEN2\r
+#define IEN_TPU9_TGI9D IEN3\r
+#define IEN_MTU3_TGIA3 IEN0\r
+#define IEN_MTU3_TGIB3 IEN1\r
+#define IEN_MTU3_TGIC3 IEN2\r
+#define IEN_MTU3_TGID3 IEN3\r
+#define IEN_TPU10_TGI10A IEN4\r
+#define IEN_TPU10_TGI10B IEN5\r
+#define IEN_MTU4_TGIA4 IEN4\r
+#define IEN_MTU4_TGIB4 IEN5\r
+#define IEN_MTU4_TGIC4 IEN6\r
+#define IEN_MTU4_TGID4 IEN7\r
+#define IEN_MTU4_TCIV4 IEN0\r
+#define IEN_MTU5_TGIU5 IEN1\r
+#define IEN_MTU5_TGIV5 IEN2\r
+#define IEN_MTU5_TGIW5 IEN3\r
+#define IEN_TPU11_TGI11A IEN4\r
+#define IEN_TPU11_TGI11B IEN5\r
+#define IEN_POE_OEI1 IEN6\r
+#define IEN_POE_OEI2 IEN7\r
+#define IEN_TMR0_CMIA0 IEN2\r
+#define IEN_TMR0_CMIB0 IEN3\r
+#define IEN_TMR0_OVI0 IEN4\r
+#define IEN_TMR1_CMIA1 IEN5\r
+#define IEN_TMR1_CMIB1 IEN6\r
+#define IEN_TMR1_OVI1 IEN7\r
+#define IEN_TMR2_CMIA2 IEN0\r
+#define IEN_TMR2_CMIB2 IEN1\r
+#define IEN_TMR2_OVI2 IEN2\r
+#define IEN_TMR3_CMIA3 IEN3\r
+#define IEN_TMR3_CMIB3 IEN4\r
+#define IEN_TMR3_OVI3 IEN5\r
+#define IEN_RIIC0_EEI0 IEN6\r
+#define IEN_RIIC0_RXI0 IEN7\r
+#define IEN_RIIC0_TXI0 IEN0\r
+#define IEN_RIIC0_TEI0 IEN1\r
+#define IEN_RIIC1_EEI1 IEN2\r
+#define IEN_RIIC1_RXI1 IEN3\r
+#define IEN_RIIC1_TXI1 IEN4\r
+#define IEN_RIIC1_TEI1 IEN5\r
+#define IEN_RIIC2_EEI2 IEN6\r
+#define IEN_RIIC2_RXI2 IEN7\r
+#define IEN_RIIC2_TXI2 IEN0\r
+#define IEN_RIIC2_TEI2 IEN1\r
+#define IEN_RIIC3_EEI3 IEN2\r
+#define IEN_RIIC3_RXI3 IEN3\r
+#define IEN_RIIC3_TXI3 IEN4\r
+#define IEN_RIIC3_TEI3 IEN5\r
+#define IEN_DMAC_DMAC0I IEN6\r
+#define IEN_DMAC_DMAC1I IEN7\r
+#define IEN_DMAC_DMAC2I IEN0\r
+#define IEN_DMAC_DMAC3I IEN1\r
+#define IEN_SCI0_RXI0 IEN6\r
+#define IEN_SCI0_TXI0 IEN7\r
+#define IEN_SCI0_TEI0 IEN0\r
+#define IEN_SCI1_RXI1 IEN1\r
+#define IEN_SCI1_TXI1 IEN2\r
+#define IEN_SCI1_TEI1 IEN3\r
+#define IEN_SCI2_RXI2 IEN4\r
+#define IEN_SCI2_TXI2 IEN5\r
+#define IEN_SCI2_TEI2 IEN6\r
+#define IEN_SCI3_RXI3 IEN7\r
+#define IEN_SCI3_TXI3 IEN0\r
+#define IEN_SCI3_TEI3 IEN1\r
+#define IEN_SCI4_RXI4 IEN2\r
+#define IEN_SCI4_TXI4 IEN3\r
+#define IEN_SCI4_TEI4 IEN4\r
+#define IEN_SCI5_RXI5 IEN5\r
+#define IEN_SCI5_TXI5 IEN6\r
+#define IEN_SCI5_TEI5 IEN7\r
+#define IEN_SCI6_RXI6 IEN0\r
+#define IEN_SCI6_TXI6 IEN1\r
+#define IEN_SCI6_TEI6 IEN2\r
+#define IEN_SCI7_RXI7 IEN3\r
+#define IEN_SCI7_TXI7 IEN4\r
+#define IEN_SCI7_TEI7 IEN5\r
+#define IEN_SCI8_RXI8 IEN6\r
+#define IEN_SCI8_TXI8 IEN7\r
+#define IEN_SCI8_TEI8 IEN0\r
+#define IEN_SCI9_RXI9 IEN1\r
+#define IEN_SCI9_TXI9 IEN2\r
+#define IEN_SCI9_TEI9 IEN3\r
+#define IEN_SCI10_RXI10 IEN4\r
+#define IEN_SCI10_TXI10 IEN5\r
+#define IEN_SCI10_TEI10 IEN6\r
+#define IEN_SCI11_RXI11 IEN7\r
+#define IEN_SCI11_TXI11 IEN0\r
+#define IEN_SCI11_TEI11 IEN1\r
+#define IEN_SCI12_RXI12 IEN2\r
+#define IEN_SCI12_TXI12 IEN3\r
+#define IEN_SCI12_TEI12 IEN4\r
+#define IEN_IEB_IEBINT IEN5\r
+\r
+#define VECT_BSC_BUSERR 16\r
+#define VECT_FCU_FIFERR 21\r
+#define VECT_FCU_FRDYI 23\r
+#define VECT_ICU_SWINT 27\r
+#define VECT_CMT0_CMI0 28\r
+#define VECT_CMT1_CMI1 29\r
+#define VECT_CMT2_CMI2 30\r
+#define VECT_CMT3_CMI3 31\r
+#define VECT_USB0_D0FIFO0 33\r
+#define VECT_USB0_D1FIFO0 34\r
+#define VECT_USB0_USBI0 35\r
+#define VECT_USB0_D0FIFO1 36\r
+#define VECT_USB0_D1FIFO1 37\r
+#define VECT_USB0_USBI1 38\r
+#define VECT_RSPI0_SPRI0 39\r
+#define VECT_RSPI0_SPTI0 40\r
+#define VECT_RSPI0_SPII0 41\r
+#define VECT_RSPI1_SPRI1 42\r
+#define VECT_RSPI1_SPTI1 43\r
+#define VECT_RSPI1_SPII1 44\r
+#define VECT_RSPI2_SPRI2 45\r
+#define VECT_RSPI2_SPTI2 46\r
+#define VECT_RSPI2_SPII2 47\r
+#define VECT_CAN0_RXF0 48\r
+#define VECT_CAN0_TXF0 49\r
+#define VECT_CAN0_RXM0 50\r
+#define VECT_CAN0_TXM0 51\r
+#define VECT_CAN1_RXF1 52\r
+#define VECT_CAN1_TXF1 53\r
+#define VECT_CAN1_RXM1 54\r
+#define VECT_CAN1_TXM1 55\r
+#define VECT_CAN2_RXF2 56\r
+#define VECT_CAN2_TXF2 57\r
+#define VECT_CAN2_RXM2 58\r
+#define VECT_CAN2_TXM2 59\r
+#define VECT_RTC_COUNTUP 62\r
+#define VECT_ICU_IRQ0 64\r
+#define VECT_ICU_IRQ1 65\r
+#define VECT_ICU_IRQ2 66\r
+#define VECT_ICU_IRQ3 67\r
+#define VECT_ICU_IRQ4 68\r
+#define VECT_ICU_IRQ5 69\r
+#define VECT_ICU_IRQ6 70\r
+#define VECT_ICU_IRQ7 71\r
+#define VECT_ICU_IRQ8 72\r
+#define VECT_ICU_IRQ9 73\r
+#define VECT_ICU_IRQ10 74\r
+#define VECT_ICU_IRQ11 75\r
+#define VECT_ICU_IRQ12 76\r
+#define VECT_ICU_IRQ13 77\r
+#define VECT_ICU_IRQ14 78\r
+#define VECT_ICU_IRQ15 79\r
+#define VECT_USB_USBR0 90\r
+#define VECT_RTC_ALARM 92\r
+#define VECT_RTC_PRD 93\r
+#define VECT_AD0_ADI0 98\r
+#define VECT_S12AD0_S12ADI0 102\r
+#define VECT_ICU_GROUPE0 106\r
+#define VECT_ICU_GROUPE1 107\r
+#define VECT_ICU_GROUPE2 108\r
+#define VECT_ICU_GROUPE3 109\r
+#define VECT_ICU_GROUPE4 110\r
+#define VECT_ICU_GROUPE5 111\r
+#define VECT_ICU_GROUPE6 112\r
+#define VECT_ICU_GROUPL0 114\r
+#define VECT_SCIX_SCIX0 122\r
+#define VECT_SCIX_SCIX1 123\r
+#define VECT_SCIX_SCIX2 124\r
+#define VECT_SCIX_SCIX3 125\r
+#define VECT_TPU0_TGI0A 126\r
+#define VECT_TPU0_TGI0B 127\r
+#define VECT_TPU0_TGI0C 128\r
+#define VECT_TPU0_TGI0D 129\r
+#define VECT_TPU1_TGI1A 130\r
+#define VECT_TPU1_TGI1B 131\r
+#define VECT_TPU2_TGI2A 132\r
+#define VECT_TPU2_TGI2B 133\r
+#define VECT_TPU3_TGI3A 134\r
+#define VECT_TPU3_TGI3B 135\r
+#define VECT_TPU3_TGI3C 136\r
+#define VECT_TPU3_TGI3D 137\r
+#define VECT_TPU4_TGI4A 138\r
+#define VECT_TPU4_TGI4B 139\r
+#define VECT_TPU5_TGI5A 140\r
+#define VECT_TPU5_TGI5B 141\r
+#define VECT_TPU6_TGI6A 142\r
+#define VECT_TPU6_TGI6B 143\r
+#define VECT_TPU6_TGI6C 144\r
+#define VECT_TPU6_TGI6D 145\r
+#define VECT_MTU0_TGIA0 142\r
+#define VECT_MTU0_TGIB0 143\r
+#define VECT_MTU0_TGIC0 144\r
+#define VECT_MTU0_TGID0 145\r
+#define VECT_MTU0_TGIE0 146\r
+#define VECT_MTU0_TGIF0 147\r
+#define VECT_TPU7_TGI7A 148\r
+#define VECT_TPU7_TGI7B 149\r
+#define VECT_MTU1_TGIA1 148\r
+#define VECT_MTU1_TGIB1 149\r
+#define VECT_TPU8_TGI8A 150\r
+#define VECT_TPU8_TGI8B 151\r
+#define VECT_MTU2_TGIA2 150\r
+#define VECT_MTU2_TGIB2 151\r
+#define VECT_TPU9_TGI9A 152\r
+#define VECT_TPU9_TGI9B 153\r
+#define VECT_TPU9_TGI9C 154\r
+#define VECT_TPU9_TGI9D 155\r
+#define VECT_MTU3_TGIA3 152\r
+#define VECT_MTU3_TGIB3 153\r
+#define VECT_MTU3_TGIC3 154\r
+#define VECT_MTU3_TGID3 155\r
+#define VECT_TPU10_TGI10A 156\r
+#define VECT_TPU10_TGI10B 157\r
+#define VECT_MTU4_TGIA4 156\r
+#define VECT_MTU4_TGIB4 157\r
+#define VECT_MTU4_TGIC4 158\r
+#define VECT_MTU4_TGID4 159\r
+#define VECT_MTU4_TCIV4 160\r
+#define VECT_MTU5_TGIU5 161\r
+#define VECT_MTU5_TGIV5 162\r
+#define VECT_MTU5_TGIW5 163\r
+#define VECT_TPU11_TGI11A 164\r
+#define VECT_TPU11_TGI11B 165\r
+#define VECT_POE_OEI1 166\r
+#define VECT_POE_OEI2 167\r
+#define VECT_TMR0_CMIA0 170\r
+#define VECT_TMR0_CMIB0 171\r
+#define VECT_TMR0_OVI0 172\r
+#define VECT_TMR1_CMIA1 173\r
+#define VECT_TMR1_CMIB1 174\r
+#define VECT_TMR1_OVI1 175\r
+#define VECT_TMR2_CMIA2 176\r
+#define VECT_TMR2_CMIB2 177\r
+#define VECT_TMR2_OVI2 178\r
+#define VECT_TMR3_CMIA3 179\r
+#define VECT_TMR3_CMIB3 180\r
+#define VECT_TMR3_OVI3 181\r
+#define VECT_RIIC0_EEI0 182\r
+#define VECT_RIIC0_RXI0 183\r
+#define VECT_RIIC0_TXI0 184\r
+#define VECT_RIIC0_TEI0 185\r
+#define VECT_RIIC1_EEI1 186\r
+#define VECT_RIIC1_RXI1 187\r
+#define VECT_RIIC1_TXI1 188\r
+#define VECT_RIIC1_TEI1 189\r
+#define VECT_RIIC2_EEI2 190\r
+#define VECT_RIIC2_RXI2 191\r
+#define VECT_RIIC2_TXI2 192\r
+#define VECT_RIIC2_TEI2 193\r
+#define VECT_RIIC3_EEI3 194\r
+#define VECT_RIIC3_RXI3 195\r
+#define VECT_RIIC3_TXI3 196\r
+#define VECT_RIIC3_TEI3 197\r
+#define VECT_DMAC_DMAC0I 198\r
+#define VECT_DMAC_DMAC1I 199\r
+#define VECT_DMAC_DMAC2I 200\r
+#define VECT_DMAC_DMAC3I 201\r
+#define VECT_SCI0_RXI0 214\r
+#define VECT_SCI0_TXI0 215\r
+#define VECT_SCI0_TEI0 216\r
+#define VECT_SCI1_RXI1 217\r
+#define VECT_SCI1_TXI1 218\r
+#define VECT_SCI1_TEI1 219\r
+#define VECT_SCI2_RXI2 220\r
+#define VECT_SCI2_TXI2 221\r
+#define VECT_SCI2_TEI2 222\r
+#define VECT_SCI3_RXI3 223\r
+#define VECT_SCI3_TXI3 224\r
+#define VECT_SCI3_TEI3 225\r
+#define VECT_SCI4_RXI4 226\r
+#define VECT_SCI4_TXI4 227\r
+#define VECT_SCI4_TEI4 228\r
+#define VECT_SCI5_RXI5 229\r
+#define VECT_SCI5_TXI5 230\r
+#define VECT_SCI5_TEI5 231\r
+#define VECT_SCI6_RXI6 232\r
+#define VECT_SCI6_TXI6 233\r
+#define VECT_SCI6_TEI6 234\r
+#define VECT_SCI7_RXI7 235\r
+#define VECT_SCI7_TXI7 236\r
+#define VECT_SCI7_TEI7 237\r
+#define VECT_SCI8_RXI8 238\r
+#define VECT_SCI8_TXI8 239\r
+#define VECT_SCI8_TEI8 240\r
+#define VECT_SCI9_RXI9 241\r
+#define VECT_SCI9_TXI9 242\r
+#define VECT_SCI9_TEI9 243\r
+#define VECT_SCI10_RXI10 244\r
+#define VECT_SCI10_TXI10 245\r
+#define VECT_SCI10_TEI10 246\r
+#define VECT_SCI11_RXI11 247\r
+#define VECT_SCI11_TXI11 248\r
+#define VECT_SCI11_TEI11 249\r
+#define VECT_SCI12_RXI12 250\r
+#define VECT_SCI12_TXI12 251\r
+#define VECT_SCI12_TEI12 252\r
+#define VECT_IEB_IEBINT 253\r
+\r
+#define MSTP_DMAC SYSTEM.MSTPCRA.BIT.MSTPA28\r
+#define MSTP_DMAC0 SYSTEM.MSTPCRA.BIT.MSTPA28\r
+#define MSTP_DMAC1 SYSTEM.MSTPCRA.BIT.MSTPA28\r
+#define MSTP_DMAC2 SYSTEM.MSTPCRA.BIT.MSTPA28\r
+#define MSTP_DMAC3 SYSTEM.MSTPCRA.BIT.MSTPA28\r
+#define MSTP_DTC SYSTEM.MSTPCRA.BIT.MSTPA28\r
+#define MSTP_AD SYSTEM.MSTPCRA.BIT.MSTPA23\r
+#define MSTP_DA SYSTEM.MSTPCRA.BIT.MSTPA19\r
+#define MSTP_S12AD SYSTEM.MSTPCRA.BIT.MSTPA17\r
+#define MSTP_CMT0 SYSTEM.MSTPCRA.BIT.MSTPA15\r
+#define MSTP_CMT1 SYSTEM.MSTPCRA.BIT.MSTPA15\r
+#define MSTP_CMT2 SYSTEM.MSTPCRA.BIT.MSTPA14\r
+#define MSTP_CMT3 SYSTEM.MSTPCRA.BIT.MSTPA14\r
+#define MSTP_TPU0 SYSTEM.MSTPCRA.BIT.MSTPA13\r
+#define MSTP_TPU1 SYSTEM.MSTPCRA.BIT.MSTPA13\r
+#define MSTP_TPU2 SYSTEM.MSTPCRA.BIT.MSTPA13\r
+#define MSTP_TPU3 SYSTEM.MSTPCRA.BIT.MSTPA13\r
+#define MSTP_TPU4 SYSTEM.MSTPCRA.BIT.MSTPA13\r
+#define MSTP_TPU5 SYSTEM.MSTPCRA.BIT.MSTPA13\r
+#define MSTP_TPU6 SYSTEM.MSTPCRA.BIT.MSTPA12\r
+#define MSTP_TPU7 SYSTEM.MSTPCRA.BIT.MSTPA12\r
+#define MSTP_TPU8 SYSTEM.MSTPCRA.BIT.MSTPA12\r
+#define MSTP_TPU9 SYSTEM.MSTPCRA.BIT.MSTPA12\r
+#define MSTP_TPU10 SYSTEM.MSTPCRA.BIT.MSTPA12\r
+#define MSTP_TPU11 SYSTEM.MSTPCRA.BIT.MSTPA12\r
+#define MSTP_PPG0 SYSTEM.MSTPCRA.BIT.MSTPA11\r
+#define MSTP_PPG1 SYSTEM.MSTPCRA.BIT.MSTPA10\r
+#define MSTP_MTU SYSTEM.MSTPCRA.BIT.MSTPA9\r
+#define MSTP_MTU0 SYSTEM.MSTPCRA.BIT.MSTPA9\r
+#define MSTP_MTU1 SYSTEM.MSTPCRA.BIT.MSTPA9\r
+#define MSTP_MTU2 SYSTEM.MSTPCRA.BIT.MSTPA9\r
+#define MSTP_MTU3 SYSTEM.MSTPCRA.BIT.MSTPA9\r
+#define MSTP_MTU4 SYSTEM.MSTPCRA.BIT.MSTPA9\r
+#define MSTP_MTU5 SYSTEM.MSTPCRA.BIT.MSTPA9\r
+#define MSTP_TMR0 SYSTEM.MSTPCRA.BIT.MSTPA5\r
+#define MSTP_TMR1 SYSTEM.MSTPCRA.BIT.MSTPA5\r
+#define MSTP_TMR01 SYSTEM.MSTPCRA.BIT.MSTPA5\r
+#define MSTP_TMR2 SYSTEM.MSTPCRA.BIT.MSTPA4\r
+#define MSTP_TMR3 SYSTEM.MSTPCRA.BIT.MSTPA4\r
+#define MSTP_TMR23 SYSTEM.MSTPCRA.BIT.MSTPA4\r
+#define MSTP_SCI0 SYSTEM.MSTPCRB.BIT.MSTPB31\r
+#define MSTP_SMCI0 SYSTEM.MSTPCRB.BIT.MSTPB31\r
+#define MSTP_SCI1 SYSTEM.MSTPCRB.BIT.MSTPB30\r
+#define MSTP_SMCI1 SYSTEM.MSTPCRB.BIT.MSTPB30\r
+#define MSTP_SCI2 SYSTEM.MSTPCRB.BIT.MSTPB29\r
+#define MSTP_SMCI2 SYSTEM.MSTPCRB.BIT.MSTPB29\r
+#define MSTP_SCI3 SYSTEM.MSTPCRB.BIT.MSTPB28\r
+#define MSTP_SMCI3 SYSTEM.MSTPCRB.BIT.MSTPB28\r
+#define MSTP_SCI4 SYSTEM.MSTPCRB.BIT.MSTPB27\r
+#define MSTP_SMCI4 SYSTEM.MSTPCRB.BIT.MSTPB27\r
+#define MSTP_SCI5 SYSTEM.MSTPCRB.BIT.MSTPB26\r
+#define MSTP_SMCI5 SYSTEM.MSTPCRB.BIT.MSTPB26\r
+#define MSTP_SCI6 SYSTEM.MSTPCRB.BIT.MSTPB25\r
+#define MSTP_SMCI6 SYSTEM.MSTPCRB.BIT.MSTPB25\r
+#define MSTP_SCI7 SYSTEM.MSTPCRB.BIT.MSTPB24\r
+#define MSTP_SMCI7 SYSTEM.MSTPCRB.BIT.MSTPB24\r
+#define MSTP_CRC SYSTEM.MSTPCRB.BIT.MSTPB23\r
+#define MSTP_RIIC0 SYSTEM.MSTPCRB.BIT.MSTPB21\r
+#define MSTP_RIIC1 SYSTEM.MSTPCRB.BIT.MSTPB20\r
+#define MSTP_USB0 SYSTEM.MSTPCRB.BIT.MSTPB19\r
+#define MSTP_RSPI0 SYSTEM.MSTPCRB.BIT.MSTPB17\r
+#define MSTP_RSPI1 SYSTEM.MSTPCRB.BIT.MSTPB16\r
+#define MSTP_TEMPS SYSTEM.MSTPCRB.BIT.MSTPB8\r
+#define MSTP_SCI12 SYSTEM.MSTPCRB.BIT.MSTPB4\r
+#define MSTP_SMCI12 SYSTEM.MSTPCRB.BIT.MSTPB4\r
+#define MSTP_CAN2 SYSTEM.MSTPCRB.BIT.MSTPB2\r
+#define MSTP_CAN1 SYSTEM.MSTPCRB.BIT.MSTPB1\r
+#define MSTP_CAN0 SYSTEM.MSTPCRB.BIT.MSTPB0\r
+#define MSTP_SCI8 SYSTEM.MSTPCRC.BIT.MSTPC27\r
+#define MSTP_SMCI8 SYSTEM.MSTPCRC.BIT.MSTPC27\r
+#define MSTP_SCI9 SYSTEM.MSTPCRC.BIT.MSTPC26\r
+#define MSTP_SMCI9 SYSTEM.MSTPCRC.BIT.MSTPC26\r
+#define MSTP_SCI10 SYSTEM.MSTPCRC.BIT.MSTPC25\r
+#define MSTP_SMCI10 SYSTEM.MSTPCRC.BIT.MSTPC25\r
+#define MSTP_SCI11 SYSTEM.MSTPCRC.BIT.MSTPC24\r
+#define MSTP_SMCI11 SYSTEM.MSTPCRC.BIT.MSTPC24\r
+#define MSTP_RSPI2 SYSTEM.MSTPCRC.BIT.MSTPC22\r
+#define MSTP_LVD SYSTEM.MSTPCRC.BIT.MSTPC20\r
+#define MSTP_IEB SYSTEM.MSTPCRC.BIT.MSTPC18\r
+#define MSTP_RIIC2 SYSTEM.MSTPCRC.BIT.MSTPC17\r
+#define MSTP_RIIC3 SYSTEM.MSTPCRC.BIT.MSTPC16\r
+#define MSTP_RAM1 SYSTEM.MSTPCRC.BIT.MSTPC1\r
+#define MSTP_RAM0 SYSTEM.MSTPCRC.BIT.MSTPC0\r
+\r
+#define IS_CAN0_ERS0 IS0\r
+#define IS_CAN1_ERS1 IS1\r
+#define IS_CAN2_ERS2 IS2\r
+#define IS_MTU0_TCIV0 IS0\r
+#define IS_MTU1_TCIV1 IS1\r
+#define IS_MTU1_TCIU1 IS2\r
+#define IS_MTU2_TCIV2 IS0\r
+#define IS_MTU2_TCIU2 IS1\r
+#define IS_MTU3_TCIV3 IS2\r
+#define IS_TPU0_TCI0V IS0\r
+#define IS_TPU1_TCI1V IS1\r
+#define IS_TPU1_TCI1U IS2\r
+#define IS_TPU5_TCI5V IS3\r
+#define IS_TPU5_TCI5U IS4\r
+#define IS_TPU2_TCI2V IS0\r
+#define IS_TPU2_TCI2U IS1\r
+#define IS_TPU3_TCI3V IS2\r
+#define IS_TPU4_TCI4V IS3\r
+#define IS_TPU4_TCI4U IS4\r
+#define IS_TPU6_TCI6V IS0\r
+#define IS_TPU7_TCI7V IS1\r
+#define IS_TPU7_TCI7U IS2\r
+#define IS_TPU11_TCI11V IS3\r
+#define IS_TPU11_TCI11U IS4\r
+#define IS_TPU8_TCI8V IS0\r
+#define IS_TPU8_TCI8U IS1\r
+#define IS_TPU9_TCI9V IS2\r
+#define IS_TPU10_TCI10V IS3\r
+#define IS_TPU10_TCI10U IS4\r
+#define IS_SCI0_ERI0 IS0\r
+#define IS_SCI1_ERI1 IS1\r
+#define IS_SCI2_ERI2 IS2\r
+#define IS_SCI3_ERI3 IS3\r
+#define IS_SCI4_ERI4 IS4\r
+#define IS_SCI5_ERI5 IS5\r
+#define IS_SCI6_ERI6 IS6\r
+#define IS_SCI7_ERI7 IS7\r
+#define IS_SCI8_ERI8 IS8\r
+#define IS_SCI9_ERI9 IS9\r
+#define IS_SCI10_ERI10 IS10\r
+#define IS_SCI11_ERI11 IS11\r
+#define IS_SCI12_ERI12 IS12\r
+#define IS_RSPI0_SPEI0 IS13\r
+#define IS_RSPI1_SPEI1 IS14\r
+#define IS_RSPI2_SPEI2 IS15\r
+\r
+#define EN_CAN0_ERS0 EN0\r
+#define EN_CAN1_ERS1 EN1\r
+#define EN_CAN2_ERS2 EN2\r
+#define EN_MTU0_TCIV0 EN0\r
+#define EN_MTU1_TCIV1 EN1\r
+#define EN_MTU1_TCIU1 EN2\r
+#define EN_MTU2_TCIV2 EN0\r
+#define EN_MTU2_TCIU2 EN1\r
+#define EN_MTU3_TCIV3 EN2\r
+#define EN_TPU0_TCI0V EN0\r
+#define EN_TPU1_TCI1V EN1\r
+#define EN_TPU1_TCI1U EN2\r
+#define EN_TPU5_TCI5V EN3\r
+#define EN_TPU5_TCI5U EN4\r
+#define EN_TPU2_TCI2V EN0\r
+#define EN_TPU2_TCI2U EN1\r
+#define EN_TPU3_TCI3V EN2\r
+#define EN_TPU4_TCI4V EN3\r
+#define EN_TPU4_TCI4U EN4\r
+#define EN_TPU6_TCI6V EN0\r
+#define EN_TPU7_TCI7V EN1\r
+#define EN_TPU7_TCI7U EN2\r
+#define EN_TPU11_TCI11V EN3\r
+#define EN_TPU11_TCI11U EN4\r
+#define EN_TPU8_TCI8V EN0\r
+#define EN_TPU8_TCI8U EN1\r
+#define EN_TPU9_TCI9V EN2\r
+#define EN_TPU10_TCI10V EN3\r
+#define EN_TPU10_TCI10U EN4\r
+#define EN_SCI0_ERI0 EN0\r
+#define EN_SCI1_ERI1 EN1\r
+#define EN_SCI2_ERI2 EN2\r
+#define EN_SCI3_ERI3 EN3\r
+#define EN_SCI4_ERI4 EN4\r
+#define EN_SCI5_ERI5 EN5\r
+#define EN_SCI6_ERI6 EN6\r
+#define EN_SCI7_ERI7 EN7\r
+#define EN_SCI8_ERI8 EN8\r
+#define EN_SCI9_ERI9 EN9\r
+#define EN_SCI10_ERI10 EN10\r
+#define EN_SCI11_ERI11 EN11\r
+#define EN_SCI12_ERI12 EN12\r
+#define EN_RSPI0_SPEI0 EN13\r
+#define EN_RSPI1_SPEI1 EN14\r
+#define EN_RSPI2_SPEI2 EN15\r
+\r
+#define CLR_CAN0_ERS0 CLR0\r
+#define CLR_CAN1_ERS1 CLR1\r
+#define CLR_CAN2_ERS2 CLR2\r
+#define CLR_MTU0_TCIV0 CLR0\r
+#define CLR_MTU1_TCIV1 CLR1\r
+#define CLR_MTU1_TCIU1 CLR2\r
+#define CLR_MTU2_TCIV2 CLR0\r
+#define CLR_MTU2_TCIU2 CLR1\r
+#define CLR_MTU3_TCIV3 CLR2\r
+#define CLR_TPU0_TCI0V CLR0\r
+#define CLR_TPU1_TCI1V CLR1\r
+#define CLR_TPU1_TCI1U CLR2\r
+#define CLR_TPU5_TCI5V CLR3\r
+#define CLR_TPU5_TCI5U CLR4\r
+#define CLR_TPU2_TCI2V CLR0\r
+#define CLR_TPU2_TCI2U CLR1\r
+#define CLR_TPU3_TCI3V CLR2\r
+#define CLR_TPU4_TCI4V CLR3\r
+#define CLR_TPU4_TCI4U CLR4\r
+#define CLR_TPU6_TCI6V CLR0\r
+#define CLR_TPU7_TCI7V CLR1\r
+#define CLR_TPU7_TCI7U CLR2\r
+#define CLR_TPU11_TCI11V CLR3\r
+#define CLR_TPU11_TCI11U CLR4\r
+#define CLR_TPU8_TCI8V CLR0\r
+#define CLR_TPU8_TCI8U CLR1\r
+#define CLR_TPU9_TCI9V CLR2\r
+#define CLR_TPU10_TCI10V CLR3\r
+#define CLR_TPU10_TCI10U CLR4\r
+#define CLR_SCI0_ERI0 CLR0\r
+#define CLR_SCI1_ERI1 CLR1\r
+#define CLR_SCI2_ERI2 CLR2\r
+#define CLR_SCI3_ERI3 CLR3\r
+#define CLR_SCI4_ERI4 CLR4\r
+#define CLR_SCI5_ERI5 CLR5\r
+#define CLR_SCI6_ERI6 CLR6\r
+#define CLR_SCI7_ERI7 CLR7\r
+#define CLR_SCI8_ERI8 CLR8\r
+#define CLR_SCI9_ERI9 CLR9\r
+#define CLR_SCI10_ERI10 CLR10\r
+#define CLR_SCI11_ERI11 CLR11\r
+#define CLR_SCI12_ERI12 CLR12\r
+#define CLR_RSPI0_SPEI0 CLR13\r
+#define CLR_RSPI1_SPEI1 CLR14\r
+#define CLR_RSPI2_SPEI2 CLR15\r
+\r
+#define CN_TPU6_TGI6A CN0\r
+#define CN_TPU6_TGI6B CN0\r
+#define CN_TPU6_TGI6C CN0\r
+#define CN_TPU6_TGI6D CN0\r
+#define CN_MTU0_TGIA0 CN0\r
+#define CN_MTU0_TGIB0 CN0\r
+#define CN_MTU0_TGIC0 CN0\r
+#define CN_MTU0_TGID0 CN0\r
+#define CN_MTU0_TGIE0 CN0\r
+#define CN_MTU0_TGIF0 CN0\r
+#define CN_TPU7_TGI7A CN1\r
+#define CN_TPU7_TGI7B CN1\r
+#define CN_MTU1_TGIA1 CN1\r
+#define CN_MTU1_TGIB1 CN1\r
+#define CN_TPU8_TGI8A CN2\r
+#define CN_TPU8_TGI8B CN2\r
+#define CN_MTU2_TGIA2 CN2\r
+#define CN_MTU2_TGIB2 CN2\r
+#define CN_TPU9_TGI9A CN3\r
+#define CN_TPU9_TGI9B CN3\r
+#define CN_TPU9_TGI9C CN3\r
+#define CN_TPU9_TGI9D CN3\r
+#define CN_MTU3_TGIA3 CN3\r
+#define CN_MTU3_TGIB3 CN3\r
+#define CN_MTU3_TGIC3 CN3\r
+#define CN_MTU3_TGID3 CN3\r
+#define CN_TPU10_TGI10A CN4\r
+#define CN_TPU10_TGI10B CN4\r
+#define CN_MTU4_TGIA4 CN4\r
+#define CN_MTU4_TGIB4 CN4\r
+#define CN_MTU4_TGIC4 CN4\r
+#define CN_MTU4_TGID4 CN4\r
+#define CN_MTU4_TGIV4 CN4\r
+#define CN_TPU11_TGI11A CN5\r
+#define CN_TPU11_TGI11B CN5\r
+#define CN_MTU5_TGIU5 CN5\r
+#define CN_MTU5_TGIV5 CN5\r
+#define CN_MTU5_TGIW5 CN5\r
+#define CN_TPU6_ CN0\r
+#define CN_MTU0_ CN0\r
+#define CN_TPU7_ CN1\r
+#define CN_MTU1_ CN1\r
+#define CN_TPU8_ CN2\r
+#define CN_MTU2_ CN2\r
+#define CN_TPU9_ CN3\r
+#define CN_MTU3_ CN3\r
+#define CN_TPU10_ CN4\r
+#define CN_MTU4_ CN4\r
+#define CN_TPU11_ CN5\r
+#define CN_MTU5_ CN5\r
+\r
+#define __IR( x ) ICU.IR[ IR ## x ].BIT.IR\r
+#define _IR( x ) __IR( x )\r
+#define IR( x , y ) _IR( _ ## x ## _ ## y )\r
+#define __DTCE( x ) ICU.DTCER[ DTCE ## x ].BIT.DTCE\r
+#define _DTCE( x ) __DTCE( x )\r
+#define DTCE( x , y ) _DTCE( _ ## x ## _ ## y )\r
+#define __IEN( x ) ICU.IER[ IER ## x ].BIT.IEN ## x\r
+#define _IEN( x ) __IEN( x )\r
+#define IEN( x , y ) _IEN( _ ## x ## _ ## y )\r
+#define __IPR( x ) ICU.IPR[ IPR ## x ].BIT.IPR\r
+#define _IPR( x ) __IPR( x )\r
+#define IPR( x , y ) _IPR( _ ## x ## _ ## y )\r
+#define __VECT( x ) VECT ## x\r
+#define _VECT( x ) __VECT( x )\r
+#define VECT( x , y ) _VECT( _ ## x ## _ ## y )\r
+#define __MSTP( x ) MSTP ## x\r
+#define _MSTP( x ) __MSTP( x )\r
+#define MSTP( x ) _MSTP( _ ## x )\r
+\r
+#define __IS( x ) ICU.GRP[ GRP ## x ].BIT.IS ## x\r
+#define _IS( x ) __IS( x )\r
+#define IS( x , y ) _IS( _ ## x ## _ ## y )\r
+#define __EN( x ) ICU.GEN[ GEN ## x ].BIT.EN ## x\r
+#define _EN( x ) __EN( x )\r
+#define EN( x , y ) _EN( _ ## x ## _ ## y )\r
+#define __CLR( x ) ICU.GCR[ GCR ## x ].BIT.CLR ## x\r
+#define _CLR( x ) __CLR( x )\r
+#define CLR( x , y ) _CLR( _ ## x ## _ ## y )\r
+#define __CN( x ) ICU.SEL.BIT.CN ## x\r
+#define _CN( x ) __CN( x )\r
+#define CN( x , y ) _CN( _ ## x ## _ ## y )\r
+\r
+#define AD (*(volatile struct st_ad __evenaccess *)0x89800)\r
+#define BSC (*(volatile struct st_bsc __evenaccess *)0x81300)\r
+#define CAN0 (*(volatile struct st_can __evenaccess *)0x90200)\r
+#define CAN1 (*(volatile struct st_can __evenaccess *)0x91200)\r
+#define CAN2 (*(volatile struct st_can __evenaccess *)0x92200)\r
+#define CMT (*(volatile struct st_cmt __evenaccess *)0x88000)\r
+#define CMT0 (*(volatile struct st_cmt0 __evenaccess *)0x88002)\r
+#define CMT1 (*(volatile struct st_cmt0 __evenaccess *)0x88008)\r
+#define CMT2 (*(volatile struct st_cmt0 __evenaccess *)0x88012)\r
+#define CMT3 (*(volatile struct st_cmt0 __evenaccess *)0x88018)\r
+#define CRC (*(volatile struct st_crc __evenaccess *)0x88280)\r
+#define DA (*(volatile struct st_da __evenaccess *)0x880C0)\r
+#define DMAC (*(volatile struct st_dmac __evenaccess *)0x82200)\r
+#define DMAC0 (*(volatile struct st_dmac0 __evenaccess *)0x82000)\r
+#define DMAC1 (*(volatile struct st_dmac1 __evenaccess *)0x82040)\r
+#define DMAC2 (*(volatile struct st_dmac1 __evenaccess *)0x82080)\r
+#define DMAC3 (*(volatile struct st_dmac1 __evenaccess *)0x820C0)\r
+#define DTC (*(volatile struct st_dtc __evenaccess *)0x82400)\r
+#define FLASH (*(volatile struct st_flash __evenaccess *)0x8C296)\r
+#define ICU (*(volatile struct st_icu __evenaccess *)0x87000)\r
+#define IEB (*(volatile struct st_ieb __evenaccess *)0x8A800)\r
+#define IWDT (*(volatile struct st_iwdt __evenaccess *)0x88030)\r
+#define MPC (*(volatile struct st_mpc __evenaccess *)0x8C100)\r
+#define MTU (*(volatile struct st_mtu __evenaccess *)0x8860A)\r
+#define MTU0 (*(volatile struct st_mtu0 __evenaccess *)0x88690)\r
+#define MTU1 (*(volatile struct st_mtu1 __evenaccess *)0x88690)\r
+#define MTU2 (*(volatile struct st_mtu2 __evenaccess *)0x88692)\r
+#define MTU3 (*(volatile struct st_mtu3 __evenaccess *)0x88600)\r
+#define MTU4 (*(volatile struct st_mtu4 __evenaccess *)0x88600)\r
+#define MTU5 (*(volatile struct st_mtu5 __evenaccess *)0x88694)\r
+#define POE (*(volatile struct st_poe __evenaccess *)0x88900)\r
+#define PORT0 (*(volatile struct st_port0 __evenaccess *)0x8C000)\r
+#define PORT1 (*(volatile struct st_port1 __evenaccess *)0x8C001)\r
+#define PORT2 (*(volatile struct st_port2 __evenaccess *)0x8C002)\r
+#define PORT3 (*(volatile struct st_port3 __evenaccess *)0x8C003)\r
+#define PORT4 (*(volatile struct st_port4 __evenaccess *)0x8C004)\r
+#define PORT5 (*(volatile struct st_port5 __evenaccess *)0x8C005)\r
+#define PORT6 (*(volatile struct st_port6 __evenaccess *)0x8C006)\r
+#define PORT7 (*(volatile struct st_port7 __evenaccess *)0x8C007)\r
+#define PORT8 (*(volatile struct st_port8 __evenaccess *)0x8C008)\r
+#define PORT9 (*(volatile struct st_port9 __evenaccess *)0x8C009)\r
+#define PORTA (*(volatile struct st_porta __evenaccess *)0x8C00A)\r
+#define PORTB (*(volatile struct st_portb __evenaccess *)0x8C00B)\r
+#define PORTC (*(volatile struct st_portc __evenaccess *)0x8C00C)\r
+#define PORTD (*(volatile struct st_portd __evenaccess *)0x8C00D)\r
+#define PORTE (*(volatile struct st_porte __evenaccess *)0x8C00E)\r
+#define PORTF (*(volatile struct st_portf __evenaccess *)0x8C00F)\r
+#define PORTG (*(volatile struct st_portg __evenaccess *)0x8C010)\r
+#define PORTH (*(volatile struct st_porth __evenaccess *)0x8C011)\r
+#define PORTJ (*(volatile struct st_portj __evenaccess *)0x8C012)\r
+#define PORTK (*(volatile struct st_portk __evenaccess *)0x8C013)\r
+#define PORTL (*(volatile struct st_portl __evenaccess *)0x8C014)\r
+#define PPG0 (*(volatile struct st_ppg0 __evenaccess *)0x881E6)\r
+#define PPG1 (*(volatile struct st_ppg1 __evenaccess *)0x881F0)\r
+#define RIIC0 (*(volatile struct st_riic0 __evenaccess *)0x88300)\r
+#define RIIC1 (*(volatile struct st_riic1 __evenaccess *)0x88320)\r
+#define RIIC2 (*(volatile struct st_riic1 __evenaccess *)0x88340)\r
+#define RIIC3 (*(volatile struct st_riic1 __evenaccess *)0x88360)\r
+#define RSPI0 (*(volatile struct st_rspi __evenaccess *)0x88380)\r
+#define RSPI1 (*(volatile struct st_rspi __evenaccess *)0x883A0)\r
+#define RSPI2 (*(volatile struct st_rspi __evenaccess *)0x883C0)\r
+#define RTC (*(volatile struct st_rtc __evenaccess *)0x8C400)\r
+#define S12AD (*(volatile struct st_s12ad __evenaccess *)0x89000)\r
+#define SCI0 (*(volatile struct st_sci0 __evenaccess *)0x8A000)\r
+#define SCI1 (*(volatile struct st_sci0 __evenaccess *)0x8A020)\r
+#define SCI2 (*(volatile struct st_sci0 __evenaccess *)0x8A040)\r
+#define SCI3 (*(volatile struct st_sci0 __evenaccess *)0x8A060)\r
+#define SCI4 (*(volatile struct st_sci0 __evenaccess *)0x8A080)\r
+#define SCI5 (*(volatile struct st_sci0 __evenaccess *)0x8A0A0)\r
+#define SCI6 (*(volatile struct st_sci0 __evenaccess *)0x8A0C0)\r
+#define SCI7 (*(volatile struct st_sci7 __evenaccess *)0x8A0E0)\r
+#define SCI8 (*(volatile struct st_sci0 __evenaccess *)0x8A100)\r
+#define SCI9 (*(volatile struct st_sci0 __evenaccess *)0x8A120)\r
+#define SCI10 (*(volatile struct st_sci0 __evenaccess *)0x8A140)\r
+#define SCI11 (*(volatile struct st_sci0 __evenaccess *)0x8A160)\r
+#define SCI12 (*(volatile struct st_sci12 __evenaccess *)0x8B300)\r
+#define SMCI0 (*(volatile struct st_smci0 __evenaccess *)0x8A000)\r
+#define SMCI1 (*(volatile struct st_smci0 __evenaccess *)0x8A020)\r
+#define SMCI2 (*(volatile struct st_smci0 __evenaccess *)0x8A040)\r
+#define SMCI3 (*(volatile struct st_smci0 __evenaccess *)0x8A060)\r
+#define SMCI4 (*(volatile struct st_smci0 __evenaccess *)0x8A080)\r
+#define SMCI5 (*(volatile struct st_smci0 __evenaccess *)0x8A0A0)\r
+#define SMCI6 (*(volatile struct st_smci0 __evenaccess *)0x8A0C0)\r
+#define SMCI7 (*(volatile struct st_smci7 __evenaccess *)0x8A0E0)\r
+#define SMCI8 (*(volatile struct st_smci0 __evenaccess *)0x8A100)\r
+#define SMCI9 (*(volatile struct st_smci0 __evenaccess *)0x8A120)\r
+#define SMCI10 (*(volatile struct st_smci0 __evenaccess *)0x8A140)\r
+#define SMCI11 (*(volatile struct st_smci0 __evenaccess *)0x8A160)\r
+#define SMCI12 (*(volatile struct st_smci0 __evenaccess *)0x8B300)\r
+#define SYSTEM (*(volatile struct st_system __evenaccess *)0x80000)\r
+#define TEMPS (*(volatile struct st_temps __evenaccess *)0x8C500)\r
+#define TMR0 (*(volatile struct st_tmr0 __evenaccess *)0x88200)\r
+#define TMR1 (*(volatile struct st_tmr1 __evenaccess *)0x88201)\r
+#define TMR2 (*(volatile struct st_tmr0 __evenaccess *)0x88210)\r
+#define TMR3 (*(volatile struct st_tmr1 __evenaccess *)0x88211)\r
+#define TMR01 (*(volatile struct st_tmr01 __evenaccess *)0x88204)\r
+#define TMR23 (*(volatile struct st_tmr01 __evenaccess *)0x88214)\r
+#define TPU0 (*(volatile struct st_tpu0 __evenaccess *)0x88108)\r
+#define TPU1 (*(volatile struct st_tpu1 __evenaccess *)0x88108)\r
+#define TPU2 (*(volatile struct st_tpu2 __evenaccess *)0x8810A)\r
+#define TPU3 (*(volatile struct st_tpu3 __evenaccess *)0x8810A)\r
+#define TPU4 (*(volatile struct st_tpu4 __evenaccess *)0x8810C)\r
+#define TPU5 (*(volatile struct st_tpu5 __evenaccess *)0x8810C)\r
+#define TPU6 (*(volatile struct st_tpu0 __evenaccess *)0x88178)\r
+#define TPU7 (*(volatile struct st_tpu1 __evenaccess *)0x88178)\r
+#define TPU8 (*(volatile struct st_tpu2 __evenaccess *)0x8817A)\r
+#define TPU9 (*(volatile struct st_tpu3 __evenaccess *)0x8817A)\r
+#define TPU10 (*(volatile struct st_tpu4 __evenaccess *)0x8817C)\r
+#define TPU11 (*(volatile struct st_tpu5 __evenaccess *)0x8817C)\r
+#define TPUA (*(volatile struct st_tpua __evenaccess *)0x88100)\r
+#define TPUB (*(volatile struct st_tpub __evenaccess *)0x88170)\r
+#define USB (*(volatile struct st_usb __evenaccess *)0xA0400)\r
+#define USB0 (*(volatile struct st_usb0 __evenaccess *)0xA0000)\r
+#define WDT (*(volatile struct st_wdt __evenaccess *)0x88020)\r
+#pragma bit_order\r
+#pragma packoption\r
+#endif\r
--- /dev/null
+/***********************************************************************/\r
+/* */\r
+/* FILE :lowsrc.h */\r
+/* DATE :Wed, Aug 11, 2010 */\r
+/* DESCRIPTION :Header file of I/O Stream file */\r
+/* CPU TYPE :Other */\r
+/* */\r
+/* This file is generated by Renesas Project Generator (Ver.4.50). */\r
+/* NOTE:THIS IS A TYPICAL EXAMPLE. */\r
+/* */\r
+/***********************************************************************/\r
+/*Number of I/O Stream*/\r
+#define IOSTREAM 20\r
--- /dev/null
+\r
+/******************************************************************************\r
+* DISCLAIMER\r
+* Please refer to http://www.renesas.com/disclaimer\r
+******************************************************************************\r
+ Copyright (C) 2008. Renesas Technology Corp., All Rights Reserved.\r
+*******************************************************************************\r
+* File Name : rskrx630def.h\r
+* Version : 1.00\r
+* Description : RSK RX630 board specific settings\r
+******************************************************************************\r
+* History : DD.MM.YYYY Version Description\r
+* : 06.10.2009 1.00 First Release\r
+******************************************************************************/\r
+\r
+#ifndef RSKRX630_H\r
+#define RSKRX630_H\r
+\r
+/******************************************************************************\r
+Includes <System Includes> , "Project Includes"\r
+******************************************************************************/\r
+#include "cgc.h"\r
+\r
+/******************************************************************************\r
+Typedef definitions\r
+******************************************************************************/\r
+\r
+/******************************************************************************\r
+Macro definitions\r
+******************************************************************************/\r
+\r
+/* System Clock Settings */\r
+/* Clock settings defined in CGC_SET.H */\r
+#if 0\r
+#define XTAL_FREQUENCY (12000000L)\r
+#define ICLK_MUL (8)\r
+#define PCLK_MUL (4)\r
+#define BCLK_MUL (4)\r
+#define ICLK_FREQUENCY (XTAL_FREQUENCY * ICLK_MUL)\r
+#define PCLK_FREQUENCY (XTAL_FREQUENCY * PCLK_MUL)\r
+#define BCLK_FREQUENCY (XTAL_FREQUENCY * BCLK_MUL)\r
+#endif\r
+\r
+#define CMT0_CLK_SELECT (512)\r
+\r
+/* General Values */\r
+#define LED_ON (0)\r
+#define LED_OFF (1)\r
+#define SET_BIT_HIGH (1)\r
+#define SET_BIT_LOW (0)\r
+#define SET_BYTE_HIGH (0xFF)\r
+#define SET_BYTE_LOW (0x00)\r
+\r
+/* Define switches to be polled if not available as interrupts */\r
+#define SW_ACTIVE FALSE\r
+#define SW1 PORT3.PODR.BIT.B2\r
+#define SW2 PORT4.PODR.BIT.B4\r
+#define SW3 PORT0.PODR.BIT.B7\r
+#define SW1_PDR PORT3.PDR.BIT.B2\r
+#define SW2_PDR PORT4.PDR.BIT.B4\r
+#define SW3_PDR PORT0.PDR.BIT.B7\r
+\r
+/* LEDs */\r
+#define LED0 PORTC.PODR.BIT.B5\r
+#define LED1 PORT2.PODR.BIT.B4\r
+#define LED2 PORTC.PODR.BIT.B2\r
+#define LED3 PORT1.PODR.BIT.B7\r
+#define LED0_PDR PORTC.PDR.BIT.B5\r
+#define LED1_PDR PORT2.PDR.BIT.B4\r
+#define LED2_PDR PORTC.PDR.BIT.B2\r
+#define LED3_PDR PORT1.PDR.BIT.B7\r
+\r
+/* 2x8 segment LCD */\r
+#define LCD_RS PORTJ.PODR.BIT.B3\r
+#define LCD_EN PORT3.PODR.BIT.B3\r
+#define LCD_DATA PORTE.PODR.BYTE\r
+#define LCD_RS_PDR PORTJ.PDR.BIT.B3\r
+#define LCD_EN_PDR PORT3.PDR.BIT.B3\r
+#define LCD_DATA_PDR PORTE.PDR.BYTE\r
+\r
+\r
+\r
+/******************************************************************************\r
+Variable Externs\r
+******************************************************************************/\r
+\r
+/******************************************************************************\r
+Functions Prototypes\r
+******************************************************************************/\r
+\r
+\r
+\r
+/* RSKRX62N_H */\r
+#endif \r
+\r
--- /dev/null
+/***********************************************************************/\r
+/* */\r
+/* FILE :stacksct.h */\r
+/* DATE :Wed, Aug 11, 2010 */\r
+/* DESCRIPTION :Setting of Stack area */\r
+/* CPU TYPE :Other */\r
+/* */\r
+/* This file is generated by Renesas Project Generator (Ver.4.50). */\r
+/* NOTE:THIS IS A TYPICAL EXAMPLE. */\r
+/* */\r
+/***********************************************************************/\r
+#pragma stacksize su=0x300 \r
+#pragma stacksize si=0x100 \r
--- /dev/null
+/***********************************************************************/\r
+/* */\r
+/* FILE :typedefine.h */\r
+/* DATE :Wed, Aug 11, 2010 */\r
+/* DESCRIPTION :Aliases of Integer Type */\r
+/* CPU TYPE :Other */\r
+/* */\r
+/* This file is generated by Renesas Project Generator (Ver.4.50). */\r
+/* NOTE:THIS IS A TYPICAL EXAMPLE. */\r
+/* */\r
+/***********************************************************************/\r
+ \r
+\r
+\r
+/*********************************************************************\r
+*\r
+* Device : RX\r
+*\r
+* File Name : typedefine.h\r
+*\r
+* Abstract : Aliases of Integer Type.\r
+*\r
+* History : 1.00 (2009-08-07)\r
+*\r
+* NOTE : THIS IS A TYPICAL EXAMPLE.\r
+*\r
+* Copyright(c) 2009 Renesas Technology Corp.\r
+* And Renesas Solutions Corp.,All Rights Reserved. \r
+*\r
+*********************************************************************/\r
+\r
+typedef signed char _SBYTE;\r
+typedef unsigned char _UBYTE;\r
+typedef signed short _SWORD;\r
+typedef unsigned short _UWORD;\r
+typedef signed int _SINT;\r
+typedef unsigned int _UINT;\r
+typedef signed long _SDWORD;\r
+typedef unsigned long _UDWORD;\r
+typedef signed long long _SQWORD;\r
+typedef unsigned long long _UQWORD;\r
--- /dev/null
+/***********************************************************************/\r
+/* */\r
+/* FILE :vect.h */\r
+/* DATE :Wed, Aug 11, 2010 */\r
+/* DESCRIPTION :Definition of Vector */\r
+/* CPU TYPE :Other */\r
+/* */\r
+/* This file is generated by Renesas Project Generator (Ver.4.50). */\r
+/* NOTE:THIS IS A TYPICAL EXAMPLE. */\r
+/* */\r
+/***********************************************************************/\r
+ \r
+\r
+\r
+/*********************************************************************\r
+*\r
+* Device : RX/RX600\r
+*\r
+* File Name : vect.h\r
+*\r
+* Abstract : Definition of Vector.\r
+*\r
+* History : 1.00 (2009-08-07)\r
+*\r
+* NOTE : THIS IS A TYPICAL EXAMPLE.\r
+*\r
+* Copyright(c) 2009 Renesas Technology Corp.\r
+* And Renesas Solutions Corp.,All Rights Reserved. \r
+*\r
+*********************************************************************/\r
+\r
+// Exception(Supervisor Instruction)\r
+#pragma interrupt (Excep_SuperVisorInst)\r
+void Excep_SuperVisorInst(void);\r
+\r
+// Exception(Undefined Instruction)\r
+#pragma interrupt (Excep_UndefinedInst)\r
+void Excep_UndefinedInst(void);\r
+\r
+// Exception(Floating Point)\r
+#pragma interrupt (Excep_FloatingPoint)\r
+void Excep_FloatingPoint(void);\r
+\r
+// NMI\r
+#pragma interrupt (NonMaskableInterrupt)\r
+void NonMaskableInterrupt(void);\r
+\r
+// Dummy\r
+#pragma interrupt (Dummy)\r
+void Dummy(void);\r
+\r
+// BRK\r
+#pragma interrupt (Excep_BRK(vect=0))\r
+void Excep_BRK(void);\r
+\r
+//;<<VECTOR DATA START (POWER ON RESET)>>\r
+//;Power On Reset PC\r
+extern void PowerON_Reset_PC(void); \r
+//;<<VECTOR DATA END (POWER ON RESET)>>\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd.\r
+ \r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ >>>NOTE<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ http://www.FreeRTOS.org - Documentation, latest information, license and\r
+ contact details.\r
+\r
+ http://www.SafeRTOS.com - A version that is certified for use in safety\r
+ critical systems.\r
+\r
+ http://www.OpenRTOS.com - Commercial support, development, porting,\r
+ licensing and training services.\r
+*/\r
+\r
+/* \r
+ * This is a very simple demo that creates two tasks and one queue. One task\r
+ * (the queue receive task) blocks on the queue to wait for data to arrive, \r
+ * toggling an LED each time '100' is received. The other task (the queue send\r
+ * task) repeatedly blocks for a fixed period before sending '100' to the queue\r
+ * (causing the first task to toggle the LED). \r
+ *\r
+ * For a much more complete and complex example select either the Debug or\r
+ * Debug_with_optimisation build configurations within the HEW IDE. \r
+*/\r
+\r
+/* Hardware specific includes. */\r
+#include "iodefine.h"\r
+\r
+/* Kernel includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "queue.h"\r
+\r
+/* Priorities at which the tasks are created. */\r
+#define configQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )\r
+#define configQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+\r
+/* The rate at which data is sent to the queue, specified in milliseconds. */\r
+#define mainQUEUE_SEND_FREQUENCY_MS ( 500 / portTICK_RATE_MS )\r
+\r
+/* The number of items the queue can hold. This is 1 as the receive task\r
+will remove items as they are added so the send task should always find the\r
+queue empty. */\r
+#define mainQUEUE_LENGTH ( 1 )\r
+\r
+/*\r
+ * The tasks as defined at the top of this file.\r
+ */\r
+static void prvQueueReceiveTask( void *pvParameters );\r
+static void prvQueueSendTask( void *pvParameters );\r
+\r
+/* The queue used by both tasks. */\r
+static xQueueHandle xQueue = NULL;\r
+\r
+/* This variable is not used by this simple Blinky example. It is defined \r
+purely to allow the project to link as it is used by the full project. */\r
+volatile unsigned long ulHighFrequencyTickCount = 0UL;\r
+/*-----------------------------------------------------------*/\r
+\r
+void main(void)\r
+{\r
+extern void HardwareSetup( void );\r
+\r
+ /* Renesas provided CPU configuration routine. The clocks are configured in\r
+ here. */\r
+ HardwareSetup();\r
+ \r
+ /* Turn all LEDs off. */\r
+ vParTestInitialise();\r
+ \r
+ /* Create the queue. */\r
+ xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( unsigned long ) );\r
+\r
+ if( xQueue != NULL )\r
+ {\r
+ /* Start the two tasks as described at the top of this file. */\r
+ xTaskCreate( prvQueueReceiveTask, "Rx", configMINIMAL_STACK_SIZE, NULL, configQUEUE_RECEIVE_TASK_PRIORITY, NULL );\r
+ xTaskCreate( prvQueueSendTask, "TX", configMINIMAL_STACK_SIZE, NULL, configQUEUE_SEND_TASK_PRIORITY, NULL );\r
+\r
+ /* Start the tasks running. */\r
+ vTaskStartScheduler();\r
+ }\r
+ \r
+ /* If all is well we will never reach here as the scheduler will now be\r
+ running. If we do reach here then it is likely that there was insufficient\r
+ heap available for the idle task to be created. */\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvQueueSendTask( void *pvParameters )\r
+{\r
+portTickType xNextWakeTime;\r
+const unsigned long ulValueToSend = 100UL;\r
+\r
+ /* Initialise xNextWakeTime - this only needs to be done once. */\r
+ xNextWakeTime = xTaskGetTickCount();\r
+\r
+ for( ;; )\r
+ {\r
+ /* Place this task in the blocked state until it is time to run again. \r
+ The block state is specified in ticks, the constant used converts ticks\r
+ to ms. */\r
+ vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS );\r
+\r
+ /* Send to the queue - causing the queue receive task to flash its LED. 0\r
+ is used so the send does not block - it shouldn't need to as the queue\r
+ should always be empty here. */\r
+ xQueueSend( xQueue, &ulValueToSend, 0 );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvQueueReceiveTask( void *pvParameters )\r
+{\r
+unsigned long ulReceivedValue;\r
+\r
+ for( ;; )\r
+ {\r
+ /* Wait until something arives in the queue - this will block \r
+ indefinitely provided INCLUDE_vTaskSuspend is set to 1 in\r
+ FreeRTOSConfig.h. */\r
+ xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY );\r
+\r
+ /* To get here something must have arrived, but is it the expected\r
+ value? If it is, toggle the LED. */\r
+ if( ulReceivedValue == 100UL )\r
+ {\r
+ vParTestToggleLED( 0 );\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationSetupTimerInterrupt( void )\r
+{\r
+ /* Enable compare match timer 0. */\r
+ MSTP( CMT0 ) = 0;\r
+ \r
+ /* Interrupt on compare match. */\r
+ CMT0.CMCR.BIT.CMIE = 1;\r
+ \r
+ /* Set the compare match value. */\r
+ CMT0.CMCOR = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / configTICK_RATE_HZ ) -1 ) / 8 );\r
+ \r
+ /* Divide the PCLK by 8. */\r
+ CMT0.CMCR.BIT.CKS = 0;\r
+ \r
+ /* Enable the interrupt... */\r
+ _IEN( _CMT0_CMI0 ) = 1;\r
+ \r
+ /* ...and set its priority to the application defined kernel priority. */\r
+ _IPR( _CMT0_CMI0 ) = configKERNEL_INTERRUPT_PRIORITY;\r
+ \r
+ /* Start the timer. */\r
+ CMT.CMSTR0.BIT.STR0 = 1;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* This function is explained by the comments above its prototype at the top\r
+of this file. */\r
+void vApplicationMallocFailedHook( void )\r
+{\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* This function is explained by the comments above its prototype at the top\r
+of this file. */\r
+void vApplicationStackOverflowHook( xTaskHandle *pxTask, signed char *pcTaskName )\r
+{\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* This function is explained by the comments above its prototype at the top\r
+of this file. */\r
+void vApplicationIdleHook( void )\r
+{\r
+ /* Just to prevent the variable getting optimised away. */\r
+ ( void ) ulHighFrequencyTickCount;\r
+}\r
+/*-----------------------------------------------------------*/\r
--- /dev/null
+/*\r
+ FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd.\r
+ \r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ >>>NOTE<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ http://www.FreeRTOS.org - Documentation, latest information, license and\r
+ contact details.\r
+\r
+ http://www.SafeRTOS.com - A version that is certified for use in safety\r
+ critical systems.\r
+\r
+ http://www.OpenRTOS.com - Commercial support, development, porting,\r
+ licensing and training services.\r
+*/\r
+\r
+/* ****************************************************************************\r
+ * This project includes a lot of tasks and tests and is therefore complex.\r
+ * If you would prefer a much simpler project to get started with then select\r
+ * the 'Blinky' build configuration within the HEW IDE.\r
+ * ****************************************************************************\r
+ *\r
+ * Creates all the demo application tasks, then starts the scheduler. The web\r
+ * documentation provides more details of the standard demo application tasks,\r
+ * which provide no particular functionality but do provide a good example of\r
+ * how to use the FreeRTOS API. The tasks defined in flop.c are included in the\r
+ * set of standard demo tasks to ensure the floating point unit gets some\r
+ * exercise.\r
+ *\r
+ * In addition to the standard demo tasks, the following tasks and tests are\r
+ * defined and/or created within this file:\r
+ *\r
+ * "Reg test" tasks - These fill the registers with known values, then check\r
+ * that each register still contains its expected value. Each task uses\r
+ * different values. The tasks run with very low priority so get preempted\r
+ * very frequently. A check variable is incremented on each iteration of the\r
+ * test loop. A register containing an unexpected value is indicative of an\r
+ * error in the context switching mechanism and will result in a branch to a\r
+ * null loop - which in turn will prevent the check variable from incrementing\r
+ * any further and allow the check task (described below) to determine that an\r
+ * error has occurred. The nature of the reg test tasks necessitates that they\r
+ * are written in assembly code.\r
+ *\r
+ * "Check" task - This only executes every five seconds but has a high priority\r
+ * to ensure it gets processor time. Its main function is to check that all the\r
+ * standard demo tasks are still operational. While no errors have been\r
+ * discovered the check task will toggle LED 5 every 5 seconds - the toggle\r
+ * rate increasing to 200ms being a visual indication that at least one task has\r
+ * reported unexpected behaviour.\r
+ *\r
+ * "High frequency timer test" - A high frequency periodic interrupt is\r
+ * generated using a timer - the interrupt is assigned a priority above\r
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY so should not be effected by anything\r
+ * the kernel is doing. The frequency and priority of the interrupt, in\r
+ * combination with other standard tests executed in this demo, should result\r
+ * in interrupts nesting at least 3 and probably 4 deep. This test is only\r
+ * included in build configurations that have the optimiser switched on. In\r
+ * optimised builds the count of high frequency ticks is used as the time base\r
+ * for the run time stats.\r
+ *\r
+ * *NOTE 1* If LED3 is toggling every 5 seconds then all the demo application\r
+ * tasks are executing as expected and no errors have been reported in any\r
+ * tasks. The toggle rate increasing to 200ms indicates that at least one task\r
+ * has reported unexpected behaviour.\r
+ *\r
+ * *NOTE 2* vApplicationSetupTimerInterrupt() is called by the kernel to let\r
+ * the application set up a timer to generate the tick interrupt. In this\r
+ * example a compare match timer is used for this purpose.\r
+ *\r
+ * *NOTE 3* The CPU must be in Supervisor mode when the scheduler is started.\r
+ * The PowerON_Reset_PC() supplied in resetprg.c with this demo has\r
+ * Change_PSW_PM_to_UserMode() commented out to ensure this is the case.\r
+ *\r
+ * *NOTE 4* The IntQueue common demo tasks test interrupt nesting and make use\r
+ * of all the 8bit timers (as two cascaded 16bit units).\r
+*/\r
+\r
+/* Hardware specific includes. */\r
+#include "iodefine.h"\r
+\r
+/* Kernel includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Standard demo includes. */\r
+#include "partest.h"\r
+#include "flash.h"\r
+#include "IntQueue.h"\r
+#include "BlockQ.h"\r
+#include "death.h"\r
+#include "integer.h"\r
+#include "blocktim.h"\r
+#include "semtest.h"\r
+#include "PollQ.h"\r
+#include "GenQTest.h"\r
+#include "QPeek.h"\r
+#include "recmutex.h"\r
+#include "flop.h"\r
+\r
+/* Values that are passed into the reg test tasks using the task parameter. The\r
+tasks check that the values are passed in correctly. */\r
+#define mainREG_TEST_1_PARAMETER ( 0x12121212UL )\r
+#define mainREG_TEST_2_PARAMETER ( 0x12345678UL )\r
+\r
+/* Priorities at which the tasks are created. */\r
+#define mainCHECK_TASK_PRIORITY ( configMAX_PRIORITIES - 1 )\r
+#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 1 )\r
+#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 )\r
+#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 )\r
+#define mainFLASH_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )\r
+#define mainuIP_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+#define mainINTEGER_TASK_PRIORITY ( tskIDLE_PRIORITY )\r
+#define mainGEN_QUEUE_TASK_PRIORITY ( tskIDLE_PRIORITY )\r
+#define mainFLOP_TASK_PRIORITY ( tskIDLE_PRIORITY )\r
+\r
+/* The WEB server uses string handling functions, which in turn use a bit more\r
+stack than most of the other tasks. */\r
+#define mainuIP_STACK_SIZE ( configMINIMAL_STACK_SIZE * 3 )\r
+\r
+/* The LED toggled by the check task. */\r
+#define mainCHECK_LED ( 3 )\r
+\r
+/* The rate at which mainCHECK_LED will toggle when all the tasks are running\r
+without error. Controlled by the check task as described at the top of this\r
+file. */\r
+#define mainNO_ERROR_CYCLE_TIME ( 5000 / portTICK_RATE_MS )\r
+\r
+/* The rate at which mainCHECK_LED will toggle when an error has been reported\r
+by at least one task. Controlled by the check task as described at the top of\r
+this file. */\r
+#define mainERROR_CYCLE_TIME ( 200 / portTICK_RATE_MS )\r
+\r
+/*\r
+ * vApplicationMallocFailedHook() will only be called if\r
+ * configUSE_MALLOC_FAILED_HOOK is set to 1 in FreeRTOSConfig.h. It is a hook\r
+ * function that will execute if a call to pvPortMalloc() fails.\r
+ * pvPortMalloc() is called internally by the kernel whenever a task, queue or\r
+ * semaphore is created. It is also called by various parts of the demo\r
+ * application.\r
+ */\r
+void vApplicationMallocFailedHook( void );\r
+\r
+/*\r
+ * vApplicationIdleHook() will only be called if configUSE_IDLE_HOOK is set to 1\r
+ * in FreeRTOSConfig.h. It is a hook function that is called on each iteration\r
+ * of the idle task. It is essential that code added to this hook function\r
+ * never attempts to block in any way (for example, call xQueueReceive() with\r
+ * a block time specified). If the application makes use of the vTaskDelete()\r
+ * API function (as this demo application does) then it is also important that\r
+ * vApplicationIdleHook() is permitted to return to its calling function because\r
+ * it is the responsibility of the idle task to clean up memory allocated by the\r
+ * kernel to any task that has since been deleted.\r
+ */\r
+void vApplicationIdleHook( void );\r
+\r
+/*\r
+ * vApplicationStackOverflowHook() will only be called if\r
+ * configCHECK_FOR_STACK_OVERFLOW is set to a non-zero value. The handle and\r
+ * name of the offending task should be passed in the function parameters, but\r
+ * it is possible that the stack overflow will have corrupted these - in which\r
+ * case pxCurrentTCB can be inspected to find the same information.\r
+ */\r
+void vApplicationStackOverflowHook( xTaskHandle *pxTask, signed char *pcTaskName );\r
+\r
+/*\r
+ * The reg test tasks as described at the top of this file.\r
+ */\r
+static void prvRegTest1Task( void *pvParameters );\r
+static void prvRegTest2Task( void *pvParameters );\r
+\r
+/*\r
+ * The actual implementation of the reg test functionality, which, because of\r
+ * the direct register access, have to be in assembly.\r
+ */\r
+static void prvRegTest1Implementation( void );\r
+static void prvRegTest2Implementation( void );\r
+\r
+/*\r
+ * The check task as described at the top of this file.\r
+ */\r
+static void prvCheckTask( void *pvParameters );\r
+\r
+/*\r
+ * Contains the implementation of the WEB server.\r
+ */\r
+extern void vuIP_Task( void *pvParameters );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Variables that are incremented on each iteration of the reg test tasks -\r
+provided the tasks have not reported any errors. The check task inspects these\r
+variables to ensure they are still incrementing as expected. If a variable\r
+stops incrementing then it is likely that its associate task has stalled. */\r
+unsigned long ulRegTest1CycleCount = 0UL, ulRegTest2CycleCount = 0UL;\r
+\r
+/* The status message that is displayed at the bottom of the "task stats" web\r
+page, which is served by the uIP task. This will report any errors picked up\r
+by the reg test task. */\r
+const char *pcStatusMessage = "All tasks executing without error.";\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void main(void)\r
+{\r
+extern void HardwareSetup( void );\r
+\r
+ /* Renesas provided CPU configuration routine. The clocks are configured in\r
+ here. */\r
+ HardwareSetup();\r
+\r
+ /* Turn all LEDs off. */\r
+ vParTestInitialise();\r
+\r
+ /* Start the reg test tasks which test the context switching mechanism. */\r
+ xTaskCreate( prvRegTest1Task, "RegTst1", configMINIMAL_STACK_SIZE, ( void * ) mainREG_TEST_1_PARAMETER, tskIDLE_PRIORITY, NULL );\r
+ xTaskCreate( prvRegTest2Task, "RegTst2", configMINIMAL_STACK_SIZE, ( void * ) mainREG_TEST_2_PARAMETER, tskIDLE_PRIORITY, NULL );\r
+\r
+ /* Start the check task as described at the top of this file. */\r
+ xTaskCreate( prvCheckTask, "Check", configMINIMAL_STACK_SIZE * 3, NULL, mainCHECK_TASK_PRIORITY, NULL );\r
+\r
+ /* Create the standard demo tasks. */\r
+ vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );\r
+ vCreateBlockTimeTasks();\r
+ vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );\r
+ vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );\r
+ vStartIntegerMathTasks( mainINTEGER_TASK_PRIORITY );\r
+ vStartGenericQueueTasks( mainGEN_QUEUE_TASK_PRIORITY );\r
+ vStartLEDFlashTasks( mainFLASH_TASK_PRIORITY );\r
+ vStartQueuePeekTasks();\r
+ vStartRecursiveMutexTasks();\r
+ vStartInterruptQueueTasks();\r
+ vStartMathTasks( mainFLOP_TASK_PRIORITY );\r
+\r
+ /* The suicide tasks must be created last as they need to know how many\r
+ tasks were running prior to their creation in order to ascertain whether\r
+ or not the correct/expected number of tasks are running at any given time. */\r
+ vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY );\r
+\r
+ /* Start the tasks running. */\r
+ vTaskStartScheduler();\r
+\r
+ /* If all is well we will never reach here as the scheduler will now be\r
+ running. If we do reach here then it is likely that there was insufficient\r
+ heap available for the idle task to be created. */\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvCheckTask( void *pvParameters )\r
+{\r
+static volatile unsigned long ulLastRegTest1CycleCount = 0UL, ulLastRegTest2CycleCount = 0UL;\r
+portTickType xNextWakeTime, xCycleFrequency = mainNO_ERROR_CYCLE_TIME;\r
+extern void vSetupHighFrequencyTimer( void );\r
+\r
+ /* If this is being executed then the kernel has been started. Start the high\r
+ frequency timer test as described at the top of this file. This is only\r
+ included in the optimised build configuration - otherwise it takes up too much\r
+ CPU time and can disrupt other tests. */\r
+ #ifdef INCLUDE_HIGH_FREQUENCY_TIMER_TEST\r
+ vSetupHighFrequencyTimer();\r
+ #endif\r
+\r
+ /* Initialise xNextWakeTime - this only needs to be done once. */\r
+ xNextWakeTime = xTaskGetTickCount();\r
+\r
+ for( ;; )\r
+ {\r
+ /* Place this task in the blocked state until it is time to run again. */\r
+ vTaskDelayUntil( &xNextWakeTime, xCycleFrequency );\r
+\r
+ /* Check the standard demo tasks are running without error. */\r
+ if( xAreGenericQueueTasksStillRunning() != pdTRUE )\r
+ {\r
+ /* Increase the rate at which this task cycles, which will increase the\r
+ rate at which mainCHECK_LED flashes to give visual feedback that an error\r
+ has occurred. */\r
+ xCycleFrequency = mainERROR_CYCLE_TIME;\r
+ pcStatusMessage = "Error: GenQueue";\r
+ }\r
+ else if( xAreQueuePeekTasksStillRunning() != pdTRUE )\r
+ {\r
+ xCycleFrequency = mainERROR_CYCLE_TIME;\r
+ pcStatusMessage = "Error: QueuePeek";\r
+ }\r
+ else if( xAreBlockingQueuesStillRunning() != pdTRUE )\r
+ {\r
+ xCycleFrequency = mainERROR_CYCLE_TIME;\r
+ pcStatusMessage = "Error: BlockQueue";\r
+ }\r
+ else if( xAreBlockTimeTestTasksStillRunning() != pdTRUE )\r
+ {\r
+ xCycleFrequency = mainERROR_CYCLE_TIME;\r
+ pcStatusMessage = "Error: BlockTime";\r
+ }\r
+ else if( xAreSemaphoreTasksStillRunning() != pdTRUE )\r
+ {\r
+ xCycleFrequency = mainERROR_CYCLE_TIME;\r
+ pcStatusMessage = "Error: SemTest";\r
+ }\r
+ else if( xArePollingQueuesStillRunning() != pdTRUE )\r
+ {\r
+ xCycleFrequency = mainERROR_CYCLE_TIME;\r
+ pcStatusMessage = "Error: PollQueue";\r
+ }\r
+ else if( xIsCreateTaskStillRunning() != pdTRUE )\r
+ {\r
+ xCycleFrequency = mainERROR_CYCLE_TIME;\r
+ pcStatusMessage = "Error: Death";\r
+ }\r
+ else if( xAreIntegerMathsTaskStillRunning() != pdTRUE )\r
+ {\r
+ xCycleFrequency = mainERROR_CYCLE_TIME;\r
+ pcStatusMessage = "Error: IntMath";\r
+ }\r
+ else if( xAreRecursiveMutexTasksStillRunning() != pdTRUE )\r
+ {\r
+ xCycleFrequency = mainERROR_CYCLE_TIME;\r
+ pcStatusMessage = "Error: RecMutex";\r
+ }\r
+ else if( xAreIntQueueTasksStillRunning() != pdPASS )\r
+ {\r
+ xCycleFrequency = mainERROR_CYCLE_TIME;\r
+ pcStatusMessage = "Error: IntQueue";\r
+ }\r
+ else if( xAreMathsTaskStillRunning() != pdPASS )\r
+ {\r
+ xCycleFrequency = mainERROR_CYCLE_TIME;\r
+ pcStatusMessage = "Error: Flop";\r
+ }\r
+\r
+ /* Check the reg test tasks are still cycling. They will stop incrementing\r
+ their loop counters if they encounter an error. */\r
+ if( ulRegTest1CycleCount == ulLastRegTest1CycleCount )\r
+ {\r
+ xCycleFrequency = mainERROR_CYCLE_TIME;\r
+ pcStatusMessage = "Error: RegTest1";\r
+ }\r
+\r
+ if( ulRegTest2CycleCount == ulLastRegTest2CycleCount )\r
+ {\r
+ xCycleFrequency = mainERROR_CYCLE_TIME;\r
+ pcStatusMessage = "Error: RegTest2";\r
+ }\r
+\r
+ ulLastRegTest1CycleCount = ulRegTest1CycleCount;\r
+ ulLastRegTest2CycleCount = ulRegTest2CycleCount;\r
+\r
+ /* Toggle the check LED to give an indication of the system status. If\r
+ the LED toggles every 5 seconds then everything is ok. A faster toggle\r
+ indicates an error. */\r
+ vParTestToggleLED( mainCHECK_LED );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The RX port uses this callback function to configure its tick interrupt.\r
+This allows the application to choose the tick interrupt source. */\r
+void vApplicationSetupTimerInterrupt( void )\r
+{\r
+ /* Enable compare match timer 0. */\r
+ MSTP( CMT0 ) = 0;\r
+\r
+ /* Interrupt on compare match. */\r
+ CMT0.CMCR.BIT.CMIE = 1;\r
+\r
+ /* Set the compare match value. */\r
+ CMT0.CMCOR = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / configTICK_RATE_HZ ) -1 ) / 8 );\r
+\r
+ /* Divide the PCLK by 8. */\r
+ CMT0.CMCR.BIT.CKS = 0;\r
+\r
+ /* Enable the interrupt... */\r
+ _IEN( _CMT0_CMI0 ) = 1;\r
+\r
+ /* ...and set its priority to the application defined kernel priority. */\r
+ _IPR( _CMT0_CMI0 ) = configKERNEL_INTERRUPT_PRIORITY;\r
+\r
+ /* Start the timer. */\r
+ CMT.CMSTR0.BIT.STR0 = 1;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* This function is explained by the comments above its prototype at the top\r
+of this file. */\r
+void vApplicationMallocFailedHook( void )\r
+{\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* This function is explained by the comments above its prototype at the top\r
+of this file. */\r
+void vApplicationStackOverflowHook( xTaskHandle *pxTask, signed char *pcTaskName )\r
+{\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* This function is explained by the comments above its prototype at the top\r
+of this file. */\r
+void vApplicationIdleHook( void )\r
+{\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* This function is explained in the comments at the top of this file. */\r
+static void prvRegTest1Task( void *pvParameters )\r
+{\r
+ if( ( ( unsigned long ) pvParameters ) != mainREG_TEST_1_PARAMETER )\r
+ {\r
+ /* The parameter did not contain the expected value. */\r
+ for( ;; )\r
+ {\r
+ /* Stop the tick interrupt so its obvious something has gone wrong. */\r
+ taskDISABLE_INTERRUPTS();\r
+ }\r
+ }\r
+\r
+ /* This is an inline asm function that never returns. */\r
+ prvRegTest1Implementation();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* This function is explained in the comments at the top of this file. */\r
+static void prvRegTest2Task( void *pvParameters )\r
+{\r
+ if( ( ( unsigned long ) pvParameters ) != mainREG_TEST_2_PARAMETER )\r
+ {\r
+ /* The parameter did not contain the expected value. */\r
+ for( ;; )\r
+ {\r
+ /* Stop the tick interrupt so its obvious something has gone wrong. */\r
+ taskDISABLE_INTERRUPTS();\r
+ }\r
+ }\r
+\r
+ /* This is an inline asm function that never returns. */\r
+ prvRegTest2Implementation();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* This function is explained in the comments at the top of this file. */\r
+#pragma inline_asm prvRegTest1Implementation\r
+static void prvRegTest1Implementation( void )\r
+{\r
+ ; Put a known value in each register.\r
+ MOV.L #1, R1\r
+ MOV.L #2, R2\r
+ MOV.L #3, R3\r
+ MOV.L #4, R4\r
+ MOV.L #5, R5\r
+ MOV.L #6, R6\r
+ MOV.L #7, R7\r
+ MOV.L #8, R8\r
+ MOV.L #9, R9\r
+ MOV.L #10, R10\r
+ MOV.L #11, R11\r
+ MOV.L #12, R12\r
+ MOV.L #13, R13\r
+ MOV.L #14, R14\r
+ MOV.L #15, R15\r
+\r
+ ; Loop, checking each itteration that each register still contains the\r
+ ; expected value.\r
+TestLoop1:\r
+\r
+ ; Push the registers that are going to get clobbered.\r
+ PUSHM R14-R15\r
+\r
+ ; Increment the loop counter to show this task is still getting CPU time.\r
+ MOV.L #_ulRegTest1CycleCount, R14\r
+ MOV.L [ R14 ], R15\r
+ ADD #1, R15\r
+ MOV.L R15, [ R14 ]\r
+\r
+ ; Yield to extend the text coverage. Set the bit in the ITU SWINTR register.\r
+ MOV.L #1, R14\r
+ MOV.L #0872E0H, R15\r
+ MOV.B R14, [R15]\r
+ NOP\r
+ NOP\r
+\r
+ ; Restore the clobbered registers.\r
+ POPM R14-R15\r
+\r
+ ; Now compare each register to ensure it still contains the value that was\r
+ ; set before this loop was entered.\r
+ CMP #1, R1\r
+ BNE RegTest1Error\r
+ CMP #2, R2\r
+ BNE RegTest1Error\r
+ CMP #3, R3\r
+ BNE RegTest1Error\r
+ CMP #4, R4\r
+ BNE RegTest1Error\r
+ CMP #5, R5\r
+ BNE RegTest1Error\r
+ CMP #6, R6\r
+ BNE RegTest1Error\r
+ CMP #7, R7\r
+ BNE RegTest1Error\r
+ CMP #8, R8\r
+ BNE RegTest1Error\r
+ CMP #9, R9\r
+ BNE RegTest1Error\r
+ CMP #10, R10\r
+ BNE RegTest1Error\r
+ CMP #11, R11\r
+ BNE RegTest1Error\r
+ CMP #12, R12\r
+ BNE RegTest1Error\r
+ CMP #13, R13\r
+ BNE RegTest1Error\r
+ CMP #14, R14\r
+ BNE RegTest1Error\r
+ CMP #15, R15\r
+ BNE RegTest1Error\r
+\r
+ ; All comparisons passed, start a new itteratio of this loop.\r
+ BRA TestLoop1\r
+\r
+RegTest1Error:\r
+ ; A compare failed, just loop here so the loop counter stops incrementing\r
+ ; causing the check task to indicate the error.\r
+ BRA RegTest1Error\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* This function is explained in the comments at the top of this file. */\r
+#pragma inline_asm prvRegTest2Implementation\r
+static void prvRegTest2Implementation( void )\r
+{\r
+ ; Put a known value in each register.\r
+ MOV.L #10, R1\r
+ MOV.L #20, R2\r
+ MOV.L #30, R3\r
+ MOV.L #40, R4\r
+ MOV.L #50, R5\r
+ MOV.L #60, R6\r
+ MOV.L #70, R7\r
+ MOV.L #80, R8\r
+ MOV.L #90, R9\r
+ MOV.L #100, R10\r
+ MOV.L #110, R11\r
+ MOV.L #120, R12\r
+ MOV.L #130, R13\r
+ MOV.L #140, R14\r
+ MOV.L #150, R15\r
+\r
+ ; Loop, checking on each itteration that each register still contains the\r
+ ; expected value.\r
+TestLoop2:\r
+\r
+ ; Push the registers that are going to get clobbered.\r
+ PUSHM R14-R15\r
+\r
+ ; Increment the loop counter to show this task is still getting CPU time.\r
+ MOV.L #_ulRegTest2CycleCount, R14\r
+ MOV.L [ R14 ], R15\r
+ ADD #1, R15\r
+ MOV.L R15, [ R14 ]\r
+\r
+ ; Restore the clobbered registers.\r
+ POPM R14-R15\r
+\r
+ CMP #10, R1\r
+ BNE RegTest2Error\r
+ CMP #20, R2\r
+ BNE RegTest2Error\r
+ CMP #30, R3\r
+ BNE RegTest2Error\r
+ CMP #40, R4\r
+ BNE RegTest2Error\r
+ CMP #50, R5\r
+ BNE RegTest2Error\r
+ CMP #60, R6\r
+ BNE RegTest2Error\r
+ CMP #70, R7\r
+ BNE RegTest2Error\r
+ CMP #80, R8\r
+ BNE RegTest2Error\r
+ CMP #90, R9\r
+ BNE RegTest2Error\r
+ CMP #100, R10\r
+ BNE RegTest2Error\r
+ CMP #110, R11\r
+ BNE RegTest2Error\r
+ CMP #120, R12\r
+ BNE RegTest2Error\r
+ CMP #130, R13\r
+ BNE RegTest2Error\r
+ CMP #140, R14\r
+ BNE RegTest2Error\r
+ CMP #150, R15\r
+ BNE RegTest2Error\r
+\r
+ ; All comparisons passed, start a new itteratio of this loop.\r
+ BRA TestLoop2\r
+\r
+RegTest2Error:\r
+ ; A compare failed, just loop here so the loop counter stops incrementing\r
+ ; - causing the check task to indicate the error.\r
+ BRA RegTest2Error\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+char *pcGetTaskStatusMessage( void )\r
+{\r
+ /* Not bothered about a critical section here although technically because of\r
+ the task priorities the pointer could change it will be atomic if not near\r
+ atomic and its not critical. */\r
+ return ( char * ) pcStatusMessage;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd.\r
+ \r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ >>>NOTE<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ http://www.FreeRTOS.org - Documentation, latest information, license and\r
+ contact details.\r
+\r
+ http://www.SafeRTOS.com - A version that is certified for use in safety\r
+ critical systems.\r
+\r
+ http://www.OpenRTOS.com - Commercial support, development, porting,\r
+ licensing and training services.\r
+*/\r
+\r
+/* Standard includes. */\r
+#include <string.h>\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "timers.h"\r
+#include "queue.h"\r
+\r
+/* uip includes. */\r
+#include "net/uip.h"\r
+#include "net/uip_arp.h"\r
+#include "apps/httpd/httpd.h"\r
+#include "sys/timer.h"\r
+#include "net/clock-arch.h"\r
+#include "r_ether.h"\r
+\r
+/* Demo includes. */\r
+#include "ParTest.h"\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* How long to wait before attempting to connect the MAC again. */\r
+#define uipINIT_WAIT ( 100 / portTICK_RATE_MS )\r
+\r
+/* Shortcut to the header within the Rx buffer. */\r
+#define xHeader ((struct uip_eth_hdr *) &uip_buf[ 0 ])\r
+\r
+/* Standard constant. */\r
+#define uipTOTAL_FRAME_HEADER_SIZE 54\r
+\r
+/* The ARP timer and the periodic timer share a callback function, so the\r
+respective timer IDs are used to determine which timer actually expired. These\r
+constants are assigned to the timer IDs. */\r
+#define uipARP_TIMER 0\r
+#define uipPERIODIC_TIMER 1\r
+\r
+/* A block time of zero ticks simply means, "don't block". */\r
+#define uipDONT_BLOCK 0UL\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Setup the MAC address in the MAC itself, and in the uIP stack.\r
+ */\r
+static void prvSetMACAddress( void );\r
+\r
+/*\r
+ * Perform any uIP initialisation necessary. \r
+ */\r
+static void prvInitialise_uIP( void );\r
+\r
+/*\r
+ * The callback function that is assigned to both the periodic timer and the\r
+ * ARP timer.\r
+ */\r
+static void prvUIPTimerCallback( xTimerHandle xTimer );\r
+\r
+/*\r
+ * Port functions required by the uIP stack.\r
+ */\r
+clock_time_t clock_time( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The queue used to send TCP/IP events to the uIP stack. */\r
+xQueueHandle xEMACEventQueue = NULL;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+clock_time_t clock_time( void )\r
+{\r
+ return xTaskGetTickCount();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vuIP_Task( void *pvParameters )\r
+{\r
+portBASE_TYPE i;\r
+unsigned long ulNewEvent = 0UL;\r
+unsigned long ulUIP_Events = 0UL;\r
+\r
+ ( void ) pvParameters;\r
+ \r
+ /* Initialise the uIP stack. */\r
+ prvInitialise_uIP();\r
+\r
+ /* Initialise the MAC. */\r
+ vInitEmac();\r
+\r
+ while( lEMACWaitForLink() != pdPASS )\r
+ {\r
+ vTaskDelay( uipINIT_WAIT );\r
+ }\r
+\r
+ for( ;; )\r
+ {\r
+ if( ( ulUIP_Events & uipETHERNET_RX_EVENT ) != 0UL )\r
+ { \r
+ /* Is there received data ready to be processed? */\r
+ uip_len = ( unsigned short ) ulEMACRead();\r
+ \r
+ if( ( uip_len > 0 ) && ( uip_buf != NULL ) )\r
+ {\r
+ /* Standard uIP loop taken from the uIP manual. */\r
+ if( xHeader->type == htons( UIP_ETHTYPE_IP ) )\r
+ {\r
+ uip_arp_ipin();\r
+ uip_input();\r
+\r
+ /* If the above function invocation resulted in data that\r
+ should be sent out on the network, the global variable\r
+ uip_len is set to a value > 0. */\r
+ if( uip_len > 0 )\r
+ {\r
+ uip_arp_out();\r
+ vEMACWrite();\r
+ }\r
+ }\r
+ else if( xHeader->type == htons( UIP_ETHTYPE_ARP ) )\r
+ {\r
+ uip_arp_arpin();\r
+\r
+ /* If the above function invocation resulted in data that\r
+ should be sent out on the network, the global variable\r
+ uip_len is set to a value > 0. */\r
+ if( uip_len > 0 )\r
+ {\r
+ vEMACWrite();\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ ulUIP_Events &= ~uipETHERNET_RX_EVENT;\r
+ }\r
+ }\r
+ \r
+ if( ( ulUIP_Events & uipPERIODIC_TIMER_EVENT ) != 0UL )\r
+ {\r
+ ulUIP_Events &= ~uipPERIODIC_TIMER_EVENT;\r
+ \r
+ for( i = 0; i < UIP_CONNS; i++ )\r
+ {\r
+ uip_periodic( i );\r
+\r
+ /* If the above function invocation resulted in data that\r
+ should be sent out on the network, the global variable\r
+ uip_len is set to a value > 0. */\r
+ if( uip_len > 0 )\r
+ {\r
+ uip_arp_out();\r
+ vEMACWrite();\r
+ }\r
+ }\r
+ }\r
+ \r
+ /* Call the ARP timer function every 10 seconds. */\r
+ if( ( ulUIP_Events & uipARP_TIMER_EVENT ) != 0 )\r
+ {\r
+ ulUIP_Events &= ~uipARP_TIMER_EVENT;\r
+ uip_arp_timer();\r
+ }\r
+ \r
+ if( ulUIP_Events == pdFALSE )\r
+ {\r
+ xQueueReceive( xEMACEventQueue, &ulNewEvent, portMAX_DELAY );\r
+ ulUIP_Events |= ulNewEvent;\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvInitialise_uIP( void )\r
+{\r
+xTimerHandle xARPTimer, xPeriodicTimer;\r
+uip_ipaddr_t xIPAddr;\r
+const unsigned long ul_uIPEventQueueLength = 10UL;\r
+\r
+ /* Initialise the uIP stack. */\r
+ uip_init();\r
+ uip_ipaddr( &xIPAddr, configIP_ADDR0, configIP_ADDR1, configIP_ADDR2, configIP_ADDR3 );\r
+ uip_sethostaddr( &xIPAddr );\r
+ uip_ipaddr( &xIPAddr, configNET_MASK0, configNET_MASK1, configNET_MASK2, configNET_MASK3 );\r
+ uip_setnetmask( &xIPAddr );\r
+ prvSetMACAddress();\r
+ httpd_init();\r
+\r
+ /* Create the queue used to sent TCP/IP events to the uIP stack. */\r
+ xEMACEventQueue = xQueueCreate( ul_uIPEventQueueLength, sizeof( unsigned long ) );\r
+\r
+ /* Create and start the uIP timers. */\r
+ xARPTimer = xTimerCreate( ( const signed char * const ) "ARPTimer", /* Just a name that is helpful for debugging, not used by the kernel. */\r
+ ( 10000UL / portTICK_RATE_MS ), /* Timer period. */\r
+ pdTRUE, /* Autor-reload. */\r
+ ( void * ) uipARP_TIMER,\r
+ prvUIPTimerCallback\r
+ );\r
+\r
+ xPeriodicTimer = xTimerCreate( ( const signed char * const ) "PeriodicTimer",\r
+ ( 500 / portTICK_RATE_MS ),\r
+ pdTRUE, /* Autor-reload. */\r
+ ( void * ) uipPERIODIC_TIMER,\r
+ prvUIPTimerCallback\r
+ );\r
+\r
+ configASSERT( xARPTimer );\r
+ configASSERT( xPeriodicTimer );\r
+\r
+ xTimerStart( xARPTimer, portMAX_DELAY );\r
+ xTimerStart( xPeriodicTimer, portMAX_DELAY );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvUIPTimerCallback( xTimerHandle xTimer )\r
+{\r
+static const unsigned long ulARPTimerExpired = uipARP_TIMER_EVENT;\r
+static const unsigned long ulPeriodicTimerExpired = uipPERIODIC_TIMER_EVENT;\r
+\r
+ /* This is a time callback, so calls to xQueueSend() must not attempt to\r
+ block. */\r
+ switch( ( int ) pvTimerGetTimerID( xTimer ) )\r
+ {\r
+ case uipARP_TIMER : xQueueSend( xEMACEventQueue, &ulARPTimerExpired, uipDONT_BLOCK );\r
+ break;\r
+\r
+ case uipPERIODIC_TIMER : xQueueSend( xEMACEventQueue, &ulPeriodicTimerExpired, uipDONT_BLOCK );\r
+ break;\r
+\r
+ default : /* Should not get here. */\r
+ break;\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSetMACAddress( void )\r
+{\r
+struct uip_eth_addr xAddr;\r
+\r
+ /* Configure the MAC address in the uIP stack. */\r
+ xAddr.addr[ 0 ] = configMAC_ADDR0;\r
+ xAddr.addr[ 1 ] = configMAC_ADDR1;\r
+ xAddr.addr[ 2 ] = configMAC_ADDR2;\r
+ xAddr.addr[ 3 ] = configMAC_ADDR3;\r
+ xAddr.addr[ 4 ] = configMAC_ADDR4;\r
+ xAddr.addr[ 5 ] = configMAC_ADDR5;\r
+ uip_setethaddr( xAddr );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationProcessFormInput( char *pcInputString )\r
+{\r
+char *c;\r
+\r
+ /* Only interested in processing form input if this is the IO page. */\r
+ c = strstr( pcInputString, "io.shtml" );\r
+ \r
+ if( c )\r
+ {\r
+ /* Is there a command in the string? */\r
+ c = strstr( pcInputString, "?" );\r
+ if( c )\r
+ {\r
+ /* Turn the LED's on or off in accordance with the check box status. */\r
+ if( strstr( c, "LED0=1" ) != NULL )\r
+ {\r
+ /* Turn the LEDs on. */\r
+ vParTestSetLED( 7, 1 );\r
+ vParTestSetLED( 8, 1 );\r
+ vParTestSetLED( 9, 1 );\r
+ vParTestSetLED( 10, 1 );\r
+ }\r
+ else\r
+ {\r
+ /* Turn the LEDs off. */\r
+ vParTestSetLED( 7, 0 );\r
+ vParTestSetLED( 8, 0 );\r
+ vParTestSetLED( 9, 0 );\r
+ vParTestSetLED( 10, 0 );\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Commands to turn LEDs off are not always explicit. */\r
+ vParTestSetLED( 7, 0 );\r
+ vParTestSetLED( 8, 0 );\r
+ vParTestSetLED( 9, 0 );\r
+ vParTestSetLED( 10, 0 );\r
+ }\r
+ }\r
+}\r
+\r
projects / freertos / commitdiff