uint64_t ullNextTime = 0ULL;\r
const uint64_t *pullNextTime = &ullNextTime;\r
const size_t uxTimerIncrementsForOneTick = ( size_t ) ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ); /* Assumes increment won't go over 32-bits. */\r
-volatile uint64_t * const pullMachineTimerCompareRegister = ( volatile uint64_t * const ) ( configCLINT_BASE_ADDRESS + 0x4000 );\r
+volatile uint64_t * const pullMachineTimerCompareRegisterBase = ( volatile uint64_t * const ) ( configCLINT_BASE_ADDRESS + 0x4000 );\r
+volatile uint64_t * pullMachineTimerCompareRegister = 0;\r
\r
/* Set configCHECK_FOR_STACK_OVERFLOW to 3 to add ISR stack checking to task\r
stack checking. A problem in the ISR stack will trigger an assert, not call the\r
uint32_t ulCurrentTimeHigh, ulCurrentTimeLow;\r
volatile uint32_t * const pulTimeHigh = ( volatile uint32_t * const ) ( configCLINT_BASE_ADDRESS + 0xBFFC );\r
volatile uint32_t * const pulTimeLow = ( volatile uint32_t * const ) ( configCLINT_BASE_ADDRESS + 0xBFF8 );\r
+ volatile uint32_t ulHartId = 0;\r
+\r
+ __asm volatile( "csrr %0, mhartid" : "=r"( ulHartId ) );\r
+ pullMachineTimerCompareRegister = &( pullMachineTimerCompareRegisterBase[ ulHartId ] );\r
\r
do\r
{\r
.extern pxCurrentTCB\r
.extern ulPortTrapHandler\r
.extern vTaskSwitchContext\r
+.extern xTaskIncrementTick\r
.extern Timer_IRQHandler\r
.extern pullMachineTimerCompareRegister\r
.extern pullNextTime\r
.extern uxTimerIncrementsForOneTick /* size_t type so 32-bit on 32-bit core and 64-bits on 64-bit core. */\r
.extern xISRStackTop\r
+.extern portasmHANDLE_INTERRUPT\r
\r
/*-----------------------------------------------------------*/\r
\r
#if( __riscv_xlen == 32 )\r
\r
/* Update the 64-bit mtimer compare match value in two 32-bit writes. */\r
+ li t4, -1\r
lw t2, 0(t1) /* Load the low word of ullNextTime into t2. */\r
lw t3, 4(t1) /* Load the high word of ullNextTime into t3. */\r
+ sw t4, 0(t0) /* Low word no smaller than old value. */\r
+ sw t3, 4(t0) /* Store high word of ullNextTime into compare register. No smaller than new value. */\r
sw t2, 0(t0) /* Store low word of ullNextTime into compare register. */\r
- sw t3, 4(t0) /* Store high word of ullNextTime into compare register. */\r
lw t0, uxTimerIncrementsForOneTick /* Load the value of ullTimerIncrementForOneTick into t0 (could this be optimized by storing in an array next to pullNextTime?). */\r
add t4, t0, t2 /* Add the low word of ullNextTime to the timer increments for one tick (assumes timer increment for one tick fits in 32-bits). */\r
sltu t5, t4, t2 /* See if the sum of low words overflowed (what about the zero case?). */\r
+++ /dev/null
-/*\r
- * FreeRTOS Kernel V10.2.1\r
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
- *\r
- * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
- * this software and associated documentation files (the "Software"), to deal in\r
- * the Software without restriction, including without limitation the rights to\r
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
- * the Software, and t\r
-\r
- o permit persons to whom the Software is furnished to do so,\r
- * subject to the following conditions:\r
- *\r
- * The above copyright notice and this permission notice shall be included in all\r
- * copies or substantial portions of the Software.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
- *\r
- * http://www.FreeRTOS.org\r
- * http://aws.amazon.com/freertos\r
- *\r
- * 1 tab == 4 spaces!\r
- */\r
-\r
-/*\r
- * The FreeRTOS kernel's RISC-V port is split between the the code that is\r
- * common across all currently supported RISC-V chips (implementations of the\r
- * RISC-V ISA), and code that tailors the port to a specific RISC-V chip:\r
- *\r
- * + FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S contains the code that\r
- * is common to all currently supported RISC-V chips. There is only one\r
- * portASM.S file because the same file is built for all RISC-V target chips.\r
- *\r
- * + Header files called freertos_risc_v_chip_specific_extensions.h contain the\r
- * code that tailors the FreeRTOS kernel's RISC-V port to a specific RISC-V\r
- * chip. There are multiple freertos_risc_v_chip_specific_extensions.h files\r
- * as there are multiple RISC-V chip implementations.\r
- *\r
- * !!!NOTE!!!\r
- * TAKE CARE TO INCLUDE THE CORRECT freertos_risc_v_chip_specific_extensions.h\r
- * HEADER FILE FOR THE CHIP IN USE. This is done using the assembler's (not the\r
- * compiler's!) include path. For example, if the chip in use includes a core\r
- * local interrupter (CLINT) and does not include any chip specific register\r
- * extensions then add the path below to the assembler's include path:\r
- * FreeRTOS\Source\portable\GCC\RISC-V-RV32\chip_specific_extensions\RV32I_CLINT_no_extensions\r
- *\r
- */\r
-\r
-/*\r
- * This freertos_risc_v_chip_specific_extensions.h is for use with Pulpino Ri5cy\r
- * devices, developed and tested using the Vega board RV32M1RM.\r
- */\r
-\r
-#ifndef __FREERTOS_RISC_V_EXTENSIONS_H__\r
-#define __FREERTOS_RISC_V_EXTENSIONS_H__\r
-\r
-#define portasmHAS_CLINT 0\r
-\r
-/* Constants to define the additional registers found on the Pulpino RI5KY. */\r
-#define lpstart0 0x7b0\r
-#define lpend0 0x7b1\r
-#define lpcount0 0x7b2\r
-#define lpstart1 0x7b4\r
-#define lpend1 0x7b5\r
-#define lpcount1 0x7b6\r
-\r
-/* Six additional registers to save and restore, as per the #defines above. */\r
-#define portasmADDITIONAL_CONTEXT_SIZE 6 /* Must be even number on 32-bit cores. */\r
-\r
-/* Save additional registers found on the Pulpino. */\r
-.macro portasmSAVE_ADDITIONAL_REGISTERS\r
- addi sp, sp, -(portasmADDITIONAL_CONTEXT_SIZE * portWORD_SIZE) /* Make room for the additional registers. */\r
- csrr t0, lpstart0 /* Load additional registers into accessible temporary registers. */\r
- csrr t1, lpend0\r
- csrr t2, lpcount0\r
- csrr t3, lpstart1\r
- csrr t4, lpend1\r
- csrr t5, lpcount1\r
- sw t0, 1 * portWORD_SIZE( sp )\r
- sw t1, 2 * portWORD_SIZE( sp )\r
- sw t2, 3 * portWORD_SIZE( sp )\r
- sw t3, 4 * portWORD_SIZE( sp )\r
- sw t4, 5 * portWORD_SIZE( sp )\r
- sw t5, 6 * portWORD_SIZE( sp )\r
- .endm\r
-\r
-/* Restore the additional registers found on the Pulpino. */\r
-.macro portasmRESTORE_ADDITIONAL_REGISTERS\r
- lw t0, 1 * portWORD_SIZE( sp ) /* Load additional registers into accessible temporary registers. */\r
- lw t1, 2 * portWORD_SIZE( sp )\r
- lw t2, 3 * portWORD_SIZE( sp )\r
- lw t3, 4 * portWORD_SIZE( sp )\r
- lw t4, 5 * portWORD_SIZE( sp )\r
- lw t5, 6 * portWORD_SIZE( sp )\r
- csrw lpstart0, t0\r
- csrw lpend0, t1\r
- csrw lpcount0, t2\r
- csrw lpstart1, t3\r
- csrw lpend1, t4\r
- csrw lpcount1, t5\r
- addi sp, sp, (portasmADDITIONAL_CONTEXT_SIZE * portWORD_SIZE )/* Remove space added for additional registers. */\r
- .endm\r
-\r
-#endif /* __FREERTOS_RISC_V_EXTENSIONS_H__ */\r
interrupt stack after the scheduler has started. */\r
#ifdef configISR_STACK_SIZE_WORDS\r
static __attribute__ ((aligned(16))) StackType_t xISRStack[ configISR_STACK_SIZE_WORDS ] = { 0 };\r
- StackType_t xISRStackTop = ( StackType_t ) 0;\r
+ const StackType_t xISRStackTop = ( StackType_t ) &( xISRStack[ configISR_STACK_SIZE_WORDS & ~portBYTE_ALIGNMENT_MASK ] );\r
#else\r
extern const uint32_t __freertos_irq_stack_top[];\r
const StackType_t xISRStackTop = ( StackType_t ) __freertos_irq_stack_top;\r
uint64_t ullNextTime = 0ULL;\r
const uint64_t *pullNextTime = &ullNextTime;\r
const size_t uxTimerIncrementsForOneTick = ( size_t ) ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ); /* Assumes increment won't go over 32-bits. */\r
-volatile uint64_t * const pullMachineTimerCompareRegister = ( uint64_t * ) ( configCLINT_BASE_ADDRESS + 0x4000 );\r
+volatile uint64_t * const pullMachineTimerCompareRegisterBase = ( uint64_t * ) ( configCLINT_BASE_ADDRESS + 0x4000 );\r
+volatile uint64_t * pullMachineTimerCompareRegister = 0;\r
\r
/* Set configCHECK_FOR_STACK_OVERFLOW to 3 to add ISR stack checking to task\r
stack checking. A problem in the ISR stack will trigger an assert, not call the\r
uint32_t ulCurrentTimeHigh, ulCurrentTimeLow;\r
volatile uint32_t * const pulTimeHigh = ( uint32_t * ) ( configCLINT_BASE_ADDRESS + 0xBFFC );\r
volatile uint32_t * const pulTimeLow = ( uint32_t * ) ( configCLINT_BASE_ADDRESS + 0xBFF8 );\r
+ volatile uint32_t ulHartId = 0;\r
+\r
+ __asm volatile( "csrr %0, 0xf14" : "=r"( ulHartId ) ); /* 0xf14 is hartid. */\r
+ pullMachineTimerCompareRegister = &( pullMachineTimerCompareRegisterBase[ ulHartId ] );\r
\r
do\r
{\r
BaseType_t xPortStartScheduler( void )\r
{\r
extern void xPortStartFirstTask( void );\r
-#warning Replicate this change in the GCC version.\r
- #ifdef configISR_STACK_SIZE_WORDS\r
- xISRStackTop = ( ( StackType_t ) &( xISRStack[ configISR_STACK_SIZE_WORDS - 1 ] ) & ~portBYTE_ALIGNMENT_MASK );\r
- #endif\r
\r
#if( configASSERT_DEFINED == 1 )\r
{\r
/*-----------------------------------------------------------*/\r
\r
SECTION `.text`:CODE:NOROOT(2)\r
- CODE\r
+ CODE\r
\r
freertos_risc_v_trap_handler:\r
addi sp, sp, -portCONTEXT_SIZE\r
#if( __riscv_xlen == 32 )\r
\r
/* Update the 64-bit mtimer compare match value in two 32-bit writes. */\r
+ li t4, -1\r
lw t2, 0(t1) /* Load the low word of ullNextTime into t2. */\r
lw t3, 4(t1) /* Load the high word of ullNextTime into t3. */\r
+ sw t4, 0(t0) /* Low word no smaller than old value. */\r
+ sw t3, 4(t0) /* Store high word of ullNextTime into compare register. No smaller than new value. */\r
sw t2, 0(t0) /* Store low word of ullNextTime into compare register. */\r
- sw t3, 4(t0) /* Store high word of ullNextTime into compare register. */\r
lw t0, uxTimerIncrementsForOneTick /* Load the value of ullTimerIncrementForOneTick into t0 (could this be optimized by storing in an array next to pullNextTime?). */\r
add t4, t0, t2 /* Add the low word of ullNextTime to the timer increments for one tick (assumes timer increment for one tick fits in 32-bits). */\r
sltu t5, t4, t2 /* See if the sum of low words overflowed (what about the zero case?). */\r
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