]> git.sur5r.net Git - freertos/commitdiff
Start to configure the uIP demo for the RX RDK hardware. ping is working, but thus...
authorrichardbarry <richardbarry@1d2547de-c912-0410-9cb9-b8ca96c0e9e2>
Sun, 5 Sep 2010 20:06:30 +0000 (20:06 +0000)
committerrichardbarry <richardbarry@1d2547de-c912-0410-9cb9-b8ca96c0e9e2>
Sun, 5 Sep 2010 20:06:30 +0000 (20:06 +0000)
git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@1081 1d2547de-c912-0410-9cb9-b8ca96c0e9e2

Demo/RX600_RX62N-RDK_Renesas/RTOSDemo.Hbp
Demo/RX600_RX62N-RDK_Renesas/RTOSDemo.tws
Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/FreeRTOSConfig.h
Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/RTOSDemo.hwp
Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/RTOSDemo.nav
Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/SessionRX600_E1_E20_SYSTEM.hsf
Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/webserver/EMAC.c
Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/webserver/uip-conf.h

index 2a473f11a90dc45abf8b27dcda9d0fd25db01c3d..0d3910dbccef6ba5eaef2d6bba2dc3fe4833fd41 100644 (file)
@@ -1,4 +1,4 @@
 [Setting]\r
 ToolChain=0\r
 [Section]\r
-WindowSize=341,352\r
+WindowSize=726,544\r
index ef666fddb1892fcab9353d33114cd7ffdbf0c996..91b379218c8c9229ab49622e31e82b311ce6afcb 100644 (file)
@@ -7,7 +7,9 @@
 [GENERAL_DATA]\r
 [BREAKPOINTS]\r
 [OPEN_WORKSPACE_FILES]\r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo\main-full.c" \r
 [WORKSPACE_FILE_STATES]\r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo\main-full.c" -4 -23 982 516 1 0 \r
 [LOADED_PROJECTS]\r
 "RTOSDemo" \r
 [END]\r
index ae232e346f77074d5b06d9e57b90665e2da80dbf..7a3ea5f6f73aef8cd856078256bc328d1647f352 100644 (file)
@@ -135,9 +135,9 @@ to exclude the API function. */
 #define configMAC_ADDR5        0x11\r
 \r
 /* IP address configuration. */\r
-#define configIP_ADDR0         172\r
-#define configIP_ADDR1         25\r
-#define configIP_ADDR2         218\r
+#define configIP_ADDR0         192\r
+#define configIP_ADDR1         168\r
+#define configIP_ADDR2         0\r
 #define configIP_ADDR3         200\r
 \r
 /* Netmask configuration. */\r
index 1aa6879676a29231e6b030dd090485c69dfb1d60..340acd12c675f589d59b7a0f652f2c783f4474c7 100644 (file)
 [LINKAGE_ORDER_Blinky]\r
 [GENERAL_DATA_CONFIGURATION_Blinky]\r
 [OPTIONS_Debug_Renesas OptLinker]\r
-"Single Shot" "0cb38d9776b4bc10" 5 \r
+"Single Shot" "0413bf9353d4bc10" 5 \r
 [OPTIONS_Debug_Renesas RX Assembler]\r
 "Assembly source file" "088b30f0a993bc10" 4 \r
 "C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo\Renesas-Files\lowlvl.src" "0cd92d23ed14bc10" 4 \r
 " 2 \r
 "[V|VERSION|1] [S|MODE|BUILD/CHANGED] [S|EXISTOUTPUTPATH|^"$(CONFIGDIR)\$(PROJECTNAME).lib^"] [B|RUNTIME|1] [B|MATH|1] [B|STDIO|1] [B|STDLIB|1] [B|STRING|1] [B|NOFLOAT|1] [S|OUTPUTPATH|^"$(CONFIGDIR)\$(PROJECTNAME).lib^"] [B|SIZE|1] [I|INLINE|100] [I|LOOP|2] [S|CPU|RX600] [S|BASE|00000000=NONE] [B|SKIPDEPENDENCY|1]\r
 " 1 \r
-"[V|VERSION|6] [S|FORM|STYPE] [S|BYTE_COUNT_VALUE|FF] [B|DEBUG|1] [S|ROM|(D,R)|(D_1,R_1)|(D_2,R_2)] [S|CRC|NONE|DEFAULT|00000000] [B|LIST|1] [S|LIST|^"$(CONFIGDIR)\$(PROJECTNAME).map^"] [S|SHOW|METHODCUSTOM|] [S|OUTPUT|^"$(CONFIGDIR)\$(PROJECTNAME).mot^"] [I|SPACE|^"FF^"] [B|OPTIMIZE|0] [S|START|B_1,R_1,B_2,R_2,B,R,SU,SI(01000)|PResetPRG(0FFF80000)|C_1,C_2,C,C$*,D*,P,PIntPRG,W*(0FFF81000)|FIXEDVECT(0FFFFFFD0)] [B|SKIPDEPENDENCY|1]\r
+"[V|VERSION|6] [S|PRELINK|SKIP] [S|FORM|STYPE] [S|BYTE_COUNT_VALUE|FF] [B|DEBUG|1] [S|ROM|(D,R)|(D_1,R_1)|(D_2,R_2)] [S|CRC|NONE|DEFAULT|00000000] [B|LIST|1] [S|LIST|^"$(CONFIGDIR)\$(PROJECTNAME).map^"] [S|SHOW|METHODCUSTOM|] [S|OUTPUT|^"$(CONFIGDIR)\$(PROJECTNAME).mot^"] [I|SPACE|^"FF^"] [B|OPTIMIZE|0] [S|START|B_RX_DESC,B_TX_DESC,B_ETHERNET_BUFFERS,B_1,R_1,B_2,R_2,B,R,SU,SI(01000)|PResetPRG(0FFF80000)|C_1,C_2,C,C$*,D*,P,PIntPRG,W*(0FFF81000)|FIXEDVECT(0FFFFFFD0)] [B|SKIPDEPENDENCY|1]\r
 " 5 \r
 [EXCLUDED_FILES_Debug]\r
 "C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo\main-blinky.c" \r
index 39863df2d58806ac89bbe870e9951b84507ff86a..1977f93ee836afcbb854ee186c67f438d253b040 100644 (file)
Binary files a/Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/RTOSDemo.nav and b/Demo/RX600_RX62N-RDK_Renesas/RTOSDemo/RTOSDemo.nav differ
index 782f0ebfa525f08514820d2e8c07daf97c2a4a6f..e68dc7d8638729742b6e7fc4c236648d75b7976d 100644 (file)
@@ -8,7 +8,7 @@
 "" \r
 [GENERAL_DATA]\r
 "FIRST_CONNECTION_TAG" "NO" \r
-"MRULABELS_DATAMANAGER_KEY" "00000000|FFFFFFFF|88218|000870B4|000870AE|88204|88208|18b8" \r
+"MRULABELS_DATAMANAGER_KEY" "FFFFFFFF|00000000|1054|fff8cd9e|1050|fff8c484|88218|000870B4|000870AE|88204|88208|18b8" \r
 "RESET_CPU_AFTER_DOWNLOAD_TAG" "VARIANT_TRUE_STORE_TAG" \r
 "{228DB593-0AB2-4EBE-A098-A2CABF094E46}RamMonitorCtrlViews" "0" \r
 "{287A8023-99B5-49E1-A54E-4DDCA43D7959}MapCtrlECX_MAP_FIND_SYMBOL_LIST" "" \r
@@ -30,7 +30,7 @@
 "{313F4FC1-6566-11D5-8BBE-0004E2013C71}TclTkCtrlLogFileName" "" \r
 "{313F4FC2-6566-11D5-8BBE-0004E2013C71}ECX_MEMORY_COMPARE_END_ADDRESS" "" \r
 "{313F4FC2-6566-11D5-8BBE-0004E2013C71}ECX_MEMORY_COMPARE_START_ADDRESS" "" \r
-"{313F4FC2-6566-11D5-8BBE-0004E2013C71}ECX_MEMORY_DISPLAY_DEST_ADDRESS" "88218\r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}ECX_MEMORY_DISPLAY_DEST_ADDRESS" "1054\r
 "{313F4FC2-6566-11D5-8BBE-0004E2013C71}ECX_MEMORY_DISPLAY_END_ADDRESS" "FFFFFFFF" \r
 "{313F4FC2-6566-11D5-8BBE-0004E2013C71}ECX_MEMORY_DISPLAY_START_ADDRESS" "00000000" \r
 "{313F4FC2-6566-11D5-8BBE-0004E2013C71}ECX_MEMORY_FILL_END_ADDRESS" "" \r
 "{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryCtrlViews" "0" \r
 "{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewA0AutoRefreshEnableTopPane" "0" \r
 "{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewA0AutoRefreshIntervalTopPane" "100" \r
-"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewA0DataLength" "1\r
-"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewA0DispAddressTopPane" "553134\r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewA0DataLength" "4\r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewA0DispAddressTopPane" "4180\r
 "{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewA0DispCode" "42208" \r
-"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewA0DispColumnCount" "16\r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewA0DispColumnCount" "4\r
 "{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewA0IsDispCode" "1" \r
 "{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewA0IsDispFloat" "0" \r
 "{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewA0IsDispLabel" "0" \r
 "{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewAInstanceKey0" "{WK_00000001_MEMORY}RTOSDemoSessionRX600_E1_E20_SYSTEM" \r
 "{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewB0AutoRefreshEnableTopPane" "0" \r
 "{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewB0AutoRefreshIntervalTopPane" "100" \r
-"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewB0DataLength" "1\r
-"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewB0DispAddressTopPane" "553134\r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewB0DataLength" "4\r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewB0DispAddressTopPane" "4180\r
 "{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewB0DispCode" "42208" \r
-"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewB0DispColumnCount" "16\r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewB0DispColumnCount" "4\r
 "{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewB0IsDispCode" "1" \r
 "{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewB0IsDispFloat" "0" \r
 "{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewB0IsDispLabel" "0" \r
 "{5F75FDA0-6FF0-11D5-B7CE-00E029352378}PACtrlViews" "0" \r
 "{64753FED-D387-4B8C-A91D-D3419C869C07}C_EVAL_DENORMAL_MODE" "16777216" \r
 "{64753FED-D387-4B8C-A91D-D3419C869C07}C_EVAL_ROUND_MODE" "768" \r
-"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_0" "000000000000BAEC\r
-"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_1" "0000000000000007\r
+"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_0" "0000000000003DA4\r
+"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_1" "000000000000EBA8\r
 "{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_10" "00000000A5A5A5A5" \r
 "{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_11" "00000000A5A5A5A5" \r
 "{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_12" "00000000A5A5A5A5" \r
 "{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_13" "00000000A5A5A5A5" \r
-"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_14" "0000000000000007\r
-"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_15" "00000000A5A5A5A5\r
-"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_16" "000000000000BAEC\r
-"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_17" "0000000000011220\r
-"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_18" "0000000000030000\r
-"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_19" "00000000FFF8E520\r
-"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_2" "000000000000C508\r
+"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_14" "0000000000000020\r
+"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_15" "0000000000001BE4\r
+"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_16" "0000000000003DA4\r
+"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_17" "0000000000011224\r
+"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_18" "0000000000030001\r
+"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_19" "00000000FFF9312A\r
+"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_2" "0000000000000020\r
 "{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_20" "00000000FFF8C424" \r
 "{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_21" "0000000080000000" \r
 "{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_22" "0000000000000000" \r
 "{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_23" "0000000000000000" \r
 "{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_24" "0000000000000100" \r
 "{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_25" "1234567887650000" \r
-"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_3" "0000000041480000\r
-"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_4" "0000000040E00000\r
-"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_5" "000000000000C4E0\r
-"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_6" "00000000A5A5A5A5\r
-"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_7" "00000000A5A5A5A5\r
+"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_3" "000000000000EB9C\r
+"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_4" "00000000000001A7\r
+"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_5" "0000000000001C1A\r
+"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_6" "0000000000000008\r
+"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_7" "0000000000000008\r
 "{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_8" "00000000A5A5A5A5" \r
 "{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_9" "00000000A5A5A5A5" \r
 "{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_COUNT" "26" \r
 "{8A898260-6F1D-11D5-8EB6-00004CC34E9D}ECX_WAVE_COMB_BUFFER" ",,,," \r
 "{8A898260-6F1D-11D5-8EB6-00004CC34E9D}ECX_WAVE_SAMPLING_RATE" "1000" \r
 "{8A898260-6F1D-11D5-8EB6-00004CC34E9D}WaveformCtrlViews" "0" \r
-"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersCtrlViews" "0\r
+"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersCtrlViews" "1\r
 "{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersWnd0ColumnWidth" "47,153,35" \r
 "{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersWnd0ECX_REGISTER_COUNT" "33" \r
 "{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersWnd0ECX_REGISTER_DISPLAYED" "1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1" \r
 "{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ColWidth12" "200" \r
 "{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ColWidth2" "120" \r
 "{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ColWidth3" "200" \r
-"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ECX_WATCH_ITEM0000" "cErrorText, 10, 0, P, Col, Hex, N" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ECX_WATCH_ITEM0000" "xCurrentRxDesc, 10, 0, P, Col, Hex, N" \r
 "{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ECX_WATCH_ITEM0000_SCOPE" "Current Scope," \r
-"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ECX_WATCH_ITEMCnt" "1" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ECX_WATCH_ITEM0001" "xEthernetBuffers, 11, 0, P, Exp, Hex, MN" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ECX_WATCH_ITEM0001_SCOPE" "Current Scope," \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ECX_WATCH_ITEM0002" "ulAlignmentVariable, 2, 0, C0001, Col, Hex, MN" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ECX_WATCH_ITEM0003" "cBuffer, 6, 0, C0001, Col, Hex, MN" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ECX_WATCH_ITEM0004" "xRxDescriptors, 6, 0, P, Col, Hex, MN" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ECX_WATCH_ITEM0004_SCOPE" "Current Scope," \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ECX_WATCH_ITEM0005" "xTxDescriptors, 6, 0, P, Col, Hex, MN" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ECX_WATCH_ITEM0005_SCOPE" "Current Scope," \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ECX_WATCH_ITEMCnt" "0" \r
 "{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd1ColWidth0" "120" \r
 "{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd1ColWidth1" "150" \r
 "{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd1ColWidth12" "200" \r
 "{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp0" "0" \r
 "{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp1" "0" \r
 "{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp10" "0" \r
+"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp100" "0" \r
+"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp101" "0" \r
+"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp102" "0" \r
+"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp103" "0" \r
+"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp104" "0" \r
+"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp105" "0" \r
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 "{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp11" "0" \r
+"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp110" "0" \r
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+"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp119" "0" \r
 "{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp12" "0" \r
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 "{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp13" "0" \r
 "{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp14" "0" \r
 "{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp15" "0" \r
-"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp16" "1\r
+"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp16" "0\r
 "{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp17" "0" \r
 "{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp18" "0" \r
 "{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp19" "0" \r
 "{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp75" "0" \r
 "{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp76" "0" \r
 "{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp77" "0" \r
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 "{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp8" "0" \r
 "{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp80" "0" \r
 "{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp81" "0" \r
 "{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp82" "0" \r
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+"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp89" "0" \r
 "{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp9" "0" \r
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+"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp99" "0" \r
 "{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0ScrollHorz" "0" \r
-"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0ScrollVert" "16" \r
+"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0ScrollVert" "96" \r
 "{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd1ColWidth0" "200" \r
 "{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd1ColWidth1" "100" \r
 "{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd1ColWidth2" "100" \r
 0 \r
 [WINDOW_POSITION_STATE_DATA_VD1]\r
 "Help" "TOOLBAR 0" 59419 1 5 "0.00" 0 0 0 0 0 17 0 "" "0.0" \r
-"{WK_00000001_CmdLine}" "WINDOW" 59422 0 2 "0.07" 270 0 0 350 200 17 0 "32771|32772|32778|<<separator>>|32773|32774|<<separator>>|32820|<<separator>>|32801|32824" "0.0" \r
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 "{WK_00000001_DISASSEMBLY}" "WINDOW" 0 0 0 "0.00" 0 0 0 1062 571 9 0 "" "0.0" \r
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-"{WK_00000001_REGISTERS}RTOSDemoSessionRX600_E1_E20_SYSTEM" "WINDOW" 59421 0 0 "1.00" 307 0 0 350 200 2065 0 "" "0.0" \r
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 "{WK_00000002_WORKSPACE}" "WINDOW" 59420 0 0 "1.00" 360 560 340 350 200 18 0 "" "0.0" \r
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 [WINDOW_POSITION_STATE_DATA_VD3]\r
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 [WINDOW_Z_ORDER]\r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo\main-full.c" \r
 [TARGET_NAME]\r
 "RX600 E1/E20 SYSTEM" "" 0 \r
 [STATUSBAR_STATEINFO_VD1]\r
 "SBK_TAR_EMUE100|Exception" 1 \r
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 "SBK_TAR_EMUE100|TaskID" 1 \r
-"SBK_TAR_EMUE100|PC" 1 \r
 "SBK_TAR_EMUE100|ExecutionTime" 1 \r
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 "" 0 0 "" 0 "" 0 0 "" 0 0 0 0 0 0 0 "" "" "" "" "" \r
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 [END]\r
index 2824ca066f87757b835afb7c14579d1aa474d0fb..5181d452fa09cddb225c0d7335d0933972c14375 100644 (file)
@@ -55,7 +55,6 @@
 #include "iodefine.h"\r
 #include "typedefine.h"\r
 #include "r_ether.h"\r
-#include "phy.h"\r
 \r
 /* FreeRTOS includes. */\r
 #include "FreeRTOS.h"\r
@@ -95,28 +94,24 @@ become free. */
 \r
 /*-----------------------------------------------------------*/\r
 \r
-/* The buffers and descriptors themselves. */\r
-static union x_RX_Desc\r
-{\r
-       unsigned long long ullAlignmentVariable;\r
-       ethfifo xDescriptorArray[ emacNUM_RX_DESCRIPTORS ];\r
-} xRxDescriptors;\r
+/* The buffers and descriptors themselves.  */\r
+#pragma section _RX_DESC\r
+       volatile ethfifo xRxDescriptors[ emacNUM_RX_DESCRIPTORS ];\r
+#pragma section _TX_DESC\r
+       volatile ethfifo xTxDescriptors[ emacNUM_TX_BUFFERS ];\r
+#pragma section _ETHERNET_BUFFERS\r
+       struct\r
+       {\r
+               unsigned long ulAlignmentVariable;\r
+               char cBuffer[ emacNUM_BUFFERS ][ UIP_BUFSIZE ];\r
+       } xEthernetBuffers;\r
+#pragma section\r
 \r
-static union x_TX_Desc\r
-{\r
-       unsigned long long ullAlignmentVariable;\r
-       ethfifo xDescriptorArray[ emacNUM_TX_BUFFERS ];\r
-} xTxDescriptors;\r
 \r
-static union x_ETH_Buffers\r
-{\r
-       unsigned long long ullAlignmentVariable;\r
-       char xDataBuffers[ emacNUM_BUFFERS ][ UIP_BUFSIZE ];\r
-} xEthernetBuffers;\r
 \r
 \r
 /* Used to indicate which buffers are free and which are in use.  If an index\r
-contains 0 then the corresponding buffer in xEthernetBuffers.xDataBuffers is free, otherwise \r
+contains 0 then the corresponding buffer in xEthernetBuffers is free, otherwise \r
 the buffer is in use or about to be used. */\r
 static unsigned char ucBufferInUse[ emacNUM_BUFFERS ];\r
 \r
@@ -128,7 +123,7 @@ static unsigned char ucBufferInUse[ emacNUM_BUFFERS ];
 static void prvInitialiseDescriptors( void );\r
 \r
 /*\r
- * Return a pointer to a free buffer within xEthernetBuffers.xDataBuffers.\r
+ * Return a pointer to a free buffer within xEthernetBuffers.\r
  */\r
 static unsigned char *prvGetNextBuffer( void );\r
 \r
@@ -204,7 +199,7 @@ long x;
        /* Wait until the second transmission of the last packet has completed. */\r
        for( x = 0; x < emacTX_WAIT_ATTEMPTS; x++ )\r
        {\r
-               if( ( xTxDescriptors.xDescriptorArray[ 1 ].status & ACT ) != 0 )\r
+               if( ( xTxDescriptors[ 1 ].status & ACT ) != 0 )\r
                {\r
                        /* Descriptor is still active. */\r
                        vTaskDelay( emacTX_WAIT_DELAY_ms );\r
@@ -216,27 +211,27 @@ long x;
        }\r
        \r
        /* Is the descriptor free after waiting for it? */\r
-       if( ( xTxDescriptors.xDescriptorArray[ 1 ].status & ACT ) != 0 )\r
+       if( ( xTxDescriptors[ 1 ].status & ACT ) != 0 )\r
        {\r
                /* Something has gone wrong. */\r
                prvResetEverything();\r
        }\r
        \r
        /* Setup both descriptors to transmit the frame. */\r
-       xTxDescriptors.xDescriptorArray[ 0 ].buf_p = ( char * ) uip_buf;\r
-       xTxDescriptors.xDescriptorArray[ 0 ].bufsize = uip_len; \r
-       xTxDescriptors.xDescriptorArray[ 1 ].buf_p = ( char * ) uip_buf;\r
-       xTxDescriptors.xDescriptorArray[ 1 ].bufsize = uip_len;\r
+       xTxDescriptors[ 0 ].buf_p = ( char * ) uip_buf;\r
+       xTxDescriptors[ 0 ].bufsize = uip_len;  \r
+       xTxDescriptors[ 1 ].buf_p = ( char * ) uip_buf;\r
+       xTxDescriptors[ 1 ].bufsize = uip_len;\r
 \r
        /* uip_buf is being sent by the Tx descriptor.  Allocate a new buffer\r
        for use by the stack. */\r
        uip_buf = prvGetNextBuffer();\r
 \r
        /* Clear previous settings and go. */\r
-       xTxDescriptors.xDescriptorArray[0].status &= ~( FP1 | FP0 );\r
-       xTxDescriptors.xDescriptorArray[0].status |= ( FP1 | FP0 | ACT );\r
-       xTxDescriptors.xDescriptorArray[1].status &= ~( FP1 | FP0 );\r
-       xTxDescriptors.xDescriptorArray[1].status |= ( FP1 | FP0 | ACT );\r
+       xTxDescriptors[0].status &= ~( FP1 | FP0 );\r
+       xTxDescriptors[0].status |= ( FP1 | FP0 | ACT );\r
+       xTxDescriptors[1].status &= ~( FP1 | FP0 );\r
+       xTxDescriptors[1].status |= ( FP1 | FP0 | ACT );\r
 \r
        EDMAC.EDTRR.LONG = 0x00000001;\r
 }\r
@@ -282,15 +277,28 @@ long lReturn;
        {\r
                /* Half duplex link */\r
                case PHY_LINK_100H:\r
+                                                               ETHERC.ECMR.BIT.DM = 0;\r
+                                                               ETHERC.ECMR.BIT.RTM = 1;\r
+                                                               lReturn = pdPASS;\r
+                                                               break;\r
+\r
                case PHY_LINK_10H:\r
                                                                ETHERC.ECMR.BIT.DM = 0;\r
+                                                               ETHERC.ECMR.BIT.RTM = 0;\r
                                                                lReturn = pdPASS;\r
                                                                break;\r
 \r
+\r
                /* Full duplex link */\r
                case PHY_LINK_100F:\r
+                                                               ETHERC.ECMR.BIT.DM = 1;\r
+                                                               ETHERC.ECMR.BIT.RTM = 1;\r
+                                                               lReturn = pdPASS;\r
+                                                               break;\r
+               \r
                case PHY_LINK_10F:\r
                                                                ETHERC.ECMR.BIT.DM = 1;\r
+                                                               ETHERC.ECMR.BIT.RTM = 0;\r
                                                                lReturn = pdPASS;\r
                                                                break;\r
 \r
@@ -327,13 +335,13 @@ long x;
        /* Initialise the Rx descriptors. */\r
        for( x = 0; x < emacNUM_RX_DESCRIPTORS; x++ )\r
        {\r
-               pxDescriptor = &( xRxDescriptors.xDescriptorArray[ x ] );\r
-               pxDescriptor->buf_p = &( xEthernetBuffers.xDataBuffers[ x ][ 0 ] );\r
+               pxDescriptor = &( xRxDescriptors[ x ] );\r
+               pxDescriptor->buf_p = &( xEthernetBuffers.cBuffer[ x ][ 0 ] );\r
 \r
                pxDescriptor->bufsize = UIP_BUFSIZE;\r
                pxDescriptor->size = 0;\r
                pxDescriptor->status = ACT;\r
-               pxDescriptor->next = &xRxDescriptors.xDescriptorArray[ x + 1 ]; \r
+               pxDescriptor->next = &xRxDescriptors[ x + 1 ];  \r
                \r
                /* Mark this buffer as in use. */\r
                ucBufferInUse[ x ] = pdTRUE;\r
@@ -341,12 +349,12 @@ long x;
 \r
        /* The last descriptor points back to the start. */\r
        pxDescriptor->status |= DL;\r
-       pxDescriptor->next = &xRxDescriptors.xDescriptorArray[ 0 ];\r
+       pxDescriptor->next = &xRxDescriptors[ 0 ];\r
        \r
        /* Initialise the Tx descriptors. */\r
        for( x = 0; x < emacNUM_TX_BUFFERS; x++ )\r
        {\r
-               pxDescriptor = &( xTxDescriptors.xDescriptorArray[ x ] );\r
+               pxDescriptor = &( xTxDescriptors[ x ] );\r
                \r
                /* A buffer is not allocated to the Tx descriptor until a send is\r
                actually required. */\r
@@ -355,15 +363,15 @@ long x;
                pxDescriptor->bufsize = UIP_BUFSIZE;\r
                pxDescriptor->size = 0;\r
                pxDescriptor->status = 0;\r
-               pxDescriptor->next = &xTxDescriptors.xDescriptorArray[ x + 1 ]; \r
+               pxDescriptor->next = &xTxDescriptors[ x + 1 ];  \r
        }\r
 \r
        /* The last descriptor points back to the start. */\r
        pxDescriptor->status |= DL;\r
-       pxDescriptor->next = &( xTxDescriptors.xDescriptorArray[ 0 ] );\r
+       pxDescriptor->next = &( xTxDescriptors[ 0 ] );\r
        \r
        /* Use the first Rx descriptor to start with. */\r
-       xCurrentRxDesc = &( xRxDescriptors.xDescriptorArray[ 0 ] );\r
+       xCurrentRxDesc = &( xRxDescriptors[ 0 ] );\r
 }\r
 /*-----------------------------------------------------------*/\r
 \r
@@ -382,7 +390,7 @@ unsigned long ulAttempts = 0;
                        if( ucBufferInUse[ x ] == pdFALSE )\r
                        {\r
                                ucBufferInUse[ x ] = pdTRUE;\r
-                               pucReturn = ( unsigned char * ) &( xEthernetBuffers.xDataBuffers[ x ][ 0 ] );\r
+                               pucReturn = ( unsigned char * ) &( xEthernetBuffers.cBuffer[ x ][ 0 ] );\r
                                break;\r
                        }\r
                }\r
@@ -413,7 +421,7 @@ unsigned long ul;
        /* Return a buffer to the pool of free buffers. */\r
        for( ul = 0; ul < emacNUM_BUFFERS; ul++ )\r
        {\r
-               if( &( xEthernetBuffers.xDataBuffers[ ul ][ 0 ] ) == ( void * ) pucBuffer )\r
+               if( &( xEthernetBuffers.cBuffer[ ul ][ 0 ] ) == ( void * ) pucBuffer )\r
                {\r
                        ucBufferInUse[ ul ] = pdFALSE;\r
                        break;\r
@@ -503,12 +511,18 @@ static void prvConfigureEtherCAndEDMAC( void )
 \r
        /* EDMAC */\r
        EDMAC.EESR.LONG = 0x47FF0F9F;                           /* Clear all ETHERC and EDMAC status bits */\r
+       #ifdef __LIT\r
+               EDMAC.EDMR.BIT.DE = 1;\r
+       #endif\r
        EDMAC.RDLAR = ( void * ) xCurrentRxDesc;        /* Initialaize Rx Descriptor List Address */\r
-       EDMAC.TDLAR = &( xTxDescriptors.xDescriptorArray[ 0 ] );                /* Initialaize Tx Descriptor List Address */\r
+       EDMAC.TDLAR = &( xTxDescriptors[ 0 ] );         /* Initialaize Tx Descriptor List Address */\r
        EDMAC.TRSCER.LONG = 0x00000000;                         /* Copy-back status is RFE & TFE only   */\r
        EDMAC.TFTR.LONG = 0x00000000;                           /* Threshold of Tx_FIFO */\r
        EDMAC.FDR.LONG = 0x00000000;                            /* Transmit fifo & receive fifo is 256 bytes */\r
        EDMAC.RMCR.LONG = 0x00000003;                           /* Receive function is normal mode(continued) */\r
+       \r
+       /* Enable the interrupt... */\r
+       _IEN( _ETHER_EINT ) = 1;        \r
 }\r
 /*-----------------------------------------------------------*/\r
 \r
@@ -527,7 +541,7 @@ static long ulTxEndInts = 0;
                if( ulTxEndInts >= 2 )\r
                {\r
                        /* Only return the buffer to the pool once both Txes have completed. */\r
-                       prvReturnBuffer( ( void * ) xTxDescriptors.xDescriptorArray[ 0 ].buf_p );\r
+                       prvReturnBuffer( ( void * ) xTxDescriptors[ 0 ].buf_p );\r
                        ulTxEndInts = 0;\r
                }\r
                EDMAC.EESR.LONG = emacTX_END_INTERRUPT;\r
@@ -542,3 +556,4 @@ static long ulTxEndInts = 0;
                EDMAC.EESR.LONG = emacRX_END_INTERRUPT;\r
        }\r
 }\r
+\r
index 62572085ffa909d8c5814eb803b722ed8ac8b444..70b70337b1fcb3e73980893f38f8c18d819d0164 100644 (file)
@@ -114,7 +114,7 @@ typedef unsigned short uip_stats_t;
  *\r
  * \hideinitializer\r
  */\r
-#define UIP_CONF_BYTE_ORDER      UIP_BIG_ENDIAN\r
+#define UIP_CONF_BYTE_ORDER      UIP_LITTLE_ENDIAN\r
 \r
 /**\r
  * Logging on or off\r