<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
+ <File>
+ <GroupNumber>3</GroupNumber>
+ <FileNumber>7</FileNumber>
+ <FileType>1</FileType>
+ <tvExp>0</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <bDave2>0</bDave2>
+ <PathWithFileName>..\..\..\Nuvoton_Code\StdDriver\src\clk.c</PathWithFileName>
+ <FilenameWithoutPath>clk.c</FilenameWithoutPath>
+ <RteFlg>0</RteFlg>
+ <bShared>0</bShared>
+ </File>
</Group>
<Group>
<RteFlg>0</RteFlg>
<File>
<GroupNumber>4</GroupNumber>
- <FileNumber>7</FileNumber>
+ <FileNumber>8</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
</File>
<File>
<GroupNumber>4</GroupNumber>
- <FileNumber>8</FileNumber>
+ <FileNumber>9</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
</File>
<File>
<GroupNumber>4</GroupNumber>
- <FileNumber>9</FileNumber>
+ <FileNumber>10</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
</File>
<File>
<GroupNumber>4</GroupNumber>
- <FileNumber>10</FileNumber>
+ <FileNumber>11</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
</File>
<File>
<GroupNumber>4</GroupNumber>
- <FileNumber>11</FileNumber>
+ <FileNumber>12</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
</File>
<File>
<GroupNumber>4</GroupNumber>
- <FileNumber>12</FileNumber>
+ <FileNumber>13</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
</File>
<File>
<GroupNumber>4</GroupNumber>
- <FileNumber>13</FileNumber>
+ <FileNumber>14</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
</File>
<File>
<GroupNumber>4</GroupNumber>
- <FileNumber>14</FileNumber>
+ <FileNumber>15</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
</File>
<File>
<GroupNumber>4</GroupNumber>
- <FileNumber>15</FileNumber>
+ <FileNumber>16</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
</File>
<File>
<GroupNumber>4</GroupNumber>
- <FileNumber>16</FileNumber>
+ <FileNumber>17</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
</File>
<File>
<GroupNumber>4</GroupNumber>
- <FileNumber>17</FileNumber>
+ <FileNumber>18</FileNumber>
<FileType>5</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
</File>
<File>
<GroupNumber>4</GroupNumber>
- <FileNumber>18</FileNumber>
+ <FileNumber>19</FileNumber>
<FileType>5</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<RteFlg>0</RteFlg>
<File>
<GroupNumber>5</GroupNumber>
- <FileNumber>19</FileNumber>
+ <FileNumber>20</FileNumber>
<FileType>5</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
</File>
<File>
<GroupNumber>5</GroupNumber>
- <FileNumber>20</FileNumber>
+ <FileNumber>21</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
</File>
<File>
<GroupNumber>5</GroupNumber>
- <FileNumber>21</FileNumber>
+ <FileNumber>22</FileNumber>
<FileType>5</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
</File>
<File>
<GroupNumber>5</GroupNumber>
- <FileNumber>22</FileNumber>
+ <FileNumber>23</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<RteFlg>0</RteFlg>
<File>
<GroupNumber>6</GroupNumber>
- <FileNumber>23</FileNumber>
+ <FileNumber>24</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<FileType>1</FileType>
<FilePath>..\..\..\Nuvoton_Code\StdDriver\src\retarget.c</FilePath>
</File>
+ <File>
+ <FileName>clk.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\Nuvoton_Code\StdDriver\src\clk.c</FilePath>
+ </File>
</Files>
</Group>
<Group>
" movs r0, #4 \n"\r
" mov r1, lr \n"\r
" tst r0, r1 \n"\r
- " beq stacking_used_msp \n"\r
+ " beq msp_used_for_stacking \n"\r
" mrs r0, psp \n"\r
" ldr r2, handler_address_const \n"\r
" bx r2 \n"\r
- "stacking_used_msp: \n"\r
+ "msp_used_for_stacking: \n"\r
" mrs r0, msp \n"\r
" ldr r2, handler_address_const \n"\r
" bx r2 \n"\r
}\r
/*-----------------------------------------------------------*/\r
\r
-void vHandleMemoryFault( uint32_t * pulFaultStackAddress )\r
+portDONT_DISCARD void vHandleMemoryFault( uint32_t * pulFaultStackAddress )\r
{\r
uint32_t ulPC;\r
+uint16_t usOffendingInstruction;\r
\r
/* Is this an expected fault? */\r
if( ucROTaskFaultTracker[ 0 ] == 1 )\r
/* Read program counter. */\r
ulPC = pulFaultStackAddress[ 6 ];\r
\r
- /* Increment the program counter by 2 to move to the next instruction. */\r
- ulPC += 2;\r
+ /* Read the offending instruction. */\r
+ usOffendingInstruction = *( uint16_t * )ulPC;\r
+\r
+ /* From ARM docs:\r
+ * If the value of bits[15:11] of the halfword being decoded is one of\r
+ * the following, the halfword is the first halfword of a 32-bit\r
+ * instruction:\r
+ * - 0b11101.\r
+ * - 0b11110.\r
+ * - 0b11111.\r
+ * Otherwise, the halfword is a 16-bit instruction.\r
+ */\r
+\r
+ /* Extract bits[15:11] of the offending instruction. */\r
+ usOffendingInstruction = usOffendingInstruction & 0xF800;\r
+ usOffendingInstruction = ( usOffendingInstruction >> 11 );\r
+\r
+ /* Determine if the offending instruction is a 32-bit instruction or\r
+ * a 16-bit instruction. */\r
+ if( usOffendingInstruction == 0x001F ||\r
+ usOffendingInstruction == 0x001E ||\r
+ usOffendingInstruction == 0x001D )\r
+ {\r
+ /* Since the offending instruction is a 32-bit instruction,\r
+ * increment the program counter by 4 to move to the next\r
+ * instruction. */\r
+ ulPC += 4;\r
+ }\r
+ else\r
+ {\r
+ /* Since the offending instruction is a 16-bit instruction,\r
+ * increment the program counter by 2 to move to the next\r
+ * instruction. */\r
+ ulPC += 2;\r
+ }\r
\r
/* Save the new program counter on the stack. */\r
pulFaultStackAddress[ 6 ] = ulPC;\r
#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )\r
#endif\r
\r
+#ifndef portDONT_DISCARD\r
+ #define portDONT_DISCARD\r
+#endif\r
+\r
#ifndef configUSE_TIME_SLICING\r
#define configUSE_TIME_SLICING 1\r
#endif\r
* Sets the pointer to the current TCB to the TCB of the highest priority task\r
* that is ready to run.\r
*/\r
-void vTaskSwitchContext( void ) PRIVILEGED_FUNCTION;\r
+portDONT_DISCARD void vTaskSwitchContext( void ) PRIVILEGED_FUNCTION;\r
\r
/*\r
* THESE FUNCTIONS MUST NOT BE USED FROM APPLICATION CODE. THEY ARE USED BY\r
/**\r
* @brief C part of SVC handler.\r
*/\r
-void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) PRIVILEGED_FUNCTION;\r
+portDONT_DISCARD void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) PRIVILEGED_FUNCTION;\r
/*-----------------------------------------------------------*/\r
\r
/**\r
* @brief Saved as part of the task context to indicate which context the\r
* task is using on the secure side.\r
*/\r
- volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;\r
+ portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;\r
#endif /* configENABLE_TRUSTZONE */\r
/*-----------------------------------------------------------*/\r
\r
}\r
/*-----------------------------------------------------------*/\r
\r
-void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) /* PRIVILEGED_FUNCTION */\r
+void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */\r
{\r
#if( configENABLE_MPU == 1 )\r
#if defined( __ARMCC_VERSION )\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+#ifndef PORTMACRO_H\r
+#define PORTMACRO_H\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Port specific definitions.\r
+ *\r
+ * The settings in this file configure FreeRTOS correctly for the given hardware\r
+ * and compiler.\r
+ *\r
+ * These settings should not be altered.\r
+ *------------------------------------------------------------------------------\r
+ */\r
+\r
+#ifndef configENABLE_FPU\r
+ #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.\r
+#endif /* configENABLE_FPU */\r
+\r
+#ifndef configENABLE_MPU\r
+ #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.\r
+#endif /* configENABLE_MPU */\r
+\r
+#ifndef configENABLE_TRUSTZONE\r
+ #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.\r
+#endif /* configENABLE_TRUSTZONE */\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Type definitions.\r
+ */\r
+#define portCHAR char\r
+#define portFLOAT float\r
+#define portDOUBLE double\r
+#define portLONG long\r
+#define portSHORT short\r
+#define portSTACK_TYPE uint32_t\r
+#define portBASE_TYPE long\r
+\r
+typedef portSTACK_TYPE StackType_t;\r
+typedef long BaseType_t;\r
+typedef unsigned long UBaseType_t;\r
+\r
+#if( configUSE_16_BIT_TICKS == 1 )\r
+ typedef uint16_t TickType_t;\r
+ #define portMAX_DELAY ( TickType_t ) 0xffff\r
+#else\r
+ typedef uint32_t TickType_t;\r
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL\r
+\r
+ /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do\r
+ * not need to be guarded with a critical section. */\r
+ #define portTICK_TYPE_IS_ATOMIC 1\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * Architecture specifics.\r
+ */\r
+#define portARCH_NAME "Cortex-M23"\r
+#define portSTACK_GROWTH ( -1 )\r
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )\r
+#define portBYTE_ALIGNMENT 8\r
+#define portNOP()\r
+#define portINLINE __inline\r
+#ifndef portFORCE_INLINE\r
+ #define portFORCE_INLINE inline __attribute__(( always_inline ))\r
+#endif\r
+#define portHAS_STACK_OVERFLOW_CHECKING 1\r
+#define portDONT_DISCARD __attribute__(( used ))\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Extern declarations.\r
+ */\r
+extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;\r
+\r
+extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;\r
+extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;\r
+\r
+extern uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
+extern void vClearInterruptMaskFromISR( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
+\r
+#if( configENABLE_TRUSTZONE == 1 )\r
+ extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */\r
+ extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;\r
+#endif /* configENABLE_TRUSTZONE */\r
+\r
+#if( configENABLE_MPU == 1 )\r
+ extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;\r
+ extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;\r
+#endif /* configENABLE_MPU */\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief MPU specific constants.\r
+ */\r
+#if( configENABLE_MPU == 1 )\r
+ #define portUSING_MPU_WRAPPERS 1\r
+ #define portPRIVILEGE_BIT ( 0x80000000UL )\r
+#else\r
+ #define portPRIVILEGE_BIT ( 0x0UL )\r
+#endif /* configENABLE_MPU */\r
+\r
+\r
+/* MPU regions. */\r
+#define portPRIVILEGED_FLASH_REGION ( 0UL )\r
+#define portUNPRIVILEGED_FLASH_REGION ( 1UL )\r
+#define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL )\r
+#define portPRIVILEGED_RAM_REGION ( 3UL )\r
+#define portSTACK_REGION ( 4UL )\r
+#define portFIRST_CONFIGURABLE_REGION ( 5UL )\r
+#define portLAST_CONFIGURABLE_REGION ( 7UL )\r
+#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )\r
+#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */\r
+\r
+/* Device memory attributes used in MPU_MAIR registers.\r
+ *\r
+ * 8-bit values encoded as follows:\r
+ * Bit[7:4] - 0000 - Device Memory\r
+ * Bit[3:2] - 00 --> Device-nGnRnE\r
+ * 01 --> Device-nGnRE\r
+ * 10 --> Device-nGRE\r
+ * 11 --> Device-GRE\r
+ * Bit[1:0] - 00, Reserved.\r
+ */\r
+#define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */\r
+#define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */\r
+#define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */\r
+#define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */\r
+\r
+/* Normal memory attributes used in MPU_MAIR registers. */\r
+#define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */\r
+#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */\r
+\r
+/* Attributes used in MPU_RBAR registers. */\r
+#define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL )\r
+#define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL )\r
+#define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL )\r
+\r
+#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL )\r
+#define portMPU_REGION_READ_WRITE ( 1UL << 1UL )\r
+#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL )\r
+#define portMPU_REGION_READ_ONLY ( 3UL << 1UL )\r
+\r
+#define portMPU_REGION_EXECUTE_NEVER ( 1UL )\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Settings to define an MPU region.\r
+ */\r
+typedef struct MPURegionSettings\r
+{\r
+ uint32_t ulRBAR; /**< RBAR for the region. */\r
+ uint32_t ulRLAR; /**< RLAR for the region. */\r
+} MPURegionSettings_t;\r
+\r
+/**\r
+ * @brief MPU settings as stored in the TCB.\r
+ */\r
+typedef struct MPU_SETTINGS\r
+{\r
+ uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */\r
+ MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */\r
+} xMPU_SETTINGS;\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief SVC numbers.\r
+ */\r
+#define portSVC_ALLOCATE_SECURE_CONTEXT 0\r
+#define portSVC_FREE_SECURE_CONTEXT 1\r
+#define portSVC_START_SCHEDULER 2\r
+#define portSVC_RAISE_PRIVILEGE 3\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Scheduler utilities.\r
+ */\r
+#define portYIELD() vPortYield()\r
+#define portNVIC_INT_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000ed04 ) )\r
+#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )\r
+#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT\r
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Critical section management.\r
+ */\r
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMaskFromISR()\r
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vClearInterruptMaskFromISR( x )\r
+#define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" )\r
+#define portENABLE_INTERRUPTS() __asm volatile ( " cpsie i " ::: "memory" )\r
+#define portENTER_CRITICAL() vPortEnterCritical()\r
+#define portEXIT_CRITICAL() vPortExitCritical()\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Task function macros as described on the FreeRTOS.org WEB site.\r
+ */\r
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
+/*-----------------------------------------------------------*/\r
+\r
+#if( configENABLE_TRUSTZONE == 1 )\r
+ /**\r
+ * @brief Allocate a secure context for the task.\r
+ *\r
+ * Tasks are not created with a secure context. Any task that is going to call\r
+ * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a\r
+ * secure context before it calls any secure function.\r
+ *\r
+ * @param[in] ulSecureStackSize The size of the secure stack to be allocated.\r
+ */\r
+ #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize )\r
+\r
+ /**\r
+ * @brief Called when a task is deleted to delete the task's secure context,\r
+ * if it has one.\r
+ *\r
+ * @param[in] pxTCB The TCB of the task being deleted.\r
+ */\r
+ #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB )\r
+#else\r
+ #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )\r
+ #define portCLEAN_UP_TCB( pxTCB )\r
+#endif /* configENABLE_TRUSTZONE */\r
+/*-----------------------------------------------------------*/\r
+\r
+#if( configENABLE_MPU == 1 )\r
+ /**\r
+ * @brief Checks whether or not the processor is privileged.\r
+ *\r
+ * @return 1 if the processor is already privileged, 0 otherwise.\r
+ */\r
+ #define portIS_PRIVILEGED() xIsPrivileged()\r
+\r
+ /**\r
+ * @brief Raise an SVC request to raise privilege.\r
+ *\r
+ * The SVC handler checks that the SVC was raised from a system call and only\r
+ * then it raises the privilege. If this is called from any other place,\r
+ * the privilege is not raised.\r
+ */\r
+ #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );\r
+\r
+ /**\r
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL\r
+ * register.\r
+ */\r
+ #define portRESET_PRIVILEGE() vResetPrivilege()\r
+#else\r
+ #define portIS_PRIVILEGED()\r
+ #define portRAISE_PRIVILEGE()\r
+ #define portRESET_PRIVILEGE()\r
+#endif /* configENABLE_MPU */\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Barriers.\r
+ */\r
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )\r
+/*-----------------------------------------------------------*/\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* PORTMACRO_H */\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+#ifndef PORTMACRO_H\r
+#define PORTMACRO_H\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Port specific definitions.\r
+ *\r
+ * The settings in this file configure FreeRTOS correctly for the given hardware\r
+ * and compiler.\r
+ *\r
+ * These settings should not be altered.\r
+ *------------------------------------------------------------------------------\r
+ */\r
+\r
+#ifndef configENABLE_FPU\r
+ #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.\r
+#endif /* configENABLE_FPU */\r
+\r
+#ifndef configENABLE_MPU\r
+ #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.\r
+#endif /* configENABLE_MPU */\r
+\r
+#ifndef configENABLE_TRUSTZONE\r
+ #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.\r
+#endif /* configENABLE_TRUSTZONE */\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Type definitions.\r
+ */\r
+#define portCHAR char\r
+#define portFLOAT float\r
+#define portDOUBLE double\r
+#define portLONG long\r
+#define portSHORT short\r
+#define portSTACK_TYPE uint32_t\r
+#define portBASE_TYPE long\r
+\r
+typedef portSTACK_TYPE StackType_t;\r
+typedef long BaseType_t;\r
+typedef unsigned long UBaseType_t;\r
+\r
+#if( configUSE_16_BIT_TICKS == 1 )\r
+ typedef uint16_t TickType_t;\r
+ #define portMAX_DELAY ( TickType_t ) 0xffff\r
+#else\r
+ typedef uint32_t TickType_t;\r
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL\r
+\r
+ /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do\r
+ * not need to be guarded with a critical section. */\r
+ #define portTICK_TYPE_IS_ATOMIC 1\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * Architecture specifics.\r
+ */\r
+#define portARCH_NAME "Cortex-M23"\r
+#define portSTACK_GROWTH ( -1 )\r
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )\r
+#define portBYTE_ALIGNMENT 8\r
+#define portNOP()\r
+#define portINLINE __inline\r
+#ifndef portFORCE_INLINE\r
+ #define portFORCE_INLINE inline __attribute__(( always_inline ))\r
+#endif\r
+#define portHAS_STACK_OVERFLOW_CHECKING 1\r
+#define portDONT_DISCARD __attribute__(( used ))\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Extern declarations.\r
+ */\r
+extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;\r
+\r
+extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;\r
+extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;\r
+\r
+extern uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
+extern void vClearInterruptMaskFromISR( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
+\r
+#if( configENABLE_TRUSTZONE == 1 )\r
+ extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */\r
+ extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;\r
+#endif /* configENABLE_TRUSTZONE */\r
+\r
+#if( configENABLE_MPU == 1 )\r
+ extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;\r
+ extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;\r
+#endif /* configENABLE_MPU */\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief MPU specific constants.\r
+ */\r
+#if( configENABLE_MPU == 1 )\r
+ #define portUSING_MPU_WRAPPERS 1\r
+ #define portPRIVILEGE_BIT ( 0x80000000UL )\r
+#else\r
+ #define portPRIVILEGE_BIT ( 0x0UL )\r
+#endif /* configENABLE_MPU */\r
+\r
+\r
+/* MPU regions. */\r
+#define portPRIVILEGED_FLASH_REGION ( 0UL )\r
+#define portUNPRIVILEGED_FLASH_REGION ( 1UL )\r
+#define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL )\r
+#define portPRIVILEGED_RAM_REGION ( 3UL )\r
+#define portSTACK_REGION ( 4UL )\r
+#define portFIRST_CONFIGURABLE_REGION ( 5UL )\r
+#define portLAST_CONFIGURABLE_REGION ( 7UL )\r
+#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )\r
+#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */\r
+\r
+/* Device memory attributes used in MPU_MAIR registers.\r
+ *\r
+ * 8-bit values encoded as follows:\r
+ * Bit[7:4] - 0000 - Device Memory\r
+ * Bit[3:2] - 00 --> Device-nGnRnE\r
+ * 01 --> Device-nGnRE\r
+ * 10 --> Device-nGRE\r
+ * 11 --> Device-GRE\r
+ * Bit[1:0] - 00, Reserved.\r
+ */\r
+#define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */\r
+#define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */\r
+#define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */\r
+#define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */\r
+\r
+/* Normal memory attributes used in MPU_MAIR registers. */\r
+#define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */\r
+#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */\r
+\r
+/* Attributes used in MPU_RBAR registers. */\r
+#define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL )\r
+#define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL )\r
+#define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL )\r
+\r
+#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL )\r
+#define portMPU_REGION_READ_WRITE ( 1UL << 1UL )\r
+#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL )\r
+#define portMPU_REGION_READ_ONLY ( 3UL << 1UL )\r
+\r
+#define portMPU_REGION_EXECUTE_NEVER ( 1UL )\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Settings to define an MPU region.\r
+ */\r
+typedef struct MPURegionSettings\r
+{\r
+ uint32_t ulRBAR; /**< RBAR for the region. */\r
+ uint32_t ulRLAR; /**< RLAR for the region. */\r
+} MPURegionSettings_t;\r
+\r
+/**\r
+ * @brief MPU settings as stored in the TCB.\r
+ */\r
+typedef struct MPU_SETTINGS\r
+{\r
+ uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */\r
+ MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */\r
+} xMPU_SETTINGS;\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief SVC numbers.\r
+ */\r
+#define portSVC_ALLOCATE_SECURE_CONTEXT 0\r
+#define portSVC_FREE_SECURE_CONTEXT 1\r
+#define portSVC_START_SCHEDULER 2\r
+#define portSVC_RAISE_PRIVILEGE 3\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Scheduler utilities.\r
+ */\r
+#define portYIELD() vPortYield()\r
+#define portNVIC_INT_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000ed04 ) )\r
+#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )\r
+#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT\r
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Critical section management.\r
+ */\r
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMaskFromISR()\r
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vClearInterruptMaskFromISR( x )\r
+#define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" )\r
+#define portENABLE_INTERRUPTS() __asm volatile ( " cpsie i " ::: "memory" )\r
+#define portENTER_CRITICAL() vPortEnterCritical()\r
+#define portEXIT_CRITICAL() vPortExitCritical()\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Task function macros as described on the FreeRTOS.org WEB site.\r
+ */\r
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
+/*-----------------------------------------------------------*/\r
+\r
+#if( configENABLE_TRUSTZONE == 1 )\r
+ /**\r
+ * @brief Allocate a secure context for the task.\r
+ *\r
+ * Tasks are not created with a secure context. Any task that is going to call\r
+ * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a\r
+ * secure context before it calls any secure function.\r
+ *\r
+ * @param[in] ulSecureStackSize The size of the secure stack to be allocated.\r
+ */\r
+ #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize )\r
+\r
+ /**\r
+ * @brief Called when a task is deleted to delete the task's secure context,\r
+ * if it has one.\r
+ *\r
+ * @param[in] pxTCB The TCB of the task being deleted.\r
+ */\r
+ #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB )\r
+#else\r
+ #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )\r
+ #define portCLEAN_UP_TCB( pxTCB )\r
+#endif /* configENABLE_TRUSTZONE */\r
+/*-----------------------------------------------------------*/\r
+\r
+#if( configENABLE_MPU == 1 )\r
+ /**\r
+ * @brief Checks whether or not the processor is privileged.\r
+ *\r
+ * @return 1 if the processor is already privileged, 0 otherwise.\r
+ */\r
+ #define portIS_PRIVILEGED() xIsPrivileged()\r
+\r
+ /**\r
+ * @brief Raise an SVC request to raise privilege.\r
+ *\r
+ * The SVC handler checks that the SVC was raised from a system call and only\r
+ * then it raises the privilege. If this is called from any other place,\r
+ * the privilege is not raised.\r
+ */\r
+ #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );\r
+\r
+ /**\r
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL\r
+ * register.\r
+ */\r
+ #define portRESET_PRIVILEGE() vResetPrivilege()\r
+#else\r
+ #define portIS_PRIVILEGED()\r
+ #define portRAISE_PRIVILEGE()\r
+ #define portRESET_PRIVILEGE()\r
+#endif /* configENABLE_MPU */\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Barriers.\r
+ */\r
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )\r
+/*-----------------------------------------------------------*/\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* PORTMACRO_H */\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+#ifndef PORTMACRO_H\r
+#define PORTMACRO_H\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Port specific definitions.\r
+ *\r
+ * The settings in this file configure FreeRTOS correctly for the given hardware\r
+ * and compiler.\r
+ *\r
+ * These settings should not be altered.\r
+ *------------------------------------------------------------------------------\r
+ */\r
+\r
+#ifndef configENABLE_FPU\r
+ #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.\r
+#endif /* configENABLE_FPU */\r
+\r
+#ifndef configENABLE_MPU\r
+ #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.\r
+#endif /* configENABLE_MPU */\r
+\r
+#ifndef configENABLE_TRUSTZONE\r
+ #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.\r
+#endif /* configENABLE_TRUSTZONE */\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Type definitions.\r
+ */\r
+#define portCHAR char\r
+#define portFLOAT float\r
+#define portDOUBLE double\r
+#define portLONG long\r
+#define portSHORT short\r
+#define portSTACK_TYPE uint32_t\r
+#define portBASE_TYPE long\r
+\r
+typedef portSTACK_TYPE StackType_t;\r
+typedef long BaseType_t;\r
+typedef unsigned long UBaseType_t;\r
+\r
+#if( configUSE_16_BIT_TICKS == 1 )\r
+ typedef uint16_t TickType_t;\r
+ #define portMAX_DELAY ( TickType_t ) 0xffff\r
+#else\r
+ typedef uint32_t TickType_t;\r
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL\r
+\r
+ /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do\r
+ * not need to be guarded with a critical section. */\r
+ #define portTICK_TYPE_IS_ATOMIC 1\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * Architecture specifics.\r
+ */\r
+#define portARCH_NAME "Cortex-M33"\r
+#define portSTACK_GROWTH ( -1 )\r
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )\r
+#define portBYTE_ALIGNMENT 8\r
+#define portNOP()\r
+#define portINLINE __inline\r
+#ifndef portFORCE_INLINE\r
+ #define portFORCE_INLINE inline __attribute__(( always_inline ))\r
+#endif\r
+#define portHAS_STACK_OVERFLOW_CHECKING 1\r
+#define portDONT_DISCARD __attribute__(( used ))\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Extern declarations.\r
+ */\r
+extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;\r
+\r
+extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;\r
+extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;\r
+\r
+extern uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
+extern void vClearInterruptMaskFromISR( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
+\r
+#if( configENABLE_TRUSTZONE == 1 )\r
+ extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */\r
+ extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;\r
+#endif /* configENABLE_TRUSTZONE */\r
+\r
+#if( configENABLE_MPU == 1 )\r
+ extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;\r
+ extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;\r
+#endif /* configENABLE_MPU */\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief MPU specific constants.\r
+ */\r
+#if( configENABLE_MPU == 1 )\r
+ #define portUSING_MPU_WRAPPERS 1\r
+ #define portPRIVILEGE_BIT ( 0x80000000UL )\r
+#else\r
+ #define portPRIVILEGE_BIT ( 0x0UL )\r
+#endif /* configENABLE_MPU */\r
+\r
+\r
+/* MPU regions. */\r
+#define portPRIVILEGED_FLASH_REGION ( 0UL )\r
+#define portUNPRIVILEGED_FLASH_REGION ( 1UL )\r
+#define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL )\r
+#define portPRIVILEGED_RAM_REGION ( 3UL )\r
+#define portSTACK_REGION ( 4UL )\r
+#define portFIRST_CONFIGURABLE_REGION ( 5UL )\r
+#define portLAST_CONFIGURABLE_REGION ( 7UL )\r
+#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )\r
+#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */\r
+\r
+/* Device memory attributes used in MPU_MAIR registers.\r
+ *\r
+ * 8-bit values encoded as follows:\r
+ * Bit[7:4] - 0000 - Device Memory\r
+ * Bit[3:2] - 00 --> Device-nGnRnE\r
+ * 01 --> Device-nGnRE\r
+ * 10 --> Device-nGRE\r
+ * 11 --> Device-GRE\r
+ * Bit[1:0] - 00, Reserved.\r
+ */\r
+#define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */\r
+#define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */\r
+#define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */\r
+#define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */\r
+\r
+/* Normal memory attributes used in MPU_MAIR registers. */\r
+#define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */\r
+#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */\r
+\r
+/* Attributes used in MPU_RBAR registers. */\r
+#define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL )\r
+#define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL )\r
+#define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL )\r
+\r
+#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL )\r
+#define portMPU_REGION_READ_WRITE ( 1UL << 1UL )\r
+#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL )\r
+#define portMPU_REGION_READ_ONLY ( 3UL << 1UL )\r
+\r
+#define portMPU_REGION_EXECUTE_NEVER ( 1UL )\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Settings to define an MPU region.\r
+ */\r
+typedef struct MPURegionSettings\r
+{\r
+ uint32_t ulRBAR; /**< RBAR for the region. */\r
+ uint32_t ulRLAR; /**< RLAR for the region. */\r
+} MPURegionSettings_t;\r
+\r
+/**\r
+ * @brief MPU settings as stored in the TCB.\r
+ */\r
+typedef struct MPU_SETTINGS\r
+{\r
+ uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */\r
+ MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */\r
+} xMPU_SETTINGS;\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief SVC numbers.\r
+ */\r
+#define portSVC_ALLOCATE_SECURE_CONTEXT 0\r
+#define portSVC_FREE_SECURE_CONTEXT 1\r
+#define portSVC_START_SCHEDULER 2\r
+#define portSVC_RAISE_PRIVILEGE 3\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Scheduler utilities.\r
+ */\r
+#define portYIELD() vPortYield()\r
+#define portNVIC_INT_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000ed04 ) )\r
+#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )\r
+#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT\r
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Critical section management.\r
+ */\r
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMaskFromISR()\r
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vClearInterruptMaskFromISR( x )\r
+#define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" )\r
+#define portENABLE_INTERRUPTS() __asm volatile ( " cpsie i " ::: "memory" )\r
+#define portENTER_CRITICAL() vPortEnterCritical()\r
+#define portEXIT_CRITICAL() vPortExitCritical()\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Task function macros as described on the FreeRTOS.org WEB site.\r
+ */\r
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
+/*-----------------------------------------------------------*/\r
+\r
+#if( configENABLE_TRUSTZONE == 1 )\r
+ /**\r
+ * @brief Allocate a secure context for the task.\r
+ *\r
+ * Tasks are not created with a secure context. Any task that is going to call\r
+ * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a\r
+ * secure context before it calls any secure function.\r
+ *\r
+ * @param[in] ulSecureStackSize The size of the secure stack to be allocated.\r
+ */\r
+ #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize )\r
+\r
+ /**\r
+ * @brief Called when a task is deleted to delete the task's secure context,\r
+ * if it has one.\r
+ *\r
+ * @param[in] pxTCB The TCB of the task being deleted.\r
+ */\r
+ #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB )\r
+#else\r
+ #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )\r
+ #define portCLEAN_UP_TCB( pxTCB )\r
+#endif /* configENABLE_TRUSTZONE */\r
+/*-----------------------------------------------------------*/\r
+\r
+#if( configENABLE_MPU == 1 )\r
+ /**\r
+ * @brief Checks whether or not the processor is privileged.\r
+ *\r
+ * @return 1 if the processor is already privileged, 0 otherwise.\r
+ */\r
+ #define portIS_PRIVILEGED() xIsPrivileged()\r
+\r
+ /**\r
+ * @brief Raise an SVC request to raise privilege.\r
+ *\r
+ * The SVC handler checks that the SVC was raised from a system call and only\r
+ * then it raises the privilege. If this is called from any other place,\r
+ * the privilege is not raised.\r
+ */\r
+ #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );\r
+\r
+ /**\r
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL\r
+ * register.\r
+ */\r
+ #define portRESET_PRIVILEGE() vResetPrivilege()\r
+#else\r
+ #define portIS_PRIVILEGED()\r
+ #define portRAISE_PRIVILEGE()\r
+ #define portRESET_PRIVILEGE()\r
+#endif /* configENABLE_MPU */\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Barriers.\r
+ */\r
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )\r
+/*-----------------------------------------------------------*/\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* PORTMACRO_H */\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+#ifndef PORTMACRO_H\r
+#define PORTMACRO_H\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Port specific definitions.\r
+ *\r
+ * The settings in this file configure FreeRTOS correctly for the given hardware\r
+ * and compiler.\r
+ *\r
+ * These settings should not be altered.\r
+ *------------------------------------------------------------------------------\r
+ */\r
+\r
+#ifndef configENABLE_FPU\r
+ #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.\r
+#endif /* configENABLE_FPU */\r
+\r
+#ifndef configENABLE_MPU\r
+ #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.\r
+#endif /* configENABLE_MPU */\r
+\r
+#ifndef configENABLE_TRUSTZONE\r
+ #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.\r
+#endif /* configENABLE_TRUSTZONE */\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Type definitions.\r
+ */\r
+#define portCHAR char\r
+#define portFLOAT float\r
+#define portDOUBLE double\r
+#define portLONG long\r
+#define portSHORT short\r
+#define portSTACK_TYPE uint32_t\r
+#define portBASE_TYPE long\r
+\r
+typedef portSTACK_TYPE StackType_t;\r
+typedef long BaseType_t;\r
+typedef unsigned long UBaseType_t;\r
+\r
+#if( configUSE_16_BIT_TICKS == 1 )\r
+ typedef uint16_t TickType_t;\r
+ #define portMAX_DELAY ( TickType_t ) 0xffff\r
+#else\r
+ typedef uint32_t TickType_t;\r
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL\r
+\r
+ /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do\r
+ * not need to be guarded with a critical section. */\r
+ #define portTICK_TYPE_IS_ATOMIC 1\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * Architecture specifics.\r
+ */\r
+#define portARCH_NAME "Cortex-M33"\r
+#define portSTACK_GROWTH ( -1 )\r
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )\r
+#define portBYTE_ALIGNMENT 8\r
+#define portNOP()\r
+#define portINLINE __inline\r
+#ifndef portFORCE_INLINE\r
+ #define portFORCE_INLINE inline __attribute__(( always_inline ))\r
+#endif\r
+#define portHAS_STACK_OVERFLOW_CHECKING 1\r
+#define portDONT_DISCARD __attribute__(( used ))\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Extern declarations.\r
+ */\r
+extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;\r
+\r
+extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;\r
+extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;\r
+\r
+extern uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
+extern void vClearInterruptMaskFromISR( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
+\r
+#if( configENABLE_TRUSTZONE == 1 )\r
+ extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */\r
+ extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;\r
+#endif /* configENABLE_TRUSTZONE */\r
+\r
+#if( configENABLE_MPU == 1 )\r
+ extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;\r
+ extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;\r
+#endif /* configENABLE_MPU */\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief MPU specific constants.\r
+ */\r
+#if( configENABLE_MPU == 1 )\r
+ #define portUSING_MPU_WRAPPERS 1\r
+ #define portPRIVILEGE_BIT ( 0x80000000UL )\r
+#else\r
+ #define portPRIVILEGE_BIT ( 0x0UL )\r
+#endif /* configENABLE_MPU */\r
+\r
+\r
+/* MPU regions. */\r
+#define portPRIVILEGED_FLASH_REGION ( 0UL )\r
+#define portUNPRIVILEGED_FLASH_REGION ( 1UL )\r
+#define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL )\r
+#define portPRIVILEGED_RAM_REGION ( 3UL )\r
+#define portSTACK_REGION ( 4UL )\r
+#define portFIRST_CONFIGURABLE_REGION ( 5UL )\r
+#define portLAST_CONFIGURABLE_REGION ( 7UL )\r
+#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )\r
+#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */\r
+\r
+/* Device memory attributes used in MPU_MAIR registers.\r
+ *\r
+ * 8-bit values encoded as follows:\r
+ * Bit[7:4] - 0000 - Device Memory\r
+ * Bit[3:2] - 00 --> Device-nGnRnE\r
+ * 01 --> Device-nGnRE\r
+ * 10 --> Device-nGRE\r
+ * 11 --> Device-GRE\r
+ * Bit[1:0] - 00, Reserved.\r
+ */\r
+#define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */\r
+#define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */\r
+#define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */\r
+#define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */\r
+\r
+/* Normal memory attributes used in MPU_MAIR registers. */\r
+#define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */\r
+#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */\r
+\r
+/* Attributes used in MPU_RBAR registers. */\r
+#define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL )\r
+#define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL )\r
+#define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL )\r
+\r
+#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL )\r
+#define portMPU_REGION_READ_WRITE ( 1UL << 1UL )\r
+#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL )\r
+#define portMPU_REGION_READ_ONLY ( 3UL << 1UL )\r
+\r
+#define portMPU_REGION_EXECUTE_NEVER ( 1UL )\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Settings to define an MPU region.\r
+ */\r
+typedef struct MPURegionSettings\r
+{\r
+ uint32_t ulRBAR; /**< RBAR for the region. */\r
+ uint32_t ulRLAR; /**< RLAR for the region. */\r
+} MPURegionSettings_t;\r
+\r
+/**\r
+ * @brief MPU settings as stored in the TCB.\r
+ */\r
+typedef struct MPU_SETTINGS\r
+{\r
+ uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */\r
+ MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */\r
+} xMPU_SETTINGS;\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief SVC numbers.\r
+ */\r
+#define portSVC_ALLOCATE_SECURE_CONTEXT 0\r
+#define portSVC_FREE_SECURE_CONTEXT 1\r
+#define portSVC_START_SCHEDULER 2\r
+#define portSVC_RAISE_PRIVILEGE 3\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Scheduler utilities.\r
+ */\r
+#define portYIELD() vPortYield()\r
+#define portNVIC_INT_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000ed04 ) )\r
+#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )\r
+#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT\r
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Critical section management.\r
+ */\r
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMaskFromISR()\r
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vClearInterruptMaskFromISR( x )\r
+#define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" )\r
+#define portENABLE_INTERRUPTS() __asm volatile ( " cpsie i " ::: "memory" )\r
+#define portENTER_CRITICAL() vPortEnterCritical()\r
+#define portEXIT_CRITICAL() vPortExitCritical()\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Task function macros as described on the FreeRTOS.org WEB site.\r
+ */\r
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
+/*-----------------------------------------------------------*/\r
+\r
+#if( configENABLE_TRUSTZONE == 1 )\r
+ /**\r
+ * @brief Allocate a secure context for the task.\r
+ *\r
+ * Tasks are not created with a secure context. Any task that is going to call\r
+ * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a\r
+ * secure context before it calls any secure function.\r
+ *\r
+ * @param[in] ulSecureStackSize The size of the secure stack to be allocated.\r
+ */\r
+ #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize )\r
+\r
+ /**\r
+ * @brief Called when a task is deleted to delete the task's secure context,\r
+ * if it has one.\r
+ *\r
+ * @param[in] pxTCB The TCB of the task being deleted.\r
+ */\r
+ #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB )\r
+#else\r
+ #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )\r
+ #define portCLEAN_UP_TCB( pxTCB )\r
+#endif /* configENABLE_TRUSTZONE */\r
+/*-----------------------------------------------------------*/\r
+\r
+#if( configENABLE_MPU == 1 )\r
+ /**\r
+ * @brief Checks whether or not the processor is privileged.\r
+ *\r
+ * @return 1 if the processor is already privileged, 0 otherwise.\r
+ */\r
+ #define portIS_PRIVILEGED() xIsPrivileged()\r
+\r
+ /**\r
+ * @brief Raise an SVC request to raise privilege.\r
+ *\r
+ * The SVC handler checks that the SVC was raised from a system call and only\r
+ * then it raises the privilege. If this is called from any other place,\r
+ * the privilege is not raised.\r
+ */\r
+ #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );\r
+\r
+ /**\r
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL\r
+ * register.\r
+ */\r
+ #define portRESET_PRIVILEGE() vResetPrivilege()\r
+#else\r
+ #define portIS_PRIVILEGED()\r
+ #define portRAISE_PRIVILEGE()\r
+ #define portRESET_PRIVILEGE()\r
+#endif /* configENABLE_MPU */\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Barriers.\r
+ */\r
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )\r
+/*-----------------------------------------------------------*/\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* PORTMACRO_H */\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+#ifndef PORTMACRO_H\r
+#define PORTMACRO_H\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Port specific definitions.\r
+ *\r
+ * The settings in this file configure FreeRTOS correctly for the given hardware\r
+ * and compiler.\r
+ *\r
+ * These settings should not be altered.\r
+ *------------------------------------------------------------------------------\r
+ */\r
+\r
+#ifndef configENABLE_FPU\r
+ #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.\r
+#endif /* configENABLE_FPU */\r
+\r
+#ifndef configENABLE_MPU\r
+ #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.\r
+#endif /* configENABLE_MPU */\r
+\r
+#ifndef configENABLE_TRUSTZONE\r
+ #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.\r
+#endif /* configENABLE_TRUSTZONE */\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Type definitions.\r
+ */\r
+#define portCHAR char\r
+#define portFLOAT float\r
+#define portDOUBLE double\r
+#define portLONG long\r
+#define portSHORT short\r
+#define portSTACK_TYPE uint32_t\r
+#define portBASE_TYPE long\r
+\r
+typedef portSTACK_TYPE StackType_t;\r
+typedef long BaseType_t;\r
+typedef unsigned long UBaseType_t;\r
+\r
+#if( configUSE_16_BIT_TICKS == 1 )\r
+ typedef uint16_t TickType_t;\r
+ #define portMAX_DELAY ( TickType_t ) 0xffff\r
+#else\r
+ typedef uint32_t TickType_t;\r
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL\r
+\r
+ /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do\r
+ * not need to be guarded with a critical section. */\r
+ #define portTICK_TYPE_IS_ATOMIC 1\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * Architecture specifics.\r
+ */\r
+#define portARCH_NAME "Cortex-M23"\r
+#define portSTACK_GROWTH ( -1 )\r
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )\r
+#define portBYTE_ALIGNMENT 8\r
+#define portNOP()\r
+#define portINLINE __inline\r
+#ifndef portFORCE_INLINE\r
+ #define portFORCE_INLINE inline __attribute__(( always_inline ))\r
+#endif\r
+#define portHAS_STACK_OVERFLOW_CHECKING 1\r
+#define portDONT_DISCARD __root\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Extern declarations.\r
+ */\r
+extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;\r
+\r
+extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;\r
+extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;\r
+\r
+extern uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
+extern void vClearInterruptMaskFromISR( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
+\r
+#if( configENABLE_TRUSTZONE == 1 )\r
+ extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */\r
+ extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;\r
+#endif /* configENABLE_TRUSTZONE */\r
+\r
+#if( configENABLE_MPU == 1 )\r
+ extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;\r
+ extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;\r
+#endif /* configENABLE_MPU */\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief MPU specific constants.\r
+ */\r
+#if( configENABLE_MPU == 1 )\r
+ #define portUSING_MPU_WRAPPERS 1\r
+ #define portPRIVILEGE_BIT ( 0x80000000UL )\r
+#else\r
+ #define portPRIVILEGE_BIT ( 0x0UL )\r
+#endif /* configENABLE_MPU */\r
+\r
+\r
+/* MPU regions. */\r
+#define portPRIVILEGED_FLASH_REGION ( 0UL )\r
+#define portUNPRIVILEGED_FLASH_REGION ( 1UL )\r
+#define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL )\r
+#define portPRIVILEGED_RAM_REGION ( 3UL )\r
+#define portSTACK_REGION ( 4UL )\r
+#define portFIRST_CONFIGURABLE_REGION ( 5UL )\r
+#define portLAST_CONFIGURABLE_REGION ( 7UL )\r
+#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )\r
+#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */\r
+\r
+/* Device memory attributes used in MPU_MAIR registers.\r
+ *\r
+ * 8-bit values encoded as follows:\r
+ * Bit[7:4] - 0000 - Device Memory\r
+ * Bit[3:2] - 00 --> Device-nGnRnE\r
+ * 01 --> Device-nGnRE\r
+ * 10 --> Device-nGRE\r
+ * 11 --> Device-GRE\r
+ * Bit[1:0] - 00, Reserved.\r
+ */\r
+#define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */\r
+#define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */\r
+#define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */\r
+#define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */\r
+\r
+/* Normal memory attributes used in MPU_MAIR registers. */\r
+#define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */\r
+#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */\r
+\r
+/* Attributes used in MPU_RBAR registers. */\r
+#define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL )\r
+#define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL )\r
+#define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL )\r
+\r
+#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL )\r
+#define portMPU_REGION_READ_WRITE ( 1UL << 1UL )\r
+#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL )\r
+#define portMPU_REGION_READ_ONLY ( 3UL << 1UL )\r
+\r
+#define portMPU_REGION_EXECUTE_NEVER ( 1UL )\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Settings to define an MPU region.\r
+ */\r
+typedef struct MPURegionSettings\r
+{\r
+ uint32_t ulRBAR; /**< RBAR for the region. */\r
+ uint32_t ulRLAR; /**< RLAR for the region. */\r
+} MPURegionSettings_t;\r
+\r
+/**\r
+ * @brief MPU settings as stored in the TCB.\r
+ */\r
+typedef struct MPU_SETTINGS\r
+{\r
+ uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */\r
+ MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */\r
+} xMPU_SETTINGS;\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief SVC numbers.\r
+ */\r
+#define portSVC_ALLOCATE_SECURE_CONTEXT 0\r
+#define portSVC_FREE_SECURE_CONTEXT 1\r
+#define portSVC_START_SCHEDULER 2\r
+#define portSVC_RAISE_PRIVILEGE 3\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Scheduler utilities.\r
+ */\r
+#define portYIELD() vPortYield()\r
+#define portNVIC_INT_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000ed04 ) )\r
+#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )\r
+#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT\r
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Critical section management.\r
+ */\r
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMaskFromISR()\r
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vClearInterruptMaskFromISR( x )\r
+#define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" )\r
+#define portENABLE_INTERRUPTS() __asm volatile ( " cpsie i " ::: "memory" )\r
+#define portENTER_CRITICAL() vPortEnterCritical()\r
+#define portEXIT_CRITICAL() vPortExitCritical()\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Task function macros as described on the FreeRTOS.org WEB site.\r
+ */\r
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
+/*-----------------------------------------------------------*/\r
+\r
+#if( configENABLE_TRUSTZONE == 1 )\r
+ /**\r
+ * @brief Allocate a secure context for the task.\r
+ *\r
+ * Tasks are not created with a secure context. Any task that is going to call\r
+ * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a\r
+ * secure context before it calls any secure function.\r
+ *\r
+ * @param[in] ulSecureStackSize The size of the secure stack to be allocated.\r
+ */\r
+ #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize )\r
+\r
+ /**\r
+ * @brief Called when a task is deleted to delete the task's secure context,\r
+ * if it has one.\r
+ *\r
+ * @param[in] pxTCB The TCB of the task being deleted.\r
+ */\r
+ #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB )\r
+#else\r
+ #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )\r
+ #define portCLEAN_UP_TCB( pxTCB )\r
+#endif /* configENABLE_TRUSTZONE */\r
+/*-----------------------------------------------------------*/\r
+\r
+#if( configENABLE_MPU == 1 )\r
+ /**\r
+ * @brief Checks whether or not the processor is privileged.\r
+ *\r
+ * @return 1 if the processor is already privileged, 0 otherwise.\r
+ */\r
+ #define portIS_PRIVILEGED() xIsPrivileged()\r
+\r
+ /**\r
+ * @brief Raise an SVC request to raise privilege.\r
+ *\r
+ * The SVC handler checks that the SVC was raised from a system call and only\r
+ * then it raises the privilege. If this is called from any other place,\r
+ * the privilege is not raised.\r
+ */\r
+ #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );\r
+\r
+ /**\r
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL\r
+ * register.\r
+ */\r
+ #define portRESET_PRIVILEGE() vResetPrivilege()\r
+#else\r
+ #define portIS_PRIVILEGED()\r
+ #define portRAISE_PRIVILEGE()\r
+ #define portRESET_PRIVILEGE()\r
+#endif /* configENABLE_MPU */\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Barriers.\r
+ */\r
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )\r
+/*-----------------------------------------------------------*/\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* PORTMACRO_H */\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+#ifndef PORTMACRO_H\r
+#define PORTMACRO_H\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Port specific definitions.\r
+ *\r
+ * The settings in this file configure FreeRTOS correctly for the given hardware\r
+ * and compiler.\r
+ *\r
+ * These settings should not be altered.\r
+ *------------------------------------------------------------------------------\r
+ */\r
+\r
+#ifndef configENABLE_FPU\r
+ #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.\r
+#endif /* configENABLE_FPU */\r
+\r
+#ifndef configENABLE_MPU\r
+ #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.\r
+#endif /* configENABLE_MPU */\r
+\r
+#ifndef configENABLE_TRUSTZONE\r
+ #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.\r
+#endif /* configENABLE_TRUSTZONE */\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Type definitions.\r
+ */\r
+#define portCHAR char\r
+#define portFLOAT float\r
+#define portDOUBLE double\r
+#define portLONG long\r
+#define portSHORT short\r
+#define portSTACK_TYPE uint32_t\r
+#define portBASE_TYPE long\r
+\r
+typedef portSTACK_TYPE StackType_t;\r
+typedef long BaseType_t;\r
+typedef unsigned long UBaseType_t;\r
+\r
+#if( configUSE_16_BIT_TICKS == 1 )\r
+ typedef uint16_t TickType_t;\r
+ #define portMAX_DELAY ( TickType_t ) 0xffff\r
+#else\r
+ typedef uint32_t TickType_t;\r
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL\r
+\r
+ /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do\r
+ * not need to be guarded with a critical section. */\r
+ #define portTICK_TYPE_IS_ATOMIC 1\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * Architecture specifics.\r
+ */\r
+#define portARCH_NAME "Cortex-M23"\r
+#define portSTACK_GROWTH ( -1 )\r
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )\r
+#define portBYTE_ALIGNMENT 8\r
+#define portNOP()\r
+#define portINLINE __inline\r
+#ifndef portFORCE_INLINE\r
+ #define portFORCE_INLINE inline __attribute__(( always_inline ))\r
+#endif\r
+#define portHAS_STACK_OVERFLOW_CHECKING 1\r
+#define portDONT_DISCARD __root\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Extern declarations.\r
+ */\r
+extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;\r
+\r
+extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;\r
+extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;\r
+\r
+extern uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
+extern void vClearInterruptMaskFromISR( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
+\r
+#if( configENABLE_TRUSTZONE == 1 )\r
+ extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */\r
+ extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;\r
+#endif /* configENABLE_TRUSTZONE */\r
+\r
+#if( configENABLE_MPU == 1 )\r
+ extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;\r
+ extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;\r
+#endif /* configENABLE_MPU */\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief MPU specific constants.\r
+ */\r
+#if( configENABLE_MPU == 1 )\r
+ #define portUSING_MPU_WRAPPERS 1\r
+ #define portPRIVILEGE_BIT ( 0x80000000UL )\r
+#else\r
+ #define portPRIVILEGE_BIT ( 0x0UL )\r
+#endif /* configENABLE_MPU */\r
+\r
+\r
+/* MPU regions. */\r
+#define portPRIVILEGED_FLASH_REGION ( 0UL )\r
+#define portUNPRIVILEGED_FLASH_REGION ( 1UL )\r
+#define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL )\r
+#define portPRIVILEGED_RAM_REGION ( 3UL )\r
+#define portSTACK_REGION ( 4UL )\r
+#define portFIRST_CONFIGURABLE_REGION ( 5UL )\r
+#define portLAST_CONFIGURABLE_REGION ( 7UL )\r
+#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )\r
+#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */\r
+\r
+/* Device memory attributes used in MPU_MAIR registers.\r
+ *\r
+ * 8-bit values encoded as follows:\r
+ * Bit[7:4] - 0000 - Device Memory\r
+ * Bit[3:2] - 00 --> Device-nGnRnE\r
+ * 01 --> Device-nGnRE\r
+ * 10 --> Device-nGRE\r
+ * 11 --> Device-GRE\r
+ * Bit[1:0] - 00, Reserved.\r
+ */\r
+#define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */\r
+#define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */\r
+#define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */\r
+#define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */\r
+\r
+/* Normal memory attributes used in MPU_MAIR registers. */\r
+#define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */\r
+#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */\r
+\r
+/* Attributes used in MPU_RBAR registers. */\r
+#define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL )\r
+#define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL )\r
+#define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL )\r
+\r
+#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL )\r
+#define portMPU_REGION_READ_WRITE ( 1UL << 1UL )\r
+#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL )\r
+#define portMPU_REGION_READ_ONLY ( 3UL << 1UL )\r
+\r
+#define portMPU_REGION_EXECUTE_NEVER ( 1UL )\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Settings to define an MPU region.\r
+ */\r
+typedef struct MPURegionSettings\r
+{\r
+ uint32_t ulRBAR; /**< RBAR for the region. */\r
+ uint32_t ulRLAR; /**< RLAR for the region. */\r
+} MPURegionSettings_t;\r
+\r
+/**\r
+ * @brief MPU settings as stored in the TCB.\r
+ */\r
+typedef struct MPU_SETTINGS\r
+{\r
+ uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */\r
+ MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */\r
+} xMPU_SETTINGS;\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief SVC numbers.\r
+ */\r
+#define portSVC_ALLOCATE_SECURE_CONTEXT 0\r
+#define portSVC_FREE_SECURE_CONTEXT 1\r
+#define portSVC_START_SCHEDULER 2\r
+#define portSVC_RAISE_PRIVILEGE 3\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Scheduler utilities.\r
+ */\r
+#define portYIELD() vPortYield()\r
+#define portNVIC_INT_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000ed04 ) )\r
+#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )\r
+#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT\r
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Critical section management.\r
+ */\r
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMaskFromISR()\r
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vClearInterruptMaskFromISR( x )\r
+#define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" )\r
+#define portENABLE_INTERRUPTS() __asm volatile ( " cpsie i " ::: "memory" )\r
+#define portENTER_CRITICAL() vPortEnterCritical()\r
+#define portEXIT_CRITICAL() vPortExitCritical()\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Task function macros as described on the FreeRTOS.org WEB site.\r
+ */\r
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
+/*-----------------------------------------------------------*/\r
+\r
+#if( configENABLE_TRUSTZONE == 1 )\r
+ /**\r
+ * @brief Allocate a secure context for the task.\r
+ *\r
+ * Tasks are not created with a secure context. Any task that is going to call\r
+ * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a\r
+ * secure context before it calls any secure function.\r
+ *\r
+ * @param[in] ulSecureStackSize The size of the secure stack to be allocated.\r
+ */\r
+ #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize )\r
+\r
+ /**\r
+ * @brief Called when a task is deleted to delete the task's secure context,\r
+ * if it has one.\r
+ *\r
+ * @param[in] pxTCB The TCB of the task being deleted.\r
+ */\r
+ #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB )\r
+#else\r
+ #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )\r
+ #define portCLEAN_UP_TCB( pxTCB )\r
+#endif /* configENABLE_TRUSTZONE */\r
+/*-----------------------------------------------------------*/\r
+\r
+#if( configENABLE_MPU == 1 )\r
+ /**\r
+ * @brief Checks whether or not the processor is privileged.\r
+ *\r
+ * @return 1 if the processor is already privileged, 0 otherwise.\r
+ */\r
+ #define portIS_PRIVILEGED() xIsPrivileged()\r
+\r
+ /**\r
+ * @brief Raise an SVC request to raise privilege.\r
+ *\r
+ * The SVC handler checks that the SVC was raised from a system call and only\r
+ * then it raises the privilege. If this is called from any other place,\r
+ * the privilege is not raised.\r
+ */\r
+ #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );\r
+\r
+ /**\r
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL\r
+ * register.\r
+ */\r
+ #define portRESET_PRIVILEGE() vResetPrivilege()\r
+#else\r
+ #define portIS_PRIVILEGED()\r
+ #define portRAISE_PRIVILEGE()\r
+ #define portRESET_PRIVILEGE()\r
+#endif /* configENABLE_MPU */\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Barriers.\r
+ */\r
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )\r
+/*-----------------------------------------------------------*/\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* PORTMACRO_H */\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+#ifndef PORTMACRO_H\r
+#define PORTMACRO_H\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Port specific definitions.\r
+ *\r
+ * The settings in this file configure FreeRTOS correctly for the given hardware\r
+ * and compiler.\r
+ *\r
+ * These settings should not be altered.\r
+ *------------------------------------------------------------------------------\r
+ */\r
+\r
+#ifndef configENABLE_FPU\r
+ #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.\r
+#endif /* configENABLE_FPU */\r
+\r
+#ifndef configENABLE_MPU\r
+ #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.\r
+#endif /* configENABLE_MPU */\r
+\r
+#ifndef configENABLE_TRUSTZONE\r
+ #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.\r
+#endif /* configENABLE_TRUSTZONE */\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Type definitions.\r
+ */\r
+#define portCHAR char\r
+#define portFLOAT float\r
+#define portDOUBLE double\r
+#define portLONG long\r
+#define portSHORT short\r
+#define portSTACK_TYPE uint32_t\r
+#define portBASE_TYPE long\r
+\r
+typedef portSTACK_TYPE StackType_t;\r
+typedef long BaseType_t;\r
+typedef unsigned long UBaseType_t;\r
+\r
+#if( configUSE_16_BIT_TICKS == 1 )\r
+ typedef uint16_t TickType_t;\r
+ #define portMAX_DELAY ( TickType_t ) 0xffff\r
+#else\r
+ typedef uint32_t TickType_t;\r
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL\r
+\r
+ /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do\r
+ * not need to be guarded with a critical section. */\r
+ #define portTICK_TYPE_IS_ATOMIC 1\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * Architecture specifics.\r
+ */\r
+#define portARCH_NAME "Cortex-M33"\r
+#define portSTACK_GROWTH ( -1 )\r
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )\r
+#define portBYTE_ALIGNMENT 8\r
+#define portNOP()\r
+#define portINLINE __inline\r
+#ifndef portFORCE_INLINE\r
+ #define portFORCE_INLINE inline __attribute__(( always_inline ))\r
+#endif\r
+#define portHAS_STACK_OVERFLOW_CHECKING 1\r
+#define portDONT_DISCARD __root\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Extern declarations.\r
+ */\r
+extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;\r
+\r
+extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;\r
+extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;\r
+\r
+extern uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
+extern void vClearInterruptMaskFromISR( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
+\r
+#if( configENABLE_TRUSTZONE == 1 )\r
+ extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */\r
+ extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;\r
+#endif /* configENABLE_TRUSTZONE */\r
+\r
+#if( configENABLE_MPU == 1 )\r
+ extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;\r
+ extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;\r
+#endif /* configENABLE_MPU */\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief MPU specific constants.\r
+ */\r
+#if( configENABLE_MPU == 1 )\r
+ #define portUSING_MPU_WRAPPERS 1\r
+ #define portPRIVILEGE_BIT ( 0x80000000UL )\r
+#else\r
+ #define portPRIVILEGE_BIT ( 0x0UL )\r
+#endif /* configENABLE_MPU */\r
+\r
+\r
+/* MPU regions. */\r
+#define portPRIVILEGED_FLASH_REGION ( 0UL )\r
+#define portUNPRIVILEGED_FLASH_REGION ( 1UL )\r
+#define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL )\r
+#define portPRIVILEGED_RAM_REGION ( 3UL )\r
+#define portSTACK_REGION ( 4UL )\r
+#define portFIRST_CONFIGURABLE_REGION ( 5UL )\r
+#define portLAST_CONFIGURABLE_REGION ( 7UL )\r
+#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )\r
+#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */\r
+\r
+/* Device memory attributes used in MPU_MAIR registers.\r
+ *\r
+ * 8-bit values encoded as follows:\r
+ * Bit[7:4] - 0000 - Device Memory\r
+ * Bit[3:2] - 00 --> Device-nGnRnE\r
+ * 01 --> Device-nGnRE\r
+ * 10 --> Device-nGRE\r
+ * 11 --> Device-GRE\r
+ * Bit[1:0] - 00, Reserved.\r
+ */\r
+#define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */\r
+#define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */\r
+#define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */\r
+#define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */\r
+\r
+/* Normal memory attributes used in MPU_MAIR registers. */\r
+#define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */\r
+#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */\r
+\r
+/* Attributes used in MPU_RBAR registers. */\r
+#define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL )\r
+#define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL )\r
+#define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL )\r
+\r
+#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL )\r
+#define portMPU_REGION_READ_WRITE ( 1UL << 1UL )\r
+#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL )\r
+#define portMPU_REGION_READ_ONLY ( 3UL << 1UL )\r
+\r
+#define portMPU_REGION_EXECUTE_NEVER ( 1UL )\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Settings to define an MPU region.\r
+ */\r
+typedef struct MPURegionSettings\r
+{\r
+ uint32_t ulRBAR; /**< RBAR for the region. */\r
+ uint32_t ulRLAR; /**< RLAR for the region. */\r
+} MPURegionSettings_t;\r
+\r
+/**\r
+ * @brief MPU settings as stored in the TCB.\r
+ */\r
+typedef struct MPU_SETTINGS\r
+{\r
+ uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */\r
+ MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */\r
+} xMPU_SETTINGS;\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief SVC numbers.\r
+ */\r
+#define portSVC_ALLOCATE_SECURE_CONTEXT 0\r
+#define portSVC_FREE_SECURE_CONTEXT 1\r
+#define portSVC_START_SCHEDULER 2\r
+#define portSVC_RAISE_PRIVILEGE 3\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Scheduler utilities.\r
+ */\r
+#define portYIELD() vPortYield()\r
+#define portNVIC_INT_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000ed04 ) )\r
+#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )\r
+#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT\r
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Critical section management.\r
+ */\r
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMaskFromISR()\r
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vClearInterruptMaskFromISR( x )\r
+#define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" )\r
+#define portENABLE_INTERRUPTS() __asm volatile ( " cpsie i " ::: "memory" )\r
+#define portENTER_CRITICAL() vPortEnterCritical()\r
+#define portEXIT_CRITICAL() vPortExitCritical()\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Task function macros as described on the FreeRTOS.org WEB site.\r
+ */\r
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
+/*-----------------------------------------------------------*/\r
+\r
+#if( configENABLE_TRUSTZONE == 1 )\r
+ /**\r
+ * @brief Allocate a secure context for the task.\r
+ *\r
+ * Tasks are not created with a secure context. Any task that is going to call\r
+ * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a\r
+ * secure context before it calls any secure function.\r
+ *\r
+ * @param[in] ulSecureStackSize The size of the secure stack to be allocated.\r
+ */\r
+ #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize )\r
+\r
+ /**\r
+ * @brief Called when a task is deleted to delete the task's secure context,\r
+ * if it has one.\r
+ *\r
+ * @param[in] pxTCB The TCB of the task being deleted.\r
+ */\r
+ #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB )\r
+#else\r
+ #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )\r
+ #define portCLEAN_UP_TCB( pxTCB )\r
+#endif /* configENABLE_TRUSTZONE */\r
+/*-----------------------------------------------------------*/\r
+\r
+#if( configENABLE_MPU == 1 )\r
+ /**\r
+ * @brief Checks whether or not the processor is privileged.\r
+ *\r
+ * @return 1 if the processor is already privileged, 0 otherwise.\r
+ */\r
+ #define portIS_PRIVILEGED() xIsPrivileged()\r
+\r
+ /**\r
+ * @brief Raise an SVC request to raise privilege.\r
+ *\r
+ * The SVC handler checks that the SVC was raised from a system call and only\r
+ * then it raises the privilege. If this is called from any other place,\r
+ * the privilege is not raised.\r
+ */\r
+ #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );\r
+\r
+ /**\r
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL\r
+ * register.\r
+ */\r
+ #define portRESET_PRIVILEGE() vResetPrivilege()\r
+#else\r
+ #define portIS_PRIVILEGED()\r
+ #define portRAISE_PRIVILEGE()\r
+ #define portRESET_PRIVILEGE()\r
+#endif /* configENABLE_MPU */\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Barriers.\r
+ */\r
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )\r
+/*-----------------------------------------------------------*/\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* PORTMACRO_H */\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+#ifndef PORTMACRO_H\r
+#define PORTMACRO_H\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Port specific definitions.\r
+ *\r
+ * The settings in this file configure FreeRTOS correctly for the given hardware\r
+ * and compiler.\r
+ *\r
+ * These settings should not be altered.\r
+ *------------------------------------------------------------------------------\r
+ */\r
+\r
+#ifndef configENABLE_FPU\r
+ #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.\r
+#endif /* configENABLE_FPU */\r
+\r
+#ifndef configENABLE_MPU\r
+ #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.\r
+#endif /* configENABLE_MPU */\r
+\r
+#ifndef configENABLE_TRUSTZONE\r
+ #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.\r
+#endif /* configENABLE_TRUSTZONE */\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Type definitions.\r
+ */\r
+#define portCHAR char\r
+#define portFLOAT float\r
+#define portDOUBLE double\r
+#define portLONG long\r
+#define portSHORT short\r
+#define portSTACK_TYPE uint32_t\r
+#define portBASE_TYPE long\r
+\r
+typedef portSTACK_TYPE StackType_t;\r
+typedef long BaseType_t;\r
+typedef unsigned long UBaseType_t;\r
+\r
+#if( configUSE_16_BIT_TICKS == 1 )\r
+ typedef uint16_t TickType_t;\r
+ #define portMAX_DELAY ( TickType_t ) 0xffff\r
+#else\r
+ typedef uint32_t TickType_t;\r
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL\r
+\r
+ /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do\r
+ * not need to be guarded with a critical section. */\r
+ #define portTICK_TYPE_IS_ATOMIC 1\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * Architecture specifics.\r
+ */\r
+#define portARCH_NAME "Cortex-M33"\r
+#define portSTACK_GROWTH ( -1 )\r
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )\r
+#define portBYTE_ALIGNMENT 8\r
+#define portNOP()\r
+#define portINLINE __inline\r
+#ifndef portFORCE_INLINE\r
+ #define portFORCE_INLINE inline __attribute__(( always_inline ))\r
+#endif\r
+#define portHAS_STACK_OVERFLOW_CHECKING 1\r
+#define portDONT_DISCARD __root\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Extern declarations.\r
+ */\r
+extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;\r
+\r
+extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;\r
+extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;\r
+\r
+extern uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
+extern void vClearInterruptMaskFromISR( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
+\r
+#if( configENABLE_TRUSTZONE == 1 )\r
+ extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */\r
+ extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;\r
+#endif /* configENABLE_TRUSTZONE */\r
+\r
+#if( configENABLE_MPU == 1 )\r
+ extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;\r
+ extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;\r
+#endif /* configENABLE_MPU */\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief MPU specific constants.\r
+ */\r
+#if( configENABLE_MPU == 1 )\r
+ #define portUSING_MPU_WRAPPERS 1\r
+ #define portPRIVILEGE_BIT ( 0x80000000UL )\r
+#else\r
+ #define portPRIVILEGE_BIT ( 0x0UL )\r
+#endif /* configENABLE_MPU */\r
+\r
+\r
+/* MPU regions. */\r
+#define portPRIVILEGED_FLASH_REGION ( 0UL )\r
+#define portUNPRIVILEGED_FLASH_REGION ( 1UL )\r
+#define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL )\r
+#define portPRIVILEGED_RAM_REGION ( 3UL )\r
+#define portSTACK_REGION ( 4UL )\r
+#define portFIRST_CONFIGURABLE_REGION ( 5UL )\r
+#define portLAST_CONFIGURABLE_REGION ( 7UL )\r
+#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )\r
+#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */\r
+\r
+/* Device memory attributes used in MPU_MAIR registers.\r
+ *\r
+ * 8-bit values encoded as follows:\r
+ * Bit[7:4] - 0000 - Device Memory\r
+ * Bit[3:2] - 00 --> Device-nGnRnE\r
+ * 01 --> Device-nGnRE\r
+ * 10 --> Device-nGRE\r
+ * 11 --> Device-GRE\r
+ * Bit[1:0] - 00, Reserved.\r
+ */\r
+#define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */\r
+#define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */\r
+#define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */\r
+#define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */\r
+\r
+/* Normal memory attributes used in MPU_MAIR registers. */\r
+#define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */\r
+#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */\r
+\r
+/* Attributes used in MPU_RBAR registers. */\r
+#define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL )\r
+#define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL )\r
+#define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL )\r
+\r
+#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL )\r
+#define portMPU_REGION_READ_WRITE ( 1UL << 1UL )\r
+#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL )\r
+#define portMPU_REGION_READ_ONLY ( 3UL << 1UL )\r
+\r
+#define portMPU_REGION_EXECUTE_NEVER ( 1UL )\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Settings to define an MPU region.\r
+ */\r
+typedef struct MPURegionSettings\r
+{\r
+ uint32_t ulRBAR; /**< RBAR for the region. */\r
+ uint32_t ulRLAR; /**< RLAR for the region. */\r
+} MPURegionSettings_t;\r
+\r
+/**\r
+ * @brief MPU settings as stored in the TCB.\r
+ */\r
+typedef struct MPU_SETTINGS\r
+{\r
+ uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */\r
+ MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */\r
+} xMPU_SETTINGS;\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief SVC numbers.\r
+ */\r
+#define portSVC_ALLOCATE_SECURE_CONTEXT 0\r
+#define portSVC_FREE_SECURE_CONTEXT 1\r
+#define portSVC_START_SCHEDULER 2\r
+#define portSVC_RAISE_PRIVILEGE 3\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Scheduler utilities.\r
+ */\r
+#define portYIELD() vPortYield()\r
+#define portNVIC_INT_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000ed04 ) )\r
+#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )\r
+#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT\r
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Critical section management.\r
+ */\r
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMaskFromISR()\r
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vClearInterruptMaskFromISR( x )\r
+#define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" )\r
+#define portENABLE_INTERRUPTS() __asm volatile ( " cpsie i " ::: "memory" )\r
+#define portENTER_CRITICAL() vPortEnterCritical()\r
+#define portEXIT_CRITICAL() vPortExitCritical()\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Task function macros as described on the FreeRTOS.org WEB site.\r
+ */\r
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
+/*-----------------------------------------------------------*/\r
+\r
+#if( configENABLE_TRUSTZONE == 1 )\r
+ /**\r
+ * @brief Allocate a secure context for the task.\r
+ *\r
+ * Tasks are not created with a secure context. Any task that is going to call\r
+ * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a\r
+ * secure context before it calls any secure function.\r
+ *\r
+ * @param[in] ulSecureStackSize The size of the secure stack to be allocated.\r
+ */\r
+ #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize )\r
+\r
+ /**\r
+ * @brief Called when a task is deleted to delete the task's secure context,\r
+ * if it has one.\r
+ *\r
+ * @param[in] pxTCB The TCB of the task being deleted.\r
+ */\r
+ #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB )\r
+#else\r
+ #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )\r
+ #define portCLEAN_UP_TCB( pxTCB )\r
+#endif /* configENABLE_TRUSTZONE */\r
+/*-----------------------------------------------------------*/\r
+\r
+#if( configENABLE_MPU == 1 )\r
+ /**\r
+ * @brief Checks whether or not the processor is privileged.\r
+ *\r
+ * @return 1 if the processor is already privileged, 0 otherwise.\r
+ */\r
+ #define portIS_PRIVILEGED() xIsPrivileged()\r
+\r
+ /**\r
+ * @brief Raise an SVC request to raise privilege.\r
+ *\r
+ * The SVC handler checks that the SVC was raised from a system call and only\r
+ * then it raises the privilege. If this is called from any other place,\r
+ * the privilege is not raised.\r
+ */\r
+ #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );\r
+\r
+ /**\r
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL\r
+ * register.\r
+ */\r
+ #define portRESET_PRIVILEGE() vResetPrivilege()\r
+#else\r
+ #define portIS_PRIVILEGED()\r
+ #define portRAISE_PRIVILEGE()\r
+ #define portRESET_PRIVILEGE()\r
+#endif /* configENABLE_MPU */\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Barriers.\r
+ */\r
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )\r
+/*-----------------------------------------------------------*/\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* PORTMACRO_H */\r
* @brief Macro to declare a function as non-secure callable.\r
*/\r
#if defined( __IAR_SYSTEMS_ICC__ )\r
- #define secureportNON_SECURE_CALLABLE __cmse_nonsecure_entry\r
+ #define secureportNON_SECURE_CALLABLE __cmse_nonsecure_entry __root\r
#else\r
- #define secureportNON_SECURE_CALLABLE __attribute__((cmse_nonsecure_entry))\r
+ #define secureportNON_SECURE_CALLABLE __attribute__((cmse_nonsecure_entry)) __attribute__((used))\r
#endif\r
\r
/**\r
/**\r
* @brief C part of SVC handler.\r
*/\r
-void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) PRIVILEGED_FUNCTION;\r
+portDONT_DISCARD void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) PRIVILEGED_FUNCTION;\r
/*-----------------------------------------------------------*/\r
\r
/**\r
* @brief Saved as part of the task context to indicate which context the\r
* task is using on the secure side.\r
*/\r
- volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;\r
+ portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;\r
#endif /* configENABLE_TRUSTZONE */\r
/*-----------------------------------------------------------*/\r
\r
}\r
/*-----------------------------------------------------------*/\r
\r
-void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) /* PRIVILEGED_FUNCTION */\r
+void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */\r
{\r
#if( configENABLE_MPU == 1 )\r
#if defined( __ARMCC_VERSION )\r
/**\r
* Architecture specifics.\r
*/\r
-#define portARCH_NAME "Cortex-M33"\r
+#define portARCH_NAME "Cortex-M23"\r
#define portSTACK_GROWTH ( -1 )\r
#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )\r
#define portBYTE_ALIGNMENT 8\r
#define portFORCE_INLINE inline __attribute__(( always_inline ))\r
#endif\r
#define portHAS_STACK_OVERFLOW_CHECKING 1\r
+#define portDONT_DISCARD __attribute__(( used ))\r
/*-----------------------------------------------------------*/\r
\r
/**\r
extern void vClearInterruptMaskFromISR( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
\r
#if( configENABLE_TRUSTZONE == 1 )\r
- extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize );\r
- extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* PRIVILEGED_FUNCTION */;\r
+ extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */\r
+ extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;\r
#endif /* configENABLE_TRUSTZONE */\r
\r
#if( configENABLE_MPU == 1 )\r
* @brief Macro to declare a function as non-secure callable.\r
*/\r
#if defined( __IAR_SYSTEMS_ICC__ )\r
- #define secureportNON_SECURE_CALLABLE __cmse_nonsecure_entry\r
+ #define secureportNON_SECURE_CALLABLE __cmse_nonsecure_entry __root\r
#else\r
- #define secureportNON_SECURE_CALLABLE __attribute__((cmse_nonsecure_entry))\r
+ #define secureportNON_SECURE_CALLABLE __attribute__((cmse_nonsecure_entry)) __attribute__((used))\r
#endif\r
\r
/**\r
/**\r
* @brief C part of SVC handler.\r
*/\r
-void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) PRIVILEGED_FUNCTION;\r
+portDONT_DISCARD void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) PRIVILEGED_FUNCTION;\r
/*-----------------------------------------------------------*/\r
\r
/**\r
* @brief Saved as part of the task context to indicate which context the\r
* task is using on the secure side.\r
*/\r
- volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;\r
+ portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;\r
#endif /* configENABLE_TRUSTZONE */\r
/*-----------------------------------------------------------*/\r
\r
}\r
/*-----------------------------------------------------------*/\r
\r
-void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) /* PRIVILEGED_FUNCTION */\r
+void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */\r
{\r
#if( configENABLE_MPU == 1 )\r
#if defined( __ARMCC_VERSION )\r
/**\r
* Architecture specifics.\r
*/\r
-#define portARCH_NAME "Cortex-M33"\r
+#define portARCH_NAME "Cortex-M23"\r
#define portSTACK_GROWTH ( -1 )\r
#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )\r
#define portBYTE_ALIGNMENT 8\r
#define portFORCE_INLINE inline __attribute__(( always_inline ))\r
#endif\r
#define portHAS_STACK_OVERFLOW_CHECKING 1\r
+#define portDONT_DISCARD __attribute__(( used ))\r
/*-----------------------------------------------------------*/\r
\r
/**\r
extern void vClearInterruptMaskFromISR( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
\r
#if( configENABLE_TRUSTZONE == 1 )\r
- extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize );\r
- extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* PRIVILEGED_FUNCTION */;\r
+ extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */\r
+ extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;\r
#endif /* configENABLE_TRUSTZONE */\r
\r
#if( configENABLE_MPU == 1 )\r
/**\r
* @brief C part of SVC handler.\r
*/\r
-void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) PRIVILEGED_FUNCTION;\r
+portDONT_DISCARD void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) PRIVILEGED_FUNCTION;\r
/*-----------------------------------------------------------*/\r
\r
/**\r
* @brief Saved as part of the task context to indicate which context the\r
* task is using on the secure side.\r
*/\r
- volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;\r
+ portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;\r
#endif /* configENABLE_TRUSTZONE */\r
/*-----------------------------------------------------------*/\r
\r
}\r
/*-----------------------------------------------------------*/\r
\r
-void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) /* PRIVILEGED_FUNCTION */\r
+void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */\r
{\r
#if( configENABLE_MPU == 1 )\r
#if defined( __ARMCC_VERSION )\r
#define portFORCE_INLINE inline __attribute__(( always_inline ))\r
#endif\r
#define portHAS_STACK_OVERFLOW_CHECKING 1\r
+#define portDONT_DISCARD __attribute__(( used ))\r
/*-----------------------------------------------------------*/\r
\r
/**\r
extern void vClearInterruptMaskFromISR( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
\r
#if( configENABLE_TRUSTZONE == 1 )\r
- extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize );\r
- extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* PRIVILEGED_FUNCTION */;\r
+ extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */\r
+ extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;\r
#endif /* configENABLE_TRUSTZONE */\r
\r
#if( configENABLE_MPU == 1 )\r
* @brief Macro to declare a function as non-secure callable.\r
*/\r
#if defined( __IAR_SYSTEMS_ICC__ )\r
- #define secureportNON_SECURE_CALLABLE __cmse_nonsecure_entry\r
+ #define secureportNON_SECURE_CALLABLE __cmse_nonsecure_entry __root\r
#else\r
- #define secureportNON_SECURE_CALLABLE __attribute__((cmse_nonsecure_entry))\r
+ #define secureportNON_SECURE_CALLABLE __attribute__((cmse_nonsecure_entry)) __attribute__((used))\r
#endif\r
\r
/**\r
/**\r
* @brief C part of SVC handler.\r
*/\r
-void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) PRIVILEGED_FUNCTION;\r
+portDONT_DISCARD void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) PRIVILEGED_FUNCTION;\r
/*-----------------------------------------------------------*/\r
\r
/**\r
* @brief Saved as part of the task context to indicate which context the\r
* task is using on the secure side.\r
*/\r
- volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;\r
+ portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;\r
#endif /* configENABLE_TRUSTZONE */\r
/*-----------------------------------------------------------*/\r
\r
}\r
/*-----------------------------------------------------------*/\r
\r
-void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) /* PRIVILEGED_FUNCTION */\r
+void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */\r
{\r
#if( configENABLE_MPU == 1 )\r
#if defined( __ARMCC_VERSION )\r
#define portFORCE_INLINE inline __attribute__(( always_inline ))\r
#endif\r
#define portHAS_STACK_OVERFLOW_CHECKING 1\r
+#define portDONT_DISCARD __attribute__(( used ))\r
/*-----------------------------------------------------------*/\r
\r
/**\r
extern void vClearInterruptMaskFromISR( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
\r
#if( configENABLE_TRUSTZONE == 1 )\r
- extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize );\r
- extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* PRIVILEGED_FUNCTION */;\r
+ extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */\r
+ extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;\r
#endif /* configENABLE_TRUSTZONE */\r
\r
#if( configENABLE_MPU == 1 )\r
/**\r
* @brief C part of SVC handler.\r
*/\r
-void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) PRIVILEGED_FUNCTION;\r
+portDONT_DISCARD void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) PRIVILEGED_FUNCTION;\r
/*-----------------------------------------------------------*/\r
\r
/**\r
* @brief Saved as part of the task context to indicate which context the\r
* task is using on the secure side.\r
*/\r
- volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;\r
+ portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;\r
#endif /* configENABLE_TRUSTZONE */\r
/*-----------------------------------------------------------*/\r
\r
}\r
/*-----------------------------------------------------------*/\r
\r
-void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) /* PRIVILEGED_FUNCTION */\r
+void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */\r
{\r
#if( configENABLE_MPU == 1 )\r
#if defined( __ARMCC_VERSION )\r
/**\r
* Architecture specifics.\r
*/\r
-#define portARCH_NAME "Cortex-M33"\r
+#define portARCH_NAME "Cortex-M23"\r
#define portSTACK_GROWTH ( -1 )\r
#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )\r
#define portBYTE_ALIGNMENT 8\r
#define portFORCE_INLINE inline __attribute__(( always_inline ))\r
#endif\r
#define portHAS_STACK_OVERFLOW_CHECKING 1\r
+#define portDONT_DISCARD __root\r
/*-----------------------------------------------------------*/\r
\r
/**\r
extern void vClearInterruptMaskFromISR( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
\r
#if( configENABLE_TRUSTZONE == 1 )\r
- extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize );\r
- extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* PRIVILEGED_FUNCTION */;\r
+ extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */\r
+ extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;\r
#endif /* configENABLE_TRUSTZONE */\r
\r
#if( configENABLE_MPU == 1 )\r
* @brief Macro to declare a function as non-secure callable.\r
*/\r
#if defined( __IAR_SYSTEMS_ICC__ )\r
- #define secureportNON_SECURE_CALLABLE __cmse_nonsecure_entry\r
+ #define secureportNON_SECURE_CALLABLE __cmse_nonsecure_entry __root\r
#else\r
- #define secureportNON_SECURE_CALLABLE __attribute__((cmse_nonsecure_entry))\r
+ #define secureportNON_SECURE_CALLABLE __attribute__((cmse_nonsecure_entry)) __attribute__((used))\r
#endif\r
\r
/**\r
/**\r
* @brief C part of SVC handler.\r
*/\r
-void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) PRIVILEGED_FUNCTION;\r
+portDONT_DISCARD void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) PRIVILEGED_FUNCTION;\r
/*-----------------------------------------------------------*/\r
\r
/**\r
* @brief Saved as part of the task context to indicate which context the\r
* task is using on the secure side.\r
*/\r
- volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;\r
+ portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;\r
#endif /* configENABLE_TRUSTZONE */\r
/*-----------------------------------------------------------*/\r
\r
}\r
/*-----------------------------------------------------------*/\r
\r
-void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) /* PRIVILEGED_FUNCTION */\r
+void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */\r
{\r
#if( configENABLE_MPU == 1 )\r
#if defined( __ARMCC_VERSION )\r
/**\r
* Architecture specifics.\r
*/\r
-#define portARCH_NAME "Cortex-M33"\r
+#define portARCH_NAME "Cortex-M23"\r
#define portSTACK_GROWTH ( -1 )\r
#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )\r
#define portBYTE_ALIGNMENT 8\r
#define portFORCE_INLINE inline __attribute__(( always_inline ))\r
#endif\r
#define portHAS_STACK_OVERFLOW_CHECKING 1\r
+#define portDONT_DISCARD __root\r
/*-----------------------------------------------------------*/\r
\r
/**\r
extern void vClearInterruptMaskFromISR( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
\r
#if( configENABLE_TRUSTZONE == 1 )\r
- extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize );\r
- extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* PRIVILEGED_FUNCTION */;\r
+ extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */\r
+ extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;\r
#endif /* configENABLE_TRUSTZONE */\r
\r
#if( configENABLE_MPU == 1 )\r
/**\r
* @brief C part of SVC handler.\r
*/\r
-void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) PRIVILEGED_FUNCTION;\r
+portDONT_DISCARD void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) PRIVILEGED_FUNCTION;\r
/*-----------------------------------------------------------*/\r
\r
/**\r
* @brief Saved as part of the task context to indicate which context the\r
* task is using on the secure side.\r
*/\r
- volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;\r
+ portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;\r
#endif /* configENABLE_TRUSTZONE */\r
/*-----------------------------------------------------------*/\r
\r
}\r
/*-----------------------------------------------------------*/\r
\r
-void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) /* PRIVILEGED_FUNCTION */\r
+void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */\r
{\r
#if( configENABLE_MPU == 1 )\r
#if defined( __ARMCC_VERSION )\r
#define portFORCE_INLINE inline __attribute__(( always_inline ))\r
#endif\r
#define portHAS_STACK_OVERFLOW_CHECKING 1\r
+#define portDONT_DISCARD __root\r
/*-----------------------------------------------------------*/\r
\r
/**\r
extern void vClearInterruptMaskFromISR( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
\r
#if( configENABLE_TRUSTZONE == 1 )\r
- extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize );\r
- extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* PRIVILEGED_FUNCTION */;\r
+ extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */\r
+ extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;\r
#endif /* configENABLE_TRUSTZONE */\r
\r
#if( configENABLE_MPU == 1 )\r
* @brief Macro to declare a function as non-secure callable.\r
*/\r
#if defined( __IAR_SYSTEMS_ICC__ )\r
- #define secureportNON_SECURE_CALLABLE __cmse_nonsecure_entry\r
+ #define secureportNON_SECURE_CALLABLE __cmse_nonsecure_entry __root\r
#else\r
- #define secureportNON_SECURE_CALLABLE __attribute__((cmse_nonsecure_entry))\r
+ #define secureportNON_SECURE_CALLABLE __attribute__((cmse_nonsecure_entry)) __attribute__((used))\r
#endif\r
\r
/**\r
/**\r
* @brief C part of SVC handler.\r
*/\r
-void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) PRIVILEGED_FUNCTION;\r
+portDONT_DISCARD void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) PRIVILEGED_FUNCTION;\r
/*-----------------------------------------------------------*/\r
\r
/**\r
* @brief Saved as part of the task context to indicate which context the\r
* task is using on the secure side.\r
*/\r
- volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;\r
+ portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;\r
#endif /* configENABLE_TRUSTZONE */\r
/*-----------------------------------------------------------*/\r
\r
}\r
/*-----------------------------------------------------------*/\r
\r
-void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) /* PRIVILEGED_FUNCTION */\r
+void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */\r
{\r
#if( configENABLE_MPU == 1 )\r
#if defined( __ARMCC_VERSION )\r
#define portFORCE_INLINE inline __attribute__(( always_inline ))\r
#endif\r
#define portHAS_STACK_OVERFLOW_CHECKING 1\r
+#define portDONT_DISCARD __root\r
/*-----------------------------------------------------------*/\r
\r
/**\r
extern void vClearInterruptMaskFromISR( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
\r
#if( configENABLE_TRUSTZONE == 1 )\r
- extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize );\r
- extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* PRIVILEGED_FUNCTION */;\r
+ extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */\r
+ extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;\r
#endif /* configENABLE_TRUSTZONE */\r
\r
#if( configENABLE_MPU == 1 )\r
projects / freertos / commitdiff