#define PIN7_IDX 7u /*!< Pin number for pin 7 in a port */
#define PIN8_IDX 8u /*!< Pin number for pin 8 in a port */
+#define PIN24_IDX 24u /*!< Pin number for pin 24 in a port */
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
BOARD_InitPins:
- options: {callFromInitBoot: 'true', coreID: cm4, enableClock: 'true'}
- pin_list:
+ - {pin_num: D6, peripheral: GPIOA, signal: 'GPIO, 24', pin_signal: PTA24/LPSPI2_PCS0/LPSPI1_SCK/LPI2C2_SCL/FB_OE_b/TPM2_CH0}
- {pin_num: N2, peripheral: LPUART0, signal: RX, pin_signal: LPCMP0_IN0/PTC7/LLWU_P15/LPSPI0_PCS3/LPUART0_RX/LPI2C1_HREQ/TPM0_CH0/LPTMR1_ALT1}
- {pin_num: P3, peripheral: LPUART0, signal: TX, pin_signal: LPCMP0_IN1/PTC8/LPSPI0_SCK/LPUART0_TX/LPI2C0_HREQ/TPM0_CH1}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*
*END**************************************************************************/
void BOARD_InitPins(void) {
+ CLOCK_EnableClock(kCLOCK_PortA); /* Clock Gate Control: 0x01u */
CLOCK_EnableClock(kCLOCK_PortC); /* Clock Gate Control: 0x01u */
+ PORT_SetPinMux(PORTA, PIN24_IDX, kPORT_MuxAsGpio); /* PORTA24 (pin D6) is configured as PTA24 */
PORT_SetPinMux(PORTC, PIN7_IDX, kPORT_MuxAlt3); /* PORTC7 (pin N2) is configured as LPUART0_RX */
PORT_SetPinMux(PORTC, PIN8_IDX, kPORT_MuxAlt3); /* PORTC8 (pin P3) is configured as LPUART0_TX */
}
</tool>\r
</toolChain>\r
</folderInfo>\r
+ <fileInfo id="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.2124579326.468406560" name="fsl_lpuart.c" rcbsApplicability="disable" resourcePath="common/rv32m1_sdk_riscv/devices/RV32M1/drivers/fsl_lpuart.c" toolsToInvoke="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.compiler.906968630.2006953853">\r
+ <tool id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.compiler.906968630.2006953853" name="GNU RISC-V Cross C Compiler" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.compiler.906968630"/>\r
+ </fileInfo>\r
<sourceEntries>\r
<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>\r
</sourceEntries>\r
pdMS_TO_TICKS() macro. mainNO_ERROR_CHECK_TASK_PERIOD is used if no errors have\r
been found, mainERROR_CHECK_TASK_PERIOD is used if an error has been found. */\r
#define mainNO_ERROR_CHECK_TASK_PERIOD pdMS_TO_TICKS( 3000UL )\r
-#define mainERROR_CHECK_TASK_PERIOD pdMS_TO_TICKS( 500UL )\r
+#define mainERROR_CHECK_TASK_PERIOD pdMS_TO_TICKS( 500UL )\r
\r
/* Parameters that are passed into the register check tasks solely for the\r
purpose of ensuring parameters are passed into tasks correctly. */\r
#define mainTIMER_TEST_PERIOD ( 50 )\r
\r
/* The size of the stack allocated to the check task (as described in the\r
-comments at the top of this file. */\r
+comments at the top of this file. This is surprisingly large as it calls\r
+the logging library's print function, which allocates a 128 byte buffer on its\r
+stack. */\r
#define mainCHECK_TASK_STACK_SIZE_WORDS 200\r
\r
/* Size of the stacks to allocated for the register check tasks. */\r
/* Clear LPIT0 interrupt. */\r
LPIT0->MSR = 1U;\r
}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* At the time of writing, interrupt nesting is not supported, so do not use\r
+the default SystemIrqHandler() implementation as that enables interrupts. A\r
+version that does not enable interrupts is provided below. THIS INTERRUPT\r
+HANDLER IS SPECIFIC TO THE VEGA BOARD WHICH DOES NOT INCLUDE A CLINT! */\r
+void SystemIrqHandler( uint32_t mcause )\r
+{\r
+uint32_t ulInterruptNumber;\r
+typedef void ( * irq_handler_t )( void );\r
+extern const irq_handler_t isrTable[];\r
+\r
+ ulInterruptNumber = mcause & 0x1FUL;\r
+\r
+ /* Clear pending flag in EVENT unit .*/\r
+ EVENT_UNIT->INTPTPENDCLEAR = ( 1U << ulInterruptNumber );\r
+\r
+ /* Read back to make sure write finished. */\r
+ (void)(EVENT_UNIT->INTPTPENDCLEAR);\r
+\r
+ /* Now call the real irq handler for ulInterruptNumber */\r
+ isrTable[ ulInterruptNumber ]();\r
+}\r
\r