]> git.sur5r.net Git - openocd/commitdiff
aarch64: Enable halting debug mode on breakpoint set
authorDavid Ung <davidu@nvidia.com>
Thu, 23 Apr 2015 20:22:13 +0000 (13:22 -0700)
committerMatthias Welwarsky <matthias.welwarsky@sysgo.com>
Fri, 10 Feb 2017 12:56:39 +0000 (13:56 +0100)
Ensure that we allow halting debug mode after setting breakpoint

Change-Id: I6f0d7a4a4775a93c133fb1ec31dfe3324d9f7395
Signed-off-by: David Ung <david.ung.42@gmail.com>
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
src/target/aarch64.c

index d991a3194ecbcdc95dcefe5e7f83ddae825d85ef..c6354c2c973bfae9733c899fa6ef599726e3d7cb 100644 (file)
@@ -1247,6 +1247,7 @@ static int aarch64_set_breakpoint(struct target *target,
        struct aarch64_common *aarch64 = target_to_aarch64(target);
        struct armv8_common *armv8 = &aarch64->armv8_common;
        struct aarch64_brp *brp_list = aarch64->brp_list;
+       uint32_t dscr;
 
        if (breakpoint->set) {
                LOG_WARNING("breakpoint already set");
@@ -1311,6 +1312,17 @@ static int aarch64_set_breakpoint(struct target *target,
                breakpoint->set = 0x11; /* Any nice value but 0 */
        }
 
+       retval = mem_ap_read_atomic_u32(armv8->debug_ap,
+                                       armv8->debug_base + CPUDBG_DSCR, &dscr);
+       /* Ensure that halting debug mode is enable */
+       dscr = dscr | DSCR_HALT_DBG_MODE;
+       retval = mem_ap_write_atomic_u32(armv8->debug_ap,
+                                        armv8->debug_base + CPUDBG_DSCR, dscr);
+       if (retval != ERROR_OK) {
+               LOG_DEBUG("Failed to set DSCR.HDE");
+               return retval;
+       }
+
        return ERROR_OK;
 }