Add in an FM3/IAR

git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@1407 1d2547de-c912-0410-9cb9-b8ca96c0e9e2

diff --git a/Demo/CORTEX_MB9B500_IAR_Keil/FreeRTOSConfig.h b/Demo/CORTEX_MB9B500_IAR_Keil/FreeRTOSConfig.h
new file mode 100644 (file)
index 0000000..f5069d9
--- /dev/null
+++ b/Demo/CORTEX_MB9B500_IAR_Keil/FreeRTOSConfig.h
@@ -0,0 +1,167 @@
+/*\r
+    FreeRTOS V7.0.0 - Copyright (C) 2011 Real Time Engineers Ltd.\r
+\r
+\r
+       FreeRTOS supports many tools and architectures. V7.0.0 is sponsored by:\r
+       Atollic AB - Atollic provides professional embedded systems development\r
+       tools for C/C++ development, code analysis and test automation.\r
+       See http://www.atollic.com\r
+\r
+\r
+    ***************************************************************************\r
+     *                                                                       *\r
+     *    FreeRTOS tutorial books are available in pdf and paperback.        *\r
+     *    Complete, revised, and edited pdf reference manuals are also       *\r
+     *    available.                                                         *\r
+     *                                                                       *\r
+     *    Purchasing FreeRTOS documentation will not only help you, by       *\r
+     *    ensuring you get running as quickly as possible and with an        *\r
+     *    in-depth knowledge of how to use FreeRTOS, it will also help       *\r
+     *    the FreeRTOS project to continue with its mission of providing     *\r
+     *    professional grade, cross platform, de facto standard solutions    *\r
+     *    for microcontrollers - completely free of charge!                  *\r
+     *                                                                       *\r
+     *    >>> See http://www.FreeRTOS.org/Documentation for details. <<<     *\r
+     *                                                                       *\r
+     *    Thank you for using FreeRTOS, and thank you for your support!      *\r
+     *                                                                       *\r
+    ***************************************************************************\r
+\r
+\r
+    This file is part of the FreeRTOS distribution.\r
+\r
+    FreeRTOS is free software; you can redistribute it and/or modify it under\r
+    the terms of the GNU General Public License (version 2) as published by the\r
+    Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+    >>>NOTE<<< The modification to the GPL is included to allow you to\r
+    distribute a combined work that includes FreeRTOS without being obliged to\r
+    provide the source code for proprietary components outside of the FreeRTOS\r
+    kernel.  FreeRTOS is distributed in the hope that it will be useful, but\r
+    WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\r
+    more details. You should have received a copy of the GNU General Public\r
+    License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+    can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+    by writing to Richard Barry, contact details for whom are available on the\r
+    FreeRTOS WEB site.\r
+\r
+    1 tab == 4 spaces!\r
+\r
+    http://www.FreeRTOS.org - Documentation, latest information, license and\r
+    contact details.\r
+\r
+    http://www.SafeRTOS.com - A version that is certified for use in safety\r
+    critical systems.\r
+\r
+    http://www.OpenRTOS.com - Commercial support, development, porting,\r
+    licensing and training services.\r
+*/\r
+\r
+\r
+#ifndef FREERTOS_CONFIG_H\r
+#define FREERTOS_CONFIG_H\r
+\r
+/*-----------------------------------------------------------\r
+ * Application specific definitions.\r
+ *\r
+ * These definitions should be adjusted for your particular hardware and\r
+ * application requirements.\r
+ *\r
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\r
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.\r
+ *\r
+ * See http://www.freertos.org/a00110.html.\r
+ *----------------------------------------------------------*/\r
+\r
+/* Use a guard to ensure the following few definitions are'nt included in\r
+assembly files that include this header file. */\r
+#ifndef __IASMARM__\r
+       #include <stdint.h>\r
+       extern uint32_t SystemCoreClock;\r
+#endif\r
+\r
+#define configUSE_PREEMPTION                   1\r
+#define configUSE_IDLE_HOOK                            1\r
+#define configUSE_TICK_HOOK                            0\r
+#define configCPU_CLOCK_HZ                             ( SystemCoreClock )\r
+#define configTICK_RATE_HZ                             ( ( portTickType ) 1000 )\r
+#define configMAX_PRIORITIES                   ( ( unsigned portBASE_TYPE ) 5 )\r
+#define configMINIMAL_STACK_SIZE               ( ( unsigned short ) 90 )\r
+#define configTOTAL_HEAP_SIZE                  ( ( size_t ) ( 30 * 1024 ) )\r
+#define configMAX_TASK_NAME_LEN                        ( 10 )\r
+#define configUSE_TRACE_FACILITY               1\r
+#define configUSE_16_BIT_TICKS                 0\r
+#define configIDLE_SHOULD_YIELD                        1\r
+#define configUSE_MUTEXES                              1\r
+#define configQUEUE_REGISTRY_SIZE              0\r
+#define configGENERATE_RUN_TIME_STATS  0\r
+#define configCHECK_FOR_STACK_OVERFLOW 2\r
+#define configUSE_RECURSIVE_MUTEXES            1\r
+#define configUSE_MALLOC_FAILED_HOOK   1\r
+#define configUSE_APPLICATION_TASK_TAG 0\r
+#define configUSE_COUNTING_SEMAPHORES  0\r
+\r
+/* Co-routine definitions. */\r
+#define configUSE_CO_ROUTINES          0\r
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )\r
+\r
+/* Software timer definitions. */\r
+#define configUSE_TIMERS                               1\r
+#define configTIMER_TASK_PRIORITY              ( 2 )\r
+#define configTIMER_QUEUE_LENGTH               10\r
+#define configTIMER_TASK_STACK_DEPTH   ( configMINIMAL_STACK_SIZE * 2 )\r
+\r
+/* Set the following definitions to 1 to include the API function, or zero\r
+to exclude the API function. */\r
+#define INCLUDE_vTaskPrioritySet               1\r
+#define INCLUDE_uxTaskPriorityGet              1\r
+#define INCLUDE_vTaskDelete                            1\r
+#define INCLUDE_vTaskCleanUpResources  1\r
+#define INCLUDE_vTaskSuspend                   1\r
+#define INCLUDE_vTaskDelayUntil                        1\r
+#define INCLUDE_vTaskDelay                             1\r
+\r
+/* Use the system definition, if there is one */\r
+#ifdef __NVIC_PRIO_BITS\r
+       #define configPRIO_BITS                 __NVIC_PRIO_BITS\r
+#else\r
+       #define configPRIO_BITS                 4        /* 15 priority levels */\r
+#endif\r
+\r
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY                        0xf\r
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY   5\r
+\r
+/* The lowest priority. */\r
+#define configKERNEL_INTERRUPT_PRIORITY        ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )\r
+/* Priority 5, or 160 as only the top three bits are implemented. */\r
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY   ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )\r
+       \r
+#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); for( ;; ); }    \r
+       \r
+#define vPortSVCHandler SVC_Handler\r
+#define xPortPendSVHandler PendSV_Handler\r
+#define vPortSVCHandler SVC_Handler\r
+#define xPortSysTickHandler SysTick_Handler\r
+\r
+/* MAC address configuration. */\r
+#define configMAC_ADDR0        0x00\r
+#define configMAC_ADDR1        0x12\r
+#define configMAC_ADDR2        0x13\r
+#define configMAC_ADDR3        0x10\r
+#define configMAC_ADDR4        0x15\r
+#define configMAC_ADDR5        0x11\r
+\r
+/* IP address configuration. */\r
+#define configIP_ADDR0         192\r
+#define configIP_ADDR1         168\r
+#define configIP_ADDR2         0\r
+#define configIP_ADDR3         200\r
+\r
+/* Netmask configuration. */\r
+#define configNET_MASK0                255\r
+#define configNET_MASK1                255\r
+#define configNET_MASK2                255\r
+#define configNET_MASK3                0\r
+\r
+#endif /* FREERTOS_CONFIG_H */\r
+\r

diff --git a/Demo/CORTEX_MB9B500_IAR_Keil/Fujitu_source/core_cm3.c b/Demo/CORTEX_MB9B500_IAR_Keil/Fujitu_source/core_cm3.c
new file mode 100644 (file)
index 0000000..f1bfb2b
--- /dev/null
+++ b/Demo/CORTEX_MB9B500_IAR_Keil/Fujitu_source/core_cm3.c
@@ -0,0 +1,359 @@
+/**************************************************************************//**\r
+ * @file     core_cm3.c\r
+ * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Source File\r
+ * @version  V1.40\r
+ * @date     18. February 2010\r
+ *\r
+ * @note\r
+ * Copyright (C) 2009-2010 ARM Limited. All rights reserved.\r
+ *\r
+ * @par\r
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M \r
+ * processor based microcontrollers.  This file can be freely distributed \r
+ * within development tools that are supporting such ARM based processors. \r
+ *\r
+ * @par\r
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+ *\r
+ ******************************************************************************/\r
+\r
+#include <stdint.h>\r
+\r
+/* define compiler specific symbols */\r
+#if defined ( __CC_ARM   )\r
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */\r
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */\r
+\r
+#elif defined ( __ICCARM__ )\r
+  #define __ASM           __asm                                       /*!< asm keyword for IAR Compiler          */\r
+  #define __INLINE        inline                                      /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */\r
+\r
+#elif defined   (  __GNUC__  )\r
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */\r
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */\r
+\r
+#elif defined   (  __TASKING__  )\r
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */\r
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */\r
+\r
+#endif\r
+\r
+\r
+/* ##########################  Core Instruction Access  ######################### */\r
+\r
+#if defined ( __CC_ARM   ) /*------------------ RealView Compiler ----------------*/\r
+\r
+/**\r
+ * @brief  Reverse byte order (16 bit)\r
+ *\r
+ * @param  value  value to reverse\r
+ * @return        reversed value\r
+ *\r
+ * Reverse byte order in unsigned short value\r
+ */\r
+#if (__ARMCC_VERSION < 400677)\r
+__ASM uint32_t __REV16(uint16_t value)\r
+{\r
+  rev16 r0, r0\r
+  bx lr\r
+}\r
+#endif /* __ARMCC_VERSION  */ \r
+\r
+/**\r
+ * @brief  Reverse byte order in signed short value with sign extension to integer\r
+ *\r
+ * @param  value  value to reverse\r
+ * @return        reversed value\r
+ *\r
+ * Reverse byte order in signed short value with sign extension to integer\r
+ */\r
+#if (__ARMCC_VERSION < 400677)\r
+__ASM int32_t __REVSH(int16_t value)\r
+{\r
+  revsh r0, r0\r
+  bx lr\r
+}\r
+#endif /* __ARMCC_VERSION  */ \r
+\r
+ /**\r
+ * @brief  Remove the exclusive lock created by ldrex\r
+ *\r
+ * Removes the exclusive lock which is created by ldrex.\r
+ */\r
+#if (__ARMCC_VERSION < 400000)\r
+__ASM void __CLREX(void)\r
+{\r
+  clrex\r
+}\r
+#endif /* __ARMCC_VERSION  */ \r
+\r
+\r
+#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/\r
+/* obsolete */\r
+#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/\r
+/* obsolete */\r
+#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/\r
+/* obsolete */\r
+#endif\r
+\r
+\r
+/* ###########################  Core Function Access  ########################### */\r
+\r
+#if defined ( __CC_ARM   ) /*------------------ RealView Compiler ----------------*/\r
+\r
+/**\r
+ * @brief  Return the Control Register value\r
+* \r
+*  @return Control value\r
+ *\r
+ * Return the content of the control register\r
+ */\r
+#if       (__ARMCC_VERSION <  400000)\r
+__ASM uint32_t __get_CONTROL(void)\r
+{\r
+  mrs r0, control\r
+  bx lr\r
+}\r
+#endif /*  __ARMCC_VERSION  */ \r
+\r
+/**\r
+ * @brief  Set the Control Register value\r
+ *\r
+ * @param  control  Control value\r
+ *\r
+ * Set the control register\r
+ */\r
+#if       (__ARMCC_VERSION <  400000)\r
+__ASM void __set_CONTROL(uint32_t control)\r
+{\r
+  msr control, r0\r
+  bx lr\r
+}\r
+#endif /*  __ARMCC_VERSION  */ \r
+\r
+/**\r
+ * @brief  Get IPSR Register value\r
+ *\r
+ * @return uint32_t IPSR value\r
+ *\r
+ * return the content of the IPSR register\r
+ */\r
+#if       (__ARMCC_VERSION <  400000)\r
+__ASM uint32_t __get_IPSR(void)\r
+{\r
+  mrs r0, ipsr\r
+  bx lr\r
+}\r
+#endif /*  __ARMCC_VERSION  */ \r
+\r
+/**\r
+ * @brief  Get APSR Register value\r
+ *\r
+ * @return uint32_t APSR value\r
+ *\r
+ * return the content of the APSR register\r
+ */\r
+#if       (__ARMCC_VERSION <  400000)\r
+__ASM uint32_t __get_APSR(void)\r
+{\r
+  mrs r0, apsr\r
+  bx lr\r
+}\r
+#endif /*  __ARMCC_VERSION  */ \r
+\r
+/**\r
+ * @brief  Get xPSR Register value\r
+ *\r
+ * @return uint32_t xPSR value\r
+ *\r
+ * return the content of the xPSR register\r
+ */\r
+#if       (__ARMCC_VERSION <  400000)\r
+__ASM uint32_t __get_xPSR(void)\r
+{\r
+  mrs r0, xpsr\r
+  bx lr\r
+}\r
+#endif /*  __ARMCC_VERSION  */ \r
+\r
+/**\r
+ * @brief  Return the Process Stack Pointer\r
+ *\r
+ * @return ProcessStackPointer\r
+ *\r
+ * Return the actual process stack pointer\r
+ */\r
+#if       (__ARMCC_VERSION <  400000)\r
+__ASM uint32_t __get_PSP(void)\r
+{\r
+  mrs r0, psp\r
+  bx lr\r
+}\r
+#endif /*  __ARMCC_VERSION  */ \r
+ \r
+/**\r
+ * @brief  Set the Process Stack Pointer\r
+ *\r
+ * @param  topOfProcStack  Process Stack Pointer\r
+ *\r
+ * Assign the value ProcessStackPointer to the MSP \r
+ * (process stack pointer) Cortex processor register\r
+ */\r
+#if       (__ARMCC_VERSION <  400000)\r
+__ASM void __set_PSP(uint32_t topOfProcStack)\r
+{\r
+  msr psp, r0\r
+  bx lr\r
+}\r
+#endif /*  __ARMCC_VERSION  */ \r
+\r
+/**\r
+ * @brief  Return the Main Stack Pointer\r
+ *\r
+ * @return Main Stack Pointer\r
+ *\r
+ * Return the current value of the MSP (main stack pointer)\r
+ * Cortex processor register\r
+ */\r
+#if       (__ARMCC_VERSION <  400000)\r
+__ASM uint32_t __get_MSP(void)\r
+{\r
+  mrs r0, msp\r
+  bx lr\r
+}\r
+#endif /*  __ARMCC_VERSION  */ \r
+ \r
+/**\r
+ * @brief  Set the Main Stack Pointer\r
+ *\r
+ * @param  topOfMainStack  Main Stack Pointer\r
+ *\r
+ * Assign the value mainStackPointer to the MSP \r
+ * (main stack pointer) Cortex processor register\r
+ */\r
+#if       (__ARMCC_VERSION <  400000)\r
+__ASM void __set_MSP(uint32_t mainStackPointer)\r
+{\r
+  msr msp, r0\r
+  bx lr\r
+}\r
+#endif /*  __ARMCC_VERSION  */ \r
+ \r
+/**\r
+ * @brief  Return the Base Priority value\r
+ *\r
+ * @return BasePriority\r
+ *\r
+ * Return the content of the base priority register\r
+ */\r
+#if       (__ARMCC_VERSION <  400000)\r
+__ASM uint32_t  __get_BASEPRI(void)\r
+{\r
+  mrs r0, basepri\r
+  bx lr\r
+}\r
+#endif /*  __ARMCC_VERSION  */ \r
+\r
+/**\r
+ * @brief  Set the Base Priority value\r
+ *\r
+ * @param  basePri  BasePriority\r
+ *\r
+ * Set the base priority register\r
+ */\r
+#if       (__ARMCC_VERSION <  400000)\r
+__ASM void __set_BASEPRI(uint32_t basePri)\r
+{\r
+  msr basepri, r0\r
+  bx lr\r
+}\r
+#endif /*  __ARMCC_VERSION  */ \r
+ \r
+/**\r
+ * @brief  Return the Priority Mask value\r
+ *\r
+ * @return PriMask\r
+ *\r
+ * Return state of the priority mask bit from the priority mask register\r
+ */\r
+#if       (__ARMCC_VERSION <  400000)\r
+__ASM uint32_t __get_PRIMASK(void)\r
+{\r
+  mrs r0, primask\r
+  bx lr\r
+}\r
+#endif /*  __ARMCC_VERSION  */ \r
+ \r
+/**\r
+ * @brief  Set the Priority Mask value\r
+ *\r
+ * @param  priMask  PriMask\r
+ *\r
+ * Set the priority mask bit in the priority mask register\r
+ */\r
+#if       (__ARMCC_VERSION <  400000)\r
+__ASM void __set_PRIMASK(uint32_t priMask)\r
+{\r
+  msr primask, r0\r
+  bx lr\r
+}\r
+#endif /*  __ARMCC_VERSION  */ \r
+ \r
+/**\r
+ * @brief  Return the Fault Mask value\r
+ *\r
+ * @return FaultMask\r
+ *\r
+ * Return the content of the fault mask register\r
+ */\r
+#if       (__ARMCC_VERSION <  400000)\r
+__ASM uint32_t  __get_FAULTMASK(void)\r
+{\r
+  mrs r0, faultmask\r
+  bx lr\r
+}\r
+#endif /*  __ARMCC_VERSION  */ \r
+\r
+/**\r
+ * @brief  Set the Fault Mask value\r
+ *\r
+ * @param  faultMask  faultMask value\r
+ *\r
+ * Set the fault mask register\r
+ */\r
+#if       (__ARMCC_VERSION <  400000)\r
+__ASM void __set_FAULTMASK(uint32_t faultMask)\r
+{\r
+  msr faultmask, r0\r
+  bx lr\r
+}\r
+#endif /*  __ARMCC_VERSION  */ \r
+\r
+/**\r
+ * @brief  Return the FPSCR value\r
+ *\r
+ * @return FloatingPointStatusControlRegister\r
+ *\r
+ * Return the content of the FPSCR register\r
+ */\r
+\r
+/**\r
+ * @brief  Set the FPSCR value\r
+ *\r
+ * @param  fpscr  FloatingPointStatusControlRegister\r
+ *\r
+ * Set the FPSCR register\r
+ */\r
+\r
+\r
+#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/\r
+/* obsolete */\r
+#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/\r
+/* obsolete */\r
+#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/\r
+/* obsolete */\r
+#endif\r

diff --git a/Demo/CORTEX_MB9B500_IAR_Keil/Fujitu_source/core_cm3.h b/Demo/CORTEX_MB9B500_IAR_Keil/Fujitu_source/core_cm3.h
new file mode 100644 (file)
index 0000000..43be05e
--- /dev/null
+++ b/Demo/CORTEX_MB9B500_IAR_Keil/Fujitu_source/core_cm3.h
@@ -0,0 +1,1166 @@
+/**************************************************************************//**\r
+ * @file     core_cm3.h\r
+ * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Header File\r
+ * @version  V1.40\r
+ * @date     16. February 2010\r
+ *\r
+ * @note\r
+ * Copyright (C) 2009-2010 ARM Limited. All rights reserved.\r
+ *\r
+ * @par\r
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M \r
+ * processor based microcontrollers.  This file can be freely distributed \r
+ * within development tools that are supporting such ARM based processors. \r
+ *\r
+ * @par\r
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+ *\r
+ ******************************************************************************/\r
+\r
+#ifndef __CORE_CM3_H__\r
+#define __CORE_CM3_H__\r
+\r
+/** @addtogroup CMSIS_CM3_core_LintCinfiguration CMSIS CM3 Core Lint Configuration\r
+ *\r
+ * List of Lint messages which will be suppressed and not shown:\r
+ *   - not yet checked\r
+ * .\r
+ * Note:  To re-enable a Message, insert a space before 'lint' *\r
+ *\r
+ */\r
+\r
+\r
+/** @addtogroup CMSIS_CM3_core_definitions CM3 Core Definitions\r
+  This file defines all structures and symbols for CMSIS core:\r
+    - CMSIS version number\r
+    - Cortex-M core registers and bitfields\r
+    - Cortex-M core peripheral base address\r
+  @{\r
+ */\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif \r
+\r
+#define __CM3_CMSIS_VERSION_MAIN  (0x01)                                                       /*!< [31:16] CMSIS HAL main version */\r
+#define __CM3_CMSIS_VERSION_SUB   (0x40)                                                       /*!< [15:0]  CMSIS HAL sub version  */\r
+#define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number       */\r
+\r
+#define __CORTEX_M                (0x03)                                                       /*!< Cortex core                    */\r
+\r
+#ifndef __NVIC_PRIO_BITS\r
+  #define __NVIC_PRIO_BITS    4               /*!< standard definition for NVIC Priority Bits */\r
+#endif\r
+\r
+\r
+#include <stdint.h>                           /* Include standard types */\r
+\r
+\r
+\r
+/**\r
+ * IO definitions\r
+ *\r
+ * define access restrictions to peripheral registers\r
+ */\r
+\r
+#ifdef __cplusplus\r
+  #define     __I     volatile                /*!< defines 'read only' permissions      */\r
+#else\r
+  #define     __I     volatile const          /*!< defines 'read only' permissions      */\r
+#endif\r
+#define     __O     volatile                  /*!< defines 'write only' permissions     */\r
+#define     __IO    volatile                  /*!< defines 'read / write' permissions   */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ *                 Register Abstraction\r
+ ******************************************************************************/\r
+/** @addtogroup CMSIS_CM3_core_register CMSIS CM3 Core Register\r
+ @{\r
+*/\r
+\r
+/** @addtogroup CMSIS_ARM_CORE CMSIS ARM Core\r
+  memory mapped structure for Nested Vectored Interrupt Controller (NVIC)\r
+  @{\r
+ */\r
+typedef union\r
+{\r
+  struct\r
+  {\r
+#if (__CORTEX_M != 0x04)\r
+    uint32_t _reserved0:27;\r
+#else\r
+    uint32_t _reserved0:16;\r
+    uint32_t GE:4;                             /*!< bit: 16..19  Greater than or Equal flags  */\r
+    uint32_t _reserved1:7;\r
+#endif\r
+    uint32_t Q:1;                              /*!< bit:     27  Saturation condition flag    */\r
+    uint32_t V:1;                              /*!< bit:     28  Overflow condition code flag */\r
+    uint32_t C:1;                              /*!< bit:     29  Carry condition code flag    */\r
+    uint32_t Z:1;                              /*!< bit:     30  Zero condition code flag     */\r
+    uint32_t N:1;                              /*!< bit:     31  Negative condition code flag */\r
+  } b;\r
+  uint32_t w;\r
+} APSR_Type;\r
+\r
+typedef union\r
+{\r
+  struct\r
+  {\r
+    uint32_t ISR:9;                            /*!< bit: 00..08  Exception number             */\r
+    uint32_t _reserved0:23;\r
+  } b;\r
+  uint32_t w;\r
+} IPSR_Type;\r
+\r
+typedef union\r
+{\r
+  struct\r
+  {\r
+    uint32_t ISR:9;                            /*!< bit: 00..08  Exception number             */\r
+#if (__CORTEX_M != 0x04)\r
+    uint32_t _reserved0:15;\r
+#else\r
+    uint32_t _reserved0:7;\r
+    uint32_t GE:4;                             /*!< bit: 16..19  Greater than or Equal flags  */\r
+    uint32_t _reserved1:4;\r
+#endif\r
+    uint32_t T:1;                              /*!< bit:     24  Thumb bit        (read 0)    */\r
+    uint32_t IT:2;                             /*!< bit: 25..26  saved IT state   (read 0)    */\r
+    uint32_t Q:1;                              /*!< bit:     27  Saturation condition flag    */\r
+    uint32_t V:1;                              /*!< bit:     28  Overflow condition code flag */\r
+    uint32_t C:1;                              /*!< bit:     29  Carry condition code flag    */\r
+    uint32_t Z:1;                              /*!< bit:     30  Zero condition code flag     */\r
+    uint32_t N:1;                              /*!< bit:     31  Negative condition code flag */\r
+  } b;\r
+  uint32_t w;\r
+} xPSR_Type;\r
+\r
+typedef union\r
+{\r
+  struct\r
+  {\r
+    uint32_t nPRIV:1;                         /*!< bit:     00  Execution privilege in Thread mode */\r
+    uint32_t SPSEL:1;                         /*!< bit:     01  Stack to be used                   */\r
+    uint32_t FPCA:1;                          /*!< bit:     02  FP extension active flag           */\r
+    uint32_t _reserved0:29;\r
+  } b;\r
+  uint32_t w;\r
+} CONTROL_Type;\r
+\r
+/*@}*/ /* end of group CMSIS_ARM_CORE */\r
+\r
+\r
+/** @addtogroup CMSIS_CM3_NVIC CMSIS CM3 NVIC\r
+  memory mapped structure for Nested Vectored Interrupt Controller (NVIC)\r
+  @{\r
+ */\r
+typedef struct\r
+{\r
+  __IO uint32_t ISER[8];                      /*!< Offset: 0x000  Interrupt Set Enable Register           */\r
+       uint32_t RESERVED0[24];                                   \r
+  __IO uint32_t ICER[8];                      /*!< Offset: 0x080  Interrupt Clear Enable Register         */\r
+       uint32_t RSERVED1[24];                                    \r
+  __IO uint32_t ISPR[8];                      /*!< Offset: 0x100  Interrupt Set Pending Register          */\r
+       uint32_t RESERVED2[24];                                   \r
+  __IO uint32_t ICPR[8];                      /*!< Offset: 0x180  Interrupt Clear Pending Register        */\r
+       uint32_t RESERVED3[24];                                   \r
+  __IO uint32_t IABR[8];                      /*!< Offset: 0x200  Interrupt Active bit Register           */\r
+       uint32_t RESERVED4[56];                                   \r
+  __IO uint8_t  IP[240];                      /*!< Offset: 0x300  Interrupt Priority Register (8Bit wide) */\r
+       uint32_t RESERVED5[644];                                  \r
+  __O  uint32_t STIR;                         /*!< Offset: 0xE00  Software Trigger Interrupt Register     */\r
+}  NVIC_Type;                                               \r
+/*@}*/ /* end of group CMSIS_CM3_NVIC */\r
+\r
+\r
+/** @addtogroup CMSIS_CM3_SCB CMSIS CM3 SCB\r
+  memory mapped structure for System Control Block (SCB)\r
+  @{\r
+ */\r
+typedef struct\r
+{\r
+  __I  uint32_t CPUID;                        /*!< Offset: 0x00  CPU ID Base Register                                  */\r
+  __IO uint32_t ICSR;                         /*!< Offset: 0x04  Interrupt Control State Register                      */\r
+  __IO uint32_t VTOR;                         /*!< Offset: 0x08  Vector Table Offset Register                          */\r
+  __IO uint32_t AIRCR;                        /*!< Offset: 0x0C  Application Interrupt / Reset Control Register        */\r
+  __IO uint32_t SCR;                          /*!< Offset: 0x10  System Control Register                               */\r
+  __IO uint32_t CCR;                          /*!< Offset: 0x14  Configuration Control Register                        */\r
+  __IO uint8_t  SHP[12];                      /*!< Offset: 0x18  System Handlers Priority Registers (4-7, 8-11, 12-15) */\r
+  __IO uint32_t SHCSR;                        /*!< Offset: 0x24  System Handler Control and State Register             */\r
+  __IO uint32_t CFSR;                         /*!< Offset: 0x28  Configurable Fault Status Register                    */\r
+  __IO uint32_t HFSR;                         /*!< Offset: 0x2C  Hard Fault Status Register                            */\r
+  __IO uint32_t DFSR;                         /*!< Offset: 0x30  Debug Fault Status Register                           */\r
+  __IO uint32_t MMFAR;                        /*!< Offset: 0x34  Mem Manage Address Register                           */\r
+  __IO uint32_t BFAR;                         /*!< Offset: 0x38  Bus Fault Address Register                            */\r
+  __IO uint32_t AFSR;                         /*!< Offset: 0x3C  Auxiliary Fault Status Register                       */\r
+  __I  uint32_t PFR[2];                       /*!< Offset: 0x40  Processor Feature Register                            */\r
+  __I  uint32_t DFR;                          /*!< Offset: 0x48  Debug Feature Register                                */\r
+  __I  uint32_t ADR;                          /*!< Offset: 0x4C  Auxiliary Feature Register                            */\r
+  __I  uint32_t MMFR[4];                      /*!< Offset: 0x50  Memory Model Feature Register                         */\r
+  __I  uint32_t ISAR[5];                      /*!< Offset: 0x60  ISA Feature Register                                  */\r
+} SCB_Type;                                                \r
+\r
+/* SCB CPUID Register Definitions */\r
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */\r
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFul << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */\r
+\r
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */\r
+#define SCB_CPUID_VARIANT_Msk              (0xFul << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */\r
+\r
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */\r
+#define SCB_CPUID_PARTNO_Msk               (0xFFFul << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */\r
+\r
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */\r
+#define SCB_CPUID_REVISION_Msk             (0xFul << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */\r
+\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */\r
+#define SCB_ICSR_NMIPENDSET_Msk            (1ul << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */\r
+#define SCB_ICSR_PENDSVSET_Msk             (1ul << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */\r
+#define SCB_ICSR_PENDSVCLR_Msk             (1ul << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */\r
+\r
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */\r
+#define SCB_ICSR_PENDSTSET_Msk             (1ul << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */\r
+\r
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */\r
+#define SCB_ICSR_PENDSTCLR_Msk             (1ul << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */\r
+\r
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */\r
+#define SCB_ICSR_ISRPREEMPT_Msk            (1ul << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */\r
+\r
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */\r
+#define SCB_ICSR_ISRPENDING_Msk            (1ul << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */\r
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFul << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */\r
+\r
+#define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */\r
+#define SCB_ICSR_RETTOBASE_Msk             (1ul << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */\r
+\r
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */\r
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFul << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */\r
+\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_VTOR_TBLBASE_Pos               29                                             /*!< SCB VTOR: TBLBASE Position */\r
+#define SCB_VTOR_TBLBASE_Msk               (0x1FFul << SCB_VTOR_TBLBASE_Pos)              /*!< SCB VTOR: TBLBASE Mask */\r
+\r
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */\r
+#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFul << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */\r
+\r
+/* SCB Application Interrupt and Reset Control Register Definitions */\r
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */\r
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFul << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */\r
+\r
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */\r
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFul << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
+\r
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */\r
+#define SCB_AIRCR_ENDIANESS_Msk            (1ul << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */\r
+\r
+#define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */\r
+#define SCB_AIRCR_PRIGROUP_Msk             (7ul << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */\r
+\r
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */\r
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1ul << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */\r
+\r
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1ul << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
+\r
+#define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */\r
+#define SCB_AIRCR_VECTRESET_Msk            (1ul << SCB_AIRCR_VECTRESET_Pos)               /*!< SCB AIRCR: VECTRESET Mask */\r
+\r
+/* SCB System Control Register Definitions */\r
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */\r
+#define SCB_SCR_SEVONPEND_Msk              (1ul << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */\r
+\r
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */\r
+#define SCB_SCR_SLEEPDEEP_Msk              (1ul << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */\r
+\r
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */\r
+#define SCB_SCR_SLEEPONEXIT_Msk            (1ul << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */\r
+\r
+/* SCB Configuration Control Register Definitions */\r
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */\r
+#define SCB_CCR_STKALIGN_Msk               (1ul << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */\r
+\r
+#define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */\r
+#define SCB_CCR_BFHFNMIGN_Msk              (1ul << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */\r
+\r
+#define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */\r
+#define SCB_CCR_DIV_0_TRP_Msk              (1ul << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */\r
+\r
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */\r
+#define SCB_CCR_UNALIGN_TRP_Msk            (1ul << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */\r
+\r
+#define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */\r
+#define SCB_CCR_USERSETMPEND_Msk           (1ul << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */\r
+\r
+#define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */\r
+#define SCB_CCR_NONBASETHRDENA_Msk         (1ul << SCB_CCR_NONBASETHRDENA_Pos)            /*!< SCB CCR: NONBASETHRDENA Mask */\r
+\r
+/* SCB System Handler Control and State Register Definitions */\r
+#define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */\r
+#define SCB_SHCSR_USGFAULTENA_Msk          (1ul << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */\r
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1ul << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */\r
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1ul << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */\r
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1ul << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */\r
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1ul << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */\r
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1ul << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */\r
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1ul << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */\r
+#define SCB_SHCSR_SYSTICKACT_Msk           (1ul << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */\r
+\r
+#define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */\r
+#define SCB_SHCSR_PENDSVACT_Msk            (1ul << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */\r
+\r
+#define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */\r
+#define SCB_SHCSR_MONITORACT_Msk           (1ul << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */\r
+\r
+#define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */\r
+#define SCB_SHCSR_SVCALLACT_Msk            (1ul << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */\r
+                                     \r
+#define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */\r
+#define SCB_SHCSR_USGFAULTACT_Msk          (1ul << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */\r
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1ul << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */\r
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1ul << SCB_SHCSR_MEMFAULTACT_Pos)             /*!< SCB SHCSR: MEMFAULTACT Mask */\r
+\r
+/* SCB Configurable Fault Status Registers Definitions */\r
+#define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */\r
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFul << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */\r
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFul << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */\r
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFul << SCB_CFSR_MEMFAULTSR_Pos)            /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\r
+\r
+/* SCB Hard Fault Status Registers Definitions */\r
+#define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */\r
+#define SCB_HFSR_DEBUGEVT_Msk              (1ul << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */\r
+\r
+#define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */\r
+#define SCB_HFSR_FORCED_Msk                (1ul << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */\r
+\r
+#define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */\r
+#define SCB_HFSR_VECTTBL_Msk               (1ul << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */\r
+\r
+/* SCB Debug Fault Status Register Definitions */\r
+#define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */\r
+#define SCB_DFSR_EXTERNAL_Msk              (1ul << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */\r
+\r
+#define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */\r
+#define SCB_DFSR_VCATCH_Msk                (1ul << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */\r
+\r
+#define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */\r
+#define SCB_DFSR_DWTTRAP_Msk               (1ul << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */\r
+\r
+#define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */\r
+#define SCB_DFSR_BKPT_Msk                  (1ul << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */\r
+\r
+#define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */\r
+#define SCB_DFSR_HALTED_Msk                (1ul << SCB_DFSR_HALTED_Pos)                   /*!< SCB DFSR: HALTED Mask */\r
+/*@}*/ /* end of group CMSIS_CM3_SCB */\r
+\r
+\r
+/** @addtogroup CMSIS_CM3_SysTick CMSIS CM3 SysTick\r
+  memory mapped structure for SysTick\r
+  @{\r
+ */\r
+typedef struct\r
+{\r
+  __IO uint32_t CTRL;                         /*!< Offset: 0x00  SysTick Control and Status Register */\r
+  __IO uint32_t LOAD;                         /*!< Offset: 0x04  SysTick Reload Value Register       */\r
+  __IO uint32_t VAL;                          /*!< Offset: 0x08  SysTick Current Value Register      */\r
+  __I  uint32_t CALIB;                        /*!< Offset: 0x0C  SysTick Calibration Register        */\r
+} SysTick_Type;\r
+\r
+/* SysTick Control / Status Register Definitions */\r
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */\r
+#define SysTick_CTRL_COUNTFLAG_Msk         (1ul << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */\r
+\r
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */\r
+#define SysTick_CTRL_CLKSOURCE_Msk         (1ul << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */\r
+\r
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */\r
+#define SysTick_CTRL_TICKINT_Msk           (1ul << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */\r
+\r
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */\r
+#define SysTick_CTRL_ENABLE_Msk            (1ul << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */\r
+\r
+/* SysTick Reload Register Definitions */\r
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */\r
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFul << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */\r
+\r
+/* SysTick Current Register Definitions */\r
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */\r
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFul << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */\r
+\r
+/* SysTick Calibration Register Definitions */\r
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */\r
+#define SysTick_CALIB_NOREF_Msk            (1ul << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */\r
+\r
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */\r
+#define SysTick_CALIB_SKEW_Msk             (1ul << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */\r
+\r
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */\r
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFul << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */\r
+/*@}*/ /* end of group CMSIS_CM3_SysTick */\r
+\r
+\r
+/** @addtogroup CMSIS_CM3_ITM CMSIS CM3 ITM\r
+  memory mapped structure for Instrumentation Trace Macrocell (ITM)\r
+  @{\r
+ */\r
+typedef struct\r
+{\r
+  __O  union  \r
+  {\r
+    __O  uint8_t    u8;                       /*!< Offset:       ITM Stimulus Port 8-bit                   */\r
+    __O  uint16_t   u16;                      /*!< Offset:       ITM Stimulus Port 16-bit                  */\r
+    __O  uint32_t   u32;                      /*!< Offset:       ITM Stimulus Port 32-bit                  */\r
+  }  PORT [32];                               /*!< Offset: 0x00  ITM Stimulus Port Registers               */\r
+       uint32_t RESERVED0[864];                                 \r
+  __IO uint32_t TER;                          /*!< Offset:       ITM Trace Enable Register                 */\r
+       uint32_t RESERVED1[15];                                  \r
+  __IO uint32_t TPR;                          /*!< Offset:       ITM Trace Privilege Register              */\r
+       uint32_t RESERVED2[15];                                  \r
+  __IO uint32_t TCR;                          /*!< Offset:       ITM Trace Control Register                */\r
+       uint32_t RESERVED3[29];                                  \r
+  __IO uint32_t IWR;                          /*!< Offset:       ITM Integration Write Register            */\r
+  __IO uint32_t IRR;                          /*!< Offset:       ITM Integration Read Register             */\r
+  __IO uint32_t IMCR;                         /*!< Offset:       ITM Integration Mode Control Register     */\r
+       uint32_t RESERVED4[43];                                  \r
+  __IO uint32_t LAR;                          /*!< Offset:       ITM Lock Access Register                  */\r
+  __IO uint32_t LSR;                          /*!< Offset:       ITM Lock Status Register                  */\r
+       uint32_t RESERVED5[6];                                   \r
+  __I  uint32_t PID4;                         /*!< Offset:       ITM Peripheral Identification Register #4 */\r
+  __I  uint32_t PID5;                         /*!< Offset:       ITM Peripheral Identification Register #5 */\r
+  __I  uint32_t PID6;                         /*!< Offset:       ITM Peripheral Identification Register #6 */\r
+  __I  uint32_t PID7;                         /*!< Offset:       ITM Peripheral Identification Register #7 */\r
+  __I  uint32_t PID0;                         /*!< Offset:       ITM Peripheral Identification Register #0 */\r
+  __I  uint32_t PID1;                         /*!< Offset:       ITM Peripheral Identification Register #1 */\r
+  __I  uint32_t PID2;                         /*!< Offset:       ITM Peripheral Identification Register #2 */\r
+  __I  uint32_t PID3;                         /*!< Offset:       ITM Peripheral Identification Register #3 */\r
+  __I  uint32_t CID0;                         /*!< Offset:       ITM Component  Identification Register #0 */\r
+  __I  uint32_t CID1;                         /*!< Offset:       ITM Component  Identification Register #1 */\r
+  __I  uint32_t CID2;                         /*!< Offset:       ITM Component  Identification Register #2 */\r
+  __I  uint32_t CID3;                         /*!< Offset:       ITM Component  Identification Register #3 */\r
+} ITM_Type;                                                \r
+\r
+/* ITM Trace Privilege Register Definitions */\r
+#define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */\r
+#define ITM_TPR_PRIVMASK_Msk               (0xFul << ITM_TPR_PRIVMASK_Pos)                /*!< ITM TPR: PRIVMASK Mask */\r
+\r
+/* ITM Trace Control Register Definitions */\r
+#define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */\r
+#define ITM_TCR_BUSY_Msk                   (1ul << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */\r
+\r
+#define ITM_TCR_ATBID_Pos                  16                                             /*!< ITM TCR: ATBID Position */\r
+#define ITM_TCR_ATBID_Msk                  (0x7Ful << ITM_TCR_ATBID_Pos)                  /*!< ITM TCR: ATBID Mask */\r
+\r
+#define ITM_TCR_TSPrescale_Pos              8                                             /*!< ITM TCR: TSPrescale Position */\r
+#define ITM_TCR_TSPrescale_Msk             (3ul << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */\r
+\r
+#define ITM_TCR_SWOENA_Pos                  4                                             /*!< ITM TCR: SWOENA Position */\r
+#define ITM_TCR_SWOENA_Msk                 (1ul << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */\r
+\r
+#define ITM_TCR_DWTENA_Pos                  3                                             /*!< ITM TCR: DWTENA Position */\r
+#define ITM_TCR_DWTENA_Msk                 (1ul << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */\r
+\r
+#define ITM_TCR_SYNCENA_Pos                 2                                             /*!< ITM TCR: SYNCENA Position */\r
+#define ITM_TCR_SYNCENA_Msk                (1ul << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */\r
+\r
+#define ITM_TCR_TSENA_Pos                   1                                             /*!< ITM TCR: TSENA Position */\r
+#define ITM_TCR_TSENA_Msk                  (1ul << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */\r
+\r
+#define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */\r
+#define ITM_TCR_ITMENA_Msk                 (1ul << ITM_TCR_ITMENA_Pos)                    /*!< ITM TCR: ITM Enable bit Mask */\r
+\r
+/* ITM Integration Write Register Definitions */\r
+#define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */\r
+#define ITM_IWR_ATVALIDM_Msk               (1ul << ITM_IWR_ATVALIDM_Pos)                  /*!< ITM IWR: ATVALIDM Mask */\r
+\r
+/* ITM Integration Read Register Definitions */\r
+#define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */\r
+#define ITM_IRR_ATREADYM_Msk               (1ul << ITM_IRR_ATREADYM_Pos)                  /*!< ITM IRR: ATREADYM Mask */\r
+\r
+/* ITM Integration Mode Control Register Definitions */\r
+#define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */\r
+#define ITM_IMCR_INTEGRATION_Msk           (1ul << ITM_IMCR_INTEGRATION_Pos)              /*!< ITM IMCR: INTEGRATION Mask */\r
+\r
+/* ITM Lock Status Register Definitions */\r
+#define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */\r
+#define ITM_LSR_ByteAcc_Msk                (1ul << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */\r
+\r
+#define ITM_LSR_Access_Pos                  1                                             /*!< ITM LSR: Access Position */\r
+#define ITM_LSR_Access_Msk                 (1ul << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */\r
+\r
+#define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */\r
+#define ITM_LSR_Present_Msk                (1ul << ITM_LSR_Present_Pos)                   /*!< ITM LSR: Present Mask */\r
+/*@}*/ /* end of group CMSIS_CM3_ITM */\r
+\r
+\r
+/** @addtogroup CMSIS_CM3_InterruptType CMSIS CM3 Interrupt Type\r
+  memory mapped structure for Interrupt Type\r
+  @{\r
+ */\r
+typedef struct\r
+{\r
+       uint32_t RESERVED0;\r
+  __I  uint32_t ICTR;                         /*!< Offset: 0x04  Interrupt Control Type Register */\r
+  __IO uint32_t ACTLR;                        /*!< Offset: 0x08  Auxiliary Control Register      */\r
+} InterruptType_Type;\r
+\r
+/* Interrupt Controller Type Register Definitions */\r
+#define InterruptType_ICTR_INTLINESNUM_Pos  0                                             /*!< InterruptType ICTR: INTLINESNUM Position */\r
+#define InterruptType_ICTR_INTLINESNUM_Msk (0x1Ful << InterruptType_ICTR_INTLINESNUM_Pos) /*!< InterruptType ICTR: INTLINESNUM Mask */\r
+\r
+/* Auxiliary Control Register Definitions */\r
+#define InterruptType_ACTLR_DISFOLD_Pos     2                                             /*!< InterruptType ACTLR: DISFOLD Position */\r
+#define InterruptType_ACTLR_DISFOLD_Msk    (1ul << InterruptType_ACTLR_DISFOLD_Pos)       /*!< InterruptType ACTLR: DISFOLD Mask */\r
+\r
+#define InterruptType_ACTLR_DISDEFWBUF_Pos  1                                             /*!< InterruptType ACTLR: DISDEFWBUF Position */\r
+#define InterruptType_ACTLR_DISDEFWBUF_Msk (1ul << InterruptType_ACTLR_DISDEFWBUF_Pos)    /*!< InterruptType ACTLR: DISDEFWBUF Mask */\r
+\r
+#define InterruptType_ACTLR_DISMCYCINT_Pos  0                                             /*!< InterruptType ACTLR: DISMCYCINT Position */\r
+#define InterruptType_ACTLR_DISMCYCINT_Msk (1ul << InterruptType_ACTLR_DISMCYCINT_Pos)    /*!< InterruptType ACTLR: DISMCYCINT Mask */\r
+/*@}*/ /* end of group CMSIS_CM3_InterruptType */\r
+\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)\r
+/** @addtogroup CMSIS_CM3_MPU CMSIS CM3 MPU\r
+  memory mapped structure for Memory Protection Unit (MPU)\r
+  @{\r
+ */\r
+typedef struct\r
+{\r
+  __I  uint32_t TYPE;                         /*!< Offset: 0x00  MPU Type Register                              */\r
+  __IO uint32_t CTRL;                         /*!< Offset: 0x04  MPU Control Register                           */\r
+  __IO uint32_t RNR;                          /*!< Offset: 0x08  MPU Region RNRber Register                     */\r
+  __IO uint32_t RBAR;                         /*!< Offset: 0x0C  MPU Region Base Address Register               */\r
+  __IO uint32_t RASR;                         /*!< Offset: 0x10  MPU Region Attribute and Size Register         */\r
+  __IO uint32_t RBAR_A1;                      /*!< Offset: 0x14  MPU Alias 1 Region Base Address Register       */\r
+  __IO uint32_t RASR_A1;                      /*!< Offset: 0x18  MPU Alias 1 Region Attribute and Size Register */\r
+  __IO uint32_t RBAR_A2;                      /*!< Offset: 0x1C  MPU Alias 2 Region Base Address Register       */\r
+  __IO uint32_t RASR_A2;                      /*!< Offset: 0x20  MPU Alias 2 Region Attribute and Size Register */\r
+  __IO uint32_t RBAR_A3;                      /*!< Offset: 0x24  MPU Alias 3 Region Base Address Register       */\r
+  __IO uint32_t RASR_A3;                      /*!< Offset: 0x28  MPU Alias 3 Region Attribute and Size Register */\r
+} MPU_Type;                                                \r
+\r
+/* MPU Type Register */\r
+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */\r
+#define MPU_TYPE_IREGION_Msk               (0xFFul << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */\r
+\r
+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */\r
+#define MPU_TYPE_DREGION_Msk               (0xFFul << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */\r
+\r
+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */\r
+#define MPU_TYPE_SEPARATE_Msk              (1ul << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */\r
+\r
+/* MPU Control Register */\r
+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */\r
+#define MPU_CTRL_PRIVDEFENA_Msk            (1ul << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */\r
+\r
+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */\r
+#define MPU_CTRL_HFNMIENA_Msk              (1ul << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */\r
+\r
+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */\r
+#define MPU_CTRL_ENABLE_Msk                (1ul << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */\r
+\r
+/* MPU Region Number Register */\r
+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */\r
+#define MPU_RNR_REGION_Msk                 (0xFFul << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */\r
+\r
+/* MPU Region Base Address Register */\r
+#define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */\r
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFul << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */\r
+\r
+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */\r
+#define MPU_RBAR_VALID_Msk                 (1ul << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */\r
+\r
+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */\r
+#define MPU_RBAR_REGION_Msk                (0xFul << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */\r
+\r
+/* MPU Region Attribute and Size Register */\r
+#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: XN Position */\r
+#define MPU_RASR_XN_Msk                    (1ul << MPU_RASR_XN_Pos)                       /*!< MPU RASR: XN Mask */\r
+\r
+#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: AP Position */\r
+#define MPU_RASR_AP_Msk                    (7ul << MPU_RASR_AP_Pos)                       /*!< MPU RASR: AP Mask */\r
+\r
+#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: TEX Position */\r
+#define MPU_RASR_TEX_Msk                   (7ul << MPU_RASR_TEX_Pos)                      /*!< MPU RASR: TEX Mask */\r
+\r
+#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: Shareable bit Position */\r
+#define MPU_RASR_S_Msk                     (1ul << MPU_RASR_S_Pos)                        /*!< MPU RASR: Shareable bit Mask */\r
+\r
+#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: Cacheable bit Position */\r
+#define MPU_RASR_C_Msk                     (1ul << MPU_RASR_C_Pos)                        /*!< MPU RASR: Cacheable bit Mask */\r
+\r
+#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: Bufferable bit Position */\r
+#define MPU_RASR_B_Msk                     (1ul << MPU_RASR_B_Pos)                        /*!< MPU RASR: Bufferable bit Mask */\r
+\r
+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */\r
+#define MPU_RASR_SRD_Msk                   (0xFFul << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */\r
+\r
+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */\r
+#define MPU_RASR_SIZE_Msk                  (0x1Ful << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */\r
+\r
+#define MPU_RASR_ENA_Pos                     0                                            /*!< MPU RASR: Region enable bit Position */\r
+#define MPU_RASR_ENA_Msk                    (0x1Ful << MPU_RASR_ENA_Pos)                  /*!< MPU RASR: Region enable bit Disable Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_CM3_MPU */\r
+#endif\r
+\r
+\r
+/** @addtogroup CMSIS_CM3_CoreDebug CMSIS CM3 Core Debug\r
+  memory mapped structure for Core Debug Register\r
+  @{\r
+ */\r
+typedef struct\r
+{\r
+  __IO uint32_t DHCSR;                        /*!< Offset: 0x00  Debug Halting Control and Status Register    */\r
+  __O  uint32_t DCRSR;                        /*!< Offset: 0x04  Debug Core Register Selector Register        */\r
+  __IO uint32_t DCRDR;                        /*!< Offset: 0x08  Debug Core Register Data Register            */\r
+  __IO uint32_t DEMCR;                        /*!< Offset: 0x0C  Debug Exception and Monitor Control Register */\r
+} CoreDebug_Type;\r
+\r
+/* Debug Halting Control and Status Register */\r
+#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */\r
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFul << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */\r
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1ul << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1ul << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */\r
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1ul << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */\r
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1ul << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */\r
+#define CoreDebug_DHCSR_S_HALT_Msk         (1ul << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */\r
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1ul << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */\r
+\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1ul << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\r
+\r
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */\r
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1ul << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */\r
+\r
+#define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */\r
+#define CoreDebug_DHCSR_C_STEP_Msk         (1ul << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */\r
+\r
+#define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */\r
+#define CoreDebug_DHCSR_C_HALT_Msk         (1ul << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1ul << CoreDebug_DHCSR_C_DEBUGEN_Pos)         /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r
+\r
+/* Debug Core Register Selector Register */\r
+#define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */\r
+#define CoreDebug_DCRSR_REGWnR_Msk         (1ul << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */\r
+\r
+#define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */\r
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1Ful << CoreDebug_DCRSR_REGSEL_Pos)         /*!< CoreDebug DCRSR: REGSEL Mask */\r
+\r
+/* Debug Exception and Monitor Control Register */\r
+#define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */\r
+#define CoreDebug_DEMCR_TRCENA_Msk         (1ul << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */\r
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1ul << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */\r
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1ul << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */\r
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1ul << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */\r
+#define CoreDebug_DEMCR_MON_EN_Msk         (1ul << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */\r
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1ul << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */\r
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1ul << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */\r
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1ul << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */\r
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1ul << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */\r
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1ul << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1ul << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */\r
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1ul << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */\r
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1ul << CoreDebug_DEMCR_VC_CORERESET_Pos)      /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r
+/*@}*/ /* end of group CMSIS_CM3_CoreDebug */\r
+\r
+\r
+/* Memory mapping of Cortex-M3 Hardware */\r
+#define SCS_BASE            (0xE000E000)                              /*!< System Control Space Base Address */\r
+#define ITM_BASE            (0xE0000000)                              /*!< ITM Base Address                  */\r
+#define CoreDebug_BASE      (0xE000EDF0)                              /*!< Core Debug Base Address           */\r
+#define SysTick_BASE        (SCS_BASE +  0x0010)                      /*!< SysTick Base Address              */\r
+#define NVIC_BASE           (SCS_BASE +  0x0100)                      /*!< NVIC Base Address                 */\r
+#define SCB_BASE            (SCS_BASE +  0x0D00)                      /*!< System Control Block Base Address */\r
+\r
+#define InterruptType       ((InterruptType_Type *) SCS_BASE)         /*!< Interrupt Type Register           */\r
+#define SCB                 ((SCB_Type *)           SCB_BASE)         /*!< SCB configuration struct          */\r
+#define SysTick             ((SysTick_Type *)       SysTick_BASE)     /*!< SysTick configuration struct      */\r
+#define NVIC                ((NVIC_Type *)          NVIC_BASE)        /*!< NVIC configuration struct         */\r
+#define ITM                 ((ITM_Type *)           ITM_BASE)         /*!< ITM configuration struct          */\r
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct   */\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)\r
+  #define MPU_BASE          (SCS_BASE +  0x0D90)                      /*!< Memory Protection Unit            */\r
+  #define MPU               ((MPU_Type*)            MPU_BASE)         /*!< Memory Protection Unit            */\r
+#endif\r
+\r
+/*@}*/ /* end of group CMSIS_CM3_core_register */\r
+\r
+\r
+/*******************************************************************************\r
+ *                Hardware Abstraction Layer\r
+ ******************************************************************************/\r
+\r
+#if defined ( __CC_ARM   )\r
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */\r
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */\r
+\r
+#elif defined ( __ICCARM__ )\r
+  #define __ASM           __asm                                       /*!< asm keyword for IAR Compiler          */\r
+  #define __INLINE        inline                                      /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */\r
+\r
+#elif defined   (  __GNUC__  )\r
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */\r
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */\r
+\r
+#elif defined   (  __TASKING__  )\r
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */\r
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */\r
+\r
+#endif\r
+\r
+/* ##########################  Core Instruction Access  ######################### */\r
+#include "core_cmInstr.h"\r
+\r
+/* ###########################  Core Function Access  ########################### */\r
+#include "core_cmFunc.h"\r
+\r
+\r
+/** @addtogroup CMSIS_CM3_Core_FunctionInterface CMSIS CM3 Core Function Interface\r
+  Core  Function Interface containing:\r
+  - Core NVIC Functions\r
+  - Core SysTick Functions\r
+  - Core Reset Functions\r
+*/\r
+/*@{*/\r
+\r
+/* ##########################   NVIC functions  #################################### */\r
+\r
+/**\r
+ * @brief  Set the Priority Grouping in NVIC Interrupt Controller\r
+ *\r
+ * @param  PriorityGroup is priority grouping field\r
+ *\r
+ * Set the priority grouping field using the required unlock sequence.\r
+ * The parameter priority_grouping is assigned to the field \r
+ * SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used.\r
+ * In case of a conflict between priority grouping and available\r
+ * priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r
+ */\r
+static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r
+{\r
+  uint32_t reg_value;\r
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);                         /* only values 0..7 are used          */\r
+  \r
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */\r
+  reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk);             /* clear bits to change               */\r
+  reg_value  =  (reg_value                       |\r
+                (0x5FA << SCB_AIRCR_VECTKEY_Pos) | \r
+                (PriorityGroupTmp << 8));                                     /* Insert write key and priorty group */\r
+  SCB->AIRCR =  reg_value;\r
+}\r
+\r
+/**\r
+ * @brief  Get the Priority Grouping from NVIC Interrupt Controller\r
+ *\r
+ * @return priority grouping field \r
+ *\r
+ * Get the priority grouping from NVIC Interrupt Controller.\r
+ * priority grouping is SCB->AIRCR [10:8] PRIGROUP field.\r
+ */\r
+static __INLINE uint32_t NVIC_GetPriorityGrouping(void)\r
+{\r
+  return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos);   /* read priority grouping field */\r
+}\r
+\r
+/**\r
+ * @brief  Enable Interrupt in NVIC Interrupt Controller\r
+ *\r
+ * @param  IRQn   The positive number of the external interrupt to enable\r
+ *\r
+ * Enable a device specific interupt in the NVIC interrupt controller.\r
+ * The interrupt number cannot be a negative value.\r
+ */\r
+static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)\r
+{\r
+  NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */\r
+}\r
+\r
+/**\r
+ * @brief  Disable the interrupt line for external interrupt specified\r
+ * \r
+ * @param  IRQn   The positive number of the external interrupt to disable\r
+ * \r
+ * Disable a device specific interupt in the NVIC interrupt controller.\r
+ * The interrupt number cannot be a negative value.\r
+ */\r
+static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)\r
+{\r
+  NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */\r
+}\r
+\r
+/**\r
+ * @brief  Read the interrupt pending bit for a device specific interrupt source\r
+ * \r
+ * @param  IRQn    The number of the device specifc interrupt\r
+ * @return         1 = interrupt pending, 0 = interrupt not pending\r
+ *\r
+ * Read the pending register in NVIC and return 1 if its status is pending, \r
+ * otherwise it returns 0\r
+ */\r
+static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+  return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */\r
+}\r
+\r
+/**\r
+ * @brief  Set the pending bit for an external interrupt\r
+ * \r
+ * @param  IRQn    The number of the interrupt for set pending\r
+ *\r
+ * Set the pending bit for the specified interrupt.\r
+ * The interrupt number cannot be a negative value.\r
+ */\r
+static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+  NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */\r
+}\r
+\r
+/**\r
+ * @brief  Clear the pending bit for an external interrupt\r
+ *\r
+ * @param  IRQn    The number of the interrupt for clear pending\r
+ *\r
+ * Clear the pending bit for the specified interrupt. \r
+ * The interrupt number cannot be a negative value.\r
+ */\r
+static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
+{\r
+  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */\r
+}\r
+\r
+/**\r
+ * @brief  Read the active bit for an external interrupt\r
+ *\r
+ * @param  IRQn    The number of the interrupt for read active bit\r
+ * @return         1 = interrupt active, 0 = interrupt not active\r
+ *\r
+ * Read the active register in NVIC and returns 1 if its status is active, \r
+ * otherwise it returns 0.\r
+ */\r
+static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)\r
+{\r
+  return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */\r
+}\r
+\r
+/**\r
+ * @brief  Set the priority for an interrupt\r
+ *\r
+ * @param  IRQn      The number of the interrupt for set priority\r
+ * @param  priority  The priority to set\r
+ *\r
+ * Set the priority for the specified interrupt. The interrupt \r
+ * number can be positive to specify an external (device specific) \r
+ * interrupt, or negative to specify an internal (core) interrupt.\r
+ *\r
+ * Note: The priority cannot be set for every core interrupt.\r
+ */\r
+static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
+{\r
+  if(IRQn < 0) {\r
+    SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M3 System Interrupts */\r
+  else {\r
+    NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);    }        /* set Priority for device specific Interrupts  */\r
+}\r
+\r
+/**\r
+ * @brief  Read the priority for an interrupt\r
+ *\r
+ * @param  IRQn      The number of the interrupt for get priority\r
+ * @return           The priority for the interrupt\r
+ *\r
+ * Read the priority for the specified interrupt. The interrupt \r
+ * number can be positive to specify an external (device specific) \r
+ * interrupt, or negative to specify an internal (core) interrupt.\r
+ *\r
+ * The returned priority value is automatically aligned to the implemented\r
+ * priority bits of the microcontroller.\r
+ *\r
+ * Note: The priority cannot be set for every core interrupt.\r
+ */\r
+static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)\r
+{\r
+\r
+  if(IRQn < 0) {\r
+    return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M3 system interrupts */\r
+  else {\r
+    return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)]           >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */\r
+}\r
+\r
+\r
+/**\r
+ * @brief  Encode the priority for an interrupt\r
+ *\r
+ * @param  PriorityGroup    The used priority group\r
+ * @param  PreemptPriority  The preemptive priority value (starting from 0)\r
+ * @param  SubPriority      The sub priority value (starting from 0)\r
+ * @return                  The encoded priority for the interrupt\r
+ *\r
+ * Encode the priority for an interrupt with the given priority group,\r
+ * preemptive priority value and sub priority value.\r
+ * In case of a conflict between priority grouping and available\r
+ * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.\r
+ *\r
+ * The returned priority value can be used for NVIC_SetPriority(...) function\r
+ */\r
+static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
+{\r
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */\r
+  uint32_t PreemptPriorityBits;\r
+  uint32_t SubPriorityBits;\r
+\r
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;\r
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;\r
+ \r
+  return (\r
+           ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |\r
+           ((SubPriority     & ((1 << (SubPriorityBits    )) - 1)))\r
+         );\r
+}\r
+\r
+\r
+/**\r
+ * @brief  Decode the priority of an interrupt\r
+ *\r
+ * @param  Priority           The priority for the interrupt\r
+ * @param  PriorityGroup      The used priority group\r
+ * @param  pPreemptPriority   The preemptive priority value (starting from 0)\r
+ * @param  pSubPriority       The sub priority value (starting from 0)\r
+ *\r
+ * Decode an interrupt priority value with the given priority group to \r
+ * preemptive priority value and sub priority value.\r
+ * In case of a conflict between priority grouping and available\r
+ * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.\r
+ *\r
+ * The priority value can be retrieved with NVIC_GetPriority(...) function\r
+ */\r
+static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)\r
+{\r
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */\r
+  uint32_t PreemptPriorityBits;\r
+  uint32_t SubPriorityBits;\r
+\r
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;\r
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;\r
+  \r
+  *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);\r
+  *pSubPriority     = (Priority                   ) & ((1 << (SubPriorityBits    )) - 1);\r
+}\r
+\r
+\r
+\r
+/* ##################################    SysTick function  ############################################ */\r
+\r
+#if (!defined (__Vendor_SysTickConfig)) || (__Vendor_SysTickConfig == 0)\r
+\r
+/**\r
+ * @brief  Initialize and start the SysTick counter and its interrupt.\r
+ *\r
+ * @param   ticks   number of ticks between two interrupts\r
+ * @return  1 = failed, 0 = successful\r
+ *\r
+ * Initialise the system tick timer and its interrupt and start the\r
+ * system tick timer / counter in free running mode to generate \r
+ * periodical interrupts.\r
+ */\r
+static __INLINE uint32_t SysTick_Config(uint32_t ticks)\r
+{ \r
+  if (ticks > SysTick_LOAD_RELOAD_Msk)  return (1);            /* Reload value impossible */\r
+                                                               \r
+  SysTick->LOAD  = (ticks & SysTick_LOAD_RELOAD_Msk) - 1;      /* set reload register */\r
+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Cortex-M0 System Interrupts */\r
+  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */\r
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk | \r
+                   SysTick_CTRL_TICKINT_Msk   | \r
+                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */\r
+  return (0);                                                  /* Function successful */\r
+}\r
+\r
+#endif\r
+\r
+\r
+\r
+\r
+/* ##################################    Reset function  ############################################ */\r
+\r
+/**\r
+ * @brief  Initiate a system reset request.\r
+ *\r
+ * Initiate a system reset request to reset the MCU\r
+ */\r
+static __INLINE void NVIC_SystemReset(void)\r
+{\r
+  __DSB();                                                     /* Ensure all outstanding memory accesses included\r
+                                                                  buffered write are completed before reset */              \r
+  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      | \r
+                 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | \r
+                 SCB_AIRCR_SYSRESETREQ_Msk);                   /* Keep priority group unchanged */\r
+  __DSB();                                                     /* Ensure completion of memory access */              \r
+  while(1);                                                    /* wait until reset */\r
+}\r
+\r
+/*@}*/ /* end of group CMSIS_CM3_Core_FunctionInterface */\r
+\r
+\r
+\r
+/* ##################################### Debug In/Output function ########################################### */\r
+\r
+/** @addtogroup CMSIS_CM3_CoreDebugInterface CMSIS CM3 Core Debug Interface\r
+  Core Debug Interface containing:\r
+  - Core Debug Receive / Transmit Functions\r
+  - Core Debug Defines\r
+  - Core Debug Variables\r
+*/\r
+/*@{*/\r
+\r
+extern volatile int ITM_RxBuffer;                    /*!< variable to receive characters                             */\r
+#define             ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */\r
+\r
+\r
+/**\r
+ * @brief  Outputs a character via the ITM channel 0\r
+ *\r
+ * @param  ch   character to output\r
+ * @return      character to output\r
+ *\r
+ * The function outputs a character via the ITM channel 0. \r
+ * The function returns when no debugger is connected that has booked the output.  \r
+ * It is blocking when a debugger is connected, but the previous character send is not transmitted. \r
+ */\r
+static __INLINE uint32_t ITM_SendChar (uint32_t ch)\r
+{\r
+  if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk)  &&      /* Trace enabled */\r
+      (ITM->TCR & ITM_TCR_ITMENA_Msk)                  &&      /* ITM enabled */\r
+      (ITM->TER & (1ul << 0)        )                    )     /* ITM Port #0 enabled */\r
+  {\r
+    while (ITM->PORT[0].u32 == 0);\r
+    ITM->PORT[0].u8 = (uint8_t) ch;\r
+  }  \r
+  return (ch);\r
+}\r
+\r
+\r
+/**\r
+ * @brief  Inputs a character via variable ITM_RxBuffer\r
+ *\r
+ * @return      received character, -1 = no character received\r
+ *\r
+ * The function inputs a character via variable ITM_RxBuffer. \r
+ * The function returns when no debugger is connected that has booked the output.  \r
+ * It is blocking when a debugger is connected, but the previous character send is not transmitted. \r
+ */\r
+static __INLINE int ITM_ReceiveChar (void) {\r
+  int ch = -1;                               /* no character available */\r
+\r
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {\r
+    ch = ITM_RxBuffer;\r
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */\r
+  }\r
+  \r
+  return (ch); \r
+}\r
+\r
+\r
+/**\r
+ * @brief  Check if a character via variable ITM_RxBuffer is available\r
+ *\r
+ * @return      1 = character available, 0 = no character available\r
+ *\r
+ * The function checks  variable ITM_RxBuffer whether a character is available or not. \r
+ * The function returns '1' if a character is available and '0' if no character is available. \r
+ */\r
+static __INLINE int ITM_CheckChar (void) {\r
+\r
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {\r
+    return (0);                                 /* no character available */\r
+  } else {\r
+    return (1);                                 /*    character available */\r
+  }\r
+}\r
+\r
+/*@}*/ /* end of group CMSIS_CM3_core_DebugInterface */\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+/*@}*/ /* end of group CMSIS_CM3_core_definitions */\r
+\r
+#endif /* __CORE_CM3_H__ */\r
+\r
+/*lint -restore */\r

diff --git a/Demo/CORTEX_MB9B500_IAR_Keil/Fujitu_source/mb9bf506n.h b/Demo/CORTEX_MB9B500_IAR_Keil/Fujitu_source/mb9bf506n.h
new file mode 100644 (file)
index 0000000..fa2a724
--- /dev/null
+++ b/Demo/CORTEX_MB9B500_IAR_Keil/Fujitu_source/mb9bf506n.h
@@ -0,0 +1,9465 @@
+/************************************************************************/\r
+/*               (C) Fujitsu Semiconductor Europe GmbH (FSEU)           */\r
+/*                                                                      */\r
+/* The following software deliverable is intended for and must only be  */\r
+/* used for reference and in an evaluation laboratory environment.      */\r
+/* It is provided on an as-is basis without charge and is subject to    */\r
+/* alterations.                                                         */\r
+/* It is the user's obligation to fully test the software in its        */\r
+/* environment and to ensure proper functionality, qualification and    */\r
+/* compliance with component specifications.                            */\r
+/*                                                                      */\r
+/* In the event the software deliverable includes the use of open       */\r
+/* source components, the provisions of the governing open source       */\r
+/* license agreement shall apply with respect to such software          */\r
+/* deliverable.                                                         */\r
+/* FSEU does not warrant that the deliverables do not infringe any      */\r
+/* third party intellectual property right (IPR). In the event that     */\r
+/* the deliverables infringe a third party IPR it is the sole           */\r
+/* responsibility of the customer to obtain necessary licenses to       */\r
+/* continue the usage of the deliverable.                               */\r
+/*                                                                      */\r
+/* To the maximum extent permitted by applicable law FSEU disclaims all */\r
+/* warranties, whether express or implied, in particular, but not       */\r
+/* limited to, warranties of merchantability and fitness for a          */\r
+/* particular purpose for which the deliverable is not designated.      */\r
+/*                                                                      */\r
+/* To the maximum extent permitted by applicable law, FSEU's liability  */\r
+/* is restricted to intentional misconduct and gross negligence.        */\r
+/* FSEU is not liable for consequential damages.                        */\r
+/*                                                                      */\r
+/* (V1.5)                                                               */\r
+/************************************************************************/\r
+/*                                                                      */\r
+/*  Header File for Device MB9BF506N                                    */\r
+/*  Version V1.00                                                       */\r
+/*  Date    2011-01-21                                                  */\r
+/*                                                                      */\r
+/************************************************************************/\r
+\r
+#ifndef _MB9BF506N_H_\r
+#define _MB9BF506N_H_\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif \r
+\r
+\r
+/******************************************************************************\r
+ * Configuration of the Cortex-M3 Processor and Core Peripherals\r
+ ******************************************************************************/\r
+#define __MPU_PRESENT           1 /* FM3 provide an MPU                           */\r
+#define __NVIC_PRIO_BITS        4 /* FM3 uses 4 Bits for the Priority Levels      */\r
+#define __Vendor_SysTickConfig  0 /* Set to 1 if different SysTick Config is used */\r
+\r
+\r
+/******************************************************************************\r
+ * Interrupt Number Definition\r
+ ******************************************************************************/\r
+typedef enum IRQn\r
+{\r
+    NMI_IRQn          = -14, /*  2 Non Maskable      */\r
+    HardFault_IRQn    = -13, /*  3 Hard Fault        */\r
+    MemManage_IRQn    = -12, /*  4 Memory Management */\r
+    BusFault_IRQn     = -11, /*  5 Bus Fault         */\r
+    UsageFault_IRQn   = -10, /*  6 Usage Fault       */\r
+    SVC_IRQn          = -5,  /* 11 SV Call           */\r
+    DebugMonitor_IRQn = -4,  /* 12 Debug Monitor     */\r
+    PendSVC_IRQn      = -2,  /* 14 Pend SV           */\r
+    SysTick_IRQn      = -1,  /* 15 System Tick       */\r
+\r
+    CSV_IRQn          = 0,   /* Clock Super Visor                        */\r
+    SWDT_IRQn         = 1,   /* Software Watchdog Timer                  */\r
+    LVD_IRQn          = 2,   /* Low Voltage Detector                     */\r
+    WFG_IRQn          = 3,   /* Wave Form Generator                      */\r
+    EXINT0_7_IRQn     = 4,   /* External Interrupt Request ch.0 to ch.7  */\r
+    EXINT8_15_IRQn    = 5,   /* External Interrupt Request ch.8 to ch.15 */\r
+    DTIM_QDU_IRQn     = 6,   /* Dual Timer / Quad Decoder                */\r
+    MFS0RX_IRQn       = 7,   /* MultiFunction Serial ch.0                */\r
+    MFS0TX_IRQn       = 8,   /* MultiFunction Serial ch.0                */\r
+    MFS1RX_IRQn       = 9,   /* MultiFunction Serial ch.1                */\r
+    MFS1TX_IRQn       = 10,  /* MultiFunction Serial ch.1                */\r
+    MFS2RX_IRQn       = 11,  /* MultiFunction Serial ch.2                */\r
+    MFS2TX_IRQn       = 12,  /* MultiFunction Serial ch.2                */\r
+    MFS3RX_IRQn       = 13,  /* MultiFunction Serial ch.3                */\r
+    MFS3TX_IRQn       = 14,  /* MultiFunction Serial ch.3                */\r
+    MFS4RX_IRQn       = 15,  /* MultiFunction Serial ch.4                */\r
+    MFS4TX_IRQn       = 16,  /* MultiFunction Serial ch.4                */\r
+    MFS5RX_IRQn       = 17,  /* MultiFunction Serial ch.5                */\r
+    MFS5TX_IRQn       = 18,  /* MultiFunction Serial ch.5                */\r
+    MFS6RX_IRQn       = 19,  /* MultiFunction Serial ch.6                */\r
+    MFS6TX_IRQn       = 20,  /* MultiFunction Serial ch.6                */\r
+    MFS7RX_IRQn       = 21,  /* MultiFunction Serial ch.7                */\r
+    MFS7TX_IRQn       = 22,  /* MultiFunction Serial ch.7                */\r
+    PPG_IRQn          = 23,  /* PPG                                      */\r
+    OSC_PLL_WC_IRQn   = 24,  /* OSC / PLL / Watch Counter                */\r
+    ADC0_IRQn         = 25,  /* ADC0                                     */\r
+    ADC1_IRQn         = 26,  /* ADC1                                     */\r
+    ADC2_IRQn         = 27,  /* ADC2                                     */\r
+    FRTIM_IRQn        = 28,  /* Free-run Timer                           */\r
+    INCAP_IRQn        = 29,  /* Input Capture                            */\r
+    OUTCOMP_IRQn      = 30,  /* Output Compare                           */\r
+    BTIM_IRQn         = 31,  /* Base Timer ch.0 to ch.7                  */\r
+    CAN0_IRQn         = 32,  /* CAN ch.0                                 */\r
+    CAN1_IRQn         = 33,  /* CAN ch.1                                 */\r
+    USBF_IRQn         = 34,  /* USB Function                             */\r
+    USBF_USBH_IRQn    = 35,  /* USB Function / USB HOST                  */\r
+    /* Reserved       = 36,                                              */\r
+    /* Reserved       = 37,                                              */\r
+    DMAC0_IRQn        = 38,  /* DMAC ch.0                                */\r
+    DMAC1_IRQn        = 39,  /* DMAC ch.1                                */\r
+    DMAC2_IRQn        = 40,  /* DMAC ch.2                                */\r
+    DMAC3_IRQn        = 41,  /* DMAC ch.3                                */\r
+    DMAC4_IRQn        = 42,  /* DMAC ch.4                                */\r
+    DMAC5_IRQn        = 43,  /* DMAC ch.5                                */\r
+    DMAC6_IRQn        = 44,  /* DMAC ch.6                                */\r
+    DMAC7_IRQn        = 45,  /* DMAC ch.7                                */\r
+    /* Reserved       = 46,                                              */\r
+    /* Reserved       = 47,                                              */\r
+} IRQn_Type;\r
+\r
+\r
+#include "core_cm3.h"\r
+#include "system_mb9bf50x.h"\r
+#include <stdint.h>\r
+\r
+#define SUCCESS  0\r
+#define ERROR    -1\r
+\r
+#ifndef NULL\r
+#define NULL 0\r
+#endif\r
+\r
+\r
+/******************************************************************************/\r
+/*                Device Specific Peripheral Registers structures             */\r
+/******************************************************************************/\r
+\r
+#if defined ( __CC_ARM   )\r
+#pragma anon_unions\r
+#endif\r
+\r
+/******************************************************************************\r
+ * Flash_IF_MODULE\r
+ ******************************************************************************/\r
+/* Flash interface registers */\r
+typedef struct\r
+{\r
+  __IO uint32_t FASZR;\r
+  __IO uint32_t FRWTR;\r
+  __IO uint32_t FSTR;\r
+        uint8_t RESERVED0[4];\r
+  __IO uint32_t FSYNDN;\r
+        uint8_t RESERVED1[236];\r
+  __IO uint32_t CRTRMM;\r
+}FM3_FIF_TypeDef;\r
+\r
+/******************************************************************************\r
+ * Clock_Reset_MODULE\r
+ ******************************************************************************/\r
+/* Clock and reset registers */\r
+typedef struct\r
+{\r
+  __IO  uint8_t SCM_CTL;\r
+        uint8_t RESERVED0[3];\r
+  __IO  uint8_t SCM_STR;\r
+        uint8_t RESERVED1[3];\r
+  __IO uint32_t STB_CTL;\r
+  __IO uint16_t RST_STR;\r
+        uint8_t RESERVED2[2];\r
+  __IO  uint8_t BSC_PSR;\r
+        uint8_t RESERVED3[3];\r
+  __IO  uint8_t APBC0_PSR;\r
+        uint8_t RESERVED4[3];\r
+  __IO  uint8_t APBC1_PSR;\r
+        uint8_t RESERVED5[3];\r
+  __IO  uint8_t APBC2_PSR;\r
+        uint8_t RESERVED6[3];\r
+  __IO  uint8_t SWC_PSR;\r
+        uint8_t RESERVED7[7];\r
+  __IO  uint8_t TTC_PSR;\r
+        uint8_t RESERVED8[7];\r
+  __IO  uint8_t CSW_TMR;\r
+        uint8_t RESERVED9[3];\r
+  __IO  uint8_t PSW_TMR;\r
+        uint8_t RESERVED10[3];\r
+  __IO  uint8_t PLL_CTL1;\r
+        uint8_t RESERVED11[3];\r
+  __IO  uint8_t PLL_CTL2;\r
+        uint8_t RESERVED12[3];\r
+  __IO uint16_t CSV_CTL;\r
+        uint8_t RESERVED13[2];\r
+  __IO  uint8_t CSV_STR;\r
+        uint8_t RESERVED14[3];\r
+  __IO uint16_t FCSWH_CTL;\r
+        uint8_t RESERVED15[2];\r
+  __IO uint16_t FCSWL_CTL;\r
+        uint8_t RESERVED16[2];\r
+  __IO uint16_t FCSWD_CTL;\r
+        uint8_t RESERVED17[2];\r
+  __IO  uint8_t DBWDT_CTL;\r
+        uint8_t RESERVED18[11];\r
+  __IO  uint8_t INT_ENR;\r
+        uint8_t RESERVED19[3];\r
+  __IO  uint8_t INT_STR;\r
+        uint8_t RESERVED20[3];\r
+  __IO  uint8_t INT_CLR;\r
+}FM3_CRG_TypeDef;\r
+\r
+/******************************************************************************\r
+ * HWWDT_MODULE\r
+ ******************************************************************************/\r
+/* Hardware watchdog registers */\r
+typedef struct\r
+{\r
+  __IO uint32_t WDG_LDR;\r
+  __IO uint32_t WDG_VLR;\r
+  __IO  uint8_t WDG_CTL;\r
+        uint8_t RESERVED0[3];\r
+  __IO  uint8_t WDG_ICL;\r
+        uint8_t RESERVED1[3];\r
+  __IO  uint8_t WDG_RIS;\r
+        uint8_t RESERVED2[3055];\r
+  __IO uint32_t WDG_LCK;\r
+}FM3_HWWDT_TypeDef;\r
+\r
+/******************************************************************************\r
+ * SWWDT_MODULE\r
+ ******************************************************************************/\r
+/* Software watchdog registers */\r
+typedef struct\r
+{\r
+  __IO uint32_t WDOGLOAD;\r
+  __IO uint32_t WDOGVALUE;\r
+  __IO  uint8_t WDOGCONTROL;\r
+        uint8_t RESERVED0[3];\r
+  __IO uint32_t WDOGINTCLR;\r
+  __IO  uint8_t WDOGRIS;\r
+        uint8_t RESERVED1[3055];\r
+  __IO uint32_t WDOGLOCK;\r
+}FM3_SWWDT_TypeDef;\r
+\r
+/******************************************************************************\r
+ * DTIM_MODULE\r
+ ******************************************************************************/\r
+/* Dual timer 1/2 registers */\r
+typedef struct\r
+{\r
+  __IO uint32_t TIMER1LOAD;\r
+  __IO uint32_t TIMER1VALUE;\r
+  __IO uint32_t TIMER1CONTROL;\r
+  __IO uint32_t TIMER1INTCLR;\r
+  __IO uint32_t TIMER1RIS;\r
+  __IO uint32_t TIMER1MIS;\r
+  __IO uint32_t TIMER1BGLOAD;\r
+        uint8_t RESERVED0[4];\r
+  __IO uint32_t TIMER2LOAD;\r
+  __IO uint32_t TIMER2VALUE;\r
+  __IO uint32_t TIMER2CONTROL;\r
+  __IO uint32_t TIMER2INTCLR;\r
+  __IO uint32_t TIMER2RIS;\r
+  __IO uint32_t TIMER2MIS;\r
+  __IO uint32_t TIMER2BGLOAD;\r
+}FM3_DTIM_TypeDef;\r
+\r
+/******************************************************************************\r
+ * MFT_FRT_MODULE\r
+ ******************************************************************************/\r
+/* Multifunction Timer unit 0 Free Running Timer registers */\r
+typedef struct\r
+{\r
+        uint8_t RESERVED0[40];\r
+  __IO uint16_t TCCP0;\r
+        uint8_t RESERVED1[2];\r
+  __IO uint16_t TCDT0;\r
+        uint8_t RESERVED2[2];\r
+  __IO uint16_t TCSA0;\r
+        uint8_t RESERVED3[2];\r
+  __IO uint16_t TCSB0;\r
+        uint8_t RESERVED4[2];\r
+  __IO uint16_t TCCP1;\r
+        uint8_t RESERVED5[2];\r
+  __IO uint16_t TCDT1;\r
+        uint8_t RESERVED6[2];\r
+  __IO uint16_t TCSA1;\r
+        uint8_t RESERVED7[2];\r
+  __IO uint16_t TCSB1;\r
+        uint8_t RESERVED8[2];\r
+  __IO uint16_t TCCP2;\r
+        uint8_t RESERVED9[2];\r
+  __IO uint16_t TCDT2;\r
+        uint8_t RESERVED10[2];\r
+  __IO uint16_t TCSA2;\r
+        uint8_t RESERVED11[2];\r
+  __IO uint16_t TCSB2;\r
+}FM3_MFT_FRT_TypeDef;\r
+\r
+/******************************************************************************\r
+ * MFT_OCU_MODULE\r
+ ******************************************************************************/\r
+/* Multifunction Timer unit 0 Output Compare Unit registers */\r
+typedef struct\r
+{\r
+  __IO uint16_t OCCP0;\r
+        uint8_t RESERVED0[2];\r
+  __IO uint16_t OCCP1;\r
+        uint8_t RESERVED1[2];\r
+  __IO uint16_t OCCP2;\r
+        uint8_t RESERVED2[2];\r
+  __IO uint16_t OCCP3;\r
+        uint8_t RESERVED3[2];\r
+  __IO uint16_t OCCP4;\r
+        uint8_t RESERVED4[2];\r
+  __IO uint16_t OCCP5;\r
+        uint8_t RESERVED5[2];\r
+  __IO  uint8_t OCSA10;\r
+  __IO  uint8_t OCSB10;\r
+        uint8_t RESERVED6[2];\r
+  __IO  uint8_t OCSA32;\r
+  __IO  uint8_t OCSB32;\r
+        uint8_t RESERVED7[2];\r
+  __IO  uint8_t OCSA54;\r
+  __IO  uint8_t OCSB54;\r
+        uint8_t RESERVED8[3];\r
+  __IO  uint8_t OCSC;\r
+        uint8_t RESERVED9[50];\r
+  __IO  uint8_t OCFS10;\r
+  __IO  uint8_t OCFS32;\r
+        uint8_t RESERVED10[2];\r
+  __IO  uint8_t OCFS54;\r
+}FM3_MFT_OCU_TypeDef;\r
+\r
+/******************************************************************************\r
+ * MFT_WFG_MODULE\r
+ ******************************************************************************/\r
+/* Multifunction Timer unit 0 Waveform Generator and Noise Canceler registers */\r
+typedef struct\r
+{\r
+        uint8_t RESERVED0[128];\r
+  __IO uint16_t WFTM10;\r
+        uint8_t RESERVED1[2];\r
+  __IO uint16_t WFTM32;\r
+        uint8_t RESERVED2[2];\r
+  __IO uint16_t WFTM54;\r
+        uint8_t RESERVED3[2];\r
+  __IO uint16_t WFSA10;\r
+        uint8_t RESERVED4[2];\r
+  __IO uint16_t WFSA32;\r
+        uint8_t RESERVED5[2];\r
+  __IO uint16_t WFSA54;\r
+        uint8_t RESERVED6[2];\r
+  __IO uint16_t WFIR;\r
+        uint8_t RESERVED7[2];\r
+  __IO uint16_t NZCL;\r
+}FM3_MFT_WFG_TypeDef;\r
+\r
+/******************************************************************************\r
+ * MFT_ICU_MODULE\r
+ ******************************************************************************/\r
+/* Multifunction Timer unit 0 Input Capture Unit registers */\r
+typedef struct\r
+{\r
+        uint8_t RESERVED0[96];\r
+  __IO  uint8_t ICFS10;\r
+  __IO  uint8_t ICFS32;\r
+        uint8_t RESERVED1[6];\r
+  __IO uint16_t ICCP0;\r
+        uint8_t RESERVED2[2];\r
+  __IO uint16_t ICCP1;\r
+        uint8_t RESERVED3[2];\r
+  __IO uint16_t ICCP2;\r
+        uint8_t RESERVED4[2];\r
+  __IO uint16_t ICCP3;\r
+        uint8_t RESERVED5[2];\r
+  __IO  uint8_t ICSA10;\r
+  __IO  uint8_t ICSB10;\r
+        uint8_t RESERVED6[2];\r
+  __IO  uint8_t ICSA32;\r
+  __IO  uint8_t ICSB32;\r
+}FM3_MFT_ICU_TypeDef;\r
+\r
+/******************************************************************************\r
+ * MFT_ADCMP_MODULE\r
+ ******************************************************************************/\r
+/* Multifunction Timer unit 0 ADC Start Compare Unit registers */\r
+typedef struct\r
+{\r
+        uint8_t RESERVED0[160];\r
+  __IO uint16_t ACCP0;\r
+        uint8_t RESERVED1[2];\r
+  __IO uint16_t ACCPDN0;\r
+        uint8_t RESERVED2[2];\r
+  __IO uint16_t ACCP1;\r
+        uint8_t RESERVED3[2];\r
+  __IO uint16_t ACCPDN1;\r
+        uint8_t RESERVED4[2];\r
+  __IO uint16_t ACCP2;\r
+        uint8_t RESERVED5[2];\r
+  __IO uint16_t ACCPDN2;\r
+        uint8_t RESERVED6[2];\r
+  __IO  uint8_t ACSB;\r
+        uint8_t RESERVED7[3];\r
+  __IO uint16_t ACSA;\r
+        uint8_t RESERVED8[2];\r
+  __IO uint16_t ATSA;\r
+}FM3_MFT_ADCMP_TypeDef;\r
+\r
+/******************************************************************************\r
+ * MFT_PPG_MODULE\r
+ ******************************************************************************/\r
+/* Multifunction Timer PPG registers */\r
+typedef struct\r
+{\r
+        uint8_t RESERVED0;\r
+  __IO  uint8_t TTCR0;\r
+        uint8_t RESERVED1[7];\r
+  __IO  uint8_t COMP0;\r
+        uint8_t RESERVED2[2];\r
+  __IO  uint8_t COMP2;\r
+        uint8_t RESERVED3[4];\r
+  __IO  uint8_t COMP4;\r
+        uint8_t RESERVED4[2];\r
+  __IO  uint8_t COMP6;\r
+        uint8_t RESERVED5[12];\r
+  __IO  uint8_t TTCR1;\r
+        uint8_t RESERVED6[7];\r
+  __IO  uint8_t COMP1;\r
+        uint8_t RESERVED7[2];\r
+  __IO  uint8_t COMP3;\r
+        uint8_t RESERVED8[4];\r
+  __IO  uint8_t COMP5;\r
+        uint8_t RESERVED9[2];\r
+  __IO  uint8_t COMP7;\r
+        uint8_t RESERVED10[203];\r
+  __IO uint16_t TRG;\r
+        uint8_t RESERVED11[2];\r
+  __IO uint16_t REVC;\r
+        uint8_t RESERVED12[250];\r
+  __IO  uint8_t PPGC1;\r
+  __IO  uint8_t PPGC0;\r
+        uint8_t RESERVED13[2];\r
+  __IO  uint8_t PPGC3;\r
+  __IO  uint8_t PPGC2;\r
+        uint8_t RESERVED14[2];\r
+  union {\r
+    __IO uint16_t PRL0;\r
+    struct {\r
+      __IO  uint8_t PRLL0;\r
+      __IO  uint8_t PRLH0;\r
+    };\r
+  };\r
+        uint8_t RESERVED15[2];\r
+  union {\r
+    __IO uint16_t PRL1;\r
+    struct {\r
+      __IO  uint8_t PRLL1;\r
+      __IO  uint8_t PRLH1;\r
+    };\r
+  };\r
+        uint8_t RESERVED16[2];\r
+  union {\r
+    __IO uint16_t PRL2;\r
+    struct {\r
+      __IO  uint8_t PRLL2;\r
+      __IO  uint8_t PRLH2;\r
+    };\r
+  };\r
+        uint8_t RESERVED17[2];\r
+  union {\r
+    __IO uint16_t PRL3;\r
+    struct {\r
+      __IO  uint8_t PRLL3;\r
+      __IO  uint8_t PRLH3;\r
+    };\r
+  };\r
+        uint8_t RESERVED18[2];\r
+  __IO  uint8_t GATEC0;\r
+        uint8_t RESERVED19[39];\r
+  __IO  uint8_t PPGC5;\r
+  __IO  uint8_t PPGC4;\r
+        uint8_t RESERVED20[2];\r
+  __IO  uint8_t PPGC7;\r
+  __IO  uint8_t PPGC6;\r
+        uint8_t RESERVED21[2];\r
+  union {\r
+    __IO uint16_t PRL4;\r
+    struct {\r
+      __IO  uint8_t PRLL4;\r
+      __IO  uint8_t PRLH4;\r
+    };\r
+  };\r
+        uint8_t RESERVED22[2];\r
+  union {\r
+    __IO uint16_t PRL5;\r
+    struct {\r
+      __IO  uint8_t PRLL5;\r
+      __IO  uint8_t PRLH5;\r
+    };\r
+  };\r
+        uint8_t RESERVED23[2];\r
+  union {\r
+    __IO uint16_t PRL6;\r
+    struct {\r
+      __IO  uint8_t PRLL6;\r
+      __IO  uint8_t PRLH6;\r
+    };\r
+  };\r
+        uint8_t RESERVED24[2];\r
+  union {\r
+    __IO uint16_t PRL7;\r
+    struct {\r
+      __IO  uint8_t PRLL7;\r
+      __IO  uint8_t PRLH7;\r
+    };\r
+  };\r
+        uint8_t RESERVED25[2];\r
+  __IO  uint8_t GATEC4;\r
+        uint8_t RESERVED26[39];\r
+  __IO  uint8_t PPGC9;\r
+  __IO  uint8_t PPGC8;\r
+        uint8_t RESERVED27[2];\r
+  __IO  uint8_t PPGC11;\r
+  __IO  uint8_t PPGC10;\r
+        uint8_t RESERVED28[2];\r
+  union {\r
+    __IO uint16_t PRL8;\r
+    struct {\r
+      __IO  uint8_t PRLL8;\r
+      __IO  uint8_t PRLH8;\r
+    };\r
+  };\r
+        uint8_t RESERVED29[2];\r
+  union {\r
+    __IO uint16_t PRL9;\r
+    struct {\r
+      __IO  uint8_t PRLL9;\r
+      __IO  uint8_t PRLH9;\r
+    };\r
+  };\r
+        uint8_t RESERVED30[2];\r
+  union {\r
+    __IO uint16_t PRL10;\r
+    struct {\r
+      __IO  uint8_t PRLL10;\r
+      __IO  uint8_t PRLH10;\r
+    };\r
+  };\r
+        uint8_t RESERVED31[2];\r
+  union {\r
+    __IO uint16_t PRL11;\r
+    struct {\r
+      __IO  uint8_t PRLL11;\r
+      __IO  uint8_t PRLH11;\r
+    };\r
+  };\r
+        uint8_t RESERVED32[2];\r
+  __IO  uint8_t GATEC8;\r
+        uint8_t RESERVED33[39];\r
+  __IO  uint8_t PPGC13;\r
+  __IO  uint8_t PPGC12;\r
+        uint8_t RESERVED34[2];\r
+  __IO  uint8_t PPGC15;\r
+  __IO  uint8_t PPGC14;\r
+        uint8_t RESERVED35[2];\r
+  union {\r
+    __IO uint16_t PRL12;\r
+    struct {\r
+      __IO  uint8_t PRLL12;\r
+      __IO  uint8_t PRLH12;\r
+    };\r
+  };\r
+        uint8_t RESERVED36[2];\r
+  union {\r
+    __IO uint16_t PRL13;\r
+    struct {\r
+      __IO  uint8_t PRLL13;\r
+      __IO  uint8_t PRLH13;\r
+    };\r
+  };\r
+        uint8_t RESERVED37[2];\r
+  union {\r
+    __IO uint16_t PRL14;\r
+    struct {\r
+      __IO  uint8_t PRLL14;\r
+      __IO  uint8_t PRLH14;\r
+    };\r
+  };\r
+        uint8_t RESERVED38[2];\r
+  union {\r
+    __IO uint16_t PRL15;\r
+    struct {\r
+      __IO  uint8_t PRLL15;\r
+      __IO  uint8_t PRLH15;\r
+    };\r
+  };\r
+        uint8_t RESERVED39[2];\r
+  __IO  uint8_t GATEC12;\r
+}FM3_MFT_PPG_TypeDef;\r
+\r
+/******************************************************************************\r
+ * BT_PPG_MODULE\r
+ ******************************************************************************/\r
+/* Base Timer 0 PPG registers */\r
+typedef struct\r
+{\r
+  __IO uint16_t PRLL;\r
+        uint8_t RESERVED0[2];\r
+  __IO uint16_t PRLH;\r
+        uint8_t RESERVED1[2];\r
+  __IO uint16_t TMR;\r
+        uint8_t RESERVED2[2];\r
+  __IO uint16_t TMCR;\r
+        uint8_t RESERVED3[2];\r
+  __IO  uint8_t STC;\r
+  __IO  uint8_t TMCR2;\r
+}FM3_BT_PPG_TypeDef;\r
+\r
+/******************************************************************************\r
+ * BT_PWM_MODULE\r
+ ******************************************************************************/\r
+/* Base Timer 0 PWM registers */\r
+typedef struct\r
+{\r
+  __IO uint16_t PCSR;\r
+        uint8_t RESERVED0[2];\r
+  __IO uint16_t PDUT;\r
+        uint8_t RESERVED1[2];\r
+  __IO uint16_t TMR;\r
+        uint8_t RESERVED2[2];\r
+  __IO uint16_t TMCR;\r
+        uint8_t RESERVED3[2];\r
+  __IO  uint8_t STC;\r
+  __IO  uint8_t TMCR2;\r
+}FM3_BT_PWM_TypeDef;\r
+\r
+/******************************************************************************\r
+ * BT_RT_MODULE\r
+ ******************************************************************************/\r
+/* Base Timer 0 RT registers */\r
+typedef struct\r
+{\r
+  __IO uint16_t PCSR;\r
+        uint8_t RESERVED0[6];\r
+  __IO uint16_t TMR;\r
+        uint8_t RESERVED1[2];\r
+  __IO uint16_t TMCR;\r
+        uint8_t RESERVED2[2];\r
+  __IO  uint8_t STC;\r
+  __IO  uint8_t TMCR2;\r
+}FM3_BT_RT_TypeDef;\r
+\r
+/******************************************************************************\r
+ * BT_PWC_MODULE\r
+ ******************************************************************************/\r
+/* Base Timer 0 PWC registers */\r
+typedef struct\r
+{\r
+        uint8_t RESERVED0[4];\r
+  __IO uint16_t DTBF;\r
+        uint8_t RESERVED1[6];\r
+  __IO uint16_t TMCR;\r
+        uint8_t RESERVED2[2];\r
+  __IO  uint8_t STC;\r
+  __IO  uint8_t TMCR2;\r
+}FM3_BT_PWC_TypeDef;\r
+\r
+/******************************************************************************\r
+ * BTIOSEL03_MODULE\r
+ ******************************************************************************/\r
+/* Base Timer I/O selector channel 0 - channel 3 registers */\r
+typedef struct\r
+{\r
+        uint8_t RESERVED0;\r
+  __IO  uint8_t BTSEL0123;\r
+}FM3_BTIOSEL03_TypeDef;\r
+\r
+/******************************************************************************\r
+ * BTIOSEL47_MODULE\r
+ ******************************************************************************/\r
+/* Base Timer I/O selector channel 4 - channel 7 registers */\r
+typedef struct\r
+{\r
+        uint8_t RESERVED0;\r
+  __IO  uint8_t BTSEL4567;\r
+}FM3_BTIOSEL47_TypeDef;\r
+\r
+/******************************************************************************\r
+ * SBSSR_MODULE\r
+ ******************************************************************************/\r
+/* Software based Simulation Startup (Base Timer) register */\r
+typedef struct\r
+{\r
+  __IO uint16_t BTSSSR;\r
+}FM3_SBSSR_TypeDef;\r
+\r
+/******************************************************************************\r
+ * QPRC_MODULE\r
+ ******************************************************************************/\r
+/* Quad position and revolution counter channel 0 registers */\r
+typedef struct\r
+{\r
+  __IO uint16_t QPCR;\r
+        uint8_t RESERVED0[2];\r
+  __IO uint16_t QRCR;\r
+        uint8_t RESERVED1[2];\r
+  __IO uint16_t QPCCR;\r
+        uint8_t RESERVED2[2];\r
+  __IO uint16_t QPRCR;\r
+        uint8_t RESERVED3[2];\r
+  __IO uint16_t QMPR;\r
+        uint8_t RESERVED4[2];\r
+  union {\r
+    __IO uint16_t QICR;\r
+    struct {\r
+      __IO  uint8_t QICRL;\r
+      __IO  uint8_t QICRH;\r
+    };\r
+  };\r
+        uint8_t RESERVED5[2];\r
+  union {\r
+    __IO uint16_t QCR;\r
+    struct {\r
+      __IO  uint8_t QCRL;\r
+      __IO  uint8_t QCRH;\r
+    };\r
+  };\r
+        uint8_t RESERVED6[2];\r
+  __IO uint16_t QECR;\r
+}FM3_QPRC_TypeDef;\r
+\r
+/******************************************************************************\r
+ * ADC12_MODULE\r
+ ******************************************************************************/\r
+/* 12-bit ADC unit 0 registers */\r
+typedef struct\r
+{\r
+  __IO  uint8_t ADSR;\r
+  __IO  uint8_t ADCR;\r
+        uint8_t RESERVED0[6];\r
+  __IO  uint8_t SFNS;\r
+  __IO  uint8_t SCCR;\r
+        uint8_t RESERVED1[2];\r
+  union {\r
+    __IO uint32_t SCFD;\r
+    struct {\r
+      __IO uint16_t SCFDL;\r
+      __IO uint16_t SCFDH;\r
+    };\r
+  };\r
+  union {\r
+    __IO uint16_t SCIS23;\r
+    struct {\r
+      __IO  uint8_t SCIS2;\r
+      __IO  uint8_t SCIS3;\r
+    };\r
+  };\r
+        uint8_t RESERVED2[2];\r
+  union {\r
+    __IO uint16_t SCIS01;\r
+    struct {\r
+      __IO  uint8_t SCIS0;\r
+      __IO  uint8_t SCIS1;\r
+    };\r
+  };\r
+        uint8_t RESERVED3[2];\r
+  __IO  uint8_t PFNS;\r
+  __IO  uint8_t PCCR;\r
+        uint8_t RESERVED4[2];\r
+  union {\r
+    __IO uint32_t PCFD;\r
+    struct {\r
+      __IO uint16_t PCFDL;\r
+      __IO uint16_t PCFDH;\r
+    };\r
+  };\r
+  __IO  uint8_t PCIS;\r
+        uint8_t RESERVED5[3];\r
+  __IO  uint8_t CMPCR;\r
+        uint8_t RESERVED6;\r
+  __IO uint16_t CMPD;\r
+  union {\r
+    __IO uint16_t ADSS23;\r
+    struct {\r
+      __IO  uint8_t ADSS2;\r
+      __IO  uint8_t ADSS3;\r
+    };\r
+  };\r
+        uint8_t RESERVED7[2];\r
+  union {\r
+    __IO uint16_t ADSS01;\r
+    struct {\r
+      __IO  uint8_t ADSS0;\r
+      __IO  uint8_t ADSS1;\r
+    };\r
+  };\r
+        uint8_t RESERVED8[2];\r
+  union {\r
+    __IO uint16_t ADST01;\r
+    struct {\r
+      __IO  uint8_t ADST1;\r
+      __IO  uint8_t ADST0;\r
+    };\r
+  };\r
+        uint8_t RESERVED9[2];\r
+  __IO  uint8_t ADCT;\r
+        uint8_t RESERVED10[3];\r
+  __IO  uint8_t PRTSL;\r
+  __IO  uint8_t SCTSL;\r
+        uint8_t RESERVED11[2];\r
+  __IO  uint8_t ADCEN;\r
+}FM3_ADC_TypeDef;\r
+\r
+/******************************************************************************\r
+ * CRTRIM_MODULE\r
+ ******************************************************************************/\r
+/* CR trimming registers */\r
+typedef struct\r
+{\r
+  __IO  uint8_t MCR_PSR;\r
+        uint8_t RESERVED0[3];\r
+  __IO uint16_t MCR_FTRM;\r
+        uint8_t RESERVED1[6];\r
+  __IO uint32_t MCR_RLR;\r
+}FM3_CRTRIM_TypeDef;\r
+\r
+/******************************************************************************\r
+ * EXTI_MODULE\r
+ ******************************************************************************/\r
+/* External interrupt registers */\r
+typedef struct\r
+{\r
+  __IO uint16_t ENIR;\r
+        uint8_t RESERVED0[2];\r
+  __IO uint16_t EIRR;\r
+        uint8_t RESERVED1[2];\r
+  __IO uint16_t EICL;\r
+        uint8_t RESERVED2[2];\r
+  __IO uint32_t ELVR;\r
+        uint8_t RESERVED3[4];\r
+  __IO  uint8_t NMIRR;\r
+        uint8_t RESERVED4[3];\r
+  __IO  uint8_t NMICL;\r
+}FM3_EXTI_TypeDef;\r
+\r
+/******************************************************************************\r
+ * INTREQ_MODULE\r
+ ******************************************************************************/\r
+/* Interrupt request read registers */\r
+typedef struct\r
+{\r
+  __IO uint32_t DRQSEL;\r
+        uint8_t RESERVED0[12];\r
+  __IO uint32_t EXC02MON;\r
+  __IO uint32_t IRQ00MON;\r
+  __IO uint32_t IRQ01MON;\r
+  __IO uint32_t IRQ02MON;\r
+  __IO uint32_t IRQ03MON;\r
+  __IO uint32_t IRQ04MON;\r
+  __IO uint32_t IRQ05MON;\r
+  __IO uint32_t IRQ06MON;\r
+  __IO uint32_t IRQ07MON;\r
+  __IO uint32_t IRQ08MON;\r
+  __IO uint32_t IRQ09MON;\r
+  __IO uint32_t IRQ10MON;\r
+  __IO uint32_t IRQ11MON;\r
+  __IO uint32_t IRQ12MON;\r
+  __IO uint32_t IRQ13MON;\r
+  __IO uint32_t IRQ14MON;\r
+  __IO uint32_t IRQ15MON;\r
+  __IO uint32_t IRQ16MON;\r
+  __IO uint32_t IRQ17MON;\r
+  __IO uint32_t IRQ18MON;\r
+  __IO uint32_t IRQ19MON;\r
+  __IO uint32_t IRQ20MON;\r
+  __IO uint32_t IRQ21MON;\r
+  __IO uint32_t IRQ22MON;\r
+  __IO uint32_t IRQ23MON;\r
+  __IO uint32_t IRQ24MON;\r
+  __IO uint32_t IRQ25MON;\r
+  __IO uint32_t IRQ26MON;\r
+  __IO uint32_t IRQ27MON;\r
+  __IO uint32_t IRQ28MON;\r
+  __IO uint32_t IRQ29MON;\r
+  __IO uint32_t IRQ30MON;\r
+  __IO uint32_t IRQ31MON;\r
+  __IO uint32_t IRQ32MON;\r
+  __IO uint32_t IRQ33MON;\r
+  __IO uint32_t IRQ34MON;\r
+  __IO uint32_t IRQ35MON;\r
+  __IO uint32_t IRQ36MON;\r
+  __IO uint32_t IRQ37MON;\r
+  __IO uint32_t IRQ38MON;\r
+  __IO uint32_t IRQ39MON;\r
+  __IO uint32_t IRQ40MON;\r
+  __IO uint32_t IRQ41MON;\r
+  __IO uint32_t IRQ42MON;\r
+  __IO uint32_t IRQ43MON;\r
+  __IO uint32_t IRQ44MON;\r
+  __IO uint32_t IRQ45MON;\r
+  __IO uint32_t IRQ46MON;\r
+  __IO uint32_t IRQ47MON;\r
+}FM3_INTREQ_TypeDef;\r
+\r
+/******************************************************************************\r
+ * GPIO_MODULE\r
+ ******************************************************************************/\r
+/* General purpose I/O registers */\r
+typedef struct\r
+{\r
+  __IO uint32_t PFR0;\r
+  __IO uint32_t PFR1;\r
+  __IO uint32_t PFR2;\r
+  __IO uint32_t PFR3;\r
+  __IO uint32_t PFR4;\r
+  __IO uint32_t PFR5;\r
+  __IO uint32_t PFR6;\r
+        uint8_t RESERVED0[4];\r
+  __IO uint32_t PFR8;\r
+        uint8_t RESERVED1[220];\r
+  __IO uint32_t PCR0;\r
+  __IO uint32_t PCR1;\r
+  __IO uint32_t PCR2;\r
+  __IO uint32_t PCR3;\r
+  __IO uint32_t PCR4;\r
+  __IO uint32_t PCR5;\r
+  __IO uint32_t PCR6;\r
+        uint8_t RESERVED2[228];\r
+  __IO uint32_t DDR0;\r
+  __IO uint32_t DDR1;\r
+  __IO uint32_t DDR2;\r
+  __IO uint32_t DDR3;\r
+  __IO uint32_t DDR4;\r
+  __IO uint32_t DDR5;\r
+  __IO uint32_t DDR6;\r
+        uint8_t RESERVED3[4];\r
+  __IO uint32_t DDR8;\r
+        uint8_t RESERVED4[220];\r
+  __IO uint32_t PDIR0;\r
+  __IO uint32_t PDIR1;\r
+  __IO uint32_t PDIR2;\r
+  __IO uint32_t PDIR3;\r
+  __IO uint32_t PDIR4;\r
+  __IO uint32_t PDIR5;\r
+  __IO uint32_t PDIR6;\r
+        uint8_t RESERVED5[4];\r
+  __IO uint32_t PDIR8;\r
+        uint8_t RESERVED6[220];\r
+  __IO uint32_t PDOR0;\r
+  __IO uint32_t PDOR1;\r
+  __IO uint32_t PDOR2;\r
+  __IO uint32_t PDOR3;\r
+  __IO uint32_t PDOR4;\r
+  __IO uint32_t PDOR5;\r
+  __IO uint32_t PDOR6;\r
+        uint8_t RESERVED7[4];\r
+  __IO uint32_t PDOR8;\r
+        uint8_t RESERVED8[220];\r
+  __IO uint32_t ADE;\r
+        uint8_t RESERVED9[124];\r
+  __IO uint32_t SPSR;\r
+        uint8_t RESERVED10[124];\r
+  __IO uint32_t EPFR00;\r
+  __IO uint32_t EPFR01;\r
+  __IO uint32_t EPFR02;\r
+        uint8_t RESERVED11[4];\r
+  __IO uint32_t EPFR04;\r
+  __IO uint32_t EPFR05;\r
+  __IO uint32_t EPFR06;\r
+  __IO uint32_t EPFR07;\r
+  __IO uint32_t EPFR08;\r
+  __IO uint32_t EPFR09;\r
+  __IO uint32_t EPFR10;\r
+}FM3_GPIO_TypeDef;\r
+\r
+/******************************************************************************\r
+ * LVD_MODULE\r
+ ******************************************************************************/\r
+/* Low voltage detection registers */\r
+typedef struct\r
+{\r
+  __IO  uint8_t LVD_CTL;\r
+        uint8_t RESERVED0[3];\r
+  __IO  uint8_t LVD_STR;\r
+        uint8_t RESERVED1[3];\r
+  __IO  uint8_t LVD_CLR;\r
+        uint8_t RESERVED2[3];\r
+  __IO uint32_t LVD_RLR;\r
+  __IO  uint8_t LVD_STR2;\r
+}FM3_LVD_TypeDef;\r
+\r
+/******************************************************************************\r
+ * USBCLK\r
+ ******************************************************************************/\r
+/* USB clock registers */\r
+typedef struct\r
+{\r
+  __IO  uint8_t UCCR;\r
+        uint8_t RESERVED0[3];\r
+  __IO  uint8_t UPCR1;\r
+        uint8_t RESERVED1[3];\r
+  __IO  uint8_t UPCR2;\r
+        uint8_t RESERVED2[3];\r
+  __IO  uint8_t UPCR3;\r
+        uint8_t RESERVED3[3];\r
+  __IO  uint8_t UPCR4;\r
+        uint8_t RESERVED4[3];\r
+  __IO  uint8_t UP_STR;\r
+        uint8_t RESERVED5[3];\r
+  __IO  uint8_t UPINT_ENR;\r
+        uint8_t RESERVED6[3];\r
+  __IO  uint8_t UPINT_CLR;\r
+        uint8_t RESERVED7[3];\r
+  __IO  uint8_t UPINT_STR;\r
+        uint8_t RESERVED8[15];\r
+  __IO  uint8_t USBEN;\r
+}FM3_USBCLK_TypeDef;\r
+\r
+/******************************************************************************\r
+ * CANPRE_MODULE\r
+ ******************************************************************************/\r
+/* CAN prescaler register */\r
+typedef struct\r
+{\r
+  __IO  uint8_t CANPRE;\r
+}FM3_CANPRE_TypeDef;\r
+\r
+/******************************************************************************\r
+ * MFS03_UART_MODULE\r
+ ******************************************************************************/\r
+/* UART asynchronous channel 0 registers */\r
+typedef struct\r
+{\r
+  __IO  uint8_t SMR;\r
+  __IO  uint8_t SCR;\r
+        uint8_t RESERVED0[2];\r
+  __IO  uint8_t ESCR;\r
+  __IO  uint8_t SSR;\r
+        uint8_t RESERVED1[2];\r
+  union {\r
+    __IO uint16_t RDR;\r
+    __IO uint16_t TDR;\r
+  };\r
+        uint8_t RESERVED2[2];\r
+  union {\r
+    __IO uint16_t BGR;\r
+    struct {\r
+      __IO  uint8_t BGR0;\r
+      __IO  uint8_t BGR1;\r
+    };\r
+  };\r
+}FM3_MFS03_UART_TypeDef;\r
+\r
+/******************************************************************************\r
+ * MFS03_CSIO_MODULE\r
+ ******************************************************************************/\r
+/* UART synchronous channel 0 registers */\r
+typedef struct\r
+{\r
+  __IO  uint8_t SMR;\r
+  __IO  uint8_t SCR;\r
+        uint8_t RESERVED0[2];\r
+  __IO  uint8_t ESCR;\r
+  __IO  uint8_t SSR;\r
+        uint8_t RESERVED1[2];\r
+  union {\r
+    __IO uint16_t RDR;\r
+    __IO uint16_t TDR;\r
+  };\r
+        uint8_t RESERVED2[2];\r
+  union {\r
+    __IO uint16_t BGR;\r
+    struct {\r
+      __IO  uint8_t BGR0;\r
+      __IO  uint8_t BGR1;\r
+    };\r
+  };\r
+}FM3_MFS03_CSIO_TypeDef;\r
+\r
+/******************************************************************************\r
+ * MFS03_LIN_MODULE\r
+ ******************************************************************************/\r
+/* UART LIN channel 0 registers */\r
+typedef struct\r
+{\r
+  __IO  uint8_t SMR;\r
+  __IO  uint8_t SCR;\r
+        uint8_t RESERVED0[2];\r
+  __IO  uint8_t ESCR;\r
+  __IO  uint8_t SSR;\r
+        uint8_t RESERVED1[2];\r
+  union {\r
+    __IO uint16_t RDR;\r
+    __IO uint16_t TDR;\r
+  };\r
+        uint8_t RESERVED2[2];\r
+  union {\r
+    __IO uint16_t BGR;\r
+    struct {\r
+      __IO  uint8_t BGR0;\r
+      __IO  uint8_t BGR1;\r
+    };\r
+  };\r
+}FM3_MFS03_LIN_TypeDef;\r
+\r
+/******************************************************************************\r
+ * MFS03_I2C_MODULE\r
+ ******************************************************************************/\r
+/* I2C channel 0 registers */\r
+typedef struct\r
+{\r
+  __IO  uint8_t SMR;\r
+  __IO  uint8_t IBCR;\r
+        uint8_t RESERVED0[2];\r
+  __IO  uint8_t IBSR;\r
+  __IO  uint8_t SSR;\r
+        uint8_t RESERVED1[2];\r
+  union {\r
+    __IO uint16_t RDR;\r
+    __IO uint16_t TDR;\r
+  };\r
+        uint8_t RESERVED2[2];\r
+  union {\r
+    __IO uint16_t BGR;\r
+    struct {\r
+      __IO  uint8_t BGR0;\r
+      __IO  uint8_t BGR1;\r
+    };\r
+  };\r
+        uint8_t RESERVED3[2];\r
+  __IO  uint8_t ISBA;\r
+  __IO  uint8_t ISMK;\r
+}FM3_MFS03_I2C_TypeDef;\r
+\r
+/******************************************************************************\r
+ * MFS47_UART_MODULE\r
+ ******************************************************************************/\r
+/* UART asynchronous channel 4 registers */\r
+typedef struct\r
+{\r
+  __IO  uint8_t SMR;\r
+  __IO  uint8_t SCR;\r
+        uint8_t RESERVED0[2];\r
+  __IO  uint8_t ESCR;\r
+  __IO  uint8_t SSR;\r
+        uint8_t RESERVED1[2];\r
+  union {\r
+    __IO uint16_t RDR;\r
+    __IO uint16_t TDR;\r
+  };\r
+        uint8_t RESERVED2[2];\r
+  union {\r
+    __IO uint16_t BGR;\r
+    struct {\r
+      __IO  uint8_t BGR0;\r
+      __IO  uint8_t BGR1;\r
+    };\r
+  };\r
+        uint8_t RESERVED3[6];\r
+  union {\r
+    __IO uint16_t FCR;\r
+    struct {\r
+      __IO  uint8_t FCR0;\r
+      __IO  uint8_t FCR1;\r
+    };\r
+  };\r
+        uint8_t RESERVED4[2];\r
+  union {\r
+    __IO uint16_t FBYTE;\r
+    struct {\r
+      __IO  uint8_t FBYTE1;\r
+      __IO  uint8_t FBYTE2;\r
+    };\r
+  };\r
+}FM3_MFS47_UART_TypeDef;\r
+\r
+/******************************************************************************\r
+ * MFS47_CSIO_MODULE\r
+ ******************************************************************************/\r
+/* UART synchronous channel 4 registers */\r
+typedef struct\r
+{\r
+  __IO  uint8_t SMR;\r
+  __IO  uint8_t SCR;\r
+        uint8_t RESERVED0[2];\r
+  __IO  uint8_t ESCR;\r
+  __IO  uint8_t SSR;\r
+        uint8_t RESERVED1[2];\r
+  union {\r
+    __IO uint16_t RDR;\r
+    __IO uint16_t TDR;\r
+  };\r
+        uint8_t RESERVED2[2];\r
+  union {\r
+    __IO uint16_t BGR;\r
+    struct {\r
+      __IO  uint8_t BGR0;\r
+      __IO  uint8_t BGR1;\r
+    };\r
+  };\r
+        uint8_t RESERVED3[6];\r
+  union {\r
+    __IO uint16_t FCR;\r
+    struct {\r
+      __IO  uint8_t FCR0;\r
+      __IO  uint8_t FCR1;\r
+    };\r
+  };\r
+        uint8_t RESERVED4[2];\r
+  union {\r
+    __IO uint16_t FBYTE;\r
+    struct {\r
+      __IO  uint8_t FBYTE1;\r
+      __IO  uint8_t FBYTE2;\r
+    };\r
+  };\r
+}FM3_MFS47_CSIO_TypeDef;\r
+\r
+/******************************************************************************\r
+ * MFS47_LIN_MODULE\r
+ ******************************************************************************/\r
+/* UART LIN channel 4 registers */\r
+typedef struct\r
+{\r
+  __IO  uint8_t SMR;\r
+  __IO  uint8_t SCR;\r
+        uint8_t RESERVED0[2];\r
+  __IO  uint8_t ESCR;\r
+  __IO  uint8_t SSR;\r
+        uint8_t RESERVED1[2];\r
+  union {\r
+    __IO uint16_t RDR;\r
+    __IO uint16_t TDR;\r
+  };\r
+        uint8_t RESERVED2[2];\r
+  union {\r
+    __IO uint16_t BGR;\r
+    struct {\r
+      __IO  uint8_t BGR0;\r
+      __IO  uint8_t BGR1;\r
+    };\r
+  };\r
+        uint8_t RESERVED3[6];\r
+  union {\r
+    __IO uint16_t FCR;\r
+    struct {\r
+      __IO  uint8_t FCR0;\r
+      __IO  uint8_t FCR1;\r
+    };\r
+  };\r
+        uint8_t RESERVED4[2];\r
+  union {\r
+    __IO uint16_t FBYTE;\r
+    struct {\r
+      __IO  uint8_t FBYTE1;\r
+      __IO  uint8_t FBYTE2;\r
+    };\r
+  };\r
+}FM3_MFS47_LIN_TypeDef;\r
+\r
+/******************************************************************************\r
+ * MFS47_I2C_MODULE\r
+ ******************************************************************************/\r
+/* I2C channel 4 registers */\r
+typedef struct\r
+{\r
+  __IO  uint8_t SMR;\r
+  __IO  uint8_t IBCR;\r
+        uint8_t RESERVED0[2];\r
+  __IO  uint8_t IBSR;\r
+  __IO  uint8_t SSR;\r
+        uint8_t RESERVED1[2];\r
+  union {\r
+    __IO uint16_t RDR;\r
+    __IO uint16_t TDR;\r
+  };\r
+        uint8_t RESERVED2[2];\r
+  union {\r
+    __IO uint16_t BGR;\r
+    struct {\r
+      __IO  uint8_t BGR0;\r
+      __IO  uint8_t BGR1;\r
+    };\r
+  };\r
+        uint8_t RESERVED3[2];\r
+  __IO  uint8_t ISBA;\r
+  __IO  uint8_t ISMK;\r
+        uint8_t RESERVED4[2];\r
+  union {\r
+    __IO uint16_t FCR;\r
+    struct {\r
+      __IO  uint8_t FCR0;\r
+      __IO  uint8_t FCR1;\r
+    };\r
+  };\r
+        uint8_t RESERVED5[2];\r
+  union {\r
+    __IO uint16_t FBYTE;\r
+    struct {\r
+      __IO  uint8_t FBYTE1;\r
+      __IO  uint8_t FBYTE2;\r
+    };\r
+  };\r
+}FM3_MFS47_I2C_TypeDef;\r
+\r
+/******************************************************************************\r
+ * CRC_MODULE\r
+ ******************************************************************************/\r
+/* CRC registers */\r
+typedef struct\r
+{\r
+  __IO  uint8_t CRCCR;\r
+        uint8_t RESERVED0[3];\r
+  __IO uint32_t CRCINIT;\r
+  union {\r
+    __IO uint32_t CRCIN;\r
+    struct {\r
+      union {\r
+        __IO uint16_t CRCINL;\r
+        struct {\r
+          __IO  uint8_t CRCINLL;\r
+          __IO  uint8_t CRCINLH;\r
+        };\r
+      };\r
+      union {\r
+        __IO uint16_t CRCINH;\r
+        struct {\r
+          __IO  uint8_t CRCINHL;\r
+          __IO  uint8_t CRCINHH;\r
+        };\r
+      };\r
+    };\r
+  };\r
+  __IO uint32_t CRCR;\r
+}FM3_CRC_TypeDef;\r
+\r
+/******************************************************************************\r
+ * WC_MODULE\r
+ ******************************************************************************/\r
+/* Watch counter registers */\r
+typedef struct\r
+{\r
+  __IO  uint8_t WCRD;\r
+  __IO  uint8_t WCRL;\r
+  __IO  uint8_t WCCR;\r
+        uint8_t RESERVED0[13];\r
+  __IO uint16_t CLK_SEL;\r
+        uint8_t RESERVED1[2];\r
+  __IO  uint8_t CLK_EN;\r
+}FM3_WC_TypeDef;\r
+\r
+/******************************************************************************\r
+ * EXBUS_MODULE\r
+ ******************************************************************************/\r
+/* External bus interface registers */\r
+typedef struct\r
+{\r
+  __IO uint32_t MODE0;\r
+  __IO uint32_t MODE1;\r
+  __IO uint32_t MODE2;\r
+  __IO uint32_t MODE3;\r
+        uint8_t RESERVED0[12];\r
+  __IO uint32_t MODE7;\r
+  __IO uint32_t TIM0;\r
+  __IO uint32_t TIM1;\r
+  __IO uint32_t TIM2;\r
+  __IO uint32_t TIM3;\r
+        uint8_t RESERVED1[12];\r
+  __IO uint32_t TIM7;\r
+  __IO uint32_t AREA0;\r
+  __IO uint32_t AREA1;\r
+  __IO uint32_t AREA2;\r
+  __IO uint32_t AREA3;\r
+        uint8_t RESERVED2[12];\r
+  __IO uint32_t AREA7;\r
+}FM3_EXBUS_TypeDef;\r
+\r
+/******************************************************************************\r
+ * USB_MODULE\r
+ ******************************************************************************/\r
+/* USB channel 0 registers */\r
+typedef struct\r
+{\r
+  union {\r
+    __IO uint16_t HCNT;\r
+    struct {\r
+      __IO  uint8_t HCNT0;\r
+      __IO  uint8_t HCNT1;\r
+    };\r
+  };\r
+        uint8_t RESERVED0[2];\r
+  __IO  uint8_t HIRQ;\r
+  __IO  uint8_t HERR;\r
+        uint8_t RESERVED1[2];\r
+  __IO  uint8_t HSTATE;\r
+  __IO  uint8_t HFCOMP;\r
+        uint8_t RESERVED2[2];\r
+  union {\r
+    __IO uint16_t HRTIMER;\r
+    struct {\r
+      __IO  uint8_t HRTIMER0;\r
+      __IO  uint8_t HRTIMER1;\r
+    };\r
+  };\r
+        uint8_t RESERVED3[2];\r
+  __IO  uint8_t HRTIMER2;\r
+  __IO  uint8_t HADR;\r
+        uint8_t RESERVED4[2];\r
+  union {\r
+    __IO uint16_t HEOF;\r
+    struct {\r
+      __IO  uint8_t HEOF0;\r
+      __IO  uint8_t HEOF1;\r
+    };\r
+  };\r
+        uint8_t RESERVED5[2];\r
+  union {\r
+    __IO uint16_t HFRAME;\r
+    struct {\r
+      __IO  uint8_t HFRAME0;\r
+      __IO  uint8_t HFRAME1;\r
+    };\r
+  };\r
+        uint8_t RESERVED6[2];\r
+  __IO  uint8_t HTOKEN;\r
+        uint8_t RESERVED7[3];\r
+  __IO uint16_t UDCC;\r
+        uint8_t RESERVED8[2];\r
+  __IO uint16_t EP0C;\r
+        uint8_t RESERVED9[2];\r
+  __IO uint16_t EP1C;\r
+        uint8_t RESERVED10[2];\r
+  __IO uint16_t EP2C;\r
+        uint8_t RESERVED11[2];\r
+  __IO uint16_t EP3C;\r
+        uint8_t RESERVED12[2];\r
+  __IO uint16_t EP4C;\r
+        uint8_t RESERVED13[2];\r
+  __IO uint16_t EP5C;\r
+        uint8_t RESERVED14[2];\r
+  __IO uint16_t TMSP;\r
+        uint8_t RESERVED15[2];\r
+  __IO  uint8_t UDCS;\r
+  __IO  uint8_t UDCIE;\r
+        uint8_t RESERVED16[2];\r
+  __IO uint16_t EP0IS;\r
+        uint8_t RESERVED17[2];\r
+  __IO uint16_t EP0OS;\r
+        uint8_t RESERVED18[2];\r
+  __IO uint16_t EP1S;\r
+        uint8_t RESERVED19[2];\r
+  __IO uint16_t EP2S;\r
+        uint8_t RESERVED20[2];\r
+  __IO uint16_t EP3S;\r
+        uint8_t RESERVED21[2];\r
+  __IO uint16_t EP4S;\r
+        uint8_t RESERVED22[2];\r
+  __IO uint16_t EP5S;\r
+        uint8_t RESERVED23[2];\r
+  union {\r
+    __IO uint16_t EP0DT;\r
+    struct {\r
+      __IO  uint8_t EP0DTL;\r
+      __IO  uint8_t EP0DTH;\r
+    };\r
+  };\r
+        uint8_t RESERVED24[2];\r
+  union {\r
+    __IO uint16_t EP1DT;\r
+    struct {\r
+      __IO  uint8_t EP1DTL;\r
+      __IO  uint8_t EP1DTH;\r
+    };\r
+  };\r
+        uint8_t RESERVED25[2];\r
+  union {\r
+    __IO uint16_t EP2DT;\r
+    struct {\r
+      __IO  uint8_t EP2DTL;\r
+      __IO  uint8_t EP2DTH;\r
+    };\r
+  };\r
+        uint8_t RESERVED26[2];\r
+  union {\r
+    __IO uint16_t EP3DT;\r
+    struct {\r
+      __IO  uint8_t EP3DTL;\r
+      __IO  uint8_t EP3DTH;\r
+    };\r
+  };\r
+        uint8_t RESERVED27[2];\r
+  union {\r
+    __IO uint16_t EP4DT;\r
+    struct {\r
+      __IO  uint8_t EP4DTL;\r
+      __IO  uint8_t EP4DTH;\r
+    };\r
+  };\r
+        uint8_t RESERVED28[2];\r
+  union {\r
+    __IO uint16_t EP5DT;\r
+    struct {\r
+      __IO  uint8_t EP5DTL;\r
+      __IO  uint8_t EP5DTH;\r
+    };\r
+  };\r
+}FM3_USB_TypeDef;\r
+\r
+/******************************************************************************\r
+ * DMAC_MODULE\r
+ ******************************************************************************/\r
+/* DMA controller */\r
+typedef struct\r
+{\r
+  __IO uint32_t DMACR;\r
+        uint8_t RESERVED0[12];\r
+  __IO uint32_t DMACA0;\r
+  __IO uint32_t DMACB0;\r
+  __IO uint32_t DMACSA0;\r
+  __IO uint32_t DMACDA0;\r
+  __IO uint32_t DMACA1;\r
+  __IO uint32_t DMACB1;\r
+  __IO uint32_t DMACSA1;\r
+  __IO uint32_t DMACDA1;\r
+  __IO uint32_t DMACA2;\r
+  __IO uint32_t DMACB2;\r
+  __IO uint32_t DMACSA2;\r
+  __IO uint32_t DMACDA2;\r
+  __IO uint32_t DMACA3;\r
+  __IO uint32_t DMACB3;\r
+  __IO uint32_t DMACSA3;\r
+  __IO uint32_t DMACDA3;\r
+  __IO uint32_t DMACA4;\r
+  __IO uint32_t DMACB4;\r
+  __IO uint32_t DMACSA4;\r
+  __IO uint32_t DMACDA4;\r
+  __IO uint32_t DMACA5;\r
+  __IO uint32_t DMACB5;\r
+  __IO uint32_t DMACSA5;\r
+  __IO uint32_t DMACDA5;\r
+  __IO uint32_t DMACA6;\r
+  __IO uint32_t DMACB6;\r
+  __IO uint32_t DMACSA6;\r
+  __IO uint32_t DMACDA6;\r
+  __IO uint32_t DMACA7;\r
+  __IO uint32_t DMACB7;\r
+  __IO uint32_t DMACSA7;\r
+  __IO uint32_t DMACDA7;\r
+}FM3_DMAC_TypeDef;\r
+\r
+/******************************************************************************\r
+ * CAN_MODULE\r
+ ******************************************************************************/\r
+/* CAN channel 0 registers */\r
+typedef struct\r
+{\r
+  __IO uint16_t CTRLR;\r
+  __IO uint16_t STATR;\r
+  __IO uint16_t ERRCNT;\r
+  __IO uint16_t BTR;\r
+  __IO uint16_t INTR;\r
+  __IO uint16_t TESTR;\r
+  __IO uint16_t BRPER;\r
+        uint8_t RESERVED0[2];\r
+  __IO uint16_t IF1CREQ;\r
+  __IO uint16_t IF1CMSK;\r
+  union {\r
+    __IO uint32_t IF1MSK;\r
+    struct {\r
+      __IO uint16_t IF1MSK1;\r
+      __IO uint16_t IF1MSK2;\r
+    };\r
+  };\r
+  union {\r
+    __IO uint32_t IF1ARB;\r
+    struct {\r
+      __IO uint16_t IF1ARB1;\r
+      __IO uint16_t IF1ARB2;\r
+    };\r
+  };\r
+  __IO uint16_t IF1MCTR;\r
+        uint8_t RESERVED1[2];\r
+  union {\r
+    __IO uint32_t IF1DTA_L;\r
+    struct {\r
+      __IO uint16_t IF1DTA1_L;\r
+      __IO uint16_t IF1DTA2_L;\r
+    };\r
+  };\r
+  union {\r
+    __IO uint32_t IF1DTB_L;\r
+    struct {\r
+      __IO uint16_t IF1DTB1_L;\r
+      __IO uint16_t IF1DTB2_L;\r
+    };\r
+  };\r
+        uint8_t RESERVED2[8];\r
+  union {\r
+    __IO uint32_t IF1DTA_B;\r
+    struct {\r
+      __IO uint16_t IF1DTA2_B;\r
+      __IO uint16_t IF1DTA1_B;\r
+    };\r
+  };\r
+  union {\r
+    __IO uint32_t IF1DTB_B;\r
+    struct {\r
+      __IO uint16_t IF1DTB2_B;\r
+      __IO uint16_t IF1DTB1_B;\r
+    };\r
+  };\r
+        uint8_t RESERVED3[8];\r
+  __IO uint16_t IF2CREQ;\r
+  __IO uint16_t IF2CMSK;\r
+  union {\r
+    __IO uint32_t IF2MSK;\r
+    struct {\r
+      __IO uint16_t IF2MSK1;\r
+      __IO uint16_t IF2MSK2;\r
+    };\r
+  };\r
+  union {\r
+    __IO uint32_t IF2ARB;\r
+    struct {\r
+      __IO uint16_t IF2ARB1;\r
+      __IO uint16_t IF2ARB2;\r
+    };\r
+  };\r
+  __IO uint16_t IF2MCTR;\r
+        uint8_t RESERVED4[2];\r
+  union {\r
+    __IO uint32_t IF2DTA_L;\r
+    struct {\r
+      __IO uint16_t IF2DTA1_L;\r
+      __IO uint16_t IF2DTA2_L;\r
+    };\r
+  };\r
+  union {\r
+    __IO uint32_t IF2DTB_L;\r
+    struct {\r
+      __IO uint16_t IF2DTB1_L;\r
+      __IO uint16_t IF2DTB2_L;\r
+    };\r
+  };\r
+        uint8_t RESERVED5[8];\r
+  union {\r
+    __IO uint32_t IF2DTA_B;\r
+    struct {\r
+      __IO uint16_t IF2DTA2_B;\r
+      __IO uint16_t IF2DTA1_B;\r
+    };\r
+  };\r
+  union {\r
+    __IO uint32_t IF2DTB_B;\r
+    struct {\r
+      __IO uint16_t IF2DTB2_B;\r
+      __IO uint16_t IF2DTB1_B;\r
+    };\r
+  };\r
+        uint8_t RESERVED6[24];\r
+  union {\r
+    __IO uint32_t TREQR;\r
+    struct {\r
+      __IO uint16_t TREQR1;\r
+      __IO uint16_t TREQR2;\r
+    };\r
+  };\r
+        uint8_t RESERVED7[12];\r
+  union {\r
+    __IO uint32_t NEWDT;\r
+    struct {\r
+      __IO uint16_t NEWDT1;\r
+      __IO uint16_t NEWDT2;\r
+    };\r
+  };\r
+        uint8_t RESERVED8[12];\r
+  union {\r
+    __IO uint32_t INTPND;\r
+    struct {\r
+      __IO uint16_t INTPND1;\r
+      __IO uint16_t INTPND2;\r
+    };\r
+  };\r
+        uint8_t RESERVED9[12];\r
+  union {\r
+    __IO uint32_t MSGVAL;\r
+    struct {\r
+      __IO uint16_t MSGVAL1;\r
+      __IO uint16_t MSGVAL2;\r
+    };\r
+  };\r
+}FM3_CAN_TypeDef;\r
+\r
+\r
+/******************************************************************************\r
+ * Peripheral memory map\r
+ ******************************************************************************/\r
+#define FM3_FLASH_BASE        (0x00000000UL)                 /* Flash Base                             */\r
+#define FM3_PERIPH_BASE       (0x40000000UL)                 /* Peripheral  Base                       */\r
+#define FM3_CM3_BASE          (0xE0100000UL)                 /* CM3 Private                            */\r
+\r
+#define FM3_FLASH_IF_BASE     (FM3_PERIPH_BASE + 0x00000UL)  /* Flash interface registers              */\r
+#define FM3_CRG_BASE          (FM3_PERIPH_BASE + 0x10000UL)  /* Clock and reset registers              */\r
+#define FM3_HWWDT_BASE        (FM3_PERIPH_BASE + 0x11000UL)  /* Hardware watchdog registers            */\r
+#define FM3_SWWDT_BASE        (FM3_PERIPH_BASE + 0x12000UL)  /* Software watchdog registers            */\r
+#define FM3_DTIM_BASE         (FM3_PERIPH_BASE + 0x15000UL)  /* Dual timer 1/2 registers               */\r
+#define FM3_MFT0_FRT_BASE     (FM3_PERIPH_BASE + 0x20000UL)  /* Multifunction Timer unit 0 Free Running Timer registers */\r
+#define FM3_MFT0_OCU_BASE     (FM3_PERIPH_BASE + 0x20000UL)  /* Multifunction Timer unit 0 Output Compare Unit registers */\r
+#define FM3_MFT0_WFG_BASE     (FM3_PERIPH_BASE + 0x20000UL)  /* Multifunction Timer unit 0 Waveform Generator and Noise Canceler registers */\r
+#define FM3_MFT0_ICU_BASE     (FM3_PERIPH_BASE + 0x20000UL)  /* Multifunction Timer unit 0 Input Capture Unit registers */\r
+#define FM3_MFT0_ADCMP_BASE   (FM3_PERIPH_BASE + 0x20000UL)  /* Multifunction Timer unit 0 ADC Start Compare Unit registers */\r
+#define FM3_MFT1_FRT_BASE     (FM3_PERIPH_BASE + 0x21000UL)  /* Multifunction Timer unit 1 Free Running Timer registers */\r
+#define FM3_MFT1_OCU_BASE     (FM3_PERIPH_BASE + 0x21000UL)  /* Multifunction Timer unit 1 Output Compare Unit registers */\r
+#define FM3_MFT1_WFG_BASE     (FM3_PERIPH_BASE + 0x21000UL)  /* Multifunction Timer unit 1 Waveform Generator and Noise Canceler registers */\r
+#define FM3_MFT1_ICU_BASE     (FM3_PERIPH_BASE + 0x21000UL)  /* Multifunction Timer unit 1 Input Capture Unit registers */\r
+#define FM3_MFT1_ADCMP_BASE   (FM3_PERIPH_BASE + 0x21000UL)  /* Multifunction Timer unit 1 ADC Start Compare Unit registers */\r
+#define FM3_MFT_PPG_BASE      (FM3_PERIPH_BASE + 0x24000UL)  /* Multifunction Timer PPG registers      */\r
+#define FM3_BT0_PPG_BASE      (FM3_PERIPH_BASE + 0x25000UL)  /* Base Timer 0 PPG registers             */\r
+#define FM3_BT0_PWM_BASE      (FM3_PERIPH_BASE + 0x25000UL)  /* Base Timer 0 PWM registers             */\r
+#define FM3_BT0_RT_BASE       (FM3_PERIPH_BASE + 0x25000UL)  /* Base Timer 0 RT registers              */\r
+#define FM3_BT0_PWC_BASE      (FM3_PERIPH_BASE + 0x25000UL)  /* Base Timer 0 PWC registers             */\r
+#define FM3_BT1_PPG_BASE      (FM3_PERIPH_BASE + 0x25040UL)  /* Base Timer 1 PPG registers             */\r
+#define FM3_BT1_PWM_BASE      (FM3_PERIPH_BASE + 0x25040UL)  /* Base Timer 1 PWM registers             */\r
+#define FM3_BT1_RT_BASE       (FM3_PERIPH_BASE + 0x25040UL)  /* Base Timer 1 RT registers              */\r
+#define FM3_BT1_PWC_BASE      (FM3_PERIPH_BASE + 0x25040UL)  /* Base Timer 1 PWC registers             */\r
+#define FM3_BT2_PPG_BASE      (FM3_PERIPH_BASE + 0x25080UL)  /* Base Timer 2 PPG registers             */\r
+#define FM3_BT2_PWM_BASE      (FM3_PERIPH_BASE + 0x25080UL)  /* Base Timer 2 PWM registers             */\r
+#define FM3_BT2_RT_BASE       (FM3_PERIPH_BASE + 0x25080UL)  /* Base Timer 2 RT registers              */\r
+#define FM3_BT2_PWC_BASE      (FM3_PERIPH_BASE + 0x25080UL)  /* Base Timer 2 PWC registers             */\r
+#define FM3_BT3_PPG_BASE      (FM3_PERIPH_BASE + 0x250C0UL)  /* Base Timer 3 PPG registers             */\r
+#define FM3_BT3_PWM_BASE      (FM3_PERIPH_BASE + 0x250C0UL)  /* Base Timer 3 PWM registers             */\r
+#define FM3_BT3_RT_BASE       (FM3_PERIPH_BASE + 0x250C0UL)  /* Base Timer 3 RT registers              */\r
+#define FM3_BT3_PWC_BASE      (FM3_PERIPH_BASE + 0x250C0UL)  /* Base Timer 3 PWC registers             */\r
+#define FM3_BT4_PPG_BASE      (FM3_PERIPH_BASE + 0x25200UL)  /* Base Timer 4 PPG registers             */\r
+#define FM3_BT4_PWM_BASE      (FM3_PERIPH_BASE + 0x25200UL)  /* Base Timer 4 PWM registers             */\r
+#define FM3_BT4_RT_BASE       (FM3_PERIPH_BASE + 0x25200UL)  /* Base Timer 4 RT registers              */\r
+#define FM3_BT4_PWC_BASE      (FM3_PERIPH_BASE + 0x25200UL)  /* Base Timer 4 PWC registers             */\r
+#define FM3_BT5_PPG_BASE      (FM3_PERIPH_BASE + 0x25240UL)  /* Base Timer 5 PPG registers             */\r
+#define FM3_BT5_PWM_BASE      (FM3_PERIPH_BASE + 0x25240UL)  /* Base Timer 5 PWM registers             */\r
+#define FM3_BT5_RT_BASE       (FM3_PERIPH_BASE + 0x25240UL)  /* Base Timer 5 RT registers              */\r
+#define FM3_BT5_PWC_BASE      (FM3_PERIPH_BASE + 0x25240UL)  /* Base Timer 5 PWC registers             */\r
+#define FM3_BT6_PPG_BASE      (FM3_PERIPH_BASE + 0x25280UL)  /* Base Timer 6 PPG registers             */\r
+#define FM3_BT6_PWM_BASE      (FM3_PERIPH_BASE + 0x25280UL)  /* Base Timer 6 PWM registers             */\r
+#define FM3_BT6_RT_BASE       (FM3_PERIPH_BASE + 0x25280UL)  /* Base Timer 6 RT registers              */\r
+#define FM3_BT6_PWC_BASE      (FM3_PERIPH_BASE + 0x25280UL)  /* Base Timer 6 PWC registers             */\r
+#define FM3_BT7_PPG_BASE      (FM3_PERIPH_BASE + 0x252C0UL)  /* Base Timer 7 PPG registers             */\r
+#define FM3_BT7_PWM_BASE      (FM3_PERIPH_BASE + 0x252C0UL)  /* Base Timer 7 PWM registers             */\r
+#define FM3_BT7_RT_BASE       (FM3_PERIPH_BASE + 0x252C0UL)  /* Base Timer 7 RT registers              */\r
+#define FM3_BT7_PWC_BASE      (FM3_PERIPH_BASE + 0x252C0UL)  /* Base Timer 7 PWC registers             */\r
+#define FM3_BTIOSEL03_BASE    (FM3_PERIPH_BASE + 0x25100UL)  /* Base Timer I/O selector channel 0 - channel 3 registers */\r
+#define FM3_BTIOSEL47_BASE    (FM3_PERIPH_BASE + 0x25300UL)  /* Base Timer I/O selector channel 4 - channel 7 registers */\r
+#define FM3_SBSSR_BASE        (FM3_PERIPH_BASE + 0x25FFCUL)  /* Software based Simulation Startup (Base Timer) register */\r
+#define FM3_QPRC0_BASE        (FM3_PERIPH_BASE + 0x26000UL)  /* Quad position and revolution counter channel 0 registers */\r
+#define FM3_QPRC1_BASE        (FM3_PERIPH_BASE + 0x26040UL)  /* Quad position and revolution counter channel 1 registers */\r
+#define FM3_ADC0_BASE         (FM3_PERIPH_BASE + 0x27000UL)  /* 12-bit ADC unit 0 registers            */\r
+#define FM3_ADC1_BASE         (FM3_PERIPH_BASE + 0x27100UL)  /* 12-bit ADC unit 1 registers            */\r
+#define FM3_ADC2_BASE         (FM3_PERIPH_BASE + 0x27200UL)  /* 12-bit ADC unit 2 registers            */\r
+#define FM3_CRTRIM_BASE       (FM3_PERIPH_BASE + 0x2E000UL)  /* CR trimming registers                  */\r
+#define FM3_EXTI_BASE         (FM3_PERIPH_BASE + 0x30000UL)  /* External interrupt registers           */\r
+#define FM3_INTREQ_BASE       (FM3_PERIPH_BASE + 0x31000UL)  /* Interrupt request read registers       */\r
+#define FM3_GPIO_BASE         (FM3_PERIPH_BASE + 0x33000UL)  /* General purpose I/O registers          */\r
+#define FM3_LVD_BASE          (FM3_PERIPH_BASE + 0x35000UL)  /* Low voltage detection registers        */\r
+#define FM3_USBCLK_BASE       (FM3_PERIPH_BASE + 0x36000UL)  /* USB clock registers                    */\r
+#define FM3_CANPRES_BASE      (FM3_PERIPH_BASE + 0x37000UL)  /* CAN prescaler register                 */\r
+#define FM3_MFS0_UART_BASE    (FM3_PERIPH_BASE + 0x38000UL)  /* UART asynchronous channel 0 registers  */\r
+#define FM3_MFS0_CSIO_BASE    (FM3_PERIPH_BASE + 0x38000UL)  /* UART synchronous channel 0 registers   */\r
+#define FM3_MFS0_LIN_BASE     (FM3_PERIPH_BASE + 0x38000UL)  /* UART LIN channel 0 registers           */\r
+#define FM3_MFS0_I2C_BASE     (FM3_PERIPH_BASE + 0x38000UL)  /* I2C channel 0 registers                */\r
+#define FM3_MFS1_UART_BASE    (FM3_PERIPH_BASE + 0x38100UL)  /* UART asynchronous channel 1 registers  */\r
+#define FM3_MFS1_CSIO_BASE    (FM3_PERIPH_BASE + 0x38100UL)  /* UART synchronous channel 1 registers   */\r
+#define FM3_MFS1_LIN_BASE     (FM3_PERIPH_BASE + 0x38100UL)  /* UART LIN channel 1 registers           */\r
+#define FM3_MFS1_I2C_BASE     (FM3_PERIPH_BASE + 0x38100UL)  /* I2C channel 1 registers                */\r
+#define FM3_MFS2_UART_BASE    (FM3_PERIPH_BASE + 0x38200UL)  /* UART asynchronous channel 2 registers  */\r
+#define FM3_MFS2_CSIO_BASE    (FM3_PERIPH_BASE + 0x38200UL)  /* UART synchronous channel 2 registers   */\r
+#define FM3_MFS2_LIN_BASE     (FM3_PERIPH_BASE + 0x38200UL)  /* UART LIN channel 2 registers           */\r
+#define FM3_MFS2_I2C_BASE     (FM3_PERIPH_BASE + 0x38200UL)  /* I2C channel 2 registers                */\r
+#define FM3_MFS3_UART_BASE    (FM3_PERIPH_BASE + 0x38300UL)  /* UART asynchronous channel 3 registers  */\r
+#define FM3_MFS3_CSIO_BASE    (FM3_PERIPH_BASE + 0x38300UL)  /* UART synchronous channel 3 registers   */\r
+#define FM3_MFS3_LIN_BASE     (FM3_PERIPH_BASE + 0x38300UL)  /* UART LIN channel 3 registers           */\r
+#define FM3_MFS3_I2C_BASE     (FM3_PERIPH_BASE + 0x38300UL)  /* I2C channel 3 registers                */\r
+#define FM3_MFS4_UART_BASE    (FM3_PERIPH_BASE + 0x38400UL)  /* UART asynchronous channel 4 registers  */\r
+#define FM3_MFS4_CSIO_BASE    (FM3_PERIPH_BASE + 0x38400UL)  /* UART synchronous channel 4 registers   */\r
+#define FM3_MFS4_LIN_BASE     (FM3_PERIPH_BASE + 0x38400UL)  /* UART LIN channel 4 registers           */\r
+#define FM3_MFS4_I2C_BASE     (FM3_PERIPH_BASE + 0x38400UL)  /* I2C channel 4 registers                */\r
+#define FM3_MFS5_UART_BASE    (FM3_PERIPH_BASE + 0x38500UL)  /* UART asynchronous channel 5 registers  */\r
+#define FM3_MFS5_CSIO_BASE    (FM3_PERIPH_BASE + 0x38500UL)  /* UART synchronous channel 5 registers   */\r
+#define FM3_MFS5_LIN_BASE     (FM3_PERIPH_BASE + 0x38500UL)  /* UART LIN channel 5 registers           */\r
+#define FM3_MFS5_I2C_BASE     (FM3_PERIPH_BASE + 0x38500UL)  /* I2C channel 5 registers                */\r
+#define FM3_MFS6_UART_BASE    (FM3_PERIPH_BASE + 0x38600UL)  /* UART asynchronous channel 6 registers  */\r
+#define FM3_MFS6_CSIO_BASE    (FM3_PERIPH_BASE + 0x38600UL)  /* UART synchronous channel 6 registers   */\r
+#define FM3_MFS6_LIN_BASE     (FM3_PERIPH_BASE + 0x38600UL)  /* UART LIN channel 6 registers           */\r
+#define FM3_MFS6_I2C_BASE     (FM3_PERIPH_BASE + 0x38600UL)  /* I2C channel 6 registers                */\r
+#define FM3_MFS7_UART_BASE    (FM3_PERIPH_BASE + 0x38700UL)  /* UART asynchronous channel 7 registers  */\r
+#define FM3_MFS7_CSIO_BASE    (FM3_PERIPH_BASE + 0x38700UL)  /* UART synchronous channel 7 registers   */\r
+#define FM3_MFS7_LIN_BASE     (FM3_PERIPH_BASE + 0x38700UL)  /* UART LIN channel 7 registers           */\r
+#define FM3_MFS7_I2C_BASE     (FM3_PERIPH_BASE + 0x38700UL)  /* I2C channel 7 registers                */\r
+#define FM3_CRC_BASE          (FM3_PERIPH_BASE + 0x39000UL)  /* CRC registers                          */\r
+#define FM3_WC_BASE           (FM3_PERIPH_BASE + 0x3A000UL)  /* Watch counter registers                */\r
+#define FM3_EXBUS_BASE        (FM3_PERIPH_BASE + 0x3F000UL)  /* External bus interface registers       */\r
+#define FM3_USB0_BASE         (FM3_PERIPH_BASE + 0x42100UL)  /* USB channel 0 registers                */\r
+#define FM3_DMAC_BASE         (FM3_PERIPH_BASE + 0x60000UL)  /* DMA controller                         */\r
+#define FM3_CAN0_BASE         (FM3_PERIPH_BASE + 0x62000UL)  /* CAN channel 0 registers                */\r
+#define FM3_CAN1_BASE         (FM3_PERIPH_BASE + 0x63000UL)  /* CAN channel 1 registers                */\r
+\r
+/******************************************************************************\r
+ * Peripheral declaration\r
+ ******************************************************************************/\r
+#define FM3_FLASH_IF    ((FM3_FIF_TypeDef *)FM3_FLASH_IF_BASE)\r
+#define FM3_CRG         ((FM3_CRG_TypeDef *)FM3_CRG_BASE)\r
+#define FM3_HWWDT       ((FM3_HWWDT_TypeDef *)FM3_HWWDT_BASE)\r
+#define FM3_SWWDT       ((FM3_SWWDT_TypeDef *)FM3_SWWDT_BASE)\r
+#define FM3_DTIM        ((FM3_DTIM_TypeDef *)FM3_DTIM_BASE)\r
+#define FM3_MFT0_FRT    ((FM3_MFT_FRT_TypeDef *)FM3_MFT0_FRT_BASE)\r
+#define FM3_MFT0_OCU    ((FM3_MFT_OCU_TypeDef *)FM3_MFT0_OCU_BASE)\r
+#define FM3_MFT0_WFG    ((FM3_MFT_WFG_TypeDef *)FM3_MFT0_WFG_BASE)\r
+#define FM3_MFT0_ICU    ((FM3_MFT_ICU_TypeDef *)FM3_MFT0_ICU_BASE)\r
+#define FM3_MFT0_ADCMP  ((FM3_MFT_ADCMP_TypeDef *)FM3_MFT0_ADCMP_BASE)\r
+#define FM3_MFT1_FRT    ((FM3_MFT_FRT_TypeDef *)FM3_MFT1_FRT_BASE)\r
+#define FM3_MFT1_OCU    ((FM3_MFT_OCU_TypeDef *)FM3_MFT1_OCU_BASE)\r
+#define FM3_MFT1_WFG    ((FM3_MFT_WFG_TypeDef *)FM3_MFT1_WFG_BASE)\r
+#define FM3_MFT1_ICU    ((FM3_MFT_ICU_TypeDef *)FM3_MFT1_ICU_BASE)\r
+#define FM3_MFT1_ADCMP  ((FM3_MFT_ADCMP_TypeDef *)FM3_MFT1_ADCMP_BASE)\r
+#define FM3_MFT_PPG     ((FM3_MFT_PPG_TypeDef *)FM3_MFT_PPG_BASE)\r
+#define FM3_BT0_PPG     ((FM3_BT_PPG_TypeDef *)FM3_BT0_PPG_BASE)\r
+#define FM3_BT0_PWM     ((FM3_BT_PWM_TypeDef *)FM3_BT0_PWM_BASE)\r
+#define FM3_BT0_RT      ((FM3_BT_RT_TypeDef *)FM3_BT0_RT_BASE)\r
+#define FM3_BT0_PWC     ((FM3_BT_PWC_TypeDef *)FM3_BT0_PWC_BASE)\r
+#define FM3_BT1_PPG     ((FM3_BT_PPG_TypeDef *)FM3_BT1_PPG_BASE)\r
+#define FM3_BT1_PWM     ((FM3_BT_PWM_TypeDef *)FM3_BT1_PWM_BASE)\r
+#define FM3_BT1_RT      ((FM3_BT_RT_TypeDef *)FM3_BT1_RT_BASE)\r
+#define FM3_BT1_PWC     ((FM3_BT_PWC_TypeDef *)FM3_BT1_PWC_BASE)\r
+#define FM3_BT2_PPG     ((FM3_BT_PPG_TypeDef *)FM3_BT2_PPG_BASE)\r
+#define FM3_BT2_PWM     ((FM3_BT_PWM_TypeDef *)FM3_BT2_PWM_BASE)\r
+#define FM3_BT2_RT      ((FM3_BT_RT_TypeDef *)FM3_BT2_RT_BASE)\r
+#define FM3_BT2_PWC     ((FM3_BT_PWC_TypeDef *)FM3_BT2_PWC_BASE)\r
+#define FM3_BT3_PPG     ((FM3_BT_PPG_TypeDef *)FM3_BT3_PPG_BASE)\r
+#define FM3_BT3_PWM     ((FM3_BT_PWM_TypeDef *)FM3_BT3_PWM_BASE)\r
+#define FM3_BT3_RT      ((FM3_BT_RT_TypeDef *)FM3_BT3_RT_BASE)\r
+#define FM3_BT3_PWC     ((FM3_BT_PWC_TypeDef *)FM3_BT3_PWC_BASE)\r
+#define FM3_BT4_PPG     ((FM3_BT_PPG_TypeDef *)FM3_BT4_PPG_BASE)\r
+#define FM3_BT4_PWM     ((FM3_BT_PWM_TypeDef *)FM3_BT4_PWM_BASE)\r
+#define FM3_BT4_RT      ((FM3_BT_RT_TypeDef *)FM3_BT4_RT_BASE)\r
+#define FM3_BT4_PWC     ((FM3_BT_PWC_TypeDef *)FM3_BT4_PWC_BASE)\r
+#define FM3_BT5_PPG     ((FM3_BT_PPG_TypeDef *)FM3_BT5_PPG_BASE)\r
+#define FM3_BT5_PWM     ((FM3_BT_PWM_TypeDef *)FM3_BT5_PWM_BASE)\r
+#define FM3_BT5_RT      ((FM3_BT_RT_TypeDef *)FM3_BT5_RT_BASE)\r
+#define FM3_BT5_PWC     ((FM3_BT_PWC_TypeDef *)FM3_BT5_PWC_BASE)\r
+#define FM3_BT6_PPG     ((FM3_BT_PPG_TypeDef *)FM3_BT6_PPG_BASE)\r
+#define FM3_BT6_PWM     ((FM3_BT_PWM_TypeDef *)FM3_BT6_PWM_BASE)\r
+#define FM3_BT6_RT      ((FM3_BT_RT_TypeDef *)FM3_BT6_RT_BASE)\r
+#define FM3_BT6_PWC     ((FM3_BT_PWC_TypeDef *)FM3_BT6_PWC_BASE)\r
+#define FM3_BT7_PPG     ((FM3_BT_PPG_TypeDef *)FM3_BT7_PPG_BASE)\r
+#define FM3_BT7_PWM     ((FM3_BT_PWM_TypeDef *)FM3_BT7_PWM_BASE)\r
+#define FM3_BT7_RT      ((FM3_BT_RT_TypeDef *)FM3_BT7_RT_BASE)\r
+#define FM3_BT7_PWC     ((FM3_BT_PWC_TypeDef *)FM3_BT7_PWC_BASE)\r
+#define FM3_BTIOSEL03   ((FM3_BTIOSEL03_TypeDef *)FM3_BTIOSEL03_BASE)\r
+#define FM3_BTIOSEL47   ((FM3_BTIOSEL47_TypeDef *)FM3_BTIOSEL47_BASE)\r
+#define FM3_SBSSR       ((FM3_SBSSR_TypeDef *)FM3_SBSSR_BASE)\r
+#define FM3_QPRC0       ((FM3_QPRC_TypeDef *)FM3_QPRC0_BASE)\r
+#define FM3_QPRC1       ((FM3_QPRC_TypeDef *)FM3_QPRC1_BASE)\r
+#define FM3_ADC0        ((FM3_ADC_TypeDef *)FM3_ADC0_BASE)\r
+#define FM3_ADC1        ((FM3_ADC_TypeDef *)FM3_ADC1_BASE)\r
+#define FM3_ADC2        ((FM3_ADC_TypeDef *)FM3_ADC2_BASE)\r
+#define FM3_CRTRIM      ((FM3_CRTRIM_TypeDef *)FM3_CRTRIM_BASE)\r
+#define FM3_EXTI        ((FM3_EXTI_TypeDef *)FM3_EXTI_BASE)\r
+#define FM3_INTREQ      ((FM3_INTREQ_TypeDef *)FM3_INTREQ_BASE)\r
+#define FM3_GPIO        ((FM3_GPIO_TypeDef *)FM3_GPIO_BASE)\r
+#define FM3_LVD         ((FM3_LVD_TypeDef *)FM3_LVD_BASE)\r
+#define FM3_USBCLK      ((FM3_USBCLK_TypeDef *)FM3_USBCLK_BASE)\r
+#define FM3_CANPRES     ((FM3_CANPRE_TypeDef *)FM3_CANPRES_BASE)\r
+#define FM3_MFS0_UART   ((FM3_MFS03_UART_TypeDef *)FM3_MFS0_UART_BASE)\r
+#define FM3_MFS0_CSIO   ((FM3_MFS03_CSIO_TypeDef *)FM3_MFS0_CSIO_BASE)\r
+#define FM3_MFS0_LIN    ((FM3_MFS03_LIN_TypeDef *)FM3_MFS0_LIN_BASE)\r
+#define FM3_MFS0_I2C    ((FM3_MFS03_I2C_TypeDef *)FM3_MFS0_I2C_BASE)\r
+#define FM3_MFS1_UART   ((FM3_MFS03_UART_TypeDef *)FM3_MFS1_UART_BASE)\r
+#define FM3_MFS1_CSIO   ((FM3_MFS03_CSIO_TypeDef *)FM3_MFS1_CSIO_BASE)\r
+#define FM3_MFS1_LIN    ((FM3_MFS03_LIN_TypeDef *)FM3_MFS1_LIN_BASE)\r
+#define FM3_MFS1_I2C    ((FM3_MFS03_I2C_TypeDef *)FM3_MFS1_I2C_BASE)\r
+#define FM3_MFS2_UART   ((FM3_MFS03_UART_TypeDef *)FM3_MFS2_UART_BASE)\r
+#define FM3_MFS2_CSIO   ((FM3_MFS03_CSIO_TypeDef *)FM3_MFS2_CSIO_BASE)\r
+#define FM3_MFS2_LIN    ((FM3_MFS03_LIN_TypeDef *)FM3_MFS2_LIN_BASE)\r
+#define FM3_MFS2_I2C    ((FM3_MFS03_I2C_TypeDef *)FM3_MFS2_I2C_BASE)\r
+#define FM3_MFS3_UART   ((FM3_MFS03_UART_TypeDef *)FM3_MFS3_UART_BASE)\r
+#define FM3_MFS3_CSIO   ((FM3_MFS03_CSIO_TypeDef *)FM3_MFS3_CSIO_BASE)\r
+#define FM3_MFS3_LIN    ((FM3_MFS03_LIN_TypeDef *)FM3_MFS3_LIN_BASE)\r
+#define FM3_MFS3_I2C    ((FM3_MFS03_I2C_TypeDef *)FM3_MFS3_I2C_BASE)\r
+#define FM3_MFS4_UART   ((FM3_MFS47_UART_TypeDef *)FM3_MFS4_UART_BASE)\r
+#define FM3_MFS4_CSIO   ((FM3_MFS47_CSIO_TypeDef *)FM3_MFS4_CSIO_BASE)\r
+#define FM3_MFS4_LIN    ((FM3_MFS47_LIN_TypeDef *)FM3_MFS4_LIN_BASE)\r
+#define FM3_MFS4_I2C    ((FM3_MFS47_I2C_TypeDef *)FM3_MFS4_I2C_BASE)\r
+#define FM3_MFS5_UART   ((FM3_MFS47_UART_TypeDef *)FM3_MFS5_UART_BASE)\r
+#define FM3_MFS5_CSIO   ((FM3_MFS47_CSIO_TypeDef *)FM3_MFS5_CSIO_BASE)\r
+#define FM3_MFS5_LIN    ((FM3_MFS47_LIN_TypeDef *)FM3_MFS5_LIN_BASE)\r
+#define FM3_MFS5_I2C    ((FM3_MFS47_I2C_TypeDef *)FM3_MFS5_I2C_BASE)\r
+#define FM3_MFS6_UART   ((FM3_MFS47_UART_TypeDef *)FM3_MFS6_UART_BASE)\r
+#define FM3_MFS6_CSIO   ((FM3_MFS47_CSIO_TypeDef *)FM3_MFS6_CSIO_BASE)\r
+#define FM3_MFS6_LIN    ((FM3_MFS47_LIN_TypeDef *)FM3_MFS6_LIN_BASE)\r
+#define FM3_MFS6_I2C    ((FM3_MFS47_I2C_TypeDef *)FM3_MFS6_I2C_BASE)\r
+#define FM3_MFS7_UART   ((FM3_MFS47_UART_TypeDef *)FM3_MFS7_UART_BASE)\r
+#define FM3_MFS7_CSIO   ((FM3_MFS47_CSIO_TypeDef *)FM3_MFS7_CSIO_BASE)\r
+#define FM3_MFS7_LIN    ((FM3_MFS47_LIN_TypeDef *)FM3_MFS7_LIN_BASE)\r
+#define FM3_MFS7_I2C    ((FM3_MFS47_I2C_TypeDef *)FM3_MFS7_I2C_BASE)\r
+#define FM3_CRC         ((FM3_CRC_TypeDef *)FM3_CRC_BASE)\r
+#define FM3_WC          ((FM3_WC_TypeDef *)FM3_WC_BASE)\r
+#define FM3_EXBUS       ((FM3_EXBUS_TypeDef *)FM3_EXBUS_BASE)\r
+#define FM3_USB0        ((FM3_USB_TypeDef *)FM3_USB0_BASE)\r
+#define FM3_DMAC        ((FM3_DMAC_TypeDef *)FM3_DMAC_BASE)\r
+#define FM3_CAN0        ((FM3_CAN_TypeDef *)FM3_CAN0_BASE)\r
+#define FM3_CAN1        ((FM3_CAN_TypeDef *)FM3_CAN1_BASE)\r
+\r
+/******************************************************************************\r
+ * Peripheral Bit Band Alias declaration\r
+ ******************************************************************************/\r
+\r
+/* Flash interface registers */\r
+#define bFM3_FLASH_IF_FASZR_ASZ0               *((volatile unsigned int*)(0x42000000UL))\r
+#define bFM3_FLASH_IF_FASZR_ASZ1               *((volatile unsigned int*)(0x42000004UL))\r
+#define bFM3_FLASH_IF_FRWTR_RWT0               *((volatile unsigned int*)(0x42000080UL))\r
+#define bFM3_FLASH_IF_FRWTR_RWT1               *((volatile unsigned int*)(0x42000084UL))\r
+#define bFM3_FLASH_IF_FSTR_RDY                 *((volatile unsigned int*)(0x42000100UL))\r
+#define bFM3_FLASH_IF_FSTR_HNG                 *((volatile unsigned int*)(0x42000104UL))\r
+#define bFM3_FLASH_IF_FSYNDN_SD0               *((volatile unsigned int*)(0x42000200UL))\r
+#define bFM3_FLASH_IF_FSYNDN_SD1               *((volatile unsigned int*)(0x42000204UL))\r
+#define bFM3_FLASH_IF_FSYNDN_SD2               *((volatile unsigned int*)(0x42000208UL))\r
+#define bFM3_FLASH_IF_CRTRMM_TRMM0             *((volatile unsigned int*)(0x42002000UL))\r
+#define bFM3_FLASH_IF_CRTRMM_TRMM1             *((volatile unsigned int*)(0x42002004UL))\r
+#define bFM3_FLASH_IF_CRTRMM_TRMM2             *((volatile unsigned int*)(0x42002008UL))\r
+#define bFM3_FLASH_IF_CRTRMM_TRMM3             *((volatile unsigned int*)(0x4200200CUL))\r
+#define bFM3_FLASH_IF_CRTRMM_TRMM4             *((volatile unsigned int*)(0x42002010UL))\r
+#define bFM3_FLASH_IF_CRTRMM_TRMM5             *((volatile unsigned int*)(0x42002014UL))\r
+#define bFM3_FLASH_IF_CRTRMM_TRMM6             *((volatile unsigned int*)(0x42002018UL))\r
+#define bFM3_FLASH_IF_CRTRMM_TRMM7             *((volatile unsigned int*)(0x4200201CUL))\r
+#define bFM3_FLASH_IF_CRTRMM_TRMM8             *((volatile unsigned int*)(0x42002020UL))\r
+#define bFM3_FLASH_IF_CRTRMM_TRMM9             *((volatile unsigned int*)(0x42002024UL))\r
+\r
+/* Clock and reset registers */\r
+#define bFM3_CRG_SCM_CTL_MOSCE                 *((volatile unsigned int*)(0x42200004UL))\r
+#define bFM3_CRG_SCM_CTL_SOSCE                 *((volatile unsigned int*)(0x4220000CUL))\r
+#define bFM3_CRG_SCM_CTL_PLLE                  *((volatile unsigned int*)(0x42200010UL))\r
+#define bFM3_CRG_SCM_CTL_RCS0                  *((volatile unsigned int*)(0x42200014UL))\r
+#define bFM3_CRG_SCM_CTL_RCS1                  *((volatile unsigned int*)(0x42200018UL))\r
+#define bFM3_CRG_SCM_CTL_RCS2                  *((volatile unsigned int*)(0x4220001CUL))\r
+#define bFM3_CRG_SCM_STR_MORDY                 *((volatile unsigned int*)(0x42200084UL))\r
+#define bFM3_CRG_SCM_STR_SORDY                 *((volatile unsigned int*)(0x4220008CUL))\r
+#define bFM3_CRG_SCM_STR_PLRDY                 *((volatile unsigned int*)(0x42200090UL))\r
+#define bFM3_CRG_SCM_STR_RCM0                  *((volatile unsigned int*)(0x42200094UL))\r
+#define bFM3_CRG_SCM_STR_RCM1                  *((volatile unsigned int*)(0x42200098UL))\r
+#define bFM3_CRG_SCM_STR_RCM2                  *((volatile unsigned int*)(0x4220009CUL))\r
+#define bFM3_CRG_RST_STR_PONR                  *((volatile unsigned int*)(0x42200180UL))\r
+#define bFM3_CRG_RST_STR_INITX                 *((volatile unsigned int*)(0x42200184UL))\r
+#define bFM3_CRG_RST_STR_SWDT                  *((volatile unsigned int*)(0x42200190UL))\r
+#define bFM3_CRG_RST_STR_HWDT                  *((volatile unsigned int*)(0x42200194UL))\r
+#define bFM3_CRG_RST_STR_CSVR                  *((volatile unsigned int*)(0x42200198UL))\r
+#define bFM3_CRG_RST_STR_FCSR                  *((volatile unsigned int*)(0x4220019CUL))\r
+#define bFM3_CRG_RST_STR_SRST                  *((volatile unsigned int*)(0x422001A0UL))\r
+#define bFM3_CRG_BSC_PSR_BSR0                  *((volatile unsigned int*)(0x42200200UL))\r
+#define bFM3_CRG_BSC_PSR_BSR1                  *((volatile unsigned int*)(0x42200204UL))\r
+#define bFM3_CRG_BSC_PSR_BSR2                  *((volatile unsigned int*)(0x42200208UL))\r
+#define bFM3_CRG_APBC0_PSR_APBC00              *((volatile unsigned int*)(0x42200280UL))\r
+#define bFM3_CRG_APBC0_PSR_APBC01              *((volatile unsigned int*)(0x42200284UL))\r
+#define bFM3_CRG_APBC1_PSR_APBC10              *((volatile unsigned int*)(0x42200300UL))\r
+#define bFM3_CRG_APBC1_PSR_APBC11              *((volatile unsigned int*)(0x42200304UL))\r
+#define bFM3_CRG_APBC1_PSR_APBC1RST            *((volatile unsigned int*)(0x42200310UL))\r
+#define bFM3_CRG_APBC1_PSR_APBC1EN             *((volatile unsigned int*)(0x4220031CUL))\r
+#define bFM3_CRG_APBC2_PSR_APBC20              *((volatile unsigned int*)(0x42200380UL))\r
+#define bFM3_CRG_APBC2_PSR_APBC21              *((volatile unsigned int*)(0x42200384UL))\r
+#define bFM3_CRG_APBC2_PSR_APBC2RST            *((volatile unsigned int*)(0x42200390UL))\r
+#define bFM3_CRG_APBC2_PSR_APBC2EN             *((volatile unsigned int*)(0x4220039CUL))\r
+#define bFM3_CRG_SWC_PSR_SWDS0                 *((volatile unsigned int*)(0x42200400UL))\r
+#define bFM3_CRG_SWC_PSR_SWDS1                 *((volatile unsigned int*)(0x42200404UL))\r
+#define bFM3_CRG_SWC_PSR_TESTB                 *((volatile unsigned int*)(0x4220041CUL))\r
+#define bFM3_CRG_TTC_PSR_TTC                   *((volatile unsigned int*)(0x42200500UL))\r
+#define bFM3_CRG_CSW_TMR_MOWT0                 *((volatile unsigned int*)(0x42200600UL))\r
+#define bFM3_CRG_CSW_TMR_MOWT1                 *((volatile unsigned int*)(0x42200604UL))\r
+#define bFM3_CRG_CSW_TMR_MOWT2                 *((volatile unsigned int*)(0x42200608UL))\r
+#define bFM3_CRG_CSW_TMR_MOWT3                 *((volatile unsigned int*)(0x4220060CUL))\r
+#define bFM3_CRG_CSW_TMR_SOWT0                 *((volatile unsigned int*)(0x42200610UL))\r
+#define bFM3_CRG_CSW_TMR_SOWT1                 *((volatile unsigned int*)(0x42200614UL))\r
+#define bFM3_CRG_CSW_TMR_SOWT2                 *((volatile unsigned int*)(0x42200618UL))\r
+#define bFM3_CRG_PSW_TMR_POWT0                 *((volatile unsigned int*)(0x42200680UL))\r
+#define bFM3_CRG_PSW_TMR_POWT1                 *((volatile unsigned int*)(0x42200684UL))\r
+#define bFM3_CRG_PSW_TMR_POWT2                 *((volatile unsigned int*)(0x42200688UL))\r
+#define bFM3_CRG_PSW_TMR_PINC                  *((volatile unsigned int*)(0x42200690UL))\r
+#define bFM3_CRG_PLL_CTL1_PLLM0                *((volatile unsigned int*)(0x42200700UL))\r
+#define bFM3_CRG_PLL_CTL1_PLLM1                *((volatile unsigned int*)(0x42200704UL))\r
+#define bFM3_CRG_PLL_CTL1_PLLM2                *((volatile unsigned int*)(0x42200708UL))\r
+#define bFM3_CRG_PLL_CTL1_PLLM3                *((volatile unsigned int*)(0x4220070CUL))\r
+#define bFM3_CRG_PLL_CTL1_PLLK0                *((volatile unsigned int*)(0x42200710UL))\r
+#define bFM3_CRG_PLL_CTL1_PLLK1                *((volatile unsigned int*)(0x42200714UL))\r
+#define bFM3_CRG_PLL_CTL1_PLLK2                *((volatile unsigned int*)(0x42200718UL))\r
+#define bFM3_CRG_PLL_CTL1_PLLK3                *((volatile unsigned int*)(0x4220071CUL))\r
+#define bFM3_CRG_PLL_CTL2_PLLN0                *((volatile unsigned int*)(0x42200780UL))\r
+#define bFM3_CRG_PLL_CTL2_PLLN1                *((volatile unsigned int*)(0x42200784UL))\r
+#define bFM3_CRG_PLL_CTL2_PLLN2                *((volatile unsigned int*)(0x42200788UL))\r
+#define bFM3_CRG_PLL_CTL2_PLLN3                *((volatile unsigned int*)(0x4220078CUL))\r
+#define bFM3_CRG_PLL_CTL2_PLLN4                *((volatile unsigned int*)(0x42200790UL))\r
+#define bFM3_CRG_CSV_CTL_MCSVE                 *((volatile unsigned int*)(0x42200800UL))\r
+#define bFM3_CRG_CSV_CTL_SCSVE                 *((volatile unsigned int*)(0x42200804UL))\r
+#define bFM3_CRG_CSV_CTL_FCSDE                 *((volatile unsigned int*)(0x42200820UL))\r
+#define bFM3_CRG_CSV_CTL_FCSRE                 *((volatile unsigned int*)(0x42200824UL))\r
+#define bFM3_CRG_CSV_CTL_FCD0                  *((volatile unsigned int*)(0x42200830UL))\r
+#define bFM3_CRG_CSV_CTL_FCD1                  *((volatile unsigned int*)(0x42200834UL))\r
+#define bFM3_CRG_CSV_CTL_FCD2                  *((volatile unsigned int*)(0x42200838UL))\r
+#define bFM3_CRG_CSV_STR_MCMF                  *((volatile unsigned int*)(0x42200880UL))\r
+#define bFM3_CRG_CSV_STR_SCMF                  *((volatile unsigned int*)(0x42200884UL))\r
+#define bFM3_CRG_DBWDT_CTL_DPSWBE              *((volatile unsigned int*)(0x42200A94UL))\r
+#define bFM3_CRG_DBWDT_CTL_DPHWBE              *((volatile unsigned int*)(0x42200A9CUL))\r
+#define bFM3_CRG_INT_ENR_MCSE                  *((volatile unsigned int*)(0x42200C00UL))\r
+#define bFM3_CRG_INT_ENR_SCSE                  *((volatile unsigned int*)(0x42200C04UL))\r
+#define bFM3_CRG_INT_ENR_PCSE                  *((volatile unsigned int*)(0x42200C08UL))\r
+#define bFM3_CRG_INT_ENR_FCSE                  *((volatile unsigned int*)(0x42200C14UL))\r
+#define bFM3_CRG_INT_STR_MCSI                  *((volatile unsigned int*)(0x42200C80UL))\r
+#define bFM3_CRG_INT_STR_SCSI                  *((volatile unsigned int*)(0x42200C84UL))\r
+#define bFM3_CRG_INT_STR_PCSI                  *((volatile unsigned int*)(0x42200C88UL))\r
+#define bFM3_CRG_INT_STR_FCSI                  *((volatile unsigned int*)(0x42200C94UL))\r
+#define bFM3_CRG_INT_CLR_MCSC                  *((volatile unsigned int*)(0x42200D00UL))\r
+#define bFM3_CRG_INT_CLR_SCSC                  *((volatile unsigned int*)(0x42200D04UL))\r
+#define bFM3_CRG_INT_CLR_PCSC                  *((volatile unsigned int*)(0x42200D08UL))\r
+#define bFM3_CRG_INT_CLR_FCSC                  *((volatile unsigned int*)(0x42200D14UL))\r
+\r
+/* Hardware watchdog registers */\r
+#define bFM3_HWWDT_WDG_CTL_INTEN               *((volatile unsigned int*)(0x42220100UL))\r
+#define bFM3_HWWDT_WDG_CTL_RESEN               *((volatile unsigned int*)(0x42220104UL))\r
+#define bFM3_HWWDT_WDG_RIS_RIS                 *((volatile unsigned int*)(0x42220200UL))\r
+\r
+/* Software watchdog registers */\r
+#define bFM3_SWWDT_WDOGCONTROL_INTEN           *((volatile unsigned int*)(0x42240100UL))\r
+#define bFM3_SWWDT_WDOGCONTROL_RESEN           *((volatile unsigned int*)(0x42240104UL))\r
+#define bFM3_SWWDT_WDOGRIS_RIS                 *((volatile unsigned int*)(0x42240200UL))\r
+\r
+/* Dual timer 1/2 registers */\r
+#define bFM3_DTIM_TIMER1CONTROL_ONESHOT        *((volatile unsigned int*)(0x422A0100UL))\r
+#define bFM3_DTIM_TIMER1CONTROL_TIMERSIZE      *((volatile unsigned int*)(0x422A0104UL))\r
+#define bFM3_DTIM_TIMER1CONTROL_TIMERPRE0      *((volatile unsigned int*)(0x422A0108UL))\r
+#define bFM3_DTIM_TIMER1CONTROL_TIMERPRE1      *((volatile unsigned int*)(0x422A010CUL))\r
+#define bFM3_DTIM_TIMER1CONTROL_INTENABLE      *((volatile unsigned int*)(0x422A0114UL))\r
+#define bFM3_DTIM_TIMER1CONTROL_TIMERMODE      *((volatile unsigned int*)(0x422A0118UL))\r
+#define bFM3_DTIM_TIMER1CONTROL_TIMEREN        *((volatile unsigned int*)(0x422A011CUL))\r
+#define bFM3_DTIM_TIMER1RIS_TIMERXRIS          *((volatile unsigned int*)(0x422A0200UL))\r
+#define bFM3_DTIM_TIMER1MIS_TIMERXRIS          *((volatile unsigned int*)(0x422A0280UL))\r
+#define bFM3_DTIM_TIMER2CONTROL_ONESHOT        *((volatile unsigned int*)(0x422A0500UL))\r
+#define bFM3_DTIM_TIMER2CONTROL_TIMERSIZE      *((volatile unsigned int*)(0x422A0504UL))\r
+#define bFM3_DTIM_TIMER2CONTROL_TIMERPRE0      *((volatile unsigned int*)(0x422A0508UL))\r
+#define bFM3_DTIM_TIMER2CONTROL_TIMERPRE1      *((volatile unsigned int*)(0x422A050CUL))\r
+#define bFM3_DTIM_TIMER2CONTROL_INTENABLE      *((volatile unsigned int*)(0x422A0514UL))\r
+#define bFM3_DTIM_TIMER2CONTROL_TIMERMODE      *((volatile unsigned int*)(0x422A0518UL))\r
+#define bFM3_DTIM_TIMER2CONTROL_TIMEREN        *((volatile unsigned int*)(0x422A051CUL))\r
+#define bFM3_DTIM_TIMER2RIS_TIMERXRIS          *((volatile unsigned int*)(0x422A0600UL))\r
+#define bFM3_DTIM_TIMER2MIS_TIMERXRIS          *((volatile unsigned int*)(0x422A0680UL))\r
+\r
+/* Multifunction Timer unit 0 Free Running Timer registers */\r
+#define bFM3_MFT0_FRT_TCSA0_CLK0               *((volatile unsigned int*)(0x42400600UL))\r
+#define bFM3_MFT0_FRT_TCSA0_CLK1               *((volatile unsigned int*)(0x42400604UL))\r
+#define bFM3_MFT0_FRT_TCSA0_CLK2               *((volatile unsigned int*)(0x42400608UL))\r
+#define bFM3_MFT0_FRT_TCSA0_CLK3               *((volatile unsigned int*)(0x4240060CUL))\r
+#define bFM3_MFT0_FRT_TCSA0_SCLR               *((volatile unsigned int*)(0x42400610UL))\r
+#define bFM3_MFT0_FRT_TCSA0_MODE               *((volatile unsigned int*)(0x42400614UL))\r
+#define bFM3_MFT0_FRT_TCSA0_STOP               *((volatile unsigned int*)(0x42400618UL))\r
+#define bFM3_MFT0_FRT_TCSA0_BFE                *((volatile unsigned int*)(0x4240061CUL))\r
+#define bFM3_MFT0_FRT_TCSA0_ICRE               *((volatile unsigned int*)(0x42400620UL))\r
+#define bFM3_MFT0_FRT_TCSA0_ICLR               *((volatile unsigned int*)(0x42400624UL))\r
+#define bFM3_MFT0_FRT_TCSA0_IRQZE              *((volatile unsigned int*)(0x42400634UL))\r
+#define bFM3_MFT0_FRT_TCSA0_IRQZF              *((volatile unsigned int*)(0x42400638UL))\r
+#define bFM3_MFT0_FRT_TCSA0_ECKE               *((volatile unsigned int*)(0x4240063CUL))\r
+#define bFM3_MFT0_FRT_TCSB0_AD0E               *((volatile unsigned int*)(0x42400680UL))\r
+#define bFM3_MFT0_FRT_TCSB0_AD1E               *((volatile unsigned int*)(0x42400684UL))\r
+#define bFM3_MFT0_FRT_TCSB0_AD2E               *((volatile unsigned int*)(0x42400688UL))\r
+#define bFM3_MFT0_FRT_TCSA1_CLK0               *((volatile unsigned int*)(0x42400800UL))\r
+#define bFM3_MFT0_FRT_TCSA1_CLK1               *((volatile unsigned int*)(0x42400804UL))\r
+#define bFM3_MFT0_FRT_TCSA1_CLK2               *((volatile unsigned int*)(0x42400808UL))\r
+#define bFM3_MFT0_FRT_TCSA1_CLK3               *((volatile unsigned int*)(0x4240080CUL))\r
+#define bFM3_MFT0_FRT_TCSA1_SCLR               *((volatile unsigned int*)(0x42400810UL))\r
+#define bFM3_MFT0_FRT_TCSA1_MODE               *((volatile unsigned int*)(0x42400814UL))\r
+#define bFM3_MFT0_FRT_TCSA1_STOP               *((volatile unsigned int*)(0x42400818UL))\r
+#define bFM3_MFT0_FRT_TCSA1_BFE                *((volatile unsigned int*)(0x4240081CUL))\r
+#define bFM3_MFT0_FRT_TCSA1_ICRE               *((volatile unsigned int*)(0x42400820UL))\r
+#define bFM3_MFT0_FRT_TCSA1_ICLR               *((volatile unsigned int*)(0x42400824UL))\r
+#define bFM3_MFT0_FRT_TCSA1_IRQZE              *((volatile unsigned int*)(0x42400834UL))\r
+#define bFM3_MFT0_FRT_TCSA1_IRQZF              *((volatile unsigned int*)(0x42400838UL))\r
+#define bFM3_MFT0_FRT_TCSA1_ECKE               *((volatile unsigned int*)(0x4240083CUL))\r
+#define bFM3_MFT0_FRT_TCSB1_AD0E               *((volatile unsigned int*)(0x42400880UL))\r
+#define bFM3_MFT0_FRT_TCSB1_AD1E               *((volatile unsigned int*)(0x42400884UL))\r
+#define bFM3_MFT0_FRT_TCSB1_AD2E               *((volatile unsigned int*)(0x42400888UL))\r
+#define bFM3_MFT0_FRT_TCSA2_CLK0               *((volatile unsigned int*)(0x42400A00UL))\r
+#define bFM3_MFT0_FRT_TCSA2_CLK1               *((volatile unsigned int*)(0x42400A04UL))\r
+#define bFM3_MFT0_FRT_TCSA2_CLK2               *((volatile unsigned int*)(0x42400A08UL))\r
+#define bFM3_MFT0_FRT_TCSA2_CLK3               *((volatile unsigned int*)(0x42400A0CUL))\r
+#define bFM3_MFT0_FRT_TCSA2_SCLR               *((volatile unsigned int*)(0x42400A10UL))\r
+#define bFM3_MFT0_FRT_TCSA2_MODE               *((volatile unsigned int*)(0x42400A14UL))\r
+#define bFM3_MFT0_FRT_TCSA2_STOP               *((volatile unsigned int*)(0x42400A18UL))\r
+#define bFM3_MFT0_FRT_TCSA2_BFE                *((volatile unsigned int*)(0x42400A1CUL))\r
+#define bFM3_MFT0_FRT_TCSA2_ICRE               *((volatile unsigned int*)(0x42400A20UL))\r
+#define bFM3_MFT0_FRT_TCSA2_ICLR               *((volatile unsigned int*)(0x42400A24UL))\r
+#define bFM3_MFT0_FRT_TCSA2_IRQZE              *((volatile unsigned int*)(0x42400A34UL))\r
+#define bFM3_MFT0_FRT_TCSA2_IRQZF              *((volatile unsigned int*)(0x42400A38UL))\r
+#define bFM3_MFT0_FRT_TCSA2_ECKE               *((volatile unsigned int*)(0x42400A3CUL))\r
+#define bFM3_MFT0_FRT_TCSB2_AD0E               *((volatile unsigned int*)(0x42400A80UL))\r
+#define bFM3_MFT0_FRT_TCSB2_AD1E               *((volatile unsigned int*)(0x42400A84UL))\r
+#define bFM3_MFT0_FRT_TCSB2_AD2E               *((volatile unsigned int*)(0x42400A88UL))\r
+\r
+/* Multifunction Timer unit 0 Output Compare Unit registers */\r
+#define bFM3_MFT0_OCU_OCSA10_CST0              *((volatile unsigned int*)(0x42400300UL))\r
+#define bFM3_MFT0_OCU_OCSA10_CST1              *((volatile unsigned int*)(0x42400304UL))\r
+#define bFM3_MFT0_OCU_OCSA10_BDIS0             *((volatile unsigned int*)(0x42400308UL))\r
+#define bFM3_MFT0_OCU_OCSA10_BDIS1             *((volatile unsigned int*)(0x4240030CUL))\r
+#define bFM3_MFT0_OCU_OCSA10_IOE0              *((volatile unsigned int*)(0x42400310UL))\r
+#define bFM3_MFT0_OCU_OCSA10_IOE1              *((volatile unsigned int*)(0x42400314UL))\r
+#define bFM3_MFT0_OCU_OCSA10_IOP0              *((volatile unsigned int*)(0x42400318UL))\r
+#define bFM3_MFT0_OCU_OCSA10_IOP1              *((volatile unsigned int*)(0x4240031CUL))\r
+#define bFM3_MFT0_OCU_OCSB10_OTD0              *((volatile unsigned int*)(0x42400320UL))\r
+#define bFM3_MFT0_OCU_OCSB10_OTD1              *((volatile unsigned int*)(0x42400324UL))\r
+#define bFM3_MFT0_OCU_OCSB10_CMOD              *((volatile unsigned int*)(0x42400330UL))\r
+#define bFM3_MFT0_OCU_OCSB10_BTS0              *((volatile unsigned int*)(0x42400334UL))\r
+#define bFM3_MFT0_OCU_OCSB10_BTS1              *((volatile unsigned int*)(0x42400338UL))\r
+#define bFM3_MFT0_OCU_OCSA32_CST2              *((volatile unsigned int*)(0x42400380UL))\r
+#define bFM3_MFT0_OCU_OCSA32_CST3              *((volatile unsigned int*)(0x42400384UL))\r
+#define bFM3_MFT0_OCU_OCSA32_BDIS2             *((volatile unsigned int*)(0x42400388UL))\r
+#define bFM3_MFT0_OCU_OCSA32_BDIS3             *((volatile unsigned int*)(0x4240038CUL))\r
+#define bFM3_MFT0_OCU_OCSA32_IOE2              *((volatile unsigned int*)(0x42400390UL))\r
+#define bFM3_MFT0_OCU_OCSA32_IOE3              *((volatile unsigned int*)(0x42400394UL))\r
+#define bFM3_MFT0_OCU_OCSA32_IOP2              *((volatile unsigned int*)(0x42400398UL))\r
+#define bFM3_MFT0_OCU_OCSA32_IOP3              *((volatile unsigned int*)(0x4240039CUL))\r
+#define bFM3_MFT0_OCU_OCSB32_OTD2              *((volatile unsigned int*)(0x424003A0UL))\r
+#define bFM3_MFT0_OCU_OCSB32_OTD3              *((volatile unsigned int*)(0x424003A4UL))\r
+#define bFM3_MFT0_OCU_OCSB32_CMOD              *((volatile unsigned int*)(0x424003B0UL))\r
+#define bFM3_MFT0_OCU_OCSB32_BTS2              *((volatile unsigned int*)(0x424003B4UL))\r
+#define bFM3_MFT0_OCU_OCSB32_BTS3              *((volatile unsigned int*)(0x424003B8UL))\r
+#define bFM3_MFT0_OCU_OCSA54_CST4              *((volatile unsigned int*)(0x42400400UL))\r
+#define bFM3_MFT0_OCU_OCSA54_CST5              *((volatile unsigned int*)(0x42400404UL))\r
+#define bFM3_MFT0_OCU_OCSA54_BDIS4             *((volatile unsigned int*)(0x42400408UL))\r
+#define bFM3_MFT0_OCU_OCSA54_BDIS5             *((volatile unsigned int*)(0x4240040CUL))\r
+#define bFM3_MFT0_OCU_OCSA54_IOE4              *((volatile unsigned int*)(0x42400410UL))\r
+#define bFM3_MFT0_OCU_OCSA54_IOE5              *((volatile unsigned int*)(0x42400414UL))\r
+#define bFM3_MFT0_OCU_OCSA54_IOP4              *((volatile unsigned int*)(0x42400418UL))\r
+#define bFM3_MFT0_OCU_OCSA54_IOP5              *((volatile unsigned int*)(0x4240041CUL))\r
+#define bFM3_MFT0_OCU_OCSB54_OTD4              *((volatile unsigned int*)(0x42400420UL))\r
+#define bFM3_MFT0_OCU_OCSB54_OTD5              *((volatile unsigned int*)(0x42400424UL))\r
+#define bFM3_MFT0_OCU_OCSB54_CMOD              *((volatile unsigned int*)(0x42400430UL))\r
+#define bFM3_MFT0_OCU_OCSB54_BTS4              *((volatile unsigned int*)(0x42400434UL))\r
+#define bFM3_MFT0_OCU_OCSB54_BTS5              *((volatile unsigned int*)(0x42400438UL))\r
+#define bFM3_MFT0_OCU_OCSC_MOD0                *((volatile unsigned int*)(0x424004A0UL))\r
+#define bFM3_MFT0_OCU_OCSC_MOD1                *((volatile unsigned int*)(0x424004A4UL))\r
+#define bFM3_MFT0_OCU_OCSC_MOD2                *((volatile unsigned int*)(0x424004A8UL))\r
+#define bFM3_MFT0_OCU_OCSC_MOD3                *((volatile unsigned int*)(0x424004ACUL))\r
+#define bFM3_MFT0_OCU_OCSC_MOD4                *((volatile unsigned int*)(0x424004B0UL))\r
+#define bFM3_MFT0_OCU_OCSC_MOD5                *((volatile unsigned int*)(0x424004B4UL))\r
+#define bFM3_MFT0_OCU_OCFS10_FSO00             *((volatile unsigned int*)(0x42400B00UL))\r
+#define bFM3_MFT0_OCU_OCFS10_FSO01             *((volatile unsigned int*)(0x42400B04UL))\r
+#define bFM3_MFT0_OCU_OCFS10_FSO02             *((volatile unsigned int*)(0x42400B08UL))\r
+#define bFM3_MFT0_OCU_OCFS10_FSO03             *((volatile unsigned int*)(0x42400B0CUL))\r
+#define bFM3_MFT0_OCU_OCFS10_FSO10             *((volatile unsigned int*)(0x42400B10UL))\r
+#define bFM3_MFT0_OCU_OCFS10_FSO11             *((volatile unsigned int*)(0x42400B14UL))\r
+#define bFM3_MFT0_OCU_OCFS10_FSO12             *((volatile unsigned int*)(0x42400B18UL))\r
+#define bFM3_MFT0_OCU_OCFS10_FSO13             *((volatile unsigned int*)(0x42400B1CUL))\r
+#define bFM3_MFT0_OCU_OCFS32_FSO20             *((volatile unsigned int*)(0x42400B20UL))\r
+#define bFM3_MFT0_OCU_OCFS32_FSO21             *((volatile unsigned int*)(0x42400B24UL))\r
+#define bFM3_MFT0_OCU_OCFS32_FSO22             *((volatile unsigned int*)(0x42400B28UL))\r
+#define bFM3_MFT0_OCU_OCFS32_FSO23             *((volatile unsigned int*)(0x42400B2CUL))\r
+#define bFM3_MFT0_OCU_OCFS32_FSO30             *((volatile unsigned int*)(0x42400B30UL))\r
+#define bFM3_MFT0_OCU_OCFS32_FSO31             *((volatile unsigned int*)(0x42400B34UL))\r
+#define bFM3_MFT0_OCU_OCFS32_FSO32             *((volatile unsigned int*)(0x42400B38UL))\r
+#define bFM3_MFT0_OCU_OCFS32_FSO33             *((volatile unsigned int*)(0x42400B3CUL))\r
+#define bFM3_MFT0_OCU_OCFS54_FSO40             *((volatile unsigned int*)(0x42400B80UL))\r
+#define bFM3_MFT0_OCU_OCFS54_FSO41             *((volatile unsigned int*)(0x42400B84UL))\r
+#define bFM3_MFT0_OCU_OCFS54_FSO42             *((volatile unsigned int*)(0x42400B88UL))\r
+#define bFM3_MFT0_OCU_OCFS54_FSO43             *((volatile unsigned int*)(0x42400B8CUL))\r
+#define bFM3_MFT0_OCU_OCFS54_FSO50             *((volatile unsigned int*)(0x42400B90UL))\r
+#define bFM3_MFT0_OCU_OCFS54_FSO51             *((volatile unsigned int*)(0x42400B94UL))\r
+#define bFM3_MFT0_OCU_OCFS54_FSO52             *((volatile unsigned int*)(0x42400B98UL))\r
+#define bFM3_MFT0_OCU_OCFS54_FSO53             *((volatile unsigned int*)(0x42400B9CUL))\r
+\r
+/* Multifunction Timer unit 0 Waveform Generator and Noise Canceler registers */\r
+#define bFM3_MFT0_WFG_WFSA10_DCK0              *((volatile unsigned int*)(0x42401180UL))\r
+#define bFM3_MFT0_WFG_WFSA10_DCK1              *((volatile unsigned int*)(0x42401184UL))\r
+#define bFM3_MFT0_WFG_WFSA10_DCK2              *((volatile unsigned int*)(0x42401188UL))\r
+#define bFM3_MFT0_WFG_WFSA10_TMD0              *((volatile unsigned int*)(0x4240118CUL))\r
+#define bFM3_MFT0_WFG_WFSA10_TMD1              *((volatile unsigned int*)(0x42401190UL))\r
+#define bFM3_MFT0_WFG_WFSA10_TMD2              *((volatile unsigned int*)(0x42401194UL))\r
+#define bFM3_MFT0_WFG_WFSA10_GTEN0             *((volatile unsigned int*)(0x42401198UL))\r
+#define bFM3_MFT0_WFG_WFSA10_GTEN1             *((volatile unsigned int*)(0x4240119CUL))\r
+#define bFM3_MFT0_WFG_WFSA10_PSEL0             *((volatile unsigned int*)(0x424011A0UL))\r
+#define bFM3_MFT0_WFG_WFSA10_PSEL1             *((volatile unsigned int*)(0x424011A4UL))\r
+#define bFM3_MFT0_WFG_WFSA10_PGEN0             *((volatile unsigned int*)(0x424011A8UL))\r
+#define bFM3_MFT0_WFG_WFSA10_PGEN1             *((volatile unsigned int*)(0x424011ACUL))\r
+#define bFM3_MFT0_WFG_WFSA10_DMOD              *((volatile unsigned int*)(0x424011B0UL))\r
+#define bFM3_MFT0_WFG_WFSA32_DCK0              *((volatile unsigned int*)(0x42401200UL))\r
+#define bFM3_MFT0_WFG_WFSA32_DCK1              *((volatile unsigned int*)(0x42401204UL))\r
+#define bFM3_MFT0_WFG_WFSA32_DCK2              *((volatile unsigned int*)(0x42401208UL))\r
+#define bFM3_MFT0_WFG_WFSA32_TMD0              *((volatile unsigned int*)(0x4240120CUL))\r
+#define bFM3_MFT0_WFG_WFSA32_TMD1              *((volatile unsigned int*)(0x42401210UL))\r
+#define bFM3_MFT0_WFG_WFSA32_TMD2              *((volatile unsigned int*)(0x42401214UL))\r
+#define bFM3_MFT0_WFG_WFSA32_GTEN0             *((volatile unsigned int*)(0x42401218UL))\r
+#define bFM3_MFT0_WFG_WFSA32_GTEN1             *((volatile unsigned int*)(0x4240121CUL))\r
+#define bFM3_MFT0_WFG_WFSA32_PSEL0             *((volatile unsigned int*)(0x42401220UL))\r
+#define bFM3_MFT0_WFG_WFSA32_PSEL1             *((volatile unsigned int*)(0x42401224UL))\r
+#define bFM3_MFT0_WFG_WFSA32_PGEN0             *((volatile unsigned int*)(0x42401228UL))\r
+#define bFM3_MFT0_WFG_WFSA32_PGEN1             *((volatile unsigned int*)(0x4240122CUL))\r
+#define bFM3_MFT0_WFG_WFSA32_DMOD              *((volatile unsigned int*)(0x42401230UL))\r
+#define bFM3_MFT0_WFG_WFSA54_DCK0              *((volatile unsigned int*)(0x42401280UL))\r
+#define bFM3_MFT0_WFG_WFSA54_DCK1              *((volatile unsigned int*)(0x42401284UL))\r
+#define bFM3_MFT0_WFG_WFSA54_DCK2              *((volatile unsigned int*)(0x42401288UL))\r
+#define bFM3_MFT0_WFG_WFSA54_TMD0              *((volatile unsigned int*)(0x4240128CUL))\r
+#define bFM3_MFT0_WFG_WFSA54_TMD1              *((volatile unsigned int*)(0x42401290UL))\r
+#define bFM3_MFT0_WFG_WFSA54_TMD2              *((volatile unsigned int*)(0x42401294UL))\r
+#define bFM3_MFT0_WFG_WFSA54_GTEN0             *((volatile unsigned int*)(0x42401298UL))\r
+#define bFM3_MFT0_WFG_WFSA54_GTEN1             *((volatile unsigned int*)(0x4240129CUL))\r
+#define bFM3_MFT0_WFG_WFSA54_PSEL0             *((volatile unsigned int*)(0x424012A0UL))\r
+#define bFM3_MFT0_WFG_WFSA54_PSEL1             *((volatile unsigned int*)(0x424012A4UL))\r
+#define bFM3_MFT0_WFG_WFSA54_PGEN0             *((volatile unsigned int*)(0x424012A8UL))\r
+#define bFM3_MFT0_WFG_WFSA54_PGEN1             *((volatile unsigned int*)(0x424012ACUL))\r
+#define bFM3_MFT0_WFG_WFSA54_DMOD              *((volatile unsigned int*)(0x424012B0UL))\r
+#define bFM3_MFT0_WFG_WFIR_DTIF                *((volatile unsigned int*)(0x42401300UL))\r
+#define bFM3_MFT0_WFG_WFIR_DTIC                *((volatile unsigned int*)(0x42401304UL))\r
+#define bFM3_MFT0_WFG_WFIR_TMIF10              *((volatile unsigned int*)(0x42401310UL))\r
+#define bFM3_MFT0_WFG_WFIR_TMIC10              *((volatile unsigned int*)(0x42401314UL))\r
+#define bFM3_MFT0_WFG_WFIR_TMIE10              *((volatile unsigned int*)(0x42401318UL))\r
+#define bFM3_MFT0_WFG_WFIR_TMIS10              *((volatile unsigned int*)(0x4240131CUL))\r
+#define bFM3_MFT0_WFG_WFIR_TMIF32              *((volatile unsigned int*)(0x42401320UL))\r
+#define bFM3_MFT0_WFG_WFIR_TMIC32              *((volatile unsigned int*)(0x42401324UL))\r
+#define bFM3_MFT0_WFG_WFIR_TMIE32              *((volatile unsigned int*)(0x42401328UL))\r
+#define bFM3_MFT0_WFG_WFIR_TMIS32              *((volatile unsigned int*)(0x4240132CUL))\r
+#define bFM3_MFT0_WFG_WFIR_TMIF54              *((volatile unsigned int*)(0x42401330UL))\r
+#define bFM3_MFT0_WFG_WFIR_TMIC54              *((volatile unsigned int*)(0x42401334UL))\r
+#define bFM3_MFT0_WFG_WFIR_TMIE54              *((volatile unsigned int*)(0x42401338UL))\r
+#define bFM3_MFT0_WFG_WFIR_TMIS54              *((volatile unsigned int*)(0x4240133CUL))\r
+#define bFM3_MFT0_WFG_NZCL_DTIE                *((volatile unsigned int*)(0x42401380UL))\r
+#define bFM3_MFT0_WFG_NZCL_NWS0                *((volatile unsigned int*)(0x42401384UL))\r
+#define bFM3_MFT0_WFG_NZCL_NWS1                *((volatile unsigned int*)(0x42401388UL))\r
+#define bFM3_MFT0_WFG_NZCL_NWS2                *((volatile unsigned int*)(0x4240138CUL))\r
+#define bFM3_MFT0_WFG_NZCL_SDTI                *((volatile unsigned int*)(0x42401390UL))\r
+\r
+/* Multifunction Timer unit 0 Input Capture Unit registers */\r
+#define bFM3_MFT0_ICU_ICFS10_FSI00             *((volatile unsigned int*)(0x42400C00UL))\r
+#define bFM3_MFT0_ICU_ICFS10_FSI01             *((volatile unsigned int*)(0x42400C04UL))\r
+#define bFM3_MFT0_ICU_ICFS10_FSI02             *((volatile unsigned int*)(0x42400C08UL))\r
+#define bFM3_MFT0_ICU_ICFS10_FSI03             *((volatile unsigned int*)(0x42400C0CUL))\r
+#define bFM3_MFT0_ICU_ICFS10_FSI10             *((volatile unsigned int*)(0x42400C10UL))\r
+#define bFM3_MFT0_ICU_ICFS10_FSI11             *((volatile unsigned int*)(0x42400C14UL))\r
+#define bFM3_MFT0_ICU_ICFS10_FSI12             *((volatile unsigned int*)(0x42400C18UL))\r
+#define bFM3_MFT0_ICU_ICFS10_FSI13             *((volatile unsigned int*)(0x42400C1CUL))\r
+#define bFM3_MFT0_ICU_ICFS32_FSI20             *((volatile unsigned int*)(0x42400C20UL))\r
+#define bFM3_MFT0_ICU_ICFS32_FSI21             *((volatile unsigned int*)(0x42400C24UL))\r
+#define bFM3_MFT0_ICU_ICFS32_FSI22             *((volatile unsigned int*)(0x42400C28UL))\r
+#define bFM3_MFT0_ICU_ICFS32_FSI23             *((volatile unsigned int*)(0x42400C2CUL))\r
+#define bFM3_MFT0_ICU_ICFS32_FSI30             *((volatile unsigned int*)(0x42400C30UL))\r
+#define bFM3_MFT0_ICU_ICFS32_FSI31             *((volatile unsigned int*)(0x42400C34UL))\r
+#define bFM3_MFT0_ICU_ICFS32_FSI32             *((volatile unsigned int*)(0x42400C38UL))\r
+#define bFM3_MFT0_ICU_ICFS32_FSI33             *((volatile unsigned int*)(0x42400C3CUL))\r
+#define bFM3_MFT0_ICU_ICSA10_EG00              *((volatile unsigned int*)(0x42400F00UL))\r
+#define bFM3_MFT0_ICU_ICSA10_EG01              *((volatile unsigned int*)(0x42400F04UL))\r
+#define bFM3_MFT0_ICU_ICSA10_EG10              *((volatile unsigned int*)(0x42400F08UL))\r
+#define bFM3_MFT0_ICU_ICSA10_EG11              *((volatile unsigned int*)(0x42400F0CUL))\r
+#define bFM3_MFT0_ICU_ICSA10_ICE0              *((volatile unsigned int*)(0x42400F10UL))\r
+#define bFM3_MFT0_ICU_ICSA10_ICE1              *((volatile unsigned int*)(0x42400F14UL))\r
+#define bFM3_MFT0_ICU_ICSA10_IPC0              *((volatile unsigned int*)(0x42400F18UL))\r
+#define bFM3_MFT0_ICU_ICSA10_IPC1              *((volatile unsigned int*)(0x42400F1CUL))\r
+#define bFM3_MFT0_ICU_ICSB10_IEI0              *((volatile unsigned int*)(0x42400F20UL))\r
+#define bFM3_MFT0_ICU_ICSB10_IEI1              *((volatile unsigned int*)(0x42400F24UL))\r
+#define bFM3_MFT0_ICU_ICSA32_EG20              *((volatile unsigned int*)(0x42400F80UL))\r
+#define bFM3_MFT0_ICU_ICSA32_EG21              *((volatile unsigned int*)(0x42400F84UL))\r
+#define bFM3_MFT0_ICU_ICSA32_EG30              *((volatile unsigned int*)(0x42400F88UL))\r
+#define bFM3_MFT0_ICU_ICSA32_EG31              *((volatile unsigned int*)(0x42400F8CUL))\r
+#define bFM3_MFT0_ICU_ICSA32_ICE2              *((volatile unsigned int*)(0x42400F90UL))\r
+#define bFM3_MFT0_ICU_ICSA32_ICE3              *((volatile unsigned int*)(0x42400F94UL))\r
+#define bFM3_MFT0_ICU_ICSA32_IPC2              *((volatile unsigned int*)(0x42400F98UL))\r
+#define bFM3_MFT0_ICU_ICSA32_IPC3              *((volatile unsigned int*)(0x42400F9CUL))\r
+#define bFM3_MFT0_ICU_ICSB32_IEI2              *((volatile unsigned int*)(0x42400FA0UL))\r
+#define bFM3_MFT0_ICU_ICSB32_IEI3              *((volatile unsigned int*)(0x42400FA4UL))\r
+\r
+/* Multifunction Timer unit 0 ADC Start Compare Unit registers */\r
+#define bFM3_MFT0_ADCMP_ACSB_BDIS0             *((volatile unsigned int*)(0x42401700UL))\r
+#define bFM3_MFT0_ADCMP_ACSB_BDIS1             *((volatile unsigned int*)(0x42401704UL))\r
+#define bFM3_MFT0_ADCMP_ACSB_BDIS2             *((volatile unsigned int*)(0x42401708UL))\r
+#define bFM3_MFT0_ADCMP_ACSB_BTS0              *((volatile unsigned int*)(0x42401710UL))\r
+#define bFM3_MFT0_ADCMP_ACSB_BTS1              *((volatile unsigned int*)(0x42401714UL))\r
+#define bFM3_MFT0_ADCMP_ACSB_BTS2              *((volatile unsigned int*)(0x42401718UL))\r
+#define bFM3_MFT0_ADCMP_ACSA_CE00              *((volatile unsigned int*)(0x42401780UL))\r
+#define bFM3_MFT0_ADCMP_ACSA_CE01              *((volatile unsigned int*)(0x42401784UL))\r
+#define bFM3_MFT0_ADCMP_ACSA_CE10              *((volatile unsigned int*)(0x42401788UL))\r
+#define bFM3_MFT0_ADCMP_ACSA_CE11              *((volatile unsigned int*)(0x4240178CUL))\r
+#define bFM3_MFT0_ADCMP_ACSA_CE20              *((volatile unsigned int*)(0x42401790UL))\r
+#define bFM3_MFT0_ADCMP_ACSA_CE21              *((volatile unsigned int*)(0x42401794UL))\r
+#define bFM3_MFT0_ADCMP_ACSA_SEL00             *((volatile unsigned int*)(0x424017A0UL))\r
+#define bFM3_MFT0_ADCMP_ACSA_SEL01             *((volatile unsigned int*)(0x424017A4UL))\r
+#define bFM3_MFT0_ADCMP_ACSA_SEL10             *((volatile unsigned int*)(0x424017A8UL))\r
+#define bFM3_MFT0_ADCMP_ACSA_SEL11             *((volatile unsigned int*)(0x424017ACUL))\r
+#define bFM3_MFT0_ADCMP_ACSA_SEL20             *((volatile unsigned int*)(0x424017B0UL))\r
+#define bFM3_MFT0_ADCMP_ACSA_SEL21             *((volatile unsigned int*)(0x424017B4UL))\r
+#define bFM3_MFT0_ADCMP_ATSA_AD0S0             *((volatile unsigned int*)(0x42401800UL))\r
+#define bFM3_MFT0_ADCMP_ATSA_AD0S1             *((volatile unsigned int*)(0x42401804UL))\r
+#define bFM3_MFT0_ADCMP_ATSA_AD1S0             *((volatile unsigned int*)(0x42401808UL))\r
+#define bFM3_MFT0_ADCMP_ATSA_AD1S1             *((volatile unsigned int*)(0x4240180CUL))\r
+#define bFM3_MFT0_ADCMP_ATSA_AD2S0             *((volatile unsigned int*)(0x42401810UL))\r
+#define bFM3_MFT0_ADCMP_ATSA_AD2S1             *((volatile unsigned int*)(0x42401814UL))\r
+#define bFM3_MFT0_ADCMP_ATSA_AD0P0             *((volatile unsigned int*)(0x42401820UL))\r
+#define bFM3_MFT0_ADCMP_ATSA_AD0P1             *((volatile unsigned int*)(0x42401824UL))\r
+#define bFM3_MFT0_ADCMP_ATSA_AD1P0             *((volatile unsigned int*)(0x42401828UL))\r
+#define bFM3_MFT0_ADCMP_ATSA_AD1P1             *((volatile unsigned int*)(0x4240182CUL))\r
+#define bFM3_MFT0_ADCMP_ATSA_AD2P0             *((volatile unsigned int*)(0x42401830UL))\r
+#define bFM3_MFT0_ADCMP_ATSA_AD2P1             *((volatile unsigned int*)(0x42401834UL))\r
+\r
+/* Multifunction Timer unit 1 Free Running Timer registers */\r
+#define bFM3_MFT1_FRT_TCSA0_CLK0               *((volatile unsigned int*)(0x42420600UL))\r
+#define bFM3_MFT1_FRT_TCSA0_CLK1               *((volatile unsigned int*)(0x42420604UL))\r
+#define bFM3_MFT1_FRT_TCSA0_CLK2               *((volatile unsigned int*)(0x42420608UL))\r
+#define bFM3_MFT1_FRT_TCSA0_CLK3               *((volatile unsigned int*)(0x4242060CUL))\r
+#define bFM3_MFT1_FRT_TCSA0_SCLR               *((volatile unsigned int*)(0x42420610UL))\r
+#define bFM3_MFT1_FRT_TCSA0_MODE               *((volatile unsigned int*)(0x42420614UL))\r
+#define bFM3_MFT1_FRT_TCSA0_STOP               *((volatile unsigned int*)(0x42420618UL))\r
+#define bFM3_MFT1_FRT_TCSA0_BFE                *((volatile unsigned int*)(0x4242061CUL))\r
+#define bFM3_MFT1_FRT_TCSA0_ICRE               *((volatile unsigned int*)(0x42420620UL))\r
+#define bFM3_MFT1_FRT_TCSA0_ICLR               *((volatile unsigned int*)(0x42420624UL))\r
+#define bFM3_MFT1_FRT_TCSA0_IRQZE              *((volatile unsigned int*)(0x42420634UL))\r
+#define bFM3_MFT1_FRT_TCSA0_IRQZF              *((volatile unsigned int*)(0x42420638UL))\r
+#define bFM3_MFT1_FRT_TCSA0_ECKE               *((volatile unsigned int*)(0x4242063CUL))\r
+#define bFM3_MFT1_FRT_TCSB0_AD0E               *((volatile unsigned int*)(0x42420680UL))\r
+#define bFM3_MFT1_FRT_TCSB0_AD1E               *((volatile unsigned int*)(0x42420684UL))\r
+#define bFM3_MFT1_FRT_TCSB0_AD2E               *((volatile unsigned int*)(0x42420688UL))\r
+#define bFM3_MFT1_FRT_TCSA1_CLK0               *((volatile unsigned int*)(0x42420800UL))\r
+#define bFM3_MFT1_FRT_TCSA1_CLK1               *((volatile unsigned int*)(0x42420804UL))\r
+#define bFM3_MFT1_FRT_TCSA1_CLK2               *((volatile unsigned int*)(0x42420808UL))\r
+#define bFM3_MFT1_FRT_TCSA1_CLK3               *((volatile unsigned int*)(0x4242080CUL))\r
+#define bFM3_MFT1_FRT_TCSA1_SCLR               *((volatile unsigned int*)(0x42420810UL))\r
+#define bFM3_MFT1_FRT_TCSA1_MODE               *((volatile unsigned int*)(0x42420814UL))\r
+#define bFM3_MFT1_FRT_TCSA1_STOP               *((volatile unsigned int*)(0x42420818UL))\r
+#define bFM3_MFT1_FRT_TCSA1_BFE                *((volatile unsigned int*)(0x4242081CUL))\r
+#define bFM3_MFT1_FRT_TCSA1_ICRE               *((volatile unsigned int*)(0x42420820UL))\r
+#define bFM3_MFT1_FRT_TCSA1_ICLR               *((volatile unsigned int*)(0x42420824UL))\r
+#define bFM3_MFT1_FRT_TCSA1_IRQZE              *((volatile unsigned int*)(0x42420834UL))\r
+#define bFM3_MFT1_FRT_TCSA1_IRQZF              *((volatile unsigned int*)(0x42420838UL))\r
+#define bFM3_MFT1_FRT_TCSA1_ECKE               *((volatile unsigned int*)(0x4242083CUL))\r
+#define bFM3_MFT1_FRT_TCSB1_AD0E               *((volatile unsigned int*)(0x42420880UL))\r
+#define bFM3_MFT1_FRT_TCSB1_AD1E               *((volatile unsigned int*)(0x42420884UL))\r
+#define bFM3_MFT1_FRT_TCSB1_AD2E               *((volatile unsigned int*)(0x42420888UL))\r
+#define bFM3_MFT1_FRT_TCSA2_CLK0               *((volatile unsigned int*)(0x42420A00UL))\r
+#define bFM3_MFT1_FRT_TCSA2_CLK1               *((volatile unsigned int*)(0x42420A04UL))\r
+#define bFM3_MFT1_FRT_TCSA2_CLK2               *((volatile unsigned int*)(0x42420A08UL))\r
+#define bFM3_MFT1_FRT_TCSA2_CLK3               *((volatile unsigned int*)(0x42420A0CUL))\r
+#define bFM3_MFT1_FRT_TCSA2_SCLR               *((volatile unsigned int*)(0x42420A10UL))\r
+#define bFM3_MFT1_FRT_TCSA2_MODE               *((volatile unsigned int*)(0x42420A14UL))\r
+#define bFM3_MFT1_FRT_TCSA2_STOP               *((volatile unsigned int*)(0x42420A18UL))\r
+#define bFM3_MFT1_FRT_TCSA2_BFE                *((volatile unsigned int*)(0x42420A1CUL))\r
+#define bFM3_MFT1_FRT_TCSA2_ICRE               *((volatile unsigned int*)(0x42420A20UL))\r
+#define bFM3_MFT1_FRT_TCSA2_ICLR               *((volatile unsigned int*)(0x42420A24UL))\r
+#define bFM3_MFT1_FRT_TCSA2_IRQZE              *((volatile unsigned int*)(0x42420A34UL))\r
+#define bFM3_MFT1_FRT_TCSA2_IRQZF              *((volatile unsigned int*)(0x42420A38UL))\r
+#define bFM3_MFT1_FRT_TCSA2_ECKE               *((volatile unsigned int*)(0x42420A3CUL))\r
+#define bFM3_MFT1_FRT_TCSB2_AD0E               *((volatile unsigned int*)(0x42420A80UL))\r
+#define bFM3_MFT1_FRT_TCSB2_AD1E               *((volatile unsigned int*)(0x42420A84UL))\r
+#define bFM3_MFT1_FRT_TCSB2_AD2E               *((volatile unsigned int*)(0x42420A88UL))\r
+\r
+/* Multifunction Timer unit 1 Output Compare Unit registers */\r
+#define bFM3_MFT1_OCU_OCSA10_CST0              *((volatile unsigned int*)(0x42420300UL))\r
+#define bFM3_MFT1_OCU_OCSA10_CST1              *((volatile unsigned int*)(0x42420304UL))\r
+#define bFM3_MFT1_OCU_OCSA10_BDIS0             *((volatile unsigned int*)(0x42420308UL))\r
+#define bFM3_MFT1_OCU_OCSA10_BDIS1             *((volatile unsigned int*)(0x4242030CUL))\r
+#define bFM3_MFT1_OCU_OCSA10_IOE0              *((volatile unsigned int*)(0x42420310UL))\r
+#define bFM3_MFT1_OCU_OCSA10_IOE1              *((volatile unsigned int*)(0x42420314UL))\r
+#define bFM3_MFT1_OCU_OCSA10_IOP0              *((volatile unsigned int*)(0x42420318UL))\r
+#define bFM3_MFT1_OCU_OCSA10_IOP1              *((volatile unsigned int*)(0x4242031CUL))\r
+#define bFM3_MFT1_OCU_OCSB10_OTD0              *((volatile unsigned int*)(0x42420320UL))\r
+#define bFM3_MFT1_OCU_OCSB10_OTD1              *((volatile unsigned int*)(0x42420324UL))\r
+#define bFM3_MFT1_OCU_OCSB10_CMOD              *((volatile unsigned int*)(0x42420330UL))\r
+#define bFM3_MFT1_OCU_OCSB10_BTS0              *((volatile unsigned int*)(0x42420334UL))\r
+#define bFM3_MFT1_OCU_OCSB10_BTS1              *((volatile unsigned int*)(0x42420338UL))\r
+#define bFM3_MFT1_OCU_OCSA32_CST2              *((volatile unsigned int*)(0x42420380UL))\r
+#define bFM3_MFT1_OCU_OCSA32_CST3              *((volatile unsigned int*)(0x42420384UL))\r
+#define bFM3_MFT1_OCU_OCSA32_BDIS2             *((volatile unsigned int*)(0x42420388UL))\r
+#define bFM3_MFT1_OCU_OCSA32_BDIS3             *((volatile unsigned int*)(0x4242038CUL))\r
+#define bFM3_MFT1_OCU_OCSA32_IOE2              *((volatile unsigned int*)(0x42420390UL))\r
+#define bFM3_MFT1_OCU_OCSA32_IOE3              *((volatile unsigned int*)(0x42420394UL))\r
+#define bFM3_MFT1_OCU_OCSA32_IOP2              *((volatile unsigned int*)(0x42420398UL))\r
+#define bFM3_MFT1_OCU_OCSA32_IOP3              *((volatile unsigned int*)(0x4242039CUL))\r
+#define bFM3_MFT1_OCU_OCSB32_OTD2              *((volatile unsigned int*)(0x424203A0UL))\r
+#define bFM3_MFT1_OCU_OCSB32_OTD3              *((volatile unsigned int*)(0x424203A4UL))\r
+#define bFM3_MFT1_OCU_OCSB32_CMOD              *((volatile unsigned int*)(0x424203B0UL))\r
+#define bFM3_MFT1_OCU_OCSB32_BTS2              *((volatile unsigned int*)(0x424203B4UL))\r
+#define bFM3_MFT1_OCU_OCSB32_BTS3              *((volatile unsigned int*)(0x424203B8UL))\r
+#define bFM3_MFT1_OCU_OCSA54_CST4              *((volatile unsigned int*)(0x42420400UL))\r
+#define bFM3_MFT1_OCU_OCSA54_CST5              *((volatile unsigned int*)(0x42420404UL))\r
+#define bFM3_MFT1_OCU_OCSA54_BDIS4             *((volatile unsigned int*)(0x42420408UL))\r
+#define bFM3_MFT1_OCU_OCSA54_BDIS5             *((volatile unsigned int*)(0x4242040CUL))\r
+#define bFM3_MFT1_OCU_OCSA54_IOE4              *((volatile unsigned int*)(0x42420410UL))\r
+#define bFM3_MFT1_OCU_OCSA54_IOE5              *((volatile unsigned int*)(0x42420414UL))\r
+#define bFM3_MFT1_OCU_OCSA54_IOP4              *((volatile unsigned int*)(0x42420418UL))\r
+#define bFM3_MFT1_OCU_OCSA54_IOP5              *((volatile unsigned int*)(0x4242041CUL))\r
+#define bFM3_MFT1_OCU_OCSB54_OTD4              *((volatile unsigned int*)(0x42420420UL))\r
+#define bFM3_MFT1_OCU_OCSB54_OTD5              *((volatile unsigned int*)(0x42420424UL))\r
+#define bFM3_MFT1_OCU_OCSB54_CMOD              *((volatile unsigned int*)(0x42420430UL))\r
+#define bFM3_MFT1_OCU_OCSB54_BTS4              *((volatile unsigned int*)(0x42420434UL))\r
+#define bFM3_MFT1_OCU_OCSB54_BTS5              *((volatile unsigned int*)(0x42420438UL))\r
+#define bFM3_MFT1_OCU_OCSC_MOD0                *((volatile unsigned int*)(0x424204A0UL))\r
+#define bFM3_MFT1_OCU_OCSC_MOD1                *((volatile unsigned int*)(0x424204A4UL))\r
+#define bFM3_MFT1_OCU_OCSC_MOD2                *((volatile unsigned int*)(0x424204A8UL))\r
+#define bFM3_MFT1_OCU_OCSC_MOD3                *((volatile unsigned int*)(0x424204ACUL))\r
+#define bFM3_MFT1_OCU_OCSC_MOD4                *((volatile unsigned int*)(0x424204B0UL))\r
+#define bFM3_MFT1_OCU_OCSC_MOD5                *((volatile unsigned int*)(0x424204B4UL))\r
+#define bFM3_MFT1_OCU_OCFS10_FSO00             *((volatile unsigned int*)(0x42420B00UL))\r
+#define bFM3_MFT1_OCU_OCFS10_FSO01             *((volatile unsigned int*)(0x42420B04UL))\r
+#define bFM3_MFT1_OCU_OCFS10_FSO02             *((volatile unsigned int*)(0x42420B08UL))\r
+#define bFM3_MFT1_OCU_OCFS10_FSO03             *((volatile unsigned int*)(0x42420B0CUL))\r
+#define bFM3_MFT1_OCU_OCFS10_FSO10             *((volatile unsigned int*)(0x42420B10UL))\r
+#define bFM3_MFT1_OCU_OCFS10_FSO11             *((volatile unsigned int*)(0x42420B14UL))\r
+#define bFM3_MFT1_OCU_OCFS10_FSO12             *((volatile unsigned int*)(0x42420B18UL))\r
+#define bFM3_MFT1_OCU_OCFS10_FSO13             *((volatile unsigned int*)(0x42420B1CUL))\r
+#define bFM3_MFT1_OCU_OCFS32_FSO20             *((volatile unsigned int*)(0x42420B20UL))\r
+#define bFM3_MFT1_OCU_OCFS32_FSO21             *((volatile unsigned int*)(0x42420B24UL))\r
+#define bFM3_MFT1_OCU_OCFS32_FSO22             *((volatile unsigned int*)(0x42420B28UL))\r
+#define bFM3_MFT1_OCU_OCFS32_FSO23             *((volatile unsigned int*)(0x42420B2CUL))\r
+#define bFM3_MFT1_OCU_OCFS32_FSO30             *((volatile unsigned int*)(0x42420B30UL))\r
+#define bFM3_MFT1_OCU_OCFS32_FSO31             *((volatile unsigned int*)(0x42420B34UL))\r
+#define bFM3_MFT1_OCU_OCFS32_FSO32             *((volatile unsigned int*)(0x42420B38UL))\r
+#define bFM3_MFT1_OCU_OCFS32_FSO33             *((volatile unsigned int*)(0x42420B3CUL))\r
+#define bFM3_MFT1_OCU_OCFS54_FSO40             *((volatile unsigned int*)(0x42420B80UL))\r
+#define bFM3_MFT1_OCU_OCFS54_FSO41             *((volatile unsigned int*)(0x42420B84UL))\r
+#define bFM3_MFT1_OCU_OCFS54_FSO42             *((volatile unsigned int*)(0x42420B88UL))\r
+#define bFM3_MFT1_OCU_OCFS54_FSO43             *((volatile unsigned int*)(0x42420B8CUL))\r
+#define bFM3_MFT1_OCU_OCFS54_FSO50             *((volatile unsigned int*)(0x42420B90UL))\r
+#define bFM3_MFT1_OCU_OCFS54_FSO51             *((volatile unsigned int*)(0x42420B94UL))\r
+#define bFM3_MFT1_OCU_OCFS54_FSO52             *((volatile unsigned int*)(0x42420B98UL))\r
+#define bFM3_MFT1_OCU_OCFS54_FSO53             *((volatile unsigned int*)(0x42420B9CUL))\r
+\r
+/* Multifunction Timer unit 1 Waveform Generator and Noise Canceler registers */\r
+#define bFM3_MFT1_WFG_WFSA10_DCK0              *((volatile unsigned int*)(0x42421180UL))\r
+#define bFM3_MFT1_WFG_WFSA10_DCK1              *((volatile unsigned int*)(0x42421184UL))\r
+#define bFM3_MFT1_WFG_WFSA10_DCK2              *((volatile unsigned int*)(0x42421188UL))\r
+#define bFM3_MFT1_WFG_WFSA10_TMD0              *((volatile unsigned int*)(0x4242118CUL))\r
+#define bFM3_MFT1_WFG_WFSA10_TMD1              *((volatile unsigned int*)(0x42421190UL))\r
+#define bFM3_MFT1_WFG_WFSA10_TMD2              *((volatile unsigned int*)(0x42421194UL))\r
+#define bFM3_MFT1_WFG_WFSA10_GTEN0             *((volatile unsigned int*)(0x42421198UL))\r
+#define bFM3_MFT1_WFG_WFSA10_GTEN1             *((volatile unsigned int*)(0x4242119CUL))\r
+#define bFM3_MFT1_WFG_WFSA10_PSEL0             *((volatile unsigned int*)(0x424211A0UL))\r
+#define bFM3_MFT1_WFG_WFSA10_PSEL1             *((volatile unsigned int*)(0x424211A4UL))\r
+#define bFM3_MFT1_WFG_WFSA10_PGEN0             *((volatile unsigned int*)(0x424211A8UL))\r
+#define bFM3_MFT1_WFG_WFSA10_PGEN1             *((volatile unsigned int*)(0x424211ACUL))\r
+#define bFM3_MFT1_WFG_WFSA10_DMOD              *((volatile unsigned int*)(0x424211B0UL))\r
+#define bFM3_MFT1_WFG_WFSA32_DCK0              *((volatile unsigned int*)(0x42421200UL))\r
+#define bFM3_MFT1_WFG_WFSA32_DCK1              *((volatile unsigned int*)(0x42421204UL))\r
+#define bFM3_MFT1_WFG_WFSA32_DCK2              *((volatile unsigned int*)(0x42421208UL))\r
+#define bFM3_MFT1_WFG_WFSA32_TMD0              *((volatile unsigned int*)(0x4242120CUL))\r
+#define bFM3_MFT1_WFG_WFSA32_TMD1              *((volatile unsigned int*)(0x42421210UL))\r
+#define bFM3_MFT1_WFG_WFSA32_TMD2              *((volatile unsigned int*)(0x42421214UL))\r
+#define bFM3_MFT1_WFG_WFSA32_GTEN0             *((volatile unsigned int*)(0x42421218UL))\r
+#define bFM3_MFT1_WFG_WFSA32_GTEN1             *((volatile unsigned int*)(0x4242121CUL))\r
+#define bFM3_MFT1_WFG_WFSA32_PSEL0             *((volatile unsigned int*)(0x42421220UL))\r
+#define bFM3_MFT1_WFG_WFSA32_PSEL1             *((volatile unsigned int*)(0x42421224UL))\r
+#define bFM3_MFT1_WFG_WFSA32_PGEN0             *((volatile unsigned int*)(0x42421228UL))\r
+#define bFM3_MFT1_WFG_WFSA32_PGEN1             *((volatile unsigned int*)(0x4242122CUL))\r
+#define bFM3_MFT1_WFG_WFSA32_DMOD              *((volatile unsigned int*)(0x42421230UL))\r
+#define bFM3_MFT1_WFG_WFSA54_DCK0              *((volatile unsigned int*)(0x42421280UL))\r
+#define bFM3_MFT1_WFG_WFSA54_DCK1              *((volatile unsigned int*)(0x42421284UL))\r
+#define bFM3_MFT1_WFG_WFSA54_DCK2              *((volatile unsigned int*)(0x42421288UL))\r
+#define bFM3_MFT1_WFG_WFSA54_TMD0              *((volatile unsigned int*)(0x4242128CUL))\r
+#define bFM3_MFT1_WFG_WFSA54_TMD1              *((volatile unsigned int*)(0x42421290UL))\r
+#define bFM3_MFT1_WFG_WFSA54_TMD2              *((volatile unsigned int*)(0x42421294UL))\r
+#define bFM3_MFT1_WFG_WFSA54_GTEN0             *((volatile unsigned int*)(0x42421298UL))\r
+#define bFM3_MFT1_WFG_WFSA54_GTEN1             *((volatile unsigned int*)(0x4242129CUL))\r
+#define bFM3_MFT1_WFG_WFSA54_PSEL0             *((volatile unsigned int*)(0x424212A0UL))\r
+#define bFM3_MFT1_WFG_WFSA54_PSEL1             *((volatile unsigned int*)(0x424212A4UL))\r
+#define bFM3_MFT1_WFG_WFSA54_PGEN0             *((volatile unsigned int*)(0x424212A8UL))\r
+#define bFM3_MFT1_WFG_WFSA54_PGEN1             *((volatile unsigned int*)(0x424212ACUL))\r
+#define bFM3_MFT1_WFG_WFSA54_DMOD              *((volatile unsigned int*)(0x424212B0UL))\r
+#define bFM3_MFT1_WFG_WFIR_DTIF                *((volatile unsigned int*)(0x42421300UL))\r
+#define bFM3_MFT1_WFG_WFIR_DTIC                *((volatile unsigned int*)(0x42421304UL))\r
+#define bFM3_MFT1_WFG_WFIR_TMIF10              *((volatile unsigned int*)(0x42421310UL))\r
+#define bFM3_MFT1_WFG_WFIR_TMIC10              *((volatile unsigned int*)(0x42421314UL))\r
+#define bFM3_MFT1_WFG_WFIR_TMIE10              *((volatile unsigned int*)(0x42421318UL))\r
+#define bFM3_MFT1_WFG_WFIR_TMIS10              *((volatile unsigned int*)(0x4242131CUL))\r
+#define bFM3_MFT1_WFG_WFIR_TMIF32              *((volatile unsigned int*)(0x42421320UL))\r
+#define bFM3_MFT1_WFG_WFIR_TMIC32              *((volatile unsigned int*)(0x42421324UL))\r
+#define bFM3_MFT1_WFG_WFIR_TMIE32              *((volatile unsigned int*)(0x42421328UL))\r
+#define bFM3_MFT1_WFG_WFIR_TMIS32              *((volatile unsigned int*)(0x4242132CUL))\r
+#define bFM3_MFT1_WFG_WFIR_TMIF54              *((volatile unsigned int*)(0x42421330UL))\r
+#define bFM3_MFT1_WFG_WFIR_TMIC54              *((volatile unsigned int*)(0x42421334UL))\r
+#define bFM3_MFT1_WFG_WFIR_TMIE54              *((volatile unsigned int*)(0x42421338UL))\r
+#define bFM3_MFT1_WFG_WFIR_TMIS54              *((volatile unsigned int*)(0x4242133CUL))\r
+#define bFM3_MFT1_WFG_NZCL_DTIE                *((volatile unsigned int*)(0x42421380UL))\r
+#define bFM3_MFT1_WFG_NZCL_NWS0                *((volatile unsigned int*)(0x42421384UL))\r
+#define bFM3_MFT1_WFG_NZCL_NWS1                *((volatile unsigned int*)(0x42421388UL))\r
+#define bFM3_MFT1_WFG_NZCL_NWS2                *((volatile unsigned int*)(0x4242138CUL))\r
+#define bFM3_MFT1_WFG_NZCL_SDTI                *((volatile unsigned int*)(0x42421390UL))\r
+\r
+/* Multifunction Timer unit 1 Input Capture Unit registers */\r
+#define bFM3_MFT1_ICU_ICFS10_FSI00             *((volatile unsigned int*)(0x42420C00UL))\r
+#define bFM3_MFT1_ICU_ICFS10_FSI01             *((volatile unsigned int*)(0x42420C04UL))\r
+#define bFM3_MFT1_ICU_ICFS10_FSI02             *((volatile unsigned int*)(0x42420C08UL))\r
+#define bFM3_MFT1_ICU_ICFS10_FSI03             *((volatile unsigned int*)(0x42420C0CUL))\r
+#define bFM3_MFT1_ICU_ICFS10_FSI10             *((volatile unsigned int*)(0x42420C10UL))\r
+#define bFM3_MFT1_ICU_ICFS10_FSI11             *((volatile unsigned int*)(0x42420C14UL))\r
+#define bFM3_MFT1_ICU_ICFS10_FSI12             *((volatile unsigned int*)(0x42420C18UL))\r
+#define bFM3_MFT1_ICU_ICFS10_FSI13             *((volatile unsigned int*)(0x42420C1CUL))\r
+#define bFM3_MFT1_ICU_ICFS32_FSI20             *((volatile unsigned int*)(0x42420C20UL))\r
+#define bFM3_MFT1_ICU_ICFS32_FSI21             *((volatile unsigned int*)(0x42420C24UL))\r
+#define bFM3_MFT1_ICU_ICFS32_FSI22             *((volatile unsigned int*)(0x42420C28UL))\r
+#define bFM3_MFT1_ICU_ICFS32_FSI23             *((volatile unsigned int*)(0x42420C2CUL))\r
+#define bFM3_MFT1_ICU_ICFS32_FSI30             *((volatile unsigned int*)(0x42420C30UL))\r
+#define bFM3_MFT1_ICU_ICFS32_FSI31             *((volatile unsigned int*)(0x42420C34UL))\r
+#define bFM3_MFT1_ICU_ICFS32_FSI32             *((volatile unsigned int*)(0x42420C38UL))\r
+#define bFM3_MFT1_ICU_ICFS32_FSI33             *((volatile unsigned int*)(0x42420C3CUL))\r
+#define bFM3_MFT1_ICU_ICSA10_EG00              *((volatile unsigned int*)(0x42420F00UL))\r
+#define bFM3_MFT1_ICU_ICSA10_EG01              *((volatile unsigned int*)(0x42420F04UL))\r
+#define bFM3_MFT1_ICU_ICSA10_EG10              *((volatile unsigned int*)(0x42420F08UL))\r
+#define bFM3_MFT1_ICU_ICSA10_EG11              *((volatile unsigned int*)(0x42420F0CUL))\r
+#define bFM3_MFT1_ICU_ICSA10_ICE0              *((volatile unsigned int*)(0x42420F10UL))\r
+#define bFM3_MFT1_ICU_ICSA10_ICE1              *((volatile unsigned int*)(0x42420F14UL))\r
+#define bFM3_MFT1_ICU_ICSA10_IPC0              *((volatile unsigned int*)(0x42420F18UL))\r
+#define bFM3_MFT1_ICU_ICSA10_IPC1              *((volatile unsigned int*)(0x42420F1CUL))\r
+#define bFM3_MFT1_ICU_ICSB10_IEI0              *((volatile unsigned int*)(0x42420F20UL))\r
+#define bFM3_MFT1_ICU_ICSB10_IEI1              *((volatile unsigned int*)(0x42420F24UL))\r
+#define bFM3_MFT1_ICU_ICSA32_EG20              *((volatile unsigned int*)(0x42420F80UL))\r
+#define bFM3_MFT1_ICU_ICSA32_EG21              *((volatile unsigned int*)(0x42420F84UL))\r
+#define bFM3_MFT1_ICU_ICSA32_EG30              *((volatile unsigned int*)(0x42420F88UL))\r
+#define bFM3_MFT1_ICU_ICSA32_EG31              *((volatile unsigned int*)(0x42420F8CUL))\r
+#define bFM3_MFT1_ICU_ICSA32_ICE2              *((volatile unsigned int*)(0x42420F90UL))\r
+#define bFM3_MFT1_ICU_ICSA32_ICE3              *((volatile unsigned int*)(0x42420F94UL))\r
+#define bFM3_MFT1_ICU_ICSA32_IPC2              *((volatile unsigned int*)(0x42420F98UL))\r
+#define bFM3_MFT1_ICU_ICSA32_IPC3              *((volatile unsigned int*)(0x42420F9CUL))\r
+#define bFM3_MFT1_ICU_ICSB32_IEI2              *((volatile unsigned int*)(0x42420FA0UL))\r
+#define bFM3_MFT1_ICU_ICSB32_IEI3              *((volatile unsigned int*)(0x42420FA4UL))\r
+\r
+/* Multifunction Timer unit 1 ADC Start Compare Unit registers */\r
+#define bFM3_MFT1_ADCMP_ACSB_BDIS0             *((volatile unsigned int*)(0x42421700UL))\r
+#define bFM3_MFT1_ADCMP_ACSB_BDIS1             *((volatile unsigned int*)(0x42421704UL))\r
+#define bFM3_MFT1_ADCMP_ACSB_BDIS2             *((volatile unsigned int*)(0x42421708UL))\r
+#define bFM3_MFT1_ADCMP_ACSB_BTS0              *((volatile unsigned int*)(0x42421710UL))\r
+#define bFM3_MFT1_ADCMP_ACSB_BTS1              *((volatile unsigned int*)(0x42421714UL))\r
+#define bFM3_MFT1_ADCMP_ACSB_BTS2              *((volatile unsigned int*)(0x42421718UL))\r
+#define bFM3_MFT1_ADCMP_ACSA_CE00              *((volatile unsigned int*)(0x42421780UL))\r
+#define bFM3_MFT1_ADCMP_ACSA_CE01              *((volatile unsigned int*)(0x42421784UL))\r
+#define bFM3_MFT1_ADCMP_ACSA_CE10              *((volatile unsigned int*)(0x42421788UL))\r
+#define bFM3_MFT1_ADCMP_ACSA_CE11              *((volatile unsigned int*)(0x4242178CUL))\r
+#define bFM3_MFT1_ADCMP_ACSA_CE20              *((volatile unsigned int*)(0x42421790UL))\r
+#define bFM3_MFT1_ADCMP_ACSA_CE21              *((volatile unsigned int*)(0x42421794UL))\r
+#define bFM3_MFT1_ADCMP_ACSA_SEL00             *((volatile unsigned int*)(0x424217A0UL))\r
+#define bFM3_MFT1_ADCMP_ACSA_SEL01             *((volatile unsigned int*)(0x424217A4UL))\r
+#define bFM3_MFT1_ADCMP_ACSA_SEL10             *((volatile unsigned int*)(0x424217A8UL))\r
+#define bFM3_MFT1_ADCMP_ACSA_SEL11             *((volatile unsigned int*)(0x424217ACUL))\r
+#define bFM3_MFT1_ADCMP_ACSA_SEL20             *((volatile unsigned int*)(0x424217B0UL))\r
+#define bFM3_MFT1_ADCMP_ACSA_SEL21             *((volatile unsigned int*)(0x424217B4UL))\r
+#define bFM3_MFT1_ADCMP_ATSA_AD0S0             *((volatile unsigned int*)(0x42421800UL))\r
+#define bFM3_MFT1_ADCMP_ATSA_AD0S1             *((volatile unsigned int*)(0x42421804UL))\r
+#define bFM3_MFT1_ADCMP_ATSA_AD1S0             *((volatile unsigned int*)(0x42421808UL))\r
+#define bFM3_MFT1_ADCMP_ATSA_AD1S1             *((volatile unsigned int*)(0x4242180CUL))\r
+#define bFM3_MFT1_ADCMP_ATSA_AD2S0             *((volatile unsigned int*)(0x42421810UL))\r
+#define bFM3_MFT1_ADCMP_ATSA_AD2S1             *((volatile unsigned int*)(0x42421814UL))\r
+#define bFM3_MFT1_ADCMP_ATSA_AD0P0             *((volatile unsigned int*)(0x42421820UL))\r
+#define bFM3_MFT1_ADCMP_ATSA_AD0P1             *((volatile unsigned int*)(0x42421824UL))\r
+#define bFM3_MFT1_ADCMP_ATSA_AD1P0             *((volatile unsigned int*)(0x42421828UL))\r
+#define bFM3_MFT1_ADCMP_ATSA_AD1P1             *((volatile unsigned int*)(0x4242182CUL))\r
+#define bFM3_MFT1_ADCMP_ATSA_AD2P0             *((volatile unsigned int*)(0x42421830UL))\r
+#define bFM3_MFT1_ADCMP_ATSA_AD2P1             *((volatile unsigned int*)(0x42421834UL))\r
+\r
+/* Multifunction Timer PPG registers */\r
+#define bFM3_MFT_PPG_TTCR0_STR0                *((volatile unsigned int*)(0x42480020UL))\r
+#define bFM3_MFT_PPG_TTCR0_MONI0               *((volatile unsigned int*)(0x42480024UL))\r
+#define bFM3_MFT_PPG_TTCR0_CS00                *((volatile unsigned int*)(0x42480028UL))\r
+#define bFM3_MFT_PPG_TTCR0_CS01                *((volatile unsigned int*)(0x4248002CUL))\r
+#define bFM3_MFT_PPG_TTCR0_TRG0O               *((volatile unsigned int*)(0x42480030UL))\r
+#define bFM3_MFT_PPG_TTCR0_TRG2O               *((volatile unsigned int*)(0x42480034UL))\r
+#define bFM3_MFT_PPG_TTCR0_TRG4O               *((volatile unsigned int*)(0x42480038UL))\r
+#define bFM3_MFT_PPG_TTCR0_TRG6O               *((volatile unsigned int*)(0x4248003CUL))\r
+#define bFM3_MFT_PPG_TTCR1_STR1                *((volatile unsigned int*)(0x42480420UL))\r
+#define bFM3_MFT_PPG_TTCR1_MONI1               *((volatile unsigned int*)(0x42480424UL))\r
+#define bFM3_MFT_PPG_TTCR1_CS10                *((volatile unsigned int*)(0x42480428UL))\r
+#define bFM3_MFT_PPG_TTCR1_CS11                *((volatile unsigned int*)(0x4248042CUL))\r
+#define bFM3_MFT_PPG_TTCR1_TRG1O               *((volatile unsigned int*)(0x42480430UL))\r
+#define bFM3_MFT_PPG_TTCR1_TRG3O               *((volatile unsigned int*)(0x42480434UL))\r
+#define bFM3_MFT_PPG_TTCR1_TRG5O               *((volatile unsigned int*)(0x42480438UL))\r
+#define bFM3_MFT_PPG_TTCR1_TRG7O               *((volatile unsigned int*)(0x4248043CUL))\r
+#define bFM3_MFT_PPG_TRG_PEN00                 *((volatile unsigned int*)(0x42482000UL))\r
+#define bFM3_MFT_PPG_TRG_PEN01                 *((volatile unsigned int*)(0x42482004UL))\r
+#define bFM3_MFT_PPG_TRG_PEN02                 *((volatile unsigned int*)(0x42482008UL))\r
+#define bFM3_MFT_PPG_TRG_PEN03                 *((volatile unsigned int*)(0x4248200CUL))\r
+#define bFM3_MFT_PPG_TRG_PEN04                 *((volatile unsigned int*)(0x42482010UL))\r
+#define bFM3_MFT_PPG_TRG_PEN05                 *((volatile unsigned int*)(0x42482014UL))\r
+#define bFM3_MFT_PPG_TRG_PEN06                 *((volatile unsigned int*)(0x42482018UL))\r
+#define bFM3_MFT_PPG_TRG_PEN07                 *((volatile unsigned int*)(0x4248201CUL))\r
+#define bFM3_MFT_PPG_TRG_PEN08                 *((volatile unsigned int*)(0x42482020UL))\r
+#define bFM3_MFT_PPG_TRG_PEN09                 *((volatile unsigned int*)(0x42482024UL))\r
+#define bFM3_MFT_PPG_TRG_PEN10                 *((volatile unsigned int*)(0x42482028UL))\r
+#define bFM3_MFT_PPG_TRG_PEN11                 *((volatile unsigned int*)(0x4248202CUL))\r
+#define bFM3_MFT_PPG_TRG_PEN12                 *((volatile unsigned int*)(0x42482030UL))\r
+#define bFM3_MFT_PPG_TRG_PEN13                 *((volatile unsigned int*)(0x42482034UL))\r
+#define bFM3_MFT_PPG_TRG_PEN14                 *((volatile unsigned int*)(0x42482038UL))\r
+#define bFM3_MFT_PPG_TRG_PEN15                 *((volatile unsigned int*)(0x4248203CUL))\r
+#define bFM3_MFT_PPG_REVC_REV00                *((volatile unsigned int*)(0x42482080UL))\r
+#define bFM3_MFT_PPG_REVC_REV01                *((volatile unsigned int*)(0x42482084UL))\r
+#define bFM3_MFT_PPG_REVC_REV02                *((volatile unsigned int*)(0x42482088UL))\r
+#define bFM3_MFT_PPG_REVC_REV03                *((volatile unsigned int*)(0x4248208CUL))\r
+#define bFM3_MFT_PPG_REVC_REV04                *((volatile unsigned int*)(0x42482090UL))\r
+#define bFM3_MFT_PPG_REVC_REV05                *((volatile unsigned int*)(0x42482094UL))\r
+#define bFM3_MFT_PPG_REVC_REV06                *((volatile unsigned int*)(0x42482098UL))\r
+#define bFM3_MFT_PPG_REVC_REV07                *((volatile unsigned int*)(0x4248209CUL))\r
+#define bFM3_MFT_PPG_REVC_REV08                *((volatile unsigned int*)(0x424820A0UL))\r
+#define bFM3_MFT_PPG_REVC_REV09                *((volatile unsigned int*)(0x424820A4UL))\r
+#define bFM3_MFT_PPG_REVC_REV10                *((volatile unsigned int*)(0x424820A8UL))\r
+#define bFM3_MFT_PPG_REVC_REV11                *((volatile unsigned int*)(0x424820ACUL))\r
+#define bFM3_MFT_PPG_REVC_REV12                *((volatile unsigned int*)(0x424820B0UL))\r
+#define bFM3_MFT_PPG_REVC_REV13                *((volatile unsigned int*)(0x424820B4UL))\r
+#define bFM3_MFT_PPG_REVC_REV14                *((volatile unsigned int*)(0x424820B8UL))\r
+#define bFM3_MFT_PPG_REVC_REV15                *((volatile unsigned int*)(0x424820BCUL))\r
+#define bFM3_MFT_PPG_PPGC1_TTRG                *((volatile unsigned int*)(0x42484000UL))\r
+#define bFM3_MFT_PPG_PPGC1_MD0                 *((volatile unsigned int*)(0x42484004UL))\r
+#define bFM3_MFT_PPG_PPGC1_MD1                 *((volatile unsigned int*)(0x42484008UL))\r
+#define bFM3_MFT_PPG_PPGC1_PCS0                *((volatile unsigned int*)(0x4248400CUL))\r
+#define bFM3_MFT_PPG_PPGC1_PCS1                *((volatile unsigned int*)(0x42484010UL))\r
+#define bFM3_MFT_PPG_PPGC1_INTM                *((volatile unsigned int*)(0x42484014UL))\r
+#define bFM3_MFT_PPG_PPGC1_PUF                 *((volatile unsigned int*)(0x42484018UL))\r
+#define bFM3_MFT_PPG_PPGC1_PIE                 *((volatile unsigned int*)(0x4248401CUL))\r
+#define bFM3_MFT_PPG_PPGC0_TTRG                *((volatile unsigned int*)(0x42484020UL))\r
+#define bFM3_MFT_PPG_PPGC0_MD0                 *((volatile unsigned int*)(0x42484024UL))\r
+#define bFM3_MFT_PPG_PPGC0_MD1                 *((volatile unsigned int*)(0x42484028UL))\r
+#define bFM3_MFT_PPG_PPGC0_PCS0                *((volatile unsigned int*)(0x4248402CUL))\r
+#define bFM3_MFT_PPG_PPGC0_PCS1                *((volatile unsigned int*)(0x42484030UL))\r
+#define bFM3_MFT_PPG_PPGC0_INTM                *((volatile unsigned int*)(0x42484034UL))\r
+#define bFM3_MFT_PPG_PPGC0_PUF                 *((volatile unsigned int*)(0x42484038UL))\r
+#define bFM3_MFT_PPG_PPGC0_PIE                 *((volatile unsigned int*)(0x4248403CUL))\r
+#define bFM3_MFT_PPG_PPGC3_TTRG                *((volatile unsigned int*)(0x42484080UL))\r
+#define bFM3_MFT_PPG_PPGC3_MD0                 *((volatile unsigned int*)(0x42484084UL))\r
+#define bFM3_MFT_PPG_PPGC3_MD1                 *((volatile unsigned int*)(0x42484088UL))\r
+#define bFM3_MFT_PPG_PPGC3_PCS0                *((volatile unsigned int*)(0x4248408CUL))\r
+#define bFM3_MFT_PPG_PPGC3_PCS1                *((volatile unsigned int*)(0x42484090UL))\r
+#define bFM3_MFT_PPG_PPGC3_INTM                *((volatile unsigned int*)(0x42484094UL))\r
+#define bFM3_MFT_PPG_PPGC3_PUF                 *((volatile unsigned int*)(0x42484098UL))\r
+#define bFM3_MFT_PPG_PPGC3_PIE                 *((volatile unsigned int*)(0x4248409CUL))\r
+#define bFM3_MFT_PPG_PPGC2_TTRG                *((volatile unsigned int*)(0x424840A0UL))\r
+#define bFM3_MFT_PPG_PPGC2_MD0                 *((volatile unsigned int*)(0x424840A4UL))\r
+#define bFM3_MFT_PPG_PPGC2_MD1                 *((volatile unsigned int*)(0x424840A8UL))\r
+#define bFM3_MFT_PPG_PPGC2_PCS0                *((volatile unsigned int*)(0x424840ACUL))\r
+#define bFM3_MFT_PPG_PPGC2_PCS1                *((volatile unsigned int*)(0x424840B0UL))\r
+#define bFM3_MFT_PPG_PPGC2_INTM                *((volatile unsigned int*)(0x424840B4UL))\r
+#define bFM3_MFT_PPG_PPGC2_PUF                 *((volatile unsigned int*)(0x424840B8UL))\r
+#define bFM3_MFT_PPG_PPGC2_PIE                 *((volatile unsigned int*)(0x424840BCUL))\r
+#define bFM3_MFT_PPG_GATEC0_EDGE0              *((volatile unsigned int*)(0x42484300UL))\r
+#define bFM3_MFT_PPG_GATEC0_STRG0              *((volatile unsigned int*)(0x42484304UL))\r
+#define bFM3_MFT_PPG_GATEC0_EDGE2              *((volatile unsigned int*)(0x42484310UL))\r
+#define bFM3_MFT_PPG_GATEC0_STRG2              *((volatile unsigned int*)(0x42484314UL))\r
+#define bFM3_MFT_PPG_PPGC5_TTRG                *((volatile unsigned int*)(0x42484800UL))\r
+#define bFM3_MFT_PPG_PPGC5_MD0                 *((volatile unsigned int*)(0x42484804UL))\r
+#define bFM3_MFT_PPG_PPGC5_MD1                 *((volatile unsigned int*)(0x42484808UL))\r
+#define bFM3_MFT_PPG_PPGC5_PCS0                *((volatile unsigned int*)(0x4248480CUL))\r
+#define bFM3_MFT_PPG_PPGC5_PCS1                *((volatile unsigned int*)(0x42484810UL))\r
+#define bFM3_MFT_PPG_PPGC5_INTM                *((volatile unsigned int*)(0x42484814UL))\r
+#define bFM3_MFT_PPG_PPGC5_PUF                 *((volatile unsigned int*)(0x42484818UL))\r
+#define bFM3_MFT_PPG_PPGC5_PIE                 *((volatile unsigned int*)(0x4248481CUL))\r
+#define bFM3_MFT_PPG_PPGC4_TTRG                *((volatile unsigned int*)(0x42484820UL))\r
+#define bFM3_MFT_PPG_PPGC4_MD0                 *((volatile unsigned int*)(0x42484824UL))\r
+#define bFM3_MFT_PPG_PPGC4_MD1                 *((volatile unsigned int*)(0x42484828UL))\r
+#define bFM3_MFT_PPG_PPGC4_PCS0                *((volatile unsigned int*)(0x4248482CUL))\r
+#define bFM3_MFT_PPG_PPGC4_PCS1                *((volatile unsigned int*)(0x42484830UL))\r
+#define bFM3_MFT_PPG_PPGC4_INTM                *((volatile unsigned int*)(0x42484834UL))\r
+#define bFM3_MFT_PPG_PPGC4_PUF                 *((volatile unsigned int*)(0x42484838UL))\r
+#define bFM3_MFT_PPG_PPGC4_PIE                 *((volatile unsigned int*)(0x4248483CUL))\r
+#define bFM3_MFT_PPG_PPGC7_TTRG                *((volatile unsigned int*)(0x42484880UL))\r
+#define bFM3_MFT_PPG_PPGC7_MD0                 *((volatile unsigned int*)(0x42484884UL))\r
+#define bFM3_MFT_PPG_PPGC7_MD1                 *((volatile unsigned int*)(0x42484888UL))\r
+#define bFM3_MFT_PPG_PPGC7_PCS0                *((volatile unsigned int*)(0x4248488CUL))\r
+#define bFM3_MFT_PPG_PPGC7_PCS1                *((volatile unsigned int*)(0x42484890UL))\r
+#define bFM3_MFT_PPG_PPGC7_INTM                *((volatile unsigned int*)(0x42484894UL))\r
+#define bFM3_MFT_PPG_PPGC7_PUF                 *((volatile unsigned int*)(0x42484898UL))\r
+#define bFM3_MFT_PPG_PPGC7_PIE                 *((volatile unsigned int*)(0x4248489CUL))\r
+#define bFM3_MFT_PPG_PPGC6_TTRG                *((volatile unsigned int*)(0x424848A0UL))\r
+#define bFM3_MFT_PPG_PPGC6_MD0                 *((volatile unsigned int*)(0x424848A4UL))\r
+#define bFM3_MFT_PPG_PPGC6_MD1                 *((volatile unsigned int*)(0x424848A8UL))\r
+#define bFM3_MFT_PPG_PPGC6_PCS0                *((volatile unsigned int*)(0x424848ACUL))\r
+#define bFM3_MFT_PPG_PPGC6_PCS1                *((volatile unsigned int*)(0x424848B0UL))\r
+#define bFM3_MFT_PPG_PPGC6_INTM                *((volatile unsigned int*)(0x424848B4UL))\r
+#define bFM3_MFT_PPG_PPGC6_PUF                 *((volatile unsigned int*)(0x424848B8UL))\r
+#define bFM3_MFT_PPG_PPGC6_PIE                 *((volatile unsigned int*)(0x424848BCUL))\r
+#define bFM3_MFT_PPG_GATEC4_EDGE4              *((volatile unsigned int*)(0x42484B00UL))\r
+#define bFM3_MFT_PPG_GATEC4_STRG4              *((volatile unsigned int*)(0x42484B04UL))\r
+#define bFM3_MFT_PPG_GATEC4_EDGE6              *((volatile unsigned int*)(0x42484B10UL))\r
+#define bFM3_MFT_PPG_GATEC4_STRG6              *((volatile unsigned int*)(0x42484B14UL))\r
+#define bFM3_MFT_PPG_PPGC9_TTRG                *((volatile unsigned int*)(0x42485000UL))\r
+#define bFM3_MFT_PPG_PPGC9_MD0                 *((volatile unsigned int*)(0x42485004UL))\r
+#define bFM3_MFT_PPG_PPGC9_MD1                 *((volatile unsigned int*)(0x42485008UL))\r
+#define bFM3_MFT_PPG_PPGC9_PCS0                *((volatile unsigned int*)(0x4248500CUL))\r
+#define bFM3_MFT_PPG_PPGC9_PCS1                *((volatile unsigned int*)(0x42485010UL))\r
+#define bFM3_MFT_PPG_PPGC9_INTM                *((volatile unsigned int*)(0x42485014UL))\r
+#define bFM3_MFT_PPG_PPGC9_PUF                 *((volatile unsigned int*)(0x42485018UL))\r
+#define bFM3_MFT_PPG_PPGC9_PIE                 *((volatile unsigned int*)(0x4248501CUL))\r
+#define bFM3_MFT_PPG_PPGC8_TTRG                *((volatile unsigned int*)(0x42485020UL))\r
+#define bFM3_MFT_PPG_PPGC8_MD0                 *((volatile unsigned int*)(0x42485024UL))\r
+#define bFM3_MFT_PPG_PPGC8_MD1                 *((volatile unsigned int*)(0x42485028UL))\r
+#define bFM3_MFT_PPG_PPGC8_PCS0                *((volatile unsigned int*)(0x4248502CUL))\r
+#define bFM3_MFT_PPG_PPGC8_PCS1                *((volatile unsigned int*)(0x42485030UL))\r
+#define bFM3_MFT_PPG_PPGC8_INTM                *((volatile unsigned int*)(0x42485034UL))\r
+#define bFM3_MFT_PPG_PPGC8_PUF                 *((volatile unsigned int*)(0x42485038UL))\r
+#define bFM3_MFT_PPG_PPGC8_PIE                 *((volatile unsigned int*)(0x4248503CUL))\r
+#define bFM3_MFT_PPG_PPGC11_TTRG               *((volatile unsigned int*)(0x42485080UL))\r
+#define bFM3_MFT_PPG_PPGC11_MD0                *((volatile unsigned int*)(0x42485084UL))\r
+#define bFM3_MFT_PPG_PPGC11_MD1                *((volatile unsigned int*)(0x42485088UL))\r
+#define bFM3_MFT_PPG_PPGC11_PCS0               *((volatile unsigned int*)(0x4248508CUL))\r
+#define bFM3_MFT_PPG_PPGC11_PCS1               *((volatile unsigned int*)(0x42485090UL))\r
+#define bFM3_MFT_PPG_PPGC11_INTM               *((volatile unsigned int*)(0x42485094UL))\r
+#define bFM3_MFT_PPG_PPGC11_PUF                *((volatile unsigned int*)(0x42485098UL))\r
+#define bFM3_MFT_PPG_PPGC11_PIE                *((volatile unsigned int*)(0x4248509CUL))\r
+#define bFM3_MFT_PPG_PPGC10_TTRG               *((volatile unsigned int*)(0x424850A0UL))\r
+#define bFM3_MFT_PPG_PPGC10_MD0                *((volatile unsigned int*)(0x424850A4UL))\r
+#define bFM3_MFT_PPG_PPGC10_MD1                *((volatile unsigned int*)(0x424850A8UL))\r
+#define bFM3_MFT_PPG_PPGC10_PCS0               *((volatile unsigned int*)(0x424850ACUL))\r
+#define bFM3_MFT_PPG_PPGC10_PCS1               *((volatile unsigned int*)(0x424850B0UL))\r
+#define bFM3_MFT_PPG_PPGC10_INTM               *((volatile unsigned int*)(0x424850B4UL))\r
+#define bFM3_MFT_PPG_PPGC10_PUF                *((volatile unsigned int*)(0x424850B8UL))\r
+#define bFM3_MFT_PPG_PPGC10_PIE                *((volatile unsigned int*)(0x424850BCUL))\r
+#define bFM3_MFT_PPG_GATEC8_EDGE8              *((volatile unsigned int*)(0x42485300UL))\r
+#define bFM3_MFT_PPG_GATEC8_STRG8              *((volatile unsigned int*)(0x42485304UL))\r
+#define bFM3_MFT_PPG_GATEC8_EDGE10             *((volatile unsigned int*)(0x42485310UL))\r
+#define bFM3_MFT_PPG_GATEC8_STRG10             *((volatile unsigned int*)(0x42485314UL))\r
+#define bFM3_MFT_PPG_PPGC13_TTRG               *((volatile unsigned int*)(0x42485800UL))\r
+#define bFM3_MFT_PPG_PPGC13_MD0                *((volatile unsigned int*)(0x42485804UL))\r
+#define bFM3_MFT_PPG_PPGC13_MD1                *((volatile unsigned int*)(0x42485808UL))\r
+#define bFM3_MFT_PPG_PPGC13_PCS0               *((volatile unsigned int*)(0x4248580CUL))\r
+#define bFM3_MFT_PPG_PPGC13_PCS1               *((volatile unsigned int*)(0x42485810UL))\r
+#define bFM3_MFT_PPG_PPGC13_INTM               *((volatile unsigned int*)(0x42485814UL))\r
+#define bFM3_MFT_PPG_PPGC13_PUF                *((volatile unsigned int*)(0x42485818UL))\r
+#define bFM3_MFT_PPG_PPGC13_PIE                *((volatile unsigned int*)(0x4248581CUL))\r
+#define bFM3_MFT_PPG_PPGC12_TTRG               *((volatile unsigned int*)(0x42485820UL))\r
+#define bFM3_MFT_PPG_PPGC12_MD0                *((volatile unsigned int*)(0x42485824UL))\r
+#define bFM3_MFT_PPG_PPGC12_MD1                *((volatile unsigned int*)(0x42485828UL))\r
+#define bFM3_MFT_PPG_PPGC12_PCS0               *((volatile unsigned int*)(0x4248582CUL))\r
+#define bFM3_MFT_PPG_PPGC12_PCS1               *((volatile unsigned int*)(0x42485830UL))\r
+#define bFM3_MFT_PPG_PPGC12_INTM               *((volatile unsigned int*)(0x42485834UL))\r
+#define bFM3_MFT_PPG_PPGC12_PUF                *((volatile unsigned int*)(0x42485838UL))\r
+#define bFM3_MFT_PPG_PPGC12_PIE                *((volatile unsigned int*)(0x4248583CUL))\r
+#define bFM3_MFT_PPG_PPGC15_TTRG               *((volatile unsigned int*)(0x42485880UL))\r
+#define bFM3_MFT_PPG_PPGC15_MD0                *((volatile unsigned int*)(0x42485884UL))\r
+#define bFM3_MFT_PPG_PPGC15_MD1                *((volatile unsigned int*)(0x42485888UL))\r
+#define bFM3_MFT_PPG_PPGC15_PCS0               *((volatile unsigned int*)(0x4248588CUL))\r
+#define bFM3_MFT_PPG_PPGC15_PCS1               *((volatile unsigned int*)(0x42485890UL))\r
+#define bFM3_MFT_PPG_PPGC15_INTM               *((volatile unsigned int*)(0x42485894UL))\r
+#define bFM3_MFT_PPG_PPGC15_PUF                *((volatile unsigned int*)(0x42485898UL))\r
+#define bFM3_MFT_PPG_PPGC15_PIE                *((volatile unsigned int*)(0x4248589CUL))\r
+#define bFM3_MFT_PPG_PPGC14_TTRG               *((volatile unsigned int*)(0x424858A0UL))\r
+#define bFM3_MFT_PPG_PPGC14_MD0                *((volatile unsigned int*)(0x424858A4UL))\r
+#define bFM3_MFT_PPG_PPGC14_MD1                *((volatile unsigned int*)(0x424858A8UL))\r
+#define bFM3_MFT_PPG_PPGC14_PCS0               *((volatile unsigned int*)(0x424858ACUL))\r
+#define bFM3_MFT_PPG_PPGC14_PCS1               *((volatile unsigned int*)(0x424858B0UL))\r
+#define bFM3_MFT_PPG_PPGC14_INTM               *((volatile unsigned int*)(0x424858B4UL))\r
+#define bFM3_MFT_PPG_PPGC14_PUF                *((volatile unsigned int*)(0x424858B8UL))\r
+#define bFM3_MFT_PPG_PPGC14_PIE                *((volatile unsigned int*)(0x424858BCUL))\r
+#define bFM3_MFT_PPG_GATEC12_EDGE12            *((volatile unsigned int*)(0x42485B00UL))\r
+#define bFM3_MFT_PPG_GATEC12_STRG12            *((volatile unsigned int*)(0x42485B04UL))\r
+#define bFM3_MFT_PPG_GATEC12_EDGE14            *((volatile unsigned int*)(0x42485B10UL))\r
+#define bFM3_MFT_PPG_GATEC12_STRG14            *((volatile unsigned int*)(0x42485B14UL))\r
+\r
+/* Base Timer 0 PPG registers */\r
+#define bFM3_BT0_PPG_TMCR_STRG                 *((volatile unsigned int*)(0x424A0180UL))\r
+#define bFM3_BT0_PPG_TMCR_CTEN                 *((volatile unsigned int*)(0x424A0184UL))\r
+#define bFM3_BT0_PPG_TMCR_MDSE                 *((volatile unsigned int*)(0x424A0188UL))\r
+#define bFM3_BT0_PPG_TMCR_OSEL                 *((volatile unsigned int*)(0x424A018CUL))\r
+#define bFM3_BT0_PPG_TMCR_FMD0                 *((volatile unsigned int*)(0x424A0190UL))\r
+#define bFM3_BT0_PPG_TMCR_FMD1                 *((volatile unsigned int*)(0x424A0194UL))\r
+#define bFM3_BT0_PPG_TMCR_FMD2                 *((volatile unsigned int*)(0x424A0198UL))\r
+#define bFM3_BT0_PPG_TMCR_EGS0                 *((volatile unsigned int*)(0x424A01A0UL))\r
+#define bFM3_BT0_PPG_TMCR_EGS1                 *((volatile unsigned int*)(0x424A01A4UL))\r
+#define bFM3_BT0_PPG_TMCR_PMSK                 *((volatile unsigned int*)(0x424A01A8UL))\r
+#define bFM3_BT0_PPG_TMCR_RTGEN                *((volatile unsigned int*)(0x424A01ACUL))\r
+#define bFM3_BT0_PPG_TMCR_CKS0                 *((volatile unsigned int*)(0x424A01B0UL))\r
+#define bFM3_BT0_PPG_TMCR_CKS1                 *((volatile unsigned int*)(0x424A01B4UL))\r
+#define bFM3_BT0_PPG_TMCR_CKS2                 *((volatile unsigned int*)(0x424A01B8UL))\r
+#define bFM3_BT0_PPG_STC_UDIR                  *((volatile unsigned int*)(0x424A0200UL))\r
+#define bFM3_BT0_PPG_STC_TGIR                  *((volatile unsigned int*)(0x424A0208UL))\r
+#define bFM3_BT0_PPG_STC_UDIE                  *((volatile unsigned int*)(0x424A0210UL))\r
+#define bFM3_BT0_PPG_STC_TGIE                  *((volatile unsigned int*)(0x424A0218UL))\r
+#define bFM3_BT0_PPG_TMCR2_CKS3                *((volatile unsigned int*)(0x424A0220UL))\r
+\r
+/* Base Timer 0 PWM registers */\r
+#define bFM3_BT0_PWM_TMCR_STRG                 *((volatile unsigned int*)(0x424A0180UL))\r
+#define bFM3_BT0_PWM_TMCR_CTEN                 *((volatile unsigned int*)(0x424A0184UL))\r
+#define bFM3_BT0_PWM_TMCR_MDSE                 *((volatile unsigned int*)(0x424A0188UL))\r
+#define bFM3_BT0_PWM_TMCR_OSEL                 *((volatile unsigned int*)(0x424A018CUL))\r
+#define bFM3_BT0_PWM_TMCR_FMD0                 *((volatile unsigned int*)(0x424A0190UL))\r
+#define bFM3_BT0_PWM_TMCR_FMD1                 *((volatile unsigned int*)(0x424A0194UL))\r
+#define bFM3_BT0_PWM_TMCR_FMD2                 *((volatile unsigned int*)(0x424A0198UL))\r
+#define bFM3_BT0_PWM_TMCR_EGS0                 *((volatile unsigned int*)(0x424A01A0UL))\r
+#define bFM3_BT0_PWM_TMCR_EGS1                 *((volatile unsigned int*)(0x424A01A4UL))\r
+#define bFM3_BT0_PWM_TMCR_PMSK                 *((volatile unsigned int*)(0x424A01A8UL))\r
+#define bFM3_BT0_PWM_TMCR_RTGEN                *((volatile unsigned int*)(0x424A01ACUL))\r
+#define bFM3_BT0_PWM_TMCR_CKS0                 *((volatile unsigned int*)(0x424A01B0UL))\r
+#define bFM3_BT0_PWM_TMCR_CKS1                 *((volatile unsigned int*)(0x424A01B4UL))\r
+#define bFM3_BT0_PWM_TMCR_CKS2                 *((volatile unsigned int*)(0x424A01B8UL))\r
+#define bFM3_BT0_PWM_STC_UDIR                  *((volatile unsigned int*)(0x424A0200UL))\r
+#define bFM3_BT0_PWM_STC_DTIR                  *((volatile unsigned int*)(0x424A0204UL))\r
+#define bFM3_BT0_PWM_STC_TGIR                  *((volatile unsigned int*)(0x424A0208UL))\r
+#define bFM3_BT0_PWM_STC_UDIE                  *((volatile unsigned int*)(0x424A0210UL))\r
+#define bFM3_BT0_PWM_STC_DTIE                  *((volatile unsigned int*)(0x424A0214UL))\r
+#define bFM3_BT0_PWM_STC_TGIE                  *((volatile unsigned int*)(0x424A0218UL))\r
+#define bFM3_BT0_PWM_TMCR2_CKS3                *((volatile unsigned int*)(0x424A0220UL))\r
+\r
+/* Base Timer 0 RT registers */\r
+#define bFM3_BT0_RT_TMCR_STRG                  *((volatile unsigned int*)(0x424A0180UL))\r
+#define bFM3_BT0_RT_TMCR_CTEN                  *((volatile unsigned int*)(0x424A0184UL))\r
+#define bFM3_BT0_RT_TMCR_MDSE                  *((volatile unsigned int*)(0x424A0188UL))\r
+#define bFM3_BT0_RT_TMCR_OSEL                  *((volatile unsigned int*)(0x424A018CUL))\r
+#define bFM3_BT0_RT_TMCR_FMD0                  *((volatile unsigned int*)(0x424A0190UL))\r
+#define bFM3_BT0_RT_TMCR_FMD1                  *((volatile unsigned int*)(0x424A0194UL))\r
+#define bFM3_BT0_RT_TMCR_FMD2                  *((volatile unsigned int*)(0x424A0198UL))\r
+#define bFM3_BT0_RT_TMCR_T32                   *((volatile unsigned int*)(0x424A019CUL))\r
+#define bFM3_BT0_RT_TMCR_EGS0                  *((volatile unsigned int*)(0x424A01A0UL))\r
+#define bFM3_BT0_RT_TMCR_EGS1                  *((volatile unsigned int*)(0x424A01A4UL))\r
+#define bFM3_BT0_RT_TMCR_CKS0                  *((volatile unsigned int*)(0x424A01B0UL))\r
+#define bFM3_BT0_RT_TMCR_CKS1                  *((volatile unsigned int*)(0x424A01B4UL))\r
+#define bFM3_BT0_RT_TMCR_CKS2                  *((volatile unsigned int*)(0x424A01B8UL))\r
+#define bFM3_BT0_RT_STC_UDIR                   *((volatile unsigned int*)(0x424A0200UL))\r
+#define bFM3_BT0_RT_STC_TGIR                   *((volatile unsigned int*)(0x424A0208UL))\r
+#define bFM3_BT0_RT_STC_UDIE                   *((volatile unsigned int*)(0x424A0210UL))\r
+#define bFM3_BT0_RT_STC_TGIE                   *((volatile unsigned int*)(0x424A0218UL))\r
+#define bFM3_BT0_RT_TMCR2_CKS3                 *((volatile unsigned int*)(0x424A0220UL))\r
+\r
+/* Base Timer 0 PWC registers */\r
+#define bFM3_BT0_PWC_TMCR_CTEN                 *((volatile unsigned int*)(0x424A0184UL))\r
+#define bFM3_BT0_PWC_TMCR_MDSE                 *((volatile unsigned int*)(0x424A0188UL))\r
+#define bFM3_BT0_PWC_TMCR_FMD0                 *((volatile unsigned int*)(0x424A0190UL))\r
+#define bFM3_BT0_PWC_TMCR_FMD1                 *((volatile unsigned int*)(0x424A0194UL))\r
+#define bFM3_BT0_PWC_TMCR_FMD2                 *((volatile unsigned int*)(0x424A0198UL))\r
+#define bFM3_BT0_PWC_TMCR_T32                  *((volatile unsigned int*)(0x424A019CUL))\r
+#define bFM3_BT0_PWC_TMCR_EGS0                 *((volatile unsigned int*)(0x424A01A0UL))\r
+#define bFM3_BT0_PWC_TMCR_EGS1                 *((volatile unsigned int*)(0x424A01A4UL))\r
+#define bFM3_BT0_PWC_TMCR_EGS2                 *((volatile unsigned int*)(0x424A01A8UL))\r
+#define bFM3_BT0_PWC_TMCR_CKS0                 *((volatile unsigned int*)(0x424A01B0UL))\r
+#define bFM3_BT0_PWC_TMCR_CKS1                 *((volatile unsigned int*)(0x424A01B4UL))\r
+#define bFM3_BT0_PWC_TMCR_CKS2                 *((volatile unsigned int*)(0x424A01B8UL))\r
+#define bFM3_BT0_PWC_STC_OVIR                  *((volatile unsigned int*)(0x424A0200UL))\r
+#define bFM3_BT0_PWC_STC_EDIR                  *((volatile unsigned int*)(0x424A0208UL))\r
+#define bFM3_BT0_PWC_STC_OVIE                  *((volatile unsigned int*)(0x424A0210UL))\r
+#define bFM3_BT0_PWC_STC_EDIE                  *((volatile unsigned int*)(0x424A0218UL))\r
+#define bFM3_BT0_PWC_STC_ERR                   *((volatile unsigned int*)(0x424A021CUL))\r
+#define bFM3_BT0_PWC_TMCR2_CKS3                *((volatile unsigned int*)(0x424A0220UL))\r
+\r
+/* Base Timer 1 PPG registers */\r
+#define bFM3_BT1_PPG_TMCR_STRG                 *((volatile unsigned int*)(0x424A0980UL))\r
+#define bFM3_BT1_PPG_TMCR_CTEN                 *((volatile unsigned int*)(0x424A0984UL))\r
+#define bFM3_BT1_PPG_TMCR_MDSE                 *((volatile unsigned int*)(0x424A0988UL))\r
+#define bFM3_BT1_PPG_TMCR_OSEL                 *((volatile unsigned int*)(0x424A098CUL))\r
+#define bFM3_BT1_PPG_TMCR_FMD0                 *((volatile unsigned int*)(0x424A0990UL))\r
+#define bFM3_BT1_PPG_TMCR_FMD1                 *((volatile unsigned int*)(0x424A0994UL))\r
+#define bFM3_BT1_PPG_TMCR_FMD2                 *((volatile unsigned int*)(0x424A0998UL))\r
+#define bFM3_BT1_PPG_TMCR_EGS0                 *((volatile unsigned int*)(0x424A09A0UL))\r
+#define bFM3_BT1_PPG_TMCR_EGS1                 *((volatile unsigned int*)(0x424A09A4UL))\r
+#define bFM3_BT1_PPG_TMCR_PMSK                 *((volatile unsigned int*)(0x424A09A8UL))\r
+#define bFM3_BT1_PPG_TMCR_RTGEN                *((volatile unsigned int*)(0x424A09ACUL))\r
+#define bFM3_BT1_PPG_TMCR_CKS0                 *((volatile unsigned int*)(0x424A09B0UL))\r
+#define bFM3_BT1_PPG_TMCR_CKS1                 *((volatile unsigned int*)(0x424A09B4UL))\r
+#define bFM3_BT1_PPG_TMCR_CKS2                 *((volatile unsigned int*)(0x424A09B8UL))\r
+#define bFM3_BT1_PPG_STC_UDIR                  *((volatile unsigned int*)(0x424A0A00UL))\r
+#define bFM3_BT1_PPG_STC_TGIR                  *((volatile unsigned int*)(0x424A0A08UL))\r
+#define bFM3_BT1_PPG_STC_UDIE                  *((volatile unsigned int*)(0x424A0A10UL))\r
+#define bFM3_BT1_PPG_STC_TGIE                  *((volatile unsigned int*)(0x424A0A18UL))\r
+#define bFM3_BT1_PPG_TMCR2_CKS3                *((volatile unsigned int*)(0x424A0A20UL))\r
+\r
+/* Base Timer 1 PWM registers */\r
+#define bFM3_BT1_PWM_TMCR_STRG                 *((volatile unsigned int*)(0x424A0980UL))\r
+#define bFM3_BT1_PWM_TMCR_CTEN                 *((volatile unsigned int*)(0x424A0984UL))\r
+#define bFM3_BT1_PWM_TMCR_MDSE                 *((volatile unsigned int*)(0x424A0988UL))\r
+#define bFM3_BT1_PWM_TMCR_OSEL                 *((volatile unsigned int*)(0x424A098CUL))\r
+#define bFM3_BT1_PWM_TMCR_FMD0                 *((volatile unsigned int*)(0x424A0990UL))\r
+#define bFM3_BT1_PWM_TMCR_FMD1                 *((volatile unsigned int*)(0x424A0994UL))\r
+#define bFM3_BT1_PWM_TMCR_FMD2                 *((volatile unsigned int*)(0x424A0998UL))\r
+#define bFM3_BT1_PWM_TMCR_EGS0                 *((volatile unsigned int*)(0x424A09A0UL))\r
+#define bFM3_BT1_PWM_TMCR_EGS1                 *((volatile unsigned int*)(0x424A09A4UL))\r
+#define bFM3_BT1_PWM_TMCR_PMSK                 *((volatile unsigned int*)(0x424A09A8UL))\r
+#define bFM3_BT1_PWM_TMCR_RTGEN                *((volatile unsigned int*)(0x424A09ACUL))\r
+#define bFM3_BT1_PWM_TMCR_CKS0                 *((volatile unsigned int*)(0x424A09B0UL))\r
+#define bFM3_BT1_PWM_TMCR_CKS1                 *((volatile unsigned int*)(0x424A09B4UL))\r
+#define bFM3_BT1_PWM_TMCR_CKS2                 *((volatile unsigned int*)(0x424A09B8UL))\r
+#define bFM3_BT1_PWM_STC_UDIR                  *((volatile unsigned int*)(0x424A0A00UL))\r
+#define bFM3_BT1_PWM_STC_DTIR                  *((volatile unsigned int*)(0x424A0A04UL))\r
+#define bFM3_BT1_PWM_STC_TGIR                  *((volatile unsigned int*)(0x424A0A08UL))\r
+#define bFM3_BT1_PWM_STC_UDIE                  *((volatile unsigned int*)(0x424A0A10UL))\r
+#define bFM3_BT1_PWM_STC_DTIE                  *((volatile unsigned int*)(0x424A0A14UL))\r
+#define bFM3_BT1_PWM_STC_TGIE                  *((volatile unsigned int*)(0x424A0A18UL))\r
+#define bFM3_BT1_PWM_TMCR2_CKS3                *((volatile unsigned int*)(0x424A0A20UL))\r
+\r
+/* Base Timer 1 RT registers */\r
+#define bFM3_BT1_RT_TMCR_STRG                  *((volatile unsigned int*)(0x424A0980UL))\r
+#define bFM3_BT1_RT_TMCR_CTEN                  *((volatile unsigned int*)(0x424A0984UL))\r
+#define bFM3_BT1_RT_TMCR_MDSE                  *((volatile unsigned int*)(0x424A0988UL))\r
+#define bFM3_BT1_RT_TMCR_OSEL                  *((volatile unsigned int*)(0x424A098CUL))\r
+#define bFM3_BT1_RT_TMCR_FMD0                  *((volatile unsigned int*)(0x424A0990UL))\r
+#define bFM3_BT1_RT_TMCR_FMD1                  *((volatile unsigned int*)(0x424A0994UL))\r
+#define bFM3_BT1_RT_TMCR_FMD2                  *((volatile unsigned int*)(0x424A0998UL))\r
+#define bFM3_BT1_RT_TMCR_T32                   *((volatile unsigned int*)(0x424A099CUL))\r
+#define bFM3_BT1_RT_TMCR_EGS0                  *((volatile unsigned int*)(0x424A09A0UL))\r
+#define bFM3_BT1_RT_TMCR_EGS1                  *((volatile unsigned int*)(0x424A09A4UL))\r
+#define bFM3_BT1_RT_TMCR_CKS0                  *((volatile unsigned int*)(0x424A09B0UL))\r
+#define bFM3_BT1_RT_TMCR_CKS1                  *((volatile unsigned int*)(0x424A09B4UL))\r
+#define bFM3_BT1_RT_TMCR_CKS2                  *((volatile unsigned int*)(0x424A09B8UL))\r
+#define bFM3_BT1_RT_STC_UDIR                   *((volatile unsigned int*)(0x424A0A00UL))\r
+#define bFM3_BT1_RT_STC_TGIR                   *((volatile unsigned int*)(0x424A0A08UL))\r
+#define bFM3_BT1_RT_STC_UDIE                   *((volatile unsigned int*)(0x424A0A10UL))\r
+#define bFM3_BT1_RT_STC_TGIE                   *((volatile unsigned int*)(0x424A0A18UL))\r
+#define bFM3_BT1_RT_TMCR2_CKS3                 *((volatile unsigned int*)(0x424A0A20UL))\r
+\r
+/* Base Timer 1 PWC registers */\r
+#define bFM3_BT1_PWC_TMCR_CTEN                 *((volatile unsigned int*)(0x424A0984UL))\r
+#define bFM3_BT1_PWC_TMCR_MDSE                 *((volatile unsigned int*)(0x424A0988UL))\r
+#define bFM3_BT1_PWC_TMCR_FMD0                 *((volatile unsigned int*)(0x424A0990UL))\r
+#define bFM3_BT1_PWC_TMCR_FMD1                 *((volatile unsigned int*)(0x424A0994UL))\r
+#define bFM3_BT1_PWC_TMCR_FMD2                 *((volatile unsigned int*)(0x424A0998UL))\r
+#define bFM3_BT1_PWC_TMCR_T32                  *((volatile unsigned int*)(0x424A099CUL))\r
+#define bFM3_BT1_PWC_TMCR_EGS0                 *((volatile unsigned int*)(0x424A09A0UL))\r
+#define bFM3_BT1_PWC_TMCR_EGS1                 *((volatile unsigned int*)(0x424A09A4UL))\r
+#define bFM3_BT1_PWC_TMCR_EGS2                 *((volatile unsigned int*)(0x424A09A8UL))\r
+#define bFM3_BT1_PWC_TMCR_CKS0                 *((volatile unsigned int*)(0x424A09B0UL))\r
+#define bFM3_BT1_PWC_TMCR_CKS1                 *((volatile unsigned int*)(0x424A09B4UL))\r
+#define bFM3_BT1_PWC_TMCR_CKS2                 *((volatile unsigned int*)(0x424A09B8UL))\r
+#define bFM3_BT1_PWC_STC_OVIR                  *((volatile unsigned int*)(0x424A0A00UL))\r
+#define bFM3_BT1_PWC_STC_EDIR                  *((volatile unsigned int*)(0x424A0A08UL))\r
+#define bFM3_BT1_PWC_STC_OVIE                  *((volatile unsigned int*)(0x424A0A10UL))\r
+#define bFM3_BT1_PWC_STC_EDIE                  *((volatile unsigned int*)(0x424A0A18UL))\r
+#define bFM3_BT1_PWC_STC_ERR                   *((volatile unsigned int*)(0x424A0A1CUL))\r
+#define bFM3_BT1_PWC_TMCR2_CKS3                *((volatile unsigned int*)(0x424A0A20UL))\r
+\r
+/* Base Timer 2 PPG registers */\r
+#define bFM3_BT2_PPG_TMCR_STRG                 *((volatile unsigned int*)(0x424A1180UL))\r
+#define bFM3_BT2_PPG_TMCR_CTEN                 *((volatile unsigned int*)(0x424A1184UL))\r
+#define bFM3_BT2_PPG_TMCR_MDSE                 *((volatile unsigned int*)(0x424A1188UL))\r
+#define bFM3_BT2_PPG_TMCR_OSEL                 *((volatile unsigned int*)(0x424A118CUL))\r
+#define bFM3_BT2_PPG_TMCR_FMD0                 *((volatile unsigned int*)(0x424A1190UL))\r
+#define bFM3_BT2_PPG_TMCR_FMD1                 *((volatile unsigned int*)(0x424A1194UL))\r
+#define bFM3_BT2_PPG_TMCR_FMD2                 *((volatile unsigned int*)(0x424A1198UL))\r
+#define bFM3_BT2_PPG_TMCR_EGS0                 *((volatile unsigned int*)(0x424A11A0UL))\r
+#define bFM3_BT2_PPG_TMCR_EGS1                 *((volatile unsigned int*)(0x424A11A4UL))\r
+#define bFM3_BT2_PPG_TMCR_PMSK                 *((volatile unsigned int*)(0x424A11A8UL))\r
+#define bFM3_BT2_PPG_TMCR_RTGEN                *((volatile unsigned int*)(0x424A11ACUL))\r
+#define bFM3_BT2_PPG_TMCR_CKS0                 *((volatile unsigned int*)(0x424A11B0UL))\r
+#define bFM3_BT2_PPG_TMCR_CKS1                 *((volatile unsigned int*)(0x424A11B4UL))\r
+#define bFM3_BT2_PPG_TMCR_CKS2                 *((volatile unsigned int*)(0x424A11B8UL))\r
+#define bFM3_BT2_PPG_STC_UDIR                  *((volatile unsigned int*)(0x424A1200UL))\r
+#define bFM3_BT2_PPG_STC_TGIR                  *((volatile unsigned int*)(0x424A1208UL))\r
+#define bFM3_BT2_PPG_STC_UDIE                  *((volatile unsigned int*)(0x424A1210UL))\r
+#define bFM3_BT2_PPG_STC_TGIE                  *((volatile unsigned int*)(0x424A1218UL))\r
+#define bFM3_BT2_PPG_TMCR2_CKS3                *((volatile unsigned int*)(0x424A1220UL))\r
+\r
+/* Base Timer 2 PWM registers */\r
+#define bFM3_BT2_PWM_TMCR_STRG                 *((volatile unsigned int*)(0x424A1180UL))\r
+#define bFM3_BT2_PWM_TMCR_CTEN                 *((volatile unsigned int*)(0x424A1184UL))\r
+#define bFM3_BT2_PWM_TMCR_MDSE                 *((volatile unsigned int*)(0x424A1188UL))\r
+#define bFM3_BT2_PWM_TMCR_OSEL                 *((volatile unsigned int*)(0x424A118CUL))\r
+#define bFM3_BT2_PWM_TMCR_FMD0                 *((volatile unsigned int*)(0x424A1190UL))\r
+#define bFM3_BT2_PWM_TMCR_FMD1                 *((volatile unsigned int*)(0x424A1194UL))\r
+#define bFM3_BT2_PWM_TMCR_FMD2                 *((volatile unsigned int*)(0x424A1198UL))\r
+#define bFM3_BT2_PWM_TMCR_EGS0                 *((volatile unsigned int*)(0x424A11A0UL))\r
+#define bFM3_BT2_PWM_TMCR_EGS1                 *((volatile unsigned int*)(0x424A11A4UL))\r
+#define bFM3_BT2_PWM_TMCR_PMSK                 *((volatile unsigned int*)(0x424A11A8UL))\r
+#define bFM3_BT2_PWM_TMCR_RTGEN                *((volatile unsigned int*)(0x424A11ACUL))\r
+#define bFM3_BT2_PWM_TMCR_CKS0                 *((volatile unsigned int*)(0x424A11B0UL))\r
+#define bFM3_BT2_PWM_TMCR_CKS1                 *((volatile unsigned int*)(0x424A11B4UL))\r
+#define bFM3_BT2_PWM_TMCR_CKS2                 *((volatile unsigned int*)(0x424A11B8UL))\r
+#define bFM3_BT2_PWM_STC_UDIR                  *((volatile unsigned int*)(0x424A1200UL))\r
+#define bFM3_BT2_PWM_STC_DTIR                  *((volatile unsigned int*)(0x424A1204UL))\r
+#define bFM3_BT2_PWM_STC_TGIR                  *((volatile unsigned int*)(0x424A1208UL))\r
+#define bFM3_BT2_PWM_STC_UDIE                  *((volatile unsigned int*)(0x424A1210UL))\r
+#define bFM3_BT2_PWM_STC_DTIE                  *((volatile unsigned int*)(0x424A1214UL))\r
+#define bFM3_BT2_PWM_STC_TGIE                  *((volatile unsigned int*)(0x424A1218UL))\r
+#define bFM3_BT2_PWM_TMCR2_CKS3                *((volatile unsigned int*)(0x424A1220UL))\r
+\r
+/* Base Timer 2 RT registers */\r
+#define bFM3_BT2_RT_TMCR_STRG                  *((volatile unsigned int*)(0x424A1180UL))\r
+#define bFM3_BT2_RT_TMCR_CTEN                  *((volatile unsigned int*)(0x424A1184UL))\r
+#define bFM3_BT2_RT_TMCR_MDSE                  *((volatile unsigned int*)(0x424A1188UL))\r
+#define bFM3_BT2_RT_TMCR_OSEL                  *((volatile unsigned int*)(0x424A118CUL))\r
+#define bFM3_BT2_RT_TMCR_FMD0                  *((volatile unsigned int*)(0x424A1190UL))\r
+#define bFM3_BT2_RT_TMCR_FMD1                  *((volatile unsigned int*)(0x424A1194UL))\r
+#define bFM3_BT2_RT_TMCR_FMD2                  *((volatile unsigned int*)(0x424A1198UL))\r
+#define bFM3_BT2_RT_TMCR_T32                   *((volatile unsigned int*)(0x424A119CUL))\r
+#define bFM3_BT2_RT_TMCR_EGS0                  *((volatile unsigned int*)(0x424A11A0UL))\r
+#define bFM3_BT2_RT_TMCR_EGS1                  *((volatile unsigned int*)(0x424A11A4UL))\r
+#define bFM3_BT2_RT_TMCR_CKS0                  *((volatile unsigned int*)(0x424A11B0UL))\r
+#define bFM3_BT2_RT_TMCR_CKS1                  *((volatile unsigned int*)(0x424A11B4UL))\r
+#define bFM3_BT2_RT_TMCR_CKS2                  *((volatile unsigned int*)(0x424A11B8UL))\r
+#define bFM3_BT2_RT_STC_UDIR                   *((volatile unsigned int*)(0x424A1200UL))\r
+#define bFM3_BT2_RT_STC_TGIR                   *((volatile unsigned int*)(0x424A1208UL))\r
+#define bFM3_BT2_RT_STC_UDIE                   *((volatile unsigned int*)(0x424A1210UL))\r
+#define bFM3_BT2_RT_STC_TGIE                   *((volatile unsigned int*)(0x424A1218UL))\r
+#define bFM3_BT2_RT_TMCR2_CKS3                 *((volatile unsigned int*)(0x424A1220UL))\r
+\r
+/* Base Timer 2 PWC registers */\r
+#define bFM3_BT2_PWC_TMCR_CTEN                 *((volatile unsigned int*)(0x424A1184UL))\r
+#define bFM3_BT2_PWC_TMCR_MDSE                 *((volatile unsigned int*)(0x424A1188UL))\r
+#define bFM3_BT2_PWC_TMCR_FMD0                 *((volatile unsigned int*)(0x424A1190UL))\r
+#define bFM3_BT2_PWC_TMCR_FMD1                 *((volatile unsigned int*)(0x424A1194UL))\r
+#define bFM3_BT2_PWC_TMCR_FMD2                 *((volatile unsigned int*)(0x424A1198UL))\r
+#define bFM3_BT2_PWC_TMCR_T32                  *((volatile unsigned int*)(0x424A119CUL))\r
+#define bFM3_BT2_PWC_TMCR_EGS0                 *((volatile unsigned int*)(0x424A11A0UL))\r
+#define bFM3_BT2_PWC_TMCR_EGS1                 *((volatile unsigned int*)(0x424A11A4UL))\r
+#define bFM3_BT2_PWC_TMCR_EGS2                 *((volatile unsigned int*)(0x424A11A8UL))\r
+#define bFM3_BT2_PWC_TMCR_CKS0                 *((volatile unsigned int*)(0x424A11B0UL))\r
+#define bFM3_BT2_PWC_TMCR_CKS1                 *((volatile unsigned int*)(0x424A11B4UL))\r
+#define bFM3_BT2_PWC_TMCR_CKS2                 *((volatile unsigned int*)(0x424A11B8UL))\r
+#define bFM3_BT2_PWC_STC_OVIR                  *((volatile unsigned int*)(0x424A1200UL))\r
+#define bFM3_BT2_PWC_STC_EDIR                  *((volatile unsigned int*)(0x424A1208UL))\r
+#define bFM3_BT2_PWC_STC_OVIE                  *((volatile unsigned int*)(0x424A1210UL))\r
+#define bFM3_BT2_PWC_STC_EDIE                  *((volatile unsigned int*)(0x424A1218UL))\r
+#define bFM3_BT2_PWC_STC_ERR                   *((volatile unsigned int*)(0x424A121CUL))\r
+#define bFM3_BT2_PWC_TMCR2_CKS3                *((volatile unsigned int*)(0x424A1220UL))\r
+\r
+/* Base Timer 3 PPG registers */\r
+#define bFM3_BT3_PPG_TMCR_STRG                 *((volatile unsigned int*)(0x424A1980UL))\r
+#define bFM3_BT3_PPG_TMCR_CTEN                 *((volatile unsigned int*)(0x424A1984UL))\r
+#define bFM3_BT3_PPG_TMCR_MDSE                 *((volatile unsigned int*)(0x424A1988UL))\r
+#define bFM3_BT3_PPG_TMCR_OSEL                 *((volatile unsigned int*)(0x424A198CUL))\r
+#define bFM3_BT3_PPG_TMCR_FMD0                 *((volatile unsigned int*)(0x424A1990UL))\r
+#define bFM3_BT3_PPG_TMCR_FMD1                 *((volatile unsigned int*)(0x424A1994UL))\r
+#define bFM3_BT3_PPG_TMCR_FMD2                 *((volatile unsigned int*)(0x424A1998UL))\r
+#define bFM3_BT3_PPG_TMCR_EGS0                 *((volatile unsigned int*)(0x424A19A0UL))\r
+#define bFM3_BT3_PPG_TMCR_EGS1                 *((volatile unsigned int*)(0x424A19A4UL))\r
+#define bFM3_BT3_PPG_TMCR_PMSK                 *((volatile unsigned int*)(0x424A19A8UL))\r
+#define bFM3_BT3_PPG_TMCR_RTGEN                *((volatile unsigned int*)(0x424A19ACUL))\r
+#define bFM3_BT3_PPG_TMCR_CKS0                 *((volatile unsigned int*)(0x424A19B0UL))\r
+#define bFM3_BT3_PPG_TMCR_CKS1                 *((volatile unsigned int*)(0x424A19B4UL))\r
+#define bFM3_BT3_PPG_TMCR_CKS2                 *((volatile unsigned int*)(0x424A19B8UL))\r
+#define bFM3_BT3_PPG_STC_UDIR                  *((volatile unsigned int*)(0x424A1A00UL))\r
+#define bFM3_BT3_PPG_STC_TGIR                  *((volatile unsigned int*)(0x424A1A08UL))\r
+#define bFM3_BT3_PPG_STC_UDIE                  *((volatile unsigned int*)(0x424A1A10UL))\r
+#define bFM3_BT3_PPG_STC_TGIE                  *((volatile unsigned int*)(0x424A1A18UL))\r
+#define bFM3_BT3_PPG_TMCR2_CKS3                *((volatile unsigned int*)(0x424A1A20UL))\r
+\r
+/* Base Timer 3 PWM registers */\r
+#define bFM3_BT3_PWM_TMCR_STRG                 *((volatile unsigned int*)(0x424A1980UL))\r
+#define bFM3_BT3_PWM_TMCR_CTEN                 *((volatile unsigned int*)(0x424A1984UL))\r
+#define bFM3_BT3_PWM_TMCR_MDSE                 *((volatile unsigned int*)(0x424A1988UL))\r
+#define bFM3_BT3_PWM_TMCR_OSEL                 *((volatile unsigned int*)(0x424A198CUL))\r
+#define bFM3_BT3_PWM_TMCR_FMD0                 *((volatile unsigned int*)(0x424A1990UL))\r
+#define bFM3_BT3_PWM_TMCR_FMD1                 *((volatile unsigned int*)(0x424A1994UL))\r
+#define bFM3_BT3_PWM_TMCR_FMD2                 *((volatile unsigned int*)(0x424A1998UL))\r
+#define bFM3_BT3_PWM_TMCR_EGS0                 *((volatile unsigned int*)(0x424A19A0UL))\r
+#define bFM3_BT3_PWM_TMCR_EGS1                 *((volatile unsigned int*)(0x424A19A4UL))\r
+#define bFM3_BT3_PWM_TMCR_PMSK                 *((volatile unsigned int*)(0x424A19A8UL))\r
+#define bFM3_BT3_PWM_TMCR_RTGEN                *((volatile unsigned int*)(0x424A19ACUL))\r
+#define bFM3_BT3_PWM_TMCR_CKS0                 *((volatile unsigned int*)(0x424A19B0UL))\r
+#define bFM3_BT3_PWM_TMCR_CKS1                 *((volatile unsigned int*)(0x424A19B4UL))\r
+#define bFM3_BT3_PWM_TMCR_CKS2                 *((volatile unsigned int*)(0x424A19B8UL))\r
+#define bFM3_BT3_PWM_STC_UDIR                  *((volatile unsigned int*)(0x424A1A00UL))\r
+#define bFM3_BT3_PWM_STC_DTIR                  *((volatile unsigned int*)(0x424A1A04UL))\r
+#define bFM3_BT3_PWM_STC_TGIR                  *((volatile unsigned int*)(0x424A1A08UL))\r
+#define bFM3_BT3_PWM_STC_UDIE                  *((volatile unsigned int*)(0x424A1A10UL))\r
+#define bFM3_BT3_PWM_STC_DTIE                  *((volatile unsigned int*)(0x424A1A14UL))\r
+#define bFM3_BT3_PWM_STC_TGIE                  *((volatile unsigned int*)(0x424A1A18UL))\r
+#define bFM3_BT3_PWM_TMCR2_CKS3                *((volatile unsigned int*)(0x424A1A20UL))\r
+\r
+/* Base Timer 3 RT registers */\r
+#define bFM3_BT3_RT_TMCR_STRG                  *((volatile unsigned int*)(0x424A1980UL))\r
+#define bFM3_BT3_RT_TMCR_CTEN                  *((volatile unsigned int*)(0x424A1984UL))\r
+#define bFM3_BT3_RT_TMCR_MDSE                  *((volatile unsigned int*)(0x424A1988UL))\r
+#define bFM3_BT3_RT_TMCR_OSEL                  *((volatile unsigned int*)(0x424A198CUL))\r
+#define bFM3_BT3_RT_TMCR_FMD0                  *((volatile unsigned int*)(0x424A1990UL))\r
+#define bFM3_BT3_RT_TMCR_FMD1                  *((volatile unsigned int*)(0x424A1994UL))\r
+#define bFM3_BT3_RT_TMCR_FMD2                  *((volatile unsigned int*)(0x424A1998UL))\r
+#define bFM3_BT3_RT_TMCR_T32                   *((volatile unsigned int*)(0x424A199CUL))\r
+#define bFM3_BT3_RT_TMCR_EGS0                  *((volatile unsigned int*)(0x424A19A0UL))\r
+#define bFM3_BT3_RT_TMCR_EGS1                  *((volatile unsigned int*)(0x424A19A4UL))\r
+#define bFM3_BT3_RT_TMCR_CKS0                  *((volatile unsigned int*)(0x424A19B0UL))\r
+#define bFM3_BT3_RT_TMCR_CKS1                  *((volatile unsigned int*)(0x424A19B4UL))\r
+#define bFM3_BT3_RT_TMCR_CKS2                  *((volatile unsigned int*)(0x424A19B8UL))\r
+#define bFM3_BT3_RT_STC_UDIR                   *((volatile unsigned int*)(0x424A1A00UL))\r
+#define bFM3_BT3_RT_STC_TGIR                   *((volatile unsigned int*)(0x424A1A08UL))\r
+#define bFM3_BT3_RT_STC_UDIE                   *((volatile unsigned int*)(0x424A1A10UL))\r
+#define bFM3_BT3_RT_STC_TGIE                   *((volatile unsigned int*)(0x424A1A18UL))\r
+#define bFM3_BT3_RT_TMCR2_CKS3                 *((volatile unsigned int*)(0x424A1A20UL))\r
+\r
+/* Base Timer 3 PWC registers */\r
+#define bFM3_BT3_PWC_TMCR_CTEN                 *((volatile unsigned int*)(0x424A1984UL))\r
+#define bFM3_BT3_PWC_TMCR_MDSE                 *((volatile unsigned int*)(0x424A1988UL))\r
+#define bFM3_BT3_PWC_TMCR_FMD0                 *((volatile unsigned int*)(0x424A1990UL))\r
+#define bFM3_BT3_PWC_TMCR_FMD1                 *((volatile unsigned int*)(0x424A1994UL))\r
+#define bFM3_BT3_PWC_TMCR_FMD2                 *((volatile unsigned int*)(0x424A1998UL))\r
+#define bFM3_BT3_PWC_TMCR_T32                  *((volatile unsigned int*)(0x424A199CUL))\r
+#define bFM3_BT3_PWC_TMCR_EGS0                 *((volatile unsigned int*)(0x424A19A0UL))\r
+#define bFM3_BT3_PWC_TMCR_EGS1                 *((volatile unsigned int*)(0x424A19A4UL))\r
+#define bFM3_BT3_PWC_TMCR_EGS2                 *((volatile unsigned int*)(0x424A19A8UL))\r
+#define bFM3_BT3_PWC_TMCR_CKS0                 *((volatile unsigned int*)(0x424A19B0UL))\r
+#define bFM3_BT3_PWC_TMCR_CKS1                 *((volatile unsigned int*)(0x424A19B4UL))\r
+#define bFM3_BT3_PWC_TMCR_CKS2                 *((volatile unsigned int*)(0x424A19B8UL))\r
+#define bFM3_BT3_PWC_STC_OVIR                  *((volatile unsigned int*)(0x424A1A00UL))\r
+#define bFM3_BT3_PWC_STC_EDIR                  *((volatile unsigned int*)(0x424A1A08UL))\r
+#define bFM3_BT3_PWC_STC_OVIE                  *((volatile unsigned int*)(0x424A1A10UL))\r
+#define bFM3_BT3_PWC_STC_EDIE                  *((volatile unsigned int*)(0x424A1A18UL))\r
+#define bFM3_BT3_PWC_STC_ERR                   *((volatile unsigned int*)(0x424A1A1CUL))\r
+#define bFM3_BT3_PWC_TMCR2_CKS3                *((volatile unsigned int*)(0x424A1A20UL))\r
+\r
+/* Base Timer 4 PPG registers */\r
+#define bFM3_BT4_PPG_TMCR_STRG                 *((volatile unsigned int*)(0x424A4180UL))\r
+#define bFM3_BT4_PPG_TMCR_CTEN                 *((volatile unsigned int*)(0x424A4184UL))\r
+#define bFM3_BT4_PPG_TMCR_MDSE                 *((volatile unsigned int*)(0x424A4188UL))\r
+#define bFM3_BT4_PPG_TMCR_OSEL                 *((volatile unsigned int*)(0x424A418CUL))\r
+#define bFM3_BT4_PPG_TMCR_FMD0                 *((volatile unsigned int*)(0x424A4190UL))\r
+#define bFM3_BT4_PPG_TMCR_FMD1                 *((volatile unsigned int*)(0x424A4194UL))\r
+#define bFM3_BT4_PPG_TMCR_FMD2                 *((volatile unsigned int*)(0x424A4198UL))\r
+#define bFM3_BT4_PPG_TMCR_EGS0                 *((volatile unsigned int*)(0x424A41A0UL))\r
+#define bFM3_BT4_PPG_TMCR_EGS1                 *((volatile unsigned int*)(0x424A41A4UL))\r
+#define bFM3_BT4_PPG_TMCR_PMSK                 *((volatile unsigned int*)(0x424A41A8UL))\r
+#define bFM3_BT4_PPG_TMCR_RTGEN                *((volatile unsigned int*)(0x424A41ACUL))\r
+#define bFM3_BT4_PPG_TMCR_CKS0                 *((volatile unsigned int*)(0x424A41B0UL))\r
+#define bFM3_BT4_PPG_TMCR_CKS1                 *((volatile unsigned int*)(0x424A41B4UL))\r
+#define bFM3_BT4_PPG_TMCR_CKS2                 *((volatile unsigned int*)(0x424A41B8UL))\r
+#define bFM3_BT4_PPG_STC_UDIR                  *((volatile unsigned int*)(0x424A4200UL))\r
+#define bFM3_BT4_PPG_STC_TGIR                  *((volatile unsigned int*)(0x424A4208UL))\r
+#define bFM3_BT4_PPG_STC_UDIE                  *((volatile unsigned int*)(0x424A4210UL))\r
+#define bFM3_BT4_PPG_STC_TGIE                  *((volatile unsigned int*)(0x424A4218UL))\r
+#define bFM3_BT4_PPG_TMCR2_CKS3                *((volatile unsigned int*)(0x424A4220UL))\r
+\r
+/* Base Timer 4 PWM registers */\r
+#define bFM3_BT4_PWM_TMCR_STRG                 *((volatile unsigned int*)(0x424A4180UL))\r
+#define bFM3_BT4_PWM_TMCR_CTEN                 *((volatile unsigned int*)(0x424A4184UL))\r
+#define bFM3_BT4_PWM_TMCR_MDSE                 *((volatile unsigned int*)(0x424A4188UL))\r
+#define bFM3_BT4_PWM_TMCR_OSEL                 *((volatile unsigned int*)(0x424A418CUL))\r
+#define bFM3_BT4_PWM_TMCR_FMD0                 *((volatile unsigned int*)(0x424A4190UL))\r
+#define bFM3_BT4_PWM_TMCR_FMD1                 *((volatile unsigned int*)(0x424A4194UL))\r
+#define bFM3_BT4_PWM_TMCR_FMD2                 *((volatile unsigned int*)(0x424A4198UL))\r
+#define bFM3_BT4_PWM_TMCR_EGS0                 *((volatile unsigned int*)(0x424A41A0UL))\r
+#define bFM3_BT4_PWM_TMCR_EGS1                 *((volatile unsigned int*)(0x424A41A4UL))\r
+#define bFM3_BT4_PWM_TMCR_PMSK                 *((volatile unsigned int*)(0x424A41A8UL))\r
+#define bFM3_BT4_PWM_TMCR_RTGEN                *((volatile unsigned int*)(0x424A41ACUL))\r
+#define bFM3_BT4_PWM_TMCR_CKS0                 *((volatile unsigned int*)(0x424A41B0UL))\r
+#define bFM3_BT4_PWM_TMCR_CKS1                 *((volatile unsigned int*)(0x424A41B4UL))\r
+#define bFM3_BT4_PWM_TMCR_CKS2                 *((volatile unsigned int*)(0x424A41B8UL))\r
+#define bFM3_BT4_PWM_STC_UDIR                  *((volatile unsigned int*)(0x424A4200UL))\r
+#define bFM3_BT4_PWM_STC_DTIR                  *((volatile unsigned int*)(0x424A4204UL))\r
+#define bFM3_BT4_PWM_STC_TGIR                  *((volatile unsigned int*)(0x424A4208UL))\r
+#define bFM3_BT4_PWM_STC_UDIE                  *((volatile unsigned int*)(0x424A4210UL))\r
+#define bFM3_BT4_PWM_STC_DTIE                  *((volatile unsigned int*)(0x424A4214UL))\r
+#define bFM3_BT4_PWM_STC_TGIE                  *((volatile unsigned int*)(0x424A4218UL))\r
+#define bFM3_BT4_PWM_TMCR2_CKS3                *((volatile unsigned int*)(0x424A4220UL))\r
+\r
+/* Base Timer 4 RT registers */\r
+#define bFM3_BT4_RT_TMCR_STRG                  *((volatile unsigned int*)(0x424A4180UL))\r
+#define bFM3_BT4_RT_TMCR_CTEN                  *((volatile unsigned int*)(0x424A4184UL))\r
+#define bFM3_BT4_RT_TMCR_MDSE                  *((volatile unsigned int*)(0x424A4188UL))\r
+#define bFM3_BT4_RT_TMCR_OSEL                  *((volatile unsigned int*)(0x424A418CUL))\r
+#define bFM3_BT4_RT_TMCR_FMD0                  *((volatile unsigned int*)(0x424A4190UL))\r
+#define bFM3_BT4_RT_TMCR_FMD1                  *((volatile unsigned int*)(0x424A4194UL))\r
+#define bFM3_BT4_RT_TMCR_FMD2                  *((volatile unsigned int*)(0x424A4198UL))\r
+#define bFM3_BT4_RT_TMCR_T32                   *((volatile unsigned int*)(0x424A419CUL))\r
+#define bFM3_BT4_RT_TMCR_EGS0                  *((volatile unsigned int*)(0x424A41A0UL))\r
+#define bFM3_BT4_RT_TMCR_EGS1                  *((volatile unsigned int*)(0x424A41A4UL))\r
+#define bFM3_BT4_RT_TMCR_CKS0                  *((volatile unsigned int*)(0x424A41B0UL))\r
+#define bFM3_BT4_RT_TMCR_CKS1                  *((volatile unsigned int*)(0x424A41B4UL))\r
+#define bFM3_BT4_RT_TMCR_CKS2                  *((volatile unsigned int*)(0x424A41B8UL))\r
+#define bFM3_BT4_RT_STC_UDIR                   *((volatile unsigned int*)(0x424A4200UL))\r
+#define bFM3_BT4_RT_STC_TGIR                   *((volatile unsigned int*)(0x424A4208UL))\r
+#define bFM3_BT4_RT_STC_UDIE                   *((volatile unsigned int*)(0x424A4210UL))\r
+#define bFM3_BT4_RT_STC_TGIE                   *((volatile unsigned int*)(0x424A4218UL))\r
+#define bFM3_BT4_RT_TMCR2_CKS3                 *((volatile unsigned int*)(0x424A4220UL))\r
+\r
+/* Base Timer 4 PWC registers */\r
+#define bFM3_BT4_PWC_TMCR_CTEN                 *((volatile unsigned int*)(0x424A4184UL))\r
+#define bFM3_BT4_PWC_TMCR_MDSE                 *((volatile unsigned int*)(0x424A4188UL))\r
+#define bFM3_BT4_PWC_TMCR_FMD0                 *((volatile unsigned int*)(0x424A4190UL))\r
+#define bFM3_BT4_PWC_TMCR_FMD1                 *((volatile unsigned int*)(0x424A4194UL))\r
+#define bFM3_BT4_PWC_TMCR_FMD2                 *((volatile unsigned int*)(0x424A4198UL))\r
+#define bFM3_BT4_PWC_TMCR_T32                  *((volatile unsigned int*)(0x424A419CUL))\r
+#define bFM3_BT4_PWC_TMCR_EGS0                 *((volatile unsigned int*)(0x424A41A0UL))\r
+#define bFM3_BT4_PWC_TMCR_EGS1                 *((volatile unsigned int*)(0x424A41A4UL))\r
+#define bFM3_BT4_PWC_TMCR_EGS2                 *((volatile unsigned int*)(0x424A41A8UL))\r
+#define bFM3_BT4_PWC_TMCR_CKS0                 *((volatile unsigned int*)(0x424A41B0UL))\r
+#define bFM3_BT4_PWC_TMCR_CKS1                 *((volatile unsigned int*)(0x424A41B4UL))\r
+#define bFM3_BT4_PWC_TMCR_CKS2                 *((volatile unsigned int*)(0x424A41B8UL))\r
+#define bFM3_BT4_PWC_STC_OVIR                  *((volatile unsigned int*)(0x424A4200UL))\r
+#define bFM3_BT4_PWC_STC_EDIR                  *((volatile unsigned int*)(0x424A4208UL))\r
+#define bFM3_BT4_PWC_STC_OVIE                  *((volatile unsigned int*)(0x424A4210UL))\r
+#define bFM3_BT4_PWC_STC_EDIE                  *((volatile unsigned int*)(0x424A4218UL))\r
+#define bFM3_BT4_PWC_STC_ERR                   *((volatile unsigned int*)(0x424A421CUL))\r
+#define bFM3_BT4_PWC_TMCR2_CKS3                *((volatile unsigned int*)(0x424A4220UL))\r
+\r
+/* Base Timer 5 PPG registers */\r
+#define bFM3_BT5_PPG_TMCR_STRG                 *((volatile unsigned int*)(0x424A4980UL))\r
+#define bFM3_BT5_PPG_TMCR_CTEN                 *((volatile unsigned int*)(0x424A4984UL))\r
+#define bFM3_BT5_PPG_TMCR_MDSE                 *((volatile unsigned int*)(0x424A4988UL))\r
+#define bFM3_BT5_PPG_TMCR_OSEL                 *((volatile unsigned int*)(0x424A498CUL))\r
+#define bFM3_BT5_PPG_TMCR_FMD0                 *((volatile unsigned int*)(0x424A4990UL))\r
+#define bFM3_BT5_PPG_TMCR_FMD1                 *((volatile unsigned int*)(0x424A4994UL))\r
+#define bFM3_BT5_PPG_TMCR_FMD2                 *((volatile unsigned int*)(0x424A4998UL))\r
+#define bFM3_BT5_PPG_TMCR_EGS0                 *((volatile unsigned int*)(0x424A49A0UL))\r
+#define bFM3_BT5_PPG_TMCR_EGS1                 *((volatile unsigned int*)(0x424A49A4UL))\r
+#define bFM3_BT5_PPG_TMCR_PMSK                 *((volatile unsigned int*)(0x424A49A8UL))\r
+#define bFM3_BT5_PPG_TMCR_RTGEN                *((volatile unsigned int*)(0x424A49ACUL))\r
+#define bFM3_BT5_PPG_TMCR_CKS0                 *((volatile unsigned int*)(0x424A49B0UL))\r
+#define bFM3_BT5_PPG_TMCR_CKS1                 *((volatile unsigned int*)(0x424A49B4UL))\r
+#define bFM3_BT5_PPG_TMCR_CKS2                 *((volatile unsigned int*)(0x424A49B8UL))\r
+#define bFM3_BT5_PPG_STC_UDIR                  *((volatile unsigned int*)(0x424A4A00UL))\r
+#define bFM3_BT5_PPG_STC_TGIR                  *((volatile unsigned int*)(0x424A4A08UL))\r
+#define bFM3_BT5_PPG_STC_UDIE                  *((volatile unsigned int*)(0x424A4A10UL))\r
+#define bFM3_BT5_PPG_STC_TGIE                  *((volatile unsigned int*)(0x424A4A18UL))\r
+#define bFM3_BT5_PPG_TMCR2_CKS3                *((volatile unsigned int*)(0x424A4A20UL))\r
+\r
+/* Base Timer 5 PWM registers */\r
+#define bFM3_BT5_PWM_TMCR_STRG                 *((volatile unsigned int*)(0x424A4980UL))\r
+#define bFM3_BT5_PWM_TMCR_CTEN                 *((volatile unsigned int*)(0x424A4984UL))\r
+#define bFM3_BT5_PWM_TMCR_MDSE                 *((volatile unsigned int*)(0x424A4988UL))\r
+#define bFM3_BT5_PWM_TMCR_OSEL                 *((volatile unsigned int*)(0x424A498CUL))\r
+#define bFM3_BT5_PWM_TMCR_FMD0                 *((volatile unsigned int*)(0x424A4990UL))\r
+#define bFM3_BT5_PWM_TMCR_FMD1                 *((volatile unsigned int*)(0x424A4994UL))\r
+#define bFM3_BT5_PWM_TMCR_FMD2                 *((volatile unsigned int*)(0x424A4998UL))\r
+#define bFM3_BT5_PWM_TMCR_EGS0                 *((volatile unsigned int*)(0x424A49A0UL))\r
+#define bFM3_BT5_PWM_TMCR_EGS1                 *((volatile unsigned int*)(0x424A49A4UL))\r
+#define bFM3_BT5_PWM_TMCR_PMSK                 *((volatile unsigned int*)(0x424A49A8UL))\r
+#define bFM3_BT5_PWM_TMCR_RTGEN                *((volatile unsigned int*)(0x424A49ACUL))\r
+#define bFM3_BT5_PWM_TMCR_CKS0                 *((volatile unsigned int*)(0x424A49B0UL))\r
+#define bFM3_BT5_PWM_TMCR_CKS1                 *((volatile unsigned int*)(0x424A49B4UL))\r
+#define bFM3_BT5_PWM_TMCR_CKS2                 *((volatile unsigned int*)(0x424A49B8UL))\r
+#define bFM3_BT5_PWM_STC_UDIR                  *((volatile unsigned int*)(0x424A4A00UL))\r
+#define bFM3_BT5_PWM_STC_DTIR                  *((volatile unsigned int*)(0x424A4A04UL))\r
+#define bFM3_BT5_PWM_STC_TGIR                  *((volatile unsigned int*)(0x424A4A08UL))\r
+#define bFM3_BT5_PWM_STC_UDIE                  *((volatile unsigned int*)(0x424A4A10UL))\r
+#define bFM3_BT5_PWM_STC_DTIE                  *((volatile unsigned int*)(0x424A4A14UL))\r
+#define bFM3_BT5_PWM_STC_TGIE                  *((volatile unsigned int*)(0x424A4A18UL))\r
+#define bFM3_BT5_PWM_TMCR2_CKS3                *((volatile unsigned int*)(0x424A4A20UL))\r
+\r
+/* Base Timer 5 RT registers */\r
+#define bFM3_BT5_RT_TMCR_STRG                  *((volatile unsigned int*)(0x424A4980UL))\r
+#define bFM3_BT5_RT_TMCR_CTEN                  *((volatile unsigned int*)(0x424A4984UL))\r
+#define bFM3_BT5_RT_TMCR_MDSE                  *((volatile unsigned int*)(0x424A4988UL))\r
+#define bFM3_BT5_RT_TMCR_OSEL                  *((volatile unsigned int*)(0x424A498CUL))\r
+#define bFM3_BT5_RT_TMCR_FMD0                  *((volatile unsigned int*)(0x424A4990UL))\r
+#define bFM3_BT5_RT_TMCR_FMD1                  *((volatile unsigned int*)(0x424A4994UL))\r
+#define bFM3_BT5_RT_TMCR_FMD2                  *((volatile unsigned int*)(0x424A4998UL))\r
+#define bFM3_BT5_RT_TMCR_T32                   *((volatile unsigned int*)(0x424A499CUL))\r
+#define bFM3_BT5_RT_TMCR_EGS0                  *((volatile unsigned int*)(0x424A49A0UL))\r
+#define bFM3_BT5_RT_TMCR_EGS1                  *((volatile unsigned int*)(0x424A49A4UL))\r
+#define bFM3_BT5_RT_TMCR_CKS0                  *((volatile unsigned int*)(0x424A49B0UL))\r
+#define bFM3_BT5_RT_TMCR_CKS1                  *((volatile unsigned int*)(0x424A49B4UL))\r
+#define bFM3_BT5_RT_TMCR_CKS2                  *((volatile unsigned int*)(0x424A49B8UL))\r
+#define bFM3_BT5_RT_STC_UDIR                   *((volatile unsigned int*)(0x424A4A00UL))\r
+#define bFM3_BT5_RT_STC_TGIR                   *((volatile unsigned int*)(0x424A4A08UL))\r
+#define bFM3_BT5_RT_STC_UDIE                   *((volatile unsigned int*)(0x424A4A10UL))\r
+#define bFM3_BT5_RT_STC_TGIE                   *((volatile unsigned int*)(0x424A4A18UL))\r
+#define bFM3_BT5_RT_TMCR2_CKS3                 *((volatile unsigned int*)(0x424A4A20UL))\r
+\r
+/* Base Timer 5 PWC registers */\r
+#define bFM3_BT5_PWC_TMCR_CTEN                 *((volatile unsigned int*)(0x424A4984UL))\r
+#define bFM3_BT5_PWC_TMCR_MDSE                 *((volatile unsigned int*)(0x424A4988UL))\r
+#define bFM3_BT5_PWC_TMCR_FMD0                 *((volatile unsigned int*)(0x424A4990UL))\r
+#define bFM3_BT5_PWC_TMCR_FMD1                 *((volatile unsigned int*)(0x424A4994UL))\r
+#define bFM3_BT5_PWC_TMCR_FMD2                 *((volatile unsigned int*)(0x424A4998UL))\r
+#define bFM3_BT5_PWC_TMCR_T32                  *((volatile unsigned int*)(0x424A499CUL))\r
+#define bFM3_BT5_PWC_TMCR_EGS0                 *((volatile unsigned int*)(0x424A49A0UL))\r
+#define bFM3_BT5_PWC_TMCR_EGS1                 *((volatile unsigned int*)(0x424A49A4UL))\r
+#define bFM3_BT5_PWC_TMCR_EGS2                 *((volatile unsigned int*)(0x424A49A8UL))\r
+#define bFM3_BT5_PWC_TMCR_CKS0                 *((volatile unsigned int*)(0x424A49B0UL))\r
+#define bFM3_BT5_PWC_TMCR_CKS1                 *((volatile unsigned int*)(0x424A49B4UL))\r
+#define bFM3_BT5_PWC_TMCR_CKS2                 *((volatile unsigned int*)(0x424A49B8UL))\r
+#define bFM3_BT5_PWC_STC_OVIR                  *((volatile unsigned int*)(0x424A4A00UL))\r
+#define bFM3_BT5_PWC_STC_EDIR                  *((volatile unsigned int*)(0x424A4A08UL))\r
+#define bFM3_BT5_PWC_STC_OVIE                  *((volatile unsigned int*)(0x424A4A10UL))\r
+#define bFM3_BT5_PWC_STC_EDIE                  *((volatile unsigned int*)(0x424A4A18UL))\r
+#define bFM3_BT5_PWC_STC_ERR                   *((volatile unsigned int*)(0x424A4A1CUL))\r
+#define bFM3_BT5_PWC_TMCR2_CKS3                *((volatile unsigned int*)(0x424A4A20UL))\r
+\r
+/* Base Timer 6 PPG registers */\r
+#define bFM3_BT6_PPG_TMCR_STRG                 *((volatile unsigned int*)(0x424A5180UL))\r
+#define bFM3_BT6_PPG_TMCR_CTEN                 *((volatile unsigned int*)(0x424A5184UL))\r
+#define bFM3_BT6_PPG_TMCR_MDSE                 *((volatile unsigned int*)(0x424A5188UL))\r
+#define bFM3_BT6_PPG_TMCR_OSEL                 *((volatile unsigned int*)(0x424A518CUL))\r
+#define bFM3_BT6_PPG_TMCR_FMD0                 *((volatile unsigned int*)(0x424A5190UL))\r
+#define bFM3_BT6_PPG_TMCR_FMD1                 *((volatile unsigned int*)(0x424A5194UL))\r
+#define bFM3_BT6_PPG_TMCR_FMD2                 *((volatile unsigned int*)(0x424A5198UL))\r
+#define bFM3_BT6_PPG_TMCR_EGS0                 *((volatile unsigned int*)(0x424A51A0UL))\r
+#define bFM3_BT6_PPG_TMCR_EGS1                 *((volatile unsigned int*)(0x424A51A4UL))\r
+#define bFM3_BT6_PPG_TMCR_PMSK                 *((volatile unsigned int*)(0x424A51A8UL))\r
+#define bFM3_BT6_PPG_TMCR_RTGEN                *((volatile unsigned int*)(0x424A51ACUL))\r
+#define bFM3_BT6_PPG_TMCR_CKS0                 *((volatile unsigned int*)(0x424A51B0UL))\r
+#define bFM3_BT6_PPG_TMCR_CKS1                 *((volatile unsigned int*)(0x424A51B4UL))\r
+#define bFM3_BT6_PPG_TMCR_CKS2                 *((volatile unsigned int*)(0x424A51B8UL))\r
+#define bFM3_BT6_PPG_STC_UDIR                  *((volatile unsigned int*)(0x424A5200UL))\r
+#define bFM3_BT6_PPG_STC_TGIR                  *((volatile unsigned int*)(0x424A5208UL))\r
+#define bFM3_BT6_PPG_STC_UDIE                  *((volatile unsigned int*)(0x424A5210UL))\r
+#define bFM3_BT6_PPG_STC_TGIE                  *((volatile unsigned int*)(0x424A5218UL))\r
+#define bFM3_BT6_PPG_TMCR2_CKS3                *((volatile unsigned int*)(0x424A5220UL))\r
+\r
+/* Base Timer 6 PWM registers */\r
+#define bFM3_BT6_PWM_TMCR_STRG                 *((volatile unsigned int*)(0x424A5180UL))\r
+#define bFM3_BT6_PWM_TMCR_CTEN                 *((volatile unsigned int*)(0x424A5184UL))\r
+#define bFM3_BT6_PWM_TMCR_MDSE                 *((volatile unsigned int*)(0x424A5188UL))\r
+#define bFM3_BT6_PWM_TMCR_OSEL                 *((volatile unsigned int*)(0x424A518CUL))\r
+#define bFM3_BT6_PWM_TMCR_FMD0                 *((volatile unsigned int*)(0x424A5190UL))\r
+#define bFM3_BT6_PWM_TMCR_FMD1                 *((volatile unsigned int*)(0x424A5194UL))\r
+#define bFM3_BT6_PWM_TMCR_FMD2                 *((volatile unsigned int*)(0x424A5198UL))\r
+#define bFM3_BT6_PWM_TMCR_EGS0                 *((volatile unsigned int*)(0x424A51A0UL))\r
+#define bFM3_BT6_PWM_TMCR_EGS1                 *((volatile unsigned int*)(0x424A51A4UL))\r
+#define bFM3_BT6_PWM_TMCR_PMSK                 *((volatile unsigned int*)(0x424A51A8UL))\r
+#define bFM3_BT6_PWM_TMCR_RTGEN                *((volatile unsigned int*)(0x424A51ACUL))\r
+#define bFM3_BT6_PWM_TMCR_CKS0                 *((volatile unsigned int*)(0x424A51B0UL))\r
+#define bFM3_BT6_PWM_TMCR_CKS1                 *((volatile unsigned int*)(0x424A51B4UL))\r
+#define bFM3_BT6_PWM_TMCR_CKS2                 *((volatile unsigned int*)(0x424A51B8UL))\r
+#define bFM3_BT6_PWM_STC_UDIR                  *((volatile unsigned int*)(0x424A5200UL))\r
+#define bFM3_BT6_PWM_STC_DTIR                  *((volatile unsigned int*)(0x424A5204UL))\r
+#define bFM3_BT6_PWM_STC_TGIR                  *((volatile unsigned int*)(0x424A5208UL))\r
+#define bFM3_BT6_PWM_STC_UDIE                  *((volatile unsigned int*)(0x424A5210UL))\r
+#define bFM3_BT6_PWM_STC_DTIE                  *((volatile unsigned int*)(0x424A5214UL))\r
+#define bFM3_BT6_PWM_STC_TGIE                  *((volatile unsigned int*)(0x424A5218UL))\r
+#define bFM3_BT6_PWM_TMCR2_CKS3                *((volatile unsigned int*)(0x424A5220UL))\r
+\r
+/* Base Timer 6 RT registers */\r
+#define bFM3_BT6_RT_TMCR_STRG                  *((volatile unsigned int*)(0x424A5180UL))\r
+#define bFM3_BT6_RT_TMCR_CTEN                  *((volatile unsigned int*)(0x424A5184UL))\r
+#define bFM3_BT6_RT_TMCR_MDSE                  *((volatile unsigned int*)(0x424A5188UL))\r
+#define bFM3_BT6_RT_TMCR_OSEL                  *((volatile unsigned int*)(0x424A518CUL))\r
+#define bFM3_BT6_RT_TMCR_FMD0                  *((volatile unsigned int*)(0x424A5190UL))\r
+#define bFM3_BT6_RT_TMCR_FMD1                  *((volatile unsigned int*)(0x424A5194UL))\r
+#define bFM3_BT6_RT_TMCR_FMD2                  *((volatile unsigned int*)(0x424A5198UL))\r
+#define bFM3_BT6_RT_TMCR_T32                   *((volatile unsigned int*)(0x424A519CUL))\r
+#define bFM3_BT6_RT_TMCR_EGS0                  *((volatile unsigned int*)(0x424A51A0UL))\r
+#define bFM3_BT6_RT_TMCR_EGS1                  *((volatile unsigned int*)(0x424A51A4UL))\r
+#define bFM3_BT6_RT_TMCR_CKS0                  *((volatile unsigned int*)(0x424A51B0UL))\r
+#define bFM3_BT6_RT_TMCR_CKS1                  *((volatile unsigned int*)(0x424A51B4UL))\r
+#define bFM3_BT6_RT_TMCR_CKS2                  *((volatile unsigned int*)(0x424A51B8UL))\r
+#define bFM3_BT6_RT_STC_UDIR                   *((volatile unsigned int*)(0x424A5200UL))\r
+#define bFM3_BT6_RT_STC_TGIR                   *((volatile unsigned int*)(0x424A5208UL))\r
+#define bFM3_BT6_RT_STC_UDIE                   *((volatile unsigned int*)(0x424A5210UL))\r
+#define bFM3_BT6_RT_STC_TGIE                   *((volatile unsigned int*)(0x424A5218UL))\r
+#define bFM3_BT6_RT_TMCR2_CKS3                 *((volatile unsigned int*)(0x424A5220UL))\r
+\r
+/* Base Timer 6 PWC registers */\r
+#define bFM3_BT6_PWC_TMCR_CTEN                 *((volatile unsigned int*)(0x424A5184UL))\r
+#define bFM3_BT6_PWC_TMCR_MDSE                 *((volatile unsigned int*)(0x424A5188UL))\r
+#define bFM3_BT6_PWC_TMCR_FMD0                 *((volatile unsigned int*)(0x424A5190UL))\r
+#define bFM3_BT6_PWC_TMCR_FMD1                 *((volatile unsigned int*)(0x424A5194UL))\r
+#define bFM3_BT6_PWC_TMCR_FMD2                 *((volatile unsigned int*)(0x424A5198UL))\r
+#define bFM3_BT6_PWC_TMCR_T32                  *((volatile unsigned int*)(0x424A519CUL))\r
+#define bFM3_BT6_PWC_TMCR_EGS0                 *((volatile unsigned int*)(0x424A51A0UL))\r
+#define bFM3_BT6_PWC_TMCR_EGS1                 *((volatile unsigned int*)(0x424A51A4UL))\r
+#define bFM3_BT6_PWC_TMCR_EGS2                 *((volatile unsigned int*)(0x424A51A8UL))\r
+#define bFM3_BT6_PWC_TMCR_CKS0                 *((volatile unsigned int*)(0x424A51B0UL))\r
+#define bFM3_BT6_PWC_TMCR_CKS1                 *((volatile unsigned int*)(0x424A51B4UL))\r
+#define bFM3_BT6_PWC_TMCR_CKS2                 *((volatile unsigned int*)(0x424A51B8UL))\r
+#define bFM3_BT6_PWC_STC_OVIR                  *((volatile unsigned int*)(0x424A5200UL))\r
+#define bFM3_BT6_PWC_STC_EDIR                  *((volatile unsigned int*)(0x424A5208UL))\r
+#define bFM3_BT6_PWC_STC_OVIE                  *((volatile unsigned int*)(0x424A5210UL))\r
+#define bFM3_BT6_PWC_STC_EDIE                  *((volatile unsigned int*)(0x424A5218UL))\r
+#define bFM3_BT6_PWC_STC_ERR                   *((volatile unsigned int*)(0x424A521CUL))\r
+#define bFM3_BT6_PWC_TMCR2_CKS3                *((volatile unsigned int*)(0x424A5220UL))\r
+\r
+/* Base Timer 7 PPG registers */\r
+#define bFM3_BT7_PPG_TMCR_STRG                 *((volatile unsigned int*)(0x424A5980UL))\r
+#define bFM3_BT7_PPG_TMCR_CTEN                 *((volatile unsigned int*)(0x424A5984UL))\r
+#define bFM3_BT7_PPG_TMCR_MDSE                 *((volatile unsigned int*)(0x424A5988UL))\r
+#define bFM3_BT7_PPG_TMCR_OSEL                 *((volatile unsigned int*)(0x424A598CUL))\r
+#define bFM3_BT7_PPG_TMCR_FMD0                 *((volatile unsigned int*)(0x424A5990UL))\r
+#define bFM3_BT7_PPG_TMCR_FMD1                 *((volatile unsigned int*)(0x424A5994UL))\r
+#define bFM3_BT7_PPG_TMCR_FMD2                 *((volatile unsigned int*)(0x424A5998UL))\r
+#define bFM3_BT7_PPG_TMCR_EGS0                 *((volatile unsigned int*)(0x424A59A0UL))\r
+#define bFM3_BT7_PPG_TMCR_EGS1                 *((volatile unsigned int*)(0x424A59A4UL))\r
+#define bFM3_BT7_PPG_TMCR_PMSK                 *((volatile unsigned int*)(0x424A59A8UL))\r
+#define bFM3_BT7_PPG_TMCR_RTGEN                *((volatile unsigned int*)(0x424A59ACUL))\r
+#define bFM3_BT7_PPG_TMCR_CKS0                 *((volatile unsigned int*)(0x424A59B0UL))\r
+#define bFM3_BT7_PPG_TMCR_CKS1                 *((volatile unsigned int*)(0x424A59B4UL))\r
+#define bFM3_BT7_PPG_TMCR_CKS2                 *((volatile unsigned int*)(0x424A59B8UL))\r
+#define bFM3_BT7_PPG_STC_UDIR                  *((volatile unsigned int*)(0x424A5A00UL))\r
+#define bFM3_BT7_PPG_STC_TGIR                  *((volatile unsigned int*)(0x424A5A08UL))\r
+#define bFM3_BT7_PPG_STC_UDIE                  *((volatile unsigned int*)(0x424A5A10UL))\r
+#define bFM3_BT7_PPG_STC_TGIE                  *((volatile unsigned int*)(0x424A5A18UL))\r
+#define bFM3_BT7_PPG_TMCR2_CKS3                *((volatile unsigned int*)(0x424A5A20UL))\r
+\r
+/* Base Timer 7 PWM registers */\r
+#define bFM3_BT7_PWM_TMCR_STRG                 *((volatile unsigned int*)(0x424A5980UL))\r
+#define bFM3_BT7_PWM_TMCR_CTEN                 *((volatile unsigned int*)(0x424A5984UL))\r
+#define bFM3_BT7_PWM_TMCR_MDSE                 *((volatile unsigned int*)(0x424A5988UL))\r
+#define bFM3_BT7_PWM_TMCR_OSEL                 *((volatile unsigned int*)(0x424A598CUL))\r
+#define bFM3_BT7_PWM_TMCR_FMD0                 *((volatile unsigned int*)(0x424A5990UL))\r
+#define bFM3_BT7_PWM_TMCR_FMD1                 *((volatile unsigned int*)(0x424A5994UL))\r
+#define bFM3_BT7_PWM_TMCR_FMD2                 *((volatile unsigned int*)(0x424A5998UL))\r
+#define bFM3_BT7_PWM_TMCR_EGS0                 *((volatile unsigned int*)(0x424A59A0UL))\r
+#define bFM3_BT7_PWM_TMCR_EGS1                 *((volatile unsigned int*)(0x424A59A4UL))\r
+#define bFM3_BT7_PWM_TMCR_PMSK                 *((volatile unsigned int*)(0x424A59A8UL))\r
+#define bFM3_BT7_PWM_TMCR_RTGEN                *((volatile unsigned int*)(0x424A59ACUL))\r
+#define bFM3_BT7_PWM_TMCR_CKS0                 *((volatile unsigned int*)(0x424A59B0UL))\r
+#define bFM3_BT7_PWM_TMCR_CKS1                 *((volatile unsigned int*)(0x424A59B4UL))\r
+#define bFM3_BT7_PWM_TMCR_CKS2                 *((volatile unsigned int*)(0x424A59B8UL))\r
+#define bFM3_BT7_PWM_STC_UDIR                  *((volatile unsigned int*)(0x424A5A00UL))\r
+#define bFM3_BT7_PWM_STC_DTIR                  *((volatile unsigned int*)(0x424A5A04UL))\r
+#define bFM3_BT7_PWM_STC_TGIR                  *((volatile unsigned int*)(0x424A5A08UL))\r
+#define bFM3_BT7_PWM_STC_UDIE                  *((volatile unsigned int*)(0x424A5A10UL))\r
+#define bFM3_BT7_PWM_STC_DTIE                  *((volatile unsigned int*)(0x424A5A14UL))\r
+#define bFM3_BT7_PWM_STC_TGIE                  *((volatile unsigned int*)(0x424A5A18UL))\r
+#define bFM3_BT7_PWM_TMCR2_CKS3                *((volatile unsigned int*)(0x424A5A20UL))\r
+\r
+/* Base Timer 7 RT registers */\r
+#define bFM3_BT7_RT_TMCR_STRG                  *((volatile unsigned int*)(0x424A5980UL))\r
+#define bFM3_BT7_RT_TMCR_CTEN                  *((volatile unsigned int*)(0x424A5984UL))\r
+#define bFM3_BT7_RT_TMCR_MDSE                  *((volatile unsigned int*)(0x424A5988UL))\r
+#define bFM3_BT7_RT_TMCR_OSEL                  *((volatile unsigned int*)(0x424A598CUL))\r
+#define bFM3_BT7_RT_TMCR_FMD0                  *((volatile unsigned int*)(0x424A5990UL))\r
+#define bFM3_BT7_RT_TMCR_FMD1                  *((volatile unsigned int*)(0x424A5994UL))\r
+#define bFM3_BT7_RT_TMCR_FMD2                  *((volatile unsigned int*)(0x424A5998UL))\r
+#define bFM3_BT7_RT_TMCR_T32                   *((volatile unsigned int*)(0x424A599CUL))\r
+#define bFM3_BT7_RT_TMCR_EGS0                  *((volatile unsigned int*)(0x424A59A0UL))\r
+#define bFM3_BT7_RT_TMCR_EGS1                  *((volatile unsigned int*)(0x424A59A4UL))\r
+#define bFM3_BT7_RT_TMCR_CKS0                  *((volatile unsigned int*)(0x424A59B0UL))\r
+#define bFM3_BT7_RT_TMCR_CKS1                  *((volatile unsigned int*)(0x424A59B4UL))\r
+#define bFM3_BT7_RT_TMCR_CKS2                  *((volatile unsigned int*)(0x424A59B8UL))\r
+#define bFM3_BT7_RT_STC_UDIR                   *((volatile unsigned int*)(0x424A5A00UL))\r
+#define bFM3_BT7_RT_STC_TGIR                   *((volatile unsigned int*)(0x424A5A08UL))\r
+#define bFM3_BT7_RT_STC_UDIE                   *((volatile unsigned int*)(0x424A5A10UL))\r
+#define bFM3_BT7_RT_STC_TGIE                   *((volatile unsigned int*)(0x424A5A18UL))\r
+#define bFM3_BT7_RT_TMCR2_CKS3                 *((volatile unsigned int*)(0x424A5A20UL))\r
+\r
+/* Base Timer 7 PWC registers */\r
+#define bFM3_BT7_PWC_TMCR_CTEN                 *((volatile unsigned int*)(0x424A5984UL))\r
+#define bFM3_BT7_PWC_TMCR_MDSE                 *((volatile unsigned int*)(0x424A5988UL))\r
+#define bFM3_BT7_PWC_TMCR_FMD0                 *((volatile unsigned int*)(0x424A5990UL))\r
+#define bFM3_BT7_PWC_TMCR_FMD1                 *((volatile unsigned int*)(0x424A5994UL))\r
+#define bFM3_BT7_PWC_TMCR_FMD2                 *((volatile unsigned int*)(0x424A5998UL))\r
+#define bFM3_BT7_PWC_TMCR_T32                  *((volatile unsigned int*)(0x424A599CUL))\r
+#define bFM3_BT7_PWC_TMCR_EGS0                 *((volatile unsigned int*)(0x424A59A0UL))\r
+#define bFM3_BT7_PWC_TMCR_EGS1                 *((volatile unsigned int*)(0x424A59A4UL))\r
+#define bFM3_BT7_PWC_TMCR_EGS2                 *((volatile unsigned int*)(0x424A59A8UL))\r
+#define bFM3_BT7_PWC_TMCR_CKS0                 *((volatile unsigned int*)(0x424A59B0UL))\r
+#define bFM3_BT7_PWC_TMCR_CKS1                 *((volatile unsigned int*)(0x424A59B4UL))\r
+#define bFM3_BT7_PWC_TMCR_CKS2                 *((volatile unsigned int*)(0x424A59B8UL))\r
+#define bFM3_BT7_PWC_STC_OVIR                  *((volatile unsigned int*)(0x424A5A00UL))\r
+#define bFM3_BT7_PWC_STC_EDIR                  *((volatile unsigned int*)(0x424A5A08UL))\r
+#define bFM3_BT7_PWC_STC_OVIE                  *((volatile unsigned int*)(0x424A5A10UL))\r
+#define bFM3_BT7_PWC_STC_EDIE                  *((volatile unsigned int*)(0x424A5A18UL))\r
+#define bFM3_BT7_PWC_STC_ERR                   *((volatile unsigned int*)(0x424A5A1CUL))\r
+#define bFM3_BT7_PWC_TMCR2_CKS3                *((volatile unsigned int*)(0x424A5A20UL))\r
+\r
+/* Base Timer I/O selector channel 0 - channel 3 registers */\r
+#define bFM3_BTIOSEL03_BTSEL0123_SEL01_0       *((volatile unsigned int*)(0x424A2020UL))\r
+#define bFM3_BTIOSEL03_BTSEL0123_SEL01_1       *((volatile unsigned int*)(0x424A2024UL))\r
+#define bFM3_BTIOSEL03_BTSEL0123_SEL01_2       *((volatile unsigned int*)(0x424A2028UL))\r
+#define bFM3_BTIOSEL03_BTSEL0123_SEL01_3       *((volatile unsigned int*)(0x424A202CUL))\r
+#define bFM3_BTIOSEL03_BTSEL0123_SEL23_0       *((volatile unsigned int*)(0x424A2030UL))\r
+#define bFM3_BTIOSEL03_BTSEL0123_SEL23_1       *((volatile unsigned int*)(0x424A2034UL))\r
+#define bFM3_BTIOSEL03_BTSEL0123_SEL23_2       *((volatile unsigned int*)(0x424A2038UL))\r
+#define bFM3_BTIOSEL03_BTSEL0123_SEL23_3       *((volatile unsigned int*)(0x424A203CUL))\r
+\r
+/* Base Timer I/O selector channel 4 - channel 7 registers */\r
+#define bFM3_BTIOSEL47_BTSEL4567_SEL45_0       *((volatile unsigned int*)(0x424A6020UL))\r
+#define bFM3_BTIOSEL47_BTSEL4567_SEL45_1       *((volatile unsigned int*)(0x424A6024UL))\r
+#define bFM3_BTIOSEL47_BTSEL4567_SEL45_2       *((volatile unsigned int*)(0x424A6028UL))\r
+#define bFM3_BTIOSEL47_BTSEL4567_SEL45_3       *((volatile unsigned int*)(0x424A602CUL))\r
+#define bFM3_BTIOSEL47_BTSEL4567_SEL67_0       *((volatile unsigned int*)(0x424A6030UL))\r
+#define bFM3_BTIOSEL47_BTSEL4567_SEL67_1       *((volatile unsigned int*)(0x424A6034UL))\r
+#define bFM3_BTIOSEL47_BTSEL4567_SEL67_2       *((volatile unsigned int*)(0x424A6038UL))\r
+#define bFM3_BTIOSEL47_BTSEL4567_SEL67_3       *((volatile unsigned int*)(0x424A603CUL))\r
+\r
+/* Software based Simulation Startup (Base Timer) register */\r
+#define bFM3_SBSSR_BTSSSR_SSR0                 *((volatile unsigned int*)(0x424BFF80UL))\r
+#define bFM3_SBSSR_BTSSSR_SSR1                 *((volatile unsigned int*)(0x424BFF84UL))\r
+#define bFM3_SBSSR_BTSSSR_SSR2                 *((volatile unsigned int*)(0x424BFF88UL))\r
+#define bFM3_SBSSR_BTSSSR_SSR3                 *((volatile unsigned int*)(0x424BFF8CUL))\r
+#define bFM3_SBSSR_BTSSSR_SSR4                 *((volatile unsigned int*)(0x424BFF90UL))\r
+#define bFM3_SBSSR_BTSSSR_SSR5                 *((volatile unsigned int*)(0x424BFF94UL))\r
+#define bFM3_SBSSR_BTSSSR_SSR6                 *((volatile unsigned int*)(0x424BFF98UL))\r
+#define bFM3_SBSSR_BTSSSR_SSR7                 *((volatile unsigned int*)(0x424BFF9CUL))\r
+#define bFM3_SBSSR_BTSSSR_SSR8                 *((volatile unsigned int*)(0x424BFFA0UL))\r
+#define bFM3_SBSSR_BTSSSR_SSR9                 *((volatile unsigned int*)(0x424BFFA4UL))\r
+#define bFM3_SBSSR_BTSSSR_SSR10                *((volatile unsigned int*)(0x424BFFA8UL))\r
+#define bFM3_SBSSR_BTSSSR_SSR11                *((volatile unsigned int*)(0x424BFFACUL))\r
+#define bFM3_SBSSR_BTSSSR_SSR12                *((volatile unsigned int*)(0x424BFFB0UL))\r
+#define bFM3_SBSSR_BTSSSR_SSR13                *((volatile unsigned int*)(0x424BFFB4UL))\r
+#define bFM3_SBSSR_BTSSSR_SSR14                *((volatile unsigned int*)(0x424BFFB8UL))\r
+#define bFM3_SBSSR_BTSSSR_SSR15                *((volatile unsigned int*)(0x424BFFBCUL))\r
+\r
+/* Quad position and revolution counter channel 0 registers */\r
+#define bFM3_QPRC0_QICR_QPCMIE                 *((volatile unsigned int*)(0x424C0280UL))\r
+#define bFM3_QPRC0_QICR_QPCMF                  *((volatile unsigned int*)(0x424C0284UL))\r
+#define bFM3_QPRC0_QICR_QPRCMIE                *((volatile unsigned int*)(0x424C0288UL))\r
+#define bFM3_QPRC0_QICR_QPRCMF                 *((volatile unsigned int*)(0x424C028CUL))\r
+#define bFM3_QPRC0_QICR_OUZIE                  *((volatile unsigned int*)(0x424C0290UL))\r
+#define bFM3_QPRC0_QICR_UFDF                   *((volatile unsigned int*)(0x424C0294UL))\r
+#define bFM3_QPRC0_QICR_OFDF                   *((volatile unsigned int*)(0x424C0298UL))\r
+#define bFM3_QPRC0_QICR_ZIIF                   *((volatile unsigned int*)(0x424C029CUL))\r
+#define bFM3_QPRC0_QICR_CDCIE                  *((volatile unsigned int*)(0x424C02A0UL))\r
+#define bFM3_QPRC0_QICR_CDCF                   *((volatile unsigned int*)(0x424C02A4UL))\r
+#define bFM3_QPRC0_QICR_DIRPC                  *((volatile unsigned int*)(0x424C02A8UL))\r
+#define bFM3_QPRC0_QICR_DIROU                  *((volatile unsigned int*)(0x424C02ACUL))\r
+#define bFM3_QPRC0_QICR_QPCNRCMIE              *((volatile unsigned int*)(0x424C02B0UL))\r
+#define bFM3_QPRC0_QICR_QPCNRCMF               *((volatile unsigned int*)(0x424C02B4UL))\r
+#define bFM3_QPRC0_QICRL_QPCMIE                *((volatile unsigned int*)(0x424C0280UL))\r
+#define bFM3_QPRC0_QICRL_QPCMF                 *((volatile unsigned int*)(0x424C0284UL))\r
+#define bFM3_QPRC0_QICRL_QPRCMIE               *((volatile unsigned int*)(0x424C0288UL))\r
+#define bFM3_QPRC0_QICRL_QPRCMF                *((volatile unsigned int*)(0x424C028CUL))\r
+#define bFM3_QPRC0_QICRL_OUZIE                 *((volatile unsigned int*)(0x424C0290UL))\r
+#define bFM3_QPRC0_QICRL_UFDF                  *((volatile unsigned int*)(0x424C0294UL))\r
+#define bFM3_QPRC0_QICRL_OFDF                  *((volatile unsigned int*)(0x424C0298UL))\r
+#define bFM3_QPRC0_QICRL_ZIIF                  *((volatile unsigned int*)(0x424C029CUL))\r
+#define bFM3_QPRC0_QICRH_CDCIE                 *((volatile unsigned int*)(0x424C02A0UL))\r
+#define bFM3_QPRC0_QICRH_CDCF                  *((volatile unsigned int*)(0x424C02A4UL))\r
+#define bFM3_QPRC0_QICRH_DIRPC                 *((volatile unsigned int*)(0x424C02A8UL))\r
+#define bFM3_QPRC0_QICRH_DIROU                 *((volatile unsigned int*)(0x424C02ACUL))\r
+#define bFM3_QPRC0_QICRH_QPCNRCMIE             *((volatile unsigned int*)(0x424C02B0UL))\r
+#define bFM3_QPRC0_QICRH_QPCNRCMF              *((volatile unsigned int*)(0x424C02B4UL))\r
+#define bFM3_QPRC0_QCR_PCM0                    *((volatile unsigned int*)(0x424C0300UL))\r
+#define bFM3_QPRC0_QCR_PCM1                    *((volatile unsigned int*)(0x424C0304UL))\r
+#define bFM3_QPRC0_QCR_RCM0                    *((volatile unsigned int*)(0x424C0308UL))\r
+#define bFM3_QPRC0_QCR_RCM1                    *((volatile unsigned int*)(0x424C030CUL))\r
+#define bFM3_QPRC0_QCR_PSTP                    *((volatile unsigned int*)(0x424C0310UL))\r
+#define bFM3_QPRC0_QCR_CGSC                    *((volatile unsigned int*)(0x424C0314UL))\r
+#define bFM3_QPRC0_QCR_RSEL                    *((volatile unsigned int*)(0x424C0318UL))\r
+#define bFM3_QPRC0_QCR_SWAP                    *((volatile unsigned int*)(0x424C031CUL))\r
+#define bFM3_QPRC0_QCR_PCRM0                   *((volatile unsigned int*)(0x424C0320UL))\r
+#define bFM3_QPRC0_QCR_PCRM1                   *((volatile unsigned int*)(0x424C0324UL))\r
+#define bFM3_QPRC0_QCR_AES0                    *((volatile unsigned int*)(0x424C0328UL))\r
+#define bFM3_QPRC0_QCR_AES1                    *((volatile unsigned int*)(0x424C032CUL))\r
+#define bFM3_QPRC0_QCR_BES0                    *((volatile unsigned int*)(0x424C0330UL))\r
+#define bFM3_QPRC0_QCR_BES1                    *((volatile unsigned int*)(0x424C0334UL))\r
+#define bFM3_QPRC0_QCR_CGE0                    *((volatile unsigned int*)(0x424C0338UL))\r
+#define bFM3_QPRC0_QCR_CGE1                    *((volatile unsigned int*)(0x424C033CUL))\r
+#define bFM3_QPRC0_QCRL_PCM0                   *((volatile unsigned int*)(0x424C0300UL))\r
+#define bFM3_QPRC0_QCRL_PCM1                   *((volatile unsigned int*)(0x424C0304UL))\r
+#define bFM3_QPRC0_QCRL_RCM0                   *((volatile unsigned int*)(0x424C0308UL))\r
+#define bFM3_QPRC0_QCRL_RCM1                   *((volatile unsigned int*)(0x424C030CUL))\r
+#define bFM3_QPRC0_QCRL_PSTP                   *((volatile unsigned int*)(0x424C0310UL))\r
+#define bFM3_QPRC0_QCRL_CGSC                   *((volatile unsigned int*)(0x424C0314UL))\r
+#define bFM3_QPRC0_QCRL_RSEL                   *((volatile unsigned int*)(0x424C0318UL))\r
+#define bFM3_QPRC0_QCRL_SWAP                   *((volatile unsigned int*)(0x424C031CUL))\r
+#define bFM3_QPRC0_QCRH_PCRM0                  *((volatile unsigned int*)(0x424C0320UL))\r
+#define bFM3_QPRC0_QCRH_PCRM1                  *((volatile unsigned int*)(0x424C0324UL))\r
+#define bFM3_QPRC0_QCRH_AES0                   *((volatile unsigned int*)(0x424C0328UL))\r
+#define bFM3_QPRC0_QCRH_AES1                   *((volatile unsigned int*)(0x424C032CUL))\r
+#define bFM3_QPRC0_QCRH_BES0                   *((volatile unsigned int*)(0x424C0330UL))\r
+#define bFM3_QPRC0_QCRH_BES1                   *((volatile unsigned int*)(0x424C0334UL))\r
+#define bFM3_QPRC0_QCRH_CGE0                   *((volatile unsigned int*)(0x424C0338UL))\r
+#define bFM3_QPRC0_QCRH_CGE1                   *((volatile unsigned int*)(0x424C033CUL))\r
+#define bFM3_QPRC0_QECR_ORNGMD                 *((volatile unsigned int*)(0x424C0380UL))\r
+#define bFM3_QPRC0_QECR_ORNGF                  *((volatile unsigned int*)(0x424C0384UL))\r
+#define bFM3_QPRC0_QECR_ORNGIE                 *((volatile unsigned int*)(0x424C0388UL))\r
+\r
+/* Quad position and revolution counter channel 1 registers */\r
+#define bFM3_QPRC1_QICR_QPCMIE                 *((volatile unsigned int*)(0x424C0A80UL))\r
+#define bFM3_QPRC1_QICR_QPCMF                  *((volatile unsigned int*)(0x424C0A84UL))\r
+#define bFM3_QPRC1_QICR_QPRCMIE                *((volatile unsigned int*)(0x424C0A88UL))\r
+#define bFM3_QPRC1_QICR_QPRCMF                 *((volatile unsigned int*)(0x424C0A8CUL))\r
+#define bFM3_QPRC1_QICR_OUZIE                  *((volatile unsigned int*)(0x424C0A90UL))\r
+#define bFM3_QPRC1_QICR_UFDF                   *((volatile unsigned int*)(0x424C0A94UL))\r
+#define bFM3_QPRC1_QICR_OFDF                   *((volatile unsigned int*)(0x424C0A98UL))\r
+#define bFM3_QPRC1_QICR_ZIIF                   *((volatile unsigned int*)(0x424C0A9CUL))\r
+#define bFM3_QPRC1_QICR_CDCIE                  *((volatile unsigned int*)(0x424C0AA0UL))\r
+#define bFM3_QPRC1_QICR_CDCF                   *((volatile unsigned int*)(0x424C0AA4UL))\r
+#define bFM3_QPRC1_QICR_DIRPC                  *((volatile unsigned int*)(0x424C0AA8UL))\r
+#define bFM3_QPRC1_QICR_DIROU                  *((volatile unsigned int*)(0x424C0AACUL))\r
+#define bFM3_QPRC1_QICR_QPCNRCMIE              *((volatile unsigned int*)(0x424C0AB0UL))\r
+#define bFM3_QPRC1_QICR_QPCNRCMF               *((volatile unsigned int*)(0x424C0AB4UL))\r
+#define bFM3_QPRC1_QICRL_QPCMIE                *((volatile unsigned int*)(0x424C0A80UL))\r
+#define bFM3_QPRC1_QICRL_QPCMF                 *((volatile unsigned int*)(0x424C0A84UL))\r
+#define bFM3_QPRC1_QICRL_QPRCMIE               *((volatile unsigned int*)(0x424C0A88UL))\r
+#define bFM3_QPRC1_QICRL_QPRCMF                *((volatile unsigned int*)(0x424C0A8CUL))\r
+#define bFM3_QPRC1_QICRL_OUZIE                 *((volatile unsigned int*)(0x424C0A90UL))\r
+#define bFM3_QPRC1_QICRL_UFDF                  *((volatile unsigned int*)(0x424C0A94UL))\r
+#define bFM3_QPRC1_QICRL_OFDF                  *((volatile unsigned int*)(0x424C0A98UL))\r
+#define bFM3_QPRC1_QICRL_ZIIF                  *((volatile unsigned int*)(0x424C0A9CUL))\r
+#define bFM3_QPRC1_QICRH_CDCIE                 *((volatile unsigned int*)(0x424C0AA0UL))\r
+#define bFM3_QPRC1_QICRH_CDCF                  *((volatile unsigned int*)(0x424C0AA4UL))\r
+#define bFM3_QPRC1_QICRH_DIRPC                 *((volatile unsigned int*)(0x424C0AA8UL))\r
+#define bFM3_QPRC1_QICRH_DIROU                 *((volatile unsigned int*)(0x424C0AACUL))\r
+#define bFM3_QPRC1_QICRH_QPCNRCMIE             *((volatile unsigned int*)(0x424C0AB0UL))\r
+#define bFM3_QPRC1_QICRH_QPCNRCMF              *((volatile unsigned int*)(0x424C0AB4UL))\r
+#define bFM3_QPRC1_QCR_PCM0                    *((volatile unsigned int*)(0x424C0B00UL))\r
+#define bFM3_QPRC1_QCR_PCM1                    *((volatile unsigned int*)(0x424C0B04UL))\r
+#define bFM3_QPRC1_QCR_RCM0                    *((volatile unsigned int*)(0x424C0B08UL))\r
+#define bFM3_QPRC1_QCR_RCM1                    *((volatile unsigned int*)(0x424C0B0CUL))\r
+#define bFM3_QPRC1_QCR_PSTP                    *((volatile unsigned int*)(0x424C0B10UL))\r
+#define bFM3_QPRC1_QCR_CGSC                    *((volatile unsigned int*)(0x424C0B14UL))\r
+#define bFM3_QPRC1_QCR_RSEL                    *((volatile unsigned int*)(0x424C0B18UL))\r
+#define bFM3_QPRC1_QCR_SWAP                    *((volatile unsigned int*)(0x424C0B1CUL))\r
+#define bFM3_QPRC1_QCR_PCRM0                   *((volatile unsigned int*)(0x424C0B20UL))\r
+#define bFM3_QPRC1_QCR_PCRM1                   *((volatile unsigned int*)(0x424C0B24UL))\r
+#define bFM3_QPRC1_QCR_AES0                    *((volatile unsigned int*)(0x424C0B28UL))\r
+#define bFM3_QPRC1_QCR_AES1                    *((volatile unsigned int*)(0x424C0B2CUL))\r
+#define bFM3_QPRC1_QCR_BES0                    *((volatile unsigned int*)(0x424C0B30UL))\r
+#define bFM3_QPRC1_QCR_BES1                    *((volatile unsigned int*)(0x424C0B34UL))\r
+#define bFM3_QPRC1_QCR_CGE0                    *((volatile unsigned int*)(0x424C0B38UL))\r
+#define bFM3_QPRC1_QCR_CGE1                    *((volatile unsigned int*)(0x424C0B3CUL))\r
+#define bFM3_QPRC1_QCRL_PCM0                   *((volatile unsigned int*)(0x424C0B00UL))\r
+#define bFM3_QPRC1_QCRL_PCM1                   *((volatile unsigned int*)(0x424C0B04UL))\r
+#define bFM3_QPRC1_QCRL_RCM0                   *((volatile unsigned int*)(0x424C0B08UL))\r
+#define bFM3_QPRC1_QCRL_RCM1                   *((volatile unsigned int*)(0x424C0B0CUL))\r
+#define bFM3_QPRC1_QCRL_PSTP                   *((volatile unsigned int*)(0x424C0B10UL))\r
+#define bFM3_QPRC1_QCRL_CGSC                   *((volatile unsigned int*)(0x424C0B14UL))\r
+#define bFM3_QPRC1_QCRL_RSEL                   *((volatile unsigned int*)(0x424C0B18UL))\r
+#define bFM3_QPRC1_QCRL_SWAP                   *((volatile unsigned int*)(0x424C0B1CUL))\r
+#define bFM3_QPRC1_QCRH_PCRM0                  *((volatile unsigned int*)(0x424C0B20UL))\r
+#define bFM3_QPRC1_QCRH_PCRM1                  *((volatile unsigned int*)(0x424C0B24UL))\r
+#define bFM3_QPRC1_QCRH_AES0                   *((volatile unsigned int*)(0x424C0B28UL))\r
+#define bFM3_QPRC1_QCRH_AES1                   *((volatile unsigned int*)(0x424C0B2CUL))\r
+#define bFM3_QPRC1_QCRH_BES0                   *((volatile unsigned int*)(0x424C0B30UL))\r
+#define bFM3_QPRC1_QCRH_BES1                   *((volatile unsigned int*)(0x424C0B34UL))\r
+#define bFM3_QPRC1_QCRH_CGE0                   *((volatile unsigned int*)(0x424C0B38UL))\r
+#define bFM3_QPRC1_QCRH_CGE1                   *((volatile unsigned int*)(0x424C0B3CUL))\r
+#define bFM3_QPRC1_QECR_ORNGMD                 *((volatile unsigned int*)(0x424C0B80UL))\r
+#define bFM3_QPRC1_QECR_ORNGF                  *((volatile unsigned int*)(0x424C0B84UL))\r
+#define bFM3_QPRC1_QECR_ORNGIE                 *((volatile unsigned int*)(0x424C0B88UL))\r
+\r
+/* 12-bit ADC unit 0 registers */\r
+#define bFM3_ADC0_ADSR_SCS                     *((volatile unsigned int*)(0x424E0000UL))\r
+#define bFM3_ADC0_ADSR_PCS                     *((volatile unsigned int*)(0x424E0004UL))\r
+#define bFM3_ADC0_ADSR_PCNS                    *((volatile unsigned int*)(0x424E0008UL))\r
+#define bFM3_ADC0_ADSR_FDAS                    *((volatile unsigned int*)(0x424E0018UL))\r
+#define bFM3_ADC0_ADSR_ADSTP                   *((volatile unsigned int*)(0x424E001CUL))\r
+#define bFM3_ADC0_ADCR_OVRIE                   *((volatile unsigned int*)(0x424E0020UL))\r
+#define bFM3_ADC0_ADCR_CMPIE                   *((volatile unsigned int*)(0x424E0024UL))\r
+#define bFM3_ADC0_ADCR_PCIE                    *((volatile unsigned int*)(0x424E0028UL))\r
+#define bFM3_ADC0_ADCR_SCIE                    *((volatile unsigned int*)(0x424E002CUL))\r
+#define bFM3_ADC0_ADCR_CMPIF                   *((volatile unsigned int*)(0x424E0034UL))\r
+#define bFM3_ADC0_ADCR_PCIF                    *((volatile unsigned int*)(0x424E0038UL))\r
+#define bFM3_ADC0_ADCR_SCIF                    *((volatile unsigned int*)(0x424E003CUL))\r
+#define bFM3_ADC0_SFNS_SFS0                    *((volatile unsigned int*)(0x424E0100UL))\r
+#define bFM3_ADC0_SFNS_SFS1                    *((volatile unsigned int*)(0x424E0104UL))\r
+#define bFM3_ADC0_SFNS_SFS2                    *((volatile unsigned int*)(0x424E0108UL))\r
+#define bFM3_ADC0_SFNS_SFS3                    *((volatile unsigned int*)(0x424E010CUL))\r
+#define bFM3_ADC0_SCCR_SSTR                    *((volatile unsigned int*)(0x424E0120UL))\r
+#define bFM3_ADC0_SCCR_SHEN                    *((volatile unsigned int*)(0x424E0124UL))\r
+#define bFM3_ADC0_SCCR_RPT                     *((volatile unsigned int*)(0x424E0128UL))\r
+#define bFM3_ADC0_SCCR_SFCLR                   *((volatile unsigned int*)(0x424E0130UL))\r
+#define bFM3_ADC0_SCCR_SOVR                    *((volatile unsigned int*)(0x424E0134UL))\r
+#define bFM3_ADC0_SCCR_SFUL                    *((volatile unsigned int*)(0x424E0138UL))\r
+#define bFM3_ADC0_SCCR_SEMP                    *((volatile unsigned int*)(0x424E013CUL))\r
+#define bFM3_ADC0_SCFD_SC0                     *((volatile unsigned int*)(0x424E0180UL))\r
+#define bFM3_ADC0_SCFD_SC1                     *((volatile unsigned int*)(0x424E0184UL))\r
+#define bFM3_ADC0_SCFD_SC2                     *((volatile unsigned int*)(0x424E0188UL))\r
+#define bFM3_ADC0_SCFD_SC3                     *((volatile unsigned int*)(0x424E018CUL))\r
+#define bFM3_ADC0_SCFD_SC4                     *((volatile unsigned int*)(0x424E0190UL))\r
+#define bFM3_ADC0_SCFD_RS0                     *((volatile unsigned int*)(0x424E01A0UL))\r
+#define bFM3_ADC0_SCFD_RS1                     *((volatile unsigned int*)(0x424E01A4UL))\r
+#define bFM3_ADC0_SCFD_INVL                    *((volatile unsigned int*)(0x424E01B0UL))\r
+#define bFM3_ADC0_SCFD_SD0                     *((volatile unsigned int*)(0x424E01D0UL))\r
+#define bFM3_ADC0_SCFD_SD1                     *((volatile unsigned int*)(0x424E01D4UL))\r
+#define bFM3_ADC0_SCFD_SD2                     *((volatile unsigned int*)(0x424E01D8UL))\r
+#define bFM3_ADC0_SCFD_SD3                     *((volatile unsigned int*)(0x424E01DCUL))\r
+#define bFM3_ADC0_SCFD_SD4                     *((volatile unsigned int*)(0x424E01E0UL))\r
+#define bFM3_ADC0_SCFD_SD5                     *((volatile unsigned int*)(0x424E01E4UL))\r
+#define bFM3_ADC0_SCFD_SD6                     *((volatile unsigned int*)(0x424E01E8UL))\r
+#define bFM3_ADC0_SCFD_SD7                     *((volatile unsigned int*)(0x424E01ECUL))\r
+#define bFM3_ADC0_SCFD_SD8                     *((volatile unsigned int*)(0x424E01F0UL))\r
+#define bFM3_ADC0_SCFD_SD9                     *((volatile unsigned int*)(0x424E01F4UL))\r
+#define bFM3_ADC0_SCFD_SD10                    *((volatile unsigned int*)(0x424E01F8UL))\r
+#define bFM3_ADC0_SCFD_SD11                    *((volatile unsigned int*)(0x424E01FCUL))\r
+#define bFM3_ADC0_SCFDL_SC0                    *((volatile unsigned int*)(0x424E0180UL))\r
+#define bFM3_ADC0_SCFDL_SC1                    *((volatile unsigned int*)(0x424E0184UL))\r
+#define bFM3_ADC0_SCFDL_SC2                    *((volatile unsigned int*)(0x424E0188UL))\r
+#define bFM3_ADC0_SCFDL_SC3                    *((volatile unsigned int*)(0x424E018CUL))\r
+#define bFM3_ADC0_SCFDL_SC4                    *((volatile unsigned int*)(0x424E0190UL))\r
+#define bFM3_ADC0_SCFDL_RS0                    *((volatile unsigned int*)(0x424E01A0UL))\r
+#define bFM3_ADC0_SCFDL_RS1                    *((volatile unsigned int*)(0x424E01A4UL))\r
+#define bFM3_ADC0_SCFDL_INVL                   *((volatile unsigned int*)(0x424E01B0UL))\r
+#define bFM3_ADC0_SCFDH_SD0                    *((volatile unsigned int*)(0x424E01D0UL))\r
+#define bFM3_ADC0_SCFDH_SD1                    *((volatile unsigned int*)(0x424E01D4UL))\r
+#define bFM3_ADC0_SCFDH_SD2                    *((volatile unsigned int*)(0x424E01D8UL))\r
+#define bFM3_ADC0_SCFDH_SD3                    *((volatile unsigned int*)(0x424E01DCUL))\r
+#define bFM3_ADC0_SCFDH_SD4                    *((volatile unsigned int*)(0x424E01E0UL))\r
+#define bFM3_ADC0_SCFDH_SD5                    *((volatile unsigned int*)(0x424E01E4UL))\r
+#define bFM3_ADC0_SCFDH_SD6                    *((volatile unsigned int*)(0x424E01E8UL))\r
+#define bFM3_ADC0_SCFDH_SD7                    *((volatile unsigned int*)(0x424E01ECUL))\r
+#define bFM3_ADC0_SCFDH_SD8                    *((volatile unsigned int*)(0x424E01F0UL))\r
+#define bFM3_ADC0_SCFDH_SD9                    *((volatile unsigned int*)(0x424E01F4UL))\r
+#define bFM3_ADC0_SCFDH_SD10                   *((volatile unsigned int*)(0x424E01F8UL))\r
+#define bFM3_ADC0_SCFDH_SD11                   *((volatile unsigned int*)(0x424E01FCUL))\r
+#define bFM3_ADC0_SCIS23_AN16                  *((volatile unsigned int*)(0x424E0200UL))\r
+#define bFM3_ADC0_SCIS23_AN17                  *((volatile unsigned int*)(0x424E0204UL))\r
+#define bFM3_ADC0_SCIS23_AN18                  *((volatile unsigned int*)(0x424E0208UL))\r
+#define bFM3_ADC0_SCIS23_AN19                  *((volatile unsigned int*)(0x424E020CUL))\r
+#define bFM3_ADC0_SCIS23_AN20                  *((volatile unsigned int*)(0x424E0210UL))\r
+#define bFM3_ADC0_SCIS23_AN21                  *((volatile unsigned int*)(0x424E0214UL))\r
+#define bFM3_ADC0_SCIS23_AN22                  *((volatile unsigned int*)(0x424E0218UL))\r
+#define bFM3_ADC0_SCIS23_AN23                  *((volatile unsigned int*)(0x424E021CUL))\r
+#define bFM3_ADC0_SCIS23_AN24                  *((volatile unsigned int*)(0x424E0220UL))\r
+#define bFM3_ADC0_SCIS23_AN25                  *((volatile unsigned int*)(0x424E0224UL))\r
+#define bFM3_ADC0_SCIS23_AN26                  *((volatile unsigned int*)(0x424E0228UL))\r
+#define bFM3_ADC0_SCIS23_AN27                  *((volatile unsigned int*)(0x424E022CUL))\r
+#define bFM3_ADC0_SCIS23_AN28                  *((volatile unsigned int*)(0x424E0230UL))\r
+#define bFM3_ADC0_SCIS23_AN29                  *((volatile unsigned int*)(0x424E0234UL))\r
+#define bFM3_ADC0_SCIS23_AN30                  *((volatile unsigned int*)(0x424E0238UL))\r
+#define bFM3_ADC0_SCIS23_AN31                  *((volatile unsigned int*)(0x424E023CUL))\r
+#define bFM3_ADC0_SCIS2_AN16                   *((volatile unsigned int*)(0x424E0200UL))\r
+#define bFM3_ADC0_SCIS2_AN17                   *((volatile unsigned int*)(0x424E0204UL))\r
+#define bFM3_ADC0_SCIS2_AN18                   *((volatile unsigned int*)(0x424E0208UL))\r
+#define bFM3_ADC0_SCIS2_AN19                   *((volatile unsigned int*)(0x424E020CUL))\r
+#define bFM3_ADC0_SCIS2_AN20                   *((volatile unsigned int*)(0x424E0210UL))\r
+#define bFM3_ADC0_SCIS2_AN21                   *((volatile unsigned int*)(0x424E0214UL))\r
+#define bFM3_ADC0_SCIS2_AN22                   *((volatile unsigned int*)(0x424E0218UL))\r
+#define bFM3_ADC0_SCIS2_AN23                   *((volatile unsigned int*)(0x424E021CUL))\r
+#define bFM3_ADC0_SCIS3_AN24                   *((volatile unsigned int*)(0x424E0220UL))\r
+#define bFM3_ADC0_SCIS3_AN25                   *((volatile unsigned int*)(0x424E0224UL))\r
+#define bFM3_ADC0_SCIS3_AN26                   *((volatile unsigned int*)(0x424E0228UL))\r
+#define bFM3_ADC0_SCIS3_AN27                   *((volatile unsigned int*)(0x424E022CUL))\r
+#define bFM3_ADC0_SCIS3_AN28                   *((volatile unsigned int*)(0x424E0230UL))\r
+#define bFM3_ADC0_SCIS3_AN29                   *((volatile unsigned int*)(0x424E0234UL))\r
+#define bFM3_ADC0_SCIS3_AN30                   *((volatile unsigned int*)(0x424E0238UL))\r
+#define bFM3_ADC0_SCIS3_AN31                   *((volatile unsigned int*)(0x424E023CUL))\r
+#define bFM3_ADC0_SCIS01_AN0                   *((volatile unsigned int*)(0x424E0280UL))\r
+#define bFM3_ADC0_SCIS01_AN1                   *((volatile unsigned int*)(0x424E0284UL))\r
+#define bFM3_ADC0_SCIS01_AN2                   *((volatile unsigned int*)(0x424E0288UL))\r
+#define bFM3_ADC0_SCIS01_AN3                   *((volatile unsigned int*)(0x424E028CUL))\r
+#define bFM3_ADC0_SCIS01_AN4                   *((volatile unsigned int*)(0x424E0290UL))\r
+#define bFM3_ADC0_SCIS01_AN5                   *((volatile unsigned int*)(0x424E0294UL))\r
+#define bFM3_ADC0_SCIS01_AN6                   *((volatile unsigned int*)(0x424E0298UL))\r
+#define bFM3_ADC0_SCIS01_AN7                   *((volatile unsigned int*)(0x424E029CUL))\r
+#define bFM3_ADC0_SCIS01_AN8                   *((volatile unsigned int*)(0x424E02A0UL))\r
+#define bFM3_ADC0_SCIS01_AN9                   *((volatile unsigned int*)(0x424E02A4UL))\r
+#define bFM3_ADC0_SCIS01_AN10                  *((volatile unsigned int*)(0x424E02A8UL))\r
+#define bFM3_ADC0_SCIS01_AN11                  *((volatile unsigned int*)(0x424E02ACUL))\r
+#define bFM3_ADC0_SCIS01_AN12                  *((volatile unsigned int*)(0x424E02B0UL))\r
+#define bFM3_ADC0_SCIS01_AN13                  *((volatile unsigned int*)(0x424E02B4UL))\r
+#define bFM3_ADC0_SCIS01_AN14                  *((volatile unsigned int*)(0x424E02B8UL))\r
+#define bFM3_ADC0_SCIS01_AN15                  *((volatile unsigned int*)(0x424E02BCUL))\r
+#define bFM3_ADC0_SCIS0_AN0                    *((volatile unsigned int*)(0x424E0280UL))\r
+#define bFM3_ADC0_SCIS0_AN1                    *((volatile unsigned int*)(0x424E0284UL))\r
+#define bFM3_ADC0_SCIS0_AN2                    *((volatile unsigned int*)(0x424E0288UL))\r
+#define bFM3_ADC0_SCIS0_AN3                    *((volatile unsigned int*)(0x424E028CUL))\r
+#define bFM3_ADC0_SCIS0_AN4                    *((volatile unsigned int*)(0x424E0290UL))\r
+#define bFM3_ADC0_SCIS0_AN5                    *((volatile unsigned int*)(0x424E0294UL))\r
+#define bFM3_ADC0_SCIS0_AN6                    *((volatile unsigned int*)(0x424E0298UL))\r
+#define bFM3_ADC0_SCIS0_AN7                    *((volatile unsigned int*)(0x424E029CUL))\r
+#define bFM3_ADC0_SCIS1_AN8                    *((volatile unsigned int*)(0x424E02A0UL))\r
+#define bFM3_ADC0_SCIS1_AN9                    *((volatile unsigned int*)(0x424E02A4UL))\r
+#define bFM3_ADC0_SCIS1_AN10                   *((volatile unsigned int*)(0x424E02A8UL))\r
+#define bFM3_ADC0_SCIS1_AN11                   *((volatile unsigned int*)(0x424E02ACUL))\r
+#define bFM3_ADC0_SCIS1_AN12                   *((volatile unsigned int*)(0x424E02B0UL))\r
+#define bFM3_ADC0_SCIS1_AN13                   *((volatile unsigned int*)(0x424E02B4UL))\r
+#define bFM3_ADC0_SCIS1_AN14                   *((volatile unsigned int*)(0x424E02B8UL))\r
+#define bFM3_ADC0_SCIS1_AN15                   *((volatile unsigned int*)(0x424E02BCUL))\r
+#define bFM3_ADC0_PFNS_PFS0                    *((volatile unsigned int*)(0x424E0300UL))\r
+#define bFM3_ADC0_PFNS_PFS1                    *((volatile unsigned int*)(0x424E0304UL))\r
+#define bFM3_ADC0_PFNS_TEST0                   *((volatile unsigned int*)(0x424E0310UL))\r
+#define bFM3_ADC0_PFNS_TEST1                   *((volatile unsigned int*)(0x424E0314UL))\r
+#define bFM3_ADC0_PCCR_PSTR                    *((volatile unsigned int*)(0x424E0320UL))\r
+#define bFM3_ADC0_PCCR_PHEN                    *((volatile unsigned int*)(0x424E0324UL))\r
+#define bFM3_ADC0_PCCR_PEEN                    *((volatile unsigned int*)(0x424E0328UL))\r
+#define bFM3_ADC0_PCCR_ESCE                    *((volatile unsigned int*)(0x424E032CUL))\r
+#define bFM3_ADC0_PCCR_PFCLR                   *((volatile unsigned int*)(0x424E0330UL))\r
+#define bFM3_ADC0_PCCR_POVR                    *((volatile unsigned int*)(0x424E0334UL))\r
+#define bFM3_ADC0_PCCR_PFUL                    *((volatile unsigned int*)(0x424E0338UL))\r
+#define bFM3_ADC0_PCCR_PEMP                    *((volatile unsigned int*)(0x424E033CUL))\r
+#define bFM3_ADC0_PCFD_PC0                     *((volatile unsigned int*)(0x424E0380UL))\r
+#define bFM3_ADC0_PCFD_PC1                     *((volatile unsigned int*)(0x424E0384UL))\r
+#define bFM3_ADC0_PCFD_PC2                     *((volatile unsigned int*)(0x424E0388UL))\r
+#define bFM3_ADC0_PCFD_PC3                     *((volatile unsigned int*)(0x424E038CUL))\r
+#define bFM3_ADC0_PCFD_PC4                     *((volatile unsigned int*)(0x424E0390UL))\r
+#define bFM3_ADC0_PCFD_RS0                     *((volatile unsigned int*)(0x424E03A0UL))\r
+#define bFM3_ADC0_PCFD_RS1                     *((volatile unsigned int*)(0x424E03A4UL))\r
+#define bFM3_ADC0_PCFD_RS2                     *((volatile unsigned int*)(0x424E03A8UL))\r
+#define bFM3_ADC0_PCFD_INVL                    *((volatile unsigned int*)(0x424E03B0UL))\r
+#define bFM3_ADC0_PCFD_PD0                     *((volatile unsigned int*)(0x424E03D0UL))\r
+#define bFM3_ADC0_PCFD_PD1                     *((volatile unsigned int*)(0x424E03D4UL))\r
+#define bFM3_ADC0_PCFD_PD2                     *((volatile unsigned int*)(0x424E03D8UL))\r
+#define bFM3_ADC0_PCFD_PD3                     *((volatile unsigned int*)(0x424E03DCUL))\r
+#define bFM3_ADC0_PCFD_PD4                     *((volatile unsigned int*)(0x424E03E0UL))\r
+#define bFM3_ADC0_PCFD_PD5                     *((volatile unsigned int*)(0x424E03E4UL))\r
+#define bFM3_ADC0_PCFD_PD6                     *((volatile unsigned int*)(0x424E03E8UL))\r
+#define bFM3_ADC0_PCFD_PD7                     *((volatile unsigned int*)(0x424E03ECUL))\r
+#define bFM3_ADC0_PCFD_PD8                     *((volatile unsigned int*)(0x424E03F0UL))\r
+#define bFM3_ADC0_PCFD_PD9                     *((volatile unsigned int*)(0x424E03F4UL))\r
+#define bFM3_ADC0_PCFD_PD10                    *((volatile unsigned int*)(0x424E03F8UL))\r
+#define bFM3_ADC0_PCFD_PD11                    *((volatile unsigned int*)(0x424E03FCUL))\r
+#define bFM3_ADC0_PCFDL_PC0                    *((volatile unsigned int*)(0x424E0380UL))\r
+#define bFM3_ADC0_PCFDL_PC1                    *((volatile unsigned int*)(0x424E0384UL))\r
+#define bFM3_ADC0_PCFDL_PC2                    *((volatile unsigned int*)(0x424E0388UL))\r
+#define bFM3_ADC0_PCFDL_PC3                    *((volatile unsigned int*)(0x424E038CUL))\r
+#define bFM3_ADC0_PCFDL_PC4                    *((volatile unsigned int*)(0x424E0390UL))\r
+#define bFM3_ADC0_PCFDL_RS0                    *((volatile unsigned int*)(0x424E03A0UL))\r
+#define bFM3_ADC0_PCFDL_RS1                    *((volatile unsigned int*)(0x424E03A4UL))\r
+#define bFM3_ADC0_PCFDL_RS2                    *((volatile unsigned int*)(0x424E03A8UL))\r
+#define bFM3_ADC0_PCFDL_INVL                   *((volatile unsigned int*)(0x424E03B0UL))\r
+#define bFM3_ADC0_PCFDH_PD0                    *((volatile unsigned int*)(0x424E03D0UL))\r
+#define bFM3_ADC0_PCFDH_PD1                    *((volatile unsigned int*)(0x424E03D4UL))\r
+#define bFM3_ADC0_PCFDH_PD2                    *((volatile unsigned int*)(0x424E03D8UL))\r
+#define bFM3_ADC0_PCFDH_PD3                    *((volatile unsigned int*)(0x424E03DCUL))\r
+#define bFM3_ADC0_PCFDH_PD4                    *((volatile unsigned int*)(0x424E03E0UL))\r
+#define bFM3_ADC0_PCFDH_PD5                    *((volatile unsigned int*)(0x424E03E4UL))\r
+#define bFM3_ADC0_PCFDH_PD6                    *((volatile unsigned int*)(0x424E03E8UL))\r
+#define bFM3_ADC0_PCFDH_PD7                    *((volatile unsigned int*)(0x424E03ECUL))\r
+#define bFM3_ADC0_PCFDH_PD8                    *((volatile unsigned int*)(0x424E03F0UL))\r
+#define bFM3_ADC0_PCFDH_PD9                    *((volatile unsigned int*)(0x424E03F4UL))\r
+#define bFM3_ADC0_PCFDH_PD10                   *((volatile unsigned int*)(0x424E03F8UL))\r
+#define bFM3_ADC0_PCFDH_PD11                   *((volatile unsigned int*)(0x424E03FCUL))\r
+#define bFM3_ADC0_PCIS_P1A0                    *((volatile unsigned int*)(0x424E0400UL))\r
+#define bFM3_ADC0_PCIS_P1A1                    *((volatile unsigned int*)(0x424E0404UL))\r
+#define bFM3_ADC0_PCIS_P1A2                    *((volatile unsigned int*)(0x424E0408UL))\r
+#define bFM3_ADC0_PCIS_P2A0                    *((volatile unsigned int*)(0x424E040CUL))\r
+#define bFM3_ADC0_PCIS_P2A1                    *((volatile unsigned int*)(0x424E0410UL))\r
+#define bFM3_ADC0_PCIS_P2A2                    *((volatile unsigned int*)(0x424E0414UL))\r
+#define bFM3_ADC0_PCIS_P2A3                    *((volatile unsigned int*)(0x424E0418UL))\r
+#define bFM3_ADC0_PCIS_P2A4                    *((volatile unsigned int*)(0x424E041CUL))\r
+#define bFM3_ADC0_CMPCR_CCH0                   *((volatile unsigned int*)(0x424E0480UL))\r
+#define bFM3_ADC0_CMPCR_CCH1                   *((volatile unsigned int*)(0x424E0484UL))\r
+#define bFM3_ADC0_CMPCR_CCH2                   *((volatile unsigned int*)(0x424E0488UL))\r
+#define bFM3_ADC0_CMPCR_CCH3                   *((volatile unsigned int*)(0x424E048CUL))\r
+#define bFM3_ADC0_CMPCR_CCH4                   *((volatile unsigned int*)(0x424E0490UL))\r
+#define bFM3_ADC0_CMPCR_CMD0                   *((volatile unsigned int*)(0x424E0494UL))\r
+#define bFM3_ADC0_CMPCR_CMD1                   *((volatile unsigned int*)(0x424E0498UL))\r
+#define bFM3_ADC0_CMPCR_CMPEN                  *((volatile unsigned int*)(0x424E049CUL))\r
+#define bFM3_ADC0_CMPD_CMAD2                   *((volatile unsigned int*)(0x424E04D8UL))\r
+#define bFM3_ADC0_CMPD_CMAD3                   *((volatile unsigned int*)(0x424E04DCUL))\r
+#define bFM3_ADC0_CMPD_CMAD4                   *((volatile unsigned int*)(0x424E04E0UL))\r
+#define bFM3_ADC0_CMPD_CMAD5                   *((volatile unsigned int*)(0x424E04E4UL))\r
+#define bFM3_ADC0_CMPD_CMAD6                   *((volatile unsigned int*)(0x424E04E8UL))\r
+#define bFM3_ADC0_CMPD_CMAD7                   *((volatile unsigned int*)(0x424E04ECUL))\r
+#define bFM3_ADC0_CMPD_CMAD8                   *((volatile unsigned int*)(0x424E04F0UL))\r
+#define bFM3_ADC0_CMPD_CMAD9                   *((volatile unsigned int*)(0x424E04F4UL))\r
+#define bFM3_ADC0_CMPD_CMAD10                  *((volatile unsigned int*)(0x424E04F8UL))\r
+#define bFM3_ADC0_CMPD_CMAD11                  *((volatile unsigned int*)(0x424E04FCUL))\r
+#define bFM3_ADC0_ADSS23_TS16                  *((volatile unsigned int*)(0x424E0500UL))\r
+#define bFM3_ADC0_ADSS23_TS17                  *((volatile unsigned int*)(0x424E0504UL))\r
+#define bFM3_ADC0_ADSS23_TS18                  *((volatile unsigned int*)(0x424E0508UL))\r
+#define bFM3_ADC0_ADSS23_TS19                  *((volatile unsigned int*)(0x424E050CUL))\r
+#define bFM3_ADC0_ADSS23_TS20                  *((volatile unsigned int*)(0x424E0510UL))\r
+#define bFM3_ADC0_ADSS23_TS21                  *((volatile unsigned int*)(0x424E0514UL))\r
+#define bFM3_ADC0_ADSS23_TS22                  *((volatile unsigned int*)(0x424E0518UL))\r
+#define bFM3_ADC0_ADSS23_TS23                  *((volatile unsigned int*)(0x424E051CUL))\r
+#define bFM3_ADC0_ADSS23_TS24                  *((volatile unsigned int*)(0x424E0520UL))\r
+#define bFM3_ADC0_ADSS23_TS25                  *((volatile unsigned int*)(0x424E0524UL))\r
+#define bFM3_ADC0_ADSS23_TS26                  *((volatile unsigned int*)(0x424E0528UL))\r
+#define bFM3_ADC0_ADSS23_TS27                  *((volatile unsigned int*)(0x424E052CUL))\r
+#define bFM3_ADC0_ADSS23_TS28                  *((volatile unsigned int*)(0x424E0530UL))\r
+#define bFM3_ADC0_ADSS23_TS29                  *((volatile unsigned int*)(0x424E0534UL))\r
+#define bFM3_ADC0_ADSS23_TS30                  *((volatile unsigned int*)(0x424E0538UL))\r
+#define bFM3_ADC0_ADSS23_TS31                  *((volatile unsigned int*)(0x424E053CUL))\r
+#define bFM3_ADC0_ADSS2_TS16                   *((volatile unsigned int*)(0x424E0500UL))\r
+#define bFM3_ADC0_ADSS2_TS17                   *((volatile unsigned int*)(0x424E0504UL))\r
+#define bFM3_ADC0_ADSS2_TS18                   *((volatile unsigned int*)(0x424E0508UL))\r
+#define bFM3_ADC0_ADSS2_TS19                   *((volatile unsigned int*)(0x424E050CUL))\r
+#define bFM3_ADC0_ADSS2_TS20                   *((volatile unsigned int*)(0x424E0510UL))\r
+#define bFM3_ADC0_ADSS2_TS21                   *((volatile unsigned int*)(0x424E0514UL))\r
+#define bFM3_ADC0_ADSS2_TS22                   *((volatile unsigned int*)(0x424E0518UL))\r
+#define bFM3_ADC0_ADSS2_TS23                   *((volatile unsigned int*)(0x424E051CUL))\r
+#define bFM3_ADC0_ADSS3_TS24                   *((volatile unsigned int*)(0x424E0520UL))\r
+#define bFM3_ADC0_ADSS3_TS25                   *((volatile unsigned int*)(0x424E0524UL))\r
+#define bFM3_ADC0_ADSS3_TS26                   *((volatile unsigned int*)(0x424E0528UL))\r
+#define bFM3_ADC0_ADSS3_TS27                   *((volatile unsigned int*)(0x424E052CUL))\r
+#define bFM3_ADC0_ADSS3_TS28                   *((volatile unsigned int*)(0x424E0530UL))\r
+#define bFM3_ADC0_ADSS3_TS29                   *((volatile unsigned int*)(0x424E0534UL))\r
+#define bFM3_ADC0_ADSS3_TS30                   *((volatile unsigned int*)(0x424E0538UL))\r
+#define bFM3_ADC0_ADSS3_TS31                   *((volatile unsigned int*)(0x424E053CUL))\r
+#define bFM3_ADC0_ADSS01_TS0                   *((volatile unsigned int*)(0x424E0580UL))\r
+#define bFM3_ADC0_ADSS01_TS1                   *((volatile unsigned int*)(0x424E0584UL))\r
+#define bFM3_ADC0_ADSS01_TS2                   *((volatile unsigned int*)(0x424E0588UL))\r
+#define bFM3_ADC0_ADSS01_TS3                   *((volatile unsigned int*)(0x424E058CUL))\r
+#define bFM3_ADC0_ADSS01_TS4                   *((volatile unsigned int*)(0x424E0590UL))\r
+#define bFM3_ADC0_ADSS01_TS5                   *((volatile unsigned int*)(0x424E0594UL))\r
+#define bFM3_ADC0_ADSS01_TS6                   *((volatile unsigned int*)(0x424E0598UL))\r
+#define bFM3_ADC0_ADSS01_TS7                   *((volatile unsigned int*)(0x424E059CUL))\r
+#define bFM3_ADC0_ADSS01_TS8                   *((volatile unsigned int*)(0x424E05A0UL))\r
+#define bFM3_ADC0_ADSS01_TS9                   *((volatile unsigned int*)(0x424E05A4UL))\r
+#define bFM3_ADC0_ADSS01_TS10                  *((volatile unsigned int*)(0x424E05A8UL))\r
+#define bFM3_ADC0_ADSS01_TS11                  *((volatile unsigned int*)(0x424E05ACUL))\r
+#define bFM3_ADC0_ADSS01_TS12                  *((volatile unsigned int*)(0x424E05B0UL))\r
+#define bFM3_ADC0_ADSS01_TS13                  *((volatile unsigned int*)(0x424E05B4UL))\r
+#define bFM3_ADC0_ADSS01_TS14                  *((volatile unsigned int*)(0x424E05B8UL))\r
+#define bFM3_ADC0_ADSS01_TS15                  *((volatile unsigned int*)(0x424E05BCUL))\r
+#define bFM3_ADC0_ADSS0_TS0                    *((volatile unsigned int*)(0x424E0580UL))\r
+#define bFM3_ADC0_ADSS0_TS1                    *((volatile unsigned int*)(0x424E0584UL))\r
+#define bFM3_ADC0_ADSS0_TS2                    *((volatile unsigned int*)(0x424E0588UL))\r
+#define bFM3_ADC0_ADSS0_TS3                    *((volatile unsigned int*)(0x424E058CUL))\r
+#define bFM3_ADC0_ADSS0_TS4                    *((volatile unsigned int*)(0x424E0590UL))\r
+#define bFM3_ADC0_ADSS0_TS5                    *((volatile unsigned int*)(0x424E0594UL))\r
+#define bFM3_ADC0_ADSS0_TS6                    *((volatile unsigned int*)(0x424E0598UL))\r
+#define bFM3_ADC0_ADSS0_TS7                    *((volatile unsigned int*)(0x424E059CUL))\r
+#define bFM3_ADC0_ADSS1_TS8                    *((volatile unsigned int*)(0x424E05A0UL))\r
+#define bFM3_ADC0_ADSS1_TS9                    *((volatile unsigned int*)(0x424E05A4UL))\r
+#define bFM3_ADC0_ADSS1_TS10                   *((volatile unsigned int*)(0x424E05A8UL))\r
+#define bFM3_ADC0_ADSS1_TS11                   *((volatile unsigned int*)(0x424E05ACUL))\r
+#define bFM3_ADC0_ADSS1_TS12                   *((volatile unsigned int*)(0x424E05B0UL))\r
+#define bFM3_ADC0_ADSS1_TS13                   *((volatile unsigned int*)(0x424E05B4UL))\r
+#define bFM3_ADC0_ADSS1_TS14                   *((volatile unsigned int*)(0x424E05B8UL))\r
+#define bFM3_ADC0_ADSS1_TS15                   *((volatile unsigned int*)(0x424E05BCUL))\r
+#define bFM3_ADC0_ADST01_ST10                  *((volatile unsigned int*)(0x424E0600UL))\r
+#define bFM3_ADC0_ADST01_ST11                  *((volatile unsigned int*)(0x424E0604UL))\r
+#define bFM3_ADC0_ADST01_ST12                  *((volatile unsigned int*)(0x424E0608UL))\r
+#define bFM3_ADC0_ADST01_ST13                  *((volatile unsigned int*)(0x424E060CUL))\r
+#define bFM3_ADC0_ADST01_ST14                  *((volatile unsigned int*)(0x424E0610UL))\r
+#define bFM3_ADC0_ADST01_STX10                 *((volatile unsigned int*)(0x424E0614UL))\r
+#define bFM3_ADC0_ADST01_STX11                 *((volatile unsigned int*)(0x424E0618UL))\r
+#define bFM3_ADC0_ADST01_STX12                 *((volatile unsigned int*)(0x424E061CUL))\r
+#define bFM3_ADC0_ADST01_ST00                  *((volatile unsigned int*)(0x424E0620UL))\r
+#define bFM3_ADC0_ADST01_ST01                  *((volatile unsigned int*)(0x424E0624UL))\r
+#define bFM3_ADC0_ADST01_ST02                  *((volatile unsigned int*)(0x424E0628UL))\r
+#define bFM3_ADC0_ADST01_ST03                  *((volatile unsigned int*)(0x424E062CUL))\r
+#define bFM3_ADC0_ADST01_ST04                  *((volatile unsigned int*)(0x424E0630UL))\r
+#define bFM3_ADC0_ADST01_STX00                 *((volatile unsigned int*)(0x424E0634UL))\r
+#define bFM3_ADC0_ADST01_STX01                 *((volatile unsigned int*)(0x424E0638UL))\r
+#define bFM3_ADC0_ADST01_STX02                 *((volatile unsigned int*)(0x424E063CUL))\r
+#define bFM3_ADC0_ADST1_ST10                   *((volatile unsigned int*)(0x424E0600UL))\r
+#define bFM3_ADC0_ADST1_ST11                   *((volatile unsigned int*)(0x424E0604UL))\r
+#define bFM3_ADC0_ADST1_ST12                   *((volatile unsigned int*)(0x424E0608UL))\r
+#define bFM3_ADC0_ADST1_ST13                   *((volatile unsigned int*)(0x424E060CUL))\r
+#define bFM3_ADC0_ADST1_ST14                   *((volatile unsigned int*)(0x424E0610UL))\r
+#define bFM3_ADC0_ADST1_STX10                  *((volatile unsigned int*)(0x424E0614UL))\r
+#define bFM3_ADC0_ADST1_STX11                  *((volatile unsigned int*)(0x424E0618UL))\r
+#define bFM3_ADC0_ADST1_STX12                  *((volatile unsigned int*)(0x424E061CUL))\r
+#define bFM3_ADC0_ADST0_ST00                   *((volatile unsigned int*)(0x424E0620UL))\r
+#define bFM3_ADC0_ADST0_ST01                   *((volatile unsigned int*)(0x424E0624UL))\r
+#define bFM3_ADC0_ADST0_ST02                   *((volatile unsigned int*)(0x424E0628UL))\r
+#define bFM3_ADC0_ADST0_ST03                   *((volatile unsigned int*)(0x424E062CUL))\r
+#define bFM3_ADC0_ADST0_ST04                   *((volatile unsigned int*)(0x424E0630UL))\r
+#define bFM3_ADC0_ADST0_STX00                  *((volatile unsigned int*)(0x424E0634UL))\r
+#define bFM3_ADC0_ADST0_STX01                  *((volatile unsigned int*)(0x424E0638UL))\r
+#define bFM3_ADC0_ADST0_STX02                  *((volatile unsigned int*)(0x424E063CUL))\r
+#define bFM3_ADC0_ADCT_CT0                     *((volatile unsigned int*)(0x424E0680UL))\r
+#define bFM3_ADC0_ADCT_CT1                     *((volatile unsigned int*)(0x424E0684UL))\r
+#define bFM3_ADC0_ADCT_CT2                     *((volatile unsigned int*)(0x424E0688UL))\r
+#define bFM3_ADC0_PRTSL_PRTSL0                 *((volatile unsigned int*)(0x424E0700UL))\r
+#define bFM3_ADC0_PRTSL_PRTSL1                 *((volatile unsigned int*)(0x424E0704UL))\r
+#define bFM3_ADC0_PRTSL_PRTSL2                 *((volatile unsigned int*)(0x424E0708UL))\r
+#define bFM3_ADC0_PRTSL_PRTSL3                 *((volatile unsigned int*)(0x424E070CUL))\r
+#define bFM3_ADC0_SCTSL_SCTSL0                 *((volatile unsigned int*)(0x424E0720UL))\r
+#define bFM3_ADC0_SCTSL_SCTSL1                 *((volatile unsigned int*)(0x424E0724UL))\r
+#define bFM3_ADC0_SCTSL_SCTSL2                 *((volatile unsigned int*)(0x424E0728UL))\r
+#define bFM3_ADC0_SCTSL_SCTSL3                 *((volatile unsigned int*)(0x424E072CUL))\r
+#define bFM3_ADC0_ADCEN_ENBL                   *((volatile unsigned int*)(0x424E0780UL))\r
+#define bFM3_ADC0_ADCEN_READY                  *((volatile unsigned int*)(0x424E0784UL))\r
+\r
+/* 12-bit ADC unit 1 registers */\r
+#define bFM3_ADC1_ADSR_SCS                     *((volatile unsigned int*)(0x424E2000UL))\r
+#define bFM3_ADC1_ADSR_PCS                     *((volatile unsigned int*)(0x424E2004UL))\r
+#define bFM3_ADC1_ADSR_PCNS                    *((volatile unsigned int*)(0x424E2008UL))\r
+#define bFM3_ADC1_ADSR_FDAS                    *((volatile unsigned int*)(0x424E2018UL))\r
+#define bFM3_ADC1_ADSR_ADSTP                   *((volatile unsigned int*)(0x424E201CUL))\r
+#define bFM3_ADC1_ADCR_OVRIE                   *((volatile unsigned int*)(0x424E2020UL))\r
+#define bFM3_ADC1_ADCR_CMPIE                   *((volatile unsigned int*)(0x424E2024UL))\r
+#define bFM3_ADC1_ADCR_PCIE                    *((volatile unsigned int*)(0x424E2028UL))\r
+#define bFM3_ADC1_ADCR_SCIE                    *((volatile unsigned int*)(0x424E202CUL))\r
+#define bFM3_ADC1_ADCR_CMPIF                   *((volatile unsigned int*)(0x424E2034UL))\r
+#define bFM3_ADC1_ADCR_PCIF                    *((volatile unsigned int*)(0x424E2038UL))\r
+#define bFM3_ADC1_ADCR_SCIF                    *((volatile unsigned int*)(0x424E203CUL))\r
+#define bFM3_ADC1_SFNS_SFS0                    *((volatile unsigned int*)(0x424E2100UL))\r
+#define bFM3_ADC1_SFNS_SFS1                    *((volatile unsigned int*)(0x424E2104UL))\r
+#define bFM3_ADC1_SFNS_SFS2                    *((volatile unsigned int*)(0x424E2108UL))\r
+#define bFM3_ADC1_SFNS_SFS3                    *((volatile unsigned int*)(0x424E210CUL))\r
+#define bFM3_ADC1_SCCR_SSTR                    *((volatile unsigned int*)(0x424E2120UL))\r
+#define bFM3_ADC1_SCCR_SHEN                    *((volatile unsigned int*)(0x424E2124UL))\r
+#define bFM3_ADC1_SCCR_RPT                     *((volatile unsigned int*)(0x424E2128UL))\r
+#define bFM3_ADC1_SCCR_SFCLR                   *((volatile unsigned int*)(0x424E2130UL))\r
+#define bFM3_ADC1_SCCR_SOVR                    *((volatile unsigned int*)(0x424E2134UL))\r
+#define bFM3_ADC1_SCCR_SFUL                    *((volatile unsigned int*)(0x424E2138UL))\r
+#define bFM3_ADC1_SCCR_SEMP                    *((volatile unsigned int*)(0x424E213CUL))\r
+#define bFM3_ADC1_SCFD_SC0                     *((volatile unsigned int*)(0x424E2180UL))\r
+#define bFM3_ADC1_SCFD_SC1                     *((volatile unsigned int*)(0x424E2184UL))\r
+#define bFM3_ADC1_SCFD_SC2                     *((volatile unsigned int*)(0x424E2188UL))\r
+#define bFM3_ADC1_SCFD_SC3                     *((volatile unsigned int*)(0x424E218CUL))\r
+#define bFM3_ADC1_SCFD_SC4                     *((volatile unsigned int*)(0x424E2190UL))\r
+#define bFM3_ADC1_SCFD_RS0                     *((volatile unsigned int*)(0x424E21A0UL))\r
+#define bFM3_ADC1_SCFD_RS1                     *((volatile unsigned int*)(0x424E21A4UL))\r
+#define bFM3_ADC1_SCFD_INVL                    *((volatile unsigned int*)(0x424E21B0UL))\r
+#define bFM3_ADC1_SCFD_SD0                     *((volatile unsigned int*)(0x424E21D0UL))\r
+#define bFM3_ADC1_SCFD_SD1                     *((volatile unsigned int*)(0x424E21D4UL))\r
+#define bFM3_ADC1_SCFD_SD2                     *((volatile unsigned int*)(0x424E21D8UL))\r
+#define bFM3_ADC1_SCFD_SD3                     *((volatile unsigned int*)(0x424E21DCUL))\r
+#define bFM3_ADC1_SCFD_SD4                     *((volatile unsigned int*)(0x424E21E0UL))\r
+#define bFM3_ADC1_SCFD_SD5                     *((volatile unsigned int*)(0x424E21E4UL))\r
+#define bFM3_ADC1_SCFD_SD6                     *((volatile unsigned int*)(0x424E21E8UL))\r
+#define bFM3_ADC1_SCFD_SD7                     *((volatile unsigned int*)(0x424E21ECUL))\r
+#define bFM3_ADC1_SCFD_SD8                     *((volatile unsigned int*)(0x424E21F0UL))\r
+#define bFM3_ADC1_SCFD_SD9                     *((volatile unsigned int*)(0x424E21F4UL))\r
+#define bFM3_ADC1_SCFD_SD10                    *((volatile unsigned int*)(0x424E21F8UL))\r
+#define bFM3_ADC1_SCFD_SD11                    *((volatile unsigned int*)(0x424E21FCUL))\r
+#define bFM3_ADC1_SCFDL_SC0                    *((volatile unsigned int*)(0x424E2180UL))\r
+#define bFM3_ADC1_SCFDL_SC1                    *((volatile unsigned int*)(0x424E2184UL))\r
+#define bFM3_ADC1_SCFDL_SC2                    *((volatile unsigned int*)(0x424E2188UL))\r
+#define bFM3_ADC1_SCFDL_SC3                    *((volatile unsigned int*)(0x424E218CUL))\r
+#define bFM3_ADC1_SCFDL_SC4                    *((volatile unsigned int*)(0x424E2190UL))\r
+#define bFM3_ADC1_SCFDL_RS0                    *((volatile unsigned int*)(0x424E21A0UL))\r
+#define bFM3_ADC1_SCFDL_RS1                    *((volatile unsigned int*)(0x424E21A4UL))\r
+#define bFM3_ADC1_SCFDL_INVL                   *((volatile unsigned int*)(0x424E21B0UL))\r
+#define bFM3_ADC1_SCFDH_SD0                    *((volatile unsigned int*)(0x424E21D0UL))\r
+#define bFM3_ADC1_SCFDH_SD1                    *((volatile unsigned int*)(0x424E21D4UL))\r
+#define bFM3_ADC1_SCFDH_SD2                    *((volatile unsigned int*)(0x424E21D8UL))\r
+#define bFM3_ADC1_SCFDH_SD3                    *((volatile unsigned int*)(0x424E21DCUL))\r
+#define bFM3_ADC1_SCFDH_SD4                    *((volatile unsigned int*)(0x424E21E0UL))\r
+#define bFM3_ADC1_SCFDH_SD5                    *((volatile unsigned int*)(0x424E21E4UL))\r
+#define bFM3_ADC1_SCFDH_SD6                    *((volatile unsigned int*)(0x424E21E8UL))\r
+#define bFM3_ADC1_SCFDH_SD7                    *((volatile unsigned int*)(0x424E21ECUL))\r
+#define bFM3_ADC1_SCFDH_SD8                    *((volatile unsigned int*)(0x424E21F0UL))\r
+#define bFM3_ADC1_SCFDH_SD9                    *((volatile unsigned int*)(0x424E21F4UL))\r
+#define bFM3_ADC1_SCFDH_SD10                   *((volatile unsigned int*)(0x424E21F8UL))\r
+#define bFM3_ADC1_SCFDH_SD11                   *((volatile unsigned int*)(0x424E21FCUL))\r
+#define bFM3_ADC1_SCIS23_AN16                  *((volatile unsigned int*)(0x424E2200UL))\r
+#define bFM3_ADC1_SCIS23_AN17                  *((volatile unsigned int*)(0x424E2204UL))\r
+#define bFM3_ADC1_SCIS23_AN18                  *((volatile unsigned int*)(0x424E2208UL))\r
+#define bFM3_ADC1_SCIS23_AN19                  *((volatile unsigned int*)(0x424E220CUL))\r
+#define bFM3_ADC1_SCIS23_AN20                  *((volatile unsigned int*)(0x424E2210UL))\r
+#define bFM3_ADC1_SCIS23_AN21                  *((volatile unsigned int*)(0x424E2214UL))\r
+#define bFM3_ADC1_SCIS23_AN22                  *((volatile unsigned int*)(0x424E2218UL))\r
+#define bFM3_ADC1_SCIS23_AN23                  *((volatile unsigned int*)(0x424E221CUL))\r
+#define bFM3_ADC1_SCIS23_AN24                  *((volatile unsigned int*)(0x424E2220UL))\r
+#define bFM3_ADC1_SCIS23_AN25                  *((volatile unsigned int*)(0x424E2224UL))\r
+#define bFM3_ADC1_SCIS23_AN26                  *((volatile unsigned int*)(0x424E2228UL))\r
+#define bFM3_ADC1_SCIS23_AN27                  *((volatile unsigned int*)(0x424E222CUL))\r
+#define bFM3_ADC1_SCIS23_AN28                  *((volatile unsigned int*)(0x424E2230UL))\r
+#define bFM3_ADC1_SCIS23_AN29                  *((volatile unsigned int*)(0x424E2234UL))\r
+#define bFM3_ADC1_SCIS23_AN30                  *((volatile unsigned int*)(0x424E2238UL))\r
+#define bFM3_ADC1_SCIS23_AN31                  *((volatile unsigned int*)(0x424E223CUL))\r
+#define bFM3_ADC1_SCIS2_AN16                   *((volatile unsigned int*)(0x424E2200UL))\r
+#define bFM3_ADC1_SCIS2_AN17                   *((volatile unsigned int*)(0x424E2204UL))\r
+#define bFM3_ADC1_SCIS2_AN18                   *((volatile unsigned int*)(0x424E2208UL))\r
+#define bFM3_ADC1_SCIS2_AN19                   *((volatile unsigned int*)(0x424E220CUL))\r
+#define bFM3_ADC1_SCIS2_AN20                   *((volatile unsigned int*)(0x424E2210UL))\r
+#define bFM3_ADC1_SCIS2_AN21                   *((volatile unsigned int*)(0x424E2214UL))\r
+#define bFM3_ADC1_SCIS2_AN22                   *((volatile unsigned int*)(0x424E2218UL))\r
+#define bFM3_ADC1_SCIS2_AN23                   *((volatile unsigned int*)(0x424E221CUL))\r
+#define bFM3_ADC1_SCIS3_AN24                   *((volatile unsigned int*)(0x424E2220UL))\r
+#define bFM3_ADC1_SCIS3_AN25                   *((volatile unsigned int*)(0x424E2224UL))\r
+#define bFM3_ADC1_SCIS3_AN26                   *((volatile unsigned int*)(0x424E2228UL))\r
+#define bFM3_ADC1_SCIS3_AN27                   *((volatile unsigned int*)(0x424E222CUL))\r
+#define bFM3_ADC1_SCIS3_AN28                   *((volatile unsigned int*)(0x424E2230UL))\r
+#define bFM3_ADC1_SCIS3_AN29                   *((volatile unsigned int*)(0x424E2234UL))\r
+#define bFM3_ADC1_SCIS3_AN30                   *((volatile unsigned int*)(0x424E2238UL))\r
+#define bFM3_ADC1_SCIS3_AN31                   *((volatile unsigned int*)(0x424E223CUL))\r
+#define bFM3_ADC1_SCIS01_AN0                   *((volatile unsigned int*)(0x424E2280UL))\r
+#define bFM3_ADC1_SCIS01_AN1                   *((volatile unsigned int*)(0x424E2284UL))\r
+#define bFM3_ADC1_SCIS01_AN2                   *((volatile unsigned int*)(0x424E2288UL))\r
+#define bFM3_ADC1_SCIS01_AN3                   *((volatile unsigned int*)(0x424E228CUL))\r
+#define bFM3_ADC1_SCIS01_AN4                   *((volatile unsigned int*)(0x424E2290UL))\r
+#define bFM3_ADC1_SCIS01_AN5                   *((volatile unsigned int*)(0x424E2294UL))\r
+#define bFM3_ADC1_SCIS01_AN6                   *((volatile unsigned int*)(0x424E2298UL))\r
+#define bFM3_ADC1_SCIS01_AN7                   *((volatile unsigned int*)(0x424E229CUL))\r
+#define bFM3_ADC1_SCIS01_AN8                   *((volatile unsigned int*)(0x424E22A0UL))\r
+#define bFM3_ADC1_SCIS01_AN9                   *((volatile unsigned int*)(0x424E22A4UL))\r
+#define bFM3_ADC1_SCIS01_AN10                  *((volatile unsigned int*)(0x424E22A8UL))\r
+#define bFM3_ADC1_SCIS01_AN11                  *((volatile unsigned int*)(0x424E22ACUL))\r
+#define bFM3_ADC1_SCIS01_AN12                  *((volatile unsigned int*)(0x424E22B0UL))\r
+#define bFM3_ADC1_SCIS01_AN13                  *((volatile unsigned int*)(0x424E22B4UL))\r
+#define bFM3_ADC1_SCIS01_AN14                  *((volatile unsigned int*)(0x424E22B8UL))\r
+#define bFM3_ADC1_SCIS01_AN15                  *((volatile unsigned int*)(0x424E22BCUL))\r
+#define bFM3_ADC1_SCIS0_AN0                    *((volatile unsigned int*)(0x424E2280UL))\r
+#define bFM3_ADC1_SCIS0_AN1                    *((volatile unsigned int*)(0x424E2284UL))\r
+#define bFM3_ADC1_SCIS0_AN2                    *((volatile unsigned int*)(0x424E2288UL))\r
+#define bFM3_ADC1_SCIS0_AN3                    *((volatile unsigned int*)(0x424E228CUL))\r
+#define bFM3_ADC1_SCIS0_AN4                    *((volatile unsigned int*)(0x424E2290UL))\r
+#define bFM3_ADC1_SCIS0_AN5                    *((volatile unsigned int*)(0x424E2294UL))\r
+#define bFM3_ADC1_SCIS0_AN6                    *((volatile unsigned int*)(0x424E2298UL))\r
+#define bFM3_ADC1_SCIS0_AN7                    *((volatile unsigned int*)(0x424E229CUL))\r
+#define bFM3_ADC1_SCIS1_AN8                    *((volatile unsigned int*)(0x424E22A0UL))\r
+#define bFM3_ADC1_SCIS1_AN9                    *((volatile unsigned int*)(0x424E22A4UL))\r
+#define bFM3_ADC1_SCIS1_AN10                   *((volatile unsigned int*)(0x424E22A8UL))\r
+#define bFM3_ADC1_SCIS1_AN11                   *((volatile unsigned int*)(0x424E22ACUL))\r
+#define bFM3_ADC1_SCIS1_AN12                   *((volatile unsigned int*)(0x424E22B0UL))\r
+#define bFM3_ADC1_SCIS1_AN13                   *((volatile unsigned int*)(0x424E22B4UL))\r
+#define bFM3_ADC1_SCIS1_AN14                   *((volatile unsigned int*)(0x424E22B8UL))\r
+#define bFM3_ADC1_SCIS1_AN15                   *((volatile unsigned int*)(0x424E22BCUL))\r
+#define bFM3_ADC1_PFNS_PFS0                    *((volatile unsigned int*)(0x424E2300UL))\r
+#define bFM3_ADC1_PFNS_PFS1                    *((volatile unsigned int*)(0x424E2304UL))\r
+#define bFM3_ADC1_PFNS_TEST0                   *((volatile unsigned int*)(0x424E2310UL))\r
+#define bFM3_ADC1_PFNS_TEST1                   *((volatile unsigned int*)(0x424E2314UL))\r
+#define bFM3_ADC1_PCCR_PSTR                    *((volatile unsigned int*)(0x424E2320UL))\r
+#define bFM3_ADC1_PCCR_PHEN                    *((volatile unsigned int*)(0x424E2324UL))\r
+#define bFM3_ADC1_PCCR_PEEN                    *((volatile unsigned int*)(0x424E2328UL))\r
+#define bFM3_ADC1_PCCR_ESCE                    *((volatile unsigned int*)(0x424E232CUL))\r
+#define bFM3_ADC1_PCCR_PFCLR                   *((volatile unsigned int*)(0x424E2330UL))\r
+#define bFM3_ADC1_PCCR_POVR                    *((volatile unsigned int*)(0x424E2334UL))\r
+#define bFM3_ADC1_PCCR_PFUL                    *((volatile unsigned int*)(0x424E2338UL))\r
+#define bFM3_ADC1_PCCR_PEMP                    *((volatile unsigned int*)(0x424E233CUL))\r
+#define bFM3_ADC1_PCFD_PC0                     *((volatile unsigned int*)(0x424E2380UL))\r
+#define bFM3_ADC1_PCFD_PC1                     *((volatile unsigned int*)(0x424E2384UL))\r
+#define bFM3_ADC1_PCFD_PC2                     *((volatile unsigned int*)(0x424E2388UL))\r
+#define bFM3_ADC1_PCFD_PC3                     *((volatile unsigned int*)(0x424E238CUL))\r
+#define bFM3_ADC1_PCFD_PC4                     *((volatile unsigned int*)(0x424E2390UL))\r
+#define bFM3_ADC1_PCFD_RS0                     *((volatile unsigned int*)(0x424E23A0UL))\r
+#define bFM3_ADC1_PCFD_RS1                     *((volatile unsigned int*)(0x424E23A4UL))\r
+#define bFM3_ADC1_PCFD_RS2                     *((volatile unsigned int*)(0x424E23A8UL))\r
+#define bFM3_ADC1_PCFD_INVL                    *((volatile unsigned int*)(0x424E23B0UL))\r
+#define bFM3_ADC1_PCFD_PD0                     *((volatile unsigned int*)(0x424E23D0UL))\r
+#define bFM3_ADC1_PCFD_PD1                     *((volatile unsigned int*)(0x424E23D4UL))\r
+#define bFM3_ADC1_PCFD_PD2                     *((volatile unsigned int*)(0x424E23D8UL))\r
+#define bFM3_ADC1_PCFD_PD3                     *((volatile unsigned int*)(0x424E23DCUL))\r
+#define bFM3_ADC1_PCFD_PD4                     *((volatile unsigned int*)(0x424E23E0UL))\r
+#define bFM3_ADC1_PCFD_PD5                     *((volatile unsigned int*)(0x424E23E4UL))\r
+#define bFM3_ADC1_PCFD_PD6                     *((volatile unsigned int*)(0x424E23E8UL))\r
+#define bFM3_ADC1_PCFD_PD7                     *((volatile unsigned int*)(0x424E23ECUL))\r
+#define bFM3_ADC1_PCFD_PD8                     *((volatile unsigned int*)(0x424E23F0UL))\r
+#define bFM3_ADC1_PCFD_PD9                     *((volatile unsigned int*)(0x424E23F4UL))\r
+#define bFM3_ADC1_PCFD_PD10                    *((volatile unsigned int*)(0x424E23F8UL))\r
+#define bFM3_ADC1_PCFD_PD11                    *((volatile unsigned int*)(0x424E23FCUL))\r
+#define bFM3_ADC1_PCFDL_PC0                    *((volatile unsigned int*)(0x424E2380UL))\r
+#define bFM3_ADC1_PCFDL_PC1                    *((volatile unsigned int*)(0x424E2384UL))\r
+#define bFM3_ADC1_PCFDL_PC2                    *((volatile unsigned int*)(0x424E2388UL))\r
+#define bFM3_ADC1_PCFDL_PC3                    *((volatile unsigned int*)(0x424E238CUL))\r
+#define bFM3_ADC1_PCFDL_PC4                    *((volatile unsigned int*)(0x424E2390UL))\r
+#define bFM3_ADC1_PCFDL_RS0                    *((volatile unsigned int*)(0x424E23A0UL))\r
+#define bFM3_ADC1_PCFDL_RS1                    *((volatile unsigned int*)(0x424E23A4UL))\r
+#define bFM3_ADC1_PCFDL_RS2                    *((volatile unsigned int*)(0x424E23A8UL))\r
+#define bFM3_ADC1_PCFDL_INVL                   *((volatile unsigned int*)(0x424E23B0UL))\r
+#define bFM3_ADC1_PCFDH_PD0                    *((volatile unsigned int*)(0x424E23D0UL))\r
+#define bFM3_ADC1_PCFDH_PD1                    *((volatile unsigned int*)(0x424E23D4UL))\r
+#define bFM3_ADC1_PCFDH_PD2                    *((volatile unsigned int*)(0x424E23D8UL))\r
+#define bFM3_ADC1_PCFDH_PD3                    *((volatile unsigned int*)(0x424E23DCUL))\r
+#define bFM3_ADC1_PCFDH_PD4                    *((volatile unsigned int*)(0x424E23E0UL))\r
+#define bFM3_ADC1_PCFDH_PD5                    *((volatile unsigned int*)(0x424E23E4UL))\r
+#define bFM3_ADC1_PCFDH_PD6                    *((volatile unsigned int*)(0x424E23E8UL))\r
+#define bFM3_ADC1_PCFDH_PD7                    *((volatile unsigned int*)(0x424E23ECUL))\r
+#define bFM3_ADC1_PCFDH_PD8                    *((volatile unsigned int*)(0x424E23F0UL))\r
+#define bFM3_ADC1_PCFDH_PD9                    *((volatile unsigned int*)(0x424E23F4UL))\r
+#define bFM3_ADC1_PCFDH_PD10                   *((volatile unsigned int*)(0x424E23F8UL))\r
+#define bFM3_ADC1_PCFDH_PD11                   *((volatile unsigned int*)(0x424E23FCUL))\r
+#define bFM3_ADC1_PCIS_P1A0                    *((volatile unsigned int*)(0x424E2400UL))\r
+#define bFM3_ADC1_PCIS_P1A1                    *((volatile unsigned int*)(0x424E2404UL))\r
+#define bFM3_ADC1_PCIS_P1A2                    *((volatile unsigned int*)(0x424E2408UL))\r
+#define bFM3_ADC1_PCIS_P2A0                    *((volatile unsigned int*)(0x424E240CUL))\r
+#define bFM3_ADC1_PCIS_P2A1                    *((volatile unsigned int*)(0x424E2410UL))\r
+#define bFM3_ADC1_PCIS_P2A2                    *((volatile unsigned int*)(0x424E2414UL))\r
+#define bFM3_ADC1_PCIS_P2A3                    *((volatile unsigned int*)(0x424E2418UL))\r
+#define bFM3_ADC1_PCIS_P2A4                    *((volatile unsigned int*)(0x424E241CUL))\r
+#define bFM3_ADC1_CMPCR_CCH0                   *((volatile unsigned int*)(0x424E2480UL))\r
+#define bFM3_ADC1_CMPCR_CCH1                   *((volatile unsigned int*)(0x424E2484UL))\r
+#define bFM3_ADC1_CMPCR_CCH2                   *((volatile unsigned int*)(0x424E2488UL))\r
+#define bFM3_ADC1_CMPCR_CCH3                   *((volatile unsigned int*)(0x424E248CUL))\r
+#define bFM3_ADC1_CMPCR_CCH4                   *((volatile unsigned int*)(0x424E2490UL))\r
+#define bFM3_ADC1_CMPCR_CMD0                   *((volatile unsigned int*)(0x424E2494UL))\r
+#define bFM3_ADC1_CMPCR_CMD1                   *((volatile unsigned int*)(0x424E2498UL))\r
+#define bFM3_ADC1_CMPCR_CMPEN                  *((volatile unsigned int*)(0x424E249CUL))\r
+#define bFM3_ADC1_CMPD_CMAD2                   *((volatile unsigned int*)(0x424E24D8UL))\r
+#define bFM3_ADC1_CMPD_CMAD3                   *((volatile unsigned int*)(0x424E24DCUL))\r
+#define bFM3_ADC1_CMPD_CMAD4                   *((volatile unsigned int*)(0x424E24E0UL))\r
+#define bFM3_ADC1_CMPD_CMAD5                   *((volatile unsigned int*)(0x424E24E4UL))\r
+#define bFM3_ADC1_CMPD_CMAD6                   *((volatile unsigned int*)(0x424E24E8UL))\r
+#define bFM3_ADC1_CMPD_CMAD7                   *((volatile unsigned int*)(0x424E24ECUL))\r
+#define bFM3_ADC1_CMPD_CMAD8                   *((volatile unsigned int*)(0x424E24F0UL))\r
+#define bFM3_ADC1_CMPD_CMAD9                   *((volatile unsigned int*)(0x424E24F4UL))\r
+#define bFM3_ADC1_CMPD_CMAD10                  *((volatile unsigned int*)(0x424E24F8UL))\r
+#define bFM3_ADC1_CMPD_CMAD11                  *((volatile unsigned int*)(0x424E24FCUL))\r
+#define bFM3_ADC1_ADSS23_TS16                  *((volatile unsigned int*)(0x424E2500UL))\r
+#define bFM3_ADC1_ADSS23_TS17                  *((volatile unsigned int*)(0x424E2504UL))\r
+#define bFM3_ADC1_ADSS23_TS18                  *((volatile unsigned int*)(0x424E2508UL))\r
+#define bFM3_ADC1_ADSS23_TS19                  *((volatile unsigned int*)(0x424E250CUL))\r
+#define bFM3_ADC1_ADSS23_TS20                  *((volatile unsigned int*)(0x424E2510UL))\r
+#define bFM3_ADC1_ADSS23_TS21                  *((volatile unsigned int*)(0x424E2514UL))\r
+#define bFM3_ADC1_ADSS23_TS22                  *((volatile unsigned int*)(0x424E2518UL))\r
+#define bFM3_ADC1_ADSS23_TS23                  *((volatile unsigned int*)(0x424E251CUL))\r
+#define bFM3_ADC1_ADSS23_TS24                  *((volatile unsigned int*)(0x424E2520UL))\r
+#define bFM3_ADC1_ADSS23_TS25                  *((volatile unsigned int*)(0x424E2524UL))\r
+#define bFM3_ADC1_ADSS23_TS26                  *((volatile unsigned int*)(0x424E2528UL))\r
+#define bFM3_ADC1_ADSS23_TS27                  *((volatile unsigned int*)(0x424E252CUL))\r
+#define bFM3_ADC1_ADSS23_TS28                  *((volatile unsigned int*)(0x424E2530UL))\r
+#define bFM3_ADC1_ADSS23_TS29                  *((volatile unsigned int*)(0x424E2534UL))\r
+#define bFM3_ADC1_ADSS23_TS30                  *((volatile unsigned int*)(0x424E2538UL))\r
+#define bFM3_ADC1_ADSS23_TS31                  *((volatile unsigned int*)(0x424E253CUL))\r
+#define bFM3_ADC1_ADSS2_TS16                   *((volatile unsigned int*)(0x424E2500UL))\r
+#define bFM3_ADC1_ADSS2_TS17                   *((volatile unsigned int*)(0x424E2504UL))\r
+#define bFM3_ADC1_ADSS2_TS18                   *((volatile unsigned int*)(0x424E2508UL))\r
+#define bFM3_ADC1_ADSS2_TS19                   *((volatile unsigned int*)(0x424E250CUL))\r
+#define bFM3_ADC1_ADSS2_TS20                   *((volatile unsigned int*)(0x424E2510UL))\r
+#define bFM3_ADC1_ADSS2_TS21                   *((volatile unsigned int*)(0x424E2514UL))\r
+#define bFM3_ADC1_ADSS2_TS22                   *((volatile unsigned int*)(0x424E2518UL))\r
+#define bFM3_ADC1_ADSS2_TS23                   *((volatile unsigned int*)(0x424E251CUL))\r
+#define bFM3_ADC1_ADSS3_TS24                   *((volatile unsigned int*)(0x424E2520UL))\r
+#define bFM3_ADC1_ADSS3_TS25                   *((volatile unsigned int*)(0x424E2524UL))\r
+#define bFM3_ADC1_ADSS3_TS26                   *((volatile unsigned int*)(0x424E2528UL))\r
+#define bFM3_ADC1_ADSS3_TS27                   *((volatile unsigned int*)(0x424E252CUL))\r
+#define bFM3_ADC1_ADSS3_TS28                   *((volatile unsigned int*)(0x424E2530UL))\r
+#define bFM3_ADC1_ADSS3_TS29                   *((volatile unsigned int*)(0x424E2534UL))\r
+#define bFM3_ADC1_ADSS3_TS30                   *((volatile unsigned int*)(0x424E2538UL))\r
+#define bFM3_ADC1_ADSS3_TS31                   *((volatile unsigned int*)(0x424E253CUL))\r
+#define bFM3_ADC1_ADSS01_TS0                   *((volatile unsigned int*)(0x424E2580UL))\r
+#define bFM3_ADC1_ADSS01_TS1                   *((volatile unsigned int*)(0x424E2584UL))\r
+#define bFM3_ADC1_ADSS01_TS2                   *((volatile unsigned int*)(0x424E2588UL))\r
+#define bFM3_ADC1_ADSS01_TS3                   *((volatile unsigned int*)(0x424E258CUL))\r
+#define bFM3_ADC1_ADSS01_TS4                   *((volatile unsigned int*)(0x424E2590UL))\r
+#define bFM3_ADC1_ADSS01_TS5                   *((volatile unsigned int*)(0x424E2594UL))\r
+#define bFM3_ADC1_ADSS01_TS6                   *((volatile unsigned int*)(0x424E2598UL))\r
+#define bFM3_ADC1_ADSS01_TS7                   *((volatile unsigned int*)(0x424E259CUL))\r
+#define bFM3_ADC1_ADSS01_TS8                   *((volatile unsigned int*)(0x424E25A0UL))\r
+#define bFM3_ADC1_ADSS01_TS9                   *((volatile unsigned int*)(0x424E25A4UL))\r
+#define bFM3_ADC1_ADSS01_TS10                  *((volatile unsigned int*)(0x424E25A8UL))\r
+#define bFM3_ADC1_ADSS01_TS11                  *((volatile unsigned int*)(0x424E25ACUL))\r
+#define bFM3_ADC1_ADSS01_TS12                  *((volatile unsigned int*)(0x424E25B0UL))\r
+#define bFM3_ADC1_ADSS01_TS13                  *((volatile unsigned int*)(0x424E25B4UL))\r
+#define bFM3_ADC1_ADSS01_TS14                  *((volatile unsigned int*)(0x424E25B8UL))\r
+#define bFM3_ADC1_ADSS01_TS15                  *((volatile unsigned int*)(0x424E25BCUL))\r
+#define bFM3_ADC1_ADSS0_TS0                    *((volatile unsigned int*)(0x424E2580UL))\r
+#define bFM3_ADC1_ADSS0_TS1                    *((volatile unsigned int*)(0x424E2584UL))\r
+#define bFM3_ADC1_ADSS0_TS2                    *((volatile unsigned int*)(0x424E2588UL))\r
+#define bFM3_ADC1_ADSS0_TS3                    *((volatile unsigned int*)(0x424E258CUL))\r
+#define bFM3_ADC1_ADSS0_TS4                    *((volatile unsigned int*)(0x424E2590UL))\r
+#define bFM3_ADC1_ADSS0_TS5                    *((volatile unsigned int*)(0x424E2594UL))\r
+#define bFM3_ADC1_ADSS0_TS6                    *((volatile unsigned int*)(0x424E2598UL))\r
+#define bFM3_ADC1_ADSS0_TS7                    *((volatile unsigned int*)(0x424E259CUL))\r
+#define bFM3_ADC1_ADSS1_TS8                    *((volatile unsigned int*)(0x424E25A0UL))\r
+#define bFM3_ADC1_ADSS1_TS9                    *((volatile unsigned int*)(0x424E25A4UL))\r
+#define bFM3_ADC1_ADSS1_TS10                   *((volatile unsigned int*)(0x424E25A8UL))\r
+#define bFM3_ADC1_ADSS1_TS11                   *((volatile unsigned int*)(0x424E25ACUL))\r
+#define bFM3_ADC1_ADSS1_TS12                   *((volatile unsigned int*)(0x424E25B0UL))\r
+#define bFM3_ADC1_ADSS1_TS13                   *((volatile unsigned int*)(0x424E25B4UL))\r
+#define bFM3_ADC1_ADSS1_TS14                   *((volatile unsigned int*)(0x424E25B8UL))\r
+#define bFM3_ADC1_ADSS1_TS15                   *((volatile unsigned int*)(0x424E25BCUL))\r
+#define bFM3_ADC1_ADST01_ST10                  *((volatile unsigned int*)(0x424E2600UL))\r
+#define bFM3_ADC1_ADST01_ST11                  *((volatile unsigned int*)(0x424E2604UL))\r
+#define bFM3_ADC1_ADST01_ST12                  *((volatile unsigned int*)(0x424E2608UL))\r
+#define bFM3_ADC1_ADST01_ST13                  *((volatile unsigned int*)(0x424E260CUL))\r
+#define bFM3_ADC1_ADST01_ST14                  *((volatile unsigned int*)(0x424E2610UL))\r
+#define bFM3_ADC1_ADST01_STX10                 *((volatile unsigned int*)(0x424E2614UL))\r
+#define bFM3_ADC1_ADST01_STX11                 *((volatile unsigned int*)(0x424E2618UL))\r
+#define bFM3_ADC1_ADST01_STX12                 *((volatile unsigned int*)(0x424E261CUL))\r
+#define bFM3_ADC1_ADST01_ST00                  *((volatile unsigned int*)(0x424E2620UL))\r
+#define bFM3_ADC1_ADST01_ST01                  *((volatile unsigned int*)(0x424E2624UL))\r
+#define bFM3_ADC1_ADST01_ST02                  *((volatile unsigned int*)(0x424E2628UL))\r
+#define bFM3_ADC1_ADST01_ST03                  *((volatile unsigned int*)(0x424E262CUL))\r
+#define bFM3_ADC1_ADST01_ST04                  *((volatile unsigned int*)(0x424E2630UL))\r
+#define bFM3_ADC1_ADST01_STX00                 *((volatile unsigned int*)(0x424E2634UL))\r
+#define bFM3_ADC1_ADST01_STX01                 *((volatile unsigned int*)(0x424E2638UL))\r
+#define bFM3_ADC1_ADST01_STX02                 *((volatile unsigned int*)(0x424E263CUL))\r
+#define bFM3_ADC1_ADST1_ST10                   *((volatile unsigned int*)(0x424E2600UL))\r
+#define bFM3_ADC1_ADST1_ST11                   *((volatile unsigned int*)(0x424E2604UL))\r
+#define bFM3_ADC1_ADST1_ST12                   *((volatile unsigned int*)(0x424E2608UL))\r
+#define bFM3_ADC1_ADST1_ST13                   *((volatile unsigned int*)(0x424E260CUL))\r
+#define bFM3_ADC1_ADST1_ST14                   *((volatile unsigned int*)(0x424E2610UL))\r
+#define bFM3_ADC1_ADST1_STX10                  *((volatile unsigned int*)(0x424E2614UL))\r
+#define bFM3_ADC1_ADST1_STX11                  *((volatile unsigned int*)(0x424E2618UL))\r
+#define bFM3_ADC1_ADST1_STX12                  *((volatile unsigned int*)(0x424E261CUL))\r
+#define bFM3_ADC1_ADST0_ST00                   *((volatile unsigned int*)(0x424E2620UL))\r
+#define bFM3_ADC1_ADST0_ST01                   *((volatile unsigned int*)(0x424E2624UL))\r
+#define bFM3_ADC1_ADST0_ST02                   *((volatile unsigned int*)(0x424E2628UL))\r
+#define bFM3_ADC1_ADST0_ST03                   *((volatile unsigned int*)(0x424E262CUL))\r
+#define bFM3_ADC1_ADST0_ST04                   *((volatile unsigned int*)(0x424E2630UL))\r
+#define bFM3_ADC1_ADST0_STX00                  *((volatile unsigned int*)(0x424E2634UL))\r
+#define bFM3_ADC1_ADST0_STX01                  *((volatile unsigned int*)(0x424E2638UL))\r
+#define bFM3_ADC1_ADST0_STX02                  *((volatile unsigned int*)(0x424E263CUL))\r
+#define bFM3_ADC1_ADCT_CT0                     *((volatile unsigned int*)(0x424E2680UL))\r
+#define bFM3_ADC1_ADCT_CT1                     *((volatile unsigned int*)(0x424E2684UL))\r
+#define bFM3_ADC1_ADCT_CT2                     *((volatile unsigned int*)(0x424E2688UL))\r
+#define bFM3_ADC1_PRTSL_PRTSL0                 *((volatile unsigned int*)(0x424E2700UL))\r
+#define bFM3_ADC1_PRTSL_PRTSL1                 *((volatile unsigned int*)(0x424E2704UL))\r
+#define bFM3_ADC1_PRTSL_PRTSL2                 *((volatile unsigned int*)(0x424E2708UL))\r
+#define bFM3_ADC1_PRTSL_PRTSL3                 *((volatile unsigned int*)(0x424E270CUL))\r
+#define bFM3_ADC1_SCTSL_SCTSL0                 *((volatile unsigned int*)(0x424E2720UL))\r
+#define bFM3_ADC1_SCTSL_SCTSL1                 *((volatile unsigned int*)(0x424E2724UL))\r
+#define bFM3_ADC1_SCTSL_SCTSL2                 *((volatile unsigned int*)(0x424E2728UL))\r
+#define bFM3_ADC1_SCTSL_SCTSL3                 *((volatile unsigned int*)(0x424E272CUL))\r
+#define bFM3_ADC1_ADCEN_ENBL                   *((volatile unsigned int*)(0x424E2780UL))\r
+#define bFM3_ADC1_ADCEN_READY                  *((volatile unsigned int*)(0x424E2784UL))\r
+\r
+/* 12-bit ADC unit 2 registers */\r
+#define bFM3_ADC2_ADSR_SCS                     *((volatile unsigned int*)(0x424E4000UL))\r
+#define bFM3_ADC2_ADSR_PCS                     *((volatile unsigned int*)(0x424E4004UL))\r
+#define bFM3_ADC2_ADSR_PCNS                    *((volatile unsigned int*)(0x424E4008UL))\r
+#define bFM3_ADC2_ADSR_FDAS                    *((volatile unsigned int*)(0x424E4018UL))\r
+#define bFM3_ADC2_ADSR_ADSTP                   *((volatile unsigned int*)(0x424E401CUL))\r
+#define bFM3_ADC2_ADCR_OVRIE                   *((volatile unsigned int*)(0x424E4020UL))\r
+#define bFM3_ADC2_ADCR_CMPIE                   *((volatile unsigned int*)(0x424E4024UL))\r
+#define bFM3_ADC2_ADCR_PCIE                    *((volatile unsigned int*)(0x424E4028UL))\r
+#define bFM3_ADC2_ADCR_SCIE                    *((volatile unsigned int*)(0x424E402CUL))\r
+#define bFM3_ADC2_ADCR_CMPIF                   *((volatile unsigned int*)(0x424E4034UL))\r
+#define bFM3_ADC2_ADCR_PCIF                    *((volatile unsigned int*)(0x424E4038UL))\r
+#define bFM3_ADC2_ADCR_SCIF                    *((volatile unsigned int*)(0x424E403CUL))\r
+#define bFM3_ADC2_SFNS_SFS0                    *((volatile unsigned int*)(0x424E4100UL))\r
+#define bFM3_ADC2_SFNS_SFS1                    *((volatile unsigned int*)(0x424E4104UL))\r
+#define bFM3_ADC2_SFNS_SFS2                    *((volatile unsigned int*)(0x424E4108UL))\r
+#define bFM3_ADC2_SFNS_SFS3                    *((volatile unsigned int*)(0x424E410CUL))\r
+#define bFM3_ADC2_SCCR_SSTR                    *((volatile unsigned int*)(0x424E4120UL))\r
+#define bFM3_ADC2_SCCR_SHEN                    *((volatile unsigned int*)(0x424E4124UL))\r
+#define bFM3_ADC2_SCCR_RPT                     *((volatile unsigned int*)(0x424E4128UL))\r
+#define bFM3_ADC2_SCCR_SFCLR                   *((volatile unsigned int*)(0x424E4130UL))\r
+#define bFM3_ADC2_SCCR_SOVR                    *((volatile unsigned int*)(0x424E4134UL))\r
+#define bFM3_ADC2_SCCR_SFUL                    *((volatile unsigned int*)(0x424E4138UL))\r
+#define bFM3_ADC2_SCCR_SEMP                    *((volatile unsigned int*)(0x424E413CUL))\r
+#define bFM3_ADC2_SCFD_SC0                     *((volatile unsigned int*)(0x424E4180UL))\r
+#define bFM3_ADC2_SCFD_SC1                     *((volatile unsigned int*)(0x424E4184UL))\r
+#define bFM3_ADC2_SCFD_SC2                     *((volatile unsigned int*)(0x424E4188UL))\r
+#define bFM3_ADC2_SCFD_SC3                     *((volatile unsigned int*)(0x424E418CUL))\r
+#define bFM3_ADC2_SCFD_SC4                     *((volatile unsigned int*)(0x424E4190UL))\r
+#define bFM3_ADC2_SCFD_RS0                     *((volatile unsigned int*)(0x424E41A0UL))\r
+#define bFM3_ADC2_SCFD_RS1                     *((volatile unsigned int*)(0x424E41A4UL))\r
+#define bFM3_ADC2_SCFD_INVL                    *((volatile unsigned int*)(0x424E41B0UL))\r
+#define bFM3_ADC2_SCFD_SD0                     *((volatile unsigned int*)(0x424E41D0UL))\r
+#define bFM3_ADC2_SCFD_SD1                     *((volatile unsigned int*)(0x424E41D4UL))\r
+#define bFM3_ADC2_SCFD_SD2                     *((volatile unsigned int*)(0x424E41D8UL))\r
+#define bFM3_ADC2_SCFD_SD3                     *((volatile unsigned int*)(0x424E41DCUL))\r
+#define bFM3_ADC2_SCFD_SD4                     *((volatile unsigned int*)(0x424E41E0UL))\r
+#define bFM3_ADC2_SCFD_SD5                     *((volatile unsigned int*)(0x424E41E4UL))\r
+#define bFM3_ADC2_SCFD_SD6                     *((volatile unsigned int*)(0x424E41E8UL))\r
+#define bFM3_ADC2_SCFD_SD7                     *((volatile unsigned int*)(0x424E41ECUL))\r
+#define bFM3_ADC2_SCFD_SD8                     *((volatile unsigned int*)(0x424E41F0UL))\r
+#define bFM3_ADC2_SCFD_SD9                     *((volatile unsigned int*)(0x424E41F4UL))\r
+#define bFM3_ADC2_SCFD_SD10                    *((volatile unsigned int*)(0x424E41F8UL))\r
+#define bFM3_ADC2_SCFD_SD11                    *((volatile unsigned int*)(0x424E41FCUL))\r
+#define bFM3_ADC2_SCFDL_SC0                    *((volatile unsigned int*)(0x424E4180UL))\r
+#define bFM3_ADC2_SCFDL_SC1                    *((volatile unsigned int*)(0x424E4184UL))\r
+#define bFM3_ADC2_SCFDL_SC2                    *((volatile unsigned int*)(0x424E4188UL))\r
+#define bFM3_ADC2_SCFDL_SC3                    *((volatile unsigned int*)(0x424E418CUL))\r
+#define bFM3_ADC2_SCFDL_SC4                    *((volatile unsigned int*)(0x424E4190UL))\r
+#define bFM3_ADC2_SCFDL_RS0                    *((volatile unsigned int*)(0x424E41A0UL))\r
+#define bFM3_ADC2_SCFDL_RS1                    *((volatile unsigned int*)(0x424E41A4UL))\r
+#define bFM3_ADC2_SCFDL_INVL                   *((volatile unsigned int*)(0x424E41B0UL))\r
+#define bFM3_ADC2_SCFDH_SD0                    *((volatile unsigned int*)(0x424E41D0UL))\r
+#define bFM3_ADC2_SCFDH_SD1                    *((volatile unsigned int*)(0x424E41D4UL))\r
+#define bFM3_ADC2_SCFDH_SD2                    *((volatile unsigned int*)(0x424E41D8UL))\r
+#define bFM3_ADC2_SCFDH_SD3                    *((volatile unsigned int*)(0x424E41DCUL))\r
+#define bFM3_ADC2_SCFDH_SD4                    *((volatile unsigned int*)(0x424E41E0UL))\r
+#define bFM3_ADC2_SCFDH_SD5                    *((volatile unsigned int*)(0x424E41E4UL))\r
+#define bFM3_ADC2_SCFDH_SD6                    *((volatile unsigned int*)(0x424E41E8UL))\r
+#define bFM3_ADC2_SCFDH_SD7                    *((volatile unsigned int*)(0x424E41ECUL))\r
+#define bFM3_ADC2_SCFDH_SD8                    *((volatile unsigned int*)(0x424E41F0UL))\r
+#define bFM3_ADC2_SCFDH_SD9                    *((volatile unsigned int*)(0x424E41F4UL))\r
+#define bFM3_ADC2_SCFDH_SD10                   *((volatile unsigned int*)(0x424E41F8UL))\r
+#define bFM3_ADC2_SCFDH_SD11                   *((volatile unsigned int*)(0x424E41FCUL))\r
+#define bFM3_ADC2_SCIS23_AN16                  *((volatile unsigned int*)(0x424E4200UL))\r
+#define bFM3_ADC2_SCIS23_AN17                  *((volatile unsigned int*)(0x424E4204UL))\r
+#define bFM3_ADC2_SCIS23_AN18                  *((volatile unsigned int*)(0x424E4208UL))\r
+#define bFM3_ADC2_SCIS23_AN19                  *((volatile unsigned int*)(0x424E420CUL))\r
+#define bFM3_ADC2_SCIS23_AN20                  *((volatile unsigned int*)(0x424E4210UL))\r
+#define bFM3_ADC2_SCIS23_AN21                  *((volatile unsigned int*)(0x424E4214UL))\r
+#define bFM3_ADC2_SCIS23_AN22                  *((volatile unsigned int*)(0x424E4218UL))\r
+#define bFM3_ADC2_SCIS23_AN23                  *((volatile unsigned int*)(0x424E421CUL))\r
+#define bFM3_ADC2_SCIS23_AN24                  *((volatile unsigned int*)(0x424E4220UL))\r
+#define bFM3_ADC2_SCIS23_AN25                  *((volatile unsigned int*)(0x424E4224UL))\r
+#define bFM3_ADC2_SCIS23_AN26                  *((volatile unsigned int*)(0x424E4228UL))\r
+#define bFM3_ADC2_SCIS23_AN27                  *((volatile unsigned int*)(0x424E422CUL))\r
+#define bFM3_ADC2_SCIS23_AN28                  *((volatile unsigned int*)(0x424E4230UL))\r
+#define bFM3_ADC2_SCIS23_AN29                  *((volatile unsigned int*)(0x424E4234UL))\r
+#define bFM3_ADC2_SCIS23_AN30                  *((volatile unsigned int*)(0x424E4238UL))\r
+#define bFM3_ADC2_SCIS23_AN31                  *((volatile unsigned int*)(0x424E423CUL))\r
+#define bFM3_ADC2_SCIS2_AN16                   *((volatile unsigned int*)(0x424E4200UL))\r
+#define bFM3_ADC2_SCIS2_AN17                   *((volatile unsigned int*)(0x424E4204UL))\r
+#define bFM3_ADC2_SCIS2_AN18                   *((volatile unsigned int*)(0x424E4208UL))\r
+#define bFM3_ADC2_SCIS2_AN19                   *((volatile unsigned int*)(0x424E420CUL))\r
+#define bFM3_ADC2_SCIS2_AN20                   *((volatile unsigned int*)(0x424E4210UL))\r
+#define bFM3_ADC2_SCIS2_AN21                   *((volatile unsigned int*)(0x424E4214UL))\r
+#define bFM3_ADC2_SCIS2_AN22                   *((volatile unsigned int*)(0x424E4218UL))\r
+#define bFM3_ADC2_SCIS2_AN23                   *((volatile unsigned int*)(0x424E421CUL))\r
+#define bFM3_ADC2_SCIS3_AN24                   *((volatile unsigned int*)(0x424E4220UL))\r
+#define bFM3_ADC2_SCIS3_AN25                   *((volatile unsigned int*)(0x424E4224UL))\r
+#define bFM3_ADC2_SCIS3_AN26                   *((volatile unsigned int*)(0x424E4228UL))\r
+#define bFM3_ADC2_SCIS3_AN27                   *((volatile unsigned int*)(0x424E422CUL))\r
+#define bFM3_ADC2_SCIS3_AN28                   *((volatile unsigned int*)(0x424E4230UL))\r
+#define bFM3_ADC2_SCIS3_AN29                   *((volatile unsigned int*)(0x424E4234UL))\r
+#define bFM3_ADC2_SCIS3_AN30                   *((volatile unsigned int*)(0x424E4238UL))\r
+#define bFM3_ADC2_SCIS3_AN31                   *((volatile unsigned int*)(0x424E423CUL))\r
+#define bFM3_ADC2_SCIS01_AN0                   *((volatile unsigned int*)(0x424E4280UL))\r
+#define bFM3_ADC2_SCIS01_AN1                   *((volatile unsigned int*)(0x424E4284UL))\r
+#define bFM3_ADC2_SCIS01_AN2                   *((volatile unsigned int*)(0x424E4288UL))\r
+#define bFM3_ADC2_SCIS01_AN3                   *((volatile unsigned int*)(0x424E428CUL))\r
+#define bFM3_ADC2_SCIS01_AN4                   *((volatile unsigned int*)(0x424E4290UL))\r
+#define bFM3_ADC2_SCIS01_AN5                   *((volatile unsigned int*)(0x424E4294UL))\r
+#define bFM3_ADC2_SCIS01_AN6                   *((volatile unsigned int*)(0x424E4298UL))\r
+#define bFM3_ADC2_SCIS01_AN7                   *((volatile unsigned int*)(0x424E429CUL))\r
+#define bFM3_ADC2_SCIS01_AN8                   *((volatile unsigned int*)(0x424E42A0UL))\r
+#define bFM3_ADC2_SCIS01_AN9                   *((volatile unsigned int*)(0x424E42A4UL))\r
+#define bFM3_ADC2_SCIS01_AN10                  *((volatile unsigned int*)(0x424E42A8UL))\r
+#define bFM3_ADC2_SCIS01_AN11                  *((volatile unsigned int*)(0x424E42ACUL))\r
+#define bFM3_ADC2_SCIS01_AN12                  *((volatile unsigned int*)(0x424E42B0UL))\r
+#define bFM3_ADC2_SCIS01_AN13                  *((volatile unsigned int*)(0x424E42B4UL))\r
+#define bFM3_ADC2_SCIS01_AN14                  *((volatile unsigned int*)(0x424E42B8UL))\r
+#define bFM3_ADC2_SCIS01_AN15                  *((volatile unsigned int*)(0x424E42BCUL))\r
+#define bFM3_ADC2_SCIS0_AN0                    *((volatile unsigned int*)(0x424E4280UL))\r
+#define bFM3_ADC2_SCIS0_AN1                    *((volatile unsigned int*)(0x424E4284UL))\r
+#define bFM3_ADC2_SCIS0_AN2                    *((volatile unsigned int*)(0x424E4288UL))\r
+#define bFM3_ADC2_SCIS0_AN3                    *((volatile unsigned int*)(0x424E428CUL))\r
+#define bFM3_ADC2_SCIS0_AN4                    *((volatile unsigned int*)(0x424E4290UL))\r
+#define bFM3_ADC2_SCIS0_AN5                    *((volatile unsigned int*)(0x424E4294UL))\r
+#define bFM3_ADC2_SCIS0_AN6                    *((volatile unsigned int*)(0x424E4298UL))\r
+#define bFM3_ADC2_SCIS0_AN7                    *((volatile unsigned int*)(0x424E429CUL))\r
+#define bFM3_ADC2_SCIS1_AN8                    *((volatile unsigned int*)(0x424E42A0UL))\r
+#define bFM3_ADC2_SCIS1_AN9                    *((volatile unsigned int*)(0x424E42A4UL))\r
+#define bFM3_ADC2_SCIS1_AN10                   *((volatile unsigned int*)(0x424E42A8UL))\r
+#define bFM3_ADC2_SCIS1_AN11                   *((volatile unsigned int*)(0x424E42ACUL))\r
+#define bFM3_ADC2_SCIS1_AN12                   *((volatile unsigned int*)(0x424E42B0UL))\r
+#define bFM3_ADC2_SCIS1_AN13                   *((volatile unsigned int*)(0x424E42B4UL))\r
+#define bFM3_ADC2_SCIS1_AN14                   *((volatile unsigned int*)(0x424E42B8UL))\r
+#define bFM3_ADC2_SCIS1_AN15                   *((volatile unsigned int*)(0x424E42BCUL))\r
+#define bFM3_ADC2_PFNS_PFS0                    *((volatile unsigned int*)(0x424E4300UL))\r
+#define bFM3_ADC2_PFNS_PFS1                    *((volatile unsigned int*)(0x424E4304UL))\r
+#define bFM3_ADC2_PFNS_TEST0                   *((volatile unsigned int*)(0x424E4310UL))\r
+#define bFM3_ADC2_PFNS_TEST1                   *((volatile unsigned int*)(0x424E4314UL))\r
+#define bFM3_ADC2_PCCR_PSTR                    *((volatile unsigned int*)(0x424E4320UL))\r
+#define bFM3_ADC2_PCCR_PHEN                    *((volatile unsigned int*)(0x424E4324UL))\r
+#define bFM3_ADC2_PCCR_PEEN                    *((volatile unsigned int*)(0x424E4328UL))\r
+#define bFM3_ADC2_PCCR_ESCE                    *((volatile unsigned int*)(0x424E432CUL))\r
+#define bFM3_ADC2_PCCR_PFCLR                   *((volatile unsigned int*)(0x424E4330UL))\r
+#define bFM3_ADC2_PCCR_POVR                    *((volatile unsigned int*)(0x424E4334UL))\r
+#define bFM3_ADC2_PCCR_PFUL                    *((volatile unsigned int*)(0x424E4338UL))\r
+#define bFM3_ADC2_PCCR_PEMP                    *((volatile unsigned int*)(0x424E433CUL))\r
+#define bFM3_ADC2_PCFD_PC0                     *((volatile unsigned int*)(0x424E4380UL))\r
+#define bFM3_ADC2_PCFD_PC1                     *((volatile unsigned int*)(0x424E4384UL))\r
+#define bFM3_ADC2_PCFD_PC2                     *((volatile unsigned int*)(0x424E4388UL))\r
+#define bFM3_ADC2_PCFD_PC3                     *((volatile unsigned int*)(0x424E438CUL))\r
+#define bFM3_ADC2_PCFD_PC4                     *((volatile unsigned int*)(0x424E4390UL))\r
+#define bFM3_ADC2_PCFD_RS0                     *((volatile unsigned int*)(0x424E43A0UL))\r
+#define bFM3_ADC2_PCFD_RS1                     *((volatile unsigned int*)(0x424E43A4UL))\r
+#define bFM3_ADC2_PCFD_RS2                     *((volatile unsigned int*)(0x424E43A8UL))\r
+#define bFM3_ADC2_PCFD_INVL                    *((volatile unsigned int*)(0x424E43B0UL))\r
+#define bFM3_ADC2_PCFD_PD0                     *((volatile unsigned int*)(0x424E43D0UL))\r
+#define bFM3_ADC2_PCFD_PD1                     *((volatile unsigned int*)(0x424E43D4UL))\r
+#define bFM3_ADC2_PCFD_PD2                     *((volatile unsigned int*)(0x424E43D8UL))\r
+#define bFM3_ADC2_PCFD_PD3                     *((volatile unsigned int*)(0x424E43DCUL))\r
+#define bFM3_ADC2_PCFD_PD4                     *((volatile unsigned int*)(0x424E43E0UL))\r
+#define bFM3_ADC2_PCFD_PD5                     *((volatile unsigned int*)(0x424E43E4UL))\r
+#define bFM3_ADC2_PCFD_PD6                     *((volatile unsigned int*)(0x424E43E8UL))\r
+#define bFM3_ADC2_PCFD_PD7                     *((volatile unsigned int*)(0x424E43ECUL))\r
+#define bFM3_ADC2_PCFD_PD8                     *((volatile unsigned int*)(0x424E43F0UL))\r
+#define bFM3_ADC2_PCFD_PD9                     *((volatile unsigned int*)(0x424E43F4UL))\r
+#define bFM3_ADC2_PCFD_PD10                    *((volatile unsigned int*)(0x424E43F8UL))\r
+#define bFM3_ADC2_PCFD_PD11                    *((volatile unsigned int*)(0x424E43FCUL))\r
+#define bFM3_ADC2_PCFDL_PC0                    *((volatile unsigned int*)(0x424E4380UL))\r
+#define bFM3_ADC2_PCFDL_PC1                    *((volatile unsigned int*)(0x424E4384UL))\r
+#define bFM3_ADC2_PCFDL_PC2                    *((volatile unsigned int*)(0x424E4388UL))\r
+#define bFM3_ADC2_PCFDL_PC3                    *((volatile unsigned int*)(0x424E438CUL))\r
+#define bFM3_ADC2_PCFDL_PC4                    *((volatile unsigned int*)(0x424E4390UL))\r
+#define bFM3_ADC2_PCFDL_RS0                    *((volatile unsigned int*)(0x424E43A0UL))\r
+#define bFM3_ADC2_PCFDL_RS1                    *((volatile unsigned int*)(0x424E43A4UL))\r
+#define bFM3_ADC2_PCFDL_RS2                    *((volatile unsigned int*)(0x424E43A8UL))\r
+#define bFM3_ADC2_PCFDL_INVL                   *((volatile unsigned int*)(0x424E43B0UL))\r
+#define bFM3_ADC2_PCFDH_PD0                    *((volatile unsigned int*)(0x424E43D0UL))\r
+#define bFM3_ADC2_PCFDH_PD1                    *((volatile unsigned int*)(0x424E43D4UL))\r
+#define bFM3_ADC2_PCFDH_PD2                    *((volatile unsigned int*)(0x424E43D8UL))\r
+#define bFM3_ADC2_PCFDH_PD3                    *((volatile unsigned int*)(0x424E43DCUL))\r
+#define bFM3_ADC2_PCFDH_PD4                    *((volatile unsigned int*)(0x424E43E0UL))\r
+#define bFM3_ADC2_PCFDH_PD5                    *((volatile unsigned int*)(0x424E43E4UL))\r
+#define bFM3_ADC2_PCFDH_PD6                    *((volatile unsigned int*)(0x424E43E8UL))\r
+#define bFM3_ADC2_PCFDH_PD7                    *((volatile unsigned int*)(0x424E43ECUL))\r
+#define bFM3_ADC2_PCFDH_PD8                    *((volatile unsigned int*)(0x424E43F0UL))\r
+#define bFM3_ADC2_PCFDH_PD9                    *((volatile unsigned int*)(0x424E43F4UL))\r
+#define bFM3_ADC2_PCFDH_PD10                   *((volatile unsigned int*)(0x424E43F8UL))\r
+#define bFM3_ADC2_PCFDH_PD11                   *((volatile unsigned int*)(0x424E43FCUL))\r
+#define bFM3_ADC2_PCIS_P1A0                    *((volatile unsigned int*)(0x424E4400UL))\r
+#define bFM3_ADC2_PCIS_P1A1                    *((volatile unsigned int*)(0x424E4404UL))\r
+#define bFM3_ADC2_PCIS_P1A2                    *((volatile unsigned int*)(0x424E4408UL))\r
+#define bFM3_ADC2_PCIS_P2A0                    *((volatile unsigned int*)(0x424E440CUL))\r
+#define bFM3_ADC2_PCIS_P2A1                    *((volatile unsigned int*)(0x424E4410UL))\r
+#define bFM3_ADC2_PCIS_P2A2                    *((volatile unsigned int*)(0x424E4414UL))\r
+#define bFM3_ADC2_PCIS_P2A3                    *((volatile unsigned int*)(0x424E4418UL))\r
+#define bFM3_ADC2_PCIS_P2A4                    *((volatile unsigned int*)(0x424E441CUL))\r
+#define bFM3_ADC2_CMPCR_CCH0                   *((volatile unsigned int*)(0x424E4480UL))\r
+#define bFM3_ADC2_CMPCR_CCH1                   *((volatile unsigned int*)(0x424E4484UL))\r
+#define bFM3_ADC2_CMPCR_CCH2                   *((volatile unsigned int*)(0x424E4488UL))\r
+#define bFM3_ADC2_CMPCR_CCH3                   *((volatile unsigned int*)(0x424E448CUL))\r
+#define bFM3_ADC2_CMPCR_CCH4                   *((volatile unsigned int*)(0x424E4490UL))\r
+#define bFM3_ADC2_CMPCR_CMD0                   *((volatile unsigned int*)(0x424E4494UL))\r
+#define bFM3_ADC2_CMPCR_CMD1                   *((volatile unsigned int*)(0x424E4498UL))\r
+#define bFM3_ADC2_CMPCR_CMPEN                  *((volatile unsigned int*)(0x424E449CUL))\r
+#define bFM3_ADC2_CMPD_CMAD2                   *((volatile unsigned int*)(0x424E44D8UL))\r
+#define bFM3_ADC2_CMPD_CMAD3                   *((volatile unsigned int*)(0x424E44DCUL))\r
+#define bFM3_ADC2_CMPD_CMAD4                   *((volatile unsigned int*)(0x424E44E0UL))\r
+#define bFM3_ADC2_CMPD_CMAD5                   *((volatile unsigned int*)(0x424E44E4UL))\r
+#define bFM3_ADC2_CMPD_CMAD6                   *((volatile unsigned int*)(0x424E44E8UL))\r
+#define bFM3_ADC2_CMPD_CMAD7                   *((volatile unsigned int*)(0x424E44ECUL))\r
+#define bFM3_ADC2_CMPD_CMAD8                   *((volatile unsigned int*)(0x424E44F0UL))\r
+#define bFM3_ADC2_CMPD_CMAD9                   *((volatile unsigned int*)(0x424E44F4UL))\r
+#define bFM3_ADC2_CMPD_CMAD10                  *((volatile unsigned int*)(0x424E44F8UL))\r
+#define bFM3_ADC2_CMPD_CMAD11                  *((volatile unsigned int*)(0x424E44FCUL))\r
+#define bFM3_ADC2_ADSS23_TS16                  *((volatile unsigned int*)(0x424E4500UL))\r
+#define bFM3_ADC2_ADSS23_TS17                  *((volatile unsigned int*)(0x424E4504UL))\r
+#define bFM3_ADC2_ADSS23_TS18                  *((volatile unsigned int*)(0x424E4508UL))\r
+#define bFM3_ADC2_ADSS23_TS19                  *((volatile unsigned int*)(0x424E450CUL))\r
+#define bFM3_ADC2_ADSS23_TS20                  *((volatile unsigned int*)(0x424E4510UL))\r
+#define bFM3_ADC2_ADSS23_TS21                  *((volatile unsigned int*)(0x424E4514UL))\r
+#define bFM3_ADC2_ADSS23_TS22                  *((volatile unsigned int*)(0x424E4518UL))\r
+#define bFM3_ADC2_ADSS23_TS23                  *((volatile unsigned int*)(0x424E451CUL))\r
+#define bFM3_ADC2_ADSS23_TS24                  *((volatile unsigned int*)(0x424E4520UL))\r
+#define bFM3_ADC2_ADSS23_TS25                  *((volatile unsigned int*)(0x424E4524UL))\r
+#define bFM3_ADC2_ADSS23_TS26                  *((volatile unsigned int*)(0x424E4528UL))\r
+#define bFM3_ADC2_ADSS23_TS27                  *((volatile unsigned int*)(0x424E452CUL))\r
+#define bFM3_ADC2_ADSS23_TS28                  *((volatile unsigned int*)(0x424E4530UL))\r
+#define bFM3_ADC2_ADSS23_TS29                  *((volatile unsigned int*)(0x424E4534UL))\r
+#define bFM3_ADC2_ADSS23_TS30                  *((volatile unsigned int*)(0x424E4538UL))\r
+#define bFM3_ADC2_ADSS23_TS31                  *((volatile unsigned int*)(0x424E453CUL))\r
+#define bFM3_ADC2_ADSS2_TS16                   *((volatile unsigned int*)(0x424E4500UL))\r
+#define bFM3_ADC2_ADSS2_TS17                   *((volatile unsigned int*)(0x424E4504UL))\r
+#define bFM3_ADC2_ADSS2_TS18                   *((volatile unsigned int*)(0x424E4508UL))\r
+#define bFM3_ADC2_ADSS2_TS19                   *((volatile unsigned int*)(0x424E450CUL))\r
+#define bFM3_ADC2_ADSS2_TS20                   *((volatile unsigned int*)(0x424E4510UL))\r
+#define bFM3_ADC2_ADSS2_TS21                   *((volatile unsigned int*)(0x424E4514UL))\r
+#define bFM3_ADC2_ADSS2_TS22                   *((volatile unsigned int*)(0x424E4518UL))\r
+#define bFM3_ADC2_ADSS2_TS23                   *((volatile unsigned int*)(0x424E451CUL))\r
+#define bFM3_ADC2_ADSS3_TS24                   *((volatile unsigned int*)(0x424E4520UL))\r
+#define bFM3_ADC2_ADSS3_TS25                   *((volatile unsigned int*)(0x424E4524UL))\r
+#define bFM3_ADC2_ADSS3_TS26                   *((volatile unsigned int*)(0x424E4528UL))\r
+#define bFM3_ADC2_ADSS3_TS27                   *((volatile unsigned int*)(0x424E452CUL))\r
+#define bFM3_ADC2_ADSS3_TS28                   *((volatile unsigned int*)(0x424E4530UL))\r
+#define bFM3_ADC2_ADSS3_TS29                   *((volatile unsigned int*)(0x424E4534UL))\r
+#define bFM3_ADC2_ADSS3_TS30                   *((volatile unsigned int*)(0x424E4538UL))\r
+#define bFM3_ADC2_ADSS3_TS31                   *((volatile unsigned int*)(0x424E453CUL))\r
+#define bFM3_ADC2_ADSS01_TS0                   *((volatile unsigned int*)(0x424E4580UL))\r
+#define bFM3_ADC2_ADSS01_TS1                   *((volatile unsigned int*)(0x424E4584UL))\r
+#define bFM3_ADC2_ADSS01_TS2                   *((volatile unsigned int*)(0x424E4588UL))\r
+#define bFM3_ADC2_ADSS01_TS3                   *((volatile unsigned int*)(0x424E458CUL))\r
+#define bFM3_ADC2_ADSS01_TS4                   *((volatile unsigned int*)(0x424E4590UL))\r
+#define bFM3_ADC2_ADSS01_TS5                   *((volatile unsigned int*)(0x424E4594UL))\r
+#define bFM3_ADC2_ADSS01_TS6                   *((volatile unsigned int*)(0x424E4598UL))\r
+#define bFM3_ADC2_ADSS01_TS7                   *((volatile unsigned int*)(0x424E459CUL))\r
+#define bFM3_ADC2_ADSS01_TS8                   *((volatile unsigned int*)(0x424E45A0UL))\r
+#define bFM3_ADC2_ADSS01_TS9                   *((volatile unsigned int*)(0x424E45A4UL))\r
+#define bFM3_ADC2_ADSS01_TS10                  *((volatile unsigned int*)(0x424E45A8UL))\r
+#define bFM3_ADC2_ADSS01_TS11                  *((volatile unsigned int*)(0x424E45ACUL))\r
+#define bFM3_ADC2_ADSS01_TS12                  *((volatile unsigned int*)(0x424E45B0UL))\r
+#define bFM3_ADC2_ADSS01_TS13                  *((volatile unsigned int*)(0x424E45B4UL))\r
+#define bFM3_ADC2_ADSS01_TS14                  *((volatile unsigned int*)(0x424E45B8UL))\r
+#define bFM3_ADC2_ADSS01_TS15                  *((volatile unsigned int*)(0x424E45BCUL))\r
+#define bFM3_ADC2_ADSS0_TS0                    *((volatile unsigned int*)(0x424E4580UL))\r
+#define bFM3_ADC2_ADSS0_TS1                    *((volatile unsigned int*)(0x424E4584UL))\r
+#define bFM3_ADC2_ADSS0_TS2                    *((volatile unsigned int*)(0x424E4588UL))\r
+#define bFM3_ADC2_ADSS0_TS3                    *((volatile unsigned int*)(0x424E458CUL))\r
+#define bFM3_ADC2_ADSS0_TS4                    *((volatile unsigned int*)(0x424E4590UL))\r
+#define bFM3_ADC2_ADSS0_TS5                    *((volatile unsigned int*)(0x424E4594UL))\r
+#define bFM3_ADC2_ADSS0_TS6                    *((volatile unsigned int*)(0x424E4598UL))\r
+#define bFM3_ADC2_ADSS0_TS7                    *((volatile unsigned int*)(0x424E459CUL))\r
+#define bFM3_ADC2_ADSS1_TS8                    *((volatile unsigned int*)(0x424E45A0UL))\r
+#define bFM3_ADC2_ADSS1_TS9                    *((volatile unsigned int*)(0x424E45A4UL))\r
+#define bFM3_ADC2_ADSS1_TS10                   *((volatile unsigned int*)(0x424E45A8UL))\r
+#define bFM3_ADC2_ADSS1_TS11                   *((volatile unsigned int*)(0x424E45ACUL))\r
+#define bFM3_ADC2_ADSS1_TS12                   *((volatile unsigned int*)(0x424E45B0UL))\r
+#define bFM3_ADC2_ADSS1_TS13                   *((volatile unsigned int*)(0x424E45B4UL))\r
+#define bFM3_ADC2_ADSS1_TS14                   *((volatile unsigned int*)(0x424E45B8UL))\r
+#define bFM3_ADC2_ADSS1_TS15                   *((volatile unsigned int*)(0x424E45BCUL))\r
+#define bFM3_ADC2_ADST01_ST10                  *((volatile unsigned int*)(0x424E4600UL))\r
+#define bFM3_ADC2_ADST01_ST11                  *((volatile unsigned int*)(0x424E4604UL))\r
+#define bFM3_ADC2_ADST01_ST12                  *((volatile unsigned int*)(0x424E4608UL))\r
+#define bFM3_ADC2_ADST01_ST13                  *((volatile unsigned int*)(0x424E460CUL))\r
+#define bFM3_ADC2_ADST01_ST14                  *((volatile unsigned int*)(0x424E4610UL))\r
+#define bFM3_ADC2_ADST01_STX10                 *((volatile unsigned int*)(0x424E4614UL))\r
+#define bFM3_ADC2_ADST01_STX11                 *((volatile unsigned int*)(0x424E4618UL))\r
+#define bFM3_ADC2_ADST01_STX12                 *((volatile unsigned int*)(0x424E461CUL))\r
+#define bFM3_ADC2_ADST01_ST00                  *((volatile unsigned int*)(0x424E4620UL))\r
+#define bFM3_ADC2_ADST01_ST01                  *((volatile unsigned int*)(0x424E4624UL))\r
+#define bFM3_ADC2_ADST01_ST02                  *((volatile unsigned int*)(0x424E4628UL))\r
+#define bFM3_ADC2_ADST01_ST03                  *((volatile unsigned int*)(0x424E462CUL))\r
+#define bFM3_ADC2_ADST01_ST04                  *((volatile unsigned int*)(0x424E4630UL))\r
+#define bFM3_ADC2_ADST01_STX00                 *((volatile unsigned int*)(0x424E4634UL))\r
+#define bFM3_ADC2_ADST01_STX01                 *((volatile unsigned int*)(0x424E4638UL))\r
+#define bFM3_ADC2_ADST01_STX02                 *((volatile unsigned int*)(0x424E463CUL))\r
+#define bFM3_ADC2_ADST1_ST10                   *((volatile unsigned int*)(0x424E4600UL))\r
+#define bFM3_ADC2_ADST1_ST11                   *((volatile unsigned int*)(0x424E4604UL))\r
+#define bFM3_ADC2_ADST1_ST12                   *((volatile unsigned int*)(0x424E4608UL))\r
+#define bFM3_ADC2_ADST1_ST13                   *((volatile unsigned int*)(0x424E460CUL))\r
+#define bFM3_ADC2_ADST1_ST14                   *((volatile unsigned int*)(0x424E4610UL))\r
+#define bFM3_ADC2_ADST1_STX10                  *((volatile unsigned int*)(0x424E4614UL))\r
+#define bFM3_ADC2_ADST1_STX11                  *((volatile unsigned int*)(0x424E4618UL))\r
+#define bFM3_ADC2_ADST1_STX12                  *((volatile unsigned int*)(0x424E461CUL))\r
+#define bFM3_ADC2_ADST0_ST00                   *((volatile unsigned int*)(0x424E4620UL))\r
+#define bFM3_ADC2_ADST0_ST01                   *((volatile unsigned int*)(0x424E4624UL))\r
+#define bFM3_ADC2_ADST0_ST02                   *((volatile unsigned int*)(0x424E4628UL))\r
+#define bFM3_ADC2_ADST0_ST03                   *((volatile unsigned int*)(0x424E462CUL))\r
+#define bFM3_ADC2_ADST0_ST04                   *((volatile unsigned int*)(0x424E4630UL))\r
+#define bFM3_ADC2_ADST0_STX00                  *((volatile unsigned int*)(0x424E4634UL))\r
+#define bFM3_ADC2_ADST0_STX01                  *((volatile unsigned int*)(0x424E4638UL))\r
+#define bFM3_ADC2_ADST0_STX02                  *((volatile unsigned int*)(0x424E463CUL))\r
+#define bFM3_ADC2_ADCT_CT0                     *((volatile unsigned int*)(0x424E4680UL))\r
+#define bFM3_ADC2_ADCT_CT1                     *((volatile unsigned int*)(0x424E4684UL))\r
+#define bFM3_ADC2_ADCT_CT2                     *((volatile unsigned int*)(0x424E4688UL))\r
+#define bFM3_ADC2_PRTSL_PRTSL0                 *((volatile unsigned int*)(0x424E4700UL))\r
+#define bFM3_ADC2_PRTSL_PRTSL1                 *((volatile unsigned int*)(0x424E4704UL))\r
+#define bFM3_ADC2_PRTSL_PRTSL2                 *((volatile unsigned int*)(0x424E4708UL))\r
+#define bFM3_ADC2_PRTSL_PRTSL3                 *((volatile unsigned int*)(0x424E470CUL))\r
+#define bFM3_ADC2_SCTSL_SCTSL0                 *((volatile unsigned int*)(0x424E4720UL))\r
+#define bFM3_ADC2_SCTSL_SCTSL1                 *((volatile unsigned int*)(0x424E4724UL))\r
+#define bFM3_ADC2_SCTSL_SCTSL2                 *((volatile unsigned int*)(0x424E4728UL))\r
+#define bFM3_ADC2_SCTSL_SCTSL3                 *((volatile unsigned int*)(0x424E472CUL))\r
+#define bFM3_ADC2_ADCEN_ENBL                   *((volatile unsigned int*)(0x424E4780UL))\r
+#define bFM3_ADC2_ADCEN_READY                  *((volatile unsigned int*)(0x424E4784UL))\r
+\r
+/* CR trimming registers */\r
+#define bFM3_CRTRIM_MCR_PSR_CSR0               *((volatile unsigned int*)(0x425C0000UL))\r
+#define bFM3_CRTRIM_MCR_PSR_CSR1               *((volatile unsigned int*)(0x425C0004UL))\r
+#define bFM3_CRTRIM_MCR_FTRM_TRD0              *((volatile unsigned int*)(0x425C0080UL))\r
+#define bFM3_CRTRIM_MCR_FTRM_TRD1              *((volatile unsigned int*)(0x425C0084UL))\r
+#define bFM3_CRTRIM_MCR_FTRM_TRD2              *((volatile unsigned int*)(0x425C0088UL))\r
+#define bFM3_CRTRIM_MCR_FTRM_TRD3              *((volatile unsigned int*)(0x425C008CUL))\r
+#define bFM3_CRTRIM_MCR_FTRM_TRD4              *((volatile unsigned int*)(0x425C0090UL))\r
+#define bFM3_CRTRIM_MCR_FTRM_TRD5              *((volatile unsigned int*)(0x425C0094UL))\r
+#define bFM3_CRTRIM_MCR_FTRM_TRD6              *((volatile unsigned int*)(0x425C0098UL))\r
+#define bFM3_CRTRIM_MCR_FTRM_TRD7              *((volatile unsigned int*)(0x425C009CUL))\r
+#define bFM3_CRTRIM_MCR_FTRM_TRD8              *((volatile unsigned int*)(0x425C00A0UL))\r
+#define bFM3_CRTRIM_MCR_FTRM_TRD9              *((volatile unsigned int*)(0x425C00A4UL))\r
+\r
+/* External interrupt registers */\r
+#define bFM3_EXTI_ENIR_EN0                     *((volatile unsigned int*)(0x42600000UL))\r
+#define bFM3_EXTI_ENIR_EN1                     *((volatile unsigned int*)(0x42600004UL))\r
+#define bFM3_EXTI_ENIR_EN2                     *((volatile unsigned int*)(0x42600008UL))\r
+#define bFM3_EXTI_ENIR_EN3                     *((volatile unsigned int*)(0x4260000CUL))\r
+#define bFM3_EXTI_ENIR_EN4                     *((volatile unsigned int*)(0x42600010UL))\r
+#define bFM3_EXTI_ENIR_EN5                     *((volatile unsigned int*)(0x42600014UL))\r
+#define bFM3_EXTI_ENIR_EN6                     *((volatile unsigned int*)(0x42600018UL))\r
+#define bFM3_EXTI_ENIR_EN7                     *((volatile unsigned int*)(0x4260001CUL))\r
+#define bFM3_EXTI_ENIR_EN8                     *((volatile unsigned int*)(0x42600020UL))\r
+#define bFM3_EXTI_ENIR_EN9                     *((volatile unsigned int*)(0x42600024UL))\r
+#define bFM3_EXTI_ENIR_EN10                    *((volatile unsigned int*)(0x42600028UL))\r
+#define bFM3_EXTI_ENIR_EN11                    *((volatile unsigned int*)(0x4260002CUL))\r
+#define bFM3_EXTI_ENIR_EN12                    *((volatile unsigned int*)(0x42600030UL))\r
+#define bFM3_EXTI_ENIR_EN13                    *((volatile unsigned int*)(0x42600034UL))\r
+#define bFM3_EXTI_ENIR_EN14                    *((volatile unsigned int*)(0x42600038UL))\r
+#define bFM3_EXTI_ENIR_EN15                    *((volatile unsigned int*)(0x4260003CUL))\r
+#define bFM3_EXTI_EIRR_ER0                     *((volatile unsigned int*)(0x42600080UL))\r
+#define bFM3_EXTI_EIRR_ER1                     *((volatile unsigned int*)(0x42600084UL))\r
+#define bFM3_EXTI_EIRR_ER2                     *((volatile unsigned int*)(0x42600088UL))\r
+#define bFM3_EXTI_EIRR_ER3                     *((volatile unsigned int*)(0x4260008CUL))\r
+#define bFM3_EXTI_EIRR_ER4                     *((volatile unsigned int*)(0x42600090UL))\r
+#define bFM3_EXTI_EIRR_ER5                     *((volatile unsigned int*)(0x42600094UL))\r
+#define bFM3_EXTI_EIRR_ER6                     *((volatile unsigned int*)(0x42600098UL))\r
+#define bFM3_EXTI_EIRR_ER7                     *((volatile unsigned int*)(0x4260009CUL))\r
+#define bFM3_EXTI_EIRR_ER8                     *((volatile unsigned int*)(0x426000A0UL))\r
+#define bFM3_EXTI_EIRR_ER9                     *((volatile unsigned int*)(0x426000A4UL))\r
+#define bFM3_EXTI_EIRR_ER10                    *((volatile unsigned int*)(0x426000A8UL))\r
+#define bFM3_EXTI_EIRR_ER11                    *((volatile unsigned int*)(0x426000ACUL))\r
+#define bFM3_EXTI_EIRR_ER12                    *((volatile unsigned int*)(0x426000B0UL))\r
+#define bFM3_EXTI_EIRR_ER13                    *((volatile unsigned int*)(0x426000B4UL))\r
+#define bFM3_EXTI_EIRR_ER14                    *((volatile unsigned int*)(0x426000B8UL))\r
+#define bFM3_EXTI_EIRR_ER15                    *((volatile unsigned int*)(0x426000BCUL))\r
+#define bFM3_EXTI_EICL_ECL0                    *((volatile unsigned int*)(0x42600100UL))\r
+#define bFM3_EXTI_EICL_ECL1                    *((volatile unsigned int*)(0x42600104UL))\r
+#define bFM3_EXTI_EICL_ECL2                    *((volatile unsigned int*)(0x42600108UL))\r
+#define bFM3_EXTI_EICL_ECL3                    *((volatile unsigned int*)(0x4260010CUL))\r
+#define bFM3_EXTI_EICL_ECL4                    *((volatile unsigned int*)(0x42600110UL))\r
+#define bFM3_EXTI_EICL_ECL5                    *((volatile unsigned int*)(0x42600114UL))\r
+#define bFM3_EXTI_EICL_ECL6                    *((volatile unsigned int*)(0x42600118UL))\r
+#define bFM3_EXTI_EICL_ECL7                    *((volatile unsigned int*)(0x4260011CUL))\r
+#define bFM3_EXTI_EICL_ECL8                    *((volatile unsigned int*)(0x42600120UL))\r
+#define bFM3_EXTI_EICL_ECL9                    *((volatile unsigned int*)(0x42600124UL))\r
+#define bFM3_EXTI_EICL_ECL10                   *((volatile unsigned int*)(0x42600128UL))\r
+#define bFM3_EXTI_EICL_ECL11                   *((volatile unsigned int*)(0x4260012CUL))\r
+#define bFM3_EXTI_EICL_ECL12                   *((volatile unsigned int*)(0x42600130UL))\r
+#define bFM3_EXTI_EICL_ECL13                   *((volatile unsigned int*)(0x42600134UL))\r
+#define bFM3_EXTI_EICL_ECL14                   *((volatile unsigned int*)(0x42600138UL))\r
+#define bFM3_EXTI_EICL_ECL15                   *((volatile unsigned int*)(0x4260013CUL))\r
+#define bFM3_EXTI_ELVR_LA0                     *((volatile unsigned int*)(0x42600180UL))\r
+#define bFM3_EXTI_ELVR_LB0                     *((volatile unsigned int*)(0x42600184UL))\r
+#define bFM3_EXTI_ELVR_LA1                     *((volatile unsigned int*)(0x42600188UL))\r
+#define bFM3_EXTI_ELVR_LB1                     *((volatile unsigned int*)(0x4260018CUL))\r
+#define bFM3_EXTI_ELVR_LA2                     *((volatile unsigned int*)(0x42600190UL))\r
+#define bFM3_EXTI_ELVR_LB2                     *((volatile unsigned int*)(0x42600194UL))\r
+#define bFM3_EXTI_ELVR_LA3                     *((volatile unsigned int*)(0x42600198UL))\r
+#define bFM3_EXTI_ELVR_LB3                     *((volatile unsigned int*)(0x4260019CUL))\r
+#define bFM3_EXTI_ELVR_LA4                     *((volatile unsigned int*)(0x426001A0UL))\r
+#define bFM3_EXTI_ELVR_LB4                     *((volatile unsigned int*)(0x426001A4UL))\r
+#define bFM3_EXTI_ELVR_LA5                     *((volatile unsigned int*)(0x426001A8UL))\r
+#define bFM3_EXTI_ELVR_LB5                     *((volatile unsigned int*)(0x426001ACUL))\r
+#define bFM3_EXTI_ELVR_LA6                     *((volatile unsigned int*)(0x426001B0UL))\r
+#define bFM3_EXTI_ELVR_LB6                     *((volatile unsigned int*)(0x426001B4UL))\r
+#define bFM3_EXTI_ELVR_LA7                     *((volatile unsigned int*)(0x426001B8UL))\r
+#define bFM3_EXTI_ELVR_LB7                     *((volatile unsigned int*)(0x426001BCUL))\r
+#define bFM3_EXTI_ELVR_LA8                     *((volatile unsigned int*)(0x426001C0UL))\r
+#define bFM3_EXTI_ELVR_LB8                     *((volatile unsigned int*)(0x426001C4UL))\r
+#define bFM3_EXTI_ELVR_LA9                     *((volatile unsigned int*)(0x426001C8UL))\r
+#define bFM3_EXTI_ELVR_LB9                     *((volatile unsigned int*)(0x426001CCUL))\r
+#define bFM3_EXTI_ELVR_LA10                    *((volatile unsigned int*)(0x426001D0UL))\r
+#define bFM3_EXTI_ELVR_LB10                    *((volatile unsigned int*)(0x426001D4UL))\r
+#define bFM3_EXTI_ELVR_LA11                    *((volatile unsigned int*)(0x426001D8UL))\r
+#define bFM3_EXTI_ELVR_LB11                    *((volatile unsigned int*)(0x426001DCUL))\r
+#define bFM3_EXTI_ELVR_LA12                    *((volatile unsigned int*)(0x426001E0UL))\r
+#define bFM3_EXTI_ELVR_LB12                    *((volatile unsigned int*)(0x426001E4UL))\r
+#define bFM3_EXTI_ELVR_LA13                    *((volatile unsigned int*)(0x426001E8UL))\r
+#define bFM3_EXTI_ELVR_LB13                    *((volatile unsigned int*)(0x426001ECUL))\r
+#define bFM3_EXTI_ELVR_LA14                    *((volatile unsigned int*)(0x426001F0UL))\r
+#define bFM3_EXTI_ELVR_LB14                    *((volatile unsigned int*)(0x426001F4UL))\r
+#define bFM3_EXTI_ELVR_LA15                    *((volatile unsigned int*)(0x426001F8UL))\r
+#define bFM3_EXTI_ELVR_LB15                    *((volatile unsigned int*)(0x426001FCUL))\r
+#define bFM3_EXTI_NMIRR_NR0                    *((volatile unsigned int*)(0x42600280UL))\r
+#define bFM3_EXTI_NMICL_NCL0                   *((volatile unsigned int*)(0x42600300UL))\r
+\r
+/* Interrupt request read registers */\r
+#define bFM3_INTREQ_DRQSEL_DRQSEL0             *((volatile unsigned int*)(0x42620000UL))\r
+#define bFM3_INTREQ_DRQSEL_DRQSEL1             *((volatile unsigned int*)(0x42620004UL))\r
+#define bFM3_INTREQ_DRQSEL_DRQSEL2             *((volatile unsigned int*)(0x42620008UL))\r
+#define bFM3_INTREQ_DRQSEL_DRQSEL3             *((volatile unsigned int*)(0x4262000CUL))\r
+#define bFM3_INTREQ_DRQSEL_DRQSEL4             *((volatile unsigned int*)(0x42620010UL))\r
+#define bFM3_INTREQ_DRQSEL_DRQSEL5             *((volatile unsigned int*)(0x42620014UL))\r
+#define bFM3_INTREQ_DRQSEL_DRQSEL6             *((volatile unsigned int*)(0x42620018UL))\r
+#define bFM3_INTREQ_DRQSEL_DRQSEL7             *((volatile unsigned int*)(0x4262001CUL))\r
+#define bFM3_INTREQ_DRQSEL_DRQSEL8             *((volatile unsigned int*)(0x42620020UL))\r
+#define bFM3_INTREQ_DRQSEL_DRQSEL9             *((volatile unsigned int*)(0x42620024UL))\r
+#define bFM3_INTREQ_DRQSEL_DRQSEL10            *((volatile unsigned int*)(0x42620028UL))\r
+#define bFM3_INTREQ_DRQSEL_DRQSEL11            *((volatile unsigned int*)(0x4262002CUL))\r
+#define bFM3_INTREQ_DRQSEL_DRQSEL12            *((volatile unsigned int*)(0x42620030UL))\r
+#define bFM3_INTREQ_DRQSEL_DRQSEL13            *((volatile unsigned int*)(0x42620034UL))\r
+#define bFM3_INTREQ_DRQSEL_DRQSEL14            *((volatile unsigned int*)(0x42620038UL))\r
+#define bFM3_INTREQ_DRQSEL_DRQSEL15            *((volatile unsigned int*)(0x4262003CUL))\r
+#define bFM3_INTREQ_DRQSEL_DRQSEL16            *((volatile unsigned int*)(0x42620040UL))\r
+#define bFM3_INTREQ_DRQSEL_DRQSEL17            *((volatile unsigned int*)(0x42620044UL))\r
+#define bFM3_INTREQ_DRQSEL_DRQSEL18            *((volatile unsigned int*)(0x42620048UL))\r
+#define bFM3_INTREQ_DRQSEL_DRQSEL19            *((volatile unsigned int*)(0x4262004CUL))\r
+#define bFM3_INTREQ_DRQSEL_DRQSEL20            *((volatile unsigned int*)(0x42620050UL))\r
+#define bFM3_INTREQ_DRQSEL_DRQSEL21            *((volatile unsigned int*)(0x42620054UL))\r
+#define bFM3_INTREQ_DRQSEL_DRQSEL22            *((volatile unsigned int*)(0x42620058UL))\r
+#define bFM3_INTREQ_DRQSEL_DRQSEL23            *((volatile unsigned int*)(0x4262005CUL))\r
+#define bFM3_INTREQ_DRQSEL_DRQSEL24            *((volatile unsigned int*)(0x42620060UL))\r
+#define bFM3_INTREQ_DRQSEL_DRQSEL25            *((volatile unsigned int*)(0x42620064UL))\r
+#define bFM3_INTREQ_DRQSEL_DRQSEL26            *((volatile unsigned int*)(0x42620068UL))\r
+#define bFM3_INTREQ_DRQSEL_DRQSEL27            *((volatile unsigned int*)(0x4262006CUL))\r
+#define bFM3_INTREQ_DRQSEL_DRQSEL28            *((volatile unsigned int*)(0x42620070UL))\r
+#define bFM3_INTREQ_DRQSEL_DRQSEL29            *((volatile unsigned int*)(0x42620074UL))\r
+#define bFM3_INTREQ_DRQSEL_DRQSEL30            *((volatile unsigned int*)(0x42620078UL))\r
+#define bFM3_INTREQ_DRQSEL_DRQSEL31            *((volatile unsigned int*)(0x4262007CUL))\r
+#define bFM3_INTREQ_EXC02MON_NMI               *((volatile unsigned int*)(0x42620200UL))\r
+#define bFM3_INTREQ_EXC02MON_HWINT             *((volatile unsigned int*)(0x42620204UL))\r
+#define bFM3_INTREQ_IRQ00MON_FCSINT            *((volatile unsigned int*)(0x42620280UL))\r
+#define bFM3_INTREQ_IRQ01MON_SWWDTINT          *((volatile unsigned int*)(0x42620300UL))\r
+#define bFM3_INTREQ_IRQ02MON_LVDINT            *((volatile unsigned int*)(0x42620380UL))\r
+#define bFM3_INTREQ_IRQ03MON_WAVE0INT0         *((volatile unsigned int*)(0x42620400UL))\r
+#define bFM3_INTREQ_IRQ03MON_WAVE0INT1         *((volatile unsigned int*)(0x42620404UL))\r
+#define bFM3_INTREQ_IRQ03MON_WAVE0INT2         *((volatile unsigned int*)(0x42620408UL))\r
+#define bFM3_INTREQ_IRQ03MON_WAVE0INT3         *((volatile unsigned int*)(0x4262040CUL))\r
+#define bFM3_INTREQ_IRQ03MON_WAVE1INT0         *((volatile unsigned int*)(0x42620410UL))\r
+#define bFM3_INTREQ_IRQ03MON_WAVE1INT1         *((volatile unsigned int*)(0x42620414UL))\r
+#define bFM3_INTREQ_IRQ03MON_WAVE1INT2         *((volatile unsigned int*)(0x42620418UL))\r
+#define bFM3_INTREQ_IRQ03MON_WAVE1INT3         *((volatile unsigned int*)(0x4262041CUL))\r
+#define bFM3_INTREQ_IRQ04MON_EXTINT0           *((volatile unsigned int*)(0x42620480UL))\r
+#define bFM3_INTREQ_IRQ04MON_EXTINT1           *((volatile unsigned int*)(0x42620484UL))\r
+#define bFM3_INTREQ_IRQ04MON_EXTINT2           *((volatile unsigned int*)(0x42620488UL))\r
+#define bFM3_INTREQ_IRQ04MON_EXTINT3           *((volatile unsigned int*)(0x4262048CUL))\r
+#define bFM3_INTREQ_IRQ04MON_EXTINT4           *((volatile unsigned int*)(0x42620490UL))\r
+#define bFM3_INTREQ_IRQ04MON_EXTINT5           *((volatile unsigned int*)(0x42620494UL))\r
+#define bFM3_INTREQ_IRQ04MON_EXTINT6           *((volatile unsigned int*)(0x42620498UL))\r
+#define bFM3_INTREQ_IRQ04MON_EXTINT7           *((volatile unsigned int*)(0x4262049CUL))\r
+#define bFM3_INTREQ_IRQ05MON_EXTINT0           *((volatile unsigned int*)(0x42620500UL))\r
+#define bFM3_INTREQ_IRQ05MON_EXTINT1           *((volatile unsigned int*)(0x42620504UL))\r
+#define bFM3_INTREQ_IRQ05MON_EXTINT2           *((volatile unsigned int*)(0x42620508UL))\r
+#define bFM3_INTREQ_IRQ05MON_EXTINT3           *((volatile unsigned int*)(0x4262050CUL))\r
+#define bFM3_INTREQ_IRQ05MON_EXTINT4           *((volatile unsigned int*)(0x42620510UL))\r
+#define bFM3_INTREQ_IRQ05MON_EXTINT5           *((volatile unsigned int*)(0x42620514UL))\r
+#define bFM3_INTREQ_IRQ05MON_EXTINT6           *((volatile unsigned int*)(0x42620518UL))\r
+#define bFM3_INTREQ_IRQ05MON_EXTINT7           *((volatile unsigned int*)(0x4262051CUL))\r
+#define bFM3_INTREQ_IRQ06MON_TIMINT0           *((volatile unsigned int*)(0x42620580UL))\r
+#define bFM3_INTREQ_IRQ06MON_TIMINT1           *((volatile unsigned int*)(0x42620584UL))\r
+#define bFM3_INTREQ_IRQ06MON_QUD0INT0          *((volatile unsigned int*)(0x42620588UL))\r
+#define bFM3_INTREQ_IRQ06MON_QUD0INT1          *((volatile unsigned int*)(0x4262058CUL))\r
+#define bFM3_INTREQ_IRQ06MON_QUD0INT2          *((volatile unsigned int*)(0x42620590UL))\r
+#define bFM3_INTREQ_IRQ06MON_QUD0INT3          *((volatile unsigned int*)(0x42620594UL))\r
+#define bFM3_INTREQ_IRQ06MON_QUD0INT4          *((volatile unsigned int*)(0x42620598UL))\r
+#define bFM3_INTREQ_IRQ06MON_QUD0INT5          *((volatile unsigned int*)(0x4262059CUL))\r
+#define bFM3_INTREQ_IRQ06MON_QUD1INT0          *((volatile unsigned int*)(0x426205A0UL))\r
+#define bFM3_INTREQ_IRQ06MON_QUD1INT1          *((volatile unsigned int*)(0x426205A4UL))\r
+#define bFM3_INTREQ_IRQ06MON_QUD1INT2          *((volatile unsigned int*)(0x426205A8UL))\r
+#define bFM3_INTREQ_IRQ06MON_QUD1INT3          *((volatile unsigned int*)(0x426205ACUL))\r
+#define bFM3_INTREQ_IRQ06MON_QUD1INT4          *((volatile unsigned int*)(0x426205B0UL))\r
+#define bFM3_INTREQ_IRQ06MON_QUD1INT5          *((volatile unsigned int*)(0x426205B4UL))\r
+#define bFM3_INTREQ_IRQ07MON_FMSINT            *((volatile unsigned int*)(0x42620600UL))\r
+#define bFM3_INTREQ_IRQ08MON_MFSINT0           *((volatile unsigned int*)(0x42620680UL))\r
+#define bFM3_INTREQ_IRQ08MON_MFSINT1           *((volatile unsigned int*)(0x42620684UL))\r
+#define bFM3_INTREQ_IRQ09MON_FMSINT            *((volatile unsigned int*)(0x42620700UL))\r
+#define bFM3_INTREQ_IRQ10MON_MFSINT0           *((volatile unsigned int*)(0x42620780UL))\r
+#define bFM3_INTREQ_IRQ10MON_MFSINT1           *((volatile unsigned int*)(0x42620784UL))\r
+#define bFM3_INTREQ_IRQ11MON_FMSINT            *((volatile unsigned int*)(0x42620800UL))\r
+#define bFM3_INTREQ_IRQ12MON_MFSINT0           *((volatile unsigned int*)(0x42620880UL))\r
+#define bFM3_INTREQ_IRQ12MON_MFSINT1           *((volatile unsigned int*)(0x42620884UL))\r
+#define bFM3_INTREQ_IRQ13MON_FMSINT            *((volatile unsigned int*)(0x42620900UL))\r
+#define bFM3_INTREQ_IRQ14MON_MFSINT0           *((volatile unsigned int*)(0x42620980UL))\r
+#define bFM3_INTREQ_IRQ14MON_MFSINT1           *((volatile unsigned int*)(0x42620984UL))\r
+#define bFM3_INTREQ_IRQ15MON_FMSINT            *((volatile unsigned int*)(0x42620A00UL))\r
+#define bFM3_INTREQ_IRQ16MON_MFSINT0           *((volatile unsigned int*)(0x42620A80UL))\r
+#define bFM3_INTREQ_IRQ16MON_MFSINT1           *((volatile unsigned int*)(0x42620A84UL))\r
+#define bFM3_INTREQ_IRQ17MON_FMSINT            *((volatile unsigned int*)(0x42620B00UL))\r
+#define bFM3_INTREQ_IRQ18MON_MFSINT0           *((volatile unsigned int*)(0x42620B80UL))\r
+#define bFM3_INTREQ_IRQ18MON_MFSINT1           *((volatile unsigned int*)(0x42620B84UL))\r
+#define bFM3_INTREQ_IRQ19MON_FMSINT            *((volatile unsigned int*)(0x42620C00UL))\r
+#define bFM3_INTREQ_IRQ20MON_MFSINT0           *((volatile unsigned int*)(0x42620C80UL))\r
+#define bFM3_INTREQ_IRQ20MON_MFSINT1           *((volatile unsigned int*)(0x42620C84UL))\r
+#define bFM3_INTREQ_IRQ21MON_FMSINT            *((volatile unsigned int*)(0x42620D00UL))\r
+#define bFM3_INTREQ_IRQ22MON_MFSINT0           *((volatile unsigned int*)(0x42620D80UL))\r
+#define bFM3_INTREQ_IRQ22MON_MFSINT1           *((volatile unsigned int*)(0x42620D84UL))\r
+#define bFM3_INTREQ_IRQ23MON_PPGINT0           *((volatile unsigned int*)(0x42620E00UL))\r
+#define bFM3_INTREQ_IRQ23MON_PPGINT1           *((volatile unsigned int*)(0x42620E04UL))\r
+#define bFM3_INTREQ_IRQ23MON_PPGINT2           *((volatile unsigned int*)(0x42620E08UL))\r
+#define bFM3_INTREQ_IRQ23MON_PPGINT3           *((volatile unsigned int*)(0x42620E0CUL))\r
+#define bFM3_INTREQ_IRQ23MON_PPGINT4           *((volatile unsigned int*)(0x42620E10UL))\r
+#define bFM3_INTREQ_IRQ23MON_PPGINT5           *((volatile unsigned int*)(0x42620E14UL))\r
+#define bFM3_INTREQ_IRQ24MON_MOSCINT           *((volatile unsigned int*)(0x42620E80UL))\r
+#define bFM3_INTREQ_IRQ24MON_SOSCINT           *((volatile unsigned int*)(0x42620E84UL))\r
+#define bFM3_INTREQ_IRQ24MON_MPLLINT           *((volatile unsigned int*)(0x42620E88UL))\r
+#define bFM3_INTREQ_IRQ24MON_UPLLINT           *((volatile unsigned int*)(0x42620E8CUL))\r
+#define bFM3_INTREQ_IRQ24MON_WCINT             *((volatile unsigned int*)(0x42620E90UL))\r
+#define bFM3_INTREQ_IRQ25MON_ADCINT0           *((volatile unsigned int*)(0x42620F00UL))\r
+#define bFM3_INTREQ_IRQ25MON_ADCINT1           *((volatile unsigned int*)(0x42620F04UL))\r
+#define bFM3_INTREQ_IRQ25MON_ADCINT2           *((volatile unsigned int*)(0x42620F08UL))\r
+#define bFM3_INTREQ_IRQ25MON_ADCINT3           *((volatile unsigned int*)(0x42620F0CUL))\r
+#define bFM3_INTREQ_IRQ26MON_ADCINT0           *((volatile unsigned int*)(0x42620F80UL))\r
+#define bFM3_INTREQ_IRQ26MON_ADCINT1           *((volatile unsigned int*)(0x42620F84UL))\r
+#define bFM3_INTREQ_IRQ26MON_ADCINT2           *((volatile unsigned int*)(0x42620F88UL))\r
+#define bFM3_INTREQ_IRQ26MON_ADCINT3           *((volatile unsigned int*)(0x42620F8CUL))\r
+#define bFM3_INTREQ_IRQ27MON_ADCINT0           *((volatile unsigned int*)(0x42621000UL))\r
+#define bFM3_INTREQ_IRQ27MON_ADCINT1           *((volatile unsigned int*)(0x42621004UL))\r
+#define bFM3_INTREQ_IRQ27MON_ADCINT2           *((volatile unsigned int*)(0x42621008UL))\r
+#define bFM3_INTREQ_IRQ27MON_ADCINT3           *((volatile unsigned int*)(0x4262100CUL))\r
+#define bFM3_INTREQ_IRQ28MON_FRT0INT0          *((volatile unsigned int*)(0x42621080UL))\r
+#define bFM3_INTREQ_IRQ28MON_FRT0INT1          *((volatile unsigned int*)(0x42621084UL))\r
+#define bFM3_INTREQ_IRQ28MON_FRT0INT2          *((volatile unsigned int*)(0x42621088UL))\r
+#define bFM3_INTREQ_IRQ28MON_FRT0INT3          *((volatile unsigned int*)(0x4262108CUL))\r
+#define bFM3_INTREQ_IRQ28MON_FRT0INT4          *((volatile unsigned int*)(0x42621090UL))\r
+#define bFM3_INTREQ_IRQ28MON_FRT0INT5          *((volatile unsigned int*)(0x42621094UL))\r
+#define bFM3_INTREQ_IRQ28MON_FRT1INT0          *((volatile unsigned int*)(0x42621098UL))\r
+#define bFM3_INTREQ_IRQ28MON_FRT1INT1          *((volatile unsigned int*)(0x4262109CUL))\r
+#define bFM3_INTREQ_IRQ28MON_FRT1INT2          *((volatile unsigned int*)(0x426210A0UL))\r
+#define bFM3_INTREQ_IRQ28MON_FRT1INT3          *((volatile unsigned int*)(0x426210A4UL))\r
+#define bFM3_INTREQ_IRQ28MON_FRT1INT4          *((volatile unsigned int*)(0x426210A8UL))\r
+#define bFM3_INTREQ_IRQ28MON_FRT1INT5          *((volatile unsigned int*)(0x426210ACUL))\r
+#define bFM3_INTREQ_IRQ29MON_ICU0INT0          *((volatile unsigned int*)(0x42621100UL))\r
+#define bFM3_INTREQ_IRQ29MON_ICU0INT1          *((volatile unsigned int*)(0x42621104UL))\r
+#define bFM3_INTREQ_IRQ29MON_ICU0INT2          *((volatile unsigned int*)(0x42621108UL))\r
+#define bFM3_INTREQ_IRQ29MON_ICU0INT3          *((volatile unsigned int*)(0x4262110CUL))\r
+#define bFM3_INTREQ_IRQ29MON_ICU1INT0          *((volatile unsigned int*)(0x42621110UL))\r
+#define bFM3_INTREQ_IRQ29MON_ICU1INT1          *((volatile unsigned int*)(0x42621114UL))\r
+#define bFM3_INTREQ_IRQ29MON_ICU1INT2          *((volatile unsigned int*)(0x42621118UL))\r
+#define bFM3_INTREQ_IRQ29MON_ICU1INT3          *((volatile unsigned int*)(0x4262111CUL))\r
+#define bFM3_INTREQ_IRQ30MON_OCU0INT0          *((volatile unsigned int*)(0x42621180UL))\r
+#define bFM3_INTREQ_IRQ30MON_OCU0INT1          *((volatile unsigned int*)(0x42621184UL))\r
+#define bFM3_INTREQ_IRQ30MON_OCU0INT2          *((volatile unsigned int*)(0x42621188UL))\r
+#define bFM3_INTREQ_IRQ30MON_OCU0INT3          *((volatile unsigned int*)(0x4262118CUL))\r
+#define bFM3_INTREQ_IRQ30MON_OCU0INT4          *((volatile unsigned int*)(0x42621190UL))\r
+#define bFM3_INTREQ_IRQ30MON_OCU0INT5          *((volatile unsigned int*)(0x42621194UL))\r
+#define bFM3_INTREQ_IRQ30MON_OCU1INT0          *((volatile unsigned int*)(0x42621198UL))\r
+#define bFM3_INTREQ_IRQ30MON_OCU1INT1          *((volatile unsigned int*)(0x4262119CUL))\r
+#define bFM3_INTREQ_IRQ30MON_OCU1INT2          *((volatile unsigned int*)(0x426211A0UL))\r
+#define bFM3_INTREQ_IRQ30MON_OCU1INT3          *((volatile unsigned int*)(0x426211A4UL))\r
+#define bFM3_INTREQ_IRQ30MON_OCU1INT4          *((volatile unsigned int*)(0x426211A8UL))\r
+#define bFM3_INTREQ_IRQ30MON_OCU1INT5          *((volatile unsigned int*)(0x426211ACUL))\r
+#define bFM3_INTREQ_IRQ31MON_BTINT0            *((volatile unsigned int*)(0x42621200UL))\r
+#define bFM3_INTREQ_IRQ31MON_BTINT1            *((volatile unsigned int*)(0x42621204UL))\r
+#define bFM3_INTREQ_IRQ31MON_BTINT2            *((volatile unsigned int*)(0x42621208UL))\r
+#define bFM3_INTREQ_IRQ31MON_BTINT3            *((volatile unsigned int*)(0x4262120CUL))\r
+#define bFM3_INTREQ_IRQ31MON_BTINT4            *((volatile unsigned int*)(0x42621210UL))\r
+#define bFM3_INTREQ_IRQ31MON_BTINT5            *((volatile unsigned int*)(0x42621214UL))\r
+#define bFM3_INTREQ_IRQ31MON_BTINT6            *((volatile unsigned int*)(0x42621218UL))\r
+#define bFM3_INTREQ_IRQ31MON_BTINT7            *((volatile unsigned int*)(0x4262121CUL))\r
+#define bFM3_INTREQ_IRQ31MON_BTINT8            *((volatile unsigned int*)(0x42621220UL))\r
+#define bFM3_INTREQ_IRQ31MON_BTINT9            *((volatile unsigned int*)(0x42621224UL))\r
+#define bFM3_INTREQ_IRQ31MON_BTINT10           *((volatile unsigned int*)(0x42621228UL))\r
+#define bFM3_INTREQ_IRQ31MON_BTINT11           *((volatile unsigned int*)(0x4262122CUL))\r
+#define bFM3_INTREQ_IRQ31MON_BTINT12           *((volatile unsigned int*)(0x42621230UL))\r
+#define bFM3_INTREQ_IRQ31MON_BTINT13           *((volatile unsigned int*)(0x42621234UL))\r
+#define bFM3_INTREQ_IRQ31MON_BTINT14           *((volatile unsigned int*)(0x42621238UL))\r
+#define bFM3_INTREQ_IRQ31MON_BTINT15           *((volatile unsigned int*)(0x4262123CUL))\r
+#define bFM3_INTREQ_IRQ32MON_CANINT            *((volatile unsigned int*)(0x42621280UL))\r
+#define bFM3_INTREQ_IRQ33MON_CANINT            *((volatile unsigned int*)(0x42621300UL))\r
+#define bFM3_INTREQ_IRQ34MON_USB0INT0          *((volatile unsigned int*)(0x42621380UL))\r
+#define bFM3_INTREQ_IRQ34MON_USB0INT1          *((volatile unsigned int*)(0x42621384UL))\r
+#define bFM3_INTREQ_IRQ34MON_USB0INT2          *((volatile unsigned int*)(0x42621388UL))\r
+#define bFM3_INTREQ_IRQ34MON_USB0INT3          *((volatile unsigned int*)(0x4262138CUL))\r
+#define bFM3_INTREQ_IRQ34MON_USB0INT4          *((volatile unsigned int*)(0x42621390UL))\r
+#define bFM3_INTREQ_IRQ35MON_USB0INT0          *((volatile unsigned int*)(0x42621400UL))\r
+#define bFM3_INTREQ_IRQ35MON_USB0INT1          *((volatile unsigned int*)(0x42621404UL))\r
+#define bFM3_INTREQ_IRQ35MON_USB0INT2          *((volatile unsigned int*)(0x42621408UL))\r
+#define bFM3_INTREQ_IRQ35MON_USB0INT3          *((volatile unsigned int*)(0x4262140CUL))\r
+#define bFM3_INTREQ_IRQ35MON_USB0INT4          *((volatile unsigned int*)(0x42621410UL))\r
+#define bFM3_INTREQ_IRQ38MON_DMAINT            *((volatile unsigned int*)(0x42621580UL))\r
+#define bFM3_INTREQ_IRQ39MON_DMAINT            *((volatile unsigned int*)(0x42621600UL))\r
+#define bFM3_INTREQ_IRQ40MON_DMAINT            *((volatile unsigned int*)(0x42621680UL))\r
+#define bFM3_INTREQ_IRQ41MON_DMAINT            *((volatile unsigned int*)(0x42621700UL))\r
+#define bFM3_INTREQ_IRQ42MON_DMAINT            *((volatile unsigned int*)(0x42621780UL))\r
+#define bFM3_INTREQ_IRQ43MON_DMAINT            *((volatile unsigned int*)(0x42621800UL))\r
+#define bFM3_INTREQ_IRQ44MON_DMAINT            *((volatile unsigned int*)(0x42621880UL))\r
+#define bFM3_INTREQ_IRQ45MON_DMAINT            *((volatile unsigned int*)(0x42621900UL))\r
+\r
+/* General purpose I/O registers */\r
+#define bFM3_GPIO_PFR0_P0                      *((volatile unsigned int*)(0x42660000UL))\r
+#define bFM3_GPIO_PFR0_P1                      *((volatile unsigned int*)(0x42660004UL))\r
+#define bFM3_GPIO_PFR0_P2                      *((volatile unsigned int*)(0x42660008UL))\r
+#define bFM3_GPIO_PFR0_P3                      *((volatile unsigned int*)(0x4266000CUL))\r
+#define bFM3_GPIO_PFR0_P4                      *((volatile unsigned int*)(0x42660010UL))\r
+#define bFM3_GPIO_PFR0_P5                      *((volatile unsigned int*)(0x42660014UL))\r
+#define bFM3_GPIO_PFR0_P6                      *((volatile unsigned int*)(0x42660018UL))\r
+#define bFM3_GPIO_PFR0_P7                      *((volatile unsigned int*)(0x4266001CUL))\r
+#define bFM3_GPIO_PFR0_P8                      *((volatile unsigned int*)(0x42660020UL))\r
+#define bFM3_GPIO_PFR0_P9                      *((volatile unsigned int*)(0x42660024UL))\r
+#define bFM3_GPIO_PFR0_PA                      *((volatile unsigned int*)(0x42660028UL))\r
+#define bFM3_GPIO_PFR0_PB                      *((volatile unsigned int*)(0x4266002CUL))\r
+#define bFM3_GPIO_PFR0_PC                      *((volatile unsigned int*)(0x42660030UL))\r
+#define bFM3_GPIO_PFR0_PD                      *((volatile unsigned int*)(0x42660034UL))\r
+#define bFM3_GPIO_PFR0_PE                      *((volatile unsigned int*)(0x42660038UL))\r
+#define bFM3_GPIO_PFR0_PF                      *((volatile unsigned int*)(0x4266003CUL))\r
+#define bFM3_GPIO_PFR1_P0                      *((volatile unsigned int*)(0x42660080UL))\r
+#define bFM3_GPIO_PFR1_P1                      *((volatile unsigned int*)(0x42660084UL))\r
+#define bFM3_GPIO_PFR1_P2                      *((volatile unsigned int*)(0x42660088UL))\r
+#define bFM3_GPIO_PFR1_P3                      *((volatile unsigned int*)(0x4266008CUL))\r
+#define bFM3_GPIO_PFR1_P4                      *((volatile unsigned int*)(0x42660090UL))\r
+#define bFM3_GPIO_PFR1_P5                      *((volatile unsigned int*)(0x42660094UL))\r
+#define bFM3_GPIO_PFR1_P6                      *((volatile unsigned int*)(0x42660098UL))\r
+#define bFM3_GPIO_PFR1_P7                      *((volatile unsigned int*)(0x4266009CUL))\r
+#define bFM3_GPIO_PFR1_P8                      *((volatile unsigned int*)(0x426600A0UL))\r
+#define bFM3_GPIO_PFR1_P9                      *((volatile unsigned int*)(0x426600A4UL))\r
+#define bFM3_GPIO_PFR1_PA                      *((volatile unsigned int*)(0x426600A8UL))\r
+#define bFM3_GPIO_PFR1_PB                      *((volatile unsigned int*)(0x426600ACUL))\r
+#define bFM3_GPIO_PFR1_PC                      *((volatile unsigned int*)(0x426600B0UL))\r
+#define bFM3_GPIO_PFR1_PD                      *((volatile unsigned int*)(0x426600B4UL))\r
+#define bFM3_GPIO_PFR1_PE                      *((volatile unsigned int*)(0x426600B8UL))\r
+#define bFM3_GPIO_PFR1_PF                      *((volatile unsigned int*)(0x426600BCUL))\r
+#define bFM3_GPIO_PFR2_P0                      *((volatile unsigned int*)(0x42660100UL))\r
+#define bFM3_GPIO_PFR2_P1                      *((volatile unsigned int*)(0x42660104UL))\r
+#define bFM3_GPIO_PFR2_P2                      *((volatile unsigned int*)(0x42660108UL))\r
+#define bFM3_GPIO_PFR2_P3                      *((volatile unsigned int*)(0x4266010CUL))\r
+#define bFM3_GPIO_PFR3_P0                      *((volatile unsigned int*)(0x42660180UL))\r
+#define bFM3_GPIO_PFR3_P1                      *((volatile unsigned int*)(0x42660184UL))\r
+#define bFM3_GPIO_PFR3_P2                      *((volatile unsigned int*)(0x42660188UL))\r
+#define bFM3_GPIO_PFR3_P3                      *((volatile unsigned int*)(0x4266018CUL))\r
+#define bFM3_GPIO_PFR3_P4                      *((volatile unsigned int*)(0x42660190UL))\r
+#define bFM3_GPIO_PFR3_P5                      *((volatile unsigned int*)(0x42660194UL))\r
+#define bFM3_GPIO_PFR3_P6                      *((volatile unsigned int*)(0x42660198UL))\r
+#define bFM3_GPIO_PFR3_P7                      *((volatile unsigned int*)(0x4266019CUL))\r
+#define bFM3_GPIO_PFR3_P8                      *((volatile unsigned int*)(0x426601A0UL))\r
+#define bFM3_GPIO_PFR3_P9                      *((volatile unsigned int*)(0x426601A4UL))\r
+#define bFM3_GPIO_PFR3_PA                      *((volatile unsigned int*)(0x426601A8UL))\r
+#define bFM3_GPIO_PFR3_PB                      *((volatile unsigned int*)(0x426601ACUL))\r
+#define bFM3_GPIO_PFR3_PC                      *((volatile unsigned int*)(0x426601B0UL))\r
+#define bFM3_GPIO_PFR3_PD                      *((volatile unsigned int*)(0x426601B4UL))\r
+#define bFM3_GPIO_PFR3_PE                      *((volatile unsigned int*)(0x426601B8UL))\r
+#define bFM3_GPIO_PFR3_PF                      *((volatile unsigned int*)(0x426601BCUL))\r
+#define bFM3_GPIO_PFR4_P0                      *((volatile unsigned int*)(0x42660200UL))\r
+#define bFM3_GPIO_PFR4_P1                      *((volatile unsigned int*)(0x42660204UL))\r
+#define bFM3_GPIO_PFR4_P2                      *((volatile unsigned int*)(0x42660208UL))\r
+#define bFM3_GPIO_PFR4_P3                      *((volatile unsigned int*)(0x4266020CUL))\r
+#define bFM3_GPIO_PFR4_P4                      *((volatile unsigned int*)(0x42660210UL))\r
+#define bFM3_GPIO_PFR4_P5                      *((volatile unsigned int*)(0x42660214UL))\r
+#define bFM3_GPIO_PFR4_P6                      *((volatile unsigned int*)(0x42660218UL))\r
+#define bFM3_GPIO_PFR4_P7                      *((volatile unsigned int*)(0x4266021CUL))\r
+#define bFM3_GPIO_PFR4_P8                      *((volatile unsigned int*)(0x42660220UL))\r
+#define bFM3_GPIO_PFR4_P9                      *((volatile unsigned int*)(0x42660224UL))\r
+#define bFM3_GPIO_PFR4_PA                      *((volatile unsigned int*)(0x42660228UL))\r
+#define bFM3_GPIO_PFR4_PB                      *((volatile unsigned int*)(0x4266022CUL))\r
+#define bFM3_GPIO_PFR4_PC                      *((volatile unsigned int*)(0x42660230UL))\r
+#define bFM3_GPIO_PFR4_PD                      *((volatile unsigned int*)(0x42660234UL))\r
+#define bFM3_GPIO_PFR4_PE                      *((volatile unsigned int*)(0x42660238UL))\r
+#define bFM3_GPIO_PFR5_P0                      *((volatile unsigned int*)(0x42660280UL))\r
+#define bFM3_GPIO_PFR5_P1                      *((volatile unsigned int*)(0x42660284UL))\r
+#define bFM3_GPIO_PFR5_P2                      *((volatile unsigned int*)(0x42660288UL))\r
+#define bFM3_GPIO_PFR5_P3                      *((volatile unsigned int*)(0x4266028CUL))\r
+#define bFM3_GPIO_PFR5_P4                      *((volatile unsigned int*)(0x42660290UL))\r
+#define bFM3_GPIO_PFR5_P5                      *((volatile unsigned int*)(0x42660294UL))\r
+#define bFM3_GPIO_PFR5_P6                      *((volatile unsigned int*)(0x42660298UL))\r
+#define bFM3_GPIO_PFR6_P0                      *((volatile unsigned int*)(0x42660300UL))\r
+#define bFM3_GPIO_PFR6_P1                      *((volatile unsigned int*)(0x42660304UL))\r
+#define bFM3_GPIO_PFR6_P2                      *((volatile unsigned int*)(0x42660308UL))\r
+#define bFM3_GPIO_PFR6_P3                      *((volatile unsigned int*)(0x4266030CUL))\r
+#define bFM3_GPIO_PFR8_P0                      *((volatile unsigned int*)(0x42660400UL))\r
+#define bFM3_GPIO_PFR8_P1                      *((volatile unsigned int*)(0x42660404UL))\r
+#define bFM3_GPIO_PCR0_P0                      *((volatile unsigned int*)(0x42662000UL))\r
+#define bFM3_GPIO_PCR0_P1                      *((volatile unsigned int*)(0x42662004UL))\r
+#define bFM3_GPIO_PCR0_P2                      *((volatile unsigned int*)(0x42662008UL))\r
+#define bFM3_GPIO_PCR0_P3                      *((volatile unsigned int*)(0x4266200CUL))\r
+#define bFM3_GPIO_PCR0_P4                      *((volatile unsigned int*)(0x42662010UL))\r
+#define bFM3_GPIO_PCR0_P5                      *((volatile unsigned int*)(0x42662014UL))\r
+#define bFM3_GPIO_PCR0_P6                      *((volatile unsigned int*)(0x42662018UL))\r
+#define bFM3_GPIO_PCR0_P7                      *((volatile unsigned int*)(0x4266201CUL))\r
+#define bFM3_GPIO_PCR0_P8                      *((volatile unsigned int*)(0x42662020UL))\r
+#define bFM3_GPIO_PCR0_P9                      *((volatile unsigned int*)(0x42662024UL))\r
+#define bFM3_GPIO_PCR0_PA                      *((volatile unsigned int*)(0x42662028UL))\r
+#define bFM3_GPIO_PCR0_PB                      *((volatile unsigned int*)(0x4266202CUL))\r
+#define bFM3_GPIO_PCR0_PC                      *((volatile unsigned int*)(0x42662030UL))\r
+#define bFM3_GPIO_PCR0_PD                      *((volatile unsigned int*)(0x42662034UL))\r
+#define bFM3_GPIO_PCR0_PE                      *((volatile unsigned int*)(0x42662038UL))\r
+#define bFM3_GPIO_PCR0_PF                      *((volatile unsigned int*)(0x4266203CUL))\r
+#define bFM3_GPIO_PCR1_P0                      *((volatile unsigned int*)(0x42662080UL))\r
+#define bFM3_GPIO_PCR1_P1                      *((volatile unsigned int*)(0x42662084UL))\r
+#define bFM3_GPIO_PCR1_P2                      *((volatile unsigned int*)(0x42662088UL))\r
+#define bFM3_GPIO_PCR1_P3                      *((volatile unsigned int*)(0x4266208CUL))\r
+#define bFM3_GPIO_PCR1_P4                      *((volatile unsigned int*)(0x42662090UL))\r
+#define bFM3_GPIO_PCR1_P5                      *((volatile unsigned int*)(0x42662094UL))\r
+#define bFM3_GPIO_PCR1_P6                      *((volatile unsigned int*)(0x42662098UL))\r
+#define bFM3_GPIO_PCR1_P7                      *((volatile unsigned int*)(0x4266209CUL))\r
+#define bFM3_GPIO_PCR1_P8                      *((volatile unsigned int*)(0x426620A0UL))\r
+#define bFM3_GPIO_PCR1_P9                      *((volatile unsigned int*)(0x426620A4UL))\r
+#define bFM3_GPIO_PCR1_PA                      *((volatile unsigned int*)(0x426620A8UL))\r
+#define bFM3_GPIO_PCR1_PB                      *((volatile unsigned int*)(0x426620ACUL))\r
+#define bFM3_GPIO_PCR1_PC                      *((volatile unsigned int*)(0x426620B0UL))\r
+#define bFM3_GPIO_PCR1_PD                      *((volatile unsigned int*)(0x426620B4UL))\r
+#define bFM3_GPIO_PCR1_PE                      *((volatile unsigned int*)(0x426620B8UL))\r
+#define bFM3_GPIO_PCR1_PF                      *((volatile unsigned int*)(0x426620BCUL))\r
+#define bFM3_GPIO_PCR2_P0                      *((volatile unsigned int*)(0x42662100UL))\r
+#define bFM3_GPIO_PCR2_P1                      *((volatile unsigned int*)(0x42662104UL))\r
+#define bFM3_GPIO_PCR2_P2                      *((volatile unsigned int*)(0x42662108UL))\r
+#define bFM3_GPIO_PCR2_P3                      *((volatile unsigned int*)(0x4266210CUL))\r
+#define bFM3_GPIO_PCR3_P0                      *((volatile unsigned int*)(0x42662180UL))\r
+#define bFM3_GPIO_PCR3_P1                      *((volatile unsigned int*)(0x42662184UL))\r
+#define bFM3_GPIO_PCR3_P2                      *((volatile unsigned int*)(0x42662188UL))\r
+#define bFM3_GPIO_PCR3_P3                      *((volatile unsigned int*)(0x4266218CUL))\r
+#define bFM3_GPIO_PCR3_P4                      *((volatile unsigned int*)(0x42662190UL))\r
+#define bFM3_GPIO_PCR3_P5                      *((volatile unsigned int*)(0x42662194UL))\r
+#define bFM3_GPIO_PCR3_P6                      *((volatile unsigned int*)(0x42662198UL))\r
+#define bFM3_GPIO_PCR3_P7                      *((volatile unsigned int*)(0x4266219CUL))\r
+#define bFM3_GPIO_PCR3_P8                      *((volatile unsigned int*)(0x426621A0UL))\r
+#define bFM3_GPIO_PCR3_P9                      *((volatile unsigned int*)(0x426621A4UL))\r
+#define bFM3_GPIO_PCR3_PA                      *((volatile unsigned int*)(0x426621A8UL))\r
+#define bFM3_GPIO_PCR3_PB                      *((volatile unsigned int*)(0x426621ACUL))\r
+#define bFM3_GPIO_PCR3_PC                      *((volatile unsigned int*)(0x426621B0UL))\r
+#define bFM3_GPIO_PCR3_PD                      *((volatile unsigned int*)(0x426621B4UL))\r
+#define bFM3_GPIO_PCR3_PE                      *((volatile unsigned int*)(0x426621B8UL))\r
+#define bFM3_GPIO_PCR3_PF                      *((volatile unsigned int*)(0x426621BCUL))\r
+#define bFM3_GPIO_PCR4_P0                      *((volatile unsigned int*)(0x42662200UL))\r
+#define bFM3_GPIO_PCR4_P1                      *((volatile unsigned int*)(0x42662204UL))\r
+#define bFM3_GPIO_PCR4_P2                      *((volatile unsigned int*)(0x42662208UL))\r
+#define bFM3_GPIO_PCR4_P3                      *((volatile unsigned int*)(0x4266220CUL))\r
+#define bFM3_GPIO_PCR4_P4                      *((volatile unsigned int*)(0x42662210UL))\r
+#define bFM3_GPIO_PCR4_P5                      *((volatile unsigned int*)(0x42662214UL))\r
+#define bFM3_GPIO_PCR4_P6                      *((volatile unsigned int*)(0x42662218UL))\r
+#define bFM3_GPIO_PCR4_P7                      *((volatile unsigned int*)(0x4266221CUL))\r
+#define bFM3_GPIO_PCR4_P8                      *((volatile unsigned int*)(0x42662220UL))\r
+#define bFM3_GPIO_PCR4_P9                      *((volatile unsigned int*)(0x42662224UL))\r
+#define bFM3_GPIO_PCR4_PA                      *((volatile unsigned int*)(0x42662228UL))\r
+#define bFM3_GPIO_PCR4_PB                      *((volatile unsigned int*)(0x4266222CUL))\r
+#define bFM3_GPIO_PCR4_PC                      *((volatile unsigned int*)(0x42662230UL))\r
+#define bFM3_GPIO_PCR4_PD                      *((volatile unsigned int*)(0x42662234UL))\r
+#define bFM3_GPIO_PCR4_PE                      *((volatile unsigned int*)(0x42662238UL))\r
+#define bFM3_GPIO_PCR5_P0                      *((volatile unsigned int*)(0x42662280UL))\r
+#define bFM3_GPIO_PCR5_P1                      *((volatile unsigned int*)(0x42662284UL))\r
+#define bFM3_GPIO_PCR5_P2                      *((volatile unsigned int*)(0x42662288UL))\r
+#define bFM3_GPIO_PCR5_P3                      *((volatile unsigned int*)(0x4266228CUL))\r
+#define bFM3_GPIO_PCR5_P4                      *((volatile unsigned int*)(0x42662290UL))\r
+#define bFM3_GPIO_PCR5_P5                      *((volatile unsigned int*)(0x42662294UL))\r
+#define bFM3_GPIO_PCR5_P6                      *((volatile unsigned int*)(0x42662298UL))\r
+#define bFM3_GPIO_PCR6_P0                      *((volatile unsigned int*)(0x42662300UL))\r
+#define bFM3_GPIO_PCR6_P1                      *((volatile unsigned int*)(0x42662304UL))\r
+#define bFM3_GPIO_PCR6_P2                      *((volatile unsigned int*)(0x42662308UL))\r
+#define bFM3_GPIO_PCR6_P3                      *((volatile unsigned int*)(0x4266230CUL))\r
+#define bFM3_GPIO_DDR0_P0                      *((volatile unsigned int*)(0x42664000UL))\r
+#define bFM3_GPIO_DDR0_P1                      *((volatile unsigned int*)(0x42664004UL))\r
+#define bFM3_GPIO_DDR0_P2                      *((volatile unsigned int*)(0x42664008UL))\r
+#define bFM3_GPIO_DDR0_P3                      *((volatile unsigned int*)(0x4266400CUL))\r
+#define bFM3_GPIO_DDR0_P4                      *((volatile unsigned int*)(0x42664010UL))\r
+#define bFM3_GPIO_DDR0_P5                      *((volatile unsigned int*)(0x42664014UL))\r
+#define bFM3_GPIO_DDR0_P6                      *((volatile unsigned int*)(0x42664018UL))\r
+#define bFM3_GPIO_DDR0_P7                      *((volatile unsigned int*)(0x4266401CUL))\r
+#define bFM3_GPIO_DDR0_P8                      *((volatile unsigned int*)(0x42664020UL))\r
+#define bFM3_GPIO_DDR0_P9                      *((volatile unsigned int*)(0x42664024UL))\r
+#define bFM3_GPIO_DDR0_PA                      *((volatile unsigned int*)(0x42664028UL))\r
+#define bFM3_GPIO_DDR0_PB                      *((volatile unsigned int*)(0x4266402CUL))\r
+#define bFM3_GPIO_DDR0_PC                      *((volatile unsigned int*)(0x42664030UL))\r
+#define bFM3_GPIO_DDR0_PD                      *((volatile unsigned int*)(0x42664034UL))\r
+#define bFM3_GPIO_DDR0_PE                      *((volatile unsigned int*)(0x42664038UL))\r
+#define bFM3_GPIO_DDR0_PF                      *((volatile unsigned int*)(0x4266403CUL))\r
+#define bFM3_GPIO_DDR1_P0                      *((volatile unsigned int*)(0x42664080UL))\r
+#define bFM3_GPIO_DDR1_P1                      *((volatile unsigned int*)(0x42664084UL))\r
+#define bFM3_GPIO_DDR1_P2                      *((volatile unsigned int*)(0x42664088UL))\r
+#define bFM3_GPIO_DDR1_P3                      *((volatile unsigned int*)(0x4266408CUL))\r
+#define bFM3_GPIO_DDR1_P4                      *((volatile unsigned int*)(0x42664090UL))\r
+#define bFM3_GPIO_DDR1_P5                      *((volatile unsigned int*)(0x42664094UL))\r
+#define bFM3_GPIO_DDR1_P6                      *((volatile unsigned int*)(0x42664098UL))\r
+#define bFM3_GPIO_DDR1_P7                      *((volatile unsigned int*)(0x4266409CUL))\r
+#define bFM3_GPIO_DDR1_P8                      *((volatile unsigned int*)(0x426640A0UL))\r
+#define bFM3_GPIO_DDR1_P9                      *((volatile unsigned int*)(0x426640A4UL))\r
+#define bFM3_GPIO_DDR1_PA                      *((volatile unsigned int*)(0x426640A8UL))\r
+#define bFM3_GPIO_DDR1_PB                      *((volatile unsigned int*)(0x426640ACUL))\r
+#define bFM3_GPIO_DDR1_PC                      *((volatile unsigned int*)(0x426640B0UL))\r
+#define bFM3_GPIO_DDR1_PD                      *((volatile unsigned int*)(0x426640B4UL))\r
+#define bFM3_GPIO_DDR1_PE                      *((volatile unsigned int*)(0x426640B8UL))\r
+#define bFM3_GPIO_DDR1_PF                      *((volatile unsigned int*)(0x426640BCUL))\r
+#define bFM3_GPIO_DDR2_P0                      *((volatile unsigned int*)(0x42664100UL))\r
+#define bFM3_GPIO_DDR2_P1                      *((volatile unsigned int*)(0x42664104UL))\r
+#define bFM3_GPIO_DDR2_P2                      *((volatile unsigned int*)(0x42664108UL))\r
+#define bFM3_GPIO_DDR2_P3                      *((volatile unsigned int*)(0x4266410CUL))\r
+#define bFM3_GPIO_DDR3_P0                      *((volatile unsigned int*)(0x42664180UL))\r
+#define bFM3_GPIO_DDR3_P1                      *((volatile unsigned int*)(0x42664184UL))\r
+#define bFM3_GPIO_DDR3_P2                      *((volatile unsigned int*)(0x42664188UL))\r
+#define bFM3_GPIO_DDR3_P3                      *((volatile unsigned int*)(0x4266418CUL))\r
+#define bFM3_GPIO_DDR3_P4                      *((volatile unsigned int*)(0x42664190UL))\r
+#define bFM3_GPIO_DDR3_P5                      *((volatile unsigned int*)(0x42664194UL))\r
+#define bFM3_GPIO_DDR3_P6                      *((volatile unsigned int*)(0x42664198UL))\r
+#define bFM3_GPIO_DDR3_P7                      *((volatile unsigned int*)(0x4266419CUL))\r
+#define bFM3_GPIO_DDR3_P8                      *((volatile unsigned int*)(0x426641A0UL))\r
+#define bFM3_GPIO_DDR3_P9                      *((volatile unsigned int*)(0x426641A4UL))\r
+#define bFM3_GPIO_DDR3_PA                      *((volatile unsigned int*)(0x426641A8UL))\r
+#define bFM3_GPIO_DDR3_PB                      *((volatile unsigned int*)(0x426641ACUL))\r
+#define bFM3_GPIO_DDR3_PC                      *((volatile unsigned int*)(0x426641B0UL))\r
+#define bFM3_GPIO_DDR3_PD                      *((volatile unsigned int*)(0x426641B4UL))\r
+#define bFM3_GPIO_DDR3_PE                      *((volatile unsigned int*)(0x426641B8UL))\r
+#define bFM3_GPIO_DDR3_PF                      *((volatile unsigned int*)(0x426641BCUL))\r
+#define bFM3_GPIO_DDR4_P0                      *((volatile unsigned int*)(0x42664200UL))\r
+#define bFM3_GPIO_DDR4_P1                      *((volatile unsigned int*)(0x42664204UL))\r
+#define bFM3_GPIO_DDR4_P2                      *((volatile unsigned int*)(0x42664208UL))\r
+#define bFM3_GPIO_DDR4_P3                      *((volatile unsigned int*)(0x4266420CUL))\r
+#define bFM3_GPIO_DDR4_P4                      *((volatile unsigned int*)(0x42664210UL))\r
+#define bFM3_GPIO_DDR4_P5                      *((volatile unsigned int*)(0x42664214UL))\r
+#define bFM3_GPIO_DDR4_P6                      *((volatile unsigned int*)(0x42664218UL))\r
+#define bFM3_GPIO_DDR4_P7                      *((volatile unsigned int*)(0x4266421CUL))\r
+#define bFM3_GPIO_DDR4_P8                      *((volatile unsigned int*)(0x42664220UL))\r
+#define bFM3_GPIO_DDR4_P9                      *((volatile unsigned int*)(0x42664224UL))\r
+#define bFM3_GPIO_DDR4_PA                      *((volatile unsigned int*)(0x42664228UL))\r
+#define bFM3_GPIO_DDR4_PB                      *((volatile unsigned int*)(0x4266422CUL))\r
+#define bFM3_GPIO_DDR4_PC                      *((volatile unsigned int*)(0x42664230UL))\r
+#define bFM3_GPIO_DDR4_PD                      *((volatile unsigned int*)(0x42664234UL))\r
+#define bFM3_GPIO_DDR4_PE                      *((volatile unsigned int*)(0x42664238UL))\r
+#define bFM3_GPIO_DDR5_P0                      *((volatile unsigned int*)(0x42664280UL))\r
+#define bFM3_GPIO_DDR5_P1                      *((volatile unsigned int*)(0x42664284UL))\r
+#define bFM3_GPIO_DDR5_P2                      *((volatile unsigned int*)(0x42664288UL))\r
+#define bFM3_GPIO_DDR5_P3                      *((volatile unsigned int*)(0x4266428CUL))\r
+#define bFM3_GPIO_DDR5_P4                      *((volatile unsigned int*)(0x42664290UL))\r
+#define bFM3_GPIO_DDR5_P5                      *((volatile unsigned int*)(0x42664294UL))\r
+#define bFM3_GPIO_DDR5_P6                      *((volatile unsigned int*)(0x42664298UL))\r
+#define bFM3_GPIO_DDR6_P0                      *((volatile unsigned int*)(0x42664300UL))\r
+#define bFM3_GPIO_DDR6_P1                      *((volatile unsigned int*)(0x42664304UL))\r
+#define bFM3_GPIO_DDR6_P2                      *((volatile unsigned int*)(0x42664308UL))\r
+#define bFM3_GPIO_DDR6_P3                      *((volatile unsigned int*)(0x4266430CUL))\r
+#define bFM3_GPIO_DDR8_P0                      *((volatile unsigned int*)(0x42664400UL))\r
+#define bFM3_GPIO_DDR8_P1                      *((volatile unsigned int*)(0x42664404UL))\r
+#define bFM3_GPIO_PDIR0_P0                     *((volatile unsigned int*)(0x42666000UL))\r
+#define bFM3_GPIO_PDIR0_P1                     *((volatile unsigned int*)(0x42666004UL))\r
+#define bFM3_GPIO_PDIR0_P2                     *((volatile unsigned int*)(0x42666008UL))\r
+#define bFM3_GPIO_PDIR0_P3                     *((volatile unsigned int*)(0x4266600CUL))\r
+#define bFM3_GPIO_PDIR0_P4                     *((volatile unsigned int*)(0x42666010UL))\r
+#define bFM3_GPIO_PDIR0_P5                     *((volatile unsigned int*)(0x42666014UL))\r
+#define bFM3_GPIO_PDIR0_P6                     *((volatile unsigned int*)(0x42666018UL))\r
+#define bFM3_GPIO_PDIR0_P7                     *((volatile unsigned int*)(0x4266601CUL))\r
+#define bFM3_GPIO_PDIR0_P8                     *((volatile unsigned int*)(0x42666020UL))\r
+#define bFM3_GPIO_PDIR0_P9                     *((volatile unsigned int*)(0x42666024UL))\r
+#define bFM3_GPIO_PDIR0_PA                     *((volatile unsigned int*)(0x42666028UL))\r
+#define bFM3_GPIO_PDIR0_PB                     *((volatile unsigned int*)(0x4266602CUL))\r
+#define bFM3_GPIO_PDIR0_PC                     *((volatile unsigned int*)(0x42666030UL))\r
+#define bFM3_GPIO_PDIR0_PD                     *((volatile unsigned int*)(0x42666034UL))\r
+#define bFM3_GPIO_PDIR0_PE                     *((volatile unsigned int*)(0x42666038UL))\r
+#define bFM3_GPIO_PDIR0_PF                     *((volatile unsigned int*)(0x4266603CUL))\r
+#define bFM3_GPIO_PDIR1_P0                     *((volatile unsigned int*)(0x42666080UL))\r
+#define bFM3_GPIO_PDIR1_P1                     *((volatile unsigned int*)(0x42666084UL))\r
+#define bFM3_GPIO_PDIR1_P2                     *((volatile unsigned int*)(0x42666088UL))\r
+#define bFM3_GPIO_PDIR1_P3                     *((volatile unsigned int*)(0x4266608CUL))\r
+#define bFM3_GPIO_PDIR1_P4                     *((volatile unsigned int*)(0x42666090UL))\r
+#define bFM3_GPIO_PDIR1_P5                     *((volatile unsigned int*)(0x42666094UL))\r
+#define bFM3_GPIO_PDIR1_P6                     *((volatile unsigned int*)(0x42666098UL))\r
+#define bFM3_GPIO_PDIR1_P7                     *((volatile unsigned int*)(0x4266609CUL))\r
+#define bFM3_GPIO_PDIR1_P8                     *((volatile unsigned int*)(0x426660A0UL))\r
+#define bFM3_GPIO_PDIR1_P9                     *((volatile unsigned int*)(0x426660A4UL))\r
+#define bFM3_GPIO_PDIR1_PA                     *((volatile unsigned int*)(0x426660A8UL))\r
+#define bFM3_GPIO_PDIR1_PB                     *((volatile unsigned int*)(0x426660ACUL))\r
+#define bFM3_GPIO_PDIR1_PC                     *((volatile unsigned int*)(0x426660B0UL))\r
+#define bFM3_GPIO_PDIR1_PD                     *((volatile unsigned int*)(0x426660B4UL))\r
+#define bFM3_GPIO_PDIR1_PE                     *((volatile unsigned int*)(0x426660B8UL))\r
+#define bFM3_GPIO_PDIR1_PF                     *((volatile unsigned int*)(0x426660BCUL))\r
+#define bFM3_GPIO_PDIR2_P0                     *((volatile unsigned int*)(0x42666100UL))\r
+#define bFM3_GPIO_PDIR2_P1                     *((volatile unsigned int*)(0x42666104UL))\r
+#define bFM3_GPIO_PDIR2_P2                     *((volatile unsigned int*)(0x42666108UL))\r
+#define bFM3_GPIO_PDIR2_P3                     *((volatile unsigned int*)(0x4266610CUL))\r
+#define bFM3_GPIO_PDIR3_P0                     *((volatile unsigned int*)(0x42666180UL))\r
+#define bFM3_GPIO_PDIR3_P1                     *((volatile unsigned int*)(0x42666184UL))\r
+#define bFM3_GPIO_PDIR3_P2                     *((volatile unsigned int*)(0x42666188UL))\r
+#define bFM3_GPIO_PDIR3_P3                     *((volatile unsigned int*)(0x4266618CUL))\r
+#define bFM3_GPIO_PDIR3_P4                     *((volatile unsigned int*)(0x42666190UL))\r
+#define bFM3_GPIO_PDIR3_P5                     *((volatile unsigned int*)(0x42666194UL))\r
+#define bFM3_GPIO_PDIR3_P6                     *((volatile unsigned int*)(0x42666198UL))\r
+#define bFM3_GPIO_PDIR3_P7                     *((volatile unsigned int*)(0x4266619CUL))\r
+#define bFM3_GPIO_PDIR3_P8                     *((volatile unsigned int*)(0x426661A0UL))\r
+#define bFM3_GPIO_PDIR3_P9                     *((volatile unsigned int*)(0x426661A4UL))\r
+#define bFM3_GPIO_PDIR3_PA                     *((volatile unsigned int*)(0x426661A8UL))\r
+#define bFM3_GPIO_PDIR3_PB                     *((volatile unsigned int*)(0x426661ACUL))\r
+#define bFM3_GPIO_PDIR3_PC                     *((volatile unsigned int*)(0x426661B0UL))\r
+#define bFM3_GPIO_PDIR3_PD                     *((volatile unsigned int*)(0x426661B4UL))\r
+#define bFM3_GPIO_PDIR3_PE                     *((volatile unsigned int*)(0x426661B8UL))\r
+#define bFM3_GPIO_PDIR3_PF                     *((volatile unsigned int*)(0x426661BCUL))\r
+#define bFM3_GPIO_PDIR4_P0                     *((volatile unsigned int*)(0x42666200UL))\r
+#define bFM3_GPIO_PDIR4_P1                     *((volatile unsigned int*)(0x42666204UL))\r
+#define bFM3_GPIO_PDIR4_P2                     *((volatile unsigned int*)(0x42666208UL))\r
+#define bFM3_GPIO_PDIR4_P3                     *((volatile unsigned int*)(0x4266620CUL))\r
+#define bFM3_GPIO_PDIR4_P4                     *((volatile unsigned int*)(0x42666210UL))\r
+#define bFM3_GPIO_PDIR4_P5                     *((volatile unsigned int*)(0x42666214UL))\r
+#define bFM3_GPIO_PDIR4_P6                     *((volatile unsigned int*)(0x42666218UL))\r
+#define bFM3_GPIO_PDIR4_P7                     *((volatile unsigned int*)(0x4266621CUL))\r
+#define bFM3_GPIO_PDIR4_P8                     *((volatile unsigned int*)(0x42666220UL))\r
+#define bFM3_GPIO_PDIR4_P9                     *((volatile unsigned int*)(0x42666224UL))\r
+#define bFM3_GPIO_PDIR4_PA                     *((volatile unsigned int*)(0x42666228UL))\r
+#define bFM3_GPIO_PDIR4_PB                     *((volatile unsigned int*)(0x4266622CUL))\r
+#define bFM3_GPIO_PDIR4_PC                     *((volatile unsigned int*)(0x42666230UL))\r
+#define bFM3_GPIO_PDIR4_PD                     *((volatile unsigned int*)(0x42666234UL))\r
+#define bFM3_GPIO_PDIR4_PE                     *((volatile unsigned int*)(0x42666238UL))\r
+#define bFM3_GPIO_PDIR5_P0                     *((volatile unsigned int*)(0x42666280UL))\r
+#define bFM3_GPIO_PDIR5_P1                     *((volatile unsigned int*)(0x42666284UL))\r
+#define bFM3_GPIO_PDIR5_P2                     *((volatile unsigned int*)(0x42666288UL))\r
+#define bFM3_GPIO_PDIR5_P3                     *((volatile unsigned int*)(0x4266628CUL))\r
+#define bFM3_GPIO_PDIR5_P4                     *((volatile unsigned int*)(0x42666290UL))\r
+#define bFM3_GPIO_PDIR5_P5                     *((volatile unsigned int*)(0x42666294UL))\r
+#define bFM3_GPIO_PDIR5_P6                     *((volatile unsigned int*)(0x42666298UL))\r
+#define bFM3_GPIO_PDIR6_P0                     *((volatile unsigned int*)(0x42666300UL))\r
+#define bFM3_GPIO_PDIR6_P1                     *((volatile unsigned int*)(0x42666304UL))\r
+#define bFM3_GPIO_PDIR6_P2                     *((volatile unsigned int*)(0x42666308UL))\r
+#define bFM3_GPIO_PDIR6_P3                     *((volatile unsigned int*)(0x4266630CUL))\r
+#define bFM3_GPIO_PDIR8_P0                     *((volatile unsigned int*)(0x42666400UL))\r
+#define bFM3_GPIO_PDIR8_P1                     *((volatile unsigned int*)(0x42666404UL))\r
+#define bFM3_GPIO_PDOR0_P0                     *((volatile unsigned int*)(0x42668000UL))\r
+#define bFM3_GPIO_PDOR0_P1                     *((volatile unsigned int*)(0x42668004UL))\r
+#define bFM3_GPIO_PDOR0_P2                     *((volatile unsigned int*)(0x42668008UL))\r
+#define bFM3_GPIO_PDOR0_P3                     *((volatile unsigned int*)(0x4266800CUL))\r
+#define bFM3_GPIO_PDOR0_P4                     *((volatile unsigned int*)(0x42668010UL))\r
+#define bFM3_GPIO_PDOR0_P5                     *((volatile unsigned int*)(0x42668014UL))\r
+#define bFM3_GPIO_PDOR0_P6                     *((volatile unsigned int*)(0x42668018UL))\r
+#define bFM3_GPIO_PDOR0_P7                     *((volatile unsigned int*)(0x4266801CUL))\r
+#define bFM3_GPIO_PDOR0_P8                     *((volatile unsigned int*)(0x42668020UL))\r
+#define bFM3_GPIO_PDOR0_P9                     *((volatile unsigned int*)(0x42668024UL))\r
+#define bFM3_GPIO_PDOR0_PA                     *((volatile unsigned int*)(0x42668028UL))\r
+#define bFM3_GPIO_PDOR0_PB                     *((volatile unsigned int*)(0x4266802CUL))\r
+#define bFM3_GPIO_PDOR0_PC                     *((volatile unsigned int*)(0x42668030UL))\r
+#define bFM3_GPIO_PDOR0_PD                     *((volatile unsigned int*)(0x42668034UL))\r
+#define bFM3_GPIO_PDOR0_PE                     *((volatile unsigned int*)(0x42668038UL))\r
+#define bFM3_GPIO_PDOR0_PF                     *((volatile unsigned int*)(0x4266803CUL))\r
+#define bFM3_GPIO_PDOR1_P0                     *((volatile unsigned int*)(0x42668080UL))\r
+#define bFM3_GPIO_PDOR1_P1                     *((volatile unsigned int*)(0x42668084UL))\r
+#define bFM3_GPIO_PDOR1_P2                     *((volatile unsigned int*)(0x42668088UL))\r
+#define bFM3_GPIO_PDOR1_P3                     *((volatile unsigned int*)(0x4266808CUL))\r
+#define bFM3_GPIO_PDOR1_P4                     *((volatile unsigned int*)(0x42668090UL))\r
+#define bFM3_GPIO_PDOR1_P5                     *((volatile unsigned int*)(0x42668094UL))\r
+#define bFM3_GPIO_PDOR1_P6                     *((volatile unsigned int*)(0x42668098UL))\r
+#define bFM3_GPIO_PDOR1_P7                     *((volatile unsigned int*)(0x4266809CUL))\r
+#define bFM3_GPIO_PDOR1_P8                     *((volatile unsigned int*)(0x426680A0UL))\r
+#define bFM3_GPIO_PDOR1_P9                     *((volatile unsigned int*)(0x426680A4UL))\r
+#define bFM3_GPIO_PDOR1_PA                     *((volatile unsigned int*)(0x426680A8UL))\r
+#define bFM3_GPIO_PDOR1_PB                     *((volatile unsigned int*)(0x426680ACUL))\r
+#define bFM3_GPIO_PDOR1_PC                     *((volatile unsigned int*)(0x426680B0UL))\r
+#define bFM3_GPIO_PDOR1_PD                     *((volatile unsigned int*)(0x426680B4UL))\r
+#define bFM3_GPIO_PDOR1_PE                     *((volatile unsigned int*)(0x426680B8UL))\r
+#define bFM3_GPIO_PDOR1_PF                     *((volatile unsigned int*)(0x426680BCUL))\r
+#define bFM3_GPIO_PDOR2_P0                     *((volatile unsigned int*)(0x42668100UL))\r
+#define bFM3_GPIO_PDOR2_P1                     *((volatile unsigned int*)(0x42668104UL))\r
+#define bFM3_GPIO_PDOR2_P2                     *((volatile unsigned int*)(0x42668108UL))\r
+#define bFM3_GPIO_PDOR2_P3                     *((volatile unsigned int*)(0x4266810CUL))\r
+#define bFM3_GPIO_PDOR3_P0                     *((volatile unsigned int*)(0x42668180UL))\r
+#define bFM3_GPIO_PDOR3_P1                     *((volatile unsigned int*)(0x42668184UL))\r
+#define bFM3_GPIO_PDOR3_P2                     *((volatile unsigned int*)(0x42668188UL))\r
+#define bFM3_GPIO_PDOR3_P3                     *((volatile unsigned int*)(0x4266818CUL))\r
+#define bFM3_GPIO_PDOR3_P4                     *((volatile unsigned int*)(0x42668190UL))\r
+#define bFM3_GPIO_PDOR3_P5                     *((volatile unsigned int*)(0x42668194UL))\r
+#define bFM3_GPIO_PDOR3_P6                     *((volatile unsigned int*)(0x42668198UL))\r
+#define bFM3_GPIO_PDOR3_P7                     *((volatile unsigned int*)(0x4266819CUL))\r
+#define bFM3_GPIO_PDOR3_P8                     *((volatile unsigned int*)(0x426681A0UL))\r
+#define bFM3_GPIO_PDOR3_P9                     *((volatile unsigned int*)(0x426681A4UL))\r
+#define bFM3_GPIO_PDOR3_PA                     *((volatile unsigned int*)(0x426681A8UL))\r
+#define bFM3_GPIO_PDOR3_PB                     *((volatile unsigned int*)(0x426681ACUL))\r
+#define bFM3_GPIO_PDOR3_PC                     *((volatile unsigned int*)(0x426681B0UL))\r
+#define bFM3_GPIO_PDOR3_PD                     *((volatile unsigned int*)(0x426681B4UL))\r
+#define bFM3_GPIO_PDOR3_PE                     *((volatile unsigned int*)(0x426681B8UL))\r
+#define bFM3_GPIO_PDOR3_PF                     *((volatile unsigned int*)(0x426681BCUL))\r
+#define bFM3_GPIO_PDOR4_P0                     *((volatile unsigned int*)(0x42668200UL))\r
+#define bFM3_GPIO_PDOR4_P1                     *((volatile unsigned int*)(0x42668204UL))\r
+#define bFM3_GPIO_PDOR4_P2                     *((volatile unsigned int*)(0x42668208UL))\r
+#define bFM3_GPIO_PDOR4_P3                     *((volatile unsigned int*)(0x4266820CUL))\r
+#define bFM3_GPIO_PDOR4_P4                     *((volatile unsigned int*)(0x42668210UL))\r
+#define bFM3_GPIO_PDOR4_P5                     *((volatile unsigned int*)(0x42668214UL))\r
+#define bFM3_GPIO_PDOR4_P6                     *((volatile unsigned int*)(0x42668218UL))\r
+#define bFM3_GPIO_PDOR4_P7                     *((volatile unsigned int*)(0x4266821CUL))\r
+#define bFM3_GPIO_PDOR4_P8                     *((volatile unsigned int*)(0x42668220UL))\r
+#define bFM3_GPIO_PDOR4_P9                     *((volatile unsigned int*)(0x42668224UL))\r
+#define bFM3_GPIO_PDOR4_PA                     *((volatile unsigned int*)(0x42668228UL))\r
+#define bFM3_GPIO_PDOR4_PB                     *((volatile unsigned int*)(0x4266822CUL))\r
+#define bFM3_GPIO_PDOR4_PC                     *((volatile unsigned int*)(0x42668230UL))\r
+#define bFM3_GPIO_PDOR4_PD                     *((volatile unsigned int*)(0x42668234UL))\r
+#define bFM3_GPIO_PDOR4_PE                     *((volatile unsigned int*)(0x42668238UL))\r
+#define bFM3_GPIO_PDOR5_P0                     *((volatile unsigned int*)(0x42668280UL))\r
+#define bFM3_GPIO_PDOR5_P1                     *((volatile unsigned int*)(0x42668284UL))\r
+#define bFM3_GPIO_PDOR5_P2                     *((volatile unsigned int*)(0x42668288UL))\r
+#define bFM3_GPIO_PDOR5_P3                     *((volatile unsigned int*)(0x4266828CUL))\r
+#define bFM3_GPIO_PDOR5_P4                     *((volatile unsigned int*)(0x42668290UL))\r
+#define bFM3_GPIO_PDOR5_P5                     *((volatile unsigned int*)(0x42668294UL))\r
+#define bFM3_GPIO_PDOR5_P6                     *((volatile unsigned int*)(0x42668298UL))\r
+#define bFM3_GPIO_PDOR6_P0                     *((volatile unsigned int*)(0x42668300UL))\r
+#define bFM3_GPIO_PDOR6_P1                     *((volatile unsigned int*)(0x42668304UL))\r
+#define bFM3_GPIO_PDOR6_P2                     *((volatile unsigned int*)(0x42668308UL))\r
+#define bFM3_GPIO_PDOR6_P3                     *((volatile unsigned int*)(0x4266830CUL))\r
+#define bFM3_GPIO_PDOR8_P0                     *((volatile unsigned int*)(0x42668400UL))\r
+#define bFM3_GPIO_PDOR8_P1                     *((volatile unsigned int*)(0x42668404UL))\r
+#define bFM3_GPIO_ADE_AN0                      *((volatile unsigned int*)(0x4266A000UL))\r
+#define bFM3_GPIO_ADE_AN1                      *((volatile unsigned int*)(0x4266A004UL))\r
+#define bFM3_GPIO_ADE_AN2                      *((volatile unsigned int*)(0x4266A008UL))\r
+#define bFM3_GPIO_ADE_AN3                      *((volatile unsigned int*)(0x4266A00CUL))\r
+#define bFM3_GPIO_ADE_AN4                      *((volatile unsigned int*)(0x4266A010UL))\r
+#define bFM3_GPIO_ADE_AN5                      *((volatile unsigned int*)(0x4266A014UL))\r
+#define bFM3_GPIO_ADE_AN6                      *((volatile unsigned int*)(0x4266A018UL))\r
+#define bFM3_GPIO_ADE_AN7                      *((volatile unsigned int*)(0x4266A01CUL))\r
+#define bFM3_GPIO_ADE_AN8                      *((volatile unsigned int*)(0x4266A020UL))\r
+#define bFM3_GPIO_ADE_AN9                      *((volatile unsigned int*)(0x4266A024UL))\r
+#define bFM3_GPIO_ADE_ANA                      *((volatile unsigned int*)(0x4266A028UL))\r
+#define bFM3_GPIO_ADE_ANB                      *((volatile unsigned int*)(0x4266A02CUL))\r
+#define bFM3_GPIO_ADE_ANC                      *((volatile unsigned int*)(0x4266A030UL))\r
+#define bFM3_GPIO_ADE_AND                      *((volatile unsigned int*)(0x4266A034UL))\r
+#define bFM3_GPIO_ADE_ANE                      *((volatile unsigned int*)(0x4266A038UL))\r
+#define bFM3_GPIO_ADE_ANF                      *((volatile unsigned int*)(0x4266A03CUL))\r
+#define bFM3_GPIO_SPSR_SUBXC                   *((volatile unsigned int*)(0x4266B000UL))\r
+#define bFM3_GPIO_SPSR_USB0C                   *((volatile unsigned int*)(0x4266B010UL))\r
+#define bFM3_GPIO_EPFR00_NMIS                  *((volatile unsigned int*)(0x4266C000UL))\r
+#define bFM3_GPIO_EPFR00_CROUTE                *((volatile unsigned int*)(0x4266C004UL))\r
+#define bFM3_GPIO_EPFR00_USB0PE                *((volatile unsigned int*)(0x4266C024UL))\r
+#define bFM3_GPIO_EPFR00_JTAGEN0B              *((volatile unsigned int*)(0x4266C040UL))\r
+#define bFM3_GPIO_EPFR00_JTAGEN1S              *((volatile unsigned int*)(0x4266C044UL))\r
+#define bFM3_GPIO_EPFR00_TRC0E                 *((volatile unsigned int*)(0x4266C060UL))\r
+#define bFM3_GPIO_EPFR00_TRC1E                 *((volatile unsigned int*)(0x4266C064UL))\r
+#define bFM3_GPIO_EPFR01_RTO00E0               *((volatile unsigned int*)(0x4266C080UL))\r
+#define bFM3_GPIO_EPFR01_RTO00E1               *((volatile unsigned int*)(0x4266C084UL))\r
+#define bFM3_GPIO_EPFR01_RTO01E0               *((volatile unsigned int*)(0x4266C088UL))\r
+#define bFM3_GPIO_EPFR01_RTO01E1               *((volatile unsigned int*)(0x4266C08CUL))\r
+#define bFM3_GPIO_EPFR01_RTO02E0               *((volatile unsigned int*)(0x4266C090UL))\r
+#define bFM3_GPIO_EPFR01_RTO02E1               *((volatile unsigned int*)(0x4266C094UL))\r
+#define bFM3_GPIO_EPFR01_RTO03E0               *((volatile unsigned int*)(0x4266C098UL))\r
+#define bFM3_GPIO_EPFR01_RTO03E1               *((volatile unsigned int*)(0x4266C09CUL))\r
+#define bFM3_GPIO_EPFR01_RTO04E0               *((volatile unsigned int*)(0x4266C0A0UL))\r
+#define bFM3_GPIO_EPFR01_RTO04E1               *((volatile unsigned int*)(0x4266C0A4UL))\r
+#define bFM3_GPIO_EPFR01_RTO05E0               *((volatile unsigned int*)(0x4266C0A8UL))\r
+#define bFM3_GPIO_EPFR01_RTO05E1               *((volatile unsigned int*)(0x4266C0ACUL))\r
+#define bFM3_GPIO_EPFR01_DTTI0C                *((volatile unsigned int*)(0x4266C0B0UL))\r
+#define bFM3_GPIO_EPFR01_DTTI0S0               *((volatile unsigned int*)(0x4266C0C0UL))\r
+#define bFM3_GPIO_EPFR01_DTTI0S1               *((volatile unsigned int*)(0x4266C0C4UL))\r
+#define bFM3_GPIO_EPFR01_FRCK0S0               *((volatile unsigned int*)(0x4266C0C8UL))\r
+#define bFM3_GPIO_EPFR01_FRCK0S1               *((volatile unsigned int*)(0x4266C0CCUL))\r
+#define bFM3_GPIO_EPFR01_IC00S0                *((volatile unsigned int*)(0x4266C0D0UL))\r
+#define bFM3_GPIO_EPFR01_IC00S1                *((volatile unsigned int*)(0x4266C0D4UL))\r
+#define bFM3_GPIO_EPFR01_IC00S2                *((volatile unsigned int*)(0x4266C0D8UL))\r
+#define bFM3_GPIO_EPFR01_IC01S0                *((volatile unsigned int*)(0x4266C0DCUL))\r
+#define bFM3_GPIO_EPFR01_IC01S1                *((volatile unsigned int*)(0x4266C0E0UL))\r
+#define bFM3_GPIO_EPFR01_IC01S2                *((volatile unsigned int*)(0x4266C0E4UL))\r
+#define bFM3_GPIO_EPFR01_IC02S0                *((volatile unsigned int*)(0x4266C0E8UL))\r
+#define bFM3_GPIO_EPFR01_IC02S1                *((volatile unsigned int*)(0x4266C0ECUL))\r
+#define bFM3_GPIO_EPFR01_IC02S2                *((volatile unsigned int*)(0x4266C0F0UL))\r
+#define bFM3_GPIO_EPFR01_IC03S0                *((volatile unsigned int*)(0x4266C0F4UL))\r
+#define bFM3_GPIO_EPFR01_IC03S1                *((volatile unsigned int*)(0x4266C0F8UL))\r
+#define bFM3_GPIO_EPFR01_IC03S2                *((volatile unsigned int*)(0x4266C0FCUL))\r
+#define bFM3_GPIO_EPFR02_RTO10E0               *((volatile unsigned int*)(0x4266C100UL))\r
+#define bFM3_GPIO_EPFR02_RTO10E1               *((volatile unsigned int*)(0x4266C104UL))\r
+#define bFM3_GPIO_EPFR02_RTO11E0               *((volatile unsigned int*)(0x4266C108UL))\r
+#define bFM3_GPIO_EPFR02_RTO11E1               *((volatile unsigned int*)(0x4266C10CUL))\r
+#define bFM3_GPIO_EPFR02_RTO12E0               *((volatile unsigned int*)(0x4266C110UL))\r
+#define bFM3_GPIO_EPFR02_RTO12E1               *((volatile unsigned int*)(0x4266C114UL))\r
+#define bFM3_GPIO_EPFR02_RTO13E0               *((volatile unsigned int*)(0x4266C118UL))\r
+#define bFM3_GPIO_EPFR02_RTO13E1               *((volatile unsigned int*)(0x4266C11CUL))\r
+#define bFM3_GPIO_EPFR02_RTO14E0               *((volatile unsigned int*)(0x4266C120UL))\r
+#define bFM3_GPIO_EPFR02_RTO14E1               *((volatile unsigned int*)(0x4266C124UL))\r
+#define bFM3_GPIO_EPFR02_RTO15E0               *((volatile unsigned int*)(0x4266C128UL))\r
+#define bFM3_GPIO_EPFR02_RTO15E1               *((volatile unsigned int*)(0x4266C12CUL))\r
+#define bFM3_GPIO_EPFR02_DTTI1C                *((volatile unsigned int*)(0x4266C130UL))\r
+#define bFM3_GPIO_EPFR02_DTTI1S0               *((volatile unsigned int*)(0x4266C140UL))\r
+#define bFM3_GPIO_EPFR02_DTTI1S1               *((volatile unsigned int*)(0x4266C144UL))\r
+#define bFM3_GPIO_EPFR02_FRCK1S0               *((volatile unsigned int*)(0x4266C148UL))\r
+#define bFM3_GPIO_EPFR02_FRCK1S1               *((volatile unsigned int*)(0x4266C14CUL))\r
+#define bFM3_GPIO_EPFR02_IC10S0                *((volatile unsigned int*)(0x4266C150UL))\r
+#define bFM3_GPIO_EPFR02_IC10S1                *((volatile unsigned int*)(0x4266C154UL))\r
+#define bFM3_GPIO_EPFR02_IC10S2                *((volatile unsigned int*)(0x4266C158UL))\r
+#define bFM3_GPIO_EPFR02_IC11S0                *((volatile unsigned int*)(0x4266C15CUL))\r
+#define bFM3_GPIO_EPFR02_IC11S1                *((volatile unsigned int*)(0x4266C160UL))\r
+#define bFM3_GPIO_EPFR02_IC11S2                *((volatile unsigned int*)(0x4266C164UL))\r
+#define bFM3_GPIO_EPFR02_IC12S0                *((volatile unsigned int*)(0x4266C168UL))\r
+#define bFM3_GPIO_EPFR02_IC12S1                *((volatile unsigned int*)(0x4266C16CUL))\r
+#define bFM3_GPIO_EPFR02_IC12S2                *((volatile unsigned int*)(0x4266C170UL))\r
+#define bFM3_GPIO_EPFR02_IC13S0                *((volatile unsigned int*)(0x4266C174UL))\r
+#define bFM3_GPIO_EPFR02_IC13S1                *((volatile unsigned int*)(0x4266C178UL))\r
+#define bFM3_GPIO_EPFR02_IC13S2                *((volatile unsigned int*)(0x4266C17CUL))\r
+#define bFM3_GPIO_EPFR04_TIOA0E0               *((volatile unsigned int*)(0x4266C208UL))\r
+#define bFM3_GPIO_EPFR04_TIOA0E1               *((volatile unsigned int*)(0x4266C20CUL))\r
+#define bFM3_GPIO_EPFR04_TIOB0S0               *((volatile unsigned int*)(0x4266C210UL))\r
+#define bFM3_GPIO_EPFR04_TIOB0S1               *((volatile unsigned int*)(0x4266C214UL))\r
+#define bFM3_GPIO_EPFR04_TIOA1S0               *((volatile unsigned int*)(0x4266C220UL))\r
+#define bFM3_GPIO_EPFR04_TIOA1S1               *((volatile unsigned int*)(0x4266C224UL))\r
+#define bFM3_GPIO_EPFR04_TIOA1E0               *((volatile unsigned int*)(0x4266C228UL))\r
+#define bFM3_GPIO_EPFR04_TIOA1E1               *((volatile unsigned int*)(0x4266C22CUL))\r
+#define bFM3_GPIO_EPFR04_TIOB1S0               *((volatile unsigned int*)(0x4266C230UL))\r
+#define bFM3_GPIO_EPFR04_TIOB1S1               *((volatile unsigned int*)(0x4266C234UL))\r
+#define bFM3_GPIO_EPFR04_TIOA2E0               *((volatile unsigned int*)(0x4266C248UL))\r
+#define bFM3_GPIO_EPFR04_TIOA2E1               *((volatile unsigned int*)(0x4266C24CUL))\r
+#define bFM3_GPIO_EPFR04_TIOB2S0               *((volatile unsigned int*)(0x4266C250UL))\r
+#define bFM3_GPIO_EPFR04_TIOB2S1               *((volatile unsigned int*)(0x4266C254UL))\r
+#define bFM3_GPIO_EPFR04_TIOA3S0               *((volatile unsigned int*)(0x4266C260UL))\r
+#define bFM3_GPIO_EPFR04_TIOA3S1               *((volatile unsigned int*)(0x4266C264UL))\r
+#define bFM3_GPIO_EPFR04_TIOA3E0               *((volatile unsigned int*)(0x4266C268UL))\r
+#define bFM3_GPIO_EPFR04_TIOA3E1               *((volatile unsigned int*)(0x4266C26CUL))\r
+#define bFM3_GPIO_EPFR04_TIOB3S0               *((volatile unsigned int*)(0x4266C270UL))\r
+#define bFM3_GPIO_EPFR04_TIOB3S1               *((volatile unsigned int*)(0x4266C274UL))\r
+#define bFM3_GPIO_EPFR05_TIOA4E0               *((volatile unsigned int*)(0x4266C288UL))\r
+#define bFM3_GPIO_EPFR05_TIOA4E1               *((volatile unsigned int*)(0x4266C28CUL))\r
+#define bFM3_GPIO_EPFR05_TIOB4S0               *((volatile unsigned int*)(0x4266C290UL))\r
+#define bFM3_GPIO_EPFR05_TIOB4S1               *((volatile unsigned int*)(0x4266C294UL))\r
+#define bFM3_GPIO_EPFR05_TIOA5S0               *((volatile unsigned int*)(0x4266C2A0UL))\r
+#define bFM3_GPIO_EPFR05_TIOA5S1               *((volatile unsigned int*)(0x4266C2A4UL))\r
+#define bFM3_GPIO_EPFR05_TIOA5E0               *((volatile unsigned int*)(0x4266C2A8UL))\r
+#define bFM3_GPIO_EPFR05_TIOA5E1               *((volatile unsigned int*)(0x4266C2ACUL))\r
+#define bFM3_GPIO_EPFR05_TIOB5S0               *((volatile unsigned int*)(0x4266C2B0UL))\r
+#define bFM3_GPIO_EPFR05_TIOB5S1               *((volatile unsigned int*)(0x4266C2B4UL))\r
+#define bFM3_GPIO_EPFR05_TIOA6E0               *((volatile unsigned int*)(0x4266C2C8UL))\r
+#define bFM3_GPIO_EPFR05_TIOA6E1               *((volatile unsigned int*)(0x4266C2CCUL))\r
+#define bFM3_GPIO_EPFR05_TIOB6S0               *((volatile unsigned int*)(0x4266C2D0UL))\r
+#define bFM3_GPIO_EPFR05_TIOB6S1               *((volatile unsigned int*)(0x4266C2D4UL))\r
+#define bFM3_GPIO_EPFR05_TIOA7S0               *((volatile unsigned int*)(0x4266C2E0UL))\r
+#define bFM3_GPIO_EPFR05_TIOA7S1               *((volatile unsigned int*)(0x4266C2E4UL))\r
+#define bFM3_GPIO_EPFR05_TIOA7E0               *((volatile unsigned int*)(0x4266C2E8UL))\r
+#define bFM3_GPIO_EPFR05_TIOA7E1               *((volatile unsigned int*)(0x4266C2ECUL))\r
+#define bFM3_GPIO_EPFR05_TIOB7S0               *((volatile unsigned int*)(0x4266C2F0UL))\r
+#define bFM3_GPIO_EPFR05_TIOB7S1               *((volatile unsigned int*)(0x4266C2F4UL))\r
+#define bFM3_GPIO_EPFR06_EINT00S0              *((volatile unsigned int*)(0x4266C300UL))\r
+#define bFM3_GPIO_EPFR06_EINT00S1              *((volatile unsigned int*)(0x4266C304UL))\r
+#define bFM3_GPIO_EPFR06_EINT01S0              *((volatile unsigned int*)(0x4266C308UL))\r
+#define bFM3_GPIO_EPFR06_EINT01S1              *((volatile unsigned int*)(0x4266C30CUL))\r
+#define bFM3_GPIO_EPFR06_EINT02S0              *((volatile unsigned int*)(0x4266C310UL))\r
+#define bFM3_GPIO_EPFR06_EINT02S1              *((volatile unsigned int*)(0x4266C314UL))\r
+#define bFM3_GPIO_EPFR06_EINT03S0              *((volatile unsigned int*)(0x4266C318UL))\r
+#define bFM3_GPIO_EPFR06_EINT03S1              *((volatile unsigned int*)(0x4266C31CUL))\r
+#define bFM3_GPIO_EPFR06_EINT04S0              *((volatile unsigned int*)(0x4266C320UL))\r
+#define bFM3_GPIO_EPFR06_EINT04S1              *((volatile unsigned int*)(0x4266C324UL))\r
+#define bFM3_GPIO_EPFR06_EINT05S0              *((volatile unsigned int*)(0x4266C328UL))\r
+#define bFM3_GPIO_EPFR06_EINT05S1              *((volatile unsigned int*)(0x4266C32CUL))\r
+#define bFM3_GPIO_EPFR06_EINT06S0              *((volatile unsigned int*)(0x4266C330UL))\r
+#define bFM3_GPIO_EPFR06_EINT06S1              *((volatile unsigned int*)(0x4266C334UL))\r
+#define bFM3_GPIO_EPFR06_EINT07S0              *((volatile unsigned int*)(0x4266C338UL))\r
+#define bFM3_GPIO_EPFR06_EINT07S1              *((volatile unsigned int*)(0x4266C33CUL))\r
+#define bFM3_GPIO_EPFR06_EINT08S0              *((volatile unsigned int*)(0x4266C340UL))\r
+#define bFM3_GPIO_EPFR06_EINT08S1              *((volatile unsigned int*)(0x4266C344UL))\r
+#define bFM3_GPIO_EPFR06_EINT09S0              *((volatile unsigned int*)(0x4266C348UL))\r
+#define bFM3_GPIO_EPFR06_EINT09S1              *((volatile unsigned int*)(0x4266C34CUL))\r
+#define bFM3_GPIO_EPFR06_EINT10S0              *((volatile unsigned int*)(0x4266C350UL))\r
+#define bFM3_GPIO_EPFR06_EINT10S1              *((volatile unsigned int*)(0x4266C354UL))\r
+#define bFM3_GPIO_EPFR06_EINT11S0              *((volatile unsigned int*)(0x4266C358UL))\r
+#define bFM3_GPIO_EPFR06_EINT11S1              *((volatile unsigned int*)(0x4266C35CUL))\r
+#define bFM3_GPIO_EPFR06_EINT12S0              *((volatile unsigned int*)(0x4266C360UL))\r
+#define bFM3_GPIO_EPFR06_EINT12S1              *((volatile unsigned int*)(0x4266C364UL))\r
+#define bFM3_GPIO_EPFR06_EINT13S0              *((volatile unsigned int*)(0x4266C368UL))\r
+#define bFM3_GPIO_EPFR06_EINT13S1              *((volatile unsigned int*)(0x4266C36CUL))\r
+#define bFM3_GPIO_EPFR06_EINT14S0              *((volatile unsigned int*)(0x4266C370UL))\r
+#define bFM3_GPIO_EPFR06_EINT14S1              *((volatile unsigned int*)(0x4266C374UL))\r
+#define bFM3_GPIO_EPFR06_EINT15S0              *((volatile unsigned int*)(0x4266C378UL))\r
+#define bFM3_GPIO_EPFR06_EINT15S1              *((volatile unsigned int*)(0x4266C37CUL))\r
+#define bFM3_GPIO_EPFR07_SIN0S0                *((volatile unsigned int*)(0x4266C390UL))\r
+#define bFM3_GPIO_EPFR07_SIN0S1                *((volatile unsigned int*)(0x4266C394UL))\r
+#define bFM3_GPIO_EPFR07_SOT0B0                *((volatile unsigned int*)(0x4266C398UL))\r
+#define bFM3_GPIO_EPFR07_SOT0B1                *((volatile unsigned int*)(0x4266C39CUL))\r
+#define bFM3_GPIO_EPFR07_SCK0B0                *((volatile unsigned int*)(0x4266C3A0UL))\r
+#define bFM3_GPIO_EPFR07_SCK0B1                *((volatile unsigned int*)(0x4266C3A4UL))\r
+#define bFM3_GPIO_EPFR07_SIN1S0                *((volatile unsigned int*)(0x4266C3A8UL))\r
+#define bFM3_GPIO_EPFR07_SIN1S1                *((volatile unsigned int*)(0x4266C3ACUL))\r
+#define bFM3_GPIO_EPFR07_SOT1B0                *((volatile unsigned int*)(0x4266C3B0UL))\r
+#define bFM3_GPIO_EPFR07_SOT1B1                *((volatile unsigned int*)(0x4266C3B4UL))\r
+#define bFM3_GPIO_EPFR07_SCK1B0                *((volatile unsigned int*)(0x4266C3B8UL))\r
+#define bFM3_GPIO_EPFR07_SCK1B1                *((volatile unsigned int*)(0x4266C3BCUL))\r
+#define bFM3_GPIO_EPFR07_SIN2S0                *((volatile unsigned int*)(0x4266C3C0UL))\r
+#define bFM3_GPIO_EPFR07_SIN2S1                *((volatile unsigned int*)(0x4266C3C4UL))\r
+#define bFM3_GPIO_EPFR07_SOT2B0                *((volatile unsigned int*)(0x4266C3C8UL))\r
+#define bFM3_GPIO_EPFR07_SOT2B1                *((volatile unsigned int*)(0x4266C3CCUL))\r
+#define bFM3_GPIO_EPFR07_SCK2B0                *((volatile unsigned int*)(0x4266C3D0UL))\r
+#define bFM3_GPIO_EPFR07_SCK2B1                *((volatile unsigned int*)(0x4266C3D4UL))\r
+#define bFM3_GPIO_EPFR07_SIN3S0                *((volatile unsigned int*)(0x4266C3D8UL))\r
+#define bFM3_GPIO_EPFR07_SIN3S1                *((volatile unsigned int*)(0x4266C3DCUL))\r
+#define bFM3_GPIO_EPFR07_SOT3B0                *((volatile unsigned int*)(0x4266C3E0UL))\r
+#define bFM3_GPIO_EPFR07_SOT3B1                *((volatile unsigned int*)(0x4266C3E4UL))\r
+#define bFM3_GPIO_EPFR07_SCK3B0                *((volatile unsigned int*)(0x4266C3E8UL))\r
+#define bFM3_GPIO_EPFR07_SCK3B1                *((volatile unsigned int*)(0x4266C3ECUL))\r
+#define bFM3_GPIO_EPFR08_RTS4E0                *((volatile unsigned int*)(0x4266C400UL))\r
+#define bFM3_GPIO_EPFR08_RTS4E1                *((volatile unsigned int*)(0x4266C404UL))\r
+#define bFM3_GPIO_EPFR08_CTS4S0                *((volatile unsigned int*)(0x4266C408UL))\r
+#define bFM3_GPIO_EPFR08_CTS4S1                *((volatile unsigned int*)(0x4266C40CUL))\r
+#define bFM3_GPIO_EPFR08_SIN4S0                *((volatile unsigned int*)(0x4266C410UL))\r
+#define bFM3_GPIO_EPFR08_SIN4S1                *((volatile unsigned int*)(0x4266C414UL))\r
+#define bFM3_GPIO_EPFR08_SOT4B0                *((volatile unsigned int*)(0x4266C418UL))\r
+#define bFM3_GPIO_EPFR08_SOT4B1                *((volatile unsigned int*)(0x4266C41CUL))\r
+#define bFM3_GPIO_EPFR08_SCK4B0                *((volatile unsigned int*)(0x4266C420UL))\r
+#define bFM3_GPIO_EPFR08_SCK4B1                *((volatile unsigned int*)(0x4266C424UL))\r
+#define bFM3_GPIO_EPFR08_SIN5S0                *((volatile unsigned int*)(0x4266C428UL))\r
+#define bFM3_GPIO_EPFR08_SIN5S1                *((volatile unsigned int*)(0x4266C42CUL))\r
+#define bFM3_GPIO_EPFR08_SOT5B0                *((volatile unsigned int*)(0x4266C430UL))\r
+#define bFM3_GPIO_EPFR08_SOT5B1                *((volatile unsigned int*)(0x4266C434UL))\r
+#define bFM3_GPIO_EPFR08_SCK5B0                *((volatile unsigned int*)(0x4266C438UL))\r
+#define bFM3_GPIO_EPFR08_SCK5B1                *((volatile unsigned int*)(0x4266C43CUL))\r
+#define bFM3_GPIO_EPFR08_SIN6S0                *((volatile unsigned int*)(0x4266C440UL))\r
+#define bFM3_GPIO_EPFR08_SIN6S1                *((volatile unsigned int*)(0x4266C444UL))\r
+#define bFM3_GPIO_EPFR08_SOT6B0                *((volatile unsigned int*)(0x4266C448UL))\r
+#define bFM3_GPIO_EPFR08_SOT6B1                *((volatile unsigned int*)(0x4266C44CUL))\r
+#define bFM3_GPIO_EPFR08_SCK6B0                *((volatile unsigned int*)(0x4266C450UL))\r
+#define bFM3_GPIO_EPFR08_SCK6B1                *((volatile unsigned int*)(0x4266C454UL))\r
+#define bFM3_GPIO_EPFR08_SIN7S0                *((volatile unsigned int*)(0x4266C458UL))\r
+#define bFM3_GPIO_EPFR08_SIN7S1                *((volatile unsigned int*)(0x4266C45CUL))\r
+#define bFM3_GPIO_EPFR08_SOT7B0                *((volatile unsigned int*)(0x4266C460UL))\r
+#define bFM3_GPIO_EPFR08_SOT7B1                *((volatile unsigned int*)(0x4266C464UL))\r
+#define bFM3_GPIO_EPFR08_SCK7B0                *((volatile unsigned int*)(0x4266C468UL))\r
+#define bFM3_GPIO_EPFR08_SCK7B1                *((volatile unsigned int*)(0x4266C46CUL))\r
+#define bFM3_GPIO_EPFR09_QAIN0S0               *((volatile unsigned int*)(0x4266C480UL))\r
+#define bFM3_GPIO_EPFR09_QAIN0S1               *((volatile unsigned int*)(0x4266C484UL))\r
+#define bFM3_GPIO_EPFR09_QBIN0S0               *((volatile unsigned int*)(0x4266C488UL))\r
+#define bFM3_GPIO_EPFR09_QBIN0S1               *((volatile unsigned int*)(0x4266C48CUL))\r
+#define bFM3_GPIO_EPFR09_QZIN0S0               *((volatile unsigned int*)(0x4266C490UL))\r
+#define bFM3_GPIO_EPFR09_QZIN0S1               *((volatile unsigned int*)(0x4266C494UL))\r
+#define bFM3_GPIO_EPFR09_QAIN1S0               *((volatile unsigned int*)(0x4266C498UL))\r
+#define bFM3_GPIO_EPFR09_QAIN1S1               *((volatile unsigned int*)(0x4266C49CUL))\r
+#define bFM3_GPIO_EPFR09_QBIN1S0               *((volatile unsigned int*)(0x4266C4A0UL))\r
+#define bFM3_GPIO_EPFR09_QBIN1S1               *((volatile unsigned int*)(0x4266C4A4UL))\r
+#define bFM3_GPIO_EPFR09_QZIN1S0               *((volatile unsigned int*)(0x4266C4A8UL))\r
+#define bFM3_GPIO_EPFR09_QZIN1S1               *((volatile unsigned int*)(0x4266C4ACUL))\r
+#define bFM3_GPIO_EPFR09_ADTRG0S0              *((volatile unsigned int*)(0x4266C4B0UL))\r
+#define bFM3_GPIO_EPFR09_ADTRG0S1              *((volatile unsigned int*)(0x4266C4B4UL))\r
+#define bFM3_GPIO_EPFR09_ADTRG0S2              *((volatile unsigned int*)(0x4266C4B8UL))\r
+#define bFM3_GPIO_EPFR09_ADTRG0S3              *((volatile unsigned int*)(0x4266C4BCUL))\r
+#define bFM3_GPIO_EPFR09_ADTRG1S0              *((volatile unsigned int*)(0x4266C4C0UL))\r
+#define bFM3_GPIO_EPFR09_ADTRG1S1              *((volatile unsigned int*)(0x4266C4C4UL))\r
+#define bFM3_GPIO_EPFR09_ADTRG1S2              *((volatile unsigned int*)(0x4266C4C8UL))\r
+#define bFM3_GPIO_EPFR09_ADTRG1S3              *((volatile unsigned int*)(0x4266C4CCUL))\r
+#define bFM3_GPIO_EPFR09_ADTRG2S0              *((volatile unsigned int*)(0x4266C4D0UL))\r
+#define bFM3_GPIO_EPFR09_ADTRG2S1              *((volatile unsigned int*)(0x4266C4D4UL))\r
+#define bFM3_GPIO_EPFR09_ADTRG2S2              *((volatile unsigned int*)(0x4266C4D8UL))\r
+#define bFM3_GPIO_EPFR09_ADTRG2S3              *((volatile unsigned int*)(0x4266C4DCUL))\r
+#define bFM3_GPIO_EPFR09_CRX0S0                *((volatile unsigned int*)(0x4266C4E0UL))\r
+#define bFM3_GPIO_EPFR09_CRX0S1                *((volatile unsigned int*)(0x4266C4E4UL))\r
+#define bFM3_GPIO_EPFR09_CTX0E0                *((volatile unsigned int*)(0x4266C4E8UL))\r
+#define bFM3_GPIO_EPFR09_CTX0E1                *((volatile unsigned int*)(0x4266C4ECUL))\r
+#define bFM3_GPIO_EPFR09_CRX1S0                *((volatile unsigned int*)(0x4266C4F0UL))\r
+#define bFM3_GPIO_EPFR09_CRX1S1                *((volatile unsigned int*)(0x4266C4F4UL))\r
+#define bFM3_GPIO_EPFR09_CTX1E0                *((volatile unsigned int*)(0x4266C4F8UL))\r
+#define bFM3_GPIO_EPFR09_CTX1E1                *((volatile unsigned int*)(0x4266C4FCUL))\r
+#define bFM3_GPIO_EPFR10_UEDEFB                *((volatile unsigned int*)(0x4266C500UL))\r
+#define bFM3_GPIO_EPFR10_UEDTHB                *((volatile unsigned int*)(0x4266C504UL))\r
+#define bFM3_GPIO_EPFR10_TESTB                 *((volatile unsigned int*)(0x4266C508UL))\r
+#define bFM3_GPIO_EPFR10_UEWEXE                *((volatile unsigned int*)(0x4266C50CUL))\r
+#define bFM3_GPIO_EPFR10_UEDQME                *((volatile unsigned int*)(0x4266C510UL))\r
+#define bFM3_GPIO_EPFR10_UEOEXE                *((volatile unsigned int*)(0x4266C514UL))\r
+#define bFM3_GPIO_EPFR10_UEFLSE                *((volatile unsigned int*)(0x4266C518UL))\r
+#define bFM3_GPIO_EPFR10_UECS1E                *((volatile unsigned int*)(0x4266C51CUL))\r
+#define bFM3_GPIO_EPFR10_UECS2E                *((volatile unsigned int*)(0x4266C520UL))\r
+#define bFM3_GPIO_EPFR10_UECS3E                *((volatile unsigned int*)(0x4266C524UL))\r
+#define bFM3_GPIO_EPFR10_UECS4E                *((volatile unsigned int*)(0x4266C528UL))\r
+#define bFM3_GPIO_EPFR10_UECS5E                *((volatile unsigned int*)(0x4266C52CUL))\r
+#define bFM3_GPIO_EPFR10_UECS6E                *((volatile unsigned int*)(0x4266C530UL))\r
+#define bFM3_GPIO_EPFR10_UECS7E                *((volatile unsigned int*)(0x4266C534UL))\r
+#define bFM3_GPIO_EPFR10_UEAOOE                *((volatile unsigned int*)(0x4266C538UL))\r
+#define bFM3_GPIO_EPFR10_UEA08E                *((volatile unsigned int*)(0x4266C53CUL))\r
+#define bFM3_GPIO_EPFR10_UEA09E                *((volatile unsigned int*)(0x4266C540UL))\r
+#define bFM3_GPIO_EPFR10_UEA10E                *((volatile unsigned int*)(0x4266C544UL))\r
+#define bFM3_GPIO_EPFR10_UEA11E                *((volatile unsigned int*)(0x4266C548UL))\r
+#define bFM3_GPIO_EPFR10_UEA12E                *((volatile unsigned int*)(0x4266C54CUL))\r
+#define bFM3_GPIO_EPFR10_UEA13E                *((volatile unsigned int*)(0x4266C550UL))\r
+#define bFM3_GPIO_EPFR10_UEA14E                *((volatile unsigned int*)(0x4266C554UL))\r
+#define bFM3_GPIO_EPFR10_UEA15E                *((volatile unsigned int*)(0x4266C558UL))\r
+#define bFM3_GPIO_EPFR10_UEA16E                *((volatile unsigned int*)(0x4266C55CUL))\r
+#define bFM3_GPIO_EPFR10_UEA17E                *((volatile unsigned int*)(0x4266C560UL))\r
+#define bFM3_GPIO_EPFR10_UEA18E                *((volatile unsigned int*)(0x4266C564UL))\r
+#define bFM3_GPIO_EPFR10_UEA19E                *((volatile unsigned int*)(0x4266C568UL))\r
+#define bFM3_GPIO_EPFR10_UEA20E                *((volatile unsigned int*)(0x4266C56CUL))\r
+#define bFM3_GPIO_EPFR10_UEA21E                *((volatile unsigned int*)(0x4266C570UL))\r
+#define bFM3_GPIO_EPFR10_UEA22E                *((volatile unsigned int*)(0x4266C574UL))\r
+#define bFM3_GPIO_EPFR10_UEA23E                *((volatile unsigned int*)(0x4266C578UL))\r
+#define bFM3_GPIO_EPFR10_UEA24E                *((volatile unsigned int*)(0x4266C57CUL))\r
+\r
+/* Low voltage detection registers */\r
+#define bFM3_LVD_LVD_CTL_SVHI0                 *((volatile unsigned int*)(0x426A0008UL))\r
+#define bFM3_LVD_LVD_CTL_SVHI1                 *((volatile unsigned int*)(0x426A000CUL))\r
+#define bFM3_LVD_LVD_CTL_SVHI2                 *((volatile unsigned int*)(0x426A0010UL))\r
+#define bFM3_LVD_LVD_CTL_SVHI3                 *((volatile unsigned int*)(0x426A0014UL))\r
+#define bFM3_LVD_LVD_CTL_LVDIE                 *((volatile unsigned int*)(0x426A001CUL))\r
+#define bFM3_LVD_LVD_STR_LVDIR                 *((volatile unsigned int*)(0x426A009CUL))\r
+#define bFM3_LVD_LVD_CLR_LVDCL                 *((volatile unsigned int*)(0x426A011CUL))\r
+#define bFM3_LVD_LVD_STR2_LVDIRDY              *((volatile unsigned int*)(0x426A021CUL))\r
+\r
+/* USB clock registers */\r
+#define bFM3_USBCLK_UCCR_UCEN                  *((volatile unsigned int*)(0x426C0000UL))\r
+#define bFM3_USBCLK_UCCR_UCSEL                 *((volatile unsigned int*)(0x426C0004UL))\r
+#define bFM3_USBCLK_UPCR1_UPLLEN               *((volatile unsigned int*)(0x426C0080UL))\r
+#define bFM3_USBCLK_UPCR1_UPINC                *((volatile unsigned int*)(0x426C0084UL))\r
+#define bFM3_USBCLK_UPCR2_UPOWT0               *((volatile unsigned int*)(0x426C0100UL))\r
+#define bFM3_USBCLK_UPCR2_UPOWT1               *((volatile unsigned int*)(0x426C0104UL))\r
+#define bFM3_USBCLK_UPCR2_UPOWT2               *((volatile unsigned int*)(0x426C0108UL))\r
+#define bFM3_USBCLK_UPCR3_UPLLK0               *((volatile unsigned int*)(0x426C0180UL))\r
+#define bFM3_USBCLK_UPCR3_UPLLK1               *((volatile unsigned int*)(0x426C0184UL))\r
+#define bFM3_USBCLK_UPCR3_UPLLK2               *((volatile unsigned int*)(0x426C0188UL))\r
+#define bFM3_USBCLK_UPCR3_UPLLK3               *((volatile unsigned int*)(0x426C018CUL))\r
+#define bFM3_USBCLK_UPCR3_UPLLK4               *((volatile unsigned int*)(0x426C0190UL))\r
+#define bFM3_USBCLK_UPCR4_UPLLN0               *((volatile unsigned int*)(0x426C0200UL))\r
+#define bFM3_USBCLK_UPCR4_UPLLN1               *((volatile unsigned int*)(0x426C0204UL))\r
+#define bFM3_USBCLK_UPCR4_UPLLN2               *((volatile unsigned int*)(0x426C0208UL))\r
+#define bFM3_USBCLK_UPCR4_UPLLN3               *((volatile unsigned int*)(0x426C020CUL))\r
+#define bFM3_USBCLK_UPCR4_UPLLN4               *((volatile unsigned int*)(0x426C0210UL))\r
+#define bFM3_USBCLK_UP_STR_UPRDY               *((volatile unsigned int*)(0x426C0280UL))\r
+#define bFM3_USBCLK_UPINT_ENR_UPCSE            *((volatile unsigned int*)(0x426C0300UL))\r
+#define bFM3_USBCLK_UPINT_CLR_UPCSC            *((volatile unsigned int*)(0x426C0380UL))\r
+#define bFM3_USBCLK_UPINT_STR_UPCSI            *((volatile unsigned int*)(0x426C0400UL))\r
+#define bFM3_USBCLK_USBEN_USBEN                *((volatile unsigned int*)(0x426C0600UL))\r
+\r
+/* CAN prescaler register */\r
+#define bFM3_CANPRES_CANPRE_CANPRE0            *((volatile unsigned int*)(0x426E0000UL))\r
+#define bFM3_CANPRES_CANPRE_CANPRE1            *((volatile unsigned int*)(0x426E0004UL))\r
+#define bFM3_CANPRES_CANPRE_CANPRE2            *((volatile unsigned int*)(0x426E0008UL))\r
+#define bFM3_CANPRES_CANPRE_CANPRE3            *((volatile unsigned int*)(0x426E000CUL))\r
+\r
+/* UART asynchronous channel 0 registers */\r
+#define bFM3_MFS0_UART_SMR_SOE                 *((volatile unsigned int*)(0x42700000UL))\r
+#define bFM3_MFS0_UART_SMR_BDS                 *((volatile unsigned int*)(0x42700008UL))\r
+#define bFM3_MFS0_UART_SMR_SBL                 *((volatile unsigned int*)(0x4270000CUL))\r
+#define bFM3_MFS0_UART_SMR_WUCR                *((volatile unsigned int*)(0x42700010UL))\r
+#define bFM3_MFS0_UART_SMR_MD0                 *((volatile unsigned int*)(0x42700014UL))\r
+#define bFM3_MFS0_UART_SMR_MD1                 *((volatile unsigned int*)(0x42700018UL))\r
+#define bFM3_MFS0_UART_SMR_MD2                 *((volatile unsigned int*)(0x4270001CUL))\r
+#define bFM3_MFS0_UART_SCR_TXE                 *((volatile unsigned int*)(0x42700020UL))\r
+#define bFM3_MFS0_UART_SCR_RXE                 *((volatile unsigned int*)(0x42700024UL))\r
+#define bFM3_MFS0_UART_SCR_TBIE                *((volatile unsigned int*)(0x42700028UL))\r
+#define bFM3_MFS0_UART_SCR_TIE                 *((volatile unsigned int*)(0x4270002CUL))\r
+#define bFM3_MFS0_UART_SCR_RIE                 *((volatile unsigned int*)(0x42700030UL))\r
+#define bFM3_MFS0_UART_SCR_UPCL                *((volatile unsigned int*)(0x4270003CUL))\r
+#define bFM3_MFS0_UART_ESCR_L0                 *((volatile unsigned int*)(0x42700080UL))\r
+#define bFM3_MFS0_UART_ESCR_L1                 *((volatile unsigned int*)(0x42700084UL))\r
+#define bFM3_MFS0_UART_ESCR_L2                 *((volatile unsigned int*)(0x42700088UL))\r
+#define bFM3_MFS0_UART_ESCR_P                  *((volatile unsigned int*)(0x4270008CUL))\r
+#define bFM3_MFS0_UART_ESCR_PEN                *((volatile unsigned int*)(0x42700090UL))\r
+#define bFM3_MFS0_UART_ESCR_INV                *((volatile unsigned int*)(0x42700094UL))\r
+#define bFM3_MFS0_UART_ESCR_ESBL               *((volatile unsigned int*)(0x42700098UL))\r
+#define bFM3_MFS0_UART_ESCR_FLWEN              *((volatile unsigned int*)(0x4270009CUL))\r
+#define bFM3_MFS0_UART_SSR_TBI                 *((volatile unsigned int*)(0x427000A0UL))\r
+#define bFM3_MFS0_UART_SSR_TDRE                *((volatile unsigned int*)(0x427000A4UL))\r
+#define bFM3_MFS0_UART_SSR_RDRF                *((volatile unsigned int*)(0x427000A8UL))\r
+#define bFM3_MFS0_UART_SSR_ORE                 *((volatile unsigned int*)(0x427000ACUL))\r
+#define bFM3_MFS0_UART_SSR_FRE                 *((volatile unsigned int*)(0x427000B0UL))\r
+#define bFM3_MFS0_UART_SSR_PE                  *((volatile unsigned int*)(0x427000B4UL))\r
+#define bFM3_MFS0_UART_SSR_REC                 *((volatile unsigned int*)(0x427000BCUL))\r
+#define bFM3_MFS0_UART_RDR_AD                  *((volatile unsigned int*)(0x42700120UL))\r
+#define bFM3_MFS0_UART_TDR_AD                  *((volatile unsigned int*)(0x42700120UL))\r
+#define bFM3_MFS0_UART_BGR_EXT                 *((volatile unsigned int*)(0x427001BCUL))\r
+#define bFM3_MFS0_UART_BGR1_EXT                *((volatile unsigned int*)(0x427001BCUL))\r
+\r
+/* UART synchronous channel 0 registers */\r
+#define bFM3_MFS0_CSIO_SMR_SOE                 *((volatile unsigned int*)(0x42700000UL))\r
+#define bFM3_MFS0_CSIO_SMR_SCKE                *((volatile unsigned int*)(0x42700004UL))\r
+#define bFM3_MFS0_CSIO_SMR_BDS                 *((volatile unsigned int*)(0x42700008UL))\r
+#define bFM3_MFS0_CSIO_SMR_SCINV               *((volatile unsigned int*)(0x4270000CUL))\r
+#define bFM3_MFS0_CSIO_SMR_WUCR                *((volatile unsigned int*)(0x42700010UL))\r
+#define bFM3_MFS0_CSIO_SMR_MD0                 *((volatile unsigned int*)(0x42700014UL))\r
+#define bFM3_MFS0_CSIO_SMR_MD1                 *((volatile unsigned int*)(0x42700018UL))\r
+#define bFM3_MFS0_CSIO_SMR_MD2                 *((volatile unsigned int*)(0x4270001CUL))\r
+#define bFM3_MFS0_CSIO_SCR_TXE                 *((volatile unsigned int*)(0x42700020UL))\r
+#define bFM3_MFS0_CSIO_SCR_RXE                 *((volatile unsigned int*)(0x42700024UL))\r
+#define bFM3_MFS0_CSIO_SCR_TBIE                *((volatile unsigned int*)(0x42700028UL))\r
+#define bFM3_MFS0_CSIO_SCR_TIE                 *((volatile unsigned int*)(0x4270002CUL))\r
+#define bFM3_MFS0_CSIO_SCR_RIE                 *((volatile unsigned int*)(0x42700030UL))\r
+#define bFM3_MFS0_CSIO_SCR_SPI                 *((volatile unsigned int*)(0x42700034UL))\r
+#define bFM3_MFS0_CSIO_SCR_MS                  *((volatile unsigned int*)(0x42700038UL))\r
+#define bFM3_MFS0_CSIO_SCR_UPCL                *((volatile unsigned int*)(0x4270003CUL))\r
+#define bFM3_MFS0_CSIO_ESCR_L0                 *((volatile unsigned int*)(0x42700080UL))\r
+#define bFM3_MFS0_CSIO_ESCR_L1                 *((volatile unsigned int*)(0x42700084UL))\r
+#define bFM3_MFS0_CSIO_ESCR_L2                 *((volatile unsigned int*)(0x42700088UL))\r
+#define bFM3_MFS0_CSIO_ESCR_WT0                *((volatile unsigned int*)(0x4270008CUL))\r
+#define bFM3_MFS0_CSIO_ESCR_WT1                *((volatile unsigned int*)(0x42700090UL))\r
+#define bFM3_MFS0_CSIO_ESCR_SOP                *((volatile unsigned int*)(0x4270009CUL))\r
+#define bFM3_MFS0_CSIO_SSR_TBI                 *((volatile unsigned int*)(0x427000A0UL))\r
+#define bFM3_MFS0_CSIO_SSR_TDRE                *((volatile unsigned int*)(0x427000A4UL))\r
+#define bFM3_MFS0_CSIO_SSR_RDRF                *((volatile unsigned int*)(0x427000A8UL))\r
+#define bFM3_MFS0_CSIO_SSR_ORE                 *((volatile unsigned int*)(0x427000ACUL))\r
+#define bFM3_MFS0_CSIO_SSR_REC                 *((volatile unsigned int*)(0x427000BCUL))\r
+\r
+/* UART LIN channel 0 registers */\r
+#define bFM3_MFS0_LIN_SMR_SOE                  *((volatile unsigned int*)(0x42700000UL))\r
+#define bFM3_MFS0_LIN_SMR_SBL                  *((volatile unsigned int*)(0x4270000CUL))\r
+#define bFM3_MFS0_LIN_SMR_WUCR                 *((volatile unsigned int*)(0x42700010UL))\r
+#define bFM3_MFS0_LIN_SMR_MD0                  *((volatile unsigned int*)(0x42700014UL))\r
+#define bFM3_MFS0_LIN_SMR_MD1                  *((volatile unsigned int*)(0x42700018UL))\r
+#define bFM3_MFS0_LIN_SMR_MD2                  *((volatile unsigned int*)(0x4270001CUL))\r
+#define bFM3_MFS0_LIN_SCR_TXE                  *((volatile unsigned int*)(0x42700020UL))\r
+#define bFM3_MFS0_LIN_SCR_RXE                  *((volatile unsigned int*)(0x42700024UL))\r
+#define bFM3_MFS0_LIN_SCR_TBIE                 *((volatile unsigned int*)(0x42700028UL))\r
+#define bFM3_MFS0_LIN_SCR_TIE                  *((volatile unsigned int*)(0x4270002CUL))\r
+#define bFM3_MFS0_LIN_SCR_RIE                  *((volatile unsigned int*)(0x42700030UL))\r
+#define bFM3_MFS0_LIN_SCR_LBR                  *((volatile unsigned int*)(0x42700034UL))\r
+#define bFM3_MFS0_LIN_SCR_MS                   *((volatile unsigned int*)(0x42700038UL))\r
+#define bFM3_MFS0_LIN_SCR_UPCL                 *((volatile unsigned int*)(0x4270003CUL))\r
+#define bFM3_MFS0_LIN_ESCR_DEL0                *((volatile unsigned int*)(0x42700080UL))\r
+#define bFM3_MFS0_LIN_ESCR_DEL1                *((volatile unsigned int*)(0x42700084UL))\r
+#define bFM3_MFS0_LIN_ESCR_LBL0                *((volatile unsigned int*)(0x42700088UL))\r
+#define bFM3_MFS0_LIN_ESCR_LBL1                *((volatile unsigned int*)(0x4270008CUL))\r
+#define bFM3_MFS0_LIN_ESCR_LBIE                *((volatile unsigned int*)(0x42700090UL))\r
+#define bFM3_MFS0_LIN_ESCR_ESBL                *((volatile unsigned int*)(0x42700098UL))\r
+#define bFM3_MFS0_LIN_SSR_TBI                  *((volatile unsigned int*)(0x427000A0UL))\r
+#define bFM3_MFS0_LIN_SSR_TDRE                 *((volatile unsigned int*)(0x427000A4UL))\r
+#define bFM3_MFS0_LIN_SSR_RDRF                 *((volatile unsigned int*)(0x427000A8UL))\r
+#define bFM3_MFS0_LIN_SSR_ORE                  *((volatile unsigned int*)(0x427000ACUL))\r
+#define bFM3_MFS0_LIN_SSR_FRE                  *((volatile unsigned int*)(0x427000B0UL))\r
+#define bFM3_MFS0_LIN_SSR_LBD                  *((volatile unsigned int*)(0x427000B4UL))\r
+#define bFM3_MFS0_LIN_SSR_REC                  *((volatile unsigned int*)(0x427000BCUL))\r
+#define bFM3_MFS0_LIN_BGR_EXT                  *((volatile unsigned int*)(0x427001BCUL))\r
+#define bFM3_MFS0_LIN_BGR1_EXT                 *((volatile unsigned int*)(0x427001BCUL))\r
+\r
+/* I2C channel 0 registers */\r
+#define bFM3_MFS0_I2C_SMR_ITST0                *((volatile unsigned int*)(0x42700000UL))\r
+#define bFM3_MFS0_I2C_SMR_ITST1                *((volatile unsigned int*)(0x42700004UL))\r
+#define bFM3_MFS0_I2C_SMR_TIE                  *((volatile unsigned int*)(0x42700008UL))\r
+#define bFM3_MFS0_I2C_SMR_RIE                  *((volatile unsigned int*)(0x4270000CUL))\r
+#define bFM3_MFS0_I2C_SMR_WUCR                 *((volatile unsigned int*)(0x42700010UL))\r
+#define bFM3_MFS0_I2C_SMR_MD0                  *((volatile unsigned int*)(0x42700014UL))\r
+#define bFM3_MFS0_I2C_SMR_MD1                  *((volatile unsigned int*)(0x42700018UL))\r
+#define bFM3_MFS0_I2C_SMR_MD2                  *((volatile unsigned int*)(0x4270001CUL))\r
+#define bFM3_MFS0_I2C_IBCR_INT                 *((volatile unsigned int*)(0x42700020UL))\r
+#define bFM3_MFS0_I2C_IBCR_BER                 *((volatile unsigned int*)(0x42700024UL))\r
+#define bFM3_MFS0_I2C_IBCR_INTE                *((volatile unsigned int*)(0x42700028UL))\r
+#define bFM3_MFS0_I2C_IBCR_CNDE                *((volatile unsigned int*)(0x4270002CUL))\r
+#define bFM3_MFS0_I2C_IBCR_WSEL                *((volatile unsigned int*)(0x42700030UL))\r
+#define bFM3_MFS0_I2C_IBCR_ACKE                *((volatile unsigned int*)(0x42700034UL))\r
+#define bFM3_MFS0_I2C_IBCR_ACT                 *((volatile unsigned int*)(0x42700038UL))\r
+#define bFM3_MFS0_I2C_IBCR_SCC                 *((volatile unsigned int*)(0x42700038UL))\r
+#define bFM3_MFS0_I2C_IBCR_MSS                 *((volatile unsigned int*)(0x4270003CUL))\r
+#define bFM3_MFS0_I2C_IBSR_BB                  *((volatile unsigned int*)(0x42700080UL))\r
+#define bFM3_MFS0_I2C_IBSR_SPC                 *((volatile unsigned int*)(0x42700084UL))\r
+#define bFM3_MFS0_I2C_IBSR_RSC                 *((volatile unsigned int*)(0x42700088UL))\r
+#define bFM3_MFS0_I2C_IBSR_AL                  *((volatile unsigned int*)(0x4270008CUL))\r
+#define bFM3_MFS0_I2C_IBSR_TRX                 *((volatile unsigned int*)(0x42700090UL))\r
+#define bFM3_MFS0_I2C_IBSR_RSA                 *((volatile unsigned int*)(0x42700094UL))\r
+#define bFM3_MFS0_I2C_IBSR_RACK                *((volatile unsigned int*)(0x42700098UL))\r
+#define bFM3_MFS0_I2C_IBSR_FBT                 *((volatile unsigned int*)(0x4270009CUL))\r
+#define bFM3_MFS0_I2C_SSR_TBI                  *((volatile unsigned int*)(0x427000A0UL))\r
+#define bFM3_MFS0_I2C_SSR_TDRE                 *((volatile unsigned int*)(0x427000A4UL))\r
+#define bFM3_MFS0_I2C_SSR_RDRF                 *((volatile unsigned int*)(0x427000A8UL))\r
+#define bFM3_MFS0_I2C_SSR_ORE                  *((volatile unsigned int*)(0x427000ACUL))\r
+#define bFM3_MFS0_I2C_SSR_TBIE                 *((volatile unsigned int*)(0x427000B0UL))\r
+#define bFM3_MFS0_I2C_SSR_DMA                  *((volatile unsigned int*)(0x427000B4UL))\r
+#define bFM3_MFS0_I2C_SSR_TSET                 *((volatile unsigned int*)(0x427000B8UL))\r
+#define bFM3_MFS0_I2C_SSR_REC                  *((volatile unsigned int*)(0x427000BCUL))\r
+#define bFM3_MFS0_I2C_ISBA_SA0                 *((volatile unsigned int*)(0x42700200UL))\r
+#define bFM3_MFS0_I2C_ISBA_SA1                 *((volatile unsigned int*)(0x42700204UL))\r
+#define bFM3_MFS0_I2C_ISBA_SA2                 *((volatile unsigned int*)(0x42700208UL))\r
+#define bFM3_MFS0_I2C_ISBA_SA3                 *((volatile unsigned int*)(0x4270020CUL))\r
+#define bFM3_MFS0_I2C_ISBA_SA4                 *((volatile unsigned int*)(0x42700210UL))\r
+#define bFM3_MFS0_I2C_ISBA_SA5                 *((volatile unsigned int*)(0x42700214UL))\r
+#define bFM3_MFS0_I2C_ISBA_SA6                 *((volatile unsigned int*)(0x42700218UL))\r
+#define bFM3_MFS0_I2C_ISBA_SAEN                *((volatile unsigned int*)(0x4270021CUL))\r
+#define bFM3_MFS0_I2C_ISMK_SM0                 *((volatile unsigned int*)(0x42700220UL))\r
+#define bFM3_MFS0_I2C_ISMK_SM1                 *((volatile unsigned int*)(0x42700224UL))\r
+#define bFM3_MFS0_I2C_ISMK_SM2                 *((volatile unsigned int*)(0x42700228UL))\r
+#define bFM3_MFS0_I2C_ISMK_SM3                 *((volatile unsigned int*)(0x4270022CUL))\r
+#define bFM3_MFS0_I2C_ISMK_SM4                 *((volatile unsigned int*)(0x42700230UL))\r
+#define bFM3_MFS0_I2C_ISMK_SM5                 *((volatile unsigned int*)(0x42700234UL))\r
+#define bFM3_MFS0_I2C_ISMK_SM6                 *((volatile unsigned int*)(0x42700238UL))\r
+#define bFM3_MFS0_I2C_ISMK_EN                  *((volatile unsigned int*)(0x4270023CUL))\r
+\r
+/* UART asynchronous channel 1 registers */\r
+#define bFM3_MFS1_UART_SMR_SOE                 *((volatile unsigned int*)(0x42702000UL))\r
+#define bFM3_MFS1_UART_SMR_BDS                 *((volatile unsigned int*)(0x42702008UL))\r
+#define bFM3_MFS1_UART_SMR_SBL                 *((volatile unsigned int*)(0x4270200CUL))\r
+#define bFM3_MFS1_UART_SMR_WUCR                *((volatile unsigned int*)(0x42702010UL))\r
+#define bFM3_MFS1_UART_SMR_MD0                 *((volatile unsigned int*)(0x42702014UL))\r
+#define bFM3_MFS1_UART_SMR_MD1                 *((volatile unsigned int*)(0x42702018UL))\r
+#define bFM3_MFS1_UART_SMR_MD2                 *((volatile unsigned int*)(0x4270201CUL))\r
+#define bFM3_MFS1_UART_SCR_TXE                 *((volatile unsigned int*)(0x42702020UL))\r
+#define bFM3_MFS1_UART_SCR_RXE                 *((volatile unsigned int*)(0x42702024UL))\r
+#define bFM3_MFS1_UART_SCR_TBIE                *((volatile unsigned int*)(0x42702028UL))\r
+#define bFM3_MFS1_UART_SCR_TIE                 *((volatile unsigned int*)(0x4270202CUL))\r
+#define bFM3_MFS1_UART_SCR_RIE                 *((volatile unsigned int*)(0x42702030UL))\r
+#define bFM3_MFS1_UART_SCR_UPCL                *((volatile unsigned int*)(0x4270203CUL))\r
+#define bFM3_MFS1_UART_ESCR_L0                 *((volatile unsigned int*)(0x42702080UL))\r
+#define bFM3_MFS1_UART_ESCR_L1                 *((volatile unsigned int*)(0x42702084UL))\r
+#define bFM3_MFS1_UART_ESCR_L2                 *((volatile unsigned int*)(0x42702088UL))\r
+#define bFM3_MFS1_UART_ESCR_P                  *((volatile unsigned int*)(0x4270208CUL))\r
+#define bFM3_MFS1_UART_ESCR_PEN                *((volatile unsigned int*)(0x42702090UL))\r
+#define bFM3_MFS1_UART_ESCR_INV                *((volatile unsigned int*)(0x42702094UL))\r
+#define bFM3_MFS1_UART_ESCR_ESBL               *((volatile unsigned int*)(0x42702098UL))\r
+#define bFM3_MFS1_UART_ESCR_FLWEN              *((volatile unsigned int*)(0x4270209CUL))\r
+#define bFM3_MFS1_UART_SSR_TBI                 *((volatile unsigned int*)(0x427020A0UL))\r
+#define bFM3_MFS1_UART_SSR_TDRE                *((volatile unsigned int*)(0x427020A4UL))\r
+#define bFM3_MFS1_UART_SSR_RDRF                *((volatile unsigned int*)(0x427020A8UL))\r
+#define bFM3_MFS1_UART_SSR_ORE                 *((volatile unsigned int*)(0x427020ACUL))\r
+#define bFM3_MFS1_UART_SSR_FRE                 *((volatile unsigned int*)(0x427020B0UL))\r
+#define bFM3_MFS1_UART_SSR_PE                  *((volatile unsigned int*)(0x427020B4UL))\r
+#define bFM3_MFS1_UART_SSR_REC                 *((volatile unsigned int*)(0x427020BCUL))\r
+#define bFM3_MFS1_UART_RDR_AD                  *((volatile unsigned int*)(0x42702120UL))\r
+#define bFM3_MFS1_UART_TDR_AD                  *((volatile unsigned int*)(0x42702120UL))\r
+#define bFM3_MFS1_UART_BGR_EXT                 *((volatile unsigned int*)(0x427021BCUL))\r
+#define bFM3_MFS1_UART_BGR1_EXT                *((volatile unsigned int*)(0x427021BCUL))\r
+\r
+/* UART synchronous channel 1 registers */\r
+#define bFM3_MFS1_CSIO_SMR_SOE                 *((volatile unsigned int*)(0x42702000UL))\r
+#define bFM3_MFS1_CSIO_SMR_SCKE                *((volatile unsigned int*)(0x42702004UL))\r
+#define bFM3_MFS1_CSIO_SMR_BDS                 *((volatile unsigned int*)(0x42702008UL))\r
+#define bFM3_MFS1_CSIO_SMR_SCINV               *((volatile unsigned int*)(0x4270200CUL))\r
+#define bFM3_MFS1_CSIO_SMR_WUCR                *((volatile unsigned int*)(0x42702010UL))\r
+#define bFM3_MFS1_CSIO_SMR_MD0                 *((volatile unsigned int*)(0x42702014UL))\r
+#define bFM3_MFS1_CSIO_SMR_MD1                 *((volatile unsigned int*)(0x42702018UL))\r
+#define bFM3_MFS1_CSIO_SMR_MD2                 *((volatile unsigned int*)(0x4270201CUL))\r
+#define bFM3_MFS1_CSIO_SCR_TXE                 *((volatile unsigned int*)(0x42702020UL))\r
+#define bFM3_MFS1_CSIO_SCR_RXE                 *((volatile unsigned int*)(0x42702024UL))\r
+#define bFM3_MFS1_CSIO_SCR_TBIE                *((volatile unsigned int*)(0x42702028UL))\r
+#define bFM3_MFS1_CSIO_SCR_TIE                 *((volatile unsigned int*)(0x4270202CUL))\r
+#define bFM3_MFS1_CSIO_SCR_RIE                 *((volatile unsigned int*)(0x42702030UL))\r
+#define bFM3_MFS1_CSIO_SCR_SPI                 *((volatile unsigned int*)(0x42702034UL))\r
+#define bFM3_MFS1_CSIO_SCR_MS                  *((volatile unsigned int*)(0x42702038UL))\r
+#define bFM3_MFS1_CSIO_SCR_UPCL                *((volatile unsigned int*)(0x4270203CUL))\r
+#define bFM3_MFS1_CSIO_ESCR_L0                 *((volatile unsigned int*)(0x42702080UL))\r
+#define bFM3_MFS1_CSIO_ESCR_L1                 *((volatile unsigned int*)(0x42702084UL))\r
+#define bFM3_MFS1_CSIO_ESCR_L2                 *((volatile unsigned int*)(0x42702088UL))\r
+#define bFM3_MFS1_CSIO_ESCR_WT0                *((volatile unsigned int*)(0x4270208CUL))\r
+#define bFM3_MFS1_CSIO_ESCR_WT1                *((volatile unsigned int*)(0x42702090UL))\r
+#define bFM3_MFS1_CSIO_ESCR_SOP                *((volatile unsigned int*)(0x4270209CUL))\r
+#define bFM3_MFS1_CSIO_SSR_TBI                 *((volatile unsigned int*)(0x427020A0UL))\r
+#define bFM3_MFS1_CSIO_SSR_TDRE                *((volatile unsigned int*)(0x427020A4UL))\r
+#define bFM3_MFS1_CSIO_SSR_RDRF                *((volatile unsigned int*)(0x427020A8UL))\r
+#define bFM3_MFS1_CSIO_SSR_ORE                 *((volatile unsigned int*)(0x427020ACUL))\r
+#define bFM3_MFS1_CSIO_SSR_REC                 *((volatile unsigned int*)(0x427020BCUL))\r
+\r
+/* UART LIN channel 1 registers */\r
+#define bFM3_MFS1_LIN_SMR_SOE                  *((volatile unsigned int*)(0x42702000UL))\r
+#define bFM3_MFS1_LIN_SMR_SBL                  *((volatile unsigned int*)(0x4270200CUL))\r
+#define bFM3_MFS1_LIN_SMR_WUCR                 *((volatile unsigned int*)(0x42702010UL))\r
+#define bFM3_MFS1_LIN_SMR_MD0                  *((volatile unsigned int*)(0x42702014UL))\r
+#define bFM3_MFS1_LIN_SMR_MD1                  *((volatile unsigned int*)(0x42702018UL))\r
+#define bFM3_MFS1_LIN_SMR_MD2                  *((volatile unsigned int*)(0x4270201CUL))\r
+#define bFM3_MFS1_LIN_SCR_TXE                  *((volatile unsigned int*)(0x42702020UL))\r
+#define bFM3_MFS1_LIN_SCR_RXE                  *((volatile unsigned int*)(0x42702024UL))\r
+#define bFM3_MFS1_LIN_SCR_TBIE                 *((volatile unsigned int*)(0x42702028UL))\r
+#define bFM3_MFS1_LIN_SCR_TIE                  *((volatile unsigned int*)(0x4270202CUL))\r
+#define bFM3_MFS1_LIN_SCR_RIE                  *((volatile unsigned int*)(0x42702030UL))\r
+#define bFM3_MFS1_LIN_SCR_LBR                  *((volatile unsigned int*)(0x42702034UL))\r
+#define bFM3_MFS1_LIN_SCR_MS                   *((volatile unsigned int*)(0x42702038UL))\r
+#define bFM3_MFS1_LIN_SCR_UPCL                 *((volatile unsigned int*)(0x4270203CUL))\r
+#define bFM3_MFS1_LIN_ESCR_DEL0                *((volatile unsigned int*)(0x42702080UL))\r
+#define bFM3_MFS1_LIN_ESCR_DEL1                *((volatile unsigned int*)(0x42702084UL))\r
+#define bFM3_MFS1_LIN_ESCR_LBL0                *((volatile unsigned int*)(0x42702088UL))\r
+#define bFM3_MFS1_LIN_ESCR_LBL1                *((volatile unsigned int*)(0x4270208CUL))\r
+#define bFM3_MFS1_LIN_ESCR_LBIE                *((volatile unsigned int*)(0x42702090UL))\r
+#define bFM3_MFS1_LIN_ESCR_ESBL                *((volatile unsigned int*)(0x42702098UL))\r
+#define bFM3_MFS1_LIN_SSR_TBI                  *((volatile unsigned int*)(0x427020A0UL))\r
+#define bFM3_MFS1_LIN_SSR_TDRE                 *((volatile unsigned int*)(0x427020A4UL))\r
+#define bFM3_MFS1_LIN_SSR_RDRF                 *((volatile unsigned int*)(0x427020A8UL))\r
+#define bFM3_MFS1_LIN_SSR_ORE                  *((volatile unsigned int*)(0x427020ACUL))\r
+#define bFM3_MFS1_LIN_SSR_FRE                  *((volatile unsigned int*)(0x427020B0UL))\r
+#define bFM3_MFS1_LIN_SSR_LBD                  *((volatile unsigned int*)(0x427020B4UL))\r
+#define bFM3_MFS1_LIN_SSR_REC                  *((volatile unsigned int*)(0x427020BCUL))\r
+#define bFM3_MFS1_LIN_BGR_EXT                  *((volatile unsigned int*)(0x427021BCUL))\r
+#define bFM3_MFS1_LIN_BGR1_EXT                 *((volatile unsigned int*)(0x427021BCUL))\r
+\r
+/* I2C channel 1 registers */\r
+#define bFM3_MFS1_I2C_SMR_ITST0                *((volatile unsigned int*)(0x42702000UL))\r
+#define bFM3_MFS1_I2C_SMR_ITST1                *((volatile unsigned int*)(0x42702004UL))\r
+#define bFM3_MFS1_I2C_SMR_TIE                  *((volatile unsigned int*)(0x42702008UL))\r
+#define bFM3_MFS1_I2C_SMR_RIE                  *((volatile unsigned int*)(0x4270200CUL))\r
+#define bFM3_MFS1_I2C_SMR_WUCR                 *((volatile unsigned int*)(0x42702010UL))\r
+#define bFM3_MFS1_I2C_SMR_MD0                  *((volatile unsigned int*)(0x42702014UL))\r
+#define bFM3_MFS1_I2C_SMR_MD1                  *((volatile unsigned int*)(0x42702018UL))\r
+#define bFM3_MFS1_I2C_SMR_MD2                  *((volatile unsigned int*)(0x4270201CUL))\r
+#define bFM3_MFS1_I2C_IBCR_INT                 *((volatile unsigned int*)(0x42702020UL))\r
+#define bFM3_MFS1_I2C_IBCR_BER                 *((volatile unsigned int*)(0x42702024UL))\r
+#define bFM3_MFS1_I2C_IBCR_INTE                *((volatile unsigned int*)(0x42702028UL))\r
+#define bFM3_MFS1_I2C_IBCR_CNDE                *((volatile unsigned int*)(0x4270202CUL))\r
+#define bFM3_MFS1_I2C_IBCR_WSEL                *((volatile unsigned int*)(0x42702030UL))\r
+#define bFM3_MFS1_I2C_IBCR_ACKE                *((volatile unsigned int*)(0x42702034UL))\r
+#define bFM3_MFS1_I2C_IBCR_ACT                 *((volatile unsigned int*)(0x42702038UL))\r
+#define bFM3_MFS1_I2C_IBCR_SCC                 *((volatile unsigned int*)(0x42702038UL))\r
+#define bFM3_MFS1_I2C_IBCR_MSS                 *((volatile unsigned int*)(0x4270203CUL))\r
+#define bFM3_MFS1_I2C_IBSR_BB                  *((volatile unsigned int*)(0x42702080UL))\r
+#define bFM3_MFS1_I2C_IBSR_SPC                 *((volatile unsigned int*)(0x42702084UL))\r
+#define bFM3_MFS1_I2C_IBSR_RSC                 *((volatile unsigned int*)(0x42702088UL))\r
+#define bFM3_MFS1_I2C_IBSR_AL                  *((volatile unsigned int*)(0x4270208CUL))\r
+#define bFM3_MFS1_I2C_IBSR_TRX                 *((volatile unsigned int*)(0x42702090UL))\r
+#define bFM3_MFS1_I2C_IBSR_RSA                 *((volatile unsigned int*)(0x42702094UL))\r
+#define bFM3_MFS1_I2C_IBSR_RACK                *((volatile unsigned int*)(0x42702098UL))\r
+#define bFM3_MFS1_I2C_IBSR_FBT                 *((volatile unsigned int*)(0x4270209CUL))\r
+#define bFM3_MFS1_I2C_SSR_TBI                  *((volatile unsigned int*)(0x427020A0UL))\r
+#define bFM3_MFS1_I2C_SSR_TDRE                 *((volatile unsigned int*)(0x427020A4UL))\r
+#define bFM3_MFS1_I2C_SSR_RDRF                 *((volatile unsigned int*)(0x427020A8UL))\r
+#define bFM3_MFS1_I2C_SSR_ORE                  *((volatile unsigned int*)(0x427020ACUL))\r
+#define bFM3_MFS1_I2C_SSR_TBIE                 *((volatile unsigned int*)(0x427020B0UL))\r
+#define bFM3_MFS1_I2C_SSR_DMA                  *((volatile unsigned int*)(0x427020B4UL))\r
+#define bFM3_MFS1_I2C_SSR_TSET                 *((volatile unsigned int*)(0x427020B8UL))\r
+#define bFM3_MFS1_I2C_SSR_REC                  *((volatile unsigned int*)(0x427020BCUL))\r
+#define bFM3_MFS1_I2C_ISBA_SA0                 *((volatile unsigned int*)(0x42702200UL))\r
+#define bFM3_MFS1_I2C_ISBA_SA1                 *((volatile unsigned int*)(0x42702204UL))\r
+#define bFM3_MFS1_I2C_ISBA_SA2                 *((volatile unsigned int*)(0x42702208UL))\r
+#define bFM3_MFS1_I2C_ISBA_SA3                 *((volatile unsigned int*)(0x4270220CUL))\r
+#define bFM3_MFS1_I2C_ISBA_SA4                 *((volatile unsigned int*)(0x42702210UL))\r
+#define bFM3_MFS1_I2C_ISBA_SA5                 *((volatile unsigned int*)(0x42702214UL))\r
+#define bFM3_MFS1_I2C_ISBA_SA6                 *((volatile unsigned int*)(0x42702218UL))\r
+#define bFM3_MFS1_I2C_ISBA_SAEN                *((volatile unsigned int*)(0x4270221CUL))\r
+#define bFM3_MFS1_I2C_ISMK_SM0                 *((volatile unsigned int*)(0x42702220UL))\r
+#define bFM3_MFS1_I2C_ISMK_SM1                 *((volatile unsigned int*)(0x42702224UL))\r
+#define bFM3_MFS1_I2C_ISMK_SM2                 *((volatile unsigned int*)(0x42702228UL))\r
+#define bFM3_MFS1_I2C_ISMK_SM3                 *((volatile unsigned int*)(0x4270222CUL))\r
+#define bFM3_MFS1_I2C_ISMK_SM4                 *((volatile unsigned int*)(0x42702230UL))\r
+#define bFM3_MFS1_I2C_ISMK_SM5                 *((volatile unsigned int*)(0x42702234UL))\r
+#define bFM3_MFS1_I2C_ISMK_SM6                 *((volatile unsigned int*)(0x42702238UL))\r
+#define bFM3_MFS1_I2C_ISMK_EN                  *((volatile unsigned int*)(0x4270223CUL))\r
+\r
+/* UART asynchronous channel 2 registers */\r
+#define bFM3_MFS2_UART_SMR_SOE                 *((volatile unsigned int*)(0x42704000UL))\r
+#define bFM3_MFS2_UART_SMR_BDS                 *((volatile unsigned int*)(0x42704008UL))\r
+#define bFM3_MFS2_UART_SMR_SBL                 *((volatile unsigned int*)(0x4270400CUL))\r
+#define bFM3_MFS2_UART_SMR_WUCR                *((volatile unsigned int*)(0x42704010UL))\r
+#define bFM3_MFS2_UART_SMR_MD0                 *((volatile unsigned int*)(0x42704014UL))\r
+#define bFM3_MFS2_UART_SMR_MD1                 *((volatile unsigned int*)(0x42704018UL))\r
+#define bFM3_MFS2_UART_SMR_MD2                 *((volatile unsigned int*)(0x4270401CUL))\r
+#define bFM3_MFS2_UART_SCR_TXE                 *((volatile unsigned int*)(0x42704020UL))\r
+#define bFM3_MFS2_UART_SCR_RXE                 *((volatile unsigned int*)(0x42704024UL))\r
+#define bFM3_MFS2_UART_SCR_TBIE                *((volatile unsigned int*)(0x42704028UL))\r
+#define bFM3_MFS2_UART_SCR_TIE                 *((volatile unsigned int*)(0x4270402CUL))\r
+#define bFM3_MFS2_UART_SCR_RIE                 *((volatile unsigned int*)(0x42704030UL))\r
+#define bFM3_MFS2_UART_SCR_UPCL                *((volatile unsigned int*)(0x4270403CUL))\r
+#define bFM3_MFS2_UART_ESCR_L0                 *((volatile unsigned int*)(0x42704080UL))\r
+#define bFM3_MFS2_UART_ESCR_L1                 *((volatile unsigned int*)(0x42704084UL))\r
+#define bFM3_MFS2_UART_ESCR_L2                 *((volatile unsigned int*)(0x42704088UL))\r
+#define bFM3_MFS2_UART_ESCR_P                  *((volatile unsigned int*)(0x4270408CUL))\r
+#define bFM3_MFS2_UART_ESCR_PEN                *((volatile unsigned int*)(0x42704090UL))\r
+#define bFM3_MFS2_UART_ESCR_INV                *((volatile unsigned int*)(0x42704094UL))\r
+#define bFM3_MFS2_UART_ESCR_ESBL               *((volatile unsigned int*)(0x42704098UL))\r
+#define bFM3_MFS2_UART_ESCR_FLWEN              *((volatile unsigned int*)(0x4270409CUL))\r
+#define bFM3_MFS2_UART_SSR_TBI                 *((volatile unsigned int*)(0x427040A0UL))\r
+#define bFM3_MFS2_UART_SSR_TDRE                *((volatile unsigned int*)(0x427040A4UL))\r
+#define bFM3_MFS2_UART_SSR_RDRF                *((volatile unsigned int*)(0x427040A8UL))\r
+#define bFM3_MFS2_UART_SSR_ORE                 *((volatile unsigned int*)(0x427040ACUL))\r
+#define bFM3_MFS2_UART_SSR_FRE                 *((volatile unsigned int*)(0x427040B0UL))\r
+#define bFM3_MFS2_UART_SSR_PE                  *((volatile unsigned int*)(0x427040B4UL))\r
+#define bFM3_MFS2_UART_SSR_REC                 *((volatile unsigned int*)(0x427040BCUL))\r
+#define bFM3_MFS2_UART_RDR_AD                  *((volatile unsigned int*)(0x42704120UL))\r
+#define bFM3_MFS2_UART_TDR_AD                  *((volatile unsigned int*)(0x42704120UL))\r
+#define bFM3_MFS2_UART_BGR_EXT                 *((volatile unsigned int*)(0x427041BCUL))\r
+#define bFM3_MFS2_UART_BGR1_EXT                *((volatile unsigned int*)(0x427041BCUL))\r
+\r
+/* UART synchronous channel 2 registers */\r
+#define bFM3_MFS2_CSIO_SMR_SOE                 *((volatile unsigned int*)(0x42704000UL))\r
+#define bFM3_MFS2_CSIO_SMR_SCKE                *((volatile unsigned int*)(0x42704004UL))\r
+#define bFM3_MFS2_CSIO_SMR_BDS                 *((volatile unsigned int*)(0x42704008UL))\r
+#define bFM3_MFS2_CSIO_SMR_SCINV               *((volatile unsigned int*)(0x4270400CUL))\r
+#define bFM3_MFS2_CSIO_SMR_WUCR                *((volatile unsigned int*)(0x42704010UL))\r
+#define bFM3_MFS2_CSIO_SMR_MD0                 *((volatile unsigned int*)(0x42704014UL))\r
+#define bFM3_MFS2_CSIO_SMR_MD1                 *((volatile unsigned int*)(0x42704018UL))\r
+#define bFM3_MFS2_CSIO_SMR_MD2                 *((volatile unsigned int*)(0x4270401CUL))\r
+#define bFM3_MFS2_CSIO_SCR_TXE                 *((volatile unsigned int*)(0x42704020UL))\r
+#define bFM3_MFS2_CSIO_SCR_RXE                 *((volatile unsigned int*)(0x42704024UL))\r
+#define bFM3_MFS2_CSIO_SCR_TBIE                *((volatile unsigned int*)(0x42704028UL))\r
+#define bFM3_MFS2_CSIO_SCR_TIE                 *((volatile unsigned int*)(0x4270402CUL))\r
+#define bFM3_MFS2_CSIO_SCR_RIE                 *((volatile unsigned int*)(0x42704030UL))\r
+#define bFM3_MFS2_CSIO_SCR_SPI                 *((volatile unsigned int*)(0x42704034UL))\r
+#define bFM3_MFS2_CSIO_SCR_MS                  *((volatile unsigned int*)(0x42704038UL))\r
+#define bFM3_MFS2_CSIO_SCR_UPCL                *((volatile unsigned int*)(0x4270403CUL))\r
+#define bFM3_MFS2_CSIO_ESCR_L0                 *((volatile unsigned int*)(0x42704080UL))\r
+#define bFM3_MFS2_CSIO_ESCR_L1                 *((volatile unsigned int*)(0x42704084UL))\r
+#define bFM3_MFS2_CSIO_ESCR_L2                 *((volatile unsigned int*)(0x42704088UL))\r
+#define bFM3_MFS2_CSIO_ESCR_WT0                *((volatile unsigned int*)(0x4270408CUL))\r
+#define bFM3_MFS2_CSIO_ESCR_WT1                *((volatile unsigned int*)(0x42704090UL))\r
+#define bFM3_MFS2_CSIO_ESCR_SOP                *((volatile unsigned int*)(0x4270409CUL))\r
+#define bFM3_MFS2_CSIO_SSR_TBI                 *((volatile unsigned int*)(0x427040A0UL))\r
+#define bFM3_MFS2_CSIO_SSR_TDRE                *((volatile unsigned int*)(0x427040A4UL))\r
+#define bFM3_MFS2_CSIO_SSR_RDRF                *((volatile unsigned int*)(0x427040A8UL))\r
+#define bFM3_MFS2_CSIO_SSR_ORE                 *((volatile unsigned int*)(0x427040ACUL))\r
+#define bFM3_MFS2_CSIO_SSR_REC                 *((volatile unsigned int*)(0x427040BCUL))\r
+\r
+/* UART LIN channel 2 registers */\r
+#define bFM3_MFS2_LIN_SMR_SOE                  *((volatile unsigned int*)(0x42704000UL))\r
+#define bFM3_MFS2_LIN_SMR_SBL                  *((volatile unsigned int*)(0x4270400CUL))\r
+#define bFM3_MFS2_LIN_SMR_WUCR                 *((volatile unsigned int*)(0x42704010UL))\r
+#define bFM3_MFS2_LIN_SMR_MD0                  *((volatile unsigned int*)(0x42704014UL))\r
+#define bFM3_MFS2_LIN_SMR_MD1                  *((volatile unsigned int*)(0x42704018UL))\r
+#define bFM3_MFS2_LIN_SMR_MD2                  *((volatile unsigned int*)(0x4270401CUL))\r
+#define bFM3_MFS2_LIN_SCR_TXE                  *((volatile unsigned int*)(0x42704020UL))\r
+#define bFM3_MFS2_LIN_SCR_RXE                  *((volatile unsigned int*)(0x42704024UL))\r
+#define bFM3_MFS2_LIN_SCR_TBIE                 *((volatile unsigned int*)(0x42704028UL))\r
+#define bFM3_MFS2_LIN_SCR_TIE                  *((volatile unsigned int*)(0x4270402CUL))\r
+#define bFM3_MFS2_LIN_SCR_RIE                  *((volatile unsigned int*)(0x42704030UL))\r
+#define bFM3_MFS2_LIN_SCR_LBR                  *((volatile unsigned int*)(0x42704034UL))\r
+#define bFM3_MFS2_LIN_SCR_MS                   *((volatile unsigned int*)(0x42704038UL))\r
+#define bFM3_MFS2_LIN_SCR_UPCL                 *((volatile unsigned int*)(0x4270403CUL))\r
+#define bFM3_MFS2_LIN_ESCR_DEL0                *((volatile unsigned int*)(0x42704080UL))\r
+#define bFM3_MFS2_LIN_ESCR_DEL1                *((volatile unsigned int*)(0x42704084UL))\r
+#define bFM3_MFS2_LIN_ESCR_LBL0                *((volatile unsigned int*)(0x42704088UL))\r
+#define bFM3_MFS2_LIN_ESCR_LBL1                *((volatile unsigned int*)(0x4270408CUL))\r
+#define bFM3_MFS2_LIN_ESCR_LBIE                *((volatile unsigned int*)(0x42704090UL))\r
+#define bFM3_MFS2_LIN_ESCR_ESBL                *((volatile unsigned int*)(0x42704098UL))\r
+#define bFM3_MFS2_LIN_SSR_TBI                  *((volatile unsigned int*)(0x427040A0UL))\r
+#define bFM3_MFS2_LIN_SSR_TDRE                 *((volatile unsigned int*)(0x427040A4UL))\r
+#define bFM3_MFS2_LIN_SSR_RDRF                 *((volatile unsigned int*)(0x427040A8UL))\r
+#define bFM3_MFS2_LIN_SSR_ORE                  *((volatile unsigned int*)(0x427040ACUL))\r
+#define bFM3_MFS2_LIN_SSR_FRE                  *((volatile unsigned int*)(0x427040B0UL))\r
+#define bFM3_MFS2_LIN_SSR_LBD                  *((volatile unsigned int*)(0x427040B4UL))\r
+#define bFM3_MFS2_LIN_SSR_REC                  *((volatile unsigned int*)(0x427040BCUL))\r
+#define bFM3_MFS2_LIN_BGR_EXT                  *((volatile unsigned int*)(0x427041BCUL))\r
+#define bFM3_MFS2_LIN_BGR1_EXT                 *((volatile unsigned int*)(0x427041BCUL))\r
+\r
+/* I2C channel 2 registers */\r
+#define bFM3_MFS2_I2C_SMR_ITST0                *((volatile unsigned int*)(0x42704000UL))\r
+#define bFM3_MFS2_I2C_SMR_ITST1                *((volatile unsigned int*)(0x42704004UL))\r
+#define bFM3_MFS2_I2C_SMR_TIE                  *((volatile unsigned int*)(0x42704008UL))\r
+#define bFM3_MFS2_I2C_SMR_RIE                  *((volatile unsigned int*)(0x4270400CUL))\r
+#define bFM3_MFS2_I2C_SMR_WUCR                 *((volatile unsigned int*)(0x42704010UL))\r
+#define bFM3_MFS2_I2C_SMR_MD0                  *((volatile unsigned int*)(0x42704014UL))\r
+#define bFM3_MFS2_I2C_SMR_MD1                  *((volatile unsigned int*)(0x42704018UL))\r
+#define bFM3_MFS2_I2C_SMR_MD2                  *((volatile unsigned int*)(0x4270401CUL))\r
+#define bFM3_MFS2_I2C_IBCR_INT                 *((volatile unsigned int*)(0x42704020UL))\r
+#define bFM3_MFS2_I2C_IBCR_BER                 *((volatile unsigned int*)(0x42704024UL))\r
+#define bFM3_MFS2_I2C_IBCR_INTE                *((volatile unsigned int*)(0x42704028UL))\r
+#define bFM3_MFS2_I2C_IBCR_CNDE                *((volatile unsigned int*)(0x4270402CUL))\r
+#define bFM3_MFS2_I2C_IBCR_WSEL                *((volatile unsigned int*)(0x42704030UL))\r
+#define bFM3_MFS2_I2C_IBCR_ACKE                *((volatile unsigned int*)(0x42704034UL))\r
+#define bFM3_MFS2_I2C_IBCR_ACT                 *((volatile unsigned int*)(0x42704038UL))\r
+#define bFM3_MFS2_I2C_IBCR_SCC                 *((volatile unsigned int*)(0x42704038UL))\r
+#define bFM3_MFS2_I2C_IBCR_MSS                 *((volatile unsigned int*)(0x4270403CUL))\r
+#define bFM3_MFS2_I2C_IBSR_BB                  *((volatile unsigned int*)(0x42704080UL))\r
+#define bFM3_MFS2_I2C_IBSR_SPC                 *((volatile unsigned int*)(0x42704084UL))\r
+#define bFM3_MFS2_I2C_IBSR_RSC                 *((volatile unsigned int*)(0x42704088UL))\r
+#define bFM3_MFS2_I2C_IBSR_AL                  *((volatile unsigned int*)(0x4270408CUL))\r
+#define bFM3_MFS2_I2C_IBSR_TRX                 *((volatile unsigned int*)(0x42704090UL))\r
+#define bFM3_MFS2_I2C_IBSR_RSA                 *((volatile unsigned int*)(0x42704094UL))\r
+#define bFM3_MFS2_I2C_IBSR_RACK                *((volatile unsigned int*)(0x42704098UL))\r
+#define bFM3_MFS2_I2C_IBSR_FBT                 *((volatile unsigned int*)(0x4270409CUL))\r
+#define bFM3_MFS2_I2C_SSR_TBI                  *((volatile unsigned int*)(0x427040A0UL))\r
+#define bFM3_MFS2_I2C_SSR_TDRE                 *((volatile unsigned int*)(0x427040A4UL))\r
+#define bFM3_MFS2_I2C_SSR_RDRF                 *((volatile unsigned int*)(0x427040A8UL))\r
+#define bFM3_MFS2_I2C_SSR_ORE                  *((volatile unsigned int*)(0x427040ACUL))\r
+#define bFM3_MFS2_I2C_SSR_TBIE                 *((volatile unsigned int*)(0x427040B0UL))\r
+#define bFM3_MFS2_I2C_SSR_DMA                  *((volatile unsigned int*)(0x427040B4UL))\r
+#define bFM3_MFS2_I2C_SSR_TSET                 *((volatile unsigned int*)(0x427040B8UL))\r
+#define bFM3_MFS2_I2C_SSR_REC                  *((volatile unsigned int*)(0x427040BCUL))\r
+#define bFM3_MFS2_I2C_ISBA_SA0                 *((volatile unsigned int*)(0x42704200UL))\r
+#define bFM3_MFS2_I2C_ISBA_SA1                 *((volatile unsigned int*)(0x42704204UL))\r
+#define bFM3_MFS2_I2C_ISBA_SA2                 *((volatile unsigned int*)(0x42704208UL))\r
+#define bFM3_MFS2_I2C_ISBA_SA3                 *((volatile unsigned int*)(0x4270420CUL))\r
+#define bFM3_MFS2_I2C_ISBA_SA4                 *((volatile unsigned int*)(0x42704210UL))\r
+#define bFM3_MFS2_I2C_ISBA_SA5                 *((volatile unsigned int*)(0x42704214UL))\r
+#define bFM3_MFS2_I2C_ISBA_SA6                 *((volatile unsigned int*)(0x42704218UL))\r
+#define bFM3_MFS2_I2C_ISBA_SAEN                *((volatile unsigned int*)(0x4270421CUL))\r
+#define bFM3_MFS2_I2C_ISMK_SM0                 *((volatile unsigned int*)(0x42704220UL))\r
+#define bFM3_MFS2_I2C_ISMK_SM1                 *((volatile unsigned int*)(0x42704224UL))\r
+#define bFM3_MFS2_I2C_ISMK_SM2                 *((volatile unsigned int*)(0x42704228UL))\r
+#define bFM3_MFS2_I2C_ISMK_SM3                 *((volatile unsigned int*)(0x4270422CUL))\r
+#define bFM3_MFS2_I2C_ISMK_SM4                 *((volatile unsigned int*)(0x42704230UL))\r
+#define bFM3_MFS2_I2C_ISMK_SM5                 *((volatile unsigned int*)(0x42704234UL))\r
+#define bFM3_MFS2_I2C_ISMK_SM6                 *((volatile unsigned int*)(0x42704238UL))\r
+#define bFM3_MFS2_I2C_ISMK_EN                  *((volatile unsigned int*)(0x4270423CUL))\r
+\r
+/* UART asynchronous channel 3 registers */\r
+#define bFM3_MFS3_UART_SMR_SOE                 *((volatile unsigned int*)(0x42706000UL))\r
+#define bFM3_MFS3_UART_SMR_BDS                 *((volatile unsigned int*)(0x42706008UL))\r
+#define bFM3_MFS3_UART_SMR_SBL                 *((volatile unsigned int*)(0x4270600CUL))\r
+#define bFM3_MFS3_UART_SMR_WUCR                *((volatile unsigned int*)(0x42706010UL))\r
+#define bFM3_MFS3_UART_SMR_MD0                 *((volatile unsigned int*)(0x42706014UL))\r
+#define bFM3_MFS3_UART_SMR_MD1                 *((volatile unsigned int*)(0x42706018UL))\r
+#define bFM3_MFS3_UART_SMR_MD2                 *((volatile unsigned int*)(0x4270601CUL))\r
+#define bFM3_MFS3_UART_SCR_TXE                 *((volatile unsigned int*)(0x42706020UL))\r
+#define bFM3_MFS3_UART_SCR_RXE                 *((volatile unsigned int*)(0x42706024UL))\r
+#define bFM3_MFS3_UART_SCR_TBIE                *((volatile unsigned int*)(0x42706028UL))\r
+#define bFM3_MFS3_UART_SCR_TIE                 *((volatile unsigned int*)(0x4270602CUL))\r
+#define bFM3_MFS3_UART_SCR_RIE                 *((volatile unsigned int*)(0x42706030UL))\r
+#define bFM3_MFS3_UART_SCR_UPCL                *((volatile unsigned int*)(0x4270603CUL))\r
+#define bFM3_MFS3_UART_ESCR_L0                 *((volatile unsigned int*)(0x42706080UL))\r
+#define bFM3_MFS3_UART_ESCR_L1                 *((volatile unsigned int*)(0x42706084UL))\r
+#define bFM3_MFS3_UART_ESCR_L2                 *((volatile unsigned int*)(0x42706088UL))\r
+#define bFM3_MFS3_UART_ESCR_P                  *((volatile unsigned int*)(0x4270608CUL))\r
+#define bFM3_MFS3_UART_ESCR_PEN                *((volatile unsigned int*)(0x42706090UL))\r
+#define bFM3_MFS3_UART_ESCR_INV                *((volatile unsigned int*)(0x42706094UL))\r
+#define bFM3_MFS3_UART_ESCR_ESBL               *((volatile unsigned int*)(0x42706098UL))\r
+#define bFM3_MFS3_UART_ESCR_FLWEN              *((volatile unsigned int*)(0x4270609CUL))\r
+#define bFM3_MFS3_UART_SSR_TBI                 *((volatile unsigned int*)(0x427060A0UL))\r
+#define bFM3_MFS3_UART_SSR_TDRE                *((volatile unsigned int*)(0x427060A4UL))\r
+#define bFM3_MFS3_UART_SSR_RDRF                *((volatile unsigned int*)(0x427060A8UL))\r
+#define bFM3_MFS3_UART_SSR_ORE                 *((volatile unsigned int*)(0x427060ACUL))\r
+#define bFM3_MFS3_UART_SSR_FRE                 *((volatile unsigned int*)(0x427060B0UL))\r
+#define bFM3_MFS3_UART_SSR_PE                  *((volatile unsigned int*)(0x427060B4UL))\r
+#define bFM3_MFS3_UART_SSR_REC                 *((volatile unsigned int*)(0x427060BCUL))\r
+#define bFM3_MFS3_UART_RDR_AD                  *((volatile unsigned int*)(0x42706120UL))\r
+#define bFM3_MFS3_UART_TDR_AD                  *((volatile unsigned int*)(0x42706120UL))\r
+#define bFM3_MFS3_UART_BGR_EXT                 *((volatile unsigned int*)(0x427061BCUL))\r
+#define bFM3_MFS3_UART_BGR1_EXT                *((volatile unsigned int*)(0x427061BCUL))\r
+\r
+/* UART synchronous channel 3 registers */\r
+#define bFM3_MFS3_CSIO_SMR_SOE                 *((volatile unsigned int*)(0x42706000UL))\r
+#define bFM3_MFS3_CSIO_SMR_SCKE                *((volatile unsigned int*)(0x42706004UL))\r
+#define bFM3_MFS3_CSIO_SMR_BDS                 *((volatile unsigned int*)(0x42706008UL))\r
+#define bFM3_MFS3_CSIO_SMR_SCINV               *((volatile unsigned int*)(0x4270600CUL))\r
+#define bFM3_MFS3_CSIO_SMR_WUCR                *((volatile unsigned int*)(0x42706010UL))\r
+#define bFM3_MFS3_CSIO_SMR_MD0                 *((volatile unsigned int*)(0x42706014UL))\r
+#define bFM3_MFS3_CSIO_SMR_MD1                 *((volatile unsigned int*)(0x42706018UL))\r
+#define bFM3_MFS3_CSIO_SMR_MD2                 *((volatile unsigned int*)(0x4270601CUL))\r
+#define bFM3_MFS3_CSIO_SCR_TXE                 *((volatile unsigned int*)(0x42706020UL))\r
+#define bFM3_MFS3_CSIO_SCR_RXE                 *((volatile unsigned int*)(0x42706024UL))\r
+#define bFM3_MFS3_CSIO_SCR_TBIE                *((volatile unsigned int*)(0x42706028UL))\r
+#define bFM3_MFS3_CSIO_SCR_TIE                 *((volatile unsigned int*)(0x4270602CUL))\r
+#define bFM3_MFS3_CSIO_SCR_RIE                 *((volatile unsigned int*)(0x42706030UL))\r
+#define bFM3_MFS3_CSIO_SCR_SPI                 *((volatile unsigned int*)(0x42706034UL))\r
+#define bFM3_MFS3_CSIO_SCR_MS                  *((volatile unsigned int*)(0x42706038UL))\r
+#define bFM3_MFS3_CSIO_SCR_UPCL                *((volatile unsigned int*)(0x4270603CUL))\r
+#define bFM3_MFS3_CSIO_ESCR_L0                 *((volatile unsigned int*)(0x42706080UL))\r
+#define bFM3_MFS3_CSIO_ESCR_L1                 *((volatile unsigned int*)(0x42706084UL))\r
+#define bFM3_MFS3_CSIO_ESCR_L2                 *((volatile unsigned int*)(0x42706088UL))\r
+#define bFM3_MFS3_CSIO_ESCR_WT0                *((volatile unsigned int*)(0x4270608CUL))\r
+#define bFM3_MFS3_CSIO_ESCR_WT1                *((volatile unsigned int*)(0x42706090UL))\r
+#define bFM3_MFS3_CSIO_ESCR_SOP                *((volatile unsigned int*)(0x4270609CUL))\r
+#define bFM3_MFS3_CSIO_SSR_TBI                 *((volatile unsigned int*)(0x427060A0UL))\r
+#define bFM3_MFS3_CSIO_SSR_TDRE                *((volatile unsigned int*)(0x427060A4UL))\r
+#define bFM3_MFS3_CSIO_SSR_RDRF                *((volatile unsigned int*)(0x427060A8UL))\r
+#define bFM3_MFS3_CSIO_SSR_ORE                 *((volatile unsigned int*)(0x427060ACUL))\r
+#define bFM3_MFS3_CSIO_SSR_REC                 *((volatile unsigned int*)(0x427060BCUL))\r
+\r
+/* UART LIN channel 3 registers */\r
+#define bFM3_MFS3_LIN_SMR_SOE                  *((volatile unsigned int*)(0x42706000UL))\r
+#define bFM3_MFS3_LIN_SMR_SBL                  *((volatile unsigned int*)(0x4270600CUL))\r
+#define bFM3_MFS3_LIN_SMR_WUCR                 *((volatile unsigned int*)(0x42706010UL))\r
+#define bFM3_MFS3_LIN_SMR_MD0                  *((volatile unsigned int*)(0x42706014UL))\r
+#define bFM3_MFS3_LIN_SMR_MD1                  *((volatile unsigned int*)(0x42706018UL))\r
+#define bFM3_MFS3_LIN_SMR_MD2                  *((volatile unsigned int*)(0x4270601CUL))\r
+#define bFM3_MFS3_LIN_SCR_TXE                  *((volatile unsigned int*)(0x42706020UL))\r
+#define bFM3_MFS3_LIN_SCR_RXE                  *((volatile unsigned int*)(0x42706024UL))\r
+#define bFM3_MFS3_LIN_SCR_TBIE                 *((volatile unsigned int*)(0x42706028UL))\r
+#define bFM3_MFS3_LIN_SCR_TIE                  *((volatile unsigned int*)(0x4270602CUL))\r
+#define bFM3_MFS3_LIN_SCR_RIE                  *((volatile unsigned int*)(0x42706030UL))\r
+#define bFM3_MFS3_LIN_SCR_LBR                  *((volatile unsigned int*)(0x42706034UL))\r
+#define bFM3_MFS3_LIN_SCR_MS                   *((volatile unsigned int*)(0x42706038UL))\r
+#define bFM3_MFS3_LIN_SCR_UPCL                 *((volatile unsigned int*)(0x4270603CUL))\r
+#define bFM3_MFS3_LIN_ESCR_DEL0                *((volatile unsigned int*)(0x42706080UL))\r
+#define bFM3_MFS3_LIN_ESCR_DEL1                *((volatile unsigned int*)(0x42706084UL))\r
+#define bFM3_MFS3_LIN_ESCR_LBL0                *((volatile unsigned int*)(0x42706088UL))\r
+#define bFM3_MFS3_LIN_ESCR_LBL1                *((volatile unsigned int*)(0x4270608CUL))\r
+#define bFM3_MFS3_LIN_ESCR_LBIE                *((volatile unsigned int*)(0x42706090UL))\r
+#define bFM3_MFS3_LIN_ESCR_ESBL                *((volatile unsigned int*)(0x42706098UL))\r
+#define bFM3_MFS3_LIN_SSR_TBI                  *((volatile unsigned int*)(0x427060A0UL))\r
+#define bFM3_MFS3_LIN_SSR_TDRE                 *((volatile unsigned int*)(0x427060A4UL))\r
+#define bFM3_MFS3_LIN_SSR_RDRF                 *((volatile unsigned int*)(0x427060A8UL))\r
+#define bFM3_MFS3_LIN_SSR_ORE                  *((volatile unsigned int*)(0x427060ACUL))\r
+#define bFM3_MFS3_LIN_SSR_FRE                  *((volatile unsigned int*)(0x427060B0UL))\r
+#define bFM3_MFS3_LIN_SSR_LBD                  *((volatile unsigned int*)(0x427060B4UL))\r
+#define bFM3_MFS3_LIN_SSR_REC                  *((volatile unsigned int*)(0x427060BCUL))\r
+#define bFM3_MFS3_LIN_BGR_EXT                  *((volatile unsigned int*)(0x427061BCUL))\r
+#define bFM3_MFS3_LIN_BGR1_EXT                 *((volatile unsigned int*)(0x427061BCUL))\r
+\r
+/* I2C channel 3 registers */\r
+#define bFM3_MFS3_I2C_SMR_ITST0                *((volatile unsigned int*)(0x42706000UL))\r
+#define bFM3_MFS3_I2C_SMR_ITST1                *((volatile unsigned int*)(0x42706004UL))\r
+#define bFM3_MFS3_I2C_SMR_TIE                  *((volatile unsigned int*)(0x42706008UL))\r
+#define bFM3_MFS3_I2C_SMR_RIE                  *((volatile unsigned int*)(0x4270600CUL))\r
+#define bFM3_MFS3_I2C_SMR_WUCR                 *((volatile unsigned int*)(0x42706010UL))\r
+#define bFM3_MFS3_I2C_SMR_MD0                  *((volatile unsigned int*)(0x42706014UL))\r
+#define bFM3_MFS3_I2C_SMR_MD1                  *((volatile unsigned int*)(0x42706018UL))\r
+#define bFM3_MFS3_I2C_SMR_MD2                  *((volatile unsigned int*)(0x4270601CUL))\r
+#define bFM3_MFS3_I2C_IBCR_INT                 *((volatile unsigned int*)(0x42706020UL))\r
+#define bFM3_MFS3_I2C_IBCR_BER                 *((volatile unsigned int*)(0x42706024UL))\r
+#define bFM3_MFS3_I2C_IBCR_INTE                *((volatile unsigned int*)(0x42706028UL))\r
+#define bFM3_MFS3_I2C_IBCR_CNDE                *((volatile unsigned int*)(0x4270602CUL))\r
+#define bFM3_MFS3_I2C_IBCR_WSEL                *((volatile unsigned int*)(0x42706030UL))\r
+#define bFM3_MFS3_I2C_IBCR_ACKE                *((volatile unsigned int*)(0x42706034UL))\r
+#define bFM3_MFS3_I2C_IBCR_ACT                 *((volatile unsigned int*)(0x42706038UL))\r
+#define bFM3_MFS3_I2C_IBCR_SCC                 *((volatile unsigned int*)(0x42706038UL))\r
+#define bFM3_MFS3_I2C_IBCR_MSS                 *((volatile unsigned int*)(0x4270603CUL))\r
+#define bFM3_MFS3_I2C_IBSR_BB                  *((volatile unsigned int*)(0x42706080UL))\r
+#define bFM3_MFS3_I2C_IBSR_SPC                 *((volatile unsigned int*)(0x42706084UL))\r
+#define bFM3_MFS3_I2C_IBSR_RSC                 *((volatile unsigned int*)(0x42706088UL))\r
+#define bFM3_MFS3_I2C_IBSR_AL                  *((volatile unsigned int*)(0x4270608CUL))\r
+#define bFM3_MFS3_I2C_IBSR_TRX                 *((volatile unsigned int*)(0x42706090UL))\r
+#define bFM3_MFS3_I2C_IBSR_RSA                 *((volatile unsigned int*)(0x42706094UL))\r
+#define bFM3_MFS3_I2C_IBSR_RACK                *((volatile unsigned int*)(0x42706098UL))\r
+#define bFM3_MFS3_I2C_IBSR_FBT                 *((volatile unsigned int*)(0x4270609CUL))\r
+#define bFM3_MFS3_I2C_SSR_TBI                  *((volatile unsigned int*)(0x427060A0UL))\r
+#define bFM3_MFS3_I2C_SSR_TDRE                 *((volatile unsigned int*)(0x427060A4UL))\r
+#define bFM3_MFS3_I2C_SSR_RDRF                 *((volatile unsigned int*)(0x427060A8UL))\r
+#define bFM3_MFS3_I2C_SSR_ORE                  *((volatile unsigned int*)(0x427060ACUL))\r
+#define bFM3_MFS3_I2C_SSR_TBIE                 *((volatile unsigned int*)(0x427060B0UL))\r
+#define bFM3_MFS3_I2C_SSR_DMA                  *((volatile unsigned int*)(0x427060B4UL))\r
+#define bFM3_MFS3_I2C_SSR_TSET                 *((volatile unsigned int*)(0x427060B8UL))\r
+#define bFM3_MFS3_I2C_SSR_REC                  *((volatile unsigned int*)(0x427060BCUL))\r
+#define bFM3_MFS3_I2C_ISBA_SA0                 *((volatile unsigned int*)(0x42706200UL))\r
+#define bFM3_MFS3_I2C_ISBA_SA1                 *((volatile unsigned int*)(0x42706204UL))\r
+#define bFM3_MFS3_I2C_ISBA_SA2                 *((volatile unsigned int*)(0x42706208UL))\r
+#define bFM3_MFS3_I2C_ISBA_SA3                 *((volatile unsigned int*)(0x4270620CUL))\r
+#define bFM3_MFS3_I2C_ISBA_SA4                 *((volatile unsigned int*)(0x42706210UL))\r
+#define bFM3_MFS3_I2C_ISBA_SA5                 *((volatile unsigned int*)(0x42706214UL))\r
+#define bFM3_MFS3_I2C_ISBA_SA6                 *((volatile unsigned int*)(0x42706218UL))\r
+#define bFM3_MFS3_I2C_ISBA_SAEN                *((volatile unsigned int*)(0x4270621CUL))\r
+#define bFM3_MFS3_I2C_ISMK_SM0                 *((volatile unsigned int*)(0x42706220UL))\r
+#define bFM3_MFS3_I2C_ISMK_SM1                 *((volatile unsigned int*)(0x42706224UL))\r
+#define bFM3_MFS3_I2C_ISMK_SM2                 *((volatile unsigned int*)(0x42706228UL))\r
+#define bFM3_MFS3_I2C_ISMK_SM3                 *((volatile unsigned int*)(0x4270622CUL))\r
+#define bFM3_MFS3_I2C_ISMK_SM4                 *((volatile unsigned int*)(0x42706230UL))\r
+#define bFM3_MFS3_I2C_ISMK_SM5                 *((volatile unsigned int*)(0x42706234UL))\r
+#define bFM3_MFS3_I2C_ISMK_SM6                 *((volatile unsigned int*)(0x42706238UL))\r
+#define bFM3_MFS3_I2C_ISMK_EN                  *((volatile unsigned int*)(0x4270623CUL))\r
+\r
+/* UART asynchronous channel 4 registers */\r
+#define bFM3_MFS4_UART_SMR_SOE                 *((volatile unsigned int*)(0x42708000UL))\r
+#define bFM3_MFS4_UART_SMR_BDS                 *((volatile unsigned int*)(0x42708008UL))\r
+#define bFM3_MFS4_UART_SMR_SBL                 *((volatile unsigned int*)(0x4270800CUL))\r
+#define bFM3_MFS4_UART_SMR_WUCR                *((volatile unsigned int*)(0x42708010UL))\r
+#define bFM3_MFS4_UART_SMR_MD0                 *((volatile unsigned int*)(0x42708014UL))\r
+#define bFM3_MFS4_UART_SMR_MD1                 *((volatile unsigned int*)(0x42708018UL))\r
+#define bFM3_MFS4_UART_SMR_MD2                 *((volatile unsigned int*)(0x4270801CUL))\r
+#define bFM3_MFS4_UART_SCR_TXE                 *((volatile unsigned int*)(0x42708020UL))\r
+#define bFM3_MFS4_UART_SCR_RXE                 *((volatile unsigned int*)(0x42708024UL))\r
+#define bFM3_MFS4_UART_SCR_TBIE                *((volatile unsigned int*)(0x42708028UL))\r
+#define bFM3_MFS4_UART_SCR_TIE                 *((volatile unsigned int*)(0x4270802CUL))\r
+#define bFM3_MFS4_UART_SCR_RIE                 *((volatile unsigned int*)(0x42708030UL))\r
+#define bFM3_MFS4_UART_SCR_UPCL                *((volatile unsigned int*)(0x4270803CUL))\r
+#define bFM3_MFS4_UART_ESCR_L0                 *((volatile unsigned int*)(0x42708080UL))\r
+#define bFM3_MFS4_UART_ESCR_L1                 *((volatile unsigned int*)(0x42708084UL))\r
+#define bFM3_MFS4_UART_ESCR_L2                 *((volatile unsigned int*)(0x42708088UL))\r
+#define bFM3_MFS4_UART_ESCR_P                  *((volatile unsigned int*)(0x4270808CUL))\r
+#define bFM3_MFS4_UART_ESCR_PEN                *((volatile unsigned int*)(0x42708090UL))\r
+#define bFM3_MFS4_UART_ESCR_INV                *((volatile unsigned int*)(0x42708094UL))\r
+#define bFM3_MFS4_UART_ESCR_ESBL               *((volatile unsigned int*)(0x42708098UL))\r
+#define bFM3_MFS4_UART_ESCR_FLWEN              *((volatile unsigned int*)(0x4270809CUL))\r
+#define bFM3_MFS4_UART_SSR_TBI                 *((volatile unsigned int*)(0x427080A0UL))\r
+#define bFM3_MFS4_UART_SSR_TDRE                *((volatile unsigned int*)(0x427080A4UL))\r
+#define bFM3_MFS4_UART_SSR_RDRF                *((volatile unsigned int*)(0x427080A8UL))\r
+#define bFM3_MFS4_UART_SSR_ORE                 *((volatile unsigned int*)(0x427080ACUL))\r
+#define bFM3_MFS4_UART_SSR_FRE                 *((volatile unsigned int*)(0x427080B0UL))\r
+#define bFM3_MFS4_UART_SSR_PE                  *((volatile unsigned int*)(0x427080B4UL))\r
+#define bFM3_MFS4_UART_SSR_REC                 *((volatile unsigned int*)(0x427080BCUL))\r
+#define bFM3_MFS4_UART_RDR_AD                  *((volatile unsigned int*)(0x42708120UL))\r
+#define bFM3_MFS4_UART_TDR_AD                  *((volatile unsigned int*)(0x42708120UL))\r
+#define bFM3_MFS4_UART_BGR_EXT                 *((volatile unsigned int*)(0x427081BCUL))\r
+#define bFM3_MFS4_UART_BGR1_EXT                *((volatile unsigned int*)(0x427081BCUL))\r
+#define bFM3_MFS4_UART_FCR_FE1                 *((volatile unsigned int*)(0x42708280UL))\r
+#define bFM3_MFS4_UART_FCR_FE2                 *((volatile unsigned int*)(0x42708284UL))\r
+#define bFM3_MFS4_UART_FCR_FCL1                *((volatile unsigned int*)(0x42708288UL))\r
+#define bFM3_MFS4_UART_FCR_FCL2                *((volatile unsigned int*)(0x4270828CUL))\r
+#define bFM3_MFS4_UART_FCR_FSET                *((volatile unsigned int*)(0x42708290UL))\r
+#define bFM3_MFS4_UART_FCR_FLD                 *((volatile unsigned int*)(0x42708294UL))\r
+#define bFM3_MFS4_UART_FCR_FLST                *((volatile unsigned int*)(0x42708298UL))\r
+#define bFM3_MFS4_UART_FCR_FSEL                *((volatile unsigned int*)(0x427082A0UL))\r
+#define bFM3_MFS4_UART_FCR_FTIE                *((volatile unsigned int*)(0x427082A4UL))\r
+#define bFM3_MFS4_UART_FCR_FDRQ                *((volatile unsigned int*)(0x427082A8UL))\r
+#define bFM3_MFS4_UART_FCR_FRIE                *((volatile unsigned int*)(0x427082ACUL))\r
+#define bFM3_MFS4_UART_FCR_FLSTE               *((volatile unsigned int*)(0x427082B0UL))\r
+#define bFM3_MFS4_UART_FCR_FTST0               *((volatile unsigned int*)(0x427082B8UL))\r
+#define bFM3_MFS4_UART_FCR_FTST1               *((volatile unsigned int*)(0x427082BCUL))\r
+#define bFM3_MFS4_UART_FCR0_FE1                *((volatile unsigned int*)(0x42708280UL))\r
+#define bFM3_MFS4_UART_FCR0_FE2                *((volatile unsigned int*)(0x42708284UL))\r
+#define bFM3_MFS4_UART_FCR0_FCL1               *((volatile unsigned int*)(0x42708288UL))\r
+#define bFM3_MFS4_UART_FCR0_FCL2               *((volatile unsigned int*)(0x4270828CUL))\r
+#define bFM3_MFS4_UART_FCR0_FSET               *((volatile unsigned int*)(0x42708290UL))\r
+#define bFM3_MFS4_UART_FCR0_FLD                *((volatile unsigned int*)(0x42708294UL))\r
+#define bFM3_MFS4_UART_FCR0_FLST               *((volatile unsigned int*)(0x42708298UL))\r
+#define bFM3_MFS4_UART_FCR1_FSEL               *((volatile unsigned int*)(0x427082A0UL))\r
+#define bFM3_MFS4_UART_FCR1_FTIE               *((volatile unsigned int*)(0x427082A4UL))\r
+#define bFM3_MFS4_UART_FCR1_FDRQ               *((volatile unsigned int*)(0x427082A8UL))\r
+#define bFM3_MFS4_UART_FCR1_FRIE               *((volatile unsigned int*)(0x427082ACUL))\r
+#define bFM3_MFS4_UART_FCR1_FLSTE              *((volatile unsigned int*)(0x427082B0UL))\r
+#define bFM3_MFS4_UART_FCR1_FTST0              *((volatile unsigned int*)(0x427082B8UL))\r
+#define bFM3_MFS4_UART_FCR1_FTST1              *((volatile unsigned int*)(0x427082BCUL))\r
+#define bFM3_MFS4_UART_FBYTE_FD0               *((volatile unsigned int*)(0x42708300UL))\r
+#define bFM3_MFS4_UART_FBYTE_FD1               *((volatile unsigned int*)(0x42708304UL))\r
+#define bFM3_MFS4_UART_FBYTE_FD2               *((volatile unsigned int*)(0x42708308UL))\r
+#define bFM3_MFS4_UART_FBYTE_FD3               *((volatile unsigned int*)(0x4270830CUL))\r
+#define bFM3_MFS4_UART_FBYTE_FD4               *((volatile unsigned int*)(0x42708310UL))\r
+#define bFM3_MFS4_UART_FBYTE_FD5               *((volatile unsigned int*)(0x42708314UL))\r
+#define bFM3_MFS4_UART_FBYTE_FD6               *((volatile unsigned int*)(0x42708318UL))\r
+#define bFM3_MFS4_UART_FBYTE_FD7               *((volatile unsigned int*)(0x4270831CUL))\r
+#define bFM3_MFS4_UART_FBYTE_FD8               *((volatile unsigned int*)(0x42708320UL))\r
+#define bFM3_MFS4_UART_FBYTE_FD9               *((volatile unsigned int*)(0x42708324UL))\r
+#define bFM3_MFS4_UART_FBYTE_FD10              *((volatile unsigned int*)(0x42708328UL))\r
+#define bFM3_MFS4_UART_FBYTE_FD11              *((volatile unsigned int*)(0x4270832CUL))\r
+#define bFM3_MFS4_UART_FBYTE_FD12              *((volatile unsigned int*)(0x42708330UL))\r
+#define bFM3_MFS4_UART_FBYTE_FD13              *((volatile unsigned int*)(0x42708334UL))\r
+#define bFM3_MFS4_UART_FBYTE_FD14              *((volatile unsigned int*)(0x42708338UL))\r
+#define bFM3_MFS4_UART_FBYTE_FD15              *((volatile unsigned int*)(0x4270833CUL))\r
+#define bFM3_MFS4_UART_FBYTE1_FD0              *((volatile unsigned int*)(0x42708300UL))\r
+#define bFM3_MFS4_UART_FBYTE1_FD1              *((volatile unsigned int*)(0x42708304UL))\r
+#define bFM3_MFS4_UART_FBYTE1_FD2              *((volatile unsigned int*)(0x42708308UL))\r
+#define bFM3_MFS4_UART_FBYTE1_FD3              *((volatile unsigned int*)(0x4270830CUL))\r
+#define bFM3_MFS4_UART_FBYTE1_FD4              *((volatile unsigned int*)(0x42708310UL))\r
+#define bFM3_MFS4_UART_FBYTE1_FD5              *((volatile unsigned int*)(0x42708314UL))\r
+#define bFM3_MFS4_UART_FBYTE1_FD6              *((volatile unsigned int*)(0x42708318UL))\r
+#define bFM3_MFS4_UART_FBYTE1_FD7              *((volatile unsigned int*)(0x4270831CUL))\r
+#define bFM3_MFS4_UART_FBYTE2_FD8              *((volatile unsigned int*)(0x42708320UL))\r
+#define bFM3_MFS4_UART_FBYTE2_FD9              *((volatile unsigned int*)(0x42708324UL))\r
+#define bFM3_MFS4_UART_FBYTE2_FD10             *((volatile unsigned int*)(0x42708328UL))\r
+#define bFM3_MFS4_UART_FBYTE2_FD11             *((volatile unsigned int*)(0x4270832CUL))\r
+#define bFM3_MFS4_UART_FBYTE2_FD12             *((volatile unsigned int*)(0x42708330UL))\r
+#define bFM3_MFS4_UART_FBYTE2_FD13             *((volatile unsigned int*)(0x42708334UL))\r
+#define bFM3_MFS4_UART_FBYTE2_FD14             *((volatile unsigned int*)(0x42708338UL))\r
+#define bFM3_MFS4_UART_FBYTE2_FD15             *((volatile unsigned int*)(0x4270833CUL))\r
+\r
+/* UART synchronous channel 4 registers */\r
+#define bFM3_MFS4_CSIO_SMR_SOE                 *((volatile unsigned int*)(0x42708000UL))\r
+#define bFM3_MFS4_CSIO_SMR_SCKE                *((volatile unsigned int*)(0x42708004UL))\r
+#define bFM3_MFS4_CSIO_SMR_BDS                 *((volatile unsigned int*)(0x42708008UL))\r
+#define bFM3_MFS4_CSIO_SMR_SCINV               *((volatile unsigned int*)(0x4270800CUL))\r
+#define bFM3_MFS4_CSIO_SMR_WUCR                *((volatile unsigned int*)(0x42708010UL))\r
+#define bFM3_MFS4_CSIO_SMR_MD0                 *((volatile unsigned int*)(0x42708014UL))\r
+#define bFM3_MFS4_CSIO_SMR_MD1                 *((volatile unsigned int*)(0x42708018UL))\r
+#define bFM3_MFS4_CSIO_SMR_MD2                 *((volatile unsigned int*)(0x4270801CUL))\r
+#define bFM3_MFS4_CSIO_SCR_TXE                 *((volatile unsigned int*)(0x42708020UL))\r
+#define bFM3_MFS4_CSIO_SCR_RXE                 *((volatile unsigned int*)(0x42708024UL))\r
+#define bFM3_MFS4_CSIO_SCR_TBIE                *((volatile unsigned int*)(0x42708028UL))\r
+#define bFM3_MFS4_CSIO_SCR_TIE                 *((volatile unsigned int*)(0x4270802CUL))\r
+#define bFM3_MFS4_CSIO_SCR_RIE                 *((volatile unsigned int*)(0x42708030UL))\r
+#define bFM3_MFS4_CSIO_SCR_SPI                 *((volatile unsigned int*)(0x42708034UL))\r
+#define bFM3_MFS4_CSIO_SCR_MS                  *((volatile unsigned int*)(0x42708038UL))\r
+#define bFM3_MFS4_CSIO_SCR_UPCL                *((volatile unsigned int*)(0x4270803CUL))\r
+#define bFM3_MFS4_CSIO_ESCR_L0                 *((volatile unsigned int*)(0x42708080UL))\r
+#define bFM3_MFS4_CSIO_ESCR_L1                 *((volatile unsigned int*)(0x42708084UL))\r
+#define bFM3_MFS4_CSIO_ESCR_L2                 *((volatile unsigned int*)(0x42708088UL))\r
+#define bFM3_MFS4_CSIO_ESCR_WT0                *((volatile unsigned int*)(0x4270808CUL))\r
+#define bFM3_MFS4_CSIO_ESCR_WT1                *((volatile unsigned int*)(0x42708090UL))\r
+#define bFM3_MFS4_CSIO_ESCR_SOP                *((volatile unsigned int*)(0x4270809CUL))\r
+#define bFM3_MFS4_CSIO_SSR_TBI                 *((volatile unsigned int*)(0x427080A0UL))\r
+#define bFM3_MFS4_CSIO_SSR_TDRE                *((volatile unsigned int*)(0x427080A4UL))\r
+#define bFM3_MFS4_CSIO_SSR_RDRF                *((volatile unsigned int*)(0x427080A8UL))\r
+#define bFM3_MFS4_CSIO_SSR_ORE                 *((volatile unsigned int*)(0x427080ACUL))\r
+#define bFM3_MFS4_CSIO_SSR_REC                 *((volatile unsigned int*)(0x427080BCUL))\r
+#define bFM3_MFS4_CSIO_FCR_FE1                 *((volatile unsigned int*)(0x42708280UL))\r
+#define bFM3_MFS4_CSIO_FCR_FE2                 *((volatile unsigned int*)(0x42708284UL))\r
+#define bFM3_MFS4_CSIO_FCR_FCL1                *((volatile unsigned int*)(0x42708288UL))\r
+#define bFM3_MFS4_CSIO_FCR_FCL2                *((volatile unsigned int*)(0x4270828CUL))\r
+#define bFM3_MFS4_CSIO_FCR_FSET                *((volatile unsigned int*)(0x42708290UL))\r
+#define bFM3_MFS4_CSIO_FCR_FLD                 *((volatile unsigned int*)(0x42708294UL))\r
+#define bFM3_MFS4_CSIO_FCR_FLST                *((volatile unsigned int*)(0x42708298UL))\r
+#define bFM3_MFS4_CSIO_FCR_FSEL                *((volatile unsigned int*)(0x427082A0UL))\r
+#define bFM3_MFS4_CSIO_FCR_FTIE                *((volatile unsigned int*)(0x427082A4UL))\r
+#define bFM3_MFS4_CSIO_FCR_FDRQ                *((volatile unsigned int*)(0x427082A8UL))\r
+#define bFM3_MFS4_CSIO_FCR_FRIE                *((volatile unsigned int*)(0x427082ACUL))\r
+#define bFM3_MFS4_CSIO_FCR_FLSTE               *((volatile unsigned int*)(0x427082B0UL))\r
+#define bFM3_MFS4_CSIO_FCR_FTST0               *((volatile unsigned int*)(0x427082B8UL))\r
+#define bFM3_MFS4_CSIO_FCR_FTST1               *((volatile unsigned int*)(0x427082BCUL))\r
+#define bFM3_MFS4_CSIO_FCR0_FE1                *((volatile unsigned int*)(0x42708280UL))\r
+#define bFM3_MFS4_CSIO_FCR0_FE2                *((volatile unsigned int*)(0x42708284UL))\r
+#define bFM3_MFS4_CSIO_FCR0_FCL1               *((volatile unsigned int*)(0x42708288UL))\r
+#define bFM3_MFS4_CSIO_FCR0_FCL2               *((volatile unsigned int*)(0x4270828CUL))\r
+#define bFM3_MFS4_CSIO_FCR0_FSET               *((volatile unsigned int*)(0x42708290UL))\r
+#define bFM3_MFS4_CSIO_FCR0_FLD                *((volatile unsigned int*)(0x42708294UL))\r
+#define bFM3_MFS4_CSIO_FCR0_FLST               *((volatile unsigned int*)(0x42708298UL))\r
+#define bFM3_MFS4_CSIO_FCR1_FSEL               *((volatile unsigned int*)(0x427082A0UL))\r
+#define bFM3_MFS4_CSIO_FCR1_FTIE               *((volatile unsigned int*)(0x427082A4UL))\r
+#define bFM3_MFS4_CSIO_FCR1_FDRQ               *((volatile unsigned int*)(0x427082A8UL))\r
+#define bFM3_MFS4_CSIO_FCR1_FRIE               *((volatile unsigned int*)(0x427082ACUL))\r
+#define bFM3_MFS4_CSIO_FCR1_FLSTE              *((volatile unsigned int*)(0x427082B0UL))\r
+#define bFM3_MFS4_CSIO_FCR1_FTST0              *((volatile unsigned int*)(0x427082B8UL))\r
+#define bFM3_MFS4_CSIO_FCR1_FTST1              *((volatile unsigned int*)(0x427082BCUL))\r
+#define bFM3_MFS4_CSIO_FBYTE_FD0               *((volatile unsigned int*)(0x42708300UL))\r
+#define bFM3_MFS4_CSIO_FBYTE_FD1               *((volatile unsigned int*)(0x42708304UL))\r
+#define bFM3_MFS4_CSIO_FBYTE_FD2               *((volatile unsigned int*)(0x42708308UL))\r
+#define bFM3_MFS4_CSIO_FBYTE_FD3               *((volatile unsigned int*)(0x4270830CUL))\r
+#define bFM3_MFS4_CSIO_FBYTE_FD4               *((volatile unsigned int*)(0x42708310UL))\r
+#define bFM3_MFS4_CSIO_FBYTE_FD5               *((volatile unsigned int*)(0x42708314UL))\r
+#define bFM3_MFS4_CSIO_FBYTE_FD6               *((volatile unsigned int*)(0x42708318UL))\r
+#define bFM3_MFS4_CSIO_FBYTE_FD7               *((volatile unsigned int*)(0x4270831CUL))\r
+#define bFM3_MFS4_CSIO_FBYTE_FD8               *((volatile unsigned int*)(0x42708320UL))\r
+#define bFM3_MFS4_CSIO_FBYTE_FD9               *((volatile unsigned int*)(0x42708324UL))\r
+#define bFM3_MFS4_CSIO_FBYTE_FD10              *((volatile unsigned int*)(0x42708328UL))\r
+#define bFM3_MFS4_CSIO_FBYTE_FD11              *((volatile unsigned int*)(0x4270832CUL))\r
+#define bFM3_MFS4_CSIO_FBYTE_FD12              *((volatile unsigned int*)(0x42708330UL))\r
+#define bFM3_MFS4_CSIO_FBYTE_FD13              *((volatile unsigned int*)(0x42708334UL))\r
+#define bFM3_MFS4_CSIO_FBYTE_FD14              *((volatile unsigned int*)(0x42708338UL))\r
+#define bFM3_MFS4_CSIO_FBYTE_FD15              *((volatile unsigned int*)(0x4270833CUL))\r
+#define bFM3_MFS4_CSIO_FBYTE1_FD0              *((volatile unsigned int*)(0x42708300UL))\r
+#define bFM3_MFS4_CSIO_FBYTE1_FD1              *((volatile unsigned int*)(0x42708304UL))\r
+#define bFM3_MFS4_CSIO_FBYTE1_FD2              *((volatile unsigned int*)(0x42708308UL))\r
+#define bFM3_MFS4_CSIO_FBYTE1_FD3              *((volatile unsigned int*)(0x4270830CUL))\r
+#define bFM3_MFS4_CSIO_FBYTE1_FD4              *((volatile unsigned int*)(0x42708310UL))\r
+#define bFM3_MFS4_CSIO_FBYTE1_FD5              *((volatile unsigned int*)(0x42708314UL))\r
+#define bFM3_MFS4_CSIO_FBYTE1_FD6              *((volatile unsigned int*)(0x42708318UL))\r
+#define bFM3_MFS4_CSIO_FBYTE1_FD7              *((volatile unsigned int*)(0x4270831CUL))\r
+#define bFM3_MFS4_CSIO_FBYTE2_FD8              *((volatile unsigned int*)(0x42708340UL))\r
+#define bFM3_MFS4_CSIO_FBYTE2_FD9              *((volatile unsigned int*)(0x42708344UL))\r
+#define bFM3_MFS4_CSIO_FBYTE2_FD10             *((volatile unsigned int*)(0x42708348UL))\r
+#define bFM3_MFS4_CSIO_FBYTE2_FD11             *((volatile unsigned int*)(0x4270834CUL))\r
+#define bFM3_MFS4_CSIO_FBYTE2_FD12             *((volatile unsigned int*)(0x42708350UL))\r
+#define bFM3_MFS4_CSIO_FBYTE2_FD13             *((volatile unsigned int*)(0x42708354UL))\r
+#define bFM3_MFS4_CSIO_FBYTE2_FD14             *((volatile unsigned int*)(0x42708358UL))\r
+#define bFM3_MFS4_CSIO_FBYTE2_FD15             *((volatile unsigned int*)(0x4270835CUL))\r
+\r
+/* UART LIN channel 4 registers */\r
+#define bFM3_MFS4_LIN_SMR_SOE                  *((volatile unsigned int*)(0x42708000UL))\r
+#define bFM3_MFS4_LIN_SMR_SBL                  *((volatile unsigned int*)(0x4270800CUL))\r
+#define bFM3_MFS4_LIN_SMR_WUCR                 *((volatile unsigned int*)(0x42708010UL))\r
+#define bFM3_MFS4_LIN_SMR_MD0                  *((volatile unsigned int*)(0x42708014UL))\r
+#define bFM3_MFS4_LIN_SMR_MD1                  *((volatile unsigned int*)(0x42708018UL))\r
+#define bFM3_MFS4_LIN_SMR_MD2                  *((volatile unsigned int*)(0x4270801CUL))\r
+#define bFM3_MFS4_LIN_SCR_TXE                  *((volatile unsigned int*)(0x42708020UL))\r
+#define bFM3_MFS4_LIN_SCR_RXE                  *((volatile unsigned int*)(0x42708024UL))\r
+#define bFM3_MFS4_LIN_SCR_TBIE                 *((volatile unsigned int*)(0x42708028UL))\r
+#define bFM3_MFS4_LIN_SCR_TIE                  *((volatile unsigned int*)(0x4270802CUL))\r
+#define bFM3_MFS4_LIN_SCR_RIE                  *((volatile unsigned int*)(0x42708030UL))\r
+#define bFM3_MFS4_LIN_SCR_LBR                  *((volatile unsigned int*)(0x42708034UL))\r
+#define bFM3_MFS4_LIN_SCR_MS                   *((volatile unsigned int*)(0x42708038UL))\r
+#define bFM3_MFS4_LIN_SCR_UPCL                 *((volatile unsigned int*)(0x4270803CUL))\r
+#define bFM3_MFS4_LIN_ESCR_DEL0                *((volatile unsigned int*)(0x42708080UL))\r
+#define bFM3_MFS4_LIN_ESCR_DEL1                *((volatile unsigned int*)(0x42708084UL))\r
+#define bFM3_MFS4_LIN_ESCR_LBL0                *((volatile unsigned int*)(0x42708088UL))\r
+#define bFM3_MFS4_LIN_ESCR_LBL1                *((volatile unsigned int*)(0x4270808CUL))\r
+#define bFM3_MFS4_LIN_ESCR_LBIE                *((volatile unsigned int*)(0x42708090UL))\r
+#define bFM3_MFS4_LIN_ESCR_ESBL                *((volatile unsigned int*)(0x42708098UL))\r
+#define bFM3_MFS4_LIN_SSR_TBI                  *((volatile unsigned int*)(0x427080A0UL))\r
+#define bFM3_MFS4_LIN_SSR_TDRE                 *((volatile unsigned int*)(0x427080A4UL))\r
+#define bFM3_MFS4_LIN_SSR_RDRF                 *((volatile unsigned int*)(0x427080A8UL))\r
+#define bFM3_MFS4_LIN_SSR_ORE                  *((volatile unsigned int*)(0x427080ACUL))\r
+#define bFM3_MFS4_LIN_SSR_FRE                  *((volatile unsigned int*)(0x427080B0UL))\r
+#define bFM3_MFS4_LIN_SSR_LBD                  *((volatile unsigned int*)(0x427080B4UL))\r
+#define bFM3_MFS4_LIN_SSR_REC                  *((volatile unsigned int*)(0x427080BCUL))\r
+#define bFM3_MFS4_LIN_BGR_EXT                  *((volatile unsigned int*)(0x427081BCUL))\r
+#define bFM3_MFS4_LIN_BGR1_EXT                 *((volatile unsigned int*)(0x427081BCUL))\r
+#define bFM3_MFS4_LIN_FCR_FE1                  *((volatile unsigned int*)(0x42708280UL))\r
+#define bFM3_MFS4_LIN_FCR_FE2                  *((volatile unsigned int*)(0x42708284UL))\r
+#define bFM3_MFS4_LIN_FCR_FCL1                 *((volatile unsigned int*)(0x42708288UL))\r
+#define bFM3_MFS4_LIN_FCR_FCL2                 *((volatile unsigned int*)(0x4270828CUL))\r
+#define bFM3_MFS4_LIN_FCR_FSET                 *((volatile unsigned int*)(0x42708290UL))\r
+#define bFM3_MFS4_LIN_FCR_FLD                  *((volatile unsigned int*)(0x42708294UL))\r
+#define bFM3_MFS4_LIN_FCR_FLST                 *((volatile unsigned int*)(0x42708298UL))\r
+#define bFM3_MFS4_LIN_FCR_FSEL                 *((volatile unsigned int*)(0x427082A0UL))\r
+#define bFM3_MFS4_LIN_FCR_FTIE                 *((volatile unsigned int*)(0x427082A4UL))\r
+#define bFM3_MFS4_LIN_FCR_FDRQ                 *((volatile unsigned int*)(0x427082A8UL))\r
+#define bFM3_MFS4_LIN_FCR_FRIE                 *((volatile unsigned int*)(0x427082ACUL))\r
+#define bFM3_MFS4_LIN_FCR_FLSTE                *((volatile unsigned int*)(0x427082B0UL))\r
+#define bFM3_MFS4_LIN_FCR_FTST0                *((volatile unsigned int*)(0x427082B8UL))\r
+#define bFM3_MFS4_LIN_FCR_FTST1                *((volatile unsigned int*)(0x427082BCUL))\r
+#define bFM3_MFS4_LIN_FCR0_FE1                 *((volatile unsigned int*)(0x42708280UL))\r
+#define bFM3_MFS4_LIN_FCR0_FE2                 *((volatile unsigned int*)(0x42708284UL))\r
+#define bFM3_MFS4_LIN_FCR0_FCL1                *((volatile unsigned int*)(0x42708288UL))\r
+#define bFM3_MFS4_LIN_FCR0_FCL2                *((volatile unsigned int*)(0x4270828CUL))\r
+#define bFM3_MFS4_LIN_FCR0_FSET                *((volatile unsigned int*)(0x42708290UL))\r
+#define bFM3_MFS4_LIN_FCR0_FLD                 *((volatile unsigned int*)(0x42708294UL))\r
+#define bFM3_MFS4_LIN_FCR0_FLST                *((volatile unsigned int*)(0x42708298UL))\r
+#define bFM3_MFS4_LIN_FCR1_FSEL                *((volatile unsigned int*)(0x427082A0UL))\r
+#define bFM3_MFS4_LIN_FCR1_FTIE                *((volatile unsigned int*)(0x427082A4UL))\r
+#define bFM3_MFS4_LIN_FCR1_FDRQ                *((volatile unsigned int*)(0x427082A8UL))\r
+#define bFM3_MFS4_LIN_FCR1_FRIE                *((volatile unsigned int*)(0x427082ACUL))\r
+#define bFM3_MFS4_LIN_FCR1_FLSTE               *((volatile unsigned int*)(0x427082B0UL))\r
+#define bFM3_MFS4_LIN_FCR1_FTST0               *((volatile unsigned int*)(0x427082B8UL))\r
+#define bFM3_MFS4_LIN_FCR1_FTST1               *((volatile unsigned int*)(0x427082BCUL))\r
+#define bFM3_MFS4_LIN_FBYTE_FD0                *((volatile unsigned int*)(0x42708300UL))\r
+#define bFM3_MFS4_LIN_FBYTE_FD1                *((volatile unsigned int*)(0x42708304UL))\r
+#define bFM3_MFS4_LIN_FBYTE_FD2                *((volatile unsigned int*)(0x42708308UL))\r
+#define bFM3_MFS4_LIN_FBYTE_FD3                *((volatile unsigned int*)(0x4270830CUL))\r
+#define bFM3_MFS4_LIN_FBYTE_FD4                *((volatile unsigned int*)(0x42708310UL))\r
+#define bFM3_MFS4_LIN_FBYTE_FD5                *((volatile unsigned int*)(0x42708314UL))\r
+#define bFM3_MFS4_LIN_FBYTE_FD6                *((volatile unsigned int*)(0x42708318UL))\r
+#define bFM3_MFS4_LIN_FBYTE_FD7                *((volatile unsigned int*)(0x4270831CUL))\r
+#define bFM3_MFS4_LIN_FBYTE_FD8                *((volatile unsigned int*)(0x42708320UL))\r
+#define bFM3_MFS4_LIN_FBYTE_FD9                *((volatile unsigned int*)(0x42708324UL))\r
+#define bFM3_MFS4_LIN_FBYTE_FD10               *((volatile unsigned int*)(0x42708328UL))\r
+#define bFM3_MFS4_LIN_FBYTE_FD11               *((volatile unsigned int*)(0x4270832CUL))\r
+#define bFM3_MFS4_LIN_FBYTE_FD12               *((volatile unsigned int*)(0x42708330UL))\r
+#define bFM3_MFS4_LIN_FBYTE_FD13               *((volatile unsigned int*)(0x42708334UL))\r
+#define bFM3_MFS4_LIN_FBYTE_FD14               *((volatile unsigned int*)(0x42708338UL))\r
+#define bFM3_MFS4_LIN_FBYTE_FD15               *((volatile unsigned int*)(0x4270833CUL))\r
+#define bFM3_MFS4_LIN_FBYTE1_FD0               *((volatile unsigned int*)(0x42708300UL))\r
+#define bFM3_MFS4_LIN_FBYTE1_FD1               *((volatile unsigned int*)(0x42708304UL))\r
+#define bFM3_MFS4_LIN_FBYTE1_FD2               *((volatile unsigned int*)(0x42708308UL))\r
+#define bFM3_MFS4_LIN_FBYTE1_FD3               *((volatile unsigned int*)(0x4270830CUL))\r
+#define bFM3_MFS4_LIN_FBYTE1_FD4               *((volatile unsigned int*)(0x42708310UL))\r
+#define bFM3_MFS4_LIN_FBYTE1_FD5               *((volatile unsigned int*)(0x42708314UL))\r
+#define bFM3_MFS4_LIN_FBYTE1_FD6               *((volatile unsigned int*)(0x42708318UL))\r
+#define bFM3_MFS4_LIN_FBYTE1_FD7               *((volatile unsigned int*)(0x4270831CUL))\r
+#define bFM3_MFS4_LIN_FBYTE2_FD8               *((volatile unsigned int*)(0x42708340UL))\r
+#define bFM3_MFS4_LIN_FBYTE2_FD9               *((volatile unsigned int*)(0x42708344UL))\r
+#define bFM3_MFS4_LIN_FBYTE2_FD10              *((volatile unsigned int*)(0x42708348UL))\r
+#define bFM3_MFS4_LIN_FBYTE2_FD11              *((volatile unsigned int*)(0x4270834CUL))\r
+#define bFM3_MFS4_LIN_FBYTE2_FD12              *((volatile unsigned int*)(0x42708350UL))\r
+#define bFM3_MFS4_LIN_FBYTE2_FD13              *((volatile unsigned int*)(0x42708354UL))\r
+#define bFM3_MFS4_LIN_FBYTE2_FD14              *((volatile unsigned int*)(0x42708358UL))\r
+#define bFM3_MFS4_LIN_FBYTE2_FD15              *((volatile unsigned int*)(0x4270835CUL))\r
+\r
+/* I2C channel 4 registers */\r
+#define bFM3_MFS4_I2C_SMR_ITST0                *((volatile unsigned int*)(0x42708000UL))\r
+#define bFM3_MFS4_I2C_SMR_ITST1                *((volatile unsigned int*)(0x42708004UL))\r
+#define bFM3_MFS4_I2C_SMR_TIE                  *((volatile unsigned int*)(0x42708008UL))\r
+#define bFM3_MFS4_I2C_SMR_RIE                  *((volatile unsigned int*)(0x4270800CUL))\r
+#define bFM3_MFS4_I2C_SMR_WUCR                 *((volatile unsigned int*)(0x42708010UL))\r
+#define bFM3_MFS4_I2C_SMR_MD0                  *((volatile unsigned int*)(0x42708014UL))\r
+#define bFM3_MFS4_I2C_SMR_MD1                  *((volatile unsigned int*)(0x42708018UL))\r
+#define bFM3_MFS4_I2C_SMR_MD2                  *((volatile unsigned int*)(0x4270801CUL))\r
+#define bFM3_MFS4_I2C_IBCR_INT                 *((volatile unsigned int*)(0x42708020UL))\r
+#define bFM3_MFS4_I2C_IBCR_BER                 *((volatile unsigned int*)(0x42708024UL))\r
+#define bFM3_MFS4_I2C_IBCR_INTE                *((volatile unsigned int*)(0x42708028UL))\r
+#define bFM3_MFS4_I2C_IBCR_CNDE                *((volatile unsigned int*)(0x4270802CUL))\r
+#define bFM3_MFS4_I2C_IBCR_WSEL                *((volatile unsigned int*)(0x42708030UL))\r
+#define bFM3_MFS4_I2C_IBCR_ACKE                *((volatile unsigned int*)(0x42708034UL))\r
+#define bFM3_MFS4_I2C_IBCR_ACT                 *((volatile unsigned int*)(0x42708038UL))\r
+#define bFM3_MFS4_I2C_IBCR_SCC                 *((volatile unsigned int*)(0x42708038UL))\r
+#define bFM3_MFS4_I2C_IBCR_MSS                 *((volatile unsigned int*)(0x4270803CUL))\r
+#define bFM3_MFS4_I2C_IBSR_BB                  *((volatile unsigned int*)(0x42708080UL))\r
+#define bFM3_MFS4_I2C_IBSR_SPC                 *((volatile unsigned int*)(0x42708084UL))\r
+#define bFM3_MFS4_I2C_IBSR_RSC                 *((volatile unsigned int*)(0x42708088UL))\r
+#define bFM3_MFS4_I2C_IBSR_AL                  *((volatile unsigned int*)(0x4270808CUL))\r
+#define bFM3_MFS4_I2C_IBSR_TRX                 *((volatile unsigned int*)(0x42708090UL))\r
+#define bFM3_MFS4_I2C_IBSR_RSA                 *((volatile unsigned int*)(0x42708094UL))\r
+#define bFM3_MFS4_I2C_IBSR_RACK                *((volatile unsigned int*)(0x42708098UL))\r
+#define bFM3_MFS4_I2C_IBSR_FBT                 *((volatile unsigned int*)(0x4270809CUL))\r
+#define bFM3_MFS4_I2C_SSR_TBI                  *((volatile unsigned int*)(0x427080A0UL))\r
+#define bFM3_MFS4_I2C_SSR_TDRE                 *((volatile unsigned int*)(0x427080A4UL))\r
+#define bFM3_MFS4_I2C_SSR_RDRF                 *((volatile unsigned int*)(0x427080A8UL))\r
+#define bFM3_MFS4_I2C_SSR_ORE                  *((volatile unsigned int*)(0x427080ACUL))\r
+#define bFM3_MFS4_I2C_SSR_TBIE                 *((volatile unsigned int*)(0x427080B0UL))\r
+#define bFM3_MFS4_I2C_SSR_DMA                  *((volatile unsigned int*)(0x427080B4UL))\r
+#define bFM3_MFS4_I2C_SSR_TSET                 *((volatile unsigned int*)(0x427080B8UL))\r
+#define bFM3_MFS4_I2C_SSR_REC                  *((volatile unsigned int*)(0x427080BCUL))\r
+#define bFM3_MFS4_I2C_ISBA_SA0                 *((volatile unsigned int*)(0x42708200UL))\r
+#define bFM3_MFS4_I2C_ISBA_SA1                 *((volatile unsigned int*)(0x42708204UL))\r
+#define bFM3_MFS4_I2C_ISBA_SA2                 *((volatile unsigned int*)(0x42708208UL))\r
+#define bFM3_MFS4_I2C_ISBA_SA3                 *((volatile unsigned int*)(0x4270820CUL))\r
+#define bFM3_MFS4_I2C_ISBA_SA4                 *((volatile unsigned int*)(0x42708210UL))\r
+#define bFM3_MFS4_I2C_ISBA_SA5                 *((volatile unsigned int*)(0x42708214UL))\r
+#define bFM3_MFS4_I2C_ISBA_SA6                 *((volatile unsigned int*)(0x42708218UL))\r
+#define bFM3_MFS4_I2C_ISBA_SAEN                *((volatile unsigned int*)(0x4270821CUL))\r
+#define bFM3_MFS4_I2C_ISMK_SM0                 *((volatile unsigned int*)(0x42708220UL))\r
+#define bFM3_MFS4_I2C_ISMK_SM1                 *((volatile unsigned int*)(0x42708224UL))\r
+#define bFM3_MFS4_I2C_ISMK_SM2                 *((volatile unsigned int*)(0x42708228UL))\r
+#define bFM3_MFS4_I2C_ISMK_SM3                 *((volatile unsigned int*)(0x4270822CUL))\r
+#define bFM3_MFS4_I2C_ISMK_SM4                 *((volatile unsigned int*)(0x42708230UL))\r
+#define bFM3_MFS4_I2C_ISMK_SM5                 *((volatile unsigned int*)(0x42708234UL))\r
+#define bFM3_MFS4_I2C_ISMK_SM6                 *((volatile unsigned int*)(0x42708238UL))\r
+#define bFM3_MFS4_I2C_ISMK_EN                  *((volatile unsigned int*)(0x4270823CUL))\r
+#define bFM3_MFS4_I2C_FCR_FE1                  *((volatile unsigned int*)(0x42708280UL))\r
+#define bFM3_MFS4_I2C_FCR_FE2                  *((volatile unsigned int*)(0x42708284UL))\r
+#define bFM3_MFS4_I2C_FCR_FCL1                 *((volatile unsigned int*)(0x42708288UL))\r
+#define bFM3_MFS4_I2C_FCR_FCL2                 *((volatile unsigned int*)(0x4270828CUL))\r
+#define bFM3_MFS4_I2C_FCR_FSET                 *((volatile unsigned int*)(0x42708290UL))\r
+#define bFM3_MFS4_I2C_FCR_FLD                  *((volatile unsigned int*)(0x42708294UL))\r
+#define bFM3_MFS4_I2C_FCR_FLST                 *((volatile unsigned int*)(0x42708298UL))\r
+#define bFM3_MFS4_I2C_FCR_FSEL                 *((volatile unsigned int*)(0x427082A0UL))\r
+#define bFM3_MFS4_I2C_FCR_FTIE                 *((volatile unsigned int*)(0x427082A4UL))\r
+#define bFM3_MFS4_I2C_FCR_FDRQ                 *((volatile unsigned int*)(0x427082A8UL))\r
+#define bFM3_MFS4_I2C_FCR_FRIE                 *((volatile unsigned int*)(0x427082ACUL))\r
+#define bFM3_MFS4_I2C_FCR_FLSTE                *((volatile unsigned int*)(0x427082B0UL))\r
+#define bFM3_MFS4_I2C_FCR_FTST0                *((volatile unsigned int*)(0x427082B8UL))\r
+#define bFM3_MFS4_I2C_FCR_FTST1                *((volatile unsigned int*)(0x427082BCUL))\r
+#define bFM3_MFS4_I2C_FCR0_FE1                 *((volatile unsigned int*)(0x42708280UL))\r
+#define bFM3_MFS4_I2C_FCR0_FE2                 *((volatile unsigned int*)(0x42708284UL))\r
+#define bFM3_MFS4_I2C_FCR0_FCL1                *((volatile unsigned int*)(0x42708288UL))\r
+#define bFM3_MFS4_I2C_FCR0_FCL2                *((volatile unsigned int*)(0x4270828CUL))\r
+#define bFM3_MFS4_I2C_FCR0_FSET                *((volatile unsigned int*)(0x42708290UL))\r
+#define bFM3_MFS4_I2C_FCR0_FLD                 *((volatile unsigned int*)(0x42708294UL))\r
+#define bFM3_MFS4_I2C_FCR0_FLST                *((volatile unsigned int*)(0x42708298UL))\r
+#define bFM3_MFS4_I2C_FCR1_FSEL                *((volatile unsigned int*)(0x427082A0UL))\r
+#define bFM3_MFS4_I2C_FCR1_FTIE                *((volatile unsigned int*)(0x427082A4UL))\r
+#define bFM3_MFS4_I2C_FCR1_FDRQ                *((volatile unsigned int*)(0x427082A8UL))\r
+#define bFM3_MFS4_I2C_FCR1_FRIE                *((volatile unsigned int*)(0x427082ACUL))\r
+#define bFM3_MFS4_I2C_FCR1_FLSTE               *((volatile unsigned int*)(0x427082B0UL))\r
+#define bFM3_MFS4_I2C_FCR1_FTST0               *((volatile unsigned int*)(0x427082B8UL))\r
+#define bFM3_MFS4_I2C_FCR1_FTST1               *((volatile unsigned int*)(0x427082BCUL))\r
+#define bFM3_MFS4_I2C_FBYTE_FD0                *((volatile unsigned int*)(0x42708300UL))\r
+#define bFM3_MFS4_I2C_FBYTE_FD1                *((volatile unsigned int*)(0x42708304UL))\r
+#define bFM3_MFS4_I2C_FBYTE_FD2                *((volatile unsigned int*)(0x42708308UL))\r
+#define bFM3_MFS4_I2C_FBYTE_FD3                *((volatile unsigned int*)(0x4270830CUL))\r
+#define bFM3_MFS4_I2C_FBYTE_FD4                *((volatile unsigned int*)(0x42708310UL))\r
+#define bFM3_MFS4_I2C_FBYTE_FD5                *((volatile unsigned int*)(0x42708314UL))\r
+#define bFM3_MFS4_I2C_FBYTE_FD6                *((volatile unsigned int*)(0x42708318UL))\r
+#define bFM3_MFS4_I2C_FBYTE_FD7                *((volatile unsigned int*)(0x4270831CUL))\r
+#define bFM3_MFS4_I2C_FBYTE_FD8                *((volatile unsigned int*)(0x42708320UL))\r
+#define bFM3_MFS4_I2C_FBYTE_FD9                *((volatile unsigned int*)(0x42708324UL))\r
+#define bFM3_MFS4_I2C_FBYTE_FD10               *((volatile unsigned int*)(0x42708328UL))\r
+#define bFM3_MFS4_I2C_FBYTE_FD11               *((volatile unsigned int*)(0x4270832CUL))\r
+#define bFM3_MFS4_I2C_FBYTE_FD12               *((volatile unsigned int*)(0x42708330UL))\r
+#define bFM3_MFS4_I2C_FBYTE_FD13               *((volatile unsigned int*)(0x42708334UL))\r
+#define bFM3_MFS4_I2C_FBYTE_FD14               *((volatile unsigned int*)(0x42708338UL))\r
+#define bFM3_MFS4_I2C_FBYTE_FD15               *((volatile unsigned int*)(0x4270833CUL))\r
+#define bFM3_MFS4_I2C_FBYTE1_FD0               *((volatile unsigned int*)(0x42708300UL))\r
+#define bFM3_MFS4_I2C_FBYTE1_FD1               *((volatile unsigned int*)(0x42708304UL))\r
+#define bFM3_MFS4_I2C_FBYTE1_FD2               *((volatile unsigned int*)(0x42708308UL))\r
+#define bFM3_MFS4_I2C_FBYTE1_FD3               *((volatile unsigned int*)(0x4270830CUL))\r
+#define bFM3_MFS4_I2C_FBYTE1_FD4               *((volatile unsigned int*)(0x42708310UL))\r
+#define bFM3_MFS4_I2C_FBYTE1_FD5               *((volatile unsigned int*)(0x42708314UL))\r
+#define bFM3_MFS4_I2C_FBYTE1_FD6               *((volatile unsigned int*)(0x42708318UL))\r
+#define bFM3_MFS4_I2C_FBYTE1_FD7               *((volatile unsigned int*)(0x4270831CUL))\r
+#define bFM3_MFS4_I2C_FBYTE2_FD8               *((volatile unsigned int*)(0x42708340UL))\r
+#define bFM3_MFS4_I2C_FBYTE2_FD9               *((volatile unsigned int*)(0x42708344UL))\r
+#define bFM3_MFS4_I2C_FBYTE2_FD10              *((volatile unsigned int*)(0x42708348UL))\r
+#define bFM3_MFS4_I2C_FBYTE2_FD11              *((volatile unsigned int*)(0x4270834CUL))\r
+#define bFM3_MFS4_I2C_FBYTE2_FD12              *((volatile unsigned int*)(0x42708350UL))\r
+#define bFM3_MFS4_I2C_FBYTE2_FD13              *((volatile unsigned int*)(0x42708354UL))\r
+#define bFM3_MFS4_I2C_FBYTE2_FD14              *((volatile unsigned int*)(0x42708358UL))\r
+#define bFM3_MFS4_I2C_FBYTE2_FD15              *((volatile unsigned int*)(0x4270835CUL))\r
+\r
+/* UART asynchronous channel 5 registers */\r
+#define bFM3_MFS5_UART_SMR_SOE                 *((volatile unsigned int*)(0x4270A000UL))\r
+#define bFM3_MFS5_UART_SMR_BDS                 *((volatile unsigned int*)(0x4270A008UL))\r
+#define bFM3_MFS5_UART_SMR_SBL                 *((volatile unsigned int*)(0x4270A00CUL))\r
+#define bFM3_MFS5_UART_SMR_WUCR                *((volatile unsigned int*)(0x4270A010UL))\r
+#define bFM3_MFS5_UART_SMR_MD0                 *((volatile unsigned int*)(0x4270A014UL))\r
+#define bFM3_MFS5_UART_SMR_MD1                 *((volatile unsigned int*)(0x4270A018UL))\r
+#define bFM3_MFS5_UART_SMR_MD2                 *((volatile unsigned int*)(0x4270A01CUL))\r
+#define bFM3_MFS5_UART_SCR_TXE                 *((volatile unsigned int*)(0x4270A020UL))\r
+#define bFM3_MFS5_UART_SCR_RXE                 *((volatile unsigned int*)(0x4270A024UL))\r
+#define bFM3_MFS5_UART_SCR_TBIE                *((volatile unsigned int*)(0x4270A028UL))\r
+#define bFM3_MFS5_UART_SCR_TIE                 *((volatile unsigned int*)(0x4270A02CUL))\r
+#define bFM3_MFS5_UART_SCR_RIE                 *((volatile unsigned int*)(0x4270A030UL))\r
+#define bFM3_MFS5_UART_SCR_UPCL                *((volatile unsigned int*)(0x4270A03CUL))\r
+#define bFM3_MFS5_UART_ESCR_L0                 *((volatile unsigned int*)(0x4270A080UL))\r
+#define bFM3_MFS5_UART_ESCR_L1                 *((volatile unsigned int*)(0x4270A084UL))\r
+#define bFM3_MFS5_UART_ESCR_L2                 *((volatile unsigned int*)(0x4270A088UL))\r
+#define bFM3_MFS5_UART_ESCR_P                  *((volatile unsigned int*)(0x4270A08CUL))\r
+#define bFM3_MFS5_UART_ESCR_PEN                *((volatile unsigned int*)(0x4270A090UL))\r
+#define bFM3_MFS5_UART_ESCR_INV                *((volatile unsigned int*)(0x4270A094UL))\r
+#define bFM3_MFS5_UART_ESCR_ESBL               *((volatile unsigned int*)(0x4270A098UL))\r
+#define bFM3_MFS5_UART_ESCR_FLWEN              *((volatile unsigned int*)(0x4270A09CUL))\r
+#define bFM3_MFS5_UART_SSR_TBI                 *((volatile unsigned int*)(0x4270A0A0UL))\r
+#define bFM3_MFS5_UART_SSR_TDRE                *((volatile unsigned int*)(0x4270A0A4UL))\r
+#define bFM3_MFS5_UART_SSR_RDRF                *((volatile unsigned int*)(0x4270A0A8UL))\r
+#define bFM3_MFS5_UART_SSR_ORE                 *((volatile unsigned int*)(0x4270A0ACUL))\r
+#define bFM3_MFS5_UART_SSR_FRE                 *((volatile unsigned int*)(0x4270A0B0UL))\r
+#define bFM3_MFS5_UART_SSR_PE                  *((volatile unsigned int*)(0x4270A0B4UL))\r
+#define bFM3_MFS5_UART_SSR_REC                 *((volatile unsigned int*)(0x4270A0BCUL))\r
+#define bFM3_MFS5_UART_RDR_AD                  *((volatile unsigned int*)(0x4270A120UL))\r
+#define bFM3_MFS5_UART_TDR_AD                  *((volatile unsigned int*)(0x4270A120UL))\r
+#define bFM3_MFS5_UART_BGR_EXT                 *((volatile unsigned int*)(0x4270A1BCUL))\r
+#define bFM3_MFS5_UART_BGR1_EXT                *((volatile unsigned int*)(0x4270A1BCUL))\r
+#define bFM3_MFS5_UART_FCR_FE1                 *((volatile unsigned int*)(0x4270A280UL))\r
+#define bFM3_MFS5_UART_FCR_FE2                 *((volatile unsigned int*)(0x4270A284UL))\r
+#define bFM3_MFS5_UART_FCR_FCL1                *((volatile unsigned int*)(0x4270A288UL))\r
+#define bFM3_MFS5_UART_FCR_FCL2                *((volatile unsigned int*)(0x4270A28CUL))\r
+#define bFM3_MFS5_UART_FCR_FSET                *((volatile unsigned int*)(0x4270A290UL))\r
+#define bFM3_MFS5_UART_FCR_FLD                 *((volatile unsigned int*)(0x4270A294UL))\r
+#define bFM3_MFS5_UART_FCR_FLST                *((volatile unsigned int*)(0x4270A298UL))\r
+#define bFM3_MFS5_UART_FCR_FSEL                *((volatile unsigned int*)(0x4270A2A0UL))\r
+#define bFM3_MFS5_UART_FCR_FTIE                *((volatile unsigned int*)(0x4270A2A4UL))\r
+#define bFM3_MFS5_UART_FCR_FDRQ                *((volatile unsigned int*)(0x4270A2A8UL))\r
+#define bFM3_MFS5_UART_FCR_FRIE                *((volatile unsigned int*)(0x4270A2ACUL))\r
+#define bFM3_MFS5_UART_FCR_FLSTE               *((volatile unsigned int*)(0x4270A2B0UL))\r
+#define bFM3_MFS5_UART_FCR_FTST0               *((volatile unsigned int*)(0x4270A2B8UL))\r
+#define bFM3_MFS5_UART_FCR_FTST1               *((volatile unsigned int*)(0x4270A2BCUL))\r
+#define bFM3_MFS5_UART_FCR0_FE1                *((volatile unsigned int*)(0x4270A280UL))\r
+#define bFM3_MFS5_UART_FCR0_FE2                *((volatile unsigned int*)(0x4270A284UL))\r
+#define bFM3_MFS5_UART_FCR0_FCL1               *((volatile unsigned int*)(0x4270A288UL))\r
+#define bFM3_MFS5_UART_FCR0_FCL2               *((volatile unsigned int*)(0x4270A28CUL))\r
+#define bFM3_MFS5_UART_FCR0_FSET               *((volatile unsigned int*)(0x4270A290UL))\r
+#define bFM3_MFS5_UART_FCR0_FLD                *((volatile unsigned int*)(0x4270A294UL))\r
+#define bFM3_MFS5_UART_FCR0_FLST               *((volatile unsigned int*)(0x4270A298UL))\r
+#define bFM3_MFS5_UART_FCR1_FSEL               *((volatile unsigned int*)(0x4270A2A0UL))\r
+#define bFM3_MFS5_UART_FCR1_FTIE               *((volatile unsigned int*)(0x4270A2A4UL))\r
+#define bFM3_MFS5_UART_FCR1_FDRQ               *((volatile unsigned int*)(0x4270A2A8UL))\r
+#define bFM3_MFS5_UART_FCR1_FRIE               *((volatile unsigned int*)(0x4270A2ACUL))\r
+#define bFM3_MFS5_UART_FCR1_FLSTE              *((volatile unsigned int*)(0x4270A2B0UL))\r
+#define bFM3_MFS5_UART_FCR1_FTST0              *((volatile unsigned int*)(0x4270A2B8UL))\r
+#define bFM3_MFS5_UART_FCR1_FTST1              *((volatile unsigned int*)(0x4270A2BCUL))\r
+#define bFM3_MFS5_UART_FBYTE_FD0               *((volatile unsigned int*)(0x4270A300UL))\r
+#define bFM3_MFS5_UART_FBYTE_FD1               *((volatile unsigned int*)(0x4270A304UL))\r
+#define bFM3_MFS5_UART_FBYTE_FD2               *((volatile unsigned int*)(0x4270A308UL))\r
+#define bFM3_MFS5_UART_FBYTE_FD3               *((volatile unsigned int*)(0x4270A30CUL))\r
+#define bFM3_MFS5_UART_FBYTE_FD4               *((volatile unsigned int*)(0x4270A310UL))\r
+#define bFM3_MFS5_UART_FBYTE_FD5               *((volatile unsigned int*)(0x4270A314UL))\r
+#define bFM3_MFS5_UART_FBYTE_FD6               *((volatile unsigned int*)(0x4270A318UL))\r
+#define bFM3_MFS5_UART_FBYTE_FD7               *((volatile unsigned int*)(0x4270A31CUL))\r
+#define bFM3_MFS5_UART_FBYTE_FD8               *((volatile unsigned int*)(0x4270A320UL))\r
+#define bFM3_MFS5_UART_FBYTE_FD9               *((volatile unsigned int*)(0x4270A324UL))\r
+#define bFM3_MFS5_UART_FBYTE_FD10              *((volatile unsigned int*)(0x4270A328UL))\r
+#define bFM3_MFS5_UART_FBYTE_FD11              *((volatile unsigned int*)(0x4270A32CUL))\r
+#define bFM3_MFS5_UART_FBYTE_FD12              *((volatile unsigned int*)(0x4270A330UL))\r
+#define bFM3_MFS5_UART_FBYTE_FD13              *((volatile unsigned int*)(0x4270A334UL))\r
+#define bFM3_MFS5_UART_FBYTE_FD14              *((volatile unsigned int*)(0x4270A338UL))\r
+#define bFM3_MFS5_UART_FBYTE_FD15              *((volatile unsigned int*)(0x4270A33CUL))\r
+#define bFM3_MFS5_UART_FBYTE1_FD0              *((volatile unsigned int*)(0x4270A300UL))\r
+#define bFM3_MFS5_UART_FBYTE1_FD1              *((volatile unsigned int*)(0x4270A304UL))\r
+#define bFM3_MFS5_UART_FBYTE1_FD2              *((volatile unsigned int*)(0x4270A308UL))\r
+#define bFM3_MFS5_UART_FBYTE1_FD3              *((volatile unsigned int*)(0x4270A30CUL))\r
+#define bFM3_MFS5_UART_FBYTE1_FD4              *((volatile unsigned int*)(0x4270A310UL))\r
+#define bFM3_MFS5_UART_FBYTE1_FD5              *((volatile unsigned int*)(0x4270A314UL))\r
+#define bFM3_MFS5_UART_FBYTE1_FD6              *((volatile unsigned int*)(0x4270A318UL))\r
+#define bFM3_MFS5_UART_FBYTE1_FD7              *((volatile unsigned int*)(0x4270A31CUL))\r
+#define bFM3_MFS5_UART_FBYTE2_FD8              *((volatile unsigned int*)(0x4270A320UL))\r
+#define bFM3_MFS5_UART_FBYTE2_FD9              *((volatile unsigned int*)(0x4270A324UL))\r
+#define bFM3_MFS5_UART_FBYTE2_FD10             *((volatile unsigned int*)(0x4270A328UL))\r
+#define bFM3_MFS5_UART_FBYTE2_FD11             *((volatile unsigned int*)(0x4270A32CUL))\r
+#define bFM3_MFS5_UART_FBYTE2_FD12             *((volatile unsigned int*)(0x4270A330UL))\r
+#define bFM3_MFS5_UART_FBYTE2_FD13             *((volatile unsigned int*)(0x4270A334UL))\r
+#define bFM3_MFS5_UART_FBYTE2_FD14             *((volatile unsigned int*)(0x4270A338UL))\r
+#define bFM3_MFS5_UART_FBYTE2_FD15             *((volatile unsigned int*)(0x4270A33CUL))\r
+\r
+/* UART synchronous channel 5 registers */\r
+#define bFM3_MFS5_CSIO_SMR_SOE                 *((volatile unsigned int*)(0x4270A000UL))\r
+#define bFM3_MFS5_CSIO_SMR_SCKE                *((volatile unsigned int*)(0x4270A004UL))\r
+#define bFM3_MFS5_CSIO_SMR_BDS                 *((volatile unsigned int*)(0x4270A008UL))\r
+#define bFM3_MFS5_CSIO_SMR_SCINV               *((volatile unsigned int*)(0x4270A00CUL))\r
+#define bFM3_MFS5_CSIO_SMR_WUCR                *((volatile unsigned int*)(0x4270A010UL))\r
+#define bFM3_MFS5_CSIO_SMR_MD0                 *((volatile unsigned int*)(0x4270A014UL))\r
+#define bFM3_MFS5_CSIO_SMR_MD1                 *((volatile unsigned int*)(0x4270A018UL))\r
+#define bFM3_MFS5_CSIO_SMR_MD2                 *((volatile unsigned int*)(0x4270A01CUL))\r
+#define bFM3_MFS5_CSIO_SCR_TXE                 *((volatile unsigned int*)(0x4270A020UL))\r
+#define bFM3_MFS5_CSIO_SCR_RXE                 *((volatile unsigned int*)(0x4270A024UL))\r
+#define bFM3_MFS5_CSIO_SCR_TBIE                *((volatile unsigned int*)(0x4270A028UL))\r
+#define bFM3_MFS5_CSIO_SCR_TIE                 *((volatile unsigned int*)(0x4270A02CUL))\r
+#define bFM3_MFS5_CSIO_SCR_RIE                 *((volatile unsigned int*)(0x4270A030UL))\r
+#define bFM3_MFS5_CSIO_SCR_SPI                 *((volatile unsigned int*)(0x4270A034UL))\r
+#define bFM3_MFS5_CSIO_SCR_MS                  *((volatile unsigned int*)(0x4270A038UL))\r
+#define bFM3_MFS5_CSIO_SCR_UPCL                *((volatile unsigned int*)(0x4270A03CUL))\r
+#define bFM3_MFS5_CSIO_ESCR_L0                 *((volatile unsigned int*)(0x4270A080UL))\r
+#define bFM3_MFS5_CSIO_ESCR_L1                 *((volatile unsigned int*)(0x4270A084UL))\r
+#define bFM3_MFS5_CSIO_ESCR_L2                 *((volatile unsigned int*)(0x4270A088UL))\r
+#define bFM3_MFS5_CSIO_ESCR_WT0                *((volatile unsigned int*)(0x4270A08CUL))\r
+#define bFM3_MFS5_CSIO_ESCR_WT1                *((volatile unsigned int*)(0x4270A090UL))\r
+#define bFM3_MFS5_CSIO_ESCR_SOP                *((volatile unsigned int*)(0x4270A09CUL))\r
+#define bFM3_MFS5_CSIO_SSR_TBI                 *((volatile unsigned int*)(0x4270A0A0UL))\r
+#define bFM3_MFS5_CSIO_SSR_TDRE                *((volatile unsigned int*)(0x4270A0A4UL))\r
+#define bFM3_MFS5_CSIO_SSR_RDRF                *((volatile unsigned int*)(0x4270A0A8UL))\r
+#define bFM3_MFS5_CSIO_SSR_ORE                 *((volatile unsigned int*)(0x4270A0ACUL))\r
+#define bFM3_MFS5_CSIO_SSR_REC                 *((volatile unsigned int*)(0x4270A0BCUL))\r
+#define bFM3_MFS5_CSIO_FCR_FE1                 *((volatile unsigned int*)(0x4270A280UL))\r
+#define bFM3_MFS5_CSIO_FCR_FE2                 *((volatile unsigned int*)(0x4270A284UL))\r
+#define bFM3_MFS5_CSIO_FCR_FCL1                *((volatile unsigned int*)(0x4270A288UL))\r
+#define bFM3_MFS5_CSIO_FCR_FCL2                *((volatile unsigned int*)(0x4270A28CUL))\r
+#define bFM3_MFS5_CSIO_FCR_FSET                *((volatile unsigned int*)(0x4270A290UL))\r
+#define bFM3_MFS5_CSIO_FCR_FLD                 *((volatile unsigned int*)(0x4270A294UL))\r
+#define bFM3_MFS5_CSIO_FCR_FLST                *((volatile unsigned int*)(0x4270A298UL))\r
+#define bFM3_MFS5_CSIO_FCR_FSEL                *((volatile unsigned int*)(0x4270A2A0UL))\r
+#define bFM3_MFS5_CSIO_FCR_FTIE                *((volatile unsigned int*)(0x4270A2A4UL))\r
+#define bFM3_MFS5_CSIO_FCR_FDRQ                *((volatile unsigned int*)(0x4270A2A8UL))\r
+#define bFM3_MFS5_CSIO_FCR_FRIE                *((volatile unsigned int*)(0x4270A2ACUL))\r
+#define bFM3_MFS5_CSIO_FCR_FLSTE               *((volatile unsigned int*)(0x4270A2B0UL))\r
+#define bFM3_MFS5_CSIO_FCR_FTST0               *((volatile unsigned int*)(0x4270A2B8UL))\r
+#define bFM3_MFS5_CSIO_FCR_FTST1               *((volatile unsigned int*)(0x4270A2BCUL))\r
+#define bFM3_MFS5_CSIO_FCR0_FE1                *((volatile unsigned int*)(0x4270A280UL))\r
+#define bFM3_MFS5_CSIO_FCR0_FE2                *((volatile unsigned int*)(0x4270A284UL))\r
+#define bFM3_MFS5_CSIO_FCR0_FCL1               *((volatile unsigned int*)(0x4270A288UL))\r
+#define bFM3_MFS5_CSIO_FCR0_FCL2               *((volatile unsigned int*)(0x4270A28CUL))\r
+#define bFM3_MFS5_CSIO_FCR0_FSET               *((volatile unsigned int*)(0x4270A290UL))\r
+#define bFM3_MFS5_CSIO_FCR0_FLD                *((volatile unsigned int*)(0x4270A294UL))\r
+#define bFM3_MFS5_CSIO_FCR0_FLST               *((volatile unsigned int*)(0x4270A298UL))\r
+#define bFM3_MFS5_CSIO_FCR1_FSEL               *((volatile unsigned int*)(0x4270A2A0UL))\r
+#define bFM3_MFS5_CSIO_FCR1_FTIE               *((volatile unsigned int*)(0x4270A2A4UL))\r
+#define bFM3_MFS5_CSIO_FCR1_FDRQ               *((volatile unsigned int*)(0x4270A2A8UL))\r
+#define bFM3_MFS5_CSIO_FCR1_FRIE               *((volatile unsigned int*)(0x4270A2ACUL))\r
+#define bFM3_MFS5_CSIO_FCR1_FLSTE              *((volatile unsigned int*)(0x4270A2B0UL))\r
+#define bFM3_MFS5_CSIO_FCR1_FTST0              *((volatile unsigned int*)(0x4270A2B8UL))\r
+#define bFM3_MFS5_CSIO_FCR1_FTST1              *((volatile unsigned int*)(0x4270A2BCUL))\r
+#define bFM3_MFS5_CSIO_FBYTE_FD0               *((volatile unsigned int*)(0x4270A300UL))\r
+#define bFM3_MFS5_CSIO_FBYTE_FD1               *((volatile unsigned int*)(0x4270A304UL))\r
+#define bFM3_MFS5_CSIO_FBYTE_FD2               *((volatile unsigned int*)(0x4270A308UL))\r
+#define bFM3_MFS5_CSIO_FBYTE_FD3               *((volatile unsigned int*)(0x4270A30CUL))\r
+#define bFM3_MFS5_CSIO_FBYTE_FD4               *((volatile unsigned int*)(0x4270A310UL))\r
+#define bFM3_MFS5_CSIO_FBYTE_FD5               *((volatile unsigned int*)(0x4270A314UL))\r
+#define bFM3_MFS5_CSIO_FBYTE_FD6               *((volatile unsigned int*)(0x4270A318UL))\r
+#define bFM3_MFS5_CSIO_FBYTE_FD7               *((volatile unsigned int*)(0x4270A31CUL))\r
+#define bFM3_MFS5_CSIO_FBYTE_FD8               *((volatile unsigned int*)(0x4270A320UL))\r
+#define bFM3_MFS5_CSIO_FBYTE_FD9               *((volatile unsigned int*)(0x4270A324UL))\r
+#define bFM3_MFS5_CSIO_FBYTE_FD10              *((volatile unsigned int*)(0x4270A328UL))\r
+#define bFM3_MFS5_CSIO_FBYTE_FD11              *((volatile unsigned int*)(0x4270A32CUL))\r
+#define bFM3_MFS5_CSIO_FBYTE_FD12              *((volatile unsigned int*)(0x4270A330UL))\r
+#define bFM3_MFS5_CSIO_FBYTE_FD13              *((volatile unsigned int*)(0x4270A334UL))\r
+#define bFM3_MFS5_CSIO_FBYTE_FD14              *((volatile unsigned int*)(0x4270A338UL))\r
+#define bFM3_MFS5_CSIO_FBYTE_FD15              *((volatile unsigned int*)(0x4270A33CUL))\r
+#define bFM3_MFS5_CSIO_FBYTE1_FD0              *((volatile unsigned int*)(0x4270A300UL))\r
+#define bFM3_MFS5_CSIO_FBYTE1_FD1              *((volatile unsigned int*)(0x4270A304UL))\r
+#define bFM3_MFS5_CSIO_FBYTE1_FD2              *((volatile unsigned int*)(0x4270A308UL))\r
+#define bFM3_MFS5_CSIO_FBYTE1_FD3              *((volatile unsigned int*)(0x4270A30CUL))\r
+#define bFM3_MFS5_CSIO_FBYTE1_FD4              *((volatile unsigned int*)(0x4270A310UL))\r
+#define bFM3_MFS5_CSIO_FBYTE1_FD5              *((volatile unsigned int*)(0x4270A314UL))\r
+#define bFM3_MFS5_CSIO_FBYTE1_FD6              *((volatile unsigned int*)(0x4270A318UL))\r
+#define bFM3_MFS5_CSIO_FBYTE1_FD7              *((volatile unsigned int*)(0x4270A31CUL))\r
+#define bFM3_MFS5_CSIO_FBYTE2_FD8              *((volatile unsigned int*)(0x4270A340UL))\r
+#define bFM3_MFS5_CSIO_FBYTE2_FD9              *((volatile unsigned int*)(0x4270A344UL))\r
+#define bFM3_MFS5_CSIO_FBYTE2_FD10             *((volatile unsigned int*)(0x4270A348UL))\r
+#define bFM3_MFS5_CSIO_FBYTE2_FD11             *((volatile unsigned int*)(0x4270A34CUL))\r
+#define bFM3_MFS5_CSIO_FBYTE2_FD12             *((volatile unsigned int*)(0x4270A350UL))\r
+#define bFM3_MFS5_CSIO_FBYTE2_FD13             *((volatile unsigned int*)(0x4270A354UL))\r
+#define bFM3_MFS5_CSIO_FBYTE2_FD14             *((volatile unsigned int*)(0x4270A358UL))\r
+#define bFM3_MFS5_CSIO_FBYTE2_FD15             *((volatile unsigned int*)(0x4270A35CUL))\r
+\r
+/* UART LIN channel 5 registers */\r
+#define bFM3_MFS5_LIN_SMR_SOE                  *((volatile unsigned int*)(0x4270A000UL))\r
+#define bFM3_MFS5_LIN_SMR_SBL                  *((volatile unsigned int*)(0x4270A00CUL))\r
+#define bFM3_MFS5_LIN_SMR_WUCR                 *((volatile unsigned int*)(0x4270A010UL))\r
+#define bFM3_MFS5_LIN_SMR_MD0                  *((volatile unsigned int*)(0x4270A014UL))\r
+#define bFM3_MFS5_LIN_SMR_MD1                  *((volatile unsigned int*)(0x4270A018UL))\r
+#define bFM3_MFS5_LIN_SMR_MD2                  *((volatile unsigned int*)(0x4270A01CUL))\r
+#define bFM3_MFS5_LIN_SCR_TXE                  *((volatile unsigned int*)(0x4270A020UL))\r
+#define bFM3_MFS5_LIN_SCR_RXE                  *((volatile unsigned int*)(0x4270A024UL))\r
+#define bFM3_MFS5_LIN_SCR_TBIE                 *((volatile unsigned int*)(0x4270A028UL))\r
+#define bFM3_MFS5_LIN_SCR_TIE                  *((volatile unsigned int*)(0x4270A02CUL))\r
+#define bFM3_MFS5_LIN_SCR_RIE                  *((volatile unsigned int*)(0x4270A030UL))\r
+#define bFM3_MFS5_LIN_SCR_LBR                  *((volatile unsigned int*)(0x4270A034UL))\r
+#define bFM3_MFS5_LIN_SCR_MS                   *((volatile unsigned int*)(0x4270A038UL))\r
+#define bFM3_MFS5_LIN_SCR_UPCL                 *((volatile unsigned int*)(0x4270A03CUL))\r
+#define bFM3_MFS5_LIN_ESCR_DEL0                *((volatile unsigned int*)(0x4270A080UL))\r
+#define bFM3_MFS5_LIN_ESCR_DEL1                *((volatile unsigned int*)(0x4270A084UL))\r
+#define bFM3_MFS5_LIN_ESCR_LBL0                *((volatile unsigned int*)(0x4270A088UL))\r
+#define bFM3_MFS5_LIN_ESCR_LBL1                *((volatile unsigned int*)(0x4270A08CUL))\r
+#define bFM3_MFS5_LIN_ESCR_LBIE                *((volatile unsigned int*)(0x4270A090UL))\r
+#define bFM3_MFS5_LIN_ESCR_ESBL                *((volatile unsigned int*)(0x4270A098UL))\r
+#define bFM3_MFS5_LIN_SSR_TBI                  *((volatile unsigned int*)(0x4270A0A0UL))\r
+#define bFM3_MFS5_LIN_SSR_TDRE                 *((volatile unsigned int*)(0x4270A0A4UL))\r
+#define bFM3_MFS5_LIN_SSR_RDRF                 *((volatile unsigned int*)(0x4270A0A8UL))\r
+#define bFM3_MFS5_LIN_SSR_ORE                  *((volatile unsigned int*)(0x4270A0ACUL))\r
+#define bFM3_MFS5_LIN_SSR_FRE                  *((volatile unsigned int*)(0x4270A0B0UL))\r
+#define bFM3_MFS5_LIN_SSR_LBD                  *((volatile unsigned int*)(0x4270A0B4UL))\r
+#define bFM3_MFS5_LIN_SSR_REC                  *((volatile unsigned int*)(0x4270A0BCUL))\r
+#define bFM3_MFS5_LIN_BGR_EXT                  *((volatile unsigned int*)(0x4270A1BCUL))\r
+#define bFM3_MFS5_LIN_BGR1_EXT                 *((volatile unsigned int*)(0x4270A1BCUL))\r
+#define bFM3_MFS5_LIN_FCR_FE1                  *((volatile unsigned int*)(0x4270A280UL))\r
+#define bFM3_MFS5_LIN_FCR_FE2                  *((volatile unsigned int*)(0x4270A284UL))\r
+#define bFM3_MFS5_LIN_FCR_FCL1                 *((volatile unsigned int*)(0x4270A288UL))\r
+#define bFM3_MFS5_LIN_FCR_FCL2                 *((volatile unsigned int*)(0x4270A28CUL))\r
+#define bFM3_MFS5_LIN_FCR_FSET                 *((volatile unsigned int*)(0x4270A290UL))\r
+#define bFM3_MFS5_LIN_FCR_FLD                  *((volatile unsigned int*)(0x4270A294UL))\r
+#define bFM3_MFS5_LIN_FCR_FLST                 *((volatile unsigned int*)(0x4270A298UL))\r
+#define bFM3_MFS5_LIN_FCR_FSEL                 *((volatile unsigned int*)(0x4270A2A0UL))\r
+#define bFM3_MFS5_LIN_FCR_FTIE                 *((volatile unsigned int*)(0x4270A2A4UL))\r
+#define bFM3_MFS5_LIN_FCR_FDRQ                 *((volatile unsigned int*)(0x4270A2A8UL))\r
+#define bFM3_MFS5_LIN_FCR_FRIE                 *((volatile unsigned int*)(0x4270A2ACUL))\r
+#define bFM3_MFS5_LIN_FCR_FLSTE                *((volatile unsigned int*)(0x4270A2B0UL))\r
+#define bFM3_MFS5_LIN_FCR_FTST0                *((volatile unsigned int*)(0x4270A2B8UL))\r
+#define bFM3_MFS5_LIN_FCR_FTST1                *((volatile unsigned int*)(0x4270A2BCUL))\r
+#define bFM3_MFS5_LIN_FCR0_FE1                 *((volatile unsigned int*)(0x4270A280UL))\r
+#define bFM3_MFS5_LIN_FCR0_FE2                 *((volatile unsigned int*)(0x4270A284UL))\r
+#define bFM3_MFS5_LIN_FCR0_FCL1                *((volatile unsigned int*)(0x4270A288UL))\r
+#define bFM3_MFS5_LIN_FCR0_FCL2                *((volatile unsigned int*)(0x4270A28CUL))\r
+#define bFM3_MFS5_LIN_FCR0_FSET                *((volatile unsigned int*)(0x4270A290UL))\r
+#define bFM3_MFS5_LIN_FCR0_FLD                 *((volatile unsigned int*)(0x4270A294UL))\r
+#define bFM3_MFS5_LIN_FCR0_FLST                *((volatile unsigned int*)(0x4270A298UL))\r
+#define bFM3_MFS5_LIN_FCR1_FSEL                *((volatile unsigned int*)(0x4270A2A0UL))\r
+#define bFM3_MFS5_LIN_FCR1_FTIE                *((volatile unsigned int*)(0x4270A2A4UL))\r
+#define bFM3_MFS5_LIN_FCR1_FDRQ                *((volatile unsigned int*)(0x4270A2A8UL))\r
+#define bFM3_MFS5_LIN_FCR1_FRIE                *((volatile unsigned int*)(0x4270A2ACUL))\r
+#define bFM3_MFS5_LIN_FCR1_FLSTE               *((volatile unsigned int*)(0x4270A2B0UL))\r
+#define bFM3_MFS5_LIN_FCR1_FTST0               *((volatile unsigned int*)(0x4270A2B8UL))\r
+#define bFM3_MFS5_LIN_FCR1_FTST1               *((volatile unsigned int*)(0x4270A2BCUL))\r
+#define bFM3_MFS5_LIN_FBYTE_FD0                *((volatile unsigned int*)(0x4270A300UL))\r
+#define bFM3_MFS5_LIN_FBYTE_FD1                *((volatile unsigned int*)(0x4270A304UL))\r
+#define bFM3_MFS5_LIN_FBYTE_FD2                *((volatile unsigned int*)(0x4270A308UL))\r
+#define bFM3_MFS5_LIN_FBYTE_FD3                *((volatile unsigned int*)(0x4270A30CUL))\r
+#define bFM3_MFS5_LIN_FBYTE_FD4                *((volatile unsigned int*)(0x4270A310UL))\r
+#define bFM3_MFS5_LIN_FBYTE_FD5                *((volatile unsigned int*)(0x4270A314UL))\r
+#define bFM3_MFS5_LIN_FBYTE_FD6                *((volatile unsigned int*)(0x4270A318UL))\r
+#define bFM3_MFS5_LIN_FBYTE_FD7                *((volatile unsigned int*)(0x4270A31CUL))\r
+#define bFM3_MFS5_LIN_FBYTE_FD8                *((volatile unsigned int*)(0x4270A320UL))\r
+#define bFM3_MFS5_LIN_FBYTE_FD9                *((volatile unsigned int*)(0x4270A324UL))\r
+#define bFM3_MFS5_LIN_FBYTE_FD10               *((volatile unsigned int*)(0x4270A328UL))\r
+#define bFM3_MFS5_LIN_FBYTE_FD11               *((volatile unsigned int*)(0x4270A32CUL))\r
+#define bFM3_MFS5_LIN_FBYTE_FD12               *((volatile unsigned int*)(0x4270A330UL))\r
+#define bFM3_MFS5_LIN_FBYTE_FD13               *((volatile unsigned int*)(0x4270A334UL))\r
+#define bFM3_MFS5_LIN_FBYTE_FD14               *((volatile unsigned int*)(0x4270A338UL))\r
+#define bFM3_MFS5_LIN_FBYTE_FD15               *((volatile unsigned int*)(0x4270A33CUL))\r
+#define bFM3_MFS5_LIN_FBYTE1_FD0               *((volatile unsigned int*)(0x4270A300UL))\r
+#define bFM3_MFS5_LIN_FBYTE1_FD1               *((volatile unsigned int*)(0x4270A304UL))\r
+#define bFM3_MFS5_LIN_FBYTE1_FD2               *((volatile unsigned int*)(0x4270A308UL))\r
+#define bFM3_MFS5_LIN_FBYTE1_FD3               *((volatile unsigned int*)(0x4270A30CUL))\r
+#define bFM3_MFS5_LIN_FBYTE1_FD4               *((volatile unsigned int*)(0x4270A310UL))\r
+#define bFM3_MFS5_LIN_FBYTE1_FD5               *((volatile unsigned int*)(0x4270A314UL))\r
+#define bFM3_MFS5_LIN_FBYTE1_FD6               *((volatile unsigned int*)(0x4270A318UL))\r
+#define bFM3_MFS5_LIN_FBYTE1_FD7               *((volatile unsigned int*)(0x4270A31CUL))\r
+#define bFM3_MFS5_LIN_FBYTE2_FD8               *((volatile unsigned int*)(0x4270A340UL))\r
+#define bFM3_MFS5_LIN_FBYTE2_FD9               *((volatile unsigned int*)(0x4270A344UL))\r
+#define bFM3_MFS5_LIN_FBYTE2_FD10              *((volatile unsigned int*)(0x4270A348UL))\r
+#define bFM3_MFS5_LIN_FBYTE2_FD11              *((volatile unsigned int*)(0x4270A34CUL))\r
+#define bFM3_MFS5_LIN_FBYTE2_FD12              *((volatile unsigned int*)(0x4270A350UL))\r
+#define bFM3_MFS5_LIN_FBYTE2_FD13              *((volatile unsigned int*)(0x4270A354UL))\r
+#define bFM3_MFS5_LIN_FBYTE2_FD14              *((volatile unsigned int*)(0x4270A358UL))\r
+#define bFM3_MFS5_LIN_FBYTE2_FD15              *((volatile unsigned int*)(0x4270A35CUL))\r
+\r
+/* I2C channel 5 registers */\r
+#define bFM3_MFS5_I2C_SMR_ITST0                *((volatile unsigned int*)(0x4270A000UL))\r
+#define bFM3_MFS5_I2C_SMR_ITST1                *((volatile unsigned int*)(0x4270A004UL))\r
+#define bFM3_MFS5_I2C_SMR_TIE                  *((volatile unsigned int*)(0x4270A008UL))\r
+#define bFM3_MFS5_I2C_SMR_RIE                  *((volatile unsigned int*)(0x4270A00CUL))\r
+#define bFM3_MFS5_I2C_SMR_WUCR                 *((volatile unsigned int*)(0x4270A010UL))\r
+#define bFM3_MFS5_I2C_SMR_MD0                  *((volatile unsigned int*)(0x4270A014UL))\r
+#define bFM3_MFS5_I2C_SMR_MD1                  *((volatile unsigned int*)(0x4270A018UL))\r
+#define bFM3_MFS5_I2C_SMR_MD2                  *((volatile unsigned int*)(0x4270A01CUL))\r
+#define bFM3_MFS5_I2C_IBCR_INT                 *((volatile unsigned int*)(0x4270A020UL))\r
+#define bFM3_MFS5_I2C_IBCR_BER                 *((volatile unsigned int*)(0x4270A024UL))\r
+#define bFM3_MFS5_I2C_IBCR_INTE                *((volatile unsigned int*)(0x4270A028UL))\r
+#define bFM3_MFS5_I2C_IBCR_CNDE                *((volatile unsigned int*)(0x4270A02CUL))\r
+#define bFM3_MFS5_I2C_IBCR_WSEL                *((volatile unsigned int*)(0x4270A030UL))\r
+#define bFM3_MFS5_I2C_IBCR_ACKE                *((volatile unsigned int*)(0x4270A034UL))\r
+#define bFM3_MFS5_I2C_IBCR_ACT                 *((volatile unsigned int*)(0x4270A038UL))\r
+#define bFM3_MFS5_I2C_IBCR_SCC                 *((volatile unsigned int*)(0x4270A038UL))\r
+#define bFM3_MFS5_I2C_IBCR_MSS                 *((volatile unsigned int*)(0x4270A03CUL))\r
+#define bFM3_MFS5_I2C_IBSR_BB                  *((volatile unsigned int*)(0x4270A080UL))\r
+#define bFM3_MFS5_I2C_IBSR_SPC                 *((volatile unsigned int*)(0x4270A084UL))\r
+#define bFM3_MFS5_I2C_IBSR_RSC                 *((volatile unsigned int*)(0x4270A088UL))\r
+#define bFM3_MFS5_I2C_IBSR_AL                  *((volatile unsigned int*)(0x4270A08CUL))\r
+#define bFM3_MFS5_I2C_IBSR_TRX                 *((volatile unsigned int*)(0x4270A090UL))\r
+#define bFM3_MFS5_I2C_IBSR_RSA                 *((volatile unsigned int*)(0x4270A094UL))\r
+#define bFM3_MFS5_I2C_IBSR_RACK                *((volatile unsigned int*)(0x4270A098UL))\r
+#define bFM3_MFS5_I2C_IBSR_FBT                 *((volatile unsigned int*)(0x4270A09CUL))\r
+#define bFM3_MFS5_I2C_SSR_TBI                  *((volatile unsigned int*)(0x4270A0A0UL))\r
+#define bFM3_MFS5_I2C_SSR_TDRE                 *((volatile unsigned int*)(0x4270A0A4UL))\r
+#define bFM3_MFS5_I2C_SSR_RDRF                 *((volatile unsigned int*)(0x4270A0A8UL))\r
+#define bFM3_MFS5_I2C_SSR_ORE                  *((volatile unsigned int*)(0x4270A0ACUL))\r
+#define bFM3_MFS5_I2C_SSR_TBIE                 *((volatile unsigned int*)(0x4270A0B0UL))\r
+#define bFM3_MFS5_I2C_SSR_DMA                  *((volatile unsigned int*)(0x4270A0B4UL))\r
+#define bFM3_MFS5_I2C_SSR_TSET                 *((volatile unsigned int*)(0x4270A0B8UL))\r
+#define bFM3_MFS5_I2C_SSR_REC                  *((volatile unsigned int*)(0x4270A0BCUL))\r
+#define bFM3_MFS5_I2C_ISBA_SA0                 *((volatile unsigned int*)(0x4270A200UL))\r
+#define bFM3_MFS5_I2C_ISBA_SA1                 *((volatile unsigned int*)(0x4270A204UL))\r
+#define bFM3_MFS5_I2C_ISBA_SA2                 *((volatile unsigned int*)(0x4270A208UL))\r
+#define bFM3_MFS5_I2C_ISBA_SA3                 *((volatile unsigned int*)(0x4270A20CUL))\r
+#define bFM3_MFS5_I2C_ISBA_SA4                 *((volatile unsigned int*)(0x4270A210UL))\r
+#define bFM3_MFS5_I2C_ISBA_SA5                 *((volatile unsigned int*)(0x4270A214UL))\r
+#define bFM3_MFS5_I2C_ISBA_SA6                 *((volatile unsigned int*)(0x4270A218UL))\r
+#define bFM3_MFS5_I2C_ISBA_SAEN                *((volatile unsigned int*)(0x4270A21CUL))\r
+#define bFM3_MFS5_I2C_ISMK_SM0                 *((volatile unsigned int*)(0x4270A220UL))\r
+#define bFM3_MFS5_I2C_ISMK_SM1                 *((volatile unsigned int*)(0x4270A224UL))\r
+#define bFM3_MFS5_I2C_ISMK_SM2                 *((volatile unsigned int*)(0x4270A228UL))\r
+#define bFM3_MFS5_I2C_ISMK_SM3                 *((volatile unsigned int*)(0x4270A22CUL))\r
+#define bFM3_MFS5_I2C_ISMK_SM4                 *((volatile unsigned int*)(0x4270A230UL))\r
+#define bFM3_MFS5_I2C_ISMK_SM5                 *((volatile unsigned int*)(0x4270A234UL))\r
+#define bFM3_MFS5_I2C_ISMK_SM6                 *((volatile unsigned int*)(0x4270A238UL))\r
+#define bFM3_MFS5_I2C_ISMK_EN                  *((volatile unsigned int*)(0x4270A23CUL))\r
+#define bFM3_MFS5_I2C_FCR_FE1                  *((volatile unsigned int*)(0x4270A280UL))\r
+#define bFM3_MFS5_I2C_FCR_FE2                  *((volatile unsigned int*)(0x4270A284UL))\r
+#define bFM3_MFS5_I2C_FCR_FCL1                 *((volatile unsigned int*)(0x4270A288UL))\r
+#define bFM3_MFS5_I2C_FCR_FCL2                 *((volatile unsigned int*)(0x4270A28CUL))\r
+#define bFM3_MFS5_I2C_FCR_FSET                 *((volatile unsigned int*)(0x4270A290UL))\r
+#define bFM3_MFS5_I2C_FCR_FLD                  *((volatile unsigned int*)(0x4270A294UL))\r
+#define bFM3_MFS5_I2C_FCR_FLST                 *((volatile unsigned int*)(0x4270A298UL))\r
+#define bFM3_MFS5_I2C_FCR_FSEL                 *((volatile unsigned int*)(0x4270A2A0UL))\r
+#define bFM3_MFS5_I2C_FCR_FTIE                 *((volatile unsigned int*)(0x4270A2A4UL))\r
+#define bFM3_MFS5_I2C_FCR_FDRQ                 *((volatile unsigned int*)(0x4270A2A8UL))\r
+#define bFM3_MFS5_I2C_FCR_FRIE                 *((volatile unsigned int*)(0x4270A2ACUL))\r
+#define bFM3_MFS5_I2C_FCR_FLSTE                *((volatile unsigned int*)(0x4270A2B0UL))\r
+#define bFM3_MFS5_I2C_FCR_FTST0                *((volatile unsigned int*)(0x4270A2B8UL))\r
+#define bFM3_MFS5_I2C_FCR_FTST1                *((volatile unsigned int*)(0x4270A2BCUL))\r
+#define bFM3_MFS5_I2C_FCR0_FE1                 *((volatile unsigned int*)(0x4270A280UL))\r
+#define bFM3_MFS5_I2C_FCR0_FE2                 *((volatile unsigned int*)(0x4270A284UL))\r
+#define bFM3_MFS5_I2C_FCR0_FCL1                *((volatile unsigned int*)(0x4270A288UL))\r
+#define bFM3_MFS5_I2C_FCR0_FCL2                *((volatile unsigned int*)(0x4270A28CUL))\r
+#define bFM3_MFS5_I2C_FCR0_FSET                *((volatile unsigned int*)(0x4270A290UL))\r
+#define bFM3_MFS5_I2C_FCR0_FLD                 *((volatile unsigned int*)(0x4270A294UL))\r
+#define bFM3_MFS5_I2C_FCR0_FLST                *((volatile unsigned int*)(0x4270A298UL))\r
+#define bFM3_MFS5_I2C_FCR1_FSEL                *((volatile unsigned int*)(0x4270A2A0UL))\r
+#define bFM3_MFS5_I2C_FCR1_FTIE                *((volatile unsigned int*)(0x4270A2A4UL))\r
+#define bFM3_MFS5_I2C_FCR1_FDRQ                *((volatile unsigned int*)(0x4270A2A8UL))\r
+#define bFM3_MFS5_I2C_FCR1_FRIE                *((volatile unsigned int*)(0x4270A2ACUL))\r
+#define bFM3_MFS5_I2C_FCR1_FLSTE               *((volatile unsigned int*)(0x4270A2B0UL))\r
+#define bFM3_MFS5_I2C_FCR1_FTST0               *((volatile unsigned int*)(0x4270A2B8UL))\r
+#define bFM3_MFS5_I2C_FCR1_FTST1               *((volatile unsigned int*)(0x4270A2BCUL))\r
+#define bFM3_MFS5_I2C_FBYTE_FD0                *((volatile unsigned int*)(0x4270A300UL))\r
+#define bFM3_MFS5_I2C_FBYTE_FD1                *((volatile unsigned int*)(0x4270A304UL))\r
+#define bFM3_MFS5_I2C_FBYTE_FD2                *((volatile unsigned int*)(0x4270A308UL))\r
+#define bFM3_MFS5_I2C_FBYTE_FD3                *((volatile unsigned int*)(0x4270A30CUL))\r
+#define bFM3_MFS5_I2C_FBYTE_FD4                *((volatile unsigned int*)(0x4270A310UL))\r
+#define bFM3_MFS5_I2C_FBYTE_FD5                *((volatile unsigned int*)(0x4270A314UL))\r
+#define bFM3_MFS5_I2C_FBYTE_FD6                *((volatile unsigned int*)(0x4270A318UL))\r
+#define bFM3_MFS5_I2C_FBYTE_FD7                *((volatile unsigned int*)(0x4270A31CUL))\r
+#define bFM3_MFS5_I2C_FBYTE_FD8                *((volatile unsigned int*)(0x4270A320UL))\r
+#define bFM3_MFS5_I2C_FBYTE_FD9                *((volatile unsigned int*)(0x4270A324UL))\r
+#define bFM3_MFS5_I2C_FBYTE_FD10               *((volatile unsigned int*)(0x4270A328UL))\r
+#define bFM3_MFS5_I2C_FBYTE_FD11               *((volatile unsigned int*)(0x4270A32CUL))\r
+#define bFM3_MFS5_I2C_FBYTE_FD12               *((volatile unsigned int*)(0x4270A330UL))\r
+#define bFM3_MFS5_I2C_FBYTE_FD13               *((volatile unsigned int*)(0x4270A334UL))\r
+#define bFM3_MFS5_I2C_FBYTE_FD14               *((volatile unsigned int*)(0x4270A338UL))\r
+#define bFM3_MFS5_I2C_FBYTE_FD15               *((volatile unsigned int*)(0x4270A33CUL))\r
+#define bFM3_MFS5_I2C_FBYTE1_FD0               *((volatile unsigned int*)(0x4270A300UL))\r
+#define bFM3_MFS5_I2C_FBYTE1_FD1               *((volatile unsigned int*)(0x4270A304UL))\r
+#define bFM3_MFS5_I2C_FBYTE1_FD2               *((volatile unsigned int*)(0x4270A308UL))\r
+#define bFM3_MFS5_I2C_FBYTE1_FD3               *((volatile unsigned int*)(0x4270A30CUL))\r
+#define bFM3_MFS5_I2C_FBYTE1_FD4               *((volatile unsigned int*)(0x4270A310UL))\r
+#define bFM3_MFS5_I2C_FBYTE1_FD5               *((volatile unsigned int*)(0x4270A314UL))\r
+#define bFM3_MFS5_I2C_FBYTE1_FD6               *((volatile unsigned int*)(0x4270A318UL))\r
+#define bFM3_MFS5_I2C_FBYTE1_FD7               *((volatile unsigned int*)(0x4270A31CUL))\r
+#define bFM3_MFS5_I2C_FBYTE2_FD8               *((volatile unsigned int*)(0x4270A340UL))\r
+#define bFM3_MFS5_I2C_FBYTE2_FD9               *((volatile unsigned int*)(0x4270A344UL))\r
+#define bFM3_MFS5_I2C_FBYTE2_FD10              *((volatile unsigned int*)(0x4270A348UL))\r
+#define bFM3_MFS5_I2C_FBYTE2_FD11              *((volatile unsigned int*)(0x4270A34CUL))\r
+#define bFM3_MFS5_I2C_FBYTE2_FD12              *((volatile unsigned int*)(0x4270A350UL))\r
+#define bFM3_MFS5_I2C_FBYTE2_FD13              *((volatile unsigned int*)(0x4270A354UL))\r
+#define bFM3_MFS5_I2C_FBYTE2_FD14              *((volatile unsigned int*)(0x4270A358UL))\r
+#define bFM3_MFS5_I2C_FBYTE2_FD15              *((volatile unsigned int*)(0x4270A35CUL))\r
+\r
+/* UART asynchronous channel 6 registers */\r
+#define bFM3_MFS6_UART_SMR_SOE                 *((volatile unsigned int*)(0x4270C000UL))\r
+#define bFM3_MFS6_UART_SMR_BDS                 *((volatile unsigned int*)(0x4270C008UL))\r
+#define bFM3_MFS6_UART_SMR_SBL                 *((volatile unsigned int*)(0x4270C00CUL))\r
+#define bFM3_MFS6_UART_SMR_WUCR                *((volatile unsigned int*)(0x4270C010UL))\r
+#define bFM3_MFS6_UART_SMR_MD0                 *((volatile unsigned int*)(0x4270C014UL))\r
+#define bFM3_MFS6_UART_SMR_MD1                 *((volatile unsigned int*)(0x4270C018UL))\r
+#define bFM3_MFS6_UART_SMR_MD2                 *((volatile unsigned int*)(0x4270C01CUL))\r
+#define bFM3_MFS6_UART_SCR_TXE                 *((volatile unsigned int*)(0x4270C020UL))\r
+#define bFM3_MFS6_UART_SCR_RXE                 *((volatile unsigned int*)(0x4270C024UL))\r
+#define bFM3_MFS6_UART_SCR_TBIE                *((volatile unsigned int*)(0x4270C028UL))\r
+#define bFM3_MFS6_UART_SCR_TIE                 *((volatile unsigned int*)(0x4270C02CUL))\r
+#define bFM3_MFS6_UART_SCR_RIE                 *((volatile unsigned int*)(0x4270C030UL))\r
+#define bFM3_MFS6_UART_SCR_UPCL                *((volatile unsigned int*)(0x4270C03CUL))\r
+#define bFM3_MFS6_UART_ESCR_L0                 *((volatile unsigned int*)(0x4270C080UL))\r
+#define bFM3_MFS6_UART_ESCR_L1                 *((volatile unsigned int*)(0x4270C084UL))\r
+#define bFM3_MFS6_UART_ESCR_L2                 *((volatile unsigned int*)(0x4270C088UL))\r
+#define bFM3_MFS6_UART_ESCR_P                  *((volatile unsigned int*)(0x4270C08CUL))\r
+#define bFM3_MFS6_UART_ESCR_PEN                *((volatile unsigned int*)(0x4270C090UL))\r
+#define bFM3_MFS6_UART_ESCR_INV                *((volatile unsigned int*)(0x4270C094UL))\r
+#define bFM3_MFS6_UART_ESCR_ESBL               *((volatile unsigned int*)(0x4270C098UL))\r
+#define bFM3_MFS6_UART_ESCR_FLWEN              *((volatile unsigned int*)(0x4270C09CUL))\r
+#define bFM3_MFS6_UART_SSR_TBI                 *((volatile unsigned int*)(0x4270C0A0UL))\r
+#define bFM3_MFS6_UART_SSR_TDRE                *((volatile unsigned int*)(0x4270C0A4UL))\r
+#define bFM3_MFS6_UART_SSR_RDRF                *((volatile unsigned int*)(0x4270C0A8UL))\r
+#define bFM3_MFS6_UART_SSR_ORE                 *((volatile unsigned int*)(0x4270C0ACUL))\r
+#define bFM3_MFS6_UART_SSR_FRE                 *((volatile unsigned int*)(0x4270C0B0UL))\r
+#define bFM3_MFS6_UART_SSR_PE                  *((volatile unsigned int*)(0x4270C0B4UL))\r
+#define bFM3_MFS6_UART_SSR_REC                 *((volatile unsigned int*)(0x4270C0BCUL))\r
+#define bFM3_MFS6_UART_RDR_AD                  *((volatile unsigned int*)(0x4270C120UL))\r
+#define bFM3_MFS6_UART_TDR_AD                  *((volatile unsigned int*)(0x4270C120UL))\r
+#define bFM3_MFS6_UART_BGR_EXT                 *((volatile unsigned int*)(0x4270C1BCUL))\r
+#define bFM3_MFS6_UART_BGR1_EXT                *((volatile unsigned int*)(0x4270C1BCUL))\r
+#define bFM3_MFS6_UART_FCR_FE1                 *((volatile unsigned int*)(0x4270C280UL))\r
+#define bFM3_MFS6_UART_FCR_FE2                 *((volatile unsigned int*)(0x4270C284UL))\r
+#define bFM3_MFS6_UART_FCR_FCL1                *((volatile unsigned int*)(0x4270C288UL))\r
+#define bFM3_MFS6_UART_FCR_FCL2                *((volatile unsigned int*)(0x4270C28CUL))\r
+#define bFM3_MFS6_UART_FCR_FSET                *((volatile unsigned int*)(0x4270C290UL))\r
+#define bFM3_MFS6_UART_FCR_FLD                 *((volatile unsigned int*)(0x4270C294UL))\r
+#define bFM3_MFS6_UART_FCR_FLST                *((volatile unsigned int*)(0x4270C298UL))\r
+#define bFM3_MFS6_UART_FCR_FSEL                *((volatile unsigned int*)(0x4270C2A0UL))\r
+#define bFM3_MFS6_UART_FCR_FTIE                *((volatile unsigned int*)(0x4270C2A4UL))\r
+#define bFM3_MFS6_UART_FCR_FDRQ                *((volatile unsigned int*)(0x4270C2A8UL))\r
+#define bFM3_MFS6_UART_FCR_FRIE                *((volatile unsigned int*)(0x4270C2ACUL))\r
+#define bFM3_MFS6_UART_FCR_FLSTE               *((volatile unsigned int*)(0x4270C2B0UL))\r
+#define bFM3_MFS6_UART_FCR_FTST0               *((volatile unsigned int*)(0x4270C2B8UL))\r
+#define bFM3_MFS6_UART_FCR_FTST1               *((volatile unsigned int*)(0x4270C2BCUL))\r
+#define bFM3_MFS6_UART_FCR0_FE1                *((volatile unsigned int*)(0x4270C280UL))\r
+#define bFM3_MFS6_UART_FCR0_FE2                *((volatile unsigned int*)(0x4270C284UL))\r
+#define bFM3_MFS6_UART_FCR0_FCL1               *((volatile unsigned int*)(0x4270C288UL))\r
+#define bFM3_MFS6_UART_FCR0_FCL2               *((volatile unsigned int*)(0x4270C28CUL))\r
+#define bFM3_MFS6_UART_FCR0_FSET               *((volatile unsigned int*)(0x4270C290UL))\r
+#define bFM3_MFS6_UART_FCR0_FLD                *((volatile unsigned int*)(0x4270C294UL))\r
+#define bFM3_MFS6_UART_FCR0_FLST               *((volatile unsigned int*)(0x4270C298UL))\r
+#define bFM3_MFS6_UART_FCR1_FSEL               *((volatile unsigned int*)(0x4270C2A0UL))\r
+#define bFM3_MFS6_UART_FCR1_FTIE               *((volatile unsigned int*)(0x4270C2A4UL))\r
+#define bFM3_MFS6_UART_FCR1_FDRQ               *((volatile unsigned int*)(0x4270C2A8UL))\r
+#define bFM3_MFS6_UART_FCR1_FRIE               *((volatile unsigned int*)(0x4270C2ACUL))\r
+#define bFM3_MFS6_UART_FCR1_FLSTE              *((volatile unsigned int*)(0x4270C2B0UL))\r
+#define bFM3_MFS6_UART_FCR1_FTST0              *((volatile unsigned int*)(0x4270C2B8UL))\r
+#define bFM3_MFS6_UART_FCR1_FTST1              *((volatile unsigned int*)(0x4270C2BCUL))\r
+#define bFM3_MFS6_UART_FBYTE_FD0               *((volatile unsigned int*)(0x4270C300UL))\r
+#define bFM3_MFS6_UART_FBYTE_FD1               *((volatile unsigned int*)(0x4270C304UL))\r
+#define bFM3_MFS6_UART_FBYTE_FD2               *((volatile unsigned int*)(0x4270C308UL))\r
+#define bFM3_MFS6_UART_FBYTE_FD3               *((volatile unsigned int*)(0x4270C30CUL))\r
+#define bFM3_MFS6_UART_FBYTE_FD4               *((volatile unsigned int*)(0x4270C310UL))\r
+#define bFM3_MFS6_UART_FBYTE_FD5               *((volatile unsigned int*)(0x4270C314UL))\r
+#define bFM3_MFS6_UART_FBYTE_FD6               *((volatile unsigned int*)(0x4270C318UL))\r
+#define bFM3_MFS6_UART_FBYTE_FD7               *((volatile unsigned int*)(0x4270C31CUL))\r
+#define bFM3_MFS6_UART_FBYTE_FD8               *((volatile unsigned int*)(0x4270C320UL))\r
+#define bFM3_MFS6_UART_FBYTE_FD9               *((volatile unsigned int*)(0x4270C324UL))\r
+#define bFM3_MFS6_UART_FBYTE_FD10              *((volatile unsigned int*)(0x4270C328UL))\r
+#define bFM3_MFS6_UART_FBYTE_FD11              *((volatile unsigned int*)(0x4270C32CUL))\r
+#define bFM3_MFS6_UART_FBYTE_FD12              *((volatile unsigned int*)(0x4270C330UL))\r
+#define bFM3_MFS6_UART_FBYTE_FD13              *((volatile unsigned int*)(0x4270C334UL))\r
+#define bFM3_MFS6_UART_FBYTE_FD14              *((volatile unsigned int*)(0x4270C338UL))\r
+#define bFM3_MFS6_UART_FBYTE_FD15              *((volatile unsigned int*)(0x4270C33CUL))\r
+#define bFM3_MFS6_UART_FBYTE1_FD0              *((volatile unsigned int*)(0x4270C300UL))\r
+#define bFM3_MFS6_UART_FBYTE1_FD1              *((volatile unsigned int*)(0x4270C304UL))\r
+#define bFM3_MFS6_UART_FBYTE1_FD2              *((volatile unsigned int*)(0x4270C308UL))\r
+#define bFM3_MFS6_UART_FBYTE1_FD3              *((volatile unsigned int*)(0x4270C30CUL))\r
+#define bFM3_MFS6_UART_FBYTE1_FD4              *((volatile unsigned int*)(0x4270C310UL))\r
+#define bFM3_MFS6_UART_FBYTE1_FD5              *((volatile unsigned int*)(0x4270C314UL))\r
+#define bFM3_MFS6_UART_FBYTE1_FD6              *((volatile unsigned int*)(0x4270C318UL))\r
+#define bFM3_MFS6_UART_FBYTE1_FD7              *((volatile unsigned int*)(0x4270C31CUL))\r
+#define bFM3_MFS6_UART_FBYTE2_FD8              *((volatile unsigned int*)(0x4270C320UL))\r
+#define bFM3_MFS6_UART_FBYTE2_FD9              *((volatile unsigned int*)(0x4270C324UL))\r
+#define bFM3_MFS6_UART_FBYTE2_FD10             *((volatile unsigned int*)(0x4270C328UL))\r
+#define bFM3_MFS6_UART_FBYTE2_FD11             *((volatile unsigned int*)(0x4270C32CUL))\r
+#define bFM3_MFS6_UART_FBYTE2_FD12             *((volatile unsigned int*)(0x4270C330UL))\r
+#define bFM3_MFS6_UART_FBYTE2_FD13             *((volatile unsigned int*)(0x4270C334UL))\r
+#define bFM3_MFS6_UART_FBYTE2_FD14             *((volatile unsigned int*)(0x4270C338UL))\r
+#define bFM3_MFS6_UART_FBYTE2_FD15             *((volatile unsigned int*)(0x4270C33CUL))\r
+\r
+/* UART synchronous channel 6 registers */\r
+#define bFM3_MFS6_CSIO_SMR_SOE                 *((volatile unsigned int*)(0x4270C000UL))\r
+#define bFM3_MFS6_CSIO_SMR_SCKE                *((volatile unsigned int*)(0x4270C004UL))\r
+#define bFM3_MFS6_CSIO_SMR_BDS                 *((volatile unsigned int*)(0x4270C008UL))\r
+#define bFM3_MFS6_CSIO_SMR_SCINV               *((volatile unsigned int*)(0x4270C00CUL))\r
+#define bFM3_MFS6_CSIO_SMR_WUCR                *((volatile unsigned int*)(0x4270C010UL))\r
+#define bFM3_MFS6_CSIO_SMR_MD0                 *((volatile unsigned int*)(0x4270C014UL))\r
+#define bFM3_MFS6_CSIO_SMR_MD1                 *((volatile unsigned int*)(0x4270C018UL))\r
+#define bFM3_MFS6_CSIO_SMR_MD2                 *((volatile unsigned int*)(0x4270C01CUL))\r
+#define bFM3_MFS6_CSIO_SCR_TXE                 *((volatile unsigned int*)(0x4270C020UL))\r
+#define bFM3_MFS6_CSIO_SCR_RXE                 *((volatile unsigned int*)(0x4270C024UL))\r
+#define bFM3_MFS6_CSIO_SCR_TBIE                *((volatile unsigned int*)(0x4270C028UL))\r
+#define bFM3_MFS6_CSIO_SCR_TIE                 *((volatile unsigned int*)(0x4270C02CUL))\r
+#define bFM3_MFS6_CSIO_SCR_RIE                 *((volatile unsigned int*)(0x4270C030UL))\r
+#define bFM3_MFS6_CSIO_SCR_SPI                 *((volatile unsigned int*)(0x4270C034UL))\r
+#define bFM3_MFS6_CSIO_SCR_MS                  *((volatile unsigned int*)(0x4270C038UL))\r
+#define bFM3_MFS6_CSIO_SCR_UPCL                *((volatile unsigned int*)(0x4270C03CUL))\r
+#define bFM3_MFS6_CSIO_ESCR_L0                 *((volatile unsigned int*)(0x4270C080UL))\r
+#define bFM3_MFS6_CSIO_ESCR_L1                 *((volatile unsigned int*)(0x4270C084UL))\r
+#define bFM3_MFS6_CSIO_ESCR_L2                 *((volatile unsigned int*)(0x4270C088UL))\r
+#define bFM3_MFS6_CSIO_ESCR_WT0                *((volatile unsigned int*)(0x4270C08CUL))\r
+#define bFM3_MFS6_CSIO_ESCR_WT1                *((volatile unsigned int*)(0x4270C090UL))\r
+#define bFM3_MFS6_CSIO_ESCR_SOP                *((volatile unsigned int*)(0x4270C09CUL))\r
+#define bFM3_MFS6_CSIO_SSR_TBI                 *((volatile unsigned int*)(0x4270C0A0UL))\r
+#define bFM3_MFS6_CSIO_SSR_TDRE                *((volatile unsigned int*)(0x4270C0A4UL))\r
+#define bFM3_MFS6_CSIO_SSR_RDRF                *((volatile unsigned int*)(0x4270C0A8UL))\r
+#define bFM3_MFS6_CSIO_SSR_ORE                 *((volatile unsigned int*)(0x4270C0ACUL))\r
+#define bFM3_MFS6_CSIO_SSR_REC                 *((volatile unsigned int*)(0x4270C0BCUL))\r
+#define bFM3_MFS6_CSIO_FCR_FE1                 *((volatile unsigned int*)(0x4270C280UL))\r
+#define bFM3_MFS6_CSIO_FCR_FE2                 *((volatile unsigned int*)(0x4270C284UL))\r
+#define bFM3_MFS6_CSIO_FCR_FCL1                *((volatile unsigned int*)(0x4270C288UL))\r
+#define bFM3_MFS6_CSIO_FCR_FCL2                *((volatile unsigned int*)(0x4270C28CUL))\r
+#define bFM3_MFS6_CSIO_FCR_FSET                *((volatile unsigned int*)(0x4270C290UL))\r
+#define bFM3_MFS6_CSIO_FCR_FLD                 *((volatile unsigned int*)(0x4270C294UL))\r
+#define bFM3_MFS6_CSIO_FCR_FLST                *((volatile unsigned int*)(0x4270C298UL))\r
+#define bFM3_MFS6_CSIO_FCR_FSEL                *((volatile unsigned int*)(0x4270C2A0UL))\r
+#define bFM3_MFS6_CSIO_FCR_FTIE                *((volatile unsigned int*)(0x4270C2A4UL))\r
+#define bFM3_MFS6_CSIO_FCR_FDRQ                *((volatile unsigned int*)(0x4270C2A8UL))\r
+#define bFM3_MFS6_CSIO_FCR_FRIE                *((volatile unsigned int*)(0x4270C2ACUL))\r
+#define bFM3_MFS6_CSIO_FCR_FLSTE               *((volatile unsigned int*)(0x4270C2B0UL))\r
+#define bFM3_MFS6_CSIO_FCR_FTST0               *((volatile unsigned int*)(0x4270C2B8UL))\r
+#define bFM3_MFS6_CSIO_FCR_FTST1               *((volatile unsigned int*)(0x4270C2BCUL))\r
+#define bFM3_MFS6_CSIO_FCR0_FE1                *((volatile unsigned int*)(0x4270C280UL))\r
+#define bFM3_MFS6_CSIO_FCR0_FE2                *((volatile unsigned int*)(0x4270C284UL))\r
+#define bFM3_MFS6_CSIO_FCR0_FCL1               *((volatile unsigned int*)(0x4270C288UL))\r
+#define bFM3_MFS6_CSIO_FCR0_FCL2               *((volatile unsigned int*)(0x4270C28CUL))\r
+#define bFM3_MFS6_CSIO_FCR0_FSET               *((volatile unsigned int*)(0x4270C290UL))\r
+#define bFM3_MFS6_CSIO_FCR0_FLD                *((volatile unsigned int*)(0x4270C294UL))\r
+#define bFM3_MFS6_CSIO_FCR0_FLST               *((volatile unsigned int*)(0x4270C298UL))\r
+#define bFM3_MFS6_CSIO_FCR1_FSEL               *((volatile unsigned int*)(0x4270C2A0UL))\r
+#define bFM3_MFS6_CSIO_FCR1_FTIE               *((volatile unsigned int*)(0x4270C2A4UL))\r
+#define bFM3_MFS6_CSIO_FCR1_FDRQ               *((volatile unsigned int*)(0x4270C2A8UL))\r
+#define bFM3_MFS6_CSIO_FCR1_FRIE               *((volatile unsigned int*)(0x4270C2ACUL))\r
+#define bFM3_MFS6_CSIO_FCR1_FLSTE              *((volatile unsigned int*)(0x4270C2B0UL))\r
+#define bFM3_MFS6_CSIO_FCR1_FTST0              *((volatile unsigned int*)(0x4270C2B8UL))\r
+#define bFM3_MFS6_CSIO_FCR1_FTST1              *((volatile unsigned int*)(0x4270C2BCUL))\r
+#define bFM3_MFS6_CSIO_FBYTE_FD0               *((volatile unsigned int*)(0x4270C300UL))\r
+#define bFM3_MFS6_CSIO_FBYTE_FD1               *((volatile unsigned int*)(0x4270C304UL))\r
+#define bFM3_MFS6_CSIO_FBYTE_FD2               *((volatile unsigned int*)(0x4270C308UL))\r
+#define bFM3_MFS6_CSIO_FBYTE_FD3               *((volatile unsigned int*)(0x4270C30CUL))\r
+#define bFM3_MFS6_CSIO_FBYTE_FD4               *((volatile unsigned int*)(0x4270C310UL))\r
+#define bFM3_MFS6_CSIO_FBYTE_FD5               *((volatile unsigned int*)(0x4270C314UL))\r
+#define bFM3_MFS6_CSIO_FBYTE_FD6               *((volatile unsigned int*)(0x4270C318UL))\r
+#define bFM3_MFS6_CSIO_FBYTE_FD7               *((volatile unsigned int*)(0x4270C31CUL))\r
+#define bFM3_MFS6_CSIO_FBYTE_FD8               *((volatile unsigned int*)(0x4270C320UL))\r
+#define bFM3_MFS6_CSIO_FBYTE_FD9               *((volatile unsigned int*)(0x4270C324UL))\r
+#define bFM3_MFS6_CSIO_FBYTE_FD10              *((volatile unsigned int*)(0x4270C328UL))\r
+#define bFM3_MFS6_CSIO_FBYTE_FD11              *((volatile unsigned int*)(0x4270C32CUL))\r
+#define bFM3_MFS6_CSIO_FBYTE_FD12              *((volatile unsigned int*)(0x4270C330UL))\r
+#define bFM3_MFS6_CSIO_FBYTE_FD13              *((volatile unsigned int*)(0x4270C334UL))\r
+#define bFM3_MFS6_CSIO_FBYTE_FD14              *((volatile unsigned int*)(0x4270C338UL))\r
+#define bFM3_MFS6_CSIO_FBYTE_FD15              *((volatile unsigned int*)(0x4270C33CUL))\r
+#define bFM3_MFS6_CSIO_FBYTE1_FD0              *((volatile unsigned int*)(0x4270C300UL))\r
+#define bFM3_MFS6_CSIO_FBYTE1_FD1              *((volatile unsigned int*)(0x4270C304UL))\r
+#define bFM3_MFS6_CSIO_FBYTE1_FD2              *((volatile unsigned int*)(0x4270C308UL))\r
+#define bFM3_MFS6_CSIO_FBYTE1_FD3              *((volatile unsigned int*)(0x4270C30CUL))\r
+#define bFM3_MFS6_CSIO_FBYTE1_FD4              *((volatile unsigned int*)(0x4270C310UL))\r
+#define bFM3_MFS6_CSIO_FBYTE1_FD5              *((volatile unsigned int*)(0x4270C314UL))\r
+#define bFM3_MFS6_CSIO_FBYTE1_FD6              *((volatile unsigned int*)(0x4270C318UL))\r
+#define bFM3_MFS6_CSIO_FBYTE1_FD7              *((volatile unsigned int*)(0x4270C31CUL))\r
+#define bFM3_MFS6_CSIO_FBYTE2_FD8              *((volatile unsigned int*)(0x4270C340UL))\r
+#define bFM3_MFS6_CSIO_FBYTE2_FD9              *((volatile unsigned int*)(0x4270C344UL))\r
+#define bFM3_MFS6_CSIO_FBYTE2_FD10             *((volatile unsigned int*)(0x4270C348UL))\r
+#define bFM3_MFS6_CSIO_FBYTE2_FD11             *((volatile unsigned int*)(0x4270C34CUL))\r
+#define bFM3_MFS6_CSIO_FBYTE2_FD12             *((volatile unsigned int*)(0x4270C350UL))\r
+#define bFM3_MFS6_CSIO_FBYTE2_FD13             *((volatile unsigned int*)(0x4270C354UL))\r
+#define bFM3_MFS6_CSIO_FBYTE2_FD14             *((volatile unsigned int*)(0x4270C358UL))\r
+#define bFM3_MFS6_CSIO_FBYTE2_FD15             *((volatile unsigned int*)(0x4270C35CUL))\r
+\r
+/* UART LIN channel 6 registers */\r
+#define bFM3_MFS6_LIN_SMR_SOE                  *((volatile unsigned int*)(0x4270C000UL))\r
+#define bFM3_MFS6_LIN_SMR_SBL                  *((volatile unsigned int*)(0x4270C00CUL))\r
+#define bFM3_MFS6_LIN_SMR_WUCR                 *((volatile unsigned int*)(0x4270C010UL))\r
+#define bFM3_MFS6_LIN_SMR_MD0                  *((volatile unsigned int*)(0x4270C014UL))\r
+#define bFM3_MFS6_LIN_SMR_MD1                  *((volatile unsigned int*)(0x4270C018UL))\r
+#define bFM3_MFS6_LIN_SMR_MD2                  *((volatile unsigned int*)(0x4270C01CUL))\r
+#define bFM3_MFS6_LIN_SCR_TXE                  *((volatile unsigned int*)(0x4270C020UL))\r
+#define bFM3_MFS6_LIN_SCR_RXE                  *((volatile unsigned int*)(0x4270C024UL))\r
+#define bFM3_MFS6_LIN_SCR_TBIE                 *((volatile unsigned int*)(0x4270C028UL))\r
+#define bFM3_MFS6_LIN_SCR_TIE                  *((volatile unsigned int*)(0x4270C02CUL))\r
+#define bFM3_MFS6_LIN_SCR_RIE                  *((volatile unsigned int*)(0x4270C030UL))\r
+#define bFM3_MFS6_LIN_SCR_LBR                  *((volatile unsigned int*)(0x4270C034UL))\r
+#define bFM3_MFS6_LIN_SCR_MS                   *((volatile unsigned int*)(0x4270C038UL))\r
+#define bFM3_MFS6_LIN_SCR_UPCL                 *((volatile unsigned int*)(0x4270C03CUL))\r
+#define bFM3_MFS6_LIN_ESCR_DEL0                *((volatile unsigned int*)(0x4270C080UL))\r
+#define bFM3_MFS6_LIN_ESCR_DEL1                *((volatile unsigned int*)(0x4270C084UL))\r
+#define bFM3_MFS6_LIN_ESCR_LBL0                *((volatile unsigned int*)(0x4270C088UL))\r
+#define bFM3_MFS6_LIN_ESCR_LBL1                *((volatile unsigned int*)(0x4270C08CUL))\r
+#define bFM3_MFS6_LIN_ESCR_LBIE                *((volatile unsigned int*)(0x4270C090UL))\r
+#define bFM3_MFS6_LIN_ESCR_ESBL                *((volatile unsigned int*)(0x4270C098UL))\r
+#define bFM3_MFS6_LIN_SSR_TBI                  *((volatile unsigned int*)(0x4270C0A0UL))\r
+#define bFM3_MFS6_LIN_SSR_TDRE                 *((volatile unsigned int*)(0x4270C0A4UL))\r
+#define bFM3_MFS6_LIN_SSR_RDRF                 *((volatile unsigned int*)(0x4270C0A8UL))\r
+#define bFM3_MFS6_LIN_SSR_ORE                  *((volatile unsigned int*)(0x4270C0ACUL))\r
+#define bFM3_MFS6_LIN_SSR_FRE                  *((volatile unsigned int*)(0x4270C0B0UL))\r
+#define bFM3_MFS6_LIN_SSR_LBD                  *((volatile unsigned int*)(0x4270C0B4UL))\r
+#define bFM3_MFS6_LIN_SSR_REC                  *((volatile unsigned int*)(0x4270C0BCUL))\r
+#define bFM3_MFS6_LIN_BGR_EXT                  *((volatile unsigned int*)(0x4270C1BCUL))\r
+#define bFM3_MFS6_LIN_BGR1_EXT                 *((volatile unsigned int*)(0x4270C1BCUL))\r
+#define bFM3_MFS6_LIN_FCR_FE1                  *((volatile unsigned int*)(0x4270C280UL))\r
+#define bFM3_MFS6_LIN_FCR_FE2                  *((volatile unsigned int*)(0x4270C284UL))\r
+#define bFM3_MFS6_LIN_FCR_FCL1                 *((volatile unsigned int*)(0x4270C288UL))\r
+#define bFM3_MFS6_LIN_FCR_FCL2                 *((volatile unsigned int*)(0x4270C28CUL))\r
+#define bFM3_MFS6_LIN_FCR_FSET                 *((volatile unsigned int*)(0x4270C290UL))\r
+#define bFM3_MFS6_LIN_FCR_FLD                  *((volatile unsigned int*)(0x4270C294UL))\r
+#define bFM3_MFS6_LIN_FCR_FLST                 *((volatile unsigned int*)(0x4270C298UL))\r
+#define bFM3_MFS6_LIN_FCR_FSEL                 *((volatile unsigned int*)(0x4270C2A0UL))\r
+#define bFM3_MFS6_LIN_FCR_FTIE                 *((volatile unsigned int*)(0x4270C2A4UL))\r
+#define bFM3_MFS6_LIN_FCR_FDRQ                 *((volatile unsigned int*)(0x4270C2A8UL))\r
+#define bFM3_MFS6_LIN_FCR_FRIE                 *((volatile unsigned int*)(0x4270C2ACUL))\r
+#define bFM3_MFS6_LIN_FCR_FLSTE                *((volatile unsigned int*)(0x4270C2B0UL))\r
+#define bFM3_MFS6_LIN_FCR_FTST0                *((volatile unsigned int*)(0x4270C2B8UL))\r
+#define bFM3_MFS6_LIN_FCR_FTST1                *((volatile unsigned int*)(0x4270C2BCUL))\r
+#define bFM3_MFS6_LIN_FCR0_FE1                 *((volatile unsigned int*)(0x4270C280UL))\r
+#define bFM3_MFS6_LIN_FCR0_FE2                 *((volatile unsigned int*)(0x4270C284UL))\r
+#define bFM3_MFS6_LIN_FCR0_FCL1                *((volatile unsigned int*)(0x4270C288UL))\r
+#define bFM3_MFS6_LIN_FCR0_FCL2                *((volatile unsigned int*)(0x4270C28CUL))\r
+#define bFM3_MFS6_LIN_FCR0_FSET                *((volatile unsigned int*)(0x4270C290UL))\r
+#define bFM3_MFS6_LIN_FCR0_FLD                 *((volatile unsigned int*)(0x4270C294UL))\r
+#define bFM3_MFS6_LIN_FCR0_FLST                *((volatile unsigned int*)(0x4270C298UL))\r
+#define bFM3_MFS6_LIN_FCR1_FSEL                *((volatile unsigned int*)(0x4270C2A0UL))\r
+#define bFM3_MFS6_LIN_FCR1_FTIE                *((volatile unsigned int*)(0x4270C2A4UL))\r
+#define bFM3_MFS6_LIN_FCR1_FDRQ                *((volatile unsigned int*)(0x4270C2A8UL))\r
+#define bFM3_MFS6_LIN_FCR1_FRIE                *((volatile unsigned int*)(0x4270C2ACUL))\r
+#define bFM3_MFS6_LIN_FCR1_FLSTE               *((volatile unsigned int*)(0x4270C2B0UL))\r
+#define bFM3_MFS6_LIN_FCR1_FTST0               *((volatile unsigned int*)(0x4270C2B8UL))\r
+#define bFM3_MFS6_LIN_FCR1_FTST1               *((volatile unsigned int*)(0x4270C2BCUL))\r
+#define bFM3_MFS6_LIN_FBYTE_FD0                *((volatile unsigned int*)(0x4270C300UL))\r
+#define bFM3_MFS6_LIN_FBYTE_FD1                *((volatile unsigned int*)(0x4270C304UL))\r
+#define bFM3_MFS6_LIN_FBYTE_FD2                *((volatile unsigned int*)(0x4270C308UL))\r
+#define bFM3_MFS6_LIN_FBYTE_FD3                *((volatile unsigned int*)(0x4270C30CUL))\r
+#define bFM3_MFS6_LIN_FBYTE_FD4                *((volatile unsigned int*)(0x4270C310UL))\r
+#define bFM3_MFS6_LIN_FBYTE_FD5                *((volatile unsigned int*)(0x4270C314UL))\r
+#define bFM3_MFS6_LIN_FBYTE_FD6                *((volatile unsigned int*)(0x4270C318UL))\r
+#define bFM3_MFS6_LIN_FBYTE_FD7                *((volatile unsigned int*)(0x4270C31CUL))\r
+#define bFM3_MFS6_LIN_FBYTE_FD8                *((volatile unsigned int*)(0x4270C320UL))\r
+#define bFM3_MFS6_LIN_FBYTE_FD9                *((volatile unsigned int*)(0x4270C324UL))\r
+#define bFM3_MFS6_LIN_FBYTE_FD10               *((volatile unsigned int*)(0x4270C328UL))\r
+#define bFM3_MFS6_LIN_FBYTE_FD11               *((volatile unsigned int*)(0x4270C32CUL))\r
+#define bFM3_MFS6_LIN_FBYTE_FD12               *((volatile unsigned int*)(0x4270C330UL))\r
+#define bFM3_MFS6_LIN_FBYTE_FD13               *((volatile unsigned int*)(0x4270C334UL))\r
+#define bFM3_MFS6_LIN_FBYTE_FD14               *((volatile unsigned int*)(0x4270C338UL))\r
+#define bFM3_MFS6_LIN_FBYTE_FD15               *((volatile unsigned int*)(0x4270C33CUL))\r
+#define bFM3_MFS6_LIN_FBYTE1_FD0               *((volatile unsigned int*)(0x4270C300UL))\r
+#define bFM3_MFS6_LIN_FBYTE1_FD1               *((volatile unsigned int*)(0x4270C304UL))\r
+#define bFM3_MFS6_LIN_FBYTE1_FD2               *((volatile unsigned int*)(0x4270C308UL))\r
+#define bFM3_MFS6_LIN_FBYTE1_FD3               *((volatile unsigned int*)(0x4270C30CUL))\r
+#define bFM3_MFS6_LIN_FBYTE1_FD4               *((volatile unsigned int*)(0x4270C310UL))\r
+#define bFM3_MFS6_LIN_FBYTE1_FD5               *((volatile unsigned int*)(0x4270C314UL))\r
+#define bFM3_MFS6_LIN_FBYTE1_FD6               *((volatile unsigned int*)(0x4270C318UL))\r
+#define bFM3_MFS6_LIN_FBYTE1_FD7               *((volatile unsigned int*)(0x4270C31CUL))\r
+#define bFM3_MFS6_LIN_FBYTE2_FD8               *((volatile unsigned int*)(0x4270C340UL))\r
+#define bFM3_MFS6_LIN_FBYTE2_FD9               *((volatile unsigned int*)(0x4270C344UL))\r
+#define bFM3_MFS6_LIN_FBYTE2_FD10              *((volatile unsigned int*)(0x4270C348UL))\r
+#define bFM3_MFS6_LIN_FBYTE2_FD11              *((volatile unsigned int*)(0x4270C34CUL))\r
+#define bFM3_MFS6_LIN_FBYTE2_FD12              *((volatile unsigned int*)(0x4270C350UL))\r
+#define bFM3_MFS6_LIN_FBYTE2_FD13              *((volatile unsigned int*)(0x4270C354UL))\r
+#define bFM3_MFS6_LIN_FBYTE2_FD14              *((volatile unsigned int*)(0x4270C358UL))\r
+#define bFM3_MFS6_LIN_FBYTE2_FD15              *((volatile unsigned int*)(0x4270C35CUL))\r
+\r
+/* I2C channel 6 registers */\r
+#define bFM3_MFS6_I2C_SMR_ITST0                *((volatile unsigned int*)(0x4270C000UL))\r
+#define bFM3_MFS6_I2C_SMR_ITST1                *((volatile unsigned int*)(0x4270C004UL))\r
+#define bFM3_MFS6_I2C_SMR_TIE                  *((volatile unsigned int*)(0x4270C008UL))\r
+#define bFM3_MFS6_I2C_SMR_RIE                  *((volatile unsigned int*)(0x4270C00CUL))\r
+#define bFM3_MFS6_I2C_SMR_WUCR                 *((volatile unsigned int*)(0x4270C010UL))\r
+#define bFM3_MFS6_I2C_SMR_MD0                  *((volatile unsigned int*)(0x4270C014UL))\r
+#define bFM3_MFS6_I2C_SMR_MD1                  *((volatile unsigned int*)(0x4270C018UL))\r
+#define bFM3_MFS6_I2C_SMR_MD2                  *((volatile unsigned int*)(0x4270C01CUL))\r
+#define bFM3_MFS6_I2C_IBCR_INT                 *((volatile unsigned int*)(0x4270C020UL))\r
+#define bFM3_MFS6_I2C_IBCR_BER                 *((volatile unsigned int*)(0x4270C024UL))\r
+#define bFM3_MFS6_I2C_IBCR_INTE                *((volatile unsigned int*)(0x4270C028UL))\r
+#define bFM3_MFS6_I2C_IBCR_CNDE                *((volatile unsigned int*)(0x4270C02CUL))\r
+#define bFM3_MFS6_I2C_IBCR_WSEL                *((volatile unsigned int*)(0x4270C030UL))\r
+#define bFM3_MFS6_I2C_IBCR_ACKE                *((volatile unsigned int*)(0x4270C034UL))\r
+#define bFM3_MFS6_I2C_IBCR_ACT                 *((volatile unsigned int*)(0x4270C038UL))\r
+#define bFM3_MFS6_I2C_IBCR_SCC                 *((volatile unsigned int*)(0x4270C038UL))\r
+#define bFM3_MFS6_I2C_IBCR_MSS                 *((volatile unsigned int*)(0x4270C03CUL))\r
+#define bFM3_MFS6_I2C_IBSR_BB                  *((volatile unsigned int*)(0x4270C080UL))\r
+#define bFM3_MFS6_I2C_IBSR_SPC                 *((volatile unsigned int*)(0x4270C084UL))\r
+#define bFM3_MFS6_I2C_IBSR_RSC                 *((volatile unsigned int*)(0x4270C088UL))\r
+#define bFM3_MFS6_I2C_IBSR_AL                  *((volatile unsigned int*)(0x4270C08CUL))\r
+#define bFM3_MFS6_I2C_IBSR_TRX                 *((volatile unsigned int*)(0x4270C090UL))\r
+#define bFM3_MFS6_I2C_IBSR_RSA                 *((volatile unsigned int*)(0x4270C094UL))\r
+#define bFM3_MFS6_I2C_IBSR_RACK                *((volatile unsigned int*)(0x4270C098UL))\r
+#define bFM3_MFS6_I2C_IBSR_FBT                 *((volatile unsigned int*)(0x4270C09CUL))\r
+#define bFM3_MFS6_I2C_SSR_TBI                  *((volatile unsigned int*)(0x4270C0A0UL))\r
+#define bFM3_MFS6_I2C_SSR_TDRE                 *((volatile unsigned int*)(0x4270C0A4UL))\r
+#define bFM3_MFS6_I2C_SSR_RDRF                 *((volatile unsigned int*)(0x4270C0A8UL))\r
+#define bFM3_MFS6_I2C_SSR_ORE                  *((volatile unsigned int*)(0x4270C0ACUL))\r
+#define bFM3_MFS6_I2C_SSR_TBIE                 *((volatile unsigned int*)(0x4270C0B0UL))\r
+#define bFM3_MFS6_I2C_SSR_DMA                  *((volatile unsigned int*)(0x4270C0B4UL))\r
+#define bFM3_MFS6_I2C_SSR_TSET                 *((volatile unsigned int*)(0x4270C0B8UL))\r
+#define bFM3_MFS6_I2C_SSR_REC                  *((volatile unsigned int*)(0x4270C0BCUL))\r
+#define bFM3_MFS6_I2C_ISBA_SA0                 *((volatile unsigned int*)(0x4270C200UL))\r
+#define bFM3_MFS6_I2C_ISBA_SA1                 *((volatile unsigned int*)(0x4270C204UL))\r
+#define bFM3_MFS6_I2C_ISBA_SA2                 *((volatile unsigned int*)(0x4270C208UL))\r
+#define bFM3_MFS6_I2C_ISBA_SA3                 *((volatile unsigned int*)(0x4270C20CUL))\r
+#define bFM3_MFS6_I2C_ISBA_SA4                 *((volatile unsigned int*)(0x4270C210UL))\r
+#define bFM3_MFS6_I2C_ISBA_SA5                 *((volatile unsigned int*)(0x4270C214UL))\r
+#define bFM3_MFS6_I2C_ISBA_SA6                 *((volatile unsigned int*)(0x4270C218UL))\r
+#define bFM3_MFS6_I2C_ISBA_SAEN                *((volatile unsigned int*)(0x4270C21CUL))\r
+#define bFM3_MFS6_I2C_ISMK_SM0                 *((volatile unsigned int*)(0x4270C220UL))\r
+#define bFM3_MFS6_I2C_ISMK_SM1                 *((volatile unsigned int*)(0x4270C224UL))\r
+#define bFM3_MFS6_I2C_ISMK_SM2                 *((volatile unsigned int*)(0x4270C228UL))\r
+#define bFM3_MFS6_I2C_ISMK_SM3                 *((volatile unsigned int*)(0x4270C22CUL))\r
+#define bFM3_MFS6_I2C_ISMK_SM4                 *((volatile unsigned int*)(0x4270C230UL))\r
+#define bFM3_MFS6_I2C_ISMK_SM5                 *((volatile unsigned int*)(0x4270C234UL))\r
+#define bFM3_MFS6_I2C_ISMK_SM6                 *((volatile unsigned int*)(0x4270C238UL))\r
+#define bFM3_MFS6_I2C_ISMK_EN                  *((volatile unsigned int*)(0x4270C23CUL))\r
+#define bFM3_MFS6_I2C_FCR_FE1                  *((volatile unsigned int*)(0x4270C280UL))\r
+#define bFM3_MFS6_I2C_FCR_FE2                  *((volatile unsigned int*)(0x4270C284UL))\r
+#define bFM3_MFS6_I2C_FCR_FCL1                 *((volatile unsigned int*)(0x4270C288UL))\r
+#define bFM3_MFS6_I2C_FCR_FCL2                 *((volatile unsigned int*)(0x4270C28CUL))\r
+#define bFM3_MFS6_I2C_FCR_FSET                 *((volatile unsigned int*)(0x4270C290UL))\r
+#define bFM3_MFS6_I2C_FCR_FLD                  *((volatile unsigned int*)(0x4270C294UL))\r
+#define bFM3_MFS6_I2C_FCR_FLST                 *((volatile unsigned int*)(0x4270C298UL))\r
+#define bFM3_MFS6_I2C_FCR_FSEL                 *((volatile unsigned int*)(0x4270C2A0UL))\r
+#define bFM3_MFS6_I2C_FCR_FTIE                 *((volatile unsigned int*)(0x4270C2A4UL))\r
+#define bFM3_MFS6_I2C_FCR_FDRQ                 *((volatile unsigned int*)(0x4270C2A8UL))\r
+#define bFM3_MFS6_I2C_FCR_FRIE                 *((volatile unsigned int*)(0x4270C2ACUL))\r
+#define bFM3_MFS6_I2C_FCR_FLSTE                *((volatile unsigned int*)(0x4270C2B0UL))\r
+#define bFM3_MFS6_I2C_FCR_FTST0                *((volatile unsigned int*)(0x4270C2B8UL))\r
+#define bFM3_MFS6_I2C_FCR_FTST1                *((volatile unsigned int*)(0x4270C2BCUL))\r
+#define bFM3_MFS6_I2C_FCR0_FE1                 *((volatile unsigned int*)(0x4270C280UL))\r
+#define bFM3_MFS6_I2C_FCR0_FE2                 *((volatile unsigned int*)(0x4270C284UL))\r
+#define bFM3_MFS6_I2C_FCR0_FCL1                *((volatile unsigned int*)(0x4270C288UL))\r
+#define bFM3_MFS6_I2C_FCR0_FCL2                *((volatile unsigned int*)(0x4270C28CUL))\r
+#define bFM3_MFS6_I2C_FCR0_FSET                *((volatile unsigned int*)(0x4270C290UL))\r
+#define bFM3_MFS6_I2C_FCR0_FLD                 *((volatile unsigned int*)(0x4270C294UL))\r
+#define bFM3_MFS6_I2C_FCR0_FLST                *((volatile unsigned int*)(0x4270C298UL))\r
+#define bFM3_MFS6_I2C_FCR1_FSEL                *((volatile unsigned int*)(0x4270C2A0UL))\r
+#define bFM3_MFS6_I2C_FCR1_FTIE                *((volatile unsigned int*)(0x4270C2A4UL))\r
+#define bFM3_MFS6_I2C_FCR1_FDRQ                *((volatile unsigned int*)(0x4270C2A8UL))\r
+#define bFM3_MFS6_I2C_FCR1_FRIE                *((volatile unsigned int*)(0x4270C2ACUL))\r
+#define bFM3_MFS6_I2C_FCR1_FLSTE               *((volatile unsigned int*)(0x4270C2B0UL))\r
+#define bFM3_MFS6_I2C_FCR1_FTST0               *((volatile unsigned int*)(0x4270C2B8UL))\r
+#define bFM3_MFS6_I2C_FCR1_FTST1               *((volatile unsigned int*)(0x4270C2BCUL))\r
+#define bFM3_MFS6_I2C_FBYTE_FD0                *((volatile unsigned int*)(0x4270C300UL))\r
+#define bFM3_MFS6_I2C_FBYTE_FD1                *((volatile unsigned int*)(0x4270C304UL))\r
+#define bFM3_MFS6_I2C_FBYTE_FD2                *((volatile unsigned int*)(0x4270C308UL))\r
+#define bFM3_MFS6_I2C_FBYTE_FD3                *((volatile unsigned int*)(0x4270C30CUL))\r
+#define bFM3_MFS6_I2C_FBYTE_FD4                *((volatile unsigned int*)(0x4270C310UL))\r
+#define bFM3_MFS6_I2C_FBYTE_FD5                *((volatile unsigned int*)(0x4270C314UL))\r
+#define bFM3_MFS6_I2C_FBYTE_FD6                *((volatile unsigned int*)(0x4270C318UL))\r
+#define bFM3_MFS6_I2C_FBYTE_FD7                *((volatile unsigned int*)(0x4270C31CUL))\r
+#define bFM3_MFS6_I2C_FBYTE_FD8                *((volatile unsigned int*)(0x4270C320UL))\r
+#define bFM3_MFS6_I2C_FBYTE_FD9                *((volatile unsigned int*)(0x4270C324UL))\r
+#define bFM3_MFS6_I2C_FBYTE_FD10               *((volatile unsigned int*)(0x4270C328UL))\r
+#define bFM3_MFS6_I2C_FBYTE_FD11               *((volatile unsigned int*)(0x4270C32CUL))\r
+#define bFM3_MFS6_I2C_FBYTE_FD12               *((volatile unsigned int*)(0x4270C330UL))\r
+#define bFM3_MFS6_I2C_FBYTE_FD13               *((volatile unsigned int*)(0x4270C334UL))\r
+#define bFM3_MFS6_I2C_FBYTE_FD14               *((volatile unsigned int*)(0x4270C338UL))\r
+#define bFM3_MFS6_I2C_FBYTE_FD15               *((volatile unsigned int*)(0x4270C33CUL))\r
+#define bFM3_MFS6_I2C_FBYTE1_FD0               *((volatile unsigned int*)(0x4270C300UL))\r
+#define bFM3_MFS6_I2C_FBYTE1_FD1               *((volatile unsigned int*)(0x4270C304UL))\r
+#define bFM3_MFS6_I2C_FBYTE1_FD2               *((volatile unsigned int*)(0x4270C308UL))\r
+#define bFM3_MFS6_I2C_FBYTE1_FD3               *((volatile unsigned int*)(0x4270C30CUL))\r
+#define bFM3_MFS6_I2C_FBYTE1_FD4               *((volatile unsigned int*)(0x4270C310UL))\r
+#define bFM3_MFS6_I2C_FBYTE1_FD5               *((volatile unsigned int*)(0x4270C314UL))\r
+#define bFM3_MFS6_I2C_FBYTE1_FD6               *((volatile unsigned int*)(0x4270C318UL))\r
+#define bFM3_MFS6_I2C_FBYTE1_FD7               *((volatile unsigned int*)(0x4270C31CUL))\r
+#define bFM3_MFS6_I2C_FBYTE2_FD8               *((volatile unsigned int*)(0x4270C340UL))\r
+#define bFM3_MFS6_I2C_FBYTE2_FD9               *((volatile unsigned int*)(0x4270C344UL))\r
+#define bFM3_MFS6_I2C_FBYTE2_FD10              *((volatile unsigned int*)(0x4270C348UL))\r
+#define bFM3_MFS6_I2C_FBYTE2_FD11              *((volatile unsigned int*)(0x4270C34CUL))\r
+#define bFM3_MFS6_I2C_FBYTE2_FD12              *((volatile unsigned int*)(0x4270C350UL))\r
+#define bFM3_MFS6_I2C_FBYTE2_FD13              *((volatile unsigned int*)(0x4270C354UL))\r
+#define bFM3_MFS6_I2C_FBYTE2_FD14              *((volatile unsigned int*)(0x4270C358UL))\r
+#define bFM3_MFS6_I2C_FBYTE2_FD15              *((volatile unsigned int*)(0x4270C35CUL))\r
+\r
+/* UART asynchronous channel 7 registers */\r
+#define bFM3_MFS7_UART_SMR_SOE                 *((volatile unsigned int*)(0x4270E000UL))\r
+#define bFM3_MFS7_UART_SMR_BDS                 *((volatile unsigned int*)(0x4270E008UL))\r
+#define bFM3_MFS7_UART_SMR_SBL                 *((volatile unsigned int*)(0x4270E00CUL))\r
+#define bFM3_MFS7_UART_SMR_WUCR                *((volatile unsigned int*)(0x4270E010UL))\r
+#define bFM3_MFS7_UART_SMR_MD0                 *((volatile unsigned int*)(0x4270E014UL))\r
+#define bFM3_MFS7_UART_SMR_MD1                 *((volatile unsigned int*)(0x4270E018UL))\r
+#define bFM3_MFS7_UART_SMR_MD2                 *((volatile unsigned int*)(0x4270E01CUL))\r
+#define bFM3_MFS7_UART_SCR_TXE                 *((volatile unsigned int*)(0x4270E020UL))\r
+#define bFM3_MFS7_UART_SCR_RXE                 *((volatile unsigned int*)(0x4270E024UL))\r
+#define bFM3_MFS7_UART_SCR_TBIE                *((volatile unsigned int*)(0x4270E028UL))\r
+#define bFM3_MFS7_UART_SCR_TIE                 *((volatile unsigned int*)(0x4270E02CUL))\r
+#define bFM3_MFS7_UART_SCR_RIE                 *((volatile unsigned int*)(0x4270E030UL))\r
+#define bFM3_MFS7_UART_SCR_UPCL                *((volatile unsigned int*)(0x4270E03CUL))\r
+#define bFM3_MFS7_UART_ESCR_L0                 *((volatile unsigned int*)(0x4270E080UL))\r
+#define bFM3_MFS7_UART_ESCR_L1                 *((volatile unsigned int*)(0x4270E084UL))\r
+#define bFM3_MFS7_UART_ESCR_L2                 *((volatile unsigned int*)(0x4270E088UL))\r
+#define bFM3_MFS7_UART_ESCR_P                  *((volatile unsigned int*)(0x4270E08CUL))\r
+#define bFM3_MFS7_UART_ESCR_PEN                *((volatile unsigned int*)(0x4270E090UL))\r
+#define bFM3_MFS7_UART_ESCR_INV                *((volatile unsigned int*)(0x4270E094UL))\r
+#define bFM3_MFS7_UART_ESCR_ESBL               *((volatile unsigned int*)(0x4270E098UL))\r
+#define bFM3_MFS7_UART_ESCR_FLWEN              *((volatile unsigned int*)(0x4270E09CUL))\r
+#define bFM3_MFS7_UART_SSR_TBI                 *((volatile unsigned int*)(0x4270E0A0UL))\r
+#define bFM3_MFS7_UART_SSR_TDRE                *((volatile unsigned int*)(0x4270E0A4UL))\r
+#define bFM3_MFS7_UART_SSR_RDRF                *((volatile unsigned int*)(0x4270E0A8UL))\r
+#define bFM3_MFS7_UART_SSR_ORE                 *((volatile unsigned int*)(0x4270E0ACUL))\r
+#define bFM3_MFS7_UART_SSR_FRE                 *((volatile unsigned int*)(0x4270E0B0UL))\r
+#define bFM3_MFS7_UART_SSR_PE                  *((volatile unsigned int*)(0x4270E0B4UL))\r
+#define bFM3_MFS7_UART_SSR_REC                 *((volatile unsigned int*)(0x4270E0BCUL))\r
+#define bFM3_MFS7_UART_RDR_AD                  *((volatile unsigned int*)(0x4270E120UL))\r
+#define bFM3_MFS7_UART_TDR_AD                  *((volatile unsigned int*)(0x4270E120UL))\r
+#define bFM3_MFS7_UART_BGR_EXT                 *((volatile unsigned int*)(0x4270E1BCUL))\r
+#define bFM3_MFS7_UART_BGR1_EXT                *((volatile unsigned int*)(0x4270E1BCUL))\r
+#define bFM3_MFS7_UART_FCR_FE1                 *((volatile unsigned int*)(0x4270E280UL))\r
+#define bFM3_MFS7_UART_FCR_FE2                 *((volatile unsigned int*)(0x4270E284UL))\r
+#define bFM3_MFS7_UART_FCR_FCL1                *((volatile unsigned int*)(0x4270E288UL))\r
+#define bFM3_MFS7_UART_FCR_FCL2                *((volatile unsigned int*)(0x4270E28CUL))\r
+#define bFM3_MFS7_UART_FCR_FSET                *((volatile unsigned int*)(0x4270E290UL))\r
+#define bFM3_MFS7_UART_FCR_FLD                 *((volatile unsigned int*)(0x4270E294UL))\r
+#define bFM3_MFS7_UART_FCR_FLST                *((volatile unsigned int*)(0x4270E298UL))\r
+#define bFM3_MFS7_UART_FCR_FSEL                *((volatile unsigned int*)(0x4270E2A0UL))\r
+#define bFM3_MFS7_UART_FCR_FTIE                *((volatile unsigned int*)(0x4270E2A4UL))\r
+#define bFM3_MFS7_UART_FCR_FDRQ                *((volatile unsigned int*)(0x4270E2A8UL))\r
+#define bFM3_MFS7_UART_FCR_FRIE                *((volatile unsigned int*)(0x4270E2ACUL))\r
+#define bFM3_MFS7_UART_FCR_FLSTE               *((volatile unsigned int*)(0x4270E2B0UL))\r
+#define bFM3_MFS7_UART_FCR_FTST0               *((volatile unsigned int*)(0x4270E2B8UL))\r
+#define bFM3_MFS7_UART_FCR_FTST1               *((volatile unsigned int*)(0x4270E2BCUL))\r
+#define bFM3_MFS7_UART_FCR0_FE1                *((volatile unsigned int*)(0x4270E280UL))\r
+#define bFM3_MFS7_UART_FCR0_FE2                *((volatile unsigned int*)(0x4270E284UL))\r
+#define bFM3_MFS7_UART_FCR0_FCL1               *((volatile unsigned int*)(0x4270E288UL))\r
+#define bFM3_MFS7_UART_FCR0_FCL2               *((volatile unsigned int*)(0x4270E28CUL))\r
+#define bFM3_MFS7_UART_FCR0_FSET               *((volatile unsigned int*)(0x4270E290UL))\r
+#define bFM3_MFS7_UART_FCR0_FLD                *((volatile unsigned int*)(0x4270E294UL))\r
+#define bFM3_MFS7_UART_FCR0_FLST               *((volatile unsigned int*)(0x4270E298UL))\r
+#define bFM3_MFS7_UART_FCR1_FSEL               *((volatile unsigned int*)(0x4270E2A0UL))\r
+#define bFM3_MFS7_UART_FCR1_FTIE               *((volatile unsigned int*)(0x4270E2A4UL))\r
+#define bFM3_MFS7_UART_FCR1_FDRQ               *((volatile unsigned int*)(0x4270E2A8UL))\r
+#define bFM3_MFS7_UART_FCR1_FRIE               *((volatile unsigned int*)(0x4270E2ACUL))\r
+#define bFM3_MFS7_UART_FCR1_FLSTE              *((volatile unsigned int*)(0x4270E2B0UL))\r
+#define bFM3_MFS7_UART_FCR1_FTST0              *((volatile unsigned int*)(0x4270E2B8UL))\r
+#define bFM3_MFS7_UART_FCR1_FTST1              *((volatile unsigned int*)(0x4270E2BCUL))\r
+#define bFM3_MFS7_UART_FBYTE_FD0               *((volatile unsigned int*)(0x4270E300UL))\r
+#define bFM3_MFS7_UART_FBYTE_FD1               *((volatile unsigned int*)(0x4270E304UL))\r
+#define bFM3_MFS7_UART_FBYTE_FD2               *((volatile unsigned int*)(0x4270E308UL))\r
+#define bFM3_MFS7_UART_FBYTE_FD3               *((volatile unsigned int*)(0x4270E30CUL))\r
+#define bFM3_MFS7_UART_FBYTE_FD4               *((volatile unsigned int*)(0x4270E310UL))\r
+#define bFM3_MFS7_UART_FBYTE_FD5               *((volatile unsigned int*)(0x4270E314UL))\r
+#define bFM3_MFS7_UART_FBYTE_FD6               *((volatile unsigned int*)(0x4270E318UL))\r
+#define bFM3_MFS7_UART_FBYTE_FD7               *((volatile unsigned int*)(0x4270E31CUL))\r
+#define bFM3_MFS7_UART_FBYTE_FD8               *((volatile unsigned int*)(0x4270E320UL))\r
+#define bFM3_MFS7_UART_FBYTE_FD9               *((volatile unsigned int*)(0x4270E324UL))\r
+#define bFM3_MFS7_UART_FBYTE_FD10              *((volatile unsigned int*)(0x4270E328UL))\r
+#define bFM3_MFS7_UART_FBYTE_FD11              *((volatile unsigned int*)(0x4270E32CUL))\r
+#define bFM3_MFS7_UART_FBYTE_FD12              *((volatile unsigned int*)(0x4270E330UL))\r
+#define bFM3_MFS7_UART_FBYTE_FD13              *((volatile unsigned int*)(0x4270E334UL))\r
+#define bFM3_MFS7_UART_FBYTE_FD14              *((volatile unsigned int*)(0x4270E338UL))\r
+#define bFM3_MFS7_UART_FBYTE_FD15              *((volatile unsigned int*)(0x4270E33CUL))\r
+#define bFM3_MFS7_UART_FBYTE1_FD0              *((volatile unsigned int*)(0x4270E300UL))\r
+#define bFM3_MFS7_UART_FBYTE1_FD1              *((volatile unsigned int*)(0x4270E304UL))\r
+#define bFM3_MFS7_UART_FBYTE1_FD2              *((volatile unsigned int*)(0x4270E308UL))\r
+#define bFM3_MFS7_UART_FBYTE1_FD3              *((volatile unsigned int*)(0x4270E30CUL))\r
+#define bFM3_MFS7_UART_FBYTE1_FD4              *((volatile unsigned int*)(0x4270E310UL))\r
+#define bFM3_MFS7_UART_FBYTE1_FD5              *((volatile unsigned int*)(0x4270E314UL))\r
+#define bFM3_MFS7_UART_FBYTE1_FD6              *((volatile unsigned int*)(0x4270E318UL))\r
+#define bFM3_MFS7_UART_FBYTE1_FD7              *((volatile unsigned int*)(0x4270E31CUL))\r
+#define bFM3_MFS7_UART_FBYTE2_FD8              *((volatile unsigned int*)(0x4270E320UL))\r
+#define bFM3_MFS7_UART_FBYTE2_FD9              *((volatile unsigned int*)(0x4270E324UL))\r
+#define bFM3_MFS7_UART_FBYTE2_FD10             *((volatile unsigned int*)(0x4270E328UL))\r
+#define bFM3_MFS7_UART_FBYTE2_FD11             *((volatile unsigned int*)(0x4270E32CUL))\r
+#define bFM3_MFS7_UART_FBYTE2_FD12             *((volatile unsigned int*)(0x4270E330UL))\r
+#define bFM3_MFS7_UART_FBYTE2_FD13             *((volatile unsigned int*)(0x4270E334UL))\r
+#define bFM3_MFS7_UART_FBYTE2_FD14             *((volatile unsigned int*)(0x4270E338UL))\r
+#define bFM3_MFS7_UART_FBYTE2_FD15             *((volatile unsigned int*)(0x4270E33CUL))\r
+\r
+/* UART synchronous channel 7 registers */\r
+#define bFM3_MFS7_CSIO_SMR_SOE                 *((volatile unsigned int*)(0x4270E000UL))\r
+#define bFM3_MFS7_CSIO_SMR_SCKE                *((volatile unsigned int*)(0x4270E004UL))\r
+#define bFM3_MFS7_CSIO_SMR_BDS                 *((volatile unsigned int*)(0x4270E008UL))\r
+#define bFM3_MFS7_CSIO_SMR_SCINV               *((volatile unsigned int*)(0x4270E00CUL))\r
+#define bFM3_MFS7_CSIO_SMR_WUCR                *((volatile unsigned int*)(0x4270E010UL))\r
+#define bFM3_MFS7_CSIO_SMR_MD0                 *((volatile unsigned int*)(0x4270E014UL))\r
+#define bFM3_MFS7_CSIO_SMR_MD1                 *((volatile unsigned int*)(0x4270E018UL))\r
+#define bFM3_MFS7_CSIO_SMR_MD2                 *((volatile unsigned int*)(0x4270E01CUL))\r
+#define bFM3_MFS7_CSIO_SCR_TXE                 *((volatile unsigned int*)(0x4270E020UL))\r
+#define bFM3_MFS7_CSIO_SCR_RXE                 *((volatile unsigned int*)(0x4270E024UL))\r
+#define bFM3_MFS7_CSIO_SCR_TBIE                *((volatile unsigned int*)(0x4270E028UL))\r
+#define bFM3_MFS7_CSIO_SCR_TIE                 *((volatile unsigned int*)(0x4270E02CUL))\r
+#define bFM3_MFS7_CSIO_SCR_RIE                 *((volatile unsigned int*)(0x4270E030UL))\r
+#define bFM3_MFS7_CSIO_SCR_SPI                 *((volatile unsigned int*)(0x4270E034UL))\r
+#define bFM3_MFS7_CSIO_SCR_MS                  *((volatile unsigned int*)(0x4270E038UL))\r
+#define bFM3_MFS7_CSIO_SCR_UPCL                *((volatile unsigned int*)(0x4270E03CUL))\r
+#define bFM3_MFS7_CSIO_ESCR_L0                 *((volatile unsigned int*)(0x4270E080UL))\r
+#define bFM3_MFS7_CSIO_ESCR_L1                 *((volatile unsigned int*)(0x4270E084UL))\r
+#define bFM3_MFS7_CSIO_ESCR_L2                 *((volatile unsigned int*)(0x4270E088UL))\r
+#define bFM3_MFS7_CSIO_ESCR_WT0                *((volatile unsigned int*)(0x4270E08CUL))\r
+#define bFM3_MFS7_CSIO_ESCR_WT1                *((volatile unsigned int*)(0x4270E090UL))\r
+#define bFM3_MFS7_CSIO_ESCR_SOP                *((volatile unsigned int*)(0x4270E09CUL))\r
+#define bFM3_MFS7_CSIO_SSR_TBI                 *((volatile unsigned int*)(0x4270E0A0UL))\r
+#define bFM3_MFS7_CSIO_SSR_TDRE                *((volatile unsigned int*)(0x4270E0A4UL))\r
+#define bFM3_MFS7_CSIO_SSR_RDRF                *((volatile unsigned int*)(0x4270E0A8UL))\r
+#define bFM3_MFS7_CSIO_SSR_ORE                 *((volatile unsigned int*)(0x4270E0ACUL))\r
+#define bFM3_MFS7_CSIO_SSR_REC                 *((volatile unsigned int*)(0x4270E0BCUL))\r
+#define bFM3_MFS7_CSIO_FCR_FE1                 *((volatile unsigned int*)(0x4270E280UL))\r
+#define bFM3_MFS7_CSIO_FCR_FE2                 *((volatile unsigned int*)(0x4270E284UL))\r
+#define bFM3_MFS7_CSIO_FCR_FCL1                *((volatile unsigned int*)(0x4270E288UL))\r
+#define bFM3_MFS7_CSIO_FCR_FCL2                *((volatile unsigned int*)(0x4270E28CUL))\r
+#define bFM3_MFS7_CSIO_FCR_FSET                *((volatile unsigned int*)(0x4270E290UL))\r
+#define bFM3_MFS7_CSIO_FCR_FLD                 *((volatile unsigned int*)(0x4270E294UL))\r
+#define bFM3_MFS7_CSIO_FCR_FLST                *((volatile unsigned int*)(0x4270E298UL))\r
+#define bFM3_MFS7_CSIO_FCR_FSEL                *((volatile unsigned int*)(0x4270E2A0UL))\r
+#define bFM3_MFS7_CSIO_FCR_FTIE                *((volatile unsigned int*)(0x4270E2A4UL))\r
+#define bFM3_MFS7_CSIO_FCR_FDRQ                *((volatile unsigned int*)(0x4270E2A8UL))\r
+#define bFM3_MFS7_CSIO_FCR_FRIE                *((volatile unsigned int*)(0x4270E2ACUL))\r
+#define bFM3_MFS7_CSIO_FCR_FLSTE               *((volatile unsigned int*)(0x4270E2B0UL))\r
+#define bFM3_MFS7_CSIO_FCR_FTST0               *((volatile unsigned int*)(0x4270E2B8UL))\r
+#define bFM3_MFS7_CSIO_FCR_FTST1               *((volatile unsigned int*)(0x4270E2BCUL))\r
+#define bFM3_MFS7_CSIO_FCR0_FE1                *((volatile unsigned int*)(0x4270E280UL))\r
+#define bFM3_MFS7_CSIO_FCR0_FE2                *((volatile unsigned int*)(0x4270E284UL))\r
+#define bFM3_MFS7_CSIO_FCR0_FCL1               *((volatile unsigned int*)(0x4270E288UL))\r
+#define bFM3_MFS7_CSIO_FCR0_FCL2               *((volatile unsigned int*)(0x4270E28CUL))\r
+#define bFM3_MFS7_CSIO_FCR0_FSET               *((volatile unsigned int*)(0x4270E290UL))\r
+#define bFM3_MFS7_CSIO_FCR0_FLD                *((volatile unsigned int*)(0x4270E294UL))\r
+#define bFM3_MFS7_CSIO_FCR0_FLST               *((volatile unsigned int*)(0x4270E298UL))\r
+#define bFM3_MFS7_CSIO_FCR1_FSEL               *((volatile unsigned int*)(0x4270E2A0UL))\r
+#define bFM3_MFS7_CSIO_FCR1_FTIE               *((volatile unsigned int*)(0x4270E2A4UL))\r
+#define bFM3_MFS7_CSIO_FCR1_FDRQ               *((volatile unsigned int*)(0x4270E2A8UL))\r
+#define bFM3_MFS7_CSIO_FCR1_FRIE               *((volatile unsigned int*)(0x4270E2ACUL))\r
+#define bFM3_MFS7_CSIO_FCR1_FLSTE              *((volatile unsigned int*)(0x4270E2B0UL))\r
+#define bFM3_MFS7_CSIO_FCR1_FTST0              *((volatile unsigned int*)(0x4270E2B8UL))\r
+#define bFM3_MFS7_CSIO_FCR1_FTST1              *((volatile unsigned int*)(0x4270E2BCUL))\r
+#define bFM3_MFS7_CSIO_FBYTE_FD0               *((volatile unsigned int*)(0x4270E300UL))\r
+#define bFM3_MFS7_CSIO_FBYTE_FD1               *((volatile unsigned int*)(0x4270E304UL))\r
+#define bFM3_MFS7_CSIO_FBYTE_FD2               *((volatile unsigned int*)(0x4270E308UL))\r
+#define bFM3_MFS7_CSIO_FBYTE_FD3               *((volatile unsigned int*)(0x4270E30CUL))\r
+#define bFM3_MFS7_CSIO_FBYTE_FD4               *((volatile unsigned int*)(0x4270E310UL))\r
+#define bFM3_MFS7_CSIO_FBYTE_FD5               *((volatile unsigned int*)(0x4270E314UL))\r
+#define bFM3_MFS7_CSIO_FBYTE_FD6               *((volatile unsigned int*)(0x4270E318UL))\r
+#define bFM3_MFS7_CSIO_FBYTE_FD7               *((volatile unsigned int*)(0x4270E31CUL))\r
+#define bFM3_MFS7_CSIO_FBYTE_FD8               *((volatile unsigned int*)(0x4270E320UL))\r
+#define bFM3_MFS7_CSIO_FBYTE_FD9               *((volatile unsigned int*)(0x4270E324UL))\r
+#define bFM3_MFS7_CSIO_FBYTE_FD10              *((volatile unsigned int*)(0x4270E328UL))\r
+#define bFM3_MFS7_CSIO_FBYTE_FD11              *((volatile unsigned int*)(0x4270E32CUL))\r
+#define bFM3_MFS7_CSIO_FBYTE_FD12              *((volatile unsigned int*)(0x4270E330UL))\r
+#define bFM3_MFS7_CSIO_FBYTE_FD13              *((volatile unsigned int*)(0x4270E334UL))\r
+#define bFM3_MFS7_CSIO_FBYTE_FD14              *((volatile unsigned int*)(0x4270E338UL))\r
+#define bFM3_MFS7_CSIO_FBYTE_FD15              *((volatile unsigned int*)(0x4270E33CUL))\r
+#define bFM3_MFS7_CSIO_FBYTE1_FD0              *((volatile unsigned int*)(0x4270E300UL))\r
+#define bFM3_MFS7_CSIO_FBYTE1_FD1              *((volatile unsigned int*)(0x4270E304UL))\r
+#define bFM3_MFS7_CSIO_FBYTE1_FD2              *((volatile unsigned int*)(0x4270E308UL))\r
+#define bFM3_MFS7_CSIO_FBYTE1_FD3              *((volatile unsigned int*)(0x4270E30CUL))\r
+#define bFM3_MFS7_CSIO_FBYTE1_FD4              *((volatile unsigned int*)(0x4270E310UL))\r
+#define bFM3_MFS7_CSIO_FBYTE1_FD5              *((volatile unsigned int*)(0x4270E314UL))\r
+#define bFM3_MFS7_CSIO_FBYTE1_FD6              *((volatile unsigned int*)(0x4270E318UL))\r
+#define bFM3_MFS7_CSIO_FBYTE1_FD7              *((volatile unsigned int*)(0x4270E31CUL))\r
+#define bFM3_MFS7_CSIO_FBYTE2_FD8              *((volatile unsigned int*)(0x4270E340UL))\r
+#define bFM3_MFS7_CSIO_FBYTE2_FD9              *((volatile unsigned int*)(0x4270E344UL))\r
+#define bFM3_MFS7_CSIO_FBYTE2_FD10             *((volatile unsigned int*)(0x4270E348UL))\r
+#define bFM3_MFS7_CSIO_FBYTE2_FD11             *((volatile unsigned int*)(0x4270E34CUL))\r
+#define bFM3_MFS7_CSIO_FBYTE2_FD12             *((volatile unsigned int*)(0x4270E350UL))\r
+#define bFM3_MFS7_CSIO_FBYTE2_FD13             *((volatile unsigned int*)(0x4270E354UL))\r
+#define bFM3_MFS7_CSIO_FBYTE2_FD14             *((volatile unsigned int*)(0x4270E358UL))\r
+#define bFM3_MFS7_CSIO_FBYTE2_FD15             *((volatile unsigned int*)(0x4270E35CUL))\r
+\r
+/* UART LIN channel 7 registers */\r
+#define bFM3_MFS7_LIN_SMR_SOE                  *((volatile unsigned int*)(0x4270E000UL))\r
+#define bFM3_MFS7_LIN_SMR_SBL                  *((volatile unsigned int*)(0x4270E00CUL))\r
+#define bFM3_MFS7_LIN_SMR_WUCR                 *((volatile unsigned int*)(0x4270E010UL))\r
+#define bFM3_MFS7_LIN_SMR_MD0                  *((volatile unsigned int*)(0x4270E014UL))\r
+#define bFM3_MFS7_LIN_SMR_MD1                  *((volatile unsigned int*)(0x4270E018UL))\r
+#define bFM3_MFS7_LIN_SMR_MD2                  *((volatile unsigned int*)(0x4270E01CUL))\r
+#define bFM3_MFS7_LIN_SCR_TXE                  *((volatile unsigned int*)(0x4270E020UL))\r
+#define bFM3_MFS7_LIN_SCR_RXE                  *((volatile unsigned int*)(0x4270E024UL))\r
+#define bFM3_MFS7_LIN_SCR_TBIE                 *((volatile unsigned int*)(0x4270E028UL))\r
+#define bFM3_MFS7_LIN_SCR_TIE                  *((volatile unsigned int*)(0x4270E02CUL))\r
+#define bFM3_MFS7_LIN_SCR_RIE                  *((volatile unsigned int*)(0x4270E030UL))\r
+#define bFM3_MFS7_LIN_SCR_LBR                  *((volatile unsigned int*)(0x4270E034UL))\r
+#define bFM3_MFS7_LIN_SCR_MS                   *((volatile unsigned int*)(0x4270E038UL))\r
+#define bFM3_MFS7_LIN_SCR_UPCL                 *((volatile unsigned int*)(0x4270E03CUL))\r
+#define bFM3_MFS7_LIN_ESCR_DEL0                *((volatile unsigned int*)(0x4270E080UL))\r
+#define bFM3_MFS7_LIN_ESCR_DEL1                *((volatile unsigned int*)(0x4270E084UL))\r
+#define bFM3_MFS7_LIN_ESCR_LBL0                *((volatile unsigned int*)(0x4270E088UL))\r
+#define bFM3_MFS7_LIN_ESCR_LBL1                *((volatile unsigned int*)(0x4270E08CUL))\r
+#define bFM3_MFS7_LIN_ESCR_LBIE                *((volatile unsigned int*)(0x4270E090UL))\r
+#define bFM3_MFS7_LIN_ESCR_ESBL                *((volatile unsigned int*)(0x4270E098UL))\r
+#define bFM3_MFS7_LIN_SSR_TBI                  *((volatile unsigned int*)(0x4270E0A0UL))\r
+#define bFM3_MFS7_LIN_SSR_TDRE                 *((volatile unsigned int*)(0x4270E0A4UL))\r
+#define bFM3_MFS7_LIN_SSR_RDRF                 *((volatile unsigned int*)(0x4270E0A8UL))\r
+#define bFM3_MFS7_LIN_SSR_ORE                  *((volatile unsigned int*)(0x4270E0ACUL))\r
+#define bFM3_MFS7_LIN_SSR_FRE                  *((volatile unsigned int*)(0x4270E0B0UL))\r
+#define bFM3_MFS7_LIN_SSR_LBD                  *((volatile unsigned int*)(0x4270E0B4UL))\r
+#define bFM3_MFS7_LIN_SSR_REC                  *((volatile unsigned int*)(0x4270E0BCUL))\r
+#define bFM3_MFS7_LIN_BGR_EXT                  *((volatile unsigned int*)(0x4270E1BCUL))\r
+#define bFM3_MFS7_LIN_BGR1_EXT                 *((volatile unsigned int*)(0x4270E1BCUL))\r
+#define bFM3_MFS7_LIN_FCR_FE1                  *((volatile unsigned int*)(0x4270E280UL))\r
+#define bFM3_MFS7_LIN_FCR_FE2                  *((volatile unsigned int*)(0x4270E284UL))\r
+#define bFM3_MFS7_LIN_FCR_FCL1                 *((volatile unsigned int*)(0x4270E288UL))\r
+#define bFM3_MFS7_LIN_FCR_FCL2                 *((volatile unsigned int*)(0x4270E28CUL))\r
+#define bFM3_MFS7_LIN_FCR_FSET                 *((volatile unsigned int*)(0x4270E290UL))\r
+#define bFM3_MFS7_LIN_FCR_FLD                  *((volatile unsigned int*)(0x4270E294UL))\r
+#define bFM3_MFS7_LIN_FCR_FLST                 *((volatile unsigned int*)(0x4270E298UL))\r
+#define bFM3_MFS7_LIN_FCR_FSEL                 *((volatile unsigned int*)(0x4270E2A0UL))\r
+#define bFM3_MFS7_LIN_FCR_FTIE                 *((volatile unsigned int*)(0x4270E2A4UL))\r
+#define bFM3_MFS7_LIN_FCR_FDRQ                 *((volatile unsigned int*)(0x4270E2A8UL))\r
+#define bFM3_MFS7_LIN_FCR_FRIE                 *((volatile unsigned int*)(0x4270E2ACUL))\r
+#define bFM3_MFS7_LIN_FCR_FLSTE                *((volatile unsigned int*)(0x4270E2B0UL))\r
+#define bFM3_MFS7_LIN_FCR_FTST0                *((volatile unsigned int*)(0x4270E2B8UL))\r
+#define bFM3_MFS7_LIN_FCR_FTST1                *((volatile unsigned int*)(0x4270E2BCUL))\r
+#define bFM3_MFS7_LIN_FCR0_FE1                 *((volatile unsigned int*)(0x4270E280UL))\r
+#define bFM3_MFS7_LIN_FCR0_FE2                 *((volatile unsigned int*)(0x4270E284UL))\r
+#define bFM3_MFS7_LIN_FCR0_FCL1                *((volatile unsigned int*)(0x4270E288UL))\r
+#define bFM3_MFS7_LIN_FCR0_FCL2                *((volatile unsigned int*)(0x4270E28CUL))\r
+#define bFM3_MFS7_LIN_FCR0_FSET                *((volatile unsigned int*)(0x4270E290UL))\r
+#define bFM3_MFS7_LIN_FCR0_FLD                 *((volatile unsigned int*)(0x4270E294UL))\r
+#define bFM3_MFS7_LIN_FCR0_FLST                *((volatile unsigned int*)(0x4270E298UL))\r
+#define bFM3_MFS7_LIN_FCR1_FSEL                *((volatile unsigned int*)(0x4270E2A0UL))\r
+#define bFM3_MFS7_LIN_FCR1_FTIE                *((volatile unsigned int*)(0x4270E2A4UL))\r
+#define bFM3_MFS7_LIN_FCR1_FDRQ                *((volatile unsigned int*)(0x4270E2A8UL))\r
+#define bFM3_MFS7_LIN_FCR1_FRIE                *((volatile unsigned int*)(0x4270E2ACUL))\r
+#define bFM3_MFS7_LIN_FCR1_FLSTE               *((volatile unsigned int*)(0x4270E2B0UL))\r
+#define bFM3_MFS7_LIN_FCR1_FTST0               *((volatile unsigned int*)(0x4270E2B8UL))\r
+#define bFM3_MFS7_LIN_FCR1_FTST1               *((volatile unsigned int*)(0x4270E2BCUL))\r
+#define bFM3_MFS7_LIN_FBYTE_FD0                *((volatile unsigned int*)(0x4270E300UL))\r
+#define bFM3_MFS7_LIN_FBYTE_FD1                *((volatile unsigned int*)(0x4270E304UL))\r
+#define bFM3_MFS7_LIN_FBYTE_FD2                *((volatile unsigned int*)(0x4270E308UL))\r
+#define bFM3_MFS7_LIN_FBYTE_FD3                *((volatile unsigned int*)(0x4270E30CUL))\r
+#define bFM3_MFS7_LIN_FBYTE_FD4                *((volatile unsigned int*)(0x4270E310UL))\r
+#define bFM3_MFS7_LIN_FBYTE_FD5                *((volatile unsigned int*)(0x4270E314UL))\r
+#define bFM3_MFS7_LIN_FBYTE_FD6                *((volatile unsigned int*)(0x4270E318UL))\r
+#define bFM3_MFS7_LIN_FBYTE_FD7                *((volatile unsigned int*)(0x4270E31CUL))\r
+#define bFM3_MFS7_LIN_FBYTE_FD8                *((volatile unsigned int*)(0x4270E320UL))\r
+#define bFM3_MFS7_LIN_FBYTE_FD9                *((volatile unsigned int*)(0x4270E324UL))\r
+#define bFM3_MFS7_LIN_FBYTE_FD10               *((volatile unsigned int*)(0x4270E328UL))\r
+#define bFM3_MFS7_LIN_FBYTE_FD11               *((volatile unsigned int*)(0x4270E32CUL))\r
+#define bFM3_MFS7_LIN_FBYTE_FD12               *((volatile unsigned int*)(0x4270E330UL))\r
+#define bFM3_MFS7_LIN_FBYTE_FD13               *((volatile unsigned int*)(0x4270E334UL))\r
+#define bFM3_MFS7_LIN_FBYTE_FD14               *((volatile unsigned int*)(0x4270E338UL))\r
+#define bFM3_MFS7_LIN_FBYTE_FD15               *((volatile unsigned int*)(0x4270E33CUL))\r
+#define bFM3_MFS7_LIN_FBYTE1_FD0               *((volatile unsigned int*)(0x4270E300UL))\r
+#define bFM3_MFS7_LIN_FBYTE1_FD1               *((volatile unsigned int*)(0x4270E304UL))\r
+#define bFM3_MFS7_LIN_FBYTE1_FD2               *((volatile unsigned int*)(0x4270E308UL))\r
+#define bFM3_MFS7_LIN_FBYTE1_FD3               *((volatile unsigned int*)(0x4270E30CUL))\r
+#define bFM3_MFS7_LIN_FBYTE1_FD4               *((volatile unsigned int*)(0x4270E310UL))\r
+#define bFM3_MFS7_LIN_FBYTE1_FD5               *((volatile unsigned int*)(0x4270E314UL))\r
+#define bFM3_MFS7_LIN_FBYTE1_FD6               *((volatile unsigned int*)(0x4270E318UL))\r
+#define bFM3_MFS7_LIN_FBYTE1_FD7               *((volatile unsigned int*)(0x4270E31CUL))\r
+#define bFM3_MFS7_LIN_FBYTE2_FD8               *((volatile unsigned int*)(0x4270E340UL))\r
+#define bFM3_MFS7_LIN_FBYTE2_FD9               *((volatile unsigned int*)(0x4270E344UL))\r
+#define bFM3_MFS7_LIN_FBYTE2_FD10              *((volatile unsigned int*)(0x4270E348UL))\r
+#define bFM3_MFS7_LIN_FBYTE2_FD11              *((volatile unsigned int*)(0x4270E34CUL))\r
+#define bFM3_MFS7_LIN_FBYTE2_FD12              *((volatile unsigned int*)(0x4270E350UL))\r
+#define bFM3_MFS7_LIN_FBYTE2_FD13              *((volatile unsigned int*)(0x4270E354UL))\r
+#define bFM3_MFS7_LIN_FBYTE2_FD14              *((volatile unsigned int*)(0x4270E358UL))\r
+#define bFM3_MFS7_LIN_FBYTE2_FD15              *((volatile unsigned int*)(0x4270E35CUL))\r
+\r
+/* I2C channel 7 registers */\r
+#define bFM3_MFS7_I2C_SMR_ITST0                *((volatile unsigned int*)(0x4270E000UL))\r
+#define bFM3_MFS7_I2C_SMR_ITST1                *((volatile unsigned int*)(0x4270E004UL))\r
+#define bFM3_MFS7_I2C_SMR_TIE                  *((volatile unsigned int*)(0x4270E008UL))\r
+#define bFM3_MFS7_I2C_SMR_RIE                  *((volatile unsigned int*)(0x4270E00CUL))\r
+#define bFM3_MFS7_I2C_SMR_WUCR                 *((volatile unsigned int*)(0x4270E010UL))\r
+#define bFM3_MFS7_I2C_SMR_MD0                  *((volatile unsigned int*)(0x4270E014UL))\r
+#define bFM3_MFS7_I2C_SMR_MD1                  *((volatile unsigned int*)(0x4270E018UL))\r
+#define bFM3_MFS7_I2C_SMR_MD2                  *((volatile unsigned int*)(0x4270E01CUL))\r
+#define bFM3_MFS7_I2C_IBCR_INT                 *((volatile unsigned int*)(0x4270E020UL))\r
+#define bFM3_MFS7_I2C_IBCR_BER                 *((volatile unsigned int*)(0x4270E024UL))\r
+#define bFM3_MFS7_I2C_IBCR_INTE                *((volatile unsigned int*)(0x4270E028UL))\r
+#define bFM3_MFS7_I2C_IBCR_CNDE                *((volatile unsigned int*)(0x4270E02CUL))\r
+#define bFM3_MFS7_I2C_IBCR_WSEL                *((volatile unsigned int*)(0x4270E030UL))\r
+#define bFM3_MFS7_I2C_IBCR_ACKE                *((volatile unsigned int*)(0x4270E034UL))\r
+#define bFM3_MFS7_I2C_IBCR_ACT                 *((volatile unsigned int*)(0x4270E038UL))\r
+#define bFM3_MFS7_I2C_IBCR_SCC                 *((volatile unsigned int*)(0x4270E038UL))\r
+#define bFM3_MFS7_I2C_IBCR_MSS                 *((volatile unsigned int*)(0x4270E03CUL))\r
+#define bFM3_MFS7_I2C_IBSR_BB                  *((volatile unsigned int*)(0x4270E080UL))\r
+#define bFM3_MFS7_I2C_IBSR_SPC                 *((volatile unsigned int*)(0x4270E084UL))\r
+#define bFM3_MFS7_I2C_IBSR_RSC                 *((volatile unsigned int*)(0x4270E088UL))\r
+#define bFM3_MFS7_I2C_IBSR_AL                  *((volatile unsigned int*)(0x4270E08CUL))\r
+#define bFM3_MFS7_I2C_IBSR_TRX                 *((volatile unsigned int*)(0x4270E090UL))\r
+#define bFM3_MFS7_I2C_IBSR_RSA                 *((volatile unsigned int*)(0x4270E094UL))\r
+#define bFM3_MFS7_I2C_IBSR_RACK                *((volatile unsigned int*)(0x4270E098UL))\r
+#define bFM3_MFS7_I2C_IBSR_FBT                 *((volatile unsigned int*)(0x4270E09CUL))\r
+#define bFM3_MFS7_I2C_SSR_TBI                  *((volatile unsigned int*)(0x4270E0A0UL))\r
+#define bFM3_MFS7_I2C_SSR_TDRE                 *((volatile unsigned int*)(0x4270E0A4UL))\r
+#define bFM3_MFS7_I2C_SSR_RDRF                 *((volatile unsigned int*)(0x4270E0A8UL))\r
+#define bFM3_MFS7_I2C_SSR_ORE                  *((volatile unsigned int*)(0x4270E0ACUL))\r
+#define bFM3_MFS7_I2C_SSR_TBIE                 *((volatile unsigned int*)(0x4270E0B0UL))\r
+#define bFM3_MFS7_I2C_SSR_DMA                  *((volatile unsigned int*)(0x4270E0B4UL))\r
+#define bFM3_MFS7_I2C_SSR_TSET                 *((volatile unsigned int*)(0x4270E0B8UL))\r
+#define bFM3_MFS7_I2C_SSR_REC                  *((volatile unsigned int*)(0x4270E0BCUL))\r
+#define bFM3_MFS7_I2C_ISBA_SA0                 *((volatile unsigned int*)(0x4270E200UL))\r
+#define bFM3_MFS7_I2C_ISBA_SA1                 *((volatile unsigned int*)(0x4270E204UL))\r
+#define bFM3_MFS7_I2C_ISBA_SA2                 *((volatile unsigned int*)(0x4270E208UL))\r
+#define bFM3_MFS7_I2C_ISBA_SA3                 *((volatile unsigned int*)(0x4270E20CUL))\r
+#define bFM3_MFS7_I2C_ISBA_SA4                 *((volatile unsigned int*)(0x4270E210UL))\r
+#define bFM3_MFS7_I2C_ISBA_SA5                 *((volatile unsigned int*)(0x4270E214UL))\r
+#define bFM3_MFS7_I2C_ISBA_SA6                 *((volatile unsigned int*)(0x4270E218UL))\r
+#define bFM3_MFS7_I2C_ISBA_SAEN                *((volatile unsigned int*)(0x4270E21CUL))\r
+#define bFM3_MFS7_I2C_ISMK_SM0                 *((volatile unsigned int*)(0x4270E220UL))\r
+#define bFM3_MFS7_I2C_ISMK_SM1                 *((volatile unsigned int*)(0x4270E224UL))\r
+#define bFM3_MFS7_I2C_ISMK_SM2                 *((volatile unsigned int*)(0x4270E228UL))\r
+#define bFM3_MFS7_I2C_ISMK_SM3                 *((volatile unsigned int*)(0x4270E22CUL))\r
+#define bFM3_MFS7_I2C_ISMK_SM4                 *((volatile unsigned int*)(0x4270E230UL))\r
+#define bFM3_MFS7_I2C_ISMK_SM5                 *((volatile unsigned int*)(0x4270E234UL))\r
+#define bFM3_MFS7_I2C_ISMK_SM6                 *((volatile unsigned int*)(0x4270E238UL))\r
+#define bFM3_MFS7_I2C_ISMK_EN                  *((volatile unsigned int*)(0x4270E23CUL))\r
+#define bFM3_MFS7_I2C_FCR_FE1                  *((volatile unsigned int*)(0x4270E280UL))\r
+#define bFM3_MFS7_I2C_FCR_FE2                  *((volatile unsigned int*)(0x4270E284UL))\r
+#define bFM3_MFS7_I2C_FCR_FCL1                 *((volatile unsigned int*)(0x4270E288UL))\r
+#define bFM3_MFS7_I2C_FCR_FCL2                 *((volatile unsigned int*)(0x4270E28CUL))\r
+#define bFM3_MFS7_I2C_FCR_FSET                 *((volatile unsigned int*)(0x4270E290UL))\r
+#define bFM3_MFS7_I2C_FCR_FLD                  *((volatile unsigned int*)(0x4270E294UL))\r
+#define bFM3_MFS7_I2C_FCR_FLST                 *((volatile unsigned int*)(0x4270E298UL))\r
+#define bFM3_MFS7_I2C_FCR_FSEL                 *((volatile unsigned int*)(0x4270E2A0UL))\r
+#define bFM3_MFS7_I2C_FCR_FTIE                 *((volatile unsigned int*)(0x4270E2A4UL))\r
+#define bFM3_MFS7_I2C_FCR_FDRQ                 *((volatile unsigned int*)(0x4270E2A8UL))\r
+#define bFM3_MFS7_I2C_FCR_FRIE                 *((volatile unsigned int*)(0x4270E2ACUL))\r
+#define bFM3_MFS7_I2C_FCR_FLSTE                *((volatile unsigned int*)(0x4270E2B0UL))\r
+#define bFM3_MFS7_I2C_FCR_FTST0                *((volatile unsigned int*)(0x4270E2B8UL))\r
+#define bFM3_MFS7_I2C_FCR_FTST1                *((volatile unsigned int*)(0x4270E2BCUL))\r
+#define bFM3_MFS7_I2C_FCR0_FE1                 *((volatile unsigned int*)(0x4270E280UL))\r
+#define bFM3_MFS7_I2C_FCR0_FE2                 *((volatile unsigned int*)(0x4270E284UL))\r
+#define bFM3_MFS7_I2C_FCR0_FCL1                *((volatile unsigned int*)(0x4270E288UL))\r
+#define bFM3_MFS7_I2C_FCR0_FCL2                *((volatile unsigned int*)(0x4270E28CUL))\r
+#define bFM3_MFS7_I2C_FCR0_FSET                *((volatile unsigned int*)(0x4270E290UL))\r
+#define bFM3_MFS7_I2C_FCR0_FLD                 *((volatile unsigned int*)(0x4270E294UL))\r
+#define bFM3_MFS7_I2C_FCR0_FLST                *((volatile unsigned int*)(0x4270E298UL))\r
+#define bFM3_MFS7_I2C_FCR1_FSEL                *((volatile unsigned int*)(0x4270E2A0UL))\r
+#define bFM3_MFS7_I2C_FCR1_FTIE                *((volatile unsigned int*)(0x4270E2A4UL))\r
+#define bFM3_MFS7_I2C_FCR1_FDRQ                *((volatile unsigned int*)(0x4270E2A8UL))\r
+#define bFM3_MFS7_I2C_FCR1_FRIE                *((volatile unsigned int*)(0x4270E2ACUL))\r
+#define bFM3_MFS7_I2C_FCR1_FLSTE               *((volatile unsigned int*)(0x4270E2B0UL))\r
+#define bFM3_MFS7_I2C_FCR1_FTST0               *((volatile unsigned int*)(0x4270E2B8UL))\r
+#define bFM3_MFS7_I2C_FCR1_FTST1               *((volatile unsigned int*)(0x4270E2BCUL))\r
+#define bFM3_MFS7_I2C_FBYTE_FD0                *((volatile unsigned int*)(0x4270E300UL))\r
+#define bFM3_MFS7_I2C_FBYTE_FD1                *((volatile unsigned int*)(0x4270E304UL))\r
+#define bFM3_MFS7_I2C_FBYTE_FD2                *((volatile unsigned int*)(0x4270E308UL))\r
+#define bFM3_MFS7_I2C_FBYTE_FD3                *((volatile unsigned int*)(0x4270E30CUL))\r
+#define bFM3_MFS7_I2C_FBYTE_FD4                *((volatile unsigned int*)(0x4270E310UL))\r
+#define bFM3_MFS7_I2C_FBYTE_FD5                *((volatile unsigned int*)(0x4270E314UL))\r
+#define bFM3_MFS7_I2C_FBYTE_FD6                *((volatile unsigned int*)(0x4270E318UL))\r
+#define bFM3_MFS7_I2C_FBYTE_FD7                *((volatile unsigned int*)(0x4270E31CUL))\r
+#define bFM3_MFS7_I2C_FBYTE_FD8                *((volatile unsigned int*)(0x4270E320UL))\r
+#define bFM3_MFS7_I2C_FBYTE_FD9                *((volatile unsigned int*)(0x4270E324UL))\r
+#define bFM3_MFS7_I2C_FBYTE_FD10               *((volatile unsigned int*)(0x4270E328UL))\r
+#define bFM3_MFS7_I2C_FBYTE_FD11               *((volatile unsigned int*)(0x4270E32CUL))\r
+#define bFM3_MFS7_I2C_FBYTE_FD12               *((volatile unsigned int*)(0x4270E330UL))\r
+#define bFM3_MFS7_I2C_FBYTE_FD13               *((volatile unsigned int*)(0x4270E334UL))\r
+#define bFM3_MFS7_I2C_FBYTE_FD14               *((volatile unsigned int*)(0x4270E338UL))\r
+#define bFM3_MFS7_I2C_FBYTE_FD15               *((volatile unsigned int*)(0x4270E33CUL))\r
+#define bFM3_MFS7_I2C_FBYTE1_FD0               *((volatile unsigned int*)(0x4270E300UL))\r
+#define bFM3_MFS7_I2C_FBYTE1_FD1               *((volatile unsigned int*)(0x4270E304UL))\r
+#define bFM3_MFS7_I2C_FBYTE1_FD2               *((volatile unsigned int*)(0x4270E308UL))\r
+#define bFM3_MFS7_I2C_FBYTE1_FD3               *((volatile unsigned int*)(0x4270E30CUL))\r
+#define bFM3_MFS7_I2C_FBYTE1_FD4               *((volatile unsigned int*)(0x4270E310UL))\r
+#define bFM3_MFS7_I2C_FBYTE1_FD5               *((volatile unsigned int*)(0x4270E314UL))\r
+#define bFM3_MFS7_I2C_FBYTE1_FD6               *((volatile unsigned int*)(0x4270E318UL))\r
+#define bFM3_MFS7_I2C_FBYTE1_FD7               *((volatile unsigned int*)(0x4270E31CUL))\r
+#define bFM3_MFS7_I2C_FBYTE2_FD8               *((volatile unsigned int*)(0x4270E340UL))\r
+#define bFM3_MFS7_I2C_FBYTE2_FD9               *((volatile unsigned int*)(0x4270E344UL))\r
+#define bFM3_MFS7_I2C_FBYTE2_FD10              *((volatile unsigned int*)(0x4270E348UL))\r
+#define bFM3_MFS7_I2C_FBYTE2_FD11              *((volatile unsigned int*)(0x4270E34CUL))\r
+#define bFM3_MFS7_I2C_FBYTE2_FD12              *((volatile unsigned int*)(0x4270E350UL))\r
+#define bFM3_MFS7_I2C_FBYTE2_FD13              *((volatile unsigned int*)(0x4270E354UL))\r
+#define bFM3_MFS7_I2C_FBYTE2_FD14              *((volatile unsigned int*)(0x4270E358UL))\r
+#define bFM3_MFS7_I2C_FBYTE2_FD15              *((volatile unsigned int*)(0x4270E35CUL))\r
+\r
+/* CRC registers */\r
+#define bFM3_CRC_CRCCR_INIT                    *((volatile unsigned int*)(0x42720000UL))\r
+#define bFM3_CRC_CRCCR_CRC32                   *((volatile unsigned int*)(0x42720004UL))\r
+#define bFM3_CRC_CRCCR_LTLEND                  *((volatile unsigned int*)(0x42720008UL))\r
+#define bFM3_CRC_CRCCR_LSBFST                  *((volatile unsigned int*)(0x4272000CUL))\r
+#define bFM3_CRC_CRCCR_CRCLTE                  *((volatile unsigned int*)(0x42720010UL))\r
+#define bFM3_CRC_CRCCR_CRCLSF                  *((volatile unsigned int*)(0x42720014UL))\r
+#define bFM3_CRC_CRCCR_FXOR                    *((volatile unsigned int*)(0x42720018UL))\r
+\r
+/* Watch counter registers */\r
+#define bFM3_WC_WCRD_CTR0                      *((volatile unsigned int*)(0x42740000UL))\r
+#define bFM3_WC_WCRD_CTR1                      *((volatile unsigned int*)(0x42740004UL))\r
+#define bFM3_WC_WCRD_CTR2                      *((volatile unsigned int*)(0x42740008UL))\r
+#define bFM3_WC_WCRD_CTR3                      *((volatile unsigned int*)(0x4274000CUL))\r
+#define bFM3_WC_WCRD_CTR4                      *((volatile unsigned int*)(0x42740010UL))\r
+#define bFM3_WC_WCRD_CTR5                      *((volatile unsigned int*)(0x42740014UL))\r
+#define bFM3_WC_WCRL_RLC0                      *((volatile unsigned int*)(0x42740020UL))\r
+#define bFM3_WC_WCRL_RLC1                      *((volatile unsigned int*)(0x42740024UL))\r
+#define bFM3_WC_WCRL_RLC2                      *((volatile unsigned int*)(0x42740028UL))\r
+#define bFM3_WC_WCRL_RLC3                      *((volatile unsigned int*)(0x4274002CUL))\r
+#define bFM3_WC_WCRL_RLC4                      *((volatile unsigned int*)(0x42740030UL))\r
+#define bFM3_WC_WCRL_RLC5                      *((volatile unsigned int*)(0x42740034UL))\r
+#define bFM3_WC_WCCR_WCIF                      *((volatile unsigned int*)(0x42740040UL))\r
+#define bFM3_WC_WCCR_WCIE                      *((volatile unsigned int*)(0x42740044UL))\r
+#define bFM3_WC_WCCR_CS0                       *((volatile unsigned int*)(0x42740048UL))\r
+#define bFM3_WC_WCCR_CS1                       *((volatile unsigned int*)(0x4274004CUL))\r
+#define bFM3_WC_WCCR_WCOP                      *((volatile unsigned int*)(0x42740058UL))\r
+#define bFM3_WC_WCCR_WCEN                      *((volatile unsigned int*)(0x4274005CUL))\r
+#define bFM3_WC_CLK_SEL_SEL_IN                 *((volatile unsigned int*)(0x42740200UL))\r
+#define bFM3_WC_CLK_SEL_SEL_OUT                *((volatile unsigned int*)(0x42740220UL))\r
+#define bFM3_WC_CLK_EN_CLK_EN                  *((volatile unsigned int*)(0x42740280UL))\r
+#define bFM3_WC_CLK_EN_CLK_EN_R                *((volatile unsigned int*)(0x42740284UL))\r
+\r
+/* External bus interface registers */\r
+#define bFM3_EXBUS_MODE0_WDTH0                 *((volatile unsigned int*)(0x427E0000UL))\r
+#define bFM3_EXBUS_MODE0_WDTH1                 *((volatile unsigned int*)(0x427E0004UL))\r
+#define bFM3_EXBUS_MODE0_RBMON                 *((volatile unsigned int*)(0x427E0008UL))\r
+#define bFM3_EXBUS_MODE0_WEOFF                 *((volatile unsigned int*)(0x427E000CUL))\r
+#define bFM3_EXBUS_MODE0_PAGE                  *((volatile unsigned int*)(0x427E0014UL))\r
+#define bFM3_EXBUS_MODE0_TEST                  *((volatile unsigned int*)(0x427E0018UL))\r
+#define bFM3_EXBUS_MODE1_WDTH0                 *((volatile unsigned int*)(0x427E0080UL))\r
+#define bFM3_EXBUS_MODE1_WDTH1                 *((volatile unsigned int*)(0x427E0084UL))\r
+#define bFM3_EXBUS_MODE1_RBMON                 *((volatile unsigned int*)(0x427E0088UL))\r
+#define bFM3_EXBUS_MODE1_WEOFF                 *((volatile unsigned int*)(0x427E008CUL))\r
+#define bFM3_EXBUS_MODE1_PAGE                  *((volatile unsigned int*)(0x427E0094UL))\r
+#define bFM3_EXBUS_MODE1_TEST                  *((volatile unsigned int*)(0x427E0098UL))\r
+#define bFM3_EXBUS_MODE2_WDTH0                 *((volatile unsigned int*)(0x427E0100UL))\r
+#define bFM3_EXBUS_MODE2_WDTH1                 *((volatile unsigned int*)(0x427E0104UL))\r
+#define bFM3_EXBUS_MODE2_RBMON                 *((volatile unsigned int*)(0x427E0108UL))\r
+#define bFM3_EXBUS_MODE2_WEOFF                 *((volatile unsigned int*)(0x427E010CUL))\r
+#define bFM3_EXBUS_MODE2_PAGE                  *((volatile unsigned int*)(0x427E0114UL))\r
+#define bFM3_EXBUS_MODE2_TEST                  *((volatile unsigned int*)(0x427E0118UL))\r
+#define bFM3_EXBUS_MODE3_WDTH0                 *((volatile unsigned int*)(0x427E0180UL))\r
+#define bFM3_EXBUS_MODE3_WDTH1                 *((volatile unsigned int*)(0x427E0184UL))\r
+#define bFM3_EXBUS_MODE3_RBMON                 *((volatile unsigned int*)(0x427E0188UL))\r
+#define bFM3_EXBUS_MODE3_WEOFF                 *((volatile unsigned int*)(0x427E018CUL))\r
+#define bFM3_EXBUS_MODE3_PAGE                  *((volatile unsigned int*)(0x427E0194UL))\r
+#define bFM3_EXBUS_MODE3_TEST                  *((volatile unsigned int*)(0x427E0198UL))\r
+#define bFM3_EXBUS_MODE7_WDTH0                 *((volatile unsigned int*)(0x427E0380UL))\r
+#define bFM3_EXBUS_MODE7_WDTH1                 *((volatile unsigned int*)(0x427E0384UL))\r
+#define bFM3_EXBUS_MODE7_RBMON                 *((volatile unsigned int*)(0x427E0388UL))\r
+#define bFM3_EXBUS_MODE7_WEOFF                 *((volatile unsigned int*)(0x427E038CUL))\r
+#define bFM3_EXBUS_MODE7_PAGE                  *((volatile unsigned int*)(0x427E0394UL))\r
+#define bFM3_EXBUS_MODE7_TEST                  *((volatile unsigned int*)(0x427E0398UL))\r
+#define bFM3_EXBUS_TIM0_RACC0                  *((volatile unsigned int*)(0x427E0400UL))\r
+#define bFM3_EXBUS_TIM0_RACC1                  *((volatile unsigned int*)(0x427E0404UL))\r
+#define bFM3_EXBUS_TIM0_RACC2                  *((volatile unsigned int*)(0x427E0408UL))\r
+#define bFM3_EXBUS_TIM0_RACC3                  *((volatile unsigned int*)(0x427E040CUL))\r
+#define bFM3_EXBUS_TIM0_RADC0                  *((volatile unsigned int*)(0x427E0410UL))\r
+#define bFM3_EXBUS_TIM0_RADC1                  *((volatile unsigned int*)(0x427E0414UL))\r
+#define bFM3_EXBUS_TIM0_RADC2                  *((volatile unsigned int*)(0x427E0418UL))\r
+#define bFM3_EXBUS_TIM0_RADC3                  *((volatile unsigned int*)(0x427E041CUL))\r
+#define bFM3_EXBUS_TIM0_FRADC0                 *((volatile unsigned int*)(0x427E0420UL))\r
+#define bFM3_EXBUS_TIM0_FRADC1                 *((volatile unsigned int*)(0x427E0424UL))\r
+#define bFM3_EXBUS_TIM0_FRADC2                 *((volatile unsigned int*)(0x427E0428UL))\r
+#define bFM3_EXBUS_TIM0_FRADC3                 *((volatile unsigned int*)(0x427E042CUL))\r
+#define bFM3_EXBUS_TIM0_RIDLC0                 *((volatile unsigned int*)(0x427E0430UL))\r
+#define bFM3_EXBUS_TIM0_RIDLC1                 *((volatile unsigned int*)(0x427E0434UL))\r
+#define bFM3_EXBUS_TIM0_RIDLC2                 *((volatile unsigned int*)(0x427E0438UL))\r
+#define bFM3_EXBUS_TIM0_RIDLC3                 *((volatile unsigned int*)(0x427E043CUL))\r
+#define bFM3_EXBUS_TIM0_WACC0                  *((volatile unsigned int*)(0x427E0440UL))\r
+#define bFM3_EXBUS_TIM0_WACC1                  *((volatile unsigned int*)(0x427E0444UL))\r
+#define bFM3_EXBUS_TIM0_WACC2                  *((volatile unsigned int*)(0x427E0448UL))\r
+#define bFM3_EXBUS_TIM0_WACC3                  *((volatile unsigned int*)(0x427E044CUL))\r
+#define bFM3_EXBUS_TIM0_WADC0                  *((volatile unsigned int*)(0x427E0450UL))\r
+#define bFM3_EXBUS_TIM0_WADC1                  *((volatile unsigned int*)(0x427E0454UL))\r
+#define bFM3_EXBUS_TIM0_WADC2                  *((volatile unsigned int*)(0x427E0458UL))\r
+#define bFM3_EXBUS_TIM0_WADC3                  *((volatile unsigned int*)(0x427E045CUL))\r
+#define bFM3_EXBUS_TIM0_WWEC0                  *((volatile unsigned int*)(0x427E0460UL))\r
+#define bFM3_EXBUS_TIM0_WWEC1                  *((volatile unsigned int*)(0x427E0464UL))\r
+#define bFM3_EXBUS_TIM0_WWEC2                  *((volatile unsigned int*)(0x427E0468UL))\r
+#define bFM3_EXBUS_TIM0_WWEC3                  *((volatile unsigned int*)(0x427E046CUL))\r
+#define bFM3_EXBUS_TIM0_WIDLC0                 *((volatile unsigned int*)(0x427E0470UL))\r
+#define bFM3_EXBUS_TIM0_WIDLC1                 *((volatile unsigned int*)(0x427E0474UL))\r
+#define bFM3_EXBUS_TIM0_WIDLC2                 *((volatile unsigned int*)(0x427E0478UL))\r
+#define bFM3_EXBUS_TIM0_WIDLC3                 *((volatile unsigned int*)(0x427E047CUL))\r
+#define bFM3_EXBUS_TIM1_RACC0                  *((volatile unsigned int*)(0x427E0480UL))\r
+#define bFM3_EXBUS_TIM1_RACC1                  *((volatile unsigned int*)(0x427E0484UL))\r
+#define bFM3_EXBUS_TIM1_RACC2                  *((volatile unsigned int*)(0x427E0488UL))\r
+#define bFM3_EXBUS_TIM1_RACC3                  *((volatile unsigned int*)(0x427E048CUL))\r
+#define bFM3_EXBUS_TIM1_RADC0                  *((volatile unsigned int*)(0x427E0490UL))\r
+#define bFM3_EXBUS_TIM1_RADC1                  *((volatile unsigned int*)(0x427E0494UL))\r
+#define bFM3_EXBUS_TIM1_RADC2                  *((volatile unsigned int*)(0x427E0498UL))\r
+#define bFM3_EXBUS_TIM1_RADC3                  *((volatile unsigned int*)(0x427E049CUL))\r
+#define bFM3_EXBUS_TIM1_FRADC0                 *((volatile unsigned int*)(0x427E04A0UL))\r
+#define bFM3_EXBUS_TIM1_FRADC1                 *((volatile unsigned int*)(0x427E04A4UL))\r
+#define bFM3_EXBUS_TIM1_FRADC2                 *((volatile unsigned int*)(0x427E04A8UL))\r
+#define bFM3_EXBUS_TIM1_FRADC3                 *((volatile unsigned int*)(0x427E04ACUL))\r
+#define bFM3_EXBUS_TIM1_RIDLC0                 *((volatile unsigned int*)(0x427E04B0UL))\r
+#define bFM3_EXBUS_TIM1_RIDLC1                 *((volatile unsigned int*)(0x427E04B4UL))\r
+#define bFM3_EXBUS_TIM1_RIDLC2                 *((volatile unsigned int*)(0x427E04B8UL))\r
+#define bFM3_EXBUS_TIM1_RIDLC3                 *((volatile unsigned int*)(0x427E04BCUL))\r
+#define bFM3_EXBUS_TIM1_WACC0                  *((volatile unsigned int*)(0x427E04C0UL))\r
+#define bFM3_EXBUS_TIM1_WACC1                  *((volatile unsigned int*)(0x427E04C4UL))\r
+#define bFM3_EXBUS_TIM1_WACC2                  *((volatile unsigned int*)(0x427E04C8UL))\r
+#define bFM3_EXBUS_TIM1_WACC3                  *((volatile unsigned int*)(0x427E04CCUL))\r
+#define bFM3_EXBUS_TIM1_WADC0                  *((volatile unsigned int*)(0x427E04D0UL))\r
+#define bFM3_EXBUS_TIM1_WADC1                  *((volatile unsigned int*)(0x427E04D4UL))\r
+#define bFM3_EXBUS_TIM1_WADC2                  *((volatile unsigned int*)(0x427E04D8UL))\r
+#define bFM3_EXBUS_TIM1_WADC3                  *((volatile unsigned int*)(0x427E04DCUL))\r
+#define bFM3_EXBUS_TIM1_WWEC0                  *((volatile unsigned int*)(0x427E04E0UL))\r
+#define bFM3_EXBUS_TIM1_WWEC1                  *((volatile unsigned int*)(0x427E04E4UL))\r
+#define bFM3_EXBUS_TIM1_WWEC2                  *((volatile unsigned int*)(0x427E04E8UL))\r
+#define bFM3_EXBUS_TIM1_WWEC3                  *((volatile unsigned int*)(0x427E04ECUL))\r
+#define bFM3_EXBUS_TIM1_WIDLC0                 *((volatile unsigned int*)(0x427E04F0UL))\r
+#define bFM3_EXBUS_TIM1_WIDLC1                 *((volatile unsigned int*)(0x427E04F4UL))\r
+#define bFM3_EXBUS_TIM1_WIDLC2                 *((volatile unsigned int*)(0x427E04F8UL))\r
+#define bFM3_EXBUS_TIM1_WIDLC3                 *((volatile unsigned int*)(0x427E04FCUL))\r
+#define bFM3_EXBUS_TIM2_RACC0                  *((volatile unsigned int*)(0x427E0500UL))\r
+#define bFM3_EXBUS_TIM2_RACC1                  *((volatile unsigned int*)(0x427E0504UL))\r
+#define bFM3_EXBUS_TIM2_RACC2                  *((volatile unsigned int*)(0x427E0508UL))\r
+#define bFM3_EXBUS_TIM2_RACC3                  *((volatile unsigned int*)(0x427E050CUL))\r
+#define bFM3_EXBUS_TIM2_RADC0                  *((volatile unsigned int*)(0x427E0510UL))\r
+#define bFM3_EXBUS_TIM2_RADC1                  *((volatile unsigned int*)(0x427E0514UL))\r
+#define bFM3_EXBUS_TIM2_RADC2                  *((volatile unsigned int*)(0x427E0518UL))\r
+#define bFM3_EXBUS_TIM2_RADC3                  *((volatile unsigned int*)(0x427E051CUL))\r
+#define bFM3_EXBUS_TIM2_FRADC0                 *((volatile unsigned int*)(0x427E0520UL))\r
+#define bFM3_EXBUS_TIM2_FRADC1                 *((volatile unsigned int*)(0x427E0524UL))\r
+#define bFM3_EXBUS_TIM2_FRADC2                 *((volatile unsigned int*)(0x427E0528UL))\r
+#define bFM3_EXBUS_TIM2_FRADC3                 *((volatile unsigned int*)(0x427E052CUL))\r
+#define bFM3_EXBUS_TIM2_RIDLC0                 *((volatile unsigned int*)(0x427E0530UL))\r
+#define bFM3_EXBUS_TIM2_RIDLC1                 *((volatile unsigned int*)(0x427E0534UL))\r
+#define bFM3_EXBUS_TIM2_RIDLC2                 *((volatile unsigned int*)(0x427E0538UL))\r
+#define bFM3_EXBUS_TIM2_RIDLC3                 *((volatile unsigned int*)(0x427E053CUL))\r
+#define bFM3_EXBUS_TIM2_WACC0                  *((volatile unsigned int*)(0x427E0540UL))\r
+#define bFM3_EXBUS_TIM2_WACC1                  *((volatile unsigned int*)(0x427E0544UL))\r
+#define bFM3_EXBUS_TIM2_WACC2                  *((volatile unsigned int*)(0x427E0548UL))\r
+#define bFM3_EXBUS_TIM2_WACC3                  *((volatile unsigned int*)(0x427E054CUL))\r
+#define bFM3_EXBUS_TIM2_WADC0                  *((volatile unsigned int*)(0x427E0550UL))\r
+#define bFM3_EXBUS_TIM2_WADC1                  *((volatile unsigned int*)(0x427E0554UL))\r
+#define bFM3_EXBUS_TIM2_WADC2                  *((volatile unsigned int*)(0x427E0558UL))\r
+#define bFM3_EXBUS_TIM2_WADC3                  *((volatile unsigned int*)(0x427E055CUL))\r
+#define bFM3_EXBUS_TIM2_WWEC0                  *((volatile unsigned int*)(0x427E0560UL))\r
+#define bFM3_EXBUS_TIM2_WWEC1                  *((volatile unsigned int*)(0x427E0564UL))\r
+#define bFM3_EXBUS_TIM2_WWEC2                  *((volatile unsigned int*)(0x427E0568UL))\r
+#define bFM3_EXBUS_TIM2_WWEC3                  *((volatile unsigned int*)(0x427E056CUL))\r
+#define bFM3_EXBUS_TIM2_WIDLC0                 *((volatile unsigned int*)(0x427E0570UL))\r
+#define bFM3_EXBUS_TIM2_WIDLC1                 *((volatile unsigned int*)(0x427E0574UL))\r
+#define bFM3_EXBUS_TIM2_WIDLC2                 *((volatile unsigned int*)(0x427E0578UL))\r
+#define bFM3_EXBUS_TIM2_WIDLC3                 *((volatile unsigned int*)(0x427E057CUL))\r
+#define bFM3_EXBUS_TIM3_RACC0                  *((volatile unsigned int*)(0x427E0580UL))\r
+#define bFM3_EXBUS_TIM3_RACC1                  *((volatile unsigned int*)(0x427E0584UL))\r
+#define bFM3_EXBUS_TIM3_RACC2                  *((volatile unsigned int*)(0x427E0588UL))\r
+#define bFM3_EXBUS_TIM3_RACC3                  *((volatile unsigned int*)(0x427E058CUL))\r
+#define bFM3_EXBUS_TIM3_RADC0                  *((volatile unsigned int*)(0x427E0590UL))\r
+#define bFM3_EXBUS_TIM3_RADC1                  *((volatile unsigned int*)(0x427E0594UL))\r
+#define bFM3_EXBUS_TIM3_RADC2                  *((volatile unsigned int*)(0x427E0598UL))\r
+#define bFM3_EXBUS_TIM3_RADC3                  *((volatile unsigned int*)(0x427E059CUL))\r
+#define bFM3_EXBUS_TIM3_FRADC0                 *((volatile unsigned int*)(0x427E05A0UL))\r
+#define bFM3_EXBUS_TIM3_FRADC1                 *((volatile unsigned int*)(0x427E05A4UL))\r
+#define bFM3_EXBUS_TIM3_FRADC2                 *((volatile unsigned int*)(0x427E05A8UL))\r
+#define bFM3_EXBUS_TIM3_FRADC3                 *((volatile unsigned int*)(0x427E05ACUL))\r
+#define bFM3_EXBUS_TIM3_RIDLC0                 *((volatile unsigned int*)(0x427E05B0UL))\r
+#define bFM3_EXBUS_TIM3_RIDLC1                 *((volatile unsigned int*)(0x427E05B4UL))\r
+#define bFM3_EXBUS_TIM3_RIDLC2                 *((volatile unsigned int*)(0x427E05B8UL))\r
+#define bFM3_EXBUS_TIM3_RIDLC3                 *((volatile unsigned int*)(0x427E05BCUL))\r
+#define bFM3_EXBUS_TIM3_WACC0                  *((volatile unsigned int*)(0x427E05C0UL))\r
+#define bFM3_EXBUS_TIM3_WACC1                  *((volatile unsigned int*)(0x427E05C4UL))\r
+#define bFM3_EXBUS_TIM3_WACC2                  *((volatile unsigned int*)(0x427E05C8UL))\r
+#define bFM3_EXBUS_TIM3_WACC3                  *((volatile unsigned int*)(0x427E05CCUL))\r
+#define bFM3_EXBUS_TIM3_WADC0                  *((volatile unsigned int*)(0x427E05D0UL))\r
+#define bFM3_EXBUS_TIM3_WADC1                  *((volatile unsigned int*)(0x427E05D4UL))\r
+#define bFM3_EXBUS_TIM3_WADC2                  *((volatile unsigned int*)(0x427E05D8UL))\r
+#define bFM3_EXBUS_TIM3_WADC3                  *((volatile unsigned int*)(0x427E05DCUL))\r
+#define bFM3_EXBUS_TIM3_WWEC0                  *((volatile unsigned int*)(0x427E05E0UL))\r
+#define bFM3_EXBUS_TIM3_WWEC1                  *((volatile unsigned int*)(0x427E05E4UL))\r
+#define bFM3_EXBUS_TIM3_WWEC2                  *((volatile unsigned int*)(0x427E05E8UL))\r
+#define bFM3_EXBUS_TIM3_WWEC3                  *((volatile unsigned int*)(0x427E05ECUL))\r
+#define bFM3_EXBUS_TIM3_WIDLC0                 *((volatile unsigned int*)(0x427E05F0UL))\r
+#define bFM3_EXBUS_TIM3_WIDLC1                 *((volatile unsigned int*)(0x427E05F4UL))\r
+#define bFM3_EXBUS_TIM3_WIDLC2                 *((volatile unsigned int*)(0x427E05F8UL))\r
+#define bFM3_EXBUS_TIM3_WIDLC3                 *((volatile unsigned int*)(0x427E05FCUL))\r
+#define bFM3_EXBUS_TIM7_RACC0                  *((volatile unsigned int*)(0x427E0780UL))\r
+#define bFM3_EXBUS_TIM7_RACC1                  *((volatile unsigned int*)(0x427E0784UL))\r
+#define bFM3_EXBUS_TIM7_RACC2                  *((volatile unsigned int*)(0x427E0788UL))\r
+#define bFM3_EXBUS_TIM7_RACC3                  *((volatile unsigned int*)(0x427E078CUL))\r
+#define bFM3_EXBUS_TIM7_RADC0                  *((volatile unsigned int*)(0x427E0790UL))\r
+#define bFM3_EXBUS_TIM7_RADC1                  *((volatile unsigned int*)(0x427E0794UL))\r
+#define bFM3_EXBUS_TIM7_RADC2                  *((volatile unsigned int*)(0x427E0798UL))\r
+#define bFM3_EXBUS_TIM7_RADC3                  *((volatile unsigned int*)(0x427E079CUL))\r
+#define bFM3_EXBUS_TIM7_FRADC0                 *((volatile unsigned int*)(0x427E07A0UL))\r
+#define bFM3_EXBUS_TIM7_FRADC1                 *((volatile unsigned int*)(0x427E07A4UL))\r
+#define bFM3_EXBUS_TIM7_FRADC2                 *((volatile unsigned int*)(0x427E07A8UL))\r
+#define bFM3_EXBUS_TIM7_FRADC3                 *((volatile unsigned int*)(0x427E07ACUL))\r
+#define bFM3_EXBUS_TIM7_RIDLC0                 *((volatile unsigned int*)(0x427E07B0UL))\r
+#define bFM3_EXBUS_TIM7_RIDLC1                 *((volatile unsigned int*)(0x427E07B4UL))\r
+#define bFM3_EXBUS_TIM7_RIDLC2                 *((volatile unsigned int*)(0x427E07B8UL))\r
+#define bFM3_EXBUS_TIM7_RIDLC3                 *((volatile unsigned int*)(0x427E07BCUL))\r
+#define bFM3_EXBUS_TIM7_WACC0                  *((volatile unsigned int*)(0x427E07C0UL))\r
+#define bFM3_EXBUS_TIM7_WACC1                  *((volatile unsigned int*)(0x427E07C4UL))\r
+#define bFM3_EXBUS_TIM7_WACC2                  *((volatile unsigned int*)(0x427E07C8UL))\r
+#define bFM3_EXBUS_TIM7_WACC3                  *((volatile unsigned int*)(0x427E07CCUL))\r
+#define bFM3_EXBUS_TIM7_WADC0                  *((volatile unsigned int*)(0x427E07D0UL))\r
+#define bFM3_EXBUS_TIM7_WADC1                  *((volatile unsigned int*)(0x427E07D4UL))\r
+#define bFM3_EXBUS_TIM7_WADC2                  *((volatile unsigned int*)(0x427E07D8UL))\r
+#define bFM3_EXBUS_TIM7_WADC3                  *((volatile unsigned int*)(0x427E07DCUL))\r
+#define bFM3_EXBUS_TIM7_WWEC0                  *((volatile unsigned int*)(0x427E07E0UL))\r
+#define bFM3_EXBUS_TIM7_WWEC1                  *((volatile unsigned int*)(0x427E07E4UL))\r
+#define bFM3_EXBUS_TIM7_WWEC2                  *((volatile unsigned int*)(0x427E07E8UL))\r
+#define bFM3_EXBUS_TIM7_WWEC3                  *((volatile unsigned int*)(0x427E07ECUL))\r
+#define bFM3_EXBUS_TIM7_WIDLC0                 *((volatile unsigned int*)(0x427E07F0UL))\r
+#define bFM3_EXBUS_TIM7_WIDLC1                 *((volatile unsigned int*)(0x427E07F4UL))\r
+#define bFM3_EXBUS_TIM7_WIDLC2                 *((volatile unsigned int*)(0x427E07F8UL))\r
+#define bFM3_EXBUS_TIM7_WIDLC3                 *((volatile unsigned int*)(0x427E07FCUL))\r
+#define bFM3_EXBUS_AREA0_ADDR0                 *((volatile unsigned int*)(0x427E0800UL))\r
+#define bFM3_EXBUS_AREA0_ADDR1                 *((volatile unsigned int*)(0x427E0804UL))\r
+#define bFM3_EXBUS_AREA0_ADDR2                 *((volatile unsigned int*)(0x427E0808UL))\r
+#define bFM3_EXBUS_AREA0_ADDR3                 *((volatile unsigned int*)(0x427E080CUL))\r
+#define bFM3_EXBUS_AREA0_ADDR4                 *((volatile unsigned int*)(0x427E0810UL))\r
+#define bFM3_EXBUS_AREA0_ADDR5                 *((volatile unsigned int*)(0x427E0814UL))\r
+#define bFM3_EXBUS_AREA0_ADDR6                 *((volatile unsigned int*)(0x427E0818UL))\r
+#define bFM3_EXBUS_AREA0_ADDR7                 *((volatile unsigned int*)(0x427E081CUL))\r
+#define bFM3_EXBUS_AREA0_MASK0                 *((volatile unsigned int*)(0x427E0840UL))\r
+#define bFM3_EXBUS_AREA0_MASK1                 *((volatile unsigned int*)(0x427E0844UL))\r
+#define bFM3_EXBUS_AREA0_MASK2                 *((volatile unsigned int*)(0x427E0848UL))\r
+#define bFM3_EXBUS_AREA0_MASK3                 *((volatile unsigned int*)(0x427E084CUL))\r
+#define bFM3_EXBUS_AREA0_MASK4                 *((volatile unsigned int*)(0x427E0850UL))\r
+#define bFM3_EXBUS_AREA0_MASK5                 *((volatile unsigned int*)(0x427E0854UL))\r
+#define bFM3_EXBUS_AREA0_MASK6                 *((volatile unsigned int*)(0x427E0858UL))\r
+#define bFM3_EXBUS_AREA1_ADDR0                 *((volatile unsigned int*)(0x427E0880UL))\r
+#define bFM3_EXBUS_AREA1_ADDR1                 *((volatile unsigned int*)(0x427E0884UL))\r
+#define bFM3_EXBUS_AREA1_ADDR2                 *((volatile unsigned int*)(0x427E0888UL))\r
+#define bFM3_EXBUS_AREA1_ADDR3                 *((volatile unsigned int*)(0x427E088CUL))\r
+#define bFM3_EXBUS_AREA1_ADDR4                 *((volatile unsigned int*)(0x427E0890UL))\r
+#define bFM3_EXBUS_AREA1_ADDR5                 *((volatile unsigned int*)(0x427E0894UL))\r
+#define bFM3_EXBUS_AREA1_ADDR6                 *((volatile unsigned int*)(0x427E0898UL))\r
+#define bFM3_EXBUS_AREA1_ADDR7                 *((volatile unsigned int*)(0x427E089CUL))\r
+#define bFM3_EXBUS_AREA1_MASK0                 *((volatile unsigned int*)(0x427E08C0UL))\r
+#define bFM3_EXBUS_AREA1_MASK1                 *((volatile unsigned int*)(0x427E08C4UL))\r
+#define bFM3_EXBUS_AREA1_MASK2                 *((volatile unsigned int*)(0x427E08C8UL))\r
+#define bFM3_EXBUS_AREA1_MASK3                 *((volatile unsigned int*)(0x427E08CCUL))\r
+#define bFM3_EXBUS_AREA1_MASK4                 *((volatile unsigned int*)(0x427E08D0UL))\r
+#define bFM3_EXBUS_AREA1_MASK5                 *((volatile unsigned int*)(0x427E08D4UL))\r
+#define bFM3_EXBUS_AREA1_MASK6                 *((volatile unsigned int*)(0x427E08D8UL))\r
+#define bFM3_EXBUS_AREA2_ADDR0                 *((volatile unsigned int*)(0x427E0900UL))\r
+#define bFM3_EXBUS_AREA2_ADDR1                 *((volatile unsigned int*)(0x427E0904UL))\r
+#define bFM3_EXBUS_AREA2_ADDR2                 *((volatile unsigned int*)(0x427E0908UL))\r
+#define bFM3_EXBUS_AREA2_ADDR3                 *((volatile unsigned int*)(0x427E090CUL))\r
+#define bFM3_EXBUS_AREA2_ADDR4                 *((volatile unsigned int*)(0x427E0910UL))\r
+#define bFM3_EXBUS_AREA2_ADDR5                 *((volatile unsigned int*)(0x427E0914UL))\r
+#define bFM3_EXBUS_AREA2_ADDR6                 *((volatile unsigned int*)(0x427E0918UL))\r
+#define bFM3_EXBUS_AREA2_ADDR7                 *((volatile unsigned int*)(0x427E091CUL))\r
+#define bFM3_EXBUS_AREA2_MASK0                 *((volatile unsigned int*)(0x427E0940UL))\r
+#define bFM3_EXBUS_AREA2_MASK1                 *((volatile unsigned int*)(0x427E0944UL))\r
+#define bFM3_EXBUS_AREA2_MASK2                 *((volatile unsigned int*)(0x427E0948UL))\r
+#define bFM3_EXBUS_AREA2_MASK3                 *((volatile unsigned int*)(0x427E094CUL))\r
+#define bFM3_EXBUS_AREA2_MASK4                 *((volatile unsigned int*)(0x427E0950UL))\r
+#define bFM3_EXBUS_AREA2_MASK5                 *((volatile unsigned int*)(0x427E0954UL))\r
+#define bFM3_EXBUS_AREA2_MASK6                 *((volatile unsigned int*)(0x427E0958UL))\r
+#define bFM3_EXBUS_AREA3_ADDR0                 *((volatile unsigned int*)(0x427E0980UL))\r
+#define bFM3_EXBUS_AREA3_ADDR1                 *((volatile unsigned int*)(0x427E0984UL))\r
+#define bFM3_EXBUS_AREA3_ADDR2                 *((volatile unsigned int*)(0x427E0988UL))\r
+#define bFM3_EXBUS_AREA3_ADDR3                 *((volatile unsigned int*)(0x427E098CUL))\r
+#define bFM3_EXBUS_AREA3_ADDR4                 *((volatile unsigned int*)(0x427E0990UL))\r
+#define bFM3_EXBUS_AREA3_ADDR5                 *((volatile unsigned int*)(0x427E0994UL))\r
+#define bFM3_EXBUS_AREA3_ADDR6                 *((volatile unsigned int*)(0x427E0998UL))\r
+#define bFM3_EXBUS_AREA3_ADDR7                 *((volatile unsigned int*)(0x427E099CUL))\r
+#define bFM3_EXBUS_AREA3_MASK0                 *((volatile unsigned int*)(0x427E09C0UL))\r
+#define bFM3_EXBUS_AREA3_MASK1                 *((volatile unsigned int*)(0x427E09C4UL))\r
+#define bFM3_EXBUS_AREA3_MASK2                 *((volatile unsigned int*)(0x427E09C8UL))\r
+#define bFM3_EXBUS_AREA3_MASK3                 *((volatile unsigned int*)(0x427E09CCUL))\r
+#define bFM3_EXBUS_AREA3_MASK4                 *((volatile unsigned int*)(0x427E09D0UL))\r
+#define bFM3_EXBUS_AREA3_MASK5                 *((volatile unsigned int*)(0x427E09D4UL))\r
+#define bFM3_EXBUS_AREA3_MASK6                 *((volatile unsigned int*)(0x427E09D8UL))\r
+#define bFM3_EXBUS_AREA7_ADDR0                 *((volatile unsigned int*)(0x427E0B80UL))\r
+#define bFM3_EXBUS_AREA7_ADDR1                 *((volatile unsigned int*)(0x427E0B84UL))\r
+#define bFM3_EXBUS_AREA7_ADDR2                 *((volatile unsigned int*)(0x427E0B88UL))\r
+#define bFM3_EXBUS_AREA7_ADDR3                 *((volatile unsigned int*)(0x427E0B8CUL))\r
+#define bFM3_EXBUS_AREA7_ADDR4                 *((volatile unsigned int*)(0x427E0B90UL))\r
+#define bFM3_EXBUS_AREA7_ADDR5                 *((volatile unsigned int*)(0x427E0B94UL))\r
+#define bFM3_EXBUS_AREA7_ADDR6                 *((volatile unsigned int*)(0x427E0B98UL))\r
+#define bFM3_EXBUS_AREA7_ADDR7                 *((volatile unsigned int*)(0x427E0B9CUL))\r
+#define bFM3_EXBUS_AREA7_MASK0                 *((volatile unsigned int*)(0x427E0BC0UL))\r
+#define bFM3_EXBUS_AREA7_MASK1                 *((volatile unsigned int*)(0x427E0BC4UL))\r
+#define bFM3_EXBUS_AREA7_MASK2                 *((volatile unsigned int*)(0x427E0BC8UL))\r
+#define bFM3_EXBUS_AREA7_MASK3                 *((volatile unsigned int*)(0x427E0BCCUL))\r
+#define bFM3_EXBUS_AREA7_MASK4                 *((volatile unsigned int*)(0x427E0BD0UL))\r
+#define bFM3_EXBUS_AREA7_MASK5                 *((volatile unsigned int*)(0x427E0BD4UL))\r
+#define bFM3_EXBUS_AREA7_MASK6                 *((volatile unsigned int*)(0x427E0BD8UL))\r
+\r
+/* USB channel 0 registers */\r
+#define bFM3_USB0_HCNT_HOST                    *((volatile unsigned int*)(0x42842000UL))\r
+#define bFM3_USB0_HCNT_URST                    *((volatile unsigned int*)(0x42842004UL))\r
+#define bFM3_USB0_HCNT_SOFIRE                  *((volatile unsigned int*)(0x42842008UL))\r
+#define bFM3_USB0_HCNT_DIRE                    *((volatile unsigned int*)(0x4284200CUL))\r
+#define bFM3_USB0_HCNT_CNNIRE                  *((volatile unsigned int*)(0x42842010UL))\r
+#define bFM3_USB0_HCNT_CMPIRE                  *((volatile unsigned int*)(0x42842014UL))\r
+#define bFM3_USB0_HCNT_URIRE                   *((volatile unsigned int*)(0x42842018UL))\r
+#define bFM3_USB0_HCNT_RWKIRE                  *((volatile unsigned int*)(0x4284201CUL))\r
+#define bFM3_USB0_HCNT_RETRY                   *((volatile unsigned int*)(0x42842020UL))\r
+#define bFM3_USB0_HCNT_CANCEL                  *((volatile unsigned int*)(0x42842024UL))\r
+#define bFM3_USB0_HCNT_SOFSTEP                 *((volatile unsigned int*)(0x42842028UL))\r
+#define bFM3_USB0_HCNT0_HOST                   *((volatile unsigned int*)(0x42842000UL))\r
+#define bFM3_USB0_HCNT0_URST                   *((volatile unsigned int*)(0x42842004UL))\r
+#define bFM3_USB0_HCNT0_SOFIRE                 *((volatile unsigned int*)(0x42842008UL))\r
+#define bFM3_USB0_HCNT0_DIRE                   *((volatile unsigned int*)(0x4284200CUL))\r
+#define bFM3_USB0_HCNT0_CNNIRE                 *((volatile unsigned int*)(0x42842010UL))\r
+#define bFM3_USB0_HCNT0_CMPIRE                 *((volatile unsigned int*)(0x42842014UL))\r
+#define bFM3_USB0_HCNT0_URIRE                  *((volatile unsigned int*)(0x42842018UL))\r
+#define bFM3_USB0_HCNT0_RWKIRE                 *((volatile unsigned int*)(0x4284201CUL))\r
+#define bFM3_USB0_HCNT1_RETRY                  *((volatile unsigned int*)(0x42842020UL))\r
+#define bFM3_USB0_HCNT1_CANCEL                 *((volatile unsigned int*)(0x42842024UL))\r
+#define bFM3_USB0_HCNT1_SOFSTEP                *((volatile unsigned int*)(0x42842028UL))\r
+#define bFM3_USB0_HIRQ_SOFIRQ                  *((volatile unsigned int*)(0x42842080UL))\r
+#define bFM3_USB0_HIRQ_DIRQ                    *((volatile unsigned int*)(0x42842084UL))\r
+#define bFM3_USB0_HIRQ_CNNIRQ                  *((volatile unsigned int*)(0x42842088UL))\r
+#define bFM3_USB0_HIRQ_CMPIRQ                  *((volatile unsigned int*)(0x4284208CUL))\r
+#define bFM3_USB0_HIRQ_URIRQ                   *((volatile unsigned int*)(0x42842090UL))\r
+#define bFM3_USB0_HIRQ_RWKIRQ                  *((volatile unsigned int*)(0x42842094UL))\r
+#define bFM3_USB0_HIRQ_TCAN                    *((volatile unsigned int*)(0x4284209CUL))\r
+#define bFM3_USB0_HERR_HS0                     *((volatile unsigned int*)(0x428420A0UL))\r
+#define bFM3_USB0_HERR_HS1                     *((volatile unsigned int*)(0x428420A4UL))\r
+#define bFM3_USB0_HERR_STUFF                   *((volatile unsigned int*)(0x428420A8UL))\r
+#define bFM3_USB0_HERR_TGERR                   *((volatile unsigned int*)(0x428420ACUL))\r
+#define bFM3_USB0_HERR_CRC                     *((volatile unsigned int*)(0x428420B0UL))\r
+#define bFM3_USB0_HERR_TOUT                    *((volatile unsigned int*)(0x428420B4UL))\r
+#define bFM3_USB0_HERR_RERR                    *((volatile unsigned int*)(0x428420B8UL))\r
+#define bFM3_USB0_HERR_LSTOF                   *((volatile unsigned int*)(0x428420BCUL))\r
+#define bFM3_USB0_HSTATE_CSTAT                 *((volatile unsigned int*)(0x42842100UL))\r
+#define bFM3_USB0_HSTATE_TMODE                 *((volatile unsigned int*)(0x42842104UL))\r
+#define bFM3_USB0_HSTATE_SUSP                  *((volatile unsigned int*)(0x42842108UL))\r
+#define bFM3_USB0_HSTATE_SOFBUSY               *((volatile unsigned int*)(0x4284210CUL))\r
+#define bFM3_USB0_HSTATE_CLKSEL                *((volatile unsigned int*)(0x42842110UL))\r
+#define bFM3_USB0_HSTATE_ALIVE                 *((volatile unsigned int*)(0x42842114UL))\r
+#define bFM3_USB0_HFCOMP_FRAMECOMP0            *((volatile unsigned int*)(0x42842120UL))\r
+#define bFM3_USB0_HFCOMP_FRAMECOMP1            *((volatile unsigned int*)(0x42842124UL))\r
+#define bFM3_USB0_HFCOMP_FRAMECOMP2            *((volatile unsigned int*)(0x42842128UL))\r
+#define bFM3_USB0_HFCOMP_FRAMECOMP3            *((volatile unsigned int*)(0x4284212CUL))\r
+#define bFM3_USB0_HFCOMP_FRAMECOMP4            *((volatile unsigned int*)(0x42842130UL))\r
+#define bFM3_USB0_HFCOMP_FRAMECOMP5            *((volatile unsigned int*)(0x42842134UL))\r
+#define bFM3_USB0_HFCOMP_FRAMECOMP6            *((volatile unsigned int*)(0x42842138UL))\r
+#define bFM3_USB0_HFCOMP_FRAMECOMP7            *((volatile unsigned int*)(0x4284213CUL))\r
+#define bFM3_USB0_HRTIMER_RTIMER0              *((volatile unsigned int*)(0x42842180UL))\r
+#define bFM3_USB0_HRTIMER_RTIMER1              *((volatile unsigned int*)(0x42842184UL))\r
+#define bFM3_USB0_HRTIMER_RTIMER2              *((volatile unsigned int*)(0x42842188UL))\r
+#define bFM3_USB0_HRTIMER_RTIMER3              *((volatile unsigned int*)(0x4284218CUL))\r
+#define bFM3_USB0_HRTIMER_RTIMER4              *((volatile unsigned int*)(0x42842190UL))\r
+#define bFM3_USB0_HRTIMER_RTIMER5              *((volatile unsigned int*)(0x42842194UL))\r
+#define bFM3_USB0_HRTIMER_RTIMER6              *((volatile unsigned int*)(0x42842198UL))\r
+#define bFM3_USB0_HRTIMER_RTIMER7              *((volatile unsigned int*)(0x4284219CUL))\r
+#define bFM3_USB0_HRTIMER_RTIMER8              *((volatile unsigned int*)(0x428421A0UL))\r
+#define bFM3_USB0_HRTIMER_RTIMER9              *((volatile unsigned int*)(0x428421A4UL))\r
+#define bFM3_USB0_HRTIMER_RTIMER10             *((volatile unsigned int*)(0x428421A8UL))\r
+#define bFM3_USB0_HRTIMER_RTIMER11             *((volatile unsigned int*)(0x428421ACUL))\r
+#define bFM3_USB0_HRTIMER_RTIMER12             *((volatile unsigned int*)(0x428421B0UL))\r
+#define bFM3_USB0_HRTIMER_RTIMER13             *((volatile unsigned int*)(0x428421B4UL))\r
+#define bFM3_USB0_HRTIMER_RTIMER14             *((volatile unsigned int*)(0x428421B8UL))\r
+#define bFM3_USB0_HRTIMER_RTIMER15             *((volatile unsigned int*)(0x428421BCUL))\r
+#define bFM3_USB0_HRTIMER0_RTIMER00            *((volatile unsigned int*)(0x42842180UL))\r
+#define bFM3_USB0_HRTIMER0_RTIMER01            *((volatile unsigned int*)(0x42842184UL))\r
+#define bFM3_USB0_HRTIMER0_RTIMER02            *((volatile unsigned int*)(0x42842188UL))\r
+#define bFM3_USB0_HRTIMER0_RTIMER03            *((volatile unsigned int*)(0x4284218CUL))\r
+#define bFM3_USB0_HRTIMER0_RTIMER04            *((volatile unsigned int*)(0x42842190UL))\r
+#define bFM3_USB0_HRTIMER0_RTIMER05            *((volatile unsigned int*)(0x42842194UL))\r
+#define bFM3_USB0_HRTIMER0_RTIMER06            *((volatile unsigned int*)(0x42842198UL))\r
+#define bFM3_USB0_HRTIMER0_RTIMER07            *((volatile unsigned int*)(0x4284219CUL))\r
+#define bFM3_USB0_HRTIMER1_RTIMER10            *((volatile unsigned int*)(0x428421A0UL))\r
+#define bFM3_USB0_HRTIMER1_RTIMER11            *((volatile unsigned int*)(0x428421A4UL))\r
+#define bFM3_USB0_HRTIMER1_RTIMER12            *((volatile unsigned int*)(0x428421A8UL))\r
+#define bFM3_USB0_HRTIMER1_RTIMER13            *((volatile unsigned int*)(0x428421ACUL))\r
+#define bFM3_USB0_HRTIMER1_RTIMER14            *((volatile unsigned int*)(0x428421B0UL))\r
+#define bFM3_USB0_HRTIMER1_RTIMER15            *((volatile unsigned int*)(0x428421B4UL))\r
+#define bFM3_USB0_HRTIMER1_RTIMER16            *((volatile unsigned int*)(0x428421B8UL))\r
+#define bFM3_USB0_HRTIMER1_RTIMER17            *((volatile unsigned int*)(0x428421BCUL))\r
+#define bFM3_USB0_HRTIMER2_RTIMER20            *((volatile unsigned int*)(0x42842200UL))\r
+#define bFM3_USB0_HRTIMER2_RTIMER21            *((volatile unsigned int*)(0x42842204UL))\r
+#define bFM3_USB0_HRTIMER2_RTIMER22            *((volatile unsigned int*)(0x42842208UL))\r
+#define bFM3_USB0_HADR_ADDRESS0                *((volatile unsigned int*)(0x42842220UL))\r
+#define bFM3_USB0_HADR_ADDRESS1                *((volatile unsigned int*)(0x42842224UL))\r
+#define bFM3_USB0_HADR_ADDRESS2                *((volatile unsigned int*)(0x42842228UL))\r
+#define bFM3_USB0_HADR_ADDRESS3                *((volatile unsigned int*)(0x4284222CUL))\r
+#define bFM3_USB0_HADR_ADDRESS4                *((volatile unsigned int*)(0x42842230UL))\r
+#define bFM3_USB0_HADR_ADDRESS5                *((volatile unsigned int*)(0x42842234UL))\r
+#define bFM3_USB0_HADR_ADDRESS6                *((volatile unsigned int*)(0x42842238UL))\r
+#define bFM3_USB0_HEOF_EOF0                    *((volatile unsigned int*)(0x42842280UL))\r
+#define bFM3_USB0_HEOF_EOF1                    *((volatile unsigned int*)(0x42842284UL))\r
+#define bFM3_USB0_HEOF_EOF2                    *((volatile unsigned int*)(0x42842288UL))\r
+#define bFM3_USB0_HEOF_EOF3                    *((volatile unsigned int*)(0x4284228CUL))\r
+#define bFM3_USB0_HEOF_EOF4                    *((volatile unsigned int*)(0x42842290UL))\r
+#define bFM3_USB0_HEOF_EOF5                    *((volatile unsigned int*)(0x42842294UL))\r
+#define bFM3_USB0_HEOF_EOF6                    *((volatile unsigned int*)(0x42842298UL))\r
+#define bFM3_USB0_HEOF_EOF7                    *((volatile unsigned int*)(0x4284229CUL))\r
+#define bFM3_USB0_HEOF_EOF8                    *((volatile unsigned int*)(0x428422A0UL))\r
+#define bFM3_USB0_HEOF_EOF9                    *((volatile unsigned int*)(0x428422A4UL))\r
+#define bFM3_USB0_HEOF_EOF10                   *((volatile unsigned int*)(0x428422A8UL))\r
+#define bFM3_USB0_HEOF_EOF11                   *((volatile unsigned int*)(0x428422ACUL))\r
+#define bFM3_USB0_HEOF_EOF12                   *((volatile unsigned int*)(0x428422B0UL))\r
+#define bFM3_USB0_HEOF_EOF13                   *((volatile unsigned int*)(0x428422B4UL))\r
+#define bFM3_USB0_HEOF_EOF14                   *((volatile unsigned int*)(0x428422B8UL))\r
+#define bFM3_USB0_HEOF_EOF15                   *((volatile unsigned int*)(0x428422BCUL))\r
+#define bFM3_USB0_HEOF0_EOF00                  *((volatile unsigned int*)(0x42842280UL))\r
+#define bFM3_USB0_HEOF0_EOF01                  *((volatile unsigned int*)(0x42842284UL))\r
+#define bFM3_USB0_HEOF0_EOF02                  *((volatile unsigned int*)(0x42842288UL))\r
+#define bFM3_USB0_HEOF0_EOF03                  *((volatile unsigned int*)(0x4284228CUL))\r
+#define bFM3_USB0_HEOF0_EOF04                  *((volatile unsigned int*)(0x42842290UL))\r
+#define bFM3_USB0_HEOF0_EOF05                  *((volatile unsigned int*)(0x42842294UL))\r
+#define bFM3_USB0_HEOF0_EOF06                  *((volatile unsigned int*)(0x42842298UL))\r
+#define bFM3_USB0_HEOF0_EOF07                  *((volatile unsigned int*)(0x4284229CUL))\r
+#define bFM3_USB0_HEOF1_EOF10                  *((volatile unsigned int*)(0x428422A0UL))\r
+#define bFM3_USB0_HEOF1_EOF11                  *((volatile unsigned int*)(0x428422A4UL))\r
+#define bFM3_USB0_HEOF1_EOF12                  *((volatile unsigned int*)(0x428422A8UL))\r
+#define bFM3_USB0_HEOF1_EOF13                  *((volatile unsigned int*)(0x428422ACUL))\r
+#define bFM3_USB0_HEOF1_EOF14                  *((volatile unsigned int*)(0x428422B0UL))\r
+#define bFM3_USB0_HEOF1_EOF15                  *((volatile unsigned int*)(0x428422B4UL))\r
+#define bFM3_USB0_HFRAME_FRAME0                *((volatile unsigned int*)(0x42842300UL))\r
+#define bFM3_USB0_HFRAME_FRAME1                *((volatile unsigned int*)(0x42842304UL))\r
+#define bFM3_USB0_HFRAME_FRAME2                *((volatile unsigned int*)(0x42842308UL))\r
+#define bFM3_USB0_HFRAME_FRAME3                *((volatile unsigned int*)(0x4284230CUL))\r
+#define bFM3_USB0_HFRAME_FRAME4                *((volatile unsigned int*)(0x42842310UL))\r
+#define bFM3_USB0_HFRAME_FRAME5                *((volatile unsigned int*)(0x42842314UL))\r
+#define bFM3_USB0_HFRAME_FRAME6                *((volatile unsigned int*)(0x42842318UL))\r
+#define bFM3_USB0_HFRAME_FRAME7                *((volatile unsigned int*)(0x4284231CUL))\r
+#define bFM3_USB0_HFRAME_FRAME8                *((volatile unsigned int*)(0x42842320UL))\r
+#define bFM3_USB0_HFRAME_FRAME9                *((volatile unsigned int*)(0x42842324UL))\r
+#define bFM3_USB0_HFRAME_FRAME10               *((volatile unsigned int*)(0x42842328UL))\r
+#define bFM3_USB0_HFRAME0_FRAME00              *((volatile unsigned int*)(0x42842300UL))\r
+#define bFM3_USB0_HFRAME0_FRAME01              *((volatile unsigned int*)(0x42842304UL))\r
+#define bFM3_USB0_HFRAME0_FRAME02              *((volatile unsigned int*)(0x42842308UL))\r
+#define bFM3_USB0_HFRAME0_FRAME03              *((volatile unsigned int*)(0x4284230CUL))\r
+#define bFM3_USB0_HFRAME0_FRAME04              *((volatile unsigned int*)(0x42842310UL))\r
+#define bFM3_USB0_HFRAME0_FRAME05              *((volatile unsigned int*)(0x42842314UL))\r
+#define bFM3_USB0_HFRAME0_FRAME06              *((volatile unsigned int*)(0x42842318UL))\r
+#define bFM3_USB0_HFRAME0_FRAME07              *((volatile unsigned int*)(0x4284231CUL))\r
+#define bFM3_USB0_HFRAME1_FRAME10              *((volatile unsigned int*)(0x42842320UL))\r
+#define bFM3_USB0_HFRAME1_FRAME11              *((volatile unsigned int*)(0x42842324UL))\r
+#define bFM3_USB0_HFRAME1_FRAME12              *((volatile unsigned int*)(0x42842328UL))\r
+#define bFM3_USB0_HFRAME1_FRAME13              *((volatile unsigned int*)(0x4284232CUL))\r
+#define bFM3_USB0_HTOKEN_ENDPT0                *((volatile unsigned int*)(0x42842380UL))\r
+#define bFM3_USB0_HTOKEN_ENDPT1                *((volatile unsigned int*)(0x42842384UL))\r
+#define bFM3_USB0_HTOKEN_ENDPT2                *((volatile unsigned int*)(0x42842388UL))\r
+#define bFM3_USB0_HTOKEN_ENDPT3                *((volatile unsigned int*)(0x4284238CUL))\r
+#define bFM3_USB0_HTOKEN_TKNEN0                *((volatile unsigned int*)(0x42842390UL))\r
+#define bFM3_USB0_HTOKEN_TKNEN1                *((volatile unsigned int*)(0x42842394UL))\r
+#define bFM3_USB0_HTOKEN_TKNEN2                *((volatile unsigned int*)(0x42842398UL))\r
+#define bFM3_USB0_HTOKEN_TGGL                  *((volatile unsigned int*)(0x4284239CUL))\r
+#define bFM3_USB0_UDCC_PWC                     *((volatile unsigned int*)(0x42842400UL))\r
+#define bFM3_USB0_UDCC_RFBK                    *((volatile unsigned int*)(0x42842404UL))\r
+#define bFM3_USB0_UDCC_STALCLREN               *((volatile unsigned int*)(0x4284240CUL))\r
+#define bFM3_USB0_UDCC_USTP                    *((volatile unsigned int*)(0x42842410UL))\r
+#define bFM3_USB0_UDCC_HCONX                   *((volatile unsigned int*)(0x42842414UL))\r
+#define bFM3_USB0_UDCC_RESUM                   *((volatile unsigned int*)(0x42842418UL))\r
+#define bFM3_USB0_UDCC_RST                     *((volatile unsigned int*)(0x4284241CUL))\r
+#define bFM3_USB0_EP0C_PKS00                   *((volatile unsigned int*)(0x42842480UL))\r
+#define bFM3_USB0_EP0C_PKS01                   *((volatile unsigned int*)(0x42842484UL))\r
+#define bFM3_USB0_EP0C_PKS02                   *((volatile unsigned int*)(0x42842488UL))\r
+#define bFM3_USB0_EP0C_PKS03                   *((volatile unsigned int*)(0x4284248CUL))\r
+#define bFM3_USB0_EP0C_PKS04                   *((volatile unsigned int*)(0x42842490UL))\r
+#define bFM3_USB0_EP0C_PKS05                   *((volatile unsigned int*)(0x42842494UL))\r
+#define bFM3_USB0_EP0C_PKS06                   *((volatile unsigned int*)(0x42842498UL))\r
+#define bFM3_USB0_EP0C_STAL                    *((volatile unsigned int*)(0x428424A4UL))\r
+#define bFM3_USB0_EP1C_PKS10                   *((volatile unsigned int*)(0x42842500UL))\r
+#define bFM3_USB0_EP1C_PKS11                   *((volatile unsigned int*)(0x42842504UL))\r
+#define bFM3_USB0_EP1C_PKS12                   *((volatile unsigned int*)(0x42842508UL))\r
+#define bFM3_USB0_EP1C_PKS13                   *((volatile unsigned int*)(0x4284250CUL))\r
+#define bFM3_USB0_EP1C_PKS14                   *((volatile unsigned int*)(0x42842510UL))\r
+#define bFM3_USB0_EP1C_PKS15                   *((volatile unsigned int*)(0x42842514UL))\r
+#define bFM3_USB0_EP1C_PKS16                   *((volatile unsigned int*)(0x42842518UL))\r
+#define bFM3_USB0_EP1C_PKS17                   *((volatile unsigned int*)(0x4284251CUL))\r
+#define bFM3_USB0_EP1C_PSK18                   *((volatile unsigned int*)(0x42842520UL))\r
+#define bFM3_USB0_EP1C_STAL                    *((volatile unsigned int*)(0x42842524UL))\r
+#define bFM3_USB0_EP1C_NULE                    *((volatile unsigned int*)(0x42842528UL))\r
+#define bFM3_USB0_EP1C_DMAE                    *((volatile unsigned int*)(0x4284252CUL))\r
+#define bFM3_USB0_EP1C_DIR                     *((volatile unsigned int*)(0x42842530UL))\r
+#define bFM3_USB0_EP1C_TYPE0                   *((volatile unsigned int*)(0x42842534UL))\r
+#define bFM3_USB0_EP1C_TYPE1                   *((volatile unsigned int*)(0x42842538UL))\r
+#define bFM3_USB0_EP1C_EPEN                    *((volatile unsigned int*)(0x4284253CUL))\r
+#define bFM3_USB0_EP2C_PKS20                   *((volatile unsigned int*)(0x42842580UL))\r
+#define bFM3_USB0_EP2C_PKS21                   *((volatile unsigned int*)(0x42842584UL))\r
+#define bFM3_USB0_EP2C_PKS22                   *((volatile unsigned int*)(0x42842588UL))\r
+#define bFM3_USB0_EP2C_PKS23                   *((volatile unsigned int*)(0x4284258CUL))\r
+#define bFM3_USB0_EP2C_PKS24                   *((volatile unsigned int*)(0x42842590UL))\r
+#define bFM3_USB0_EP2C_PKS25                   *((volatile unsigned int*)(0x42842594UL))\r
+#define bFM3_USB0_EP2C_PKS26                   *((volatile unsigned int*)(0x42842598UL))\r
+#define bFM3_USB0_EP2C_STAL                    *((volatile unsigned int*)(0x428425A4UL))\r
+#define bFM3_USB0_EP2C_NULE                    *((volatile unsigned int*)(0x428425A8UL))\r
+#define bFM3_USB0_EP2C_DMAE                    *((volatile unsigned int*)(0x428425ACUL))\r
+#define bFM3_USB0_EP2C_DIR                     *((volatile unsigned int*)(0x428425B0UL))\r
+#define bFM3_USB0_EP2C_TYPE0                   *((volatile unsigned int*)(0x428425B4UL))\r
+#define bFM3_USB0_EP2C_TYPE1                   *((volatile unsigned int*)(0x428425B8UL))\r
+#define bFM3_USB0_EP2C_EPEN                    *((volatile unsigned int*)(0x428425BCUL))\r
+#define bFM3_USB0_EP3C_PKS30                   *((volatile unsigned int*)(0x42842600UL))\r
+#define bFM3_USB0_EP3C_PKS31                   *((volatile unsigned int*)(0x42842604UL))\r
+#define bFM3_USB0_EP3C_PKS32                   *((volatile unsigned int*)(0x42842608UL))\r
+#define bFM3_USB0_EP3C_PKS33                   *((volatile unsigned int*)(0x4284260CUL))\r
+#define bFM3_USB0_EP3C_PKS34                   *((volatile unsigned int*)(0x42842610UL))\r
+#define bFM3_USB0_EP3C_PKS35                   *((volatile unsigned int*)(0x42842614UL))\r
+#define bFM3_USB0_EP3C_PKS36                   *((volatile unsigned int*)(0x42842618UL))\r
+#define bFM3_USB0_EP3C_STAL                    *((volatile unsigned int*)(0x42842624UL))\r
+#define bFM3_USB0_EP3C_NULE                    *((volatile unsigned int*)(0x42842628UL))\r
+#define bFM3_USB0_EP3C_DMAE                    *((volatile unsigned int*)(0x4284262CUL))\r
+#define bFM3_USB0_EP3C_DIR                     *((volatile unsigned int*)(0x42842630UL))\r
+#define bFM3_USB0_EP3C_TYPE0                   *((volatile unsigned int*)(0x42842634UL))\r
+#define bFM3_USB0_EP3C_TYPE1                   *((volatile unsigned int*)(0x42842638UL))\r
+#define bFM3_USB0_EP3C_EPEN                    *((volatile unsigned int*)(0x4284263CUL))\r
+#define bFM3_USB0_EP4C_PKS40                   *((volatile unsigned int*)(0x42842680UL))\r
+#define bFM3_USB0_EP4C_PKS41                   *((volatile unsigned int*)(0x42842684UL))\r
+#define bFM3_USB0_EP4C_PKS42                   *((volatile unsigned int*)(0x42842688UL))\r
+#define bFM3_USB0_EP4C_PKS43                   *((volatile unsigned int*)(0x4284268CUL))\r
+#define bFM3_USB0_EP4C_PKS44                   *((volatile unsigned int*)(0x42842690UL))\r
+#define bFM3_USB0_EP4C_PKS45                   *((volatile unsigned int*)(0x42842694UL))\r
+#define bFM3_USB0_EP4C_PKS46                   *((volatile unsigned int*)(0x42842698UL))\r
+#define bFM3_USB0_EP4C_STAL                    *((volatile unsigned int*)(0x428426A4UL))\r
+#define bFM3_USB0_EP4C_NULE                    *((volatile unsigned int*)(0x428426A8UL))\r
+#define bFM3_USB0_EP4C_DMAE                    *((volatile unsigned int*)(0x428426ACUL))\r
+#define bFM3_USB0_EP4C_DIR                     *((volatile unsigned int*)(0x428426B0UL))\r
+#define bFM3_USB0_EP4C_TYPE0                   *((volatile unsigned int*)(0x428426B4UL))\r
+#define bFM3_USB0_EP4C_TYPE1                   *((volatile unsigned int*)(0x428426B8UL))\r
+#define bFM3_USB0_EP4C_EPEN                    *((volatile unsigned int*)(0x428426BCUL))\r
+#define bFM3_USB0_EP5C_PKS50                   *((volatile unsigned int*)(0x42842700UL))\r
+#define bFM3_USB0_EP5C_PKS51                   *((volatile unsigned int*)(0x42842704UL))\r
+#define bFM3_USB0_EP5C_PKS52                   *((volatile unsigned int*)(0x42842708UL))\r
+#define bFM3_USB0_EP5C_PKS53                   *((volatile unsigned int*)(0x4284270CUL))\r
+#define bFM3_USB0_EP5C_PKS54                   *((volatile unsigned int*)(0x42842710UL))\r
+#define bFM3_USB0_EP5C_PKS55                   *((volatile unsigned int*)(0x42842714UL))\r
+#define bFM3_USB0_EP5C_PKS56                   *((volatile unsigned int*)(0x42842718UL))\r
+#define bFM3_USB0_EP5C_STAL                    *((volatile unsigned int*)(0x42842724UL))\r
+#define bFM3_USB0_EP5C_NULE                    *((volatile unsigned int*)(0x42842728UL))\r
+#define bFM3_USB0_EP5C_DMAE                    *((volatile unsigned int*)(0x4284272CUL))\r
+#define bFM3_USB0_EP5C_DIR                     *((volatile unsigned int*)(0x42842730UL))\r
+#define bFM3_USB0_EP5C_TYPE0                   *((volatile unsigned int*)(0x42842734UL))\r
+#define bFM3_USB0_EP5C_TYPE1                   *((volatile unsigned int*)(0x42842738UL))\r
+#define bFM3_USB0_EP5C_EPEN                    *((volatile unsigned int*)(0x4284273CUL))\r
+#define bFM3_USB0_TMSP_TMSP0                   *((volatile unsigned int*)(0x42842780UL))\r
+#define bFM3_USB0_TMSP_TMSP1                   *((volatile unsigned int*)(0x42842784UL))\r
+#define bFM3_USB0_TMSP_TMSP2                   *((volatile unsigned int*)(0x42842788UL))\r
+#define bFM3_USB0_TMSP_TMSP3                   *((volatile unsigned int*)(0x4284278CUL))\r
+#define bFM3_USB0_TMSP_TMSP4                   *((volatile unsigned int*)(0x42842790UL))\r
+#define bFM3_USB0_TMSP_TMSP5                   *((volatile unsigned int*)(0x42842794UL))\r
+#define bFM3_USB0_TMSP_TMSP6                   *((volatile unsigned int*)(0x42842798UL))\r
+#define bFM3_USB0_TMSP_TMSP7                   *((volatile unsigned int*)(0x4284279CUL))\r
+#define bFM3_USB0_TMSP_TMSP8                   *((volatile unsigned int*)(0x428427A0UL))\r
+#define bFM3_USB0_TMSP_TMSP9                   *((volatile unsigned int*)(0x428427A4UL))\r
+#define bFM3_USB0_TMSP_TMSP10                  *((volatile unsigned int*)(0x428427A8UL))\r
+#define bFM3_USB0_UDCS_CONF                    *((volatile unsigned int*)(0x42842800UL))\r
+#define bFM3_USB0_UDCS_SETP                    *((volatile unsigned int*)(0x42842804UL))\r
+#define bFM3_USB0_UDCS_WKUP                    *((volatile unsigned int*)(0x42842808UL))\r
+#define bFM3_USB0_UDCS_BRST                    *((volatile unsigned int*)(0x4284280CUL))\r
+#define bFM3_USB0_UDCS_SOF                     *((volatile unsigned int*)(0x42842810UL))\r
+#define bFM3_USB0_UDCS_SUSP                    *((volatile unsigned int*)(0x42842814UL))\r
+#define bFM3_USB0_UDCIE_CONFIE                 *((volatile unsigned int*)(0x42842820UL))\r
+#define bFM3_USB0_UDCIE_CONFN                  *((volatile unsigned int*)(0x42842824UL))\r
+#define bFM3_USB0_UDCIE_WKUPIE                 *((volatile unsigned int*)(0x42842828UL))\r
+#define bFM3_USB0_UDCIE_BRSTIE                 *((volatile unsigned int*)(0x4284282CUL))\r
+#define bFM3_USB0_UDCIE_SOFIE                  *((volatile unsigned int*)(0x42842830UL))\r
+#define bFM3_USB0_UDCIE_SUSPIE                 *((volatile unsigned int*)(0x42842834UL))\r
+#define bFM3_USB0_EP0IS_DRQI                   *((volatile unsigned int*)(0x428428A8UL))\r
+#define bFM3_USB0_EP0IS_DRQIIE                 *((volatile unsigned int*)(0x428428B8UL))\r
+#define bFM3_USB0_EP0IS_BFINI                  *((volatile unsigned int*)(0x428428BCUL))\r
+#define bFM3_USB0_EP0OS_SIZE0                  *((volatile unsigned int*)(0x42842900UL))\r
+#define bFM3_USB0_EP0OS_SIZE1                  *((volatile unsigned int*)(0x42842904UL))\r
+#define bFM3_USB0_EP0OS_SIZE2                  *((volatile unsigned int*)(0x42842908UL))\r
+#define bFM3_USB0_EP0OS_SIZE3                  *((volatile unsigned int*)(0x4284290CUL))\r
+#define bFM3_USB0_EP0OS_SIZE4                  *((volatile unsigned int*)(0x42842910UL))\r
+#define bFM3_USB0_EP0OS_SIZE5                  *((volatile unsigned int*)(0x42842914UL))\r
+#define bFM3_USB0_EP0OS_SIZE6                  *((volatile unsigned int*)(0x42842918UL))\r
+#define bFM3_USB0_EP0OS_SPK                    *((volatile unsigned int*)(0x42842924UL))\r
+#define bFM3_USB0_EP0OS_DRQO                   *((volatile unsigned int*)(0x42842928UL))\r
+#define bFM3_USB0_EP0OS_SPKIE                  *((volatile unsigned int*)(0x42842934UL))\r
+#define bFM3_USB0_EP0OS_DRQOIE                 *((volatile unsigned int*)(0x42842938UL))\r
+#define bFM3_USB0_EP0OS_BFINI                  *((volatile unsigned int*)(0x4284293CUL))\r
+#define bFM3_USB0_EP1S_SIZE10                  *((volatile unsigned int*)(0x42842980UL))\r
+#define bFM3_USB0_EP1S_SIZE11                  *((volatile unsigned int*)(0x42842984UL))\r
+#define bFM3_USB0_EP1S_SIZE12                  *((volatile unsigned int*)(0x42842988UL))\r
+#define bFM3_USB0_EP1S_SIZE13                  *((volatile unsigned int*)(0x4284298CUL))\r
+#define bFM3_USB0_EP1S_SIZE14                  *((volatile unsigned int*)(0x42842990UL))\r
+#define bFM3_USB0_EP1S_SIZE15                  *((volatile unsigned int*)(0x42842994UL))\r
+#define bFM3_USB0_EP1S_SIZE16                  *((volatile unsigned int*)(0x42842998UL))\r
+#define bFM3_USB0_EP1S_SIZE17                  *((volatile unsigned int*)(0x4284299CUL))\r
+#define bFM3_USB0_EP1S_SPK                     *((volatile unsigned int*)(0x428429A4UL))\r
+#define bFM3_USB0_EP1S_DRQ                     *((volatile unsigned int*)(0x428429A8UL))\r
+#define bFM3_USB0_EP1S_BUSY                    *((volatile unsigned int*)(0x428429ACUL))\r
+#define bFM3_USB0_EP1S_SPKIE                   *((volatile unsigned int*)(0x428429B4UL))\r
+#define bFM3_USB0_EP1S_DRQIE                   *((volatile unsigned int*)(0x428429B8UL))\r
+#define bFM3_USB0_EP1S_BFINI                   *((volatile unsigned int*)(0x428429BCUL))\r
+#define bFM3_USB0_EP2S_SIZE20                  *((volatile unsigned int*)(0x42842A00UL))\r
+#define bFM3_USB0_EP2S_SIZE21                  *((volatile unsigned int*)(0x42842A04UL))\r
+#define bFM3_USB0_EP2S_SIZE22                  *((volatile unsigned int*)(0x42842A08UL))\r
+#define bFM3_USB0_EP2S_SIZE23                  *((volatile unsigned int*)(0x42842A0CUL))\r
+#define bFM3_USB0_EP2S_SIZE24                  *((volatile unsigned int*)(0x42842A10UL))\r
+#define bFM3_USB0_EP2S_SIZE25                  *((volatile unsigned int*)(0x42842A14UL))\r
+#define bFM3_USB0_EP2S_SIZE26                  *((volatile unsigned int*)(0x42842A18UL))\r
+#define bFM3_USB0_EP2S_SPK                     *((volatile unsigned int*)(0x42842A24UL))\r
+#define bFM3_USB0_EP2S_DRQ                     *((volatile unsigned int*)(0x42842A28UL))\r
+#define bFM3_USB0_EP2S_BUSY                    *((volatile unsigned int*)(0x42842A2CUL))\r
+#define bFM3_USB0_EP2S_SPKIE                   *((volatile unsigned int*)(0x42842A34UL))\r
+#define bFM3_USB0_EP2S_DRQIE                   *((volatile unsigned int*)(0x42842A38UL))\r
+#define bFM3_USB0_EP2S_BFINI                   *((volatile unsigned int*)(0x42842A3CUL))\r
+#define bFM3_USB0_EP3S_SIZE30                  *((volatile unsigned int*)(0x42842A80UL))\r
+#define bFM3_USB0_EP3S_SIZE31                  *((volatile unsigned int*)(0x42842A84UL))\r
+#define bFM3_USB0_EP3S_SIZE32                  *((volatile unsigned int*)(0x42842A88UL))\r
+#define bFM3_USB0_EP3S_SIZE33                  *((volatile unsigned int*)(0x42842A8CUL))\r
+#define bFM3_USB0_EP3S_SIZE34                  *((volatile unsigned int*)(0x42842A90UL))\r
+#define bFM3_USB0_EP3S_SIZE35                  *((volatile unsigned int*)(0x42842A94UL))\r
+#define bFM3_USB0_EP3S_SIZE36                  *((volatile unsigned int*)(0x42842A98UL))\r
+#define bFM3_USB0_EP3S_SPK                     *((volatile unsigned int*)(0x42842AA4UL))\r
+#define bFM3_USB0_EP3S_DRQ                     *((volatile unsigned int*)(0x42842AA8UL))\r
+#define bFM3_USB0_EP3S_BUSY                    *((volatile unsigned int*)(0x42842AACUL))\r
+#define bFM3_USB0_EP3S_SPKIE                   *((volatile unsigned int*)(0x42842AB4UL))\r
+#define bFM3_USB0_EP3S_DRQIE                   *((volatile unsigned int*)(0x42842AB8UL))\r
+#define bFM3_USB0_EP3S_BFINI                   *((volatile unsigned int*)(0x42842ABCUL))\r
+#define bFM3_USB0_EP4S_SIZE40                  *((volatile unsigned int*)(0x42842B00UL))\r
+#define bFM3_USB0_EP4S_SIZE41                  *((volatile unsigned int*)(0x42842B04UL))\r
+#define bFM3_USB0_EP4S_SIZE42                  *((volatile unsigned int*)(0x42842B08UL))\r
+#define bFM3_USB0_EP4S_SIZE43                  *((volatile unsigned int*)(0x42842B0CUL))\r
+#define bFM3_USB0_EP4S_SIZE44                  *((volatile unsigned int*)(0x42842B10UL))\r
+#define bFM3_USB0_EP4S_SIZE45                  *((volatile unsigned int*)(0x42842B14UL))\r
+#define bFM3_USB0_EP4S_SIZE46                  *((volatile unsigned int*)(0x42842B18UL))\r
+#define bFM3_USB0_EP4S_SPK                     *((volatile unsigned int*)(0x42842B24UL))\r
+#define bFM3_USB0_EP4S_DRQ                     *((volatile unsigned int*)(0x42842B28UL))\r
+#define bFM3_USB0_EP4S_BUSY                    *((volatile unsigned int*)(0x42842B2CUL))\r
+#define bFM3_USB0_EP4S_SPKIE                   *((volatile unsigned int*)(0x42842B34UL))\r
+#define bFM3_USB0_EP4S_DRQIE                   *((volatile unsigned int*)(0x42842B38UL))\r
+#define bFM3_USB0_EP4S_BFINI                   *((volatile unsigned int*)(0x42842B3CUL))\r
+#define bFM3_USB0_EP5S_SIZE50                  *((volatile unsigned int*)(0x42842B80UL))\r
+#define bFM3_USB0_EP5S_SIZE51                  *((volatile unsigned int*)(0x42842B84UL))\r
+#define bFM3_USB0_EP5S_SIZE52                  *((volatile unsigned int*)(0x42842B88UL))\r
+#define bFM3_USB0_EP5S_SIZE53                  *((volatile unsigned int*)(0x42842B8CUL))\r
+#define bFM3_USB0_EP5S_SIZE54                  *((volatile unsigned int*)(0x42842B90UL))\r
+#define bFM3_USB0_EP5S_SIZE55                  *((volatile unsigned int*)(0x42842B94UL))\r
+#define bFM3_USB0_EP5S_SIZE56                  *((volatile unsigned int*)(0x42842B98UL))\r
+#define bFM3_USB0_EP5S_SPK                     *((volatile unsigned int*)(0x42842BA4UL))\r
+#define bFM3_USB0_EP5S_DRQ                     *((volatile unsigned int*)(0x42842BA8UL))\r
+#define bFM3_USB0_EP5S_BUSY                    *((volatile unsigned int*)(0x42842BACUL))\r
+#define bFM3_USB0_EP5S_SPKIE                   *((volatile unsigned int*)(0x42842BB4UL))\r
+#define bFM3_USB0_EP5S_DRQIE                   *((volatile unsigned int*)(0x42842BB8UL))\r
+#define bFM3_USB0_EP5S_BFINI                   *((volatile unsigned int*)(0x42842BBCUL))\r
+\r
+/* DMA controller */\r
+#define bFM3_DMAC_DMACR_DH0                    *((volatile unsigned int*)(0x42C00060UL))\r
+#define bFM3_DMAC_DMACR_DH1                    *((volatile unsigned int*)(0x42C00064UL))\r
+#define bFM3_DMAC_DMACR_DH2                    *((volatile unsigned int*)(0x42C00068UL))\r
+#define bFM3_DMAC_DMACR_DH3                    *((volatile unsigned int*)(0x42C0006CUL))\r
+#define bFM3_DMAC_DMACR_PR                     *((volatile unsigned int*)(0x42C00070UL))\r
+#define bFM3_DMAC_DMACR_DS                     *((volatile unsigned int*)(0x42C00078UL))\r
+#define bFM3_DMAC_DMACR_DE                     *((volatile unsigned int*)(0x42C0007CUL))\r
+#define bFM3_DMAC_DMACA0_TC0                   *((volatile unsigned int*)(0x42C00200UL))\r
+#define bFM3_DMAC_DMACA0_TC1                   *((volatile unsigned int*)(0x42C00204UL))\r
+#define bFM3_DMAC_DMACA0_TC2                   *((volatile unsigned int*)(0x42C00208UL))\r
+#define bFM3_DMAC_DMACA0_TC3                   *((volatile unsigned int*)(0x42C0020CUL))\r
+#define bFM3_DMAC_DMACA0_TC4                   *((volatile unsigned int*)(0x42C00210UL))\r
+#define bFM3_DMAC_DMACA0_TC5                   *((volatile unsigned int*)(0x42C00214UL))\r
+#define bFM3_DMAC_DMACA0_TC6                   *((volatile unsigned int*)(0x42C00218UL))\r
+#define bFM3_DMAC_DMACA0_TC7                   *((volatile unsigned int*)(0x42C0021CUL))\r
+#define bFM3_DMAC_DMACA0_TC8                   *((volatile unsigned int*)(0x42C00220UL))\r
+#define bFM3_DMAC_DMACA0_TC9                   *((volatile unsigned int*)(0x42C00224UL))\r
+#define bFM3_DMAC_DMACA0_TC10                  *((volatile unsigned int*)(0x42C00228UL))\r
+#define bFM3_DMAC_DMACA0_TC11                  *((volatile unsigned int*)(0x42C0022CUL))\r
+#define bFM3_DMAC_DMACA0_TC12                  *((volatile unsigned int*)(0x42C00230UL))\r
+#define bFM3_DMAC_DMACA0_TC13                  *((volatile unsigned int*)(0x42C00234UL))\r
+#define bFM3_DMAC_DMACA0_TC14                  *((volatile unsigned int*)(0x42C00238UL))\r
+#define bFM3_DMAC_DMACA0_TC15                  *((volatile unsigned int*)(0x42C0023CUL))\r
+#define bFM3_DMAC_DMACA0_BC0                   *((volatile unsigned int*)(0x42C00240UL))\r
+#define bFM3_DMAC_DMACA0_BC1                   *((volatile unsigned int*)(0x42C00244UL))\r
+#define bFM3_DMAC_DMACA0_BC2                   *((volatile unsigned int*)(0x42C00248UL))\r
+#define bFM3_DMAC_DMACA0_BC3                   *((volatile unsigned int*)(0x42C0024CUL))\r
+#define bFM3_DMAC_DMACA0_IS0                   *((volatile unsigned int*)(0x42C0025CUL))\r
+#define bFM3_DMAC_DMACA0_IS1                   *((volatile unsigned int*)(0x42C00260UL))\r
+#define bFM3_DMAC_DMACA0_IS2                   *((volatile unsigned int*)(0x42C00264UL))\r
+#define bFM3_DMAC_DMACA0_IS3                   *((volatile unsigned int*)(0x42C00268UL))\r
+#define bFM3_DMAC_DMACA0_IS4                   *((volatile unsigned int*)(0x42C0026CUL))\r
+#define bFM3_DMAC_DMACA0_IS5                   *((volatile unsigned int*)(0x42C00270UL))\r
+#define bFM3_DMAC_DMACA0_ST                    *((volatile unsigned int*)(0x42C00274UL))\r
+#define bFM3_DMAC_DMACA0_PB                    *((volatile unsigned int*)(0x42C00278UL))\r
+#define bFM3_DMAC_DMACA0_EB                    *((volatile unsigned int*)(0x42C0027CUL))\r
+#define bFM3_DMAC_DMACB0_EM                    *((volatile unsigned int*)(0x42C00280UL))\r
+#define bFM3_DMAC_DMACB0_SS0                   *((volatile unsigned int*)(0x42C002C0UL))\r
+#define bFM3_DMAC_DMACB0_SS1                   *((volatile unsigned int*)(0x42C002C4UL))\r
+#define bFM3_DMAC_DMACB0_SS2                   *((volatile unsigned int*)(0x42C002C8UL))\r
+#define bFM3_DMAC_DMACB0_CI                    *((volatile unsigned int*)(0x42C002CCUL))\r
+#define bFM3_DMAC_DMACB0_EI                    *((volatile unsigned int*)(0x42C002D0UL))\r
+#define bFM3_DMAC_DMACB0_RD                    *((volatile unsigned int*)(0x42C002D4UL))\r
+#define bFM3_DMAC_DMACB0_RS                    *((volatile unsigned int*)(0x42C002D8UL))\r
+#define bFM3_DMAC_DMACB0_RC                    *((volatile unsigned int*)(0x42C002DCUL))\r
+#define bFM3_DMAC_DMACB0_FD                    *((volatile unsigned int*)(0x42C002E0UL))\r
+#define bFM3_DMAC_DMACB0_FS                    *((volatile unsigned int*)(0x42C002E4UL))\r
+#define bFM3_DMAC_DMACB0_TW0                   *((volatile unsigned int*)(0x42C002E8UL))\r
+#define bFM3_DMAC_DMACB0_TW1                   *((volatile unsigned int*)(0x42C002ECUL))\r
+#define bFM3_DMAC_DMACB0_MS0                   *((volatile unsigned int*)(0x42C002F0UL))\r
+#define bFM3_DMAC_DMACB0_MS1                   *((volatile unsigned int*)(0x42C002F4UL))\r
+#define bFM3_DMAC_DMACA1_TC0                   *((volatile unsigned int*)(0x42C00400UL))\r
+#define bFM3_DMAC_DMACA1_TC1                   *((volatile unsigned int*)(0x42C00404UL))\r
+#define bFM3_DMAC_DMACA1_TC2                   *((volatile unsigned int*)(0x42C00408UL))\r
+#define bFM3_DMAC_DMACA1_TC3                   *((volatile unsigned int*)(0x42C0040CUL))\r
+#define bFM3_DMAC_DMACA1_TC4                   *((volatile unsigned int*)(0x42C00410UL))\r
+#define bFM3_DMAC_DMACA1_TC5                   *((volatile unsigned int*)(0x42C00414UL))\r
+#define bFM3_DMAC_DMACA1_TC6                   *((volatile unsigned int*)(0x42C00418UL))\r
+#define bFM3_DMAC_DMACA1_TC7                   *((volatile unsigned int*)(0x42C0041CUL))\r
+#define bFM3_DMAC_DMACA1_TC8                   *((volatile unsigned int*)(0x42C00420UL))\r
+#define bFM3_DMAC_DMACA1_TC9                   *((volatile unsigned int*)(0x42C00424UL))\r
+#define bFM3_DMAC_DMACA1_TC10                  *((volatile unsigned int*)(0x42C00428UL))\r
+#define bFM3_DMAC_DMACA1_TC11                  *((volatile unsigned int*)(0x42C0042CUL))\r
+#define bFM3_DMAC_DMACA1_TC12                  *((volatile unsigned int*)(0x42C00430UL))\r
+#define bFM3_DMAC_DMACA1_TC13                  *((volatile unsigned int*)(0x42C00434UL))\r
+#define bFM3_DMAC_DMACA1_TC14                  *((volatile unsigned int*)(0x42C00438UL))\r
+#define bFM3_DMAC_DMACA1_TC15                  *((volatile unsigned int*)(0x42C0043CUL))\r
+#define bFM3_DMAC_DMACA1_BC0                   *((volatile unsigned int*)(0x42C00440UL))\r
+#define bFM3_DMAC_DMACA1_BC1                   *((volatile unsigned int*)(0x42C00444UL))\r
+#define bFM3_DMAC_DMACA1_BC2                   *((volatile unsigned int*)(0x42C00448UL))\r
+#define bFM3_DMAC_DMACA1_BC3                   *((volatile unsigned int*)(0x42C0044CUL))\r
+#define bFM3_DMAC_DMACA1_IS0                   *((volatile unsigned int*)(0x42C0045CUL))\r
+#define bFM3_DMAC_DMACA1_IS1                   *((volatile unsigned int*)(0x42C00460UL))\r
+#define bFM3_DMAC_DMACA1_IS2                   *((volatile unsigned int*)(0x42C00464UL))\r
+#define bFM3_DMAC_DMACA1_IS3                   *((volatile unsigned int*)(0x42C00468UL))\r
+#define bFM3_DMAC_DMACA1_IS4                   *((volatile unsigned int*)(0x42C0046CUL))\r
+#define bFM3_DMAC_DMACA1_IS5                   *((volatile unsigned int*)(0x42C00470UL))\r
+#define bFM3_DMAC_DMACA1_ST                    *((volatile unsigned int*)(0x42C00474UL))\r
+#define bFM3_DMAC_DMACA1_PB                    *((volatile unsigned int*)(0x42C00478UL))\r
+#define bFM3_DMAC_DMACA1_EB                    *((volatile unsigned int*)(0x42C0047CUL))\r
+#define bFM3_DMAC_DMACB1_EM                    *((volatile unsigned int*)(0x42C00480UL))\r
+#define bFM3_DMAC_DMACB1_SS0                   *((volatile unsigned int*)(0x42C004C0UL))\r
+#define bFM3_DMAC_DMACB1_SS1                   *((volatile unsigned int*)(0x42C004C4UL))\r
+#define bFM3_DMAC_DMACB1_SS2                   *((volatile unsigned int*)(0x42C004C8UL))\r
+#define bFM3_DMAC_DMACB1_CI                    *((volatile unsigned int*)(0x42C004CCUL))\r
+#define bFM3_DMAC_DMACB1_EI                    *((volatile unsigned int*)(0x42C004D0UL))\r
+#define bFM3_DMAC_DMACB1_RD                    *((volatile unsigned int*)(0x42C004D4UL))\r
+#define bFM3_DMAC_DMACB1_RS                    *((volatile unsigned int*)(0x42C004D8UL))\r
+#define bFM3_DMAC_DMACB1_RC                    *((volatile unsigned int*)(0x42C004DCUL))\r
+#define bFM3_DMAC_DMACB1_FD                    *((volatile unsigned int*)(0x42C004E0UL))\r
+#define bFM3_DMAC_DMACB1_FS                    *((volatile unsigned int*)(0x42C004E4UL))\r
+#define bFM3_DMAC_DMACB1_TW0                   *((volatile unsigned int*)(0x42C004E8UL))\r
+#define bFM3_DMAC_DMACB1_TW1                   *((volatile unsigned int*)(0x42C004ECUL))\r
+#define bFM3_DMAC_DMACB1_MS0                   *((volatile unsigned int*)(0x42C004F0UL))\r
+#define bFM3_DMAC_DMACB1_MS1                   *((volatile unsigned int*)(0x42C004F4UL))\r
+#define bFM3_DMAC_DMACA2_TC0                   *((volatile unsigned int*)(0x42C00600UL))\r
+#define bFM3_DMAC_DMACA2_TC1                   *((volatile unsigned int*)(0x42C00604UL))\r
+#define bFM3_DMAC_DMACA2_TC2                   *((volatile unsigned int*)(0x42C00608UL))\r
+#define bFM3_DMAC_DMACA2_TC3                   *((volatile unsigned int*)(0x42C0060CUL))\r
+#define bFM3_DMAC_DMACA2_TC4                   *((volatile unsigned int*)(0x42C00610UL))\r
+#define bFM3_DMAC_DMACA2_TC5                   *((volatile unsigned int*)(0x42C00614UL))\r
+#define bFM3_DMAC_DMACA2_TC6                   *((volatile unsigned int*)(0x42C00618UL))\r
+#define bFM3_DMAC_DMACA2_TC7                   *((volatile unsigned int*)(0x42C0061CUL))\r
+#define bFM3_DMAC_DMACA2_TC8                   *((volatile unsigned int*)(0x42C00620UL))\r
+#define bFM3_DMAC_DMACA2_TC9                   *((volatile unsigned int*)(0x42C00624UL))\r
+#define bFM3_DMAC_DMACA2_TC10                  *((volatile unsigned int*)(0x42C00628UL))\r
+#define bFM3_DMAC_DMACA2_TC11                  *((volatile unsigned int*)(0x42C0062CUL))\r
+#define bFM3_DMAC_DMACA2_TC12                  *((volatile unsigned int*)(0x42C00630UL))\r
+#define bFM3_DMAC_DMACA2_TC13                  *((volatile unsigned int*)(0x42C00634UL))\r
+#define bFM3_DMAC_DMACA2_TC14                  *((volatile unsigned int*)(0x42C00638UL))\r
+#define bFM3_DMAC_DMACA2_TC15                  *((volatile unsigned int*)(0x42C0063CUL))\r
+#define bFM3_DMAC_DMACA2_BC0                   *((volatile unsigned int*)(0x42C00640UL))\r
+#define bFM3_DMAC_DMACA2_BC1                   *((volatile unsigned int*)(0x42C00644UL))\r
+#define bFM3_DMAC_DMACA2_BC2                   *((volatile unsigned int*)(0x42C00648UL))\r
+#define bFM3_DMAC_DMACA2_BC3                   *((volatile unsigned int*)(0x42C0064CUL))\r
+#define bFM3_DMAC_DMACA2_IS0                   *((volatile unsigned int*)(0x42C0065CUL))\r
+#define bFM3_DMAC_DMACA2_IS1                   *((volatile unsigned int*)(0x42C00660UL))\r
+#define bFM3_DMAC_DMACA2_IS2                   *((volatile unsigned int*)(0x42C00664UL))\r
+#define bFM3_DMAC_DMACA2_IS3                   *((volatile unsigned int*)(0x42C00668UL))\r
+#define bFM3_DMAC_DMACA2_IS4                   *((volatile unsigned int*)(0x42C0066CUL))\r
+#define bFM3_DMAC_DMACA2_IS5                   *((volatile unsigned int*)(0x42C00670UL))\r
+#define bFM3_DMAC_DMACA2_ST                    *((volatile unsigned int*)(0x42C00674UL))\r
+#define bFM3_DMAC_DMACA2_PB                    *((volatile unsigned int*)(0x42C00678UL))\r
+#define bFM3_DMAC_DMACA2_EB                    *((volatile unsigned int*)(0x42C0067CUL))\r
+#define bFM3_DMAC_DMACB2_EM                    *((volatile unsigned int*)(0x42C00680UL))\r
+#define bFM3_DMAC_DMACB2_SS0                   *((volatile unsigned int*)(0x42C006C0UL))\r
+#define bFM3_DMAC_DMACB2_SS1                   *((volatile unsigned int*)(0x42C006C4UL))\r
+#define bFM3_DMAC_DMACB2_SS2                   *((volatile unsigned int*)(0x42C006C8UL))\r
+#define bFM3_DMAC_DMACB2_CI                    *((volatile unsigned int*)(0x42C006CCUL))\r
+#define bFM3_DMAC_DMACB2_EI                    *((volatile unsigned int*)(0x42C006D0UL))\r
+#define bFM3_DMAC_DMACB2_RD                    *((volatile unsigned int*)(0x42C006D4UL))\r
+#define bFM3_DMAC_DMACB2_RS                    *((volatile unsigned int*)(0x42C006D8UL))\r
+#define bFM3_DMAC_DMACB2_RC                    *((volatile unsigned int*)(0x42C006DCUL))\r
+#define bFM3_DMAC_DMACB2_FD                    *((volatile unsigned int*)(0x42C006E0UL))\r
+#define bFM3_DMAC_DMACB2_FS                    *((volatile unsigned int*)(0x42C006E4UL))\r
+#define bFM3_DMAC_DMACB2_TW0                   *((volatile unsigned int*)(0x42C006E8UL))\r
+#define bFM3_DMAC_DMACB2_TW1                   *((volatile unsigned int*)(0x42C006ECUL))\r
+#define bFM3_DMAC_DMACB2_MS0                   *((volatile unsigned int*)(0x42C006F0UL))\r
+#define bFM3_DMAC_DMACB2_MS1                   *((volatile unsigned int*)(0x42C006F4UL))\r
+#define bFM3_DMAC_DMACA3_TC0                   *((volatile unsigned int*)(0x42C00800UL))\r
+#define bFM3_DMAC_DMACA3_TC1                   *((volatile unsigned int*)(0x42C00804UL))\r
+#define bFM3_DMAC_DMACA3_TC2                   *((volatile unsigned int*)(0x42C00808UL))\r
+#define bFM3_DMAC_DMACA3_TC3                   *((volatile unsigned int*)(0x42C0080CUL))\r
+#define bFM3_DMAC_DMACA3_TC4                   *((volatile unsigned int*)(0x42C00810UL))\r
+#define bFM3_DMAC_DMACA3_TC5                   *((volatile unsigned int*)(0x42C00814UL))\r
+#define bFM3_DMAC_DMACA3_TC6                   *((volatile unsigned int*)(0x42C00818UL))\r
+#define bFM3_DMAC_DMACA3_TC7                   *((volatile unsigned int*)(0x42C0081CUL))\r
+#define bFM3_DMAC_DMACA3_TC8                   *((volatile unsigned int*)(0x42C00820UL))\r
+#define bFM3_DMAC_DMACA3_TC9                   *((volatile unsigned int*)(0x42C00824UL))\r
+#define bFM3_DMAC_DMACA3_TC10                  *((volatile unsigned int*)(0x42C00828UL))\r
+#define bFM3_DMAC_DMACA3_TC11                  *((volatile unsigned int*)(0x42C0082CUL))\r
+#define bFM3_DMAC_DMACA3_TC12                  *((volatile unsigned int*)(0x42C00830UL))\r
+#define bFM3_DMAC_DMACA3_TC13                  *((volatile unsigned int*)(0x42C00834UL))\r
+#define bFM3_DMAC_DMACA3_TC14                  *((volatile unsigned int*)(0x42C00838UL))\r
+#define bFM3_DMAC_DMACA3_TC15                  *((volatile unsigned int*)(0x42C0083CUL))\r
+#define bFM3_DMAC_DMACA3_BC0                   *((volatile unsigned int*)(0x42C00840UL))\r
+#define bFM3_DMAC_DMACA3_BC1                   *((volatile unsigned int*)(0x42C00844UL))\r
+#define bFM3_DMAC_DMACA3_BC2                   *((volatile unsigned int*)(0x42C00848UL))\r
+#define bFM3_DMAC_DMACA3_BC3                   *((volatile unsigned int*)(0x42C0084CUL))\r
+#define bFM3_DMAC_DMACA3_IS0                   *((volatile unsigned int*)(0x42C0085CUL))\r
+#define bFM3_DMAC_DMACA3_IS1                   *((volatile unsigned int*)(0x42C00860UL))\r
+#define bFM3_DMAC_DMACA3_IS2                   *((volatile unsigned int*)(0x42C00864UL))\r
+#define bFM3_DMAC_DMACA3_IS3                   *((volatile unsigned int*)(0x42C00868UL))\r
+#define bFM3_DMAC_DMACA3_IS4                   *((volatile unsigned int*)(0x42C0086CUL))\r
+#define bFM3_DMAC_DMACA3_IS5                   *((volatile unsigned int*)(0x42C00870UL))\r
+#define bFM3_DMAC_DMACA3_ST                    *((volatile unsigned int*)(0x42C00874UL))\r
+#define bFM3_DMAC_DMACA3_PB                    *((volatile unsigned int*)(0x42C00878UL))\r
+#define bFM3_DMAC_DMACA3_EB                    *((volatile unsigned int*)(0x42C0087CUL))\r
+#define bFM3_DMAC_DMACB3_EM                    *((volatile unsigned int*)(0x42C00880UL))\r
+#define bFM3_DMAC_DMACB3_SS0                   *((volatile unsigned int*)(0x42C008C0UL))\r
+#define bFM3_DMAC_DMACB3_SS1                   *((volatile unsigned int*)(0x42C008C4UL))\r
+#define bFM3_DMAC_DMACB3_SS2                   *((volatile unsigned int*)(0x42C008C8UL))\r
+#define bFM3_DMAC_DMACB3_CI                    *((volatile unsigned int*)(0x42C008CCUL))\r
+#define bFM3_DMAC_DMACB3_EI                    *((volatile unsigned int*)(0x42C008D0UL))\r
+#define bFM3_DMAC_DMACB3_RD                    *((volatile unsigned int*)(0x42C008D4UL))\r
+#define bFM3_DMAC_DMACB3_RS                    *((volatile unsigned int*)(0x42C008D8UL))\r
+#define bFM3_DMAC_DMACB3_RC                    *((volatile unsigned int*)(0x42C008DCUL))\r
+#define bFM3_DMAC_DMACB3_FD                    *((volatile unsigned int*)(0x42C008E0UL))\r
+#define bFM3_DMAC_DMACB3_FS                    *((volatile unsigned int*)(0x42C008E4UL))\r
+#define bFM3_DMAC_DMACB3_TW0                   *((volatile unsigned int*)(0x42C008E8UL))\r
+#define bFM3_DMAC_DMACB3_TW1                   *((volatile unsigned int*)(0x42C008ECUL))\r
+#define bFM3_DMAC_DMACB3_MS0                   *((volatile unsigned int*)(0x42C008F0UL))\r
+#define bFM3_DMAC_DMACB3_MS1                   *((volatile unsigned int*)(0x42C008F4UL))\r
+#define bFM3_DMAC_DMACA4_TC0                   *((volatile unsigned int*)(0x42C00A00UL))\r
+#define bFM3_DMAC_DMACA4_TC1                   *((volatile unsigned int*)(0x42C00A04UL))\r
+#define bFM3_DMAC_DMACA4_TC2                   *((volatile unsigned int*)(0x42C00A08UL))\r
+#define bFM3_DMAC_DMACA4_TC3                   *((volatile unsigned int*)(0x42C00A0CUL))\r
+#define bFM3_DMAC_DMACA4_TC4                   *((volatile unsigned int*)(0x42C00A10UL))\r
+#define bFM3_DMAC_DMACA4_TC5                   *((volatile unsigned int*)(0x42C00A14UL))\r
+#define bFM3_DMAC_DMACA4_TC6                   *((volatile unsigned int*)(0x42C00A18UL))\r
+#define bFM3_DMAC_DMACA4_TC7                   *((volatile unsigned int*)(0x42C00A1CUL))\r
+#define bFM3_DMAC_DMACA4_TC8                   *((volatile unsigned int*)(0x42C00A20UL))\r
+#define bFM3_DMAC_DMACA4_TC9                   *((volatile unsigned int*)(0x42C00A24UL))\r
+#define bFM3_DMAC_DMACA4_TC10                  *((volatile unsigned int*)(0x42C00A28UL))\r
+#define bFM3_DMAC_DMACA4_TC11                  *((volatile unsigned int*)(0x42C00A2CUL))\r
+#define bFM3_DMAC_DMACA4_TC12                  *((volatile unsigned int*)(0x42C00A30UL))\r
+#define bFM3_DMAC_DMACA4_TC13                  *((volatile unsigned int*)(0x42C00A34UL))\r
+#define bFM3_DMAC_DMACA4_TC14                  *((volatile unsigned int*)(0x42C00A38UL))\r
+#define bFM3_DMAC_DMACA4_TC15                  *((volatile unsigned int*)(0x42C00A3CUL))\r
+#define bFM3_DMAC_DMACA4_BC0                   *((volatile unsigned int*)(0x42C00A40UL))\r
+#define bFM3_DMAC_DMACA4_BC1                   *((volatile unsigned int*)(0x42C00A44UL))\r
+#define bFM3_DMAC_DMACA4_BC2                   *((volatile unsigned int*)(0x42C00A48UL))\r
+#define bFM3_DMAC_DMACA4_BC3                   *((volatile unsigned int*)(0x42C00A4CUL))\r
+#define bFM3_DMAC_DMACA4_IS0                   *((volatile unsigned int*)(0x42C00A5CUL))\r
+#define bFM3_DMAC_DMACA4_IS1                   *((volatile unsigned int*)(0x42C00A60UL))\r
+#define bFM3_DMAC_DMACA4_IS2                   *((volatile unsigned int*)(0x42C00A64UL))\r
+#define bFM3_DMAC_DMACA4_IS3                   *((volatile unsigned int*)(0x42C00A68UL))\r
+#define bFM3_DMAC_DMACA4_IS4                   *((volatile unsigned int*)(0x42C00A6CUL))\r
+#define bFM3_DMAC_DMACA4_IS5                   *((volatile unsigned int*)(0x42C00A70UL))\r
+#define bFM3_DMAC_DMACA4_ST                    *((volatile unsigned int*)(0x42C00A74UL))\r
+#define bFM3_DMAC_DMACA4_PB                    *((volatile unsigned int*)(0x42C00A78UL))\r
+#define bFM3_DMAC_DMACA4_EB                    *((volatile unsigned int*)(0x42C00A7CUL))\r
+#define bFM3_DMAC_DMACB4_EM                    *((volatile unsigned int*)(0x42C00A80UL))\r
+#define bFM3_DMAC_DMACB4_SS0                   *((volatile unsigned int*)(0x42C00AC0UL))\r
+#define bFM3_DMAC_DMACB4_SS1                   *((volatile unsigned int*)(0x42C00AC4UL))\r
+#define bFM3_DMAC_DMACB4_SS2                   *((volatile unsigned int*)(0x42C00AC8UL))\r
+#define bFM3_DMAC_DMACB4_CI                    *((volatile unsigned int*)(0x42C00ACCUL))\r
+#define bFM3_DMAC_DMACB4_EI                    *((volatile unsigned int*)(0x42C00AD0UL))\r
+#define bFM3_DMAC_DMACB4_RD                    *((volatile unsigned int*)(0x42C00AD4UL))\r
+#define bFM3_DMAC_DMACB4_RS                    *((volatile unsigned int*)(0x42C00AD8UL))\r
+#define bFM3_DMAC_DMACB4_RC                    *((volatile unsigned int*)(0x42C00ADCUL))\r
+#define bFM3_DMAC_DMACB4_FD                    *((volatile unsigned int*)(0x42C00AE0UL))\r
+#define bFM3_DMAC_DMACB4_FS                    *((volatile unsigned int*)(0x42C00AE4UL))\r
+#define bFM3_DMAC_DMACB4_TW0                   *((volatile unsigned int*)(0x42C00AE8UL))\r
+#define bFM3_DMAC_DMACB4_TW1                   *((volatile unsigned int*)(0x42C00AECUL))\r
+#define bFM3_DMAC_DMACB4_MS0                   *((volatile unsigned int*)(0x42C00AF0UL))\r
+#define bFM3_DMAC_DMACB4_MS1                   *((volatile unsigned int*)(0x42C00AF4UL))\r
+#define bFM3_DMAC_DMACA5_TC0                   *((volatile unsigned int*)(0x42C00C00UL))\r
+#define bFM3_DMAC_DMACA5_TC1                   *((volatile unsigned int*)(0x42C00C04UL))\r
+#define bFM3_DMAC_DMACA5_TC2                   *((volatile unsigned int*)(0x42C00C08UL))\r
+#define bFM3_DMAC_DMACA5_TC3                   *((volatile unsigned int*)(0x42C00C0CUL))\r
+#define bFM3_DMAC_DMACA5_TC4                   *((volatile unsigned int*)(0x42C00C10UL))\r
+#define bFM3_DMAC_DMACA5_TC5                   *((volatile unsigned int*)(0x42C00C14UL))\r
+#define bFM3_DMAC_DMACA5_TC6                   *((volatile unsigned int*)(0x42C00C18UL))\r
+#define bFM3_DMAC_DMACA5_TC7                   *((volatile unsigned int*)(0x42C00C1CUL))\r
+#define bFM3_DMAC_DMACA5_TC8                   *((volatile unsigned int*)(0x42C00C20UL))\r
+#define bFM3_DMAC_DMACA5_TC9                   *((volatile unsigned int*)(0x42C00C24UL))\r
+#define bFM3_DMAC_DMACA5_TC10                  *((volatile unsigned int*)(0x42C00C28UL))\r
+#define bFM3_DMAC_DMACA5_TC11                  *((volatile unsigned int*)(0x42C00C2CUL))\r
+#define bFM3_DMAC_DMACA5_TC12                  *((volatile unsigned int*)(0x42C00C30UL))\r
+#define bFM3_DMAC_DMACA5_TC13                  *((volatile unsigned int*)(0x42C00C34UL))\r
+#define bFM3_DMAC_DMACA5_TC14                  *((volatile unsigned int*)(0x42C00C38UL))\r
+#define bFM3_DMAC_DMACA5_TC15                  *((volatile unsigned int*)(0x42C00C3CUL))\r
+#define bFM3_DMAC_DMACA5_BC0                   *((volatile unsigned int*)(0x42C00C40UL))\r
+#define bFM3_DMAC_DMACA5_BC1                   *((volatile unsigned int*)(0x42C00C44UL))\r
+#define bFM3_DMAC_DMACA5_BC2                   *((volatile unsigned int*)(0x42C00C48UL))\r
+#define bFM3_DMAC_DMACA5_BC3                   *((volatile unsigned int*)(0x42C00C4CUL))\r
+#define bFM3_DMAC_DMACA5_IS0                   *((volatile unsigned int*)(0x42C00C5CUL))\r
+#define bFM3_DMAC_DMACA5_IS1                   *((volatile unsigned int*)(0x42C00C60UL))\r
+#define bFM3_DMAC_DMACA5_IS2                   *((volatile unsigned int*)(0x42C00C64UL))\r
+#define bFM3_DMAC_DMACA5_IS3                   *((volatile unsigned int*)(0x42C00C68UL))\r
+#define bFM3_DMAC_DMACA5_IS4                   *((volatile unsigned int*)(0x42C00C6CUL))\r
+#define bFM3_DMAC_DMACA5_IS5                   *((volatile unsigned int*)(0x42C00C70UL))\r
+#define bFM3_DMAC_DMACA5_ST                    *((volatile unsigned int*)(0x42C00C74UL))\r
+#define bFM3_DMAC_DMACA5_PB                    *((volatile unsigned int*)(0x42C00C78UL))\r
+#define bFM3_DMAC_DMACA5_EB                    *((volatile unsigned int*)(0x42C00C7CUL))\r
+#define bFM3_DMAC_DMACB5_EM                    *((volatile unsigned int*)(0x42C00C80UL))\r
+#define bFM3_DMAC_DMACB5_SS0                   *((volatile unsigned int*)(0x42C00CC0UL))\r
+#define bFM3_DMAC_DMACB5_SS1                   *((volatile unsigned int*)(0x42C00CC4UL))\r
+#define bFM3_DMAC_DMACB5_SS2                   *((volatile unsigned int*)(0x42C00CC8UL))\r
+#define bFM3_DMAC_DMACB5_CI                    *((volatile unsigned int*)(0x42C00CCCUL))\r
+#define bFM3_DMAC_DMACB5_EI                    *((volatile unsigned int*)(0x42C00CD0UL))\r
+#define bFM3_DMAC_DMACB5_RD                    *((volatile unsigned int*)(0x42C00CD4UL))\r
+#define bFM3_DMAC_DMACB5_RS                    *((volatile unsigned int*)(0x42C00CD8UL))\r
+#define bFM3_DMAC_DMACB5_RC                    *((volatile unsigned int*)(0x42C00CDCUL))\r
+#define bFM3_DMAC_DMACB5_FD                    *((volatile unsigned int*)(0x42C00CE0UL))\r
+#define bFM3_DMAC_DMACB5_FS                    *((volatile unsigned int*)(0x42C00CE4UL))\r
+#define bFM3_DMAC_DMACB5_TW0                   *((volatile unsigned int*)(0x42C00CE8UL))\r
+#define bFM3_DMAC_DMACB5_TW1                   *((volatile unsigned int*)(0x42C00CECUL))\r
+#define bFM3_DMAC_DMACB5_MS0                   *((volatile unsigned int*)(0x42C00CF0UL))\r
+#define bFM3_DMAC_DMACB5_MS1                   *((volatile unsigned int*)(0x42C00CF4UL))\r
+#define bFM3_DMAC_DMACA6_TC0                   *((volatile unsigned int*)(0x42C00E00UL))\r
+#define bFM3_DMAC_DMACA6_TC1                   *((volatile unsigned int*)(0x42C00E04UL))\r
+#define bFM3_DMAC_DMACA6_TC2                   *((volatile unsigned int*)(0x42C00E08UL))\r
+#define bFM3_DMAC_DMACA6_TC3                   *((volatile unsigned int*)(0x42C00E0CUL))\r
+#define bFM3_DMAC_DMACA6_TC4                   *((volatile unsigned int*)(0x42C00E10UL))\r
+#define bFM3_DMAC_DMACA6_TC5                   *((volatile unsigned int*)(0x42C00E14UL))\r
+#define bFM3_DMAC_DMACA6_TC6                   *((volatile unsigned int*)(0x42C00E18UL))\r
+#define bFM3_DMAC_DMACA6_TC7                   *((volatile unsigned int*)(0x42C00E1CUL))\r
+#define bFM3_DMAC_DMACA6_TC8                   *((volatile unsigned int*)(0x42C00E20UL))\r
+#define bFM3_DMAC_DMACA6_TC9                   *((volatile unsigned int*)(0x42C00E24UL))\r
+#define bFM3_DMAC_DMACA6_TC10                  *((volatile unsigned int*)(0x42C00E28UL))\r
+#define bFM3_DMAC_DMACA6_TC11                  *((volatile unsigned int*)(0x42C00E2CUL))\r
+#define bFM3_DMAC_DMACA6_TC12                  *((volatile unsigned int*)(0x42C00E30UL))\r
+#define bFM3_DMAC_DMACA6_TC13                  *((volatile unsigned int*)(0x42C00E34UL))\r
+#define bFM3_DMAC_DMACA6_TC14                  *((volatile unsigned int*)(0x42C00E38UL))\r
+#define bFM3_DMAC_DMACA6_TC15                  *((volatile unsigned int*)(0x42C00E3CUL))\r
+#define bFM3_DMAC_DMACA6_BC0                   *((volatile unsigned int*)(0x42C00E40UL))\r
+#define bFM3_DMAC_DMACA6_BC1                   *((volatile unsigned int*)(0x42C00E44UL))\r
+#define bFM3_DMAC_DMACA6_BC2                   *((volatile unsigned int*)(0x42C00E48UL))\r
+#define bFM3_DMAC_DMACA6_BC3                   *((volatile unsigned int*)(0x42C00E4CUL))\r
+#define bFM3_DMAC_DMACA6_IS0                   *((volatile unsigned int*)(0x42C00E5CUL))\r
+#define bFM3_DMAC_DMACA6_IS1                   *((volatile unsigned int*)(0x42C00E60UL))\r
+#define bFM3_DMAC_DMACA6_IS2                   *((volatile unsigned int*)(0x42C00E64UL))\r
+#define bFM3_DMAC_DMACA6_IS3                   *((volatile unsigned int*)(0x42C00E68UL))\r
+#define bFM3_DMAC_DMACA6_IS4                   *((volatile unsigned int*)(0x42C00E6CUL))\r
+#define bFM3_DMAC_DMACA6_IS5                   *((volatile unsigned int*)(0x42C00E70UL))\r
+#define bFM3_DMAC_DMACA6_ST                    *((volatile unsigned int*)(0x42C00E74UL))\r
+#define bFM3_DMAC_DMACA6_PB                    *((volatile unsigned int*)(0x42C00E78UL))\r
+#define bFM3_DMAC_DMACA6_EB                    *((volatile unsigned int*)(0x42C00E7CUL))\r
+#define bFM3_DMAC_DMACB6_EM                    *((volatile unsigned int*)(0x42C00E80UL))\r
+#define bFM3_DMAC_DMACB6_SS0                   *((volatile unsigned int*)(0x42C00EC0UL))\r
+#define bFM3_DMAC_DMACB6_SS1                   *((volatile unsigned int*)(0x42C00EC4UL))\r
+#define bFM3_DMAC_DMACB6_SS2                   *((volatile unsigned int*)(0x42C00EC8UL))\r
+#define bFM3_DMAC_DMACB6_CI                    *((volatile unsigned int*)(0x42C00ECCUL))\r
+#define bFM3_DMAC_DMACB6_EI                    *((volatile unsigned int*)(0x42C00ED0UL))\r
+#define bFM3_DMAC_DMACB6_RD                    *((volatile unsigned int*)(0x42C00ED4UL))\r
+#define bFM3_DMAC_DMACB6_RS                    *((volatile unsigned int*)(0x42C00ED8UL))\r
+#define bFM3_DMAC_DMACB6_RC                    *((volatile unsigned int*)(0x42C00EDCUL))\r
+#define bFM3_DMAC_DMACB6_FD                    *((volatile unsigned int*)(0x42C00EE0UL))\r
+#define bFM3_DMAC_DMACB6_FS                    *((volatile unsigned int*)(0x42C00EE4UL))\r
+#define bFM3_DMAC_DMACB6_TW0                   *((volatile unsigned int*)(0x42C00EE8UL))\r
+#define bFM3_DMAC_DMACB6_TW1                   *((volatile unsigned int*)(0x42C00EECUL))\r
+#define bFM3_DMAC_DMACB6_MS0                   *((volatile unsigned int*)(0x42C00EF0UL))\r
+#define bFM3_DMAC_DMACB6_MS1                   *((volatile unsigned int*)(0x42C00EF4UL))\r
+#define bFM3_DMAC_DMACA7_TC0                   *((volatile unsigned int*)(0x42C01000UL))\r
+#define bFM3_DMAC_DMACA7_TC1                   *((volatile unsigned int*)(0x42C01004UL))\r
+#define bFM3_DMAC_DMACA7_TC2                   *((volatile unsigned int*)(0x42C01008UL))\r
+#define bFM3_DMAC_DMACA7_TC3                   *((volatile unsigned int*)(0x42C0100CUL))\r
+#define bFM3_DMAC_DMACA7_TC4                   *((volatile unsigned int*)(0x42C01010UL))\r
+#define bFM3_DMAC_DMACA7_TC5                   *((volatile unsigned int*)(0x42C01014UL))\r
+#define bFM3_DMAC_DMACA7_TC6                   *((volatile unsigned int*)(0x42C01018UL))\r
+#define bFM3_DMAC_DMACA7_TC7                   *((volatile unsigned int*)(0x42C0101CUL))\r
+#define bFM3_DMAC_DMACA7_TC8                   *((volatile unsigned int*)(0x42C01020UL))\r
+#define bFM3_DMAC_DMACA7_TC9                   *((volatile unsigned int*)(0x42C01024UL))\r
+#define bFM3_DMAC_DMACA7_TC10                  *((volatile unsigned int*)(0x42C01028UL))\r
+#define bFM3_DMAC_DMACA7_TC11                  *((volatile unsigned int*)(0x42C0102CUL))\r
+#define bFM3_DMAC_DMACA7_TC12                  *((volatile unsigned int*)(0x42C01030UL))\r
+#define bFM3_DMAC_DMACA7_TC13                  *((volatile unsigned int*)(0x42C01034UL))\r
+#define bFM3_DMAC_DMACA7_TC14                  *((volatile unsigned int*)(0x42C01038UL))\r
+#define bFM3_DMAC_DMACA7_TC15                  *((volatile unsigned int*)(0x42C0103CUL))\r
+#define bFM3_DMAC_DMACA7_BC0                   *((volatile unsigned int*)(0x42C01040UL))\r
+#define bFM3_DMAC_DMACA7_BC1                   *((volatile unsigned int*)(0x42C01044UL))\r
+#define bFM3_DMAC_DMACA7_BC2                   *((volatile unsigned int*)(0x42C01048UL))\r
+#define bFM3_DMAC_DMACA7_BC3                   *((volatile unsigned int*)(0x42C0104CUL))\r
+#define bFM3_DMAC_DMACA7_IS0                   *((volatile unsigned int*)(0x42C0105CUL))\r
+#define bFM3_DMAC_DMACA7_IS1                   *((volatile unsigned int*)(0x42C01060UL))\r
+#define bFM3_DMAC_DMACA7_IS2                   *((volatile unsigned int*)(0x42C01064UL))\r
+#define bFM3_DMAC_DMACA7_IS3                   *((volatile unsigned int*)(0x42C01068UL))\r
+#define bFM3_DMAC_DMACA7_IS4                   *((volatile unsigned int*)(0x42C0106CUL))\r
+#define bFM3_DMAC_DMACA7_IS5                   *((volatile unsigned int*)(0x42C01070UL))\r
+#define bFM3_DMAC_DMACA7_ST                    *((volatile unsigned int*)(0x42C01074UL))\r
+#define bFM3_DMAC_DMACA7_PB                    *((volatile unsigned int*)(0x42C01078UL))\r
+#define bFM3_DMAC_DMACA7_EB                    *((volatile unsigned int*)(0x42C0107CUL))\r
+#define bFM3_DMAC_DMACB7_EM                    *((volatile unsigned int*)(0x42C01080UL))\r
+#define bFM3_DMAC_DMACB7_SS0                   *((volatile unsigned int*)(0x42C010C0UL))\r
+#define bFM3_DMAC_DMACB7_SS1                   *((volatile unsigned int*)(0x42C010C4UL))\r
+#define bFM3_DMAC_DMACB7_SS2                   *((volatile unsigned int*)(0x42C010C8UL))\r
+#define bFM3_DMAC_DMACB7_CI                    *((volatile unsigned int*)(0x42C010CCUL))\r
+#define bFM3_DMAC_DMACB7_EI                    *((volatile unsigned int*)(0x42C010D0UL))\r
+#define bFM3_DMAC_DMACB7_RD                    *((volatile unsigned int*)(0x42C010D4UL))\r
+#define bFM3_DMAC_DMACB7_RS                    *((volatile unsigned int*)(0x42C010D8UL))\r
+#define bFM3_DMAC_DMACB7_RC                    *((volatile unsigned int*)(0x42C010DCUL))\r
+#define bFM3_DMAC_DMACB7_FD                    *((volatile unsigned int*)(0x42C010E0UL))\r
+#define bFM3_DMAC_DMACB7_FS                    *((volatile unsigned int*)(0x42C010E4UL))\r
+#define bFM3_DMAC_DMACB7_TW0                   *((volatile unsigned int*)(0x42C010E8UL))\r
+#define bFM3_DMAC_DMACB7_TW1                   *((volatile unsigned int*)(0x42C010ECUL))\r
+#define bFM3_DMAC_DMACB7_MS0                   *((volatile unsigned int*)(0x42C010F0UL))\r
+#define bFM3_DMAC_DMACB7_MS1                   *((volatile unsigned int*)(0x42C010F4UL))\r
+\r
+/* CAN channel 0 registers */\r
+#define bFM3_CAN0_CTRLR_INIT                   *((volatile unsigned int*)(0x42C40000UL))\r
+#define bFM3_CAN0_CTRLR_IE                     *((volatile unsigned int*)(0x42C40004UL))\r
+#define bFM3_CAN0_CTRLR_SIE                    *((volatile unsigned int*)(0x42C40008UL))\r
+#define bFM3_CAN0_CTRLR_EIE                    *((volatile unsigned int*)(0x42C4000CUL))\r
+#define bFM3_CAN0_CTRLR_DAR                    *((volatile unsigned int*)(0x42C40014UL))\r
+#define bFM3_CAN0_CTRLR_CCE                    *((volatile unsigned int*)(0x42C40018UL))\r
+#define bFM3_CAN0_CTRLR_TEST                   *((volatile unsigned int*)(0x42C4001CUL))\r
+#define bFM3_CAN0_STATR_LEC0                   *((volatile unsigned int*)(0x42C40040UL))\r
+#define bFM3_CAN0_STATR_LEC1                   *((volatile unsigned int*)(0x42C40044UL))\r
+#define bFM3_CAN0_STATR_LEC2                   *((volatile unsigned int*)(0x42C40048UL))\r
+#define bFM3_CAN0_STATR_TXOK                   *((volatile unsigned int*)(0x42C4004CUL))\r
+#define bFM3_CAN0_STATR_RXOK                   *((volatile unsigned int*)(0x42C40050UL))\r
+#define bFM3_CAN0_STATR_EPASS                  *((volatile unsigned int*)(0x42C40054UL))\r
+#define bFM3_CAN0_STATR_EWARM                  *((volatile unsigned int*)(0x42C40058UL))\r
+#define bFM3_CAN0_STATR_BOFF                   *((volatile unsigned int*)(0x42C4005CUL))\r
+#define bFM3_CAN0_ERRCNT_TEC0                  *((volatile unsigned int*)(0x42C40080UL))\r
+#define bFM3_CAN0_ERRCNT_TEC1                  *((volatile unsigned int*)(0x42C40084UL))\r
+#define bFM3_CAN0_ERRCNT_TEC2                  *((volatile unsigned int*)(0x42C40088UL))\r
+#define bFM3_CAN0_ERRCNT_TEC3                  *((volatile unsigned int*)(0x42C4008CUL))\r
+#define bFM3_CAN0_ERRCNT_TEC4                  *((volatile unsigned int*)(0x42C40090UL))\r
+#define bFM3_CAN0_ERRCNT_TEC5                  *((volatile unsigned int*)(0x42C40094UL))\r
+#define bFM3_CAN0_ERRCNT_TEC6                  *((volatile unsigned int*)(0x42C40098UL))\r
+#define bFM3_CAN0_ERRCNT_TEC7                  *((volatile unsigned int*)(0x42C4009CUL))\r
+#define bFM3_CAN0_ERRCNT_REC0                  *((volatile unsigned int*)(0x42C400A0UL))\r
+#define bFM3_CAN0_ERRCNT_REC1                  *((volatile unsigned int*)(0x42C400A4UL))\r
+#define bFM3_CAN0_ERRCNT_REC2                  *((volatile unsigned int*)(0x42C400A8UL))\r
+#define bFM3_CAN0_ERRCNT_REC3                  *((volatile unsigned int*)(0x42C400ACUL))\r
+#define bFM3_CAN0_ERRCNT_REC4                  *((volatile unsigned int*)(0x42C400B0UL))\r
+#define bFM3_CAN0_ERRCNT_REC5                  *((volatile unsigned int*)(0x42C400B4UL))\r
+#define bFM3_CAN0_ERRCNT_REC6                  *((volatile unsigned int*)(0x42C400B8UL))\r
+#define bFM3_CAN0_ERRCNT_RP                    *((volatile unsigned int*)(0x42C400BCUL))\r
+#define bFM3_CAN0_BTR_BRP0                     *((volatile unsigned int*)(0x42C400C0UL))\r
+#define bFM3_CAN0_BTR_BRP1                     *((volatile unsigned int*)(0x42C400C4UL))\r
+#define bFM3_CAN0_BTR_BRP2                     *((volatile unsigned int*)(0x42C400C8UL))\r
+#define bFM3_CAN0_BTR_BRP3                     *((volatile unsigned int*)(0x42C400CCUL))\r
+#define bFM3_CAN0_BTR_BRP4                     *((volatile unsigned int*)(0x42C400D0UL))\r
+#define bFM3_CAN0_BTR_BRP5                     *((volatile unsigned int*)(0x42C400D4UL))\r
+#define bFM3_CAN0_BTR_SJW0                     *((volatile unsigned int*)(0x42C400D8UL))\r
+#define bFM3_CAN0_BTR_SJW1                     *((volatile unsigned int*)(0x42C400DCUL))\r
+#define bFM3_CAN0_BTR_TSEG10                   *((volatile unsigned int*)(0x42C400E0UL))\r
+#define bFM3_CAN0_BTR_TSEG11                   *((volatile unsigned int*)(0x42C400E4UL))\r
+#define bFM3_CAN0_BTR_TSEG12                   *((volatile unsigned int*)(0x42C400E8UL))\r
+#define bFM3_CAN0_BTR_TSEG13                   *((volatile unsigned int*)(0x42C400ECUL))\r
+#define bFM3_CAN0_BTR_TSEG20                   *((volatile unsigned int*)(0x42C400F0UL))\r
+#define bFM3_CAN0_BTR_TSEG21                   *((volatile unsigned int*)(0x42C400F4UL))\r
+#define bFM3_CAN0_BTR_TSEG22                   *((volatile unsigned int*)(0x42C400F8UL))\r
+#define bFM3_CAN0_INTR_INTID0                  *((volatile unsigned int*)(0x42C40100UL))\r
+#define bFM3_CAN0_INTR_INTID1                  *((volatile unsigned int*)(0x42C40104UL))\r
+#define bFM3_CAN0_INTR_INTID2                  *((volatile unsigned int*)(0x42C40108UL))\r
+#define bFM3_CAN0_INTR_INTID3                  *((volatile unsigned int*)(0x42C4010CUL))\r
+#define bFM3_CAN0_INTR_INTID4                  *((volatile unsigned int*)(0x42C40110UL))\r
+#define bFM3_CAN0_INTR_INTID5                  *((volatile unsigned int*)(0x42C40114UL))\r
+#define bFM3_CAN0_INTR_INTID6                  *((volatile unsigned int*)(0x42C40118UL))\r
+#define bFM3_CAN0_INTR_INTID7                  *((volatile unsigned int*)(0x42C4011CUL))\r
+#define bFM3_CAN0_INTR_INTID8                  *((volatile unsigned int*)(0x42C40120UL))\r
+#define bFM3_CAN0_INTR_INTID9                  *((volatile unsigned int*)(0x42C40124UL))\r
+#define bFM3_CAN0_INTR_INTID10                 *((volatile unsigned int*)(0x42C40128UL))\r
+#define bFM3_CAN0_INTR_INTID11                 *((volatile unsigned int*)(0x42C4012CUL))\r
+#define bFM3_CAN0_INTR_INTID12                 *((volatile unsigned int*)(0x42C40130UL))\r
+#define bFM3_CAN0_INTR_INTID13                 *((volatile unsigned int*)(0x42C40134UL))\r
+#define bFM3_CAN0_INTR_INTID14                 *((volatile unsigned int*)(0x42C40138UL))\r
+#define bFM3_CAN0_INTR_INTID15                 *((volatile unsigned int*)(0x42C4013CUL))\r
+#define bFM3_CAN0_TESTR_BASIC                  *((volatile unsigned int*)(0x42C40148UL))\r
+#define bFM3_CAN0_TESTR_SILENT                 *((volatile unsigned int*)(0x42C4014CUL))\r
+#define bFM3_CAN0_TESTR_LBACK                  *((volatile unsigned int*)(0x42C40150UL))\r
+#define bFM3_CAN0_TESTR_TX0                    *((volatile unsigned int*)(0x42C40154UL))\r
+#define bFM3_CAN0_TESTR_TX1                    *((volatile unsigned int*)(0x42C40158UL))\r
+#define bFM3_CAN0_TESTR_RX                     *((volatile unsigned int*)(0x42C4015CUL))\r
+#define bFM3_CAN0_BRPER_BRPE0                  *((volatile unsigned int*)(0x42C40180UL))\r
+#define bFM3_CAN0_BRPER_BRPE1                  *((volatile unsigned int*)(0x42C40184UL))\r
+#define bFM3_CAN0_BRPER_BRPE2                  *((volatile unsigned int*)(0x42C40188UL))\r
+#define bFM3_CAN0_BRPER_BRPE3                  *((volatile unsigned int*)(0x42C4018CUL))\r
+#define bFM3_CAN0_IF1CREQ_BUSY                 *((volatile unsigned int*)(0x42C4023CUL))\r
+#define bFM3_CAN0_IF1CMSK_DATAB                *((volatile unsigned int*)(0x42C40240UL))\r
+#define bFM3_CAN0_IF1CMSK_DATAA                *((volatile unsigned int*)(0x42C40244UL))\r
+#define bFM3_CAN0_IF1CMSK_TXREST               *((volatile unsigned int*)(0x42C40248UL))\r
+#define bFM3_CAN0_IF1CMSK_NEWDAT               *((volatile unsigned int*)(0x42C40248UL))\r
+#define bFM3_CAN0_IF1CMSK_CIP                  *((volatile unsigned int*)(0x42C4024CUL))\r
+#define bFM3_CAN0_IF1CMSK_CONTROL              *((volatile unsigned int*)(0x42C40250UL))\r
+#define bFM3_CAN0_IF1CMSK_ARB                  *((volatile unsigned int*)(0x42C40254UL))\r
+#define bFM3_CAN0_IF1CMSK_MASK                 *((volatile unsigned int*)(0x42C40258UL))\r
+#define bFM3_CAN0_IF1CMSK_WRRD                 *((volatile unsigned int*)(0x42C4025CUL))\r
+#define bFM3_CAN0_IF1MSK_MDIR                  *((volatile unsigned int*)(0x42C402F8UL))\r
+#define bFM3_CAN0_IF1MSK_MXTD                  *((volatile unsigned int*)(0x42C402FCUL))\r
+#define bFM3_CAN0_IF1MSK2_MDIR                 *((volatile unsigned int*)(0x42C402F8UL))\r
+#define bFM3_CAN0_IF1MSK2_MXTD                 *((volatile unsigned int*)(0x42C402FCUL))\r
+#define bFM3_CAN0_IF1ARB_DIR                   *((volatile unsigned int*)(0x42C40374UL))\r
+#define bFM3_CAN0_IF1ARB_XTD                   *((volatile unsigned int*)(0x42C40378UL))\r
+#define bFM3_CAN0_IF1ARB_MSGVAL                *((volatile unsigned int*)(0x42C4037CUL))\r
+#define bFM3_CAN0_IF1ARB2_DIR                  *((volatile unsigned int*)(0x42C40374UL))\r
+#define bFM3_CAN0_IF1ARB2_XTD                  *((volatile unsigned int*)(0x42C40378UL))\r
+#define bFM3_CAN0_IF1ARB2_MSGVAL               *((volatile unsigned int*)(0x42C4037CUL))\r
+#define bFM3_CAN0_IF1MCTR_DLC0                 *((volatile unsigned int*)(0x42C40380UL))\r
+#define bFM3_CAN0_IF1MCTR_DLC1                 *((volatile unsigned int*)(0x42C40384UL))\r
+#define bFM3_CAN0_IF1MCTR_DLC2                 *((volatile unsigned int*)(0x42C40388UL))\r
+#define bFM3_CAN0_IF1MCTR_DLC3                 *((volatile unsigned int*)(0x42C4038CUL))\r
+#define bFM3_CAN0_IF1MCTR_EOB                  *((volatile unsigned int*)(0x42C4039CUL))\r
+#define bFM3_CAN0_IF1MCTR_TXRQST               *((volatile unsigned int*)(0x42C403A0UL))\r
+#define bFM3_CAN0_IF1MCTR_RMTEN                *((volatile unsigned int*)(0x42C403A4UL))\r
+#define bFM3_CAN0_IF1MCTR_RXIE                 *((volatile unsigned int*)(0x42C403A8UL))\r
+#define bFM3_CAN0_IF1MCTR_TXIE                 *((volatile unsigned int*)(0x42C403ACUL))\r
+#define bFM3_CAN0_IF1MCTR_UMASK                *((volatile unsigned int*)(0x42C403B0UL))\r
+#define bFM3_CAN0_IF1MCTR_INTPND               *((volatile unsigned int*)(0x42C403B4UL))\r
+#define bFM3_CAN0_IF1MCTR_MSGLST               *((volatile unsigned int*)(0x42C403B8UL))\r
+#define bFM3_CAN0_IF1MCTR_NEWDAT               *((volatile unsigned int*)(0x42C403BCUL))\r
+#define bFM3_CAN0_IF2CREQ_BUSY                 *((volatile unsigned int*)(0x42C4083CUL))\r
+#define bFM3_CAN0_IF2CMSK_DATAB                *((volatile unsigned int*)(0x42C40840UL))\r
+#define bFM3_CAN0_IF2CMSK_DATAA                *((volatile unsigned int*)(0x42C40844UL))\r
+#define bFM3_CAN0_IF2CMSK_TXREST               *((volatile unsigned int*)(0x42C40848UL))\r
+#define bFM3_CAN0_IF2CMSK_NEWDAT               *((volatile unsigned int*)(0x42C40848UL))\r
+#define bFM3_CAN0_IF2CMSK_CIP                  *((volatile unsigned int*)(0x42C4084CUL))\r
+#define bFM3_CAN0_IF2CMSK_CONTROL              *((volatile unsigned int*)(0x42C40850UL))\r
+#define bFM3_CAN0_IF2CMSK_ARB                  *((volatile unsigned int*)(0x42C40854UL))\r
+#define bFM3_CAN0_IF2CMSK_MASK                 *((volatile unsigned int*)(0x42C40858UL))\r
+#define bFM3_CAN0_IF2CMSK_WRRD                 *((volatile unsigned int*)(0x42C4085CUL))\r
+#define bFM3_CAN0_IF2MSK_MDIR                  *((volatile unsigned int*)(0x42C408F8UL))\r
+#define bFM3_CAN0_IF2MSK_MXTD                  *((volatile unsigned int*)(0x42C408FCUL))\r
+#define bFM3_CAN0_IF2MSK2_MDIR                 *((volatile unsigned int*)(0x42C408F8UL))\r
+#define bFM3_CAN0_IF2MSK2_MXTD                 *((volatile unsigned int*)(0x42C408FCUL))\r
+#define bFM3_CAN0_IF2ARB_DIR                   *((volatile unsigned int*)(0x42C40974UL))\r
+#define bFM3_CAN0_IF2ARB_XTD                   *((volatile unsigned int*)(0x42C40978UL))\r
+#define bFM3_CAN0_IF2ARB_MSGVAL                *((volatile unsigned int*)(0x42C4097CUL))\r
+#define bFM3_CAN0_IF2ARB2_DIR                  *((volatile unsigned int*)(0x42C40974UL))\r
+#define bFM3_CAN0_IF2ARB2_XTD                  *((volatile unsigned int*)(0x42C40978UL))\r
+#define bFM3_CAN0_IF2ARB2_MSGVAL               *((volatile unsigned int*)(0x42C4097CUL))\r
+#define bFM3_CAN0_IF2MCTR_DLC0                 *((volatile unsigned int*)(0x42C40980UL))\r
+#define bFM3_CAN0_IF2MCTR_DLC1                 *((volatile unsigned int*)(0x42C40984UL))\r
+#define bFM3_CAN0_IF2MCTR_DLC2                 *((volatile unsigned int*)(0x42C40988UL))\r
+#define bFM3_CAN0_IF2MCTR_DLC3                 *((volatile unsigned int*)(0x42C4098CUL))\r
+#define bFM3_CAN0_IF2MCTR_EOB                  *((volatile unsigned int*)(0x42C4099CUL))\r
+#define bFM3_CAN0_IF2MCTR_TXRQST               *((volatile unsigned int*)(0x42C409A0UL))\r
+#define bFM3_CAN0_IF2MCTR_RMTEN                *((volatile unsigned int*)(0x42C409A4UL))\r
+#define bFM3_CAN0_IF2MCTR_RXIE                 *((volatile unsigned int*)(0x42C409A8UL))\r
+#define bFM3_CAN0_IF2MCTR_TXIE                 *((volatile unsigned int*)(0x42C409ACUL))\r
+#define bFM3_CAN0_IF2MCTR_UMASK                *((volatile unsigned int*)(0x42C409B0UL))\r
+#define bFM3_CAN0_IF2MCTR_INTPND               *((volatile unsigned int*)(0x42C409B4UL))\r
+#define bFM3_CAN0_IF2MCTR_MSGLST               *((volatile unsigned int*)(0x42C409B8UL))\r
+#define bFM3_CAN0_IF2MCTR_NEWDAT               *((volatile unsigned int*)(0x42C409BCUL))\r
+#define bFM3_CAN0_TREQR_TXRQST1                *((volatile unsigned int*)(0x42C41000UL))\r
+#define bFM3_CAN0_TREQR_TXRQST2                *((volatile unsigned int*)(0x42C41004UL))\r
+#define bFM3_CAN0_TREQR_TXRQST3                *((volatile unsigned int*)(0x42C41008UL))\r
+#define bFM3_CAN0_TREQR_TXRQST4                *((volatile unsigned int*)(0x42C4100CUL))\r
+#define bFM3_CAN0_TREQR_TXRQST5                *((volatile unsigned int*)(0x42C41010UL))\r
+#define bFM3_CAN0_TREQR_TXRQST6                *((volatile unsigned int*)(0x42C41014UL))\r
+#define bFM3_CAN0_TREQR_TXRQST7                *((volatile unsigned int*)(0x42C41018UL))\r
+#define bFM3_CAN0_TREQR_TXRQST8                *((volatile unsigned int*)(0x42C4101CUL))\r
+#define bFM3_CAN0_TREQR_TXRQST9                *((volatile unsigned int*)(0x42C41020UL))\r
+#define bFM3_CAN0_TREQR_TXRQST10               *((volatile unsigned int*)(0x42C41024UL))\r
+#define bFM3_CAN0_TREQR_TXRQST11               *((volatile unsigned int*)(0x42C41028UL))\r
+#define bFM3_CAN0_TREQR_TXRQST12               *((volatile unsigned int*)(0x42C4102CUL))\r
+#define bFM3_CAN0_TREQR_TXRQST13               *((volatile unsigned int*)(0x42C41030UL))\r
+#define bFM3_CAN0_TREQR_TXRQST14               *((volatile unsigned int*)(0x42C41034UL))\r
+#define bFM3_CAN0_TREQR_TXRQST15               *((volatile unsigned int*)(0x42C41038UL))\r
+#define bFM3_CAN0_TREQR_TXRQST16               *((volatile unsigned int*)(0x42C4103CUL))\r
+#define bFM3_CAN0_TREQR_TXRQST17               *((volatile unsigned int*)(0x42C41040UL))\r
+#define bFM3_CAN0_TREQR_TXRQST18               *((volatile unsigned int*)(0x42C41044UL))\r
+#define bFM3_CAN0_TREQR_TXRQST19               *((volatile unsigned int*)(0x42C41048UL))\r
+#define bFM3_CAN0_TREQR_TXRQST20               *((volatile unsigned int*)(0x42C4104CUL))\r
+#define bFM3_CAN0_TREQR_TXRQST21               *((volatile unsigned int*)(0x42C41050UL))\r
+#define bFM3_CAN0_TREQR_TXRQST22               *((volatile unsigned int*)(0x42C41054UL))\r
+#define bFM3_CAN0_TREQR_TXRQST23               *((volatile unsigned int*)(0x42C41058UL))\r
+#define bFM3_CAN0_TREQR_TXRQST24               *((volatile unsigned int*)(0x42C4105CUL))\r
+#define bFM3_CAN0_TREQR_TXRQST25               *((volatile unsigned int*)(0x42C41060UL))\r
+#define bFM3_CAN0_TREQR_TXRQST26               *((volatile unsigned int*)(0x42C41064UL))\r
+#define bFM3_CAN0_TREQR_TXRQST27               *((volatile unsigned int*)(0x42C41068UL))\r
+#define bFM3_CAN0_TREQR_TXRQST28               *((volatile unsigned int*)(0x42C4106CUL))\r
+#define bFM3_CAN0_TREQR_TXRQST29               *((volatile unsigned int*)(0x42C41070UL))\r
+#define bFM3_CAN0_TREQR_TXRQST30               *((volatile unsigned int*)(0x42C41074UL))\r
+#define bFM3_CAN0_TREQR_TXRQST31               *((volatile unsigned int*)(0x42C41078UL))\r
+#define bFM3_CAN0_TREQR_TXRQST32               *((volatile unsigned int*)(0x42C4107CUL))\r
+#define bFM3_CAN0_TREQR1_TXRQST1               *((volatile unsigned int*)(0x42C41000UL))\r
+#define bFM3_CAN0_TREQR1_TXRQST2               *((volatile unsigned int*)(0x42C41004UL))\r
+#define bFM3_CAN0_TREQR1_TXRQST3               *((volatile unsigned int*)(0x42C41008UL))\r
+#define bFM3_CAN0_TREQR1_TXRQST4               *((volatile unsigned int*)(0x42C4100CUL))\r
+#define bFM3_CAN0_TREQR1_TXRQST5               *((volatile unsigned int*)(0x42C41010UL))\r
+#define bFM3_CAN0_TREQR1_TXRQST6               *((volatile unsigned int*)(0x42C41014UL))\r
+#define bFM3_CAN0_TREQR1_TXRQST7               *((volatile unsigned int*)(0x42C41018UL))\r
+#define bFM3_CAN0_TREQR1_TXRQST8               *((volatile unsigned int*)(0x42C4101CUL))\r
+#define bFM3_CAN0_TREQR1_TXRQST9               *((volatile unsigned int*)(0x42C41020UL))\r
+#define bFM3_CAN0_TREQR1_TXRQST10              *((volatile unsigned int*)(0x42C41024UL))\r
+#define bFM3_CAN0_TREQR1_TXRQST11              *((volatile unsigned int*)(0x42C41028UL))\r
+#define bFM3_CAN0_TREQR1_TXRQST12              *((volatile unsigned int*)(0x42C4102CUL))\r
+#define bFM3_CAN0_TREQR1_TXRQST13              *((volatile unsigned int*)(0x42C41030UL))\r
+#define bFM3_CAN0_TREQR1_TXRQST14              *((volatile unsigned int*)(0x42C41034UL))\r
+#define bFM3_CAN0_TREQR1_TXRQST15              *((volatile unsigned int*)(0x42C41038UL))\r
+#define bFM3_CAN0_TREQR1_TXRQST16              *((volatile unsigned int*)(0x42C4103CUL))\r
+#define bFM3_CAN0_TREQR2_TXRQST17              *((volatile unsigned int*)(0x42C41040UL))\r
+#define bFM3_CAN0_TREQR2_TXRQST18              *((volatile unsigned int*)(0x42C41044UL))\r
+#define bFM3_CAN0_TREQR2_TXRQST19              *((volatile unsigned int*)(0x42C41048UL))\r
+#define bFM3_CAN0_TREQR2_TXRQST20              *((volatile unsigned int*)(0x42C4104CUL))\r
+#define bFM3_CAN0_TREQR2_TXRQST21              *((volatile unsigned int*)(0x42C41050UL))\r
+#define bFM3_CAN0_TREQR2_TXRQST22              *((volatile unsigned int*)(0x42C41054UL))\r
+#define bFM3_CAN0_TREQR2_TXRQST23              *((volatile unsigned int*)(0x42C41058UL))\r
+#define bFM3_CAN0_TREQR2_TXRQST24              *((volatile unsigned int*)(0x42C4105CUL))\r
+#define bFM3_CAN0_TREQR2_TXRQST25              *((volatile unsigned int*)(0x42C41060UL))\r
+#define bFM3_CAN0_TREQR2_TXRQST26              *((volatile unsigned int*)(0x42C41064UL))\r
+#define bFM3_CAN0_TREQR2_TXRQST27              *((volatile unsigned int*)(0x42C41068UL))\r
+#define bFM3_CAN0_TREQR2_TXRQST28              *((volatile unsigned int*)(0x42C4106CUL))\r
+#define bFM3_CAN0_TREQR2_TXRQST29              *((volatile unsigned int*)(0x42C41070UL))\r
+#define bFM3_CAN0_TREQR2_TXRQST30              *((volatile unsigned int*)(0x42C41074UL))\r
+#define bFM3_CAN0_TREQR2_TXRQST31              *((volatile unsigned int*)(0x42C41078UL))\r
+#define bFM3_CAN0_TREQR2_TXRQST32              *((volatile unsigned int*)(0x42C4107CUL))\r
+#define bFM3_CAN0_NEWDT_NEWDAT1                *((volatile unsigned int*)(0x42C41200UL))\r
+#define bFM3_CAN0_NEWDT_NEWDAT2                *((volatile unsigned int*)(0x42C41204UL))\r
+#define bFM3_CAN0_NEWDT_NEWDAT3                *((volatile unsigned int*)(0x42C41208UL))\r
+#define bFM3_CAN0_NEWDT_NEWDAT4                *((volatile unsigned int*)(0x42C4120CUL))\r
+#define bFM3_CAN0_NEWDT_NEWDAT5                *((volatile unsigned int*)(0x42C41210UL))\r
+#define bFM3_CAN0_NEWDT_NEWDAT6                *((volatile unsigned int*)(0x42C41214UL))\r
+#define bFM3_CAN0_NEWDT_NEWDAT7                *((volatile unsigned int*)(0x42C41218UL))\r
+#define bFM3_CAN0_NEWDT_NEWDAT8                *((volatile unsigned int*)(0x42C4121CUL))\r
+#define bFM3_CAN0_NEWDT_NEWDAT9                *((volatile unsigned int*)(0x42C41220UL))\r
+#define bFM3_CAN0_NEWDT_NEWDAT10               *((volatile unsigned int*)(0x42C41224UL))\r
+#define bFM3_CAN0_NEWDT_NEWDAT11               *((volatile unsigned int*)(0x42C41228UL))\r
+#define bFM3_CAN0_NEWDT_NEWDAT12               *((volatile unsigned int*)(0x42C4122CUL))\r
+#define bFM3_CAN0_NEWDT_NEWDAT13               *((volatile unsigned int*)(0x42C41230UL))\r
+#define bFM3_CAN0_NEWDT_NEWDAT14               *((volatile unsigned int*)(0x42C41234UL))\r
+#define bFM3_CAN0_NEWDT_NEWDAT15               *((volatile unsigned int*)(0x42C41238UL))\r
+#define bFM3_CAN0_NEWDT_NEWDAT16               *((volatile unsigned int*)(0x42C4123CUL))\r
+#define bFM3_CAN0_NEWDT_NEWDAT17               *((volatile unsigned int*)(0x42C41240UL))\r
+#define bFM3_CAN0_NEWDT_NEWDAT18               *((volatile unsigned int*)(0x42C41244UL))\r
+#define bFM3_CAN0_NEWDT_NEWDAT19               *((volatile unsigned int*)(0x42C41248UL))\r
+#define bFM3_CAN0_NEWDT_NEWDAT20               *((volatile unsigned int*)(0x42C4124CUL))\r
+#define bFM3_CAN0_NEWDT_NEWDAT21               *((volatile unsigned int*)(0x42C41250UL))\r
+#define bFM3_CAN0_NEWDT_NEWDAT22               *((volatile unsigned int*)(0x42C41254UL))\r
+#define bFM3_CAN0_NEWDT_NEWDAT23               *((volatile unsigned int*)(0x42C41258UL))\r
+#define bFM3_CAN0_NEWDT_NEWDAT24               *((volatile unsigned int*)(0x42C4125CUL))\r
+#define bFM3_CAN0_NEWDT_NEWDAT25               *((volatile unsigned int*)(0x42C41260UL))\r
+#define bFM3_CAN0_NEWDT_NEWDAT26               *((volatile unsigned int*)(0x42C41264UL))\r
+#define bFM3_CAN0_NEWDT_NEWDAT27               *((volatile unsigned int*)(0x42C41268UL))\r
+#define bFM3_CAN0_NEWDT_NEWDAT28               *((volatile unsigned int*)(0x42C4126CUL))\r
+#define bFM3_CAN0_NEWDT_NEWDAT29               *((volatile unsigned int*)(0x42C41270UL))\r
+#define bFM3_CAN0_NEWDT_NEWDAT30               *((volatile unsigned int*)(0x42C41274UL))\r
+#define bFM3_CAN0_NEWDT_NEWDAT31               *((volatile unsigned int*)(0x42C41278UL))\r
+#define bFM3_CAN0_NEWDT_NEWDAT32               *((volatile unsigned int*)(0x42C4127CUL))\r
+#define bFM3_CAN0_NEWDT1_NEWDAT1               *((volatile unsigned int*)(0x42C41200UL))\r
+#define bFM3_CAN0_NEWDT1_NEWDAT2               *((volatile unsigned int*)(0x42C41204UL))\r
+#define bFM3_CAN0_NEWDT1_NEWDAT3               *((volatile unsigned int*)(0x42C41208UL))\r
+#define bFM3_CAN0_NEWDT1_NEWDAT4               *((volatile unsigned int*)(0x42C4120CUL))\r
+#define bFM3_CAN0_NEWDT1_NEWDAT5               *((volatile unsigned int*)(0x42C41210UL))\r
+#define bFM3_CAN0_NEWDT1_NEWDAT6               *((volatile unsigned int*)(0x42C41214UL))\r
+#define bFM3_CAN0_NEWDT1_NEWDAT7               *((volatile unsigned int*)(0x42C41218UL))\r
+#define bFM3_CAN0_NEWDT1_NEWDAT8               *((volatile unsigned int*)(0x42C4121CUL))\r
+#define bFM3_CAN0_NEWDT1_NEWDAT9               *((volatile unsigned int*)(0x42C41220UL))\r
+#define bFM3_CAN0_NEWDT1_NEWDAT10              *((volatile unsigned int*)(0x42C41224UL))\r
+#define bFM3_CAN0_NEWDT1_NEWDAT11              *((volatile unsigned int*)(0x42C41228UL))\r
+#define bFM3_CAN0_NEWDT1_NEWDAT12              *((volatile unsigned int*)(0x42C4122CUL))\r
+#define bFM3_CAN0_NEWDT1_NEWDAT13              *((volatile unsigned int*)(0x42C41230UL))\r
+#define bFM3_CAN0_NEWDT1_NEWDAT14              *((volatile unsigned int*)(0x42C41234UL))\r
+#define bFM3_CAN0_NEWDT1_NEWDAT15              *((volatile unsigned int*)(0x42C41238UL))\r
+#define bFM3_CAN0_NEWDT1_NEWDAT16              *((volatile unsigned int*)(0x42C4123CUL))\r
+#define bFM3_CAN0_NEWDT2_NEWDAT17              *((volatile unsigned int*)(0x42C41240UL))\r
+#define bFM3_CAN0_NEWDT2_NEWDAT18              *((volatile unsigned int*)(0x42C41244UL))\r
+#define bFM3_CAN0_NEWDT2_NEWDAT19              *((volatile unsigned int*)(0x42C41248UL))\r
+#define bFM3_CAN0_NEWDT2_NEWDAT20              *((volatile unsigned int*)(0x42C4124CUL))\r
+#define bFM3_CAN0_NEWDT2_NEWDAT21              *((volatile unsigned int*)(0x42C41250UL))\r
+#define bFM3_CAN0_NEWDT2_NEWDAT22              *((volatile unsigned int*)(0x42C41254UL))\r
+#define bFM3_CAN0_NEWDT2_NEWDAT23              *((volatile unsigned int*)(0x42C41258UL))\r
+#define bFM3_CAN0_NEWDT2_NEWDAT24              *((volatile unsigned int*)(0x42C4125CUL))\r
+#define bFM3_CAN0_NEWDT2_NEWDAT25              *((volatile unsigned int*)(0x42C41260UL))\r
+#define bFM3_CAN0_NEWDT2_NEWDAT26              *((volatile unsigned int*)(0x42C41264UL))\r
+#define bFM3_CAN0_NEWDT2_NEWDAT27              *((volatile unsigned int*)(0x42C41268UL))\r
+#define bFM3_CAN0_NEWDT2_NEWDAT28              *((volatile unsigned int*)(0x42C4126CUL))\r
+#define bFM3_CAN0_NEWDT2_NEWDAT29              *((volatile unsigned int*)(0x42C41270UL))\r
+#define bFM3_CAN0_NEWDT2_NEWDAT30              *((volatile unsigned int*)(0x42C41274UL))\r
+#define bFM3_CAN0_NEWDT2_NEWDAT31              *((volatile unsigned int*)(0x42C41278UL))\r
+#define bFM3_CAN0_NEWDT2_NEWDAT32              *((volatile unsigned int*)(0x42C4127CUL))\r
+#define bFM3_CAN0_INTPND_INTPND1               *((volatile unsigned int*)(0x42C41400UL))\r
+#define bFM3_CAN0_INTPND_INTPND2               *((volatile unsigned int*)(0x42C41404UL))\r
+#define bFM3_CAN0_INTPND_INTPND3               *((volatile unsigned int*)(0x42C41408UL))\r
+#define bFM3_CAN0_INTPND_INTPND4               *((volatile unsigned int*)(0x42C4140CUL))\r
+#define bFM3_CAN0_INTPND_INTPND5               *((volatile unsigned int*)(0x42C41410UL))\r
+#define bFM3_CAN0_INTPND_INTPND6               *((volatile unsigned int*)(0x42C41414UL))\r
+#define bFM3_CAN0_INTPND_INTPND7               *((volatile unsigned int*)(0x42C41418UL))\r
+#define bFM3_CAN0_INTPND_INTPND8               *((volatile unsigned int*)(0x42C4141CUL))\r
+#define bFM3_CAN0_INTPND_INTPND9               *((volatile unsigned int*)(0x42C41420UL))\r
+#define bFM3_CAN0_INTPND_INTPND10              *((volatile unsigned int*)(0x42C41424UL))\r
+#define bFM3_CAN0_INTPND_INTPND11              *((volatile unsigned int*)(0x42C41428UL))\r
+#define bFM3_CAN0_INTPND_INTPND12              *((volatile unsigned int*)(0x42C4142CUL))\r
+#define bFM3_CAN0_INTPND_INTPND13              *((volatile unsigned int*)(0x42C41430UL))\r
+#define bFM3_CAN0_INTPND_INTPND14              *((volatile unsigned int*)(0x42C41434UL))\r
+#define bFM3_CAN0_INTPND_INTPND15              *((volatile unsigned int*)(0x42C41438UL))\r
+#define bFM3_CAN0_INTPND_INTPND16              *((volatile unsigned int*)(0x42C4143CUL))\r
+#define bFM3_CAN0_INTPND_INTPND17              *((volatile unsigned int*)(0x42C41440UL))\r
+#define bFM3_CAN0_INTPND_INTPND18              *((volatile unsigned int*)(0x42C41444UL))\r
+#define bFM3_CAN0_INTPND_INTPND19              *((volatile unsigned int*)(0x42C41448UL))\r
+#define bFM3_CAN0_INTPND_INTPND20              *((volatile unsigned int*)(0x42C4144CUL))\r
+#define bFM3_CAN0_INTPND_INTPND21              *((volatile unsigned int*)(0x42C41450UL))\r
+#define bFM3_CAN0_INTPND_INTPND22              *((volatile unsigned int*)(0x42C41454UL))\r
+#define bFM3_CAN0_INTPND_INTPND23              *((volatile unsigned int*)(0x42C41458UL))\r
+#define bFM3_CAN0_INTPND_INTPND24              *((volatile unsigned int*)(0x42C4145CUL))\r
+#define bFM3_CAN0_INTPND_INTPND25              *((volatile unsigned int*)(0x42C41460UL))\r
+#define bFM3_CAN0_INTPND_INTPND26              *((volatile unsigned int*)(0x42C41464UL))\r
+#define bFM3_CAN0_INTPND_INTPND27              *((volatile unsigned int*)(0x42C41468UL))\r
+#define bFM3_CAN0_INTPND_INTPND28              *((volatile unsigned int*)(0x42C4146CUL))\r
+#define bFM3_CAN0_INTPND_INTPND29              *((volatile unsigned int*)(0x42C41470UL))\r
+#define bFM3_CAN0_INTPND_INTPND30              *((volatile unsigned int*)(0x42C41474UL))\r
+#define bFM3_CAN0_INTPND_INTPND31              *((volatile unsigned int*)(0x42C41478UL))\r
+#define bFM3_CAN0_INTPND_INTPND32              *((volatile unsigned int*)(0x42C4147CUL))\r
+#define bFM3_CAN0_INTPND1_INTPND1              *((volatile unsigned int*)(0x42C41400UL))\r
+#define bFM3_CAN0_INTPND1_INTPND2              *((volatile unsigned int*)(0x42C41404UL))\r
+#define bFM3_CAN0_INTPND1_INTPND3              *((volatile unsigned int*)(0x42C41408UL))\r
+#define bFM3_CAN0_INTPND1_INTPND4              *((volatile unsigned int*)(0x42C4140CUL))\r
+#define bFM3_CAN0_INTPND1_INTPND5              *((volatile unsigned int*)(0x42C41410UL))\r
+#define bFM3_CAN0_INTPND1_INTPND6              *((volatile unsigned int*)(0x42C41414UL))\r
+#define bFM3_CAN0_INTPND1_INTPND7              *((volatile unsigned int*)(0x42C41418UL))\r
+#define bFM3_CAN0_INTPND1_INTPND8              *((volatile unsigned int*)(0x42C4141CUL))\r
+#define bFM3_CAN0_INTPND1_INTPND9              *((volatile unsigned int*)(0x42C41420UL))\r
+#define bFM3_CAN0_INTPND1_INTPND10             *((volatile unsigned int*)(0x42C41424UL))\r
+#define bFM3_CAN0_INTPND1_INTPND11             *((volatile unsigned int*)(0x42C41428UL))\r
+#define bFM3_CAN0_INTPND1_INTPND12             *((volatile unsigned int*)(0x42C4142CUL))\r
+#define bFM3_CAN0_INTPND1_INTPND13             *((volatile unsigned int*)(0x42C41430UL))\r
+#define bFM3_CAN0_INTPND1_INTPND14             *((volatile unsigned int*)(0x42C41434UL))\r
+#define bFM3_CAN0_INTPND1_INTPND15             *((volatile unsigned int*)(0x42C41438UL))\r
+#define bFM3_CAN0_INTPND1_INTPND16             *((volatile unsigned int*)(0x42C4143CUL))\r
+#define bFM3_CAN0_INTPND2_INTPND17             *((volatile unsigned int*)(0x42C41440UL))\r
+#define bFM3_CAN0_INTPND2_INTPND18             *((volatile unsigned int*)(0x42C41444UL))\r
+#define bFM3_CAN0_INTPND2_INTPND19             *((volatile unsigned int*)(0x42C41448UL))\r
+#define bFM3_CAN0_INTPND2_INTPND20             *((volatile unsigned int*)(0x42C4144CUL))\r
+#define bFM3_CAN0_INTPND2_INTPND21             *((volatile unsigned int*)(0x42C41450UL))\r
+#define bFM3_CAN0_INTPND2_INTPND22             *((volatile unsigned int*)(0x42C41454UL))\r
+#define bFM3_CAN0_INTPND2_INTPND23             *((volatile unsigned int*)(0x42C41458UL))\r
+#define bFM3_CAN0_INTPND2_INTPND24             *((volatile unsigned int*)(0x42C4145CUL))\r
+#define bFM3_CAN0_INTPND2_INTPND25             *((volatile unsigned int*)(0x42C41460UL))\r
+#define bFM3_CAN0_INTPND2_INTPND26             *((volatile unsigned int*)(0x42C41464UL))\r
+#define bFM3_CAN0_INTPND2_INTPND27             *((volatile unsigned int*)(0x42C41468UL))\r
+#define bFM3_CAN0_INTPND2_INTPND28             *((volatile unsigned int*)(0x42C4146CUL))\r
+#define bFM3_CAN0_INTPND2_INTPND29             *((volatile unsigned int*)(0x42C41470UL))\r
+#define bFM3_CAN0_INTPND2_INTPND30             *((volatile unsigned int*)(0x42C41474UL))\r
+#define bFM3_CAN0_INTPND2_INTPND31             *((volatile unsigned int*)(0x42C41478UL))\r
+#define bFM3_CAN0_INTPND2_INTPND32             *((volatile unsigned int*)(0x42C4147CUL))\r
+#define bFM3_CAN0_MSGVAL_MSGVAL1               *((volatile unsigned int*)(0x42C41600UL))\r
+#define bFM3_CAN0_MSGVAL_MSGVAL2               *((volatile unsigned int*)(0x42C41604UL))\r
+#define bFM3_CAN0_MSGVAL_MSGVAL3               *((volatile unsigned int*)(0x42C41608UL))\r
+#define bFM3_CAN0_MSGVAL_MSGVAL4               *((volatile unsigned int*)(0x42C4160CUL))\r
+#define bFM3_CAN0_MSGVAL_MSGVAL5               *((volatile unsigned int*)(0x42C41610UL))\r
+#define bFM3_CAN0_MSGVAL_MSGVAL6               *((volatile unsigned int*)(0x42C41614UL))\r
+#define bFM3_CAN0_MSGVAL_MSGVAL7               *((volatile unsigned int*)(0x42C41618UL))\r
+#define bFM3_CAN0_MSGVAL_MSGVAL8               *((volatile unsigned int*)(0x42C4161CUL))\r
+#define bFM3_CAN0_MSGVAL_MSGVAL9               *((volatile unsigned int*)(0x42C41620UL))\r
+#define bFM3_CAN0_MSGVAL_MSGVAL10              *((volatile unsigned int*)(0x42C41624UL))\r
+#define bFM3_CAN0_MSGVAL_MSGVAL11              *((volatile unsigned int*)(0x42C41628UL))\r
+#define bFM3_CAN0_MSGVAL_MSGVAL12              *((volatile unsigned int*)(0x42C4162CUL))\r
+#define bFM3_CAN0_MSGVAL_MSGVAL13              *((volatile unsigned int*)(0x42C41630UL))\r
+#define bFM3_CAN0_MSGVAL_MSGVAL14              *((volatile unsigned int*)(0x42C41634UL))\r
+#define bFM3_CAN0_MSGVAL_MSGVAL15              *((volatile unsigned int*)(0x42C41638UL))\r
+#define bFM3_CAN0_MSGVAL_MSGVAL16              *((volatile unsigned int*)(0x42C4163CUL))\r
+#define bFM3_CAN0_MSGVAL_MSGVAL17              *((volatile unsigned int*)(0x42C41640UL))\r
+#define bFM3_CAN0_MSGVAL_MSGVAL18              *((volatile unsigned int*)(0x42C41644UL))\r
+#define bFM3_CAN0_MSGVAL_MSGVAL19              *((volatile unsigned int*)(0x42C41648UL))\r
+#define bFM3_CAN0_MSGVAL_MSGVAL20              *((volatile unsigned int*)(0x42C4164CUL))\r
+#define bFM3_CAN0_MSGVAL_MSGVAL21              *((volatile unsigned int*)(0x42C41650UL))\r
+#define bFM3_CAN0_MSGVAL_MSGVAL22              *((volatile unsigned int*)(0x42C41654UL))\r
+#define bFM3_CAN0_MSGVAL_MSGVAL23              *((volatile unsigned int*)(0x42C41658UL))\r
+#define bFM3_CAN0_MSGVAL_MSGVAL24              *((volatile unsigned int*)(0x42C4165CUL))\r
+#define bFM3_CAN0_MSGVAL_MSGVAL25              *((volatile unsigned int*)(0x42C41660UL))\r
+#define bFM3_CAN0_MSGVAL_MSGVAL26              *((volatile unsigned int*)(0x42C41664UL))\r
+#define bFM3_CAN0_MSGVAL_MSGVAL27              *((volatile unsigned int*)(0x42C41668UL))\r
+#define bFM3_CAN0_MSGVAL_MSGVAL28              *((volatile unsigned int*)(0x42C4166CUL))\r
+#define bFM3_CAN0_MSGVAL_MSGVAL29              *((volatile unsigned int*)(0x42C41670UL))\r
+#define bFM3_CAN0_MSGVAL_MSGVAL30              *((volatile unsigned int*)(0x42C41674UL))\r
+#define bFM3_CAN0_MSGVAL_MSGVAL31              *((volatile unsigned int*)(0x42C41678UL))\r
+#define bFM3_CAN0_MSGVAL_MSGVAL32              *((volatile unsigned int*)(0x42C4167CUL))\r
+#define bFM3_CAN0_MSGVAL1_MSGVAL1              *((volatile unsigned int*)(0x42C41600UL))\r
+#define bFM3_CAN0_MSGVAL1_MSGVAL2              *((volatile unsigned int*)(0x42C41604UL))\r
+#define bFM3_CAN0_MSGVAL1_MSGVAL3              *((volatile unsigned int*)(0x42C41608UL))\r
+#define bFM3_CAN0_MSGVAL1_MSGVAL4              *((volatile unsigned int*)(0x42C4160CUL))\r
+#define bFM3_CAN0_MSGVAL1_MSGVAL5              *((volatile unsigned int*)(0x42C41610UL))\r
+#define bFM3_CAN0_MSGVAL1_MSGVAL6              *((volatile unsigned int*)(0x42C41614UL))\r
+#define bFM3_CAN0_MSGVAL1_MSGVAL7              *((volatile unsigned int*)(0x42C41618UL))\r
+#define bFM3_CAN0_MSGVAL1_MSGVAL8              *((volatile unsigned int*)(0x42C4161CUL))\r
+#define bFM3_CAN0_MSGVAL1_MSGVAL9              *((volatile unsigned int*)(0x42C41620UL))\r
+#define bFM3_CAN0_MSGVAL1_MSGVAL10             *((volatile unsigned int*)(0x42C41624UL))\r
+#define bFM3_CAN0_MSGVAL1_MSGVAL11             *((volatile unsigned int*)(0x42C41628UL))\r
+#define bFM3_CAN0_MSGVAL1_MSGVAL12             *((volatile unsigned int*)(0x42C4162CUL))\r
+#define bFM3_CAN0_MSGVAL1_MSGVAL13             *((volatile unsigned int*)(0x42C41630UL))\r
+#define bFM3_CAN0_MSGVAL1_MSGVAL14             *((volatile unsigned int*)(0x42C41634UL))\r
+#define bFM3_CAN0_MSGVAL1_MSGVAL15             *((volatile unsigned int*)(0x42C41638UL))\r
+#define bFM3_CAN0_MSGVAL1_MSGVAL16             *((volatile unsigned int*)(0x42C4163CUL))\r
+#define bFM3_CAN0_MSGVAL2_MSGVAL17             *((volatile unsigned int*)(0x42C41640UL))\r
+#define bFM3_CAN0_MSGVAL2_MSGVAL18             *((volatile unsigned int*)(0x42C41644UL))\r
+#define bFM3_CAN0_MSGVAL2_MSGVAL19             *((volatile unsigned int*)(0x42C41648UL))\r
+#define bFM3_CAN0_MSGVAL2_MSGVAL20             *((volatile unsigned int*)(0x42C4164CUL))\r
+#define bFM3_CAN0_MSGVAL2_MSGVAL21             *((volatile unsigned int*)(0x42C41650UL))\r
+#define bFM3_CAN0_MSGVAL2_MSGVAL22             *((volatile unsigned int*)(0x42C41654UL))\r
+#define bFM3_CAN0_MSGVAL2_MSGVAL23             *((volatile unsigned int*)(0x42C41658UL))\r
+#define bFM3_CAN0_MSGVAL2_MSGVAL24             *((volatile unsigned int*)(0x42C4165CUL))\r
+#define bFM3_CAN0_MSGVAL2_MSGVAL25             *((volatile unsigned int*)(0x42C41660UL))\r
+#define bFM3_CAN0_MSGVAL2_MSGVAL26             *((volatile unsigned int*)(0x42C41664UL))\r
+#define bFM3_CAN0_MSGVAL2_MSGVAL27             *((volatile unsigned int*)(0x42C41668UL))\r
+#define bFM3_CAN0_MSGVAL2_MSGVAL28             *((volatile unsigned int*)(0x42C4166CUL))\r
+#define bFM3_CAN0_MSGVAL2_MSGVAL29             *((volatile unsigned int*)(0x42C41670UL))\r
+#define bFM3_CAN0_MSGVAL2_MSGVAL30             *((volatile unsigned int*)(0x42C41674UL))\r
+#define bFM3_CAN0_MSGVAL2_MSGVAL31             *((volatile unsigned int*)(0x42C41678UL))\r
+#define bFM3_CAN0_MSGVAL2_MSGVAL32             *((volatile unsigned int*)(0x42C4167CUL))\r
+\r
+/* CAN channel 1 registers */\r
+#define bFM3_CAN1_CTRLR_INIT                   *((volatile unsigned int*)(0x42C60000UL))\r
+#define bFM3_CAN1_CTRLR_IE                     *((volatile unsigned int*)(0x42C60004UL))\r
+#define bFM3_CAN1_CTRLR_SIE                    *((volatile unsigned int*)(0x42C60008UL))\r
+#define bFM3_CAN1_CTRLR_EIE                    *((volatile unsigned int*)(0x42C6000CUL))\r
+#define bFM3_CAN1_CTRLR_DAR                    *((volatile unsigned int*)(0x42C60014UL))\r
+#define bFM3_CAN1_CTRLR_CCE                    *((volatile unsigned int*)(0x42C60018UL))\r
+#define bFM3_CAN1_CTRLR_TEST                   *((volatile unsigned int*)(0x42C6001CUL))\r
+#define bFM3_CAN1_STATR_LEC0                   *((volatile unsigned int*)(0x42C60040UL))\r
+#define bFM3_CAN1_STATR_LEC1                   *((volatile unsigned int*)(0x42C60044UL))\r
+#define bFM3_CAN1_STATR_LEC2                   *((volatile unsigned int*)(0x42C60048UL))\r
+#define bFM3_CAN1_STATR_TXOK                   *((volatile unsigned int*)(0x42C6004CUL))\r
+#define bFM3_CAN1_STATR_RXOK                   *((volatile unsigned int*)(0x42C60050UL))\r
+#define bFM3_CAN1_STATR_EPASS                  *((volatile unsigned int*)(0x42C60054UL))\r
+#define bFM3_CAN1_STATR_EWARM                  *((volatile unsigned int*)(0x42C60058UL))\r
+#define bFM3_CAN1_STATR_BOFF                   *((volatile unsigned int*)(0x42C6005CUL))\r
+#define bFM3_CAN1_ERRCNT_TEC0                  *((volatile unsigned int*)(0x42C60080UL))\r
+#define bFM3_CAN1_ERRCNT_TEC1                  *((volatile unsigned int*)(0x42C60084UL))\r
+#define bFM3_CAN1_ERRCNT_TEC2                  *((volatile unsigned int*)(0x42C60088UL))\r
+#define bFM3_CAN1_ERRCNT_TEC3                  *((volatile unsigned int*)(0x42C6008CUL))\r
+#define bFM3_CAN1_ERRCNT_TEC4                  *((volatile unsigned int*)(0x42C60090UL))\r
+#define bFM3_CAN1_ERRCNT_TEC5                  *((volatile unsigned int*)(0x42C60094UL))\r
+#define bFM3_CAN1_ERRCNT_TEC6                  *((volatile unsigned int*)(0x42C60098UL))\r
+#define bFM3_CAN1_ERRCNT_TEC7                  *((volatile unsigned int*)(0x42C6009CUL))\r
+#define bFM3_CAN1_ERRCNT_REC0                  *((volatile unsigned int*)(0x42C600A0UL))\r
+#define bFM3_CAN1_ERRCNT_REC1                  *((volatile unsigned int*)(0x42C600A4UL))\r
+#define bFM3_CAN1_ERRCNT_REC2                  *((volatile unsigned int*)(0x42C600A8UL))\r
+#define bFM3_CAN1_ERRCNT_REC3                  *((volatile unsigned int*)(0x42C600ACUL))\r
+#define bFM3_CAN1_ERRCNT_REC4                  *((volatile unsigned int*)(0x42C600B0UL))\r
+#define bFM3_CAN1_ERRCNT_REC5                  *((volatile unsigned int*)(0x42C600B4UL))\r
+#define bFM3_CAN1_ERRCNT_REC6                  *((volatile unsigned int*)(0x42C600B8UL))\r
+#define bFM3_CAN1_ERRCNT_RP                    *((volatile unsigned int*)(0x42C600BCUL))\r
+#define bFM3_CAN1_BTR_BRP0                     *((volatile unsigned int*)(0x42C600C0UL))\r
+#define bFM3_CAN1_BTR_BRP1                     *((volatile unsigned int*)(0x42C600C4UL))\r
+#define bFM3_CAN1_BTR_BRP2                     *((volatile unsigned int*)(0x42C600C8UL))\r
+#define bFM3_CAN1_BTR_BRP3                     *((volatile unsigned int*)(0x42C600CCUL))\r
+#define bFM3_CAN1_BTR_BRP4                     *((volatile unsigned int*)(0x42C600D0UL))\r
+#define bFM3_CAN1_BTR_BRP5                     *((volatile unsigned int*)(0x42C600D4UL))\r
+#define bFM3_CAN1_BTR_SJW0                     *((volatile unsigned int*)(0x42C600D8UL))\r
+#define bFM3_CAN1_BTR_SJW1                     *((volatile unsigned int*)(0x42C600DCUL))\r
+#define bFM3_CAN1_BTR_TSEG10                   *((volatile unsigned int*)(0x42C600E0UL))\r
+#define bFM3_CAN1_BTR_TSEG11                   *((volatile unsigned int*)(0x42C600E4UL))\r
+#define bFM3_CAN1_BTR_TSEG12                   *((volatile unsigned int*)(0x42C600E8UL))\r
+#define bFM3_CAN1_BTR_TSEG13                   *((volatile unsigned int*)(0x42C600ECUL))\r
+#define bFM3_CAN1_BTR_TSEG20                   *((volatile unsigned int*)(0x42C600F0UL))\r
+#define bFM3_CAN1_BTR_TSEG21                   *((volatile unsigned int*)(0x42C600F4UL))\r
+#define bFM3_CAN1_BTR_TSEG22                   *((volatile unsigned int*)(0x42C600F8UL))\r
+#define bFM3_CAN1_INTR_INTID0                  *((volatile unsigned int*)(0x42C60100UL))\r
+#define bFM3_CAN1_INTR_INTID1                  *((volatile unsigned int*)(0x42C60104UL))\r
+#define bFM3_CAN1_INTR_INTID2                  *((volatile unsigned int*)(0x42C60108UL))\r
+#define bFM3_CAN1_INTR_INTID3                  *((volatile unsigned int*)(0x42C6010CUL))\r
+#define bFM3_CAN1_INTR_INTID4                  *((volatile unsigned int*)(0x42C60110UL))\r
+#define bFM3_CAN1_INTR_INTID5                  *((volatile unsigned int*)(0x42C60114UL))\r
+#define bFM3_CAN1_INTR_INTID6                  *((volatile unsigned int*)(0x42C60118UL))\r
+#define bFM3_CAN1_INTR_INTID7                  *((volatile unsigned int*)(0x42C6011CUL))\r
+#define bFM3_CAN1_INTR_INTID8                  *((volatile unsigned int*)(0x42C60120UL))\r
+#define bFM3_CAN1_INTR_INTID9                  *((volatile unsigned int*)(0x42C60124UL))\r
+#define bFM3_CAN1_INTR_INTID10                 *((volatile unsigned int*)(0x42C60128UL))\r
+#define bFM3_CAN1_INTR_INTID11                 *((volatile unsigned int*)(0x42C6012CUL))\r
+#define bFM3_CAN1_INTR_INTID12                 *((volatile unsigned int*)(0x42C60130UL))\r
+#define bFM3_CAN1_INTR_INTID13                 *((volatile unsigned int*)(0x42C60134UL))\r
+#define bFM3_CAN1_INTR_INTID14                 *((volatile unsigned int*)(0x42C60138UL))\r
+#define bFM3_CAN1_INTR_INTID15                 *((volatile unsigned int*)(0x42C6013CUL))\r
+#define bFM3_CAN1_TESTR_BASIC                  *((volatile unsigned int*)(0x42C60148UL))\r
+#define bFM3_CAN1_TESTR_SILENT                 *((volatile unsigned int*)(0x42C6014CUL))\r
+#define bFM3_CAN1_TESTR_LBACK                  *((volatile unsigned int*)(0x42C60150UL))\r
+#define bFM3_CAN1_TESTR_TX0                    *((volatile unsigned int*)(0x42C60154UL))\r
+#define bFM3_CAN1_TESTR_TX1                    *((volatile unsigned int*)(0x42C60158UL))\r
+#define bFM3_CAN1_TESTR_RX                     *((volatile unsigned int*)(0x42C6015CUL))\r
+#define bFM3_CAN1_BRPER_BRPE0                  *((volatile unsigned int*)(0x42C60180UL))\r
+#define bFM3_CAN1_BRPER_BRPE1                  *((volatile unsigned int*)(0x42C60184UL))\r
+#define bFM3_CAN1_BRPER_BRPE2                  *((volatile unsigned int*)(0x42C60188UL))\r
+#define bFM3_CAN1_BRPER_BRPE3                  *((volatile unsigned int*)(0x42C6018CUL))\r
+#define bFM3_CAN1_IF1CREQ_BUSY                 *((volatile unsigned int*)(0x42C6023CUL))\r
+#define bFM3_CAN1_IF1CMSK_DATAB                *((volatile unsigned int*)(0x42C60240UL))\r
+#define bFM3_CAN1_IF1CMSK_DATAA                *((volatile unsigned int*)(0x42C60244UL))\r
+#define bFM3_CAN1_IF1CMSK_TXREST               *((volatile unsigned int*)(0x42C60248UL))\r
+#define bFM3_CAN1_IF1CMSK_NEWDAT               *((volatile unsigned int*)(0x42C60248UL))\r
+#define bFM3_CAN1_IF1CMSK_CIP                  *((volatile unsigned int*)(0x42C6024CUL))\r
+#define bFM3_CAN1_IF1CMSK_CONTROL              *((volatile unsigned int*)(0x42C60250UL))\r
+#define bFM3_CAN1_IF1CMSK_ARB                  *((volatile unsigned int*)(0x42C60254UL))\r
+#define bFM3_CAN1_IF1CMSK_MASK                 *((volatile unsigned int*)(0x42C60258UL))\r
+#define bFM3_CAN1_IF1CMSK_WRRD                 *((volatile unsigned int*)(0x42C6025CUL))\r
+#define bFM3_CAN1_IF1MSK_MDIR                  *((volatile unsigned int*)(0x42C602F8UL))\r
+#define bFM3_CAN1_IF1MSK_MXTD                  *((volatile unsigned int*)(0x42C602FCUL))\r
+#define bFM3_CAN1_IF1MSK2_MDIR                 *((volatile unsigned int*)(0x42C602F8UL))\r
+#define bFM3_CAN1_IF1MSK2_MXTD                 *((volatile unsigned int*)(0x42C602FCUL))\r
+#define bFM3_CAN1_IF1ARB_DIR                   *((volatile unsigned int*)(0x42C60374UL))\r
+#define bFM3_CAN1_IF1ARB_XTD                   *((volatile unsigned int*)(0x42C60378UL))\r
+#define bFM3_CAN1_IF1ARB_MSGVAL                *((volatile unsigned int*)(0x42C6037CUL))\r
+#define bFM3_CAN1_IF1ARB2_DIR                  *((volatile unsigned int*)(0x42C60374UL))\r
+#define bFM3_CAN1_IF1ARB2_XTD                  *((volatile unsigned int*)(0x42C60378UL))\r
+#define bFM3_CAN1_IF1ARB2_MSGVAL               *((volatile unsigned int*)(0x42C6037CUL))\r
+#define bFM3_CAN1_IF1MCTR_DLC0                 *((volatile unsigned int*)(0x42C60380UL))\r
+#define bFM3_CAN1_IF1MCTR_DLC1                 *((volatile unsigned int*)(0x42C60384UL))\r
+#define bFM3_CAN1_IF1MCTR_DLC2                 *((volatile unsigned int*)(0x42C60388UL))\r
+#define bFM3_CAN1_IF1MCTR_DLC3                 *((volatile unsigned int*)(0x42C6038CUL))\r
+#define bFM3_CAN1_IF1MCTR_EOB                  *((volatile unsigned int*)(0x42C6039CUL))\r
+#define bFM3_CAN1_IF1MCTR_TXRQST               *((volatile unsigned int*)(0x42C603A0UL))\r
+#define bFM3_CAN1_IF1MCTR_RMTEN                *((volatile unsigned int*)(0x42C603A4UL))\r
+#define bFM3_CAN1_IF1MCTR_RXIE                 *((volatile unsigned int*)(0x42C603A8UL))\r
+#define bFM3_CAN1_IF1MCTR_TXIE                 *((volatile unsigned int*)(0x42C603ACUL))\r
+#define bFM3_CAN1_IF1MCTR_UMASK                *((volatile unsigned int*)(0x42C603B0UL))\r
+#define bFM3_CAN1_IF1MCTR_INTPND               *((volatile unsigned int*)(0x42C603B4UL))\r
+#define bFM3_CAN1_IF1MCTR_MSGLST               *((volatile unsigned int*)(0x42C603B8UL))\r
+#define bFM3_CAN1_IF1MCTR_NEWDAT               *((volatile unsigned int*)(0x42C603BCUL))\r
+#define bFM3_CAN1_IF2CREQ_BUSY                 *((volatile unsigned int*)(0x42C6083CUL))\r
+#define bFM3_CAN1_IF2CMSK_DATAB                *((volatile unsigned int*)(0x42C60840UL))\r
+#define bFM3_CAN1_IF2CMSK_DATAA                *((volatile unsigned int*)(0x42C60844UL))\r
+#define bFM3_CAN1_IF2CMSK_TXREST               *((volatile unsigned int*)(0x42C60848UL))\r
+#define bFM3_CAN1_IF2CMSK_NEWDAT               *((volatile unsigned int*)(0x42C60848UL))\r
+#define bFM3_CAN1_IF2CMSK_CIP                  *((volatile unsigned int*)(0x42C6084CUL))\r
+#define bFM3_CAN1_IF2CMSK_CONTROL              *((volatile unsigned int*)(0x42C60850UL))\r
+#define bFM3_CAN1_IF2CMSK_ARB                  *((volatile unsigned int*)(0x42C60854UL))\r
+#define bFM3_CAN1_IF2CMSK_MASK                 *((volatile unsigned int*)(0x42C60858UL))\r
+#define bFM3_CAN1_IF2CMSK_WRRD                 *((volatile unsigned int*)(0x42C6085CUL))\r
+#define bFM3_CAN1_IF2MSK_MDIR                  *((volatile unsigned int*)(0x42C608F8UL))\r
+#define bFM3_CAN1_IF2MSK_MXTD                  *((volatile unsigned int*)(0x42C608FCUL))\r
+#define bFM3_CAN1_IF2MSK2_MDIR                 *((volatile unsigned int*)(0x42C608F8UL))\r
+#define bFM3_CAN1_IF2MSK2_MXTD                 *((volatile unsigned int*)(0x42C608FCUL))\r
+#define bFM3_CAN1_IF2ARB_DIR                   *((volatile unsigned int*)(0x42C60974UL))\r
+#define bFM3_CAN1_IF2ARB_XTD                   *((volatile unsigned int*)(0x42C60978UL))\r
+#define bFM3_CAN1_IF2ARB_MSGVAL                *((volatile unsigned int*)(0x42C6097CUL))\r
+#define bFM3_CAN1_IF2ARB2_DIR                  *((volatile unsigned int*)(0x42C60974UL))\r
+#define bFM3_CAN1_IF2ARB2_XTD                  *((volatile unsigned int*)(0x42C60978UL))\r
+#define bFM3_CAN1_IF2ARB2_MSGVAL               *((volatile unsigned int*)(0x42C6097CUL))\r
+#define bFM3_CAN1_IF2MCTR_DLC0                 *((volatile unsigned int*)(0x42C60980UL))\r
+#define bFM3_CAN1_IF2MCTR_DLC1                 *((volatile unsigned int*)(0x42C60984UL))\r
+#define bFM3_CAN1_IF2MCTR_DLC2                 *((volatile unsigned int*)(0x42C60988UL))\r
+#define bFM3_CAN1_IF2MCTR_DLC3                 *((volatile unsigned int*)(0x42C6098CUL))\r
+#define bFM3_CAN1_IF2MCTR_EOB                  *((volatile unsigned int*)(0x42C6099CUL))\r
+#define bFM3_CAN1_IF2MCTR_TXRQST               *((volatile unsigned int*)(0x42C609A0UL))\r
+#define bFM3_CAN1_IF2MCTR_RMTEN                *((volatile unsigned int*)(0x42C609A4UL))\r
+#define bFM3_CAN1_IF2MCTR_RXIE                 *((volatile unsigned int*)(0x42C609A8UL))\r
+#define bFM3_CAN1_IF2MCTR_TXIE                 *((volatile unsigned int*)(0x42C609ACUL))\r
+#define bFM3_CAN1_IF2MCTR_UMASK                *((volatile unsigned int*)(0x42C609B0UL))\r
+#define bFM3_CAN1_IF2MCTR_INTPND               *((volatile unsigned int*)(0x42C609B4UL))\r
+#define bFM3_CAN1_IF2MCTR_MSGLST               *((volatile unsigned int*)(0x42C609B8UL))\r
+#define bFM3_CAN1_IF2MCTR_NEWDAT               *((volatile unsigned int*)(0x42C609BCUL))\r
+#define bFM3_CAN1_TREQR_TXRQST1                *((volatile unsigned int*)(0x42C61000UL))\r
+#define bFM3_CAN1_TREQR_TXRQST2                *((volatile unsigned int*)(0x42C61004UL))\r
+#define bFM3_CAN1_TREQR_TXRQST3                *((volatile unsigned int*)(0x42C61008UL))\r
+#define bFM3_CAN1_TREQR_TXRQST4                *((volatile unsigned int*)(0x42C6100CUL))\r
+#define bFM3_CAN1_TREQR_TXRQST5                *((volatile unsigned int*)(0x42C61010UL))\r
+#define bFM3_CAN1_TREQR_TXRQST6                *((volatile unsigned int*)(0x42C61014UL))\r
+#define bFM3_CAN1_TREQR_TXRQST7                *((volatile unsigned int*)(0x42C61018UL))\r
+#define bFM3_CAN1_TREQR_TXRQST8                *((volatile unsigned int*)(0x42C6101CUL))\r
+#define bFM3_CAN1_TREQR_TXRQST9                *((volatile unsigned int*)(0x42C61020UL))\r
+#define bFM3_CAN1_TREQR_TXRQST10               *((volatile unsigned int*)(0x42C61024UL))\r
+#define bFM3_CAN1_TREQR_TXRQST11               *((volatile unsigned int*)(0x42C61028UL))\r
+#define bFM3_CAN1_TREQR_TXRQST12               *((volatile unsigned int*)(0x42C6102CUL))\r
+#define bFM3_CAN1_TREQR_TXRQST13               *((volatile unsigned int*)(0x42C61030UL))\r
+#define bFM3_CAN1_TREQR_TXRQST14               *((volatile unsigned int*)(0x42C61034UL))\r
+#define bFM3_CAN1_TREQR_TXRQST15               *((volatile unsigned int*)(0x42C61038UL))\r
+#define bFM3_CAN1_TREQR_TXRQST16               *((volatile unsigned int*)(0x42C6103CUL))\r
+#define bFM3_CAN1_TREQR_TXRQST17               *((volatile unsigned int*)(0x42C61040UL))\r
+#define bFM3_CAN1_TREQR_TXRQST18               *((volatile unsigned int*)(0x42C61044UL))\r
+#define bFM3_CAN1_TREQR_TXRQST19               *((volatile unsigned int*)(0x42C61048UL))\r
+#define bFM3_CAN1_TREQR_TXRQST20               *((volatile unsigned int*)(0x42C6104CUL))\r
+#define bFM3_CAN1_TREQR_TXRQST21               *((volatile unsigned int*)(0x42C61050UL))\r
+#define bFM3_CAN1_TREQR_TXRQST22               *((volatile unsigned int*)(0x42C61054UL))\r
+#define bFM3_CAN1_TREQR_TXRQST23               *((volatile unsigned int*)(0x42C61058UL))\r
+#define bFM3_CAN1_TREQR_TXRQST24               *((volatile unsigned int*)(0x42C6105CUL))\r
+#define bFM3_CAN1_TREQR_TXRQST25               *((volatile unsigned int*)(0x42C61060UL))\r
+#define bFM3_CAN1_TREQR_TXRQST26               *((volatile unsigned int*)(0x42C61064UL))\r
+#define bFM3_CAN1_TREQR_TXRQST27               *((volatile unsigned int*)(0x42C61068UL))\r
+#define bFM3_CAN1_TREQR_TXRQST28               *((volatile unsigned int*)(0x42C6106CUL))\r
+#define bFM3_CAN1_TREQR_TXRQST29               *((volatile unsigned int*)(0x42C61070UL))\r
+#define bFM3_CAN1_TREQR_TXRQST30               *((volatile unsigned int*)(0x42C61074UL))\r
+#define bFM3_CAN1_TREQR_TXRQST31               *((volatile unsigned int*)(0x42C61078UL))\r
+#define bFM3_CAN1_TREQR_TXRQST32               *((volatile unsigned int*)(0x42C6107CUL))\r
+#define bFM3_CAN1_TREQR1_TXRQST1               *((volatile unsigned int*)(0x42C61000UL))\r
+#define bFM3_CAN1_TREQR1_TXRQST2               *((volatile unsigned int*)(0x42C61004UL))\r
+#define bFM3_CAN1_TREQR1_TXRQST3               *((volatile unsigned int*)(0x42C61008UL))\r
+#define bFM3_CAN1_TREQR1_TXRQST4               *((volatile unsigned int*)(0x42C6100CUL))\r
+#define bFM3_CAN1_TREQR1_TXRQST5               *((volatile unsigned int*)(0x42C61010UL))\r
+#define bFM3_CAN1_TREQR1_TXRQST6               *((volatile unsigned int*)(0x42C61014UL))\r
+#define bFM3_CAN1_TREQR1_TXRQST7               *((volatile unsigned int*)(0x42C61018UL))\r
+#define bFM3_CAN1_TREQR1_TXRQST8               *((volatile unsigned int*)(0x42C6101CUL))\r
+#define bFM3_CAN1_TREQR1_TXRQST9               *((volatile unsigned int*)(0x42C61020UL))\r
+#define bFM3_CAN1_TREQR1_TXRQST10              *((volatile unsigned int*)(0x42C61024UL))\r
+#define bFM3_CAN1_TREQR1_TXRQST11              *((volatile unsigned int*)(0x42C61028UL))\r
+#define bFM3_CAN1_TREQR1_TXRQST12              *((volatile unsigned int*)(0x42C6102CUL))\r
+#define bFM3_CAN1_TREQR1_TXRQST13              *((volatile unsigned int*)(0x42C61030UL))\r
+#define bFM3_CAN1_TREQR1_TXRQST14              *((volatile unsigned int*)(0x42C61034UL))\r
+#define bFM3_CAN1_TREQR1_TXRQST15              *((volatile unsigned int*)(0x42C61038UL))\r
+#define bFM3_CAN1_TREQR1_TXRQST16              *((volatile unsigned int*)(0x42C6103CUL))\r
+#define bFM3_CAN1_TREQR2_TXRQST17              *((volatile unsigned int*)(0x42C61040UL))\r
+#define bFM3_CAN1_TREQR2_TXRQST18              *((volatile unsigned int*)(0x42C61044UL))\r
+#define bFM3_CAN1_TREQR2_TXRQST19              *((volatile unsigned int*)(0x42C61048UL))\r
+#define bFM3_CAN1_TREQR2_TXRQST20              *((volatile unsigned int*)(0x42C6104CUL))\r
+#define bFM3_CAN1_TREQR2_TXRQST21              *((volatile unsigned int*)(0x42C61050UL))\r
+#define bFM3_CAN1_TREQR2_TXRQST22              *((volatile unsigned int*)(0x42C61054UL))\r
+#define bFM3_CAN1_TREQR2_TXRQST23              *((volatile unsigned int*)(0x42C61058UL))\r
+#define bFM3_CAN1_TREQR2_TXRQST24              *((volatile unsigned int*)(0x42C6105CUL))\r
+#define bFM3_CAN1_TREQR2_TXRQST25              *((volatile unsigned int*)(0x42C61060UL))\r
+#define bFM3_CAN1_TREQR2_TXRQST26              *((volatile unsigned int*)(0x42C61064UL))\r
+#define bFM3_CAN1_TREQR2_TXRQST27              *((volatile unsigned int*)(0x42C61068UL))\r
+#define bFM3_CAN1_TREQR2_TXRQST28              *((volatile unsigned int*)(0x42C6106CUL))\r
+#define bFM3_CAN1_TREQR2_TXRQST29              *((volatile unsigned int*)(0x42C61070UL))\r
+#define bFM3_CAN1_TREQR2_TXRQST30              *((volatile unsigned int*)(0x42C61074UL))\r
+#define bFM3_CAN1_TREQR2_TXRQST31              *((volatile unsigned int*)(0x42C61078UL))\r
+#define bFM3_CAN1_TREQR2_TXRQST32              *((volatile unsigned int*)(0x42C6107CUL))\r
+#define bFM3_CAN1_NEWDT_NEWDAT1                *((volatile unsigned int*)(0x42C61200UL))\r
+#define bFM3_CAN1_NEWDT_NEWDAT2                *((volatile unsigned int*)(0x42C61204UL))\r
+#define bFM3_CAN1_NEWDT_NEWDAT3                *((volatile unsigned int*)(0x42C61208UL))\r
+#define bFM3_CAN1_NEWDT_NEWDAT4                *((volatile unsigned int*)(0x42C6120CUL))\r
+#define bFM3_CAN1_NEWDT_NEWDAT5                *((volatile unsigned int*)(0x42C61210UL))\r
+#define bFM3_CAN1_NEWDT_NEWDAT6                *((volatile unsigned int*)(0x42C61214UL))\r
+#define bFM3_CAN1_NEWDT_NEWDAT7                *((volatile unsigned int*)(0x42C61218UL))\r
+#define bFM3_CAN1_NEWDT_NEWDAT8                *((volatile unsigned int*)(0x42C6121CUL))\r
+#define bFM3_CAN1_NEWDT_NEWDAT9                *((volatile unsigned int*)(0x42C61220UL))\r
+#define bFM3_CAN1_NEWDT_NEWDAT10               *((volatile unsigned int*)(0x42C61224UL))\r
+#define bFM3_CAN1_NEWDT_NEWDAT11               *((volatile unsigned int*)(0x42C61228UL))\r
+#define bFM3_CAN1_NEWDT_NEWDAT12               *((volatile unsigned int*)(0x42C6122CUL))\r
+#define bFM3_CAN1_NEWDT_NEWDAT13               *((volatile unsigned int*)(0x42C61230UL))\r
+#define bFM3_CAN1_NEWDT_NEWDAT14               *((volatile unsigned int*)(0x42C61234UL))\r
+#define bFM3_CAN1_NEWDT_NEWDAT15               *((volatile unsigned int*)(0x42C61238UL))\r
+#define bFM3_CAN1_NEWDT_NEWDAT16               *((volatile unsigned int*)(0x42C6123CUL))\r
+#define bFM3_CAN1_NEWDT_NEWDAT17               *((volatile unsigned int*)(0x42C61240UL))\r
+#define bFM3_CAN1_NEWDT_NEWDAT18               *((volatile unsigned int*)(0x42C61244UL))\r
+#define bFM3_CAN1_NEWDT_NEWDAT19               *((volatile unsigned int*)(0x42C61248UL))\r
+#define bFM3_CAN1_NEWDT_NEWDAT20               *((volatile unsigned int*)(0x42C6124CUL))\r
+#define bFM3_CAN1_NEWDT_NEWDAT21               *((volatile unsigned int*)(0x42C61250UL))\r
+#define bFM3_CAN1_NEWDT_NEWDAT22               *((volatile unsigned int*)(0x42C61254UL))\r
+#define bFM3_CAN1_NEWDT_NEWDAT23               *((volatile unsigned int*)(0x42C61258UL))\r
+#define bFM3_CAN1_NEWDT_NEWDAT24               *((volatile unsigned int*)(0x42C6125CUL))\r
+#define bFM3_CAN1_NEWDT_NEWDAT25               *((volatile unsigned int*)(0x42C61260UL))\r
+#define bFM3_CAN1_NEWDT_NEWDAT26               *((volatile unsigned int*)(0x42C61264UL))\r
+#define bFM3_CAN1_NEWDT_NEWDAT27               *((volatile unsigned int*)(0x42C61268UL))\r
+#define bFM3_CAN1_NEWDT_NEWDAT28               *((volatile unsigned int*)(0x42C6126CUL))\r
+#define bFM3_CAN1_NEWDT_NEWDAT29               *((volatile unsigned int*)(0x42C61270UL))\r
+#define bFM3_CAN1_NEWDT_NEWDAT30               *((volatile unsigned int*)(0x42C61274UL))\r
+#define bFM3_CAN1_NEWDT_NEWDAT31               *((volatile unsigned int*)(0x42C61278UL))\r
+#define bFM3_CAN1_NEWDT_NEWDAT32               *((volatile unsigned int*)(0x42C6127CUL))\r
+#define bFM3_CAN1_NEWDT1_NEWDAT1               *((volatile unsigned int*)(0x42C61200UL))\r
+#define bFM3_CAN1_NEWDT1_NEWDAT2               *((volatile unsigned int*)(0x42C61204UL))\r
+#define bFM3_CAN1_NEWDT1_NEWDAT3               *((volatile unsigned int*)(0x42C61208UL))\r
+#define bFM3_CAN1_NEWDT1_NEWDAT4               *((volatile unsigned int*)(0x42C6120CUL))\r
+#define bFM3_CAN1_NEWDT1_NEWDAT5               *((volatile unsigned int*)(0x42C61210UL))\r
+#define bFM3_CAN1_NEWDT1_NEWDAT6               *((volatile unsigned int*)(0x42C61214UL))\r
+#define bFM3_CAN1_NEWDT1_NEWDAT7               *((volatile unsigned int*)(0x42C61218UL))\r
+#define bFM3_CAN1_NEWDT1_NEWDAT8               *((volatile unsigned int*)(0x42C6121CUL))\r
+#define bFM3_CAN1_NEWDT1_NEWDAT9               *((volatile unsigned int*)(0x42C61220UL))\r
+#define bFM3_CAN1_NEWDT1_NEWDAT10              *((volatile unsigned int*)(0x42C61224UL))\r
+#define bFM3_CAN1_NEWDT1_NEWDAT11              *((volatile unsigned int*)(0x42C61228UL))\r
+#define bFM3_CAN1_NEWDT1_NEWDAT12              *((volatile unsigned int*)(0x42C6122CUL))\r
+#define bFM3_CAN1_NEWDT1_NEWDAT13              *((volatile unsigned int*)(0x42C61230UL))\r
+#define bFM3_CAN1_NEWDT1_NEWDAT14              *((volatile unsigned int*)(0x42C61234UL))\r
+#define bFM3_CAN1_NEWDT1_NEWDAT15              *((volatile unsigned int*)(0x42C61238UL))\r
+#define bFM3_CAN1_NEWDT1_NEWDAT16              *((volatile unsigned int*)(0x42C6123CUL))\r
+#define bFM3_CAN1_NEWDT2_NEWDAT17              *((volatile unsigned int*)(0x42C61240UL))\r
+#define bFM3_CAN1_NEWDT2_NEWDAT18              *((volatile unsigned int*)(0x42C61244UL))\r
+#define bFM3_CAN1_NEWDT2_NEWDAT19              *((volatile unsigned int*)(0x42C61248UL))\r
+#define bFM3_CAN1_NEWDT2_NEWDAT20              *((volatile unsigned int*)(0x42C6124CUL))\r
+#define bFM3_CAN1_NEWDT2_NEWDAT21              *((volatile unsigned int*)(0x42C61250UL))\r
+#define bFM3_CAN1_NEWDT2_NEWDAT22              *((volatile unsigned int*)(0x42C61254UL))\r
+#define bFM3_CAN1_NEWDT2_NEWDAT23              *((volatile unsigned int*)(0x42C61258UL))\r
+#define bFM3_CAN1_NEWDT2_NEWDAT24              *((volatile unsigned int*)(0x42C6125CUL))\r
+#define bFM3_CAN1_NEWDT2_NEWDAT25              *((volatile unsigned int*)(0x42C61260UL))\r
+#define bFM3_CAN1_NEWDT2_NEWDAT26              *((volatile unsigned int*)(0x42C61264UL))\r
+#define bFM3_CAN1_NEWDT2_NEWDAT27              *((volatile unsigned int*)(0x42C61268UL))\r
+#define bFM3_CAN1_NEWDT2_NEWDAT28              *((volatile unsigned int*)(0x42C6126CUL))\r
+#define bFM3_CAN1_NEWDT2_NEWDAT29              *((volatile unsigned int*)(0x42C61270UL))\r
+#define bFM3_CAN1_NEWDT2_NEWDAT30              *((volatile unsigned int*)(0x42C61274UL))\r
+#define bFM3_CAN1_NEWDT2_NEWDAT31              *((volatile unsigned int*)(0x42C61278UL))\r
+#define bFM3_CAN1_NEWDT2_NEWDAT32              *((volatile unsigned int*)(0x42C6127CUL))\r
+#define bFM3_CAN1_INTPND_INTPND1               *((volatile unsigned int*)(0x42C61400UL))\r
+#define bFM3_CAN1_INTPND_INTPND2               *((volatile unsigned int*)(0x42C61404UL))\r
+#define bFM3_CAN1_INTPND_INTPND3               *((volatile unsigned int*)(0x42C61408UL))\r
+#define bFM3_CAN1_INTPND_INTPND4               *((volatile unsigned int*)(0x42C6140CUL))\r
+#define bFM3_CAN1_INTPND_INTPND5               *((volatile unsigned int*)(0x42C61410UL))\r
+#define bFM3_CAN1_INTPND_INTPND6               *((volatile unsigned int*)(0x42C61414UL))\r
+#define bFM3_CAN1_INTPND_INTPND7               *((volatile unsigned int*)(0x42C61418UL))\r
+#define bFM3_CAN1_INTPND_INTPND8               *((volatile unsigned int*)(0x42C6141CUL))\r
+#define bFM3_CAN1_INTPND_INTPND9               *((volatile unsigned int*)(0x42C61420UL))\r
+#define bFM3_CAN1_INTPND_INTPND10              *((volatile unsigned int*)(0x42C61424UL))\r
+#define bFM3_CAN1_INTPND_INTPND11              *((volatile unsigned int*)(0x42C61428UL))\r
+#define bFM3_CAN1_INTPND_INTPND12              *((volatile unsigned int*)(0x42C6142CUL))\r
+#define bFM3_CAN1_INTPND_INTPND13              *((volatile unsigned int*)(0x42C61430UL))\r
+#define bFM3_CAN1_INTPND_INTPND14              *((volatile unsigned int*)(0x42C61434UL))\r
+#define bFM3_CAN1_INTPND_INTPND15              *((volatile unsigned int*)(0x42C61438UL))\r
+#define bFM3_CAN1_INTPND_INTPND16              *((volatile unsigned int*)(0x42C6143CUL))\r
+#define bFM3_CAN1_INTPND_INTPND17              *((volatile unsigned int*)(0x42C61440UL))\r
+#define bFM3_CAN1_INTPND_INTPND18              *((volatile unsigned int*)(0x42C61444UL))\r
+#define bFM3_CAN1_INTPND_INTPND19              *((volatile unsigned int*)(0x42C61448UL))\r
+#define bFM3_CAN1_INTPND_INTPND20              *((volatile unsigned int*)(0x42C6144CUL))\r
+#define bFM3_CAN1_INTPND_INTPND21              *((volatile unsigned int*)(0x42C61450UL))\r
+#define bFM3_CAN1_INTPND_INTPND22              *((volatile unsigned int*)(0x42C61454UL))\r
+#define bFM3_CAN1_INTPND_INTPND23              *((volatile unsigned int*)(0x42C61458UL))\r
+#define bFM3_CAN1_INTPND_INTPND24              *((volatile unsigned int*)(0x42C6145CUL))\r
+#define bFM3_CAN1_INTPND_INTPND25              *((volatile unsigned int*)(0x42C61460UL))\r
+#define bFM3_CAN1_INTPND_INTPND26              *((volatile unsigned int*)(0x42C61464UL))\r
+#define bFM3_CAN1_INTPND_INTPND27              *((volatile unsigned int*)(0x42C61468UL))\r
+#define bFM3_CAN1_INTPND_INTPND28              *((volatile unsigned int*)(0x42C6146CUL))\r
+#define bFM3_CAN1_INTPND_INTPND29              *((volatile unsigned int*)(0x42C61470UL))\r
+#define bFM3_CAN1_INTPND_INTPND30              *((volatile unsigned int*)(0x42C61474UL))\r
+#define bFM3_CAN1_INTPND_INTPND31              *((volatile unsigned int*)(0x42C61478UL))\r
+#define bFM3_CAN1_INTPND_INTPND32              *((volatile unsigned int*)(0x42C6147CUL))\r
+#define bFM3_CAN1_INTPND1_INTPND1              *((volatile unsigned int*)(0x42C61400UL))\r
+#define bFM3_CAN1_INTPND1_INTPND2              *((volatile unsigned int*)(0x42C61404UL))\r
+#define bFM3_CAN1_INTPND1_INTPND3              *((volatile unsigned int*)(0x42C61408UL))\r
+#define bFM3_CAN1_INTPND1_INTPND4              *((volatile unsigned int*)(0x42C6140CUL))\r
+#define bFM3_CAN1_INTPND1_INTPND5              *((volatile unsigned int*)(0x42C61410UL))\r
+#define bFM3_CAN1_INTPND1_INTPND6              *((volatile unsigned int*)(0x42C61414UL))\r
+#define bFM3_CAN1_INTPND1_INTPND7              *((volatile unsigned int*)(0x42C61418UL))\r
+#define bFM3_CAN1_INTPND1_INTPND8              *((volatile unsigned int*)(0x42C6141CUL))\r
+#define bFM3_CAN1_INTPND1_INTPND9              *((volatile unsigned int*)(0x42C61420UL))\r
+#define bFM3_CAN1_INTPND1_INTPND10             *((volatile unsigned int*)(0x42C61424UL))\r
+#define bFM3_CAN1_INTPND1_INTPND11             *((volatile unsigned int*)(0x42C61428UL))\r
+#define bFM3_CAN1_INTPND1_INTPND12             *((volatile unsigned int*)(0x42C6142CUL))\r
+#define bFM3_CAN1_INTPND1_INTPND13             *((volatile unsigned int*)(0x42C61430UL))\r
+#define bFM3_CAN1_INTPND1_INTPND14             *((volatile unsigned int*)(0x42C61434UL))\r
+#define bFM3_CAN1_INTPND1_INTPND15             *((volatile unsigned int*)(0x42C61438UL))\r
+#define bFM3_CAN1_INTPND1_INTPND16             *((volatile unsigned int*)(0x42C6143CUL))\r
+#define bFM3_CAN1_INTPND2_INTPND17             *((volatile unsigned int*)(0x42C61440UL))\r
+#define bFM3_CAN1_INTPND2_INTPND18             *((volatile unsigned int*)(0x42C61444UL))\r
+#define bFM3_CAN1_INTPND2_INTPND19             *((volatile unsigned int*)(0x42C61448UL))\r
+#define bFM3_CAN1_INTPND2_INTPND20             *((volatile unsigned int*)(0x42C6144CUL))\r
+#define bFM3_CAN1_INTPND2_INTPND21             *((volatile unsigned int*)(0x42C61450UL))\r
+#define bFM3_CAN1_INTPND2_INTPND22             *((volatile unsigned int*)(0x42C61454UL))\r
+#define bFM3_CAN1_INTPND2_INTPND23             *((volatile unsigned int*)(0x42C61458UL))\r
+#define bFM3_CAN1_INTPND2_INTPND24             *((volatile unsigned int*)(0x42C6145CUL))\r
+#define bFM3_CAN1_INTPND2_INTPND25             *((volatile unsigned int*)(0x42C61460UL))\r
+#define bFM3_CAN1_INTPND2_INTPND26             *((volatile unsigned int*)(0x42C61464UL))\r
+#define bFM3_CAN1_INTPND2_INTPND27             *((volatile unsigned int*)(0x42C61468UL))\r
+#define bFM3_CAN1_INTPND2_INTPND28             *((volatile unsigned int*)(0x42C6146CUL))\r
+#define bFM3_CAN1_INTPND2_INTPND29             *((volatile unsigned int*)(0x42C61470UL))\r
+#define bFM3_CAN1_INTPND2_INTPND30             *((volatile unsigned int*)(0x42C61474UL))\r
+#define bFM3_CAN1_INTPND2_INTPND31             *((volatile unsigned int*)(0x42C61478UL))\r
+#define bFM3_CAN1_INTPND2_INTPND32             *((volatile unsigned int*)(0x42C6147CUL))\r
+#define bFM3_CAN1_MSGVAL_MSGVAL1               *((volatile unsigned int*)(0x42C61600UL))\r
+#define bFM3_CAN1_MSGVAL_MSGVAL2               *((volatile unsigned int*)(0x42C61604UL))\r
+#define bFM3_CAN1_MSGVAL_MSGVAL3               *((volatile unsigned int*)(0x42C61608UL))\r
+#define bFM3_CAN1_MSGVAL_MSGVAL4               *((volatile unsigned int*)(0x42C6160CUL))\r
+#define bFM3_CAN1_MSGVAL_MSGVAL5               *((volatile unsigned int*)(0x42C61610UL))\r
+#define bFM3_CAN1_MSGVAL_MSGVAL6               *((volatile unsigned int*)(0x42C61614UL))\r
+#define bFM3_CAN1_MSGVAL_MSGVAL7               *((volatile unsigned int*)(0x42C61618UL))\r
+#define bFM3_CAN1_MSGVAL_MSGVAL8               *((volatile unsigned int*)(0x42C6161CUL))\r
+#define bFM3_CAN1_MSGVAL_MSGVAL9               *((volatile unsigned int*)(0x42C61620UL))\r
+#define bFM3_CAN1_MSGVAL_MSGVAL10              *((volatile unsigned int*)(0x42C61624UL))\r
+#define bFM3_CAN1_MSGVAL_MSGVAL11              *((volatile unsigned int*)(0x42C61628UL))\r
+#define bFM3_CAN1_MSGVAL_MSGVAL12              *((volatile unsigned int*)(0x42C6162CUL))\r
+#define bFM3_CAN1_MSGVAL_MSGVAL13              *((volatile unsigned int*)(0x42C61630UL))\r
+#define bFM3_CAN1_MSGVAL_MSGVAL14              *((volatile unsigned int*)(0x42C61634UL))\r
+#define bFM3_CAN1_MSGVAL_MSGVAL15              *((volatile unsigned int*)(0x42C61638UL))\r
+#define bFM3_CAN1_MSGVAL_MSGVAL16              *((volatile unsigned int*)(0x42C6163CUL))\r
+#define bFM3_CAN1_MSGVAL_MSGVAL17              *((volatile unsigned int*)(0x42C61640UL))\r
+#define bFM3_CAN1_MSGVAL_MSGVAL18              *((volatile unsigned int*)(0x42C61644UL))\r
+#define bFM3_CAN1_MSGVAL_MSGVAL19              *((volatile unsigned int*)(0x42C61648UL))\r
+#define bFM3_CAN1_MSGVAL_MSGVAL20              *((volatile unsigned int*)(0x42C6164CUL))\r
+#define bFM3_CAN1_MSGVAL_MSGVAL21              *((volatile unsigned int*)(0x42C61650UL))\r
+#define bFM3_CAN1_MSGVAL_MSGVAL22              *((volatile unsigned int*)(0x42C61654UL))\r
+#define bFM3_CAN1_MSGVAL_MSGVAL23              *((volatile unsigned int*)(0x42C61658UL))\r
+#define bFM3_CAN1_MSGVAL_MSGVAL24              *((volatile unsigned int*)(0x42C6165CUL))\r
+#define bFM3_CAN1_MSGVAL_MSGVAL25              *((volatile unsigned int*)(0x42C61660UL))\r
+#define bFM3_CAN1_MSGVAL_MSGVAL26              *((volatile unsigned int*)(0x42C61664UL))\r
+#define bFM3_CAN1_MSGVAL_MSGVAL27              *((volatile unsigned int*)(0x42C61668UL))\r
+#define bFM3_CAN1_MSGVAL_MSGVAL28              *((volatile unsigned int*)(0x42C6166CUL))\r
+#define bFM3_CAN1_MSGVAL_MSGVAL29              *((volatile unsigned int*)(0x42C61670UL))\r
+#define bFM3_CAN1_MSGVAL_MSGVAL30              *((volatile unsigned int*)(0x42C61674UL))\r
+#define bFM3_CAN1_MSGVAL_MSGVAL31              *((volatile unsigned int*)(0x42C61678UL))\r
+#define bFM3_CAN1_MSGVAL_MSGVAL32              *((volatile unsigned int*)(0x42C6167CUL))\r
+#define bFM3_CAN1_MSGVAL1_MSGVAL1              *((volatile unsigned int*)(0x42C61600UL))\r
+#define bFM3_CAN1_MSGVAL1_MSGVAL2              *((volatile unsigned int*)(0x42C61604UL))\r
+#define bFM3_CAN1_MSGVAL1_MSGVAL3              *((volatile unsigned int*)(0x42C61608UL))\r
+#define bFM3_CAN1_MSGVAL1_MSGVAL4              *((volatile unsigned int*)(0x42C6160CUL))\r
+#define bFM3_CAN1_MSGVAL1_MSGVAL5              *((volatile unsigned int*)(0x42C61610UL))\r
+#define bFM3_CAN1_MSGVAL1_MSGVAL6              *((volatile unsigned int*)(0x42C61614UL))\r
+#define bFM3_CAN1_MSGVAL1_MSGVAL7              *((volatile unsigned int*)(0x42C61618UL))\r
+#define bFM3_CAN1_MSGVAL1_MSGVAL8              *((volatile unsigned int*)(0x42C6161CUL))\r
+#define bFM3_CAN1_MSGVAL1_MSGVAL9              *((volatile unsigned int*)(0x42C61620UL))\r
+#define bFM3_CAN1_MSGVAL1_MSGVAL10             *((volatile unsigned int*)(0x42C61624UL))\r
+#define bFM3_CAN1_MSGVAL1_MSGVAL11             *((volatile unsigned int*)(0x42C61628UL))\r
+#define bFM3_CAN1_MSGVAL1_MSGVAL12             *((volatile unsigned int*)(0x42C6162CUL))\r
+#define bFM3_CAN1_MSGVAL1_MSGVAL13             *((volatile unsigned int*)(0x42C61630UL))\r
+#define bFM3_CAN1_MSGVAL1_MSGVAL14             *((volatile unsigned int*)(0x42C61634UL))\r
+#define bFM3_CAN1_MSGVAL1_MSGVAL15             *((volatile unsigned int*)(0x42C61638UL))\r
+#define bFM3_CAN1_MSGVAL1_MSGVAL16             *((volatile unsigned int*)(0x42C6163CUL))\r
+#define bFM3_CAN1_MSGVAL2_MSGVAL17             *((volatile unsigned int*)(0x42C61640UL))\r
+#define bFM3_CAN1_MSGVAL2_MSGVAL18             *((volatile unsigned int*)(0x42C61644UL))\r
+#define bFM3_CAN1_MSGVAL2_MSGVAL19             *((volatile unsigned int*)(0x42C61648UL))\r
+#define bFM3_CAN1_MSGVAL2_MSGVAL20             *((volatile unsigned int*)(0x42C6164CUL))\r
+#define bFM3_CAN1_MSGVAL2_MSGVAL21             *((volatile unsigned int*)(0x42C61650UL))\r
+#define bFM3_CAN1_MSGVAL2_MSGVAL22             *((volatile unsigned int*)(0x42C61654UL))\r
+#define bFM3_CAN1_MSGVAL2_MSGVAL23             *((volatile unsigned int*)(0x42C61658UL))\r
+#define bFM3_CAN1_MSGVAL2_MSGVAL24             *((volatile unsigned int*)(0x42C6165CUL))\r
+#define bFM3_CAN1_MSGVAL2_MSGVAL25             *((volatile unsigned int*)(0x42C61660UL))\r
+#define bFM3_CAN1_MSGVAL2_MSGVAL26             *((volatile unsigned int*)(0x42C61664UL))\r
+#define bFM3_CAN1_MSGVAL2_MSGVAL27             *((volatile unsigned int*)(0x42C61668UL))\r
+#define bFM3_CAN1_MSGVAL2_MSGVAL28             *((volatile unsigned int*)(0x42C6166CUL))\r
+#define bFM3_CAN1_MSGVAL2_MSGVAL29             *((volatile unsigned int*)(0x42C61670UL))\r
+#define bFM3_CAN1_MSGVAL2_MSGVAL30             *((volatile unsigned int*)(0x42C61674UL))\r
+#define bFM3_CAN1_MSGVAL2_MSGVAL31             *((volatile unsigned int*)(0x42C61678UL))\r
+#define bFM3_CAN1_MSGVAL2_MSGVAL32             *((volatile unsigned int*)(0x42C6167CUL))\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* _MB9BF506N_H_ */\r
+\r

diff --git a/Demo/CORTEX_MB9B500_IAR_Keil/Fujitu_source/startup_iar/startup_mb9bf50x.s b/Demo/CORTEX_MB9B500_IAR_Keil/Fujitu_source/startup_iar/startup_mb9bf50x.s
new file mode 100644 (file)
index 0000000..ebbbff9
--- /dev/null
+++ b/Demo/CORTEX_MB9B500_IAR_Keil/Fujitu_source/startup_iar/startup_mb9bf50x.s
@@ -0,0 +1,402 @@
+;/************************************************************************/\r
+;/*               (C) Fujitsu Semiconductor Europe GmbH (FSEU)           */\r
+;/*                                                                      */\r
+;/* The following software deliverable is intended for and must only be  */\r
+;/* used for reference and in an evaluation laboratory environment.      */\r
+;/* It is provided on an as-is basis without charge and is subject to    */\r
+;/* alterations.                                                         */\r
+;/* It is the user's obligation to fully test the software in its        */\r
+;/* environment and to ensure proper functionality, qualification and    */\r
+;/* compliance with component specifications.                            */\r
+;/*                                                                      */\r
+;/* In the event the software deliverable includes the use of open       */\r
+;/* source components, the provisions of the governing open source       */\r
+;/* license agreement shall apply with respect to such software          */\r
+;/* deliverable.                                                         */\r
+;/* FSEU does not warrant that the deliverables do not infringe any      */\r
+;/* third party intellectual property right (IPR). In the event that     */\r
+;/* the deliverables infringe a third party IPR it is the sole           */\r
+;/* responsibility of the customer to obtain necessary licenses to       */\r
+;/* continue the usage of the deliverable.                               */\r
+;/*                                                                      */\r
+;/* To the maximum extent permitted by applicable law FSEU disclaims all */\r
+;/* warranties, whether express or implied, in particular, but not       */\r
+;/* limited to, warranties of merchantability and fitness for a          */\r
+;/* particular purpose for which the deliverable is not designated.      */\r
+;/*                                                                      */\r
+;/* To the maximum extent permitted by applicable law, FSEU's liability  */\r
+;/* is restricted to intentional misconduct and gross negligence.        */\r
+;/* FSEU is not liable for consequential damages.                        */\r
+;/*                                                                      */\r
+;/* (V1.5)                                                               */\r
+;/************************************************************************/\r
+;/*  Startup for IAR                                                     */\r
+;/*  Version     V1.02                                                   */\r
+;/*  Date        2011-01-05                                              */\r
+;/*  Target-mcu  MB9B5xx                                                 */\r
+;/************************************************************************/\r
+\r
+\r
+                MODULE  ?cstartup\r
+\r
+                ;; Forward declaration of sections.\r
+                SECTION CSTACK:DATA:NOROOT(3)\r
+\r
+                SECTION .intvec:CODE:NOROOT(2)\r
+\r
+                EXTERN  __iar_program_start\r
+                EXTERN  SystemInit\r
+                PUBLIC  __vector_table\r
+\r
+                DATA\r
+__vector_table  DCD     sfe(CSTACK)               ; Top of Stack\r
+                       DCD     Reset_Handler             ; Reset\r
+                DCD     NMI_Handler               ; NMI\r
+                DCD     HardFault_Handler         ; Hard Fault\r
+                DCD     MemManage_Handler         ; MPU Fault\r
+                DCD     BusFault_Handler          ; Bus Fault\r
+                DCD     UsageFault_Handler        ; Usage Fault\r
+                DCD     0                         ; Reserved\r
+                DCD     0                         ; Reserved\r
+                DCD     0                         ; Reserved\r
+                DCD     0                         ; Reserved\r
+                DCD     SVC_Handler               ; SVCall\r
+                DCD     DebugMon_Handler          ; Debug Monitor\r
+                DCD     0                         ; Reserved\r
+                DCD     PendSV_Handler            ; PendSV\r
+                DCD     SysTick_Handler           ; SysTick\r
+\r
+                DCD     CSV_Handler               ; 0: Clock Super Visor\r
+                DCD     SWDT_Handler              ; 1: Software Watchdog Timer\r
+                DCD     LVD_Handler               ; 2: Low Voltage Detector\r
+                DCD     MFT_WG_IRQHandler         ; 3: Wave Form Generator / DTIF\r
+                DCD     INT0_7_Handler            ; 4: External Interrupt Request ch.0 to ch.7\r
+                DCD     INT8_15_Handler           ; 5: External Interrupt Request ch.8 to ch.15\r
+                DCD     DT_Handler                ; 6: Dual Timer / Quad Decoder\r
+                DCD     MFS0RX_IRQHandler         ; 7: MultiFunction Serial ch.0\r
+                DCD     MFS0TX_IRQHandler         ; 8: MultiFunction Serial ch.0\r
+                DCD     MFS1RX_IRQHandler         ; 9: MultiFunction Serial ch.1\r
+                DCD     MFS1TX_IRQHandler         ; 10: MultiFunction Serial ch.1\r
+                DCD     MFS2RX_IRQHandler         ; 11: MultiFunction Serial ch.2\r
+                DCD     MFS2TX_IRQHandler         ; 12: MultiFunction Serial ch.2\r
+                DCD     MFS3RX_IRQHandler         ; 13: MultiFunction Serial ch.3\r
+                DCD     MFS3TX_IRQHandler         ; 14: MultiFunction Serial ch.3\r
+                DCD     MFS4RX_IRQHandler         ; 15: MultiFunction Serial ch.4\r
+                DCD     MFS4TX_IRQHandler         ; 16: MultiFunction Serial ch.4\r
+                DCD     MFS5RX_IRQHandler         ; 17: MultiFunction Serial ch.5\r
+                DCD     MFS5TX_IRQHandler         ; 18: MultiFunction Serial ch.5\r
+                DCD     MFS6RX_IRQHandler         ; 19: MultiFunction Serial ch.6\r
+                DCD     MFS6TX_IRQHandler         ; 20: MultiFunction Serial ch.6\r
+                DCD     MFS7RX_IRQHandler         ; 21: MultiFunction Serial ch.7\r
+                DCD     MFS7TX_IRQHandler         ; 22: MultiFunction Serial ch.7\r
+                DCD     PPG_Handler               ; 23: PPG\r
+                DCD     TIM_IRQHandler            ; 24: OSC / PLL / Watch Counter\r
+                DCD     ADC0_IRQHandler           ; 25: ADC0\r
+                DCD     ADC1_IRQHandler           ; 26: ADC1\r
+                DCD     ADC2_IRQHandler           ; 27: ADC2\r
+                DCD     MFT_FRT_IRQHandler        ; 28: Free-run Timer\r
+                DCD     MFT_IPC_IRQHandler        ; 29: Input Capture\r
+                DCD     MFT_OPC_IRQHandler        ; 30: Output Compare\r
+                DCD     BT_IRQHandler             ; 31: Base Timer ch.0 to ch.7\r
+                DCD     CAN0_IRQHandler           ; 32: CAN ch.0\r
+                DCD     CAN1_IRQHandler           ; 33: CAN ch.1\r
+                DCD     USBF_Handler              ; 34: USB Function\r
+                DCD     USB_Handler               ; 35: USB Function / USB HOST\r
+                DCD     DummyHandler              ; 36: Reserved\r
+                DCD     DummyHandler              ; 37: Reserved\r
+                DCD     DMAC0_Handler             ; 38: DMAC ch.0\r
+                DCD     DMAC1_Handler             ; 39: DMAC ch.1\r
+                DCD     DMAC2_Handler             ; 40: DMAC ch.2\r
+                DCD     DMAC3_Handler             ; 41: DMAC ch.3\r
+                DCD     DMAC4_Handler             ; 42: DMAC ch.4\r
+                DCD     DMAC5_Handler             ; 43: DMAC ch.5\r
+                DCD     DMAC6_Handler             ; 44: DMAC ch.6\r
+                DCD     DMAC7_Handler             ; 45: DMAC ch.7\r
+                DCD     DummyHandler              ; 46: Reserved\r
+                DCD     DummyHandler              ; 47: Reserved\r
+\r
+                THUMB\r
+; Dummy Exception Handlers (infinite loops which can be modified)\r
+\r
+                PUBWEAK Reset_Handler\r
+                SECTION .text:CODE:REORDER(2)\r
+Reset_Handler\r
+                LDR     R0, =SystemInit\r
+                BLX     R0\r
+                LDR     R0, =__iar_program_start\r
+                BX      R0\r
+\r
+                PUBWEAK NMI_Handler\r
+                SECTION .text:CODE:REORDER(1)\r
+NMI_Handler\r
+                B       NMI_Handler\r
+\r
+                PUBWEAK HardFault_Handler\r
+                SECTION .text:CODE:REORDER(1)\r
+HardFault_Handler\r
+                B       HardFault_Handler\r
+\r
+                PUBWEAK MemManage_Handler\r
+                SECTION .text:CODE:REORDER(1)\r
+MemManage_Handler\r
+                B       MemManage_Handler\r
+\r
+                PUBWEAK BusFault_Handler\r
+                SECTION .text:CODE:REORDER(1)\r
+BusFault_Handler\r
+                B       BusFault_Handler\r
+\r
+                PUBWEAK UsageFault_Handler\r
+                SECTION .text:CODE:REORDER(1)\r
+UsageFault_Handler\r
+                B       UsageFault_Handler\r
+\r
+                PUBWEAK SVC_Handler\r
+                SECTION .text:CODE:REORDER(1)\r
+SVC_Handler\r
+                B       SVC_Handler\r
+\r
+                PUBWEAK DebugMon_Handler\r
+                SECTION .text:CODE:REORDER(1)\r
+DebugMon_Handler\r
+                B       DebugMon_Handler\r
+\r
+                PUBWEAK PendSV_Handler\r
+                SECTION .text:CODE:REORDER(1)\r
+PendSV_Handler\r
+                B       PendSV_Handler\r
+\r
+                PUBWEAK SysTick_Handler\r
+                SECTION .text:CODE:REORDER(1)\r
+SysTick_Handler\r
+                B       SysTick_Handler\r
+\r
+\r
+\r
+                PUBWEAK CSV_Handler\r
+                SECTION .text:CODE:REORDER(1)\r
+CSV_Handler\r
+                B       CSV_Handler\r
+\r
+                PUBWEAK SWDT_Handler\r
+                SECTION .text:CODE:REORDER(1)\r
+SWDT_Handler\r
+                B       SWDT_Handler\r
+\r
+                PUBWEAK LVD_Handler\r
+                SECTION .text:CODE:REORDER(1)\r
+LVD_Handler\r
+                B       LVD_Handler\r
+\r
+                PUBWEAK MFT_WG_IRQHandler\r
+                SECTION .text:CODE:REORDER(1)\r
+MFT_WG_IRQHandler\r
+                B       MFT_WG_IRQHandler\r
+                \r
+                PUBWEAK INT0_7_Handler\r
+                SECTION .text:CODE:REORDER(1)\r
+INT0_7_Handler\r
+                B       INT0_7_Handler\r
+\r
+                PUBWEAK INT8_15_Handler\r
+                SECTION .text:CODE:REORDER(1)\r
+INT8_15_Handler\r
+                B       INT8_15_Handler\r
+                \r
+                PUBWEAK DT_Handler\r
+                SECTION .text:CODE:REORDER(1)\r
+DT_Handler\r
+                B       DT_Handler\r
+\r
+                PUBWEAK MFS0RX_IRQHandler\r
+                SECTION .text:CODE:REORDER(1)\r
+MFS0RX_IRQHandler\r
+                B       MFS0RX_IRQHandler\r
+\r
+                PUBWEAK MFS0TX_IRQHandler\r
+                SECTION .text:CODE:REORDER(1)\r
+MFS0TX_IRQHandler\r
+                B       MFS0TX_IRQHandler\r
+\r
+                PUBWEAK MFS1RX_IRQHandler\r
+                SECTION .text:CODE:REORDER(1)\r
+MFS1RX_IRQHandler\r
+                B       MFS1RX_IRQHandler\r
+\r
+                PUBWEAK MFS1TX_IRQHandler\r
+                SECTION .text:CODE:REORDER(1)\r
+MFS1TX_IRQHandler\r
+                B       MFS1TX_IRQHandler\r
+\r
+                PUBWEAK MFS2RX_IRQHandler\r
+                SECTION .text:CODE:REORDER(1)\r
+MFS2RX_IRQHandler\r
+                B       MFS2RX_IRQHandler\r
+\r
+                PUBWEAK MFS2TX_IRQHandler\r
+                SECTION .text:CODE:REORDER(1)\r
+MFS2TX_IRQHandler\r
+                B       MFS2TX_IRQHandler\r
+\r
+                PUBWEAK MFS3RX_IRQHandler\r
+                SECTION .text:CODE:REORDER(1)\r
+MFS3RX_IRQHandler\r
+                B       MFS3RX_IRQHandler\r
+\r
+                PUBWEAK MFS3TX_IRQHandler\r
+                SECTION .text:CODE:REORDER(1)\r
+MFS3TX_IRQHandler\r
+                B       MFS3TX_IRQHandler\r
+\r
+                PUBWEAK MFS4RX_IRQHandler\r
+                SECTION .text:CODE:REORDER(1)\r
+MFS4RX_IRQHandler\r
+                B       MFS4RX_IRQHandler\r
+\r
+                PUBWEAK MFS4TX_IRQHandler\r
+                SECTION .text:CODE:REORDER(1)\r
+MFS4TX_IRQHandler\r
+                B       MFS4TX_IRQHandler\r
+\r
+                PUBWEAK MFS5RX_IRQHandler\r
+                SECTION .text:CODE:REORDER(1)\r
+MFS5RX_IRQHandler\r
+                B       MFS5RX_IRQHandler\r
+\r
+                PUBWEAK MFS5TX_IRQHandler\r
+                SECTION .text:CODE:REORDER(1)\r
+MFS5TX_IRQHandler\r
+                B       MFS5TX_IRQHandler\r
+\r
+                PUBWEAK MFS6RX_IRQHandler\r
+                SECTION .text:CODE:REORDER(1)\r
+MFS6RX_IRQHandler\r
+                B       MFS6RX_IRQHandler\r
+\r
+                PUBWEAK MFS6TX_IRQHandler\r
+                SECTION .text:CODE:REORDER(1)\r
+MFS6TX_IRQHandler\r
+                B       MFS6TX_IRQHandler\r
+\r
+                PUBWEAK MFS7RX_IRQHandler\r
+                SECTION .text:CODE:REORDER(1)\r
+MFS7RX_IRQHandler\r
+                B       MFS7RX_IRQHandler\r
+\r
+                PUBWEAK MFS7TX_IRQHandler\r
+                SECTION .text:CODE:REORDER(1)\r
+MFS7TX_IRQHandler\r
+                B       MFS7TX_IRQHandler\r
+\r
+                PUBWEAK PPG_Handler\r
+                SECTION .text:CODE:REORDER(1)\r
+PPG_Handler\r
+                B       PPG_Handler\r
+\r
+                PUBWEAK TIM_IRQHandler\r
+                SECTION .text:CODE:REORDER(1)\r
+TIM_IRQHandler\r
+                B       TIM_IRQHandler\r
+\r
+                PUBWEAK ADC0_IRQHandler\r
+                SECTION .text:CODE:REORDER(1)\r
+ADC0_IRQHandler\r
+                B       ADC0_IRQHandler\r
+\r
+                PUBWEAK ADC1_IRQHandler\r
+                SECTION .text:CODE:REORDER(1)\r
+ADC1_IRQHandler\r
+                B       ADC1_IRQHandler\r
+\r
+                PUBWEAK ADC2_IRQHandler\r
+                SECTION .text:CODE:REORDER(1)\r
+ADC2_IRQHandler\r
+                B       ADC2_IRQHandler\r
+\r
+                PUBWEAK MFT_FRT_IRQHandler\r
+                SECTION .text:CODE:REORDER(1)\r
+MFT_FRT_IRQHandler\r
+                B       MFT_FRT_IRQHandler\r
+\r
+                PUBWEAK MFT_IPC_IRQHandler\r
+                SECTION .text:CODE:REORDER(1)\r
+MFT_IPC_IRQHandler\r
+                B       MFT_IPC_IRQHandler\r
+\r
+                PUBWEAK MFT_OPC_IRQHandler\r
+                SECTION .text:CODE:REORDER(1)\r
+MFT_OPC_IRQHandler\r
+                B       MFT_OPC_IRQHandler\r
+\r
+                PUBWEAK BT_IRQHandler\r
+                SECTION .text:CODE:REORDER(1)\r
+BT_IRQHandler\r
+                B       BT_IRQHandler\r
+\r
+                PUBWEAK CAN0_IRQHandler\r
+                SECTION .text:CODE:REORDER(1)\r
+CAN0_IRQHandler\r
+                B       CAN0_IRQHandler\r
+\r
+                PUBWEAK CAN1_IRQHandler\r
+                SECTION .text:CODE:REORDER(1)\r
+CAN1_IRQHandler\r
+                B       CAN1_IRQHandler\r
+\r
+                PUBWEAK USBF_Handler\r
+                SECTION .text:CODE:REORDER(1)\r
+USBF_Handler\r
+                B       USBF_Handler\r
+\r
+                PUBWEAK USB_Handler\r
+                SECTION .text:CODE:REORDER(1)\r
+USB_Handler\r
+                B       USB_Handler\r
+\r
+                PUBWEAK DMAC0_Handler\r
+                SECTION .text:CODE:REORDER(1)\r
+DMAC0_Handler\r
+                B       DMAC0_Handler\r
+\r
+\r
+                PUBWEAK DMAC1_Handler\r
+                SECTION .text:CODE:REORDER(1)\r
+DMAC1_Handler\r
+                B       DMAC1_Handler\r
+\r
+                PUBWEAK DMAC2_Handler\r
+                SECTION .text:CODE:REORDER(1)\r
+DMAC2_Handler\r
+                B       DMAC2_Handler\r
+\r
+                PUBWEAK DMAC3_Handler\r
+                SECTION .text:CODE:REORDER(1)\r
+DMAC3_Handler\r
+                B       DMAC3_Handler\r
+\r
+                PUBWEAK DMAC4_Handler\r
+                SECTION .text:CODE:REORDER(1)\r
+DMAC4_Handler\r
+                B       DMAC4_Handler\r
+\r
+                PUBWEAK DMAC5_Handler\r
+                SECTION .text:CODE:REORDER(1)\r
+DMAC5_Handler\r
+                B       DMAC5_Handler\r
+\r
+                PUBWEAK DMAC6_Handler\r
+                SECTION .text:CODE:REORDER(1)\r
+DMAC6_Handler\r
+                B       DMAC6_Handler\r
+\r
+                PUBWEAK DMAC7_Handler\r
+                SECTION .text:CODE:REORDER(1)\r
+DMAC7_Handler\r
+                B       DMAC7_Handler\r
+\r
+                PUBWEAK DummyHandler\r
+                SECTION .text:CODE:REORDER(1)\r
+DummyHandler\r
+                B       DummyHandler\r
+\r
+                END\r

diff --git a/Demo/CORTEX_MB9B500_IAR_Keil/Fujitu_source/system_mb9bf50x.c b/Demo/CORTEX_MB9B500_IAR_Keil/Fujitu_source/system_mb9bf50x.c
new file mode 100644 (file)
index 0000000..414f549
--- /dev/null
+++ b/Demo/CORTEX_MB9B500_IAR_Keil/Fujitu_source/system_mb9bf50x.c
@@ -0,0 +1,456 @@
+/************************************************************************/\r
+/*               (C) Fujitsu Semiconductor Europe GmbH (FSEU)           */\r
+/*                                                                      */\r
+/* The following software deliverable is intended for and must only be  */\r
+/* used for reference and in an evaluation laboratory environment.      */\r
+/* It is provided on an as-is basis without charge and is subject to    */\r
+/* alterations.                                                         */\r
+/* It is the user's obligation to fully test the software in its        */\r
+/* environment and to ensure proper functionality, qualification and    */\r
+/* compliance with component specifications.                            */\r
+/*                                                                      */\r
+/* In the event the software deliverable includes the use of open       */\r
+/* source components, the provisions of the governing open source       */\r
+/* license agreement shall apply with respect to such software          */\r
+/* deliverable.                                                         */\r
+/* FSEU does not warrant that the deliverables do not infringe any      */\r
+/* third party intellectual property right (IPR). In the event that     */\r
+/* the deliverables infringe a third party IPR it is the sole           */\r
+/* responsibility of the customer to obtain necessary licenses to       */\r
+/* continue the usage of the deliverable.                               */\r
+/*                                                                      */\r
+/* To the maximum extent permitted by applicable law FSEU disclaims all */\r
+/* warranties, whether express or implied, in particular, but not       */\r
+/* limited to, warranties of merchantability and fitness for a          */\r
+/* particular purpose for which the deliverable is not designated.      */\r
+/*                                                                      */\r
+/* To the maximum extent permitted by applicable law, FSEU's liability  */\r
+/* is restricted to intentional misconduct and gross negligence.        */\r
+/* FSEU is not liable for consequential damages.                        */\r
+/*                                                                      */\r
+/* (V1.5)                                                               */\r
+/************************************************************************/\r
+\r
+#include <stdint.h>\r
+#include "mb9bf506n.h"\r
+\r
+/*--------------------- Clock Configuration ----------------------------------*/\r
+//\r
+// <e0> Clock Configuration\r
+//   <h> System Clock Configuration\r
+//     <o1.1>    SCM_CTL.MOSCE: Main clock oscillation enable\r
+//     <o2.0..3> CSW_TMR.MOWT: Main clock stabilization wait time\r
+//           <i> Default: ~ 500 ns\r
+//                     < 0=> ~ 500 ns \r
+//                     < 1=> ~ 8 us\r
+//                     < 2=> ~ 16 us\r
+//                     < 3=> ~ 32 us\r
+//                     < 4=> ~ 64 us\r
+//                     < 5=> ~ 128 us\r
+//                     < 6=> ~ 256 us\r
+//                     < 7=> ~ 512 us\r
+//                     < 8=> ~ 1.0 ms\r
+//                     < 9=> ~ 2.0 ms\r
+//                     <10=> ~ 4.0 ms\r
+//                     <11=> ~ 8.0 ms\r
+//                     <12=> ~ 33.0 ms\r
+//                     <13=> ~ 131 ms\r
+//                     <14=> ~ 524 ms\r
+//                     <15=> ~ 2.0 s\r
+//     <o1.3>    SCM_CTL.SOSCE: Sub clock oscillation enable\r
+//     <o2.4..6> CSW_TMR.SOWT: SOWT: Sub clock stabilization wait time\r
+//           <i> Default: ~ 31.19 ms\r
+//                     <0=> ~ 31.19 ms \r
+//                     <1=> ~ 62.44 ms\r
+//                     <2=> ~ 0.125 s\r
+//                     <3=> ~ 0.25 s\r
+//                     <4=> ~ 0.50 s\r
+//                     <5=> ~ 1.00 s\r
+//                     <6=> ~ 2.00 s\r
+//                     <7=> ~ 4.00 s\r
+//     <e1.4>    SCM_CTL.PLLE: PLL oscillation enable\r
+//           <i> fPLLO Max = 120MHz, CLKPLL Min = 60MHz\r
+//           <i> CLKPLL = (CLKMO / PLLK) * PLLN\r
+//       <o4.4..7> PLL_CTL1.PLLK: PLL input clock frequency division\r
+//                     <1-16><#-1>\r
+//       <o5.0..4> PLL_CTL1.PLLN: PLL feedback frequency division\r
+//                     <1-32><#-1>\r
+//       <o4.0..3> PLL_CTL1.PLLM: PLL VCO clock frequency division\r
+//                     <1-16><#-1>\r
+//       <o3.0..2> PSW_TMR.POWT: PLL clock stabilization wait time  \r
+//           <i> Default: ~ 128 us\r
+//                     <0=> ~ 128 us \r
+//                     <1=> ~ 256 us\r
+//                     <2=> ~ 512 us\r
+//                     <3=> ~ 1.02 ms\r
+//                     <4=> ~ 2.05 ms\r
+//                     <5=> ~ 4.10 ms\r
+//                     <6=> ~ 8.20 ms\r
+//                     <7=> ~ 16.40 ms\r
+//     </e>\r
+//     <o1.5..7> SCM_CTL.RCS: Master clock switch control\r
+//           <i> Default: Master Clock = CLKHC\r
+//                     <0=> Master Clock = CLKHC \r
+//                     <1=> Master Clock = CLKMO\r
+//                     <2=> Master Clock = CLKPLL\r
+//                     <4=> Master Clock = CLKLC\r
+//                     <5=> Master Clock = CLKSO\r
+//   </h>\r
+//\r
+//   <h> Base Clock Prescaler\r
+//     <o6.0..2> BSC_PSR.BSR: Base clock frequency division \r
+//           <i> Default: HCLK = Master Clock\r
+//           <i> HCLK Max = 80MHz\r
+//                     <0=> HCLK = Master Clock\r
+//                     <1=> HCLK = Master Clock / 2\r
+//                     <2=> HCLK = Master Clock / 3\r
+//                     <3=> HCLK = Master Clock / 4\r
+//                     <4=> HCLK = Master Clock / 6\r
+//                     <5=> HCLK = Master Clock / 8\r
+//                     <6=> HCLK = Master Clock / 16\r
+//   </h>\r
+//\r
+//   <h> APB0 Prescaler\r
+//     <o7.0..1> APBC0_PSR.APBC0: APB0 bus clock frequency division \r
+//           <i> PCLK0 Max = 40MHz\r
+//           <i> Default: PCLK0 = HCLK\r
+//                     <0=> PCLK0 = HCLK\r
+//                     <1=> PCLK0 = HCLK / 2\r
+//                     <2=> PCLK0 = HCLK / 4\r
+//                     <3=> PCLK0 = HCLK / 8\r
+//   </h>\r
+//\r
+//   <h> APB1 Prescaler\r
+//     <o8.0..1> APBC1_PSR.APBC1: APB1 bus clock frequency \r
+//           <i> PCLK1 Max = 40MHz\r
+//           <i> Default: PCLK1 = HCLK\r
+//                     <0=> PCLK1 = HCLK\r
+//                     <1=> PCLK1 = HCLK / 2\r
+//                     <2=> PCLK1 = HCLK / 4\r
+//                     <3=> PCLK1 = HCLK / 8\r
+//     <o8.7>    APBC1_PSR.APBC1EN: APB1 clock enable\r
+//   </h>\r
+//\r
+//   <h> APB2 Prescaler\r
+//     <o9.0..1> APBC2_PSR.APBC2: APB2 bus clock frequency \r
+//           <i> PCLK2 Max = 40MHz\r
+//           <i> Default: PCLK2 = HCLK\r
+//                     <0=> PCLK2 = HCLK\r
+//                     <1=> PCLK2 = HCLK / 2\r
+//                     <2=> PCLK2 = HCLK / 4\r
+//                     <3=> PCLK2 = HCLK / 8\r
+//     <o9.7>    APBC2_PSR.APBC2EN: APB2 clock enable\r
+//   </h>\r
+//\r
+//   <h> SW Watchdog Clock Prescaler\r
+//     <o10.0..1>SWC_PSR.SWDS: Software watchdog clock frequency division \r
+//           <i> Default: SWDGOGCLK = PCLK0\r
+//                     <0=> SWDGOGCLK = PCLK0\r
+//                     <1=> SWDGOGCLK = PCLK0 / 2\r
+//                     <2=> SWDGOGCLK = PCLK0 / 4\r
+//                     <3=> SWDGOGCLK = PCLK0 / 8\r
+//   </h>\r
+//\r
+//   <h> Trace Clock Prescaler\r
+//     <o11.0>   TTC_PSR.TTC: Trace clock frequency division \r
+//           <i> Default: TPIUCLK = HCLK\r
+//                     <0=> TPIUCLK = HCLK\r
+//                     <1=> TPIUCLK = HCLK / 2\r
+//   </h>\r
+//\r
+// </e>\r
+\r
+#define CLOCK_SETUP           1\r
+#define SCM_CTL_Val           0x00000052\r
+#define CSW_TMR_Val           0x0000005C\r
+#define PSW_TMR_Val           0x00000000\r
+#define PLL_CTL1_Val          0x00000000\r
+#define PLL_CTL2_Val          0x00000013\r
+#define BSC_PSR_Val           0x00000000\r
+#define APBC0_PSR_Val         0x00000001\r
+#define APBC1_PSR_Val         0x00000082\r
+#define APBC2_PSR_Val         0x00000081\r
+#define SWC_PSR_Val           0x00000003\r
+#define TTC_PSR_Val           0x00000000\r
+\r
+/*--------------------- WatchDog Configuration -------------------------------*/\r
+//\r
+// <o0.0>  HW Watchdog disable \r
+\r
+#define HWWD_DISABLE          0x00000001\r
+\r
+/*\r
+//-------- <<< end of configuration section >>> ------------------------------\r
+*/\r
+\r
+/*----------------------------------------------------------------------------\r
+  Check the register settings\r
+ *----------------------------------------------------------------------------*/\r
+#define CHECK_RANGE(val, min, max)                ((val < min) || (val > max))\r
+#define CHECK_RSVD(val, mask)                     (val & mask)\r
+\r
+/* Clock Configuration -------------------------------------------------------*/\r
+#if (CHECK_RSVD((SCM_CTL_Val),    ~0x000000FA))\r
+   #error "SCM_CTL: Invalid values of reserved bits!"\r
+#endif\r
+\r
+#if ((SCM_CTL_Val & 0xE0) == 0x40) && ((SCM_CTL_Val & 0x10) != 0x10)\r
+   #error "SCM_CTL: CLKPLL is selected but PLL is not enabled!"\r
+#endif\r
+\r
+#if (CHECK_RSVD((CSW_TMR_Val),    ~0x0000007F))\r
+   #error "CSW_TMR: Invalid values of reserved bits!"\r
+#endif\r
+\r
+#if ((SCM_CTL_Val & 0x10))       /* if PLL is used */\r
+  #if (CHECK_RSVD((PSW_TMR_val),  ~0x00000007))\r
+     #error "PSW_TMR: Invalid values of reserved bits!"\r
+  #endif\r
+\r
+  #if (CHECK_RSVD((PLL_CTL1_Val), ~0x000000FF))\r
+     #error "PLL_CTL1: Invalid values of reserved bits!"\r
+  #endif\r
+\r
+  #if (CHECK_RSVD((PLL_CTL2_Val), ~0x0000001F))\r
+     #error "PLL_CTL2: Invalid values of reserved bits!"\r
+  #endif\r
+#endif\r
+\r
+#if (CHECK_RSVD((BSC_PSR_Val),    ~0x00000007))\r
+   #error "BSC_PSR: Invalid values of reserved bits!"\r
+#endif\r
+\r
+#if (CHECK_RSVD((APBC0_PSR_Val),  ~0x00000003))\r
+   #error "APBC0_PSR: Invalid values of reserved bits!"\r
+#endif\r
+\r
+#if (CHECK_RSVD((APBC1_PSR_Val),  ~0x00000083))\r
+   #error "APBC1_PSR: Invalid values of reserved bits!"\r
+#endif\r
+\r
+#if (CHECK_RSVD((APBC2_PSR_Val),  ~0x00000083))\r
+   #error "APBC2_PSR: Invalid values of reserved bits!"\r
+#endif\r
+\r
+#if (CHECK_RSVD((SWC_PSR_Val),    ~0x00000003))\r
+   #error "SWC_PSR: Invalid values of reserved bits!"\r
+#endif\r
+\r
+#if (CHECK_RSVD((TTC_PSR_Val),    ~0x00000001))\r
+   #error "TTC_PSR: Invalid values of reserved bits!"\r
+#endif\r
+\r
+\r
+/*----------------------------------------------------------------------------\r
+  DEFINES\r
+ *----------------------------------------------------------------------------*/\r
+    \r
+/*----------------------------------------------------------------------------\r
+  Define clocks\r
+ *----------------------------------------------------------------------------*/\r
+#define __CLKMO        ( 4000000UL)         /* External   4MHz Crystal        */\r
+#define __CLKSO        (   32768UL)         /* External  32KHz Crystal        */\r
+#define __CLKHC        ( 4000000UL)         /* Internal   4MHz RC Oscillator  */\r
+#define __CLKLC        (  100000UL)         /* Internal 100KHz RC Oscillator  */\r
+\r
+\r
+/* CLKPLL = (CLKMO / PLLK) * PLLN  */\r
+#define __PLLK         (((PLL_CTL1_Val >> 4) & 0x0F) + 1)\r
+#define __PLLN         (((PLL_CTL2_Val     ) & 0x1F) + 1)\r
+#define __PLLCLK       ((__CLKMO  * __PLLN) / __PLLK)\r
+\r
+/* Determine core clock frequency according to settings */\r
+#if   (((SCM_CTL_Val >> 5) & 0x07) == 0)\r
+    #define __MASTERCLK     (__CLKHC)\r
+#elif (((SCM_CTL_Val >> 5) & 0x07) == 1)\r
+    #define __MASTERCLK     (__CLKMO)\r
+#elif (((SCM_CTL_Val >> 5) & 0x07) == 2)\r
+    #define __MASTERCLK     (__PLLCLK)\r
+#elif (((SCM_CTL_Val >> 5) & 0x07) == 4)\r
+    #define __MASTERCLK     (__CLKLC)\r
+#elif (((SCM_CTL_Val >> 5) & 0x07) == 5)\r
+    #define __MASTERCLK     (__CLKSO)\r
+#else\r
+    #define __MASTERCLK     (0UL)\r
+#endif\r
+\r
+#if   ((BSC_PSR_Val & 0x07) == 0)\r
+    #define __HCLK         (__MASTERCLK / 1)\r
+#elif ((BSC_PSR_Val & 0x07) == 1)\r
+    #define __HCLK         (__MASTERCLK / 2)\r
+#elif ((BSC_PSR_Val & 0x07) == 2)\r
+    #define __HCLK         (__MASTERCLK / 3)\r
+#elif ((BSC_PSR_Val & 0x07) == 3)\r
+    #define __HCLK         (__MASTERCLK / 4)\r
+#elif ((BSC_PSR_Val & 0x07) == 4)\r
+    #define __HCLK         (__MASTERCLK / 6)\r
+#elif ((BSC_PSR_Val & 0x07) == 5)\r
+    #define __HCLK         (__MASTERCLK / 8)\r
+#elif ((BSC_PSR_Val & 0x07) == 6)\r
+    #define __HCLK         (__MASTERCLK /16)\r
+#else\r
+    #define __HCLK         (0UL)\r
+#endif\r
+\r
+\r
+\r
+/*----------------------------------------------------------------------------\r
+  Clock Variable definitions\r
+ *----------------------------------------------------------------------------*/\r
+uint32_t SystemCoreClock = __HCLK;    /*!< System Clock Frequency (Core Clock)*/\r
+\r
+\r
+/**\r
+ * Retrieve the system core clock\r
+ *\r
+ * @param  none\r
+ * @return none\r
+ *\r
+ * @brief  retrieve system core clock from register settings.\r
+ */\r
+void SystemCoreClockUpdate (void) {\r
+  uint32_t masterClk;\r
+  uint32_t u32RegisterRead;\r
+\r
+  switch ((FM3_CRG->SCM_CTL >> 5) & 0x07) {\r
+    case 0:                                 /* internal High-speed Cr osc.    */\r
+      masterClk = __CLKHC;\r
+      break;\r
+\r
+    case 1:                                 /* external main osc.             */\r
+      masterClk = __CLKMO;\r
+      break;\r
+\r
+    case 2:                                 /* PLL clock                      */\r
+      u32RegisterRead = (__CLKMO  * (((FM3_CRG->PLL_CTL2) & 0x1F) + 1));\r
+      masterClk = (u32RegisterRead / (((FM3_CRG->PLL_CTL1 >> 4) & 0x0F) + 1));\r
+      break;\r
+\r
+    case 4:                                 /* internal Low-speed CR osc.     */\r
+      masterClk = __CLKLC;\r
+      break;\r
+\r
+    case 5:                                 /* external Sub osc.              */\r
+      masterClk = __CLKSO;\r
+      break;\r
+\r
+    default:\r
+      masterClk = 0Ul;\r
+      break;\r
+  }\r
+\r
+  switch (FM3_CRG->BSC_PSR & 0x07) {\r
+    case 0:\r
+      SystemCoreClock = masterClk;\r
+      break;\r
+\r
+    case 1:\r
+      SystemCoreClock = masterClk / 2;\r
+      break;\r
+\r
+    case 2:\r
+      SystemCoreClock = masterClk / 3;\r
+      break;\r
+\r
+    case 3:\r
+      SystemCoreClock = masterClk / 4;\r
+      break;\r
+\r
+    case 4:\r
+      SystemCoreClock = masterClk / 6;\r
+      break;\r
+\r
+    case 5:\r
+      SystemCoreClock = masterClk /8;\r
+      break;\r
+\r
+    case 6:\r
+      SystemCoreClock = masterClk /16;\r
+      break;\r
+\r
+    default:\r
+      SystemCoreClock = 0Ul;\r
+      break;\r
+  }\r
+\r
+}\r
+\r
+/*\r
+ *  Set CR Trimming Data\r
+ *\r
+ * @param  none\r
+ * @return none\r
+ *\r
+ * @brief  Update CR trimming with Flash\r
+ *         trimming data.\r
+ */\r
+static void CrtrimSet(void)\r
+{\r
+    /* CR Trimming Data  */\r
+    if( 0x000003FF != (FM3_FLASH_IF->CRTRMM & 0x000003FF) )\r
+    {\r
+           /* UnLock (MCR_FTRM) */\r
+        FM3_CRTRIM->MCR_RLR = 0x1ACCE554;\r
+           /* Set MCR_FTRM */\r
+        FM3_CRTRIM->MCR_FTRM = FM3_FLASH_IF->CRTRMM;\r
+           /* Lock (MCR_FTRM) */\r
+        FM3_CRTRIM->MCR_RLR = 0x00000000;\r
+    }\r
+}\r
+\r
+/**\r
+ * Initialize the system\r
+ *\r
+ * @param  none\r
+ * @return none\r
+ *\r
+ * @brief  Setup the microcontroller system.\r
+ *         Initialize the System.\r
+ */\r
+void SystemInit (void) {\r
+\r
+  uint32_t u32RegisterRead;\r
+  \r
+#if (HWWD_DISABLE)                                   /* HW Watchdog Disable */\r
+  FM3_HWWDT->WDG_LCK = 0x1ACCE551;                     /* HW Watchdog Unlock */\r
+  FM3_HWWDT->WDG_LCK = 0xE5331AAE;\r
+  FM3_HWWDT->WDG_CTL = 0;                              /* HW Watchdog stop */\r
+#endif\r
+\r
+#if (CLOCK_SETUP)                                    /* Clock Setup */\r
+  FM3_CRG->BSC_PSR   = BSC_PSR_Val;                /* set System Clock presacaler */\r
+  FM3_CRG->APBC0_PSR = APBC0_PSR_Val;              /* set APB0 presacaler */\r
+  FM3_CRG->APBC1_PSR = APBC1_PSR_Val;              /* set APB1 presacaler */\r
+  FM3_CRG->APBC2_PSR = APBC2_PSR_Val;              /* set APB2 presacaler */\r
+  FM3_CRG->SWC_PSR   = SWC_PSR_Val | (1UL << 7);   /* set SW Watchdog presacaler */\r
+  FM3_CRG->TTC_PSR   = TTC_PSR_Val;                /* set Trace Clock presacaler */\r
+\r
+  FM3_CRG->CSW_TMR   = CSW_TMR_Val;                /* set oscillation stabilization wait time */\r
+  if (SCM_CTL_Val & (1UL << 1)) {                    /* Main clock oscillator enabled ? */\r
+    FM3_CRG->SCM_CTL |= (1UL << 1);                /* enable main oscillator */ \r
+    while (!(FM3_CRG->SCM_STR & (1UL << 1)));      /* wait for Main clock oscillation stable */\r
+  }\r
+  if (SCM_CTL_Val & (1UL << 3)) {                    /* Sub clock oscillator enabled ? */\r
+    FM3_CRG->SCM_CTL |= (1UL << 3);                /* enable sub oscillator */ \r
+    while (!(FM3_CRG->SCM_STR & (1UL << 3)));      /* wait for Sub clock oscillation stable */\r
+  }\r
+\r
+  FM3_CRG->PSW_TMR   = PSW_TMR_Val;                /* set PLL stabilization wait time */\r
+  FM3_CRG->PLL_CTL1  = PLL_CTL1_Val;               /* set PLLM and PLLK */\r
+  FM3_CRG->PLL_CTL2  = PLL_CTL2_Val;               /* set PLLN          */\r
+  if (SCM_CTL_Val & (1UL << 4)) {                    /* PLL enabled ? */\r
+    FM3_CRG->SCM_CTL  |= (1UL << 4);               /* enable PLL */ \r
+    while (!(FM3_CRG->SCM_STR & (1UL << 4)));      /* wait for PLL stable */\r
+  }\r
+\r
+  FM3_CRG->SCM_CTL  |= (SCM_CTL_Val & 0xE0);       /* Set Master Clock switch */ \r
+  do\r
+  {\r
+    u32RegisterRead = (FM3_CRG->SCM_CTL & 0xE0);\r
+  }while ((FM3_CRG->SCM_STR & 0xE0) != u32RegisterRead);\r
+#endif\r
+  CrtrimSet();\r
+}\r
+\r
+\r
+\r

diff --git a/Demo/CORTEX_MB9B500_IAR_Keil/Fujitu_source/system_mb9bf50x.h b/Demo/CORTEX_MB9B500_IAR_Keil/Fujitu_source/system_mb9bf50x.h
new file mode 100644 (file)
index 0000000..5b87442
--- /dev/null
+++ b/Demo/CORTEX_MB9B500_IAR_Keil/Fujitu_source/system_mb9bf50x.h
@@ -0,0 +1,63 @@
+/************************************************************************/\r
+/*               (C) Fujitsu Semiconductor Europe GmbH (FSEU)           */\r
+/*                                                                      */\r
+/* The following software deliverable is intended for and must only be  */\r
+/* used for reference and in an evaluation laboratory environment.      */\r
+/* It is provided on an as-is basis without charge and is subject to    */\r
+/* alterations.                                                         */\r
+/* It is the user's obligation to fully test the software in its        */\r
+/* environment and to ensure proper functionality, qualification and    */\r
+/* compliance with component specifications.                            */\r
+/*                                                                      */\r
+/* In the event the software deliverable includes the use of open       */\r
+/* source components, the provisions of the governing open source       */\r
+/* license agreement shall apply with respect to such software          */\r
+/* deliverable.                                                         */\r
+/* FSEU does not warrant that the deliverables do not infringe any      */\r
+/* third party intellectual property right (IPR). In the event that     */\r
+/* the deliverables infringe a third party IPR it is the sole           */\r
+/* responsibility of the customer to obtain necessary licenses to       */\r
+/* continue the usage of the deliverable.                               */\r
+/*                                                                      */\r
+/* To the maximum extent permitted by applicable law FSEU disclaims all */\r
+/* warranties, whether express or implied, in particular, but not       */\r
+/* limited to, warranties of merchantability and fitness for a          */\r
+/* particular purpose for which the deliverable is not designated.      */\r
+/*                                                                      */\r
+/* To the maximum extent permitted by applicable law, FSEU's liability  */\r
+/* is restricted to intentional misconduct and gross negligence.        */\r
+/* FSEU is not liable for consequential damages.                        */\r
+/*                                                                      */\r
+/* (V1.5)                                                               */\r
+/************************************************************************/\r
+\r
+#ifndef _SYSTEM_MB9B5XX_H_\r
+#define _SYSTEM_MB9B5XX_H_\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif \r
+\r
+/*\r
+ *  Clock\r
+ */\r
+extern uint32_t SystemCoreClock;       /* Core Clock CMSIS V 1.3 */\r
+extern const uint32_t SystemFrequency; /* Master Clock           */\r
+extern uint32_t SysFreHCLK;            /* HCLK                   */\r
+extern uint32_t SysFrePCLK0;           /* PCLK0                  */\r
+extern uint32_t SysFrePCLK1;           /* PCLK1                  */\r
+extern uint32_t SysFrePCLK2;           /* PCLK2                  */\r
+extern uint32_t SysFreTPIU;            /* TPIU                   */\r
+\r
+/*\r
+ *  Setup the microcontroller system\r
+ */\r
+extern void SystemInit(void);\r
+extern void SystemCoreClockUpdate(void);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* _SYSTEM_MB9B5XX_H_ */\r
+\r

diff --git a/Demo/CORTEX_MB9B500_IAR_Keil/RTOSDemo_IAR.ewd b/Demo/CORTEX_MB9B500_IAR_Keil/RTOSDemo_IAR.ewd
new file mode 100644 (file)
index 0000000..bf4bc60
--- /dev/null
+++ b/Demo/CORTEX_MB9B500_IAR_Keil/RTOSDemo_IAR.ewd
@@ -0,0 +1,1751 @@
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<project>\r
+  <fileVersion>2</fileVersion>\r
+  <configuration>\r
+    <name>Debug</name>\r
+    <toolchain>\r
+      <name>ARM</name>\r
+    </toolchain>\r
+    <debug>1</debug>\r
+    <settings>\r
+      <name>C-SPY</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>22</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>CInput</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CEndian</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CProcessor</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OCVariant</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>MacOverride</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>MacFile</name>\r
+          <state>$PROJ_DIR$\config\Ram_VTOR.mac</state>\r
+        </option>\r
+        <option>\r
+          <name>MemOverride</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>MemFile</name>\r
+          <state>$TOOLKIT_DIR$\CONFIG\debugger\Fujitsu\iomb9bf506n.ddf</state>\r
+        </option>\r
+        <option>\r
+          <name>RunToEnable</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>RunToName</name>\r
+          <state>main</state>\r
+        </option>\r
+        <option>\r
+          <name>CExtraOptionsCheck</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CExtraOptions</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CFpuProcessor</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDDFArgumentProducer</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>OCDownloadSuppressDownload</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDownloadVerifyAll</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OCProductVersion</name>\r
+          <state>5.50.5.51996</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDynDriverList</name>\r
+          <state>JLINK_ID</state>\r
+        </option>\r
+        <option>\r
+          <name>OCLastSavedByProductVersion</name>\r
+          <state>6.20.1.52589</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDownloadAttachToProgram</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>UseFlashLoader</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CLowLevel</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OCBE8Slave</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>MacFile2</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CDevice</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>FlashLoadersV3</name>\r
+          <state>$PROJ_DIR$\config\flashloader\FlashLoader.board</state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesSuppressCheck1</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesPath1</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesSuppressCheck2</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesPath2</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesSuppressCheck3</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesPath3</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>OverrideDefFlashBoard</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesOffset1</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesOffset2</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesOffset3</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesUse1</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesUse2</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesUse3</name>\r
+          <state>0</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>ARMSIM_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>1</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>OCSimDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OCSimEnablePSP</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCSimPspOverrideConfig</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCSimPspConfigFile</name>\r
+          <state></state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>ANGEL_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>0</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>CCAngelHeartbeat</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CAngelCommunication</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CAngelCommBaud</name>\r
+          <version>0</version>\r
+          <state>3</state>\r
+        </option>\r
+        <option>\r
+          <name>CAngelCommPort</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>ANGELTCPIP</name>\r
+          <state>aaa.bbb.ccc.ddd</state>\r
+        </option>\r
+        <option>\r
+          <name>DoAngelLogfile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>AngelLogFile</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>GDBSERVER_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>0</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>TCPIP</name>\r
+          <state>aaa.bbb.ccc.ddd</state>\r
+        </option>\r
+        <option>\r
+          <name>DoLogfile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>LogFile</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJTagBreakpointRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJTagDoUpdateBreakpoints</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJTagUpdateBreakpoints</name>\r
+          <state>_call_main</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>IARROM_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>1</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>CRomLogFileCheck</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CRomLogFileEditB</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>CRomCommPort</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CRomCommBaud</name>\r
+          <version>0</version>\r
+          <state>7</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>JLINK_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>13</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>JLinkSpeed</name>\r
+          <state>32</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkDoLogfile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkLogFile</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkHWResetDelay</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>JLinkInitialSpeed</name>\r
+          <state>32</state>\r
+        </option>\r
+        <option>\r
+          <name>CCDoJlinkMultiTarget</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCScanChainNonARMDevices</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkMultiTarget</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkIRLength</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkCommRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkTCPIP</name>\r
+          <state>aaa.bbb.ccc.ddd</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkSpeedRadioV2</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCUSBDevice</name>\r
+          <version>1</version>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchReset</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchUndef</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchSWI</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchData</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchPrefetch</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchIRQ</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchFIQ</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkBreakpointRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkDoUpdateBreakpoints</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkUpdateBreakpoints</name>\r
+          <state>_call_main</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkInterfaceRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCJLinkAttachSlave</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkResetList</name>\r
+          <version>5</version>\r
+          <state>7</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkInterfaceCmdLine</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCatchCORERESET</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCatchMMERR</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCatchNOCPERR</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCatchCHRERR</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCatchSTATERR</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCatchBUSERR</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCatchINTERR</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCatchHARDERR</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCatchDummy</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCJLinkScriptFile</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkUsbSerialNo</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CCTcpIpAlt</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkTcpIpSerialNo</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CCCpuClockEdit</name>\r
+          <state>72.0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCSwoClockAuto</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCSwoClockEdit</name>\r
+          <state>2000</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>LMIFTDI_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>2</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>LmiftdiSpeed</name>\r
+          <state>500</state>\r
+        </option>\r
+        <option>\r
+          <name>CCLmiftdiDoLogfile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCLmiftdiLogFile</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>CCLmiFtdiInterfaceRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCLmiFtdiInterfaceCmdLine</name>\r
+          <state>0</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>MACRAIGOR_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>3</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>jtag</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>EmuSpeed</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>TCPIP</name>\r
+          <state>aaa.bbb.ccc.ddd</state>\r
+        </option>\r
+        <option>\r
+          <name>DoLogfile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>LogFile</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>DoEmuMultiTarget</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>EmuMultiTarget</name>\r
+          <state>0@ARM7TDMI</state>\r
+        </option>\r
+        <option>\r
+          <name>EmuHWReset</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CEmuCommBaud</name>\r
+          <version>0</version>\r
+          <state>4</state>\r
+        </option>\r
+        <option>\r
+          <name>CEmuCommPort</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>jtago</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>UnusedAddr</name>\r
+          <state>0x00800000</state>\r
+        </option>\r
+        <option>\r
+          <name>CCMacraigorHWResetDelay</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CCJTagBreakpointRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJTagDoUpdateBreakpoints</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJTagUpdateBreakpoints</name>\r
+          <state>_call_main</state>\r
+        </option>\r
+        <option>\r
+          <name>CCMacraigorInterfaceRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCMacraigorInterfaceCmdLine</name>\r
+          <state>0</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>PEMICRO_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>0</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OCPEMicroAttachSlave</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CCPEMicroInterfaceList</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCPEMicroResetDelay</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CCPEMicroJtagSpeed</name>\r
+          <state>#UNINITIALIZED#</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJPEMicroShowSettings</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>DoLogfile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>LogFile</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>CCPEMicroUSBDevice</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCPEMicroSerialPort</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJPEMicroTCPIPAutoScanNetwork</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CCPEMicroTCPIP</name>\r
+          <state>10.0.0.1</state>\r
+        </option>\r
+        <option>\r
+          <name>CCPEMicroCommCmdLineProducer</name>\r
+          <state>0</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>RDI_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>2</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>CRDIDriverDll</name>\r
+          <state>###Uninitialized###</state>\r
+        </option>\r
+        <option>\r
+          <name>CRDILogFileCheck</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CRDILogFileEdit</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDIHWReset</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchReset</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchUndef</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchSWI</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchData</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchPrefetch</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchIRQ</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchFIQ</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>STLINK_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>2</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CCSTLinkInterfaceRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCSTLinkInterfaceCmdLine</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCSTLinkResetList</name>\r
+          <version>1</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCpuClockEdit</name>\r
+          <state>72.0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCSwoClockAuto</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCSwoClockEdit</name>\r
+          <state>2000</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>THIRDPARTY_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>0</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>CThirdPartyDriverDll</name>\r
+          <state>###Uninitialized###</state>\r
+        </option>\r
+        <option>\r
+          <name>CThirdPartyLogFileCheck</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CThirdPartyLogFileEditB</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <debuggerPlugins>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB6_Plugin.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>\r
+        <loadFlag>1</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$EW_DIR$\common\plugins\FreeRTOS\FreeRTOSPlugin.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$EW_DIR$\common\plugins\OpenRTOS\OpenRTOSPlugin.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$EW_DIR$\common\plugins\Stack\Stack.ENU.ewplugin</file>\r
+        <loadFlag>1</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>\r
+        <loadFlag>1</loadFlag>\r
+      </plugin>\r
+    </debuggerPlugins>\r
+  </configuration>\r
+  <configuration>\r
+    <name>Release</name>\r
+    <toolchain>\r
+      <name>ARM</name>\r
+    </toolchain>\r
+    <debug>0</debug>\r
+    <settings>\r
+      <name>C-SPY</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>22</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>0</debug>\r
+        <option>\r
+          <name>CInput</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CEndian</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CProcessor</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OCVariant</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>MacOverride</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>MacFile</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>MemOverride</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>MemFile</name>\r
+          <state>$TOOLKIT_DIR$\CONFIG\debugger\Fujitsu\iomb9bf506n.ddf</state>\r
+        </option>\r
+        <option>\r
+          <name>RunToEnable</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>RunToName</name>\r
+          <state>main</state>\r
+        </option>\r
+        <option>\r
+          <name>CExtraOptionsCheck</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CExtraOptions</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CFpuProcessor</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDDFArgumentProducer</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>OCDownloadSuppressDownload</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDownloadVerifyAll</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OCProductVersion</name>\r
+          <state>5.50.5.51996</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDynDriverList</name>\r
+          <state>JLINK_ID</state>\r
+        </option>\r
+        <option>\r
+          <name>OCLastSavedByProductVersion</name>\r
+          <state>6.10.3.52260</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDownloadAttachToProgram</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>UseFlashLoader</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CLowLevel</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OCBE8Slave</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>MacFile2</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CDevice</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>FlashLoadersV3</name>\r
+          <state>$PROJ_DIR$\config\flashloader\FlashLoader.board</state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesSuppressCheck1</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesPath1</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesSuppressCheck2</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesPath2</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesSuppressCheck3</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesPath3</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>OverrideDefFlashBoard</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesOffset1</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesOffset2</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesOffset3</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesUse1</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesUse2</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesUse3</name>\r
+          <state>0</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>ARMSIM_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>1</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>0</debug>\r
+        <option>\r
+          <name>OCSimDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OCSimEnablePSP</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCSimPspOverrideConfig</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCSimPspConfigFile</name>\r
+          <state></state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>ANGEL_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>0</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>0</debug>\r
+        <option>\r
+          <name>CCAngelHeartbeat</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CAngelCommunication</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CAngelCommBaud</name>\r
+          <version>0</version>\r
+          <state>3</state>\r
+        </option>\r
+        <option>\r
+          <name>CAngelCommPort</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>ANGELTCPIP</name>\r
+          <state>aaa.bbb.ccc.ddd</state>\r
+        </option>\r
+        <option>\r
+          <name>DoAngelLogfile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>AngelLogFile</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>GDBSERVER_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>0</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>0</debug>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>TCPIP</name>\r
+          <state>aaa.bbb.ccc.ddd</state>\r
+        </option>\r
+        <option>\r
+          <name>DoLogfile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>LogFile</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJTagBreakpointRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJTagDoUpdateBreakpoints</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJTagUpdateBreakpoints</name>\r
+          <state>_call_main</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>IARROM_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>1</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>0</debug>\r
+        <option>\r
+          <name>CRomLogFileCheck</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CRomLogFileEditB</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>CRomCommPort</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CRomCommBaud</name>\r
+          <version>0</version>\r
+          <state>7</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>JLINK_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>13</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>0</debug>\r
+        <option>\r
+          <name>JLinkSpeed</name>\r
+          <state>32</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkDoLogfile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkLogFile</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkHWResetDelay</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>JLinkInitialSpeed</name>\r
+          <state>32</state>\r
+        </option>\r
+        <option>\r
+          <name>CCDoJlinkMultiTarget</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCScanChainNonARMDevices</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkMultiTarget</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkIRLength</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkCommRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkTCPIP</name>\r
+          <state>aaa.bbb.ccc.ddd</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkSpeedRadioV2</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCUSBDevice</name>\r
+          <version>1</version>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchReset</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchUndef</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchSWI</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchData</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchPrefetch</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchIRQ</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchFIQ</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkBreakpointRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkDoUpdateBreakpoints</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkUpdateBreakpoints</name>\r
+          <state>_call_main</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkInterfaceRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCJLinkAttachSlave</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkResetList</name>\r
+          <version>5</version>\r
+          <state>7</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkInterfaceCmdLine</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCatchCORERESET</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCatchMMERR</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCatchNOCPERR</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCatchCHRERR</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCatchSTATERR</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCatchBUSERR</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCatchINTERR</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCatchHARDERR</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCatchDummy</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCJLinkScriptFile</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkUsbSerialNo</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CCTcpIpAlt</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkTcpIpSerialNo</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CCCpuClockEdit</name>\r
+          <state>72.0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCSwoClockAuto</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCSwoClockEdit</name>\r
+          <state>2000</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>LMIFTDI_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>2</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>0</debug>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>LmiftdiSpeed</name>\r
+          <state>500</state>\r
+        </option>\r
+        <option>\r
+          <name>CCLmiftdiDoLogfile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCLmiftdiLogFile</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>CCLmiFtdiInterfaceRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCLmiFtdiInterfaceCmdLine</name>\r
+          <state>0</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>MACRAIGOR_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>3</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>0</debug>\r
+        <option>\r
+          <name>jtag</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>EmuSpeed</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>TCPIP</name>\r
+          <state>aaa.bbb.ccc.ddd</state>\r
+        </option>\r
+        <option>\r
+          <name>DoLogfile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>LogFile</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>DoEmuMultiTarget</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>EmuMultiTarget</name>\r
+          <state>0@ARM7TDMI</state>\r
+        </option>\r
+        <option>\r
+          <name>EmuHWReset</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CEmuCommBaud</name>\r
+          <version>0</version>\r
+          <state>4</state>\r
+        </option>\r
+        <option>\r
+          <name>CEmuCommPort</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>jtago</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>UnusedAddr</name>\r
+          <state>0x00800000</state>\r
+        </option>\r
+        <option>\r
+          <name>CCMacraigorHWResetDelay</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CCJTagBreakpointRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJTagDoUpdateBreakpoints</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJTagUpdateBreakpoints</name>\r
+          <state>_call_main</state>\r
+        </option>\r
+        <option>\r
+          <name>CCMacraigorInterfaceRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCMacraigorInterfaceCmdLine</name>\r
+          <state>0</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>PEMICRO_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>0</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>0</debug>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OCPEMicroAttachSlave</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CCPEMicroInterfaceList</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCPEMicroResetDelay</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CCPEMicroJtagSpeed</name>\r
+          <state>#UNINITIALIZED#</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJPEMicroShowSettings</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>DoLogfile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>LogFile</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>CCPEMicroUSBDevice</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCPEMicroSerialPort</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJPEMicroTCPIPAutoScanNetwork</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CCPEMicroTCPIP</name>\r
+          <state>10.0.0.1</state>\r
+        </option>\r
+        <option>\r
+          <name>CCPEMicroCommCmdLineProducer</name>\r
+          <state>0</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>RDI_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>2</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>0</debug>\r
+        <option>\r
+          <name>CRDIDriverDll</name>\r
+          <state>###Uninitialized###</state>\r
+        </option>\r
+        <option>\r
+          <name>CRDILogFileCheck</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CRDILogFileEdit</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDIHWReset</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchReset</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchUndef</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchSWI</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchData</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchPrefetch</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchIRQ</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchFIQ</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>STLINK_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>2</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>0</debug>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CCSTLinkInterfaceRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCSTLinkInterfaceCmdLine</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCSTLinkResetList</name>\r
+          <version>1</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCpuClockEdit</name>\r
+          <state>72.0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCSwoClockAuto</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCSwoClockEdit</name>\r
+          <state>2000</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>THIRDPARTY_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>0</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>0</debug>\r
+        <option>\r
+          <name>CThirdPartyDriverDll</name>\r
+          <state>###Uninitialized###</state>\r
+        </option>\r
+        <option>\r
+          <name>CThirdPartyLogFileCheck</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CThirdPartyLogFileEditB</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <debuggerPlugins>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB6_Plugin.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>\r
+        <loadFlag>1</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$EW_DIR$\common\plugins\FreeRTOS\FreeRTOSPlugin.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$EW_DIR$\common\plugins\OpenRTOS\OpenRTOSPlugin.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$EW_DIR$\common\plugins\Stack\Stack.ENU.ewplugin</file>\r
+        <loadFlag>1</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>\r
+        <loadFlag>1</loadFlag>\r
+      </plugin>\r
+    </debuggerPlugins>\r
+  </configuration>\r
+</project>\r
+\r
+\r

diff --git a/Demo/CORTEX_MB9B500_IAR_Keil/RTOSDemo_IAR.ewp b/Demo/CORTEX_MB9B500_IAR_Keil/RTOSDemo_IAR.ewp
new file mode 100644 (file)
index 0000000..2a41ab2
--- /dev/null
+++ b/Demo/CORTEX_MB9B500_IAR_Keil/RTOSDemo_IAR.ewp
@@ -0,0 +1,1840 @@
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<project>\r
+  <fileVersion>2</fileVersion>\r
+  <configuration>\r
+    <name>Debug</name>\r
+    <toolchain>\r
+      <name>ARM</name>\r
+    </toolchain>\r
+    <debug>1</debug>\r
+    <settings>\r
+      <name>General</name>\r
+      <archiveVersion>3</archiveVersion>\r
+      <data>\r
+        <version>21</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>ExePath</name>\r
+          <state>output\debug\exe</state>\r
+        </option>\r
+        <option>\r
+          <name>ObjPath</name>\r
+          <state>output\debug\obj</state>\r
+        </option>\r
+        <option>\r
+          <name>ListPath</name>\r
+          <state>output\debug\list</state>\r
+        </option>\r
+        <option>\r
+          <name>Variant</name>\r
+          <version>19</version>\r
+          <state>37</state>\r
+        </option>\r
+        <option>\r
+          <name>GEndianMode</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>Input variant</name>\r
+          <version>3</version>\r
+          <state>3</state>\r
+        </option>\r
+        <option>\r
+          <name>Input description</name>\r
+          <state>No specifier n, no float nor long long.</state>\r
+        </option>\r
+        <option>\r
+          <name>Output variant</name>\r
+          <version>2</version>\r
+          <state>3</state>\r
+        </option>\r
+        <option>\r
+          <name>Output description</name>\r
+          <state>No specifier a, A.</state>\r
+        </option>\r
+        <option>\r
+          <name>GOutputBinary</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>FPU</name>\r
+          <version>2</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OGCoreOrChip</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>GRuntimeLibSelect</name>\r
+          <version>0</version>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>GRuntimeLibSelectSlave</name>\r
+          <version>0</version>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>RTDescription</name>\r
+          <state>Use the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>\r
+        </option>\r
+        <option>\r
+          <name>OGProductVersion</name>\r
+          <state>5.50.5.51996</state>\r
+        </option>\r
+        <option>\r
+          <name>OGLastSavedByProductVersion</name>\r
+          <state>6.20.1.52589</state>\r
+        </option>\r
+        <option>\r
+          <name>GeneralEnableMisra</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>GeneralMisraVerbose</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OGChipSelectEditMenu</name>\r
+          <state>MB9BF506N     Fujitsu MB9BF506N</state>\r
+        </option>\r
+        <option>\r
+          <name>GenLowLevelInterface</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>GEndianModeBE</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OGBufferedTerminalOutput</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>GenStdoutInterface</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>GeneralMisraRules98</name>\r
+          <version>0</version>\r
+          <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>\r
+        </option>\r
+        <option>\r
+          <name>GeneralMisraVer</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>GeneralMisraRules04</name>\r
+          <version>0</version>\r
+          <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>\r
+        </option>\r
+        <option>\r
+          <name>RTConfigPath2</name>\r
+          <state>$TOOLKIT_DIR$\INC\c\DLib_Config_Normal.h</state>\r
+        </option>\r
+        <option>\r
+          <name>GFPUCoreSlave</name>\r
+          <version>19</version>\r
+          <state>37</state>\r
+        </option>\r
+        <option>\r
+          <name>GBECoreSlave</name>\r
+          <version>19</version>\r
+          <state>37</state>\r
+        </option>\r
+        <option>\r
+          <name>OGUseCmsis</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OGUseCmsisDspLib</name>\r
+          <state>0</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>ICCARM</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>28</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>CCDefines</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CCPreprocFile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCPreprocComments</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCPreprocLine</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCListCFile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCListCMnemonics</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCListCMessages</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCListAssFile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCListAssSource</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCEnableRemarks</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCDiagSuppress</name>\r
+          <state>Pa082</state>\r
+        </option>\r
+        <option>\r
+          <name>CCDiagRemark</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CCDiagWarning</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CCDiagError</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CCObjPrefix</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CCAllowList</name>\r
+          <version>1</version>\r
+          <state>0000000</state>\r
+        </option>\r
+        <option>\r
+          <name>CCDebugInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IEndianMode</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IProcessor</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IExtraOptionsCheck</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IExtraOptions</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CCLangConformance</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCSignedPlainChar</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRequirePrototypes</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCMultibyteSupport</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCDiagWarnAreErr</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCompilerRuntimeInfo</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IFpuProcessor</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OutputFile</name>\r
+          <state>$FILE_BNAME$.o</state>\r
+        </option>\r
+        <option>\r
+          <name>CCLibConfigHeader</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>PreInclude</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CompilerMisraOverride</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCIncludePath2</name>\r
+          <state>$PROJ_DIR$/Fujitu_source</state>\r
+          <state>$PROJ_DIR$</state>\r
+          <state>$PROJ_DIR$/../../Source/include</state>\r
+          <state>$PROJ_DIR$/../../Source/portable/IAR/ARM_CM3</state>\r
+        </option>\r
+        <option>\r
+          <name>CCStdIncCheck</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCodeSection</name>\r
+          <state>.text</state>\r
+        </option>\r
+        <option>\r
+          <name>IInterwork2</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IProcessorMode2</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CCOptLevel</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCOptStrategy</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCOptLevelSlave</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CompilerMisraRules98</name>\r
+          <version>0</version>\r
+          <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>\r
+        </option>\r
+        <option>\r
+          <name>CompilerMisraRules04</name>\r
+          <version>0</version>\r
+          <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>\r
+        </option>\r
+        <option>\r
+          <name>CCPosIndRopi</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCPosIndRwpi</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCPosIndNoDynInit</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IccLang</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IccCDialect</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IccAllowVLA</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IccCppDialect</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IccExceptions</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IccRTTI</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IccStaticDestr</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IccCppInlineSemantics</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IccCmsis</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IccFloatSemantics</name>\r
+          <state>0</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>AARM</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>8</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>AObjPrefix</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>AEndian</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>ACaseSensitivity</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>MacroChars</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>AWarnEnable</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>AWarnWhat</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>AWarnOne</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>AWarnRange1</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>AWarnRange2</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>ADebug</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>AltRegisterNames</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>ADefines</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>AList</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>AListHeader</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>AListing</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>Includes</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>MacDefs</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>MacExps</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>MacExec</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OnlyAssed</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>MultiLine</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>PageLengthCheck</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>PageLength</name>\r
+          <state>80</state>\r
+        </option>\r
+        <option>\r
+          <name>TabSpacing</name>\r
+          <state>8</state>\r
+        </option>\r
+        <option>\r
+          <name>AXRef</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>AXRefDefines</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>AXRefInternal</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>AXRefDual</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>AProcessor</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>AFpuProcessor</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>AOutputFile</name>\r
+          <state>$FILE_BNAME$.o</state>\r
+        </option>\r
+        <option>\r
+          <name>AMultibyteSupport</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>ALimitErrorsCheck</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>ALimitErrorsEdit</name>\r
+          <state>100</state>\r
+        </option>\r
+        <option>\r
+          <name>AIgnoreStdInclude</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>AUserIncludes</name>\r
+          <state>$PROJ_DIR$</state>\r
+        </option>\r
+        <option>\r
+          <name>AExtraOptionsCheckV2</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>AExtraOptionsV2</name>\r
+          <state></state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>OBJCOPY</name>\r
+      <archiveVersion>0</archiveVersion>\r
+      <data>\r
+        <version>1</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>OOCOutputFormat</name>\r
+          <version>2</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCOutputOverride</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OOCOutputFile</name>\r
+          <state>RTOSDemo_IAR.srec</state>\r
+        </option>\r
+        <option>\r
+          <name>OOCCommandLineProducer</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OOCObjCopyEnable</name>\r
+          <state>0</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>CUSTOM</name>\r
+      <archiveVersion>3</archiveVersion>\r
+      <data>\r
+        <extensions></extensions>\r
+        <cmdline></cmdline>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>BICOMP</name>\r
+      <archiveVersion>0</archiveVersion>\r
+      <data/>\r
+    </settings>\r
+    <settings>\r
+      <name>BUILDACTION</name>\r
+      <archiveVersion>1</archiveVersion>\r
+      <data>\r
+        <prebuild></prebuild>\r
+        <postbuild></postbuild>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>ILINK</name>\r
+      <archiveVersion>0</archiveVersion>\r
+      <data>\r
+        <version>13</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>IlinkLibIOConfig</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>XLinkMisraHandler</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkInputFileSlave</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkOutputFile</name>\r
+          <state>RTOSDemo_IAR.out</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkDebugInfoEnable</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkKeepSymbols</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkRawBinaryFile</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkRawBinarySymbol</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkRawBinarySegment</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkRawBinaryAlign</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkDefines</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkConfigDefines</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkMapFile</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkLogFile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkLogInitialization</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkLogModule</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkLogSection</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkLogVeneer</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkIcfOverride</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkIcfFile</name>\r
+          <state>$PROJ_DIR$\config\mb9bf506_ram.icf</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkIcfFileSlave</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkEnableRemarks</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkSuppressDiags</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkTreatAsRem</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkTreatAsWarn</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkTreatAsErr</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkWarningsAreErrors</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkUseExtraOptions</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkExtraOptions</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkLowLevelInterfaceSlave</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkAutoLibEnable</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkAdditionalLibs</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkOverrideProgramEntryLabel</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkProgramEntryLabelSelect</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkProgramEntryLabel</name>\r
+          <state>__iar_program_start</state>\r
+        </option>\r
+        <option>\r
+          <name>DoFill</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>FillerByte</name>\r
+          <state>0xFF</state>\r
+        </option>\r
+        <option>\r
+          <name>FillerStart</name>\r
+          <state>0x0</state>\r
+        </option>\r
+        <option>\r
+          <name>FillerEnd</name>\r
+          <state>0x0</state>\r
+        </option>\r
+        <option>\r
+          <name>CrcSize</name>\r
+          <version>0</version>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CrcAlign</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CrcAlgo</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CrcPoly</name>\r
+          <state>0x11021</state>\r
+        </option>\r
+        <option>\r
+          <name>CrcCompl</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CrcBitOrder</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CrcInitialValue</name>\r
+          <state>0x0</state>\r
+        </option>\r
+        <option>\r
+          <name>DoCrc</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkBE8Slave</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkBufferedTerminalOutput</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkStdoutInterfaceSlave</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CrcFullSize</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkIElfToolPostProcess</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkLogAutoLibSelect</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkLogRedirSymbols</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkLogUnusedFragments</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkCrcReverseByteOrder</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkCrcUseAsInput</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkOptInline</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkOptExceptionsAllow</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkOptExceptionsForce</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkCmsis</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkOptMergeDuplSections</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkOptUseVfe</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkOptForceVfe</name>\r
+          <state>0</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>IARCHIVE</name>\r
+      <archiveVersion>0</archiveVersion>\r
+      <data>\r
+        <version>0</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>IarchiveInputs</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IarchiveOverride</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IarchiveOutput</name>\r
+          <state>###Unitialized###</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>BILINK</name>\r
+      <archiveVersion>0</archiveVersion>\r
+      <data/>\r
+    </settings>\r
+  </configuration>\r
+  <configuration>\r
+    <name>Release</name>\r
+    <toolchain>\r
+      <name>ARM</name>\r
+    </toolchain>\r
+    <debug>0</debug>\r
+    <settings>\r
+      <name>General</name>\r
+      <archiveVersion>3</archiveVersion>\r
+      <data>\r
+        <version>21</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>0</debug>\r
+        <option>\r
+          <name>ExePath</name>\r
+          <state>output\release\exe</state>\r
+        </option>\r
+        <option>\r
+          <name>ObjPath</name>\r
+          <state>output\release\obj</state>\r
+        </option>\r
+        <option>\r
+          <name>ListPath</name>\r
+          <state>output\release\list</state>\r
+        </option>\r
+        <option>\r
+          <name>Variant</name>\r
+          <version>19</version>\r
+          <state>37</state>\r
+        </option>\r
+        <option>\r
+          <name>GEndianMode</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>Input variant</name>\r
+          <version>3</version>\r
+          <state>3</state>\r
+        </option>\r
+        <option>\r
+          <name>Input description</name>\r
+          <state>No specifier n, no float nor long long.</state>\r
+        </option>\r
+        <option>\r
+          <name>Output variant</name>\r
+          <version>2</version>\r
+          <state>3</state>\r
+        </option>\r
+        <option>\r
+          <name>Output description</name>\r
+          <state>No specifier a, A.</state>\r
+        </option>\r
+        <option>\r
+          <name>GOutputBinary</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>FPU</name>\r
+          <version>2</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OGCoreOrChip</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>GRuntimeLibSelect</name>\r
+          <version>0</version>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>GRuntimeLibSelectSlave</name>\r
+          <version>0</version>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>RTDescription</name>\r
+          <state>Use the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>\r
+        </option>\r
+        <option>\r
+          <name>OGProductVersion</name>\r
+          <state>5.50.5.51996</state>\r
+        </option>\r
+        <option>\r
+          <name>OGLastSavedByProductVersion</name>\r
+          <state>6.10.3.52260</state>\r
+        </option>\r
+        <option>\r
+          <name>GeneralEnableMisra</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>GeneralMisraVerbose</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OGChipSelectEditMenu</name>\r
+          <state>MB9BF506N     Fujitsu MB9BF506N</state>\r
+        </option>\r
+        <option>\r
+          <name>GenLowLevelInterface</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>GEndianModeBE</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OGBufferedTerminalOutput</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>GenStdoutInterface</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>GeneralMisraRules98</name>\r
+          <version>0</version>\r
+          <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>\r
+        </option>\r
+        <option>\r
+          <name>GeneralMisraVer</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>GeneralMisraRules04</name>\r
+          <version>0</version>\r
+          <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>\r
+        </option>\r
+        <option>\r
+          <name>RTConfigPath2</name>\r
+          <state>$TOOLKIT_DIR$\INC\c\DLib_Config_Normal.h</state>\r
+        </option>\r
+        <option>\r
+          <name>GFPUCoreSlave</name>\r
+          <version>19</version>\r
+          <state>37</state>\r
+        </option>\r
+        <option>\r
+          <name>GBECoreSlave</name>\r
+          <version>19</version>\r
+          <state>37</state>\r
+        </option>\r
+        <option>\r
+          <name>OGUseCmsis</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OGUseCmsisDspLib</name>\r
+          <state>0</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>ICCARM</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>28</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>0</debug>\r
+        <option>\r
+          <name>CCDefines</name>\r
+          <state>NDEBUG</state>\r
+        </option>\r
+        <option>\r
+          <name>CCPreprocFile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCPreprocComments</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCPreprocLine</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCListCFile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCListCMnemonics</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCListCMessages</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCListAssFile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCListAssSource</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCEnableRemarks</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCDiagSuppress</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CCDiagRemark</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CCDiagWarning</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CCDiagError</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CCObjPrefix</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CCAllowList</name>\r
+          <version>1</version>\r
+          <state>0000000</state>\r
+        </option>\r
+        <option>\r
+          <name>CCDebugInfo</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IEndianMode</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IProcessor</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IExtraOptionsCheck</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IExtraOptions</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CCLangConformance</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCSignedPlainChar</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRequirePrototypes</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCMultibyteSupport</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCDiagWarnAreErr</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCompilerRuntimeInfo</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IFpuProcessor</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OutputFile</name>\r
+          <state>$FILE_BNAME$.o</state>\r
+        </option>\r
+        <option>\r
+          <name>CCLibConfigHeader</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>PreInclude</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CompilerMisraOverride</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCIncludePath2</name>\r
+          <state>../../Common</state>\r
+        </option>\r
+        <option>\r
+          <name>CCStdIncCheck</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCodeSection</name>\r
+          <state>.text</state>\r
+        </option>\r
+        <option>\r
+          <name>IInterwork2</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IProcessorMode2</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CCOptLevel</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCOptStrategy</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCOptLevelSlave</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CompilerMisraRules98</name>\r
+          <version>0</version>\r
+          <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>\r
+        </option>\r
+        <option>\r
+          <name>CompilerMisraRules04</name>\r
+          <version>0</version>\r
+          <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>\r
+        </option>\r
+        <option>\r
+          <name>CCPosIndRopi</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCPosIndRwpi</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCPosIndNoDynInit</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IccLang</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IccCDialect</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IccAllowVLA</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IccCppDialect</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IccExceptions</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IccRTTI</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IccStaticDestr</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IccCppInlineSemantics</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IccCmsis</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IccFloatSemantics</name>\r
+          <state>0</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>AARM</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>8</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>0</debug>\r
+        <option>\r
+          <name>AObjPrefix</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>AEndian</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>ACaseSensitivity</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>MacroChars</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>AWarnEnable</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>AWarnWhat</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>AWarnOne</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>AWarnRange1</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>AWarnRange2</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>ADebug</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>AltRegisterNames</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>ADefines</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>AList</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>AListHeader</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>AListing</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>Includes</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>MacDefs</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>MacExps</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>MacExec</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OnlyAssed</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>MultiLine</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>PageLengthCheck</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>PageLength</name>\r
+          <state>80</state>\r
+        </option>\r
+        <option>\r
+          <name>TabSpacing</name>\r
+          <state>8</state>\r
+        </option>\r
+        <option>\r
+          <name>AXRef</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>AXRefDefines</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>AXRefInternal</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>AXRefDual</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>AProcessor</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>AFpuProcessor</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>AOutputFile</name>\r
+          <state>$FILE_BNAME$.o</state>\r
+        </option>\r
+        <option>\r
+          <name>AMultibyteSupport</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>ALimitErrorsCheck</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>ALimitErrorsEdit</name>\r
+          <state>100</state>\r
+        </option>\r
+        <option>\r
+          <name>AIgnoreStdInclude</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>AUserIncludes</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>AExtraOptionsCheckV2</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>AExtraOptionsV2</name>\r
+          <state></state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>OBJCOPY</name>\r
+      <archiveVersion>0</archiveVersion>\r
+      <data>\r
+        <version>1</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>0</debug>\r
+        <option>\r
+          <name>OOCOutputFormat</name>\r
+          <version>2</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCOutputOverride</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OOCOutputFile</name>\r
+          <state>RTOSDemo_IAR.srec</state>\r
+        </option>\r
+        <option>\r
+          <name>OOCCommandLineProducer</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OOCObjCopyEnable</name>\r
+          <state>1</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>CUSTOM</name>\r
+      <archiveVersion>3</archiveVersion>\r
+      <data>\r
+        <extensions></extensions>\r
+        <cmdline></cmdline>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>BICOMP</name>\r
+      <archiveVersion>0</archiveVersion>\r
+      <data/>\r
+    </settings>\r
+    <settings>\r
+      <name>BUILDACTION</name>\r
+      <archiveVersion>1</archiveVersion>\r
+      <data>\r
+        <prebuild></prebuild>\r
+        <postbuild></postbuild>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>ILINK</name>\r
+      <archiveVersion>0</archiveVersion>\r
+      <data>\r
+        <version>13</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>0</debug>\r
+        <option>\r
+          <name>IlinkLibIOConfig</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>XLinkMisraHandler</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkInputFileSlave</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkOutputFile</name>\r
+          <state>RTOSDemo_IAR.out</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkDebugInfoEnable</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkKeepSymbols</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkRawBinaryFile</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkRawBinarySymbol</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkRawBinarySegment</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkRawBinaryAlign</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkDefines</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkConfigDefines</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkMapFile</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkLogFile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkLogInitialization</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkLogModule</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkLogSection</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkLogVeneer</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkIcfOverride</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkIcfFile</name>\r
+          <state>$PROJ_DIR$\config\mb9bf506.icf</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkIcfFileSlave</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkEnableRemarks</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkSuppressDiags</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkTreatAsRem</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkTreatAsWarn</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkTreatAsErr</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkWarningsAreErrors</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkUseExtraOptions</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkExtraOptions</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkLowLevelInterfaceSlave</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkAutoLibEnable</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkAdditionalLibs</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkOverrideProgramEntryLabel</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkProgramEntryLabelSelect</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkProgramEntryLabel</name>\r
+          <state>__iar_program_start</state>\r
+        </option>\r
+        <option>\r
+          <name>DoFill</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>FillerByte</name>\r
+          <state>0xFF</state>\r
+        </option>\r
+        <option>\r
+          <name>FillerStart</name>\r
+          <state>0x0</state>\r
+        </option>\r
+        <option>\r
+          <name>FillerEnd</name>\r
+          <state>0x0</state>\r
+        </option>\r
+        <option>\r
+          <name>CrcSize</name>\r
+          <version>0</version>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CrcAlign</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CrcAlgo</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CrcPoly</name>\r
+          <state>0x11021</state>\r
+        </option>\r
+        <option>\r
+          <name>CrcCompl</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CrcBitOrder</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CrcInitialValue</name>\r
+          <state>0x0</state>\r
+        </option>\r
+        <option>\r
+          <name>DoCrc</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkBE8Slave</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkBufferedTerminalOutput</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkStdoutInterfaceSlave</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CrcFullSize</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkIElfToolPostProcess</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkLogAutoLibSelect</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkLogRedirSymbols</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkLogUnusedFragments</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkCrcReverseByteOrder</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkCrcUseAsInput</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkOptInline</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkOptExceptionsAllow</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkOptExceptionsForce</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkCmsis</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkOptMergeDuplSections</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkOptUseVfe</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkOptForceVfe</name>\r
+          <state>0</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>IARCHIVE</name>\r
+      <archiveVersion>0</archiveVersion>\r
+      <data>\r
+        <version>0</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>0</debug>\r
+        <option>\r
+          <name>IarchiveInputs</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IarchiveOverride</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IarchiveOutput</name>\r
+          <state>###Unitialized###</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>BILINK</name>\r
+      <archiveVersion>0</archiveVersion>\r
+      <data/>\r
+    </settings>\r
+  </configuration>\r
+  <group>\r
+    <name>FreeRTOS_Source</name>\r
+    <group>\r
+      <name>Portable</name>\r
+      <file>\r
+        <name>$PROJ_DIR$\..\..\Source\portable\MemMang\heap_2.c</name>\r
+      </file>\r
+      <file>\r
+        <name>$PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM3\port.c</name>\r
+      </file>\r
+      <file>\r
+        <name>$PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM3\portasm.s</name>\r
+      </file>\r
+    </group>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\..\Source\list.c</name>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\..\Source\queue.c</name>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\..\Source\tasks.c</name>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\..\Source\timers.c</name>\r
+    </file>\r
+  </group>\r
+  <group>\r
+    <name>Fujitsu_Source</name>\r
+    <file>\r
+      <name>$PROJ_DIR$\Fujitu_source\core_cm3.c</name>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\Fujitu_source\startup_iar\startup_mb9bf50x.s</name>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\Fujitu_source\system_mb9bf50x.c</name>\r
+    </file>\r
+  </group>\r
+  <file>\r
+    <name>$PROJ_DIR$\main_blinky.c</name>\r
+  </file>\r
+</project>\r
+\r
+\r

diff --git a/Demo/CORTEX_MB9B500_IAR_Keil/RTOSDemo_IAR.eww b/Demo/CORTEX_MB9B500_IAR_Keil/RTOSDemo_IAR.eww
new file mode 100644 (file)
index 0000000..f4971a4
--- /dev/null
+++ b/Demo/CORTEX_MB9B500_IAR_Keil/RTOSDemo_IAR.eww
@@ -0,0 +1,10 @@
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<workspace>\r
+  <project>\r
+    <path>$WS_DIR$\RTOSDemo_IAR.ewp</path>\r
+  </project>\r
+  <batchBuild/>\r
+</workspace>\r
+\r
+\r

diff --git a/Demo/CORTEX_MB9B500_IAR_Keil/main_blinky.c b/Demo/CORTEX_MB9B500_IAR_Keil/main_blinky.c
new file mode 100644 (file)
index 0000000..448ca61
--- /dev/null
+++ b/Demo/CORTEX_MB9B500_IAR_Keil/main_blinky.c
@@ -0,0 +1,404 @@
+/*\r
+    FreeRTOS V7.0.0 - Copyright (C) 2011 Real Time Engineers Ltd.\r
+\r
+\r
+       FreeRTOS supports many tools and architectures. V7.0.0 is sponsored by:\r
+       Atollic AB - Atollic provides professional embedded systems development\r
+       tools for C/C++ development, code analysis and test automation.\r
+       See http://www.atollic.com\r
+\r
+\r
+    ***************************************************************************\r
+     *                                                                       *\r
+     *    FreeRTOS tutorial books are available in pdf and paperback.        *\r
+     *    Complete, revised, and edited pdf reference manuals are also       *\r
+     *    available.                                                         *\r
+     *                                                                       *\r
+     *    Purchasing FreeRTOS documentation will not only help you, by       *\r
+     *    ensuring you get running as quickly as possible and with an        *\r
+     *    in-depth knowledge of how to use FreeRTOS, it will also help       *\r
+     *    the FreeRTOS project to continue with its mission of providing     *\r
+     *    professional grade, cross platform, de facto standard solutions    *\r
+     *    for microcontrollers - completely free of charge!                  *\r
+     *                                                                       *\r
+     *    >>> See http://www.FreeRTOS.org/Documentation for details. <<<     *\r
+     *                                                                       *\r
+     *    Thank you for using FreeRTOS, and thank you for your support!      *\r
+     *                                                                       *\r
+    ***************************************************************************\r
+\r
+\r
+    This file is part of the FreeRTOS distribution.\r
+\r
+    FreeRTOS is free software; you can redistribute it and/or modify it under\r
+    the terms of the GNU General Public License (version 2) as published by the\r
+    Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+    >>>NOTE<<< The modification to the GPL is included to allow you to\r
+    distribute a combined work that includes FreeRTOS without being obliged to\r
+    provide the source code for proprietary components outside of the FreeRTOS\r
+    kernel.  FreeRTOS is distributed in the hope that it will be useful, but\r
+    WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\r
+    more details. You should have received a copy of the GNU General Public\r
+    License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+    can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+    by writing to Richard Barry, contact details for whom are available on the\r
+    FreeRTOS WEB site.\r
+\r
+    1 tab == 4 spaces!\r
+\r
+    http://www.FreeRTOS.org - Documentation, latest information, license and\r
+    contact details.\r
+\r
+    http://www.SafeRTOS.com - A version that is certified for use in safety\r
+    critical systems.\r
+\r
+    http://www.OpenRTOS.com - Commercial support, development, porting,\r
+    licensing and training services.\r
+*/\r
+\r
+/*\r
+ * main-blinky.c is included when the "Blinky" build configuration is used.\r
+ * main-full.c is included when the "Full" build configuration is used.\r
+ *\r
+ * main-blinky.c (this file) defines a very simple demo that creates two tasks,\r
+ * one queue, and one timer.  It also demonstrates how Cortex-M3 interrupts can\r
+ * interact with FreeRTOS tasks/timers.\r
+ *\r
+ * This simple demo project runs on the SmartFusion A2F-EVAL-KIT evaluation\r
+ * board, which is populated with an A2F200M3F SmartFusion mixed signal FPGA.\r
+ * The A2F200M3F incorporates a Cortex-M3 microcontroller.\r
+ *\r
+ * The idle hook function:\r
+ * The idle hook function demonstrates how to query the amount of FreeRTOS heap\r
+ * space that is remaining (see vApplicationIdleHook() defined in this file).\r
+ *\r
+ * The main() Function:\r
+ * main() creates one software timer, one queue, and two tasks.  It then starts\r
+ * the scheduler.\r
+ *\r
+ * The Queue Send Task:\r
+ * The queue send task is implemented by the prvQueueSendTask() function in\r
+ * this file.  prvQueueSendTask() sits in a loop that causes it to repeatedly\r
+ * block for 200 milliseconds, before sending the value 100 to the queue that\r
+ * was created within main().  Once the value is sent, the task loops back\r
+ * around to block for another 200 milliseconds.\r
+ *\r
+ * The Queue Receive Task:\r
+ * The queue receive task is implemented by the prvQueueReceiveTask() function\r
+ * in this file.  prvQueueReceiveTask() sits in a loop that causes it to\r
+ * repeatedly attempt to read data from the queue that was created within\r
+ * main().  When data is received, the task checks the value of the data, and\r
+ * if the value equals the expected 100, toggles the green LED.  The 'block\r
+ * time' parameter passed to the queue receive function specifies that the task\r
+ * should be held in the Blocked state indefinitely to wait for data to be\r
+ * available on the queue.  The queue receive task will only leave the Blocked\r
+ * state when the queue send task writes to the queue.  As the queue send task\r
+ * writes to the queue every 200 milliseconds, the queue receive task leaves\r
+ * the Blocked state every 200 milliseconds, and therefore toggles the LED\r
+ * every 200 milliseconds.\r
+ *\r
+ * The LED Software Timer and the Button Interrupt:\r
+ * The user button SW1 is configured to generate an interrupt each time it is\r
+ * pressed.  The interrupt service routine switches an LED on, and resets the\r
+ * LED software timer.  The LED timer has a 5000 millisecond (5 second) period,\r
+ * and uses a callback function that is defined to just turn the LED off again.\r
+ * Therefore, pressing the user button will turn the LED on, and the LED will\r
+ * remain on until a full five seconds pass without the button being pressed.\r
+ */\r
+\r
+/* Kernel includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "queue.h"\r
+#include "timers.h"\r
+\r
+/* Fujitsu drivers/libraries. */\r
+#include "mb9bf506n.h"\r
+#include "system_mb9bf50x.h"\r
+\r
+\r
+/* Priorities at which the tasks are created. */\r
+#define mainQUEUE_RECEIVE_TASK_PRIORITY                ( tskIDLE_PRIORITY + 2 )\r
+#define        mainQUEUE_SEND_TASK_PRIORITY            ( tskIDLE_PRIORITY + 1 )\r
+\r
+/* The rate at which data is sent to the queue, specified in milliseconds, and\r
+converted to ticks using the portTICK_RATE_MS constant. */\r
+#define mainQUEUE_SEND_FREQUENCY_MS                    ( 200 / portTICK_RATE_MS )\r
+\r
+/* The number of items the queue can hold.  This is 1 as the receive task\r
+will remove items as they are added, meaning the send task should always find\r
+the queue empty. */\r
+#define mainQUEUE_LENGTH                                       ( 1 )\r
+\r
+/* The LED toggle by the queue receive task. */\r
+#define mainTASK_CONTROLLED_LED                                0x0100UL\r
+\r
+/* The LED turned on by the button interrupt, and turned off by the LED timer. */\r
+#define mainTIMER_CONTROLLED_LED                       0x0200UL\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Setup the NVIC, LED outputs, and button inputs.\r
+ */\r
+static void prvSetupHardware( void );\r
+\r
+/*\r
+ * The tasks as described in the comments at the top of this file.\r
+ */\r
+static void prvQueueReceiveTask( void *pvParameters );\r
+static void prvQueueSendTask( void *pvParameters );\r
+\r
+/*\r
+ * The LED timer callback function.  This does nothing but switch off the\r
+ * LED defined by the mainTIMER_CONTROLLED_LED constant.\r
+ */\r
+static void vLEDTimerCallback( xTimerHandle xTimer );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The queue used by both tasks. */\r
+static xQueueHandle xQueue = NULL;\r
+\r
+/* The LED software timer.  This uses vLEDTimerCallback() as its callback\r
+function. */\r
+static xTimerHandle xLEDTimer = NULL;\r
+\r
+/* Maintains the current LED output state. */\r
+static volatile unsigned long ulGPIOState = 0xffffUL;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+int main(void)\r
+{\r
+       /* Configure the NVIC, LED outputs and button inputs. */\r
+       prvSetupHardware();\r
+\r
+       /* Create the queue. */\r
+       xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( unsigned long ) );\r
+\r
+       if( xQueue != NULL )\r
+       {\r
+               /* Start the two tasks as described in the comments at the top of this\r
+               file. */\r
+               xTaskCreate( prvQueueReceiveTask, ( signed char * ) "Rx", configMINIMAL_STACK_SIZE, NULL, mainQUEUE_RECEIVE_TASK_PRIORITY, NULL );\r
+               xTaskCreate( prvQueueSendTask, ( signed char * ) "TX", configMINIMAL_STACK_SIZE, NULL, mainQUEUE_SEND_TASK_PRIORITY, NULL );\r
+\r
+               /* Create the software timer that is responsible for turning off the LED\r
+               if the button is not pushed within 5000ms, as described at the top of\r
+               this file. */\r
+               xLEDTimer = xTimerCreate(       ( const signed char * ) "LEDTimer", /* A text name, purely to help debugging. */\r
+                                                                       ( 5000 / portTICK_RATE_MS ),            /* The timer period, in this case 5000ms (5s). */\r
+                                                                       pdFALSE,                                                        /* This is a one shot timer, so xAutoReload is set to pdFALSE. */\r
+                                                                       ( void * ) 0,                                           /* The ID is not used, so can be set to anything. */\r
+                                                                       vLEDTimerCallback                                       /* The callback function that switches the LED off. */\r
+                                                               );\r
+\r
+               /* Start the tasks and timer running. */\r
+               vTaskStartScheduler();\r
+       }\r
+\r
+       /* If all is well, the scheduler will now be running, and the following line\r
+       will never be reached.  If the following line does execute, then there was\r
+       insufficient FreeRTOS heap memory available for the idle and/or timer tasks\r
+       to be created.  See the memory management section on the FreeRTOS web site\r
+       for more details. */\r
+       for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void vLEDTimerCallback( xTimerHandle xTimer )\r
+{\r
+       /* The timer has expired - so no button pushes have occurred in the last\r
+       five seconds - turn the LED off.  NOTE - accessing the LED port should use\r
+       a critical section because it is accessed from multiple tasks, and the\r
+       button interrupt - in this trivial case, for simplicity, the critical\r
+       section is omitted. */\r
+       ulGPIOState |= mainTIMER_CONTROLLED_LED;\r
+       FM3_GPIO->PDOR3 = ulGPIOState;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The ISR executed when the user button is pushed. */\r
+void INT0_7_Handler( void )\r
+{\r
+portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE;\r
+\r
+       /* The button was pushed, so ensure the LED is on before resetting the\r
+       LED timer.  The LED timer will turn the LED off if the button is not\r
+       pushed within 5000ms. */\r
+       ulGPIOState &= ~mainTIMER_CONTROLLED_LED;\r
+       FM3_GPIO->PDOR3 = ulGPIOState;\r
+\r
+       /* This interrupt safe FreeRTOS function can be called from this interrupt\r
+       because the interrupt priority is below the\r
+       configMAX_SYSCALL_INTERRUPT_PRIORITY setting in FreeRTOSConfig.h. */\r
+       xTimerResetFromISR( xLEDTimer, &xHigherPriorityTaskWoken );\r
+\r
+       /* Clear the interrupt before leaving. */\r
+       FM3_EXTI->EICL  = 0x0000;\r
+\r
+       /* If calling xTimerResetFromISR() caused a task (in this case the timer\r
+       service/daemon task) to unblock, and the unblocked task has a priority\r
+       higher than or equal to the task that was interrupted, then\r
+       xHigherPriorityTaskWoken will now be set to pdTRUE, and calling\r
+       portEND_SWITCHING_ISR() will ensure the unblocked task runs next. */\r
+       portEND_SWITCHING_ISR( xHigherPriorityTaskWoken );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvQueueSendTask( void *pvParameters )\r
+{\r
+portTickType xNextWakeTime;\r
+const unsigned long ulValueToSend = 100UL;\r
+\r
+       /* Initialise xNextWakeTime - this only needs to be done once. */\r
+       xNextWakeTime = xTaskGetTickCount();\r
+\r
+       for( ;; )\r
+       {\r
+               /* Place this task in the blocked state until it is time to run again.\r
+               The block time is specified in ticks, the constant used converts ticks\r
+               to ms.  While in the Blocked state this task will not consume any CPU\r
+               time. */\r
+               vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS );\r
+\r
+               /* Send to the queue - causing the queue receive task to unblock and\r
+               toggle an LED.  0 is used as the block time so the sending operation\r
+               will not block - it shouldn't need to block as the queue should always\r
+               be empty at this point in the code. */\r
+               xQueueSend( xQueue, &ulValueToSend, 0 );\r
+       }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvQueueReceiveTask( void *pvParameters )\r
+{\r
+unsigned long ulReceivedValue;\r
+\r
+       for( ;; )\r
+       {\r
+               /* Wait until something arrives in the queue - this task will block\r
+               indefinitely provided INCLUDE_vTaskSuspend is set to 1 in\r
+               FreeRTOSConfig.h. */\r
+               xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY );\r
+\r
+               /*  To get here something must have been received from the queue, but\r
+               is it the expected value?  If it is, toggle the green LED. */\r
+               if( ulReceivedValue == 100UL )\r
+               {\r
+                       /* NOTE - accessing the LED port should use a critical section\r
+                       because it is accessed from multiple tasks, and the button interrupt\r
+                       - in this trivial case, for simplicity, the critical section is\r
+                       omitted. */\r
+                       if( ( ulGPIOState & mainTASK_CONTROLLED_LED ) != 0 )\r
+                       {\r
+                               ulGPIOState &= ~mainTASK_CONTROLLED_LED;\r
+                       }\r
+                       else\r
+                       {\r
+                               ulGPIOState |= mainTASK_CONTROLLED_LED;\r
+                       }\r
+                       FM3_GPIO->PDOR3 = ulGPIOState;\r
+               }\r
+       }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSetupHardware( void )\r
+{\r
+       SystemInit();\r
+       SystemCoreClockUpdate();\r
+       \r
+       /* No analog inputs. */\r
+       FM3_GPIO->ADE  = 0x00FF;\r
+       \r
+       /* LED seg1 to GPIO output (P18->P1F). */\r
+       FM3_GPIO->DDR1 = 0xFF00;\r
+       FM3_GPIO->PFR1 = 0x0000;\r
+       \r
+       /* LED seg2 to GPIO output (P30->P3F). */\r
+       FM3_GPIO->DDR3 = 0xFF00;\r
+       FM3_GPIO->PFR3 = 0x0000;\r
+       \r
+       /* Start with all LEDs off. */\r
+       FM3_GPIO->PDOR3 = ulGPIOState;\r
+       FM3_GPIO->PDOR1 = ulGPIOState;\r
+       \r
+       /* Set the switches to input (P18->P1F). */\r
+       FM3_GPIO->DDR5 = 0x0000;\r
+       FM3_GPIO->PFR5 = 0x0000;\r
+\r
+       \r
+       /* setting INT02_1 */\r
+       /* MB9BF500(120pin) pin63->P11,AN01,SIN1_1,INT02_1,RX1_2 */\r
+//     GPIO->EPFR06 = 0x00000020;                      /* bit5,4:EINT02S=0b10 EINT-ch2 use INT02_1 */\r
+       \r
+//     GPIO->ADE   &= 0xFFFD;                          /* bit2:ADE2=0b0 AN01pin use digital input/output pin */\r
+       \r
+//     GPIO->PFR1  |= 0x0002;                          /* bit2:PFR1_2=0b1 P11pin use peripheral port */\r
+                                                                               /* I/O port setting end */\r
+       \r
+       FM3_EXTI->ENIR  = 0x0000;                               /* INT interrupt disable */\r
+       FM3_EXTI->ELVR  = 0x0030;                               /* bit5,4:LB2,LA2=0b11 INT2 low level edge */\r
+\r
+       FM3_EXTI->EICL  = 0x0000;                               /* bit2:ECL=0b0 INT2 interrupt request clear */\r
+\r
+//     FM3_EXTI->ENIR  = 0x0004;                               /* bit2:EN2=0b1 enable INT2 */\r
+       FM3_EXTI->ENIR  = 0x0001;                               /* Enable INT0. */\r
+       \r
+       \r
+       /* Setup the GPIO and the NVIC for the switch used in this simple demo. */\r
+       NVIC_SetPriority( EXINT0_7_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );\r
+    NVIC_EnableIRQ( EXINT0_7_IRQn );\r
+//    MSS_GPIO_config( MSS_GPIO_8, MSS_GPIO_INPUT_MODE | MSS_GPIO_IRQ_EDGE_NEGATIVE );\r
+//    MSS_GPIO_enable_irq( MSS_GPIO_8 );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationMallocFailedHook( void )\r
+{\r
+       /* Called if a call to pvPortMalloc() fails because there is insufficient\r
+       free memory available in the FreeRTOS heap.  pvPortMalloc() is called\r
+       internally by FreeRTOS API functions that create tasks, queues, software\r
+       timers, and semaphores.  The size of the FreeRTOS heap is set by the\r
+       configTOTAL_HEAP_SIZE configuration constant in FreeRTOSConfig.h. */\r
+       for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationStackOverflowHook( xTaskHandle *pxTask, signed char *pcTaskName )\r
+{\r
+       ( void ) pcTaskName;\r
+       ( void ) pxTask;\r
+\r
+       /* Run time stack overflow checking is performed if\r
+       configconfigCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2.  This hook\r
+       function is called if a stack overflow is detected. */\r
+       for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationIdleHook( void )\r
+{\r
+volatile size_t xFreeStackSpace;\r
+\r
+       /* This function is called on each cycle of the idle task.  In this case it\r
+       does nothing useful, other than report the amout of FreeRTOS heap that\r
+       remains unallocated. */\r
+       xFreeStackSpace = xPortGetFreeHeapSize();\r
+\r
+       if( xFreeStackSpace > 100 )\r
+       {\r
+               /* By now, the kernel has allocated everything it is going to, so\r
+               if there is a lot of heap remaining unallocated then\r
+               the value of configTOTAL_HEAP_SIZE in FreeRTOSConfig.h can be\r
+               reduced accordingly. */\r
+       }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+\r
+\r
+\r