Add more "memory" clobbers into asm code of GCC/ARM_CRx_No_GIC port to make it robust...

git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2499 1d2547de-c912-0410-9cb9-b8ca96c0e9e2

diff --git a/FreeRTOS/Source/portable/GCC/ARM_CRx_No_GIC/port.c b/FreeRTOS/Source/portable/GCC/ARM_CRx_No_GIC/port.c
index b8399c56353ed01a37e33af16cf965bd7fc69208..01bce44bb8d93c49afa089c68fc3bde356ad38b2 100644 (file)
--- a/FreeRTOS/Source/portable/GCC/ARM_CRx_No_GIC/port.c
+++ b/FreeRTOS/Source/portable/GCC/ARM_CRx_No_GIC/port.c
@@ -254,7 +254,7 @@ uint32_t ulAPSR;
 \r
        /* Only continue if the CPU is not in User mode.  The CPU must be in a\r
        Privileged mode for the scheduler to start. */\r
-       __asm volatile ( "MRS %0, APSR" : "=r" ( ulAPSR ) );\r
+       __asm volatile ( "MRS %0, APSR" : "=r" ( ulAPSR ) :: "memory" );\r
        ulAPSR &= portAPSR_MODE_BITS_MASK;\r
        configASSERT( ulAPSR != portAPSR_USER_MODE );\r
 \r
@@ -354,7 +354,7 @@ uint32_t ulInitialFPSCR = 0;
        ulPortTaskHasFPUContext = pdTRUE;\r
 \r
        /* Initialise the floating point status register. */\r
-       __asm volatile ( "FMXR  FPSCR, %0" :: "r" (ulInitialFPSCR) );\r
+       __asm volatile ( "FMXR  FPSCR, %0" :: "r" (ulInitialFPSCR) : "memory" );\r
 }\r
 /*-----------------------------------------------------------*/\r
 \r

diff --git a/FreeRTOS/Source/portable/GCC/ARM_CRx_No_GIC/portmacro.h b/FreeRTOS/Source/portable/GCC/ARM_CRx_No_GIC/portmacro.h
index 5fe5011df27f5f946946be48f34d3873ec165a98..1801f338db5a0cfe0c8b6a415897d98634792b59 100644 (file)
--- a/FreeRTOS/Source/portable/GCC/ARM_CRx_No_GIC/portmacro.h
+++ b/FreeRTOS/Source/portable/GCC/ARM_CRx_No_GIC/portmacro.h
@@ -128,7 +128,7 @@ extern volatile uint32_t ulPortYieldRequired;       \
 \r
 #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )\r
 #define portYIELD() __asm volatile ( "SWI 0            \n"                             \\r
-                                                                        "ISB             " );\r
+                                                                        "ISB             " ::: "memory" );\r
 \r
 \r
 /*-----------------------------------------------------------\r
@@ -148,16 +148,16 @@ extern void vPortInstallFreeRTOSVectorTable( void );
 globally enable and disable interrupts. */\r
 #define portENTER_CRITICAL()           vPortEnterCritical();\r
 #define portEXIT_CRITICAL()                    vPortExitCritical();\r
-#define portENABLE_INTERRUPTS()                __asm volatile ( "CPSIE i       \n"     );\r
+#define portENABLE_INTERRUPTS()                __asm volatile ( "CPSIE i       \n"     ::: "memory" );\r
 #define portDISABLE_INTERRUPTS()       __asm volatile ( "CPSID i       \n"             \\r
                                                                                                         "DSB           \n"             \\r
-                                                                                                        "ISB             " );\r
+                                                                                                        "ISB             " ::: "memory" );\r
 \r
 __attribute__( ( always_inline ) ) static __inline uint32_t portINLINE_SET_INTERRUPT_MASK_FROM_ISR( void )\r
 {\r
 volatile uint32_t ulCPSR;\r
 \r
-       __asm volatile ( "MRS %0, CPSR" : "=r" (ulCPSR) );\r
+       __asm volatile ( "MRS %0, CPSR" : "=r" (ulCPSR) :: "memory" );\r
        ulCPSR &= portINTERRUPT_ENABLE_BIT;\r
        portDISABLE_INTERRUPTS();\r
        return ulCPSR;\r