mips: optimize CP0 read/write code

MIPS32_PRACC_BASE_ADDR is defined as 0xFF200000. Now is
possible to load the base address with a lui instruction and
only one pracc access.
Offsets to the pracc code addresses are defined to simplify the code
and probably make it a bit more readable or self-explained.

Change-Id: I853dd2d7fad52745931cc6e6be68c0ae156d897e
Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es>
Reviewed-on: http://openocd.zylin.com/951
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Tested-by: jenkins

diff --git a/src/target/mips32_pracc.c b/src/target/mips32_pracc.c
index bae436784af3253a64c7520e2d3b800b6db3b2cf..0aa624c967c2d506f00f0b093a523030bbb2c5a7 100644 (file)
--- a/src/target/mips32_pracc.c
+++ b/src/target/mips32_pracc.c
@@ -568,26 +568,20 @@ int mips32_cp0_read(struct mips_ejtag *ejtag_info, uint32_t *val, uint32_t cp0_r
 {
        /**
         * Do not make this code static, but regenerate it every time,
-        * as 5th element has to be changed to add parameters
+        * as 3th element has to be changed to add parameters
         */
        uint32_t code[] = {
-                                                                                                                       /* start: */
-               MIPS32_MTC0(15, 31, 0),                                                         /* move $15 to COP0 DeSave */
-               MIPS32_LUI(15, UPPER16(MIPS32_PRACC_STACK)),            /* $15 = MIPS32_PRACC_STACK */
-               MIPS32_ORI(15, 15, LOWER16(MIPS32_PRACC_STACK)),
-               MIPS32_SW(8, 0, 15),                                                            /* sw $8,($15) */
-               MIPS32_SW(9, 0, 15),                                                            /* sw $9,($15) */
-
-               /* 5 */ MIPS32_MFC0(8, 0, 0),                                           /* move COP0 [cp0_reg select] to $8 */
+                                                                                                               /* start: */
+               MIPS32_MTC0(15, 31, 0),                                                 /* move $15 to COP0 DeSave */
+               MIPS32_LUI(15, PRACC_UPPER_BASE_ADDR),                                  /* $15 = MIPS32_PRACC_BASE_ADDR */
+               MIPS32_SW(8, PRACC_STACK_OFFSET, 15),                                   /* sw $8,PRACC_STACK_OFFSET($15) */
 
-               MIPS32_LUI(9, UPPER16(MIPS32_PRACC_PARAM_OUT)),         /* $11 = MIPS32_PRACC_PARAM_OUT */
-               MIPS32_ORI(9, 9, LOWER16(MIPS32_PRACC_PARAM_OUT)),
-               MIPS32_SW(8, 0, 9),                                                                     /* sw $8,0($9) */
+               /* 3 */ MIPS32_MFC0(8, 0, 0),                                           /* move COP0 [cp0_reg select] to $8 */
+               MIPS32_SW(8, PRACC_OUT_OFFSET, 15),                                     /* sw $8,PRACC_OUT_OFFSET($15) */
 
-               MIPS32_LW(9, 0, 15),                                                            /* lw $9,($15) */
-               MIPS32_LW(8, 0, 15),                                                            /* lw $8,($15) */
-               MIPS32_B(NEG16(12)),                                                            /* b start */
-               MIPS32_MFC0(15, 31, 0),                                                         /* move COP0 DeSave to $15 */
+               MIPS32_LW(8, PRACC_STACK_OFFSET, 15),                                   /* lw $8,PRACC_STACK_OFFSET($15) */
+               MIPS32_B(NEG16(7)),                                                     /* b start */
+               MIPS32_MFC0(15, 31, 0),                                                 /* move COP0 DeSave to $15 */
        };
 
        /**
@@ -604,56 +598,32 @@ int mips32_cp0_read(struct mips_ejtag *ejtag_info, uint32_t *val, uint32_t cp0_r
         * MIPS32_MTC0 is implemented via MIPS32_R_INST macro.
         * In order to insert our parameters, we must change rd and funct fields.
         */
-       code[5] |= (cp0_reg << 11) | cp0_sel;  /* change rd and funct of MIPS32_R_INST macro */
-
-       /* TODO remove array */
-       uint32_t *param_out = val;
-       int retval;
-
-       retval = mips32_pracc_exec(ejtag_info, ARRAY_SIZE(code), code, 0, NULL, 1, param_out, 1);
+       code[3] |= (cp0_reg << 11) | cp0_sel;  /* change rd and funct of MIPS32_R_INST macro */
 
-       return retval;
+       return mips32_pracc_exec(ejtag_info, ARRAY_SIZE(code), code, 0, NULL, 1, val, 1);
 }
 
-int mips32_cp0_write(struct mips_ejtag *ejtag_info,
-               uint32_t val, uint32_t cp0_reg, uint32_t cp0_sel)
+int mips32_cp0_write(struct mips_ejtag *ejtag_info, uint32_t val, uint32_t cp0_reg, uint32_t cp0_sel)
 {
        uint32_t code[] = {
                                                                                                                        /* start: */
-               MIPS32_MTC0(15, 31, 0),                                                         /* move $15 to COP0 DeSave */
-               MIPS32_LUI(15, UPPER16(MIPS32_PRACC_STACK)),            /* $15 = MIPS32_PRACC_STACK */
-               MIPS32_ORI(15, 15, LOWER16(MIPS32_PRACC_STACK)),
-               MIPS32_SW(8, 0, 15),                                                            /* sw $8,($15) */
-               MIPS32_SW(9, 0, 15),                                                            /* sw $9,($15) */
-
-               MIPS32_LUI(8, UPPER16(MIPS32_PRACC_PARAM_IN)),          /* $8 = MIPS32_PRACC_PARAM_IN */
-               MIPS32_ORI(8, 8, LOWER16(MIPS32_PRACC_PARAM_IN)),
-               MIPS32_LW(9, 0, 8),                                                                     /* Load write val to $9 */
+               MIPS32_MTC0(15, 31, 0),                                                 /* move $15 to COP0 DeSave */
+               MIPS32_LUI(15, UPPER16(val)),                                           /* Load val to $15 */
+               MIPS32_ORI(15, 15, LOWER16(val)),
 
-               /* 8 */ MIPS32_MTC0(9, 0, 0),                                           /* move $9 to COP0 [cp0_reg select] */
+               /* 3 */ MIPS32_MTC0(15, 0, 0),                                          /* move $15 to COP0 [cp0_reg select] */
 
-               MIPS32_LW(9, 0, 15),                                                            /* lw $9,($15) */
-               MIPS32_LW(8, 0, 15),                                                            /* lw $8,($15) */
-               MIPS32_B(NEG16(12)),                                                            /* b start */
-               MIPS32_MFC0(15, 31, 0),                                                         /* move COP0 DeSave to $15 */
+               MIPS32_B(NEG16(5)),                                                     /* b start */
+               MIPS32_MFC0(15, 31, 0),                                                 /* move COP0 DeSave to $15 */
        };
 
        /**
         * Note that MIPS32_MTC0 macro is implemented via MIPS32_R_INST macro.
         * In order to insert our parameters, we must change rd and funct fields.
         */
-       code[8] |= (cp0_reg << 11) | cp0_sel;  /* change rd and funct fields of MIPS32_R_INST macro */
-
-       /* TODO remove array */
-       uint32_t *param_in = malloc(1 * sizeof(uint32_t));
-       int retval;
-       param_in[0] = val;
+       code[3] |= (cp0_reg << 11) | cp0_sel;  /* change rd and funct fields of MIPS32_R_INST macro */
 
-       retval = mips32_pracc_exec(ejtag_info, ARRAY_SIZE(code), code, 1, param_in, 0, NULL, 1);
-
-       free(param_in);
-
-       return retval;
+       return mips32_pracc_exec(ejtag_info, ARRAY_SIZE(code), code, 0, NULL, 0, NULL, 1);
 }
 
 /**

diff --git a/src/target/mips32_pracc.h b/src/target/mips32_pracc.h
index c200e93d51d7e512366c97c609805685a828733f..8f208f5fda54fb19aaff6d030b5f988ed705e8fe 100644 (file)
--- a/src/target/mips32_pracc.h
+++ b/src/target/mips32_pracc.h
@@ -30,6 +30,7 @@
 #include <target/mips_ejtag.h>
 
 #define MIPS32_PRACC_FASTDATA_AREA             0xFF200000
+#define MIPS32_PRACC_BASE_ADDR                 0xFF200000
 #define MIPS32_PRACC_FASTDATA_SIZE             16
 #define MIPS32_PRACC_TEXT                              0xFF200200
 #define MIPS32_PRACC_STACK                             0xFF204000
@@ -38,6 +39,12 @@
 #define MIPS32_PRACC_PARAM_OUT                 (MIPS32_PRACC_PARAM_IN + MIPS32_PRACC_PARAM_IN_SIZE)
 #define MIPS32_PRACC_PARAM_OUT_SIZE            0x1000
 
+#define PRACC_UPPER_BASE_ADDR                  (MIPS32_PRACC_BASE_ADDR >> 16)
+#define PRACC_TEXT_OFFSET                      (MIPS32_PRACC_TEXT - MIPS32_PRACC_BASE_ADDR)
+#define PRACC_IN_OFFSET                                (MIPS32_PRACC_PARAM_IN - MIPS32_PRACC_BASE_ADDR)
+#define PRACC_OUT_OFFSET                       (MIPS32_PRACC_PARAM_OUT - MIPS32_PRACC_BASE_ADDR)
+#define PRACC_STACK_OFFSET                     (MIPS32_PRACC_STACK - MIPS32_PRACC_BASE_ADDR)
+
 #define MIPS32_FASTDATA_HANDLER_SIZE   0x80
 #define UPPER16(uint32_t)                              (uint32_t >> 16)
 #define LOWER16(uint32_t)                              (uint32_t & 0xFFFF)