Merge git://git.denx.de/u-boot-sunxi

diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index 6e13ee32c14d7715739f2dcbdbbff4c54b839862..dcacdf3e626db2fc454a708a2f35d8910cf8556c 100644 (file)
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -217,6 +217,8 @@ int board_init(void)
        satapwr_pin = sunxi_name_to_gpio(CONFIG_SATAPWR);
        gpio_request(satapwr_pin, "satapwr");
        gpio_direction_output(satapwr_pin, 1);
+       /* Give attached sata device time to power-up to avoid link timeouts */
+       mdelay(500);
 #endif
 #ifdef CONFIG_MACPWR
        macpwr_pin = sunxi_name_to_gpio(CONFIG_MACPWR);

diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c
index 09bbb2cdb5cad47967ffb5ca4f9f9f871349fc54..3ccc6b0bb612de20e6973979c28bb7d981cbc2df 100644 (file)
--- a/drivers/net/sun8i_emac.c
+++ b/drivers/net/sun8i_emac.c
@@ -604,6 +604,8 @@ static void sun8i_emac_board_setup(struct emac_eth_dev *priv)
 {
        struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 
+#ifdef CONFIG_MACH_SUNXI_H3_H5
+       /* Only H3/H5 have clock controls for internal EPHY */
        if (priv->use_internal_phy) {
                /* Set clock gating for ephy */
                setbits_le32(&ccm->bus_gate4, BIT(AHB_GATE_OFFSET_EPHY));
@@ -611,6 +613,7 @@ static void sun8i_emac_board_setup(struct emac_eth_dev *priv)
                /* Deassert EPHY */
                setbits_le32(&ccm->ahb_reset2_cfg, BIT(AHB_RESET_OFFSET_EPHY));
        }
+#endif
 
        /* Set clock gating for emac */
        setbits_le32(&ccm->ahb_gate0, BIT(AHB_GATE_OFFSET_GMAC));