#define configUSE_TICK_HOOK 0\r
#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 64000000 )\r
#define configTICK_RATE_HZ ( ( portTickType ) 1000 )\r
-#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 90 )\r
-#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 24000 ) )\r
+#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 100 )\r
+#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 30000 ) )\r
#define configMAX_TASK_NAME_LEN ( 12 )\r
#define configUSE_TRACE_FACILITY 1\r
#define configUSE_16_BIT_TICKS 0\r
const unsigned portSHORT usCompareMatchValue = ( ( configCPU_CLOCK_HZ / portPRESCALE_VALUE ) / configTICK_RATE_HZ );\r
\r
/* Configure interrupt priority and level and unmask interrupt. */\r
- MCF_INTC0_ICR55 = ( configKERNEL_INTERRUPT_PRIORITY | ( 1 << 3 ) );\r
+ MCF_INTC0_ICR55 = ( 2 | ( configKERNEL_INTERRUPT_PRIORITY << 3 ) );\r
MCF_INTC0_IMRH &= ~( MCF_INTC_IMRH_INT_MASK55 );\r
\r
- MCF_INTC0_ICR63 = ( configKERNEL_INTERRUPT_PRIORITY | ( 1 << 3 ) );\r
+ MCF_INTC0_ICR63 = ( 1 | configKERNEL_INTERRUPT_PRIORITY << 3 );\r
MCF_INTC0_IMRH &= ~( MCF_INTC_IMRH_INT_MASK63 );\r
\r
MCF_PIT0_PCSR |= MCF_PIT_PCSR_PIF;\r
\r
void __attribute__ ((interrupt)) __cs3_isr_interrupt_119( void )\r
{\r
+unsigned portLONG ulSavedInterruptMask;\r
+\r
MCF_PIT0_PCSR |= MCF_PIT_PCSR_PIF;\r
- vTaskIncrementTick();\r
+ ulSavedInterruptMask = portSET_INTERRUPT_MASK_FROM_ISR();\r
+ vTaskIncrementTick();\r
+ portCLEAR_INTERRUPT_MASK_FROM_ISR( ulSavedInterruptMask );\r
\r
#if configUSE_PREEMPTION == 1\r
{\r
--- /dev/null
+/*\r
+ FreeRTOS.org V5.0.3 - Copyright (C) 2003-2008 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS.org distribution.\r
+\r
+ FreeRTOS.org is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS.org is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS.org; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS.org, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section\r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ ***************************************************************************\r
+ * *\r
+ * SAVE TIME AND MONEY! We can port FreeRTOS.org to your own hardware, *\r
+ * and even write all or part of your application on your behalf. *\r
+ * See http://www.OpenRTOS.com for details of the services we provide to *\r
+ * expedite your project. *\r
+ * *\r
+ ***************************************************************************\r
+ ***************************************************************************\r
+\r
+ Please ensure to read the configuration and relevant port sections of the\r
+ online documentation.\r
+\r
+ http://www.FreeRTOS.org - Documentation, latest information, license and\r
+ contact details.\r
+\r
+ http://www.SafeRTOS.com - A version that is certified for use in safety\r
+ critical systems.\r
+\r
+ http://www.OpenRTOS.com - Commercial support, development, porting,\r
+ licensing and training services.\r
+*/\r
+\r
+#include "FreeRTOS.h"\r
+#include "IntQueueTimer.h"\r
+#include "IntQueue.h"\r
+\r
+#define timerINTERRUPT1_FREQUENCY ( 2000UL )\r
+#define timerINTERRUPT2_FREQUENCY ( 2001UL )\r
+#define timerPRESCALE_VALUE ( 2 )\r
+\r
+void vInitialiseTimerForIntQueueTest( void )\r
+{\r
+const unsigned portSHORT usCompareMatchValue1 = ( unsigned portSHORT ) ( ( configCPU_CLOCK_HZ / timerPRESCALE_VALUE ) / timerINTERRUPT1_FREQUENCY );\r
+const unsigned portSHORT usCompareMatchValue2 = ( unsigned portSHORT ) ( ( configCPU_CLOCK_HZ / timerPRESCALE_VALUE ) / timerINTERRUPT2_FREQUENCY );\r
+\r
+ /* Configure interrupt priority and level and unmask interrupt. */\r
+ MCF_INTC0_ICR56 = ( ( configMAX_SYSCALL_INTERRUPT_PRIORITY - 1 ) << 3 );\r
+ MCF_INTC0_IMRH &= ~( MCF_INTC_IMRH_INT_MASK56 );\r
+\r
+ MCF_PIT1_PCSR |= MCF_PIT_PCSR_PIF;\r
+ MCF_PIT1_PCSR = ( MCF_PIT_PCSR_PIE | MCF_PIT_PCSR_RLD | MCF_PIT_PCSR_EN );\r
+ MCF_PIT1_PMR = usCompareMatchValue1;\r
+\r
+ MCF_INTC0_ICR57 = ( configMAX_SYSCALL_INTERRUPT_PRIORITY << 3 );\r
+ MCF_INTC0_IMRH &= ~( MCF_INTC_IMRH_INT_MASK57 );\r
+\r
+ MCF_PIT2_PCSR |= MCF_PIT_PCSR_PIF;\r
+ MCF_PIT2_PCSR = ( MCF_PIT_PCSR_PIE | MCF_PIT_PCSR_RLD | MCF_PIT_PCSR_EN );\r
+ MCF_PIT2_PMR = usCompareMatchValue2;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void __attribute__ ((interrupt)) __cs3_isr_interrupt_120( void )\r
+{\r
+ MCF_PIT1_PCSR |= MCF_PIT_PCSR_PIF;\r
+ portEND_SWITCHING_ISR( xFirstTimerHandler() );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void __attribute__ ((interrupt)) __cs3_isr_interrupt_121( void )\r
+{\r
+ MCF_PIT2_PCSR |= MCF_PIT_PCSR_PIF;\r
+ portEND_SWITCHING_ISR( xSecondTimerHandler() );\r
+}\r
--- /dev/null
+/*\r
+ FreeRTOS.org V5.0.3 - Copyright (C) 2003-2008 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS.org distribution.\r
+\r
+ FreeRTOS.org is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS.org is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS.org; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS.org, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section\r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ ***************************************************************************\r
+ * *\r
+ * SAVE TIME AND MONEY! We can port FreeRTOS.org to your own hardware, *\r
+ * and even write all or part of your application on your behalf. *\r
+ * See http://www.OpenRTOS.com for details of the services we provide to *\r
+ * expedite your project. *\r
+ * *\r
+ ***************************************************************************\r
+ ***************************************************************************\r
+\r
+ Please ensure to read the configuration and relevant port sections of the\r
+ online documentation.\r
+\r
+ http://www.FreeRTOS.org - Documentation, latest information, license and \r
+ contact details.\r
+\r
+ http://www.SafeRTOS.com - A version that is certified for use in safety \r
+ critical systems.\r
+\r
+ http://www.OpenRTOS.com - Commercial support, development, porting, \r
+ licensing and training services.\r
+*/\r
+\r
+#ifndef INT_QUEUE_TIMER_H\r
+#define INT_QUEUE_TIMER_H\r
+\r
+void vInitialiseTimerForIntQueueTest( void );\r
+portBASE_TYPE xTimer0Handler( void );\r
+portBASE_TYPE xTimer1Handler( void );\r
+\r
+#endif\r
+\r
}\r
#endif\r
\r
+#define MCF5XXX_CACR_CENB (0x80000000)\r
+#define MCF5XXX_CACR_CPDI (0x10000000)\r
+#define MCF5XXX_CACR_CPD (0x10000000)\r
+#define MCF5XXX_CACR_CFRZ (0x08000000)\r
+#define MCF5XXX_CACR_CINV (0x01000000)\r
+#define MCF5XXX_CACR_DIDI (0x00800000)\r
+#define MCF5XXX_CACR_DISD (0x00400000)\r
+#define MCF5XXX_CACR_INVI (0x00200000)\r
+#define MCF5XXX_CACR_INVD (0x00100000)\r
+#define MCF5XXX_CACR_CEIB (0x00000400)\r
+#define MCF5XXX_CACR_DCM_WR (0x00000000)\r
+#define MCF5XXX_CACR_DCM_CB (0x00000100)\r
+#define MCF5XXX_CACR_DCM_IP (0x00000200)\r
+#define MCF5XXX_CACR_DCM (0x00000200)\r
+#define MCF5XXX_CACR_DCM_II (0x00000300)\r
+#define MCF5XXX_CACR_DBWE (0x00000100)\r
+#define MCF5XXX_CACR_DWP (0x00000020)\r
+#define MCF5XXX_CACR_EUST (0x00000010)\r
+#define MCF5XXX_CACR_CLNF_00 (0x00000000)\r
+#define MCF5XXX_CACR_CLNF_01 (0x00000002)\r
+#define MCF5XXX_CACR_CLNF_10 (0x00000004)\r
+#define MCF5XXX_CACR_CLNF_11 (0x00000006)\r
\r
#endif /* __MCF5282_H__ */\r
\r
/* Configure the interrupt controller. Run the UARTs above the kernel\r
interrupt priority for demo purposes. */\r
- MCF_INTC0_ICR14 = ( ( configKERNEL_INTERRUPT_PRIORITY + 1 ) | ( 1 << 3 ) );\r
+ MCF_INTC0_ICR14 = ( ( configMAX_SYSCALL_INTERRUPT_PRIORITY - 2 ) << 3 );\r
MCF_INTC0_IMRL &= ~( MCF_INTC_IMRL_INT_MASK14 | 0x01 );\r
\r
/* The Tx interrupt is not enabled until there is data to send. */\r
projects / freertos / commitdiff