cortex_m: Select an AP when accessing the DAP

Prepare to support multiple cortex-m cores on one DAP. Uses mem_ap_sel_*
functions and removes mem_ap_* functions. Adds a new debug_ap
parameter to the cortex_m (currently set to zero as in existing code).

Change-Id: I6926029d1e7bf44a42d453d1aff349bda824ba72
Signed-off-by: Patrick Stewart <patstew@gmail.com>
Reviewed-on: http://openocd.zylin.com/2983
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>

diff --git a/src/flash/nor/at91sam4l.c b/src/flash/nor/at91sam4l.c
index 74d5dbc6812a93dc0cd8a7f2eef5b4b457159e84..c5ec152892f91f4fa1ee34da68f8132da53da4cb 100644 (file)
--- a/src/flash/nor/at91sam4l.c
+++ b/src/flash/nor/at91sam4l.c
@@ -660,14 +660,14 @@ COMMAND_HANDLER(sam4l_handle_reset_deassert)
         * After vectreset SMAP release is not needed however makes no harm
         */
        if (target->reset_halt && (jtag_reset_config & RESET_HAS_SRST)) {
-               retval = mem_ap_write_u32(swjdp, DCB_DHCSR, DBGKEY | C_HALT | C_DEBUGEN);
+               retval = mem_ap_sel_write_u32(swjdp, armv7m->debug_ap, DCB_DHCSR, DBGKEY | C_HALT | C_DEBUGEN);
                if (retval == ERROR_OK)
-                       retval = mem_ap_write_atomic_u32(swjdp, DCB_DEMCR,
+                       retval = mem_ap_sel_write_atomic_u32(swjdp, armv7m->debug_ap, DCB_DEMCR,
                                TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
                /* do not return on error here, releasing SMAP reset is more important */
        }
 
-       int retval2 = mem_ap_write_atomic_u32(swjdp, SMAP_SCR, SMAP_SCR_HCR);
+       int retval2 = mem_ap_sel_write_atomic_u32(swjdp, armv7m->debug_ap, SMAP_SCR, SMAP_SCR_HCR);
        if (retval2 != ERROR_OK)
                return retval2;
 

diff --git a/src/flash/nor/at91samd.c b/src/flash/nor/at91samd.c
index 04915802b64f5c527d5c02972f3dc3e8fff8159b..6e37dd33222f67a02edce367ec8fe7b39e5106c0 100644 (file)
--- a/src/flash/nor/at91samd.c
+++ b/src/flash/nor/at91samd.c
@@ -1000,9 +1000,9 @@ COMMAND_HANDLER(samd_handle_reset_deassert)
         * After vectreset DSU release is not needed however makes no harm
         */
        if (target->reset_halt && (jtag_reset_config & RESET_HAS_SRST)) {
-               retval = mem_ap_write_u32(swjdp, DCB_DHCSR, DBGKEY | C_HALT | C_DEBUGEN);
+               retval = mem_ap_sel_write_u32(swjdp, armv7m->debug_ap, DCB_DHCSR, DBGKEY | C_HALT | C_DEBUGEN);
                if (retval == ERROR_OK)
-                       retval = mem_ap_write_u32(swjdp, DCB_DEMCR,
+                       retval = mem_ap_sel_write_u32(swjdp, armv7m->debug_ap, DCB_DEMCR,
                                TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
                /* do not return on error here, releasing DSU reset is more important */
        }

diff --git a/src/target/arm_adi_v5.c b/src/target/arm_adi_v5.c
index fd91281b3776253daf36b64ae564ef173c029f02..a5d02d0b71455f1299f233b4c5829e9d7335e78f 100644 (file)
--- a/src/target/arm_adi_v5.c
+++ b/src/target/arm_adi_v5.c
@@ -187,7 +187,7 @@ int dap_setup_accessport(struct adiv5_dap *dap, uint32_t csw, uint32_t tar)
  *
  * @return ERROR_OK for success.  Otherwise a fault code.
  */
-int mem_ap_read_u32(struct adiv5_dap *dap, uint32_t address,
+static int mem_ap_read_u32(struct adiv5_dap *dap, uint32_t address,
                uint32_t *value)
 {
        int retval;
@@ -215,7 +215,7 @@ int mem_ap_read_u32(struct adiv5_dap *dap, uint32_t address,
  * @return ERROR_OK for success; *value holds the result.
  * Otherwise a fault code.
  */
-int mem_ap_read_atomic_u32(struct adiv5_dap *dap, uint32_t address,
+static int mem_ap_read_atomic_u32(struct adiv5_dap *dap, uint32_t address,
                uint32_t *value)
 {
        int retval;
@@ -238,7 +238,7 @@ int mem_ap_read_atomic_u32(struct adiv5_dap *dap, uint32_t address,
  *
  * @return ERROR_OK for success.  Otherwise a fault code.
  */
-int mem_ap_write_u32(struct adiv5_dap *dap, uint32_t address,
+static int mem_ap_write_u32(struct adiv5_dap *dap, uint32_t address,
                uint32_t value)
 {
        int retval;
@@ -266,7 +266,7 @@ int mem_ap_write_u32(struct adiv5_dap *dap, uint32_t address,
  *
  * @return ERROR_OK for success; the data was written.  Otherwise a fault code.
  */
-int mem_ap_write_atomic_u32(struct adiv5_dap *dap, uint32_t address,
+static int mem_ap_write_atomic_u32(struct adiv5_dap *dap, uint32_t address,
                uint32_t value)
 {
        int retval = mem_ap_write_u32(dap, address, value);
@@ -289,7 +289,7 @@ int mem_ap_write_atomic_u32(struct adiv5_dap *dap, uint32_t address,
  *  should normally be true, except when writing to e.g. a FIFO.
  * @return ERROR_OK on success, otherwise an error code.
  */
-int mem_ap_write(struct adiv5_dap *dap, const uint8_t *buffer, uint32_t size, uint32_t count,
+static int mem_ap_write(struct adiv5_dap *dap, const uint8_t *buffer, uint32_t size, uint32_t count,
                uint32_t address, bool addrinc)
 {
        size_t nbytes = size * count;
@@ -419,7 +419,7 @@ int mem_ap_write(struct adiv5_dap *dap, const uint8_t *buffer, uint32_t size, ui
  *  should normally be true, except when reading from e.g. a FIFO.
  * @return ERROR_OK on success, otherwise an error code.
  */
-int mem_ap_read(struct adiv5_dap *dap, uint8_t *buffer, uint32_t size, uint32_t count,
+static int mem_ap_read(struct adiv5_dap *dap, uint8_t *buffer, uint32_t size, uint32_t count,
                uint32_t adr, bool addrinc)
 {
        size_t nbytes = size * count;
@@ -640,7 +640,7 @@ extern const struct dap_ops jtag_dp_ops;
  * in layering.  (JTAG is useful without any debug target; but not SWD.)
  * And this may not even use an AHB-AP ... e.g. DAP-Lite uses an APB-AP.
  */
-int ahbap_debugport_init(struct adiv5_dap *dap)
+int ahbap_debugport_init(struct adiv5_dap *dap, uint8_t apsel)
 {
        /* check that we support packed transfers */
        uint32_t csw, cfg;
@@ -661,8 +661,8 @@ int ahbap_debugport_init(struct adiv5_dap *dap)
         * Should we probe, or take a hint from the caller?
         * Presumably we can ignore the possibility of multiple APs.
         */
-       dap->ap_current = !0;
-       dap_ap_select(dap, 0);
+       dap->ap_current = -1;
+       dap_ap_select(dap, apsel);
        dap->last_read = NULL;
 
        for (size_t i = 0; i < 10; i++) {

diff --git a/src/target/arm_adi_v5.h b/src/target/arm_adi_v5.h
index 1c4b1000c55644187497f336fbbe8fd44d0a594e..178194113958de478b79b7852751e57305e5fcf7 100644 (file)
--- a/src/target/arm_adi_v5.h
+++ b/src/target/arm_adi_v5.h
@@ -422,16 +422,6 @@ void dap_ap_select(struct adiv5_dap *dap, uint8_t ap);
 int dap_setup_accessport(struct adiv5_dap *swjdp,
                uint32_t csw, uint32_t tar);
 
-/* Queued MEM-AP memory mapped single word transfers */
-int mem_ap_read_u32(struct adiv5_dap *swjdp, uint32_t address, uint32_t *value);
-int mem_ap_write_u32(struct adiv5_dap *swjdp, uint32_t address, uint32_t value);
-
-/* Synchronous MEM-AP memory mapped single word transfers */
-int mem_ap_read_atomic_u32(struct adiv5_dap *swjdp,
-               uint32_t address, uint32_t *value);
-int mem_ap_write_atomic_u32(struct adiv5_dap *swjdp,
-               uint32_t address, uint32_t value);
-
 /* Queued MEM-AP memory mapped single word transfers with selection of ap */
 int mem_ap_sel_read_u32(struct adiv5_dap *swjdp, uint8_t ap,
                uint32_t address, uint32_t *value);
@@ -444,12 +434,6 @@ int mem_ap_sel_read_atomic_u32(struct adiv5_dap *swjdp, uint8_t ap,
 int mem_ap_sel_write_atomic_u32(struct adiv5_dap *swjdp, uint8_t ap,
                uint32_t address, uint32_t value);
 
-/* Synchronous MEM-AP memory mapped bus block transfers */
-int mem_ap_read(struct adiv5_dap *dap, uint8_t *buffer, uint32_t size,
-               uint32_t count, uint32_t address, bool addrinc);
-int mem_ap_write(struct adiv5_dap *dap, const uint8_t *buffer, uint32_t size,
-               uint32_t count, uint32_t address, bool addrinc);
-
 /* Synchronous MEM-AP memory mapped bus block transfers with selection of ap */
 int mem_ap_sel_read_buf(struct adiv5_dap *swjdp, uint8_t ap,
                uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address);
@@ -464,7 +448,7 @@ int mem_ap_sel_write_buf_noincr(struct adiv5_dap *swjdp, uint8_t ap,
                const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address);
 
 /* Initialisation of the debug system, power domains and registers */
-int ahbap_debugport_init(struct adiv5_dap *swjdp);
+int ahbap_debugport_init(struct adiv5_dap *swjdp, uint8_t apsel);
 
 /* Probe the AP for ROM Table location */
 int dap_get_debugbase(struct adiv5_dap *dap, int ap,

diff --git a/src/target/armv7m.h b/src/target/armv7m.h
index 4ecf102c5c547fd066353cb59803a7ba6cedbfde..4c55e8ad3e42369826487b2744d3f7d53e961b29 100644 (file)
--- a/src/target/armv7m.h
+++ b/src/target/armv7m.h
@@ -148,6 +148,9 @@ struct armv7m_common {
        int exception_number;
        struct adiv5_dap dap;
 
+       /* AP this processor is connected to in the DAP */
+       uint8_t debug_ap;
+
        int fp_feature;
        uint32_t demcr;
 

diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c
index 86bf757ee519dc3416431d7d2ad860d726123741..410b13f54a3c3db7d15ca88f769ba740595ad6b1 100644 (file)
--- a/src/target/cortex_a.c
+++ b/src/target/cortex_a.c
@@ -2938,7 +2938,7 @@ static int cortex_a_examine_first(struct target *target)
        /* We do one extra read to ensure DAP is configured,
         * we call ahbap_debugport_init(swjdp) instead
         */
-       retval = ahbap_debugport_init(swjdp);
+       retval = ahbap_debugport_init(swjdp, 0);
        if (retval != ERROR_OK)
                return retval;
 

diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c
index 88b226d85c8ad86e6167ad7a67a0fdb457b18b2f..b821bde8538406ca2a7198ae11f9c99c9ffd714f 100644 (file)
--- a/src/target/cortex_m.c
+++ b/src/target/cortex_m.c
@@ -74,16 +74,16 @@ static int cortexm_dap_read_coreregister_u32(struct target *target,
        /* because the DCB_DCRDR is used for the emulated dcc channel
         * we have to save/restore the DCB_DCRDR when used */
        if (target->dbg_msg_enabled) {
-               retval = mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr);
+               retval = mem_ap_sel_read_u32(swjdp, armv7m->debug_ap, DCB_DCRDR, &dcrdr);
                if (retval != ERROR_OK)
                        return retval;
        }
 
-       retval = mem_ap_write_u32(swjdp, DCB_DCRSR, regnum);
+       retval = mem_ap_sel_write_u32(swjdp, armv7m->debug_ap, DCB_DCRSR, regnum);
        if (retval != ERROR_OK)
                return retval;
 
-       retval = mem_ap_read_atomic_u32(swjdp, DCB_DCRDR, value);
+       retval = mem_ap_sel_read_atomic_u32(swjdp, armv7m->debug_ap, DCB_DCRDR, value);
        if (retval != ERROR_OK)
                return retval;
 
@@ -91,7 +91,7 @@ static int cortexm_dap_read_coreregister_u32(struct target *target,
                /* restore DCB_DCRDR - this needs to be in a separate
                 * transaction otherwise the emulated DCC channel breaks */
                if (retval == ERROR_OK)
-                       retval = mem_ap_write_atomic_u32(swjdp, DCB_DCRDR, dcrdr);
+                       retval = mem_ap_sel_write_atomic_u32(swjdp, armv7m->debug_ap, DCB_DCRDR, dcrdr);
        }
 
        return retval;
@@ -108,16 +108,16 @@ static int cortexm_dap_write_coreregister_u32(struct target *target,
        /* because the DCB_DCRDR is used for the emulated dcc channel
         * we have to save/restore the DCB_DCRDR when used */
        if (target->dbg_msg_enabled) {
-               retval = mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr);
+               retval = mem_ap_sel_read_u32(swjdp, armv7m->debug_ap, DCB_DCRDR, &dcrdr);
                if (retval != ERROR_OK)
                        return retval;
        }
 
-       retval = mem_ap_write_u32(swjdp, DCB_DCRDR, value);
+       retval = mem_ap_sel_write_u32(swjdp, armv7m->debug_ap, DCB_DCRDR, value);
        if (retval != ERROR_OK)
                return retval;
 
-       retval = mem_ap_write_atomic_u32(swjdp, DCB_DCRSR, regnum | DCRSR_WnR);
+       retval = mem_ap_sel_write_atomic_u32(swjdp, armv7m->debug_ap, DCB_DCRSR, regnum | DCRSR_WnR);
        if (retval != ERROR_OK)
                return retval;
 
@@ -125,7 +125,7 @@ static int cortexm_dap_write_coreregister_u32(struct target *target,
                /* restore DCB_DCRDR - this needs to be in a seperate
                 * transaction otherwise the emulated DCC channel breaks */
                if (retval == ERROR_OK)
-                       retval = mem_ap_write_atomic_u32(swjdp, DCB_DCRDR, dcrdr);
+                       retval = mem_ap_sel_write_atomic_u32(swjdp, armv7m->debug_ap, DCB_DCRDR, dcrdr);
        }
 
        return retval;
@@ -135,6 +135,7 @@ static int cortex_m_write_debug_halt_mask(struct target *target,
        uint32_t mask_on, uint32_t mask_off)
 {
        struct cortex_m_common *cortex_m = target_to_cm(target);
+       struct armv7m_common *armv7m = &cortex_m->armv7m;
        struct adiv5_dap *swjdp = cortex_m->armv7m.arm.dap;
 
        /* mask off status bits */
@@ -142,12 +143,13 @@ static int cortex_m_write_debug_halt_mask(struct target *target,
        /* create new register mask */
        cortex_m->dcb_dhcsr |= DBGKEY | C_DEBUGEN | mask_on;
 
-       return mem_ap_write_atomic_u32(swjdp, DCB_DHCSR, cortex_m->dcb_dhcsr);
+       return mem_ap_sel_write_atomic_u32(swjdp, armv7m->debug_ap, DCB_DHCSR, cortex_m->dcb_dhcsr);
 }
 
 static int cortex_m_clear_halt(struct target *target)
 {
        struct cortex_m_common *cortex_m = target_to_cm(target);
+       struct armv7m_common *armv7m = &cortex_m->armv7m;
        struct adiv5_dap *swjdp = cortex_m->armv7m.arm.dap;
        int retval;
 
@@ -155,12 +157,12 @@ static int cortex_m_clear_halt(struct target *target)
        cortex_m_write_debug_halt_mask(target, C_HALT, C_STEP);
 
        /* Read Debug Fault Status Register */
-       retval = mem_ap_read_atomic_u32(swjdp, NVIC_DFSR, &cortex_m->nvic_dfsr);
+       retval = mem_ap_sel_read_atomic_u32(swjdp, armv7m->debug_ap, NVIC_DFSR, &cortex_m->nvic_dfsr);
        if (retval != ERROR_OK)
                return retval;
 
        /* Clear Debug Fault Status */
-       retval = mem_ap_write_atomic_u32(swjdp, NVIC_DFSR, cortex_m->nvic_dfsr);
+       retval = mem_ap_sel_write_atomic_u32(swjdp, armv7m->debug_ap, NVIC_DFSR, cortex_m->nvic_dfsr);
        if (retval != ERROR_OK)
                return retval;
        LOG_DEBUG(" NVIC_DFSR 0x%" PRIx32 "", cortex_m->nvic_dfsr);
@@ -171,6 +173,7 @@ static int cortex_m_clear_halt(struct target *target)
 static int cortex_m_single_step_core(struct target *target)
 {
        struct cortex_m_common *cortex_m = target_to_cm(target);
+       struct armv7m_common *armv7m = &cortex_m->armv7m;
        struct adiv5_dap *swjdp = cortex_m->armv7m.arm.dap;
        uint32_t dhcsr_save;
        int retval;
@@ -183,12 +186,12 @@ static int cortex_m_single_step_core(struct target *target)
         * HALT can put the core into an unknown state.
         */
        if (!(cortex_m->dcb_dhcsr & C_MASKINTS)) {
-               retval = mem_ap_write_atomic_u32(swjdp, DCB_DHCSR,
+               retval = mem_ap_sel_write_atomic_u32(swjdp, armv7m->debug_ap, DCB_DHCSR,
                                DBGKEY | C_MASKINTS | C_HALT | C_DEBUGEN);
                if (retval != ERROR_OK)
                        return retval;
        }
-       retval = mem_ap_write_atomic_u32(swjdp, DCB_DHCSR,
+       retval = mem_ap_sel_write_atomic_u32(swjdp, armv7m->debug_ap, DCB_DHCSR,
                        DBGKEY | C_MASKINTS | C_STEP | C_DEBUGEN);
        if (retval != ERROR_OK)
                return retval;
@@ -231,22 +234,22 @@ static int cortex_m_endreset_event(struct target *target)
        struct cortex_m_dwt_comparator *dwt_list = cortex_m->dwt_comparator_list;
 
        /* REVISIT The four debug monitor bits are currently ignored... */
-       retval = mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &dcb_demcr);
+       retval = mem_ap_sel_read_atomic_u32(swjdp, armv7m->debug_ap, DCB_DEMCR, &dcb_demcr);
        if (retval != ERROR_OK)
                return retval;
        LOG_DEBUG("DCB_DEMCR = 0x%8.8" PRIx32 "", dcb_demcr);
 
        /* this register is used for emulated dcc channel */
-       retval = mem_ap_write_u32(swjdp, DCB_DCRDR, 0);
+       retval = mem_ap_sel_write_u32(swjdp, armv7m->debug_ap, DCB_DCRDR, 0);
        if (retval != ERROR_OK)
                return retval;
 
        /* Enable debug requests */
-       retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m->dcb_dhcsr);
+       retval = mem_ap_sel_read_atomic_u32(swjdp, armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
        if (retval != ERROR_OK)
                return retval;
        if (!(cortex_m->dcb_dhcsr & C_DEBUGEN)) {
-               retval = mem_ap_write_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN);
+               retval = mem_ap_sel_write_u32(swjdp, armv7m->debug_ap, DCB_DHCSR, DBGKEY | C_DEBUGEN);
                if (retval != ERROR_OK)
                        return retval;
        }
@@ -261,7 +264,7 @@ static int cortex_m_endreset_event(struct target *target)
         * choices *EXCEPT* explicitly scripted overrides like "vector_catch"
         * or manual updates to the NVIC SHCSR and CCR registers.
         */
-       retval = mem_ap_write_u32(swjdp, DCB_DEMCR, TRCENA | armv7m->demcr);
+       retval = mem_ap_sel_write_u32(swjdp, armv7m->debug_ap, DCB_DEMCR, TRCENA | armv7m->demcr);
        if (retval != ERROR_OK)
                return retval;
 
@@ -307,7 +310,7 @@ static int cortex_m_endreset_event(struct target *target)
        register_cache_invalidate(armv7m->arm.core_cache);
 
        /* make sure we have latest dhcsr flags */
-       retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m->dcb_dhcsr);
+       retval = mem_ap_sel_read_atomic_u32(swjdp, armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
 
        return retval;
 }
@@ -343,47 +346,47 @@ static int cortex_m_examine_exception_reason(struct target *target)
        struct adiv5_dap *swjdp = armv7m->arm.dap;
        int retval;
 
-       retval = mem_ap_read_u32(swjdp, NVIC_SHCSR, &shcsr);
+       retval = mem_ap_sel_read_u32(swjdp, armv7m->debug_ap, NVIC_SHCSR, &shcsr);
        if (retval != ERROR_OK)
                return retval;
        switch (armv7m->exception_number) {
                case 2: /* NMI */
                        break;
                case 3: /* Hard Fault */
-                       retval = mem_ap_read_atomic_u32(swjdp, NVIC_HFSR, &except_sr);
+                       retval = mem_ap_sel_read_atomic_u32(swjdp, armv7m->debug_ap, NVIC_HFSR, &except_sr);
                        if (retval != ERROR_OK)
                                return retval;
                        if (except_sr & 0x40000000) {
-                               retval = mem_ap_read_u32(swjdp, NVIC_CFSR, &cfsr);
+                               retval = mem_ap_sel_read_u32(swjdp, armv7m->debug_ap, NVIC_CFSR, &cfsr);
                                if (retval != ERROR_OK)
                                        return retval;
                        }
                        break;
                case 4: /* Memory Management */
-                       retval = mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
+                       retval = mem_ap_sel_read_u32(swjdp, armv7m->debug_ap, NVIC_CFSR, &except_sr);
                        if (retval != ERROR_OK)
                                return retval;
-                       retval = mem_ap_read_u32(swjdp, NVIC_MMFAR, &except_ar);
+                       retval = mem_ap_sel_read_u32(swjdp, armv7m->debug_ap, NVIC_MMFAR, &except_ar);
                        if (retval != ERROR_OK)
                                return retval;
                        break;
                case 5: /* Bus Fault */
-                       retval = mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
+                       retval = mem_ap_sel_read_u32(swjdp, armv7m->debug_ap, NVIC_CFSR, &except_sr);
                        if (retval != ERROR_OK)
                                return retval;
-                       retval = mem_ap_read_u32(swjdp, NVIC_BFAR, &except_ar);
+                       retval = mem_ap_sel_read_u32(swjdp, armv7m->debug_ap, NVIC_BFAR, &except_ar);
                        if (retval != ERROR_OK)
                                return retval;
                        break;
                case 6: /* Usage Fault */
-                       retval = mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
+                       retval = mem_ap_sel_read_u32(swjdp, armv7m->debug_ap, NVIC_CFSR, &except_sr);
                        if (retval != ERROR_OK)
                                return retval;
                        break;
                case 11:        /* SVCall */
                        break;
                case 12:        /* Debug Monitor */
-                       retval = mem_ap_read_u32(swjdp, NVIC_DFSR, &except_sr);
+                       retval = mem_ap_sel_read_u32(swjdp, armv7m->debug_ap, NVIC_DFSR, &except_sr);
                        if (retval != ERROR_OK)
                                return retval;
                        break;
@@ -418,7 +421,7 @@ static int cortex_m_debug_entry(struct target *target)
        LOG_DEBUG(" ");
 
        cortex_m_clear_halt(target);
-       retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m->dcb_dhcsr);
+       retval = mem_ap_sel_read_atomic_u32(swjdp, armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
        if (retval != ERROR_OK)
                return retval;
 
@@ -492,10 +495,11 @@ static int cortex_m_poll(struct target *target)
        int retval = ERROR_OK;
        enum target_state prev_target_state = target->state;
        struct cortex_m_common *cortex_m = target_to_cm(target);
+       struct armv7m_common *armv7m = &cortex_m->armv7m;
        struct adiv5_dap *swjdp = cortex_m->armv7m.arm.dap;
 
        /* Read from Debug Halting Control and Status Register */
-       retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m->dcb_dhcsr);
+       retval = mem_ap_sel_read_atomic_u32(swjdp, armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
        if (retval != ERROR_OK) {
                target->state = TARGET_UNKNOWN;
                return retval;
@@ -516,7 +520,7 @@ static int cortex_m_poll(struct target *target)
                detected_failure = ERROR_FAIL;
 
                /* refresh status bits */
-               retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m->dcb_dhcsr);
+               retval = mem_ap_sel_read_atomic_u32(swjdp, armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
                if (retval != ERROR_OK)
                        return retval;
        }
@@ -620,6 +624,7 @@ static int cortex_m_halt(struct target *target)
 static int cortex_m_soft_reset_halt(struct target *target)
 {
        struct cortex_m_common *cortex_m = target_to_cm(target);
+       struct armv7m_common *armv7m = &cortex_m->armv7m;
        struct adiv5_dap *swjdp = cortex_m->armv7m.arm.dap;
        uint32_t dcb_dhcsr = 0;
        int retval, timeout = 0;
@@ -631,13 +636,13 @@ static int cortex_m_soft_reset_halt(struct target *target)
        LOG_WARNING("soft_reset_halt is deprecated, please use 'reset halt' instead.");
 
        /* Enter debug state on reset; restore DEMCR in endreset_event() */
-       retval = mem_ap_write_u32(swjdp, DCB_DEMCR,
+       retval = mem_ap_sel_write_u32(swjdp, armv7m->debug_ap, DCB_DEMCR,
                        TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
        if (retval != ERROR_OK)
                return retval;
 
        /* Request a core-only reset */
-       retval = mem_ap_write_atomic_u32(swjdp, NVIC_AIRCR,
+       retval = mem_ap_sel_write_atomic_u32(swjdp, armv7m->debug_ap, NVIC_AIRCR,
                        AIRCR_VECTKEY | AIRCR_VECTRESET);
        if (retval != ERROR_OK)
                return retval;
@@ -647,9 +652,9 @@ static int cortex_m_soft_reset_halt(struct target *target)
        register_cache_invalidate(cortex_m->armv7m.arm.core_cache);
 
        while (timeout < 100) {
-               retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &dcb_dhcsr);
+               retval = mem_ap_sel_read_atomic_u32(swjdp, armv7m->debug_ap, DCB_DHCSR, &dcb_dhcsr);
                if (retval == ERROR_OK) {
-                       retval = mem_ap_read_atomic_u32(swjdp, NVIC_DFSR,
+                       retval = mem_ap_sel_read_atomic_u32(swjdp, armv7m->debug_ap, NVIC_DFSR,
                                        &cortex_m->nvic_dfsr);
                        if (retval != ERROR_OK)
                                return retval;
@@ -893,7 +898,7 @@ static int cortex_m_step(struct target *target, int current,
 
                                        /* Wait for pending handlers to complete or timeout */
                                        do {
-                                               retval = mem_ap_read_atomic_u32(swjdp,
+                                               retval = mem_ap_sel_read_atomic_u32(swjdp, armv7m->debug_ap,
                                                                DCB_DHCSR,
                                                                &cortex_m->dcb_dhcsr);
                                                if (retval != ERROR_OK) {
@@ -928,7 +933,7 @@ static int cortex_m_step(struct target *target, int current,
                }
        }
 
-       retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m->dcb_dhcsr);
+       retval = mem_ap_sel_read_atomic_u32(swjdp, armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
        if (retval != ERROR_OK)
                return retval;
 
@@ -964,6 +969,7 @@ static int cortex_m_step(struct target *target, int current,
 static int cortex_m_assert_reset(struct target *target)
 {
        struct cortex_m_common *cortex_m = target_to_cm(target);
+       struct armv7m_common *armv7m = &cortex_m->armv7m;
        struct adiv5_dap *swjdp = cortex_m->armv7m.arm.dap;
        enum cortex_m_soft_reset_config reset_config = cortex_m->soft_reset_config;
 
@@ -995,11 +1001,11 @@ static int cortex_m_assert_reset(struct target *target)
 
        /* Enable debug requests */
        int retval;
-       retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m->dcb_dhcsr);
+       retval = mem_ap_sel_read_atomic_u32(swjdp, armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
        if (retval != ERROR_OK)
                return retval;
        if (!(cortex_m->dcb_dhcsr & C_DEBUGEN)) {
-               retval = mem_ap_write_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN);
+               retval = mem_ap_sel_write_u32(swjdp, armv7m->debug_ap, DCB_DHCSR, DBGKEY | C_DEBUGEN);
                if (retval != ERROR_OK)
                        return retval;
        }
@@ -1007,19 +1013,19 @@ static int cortex_m_assert_reset(struct target *target)
        /* If the processor is sleeping in a WFI or WFE instruction, the
         * C_HALT bit must be asserted to regain control */
        if (cortex_m->dcb_dhcsr & S_SLEEP) {
-               retval = mem_ap_write_u32(swjdp, DCB_DHCSR, DBGKEY | C_HALT | C_DEBUGEN);
+               retval = mem_ap_sel_write_u32(swjdp, armv7m->debug_ap, DCB_DHCSR, DBGKEY | C_HALT | C_DEBUGEN);
                if (retval != ERROR_OK)
                        return retval;
        }
 
-       retval = mem_ap_write_u32(swjdp, DCB_DCRDR, 0);
+       retval = mem_ap_sel_write_u32(swjdp, armv7m->debug_ap, DCB_DCRDR, 0);
        if (retval != ERROR_OK)
                return retval;
 
        if (!target->reset_halt) {
                /* Set/Clear C_MASKINTS in a separate operation */
                if (cortex_m->dcb_dhcsr & C_MASKINTS) {
-                       retval = mem_ap_write_atomic_u32(swjdp, DCB_DHCSR,
+                       retval = mem_ap_sel_write_atomic_u32(swjdp, armv7m->debug_ap, DCB_DHCSR,
                                        DBGKEY | C_DEBUGEN | C_HALT);
                        if (retval != ERROR_OK)
                                return retval;
@@ -1037,7 +1043,7 @@ static int cortex_m_assert_reset(struct target *target)
                 * bad vector table entries.  Should this include MMERR or
                 * other flags too?
                 */
-               retval = mem_ap_write_atomic_u32(swjdp, DCB_DEMCR,
+               retval = mem_ap_sel_write_atomic_u32(swjdp, armv7m->debug_ap, DCB_DEMCR,
                                TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
                if (retval != ERROR_OK)
                        return retval;
@@ -1061,13 +1067,13 @@ static int cortex_m_assert_reset(struct target *target)
                                "handler to reset any peripherals or configure hardware srst support.");
                }
 
-               retval = mem_ap_write_atomic_u32(swjdp, NVIC_AIRCR,
+               retval = mem_ap_sel_write_atomic_u32(swjdp, armv7m->debug_ap, NVIC_AIRCR,
                                AIRCR_VECTKEY | ((reset_config == CORTEX_M_RESET_SYSRESETREQ)
                                ? AIRCR_SYSRESETREQ : AIRCR_VECTRESET));
                if (retval != ERROR_OK)
                        LOG_DEBUG("Ignoring AP write error right after reset");
 
-               retval = ahbap_debugport_init(swjdp);
+               retval = ahbap_debugport_init(swjdp, armv7m->debug_ap);
                if (retval != ERROR_OK) {
                        LOG_ERROR("DP initialisation failed");
                        return retval;
@@ -1079,7 +1085,7 @@ static int cortex_m_assert_reset(struct target *target)
                         * after reset) on LM3S6918 -- Michael Schwingen
                         */
                        uint32_t tmp;
-                       retval = mem_ap_read_atomic_u32(swjdp, NVIC_AIRCR, &tmp);
+                       retval = mem_ap_sel_read_atomic_u32(swjdp, armv7m->debug_ap, NVIC_AIRCR, &tmp);
                        if (retval != ERROR_OK)
                                return retval;
                }
@@ -1101,6 +1107,8 @@ static int cortex_m_assert_reset(struct target *target)
 
 static int cortex_m_deassert_reset(struct target *target)
 {
+       struct armv7m_common *armv7m = &target_to_cm(target)->armv7m;
+
        LOG_DEBUG("target->state: %s",
                target_state_name(target));
 
@@ -1111,7 +1119,7 @@ static int cortex_m_deassert_reset(struct target *target)
 
        if ((jtag_reset_config & RESET_HAS_SRST) &&
            !(jtag_reset_config & RESET_SRST_NO_GATING)) {
-               int retval = ahbap_debugport_init(target_to_cm(target)->armv7m.arm.dap);
+               int retval = ahbap_debugport_init(armv7m->arm.dap, armv7m->debug_ap);
                if (retval != ERROR_OK) {
                        LOG_ERROR("DP initialisation failed");
                        return retval;
@@ -1672,7 +1680,7 @@ static int cortex_m_read_memory(struct target *target, uint32_t address,
                        return ERROR_TARGET_UNALIGNED_ACCESS;
        }
 
-       return mem_ap_read(swjdp, buffer, size, count, address, true);
+       return mem_ap_sel_read_buf(swjdp, armv7m->debug_ap, buffer, size, count, address);
 }
 
 static int cortex_m_write_memory(struct target *target, uint32_t address,
@@ -1687,7 +1695,7 @@ static int cortex_m_write_memory(struct target *target, uint32_t address,
                        return ERROR_TARGET_UNALIGNED_ACCESS;
        }
 
-       return mem_ap_write(swjdp, buffer, size, count, address, true);
+       return mem_ap_sel_write_buf(swjdp, armv7m->debug_ap, buffer, size, count, address);
 }
 
 static int cortex_m_init_target(struct command_context *cmd_ctx,
@@ -1898,7 +1906,7 @@ int cortex_m_examine(struct target *target)
        /* stlink shares the examine handler but does not support
         * all its calls */
        if (!armv7m->stlink) {
-               retval = ahbap_debugport_init(swjdp);
+               retval = ahbap_debugport_init(swjdp, armv7m->debug_ap);
                if (retval != ERROR_OK)
                        return retval;
        }
@@ -2014,7 +2022,7 @@ static int cortex_m_dcc_read(struct target *target, uint8_t *value, uint8_t *ctr
        uint8_t buf[2];
        int retval;
 
-       retval = mem_ap_read(swjdp, buf, 2, 1, DCB_DCRDR, false);
+       retval = mem_ap_sel_read_buf_noincr(swjdp, armv7m->debug_ap, buf, 2, 1, DCB_DCRDR);
        if (retval != ERROR_OK)
                return retval;
 
@@ -2028,7 +2036,7 @@ static int cortex_m_dcc_read(struct target *target, uint8_t *value, uint8_t *ctr
         * signify we have read data */
        if (dcrdr & (1 << 0)) {
                target_buffer_set_u16(target, buf, 0);
-               retval = mem_ap_write(swjdp, buf, 2, 1, DCB_DCRDR, false);
+               retval = mem_ap_sel_write_buf_noincr(swjdp, armv7m->debug_ap, buf, 2, 1, DCB_DCRDR);
                if (retval != ERROR_OK)
                        return retval;
        }
@@ -2191,7 +2199,7 @@ COMMAND_HANDLER(handle_cortex_m_vector_catch_command)
        if (retval != ERROR_OK)
                return retval;
 
-       retval = mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &demcr);
+       retval = mem_ap_sel_read_atomic_u32(swjdp, armv7m->debug_ap, DCB_DEMCR, &demcr);
        if (retval != ERROR_OK)
                return retval;
 
@@ -2228,10 +2236,10 @@ write:
                demcr |= catch;
 
                /* write, but don't assume it stuck (why not??) */
-               retval = mem_ap_write_u32(swjdp, DCB_DEMCR, demcr);
+               retval = mem_ap_sel_write_u32(swjdp, armv7m->debug_ap, DCB_DEMCR, demcr);
                if (retval != ERROR_OK)
                        return retval;
-               retval = mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &demcr);
+               retval = mem_ap_sel_read_atomic_u32(swjdp, armv7m->debug_ap, DCB_DEMCR, &demcr);
                if (retval != ERROR_OK)
                        return retval;