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Add SmartFusion2 demo for the SmartFustion2 development kit.
authorrichardbarry <richardbarry@1d2547de-c912-0410-9cb9-b8ca96c0e9e2>
Sun, 12 May 2013 20:07:49 +0000 (20:07 +0000)
committerrichardbarry <richardbarry@1d2547de-c912-0410-9cb9-b8ca96c0e9e2>
Sun, 12 May 2013 20:07:49 +0000 (20:07 +0000)
git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@1892 1d2547de-c912-0410-9cb9-b8ca96c0e9e2

68 files changed:
FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/CreateProjectDirectoryStructure.bat [new file with mode: 0644] patch | blob
FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/LiberoOutput/DEV_KIT_DEMO_top.stp [new file with mode: 0644] patch | blob
FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/LiberoOutput/DEV_KIT_DEMO_top_DataSheet.xml [new file with mode: 0644] patch | blob
FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/LiberoOutput/datasheet.xsl [new file with mode: 0644] patch | blob
FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo/.cproject [new file with mode: 0644] patch | blob
FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo/.project [new file with mode: 0644] patch | blob
FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo/Blinky-Demo/main_blinky.c [new file with mode: 0644] patch | blob
FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo/FreeRTOSConfig.h [new file with mode: 0644] patch | blob
FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo/Full-Demo/Common-Demo-Source/ReadMe.txt [new file with mode: 0644] patch | blob
FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo/Full-Demo/Common-Demo-Source/include/ReadMe.txt [new file with mode: 0644] patch | blob
FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo/Full-Demo/File-releated-CLI-commands.c [new file with mode: 0644] patch | blob
FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo/Full-Demo/File-system-demo.c [new file with mode: 0644] patch | blob
FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo/Full-Demo/FreeRTOS-Plus-FAT-SL-Source/ReadMe.txt [new file with mode: 0644] patch | blob
FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo/Full-Demo/ReadMe.txt [new file with mode: 0644] patch | blob
FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo/Full-Demo/Sample-CLI-commands.c [new file with mode: 0644] patch | blob
FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo/Full-Demo/UARTCommandConsole.c [new file with mode: 0644] patch | blob
FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo/Full-Demo/UARTCommandConsole.h [new file with mode: 0644] patch | blob
FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo/Full-Demo/config_fat_sl.h [new file with mode: 0644] patch | blob
FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo/Full-Demo/config_mdriver_ram.h [new file with mode: 0644] patch | blob
FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo/Full-Demo/main_full.c [new file with mode: 0644] patch | blob
FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo/ParTest.c [new file with mode: 0644] patch | blob
FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo/RunTimeStatsTimer.c [new file with mode: 0644] patch | blob
FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo/main.c [new file with mode: 0644] patch | blob
FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo/printf-stdarg.c [new file with mode: 0644] patch | blob
FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/.cproject [new file with mode: 0644] patch | blob
FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/.project [new file with mode: 0644] patch | blob
FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/CMSIS/hw_reg_io.h [new file with mode: 0644] patch | blob
FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/CMSIS/m2sxxx.h [new file with mode: 0644] patch | blob
FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/CMSIS/mss_assert.h [new file with mode: 0644] patch | blob
FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/CMSIS/startup_gcc/debug-in-external-ram.ld [new file with mode: 0644] patch | blob
FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/CMSIS/startup_gcc/debug-in-microsemi-smartfusion2-envm.ld [new file with mode: 0644] patch | blob
FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/CMSIS/startup_gcc/debug-in-microsemi-smartfusion2-esram.ld [new file with mode: 0644] patch | blob
FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/CMSIS/startup_gcc/newlib_stubs.c [new file with mode: 0644] patch | blob
FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/CMSIS/startup_gcc/production-execute-in-place.ld [new file with mode: 0644] patch | blob
FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/CMSIS/startup_gcc/production-relocate-executable.ld [new file with mode: 0644] patch | blob
FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/CMSIS/startup_gcc/startup_m2sxxx.s [new file with mode: 0644] patch | blob
FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/CMSIS/sys_init_cfg_types.h [new file with mode: 0644] patch | blob
FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/CMSIS/system_m2sxxx.c [new file with mode: 0644] patch | blob
FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/CMSIS/system_m2sxxx.h [new file with mode: 0644] patch | blob
FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/RTOSDemo_hw_platform.h [new file with mode: 0644] patch | blob
FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers/mss_gpio/mss_gpio.c [new file with mode: 0644] patch | blob
FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers/mss_gpio/mss_gpio.h [new file with mode: 0644] patch | blob
FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers/mss_hpdma/mss_hpdma.c [new file with mode: 0644] patch | blob
FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers/mss_hpdma/mss_hpdma.h [new file with mode: 0644] patch | blob
FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers/mss_nvm/mss_nvm.c [new file with mode: 0644] patch | blob
FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers/mss_nvm/mss_nvm.h [new file with mode: 0644] patch | blob
FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers/mss_rtc/mss_rtc.c [new file with mode: 0644] patch | blob
FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers/mss_rtc/mss_rtc.h [new file with mode: 0644] patch | blob
FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers/mss_sys_services/mss_comblk.c [new file with mode: 0644] patch | blob
FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers/mss_sys_services/mss_comblk.h [new file with mode: 0644] patch | blob
FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers/mss_sys_services/mss_sys_services.c [new file with mode: 0644] patch | blob
FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers/mss_sys_services/mss_sys_services.h [new file with mode: 0644] patch | blob
FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers/mss_timer/mss_timer.h [new file with mode: 0644] patch | blob
FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers/mss_uart/mss_uart.c [new file with mode: 0644] patch | blob
FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers/mss_uart/mss_uart.h [new file with mode: 0644] patch | blob
FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers/mss_uart/mss_uart_regs.h [new file with mode: 0644] patch | blob
FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers_config/sys_config/sys_config.c [new file with mode: 0644] patch | blob
FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers_config/sys_config/sys_config.h [new file with mode: 0644] patch | blob
FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers_config/sys_config/sys_config_mss_clocks.h [new file with mode: 0644] patch | blob
FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/hal/CortexM3/GNU/cpu_types.h [new file with mode: 0644] patch | blob
FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/hal/CortexM3/GNU/hal.s [new file with mode: 0644] patch | blob
FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/hal/CortexM3/GNU/hw_macros.h [new file with mode: 0644] patch | blob
FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/hal/CortexM3/GNU/hw_reg_access.s [new file with mode: 0644] patch | blob
FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/hal/CortexM3/cortex_nvic.c [new file with mode: 0644] patch | blob
FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/hal/CortexM3/cortex_nvic.h [new file with mode: 0644] patch | blob
FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/hal/hal.h [new file with mode: 0644] patch | blob
FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/hal/hal_assert.h [new file with mode: 0644] patch | blob
FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/hal/hw_reg_access.h [new file with mode: 0644] patch | blob

diff --git a/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/CreateProjectDirectoryStructure.bat b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/CreateProjectDirectoryStructure.bat
new file mode 100644 (file)
index 0000000..efc8b8e
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/CreateProjectDirectoryStructure.bat
@@ -0,0 +1,65 @@
+REM This file should be executed from the command line prior to the first\r
+REM build.  It will be necessary to refresh the Eclipse project once the\r
+REM .bat file has been executed (normally just press F5 to refresh).\r
+\r
+REM Copies all the required files from their location within the standard\r
+REM FreeRTOS directory structure to under the Eclipse project directory.\r
+REM This permits the Eclipse project to be used in 'managed' mode and without\r
+REM having to setup any linked resources.\r
+\r
+REM Standard paths\r
+SET FREERTOS_SOURCE=..\..\Source\r
+SET COMMON_SOURCE=..\Common\minimal\r
+SET COMMON_INCLUDE=..\Common\include\r
+SET CLI_SOURCE=..\..\..\FreeRTOS-Plus\Source\FreeRTOS-Plus-CLI\r
+SET FAT_SOURCE=..\..\..\FreeRTOS-Plus\Source\FreeRTOS-Plus-FAT-SL\r
+\r
+REM Have the files already been copied?\r
+IF EXIST RTOSDemo\FreeRTOS-Source Goto END\r
+\r
+    REM Create the required directory structure.\r
+    MD RTOSDemo\FreeRTOS-Source\r
+    MD RTOSDemo\FreeRTOS-Source\include\r
+    MD RTOSDemo\FreeRTOS-Source\portable\r
+    MD RTOSDemo\FreeRTOS-Source\portable\GCC\r
+    MD RTOSDemo\FreeRTOS-Source\portable\GCC\ARM_CM3\r
+    MD RTOSDemo\FreeRTOS-Source\portable\MemMang\r
+\r
+    REM Copy the core kernel files into the project directory\r
+    copy %FREERTOS_SOURCE%\tasks.c RTOSDemo\FreeRTOS-Source\r
+    copy %FREERTOS_SOURCE%\queue.c RTOSDemo\FreeRTOS-Source\r
+    copy %FREERTOS_SOURCE%\list.c RTOSDemo\FreeRTOS-Source\r
+    copy %FREERTOS_SOURCE%\timers.c RTOSDemo\FreeRTOS-Source\r
+\r
+    REM Copy the common header files into the project directory\r
+    copy %FREERTOS_SOURCE%\include\*.* RTOSDemo\FreeRTOS-Source\include\r
+\r
+    REM Copy the portable layer files into the project directory\r
+    copy %FREERTOS_SOURCE%\portable\GCC\ARM_CM3\*.* RTOSDemo\FreeRTOS-Source\portable\GCC\ARM_CM3\r
+\r
+    REM Copy the memory allocation files into the project directory\r
+    copy %FREERTOS_SOURCE%\portable\MemMang\heap_4.c RTOSDemo\FreeRTOS-Source\portable\MemMang\r
+\r
+    REM Copy the files that define the common demo tasks.\r
+    copy %COMMON_SOURCE%\dynamic.c         RTOSDemo\Full-Demo\Common-Demo-Source\r
+    copy %COMMON_SOURCE%\BlockQ.c          RTOSDemo\Full-Demo\Common-Demo-Source\r
+    copy %COMMON_SOURCE%\flash_timer.c     RTOSDemo\Full-Demo\Common-Demo-Source\r
+    copy %COMMON_SOURCE%\death.c           RTOSDemo\Full-Demo\Common-Demo-Source\r
+    copy %COMMON_SOURCE%\blocktim.c        RTOSDemo\Full-Demo\Common-Demo-Source\r
+    copy %COMMON_SOURCE%\semtest.c         RTOSDemo\Full-Demo\Common-Demo-Source\r
+    copy %COMMON_SOURCE%\PollQ.c           RTOSDemo\Full-Demo\Common-Demo-Source\r
+    copy %COMMON_SOURCE%\GenQTest.c        RTOSDemo\Full-Demo\Common-Demo-Source\r
+    copy %COMMON_SOURCE%\recmutex.c        RTOSDemo\Full-Demo\Common-Demo-Source\r
+    copy %COMMON_SOURCE%\countsem.c        RTOSDemo\Full-Demo\Common-Demo-Source\r
+    copy %COMMON_SOURCE%\integer.c         RTOSDemo\Full-Demo\Common-Demo-Source\r
+\r
+    REM Copy the common demo file headers.\r
+    copy %COMMON_INCLUDE%\*.h              RTOSDemo\Full-Demo\Common-Demo-Source\include\r
+\r
+       REM Copy the FreeRTOS+CLI source.\r
+       copy %CLI_SOURCE%\*.*                  RTOSDemo\Full-Demo\FreeRTOS-Plus-CLI-Source\r
+\r
+       REM Copy the FreeRTOS+FAT SL source.\r
+       xcopy %FAT_SOURCE%\*.*                 RTOSDemo\Full-Demo\FreeRTOS-Plus-FAT-SL-Source /S\r
+\r
+: END\r
diff --git a/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/LiberoOutput/DEV_KIT_DEMO_top.stp b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/LiberoOutput/DEV_KIT_DEMO_top.stp
new file mode 100644 (file)
index 0000000..be3730f
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/LiberoOutput/DEV_KIT_DEMO_top.stp
@@ -0,0 +1,49148 @@
+NOTE "CREATOR" "FlashPro Version: v11.0";\r
+NOTE "CAPTURE" "11.0.0.23";\r
+NOTE "DEVICE" "M2S050T_ES";\r
+NOTE "PACKAGE" "M2S050T_ES-fg896";\r
+NOTE "DATE" "2013/04/24";\r
+NOTE "TIME" "17:10:34";\r
+NOTE "STAPL_VERSION" "JESD71";\r
+NOTE "VENDOR" "Microsemi Corporation";\r
+NOTE "IDCODE" "0F8021CF";\r
+NOTE "IDMASK" "0FFFFFFF";\r
+NOTE "DESIGN" "DEV_KIT_DEMO_top";\r
+NOTE "DESIGN_DIRECTORY" "";\r
+NOTE "CHECKSUM" "B72B";\r
+NOTE "SECURITY" "Disable";\r
+NOTE "ALG_VERSION" "1";\r
+NOTE "MAP_VERSION" "0";\r
+NOTE "TOOL_VERSION" "1";\r
+NOTE "MAX_FREQ" "10000000";\r
+NOTE "SILSIG" "00000000";\r
+NOTE "SPEED_GRAD" "-1";\r
+NOTE "TEMP_GRAD" "COM";\r
+NOTE "PLAYER_VERSION_VARIABLE" "PLAYERVERSIONVARIABLE";\r
+NOTE "PLAYER_VERSION_SW_VARIABLE" "PLAYERVERSIONSWVARIABLE";\r
+\r
+ACTION PROGRAM = \r
+       VERIFY_IDCODE,\r
+       DO_PROGRAM_ENVM,\r
+       DO_VERIFY_ENVM OPTIONAL,\r
+       PROC_ENABLE,\r
+       DO_PROGRAM,\r
+       DO_VERIFY OPTIONAL,\r
+       DO_EXIT;\r
+ACTION VERIFY = \r
+       VERIFY_IDCODE,\r
+       DO_VERIFY_ENVM,\r
+       PROC_ENABLE,\r
+       DO_VERIFY,\r
+       DO_EXIT;\r
+ACTION ENC_DATA_AUTHENTICATION = \r
+       VERIFY_IDCODE,\r
+       DO_AUTHENTICATION_ENVM,\r
+       DO_AUTHENTICATION,\r
+       DO_EXIT;\r
+ACTION READ_IDCODE = \r
+       VERIFY_IDCODE,\r
+       PRINT_IDCODE,\r
+       DO_EXIT;\r
+ACTION DEVICE_INFO = \r
+       VERIFY_IDCODE,\r
+       DO_DEVICE_INFO,\r
+       DO_EXIT;\r
+\r
+\r
+\r
+DATA PARAMETERS;\r
+    INTEGER FREQ =4;\r
+ENDDATA;\r
+\r
+DATA GV;\r
+    BOOLEAN ID[32];\r
+    BOOLEAN PASS = 1;\r
+    BOOLEAN BUFF32[32];\r
+    INTEGER STATUS =0;\r
+    INTEGER DATAINDEX =0;\r
+    INTEGER ICURNUMOFCOMPONENTS =0;\r
+    INTEGER ICURCOMPONENTNO =0;\r
+    INTEGER IPOLL =0;\r
+    INTEGER BPGMMODE =0;\r
+    INTEGER I =0;\r
+    INTEGER INUMOFBLOCKS =0;\r
+    BOOLEAN SHARED_BUFFER[4736];\r
+    BOOLEAN ACT_UROW_ALGO_VERSION[6] = $01;\r
+    BOOLEAN ACT_UROW_PGM_TYPE[4];\r
+    BOOLEAN ACT_UROW_SW_VERSION[7];\r
+    BOOLEAN ACT_UROW_PROGRAM_SW[4];\r
+    INTEGER HEX[16] = 70,69,68,67,66,65,57,56,55,54,53,52,51,50,49,48;\r
+    BOOLEAN PGMMODE[8];\r
+    BOOLEAN DATA_STATUS_RESULT[32];\r
+    BOOLEAN READ_PROG_INFO_RESULT[128];\r
+    BOOLEAN KEYHI_REG[128];\r
+    BOOLEAN KEYLO_REG[128];\r
+    BOOLEAN IDCODEVALUE[32] = $0f8021cf;\r
+    BOOLEAN IDMASK[32] = $0fffffff;\r
+    INTEGER IDREV;\r
+    INTEGER IDFAB;\r
+    BOOLEAN BSRPATTERN[1146] = $249249249249249249249249249249249249249249249249\r
+        249249249249249249249249249249249249249249249249249249249249249249249249\r
+        249249249249249249249249249249249249249249249249249249249249249249249249\r
+        249249249249249249249249249249249249249249249249249249249249249249249249\r
+        24924924924924924924924;\r
+    BOOLEAN SAMPLEMASK[1146] = $000000000000000000000000000000000000000000000000\r
+        000000000000000000000000000000000000000000000000000000000000000000000000\r
+        000000000000000000000000000000000000000000000000000000000000000000000000\r
+        000000000000000000000000000000000000000000000000000000000000000000000000\r
+        00000000000000000000000;\r
+    BOOLEAN BSR[1146];\r
+    BOOLEAN SAMPLE_DEVICE[1146];\r
+    BOOLEAN SEC_UL[96];\r
+    BOOLEAN SEC_UKL[12];\r
+    BOOLEAN SEC_VL[12];\r
+    BOOLEAN SEC_OPOK[4];\r
+    BOOLEAN SEC_CCNFG[8];\r
+    BOOLEAN SEC_USERCODE[32];\r
+    BOOLEAN SEC_UCNFG[46];\r
+    BOOLEAN SEC_CL[12];\r
+    BOOLEAN SEC_DL[12];\r
+    BOOLEAN SECURITY_QUERIED = 0;\r
+    INTEGER DATASTARTINDEX =0;\r
+    INTEGER DATAENVMSTARTINDEX =19351168;\r
+    INTEGER DATAENVMSIZE =3;\r
+    INTEGER DATASIZE =4;\r
+    INTEGER NUMOFCOMPONENTS =7;\r
+    BOOLEAN NUMOFBLOCKS[154] = $000019003f4c000200000640005b0937e400020;\r
+    BOOLEAN TOOL_INFO[32] = $00000000;\r
+    INTEGER LABEL_SEPARATOR;\r
+ENDDATA;\r
+\r
+DATA CONSTBLOCK;\r
+    INTEGER SELF=1;\r
+    INTEGER SCULPTW=3;\r
+    INTEGER BPWIN=4;\r
+    INTEGER ACTEL_IHP=5;\r
+    INTEGER FP3=2;\r
+    INTEGER FP4=7;\r
+    INTEGER FP_FTDI=8;\r
+    INTEGER SIL_EXPL=9;\r
+    INTEGER ATE=14;\r
+    INTEGER FP34=1;\r
+    INTEGER FP40=2;\r
+    INTEGER FP41=3;\r
+    INTEGER FP42=4;\r
+    INTEGER FP50=5;\r
+    INTEGER FP51=6;\r
+    INTEGER FP60=7;\r
+    INTEGER FP61=8;\r
+    INTEGER FP62=9;\r
+    INTEGER FP84=11;\r
+    INTEGER FP85=12;\r
+    INTEGER FP86=13;\r
+    INTEGER FP90=14;\r
+    INTEGER FP91=15;\r
+    INTEGER FP_10_LCP=16;\r
+    INTEGER FP_11_BETA_SPA=17;\r
+    INTEGER FP_11_BETA_SP1=18;\r
+    INTEGER FP_11=19;\r
+    INTEGER FP=1;\r
+    INTEGER DIRECTC=2;\r
+    INTEGER NON_ACTEL=6;\r
+    INTEGER SPI_MASTER=1;\r
+    INTEGER SPI_SLAVE=2;\r
+    INTEGER JTAG=3;\r
+    INTEGER I2C_MASTER=4;\r
+    INTEGER I2C_SLAVE=5;\r
+    INTEGER PDB=1;\r
+    INTEGER STAPL=2;\r
+    INTEGER SVF=3;\r
+    INTEGER PCF=4;\r
+    INTEGER IEEE1532=5;\r
+ENDDATA;\r
+\r
+DATA BITSTREAM;\r
+    BOOLEAN DATASTREAM[19876992] = @GcU90eQH5XP43ehXdCL5C@w3P5CaLzX16b4d8LcDRY7U\r
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+        U6HkG2timRihRA_vasmSsIZT4aLaTi326BBRlz7umatvpVRwdzQnKRc7MCzE0zzFs@jAnFFd\r
+        16C9W6wYfymZSYsTquILty2D9gaQCKuvpXisi6TW5QelkzWBwxHMCNoOFCg@FGASRlpEGwcn\r
+        NCFo4@gtxG_6EHKQKCu5OsfR9DggAPMmnqiG1EfMRArjRGRrezPfbATGCJqv86d8o0hp2gag\r
+        pymdnRw0DFJhQOEAvNPPq22EeGZ1hejGoqOn28eBuceKol6I8Bi9XmhbHO0Jpt9GA@ws5qoN\r
+        3Inq810kU3oNNny3vc_AsNd_gmIais5@qA1pJS2XrsegHnVK2m6Shq6mY_mGyXDcyMaEVXmO\r
+        Pqcgkog_CscgG1QDpXvr5toH8k58iqEdiG91CfvbOGHDMXjfqDPMHMevtAf5i@Ql5kJpIC9u\r
+        YdHyjyE6cwy8_kjvgth0OSJekiEPRIj66_u2uWF5RRymJHf8kenHVPIvniB2g9BWIWLvB19a\r
+        27X45P@vNqUl47WB@dff5gtmnfbSr_1DKML2B_RHYoN8w@83eKza6OfSMSqjeyPSyo@zxgcX\r
+        WmMjF__xRqztCk4qxrnYeX1wpqR8alVLg3xWmi4lnBGgZx8Sa4oCWUXnXuETmQMOg3Hjc8qf\r
+        jjj6d0LF@yiUbfPsgEOkL1lcxd7uIxhmlwovMWqKP60XeOxiZGIOGIlwVWZQQBHZZZuV@YDD\r
+        y0n3o863FqbTNI2MAZLW1OIC22MZ3H7dCrIgaLhOTpv2WtnFX3gbZTgKrUA1ZqMS9hJr0KAw\r
+        LDgIfmVtyKHzW6K_64LO1e6Cz@9dqZgFz5Hq4EcqZnFbFPX2b6FCQhr2OjMdzVpg33YOzECb\r
+        qQEXjoHF3EwK6APA3CadCFOJx8GafT6DF2W8iMDx9CT6WUUisJmHCFv36WQTM9qankEklBR8\r
+        RUvMfsDepK@G0jpKSsiCu0c8LMRlQ_GSDrMdHbUcog0i3n_eIhPQDCuD0jZ2kpKLQmDr55el\r
+        tTak1TO6nE9XULurnHNxy0COw0Nf4mmm@M6bEpB10bQ1s5U8MezT8dBnCRMo5VtM24oA6A60\r
+        BaquUJhRcQ6jAKBvBYIkQq_kdav2@MXO5U823bDEoRGWbd6000m00@F0m@30y@000vYuFmRo\r
+        G9iAUACO12SkwmLbf@R_di3pzwab7HSTjzCkrJ8uKKv8_KDmnCR8Q5KMkUcuCBxqP86LBCFK\r
+        s9HcW9796OtKc2QFYKP62vuPk1H4rcDqyF20W0dAy@00T1;\r
+ENDDATA;\r
+\r
+\r
+PROCEDURE READ_FSN USES GV;\r
+    BOOLEAN READ_FSN_RESULT[129];\r
+    PASS = 0;\r
+    READ_FSN_RESULT[128..0] = $000000000000000000000000000000000;\r
+    IRSTOP IRPAUSE;\r
+    DRSTOP DRPAUSE;\r
+    IRSCAN 8, $f0;\r
+    DRSCAN 129, READ_FSN_RESULT[];\r
+    WAIT IDLE, 3 CYCLES;\r
+    WAIT 10 USEC, DRPAUSE;\r
+    FOR IPOLL = 100000 TO 0 STEP -1;\r
+        DRSCAN 129, $000000000000000000000000000000000, CAPTURE READ_FSN_RESULT[];\r
+        IF ( ! (READ_FSN_RESULT[128]==0) ) THEN GOTO READ_FSN_POLL;\r
+        IPOLL = 0;\r
+        PASS = 1;\r
+        READ_FSN_POLL:\r
+        IF ( ! (PASS==0) ) THEN GOTO READ_FSN_DONE;\r
+        IRSCAN 8, $f0;\r
+        WAIT IRPAUSE, 10 USEC;\r
+        READ_FSN_DONE:\r
+        LABEL_SEPARATOR = 0;\r
+    NEXT IPOLL;\r
+    IF ( ! (PASS==0) ) THEN GOTO READ_FSN_COMPLETE;\r
+    PRINT "Failed to read FSN.";\r
+    STATUS = -24;\r
+    READ_FSN_COMPLETE:\r
+    PRINT "===================================================================================";\r
+    EXPORT "DSN", READ_FSN_RESULT[127..0];\r
+    PRINT "===================================================================================";\r
+ENDPROC;\r
+\r
+PROCEDURE DO_EXIT USES GV;\r
+    PRINT "Please power cycle your board.";\r
+    EXIT STATUS;\r
+ENDPROC;\r
+\r
+PROCEDURE LOAD_KEYLO USES GV,DO_EXIT;\r
+    BOOLEAN KEYLO_RESULT[128];\r
+    PASS = 0;\r
+    IRSTOP IRPAUSE;\r
+    DRSTOP DRPAUSE;\r
+    IRSCAN 8, $eb;\r
+    DRSCAN 128, KEYLO_REG[];\r
+    WAIT IDLE, 3 CYCLES;\r
+    WAIT 10 USEC, DRPAUSE;\r
+    FOR IPOLL = 100000 TO 0 STEP -1;\r
+        DRSCAN 128, $00000000000000000000000000000000, CAPTURE KEYLO_RESULT[127..0];\r
+        IF ( ! (KEYLO_RESULT[127]==0) ) THEN GOTO KEYLO_POLL;\r
+        IPOLL = 0;\r
+        PASS = 1;\r
+        KEYLO_POLL:\r
+        IF ( ! (PASS==0) ) THEN GOTO KEYLO_DONE;\r
+        IRSCAN 8, $eb;\r
+        WAIT IRPAUSE, 10 USEC;\r
+        KEYLO_DONE:\r
+        LABEL_SEPARATOR = 0;\r
+    NEXT IPOLL;\r
+    IF ( ! (PASS==0) ) THEN GOTO KEYLO_PASS;\r
+    PRINT "Failed to load keylo.";\r
+    EXPORT "keylo_result", KEYLO_RESULT[127..0];\r
+    STATUS = -35;\r
+    CALL DO_EXIT;\r
+    KEYLO_PASS:\r
+    LABEL_SEPARATOR = 0;\r
+ENDPROC;\r
+\r
+PROCEDURE LOAD_KEYHI USES GV,DO_EXIT;\r
+    BOOLEAN KEYHI_RESULT[128];\r
+    PASS = 0;\r
+    IRSTOP IRPAUSE;\r
+    DRSTOP DRPAUSE;\r
+    IRSCAN 8, $ec;\r
+    DRSCAN 128, KEYHI_REG[];\r
+    WAIT IDLE, 3 CYCLES;\r
+    WAIT 10 USEC, DRPAUSE;\r
+    FOR IPOLL = 100000 TO 0 STEP -1;\r
+        DRSCAN 128, $00000000000000000000000000000000, CAPTURE KEYHI_RESULT[127..0];\r
+        IF ( ! (KEYHI_RESULT[127]==0) ) THEN GOTO KEYHI_POLL;\r
+        IPOLL = 0;\r
+        PASS = 1;\r
+        KEYHI_POLL:\r
+        IF ( ! (PASS==0) ) THEN GOTO KEYHI_DONE;\r
+        IRSCAN 8, $ec;\r
+        WAIT IRPAUSE, 10 USEC;\r
+        KEYHI_DONE:\r
+        LABEL_SEPARATOR = 0;\r
+    NEXT IPOLL;\r
+    IF ( ! (PASS==0) ) THEN GOTO KEYHI_PASS;\r
+    PRINT "Failed to load keyhi.";\r
+    EXPORT "keyhi_result", KEYHI_RESULT[127..0];\r
+    STATUS = -35;\r
+    CALL DO_EXIT;\r
+    KEYHI_PASS:\r
+    LABEL_SEPARATOR = 0;\r
+ENDPROC;\r
+\r
+PROCEDURE DUMP_SECURITY_INFO USES GV;\r
+    PRINT "--- Security locks and configuration settings ---";\r
+    EXPORT "QUERY_SECURITY", SHARED_BUFFER[335..0];\r
+    IF ( ! (SECURITY_QUERIED==1) ) THEN GOTO Label_0;\r
+    IF ( ! (SEC_UL[0]==1) ) THEN GOTO JTAGTESTDIS_SELECT;\r
+    PRINT "JTAG test instructions are disabled.";\r
+    JTAGTESTDIS_SELECT:\r
+    IF ( ! (SEC_UL[1]==1) ) THEN GOTO USL_SELECT;\r
+    PRINT "User lock segment is protected.";\r
+    USL_SELECT:\r
+    IF ( ! (SEC_UL[2]==1) ) THEN GOTO UEWL_SELECT;\r
+    PRINT "FPGA array erase/write protected.";\r
+    UEWL_SELECT:\r
+    IF ( ! (SEC_UL[3]==1) ) THEN GOTO UVL_SELECT;\r
+    PRINT "Fabric verify is protected.";\r
+    UVL_SELECT:\r
+    IF ( ! (SEC_UL[4]==1) ) THEN GOTO UPTL_SELECT;\r
+    PRINT "User key 1/2 encrypted programming is enforced for the FPGA Array.";\r
+    UPTL_SELECT:\r
+    IF ( ! (SEC_UL[8]==1) ) THEN GOTO UL_JTAG_PROG_SELECT;\r
+    PRINT "JTAG programming interface is protected.";\r
+    UL_JTAG_PROG_SELECT:\r
+    IF ( ! (SEC_UL[9]==1) ) THEN GOTO UL_SPI_PROG_SELECT;\r
+    PRINT "SPI slave programming interface is protected.";\r
+    UL_SPI_PROG_SELECT:\r
+    IF ( ! (SEC_UL[11]==1) ) THEN GOTO USPL_SELECT;\r
+    PRINT "User security is permanently locked.";\r
+    USPL_SELECT:\r
+    IF ( ! (SEC_UL[12]==1) ) THEN GOTO UL_E0_R_SELECT;\r
+    PRINT "Debug read access to eNVM module 0 is protected.";\r
+    UL_E0_R_SELECT:\r
+    IF ( ! (SEC_UL[13]==1) ) THEN GOTO UL_E1_R_SELECT;\r
+    PRINT "Debug read access to eNVM module 1 is protected.";\r
+    UL_E1_R_SELECT:\r
+    IF ( ! (SEC_UL[17]==1) ) THEN GOTO UL_E0_PT_SELECT;\r
+    PRINT "User key 1/2 encrypted programming is enforced for eNVM module 0.";\r
+    UL_E0_PT_SELECT:\r
+    IF ( ! (SEC_UL[18]==1) ) THEN GOTO UL_PROG_SVC_ENABLE_SELECT;\r
+    PRINT "IAP/ISP services are protected.";\r
+    UL_PROG_SVC_ENABLE_SELECT:\r
+    IF ( ! (SEC_UL[26]==1) ) THEN GOTO UL_EXTDIGEST_ENABLE_SELECT;\r
+    PRINT "Digest requests from SPI/JTAG is protected.";\r
+    UL_EXTDIGEST_ENABLE_SELECT:\r
+    IF ( ! (SEC_UL[27]==1) ) THEN GOTO UL_REFLASH_ENABLE_SELECT;\r
+    PRINT "Auto Programming is protected.";\r
+    UL_REFLASH_ENABLE_SELECT:\r
+    IF ( ! (SEC_UL[28]==1) ) THEN GOTO UL_BACKLEVEL_DISABLE_SELECT;\r
+    PRINT "BACKLEVEL checking is enabled.";\r
+    UL_BACKLEVEL_DISABLE_SELECT:\r
+    IF ( ! (SEC_UL[31]==1) ) THEN GOTO UL_BUS_IDS_ESRAM0_R_SELECT;\r
+    PRINT "Arm CortexM3 access to eSRAM module 0 read is protected.";\r
+    UL_BUS_IDS_ESRAM0_R_SELECT:\r
+    IF ( ! (SEC_UL[32]==1) ) THEN GOTO UL_BUS_IDS_ESRAM0_W_SELECT;\r
+    PRINT "Arm CortexM3 access to eSRAM module 0 write is protected.";\r
+    UL_BUS_IDS_ESRAM0_W_SELECT:\r
+    IF ( ! (SEC_UL[33]==1) ) THEN GOTO UL_BUS_IDS_ESRAM1_R_SELECT;\r
+    PRINT "Arm CortexM3 access to eSRAM module 1 read is protected.";\r
+    UL_BUS_IDS_ESRAM1_R_SELECT:\r
+    IF ( ! (SEC_UL[34]==1) ) THEN GOTO UL_BUS_IDS_ESRAM1_W_SELECT;\r
+    PRINT "Arm CortexM3 access to eSRAM module 1 write is protected.";\r
+    UL_BUS_IDS_ESRAM1_W_SELECT:\r
+    IF ( ! (SEC_UL[35]==1) ) THEN GOTO UL_BUS_IDS_ENVM0_R_SELECT;\r
+    PRINT "Arm CortexM3 access to eNVM module 0 read is protected.";\r
+    UL_BUS_IDS_ENVM0_R_SELECT:\r
+    IF ( ! (SEC_UL[36]==1) ) THEN GOTO UL_BUS_IDS_ENVM0_W_SELECT;\r
+    PRINT "Arm CortexM3 access to eNVM module 0 write is protected.";\r
+    UL_BUS_IDS_ENVM0_W_SELECT:\r
+    IF ( ! (SEC_UL[37]==1) ) THEN GOTO UL_BUS_IDS_ENVM1_R_SELECT;\r
+    PRINT "Arm CortexM3 access to eNVM module 1 read is protected.";\r
+    UL_BUS_IDS_ENVM1_R_SELECT:\r
+    IF ( ! (SEC_UL[38]==1) ) THEN GOTO UL_BUS_IDS_ENVM1_W_SELECT;\r
+    PRINT "Arm CortexM3 access to eNVM module 1 write is protected.";\r
+    UL_BUS_IDS_ENVM1_W_SELECT:\r
+    IF ( ! (SEC_UL[39]==1) ) THEN GOTO UL_BUS_IDS_DDR_R_SELECT;\r
+    PRINT "Arm CortexM3 access to DDR bridge read is protected.";\r
+    UL_BUS_IDS_DDR_R_SELECT:\r
+    IF ( ! (SEC_UL[40]==1) ) THEN GOTO UL_BUS_IDS_DDR_W_SELECT;\r
+    PRINT "Arm CortexM3 access to DDR bridge write is protected.";\r
+    UL_BUS_IDS_DDR_W_SELECT:\r
+    IF ( ! (SEC_UL[41]==1) ) THEN GOTO UL_BUS_FIC_ESRAM0_R_SELECT;\r
+    PRINT "Fabric access to eSRAM module 0 read is protected.";\r
+    UL_BUS_FIC_ESRAM0_R_SELECT:\r
+    IF ( ! (SEC_UL[42]==1) ) THEN GOTO UL_BUS_FIC_ESRAM0_W_SELECT;\r
+    PRINT "Fabric access to eSRAM module 0 write is protected.";\r
+    UL_BUS_FIC_ESRAM0_W_SELECT:\r
+    IF ( ! (SEC_UL[43]==1) ) THEN GOTO UL_BUS_FIC_ESRAM1_R_SELECT;\r
+    PRINT "Fabric access to eSRAM module 1 read is protected.";\r
+    UL_BUS_FIC_ESRAM1_R_SELECT:\r
+    IF ( ! (SEC_UL[44]==1) ) THEN GOTO UL_BUS_FIC_ESRAM1_W_SELECT;\r
+    PRINT "Fabric access to eSRAM module 1 write is protected.";\r
+    UL_BUS_FIC_ESRAM1_W_SELECT:\r
+    IF ( ! (SEC_UL[45]==1) ) THEN GOTO UL_BUS_FIC_ENVM0_R_SELECT;\r
+    PRINT "Fabric access to eNVM module 0 read is protected.";\r
+    UL_BUS_FIC_ENVM0_R_SELECT:\r
+    IF ( ! (SEC_UL[46]==1) ) THEN GOTO UL_BUS_FIC_ENVM0_W_SELECT;\r
+    PRINT "Fabric access to eNVM module 0 write is protected.";\r
+    UL_BUS_FIC_ENVM0_W_SELECT:\r
+    IF ( ! (SEC_UL[47]==1) ) THEN GOTO UL_BUS_FIC_ENVM1_R_SELECT;\r
+    PRINT "Fabric access to eNVM module 1 read is protected.";\r
+    UL_BUS_FIC_ENVM1_R_SELECT:\r
+    IF ( ! (SEC_UL[48]==1) ) THEN GOTO UL_BUS_FIC_ENVM1_W_SELECT;\r
+    PRINT "Fabric access to eNVM module 1 write is protected.";\r
+    UL_BUS_FIC_ENVM1_W_SELECT:\r
+    IF ( ! (SEC_UL[49]==1) ) THEN GOTO UL_BUS_FIC_DDR_R_SELECT;\r
+    PRINT "Fabric access to DDR bridge read is protected.";\r
+    UL_BUS_FIC_DDR_R_SELECT:\r
+    IF ( ! (SEC_UL[50]==1) ) THEN GOTO UL_BUS_FIC_DDR_W_SELECT;\r
+    PRINT "Fabric access to DDR bridge write is protected.";\r
+    UL_BUS_FIC_DDR_W_SELECT:\r
+    IF ( ! (SEC_UL[51]==1) ) THEN GOTO UL_BUS_EXT_ESRAM0_R_SELECT;\r
+    PRINT "External master access to eSRAM module 0 read is protected.";\r
+    UL_BUS_EXT_ESRAM0_R_SELECT:\r
+    IF ( ! (SEC_UL[52]==1) ) THEN GOTO UL_BUS_EXT_ESRAM0_W_SELECT;\r
+    PRINT "External master access to eSRAM module 0 write is protected.";\r
+    UL_BUS_EXT_ESRAM0_W_SELECT:\r
+    IF ( ! (SEC_UL[53]==1) ) THEN GOTO UL_BUS_EXT_ESRAM1_R_SELECT;\r
+    PRINT "External master access to eSRAM module 1 read is protected.";\r
+    UL_BUS_EXT_ESRAM1_R_SELECT:\r
+    IF ( ! (SEC_UL[54]==1) ) THEN GOTO UL_BUS_EXT_ESRAM1_W_SELECT;\r
+    PRINT "External master access to eSRAM module 1 write is protected.";\r
+    UL_BUS_EXT_ESRAM1_W_SELECT:\r
+    IF ( ! (SEC_UL[55]==1) ) THEN GOTO UL_BUS_EXT_ENVM0_R_SELECT;\r
+    PRINT "External master access to eNVM module 0 read is protected.";\r
+    UL_BUS_EXT_ENVM0_R_SELECT:\r
+    IF ( ! (SEC_UL[56]==1) ) THEN GOTO UL_BUS_EXT_ENVM0_W_SELECT;\r
+    PRINT "External master access to eNVM module 0 write is protected.";\r
+    UL_BUS_EXT_ENVM0_W_SELECT:\r
+    IF ( ! (SEC_UL[57]==1) ) THEN GOTO UL_BUS_EXT_ENVM1_R_SELECT;\r
+    PRINT "External master access to eNVM module 1 read is protected.";\r
+    UL_BUS_EXT_ENVM1_R_SELECT:\r
+    IF ( ! (SEC_UL[58]==1) ) THEN GOTO UL_BUS_EXT_ENVM1_W_SELECT;\r
+    PRINT "External master access to eNVM module 1 write is protected.";\r
+    UL_BUS_EXT_ENVM1_W_SELECT:\r
+    IF ( ! (SEC_UL[59]==1) ) THEN GOTO UL_BUS_EXT_DDR_R_SELECT;\r
+    PRINT "External master access to DDR bridge read is protected.";\r
+    UL_BUS_EXT_DDR_R_SELECT:\r
+    IF ( ! (SEC_UL[60]==1) ) THEN GOTO UL_BUS_EXT_DDR_W_SELECT;\r
+    PRINT "External master access to DDR bridge write is protected.";\r
+    UL_BUS_EXT_DDR_W_SELECT:\r
+    IF ( ! (SEC_UL[65]==1) ) THEN GOTO UL_BUS_SII_ENVM0_R_SELECT;\r
+    PRINT "eNVM Module 0 is read/verify protected.";\r
+    UL_BUS_SII_ENVM0_R_SELECT:\r
+    IF ( ! (SEC_UL[66]==1) ) THEN GOTO UL_BUS_SII_ENVM0_W_SELECT;\r
+    PRINT "eNVM module 0 is erase/write protected.";\r
+    UL_BUS_SII_ENVM0_W_SELECT:\r
+    IF ( ! (SEC_UL[71]==1) ) THEN GOTO UL_M3_ALLOWED_L0_SELECT;\r
+    PRINT "Arm CortexM3 access to eNVM module 0 lower sector is protected.";\r
+    UL_M3_ALLOWED_L0_SELECT:\r
+    IF ( ! (SEC_UL[72]==1) ) THEN GOTO UL_FAB_ALLOWED_L0_SELECT;\r
+    PRINT "Fabric access to eNVM module 0 lower sector is protected.";\r
+    UL_FAB_ALLOWED_L0_SELECT:\r
+    IF ( ! (SEC_UL[73]==1) ) THEN GOTO UL_OTHERS_ALLOWED_L0_SELECT;\r
+    PRINT "Other masters access to eNVM module 0 lower sector is protected.";\r
+    UL_OTHERS_ALLOWED_L0_SELECT:\r
+    IF ( ! (SEC_UL[74]==1) ) THEN GOTO UL_WRITE_ALLOWED_L0_SELECT;\r
+    PRINT "Master write access to eNVM module 0 lower sector is protected.";\r
+    UL_WRITE_ALLOWED_L0_SELECT:\r
+    IF ( ! (SEC_UL[75]==1) ) THEN GOTO UL_M3_ALLOWED_U0_SELECT;\r
+    PRINT "Arm CortexM3 access to eNVM module 0 upper sector is protected.";\r
+    UL_M3_ALLOWED_U0_SELECT:\r
+    IF ( ! (SEC_UL[76]==1) ) THEN GOTO UL_FAB_ALLOWED_U0_SELECT;\r
+    PRINT "Fabric access to eNVM module 0 upper sector is protected.";\r
+    UL_FAB_ALLOWED_U0_SELECT:\r
+    IF ( ! (SEC_UL[77]==1) ) THEN GOTO UL_OTHERS_ALLOWED_U0_SELECT;\r
+    PRINT "Other masters access to eNVM module 0 upper sector is protected.";\r
+    UL_OTHERS_ALLOWED_U0_SELECT:\r
+    IF ( ! (SEC_UL[78]==1) ) THEN GOTO UL_WRITE_ALLOWED_U0_SELECT;\r
+    PRINT "Master write access to eNVM module 0 upper sector is protected.";\r
+    UL_WRITE_ALLOWED_U0_SELECT:\r
+    IF ( ! (SEC_UL[30]==1) ) THEN GOTO UL_AUTO_DIGEST_POR_SELECT;\r
+    PRINT "Automatic digest check at power up is enabled.";\r
+    IF ( ! ( (SEC_UCNFG[4]==1)&&(SEC_UL[10]==0)) ) THEN GOTO AUTODIGEST_FABRIC_SELECT;\r
+    PRINT "FPGA array power on digest is enabled.";\r
+    AUTODIGEST_FABRIC_SELECT:\r
+    IF ( ! (SEC_UCNFG[5]==1) ) THEN GOTO AUTODIGEST_ENVM0_SELECT;\r
+    PRINT "eNVM module 0 power on digest is enabled.";\r
+    AUTODIGEST_ENVM0_SELECT:\r
+    LABEL_SEPARATOR = 0;\r
+    UL_AUTO_DIGEST_POR_SELECT:\r
+    IF ( ! (SEC_UKL[0]==1) ) THEN GOTO UKSL_SELECT;\r
+    PRINT "User Key Set 1 is erase/write protected.";\r
+    UKSL_SELECT:\r
+    IF ( ! (SEC_UKL[1]==1) ) THEN GOTO UKSVL_SELECT;\r
+    PRINT "User Key Set 1 is verify protected.";\r
+    UKSVL_SELECT:\r
+    IF ( ! (SEC_VL[0]==1) ) THEN GOTO VSL_SELECT;\r
+    PRINT "User Key Set 2 is erase/write protected.";\r
+    VSL_SELECT:\r
+    IF ( ! (SEC_VL[1]==1) ) THEN GOTO VSPL_SELECT;\r
+    PRINT "User Key Set 2 is permanently locked.";\r
+    VSPL_SELECT:\r
+    IF ( ! (INT(SEC_CCNFG[1..0])==0) ) THEN GOTO NOT_50US;\r
+    PRINT "Power on reset delay: 50us";\r
+    NOT_50US:\r
+    IF ( ! (INT(SEC_CCNFG[1..0])==1) ) THEN GOTO NOT_1MS;\r
+    PRINT "Power on reset delay: 1ms";\r
+    NOT_1MS:\r
+    IF ( ! (INT(SEC_CCNFG[1..0])==2) ) THEN GOTO NOT_10MS;\r
+    PRINT "Power on reset delay: 10ms";\r
+    NOT_10MS:\r
+    IF ( ! (INT(SEC_CCNFG[1..0])==3) ) THEN GOTO NOT_100MS;\r
+    PRINT "Power on reset delay: 100ms";\r
+    NOT_100MS:\r
+    IF ( ! (SEC_CCNFG[2]==1) ) THEN GOTO BG_AVM_DISABLE_SELECT;\r
+    PRINT "Avionics Mode is disabled.";\r
+    BG_AVM_DISABLE_SELECT:\r
+    IF ( ! (SEC_CCNFG[3]==0) ) THEN GOTO MODE1V_SELECT;\r
+    PRINT "Operational Voltage: 1.2V";\r
+    PRINT "Internal Oscillator: 50MHZ";\r
+    MODE1V_SELECT:\r
+    IF ( ! (SEC_CCNFG[3]==1) ) THEN GOTO MODE12V_SELECT;\r
+    PRINT "Operational Voltage: 1.0V";\r
+    PRINT "Internal Oscillator: 25MHZ";\r
+    MODE12V_SELECT:\r
+    IF ( ! (SEC_CL[0]==1) ) THEN GOTO OTPL_SELECT;\r
+    PRINT "FPGA Array is one time programmable.";\r
+    OTPL_SELECT:\r
+    LABEL_SEPARATOR = 0;\r
+    Label_0:\r
+    IF ( ! (SECURITY_QUERIED==0) ) THEN GOTO DUMP_SEC_CANNOTREAD;\r
+    PRINT "Security locks and configuration settings cannot be read from the device.";\r
+    PRINT "This could be because of debug locks, please use programming file with DPK.";\r
+    DUMP_SEC_CANNOTREAD:\r
+    PRINT "-------------------------------------------------\r
+    ";\r
+ENDPROC;\r
+\r
+PROCEDURE SET_PGM_MODE USES GV,DO_EXIT;\r
+    BOOLEAN MODE_RESULT[8];\r
+    PASS = 0;\r
+    IRSTOP IRPAUSE;\r
+    DRSTOP DRPAUSE;\r
+    IRSCAN 8, $af;\r
+    DRSCAN 8, $00;\r
+    WAIT IDLE, 3 CYCLES;\r
+    WAIT 10 USEC, DRPAUSE;\r
+    FOR IPOLL = 100000 TO 0 STEP -1;\r
+        DRSCAN 8, $00, CAPTURE MODE_RESULT[7..0];\r
+        IF ( ! (MODE_RESULT[7]==0) ) THEN GOTO MODE_POLL;\r
+        IPOLL = 0;\r
+        PASS = 1;\r
+        MODE_POLL:\r
+        IF ( ! (PASS==0) ) THEN GOTO MODE_DONE;\r
+        IRSCAN 8, $af;\r
+        WAIT IRPAUSE, 10 USEC;\r
+        MODE_DONE:\r
+        LABEL_SEPARATOR = 0;\r
+    NEXT IPOLL;\r
+    IF ( ! (PASS==0) ) THEN GOTO MODE_PASSED;\r
+    PRINT "Failed to set programming voltage";\r
+    STATUS = 5;\r
+    CALL DO_EXIT;\r
+    MODE_PASSED:\r
+    LABEL_SEPARATOR = 0;\r
+ENDPROC;\r
+\r
+PROCEDURE POLL_DEVICE_READY USES GV,DO_EXIT;\r
+    PASS = 0;\r
+    INTEGER ILOOP_0;\r
+    FOR ILOOP_0 = 1000000 - 1 TO 0 STEP -1;\r
+        IRSTOP IRPAUSE;\r
+        DRSTOP DRPAUSE;\r
+        IRSCAN 8, $8f;\r
+        WAIT IDLE, 1 CYCLES;\r
+        WAIT IDLE, 10 USEC;\r
+        DRSCAN 8, $00,COMPARE $00,$80,PASS;\r
+        IF PASS THEN ILOOP_0 = 0;\r
+    NEXT ILOOP_0;\r
+    IF ( ! (PASS==0) ) THEN GOTO DEVICE_READY;\r
+    PRINT "Device is busy.";\r
+    STATUS = 5;\r
+    CALL DO_EXIT;\r
+    DEVICE_READY:\r
+    LABEL_SEPARATOR = 0;\r
+ENDPROC;\r
+\r
+PROCEDURE READ_SHARED_BUFFER USES GV,DO_EXIT;\r
+    INTEGER IBLOCK =0;\r
+    BOOLEAN BLOCKBUFFER[129];\r
+    FOR IBLOCK = 0 TO (INUMOFBLOCKS-1) STEP 1;\r
+        PASS = 0;\r
+        BOOLEAN SHARED_BUFFER_RESULT[129];\r
+        BLOCKBUFFER[6..1] = BOOL(IBLOCK);\r
+        IRSTOP IRPAUSE;\r
+        DRSTOP DRPAUSE;\r
+        IRSCAN 8, $f2;\r
+        DRSCAN 129, BLOCKBUFFER[];\r
+        WAIT IDLE, 3 CYCLES;\r
+        WAIT 10 USEC, DRPAUSE;\r
+        FOR IPOLL = 100000 TO 0 STEP -1;\r
+            DRSCAN 129, $000000000000000000000000000000000, CAPTURE SHARED_BUFFER_RESULT[];\r
+            IF ( ! (SHARED_BUFFER_RESULT[128]==0) ) THEN GOTO READ_BUFFER_POLL;\r
+            IPOLL = 0;\r
+            PASS = 1;\r
+            READ_BUFFER_POLL:\r
+            IF ( ! (PASS==0) ) THEN GOTO READ_BUFFER_DONE;\r
+            IRSCAN 8, $f2;\r
+            WAIT IRPAUSE, 10 USEC;\r
+            READ_BUFFER_DONE:\r
+            LABEL_SEPARATOR = 0;\r
+        NEXT IPOLL;\r
+        IF ( ! (PASS==0) ) THEN GOTO READ_BUFFER_PASS;\r
+        PRINT "Failed to read design information.";\r
+        STATUS = 5;\r
+        CALL DO_EXIT;\r
+        READ_BUFFER_PASS:\r
+        SHARED_BUFFER[((128*IBLOCK)+127)..(128*IBLOCK)] = SHARED_BUFFER_RESULT[127..0];\r
+    NEXT IBLOCK;\r
+ENDPROC;\r
+\r
+PROCEDURE DO_QUERY_SECURITY USES GV,DO_EXIT,READ_SHARED_BUFFER;\r
+    BOOLEAN QUERY_SECURITY_RESULT[16];\r
+    PASS = 0;\r
+    SECURITY_QUERIED = 0;\r
+    IRSTOP IRPAUSE;\r
+    DRSTOP DRPAUSE;\r
+    IRSCAN 8, $b8;\r
+    DRSCAN 16, $0000;\r
+    WAIT IDLE, 3 CYCLES;\r
+    WAIT 10 USEC, DRPAUSE;\r
+    FOR IPOLL = 100000 TO 0 STEP -1;\r
+        DRSCAN 16, $0000, CAPTURE QUERY_SECURITY_RESULT[];\r
+        IF ( ! (QUERY_SECURITY_RESULT[15]==0) ) THEN GOTO QUERY_SECURITY_POLL;\r
+        IPOLL = 0;\r
+        PASS = 1;\r
+        QUERY_SECURITY_POLL:\r
+        IF ( ! (PASS==0) ) THEN GOTO QUERY_SECURITY_DONE;\r
+        IRSCAN 8, $b8;\r
+        WAIT IRPAUSE, 10 USEC;\r
+        QUERY_SECURITY_DONE:\r
+        LABEL_SEPARATOR = 0;\r
+    NEXT IPOLL;\r
+    IF ( ! (PASS==0) ) THEN GOTO QUERY_SECURITY_PASS;\r
+    PRINT "Failed to query security information.";\r
+    STATUS = 14;\r
+    CALL DO_EXIT;\r
+    QUERY_SECURITY_PASS:\r
+    INUMOFBLOCKS = 3;\r
+    CALL READ_SHARED_BUFFER;\r
+    FOR I = 0 TO 319 STEP 1;\r
+        IF ( ! (SHARED_BUFFER[I]==1) ) THEN GOTO DO_QUERY_SECURITY_SUCCESS;\r
+        SECURITY_QUERIED = 1;\r
+        I = 320;\r
+        DO_QUERY_SECURITY_SUCCESS:\r
+        LABEL_SEPARATOR = 0;\r
+    NEXT I;\r
+ENDPROC;\r
+\r
+PROCEDURE DO_READ_SECURITY USES GV,DO_QUERY_SECURITY;\r
+    INTEGER BYTEIDX =0;\r
+    CALL DO_QUERY_SECURITY;\r
+    IF ( ! (SECURITY_QUERIED==0) ) THEN GOTO Label_1;\r
+    PRINT "WARNING! Security cannot be read. This can be because of programmed debug lock. Please generate programming file with debug passkey provided.";\r
+    Label_1:\r
+    BYTEIDX = 0;\r
+    SEC_UKL[5..0] = SHARED_BUFFER[((BYTEIDX*8)+7)..((BYTEIDX*8)+2)];\r
+    BYTEIDX = 1;\r
+    SEC_UKL[11..6] = SHARED_BUFFER[((BYTEIDX*8)+7)..((BYTEIDX*8)+2)];\r
+    BYTEIDX = 2;\r
+    SEC_VL[5..0] = SHARED_BUFFER[((BYTEIDX*8)+7)..((BYTEIDX*8)+2)];\r
+    BYTEIDX = 3;\r
+    SEC_VL[11..6] = SHARED_BUFFER[((BYTEIDX*8)+7)..((BYTEIDX*8)+2)];\r
+    BYTEIDX = 4;\r
+    SEC_UL[5..0] = SHARED_BUFFER[((BYTEIDX*8)+7)..((BYTEIDX*8)+2)];\r
+    BYTEIDX = 5;\r
+    SEC_UL[11..6] = SHARED_BUFFER[((BYTEIDX*8)+7)..((BYTEIDX*8)+2)];\r
+    BYTEIDX = 6;\r
+    SEC_UL[17..12] = SHARED_BUFFER[((BYTEIDX*8)+7)..((BYTEIDX*8)+2)];\r
+    BYTEIDX = 7;\r
+    SEC_UL[23..18] = SHARED_BUFFER[((BYTEIDX*8)+7)..((BYTEIDX*8)+2)];\r
+    BYTEIDX = 8;\r
+    SEC_CL[2..0] = SHARED_BUFFER[((BYTEIDX*8)+7)..((BYTEIDX*8)+5)];\r
+    SEC_OPOK[2..0] = SHARED_BUFFER[((BYTEIDX*8)+4)..((BYTEIDX*8)+2)];\r
+    BYTEIDX = 9;\r
+    SEC_CL[5..3] = SHARED_BUFFER[((BYTEIDX*8)+7)..((BYTEIDX*8)+5)];\r
+    SEC_CCNFG[1..0] = SHARED_BUFFER[((BYTEIDX*8)+4)..((BYTEIDX*8)+3)];\r
+    SEC_OPOK[3] = SHARED_BUFFER[((BYTEIDX*8)+2)];\r
+    BYTEIDX = 10;\r
+    SEC_CL[8..6] = SHARED_BUFFER[((BYTEIDX*8)+7)..((BYTEIDX*8)+5)];\r
+    SEC_CCNFG[4..2] = SHARED_BUFFER[((BYTEIDX*8)+4)..((BYTEIDX*8)+2)];\r
+    BYTEIDX = 11;\r
+    SEC_CL[11..9] = SHARED_BUFFER[((BYTEIDX*8)+7)..((BYTEIDX*8)+5)];\r
+    SEC_CCNFG[7..5] = SHARED_BUFFER[((BYTEIDX*8)+4)..((BYTEIDX*8)+2)];\r
+    BYTEIDX = 12;\r
+    SEC_UL[26..24] = SHARED_BUFFER[((BYTEIDX*8)+7)..((BYTEIDX*8)+5)];\r
+    SEC_USERCODE[2..0] = SHARED_BUFFER[((BYTEIDX*8)+4)..((BYTEIDX*8)+2)];\r
+    BYTEIDX = 13;\r
+    SEC_UL[29..27] = SHARED_BUFFER[((BYTEIDX*8)+7)..((BYTEIDX*8)+5)];\r
+    SEC_USERCODE[5..3] = SHARED_BUFFER[((BYTEIDX*8)+4)..((BYTEIDX*8)+2)];\r
+    BYTEIDX = 14;\r
+    SEC_UL[32..30] = SHARED_BUFFER[((BYTEIDX*8)+7)..((BYTEIDX*8)+5)];\r
+    SEC_USERCODE[8..6] = SHARED_BUFFER[((BYTEIDX*8)+4)..((BYTEIDX*8)+2)];\r
+    BYTEIDX = 15;\r
+    SEC_UL[35..33] = SHARED_BUFFER[((BYTEIDX*8)+7)..((BYTEIDX*8)+5)];\r
+    SEC_USERCODE[11..9] = SHARED_BUFFER[((BYTEIDX*8)+4)..((BYTEIDX*8)+2)];\r
+    BYTEIDX = 16;\r
+    SEC_UL[38..36] = SHARED_BUFFER[((BYTEIDX*8)+7)..((BYTEIDX*8)+5)];\r
+    SEC_USERCODE[14..12] = SHARED_BUFFER[((BYTEIDX*8)+4)..((BYTEIDX*8)+2)];\r
+    BYTEIDX = 17;\r
+    SEC_UL[41..39] = SHARED_BUFFER[((BYTEIDX*8)+7)..((BYTEIDX*8)+5)];\r
+    SEC_USERCODE[17..15] = SHARED_BUFFER[((BYTEIDX*8)+4)..((BYTEIDX*8)+2)];\r
+    BYTEIDX = 18;\r
+    SEC_UL[44..42] = SHARED_BUFFER[((BYTEIDX*8)+7)..((BYTEIDX*8)+5)];\r
+    SEC_USERCODE[20..18] = SHARED_BUFFER[((BYTEIDX*8)+4)..((BYTEIDX*8)+2)];\r
+    BYTEIDX = 19;\r
+    SEC_UL[47..45] = SHARED_BUFFER[((BYTEIDX*8)+7)..((BYTEIDX*8)+5)];\r
+    SEC_USERCODE[23..21] = SHARED_BUFFER[((BYTEIDX*8)+4)..((BYTEIDX*8)+2)];\r
+    BYTEIDX = 20;\r
+    SEC_UL[50..48] = SHARED_BUFFER[((BYTEIDX*8)+7)..((BYTEIDX*8)+5)];\r
+    SEC_USERCODE[26..24] = SHARED_BUFFER[((BYTEIDX*8)+4)..((BYTEIDX*8)+2)];\r
+    BYTEIDX = 21;\r
+    SEC_UL[53..51] = SHARED_BUFFER[((BYTEIDX*8)+7)..((BYTEIDX*8)+5)];\r
+    SEC_USERCODE[29..27] = SHARED_BUFFER[((BYTEIDX*8)+4)..((BYTEIDX*8)+2)];\r
+    BYTEIDX = 22;\r
+    SEC_UL[56..54] = SHARED_BUFFER[((BYTEIDX*8)+7)..((BYTEIDX*8)+5)];\r
+    SEC_UCNFG[0] = SHARED_BUFFER[((BYTEIDX*8)+4)];\r
+    SEC_USERCODE[31..30] = SHARED_BUFFER[((BYTEIDX*8)+3)..((BYTEIDX*8)+2)];\r
+    BYTEIDX = 23;\r
+    SEC_UL[59..57] = SHARED_BUFFER[((BYTEIDX*8)+7)..((BYTEIDX*8)+5)];\r
+    SEC_UCNFG[3..1] = SHARED_BUFFER[((BYTEIDX*8)+4)..((BYTEIDX*8)+2)];\r
+    BYTEIDX = 24;\r
+    SEC_UL[62..60] = SHARED_BUFFER[((BYTEIDX*8)+7)..((BYTEIDX*8)+5)];\r
+    SEC_UCNFG[6..4] = SHARED_BUFFER[((BYTEIDX*8)+4)..((BYTEIDX*8)+2)];\r
+    BYTEIDX = 25;\r
+    SEC_UL[65..63] = SHARED_BUFFER[((BYTEIDX*8)+7)..((BYTEIDX*8)+5)];\r
+    SEC_UCNFG[9..7] = SHARED_BUFFER[((BYTEIDX*8)+4)..((BYTEIDX*8)+2)];\r
+    BYTEIDX = 26;\r
+    SEC_UL[68..66] = SHARED_BUFFER[((BYTEIDX*8)+7)..((BYTEIDX*8)+5)];\r
+    SEC_UCNFG[12..10] = SHARED_BUFFER[((BYTEIDX*8)+4)..((BYTEIDX*8)+2)];\r
+    BYTEIDX = 27;\r
+    SEC_UL[71..69] = SHARED_BUFFER[((BYTEIDX*8)+7)..((BYTEIDX*8)+5)];\r
+    SEC_UCNFG[15..13] = SHARED_BUFFER[((BYTEIDX*8)+4)..((BYTEIDX*8)+2)];\r
+    BYTEIDX = 28;\r
+    SEC_UL[74..72] = SHARED_BUFFER[((BYTEIDX*8)+7)..((BYTEIDX*8)+5)];\r
+    BYTEIDX = 29;\r
+    SEC_UL[77..75] = SHARED_BUFFER[((BYTEIDX*8)+7)..((BYTEIDX*8)+5)];\r
+    BYTEIDX = 30;\r
+    SEC_UL[80..78] = SHARED_BUFFER[((BYTEIDX*8)+7)..((BYTEIDX*8)+5)];\r
+    SEC_UCNFG[18..16] = SHARED_BUFFER[((BYTEIDX*8)+4)..((BYTEIDX*8)+2)];\r
+    BYTEIDX = 31;\r
+    SEC_UL[83..81] = SHARED_BUFFER[((BYTEIDX*8)+7)..((BYTEIDX*8)+5)];\r
+    SEC_UCNFG[21..19] = SHARED_BUFFER[((BYTEIDX*8)+4)..((BYTEIDX*8)+2)];\r
+    BYTEIDX = 32;\r
+    SEC_UL[86..84] = SHARED_BUFFER[((BYTEIDX*8)+7)..((BYTEIDX*8)+5)];\r
+    SEC_UCNFG[24..22] = SHARED_BUFFER[((BYTEIDX*8)+4)..((BYTEIDX*8)+2)];\r
+    BYTEIDX = 33;\r
+    SEC_UL[89..87] = SHARED_BUFFER[((BYTEIDX*8)+7)..((BYTEIDX*8)+5)];\r
+    SEC_UCNFG[27..25] = SHARED_BUFFER[((BYTEIDX*8)+4)..((BYTEIDX*8)+2)];\r
+    BYTEIDX = 34;\r
+    SEC_UL[92..90] = SHARED_BUFFER[((BYTEIDX*8)+7)..((BYTEIDX*8)+5)];\r
+    SEC_UCNFG[30..28] = SHARED_BUFFER[((BYTEIDX*8)+4)..((BYTEIDX*8)+2)];\r
+    BYTEIDX = 35;\r
+    SEC_UL[95..93] = SHARED_BUFFER[((BYTEIDX*8)+7)..((BYTEIDX*8)+5)];\r
+    SEC_UCNFG[33..31] = SHARED_BUFFER[((BYTEIDX*8)+4)..((BYTEIDX*8)+2)];\r
+    BYTEIDX = 36;\r
+    SEC_DL[2..0] = SHARED_BUFFER[((BYTEIDX*8)+7)..((BYTEIDX*8)+5)];\r
+    SEC_UCNFG[36..34] = SHARED_BUFFER[((BYTEIDX*8)+4)..((BYTEIDX*8)+2)];\r
+    BYTEIDX = 37;\r
+    SEC_DL[5..3] = SHARED_BUFFER[((BYTEIDX*8)+7)..((BYTEIDX*8)+5)];\r
+    SEC_UCNFG[39..37] = SHARED_BUFFER[((BYTEIDX*8)+4)..((BYTEIDX*8)+2)];\r
+    BYTEIDX = 38;\r
+    SEC_DL[8..6] = SHARED_BUFFER[((BYTEIDX*8)+7)..((BYTEIDX*8)+5)];\r
+    SEC_UCNFG[42..40] = SHARED_BUFFER[((BYTEIDX*8)+4)..((BYTEIDX*8)+2)];\r
+    BYTEIDX = 39;\r
+    SEC_DL[11..9] = SHARED_BUFFER[((BYTEIDX*8)+7)..((BYTEIDX*8)+5)];\r
+    SEC_UCNFG[45..43] = SHARED_BUFFER[((BYTEIDX*8)+4)..((BYTEIDX*8)+2)];\r
+ENDPROC;\r
+\r
+PROCEDURE PROC_ENABLE USES GV,DO_EXIT,SET_PGM_MODE,POLL_DEVICE_READY,DO_READ_SECURITY;\r
+    CALL POLL_DEVICE_READY;\r
+    CALL SET_PGM_MODE;\r
+    CALL DO_READ_SECURITY;\r
+    BOOLEAN ISC_ENABLE_RESULT[32];\r
+    BPGMMODE = 1;\r
+    PASS = 0;\r
+    BSR[1145..0] = BSRPATTERN[1145..0];\r
+    BOOLEAN SHIFT_DATA[1146];\r
+    IRSCAN 8, $01;\r
+    DRSCAN 1146, BSR[];\r
+    WAIT IDLE, 1 CYCLES;\r
+    DRSCAN 1146, SHIFT_DATA[], CAPTURE SAMPLE_DEVICE[];\r
+    FOR I = 0 TO 1145;\r
+        IF ( ! (SAMPLEMASK[I]==1) ) THEN GOTO Label_2;\r
+        BSR[I] = SAMPLE_DEVICE[I];\r
+        Label_2:\r
+        LABEL_SEPARATOR = 0;\r
+    NEXT I;\r
+    IRSTOP IRPAUSE;\r
+    DRSTOP DRPAUSE;\r
+    IRSCAN 8, $01;\r
+    DRSCAN 1146, BSR[];\r
+    WAIT IDLE, 1 CYCLES;\r
+    BOOLEAN TOOLINFO[32] = $00000000;\r
+    TOOLINFO[5..0] = ACT_UROW_ALGO_VERSION[5..0];\r
+    TOOLINFO[9..6] = ACT_UROW_PROGRAM_SW[3..0];\r
+    TOOLINFO[22..17] = ACT_UROW_SW_VERSION[5..0];\r
+    TOOLINFO[25..23] = BOOL(1);\r
+    TOOLINFO[28..26] = BOOL(3);\r
+    TOOLINFO[31..29] = BOOL(2);\r
+    IRSTOP IRPAUSE;\r
+    DRSTOP DRPAUSE;\r
+    IRSCAN 8, $80;\r
+    DRSCAN 32, TOOLINFO[];\r
+    WAIT IDLE, 3 CYCLES;\r
+    WAIT 10 USEC, DRPAUSE;\r
+    FOR IPOLL = 1000000 TO 0 STEP -1;\r
+        DRSCAN 32, $00000000, CAPTURE ISC_ENABLE_RESULT[31..0];\r
+        IF ( ! (ISC_ENABLE_RESULT[31]==0) ) THEN GOTO ISC_ENABLE_POLL;\r
+        IPOLL = 0;\r
+        PASS = 1;\r
+        ISC_ENABLE_POLL:\r
+        IF ( ! (PASS==0) ) THEN GOTO ISC_ENABLE_DONE;\r
+        IRSCAN 8, $80;\r
+        WAIT IRPAUSE, 10 USEC;\r
+        ISC_ENABLE_DONE:\r
+        LABEL_SEPARATOR = 0;\r
+    NEXT IPOLL;\r
+    EXPORT "ISC_ENABLE_RESULT", ISC_ENABLE_RESULT[];\r
+    EXPORT "CRCERR: ", ISC_ENABLE_RESULT[0];\r
+    EXPORT "EDCERR: ", ISC_ENABLE_RESULT[1];\r
+    IF ( ! (INT(ISC_ENABLE_RESULT[4..2])==0) ) THEN GOTO NOT_COLD;\r
+    PRINT "TEMPRANGE: COLD";\r
+    NOT_COLD:\r
+    IF ( ! (INT(ISC_ENABLE_RESULT[4..2])==1) ) THEN GOTO NOT_ROOM;\r
+    PRINT "TEMPGRADE: ROOM";\r
+    NOT_ROOM:\r
+    IF ( ! (INT(ISC_ENABLE_RESULT[4..2])==2) ) THEN GOTO NOT_HOT;\r
+    PRINT "TEMPGRADE: HOT";\r
+    NOT_HOT:\r
+    EXPORT "VPPRANGE: ", ISC_ENABLE_RESULT[7..5];\r
+    IF ( ! (INT(ISC_ENABLE_RESULT[7..5])==0) ) THEN GOTO NOT_LOW;\r
+    PRINT "VPPRANGE: LOW";\r
+    NOT_LOW:\r
+    IF ( ! (INT(ISC_ENABLE_RESULT[7..5])==1) ) THEN GOTO NOT_NOMINAL;\r
+    PRINT "VPPRANGE: NOMINAL";\r
+    NOT_NOMINAL:\r
+    IF ( ! (INT(ISC_ENABLE_RESULT[7..5])==2) ) THEN GOTO NOT_HIGH;\r
+    PRINT "VPPRANGE: HIGH";\r
+    NOT_HIGH:\r
+    EXPORT "TEMP: ", ISC_ENABLE_RESULT[15..8];\r
+    EXPORT "VPP: ", ISC_ENABLE_RESULT[23..16];\r
+    IF ( ! ( (PASS==0)||( (PASS==1)&&(ISC_ENABLE_RESULT[0]==1))) ) THEN GOTO ISC_ENABLE_PASS;\r
+    PRINT "Failed to enter programming mode.";\r
+    STATUS = 5;\r
+    CALL DO_EXIT;\r
+    ISC_ENABLE_PASS:\r
+    LABEL_SEPARATOR = 0;\r
+ENDPROC;\r
+\r
+PROCEDURE PRINT_IDCODE USES GV;\r
+    EXPORT "IDCODE", ID[];\r
+ENDPROC;\r
+\r
+PROCEDURE VERIFY_IDCODE USES GV,PARAMETERS,DO_EXIT;\r
+    FREQUENCY (FREQ*1000000);\r
+    WAIT RESET, 5 CYCLES;\r
+    IRSTOP IRPAUSE;\r
+    DRSTOP DRPAUSE;\r
+    IRSCAN 8, $0f;\r
+    DRSCAN 32, $00000000;\r
+    WAIT IDLE, 1 CYCLES;\r
+    DRSCAN 32, $00000000, CAPTURE ID[],COMPARE IDCODEVALUE[],IDMASK[],PASS;\r
+    IF ( ! (PASS==0) ) THEN GOTO IDOK;\r
+    STATUS = 6;\r
+    PRINT "Failed to verify IDCODE";\r
+    CALL DO_EXIT;\r
+    IDOK:\r
+    IF ( ! (PASS==1) ) THEN GOTO IDNOTOK;\r
+    IDNOTOK:\r
+    IDREV = INT(ID[31..28]);\r
+ENDPROC;\r
+\r
+PROCEDURE GET_DATA_STATUS USES GV;\r
+    INTEGER IPOLLDATA =0;\r
+    PASS = 0;\r
+    IRSTOP IRPAUSE;\r
+    DRSTOP DRPAUSE;\r
+    IRSCAN 8, $c9;\r
+    DRSCAN 32, $00000000;\r
+    WAIT IDLE, 3 CYCLES;\r
+    WAIT 10 USEC, DRPAUSE;\r
+    FOR IPOLLDATA = 100000 TO 0 STEP -1;\r
+        DRSCAN 32, $00000000, CAPTURE DATA_STATUS_RESULT[31..0];\r
+        IF ( ! (DATA_STATUS_RESULT[31]==0) ) THEN GOTO DATA_STATUS_POLL;\r
+        IPOLLDATA = 0;\r
+        PASS = 1;\r
+        DATA_STATUS_POLL:\r
+        IF ( ! (PASS==0) ) THEN GOTO DATA_STATUS_READ;\r
+        IRSCAN 8, $c9;\r
+        WAIT IRPAUSE, 10 USEC;\r
+        DATA_STATUS_READ:\r
+        LABEL_SEPARATOR = 0;\r
+    NEXT IPOLLDATA;\r
+ENDPROC;\r
+\r
+PROCEDURE PROCESS_DATA USES BITSTREAM,GV,DO_EXIT,GET_DATA_STATUS;\r
+    BOOLEAN DATA_SHIFT_RESULT[128];\r
+    INTEGER BLOCKNO =0;\r
+    INTEGER CURRNUMOFBLOCKS =0;\r
+    INTEGER COMPONENTNO =0;\r
+    FOR COMPONENTNO = ICURCOMPONENTNO TO ICURNUMOFCOMPONENTS STEP 1;\r
+        CURRNUMOFBLOCKS = INT(NUMOFBLOCKS[((COMPONENTNO*22)-1)..((COMPONENTNO-1)*22)]);\r
+        FOR BLOCKNO = 1 TO CURRNUMOFBLOCKS STEP 1;\r
+            PASS = 0;\r
+            IRSTOP IRPAUSE;\r
+            DRSTOP DRPAUSE;\r
+            IRSCAN 8, $ee;\r
+            DRSCAN 128, DATASTREAM[(DATAINDEX+127)..DATAINDEX];\r
+            WAIT IDLE, 3 CYCLES;\r
+            WAIT 16 USEC, DRPAUSE;\r
+            FOR IPOLL = 10000000 TO 0 STEP -1;\r
+                DRSCAN 128, $00000000000000000000000000000000, CAPTURE DATA_SHIFT_RESULT[127..0];\r
+                IF ( ! (DATA_SHIFT_RESULT[127]==0) ) THEN GOTO DATA_POLL;\r
+                IPOLL = 0;\r
+                PASS = 1;\r
+                DATA_POLL:\r
+                IF ( ! (PASS==0) ) THEN GOTO DATA_DONE;\r
+                IRSCAN 8, $ee;\r
+                WAIT IRPAUSE, 10 USEC;\r
+                DATA_DONE:\r
+                LABEL_SEPARATOR = 0;\r
+            NEXT IPOLL;\r
+            IF ( ! ( (PASS==0)||( (PASS==1)&&( (DATA_SHIFT_RESULT[3]==1)||(DATA_SHIFT_RESULT[4]==1)))) ) THEN GOTO DATA_PASS;\r
+            CALL GET_DATA_STATUS;\r
+            IF ( ! ( (PASS==0)||( (PASS==1)&&(DATA_STATUS_RESULT[2]==1))) ) THEN GOTO NO_ERROR_PER_BLOCK;\r
+            IF ( ! (INT(DATA_STATUS_RESULT[15..8])!=0) ) THEN GOTO NOT_AUTHERR;\r
+            PRINT "Authentication Error.";\r
+            IF ( ! ( ( ( ( ( ( (INT(DATA_STATUS_RESULT[15..8])==1)||(INT(DATA_STATUS_RESULT[15..8])==2))||(INT(DATA_STATUS_RESULT[15..8])==3))||(INT(DATA_STATUS_RESULT[15..8])==4))||(INT(DATA_STATUS_RESULT[15..8])==7))||(INT(DATA_STATUS_RESULT[15..8])==8))||(INT(DATA_STATUS_RESULT[15..8])==9)) ) THEN GOTO NOT_INVALID_BITSTREAM;\r
+            PRINT "Invalid/Corrupted programming file.";\r
+            NOT_INVALID_BITSTREAM:\r
+            IF ( ! (INT(DATA_STATUS_RESULT[15..8])==5) ) THEN GOTO BACKLEVEL_SATISFIED;\r
+            PRINT "Back level not satisfied.";\r
+            BACKLEVEL_SATISFIED:\r
+            IF ( ! (INT(DATA_STATUS_RESULT[15..8])==10) ) THEN GOTO CORRECT_IDCODE;\r
+            PRINT "Incorrect DEVICEID.";\r
+            CORRECT_IDCODE:\r
+            IF ( ! (INT(DATA_STATUS_RESULT[15..8])==11) ) THEN GOTO BITSTREAM_FINE;\r
+            PRINT "Programming file is out dated, please regenerate.";\r
+            BITSTREAM_FINE:\r
+            IF ( ! (INT(DATA_STATUS_RESULT[15..8])==12) ) THEN GOTO BITSTREAM_VER;\r
+            PRINT "Programming file does not support verification.";\r
+            BITSTREAM_VER:\r
+            LABEL_SEPARATOR = 0;\r
+            NOT_AUTHERR:\r
+            IF ( ! (INT(DATA_STATUS_RESULT[7..3])!=0) ) THEN GOTO NOT_ERRORCODE;\r
+            IF ( ! (INT(DATA_STATUS_RESULT[7..3])==5) ) THEN GOTO NOT_NVMVERIFY;\r
+            PRINT "Failed to verify eNVM.";\r
+            NOT_NVMVERIFY:\r
+            IF ( ! (INT(DATA_STATUS_RESULT[7..3])==4) ) THEN GOTO NOT_NVMPRG;\r
+            PRINT "Failed to program eNVM.";\r
+            NOT_NVMPRG:\r
+            IF ( ! (INT(DATA_STATUS_RESULT[7..3])==3) ) THEN GOTO PROTOCOL_ENABLED;\r
+            PRINT "Programming protocol is disabled.";\r
+            PROTOCOL_ENABLED:\r
+            IF ( ! (INT(DATA_STATUS_RESULT[7..3])==2) ) THEN GOTO DEVICE_NO_SEC;\r
+            PRINT "Device security prevented operation.";\r
+            DEVICE_NO_SEC:\r
+            IF ( ! (INT(DATA_STATUS_RESULT[7..3])==1) ) THEN GOTO FABRIC_VER_FINE;\r
+            PRINT "Failed to verify FPGA Array.";\r
+            FABRIC_VER_FINE:\r
+            LABEL_SEPARATOR = 0;\r
+            NOT_ERRORCODE:\r
+            PRINT "componentNo: ",COMPONENTNO;\r
+            PRINT "blockNo: ",BLOCKNO;\r
+            EXPORT "DATA_STATUS_RESULT: ", DATA_STATUS_RESULT[31..0];\r
+            EXPORT "ERRORCODE: ", DATA_STATUS_RESULT[7..3];\r
+            EXPORT "AUTHERRCODE: ", DATA_STATUS_RESULT[15..8];\r
+            STATUS = 10;\r
+            CALL DO_EXIT;\r
+            NO_ERROR_PER_BLOCK:\r
+            LABEL_SEPARATOR = 0;\r
+            DATA_PASS:\r
+            DATAINDEX = (DATAINDEX+128);\r
+        NEXT BLOCKNO;\r
+    NEXT COMPONENTNO;\r
+ENDPROC;\r
+\r
+PROCEDURE SET_MODE USES GV,DO_EXIT;\r
+    BOOLEAN DATA_INIT_RESULT[8];\r
+    PASS = 0;\r
+    IRSTOP IRPAUSE;\r
+    DRSTOP DRPAUSE;\r
+    IRSCAN 8, $ae;\r
+    DRSCAN 8, PGMMODE[];\r
+    WAIT IDLE, 3 CYCLES;\r
+    WAIT 10 USEC, DRPAUSE;\r
+    FOR IPOLL = 100000 TO 0 STEP -1;\r
+        DRSCAN 8, $00, CAPTURE DATA_INIT_RESULT[7..0];\r
+        IF ( ! (DATA_INIT_RESULT[7]==0) ) THEN GOTO DATA_INIT_POLL;\r
+        IPOLL = 0;\r
+        PASS = 1;\r
+        DATA_INIT_POLL:\r
+        IF ( ! (PASS==0) ) THEN GOTO DATA_INIT_DONE;\r
+        IRSCAN 8, $ae;\r
+        WAIT IRPAUSE, 10 USEC;\r
+        DATA_INIT_DONE:\r
+        LABEL_SEPARATOR = 0;\r
+    NEXT IPOLL;\r
+    IF ( ! (PASS==0) ) THEN GOTO DATA_INIT_PASSED;\r
+    PRINT "Failed to set programming mode";\r
+    STATUS = 5;\r
+    CALL DO_EXIT;\r
+    DATA_INIT_PASSED:\r
+    LABEL_SEPARATOR = 0;\r
+ENDPROC;\r
+\r
+PROCEDURE DO_PROGRAM_ENVM USES GV,PROCESS_DATA,SET_MODE;\r
+    PRINT "Programming eNVM...";\r
+    PGMMODE[7..0] = $01;\r
+    CALL SET_MODE;\r
+    ICURCOMPONENTNO = (DATASIZE+1);\r
+    ICURNUMOFCOMPONENTS = (DATASIZE+DATAENVMSIZE);\r
+    DATAINDEX = DATAENVMSTARTINDEX;\r
+    CALL PROCESS_DATA;\r
+ENDPROC;\r
+\r
+PROCEDURE DO_VERIFY_ENVM USES GV,PROCESS_DATA,SET_MODE;\r
+    PRINT "Verifying eNVM...";\r
+    PGMMODE[7..0] = $02;\r
+    CALL SET_MODE;\r
+    ICURCOMPONENTNO = (DATASIZE+1);\r
+    ICURNUMOFCOMPONENTS = (DATASIZE+DATAENVMSIZE);\r
+    DATAINDEX = DATAENVMSTARTINDEX;\r
+    CALL PROCESS_DATA;\r
+ENDPROC;\r
+\r
+PROCEDURE DO_AUTHENTICATION_ENVM USES GV,PROCESS_DATA,SET_MODE;\r
+    PRINT "Encrypted data authentication...";\r
+    PGMMODE[7..0] = $00;\r
+    CALL SET_MODE;\r
+    ICURCOMPONENTNO = (DATASIZE+1);\r
+    ICURNUMOFCOMPONENTS = (DATASIZE+DATAENVMSIZE);\r
+    DATAINDEX = DATAENVMSTARTINDEX;\r
+    CALL PROCESS_DATA;\r
+ENDPROC;\r
+\r
+PROCEDURE DO_VERIFY USES GV,PROCESS_DATA,SET_MODE;\r
+    PRINT "Verifying FPGA Array...";\r
+    PGMMODE[7..0] = $02;\r
+    CALL SET_MODE;\r
+    ICURCOMPONENTNO = 1;\r
+    ICURNUMOFCOMPONENTS = DATASIZE;\r
+    DATAINDEX = DATASTARTINDEX;\r
+    CALL PROCESS_DATA;\r
+ENDPROC;\r
+\r
+PROCEDURE DO_PROGRAM USES GV,PROCESS_DATA,SET_MODE;\r
+    PRINT "Programming FPGA Array...";\r
+    PGMMODE[7..0] = $01;\r
+    CALL SET_MODE;\r
+    ICURCOMPONENTNO = 1;\r
+    ICURNUMOFCOMPONENTS = DATASIZE;\r
+    DATAINDEX = DATASTARTINDEX;\r
+    CALL PROCESS_DATA;\r
+ENDPROC;\r
+\r
+PROCEDURE DO_AUTHENTICATION USES GV,PROCESS_DATA,SET_MODE;\r
+    PRINT "Encrypted data authentication...";\r
+    PGMMODE[7..0] = $00;\r
+    CALL SET_MODE;\r
+    ICURCOMPONENTNO = 1;\r
+    ICURNUMOFCOMPONENTS = DATASIZE;\r
+    DATAINDEX = DATASTARTINDEX;\r
+    CALL PROCESS_DATA;\r
+ENDPROC;\r
+\r
+PROCEDURE DUMP_PROG_INFO USES GV,CONSTBLOCK;\r
+    INTEGER TMPINT =0;\r
+    BUFF32[31..0] = READ_PROG_INFO_RESULT[95..64];\r
+    EXPORT "PROG_INFO", READ_PROG_INFO_RESULT[127..0];\r
+    TMPINT = INT(READ_PROG_INFO_RESULT[48..48]);\r
+    IF ( ! (TMPINT==0) ) THEN GOTO NOT_12;\r
+    PRINT "VCC was programmed at 1.2V";\r
+    NOT_12:\r
+    IF ( ! (TMPINT==1) ) THEN GOTO NOT_10;\r
+    PRINT "VCC was programmed at 1.0V";\r
+    NOT_10:\r
+    TMPINT = INT(BUFF32[5..0]);\r
+    IF ( ! ( (TMPINT==0)||(TMPINT==63)) ) THEN GOTO NOT_UNDEF;\r
+    PRINT "Algorithm Version:";\r
+    NOT_UNDEF:\r
+    IF ( ! ( (TMPINT!=0)&&(TMPINT!=63)) ) THEN GOTO UNDEF;\r
+    PRINT "Algorithm Version: ",INT(BUFF32[5..0]);\r
+    UNDEF:\r
+    TMPINT = INT(BUFF32[9..6]);\r
+    IF ( ! (TMPINT==SELF) ) THEN GOTO NOT_SELF;\r
+    PRINT "Programmer: SPI Master Auto Programming";\r
+    NOT_SELF:\r
+    IF ( ! (TMPINT==SCULPTW) ) THEN GOTO NOT_SCULPTW;\r
+    PRINT "Programmer: Silicon Sculptor II/III";\r
+    NOT_SCULPTW:\r
+    IF ( ! (TMPINT==BPWIN) ) THEN GOTO NOT_BPW;\r
+    PRINT "Programmer: BP Programmer";\r
+    NOT_BPW:\r
+    IF ( ! (TMPINT==ACTEL_IHP) ) THEN GOTO NOT_ACTEL_IHP;\r
+    PRINT "Programmer: Actel IHP";\r
+    NOT_ACTEL_IHP:\r
+    IF ( ! (TMPINT==FP3) ) THEN GOTO NOT_FP3;\r
+    PRINT "Programmer: FlashPro3";\r
+    NOT_FP3:\r
+    IF ( ! (TMPINT==FP4) ) THEN GOTO NOT_FP4;\r
+    PRINT "Programmer: FlashPro4";\r
+    NOT_FP4:\r
+    IF ( ! (TMPINT==FP_FTDI) ) THEN GOTO NOT_FTDI;\r
+    PRINT "Programmer: FP-FTDI";\r
+    NOT_FTDI:\r
+    IF ( ! (TMPINT==SIL_EXPL) ) THEN GOTO NOT_SIL_EXPL;\r
+    PRINT "Programmer: Silicon Explorer";\r
+    NOT_SIL_EXPL:\r
+    IF ( ! (TMPINT==ATE) ) THEN GOTO NOT_ATE;\r
+    PRINT "Programmer: Non Actel Programmer";\r
+    NOT_ATE:\r
+    IF ( ! ( (TMPINT==0)||(TMPINT==15)) ) THEN GOTO UNDEF_P_T;\r
+    PRINT "Programmer:";\r
+    UNDEF_P_T:\r
+    TMPINT = INT(BUFF32[22..17]);\r
+    IF ( ! (TMPINT==FP34) ) THEN GOTO NOT_FP34;\r
+    PRINT "Software Version: FlashPro v3.4";\r
+    NOT_FP34:\r
+    IF ( ! (TMPINT==FP40) ) THEN GOTO NOT_FP40;\r
+    PRINT "Software Version: FlashPro v4.0";\r
+    NOT_FP40:\r
+    IF ( ! (TMPINT==FP41) ) THEN GOTO NOT_FP41;\r
+    PRINT "Software Version: FlashPro v4.1";\r
+    NOT_FP41:\r
+    IF ( ! (TMPINT==FP42) ) THEN GOTO NOT_FP42;\r
+    PRINT "Software Version: FlashPro v4.2";\r
+    NOT_FP42:\r
+    IF ( ! (TMPINT==FP50) ) THEN GOTO NOT_FP50;\r
+    PRINT "Software Version: FlashPro v5.0";\r
+    NOT_FP50:\r
+    IF ( ! (TMPINT==FP51) ) THEN GOTO NOT_FP51;\r
+    PRINT "Software Version: FlashPro v5.1";\r
+    NOT_FP51:\r
+    IF ( ! (TMPINT==FP60) ) THEN GOTO NOT_FP60;\r
+    PRINT "Software Version: FlashPro v6.0";\r
+    NOT_FP60:\r
+    IF ( ! (TMPINT==FP61) ) THEN GOTO NOT_FP61;\r
+    PRINT "Software Version: FlashPro v6.1";\r
+    NOT_FP61:\r
+    IF ( ! (TMPINT==FP62) ) THEN GOTO NOT_FP62;\r
+    PRINT "Software Version: FlashPro v6.2";\r
+    NOT_FP62:\r
+    IF ( ! (TMPINT==FP84) ) THEN GOTO NOT_FP84;\r
+    PRINT "Software Version: FlashPro v8.4";\r
+    NOT_FP84:\r
+    IF ( ! (TMPINT==FP85) ) THEN GOTO NOT_FP85;\r
+    PRINT "Software Version: FlashPro v8.5";\r
+    NOT_FP85:\r
+    IF ( ! (TMPINT==FP86) ) THEN GOTO NOT_FP86;\r
+    PRINT "Software Version: FlashPro v8.6";\r
+    NOT_FP86:\r
+    IF ( ! (TMPINT==FP90) ) THEN GOTO NOT_FP90;\r
+    PRINT "Software Version: FlashPro v9.0";\r
+    NOT_FP90:\r
+    IF ( ! (TMPINT==FP91) ) THEN GOTO NOT_FP91;\r
+    PRINT "Software Version: FlashPro v9.1";\r
+    NOT_FP91:\r
+    IF ( ! (TMPINT==FP_10_LCP) ) THEN GOTO NOT_10_LCP;\r
+    PRINT "Software Version: FlashPro 10.0 LCP";\r
+    NOT_10_LCP:\r
+    IF ( ! (TMPINT==FP_11_BETA_SPA) ) THEN GOTO NOT_11_BETA_SPA;\r
+    PRINT "Software Version: FlashPro 11.0 Beta SPA";\r
+    NOT_11_BETA_SPA:\r
+    IF ( ! (TMPINT==FP_11_BETA_SP1) ) THEN GOTO NOT_11_BETA_SP1;\r
+    PRINT "Software Version: FlashPro 11.0 Beta SP1";\r
+    NOT_11_BETA_SP1:\r
+    IF ( ! (TMPINT==FP_11) ) THEN GOTO NOT_11;\r
+    PRINT "Software Version: FlashPro 11.0";\r
+    NOT_11:\r
+    IF ( ! ( (TMPINT==0)||(TMPINT==63)) ) THEN GOTO NOT_UNDEF_SOFT_VER;\r
+    PRINT "Software Version:";\r
+    NOT_UNDEF_SOFT_VER:\r
+    TMPINT = INT(BUFF32[25..23]);\r
+    IF ( ! (TMPINT==FP) ) THEN GOTO NOT_FP;\r
+    PRINT "Programming Software: FlashPro";\r
+    NOT_FP:\r
+    IF ( ! (TMPINT==DIRECTC) ) THEN GOTO NOT_DC;\r
+    PRINT "Programming Software: Direct C";\r
+    NOT_DC:\r
+    IF ( ! (TMPINT==NON_ACTEL) ) THEN GOTO NOT_NON_ACTEL;\r
+    PRINT "Programming Software: Non Actel SW";\r
+    NOT_NON_ACTEL:\r
+    IF ( ! ( (TMPINT==0)||(TMPINT==7)) ) THEN GOTO UNDEF_P_S;\r
+    PRINT "Programming Software:";\r
+    UNDEF_P_S:\r
+    TMPINT = INT(BUFF32[28..26]);\r
+    IF ( ! (TMPINT==SPI_MASTER) ) THEN GOTO NOT_SPI_MASTER;\r
+    PRINT "Programming Interface Protocol: SPI Master";\r
+    NOT_SPI_MASTER:\r
+    IF ( ! (TMPINT==SPI_SLAVE) ) THEN GOTO NOT_SPI_SLAVE;\r
+    PRINT "Programming Interface Protocol: SPI Slave";\r
+    NOT_SPI_SLAVE:\r
+    IF ( ! (TMPINT==JTAG) ) THEN GOTO NOT_JTAG;\r
+    PRINT "Programming Interface Protocol: JTAG";\r
+    NOT_JTAG:\r
+    IF ( ! (TMPINT==I2C_MASTER) ) THEN GOTO NOT_I2C_MASTER;\r
+    PRINT "Programming Interface Protocol: I2C Master";\r
+    NOT_I2C_MASTER:\r
+    IF ( ! (TMPINT==I2C_SLAVE) ) THEN GOTO NOT_I2C_SLAVE;\r
+    PRINT "Programming Interface Protocol: I2C Slave";\r
+    NOT_I2C_SLAVE:\r
+    IF ( ! ( (TMPINT==0)||(TMPINT==7)) ) THEN GOTO UNDEF_P_I_P;\r
+    PRINT "Programming Interface Protocol:";\r
+    UNDEF_P_I_P:\r
+    TMPINT = INT(BUFF32[31..29]);\r
+    IF ( ! (TMPINT==PDB) ) THEN GOTO NOT_PDB;\r
+    PRINT "Programming File Type: PDB";\r
+    NOT_PDB:\r
+    IF ( ! (TMPINT==STAPL) ) THEN GOTO NOT_STAPL;\r
+    PRINT "Programming File Type: STAPL";\r
+    NOT_STAPL:\r
+    IF ( ! (TMPINT==SVF) ) THEN GOTO NOT_SVF;\r
+    PRINT "Programming File Type: SVF";\r
+    NOT_SVF:\r
+    IF ( ! (TMPINT==PCF) ) THEN GOTO NOT_PCF;\r
+    PRINT "Programming File Type: PCF";\r
+    NOT_PCF:\r
+    IF ( ! (TMPINT==IEEE1532) ) THEN GOTO NOT_IEEE1532;\r
+    PRINT "Programming File Type: IEEE 1532";\r
+    NOT_IEEE1532:\r
+    IF ( ! ( (TMPINT==0)||(TMPINT==7)) ) THEN GOTO UNDEF_P_F_T;\r
+    PRINT "Programming File Type:";\r
+    UNDEF_P_F_T:\r
+    LABEL_SEPARATOR = 0;\r
+ENDPROC;\r
+\r
+PROCEDURE FIX_INT_ARRAYS USES GV;\r
+    INTEGER TEMP =0;\r
+    IF ( ! (HEX[0]!=48) ) THEN GOTO Label_3;\r
+    FOR I = 0 TO 7;\r
+        TEMP = HEX[I];\r
+        HEX[I] = HEX[(15-I)];\r
+        HEX[(15-I)] = TEMP;\r
+    NEXT I;\r
+    Label_3:\r
+    LABEL_SEPARATOR = 0;\r
+ENDPROC;\r
+\r
+PROCEDURE DO_READ_DESIGN_INFO USES GV,DO_EXIT,READ_SHARED_BUFFER;\r
+    BOOLEAN READ_DESIGN_INFO_RESULT[8];\r
+    PASS = 0;\r
+    IRSTOP IRPAUSE;\r
+    DRSTOP DRPAUSE;\r
+    IRSCAN 8, $a6;\r
+    DRSCAN 8, $00;\r
+    WAIT IDLE, 3 CYCLES;\r
+    WAIT 10 USEC, DRPAUSE;\r
+    FOR IPOLL = 100000 TO 0 STEP -1;\r
+        DRSCAN 8, $00, CAPTURE READ_DESIGN_INFO_RESULT[];\r
+        IF ( ! (READ_DESIGN_INFO_RESULT[7]==0) ) THEN GOTO READ_DESIGN_INFO_POLL;\r
+        IPOLL = 0;\r
+        PASS = 1;\r
+        READ_DESIGN_INFO_POLL:\r
+        IF ( ! (PASS==0) ) THEN GOTO READ_DESIGN_INFO_DONE;\r
+        IRSCAN 8, $a6;\r
+        WAIT IRPAUSE, 10 USEC;\r
+        READ_DESIGN_INFO_DONE:\r
+        LABEL_SEPARATOR = 0;\r
+    NEXT IPOLL;\r
+    IF ( ! (PASS==0) ) THEN GOTO READ_DESIGN_INFO_PASS;\r
+    PRINT "Failed to read design information.";\r
+    STATUS = 5;\r
+    CALL DO_EXIT;\r
+    READ_DESIGN_INFO_PASS:\r
+    INUMOFBLOCKS = 3;\r
+    CALL READ_SHARED_BUFFER;\r
+    PRINT "Design Name: ",CHR$(INT(SHARED_BUFFER[23..16])),CHR$(INT(SHARED_BUFFER[31..24]))\r
+        ,CHR$(INT(SHARED_BUFFER[39..32])),CHR$(INT(SHARED_BUFFER[47..40])),CHR$(INT(SHARED_BUFFER[55..48]))\r
+        ,CHR$(INT(SHARED_BUFFER[63..56])),CHR$(INT(SHARED_BUFFER[71..64])),CHR$(INT(SHARED_BUFFER[79..72]))\r
+        ,CHR$(INT(SHARED_BUFFER[87..80])),CHR$(INT(SHARED_BUFFER[95..88])),CHR$(INT(SHARED_BUFFER[103..96]))\r
+        ,CHR$(INT(SHARED_BUFFER[111..104])),CHR$(INT(SHARED_BUFFER[119..112])),CHR$(INT(SHARED_BUFFER[127..120]))\r
+        ,CHR$(INT(SHARED_BUFFER[135..128])),CHR$(INT(SHARED_BUFFER[143..136])),CHR$(INT(SHARED_BUFFER[151..144]))\r
+        ,CHR$(INT(SHARED_BUFFER[159..152])),CHR$(INT(SHARED_BUFFER[167..160])),CHR$(INT(SHARED_BUFFER[175..168]))\r
+        ,CHR$(INT(SHARED_BUFFER[183..176])),CHR$(INT(SHARED_BUFFER[191..184])),CHR$(INT(SHARED_BUFFER[199..192]))\r
+        ,CHR$(INT(SHARED_BUFFER[207..200])),CHR$(INT(SHARED_BUFFER[215..208])),CHR$(INT(SHARED_BUFFER[223..216]))\r
+        ,CHR$(INT(SHARED_BUFFER[231..224])),CHR$(INT(SHARED_BUFFER[239..232])),CHR$(INT(SHARED_BUFFER[247..240]))\r
+        ,CHR$(INT(SHARED_BUFFER[255..248]));\r
+    EXPORT "CHECKSUM: ", SHARED_BUFFER[15..0];\r
+    EXPORT "READ_DESIGN_INFO: ", SHARED_BUFFER[271..0];\r
+    EXPORT "DESIGNVER: ", SHARED_BUFFER[271..256];\r
+    EXPORT "BACKLEVEL: ", SHARED_BUFFER[287..272];\r
+ENDPROC;\r
+\r
+PROCEDURE DO_READ_PROG_INFO USES GV,DO_EXIT;\r
+    PASS = 0;\r
+    IRSTOP IRPAUSE;\r
+    DRSTOP DRPAUSE;\r
+    IRSCAN 8, $e7;\r
+    DRSCAN 128, $00000000000000000000000000000000;\r
+    WAIT IDLE, 3 CYCLES;\r
+    WAIT 10 USEC, DRPAUSE;\r
+    FOR IPOLL = 100000 TO 0 STEP -1;\r
+        DRSCAN 128, $00000000000000000000000000000000, CAPTURE READ_PROG_INFO_RESULT[];\r
+        IF ( ! (READ_PROG_INFO_RESULT[127]==0) ) THEN GOTO READ_PROG_INFO_POLL;\r
+        IPOLL = 0;\r
+        PASS = 1;\r
+        READ_PROG_INFO_POLL:\r
+        IF ( ! (PASS==0) ) THEN GOTO READ_PROG_INFO_DONE;\r
+        IRSCAN 8, $e7;\r
+        WAIT IRPAUSE, 10 USEC;\r
+        READ_PROG_INFO_DONE:\r
+        LABEL_SEPARATOR = 0;\r
+    NEXT IPOLL;\r
+    IF ( ! (PASS==0) ) THEN GOTO READ_PROG_INFO_PASS;\r
+    PRINT "Failed to read programming information.";\r
+    STATUS = 5;\r
+    CALL DO_EXIT;\r
+    READ_PROG_INFO_PASS:\r
+    LABEL_SEPARATOR = 0;\r
+ENDPROC;\r
+\r
+PROCEDURE DO_DEVICE_INFO USES GV,READ_FSN,DO_EXIT,DUMP_SECURITY_INFO,DO_READ_SECURITY\r
+    ,PRINT_IDCODE,DUMP_PROG_INFO,DO_READ_DESIGN_INFO,DO_READ_PROG_INFO;\r
+    CALL PRINT_IDCODE;\r
+    IRSCAN 8, $8f, CAPTURE BUFF32[7..0];\r
+    IF ( ! (BUFF32[2]==1) ) THEN GOTO CORE_NOT_ENABLED;\r
+    PRINT "FPGA Array is programmed and enabled.";\r
+    CORE_NOT_ENABLED:\r
+    IF ( ! (BUFF32[2]==0) ) THEN GOTO CORE_ENABLED;\r
+    PRINT "FPGA Array is not enabled.";\r
+    CORE_ENABLED:\r
+    CALL DO_READ_DESIGN_INFO;\r
+    CALL DO_READ_PROG_INFO;\r
+    CALL DUMP_PROG_INFO;\r
+    CALL READ_FSN;\r
+    IF ( ! (READ_FSN_RESULT[128]==1) ) THEN GOTO FSN_NOT_BUSY;\r
+    CALL DO_EXIT;\r
+    FSN_NOT_BUSY:\r
+    CALL DO_READ_SECURITY;\r
+    CALL DUMP_SECURITY_INFO;\r
+ENDPROC;\r
+\r
+\r
+CRC 71E8;\r
diff --git a/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/LiberoOutput/DEV_KIT_DEMO_top_DataSheet.xml b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/LiberoOutput/DEV_KIT_DEMO_top_DataSheet.xml
new file mode 100644 (file)
index 0000000..fafb6c2
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/LiberoOutput/DEV_KIT_DEMO_top_DataSheet.xml
@@ -0,0 +1,3559 @@
+<?xml version="1.0" encoding="ISO-8859-1" ?>\r
+<?xml-stylesheet type="text/xsl" href="datasheet.xsl"?>\r
+<datasheet>\r
+  <header>DEV_KIT_DEMO_top</header>\r
+  <project-settings>\r
+    <fam>SmartFusion2</fam>\r
+    <die>M2S050T_ES</die>\r
+    <package>896 FBGA</package>\r
+    <speed-grade>-1</speed-grade>\r
+    <voltage>1.2</voltage>\r
+    <hdl-type>Verilog</hdl-type>\r
+    <project-description>\r
+    </project-description>\r
+    <location>D:/Actelprj/SF2_DEVKIT_DEMO/component/work/DEV_KIT_DEMO_top</location>\r
+    <state>GENERATED ( Wed Apr 24 17:06:15 2013 )</state>\r
+    <swide-toolchain>SoftConsole workspace generated to D:\Actelprj\SF2_DEVKIT_DEMO\SoftConsole</swide-toolchain>\r
+  </project-settings>\r
+  <site-map>\r
+  </site-map>\r
+  <fileset>\r
+    <name>HDL File(s)</name>\r
+    <file>D:\Actelprj\SF2_DEVKIT_DEMO\component\Actel\DirectCore\CoreAPB3\4.0.100\rtl\vlog\core_obfuscated\coreapb3.v</file>\r
+    <file>D:\Actelprj\SF2_DEVKIT_DEMO\component\Actel\DirectCore\CoreAPB3\4.0.100\rtl\vlog\core_obfuscated\coreapb3_iaddr_reg.v</file>\r
+    <file>D:\Actelprj\SF2_DEVKIT_DEMO\component\Actel\DirectCore\CoreAPB3\4.0.100\rtl\vlog\core_obfuscated\coreapb3_muxptob3.v</file>\r
+    <file>D:\Actelprj\SF2_DEVKIT_DEMO\component\Actel\DirectCore\COREAXI\2.0.103\rtl\vlog\core_obfuscated\axi_interconnect.v</file>\r
+    <file>D:\Actelprj\SF2_DEVKIT_DEMO\component\Actel\DirectCore\COREAXI\2.0.103\rtl\vlog\core_obfuscated\master_stage.v</file>\r
+    <file>D:\Actelprj\SF2_DEVKIT_DEMO\component\Actel\DirectCore\COREAXI\2.0.103\rtl\vlog\core_obfuscated\slave_stage.v</file>\r
+    <file>D:\Actelprj\SF2_DEVKIT_DEMO\component\Actel\DirectCore\CoreSF2Config\2.0.100\rtl\vlog\core_obfuscated\coresf2config.v</file>\r
+    <file>D:\Actelprj\SF2_DEVKIT_DEMO\component\Actel\DirectCore\CoreSF2Reset\1.0.101\rtl\vlog\core_obfuscated\coresf2reset.v</file>\r
+    <file>D:\Actelprj\SF2_DEVKIT_DEMO\component\Actel\SgCore\OSC\1.0.100\osc_comps.v</file>\r
+    <file>D:\Actelprj\SF2_DEVKIT_DEMO\component\work\DEV_KIT_DEMO\CCC_0\DEV_KIT_DEMO_CCC_0_FCCC.v</file>\r
+    <file>D:\Actelprj\SF2_DEVKIT_DEMO\component\work\DEV_KIT_DEMO\COREAXI_0\rtl\vlog\core_obfuscated\coreaxi.v</file>\r
+    <file>D:\Actelprj\SF2_DEVKIT_DEMO\component\work\DEV_KIT_DEMO\DEV_KIT_DEMO.v</file>\r
+    <file>D:\Actelprj\SF2_DEVKIT_DEMO\component\work\DEV_KIT_DEMO\FABOSC_0\DEV_KIT_DEMO_FABOSC_0_OSC.v</file>\r
+    <file>D:\Actelprj\SF2_DEVKIT_DEMO\component\work\DEV_KIT_DEMO_MSS\DEV_KIT_DEMO_MSS.v</file>\r
+    <file>D:\Actelprj\SF2_DEVKIT_DEMO\component\work\DEV_KIT_DEMO_MSS\DEV_KIT_DEMO_MSS_tmp_syn.v</file>\r
+    <file>D:\Actelprj\SF2_DEVKIT_DEMO\component\work\DEV_KIT_DEMO_top\COREABC_0\coreparameters_tgi.v</file>\r
+    <file>D:\Actelprj\SF2_DEVKIT_DEMO\component\work\DEV_KIT_DEMO_top\COREABC_0\rtl\vlog\core_obfuscated\acmtable.v</file>\r
+    <file>D:\Actelprj\SF2_DEVKIT_DEMO\component\work\DEV_KIT_DEMO_top\COREABC_0\rtl\vlog\core_obfuscated\coreabc.v</file>\r
+    <file>D:\Actelprj\SF2_DEVKIT_DEMO\component\work\DEV_KIT_DEMO_top\COREABC_0\rtl\vlog\core_obfuscated\debugblk.v</file>\r
+    <file>D:\Actelprj\SF2_DEVKIT_DEMO\component\work\DEV_KIT_DEMO_top\COREABC_0\rtl\vlog\core_obfuscated\instructions.v</file>\r
+    <file>D:\Actelprj\SF2_DEVKIT_DEMO\component\work\DEV_KIT_DEMO_top\COREABC_0\rtl\vlog\core_obfuscated\instructnvm_bb.v</file>\r
+    <file>D:\Actelprj\SF2_DEVKIT_DEMO\component\work\DEV_KIT_DEMO_top\COREABC_0\rtl\vlog\core_obfuscated\instructram.v</file>\r
+    <file>D:\Actelprj\SF2_DEVKIT_DEMO\component\work\DEV_KIT_DEMO_top\COREABC_0\rtl\vlog\core_obfuscated\iram512x9_rtl.v</file>\r
+    <file>D:\Actelprj\SF2_DEVKIT_DEMO\component\work\DEV_KIT_DEMO_top\COREABC_0\rtl\vlog\core_obfuscated\ram128x8_smartfusion2.v</file>\r
+    <file>D:\Actelprj\SF2_DEVKIT_DEMO\component\work\DEV_KIT_DEMO_top\COREABC_0\rtl\vlog\core_obfuscated\ram256x16_rtl.v</file>\r
+    <file>D:\Actelprj\SF2_DEVKIT_DEMO\component\work\DEV_KIT_DEMO_top\COREABC_0\rtl\vlog\core_obfuscated\ram256x8_rtl.v</file>\r
+    <file>D:\Actelprj\SF2_DEVKIT_DEMO\component\work\DEV_KIT_DEMO_top\COREABC_0\rtl\vlog\core_obfuscated\ramblocks.v</file>\r
+    <file>D:\Actelprj\SF2_DEVKIT_DEMO\component\work\DEV_KIT_DEMO_top\COREABC_0\rtl\vlog\core_obfuscated\support.v</file>\r
+    <file>D:\Actelprj\SF2_DEVKIT_DEMO\component\work\DEV_KIT_DEMO_top\DEV_KIT_DEMO_top.v</file>\r
+    <file>D:\Actelprj\SF2_DEVKIT_DEMO\component\work\DEV_KIT_DEMO_top\SERDES_IF_0\DEV_KIT_DEMO_top_SERDES_IF_0_SERDES_IF.v</file>\r
+    <file>D:\Actelprj\SF2_DEVKIT_DEMO\component\work\DEV_KIT_DEMO_top\SERDES_IF_0\DEV_KIT_DEMO_top_SERDES_IF_0_SERDES_IF_syn.v</file>\r
+  </fileset>\r
+  <fileset>\r
+    <name>Flash Memory File(s)</name>\r
+    <file>D:\Actelprj\SF2_DEVKIT_DEMO\component\work\./ENVM/ENVM.efc</file>\r
+    <file>D:\Actelprj\SF2_DEVKIT_DEMO\component\work\./ENVM/ENVM.efc\D:/Actelprj/SF2_DEVKIT_DEMO/component/work/DEV_KIT_DEMO_MSS/ENVM/ENVM.efc</file>\r
+  </fileset>\r
+  <io>\r
+    <port-name>USB_ULPI_DATA[3]</port-name>\r
+    <direction>INOUT</direction>\r
+    <pin-number>-</pin-number>\r
+    <io-standard>LVCMOS25</io-standard>\r
+  </io>\r
+  <io>\r
+    <port-name>MDDR_ADDR[11]</port-name>\r
+    <direction>OUT</direction>\r
+    <pin-number>-</pin-number>\r
+    <io-standard>LVCMOS25</io-standard>\r
+  </io>\r
+  <io>\r
+    <port-name>REFCLK0_P</port-name>\r
+    <direction>IN</direction>\r
+    <pin-number>-</pin-number>\r
+    <io-standard>LVCMOS25</io-standard>\r
+  </io>\r
+  <io>\r
+    <port-name>MDDR_ADDR[3]</port-name>\r
+    <direction>OUT</direction>\r
+    <pin-number>-</pin-number>\r
+    <io-standard>LVCMOS25</io-standard>\r
+  </io>\r
+  <io>\r
+    <port-name>MDDR_ADDR[15]</port-name>\r
+    <direction>OUT</direction>\r
+    <pin-number>-</pin-number>\r
+    <io-standard>LVCMOS25</io-standard>\r
+  </io>\r
+  <io>\r
+    <port-name>MDDR_DQ[10]</port-name>\r
+    <direction>INOUT</direction>\r
+    <pin-number>-</pin-number>\r
+    <io-standard>LVCMOS25</io-standard>\r
+  </io>\r
+  <io>\r
+    <port-name>I2C_0_SCL</port-name>\r
+    <direction>INOUT</direction>\r
+    <pin-number>-</pin-number>\r
+    <io-standard>LVCMOS25</io-standard>\r
+  </io>\r
+  <io>\r
+    <port-name>SPI_0_DI</port-name>\r
+    <direction>IN</direction>\r
+    <pin-number>-</pin-number>\r
+    <io-standard>LVCMOS25</io-standard>\r
+  </io>\r
+  <io>\r
+    <port-name>USB_ULPI_DATA[1]</port-name>\r
+    <direction>INOUT</direction>\r
+    <pin-number>-</pin-number>\r
+    <io-standard>LVCMOS25</io-standard>\r
+  </io>\r
+  <io>\r
+    <port-name>TXD0_N</port-name>\r
+    <direction>OUT</direction>\r
+    <pin-number>-</pin-number>\r
+    <io-standard>LVCMOS25</io-standard>\r
+  </io>\r
+  <io>\r
+    <port-name>MDDR_DQ[6]</port-name>\r
+    <direction>INOUT</direction>\r
+    <pin-number>-</pin-number>\r
+    <io-standard>LVCMOS25</io-standard>\r
+  </io>\r
+  <io>\r
+    <port-name>RXD3_N</port-name>\r
+    <direction>IN</direction>\r
+    <pin-number>-</pin-number>\r
+    <io-standard>LVCMOS25</io-standard>\r
+  </io>\r
+  <io>\r
+    <port-name>MDDR_DQ[0]</port-name>\r
+    <direction>INOUT</direction>\r
+    <pin-number>-</pin-number>\r
+    <io-standard>LVCMOS25</io-standard>\r
+  </io>\r
+  <io>\r
+    <port-name>GPIO_13_F2M</port-name>\r
+    <direction>IN</direction>\r
+    <pin-number>-</pin-number>\r
+    <io-standard>LVCMOS25</io-standard>\r
+  </io>\r
+  <io>\r
+    <port-name>MDDR_DQ[8]</port-name>\r
+    <direction>INOUT</direction>\r
+    <pin-number>-</pin-number>\r
+    <io-standard>LVCMOS25</io-standard>\r
+  </io>\r
+  <io>\r
+    <port-name>LED_6</port-name>\r
+    <direction>OUT</direction>\r
+    <pin-number>-</pin-number>\r
+    <io-standard>LVCMOS25</io-standard>\r
+  </io>\r
+  <io>\r
+    <port-name>FF_EXIT</port-name>\r
+    <direction>IN</direction>\r
+    <pin-number>-</pin-number>\r
+    <io-standard>LVCMOS25</io-standard>\r
+  </io>\r
+  <io>\r
+    <port-name>USB_ULPI_DIR</port-name>\r
+    <direction>IN</direction>\r
+    <pin-number>-</pin-number>\r
+    <io-standard>LVCMOS25</io-standard>\r
+  </io>\r
+  <io>\r
+    <port-name>RXD3_P</port-name>\r
+    <direction>IN</direction>\r
+    <pin-number>-</pin-number>\r
+    <io-standard>LVCMOS25</io-standard>\r
+  </io>\r
+  <io>\r
+    <port-name>MDDR_DQ[15]</port-name>\r
+    <direction>INOUT</direction>\r
+    <pin-number>-</pin-number>\r
+    <io-standard>LVCMOS25</io-standard>\r
+  </io>\r
+  <io>\r
+    <port-name>MDDR_ADDR[6]</port-name>\r
+    <direction>OUT</direction>\r
+    <pin-number>-</pin-number>\r
+    <io-standard>LVCMOS25</io-standard>\r
+  </io>\r
+  <io>\r
+    <port-name>GPIO_15_M2F</port-name>\r
+    <direction>OUT</direction>\r
+    <pin-number>-</pin-number>\r
+    <io-standard>LVCMOS25</io-standard>\r
+  </io>\r
+  <io>\r
+    <port-name>MDDR_ADDR[8]</port-name>\r
+    <direction>OUT</direction>\r
+    <pin-number>-</pin-number>\r
+    <io-standard>LVCMOS25</io-standard>\r
+  </io>\r
+  <io>\r
+    <port-name>SPI_0_SS0</port-name>\r
+    <direction>INOUT</direction>\r
+    <pin-number>-</pin-number>\r
+    <io-standard>LVCMOS25</io-standard>\r
+  </io>\r
+  <io>\r
+    <port-name>TXD1_P</port-name>\r
+    <direction>OUT</direction>\r
+    <pin-number>-</pin-number>\r
+    <io-standard>LVCMOS25</io-standard>\r
+  </io>\r
+  <io>\r
+    <port-name>MDDR_WE_N</port-name>\r
+    <direction>OUT</direction>\r
+    <pin-number>-</pin-number>\r
+    <io-standard>LVCMOS25</io-standard>\r
+  </io>\r
+  <io>\r
+    <port-name>MDDR_CS_N</port-name>\r
+    <direction>OUT</direction>\r
+    <pin-number>-</pin-number>\r
+    <io-standard>LVCMOS25</io-standard>\r
+  </io>\r
+  <io>\r
+    <port-name>USB_RESET_N</port-name>\r
+    <direction>OUT</direction>\r
+    <pin-number>-</pin-number>\r
+    <io-standard>LVCMOS25</io-standard>\r
+  </io>\r
+  <io>\r
+    <port-name>TXD0_P</port-name>\r
+    <direction>OUT</direction>\r
+    <pin-number>-</pin-number>\r
+    <io-standard>LVCMOS25</io-standard>\r
+  </io>\r
+  <io>\r
+    <port-name>MDDR_DQ[1]</port-name>\r
+    <direction>INOUT</direction>\r
+    <pin-number>-</pin-number>\r
+    <io-standard>LVCMOS25</io-standard>\r
+  </io>\r
+  <io>\r
+    <port-name>USB_ULPI_DATA[6]</port-name>\r
+    <direction>INOUT</direction>\r
+    <pin-number>-</pin-number>\r
+    <io-standard>LVCMOS25</io-standard>\r
+  </io>\r
+  <io>\r
+    <port-name>MMUART_1_TXD_M2F</port-name>\r
+    <direction>OUT</direction>\r
+    <pin-number>-</pin-number>\r
+    <io-standard>LVCMOS25</io-standard>\r
+  </io>\r
+  <io>\r
+    <port-name>MDDR_DQS_N[1]</port-name>\r
+    <direction>INOUT</direction>\r
+    <pin-number>-</pin-number>\r
+    <io-standard>LVCMOS25</io-standard>\r
+  </io>\r
+  <io>\r
+    <port-name>MDDR_ADDR[9]</port-name>\r
+    <direction>OUT</direction>\r
+    <pin-number>-</pin-number>\r
+    <io-standard>LVCMOS25</io-standard>\r
+  </io>\r
+  <io>\r
+    <port-name>MDDR_ADDR[0]</port-name>\r
+    <direction>OUT</direction>\r
+    <pin-number>-</pin-number>\r
+    <io-standard>LVCMOS25</io-standard>\r
+  </io>\r
+  <io>\r
+    <port-name>MDDR_DQ[13]</port-name>\r
+    <direction>INOUT</direction>\r
+    <pin-number>-</pin-number>\r
+    <io-standard>LVCMOS25</io-standard>\r
+  </io>\r
+  <io>\r
+    <port-name>MDDR_ADDR[5]</port-name>\r
+    <direction>OUT</direction>\r
+    <pin-number>-</pin-number>\r
+    <io-standard>LVCMOS25</io-standard>\r
+  </io>\r
+  <io>\r
+    <port-name>LED_1</port-name>\r
+    <direction>OUT</direction>\r
+    <pin-number>-</pin-number>\r
+    <io-standard>LVCMOS25</io-standard>\r
+  </io>\r
+  <io>\r
+    <port-name>SPI_0_CLK</port-name>\r
+    <direction>INOUT</direction>\r
+    <pin-number>-</pin-number>\r
+    <io-standard>LVCMOS25</io-standard>\r
+  </io>\r
+  <io>\r
+    <port-name>USB_ULPI_XCLK</port-name>\r
+    <direction>INOUT</direction>\r
+    <pin-number>-</pin-number>\r
+    <io-standard>LVCMOS25</io-standard>\r
+  </io>\r
+  <io>\r
+    <port-name>MDDR_RESET_N</port-name>\r
+    <direction>OUT</direction>\r
+    <pin-number>-</pin-number>\r
+    <io-standard>LVCMOS25</io-standard>\r
+  </io>\r
+  <io>\r
+    <port-name>GPIO_4_F2M</port-name>\r
+    <direction>IN</direction>\r
+    <pin-number>-</pin-number>\r
+    <io-standard>LVCMOS25</io-standard>\r
+  </io>\r
+  <io>\r
+    <port-name>MDDR_ADDR[7]</port-name>\r
+    <direction>OUT</direction>\r
+    <pin-number>-</pin-number>\r
+    <io-standard>LVCMOS25</io-standard>\r
+  </io>\r
+  <io>\r
+    <port-name>MDDR_DQ[3]</port-name>\r
+    <direction>INOUT</direction>\r
+    <pin-number>-</pin-number>\r
+    <io-standard>LVCMOS25</io-standard>\r
+  </io>\r
+  <io>\r
+    <port-name>RXD1_N</port-name>\r
+    <direction>IN</direction>\r
+    <pin-number>-</pin-number>\r
+    <io-standard>LVCMOS25</io-standard>\r
+  </io>\r
+  <io>\r
+    <port-name>MDDR_ADDR[1]</port-name>\r
+    <direction>OUT</direction>\r
+    <pin-number>-</pin-number>\r
+    <io-standard>LVCMOS25</io-standard>\r
+  </io>\r
+  <io>\r
+    <port-name>MDDR_DQ[14]</port-name>\r
+    <direction>INOUT</direction>\r
+    <pin-number>-</pin-number>\r
+    <io-standard>LVCMOS25</io-standard>\r
+  </io>\r
+  <io>\r
+    <port-name>USB_ULPI_STP</port-name>\r
+    <direction>OUT</direction>\r
+    <pin-number>-</pin-number>\r
+    <io-standard>LVCMOS25</io-standard>\r
+  </io>\r
+  <io>\r
+    <port-name>MDDR_DQS[1]</port-name>\r
+    <direction>INOUT</direction>\r
+    <pin-number>-</pin-number>\r
+    <io-standard>LVCMOS25</io-standard>\r
+  </io>\r
+  <io>\r
+    <port-name>MDDR_ODT</port-name>\r
+    <direction>OUT</direction>\r
+    <pin-number>-</pin-number>\r
+    <io-standard>LVCMOS25</io-standard>\r
+  </io>\r
+  <io>\r
+    <port-name>RXD0_N</port-name>\r
+    <direction>IN</direction>\r
+    <pin-number>-</pin-number>\r
+    <io-standard>LVCMOS25</io-standard>\r
+  </io>\r
+  <io>\r
+    <port-name>TXD2_N</port-name>\r
+    <direction>OUT</direction>\r
+    <pin-number>-</pin-number>\r
+    <io-standard>LVCMOS25</io-standard>\r
+  </io>\r
+  <io>\r
+    <port-name>MDDR_DQ[2]</port-name>\r
+    <direction>INOUT</direction>\r
+    <pin-number>-</pin-number>\r
+    <io-standard>LVCMOS25</io-standard>\r
+  </io>\r
+  <io>\r
+    <port-name>GPIO_1_F2M</port-name>\r
+    <direction>IN</direction>\r
+    <pin-number>-</pin-number>\r
+    <io-standard>LVCMOS25</io-standard>\r
+  </io>\r
+  <io>\r
+    <port-name>CLK0_PAD</port-name>\r
+    <direction>IN</direction>\r
+    <pin-number>-</pin-number>\r
+    <io-standard>LVCMOS25</io-standard>\r
+  </io>\r
+  <io>\r
+    <port-name>MDDR_ADDR[12]</port-name>\r
+    <direction>OUT</direction>\r
+    <pin-number>-</pin-number>\r
+    <io-standard>LVCMOS25</io-standard>\r
+  </io>\r
+  <io>\r
+    <port-name>SPI_0_DO</port-name>\r
+    <direction>OUT</direction>\r
+    <pin-number>-</pin-number>\r
+    <io-standard>LVCMOS25</io-standard>\r
+  </io>\r
+  <io>\r
+    <port-name>MDDR_ADDR[14]</port-name>\r
+    <direction>OUT</direction>\r
+    <pin-number>-</pin-number>\r
+    <io-standard>LVCMOS25</io-standard>\r
+  </io>\r
+  <io>\r
+    <port-name>GPIO_2_F2M</port-name>\r
+    <direction>IN</direction>\r
+    <pin-number>-</pin-number>\r
+    <io-standard>LVCMOS25</io-standard>\r
+  </io>\r
+  <io>\r
+    <port-name>MDDR_DQ[5]</port-name>\r
+    <direction>INOUT</direction>\r
+    <pin-number>-</pin-number>\r
+    <io-standard>LVCMOS25</io-standard>\r
+  </io>\r
+  <io>\r
+    <port-name>MDDR_DM_RDQS[1]</port-name>\r
+    <direction>INOUT</direction>\r
+    <pin-number>-</pin-number>\r
+    <io-standard>LVCMOS25</io-standard>\r
+  </io>\r
+  <io>\r
+    <port-name>MDDR_BA[1]</port-name>\r
+    <direction>OUT</direction>\r
+    <pin-number>-</pin-number>\r
+    <io-standard>LVCMOS25</io-standard>\r
+  </io>\r
+  <io>\r
+    <port-name>MDDR_DQS_TMATCH_0_IN</port-name>\r
+    <direction>IN</direction>\r
+    <pin-number>-</pin-number>\r
+    <io-standard>LVCMOS25</io-standard>\r
+  </io>\r
+  <io>\r
+    <port-name>MDDR_CLK_N</port-name>\r
+    <direction>OUT</direction>\r
+    <pin-number>-</pin-number>\r
+    <io-standard>LVCMOS25</io-standard>\r
+  </io>\r
+  <io>\r
+    <port-name>USB_ULPI_DATA[4]</port-name>\r
+    <direction>INOUT</direction>\r
+    <pin-number>-</pin-number>\r
+    <io-standard>LVCMOS25</io-standard>\r
+  </io>\r
+  <io>\r
+    <port-name>MDDR_CAS_N</port-name>\r
+    <direction>OUT</direction>\r
+    <pin-number>-</pin-number>\r
+    <io-standard>LVCMOS25</io-standard>\r
+  </io>\r
+  <io>\r
+    <port-name>GPIO_8_F2M</port-name>\r
+    <direction>IN</direction>\r
+    <pin-number>-</pin-number>\r
+    <io-standard>LVCMOS25</io-standard>\r
+  </io>\r
+  <io>\r
+    <port-name>MDDR_DQS_N[0]</port-name>\r
+    <direction>INOUT</direction>\r
+    <pin-number>-</pin-number>\r
+    <io-standard>LVCMOS25</io-standard>\r
+  </io>\r
+  <io>\r
+    <port-name>I2C_1_SDA</port-name>\r
+    <direction>INOUT</direction>\r
+    <pin-number>-</pin-number>\r
+    <io-standard>LVCMOS25</io-standard>\r
+  </io>\r
+  <io>\r
+    <port-name>MDDR_DQ[11]</port-name>\r
+    <direction>INOUT</direction>\r
+    <pin-number>-</pin-number>\r
+    <io-standard>LVCMOS25</io-standard>\r
+  </io>\r
+  <io>\r
+    <port-name>DEVRST_N</port-name>\r
+    <direction>IN</direction>\r
+    <pin-number>-</pin-number>\r
+    <io-standard>LVCMOS25</io-standard>\r
+  </io>\r
+  <io>\r
+    <port-name>TXD1_N</port-name>\r
+    <direction>OUT</direction>\r
+    <pin-number>-</pin-number>\r
+    <io-standard>LVCMOS25</io-standard>\r
+  </io>\r
+  <io>\r
+    <port-name>MDDR_BA[2]</port-name>\r
+    <direction>OUT</direction>\r
+    <pin-number>-</pin-number>\r
+    <io-standard>LVCMOS25</io-standard>\r
+  </io>\r
+  <io>\r
+    <port-name>GPIO_11_F2M</port-name>\r
+    <direction>IN</direction>\r
+    <pin-number>-</pin-number>\r
+    <io-standard>LVCMOS25</io-standard>\r
+  </io>\r
+  <io>\r
+    <port-name>RXD1_P</port-name>\r
+    <direction>IN</direction>\r
+    <pin-number>-</pin-number>\r
+    <io-standard>LVCMOS25</io-standard>\r
+  </io>\r
+  <io>\r
+    <port-name>MDDR_DM_RDQS[0]</port-name>\r
+    <direction>INOUT</direction>\r
+    <pin-number>-</pin-number>\r
+    <io-standard>LVCMOS25</io-standard>\r
+  </io>\r
+  <io>\r
+    <port-name>MDDR_DQS_TMATCH_0_OUT</port-name>\r
+    <direction>OUT</direction>\r
+    <pin-number>-</pin-number>\r
+    <io-standard>LVCMOS25</io-standard>\r
+  </io>\r
+  <io>\r
+    <port-name>MDDR_CKE</port-name>\r
+    <direction>OUT</direction>\r
+    <pin-number>-</pin-number>\r
+    <io-standard>LVCMOS25</io-standard>\r
+  </io>\r
+  <io>\r
+    <port-name>MMUART_1_RXD_F2M</port-name>\r
+    <direction>IN</direction>\r
+    <pin-number>-</pin-number>\r
+    <io-standard>LVCMOS25</io-standard>\r
+  </io>\r
+  <io>\r
+    <port-name>MDDR_DQS[0]</port-name>\r
+    <direction>INOUT</direction>\r
+    <pin-number>-</pin-number>\r
+    <io-standard>LVCMOS25</io-standard>\r
+  </io>\r
+  <io>\r
+    <port-name>MDDR_BA[0]</port-name>\r
+    <direction>OUT</direction>\r
+    <pin-number>-</pin-number>\r
+    <io-standard>LVCMOS25</io-standard>\r
+  </io>\r
+  <io>\r
+    <port-name>USB_ULPI_DATA[5]</port-name>\r
+    <direction>INOUT</direction>\r
+    <pin-number>-</pin-number>\r
+    <io-standard>LVCMOS25</io-standard>\r
+  </io>\r
+  <io>\r
+    <port-name>I2C_0_SDA</port-name>\r
+    <direction>INOUT</direction>\r
+    <pin-number>-</pin-number>\r
+    <io-standard>LVCMOS25</io-standard>\r
+  </io>\r
+  <io>\r
+    <port-name>MDDR_ADDR[13]</port-name>\r
+    <direction>OUT</direction>\r
+    <pin-number>-</pin-number>\r
+    <io-standard>LVCMOS25</io-standard>\r
+  </io>\r
+  <io>\r
+    <port-name>MDDR_CLK</port-name>\r
+    <direction>OUT</direction>\r
+    <pin-number>-</pin-number>\r
+    <io-standard>LVCMOS25</io-standard>\r
+  </io>\r
+  <io>\r
+    <port-name>RXD2_N</port-name>\r
+    <direction>IN</direction>\r
+    <pin-number>-</pin-number>\r
+    <io-standard>LVCMOS25</io-standard>\r
+  </io>\r
+  <io>\r
+    <port-name>MDDR_ADDR[4]</port-name>\r
+    <direction>OUT</direction>\r
+    <pin-number>-</pin-number>\r
+    <io-standard>LVCMOS25</io-standard>\r
+  </io>\r
+  <io>\r
+    <port-name>MDDR_DQ[12]</port-name>\r
+    <direction>INOUT</direction>\r
+    <pin-number>-</pin-number>\r
+    <io-standard>LVCMOS25</io-standard>\r
+  </io>\r
+  <io>\r
+    <port-name>MDDR_DQ[4]</port-name>\r
+    <direction>INOUT</direction>\r
+    <pin-number>-</pin-number>\r
+    <io-standard>LVCMOS25</io-standard>\r
+  </io>\r
+  <io>\r
+    <port-name>I2C_1_SCL</port-name>\r
+    <direction>INOUT</direction>\r
+    <pin-number>-</pin-number>\r
+    <io-standard>LVCMOS25</io-standard>\r
+  </io>\r
+  <io>\r
+    <port-name>MDDR_RAS_N</port-name>\r
+    <direction>OUT</direction>\r
+    <pin-number>-</pin-number>\r
+    <io-standard>LVCMOS25</io-standard>\r
+  </io>\r
+  <io>\r
+    <port-name>TXD3_N</port-name>\r
+    <direction>OUT</direction>\r
+    <pin-number>-</pin-number>\r
+    <io-standard>LVCMOS25</io-standard>\r
+  </io>\r
+  <io>\r
+    <port-name>REFCLK0_N</port-name>\r
+    <direction>IN</direction>\r
+    <pin-number>-</pin-number>\r
+    <io-standard>LVCMOS25</io-standard>\r
+  </io>\r
+  <io>\r
+    <port-name>GPIO_12_F2M</port-name>\r
+    <direction>IN</direction>\r
+    <pin-number>-</pin-number>\r
+    <io-standard>LVCMOS25</io-standard>\r
+  </io>\r
+  <io>\r
+    <port-name>MDDR_ADDR[10]</port-name>\r
+    <direction>OUT</direction>\r
+    <pin-number>-</pin-number>\r
+    <io-standard>LVCMOS25</io-standard>\r
+  </io>\r
+  <io>\r
+    <port-name>MDDR_ADDR[2]</port-name>\r
+    <direction>OUT</direction>\r
+    <pin-number>-</pin-number>\r
+    <io-standard>LVCMOS25</io-standard>\r
+  </io>\r
+  <io>\r
+    <port-name>RXD2_P</port-name>\r
+    <direction>IN</direction>\r
+    <pin-number>-</pin-number>\r
+    <io-standard>LVCMOS25</io-standard>\r
+  </io>\r
+  <io>\r
+    <port-name>USB_ULPI_DATA[0]</port-name>\r
+    <direction>INOUT</direction>\r
+    <pin-number>-</pin-number>\r
+    <io-standard>LVCMOS25</io-standard>\r
+  </io>\r
+  <io>\r
+    <port-name>TXD2_P</port-name>\r
+    <direction>OUT</direction>\r
+    <pin-number>-</pin-number>\r
+    <io-standard>LVCMOS25</io-standard>\r
+  </io>\r
+  <io>\r
+    <port-name>USB_ULPI_DATA[2]</port-name>\r
+    <direction>INOUT</direction>\r
+    <pin-number>-</pin-number>\r
+    <io-standard>LVCMOS25</io-standard>\r
+  </io>\r
+  <io>\r
+    <port-name>USB_ULPI_NXT</port-name>\r
+    <direction>IN</direction>\r
+    <pin-number>-</pin-number>\r
+    <io-standard>LVCMOS25</io-standard>\r
+  </io>\r
+  <io>\r
+    <port-name>GPIO_14_M2F</port-name>\r
+    <direction>OUT</direction>\r
+    <pin-number>-</pin-number>\r
+    <io-standard>LVCMOS25</io-standard>\r
+  </io>\r
+  <io>\r
+    <port-name>MDDR_DQ[7]</port-name>\r
+    <direction>INOUT</direction>\r
+    <pin-number>-</pin-number>\r
+    <io-standard>LVCMOS25</io-standard>\r
+  </io>\r
+  <io>\r
+    <port-name>MDDR_DQ[9]</port-name>\r
+    <direction>INOUT</direction>\r
+    <pin-number>-</pin-number>\r
+    <io-standard>LVCMOS25</io-standard>\r
+  </io>\r
+  <io>\r
+    <port-name>TXD3_P</port-name>\r
+    <direction>OUT</direction>\r
+    <pin-number>-</pin-number>\r
+    <io-standard>LVCMOS25</io-standard>\r
+  </io>\r
+  <io>\r
+    <port-name>RXD0_P</port-name>\r
+    <direction>IN</direction>\r
+    <pin-number>-</pin-number>\r
+    <io-standard>LVCMOS25</io-standard>\r
+  </io>\r
+  <io>\r
+    <port-name>USB_ULPI_DATA[7]</port-name>\r
+    <direction>INOUT</direction>\r
+    <pin-number>-</pin-number>\r
+    <io-standard>LVCMOS25</io-standard>\r
+  </io>\r
+  <core type="SpiritModule">\r
+    <core-exttype>IP</core-exttype>\r
+    <core-type>SpiritModule</core-type>\r
+    <core-vendor>Actel</core-vendor>\r
+    <core-lib>DirectCore</core-lib>\r
+    <core-intname>COREABC</core-intname>\r
+    <core-ver>3.4.101</core-ver>\r
+    <core-desc>CoreABC (APB Bus Controller) is a simple, configurable, low gate count, programmable state machine/controller primarily targeted towards the implementation of AMBA (Advanced Microcontroller Bus Architecture) APB (Advanced Peripheral Bus) based designs. It is particularly suitable where:\r
+\r
+- a programmable controller is required but a "full blown" CPU such as a Core8051s or Cortex-M1 is not needed or cannot be justified due to cost or resource/size constraints;\r
+- a "full blown" CPU based system requires a CoreABC based programmable "offload engine/coprocessor" subsystem for performance reasons;\r
+- an Actel Fusion system using, for example, CoreAI, CorePWM etc. requires programmable control either as a standalone design or as a Fusion analog "offload engine/coprocessor" for a larger CPU based system.\r
+\r
+CoreABC is available through the Libero IDE IP Catalog through which it can be downloaded from a remote web based repository and installed into the user's local vault ready for use. It operates natively within the SmartDesign design entry environment allowing it to be easily instantiated, configured, connected to other IP core instances and generated ready for simulation, synthesis etc.\r
+CoreABC is an AMBA3 APB master which can connect to and manage any APB slave peripherals via an AMBA3 APB bus fabric component such as CoreAPB3.\r
+\r
+CoreABC supports a comprehensive assembler based configurable instruction set architecture and extensive and flexible configuration of size and feature options allowing it to be tuned to meet the resource constraints and processing power requirements of a wide variety of applications.\r
+CoreABC supports three program storage modes:\r
+\r
+- "Hard" mode: program image stored in an internal ROM implemented in FPGA fabric tiles;\r
+- "Soft" mode: program image stored in Actel FPGA RAM blocks which are initialized at runtime from the binary image stored in Fusion NVM or an external flash memory;\r
+- "NVM" mode (Fusion only): program image stored in and executed directly from Fusion NVM.\r
+</core-desc>\r
+    <core-param>\r
+      <param-name>NVM with calibration data:</param-name>\r
+      <param-value>true</param-value>\r
+      <param-hdlname>ACT_CALIBRATIONDATA</param-hdlname>\r
+      <param-hdlvalue>1</param-hdlvalue>\r
+      <param-tag>spirit:hwParameter</param-tag>\r
+    </core-param>\r
+    <core-param>\r
+      <param-name>APB Slot Size:</param-name>\r
+      <param-value>64k locations</param-value>\r
+      <param-hdlname>APB_AWIDTH</param-hdlname>\r
+      <param-hdlvalue>16</param-hdlvalue>\r
+      <param-tag>spirit:hwParameter</param-tag>\r
+    </core-param>\r
+    <core-param>\r
+      <param-name>APB Data Bus Width:</param-name>\r
+      <param-value>32</param-value>\r
+      <param-hdlname>APB_DWIDTH</param-hdlname>\r
+      <param-hdlvalue>32</param-hdlvalue>\r
+      <param-tag>spirit:hwParameter</param-tag>\r
+    </core-param>\r
+    <core-param>\r
+      <param-name>Number of APB Slots:</param-name>\r
+      <param-value>16</param-value>\r
+      <param-hdlname>APB_SDEPTH</param-hdlname>\r
+      <param-hdlvalue>16</param-hdlvalue>\r
+      <param-tag>spirit:hwParameter</param-tag>\r
+    </core-param>\r
+    <core-param>\r
+      <param-name>Verbose Simulation Log:</param-name>\r
+      <param-value>true</param-value>\r
+      <param-hdlname>DEBUG</param-hdlname>\r
+      <param-hdlvalue>1</param-hdlvalue>\r
+      <param-tag>spirit:hwParameter</param-tag>\r
+    </core-param>\r
+    <core-param>\r
+      <param-name>APBWRT ACM</param-name>\r
+      <param-value>false</param-value>\r
+      <param-hdlname>EN_ACM</param-hdlname>\r
+      <param-hdlvalue>0</param-hdlvalue>\r
+      <param-tag>spirit:hwParameter</param-tag>\r
+    </core-param>\r
+    <core-param>\r
+      <param-name>ADD, SUB, DEC, CMPLEQ</param-name>\r
+      <param-value>true</param-value>\r
+      <param-hdlname>EN_ADD</param-hdlname>\r
+      <param-hdlvalue>1</param-hdlvalue>\r
+      <param-tag>spirit:hwParameter</param-tag>\r
+    </core-param>\r
+    <core-param>\r
+      <param-name>ALU Operations from Memory:</param-name>\r
+      <param-value>false</param-value>\r
+      <param-hdlname>EN_ALURAM</param-hdlname>\r
+      <param-hdlvalue>0</param-hdlvalue>\r
+      <param-tag>spirit:hwParameter</param-tag>\r
+    </core-param>\r
+    <core-param>\r
+      <param-name>AND, BITCLR, BITTST</param-name>\r
+      <param-value>true</param-value>\r
+      <param-hdlname>EN_AND</param-hdlname>\r
+      <param-hdlvalue>1</param-hdlvalue>\r
+      <param-tag>spirit:hwParameter</param-tag>\r
+    </core-param>\r
+    <core-param>\r
+      <param-name>CALL, RETURN, RETISR</param-name>\r
+      <param-value>true</param-value>\r
+      <param-hdlname>EN_CALL</param-hdlname>\r
+      <param-hdlvalue>1</param-hdlvalue>\r
+      <param-tag>spirit:hwParameter</param-tag>\r
+    </core-param>\r
+    <core-param>\r
+      <param-name>Supported Data Sources:</param-name>\r
+      <param-value>Accumulator and Immediate</param-value>\r
+      <param-hdlname>EN_DATAM</param-hdlname>\r
+      <param-hdlvalue>2</param-hdlvalue>\r
+      <param-tag>spirit:hwParameter</param-tag>\r
+    </core-param>\r
+    <core-param>\r
+      <param-name>INC</param-name>\r
+      <param-value>true</param-value>\r
+      <param-hdlname>EN_INC</param-hdlname>\r
+      <param-hdlvalue>1</param-hdlvalue>\r
+      <param-tag>spirit:hwParameter</param-tag>\r
+    </core-param>\r
+    <core-param>\r
+      <param-name>APB Indirect Addressing:</param-name>\r
+      <param-value>false</param-value>\r
+      <param-hdlname>EN_INDIRECT</param-hdlname>\r
+      <param-hdlvalue>0</param-hdlvalue>\r
+      <param-tag>spirit:hwParameter</param-tag>\r
+    </core-param>\r
+    <core-param>\r
+      <param-name>Interrupt Support:</param-name>\r
+      <param-value>Disabled</param-value>\r
+      <param-hdlname>EN_INT</param-hdlname>\r
+      <param-hdlvalue>0</param-hdlvalue>\r
+      <param-tag>spirit:hwParameter</param-tag>\r
+    </core-param>\r
+    <core-param>\r
+      <param-name>IOREAD</param-name>\r
+      <param-value>true</param-value>\r
+      <param-hdlname>EN_IOREAD</param-hdlname>\r
+      <param-hdlvalue>1</param-hdlvalue>\r
+      <param-tag>spirit:hwParameter</param-tag>\r
+    </core-param>\r
+    <core-param>\r
+      <param-name>IOWRT</param-name>\r
+      <param-value>true</param-value>\r
+      <param-hdlname>EN_IOWRT</param-hdlname>\r
+      <param-hdlvalue>1</param-hdlvalue>\r
+      <param-tag>spirit:hwParameter</param-tag>\r
+    </core-param>\r
+    <core-param>\r
+      <param-name>MULT</param-name>\r
+      <param-value>Not Implemented</param-value>\r
+      <param-hdlname>EN_MULT</param-hdlname>\r
+      <param-hdlvalue>0</param-hdlvalue>\r
+      <param-tag>spirit:hwParameter</param-tag>\r
+    </core-param>\r
+    <core-param>\r
+      <param-name>OR, BITSET</param-name>\r
+      <param-value>true</param-value>\r
+      <param-hdlname>EN_OR</param-hdlname>\r
+      <param-hdlvalue>1</param-hdlvalue>\r
+      <param-tag>spirit:hwParameter</param-tag>\r
+    </core-param>\r
+    <core-param>\r
+      <param-name>PUSH, POP</param-name>\r
+      <param-value>true</param-value>\r
+      <param-hdlname>EN_PUSH</param-hdlname>\r
+      <param-hdlvalue>1</param-hdlvalue>\r
+      <param-tag>spirit:hwParameter</param-tag>\r
+    </core-param>\r
+    <core-param>\r
+      <param-name>Internal Data/Stack Memory:</param-name>\r
+      <param-value>true</param-value>\r
+      <param-hdlname>EN_RAM</param-hdlname>\r
+      <param-hdlvalue>1</param-hdlvalue>\r
+      <param-tag>spirit:hwParameter</param-tag>\r
+    </core-param>\r
+    <core-param>\r
+      <param-name>SHL, ROL</param-name>\r
+      <param-value>true</param-value>\r
+      <param-hdlname>EN_SHL</param-hdlname>\r
+      <param-hdlvalue>1</param-hdlvalue>\r
+      <param-tag>spirit:hwParameter</param-tag>\r
+    </core-param>\r
+    <core-param>\r
+      <param-name>SHR, ROR</param-name>\r
+      <param-value>true</param-value>\r
+      <param-hdlname>EN_SHR</param-hdlname>\r
+      <param-hdlvalue>1</param-hdlvalue>\r
+      <param-tag>spirit:hwParameter</param-tag>\r
+    </core-param>\r
+    <core-param>\r
+      <param-name>XOR, CMP</param-name>\r
+      <param-value>true</param-value>\r
+      <param-hdlname>EN_XOR</param-hdlname>\r
+      <param-hdlvalue>1</param-hdlvalue>\r
+      <param-tag>spirit:hwParameter</param-tag>\r
+    </core-param>\r
+    <core-param>\r
+      <param-name>FPGA Family:</param-name>\r
+      <param-value>SmartFusion2</param-value>\r
+      <param-hdlname>FAMILY</param-hdlname>\r
+      <param-hdlvalue>19</param-hdlvalue>\r
+      <param-tag>spirit:hwParameter</param-tag>\r
+    </core-param>\r
+    <core-param>\r
+      <param-name>Maximum Number of Instructions:</param-name>\r
+      <param-value>64</param-value>\r
+      <param-hdlname>ICWIDTH</param-hdlname>\r
+      <param-hdlvalue>6</param-hdlvalue>\r
+      <param-tag>spirit:hwParameter</param-tag>\r
+    </core-param>\r
+    <core-param>\r
+      <param-name>Number of I/O Flags:</param-name>\r
+      <param-value>0</param-value>\r
+      <param-hdlname>IFWIDTH</param-hdlname>\r
+      <param-hdlvalue>0</param-hdlvalue>\r
+      <param-tag>spirit:hwParameter</param-tag>\r
+    </core-param>\r
+    <core-param>\r
+      <param-name>Number of I/O Inputs:</param-name>\r
+      <param-value>1</param-value>\r
+      <param-hdlname>IIWIDTH</param-hdlname>\r
+      <param-hdlvalue>1</param-hdlvalue>\r
+      <param-tag>spirit:hwParameter</param-tag>\r
+    </core-param>\r
+    <core-param>\r
+      <param-name>Instruction Memory Access</param-name>\r
+      <param-value>None</param-value>\r
+      <param-hdlname>IMEM_APB_ACCESS</param-hdlname>\r
+      <param-hdlvalue>0</param-hdlvalue>\r
+      <param-tag>spirit:hwParameter</param-tag>\r
+    </core-param>\r
+    <core-param>\r
+      <param-name>Initialization Width:</param-name>\r
+      <param-value>11</param-value>\r
+      <param-hdlname>INITWIDTH</param-hdlname>\r
+      <param-hdlvalue>11</param-hdlvalue>\r
+      <param-tag>spirit:hwParameter</param-tag>\r
+    </core-param>\r
+    <core-param>\r
+      <param-name>Instruction Store:</param-name>\r
+      <param-value>Hard (FPGA Tiles)</param-value>\r
+      <param-hdlname>INSMODE</param-hdlname>\r
+      <param-hdlvalue>0</param-hdlvalue>\r
+      <param-tag>spirit:hwParameter</param-tag>\r
+    </core-param>\r
+    <core-param>\r
+      <param-name>Number of I/O Outputs:</param-name>\r
+      <param-value>1</param-value>\r
+      <param-hdlname>IOWIDTH</param-hdlname>\r
+      <param-hdlvalue>1</param-hdlvalue>\r
+      <param-tag>spirit:hwParameter</param-tag>\r
+    </core-param>\r
+    <core-param>\r
+      <param-name>ISR Address:</param-name>\r
+      <param-value>1</param-value>\r
+      <param-hdlname>ISRADDR</param-hdlname>\r
+      <param-hdlvalue>1</param-hdlvalue>\r
+      <param-tag>spirit:hwParameter</param-tag>\r
+    </core-param>\r
+    <core-param>\r
+      <param-name>\r
+      </param-name>\r
+      <param-value>32</param-value>\r
+      <param-hdlname>MAX_NVMDWIDTH</param-hdlname>\r
+      <param-hdlvalue>32</param-hdlvalue>\r
+      <param-tag>spirit:hwParameter</param-tag>\r
+    </core-param>\r
+    <core-param>\r
+      <param-name>Stack Size:</param-name>\r
+      <param-value>16</param-value>\r
+      <param-hdlname>STWIDTH</param-hdlname>\r
+      <param-hdlvalue>4</param-hdlvalue>\r
+      <param-tag>spirit:hwParameter</param-tag>\r
+    </core-param>\r
+    <core-param>\r
+      <param-name>Test Mode:</param-name>\r
+      <param-value>User  configured code</param-value>\r
+      <param-hdlname>TESTMODE</param-hdlname>\r
+      <param-hdlvalue>0</param-hdlvalue>\r
+      <param-tag>spirit:hwParameter</param-tag>\r
+    </core-param>\r
+    <core-param>\r
+      <param-name>\r
+      </param-name>\r
+      <param-value>26</param-value>\r
+      <param-hdlname>UNIQ_STRING_LENGTH</param-hdlname>\r
+      <param-hdlvalue>26</param-hdlvalue>\r
+      <param-tag>spirit:hwParameter</param-tag>\r
+    </core-param>\r
+    <core-param>\r
+      <param-name>Z Register Size (Bits):</param-name>\r
+      <param-value>Disabled</param-value>\r
+      <param-hdlname>ZRWIDTH</param-hdlname>\r
+      <param-hdlvalue>0</param-hdlvalue>\r
+      <param-tag>spirit:hwParameter</param-tag>\r
+    </core-param>\r
+    <core-name>COREABC_0</core-name>\r
+  </core>\r
+  <core type="SpiritModule">\r
+    <core-exttype>IP</core-exttype>\r
+    <core-type>SpiritModule</core-type>\r
+    <core-vendor>Actel</core-vendor>\r
+    <core-lib>DirectCore</core-lib>\r
+    <core-intname>CoreAPB3</core-intname>\r
+    <core-ver>4.0.100</core-ver>\r
+    <core-desc>\r
+The CoreAPB3 component implements an APB3 (AMBA3 APB) fabric, which is backwards compatible with APB2 slave peripherals.\r
+\r
+There is one APB3 Master interface.\r
+\r
+        </core-desc>\r
+    <core-param>\r
+      <param-name>APB Master Data Bus Width</param-name>\r
+      <param-value>32-bit</param-value>\r
+      <param-hdlname>APB_DWIDTH</param-hdlname>\r
+      <param-hdlvalue>32</param-hdlvalue>\r
+      <param-tag>spirit:hwParameter</param-tag>\r
+    </core-param>\r
+    <core-param>\r
+      <param-name>Slot 0:</param-name>\r
+      <param-value>true</param-value>\r
+      <param-hdlname>APBSLOT0ENABLE</param-hdlname>\r
+      <param-hdlvalue>1</param-hdlvalue>\r
+      <param-tag>spirit:hwParameter</param-tag>\r
+    </core-param>\r
+    <core-param>\r
+      <param-name>Slot 1:</param-name>\r
+      <param-value>false</param-value>\r
+      <param-hdlname>APBSLOT1ENABLE</param-hdlname>\r
+      <param-hdlvalue>0</param-hdlvalue>\r
+      <param-tag>spirit:hwParameter</param-tag>\r
+    </core-param>\r
+    <core-param>\r
+      <param-name>Slot 2:</param-name>\r
+      <param-value>false</param-value>\r
+      <param-hdlname>APBSLOT2ENABLE</param-hdlname>\r
+      <param-hdlvalue>0</param-hdlvalue>\r
+      <param-tag>spirit:hwParameter</param-tag>\r
+    </core-param>\r
+    <core-param>\r
+      <param-name>Slot 3:</param-name>\r
+      <param-value>false</param-value>\r
+      <param-hdlname>APBSLOT3ENABLE</param-hdlname>\r
+      <param-hdlvalue>0</param-hdlvalue>\r
+      <param-tag>spirit:hwParameter</param-tag>\r
+    </core-param>\r
+    <core-param>\r
+      <param-name>Slot 4:</param-name>\r
+      <param-value>false</param-value>\r
+      <param-hdlname>APBSLOT4ENABLE</param-hdlname>\r
+      <param-hdlvalue>0</param-hdlvalue>\r
+      <param-tag>spirit:hwParameter</param-tag>\r
+    </core-param>\r
+    <core-param>\r
+      <param-name>Slot 5:</param-name>\r
+      <param-value>false</param-value>\r
+      <param-hdlname>APBSLOT5ENABLE</param-hdlname>\r
+      <param-hdlvalue>0</param-hdlvalue>\r
+      <param-tag>spirit:hwParameter</param-tag>\r
+    </core-param>\r
+    <core-param>\r
+      <param-name>Slot 6:</param-name>\r
+      <param-value>false</param-value>\r
+      <param-hdlname>APBSLOT6ENABLE</param-hdlname>\r
+      <param-hdlvalue>0</param-hdlvalue>\r
+      <param-tag>spirit:hwParameter</param-tag>\r
+    </core-param>\r
+    <core-param>\r
+      <param-name>Slot 7:</param-name>\r
+      <param-value>false</param-value>\r
+      <param-hdlname>APBSLOT7ENABLE</param-hdlname>\r
+      <param-hdlvalue>0</param-hdlvalue>\r
+      <param-tag>spirit:hwParameter</param-tag>\r
+    </core-param>\r
+    <core-param>\r
+      <param-name>Slot 8:</param-name>\r
+      <param-value>false</param-value>\r
+      <param-hdlname>APBSLOT8ENABLE</param-hdlname>\r
+      <param-hdlvalue>0</param-hdlvalue>\r
+      <param-tag>spirit:hwParameter</param-tag>\r
+    </core-param>\r
+    <core-param>\r
+      <param-name>Slot 9:</param-name>\r
+      <param-value>false</param-value>\r
+      <param-hdlname>APBSLOT9ENABLE</param-hdlname>\r
+      <param-hdlvalue>0</param-hdlvalue>\r
+      <param-tag>spirit:hwParameter</param-tag>\r
+    </core-param>\r
+    <core-param>\r
+      <param-name>Slot 10:</param-name>\r
+      <param-value>false</param-value>\r
+      <param-hdlname>APBSLOT10ENABLE</param-hdlname>\r
+      <param-hdlvalue>0</param-hdlvalue>\r
+      <param-tag>spirit:hwParameter</param-tag>\r
+    </core-param>\r
+    <core-param>\r
+      <param-name>Slot 11:</param-name>\r
+      <param-value>false</param-value>\r
+      <param-hdlname>APBSLOT11ENABLE</param-hdlname>\r
+      <param-hdlvalue>0</param-hdlvalue>\r
+      <param-tag>spirit:hwParameter</param-tag>\r
+    </core-param>\r
+    <core-param>\r
+      <param-name>Slot 12:</param-name>\r
+      <param-value>false</param-value>\r
+      <param-hdlname>APBSLOT12ENABLE</param-hdlname>\r
+      <param-hdlvalue>0</param-hdlvalue>\r
+      <param-tag>spirit:hwParameter</param-tag>\r
+    </core-param>\r
+    <core-param>\r
+      <param-name>Slot 13:</param-name>\r
+      <param-value>false</param-value>\r
+      <param-hdlname>APBSLOT13ENABLE</param-hdlname>\r
+      <param-hdlvalue>0</param-hdlvalue>\r
+      <param-tag>spirit:hwParameter</param-tag>\r
+    </core-param>\r
+    <core-param>\r
+      <param-name>Slot 14:</param-name>\r
+      <param-value>false</param-value>\r
+      <param-hdlname>APBSLOT14ENABLE</param-hdlname>\r
+      <param-hdlvalue>0</param-hdlvalue>\r
+      <param-tag>spirit:hwParameter</param-tag>\r
+    </core-param>\r
+    <core-param>\r
+      <param-name>Slot 15:</param-name>\r
+      <param-value>false</param-value>\r
+      <param-hdlname>APBSLOT15ENABLE</param-hdlname>\r
+      <param-hdlvalue>0</param-hdlvalue>\r
+      <param-tag>spirit:hwParameter</param-tag>\r
+    </core-param>\r
+    <core-param>\r
+      <param-name>Indirect Addressing:</param-name>\r
+      <param-value>Indirect address sourced from register(s) in slot 4 space</param-value>\r
+      <param-hdlname>IADDR_OPTION</param-hdlname>\r
+      <param-hdlvalue>6</param-hdlvalue>\r
+      <param-tag>spirit:hwParameter</param-tag>\r
+    </core-param>\r
+    <core-param>\r
+      <param-name>Number of address bits driven by master:</param-name>\r
+      <param-value>20</param-value>\r
+      <param-hdlname>MADDR_BITS</param-hdlname>\r
+      <param-hdlvalue>20</param-hdlvalue>\r
+      <param-tag>spirit:hwParameter</param-tag>\r
+    </core-param>\r
+    <core-param>\r
+      <param-name>Slot 0:</param-name>\r
+      <param-value>false</param-value>\r
+      <param-hdlname>SC_0</param-hdlname>\r
+      <param-hdlvalue>0</param-hdlvalue>\r
+      <param-tag>spirit:hwParameter</param-tag>\r
+    </core-param>\r
+    <core-param>\r
+      <param-name>Slot 1:</param-name>\r
+      <param-value>false</param-value>\r
+      <param-hdlname>SC_1</param-hdlname>\r
+      <param-hdlvalue>0</param-hdlvalue>\r
+      <param-tag>spirit:hwParameter</param-tag>\r
+    </core-param>\r
+    <core-param>\r
+      <param-name>Slot 2:</param-name>\r
+      <param-value>false</param-value>\r
+      <param-hdlname>SC_2</param-hdlname>\r
+      <param-hdlvalue>0</param-hdlvalue>\r
+      <param-tag>spirit:hwParameter</param-tag>\r
+    </core-param>\r
+    <core-param>\r
+      <param-name>Slot 3:</param-name>\r
+      <param-value>false</param-value>\r
+      <param-hdlname>SC_3</param-hdlname>\r
+      <param-hdlvalue>0</param-hdlvalue>\r
+      <param-tag>spirit:hwParameter</param-tag>\r
+    </core-param>\r
+    <core-param>\r
+      <param-name>Slot 4:</param-name>\r
+      <param-value>false</param-value>\r
+      <param-hdlname>SC_4</param-hdlname>\r
+      <param-hdlvalue>0</param-hdlvalue>\r
+      <param-tag>spirit:hwParameter</param-tag>\r
+    </core-param>\r
+    <core-param>\r
+      <param-name>Slot 5:</param-name>\r
+      <param-value>false</param-value>\r
+      <param-hdlname>SC_5</param-hdlname>\r
+      <param-hdlvalue>0</param-hdlvalue>\r
+      <param-tag>spirit:hwParameter</param-tag>\r
+    </core-param>\r
+    <core-param>\r
+      <param-name>Slot 6:</param-name>\r
+      <param-value>false</param-value>\r
+      <param-hdlname>SC_6</param-hdlname>\r
+      <param-hdlvalue>0</param-hdlvalue>\r
+      <param-tag>spirit:hwParameter</param-tag>\r
+    </core-param>\r
+    <core-param>\r
+      <param-name>Slot 7:</param-name>\r
+      <param-value>false</param-value>\r
+      <param-hdlname>SC_7</param-hdlname>\r
+      <param-hdlvalue>0</param-hdlvalue>\r
+      <param-tag>spirit:hwParameter</param-tag>\r
+    </core-param>\r
+    <core-param>\r
+      <param-name>Slot 8:</param-name>\r
+      <param-value>false</param-value>\r
+      <param-hdlname>SC_8</param-hdlname>\r
+      <param-hdlvalue>0</param-hdlvalue>\r
+      <param-tag>spirit:hwParameter</param-tag>\r
+    </core-param>\r
+    <core-param>\r
+      <param-name>Slot 9:</param-name>\r
+      <param-value>false</param-value>\r
+      <param-hdlname>SC_9</param-hdlname>\r
+      <param-hdlvalue>0</param-hdlvalue>\r
+      <param-tag>spirit:hwParameter</param-tag>\r
+    </core-param>\r
+    <core-param>\r
+      <param-name>Slot 10:</param-name>\r
+      <param-value>false</param-value>\r
+      <param-hdlname>SC_10</param-hdlname>\r
+      <param-hdlvalue>0</param-hdlvalue>\r
+      <param-tag>spirit:hwParameter</param-tag>\r
+    </core-param>\r
+    <core-param>\r
+      <param-name>Slot 11:</param-name>\r
+      <param-value>false</param-value>\r
+      <param-hdlname>SC_11</param-hdlname>\r
+      <param-hdlvalue>0</param-hdlvalue>\r
+      <param-tag>spirit:hwParameter</param-tag>\r
+    </core-param>\r
+    <core-param>\r
+      <param-name>Slot 12:</param-name>\r
+      <param-value>false</param-value>\r
+      <param-hdlname>SC_12</param-hdlname>\r
+      <param-hdlvalue>0</param-hdlvalue>\r
+      <param-tag>spirit:hwParameter</param-tag>\r
+    </core-param>\r
+    <core-param>\r
+      <param-name>Slot 13:</param-name>\r
+      <param-value>false</param-value>\r
+      <param-hdlname>SC_13</param-hdlname>\r
+      <param-hdlvalue>0</param-hdlvalue>\r
+      <param-tag>spirit:hwParameter</param-tag>\r
+    </core-param>\r
+    <core-param>\r
+      <param-name>Slot 14:</param-name>\r
+      <param-value>false</param-value>\r
+      <param-hdlname>SC_14</param-hdlname>\r
+      <param-hdlvalue>0</param-hdlvalue>\r
+      <param-tag>spirit:hwParameter</param-tag>\r
+    </core-param>\r
+    <core-param>\r
+      <param-name>Slot 15:</param-name>\r
+      <param-value>false</param-value>\r
+      <param-hdlname>SC_15</param-hdlname>\r
+      <param-hdlvalue>0</param-hdlvalue>\r
+      <param-tag>spirit:hwParameter</param-tag>\r
+    </core-param>\r
+    <core-param>\r
+      <param-name>Position in slave address of upper 4 bits of master address:</param-name>\r
+      <param-value>[19:16] (Ignored if master address width >= 24 bits)</param-value>\r
+      <param-hdlname>UPR_NIBBLE_POSN</param-hdlname>\r
+      <param-hdlvalue>4</param-hdlvalue>\r
+      <param-tag>spirit:hwParameter</param-tag>\r
+    </core-param>\r
+    <core-name>CoreAPB3_0</core-name>\r
+  </core>\r
+  <core type="ComponentModule">\r
+    <core-type>ComponentModule</core-type>\r
+    <core-exttype>SmartDesign</core-exttype>\r
+    <core-location>D:/Actelprj/SF2_DEVKIT_DEMO/component/work/DEV_KIT_DEMO</core-location>\r
+    <core-name>DEV_KIT_DEMO_0</core-name>\r
+  </core>\r
+  <core type="SpiritModule">\r
+    <core-exttype>IP</core-exttype>\r
+    <core-type>SpiritModule</core-type>\r
+    <core-vendor>Actel</core-vendor>\r
+    <core-lib>SgCore</core-lib>\r
+    <core-intname>SERDES_IF</core-intname>\r
+    <core-ver>1.0.100</core-ver>\r
+    <core-desc>SmartFusion2 High Speed Serial Interface</core-desc>\r
+    <core-name>SERDES_IF_0</core-name>\r
+  </core>\r
+  <firmware_core type="FirmWareModule">\r
+    <core-exttype>IP</core-exttype>\r
+    <core-type>FirmWareModule</core-type>\r
+    <core-vendor>Actel</core-vendor>\r
+    <core-lib>Firmware</core-lib>\r
+    <core-intname>SmartFusion2_CMSIS</core-intname>\r
+    <core-ver>2.1.101</core-ver>\r
+    <core-desc>SmartFusion2 Cortex Microcontroller Software Interface Standard (CMSIS).\r
+\r
+The firmware package provides:\r
+- Cortex-M3 startup code.\r
+- CMSIS standard naming for exception and interrupt handlers.\r
+- CMSIS standard functions for controlling the Cortex-M3 Nested Vectored Interrupt Controller (NVIC).\r
+- peripherals registers description.\r
+- hardware abstraction layer (HAL) for FPGA fabric soft-IP peripherirals.\r
+\r
+These files are required by the SmartFusion2 bare metal peripheral drivers to build correctly.\r
+</core-desc>\r
+    <core-param>\r
+      <param-name>Software Tool Chain:</param-name>\r
+      <param-value>SoftConsole</param-value>\r
+      <param-hdlname>ToolChain</param-hdlname>\r
+      <param-hdlvalue>0</param-hdlvalue>\r
+      <param-tag>actel-cc:variantParameter</param-tag>\r
+    </core-param>\r
+    <core-name>SmartFusion2_CMSIS_0</core-name>\r
+  </firmware_core>\r
+  <firmware_core type="FirmWareModule">\r
+    <core-exttype>IP</core-exttype>\r
+    <core-type>FirmWareModule</core-type>\r
+    <core-vendor>Actel</core-vendor>\r
+    <core-lib>Firmware</core-lib>\r
+    <core-intname>SmartFusion2_MSS_GPIO_Driver</core-intname>\r
+    <core-ver>2.0.101</core-ver>\r
+    <core-desc>SmartFusion2 microcontroller subsystem (MSS) GPIO bare metal software driver.\r
+\r
+This driver requires the SmartFusion2 CMSIS Hardware Abstraction Layer to build correctly.</core-desc>\r
+    <core-name>SmartFusion2_MSS_GPIO_Driver_0</core-name>\r
+  </firmware_core>\r
+  <firmware_core type="FirmWareModule">\r
+    <core-exttype>IP</core-exttype>\r
+    <core-type>FirmWareModule</core-type>\r
+    <core-vendor>Actel</core-vendor>\r
+    <core-lib>Firmware</core-lib>\r
+    <core-intname>SmartFusion2_MSS_HPDMA_Driver</core-intname>\r
+    <core-ver>2.0.101</core-ver>\r
+    <core-desc>SmartFusion2 microcontroller subsystem (MSS) High Performance DMA bare metal software driver.\r
+\r
+This driver requires the SmartFusion2 CMSIS Hardware Abstraction Layer to build correctly.</core-desc>\r
+    <core-name>SmartFusion2_MSS_HPDMA_Driver_0</core-name>\r
+  </firmware_core>\r
+  <firmware_core type="FirmWareModule">\r
+    <core-exttype>IP</core-exttype>\r
+    <core-type>FirmWareModule</core-type>\r
+    <core-vendor>Actel</core-vendor>\r
+    <core-lib>Firmware</core-lib>\r
+    <core-intname>SmartFusion2_MSS_I2C_Driver</core-intname>\r
+    <core-ver>2.0.100</core-ver>\r
+    <core-desc>SmartFusion2 microcontroller subsystem (MSS) I2C bare metal software driver.\r
+\r
+This driver requires the SmartFusion2 CMSIS Hardware Abstraction Layer to build correctly.</core-desc>\r
+    <core-name>SmartFusion2_MSS_I2C_Driver_0</core-name>\r
+  </firmware_core>\r
+  <firmware_core type="FirmWareModule">\r
+    <core-exttype>IP</core-exttype>\r
+    <core-type>FirmWareModule</core-type>\r
+    <core-vendor>Actel</core-vendor>\r
+    <core-lib>Firmware</core-lib>\r
+    <core-intname>SmartFusion2_MSS_I2C_Driver</core-intname>\r
+    <core-ver>2.0.100</core-ver>\r
+    <core-desc>SmartFusion2 microcontroller subsystem (MSS) I2C bare metal software driver.\r
+\r
+This driver requires the SmartFusion2 CMSIS Hardware Abstraction Layer to build correctly.</core-desc>\r
+    <core-name>SmartFusion2_MSS_I2C_Driver_1</core-name>\r
+  </firmware_core>\r
+  <firmware_core type="FirmWareModule">\r
+    <core-exttype>IP</core-exttype>\r
+    <core-type>FirmWareModule</core-type>\r
+    <core-vendor>Actel</core-vendor>\r
+    <core-lib>Firmware</core-lib>\r
+    <core-intname>SmartFusion2_MSS_MMUART_Driver</core-intname>\r
+    <core-ver>2.0.101</core-ver>\r
+    <core-desc>SmartFusion2 microcontroller subsystem (MSS) MMUART bare metal software driver.\r
+\r
+This driver requires the SmartFusion2 CMSIS Hardware Abstraction Layer to build correctly.</core-desc>\r
+    <core-name>SmartFusion2_MSS_MMUART_Driver_0</core-name>\r
+  </firmware_core>\r
+  <firmware_core type="FirmWareModule">\r
+    <core-exttype>IP</core-exttype>\r
+    <core-type>FirmWareModule</core-type>\r
+    <core-vendor>Actel</core-vendor>\r
+    <core-lib>Firmware</core-lib>\r
+    <core-intname>SmartFusion2_MSS_PDMA_Driver</core-intname>\r
+    <core-ver>2.0.102</core-ver>\r
+    <core-desc>SmartFusion2 microcontroller subsystem (MSS) Peripheral DMA bare metal software driver.\r
+\r
+This driver requires the SmartFusion2 CMSIS Hardware Abstraction Layer to build correctly.</core-desc>\r
+    <core-name>SmartFusion2_MSS_PDMA_Driver_0</core-name>\r
+  </firmware_core>\r
+  <firmware_core type="FirmWareModule">\r
+    <core-exttype>IP</core-exttype>\r
+    <core-type>FirmWareModule</core-type>\r
+    <core-vendor>Actel</core-vendor>\r
+    <core-lib>Firmware</core-lib>\r
+    <core-intname>SmartFusion2_MSS_RTC_Driver</core-intname>\r
+    <core-ver>2.0.101</core-ver>\r
+    <core-desc>SmartFusion2 microcontroller subsystem (MSS) RTC bare metal software driver.\r
+\r
+This driver requires the SmartFusion2 CMSIS Hardware Abstraction Layer to build correctly.</core-desc>\r
+    <core-name>SmartFusion2_MSS_RTC_Driver_0</core-name>\r
+  </firmware_core>\r
+  <firmware_core type="FirmWareModule">\r
+    <core-exttype>IP</core-exttype>\r
+    <core-type>FirmWareModule</core-type>\r
+    <core-vendor>Actel</core-vendor>\r
+    <core-lib>Firmware</core-lib>\r
+    <core-intname>SmartFusion2_MSS_SPI_Driver</core-intname>\r
+    <core-ver>2.0.103</core-ver>\r
+    <core-desc>SmartFusion2 microcontroller subsystem (MSS) SPI bare metal software driver.\r
+\r
+This driver requires the SmartFusion2 CMSIS Hardware Abstraction Layer to build correctly.</core-desc>\r
+    <core-name>SmartFusion2_MSS_SPI_Driver_0</core-name>\r
+  </firmware_core>\r
+  <firmware_core type="FirmWareModule">\r
+    <core-exttype>IP</core-exttype>\r
+    <core-type>FirmWareModule</core-type>\r
+    <core-vendor>Actel</core-vendor>\r
+    <core-lib>Firmware</core-lib>\r
+    <core-intname>SmartFusion2_MSS_System_Services_Driver</core-intname>\r
+    <core-ver>2.0.103</core-ver>\r
+    <core-desc>SmartFusion2 microsontroller subsystem (MSS) System Services software driver.\r
+\r
+This driver requires the SmartFusion2 CMSIS Hardware Abstraction Layer to build correctly.</core-desc>\r
+    <core-name>SmartFusion2_MSS_System_Services_Driver_0</core-name>\r
+  </firmware_core>\r
+  <firmware_core type="FirmWareModule">\r
+    <core-exttype>IP</core-exttype>\r
+    <core-type>FirmWareModule</core-type>\r
+    <core-vendor>Actel</core-vendor>\r
+    <core-lib>Firmware</core-lib>\r
+    <core-intname>SmartFusion2_MSS_Timer_Driver</core-intname>\r
+    <core-ver>2.0.101</core-ver>\r
+    <core-desc>SmartFusion2 microcontroller subsystem (MSS) Timer bare metal software driver.\r
+\r
+This driver requires the SmartFusion2 CMSIS Hardware Abstraction Layer to build correctly.</core-desc>\r
+    <core-name>SmartFusion2_MSS_Timer_Driver_0</core-name>\r
+  </firmware_core>\r
+  <firmware_core type="FirmWareModule">\r
+    <core-exttype>IP</core-exttype>\r
+    <core-type>FirmWareModule</core-type>\r
+    <core-vendor>Actel</core-vendor>\r
+    <core-lib>Firmware</core-lib>\r
+    <core-intname>SmartFusion2_MSS_USB_Driver</core-intname>\r
+    <core-ver>2.1.100</core-ver>\r
+    <core-desc>SmartFusion2 microcontroller subsystem (MSS) USB bare metal software driver.\r
+\r
+The firmware package provides:\r
+- MSS USB Device Core Driver \r
+- USB MSC Device Class driver with example project.\r
+- USB CDC Device Class driver with example project.\r
+- USB HID Device Class driver with example project.\r
+\r
+\r
+This driver requires the SmartFusion2 CMSIS Hardware Abstraction Layer to build correctly.</core-desc>\r
+    <core-name>SmartFusion2_MSS_USB_Driver_0</core-name>\r
+  </firmware_core>\r
+  <firmware_core type="FirmWareModule">\r
+    <core-exttype>IP</core-exttype>\r
+    <core-type>FirmWareModule</core-type>\r
+    <core-vendor>Actel</core-vendor>\r
+    <core-lib>Firmware</core-lib>\r
+    <core-intname>SmartFusion2_MSS_Watchdog_Driver</core-intname>\r
+    <core-ver>2.0.102</core-ver>\r
+    <core-desc>SmartFusion2 microcontroller subsystem (MSS) Watchdog bare metal software driver.\r
+\r
+This driver requires the SmartFusion2 CMSIS Hardware Abstraction Layer to build correctly.</core-desc>\r
+    <core-name>SmartFusion2_MSS_Watchdog_Driver_0</core-name>\r
+  </firmware_core>\r
+  <memorysystem>\r
+    <title>Memory Map for DEV_KIT_DEMO_top</title>\r
+    <description>The project contains the following subsystems:</description>\r
+    <subsystems>\r
+      <subsystem>\r
+        <name>CM3</name>\r
+        <master>CM3</master>\r
+        <master>FABRIC2MSSFIC2</master>\r
+        <master>FABRICTOMSSFIC0_APB_BRIDGE</master>\r
+        <addressNames>\r
+          <count>1</count>\r
+          <name>\r
+          </name>\r
+        </addressNames>\r
+        <slave>\r
+          <name>FIC32_REGION5</name>\r
+          <fullPinName>\r
+          </fullPinName>\r
+          <remapAddress>0xF0000000</remapAddress>\r
+          <fullAddressSpace>0xF0000000 - 0xFFFFFFFF</fullAddressSpace>\r
+          <range>0x10000000</range>\r
+        </slave>\r
+        <slave>\r
+          <name>DDR_0_SPACE_3</name>\r
+          <fullPinName>\r
+          </fullPinName>\r
+          <remapAddress>0xD0000000</remapAddress>\r
+          <fullAddressSpace>0xD0000000 - 0xDFFFFFFF</fullAddressSpace>\r
+          <range>0x10000000</range>\r
+        </slave>\r
+        <slave>\r
+          <name>DDR_0_SPACE_2</name>\r
+          <fullPinName>\r
+          </fullPinName>\r
+          <remapAddress>0xC0000000</remapAddress>\r
+          <fullAddressSpace>0xC0000000 - 0xCFFFFFFF</fullAddressSpace>\r
+          <range>0x10000000</range>\r
+        </slave>\r
+        <slave>\r
+          <name>DDR_0_SPACE_1</name>\r
+          <fullPinName>\r
+          </fullPinName>\r
+          <remapAddress>0xB0000000</remapAddress>\r
+          <fullAddressSpace>0xB0000000 - 0xBFFFFFFF</fullAddressSpace>\r
+          <range>0x10000000</range>\r
+        </slave>\r
+        <slave>\r
+          <name>DDR_0_SPACE_0</name>\r
+          <fullPinName>\r
+          </fullPinName>\r
+          <remapAddress>0xA0000000</remapAddress>\r
+          <fullAddressSpace>0xA0000000 - 0xAFFFFFFF</fullAddressSpace>\r
+          <range>0x10000000</range>\r
+        </slave>\r
+        <slave>\r
+          <name>FIC32_REGION4</name>\r
+          <fullPinName>\r
+          </fullPinName>\r
+          <remapAddress>0x90000000</remapAddress>\r
+          <fullAddressSpace>0x90000000 - 0x9FFFFFFF</fullAddressSpace>\r
+          <range>0x10000000</range>\r
+        </slave>\r
+        <slave>\r
+          <name>FIC32_REGION3</name>\r
+          <fullPinName>\r
+          </fullPinName>\r
+          <remapAddress>0x80000000</remapAddress>\r
+          <fullAddressSpace>0x80000000 - 0x8FFFFFFF</fullAddressSpace>\r
+          <range>0x10000000</range>\r
+        </slave>\r
+        <slave>\r
+          <name>AHB2ENVM1_REGISTERS</name>\r
+          <fullPinName>\r
+          </fullPinName>\r
+          <remapAddress>0x600C0000</remapAddress>\r
+          <fullAddressSpace>0x600C0000 - 0x600FFFFF</fullAddressSpace>\r
+          <range>0x00040000</range>\r
+        </slave>\r
+        <slave>\r
+          <name>AHB2ENVM0_REGISTERS</name>\r
+          <fullPinName>\r
+          </fullPinName>\r
+          <remapAddress>0x60080000</remapAddress>\r
+          <fullAddressSpace>0x60080000 - 0x600BFFFF</fullAddressSpace>\r
+          <range>0x00040000</range>\r
+        </slave>\r
+        <slave>\r
+          <name>ENVM1</name>\r
+          <fullPinName>\r
+          </fullPinName>\r
+          <remapAddress>0x60040000</remapAddress>\r
+          <fullAddressSpace>0x60040000 - 0x6007FFFF</fullAddressSpace>\r
+          <range>0x00040000</range>\r
+        </slave>\r
+        <slave>\r
+          <name>ENVM0</name>\r
+          <fullPinName>\r
+          </fullPinName>\r
+          <remapAddress>0x60000000</remapAddress>\r
+          <fullAddressSpace>0x60000000 - 0x6003FFFF</fullAddressSpace>\r
+          <range>0x00040000</range>\r
+        </slave>\r
+        <slave>\r
+          <name>FIC32_REGION1</name>\r
+          <fullPinName>\r
+          </fullPinName>\r
+          <remapAddress>0x50000000</remapAddress>\r
+          <fullAddressSpace>0x50000000 - 0x5FFFFFFF</fullAddressSpace>\r
+          <range>0x10000000</range>\r
+        </slave>\r
+        <slave>\r
+          <name>CACHE_BACKDOOR</name>\r
+          <fullPinName>\r
+          </fullPinName>\r
+          <remapAddress>0x40400000</remapAddress>\r
+          <fullAddressSpace>0x40400000 - 0x4040FFFF</fullAddressSpace>\r
+          <range>0x00010000</range>\r
+        </slave>\r
+        <slave>\r
+          <name>USB</name>\r
+          <fullPinName>\r
+          </fullPinName>\r
+          <remapAddress>0x40043000</remapAddress>\r
+          <fullAddressSpace>0x40043000 - 0x40043FFF</fullAddressSpace>\r
+          <range>0x00001000</range>\r
+        </slave>\r
+        <slave>\r
+          <name>SYSREG</name>\r
+          <fullPinName>\r
+          </fullPinName>\r
+          <remapAddress>0x40038000</remapAddress>\r
+          <fullAddressSpace>0x40038000 - 0x40038FFF</fullAddressSpace>\r
+          <range>0x00001000</range>\r
+          <memoryMap>\r
+            <name>RegisterMap</name>\r
+            <addressBlock>\r
+              <baseAddress>0x0</baseAddress>\r
+              <range format="long">0x1000</range>\r
+              <width format="long" id="width">32</width>\r
+              <register>\r
+                <name>ESRAM_CONFIG</name>\r
+                <addressOffset>0x0</addressOffset>\r
+                <absoluteAddress>0x40038000</absoluteAddress>\r
+                <size>32</size>\r
+                <access>R/W</access>\r
+                <resetValue>0x0</resetValue>\r
+                <field>\r
+                  <name>F2_ESRAMSIZE</name>\r
+                  <bitNumber>4:3</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>F2_TESTESRAM1REMAP_SYNC</name>\r
+                  <bitNumber>2</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>F2_TESTREMAPENABLE_SYNC</name>\r
+                  <bitNumber>1</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>COM_ESRAMFWREMAP</name>\r
+                  <bitNumber>0</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+              </register>\r
+              <register>\r
+                <name>ENVM_CONFIG</name>\r
+                <addressOffset>0x4</addressOffset>\r
+                <absoluteAddress>0x40038004</absoluteAddress>\r
+                <size>32</size>\r
+                <access>R/W</access>\r
+                <resetValue>0x0</resetValue>\r
+                <field>\r
+                  <name>ENVM_SIX_CYCLE</name>\r
+                  <bitNumber>7</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>ENVM_PIPE_BYPASS</name>\r
+                  <bitNumber>6</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>F2_ENVMPOWEREDDOWN</name>\r
+                  <bitNumber>5</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>COM_ENVMREMAPSIZE</name>\r
+                  <bitNumber>4:0</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+              </register>\r
+              <register>\r
+                <name>ENVM_REMAP_BASE</name>\r
+                <addressOffset>0x8</addressOffset>\r
+                <absoluteAddress>0x40038008</absoluteAddress>\r
+                <size>32</size>\r
+                <access>R/W</access>\r
+                <resetValue>0x0</resetValue>\r
+                <field>\r
+                  <name>COM_ENVMREMAPBASE</name>\r
+                  <bitNumber>19:0</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+              </register>\r
+              <register>\r
+                <name>ENVM_FAB_REMAP</name>\r
+                <addressOffset>0xC</addressOffset>\r
+                <absoluteAddress>0x4003800C</absoluteAddress>\r
+                <size>32</size>\r
+                <access>R/W</access>\r
+                <resetValue>0x0</resetValue>\r
+                <field>\r
+                  <name>COM_ENVMFABREMAPBASE</name>\r
+                  <bitNumber>19:0</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+              </register>\r
+              <register>\r
+                <name>FAB_PROT_SIZE</name>\r
+                <addressOffset>0x10</addressOffset>\r
+                <absoluteAddress>0x40038010</absoluteAddress>\r
+                <size>32</size>\r
+                <access>R/W</access>\r
+                <resetValue>0x0</resetValue>\r
+                <field>\r
+                  <name>COM_PROTREGIONSIZE</name>\r
+                  <bitNumber>4:0</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+              </register>\r
+              <register>\r
+                <name>FAB_PROT_BASE</name>\r
+                <addressOffset>0x14</addressOffset>\r
+                <absoluteAddress>0x40038014</absoluteAddress>\r
+                <size>32</size>\r
+                <access>R/W</access>\r
+                <resetValue>0x0</resetValue>\r
+                <field>\r
+                  <name>COM_PROTREGIONBASE</name>\r
+                  <bitNumber>31:0</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+              </register>\r
+              <register>\r
+                <name>MATRIX_CONFIG</name>\r
+                <addressOffset>0x18</addressOffset>\r
+                <absoluteAddress>0x40038018</absoluteAddress>\r
+                <size>32</size>\r
+                <access>R/W</access>\r
+                <resetValue>0x0</resetValue>\r
+                <field>\r
+                  <name>COM_WEIGHTEDMODE</name>\r
+                  <bitNumber>3</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>COM_MASTERENABLE</name>\r
+                  <bitNumber>2:0</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+              </register>\r
+              <register>\r
+                <name>DSS_STATUS</name>\r
+                <addressOffset>0x1C</addressOffset>\r
+                <absoluteAddress>0x4003801C</absoluteAddress>\r
+                <size>32</size>\r
+                <access>R/W</access>\r
+                <resetValue>0x0</resetValue>\r
+                <field>\r
+                  <name>PLLLOCKLOSTINT</name>\r
+                  <bitNumber>10</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>PLLLOCKINT</name>\r
+                  <bitNumber>9</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>COM_ERRORSTATUS</name>\r
+                  <bitNumber>8:4</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>BROWNOUT3_3VINT</name>\r
+                  <bitNumber>3</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>BROWNOUT1_5VINT</name>\r
+                  <bitNumber>2</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>WDOGTIMEOUTEVENT</name>\r
+                  <bitNumber>1</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>RTCMATCHEVENT</name>\r
+                  <bitNumber>0</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+              </register>\r
+              <register>\r
+                <name>CLR_DSS_STATUS</name>\r
+                <addressOffset>0x20</addressOffset>\r
+                <absoluteAddress>0x40038020</absoluteAddress>\r
+                <size>32</size>\r
+                <access>R/W</access>\r
+                <resetValue>0x0</resetValue>\r
+                <field>\r
+                  <name>CLRPLLLOCKLOSTINT</name>\r
+                  <bitNumber>10</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>CLRPLLLOCKINT</name>\r
+                  <bitNumber>9</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>COM_CLEARSTATUS</name>\r
+                  <bitNumber>8:4</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>CLRBROWNOUT3_3VINT</name>\r
+                  <bitNumber>3</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>CLRBROWNOUT1_5VINT</name>\r
+                  <bitNumber>2</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>CLRWDOGTIMEOUTEVENT</name>\r
+                  <bitNumber>1</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>CLRRTCMATCHEVENT</name>\r
+                  <bitNumber>0</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+              </register>\r
+              <register>\r
+                <name>FROM_CONFIG</name>\r
+                <addressOffset>0x24</addressOffset>\r
+                <absoluteAddress>0x40038024</absoluteAddress>\r
+                <size>32</size>\r
+                <access>R/W</access>\r
+                <resetValue>0x0</resetValue>\r
+                <field>\r
+                  <name>SYS_TOPT</name>\r
+                  <bitNumber>3:0</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+              </register>\r
+              <register>\r
+                <name>IAP_CONFIG</name>\r
+                <addressOffset>0x28</addressOffset>\r
+                <absoluteAddress>0x40038028</absoluteAddress>\r
+                <size>32</size>\r
+                <access>R/W</access>\r
+                <resetValue>0x0</resetValue>\r
+                <field>\r
+                  <name>SYS_FCFG</name>\r
+                  <bitNumber>2:0</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+              </register>\r
+              <register>\r
+                <name>SOFT_INTERRUPT</name>\r
+                <addressOffset>0x2C</addressOffset>\r
+                <absoluteAddress>0x4003802C</absoluteAddress>\r
+                <size>32</size>\r
+                <access>R/W</access>\r
+                <resetValue>0x0</resetValue>\r
+                <field>\r
+                  <name>SOFTINTERRUPT</name>\r
+                  <bitNumber>0</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+              </register>\r
+              <register>\r
+                <name>SOFT_RESET</name>\r
+                <addressOffset>0x30</addressOffset>\r
+                <absoluteAddress>0x40038030</absoluteAddress>\r
+                <size>32</size>\r
+                <access>R/W</access>\r
+                <resetValue>0x0</resetValue>\r
+                <field>\r
+                  <name>PADRESETENABLE</name>\r
+                  <bitNumber>19</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>USERRESETACTIVE</name>\r
+                  <bitNumber>18</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>FPGA_SOFTRESET</name>\r
+                  <bitNumber>17</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>EXT_SOFTRESET</name>\r
+                  <bitNumber>16</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>IAP_SOFTRESET</name>\r
+                  <bitNumber>15</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>GPIO_SOFTRESET</name>\r
+                  <bitNumber>14</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>ACE_SOFTRESET</name>\r
+                  <bitNumber>13</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>I2C1_SOFTRESET</name>\r
+                  <bitNumber>12</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>I2C0_SOFTRESET</name>\r
+                  <bitNumber>11</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>SPI1_SOFTRESET</name>\r
+                  <bitNumber>10</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>SPI0_SOFTRESET</name>\r
+                  <bitNumber>9</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>UART1_SOFTRESET</name>\r
+                  <bitNumber>8</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>UART0_SOFTRESET</name>\r
+                  <bitNumber>7</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>TIMER_SOFTRESET</name>\r
+                  <bitNumber>6</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>PDMA_SOFTRESET</name>\r
+                  <bitNumber>5</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>MAC_SOFTRESET</name>\r
+                  <bitNumber>4</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>EMC_SOFTRESET</name>\r
+                  <bitNumber>3</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>ESRAM1_SOFTRESET</name>\r
+                  <bitNumber>2</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>ESRAM0_SOFTRESET</name>\r
+                  <bitNumber>1</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>ENVM_SOFTRESET</name>\r
+                  <bitNumber>0</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+              </register>\r
+              <register>\r
+                <name>DEVICE_STATUS</name>\r
+                <addressOffset>0x34</addressOffset>\r
+                <absoluteAddress>0x40038034</absoluteAddress>\r
+                <size>32</size>\r
+                <access>R/W</access>\r
+                <resetValue>0x0</resetValue>\r
+                <field>\r
+                  <name>FPGAGOOD_SYNC</name>\r
+                  <bitNumber>6</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>FPGAPROGRAMMING_SYNC</name>\r
+                  <bitNumber>5</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>F2_PC_ACCESS_SYNC</name>\r
+                  <bitNumber>4:3</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>VCCIBGOOD_SYNC</name>\r
+                  <bitNumber>2</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>BROWNOUT3_3V_SYNCN</name>\r
+                  <bitNumber>1</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>BROWNOUT1_5V_SYNCN</name>\r
+                  <bitNumber>0</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+              </register>\r
+              <register>\r
+                <name>SYSTICK_CONFIG</name>\r
+                <addressOffset>0x38</addressOffset>\r
+                <absoluteAddress>0x40038038</absoluteAddress>\r
+                <size>32</size>\r
+                <access>R/W</access>\r
+                <resetValue>0x0</resetValue>\r
+                <field>\r
+                  <name>STCLK_DIVISOR</name>\r
+                  <bitNumber>29:28</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>STCALIB</name>\r
+                  <bitNumber>25:0</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+              </register>\r
+              <register>\r
+                <name>EM_MUX_CONFIG</name>\r
+                <addressOffset>0x3C</addressOffset>\r
+                <absoluteAddress>0x4003803C</absoluteAddress>\r
+                <size>32</size>\r
+                <access>R/W</access>\r
+                <resetValue>0x0</resetValue>\r
+                <field>\r
+                  <name>EM_SEL</name>\r
+                  <bitNumber>0</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+              </register>\r
+              <register>\r
+                <name>EM_CONFIG_0</name>\r
+                <addressOffset>0x40</addressOffset>\r
+                <absoluteAddress>0x40038040</absoluteAddress>\r
+                <size>32</size>\r
+                <access>R/W</access>\r
+                <resetValue>0x0</resetValue>\r
+                <field>\r
+                  <name>EM_CSFE0</name>\r
+                  <bitNumber>21</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>EM_WENBEN0</name>\r
+                  <bitNumber>20</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>EM_RWPOL0</name>\r
+                  <bitNumber>19</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>EM_PIPEWRN0</name>\r
+                  <bitNumber>18</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>EM_PIPERDN0</name>\r
+                  <bitNumber>17</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>EM_IDD0</name>\r
+                  <bitNumber>16:15</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>EM_WRITELAT0</name>\r
+                  <bitNumber>14:11</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>EM_RDLATREST0</name>\r
+                  <bitNumber>10:7</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>EM_RDLATFIRST0</name>\r
+                  <bitNumber>6:3</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>EM_PORTSIZE0</name>\r
+                  <bitNumber>2</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>EM_MEMTYPE0</name>\r
+                  <bitNumber>1:0</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+              </register>\r
+              <register>\r
+                <name>EM_CONFIG_1</name>\r
+                <addressOffset>0x44</addressOffset>\r
+                <absoluteAddress>0x40038044</absoluteAddress>\r
+                <size>32</size>\r
+                <access>R/W</access>\r
+                <resetValue>0x0</resetValue>\r
+                <field>\r
+                  <name>EM_CSFE1</name>\r
+                  <bitNumber>21</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>EM_WENBEN1</name>\r
+                  <bitNumber>20</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>EM_RWPOL1</name>\r
+                  <bitNumber>19</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>EM_PIPEWRN1</name>\r
+                  <bitNumber>18</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>EM_PIPERDN1</name>\r
+                  <bitNumber>17</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>EM_IDD1</name>\r
+                  <bitNumber>16:15</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>EM_WRITELAT1</name>\r
+                  <bitNumber>14:11</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>EM_RDLATREST1</name>\r
+                  <bitNumber>10:7</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>EM_RDLATFIRST1</name>\r
+                  <bitNumber>6:3</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>EM_PORTSIZE1</name>\r
+                  <bitNumber>2</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>EM_MEMTYPE1</name>\r
+                  <bitNumber>1:0</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+              </register>\r
+              <register>\r
+                <name>CLK_CTRL</name>\r
+                <addressOffset>0x48</addressOffset>\r
+                <absoluteAddress>0x40038048</absoluteAddress>\r
+                <size>32</size>\r
+                <access>R/W</access>\r
+                <resetValue>0x0</resetValue>\r
+                <field>\r
+                  <name>GLBDIVISOR</name>\r
+                  <bitNumber>13:12</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>RTCIF_ACMDIVISOR</name>\r
+                  <bitNumber>11:8</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>ACLKDIVISOR</name>\r
+                  <bitNumber>7:6</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>PCLK1DIVISOR</name>\r
+                  <bitNumber>5:4</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>PCLK0DIVISOR</name>\r
+                  <bitNumber>3:2</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>RMIICLKSEL</name>\r
+                  <bitNumber>1</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+              </register>\r
+              <register>\r
+                <name>CCC_DIV_CONFIG</name>\r
+                <addressOffset>0x4C</addressOffset>\r
+                <absoluteAddress>0x4003804C</absoluteAddress>\r
+                <size>32</size>\r
+                <access>R/W</access>\r
+                <resetValue>0x0</resetValue>\r
+                <field>\r
+                  <name>OCDIVRST</name>\r
+                  <bitNumber>22</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>OCDIVHALF</name>\r
+                  <bitNumber>21</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>OCDIV4</name>\r
+                  <bitNumber>20</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>OCDIV3</name>\r
+                  <bitNumber>19</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>OCDIV2</name>\r
+                  <bitNumber>18</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>OCDIV1</name>\r
+                  <bitNumber>17</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>OCDIV0</name>\r
+                  <bitNumber>16</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>OBDIVRST</name>\r
+                  <bitNumber>14</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>OBDIVHALF</name>\r
+                  <bitNumber>13</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>OBDIV4</name>\r
+                  <bitNumber>12</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>OBDIV3</name>\r
+                  <bitNumber>11</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>OBDIV2</name>\r
+                  <bitNumber>10</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>OBDIV1</name>\r
+                  <bitNumber>9</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>OBDIV0</name>\r
+                  <bitNumber>8</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>OADIVRST</name>\r
+                  <bitNumber>6</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>OADIVHALF</name>\r
+                  <bitNumber>5</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>OADIV4</name>\r
+                  <bitNumber>4</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>OADIV3</name>\r
+                  <bitNumber>3</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>OADIV2</name>\r
+                  <bitNumber>2</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>OADIV1</name>\r
+                  <bitNumber>1</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>OADIV0</name>\r
+                  <bitNumber>0</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+              </register>\r
+              <register>\r
+                <name>CCC_MUX_CONFIG</name>\r
+                <addressOffset>0x50</addressOffset>\r
+                <absoluteAddress>0x40038050</absoluteAddress>\r
+                <size>32</size>\r
+                <access>R/W</access>\r
+                <resetValue>0x0</resetValue>\r
+                <field>\r
+                  <name>MODE</name>\r
+                  <bitNumber>31:30</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>EN</name>\r
+                  <bitNumber>29</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>GLMUXCFG1</name>\r
+                  <bitNumber>27</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>GLMUXCFG0</name>\r
+                  <bitNumber>26</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>GLMUXSEL1</name>\r
+                  <bitNumber>25</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>GLMUXSEL0</name>\r
+                  <bitNumber>24</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>BYPASS_PLL3</name>\r
+                  <bitNumber>22</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>OCMUX2</name>\r
+                  <bitNumber>21</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>OCMUX1</name>\r
+                  <bitNumber>20</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>OCMUX0</name>\r
+                  <bitNumber>19</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>DYNCSEL</name>\r
+                  <bitNumber>18</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>RXCSEL</name>\r
+                  <bitNumber>17</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>STATCSEL</name>\r
+                  <bitNumber>16</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>BYPASS_PLL2</name>\r
+                  <bitNumber>14</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>OBMUX2</name>\r
+                  <bitNumber>13</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>OBMUX1</name>\r
+                  <bitNumber>12</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>OBMUX0</name>\r
+                  <bitNumber>11</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>DYNBSEL</name>\r
+                  <bitNumber>10</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>RXBSEL</name>\r
+                  <bitNumber>9</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>STATBSEL</name>\r
+                  <bitNumber>8</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>BYPASS_PLL1</name>\r
+                  <bitNumber>6</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>OAMUX2</name>\r
+                  <bitNumber>5</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>OAMUX1</name>\r
+                  <bitNumber>4</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>OAMUX0</name>\r
+                  <bitNumber>3</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>DYNASEL</name>\r
+                  <bitNumber>2</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>RXASEL</name>\r
+                  <bitNumber>1</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>STATASEL</name>\r
+                  <bitNumber>0</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+              </register>\r
+              <register>\r
+                <name>CCC_PLL_CONFIG</name>\r
+                <addressOffset>0x54</addressOffset>\r
+                <absoluteAddress>0x40038054</absoluteAddress>\r
+                <size>32</size>\r
+                <access>R/W</access>\r
+                <resetValue>0x0</resetValue>\r
+                <field>\r
+                  <name>POWERDOWN</name>\r
+                  <bitNumber>31</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>VCOSEL2</name>\r
+                  <bitNumber>24</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>VCOSEL1</name>\r
+                  <bitNumber>23</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>VCOSEL0</name>\r
+                  <bitNumber>22</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>XDLYSEL</name>\r
+                  <bitNumber>21</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>FBDLY4</name>\r
+                  <bitNumber>20</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>FBDLY3</name>\r
+                  <bitNumber>19</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>FBDLY2</name>\r
+                  <bitNumber>18</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>FBDLY1</name>\r
+                  <bitNumber>17</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>FBDLY0</name>\r
+                  <bitNumber>16</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>FBSEL1</name>\r
+                  <bitNumber>15</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>FBSEL0</name>\r
+                  <bitNumber>14</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>FBDIV6</name>\r
+                  <bitNumber>13</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>FBDIV5</name>\r
+                  <bitNumber>12</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>FBDIV4</name>\r
+                  <bitNumber>11</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>FBDIV3</name>\r
+                  <bitNumber>10</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>FBDIV2</name>\r
+                  <bitNumber>9</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>FBDIV1</name>\r
+                  <bitNumber>8</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>FBDIV0</name>\r
+                  <bitNumber>7</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>FINDIV6</name>\r
+                  <bitNumber>6</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>FINDIV5</name>\r
+                  <bitNumber>5</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>FINDIV4</name>\r
+                  <bitNumber>4</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>FINDIV3</name>\r
+                  <bitNumber>3</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>FINDIV2</name>\r
+                  <bitNumber>2</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>FINDIV1</name>\r
+                  <bitNumber>1</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>FINDIV0</name>\r
+                  <bitNumber>0</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+              </register>\r
+              <register>\r
+                <name>CCC_DLY_CONFIG</name>\r
+                <addressOffset>0x58</addressOffset>\r
+                <absoluteAddress>0x40038058</absoluteAddress>\r
+                <size>32</size>\r
+                <access>R/W</access>\r
+                <resetValue>0x0</resetValue>\r
+                <field>\r
+                  <name>DLYA14</name>\r
+                  <bitNumber>24</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>DLYA13</name>\r
+                  <bitNumber>23</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>DLYA12</name>\r
+                  <bitNumber>22</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>DLYA11</name>\r
+                  <bitNumber>21</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>DLYA10</name>\r
+                  <bitNumber>20</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>DLYA04</name>\r
+                  <bitNumber>19</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>DLYA03</name>\r
+                  <bitNumber>18</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>DLYA02</name>\r
+                  <bitNumber>17</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>DLYA01</name>\r
+                  <bitNumber>16</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>DLYA00</name>\r
+                  <bitNumber>15</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>DLYHCC4</name>\r
+                  <bitNumber>14</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>DLYHCC3</name>\r
+                  <bitNumber>13</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>DLYHCC2</name>\r
+                  <bitNumber>12</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>DLYHCC1</name>\r
+                  <bitNumber>11</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>DLYHCC0</name>\r
+                  <bitNumber>10</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>DLYHCB4</name>\r
+                  <bitNumber>9</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>DLYHCB3</name>\r
+                  <bitNumber>8</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>DLYHCB2</name>\r
+                  <bitNumber>7</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>DLYHCB1</name>\r
+                  <bitNumber>6</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>DLYHCB0</name>\r
+                  <bitNumber>5</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>DLYHCA4</name>\r
+                  <bitNumber>4</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>DLYHCA3</name>\r
+                  <bitNumber>3</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>DLYHCA2</name>\r
+                  <bitNumber>2</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>DLYHCA1</name>\r
+                  <bitNumber>1</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>DLYHCA0</name>\r
+                  <bitNumber>0</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+              </register>\r
+              <register>\r
+                <name>CCC_STATUS</name>\r
+                <addressOffset>0x5C</addressOffset>\r
+                <absoluteAddress>0x4003805C</absoluteAddress>\r
+                <size>32</size>\r
+                <access>R/W</access>\r
+                <resetValue>0x0</resetValue>\r
+                <field>\r
+                  <name>PLLLOCK_SYNC</name>\r
+                  <bitNumber>0</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+              </register>\r
+              <register>\r
+                <name>VTG_CTRL</name>\r
+                <addressOffset>0x64</addressOffset>\r
+                <absoluteAddress>0x40038064</absoluteAddress>\r
+                <size>32</size>\r
+                <access>R/W</access>\r
+                <resetValue>0x0</resetValue>\r
+                <field>\r
+                  <name>BGPSMENABLE</name>\r
+                  <bitNumber>4</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>VBATSELECT</name>\r
+                  <bitNumber>3</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>RTCIF_CLRPUBINT</name>\r
+                  <bitNumber>2</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>RTCIF_VRONENABLE</name>\r
+                  <bitNumber>1</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>RTCIF_FWVRON</name>\r
+                  <bitNumber>0</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+              </register>\r
+              <register>\r
+                <name>FAB_IF</name>\r
+                <addressOffset>0x6C</addressOffset>\r
+                <absoluteAddress>0x4003806C</absoluteAddress>\r
+                <size>32</size>\r
+                <access>R/W</access>\r
+                <resetValue>0x0</resetValue>\r
+                <field>\r
+                  <name>FABCALIBFAIL</name>\r
+                  <bitNumber>6</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>FABCALIBSTART</name>\r
+                  <bitNumber>5</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>F2_LARGE_CT_XS</name>\r
+                  <bitNumber>4</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>FAB_APB32</name>\r
+                  <bitNumber>3</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>FAB_AHBIF</name>\r
+                  <bitNumber>2</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>F2_AHBCAPABLE</name>\r
+                  <bitNumber>1</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>FAB_AHB_BYPASS</name>\r
+                  <bitNumber>0</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+              </register>\r
+              <register>\r
+                <name>APB_EXTN</name>\r
+                <addressOffset>0x70</addressOffset>\r
+                <absoluteAddress>0x40038070</absoluteAddress>\r
+                <size>32</size>\r
+                <access>R/W</access>\r
+                <resetValue>0x0</resetValue>\r
+                <field>\r
+                  <name>APB16_XHOLD</name>\r
+                  <bitNumber>15:0</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+              </register>\r
+              <register>\r
+                <name>LOOPBACK_CTRL</name>\r
+                <addressOffset>0x74</addressOffset>\r
+                <absoluteAddress>0x40038074</absoluteAddress>\r
+                <size>32</size>\r
+                <access>R/W</access>\r
+                <resetValue>0x0</resetValue>\r
+                <field>\r
+                  <name>DSS_EMACLOOPBACK</name>\r
+                  <bitNumber>4</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>DSS_GPIOLOOPBACK</name>\r
+                  <bitNumber>3</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>DSS_I2CLOOPBACK</name>\r
+                  <bitNumber>2</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>DSS_SPILOOPBACK</name>\r
+                  <bitNumber>1</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>DSS_UARTLOOPBACK</name>\r
+                  <bitNumber>0</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+              </register>\r
+              <register>\r
+                <name>IO_BANK_CONFIG</name>\r
+                <addressOffset>0x78</addressOffset>\r
+                <absoluteAddress>0x40038078</absoluteAddress>\r
+                <size>32</size>\r
+                <access>R/W</access>\r
+                <resetValue>0x0</resetValue>\r
+                <field>\r
+                  <name>BTWEST</name>\r
+                  <bitNumber>3:2</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>BTEAST</name>\r
+                  <bitNumber>1:0</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+              </register>\r
+              <register>\r
+                <name>GPIN_SRC_SEL</name>\r
+                <addressOffset>0x7C</addressOffset>\r
+                <absoluteAddress>0x4003807C</absoluteAddress>\r
+                <size>32</size>\r
+                <access>R/W</access>\r
+                <resetValue>0x0</resetValue>\r
+                <field>\r
+                  <name>DSS_GPINSOURCE[15]</name>\r
+                  <bitNumber>15</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>DSS_GPINSOURCE[14]</name>\r
+                  <bitNumber>14</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>DSS_GPINSOURCE[13]</name>\r
+                  <bitNumber>13</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>DSS_GPINSOURCE[12]</name>\r
+                  <bitNumber>12</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>DSS_GPINSOURCE[11]</name>\r
+                  <bitNumber>11</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>DSS_GPINSOURCE[10]</name>\r
+                  <bitNumber>10</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>DSS_GPINSOURCE[9]</name>\r
+                  <bitNumber>9</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>DSS_GPINSOURCE[8]</name>\r
+                  <bitNumber>8</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>DSS_GPINSOURCE[7]</name>\r
+                  <bitNumber>7</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>DSS_GPINSOURCE[6]</name>\r
+                  <bitNumber>6</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>DSS_GPINSOURCE[5]</name>\r
+                  <bitNumber>5</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>DSS_GPINSOURCE[4]</name>\r
+                  <bitNumber>4</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>DSS_GPINSOURCE[3]</name>\r
+                  <bitNumber>3</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>DSS_GPINSOURCE[2]</name>\r
+                  <bitNumber>2</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>DSS_GPINSOURCE[1]</name>\r
+                  <bitNumber>1</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+                <field>\r
+                  <name>DSS_GPINSOURCE[0]</name>\r
+                  <bitNumber>0</bitNumber>\r
+                  <access>R/W</access>\r
+                  <description>\r
+                  </description>\r
+                </field>\r
+              </register>\r
+            </addressBlock>\r
+          </memoryMap>\r
+        </slave>\r
+        <slave>\r
+          <name>CFGM</name>\r
+          <fullPinName>DEV_KIT_DEMO_MSS_0:MDDR_APB_SLAVE</fullPinName>\r
+          <remapAddress>0x40020800</remapAddress>\r
+          <fullAddressSpace>0x40020800 - 0x40020FFF</fullAddressSpace>\r
+          <range>0x800</range>\r
+        </slave>\r
+        <slave>\r
+          <name>CORESF2CONFIG_0</name>\r
+          <fullPinName>DEV_KIT_DEMO:SDIF1_APBmslave</fullPinName>\r
+          <remapAddress>0x4002C000</remapAddress>\r
+          <fullAddressSpace>0x4002C000 - 0x4002E3FF</fullAddressSpace>\r
+          <range>0x2400</range>\r
+        </slave>\r
+        <slave>\r
+          <name>RTC</name>\r
+          <fullPinName>\r
+          </fullPinName>\r
+          <remapAddress>0x40017000</remapAddress>\r
+          <fullAddressSpace>0x40017000 - 0x40017FFF</fullAddressSpace>\r
+          <range>0x1000</range>\r
+        </slave>\r
+        <slave>\r
+          <name>COMBLK</name>\r
+          <fullPinName>\r
+          </fullPinName>\r
+          <remapAddress>0x40016000</remapAddress>\r
+          <fullAddressSpace>0x40016000 - 0x40016FFF</fullAddressSpace>\r
+          <range>0x1000</range>\r
+        </slave>\r
+        <slave>\r
+          <name>HDMA</name>\r
+          <fullPinName>\r
+          </fullPinName>\r
+          <remapAddress>0x40014000</remapAddress>\r
+          <fullAddressSpace>0x40014000 - 0x40014FFF</fullAddressSpace>\r
+          <range>0x1000</range>\r
+        </slave>\r
+        <slave>\r
+          <name>GPIO</name>\r
+          <fullPinName>\r
+          </fullPinName>\r
+          <remapAddress>0x40013000</remapAddress>\r
+          <fullAddressSpace>0x40013000 - 0x40013FFF</fullAddressSpace>\r
+          <range>0x1000</range>\r
+        </slave>\r
+        <slave>\r
+          <name>I2C_1</name>\r
+          <fullPinName>\r
+          </fullPinName>\r
+          <remapAddress>0x40012000</remapAddress>\r
+          <fullAddressSpace>0x40012000 - 0x40012FFF</fullAddressSpace>\r
+          <range>0x1000</range>\r
+        </slave>\r
+        <slave>\r
+          <name>MMUART_1</name>\r
+          <fullPinName>\r
+          </fullPinName>\r
+          <remapAddress>0x40010000</remapAddress>\r
+          <fullAddressSpace>0x40010000 - 0x40010FFF</fullAddressSpace>\r
+          <range>0x1000</range>\r
+        </slave>\r
+        <slave>\r
+          <name>H2FINTERRUPT</name>\r
+          <fullPinName>\r
+          </fullPinName>\r
+          <remapAddress>0x40006000</remapAddress>\r
+          <fullAddressSpace>0x40006000 - 0x40006FFF</fullAddressSpace>\r
+          <range>0x1000</range>\r
+        </slave>\r
+        <slave>\r
+          <name>WATCHDOG</name>\r
+          <fullPinName>\r
+          </fullPinName>\r
+          <remapAddress>0x40005000</remapAddress>\r
+          <fullAddressSpace>0x40005000 - 0x40005FFF</fullAddressSpace>\r
+          <range>0x1000</range>\r
+        </slave>\r
+        <slave>\r
+          <name>TIMER</name>\r
+          <fullPinName>\r
+          </fullPinName>\r
+          <remapAddress>0x40004000</remapAddress>\r
+          <fullAddressSpace>0x40004000 - 0x40004FFF</fullAddressSpace>\r
+          <range>0x1000</range>\r
+        </slave>\r
+        <slave>\r
+          <name>PDMA</name>\r
+          <fullPinName>\r
+          </fullPinName>\r
+          <remapAddress>0x40003000</remapAddress>\r
+          <fullAddressSpace>0x40003000 - 0x40003FFF</fullAddressSpace>\r
+          <range>0x1000</range>\r
+        </slave>\r
+        <slave>\r
+          <name>I2C_0</name>\r
+          <fullPinName>\r
+          </fullPinName>\r
+          <remapAddress>0x40002000</remapAddress>\r
+          <fullAddressSpace>0x40002000 - 0x40002FFF</fullAddressSpace>\r
+          <range>0x1000</range>\r
+        </slave>\r
+        <slave>\r
+          <name>SPI_0</name>\r
+          <fullPinName>\r
+          </fullPinName>\r
+          <remapAddress>0x40001000</remapAddress>\r
+          <fullAddressSpace>0x40001000 - 0x40001FFF</fullAddressSpace>\r
+          <range>0x1000</range>\r
+        </slave>\r
+        <slave>\r
+          <name>RECYCLED_ESRAM1</name>\r
+          <fullPinName>\r
+          </fullPinName>\r
+          <remapAddress>0x20012000</remapAddress>\r
+          <fullAddressSpace>0x20012000 - 0x20013FFF</fullAddressSpace>\r
+          <range>0x00002000</range>\r
+        </slave>\r
+        <slave>\r
+          <name>RECYCLED_ESRAM0</name>\r
+          <fullPinName>\r
+          </fullPinName>\r
+          <remapAddress>0x20010000</remapAddress>\r
+          <fullAddressSpace>0x20010000 - 0x20011FFF</fullAddressSpace>\r
+          <range>0x00002000</range>\r
+        </slave>\r
+        <slave>\r
+          <name>ESRAM1</name>\r
+          <fullPinName>\r
+          </fullPinName>\r
+          <remapAddress>0x20008000</remapAddress>\r
+          <fullAddressSpace>0x20008000 - 0x2000FFFF</fullAddressSpace>\r
+          <range>0x00008000</range>\r
+        </slave>\r
+        <slave>\r
+          <name>ESRAM0</name>\r
+          <fullPinName>\r
+          </fullPinName>\r
+          <remapAddress>0x00080000</remapAddress>\r
+          <fullAddressSpace>0x00080000 - 0x00087FFF</fullAddressSpace>\r
+          <range>0x00008000</range>\r
+        </slave>\r
+      </subsystem>\r
+      <subsystem>\r
+        <name>COREABC_0</name>\r
+        <master>COREABC_0</master>\r
+        <addressNames>\r
+          <count>1</count>\r
+          <name>\r
+          </name>\r
+        </addressNames>\r
+        <slave>\r
+          <name>FIC32_0</name>\r
+          <fullPinName>DEV_KIT_DEMO_0:FIC_0_APB_SLAVE</fullPinName>\r
+          <remapAddress>0x00000000</remapAddress>\r
+          <fullAddressSpace>0x00000000 - 0x0000FFFF</fullAddressSpace>\r
+          <range>0x00010000</range>\r
+        </slave>\r
+      </subsystem>\r
+    </subsystems>\r
+  </memorysystem>\r
+</datasheet>\r
diff --git a/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/LiberoOutput/datasheet.xsl b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/LiberoOutput/datasheet.xsl
new file mode 100644 (file)
index 0000000..38ca42d
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/LiberoOutput/datasheet.xsl
@@ -0,0 +1,1077 @@
+<?xml version="1.0" encoding="iso-8859-1" ?>\r
+\r
+<xsl:stylesheet version="1.0" xmlns:xsl="http://www.w3.org/1999/XSL/Transform">\r
+\r
+    <xsl:template match="datasheet">\r
+        <html>\r
+            <head>\r
+                <xsl:call-template name="css"/>\r
+            </head>\r
+            <body>\r
+                <a name="top"/>\r
+                <div>\r
+                    <xsl:apply-templates select="header"/>\r
+                </div>\r
+                <div class="dsheet">\r
+                    <div>\r
+                        <xsl:apply-templates select="project-settings"/>\r
+                    </div>\r
+                    <div>\r
+                        <div class="header">Table of Contents</div>\r
+                        <div class="content" >\r
+                            <a href="#generated_files">Generated Files</a>\r
+                            <br/>\r
+                            <a href="#ios">IO's</a>\r
+                            <br/>\r
+                            <a href="#cores">Hardware Instances</a>\r
+                            <br/>\r
+                            <a href="#firmware_cores">Firmware</a>\r
+                            <br/>\r
+                            <a href="#memmap">Memory Map</a>\r
+                            <!-- <a href="{header}_MemoryMap.xml" >Memory Map</a> -->\r
+                        </div>\r
+                    </div>\r
+\r
+                    <!-- ======= Generated File's ======= -->\r
+                    <div>\r
+                        <p>\r
+                            <a name="generated_files"/>\r
+                            <div class="header">Generated Files</div>\r
+                        </p>\r
+                        <xsl:call-template name="generated_files"/>\r
+                    </div>\r
+\r
+                    <!-- ======= IO's ======= -->\r
+                    <div>\r
+                        <p>\r
+                            <a name="ios"/>\r
+                            <div class="header">IO's</div>\r
+                        </p>\r
+                        <xsl:call-template name="ios"/>\r
+                    </div>\r
+\r
+                    <br/>\r
+                    <!-- ===== CORES ====== -->\r
+                    <div>\r
+                        <a name="cores"/>\r
+                        <div class="header">\r
+                            Cores\r
+                        </div>\r
+                        <xsl:call-template name="cores"/>\r
+\r
+                    </div>\r
+\r
+                    <!-- ======= Firwmare ======= -->\r
+                    <div>\r
+                        <p>\r
+                            <a name="firmware_cores"/>\r
+                            <div class="header">Firmware</div>\r
+                        </p>\r
+                        <xsl:call-template name="firmware_cores"/>\r
+                    </div>\r
+\r
+                    <!-- ===== MEMORY MAP ====== -->\r
+                    <div>\r
+                        <a name="memmap"/>\r
+                        <div class="header">\r
+                            Memory Map\r
+                        </div>\r
+                        <xsl:apply-templates select="memorysystem"/>\r
+                    </div>\r
+\r
+                </div>\r
+            </body>\r
+        </html>\r
+    </xsl:template>\r
+\r
+\r
+\r
+    <xsl:template match="header">\r
+        <div class="title">\r
+            <h1>\r
+                Data Sheet: <xsl:value-of select="."/>\r
+            </h1>\r
+            <!-- ======= IO's ======= \r
+      <div class="copyright">\r
+        Copyright 2008 Actel Corporation\r
+      </div>\r
+         -->\r
+        </div>\r
+    </xsl:template>\r
+\r
+    <xsl:template match="project-settings">\r
+        <div class="header">Project Settings</div>\r
+\r
+        <div class="content">\r
+            <table border="0" cellspacing="4">\r
+                <tr>\r
+                    <td>\r
+                        <b>FAM: </b>\r
+                    </td>\r
+                    <td>\r
+                        <xsl:apply-templates select="fam"/>\r
+                    </td>\r
+                </tr>\r
+                <tr>\r
+                    <td>\r
+                        <b>Die: </b>\r
+                    </td>\r
+                    <td>\r
+                        <xsl:apply-templates select="die"/>\r
+                    </td>\r
+                </tr>\r
+                <tr>\r
+                    <td>\r
+                        <b>Package: </b>\r
+                    </td>\r
+                    <td>\r
+                        <xsl:apply-templates select="package"/>\r
+                    </td>\r
+                </tr>\r
+\r
+                <tr>\r
+                    <td>\r
+                        <b>Speed Grade: </b>\r
+                    </td>\r
+                    <td>\r
+                        <xsl:apply-templates select="speed-grade"/>\r
+                    </td>\r
+                </tr>\r
+\r
+                <tr>\r
+                    <td>\r
+                        <b>Voltage: </b>\r
+                    </td>\r
+                    <td>\r
+                        <xsl:apply-templates select="voltage"/>\r
+                    </td>\r
+                </tr>\r
+\r
+                <tr>\r
+                    <td>\r
+                        <b>HDL: </b>\r
+                    </td>\r
+                    <td>\r
+                        <xsl:apply-templates select="hdl-type"/>\r
+                    </td>\r
+                </tr>\r
+\r
+                <tr>\r
+                    <td>\r
+                        <b>Project Description: </b>\r
+                    </td>\r
+                    <td>\r
+                        <xsl:apply-templates select="project-description"/>\r
+                    </td>\r
+                </tr>\r
+\r
+                <tr>\r
+                    <td>\r
+                        <b>Location: </b>\r
+                    </td>\r
+                    <td>\r
+                        <xsl:apply-templates select="location"/>\r
+                    </td>\r
+                </tr>\r
+\r
+                <tr>\r
+                    <td>\r
+                        <b>State (Time): </b>\r
+                    </td>\r
+                    <td>\r
+                        <xsl:apply-templates select="state"/>\r
+                    </td>\r
+                </tr>\r
+            </table>\r
+        </div>\r
+        <br/>\r
+    </xsl:template>\r
+\r
+    <!-- /////////////////////////////////////////////////////////  -->\r
+\r
+    <xsl:template name="generated_files">\r
+        <div class="content">\r
+            <xsl:for-each select="fileset">\r
+                <b>File set:  </b>\r
+                <xsl:value-of select="name"/>\r
+                <br/>\r
+\r
+                <xsl:for-each select="file">\r
+                    <li>\r
+                        <xsl:value-of select="."/>\r
+                    </li>\r
+                </xsl:for-each>\r
+                <br/>\r
+            </xsl:for-each>\r
+        </div>\r
+        <xsl:call-template name="top-link"/>\r
+    </xsl:template>\r
+\r
+\r
+    <!-- /////////////////////////////////////////////////////////  -->\r
+\r
+    <xsl:template name="print-ios">\r
+        <td>\r
+            <xsl:apply-templates select="port-name"/>\r
+        </td>\r
+        <td>\r
+            <xsl:apply-templates select="direction"/>\r
+        </td>\r
+        <td>\r
+            <xsl:apply-templates select="pin-number"/>\r
+        </td>\r
+        <td>\r
+            <xsl:apply-templates select="io-standard"/>\r
+        </td>\r
+    </xsl:template>\r
+\r
+    <xsl:template name="ios">\r
+        <xsl:choose>\r
+            <xsl:when test="count(io) &gt; 0">\r
+                <table class="ios"  align="center"  border="1" width="75%" cellspacing="0" cellpadding="4">\r
+                    <tr>\r
+                        <th>\r
+                            Port Name\r
+                        </th>\r
+                        <th>\r
+                            Direction\r
+                        </th>\r
+                        <th>\r
+                            Pin\r
+                        </th>\r
+                        <th>\r
+                            I/O Standard\r
+                        </th>\r
+                    </tr>\r
+                    <xsl:for-each select="io">\r
+                        <tr>\r
+                            <xsl:call-template name="print-ios"/>\r
+                        </tr>\r
+                    </xsl:for-each>\r
+                </table>\r
+            </xsl:when>\r
+            <xsl:otherwise>\r
+                <i>No IO's </i>\r
+                <br/>\r
+                <br/>\r
+            </xsl:otherwise>\r
+        </xsl:choose>\r
+        <xsl:call-template name="top-link"/>\r
+    </xsl:template>\r
+\r
+\r
+    <!-- /////////////////////////////////////////////////////////  -->\r
+\r
+    <xsl:template name="firmware_cores">\r
+        <xsl:choose>\r
+            <xsl:when test="count(firmware_core) &gt; 0">\r
+                <!-- Core TOC -->\r
+                <div class="content">\r
+                    <b>Software IDE: </b>\r
+                    <xsl:value-of select="/datasheet/project-settings/swide-toolchain"/>\r
+                    <br/>\r
+                    <br/>\r
+\r
+                    <span class="instances">Drivers:</span>\r
+                    <br/>\r
+                    <xsl:for-each select="firmware_core">\r
+                        <a href="#{core-name}">\r
+                            <xsl:value-of select="core-name"/>\r
+                        </a>\r
+\r
+                        <br/>\r
+                    </xsl:for-each>\r
+                    <br/>\r
+                    <div class="toplinks">\r
+                        <xsl:call-template name="top-link"/>\r
+                    </div>\r
+                </div>\r
+\r
+                <xsl:for-each select="firmware_core">\r
+                    <div class="content">\r
+                        <!-- Core TOC -->\r
+                        <a name="{core-name}"/>\r
+\r
+                        <table class="cores" width="97%" border="0" cellspacing="0" cellpadding="14">\r
+                            <!--border="1"  cellspacing="0" cellpadding="14"> -->\r
+                            <xsl:choose>\r
+\r
+                                <xsl:when test='@type="FirmWareModule"'>\r
+                                    <xsl:call-template name="print-cores-spirit"/>\r
+                                </xsl:when>\r
+\r
+                            </xsl:choose>\r
+\r
+                        </table>\r
+                        <div class="toplinks">\r
+                            <a href="#cores">instance list</a>, <xsl:call-template name="top-link"/>\r
+                        </div>\r
+                    </div>\r
+                    <br/>\r
+                </xsl:for-each>\r
+                <br/>\r
+            </xsl:when>\r
+            <xsl:otherwise>\r
+                <br/>\r
+                <i>No Firmware Generated.  Design may not contain any processor subsystems, or firmware have not been downloaded to your vault</i>\r
+                <br/>\r
+                <br/>\r
+                <xsl:call-template name="top-link"/>\r
+                <br/>\r
+                <br/>\r
+            </xsl:otherwise>\r
+        </xsl:choose>\r
+    </xsl:template>\r
+\r
+\r
+\r
+    <!-- /////////////////////////////////////////////////////////  -->\r
+\r
+    <xsl:template name="cores">\r
+        <xsl:choose>\r
+\r
+            <xsl:when test="count(core) &gt; 0">\r
+                <!-- Core TOC -->\r
+                <div class="content">\r
+                    <span class="instances">Instances:</span>\r
+                    <br/>\r
+                    <xsl:for-each select="core">\r
+                        <a href="#{core-name}">\r
+                            <xsl:value-of select="core-name"/>\r
+                        </a>\r
+\r
+                        <br/>\r
+                    </xsl:for-each>\r
+                    <br/>\r
+                    <div class="toplinks">\r
+                        <xsl:call-template name="top-link"/>\r
+                    </div>\r
+                </div>\r
+\r
+                <xsl:for-each select="core">\r
+                    <div class="content">\r
+                        <!-- Core TOC -->\r
+                        <a name="{core-name}"/>\r
+\r
+                        <table class="cores" width="97%" border="0" cellspacing="0" cellpadding="14">\r
+                            <!--border="1"  cellspacing="0" cellpadding="14"> -->\r
+                            <xsl:choose>\r
+                                <xsl:when test='@type="ComponentModule"'>\r
+                                    <xsl:call-template name="print-cores-comp"/>\r
+                                </xsl:when>\r
+                                <xsl:when test='@type="SpiritModule"'>\r
+                                    <xsl:call-template name="print-cores-spirit"/>\r
+                                </xsl:when>\r
+                                <xsl:when test='@type="AdlibModule"'>\r
+                                    <xsl:call-template name="print-cores-adlib"/>\r
+                                </xsl:when>\r
+                                <xsl:when test='@type="HdlModule"'>\r
+                                    <xsl:call-template name="print-cores-hdl"/>\r
+                                </xsl:when>\r
+                            </xsl:choose>\r
+\r
+                        </table>\r
+                        <div class="toplinks">\r
+                            <a href="#cores">instance list</a>, <xsl:call-template name="top-link"/>\r
+                        </div>\r
+                    </div>\r
+                    <br/>\r
+                </xsl:for-each>\r
+                <br/>\r
+            </xsl:when>\r
+            <xsl:otherwise>\r
+                <br/>\r
+                <i>No Instances</i>\r
+                <br/>\r
+                <br/>\r
+                <xsl:call-template name="top-link"/>\r
+                <br/>\r
+                <br/>\r
+            </xsl:otherwise>\r
+        </xsl:choose>\r
+    </xsl:template>\r
+\r
+    <xsl:template name="print-cores-comp">\r
+        <tr>\r
+            <td>\r
+                <table border="0">\r
+                    <xsl:call-template name="print-cores"/>\r
+                    <tr>\r
+                        <td>\r
+                            <b>Type: </b>\r
+                        </td>\r
+                        <td>\r
+                            <xsl:apply-templates select="core-exttype"/>\r
+                        </td>\r
+                    </tr>\r
+                    <tr>\r
+                        <td>\r
+                            <b>Location: </b>\r
+                        </td>\r
+                        <td>\r
+                            <xsl:apply-templates select="core-location"/>\r
+                        </td>\r
+                    </tr>\r
+                </table>\r
+            </td>\r
+        </tr>\r
+    </xsl:template>\r
+\r
+    <xsl:template name="print-cores-spirit">\r
+        <tr>\r
+            <td>\r
+                <table border="0">\r
+                    <xsl:call-template name="print-cores"/>\r
+                    <tr>\r
+                        <td>\r
+                            <b>Type: </b>\r
+                        </td>\r
+                        <td>\r
+                            <xsl:apply-templates select="core-exttype"/>\r
+                        </td>\r
+                    </tr>\r
+                    <tr>\r
+                        <td>\r
+                            <b>Vendor: </b>\r
+                        </td>\r
+                        <td>\r
+                            <xsl:apply-templates select="core-vendor"/>\r
+                        </td>\r
+                    </tr>\r
+                    <tr>\r
+                        <td>\r
+                            <b>Library: </b>\r
+                        </td>\r
+                        <td>\r
+                            <xsl:apply-templates select="core-lib"/>\r
+                        </td>\r
+                    </tr>\r
+                    <tr>\r
+                        <td>\r
+                            <b>Core Name: </b>\r
+                        </td>\r
+                        <td>\r
+                            <xsl:apply-templates select="core-intname"/>\r
+                        </td>\r
+                    </tr>\r
+                    <tr>\r
+                        <td>\r
+                            <b>Version: </b>\r
+                        </td>\r
+                        <td>\r
+                            <xsl:apply-templates select="core-ver"/>\r
+                        </td>\r
+                    </tr>\r
+                    <tr>\r
+                        <td>\r
+                            <b>Description: </b>\r
+                        </td>\r
+                        <td>\r
+                            <xsl:apply-templates select="core-desc"/>\r
+                        </td>\r
+                    </tr>\r
+                    <tr>\r
+                        <td>\r
+                            <b>Parameters: </b>\r
+                        </td>\r
+                        <td>\r
+                            <xsl:call-template name="print-spirit-params"/>\r
+                        </td>\r
+                    </tr>\r
+                </table>\r
+            </td>\r
+        </tr>\r
+    </xsl:template>\r
+\r
+    <xsl:template name="print-spirit-params" >\r
+        <xsl:if test="count(core-param) > 0">\r
+            <div style="background-color: #F0F0F0; " >\r
+                <br/>\r
+                <table>\r
+                    <!-- <tr>\r
+            <th>\r
+              Name\r
+            </th>\r
+            <th>\r
+              Value\r
+            </th>\r
+          </tr> -->\r
+                    <xsl:for-each select="core-param">\r
+                        <xsl:call-template name="print-core-params"/>\r
+                    </xsl:for-each>\r
+                </table>\r
+            </div>\r
+        </xsl:if>\r
+        <xsl:if test="count(core-param) &lt; 1">\r
+            <i>No parameters</i>\r
+        </xsl:if>\r
+    </xsl:template>\r
+\r
+    <xsl:template name="print-cores-adlib">\r
+        <tr>\r
+            <td>\r
+                <table border="0">\r
+                    <xsl:call-template name="print-cores"/>\r
+                    <tr>\r
+                        <td>\r
+                            <b>Cell Type: </b>\r
+                        </td>\r
+                        <td>\r
+                            <xsl:apply-templates select="core-exttype"/>\r
+                        </td>\r
+                    </tr>\r
+                </table>\r
+\r
+            </td>\r
+        </tr>\r
+    </xsl:template>\r
+\r
+    <xsl:template name="print-cores-hdl">\r
+        <tr>\r
+            <td>\r
+                <table border="0">\r
+                    <xsl:call-template name="print-cores"/>\r
+                    <tr>\r
+                        <td>\r
+                            <b>Module Name: </b>\r
+                        </td>\r
+                        <td>\r
+                            <xsl:apply-templates select="core-exttype"/>\r
+                        </td>\r
+                    </tr>\r
+                    <tr>\r
+                        <td>\r
+                            <b>HDL File: </b>\r
+                        </td>\r
+                        <td>\r
+                            <xsl:apply-templates select="core-location"/>\r
+                        </td>\r
+                    </tr>\r
+                </table>\r
+            </td>\r
+        </tr>\r
+    </xsl:template>\r
+\r
+    <xsl:template name="print-cores">\r
+        <tr>\r
+            <td width="200">\r
+                <b>Instance Name: </b>\r
+            </td>\r
+            <td>\r
+                <xsl:apply-templates select="core-name"/>\r
+            </td>\r
+        </tr>\r
+    </xsl:template>\r
+\r
+    <xsl:template name="print-core-params">\r
+        <tr>\r
+            <td>\r
+                <b class="params-name">\r
+                    <xsl:apply-templates select="param-hdlname"/> [ <xsl:apply-templates select="param-name"/> ]\r
+                </b>\r
+            </td>\r
+            <td>\r
+                <xsl:apply-templates select="param-hdlvalue"/> [ <xsl:apply-templates select="param-value"/> ]\r
+            </td>\r
+        </tr>\r
+    </xsl:template>\r
+\r
+\r
+\r
+\r
+    <!--/////////////////////////////////////////////////////////-->\r
+\r
+    <xsl:template match="port-name|direction|pin-number|io-standard">\r
+        <xsl:value-of select="."/>\r
+    </xsl:template >\r
+\r
+    <xsl:template match="core-name|core-type|core-exttype">\r
+        <xsl:value-of select="."/>\r
+    </xsl:template >\r
+\r
+    <xsl:template match="core-vendor|core-lib|core-intname|core-ver|core-desc">\r
+        <xsl:value-of select="."/>\r
+    </xsl:template >\r
+\r
+    <xsl:template match="core-location">\r
+        <xsl:value-of select="."/>\r
+    </xsl:template >\r
+\r
+    <xsl:template match="fam|die|package|hdl-type|location|state">\r
+        <xsl:value-of select="."/>\r
+    </xsl:template >\r
+\r
+    <xsl:template match="param-name|param-value|param-tag|param-hdlname|param-hdlvalue">\r
+        <xsl:value-of select="."/>\r
+    </xsl:template >\r
+\r
+\r
+    <xsl:template name="top-link">\r
+        <a href="#top">top of page</a>\r
+    </xsl:template>\r
+\r
+\r
+\r
+    <!--=============================MEMORY MAP===================================-->\r
+\r
+    <xsl:template match="memorysystem">\r
+\r
+        <div class="content">\r
+            <xsl:apply-templates select="description"/>\r
+        </div>\r
+        <div>\r
+            <xsl:apply-templates select="subsystems"/>\r
+        </div>\r
+\r
+    </xsl:template>\r
+\r
+\r
+    <xsl:template match="subsystems">\r
+\r
+        <xsl:for-each select="subsystem">\r
+            <li>\r
+                <div class="content">\r
+                    <a href="#{name} Memory Map">\r
+                        <xsl:value-of select="node()"/>\r
+                    </a>\r
+                </div>\r
+            </li>\r
+        </xsl:for-each>\r
+\r
+        <div class="content">\r
+            <div class="toplinks">\r
+                <xsl:call-template name="top-link"/>\r
+            </div>\r
+        </div>\r
+        <br/>\r
+\r
+        <hr></hr>\r
+        <xsl:apply-templates select="subsystem"/>\r
+\r
+    </xsl:template>\r
+\r
+    <xsl:template match="subsystem">\r
+        <div class="content">\r
+            <h2>\r
+                <a name="{name} Memory Map">\r
+                    <xsl:value-of select="name"/>\r
+                </a> Subsystem\r
+            </h2>\r
+            Master(s) on this bus:\r
+            <xsl:apply-templates select="master"/>\r
+            <br></br><br></br>\r
+\r
+            <xsl:apply-templates select="addressNames" />\r
+            <a href="#memmap">subsystem list</a>,\r
+            <xsl:call-template name="top-link"/>\r
+\r
+            <br/><br/>\r
+            <hr></hr>\r
+            <xsl:apply-templates select="slave"/>\r
+        </div>\r
+    </xsl:template>\r
+\r
+    <xsl:template match="title">\r
+        <span style="color:#000000">\r
+            <xsl:value-of select="text()"/>\r
+        </span>\r
+    </xsl:template>\r
+\r
+    <xsl:template match="description">\r
+        <xsl:value-of select="text()"/>\r
+    </xsl:template>\r
+\r
+    <xsl:template match="master">\r
+        <li>\r
+            <div class="content">\r
+                <xsl:value-of select="text()"/>\r
+            </div>\r
+        </li>\r
+    </xsl:template>\r
+\r
+    <xsl:template match="addressNames">\r
+        <table class="regs" border="1" cellspace="0" cellpadding="10"  align="center" >\r
+            <xsl:if test="count = 1">\r
+                <tr bgcolor="#aaaacc">\r
+                    <th rowspan="1"></th>\r
+                    <th colspan="2">Address Range</th>\r
+                </tr>\r
+            </xsl:if>\r
+            <xsl:if test="count &gt; 1">\r
+                <tr bgcolor="#aaaacc">\r
+                    <th rowspan="2"></th>\r
+                    <th colspan="2">Address Range</th>\r
+                </tr>\r
+                <tr>\r
+                    <xsl:for-each select="name">\r
+                        <th bgcolor="#aaaacc">\r
+                            <xsl:value-of select="text()"/>\r
+                        </th>\r
+                    </xsl:for-each>\r
+                </tr>\r
+            </xsl:if>\r
+\r
+            <xsl:for-each select="../slave">\r
+                <tr>\r
+                    <th cellspace="0" colspan="1">\r
+                        <b>\r
+                            <a class="toplinks" href="#{name}_{memoryMap/name} Register">\r
+                                <xsl:value-of select="name"/> : <xsl:value-of select="memoryMap/name"/>\r
+                            </a>\r
+                        </b>\r
+                    </th>\r
+                    <xsl:for-each select="fullAddressSpace">\r
+                        <td align="center">\r
+                            <xsl:value-of select="text()"/>\r
+                        </td>\r
+                    </xsl:for-each>\r
+                </tr>\r
+            </xsl:for-each>\r
+\r
+        </table>\r
+    </xsl:template>\r
+\r
+    <xsl:template match="slave">\r
+        <div class="content">\r
+            <h3>\r
+                <a name="{name}_{memoryMap/name} Register">\r
+                    <xsl:value-of select="name"/> : <xsl:value-of select="memoryMap/name"/> Memory Map [\r
+                    <xsl:value-of select="fullAddressSpace"/> ]\r
+                </a>\r
+            </h3>\r
+        </div>\r
+        <div class="mmrange">\r
+\r
+            <i>range: </i>\r
+            <xsl:apply-templates select="range"/>\r
+\r
+        </div>\r
+        <xsl:if test="memoryMap/addressBlock/register">\r
+            <xsl:apply-templates select="memoryMap/addressBlock"/>\r
+        </xsl:if>\r
+        <a class="toplinks" href="#{../name} Memory Map">\r
+            back to <xsl:value-of select="../name"/> Memory Map\r
+        </a>\r
+        <br/>\r
+        <br/>\r
+        <hr></hr>\r
+    </xsl:template>\r
+\r
+    <xsl:template match="addressBlock">\r
+        <table class="regs" border="2" cellspace="0" cellpadding="4" align="center">\r
+            <tr bgcolor="#aaaacc">\r
+                <th>Address</th>\r
+                <th>Name</th>\r
+                <th>R/W</th>\r
+                <th>Width</th>\r
+                <th>Reset Value</th>\r
+                <th>Description</th>\r
+            </tr>\r
+            <xsl:for-each select="register">\r
+                <tr>\r
+                    <td align="center" nowrap="true">\r
+                        <xsl:value-of select="absoluteAddress"/>\r
+                    </td>\r
+                    <xsl:choose>\r
+                        <xsl:when test="field">\r
+                            <td align="center">\r
+                                <a class="toplinks" href="#{../../../name}_{name}">\r
+                                    <xsl:value-of select="name"/>\r
+                                </a>\r
+                            </td>\r
+                        </xsl:when>\r
+                        <xsl:otherwise>\r
+                            <td align="center">\r
+                                <xsl:value-of select="name"/>\r
+                            </td>\r
+                        </xsl:otherwise>\r
+                    </xsl:choose>\r
+                    <td align="center" nowrap="true">\r
+                        <xsl:value-of select="access"/>\r
+                    </td>\r
+                    <td align="center">\r
+                        <xsl:value-of select="size"/>\r
+                    </td>\r
+                    <td align="center">\r
+                        <xsl:value-of select="resetValue"/>\r
+                    </td>\r
+                    <td align="left">\r
+                        <xsl:value-of select="description"/>\r
+                    </td>\r
+                </tr>\r
+            </xsl:for-each>\r
+        </table>\r
+\r
+        <xsl:if test="register/field">\r
+            <a class="toplinks" href="#{../../../name} Memory Map">\r
+                back to <xsl:value-of select="../../../name"/> Memory Map\r
+            </a>\r
+            <xsl:for-each select="register">\r
+                <div class="content">\r
+                    <h4>\r
+                        <a class="register-details" name="{../../../name}_{name}">\r
+                            <xsl:value-of select="name"/> register details [ <xsl:value-of select="absoluteAddress"/> ] :\r
+                        </a>\r
+                    </h4>\r
+                </div>\r
+                <div class="regwidth">\r
+\r
+                    <i>width: </i>\r
+                    <xsl:apply-templates select="size"/>-bit\r
+\r
+                </div>\r
+\r
+                <table class="regs" border="2" cellspace="0" cellpadding="4" align="center" >\r
+                    <tr bgcolor="#aaaacc">\r
+                        <th align="left">Bit Number</th>\r
+                        <th>Name</th>\r
+                        <th>R/W</th>\r
+                        <th>Description</th>\r
+                    </tr>\r
+                    <xsl:for-each select="field">\r
+                        <tr>\r
+                            <td align="left">\r
+                                <xsl:value-of select="bitNumber"/>\r
+                            </td>\r
+                            <td align="center">\r
+                                <xsl:value-of select="name"/>\r
+                            </td>\r
+                            <td align="center" nowrap="true">\r
+                                <xsl:value-of select="access"/>\r
+                            </td>\r
+                            <td align="left">\r
+                                <xsl:value-of select="description"/>\r
+                            </td>\r
+                        </tr>\r
+                    </xsl:for-each>\r
+                </table>\r
+\r
+                <a class="toplinks" href="#{../../../name}_{../../../memoryMap/name} Register">\r
+                    back to <xsl:value-of select="../../../name"/> Registers\r
+                </a>\r
+                <br/>\r
+                <br/>\r
+            </xsl:for-each>\r
+            <br/>\r
+            <br/>\r
+        </xsl:if>\r
+\r
+    </xsl:template>\r
+\r
+    <xsl:template match="range">\r
+        <xsl:value-of select="."/>\r
+    </xsl:template >\r
+\r
+    <!--==========================END MEMORY MAP===================================-->\r
+\r
+\r
+\r
+    <!--============================= CSS ===================================-->\r
+    <xsl:template name="css">\r
+        <style>\r
+\r
+            html\r
+            {\r
+            background-color:darkgray;\r
+            }\r
+\r
+            body\r
+            {\r
+            font-family:arial;\r
+            font-size: 11pt;\r
+            text-align:center;\r
+            }\r
+\r
+\r
+            th\r
+            {\r
+            background-color: #F0F0F0;\r
+            }\r
+\r
+            table.cores\r
+            {\r
+            background-color: #F0F0F0;\r
+            border-color: #B0B0B0;\r
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diff --git a/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo/.cproject b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo/.cproject
new file mode 100644 (file)
index 0000000..ec9cfe4
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo/.cproject
@@ -0,0 +1,462 @@
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+</scannerConfigBuildInfo>\r
+</storageModule>\r
+<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>\r
+<storageModule moduleId="org.eclipse.cdt.core.language.mapping"/>\r
+<storageModule moduleId="org.eclipse.cdt.internal.ui.text.commentOwnerProjectMappings"/>\r
+</cconfiguration>\r
+</storageModule>\r
+<storageModule moduleId="cdtBuildSystem" version="4.0.0">\r
+<project id="RTOSDemo.cdt.managedbuild.target.gnu.cross.cortexm3.exe.340201866" name="Executable (Managed Make)" projectType="cdt.managedbuild.target.gnu.cross.cortexm3.exe"/>\r
+</storageModule>\r
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diff --git a/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo/.project b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo/.project
new file mode 100644 (file)
index 0000000..db74fca
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo/.project
@@ -0,0 +1,81 @@
+<?xml version="1.0" encoding="UTF-8"?>\r
+<projectDescription>\r
+       <name>RTOSDemo</name>\r
+       <comment></comment>\r
+       <projects>\r
+        <project> RTOSDemo_Hardware_Platform </project>\r
+       </projects>\r
+       <buildSpec>\r
+               <buildCommand>\r
+                       <name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>\r
+                       <arguments>\r
+                               <dictionary>\r
+                                       <key>?name?</key>\r
+                                       <value></value>\r
+                               </dictionary>\r
+                               <dictionary>\r
+                                       <key>org.eclipse.cdt.make.core.append_environment</key>\r
+                                       <value>true</value>\r
+                               </dictionary>\r
+                               <dictionary>\r
+                                       <key>org.eclipse.cdt.make.core.autoBuildTarget</key>\r
+                                       <value>all</value>\r
+                               </dictionary>\r
+                               <dictionary>\r
+                                       <key>org.eclipse.cdt.make.core.buildArguments</key>\r
+                                       <value></value>\r
+                               </dictionary>\r
+                               <dictionary>\r
+                                       <key>org.eclipse.cdt.make.core.buildCommand</key>\r
+                                       <value>make</value>\r
+                               </dictionary>\r
+                               <dictionary>\r
+                                       <key>org.eclipse.cdt.make.core.buildLocation</key>\r
+                                       <value>${workspace_loc:/RTOSDemo/Debug}</value>\r
+                               </dictionary>\r
+                               <dictionary>\r
+                                       <key>org.eclipse.cdt.make.core.cleanBuildTarget</key>\r
+                                       <value>clean</value>\r
+                               </dictionary>\r
+                               <dictionary>\r
+                                       <key>org.eclipse.cdt.make.core.contents</key>\r
+                                       <value>org.eclipse.cdt.make.core.activeConfigSettings</value>\r
+                               </dictionary>\r
+                               <dictionary>\r
+                                       <key>org.eclipse.cdt.make.core.enableAutoBuild</key>\r
+                                       <value>true</value>\r
+                               </dictionary>\r
+                               <dictionary>\r
+                                       <key>org.eclipse.cdt.make.core.enableCleanBuild</key>\r
+                                       <value>true</value>\r
+                               </dictionary>\r
+                               <dictionary>\r
+                                       <key>org.eclipse.cdt.make.core.enableFullBuild</key>\r
+                                       <value>true</value>\r
+                               </dictionary>\r
+                               <dictionary>\r
+                                       <key>org.eclipse.cdt.make.core.fullBuildTarget</key>\r
+                                       <value>all</value>\r
+                               </dictionary>\r
+                               <dictionary>\r
+                                       <key>org.eclipse.cdt.make.core.stopOnError</key>\r
+                                       <value>true</value>\r
+                               </dictionary>\r
+                               <dictionary>\r
+                                       <key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>\r
+                                       <value>true</value>\r
+                               </dictionary>\r
+                       </arguments>\r
+               </buildCommand>\r
+               <buildCommand>\r
+                       <name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>\r
+                       <arguments>\r
+                       </arguments>\r
+               </buildCommand>\r
+       </buildSpec>\r
+       <natures>\r
+               <nature>org.eclipse.cdt.core.cnature</nature>\r
+               <nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>\r
+               <nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>\r
+       </natures>\r
+</projectDescription>\r
diff --git a/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo/Blinky-Demo/main_blinky.c b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo/Blinky-Demo/main_blinky.c
new file mode 100644 (file)
index 0000000..f399c90
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo/Blinky-Demo/main_blinky.c
@@ -0,0 +1,245 @@
+/*\r
+    FreeRTOS V7.4.2 - Copyright (C) 2013 Real Time Engineers Ltd.\r
+\r
+    FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME.  PLEASE VISIT\r
+    http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+    ***************************************************************************\r
+     *                                                                       *\r
+     *    FreeRTOS tutorial books are available in pdf and paperback.        *\r
+     *    Complete, revised, and edited pdf reference manuals are also       *\r
+     *    available.                                                         *\r
+     *                                                                       *\r
+     *    Purchasing FreeRTOS documentation will not only help you, by       *\r
+     *    ensuring you get running as quickly as possible and with an        *\r
+     *    in-depth knowledge of how to use FreeRTOS, it will also help       *\r
+     *    the FreeRTOS project to continue with its mission of providing     *\r
+     *    professional grade, cross platform, de facto standard solutions    *\r
+     *    for microcontrollers - completely free of charge!                  *\r
+     *                                                                       *\r
+     *    >>> See http://www.FreeRTOS.org/Documentation for details. <<<     *\r
+     *                                                                       *\r
+     *    Thank you for using FreeRTOS, and thank you for your support!      *\r
+     *                                                                       *\r
+    ***************************************************************************\r
+\r
+\r
+    This file is part of the FreeRTOS distribution.\r
+\r
+    FreeRTOS is free software; you can redistribute it and/or modify it under\r
+    the terms of the GNU General Public License (version 2) as published by the\r
+    Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+\r
+    >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to\r
+    distribute a combined work that includes FreeRTOS without being obliged to\r
+    provide the source code for proprietary components outside of the FreeRTOS\r
+    kernel.\r
+\r
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+    FOR A PARTICULAR PURPOSE.  See the GNU General Public License for more\r
+    details. You should have received a copy of the GNU General Public License\r
+    and the FreeRTOS license exception along with FreeRTOS; if not it can be\r
+    viewed here: http://www.freertos.org/a00114.html and also obtained by\r
+    writing to Real Time Engineers Ltd., contact details for whom are available\r
+    on the FreeRTOS WEB site.\r
+\r
+    1 tab == 4 spaces!\r
+\r
+    ***************************************************************************\r
+     *                                                                       *\r
+     *    Having a problem?  Start by reading the FAQ "My application does   *\r
+     *    not run, what could be wrong?"                                     *\r
+     *                                                                       *\r
+     *    http://www.FreeRTOS.org/FAQHelp.html                               *\r
+     *                                                                       *\r
+    ***************************************************************************\r
+\r
+\r
+    http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
+    license and Real Time Engineers Ltd. contact details.\r
+\r
+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+    including FreeRTOS+Trace - an indispensable productivity tool, and our new\r
+    fully thread aware and reentrant UDP/IP stack.\r
+\r
+    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
+    Integrity Systems, who sell the code with commercial support,\r
+    indemnification and middleware, under the OpenRTOS brand.\r
+\r
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+    engineered and independently SIL3 certified version for use in safety and\r
+    mission critical applications that require provable dependability.\r
+*/\r
+\r
+/******************************************************************************\r
+ * NOTE 1:  This project provides two demo applications.  A simple blinky style\r
+ * project, and a more comprehensive test and demo application.  The\r
+ * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to select\r
+ * between the two.  See the notes on using mainCREATE_SIMPLE_BLINKY_DEMO_ONLY\r
+ * in main.c.  This file implements the simply blinky style version.\r
+ *\r
+ * NOTE 2:  This file only contains the source code that is specific to the\r
+ * basic demo.  Generic functions, such FreeRTOS hook functions, and functions\r
+ * required to configure the hardware, are defined in main.c.\r
+ ******************************************************************************\r
+ *\r
+ * main_blinky() creates one queue, and two tasks.  It then starts the\r
+ * scheduler.\r
+ *\r
+ * The Queue Send Task:\r
+ * The queue send task is implemented by the prvQueueSendTask() function in\r
+ * this file.  prvQueueSendTask() sits in a loop that causes it to repeatedly\r
+ * block for 200 milliseconds, before sending the value 100 to the queue that\r
+ * was created within main_blinky().  Once the value is sent, the task loops\r
+ * back around to block for another 200 milliseconds.\r
+ *\r
+ * The Queue Receive Task:\r
+ * The queue receive task is implemented by the prvQueueReceiveTask() function\r
+ * in this file.  prvQueueReceiveTask() sits in a loop where it repeatedly\r
+ * blocks on attempts to read data from the queue that was created within\r
+ * main_blinky().  When data is received, the task checks the value of the\r
+ * data, and if the value equals the expected 100, toggles the LED.  The 'block\r
+ * time' parameter passed to the queue receive function specifies that the\r
+ * task should be held in the Blocked state indefinitely to wait for data to\r
+ * be available on the queue.  The queue receive task will only leave the\r
+ * Blocked state when the queue send task writes to the queue.  As the queue\r
+ * send task writes to the queue every 200 milliseconds, the queue receive\r
+ * task leaves the Blocked state every 200 milliseconds, and therefore toggles\r
+ * the LED every 200 milliseconds.\r
+ */\r
+\r
+/* Standard includes. */\r
+#include <stdio.h>\r
+\r
+/* Kernel includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "semphr.h"\r
+\r
+/* Common demo includes. */\r
+#include "partest.h"\r
+\r
+/* Priorities at which the tasks are created. */\r
+#define mainQUEUE_RECEIVE_TASK_PRIORITY                ( tskIDLE_PRIORITY + 2 )\r
+#define        mainQUEUE_SEND_TASK_PRIORITY            ( tskIDLE_PRIORITY + 1 )\r
+\r
+/* The rate at which data is sent to the queue.  The 200ms value is converted\r
+to ticks using the portTICK_RATE_MS constant. */\r
+#define mainQUEUE_SEND_FREQUENCY_MS                    ( 200 / portTICK_RATE_MS )\r
+\r
+/* The number of items the queue can hold.  This is 1 as the receive task\r
+will remove items as they are added, meaning the send task should always find\r
+the queue empty. */\r
+#define mainQUEUE_LENGTH                                       ( 1 )\r
+\r
+/* Values passed to the two tasks just to check the task parameter\r
+functionality. */\r
+#define mainQUEUE_SEND_PARAMETER                       ( 0x1111UL )\r
+#define mainQUEUE_RECEIVE_PARAMETER                    ( 0x22UL )\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * The tasks as described in the comments at the top of this file.\r
+ */\r
+static void prvQueueReceiveTask( void *pvParameters );\r
+static void prvQueueSendTask( void *pvParameters );\r
+\r
+/*\r
+ * Called by main() to create the simply blinky style application if\r
+ * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1.\r
+ */\r
+void main_blinky( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The queue used by both tasks. */\r
+static xQueueHandle xQueue = NULL;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void main_blinky( void )\r
+{\r
+       /* Create the queue. */\r
+       xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( unsigned long ) );\r
+\r
+       if( xQueue != NULL )\r
+       {\r
+               /* Start the two tasks as described in the comments at the top of this\r
+               file. */\r
+               xTaskCreate( prvQueueReceiveTask,                                       /* The function that implements the task. */\r
+                                       ( signed char * ) "Rx",                                 /* The text name assigned to the task - for debug only as it is not used by the kernel. */\r
+                                       configMINIMAL_STACK_SIZE,                               /* The size of the stack to allocate to the task. */\r
+                                       ( void * ) mainQUEUE_RECEIVE_PARAMETER, /* The parameter passed to the task - just to check the functionality. */\r
+                                       mainQUEUE_RECEIVE_TASK_PRIORITY,                /* The priority assigned to the task. */\r
+                                       NULL );                                                                 /* The task handle is not required, so NULL is passed. */\r
+\r
+               xTaskCreate( prvQueueSendTask, ( signed char * ) "TX", configMINIMAL_STACK_SIZE, ( void * ) mainQUEUE_SEND_PARAMETER, mainQUEUE_SEND_TASK_PRIORITY, NULL );\r
+\r
+               /* Start the tasks and timer running. */\r
+               vTaskStartScheduler();\r
+       }\r
+\r
+       /* If all is well, the scheduler will now be running, and the following\r
+       line will never be reached.  If the following line does execute, then\r
+       there was insufficient FreeRTOS heap memory available for the idle and/or\r
+       timer tasks     to be created.  See the memory management section on the\r
+       FreeRTOS web site for more details. */\r
+       for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvQueueSendTask( void *pvParameters )\r
+{\r
+portTickType xNextWakeTime;\r
+const unsigned long ulValueToSend = 100UL;\r
+\r
+       /* Check the task parameter is as expected. */\r
+       configASSERT( ( ( unsigned long ) pvParameters ) == mainQUEUE_SEND_PARAMETER );\r
+\r
+       /* Initialise xNextWakeTime - this only needs to be done once. */\r
+       xNextWakeTime = xTaskGetTickCount();\r
+\r
+       for( ;; )\r
+       {\r
+               /* Place this task in the blocked state until it is time to run again.\r
+               The block time is specified in ticks, the constant used converts ticks\r
+               to ms.  While in the Blocked state this task will not consume any CPU\r
+               time. */\r
+               vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS );\r
+\r
+               /* Send to the queue - causing the queue receive task to unblock and\r
+               toggle the LED.  0 is used as the block time so the sending operation\r
+               will not block - it shouldn't need to block as the queue should always\r
+               be empty at this point in the code. */\r
+               xQueueSend( xQueue, &ulValueToSend, 0U );\r
+       }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvQueueReceiveTask( void *pvParameters )\r
+{\r
+unsigned long ulReceivedValue;\r
+\r
+       /* Check the task parameter is as expected. */\r
+       configASSERT( ( ( unsigned long ) pvParameters ) == mainQUEUE_RECEIVE_PARAMETER );\r
+\r
+       for( ;; )\r
+       {\r
+               /* Wait until something arrives in the queue - this task will block\r
+               indefinitely provided INCLUDE_vTaskSuspend is set to 1 in\r
+               FreeRTOSConfig.h. */\r
+               xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY );\r
+\r
+               /*  To get here something must have been received from the queue, but\r
+               is it the expected value?  If it is, toggle the LED. */\r
+               if( ulReceivedValue == 100UL )\r
+               {\r
+                       vParTestToggleLED( 0 );\r
+                       ulReceivedValue = 0U;\r
+               }\r
+       }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
diff --git a/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo/FreeRTOSConfig.h
new file mode 100644 (file)
index 0000000..53c1313
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo/FreeRTOSConfig.h
@@ -0,0 +1,191 @@
+/*\r
+    FreeRTOS V7.4.2 - Copyright (C) 2013 Real Time Engineers Ltd.\r
+\r
+    FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME.  PLEASE VISIT\r
+    http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+    ***************************************************************************\r
+     *                                                                       *\r
+     *    FreeRTOS tutorial books are available in pdf and paperback.        *\r
+     *    Complete, revised, and edited pdf reference manuals are also       *\r
+     *    available.                                                         *\r
+     *                                                                       *\r
+     *    Purchasing FreeRTOS documentation will not only help you, by       *\r
+     *    ensuring you get running as quickly as possible and with an        *\r
+     *    in-depth knowledge of how to use FreeRTOS, it will also help       *\r
+     *    the FreeRTOS project to continue with its mission of providing     *\r
+     *    professional grade, cross platform, de facto standard solutions    *\r
+     *    for microcontrollers - completely free of charge!                  *\r
+     *                                                                       *\r
+     *    >>> See http://www.FreeRTOS.org/Documentation for details. <<<     *\r
+     *                                                                       *\r
+     *    Thank you for using FreeRTOS, and thank you for your support!      *\r
+     *                                                                       *\r
+    ***************************************************************************\r
+\r
+\r
+    This file is part of the FreeRTOS distribution.\r
+\r
+    FreeRTOS is free software; you can redistribute it and/or modify it under\r
+    the terms of the GNU General Public License (version 2) as published by the\r
+    Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+\r
+    >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to\r
+    distribute a combined work that includes FreeRTOS without being obliged to\r
+    provide the source code for proprietary components outside of the FreeRTOS\r
+    kernel.\r
+\r
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+    FOR A PARTICULAR PURPOSE.  See the GNU General Public License for more\r
+    details. You should have received a copy of the GNU General Public License\r
+    and the FreeRTOS license exception along with FreeRTOS; if not it can be\r
+    viewed here: http://www.freertos.org/a00114.html and also obtained by\r
+    writing to Real Time Engineers Ltd., contact details for whom are available\r
+    on the FreeRTOS WEB site.\r
+\r
+    1 tab == 4 spaces!\r
+\r
+    ***************************************************************************\r
+     *                                                                       *\r
+     *    Having a problem?  Start by reading the FAQ "My application does   *\r
+     *    not run, what could be wrong?"                                     *\r
+     *                                                                       *\r
+     *    http://www.FreeRTOS.org/FAQHelp.html                               *\r
+     *                                                                       *\r
+    ***************************************************************************\r
+\r
+\r
+    http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
+    license and Real Time Engineers Ltd. contact details.\r
+\r
+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+    including FreeRTOS+Trace - an indispensable productivity tool, and our new\r
+    fully thread aware and reentrant UDP/IP stack.\r
+\r
+    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
+    Integrity Systems, who sell the code with commercial support,\r
+    indemnification and middleware, under the OpenRTOS brand.\r
+\r
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+    engineered and independently SIL3 certified version for use in safety and\r
+    mission critical applications that require provable dependability.\r
+*/\r
+\r
+\r
+#ifndef FREERTOS_CONFIG_H\r
+#define FREERTOS_CONFIG_H\r
+\r
+/*\r
+ * The following #error directive is to remind users that a batch file must be\r
+ * executed prior to this project being built.  Once it has been executed\r
+ * remove the #error line below.\r
+ */\r
+//#error Ensure CreateProjectDirectoryStructure.bat has been executed before building.  See comment immediately above.\r
+\r
+/*-----------------------------------------------------------\r
+ * Application specific definitions.\r
+ *\r
+ * These definitions should be adjusted for your particular hardware and\r
+ * application requirements.\r
+ *\r
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\r
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.\r
+ *\r
+ * See http://www.freertos.org/a00110.html.\r
+ *----------------------------------------------------------*/\r
+\r
+#include <stdint.h>\r
+extern uint32_t SystemCoreClock;\r
+\r
+#define configUSE_PREEMPTION                   1\r
+#define configUSE_IDLE_HOOK                            1\r
+#define configUSE_TICK_HOOK                            0\r
+#define configCPU_CLOCK_HZ                             ( SystemCoreClock )\r
+#define configTICK_RATE_HZ                             ( ( portTickType ) 1000 )\r
+#define configMAX_PRIORITIES                   ( ( unsigned portBASE_TYPE ) 5 )\r
+#define configMINIMAL_STACK_SIZE               ( ( unsigned short ) 80 )\r
+#define configTOTAL_HEAP_SIZE                  ( ( size_t ) ( 25000 ) )\r
+#define configMAX_TASK_NAME_LEN                        ( 10 )\r
+#define configUSE_TRACE_FACILITY               1\r
+#define configUSE_16_BIT_TICKS                 0\r
+#define configIDLE_SHOULD_YIELD                        1\r
+#define configUSE_MUTEXES                              1\r
+#define configQUEUE_REGISTRY_SIZE              0\r
+#define configCHECK_FOR_STACK_OVERFLOW 2\r
+#define configUSE_RECURSIVE_MUTEXES            1\r
+#define configUSE_MALLOC_FAILED_HOOK   1\r
+#define configUSE_APPLICATION_TASK_TAG 0\r
+#define configUSE_COUNTING_SEMAPHORES  1\r
+\r
+/* Co-routine definitions. */\r
+#define configUSE_CO_ROUTINES                  0\r
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )\r
+\r
+/* Software timer definitions. */\r
+#define configUSE_TIMERS                               1\r
+#define configTIMER_TASK_PRIORITY              ( 2 )\r
+#define configTIMER_QUEUE_LENGTH               5\r
+#define configTIMER_TASK_STACK_DEPTH   ( configMINIMAL_STACK_SIZE * 2 )\r
+\r
+/* Run time stats gathering definitions. */\r
+void vConfigureTimerForRunTimeStats( void );\r
+uint32_t ulGetRunTimeCounterValue( void );\r
+#define configGENERATE_RUN_TIME_STATS  1\r
+#define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() vConfigureTimerForRunTimeStats()\r
+#define portGET_RUN_TIME_COUNTER_VALUE() ulGetRunTimeCounterValue()\r
+\r
+/* Set the following definitions to 1 to include the API function, or zero\r
+to exclude the API function. */\r
+#define INCLUDE_vTaskPrioritySet               1\r
+#define INCLUDE_uxTaskPriorityGet              1\r
+#define INCLUDE_vTaskDelete                            1\r
+#define INCLUDE_vTaskCleanUpResources  1\r
+#define INCLUDE_vTaskSuspend                   1\r
+#define INCLUDE_vTaskDelayUntil                        1\r
+#define INCLUDE_vTaskDelay                             1\r
+\r
+/* The size of the global output buffer that is available for use when there\r
+are multiple command interpreters running at once (for example, one on a UART\r
+and one on TCP/IP).  This is done to prevent an output buffer being defined by\r
+each implementation - which would waste RAM.  In this case, there is only one\r
+command interpreter running. */\r
+#define configCOMMAND_INT_MAX_OUTPUT_SIZE 2048\r
+\r
+/* Cortex-M specific definitions. */\r
+#ifdef __NVIC_PRIO_BITS\r
+       /* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */\r
+       #define configPRIO_BITS                 __NVIC_PRIO_BITS\r
+#else\r
+       #define configPRIO_BITS                 4        /* 15 priority levels */\r
+#endif\r
+\r
+/* The lowest interrupt priority that can be used in a call to a "set priority"\r
+function. */\r
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY                        0x0f\r
+\r
+/* The highest interrupt priority that can be used by any interrupt service\r
+routine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL\r
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER\r
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */\r
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY   10\r
+\r
+/* Interrupt priorities used by the kernel port layer itself.  These are generic\r
+to all Cortex-M ports, and do not rely on any particular library functions. */\r
+#define configKERNEL_INTERRUPT_PRIORITY                ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )\r
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!\r
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */\r
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY   ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )\r
+\r
+/* Normal assert() semantics without relying on the provision of an assert.h\r
+header file. */\r
+#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); for( ;; ); }\r
+\r
+/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS\r
+standard names. */\r
+#define vPortSVCHandler SVC_Handler\r
+#define xPortPendSVHandler PendSV_Handler\r
+#define xPortSysTickHandler SysTick_Handler\r
+\r
+#endif /* FREERTOS_CONFIG_H */\r
+\r
diff --git a/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo/Full-Demo/Common-Demo-Source/ReadMe.txt b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo/Full-Demo/Common-Demo-Source/ReadMe.txt
new file mode 100644 (file)
index 0000000..d19749f
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo/Full-Demo/Common-Demo-Source/ReadMe.txt
@@ -0,0 +1 @@
+Run the CreateProjectDirectoryStructure.bat batch file to populate this directory before building the demo.
\ No newline at end of file
diff --git a/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo/Full-Demo/Common-Demo-Source/include/ReadMe.txt b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo/Full-Demo/Common-Demo-Source/include/ReadMe.txt
new file mode 100644 (file)
index 0000000..d19749f
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo/Full-Demo/Common-Demo-Source/include/ReadMe.txt
@@ -0,0 +1 @@
+Run the CreateProjectDirectoryStructure.bat batch file to populate this directory before building the demo.
\ No newline at end of file
diff --git a/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo/Full-Demo/File-releated-CLI-commands.c b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo/Full-Demo/File-releated-CLI-commands.c
new file mode 100644 (file)
index 0000000..5e7b7a3
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo/Full-Demo/File-releated-CLI-commands.c
@@ -0,0 +1,575 @@
+/*\r
+    FreeRTOS V7.4.2 - Copyright (C) 2013 Real Time Engineers Ltd.\r
+\r
+    FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME.  PLEASE VISIT\r
+    http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+    ***************************************************************************\r
+     *                                                                       *\r
+     *    FreeRTOS tutorial books are available in pdf and paperback.        *\r
+     *    Complete, revised, and edited pdf reference manuals are also       *\r
+     *    available.                                                         *\r
+     *                                                                       *\r
+     *    Purchasing FreeRTOS documentation will not only help you, by       *\r
+     *    ensuring you get running as quickly as possible and with an        *\r
+     *    in-depth knowledge of how to use FreeRTOS, it will also help       *\r
+     *    the FreeRTOS project to continue with its mission of providing     *\r
+     *    professional grade, cross platform, de facto standard solutions    *\r
+     *    for microcontrollers - completely free of charge!                  *\r
+     *                                                                       *\r
+     *    >>> See http://www.FreeRTOS.org/Documentation for details. <<<     *\r
+     *                                                                       *\r
+     *    Thank you for using FreeRTOS, and thank you for your support!      *\r
+     *                                                                       *\r
+    ***************************************************************************\r
+\r
+\r
+    This file is part of the FreeRTOS distribution.\r
+\r
+    FreeRTOS is free software; you can redistribute it and/or modify it under\r
+    the terms of the GNU General Public License (version 2) as published by the\r
+    Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+\r
+    >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to\r
+    distribute a combined work that includes FreeRTOS without being obliged to\r
+    provide the source code for proprietary components outside of the FreeRTOS\r
+    kernel.\r
+\r
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+    FOR A PARTICULAR PURPOSE.  See the GNU General Public License for more\r
+    details. You should have received a copy of the GNU General Public License\r
+    and the FreeRTOS license exception along with FreeRTOS; if not itcan be\r
+    viewed here: http://www.freertos.org/a00114.html and also obtained by\r
+    writing to Real Time Engineers Ltd., contact details for whom are available\r
+    on the FreeRTOS WEB site.\r
+\r
+    1 tab == 4 spaces!\r
+\r
+    ***************************************************************************\r
+     *                                                                       *\r
+     *    Having a problem?  Start by reading the FAQ "My application does   *\r
+     *    not run, what could be wrong?"                                     *\r
+     *                                                                       *\r
+     *    http://www.FreeRTOS.org/FAQHelp.html                               *\r
+     *                                                                       *\r
+    ***************************************************************************\r
+\r
+\r
+    http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
+    license and Real Time Engineers Ltd. contact details.\r
+\r
+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+    including FreeRTOS+Trace - an indispensable productivity tool, and our new\r
+    fully thread aware and reentrant UDP/IP stack.\r
+\r
+    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
+    Integrity Systems, who sell the code with commercial support,\r
+    indemnification and middleware, under the OpenRTOS brand.\r
+\r
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+    engineered and independently SIL3 certified version for use in safety and\r
+    mission critical applications that require provable dependability.\r
+*/\r
+\r
+/* FreeRTOS includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Standard includes. */\r
+#include <stdint.h>\r
+#include <stdio.h>\r
+#include <stdlib.h>\r
+#include <string.h>\r
+\r
+/* FreeRTOS+CLI includes. */\r
+#include "FreeRTOS_CLI.h"\r
+\r
+/* File system includes. */\r
+#include "fat_sl.h"\r
+#include "api_mdriver_ram.h"\r
+\r
+#ifdef _WINDOWS_\r
+       #define snprintf _snprintf\r
+#endif\r
+\r
+#define cliNEW_LINE            "\r\n"\r
+\r
+/*******************************************************************************\r
+ * See the URL in the comments within main.c for the location of the online\r
+ * documentation.\r
+ ******************************************************************************/\r
+\r
+/*\r
+ * Print out information on a single file.\r
+ */\r
+static void prvCreateFileInfoString( int8_t *pcBuffer, F_FIND *pxFindStruct );\r
+\r
+/*\r
+ * Copies an existing file into a newly created file.\r
+ */\r
+static portBASE_TYPE prvPerformCopy( int8_t *pcSourceFile,\r
+                                                       int32_t lSourceFileLength,\r
+                                                       int8_t *pcDestinationFile,\r
+                                                       int8_t *pxWriteBuffer,\r
+                                                       size_t xWriteBufferLen );\r
+\r
+/*\r
+ * Implements the DIR command.\r
+ */\r
+static portBASE_TYPE prvDIRCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString );\r
+\r
+/*\r
+ * Implements the CD command.\r
+ */\r
+static portBASE_TYPE prvCDCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString );\r
+\r
+/*\r
+ * Implements the DEL command.\r
+ */\r
+static portBASE_TYPE prvDELCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString );\r
+\r
+/*\r
+ * Implements the TYPE command.\r
+ */\r
+static portBASE_TYPE prvTYPECommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString );\r
+\r
+/*\r
+ * Implements the COPY command.\r
+ */\r
+static portBASE_TYPE prvCOPYCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString );\r
+\r
+/* Structure that defines the DIR command line command, which lists all the\r
+files in the current directory. */\r
+static const CLI_Command_Definition_t xDIR =\r
+{\r
+       ( const int8_t * const ) "dir", /* The command string to type. */\r
+       ( const int8_t * const ) "\r\ndir:\r\n Lists the files in the current directory\r\n",\r
+       prvDIRCommand, /* The function to run. */\r
+       0 /* No parameters are expected. */\r
+};\r
+\r
+/* Structure that defines the CD command line command, which changes the\r
+working directory. */\r
+static const CLI_Command_Definition_t xCD =\r
+{\r
+       ( const int8_t * const ) "cd", /* The command string to type. */\r
+       ( const int8_t * const ) "\r\ncd <dir name>:\r\n Changes the working directory\r\n",\r
+       prvCDCommand, /* The function to run. */\r
+       1 /* One parameter is expected. */\r
+};\r
+\r
+/* Structure that defines the TYPE command line command, which prints the\r
+contents of a file to the console. */\r
+static const CLI_Command_Definition_t xTYPE =\r
+{\r
+       ( const int8_t * const ) "type", /* The command string to type. */\r
+       ( const int8_t * const ) "\r\ntype <filename>:\r\n Prints file contents to the terminal\r\n",\r
+       prvTYPECommand, /* The function to run. */\r
+       1 /* One parameter is expected. */\r
+};\r
+\r
+/* Structure that defines the DEL command line command, which deletes a file. */\r
+static const CLI_Command_Definition_t xDEL =\r
+{\r
+       ( const int8_t * const ) "del", /* The command string to type. */\r
+       ( const int8_t * const ) "\r\ndel <filename>:\r\n deletes a file or directory\r\n",\r
+       prvDELCommand, /* The function to run. */\r
+       1 /* One parameter is expected. */\r
+};\r
+\r
+/* Structure that defines the COPY command line command, which deletes a file. */\r
+static const CLI_Command_Definition_t xCOPY =\r
+{\r
+       ( const int8_t * const ) "copy", /* The command string to type. */\r
+       ( const int8_t * const ) "\r\ncopy <source file> <dest file>:\r\n Copies <source file> to <dest file>\r\n",\r
+       prvCOPYCommand, /* The function to run. */\r
+       2 /* Two parameters are expected. */\r
+};\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void vRegisterFileSystemCLICommands( void )\r
+{\r
+       /* Register all the command line commands defined immediately above. */\r
+       FreeRTOS_CLIRegisterCommand( &xDIR );\r
+       FreeRTOS_CLIRegisterCommand( &xCD );\r
+       FreeRTOS_CLIRegisterCommand( &xTYPE );\r
+       FreeRTOS_CLIRegisterCommand( &xDEL );\r
+       FreeRTOS_CLIRegisterCommand( &xCOPY );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static portBASE_TYPE prvTYPECommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString )\r
+{\r
+int8_t *pcParameter;\r
+portBASE_TYPE xParameterStringLength, xReturn = pdTRUE;\r
+static F_FILE *pxFile = NULL;\r
+int iChar;\r
+size_t xByte;\r
+size_t xColumns = 50U;\r
+\r
+       /* Ensure there is always a null terminator after each character written. */\r
+       memset( pcWriteBuffer, 0x00, xWriteBufferLen );\r
+\r
+       /* Ensure the buffer leaves space for the \r\n. */\r
+       configASSERT( xWriteBufferLen > ( strlen( cliNEW_LINE ) * 2 ) );\r
+       xWriteBufferLen -= strlen( cliNEW_LINE );\r
+\r
+       if( xWriteBufferLen < xColumns )\r
+       {\r
+               /* Ensure the loop that uses xColumns as an end condition does not\r
+               write off the end of the buffer. */\r
+               xColumns = xWriteBufferLen;\r
+       }\r
+\r
+       if( pxFile == NULL )\r
+       {\r
+               /* The file has not been opened yet.  Find the file name. */\r
+               pcParameter = ( int8_t * ) FreeRTOS_CLIGetParameter\r
+                                                                       (\r
+                                                                               pcCommandString,                /* The command string itself. */\r
+                                                                               1,                                              /* Return the first parameter. */\r
+                                                                               &xParameterStringLength /* Store the parameter string length. */\r
+                                                                       );\r
+\r
+               /* Sanity check something was returned. */\r
+               configASSERT( pcParameter );\r
+\r
+               /* Attempt to open the requested file. */\r
+               pxFile = f_open( ( const char * ) pcParameter, "r" );\r
+       }\r
+\r
+       if( pxFile != NULL )\r
+       {\r
+               /* Read the next chunk of data from the file. */\r
+               for( xByte = 0; xByte < xColumns; xByte++ )\r
+               {\r
+                       iChar = f_getc( pxFile );\r
+\r
+                       if( iChar == -1 )\r
+                       {\r
+                               /* No more characters to return. */\r
+                               f_close( pxFile );\r
+                               pxFile = NULL;\r
+                               break;\r
+                       }\r
+                       else\r
+                       {\r
+                               pcWriteBuffer[ xByte ] = ( int8_t ) iChar;\r
+                       }\r
+               }\r
+       }\r
+\r
+       if( pxFile == NULL )\r
+       {\r
+               /* Either the file was not opened, or all the data from the file has\r
+               been returned and the file is now closed. */\r
+               xReturn = pdFALSE;\r
+       }\r
+\r
+       strcat( ( char * ) pcWriteBuffer, cliNEW_LINE );\r
+\r
+       return xReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static portBASE_TYPE prvCDCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString )\r
+{\r
+int8_t *pcParameter;\r
+portBASE_TYPE xParameterStringLength;\r
+unsigned char ucReturned;\r
+size_t xStringLength;\r
+\r
+       /* Obtain the parameter string. */\r
+       pcParameter = ( int8_t * ) FreeRTOS_CLIGetParameter\r
+                                                               (\r
+                                                                       pcCommandString,                /* The command string itself. */\r
+                                                                       1,                                              /* Return the first parameter. */\r
+                                                                       &xParameterStringLength /* Store the parameter string length. */\r
+                                                               );\r
+\r
+       /* Sanity check something was returned. */\r
+       configASSERT( pcParameter );\r
+\r
+       /* Attempt to move to the requested directory. */\r
+       ucReturned = f_chdir( ( char * ) pcParameter );\r
+\r
+       if( ucReturned == F_NO_ERROR )\r
+       {\r
+               sprintf( ( char * ) pcWriteBuffer, "In: " );\r
+               xStringLength = strlen( ( const char * ) pcWriteBuffer );\r
+               f_getcwd( ( char * ) &( pcWriteBuffer[ xStringLength ] ), ( unsigned char ) ( xWriteBufferLen - xStringLength ) );\r
+       }\r
+       else\r
+       {\r
+               sprintf( ( char * ) pcWriteBuffer, "Error" );\r
+       }\r
+\r
+       strcat( ( char * ) pcWriteBuffer, cliNEW_LINE );\r
+\r
+       return pdFALSE;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static portBASE_TYPE prvDIRCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString )\r
+{\r
+static F_FIND *pxFindStruct = NULL;\r
+unsigned char ucReturned;\r
+portBASE_TYPE xReturn = pdFALSE;\r
+\r
+       /* This assumes pcWriteBuffer is long enough. */\r
+       ( void ) pcCommandString;\r
+\r
+       /* Ensure the buffer leaves space for the \r\n. */\r
+       configASSERT( xWriteBufferLen > ( strlen( cliNEW_LINE ) * 2 ) );\r
+       xWriteBufferLen -= strlen( cliNEW_LINE );\r
+\r
+       if( pxFindStruct == NULL )\r
+       {\r
+               /* This is the first time this function has been executed since the Dir\r
+               command was run.  Create the find structure. */\r
+               pxFindStruct = ( F_FIND * ) pvPortMalloc( sizeof( F_FIND ) );\r
+\r
+               if( pxFindStruct != NULL )\r
+               {\r
+                       ucReturned = f_findfirst( "*.*", pxFindStruct );\r
+\r
+                       if( ucReturned == F_NO_ERROR )\r
+                       {\r
+                               prvCreateFileInfoString( pcWriteBuffer, pxFindStruct );\r
+                               xReturn = pdPASS;\r
+                       }\r
+                       else\r
+                       {\r
+                               snprintf( ( char * ) pcWriteBuffer, xWriteBufferLen, "Error: f_findfirst() failed." );\r
+                       }\r
+               }\r
+               else\r
+               {\r
+                       snprintf( ( char * ) pcWriteBuffer, xWriteBufferLen, "Failed to allocate RAM (using heap_4.c will prevent fragmentation)." );\r
+               }\r
+       }\r
+       else\r
+       {\r
+               /* The find struct has already been created.  Find the next file in\r
+               the directory. */\r
+               ucReturned = f_findnext( pxFindStruct );\r
+\r
+               if( ucReturned == F_NO_ERROR )\r
+               {\r
+                       prvCreateFileInfoString( pcWriteBuffer, pxFindStruct );\r
+                       xReturn = pdPASS;\r
+               }\r
+               else\r
+               {\r
+                       /* There are no more files.  Free the find structure. */\r
+                       vPortFree( pxFindStruct );\r
+                       pxFindStruct = NULL;\r
+\r
+                       /* No string to return. */\r
+                       pcWriteBuffer[ 0 ] = 0x00;\r
+               }\r
+       }\r
+\r
+       strcat( ( char * ) pcWriteBuffer, cliNEW_LINE );\r
+\r
+       return xReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static portBASE_TYPE prvDELCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString )\r
+{\r
+int8_t *pcParameter;\r
+portBASE_TYPE xParameterStringLength;\r
+unsigned char ucReturned;\r
+\r
+       /* This function assumes xWriteBufferLen is large enough! */\r
+       ( void ) xWriteBufferLen;\r
+\r
+       /* Obtain the parameter string. */\r
+       pcParameter = ( int8_t * ) FreeRTOS_CLIGetParameter\r
+                                                               (\r
+                                                                       pcCommandString,                /* The command string itself. */\r
+                                                                       1,                                              /* Return the first parameter. */\r
+                                                                       &xParameterStringLength /* Store the parameter string length. */\r
+                                                               );\r
+\r
+       /* Sanity check something was returned. */\r
+       configASSERT( pcParameter );\r
+\r
+       /* Attempt to delete the file. */\r
+       ucReturned = f_delete( ( const char * ) pcParameter );\r
+\r
+       if( ucReturned == F_NO_ERROR )\r
+       {\r
+               sprintf( ( char * ) pcWriteBuffer, "%s was deleted", pcParameter );\r
+       }\r
+       else\r
+       {\r
+               sprintf( ( char * ) pcWriteBuffer, "Error" );\r
+       }\r
+\r
+       strcat( ( char * ) pcWriteBuffer, cliNEW_LINE );\r
+\r
+       return pdFALSE;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static portBASE_TYPE prvCOPYCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString )\r
+{\r
+int8_t *pcSourceFile, *pcDestinationFile;\r
+portBASE_TYPE xParameterStringLength;\r
+long lSourceLength, lDestinationLength = 0;\r
+\r
+       /* Obtain the name of the destination file. */\r
+       pcDestinationFile = ( int8_t * ) FreeRTOS_CLIGetParameter\r
+                                                               (\r
+                                                                       pcCommandString,                /* The command string itself. */\r
+                                                                       2,                                              /* Return the second parameter. */\r
+                                                                       &xParameterStringLength /* Store the parameter string length. */\r
+                                                               );\r
+\r
+       /* Sanity check something was returned. */\r
+       configASSERT( pcDestinationFile );\r
+\r
+       /* Obtain the name of the source file. */\r
+       pcSourceFile = ( int8_t * ) FreeRTOS_CLIGetParameter\r
+                                                               (\r
+                                                                       pcCommandString,                /* The command string itself. */\r
+                                                                       1,                                              /* Return the first parameter. */\r
+                                                                       &xParameterStringLength /* Store the parameter string length. */\r
+                                                               );\r
+\r
+       /* Sanity check something was returned. */\r
+       configASSERT( pcSourceFile );\r
+\r
+       /* Terminate the string. */\r
+       pcSourceFile[ xParameterStringLength ] = 0x00;\r
+\r
+       /* See if the source file exists, obtain its length if it does. */\r
+       lSourceLength = f_filelength( ( const char * ) pcSourceFile );\r
+\r
+       if( lSourceLength == 0 )\r
+       {\r
+               sprintf( ( char * ) pcWriteBuffer, "Source file does not exist" );\r
+       }\r
+       else\r
+       {\r
+               /* See if the destination file exists. */\r
+               lDestinationLength = f_filelength( ( const char * ) pcDestinationFile );\r
+\r
+               if( lDestinationLength != 0 )\r
+               {\r
+                       sprintf( ( char * ) pcWriteBuffer, "Error: Destination file already exists" );\r
+               }\r
+       }\r
+\r
+       /* Continue only if the source file exists and the destination file does\r
+       not exist. */\r
+       if( ( lSourceLength != 0 ) && ( lDestinationLength == 0 ) )\r
+       {\r
+               if( prvPerformCopy( pcSourceFile, lSourceLength, pcDestinationFile, pcWriteBuffer, xWriteBufferLen ) == pdPASS )\r
+               {\r
+                       sprintf( ( char * ) pcWriteBuffer, "Copy made" );\r
+               }\r
+               else\r
+               {\r
+                       sprintf( ( char * ) pcWriteBuffer, "Error during copy" );\r
+               }\r
+       }\r
+\r
+       strcat( ( char * ) pcWriteBuffer, cliNEW_LINE );\r
+\r
+       return pdFALSE;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static portBASE_TYPE prvPerformCopy( int8_t *pcSourceFile,\r
+                                                       int32_t lSourceFileLength,\r
+                                                       int8_t *pcDestinationFile,\r
+                                                       int8_t *pxWriteBuffer,\r
+                                                       size_t xWriteBufferLen )\r
+{\r
+int32_t lBytesRead = 0, lBytesToRead, lBytesRemaining;\r
+F_FILE *pxFile;\r
+portBASE_TYPE xReturn = pdPASS;\r
+\r
+       /* NOTE:  Error handling has been omitted for clarity. */\r
+\r
+       while( lBytesRead < lSourceFileLength )\r
+       {\r
+               /* How many bytes are left? */\r
+               lBytesRemaining = lSourceFileLength - lBytesRead;\r
+\r
+               /* How many bytes should be read this time around the loop.  Can't\r
+               read more bytes than will fit into the buffer. */\r
+               if( lBytesRemaining > ( long ) xWriteBufferLen )\r
+               {\r
+                       lBytesToRead = ( long ) xWriteBufferLen;\r
+               }\r
+               else\r
+               {\r
+                       lBytesToRead = lBytesRemaining;\r
+               }\r
+\r
+               /* Open the source file, seek past the data that has already been\r
+               read from the file, read the next block of data, then close the\r
+               file again so the destination file can be opened. */\r
+               pxFile = f_open( ( const char * ) pcSourceFile, "r" );\r
+               if( pxFile != NULL )\r
+               {\r
+                       f_seek( pxFile, lBytesRead, F_SEEK_SET );\r
+                       f_read( pxWriteBuffer, lBytesToRead, 1, pxFile );\r
+                       f_close( pxFile );\r
+               }\r
+               else\r
+               {\r
+                       xReturn = pdFAIL;\r
+                       break;\r
+               }\r
+\r
+               /* Open the destination file and write the block of data to the end of\r
+               the file. */\r
+               pxFile = f_open( ( const char * ) pcDestinationFile, "a" );\r
+               if( pxFile != NULL )\r
+               {\r
+                       f_write( pxWriteBuffer, lBytesToRead, 1, pxFile );\r
+                       f_close( pxFile );\r
+               }\r
+               else\r
+               {\r
+                       xReturn = pdFAIL;\r
+                       break;\r
+               }\r
+\r
+               lBytesRead += lBytesToRead;\r
+       }\r
+\r
+       return xReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvCreateFileInfoString( int8_t *pcBuffer, F_FIND *pxFindStruct )\r
+{\r
+const char *pcWritableFile = "writable file", *pcReadOnlyFile = "read only file", *pcDirectory = "directory";\r
+const char * pcAttrib;\r
+\r
+       /* Point pcAttrib to a string that describes the file. */\r
+       if( ( pxFindStruct->attr & F_ATTR_DIR ) != 0 )\r
+       {\r
+               pcAttrib = pcDirectory;\r
+       }\r
+       else if( pxFindStruct->attr & F_ATTR_READONLY )\r
+       {\r
+               pcAttrib = pcReadOnlyFile;\r
+       }\r
+       else\r
+       {\r
+               pcAttrib = pcWritableFile;\r
+       }\r
+\r
+       /* Create a string that includes the file name, the file size and the\r
+       attributes string. */\r
+       sprintf( ( char * ) pcBuffer, "%s [%s] [size=%d]", pxFindStruct->filename, pcAttrib, ( int ) pxFindStruct->filesize );\r
+}\r
diff --git a/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo/Full-Demo/File-system-demo.c b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo/Full-Demo/File-system-demo.c
new file mode 100644 (file)
index 0000000..d7ee184
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo/Full-Demo/File-system-demo.c
@@ -0,0 +1,384 @@
+/*\r
+    FreeRTOS V7.4.2 - Copyright (C) 2013 Real Time Engineers Ltd.\r
+\r
+    FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME.  PLEASE VISIT\r
+    http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+    ***************************************************************************\r
+     *                                                                       *\r
+     *    FreeRTOS tutorial books are available in pdf and paperback.        *\r
+     *    Complete, revised, and edited pdf reference manuals are also       *\r
+     *    available.                                                         *\r
+     *                                                                       *\r
+     *    Purchasing FreeRTOS documentation will not only help you, by       *\r
+     *    ensuring you get running as quickly as possible and with an        *\r
+     *    in-depth knowledge of how to use FreeRTOS, it will also help       *\r
+     *    the FreeRTOS project to continue with its mission of providing     *\r
+     *    professional grade, cross platform, de facto standard solutions    *\r
+     *    for microcontrollers - completely free of charge!                  *\r
+     *                                                                       *\r
+     *    >>> See http://www.FreeRTOS.org/Documentation for details. <<<     *\r
+     *                                                                       *\r
+     *    Thank you for using FreeRTOS, and thank you for your support!      *\r
+     *                                                                       *\r
+    ***************************************************************************\r
+\r
+\r
+    This file is part of the FreeRTOS distribution.\r
+\r
+    FreeRTOS is free software; you can redistribute it and/or modify it under\r
+    the terms of the GNU General Public License (version 2) as published by the\r
+    Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+\r
+    >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to\r
+    distribute a combined work that includes FreeRTOS without being obliged to\r
+    provide the source code for proprietary components outside of the FreeRTOS\r
+    kernel.\r
+\r
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+    FOR A PARTICULAR PURPOSE.  See the GNU General Public License for more\r
+    details. You should have received a copy of the GNU General Public License\r
+    and the FreeRTOS license exception along with FreeRTOS; if not itcan be\r
+    viewed here: http://www.freertos.org/a00114.html and also obtained by\r
+    writing to Real Time Engineers Ltd., contact details for whom are available\r
+    on the FreeRTOS WEB site.\r
+\r
+    1 tab == 4 spaces!\r
+\r
+    ***************************************************************************\r
+     *                                                                       *\r
+     *    Having a problem?  Start by reading the FAQ "My application does   *\r
+     *    not run, what could be wrong?"                                     *\r
+     *                                                                       *\r
+     *    http://www.FreeRTOS.org/FAQHelp.html                               *\r
+     *                                                                       *\r
+    ***************************************************************************\r
+\r
+\r
+    http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
+    license and Real Time Engineers Ltd. contact details.\r
+\r
+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+    including FreeRTOS+Trace - an indispensable productivity tool, and our new\r
+    fully thread aware and reentrant UDP/IP stack.\r
+\r
+    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
+    Integrity Systems, who sell the code with commercial support,\r
+    indemnification and middleware, under the OpenRTOS brand.\r
+\r
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+    engineered and independently SIL3 certified version for use in safety and\r
+    mission critical applications that require provable dependability.\r
+*/\r
+\r
+/*******************************************************************************\r
+ * See the URL in the comments within main.c for the location of the online\r
+ * documentation.\r
+ ******************************************************************************/\r
+\r
+/* Standard includes. */\r
+#include <stdio.h>\r
+#include <string.h>\r
+\r
+/* FreeRTOS includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* File system includes. */\r
+#include "fat_sl.h"\r
+#include "api_mdriver_ram.h"\r
+\r
+/* 8.3 format, plus null terminator. */\r
+#define fsMAX_FILE_NAME_LEN                            13\r
+\r
+/* The number of bytes read/written to the example files at a time. */\r
+#define fsRAM_BUFFER_SIZE                              200\r
+\r
+/* The number of bytes written to the file that uses f_putc() and f_getc(). */\r
+#define fsPUTC_FILE_SIZE                               100\r
+\r
+/* The number of files created in root. */\r
+#define fsROOT_FILES                                   3\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Creates and verifies different files on the volume, demonstrating the use of\r
+ * various different API functions.\r
+ */\r
+void vCreateAndVerifySampleFiles( void );\r
+\r
+/*\r
+ * Create a set of example files in the root directory of the volume using\r
+ * f_write().\r
+ */\r
+static void prvCreateDemoFilesUsing_f_write( void );\r
+\r
+/*\r
+ * Use f_read() to read back and verify the files that were created by\r
+ * prvCreateDemoFilesUsing_f_write().\r
+ */\r
+static void prvVerifyDemoFileUsing_f_read( void );\r
+\r
+/*\r
+ * Create an example file in a sub-directory using f_putc().\r
+ */\r
+static void prvCreateDemoFileUsing_f_putc( void );\r
+\r
+/*\r
+ * Use f_getc() to read back and verify the file that was created by\r
+ * prvCreateDemoFileUsing_f_putc().\r
+ */\r
+static void prvVerifyDemoFileUsing_f_getc( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* A buffer used to both create content to write to disk, and read content back\r
+from a disk.  Note there is no mutual exclusion on this buffer. */\r
+static char cRAMBuffer[ fsRAM_BUFFER_SIZE ];\r
+\r
+/* Names of directories that are created. */\r
+static const char *pcRoot = "/", *pcDirectory1 = "SUB1", *pcDirectory2 = "SUB2", *pcFullPath = "/SUB1/SUB2";\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void vCreateAndVerifySampleFiles( void )\r
+{\r
+unsigned char ucStatus;\r
+\r
+       /* First create the volume. */\r
+       ucStatus = f_initvolume( ram_initfunc );\r
+\r
+       /* It is expected that the volume is not formatted. */\r
+       if( ucStatus == F_ERR_NOTFORMATTED )\r
+       {\r
+               /* Format the created volume. */\r
+               ucStatus = f_format( F_FAT12_MEDIA );\r
+       }\r
+\r
+       if( ucStatus == F_NO_ERROR )\r
+       {\r
+               /* Create a set of files using f_write(). */\r
+               prvCreateDemoFilesUsing_f_write();\r
+\r
+               /* Read back and verify the files that were created using f_write(). */\r
+               prvVerifyDemoFileUsing_f_read();\r
+\r
+               /* Create sub directories two deep then create a file using putc. */\r
+               prvCreateDemoFileUsing_f_putc();\r
+\r
+               /* Read back and verify the file created by\r
+               prvCreateDemoFileUsing_f_putc(). */\r
+               prvVerifyDemoFileUsing_f_getc();\r
+       }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvCreateDemoFilesUsing_f_write( void )\r
+{\r
+portBASE_TYPE xFileNumber, xWriteNumber;\r
+char cFileName[ fsMAX_FILE_NAME_LEN ];\r
+long lItemsWritten;\r
+F_FILE *pxFile;\r
+\r
+       /* Create fsROOT_FILES files.  Each created file will be\r
+       ( xFileNumber * fsRAM_BUFFER_SIZE ) bytes in length, and filled\r
+       with a different repeating character. */\r
+       for( xFileNumber = 1; xFileNumber <= fsROOT_FILES; xFileNumber++ )\r
+       {\r
+               /* Generate a file name. */\r
+               sprintf( cFileName, "root%03d.txt", ( int ) xFileNumber );\r
+\r
+               /* Obtain the current working directory and print out the file name and\r
+               the     directory into which the file is being written. */\r
+               f_getcwd( cRAMBuffer, fsRAM_BUFFER_SIZE );\r
+               printf( "Creating file %s in %s\r\n", cFileName, cRAMBuffer );\r
+\r
+               /* Open the file, creating the file if it does not already exist. */\r
+               pxFile = f_open( cFileName, "w" );\r
+               configASSERT( pxFile );\r
+\r
+               /* Fill the RAM buffer with data that will be written to the file.  This\r
+               is just a repeating ascii character that indicates the file number. */\r
+               memset( cRAMBuffer, ( int ) ( '0' + xFileNumber ), fsRAM_BUFFER_SIZE );\r
+\r
+               /* Write the RAM buffer to the opened file a number of times.  The\r
+               number of times the RAM buffer is written to the file depends on the\r
+               file number, so the length of each created file will be different. */\r
+               for( xWriteNumber = 0; xWriteNumber < xFileNumber; xWriteNumber++ )\r
+               {\r
+                       lItemsWritten = f_write( cRAMBuffer, fsRAM_BUFFER_SIZE, 1, pxFile );\r
+                       configASSERT( lItemsWritten == 1 );\r
+               }\r
+\r
+               /* Close the file so another file can be created. */\r
+               f_close( pxFile );\r
+       }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvVerifyDemoFileUsing_f_read( void )\r
+{\r
+portBASE_TYPE xFileNumber, xReadNumber;\r
+char cFileName[ fsMAX_FILE_NAME_LEN ];\r
+long lItemsRead, lChar;\r
+F_FILE *pxFile;\r
+\r
+       /* Read back the files that were created by\r
+       prvCreateDemoFilesUsing_f_write(). */\r
+       for( xFileNumber = 1; xFileNumber <= fsROOT_FILES; xFileNumber++ )\r
+       {\r
+               /* Generate the file name. */\r
+               sprintf( cFileName, "root%03d.txt", ( int ) xFileNumber );\r
+\r
+               /* Obtain the current working directory and print out the file name and\r
+               the     directory from which the file is being read. */\r
+               f_getcwd( cRAMBuffer, fsRAM_BUFFER_SIZE );\r
+               printf( "Reading file %s from %s\r\n", cFileName, cRAMBuffer );\r
+\r
+               /* Open the file for reading. */\r
+               pxFile = f_open( cFileName, "r" );\r
+               configASSERT( pxFile );\r
+\r
+               /* Read the file into the RAM buffer, checking the file contents are as\r
+               expected.  The size of the file depends on the file number. */\r
+               for( xReadNumber = 0; xReadNumber < xFileNumber; xReadNumber++ )\r
+               {\r
+                       /* Start with the RAM buffer clear. */\r
+                       memset( cRAMBuffer, 0x00, fsRAM_BUFFER_SIZE );\r
+\r
+                       lItemsRead = f_read( cRAMBuffer, fsRAM_BUFFER_SIZE, 1, pxFile );\r
+                       configASSERT( lItemsRead == 1 );\r
+\r
+                       /* Check the RAM buffer is filled with the expected data.  Each\r
+                       file contains a different repeating ascii character that indicates\r
+                       the number of the file. */\r
+                       for( lChar = 0; lChar < fsRAM_BUFFER_SIZE; lChar++ )\r
+                       {\r
+                               configASSERT( cRAMBuffer[ lChar ] == ( '0' + ( char ) xFileNumber ) );\r
+                       }\r
+               }\r
+\r
+               /* Close the file. */\r
+               f_close( pxFile );\r
+       }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvCreateDemoFileUsing_f_putc( void )\r
+{\r
+unsigned char ucReturn;\r
+int iByte, iReturned;\r
+F_FILE *pxFile;\r
+char cFileName[ fsMAX_FILE_NAME_LEN ];\r
+\r
+       /* Obtain and print out the working directory. */\r
+       f_getcwd( cRAMBuffer, fsRAM_BUFFER_SIZE );\r
+       printf( "In directory %s\r\n", cRAMBuffer );\r
+\r
+       /* Create a sub directory. */\r
+       ucReturn = f_mkdir( pcDirectory1 );\r
+       configASSERT( ucReturn == F_NO_ERROR );\r
+\r
+       /* Move into the created sub-directory. */\r
+       ucReturn = f_chdir( pcDirectory1 );\r
+       configASSERT( ucReturn == F_NO_ERROR );\r
+\r
+       /* Obtain and print out the working directory. */\r
+       f_getcwd( cRAMBuffer, fsRAM_BUFFER_SIZE );\r
+       printf( "In directory %s\r\n", cRAMBuffer );\r
+\r
+       /* Create a subdirectory in the new directory. */\r
+       ucReturn = f_mkdir( pcDirectory2 );\r
+       configASSERT( ucReturn == F_NO_ERROR );\r
+\r
+       /* Move into the directory just created - now two directories down from\r
+       the root. */\r
+       ucReturn = f_chdir( pcDirectory2 );\r
+       configASSERT( ucReturn == F_NO_ERROR );\r
+\r
+       /* Obtain and print out the working directory. */\r
+       f_getcwd( cRAMBuffer, fsRAM_BUFFER_SIZE );\r
+       printf( "In directory %s\r\n", cRAMBuffer );\r
+       configASSERT( strcmp( ( const char * ) cRAMBuffer, pcFullPath ) == 0 );\r
+\r
+       /* Generate the file name. */\r
+       sprintf( cFileName, "%s.txt", pcDirectory2 );\r
+\r
+       /* Print out the file name and the directory into which the file is being\r
+       written. */\r
+       printf( "Writing file %s in %s\r\n", cFileName, cRAMBuffer );\r
+\r
+       pxFile = f_open( cFileName, "w" );\r
+\r
+       /* Create a file 1 byte at a time.  The file is filled with incrementing\r
+       ascii characters starting from '0'. */\r
+       for( iByte = 0; iByte < fsPUTC_FILE_SIZE; iByte++ )\r
+       {\r
+               iReturned = f_putc( ( ( int ) '0' + iByte ), pxFile );\r
+               configASSERT( iReturned ==  ( ( int ) '0' + iByte ) );\r
+       }\r
+\r
+       /* Finished so close the file. */\r
+       f_close( pxFile );\r
+\r
+       /* Move back to the root directory. */\r
+       ucReturn = f_chdir( "../.." );\r
+       configASSERT( ucReturn == F_NO_ERROR );\r
+\r
+       /* Obtain and print out the working directory. */\r
+       f_getcwd( cRAMBuffer, fsRAM_BUFFER_SIZE );\r
+       printf( "Back in root directory %s\r\n", cRAMBuffer );\r
+       configASSERT( strcmp( ( const char * ) cRAMBuffer, pcRoot ) == 0 );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvVerifyDemoFileUsing_f_getc( void )\r
+{\r
+unsigned char ucReturn;\r
+int iByte, iReturned;\r
+F_FILE *pxFile;\r
+char cFileName[ fsMAX_FILE_NAME_LEN ];\r
+\r
+       /* Move into the directory in which the file was created. */\r
+       ucReturn = f_chdir( pcFullPath );\r
+       configASSERT( ucReturn == F_NO_ERROR );\r
+\r
+       /* Obtain and print out the working directory. */\r
+       f_getcwd( cRAMBuffer, fsRAM_BUFFER_SIZE );\r
+       printf( "Back in directory %s\r\n", cRAMBuffer );\r
+       configASSERT( strcmp( ( const char * ) cRAMBuffer, pcFullPath ) == 0 );\r
+\r
+       /* Generate the file name. */\r
+       sprintf( cFileName, "%s.txt", pcDirectory2 );\r
+\r
+       /* Print out the file name and the directory from which the file is being\r
+       read. */\r
+       printf( "Reading file %s in %s\r\n", cFileName, cRAMBuffer );\r
+\r
+       /* This time the file is opened for reading. */\r
+       pxFile = f_open( cFileName, "r" );\r
+\r
+       /* Read the file 1 byte at a time. */\r
+       for( iByte = 0; iByte < fsPUTC_FILE_SIZE; iByte++ )\r
+       {\r
+               iReturned = f_getc( pxFile );\r
+               configASSERT( iReturned ==  ( ( int ) '0' + iByte ) );\r
+       }\r
+\r
+       /* Finished so close the file. */\r
+       f_close( pxFile );\r
+\r
+       /* Move back to the root directory. */\r
+       ucReturn = f_chdir( "../.." );\r
+       configASSERT( ucReturn == F_NO_ERROR );\r
+\r
+       /* Obtain and print out the working directory. */\r
+       f_getcwd( cRAMBuffer, fsRAM_BUFFER_SIZE );\r
+       printf( "Back in root directory %s\r\n", cRAMBuffer );\r
+}\r
+\r
+\r
+\r
+\r
diff --git a/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo/Full-Demo/FreeRTOS-Plus-FAT-SL-Source/ReadMe.txt b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo/Full-Demo/FreeRTOS-Plus-FAT-SL-Source/ReadMe.txt
new file mode 100644 (file)
index 0000000..d19749f
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo/Full-Demo/FreeRTOS-Plus-FAT-SL-Source/ReadMe.txt
@@ -0,0 +1 @@
+Run the CreateProjectDirectoryStructure.bat batch file to populate this directory before building the demo.
\ No newline at end of file
diff --git a/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo/Full-Demo/ReadMe.txt b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo/Full-Demo/ReadMe.txt
new file mode 100644 (file)
index 0000000..d19749f
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo/Full-Demo/ReadMe.txt
@@ -0,0 +1 @@
+Run the CreateProjectDirectoryStructure.bat batch file to populate this directory before building the demo.
\ No newline at end of file
diff --git a/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo/Full-Demo/Sample-CLI-commands.c b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo/Full-Demo/Sample-CLI-commands.c
new file mode 100644 (file)
index 0000000..32381db
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo/Full-Demo/Sample-CLI-commands.c
@@ -0,0 +1,426 @@
+/*\r
+    FreeRTOS V7.4.2 - Copyright (C) 2013 Real Time Engineers Ltd.\r
+\r
+    FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME.  PLEASE VISIT\r
+    http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+    ***************************************************************************\r
+     *                                                                       *\r
+     *    FreeRTOS tutorial books are available in pdf and paperback.        *\r
+     *    Complete, revised, and edited pdf reference manuals are also       *\r
+     *    available.                                                         *\r
+     *                                                                       *\r
+     *    Purchasing FreeRTOS documentation will not only help you, by       *\r
+     *    ensuring you get running as quickly as possible and with an        *\r
+     *    in-depth knowledge of how to use FreeRTOS, it will also help       *\r
+     *    the FreeRTOS project to continue with its mission of providing     *\r
+     *    professional grade, cross platform, de facto standard solutions    *\r
+     *    for microcontrollers - completely free of charge!                  *\r
+     *                                                                       *\r
+     *    >>> See http://www.FreeRTOS.org/Documentation for details. <<<     *\r
+     *                                                                       *\r
+     *    Thank you for using FreeRTOS, and thank you for your support!      *\r
+     *                                                                       *\r
+    ***************************************************************************\r
+\r
+\r
+    This file is part of the FreeRTOS distribution.\r
+\r
+    FreeRTOS is free software; you can redistribute it and/or modify it under\r
+    the terms of the GNU General Public License (version 2) as published by the\r
+    Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+\r
+    >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to\r
+    distribute a combined work that includes FreeRTOS without being obliged to\r
+    provide the source code for proprietary components outside of the FreeRTOS\r
+    kernel.\r
+\r
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+    FOR A PARTICULAR PURPOSE.  See the GNU General Public License for more\r
+    details. You should have received a copy of the GNU General Public License\r
+    and the FreeRTOS license exception along with FreeRTOS; if not itcan be\r
+    viewed here: http://www.freertos.org/a00114.html and also obtained by\r
+    writing to Real Time Engineers Ltd., contact details for whom are available\r
+    on the FreeRTOS WEB site.\r
+\r
+    1 tab == 4 spaces!\r
+\r
+    ***************************************************************************\r
+     *                                                                       *\r
+     *    Having a problem?  Start by reading the FAQ "My application does   *\r
+     *    not run, what could be wrong?"                                     *\r
+     *                                                                       *\r
+     *    http://www.FreeRTOS.org/FAQHelp.html                               *\r
+     *                                                                       *\r
+    ***************************************************************************\r
+\r
+\r
+    http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
+    license and Real Time Engineers Ltd. contact details.\r
+\r
+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+    including FreeRTOS+Trace - an indispensable productivity tool, and our new\r
+    fully thread aware and reentrant UDP/IP stack.\r
+\r
+    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
+    Integrity Systems, who sell the code with commercial support,\r
+    indemnification and middleware, under the OpenRTOS brand.\r
+\r
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+    engineered and independently SIL3 certified version for use in safety and\r
+    mission critical applications that require provable dependability.\r
+*/\r
+\r
+ /******************************************************************************\r
+ *\r
+ * See the following URL for information on the commands defined in this file:\r
+ * http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_UDP/Embedded_Ethernet_Examples/Ethernet_Related_CLI_Commands.shtml\r
+ *\r
+ ******************************************************************************/\r
+\r
+\r
+/* FreeRTOS includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Standard includes. */\r
+#include <stdint.h>\r
+#include <stdio.h>\r
+#include <string.h>\r
+\r
+/* FreeRTOS+CLI includes. */\r
+#include "FreeRTOS_CLI.h"\r
+\r
+#ifndef  configINCLUDE_TRACE_RELATED_CLI_COMMANDS\r
+       #define configINCLUDE_TRACE_RELATED_CLI_COMMANDS 0\r
+#endif\r
+\r
+\r
+/*\r
+ * Implements the run-time-stats command.\r
+ */\r
+static portBASE_TYPE prvTaskStatsCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString );\r
+\r
+/*\r
+ * Implements the task-stats command.\r
+ */\r
+static portBASE_TYPE prvRunTimeStatsCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString );\r
+\r
+/*\r
+ * Implements the echo-three-parameters command.\r
+ */\r
+static portBASE_TYPE prvThreeParameterEchoCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString );\r
+\r
+/*\r
+ * Implements the echo-parameters command.\r
+ */\r
+static portBASE_TYPE prvParameterEchoCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString );\r
+\r
+/*\r
+ * Implements the "trace start" and "trace stop" commands;\r
+ */\r
+#if configINCLUDE_TRACE_RELATED_CLI_COMMANDS == 1\r
+       static portBASE_TYPE prvStartStopTraceCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString );\r
+#endif\r
+\r
+/* Structure that defines the "run-time-stats" command line command.   This\r
+generates a table that shows how much run time each task has */\r
+static const CLI_Command_Definition_t xRunTimeStats =\r
+{\r
+       ( const int8_t * const ) "run-time-stats", /* The command string to type. */\r
+       ( const int8_t * const ) "\r\nrun-time-stats:\r\n Displays a table showing how much processing time each FreeRTOS task has used\r\n",\r
+       prvRunTimeStatsCommand, /* The function to run. */\r
+       0 /* No parameters are expected. */\r
+};\r
+\r
+/* Structure that defines the "task-stats" command line command.  This generates\r
+a table that gives information on each task in the system. */\r
+static const CLI_Command_Definition_t xTaskStats =\r
+{\r
+       ( const int8_t * const ) "task-stats", /* The command string to type. */\r
+       ( const int8_t * const ) "\r\ntask-stats:\r\n Displays a table showing the state of each FreeRTOS task\r\n",\r
+       prvTaskStatsCommand, /* The function to run. */\r
+       0 /* No parameters are expected. */\r
+};\r
+\r
+/* Structure that defines the "echo_3_parameters" command line command.  This\r
+takes exactly three parameters that the command simply echos back one at a\r
+time. */\r
+static const CLI_Command_Definition_t xThreeParameterEcho =\r
+{\r
+       ( const int8_t * const ) "echo-3-parameters",\r
+       ( const int8_t * const ) "\r\necho-3-parameters <param1> <param2> <param3>:\r\n Expects three parameters, echos each in turn\r\n",\r
+       prvThreeParameterEchoCommand, /* The function to run. */\r
+       3 /* Three parameters are expected, which can take any value. */\r
+};\r
+\r
+/* Structure that defines the "echo_parameters" command line command.  This\r
+takes a variable number of parameters that the command simply echos back one at\r
+a time. */\r
+static const CLI_Command_Definition_t xParameterEcho =\r
+{\r
+       ( const int8_t * const ) "echo-parameters",\r
+       ( const int8_t * const ) "\r\necho-parameters <...>:\r\n Take variable number of parameters, echos each in turn\r\n",\r
+       prvParameterEchoCommand, /* The function to run. */\r
+       -1 /* The user can enter any number of commands. */\r
+};\r
+\r
+#if configINCLUDE_TRACE_RELATED_CLI_COMMANDS == 1\r
+       /* Structure that defines the "trace" command line command.  This takes a single\r
+       parameter, which can be either "start" or "stop". */\r
+       static const CLI_Command_Definition_t xStartStopTrace =\r
+       {\r
+               ( const int8_t * const ) "trace",\r
+               ( const int8_t * const ) "\r\ntrace [start | stop]:\r\n Starts or stops a trace recording for viewing in FreeRTOS+Trace\r\n",\r
+               prvStartStopTraceCommand, /* The function to run. */\r
+               1 /* One parameter is expected.  Valid values are "start" and "stop". */\r
+       };\r
+#endif /* configINCLUDE_TRACE_RELATED_CLI_COMMANDS */\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void vRegisterSampleCLICommands( void )\r
+{\r
+       /* Register all the command line commands defined immediately above. */\r
+       FreeRTOS_CLIRegisterCommand( &xTaskStats );\r
+       FreeRTOS_CLIRegisterCommand( &xRunTimeStats );\r
+       FreeRTOS_CLIRegisterCommand( &xThreeParameterEcho );\r
+       FreeRTOS_CLIRegisterCommand( &xParameterEcho );\r
+\r
+       #if( configINCLUDE_TRACE_RELATED_CLI_COMMANDS == 1 )\r
+       {\r
+               FreeRTOS_CLIRegisterCommand( & xStartStopTrace );\r
+       }\r
+       #endif\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static portBASE_TYPE prvTaskStatsCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString )\r
+{\r
+const int8_t *const pcHeader = ( int8_t * ) "Task          State  Priority  Stack      #\r\n************************************************\r\n";\r
+\r
+       /* Remove compile time warnings about unused parameters, and check the\r
+       write buffer is not NULL.  NOTE - for simplicity, this example assumes the\r
+       write buffer length is adequate, so does not check for buffer overflows. */\r
+       ( void ) pcCommandString;\r
+       ( void ) xWriteBufferLen;\r
+       configASSERT( pcWriteBuffer );\r
+\r
+       /* Generate a table of task stats. */\r
+       strcpy( ( char * ) pcWriteBuffer, ( char * ) pcHeader );\r
+       vTaskList( pcWriteBuffer + strlen( ( char * ) pcHeader ) );\r
+\r
+       /* There is no more data to return after this single string, so return\r
+       pdFALSE. */\r
+       return pdFALSE;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static portBASE_TYPE prvRunTimeStatsCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString )\r
+{\r
+const int8_t * const pcHeader = ( int8_t * ) "Task            Abs Time      % Time\r\n****************************************\r\n";\r
+\r
+       /* Remove compile time warnings about unused parameters, and check the\r
+       write buffer is not NULL.  NOTE - for simplicity, this example assumes the\r
+       write buffer length is adequate, so does not check for buffer overflows. */\r
+       ( void ) pcCommandString;\r
+       ( void ) xWriteBufferLen;\r
+       configASSERT( pcWriteBuffer );\r
+\r
+       /* Generate a table of task stats. */\r
+       strcpy( ( char * ) pcWriteBuffer, ( char * ) pcHeader );\r
+       vTaskGetRunTimeStats( pcWriteBuffer + strlen( ( char * ) pcHeader ) );\r
+\r
+       /* There is no more data to return after this single string, so return\r
+       pdFALSE. */\r
+       return pdFALSE;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static portBASE_TYPE prvThreeParameterEchoCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString )\r
+{\r
+int8_t *pcParameter;\r
+portBASE_TYPE xParameterStringLength, xReturn;\r
+static portBASE_TYPE lParameterNumber = 0;\r
+\r
+       /* Remove compile time warnings about unused parameters, and check the\r
+       write buffer is not NULL.  NOTE - for simplicity, this example assumes the\r
+       write buffer length is adequate, so does not check for buffer overflows. */\r
+       ( void ) pcCommandString;\r
+       ( void ) xWriteBufferLen;\r
+       configASSERT( pcWriteBuffer );\r
+\r
+       if( lParameterNumber == 0 )\r
+       {\r
+               /* The first time the function is called after the command has been\r
+               entered just a header string is returned. */\r
+               sprintf( ( char * ) pcWriteBuffer, "The three parameters were:\r\n" );\r
+\r
+               /* Next time the function is called the first parameter will be echoed\r
+               back. */\r
+               lParameterNumber = 1L;\r
+\r
+               /* There is more data to be returned as no parameters have been echoed\r
+               back yet. */\r
+               xReturn = pdPASS;\r
+       }\r
+       else\r
+       {\r
+               /* Obtain the parameter string. */\r
+               pcParameter = ( int8_t * ) FreeRTOS_CLIGetParameter\r
+                                                                       (\r
+                                                                               pcCommandString,                /* The command string itself. */\r
+                                                                               lParameterNumber,               /* Return the next parameter. */\r
+                                                                               &xParameterStringLength /* Store the parameter string length. */\r
+                                                                       );\r
+\r
+               /* Sanity check something was returned. */\r
+               configASSERT( pcParameter );\r
+\r
+               /* Return the parameter string. */\r
+               memset( pcWriteBuffer, 0x00, xWriteBufferLen );\r
+               sprintf( ( char * ) pcWriteBuffer, "%d: ", ( int ) lParameterNumber );\r
+               strncat( ( char * ) pcWriteBuffer, ( const char * ) pcParameter, xParameterStringLength );\r
+               strncat( ( char * ) pcWriteBuffer, "\r\n", strlen( "\r\n" ) );\r
+\r
+               /* If this is the last of the three parameters then there are no more\r
+               strings to return after this one. */\r
+               if( lParameterNumber == 3L )\r
+               {\r
+                       /* If this is the last of the three parameters then there are no more\r
+                       strings to return after this one. */\r
+                       xReturn = pdFALSE;\r
+                       lParameterNumber = 0L;\r
+               }\r
+               else\r
+               {\r
+                       /* There are more parameters to return after this one. */\r
+                       xReturn = pdTRUE;\r
+                       lParameterNumber++;\r
+               }\r
+       }\r
+\r
+       return xReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static portBASE_TYPE prvParameterEchoCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString )\r
+{\r
+int8_t *pcParameter;\r
+portBASE_TYPE xParameterStringLength, xReturn;\r
+static portBASE_TYPE lParameterNumber = 0;\r
+\r
+       /* Remove compile time warnings about unused parameters, and check the\r
+       write buffer is not NULL.  NOTE - for simplicity, this example assumes the\r
+       write buffer length is adequate, so does not check for buffer overflows. */\r
+       ( void ) pcCommandString;\r
+       ( void ) xWriteBufferLen;\r
+       configASSERT( pcWriteBuffer );\r
+\r
+       if( lParameterNumber == 0 )\r
+       {\r
+               /* The first time the function is called after the command has been\r
+               entered just a header string is returned. */\r
+               sprintf( ( char * ) pcWriteBuffer, "The parameters were:\r\n" );\r
+\r
+               /* Next time the function is called the first parameter will be echoed\r
+               back. */\r
+               lParameterNumber = 1L;\r
+\r
+               /* There is more data to be returned as no parameters have been echoed\r
+               back yet. */\r
+               xReturn = pdPASS;\r
+       }\r
+       else\r
+       {\r
+               /* Obtain the parameter string. */\r
+               pcParameter = ( int8_t * ) FreeRTOS_CLIGetParameter\r
+                                                                       (\r
+                                                                               pcCommandString,                /* The command string itself. */\r
+                                                                               lParameterNumber,               /* Return the next parameter. */\r
+                                                                               &xParameterStringLength /* Store the parameter string length. */\r
+                                                                       );\r
+\r
+               if( pcParameter != NULL )\r
+               {\r
+                       /* Return the parameter string. */\r
+                       memset( pcWriteBuffer, 0x00, xWriteBufferLen );\r
+                       sprintf( ( char * ) pcWriteBuffer, "%d: ", ( int ) lParameterNumber );\r
+                       strncat( ( char * ) pcWriteBuffer, ( const char * ) pcParameter, xParameterStringLength );\r
+                       strncat( ( char * ) pcWriteBuffer, "\r\n", strlen( "\r\n" ) );\r
+\r
+                       /* There might be more parameters to return after this one. */\r
+                       xReturn = pdTRUE;\r
+                       lParameterNumber++;\r
+               }\r
+               else\r
+               {\r
+                       /* No more parameters were found.  Make sure the write buffer does\r
+                       not contain a valid string. */\r
+                       pcWriteBuffer[ 0 ] = 0x00;\r
+\r
+                       /* No more data to return. */\r
+                       xReturn = pdFALSE;\r
+\r
+                       /* Start over the next time this command is executed. */\r
+                       lParameterNumber = 0;\r
+               }\r
+       }\r
+\r
+       return xReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#if configINCLUDE_TRACE_RELATED_CLI_COMMANDS == 1\r
+\r
+       static portBASE_TYPE prvStartStopTraceCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString )\r
+       {\r
+       int8_t *pcParameter;\r
+       portBASE_TYPE lParameterStringLength;\r
+\r
+               /* Remove compile time warnings about unused parameters, and check the\r
+               write buffer is not NULL.  NOTE - for simplicity, this example assumes the\r
+               write buffer length is adequate, so does not check for buffer overflows. */\r
+               ( void ) pcCommandString;\r
+               ( void ) xWriteBufferLen;\r
+               configASSERT( pcWriteBuffer );\r
+\r
+               /* Obtain the parameter string. */\r
+               pcParameter = ( int8_t * ) FreeRTOS_CLIGetParameter\r
+                                                                       (\r
+                                                                               pcCommandString,                /* The command string itself. */\r
+                                                                               1,                                              /* Return the first parameter. */\r
+                                                                               &lParameterStringLength /* Store the parameter string length. */\r
+                                                                       );\r
+\r
+               /* Sanity check something was returned. */\r
+               configASSERT( pcParameter );\r
+\r
+               /* There are only two valid parameter values. */\r
+               if( strncmp( ( const char * ) pcParameter, "start", strlen( "start" ) ) == 0 )\r
+               {\r
+                       /* Start or restart the trace. */\r
+                       vTraceStop();\r
+                       vTraceClear();\r
+                       vTraceStart();\r
+\r
+                       sprintf( ( char * ) pcWriteBuffer, "Trace recording (re)started.\r\n" );\r
+               }\r
+               else if( strncmp( ( const char * ) pcParameter, "stop", strlen( "stop" ) ) == 0 )\r
+               {\r
+                       /* End the trace, if one is running. */\r
+                       vTraceStop();\r
+                       sprintf( ( char * ) pcWriteBuffer, "Stopping trace recording.\r\n" );\r
+               }\r
+               else\r
+               {\r
+                       sprintf( ( char * ) pcWriteBuffer, "Valid parameters are 'start' and 'stop'.\r\n" );\r
+               }\r
+\r
+               /* There is no more data to return after this single string, so return\r
+               pdFALSE. */\r
+               return pdFALSE;\r
+       }\r
+\r
+#endif /* configINCLUDE_TRACE_RELATED_CLI_COMMANDS */\r
diff --git a/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo/Full-Demo/UARTCommandConsole.c b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo/Full-Demo/UARTCommandConsole.c
new file mode 100644 (file)
index 0000000..4c8d235
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo/Full-Demo/UARTCommandConsole.c
@@ -0,0 +1,290 @@
+/*\r
+    FreeRTOS V7.1.0 - Copyright (C) 2011 Real Time Engineers Ltd.\r
+\r
+\r
+    ***************************************************************************\r
+     *                                                                       *\r
+     *    FreeRTOS tutorial books are available in pdf and paperback.        *\r
+     *    Complete, revised, and edited pdf reference manuals are also       *\r
+     *    available.                                                         *\r
+     *                                                                       *\r
+     *    Purchasing FreeRTOS documentation will not only help you, by       *\r
+     *    ensuring you get running as quickly as possible and with an        *\r
+     *    in-depth knowledge of how to use FreeRTOS, it will also help       *\r
+     *    the FreeRTOS project to continue with its mission of providing     *\r
+     *    professional grade, cross platform, de facto standard solutions    *\r
+     *    for microcontrollers - completely free of charge!                  *\r
+     *                                                                       *\r
+     *    >>> See http://www.FreeRTOS.org/Documentation for details. <<<     *\r
+     *                                                                       *\r
+     *    Thank you for using FreeRTOS, and thank you for your support!      *\r
+     *                                                                       *\r
+    ***************************************************************************\r
+\r
+\r
+    This file is part of the FreeRTOS distribution.\r
+\r
+    FreeRTOS is free software; you can redistribute it and/or modify it under\r
+    the terms of the GNU General Public License (version 2) as published by the\r
+    Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+    >>>NOTE<<< The modification to the GPL is included to allow you to\r
+    distribute a combined work that includes FreeRTOS without being obliged to\r
+    provide the source code for proprietary components outside of the FreeRTOS\r
+    kernel.  FreeRTOS is distributed in the hope that it will be useful, but\r
+    WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\r
+    more details. You should have received a copy of the GNU General Public\r
+    License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+    can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+    by writing to Richard Barry, contact details for whom are available on the\r
+    FreeRTOS WEB site.\r
+\r
+    1 tab == 4 spaces!\r
+\r
+    http://www.FreeRTOS.org - Documentation, latest information, license and\r
+    contact details.\r
+\r
+    http://www.SafeRTOS.com - A version that is certified for use in safety\r
+    critical systems.\r
+\r
+    http://www.OpenRTOS.com - Commercial support, development, porting,\r
+    licensing and training services.\r
+*/\r
+\r
+/* Standard includes. */\r
+#include "string.h"\r
+#include "stdio.h"\r
+\r
+/* FreeRTOS includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "queue.h"\r
+\r
+/* Driver includes. */\r
+#include "drivers/mss_uart/mss_uart.h"\r
+\r
+/* Example includes. */\r
+#include "FreeRTOS_CLI.h"\r
+#include "UARTCommandConsole.h"\r
+\r
+/* Dimensions the buffer into which input characters are placed. */\r
+#define cmdMAX_INPUT_SIZE              50\r
+\r
+/* The maximum time in ticks to wait for the UART access mutex. */\r
+#define cmdMAX_MUTEX_WAIT              ( 200 / portTICK_RATE_MS )\r
+\r
+/* Characters are only ever received slowly on the CLI so it is ok to pass\r
+received characters from the UART interrupt to the task on a queue.  This sets\r
+the length of the queue used for that purpose. */\r
+#define cmdRXED_CHARS_QUEUE_LENGTH                     ( 10 )\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * The task that implements the command console processing.\r
+ */\r
+static void prvUARTCommandConsoleTask( void *pvParameters );\r
+\r
+/*\r
+ * Ensure a previous interrupt driven Tx has completed before sending the next\r
+ * data block to the UART.
+ */\r
+static void prvSendBuffer( const uint8_t * pcBuffer, size_t xBufferLength );\r
+\r
+/*\r
+ * A UART is used for printf() output and CLI input and output.  Configure the\r
+ * UART and register prvUARTRxNotificationHandler() to handle UART Rx events.\r
+ */\r
+static void prvConfigureUART( void );\r
+static void prvUARTRxNotificationHandler( mss_uart_instance_t * this_uart );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Const messages output by the command console. */\r
+static const uint8_t * const pcWelcomeMessage = ( uint8_t * ) "\r\n\r\nFreeRTOS command server.\r\nType Help to view a list of registered commands.\r\n\r\n>";\r
+static const uint8_t * const pcEndOfOutputMessage = ( uint8_t * ) "\r\n[Press ENTER to execute the previous command again]\r\n>";\r
+static const uint8_t * const pcNewLine = ( uint8_t * ) "\r\n";\r
+\r
+/* The UART used by the CLI. */\r
+static const mss_uart_instance_t * const pxUART = &g_mss_uart1;\r
+static const IRQn_Type xUART_IRQ = UART1_IRQn;\r
+\r
+/* Because characters are received slowly (at the speed somebody can type) then\r
+it is ok to pass received characters from the Rx interrupt to the task on a\r
+queue.  This is the queue used for that purpose. */\r
+static xQueueHandle xRxedChars = NULL;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void vUARTCommandConsoleStart( uint16_t usStackSize, unsigned portBASE_TYPE uxPriority )\r
+{\r
+       /* A UART is used for printf() output and CLI input and output.  Note there\r
+       is no mutual exclusion on the UART, but the demo as it stands does not\r
+       require mutual exclusion. */\r
+       prvConfigureUART();\r
+\r
+       /* Create that task that handles the console itself. */\r
+       xTaskCreate(    prvUARTCommandConsoleTask,                      /* The task that implements the command console. */\r
+                                       ( const int8_t * const ) "CLI",         /* Text name assigned to the task.  This is just to assist debugging.  The kernel does not use this name itself. */\r
+                                       usStackSize,                                            /* The size of the stack allocated to the task. */\r
+                                       NULL,                                                           /* The parameter is not used, so NULL is passed. */\r
+                                       uxPriority,                                                     /* The priority allocated to the task. */\r
+                                       NULL );                                                         /* A handle is not required, so just pass NULL. */\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvUARTCommandConsoleTask( void *pvParameters )\r
+{\r
+int8_t cRxedChar, cInputIndex = 0, *pcOutputString;\r
+static int8_t cInputString[ cmdMAX_INPUT_SIZE ], cLastInputString[ cmdMAX_INPUT_SIZE ];\r
+portBASE_TYPE xReturned;\r
+\r
+       ( void ) pvParameters;\r
+\r
+       /* Obtain the address of the output buffer.  Note there is no mutual\r
+       exclusion on this buffer as it is assumed only one command console\r
+       interface will be used at any one time. */\r
+       pcOutputString = FreeRTOS_CLIGetOutputBuffer();\r
+\r
+       /* Send the welcome message. */\r
+       prvSendBuffer( pcWelcomeMessage, strlen( ( char * ) pcWelcomeMessage ) );\r
+\r
+       for( ;; )\r
+       {\r
+               /* Wait for the next character to arrive. */\r
+               if( xQueueReceive( xRxedChars, &cRxedChar, portMAX_DELAY ) == pdPASS )\r
+               {\r
+                       /* Echo the character back. */\r
+                       prvSendBuffer( ( uint8_t * ) &cRxedChar, sizeof( cRxedChar ) );\r
+\r
+                       /* Was it the end of the line? */\r
+                       if( cRxedChar == '\n' || cRxedChar == '\r' )\r
+                       {\r
+                               /* Just to space the output from the input. */\r
+                               prvSendBuffer( ( uint8_t * ) pcNewLine, strlen( ( char * ) pcNewLine ) );\r
+\r
+                               /* See if the command is empty, indicating that the last command is\r
+                               to be executed again. */\r
+                               if( cInputIndex == 0 )\r
+                               {\r
+                                       /* Copy the last command back into the input string. */\r
+                                       strcpy( ( char * ) cInputString, ( char * ) cLastInputString );\r
+                               }\r
+\r
+                               /* Pass the received command to the command interpreter.  The\r
+                               command interpreter is called repeatedly until it returns pdFALSE\r
+                               (indicating there is no more output) as it might generate more than\r
+                               one string. */\r
+                               do\r
+                               {\r
+                                       /* Get the next output string from the command interpreter. */\r
+                                       xReturned = FreeRTOS_CLIProcessCommand( cInputString, pcOutputString, configCOMMAND_INT_MAX_OUTPUT_SIZE );\r
+\r
+                                       /* Write the generated string to the UART. */\r
+                                       prvSendBuffer( ( uint8_t * ) pcOutputString, strlen( ( char * ) pcOutputString ) );\r
+\r
+                               } while( xReturned != pdFALSE );\r
+\r
+                               /* All the strings generated by the input command have been sent.\r
+                               Clear the input string ready to receive the next command.  Remember\r
+                               the command that was just processed first in case it is to be\r
+                               processed again. */\r
+                               strcpy( ( char * ) cLastInputString, ( char * ) cInputString );\r
+                               cInputIndex = 0;\r
+                               memset( cInputString, 0x00, cmdMAX_INPUT_SIZE );\r
+\r
+                               prvSendBuffer( ( uint8_t * ) pcEndOfOutputMessage, strlen( ( char * ) pcEndOfOutputMessage ) );\r
+                       }\r
+                       else\r
+                       {\r
+                               if( cRxedChar == '\r' )\r
+                               {\r
+                                       /* Ignore the character. */\r
+                               }\r
+                               else if( cRxedChar == '\b' )\r
+                               {\r
+                                       /* Backspace was pressed.  Erase the last character in the\r
+                                       string - if any. */\r
+                                       if( cInputIndex > 0 )\r
+                                       {\r
+                                               cInputIndex--;\r
+                                               cInputString[ cInputIndex ] = '\0';\r
+                                       }\r
+                               }\r
+                               else\r
+                               {\r
+                                       /* A character was entered.  Add it to the string\r
+                                       entered so far.  When a \n is entered the complete\r
+                                       string will be passed to the command interpreter. */\r
+                                       if( ( cRxedChar >= ' ' ) && ( cRxedChar <= '~' ) )\r
+                                       {\r
+                                               if( cInputIndex < cmdMAX_INPUT_SIZE )\r
+                                               {\r
+                                                       cInputString[ cInputIndex ] = cRxedChar;\r
+                                                       cInputIndex++;\r
+                                               }\r
+                                       }\r
+                               }\r
+                       }\r
+               }\r
+       }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSendBuffer( const uint8_t * pcBuffer, size_t xBufferLength )\r
+{\r
+const portTickType xVeryShortDelay = 2UL;\r
+\r
+       MSS_UART_irq_tx( ( mss_uart_instance_t * ) pxUART, pcBuffer, xBufferLength );\r
+\r
+       /* Ensure any previous transmissions have completed.  The default UART\r
+       interrupt does not provide an event based method of     signally the end of a Tx\r
+       - this is therefore a crude poll of the Tx end status.  Replacing the\r
+       default UART handler with one that 'gives' a semaphore when the Tx is\r
+       complete would allow this poll loop to be replaced by a simple semaphore\r
+       block. */\r
+       while( MSS_UART_tx_complete( ( mss_uart_instance_t * ) pxUART ) == pdFALSE )\r
+       {\r
+               vTaskDelay( xVeryShortDelay );\r
+       }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvConfigureUART( void )\r
+{\r
+       /* Initialise the UART which is used for printf() and CLI IO. */\r
+       MSS_UART_init( ( mss_uart_instance_t * ) pxUART, MSS_UART_115200_BAUD, MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT );\r
+\r
+       /* Characters are only ever received slowly on the CLI so it is ok to pass\r
+       received characters from the UART interrupt to the task on a queue.  Create\r
+       the queue used for that purpose. */\r
+       xRxedChars = xQueueCreate( cmdRXED_CHARS_QUEUE_LENGTH, sizeof( char ) );\r
+\r
+       /* The interrupt handler makes use of FreeRTOS API functions, so its\r
+       priority must be at or below the configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY\r
+       setting (the higher the numeric priority, the lower the logical priority). */\r
+       NVIC_SetPriority( xUART_IRQ, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );\r
+\r
+       /* Set the UART Rx notification function. */\r
+       MSS_UART_set_rx_handler( ( mss_uart_instance_t * ) pxUART, prvUARTRxNotificationHandler, MSS_UART_FIFO_SINGLE_BYTE );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvUARTRxNotificationHandler( mss_uart_instance_t * pxUART )\r
+{\r
+uint8_t cRxed;\r
+portBASE_TYPE xHigherPriorityTaskWoken;\r
+\r
+       /* The command console receives data very slowly (at the speed of somebody\r
+       typing), therefore it is ok to just handle one character at a time and use\r
+       a queue to send the characters to the task. */\r
+       if( MSS_UART_get_rx( pxUART, &cRxed, sizeof( cRxed ) ) == sizeof( cRxed ) )\r
+       {\r
+               xHigherPriorityTaskWoken = pdFALSE;\r
+               xQueueSendFromISR( xRxedChars, &cRxed, &xHigherPriorityTaskWoken );\r
+\r
+               /* portEND_SWITCHING_ISR() or portYIELD_FROM_ISR() can be used here. */\r
+               portYIELD_FROM_ISR( xHigherPriorityTaskWoken );\r
+       }\r
+}\r
+\r
diff --git a/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo/Full-Demo/UARTCommandConsole.h b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo/Full-Demo/UARTCommandConsole.h
new file mode 100644 (file)
index 0000000..5aabdb9
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo/Full-Demo/UARTCommandConsole.h
@@ -0,0 +1,87 @@
+/*\r
+    FreeRTOS V7.4.2 - Copyright (C) 2013 Real Time Engineers Ltd.\r
+\r
+    FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME.  PLEASE VISIT\r
+    http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+    ***************************************************************************\r
+     *                                                                       *\r
+     *    FreeRTOS tutorial books are available in pdf and paperback.        *\r
+     *    Complete, revised, and edited pdf reference manuals are also       *\r
+     *    available.                                                         *\r
+     *                                                                       *\r
+     *    Purchasing FreeRTOS documentation will not only help you, by       *\r
+     *    ensuring you get running as quickly as possible and with an        *\r
+     *    in-depth knowledge of how to use FreeRTOS, it will also help       *\r
+     *    the FreeRTOS project to continue with its mission of providing     *\r
+     *    professional grade, cross platform, de facto standard solutions    *\r
+     *    for microcontrollers - completely free of charge!                  *\r
+     *                                                                       *\r
+     *    >>> See http://www.FreeRTOS.org/Documentation for details. <<<     *\r
+     *                                                                       *\r
+     *    Thank you for using FreeRTOS, and thank you for your support!      *\r
+     *                                                                       *\r
+    ***************************************************************************\r
+\r
+\r
+    This file is part of the FreeRTOS distribution.\r
+\r
+    FreeRTOS is free software; you can redistribute it and/or modify it under\r
+    the terms of the GNU General Public License (version 2) as published by the\r
+    Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+\r
+    >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to\r
+    distribute a combined work that includes FreeRTOS without being obliged to\r
+    provide the source code for proprietary components outside of the FreeRTOS\r
+    kernel.\r
+\r
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+    FOR A PARTICULAR PURPOSE.  See the GNU General Public License for more\r
+    details. You should have received a copy of the GNU General Public License\r
+    and the FreeRTOS license exception along with FreeRTOS; if not it can be\r
+    viewed here: http://www.freertos.org/a00114.html and also obtained by\r
+    writing to Real Time Engineers Ltd., contact details for whom are available\r
+    on the FreeRTOS WEB site.\r
+\r
+    1 tab == 4 spaces!\r
+\r
+    ***************************************************************************\r
+     *                                                                       *\r
+     *    Having a problem?  Start by reading the FAQ "My application does   *\r
+     *    not run, what could be wrong?"                                     *\r
+     *                                                                       *\r
+     *    http://www.FreeRTOS.org/FAQHelp.html                               *\r
+     *                                                                       *\r
+    ***************************************************************************\r
+\r
+\r
+    http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
+    license and Real Time Engineers Ltd. contact details.\r
+\r
+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+    including FreeRTOS+Trace - an indispensable productivity tool, and our new\r
+    fully thread aware and reentrant UDP/IP stack.\r
+\r
+    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
+    Integrity Systems, who sell the code with commercial support,\r
+    indemnification and middleware, under the OpenRTOS brand.\r
+\r
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+    engineered and independently SIL3 certified version for use in safety and\r
+    mission critical applications that require provable dependability.\r
+*/\r
+\r
+#ifndef UART_COMMAND_CONSOLE_H\r
+#define UART_COMMAND_CONSOLE_H\r
+\r
+/*\r
+ * Create the task that implements a command console using the USB virtual com\r
+ * port driver for intput and output.\r
+ */\r
+void vUARTCommandConsoleStart( uint16_t usStackSize, unsigned portBASE_TYPE uxPriority );\r
+\r
+#endif /* UART_COMMAND_CONSOLE_H */\r
+\r
+\r
+\r
diff --git a/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo/Full-Demo/config_fat_sl.h b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo/Full-Demo/config_fat_sl.h
new file mode 100644 (file)
index 0000000..373d780
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo/Full-Demo/config_fat_sl.h
@@ -0,0 +1,67 @@
+/*\r
+ * FreeRTOS+FAT FS V1.0.0 (C) 2013 HCC Embedded\r
+ *\r
+ * FreeRTOS+FAT SL is an complementary component provided to Real Time Engineers\r
+ * Ltd. by HCC Embedded for use with FreeRTOS.  It is not, in itself, part of\r
+ * the FreeRTOS kernel.  FreeRTOS+FAT SL is licensed separately from FreeRTOS,\r
+ * and uses a different license to FreeRTOS.  FreeRTOS+FAT SL uses a dual\r
+ * license model, information on which is provided below:\r
+ *\r
+ * - Open source licensing -\r
+ * FreeRTOS+FAT SL is a free download and may be used, modified and distributed\r
+ * without charge provided the user adheres to version two of the GNU General\r
+ * Public license (GPL) and does not remove the copyright notice or this text.\r
+ * The GPL V2 text is available on the gnu.org web site, and on the following\r
+ * URL: http://www.FreeRTOS.org/gpl-2.0.txt\r
+ *\r
+ * - Commercial licensing -\r
+ * Businesses and individuals who wish to incorporate FreeRTOS+FAT SL into\r
+ * proprietary software for redistribution in any form must first obtain a\r
+ * commercial license - and in-so-doing support the maintenance, support and\r
+ * further development of the FreeRTOS+FAT SL product.  Commercial licenses can\r
+ * be obtained from http://shop.freertos.org and do not require any source files\r
+ * to be changed.\r
+ *\r
+ * FreeRTOS+FAT SL is distributed in the hope that it will be useful.  You\r
+ * cannot use FreeRTOS+FAT SL unless you agree that you use the software 'as\r
+ * is'.  FreeRTOS+FAT SL is provided WITHOUT ANY WARRANTY; without even the\r
+ * implied warranties of NON-INFRINGEMENT, MERCHANTABILITY or FITNESS FOR A\r
+ * PARTICULAR PURPOSE. Real Time Engineers Ltd. and HCC Embedded disclaims all\r
+ * conditions and terms, be they implied, expressed, or statutory.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://www.FreeRTOS.org/FreeRTOS-Plus\r
+ *\r
+ */\r
+\r
+#ifndef _CONFIG_FAT_SL_H\r
+#define _CONFIG_FAT_SL_H\r
+\r
+#include "../version/ver_fat_sl.h"\r
+#if VER_FAT_SL_MAJOR != 3 || VER_FAT_SL_MINOR != 2\r
+ #error Incompatible FAT_SL version number!\r
+#endif\r
+\r
+#include "../api/api_mdriver.h"\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+\r
+/**************************************************************************\r
+**\r
+**  FAT SL user settings\r
+**\r
+**************************************************************************/\r
+#define F_SECTOR_SIZE           512u  /* Disk sector size. */\r
+#define F_FS_THREAD_AWARE       1     /* Set to one if the file system will be access from more than one task. */\r
+#define F_MAXPATH               64    /* Maximum length a file name (including its full path) can be. */\r
+#define F_MAX_LOCK_WAIT_TICKS   20    /* The maximum number of RTOS ticks to wait when attempting to obtain a lock on the file system when F_FS_THREAD_AWARE is set to 1. */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* _CONFIG_FAT_SL_H */\r
+\r
diff --git a/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo/Full-Demo/config_mdriver_ram.h b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo/Full-Demo/config_mdriver_ram.h
new file mode 100644 (file)
index 0000000..eababe5
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo/Full-Demo/config_mdriver_ram.h
@@ -0,0 +1,52 @@
+/*\r
+ * FreeRTOS+FAT FS V1.0.0 (C) 2013 HCC Embedded\r
+ *\r
+ * FreeRTOS+FAT SL is an complementary component provided to Real Time Engineers\r
+ * Ltd. by HCC Embedded for use with FreeRTOS.  It is not, in itself, part of\r
+ * the FreeRTOS kernel.  FreeRTOS+FAT SL is licensed separately from FreeRTOS,\r
+ * and uses a different license to FreeRTOS.  FreeRTOS+FAT SL uses a dual\r
+ * license model, information on which is provided below:\r
+ *\r
+ * - Open source licensing -\r
+ * FreeRTOS+FAT SL is a free download and may be used, modified and distributed\r
+ * without charge provided the user adheres to version two of the GNU General\r
+ * Public license (GPL) and does not remove the copyright notice or this text.\r
+ * The GPL V2 text is available on the gnu.org web site, and on the following\r
+ * URL: http://www.FreeRTOS.org/gpl-2.0.txt\r
+ *\r
+ * - Commercial licensing -\r
+ * Businesses and individuals who wish to incorporate FreeRTOS+FAT SL into\r
+ * proprietary software for redistribution in any form must first obtain a\r
+ * commercial license - and in-so-doing support the maintenance, support and\r
+ * further development of the FreeRTOS+FAT SL product.  Commercial licenses can\r
+ * be obtained from http://shop.freertos.org and do not require any source files\r
+ * to be changed.\r
+ *\r
+ * FreeRTOS+FAT SL is distributed in the hope that it will be useful.  You\r
+ * cannot use FreeRTOS+FAT SL unless you agree that you use the software 'as\r
+ * is'.  FreeRTOS+FAT SL is provided WITHOUT ANY WARRANTY; without even the\r
+ * implied warranties of NON-INFRINGEMENT, MERCHANTABILITY or FITNESS FOR A\r
+ * PARTICULAR PURPOSE. Real Time Engineers Ltd. and HCC Embedded disclaims all\r
+ * conditions and terms, be they implied, expressed, or statutory.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://www.FreeRTOS.org/FreeRTOS-Plus\r
+ *\r
+ */\r
+\r
+#ifndef _CONFIG_MDRIVER_RAM_H_\r
+#define _CONFIG_MDRIVER_RAM_H_\r
+\r
+#include "../version/ver_mdriver_ram.h"\r
+#if VER_MDRIVER_RAM_MAJOR != 1 || VER_MDRIVER_RAM_MINOR != 2\r
+ #error Incompatible MDRIVER_RAM version number!\r
+#endif\r
+\r
+#define MDRIVER_RAM_SECTOR_SIZE   512       /* Sector size */\r
+\r
+#define MDRIVER_RAM_VOLUME0_SIZE  (28 * 1024) /* defintion for size of ramdrive0 */\r
+\r
+#define MDRIVER_MEM_LONG_ACCESS   1         /* set this value to 1 if 32bit access available */\r
+\r
+#endif /* ifndef _CONFIG_MDRIVER_RAM_H_ */\r
+\r
diff --git a/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo/Full-Demo/main_full.c b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo/Full-Demo/main_full.c
new file mode 100644 (file)
index 0000000..16f4ead
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo/Full-Demo/main_full.c
@@ -0,0 +1,367 @@
+/*\r
+    FreeRTOS V7.4.2 - Copyright (C) 2013 Real Time Engineers Ltd.\r
+\r
+    FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME.  PLEASE VISIT\r
+    http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+    ***************************************************************************\r
+     *                                                                       *\r
+     *    FreeRTOS tutorial books are available in pdf and paperback.        *\r
+     *    Complete, revised, and edited pdf reference manuals are also       *\r
+     *    available.                                                         *\r
+     *                                                                       *\r
+     *    Purchasing FreeRTOS documentation will not only help you, by       *\r
+     *    ensuring you get running as quickly as possible and with an        *\r
+     *    in-depth knowledge of how to use FreeRTOS, it will also help       *\r
+     *    the FreeRTOS project to continue with its mission of providing     *\r
+     *    professional grade, cross platform, de facto standard solutions    *\r
+     *    for microcontrollers - completely free of charge!                  *\r
+     *                                                                       *\r
+     *    >>> See http://www.FreeRTOS.org/Documentation for details. <<<     *\r
+     *                                                                       *\r
+     *    Thank you for using FreeRTOS, and thank you for your support!      *\r
+     *                                                                       *\r
+    ***************************************************************************\r
+\r
+\r
+    This file is part of the FreeRTOS distribution.\r
+\r
+    FreeRTOS is free software; you can redistribute it and/or modify it under\r
+    the terms of the GNU General Public License (version 2) as published by the\r
+    Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+\r
+    >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to\r
+    distribute a combined work that includes FreeRTOS without being obliged to\r
+    provide the source code for proprietary components outside of the FreeRTOS\r
+    kernel.\r
+\r
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+    FOR A PARTICULAR PURPOSE.  See the GNU General Public License for more\r
+    details. You should have received a copy of the GNU General Public License\r
+    and the FreeRTOS license exception along with FreeRTOS; if not it can be\r
+    viewed here: http://www.freertos.org/a00114.html and also obtained by\r
+    writing to Real Time Engineers Ltd., contact details for whom are available\r
+    on the FreeRTOS WEB site.\r
+\r
+    1 tab == 4 spaces!\r
+\r
+    ***************************************************************************\r
+     *                                                                       *\r
+     *    Having a problem?  Start by reading the FAQ "My application does   *\r
+     *    not run, what could be wrong?"                                     *\r
+     *                                                                       *\r
+     *    http://www.FreeRTOS.org/FAQHelp.html                               *\r
+     *                                                                       *\r
+    ***************************************************************************\r
+\r
+\r
+    http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
+    license and Real Time Engineers Ltd. contact details.\r
+\r
+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+    including FreeRTOS+Trace - an indispensable productivity tool, and our new\r
+    fully thread aware and reentrant UDP/IP stack.\r
+\r
+    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
+    Integrity Systems, who sell the code with commercial support,\r
+    indemnification and middleware, under the OpenRTOS brand.\r
+\r
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+    engineered and independently SIL3 certified version for use in safety and\r
+    mission critical applications that require provable dependability.\r
+*/\r
+\r
+/******************************************************************************\r
+ * NOTE 1:  This project provides two demo applications.  A simple blinky style\r
+ * project, and a more comprehensive test and demo application.  The\r
+ * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to select\r
+ * between the two.  See the notes on using mainCREATE_SIMPLE_BLINKY_DEMO_ONLY\r
+ * in main.c.  This file implements the comprehensive test and demo version.\r
+ *\r
+ * NOTE 2:  This file only contains the source code that is specific to the\r
+ * full demo.  Generic functions, such FreeRTOS hook functions, and functions\r
+ * required to configure the hardware, are defined in main.c.\r
+ ******************************************************************************\r
+ *\r
+ * main_full() creates all the demo application tasks and a software timer, then\r
+ * starts the scheduler.  The web documentation provides more details of the\r
+ * standard demo application tasks, which provide no particular functionality,\r
+ * but do provide a good example of how to use the FreeRTOS API.\r
+ *\r
+ * In addition to the standard demo tasks, the following tasks and tests are\r
+ * defined and/or created within this file:\r
+ *\r
+ * "Check" timer - The check software timer period is initially set to three\r
+ * seconds.  The callback function associated with the check software timer\r
+ * checks that all the standard demo tasks are not only still executing, but\r
+ * are executing without reporting any errors.  If the check software timer\r
+ * discovers that a task has either stalled, or reported an error, then it\r
+ * changes its own execution period from the initial three seconds, to just\r
+ * 200ms.  The check software timer callback function also toggles the green\r
+ * LED each time it is called.  This provides a visual indication of the system\r
+ * status:  If the green LED toggles every three seconds, then no issues have\r
+ * been discovered.  If the green LED toggles every 200ms, then an issue has\r
+ * been discovered with at least one task.\r
+ *\r
+ * FreeRTOS+CLI command console.  The command console is access through UART0\r
+ * using 115200 baud and the Microsemi MSS UART drivers.  Type "help" to see a\r
+ * list of registered commands, which include some basic file system commands\r
+ * (see FreeRTOS+FAT SL comments below). The FreeRTOS+CLI license is different\r
+ * to the FreeRTOS license, see http://www.FreeRTOS.org/cli for license and\r
+ * usage details.\r
+ *\r
+ * FreeRTOS+FAT SL.  FreeRTOS+FAT SL is demonstrated using a RAM disk.  [At the\r
+ * time of writing] The functionality of the file system demo is identical to\r
+ * the functionality of the FreeRTOS Win32 simulator file system demo with the\r
+ * command console being accessed via the UART (as described above) instead of\r
+ * a network terminal.  The FreeRTOS+FAT SL license is different to the FreeRTOS\r
+ * license, see http://www.FreeRTOS.org/fat_sl for license and usage details,\r
+ * and a description of the file system demo functionality.\r
+ *\r
+ * See the documentation page for this demo on the FreeRTOS.org web site for\r
+ * full information, including hardware setup requirements.\r
+ */\r
+\r
+/* Standard includes. */\r
+#include <stdio.h>\r
+\r
+/* Kernel includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "timers.h"\r
+#include "queue.h"\r
+\r
+/* Standard demo application includes. */\r
+#include "integer.h"\r
+#include "PollQ.h"\r
+#include "semtest.h"\r
+#include "dynamic.h"\r
+#include "BlockQ.h"\r
+#include "blocktim.h"\r
+#include "countsem.h"\r
+#include "GenQTest.h"\r
+#include "recmutex.h"\r
+#include "death.h"\r
+#include "flash_timer.h"\r
+#include "partest.h"\r
+#include "UARTCommandConsole.h"\r
+\r
+/* Priorities for the demo application tasks. */\r
+#define mainQUEUE_POLL_PRIORITY                                ( tskIDLE_PRIORITY + 2UL )\r
+#define mainSEM_TEST_PRIORITY                          ( tskIDLE_PRIORITY + 1UL )\r
+#define mainBLOCK_Q_PRIORITY                           ( tskIDLE_PRIORITY + 2UL )\r
+#define mainCREATOR_TASK_PRIORITY                      ( tskIDLE_PRIORITY + 3UL )\r
+#define mainFLOP_TASK_PRIORITY                         ( tskIDLE_PRIORITY )\r
+\r
+/* A block time of zero simply means "don't block". */\r
+#define mainDONT_BLOCK                                         ( 0UL )\r
+\r
+/* The period after which the check timer will expire, in ms, provided no errors\r
+have been reported by any of the standard demo tasks.  ms are converted to the\r
+equivalent in ticks using the portTICK_RATE_MS constant. */\r
+#define mainCHECK_TIMER_PERIOD_MS                      ( 3000UL / portTICK_RATE_MS )\r
+\r
+/* The period at which the check timer will expire, in ms, if an error has been\r
+reported in one of the standard demo tasks.  ms are converted to the equivalent\r
+in ticks using the portTICK_RATE_MS constant. */\r
+#define mainERROR_CHECK_TIMER_PERIOD_MS        ( 200UL / portTICK_RATE_MS )\r
+\r
+/* The standard demo flash timers can be used to flash any number of LEDs.  In\r
+this case, because only three LEDs are available, and one is in use by the\r
+check timer, only two are used by the flash timers. */\r
+#define mainNUMBER_OF_FLASH_TIMERS_LEDS                ( 1 )\r
+\r
+/* The LED toggled by the check timer.  The first two LEDs are toggle by the\r
+standard demo flash timers. */\r
+#define mainCHECK_LED                                          ( 1 )\r
+\r
+/* The size of the stack and the priority used by the UART command console\r
+task. */\r
+#define mainUART_COMMAND_CONSOLE_STACK_SIZE            ( configMINIMAL_STACK_SIZE * 2 )\r
+#define mainUART_COMMAND_CONSOLE_TASK_PRIORITY ( tskIDLE_PRIORITY )\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * The check timer callback function, as described at the top of this file.\r
+ */\r
+static void prvCheckTimerCallback( xTimerHandle xTimer );\r
+\r
+/*\r
+ * Register commands that can be used with FreeRTOS+CLI.  The commands are\r
+ * defined in CLI-Commands.c and File-Related-CLI-Command.c respectively.\r
+ */\r
+extern void vRegisterSampleCLICommands( void );\r
+extern void vRegisterFileSystemCLICommands( void );\r
+\r
+/* Prepare to run the full demo: Configure the IO, register the CLI\r
+ * commands, and depending on configuration, generate a set of sample files on\r
+ * a RAM disk.\r
+ */\r
+static void prvPrepareForFullDemo( void );\r
+\r
+/*\r
+ * Creates and verifies different files on the volume, demonstrating the use of\r
+ * various different API functions.\r
+ */\r
+extern void vCreateAndVerifySampleFiles( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void main_full( void )\r
+{\r
+xTimerHandle xCheckTimer = NULL;\r
+\r
+       /* Prepare to run the full demo: Configure the IO, register the CLI\r
+       commands, and depending on configuration, generate a set of sample files on\r
+       a RAM disk. */\r
+       prvPrepareForFullDemo();\r
+\r
+       /* Start all the other standard demo/test tasks.  The have not particular\r
+       functionality, but do demonstrate how to use the FreeRTOS API and test the\r
+       kernel port. */\r
+       vStartIntegerMathTasks( tskIDLE_PRIORITY );\r
+       vStartDynamicPriorityTasks();\r
+       vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );\r
+       vCreateBlockTimeTasks();\r
+       vStartCountingSemaphoreTasks();\r
+       vStartGenericQueueTasks( tskIDLE_PRIORITY );\r
+       vStartRecursiveMutexTasks();\r
+       vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );\r
+       vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );\r
+       vStartLEDFlashTimers( mainNUMBER_OF_FLASH_TIMERS_LEDS );\r
+\r
+       /* Start the tasks that implements the command console on the UART, as\r
+       described above. */\r
+       vUARTCommandConsoleStart( mainUART_COMMAND_CONSOLE_STACK_SIZE, mainUART_COMMAND_CONSOLE_TASK_PRIORITY );\r
+\r
+       /* Create the software timer that performs the 'check' functionality,\r
+       as described at the top of this file. */\r
+       xCheckTimer = xTimerCreate( ( const signed char * ) "CheckTimer",/* A text name, purely to help debugging. */\r
+                                                               ( mainCHECK_TIMER_PERIOD_MS ),          /* The timer period, in this case 3000ms (3s). */\r
+                                                               pdTRUE,                                                         /* This is an auto-reload timer, so xAutoReload is set to pdTRUE. */\r
+                                                               ( void * ) 0,                                           /* The ID is not used, so can be set to anything. */\r
+                                                               prvCheckTimerCallback                           /* The callback function that inspects the status of all the other tasks. */\r
+                                                         );\r
+\r
+       if( xCheckTimer != NULL )\r
+       {\r
+               xTimerStart( xCheckTimer, mainDONT_BLOCK );\r
+       }\r
+\r
+       /* The set of tasks created by the following function call have to be\r
+       created last as they keep account of the number of tasks they expect to see\r
+       running. */\r
+       vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY );\r
+\r
+       /* Start the scheduler. */\r
+       vTaskStartScheduler();\r
+\r
+       /* If all is well, the scheduler will now be running, and the following line\r
+       will never be reached.  If the following line does execute, then there was\r
+       insufficient FreeRTOS heap memory available for the idle and/or timer tasks\r
+       to be created.  See the memory management section on the FreeRTOS web site\r
+       for more details. */\r
+       for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvCheckTimerCallback( xTimerHandle xTimer )\r
+{\r
+static long lChangedTimerPeriodAlready = pdFALSE;\r
+unsigned long ulErrorFound = pdFALSE;\r
+\r
+       /* Check all the demo tasks (other than the flash tasks) to ensure\r
+       they are all still running, and that none have detected an error. */\r
+       if( xAreIntegerMathsTaskStillRunning() != pdTRUE )\r
+       {\r
+               ulErrorFound = pdTRUE;\r
+       }\r
+\r
+       if( xAreDynamicPriorityTasksStillRunning() != pdTRUE )\r
+       {\r
+               ulErrorFound = pdTRUE;\r
+       }\r
+\r
+       if( xAreBlockingQueuesStillRunning() != pdTRUE )\r
+       {\r
+               ulErrorFound = pdTRUE;\r
+       }\r
+\r
+       if ( xAreBlockTimeTestTasksStillRunning() != pdTRUE )\r
+       {\r
+               ulErrorFound = pdTRUE;\r
+       }\r
+\r
+       if ( xAreGenericQueueTasksStillRunning() != pdTRUE )\r
+       {\r
+               ulErrorFound = pdTRUE;\r
+       }\r
+\r
+       if ( xAreRecursiveMutexTasksStillRunning() != pdTRUE )\r
+       {\r
+               ulErrorFound = pdTRUE;\r
+       }\r
+\r
+       if( xIsCreateTaskStillRunning() != pdTRUE )\r
+       {\r
+               ulErrorFound = pdTRUE;\r
+       }\r
+\r
+       if( xArePollingQueuesStillRunning() != pdTRUE )\r
+       {\r
+               ulErrorFound = pdTRUE;\r
+       }\r
+\r
+       if( xAreSemaphoreTasksStillRunning() != pdTRUE )\r
+       {\r
+               ulErrorFound = pdTRUE;\r
+       }\r
+\r
+       /* Toggle the check LED to give an indication of the system status.  If\r
+       the LED toggles every mainCHECK_TIMER_PERIOD_MS milliseconds then\r
+       everything is ok.  A faster toggle indicates an error. */\r
+       vParTestToggleLED( mainCHECK_LED );\r
+\r
+       /* Have any errors been latch in ulErrorFound?  If so, shorten the\r
+       period of the check timer to mainERROR_CHECK_TIMER_PERIOD_MS milliseconds.\r
+       This will result in an increase in the rate at which mainCHECK_LED\r
+       toggles. */\r
+       if( ulErrorFound != pdFALSE )\r
+       {\r
+               if( lChangedTimerPeriodAlready == pdFALSE )\r
+               {\r
+                       lChangedTimerPeriodAlready = pdTRUE;\r
+\r
+                       /* This call to xTimerChangePeriod() uses a zero block time.\r
+                       Functions called from inside of a timer callback function must\r
+                       *never* attempt to block. */\r
+                       xTimerChangePeriod( xTimer, ( mainERROR_CHECK_TIMER_PERIOD_MS ), mainDONT_BLOCK );\r
+               }\r
+       }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvPrepareForFullDemo( void )\r
+{\r
+       /* If the file system is only going to be accessed from one task then\r
+       F_FS_THREAD_AWARE can be set to 0 and the set of example files are created\r
+       before the RTOS scheduler is started.  If the file system is going to be\r
+       access from more than one task then F_FS_THREAD_AWARE must be set to 1 and\r
+       the     set of sample files are created from the idle task hook function\r
+       vApplicationIdleHook() - which is defined in this file. */\r
+       #if F_FS_THREAD_AWARE == 0\r
+       {\r
+               /* Initialise the drive and file system, then create a few example\r
+               files.  The output from this function just goes to the stdout window,\r
+               allowing the output to be viewed when the UDP command console is not\r
+               connected. */\r
+               vCreateAndVerifySampleFiles();\r
+       }\r
+       #endif\r
+\r
+       /* Register both the standard and file system related CLI commands. */\r
+       vRegisterSampleCLICommands();\r
+       vRegisterFileSystemCLICommands();\r
+}\r
diff --git a/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo/ParTest.c b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo/ParTest.c
new file mode 100644 (file)
index 0000000..db80bdf
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo/ParTest.c
@@ -0,0 +1,153 @@
+/*\r
+    FreeRTOS V7.4.2 - Copyright (C) 2013 Real Time Engineers Ltd.\r
+\r
+    FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME.  PLEASE VISIT\r
+    http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+    ***************************************************************************\r
+     *                                                                       *\r
+     *    FreeRTOS tutorial books are available in pdf and paperback.        *\r
+     *    Complete, revised, and edited pdf reference manuals are also       *\r
+     *    available.                                                         *\r
+     *                                                                       *\r
+     *    Purchasing FreeRTOS documentation will not only help you, by       *\r
+     *    ensuring you get running as quickly as possible and with an        *\r
+     *    in-depth knowledge of how to use FreeRTOS, it will also help       *\r
+     *    the FreeRTOS project to continue with its mission of providing     *\r
+     *    professional grade, cross platform, de facto standard solutions    *\r
+     *    for microcontrollers - completely free of charge!                  *\r
+     *                                                                       *\r
+     *    >>> See http://www.FreeRTOS.org/Documentation for details. <<<     *\r
+     *                                                                       *\r
+     *    Thank you for using FreeRTOS, and thank you for your support!      *\r
+     *                                                                       *\r
+    ***************************************************************************\r
+\r
+\r
+    This file is part of the FreeRTOS distribution.\r
+\r
+    FreeRTOS is free software; you can redistribute it and/or modify it under\r
+    the terms of the GNU General Public License (version 2) as published by the\r
+    Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+\r
+    >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to\r
+    distribute a combined work that includes FreeRTOS without being obliged to\r
+    provide the source code for proprietary components outside of the FreeRTOS\r
+    kernel.\r
+\r
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+    FOR A PARTICULAR PURPOSE.  See the GNU General Public License for more\r
+    details. You should have received a copy of the GNU General Public License\r
+    and the FreeRTOS license exception along with FreeRTOS; if not it can be\r
+    viewed here: http://www.freertos.org/a00114.html and also obtained by\r
+    writing to Real Time Engineers Ltd., contact details for whom are available\r
+    on the FreeRTOS WEB site.\r
+\r
+    1 tab == 4 spaces!\r
+\r
+    ***************************************************************************\r
+     *                                                                       *\r
+     *    Having a problem?  Start by reading the FAQ "My application does   *\r
+     *    not run, what could be wrong?"                                     *\r
+     *                                                                       *\r
+     *    http://www.FreeRTOS.org/FAQHelp.html                               *\r
+     *                                                                       *\r
+    ***************************************************************************\r
+\r
+\r
+    http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
+    license and Real Time Engineers Ltd. contact details.\r
+\r
+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+    including FreeRTOS+Trace - an indispensable productivity tool, and our new\r
+    fully thread aware and reentrant UDP/IP stack.\r
+\r
+    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
+    Integrity Systems, who sell the code with commercial support,\r
+    indemnification and middleware, under the OpenRTOS brand.\r
+\r
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+    engineered and independently SIL3 certified version for use in safety and\r
+    mission critical applications that require provable dependability.\r
+*/\r
+\r
+/*-----------------------------------------------------------\r
+ * Simple IO routines to control the LEDs.\r
+ * This file is called ParTest.c for historic reasons.  Originally it stood for\r
+ * PARallel port TEST.\r
+ *-----------------------------------------------------------*/\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Demo includes. */\r
+#include "partest.h"\r
+\r
+/* Library includes. */\r
+#include "drivers/mss_gpio/mss_gpio.h"\r
+#include "CMSIS/system_m2sxxx.h"\r
+\r
+#define partstNUM_LEDS 2\r
+\r
+/* Remember the state of the outputs for easy toggling. */\r
+static unsigned char ucPortState = 0;\r
+\r
+static const mss_gpio_id_t ucLEDs[ partstNUM_LEDS ] = { MSS_GPIO_14, MSS_GPIO_15 };\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestInitialise( void )\r
+{\r
+long x;\r
+\r
+       /* Initialise MSS GPIOs. */\r
+    MSS_GPIO_init();\r
+\r
+    /* Ensure the LEDs are outputs and off to start. */\r
+    for( x = 0; x < partstNUM_LEDS; x++ )\r
+    {\r
+       MSS_GPIO_config( ucLEDs[ x ], MSS_GPIO_OUTPUT_MODE );\r
+       vParTestSetLED( x, pdFALSE );\r
+    }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue )\r
+{\r
+       if( uxLED < partstNUM_LEDS )\r
+       {\r
+               taskENTER_CRITICAL();\r
+               {\r
+                       MSS_GPIO_set_output( ucLEDs[ uxLED ], xValue );\r
+\r
+                       /* Remember the new output state. */\r
+                       if( xValue == 0 )\r
+                       {\r
+                               ucPortState &= ~( 1 << uxLED );\r
+                       }\r
+                       else\r
+                       {\r
+                               ucPortState |= ( 1 << uxLED );\r
+                       }\r
+               }\r
+               taskEXIT_CRITICAL();\r
+       }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestToggleLED( unsigned portBASE_TYPE uxLED )\r
+{\r
+       if( uxLED < partstNUM_LEDS )\r
+       {\r
+               taskENTER_CRITICAL();\r
+               {\r
+                       vParTestSetLED( uxLED, !( ucPortState & ( 1 << uxLED ) ) );\r
+               }\r
+               taskEXIT_CRITICAL();\r
+       }\r
+}\r
+\r
+\r
+\r
diff --git a/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo/RunTimeStatsTimer.c b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo/RunTimeStatsTimer.c
new file mode 100644 (file)
index 0000000..0ce8bc6
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo/RunTimeStatsTimer.c
@@ -0,0 +1,138 @@
+/*\r
+    FreeRTOS V7.4.2 - Copyright (C) 2013 Real Time Engineers Ltd.\r
+\r
+    FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME.  PLEASE VISIT\r
+    http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+    ***************************************************************************\r
+     *                                                                       *\r
+     *    FreeRTOS tutorial books are available in pdf and paperback.        *\r
+     *    Complete, revised, and edited pdf reference manuals are also       *\r
+     *    available.                                                         *\r
+     *                                                                       *\r
+     *    Purchasing FreeRTOS documentation will not only help you, by       *\r
+     *    ensuring you get running as quickly as possible and with an        *\r
+     *    in-depth knowledge of how to use FreeRTOS, it will also help       *\r
+     *    the FreeRTOS project to continue with its mission of providing     *\r
+     *    professional grade, cross platform, de facto standard solutions    *\r
+     *    for microcontrollers - completely free of charge!                  *\r
+     *                                                                       *\r
+     *    >>> See http://www.FreeRTOS.org/Documentation for details. <<<     *\r
+     *                                                                       *\r
+     *    Thank you for using FreeRTOS, and thank you for your support!      *\r
+     *                                                                       *\r
+    ***************************************************************************\r
+\r
+\r
+    This file is part of the FreeRTOS distribution.\r
+\r
+    FreeRTOS is free software; you can redistribute it and/or modify it under\r
+    the terms of the GNU General Public License (version 2) as published by the\r
+    Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+\r
+    >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to\r
+    distribute a combined work that includes FreeRTOS without being obliged to\r
+    provide the source code for proprietary components outside of the FreeRTOS\r
+    kernel.\r
+\r
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+    FOR A PARTICULAR PURPOSE.  See the GNU General Public License for more\r
+    details. You should have received a copy of the GNU General Public License\r
+    and the FreeRTOS license exception along with FreeRTOS; if not it can be\r
+    viewed here: http://www.freertos.org/a00114.html and also obtained by\r
+    writing to Real Time Engineers Ltd., contact details for whom are available\r
+    on the FreeRTOS WEB site.\r
+\r
+    1 tab == 4 spaces!\r
+\r
+    ***************************************************************************\r
+     *                                                                       *\r
+     *    Having a problem?  Start by reading the FAQ "My application does   *\r
+     *    not run, what could be wrong?"                                     *\r
+     *                                                                       *\r
+     *    http://www.FreeRTOS.org/FAQHelp.html                               *\r
+     *                                                                       *\r
+    ***************************************************************************\r
+\r
+\r
+    http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
+    license and Real Time Engineers Ltd. contact details.\r
+\r
+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+    including FreeRTOS+Trace - an indispensable productivity tool, and our new\r
+    fully thread aware and reentrant UDP/IP stack.\r
+\r
+    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
+    Integrity Systems, who sell the code with commercial support,\r
+    indemnification and middleware, under the OpenRTOS brand.\r
+\r
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+    engineered and independently SIL3 certified version for use in safety and\r
+    mission critical applications that require provable dependability.\r
+*/\r
+\r
+/* FreeRTOS includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Utility functions to implement run time stats on Cortex-M CPUs.  The collected\r
+run time data can be viewed through the CLI interface.  See the following URL for\r
+more information on run time stats:\r
+http://www.freertos.org/rtos-run-time-stats.html */\r
+\r
+/* Used in the run time stats calculations. */\r
+static uint32_t ulClocksPer10thOfAMilliSecond = 0UL;\r
+\r
+\r
+void vConfigureTimerForRunTimeStats( void )\r
+{\r
+       /* How many clocks are there per tenth of a millisecond? */\r
+       ulClocksPer10thOfAMilliSecond = configCPU_CLOCK_HZ / 10000UL;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+uint32_t ulGetRunTimeCounterValue( void )\r
+{\r
+uint32_t ulSysTickCounts, ulTickCount, ulReturn;\r
+const uint32_t ulSysTickReloadValue = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\r
+volatile uint32_t * const pulCurrentSysTickCount = ( ( volatile uint32_t *) 0xe000e018 );\r
+volatile uint32_t * const pulInterruptCTRLState = ( ( volatile uint32_t *) 0xe000ed04 );\r
+const uint32_t ulSysTickPendingBit = 0x04000000UL;\r
+\r
+       /* NOTE: There are potentially race conditions here.  However, it is used\r
+       anyway to keep the examples simple, and to avoid reliance on a separate\r
+       timer peripheral. */\r
+\r
+\r
+       /* The SysTick is a down counter.  How many clocks have passed since it was\r
+       last reloaded? */\r
+       ulSysTickCounts = ulSysTickReloadValue - *pulCurrentSysTickCount;\r
+\r
+       /* How many times has it overflowed? */\r
+       ulTickCount = xTaskGetTickCountFromISR();\r
+\r
+       /* Is there a SysTick interrupt pending? */\r
+       if( ( *pulInterruptCTRLState & ulSysTickPendingBit ) != 0UL )\r
+       {\r
+               /* There is a SysTick interrupt pending, so the SysTick has overflowed\r
+               but the tick count not yet incremented. */\r
+               ulTickCount++;\r
+\r
+               /* Read the SysTick again, as the overflow might have occurred since\r
+               it was read last. */\r
+               ulSysTickCounts = ulSysTickReloadValue - *pulCurrentSysTickCount;\r
+       }\r
+\r
+       /* Convert the tick count into tenths of a millisecond.  THIS ASSUMES\r
+       configTICK_RATE_HZ is 1000! */\r
+       ulReturn = ( ulTickCount * 10UL ) ;\r
+\r
+       /* Add on the number of tenths of a millisecond that have passed since the\r
+       tick count last got updated. */\r
+       ulReturn += ( ulSysTickCounts / ulClocksPer10thOfAMilliSecond );\r
+\r
+       return ulReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
diff --git a/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo/main.c b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo/main.c
new file mode 100644 (file)
index 0000000..e96a299
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo/main.c
@@ -0,0 +1,233 @@
+/*\r
+    FreeRTOS V7.4.2 - Copyright (C) 2013 Real Time Engineers Ltd.\r
+\r
+    FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME.  PLEASE VISIT\r
+    http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+    ***************************************************************************\r
+     *                                                                       *\r
+     *    FreeRTOS tutorial books are available in pdf and paperback.        *\r
+     *    Complete, revised, and edited pdf reference manuals are also       *\r
+     *    available.                                                         *\r
+     *                                                                       *\r
+     *    Purchasing FreeRTOS documentation will not only help you, by       *\r
+     *    ensuring you get running as quickly as possible and with an        *\r
+     *    in-depth knowledge of how to use FreeRTOS, it will also help       *\r
+     *    the FreeRTOS project to continue with its mission of providing     *\r
+     *    professional grade, cross platform, de facto standard solutions    *\r
+     *    for microcontrollers - completely free of charge!                  *\r
+     *                                                                       *\r
+     *    >>> See http://www.FreeRTOS.org/Documentation for details. <<<     *\r
+     *                                                                       *\r
+     *    Thank you for using FreeRTOS, and thank you for your support!      *\r
+     *                                                                       *\r
+    ***************************************************************************\r
+\r
+\r
+    This file is part of the FreeRTOS distribution.\r
+\r
+    FreeRTOS is free software; you can redistribute it and/or modify it under\r
+    the terms of the GNU General Public License (version 2) as published by the\r
+    Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+\r
+    >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to\r
+    distribute a combined work that includes FreeRTOS without being obliged to\r
+    provide the source code for proprietary components outside of the FreeRTOS\r
+    kernel.\r
+\r
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+    FOR A PARTICULAR PURPOSE.  See the GNU General Public License for more\r
+    details. You should have received a copy of the GNU General Public License\r
+    and the FreeRTOS license exception along with FreeRTOS; if not it can be\r
+    viewed here: http://www.freertos.org/a00114.html and also obtained by\r
+    writing to Real Time Engineers Ltd., contact details for whom are available\r
+    on the FreeRTOS WEB site.\r
+\r
+    1 tab == 4 spaces!\r
+\r
+    ***************************************************************************\r
+     *                                                                       *\r
+     *    Having a problem?  Start by reading the FAQ "My application does   *\r
+     *    not run, what could be wrong?"                                     *\r
+     *                                                                       *\r
+     *    http://www.FreeRTOS.org/FAQHelp.html                               *\r
+     *                                                                       *\r
+    ***************************************************************************\r
+\r
+\r
+    http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
+    license and Real Time Engineers Ltd. contact details.\r
+\r
+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+    including FreeRTOS+Trace - an indispensable productivity tool, and our new\r
+    fully thread aware and reentrant UDP/IP stack.\r
+\r
+    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
+    Integrity Systems, who sell the code with commercial support,\r
+    indemnification and middleware, under the OpenRTOS brand.\r
+\r
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+    engineered and independently SIL3 certified version for use in safety and\r
+    mission critical applications that require provable dependability.\r
+*/\r
+\r
+/******************************************************************************\r
+ * This project provides two demo applications.  A simple blinky style project,\r
+ * and a more comprehensive test and demo application.  The\r
+ * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting (defined in this file) is used to\r
+ * select between the two.  The simply blinky demo is implemented and described\r
+ * in main_blinky.c.  The more comprehensive test and demo application is\r
+ * implemented and described in main_full.c.\r
+ *\r
+ * This file implements the code that is not demo specific, including the\r
+ * hardware setup and FreeRTOS hook functions.\r
+ *\r
+ */\r
+\r
+/* Standard includes. */\r
+#include <stdio.h>\r
+\r
+/* Kernel includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Standard demo includes - just needed for the LED (ParTest) initialisation\r
+function. */\r
+#include "partest.h"\r
+\r
+/* Set mainCREATE_SIMPLE_BLINKY_DEMO_ONLY to one to run the simple blinky demo,\r
+or 0 to run the more comprehensive test and demo application. */\r
+#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY     0\r
+\r
+/*\r
+ * Set up the hardware ready to run this demo.\r
+ */\r
+static void prvSetupHardware( void );\r
+\r
+/*\r
+ * main_blinky() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1.\r
+ * main_full() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 0.\r
+ */\r
+extern void main_blinky( void );\r
+extern void main_full( void );\r
+\r
+/* Prototypes for the standard FreeRTOS callback/hook functions implemented\r
+within this file. */\r
+void vApplicationMallocFailedHook( void );\r
+void vApplicationIdleHook( void );\r
+void vApplicationStackOverflowHook( xTaskHandle pxTask, signed char *pcTaskName );\r
+void vApplicationTickHook( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+/* See the documentation page for this demo on the FreeRTOS.org web site for\r
+full information - including hardware setup requirements. */\r
+\r
+int main( void )\r
+{\r
+       /* Prepare the hardware to run this demo. */\r
+       prvSetupHardware();\r
+\r
+       /* The mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting is described at the top\r
+       of this file. */\r
+       #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1\r
+       {\r
+               main_blinky();\r
+       }\r
+       #else\r
+       {\r
+               main_full();\r
+       }\r
+       #endif\r
+\r
+       return 0;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSetupHardware( void )\r
+{\r
+       /* Perform any configuration necessary to use the ParTest LED output\r
+       functions.  The name ParTest is now somewhat obsolete - originally it\r
+       stood for PARallel port Test. */\r
+       vParTestInitialise();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationMallocFailedHook( void )\r
+{\r
+       /* vApplicationMallocFailedHook() will only be called if\r
+       configUSE_MALLOC_FAILED_HOOK is set to 1 in FreeRTOSConfig.h.  It is a hook\r
+       function that will get called if a call to pvPortMalloc() fails.\r
+       pvPortMalloc() is called internally by the kernel whenever a task, queue,\r
+       timer or semaphore is created.  It is also called by various parts of the\r
+       demo application.  If heap_1.c or heap_2.c are used, then the size of the\r
+       heap available to pvPortMalloc() is defined by configTOTAL_HEAP_SIZE in\r
+       FreeRTOSConfig.h, and the xPortGetFreeHeapSize() API function can be used\r
+       to query the size of free heap space that remains (although it does not\r
+       provide information on how the remaining heap might be fragmented). */\r
+       taskDISABLE_INTERRUPTS();\r
+       for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationIdleHook( void )\r
+{\r
+       /* vApplicationIdleHook() will only be called if configUSE_IDLE_HOOK is set\r
+       to 1 in FreeRTOSConfig.h.  It will be called on each iteration of the idle\r
+       task.  It is essential that code added to this hook function never attempts\r
+       to block in any way (for example, call xQueueReceive() with a block time\r
+       specified, or call vTaskDelay()).  If the application makes use of the\r
+       vTaskDelete() API function (as this demo application does) then it is also\r
+       important that vApplicationIdleHook() is permitted to return to its calling\r
+       function, because it is the responsibility of the idle task to clean up\r
+       memory allocated by the kernel to any task that has since been deleted. */\r
+\r
+       #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY != 1\r
+       {\r
+               /* If the file system is only going to be accessed from one task then\r
+               F_FS_THREAD_AWARE can be set to 0 and the set of example files is created\r
+               before the RTOS scheduler is started.  If the file system is going to be\r
+               access from more than one task then F_FS_THREAD_AWARE must be set to 1 and\r
+               the     set of sample files are created from the idle task hook function. */\r
+               #if F_FS_THREAD_AWARE == 1\r
+               {\r
+                       static portBASE_TYPE xCreatedSampleFiles = pdFALSE;\r
+\r
+                       /* Initialise the drive and file system, then create a few example\r
+                       files.  The output from this function just goes to the stdout window,\r
+                       allowing the output to be viewed when the UDP command console is not\r
+                       connected. */\r
+                       if( xCreatedSampleFiles == pdFALSE )\r
+                       {\r
+                               vCreateAndVerifySampleFiles();\r
+                               xCreatedSampleFiles = pdTRUE;\r
+                       }\r
+               }\r
+               #endif\r
+       }\r
+       #endif\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationStackOverflowHook( xTaskHandle pxTask, signed char *pcTaskName )\r
+{\r
+       ( void ) pcTaskName;\r
+       ( void ) pxTask;\r
+\r
+       /* Run time stack overflow checking is performed if\r
+       configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2.  This hook\r
+       function is called if a stack overflow is detected. */\r
+       taskDISABLE_INTERRUPTS();\r
+       for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationTickHook( void )\r
+{\r
+       /* This function will be called by each tick interrupt if\r
+       configUSE_TICK_HOOK is set to 1 in FreeRTOSConfig.h.  User code can be\r
+       added here, but the tick hook is called from an interrupt context, so\r
+       code must not attempt to block, and only the interrupt safe FreeRTOS API\r
+       functions can be used (those that end in FromISR()). */\r
+}\r
+/*-----------------------------------------------------------*/\r
diff --git a/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo/printf-stdarg.c b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo/printf-stdarg.c
new file mode 100644 (file)
index 0000000..6a05193
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo/printf-stdarg.c
@@ -0,0 +1,289 @@
+/*\r
+       Copyright 2001, 2002 Georges Menie (www.menie.org)\r
+       stdarg version contributed by Christian Ettinger\r
+\r
+    This program is free software; you can redistribute it and/or modify\r
+    it under the terms of the GNU Lesser General Public License as published by\r
+    the Free Software Foundation; either version 2 of the License, or\r
+    (at your option) any later version.\r
+\r
+    This program is distributed in the hope that it will be useful,\r
+    but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\r
+    GNU Lesser General Public License for more details.\r
+\r
+    You should have received a copy of the GNU Lesser General Public License\r
+    along with this program; if not, write to the Free Software\r
+    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA\r
+*/\r
+\r
+/*\r
+       putchar is the only external dependency for this file,\r
+       if you have a working putchar, leave it commented out.\r
+       If not, uncomment the define below and\r
+       replace outbyte(c) by your own function call.\r
+\r
+*/\r
+#include "FreeRTOS.h"\r
+#include <stdarg.h>\r
+#include <stdint.h>\r
+\r
+static void printchar(char **str, int c)\r
+{\r
+       if (str) {\r
+               **str = (char)c;\r
+               ++(*str);\r
+       }\r
+       else\r
+       {\r
+               /* Output char here. */\r
+       }\r
+}\r
+\r
+#define PAD_RIGHT 1\r
+#define PAD_ZERO 2\r
+\r
+static int prints(char **out, const char *string, int width, int pad)\r
+{\r
+       register int pc = 0, padchar = ' ';\r
+\r
+       if (width > 0) {\r
+               register int len = 0;\r
+               register const char *ptr;\r
+               for (ptr = string; *ptr; ++ptr) ++len;\r
+               if (len >= width) width = 0;\r
+               else width -= len;\r
+               if (pad & PAD_ZERO) padchar = '0';\r
+       }\r
+       if (!(pad & PAD_RIGHT)) {\r
+               for ( ; width > 0; --width) {\r
+                       printchar (out, padchar);\r
+                       ++pc;\r
+               }\r
+       }\r
+       for ( ; *string ; ++string) {\r
+               printchar (out, *string);\r
+               ++pc;\r
+       }\r
+       for ( ; width > 0; --width) {\r
+               printchar (out, padchar);\r
+               ++pc;\r
+       }\r
+\r
+       return pc;\r
+}\r
+\r
+/* the following should be enough for 32 bit int */\r
+#define PRINT_BUF_LEN 12\r
+\r
+static int printi(char **out, int i, int b, int sg, int width, int pad, int letbase)\r
+{\r
+       char print_buf[PRINT_BUF_LEN];\r
+       register char *s;\r
+       register int t, neg = 0, pc = 0;\r
+       register unsigned int u = (unsigned int)i;\r
+\r
+       if (i == 0) {\r
+               print_buf[0] = '0';\r
+               print_buf[1] = '\0';\r
+               return prints (out, print_buf, width, pad);\r
+       }\r
+\r
+       if (sg && b == 10 && i < 0) {\r
+               neg = 1;\r
+               u = (unsigned int)-i;\r
+       }\r
+\r
+       s = print_buf + PRINT_BUF_LEN-1;\r
+       *s = '\0';\r
+\r
+       while (u) {\r
+               t = (unsigned int)u % b;\r
+               if( t >= 10 )\r
+                       t += letbase - '0' - 10;\r
+               *--s = (char)(t + '0');\r
+               u /= b;\r
+       }\r
+\r
+       if (neg) {\r
+               if( width && (pad & PAD_ZERO) ) {\r
+                       printchar (out, '-');\r
+                       ++pc;\r
+                       --width;\r
+               }\r
+               else {\r
+                       *--s = '-';\r
+               }\r
+       }\r
+\r
+       return pc + prints (out, s, width, pad);\r
+}\r
+\r
+static int print( char **out, const char *format, va_list args )\r
+{\r
+       register int width, pad;\r
+       register int pc = 0;\r
+       char scr[2];\r
+\r
+       for (; *format != 0; ++format) {\r
+               if (*format == '%') {\r
+                       ++format;\r
+                       width = pad = 0;\r
+                       if (*format == '\0') break;\r
+                       if (*format == '%') goto out;\r
+                       if (*format == '-') {\r
+                               ++format;\r
+                               pad = PAD_RIGHT;\r
+                       }\r
+                       while (*format == '0') {\r
+                               ++format;\r
+                               pad |= PAD_ZERO;\r
+                       }\r
+                       for ( ; *format >= '0' && *format <= '9'; ++format) {\r
+                               width *= 10;\r
+                               width += *format - '0';\r
+                       }\r
+                       if( *format == 's' ) {\r
+                               register char *s = (char *)va_arg( args, int );\r
+                               pc += prints (out, s?s:"(null)", width, pad);\r
+                               continue;\r
+                       }\r
+                       if( *format == 'd' || *format == 'i' ) {\r
+                               pc += printi (out, va_arg( args, int ), 10, 1, width, pad, 'a');\r
+                               continue;\r
+                       }\r
+                       if( *format == 'x' ) {\r
+                               pc += printi (out, va_arg( args, int ), 16, 0, width, pad, 'a');\r
+                               continue;\r
+                       }\r
+                       if( *format == 'X' ) {\r
+                               pc += printi (out, va_arg( args, int ), 16, 0, width, pad, 'A');\r
+                               continue;\r
+                       }\r
+                       if( *format == 'u' ) {\r
+                               pc += printi (out, va_arg( args, int ), 10, 0, width, pad, 'a');\r
+                               continue;\r
+                       }\r
+                       if( *format == 'c' ) {\r
+                               /* char are converted to int then pushed on the stack */\r
+                               scr[0] = (char)va_arg( args, int );\r
+                               scr[1] = '\0';\r
+                               pc += prints (out, scr, width, pad);\r
+                               continue;\r
+                       }\r
+               }\r
+               else {\r
+               out:\r
+                       printchar (out, *format);\r
+                       ++pc;\r
+               }\r
+       }\r
+       if (out) **out = '\0';\r
+       va_end( args );\r
+       return pc;\r
+}\r
+\r
+int printf(const char *format, ...)\r
+{\r
+       va_list args;\r
+\r
+       va_start( args, format );\r
+       return print( 0, format, args );\r
+}\r
+\r
+int sprintf(char *out, const char *format, ...)\r
+{\r
+       va_list args;\r
+\r
+       va_start( args, format );\r
+       return print( &out, format, args );\r
+}\r
+\r
+\r
+int snprintf( char *buf, unsigned int count, const char *format, ... )\r
+{\r
+       va_list args;\r
+\r
+       ( void ) count;\r
+\r
+       va_start( args, format );\r
+       return print( &buf, format, args );\r
+}\r
+\r
+#ifdef TEST_PRINTF\r
+int main(void)\r
+{\r
+       char *ptr = "Hello world!";\r
+       char *np = 0;\r
+       int i = 5;\r
+       unsigned int bs = sizeof(int)*8;\r
+       int mi;\r
+       char buf[80];\r
+\r
+       mi = (1 << (bs-1)) + 1;\r
+       printf("%s\n", ptr);\r
+       printf("printf test\n");\r
+       printf("%s is null pointer\n", np);\r
+       printf("%d = 5\n", i);\r
+       printf("%d = - max int\n", mi);\r
+       printf("char %c = 'a'\n", 'a');\r
+       printf("hex %x = ff\n", 0xff);\r
+       printf("hex %02x = 00\n", 0);\r
+       printf("signed %d = unsigned %u = hex %x\n", -3, -3, -3);\r
+       printf("%d %s(s)%", 0, "message");\r
+       printf("\n");\r
+       printf("%d %s(s) with %%\n", 0, "message");\r
+       sprintf(buf, "justif: \"%-10s\"\n", "left"); printf("%s", buf);\r
+       sprintf(buf, "justif: \"%10s\"\n", "right"); printf("%s", buf);\r
+       sprintf(buf, " 3: %04d zero padded\n", 3); printf("%s", buf);\r
+       sprintf(buf, " 3: %-4d left justif.\n", 3); printf("%s", buf);\r
+       sprintf(buf, " 3: %4d right justif.\n", 3); printf("%s", buf);\r
+       sprintf(buf, "-3: %04d zero padded\n", -3); printf("%s", buf);\r
+       sprintf(buf, "-3: %-4d left justif.\n", -3); printf("%s", buf);\r
+       sprintf(buf, "-3: %4d right justif.\n", -3); printf("%s", buf);\r
+\r
+       return 0;\r
+}\r
+\r
+/*\r
+ * if you compile this file with\r
+ *   gcc -Wall $(YOUR_C_OPTIONS) -DTEST_PRINTF -c printf.c\r
+ * you will get a normal warning:\r
+ *   printf.c:214: warning: spurious trailing `%' in format\r
+ * this line is testing an invalid % at the end of the format string.\r
+ *\r
+ * this should display (on 32bit int machine) :\r
+ *\r
+ * Hello world!\r
+ * printf test\r
+ * (null) is null pointer\r
+ * 5 = 5\r
+ * -2147483647 = - max int\r
+ * char a = 'a'\r
+ * hex ff = ff\r
+ * hex 00 = 00\r
+ * signed -3 = unsigned 4294967293 = hex fffffffd\r
+ * 0 message(s)\r
+ * 0 message(s) with %\r
+ * justif: "left      "\r
+ * justif: "     right"\r
+ *  3: 0003 zero padded\r
+ *  3: 3    left justif.\r
+ *  3:    3 right justif.\r
+ * -3: -003 zero padded\r
+ * -3: -3   left justif.\r
+ * -3:   -3 right justif.\r
+ */\r
+\r
+#endif\r
+\r
+\r
+/* To keep linker happy. */\r
+int    write( int i, char* c, int n)\r
+{\r
+       (void)i;\r
+       (void)n;\r
+       (void)c;\r
+       return 0;\r
+}\r
+\r
diff --git a/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/.cproject b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/.cproject
new file mode 100644 (file)
index 0000000..f70f5c9
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/.cproject
@@ -0,0 +1,320 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>\r
+<?fileVersion 4.0.0?>\r
+\r
+<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">\r
+<storageModule moduleId="org.eclipse.cdt.core.settings">\r
+<cconfiguration id="cdt.managedbuild.config.gnu.cross.cortexm3.lib.debug.1468565853">\r
+<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="cdt.managedbuild.config.gnu.cross.cortexm3.lib.debug.1468565853" moduleId="org.eclipse.cdt.core.settings" name="Debug">\r
+<externalSettings>\r
+<externalSetting>\r
+<entry flags="VALUE_WORKSPACE_PATH" kind="includePath" name="/RTOSDemo_Hardware_Platform"/>\r
+<entry flags="VALUE_WORKSPACE_PATH" kind="libraryPath" name="/RTOSDemo_Hardware_Platform/Debug"/>\r
+</externalSetting>\r
+</externalSettings>\r
+<extensions>\r
+<extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>\r
+<extension id="org.eclipse.cdt.core.MakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>\r
+<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>\r
+<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>\r
+<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>\r
+</extensions>\r
+</storageModule>\r
+<storageModule moduleId="cdtBuildSystem" version="4.0.0">\r
+<configuration artifactExtension="a" artifactName="RTOSDemo_Hardware_Platform" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.staticLib" buildProperties="org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug,org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.staticLib" cleanCommand="rm -rf" description="" errorParsers="org.eclipse.cdt.core.MakeErrorParser;org.eclipse.cdt.core.GCCErrorParser;org.eclipse.cdt.core.GLDErrorParser;org.eclipse.cdt.core.GASErrorParser" id="cdt.managedbuild.config.gnu.cross.cortexm3.lib.debug.1468565853" name="Debug" parent="cdt.managedbuild.config.gnu.cross.cortexm3.lib.debug">\r
+<folderInfo id="cdt.managedbuild.config.gnu.cross.cortexm3.lib.debug.1468565853." name="/" resourcePath="">\r
+<toolChain id="cdt.managedbuild.toolchain.gnu.cross.cortexm3.lib.debug.409640005" name="Microsemi Cortex-M3 Tools" superClass="cdt.managedbuild.toolchain.gnu.cross.cortexm3.lib.debug">\r
+<targetPlatform id="cdt.managedbuild.target.gnu.platform.cross.cortexm3.lib.debug.328970973" name="%PlatformName.Dbg" superClass="cdt.managedbuild.target.gnu.platform.cross.cortexm3.lib.debug"/>\r
+<builder buildPath="${workspace_loc:/RTOSDemo_Hardware_Platform/Debug}" id="cdt.managedbuild.target.gnu.builder.cross.cortexm3.lib.debug.568072199" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" superClass="cdt.managedbuild.target.gnu.builder.cross.cortexm3.lib.debug"/>\r
+<tool id="cdt.managedbuild.tool.gnu.c.compiler.cross.cortexm3.lib.debug.2065819927" name="GNU C Compiler" superClass="cdt.managedbuild.tool.gnu.c.compiler.cross.cortexm3.lib.debug">\r
+<option defaultValue="gnu.c.optimization.level.none" id="gnu.c.compiler.cross.cortexm3.lib.debug.option.optimization.level.681489611" name="Optimization Level" superClass="gnu.c.compiler.cross.cortexm3.lib.debug.option.optimization.level" valueType="enumerated"/>\r
+<option defaultValue="gnu.c.optimization.level.none" id="gnu.c.compiler.cross.cortexm3.lib.debug.option.debugging.level.1682080951" name="Debug Level" superClass="gnu.c.compiler.cross.cortexm3.lib.debug.option.debugging.level" value="gnu.c.debugging.level.max" valueType="enumerated"/>\r
+<option id="gnu.c.compiler.option.include.paths.1398648520" name="Include paths (-I)" superClass="gnu.c.compiler.option.include.paths" valueType="includePath">\r
+<listOptionValue builtIn="false" value="${workspace_loc:/RTOSDemo_Hardware_Platform/}"/>\r
+<listOptionValue builtIn="false" value="${workspace_loc:/RTOSDemo_Hardware_Platform/CMSIS}"/>\r
+<listOptionValue builtIn="false" value="${workspace_loc:/RTOSDemo_Hardware_Platform/CMSIS/startup_gcc}"/>\r
+<listOptionValue builtIn="false" value="${workspace_loc:/RTOSDemo_Hardware_Platform/drivers}"/>\r
+<listOptionValue builtIn="false" value="${workspace_loc:/RTOSDemo_Hardware_Platform/drivers/mss_gpio}"/>\r
+<listOptionValue builtIn="false" value="${workspace_loc:/RTOSDemo_Hardware_Platform/drivers/mss_hpdma}"/>\r
+<listOptionValue builtIn="false" value="${workspace_loc:/RTOSDemo_Hardware_Platform/drivers/mss_nvm}"/>\r
+<listOptionValue builtIn="false" value="${workspace_loc:/RTOSDemo_Hardware_Platform/drivers/mss_rtc}"/>\r
+<listOptionValue builtIn="false" value="${workspace_loc:/RTOSDemo_Hardware_Platform/drivers/mss_sys_services}"/>\r
+<listOptionValue builtIn="false" value="${workspace_loc:/RTOSDemo_Hardware_Platform/drivers/mss_timer}"/>\r
+<listOptionValue builtIn="false" value="${workspace_loc:/RTOSDemo_Hardware_Platform/drivers/mss_uart}"/>\r
+<listOptionValue builtIn="false" value="${workspace_loc:/RTOSDemo_Hardware_Platform/drivers_config}"/>\r
+<listOptionValue builtIn="false" value="${workspace_loc:/RTOSDemo_Hardware_Platform/drivers_config/sys_config}"/>\r
+<listOptionValue builtIn="false" value="${workspace_loc:/RTOSDemo_Hardware_Platform/hal}"/>\r
+<listOptionValue builtIn="false" value="${workspace_loc:/RTOSDemo_Hardware_Platform/hal/CortexM3}"/>\r
+<listOptionValue builtIn="false" value="${workspace_loc:/RTOSDemo_Hardware_Platform/hal/CortexM3/GNU}"/>\r
+</option>\r
+<option id="gnu.c.compiler.option.optimization.flags.224943415" name="Other optimization flags" superClass="gnu.c.compiler.option.optimization.flags" value="-ffunction-sections -fdata-sections" valueType="string"/>\r
+<inputType id="cdt.managedbuild.tool.gnu.c.compiler.input.916892465" superClass="cdt.managedbuild.tool.gnu.c.compiler.input"/>\r
+</tool>\r
+<tool id="cdt.managedbuild.tool.gnu.cpp.compiler.cross.cortexm3.lib.debug.395470401" name="GNU C++ Compiler" superClass="cdt.managedbuild.tool.gnu.cpp.compiler.cross.cortexm3.lib.debug">\r
+<option id="gnu.cpp.compiler.cross.cortexm3.lib.debug.option.optimization.level.1205883536" name="Optimization Level" superClass="gnu.cpp.compiler.cross.cortexm3.lib.debug.option.optimization.level" value="gnu.cpp.compiler.optimization.level.none" valueType="enumerated"/>\r
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+<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>\r
+<storageModule moduleId="org.eclipse.cdt.internal.ui.text.commentOwnerProjectMappings"/>\r
+<storageModule moduleId="org.eclipse.cdt.core.language.mapping"/>\r
+</cconfiguration>\r
+</storageModule>\r
+<storageModule moduleId="cdtBuildSystem" version="4.0.0">\r
+<project id="RTOSDemo_Hardware_Platform.cdt.managedbuild.target.gnu.cross.cortexm3.lib.597503304" name="Static Library" projectType="cdt.managedbuild.target.gnu.cross.cortexm3.lib"/>\r
+</storageModule>\r
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diff --git a/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/.project b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/.project
new file mode 100644 (file)
index 0000000..876bbbc
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/.project
@@ -0,0 +1,80 @@
+<?xml version="1.0" encoding="UTF-8"?>\r
+<projectDescription>\r
+       <name>RTOSDemo_Hardware_Platform</name>\r
+       <comment></comment>\r
+       <projects>\r
+       </projects>\r
+       <buildSpec>\r
+               <buildCommand>\r
+                       <name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>\r
+                       <arguments>\r
+                               <dictionary>\r
+                                       <key>?name?</key>\r
+                                       <value></value>\r
+                               </dictionary>\r
+                               <dictionary>\r
+                                       <key>org.eclipse.cdt.make.core.append_environment</key>\r
+                                       <value>true</value>\r
+                               </dictionary>\r
+                               <dictionary>\r
+                                       <key>org.eclipse.cdt.make.core.autoBuildTarget</key>\r
+                                       <value>all</value>\r
+                               </dictionary>\r
+                               <dictionary>\r
+                                       <key>org.eclipse.cdt.make.core.buildArguments</key>\r
+                                       <value></value>\r
+                               </dictionary>\r
+                               <dictionary>\r
+                                       <key>org.eclipse.cdt.make.core.buildCommand</key>\r
+                                       <value>make</value>\r
+                               </dictionary>\r
+                               <dictionary>\r
+                                       <key>org.eclipse.cdt.make.core.buildLocation</key>\r
+                                       <value>${workspace_loc:/RTOSDemo_Hardware_Platform/Debug}</value>\r
+                               </dictionary>\r
+                               <dictionary>\r
+                                       <key>org.eclipse.cdt.make.core.cleanBuildTarget</key>\r
+                                       <value>clean</value>\r
+                               </dictionary>\r
+                               <dictionary>\r
+                                       <key>org.eclipse.cdt.make.core.contents</key>\r
+                                       <value>org.eclipse.cdt.make.core.activeConfigSettings</value>\r
+                               </dictionary>\r
+                               <dictionary>\r
+                                       <key>org.eclipse.cdt.make.core.enableAutoBuild</key>\r
+                                       <value>true</value>\r
+                               </dictionary>\r
+                               <dictionary>\r
+                                       <key>org.eclipse.cdt.make.core.enableCleanBuild</key>\r
+                                       <value>true</value>\r
+                               </dictionary>\r
+                               <dictionary>\r
+                                       <key>org.eclipse.cdt.make.core.enableFullBuild</key>\r
+                                       <value>true</value>\r
+                               </dictionary>\r
+                               <dictionary>\r
+                                       <key>org.eclipse.cdt.make.core.fullBuildTarget</key>\r
+                                       <value>all</value>\r
+                               </dictionary>\r
+                               <dictionary>\r
+                                       <key>org.eclipse.cdt.make.core.stopOnError</key>\r
+                                       <value>true</value>\r
+                               </dictionary>\r
+                               <dictionary>\r
+                                       <key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>\r
+                                       <value>true</value>\r
+                               </dictionary>\r
+                       </arguments>\r
+               </buildCommand>\r
+               <buildCommand>\r
+                       <name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>\r
+                       <arguments>\r
+                       </arguments>\r
+               </buildCommand>\r
+       </buildSpec>\r
+       <natures>\r
+               <nature>org.eclipse.cdt.core.cnature</nature>\r
+               <nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>\r
+               <nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>\r
+       </natures>\r
+</projectDescription>\r
diff --git a/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/CMSIS/hw_reg_io.h b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/CMSIS/hw_reg_io.h
new file mode 100644 (file)
index 0000000..e6ff7c1
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/CMSIS/hw_reg_io.h
@@ -0,0 +1,113 @@
+/*******************************************************************************\r
+ * (c) Copyright 2011-2013 Microsemi SoC Products Group. All rights reserved.\r
+ *\r
+ *  SmartFusion2 Cortex Microcontroller Software Interface - Peripheral\r
+ *  Access Layer.\r
+ *\r
+ *  This file provides interfaces to perform register and register bit level \r
+ *  read / write operations. These interfaces support bit-banding in case of \r
+ *  Cortex-M3 CPU.\r
+ *\r
+ * SVN $Revision: 5263 $\r
+ * SVN $Date: 2013-03-21 14:44:58 +0000 (Thu, 21 Mar 2013) $\r
+ */\r
+\r
+#ifndef HW_REG_IO_H_\r
+#define HW_REG_IO_H_\r
+\r
+#include <stdint.h>                       /* Include standard types */\r
+\r
+#if defined ( __CC_ARM   )\r
+  #define __INLINE         __inline       /*!< inline keyword for ARM Compiler       */\r
+\r
+#elif defined ( __ICCARM__ )\r
+  #define __INLINE        inline          /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */\r
+\r
+#elif defined   (  __GNUC__  )\r
+  #define __INLINE        inline          /*!< inline keyword for GNU Compiler       */\r
+#endif\r
+\r
+/*****************************************************************************************\r
+ * Definitions for register access\r
+ */\r
+\r
+#define HW_REG(addr)            (*((volatile uint32_t *) (addr)))\r
+\r
+static __INLINE void write_reg32(volatile uint32_t * reg, uint32_t val)\r
+{\r
+    HW_REG(reg) = val;\r
+}\r
+static __INLINE void write_reg16(volatile uint16_t * reg, uint16_t val)\r
+{\r
+    HW_REG(reg) = val;\r
+}\r
+static __INLINE void write_reg8(volatile uint8_t * reg, uint8_t val)\r
+{\r
+    HW_REG(reg) = val;\r
+}\r
+\r
+static __INLINE uint32_t read_reg32(volatile uint32_t * reg)\r
+{\r
+    return ( HW_REG(reg) );\r
+}\r
+static __INLINE uint16_t read_reg16(volatile uint16_t * reg)\r
+{\r
+    return ( HW_REG(reg) );\r
+}\r
+static __INLINE uint8_t read_reg8(volatile uint8_t * reg)\r
+{\r
+    return ( HW_REG(reg) );\r
+}\r
+/*****************************************************************************************\r
+ * Definitions for register bits access using bit-band aliases for Cortex-M3 \r
+ */\r
+#define BITBAND(addr,bitnum)    (((uint32_t)addr & 0xF0000000)+0x02000000+(((uint32_t)addr & 0xFFFFF)<<5)+(bitnum<<2))\r
+#define HW_REG_BIT(reg,bitnum)  (*(volatile unsigned int *)((BITBAND(reg,bitnum))))\r
+\r
+/*****************************************************************************************\r
+ * Functions to set a bit field in Cortex-M3 \r
+ */\r
+static __INLINE void set_bit_reg32(volatile uint32_t * reg, uint8_t bit)\r
+{\r
+    HW_REG_BIT(reg,bit) = 0x1;\r
+}\r
+static __INLINE void set_bit_reg16(volatile uint16_t * reg, uint8_t bit)\r
+{\r
+    HW_REG_BIT(reg,bit) = 0x1;\r
+}\r
+static __INLINE void set_bit_reg8(volatile uint8_t * reg, uint8_t bit)\r
+{\r
+    HW_REG_BIT(reg,bit) = 0x1;\r
+}\r
+/*****************************************************************************************\r
+ * Functions to clear a bit field in Cortex-M3\r
+ */\r
+static __INLINE void clear_bit_reg32(volatile uint32_t * reg, uint8_t bit)\r
+{\r
+    HW_REG_BIT(reg,bit) = 0x0;\r
+}\r
+static __INLINE void clear_bit_reg16(volatile uint16_t * reg, uint8_t bit)\r
+{\r
+    HW_REG_BIT(reg,bit) = 0x0;\r
+}\r
+static __INLINE void clear_bit_reg8(volatile uint8_t * reg, uint8_t bit)\r
+{\r
+    HW_REG_BIT(reg,bit) = 0x0;\r
+}\r
+/*****************************************************************************************\r
+ * Functions to read a bit field in Cortex-M3\r
+ */\r
+static __INLINE uint8_t read_bit_reg32(volatile uint32_t * reg, uint8_t bit)\r
+{\r
+    return (HW_REG_BIT(reg,bit));\r
+}\r
+static __INLINE uint8_t read_bit_reg16(volatile uint16_t * reg, uint8_t bit)\r
+{\r
+    return (HW_REG_BIT(reg,bit));\r
+}\r
+static __INLINE uint8_t read_bit_reg8(volatile uint8_t * reg, uint8_t bit)\r
+{\r
+    return (HW_REG_BIT(reg,bit));\r
+}\r
+\r
+#endif /* HW_REG_IO_H_ */\r
diff --git a/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/CMSIS/m2sxxx.h b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/CMSIS/m2sxxx.h
new file mode 100644 (file)
index 0000000..c2cd72b
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/CMSIS/m2sxxx.h
@@ -0,0 +1,2749 @@
+/*******************************************************************************\r
+ * (c) Copyright 2010-2013 Microsemi SoC Products Group. All rights reserved.\r
+ *\r
+ *  Microsemi SmartFusion2 Cortex Microcontroller Software Interface - Peripheral\r
+ *  Access Layer.\r
+ *\r
+ *  This file describes the interrupt assignment and peripheral registers for\r
+ *  the SmartFusion2 familly of devices.\r
+ *\r
+ * SVN $Revision: 5267 $\r
+ * SVN $Date: 2013-03-21 20:45:39 +0000 (Thu, 21 Mar 2013) $\r
+ */\r
+#ifndef __SMARTFUSION2_CMSIS_PAL_H__\r
+#define __SMARTFUSION2_CMSIS_PAL_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/*\r
+ * ==========================================================================\r
+ * ---------- Interrupt Number Definition -----------------------------------\r
+ * ==========================================================================\r
+ */\r
+\r
+typedef enum IRQn\r
+{\r
+/******  Cortex-M3 Processor Exceptions Numbers *********************************************************/\r
+  NonMaskableInt_IRQn             = -14,      /*!< 2 Non Maskable Interrupt - Watchdog timeout interrupt*/\r
+  HardFault_IRQn                  = -13,      /*!< 2 Hard Fault Interrupt                               */\r
+  MemoryManagement_IRQn           = -12,      /*!< 4 Cortex-M3 Memory Management Interrupt              */\r
+  BusFault_IRQn                   = -11,      /*!< 5 Cortex-M3 Bus Fault Interrupt                      */\r
+  UsageFault_IRQn                 = -10,      /*!< 6 Cortex-M3 Usage Fault Interrupt                    */\r
+  SVCall_IRQn                     = -5,       /*!< 11 Cortex-M3 SV Call Interrupt                       */\r
+  DebugMonitor_IRQn               = -4,       /*!< 12 Cortex-M3 Debug Monitor Interrupt                 */\r
+  PendSV_IRQn                     = -2,       /*!< 14 Cortex-M3 Pend SV Interrupt                       */\r
+  SysTick_IRQn                    = -1,       /*!< 15 Cortex-M3 System Tick Interrupt                   */\r
+\r
+/******  SmartFusion2 specific Interrupt Numbers *********************************************************/\r
+  WdogWakeup_IRQn                 = 0,        /*!< WatchDog wakeup interrupt                            */\r
+  RTC_Wakeup_IRQn                 = 1,        /*!< RTC wakeup interrupt                                 */\r
+  SPI0_IRQn                       = 2,        /*!< SPI0 interrupt                                       */\r
+  SPI1_IRQn                       = 3,        /*!< SPI1 interrupt                                       */\r
+  I2C0_IRQn                       = 4,        /*!< I2C0 interrupt                                       */\r
+  I2C0_SMBAlert_IRQn              = 5,        /*!< I2C0 SMBus Alert interrupt                           */\r
+  I2C0_SMBus_IRQn                 = 6,        /*!< I2C0 SMBus Suspend interrupt                         */\r
+  I2C1_IRQn                       = 7,        /*!< I2C1 interrupt                                       */\r
+  I2C1_SMBAlert_IRQn              = 8,        /*!< I2C1 SMBus Alert interrupt                           */\r
+  I2C1_SMBus_IRQn                 = 9,        /*!< I2C1 SMBus Suspend interrupt                         */\r
+  UART0_IRQn                      = 10,       /*!< UART0 interrupt                                      */\r
+  UART1_IRQn                      = 11,       /*!< UART1 interrupt                                      */\r
+  EthernetMAC_IRQn                = 12,       /*!< Ethernet MAC interrupt                               */\r
+  DMA_IRQn                        = 13,       /*!< Peripheral DMA interrupt                             */\r
+  Timer1_IRQn                     = 14,       /*!< Timer1 interrupt                                     */\r
+  Timer2_IRQn                     = 15,       /*!< Timer2 interrupt                                     */\r
+  CAN_IRQn                        = 16,       /*!< CAN controller interrupt                             */\r
+  ENVM0_IRQn                      = 17,       /*!< eNVM0 operation completion interrupt                 */\r
+  ENVM1_IRQn                      = 18,       /*!< eNVM1 operation completion interrupt                 */\r
+  ComBlk_IRQn                     = 19,       /*!< COM block interrupt                                  */\r
+  USB_IRQn                        = 20,       /*!< USB interrupt                                        */\r
+  USB_DMA_IRQn                    = 21,       /*!< USB DMA interrupt                                    */\r
+  PLL_Lock_IRQn                   = 22,       /*!< PLL lock interrupt                                   */\r
+  PLL_LockLost_IRQn               = 23,       /*!< PLL loss of lock interrupt                           */\r
+  CommSwitchError_IR              = 24,       /*!< Communications Switch error interrupt                */\r
+  CacheError_IRQn                 = 25,       /*!< Cache error interrupt                                */\r
+  DDR_IRQn                        = 26,       /*!< DDR controller interrupt                             */\r
+  HPDMA_Complete_IRQn             = 27,       /*!< High speed DMA transfer complete interrupt           */\r
+  HPDMA_Error_IRQn                = 28,       /*!< High speed DMA transfer error interrupt              */\r
+  ECC_Error_IRQn                  = 29,       /*!< ECC error detected                                   */\r
+  MDDR_IOCalib_IRQn               = 30,       /*!< MDDR Calibration finished interrupt                  */\r
+  FAB_PLL_Lock_IRQn               = 31,       /*!< MSSDDR Fabric PLL lock interrupt                   */\r
+  FAB_PLL_LockLost_IRQn           = 32,       /*!< MSSDDR Fabric PLL lock lost interrupt              */\r
+  FIC64_IRQn                      = 33,       /*!< FIC64 interrupt                                      */\r
+  FabricIrq0_IRQn                 = 34,       /*!< FPGA fabric interrupt 0                              */\r
+  FabricIrq1_IRQn                 = 35,       /*!< FPGA fabric interrupt 1                              */\r
+  FabricIrq2_IRQn                 = 36,       /*!< FPGA fabric interrupt 2                              */\r
+  FabricIrq3_IRQn                 = 37,       /*!< FPGA fabric interrupt 3                              */\r
+  FabricIrq4_IRQn                 = 38,       /*!< FPGA fabric interrupt 4                              */\r
+  FabricIrq5_IRQn                 = 39,       /*!< FPGA fabric interrupt 5                              */\r
+  FabricIrq6_IRQn                 = 40,       /*!< FPGA fabric interrupt 6                              */\r
+  FabricIrq7_IRQn                 = 41,       /*!< FPGA fabric interrupt 7                              */\r
+  FabricIrq8_IRQn                 = 42,       /*!< FPGA fabric interrupt 8                              */\r
+  FabricIrq9_IRQn                 = 43,       /*!< FPGA fabric interrupt 9                              */\r
+  FabricIrq10_IRQn                = 44,       /*!< FPGA fabric interrupt 10                             */\r
+  FabricIrq11_IRQn                = 45,       /*!< FPGA fabric interrupt 11                             */\r
+  FabricIrq12_IRQn                = 46,       /*!< FPGA fabric interrupt 12                             */\r
+  FabricIrq13_IRQn                = 47,       /*!< FPGA fabric interrupt 13                             */\r
+  FabricIrq14_IRQn                = 48,       /*!< FPGA fabric interrupt 14                             */\r
+  FabricIrq15_IRQn                = 49,       /*!< FPGA fabric interrupt 15                             */  \r
+  GPIO0_IRQn                      = 50,       /*!< GPIO 0 interrupt                                     */\r
+  GPIO1_IRQn                      = 51,       /*!< GPIO 1 interrupt                                     */\r
+  GPIO2_IRQn                      = 52,       /*!< GPIO 2 interrupt                                     */\r
+  GPIO3_IRQn                      = 53,       /*!< GPIO 3 interrupt                                     */\r
+  GPIO4_IRQn                      = 54,       /*!< GPIO 4 interrupt                                     */\r
+  GPIO5_IRQn                      = 55,       /*!< GPIO 5 interrupt                                     */\r
+  GPIO6_IRQn                      = 56,       /*!< GPIO 6 interrupt                                     */\r
+  GPIO7_IRQn                      = 57,       /*!< GPIO 7 interrupt                                     */\r
+  GPIO8_IRQn                      = 58,       /*!< GPIO 8 interrupt                                     */\r
+  GPIO9_IRQn                      = 59,       /*!< GPIO 9 interrupt                                     */\r
+  GPIO10_IRQn                     = 60,       /*!< GPIO 10 interrupt                                    */\r
+  GPIO11_IRQn                     = 61,       /*!< GPIO 11 interrupt                                    */\r
+  GPIO12_IRQn                     = 62,       /*!< GPIO 12 interrupt                                    */\r
+  GPIO13_IRQn                     = 63,       /*!< GPIO 13 interrupt                                    */\r
+  GPIO14_IRQn                     = 64,       /*!< GPIO 14 interrupt                                    */\r
+  GPIO15_IRQn                     = 65,       /*!< GPIO 15 interrupt                                    */\r
+  GPIO16_IRQn                     = 66,       /*!< GPIO 16 interrupt                                    */\r
+  GPIO17_IRQn                     = 67,       /*!< GPIO 17 interrupt                                    */\r
+  GPIO18_IRQn                     = 68,       /*!< GPIO 18 interrupt                                    */\r
+  GPIO19_IRQn                     = 69,       /*!< GPIO 19 interrupt                                    */\r
+  GPIO20_IRQn                     = 70,       /*!< GPIO 20 interrupt                                    */\r
+  GPIO21_IRQn                     = 71,       /*!< GPIO 21 interrupt                                    */\r
+  GPIO22_IRQn                     = 72,       /*!< GPIO 22 interrupt                                    */\r
+  GPIO23_IRQn                     = 73,       /*!< GPIO 23 interrupt                                    */\r
+  GPIO24_IRQn                     = 74,       /*!< GPIO 24 interrupt                                    */\r
+  GPIO25_IRQn                     = 75,       /*!< GPIO 25 interrupt                                    */ \r
+  GPIO26_IRQn                     = 76,       /*!< GPIO 26 interrupt                                    */\r
+  GPIO27_IRQn                     = 77,       /*!< GPIO 27 interrupt                                    */\r
+  GPIO28_IRQn                     = 78,       /*!< GPIO 28 interrupt                                    */\r
+  GPIO29_IRQn                     = 79,       /*!< GPIO 29 interrupt                                    */\r
+  GPIO30_IRQn                     = 80,       /*!< GPIO 30 interrupt                                    */\r
+  GPIO31_IRQn                     = 81        /*!< GPIO 31 interrupt                                    */\r
+} IRQn_Type;\r
+\r
+/*\r
+ * ==========================================================================\r
+ * ----------- Processor and Core Peripheral Section ------------------------\r
+ * ==========================================================================\r
+ */\r
+#define __CM3_REV                 0x0201    /*!< Core revision r2p1                              */\r
+#define __MPU_PRESENT             1         /*!< MPU present or not                              */\r
+#define __NVIC_PRIO_BITS          4         /*!< Number of Bits used for Priority Levels         */\r
+#define __Vendor_SysTickConfig    0         /*!< Set to 1 if different SysTick Config is used    */\r
+\r
+#include <core_cm3.h>   /* Cortex-M3 processor and core peripherals           */\r
+\r
+/******************************************************************************/\r
+/*                Device Specific Peripheral registers structures             */\r
+/******************************************************************************/\r
+#if defined   ( __CC_ARM   )\r
+  /* Enable anonymous unions when building using Keil-MDK */\r
+  #pragma anon_unions\r
+#endif\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/*----------------------------------- UART -----------------------------------*/\r
+/*----------------------------------------------------------------------------*/\r
+typedef struct\r
+{\r
+    union\r
+    {\r
+        __I  uint8_t    RBR;\r
+        __O  uint8_t    THR;\r
+        __IO uint8_t    DLR;\r
+             uint32_t   RESERVED0;\r
+    };\r
+\r
+    union\r
+    {\r
+        __IO uint8_t  DMR;\r
+        __IO uint8_t  IER;\r
+             uint32_t RESERVED1;\r
+    };\r
+\r
+    union\r
+    {\r
+        __IO uint8_t  IIR;\r
+        __IO uint8_t  FCR;\r
+             uint32_t RESERVED2;\r
+    };\r
+\r
+    __IO uint8_t  LCR;\r
+         uint8_t  RESERVED3[3];\r
+\r
+    __IO uint8_t  MCR;\r
+         uint8_t  RESERVED4[3];\r
+\r
+    __I  uint8_t  LSR;\r
+         uint8_t  RESERVED5[3];\r
+\r
+    __I  uint8_t  MSR;\r
+         uint8_t  RESERVED6[3];\r
+\r
+    __IO uint8_t  SR;\r
+         uint8_t  RESERVED7[7];\r
+\r
+    __IO uint8_t  IEM;\r
+         uint8_t  RESERVED8[3];\r
+\r
+    __IO uint8_t  IIM;\r
+         uint8_t  RESERVED9[7];\r
+\r
+    __IO uint8_t  MM0;\r
+         uint8_t  RESERVED10[3];\r
+\r
+    __IO uint8_t  MM1;\r
+         uint8_t  RESERVED11[3];\r
+\r
+    __IO uint8_t  MM2;\r
+         uint8_t  RESERVED12[3];\r
+\r
+    __IO uint8_t  DFR;\r
+         uint8_t  RESERVED13[7];\r
+\r
+     __IO uint8_t GFR;\r
+         uint8_t  RESERVED14[3];\r
+\r
+     __IO uint8_t TTG;\r
+         uint8_t  RESERVED15[3];\r
+\r
+     __IO uint8_t RTO;\r
+         uint8_t  RESERVED16[3];\r
+\r
+     __IO uint8_t ADR;\r
+         uint8_t  RESERVED17[3];\r
+\r
+} UART_TypeDef;\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/*----------------------------------- I2C ------------------------------------*/\r
+/*----------------------------------------------------------------------------*/\r
+typedef struct\r
+{\r
+    __IO uint8_t  CTRL;\r
+         uint8_t  RESERVED0;\r
+         uint16_t RESERVED1;\r
+         uint8_t  STATUS;\r
+         uint8_t  RESERVED2;\r
+         uint16_t RESERVED3;\r
+    __IO uint8_t  DATA;\r
+         uint8_t  RESERVED4;\r
+         uint16_t RESERVED5;\r
+    __IO uint8_t  ADDR;\r
+         uint8_t  RESERVED6;\r
+         uint16_t RESERVED7;\r
+    __IO uint8_t  SMBUS;\r
+         uint8_t  RESERVED8;\r
+         uint16_t RESERVED9;\r
+    __IO uint8_t  FREQ;\r
+         uint8_t  RESERVED10;\r
+         uint16_t RESERVED11;\r
+    __IO uint8_t  GLITCHREG;\r
+         uint8_t  RESERVED12;\r
+         uint16_t RESERVED13;\r
+    __IO uint8_t  SLAVE1_ADDR;\r
+         uint8_t  RESERVED14;\r
+         uint16_t RESERVED15;\r
+} I2C_TypeDef;\r
+\r
+/*------------------------------------------------------------------------------\r
+ * I2C bit band\r
+ */\r
+typedef struct\r
+{\r
+    __IO uint32_t CTRL_CR0;\r
+    __IO uint32_t CTRL_CR1;\r
+    __IO uint32_t CTRL_AA;\r
+    __IO uint32_t CTRL_SI;\r
+    __IO uint32_t CTRL_STO;\r
+    __IO uint32_t CTRL_STA;\r
+    __IO uint32_t CTRL_ENS1;\r
+    __IO uint32_t CTRL_CR2;\r
+         uint32_t RESERVED0[56];\r
+    __IO uint32_t DATA_DIR;\r
+         uint32_t RESERVED1[31];\r
+    __IO uint32_t ADDR_GC;\r
+} I2C_BitBand_TypeDef;\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/*----------------------------------- SPI ------------------------------------*/\r
+/*----------------------------------------------------------------------------*/\r
+typedef struct\r
+{\r
+    __IO uint32_t CONTROL;\r
+    __IO uint32_t TXRXDF_SIZE;\r
+    __I  uint32_t STATUS;\r
+    __O  uint32_t INT_CLEAR;\r
+    __I  uint32_t RX_DATA;\r
+    __O  uint32_t TX_DATA;\r
+    __IO uint32_t CLK_GEN;\r
+    __IO uint32_t SLAVE_SELECT;\r
+    __I  uint32_t MIS;\r
+    __I  uint32_t RIS;\r
+    __IO uint32_t CONTROL2;\r
+    __IO uint32_t COMMAND;\r
+    __IO uint32_t PKTSIZE;\r
+    __IO uint32_t CMDSIZE;\r
+    __IO uint32_t HWSTATUS;\r
+    __IO uint32_t STAT8;\r
+    __IO uint32_t CTRL0;\r
+    __IO uint32_t CTRL1;\r
+    __IO uint32_t CTRL2;\r
+    __IO uint32_t CTRL3;\r
+} SPI_TypeDef;\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/*----------------------------------- GPIO -----------------------------------*/\r
+/*----------------------------------------------------------------------------*/\r
+typedef struct\r
+{\r
+    __IO uint32_t GPIO_0_CFG;\r
+    __IO uint32_t GPIO_1_CFG;\r
+    __IO uint32_t GPIO_2_CFG;\r
+    __IO uint32_t GPIO_3_CFG;\r
+    __IO uint32_t GPIO_4_CFG;\r
+    __IO uint32_t GPIO_5_CFG;\r
+    __IO uint32_t GPIO_6_CFG;\r
+    __IO uint32_t GPIO_7_CFG;\r
+    __IO uint32_t GPIO_8_CFG;\r
+    __IO uint32_t GPIO_9_CFG;\r
+    __IO uint32_t GPIO_10_CFG;\r
+    __IO uint32_t GPIO_11_CFG;\r
+    __IO uint32_t GPIO_12_CFG;\r
+    __IO uint32_t GPIO_13_CFG;\r
+    __IO uint32_t GPIO_14_CFG;\r
+    __IO uint32_t GPIO_15_CFG;\r
+    __IO uint32_t GPIO_16_CFG;\r
+    __IO uint32_t GPIO_17_CFG;\r
+    __IO uint32_t GPIO_18_CFG;\r
+    __IO uint32_t GPIO_19_CFG;\r
+    __IO uint32_t GPIO_20_CFG;\r
+    __IO uint32_t GPIO_21_CFG;\r
+    __IO uint32_t GPIO_22_CFG;\r
+    __IO uint32_t GPIO_23_CFG;\r
+    __IO uint32_t GPIO_24_CFG;\r
+    __IO uint32_t GPIO_25_CFG;\r
+    __IO uint32_t GPIO_26_CFG;\r
+    __IO uint32_t GPIO_27_CFG;\r
+    __IO uint32_t GPIO_28_CFG;\r
+    __IO uint32_t GPIO_29_CFG;\r
+    __IO uint32_t GPIO_30_CFG;\r
+    __IO uint32_t GPIO_31_CFG;\r
+    __IO uint32_t GPIO_IRQ;\r
+    __I  uint32_t GPIO_IN;\r
+    __IO uint32_t GPIO_OUT;\r
+} GPIO_TypeDef;\r
+\r
+/*------------------------------------------------------------------------------\r
+ * GPIO bit band\r
+ */\r
+typedef struct\r
+{\r
+    __IO uint32_t GPIO_0_CFG[32];\r
+    __IO uint32_t GPIO_1_CFG[32];\r
+    __IO uint32_t GPIO_2_CFG[32];\r
+    __IO uint32_t GPIO_3_CFG[32];\r
+    __IO uint32_t GPIO_4_CFG[32];\r
+    __IO uint32_t GPIO_5_CFG[32];\r
+    __IO uint32_t GPIO_6_CFG[32];\r
+    __IO uint32_t GPIO_7_CFG[32];\r
+    __IO uint32_t GPIO_8_CFG[32];\r
+    __IO uint32_t GPIO_9_CFG[32];\r
+    __IO uint32_t GPIO_10_CFG[32];\r
+    __IO uint32_t GPIO_11_CFG[32];\r
+    __IO uint32_t GPIO_12_CFG[32];\r
+    __IO uint32_t GPIO_13_CFG[32];\r
+    __IO uint32_t GPIO_14_CFG[32];\r
+    __IO uint32_t GPIO_15_CFG[32];\r
+    __IO uint32_t GPIO_16_CFG[32];\r
+    __IO uint32_t GPIO_17_CFG[32];\r
+    __IO uint32_t GPIO_18_CFG[32];\r
+    __IO uint32_t GPIO_19_CFG[32];\r
+    __IO uint32_t GPIO_20_CFG[32];\r
+    __IO uint32_t GPIO_21_CFG[32];\r
+    __IO uint32_t GPIO_22_CFG[32];\r
+    __IO uint32_t GPIO_23_CFG[32];\r
+    __IO uint32_t GPIO_24_CFG[32];\r
+    __IO uint32_t GPIO_25_CFG[32];\r
+    __IO uint32_t GPIO_26_CFG[32];\r
+    __IO uint32_t GPIO_27_CFG[32];\r
+    __IO uint32_t GPIO_28_CFG[32];\r
+    __IO uint32_t GPIO_29_CFG[32];\r
+    __IO uint32_t GPIO_30_CFG[32];\r
+    __IO uint32_t GPIO_31_CFG[32];\r
+    __IO uint32_t GPIO_IRQ[32];\r
+    __I  uint32_t GPIO_IN[32];\r
+    __IO uint32_t GPIO_OUT[32];\r
+} GPIO_BitBand_TypeDef;\r
+\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/*--------------------------------- HPDMA ------------------------------------*/\r
+/*----------------------------------------------------------------------------*/\r
+\r
+typedef struct\r
+{\r
+    __IO uint32_t HPDMASAR_REG              ;\r
+    __IO uint32_t HPDMADAR_REG              ;\r
+    __IO uint32_t HPDMACR_REG               ;\r
+    __I  uint32_t HPDMASR_REG               ;\r
+    __I  uint32_t HPDMAPTR_REG              ;\r
+}HPDMA_Descriptor_TypeDef;\r
+\r
+typedef struct\r
+{\r
+    __I  uint32_t HPDMAEDR_REG              ;\r
+    HPDMA_Descriptor_TypeDef  Descriptor[4] ;\r
+    __O  uint32_t HPDMAICR_REG              ;\r
+    __I  uint32_t HPDMADR_REG               ;\r
+} HPDMA_TypeDef;\r
+\r
+typedef struct\r
+{\r
+         uint32_t RESERVED0[64];\r
+    __IO uint32_t HPDMACR_XFR_SIZE[16]     ;\r
+    __IO uint32_t HPDMACR_DCP_VALID        ;\r
+    __IO uint32_t HPDMACR_DCP_XFR_DIR      ;\r
+    __IO uint32_t HPDMACR_DCP_CLR          ;\r
+    __IO uint32_t HPDMACR_DCP_PAUSE        ;\r
+    __IO uint32_t HPDMACR_XFR_CMP_INT      ;\r
+    __IO uint32_t HPDMACR_XFR_ERR_INT      ;\r
+    __IO uint32_t HPDMACR_NON_WORD_INT     ;\r
+         uint32_t RESERVED1[9];\r
+\r
+    __I  uint32_t HPDMASR_DCP_ACTIVE       ;\r
+    __I  uint32_t HPDMASR_DCP_CMPLET       ;\r
+    __I  uint32_t HPDMASR_DCP_SERR         ;\r
+    __I  uint32_t HPDMASR_DCP_DERR         ;\r
+         uint32_t RESERVED2[60]            ;\r
+}HPDMA_Descriptor_BitBand_TypeDef;\r
+\r
+/*------------------------------------------------------------------------------\r
+ * HPDMA bit band\r
+ */\r
+typedef struct\r
+{\r
+    __I  uint32_t HPDMAEDR_DCP_EMPTY[4]           ;\r
+    __I  uint32_t HPDMAEDR_DCP_CMPLET[4]          ;\r
+    __I  uint32_t HPDMAEDR_DCP_ERR[4]             ;\r
+    __I  uint32_t HPDMAEDR_DCP_NON_WORD_ERR[4]    ;\r
+         uint32_t RESERVED0[16]                   ;\r
+\r
+    HPDMA_Descriptor_BitBand_TypeDef Descriptor[4];\r
+\r
+    __O  uint32_t HPDMAICR_CLR_XFR_INT[4]         ;\r
+    __O  uint32_t HPDMAICR_NON_WORD_INT[4]        ;\r
+         uint32_t RESERVED1[16]                   ;\r
+\r
+    __I  uint32_t HPDMADR_BFR_EMPTY               ;\r
+    __I  uint32_t HPDMADR_BFR_FULL                ;\r
+    __I  uint32_t HPDMADR_BFR_RD_PNTR[3]          ;\r
+    __I  uint32_t HPDMADR_BFR_WR_PNTR [3]         ;\r
+    __I  uint32_t HPDMADR_AHM1_CST_DBG[4]         ;\r
+    __I  uint32_t HPDMADR_AHM2_CST_DBG[4]         ;\r
+    __I  uint32_t HPDMADR_WBC_CST_DBG[3]          ;\r
+    __I  uint32_t HPDMADR_RBC_CST_DBG[3]          ;\r
+    __I  uint32_t HPDMADR_RRBN_CST_DBG[4]         ;\r
+    __I  uint32_t HPDMADR_DMA_CST_DBG[4]          ;\r
+\r
+         uint32_t RESERVED2[4]                    ;\r
+}HPDMA_BitBand_TypeDef;\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/*----------------------------------- RTC ------------------------------------*/\r
+/*----------------------------------------------------------------------------*/\r
+typedef struct\r
+{\r
+    __IO uint32_t CONTROL_REG             ;\r
+    __IO uint32_t MODE_REG                ;\r
+    __IO uint32_t PRESCALER_REG           ;\r
+    __IO uint32_t ALARM_LOWER_REG         ;\r
+    __IO uint32_t ALARM_UPPER_REG         ;\r
+    __IO uint32_t COMPARE_LOWER_REG       ;\r
+    __IO uint32_t COMPARE_UPPER_REG       ;\r
+         uint32_t RESERVED0               ;\r
+    __IO uint32_t DATE_TIME_LOWER_REG     ;\r
+    __IO uint32_t DATE_TIME_UPPER_REG     ;\r
+\r
+         uint32_t RESERVED1[2]            ;\r
+    __IO uint32_t SECONDS_REG             ;\r
+    __IO uint32_t MINUTES_REG             ;\r
+    __IO uint32_t HOURS_REG               ;\r
+    __IO uint32_t DAY_REG                 ;\r
+    __IO uint32_t MONTH_REG               ;\r
+    __IO uint32_t YEAR_REG                ;\r
+    __IO uint32_t WEEKDAY_REG             ;\r
+    __IO uint32_t WEEK_REG                ;\r
+\r
+    __IO uint32_t SECONDS_CNT_REG         ;\r
+    __IO uint32_t MINUTES_CNT_REG         ;\r
+    __IO uint32_t HOURS_CNT_REG           ;\r
+    __IO uint32_t DAY_CNT_REG             ;\r
+    __IO uint32_t MONTH_CNT_REG           ;\r
+    __IO uint32_t YEAR_CNT_REG            ;\r
+    __IO uint32_t WEEKDAY_CNT_REG         ;\r
+    __IO uint32_t WEEK_CNT_REG            ;\r
+} RTC_TypeDef;\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/*---------------------------------- Timer -----------------------------------*/\r
+/*----------------------------------------------------------------------------*/\r
+typedef struct\r
+{\r
+    __I  uint32_t TIM1_VAL;\r
+    __IO uint32_t TIM1_LOADVAL;\r
+    __IO uint32_t TIM1_BGLOADVAL;\r
+    __IO uint32_t TIM1_CTRL;\r
+    __IO uint32_t TIM1_RIS;\r
+    __I  uint32_t TIM1_MIS;\r
+\r
+    __I  uint32_t TIM2_VAL;\r
+    __IO uint32_t TIM2_LOADVAL;\r
+    __IO uint32_t TIM2_BGLOADVAL;\r
+    __IO uint32_t TIM2_CTRL;\r
+    __IO uint32_t TIM2_RIS;\r
+    __I  uint32_t TIM2_MIS;\r
+\r
+    __I  uint32_t TIM64_VAL_U;\r
+    __I  uint32_t TIM64_VAL_L;\r
+    __IO uint32_t TIM64_LOADVAL_U;\r
+    __IO uint32_t TIM64_LOADVAL_L;\r
+    __IO uint32_t TIM64_BGLOADVAL_U;\r
+    __IO uint32_t TIM64_BGLOADVAL_L;\r
+    __IO uint32_t TIM64_CTRL;\r
+    __IO uint32_t TIM64_RIS;\r
+    __I  uint32_t TIM64_MIS;\r
+    __IO uint32_t TIM64_MODE;\r
+} TIMER_TypeDef;\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Timer bit band\r
+ */\r
+typedef struct\r
+{\r
+    __I  uint32_t TIM1_VALUE_BIT[32];\r
+    __IO uint32_t TIM1_LOADVAL[32];\r
+    __IO uint32_t TIM1_BGLOADVAL[32];\r
+\r
+    __IO uint32_t TIM1ENABLE;\r
+    __IO uint32_t TIM1MODE;\r
+    __IO uint32_t TIM1INTEN;\r
+    __IO uint32_t TIM1_CTRL_RESERVED[29];\r
+    __IO uint32_t TIM1_RIS[32];\r
+    __I  uint32_t TIM1_MIS[32];\r
+\r
+    __I  uint32_t TIM2_VALUE[32];\r
+    __IO uint32_t TIM2_LOADVAL[32];\r
+    __IO uint32_t TIM2_BGLOADVAL[32];\r
+\r
+    __IO uint32_t TIM2ENABLE;\r
+    __IO uint32_t TIM2MODE;\r
+    __IO uint32_t TIM2INTEN;\r
+    __IO uint32_t TIM2_CTRL[29];\r
+    __IO uint32_t TIM2_RIS[32];\r
+    __I  uint32_t TIM2_MIS[32];\r
+\r
+    __I  uint32_t TIM64VALUEU[32];\r
+    __I  uint32_t TIM64VALUEL[32];\r
+    __IO uint32_t TIM64LOADVALUEU[32];\r
+    __IO uint32_t TIM64LOADVALUEL[32];\r
+    __IO uint32_t TIM64BGLOADVALUEU[32];\r
+    __IO uint32_t TIM64BGLOADVALUEL[32];\r
+    __IO uint32_t TIM64ENABLE;\r
+    __IO uint32_t TIM64MODE;\r
+    __IO uint32_t TIM64INTEN;\r
+    __IO uint32_t TIM64_CTRL[29];\r
+    __IO uint32_t TIM64_RIS[32];\r
+    __I  uint32_t TIM64_MIS[32];\r
+    __IO uint32_t TIM64_MODE[32];\r
+} TIMER_BitBand_TypeDef;\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/*--------------------------------- Watchdog ---------------------------------*/\r
+/*----------------------------------------------------------------------------*/\r
+typedef struct\r
+{\r
+    __I  uint32_t WDOGVALUE;\r
+    __I  uint32_t WDOGLOAD;\r
+    __I  uint32_t WDOGMVRP;\r
+    __O  uint32_t WDOGREFRESH;\r
+    __I  uint32_t WDOGENABLE;\r
+    __IO uint32_t WDOGCONTROL;\r
+    __I  uint32_t WDOGSTATUS;\r
+    __IO uint32_t WDOGRIS;\r
+    __I  uint32_t WDOGMIS;\r
+} WATCHDOG_TypeDef;\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/*----------------------------- Real Time Clock ------------------------------*/\r
+/*----------------------------------------------------------------------------*/\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/*----------------------------- Peripherals DMA ------------------------------*/\r
+/*----------------------------------------------------------------------------*/\r
+typedef struct\r
+{\r
+    __IO uint32_t CRTL;\r
+    __IO uint32_t STATUS;\r
+    __IO uint32_t BUFFER_A_SRC_ADDR;\r
+    __IO uint32_t BUFFER_A_DEST_ADDR;\r
+    __IO uint32_t BUFFER_A_TRANSFER_COUNT;\r
+    __IO uint32_t BUFFER_B_SRC_ADDR;\r
+    __IO uint32_t BUFFER_B_DEST_ADDR;\r
+    __IO uint32_t BUFFER_B_TRANSFER_COUNT;\r
+} PDMA_Channel_TypeDef;\r
+\r
+typedef struct\r
+{\r
+    __IO uint32_t RATIO_HIGH_LOW;\r
+    __IO uint32_t BUFFER_STATUS;\r
+         uint32_t RESERVED[6];\r
+    PDMA_Channel_TypeDef CHANNEL[8];\r
+} PDMA_TypeDef;\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/*------------------------------ Ethernet MAC --------------------------------*/\r
+/*----------------------------------------------------------------------------*/\r
+typedef struct\r
+{\r
+       /* \r
+     * MAC registers (MCXMAC)\r
+     */\r
+    __IO uint32_t CFG1;\r
+    __IO uint32_t CFG2;\r
+    __IO uint32_t IFG;\r
+    __IO uint32_t HALF_DUPLEX;\r
+    __IO uint32_t MAX_FRAME_LENGTH;\r
+         uint32_t RESERVED0[2];\r
+    __IO uint32_t TEST;\r
+    __IO uint32_t MII_CONFIG;\r
+    __IO uint32_t MII_COMMAND;\r
+    __IO uint32_t MII_ADDRESS;\r
+    __O  uint32_t MII_CTRL;\r
+    __I  uint32_t MII_STATUS;\r
+    __I  uint32_t MII_INDICATORS;\r
+    __IO uint32_t INTERFACE_CTRL;\r
+    __I  uint32_t INTERFACE_STATUS;\r
+    __IO uint32_t STATION_ADDRESS1;\r
+    __IO uint32_t STATION_ADDRESS2;\r
+    /* \r
+     * FIFO Configuration / Access registers (MCXFIF)\r
+     */\r
+    __IO uint32_t FIFO_CFG0;\r
+    __IO uint32_t FIFO_CFG1;\r
+    __IO uint32_t FIFO_CFG2;\r
+    __IO uint32_t FIFO_CFG3;\r
+    __IO uint32_t FIFO_CFG4;\r
+    __IO uint32_t FIFO_CFG5;\r
+    __IO uint32_t FIFO_RAM_ACCESS0;\r
+    __IO uint32_t FIFO_RAM_ACCESS1;\r
+    __IO uint32_t FIFO_RAM_ACCESS2;\r
+    __I  uint32_t FIFO_RAM_ACCESS3;\r
+    __IO uint32_t FIFO_RAM_ACCESS4;\r
+    __IO uint32_t FIFO_RAM_ACCESS5;\r
+    __IO uint32_t FIFO_RAM_ACCESS6;\r
+    __I  uint32_t FIFO_RAM_ACCESS7;\r
+    /*\r
+     * Statistics registers (MSTAT)\r
+     */\r
+    __IO uint32_t TR64;\r
+    __IO uint32_t TR127;\r
+    __IO uint32_t TR255;\r
+    __IO uint32_t TR511;\r
+    __IO uint32_t TR1K;\r
+    __IO uint32_t TRMAX;\r
+    __IO uint32_t TRMGV;\r
+    __IO uint32_t RBYT;\r
+    __IO uint32_t PPKT;\r
+    __IO uint32_t RFCS;\r
+    __IO uint32_t RMCA;\r
+    __IO uint32_t RBCA;\r
+    __IO uint32_t RXCF;\r
+    __IO uint32_t RXPF;\r
+    __IO uint32_t RXUO;\r
+    __IO uint32_t RALN;\r
+    __IO uint32_t RFLR;\r
+    __IO uint32_t RCDE;\r
+    __IO uint32_t RCSE;\r
+    __IO uint32_t RUND;\r
+    __IO uint32_t ROVR;\r
+    __IO uint32_t RFRG;\r
+    __IO uint32_t RJBR;\r
+    __IO uint32_t RDRP;\r
+    __IO uint32_t TBYT;\r
+    __IO uint32_t TPKT;\r
+    __IO uint32_t TMCA;\r
+    __IO uint32_t TBCA;\r
+    __IO uint32_t TXPF;\r
+    __IO uint32_t TDFR;\r
+    __IO uint32_t TEDF;\r
+    __IO uint32_t TSCL;\r
+    __IO uint32_t TMCL;\r
+    __IO uint32_t TLCL;\r
+    __IO uint32_t TXCL;\r
+    __IO uint32_t TNCL;\r
+    __IO uint32_t TPFH;\r
+    __IO uint32_t TDRP;\r
+    __IO uint32_t TJBR;\r
+    __IO uint32_t TFCS;\r
+    __IO uint32_t TXCF;\r
+    __IO uint32_t TOVR;\r
+    __IO uint32_t TUND;\r
+    __IO uint32_t TFRG;\r
+    __I  uint32_t CAR1;\r
+    __I  uint32_t CAR2;\r
+    __IO uint32_t CAM1;\r
+    __IO uint32_t CAM2;\r
+     uint32_t RESERVED1[16];\r
+    /*\r
+     * DMA registers (MAHBE)\r
+     */\r
+    __IO uint32_t DMA_TX_CTRL;\r
+    __IO uint32_t DMA_TX_DESC;\r
+    __IO uint32_t DMA_TX_STATUS;\r
+    __IO uint32_t DMA_RX_CTRL;\r
+    __IO uint32_t DMA_RX_DESC;\r
+    __IO uint32_t DMA_RX_STATUS;\r
+    __IO uint32_t DMA_IRQ_MASK;\r
+    __I  uint32_t DMA_IRQ;\r
+} MAC_TypeDef;\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/*------------------------------ USB --------------------------------*/\r
+/*----------------------------------------------------------------------------*/\r
+typedef struct\r
+{\r
+    __IO uint16_t   TX_MAX_P;\r
+    __IO uint16_t   TX_CSR;  \r
+    __IO uint16_t   RX_MAX_P;\r
+    __IO uint16_t   RX_CSR;  \r
+    __IO uint16_t   RX_COUNT;\r
+    __IO uint8_t    TX_TYPE; \r
+    __IO uint8_t    TX_INTERVAL;\r
+    __IO uint8_t    RX_TYPE;    \r
+    __IO uint8_t    RX_INTERVAL;\r
+    __IO uint8_t    RESERVED;\r
+    __IO uint8_t    FIFO_SIZE;  \r
+} USB_endpoint_regs_t;\r
+\r
+typedef struct\r
+{\r
+    __IO uint8_t    TX_FUNC_ADDR;\r
+    __IO uint8_t    UNUSED0;\r
+    __IO uint8_t    TX_HUB_ADDR;\r
+    __IO uint8_t    TX_HUB_PORT;\r
+    __IO uint8_t    RX_FUNC_ADDR;\r
+    __IO uint8_t    UNUSED1;\r
+    __IO uint8_t    RX_HUB_ADDR;\r
+    __IO uint8_t    RX_HUB_PORT;\r
+} USB_tar_t;\r
+\r
+typedef union\r
+{\r
+    struct\r
+    {\r
+        __IO uint32_t   VALUE;\r
+    } WORD;\r
+\r
+    struct\r
+    {\r
+        __IO uint8_t    VALUE;\r
+        __IO uint8_t    RESERVED1;\r
+        __IO uint8_t    RESERVED2;\r
+        __IO uint8_t    RESERVED3;\r
+    } BYTE;\r
+\r
+    struct\r
+    {\r
+        __IO uint16_t   VALUE;\r
+        __IO uint16_t   RESERVED;\r
+    } HALFWORD;\r
+} USB_fifo_t;\r
+\r
+typedef union\r
+{\r
+    struct                          \r
+    {\r
+        __IO uint16_t   TX_MAX_P;   \r
+        __IO uint16_t   CSR0;       \r
+        __IO uint16_t   RX_MAX_P;   \r
+        __IO uint16_t   RX_CSR;     \r
+        __IO uint16_t   COUNT0;     \r
+        __IO uint8_t    RESERVED0;\r
+        __IO uint8_t    RESERVED1;\r
+        __IO uint8_t    RESERVED2;\r
+        __IO uint8_t    RESERVED3;\r
+        __IO uint8_t    RESERVED4;\r
+        __IO uint8_t    CONFIG_DATA;  \r
+    } DEVICE_EP0;\r
+\r
+    struct                            \r
+    {\r
+        __IO uint16_t   TX_MAX_P;\r
+        __IO uint16_t   TX_CSR;\r
+        __IO uint16_t   RX_MAX_P;\r
+        __IO uint16_t   RX_CSR;\r
+        __IO uint16_t   RX_COUNT;\r
+        __IO uint8_t    RESERVED0;\r
+        __IO uint8_t    RESERVED1;\r
+        __IO uint8_t    RESERVED2;\r
+        __IO uint8_t    RESERVED3;\r
+        __IO uint8_t    RESERVED4;\r
+        __IO uint8_t    FIFO_SIZE;\r
+    } DEVICE_EPN;\r
+\r
+    struct                          \r
+    {\r
+        __IO uint16_t   TX_MAX_P;\r
+        __IO uint16_t   CSR0;\r
+        __IO uint16_t   RX_MAX_P;\r
+        __IO uint16_t   RX_CSR;\r
+        __IO uint16_t   COUNT0;\r
+        __IO uint8_t    TYPE0;\r
+        __IO uint8_t    NAK_LIMIT0;\r
+        __IO uint8_t    RX_TYPE;\r
+        __IO uint8_t    RX_INTERVAL;\r
+        __IO uint8_t    RESERVED0;\r
+        __IO uint8_t    CONFIG_DATA;\r
+    } HOST_EP0;\r
+\r
+    struct                          \r
+    {\r
+        __IO uint16_t   TX_MAX_P;\r
+        __IO uint16_t   TX_CSR;\r
+        __IO uint16_t   RX_MAX_P;\r
+        __IO uint16_t   RX_CSR;\r
+        __IO uint16_t   RX_COUNT;\r
+        __IO uint8_t    TX_TYPE;\r
+        __IO uint8_t    TX_INTERVAL;\r
+        __IO uint8_t    RX_TYPE;\r
+        __IO uint8_t    RX_INTERVAL;\r
+        __IO uint8_t    RESERVED0;\r
+        __IO uint8_t    FIFO_SIZE;\r
+    } HOST_EPN;\r
+\r
+} USB_indexed_csr_t;\r
+\r
+typedef struct {\r
+    __IO uint32_t   IRQ;    \r
+    __IO uint32_t   CNTL;\r
+    __IO uint32_t   ADDR;\r
+    __IO uint32_t   COUNT;\r
+} USB_DMA_channel;\r
+\r
+typedef struct\r
+{\r
+    /* \r
+    * Common USB Registers \r
+    */\r
+    __IO uint8_t    FADDR;            \r
+    __IO uint8_t    POWER;            \r
+    __IO uint16_t   TX_IRQ;           \r
+    __IO uint16_t   RX_IRQ;           \r
+    __IO uint16_t   TX_IRQ_ENABLE;    \r
+    __IO uint16_t   RX_IRQ_ENABLE;    \r
+    __IO uint8_t    USB_IRQ;          \r
+    __IO uint8_t    USB_ENABLE;       \r
+    __IO uint16_t   FRAME;            \r
+    __IO uint8_t    INDEX;            \r
+    __IO uint8_t    TEST_MODE;        \r
+\r
+    /*\r
+    * Indexed CSR\r
+    */\r
+    USB_indexed_csr_t   INDEXED_CSR;\r
+\r
+    /*\r
+    * Endpoint FIFOs \r
+    */\r
+    USB_fifo_t      FIFO[16];         \r
+\r
+    /*\r
+    * OTG, dynamic FIFO and version \r
+    */\r
+    __IO uint8_t    DEV_CTRL;         \r
+    __IO uint8_t    MISC;             \r
+    __IO uint8_t    TX_FIFO_SIZE;     \r
+    __IO uint8_t    RX_FIFO_SIZE;     \r
+    __IO uint16_t   TX_FIFO_ADDR;     \r
+    __IO uint16_t   RX_FIFO_ADDR;     \r
+    __IO uint32_t   VBUS_CSR;         \r
+    __IO uint16_t   HW_VERSION;       \r
+    __IO uint16_t   RESERVED;         \r
+\r
+    /* \r
+    * ULPI and configuration registers \r
+    */\r
+    __IO uint8_t    ULPI_VBUS_CTRL;   \r
+    __IO uint8_t    ULPI_CARKIT_CTRL; \r
+    __IO uint8_t    ULPI_IRQ_MASK;    \r
+    __IO uint8_t    ULPI_IRQ_SRC;     \r
+    __IO uint8_t    ULPI_DATA_REG;    \r
+    __IO uint8_t    ULPI_ADDR_REG;    \r
+    __IO uint8_t    ULPI_CTRL_REG;    \r
+    __IO uint8_t    ULPI_RAW_DATA;    \r
+    __IO uint8_t    EP_INFO;          \r
+    __IO uint8_t    RAM_INFO;         \r
+    __IO uint8_t    LINK_INFO;        \r
+    __IO uint8_t    VP_LEN;           \r
+    __IO uint8_t    HS_EOF1;          \r
+    __IO uint8_t    FS_EOF1;          \r
+    __IO uint8_t    LS_EOF1;          \r
+    __IO uint8_t    SOFT_RST;         \r
+\r
+    /* \r
+    * Target Address registers \r
+    */\r
+    USB_tar_t       TAR[16];          \r
+\r
+    /* \r
+    * Endpoints CSR \r
+    */\r
+    USB_endpoint_regs_t ENDPOINT[16]; \r
+\r
+    /* \r
+    * DMA \r
+    */\r
+    USB_DMA_channel DMA_CHANNEL[8];\r
+       \r
+    __IO uint32_t   RESERVED_EXT[32];\r
+    __IO uint32_t   RQ_PKT_CNT[16];   \r
+    __IO uint16_t   RX_DPBUF_DIS;\r
+    __IO uint16_t   TX_DPBUF_DIS;\r
+    __IO uint16_t   C_T_UCH;\r
+    __IO uint16_t   C_T_HHSRTN;\r
+    __IO uint16_t   C_T_HSBT;\r
+\r
+} MSS_USB_TypeDef;\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/*---------------------- eNVM Special Function Registers ---------------------*/\r
+/*----------------------------------------------------------------------------*/\r
+typedef struct\r
+{\r
+    __I  uint8_t  AB[128];\r
+    __IO uint8_t  WD[128];\r
+    __I  uint8_t  RESERVED0[32];\r
+    __I  uint32_t STATUS;\r
+    __IO uint32_t RESERVED1;\r
+    __IO uint32_t NV_PAGE_STATUS;\r
+    __I  uint32_t NV_FREQRNG;\r
+    __I  uint32_t NV_DPD;\r
+    __IO uint32_t NV_CE;\r
+         uint32_t RESERVED2;\r
+    __IO uint32_t RESERVED3;\r
+    __IO uint32_t PAGE_LOCK;\r
+    __IO uint32_t DWSIZE;\r
+    __IO uint32_t CMD;\r
+    __IO uint32_t RESERVED4;\r
+    __I  uint32_t RESERVED5;\r
+    __IO uint32_t INTEN;\r
+    __IO uint32_t CLRHINT;\r
+         uint32_t RESERVED6[40];\r
+    __IO uint32_t REQ_ACCESS;\r
+} NVM_TypeDef;\r
+\r
+typedef struct\r
+{\r
+    __I  uint32_t AB[32];\r
+    __IO uint32_t WD[32];\r
+    __I  uint32_t RESERVED0[8];\r
+    __I  uint32_t STATUS;\r
+    __IO uint32_t RESERVED1;\r
+    __IO uint32_t NV_PAGE_STATUS;\r
+    __I  uint32_t NV_FREQRNG;\r
+    __I  uint32_t NV_DPD;\r
+    __IO uint32_t NV_CE;\r
+         uint32_t RESERVED2;\r
+    __IO uint32_t RESERVED3;\r
+    __IO uint32_t PAGE_LOCK;\r
+    __IO uint32_t DWSIZE;\r
+    __IO uint32_t CMD;\r
+    __IO uint32_t RESERVED4;\r
+    __I  uint32_t RESERVED5;\r
+    __IO uint32_t INTEN;\r
+    __IO uint32_t CLRHINT;\r
+         uint32_t RESERVED6[40];\r
+    __IO uint32_t REQ_ACCESS;\r
+} NVM32_TypeDef;\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/*---------------------------------- COMBLK ----------------------------------*/\r
+/*----------------------------------------------------------------------------*/\r
+typedef struct\r
+{\r
+    __IO uint32_t CONTROL;\r
+    __IO uint32_t STATUS;\r
+    __IO uint32_t INT_ENABLE;\r
+    __IO uint32_t RESERVED;\r
+    __IO uint32_t DATA8;\r
+    __IO uint32_t DATA32;\r
+    __IO uint32_t FRAME_START8;\r
+    __IO uint32_t FRAME_START32;\r
+} COMBLK_TypeDef;\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/*--------------------- FPGA Fabric Interrupt Controller ---------------------*/\r
+/*----------------------------------------------------------------------------*/\r
+/*\r
+ * Please refer to the SmartFusion2 Interrupt Controller User's Guide for a\r
+ * description of the following registers.\r
+ * The registers defined below can be accessed using INTERRUPT_CTRL as follows:\r
+ *      uint32_t reason0;\r
+ *      INTERRUPT_CTRL->INTERRUPT_MODE = 0;\r
+ *      reason0 = INTERRUPT_CTRL->INTERRUPT_REASON0;\r
+ */\r
+typedef struct\r
+{\r
+    __IO uint32_t INTERRUPT_ENABLE0;\r
+    __IO uint32_t INTERRUPT_ENABLE1;\r
+    __IO uint32_t INTERRUPT_REASON0;\r
+    __IO uint32_t INTERRUPT_REASON1;\r
+    __IO uint32_t INTERRUPT_MODE;\r
+} INTERRUPT_CTRL_TypeDef;\r
+\r
+/*\r
+ * Please refer to the SmartFusion2 Interrupt Controller User's Guide for a\r
+ * description of the following register bits.\r
+ * The register bits defined below can be accessed using INTERRUPT_CTRL_BITBAND\r
+ * as follows:\r
+ *  setting/clearing a bit:\r
+ *      INTERRUPT_CTRL_BITBAND->MAC_INT_ENBL = 1;\r
+ *      INTERRUPT_CTRL_BITBAND->PDMAINTERRUPT_ENBL = 0;\r
+ *  reading a bit value:\r
+ *      uint32_t timer1_interrupt;\r
+ *      timer1_interrupt = INTERRUPT_CTRL_BITBAND->TIMER1_INTR_STATUS;\r
+ */\r
+typedef struct\r
+{\r
+    /*\r
+     * INTERRUPT_ENABLE0 register bitband definitions.\r
+     */\r
+    __IO uint32_t SPIINT0_ENBL;\r
+    __IO uint32_t SPIINT1_ENBL;\r
+    __IO uint32_t I2C_INT0_ENBL;\r
+    __IO uint32_t I2C_INT1_ENBL;\r
+    __IO uint32_t MMUART0_INTR_ENBL;\r
+    __IO uint32_t MMUART1_INTR_ENBL;\r
+    __IO uint32_t MAC_INT_ENBL;\r
+    __IO uint32_t USB_MC_INT_ENBL;\r
+    __IO uint32_t PDMAINTERRUPT_ENBL;\r
+    __IO uint32_t HPD_XFR_CMP_INT_ENBL;\r
+    __IO uint32_t TIMER1_INTR_ENBL;\r
+    __IO uint32_t TIMER2_INTR_ENBL;\r
+    __IO uint32_t CAN_INTR_ENBL;\r
+    __IO uint32_t RTC_WAKEUP_INTR_ENBL;\r
+    __IO uint32_t WDOGWAKEUPINT_ENBL;\r
+    __IO uint32_t MSSDDR_PLL_LOCKLOST_INT_ENBL;\r
+    __IO uint32_t ENVM_INT0_ENBL;\r
+    __IO uint32_t ENVM_INT1_ENBL;\r
+    __IO uint32_t I2C_SMBALERT0_ENBL;\r
+    __IO uint32_t I2C_SMBSUS0_ENBL;\r
+    __IO uint32_t I2C_SMBALERT1_ENBL;\r
+    __IO uint32_t I2C_SMBSUS1_ENBL;\r
+    __IO uint32_t HPD_XFR_ERR_INT_ENBL;\r
+    __IO uint32_t MSSDDR_PLL_LOCK_INT_ENBL;\r
+    __IO uint32_t SW_ERRORINTERRUPT_ENBL;\r
+    __IO uint32_t DDRB_INTR_ENBL;\r
+    __IO uint32_t ECCINTR_ENBL;\r
+    __IO uint32_t CACHE_ERRINTR_ENBL;\r
+    __IO uint32_t SOFTINTERRUPT_ENBL;\r
+    __IO uint32_t COMBLK_INTR_ENBL;\r
+    __IO uint32_t USB_DMA_INT_ENBL;\r
+    __IO uint32_t RESERVED0;\r
+    \r
+    /*\r
+     * INTERRUPT_ENABLE1 register bitband definitions.\r
+     */\r
+    __IO uint32_t RESERVED1[3];\r
+    __IO uint32_t MDDR_IO_CALIB_INT_ENBL;\r
+    __IO uint32_t RESERVED2;\r
+    __IO uint32_t FAB_PLL_LOCK_INT_ENBL;\r
+    __IO uint32_t FAB_PLL_LOCKLOST_INT_ENBL;\r
+    __IO uint32_t FIC64_INT_ENBL;\r
+    __IO uint32_t RESERVED3[24];\r
+    \r
+    /*\r
+     * INTERRUPT_REASON0 register bitband definitions.\r
+     */\r
+    __IO uint32_t SPIINT0_STATUS;\r
+    __IO uint32_t SPIINT1_STATUS;\r
+    __IO uint32_t I2C_INT0_STATUS;\r
+    __IO uint32_t I2C_INT1_STATUS;\r
+    __IO uint32_t MMUART0_INTR_STATUS;\r
+    __IO uint32_t MMUART1_INTR_STATUS;\r
+    __IO uint32_t MAC_INT_STATUS;\r
+    __IO uint32_t USB_MC_INT_STATUS;\r
+    __IO uint32_t PDMAINTERRUPT_STATUS;\r
+    __IO uint32_t HPD_XFR_CMP_INT_STATUS;\r
+    __IO uint32_t TIMER1_INTR_STATUS;\r
+    __IO uint32_t TIMER2_INTR_STATUS;\r
+    __IO uint32_t CAN_INTR_STATUS;\r
+    __IO uint32_t RTC_WAKEUP_INTR_STATUS;\r
+    __IO uint32_t WDOGWAKEUPINT_STATUS;\r
+    __IO uint32_t MSSDDR_PLL_LOCKLOST_INT_STATUS;\r
+    __IO uint32_t ENVM_INT0_STATUS;\r
+    __IO uint32_t ENVM_INT1_STATUS;\r
+    __IO uint32_t I2C_SMBALERT0_STATUS;\r
+    __IO uint32_t I2C_SMBSUS0_STATUS;\r
+    __IO uint32_t I2C_SMBALERT1_STATUS;\r
+    __IO uint32_t I2C_SMBSUS1_STATUS;\r
+    __IO uint32_t HPD_XFR_ERR_INT_STATUS;\r
+    __IO uint32_t MSSDDR_PLL_LOCK_INT_STATUS;\r
+    __IO uint32_t SW_ERRORINTERRUPT_STATUS;\r
+    __IO uint32_t DDRB_INTR_STATUS;\r
+    __IO uint32_t ECCINTR_STATUS;\r
+    __IO uint32_t CACHE_ERRINTR_STATUS;\r
+    __IO uint32_t SOFTINTERRUPT_STATUS;\r
+    __IO uint32_t COMBLK_INTR_STATUS;\r
+    __IO uint32_t USB_DMA_INT_STATUS;\r
+    __IO uint32_t RESERVED4;\r
+    \r
+    /*\r
+     * INTERRUPT_REASON1 register bitband definitions.\r
+     */\r
+    __IO uint32_t RESERVED5[3];\r
+    __IO uint32_t MDDR_IO_CALIB_INT_STATUS;\r
+    __IO uint32_t RESERVED6;\r
+    __IO uint32_t FAB_PLL_LOCK_INT_STATUS;\r
+    __IO uint32_t FAB_PLL_LOCKLOST_INT_STATUS;\r
+    __IO uint32_t FIC64_INT_STATUS;\r
+    __IO uint32_t RESERVED7[24];\r
+    \r
+    /*\r
+     * INTERRUPT_MODE register bitband definitions.\r
+     */\r
+    __IO uint32_t SELECT_MODE;\r
+    __IO uint32_t RESERVED8[31];\r
+    \r
+} INTERRUPT_CTRL_BitBand_TypeDef;\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/*------------------------ DDR Controller APB Registers ----------------------*/\r
+/*----------------------------------------------------------------------------*/\r
+typedef struct\r
+{\r
+    /*--------------------------------------------------------------------------\r
+     * DDR Controller registers.\r
+     * All registers are 16-bit wide unless mentioned beside the definition.\r
+     */\r
+    struct\r
+    {\r
+        __IO uint32_t DYN_SOFT_RESET_CR;\r
+        __IO uint32_t RESERVED0;\r
+        __IO uint32_t DYN_REFRESH_1_CR;\r
+        __IO uint32_t DYN_REFRESH_2_CR;\r
+        __IO uint32_t DYN_POWERDOWN_CR;\r
+        __IO uint32_t DYN_DEBUG_CR;\r
+        __IO uint32_t MODE_CR;\r
+        __IO uint32_t ADDR_MAP_BANK_CR;\r
+        __IO uint32_t ECC_DATA_MASK_CR;\r
+        __IO uint32_t ADDR_MAP_COL_1_CR;\r
+        __IO uint32_t ADDR_MAP_COL_2_CR;\r
+        __IO uint32_t ADDR_MAP_ROW_1_CR;\r
+        __IO uint32_t ADDR_MAP_ROW_2_CR;\r
+        __IO uint32_t INIT_1_CR;\r
+        __IO uint32_t CKE_RSTN_CYCLES_CR[2];     /* 0:27 bits are valid */\r
+        __IO uint32_t INIT_MR_CR;\r
+        __IO uint32_t INIT_EMR_CR;\r
+        __IO uint32_t INIT_EMR2_CR;\r
+        __IO uint32_t INIT_EMR3_CR;\r
+        __IO uint32_t DRAM_BANK_TIMING_PARAM_CR;\r
+        __IO uint32_t DRAM_RD_WR_LATENCY_CR;\r
+        __IO uint32_t DRAM_RD_WR_PRE_CR;\r
+        __IO uint32_t DRAM_MR_TIMING_PARAM_CR;\r
+        __IO uint32_t DRAM_RAS_TIMING_CR;\r
+        __IO uint32_t DRAM_RD_WR_TRNARND_TIME_CR;\r
+        __IO uint32_t DRAM_T_PD_CR;\r
+        __IO uint32_t DRAM_BANK_ACT_TIMING_CR;\r
+        __IO uint32_t ODT_PARAM_1_CR;\r
+        __IO uint32_t ODT_PARAM_2_CR;\r
+        __IO uint32_t ADDR_MAP_COL_3_CR;\r
+        __IO uint32_t MODE_REG_RD_WR_CR;\r
+        __IO uint32_t MODE_REG_DATA_CR;\r
+        __IO uint32_t PWR_SAVE_1_CR;\r
+        __IO uint32_t PWR_SAVE_2_CR;\r
+        __IO uint32_t ZQ_LONG_TIME_CR;\r
+        __IO uint32_t ZQ_SHORT_TIME_CR;\r
+        __IO uint32_t ZQ_SHORT_INT_REFRESH_MARGIN_CR[2];\r
+        __IO uint32_t PERF_PARAM_1_CR;\r
+        __IO uint32_t HPR_QUEUE_PARAM_CR[2];\r
+        __IO uint32_t LPR_QUEUE_PARAM_CR[2];\r
+        __IO uint32_t WR_QUEUE_PARAM_CR;\r
+        __IO uint32_t PERF_PARAM_2_CR;\r
+        __IO uint32_t PERF_PARAM_3_CR;\r
+        __IO uint32_t DFI_RDDATA_EN_CR;\r
+        __IO uint32_t DFI_MIN_CTRLUPD_TIMING_CR;\r
+        __IO uint32_t DFI_MAX_CTRLUPD_TIMING_CR;\r
+        __IO uint32_t DFI_WR_LVL_CONTROL_CR[2];\r
+        __IO uint32_t DFI_RD_LVL_CONTROL_CR[2];\r
+        __IO uint32_t DFI_CTRLUPD_TIME_INTERVAL_CR;\r
+        __IO uint32_t DYN_SOFT_RESET_CR2;\r
+        __IO uint32_t AXI_FABRIC_PRI_ID_CR;\r
+        __I  uint32_t DDRC_SR;\r
+        __I  uint32_t SINGLE_ERR_CNT_SR;\r
+        __I  uint32_t DOUBLE_ERR_CNT_SR;\r
+        __I  uint32_t LUE_SYNDROME_SR[5];       /* LUE : Last Uncorrected Error */\r
+        __I  uint32_t LUE_ADDRESS_SR[2];        \r
+        __I  uint32_t LCE_SYNDROME_SR[5];       /* LCE : Last Corrected Error */\r
+        __I  uint32_t LCE_ADDRESS_SR[2];\r
+        __I  uint32_t LCB_NUMBER_SR;            /* LCB : Last Corrected Bit */\r
+        __I  uint32_t LCB_MASK_SR[4];          \r
+        __I  uint32_t ECC_INT_SR;\r
+        __O  uint32_t ECC_INT_CLR_REG;\r
+        __I  uint32_t ECC_OUTPUT_DATA_SR;\r
+        __IO uint32_t RESERVED1[46];\r
+    } ddrc;\r
+    \r
+    /*--------------------------------------------------------------------------\r
+     * DDR PHY configuration registers\r
+     */\r
+    struct \r
+    {\r
+        __IO uint32_t DYN_BIST_TEST_CR;\r
+        __IO uint32_t DYN_BIST_TEST_ERRCLR_CR[3];\r
+        __IO uint32_t BIST_TEST_SHIFT_PATTERN_CR[3];\r
+        __IO uint32_t LOOPBACK_TEST_CR;\r
+        __IO uint32_t BOARD_LOOPBACK_CR;\r
+        __IO uint32_t CTRL_SLAVE_RATIO_CR;\r
+        __IO uint32_t CTRL_SLAVE_FORCE_CR;\r
+        __IO uint32_t CTRL_SLAVE_DELAY_CR;\r
+        __IO uint32_t DATA_SLICE_IN_USE_CR;\r
+        __IO uint32_t LVL_NUM_OF_DQ0_CR;\r
+        __IO uint32_t DQ_OFFSET_CR[3];\r
+        __IO uint32_t DIS_CALIB_RST_CR;\r
+        __IO uint32_t DLL_LOCK_DIFF_CR;\r
+        __IO uint32_t FIFO_WE_IN_DELAY_CR[3];\r
+        __IO uint32_t FIFO_WE_IN_FORCE_CR;\r
+        __IO uint32_t FIFO_WE_SLAVE_RATIO_CR[4];\r
+        __IO uint32_t GATELVL_INIT_MODE_CR;\r
+        __IO uint32_t GATELVL_INIT_RATIO_CR[4];\r
+        __IO uint32_t LOCAL_ODT_CR;\r
+        __IO uint32_t INVERT_CLKOUT_CR;\r
+        __IO uint32_t RD_DQS_SLAVE_DELAY_CR[3];\r
+        __IO uint32_t RD_DQS_SLAVE_FORCE_CR;\r
+        __IO uint32_t RD_DQS_SLAVE_RATIO_CR[4];\r
+        __IO uint32_t WR_DQS_SLAVE_DELAY_CR[3];\r
+        __IO uint32_t WR_DQS_SLAVE_FORCE_CR;\r
+        __IO uint32_t WR_DQS_SLAVE_RATIO_CR[4];\r
+        __IO uint32_t WR_DATA_SLAVE_DELAY_CR[3];\r
+        __IO uint32_t WR_DATA_SLAVE_FORCE_CR;\r
+        __IO uint32_t WR_DATA_SLAVE_RATIO_CR[4];\r
+        __IO uint32_t WRLVL_INIT_MODE_CR;\r
+        __IO uint32_t WRLVL_INIT_RATIO_CR[4];\r
+        __IO uint32_t WR_RD_RL_CR;\r
+        __IO uint32_t RDC_FIFO_RST_ERRCNTCLR_CR;\r
+        __IO uint32_t RDC_WE_TO_RE_DELAY_CR;\r
+        __IO uint32_t USE_FIXED_RE_CR;\r
+        __IO uint32_t USE_RANK0_DELAYS_CR;\r
+        __IO uint32_t USE_LVL_TRNG_LEVEL_CR;\r
+        __IO uint32_t CONFIG_CR;\r
+        __IO uint32_t RD_WR_GATE_LVL_CR;\r
+        __IO uint32_t DYN_RESET_CR;\r
+\r
+        /*----------------------------------------------------------------------\r
+         * DDR PHY status registers\r
+         */    \r
+        __I  uint32_t LEVELLING_FAILURE_SR;\r
+        __I  uint32_t BIST_ERROR_SR[3];\r
+        __I  uint32_t WRLVL_DQS_RATIO_SR[4];\r
+        __I  uint32_t WRLVL_DQ_RATIO_SR[4];\r
+        __I  uint32_t RDLVL_DQS_RATIO_SR[4];\r
+        __I  uint32_t FIFO_SR[4];\r
+        __I  uint32_t MASTER_DLL_SR;\r
+        __I  uint32_t DLL_SLAVE_VALUE_SR[2];\r
+        __I  uint32_t STATUS_OF_IN_DELAY_VAL_SR[2];\r
+        __I  uint32_t STATUS_OF_OUT_DELAY_VAL_SR[2];\r
+        __I  uint32_t DLL_LOCK_AND_SLAVE_VAL_SR;\r
+        __I  uint32_t CTRL_OUTPUT_FILTER_SR;\r
+        __I  uint32_t CTRL_OF_OUTPUT_DELAY_SR;\r
+        __I  uint32_t RD_DQS_SLAVE_DLL_VAL_SR[3];\r
+        __I  uint32_t WR_DATA_SLAVE_DLL_VAL_SR[3];\r
+        __I  uint32_t FIFO_WE_SLAVE_DLL_VAL_SR[3];\r
+        __I  uint32_t WR_DQS_SLAVE_DLL_VAL_SR[3];\r
+        __I  uint32_t CTRL_SLAVE_DLL_VAL_SR; \r
+        __IO uint32_t RESERVED2[13];\r
+    } phy;\r
+    \r
+    /*--------------------------------------------------------------------------\r
+     * FIC-64 registers\r
+     * These registers are 16-bit wide and 32-bit aligned.\r
+     */\r
+    struct \r
+    {\r
+        __IO uint32_t NB_ADDR_CR;\r
+        __IO uint32_t NBRWB_SIZE_CR;\r
+        __IO uint32_t WB_TIMEOUT_CR;\r
+        __IO uint32_t HPD_SW_RW_EN_CR;\r
+        __IO uint32_t HPD_SW_RW_INVAL_CR;\r
+        __IO uint32_t SW_WR_ERCLR_CR;\r
+        __IO uint32_t ERR_INT_ENABLE_CR;\r
+        __IO uint32_t NUM_AHB_MASTERS_CR;\r
+        __I  uint32_t HPB_ERR_ADDR_SR[2];\r
+        __I  uint32_t SW_ERR_ADDR_SR[2];\r
+        __I  uint32_t HPD_SW_WRB_EMPTY_SR;\r
+        __I  uint32_t SW_HPB_LOCKOUT_SR;\r
+        __I  uint32_t SW_HPD_WERR_SR;\r
+             uint32_t RESERVED0;\r
+        __IO uint32_t LOCK_TIMEOUTVAL_CR[2];\r
+        __IO uint32_t LOCK_TIMEOUT_EN_CR;\r
+             uint32_t RESERVED1[5];\r
+        __IO uint32_t RDWR_ERR_SR;\r
+    } fic;\r
+} DDRCore_TypeDef;\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/*--------------------- MDDR APB Configuration Registers ---------------------*/\r
+/*----------------------------------------------------------------------------*/\r
+typedef struct\r
+{\r
+    /*--------------------------------------------------------------------------\r
+     * MDDR core configuration registers.\r
+     * These registers are to be accessed as:\r
+     * MDDR->core.fic.<regname> = <value>;\r
+     * MDDR->core.phy.<regname> = <value>;\r
+     * MDDR->core.ddrc.<regname> = <value>;\r
+     */\r
+    DDRCore_TypeDef core;\r
+    \r
+} MDDR_TypeDef;\r
+\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/*--------------------- FDDR APB Configuration Registers ---------------------*/\r
+/*----------------------------------------------------------------------------*/\r
+typedef struct \r
+{\r
+    /*--------------------------------------------------------------------------\r
+     * FDDR core configuration registers. These are same as corresponding \r
+     * MDDR registers. \r
+     * These registers are to be accessed as:\r
+     * FDDR->core.fic.<regname> = <value>;\r
+     * FDDR->core.phy.<regname> = <value>;\r
+     * FDDR->core.ddrc.<regname> = <value>;\r
+     */\r
+    DDRCore_TypeDef core;\r
+    __IO uint32_t RESERVED[39];\r
+    \r
+    /*--------------------------------------------------------------------------\r
+     * FDDR system registers\r
+     * These registers are to be accessed as:\r
+     * FDDR->sysreg.PLL_CONFIG_LOW_2 = 0x04u;\r
+     */\r
+    struct \r
+    {\r
+        __IO uint32_t PLL_CONFIG_LOW_1;\r
+        __IO uint32_t PLL_CONFIG_LOW_2;\r
+        __IO uint32_t PLL_CONFIG_HIGH;\r
+        __IO uint32_t FACC_CLK_EN;\r
+        __IO uint32_t FACC_MUX_CONFIG;\r
+        __IO uint32_t FACC_DIVISOR_RATIO;\r
+        __IO uint32_t PLL_DELAY_LINE_SEL;\r
+        __IO uint32_t SOFT_RESET; \r
+        __IO uint32_t IO_CALIB;\r
+        __IO uint32_t INTERRUPT_ENABLE;\r
+        __IO uint32_t AXI_AHB_MODE_SEL;\r
+        __IO uint32_t PHY_SELF_REF_EN;\r
+        __IO uint32_t FAB_PLL_CLK_SR;\r
+        __IO uint32_t FPLL_CLK_SR;\r
+        __IO uint32_t CLK_CALIB_STATUS;\r
+        __IO uint32_t INTERRUPT_SR;\r
+        __IO uint32_t CLK_CALIB_CONFIG;\r
+        __IO uint32_t IO_CALIB_SR;\r
+        __IO uint32_t FATC_RESET;\r
+    } sysreg;\r
+} FDDR_TypeDef;\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/*------------------------------ SERDES Interface ----------------------------*/\r
+/*----------------------------------------------------------------------------*/\r
+\r
+/*------------------------------------------------------------------------------\r
+  AXI window\r
+ */\r
+typedef struct\r
+{\r
+    __IO    uint32_t    base;\r
+    __IO    uint32_t    size;\r
+    __IO    uint32_t    window_lsb;\r
+    __IO    uint32_t    window_msb;\r
+} axi_window_TypeDef;\r
+\r
+/*------------------------------------------------------------------------------\r
+  PCI Express Bridge Core registers.\r
+  \r
+  This data structure is used to access to the registers of the PCI Express\r
+  Bridge Core.\r
+ */\r
+typedef struct\r
+{\r
+    /*======================= Information registers ======================*/\r
+    /**\r
+      Information register: vendor_id & device_id\r
+      bits [15:0]   vendor_id\r
+      bits [31:16]  device_id\r
+     */\r
+    /* 0x000 */\r
+    __IO    uint32_t    VID_DEVID;\r
+\r
+    /**\r
+      PCI Express Control & Status Register: cfg_prmscr\r
+     */\r
+    /* 0x004 */\r
+    __IO    uint32_t    CFG_PRMSCR;\r
+    \r
+    /**\r
+      Information register: class_code\r
+     */\r
+    /* 0x008 */\r
+    __IO    uint32_t    CLASS_CODE;\r
+    \r
+    __IO    uint32_t    RESERVED0;\r
+    \r
+    /**\r
+      Bridge Configuration Register: bar0\r
+     */\r
+    /* 0x010 */\r
+    __IO    uint32_t    BAR0;\r
+    \r
+    /**\r
+      Bridge Configuration Register: bar1\r
+     */\r
+    /* 0x014 */\r
+    __IO    uint32_t    BAR1;\r
+    \r
+    /**\r
+      Bridge Configuration Register: bar2\r
+     */\r
+    /* 0x018 */\r
+    __IO    uint32_t    BAR2;\r
+    \r
+    /**\r
+      Bridge Configuration Register: bar3\r
+     */\r
+    /* 0x01C */\r
+    __IO    uint32_t    BAR3;\r
+    \r
+    /**\r
+      Bridge Configuration Register: bar4\r
+     */\r
+    /* 0x020 */\r
+    __IO    uint32_t    BAR4;\r
+    \r
+    /**\r
+      Bridge Configuration Register: bar5\r
+     */\r
+    /* 0x024 */\r
+    __IO    uint32_t    BAR5;\r
+    \r
+    __IO    uint32_t    RESERVED1;\r
+    \r
+    /**\r
+      Information register: subsystem_id\r
+     */\r
+    /* 0x02C */\r
+    __IO    uint32_t    SUBSYSTEM_ID;\r
+    \r
+    /**\r
+      PCI Express Control & Status Register: pcie_devscr\r
+     */\r
+    /* 0x030 */\r
+    __IO    uint32_t    PCIE_DEVSCR;\r
+    \r
+    /**\r
+      PCI Express Control & Status Register: pcie_linkscr\r
+     */\r
+    /* 0x034 */\r
+    __IO    uint32_t    PCIE_LINKSCR;\r
+    \r
+    /**\r
+      Bridge Configuration Register: tc_vc_mapping\r
+     */\r
+    /* 0x038 */\r
+    __IO    uint32_t    TC_VC_MAPPING;\r
+    \r
+    /**\r
+      Information register: captured_bus_device_nb\r
+     */\r
+    /* 0x03C */\r
+    __IO    uint32_t    CAPTURED_BUS_DEVICE_NB;\r
+    \r
+    /**\r
+      Endpoint Interrupt register: msi_ctrl_status\r
+     */\r
+    /* 0x040 */\r
+    __IO    uint32_t    MSI_CTRL_STATUS;\r
+    \r
+    /**\r
+      Power Management register: ltssm\r
+     */\r
+    /* 0x044 */\r
+    __IO    uint32_t    LTSSM;\r
+    \r
+    /**\r
+      Power Management register: power_mgt_capability\r
+     */\r
+    /* 0x048 */\r
+    __IO    uint32_t    POWER_MGT_CAPABILITY;\r
+    \r
+    /**\r
+      PCI Express Control & Status Register: cfg_pmscr\r
+     */\r
+    /* 0x04C */\r
+    __IO    uint32_t    CFG_PMSCR;\r
+    \r
+    /**\r
+      Bridge Configuration Register: aer_ecrc_capability\r
+     */\r
+    /* 0x050 */\r
+    __IO    uint32_t    AER_ECRC_CAPABILITY;\r
+    \r
+    /**\r
+      Bridge Configuration Register: vc1_capability\r
+     */\r
+    /* 0x054 */\r
+    __IO    uint32_t    VC1_CAPABILITY;\r
+    \r
+    /**\r
+      Bridge Configuration Register: max_payload_size\r
+     */\r
+    /* 0x058 */\r
+    __IO    uint32_t    MAX_PAYLOAD_SIZE;\r
+    \r
+    /**\r
+      Bridge Configuration Register: clkreq\r
+     */\r
+    /* 0x05C */\r
+    __IO    uint32_t    CLKREQ;\r
+    \r
+    /**\r
+      Power Management register: aspm_l0s_capability\r
+     */\r
+    /* 0x060 */\r
+    __IO    uint32_t    ASPM_L0S_CAPABILITY;\r
+    \r
+    /**\r
+      Power Management register: aspm_l1_capability\r
+     */\r
+    /* 0x064 */\r
+    __IO    uint32_t    ASPM_L1_CAPABILITY;\r
+    \r
+    /**\r
+      Power Management register: timeout_completion\r
+     */\r
+    /* 0x068 */\r
+    __IO    uint32_t    TIMEOUT_COMPLETION;\r
+\r
+    __IO    uint32_t    RESERVED2;\r
+    \r
+    /**\r
+      Power Management register: pm_data_scale\r
+     */\r
+    /* 0x070 */\r
+    __IO    uint32_t    PM_DATA_SCALE[4];\r
+    \r
+    /**\r
+      Endpoint Interrupt register: msi\r
+     */\r
+    /* 0x080 */\r
+    __IO    uint32_t    MSI[8];\r
+    \r
+    /**\r
+      Bridge Configuration Register: error_counter\r
+     */\r
+    /* 0x0A0 */\r
+    __IO    uint32_t    ERROR_COUNTER[4];\r
+    \r
+    /**\r
+      Bridge Configuration Register: credit_allocation\r
+     */\r
+    /* 0x0B0 */\r
+    __IO    uint32_t    CREDIT_ALLOCATION[4];\r
+    \r
+    /**\r
+      Address Mapping register: axi_slave_window\r
+     */\r
+    /* 0x0C0 */\r
+    axi_window_TypeDef      AXI_SLAVE_WINDOW[4];\r
+    \r
+    /**\r
+      Address Mapping register: axi_master_window\r
+     */\r
+    /* 0x100 */\r
+    axi_window_TypeDef      AXI_MASTER_WINDOW[4];\r
+    \r
+    /**\r
+      Rootport Interrupt register: imask\r
+     */\r
+    /* 0x140 */\r
+    __IO    uint32_t    IMASK;\r
+    \r
+    /**\r
+      Rootport Interrupt register: istatus\r
+     */\r
+    /* 0x144 */\r
+    __IO    uint32_t    ISTATUS;\r
+    \r
+    /**\r
+      Rootport Interrupt register: icmd\r
+     */\r
+    /* 0x148 */\r
+    __IO    uint32_t    ICMD;\r
+    \r
+    /**\r
+      Rootport Interrupt register: irstatus\r
+     */\r
+    /* 0x14C */\r
+    __IO    uint32_t    IRSTATUS;\r
+    \r
+    /**\r
+      Rootport Interrupt register: imsiaddr\r
+     */\r
+    /* 0x150 */\r
+    __IO    uint32_t    IMSIADDR;\r
+    \r
+    /**\r
+      PCI Express Control & Status Register: slotcap\r
+     */\r
+    /* 0x154 */\r
+    __IO    uint32_t    SLOTCAP;\r
+    \r
+    /**\r
+      PCI Express Control & Status Register: slotcsr\r
+     */\r
+    /* 0x158 */\r
+    __IO    uint32_t    SLOTCSR;\r
+    \r
+    /**\r
+      PCI Express Control & Status Register: rootcsr\r
+     */\r
+    /* 0x15C */\r
+    __IO    uint32_t    ROOTCSR;\r
+    \r
+    /**\r
+      Configuration Register: cfg_control\r
+     */\r
+    /* 0x160 */\r
+    __IO    uint32_t    CFG_CONTROL;\r
+    \r
+    /**\r
+      Configuration Register: cfg_write_data\r
+     */\r
+    /* 0x164 */\r
+    __IO    uint32_t    CFG_WRITE_DATA;\r
+    \r
+    /**\r
+      Configuration Register: cfg_read_data\r
+     */\r
+    /* 0x168 */\r
+    __IO    uint32_t    CFG_READ_DATA;\r
+    \r
+    /**\r
+      Information register: info\r
+     */\r
+    /* 0x16C */\r
+    __IO    uint32_t    INFO;\r
+    \r
+    /**\r
+      Input/Output Control Register: io_control\r
+     */\r
+    /* 0x170 */\r
+    __IO    uint32_t    IO_CONTROL;\r
+    \r
+    /**\r
+      Input/Output Control Register: io_addr\r
+     */\r
+    /* 0x174 */\r
+    __IO    uint32_t    IO_ADDR;\r
+    \r
+    /**\r
+      Input/Output Control Register: io_write_data\r
+     */\r
+    /* 0x178 */\r
+    __IO    uint32_t    IO_WRITE_DATA;\r
+    \r
+    /**\r
+      Input/Output Control Register: io_read_data\r
+     */\r
+    /* 0x17C */\r
+    __IO    uint32_t    IO_READ_DATA;\r
+    \r
+    /**\r
+      Configuration Register: cfg_fbe\r
+     */\r
+    /* 0x180 */\r
+    __IO    uint32_t    CFG_FBE;\r
+    \r
+    /**\r
+      Address Mapping register: prefetch_io_window\r
+     */\r
+    /* 0x184 */\r
+    __IO    uint32_t    PREFETCH_IO_WINDOW;\r
+    \r
+    __IO    uint32_t    RESERVED4[31];\r
+    \r
+    /**\r
+      Bridge Configuration Register: pcie_config\r
+     */\r
+    /* 0x204 */\r
+    __IO    uint32_t    PCIE_CONFIG;\r
+    \r
+    __IO    uint32_t    RESERVED5[10];\r
+    \r
+    /**\r
+      PCI Express Control & Status Register: pcie_dev2scr\r
+     */\r
+    /* 0x230 */\r
+    __IO    uint32_t    PCIE_DEV2SCR;\r
+    \r
+    /**\r
+      PCI Express Control & Status Register: pcie_link2scr\r
+     */\r
+    /* 0x234 */\r
+    __IO    uint32_t    PCIE_LINK2SCR;\r
+    \r
+    __IO    uint32_t    RESERVED6[10];\r
+    \r
+    /**\r
+      Power Management register: aspm_l0s_gen2 capability\r
+     */\r
+    /* 0x260 */\r
+    __IO    uint32_t    ASPM_L0S_GEN2;\r
+    \r
+    __IO    uint32_t    RESERVED7[39];\r
+    \r
+    /**\r
+      Bridge Configuration Register: k_cnt_config\r
+     */\r
+    /* 0x300 */\r
+    __IO    uint32_t    K_CNT_CONFIG[6];\r
+    \r
+    __IO    uint32_t    RESERVED8[826];\r
+    \r
+} PCIE_TypeDef;\r
+ \r
+/*------------------------------------------------------------------------------\r
+  SERDESIF System Registers.\r
+ */\r
+typedef struct\r
+{\r
+    __IO    uint32_t    SER_PLL_CONFIG_LOW;\r
+    __IO    uint32_t    SER_PLL_CONFIG_HIGH;\r
+    __IO    uint32_t    SERDESIF_SOFT_RESET;\r
+    __IO    uint32_t    SER_INTERRUPT_ENABLE;\r
+    __IO    uint32_t    CONFIG_AXI_AHB_BRIDGE;\r
+    __IO    uint32_t    CONFIG_ECC_INTR_ENABLE;\r
+    __IO    uint32_t    CONFIG_TEST_IN;\r
+    __IO    uint32_t    TEST_OUT_READ_ADDR;\r
+    __IO    uint32_t    CONFIG_PCIE_PM;\r
+    __IO    uint32_t    CONFIG_PHY_MODE_0;\r
+    __IO    uint32_t    CONFIG_PHY_MODE_1;\r
+    __IO    uint32_t    CONFIG_PHY_MODE_2;\r
+    __IO    uint32_t    CONFIG_PCIE_0;\r
+    __IO    uint32_t    CONFIG_PCIE_1;\r
+    __IO    uint32_t    CONFIG_PCIE_2;\r
+    __IO    uint32_t    CONFIG_PCIE_3;\r
+    __IO    uint32_t    CONFIG_BAR_SIZE_0_1;\r
+    __IO    uint32_t    CONFIG_BAR_SIZE_2_3;\r
+    __IO    uint32_t    CONFIG_BAR_SIZE_3_4;\r
+    __IO    uint32_t    SER_CLK_STATUS;\r
+    __IO    uint32_t    SER_CLK_CALIB_STATUS;\r
+    __IO    uint32_t    TEST_OUT_READ_DATA;\r
+    __IO    uint32_t    SER_INTERRUPT;\r
+    __IO    uint32_t    SERDESIF_INTR_STATUS;\r
+    __IO    uint32_t    SER_CLK_CALIB_CONFIG;\r
+    __IO    uint32_t    REFCLK_SEL;\r
+    __IO    uint32_t    PCLK_SEL;\r
+    __IO    uint32_t    EPCS_RSTN_SEL;\r
+    __IO    uint32_t    CHIP_ENABLES;\r
+    __IO    uint32_t    SERDES_TEST_OUT;\r
+    __IO    uint32_t    SERDES_FATC_RESET;\r
+    __IO    uint32_t    RC_OSC_SPLL_REFCLK_SEL;\r
+    __IO    uint32_t    SPREAD_SPECTRUM_CLK;\r
+    __IO    uint32_t    CONF_AXI_MSTR_WNDW_0;\r
+    __IO    uint32_t    CONF_AXI_MSTR_WNDW_1;\r
+    __IO    uint32_t    CONF_AXI_MSTR_WNDW_2;\r
+    __IO    uint32_t    CONF_AXI_MSTR_WNDW_3;\r
+    __IO    uint32_t    CONF_AXI_SLV_WNDW_0;\r
+    __IO    uint32_t    CONF_AXI_SLV_WNDW_1;\r
+    __IO    uint32_t    CONF_AXI_SLV_WNDW_2;\r
+    __IO    uint32_t    CONF_AXI_SLV_WNDW_3;\r
+    __IO    uint32_t    DESKEW_CONFIG;\r
+    __IO    uint32_t    DEBUG_MODE_KEY;\r
+    __IO    uint32_t    RESERVED0;\r
+    __IO    uint32_t    EXTRA_BITS;\r
+} SERDES_INTF_SYSREG_TypeDef;\r
+\r
+/*------------------------------------------------------------------------------\r
+  SERDES PHY registers\r
+ */\r
+typedef struct\r
+{\r
+    /**\r
+      Control register 0\r
+     */\r
+    __IO    uint32_t    CR0;\r
+    \r
+    /**\r
+      Clock count for error counter decrement\r
+     */\r
+    __IO    uint32_t    ERRCNT_DEC;\r
+    \r
+    /**\r
+      Error counter threshold - Rx idle detect max latency\r
+     */\r
+    __IO    uint32_t    RXIDLE_MAX_ERRCNT_THR;\r
+    \r
+    /**\r
+      Tx Impedance ratio\r
+     */\r
+    __IO    uint32_t    IMPED_RATIO;\r
+    \r
+    /**\r
+      PLL F settings and PCLK ratio\r
+     */\r
+    __IO    uint32_t    PLL_F_PCLK_RATIO;\r
+    \r
+    /**\r
+      PLL M & N settings\r
+     */\r
+    __IO    uint32_t    PLL_M_N;\r
+    \r
+    /**\r
+      250ns timer base count\r
+     */\r
+    __IO    uint32_t    CNT250NS_MAX;\r
+    \r
+    /**\r
+      Rx Equalization amplitude ratio\r
+     */\r
+    __IO    uint32_t    RE_AMP_RATIO;\r
+    \r
+    /**\r
+      Rx Equalization Cut frequency\r
+     */\r
+    __IO    uint32_t    RE_CUT_RATIO;\r
+    \r
+    /**\r
+      Tx Amplitude ratio\r
+     */\r
+    __IO    uint32_t    TX_AMP_RATIO;\r
+    \r
+    /**\r
+      Tx Post-Cursor ratio\r
+     */\r
+    __IO    uint32_t    TX_PST_RATIO;\r
+    \r
+    /**\r
+      Tx Pre-Cursor ratio\r
+     */\r
+    __IO    uint32_t    TX_PRE_RATIO;\r
+    \r
+    /**\r
+      End of calibration counter\r
+     */\r
+    __IO    uint32_t    ENDCALIB_MAX;\r
+    \r
+    /**\r
+      Calibration stability counter\r
+     */\r
+    __IO    uint32_t    CALIB_STABILITY_COUNT;\r
+    \r
+    /**\r
+      Power down feature\r
+     */\r
+    __IO    uint32_t    POWER_DOWN;\r
+    \r
+    /**\r
+      Rx offset counter\r
+     */\r
+    __IO    uint32_t    RX_OFFSET_COUNT;\r
+    \r
+    /**\r
+      PLL F settings and PCLK ratio (in PCIe 5 Gbps speed)\r
+     */\r
+    __IO    uint32_t    PLL_F_PCLK_RATIO_5GBPS;\r
+    \r
+    /**\r
+      PLL M & N sttings (in PCIe 5 Gbps spped)\r
+     */\r
+    __IO    uint32_t    PLL_M_N_5GBPS;\r
+    \r
+    /**\r
+      250ns timer base count (in PCIe 5 Gbps speed)\r
+     */\r
+    __IO    uint32_t    CNT250NS_MAX_5GBPS;\r
+    \r
+    /**\r
+      reserved\r
+     */\r
+    __IO    uint32_t    RESERVED;\r
+    \r
+    /**\r
+      Tx Post-Cursor ratio with TxDeemp=0, Full swing\r
+     */\r
+    __IO    uint32_t    TX_PST_RATIO_DEEMP0_FULL;\r
+    \r
+    /**\r
+      Tx Pre-Cursor ratio TxDeemp=0, full swing\r
+     */\r
+    __IO    uint32_t    TX_PRE_RATIO_DEEMP0_FULL;\r
+    \r
+    /**\r
+      Tx Post-Cursor ratio with TxDeemp=1, Full swing\r
+     */\r
+    __IO    uint32_t    TX_PST_RATIO_DEEMP1_FULL;\r
+    \r
+    /**\r
+      Tx Pre-Cursor ratio TxDeemp=1, full swing\r
+     */\r
+    __IO    uint32_t    TX_PRE_RATIO_DEEMP1_FULL;\r
+    \r
+    /**\r
+      Tx Amplitude ratio TxMargin=0, full swing\r
+     */\r
+    __IO    uint32_t    TX_AMP_RATIO_MARGIN0_FULL;\r
+    \r
+    /**\r
+      Tx Amplitude ratio TxMargin=1, full swing\r
+     */\r
+    __IO    uint32_t    TX_AMP_RATIO_MARGIN1_FULL;\r
+    \r
+    /**\r
+      Tx Amplitude ratio TxMargin=2, full swing\r
+     */\r
+    __IO    uint32_t    TX_AMP_RATIO_MARGIN2_FULL;\r
+    \r
+    /**\r
+      Tx Amplitude ratio TxMargin=3, full swing\r
+     */\r
+    __IO    uint32_t    TX_AMP_RATIO_MARGIN3_FULL;\r
+    \r
+    /**\r
+      Tx Amplitude ratio TxMargin=4, full swing\r
+     */\r
+    __IO    uint32_t    TX_AMP_RATIO_MARGIN4_FULL;\r
+    \r
+    /**\r
+      Tx Amplitude ratio TxMargin=5, full swing\r
+     */\r
+    __IO    uint32_t    TX_AMP_RATIO_MARGIN5_FULL;\r
+    \r
+    /**\r
+      Tx Amplitude ratio TxMargin=6, full swing\r
+     */\r
+    __IO    uint32_t    TX_AMP_RATIO_MARGIN6_FULL;\r
+    \r
+    /**\r
+      Tx Amplitude ratio TxMargin=7, full swing\r
+     */\r
+    __IO    uint32_t    TX_AMP_RATIO_MARGIN7_FULL;\r
+    \r
+    /**\r
+      Rx Equalization amplitude ratio TxDeemp=0\r
+     */\r
+    __IO    uint32_t    RE_AMP_RATIO_DEEMP0;\r
+    \r
+    /**\r
+      Rx Equalization Cut frequency TxDeemp=0\r
+     */\r
+    __IO    uint32_t    RE_CUT_RATIO_DEEMP0;\r
+    \r
+    /**\r
+      Rx Equalization amplitude ratio TxDeemp=1\r
+     */\r
+    __IO    uint32_t    RE_AMP_RATIO_DEEMP1;\r
+    \r
+    /**\r
+      Rx Equalization Cut frequency TxDeemp=1\r
+     */\r
+    __IO    uint32_t    RE_CUT_RATIO_DEEMP1;\r
+    \r
+    /**\r
+      Tx Post-Cursor ratio with TxDeemp=0, Half swing\r
+     */\r
+    __IO    uint32_t    TX_PST_RATIO_DEEMP0_HALF;\r
+    \r
+    /**\r
+      Tx Pre-Cursor ratio TxDeemp=0, Half swing\r
+     */\r
+    __IO    uint32_t    TX_PRE_RATIO_DEEMP0_HALF;\r
+    \r
+    /**\r
+      Tx Post-Cursor ratio with TxDeemp=1, Half swing\r
+     */\r
+    __IO    uint32_t    TX_PST_RATIO_DEEMP1_HALF;\r
+    \r
+    /**\r
+      Tx Pre-Cursor ratio TxDeemp=1, Half swing\r
+     */\r
+    __IO    uint32_t    TX_PRE_RATIO_DEEMP1_HALF;\r
+    \r
+    /**\r
+      Tx Amplitude ratio TxMargin=0, Half swing\r
+     */\r
+    __IO    uint32_t    TX_AMP_RATIO_MARGIN0_HALF;\r
+    \r
+    /**\r
+      Tx Amplitude ratio TxMargin=1, Half swing\r
+     */\r
+    __IO    uint32_t    TX_AMP_RATIO_MARGIN1_HALF;\r
+    \r
+    /**\r
+      Tx Amplitude ratio TxMargin=2, Half swing\r
+     */\r
+    __IO    uint32_t    TX_AMP_RATIO_MARGIN2_HALF;\r
+    \r
+    /**\r
+      Tx Amplitude ratio TxMargin=3, Half swing\r
+     */\r
+    __IO    uint32_t    TX_AMP_RATIO_MARGIN3_HALF;\r
+    \r
+    /**\r
+      Tx Amplitude ratio TxMargin=4, Half swing\r
+     */\r
+    __IO    uint32_t    TX_AMP_RATIO_MARGIN4_HALF;\r
+    \r
+    /**\r
+      Tx Amplitude ratio TxMargin=5, Half swing\r
+     */\r
+    __IO    uint32_t    TX_AMP_RATIO_MARGIN5_HALF;\r
+    \r
+    /**\r
+      Tx Amplitude ratio TxMargin=6, Half swing\r
+     */\r
+    __IO    uint32_t    TX_AMP_RATIO_MARGIN6_HALF;\r
+    \r
+    /**\r
+      Tx Amplitude ratio TxMargin=7, Half swing\r
+     */\r
+    __IO    uint32_t    TX_AMP_RATIO_MARGIN7_HALF;\r
+    \r
+    /**\r
+      PMA status\r
+     */\r
+    __IO    uint32_t    PMA_STATUS;\r
+    \r
+    /**\r
+      Tx sweep center (RO)\r
+     */\r
+    __IO    uint32_t    TX_SWEEP_CENTER;\r
+    \r
+    /**\r
+      Rx seep center (RO)\r
+     */\r
+    __IO    uint32_t    RX_SWEEP_CENTER;\r
+    \r
+    /**\r
+      Rx Equalization sweep center (RO)\r
+     */\r
+    __IO    uint32_t    RE_SWEEP_CENTER;\r
+    \r
+    /**\r
+      Receiver Shift Loader parameter 0 (RO)\r
+     */\r
+    __IO    uint32_t    ATXDRR_7_0;\r
+    \r
+    /**\r
+      Receiver Shift Loader parameter 1 (RO)\r
+     */\r
+    __IO    uint32_t    ATXDRR_14_8;\r
+    \r
+    /**\r
+      Transmitter P Shift Loader parameter0-0\r
+     */\r
+    __IO    uint32_t    ATXDRP_DYN_7_0;\r
+    \r
+    /**\r
+      Transmitter P Shift Loader parameter0-1\r
+     */\r
+    __IO    uint32_t    ATXDRP_DYN_15_8;\r
+    \r
+    /**\r
+      Transmitter P Shift Loader parameter0-2\r
+     */\r
+    __IO    uint32_t    ATXDRP_DYN_20_16;\r
+    \r
+    /**\r
+      Transmitter A Shift Loader parameter0-0\r
+     */\r
+    __IO    uint32_t    ATXDRA_DYN_7_0;\r
+    \r
+    /**\r
+      Transmitter A Shift Loader parameter0-1\r
+     */\r
+    __IO    uint32_t    ATXDRA_DYN_15_8;\r
+    \r
+    /**\r
+      Transmitter A Shift Loader parameter0-2\r
+     */\r
+    __IO    uint32_t    ATXDRA_DYN_20_16;\r
+    \r
+    /**\r
+      Transmitter T Shift Loader parameter0-0\r
+     */\r
+    __IO    uint32_t    ATXDRT_DYN_7_0;\r
+    \r
+    /**\r
+      Transmitter T Shift Loader parameter0-1\r
+     */\r
+    __IO    uint32_t    ATXDRT_DYN_15_8;\r
+    \r
+    /**\r
+      Transmitter T Shift Loader parameter0-2\r
+     */\r
+    __IO    uint32_t    ATXDRT_DYN_20_16;\r
+    \r
+    /**\r
+      Transmitter P Shift Loader parameter 1-0 (RO)\r
+     */\r
+    __IO    uint32_t    ATXDRP_EI1_7_0;\r
+    \r
+    /**\r
+      Transmitter P Shift Loader parameter 1-1 (RO)\r
+     */\r
+    __IO    uint32_t    ATXDRP_EI1_15_8;\r
+    \r
+    /**\r
+      Transmitter P Shift Loader parameter 1-2 (RO)\r
+     */\r
+    __IO    uint32_t    ATXDRP_EI1_20_16;\r
+    \r
+    /**\r
+      Transmitter A Shift Loader parameter 1-0 (RO)\r
+     */\r
+    __IO    uint32_t    ATXDRA_EI1_7_0;\r
+    \r
+    /**\r
+      Transmitter A Shift Loader parameter 1-1 (RO)\r
+     */\r
+    __IO    uint32_t    ATXDRA_EI1_15_8;\r
+    \r
+    /**\r
+      Transmitter A Shift Loader parameter 1-2 (RO)\r
+     */\r
+    __IO    uint32_t    ATXDRA_EI1_20_16;\r
+    \r
+    /**\r
+      Transmitter T Shift Loader parameter 1-0 (RO)\r
+     */\r
+    __IO    uint32_t    ATXDRT_EI1_7_0;\r
+    \r
+    /**\r
+      Transmitter T Shift Loader parameter 1-1 (RO)\r
+     */\r
+    __IO    uint32_t    ATXDRT_EI1_15_8;\r
+    \r
+    /**\r
+      Transmitter T Shift Loader parameter 1-2 (RO)\r
+     */\r
+    __IO    uint32_t    ATXDRT_EI1_20_16;\r
+    \r
+    /**\r
+      Transmitter P shift Loader parameter 2-0 (RO)\r
+     */\r
+    __IO    uint32_t    ATXDRP_EI2_7_0;\r
+    \r
+    /**\r
+      Transmitter P shift Loader parameter 2-1 (RO)\r
+     */\r
+    __IO    uint32_t    ATXDRP_EI2_15_8;\r
+    \r
+    /**\r
+      Transmitter P shift Loader parameter 2-2 (RO)\r
+     */\r
+    __IO    uint32_t    ATXDRP_EI2_20_16;\r
+    \r
+    /**\r
+      Transmitter A Shift parametr 2-0 (RO)\r
+     */\r
+    __IO    uint32_t    ATXDRA_EI2_7_0;\r
+    \r
+    /**\r
+      Transmitter A Shift parametr 2-1 (RO)\r
+     */\r
+    __IO    uint32_t    ATXDRA_EI2_15_8;\r
+    \r
+    /**\r
+      Transmitter A Shift parametr 2-2 (RO)\r
+     */\r
+    __IO    uint32_t    ATXDRA_EI2_20_16;\r
+    \r
+    /**\r
+      Transmitter T Shift parametr 2-0 (RO)\r
+     */\r
+    __IO    uint32_t    ATXDRT_EI2_7_0;\r
+    \r
+    /**\r
+      Transmitter T Shift parametr 2-1 (RO)\r
+     */\r
+    __IO    uint32_t    ATXDRT_EI2_15_8;\r
+    \r
+    /**\r
+      Transmitter T Shift parametr 2-2 (RO)\r
+     */\r
+    __IO    uint32_t    ATXDRT_EI2_20_16;\r
+    \r
+    /**\r
+      Override calibration register (RW)\r
+     */\r
+    __IO    uint32_t    OVERRIDE_CALIB;\r
+    \r
+    /**\r
+      Force Receiver Shift Loader parameter 0 (RW)\r
+     */\r
+    __IO    uint32_t    FORCE_ATXDRR_7_0;\r
+    \r
+    /**\r
+      Force Receiver Shift Loader parameter 1 (RW)\r
+     */\r
+    __IO    uint32_t    FORCE_ATXDRR_15_8;\r
+    \r
+    /**\r
+      Force Receiver Shift Loader parameter 2 (RW)\r
+     */\r
+    __IO    uint32_t    FORCE_ATXDRR_20_16;\r
+    \r
+    /**\r
+      Force Transmitter P Shift Loader parameter 0 (RW)\r
+     */\r
+    __IO    uint32_t    FORCE_ATXDRP_7_0;\r
+    \r
+    /**\r
+      Force Transmitter P Shift Loader parameter 1 (RW)\r
+     */\r
+    __IO    uint32_t    FORCE_ATXDRP_15_8;\r
+    \r
+    /**\r
+      Force Transmitter P Shift Loader parameter 2 (RW)\r
+     */\r
+    __IO    uint32_t    FORCE_ATXDRP_20_16;\r
+    \r
+    /**\r
+      Force Transmitter A Shift Loader parameter 0 (RW)\r
+     */\r
+    __IO    uint32_t    FORCE_ATXDRA_7_0;\r
+    \r
+    /**\r
+      Force Transmitter A Shift Loader parameter 1 (RW)\r
+     */\r
+    __IO    uint32_t    FORCE_ATXDRA_15_8;\r
+    \r
+    /**\r
+      Force Transmitter A Shift Loader parameter 2 (RW)\r
+     */\r
+    __IO    uint32_t    FORCE_ATXDRA_20_16;\r
+    \r
+    /**\r
+      Force Transmitter T Shift parameter 0-0 (RO)\r
+     */\r
+    __IO    uint32_t    FORCE_ATXDRT_7_0;\r
+    \r
+    /**\r
+      Force Transmitter T Shift parameter 0-1 (RO)\r
+     */\r
+    __IO    uint32_t    FORCE_ATXDRT_15_8;\r
+    \r
+    /**\r
+      Force Transmitter T Shift parameter 0-2 (RO)\r
+     */\r
+    __IO    uint32_t    FORCE_ATXDRT_20_16;\r
+    \r
+    /**\r
+      RxD offset calibration result (RO)\r
+     */\r
+    __IO    uint32_t    RXD_OFFSET_CALIB_RESULT;\r
+    \r
+    /**\r
+      RxT offset calibration result (RO)\r
+     */\r
+    __IO    uint32_t    RXT_OFFSET_CALIB_RESULT;\r
+    \r
+    /**\r
+      Schmitt trigger calibration result (RO)\r
+     */\r
+    __IO    uint32_t    SCHMITT_TRIG_CALIB_RESULT;\r
+    \r
+    /**\r
+      Force RxD offset calibration settings (RW)\r
+     */\r
+    __IO    uint32_t    FORCE_RXD_OFFSET_CALIB;\r
+    \r
+    /**\r
+      Force RxT offset calibration settings (RW)\r
+     */\r
+    __IO    uint32_t    FORCE_RXT_OFFSET_CALIB;\r
+    \r
+    /**\r
+      Force Schmitt trigger calibration settings (RW)\r
+     */\r
+    __IO    uint32_t    FORCE_SCHMITT_TRIG_CALIB;\r
+    \r
+    /**\r
+      PRBS control register (RW)\r
+     */\r
+    __IO    uint32_t    PRBS_CTRL;\r
+    \r
+    /**\r
+      PRBS error counter register (RO)\r
+     */\r
+    __IO    uint32_t    PRBS_ERRCNT;\r
+    \r
+    /**\r
+      PHY reset override register (RW)\r
+     */\r
+    __IO    uint32_t    PHY_RESET_OVERRIDE;\r
+    \r
+    /**\r
+      PHY power override register (RW)\r
+     */\r
+    __IO    uint32_t    PHY_POWER_OVERRIDE;\r
+    \r
+    /**\r
+      Custom Pattern Byte 0 (RW)\r
+     */\r
+    __IO    uint32_t    CUSTOM_PATTERN_7_0;\r
+    \r
+    /**\r
+      Custom Pattern Byte 1 (RW)\r
+     */\r
+    __IO    uint32_t    CUSTOM_PATTERN_15_8;\r
+    \r
+    /**\r
+      Custom Pattern Byte 2 (RW)\r
+     */\r
+    __IO    uint32_t    CUSTOM_PATTERN_23_16;\r
+    \r
+    /**\r
+      Custom Pattern Byte 3 (RW)\r
+     */\r
+    __IO    uint32_t    CUSTOM_PATTERN_31_24;\r
+    \r
+    /**\r
+      Custom Pattern Byte 4 (RW)\r
+     */\r
+    __IO    uint32_t    CUSTOM_PATTERN_39_32;\r
+    \r
+    /**\r
+      Custom Pattern Byte 5 (RW)\r
+     */\r
+    __IO    uint32_t    CUSTOM_PATTERN_47_40;\r
+    \r
+    /**\r
+      Custom Pattern Byte 6 (RW)\r
+     */\r
+    __IO    uint32_t    CUSTOM_PATTERN55_48;\r
+    \r
+    /**\r
+      Custom Pattern Byte 7 (RW)\r
+     */\r
+    __IO    uint32_t    CUSTOM_PATTERN_63_56;\r
+    \r
+    /**\r
+      Custom Pattern Byte 8 (RW)\r
+     */\r
+    __IO    uint32_t    CUSTOM_PATTERN_71_64;\r
+    \r
+    /**\r
+      Custom Pattern Byte 9 (RW)\r
+     */\r
+    __IO    uint32_t    CUSTOM_PATTERN_79_72;\r
+    \r
+    /**\r
+      Custom Pattern Control (RW)\r
+     */\r
+    __IO    uint32_t    CUSTOM_PATTERN_CTRL;\r
+    \r
+    /**\r
+      Custom Pattern Status register (RO)\r
+     */\r
+    __IO    uint32_t    CUSTOM_PATTERN_STATUS;\r
+    \r
+    /**\r
+      PCS Loopback Control (RW)\r
+     */\r
+    __IO    uint32_t    PCS_LOOPBBACK_CTRL;\r
+    \r
+    /**\r
+      Gen1 Transmit PLL Current Charge Pump (RW)\r
+     */\r
+    __IO    uint32_t    GEN1_TX_PLL_CCP;\r
+    \r
+    /**\r
+      Gen1 Receive PLL Current Charge Pump (RW)\r
+     */\r
+    __IO    uint32_t    GEN1_RX_PLL_CCP;\r
+    \r
+    /**\r
+      Gen2 Transmit PLL Current Charge Pump (RW)\r
+     */\r
+    __IO    uint32_t    GEN2_TX_PLL_CCP;\r
+    \r
+    /**\r
+      Gen2 Receive PLL Current Charge Pump (RW)\r
+     */\r
+    __IO    uint32_t    GEN2_RX_PLL_CCP;\r
+    \r
+    /**\r
+      CDR PLL manual control\r
+     */\r
+    __IO    uint32_t    CDR_PLL_MANUAL_CR;\r
+    \r
+    /**\r
+      Reserved0\r
+     */\r
+    __IO    uint32_t    RESERVED0[6];\r
+    \r
+    /**\r
+      Update settings command register\r
+     */\r
+    __IO    uint32_t    UPDATE_SETTINGS;\r
+    \r
+    /**\r
+      Reserved1\r
+     */\r
+    __IO    uint32_t    RESERVED1[31];\r
+    \r
+    /**\r
+      PRBS first error cycle counter bits [7:0]\r
+     */\r
+    __IO    uint32_t    PRBS_ERR_CYC_FIRST_7_0;\r
+    \r
+    /**\r
+      PRBS first error cycle counter bits [15:8]\r
+     */\r
+    __IO    uint32_t    PRBS_ERR_CYC_FIRST_15_8;\r
+    \r
+    /**\r
+      PRBS first error cycle counter bits [23:16]\r
+     */\r
+    __IO    uint32_t    PRBS_ERR_CYC_FIRST_23_16;\r
+    \r
+    /**\r
+      PRBS first error cycle counter bits [31:24]\r
+     */\r
+    __IO    uint32_t    PRBS_ERR_CYC_FIRST_31_24;\r
+    \r
+    /**\r
+      PRBS first error cycle counter bits [39:32]\r
+     */\r
+    __IO    uint32_t    PRBS_ERR_CYC_FIRST_39_32;\r
+    \r
+    /**\r
+      PRBS first error cycle counter bits [47:40]\r
+     */\r
+    __IO    uint32_t    PRBS_ERR_CYC_FIRST_47_40;\r
+    \r
+    /**\r
+      PRBS first error cycle counter bits [49:48]\r
+     */\r
+    __IO    uint32_t    PRBS_ERR_CYC_FIRST_49_48;\r
+    \r
+    /**\r
+      Reserved2\r
+     */\r
+    __IO    uint32_t    RESERVED2;\r
+    \r
+    /**\r
+      PRBS last error cycle counter bits [7:0]\r
+     */\r
+    __IO    uint32_t    PRBS_ERR_CYC_LAST_7_0;\r
+    \r
+    /**\r
+      PRBS last error cycle counter bits [15:8]\r
+     */\r
+    __IO    uint32_t    PRBS_ERR_CYC_LAST_15_8;\r
+    \r
+    /**\r
+      PRBS last error cycle counter bits [23:16]\r
+     */\r
+    __IO    uint32_t    PRBS_ERR_CYC_LAST_23_16;\r
+    \r
+    /**\r
+      PRBS last error cycle counter bits [31:24]\r
+     */\r
+    __IO    uint32_t    PRBS_ERR_CYC_LAST_31_24;\r
+    \r
+    /**\r
+      PRBS last error cycle counter bits [39:32]\r
+     */\r
+    __IO    uint32_t    PRBS_ERR_CYC_LAST_39_32;\r
+    \r
+    /**\r
+      PRBS last error cycle counter bits [47:40]\r
+     */\r
+    __IO    uint32_t    PRBS_ERR_CYC_LAST_47_40;\r
+    \r
+    /**\r
+      PRBS last error cycle counter bits [49:48]\r
+     */\r
+    __IO    uint32_t    PRBS_ERR_CYC_LAST_49_48;\r
+    \r
+    /**\r
+      Reserved3\r
+     */\r
+    __IO    uint32_t    RESERVED3[81];\r
+    \r
+} SERDES_TypeDef;\r
+ \r
+/*-------------------------------------------------------------------------*//**\r
+  The serdesif_regs_t data structure provides access to the complete set of the\r
+  SERDES Interface hardware block configuration registers. These registers are\r
+  accessed through the APB interface of the SERDES Interface hardware block.\r
+ */\r
+typedef struct\r
+{\r
+    /**\r
+      PCIe core registers.\r
+     */\r
+    PCIE_TypeDef                core;\r
+    \r
+    /**\r
+      SERDES macro registers.\r
+     */\r
+    SERDES_TypeDef              lane[4];\r
+    \r
+    /**\r
+      SERDESIF system registers.\r
+     */\r
+    SERDES_INTF_SYSREG_TypeDef     sys_regs;\r
+    \r
+} SERDESIF_TypeDef;\r
+\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/*------------------------------ System Registers ----------------------------*/\r
+/*----------------------------------------------------------------------------*/\r
+typedef struct\r
+{\r
+    __IO     uint32_t    ESRAM_CR;                                 /*0X0   */\r
+    __IO     uint32_t    ESRAM_MAX_LAT_CR;                         /*0X4   */\r
+    __IO     uint32_t    DDR_CR;                                   /*0X8   */\r
+    __IO     uint32_t    ENVM_CR;                                  /*0XC   */\r
+    __IO     uint32_t    ENVM_REMAP_BASE_CR;                       /*0X10  */\r
+    __IO     uint32_t    ENVM_REMAP_FAB_CR;                        /*0X14  */\r
+    __IO     uint32_t    CC_CR;                                    /*0X18  */\r
+    __IO     uint32_t    CC_REGION_CR;                             /*0X1C  */\r
+    __IO     uint32_t    CC_LOCK_BASE_ADDR_CR;                     /*0X20  */\r
+    __IO     uint32_t    CC_FLUSH_INDX_CR;                         /*0X24  */\r
+    __IO     uint32_t    DDRB_BUF_TIMER_CR;                        /*0X28  */\r
+    __IO     uint32_t    DDRB_NB_ADDR_CR;                          /*0X2C  */\r
+    __IO     uint32_t    DDRB_NB_SIZE_CR;                          /*0X30  */\r
+    __IO     uint32_t    DDRB_CR;                                  /*0X34  */\r
+    __IO     uint32_t    EDAC_CR;                                  /*0X38  */\r
+    __IO     uint32_t    MASTER_WEIGHT0_CR;                        /*0X3C  */\r
+    __IO     uint32_t    MASTER_WEIGHT1_CR;                        /*0X40  */\r
+    __IO     uint32_t    SOFT_IRQ_CR;                              /*0X44  */\r
+    __IO     uint32_t    SOFT_RST_CR;                              /*0X48  */\r
+    __IO     uint32_t    M3_CR;                                    /*0X4C  */\r
+    __IO     uint32_t    FAB_IF_CR;                                /*0X50  */\r
+    __IO     uint32_t    LOOPBACK_CR;                              /*0X54  */\r
+    __IO     uint32_t    GPIO_SYSRESET_SEL_CR;                     /*0X58  */\r
+    __IO     uint32_t    GPIN_SRC_SEL_CR;                          /*0X5C  */\r
+    __IO     uint32_t    MDDR_CR;                                  /*0X60  */\r
+    __IO     uint32_t    USB_IO_INPUT_SEL_CR;                      /*0X64  */\r
+    __IO     uint32_t    PERIPH_CLK_MUX_SEL_CR;                    /*0X68  */\r
+    __IO     uint32_t    WDOG_CR;                                  /*0X6C  */\r
+    __IO     uint32_t    MDDR_IO_CALIB_CR;                         /*0X70  */\r
+    __IO     uint32_t    SPARE_OUT_CR;                             /*0X74  */\r
+    __IO     uint32_t    EDAC_IRQ_ENABLE_CR;                       /*0X78  */\r
+    __IO     uint32_t    USB_CR;                                   /*0X7C  */\r
+    __IO     uint32_t    ESRAM_PIPELINE_CR;                        /*0X80  */\r
+    __IO     uint32_t    MSS_IRQ_ENABLE_CR;                        /*0X84  */\r
+    __IO     uint32_t    RTC_WAKEUP_CR;                            /*0X88  */\r
+    __IO     uint32_t    MAC_CR;                                   /*0X8C  */\r
+    __IO     uint32_t    MSSDDR_PLL_STATUS_LOW_CR;                 /*0X90  */\r
+    __IO     uint32_t    MSSDDR_PLL_STATUS_HIGH_CR;                /*0X94  */\r
+    __IO     uint32_t    MSSDDR_FACC1_CR;                          /*0X98  */\r
+    __IO     uint32_t    MSSDDR_FACC2_CR;                          /*0X9C  */\r
+    __IO     uint32_t    PLL_LOCK_EN_CR;                           /*0XA0  */\r
+    __IO     uint32_t    MSSDDR_CLK_CALIB_CR;                      /*0XA4  */\r
+    __IO     uint32_t    PLL_DELAY_LINE_SEL_CR;                    /*0XA8  */\r
+    __IO     uint32_t    MAC_STAT_CLRONRD_CR;                      /*0XAC  */\r
+    __IO     uint32_t    RESET_SOURCE_CR;                          /*0XB0  */\r
+    __I      uint32_t    CC_DC_ERR_ADDR_SR;                        /*0XB4  */\r
+    __I      uint32_t    CC_IC_ERR_ADDR_SR;                        /*0XB8  */\r
+    __I      uint32_t    CC_SB_ERR_ADDR_SR;                        /*0XBC  */\r
+    __I      uint32_t    CC_DECC_ERR_ADDR_SR;                      /*0XC0  */\r
+    __I      uint32_t    CC_IC_MISS_CNT_SR;                        /*0XC4  */\r
+    __I      uint32_t    CC_IC_HIT_CNT_SR;                         /*0XC8  */\r
+    __I      uint32_t    CC_DC_MISS_CNT_SR;                        /*0XCC  */\r
+    __I      uint32_t    CC_DC_HIT_CNT_SR;                         /*0XD0  */\r
+    __I      uint32_t    CC_IC_TRANS_CNT_SR;                       /*0XD4  */\r
+    __I      uint32_t    CC_DC_TRANS_CNT_SR;                       /*0XD8  */\r
+    __I      uint32_t    DDRB_DS_ERR_ADR_SR;                       /*0XDC  */\r
+    __I      uint32_t    DDRB_HPD_ERR_ADR_SR;                      /*0XE0  */\r
+    __I      uint32_t    DDRB_SW_ERR_ADR_SR;                       /*0XE4  */\r
+    __I      uint32_t    DDRB_BUF_EMPTY_SR;                        /*0XE8  */\r
+    __I      uint32_t    DDRB_DSBL_DN_SR;                          /*0XEC  */\r
+    __I      uint32_t    ESRAM0_EDAC_CNT;                          /*0XF0  */\r
+    __I      uint32_t    ESRAM1_EDAC_CNT;                          /*0XF4  */\r
+    __I      uint32_t    CC_EDAC_CNT;                              /*0XF8  */\r
+    __I      uint32_t    MAC_EDAC_TX_CNT;                          /*0XFC  */\r
+    __I      uint32_t    MAC_EDAC_RX_CNT;                          /*0X100 */\r
+    __I      uint32_t    USB_EDAC_CNT;                             /*0X104 */\r
+    __I      uint32_t    CAN_EDAC_CNT;                             /*0X108 */\r
+    __I      uint32_t    ESRAM0_EDAC_ADR;                          /*0X10C */\r
+    __I      uint32_t    ESRAM1_EDAC_ADR;                          /*0X110 */\r
+    __I      uint32_t    MAC_EDAC_RX_ADR;                          /*0X114 */\r
+    __I      uint32_t    MAC_EDAC_TX_ADR;                          /*0X118 */\r
+    __I      uint32_t    CAN_EDAC_ADR;                             /*0X11C */\r
+    __I      uint32_t    USB_EDAC_ADR;                             /*0X120 */\r
+    __I      uint32_t    MM0_1_2_SECURITY;                         /*0X124 */\r
+    __I      uint32_t    MM4_5_FIC64_SECURITY;                     /*0X128 */\r
+    __I      uint32_t    MM3_6_7_8_SECURITY;                       /*0X12C */\r
+    __I      uint32_t    MM9_SECURITY;                             /*0X130 */\r
+    __I      uint32_t    M3_SR;                                    /*0X134 */\r
+    __I      uint32_t    ETM_COUNT_LOW;                            /*0X138 */\r
+    __I      uint32_t    ETM_COUNT_HIGH;                           /*0X13C */\r
+    __I      uint32_t    DEVICE_SR;                                /*0X140 */\r
+    __I      uint32_t    ENVM_PROTECT_USER;                        /*0X144 */\r
+    __I      uint32_t    ENVM_STATUS;                              /*0X148 */\r
+    __I      uint32_t    DEVICE_VERSION;                           /*0X14C */\r
+    __I      uint32_t    MSSDDR_PLL_STATUS;                        /*0X150 */\r
+    __I      uint32_t    USB_SR;                                   /*0X154 */\r
+    __I      uint32_t    ENVM_SR;                                  /*0X158 */\r
+    __I      uint32_t    SPARE_IN;                                 /*0X15C */\r
+    __I      uint32_t    DDRB_STATUS;                              /*0X160 */\r
+    __I      uint32_t    MDDR_IO_CALIB_STATUS;                     /*0X164 */\r
+    __I      uint32_t    MSSDDR_CLK_CALIB_STATUS;                  /*0X168 */\r
+    __I      uint32_t    WDOGLOAD;                                 /*0X16C */\r
+    __I      uint32_t    WDOGMVRP;                                 /*0X170 */\r
+    __I      uint32_t    USERCONFIG0;                              /*0X174 */\r
+    __I      uint32_t    USERCONFIG1;                              /*0X178 */\r
+    __I      uint32_t    USERCONFIG2;                              /*0X17C */\r
+    __I      uint32_t    USERCONFIG3;                              /*0X180 */\r
+    __I      uint32_t    FAB_PROT_SIZE;                            /*0X184 */\r
+    __I      uint32_t    FAB_PROT_BASE;                            /*0X188 */\r
+    __I      uint32_t    MSS_GPIO_DEF;                             /*0X18C */\r
+    __IO     uint32_t    EDAC_SR;                                  /*0X190 */\r
+    __IO     uint32_t    MSS_INTERNAL_SR;                          /*0X194 */\r
+    __IO     uint32_t    MSS_EXTERNAL_SR;                          /*0X198 */\r
+    __IO     uint32_t    WDOGTIMEOUTEVENT;                         /*0X19C */\r
+    __IO     uint32_t    CLR_MSS_COUNTERS;                         /*0X1A0 */\r
+    __IO     uint32_t    CLR_EDAC_COUNTERS;                        /*0X1A4 */\r
+    __IO     uint32_t    FLUSH_CR;                                 /*0X1A8 */\r
+    __IO     uint32_t    MAC_STAT_CLR_CR;                          /*0X1AC */\r
+    __IO     uint32_t    IOMUXCELL_CONFIG[57];                     /*0X1B0 */\r
+    __I      uint32_t    NVM_PROTECT_FACTORY;                      /*0X294 */\r
+    __I      uint32_t    DEVICE_STATUS_FIXED;                      /*0X298 */\r
+    __I      uint32_t    MBIST_ES0;                                /*0X29C */\r
+    __I      uint32_t    MBIST_ES1;                                /*0X2A0 */\r
+    __IO     uint32_t    MSDDR_PLL_STAUS_1;                        /*0X2A4 */\r
+    __I      uint32_t    REDUNDANCY_ESRAM0;                        /*0X2A8 */\r
+    __I      uint32_t    REDUNDANCY_ESRAM1;                        /*0X2AC */\r
+    __I      uint32_t    SERDESIF;                                 /*0X2B0 */\r
+\r
+} SYSREG_TypeDef;\r
+\r
+#define SYSREG_ENVM0_SOFTRESET_MASK         ( (uint32_t)0x01u << 0u )\r
+#define SYSREG_ENVM1_SOFTRESET_MASK         ( (uint32_t)0x01u << 1u )\r
+#define SYSREG_ESRAM0_SOFTRESET_MASK        ( (uint32_t)0x01u << 2u )\r
+#define SYSREG_ESRAM1_SOFTRESET_MASK        ( (uint32_t)0x01u << 3u )\r
+#define SYSREG_MAC_SOFTRESET_MASK           ( (uint32_t)0x01u << 4u )\r
+#define SYSREG_PDMA_SOFTRESET_MASK          ( (uint32_t)0x01u << 5u )\r
+#define SYSREG_TIMER_SOFTRESET_MASK         ( (uint32_t)0x01u << 6u )\r
+#define SYSREG_MMUART0_SOFTRESET_MASK       ( (uint32_t)0x01u << 7u )\r
+#define SYSREG_MMUART1_SOFTRESET_MASK       ( (uint32_t)0x01u << 8u )\r
+#define SYSREG_SPI0_SOFTRESET_MASK          ( (uint32_t)0x01u << 9u )\r
+#define SYSREG_SPI1_SOFTRESET_MASK          ( (uint32_t)0x01u << 10u )\r
+#define SYSREG_I2C0_SOFTRESET_MASK          ( (uint32_t)0x01u << 11u )\r
+#define SYSREG_I2C1_SOFTRESET_MASK          ( (uint32_t)0x01u << 12u )\r
+#define SYSREG_CAN_SOFTRESET_MASK           ( (uint32_t)0x01u << 13u )\r
+#define SYSREG_USB_SOFTRESET_MASK           ( (uint32_t)0x01u << 14u )\r
+#define SYSREG_COMBLK_SOFTRESET_MASK        ( (uint32_t)0x01u << 15u )\r
+#define SYSREG_FPGA_SOFTRESET_MASK          ( (uint32_t)0x01u << 16u )\r
+#define SYSREG_HPDMA_SOFTRESET_MASK         ( (uint32_t)0x01u << 17u )\r
+#define SYSREG_FIC32_0_SOFTRESET_MASK       ( (uint32_t)0x01u << 18u )\r
+#define SYSREG_FIC32_1_SOFTRESET_MASK       ( (uint32_t)0x01u << 19u )\r
+#define SYSREG_GPIO_SOFTRESET_MASK          ( (uint32_t)0x01u << 20u )\r
+#define SYSREG_GPIO_7_0_SOFTRESET_MASK      ( (uint32_t)0x01u << 21u )\r
+#define SYSREG_GPIO_15_8_SOFTRESET_MASK     ( (uint32_t)0x01u << 22u )\r
+#define SYSREG_GPIO_23_16_SOFTRESET_MASK    ( (uint32_t)0x01u << 23u )\r
+#define SYSREG_GPIO_31_24_SOFTRESET_MASK    ( (uint32_t)0x01u << 24u )\r
+#define SYSREG_MDDR_SOFTRESET_MASK          ( (uint32_t)0x01u << 25u )\r
+#define SYSREG_FIC64_SOFTRESET_MASK         ( (uint32_t)0x01u << 26u )\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/*-------------------------- CoreSF2Config Registers -------------------------*/\r
+/*----------------------------------------------------------------------------*/\r
+typedef struct {\r
+    __IO     uint32_t   CONFIG_DONE;\r
+    __I      uint32_t   INIT_DONE;\r
+    __IO     uint32_t   CLR_INIT_DONE;\r
+} CoreSF2Config_TypeDef;\r
+\r
+/******************************************************************************/\r
+/*                         Peripheral memory map                              */\r
+/******************************************************************************/\r
+#define UART0_BASE              0x40000000u\r
+#define SPI0_BASE               0x40001000u\r
+#define I2C0_BASE               0x40002000u\r
+#define PDMA_BASE               0x40003000u\r
+#define TIMER_BASE              0x40004000u\r
+#define WATCHDOG_BASE           0x40005000u\r
+#define H2F_IRQ_CTRL_BASE       0x40006000u\r
+#define UART1_BASE              0x40010000u\r
+#define SPI1_BASE               0x40011000u\r
+#define I2C1_BASE               0x40012000u\r
+#define GPIO_BASE               0x40013000u\r
+#define HPDMA_BASE              0x40014000u\r
+#define CAN_BASE                0x40015000u\r
+#define COMBLK_BASE             0x40016000u\r
+#define RTC_BASE                0x40017000u\r
+#define DDR0_CFG_BASE           0x40020800u\r
+#define DDR1_CFG_BASE           0x40021000u\r
+#define CORE_SF2_CFG_BASE       0x40022000u\r
+#define SERDES0_CFG_BASE        0x40028000u\r
+#define SERDES1_CFG_BASE        0x4002C000u\r
+#define SYSREG_BASE             0x40038000u\r
+#define ETHERNET_BASE           0x40041000u\r
+#define USB_BASE                0x40043000u\r
+#define ENVM1_BASE              0x60080000u\r
+#define ENVM2_BASE              0x600C0000u\r
+\r
+/******************************************************************************/\r
+/* bitband address calculation macro                             */\r
+/******************************************************************************/\r
+#define BITBAND_ADDRESS(X)  ((X & 0xF0000000U) + 0x02000000U + ((X & 0xFFFFFU) << 5))\r
+\r
+/******************************************************************************/\r
+/*                         Peripheral declaration                             */\r
+/******************************************************************************/\r
+#define UART0                   ((UART_TypeDef *) UART0_BASE)\r
+#define SPI0                    ((SPI_TypeDef *) SPI0_BASE)\r
+#define I2C0                    ((I2C_TypeDef *) I2C0_BASE)\r
+#define I2C0_BITBAND            ((I2C_BitBand_TypeDef *) BITBAND_ADDRESS(I2C0_BASE))\r
+#define MAC                     ((MAC_TypeDef *) ETHERNET_BASE)\r
+#define PDMA                    ((PDMA_TypeDef *) PDMA_BASE)\r
+#define TIMER                   ((TIMER_TypeDef *) TIMER_BASE)\r
+#define TIMER_BITBAND           ((TIMER_BitBand_TypeDef *) BITBAND_ADDRESS(TIMER_BASE))\r
+#define WATCHDOG                ((WATCHDOG_TypeDef *) WATCHDOG_BASE)\r
+#define INTERRUPT_CTRL          ((INTERRUPT_CTRL_TypeDef *) H2F_IRQ_CTRL_BASE)\r
+#define INTERRUPT_CTRL_BITBAND  ((INTERRUPT_CTRL_BitBand_TypeDef *) BITBAND_ADDRESS(H2F_IRQ_CTRL_BASE))\r
+#define UART1                   ((UART_TypeDef *) UART1_BASE)\r
+#define SPI1                    ((SPI_TypeDef *) SPI1_BASE)\r
+#define I2C1                    ((I2C_TypeDef *) I2C1_BASE)\r
+#define I2C1_BITBAND            ((I2C_BitBand_TypeDef *) BITBAND_ADDRESS(I2C1_BASE))\r
+#define GPIO                    ((GPIO_TypeDef *) GPIO_BASE)\r
+#define GPIO_BITBAND            ((GPIO_BitBand_TypeDef *) BITBAND_ADDRESS(GPIO_BASE))\r
+#define HPDMA                   ((HPDMA_TypeDef *) HPDMA_BASE)\r
+#define HPDMA_BITBAND           ((HPDMA_BitBand_TypeDef *) BITBAND_ADDRESS(HPDMA_BASE))\r
+#define COMBLK                  ((COMBLK_TypeDef *) COMBLK_BASE)\r
+#define RTC                     ((RTC_TypeDef *) RTC_BASE)\r
+#define ENVM_1                  ((NVM_TypeDef *) ENVM1_BASE)\r
+#define ENVM_2                  ((NVM_TypeDef *) ENVM2_BASE)\r
+#define SYSREG                  ((SYSREG_TypeDef *) SYSREG_BASE)\r
+#define MDDR                    ((MDDR_TypeDef *) DDR0_CFG_BASE)\r
+#define FDDR                    ((FDDR_TypeDef *) DDR1_CFG_BASE) \r
+#define USB                     ((MSS_USB_TypeDef *) USB_BASE)\r
+#define SERDES0                 ((SERDESIF_TypeDef *) SERDES0_CFG_BASE)\r
+#define SERDES1                 ((SERDESIF_TypeDef *) SERDES1_CFG_BASE)\r
+#define CORE_SF2_CFG            ((CoreSF2Config_TypeDef *) CORE_SF2_CFG_BASE)\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif  /* __SMARTFUSION2_CMSIS_PAL_H__ */\r
+\r
diff --git a/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/CMSIS/mss_assert.h b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/CMSIS/mss_assert.h
new file mode 100644 (file)
index 0000000..656915f
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/CMSIS/mss_assert.h
@@ -0,0 +1,61 @@
+/*******************************************************************************\r
+ * (c) Copyright 2009-2013 Microsemi SoC Products Group. All rights reserved.\r
+ * \r
+ * Assertion implementation.\r
+ *\r
+ * This file provides the implementation of the ASSERT macro. This file can be\r
+ * modified to cater for project specific requirements regarding the way\r
+ * assertions are handled.\r
+ *\r
+ * SVN $Revision: 5279 $\r
+ * SVN $Date: 2013-03-22 20:48:38 +0000 (Fri, 22 Mar 2013) $\r
+ */\r
+#ifndef __MSS_ASSERT_H_\r
+#define __MSS_ASSERT_H_\r
+\r
+#include <assert.h>\r
+\r
+#if defined ( __GNUC__   )\r
+\r
+#if defined(NDEBUG)\r
+\r
+#define ASSERT(CHECK)\r
+\r
+#else   /* NDEBUG */\r
+/*\r
+ * SoftConsole assertion handling\r
+ */\r
+#define ASSERT(CHECK)  \\r
+    do { \\r
+        if (!(CHECK)) \\r
+        { \\r
+            __asm volatile ("BKPT\n\t"); \\r
+        } \\r
+    } while (0);\r
+    \r
+#endif  /* NDEBUG */\r
+\r
+#elif defined ( __ICCARM__ )\r
+/*\r
+ * IAR Embedded Workbench assertion handling.\r
+ * Call C library assert function which should result in error message\r
+ * displayed in debugger.\r
+ */\r
+#define ASSERT(X)   assert(X)\r
+\r
+#else\r
+/*\r
+ * Keil assertion handling.\r
+ * Call C library assert function which should result in error message\r
+ * displayed in debugger.\r
+ */\r
+\r
+#ifndef __MICROLIB\r
+  #define ASSERT(X)   assert(X)\r
+#else\r
+  #define ASSERT(X)\r
+#endif\r
+\r
+#endif\r
+\r
+#endif  /* __MSS_ASSERT_H_ */\r
diff --git a/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/CMSIS/startup_gcc/debug-in-external-ram.ld b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/CMSIS/startup_gcc/debug-in-external-ram.ld
new file mode 100644 (file)
index 0000000..95aca23
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/CMSIS/startup_gcc/debug-in-external-ram.ld
@@ -0,0 +1,186 @@
+/*******************************************************************************
+ * (c) Copyright 2012-2013 Microsemi SoC Products Group.  All rights reserved.
+ * 
+ * SmartFusion2 Cortex-M3 linker script for creating a SoftConsole downloadable
+ * debug image executing in SmartFusion2 development board external RAM.
+ *
+ * SVN $Revision: 5269 $
+ * SVN $Date: 2013-03-21 20:53:38 +0000 (Thu, 21 Mar 2013) $
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-bigarm",
+             "elf32-littlearm")
+GROUP(-lc -lgcc -lm)
+OUTPUT_ARCH(arm)
+ENTRY(Reset_Handler)
+SEARCH_DIR(.)
+__DYNAMIC  =  0;
+
+/*******************************************************************************
+ * Start of board customization.
+ *******************************************************************************/
+MEMORY
+{
+  /* SmartFusion2 internal eSRAM */
+  esram (rwx) : ORIGIN = 0x20000000, LENGTH = 64k
+  
+  /* SmartFusion2 development board external RAM */
+  external_ram (rwx) : ORIGIN = 0x70000000, LENGTH = 2M
+}
+
+RAM_START_ADDRESS = 0x70000000;        /* Must be the same value MEMORY region ram ORIGIN above. */
+RAM_SIZE = 64k;                                        /* Must be the same value MEMORY region ram LENGTH above. */
+MAIN_STACK_SIZE = 8k;                  /* Cortex main stack size. */
+PROCESS_STACK_SIZE     = 4k;           /* Cortex process stack size (only available with OS extensions).*/
+
+/*******************************************************************************
+ * End of board customization.
+ *******************************************************************************/
+ 
+PROVIDE (__main_stack_start = RAM_START_ADDRESS + RAM_SIZE);
+PROVIDE (__process_stack_start = __main_stack_start - MAIN_STACK_SIZE);
+PROVIDE (_estack = __main_stack_start);
+PROVIDE (__mirrored_nvm = 0);   /* Indicate to startup code that NVM is not mirrored to VMA address .text copy is required. */
+
+SECTIONS
+{
+  .init :
+  {
+    __vector_table_vma_base_address = .;
+    *(.isr_vector)
+    . = ALIGN(0x4);
+  } >esram
+  
+  .text :
+  {
+    CREATE_OBJECT_SYMBOLS
+    __text_load = LOADADDR(.text);
+    __text_start = .;
+    *(.text .text.* .gnu.linkonce.t.*)
+    *(.plt)
+    *(.gnu.warning)
+    *(.glue_7t) *(.glue_7) *(.vfp11_veneer)
+
+    . = ALIGN(0x4);
+    /* These are for running static constructors and destructors under ELF.  */
+    KEEP (*crtbegin.o(.ctors))
+    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*crtend.o(.ctors))
+    KEEP (*crtbegin.o(.dtors))
+    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*crtend.o(.dtors))
+
+    *(.rodata .rodata.* .gnu.linkonce.r.*)
+
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    *(.gcc_except_table) 
+    *(.eh_frame_hdr)
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(.fini_array))
+    KEEP (*(SORT(.fini_array.*)))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >external_ram
+  /* .ARM.exidx is sorted, so has to go in its own output section.  */
+   __exidx_start = .;
+  .ARM.exidx :
+  {
+    *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+  } >external_ram
+  __exidx_end = .;
+  _etext = .;
+  PROVIDE(__text_end = .);
+
+  .data :
+  {
+    __data_load = LOADADDR (.data);
+    _sidata = LOADADDR (.data);
+    __data_start = .;
+    _sdata = .;
+    KEEP(*(.jcr))
+    *(.got.plt) *(.got)
+    *(.shdata)
+    *(.data .data.* .gnu.linkonce.d.*)
+    . = ALIGN (4);
+    _edata = .;
+  } >external_ram 
+
+  .bss :
+  {
+    __bss_start__ = . ;
+    _sbss = .;
+    *(.shbss)
+    *(.bss .bss.* .gnu.linkonce.b.*)
+    *(COMMON)
+    . = ALIGN (8);
+    __bss_end__ = .;
+    _end = .;
+    __end = _end;
+    _ebss = .;
+    PROVIDE(end = .);
+  } >external_ram 
+
+  /* 
+   * The .stack section is only specified here in order for the linker to generate
+   * an error if the esram is full.
+   */
+  .stack :
+  {
+       . = ALIGN(4);
+    . += PROCESS_STACK_SIZE;
+    . = ALIGN(4);
+    . += MAIN_STACK_SIZE;
+    . = ALIGN(4);
+  } >external_ram
+  
+  .stab 0 (NOLOAD) :
+  {
+    *(.stab)
+  }
+
+  .stabstr 0 (NOLOAD) :
+  {
+    *(.stabstr)
+  }
+  /* DWARF debug sections.
+     Symbols in the DWARF debugging sections are relative to the beginning
+     of the section so we begin them at 0.  */
+  /* DWARF 1 */
+  .debug          0 : { *(.debug) }
+  .line           0 : { *(.line) }
+  /* GNU DWARF 1 extensions */
+  .debug_srcinfo  0 : { *(.debug_srcinfo) }
+  .debug_sfnames  0 : { *(.debug_sfnames) }
+  /* DWARF 1.1 and DWARF 2 */
+  .debug_aranges  0 : { *(.debug_aranges) }
+  .debug_pubnames 0 : { *(.debug_pubnames) }
+  /* DWARF 2 */
+  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+  .debug_abbrev   0 : { *(.debug_abbrev) }
+  .debug_line     0 : { *(.debug_line) }
+  .debug_frame    0 : { *(.debug_frame) }
+  .debug_str      0 : { *(.debug_str) }
+  .debug_loc      0 : { *(.debug_loc) }
+  .debug_macinfo  0 : { *(.debug_macinfo) }
+  /* SGI/MIPS DWARF 2 extensions */
+  .debug_weaknames 0 : { *(.debug_weaknames) }
+  .debug_funcnames 0 : { *(.debug_funcnames) }
+  .debug_typenames 0 : { *(.debug_typenames) }
+  .debug_varnames  0 : { *(.debug_varnames) }
+  .note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }
+  .ARM.attributes 0 : { KEEP (*(.ARM.attributes)) }
+  /DISCARD/ : { *(.note.GNU-stack) *(.isr_vector) }
+}
diff --git a/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/CMSIS/startup_gcc/debug-in-microsemi-smartfusion2-envm.ld b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/CMSIS/startup_gcc/debug-in-microsemi-smartfusion2-envm.ld
new file mode 100644 (file)
index 0000000..59daa18
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/CMSIS/startup_gcc/debug-in-microsemi-smartfusion2-envm.ld
@@ -0,0 +1,184 @@
+/*******************************************************************************
+ * (c) Copyright 2012-2013 Microsemi SoC Products Group.  All rights reserved.
+ * 
+ * SmartFusion2 Cortex-M3 linker script for creating a SoftConsole downloadable
+ * debug image executing in SmartFusion2 internal eNVM.
+ *
+ * SVN $Revision: 5269 $
+ * SVN $Date: 2013-03-21 20:53:38 +0000 (Thu, 21 Mar 2013) $
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-bigarm",
+             "elf32-littlearm")
+GROUP(-lc -lgcc -lm)
+OUTPUT_ARCH(arm)
+ENTRY(Reset_Handler)
+SEARCH_DIR(.)
+__DYNAMIC  =  0;
+
+/*******************************************************************************
+ * Start of board customization.
+ *******************************************************************************/
+MEMORY
+{
+  /*
+   * WARNING: The words "SOFTCONSOLE", "FLASH", and "USE", the colon ":", and
+   *          the name of the type of flash memory are all in a specific order.
+   *          Please do not modify that comment line, in order to ensure
+   *          debugging of your application will use the flash memory correctly.
+   */
+
+  /* SOFTCONSOLE FLASH USE: microsemi-smartfusion2-envm */
+  rom (rx)  : ORIGIN = 0x60000000, LENGTH = 256k
+  
+  /* SmartFusion2 internal eNVM mirrored to 0x00000000 */
+  romMirror (rx) : ORIGIN = 0x00000000, LENGTH = 256k
+
+  /* SmartFusion2 internal eSRAM */
+  ram (rwx) : ORIGIN = 0x20000000, LENGTH = 64k
+}
+
+RAM_START_ADDRESS = 0x20000000;        /* Must be the same value MEMORY region ram ORIGIN above. */
+RAM_SIZE = 64k;                                        /* Must be the same value MEMORY region ram LENGTH above. */
+MAIN_STACK_SIZE = 8k;                          /* Cortex main stack size. */
+PROCESS_STACK_SIZE     = 4k;                   /* Cortex process stack size (only available with OS extensions).*/
+
+/*******************************************************************************
+ * End of board customization.
+ *******************************************************************************/
+ 
+PROVIDE (__main_stack_start = RAM_START_ADDRESS + RAM_SIZE);
+PROVIDE (__process_stack_start = __main_stack_start - MAIN_STACK_SIZE);
+PROVIDE (_estack = __main_stack_start);
+PROVIDE (__mirrored_nvm = 1);   /* Indicate to startup code that NVM is mirrored to VMA address and no text copy is required. */
+
+SECTIONS
+{
+  .init :
+  {
+    __vector_table_vma_base_address = .;
+    *(.isr_vector)
+    . = ALIGN(0x4);
+  } >romMirror AT>rom
+  
+  .text :
+  {
+    CREATE_OBJECT_SYMBOLS
+    __text_load = LOADADDR(.text);
+    __text_start = .;
+    
+    *(.text .text.* .gnu.linkonce.t.*)
+    *(.plt)
+    *(.gnu.warning)
+    *(.glue_7t) *(.glue_7) *(.vfp11_veneer)
+
+    . = ALIGN(0x4);
+    /* These are for running static constructors and destructors under ELF.  */
+    KEEP (*crtbegin.o(.ctors))
+    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*crtend.o(.ctors))
+    KEEP (*crtbegin.o(.dtors))
+    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*crtend.o(.dtors))
+
+    *(.rodata .rodata.* .gnu.linkonce.r.*)
+
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    *(.gcc_except_table) 
+    *(.eh_frame_hdr)
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(.fini_array))
+    KEEP (*(SORT(.fini_array.*)))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >romMirror AT>rom
+
+  /* .ARM.exidx is sorted, so has to go in its own output section.  */
+   __exidx_start = .;
+  .ARM.exidx :
+  {
+    *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+  } >ram AT>rom
+  __exidx_end = .;
+  _etext = .;
+
+  .data :
+  {
+    __data_load = LOADADDR(.data);
+    _sidata = LOADADDR (.data);
+    __data_start = .;
+    _sdata = .;
+    KEEP(*(.jcr))
+    *(.got.plt) *(.got)
+    *(.shdata)
+    *(.data .data.* .gnu.linkonce.d.*)
+    . = ALIGN (4);
+       _edata = .;
+  } >ram AT>rom
+
+  .bss :
+  {
+    __bss_start__ = . ;
+    _sbss = .;
+    *(.shbss)
+    *(.bss .bss.* .gnu.linkonce.b.*)
+    *(COMMON)
+    . = ALIGN (8);
+    __bss_end__ = .;
+    _end = .;
+    __end = _end;
+    _ebss = .;
+    PROVIDE(end = .);
+  } >ram AT>rom
+
+  .stab 0 (NOLOAD) :
+  {
+    *(.stab)
+  }
+
+  .stabstr 0 (NOLOAD) :
+  {
+    *(.stabstr)
+  }
+  /* DWARF debug sections.
+     Symbols in the DWARF debugging sections are relative to the beginning
+     of the section so we begin them at 0.  */
+  /* DWARF 1 */
+  .debug          0 : { *(.debug) }
+  .line           0 : { *(.line) }
+  /* GNU DWARF 1 extensions */
+  .debug_srcinfo  0 : { *(.debug_srcinfo) }
+  .debug_sfnames  0 : { *(.debug_sfnames) }
+  /* DWARF 1.1 and DWARF 2 */
+  .debug_aranges  0 : { *(.debug_aranges) }
+  .debug_pubnames 0 : { *(.debug_pubnames) }
+  /* DWARF 2 */
+  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+  .debug_abbrev   0 : { *(.debug_abbrev) }
+  .debug_line     0 : { *(.debug_line) }
+  .debug_frame    0 : { *(.debug_frame) }
+  .debug_str      0 : { *(.debug_str) }
+  .debug_loc      0 : { *(.debug_loc) }
+  .debug_macinfo  0 : { *(.debug_macinfo) }
+  /* SGI/MIPS DWARF 2 extensions */
+  .debug_weaknames 0 : { *(.debug_weaknames) }
+  .debug_funcnames 0 : { *(.debug_funcnames) }
+  .debug_typenames 0 : { *(.debug_typenames) }
+  .debug_varnames  0 : { *(.debug_varnames) }
+  .note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }
+  .ARM.attributes 0 : { KEEP (*(.ARM.attributes)) }
+  /DISCARD/ : { *(.note.GNU-stack)  }
+}
diff --git a/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/CMSIS/startup_gcc/debug-in-microsemi-smartfusion2-esram.ld b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/CMSIS/startup_gcc/debug-in-microsemi-smartfusion2-esram.ld
new file mode 100644 (file)
index 0000000..79c3952
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/CMSIS/startup_gcc/debug-in-microsemi-smartfusion2-esram.ld
@@ -0,0 +1,178 @@
+/*******************************************************************************
+ * (c) Copyright 2012-2013 Microsemi SoC Products Group.  All rights reserved.
+ *
+ * SmartFusion2 Cortex-M3 linker script for creating a SoftConsole downloadable
+ * debug image executing in SmartFusion2 internal eSRAM.
+ *
+ * SVN $Revision: 5269 $
+ * SVN $Date: 2013-03-21 20:53:38 +0000 (Thu, 21 Mar 2013) $
+ */
+
+ OUTPUT_FORMAT("elf32-littlearm", "elf32-bigarm",
+             "elf32-littlearm")
+GROUP(-lc -lgcc -lm)
+OUTPUT_ARCH(arm)
+ENTRY(Reset_Handler)
+SEARCH_DIR(.)
+__DYNAMIC  =  0;
+
+/*******************************************************************************
+ * Start of board customization.
+ *******************************************************************************/
+MEMORY
+{
+  /* SmartFusion2 internal eSRAM */
+  ram (rwx) : ORIGIN = 0x20000000, LENGTH = 64k
+}
+
+RAM_START_ADDRESS = 0x20000000;        /* Must be the same value MEMORY region ram ORIGIN above. */
+RAM_SIZE = 64k;                                        /* Must be the same value MEMORY region ram LENGTH above. */
+MAIN_STACK_SIZE = 1k;                  /* Cortex main stack size. */
+PROCESS_STACK_SIZE     = 0k;           /* Cortex process stack size (only available with OS extensions).*/
+
+/*******************************************************************************
+ * End of board customization.
+ *******************************************************************************/
+
+PROVIDE (__main_stack_start = RAM_START_ADDRESS + RAM_SIZE);
+PROVIDE (__process_stack_start = __main_stack_start - MAIN_STACK_SIZE);
+PROVIDE (_estack = __main_stack_start);
+PROVIDE (__mirrored_nvm = 0);   /* Indicate to startup code that NVM is not mirrored to VMA address .text copy is required. */
+
+SECTIONS
+{
+  .text :
+  {
+    CREATE_OBJECT_SYMBOLS
+    __text_load = LOADADDR(.text);
+    __text_start = .;
+    __vector_table_vma_base_address = .;
+    *(.isr_vector)
+    *(.text .text.* .gnu.linkonce.t.*)
+    *(.plt)
+    *(.gnu.warning)
+    *(.glue_7t) *(.glue_7) *(.vfp11_veneer)
+
+    . = ALIGN(0x4);
+    /* These are for running static constructors and destructors under ELF.  */
+    KEEP (*crtbegin.o(.ctors))
+    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*crtend.o(.ctors))
+    KEEP (*crtbegin.o(.dtors))
+    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*crtend.o(.dtors))
+
+    *(.rodata .rodata.* .gnu.linkonce.r.*)
+
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    *(.gcc_except_table)
+    *(.eh_frame_hdr)
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(.fini_array))
+    KEEP (*(SORT(.fini_array.*)))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >ram
+  /* .ARM.exidx is sorted, so has to go in its own output section.  */
+   __exidx_start = .;
+  .ARM.exidx :
+  {
+    *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+  } >ram
+  __exidx_end = .;
+  _etext = .;
+  PROVIDE(__text_end = .);
+
+  .data :
+  {
+    __data_load = LOADADDR (.data);
+    _sidata = LOADADDR (.data);
+    __data_start = .;
+    _sdata = .;
+    KEEP(*(.jcr))
+    *(.got.plt) *(.got)
+    *(.shdata)
+    *(.data .data.* .gnu.linkonce.d.*)
+    . = ALIGN (4);
+    _edata = .;
+  } >ram
+
+  .bss :
+  {
+    __bss_start__ = . ;
+    _sbss = .;
+    *(.shbss)
+    *(.bss .bss.* .gnu.linkonce.b.*)
+    *(COMMON)
+    . = ALIGN (8);
+    __bss_end__ = .;
+    _end = .;
+    __end = _end;
+    _ebss = .;
+    PROVIDE(end = .);
+  } >ram
+
+  /*
+   * The .stack section is only specified here in order for the linker to generate
+   * an error if the ram is full.
+   */
+  .stack :
+  {
+       . = ALIGN(4);
+    . += PROCESS_STACK_SIZE;
+    . = ALIGN(4);
+    . += MAIN_STACK_SIZE;
+    . = ALIGN(4);
+  } >ram
+
+  .stab 0 (NOLOAD) :
+  {
+    *(.stab)
+  }
+
+  .stabstr 0 (NOLOAD) :
+  {
+    *(.stabstr)
+  }
+  /* DWARF debug sections.
+     Symbols in the DWARF debugging sections are relative to the beginning
+     of the section so we begin them at 0.  */
+  /* DWARF 1 */
+  .debug          0 : { *(.debug) }
+  .line           0 : { *(.line) }
+  /* GNU DWARF 1 extensions */
+  .debug_srcinfo  0 : { *(.debug_srcinfo) }
+  .debug_sfnames  0 : { *(.debug_sfnames) }
+  /* DWARF 1.1 and DWARF 2 */
+  .debug_aranges  0 : { *(.debug_aranges) }
+  .debug_pubnames 0 : { *(.debug_pubnames) }
+  /* DWARF 2 */
+  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+  .debug_abbrev   0 : { *(.debug_abbrev) }
+  .debug_line     0 : { *(.debug_line) }
+  .debug_frame    0 : { *(.debug_frame) }
+  .debug_str      0 : { *(.debug_str) }
+  .debug_loc      0 : { *(.debug_loc) }
+  .debug_macinfo  0 : { *(.debug_macinfo) }
+  /* SGI/MIPS DWARF 2 extensions */
+  .debug_weaknames 0 : { *(.debug_weaknames) }
+  .debug_funcnames 0 : { *(.debug_funcnames) }
+  .debug_typenames 0 : { *(.debug_typenames) }
+  .debug_varnames  0 : { *(.debug_varnames) }
+  .note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }
+  .ARM.attributes 0 : { KEEP (*(.ARM.attributes)) }
+  /DISCARD/ : { *(.note.GNU-stack) *(.isr_vector) }
+}
diff --git a/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/CMSIS/startup_gcc/newlib_stubs.c b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/CMSIS/startup_gcc/newlib_stubs.c
new file mode 100644 (file)
index 0000000..c6d794d
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/CMSIS/startup_gcc/newlib_stubs.c
@@ -0,0 +1,273 @@
+/*******************************************************************************\r
+ * (c) Copyright 2009-2013 Microsemi SoC Products Group.  All rights reserved.\r
+ * \r
+ * Stubs for Newlib system calls.\r
+ *  \r
+ * SVN $Revision: 5269 $\r
+ * SVN $Date: 2013-03-21 20:53:38 +0000 (Thu, 21 Mar 2013) $\r
+ */\r
+#include <stdlib.h>\r
+#include <sys/unistd.h>\r
+#include <sys/stat.h>\r
+#include <sys/times.h>\r
+#include <errno.h>\r
+\r
+/*==============================================================================\r
+ * Redirection of standard output to a SmartFusion2 MSS UART.\r
+ *------------------------------------------------------------------------------\r
+ * A default implementation for the redirection of the output of printf() to a\r
+ * UART is provided at the bottom of this file. This redirection is enabled by\r
+ * adding the symbol/define MICROSEMI_STDIO_THRU_MMUART0 or\r
+ * MICROSEMI_STDIO_THRU_MMUART0 to your project settings and specifying the baud\r
+ * rate using the MICROSEMI_STDIO_BAUD_RATE define.\r
+ */\r
+#ifdef MICROSEMI_STDIO_THRU_MMUART0\r
+#ifndef MICROSEMI_STDIO_THRU_UART\r
+#define MICROSEMI_STDIO_THRU_UART\r
+#endif\r
+#endif  /* MICROSEMI_STDIO_THRU_MMUART0 */\r
+\r
+#ifdef MICROSEMI_STDIO_THRU_MMUART1\r
+#ifndef MICROSEMI_STDIO_THRU_UART\r
+#define MICROSEMI_STDIO_THRU_UART\r
+#endif\r
+#endif  /* MICROSEMI_STDIO_THRU_MMUART1 */\r
+\r
+/*\r
+ * Select which MMUART will be used for stdio and what baud rate will be used.\r
+ * Default to 57600 baud if no baud rate is specified using the\r
+ * MICROSEMI_STDIO_BAUD_RATE #define.\r
+ */ \r
+#ifdef MICROSEMI_STDIO_THRU_UART\r
+#include "../../drivers/mss_uart/mss_uart.h"\r
+\r
+#ifndef MICROSEMI_STDIO_BAUD_RATE\r
+#define MICROSEMI_STDIO_BAUD_RATE  MSS_UART_57600_BAUD\r
+#endif\r
+\r
+#ifdef MICROSEMI_STDIO_THRU_MMUART0\r
+static mss_uart_instance_t * const gp_my_uart = &g_mss_uart0;\r
+#else\r
+static mss_uart_instance_t * const gp_my_uart = &g_mss_uart1;\r
+#endif\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Global flag used to indicate if the UART driver needs to be initialized.\r
+ */\r
+static int g_stdio_uart_init_done = 0;\r
+\r
+#endif /* MICROSEMI_STDIO_THRU_UART */\r
+\r
+/*==============================================================================\r
+ * Environment variables.\r
+ * A pointer to a list of environment variables and their values. For a minimal\r
+ * environment, this empty list is adequate:\r
+ */\r
+char *__env[1] = { 0 };\r
+char **environ = __env;\r
+\r
+/*==============================================================================\r
+ * Close a file.\r
+ */\r
+int _close(int file)\r
+{\r
+    return -1;\r
+}\r
+\r
+/*==============================================================================\r
+ * Transfer control to a new process.\r
+ */\r
+int _execve(char *name, char **argv, char **env)\r
+{\r
+    errno = ENOMEM;\r
+    return -1;\r
+}\r
+\r
+/*==============================================================================\r
+ * Exit a program without cleaning up files.\r
+ */\r
+void _exit( int code )\r
+{\r
+    /* Should we force a system reset? */\r
+    while( 1 )\r
+    {\r
+        ;\r
+    }\r
+}\r
+\r
+/*==============================================================================\r
+ * Create a new process.\r
+ */\r
+int _fork(void)\r
+{\r
+    errno = EAGAIN;\r
+    return -1;\r
+}\r
+\r
+/*==============================================================================\r
+ * Status of an open file.\r
+ */\r
+int _fstat(int file, struct stat *st)\r
+{\r
+    st->st_mode = S_IFCHR;\r
+    return 0;\r
+}\r
+\r
+/*==============================================================================\r
+ * Process-ID\r
+ */\r
+int _getpid(void)\r
+{\r
+    return 1;\r
+}\r
+\r
+/*==============================================================================\r
+ * Query whether output stream is a terminal.\r
+ */\r
+int _isatty(int file)\r
+{\r
+    return 1;\r
+}\r
+\r
+/*==============================================================================\r
+ * Send a signal.\r
+ */\r
+int _kill(int pid, int sig)\r
+{\r
+    errno = EINVAL;\r
+    return -1;\r
+}\r
+\r
+/*==============================================================================\r
+ * Establish a new name for an existing file.\r
+ */\r
+int _link(char *old, char *new)\r
+{\r
+    errno = EMLINK;\r
+    return -1;\r
+}\r
+\r
+/*==============================================================================\r
+ * Set position in a file.\r
+ */\r
+int _lseek(int file, int ptr, int dir)\r
+{\r
+    return 0;\r
+}\r
+\r
+/*==============================================================================\r
+ * Open a file.\r
+ */\r
+int _open(const char *name, int flags, int mode)\r
+{\r
+    return -1;\r
+}\r
+\r
+/*==============================================================================\r
+ * Read from a file.\r
+ */\r
+int _read(int file, char *ptr, int len)\r
+{\r
+    return 0;\r
+}\r
+\r
+/*==============================================================================\r
+ * Write to a file. libc subroutines will use this system routine for output to\r
+ * all files, including stdout\97so if you need to generate any output, for\r
+ * example to a serial port for debugging, you should make your minimal write\r
+ * capable of doing this.\r
+ */\r
+int _write_r( void * reent, int file, char * ptr, int len )\r
+{\r
+#ifdef MICROSEMI_STDIO_THRU_UART\r
+    /*--------------------------------------------------------------------------\r
+     * Initialize the UART driver if it is the first time this function is\r
+     * called.\r
+     */\r
+    if(!g_stdio_uart_init_done)\r
+    {\r
+        MSS_UART_init(gp_my_uart,\r
+                      MICROSEMI_STDIO_BAUD_RATE,\r
+                      MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY);\r
+                      \r
+        g_stdio_uart_init_done = 1;\r
+    }\r
+    \r
+    /*--------------------------------------------------------------------------\r
+     * Output text to the UART.\r
+     */\r
+    MSS_UART_polled_tx(gp_my_uart, (uint8_t *)ptr, len);\r
+    \r
+    return len;\r
+#else   /* MICROSEMI_STDIO_THRU_UART */\r
+    return 0;\r
+#endif  /* MICROSEMI_STDIO_THRU_UART */\r
+}\r
+\r
+/*==============================================================================\r
+ * Increase program data space. As malloc and related functions depend on this,\r
+ * it is useful to have a working implementation. The following suffices for a\r
+ * standalone system; it exploits the symbol _end automatically defined by the\r
+ * GNU linker. \r
+ */\r
+caddr_t _sbrk(int incr)\r
+{\r
+    extern char _end;        /* Defined by the linker */\r
+    static char *heap_end;\r
+    char *prev_heap_end;\r
+    char * stack_ptr;\r
+    \r
+    if (heap_end == 0)\r
+    {\r
+      heap_end = &_end;\r
+    }\r
+    \r
+    prev_heap_end = heap_end;\r
+    asm volatile ("MRS %0, msp" : "=r" (stack_ptr) );\r
+    if (heap_end + incr > stack_ptr)\r
+    {\r
+      _write_r ((void *)0, 1, "Heap and stack collision\n", 25);\r
+      _exit (1);\r
+    }\r
+  \r
+    heap_end += incr;\r
+    return (caddr_t) prev_heap_end;\r
+}\r
+\r
+/*==============================================================================\r
+ * Status of a file (by name).\r
+ */\r
+int _stat(char *file, struct stat *st)\r
+{\r
+    st->st_mode = S_IFCHR;\r
+    return 0;\r
+}\r
+\r
+/*==============================================================================\r
+ * Timing information for current process.\r
+ */\r
+int _times(struct tms *buf)\r
+{\r
+    return -1;\r
+}\r
+\r
+/*==============================================================================\r
+ * Remove a file's directory entry.\r
+ */\r
+int _unlink(char *name)\r
+{\r
+    errno = ENOENT;\r
+    return -1;\r
+}\r
+\r
+/*==============================================================================\r
+ * Wait for a child process.\r
+ */\r
+int _wait(int *status)\r
+{\r
+    errno = ECHILD;\r
+    return -1;\r
+}\r
+\r
+\r
+\r
diff --git a/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/CMSIS/startup_gcc/production-execute-in-place.ld b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/CMSIS/startup_gcc/production-execute-in-place.ld
new file mode 100644 (file)
index 0000000..9dca87a
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/CMSIS/startup_gcc/production-execute-in-place.ld
@@ -0,0 +1,172 @@
+/*******************************************************************************
+ * (c) Copyright 2009-2013 Microsemi SoC Products Group.  All rights reserved.
+ * 
+ * SmartFusion2 Cortex-M3 linker script creating an executable image for use in
+ * the Libero flow for executing code in place in internal eNVM.
+ *
+ * SVN $Revision: 5269 $
+ * SVN $Date: 2013-03-21 20:53:38 +0000 (Thu, 21 Mar 2013) $
+ */
+OUTPUT_FORMAT("elf32-littlearm", "elf32-bigarm",
+             "elf32-littlearm")
+GROUP(-lc -lgcc -lm)
+OUTPUT_ARCH(arm)
+ENTRY(Reset_Handler)
+SEARCH_DIR(.)
+__DYNAMIC  =  0;
+
+/*******************************************************************************
+ * Start of board customization.
+ *******************************************************************************/
+MEMORY
+{
+  /* SmartFusion2 internal eNVM */
+  rom (rx) : ORIGIN = 0, LENGTH = 256k
+  
+  /* SmartFusion2 internal eSRAM */
+  ram (rwx) : ORIGIN = 0x20000000, LENGTH = 64k
+}
+
+RAM_START_ADDRESS = 0x20000000;        /* Must be the same value as MEMORY region ram ORIGIN above. */
+RAM_SIZE = 64k;                                        /* Must be the same value as MEMORY region ram LENGTH above. */
+MAIN_STACK_SIZE = 8k;                  /* Cortex main stack size. */
+PROCESS_STACK_SIZE     = 4k;           /* Cortex process stack size (only available with OS extensions).*/
+
+/*******************************************************************************
+ * End of board customization.
+ *******************************************************************************/
+ 
+PROVIDE (__main_stack_start = RAM_START_ADDRESS + RAM_SIZE);
+PROVIDE (__process_stack_start = __main_stack_start - MAIN_STACK_SIZE);
+PROVIDE (_estack = __main_stack_start);
+PROVIDE (__mirrored_nvm = 0);   /* Indicate to startup code that NVM is not mirrored to VMA address .text copy is required. */
+
+SECTIONS
+{
+  .reset :
+  {
+    __vector_table_vma_base_address = .;
+    *(.isr_vector)
+    . = ALIGN(0x4);
+  } >rom
+  
+  .text :
+  {
+    CREATE_OBJECT_SYMBOLS
+    __text_load = LOADADDR(.text);
+    __text_start = .;
+    
+    *(.text .text.* .gnu.linkonce.t.*)
+    *(.plt)
+    *(.gnu.warning)
+    *(.glue_7t) *(.glue_7) *(.vfp11_veneer)
+
+    . = ALIGN(0x4);
+    /* These are for running static constructors and destructors under ELF.  */
+    KEEP (*crtbegin.o(.ctors))
+    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*crtend.o(.ctors))
+    KEEP (*crtbegin.o(.dtors))
+    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*crtend.o(.dtors))
+
+    *(.rodata .rodata.* .gnu.linkonce.r.*)
+
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    *(.gcc_except_table) 
+    *(.eh_frame_hdr)
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(.fini_array))
+    KEEP (*(SORT(.fini_array.*)))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >rom
+  /* .ARM.exidx is sorted, so has to go in its own output section.  */
+   __exidx_start = .;
+  .ARM.exidx :
+  {
+    *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+  } >rom
+  __exidx_end = .;
+  _etext = .;
+
+  .data :
+  {
+    __data_load = LOADADDR(.data);
+    _sidata = LOADADDR (.data);
+    __data_start = .;
+    _sdata = .;
+    KEEP(*(.jcr))
+    *(.got.plt) *(.got)
+    *(.shdata)
+    *(.data .data.* .gnu.linkonce.d.*)
+    . = ALIGN (4);
+       _edata = .;
+  } >ram AT>rom
+
+  .bss :
+  {
+    __bss_start__ = . ;
+    _sbss = .;
+    *(.shbss)
+    *(.bss .bss.* .gnu.linkonce.b.*)
+    *(COMMON)
+    . = ALIGN (8);
+    __bss_end__ = .;
+    _end = .;
+    __end = _end;
+    _ebss = .;
+    PROVIDE(end = .);
+  } >ram AT>rom
+
+  .stab 0 (NOLOAD) :
+  {
+    *(.stab)
+  }
+
+  .stabstr 0 (NOLOAD) :
+  {
+    *(.stabstr)
+  }
+  /* DWARF debug sections.
+     Symbols in the DWARF debugging sections are relative to the beginning
+     of the section so we begin them at 0.  */
+  /* DWARF 1 */
+  .debug          0 : { *(.debug) }
+  .line           0 : { *(.line) }
+  /* GNU DWARF 1 extensions */
+  .debug_srcinfo  0 : { *(.debug_srcinfo) }
+  .debug_sfnames  0 : { *(.debug_sfnames) }
+  /* DWARF 1.1 and DWARF 2 */
+  .debug_aranges  0 : { *(.debug_aranges) }
+  .debug_pubnames 0 : { *(.debug_pubnames) }
+  /* DWARF 2 */
+  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+  .debug_abbrev   0 : { *(.debug_abbrev) }
+  .debug_line     0 : { *(.debug_line) }
+  .debug_frame    0 : { *(.debug_frame) }
+  .debug_str      0 : { *(.debug_str) }
+  .debug_loc      0 : { *(.debug_loc) }
+  .debug_macinfo  0 : { *(.debug_macinfo) }
+  /* SGI/MIPS DWARF 2 extensions */
+  .debug_weaknames 0 : { *(.debug_weaknames) }
+  .debug_funcnames 0 : { *(.debug_funcnames) }
+  .debug_typenames 0 : { *(.debug_typenames) }
+  .debug_varnames  0 : { *(.debug_varnames) }
+  .note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }
+  .ARM.attributes 0 : { KEEP (*(.ARM.attributes)) }
+  /DISCARD/ : { *(.note.GNU-stack)  }
+}
diff --git a/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/CMSIS/startup_gcc/production-relocate-executable.ld b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/CMSIS/startup_gcc/production-relocate-executable.ld
new file mode 100644 (file)
index 0000000..89c42e3
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/CMSIS/startup_gcc/production-relocate-executable.ld
@@ -0,0 +1,178 @@
+/*******************************************************************************
+ * (c) Copyright 2009-2013 Microsemi SoC Products Group.  All rights reserved.
+ * 
+ * SmartFusion2 Cortex-M3 linker script creating an executable image for use in
+ * the Libero flow for relocating executable from internal eNVM to external RAM
+ * before starting execution.
+ *
+ * SVN $Revision: 5269 $
+ * SVN $Date: 2013-03-21 20:53:38 +0000 (Thu, 21 Mar 2013) $
+ */
+OUTPUT_FORMAT("elf32-littlearm", "elf32-bigarm",
+             "elf32-littlearm")
+GROUP(-lc -lgcc -lm)
+OUTPUT_ARCH(arm)
+ENTRY(Reset_Handler)
+SEARCH_DIR(.)
+__DYNAMIC  =  0;
+
+/*******************************************************************************
+ * Start of board customization.
+ *******************************************************************************/
+MEMORY
+{
+  /* SmartFusion2 internal eNVM */
+  rom (rx) : ORIGIN = 0, LENGTH = 256k
+  
+  /* SmartFusion2 internal eSRAM */
+  esram (rwx) : ORIGIN = 0x20000000, LENGTH = 64k
+  
+  /* SmartFusion2 development board external RAM */
+  external_ram (rwx) : ORIGIN = 0x70000000, LENGTH = 2M
+}
+
+RAM_START_ADDRESS = 0x20000000;        /* Must be the same value as MEMORY region esram ORIGIN above. */
+RAM_SIZE = 64k;                                        /* Must be the same value as MEMORY region esram LENGTH above. */
+MAIN_STACK_SIZE = 8k;                  /* Cortex main stack size. */
+PROCESS_STACK_SIZE     = 4k;           /* Cortex process stack size (only available with OS extensions).*/
+
+/*******************************************************************************
+ * End of board customization.
+ *******************************************************************************/
+ 
+PROVIDE (__main_stack_start = RAM_START_ADDRESS + RAM_SIZE);
+PROVIDE (__process_stack_start = __main_stack_start - MAIN_STACK_SIZE);
+PROVIDE (_estack = __main_stack_start);
+PROVIDE (__mirrored_nvm = 0);   /* Indicate to startup code that NVM is not mirrored to VMA address .text copy is required. */
+
+SECTIONS
+{
+  .reset :
+  {
+    __vector_table_vma_base_address = .;
+    *(.isr_vector)
+    /* SystemInit() is called before relocation to RAM so keep in ROM */
+       *system_m2sxxx.o(.text*)    
+    . = ALIGN(0x4);
+  } >rom
+  
+  .text :
+  {
+    CREATE_OBJECT_SYMBOLS
+    __text_load = LOADADDR(.text);
+    __text_start = .;
+    
+    *(.text .text.* .gnu.linkonce.t.*)
+    *(.plt)
+    *(.gnu.warning)
+    *(.glue_7t) *(.glue_7) *(.vfp11_veneer)
+
+    . = ALIGN(0x4);
+    /* These are for running static constructors and destructors under ELF.  */
+    KEEP (*crtbegin.o(.ctors))
+    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*crtend.o(.ctors))
+    KEEP (*crtbegin.o(.dtors))
+    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*crtend.o(.dtors))
+
+    *(.rodata .rodata.* .gnu.linkonce.r.*)
+
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    *(.gcc_except_table) 
+    *(.eh_frame_hdr)
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(.fini_array))
+    KEEP (*(SORT(.fini_array.*)))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >external_ram AT>rom
+  /* .ARM.exidx is sorted, so has to go in its own output section.  */
+   __exidx_start = .;
+  .ARM.exidx :
+  {
+    *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+  } >external_ram AT>rom
+  __exidx_end = .;
+  _etext = .;
+
+  .data :
+  {
+    __data_load = LOADADDR(.data);
+    _sidata = LOADADDR (.data);
+    __data_start = .;
+    _sdata = .;
+    KEEP(*(.jcr))
+    *(.got.plt) *(.got)
+    *(.shdata)
+    *(.data .data.* .gnu.linkonce.d.*)
+    . = ALIGN (4);
+       _edata = .;
+  } >esram AT>rom
+
+  .bss :
+  {
+    __bss_start__ = . ;
+    _sbss = .;
+    *(.shbss)
+    *(.bss .bss.* .gnu.linkonce.b.*)
+    *(COMMON)
+    . = ALIGN (8);
+    __bss_end__ = .;
+    _end = .;
+    __end = _end;
+    _ebss = .;
+    PROVIDE(end = .);
+  } >esram AT>rom
+
+  .stab 0 (NOLOAD) :
+  {
+    *(.stab)
+  }
+
+  .stabstr 0 (NOLOAD) :
+  {
+    *(.stabstr)
+  }
+  /* DWARF debug sections.
+     Symbols in the DWARF debugging sections are relative to the beginning
+     of the section so we begin them at 0.  */
+  /* DWARF 1 */
+  .debug          0 : { *(.debug) }
+  .line           0 : { *(.line) }
+  /* GNU DWARF 1 extensions */
+  .debug_srcinfo  0 : { *(.debug_srcinfo) }
+  .debug_sfnames  0 : { *(.debug_sfnames) }
+  /* DWARF 1.1 and DWARF 2 */
+  .debug_aranges  0 : { *(.debug_aranges) }
+  .debug_pubnames 0 : { *(.debug_pubnames) }
+  /* DWARF 2 */
+  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+  .debug_abbrev   0 : { *(.debug_abbrev) }
+  .debug_line     0 : { *(.debug_line) }
+  .debug_frame    0 : { *(.debug_frame) }
+  .debug_str      0 : { *(.debug_str) }
+  .debug_loc      0 : { *(.debug_loc) }
+  .debug_macinfo  0 : { *(.debug_macinfo) }
+  /* SGI/MIPS DWARF 2 extensions */
+  .debug_weaknames 0 : { *(.debug_weaknames) }
+  .debug_funcnames 0 : { *(.debug_funcnames) }
+  .debug_typenames 0 : { *(.debug_typenames) }
+  .debug_varnames  0 : { *(.debug_varnames) }
+  .note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }
+  .ARM.attributes 0 : { KEEP (*(.ARM.attributes)) }
+  /DISCARD/ : { *(.note.GNU-stack)  }
+}
diff --git a/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/CMSIS/startup_gcc/startup_m2sxxx.s b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/CMSIS/startup_gcc/startup_m2sxxx.s
new file mode 100644 (file)
index 0000000..ff927d5
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/CMSIS/startup_gcc/startup_m2sxxx.s
@@ -0,0 +1,951 @@
+/*******************************************************************************\r
+ * (c) Copyright 2012-2013 Microsemi SoC Products Group.  All rights reserved.\r
+ * \r
+ *  SmartFusion2 vector table and startup code for CodeSourcery G++.\r
+ *\r
+ * SVN $Revision: 5269 $\r
+ * SVN $Date: 2013-03-21 20:53:38 +0000 (Thu, 21 Mar 2013) $\r
+ */\r
+\r
+       .syntax unified\r
+    .cpu cortex-m3\r
+    .thumb\r
+    \r
+\r
+/*==============================================================================\r
+ * Vector table\r
+ */\r
+    .global     g_pfnVectors\r
+    .section    .isr_vector,"a",%progbits\r
+    .type       g_pfnVectors, %object\r
+    .size       g_pfnVectors, .-g_pfnVectors\r
+    \r
+g_pfnVectors:\r
+    .word  _estack\r
+    .word  Reset_Handler\r
+    .word  NMI_Handler\r
+    .word  HardFault_Handler\r
+    .word  MemManage_Handler\r
+    .word  BusFault_Handler\r
+    .word  UsageFault_Handler\r
+    .word  0\r
+    .word  0\r
+    .word  0\r
+    .word  0\r
+    .word  SVC_Handler\r
+    .word  DebugMon_Handler\r
+    .word  0\r
+    .word  PendSV_Handler\r
+    .word  SysTick_Handler\r
+    .word  WdogWakeup_IRQHandler\r
+    .word  RTC_Wakeup_IRQHandler\r
+    .word  SPI0_IRQHandler\r
+    .word  SPI1_IRQHandler\r
+    .word  I2C0_IRQHandler\r
+    .word  I2C0_SMBAlert_IRQHandler\r
+    .word  I2C0_SMBus_IRQHandler\r
+    .word  I2C1_IRQHandler\r
+    .word  I2C1_SMBAlert_IRQHandler\r
+    .word  I2C1_SMBus_IRQHandler\r
+    .word  UART0_IRQHandler\r
+    .word  UART1_IRQHandler\r
+    .word  EthernetMAC_IRQHandler\r
+    .word  DMA_IRQHandler\r
+    .word  Timer1_IRQHandler\r
+    .word  Timer2_IRQHandler\r
+    .word  CAN_IRQHandler\r
+    .word  ENVM0_IRQHandler\r
+    .word  ENVM1_IRQHandler\r
+    .word  ComBlk_IRQHandler\r
+    .word  USB_IRQHandler\r
+    .word  USB_DMA_IRQHandler\r
+    .word  PLL_Lock_IRQHandler\r
+    .word  PLL_LockLost_IRQHandler\r
+    .word  CommSwitchError_IRQHandler\r
+    .word  CacheError_IRQHandler\r
+    .word  DDR_IRQHandler\r
+    .word  HPDMA_Complete_IRQHandler\r
+    .word  HPDMA_Error_IRQHandler\r
+    .word  ECC_Error_IRQHandler\r
+    .word  MDDR_IOCalib_IRQHandler\r
+    .word  FAB_PLL_Lock_IRQHandler\r
+    .word  FAB_PLL_LockLost_IRQHandler\r
+    .word  FIC64_IRQHandler\r
+    .word  FabricIrq0_IRQHandler\r
+    .word  FabricIrq1_IRQHandler\r
+    .word  FabricIrq2_IRQHandler\r
+    .word  FabricIrq3_IRQHandler\r
+    .word  FabricIrq4_IRQHandler\r
+    .word  FabricIrq5_IRQHandler\r
+    .word  FabricIrq6_IRQHandler\r
+    .word  FabricIrq7_IRQHandler\r
+    .word  FabricIrq8_IRQHandler\r
+    .word  FabricIrq9_IRQHandler\r
+    .word  FabricIrq10_IRQHandler\r
+    .word  FabricIrq11_IRQHandler\r
+    .word  FabricIrq12_IRQHandler\r
+    .word  FabricIrq13_IRQHandler\r
+    .word  FabricIrq14_IRQHandler\r
+    .word  FabricIrq15_IRQHandler    \r
+    .word  GPIO0_IRQHandler\r
+    .word  GPIO1_IRQHandler\r
+    .word  GPIO2_IRQHandler\r
+    .word  GPIO3_IRQHandler\r
+    .word  GPIO4_IRQHandler\r
+    .word  GPIO5_IRQHandler\r
+    .word  GPIO6_IRQHandler\r
+    .word  GPIO7_IRQHandler\r
+    .word  GPIO8_IRQHandler\r
+    .word  GPIO9_IRQHandler\r
+    .word  GPIO10_IRQHandler\r
+    .word  GPIO11_IRQHandler\r
+    .word  GPIO12_IRQHandler\r
+    .word  GPIO13_IRQHandler\r
+    .word  GPIO14_IRQHandler\r
+    .word  GPIO15_IRQHandler\r
+    .word  GPIO16_IRQHandler\r
+    .word  GPIO17_IRQHandler\r
+    .word  GPIO18_IRQHandler\r
+    .word  GPIO19_IRQHandler\r
+    .word  GPIO20_IRQHandler\r
+    .word  GPIO21_IRQHandler\r
+    .word  GPIO22_IRQHandler\r
+    .word  GPIO23_IRQHandler\r
+    .word  GPIO24_IRQHandler\r
+    .word  GPIO25_IRQHandler\r
+    .word  GPIO26_IRQHandler\r
+    .word  GPIO27_IRQHandler\r
+    .word  GPIO28_IRQHandler\r
+    .word  GPIO29_IRQHandler\r
+    .word  GPIO30_IRQHandler\r
+    .word  GPIO31_IRQHandler\r
+\r
+       \r
+/*==============================================================================\r
+ * Reset_Handler\r
+ */\r
+    .global Reset_Handler\r
+    .type   Reset_Handler, %function\r
+Reset_Handler:\r
+_start:\r
+/*------------------------------------------------------------------------------       \r
+ * Call CMSIS system init function.\r
+ */\r
+    ldr     r0, =SystemInit\r
+    blx     r0\r
+    \r
+/*------------------------------------------------------------------------------        \r
+ * Check if the executable is built for NVM LMA mirrored to VMA address.\r
+ * This is done for debugging executables running out of eNVM with SoftConsole.\r
+ * The .text section should not be copied in this case since both the LMA and\r
+ * VMA point at the eNVM despite the LMA and VMa having different values.\r
+ */\r
+    ldr r0, =__mirrored_nvm\r
+    cmp r0, #0\r
+    bne copy_data\r
+    \r
+/*------------------------------------------------------------------------------        \r
+ * Copy code section.\r
+ */\r
+       ldr r0, =__text_load\r
+       ldr r1, =__text_start\r
+       ldr r2, =_etext\r
+       cmp r0, r1\r
+       beq copy_data\r
+copy_code_loop:\r
+       cmp r1, r2\r
+    itt ne\r
+       ldrne r3, [r0], #4\r
+       strne r3, [r1], #4\r
+       bne copy_code_loop\r
+\r
+/*------------------------------------------------------------------------------       \r
+ * Copy data section.\r
+ */\r
+copy_data:\r
+       ldr r0, =__data_load\r
+       ldr r1, =__data_start\r
+       ldr r2, =_edata\r
+       cmp r0, r1\r
+       beq clear_bss\r
+copy_data_loop:\r
+       cmp r1, r2\r
+    itt ne\r
+       ldrne r3, [r0], #4\r
+       strne r3, [r1], #4\r
+       bne copy_data_loop\r
+       \r
+/*------------------------------------------------------------------------------       \r
+ * Clear .bss\r
+ */\r
+clear_bss:\r
+       ldr r0, =0\r
+       ldr r1, =__bss_start__\r
+       ldr r2, =__bss_end__\r
+clear_bss_loop:\r
+       cmp r1, r2\r
+    it ne\r
+       strne r0, [r1], #4\r
+       bne clear_bss_loop\r
+\r
+/*------------------------------------------------------------------------------       \r
+ * Call global constructors\r
+ */\r
+    /*\r
+     * Align to word and use 32-bits LDR instruction to ensure the ADD instruction\r
+     * taking PC as argument is aligned on a word boundary.\r
+     */\r
+    .align 4\r
+call_glob_ctor:\r
+       ldr.w r0, =__libc_init_array\r
+    add lr, pc, #3\r
+       bx r0\r
+\r
+/*------------------------------------------------------------------------------       \r
+ * branch to main.\r
+ */\r
+branch_to_main:         \r
+       mov     r0, #0          /*  no arguments  */\r
+       mov     r1, #0          /*  no argv either */\r
+    ldr pc, =main\r
+\r
+ExitLoop:\r
+    B ExitLoop\r
+\r
+/*==============================================================================\r
+ * NMI_Handler\r
+ */\r
+    .weak   NMI_Handler\r
+    .type   NMI_Handler, %function\r
+NMI_Handler:\r
+    B .\r
+\r
+/*==============================================================================\r
+ * HardFault_Handler\r
+ */\r
+    .weak   HardFault_Handler\r
+    .type   HardFault_Handler, %function\r
+HardFault_Handler:\r
+    B .\r
+\r
+/*==============================================================================\r
+ * MemManage_Handler\r
+ */\r
+    .weak   MemManage_Handler\r
+    .type   MemManage_Handler, %function\r
+MemManage_Handler:\r
+    B .\r
+\r
+/*==============================================================================\r
+ * BusFault_Handler\r
+ */\r
+    .weak   BusFault_Handler\r
+    .type   BusFault_Handler, %function\r
+BusFault_Handler:\r
+    B .\r
+\r
+/*==============================================================================\r
+ * UsageFault_Handler\r
+ */\r
+    .weak   UsageFault_Handler\r
+    .type   UsageFault_Handler, %function\r
+UsageFault_Handler:\r
+    B .\r
+\r
+/*==============================================================================\r
+ * SVC_Handler\r
+ */\r
+    .weak   SVC_Handler\r
+    .type   SVC_Handler, %function\r
+SVC_Handler:\r
+    B .\r
+\r
+/*==============================================================================\r
+ * DebugMon_Handler\r
+ */\r
+    .weak   DebugMon_Handler\r
+    .type   DebugMon_Handler, %function\r
+DebugMon_Handler:\r
+    B .\r
+\r
+/*==============================================================================\r
+ * PendSV_Handler\r
+ */\r
+    .weak   PendSV_Handler\r
+    .type   PendSV_Handler, %function\r
+PendSV_Handler:\r
+    B .\r
+\r
+/*==============================================================================\r
+ * SysTick_Handler\r
+ */\r
+    .weak   SysTick_Handler\r
+    .type   SysTick_Handler, %function\r
+SysTick_Handler:\r
+    B .\r
+\r
+/*==============================================================================\r
+ * WdogWakeup_IRQHandler\r
+ */\r
+    .weak   WdogWakeup_IRQHandler\r
+    .type   WdogWakeup_IRQHandler, %function\r
+WdogWakeup_IRQHandler:\r
+    B .\r
+\r
+/*==============================================================================\r
+ * RTC_Wakeup_IRQHandler\r
+ */\r
+    .weak   RTC_Wakeup_IRQHandler\r
+    .type   RTC_Wakeup_IRQHandler, %function\r
+RTC_Wakeup_IRQHandler:\r
+    B .\r
+\r
+/*==============================================================================\r
+ * SPI0_IRQHandler\r
+ */\r
+    .weak   SPI0_IRQHandler\r
+    .type   SPI0_IRQHandler, %function\r
+SPI0_IRQHandler:\r
+    B .\r
+\r
+/*==============================================================================\r
+ * SPI1_IRQHandler\r
+ */\r
+    .weak   SPI1_IRQHandler\r
+    .type   SPI1_IRQHandler, %function\r
+SPI1_IRQHandler:\r
+    B .\r
+\r
+/*==============================================================================\r
+ * I2C0_IRQHandler\r
+ */\r
+    .weak   I2C0_IRQHandler\r
+    .type   I2C0_IRQHandler, %function\r
+I2C0_IRQHandler:\r
+    B .\r
+\r
+/*==============================================================================\r
+ * I2C0_SMBAlert_IRQHandler\r
+ */\r
+    .weak   I2C0_SMBAlert_IRQHandler\r
+    .type   I2C0_SMBAlert_IRQHandler, %function\r
+I2C0_SMBAlert_IRQHandler:\r
+    B .\r
+\r
+/*==============================================================================\r
+ * I2C0_SMBus_IRQHandler\r
+ */\r
+    .weak   I2C0_SMBus_IRQHandler\r
+    .type   I2C0_SMBus_IRQHandler, %function\r
+I2C0_SMBus_IRQHandler:\r
+    B .\r
+\r
+/*==============================================================================\r
+ * I2C1_IRQHandler\r
+ */\r
+    .weak   I2C1_IRQHandler\r
+    .type   I2C1_IRQHandler, %function\r
+I2C1_IRQHandler:\r
+    B .\r
+\r
+/*==============================================================================\r
+ * I2C1_SMBAlert_IRQHandler\r
+ */\r
+    .weak   I2C1_SMBAlert_IRQHandler\r
+    .type   I2C1_SMBAlert_IRQHandler, %function\r
+I2C1_SMBAlert_IRQHandler:\r
+    B .\r
+\r
+/*==============================================================================\r
+ * I2C1_SMBus_IRQHandler\r
+ */\r
+    .weak   I2C1_SMBus_IRQHandler\r
+    .type   I2C1_SMBus_IRQHandler, %function\r
+I2C1_SMBus_IRQHandler:\r
+    B .\r
+\r
+/*==============================================================================\r
+ * UART0_IRQHandler\r
+ */\r
+    .weak   UART0_IRQHandler\r
+    .type   UART0_IRQHandler, %function\r
+UART0_IRQHandler:\r
+    B .\r
+\r
+/*==============================================================================\r
+ * UART1_IRQHandler\r
+ */\r
+    .weak   UART1_IRQHandler\r
+    .type   UART1_IRQHandler, %function\r
+UART1_IRQHandler:\r
+    B .\r
+    \r
+/*==============================================================================\r
+ * EthernetMAC_IRQHandler\r
+ */\r
+    .weak   EthernetMAC_IRQHandler\r
+    .type   EthernetMAC_IRQHandler, %function\r
+EthernetMAC_IRQHandler:\r
+    B .\r
+\r
+/*==============================================================================\r
+ * DMA_IRQHandler\r
+ */\r
+    .weak   DMA_IRQHandler\r
+    .type   DMA_IRQHandler, %function\r
+DMA_IRQHandler:\r
+    B .\r
+\r
+/*==============================================================================\r
+ * Timer1_IRQHandler\r
+ */\r
+    .weak   Timer1_IRQHandler\r
+    .type   Timer1_IRQHandler, %function\r
+Timer1_IRQHandler:\r
+    B .\r
+\r
+/*==============================================================================\r
+ * Timer2_IRQHandler\r
+ */\r
+    .weak   Timer2_IRQHandler\r
+    .type   Timer2_IRQHandler, %function\r
+Timer2_IRQHandler:\r
+    B .\r
+    \r
+/*==============================================================================\r
+ * CAN_IRQHandler\r
+ */\r
+    .weak   CAN_IRQHandler\r
+    .type   CAN_IRQHandler, %function\r
+CAN_IRQHandler:\r
+    B .\r
+    \r
+/*==============================================================================\r
+ * ENVM0_IRQHandler\r
+ */\r
+    .weak   ENVM0_IRQHandler\r
+    .type   ENVM0_IRQHandler, %function\r
+ENVM0_IRQHandler:\r
+    B .\r
+\r
+/*==============================================================================\r
+ * ENVM1_IRQHandler\r
+ */\r
+    .weak   ENVM1_IRQHandler\r
+    .type   ENVM1_IRQHandler, %function\r
+ENVM1_IRQHandler:\r
+    B .\r
+\r
+/*==============================================================================\r
+ * ComBlk_IRQHandler\r
+ */\r
+    .weak   ComBlk_IRQHandler\r
+    .type   ComBlk_IRQHandler, %function\r
+ComBlk_IRQHandler:\r
+    B .\r
+    \r
+/*==============================================================================\r
+ * USB_IRQHandler\r
+ */\r
+    .weak   USB_IRQHandler\r
+    .type   USB_IRQHandler, %function\r
+USB_IRQHandler:\r
+    B .\r
+    \r
+/*==============================================================================\r
+ * USB_DMA_IRQHandler\r
+ */\r
+    .weak   USB_DMA_IRQHandler\r
+    .type   USB_DMA_IRQHandler, %function\r
+USB_DMA_IRQHandler:\r
+    B .\r
+\r
+/*==============================================================================\r
+ * PLL_Lock_IRQHandler\r
+ */\r
+    .weak   PLL_Lock_IRQHandler\r
+    .type   PLL_Lock_IRQHandler, %function\r
+PLL_Lock_IRQHandler:\r
+    B .\r
+\r
+/*==============================================================================\r
+ * PLL_LockLost_IRQHandler\r
+ */\r
+    .weak   PLL_LockLost_IRQHandler\r
+    .type   PLL_LockLost_IRQHandler, %function\r
+PLL_LockLost_IRQHandler:\r
+    B .\r
+\r
+/*==============================================================================\r
+ * CommSwitchError_IRQHandler\r
+ */\r
+    .weak   CommSwitchError_IRQHandler\r
+    .type   CommSwitchError_IRQHandler, %function\r
+CommSwitchError_IRQHandler:\r
+    B .\r
+\r
+/*==============================================================================\r
+ * CacheError_IRQHandler\r
+ */\r
+    .weak   CacheError_IRQHandler\r
+    .type   CacheError_IRQHandler, %function\r
+CacheError_IRQHandler:\r
+    B .\r
+\r
+/*==============================================================================\r
+ * DDR_IRQHandler\r
+ */\r
+    .weak   DDR_IRQHandler\r
+    .type   DDR_IRQHandler, %function\r
+DDR_IRQHandler:\r
+    B .\r
+\r
+/*==============================================================================\r
+ * HPDMA_Complete_IRQHandler\r
+ */\r
+    .weak   HPDMA_Complete_IRQHandler\r
+    .type   HPDMA_Complete_IRQHandler, %function\r
+HPDMA_Complete_IRQHandler:\r
+    B .\r
+\r
+/*==============================================================================\r
+ * HPDMA_Error_IRQHandler\r
+ */\r
+    .weak   HPDMA_Error_IRQHandler\r
+    .type   HPDMA_Error_IRQHandler, %function\r
+HPDMA_Error_IRQHandler:\r
+    B .\r
+    \r
+/*==============================================================================\r
+ * ECC_Error_IRQHandler\r
+ */\r
+    .weak   ECC_Error_IRQHandler\r
+    .type   ECC_Error_IRQHandler, %function\r
+ECC_Error_IRQHandler:\r
+    B .\r
+\r
+/*==============================================================================\r
+ * MDDR_IOCalib_IRQHandler\r
+ */\r
+    .weak   MDDR_IOCalib_IRQHandler\r
+    .type   MDDR_IOCalib_IRQHandler, %function\r
+MDDR_IOCalib_IRQHandler:\r
+    B .\r
+\r
+/*==============================================================================\r
+ * FAB_PLL_Lock_IRQHandler\r
+ */\r
+    .weak   FAB_PLL_Lock_IRQHandler\r
+    .type   FAB_PLL_Lock_IRQHandler, %function    \r
+FAB_PLL_Lock_IRQHandler:\r
+    B .\r
+\r
+/*==============================================================================\r
+ * FAB_PLL_LockLost_IRQHandler\r
+ */\r
+    .weak   FAB_PLL_LockLost_IRQHandler\r
+    .type   FAB_PLL_LockLost_IRQHandler, %function        \r
+FAB_PLL_LockLost_IRQHandler:\r
+    B .\r
+    \r
+/*==============================================================================\r
+ * FIC64_IRQHandler\r
+ */\r
+    .weak   FIC64_IRQHandler\r
+    .type   FIC64_IRQHandler, %function            \r
+FIC64_IRQHandler:\r
+    B .\r
+    \r
+/*==============================================================================\r
+ * FabricIrq0_IRQHandler\r
+ */\r
+    .weak   FabricIrq0_IRQHandler\r
+    .type   FabricIrq0_IRQHandler, %function\r
+FabricIrq0_IRQHandler:\r
+    B .\r
+\r
+/*==============================================================================\r
+ * FabricIrq1_IRQHandler\r
+ */\r
+    .weak   FabricIrq1_IRQHandler\r
+    .type   FabricIrq1_IRQHandler, %function\r
+FabricIrq1_IRQHandler:\r
+    B .\r
+\r
+/*==============================================================================\r
+ * FabricIrq2_IRQHandler\r
+ */\r
+    .weak   FabricIrq2_IRQHandler\r
+    .type   FabricIrq2_IRQHandler, %function\r
+FabricIrq2_IRQHandler:\r
+    B .\r
+\r
+/*==============================================================================\r
+ * FabricIrq3_IRQHandler\r
+ */\r
+    .weak   FabricIrq3_IRQHandler\r
+    .type   FabricIrq3_IRQHandler, %function\r
+FabricIrq3_IRQHandler:\r
+    B .\r
+\r
+/*==============================================================================\r
+ * FabricIrq4_IRQHandler\r
+ */\r
+    .weak   FabricIrq4_IRQHandler\r
+    .type   FabricIrq4_IRQHandler, %function\r
+FabricIrq4_IRQHandler:\r
+    B .\r
+\r
+/*==============================================================================\r
+ * FabricIrq5_IRQHandler\r
+ */\r
+    .weak   FabricIrq5_IRQHandler\r
+    .type   FabricIrq5_IRQHandler, %function\r
+FabricIrq5_IRQHandler:\r
+    B .\r
+\r
+/*==============================================================================\r
+ * FabricIrq6_IRQHandler\r
+ */\r
+    .weak   FabricIrq6_IRQHandler\r
+    .type   FabricIrq6_IRQHandler, %function\r
+FabricIrq6_IRQHandler:\r
+    B .\r
+\r
+/*==============================================================================\r
+ * FabricIrq7_IRQHandler\r
+ */\r
+    .weak   FabricIrq7_IRQHandler\r
+    .type   FabricIrq7_IRQHandler, %function\r
+FabricIrq7_IRQHandler:\r
+    B .\r
+    \r
+/*==============================================================================\r
+ * FabricIrq8_IRQHandler\r
+ */\r
+    .weak   FabricIrq8_IRQHandler\r
+    .type   FabricIrq8_IRQHandler, %function\r
+FabricIrq8_IRQHandler:\r
+    B .\r
+\r
+/*==============================================================================\r
+ * FabricIrq9_IRQHandler\r
+ */\r
+    .weak   FabricIrq9_IRQHandler\r
+    .type   FabricIrq9_IRQHandler, %function\r
+FabricIrq9_IRQHandler:\r
+    B .\r
+\r
+/*==============================================================================\r
+ * FabricIrq10_IRQHandler\r
+ */\r
+    .weak   FabricIrq10_IRQHandler\r
+    .type   FabricIrq10_IRQHandler, %function\r
+FabricIrq10_IRQHandler:\r
+    B .\r
+\r
+/*==============================================================================\r
+ * FabricIrq11_IRQHandler\r
+ */\r
+    .weak   FabricIrq11_IRQHandler\r
+    .type   FabricIrq11_IRQHandler, %function\r
+FabricIrq11_IRQHandler:\r
+    B .\r
+\r
+/*==============================================================================\r
+ * FabricIrq12_IRQHandler\r
+ */\r
+    .weak   FabricIrq12_IRQHandler\r
+    .type   FabricIrq12_IRQHandler, %function\r
+FabricIrq12_IRQHandler:\r
+    B .\r
+\r
+/*==============================================================================\r
+ * FabricIrq13_IRQHandler\r
+ */\r
+    .weak   FabricIrq13_IRQHandler\r
+    .type   FabricIrq13_IRQHandler, %function\r
+FabricIrq13_IRQHandler:\r
+    B .\r
+\r
+/*==============================================================================\r
+ * FabricIrq14_IRQHandler\r
+ */\r
+    .weak   FabricIrq14_IRQHandler\r
+    .type   FabricIrq14_IRQHandler, %function\r
+FabricIrq14_IRQHandler:\r
+    B .\r
+\r
+/*==============================================================================\r
+ * FabricIrq15_IRQHandler\r
+ */\r
+    .weak   FabricIrq15_IRQHandler\r
+    .type   FabricIrq15_IRQHandler, %function\r
+FabricIrq15_IRQHandler:\r
+    B .    \r
+\r
+/*==============================================================================\r
+ * GPIO0_IRQHandler\r
+ */\r
+    .weak   GPIO0_IRQHandler\r
+    .type   GPIO0_IRQHandler, %function\r
+GPIO0_IRQHandler:\r
+    B .\r
+\r
+/*==============================================================================\r
+ * GPIO1_IRQHandler\r
+ */\r
+    .weak   GPIO1_IRQHandler\r
+    .type   GPIO1_IRQHandler, %function\r
+GPIO1_IRQHandler:\r
+    B .\r
+\r
+/*==============================================================================\r
+ * GPIO2_IRQHandler\r
+ */\r
+    .weak   GPIO2_IRQHandler\r
+    .type   GPIO2_IRQHandler, %function\r
+GPIO2_IRQHandler:\r
+    B .\r
+\r
+/*==============================================================================\r
+ * GPIO3_IRQHandler\r
+ */\r
+    .weak   GPIO3_IRQHandler\r
+    .type   GPIO3_IRQHandler, %function\r
+GPIO3_IRQHandler:\r
+    B .\r
+\r
+/*==============================================================================\r
+ * GPIO4_IRQHandler\r
+ */\r
+    .weak   GPIO4_IRQHandler\r
+    .type   GPIO4_IRQHandler, %function\r
+GPIO4_IRQHandler:\r
+    B .\r
+\r
+/*==============================================================================\r
+ * GPIO5_IRQHandler\r
+ */\r
+    .weak   GPIO5_IRQHandler\r
+    .type   GPIO5_IRQHandler, %function\r
+GPIO5_IRQHandler:\r
+    B .\r
+\r
+/*==============================================================================\r
+ * GPIO6_IRQHandler\r
+ */\r
+    .weak   GPIO6_IRQHandler\r
+    .type   GPIO6_IRQHandler, %function\r
+GPIO6_IRQHandler:\r
+    B .\r
+\r
+/*==============================================================================\r
+ * GPIO7_IRQHandler\r
+ */\r
+    .weak   GPIO7_IRQHandler\r
+    .type   GPIO7_IRQHandler, %function\r
+GPIO7_IRQHandler:\r
+    B .\r
+\r
+/*==============================================================================\r
+ * GPIO8_IRQHandler\r
+ */\r
+    .weak   GPIO8_IRQHandler\r
+    .type   GPIO8_IRQHandler, %function\r
+GPIO8_IRQHandler:\r
+    B .\r
+\r
+/*==============================================================================\r
+ * GPIO9_IRQHandler\r
+ */\r
+    .weak   GPIO9_IRQHandler\r
+    .type   GPIO9_IRQHandler, %function\r
+GPIO9_IRQHandler:\r
+    B .\r
+\r
+/*==============================================================================\r
+ * GPIO10_IRQHandler\r
+ */\r
+    .weak   GPIO10_IRQHandler\r
+    .type   GPIO10_IRQHandler, %function\r
+GPIO10_IRQHandler:\r
+    B .\r
+\r
+/*==============================================================================\r
+ * GPIO11_IRQHandler\r
+ */\r
+    .weak   GPIO11_IRQHandler\r
+    .type   GPIO11_IRQHandler, %function\r
+GPIO11_IRQHandler:\r
+    B .\r
+\r
+/*==============================================================================\r
+ * GPIO12_IRQHandler\r
+ */\r
+    .weak   GPIO12_IRQHandler\r
+    .type   GPIO12_IRQHandler, %function\r
+GPIO12_IRQHandler:\r
+    B .\r
+\r
+/*==============================================================================\r
+ * GPIO13_IRQHandler\r
+ */\r
+    .weak   GPIO13_IRQHandler\r
+    .type   GPIO13_IRQHandler, %function\r
+GPIO13_IRQHandler:\r
+    B .\r
+\r
+/*==============================================================================\r
+ * GPIO14_IRQHandler\r
+ */\r
+    .weak   GPIO14_IRQHandler\r
+    .type   GPIO14_IRQHandler, %function\r
+GPIO14_IRQHandler:\r
+    B .\r
+\r
+/*==============================================================================\r
+ * GPIO15_IRQHandler\r
+ */\r
+    .weak   GPIO15_IRQHandler\r
+    .type   GPIO15_IRQHandler, %function\r
+GPIO15_IRQHandler:\r
+    B .\r
+\r
+/*==============================================================================\r
+ * GPIO16_IRQHandler\r
+ */\r
+    .weak   GPIO16_IRQHandler\r
+    .type   GPIO16_IRQHandler, %function\r
+GPIO16_IRQHandler:\r
+    B .\r
+\r
+/*==============================================================================\r
+ * GPIO17_IRQHandler\r
+ */\r
+    .weak   GPIO17_IRQHandler\r
+    .type   GPIO17_IRQHandler, %function\r
+GPIO17_IRQHandler:\r
+    B .\r
+\r
+/*==============================================================================\r
+ * GPIO18_IRQHandler\r
+ */\r
+    .weak   GPIO18_IRQHandler\r
+    .type   GPIO18_IRQHandler, %function\r
+GPIO18_IRQHandler:\r
+    B .\r
+\r
+/*==============================================================================\r
+ * GPIO19_IRQHandler\r
+ */\r
+    .weak   GPIO19_IRQHandler\r
+    .type   GPIO19_IRQHandler, %function\r
+GPIO19_IRQHandler:\r
+    B .\r
+\r
+/*==============================================================================\r
+ * GPIO20_IRQHandler\r
+ */\r
+    .weak   GPIO20_IRQHandler\r
+    .type   GPIO20_IRQHandler, %function\r
+GPIO20_IRQHandler:\r
+    B .\r
+\r
+/*==============================================================================\r
+ * GPIO21_IRQHandler\r
+ */\r
+    .weak   GPIO21_IRQHandler\r
+    .type   GPIO21_IRQHandler, %function\r
+GPIO21_IRQHandler:\r
+    B .\r
+\r
+/*==============================================================================\r
+ * GPIO22_IRQHandler\r
+ */\r
+    .weak   GPIO22_IRQHandler\r
+    .type   GPIO22_IRQHandler, %function\r
+GPIO22_IRQHandler:\r
+    B .\r
+\r
+/*==============================================================================\r
+ * GPIO23_IRQHandler\r
+ */\r
+    .weak   GPIO23_IRQHandler\r
+    .type   GPIO23_IRQHandler, %function\r
+GPIO23_IRQHandler:\r
+    B .\r
+\r
+/*==============================================================================\r
+ * GPIO24_IRQHandler\r
+ */\r
+    .weak   GPIO24_IRQHandler\r
+    .type   GPIO24_IRQHandler, %function\r
+GPIO24_IRQHandler:\r
+    B .\r
+\r
+/*==============================================================================\r
+ * GPIO25_IRQHandler\r
+ */\r
+    .weak   GPIO25_IRQHandler\r
+    .type   GPIO25_IRQHandler, %function\r
+GPIO25_IRQHandler:\r
+    B .\r
+\r
+/*==============================================================================\r
+ * GPIO26_IRQHandler\r
+ */\r
+    .weak   GPIO26_IRQHandler\r
+    .type   GPIO26_IRQHandler, %function\r
+GPIO26_IRQHandler:\r
+    B .\r
+\r
+/*==============================================================================\r
+ * GPIO27_IRQHandler\r
+ */\r
+    .weak   GPIO27_IRQHandler\r
+    .type   GPIO27_IRQHandler, %function\r
+GPIO27_IRQHandler:\r
+    B .\r
+\r
+/*==============================================================================\r
+ * GPIO28_IRQHandler\r
+ */\r
+    .weak   GPIO28_IRQHandler\r
+    .type   GPIO28_IRQHandler, %function\r
+GPIO28_IRQHandler:\r
+    B .\r
+\r
+/*==============================================================================\r
+ * GPIO29_IRQHandler\r
+ */\r
+    .weak   GPIO29_IRQHandler\r
+    .type   GPIO29_IRQHandler, %function\r
+GPIO29_IRQHandler:\r
+    B .\r
+\r
+/*==============================================================================\r
+ * GPIO30_IRQHandler\r
+ */\r
+    .weak   GPIO30_IRQHandler\r
+    .type   GPIO30_IRQHandler, %function\r
+GPIO30_IRQHandler:\r
+    B .\r
+\r
+/*==============================================================================\r
+ * GPIO31_IRQHandler\r
+ */\r
+    .weak   GPIO31_IRQHandler\r
+    .type   GPIO31_IRQHandler, %function\r
+GPIO31_IRQHandler:\r
+    B .\r
+\r
+/*==============================================================================\r
+ * mscc_post_hw_cfg_init\r
+ */\r
+    .weak   mscc_post_hw_cfg_init\r
+    .type   mscc_post_hw_cfg_init, %function\r
+mscc_post_hw_cfg_init:\r
+    BX LR\r
+\r
+.end\r
diff --git a/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/CMSIS/sys_init_cfg_types.h b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/CMSIS/sys_init_cfg_types.h
new file mode 100644 (file)
index 0000000..c8368af
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/CMSIS/sys_init_cfg_types.h
@@ -0,0 +1,212 @@
+/*******************************************************************************\r
+ * (c) Copyright 2012 Microsemi SoC Products Group.  All rights reserved.\r
+ * \r
+ *  \r
+ *\r
+ * SVN $Revision: 4410 $\r
+ * SVN $Date: 2012-07-16 14:36:17 +0100 (Mon, 16 Jul 2012) $\r
+ */\r
+ \r
+#ifndef SYSTEM_INIT_CFG_TYPES_H_\r
+#define SYSTEM_INIT_CFG_TYPES_H_\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif \r
+\r
+/*============================================================================*/\r
+/*                              DDR Configuration                             */\r
+/*============================================================================*/\r
+typedef struct\r
+{\r
+    /*--------------------------------------------------------------------------\r
+     * DDR Controller registers.\r
+     */\r
+    struct\r
+    {\r
+        uint16_t DYN_SOFT_RESET_CR;\r
+        uint16_t RESERVED0;\r
+        uint16_t DYN_REFRESH_1_CR;\r
+        uint16_t DYN_REFRESH_2_CR;\r
+        uint16_t DYN_POWERDOWN_CR;\r
+        uint16_t DYN_DEBUG_CR;\r
+        uint16_t MODE_CR;\r
+        uint16_t ADDR_MAP_BANK_CR;\r
+        uint16_t ECC_DATA_MASK_CR;\r
+        uint16_t ADDR_MAP_COL_1_CR;\r
+        uint16_t ADDR_MAP_COL_2_CR;\r
+        uint16_t ADDR_MAP_ROW_1_CR;\r
+        uint16_t ADDR_MAP_ROW_2_CR;\r
+        uint16_t INIT_1_CR;\r
+        uint16_t CKE_RSTN_CYCLES_1_CR;\r
+        uint16_t CKE_RSTN_CYCLES_2_CR;\r
+        uint16_t INIT_MR_CR;\r
+        uint16_t INIT_EMR_CR;\r
+        uint16_t INIT_EMR2_CR;\r
+        uint16_t INIT_EMR3_CR;\r
+        uint16_t DRAM_BANK_TIMING_PARAM_CR;\r
+        uint16_t DRAM_RD_WR_LATENCY_CR;\r
+        uint16_t DRAM_RD_WR_PRE_CR;\r
+        uint16_t DRAM_MR_TIMING_PARAM_CR;\r
+        uint16_t DRAM_RAS_TIMING_CR;\r
+        uint16_t DRAM_RD_WR_TRNARND_TIME_CR;\r
+        uint16_t DRAM_T_PD_CR;\r
+        uint16_t DRAM_BANK_ACT_TIMING_CR;\r
+        uint16_t ODT_PARAM_1_CR;\r
+        uint16_t ODT_PARAM_2_CR;\r
+        uint16_t ADDR_MAP_COL_3_CR;\r
+        uint16_t MODE_REG_RD_WR_CR;\r
+        uint16_t MODE_REG_DATA_CR;\r
+        uint16_t PWR_SAVE_1_CR;\r
+        uint16_t PWR_SAVE_2_CR;\r
+        uint16_t ZQ_LONG_TIME_CR;\r
+        uint16_t ZQ_SHORT_TIME_CR;\r
+        uint16_t ZQ_SHORT_INT_REFRESH_MARGIN_1_CR;\r
+        uint16_t ZQ_SHORT_INT_REFRESH_MARGIN_2_CR;\r
+        uint16_t PERF_PARAM_1_CR;\r
+        uint16_t HPR_QUEUE_PARAM_1_CR;\r
+        uint16_t HPR_QUEUE_PARAM_2_CR;\r
+        uint16_t LPR_QUEUE_PARAM_1_CR;\r
+        uint16_t LPR_QUEUE_PARAM_2_CR;\r
+        uint16_t WR_QUEUE_PARAM_CR;\r
+        uint16_t PERF_PARAM_2_CR;\r
+        uint16_t PERF_PARAM_3_CR;\r
+        uint16_t DFI_RDDATA_EN_CR;\r
+        uint16_t DFI_MIN_CTRLUPD_TIMING_CR;\r
+        uint16_t DFI_MAX_CTRLUPD_TIMING_CR;\r
+        uint16_t DFI_WR_LVL_CONTROL_1_CR;\r
+        uint16_t DFI_WR_LVL_CONTROL_2_CR;\r
+        uint16_t DFI_RD_LVL_CONTROL_1_CR;\r
+        uint16_t DFI_RD_LVL_CONTROL_2_CR;\r
+        uint16_t DFI_CTRLUPD_TIME_INTERVAL_CR;\r
+        uint16_t DYN_SOFT_RESET_CR2;\r
+        uint16_t AXI_FABRIC_PRI_ID_CR;\r
+    } ddrc;\r
+    \r
+    /*--------------------------------------------------------------------------\r
+     * DDR PHY configuration registers\r
+     */\r
+    struct \r
+    {\r
+        uint16_t LOOPBACK_TEST_CR;\r
+        uint16_t BOARD_LOOPBACK_CR;\r
+        uint16_t CTRL_SLAVE_RATIO_CR;\r
+        uint16_t CTRL_SLAVE_FORCE_CR;\r
+        uint16_t CTRL_SLAVE_DELAY_CR;\r
+        uint16_t DATA_SLICE_IN_USE_CR;\r
+        uint16_t LVL_NUM_OF_DQ0_CR;\r
+        uint16_t DQ_OFFSET_1_CR;\r
+        uint16_t DQ_OFFSET_2_CR;\r
+        uint16_t DQ_OFFSET_3_CR;\r
+        uint16_t DIS_CALIB_RST_CR;\r
+        uint16_t DLL_LOCK_DIFF_CR;\r
+        uint16_t FIFO_WE_IN_DELAY_1_CR;\r
+        uint16_t FIFO_WE_IN_DELAY_2_CR;\r
+        uint16_t FIFO_WE_IN_DELAY_3_CR;\r
+        uint16_t FIFO_WE_IN_FORCE_CR;\r
+        uint16_t FIFO_WE_SLAVE_RATIO_1_CR;\r
+        uint16_t FIFO_WE_SLAVE_RATIO_2_CR;\r
+        uint16_t FIFO_WE_SLAVE_RATIO_3_CR;\r
+        uint16_t FIFO_WE_SLAVE_RATIO_4_CR;\r
+        uint16_t GATELVL_INIT_MODE_CR;\r
+        uint16_t GATELVL_INIT_RATIO_1_CR;\r
+        uint16_t GATELVL_INIT_RATIO_2_CR;\r
+        uint16_t GATELVL_INIT_RATIO_3_CR;\r
+        uint16_t GATELVL_INIT_RATIO_4_CR;\r
+        uint16_t LOCAL_ODT_CR;\r
+        uint16_t INVERT_CLKOUT_CR;\r
+        uint16_t RD_DQS_SLAVE_DELAY_1_CR;\r
+        uint16_t RD_DQS_SLAVE_DELAY_2_CR;\r
+        uint16_t RD_DQS_SLAVE_DELAY_3_CR;\r
+        uint16_t RD_DQS_SLAVE_FORCE_CR;\r
+        uint16_t RD_DQS_SLAVE_RATIO_1_CR;\r
+        uint16_t RD_DQS_SLAVE_RATIO_2_CR;\r
+        uint16_t RD_DQS_SLAVE_RATIO_3_CR;\r
+        uint16_t RD_DQS_SLAVE_RATIO_4_CR;\r
+        uint16_t WR_DQS_SLAVE_DELAY_1_CR;\r
+        uint16_t WR_DQS_SLAVE_DELAY_2_CR;\r
+        uint16_t WR_DQS_SLAVE_DELAY_3_CR;\r
+        uint16_t WR_DQS_SLAVE_FORCE_CR;\r
+        uint16_t WR_DQS_SLAVE_RATIO_1_CR;\r
+        uint16_t WR_DQS_SLAVE_RATIO_2_CR;\r
+        uint16_t WR_DQS_SLAVE_RATIO_3_CR;\r
+        uint16_t WR_DQS_SLAVE_RATIO_4_CR;\r
+        uint16_t WR_DATA_SLAVE_DELAY_1_CR;\r
+        uint16_t WR_DATA_SLAVE_DELAY_2_CR;\r
+        uint16_t WR_DATA_SLAVE_DELAY_3_CR;\r
+        uint16_t WR_DATA_SLAVE_FORCE_CR;\r
+        uint16_t WR_DATA_SLAVE_RATIO_1_CR;\r
+        uint16_t WR_DATA_SLAVE_RATIO_2_CR;\r
+        uint16_t WR_DATA_SLAVE_RATIO_3_CR;\r
+        uint16_t WR_DATA_SLAVE_RATIO_4_CR;\r
+        uint16_t WRLVL_INIT_MODE_CR;\r
+        uint16_t WRLVL_INIT_RATIO_1_CR;\r
+        uint16_t WRLVL_INIT_RATIO_2_CR;\r
+        uint16_t WRLVL_INIT_RATIO_3_CR;\r
+        uint16_t WRLVL_INIT_RATIO_4_CR;\r
+        uint16_t WR_RD_RL_CR;\r
+        uint16_t RDC_FIFO_RST_ERRCNTCLR_CR;\r
+        uint16_t RDC_WE_TO_RE_DELAY_CR;\r
+        uint16_t USE_FIXED_RE_CR;\r
+        uint16_t USE_RANK0_DELAYS_CR;\r
+        uint16_t USE_LVL_TRNG_LEVEL_CR;\r
+        uint16_t CONFIG_CR;\r
+        uint16_t RD_WR_GATE_LVL_CR;\r
+        uint16_t DYN_RESET_CR;\r
+    } phy;\r
+    \r
+    /*--------------------------------------------------------------------------\r
+     * FIC-64 registers\r
+     * These registers are 16-bit wide and 32-bit aligned.\r
+     */\r
+    struct \r
+    {\r
+        uint16_t NB_ADDR_CR;\r
+        uint16_t NBRWB_SIZE_CR;\r
+        uint16_t WB_TIMEOUT_CR;\r
+        uint16_t HPD_SW_RW_EN_CR;\r
+        uint16_t HPD_SW_RW_INVAL_CR;\r
+        uint16_t SW_WR_ERCLR_CR;\r
+        uint16_t ERR_INT_ENABLE_CR;\r
+        uint16_t NUM_AHB_MASTERS_CR;\r
+        uint16_t LOCK_TIMEOUTVAL_1_CR;\r
+        uint16_t LOCK_TIMEOUTVAL_2_CR;\r
+        uint16_t LOCK_TIMEOUT_EN_CR;\r
+    } fic;\r
+} ddr_subsys_cfg_t;\r
+\r
+/*============================================================================*/\r
+/*                             FDDR Configuration                             */\r
+/*============================================================================*/\r
+\r
+typedef struct \r
+{\r
+    uint16_t PLL_CONFIG_LOW_1;\r
+    uint16_t PLL_CONFIG_LOW_2;\r
+    uint16_t PLL_CONFIG_HIGH;\r
+    uint16_t FACC_CLK_EN;\r
+    uint16_t FACC_MUX_CONFIG;\r
+    uint16_t FACC_DIVISOR_RATIO;\r
+    uint16_t PLL_DELAY_LINE_SEL;\r
+    uint16_t SOFT_RESET; \r
+    uint16_t IO_CALIB;\r
+    uint16_t INTERRUPT_ENABLE;\r
+    uint16_t AXI_AHB_MODE_SEL;\r
+    uint16_t PHY_SELF_REF_EN;\r
+} fddr_sysreg_t;\r
+\r
+/*============================================================================*/\r
+/*                 PCI Express Bridge IP Core configuration.                  */\r
+/*============================================================================*/\r
+\r
+typedef struct\r
+{\r
+    uint32_t * p_reg;\r
+    uint32_t value;\r
+} cfg_addr_value_pair_t;\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* SYSTEM_INIT_CFG_TYPES_H_ */\r
diff --git a/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/CMSIS/system_m2sxxx.c b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/CMSIS/system_m2sxxx.c
new file mode 100644 (file)
index 0000000..04134b8
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/CMSIS/system_m2sxxx.c
@@ -0,0 +1,560 @@
+/*******************************************************************************\r
+ * (c) Copyright 2012-2013 Microsemi SoC Products Group. All rights reserved.\r
+ * \r
+ *  SmartFusion2 CMSIS system initialization.\r
+ *\r
+ * SVN $Revision: 5280 $\r
+ * SVN $Date: 2013-03-22 20:51:50 +0000 (Fri, 22 Mar 2013) $\r
+ */\r
+#include "m2sxxx.h"\r
+#include "../drivers_config/sys_config/sys_config.h"\r
+#include "sys_init_cfg_types.h"\r
+\r
+/*------------------------------------------------------------------------------\r
+  Silicon revisions.\r
+ */\r
+#define UNKNOWN_SILICON_REV     0\r
+#define M2S050_REV_A_SILICON    1\r
+#define M2S050_REV_B_SILICON    2\r
+\r
+/*------------------------------------------------------------------------------\r
+ * \r
+ */\r
+void mscc_post_hw_cfg_init(void);\r
+\r
+/*------------------------------------------------------------------------------\r
+ * System registers of interest.\r
+ */\r
+/*\r
+ * MSSDDR_FACC1_CR register masks:\r
+ */\r
+#define DDR_CLK_EN_SHIFT    8u\r
+#define FACC_GLMUX_SEL_MASK         0x00001000u\r
+#define CONTROLLER_PLL_INIT_MASK    0x04000000u\r
+#define RCOSC_DIV2_MASK             0x00000004u\r
+\r
+/*\r
+ * MSSDDR_PLL_STATUS register masks:\r
+ */\r
+#define FAB_PLL_LOCK_MASK   0x00000001u\r
+#define MPLL_LOCK_MASK      0x00000002u\r
+\r
+/*\r
+ * MSSDDR_PLL_STATUS_HIGH_CR register masks:\r
+ */\r
+#define FACC_PLL_BYPASS_MASK    0x00000001u\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Standard CMSIS global variables.\r
+ */\r
+uint32_t SystemCoreClock = MSS_SYS_M3_CLK_FREQ;         /*!< System Clock Frequency (Core Clock) */\r
+\r
+/*------------------------------------------------------------------------------\r
+ * SmartFusion2 specific clocks.\r
+ */\r
+uint32_t g_FrequencyPCLK0 = MSS_SYS_APB_0_CLK_FREQ;     /*!< Clock frequency of APB bus 0. */  \r
+uint32_t g_FrequencyPCLK1 = MSS_SYS_APB_1_CLK_FREQ;     /*!< Clock frequency of APB bus 1. */\r
+uint32_t g_FrequencyPCLK2 = MSS_SYS_APB_2_CLK_FREQ;     /*!< Clock frequency of APB bus 2. */\r
+uint32_t g_FrequencyFIC0 = MSS_SYS_FIC_0_CLK_FREQ;      /*!< Clock frequecny of FPGA fabric interface controller 1. */\r
+uint32_t g_FrequencyFIC1 = MSS_SYS_FIC_1_CLK_FREQ;      /*!< Clock frequecny of FPGA fabric inteface controller 2. */\r
+uint32_t g_FrequencyFIC64 = MSS_SYS_FIC64_CLK_FREQ;     /*!< Clock frequecny of 64-bit FPGA fabric interface controller. */\r
+\r
+/*------------------------------------------------------------------------------\r
+ * System configuration tables generated by Libero.\r
+ */\r
+#if MSS_SYS_MDDR_CONFIG_BY_CORTEX\r
+extern MDDR_TypeDef * const g_m2s_mddr_addr;\r
+extern const ddr_subsys_cfg_t g_m2s_mddr_subsys_config;\r
+#endif\r
+\r
+#if MSS_SYS_FDDR_CONFIG_BY_CORTEX\r
+extern FDDR_TypeDef * const g_m2s_fddr_addr;\r
+extern const ddr_subsys_cfg_t g_m2s_fddr_subsys_config;\r
+#endif\r
+\r
+#define MSS_SYS_SERDES_CONFIG_BY_CORTEX     (MSS_SYS_SERDES_0_CONFIG_BY_CORTEX || MSS_SYS_SERDES_1_CONFIG_BY_CORTEX || MSS_SYS_SERDES_2_CONFIG_BY_CORTEX || MSS_SYS_SERDES_3_CONFIG_BY_CORTEX)\r
+\r
+#if MSS_SYS_SERDES_0_CONFIG_BY_CORTEX\r
+extern const cfg_addr_value_pair_t g_m2s_serdes_0_config[SERDES_0_CFG_NB_OF_PAIRS];\r
+#endif\r
+\r
+#if MSS_SYS_SERDES_1_CONFIG_BY_CORTEX\r
+extern const cfg_addr_value_pair_t g_m2s_serdes_1_config[SERDES_1_CFG_NB_OF_PAIRS];\r
+#endif\r
+\r
+#if MSS_SYS_SERDES_2_CONFIG_BY_CORTEX\r
+extern const cfg_addr_value_pair_t g_m2s_serdes_2_config[SERDES_2_CFG_NB_OF_PAIRS];\r
+#endif\r
+\r
+#if MSS_SYS_SERDES_3_CONFIG_BY_CORTEX\r
+extern const cfg_addr_value_pair_t g_m2s_serdes_3_config[SERDES_3_CFG_NB_OF_PAIRS];\r
+#endif\r
+\r
+#define MSS_SYS_CORESF2RESET_USED  (MSS_SYS_MDDR_CONFIG_BY_CORTEX || MSS_SYS_FDDR_CONFIG_BY_CORTEX || MSS_SYS_SERDES_CONFIG_BY_CORTEX)\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Local functions:\r
+ */\r
+static uint32_t get_silicon_revision(void);\r
+static void silicon_workarounds(void);\r
+static void m2s050_rev_a_workarounds(void);\r
+\r
+#if (MSS_SYS_FACC_INIT_BY_CORTEX == 1)\r
+static void complete_clock_config(void);\r
+#endif\r
+\r
+#if MSS_SYS_SERDES_CONFIG_BY_CORTEX\r
+static void configure_serdes_intf(void);\r
+#endif\r
+\r
+#if (MSS_SYS_MDDR_CONFIG_BY_CORTEX || MSS_SYS_FDDR_CONFIG_BY_CORTEX)\r
+static void config_ddr_subsys\r
+(\r
+    const ddr_subsys_cfg_t * p_ddr_subsys_cfg,\r
+    DDRCore_TypeDef * p_ddr_subsys_regs\r
+);\r
+#endif\r
+\r
+#if MSS_SYS_SERDES_CONFIG_BY_CORTEX\r
+static void config_by_addr_value\r
+(\r
+    const cfg_addr_value_pair_t * p_addr_value_pair,\r
+    uint32_t nb_of_cfg_pairs\r
+);\r
+#endif\r
+\r
+static uint32_t get_rcosc_25_50mhz_frequency(void);\r
+static void set_clock_frequency_globals(uint32_t fclk);\r
+\r
+/***************************************************************************//**\r
+ * See system_m2sxxx.h for details.\r
+ */\r
+void SystemInit(void)\r
+{\r
+    /*\r
+     * Do not make use of global variables or make any asumptions regarding\r
+     * memory content if modifying this function. The memory content has not been\r
+     * initialised by the time this function is called by the start-up code.\r
+     */\r
+#if (MSS_SYS_FACC_INIT_BY_CORTEX == 1)\r
+    complete_clock_config();\r
+#endif\r
+\r
+    silicon_workarounds();\r
+    \r
+    /*--------------------------------------------------------------------------\r
+     * Set STKALIGN to ensure exception stacking starts on 8 bytes address\r
+     * boundary. This ensures compliance with the "Procedure Call Standards for\r
+     * the ARM Architecture" (AAPCS).\r
+     */\r
+    SCB->CCR |= SCB_CCR_STKALIGN_Msk;\r
+    \r
+    /*--------------------------------------------------------------------------\r
+     * MDDR configuration\r
+     */\r
+#if MSS_SYS_MDDR_CONFIG_BY_CORTEX\r
+    config_ddr_subsys(&g_m2s_mddr_subsys_config, &g_m2s_mddr_addr->core);\r
+#endif\r
+\r
+    /*--------------------------------------------------------------------------\r
+     * MDDR configuration\r
+     */\r
+#if MSS_SYS_FDDR_CONFIG_BY_CORTEX\r
+    config_ddr_subsys(&g_m2s_fddr_subsys_config, &g_m2s_fddr_addr->core);\r
+#endif\r
+\r
+    /*--------------------------------------------------------------------------\r
+     * SERDES interfaces configuration.\r
+     */\r
+#if MSS_SYS_SERDES_CONFIG_BY_CORTEX\r
+    configure_serdes_intf();\r
+#endif\r
+\r
+    /*--------------------------------------------------------------------------\r
+     * Call user defined configuration function.\r
+     */\r
+    mscc_post_hw_cfg_init();\r
+    \r
+    /*--------------------------------------------------------------------------\r
+     * Synchronize with CoreSF2Reset controlling resets from the fabric.\r
+     */\r
+#if MSS_SYS_CORESF2RESET_USED\r
+    CORE_SF2_CFG->CONFIG_DONE = 1u; /* Signal to CoreSF2Reset that peripheral \r
+                                       configuration registers have been written.*/\r
+    while(!CORE_SF2_CFG->INIT_DONE)\r
+    {\r
+        ;   /* Wait for INIT_DONE from CoreSF2Reset. */\r
+    }\r
+#endif\r
+}\r
+\r
+/***************************************************************************//**\r
+ * SystemCoreClockUpdate()\r
+ */\r
+#define RCOSC_25_50MHZ_CLK_SRC  0u\r
+#define CLK_XTAL_CLK_SRC        1u\r
+#define RCOSC_1_MHZ_CLK_SRC     2u\r
+#define CCC2ASCI_CLK_SRC        3u\r
+\r
+#define FACC_STANDBY_SHIFT      6u\r
+#define FACC_STANDBY_SEL_MASK   0x00000007u\r
+\r
+#define FREQ_32KHZ   32768u\r
+#define FREQ_1MHZ    1000000u\r
+#define FREQ_25MHZ   25000000u\r
+#define FREQ_50MHZ   50000000u\r
+\r
+void SystemCoreClockUpdate(void)\r
+{\r
+#if 1\r
+    uint32_t controller_pll_init;\r
+    uint32_t clk_src;\r
+\r
+    controller_pll_init = SYSREG->MSSDDR_FACC1_CR & CONTROLLER_PLL_INIT_MASK;\r
+    \r
+    if(0u == controller_pll_init)\r
+    {\r
+        /* Normal operations. */\r
+        uint32_t global_mux_sel;\r
+        \r
+        global_mux_sel = SYSREG->MSSDDR_FACC1_CR & FACC_GLMUX_SEL_MASK;\r
+        if(0u == global_mux_sel)\r
+        {\r
+            /* MSS clocked from MSS PLL. Use Libero flow defines. */\r
+            SystemCoreClock = MSS_SYS_M3_CLK_FREQ;\r
+            g_FrequencyPCLK0 = MSS_SYS_APB_0_CLK_FREQ;\r
+            g_FrequencyPCLK1 = MSS_SYS_APB_1_CLK_FREQ;\r
+            g_FrequencyPCLK2 = MSS_SYS_APB_2_CLK_FREQ;\r
+            g_FrequencyFIC0 = MSS_SYS_FIC_0_CLK_FREQ;\r
+            g_FrequencyFIC1 = MSS_SYS_FIC_1_CLK_FREQ;\r
+            g_FrequencyFIC64 = MSS_SYS_FIC64_CLK_FREQ;\r
+        }\r
+        else\r
+        {\r
+            /* MSS clocked from standby clock. */\r
+            const uint8_t standby_clock_lut[8] = { RCOSC_25_50MHZ_CLK_SRC,\r
+                                                   CLK_XTAL_CLK_SRC,\r
+                                                   RCOSC_25_50MHZ_CLK_SRC,\r
+                                                   CLK_XTAL_CLK_SRC,\r
+                                                   RCOSC_1_MHZ_CLK_SRC,\r
+                                                   RCOSC_1_MHZ_CLK_SRC,\r
+                                                   CCC2ASCI_CLK_SRC,\r
+                                                   CCC2ASCI_CLK_SRC };\r
+            \r
+            uint32_t standby_sel;\r
+            uint8_t clock_source;\r
+            \r
+            standby_sel = (SYSREG->MSSDDR_FACC2_CR >> FACC_STANDBY_SHIFT) & FACC_STANDBY_SEL_MASK;\r
+            clock_source = standby_clock_lut[standby_sel];\r
+            switch(clock_source)\r
+            {\r
+                case RCOSC_25_50MHZ_CLK_SRC:\r
+                    clk_src = get_rcosc_25_50mhz_frequency();\r
+                    set_clock_frequency_globals(clk_src);\r
+                break;\r
+                \r
+                case CLK_XTAL_CLK_SRC:\r
+                    set_clock_frequency_globals(FREQ_32KHZ);\r
+                break;\r
+                \r
+                case RCOSC_1_MHZ_CLK_SRC:\r
+                    set_clock_frequency_globals(FREQ_1MHZ);\r
+                break;\r
+                \r
+                case CCC2ASCI_CLK_SRC:\r
+                    /* Fall through. */\r
+                default:\r
+                    set_clock_frequency_globals(FREQ_1MHZ);\r
+                break;\r
+            }   \r
+        }\r
+    }\r
+    else\r
+    {\r
+        /* PLL initialization mode. Running from 25/50MHZ RC oscillator. */\r
+        clk_src = get_rcosc_25_50mhz_frequency();\r
+        set_clock_frequency_globals(clk_src);\r
+    }\r
+    \r
+#else\r
+    /*\r
+     * Reset the clock frequency global variables to the values delected in the\r
+     * Libero flow.\r
+     */\r
+    SystemCoreClock = MSS_SYS_M3_CLK_FREQ;\r
+    g_FrequencyPCLK0 = MSS_SYS_APB_0_CLK_FREQ;\r
+    g_FrequencyPCLK1 = MSS_SYS_APB_1_CLK_FREQ;\r
+    g_FrequencyPCLK2 = MSS_SYS_APB_2_CLK_FREQ;\r
+    g_FrequencyFIC0 = MSS_SYS_FIC_0_CLK_FREQ;\r
+    g_FrequencyFIC1 = MSS_SYS_FIC_1_CLK_FREQ;\r
+    g_FrequencyFIC64 = MSS_SYS_FIC64_CLK_FREQ;\r
+#endif\r
+}\r
+\r
+/***************************************************************************//**\r
+ * Find out frequency generated by the 25_50mhz RC osciallator.\r
+ */\r
+static uint32_t get_rcosc_25_50mhz_frequency(void)\r
+{\r
+    uint32_t rcosc_div2;\r
+    uint32_t rcosc_frequency;\r
+    \r
+    rcosc_div2 = SYSREG->MSSDDR_PLL_STATUS & RCOSC_DIV2_MASK;\r
+    if(0u == rcosc_div2)\r
+    {\r
+        /* 25_50mhz oscillator is configured for 25 MHz operations. */\r
+        rcosc_frequency = FREQ_25MHZ;\r
+    }\r
+    else\r
+    {\r
+        /* 25_50mhz oscillator is configured for 50 MHz operations. */\r
+        rcosc_frequency = FREQ_50MHZ;\r
+    }\r
+    \r
+    return rcosc_frequency;\r
+}\r
+\r
+/***************************************************************************//**\r
+   Set the value of the clock frequency global variables based on the value of\r
+   standby_clk passed as parameter.\r
+   The following global variables are set by this function:\r
+        - SystemCoreClock\r
+        - g_FrequencyPCLK0\r
+        - g_FrequencyPCLK1\r
+        - g_FrequencyPCLK2\r
+        - g_FrequencyFIC0\r
+        - g_FrequencyFIC1\r
+        - g_FrequencyFIC64\r
+ */\r
+static void set_clock_frequency_globals(uint32_t standby_clk)\r
+{\r
+    SystemCoreClock = standby_clk;\r
+    g_FrequencyPCLK0 = standby_clk;\r
+    g_FrequencyPCLK1 = standby_clk;\r
+    g_FrequencyPCLK2 = MSS_SYS_APB_2_CLK_FREQ;\r
+    g_FrequencyFIC0 = standby_clk;\r
+    g_FrequencyFIC1 = standby_clk;\r
+    g_FrequencyFIC64 = standby_clk;\r
+}\r
+\r
+/***************************************************************************//**\r
+ * Write 16-bit configuration values into 32-bit word aligned registers.\r
+ */\r
+#if (MSS_SYS_MDDR_CONFIG_BY_CORTEX || MSS_SYS_FDDR_CONFIG_BY_CORTEX)\r
+static void copy_cfg16_to_regs\r
+(\r
+    volatile uint32_t * p_regs,\r
+    const uint16_t * p_cfg,\r
+    uint32_t nb_16bit_words\r
+)\r
+{\r
+    uint32_t inc;\r
+    \r
+    for(inc = 0u; inc < nb_16bit_words; ++inc)\r
+    {\r
+        p_regs[inc] = p_cfg[inc];\r
+    }\r
+}\r
+#endif\r
+\r
+/***************************************************************************//**\r
+ * Configure peripheral using register address and register value pairs.\r
+ */\r
+#if MSS_SYS_SERDES_CONFIG_BY_CORTEX\r
+static void config_by_addr_value\r
+(\r
+    const cfg_addr_value_pair_t * p_addr_value_pair,\r
+    uint32_t nb_of_cfg_pairs\r
+)\r
+{\r
+    uint32_t inc;\r
+    \r
+    for(inc = 0u; inc < nb_of_cfg_pairs; ++inc)\r
+    {\r
+        *p_addr_value_pair[inc].p_reg = p_addr_value_pair[inc].value;\r
+    }\r
+}\r
+#endif\r
+\r
+/***************************************************************************//**\r
+ * DDR subsystem configuration.\r
+ */\r
+#if (MSS_SYS_MDDR_CONFIG_BY_CORTEX || MSS_SYS_FDDR_CONFIG_BY_CORTEX)\r
+\r
+#define NB_OF_DDRC_REGS_TO_CONFIG       57u\r
+#define NB_OF_DDR_PHY_REGS_TO_CONFIG    65u\r
+\r
+static void config_ddr_subsys\r
+(\r
+    const ddr_subsys_cfg_t * p_ddr_subsys_cfg,\r
+    DDRCore_TypeDef * p_ddr_subsys_regs\r
+)\r
+{\r
+    volatile uint32_t * p_regs;\r
+    const uint16_t * p_cfg;\r
+    \r
+    /*--------------------------------------------------------------------------\r
+     * Configure DDR controller part of the MDDR subsystem.\r
+     */\r
+    p_cfg = &p_ddr_subsys_cfg->ddrc.DYN_SOFT_RESET_CR;\r
+    p_regs = &p_ddr_subsys_regs->ddrc.DYN_SOFT_RESET_CR;\r
+\r
+    copy_cfg16_to_regs(p_regs, p_cfg, NB_OF_DDRC_REGS_TO_CONFIG);\r
+    \r
+    /*--------------------------------------------------------------------------\r
+     * Configure DDR PHY.\r
+     */\r
+    p_cfg = &p_ddr_subsys_cfg->phy.LOOPBACK_TEST_CR;\r
+    p_regs = &p_ddr_subsys_regs->phy.LOOPBACK_TEST_CR;\r
+\r
+    copy_cfg16_to_regs(p_regs, p_cfg, NB_OF_DDR_PHY_REGS_TO_CONFIG);\r
+    \r
+    /*--------------------------------------------------------------------------\r
+     * Configure DDR FIC.\r
+     */\r
+    p_ddr_subsys_regs->fic.NB_ADDR_CR = p_ddr_subsys_cfg->fic.NB_ADDR_CR;\r
+    p_ddr_subsys_regs->fic.NBRWB_SIZE_CR = p_ddr_subsys_cfg->fic.NBRWB_SIZE_CR;\r
+    p_ddr_subsys_regs->fic.WB_TIMEOUT_CR = p_ddr_subsys_cfg->fic.WB_TIMEOUT_CR;\r
+    p_ddr_subsys_regs->fic.HPD_SW_RW_EN_CR = p_ddr_subsys_cfg->fic.HPD_SW_RW_EN_CR;\r
+    p_ddr_subsys_regs->fic.HPD_SW_RW_INVAL_CR = p_ddr_subsys_cfg->fic.HPD_SW_RW_INVAL_CR;\r
+    p_ddr_subsys_regs->fic.SW_WR_ERCLR_CR = p_ddr_subsys_cfg->fic.SW_WR_ERCLR_CR;\r
+    p_ddr_subsys_regs->fic.ERR_INT_ENABLE_CR = p_ddr_subsys_cfg->fic.ERR_INT_ENABLE_CR;\r
+    p_ddr_subsys_regs->fic.NUM_AHB_MASTERS_CR = p_ddr_subsys_cfg->fic.NUM_AHB_MASTERS_CR;\r
+    p_ddr_subsys_regs->fic.LOCK_TIMEOUTVAL_CR[0] = p_ddr_subsys_cfg->fic.LOCK_TIMEOUTVAL_1_CR;\r
+    p_ddr_subsys_regs->fic.LOCK_TIMEOUTVAL_CR[1] = p_ddr_subsys_cfg->fic.LOCK_TIMEOUTVAL_2_CR;\r
+    p_ddr_subsys_regs->fic.LOCK_TIMEOUT_EN_CR = p_ddr_subsys_cfg->fic.LOCK_TIMEOUT_EN_CR;\r
+\r
+    /*--------------------------------------------------------------------------\r
+     * Enable DDR.\r
+     */\r
+    p_ddr_subsys_regs->ddrc.DYN_SOFT_RESET_CR = 0x01u;\r
+    \r
+    while(0x0000u == p_ddr_subsys_regs->ddrc.DDRC_SR)\r
+    {\r
+        ;\r
+    }        \r
+}\r
+\r
+#endif\r
+\r
+/***************************************************************************//**\r
+ * Configure SERDES interfaces.\r
+ */\r
+#if MSS_SYS_SERDES_CONFIG_BY_CORTEX\r
+\r
+static void configure_serdes_intf(void)\r
+{\r
+#if MSS_SYS_SERDES_0_CONFIG_BY_CORTEX\r
+    config_by_addr_value(g_m2s_serdes_0_config, SERDES_0_CFG_NB_OF_PAIRS);\r
+#endif\r
+\r
+#if MSS_SYS_SERDES_1_CONFIG_BY_CORTEX\r
+    config_by_addr_value(g_m2s_serdes_1_config, SERDES_1_CFG_NB_OF_PAIRS);\r
+#endif\r
+\r
+#if MSS_SYS_SERDES_2_CONFIG_BY_CORTEX\r
+    config_by_addr_value(g_m2s_serdes_2_config, SERDES_2_CFG_NB_OF_PAIRS);\r
+#endif\r
+\r
+#if MSS_SYS_SERDES_3_CONFIG_BY_CORTEX\r
+    config_by_addr_value(g_m2s_serdes_3_config, SERDES_3_CFG_NB_OF_PAIRS);\r
+#endif\r
+}\r
+\r
+#endif\r
+\r
+/*------------------------------------------------------------------------------\r
+  Retrieve silicon revision from system registers.\r
+ */\r
+static uint32_t get_silicon_revision(void)\r
+{\r
+    uint32_t silicon_revision;\r
+    uint32_t device_version;\r
+    \r
+    device_version = SYSREG->DEVICE_VERSION;\r
+    switch(device_version)\r
+    {\r
+        case 0x0000F802:\r
+            silicon_revision = M2S050_REV_A_SILICON;\r
+            break;\r
+            \r
+        case 0x0001F802:\r
+            silicon_revision = M2S050_REV_B_SILICON;\r
+            break;\r
+            \r
+        default:\r
+            silicon_revision = UNKNOWN_SILICON_REV;\r
+            break;\r
+    }\r
+    \r
+    return silicon_revision;\r
+}\r
+\r
+/*------------------------------------------------------------------------------\r
+  Workarounds for various silicon versions.\r
+ */\r
+static void silicon_workarounds(void)\r
+{\r
+    uint32_t silicon_revision;\r
+    \r
+    silicon_revision = get_silicon_revision();\r
+    \r
+    switch(silicon_revision)\r
+    {\r
+        case M2S050_REV_A_SILICON:\r
+            m2s050_rev_a_workarounds();\r
+            break;\r
+            \r
+        case M2S050_REV_B_SILICON:\r
+            /* Fall through. */\r
+        case UNKNOWN_SILICON_REV:\r
+            /* Fall through. */\r
+        default:\r
+            break;\r
+    }\r
+}\r
+\r
+/*------------------------------------------------------------------------------\r
+  Silicon workarounds for M2S050 rev A.\r
+ */\r
+static void m2s050_rev_a_workarounds(void)\r
+{\r
+    /*--------------------------------------------------------------------------\r
+     * Work around a couple of silicon issues:\r
+     */\r
+    /* DDR_CLK_EN <- 1 */\r
+    SYSREG->MSSDDR_FACC1_CR |= (uint32_t)1 << DDR_CLK_EN_SHIFT;\r
+    \r
+    /* CONTROLLER_PLL_INIT <- 0 */\r
+    SYSREG->MSSDDR_FACC1_CR = SYSREG->MSSDDR_FACC1_CR & ~CONTROLLER_PLL_INIT_MASK;\r
+}\r
+\r
+/*------------------------------------------------------------------------------\r
+  Complete clock configuration if requested by Libero.\r
+ */\r
+#if (MSS_SYS_FACC_INIT_BY_CORTEX == 1)\r
+static void complete_clock_config(void)\r
+{\r
+    uint32_t pll_locked;\r
+    \r
+    /* Wait for fabric PLL to lock. */\r
+    do {\r
+        pll_locked = SYSREG->MSSDDR_PLL_STATUS & FAB_PLL_LOCK_MASK;\r
+    } while(!pll_locked);\r
+    \r
+    /* Negate MPLL bypass. */\r
+    SYSREG->MSSDDR_PLL_STATUS_HIGH_CR &= ~FACC_PLL_BYPASS_MASK;\r
+    \r
+    /* Wait for MPLL to lock. */\r
+    do {\r
+        pll_locked = SYSREG->MSSDDR_PLL_STATUS & MPLL_LOCK_MASK;\r
+    } while(!pll_locked);\r
+    \r
+    /* Switch FACC from standby to run mode. */\r
+    SYSREG->MSSDDR_FACC1_CR &= ~FACC_GLMUX_SEL_MASK;\r
+\r
+    /* Negate FPGA_SOFTRESET to de-assert MSS_RESET_N_M2F in the fabric */\r
+    SYSREG->SOFT_RST_CR &= ~SYSREG_FPGA_SOFTRESET_MASK;\r
+}\r
+#endif\r
+\r
diff --git a/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/CMSIS/system_m2sxxx.h b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/CMSIS/system_m2sxxx.h
new file mode 100644 (file)
index 0000000..3b75376
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/CMSIS/system_m2sxxx.h
@@ -0,0 +1,49 @@
+/*******************************************************************************\r
+ * (c) Copyright 2012-2013 Microsemi SoC Products Group. All rights reserved.\r
+ * \r
+ *  SmartFusion2 CMSIS system initialization.\r
+ *\r
+ * SVN $Revision: 5280 $\r
+ * SVN $Date: 2013-03-22 20:51:50 +0000 (Fri, 22 Mar 2013) $\r
+ */\r
+\r
+#ifndef SYSTEM_M2SXXX_H\r
+#define SYSTEM_M2SXXX_H\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif \r
+\r
+/* Standard CMSIS global variables. */\r
+extern uint32_t SystemCoreClock;    /*!< System Clock Frequency (Core Clock) */\r
+\r
+/* SmartFusion2 specific clocks. */\r
+extern uint32_t g_FrequencyPCLK0;   /*!< Clock frequency of APB bus 0. */  \r
+extern uint32_t g_FrequencyPCLK1;   /*!< Clock frequency of APB bus 1. */\r
+extern uint32_t g_FrequencyPCLK2;   /*!< Clock frequency of APB bus 2. */\r
+extern uint32_t g_FrequencyFIC0;    /*!< Clock frequecny of FPGA fabric interface controller 1. */\r
+extern uint32_t g_FrequencyFIC1;    /*!< Clock frequecny of FPGA fabric inteface controller 2. */\r
+extern uint32_t g_FrequencyFIC64;   /*!< Clock frequecny of 64-bit FPGA fabric interface controller. */\r
+\r
+\r
+/***************************************************************************//**\r
+ * The SystemInit() is a standard CMSIS function called during system startup.\r
+ * It is meant to perform low level hardware setup such as configuring DDR and\r
+ * SERDES controllers.\r
+ */\r
+void SystemInit(void);\r
+\r
+/***************************************************************************//**\r
+ * The SystemCoreClockUpdate() is a standard CMSIS function which can be called\r
+ * by the application in order to ensure that the SystemCoreClock global\r
+ * variable contains the up to date Cortex-M3 core frequency. Calling this\r
+ * function also updates the global variables containing the frequencies of the\r
+ * APB busses connecting the peripherals.\r
+ */\r
+void SystemCoreClockUpdate(void);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif\r
diff --git a/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/RTOSDemo_hw_platform.h b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/RTOSDemo_hw_platform.h
new file mode 100644 (file)
index 0000000..1fffa71
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/RTOSDemo_hw_platform.h
@@ -0,0 +1,16 @@
+#ifndef RTOSDemo_HW_PLATFORM_H_\r
+#define RTOSDemo_HW_PLATFORM_H_\r
+/*****************************************************************************\r
+*\r
+*Created by Actel SmartDesign  Sun May 05 13:23:22 2013\r
+*\r
+*Memory map specification for peripherals in RTOSDemo\r
+*/\r
+\r
+/*-----------------------------------------------------------------------------\r
+* CM3 subsystem memory map\r
+* Master(s) for this subsystem: CM3 \r
+*---------------------------------------------------------------------------*/\r
+\r
+\r
+#endif /* RTOSDemo_HW_PLATFORM_H_*/\r
diff --git a/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers/mss_gpio/mss_gpio.c b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers/mss_gpio/mss_gpio.c
new file mode 100644 (file)
index 0000000..096a827
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers/mss_gpio/mss_gpio.c
@@ -0,0 +1,296 @@
+/*******************************************************************************\r
+ * (c) Copyright 2008-2013 Microsemi SoC Products Group.  All rights reserved.\r
+ * \r
+ * SmartFusion2 microcontroller subsystem GPIO bare metal driver implementation.\r
+ *\r
+ * SVN $Revision: 5394 $\r
+ * SVN $Date: 2013-03-27 20:56:36 +0000 (Wed, 27 Mar 2013) $\r
+ */\r
+#include "mss_gpio.h"\r
+#include "../../CMSIS/mss_assert.h"\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif \r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ * Defines.\r
+ */\r
+#define GPIO_INT_ENABLE_MASK        ((uint32_t)0x00000008uL)\r
+#define OUTPUT_BUFFER_ENABLE_MASK   0x00000004u\r
+\r
+#define NB_OF_GPIO  ((uint32_t)32)\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ * Lookup table of GPIO configuration registers address indexed on GPIO ID.\r
+ */\r
+static uint32_t volatile * const g_config_reg_lut[NB_OF_GPIO] =\r
+{\r
+    &(GPIO->GPIO_0_CFG),\r
+    &(GPIO->GPIO_1_CFG),\r
+    &(GPIO->GPIO_2_CFG),\r
+    &(GPIO->GPIO_3_CFG),\r
+    &(GPIO->GPIO_4_CFG),\r
+    &(GPIO->GPIO_5_CFG),\r
+    &(GPIO->GPIO_6_CFG),\r
+    &(GPIO->GPIO_7_CFG),\r
+    &(GPIO->GPIO_8_CFG),\r
+    &(GPIO->GPIO_9_CFG),\r
+    &(GPIO->GPIO_10_CFG),\r
+    &(GPIO->GPIO_11_CFG),\r
+    &(GPIO->GPIO_12_CFG),\r
+    &(GPIO->GPIO_13_CFG),\r
+    &(GPIO->GPIO_14_CFG),\r
+    &(GPIO->GPIO_15_CFG),\r
+    &(GPIO->GPIO_16_CFG),\r
+    &(GPIO->GPIO_17_CFG),\r
+    &(GPIO->GPIO_18_CFG),\r
+    &(GPIO->GPIO_19_CFG),\r
+    &(GPIO->GPIO_20_CFG),\r
+    &(GPIO->GPIO_21_CFG),\r
+    &(GPIO->GPIO_22_CFG),\r
+    &(GPIO->GPIO_23_CFG),\r
+    &(GPIO->GPIO_24_CFG),\r
+    &(GPIO->GPIO_25_CFG),\r
+    &(GPIO->GPIO_26_CFG),\r
+    &(GPIO->GPIO_27_CFG),\r
+    &(GPIO->GPIO_28_CFG),\r
+    &(GPIO->GPIO_29_CFG),\r
+    &(GPIO->GPIO_30_CFG),\r
+    &(GPIO->GPIO_31_CFG)\r
+};\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ * Lookup table of Cortex-M3 GPIO interrupt number indexed on GPIO ID.\r
+ */\r
+static const IRQn_Type g_gpio_irqn_lut[NB_OF_GPIO] =\r
+{\r
+    GPIO0_IRQn,\r
+    GPIO1_IRQn,\r
+    GPIO2_IRQn,\r
+    GPIO3_IRQn,\r
+    GPIO4_IRQn,\r
+    GPIO5_IRQn,\r
+    GPIO6_IRQn,\r
+    GPIO7_IRQn,\r
+    GPIO8_IRQn,\r
+    GPIO9_IRQn,\r
+    GPIO10_IRQn,\r
+    GPIO11_IRQn,\r
+    GPIO12_IRQn,\r
+    GPIO13_IRQn,\r
+    GPIO14_IRQn,\r
+    GPIO15_IRQn,\r
+    GPIO16_IRQn,\r
+    GPIO17_IRQn,\r
+    GPIO18_IRQn,\r
+    GPIO19_IRQn,\r
+    GPIO20_IRQn,\r
+    GPIO21_IRQn,\r
+    GPIO22_IRQn,\r
+    GPIO23_IRQn,\r
+    GPIO24_IRQn,\r
+    GPIO25_IRQn,\r
+    GPIO26_IRQn,\r
+    GPIO27_IRQn,\r
+    GPIO28_IRQn,\r
+    GPIO29_IRQn,\r
+    GPIO30_IRQn,\r
+    GPIO31_IRQn\r
+};\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ * MSS_GPIO_init\r
+ * See "mss_gpio.h" for details of how to use this function.\r
+ */\r
+void MSS_GPIO_init( void )\r
+{\r
+    uint32_t inc;\r
+    \r
+    /* reset MSS GPIO hardware */\r
+    SYSREG->SOFT_RST_CR |= SYSREG_GPIO_SOFTRESET_MASK;\r
+    SYSREG->SOFT_RST_CR |= (SYSREG_GPIO_7_0_SOFTRESET_MASK |\r
+                            SYSREG_GPIO_15_8_SOFTRESET_MASK |\r
+                            SYSREG_GPIO_23_16_SOFTRESET_MASK |\r
+                            SYSREG_GPIO_31_24_SOFTRESET_MASK);\r
+                            \r
+    /* Clear any previously pended MSS GPIO interrupt */\r
+    for(inc = 0U; inc < NB_OF_GPIO; ++inc)\r
+    {\r
+        NVIC_DisableIRQ(g_gpio_irqn_lut[inc]);\r
+        NVIC_ClearPendingIRQ(g_gpio_irqn_lut[inc]);\r
+    }\r
+    /* Take MSS GPIO hardware out of reset. */\r
+    SYSREG->SOFT_RST_CR &= ~(SYSREG_GPIO_7_0_SOFTRESET_MASK |\r
+                             SYSREG_GPIO_15_8_SOFTRESET_MASK |\r
+                             SYSREG_GPIO_23_16_SOFTRESET_MASK |\r
+                             SYSREG_GPIO_31_24_SOFTRESET_MASK);\r
+    SYSREG->SOFT_RST_CR &= ~SYSREG_GPIO_SOFTRESET_MASK;\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ * MSS_GPIO_config\r
+ * See "mss_gpio.h" for details of how to use this function.\r
+ */\r
+void MSS_GPIO_config\r
+(\r
+    mss_gpio_id_t port_id,\r
+    uint32_t config\r
+)\r
+{\r
+    uint32_t gpio_idx = (uint32_t)port_id;\r
+    \r
+    ASSERT(gpio_idx < NB_OF_GPIO);\r
+\r
+    if(gpio_idx < NB_OF_GPIO)\r
+    {\r
+        *(g_config_reg_lut[gpio_idx]) = config;\r
+    }\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ * MSS_GPIO_set_output\r
+ * See "mss_gpio.h" for details of how to use this function.\r
+ */\r
+void MSS_GPIO_set_output\r
+(\r
+    mss_gpio_id_t port_id,\r
+    uint8_t value\r
+)\r
+{\r
+    uint32_t gpio_setting;\r
+    uint32_t gpio_idx = (uint32_t)port_id;\r
+    \r
+    ASSERT(gpio_idx < NB_OF_GPIO);\r
+    \r
+    if(gpio_idx < NB_OF_GPIO)\r
+    {\r
+        gpio_setting = GPIO->GPIO_OUT;\r
+        gpio_setting &= ~((uint32_t)0x01u << gpio_idx);\r
+        gpio_setting |= ((uint32_t)value & 0x01u) << gpio_idx;\r
+        GPIO->GPIO_OUT = gpio_setting;\r
+    }\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ * MSS_GPIO_drive_inout\r
+ * See "mss_gpio.h" for details of how to use this function.\r
+ */\r
+void MSS_GPIO_drive_inout\r
+(\r
+    mss_gpio_id_t port_id,\r
+    mss_gpio_inout_state_t inout_state\r
+)\r
+{\r
+    uint32_t outputs_state;\r
+    uint32_t config;\r
+    uint32_t gpio_idx = (uint32_t)port_id;\r
+    \r
+    ASSERT(gpio_idx < NB_OF_GPIO);\r
+    \r
+    if(gpio_idx < NB_OF_GPIO)\r
+    {\r
+        switch(inout_state)\r
+        {\r
+            case MSS_GPIO_DRIVE_HIGH:\r
+                /* Set output high */\r
+                outputs_state = GPIO->GPIO_OUT;\r
+                outputs_state |= (uint32_t)1 << gpio_idx;\r
+                GPIO->GPIO_OUT = outputs_state;\r
+                /* Enable output buffer */\r
+                config = *(g_config_reg_lut[gpio_idx]);\r
+                config |= OUTPUT_BUFFER_ENABLE_MASK;\r
+                *(g_config_reg_lut[gpio_idx]) = config;\r
+            break;\r
+                \r
+            case MSS_GPIO_DRIVE_LOW:\r
+                /* Set output low */\r
+                outputs_state = GPIO->GPIO_OUT;\r
+                outputs_state &= ~((uint32_t)((uint32_t)1 << gpio_idx));\r
+                GPIO->GPIO_OUT = outputs_state;\r
+                /* Enable output buffer */\r
+                config = *(g_config_reg_lut[gpio_idx]);\r
+                config |= OUTPUT_BUFFER_ENABLE_MASK;\r
+                *(g_config_reg_lut[gpio_idx]) = config;\r
+            break;\r
+                \r
+            case MSS_GPIO_HIGH_Z:\r
+                /* Disable output buffer */\r
+                config = *(g_config_reg_lut[gpio_idx]);\r
+                config &= ~OUTPUT_BUFFER_ENABLE_MASK;\r
+                *(g_config_reg_lut[gpio_idx]) = config;\r
+            break;\r
+                \r
+            default:\r
+                ASSERT(0);\r
+            break;\r
+        }\r
+    }\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ * MSS_GPIO_enable_irq\r
+ * See "mss_gpio.h" for details of how to use this function.\r
+ */\r
+void MSS_GPIO_enable_irq\r
+(\r
+    mss_gpio_id_t port_id\r
+)\r
+{\r
+    uint32_t cfg_value;\r
+    uint32_t gpio_idx = (uint32_t)port_id;\r
+    \r
+    ASSERT(gpio_idx < NB_OF_GPIO);\r
+    \r
+    if(gpio_idx < NB_OF_GPIO)\r
+    {\r
+        cfg_value = *(g_config_reg_lut[gpio_idx]);\r
+        *(g_config_reg_lut[gpio_idx]) = (cfg_value | GPIO_INT_ENABLE_MASK);\r
+        NVIC_EnableIRQ(g_gpio_irqn_lut[gpio_idx]);\r
+    }\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ * MSS_GPIO_disable_irq\r
+ * See "mss_gpio.h" for details of how to use this function.\r
+ */\r
+void MSS_GPIO_disable_irq\r
+(\r
+    mss_gpio_id_t port_id\r
+)\r
+{\r
+    uint32_t cfg_value;\r
+    uint32_t gpio_idx = (uint32_t)port_id;\r
+    \r
+    ASSERT(gpio_idx < NB_OF_GPIO);\r
+\r
+    if(gpio_idx < NB_OF_GPIO)\r
+    {\r
+        cfg_value = *(g_config_reg_lut[gpio_idx]);\r
+        *(g_config_reg_lut[gpio_idx]) = (cfg_value & ~GPIO_INT_ENABLE_MASK);\r
+    }\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ * MSS_GPIO_clear_irq\r
+ * See "mss_gpio.h" for details of how to use this function.\r
+ */\r
+void MSS_GPIO_clear_irq\r
+(\r
+    mss_gpio_id_t port_id\r
+)\r
+{\r
+    uint32_t gpio_idx = (uint32_t)port_id;\r
+    \r
+    ASSERT(gpio_idx < NB_OF_GPIO);\r
+    \r
+    if(gpio_idx < NB_OF_GPIO)\r
+    {\r
+        GPIO->GPIO_IRQ = ((uint32_t)1) << gpio_idx;\r
+    }\r
+}\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
diff --git a/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers/mss_gpio/mss_gpio.h b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers/mss_gpio/mss_gpio.h
new file mode 100644 (file)
index 0000000..b3ecb86
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers/mss_gpio/mss_gpio.h
@@ -0,0 +1,507 @@
+/*******************************************************************************\r
+ * (c) Copyright 2008-2013 Microsemi SoC Products Group.  All rights reserved.\r
+ * \r
+ *  SmartFusion2 Microcontroller Subsystem GPIO bare metal software driver public\r
+ *  API.\r
+ *\r
+ * SVN $Revision: 5487 $\r
+ * SVN $Date: 2013-03-29 15:33:22 +0000 (Fri, 29 Mar 2013) $\r
+ */\r
+\r
+/*=========================================================================*//**\r
+  @mainpage SmartFusion2 MSS GPIO Bare Metal Driver.\r
+\r
+  @section intro_sec Introduction\r
+  The SmartFusion2 Microcontroller Subsystem (MSS) includes a block of 32 general\r
+  purpose input/outputs (GPIO).\r
+  This software driver provides a set of functions for controlling the MSS GPIO\r
+  block as part of a bare metal system where no operating system is available.\r
+  This driver can be adapted for use as part of an operating system but the\r
+  implementation of the adaptation layer between this driver and the operating\r
+  system's driver model is outside the scope of this driver.\r
+  \r
+  @section hw_dependencies Hardware Flow Dependencies\r
+  The configuration of all features of the MSS GPIOs is covered by this driver\r
+  with the exception of the SmartFusion2 IOMUX configuration. SmartFusion2\r
+  allows multiple non-concurrent uses of some external pins through IOMUX\r
+  configuration. This feature allows optimization of external pin usage by\r
+  assigning external pins for use by either the microcontroller subsystem or the\r
+  FPGA fabric. The MSS GPIOs share SmartFusion2 device external pins with the\r
+  FPGA fabric and with other MSS peripherals via an IOMUX. The MSS GPIO ports\r
+  can alternatively be routed to the FPGA fabric through an IOMUX. \r
+  The IOMUXs are configured using the SmartFusion2 MSS configurator tool. You\r
+  must ensure that the MSS GPIOs are enabled and configured in the SmartFusion2\r
+  MSS configurator if you wish to use them. For more information on IOMUXs,\r
+  refer to the IOMUX section of the SmartFusion2 Microcontroller Subsystem (MSS)\r
+  User’s Guide.\r
+  The base address, register addresses and interrupt number assignment for the\r
+  MSS GPIO block are defined as constants in the SmartFusion2 CMSIS HAL. You\r
+  must ensure that the latest SmartFusion2 CMSIS HAL is included in the project\r
+  settings of the software tool chain used to build your project and that it is\r
+  generated into your project.\r
+  \r
+  @section theory_op Theory of Operation\r
+  The MSS GPIO driver functions are grouped into the following categories:\r
+    - Initialization\r
+    - Configuration\r
+    - Reading and setting GPIO state\r
+    - Interrupt control\r
+    \r
+  Initialization\r
+  The MSS GPIO driver is initialized through a call to the MSS_GPIO_init()\r
+  function. The MSS_GPIO_init() function must be called before any other MSS\r
+  GPIO driver functions can be called.\r
+  \r
+  Configuration\r
+  Each GPIO port is individually configured through a call to the\r
+  MSS_GPIO_config() function. Configuration includes deciding if a GPIO port\r
+  will be used as an input, an output or both. GPIO ports configured as inputs\r
+  can be further configured to generate interrupts based on the input's state.\r
+  Interrupts can be level or edge sensitive.\r
+  \r
+  Reading and Setting GPIO State\r
+  The state of the GPIO ports can be read and set using the following functions:\r
+    - MSS_GPIO_get_inputs()\r
+    - MSS_GPIO_get_outputs()\r
+    - MSS_GPIO_set_outputs()\r
+    - MSS_GPIO_set_output()\r
+    - MSS_GPIO_drive_inout()\r
+  \r
+  Interrupt Control\r
+  Interrupts generated by GPIO ports configured as inputs are controlled using\r
+  the following functions:\r
+    - MSS_GPIO_enable_irq()\r
+    - MSS_GPIO_disable_irq()\r
+    - MSS_GPIO_clear_irq()\r
+  \r
+ *//*=========================================================================*/\r
+#ifndef MSS_GPIO_H_\r
+#define MSS_GPIO_H_\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif \r
+\r
+#include "../../CMSIS/m2sxxx.h"\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+  The mss_gpio_id_t enumeration is used to identify individual GPIO ports as an\r
+  argument to functions:\r
+    - MSS_GPIO_config()\r
+    - MSS_GPIO_set_output() and MSS_GPIO_drive_inout()\r
+    - MSS_GPIO_enable_irq(), MSS_GPIO_disable_irq() and MSS_GPIO_clear_irq()\r
+ */\r
+typedef enum __mss_gpio_id_t\r
+{\r
+    MSS_GPIO_0 = 0,\r
+    MSS_GPIO_1 = 1,\r
+    MSS_GPIO_2 = 2,\r
+    MSS_GPIO_3 = 3,\r
+    MSS_GPIO_4 = 4,\r
+    MSS_GPIO_5 = 5,\r
+    MSS_GPIO_6 = 6,\r
+    MSS_GPIO_7 = 7,\r
+    MSS_GPIO_8 = 8,\r
+    MSS_GPIO_9 = 9,\r
+    MSS_GPIO_10 = 10,\r
+    MSS_GPIO_11 = 11,\r
+    MSS_GPIO_12 = 12,\r
+    MSS_GPIO_13 = 13,\r
+    MSS_GPIO_14 = 14,\r
+    MSS_GPIO_15 = 15,\r
+    MSS_GPIO_16 = 16,\r
+    MSS_GPIO_17 = 17,\r
+    MSS_GPIO_18 = 18,\r
+    MSS_GPIO_19 = 19,\r
+    MSS_GPIO_20 = 20,\r
+    MSS_GPIO_21 = 21,\r
+    MSS_GPIO_22 = 22,\r
+    MSS_GPIO_23 = 23,\r
+    MSS_GPIO_24 = 24,\r
+    MSS_GPIO_25 = 25,\r
+    MSS_GPIO_26 = 26,\r
+    MSS_GPIO_27 = 27,\r
+    MSS_GPIO_28 = 28,\r
+    MSS_GPIO_29 = 29,\r
+    MSS_GPIO_30 = 30,\r
+    MSS_GPIO_31 = 31\r
+} mss_gpio_id_t;\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+  These constant definitions are used as an argument to the\r
+  MSS_GPIO_set_outputs() function to identify GPIO ports. A logical OR of these\r
+  constants can be used to specify multiple GPIO ports.\r
+  These definitions can also be used to identify GPIO ports through logical\r
+  operations on the return value of the MSS_GPIO_get_inputs() function.\r
+ */\r
+#define MSS_GPIO_0_MASK         0x00000001uL\r
+#define MSS_GPIO_1_MASK         0x00000002uL\r
+#define MSS_GPIO_2_MASK         0x00000004uL\r
+#define MSS_GPIO_3_MASK         0x00000008uL\r
+#define MSS_GPIO_4_MASK         0x00000010uL\r
+#define MSS_GPIO_5_MASK         0x00000020uL\r
+#define MSS_GPIO_6_MASK         0x00000040uL\r
+#define MSS_GPIO_7_MASK         0x00000080uL\r
+#define MSS_GPIO_8_MASK         0x00000100uL\r
+#define MSS_GPIO_9_MASK         0x00000200uL\r
+#define MSS_GPIO_10_MASK        0x00000400uL\r
+#define MSS_GPIO_11_MASK        0x00000800uL\r
+#define MSS_GPIO_12_MASK        0x00001000uL\r
+#define MSS_GPIO_13_MASK        0x00002000uL\r
+#define MSS_GPIO_14_MASK        0x00004000uL\r
+#define MSS_GPIO_15_MASK        0x00008000uL\r
+#define MSS_GPIO_16_MASK        0x00010000uL\r
+#define MSS_GPIO_17_MASK        0x00020000uL\r
+#define MSS_GPIO_18_MASK        0x00040000uL\r
+#define MSS_GPIO_19_MASK        0x00080000uL\r
+#define MSS_GPIO_20_MASK        0x00100000uL\r
+#define MSS_GPIO_21_MASK        0x00200000uL\r
+#define MSS_GPIO_22_MASK        0x00400000uL\r
+#define MSS_GPIO_23_MASK        0x00800000uL\r
+#define MSS_GPIO_24_MASK        0x01000000uL\r
+#define MSS_GPIO_25_MASK        0x02000000uL\r
+#define MSS_GPIO_26_MASK        0x04000000uL\r
+#define MSS_GPIO_27_MASK        0x08000000uL\r
+#define MSS_GPIO_28_MASK        0x10000000uL\r
+#define MSS_GPIO_29_MASK        0x20000000uL\r
+#define MSS_GPIO_30_MASK        0x40000000uL\r
+#define MSS_GPIO_31_MASK        0x80000000uL\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+  These constant definitions are used as an argument to the MSS_GPIO_config()\r
+  function to specify the I/O mode of each GPIO port.\r
+ */\r
+#define MSS_GPIO_INPUT_MODE              0x0000000002uL\r
+#define MSS_GPIO_OUTPUT_MODE             0x0000000005uL\r
+#define MSS_GPIO_INOUT_MODE              0x0000000003uL\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+  These constant definitions are used as an argument to the MSS_GPIO_config()\r
+  function to specify the interrupt mode of each GPIO port.\r
+ */\r
+#define MSS_GPIO_IRQ_LEVEL_HIGH           0x0000000000uL\r
+#define MSS_GPIO_IRQ_LEVEL_LOW            0x0000000020uL\r
+#define MSS_GPIO_IRQ_EDGE_POSITIVE        0x0000000040uL\r
+#define MSS_GPIO_IRQ_EDGE_NEGATIVE        0x0000000060uL\r
+#define MSS_GPIO_IRQ_EDGE_BOTH            0x0000000080uL\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+  The mss_gpio_inout_state_t enumeration is used to specify the output state of\r
+  an INOUT GPIO port as an argument to the MSS_GPIO_drive_inout() function.\r
+ */\r
+typedef enum mss_gpio_inout_state\r
+{\r
+    MSS_GPIO_DRIVE_LOW = 0,\r
+    MSS_GPIO_DRIVE_HIGH,\r
+    MSS_GPIO_HIGH_Z\r
+} mss_gpio_inout_state_t;\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+  The MSS_GPIO_init() function initializes the SmartFusion2 MSS GPIO block. It\r
+  resets the MSS GPIO hardware block and it also clears any pending MSS GPIO\r
+  interrupts in the ARM Cortex-M3 interrupt controller. When the function exits,\r
+  it takes the MSS GPIO block out of reset.\r
+  \r
+   @param\r
+    This function has no parameters.\r
+    \r
+   @return\r
+    This function does not return a value.\r
+ */\r
+void MSS_GPIO_init( void );\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+  The MSS_GPIO_config() function is used to configure an individual GPIO port.\r
+ \r
+  @param port_id\r
+    The port_id parameter identifies the GPIO port to be configured. An\r
+    enumeration item of the form MSS_GPIO_n, where n is the number of the GPIO\r
+    port, is used to identify the GPIO port. For example, MSS_GPIO_0 identifies\r
+    the first GPIO port and MSS_GPIO_31 is the last one.\r
+    \r
+  @param config\r
+    The config parameter specifies the configuration to be applied to the GPIO\r
+    port identified by the port_id parameter. It is a logical OR of the required\r
+    I/O mode and the required interrupt mode. The interrupt mode is not relevant\r
+    if the GPIO is configured as an output only.\r
+       These I/O mode constants are allowed:\r
+           - MSS_GPIO_INPUT_MODE\r
+           - MSS_GPIO_OUTPUT_MODE\r
+           - MSS_GPIO_INOUT_MODE\r
+       These interrupt mode constants are allowed:\r
+           - MSS_GPIO_IRQ_LEVEL_HIGH\r
+           - MSS_GPIO_IRQ_LEVEL_LOW\r
+           - MSS_GPIO_IRQ_EDGE_POSITIVE\r
+           - MSS_GPIO_IRQ_EDGE_NEGATIVE\r
+           - MSS_GPIO_IRQ_EDGE_BOTH\r
+  \r
+   @return\r
+    none.\r
+\r
+  Example:\r
+  The following call will configure GPIO 4 as an input generating interrupts on\r
+  a Low to High transition of the input:\r
+  @code\r
+  MSS_GPIO_config( MSS_GPIO_4, MSS_GPIO_INPUT_MODE | MSS_GPIO_IRQ_EDGE_POSITIVE );\r
+  @endcode\r
+ */\r
+void MSS_GPIO_config\r
+(\r
+    mss_gpio_id_t port_id,\r
+    uint32_t config\r
+);\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+  The MSS_GPIO_set_outputs() function is used to set the state of all GPIO ports\r
+  configured as outputs.\r
+ \r
+  @param value\r
+    The value parameter specifies the state of the GPIO ports configured as\r
+    outputs. It is a bit mask of the form (MSS_GPIO_n_MASK | MSS_GPIO_m_MASK)\r
+    where n and m are numbers identifying GPIOs. For example, (MSS_GPIO_0_MASK |\r
+    MSS_GPIO_1_MASK | MSS_GPIO_2_MASK ) specifies that the first, second and\r
+    third GPIO outputs must be set High and all other GPIO outputs set Low. The\r
+    driver provides 32 mask constants, MSS_GPIO_0_MASK to MSS_GPIO_31_MASK\r
+    inclusive, for this purpose.\r
+  \r
+  @return\r
+    none.\r
+\r
+  Example 1:\r
+    Set GPIOs outputs 0 and 8 high and all other GPIO outputs low.\r
+    @code\r
+        MSS_GPIO_set_outputs( MSS_GPIO_0_MASK | MSS_GPIO_8_MASK );\r
+    @endcode\r
+\r
+  Example 2:\r
+    Set GPIOs outputs 2 and 4 low without affecting other GPIO outputs.\r
+    @code\r
+        uint32_t gpio_outputs;\r
+        gpio_outputs = MSS_GPIO_get_outputs();\r
+        gpio_outputs &= ~( MSS_GPIO_2_MASK | MSS_GPIO_4_MASK );\r
+        MSS_GPIO_set_outputs(  gpio_outputs );\r
+    @endcode\r
+\r
+  @see MSS_GPIO_get_outputs()\r
+ */\r
+static __INLINE void\r
+MSS_GPIO_set_outputs\r
+(\r
+   uint32_t value\r
+)\r
+{\r
+    GPIO->GPIO_OUT = value;\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+  The MSS_GPIO_set_output() function is used to set the state of a single GPIO\r
+  port configured as an output.\r
+  Note: Using bit-band writes might be a better option than this function for\r
+        performance critical applications where the application code is not\r
+        intended to be ported to a processor other than the ARM Cortex-M3 in\r
+        SmartFusion2. The bit-band write equivalent to this function would be:\r
+            GPIO_BITBAND->GPIO_OUT[port_id] = (uint32_t)value;\r
+ \r
+  @param port_id\r
+    The port_id parameter identifies the GPIO port that is to have its output\r
+    set. An enumeration item of the form MSS_GPIO_n, where n is the number of\r
+    the GPIO port, is used to identify the GPIO port. For example, MSS_GPIO_0\r
+    identifies the first GPIO port and MSS_GPIO_31 is the last one.\r
+  \r
+  @param value\r
+    The value parameter specifies the desired state for the GPIO output. A value\r
+    of 0 will set the output Low and a value of 1 will set the output High.\r
+  \r
+  @return\r
+    This function does not return a value.\r
+    \r
+  Example:\r
+  The following call will set GPIO output 12 High, leaving all other GPIO\r
+  outputs unaffected:\r
+  @code\r
+    _GPIO_set_output(MSS_GPIO_12, 1);\r
+  @endcode\r
+ */\r
+void MSS_GPIO_set_output\r
+(\r
+    mss_gpio_id_t       port_id,\r
+    uint8_t             value\r
+);\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+  The MSS_GPIO_get_inputs() function is used to read the current state all GPIO\r
+  ports configured as inputs.\r
+ \r
+  @return\r
+    This function returns a 32-bit unsigned integer where each bit represents\r
+    the state of a GPIO input. The least significant bit represents the state of\r
+    GPIO input 0 and the most significant bit the state of GPIO input 31.\r
+\r
+  Example:\r
+    Read and assign the current state of the GPIO outputs to a variable.\r
+    @code\r
+        uint32_t gpio_inputs;\r
+        gpio_inputs = MSS_GPIO_get_inputs();\r
+    @endcode\r
+ */\r
+static __INLINE uint32_t\r
+MSS_GPIO_get_inputs( void )\r
+{\r
+    return GPIO->GPIO_IN;\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+  The MSS_GPIO_get_outputs() function is used to read the current state all GPIO\r
+  ports configured as outputs.\r
+ \r
+  @return\r
+     This function returns a 32-bit unsigned integer where each bit represents\r
+     the state of a GPIO output. The least significant bit represents the state\r
+     of GPIO output 0 and the most significant bit the state of GPIO output 31.\r
+\r
+  Example:\r
+    Read and assign the current state of the GPIO outputs to a variable.\r
+    @code\r
+        uint32_t gpio_outputs;\r
+        gpio_outputs = MSS_GPIO_get_outputs();\r
+    @endcode\r
+ */\r
+static __INLINE uint32_t\r
+MSS_GPIO_get_outputs( void )\r
+{\r
+    return GPIO->GPIO_OUT;\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+  The MSS_GPIO_drive_inout() function is used to set the output state of a\r
+  single GPIO port configured as an INOUT. An INOUT GPIO can be in one of three\r
+  states:\r
+    - High\r
+    - Low\r
+    - High impedance\r
+  An INOUT output would typically be used where several devices can drive the\r
+  state of a shared signal line. The High and Low states are equivalent to the\r
+  High and Low states of a GPIO configured as an output. The High impedance\r
+  state is used to prevent the GPIO from driving its output state onto the\r
+  signal line, while at the same time allowing the input state of the GPIO to\r
+  be read.\r
+  \r
+  @param port_id\r
+    The port_id parameter identifies the GPIO port for which you want to change\r
+    the output state. An enumeration item of the form MSS_GPIO_n, where n is the\r
+    number of the GPIO port, is used to identify the GPIO port. For example,\r
+    MSS_GPIO_0 identifies the first GPIO port and MSS_GPIO_31 is the last one.\r
+    \r
+  @param inout_state\r
+    The inout_state parameter specifies the state of the GPIO port identified by\r
+    the port_id parameter. Allowed values of type mss_gpio_inout_state_t are as\r
+    follows:\r
+        - MSS_GPIO_DRIVE_HIGH\r
+        - MSS_GPIO_DRIVE_LOW\r
+        - MSS_GPIO_HIGH_Z  (High impedance)\r
+        \r
+  @return\r
+    This function does not return a value.\r
+\r
+  Example:\r
+    The call to MSS_GPIO_drive_inout() below will set the GPIO 7 output to the\r
+    high impedance state.\r
+    @code\r
+    MSS_GPIO_drive_inout( MSS_GPIO_7, MSS_GPIO_HIGH_Z );\r
+    @endcode\r
+ */\r
+void MSS_GPIO_drive_inout\r
+(\r
+    mss_gpio_id_t           port_id,\r
+    mss_gpio_inout_state_t  inout_state\r
+);\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+  The MSS_GPIO_enable_irq() function is used to enable interrupt generation for\r
+  the specified GPIO input. Interrupts are generated based on the state of the\r
+  GPIO input and the interrupt mode configured for it by MSS_GPIO_config().\r
+ \r
+  @param port_id\r
+    The port_id parameter identifies the GPIO port for which you want to enable\r
+    interrupt generation. An enumeration item of the form MSS_GPIO_n, where n is\r
+    the number of the GPIO port, is used to identify the GPIO port. For example,\r
+    MSS_GPIO_0 identifies the first GPIO port and MSS_GPIO_31 is the last one.\r
+    \r
+  @return\r
+    This function does not return a value.\r
+\r
+  Example:\r
+    The call to MSS_GPIO_enable_irq() below will allow GPIO 8 to generate\r
+    interrupts.\r
+    @code\r
+    MSS_GPIO_enable_irq( MSS_GPIO_8 );\r
+    @endcode\r
+ */\r
+void MSS_GPIO_enable_irq\r
+(\r
+    mss_gpio_id_t port_id\r
+);\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+  The MSS_GPIO_disable_irq() function is used to disable interrupt generation\r
+  for the specified GPIO input.\r
+ \r
+  @param port_id\r
+    The port_id parameter identifies the GPIO port for which you want to disable\r
+    interrupt generation. An enumeration item of the form MSS_GPIO_n, where n is\r
+    the number of the GPIO port, is used to identify the GPIO port. For example,\r
+    MSS_GPIO_0 identifies the first GPIO port and MSS_GPIO_31 is the last one.\r
+ \r
+  @return\r
+    This function does not return a value.\r
+\r
+  Example:\r
+    The call to MSS_GPIO_disable_irq() below will prevent GPIO 8 from generating\r
+    interrupts.\r
+    @code\r
+    MSS_GPIO_disable_irq( MSS_GPIO_8 );\r
+    @endcode\r
+ */\r
+void MSS_GPIO_disable_irq\r
+(\r
+    mss_gpio_id_t port_id\r
+);\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+  The MSS_GPIO_clear_irq() function is used to clear a pending interrupt from\r
+  the specified GPIO input.\r
+  Note: The MSS_GPIO_clear_irq() function must be called as part of any GPIO\r
+        interrupt service routine (ISR) in order to prevent the same interrupt\r
+        event retriggering a call to the GPIO ISR.\r
+ \r
+  @param port_id\r
+    The port_id parameter identifies the GPIO port for which you want to clear\r
+    the interrupt. An enumeration item of the form MSS_GPIO_n, where n is the\r
+    number of the GPIO port, is used to identify the GPIO port. For example,\r
+    MSS_GPIO_0 identifies the first GPIO port and MSS_GPIO_31 is the last one.\r
+    \r
+  @return\r
+    none.\r
+\r
+  Example:\r
+    The example below demonstrates the use of the MSS_GPIO_clear_irq() function\r
+    as part of the GPIO 9 interrupt service routine.  \r
+    @code\r
+    void GPIO9_IRQHandler( void )\r
+    {\r
+        do_interrupt_processing();\r
+        \r
+        MSS_GPIO_clear_irq( MSS_GPIO_9 );\r
+    }\r
+    @endcode\r
+ */\r
+void MSS_GPIO_clear_irq\r
+(\r
+    mss_gpio_id_t port_id\r
+);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* MSS_GPIO_H_ */\r
diff --git a/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers/mss_hpdma/mss_hpdma.c b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers/mss_hpdma/mss_hpdma.c
new file mode 100644 (file)
index 0000000..f43eadb
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers/mss_hpdma/mss_hpdma.c
@@ -0,0 +1,344 @@
+/*******************************************************************************\r
+ * (c) Copyright 2010-2013 Microsemi SoC Products Group.  All rights reserved.\r
+ * \r
+ * SmartFusion2 MSS HPDMA bare metal driver implementation.\r
+ *\r
+ * SVN $Revision: 5148 $\r
+ * SVN $Date: 2013-02-27 16:42:01 +0000 (Wed, 27 Feb 2013) $\r
+ */\r
+#include "mss_hpdma.h"\r
+\r
+/*==============================================================================\r
+ * Design Notes\r
+ *------------------------------------------------------------------------------\r
+  This SmartFusion2 MSS HPDMA driver only makes use of the first HPDMA\r
+  descriptor. The rationale for this choice is that the pause and clear bits of\r
+  each individual descriptor have undocumented side effects to the other\r
+  descriptors in the HPDMA hardware block. This prevents independent operations\r
+  of the descriptors in particular when it comes to error handling where error\r
+  recovery requires clearing a descriptor. An error on one descriptor would\r
+  result in aborting transfers on the other descriptors. Likewise, it is not\r
+  possible to pause individual descriptors. Setting the pause bit in one\r
+  descriptor results in all descriptors being paused.\r
+ */\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif \r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ * Constants\r
+ */\r
+#define HPDMA_ENABLE    1u\r
+#define HPDMA_DISABLE   0u\r
+#define NULL_HANDLER    ((mss_hpdma_handler_t)0)\r
+\r
+/* 64 K DMA Transfer */\r
+#define MAX_SIZE_PER_DMA_XFR   0x10000u\r
+\r
+#define DESC0       0u\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ * Mask Constants\r
+ */\r
+#define HPDMA_SOFT_RESET            0x00020000u\r
+#define HPDMA_XFR_SIZE_MASK         0xFFFF0000u\r
+\r
+#define HPDMACR_XFR_CMP_INT_MASK    0x00100000u\r
+#define HPDMACR_XFR_ERR_INT_MASK    0x00200000u\r
+#define HPDMACR_NON_WORD_INT_MASK   0x00400000u\r
+\r
+#define HPDMACR_ALL_IRQ_ENABLE_MASK (HPDMACR_XFR_CMP_INT_MASK | HPDMACR_XFR_ERR_INT_MASK | HPDMACR_NON_WORD_INT_MASK)\r
+\r
+#define HPDMAICR_CLEAR_ALL_IRQ      0x000000FFu\r
+\r
+#define HPDMAEDR_DCP_ERR_MASK           0x00000100u\r
+\r
+#define HPDMAEDR_NON_WORD_ERR_MASK      0x00001000u\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+  Current transfer state information.\r
+ */\r
+typedef struct hpdma_xfer_info\r
+{\r
+    hpdma_status_t          state;\r
+    mss_hpdma_handler_t     completion_handler;\r
+    uint32_t                src_addr;\r
+    uint32_t                des_addr;\r
+    uint32_t                xfr_size;\r
+    uint8_t                 xfr_dir;\r
+} hpdma_xfer_info_t;\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+  Current transfer state information.\r
+ */\r
+static hpdma_xfer_info_t g_transfer;\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+  Interrupt service routines function prototypes.\r
+  The name of these interrupt service routines must match the name of the ISRs\r
+  defined in startup_m2sxxx.s distributed as part of the SmartFusion2 CMSIS.\r
+ */\r
+#if defined(__GNUC__)\r
+__attribute__((__interrupt__)) void HPDMA_Complete_IRQHandler(void);\r
+#else\r
+void HPDMA_Complete_IRQHandler(void);\r
+#endif \r
+\r
+#if defined(__GNUC__)\r
+__attribute__((__interrupt__)) void HPDMA_Error_IRQHandler(void);\r
+#else\r
+void HPDMA_Error_IRQHandler(void);\r
+#endif \r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ * See "mss_hpdma.h" for details of how to use this function.\r
+ */\r
+void\r
+MSS_HPDMA_init\r
+(\r
+    void\r
+)\r
+{\r
+    /* Reset HPDMA block. */\r
+    SYSREG->SOFT_RST_CR |= HPDMA_SOFT_RESET;\r
+\r
+    /* Take HPDMA controller out of reset. */\r
+    SYSREG->SOFT_RST_CR &= ~HPDMA_SOFT_RESET;\r
+\r
+    /* Initialize data structures. */\r
+    g_transfer.xfr_size = 0u;\r
+    g_transfer.completion_handler = NULL_HANDLER;\r
+    g_transfer.state = HPDMA_COMPLETED;\r
+    \r
+    /* Disable Interrupt. */\r
+    HPDMA->Descriptor[DESC0].HPDMACR_REG &= ~HPDMACR_ALL_IRQ_ENABLE_MASK;\r
+\r
+    /* Clear any previously pended MSS HPDMA interrupt. */\r
+    NVIC_ClearPendingIRQ(HPDMA_Error_IRQn);\r
+    NVIC_ClearPendingIRQ(HPDMA_Complete_IRQn);\r
+    \r
+    /* Clear all interrupts. */\r
+    HPDMA->HPDMAICR_REG = HPDMAICR_CLEAR_ALL_IRQ;\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ * See "mss_hpdma.h" for details of how to use this function.\r
+ */\r
+void\r
+MSS_HPDMA_start\r
+(\r
+    uint32_t src_addr,\r
+    uint32_t dest_addr,\r
+    uint32_t transfer_size,\r
+    uint8_t transfer_dir\r
+)\r
+{\r
+    /* Pause transfer. */\r
+    HPDMA_BITBAND->Descriptor[DESC0].HPDMACR_DCP_PAUSE = HPDMA_ENABLE;\r
+    \r
+    /*\r
+     * Disable all interrupts for the current descriptor. Treat this function as a\r
+     * critical section. Pausing the descriptor transfer is not sufficient in case\r
+     * of non-aligned errors.\r
+     */\r
+    HPDMA->Descriptor[DESC0].HPDMACR_REG &= ~HPDMACR_ALL_IRQ_ENABLE_MASK;\r
+    \r
+    /* Set descriptor transfer direction */\r
+    HPDMA_BITBAND->Descriptor[DESC0].HPDMACR_DCP_XFR_DIR = transfer_dir;\r
+\r
+    /* Store Source and destination Address */\r
+    HPDMA->Descriptor[DESC0].HPDMASAR_REG = src_addr;\r
+    HPDMA->Descriptor[DESC0].HPDMADAR_REG = dest_addr;\r
+\r
+    /* Set the transfer size to 64K */\r
+    HPDMA->Descriptor[DESC0].HPDMACR_REG &= HPDMA_XFR_SIZE_MASK;\r
+\r
+    g_transfer.state = HPDMA_IN_PROGRESS;\r
+    if(transfer_size <= MAX_SIZE_PER_DMA_XFR)\r
+    {\r
+        /* Set descriptor transfer size */\r
+        HPDMA->Descriptor[DESC0].HPDMACR_REG |= (uint16_t)transfer_size;\r
+        g_transfer.xfr_size = 0u;\r
+    }\r
+    else\r
+    {\r
+        g_transfer.xfr_size = transfer_size - MAX_SIZE_PER_DMA_XFR;\r
+        g_transfer.des_addr = dest_addr + MAX_SIZE_PER_DMA_XFR;\r
+        g_transfer.src_addr = src_addr + MAX_SIZE_PER_DMA_XFR;\r
+        g_transfer.xfr_dir = transfer_dir;\r
+    }\r
+\r
+    /* Enable interrupts for the requested descriptor. */\r
+    HPDMA->Descriptor[DESC0].HPDMACR_REG |= HPDMACR_ALL_IRQ_ENABLE_MASK;\r
+    NVIC_EnableIRQ(HPDMA_Complete_IRQn);\r
+    NVIC_EnableIRQ(HPDMA_Error_IRQn);\r
+    \r
+    /* Set valid descriptor to start transfer */\r
+    HPDMA_BITBAND->Descriptor[DESC0].HPDMACR_DCP_VALID = HPDMA_ENABLE;\r
+\r
+    /* Start transfer */\r
+    HPDMA_BITBAND->Descriptor[DESC0].HPDMACR_DCP_PAUSE = HPDMA_DISABLE;\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ * See "mss_hpdma.h" for details of how to use this function.\r
+ */\r
+void\r
+MSS_HPDMA_pause\r
+(\r
+    void\r
+)\r
+{\r
+    /* Pause transfer */\r
+    HPDMA_BITBAND->Descriptor[DESC0].HPDMACR_DCP_PAUSE = HPDMA_ENABLE;\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ * See "mss_hpdma.h" for details of how to use this function.\r
+ */\r
+void\r
+MSS_HPDMA_resume\r
+(\r
+    void\r
+)\r
+{\r
+    /* Resume transfer */\r
+    HPDMA_BITBAND->Descriptor[DESC0].HPDMACR_DCP_PAUSE = HPDMA_DISABLE;\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ * See "mss_hpdma.h" for details of how to use this function.\r
+ */\r
+void\r
+MSS_HPDMA_abort\r
+(\r
+    void\r
+)\r
+{\r
+    HPDMA_BITBAND->Descriptor[DESC0].HPDMACR_DCP_CLR = HPDMA_ENABLE;\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ * See "mss_hpdma.h" for details of how to use this function.\r
+ */\r
+hpdma_status_t\r
+MSS_HPDMA_get_transfer_status\r
+(\r
+    void\r
+)\r
+{\r
+    return g_transfer.state;\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ * See "mss_hpdma.h" for details of how to use this function.\r
+ */\r
+void MSS_HPDMA_set_handler\r
+(\r
+    mss_hpdma_handler_t handler\r
+)\r
+{\r
+    if(handler == NULL_HANDLER)\r
+    {\r
+        g_transfer.completion_handler = NULL_HANDLER;\r
+    }\r
+    else\r
+    {\r
+        g_transfer.completion_handler = handler;\r
+    }\r
+}\r
+\r
+/*------------------------------------------------------------------------------\r
+  HPDMA Transfer complete service routine.\r
+  This function will be called as a result of any descriptor transfer\r
+  is completed by HPDMA controller .\r
+ */\r
+#if defined(__GNUC__)\r
+__attribute__((__interrupt__)) void HPDMA_Complete_IRQHandler(void)\r
+#else\r
+void HPDMA_Complete_IRQHandler(void)\r
+#endif \r
+{\r
+    /* Clear interrupt */\r
+    HPDMA_BITBAND->HPDMAICR_CLR_XFR_INT[DESC0] = HPDMA_ENABLE;\r
+\r
+    if(g_transfer.xfr_size > 0u)\r
+    {\r
+        MSS_HPDMA_start(g_transfer.src_addr,\r
+                        g_transfer.des_addr,\r
+                        g_transfer.xfr_size,\r
+                        g_transfer.xfr_dir);\r
+    }\r
+    else\r
+    {\r
+        g_transfer.state = HPDMA_COMPLETED;\r
+        if(g_transfer.completion_handler != NULL_HANDLER)\r
+        {\r
+            (*(g_transfer.completion_handler))(HPDMA_COMPLETED);\r
+        }\r
+    }\r
+}\r
+\r
+/*------------------------------------------------------------------------------\r
+  HPDMA Transfer Error service routine.\r
+  This function will be called as a result of any descriptor transfer\r
+  has an error condition or it there is non word transfer size error.\r
+ */\r
+#if defined(__GNUC__)\r
+__attribute__((__interrupt__)) void HPDMA_Error_IRQHandler(void)\r
+#else\r
+void HPDMA_Error_IRQHandler(void)\r
+#endif \r
+{\r
+    uint32_t error_bits;\r
+\r
+    /*\r
+     * Handle source/destination errors.\r
+     */\r
+    error_bits = HPDMA->HPDMAEDR_REG & HPDMAEDR_DCP_ERR_MASK;\r
+    if(error_bits != 0u)\r
+    {\r
+        if(g_transfer.completion_handler != NULL_HANDLER)\r
+        {\r
+            if(HPDMA_BITBAND->Descriptor[DESC0].HPDMASR_DCP_SERR)\r
+            {\r
+                g_transfer.state = HPDMA_SOURCE_ERROR;\r
+                (*(g_transfer.completion_handler))(HPDMA_SOURCE_ERROR);\r
+            }\r
+            \r
+            if(HPDMA_BITBAND->Descriptor[DESC0].HPDMASR_DCP_DERR)\r
+            {\r
+                g_transfer.state = HPDMA_DESTINATION_ERROR;\r
+                (*(g_transfer.completion_handler))(HPDMA_DESTINATION_ERROR);\r
+            }\r
+        }\r
+        /* Abort transfer. */\r
+        HPDMA_BITBAND->Descriptor[DESC0].HPDMACR_DCP_CLR = HPDMA_ENABLE;\r
+        /* Clear interrupt. */\r
+        HPDMA_BITBAND->HPDMAICR_CLR_XFR_INT[DESC0] = HPDMA_ENABLE;\r
+    }\r
+    \r
+    /*\r
+     * Handle non word aligned errors.\r
+     */\r
+    error_bits = HPDMA->HPDMAEDR_REG & HPDMAEDR_NON_WORD_ERR_MASK;\r
+    if(error_bits != 0u)\r
+    {\r
+        g_transfer.state = HPDMA_WORD_ALIGN_ERROR;\r
+        /* Call handler. */\r
+        if(g_transfer.completion_handler != NULL_HANDLER)\r
+        {\r
+            (*(g_transfer.completion_handler))(HPDMA_WORD_ALIGN_ERROR);\r
+        }\r
+        /* Abort transfer. */\r
+        HPDMA_BITBAND->Descriptor[DESC0].HPDMACR_DCP_CLR = HPDMA_ENABLE;\r
+        /* Clear interrupt. */\r
+        HPDMA_BITBAND->HPDMAICR_NON_WORD_INT[DESC0] = HPDMA_ENABLE;\r
+    }\r
+}\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
diff --git a/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers/mss_hpdma/mss_hpdma.h b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers/mss_hpdma/mss_hpdma.h
new file mode 100644 (file)
index 0000000..636bc44
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers/mss_hpdma/mss_hpdma.h
@@ -0,0 +1,361 @@
+/*******************************************************************************\r
+ * (c) Copyright 2010-2013 Microsemi SoC Products Group.  All rights reserved.\r
+ * \r
+ *  SmartFusion2 MSS HPDMA bare metal software driver public API.\r
+ *\r
+ * SVN $Revision: 5583 $\r
+ * SVN $Date: 2013-04-04 12:29:18 +0100 (Thu, 04 Apr 2013) $\r
+ */\r
+\r
+/*=========================================================================*//**\r
+  @mainpage SmartFusion2 MSS HPDMA Bare Metal Driver.\r
+\r
+  @section intro_sec Introduction\r
+  The SmartFusion2 Microcontroller Subsystem (MSS) includes a High Performance\r
+  Direct Memory Access (HPDMA) controller which performs fast data transfer\r
+  between any MSS memory connected to the AHB bus matrix and MSS DDR-Bridge\r
+  memory. This software driver provides a set of functions for controlling the\r
+  MSS HPDMA as part of a bare metal system where no operating system is\r
+  available. The driver can be adapted for use as part of an operating system\r
+  but the implementation of the adaptation layer between the driver and the\r
+  operating system's driver model is outside the scope of the driver.\r
+  \r
+  @section hw_dependencies Hardware Flow Dependencies\r
+  The configuration of all features of the MSS HPDMA is covered by this driver.\r
+  There are no dependencies on the hardware flow when configuring the MSS HPDMA.\r
+  The base address, register addresses and interrupt number assignment for the\r
+  MSS HPDMA blocks are defined as constants in the SmartFusion2 CMSIS HAL. You\r
+  must ensure that the latest SmartFusion2 CMSIS HAL is included in the project\r
+  settings of the software tool chain used to build your project and that it is\r
+  generated into your project.\r
+  \r
+  @section theory_op Theory of Operation\r
+  The MSS HPDMA driver functions are grouped into the following categories:\r
+    - Initialization of the MSS HPDMA driver and hardware\r
+    - Data transfer control \r
+    - Data transfer status\r
+    - Interrupt handling\r
+    \r
+  Initialization\r
+  The MSS HPDMA driver is initialized through a call to the MSS_HPDMA_init()\r
+  function. The MSS_HPDMA_init() function must be called before any other MSS\r
+  HPDMA driver functions can be called.\r
+  \r
+  Data Transfer Control\r
+  The driver provides the following functions to control HPDMA data transfers:\r
+    - MSS_HPDMA_start()  \96 This function starts a HPDMA data transfer. You must\r
+                           provide the source and destination addresses along\r
+                           with transfer size and transfer direction.\r
+    - MSS_HPDMA_pause()  \96 This function pauses the HPDMA transfer that is\r
+                           currently in progress.\r
+    - MSS_HPDMA_resume() \96 This function resumes a HPDMA transfer that was\r
+                           previously paused.\r
+    - MSS_HPDMA_abort()  \96 This function aborts the HPDMA transfer that is\r
+                           currently in progress.\r
+    \r
+  Data Transfer Status\r
+  The status of the HPDMA transfer initiated by the last call to\r
+  MSS_HPDMA_start() can be retrieved using the MSS_HPDMA_get_transfer_status()\r
+  function.\r
+  \r
+  Interrupt Handling\r
+  The MSS_HPDMA_set_handler() function is used to register a handler function\r
+  that will be called by the driver when the HPDMA transfer completes. You must\r
+  create and register a transfer completion handler function to suit your\r
+  application.\r
+\r
+ *//*=========================================================================*/\r
+#ifndef MSS_HPDMA_H_\r
+#define MSS_HPDMA_H_\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif \r
+\r
+#include "../../CMSIS/m2sxxx.h"\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+  The HPDMA_TO_DDR constant is used to specify the data transfer direction. It\r
+  indicates a transfer from memory connected to the AHB bus matrix to MSS\r
+  DDR-Bridge memory. It is used as a parameter by the MSS_HPDMA_start()\r
+  function.\r
+ */\r
+#define HPDMA_TO_DDR        0u\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+  The HPDMA_FROM_DDR constant is used to specify the data transfer direction. It\r
+  indicates a transter from MSS DDR-Bridge memory to memory connected to the AHB\r
+  bus matrix. It is used as a parameter by the MSS_HPDMA_start() function.\r
+ */\r
+#define HPDMA_FROM_DDR      1u\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+  The hpdma_status_t type is used to communicate the status of the HPDMA\r
+  transfer initiated by the most recent call to HPDMA_start(). It indicates if\r
+  a transfer is still currently in progress or the outcome of the latest\r
+  transfer. This type is returned by the MSS_HPDMA_get_transfer_status()\r
+  function and used as parameter to handler functions registered with the MSS\r
+  HPDMA driver by the application.\r
+  \r
+  - HPDMA_IN_PROGRESS       - A HPDMA transfer is taking place.\r
+  - HPDMA_COMPLETED         - The most recent HPDMA transfer initiated by a call\r
+                              to HPDMA_start() has completed successfully.\r
+  - HPDMA_SOURCE_ERROR      - The most recent HPDMA transfer failed because of a\r
+                              problem with the source address passed to\r
+                              HPDMA_start().\r
+  - HPDMA_DESTINATION_ERROR - The most recent HPDMA transfer failed because of a\r
+                              problem with the destination address passed to\r
+                              HPDMA_start().\r
+  - HPDMA_WORD_ALIGN_ERROR  - The most recent HPDMA transfer failed because the\r
+                              transfer size was not word aligned. This means\r
+                              that the transfer size passed to HPDMA_start() was\r
+                              not a multiple of four.\r
+ */\r
+typedef enum\r
+{\r
+    HPDMA_IN_PROGRESS,\r
+    HPDMA_COMPLETED,\r
+    HPDMA_SOURCE_ERROR,\r
+    HPDMA_DESTINATION_ERROR,\r
+    HPDMA_WORD_ALIGN_ERROR\r
+} hpdma_status_t;\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+  This type definition specifies the prototype of a function that can be\r
+  registered with this driver as a HPDMA transfer completion handler function\r
+  through a call to MSS_HPDMA_set_handler(). The HPDMA transfer completion\r
+  handler will be called by the driver when a HPDMA transfer completes. The MSS\r
+  HPDMA driver passes the outcome of the transfer to the completion handler in\r
+  the form of a hpdma_status_t parameter indicating if the transfer was\r
+  successful or the type of error that occurred during the transfer.\r
+ */\r
+typedef void (*mss_hpdma_handler_t)(hpdma_status_t status);\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+  The MSS_HPDMA_init() function initializes the MSS HPDMA driver. It resets the\r
+  HPDMA controller. It clears all pending HPDMA interrupts. It initializes\r
+  internal data structures used by the MSS HPDMA driver. It disables interrupts\r
+  related to HPDMA data transfers.\r
+\r
+  @param\r
+    This function has no parameters.\r
+\r
+  @return\r
+    This function does not return a value.\r
+ */\r
+void\r
+MSS_HPDMA_init\r
+(\r
+    void\r
+);\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+  The MSS_HPDMA_start() function starts a HPDMA data transfer. Its parameters\r
+  specify the source and destination addresses of the transfer as well as its\r
+  size and direction. HPDMA data transfers always use DDR memory as the source\r
+  or destination of the transfer. The HPDMA controller transfers data in 32-bit\r
+  chunks located on 32-bit word aligned address boundaries.\r
+\r
+  @param src_addr\r
+    The parameter src_addr is the address of the data that will be transferred\r
+    by the HPDMA. This address must be 32-bit word aligned. The memory location\r
+    specified by this address must be located in DDR memory if the transfer_dir\r
+    parameter is set to HPDM_FROM_DDR.\r
+\r
+  @param dest_addr\r
+    The parameter dest_addr is the address of the location at which the data\r
+    will be transferred. This address must be 32-bit word aligned. The memory\r
+    location specified by this address must be located in DDR memory if the\r
+    transfer_dir parameter is set to HPDM_TO_DDR.\r
+\r
+  @param transfer_size\r
+    The parameter transfer_size specifies the size in bytes of the requested\r
+    transfer. The value of transfer_size must be a multiple of four.\r
+\r
+  @param transfer_dir\r
+     The parameter transfer_dir is used for specifying the data transfer\r
+     direction. Allowed values for transfer_dir are as follows:\r
+        - HPDMA_TO_DDR\r
+        - HPDMA_FROM_DDR\r
+\r
+  @return\r
+    This function does not return a value.\r
+ */\r
+void\r
+MSS_HPDMA_start\r
+(\r
+    uint32_t src_addr,\r
+    uint32_t dest_addr,\r
+    uint32_t transfer_size,\r
+    uint8_t transfer_dir\r
+);\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+  The MSS_HPDMA_pause() function pauses the current HPDMA transfer. The HPDMA\r
+  transfer can be resumed later  by calling MSS_HPDMA_resume().\r
+\r
+  @param\r
+    This function has no parameters.\r
+    \r
+  @return\r
+    This function does not return a value.\r
+ */\r
+void\r
+MSS_HPDMA_pause\r
+(\r
+    void\r
+);\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+  The MSS_HPDMA_pause() function resumes the current HPDMA transfer after it was\r
+  previously paused through a call to MSS_HPDMA_pause().\r
+\r
+  @param\r
+    This function has no parameters.\r
+    \r
+  @return\r
+    This function does not return a value.\r
+ */\r
+void\r
+MSS_HPDMA_resume\r
+(\r
+    void\r
+);\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+  The MSS_HPDMA_abort() function aborts the current HPDMA transfer.\r
+\r
+  @param\r
+    This function has no parameters.\r
+    \r
+  @return\r
+    This function does not return a value.\r
+ */\r
+void\r
+MSS_HPDMA_abort\r
+(\r
+    void\r
+);\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ The MSS_HPDMA_get_transfer_status() function returns the status of the HPDMA\r
+ transfer initiated by a call to MSS_HPDMA_start(). \r
+\r
+  @param\r
+    This function has no parameters.\r
+    \r
+  @return\r
+    The MSS_HPDMA_get_transfer_status() function returns the status of the HPDMA\r
+    transfer as a value of  type hpdma_status_t. The possible return values are:\r
+        - HPDMA_IN_PROGRESS\r
+        - HPDMA_COMPLETED\r
+        - HPDMA_SOURCE_ERROR\r
+        - HPDMA_DESTINATION_ERROR\r
+        - HPDMA_WORD_ALIGN_ERROR\r
+      \r
+  The example code below demonstrates the use of the\r
+  MSS_HPDMA_get_transfer_status() function to detect the completion of the\r
+  transfer of the content of eNVM into MDDR memory.\r
+  @code\r
+    void copy_envm_to_mddr(void)\r
+    {\r
+        MSS_HPDMA_start(ENVM_BASE_ADDR,\r
+                        MDDR_BASE_ADDR,\r
+                        ENVM_SIZE_BYTE,\r
+                        HPDMA_TO_DDR);\r
+        \r
+        do {\r
+            xfer_state = MSS_HPDMA_get_transfer_status();\r
+        } while(HPDMA_IN_PROGRESS == xfer_state);\r
+    }\r
+  @endcode\r
+ */\r
+hpdma_status_t\r
+MSS_HPDMA_get_transfer_status\r
+(\r
+    void\r
+);\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+  The MSS_HPDMA_set_handler() function is used to register a handler function\r
+  that will be called by the driver when the HPDMA transfer completes. You must\r
+  create and register a transfer completion handler function to suit your\r
+  application. The MSS HPDMA driver passes the outcome of the transfer to the\r
+  completion handler in the form of a hpdma_status_t parameter indicating if the\r
+  transfer was successful or the type of error that occurred during the transfer\r
+  if the transfer failed.\r
+\r
+  @param handler\r
+    The handler parameter is a pointer to a handler function provided by your\r
+    application. This handler is of type mss_hpdma_handler_t. The handler\r
+    function must take one parameter of type hpdma_status_t and must not return\r
+    a value.\r
+\r
+  @return\r
+    This function does not return a value.\r
+    \r
+  This example code demonstrates the use of the MSS_HPDMA_set_handler()\r
+  function:\r
+  @code\r
+    void transfer_complete_handler(hpdma_status_t status);\r
+\r
+    volatile uint32_t g_xfer_in_progress = 0;\r
+\r
+    void demo_transfer(void)\r
+    {\r
+        MSS_HPDMA_init();\r
+        \r
+        MSS_HPDMA_set_handler(transfer_complete_handler);\r
+        \r
+        g_xfer_in_progress = 1;\r
+        MSS_HPDMA_start((uint32_t)0x20000000,\r
+                        (uint32_t)0x00000000,\r
+                        20,\r
+                        HPDMA_FROM_DDR);\r
+        \r
+        while(g_xfer_in_progress)\r
+        {\r
+            ;\r
+        }\r
+    }\r
+\r
+    void transfer_complete_handler(hpdma_status_t status)\r
+    {\r
+        g_xfer_in_progress = 0;\r
+        \r
+        switch(status)\r
+        {\r
+            case HPDMA_COMPLETED:\r
+                display("Transfer complete");\r
+            break;\r
+\r
+            case HPDMA_SOURCE_ERROR:\r
+                display("Transfer failed: source error");\r
+            break;\r
+\r
+            case HPDMA_DESTINATION_ERROR:\r
+                display("Transfer failed: destination error");\r
+            break;\r
+\r
+            case HPDMA_WORD_ALIGN_ERROR:\r
+                display("Transfer failed: word alignment error");\r
+            break;\r
+\r
+            default:\r
+                display("Unexpected status");\r
+            break;\r
+        }\r
+    }\r
+  @endcode\r
+ */\r
+void\r
+MSS_HPDMA_set_handler\r
+(\r
+    mss_hpdma_handler_t handler\r
+);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* MSS_HPDMA_H_ */\r
diff --git a/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers/mss_nvm/mss_nvm.c b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers/mss_nvm/mss_nvm.c
new file mode 100644 (file)
index 0000000..2ba6571
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers/mss_nvm/mss_nvm.c
@@ -0,0 +1,694 @@
+/*******************************************************************************\r
+ * (c) Copyright 2011-2013 Microsemi SoC Products Group.  All rights reserved.\r
+ *\r
+ * This source file contains SmartFusion2 eNVM driver code.\r
+ *\r
+ * SVN $Revision: 5316 $\r
+ * SVN $Date: 2013-03-24 12:33:15 +0000 (Sun, 24 Mar 2013) $\r
+ */\r
+\r
+#include "../../CMSIS/m2sxxx.h"\r
+#include "../../CMSIS/mss_assert.h"\r
+#include "../../CMSIS/system_m2sxxx.h"\r
+#include "mss_nvm.h"\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/**************************************************************************/\r
+/* Preprocessor definitions                                               */\r
+/**************************************************************************/\r
+/*     eNVM command codes       */\r
+#define PROG_ADS       0x08000000u  /* One shot program with data in WD */\r
+#define VERIFY_ADS     0x10000000u  /* One shot verification with data in WD */\r
+#define USER_UNLOCK    0x13000000u  /* User unlock */\r
+\r
+#define BITS_PER_PAGE  1024u                   /* Number of bits per page */\r
+#define BYTES_PER_PAGE (BITS_PER_PAGE / 8u)    /* Number of bytes per page */\r
+\r
+#define NVM_OFFSET_SIGNIFICANT_BITS     0x0007FFFFu\r
+#define NVM1_BOTTOM_OFFSET              0x00040000u\r
+#define NVM1_TOP_OFFSET                 0x0007FFFFu\r
+\r
+#define NVM_BASE_ADDRESS                0x60000000u\r
+\r
+#define PAGE_ADDR_MASK                  0xFFFFFF80u\r
+\r
+#define BLOCK1_FIRST_WORD_OFFSET        0x00010000u\r
+\r
+#define WD_WORD_SIZE        32u\r
+\r
+#define NB_OF_BYTES_IN_A_WORD           4u\r
+\r
+#define WRITE_ERROR_MASK    (MSS_NVM_VERIFY_FAIL | \\r
+                             MSS_NVM_EVERIFY_FAIL | \\r
+                             MSS_NVM_WVERIFY_FAIL | \\r
+                             MSS_NVM_PEFAIL_LOCK | \\r
+                             MSS_NVM_WRCNT_OVER | \\r
+                             MSS_NVM_WR_DENIED)\r
+\r
+/*******************************************************************************\r
+ * Combined status definitions\r
+ * Below definitions should be used to decoded the bit encoded status returned \r
+ * by the function MSS_NVM_get_status().\r
+ */\r
+#define MSS_NVM_BUSY_B              (1u)        /* NVM is performing an internal operation */\r
+#define MSS_NVM_VERIFY_FAIL         ((uint32_t)1 << 1u)     /* NVM verify operation failed */\r
+#define MSS_NVM_EVERIFY_FAIL        ((uint32_t)1 << 2u)     /* NVM erase verify operation failed */\r
+#define MSS_NVM_WVERIFY_FAIL        ((uint32_t)1 << 3u)     /* NVM write verify operation failed */\r
+#define MSS_NVM_PEFAIL_LOCK         ((uint32_t)1 << 4u)     /* NVM program / erase operation failed due to page lock */\r
+#define MSS_NVM_WRCNT_OVER          ((uint32_t)1 << 5u)     /* NVM write count overflowed */\r
+#define MSS_NVM_WR_DENIED           ((uint32_t)1 << 18u)    /* NVM write is denied due to protection */\r
+\r
+/*******************************************************************************\r
+ * \r
+ */\r
+#define NVM_BLOCK_0     0u\r
+#define NVM_BLOCK_1     1u\r
+\r
+/*******************************************************************************\r
+ * \r
+ */\r
+#define MAX_512K_OFFSET     0x00080000u\r
+\r
+/**************************************************************************/\r
+/* Global data definitions                                                */\r
+/**************************************************************************/\r
+/**************************************************************************//**\r
+ * Look-up table for NVM blocks.\r
+ */\r
+static NVM_TypeDef * const g_nvm[] = \r
+{\r
+    ENVM_1 ,\r
+    ENVM_2\r
+};\r
+\r
+static NVM32_TypeDef * const g_nvm32[] =\r
+{\r
+    (NVM32_TypeDef *)ENVM1_BASE ,\r
+    (NVM32_TypeDef *)ENVM2_BASE\r
+};\r
+\r
+/**************************************************************************/\r
+/* Private function declarations                                          */\r
+/**************************************************************************/\r
+static nvm_status_t request_nvm_access\r
+(\r
+    uint32_t nvm_block_id\r
+);\r
+\r
+static nvm_status_t get_ctrl_access\r
+(\r
+    uint32_t nvm_offset,\r
+    uint32_t  length\r
+);\r
+\r
+static void release_ctrl_access(void);\r
+\r
+static uint32_t get_remaining_page_length\r
+(\r
+    uint32_t offset,\r
+    uint32_t  length\r
+);\r
+\r
+static void fill_wd_buffer\r
+(\r
+    const uint8_t * p_data,\r
+    uint32_t  length,\r
+    uint32_t block,\r
+    uint32_t offset\r
+);\r
+\r
+static uint32_t \r
+write_nvm\r
+(\r
+    uint32_t addr,\r
+    const uint8_t * pidata,\r
+    uint32_t  length,\r
+    uint32_t  lock_page,\r
+    uint32_t * p_status\r
+);\r
+\r
+static uint32_t \r
+wait_nvm_ready\r
+(\r
+    uint32_t block\r
+);\r
+\r
+static nvm_status_t get_error_code(uint32_t nvm_hw_status);\r
+\r
+/**************************************************************************/\r
+/* Public function definitions                                            */\r
+/**************************************************************************/\r
+\r
+/**************************************************************************//**\r
+ * See mss_nvm.h for details of how to use this function.\r
+ */\r
+nvm_status_t \r
+NVM_write\r
+(\r
+    uint32_t start_addr,\r
+    const uint8_t * pidata,\r
+    uint32_t  length,\r
+    uint32_t  lock_page\r
+)\r
+{\r
+    nvm_status_t status;\r
+    uint32_t nvm_offset;\r
+    uint32_t device_version;\r
+    \r
+    /*\r
+     * Prevent pages being locked for silicon versions which do not allow\r
+     * locked pages to be unlocked.\r
+     */\r
+    device_version = SYSREG->DEVICE_VERSION;\r
+    if((0x0000F802u == device_version) || (0x0001F802u == device_version))\r
+    {\r
+        lock_page = NVM_DO_NOT_LOCK_PAGE;\r
+    }\r
+    \r
+    /* Ignore upper address bits to ignore remapping setting. */\r
+    nvm_offset = start_addr & NVM_OFFSET_SIGNIFICANT_BITS;  /* Ignore remapping. */\r
+    \r
+    /* Check against attempt to write data larger than eNVM. */\r
+    ASSERT((nvm_offset + length) < MAX_512K_OFFSET);\r
+    if((nvm_offset + length) < MAX_512K_OFFSET)\r
+    {\r
+        /* Gain exclusive access to eNVM controller */\r
+        status = get_ctrl_access(nvm_offset, length);\r
+\r
+        /* Write eNVM one page at a time. */\r
+        if(NVM_SUCCESS == status)\r
+        {\r
+            uint32_t remaining_length = length;\r
+            \r
+            while((remaining_length > 0u) && (NVM_SUCCESS == status))\r
+            {\r
+                uint32_t length_written;\r
+                uint32_t nvm_hw_status = 0u;\r
+                \r
+                length_written = write_nvm(start_addr + (length - remaining_length), \r
+                                           &pidata[length - remaining_length],\r
+                                           remaining_length,\r
+                                           lock_page,\r
+                                           &nvm_hw_status);\r
+                \r
+                if(0u == length_written)\r
+                {\r
+                    status = get_error_code(nvm_hw_status);\r
+                }\r
+                else if(remaining_length > length_written)\r
+                {\r
+                    remaining_length -= length_written;\r
+                }\r
+                else\r
+                {\r
+                    remaining_length = 0u;\r
+                }\r
+            }\r
+            \r
+            /* Release eNVM controllers so that other masters can gain access to it. */\r
+            release_ctrl_access();\r
+        }\r
+    }\r
+    else\r
+    {\r
+        status = NVM_INVALID_PARAMETER;\r
+    }\r
+\r
+    return status;\r
+}\r
+\r
+/**************************************************************************//**\r
+  Generate error code based on NVM status value.\r
+  \r
+  The hardware nvm status passed as parameter is expected to be masked using the\r
+  following mask:\r
+                (MSS_NVM_VERIFY_FAIL | \\r
+                 MSS_NVM_EVERIFY_FAIL | \\r
+                 MSS_NVM_WVERIFY_FAIL | \\r
+                 MSS_NVM_PEFAIL_LOCK | \\r
+                 MSS_NVM_WRCNT_OVER | \\r
+                 MSS_NVM_WR_DENIED)\r
+  \r
+ */\r
+static nvm_status_t get_error_code(uint32_t nvm_hw_status)\r
+{\r
+    nvm_status_t status;\r
+    if(nvm_hw_status & MSS_NVM_WR_DENIED)\r
+    {\r
+        status = NVM_PROTECTION_ERROR;\r
+    }\r
+    else if(nvm_hw_status & MSS_NVM_WRCNT_OVER)\r
+    {\r
+        status = NVM_WRITE_THRESHOLD_ERROR;\r
+    }\r
+    else if(nvm_hw_status & MSS_NVM_PEFAIL_LOCK)\r
+    {\r
+        status = NVM_PAGE_LOCK_ERROR;\r
+    }\r
+    else\r
+    {\r
+        status = NVM_VERIFY_FAILURE;\r
+    }\r
+    \r
+    return status;\r
+}\r
+\r
+/**************************************************************************//**\r
+ * See mss_nvm.h for details of how to use this function.\r
+ */\r
+nvm_status_t\r
+NVM_unlock\r
+(\r
+    uint32_t start_addr,\r
+    uint32_t length\r
+)\r
+{\r
+    nvm_status_t status;\r
+    uint32_t nvm_offset;\r
+    uint32_t first_page;\r
+    uint32_t last_page;\r
+    uint32_t current_page;\r
+    uint32_t current_offset;\r
+    \r
+    /* Ignore upper address bits to ignore remapping setting. */\r
+    nvm_offset = start_addr & NVM_OFFSET_SIGNIFICANT_BITS;  /* Ignore remapping. */\r
+    \r
+    /* Check against attempt to write data larger than eNVM. */\r
+    ASSERT((nvm_offset + length) < MAX_512K_OFFSET);\r
+    if((nvm_offset + length) < MAX_512K_OFFSET)\r
+    {\r
+        current_offset = nvm_offset;\r
+        \r
+        first_page = nvm_offset / BYTES_PER_PAGE;\r
+        last_page = (nvm_offset + length) / BYTES_PER_PAGE;\r
+\r
+        /* Gain exclusive access to eNVM controller */\r
+        status = get_ctrl_access(nvm_offset, length);\r
+\r
+        /* Unlock eNVM one page at a time. */\r
+        if(NVM_SUCCESS == status)\r
+        {\r
+            uint32_t block;\r
+            uint32_t inc;\r
+            uint32_t first_word;\r
+            uint32_t word_offset;\r
+            uint32_t * p_nvm32;\r
+            uint32_t errors;\r
+            \r
+            p_nvm32 = (uint32_t *)NVM_BASE_ADDRESS;\r
+            \r
+            first_word = nvm_offset / 4u;\r
+            word_offset = first_word;\r
+            \r
+            for(current_page = first_page;\r
+                (current_page <= last_page) && (NVM_SUCCESS == status);\r
+                ++current_page)\r
+            {\r
+                uint32_t ctrl_status;\r
+            \r
+                if(word_offset >= BLOCK1_FIRST_WORD_OFFSET)\r
+                {\r
+                    block = NVM_BLOCK_1;\r
+                }\r
+                else\r
+                {\r
+                    block = NVM_BLOCK_0;\r
+                }\r
+                \r
+                for(inc = 0u; inc < WD_WORD_SIZE; ++inc)\r
+                {\r
+                    g_nvm32[block]->WD[inc] = p_nvm32[word_offset];\r
+                    ++word_offset;\r
+                }\r
+                \r
+                g_nvm[block]->PAGE_LOCK = NVM_DO_NOT_LOCK_PAGE;\r
+                g_nvm[block]->CMD = USER_UNLOCK;\r
+\r
+                /* Issue program command */\r
+                g_nvm[block]->CMD = PROG_ADS | (current_offset & PAGE_ADDR_MASK);\r
+                current_offset += BYTES_PER_PAGE;\r
+                \r
+                /* Wait for NVM to become ready. */\r
+                ctrl_status = wait_nvm_ready(block);\r
+\r
+                /* Check for errors. */\r
+                errors = ctrl_status & WRITE_ERROR_MASK;\r
+                if(errors)\r
+                {\r
+                    uint32_t nvm_hw_status;\r
+                    nvm_hw_status = g_nvm[block]->STATUS;\r
+                    status = get_error_code(nvm_hw_status);\r
+                }\r
+            }\r
+            \r
+            /* Release eNVM controllers so that other masters can gain access to it. */\r
+            release_ctrl_access();\r
+        }\r
+    }\r
+    else\r
+    {\r
+        status = NVM_INVALID_PARAMETER;\r
+    }\r
+    \r
+    return status;\r
+}\r
+\r
+/**************************************************************************/\r
+/* Private function definitions                                            */\r
+/**************************************************************************/\r
+\r
+/**************************************************************************//**\r
+ * \r
+ */\r
+#define ACCESS_REQUEST_TIMEOUT      0x00800000u\r
+#define REQUEST_NVM_ACCESS          0x01u\r
+#define CORTEX_M3_ACCESS_GRANTED    0x05u\r
+\r
+static uint8_t g_envm_ctrl_locks = 0x00u;\r
+\r
+static nvm_status_t\r
+request_nvm_access\r
+(\r
+    uint32_t nvm_block_id\r
+)\r
+{\r
+    nvm_status_t status = NVM_SUCCESS;\r
+    volatile uint32_t timeout_counter;\r
+    uint32_t access;\r
+    \r
+    /*\r
+     * Use the SystemCoreClock frequency to compute a delay counter value giving\r
+     * us a delay in the 500ms range. This is a very approximate delay.\r
+     */\r
+    timeout_counter = SystemCoreClock / 16u;\r
+    \r
+    /*\r
+     * Gain access to eNVM controller.\r
+     */\r
+    do {\r
+        g_nvm[nvm_block_id]->REQ_ACCESS = REQUEST_NVM_ACCESS;\r
+        access = g_nvm[nvm_block_id]->REQ_ACCESS;\r
+        if(access != CORTEX_M3_ACCESS_GRANTED)\r
+        {\r
+            /*\r
+             * Time out if another AHB master locked access to eNVM to prevent\r
+             * the Cortex-M3 from locking up on eNVM write if some other part\r
+             * of the system fails from releasing the eNVM.\r
+             */\r
+            --timeout_counter;\r
+            if(0u == timeout_counter)\r
+            {\r
+                status = NVM_IN_USE_BY_OTHER_MASTER;\r
+            }\r
+        }\r
+    } while((access != CORTEX_M3_ACCESS_GRANTED) && (NVM_SUCCESS == status));\r
+    \r
+    /*\r
+     * Mark controller as locked if successful so that it will be unlocked by a\r
+     * call to release_ctrl_access.\r
+     */\r
+    if(NVM_SUCCESS == status)\r
+    {\r
+        g_envm_ctrl_locks |= (uint8_t)((uint32_t)0x01 << nvm_block_id);\r
+    }\r
+    \r
+    return status;\r
+}\r
+\r
+\r
+/**************************************************************************//**\r
+ * \r
+ */\r
+static nvm_status_t\r
+get_ctrl_access\r
+(\r
+    uint32_t nvm_offset,\r
+    uint32_t  length\r
+)\r
+{\r
+    nvm_status_t access_req_status;\r
+    \r
+    /*\r
+     * Gain access to eNVM controller(s).\r
+     */\r
+    if(nvm_offset < NVM1_BOTTOM_OFFSET)\r
+    {\r
+        access_req_status = request_nvm_access(NVM_BLOCK_0);\r
+        if(NVM_SUCCESS == access_req_status)\r
+        {\r
+            uint32_t last_offset;\r
+            last_offset = nvm_offset + length;\r
+            if(last_offset >= NVM1_BOTTOM_OFFSET)\r
+            {\r
+                access_req_status = request_nvm_access(NVM_BLOCK_1);\r
+                if(NVM_IN_USE_BY_OTHER_MASTER == access_req_status)\r
+                {\r
+                    release_ctrl_access();\r
+                }\r
+            }\r
+        }\r
+    }\r
+    else\r
+    {\r
+        access_req_status = request_nvm_access(NVM_BLOCK_1);\r
+    }\r
+    \r
+    return access_req_status;\r
+}\r
+\r
+/**************************************************************************//**\r
+ * Release access to eNVM controllers.\r
+ */\r
+#define NVM_BLOCK_0_LOCK_MASK   0x01u\r
+#define NVM_BLOCK_1_LOCK_MASK   0x02u\r
+\r
+static void release_ctrl_access(void)\r
+{\r
+    uint8_t block_locked;\r
+    \r
+    block_locked = g_envm_ctrl_locks & NVM_BLOCK_0_LOCK_MASK;\r
+    if(block_locked)\r
+    {\r
+        g_nvm[NVM_BLOCK_0]->REQ_ACCESS = 0x00u;\r
+        g_envm_ctrl_locks &= ~NVM_BLOCK_0_LOCK_MASK;\r
+    }\r
+    \r
+    block_locked = g_envm_ctrl_locks & NVM_BLOCK_1_LOCK_MASK;\r
+    if(block_locked)\r
+    {\r
+        g_nvm[NVM_BLOCK_1]->REQ_ACCESS = 0x00u;\r
+        g_envm_ctrl_locks &= ~NVM_BLOCK_1_LOCK_MASK;\r
+    }\r
+}\r
+\r
+/**************************************************************************//**\r
+ * \r
+ */\r
+static uint32_t wait_nvm_ready(uint32_t block) \r
+{\r
+    volatile uint32_t ctrl_status;\r
+    uint32_t ctrl_ready;\r
+    uint32_t inc;\r
+    \r
+    /*\r
+     * Wait for NVM to become ready.\r
+     * We must ensure that we can read the ready bit set to 1 twice before we\r
+     * can assume that the other status bits are valid. See SmartFusion2 errata.\r
+     */\r
+    for(inc = 0u; inc < 2u; ++inc)\r
+    {\r
+        do {\r
+            ctrl_status = g_nvm[block]->STATUS;\r
+            ctrl_ready = ctrl_status  & MSS_NVM_BUSY_B;\r
+        } while(0u == ctrl_ready);\r
+    }\r
+    \r
+    return ctrl_status;\r
+}\r
+\r
+/**************************************************************************//**\r
+  Write as much data as will fit into the eNVM page corresponding to the\r
+  address "addr" passed as parameter. Return the number of bytes written into\r
+  the page.\r
+  In case of error, return the content of the eNVM controller status register\r
+  into the 32-bit word pointed to by p_status.\r
+ */\r
+static uint32_t \r
+write_nvm\r
+(\r
+    uint32_t addr,\r
+    const uint8_t * pidata,\r
+    uint32_t  length,\r
+    uint32_t  lock_page,\r
+    uint32_t * p_status\r
+)\r
+{\r
+    uint32_t length_written;\r
+    uint32_t offset;\r
+    \r
+    *p_status = 0u;\r
+    \r
+    offset = addr & NVM_OFFSET_SIGNIFICANT_BITS;  /* Ignore remapping. */\r
+\r
+    ASSERT(offset <= NVM1_TOP_OFFSET);\r
+    \r
+    /* Adjust length to fit within one page. */\r
+    length_written = get_remaining_page_length(offset, length);\r
+    \r
+    if(offset <= NVM1_TOP_OFFSET)\r
+    {\r
+        uint32_t block;\r
+        volatile uint32_t ctrl_status;\r
+        uint32_t errors;\r
+        \r
+        if(offset < NVM1_BOTTOM_OFFSET)\r
+        {\r
+            block = NVM_BLOCK_0;\r
+        }\r
+        else\r
+        {\r
+            block = NVM_BLOCK_1;\r
+            offset = offset - NVM1_BOTTOM_OFFSET;\r
+        }\r
+        \r
+        fill_wd_buffer(pidata, length_written, block, offset);\r
+\r
+        /* Set requested locking option. */\r
+        g_nvm[block]->PAGE_LOCK = lock_page;\r
+        \r
+        /* Issue program command */\r
+        g_nvm[block]->CMD = PROG_ADS | (offset & PAGE_ADDR_MASK);\r
+        \r
+        /* Wait for NVM to become ready. */\r
+        ctrl_status = wait_nvm_ready(block);\r
+\r
+        /* Check for errors. */\r
+        errors = ctrl_status & WRITE_ERROR_MASK;\r
+        if(errors)\r
+        {\r
+            /* Signal that an error occured by returning 0 a a number of bytes written. */\r
+            length_written = 0u;\r
+            *p_status = g_nvm[block]->STATUS;\r
+        }\r
+        else\r
+        {\r
+            /* Perform a verify. */\r
+            g_nvm[block]->CMD = VERIFY_ADS | (offset & PAGE_ADDR_MASK);\r
+            /* Wait for NVM to become ready. */\r
+            ctrl_status = wait_nvm_ready(block);\r
+\r
+            /* Check for errors. */\r
+            errors = ctrl_status & WRITE_ERROR_MASK;\r
+            if(errors)\r
+            {\r
+                /* Signal that an error occured by returning 0 a a number of bytes written. */\r
+                length_written = 0u;\r
+                *p_status = g_nvm[block]->STATUS;\r
+            }\r
+        }\r
+    }\r
+    \r
+    return length_written;\r
+}\r
+\r
+/*******************************************************************************\r
+  Return the number of bytes between the offset location and the end of the page\r
+  containing the first offset location. This tells us how many actual bytes can\r
+  be programmed with a single ProgramADS command.\r
+  This also tells us if we are programming a full page. If the return value is\r
+  equal to BYTES_PER_PAGE then we will be pragramming an entire NVM page.\r
+  Alternatively, this function returning a value other than BYTES_PER_PAGE\r
+  indicates that the WD[] buffer will have to be seeded with the existing\r
+  content of the eNVM before copying the data to program to eNVM into the WD[]\r
+  buffer.\r
+ */\r
+static uint32_t get_remaining_page_length\r
+(\r
+    uint32_t offset,\r
+    uint32_t  length\r
+)\r
+{\r
+    uint32_t start_page_plus_one;\r
+    uint32_t last_page;\r
+    \r
+    start_page_plus_one = (offset / BYTES_PER_PAGE) + 1u;\r
+    last_page = (offset + length) / BYTES_PER_PAGE;\r
+    if(last_page >= start_page_plus_one)\r
+    {\r
+        length = BYTES_PER_PAGE - (offset % BYTES_PER_PAGE);\r
+    }\r
+    \r
+    return length;\r
+}\r
+\r
+/**************************************************************************//**\r
+ * \r
+ */\r
+static void fill_wd_buffer\r
+(\r
+    const uint8_t * p_data,\r
+    uint32_t  length,\r
+    uint32_t block,\r
+    uint32_t offset\r
+)\r
+{\r
+    uint32_t inc;\r
+    uint32_t wd_offset;\r
+    \r
+    if(length != BYTES_PER_PAGE)\r
+    {\r
+        uint32_t * p_nvm32;\r
+        uint32_t nb_non_written_words;\r
+        uint32_t first_non_written_word;\r
+        /* \r
+         * Fill beginning of WD[] with current content of NVM page that must not\r
+         * be overwritten.\r
+         */\r
+        p_nvm32 = (uint32_t *)((NVM_BASE_ADDRESS + offset) & PAGE_ADDR_MASK);\r
+        nb_non_written_words = (offset % BYTES_PER_PAGE) / NB_OF_BYTES_IN_A_WORD;\r
+        if((offset % NB_OF_BYTES_IN_A_WORD) > 0u)\r
+        {\r
+            ++nb_non_written_words;\r
+        }\r
+        for(inc = 0u; (inc < WD_WORD_SIZE) && (inc < nb_non_written_words); ++inc)\r
+        {\r
+            g_nvm32[block]->WD[inc] = p_nvm32[inc];\r
+        }\r
+        \r
+        /*\r
+         * Fill end of WD[] with current content of NVM page that must not be\r
+         * overwritten.\r
+         */\r
+        first_non_written_word = ((offset + length) % BYTES_PER_PAGE) / NB_OF_BYTES_IN_A_WORD;\r
+        nb_non_written_words = (BYTES_PER_PAGE / NB_OF_BYTES_IN_A_WORD) - first_non_written_word;\r
+        \r
+        for(inc = 0u; inc < nb_non_written_words; ++inc)\r
+        {\r
+            g_nvm32[block]->WD[first_non_written_word + inc] = p_nvm32[first_non_written_word + inc];\r
+        }\r
+    }\r
+    \r
+    /*\r
+     * Fill WD[] with data requested to be written into NVM.\r
+     */\r
+    wd_offset = offset % BYTES_PER_PAGE;\r
+    for(inc = 0u; inc < length; ++inc)\r
+    {\r
+        g_nvm[block]->WD[wd_offset + inc] = p_data[inc];\r
+    }\r
+}\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+/******************************** END OF FILE ******************************/\r
+\r
+\r
+\r
+\r
+\r
+\r
diff --git a/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers/mss_nvm/mss_nvm.h b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers/mss_nvm/mss_nvm.h
new file mode 100644 (file)
index 0000000..d9812aa
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers/mss_nvm/mss_nvm.h
@@ -0,0 +1,249 @@
+/*******************************************************************************\r
+ * (c) Copyright 2011-2013 Microsemi SoC Products Group.  All rights reserved.\r
+ * \r
+ * This file contains public APIs for SmartFusion2 eNVM software driver.\r
+ * \r
+ * SVN $Revision: 5362 $\r
+ * SVN $Date: 2013-03-26 21:37:53 +0000 (Tue, 26 Mar 2013) $\r
+ */\r
+/*=========================================================================*//**\r
+  @mainpage SmartFusion2 MSS eNVM Bare Metal Driver.\r
+  \r
+  @section intro_sec Introduction\r
+  The SmartFusion2 microcontroller subsystem (MSS) includes up to two embedded\r
+  non-volatile memory (eNVM) blocks. Each of these eNVM blocks can be a maximum\r
+  size of 256kB. This software driver provides a set of functions for accessing\r
+  and controlling the MSS eNVM as part of a bare metal system where no operating\r
+  system is available. The driver can be adapted for use as part of an operating\r
+  system, but the implementation of the adaptation layer between the driver and\r
+  the operating system's driver model is outside the scope of the driver.\r
+  \r
+  The MSS eNVM driver provides support for the following features:\r
+    - eNVM write (program) operations.\r
+    - eNVM page unlocking\r
+  The MSS eNVM driver is provided as C source code.\r
+\r
+  \r
+  @section configuration Driver Configuration\r
+  The size of the MSS eNVM varies with different SmartFusion2 device types. You\r
+  must only use this driver to access memory locations within the valid MSS eNVM\r
+  address space for the targeted device. The size of the valid MSS eNVM address\r
+  space corresponds to the size of the MSS eNVM in the device. Some pages of the\r
+  MSS eNVM may be write protected by the SmartFusion2 MSS configurator as part\r
+  of the hardware design flow. The driver cannot unlock or write to these\r
+  protected pages.\r
+  The base address, register addresses and interrupt number assignment for the\r
+  MSS eNVM blocks are defined as constants in the SmartFusion2 CMSIS HAL. You\r
+  must ensure that the latest SmartFusion2 CMSIS HAL is included in the project\r
+  settings of the software tool chain used to build your project and that it is\r
+  generated into your project.\r
+\r
+  @section theory_op Theory of Operation\r
+  The total amount of eNVM available in a SmartFusion device ranges from 128kB\r
+  to 512kB, provided in one or two physical eNVM blocks. The eNVM blocks are\r
+  divided into pages, with each page holding 128 bytes of data. The MSS eNVM\r
+  driver treats the entire eNVM as a contiguous memory space. It provides write\r
+  access to all pages that are in the valid eNVM address range for the\r
+  SmartFusion device and that are not write-protected. The driver imposes no\r
+  restrictions on writing data across eNVM block or page boundaries. The driver\r
+  supports random access writes to the eNVM memory. \r
+\r
+ *//*=========================================================================*/\r
+#ifndef __MSS_NVM_H\r
+#define __MSS_NVM_H\r
+\r
+#include <stdint.h>\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/******************************************************************************/\r
+/* Public definitions                                                         */\r
+/******************************************************************************/\r
+/*******************************************************************************\r
+ * Page Locking constants:\r
+ */\r
+/*\r
+ * Indicates that the NVM_write() function should not lock the addressed pages\r
+ * after programming the data.\r
+ */\r
+#define NVM_DO_NOT_LOCK_PAGE    0u\r
+\r
+/*\r
+ * Indicates that the NVM_write() function should lock the addressed pages after\r
+ * programming the data.\r
+ */\r
+#define NVM_LOCK_PAGE           1u\r
+\r
+/*******************************************************************************\r
+  The nvm_status_t enumeration specifies the possible return values from the\r
+  NVM_write() and NVM_unlock() functions.\r
+  \r
+    NVM_SUCCESS:\r
+      Indicates that the programming was successful.\r
+        \r
+    NVM_PROTECTION_ERROR:\r
+      Indicates that the operation could not be completed because of a\r
+      protection error. This happens when attempting to program a page that was\r
+      set as protected in the hardware flow.\r
+      \r
+    NVM_VERIFY_FAILURE:\r
+      Indicates that one of the verify operations failed.\r
+      \r
+    NVM_PAGE_LOCK_ERROR:\r
+      Indicates that the operation could not complete because one of the pages\r
+      is locked. This may happen if the page was locked during a previous call\r
+      to NVM_write() or if the page was locked in the hardware design flow.\r
+      \r
+    NVM_WRITE_THRESHOLD_ERROR:\r
+      Indicates that the NVM maximum number of programming cycles has been\r
+      reached.\r
+      \r
+    NVM_IN_USE_BY_OTHER_MASTER:\r
+      Indicates that some other MSS AHB Bus Matrix master is accessing the NVM.\r
+      This could be due to the FPGA logic or the system controller programming\r
+      the NVM.\r
+      \r
+    NVM_INVALID_PARAMETER:\r
+      Indicates that one of more of the function parameters has an invalid\r
+      value. This is typically  returned when attempting to write or unlock more\r
+      eNVM than is available on  the device.\r
+ */\r
+typedef enum nvm_status\r
+{\r
+    NVM_SUCCESS = 0,\r
+    NVM_PROTECTION_ERROR,\r
+    NVM_VERIFY_FAILURE,\r
+    NVM_PAGE_LOCK_ERROR,\r
+    NVM_WRITE_THRESHOLD_ERROR,\r
+    NVM_IN_USE_BY_OTHER_MASTER,\r
+    NVM_INVALID_PARAMETER\r
+} nvm_status_t;\r
+\r
+/******************************************************************************/\r
+/* Public variables                                                           */\r
+/******************************************************************************/\r
+\r
+\r
+/******************************************************************************/\r
+/* Public function declarations                                               */\r
+/******************************************************************************/\r
+\r
+/***************************************************************************//**\r
+  The NVM_write() function is used to program (or write) data into the eNVM.\r
+  This function treats the two eNVM blocks contiguously, so a total of 512kB of\r
+  memory can be accessed linearly. The start address and end address of the\r
+  memory range to be programmed do not need to be page aligned. This function\r
+  supports programming of data that spans multiple pages. This function is a\r
+  blocking function.\r
+  Note: The NVM_write() function performs a verify operation on each page \r
+        programmed to ensure the eNVM is programmed with the expected data.\r
+\r
+  @param start_addr\r
+    The start_addr parameter is the byte aligned start address in the eNVM\r
+    address space, to which the data is to be programmed.\r
+\r
+  @param pidata\r
+    The pidata parameter is the byte aligned start address of the input data.\r
+\r
+  @param length\r
+    The length parameter is the number of bytes of data to be programmed.\r
+\r
+  @param lock_page\r
+    The lock_page parameter specifies whether the pages that are programmed\r
+    must be locked or not once programmed. Locking the programmed pages prevents\r
+    them from being overwritten by mistake. Subsequent programming of these\r
+    pages will require the pages to be unlocked prior to calling NVM_write().\r
+    Allowed values for lock_page are:\r
+        - NVM_DO_NOT_LOCK_PAGE\r
+        - NVM_LOCK_PAGE\r
+        \r
+  @return\r
+    This function returns NVM_SUCCESS on successful execution. \r
+    It returns one of the following error codes if the programming of the eNVM\r
+    fails:\r
+        - NVM_PROTECTION_ERROR\r
+        - NVM_VERIFY_FAILURE\r
+        - NVM_PAGE_LOCK_ERROR\r
+        - NVM_WRITE_THRESHOLD_ERROR\r
+        - NVM_IN_USE_BY_OTHER_MASTER\r
+        - NVM_INVALID_PARAMETER\r
+        \r
+  Example:\r
+  @code\r
+    uint8_t idata[815] = {"Z"};\r
+    status = NVM_write(0x0, idata, sizeof(idata), NVM_DO_NOT_LOCK_PAGE);\r
+  @endcode\r
+ */\r
+nvm_status_t \r
+NVM_write\r
+(\r
+    uint32_t start_addr,\r
+    const uint8_t * pidata,\r
+    uint32_t  length,\r
+    uint32_t  lock_page\r
+);\r
+\r
+/***************************************************************************//**\r
+  The NVM_unlock() function is used to unlock the eNVM pages for a specified\r
+  range of eNVM addresses in preparation for writing data into the unlocked\r
+  locations. This function treats the two eNVM blocks contiguously, so a total\r
+  of 512kB of memory can be accessed linearly. The start address and end address\r
+  of the memory range to be unlocked do not need to be page aligned. This\r
+  function supports unlocking of an eNVM address range that spans multiple\r
+  pages. This function is a blocking function.\r
+\r
+  @param start_addr\r
+    The start_addr parameter is the byte aligned start address, in the eNVM\r
+    address space, of the memory range to be unlocked.\r
+    \r
+  @param length\r
+    The length parameter is the size in bytes of the memory range to be\r
+    unlocked.\r
+\r
+  @return\r
+    This function returns NVM_SUCCESS on successful execution. \r
+    It returns one of the following error codes if the unlocking of the eNVM fails:\r
+        - NVM_PROTECTION_ERROR\r
+        - NVM_VERIFY_FAILURE\r
+        - NVM_PAGE_LOCK_ERROR\r
+        - NVM_WRITE_THRESHOLD_ERROR\r
+        - NVM_IN_USE_BY_OTHER_MASTER\r
+        - NVM_INVALID_PARAMETER\r
+        \r
+  The example code below demonstrates the intended use of the NVM_unlock()\r
+  function:\r
+  @code\r
+    int program_locked_nvm(uint32_t target_addr, uint32_t length)\r
+    {\r
+        nvm_status_t status;\r
+        int success = 0;\r
+        \r
+        status = NVM_unlock(target_addr, length);\r
+        if(NVM_SUCCESS == status)\r
+        {\r
+            status = NVM_write(target_addr, buffer, length, NVM_LOCK_PAGE);\r
+            if(NVM_SUCCESS == status)\r
+            {\r
+                success = 1; \r
+            }\r
+        }\r
+        return success;\r
+    }\r
+  @endcode\r
+ */\r
+nvm_status_t\r
+NVM_unlock\r
+(\r
+    uint32_t start_addr,\r
+    uint32_t length\r
+);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __MSS_NVM_H */\r
+\r
+\r
diff --git a/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers/mss_rtc/mss_rtc.c b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers/mss_rtc/mss_rtc.c
new file mode 100644 (file)
index 0000000..2af1f0e
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers/mss_rtc/mss_rtc.c
@@ -0,0 +1,666 @@
+/*******************************************************************************\r
+ * (c) Copyright 2008-2013 Microsemi SoC Products Group.  All rights reserved.\r
+ * \r
+ * SmartFusion2 MSS RTC bare metal driver implementation.\r
+ *\r
+ * SVN $Revision: 5090 $\r
+ * SVN $Date: 2013-02-18 12:13:31 +0000 (Mon, 18 Feb 2013) $\r
+ */\r
+#include "mss_rtc.h"\r
+#include "../../CMSIS/mss_assert.h"\r
+#include <string.h>\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif \r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ * CONTROL_REG register masks.\r
+ */\r
+#define CONTROL_RUNNING_MASK        0x00000001u\r
+\r
+#define CONTROL_RTC_START_MASK      0x00000001u\r
+#define CONTROL_RTC_STOP_MASK       0x00000002u\r
+#define CONTROL_ALARM_ON_MASK       0x00000004u\r
+#define CONTROL_ALARM_OFF_MASK      0x00000008u\r
+#define CONTROL_RESET_MASK          0x00000010u\r
+#define CONTROL_UPLOAD_MASK         0x00000020u\r
+#define CONTROL_WAKEUP_CLR_MASK     0x00000100u\r
+#define CONTROL_UPDATED_MASK        0x00000400u\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ * MODE_REG register masks.\r
+ */\r
+#define MODE_CLK_MODE_MASK          0x00000001u\r
+#define MODE_WAKEUP_EN_MASK         0x00000002u\r
+#define MODE_WAKEUP_RESET_MASK      0x00000004u\r
+#define MODE_WAKEUP_CONTINUE_MASK   0x00000008u\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ * Other masks.\r
+ */\r
+#define MAX_BINARY_HIGHER_COUNT     0x7FFu\r
+#define MASK_32_BIT                 0xFFFFFFFFu\r
+#define MAX_PRESCALAR_COUNT         0x03FFFFFFu\r
+#define CALENDAR_SHIFT              8u\r
+\r
+#define COMPARE_ALL_BITS            0xFFFFFFFFu\r
+\r
+#define SYSREG_RTC_WAKEUP_M3_EN_MASK    0x00000001u\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ * Index into look-up table.\r
+ */\r
+#define SECONDS     0\r
+#define MINUTES     1\r
+#define HOURS       2\r
+#define DAYS        3\r
+#define MONTHS      4\r
+#define YEARS       5\r
+#define WEEKDAYS    6\r
+#define WEEKS       7\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+  Local functions.\r
+ */\r
+static uint8_t\r
+get_clock_mode\r
+(\r
+    void\r
+);\r
+\r
+static void set_rtc_mode(uint8_t requested_mode);\r
+\r
+static void add_alarm_cfg_values\r
+(\r
+    uint8_t calendar_item,\r
+    uint32_t * p_calendar_value,\r
+    uint32_t * p_compare_mask\r
+    \r
+);\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ * See "mss_rtc.h" for details of how to use this function.\r
+ */\r
+void\r
+MSS_RTC_init\r
+(\r
+    uint8_t mode,\r
+    uint32_t prescaler\r
+)\r
+{\r
+    ASSERT(prescaler <= MAX_PRESCALAR_COUNT);\r
+\r
+    if(prescaler <= MAX_PRESCALAR_COUNT)\r
+    {\r
+        /* Stop the RTC. */\r
+        MSS_RTC_stop();\r
+        \r
+        /* Disable alarm. */\r
+        RTC->CONTROL_REG = CONTROL_ALARM_OFF_MASK;\r
+        \r
+        /* Disable Interrupt */\r
+        MSS_RTC_disable_irq();\r
+        NVIC_ClearPendingIRQ(RTC_Wakeup_IRQn);\r
+\r
+        /* Clear RTC wake up interrupt signal */\r
+        MSS_RTC_clear_irq();\r
+\r
+        /* Enable the RTC to interrupt the Cortex-M3. */\r
+        SYSREG->RTC_WAKEUP_CR |= SYSREG_RTC_WAKEUP_M3_EN_MASK;\r
+        \r
+        /* Select mode of operation, including the wake configuration. */\r
+        if(MSS_RTC_CALENDAR_MODE == mode)\r
+        {\r
+            RTC->MODE_REG = MODE_CLK_MODE_MASK;\r
+        }\r
+        else\r
+        {\r
+            RTC->MODE_REG = 0u;\r
+        }\r
+        \r
+        /* Reset the alarm and compare registers to a known value. */\r
+        RTC->ALARM_LOWER_REG = 0u;\r
+        RTC->ALARM_UPPER_REG = 0u;\r
+        RTC->COMPARE_LOWER_REG = 0u;\r
+        RTC->COMPARE_UPPER_REG = 0u;\r
+\r
+        /* Reset the calendar counters */\r
+        MSS_RTC_reset_counter();\r
+\r
+        /* Set new Prescaler value */\r
+        RTC->PRESCALER_REG = prescaler;\r
+    }\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+  See "mss_rtc.h" for details of how to use this function.\r
+ */\r
+void\r
+MSS_RTC_set_calendar_count\r
+(\r
+    const mss_rtc_calendar_t *new_rtc_value\r
+)\r
+{\r
+    uint8_t error = 0u;\r
+    uint8_t clock_mode;\r
+    \r
+    const uint8_t g_rtc_max_count_lut[] =\r
+    {\r
+       /* Calendar mode */\r
+        59u,    /* Seconds */\r
+        59u,    /* Minutes */\r
+        23u,    /* Hours   */\r
+        31u,    /* Days    */\r
+        12u,    /* Months  */\r
+        254u,   /* Years   */\r
+        7u,     /* Weekdays*/\r
+        52u     /* Week    */\r
+    };\r
+\r
+    const uint8_t g_rtc_min_count_lut[] =\r
+    {\r
+       /* Calendar mode */\r
+        0u, /* Seconds */\r
+        0u, /* Minutes */\r
+        0u, /* Hours   */\r
+        1u, /* Days    */\r
+        1u, /* Months  */\r
+        0u, /* Years   */\r
+        1u, /* Weekdays*/\r
+        1u  /* Week    */\r
+    };\r
+    \r
+    /* Assert if the values cross the limit */\r
+    ASSERT(new_rtc_value->second >= g_rtc_min_count_lut[SECONDS]);\r
+    ASSERT(new_rtc_value->second <= g_rtc_max_count_lut[SECONDS]);\r
+    ASSERT(new_rtc_value->minute >= g_rtc_min_count_lut[MINUTES]);\r
+    ASSERT(new_rtc_value->minute <= g_rtc_max_count_lut[MINUTES]);\r
+    ASSERT(new_rtc_value->hour >= g_rtc_min_count_lut[HOURS]);\r
+    ASSERT(new_rtc_value->hour <= g_rtc_max_count_lut[HOURS]);\r
+    ASSERT(new_rtc_value->day >= g_rtc_min_count_lut[DAYS]);\r
+    ASSERT(new_rtc_value->day <= g_rtc_max_count_lut[DAYS]);\r
+    ASSERT(new_rtc_value->month >= g_rtc_min_count_lut[MONTHS]);\r
+    ASSERT(new_rtc_value->month <= g_rtc_max_count_lut[MONTHS]);\r
+    ASSERT(new_rtc_value->year >= g_rtc_min_count_lut[YEARS]);\r
+    ASSERT(new_rtc_value->year <= g_rtc_max_count_lut[YEARS]);\r
+    ASSERT(new_rtc_value->weekday >= g_rtc_min_count_lut[WEEKDAYS]);\r
+    ASSERT(new_rtc_value->weekday <= g_rtc_max_count_lut[WEEKDAYS]);\r
+    ASSERT(new_rtc_value->week >= g_rtc_min_count_lut[WEEKS]);\r
+    ASSERT(new_rtc_value->week <= g_rtc_max_count_lut[WEEKS]);\r
+\r
+    if(new_rtc_value->second < g_rtc_min_count_lut[SECONDS]) {error = 1u;}\r
+    if(new_rtc_value->second > g_rtc_max_count_lut[SECONDS]) {error = 1u;}\r
+    if(new_rtc_value->minute < g_rtc_min_count_lut[MINUTES]) {error = 1u;}\r
+    if(new_rtc_value->minute > g_rtc_max_count_lut[MINUTES]) {error = 1u;}\r
+    if(new_rtc_value->hour < g_rtc_min_count_lut[HOURS]) {error = 1u;}\r
+    if(new_rtc_value->hour > g_rtc_max_count_lut[HOURS]) {error = 1u;}\r
+    if(new_rtc_value->day < g_rtc_min_count_lut[DAYS]) {error = 1u;}\r
+    if(new_rtc_value->day > g_rtc_max_count_lut[DAYS]) {error = 1u;}\r
+    if(new_rtc_value->month < g_rtc_min_count_lut[MONTHS]) {error = 1u;}\r
+    if(new_rtc_value->month > g_rtc_max_count_lut[MONTHS]) {error = 1u;}\r
+    if(new_rtc_value->year < g_rtc_min_count_lut[YEARS]) {error = 1u;}\r
+    if(new_rtc_value->year > g_rtc_max_count_lut[YEARS]) {error = 1u;}\r
+    if(new_rtc_value->weekday < g_rtc_min_count_lut[WEEKDAYS]) {error = 1u;}\r
+    if(new_rtc_value->weekday > g_rtc_max_count_lut[WEEKDAYS]) {error = 1u;}\r
+    if(new_rtc_value->week < g_rtc_min_count_lut[WEEKS]) {error = 1u;}\r
+    if(new_rtc_value->week > g_rtc_max_count_lut[WEEKS]) {error = 1u;}\r
+\r
+    /* \r
+     * This function can only be used when the RTC is configured to operate in\r
+     * calendar counter mode. \r
+     */\r
+    clock_mode = get_clock_mode();\r
+    ASSERT(MSS_RTC_CALENDAR_MODE == clock_mode);\r
+    \r
+    if((0u == error) && (MSS_RTC_CALENDAR_MODE == clock_mode))\r
+    {\r
+        uint32_t upload_in_progress;\r
+        \r
+        /*\r
+         * Write the RTC new value. \r
+         */\r
+        RTC->SECONDS_REG = new_rtc_value->second;\r
+        RTC->MINUTES_REG = new_rtc_value->minute;\r
+        RTC->HOURS_REG = new_rtc_value->hour;\r
+        RTC->DAY_REG = new_rtc_value->day;\r
+        RTC->MONTH_REG = new_rtc_value->month;\r
+        RTC->YEAR_REG = new_rtc_value->year;\r
+        RTC->WEEKDAY_REG = new_rtc_value->weekday;\r
+        RTC->WEEK_REG = new_rtc_value->week;\r
+\r
+        /* Data is copied, now issue upload command */\r
+        RTC->CONTROL_REG = CONTROL_UPLOAD_MASK ;\r
+        \r
+        /* Wait for the upload to complete. */\r
+        do {\r
+            upload_in_progress = RTC->CONTROL_REG & CONTROL_UPLOAD_MASK;\r
+        } while(upload_in_progress);\r
+    }\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ * See "mss_rtc.h" for details of how to use this function.\r
+ */\r
+void\r
+MSS_RTC_set_binary_count\r
+(\r
+    uint64_t new_rtc_value\r
+)\r
+{\r
+    uint8_t clock_mode;\r
+\r
+    /* \r
+     * This function can only be used when the RTC is configured to operate in\r
+     * binary counter mode. \r
+     */\r
+    clock_mode = get_clock_mode();\r
+    ASSERT(MSS_RTC_BINARY_MODE == clock_mode);\r
+    \r
+    if(MSS_RTC_BINARY_MODE == clock_mode)\r
+    {\r
+        uint32_t rtc_upper_32_bit_value;\r
+        \r
+        rtc_upper_32_bit_value = (uint32_t)(new_rtc_value >> 32u) & MASK_32_BIT;\r
+\r
+        /* Assert if the values cross the limit */\r
+        ASSERT(rtc_upper_32_bit_value <= MAX_BINARY_HIGHER_COUNT);\r
+\r
+        if(rtc_upper_32_bit_value <= MAX_BINARY_HIGHER_COUNT)\r
+        {\r
+            uint32_t upload_in_progress;\r
+            \r
+            /*\r
+             * Write the RTC new value. \r
+             */\r
+            RTC->DATE_TIME_LOWER_REG = (uint32_t)new_rtc_value;\r
+            RTC->DATE_TIME_UPPER_REG =\r
+                    (uint32_t)(( new_rtc_value >> 32u) & MAX_BINARY_HIGHER_COUNT);\r
+\r
+            /* Data is copied, now issue upload command */\r
+            RTC->CONTROL_REG = CONTROL_UPLOAD_MASK;\r
+            \r
+            /* Wait for the upload to complete. */\r
+            do {\r
+                upload_in_progress = RTC->CONTROL_REG & CONTROL_UPLOAD_MASK;\r
+            } while(upload_in_progress);\r
+        }\r
+    }\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ * See "mss_rtc.h" for details of how to use this function.\r
+ */\r
+void\r
+MSS_RTC_get_calendar_count\r
+(\r
+    mss_rtc_calendar_t *p_rtc_calendar\r
+)\r
+{\r
+    uint8_t clock_mode;\r
+    /* \r
+     * This function can only be used when the RTC is configured to operate in\r
+     * calendar counter mode. \r
+     */\r
+    clock_mode = get_clock_mode();\r
+    ASSERT(MSS_RTC_CALENDAR_MODE == clock_mode);\r
+    \r
+    if(MSS_RTC_CALENDAR_MODE == clock_mode)\r
+    {\r
+        p_rtc_calendar->second = (uint8_t)RTC->SECONDS_REG;\r
+        p_rtc_calendar->minute = (uint8_t)RTC->MINUTES_REG;\r
+        p_rtc_calendar->hour = (uint8_t)RTC->HOURS_REG;\r
+        p_rtc_calendar->day = (uint8_t)RTC->DAY_REG;\r
+        p_rtc_calendar->month = (uint8_t)RTC->MONTH_REG;\r
+        p_rtc_calendar->year = (uint8_t)RTC->YEAR_REG;\r
+        p_rtc_calendar->weekday = (uint8_t)RTC->WEEKDAY_REG;\r
+        p_rtc_calendar->week = (uint8_t)RTC->WEEK_REG;\r
+    }\r
+    else\r
+    {\r
+        /*\r
+         * Set returned calendar count to zero if the RTC is not configured for\r
+         * calendar counter mode. This should make incorrect release application\r
+         * code behave consistently and help application debugging.\r
+         */\r
+        memset(p_rtc_calendar, 0, sizeof(mss_rtc_calendar_t));\r
+    }\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ * See "mss_rtc.h" for details of how to use this function.\r
+ */\r
+uint64_t\r
+MSS_RTC_get_binary_count\r
+(\r
+    void\r
+)\r
+{\r
+    uint64_t rtc_count;\r
+    uint8_t clock_mode;\r
+\r
+    /* \r
+     * This function can only be used when the RTC is configured to operate in\r
+     * binary counter mode. \r
+     */\r
+    clock_mode = get_clock_mode();\r
+    ASSERT(MSS_RTC_BINARY_MODE == clock_mode);\r
+    \r
+    if(MSS_RTC_BINARY_MODE == clock_mode)\r
+    {\r
+        rtc_count = RTC->DATE_TIME_LOWER_REG;\r
+        rtc_count = rtc_count | ((uint64_t)RTC->DATE_TIME_UPPER_REG << 32u) ;\r
+    }\r
+    else\r
+    {\r
+        /*\r
+         * Set returned binary count to zero if the RTC is not configured for\r
+         * binary counter mode. This should make incorrect release application\r
+         * code behave consistently and help application debugging.\r
+         */\r
+        rtc_count = 0u;\r
+    }\r
+\r
+    return rtc_count;\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ *\r
+ */\r
+static void add_alarm_cfg_values\r
+(\r
+    uint8_t calendar_item,\r
+    uint32_t * p_calendar_value,\r
+    uint32_t * p_compare_mask\r
+    \r
+)\r
+{\r
+    if(MSS_RTC_CALENDAR_DONT_CARE == calendar_item)\r
+    {\r
+        *p_calendar_value = (uint32_t)(*p_calendar_value << CALENDAR_SHIFT);\r
+        *p_compare_mask = (uint32_t)(*p_compare_mask << CALENDAR_SHIFT);\r
+    }\r
+    else\r
+    {\r
+        *p_calendar_value = (uint32_t)((*p_calendar_value << CALENDAR_SHIFT) | (uint32_t)calendar_item);\r
+        *p_compare_mask = (uint32_t)((*p_compare_mask << CALENDAR_SHIFT) | (uint32_t)0xFFu);\r
+    }\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ * See "mss_rtc.h" for details of how to use this function.\r
+ */\r
+void MSS_RTC_set_calendar_count_alarm\r
+(\r
+    const mss_rtc_calendar_t * alarm_value\r
+)\r
+{\r
+    uint32_t calendar_value;\r
+    uint32_t compare_mask;\r
+    uint8_t mode;\r
+    \r
+    mode = (uint8_t)(RTC->MODE_REG & MODE_CLK_MODE_MASK);\r
+    /*\r
+     * This function can only be used with the RTC set to operate in calendar\r
+     * mode.\r
+     */\r
+    ASSERT(MSS_RTC_CALENDAR_MODE == mode);\r
+    if(MSS_RTC_CALENDAR_MODE == mode)\r
+    {\r
+        uint8_t required_mode_reg;\r
+        \r
+        /* Disable the alarm before updating*/\r
+        RTC->CONTROL_REG = CONTROL_ALARM_OFF_MASK;\r
+\r
+        /* Set alarm and compare lower registers. */\r
+        calendar_value = 0u;\r
+        compare_mask = 0u;\r
+        \r
+        add_alarm_cfg_values(alarm_value->day, &calendar_value, &compare_mask);\r
+        add_alarm_cfg_values(alarm_value->hour, &calendar_value, &compare_mask);\r
+        add_alarm_cfg_values(alarm_value->minute, &calendar_value, &compare_mask);\r
+        add_alarm_cfg_values(alarm_value->second, &calendar_value, &compare_mask);\r
+\r
+        RTC->ALARM_LOWER_REG = calendar_value;\r
+        RTC->COMPARE_LOWER_REG = compare_mask;\r
+\r
+        /* Set alarm and compare upper registers. */\r
+        calendar_value = 0u;\r
+        compare_mask = 0u;\r
+        \r
+        add_alarm_cfg_values(alarm_value->week, &calendar_value, &compare_mask);\r
+        add_alarm_cfg_values(alarm_value->weekday, &calendar_value, &compare_mask);\r
+        add_alarm_cfg_values(alarm_value->year, &calendar_value, &compare_mask);\r
+        add_alarm_cfg_values(alarm_value->month, &calendar_value, &compare_mask);\r
+\r
+        RTC->ALARM_UPPER_REG = calendar_value;\r
+        RTC->COMPARE_UPPER_REG = compare_mask;\r
+        \r
+        /* Configure the RTC to enable the alarm. */\r
+        required_mode_reg = mode | MODE_WAKEUP_EN_MASK | MODE_WAKEUP_CONTINUE_MASK;\r
+        set_rtc_mode(required_mode_reg);\r
+        \r
+        /* Enable the alarm */\r
+        RTC->CONTROL_REG = CONTROL_ALARM_ON_MASK ;\r
+    }\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+  We only write the RTC mode register if really required because the RTC needs\r
+  to be stopped for the mode register to be written. Stopping the RTC everytime\r
+  the wakeup alarm configuration is set might induce drift on the RTC time.\r
+  This function is intended to be used when setting alarms.\r
+ */\r
+static void set_rtc_mode(uint8_t requested_mode)\r
+{\r
+    if(RTC->MODE_REG != requested_mode)\r
+    {\r
+        uint32_t rtc_running;\r
+        rtc_running = RTC->CONTROL_REG & CONTROL_RUNNING_MASK;\r
+        if(rtc_running)\r
+        {\r
+            /* Stop the RTC in order to change the mode register content.*/\r
+            MSS_RTC_stop();\r
+            RTC->MODE_REG = requested_mode;\r
+            MSS_RTC_start();\r
+        }\r
+        else\r
+        {\r
+            RTC->MODE_REG = requested_mode;\r
+        }\r
+    }\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ * See "mss_rtc.h" for details of how to use this function.\r
+ */\r
+void MSS_RTC_set_binary_count_alarm\r
+(\r
+    uint64_t alarm_value,\r
+    mss_rtc_alarm_type_t alarm_type\r
+)\r
+{\r
+    uint8_t mode;\r
+    \r
+    mode = (uint8_t)(RTC->MODE_REG & MODE_CLK_MODE_MASK);\r
+    /*\r
+     * This function can only be used with the RTC set to operate in binary\r
+     * counter mode.\r
+     */\r
+    ASSERT(MSS_RTC_BINARY_MODE == mode);\r
+    if(MSS_RTC_BINARY_MODE == mode)\r
+    {\r
+        uint8_t required_mode_reg;\r
+        \r
+        /* Disable the alarm before updating*/\r
+        RTC->CONTROL_REG = CONTROL_ALARM_OFF_MASK;\r
+\r
+        /* Set the alarm value. */\r
+        RTC->COMPARE_LOWER_REG = COMPARE_ALL_BITS;\r
+        RTC->COMPARE_UPPER_REG = COMPARE_ALL_BITS;\r
+        RTC->ALARM_LOWER_REG = (uint32_t)alarm_value;\r
+        RTC->ALARM_UPPER_REG = (uint32_t)(alarm_value >> 32u);\r
+\r
+        /*\r
+         * Configure the RTC to enable the alarm.\r
+         */\r
+        required_mode_reg = mode | MODE_WAKEUP_EN_MASK | MODE_WAKEUP_CONTINUE_MASK;\r
+        if(MSS_RTC_PERIODIC_ALARM == alarm_type)\r
+        {\r
+            /*\r
+             * The RTC binary counter will be fully reset when the alarm occurs.\r
+             * The counter will continue counting while the wake-up interrupt is\r
+             * active.\r
+             */\r
+            required_mode_reg |= MODE_WAKEUP_RESET_MASK;\r
+        }\r
+        set_rtc_mode(required_mode_reg);\r
+        \r
+        /* Enable the alarm */\r
+        RTC->CONTROL_REG = CONTROL_ALARM_ON_MASK;\r
+    }\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ * See "mss_rtc.h" for details of how to use this function.\r
+ */\r
+void\r
+MSS_RTC_start\r
+(\r
+    void\r
+)\r
+{\r
+    RTC->CONTROL_REG = CONTROL_RTC_START_MASK;\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ * See "mss_rtc.h" for details of how to use this function.\r
+ */\r
+void\r
+MSS_RTC_stop\r
+(\r
+    void\r
+)\r
+{\r
+    uint32_t rtc_running;\r
+    \r
+    /*\r
+     * Send command to stop RTC.\r
+     */\r
+    RTC->CONTROL_REG = CONTROL_RTC_STOP_MASK;\r
+    \r
+    /* \r
+     * Wait for RTC internal synchronization to take place and RTC to actually\r
+     * stop.\r
+     */\r
+    do {\r
+        rtc_running =  RTC->CONTROL_REG & CONTROL_RUNNING_MASK;\r
+    } while(rtc_running);\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+  See "mss_rtc.h" for details of how to use this function.\r
+ */\r
+void\r
+MSS_RTC_reset_counter\r
+(\r
+    void\r
+)\r
+{\r
+    uint32_t upload_in_progress;\r
+    \r
+    RTC->CONTROL_REG = CONTROL_RESET_MASK;\r
+    \r
+    /* Wait for the upload to complete. */\r
+    do {\r
+        upload_in_progress = RTC->CONTROL_REG & CONTROL_UPLOAD_MASK;\r
+    } while(upload_in_progress);\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+  See "mss_rtc.h" for details of how to use this function.\r
+ */\r
+uint32_t MSS_RTC_get_update_flag(void)\r
+{\r
+    uint32_t updated;\r
+    updated = RTC->CONTROL_REG & CONTROL_UPDATED_MASK;\r
+    return updated;\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+  See "mss_rtc.h" for details of how to use this function.\r
+ */\r
+void MSS_RTC_clear_update_flag(void)\r
+{\r
+    /* Clear the "updated" control bit. */\r
+    RTC->CONTROL_REG = CONTROL_UPDATED_MASK;\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+  See "mss_rtc.h" for details of how to use this function.\r
+ */\r
+void MSS_RTC_enable_irq(void)\r
+{\r
+    /*\r
+     * Only the NVIC level interrupt enable is performed within this function.\r
+     * The RTC level interrupt enable is performed within the alarm setting\r
+     * functions.\r
+     * This avoid the MODE register being modified whenever Cortex-M3 RTC\r
+     * interrupts are enabled/disabled. \r
+     */\r
+    NVIC_EnableIRQ(RTC_Wakeup_IRQn);\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+  See "mss_rtc.h" for details of how to use this function.\r
+ */\r
+void\r
+MSS_RTC_disable_irq\r
+(\r
+    void\r
+)\r
+{\r
+    /*\r
+     * Only the NVIC level interrupt disable is performed within this function.\r
+     * This avoid the MODE register being modified whenever Cortex-M3 RTC\r
+     * interrupts are enabled/disabled. \r
+     */\r
+    NVIC_DisableIRQ(RTC_Wakeup_IRQn);\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ * See "mss_rtc.h" for details of how to use this function.\r
+ */\r
+void\r
+MSS_RTC_clear_irq\r
+(\r
+    void\r
+)\r
+{\r
+    /* Clear wake up interrupt signal */\r
+    RTC->CONTROL_REG = CONTROL_WAKEUP_CLR_MASK;\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+  The get_clock_mode() function gets the clock mode of RTC hardware.\r
+  Possible clock modes are:\r
+    MSS_RTC_CALENDAR_MODE\r
+    MSS_RTC_BINARY_MODE\r
+ */\r
+static uint8_t\r
+get_clock_mode\r
+(\r
+    void\r
+)\r
+{\r
+    uint8_t clock_mode;\r
+\r
+    clock_mode = (uint8_t)(RTC->MODE_REG & MODE_CLK_MODE_MASK);\r
+\r
+    return(clock_mode);\r
+}\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
diff --git a/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers/mss_rtc/mss_rtc.h b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers/mss_rtc/mss_rtc.h
new file mode 100644 (file)
index 0000000..af7c106
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers/mss_rtc/mss_rtc.h
@@ -0,0 +1,710 @@
+/*******************************************************************************\r
+ * (c) Copyright 2008-2013 Microsemi SoC Products Group.  All rights reserved.\r
+ * \r
+ *  SmartFusion2 MSS RTC bare metal software driver public API.\r
+ *\r
+ * SVN $Revision: 5396 $\r
+ * SVN $Date: 2013-03-27 21:57:50 +0000 (Wed, 27 Mar 2013) $\r
+ */\r
+\r
+/*=========================================================================*//**\r
+  @mainpage SmartFusion2 MSS RTC Bare Metal Driver.\r
+\r
+  @section intro_sec Introduction\r
+  The SmartFusion2 microcontroller subsystem (MSS) includes a real time counter\r
+  (RTC) that can generate alarms and wakeup interrupts in real time. This\r
+  software driver provides a set of functions for controlling the MSS RTC as\r
+  part of a bare metal system where no operating system is available. The driver\r
+  can be adapted for use as part of an operating system, but the implementation\r
+  of the adaptation layer between the driver and the operating system's driver\r
+  model is outside the scope of the driver.\r
+  \r
+  The MSS RTC driver provides support for the following features:\r
+    - Initialization of the RTC\r
+    - Configuration of the RTC timebase\r
+    - Configuration as a calendar or binary mode counter\r
+    - Set the current calendar or binary mode count\r
+    - Get the current calendar or binary mode count\r
+    - Start and stop the RTC counting\r
+    - Set alarm conditions\r
+    - Enable, disable and clear the wakeup interrupt\r
+    \r
+  @section hw_dependencies Hardware Flow Dependencies\r
+  The configuration of all features of the MSS RTC is covered by this driver\r
+  with the exception of the clock source driving the MSS RTC clock (RTCCLK)\r
+  input. The SmartFusion2 MSS clock controller can supply one of three clock\r
+  sources to the MSS RTC clock input:\r
+    - Crystal Oscillator 32.768 kHz\r
+    - 1MHz Oscillator\r
+    - 50MHz Oscillator.  (25 MHz in a 1.0v part).\r
+  The SmartFusion2 MSS configurator tool in the hardware flow configures one\r
+  of these clocks as the RTCCLK input source.\r
+  The base address and register addresses and interrupt number assignment for\r
+  the MSS RTC block are defined as constants in the SmartFusion2 CMSIS HAL. You\r
+  must ensure that the SmartFusion2 CMSIS HAL is either included in the software\r
+  tool chain used to build your project or is included in your project.\r
+  \r
+  @section theory_op Theory of Operation\r
+  The MSS RTC driver functions are grouped into the following categories:\r
+    - Initialization of the RTC driver and hardware\r
+    - Setting and reading the RTC counter current value\r
+    - Setting RTC alarm values\r
+    - Starting and stopping the RTC\r
+    - Interrupt Control\r
+    \r
+  Initialization\r
+  The MSS RTC driver is initialized through a call to the MSS_RTC_init()\r
+  function. The MSS_RTC_init() function must be called before any other MSS RTC\r
+  driver functions are called.\r
+  The MSS_RTC_init() function:\r
+    - Stops the RTC counters and disables the RTC alarm\r
+    - Disables the RTC wakeup interrupt in the RTC and in the Cortex-M3\r
+      interrupt controller (NVIC).\r
+    - Clears any pending RTC wakeup interrupt in the RTC and in the Cortex-M3\r
+      interrupt controller (NVIC).\r
+    - Enables the RTC_WAKEUP_CR[0] mask bit in the MSS System Register to\r
+      connect the RTC wakeup interrupt to the Cortex-M3 interrupt controller.\r
+    - Resets the RTC counters and the alarm and compare registers\r
+    - Sets the RTC's operating mode to binary counter mode or calendar counter\r
+      mode, as specified by the mode parameter\r
+    - Sets the RTC's prescaler register to the value specified by the prescaler\r
+      parameter. The frequency of the clock source driving the MSS RTC clock\r
+      (RTCCLK) input is required to calculate the prescaler value.\r
+    \r
+  Setting and Reading the RTC Counter Value\r
+  The MSS RTC supports two mode of operation \96 binary mode and calendar mode.\r
+  The following functions are used to set and read the current value of the\r
+  counter when the MSS RTC is configured to operate in binary mode:\r
+    - MSS_RTC_set_binary_count() \96 This function is used to set the current\r
+      value of the RTC binary counter.\r
+    - MSS_RTC_get_binary_count() \96 This function is used to read the current\r
+      value of the RTC binary counter.\r
+  The following functions are used to set and read the current value of the\r
+  counter the MSS RTC is configured to operate in calendar mode:\r
+    - MSS_RTC_set_calendar_count() \96 This function is used to set the current\r
+      value of the RTC calendar counter.\r
+    - MSS_RTC_get_calendar_count() \96 This function is used to read the current\r
+      value of the RTC calendar counter.\r
+ \r
+  The following functions resets the RTC counter in either binary and calendar\r
+  operating mode:\r
+    - MSS_RTC_reset_counter() \96 This function resets the RTC counter.\r
+    \r
+  Setting RTC Alarms\r
+  The MSS RTC can generate alarms when the counter matches a specified count\r
+  value in binary mode or a date and time in calendar mode.\r
+  The following functions are used to set up alarms:\r
+    - MSS_RTC_set_binary_count_alarm() \96 This function sets up one-shot or\r
+      periodic alarms when the MSS RTC is configured to operate in binary mode.\r
+    - MSS_RTC_set_calendar_count_alarm() \96 This function sets up one-shot or\r
+      periodic alarms when the MSS RTC is configured to operate in calendar\r
+      mode.\r
+  Note: The alarm asserts a wakeup interrupt to the Cortex-M3. This function\r
+        enables the RTC\92s wakeup interrupt output, however the RTC wakeup\r
+        interrupt input to the Cortex-M3 NVIC must be enabled separately by\r
+        calling the MSS_RTC_enable_irq() function. The alarm can be disabled at\r
+        any time by calling the MSS_RTC_disable_irq() function. activate\r
+  \r
+  Starting and Stopping the RTC Counter\r
+  The following functions start and stop the RTC counter:\r
+    - MSS_RTC_start() \96 This function starts the RTC counter.\r
+    - MSS_RTC_stop() \96 This function stops the RTC counter.\r
+    \r
+  Interrupt Control\r
+  The MSS_RTC_init() function enables the RTC_WAKEUP_CR[0] mask bit in the MSS\r
+  System Register to connect the RTC wakeup interrupt to the Cortex-M3 interrupt\r
+  controller.\r
+  An RTC_Wakeup_IRQHandler() default implementation is defined, with weak\r
+  linkage, in the SmartFusion2 CMSIS HAL. You must provide your own\r
+  implementation of the RTC_Wakeup_IRQHandler() function, which will override\r
+  the default implementation, to suit your application.\r
+  The function prototype for the RTC wakeup interrupt handler is as follows:\r
+    void RTC_Wakeup_IRQHandler ( void )\r
+  The RTC wakeup interrupt is controlled using the following functions:\r
+    - MSS_RTC_enable_irq() \96 The MSS_RTC_enable_irq() function enables the RTC\r
+      to interrupt the Cortex-M3 when a wakeup alarm occurs.\r
+    - MSS_RTC_disable_irq() \96 The MSS_RTC_disable_irq() function disables the\r
+      RTC from interrupting the Cortex-M3 when a wakeup alarm occurs.\r
+    - MSS_RTC_clear_irq() \96 The MSS_RTC_clear_irq() function clears a pending\r
+      RTC wakeup interrupt at the RTC wakeup output. You must call the\r
+      MSS_RTC_clear_irq() function as part of your implementation of the\r
+      RTC_Wakeup_IRQHandler() interrupt service routine (ISR) in order to\r
+      prevent the same interrupt event retriggering a call to the ISR.\r
+\r
+ *//*=========================================================================*/\r
+#ifndef MSS_RTC_H_\r
+#define MSS_RTC_H_\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif \r
+\r
+#include "../../CMSIS/m2sxxx.h"\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+  The MSS_RTC_BINARY_MODE constant is used to specify the mode parameter to the\r
+  MSS_RTC_init() function. The RTC will run in binary mode if this constant is\r
+  used. In binary mode, the calendar counter counts consecutively from 0 all the\r
+  way to 2^43.\r
+ */\r
+#define MSS_RTC_BINARY_MODE               0u\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+  The MSS_RTC_CALENDAR_MODE constant is used to specify the mode parameter to\r
+  the MSS_RTC_init() function. The RTC will run in calendar mode if this\r
+  constant is used. In calendar mode, the calendar counter counts seconds,\r
+  minutes, hours, days, months, years, weekdays and weeks.\r
+ */\r
+#define MSS_RTC_CALENDAR_MODE             1u\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+  The alarm_value parameter of the MSS_RTC_set_calendar_count_alarm() function\r
+  is a pointer to an mss_rtc_calendar_t data structure specifying the date and\r
+  time at which the alarm is to occur. You must assign the required date and\r
+  time values to the mss_rtc_calendar_t structure before calling the function.\r
+  Any of the fields of the mss_rtc_calendar_t structure can be set to\r
+  MSS_RTC_CALENDAR_DONT_CARE, to indicate that they are not to be considered in\r
+  deciding when the alarm will occur; this is necessary when setting periodic\r
+  alarms. \r
+ */\r
+#define MSS_RTC_CALENDAR_DONT_CARE      0xFFu\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+  Days of the week.\r
+ */\r
+#define MSS_RTC_SUNDAY      1u\r
+#define MSS_RTC_MONDAY      2u\r
+#define MSS_RTC_TUESDAY     3u\r
+#define MSS_RTC_WEDNESDAY   4u\r
+#define MSS_RTC_THRUSDAY    5u\r
+#define MSS_RTC_FRIDAY      6u\r
+#define MSS_RTC_SATURDAY    7u\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+  The mss_rtc_alarm_type_t enumeration is used as the alarm_type parameter for\r
+  the MSS_RTC_set_calendar_count_alarm() and MSS_RTC_set_binary_count_alarm()\r
+  functions to specify whether the requested alarm should occur only one time or\r
+  periodically.\r
+ */\r
+typedef enum {\r
+    MSS_RTC_SINGLE_SHOT_ALARM,\r
+    MSS_RTC_PERIODIC_ALARM\r
+} mss_rtc_alarm_type_t;\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+  A pointer to an instance of the mss_rtc_calender_t data structure is used to\r
+  write new date and time values to the RTC using the\r
+  MSS_RTC_set_rtc_calendar_count() and MSS_RTC_set_calendar_count_alarm()\r
+  functions. The MSS_RTC_get_calendar_count() function also uses a pointer to an\r
+  instance of the mss_rtc_calender_t data structure to read the current date and\r
+  time value from the RTC.\r
+ */\r
+typedef struct mss_rtc_calendar\r
+{\r
+     uint8_t second;\r
+     uint8_t minute;\r
+     uint8_t hour;\r
+     uint8_t day;\r
+     uint8_t month;\r
+     uint8_t year;\r
+     uint8_t weekday;\r
+     uint8_t week;\r
+} mss_rtc_calendar_t ;\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+  The MSS_RTC_init() function initializes the RTC driver and hardware to a known\r
+  state. \r
+  To initialize the RTC hardware, this function:\r
+    - Stops the RTC counters and disables the RTC alarm\r
+    - Disables the RTC wakeup interrupt in the RTC and in the Cortex-M3\r
+      interrupt controller (NVIC).\r
+    - Clears any pending RTC wakeup interrupt in the RTC and in the Cortex-M3\r
+      interrupt controller (NVIC).\r
+    - Resets the RTC counters and the alarm and compare registers\r
+    - Sets the RTC's operating mode to binary counter mode or calendar counter\r
+      mode, as specified by the mode parameter\r
+    - Sets the RTC's prescaler register to the value specified by the prescaler\r
+      parameter\r
+  The MSS clock controller can supply one of three clock sources to the RTC\r
+  clock input (RTCCLK):\r
+    - Crystal Oscillator 32.768 kHz\r
+    - 1MHz Oscillator\r
+    - 50MHz Oscillator.  (25 MHz in a 1.0v part).\r
+  For calendar mode, program the prescaler register to generate a 1Hz signal\r
+  from the active RTCCLK according to the following equation:\r
+    prescaler = RTCCLK \96 1 (where RTCCLK unit is Hz)\r
+  For a 32.768 kHz clock, set the prescaler to 32768 - 1 = 32767. The prescaler\r
+  register is 26 bits wide, allowing clock sources of up to 67 MHz to generate\r
+  the 1Hz time base.\r
+  For binary mode, the prescaler register can be programmed to generate a 1Hz\r
+  time base or a different time base, as required.\r
+  \r
+  @param mode\r
+    The mode parameter is used to specify the operating mode of the RTC. The\r
+    allowed values for mode are:\r
+      - MSS_RTC_BINARY_MODE\r
+      - MSS_RTC_CALENDAR_MODE\r
+    \r
+  @param prescaler\r
+    The prescaler parameter specifies the value to divide the incoming RTC clock\r
+    by, to generate the RTC time base signal. For calendar mode, set the\r
+    prescaler value to generate a 1Hz time base from the incoming RTC clock\r
+    according to the following equation:\r
+        prescaler = RTCCLK \96 1    (where the RTCCLK unit is Hz)\r
+    For binary mode, set the prescaler value to generate a 1Hz time base or a\r
+    different time base, as required.\r
+    The prescaler parameter can be any integer value in the range 2 to 2^26.\r
+    \r
+  @return\r
+    This function does not return a value.\r
+    \r
+  The example code below shows how the RTC can be initialized only after a power-on\r
+  reset.\r
+  @code\r
+    #define PO_RESET_DETECT_MASK    0x00000001u\r
+    \r
+    void init_application(void)\r
+    {\r
+        uint32_t power_on_reset;\r
+        power_on_reset = SYSREG->RESET_SOURCE_CR & PO_RESET_DETECT_MASK;\r
+        if(power_on_reset)\r
+        {\r
+            MSS_RTC_init(MSS_RTC_CALENDAR_MODE, 32767);\r
+            SYSREG->RESET_SOURCE_CR = PO_RESET_DETECT_MASK;\r
+        }\r
+    }\r
+  @endcode\r
+ */\r
+void\r
+MSS_RTC_init\r
+(\r
+    uint8_t mode,\r
+    uint32_t prescaler\r
+);\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+  The MSS_RTC_set_rtc_calendar_count() function sets the current value of the\r
+  RTC calendar counter.\r
+  Note: This function must only be used when the RTC is configured to operate in\r
+        calendar counter mode.\r
+        \r
+  @param new_rtc_value\r
+    The new_rtc_value parameter is a pointer to an mss_rtc_calendar_t data\r
+    structure specifying the new date and time value from which the RTC will\r
+    increment. You must populate the mss_rtc_calendar_t structure with the\r
+    required date and time values before calling this function.\r
+    \r
+  @return\r
+    This function does not return a value.\r
+ */\r
+\r
+void\r
+MSS_RTC_set_calendar_count\r
+(\r
+    const mss_rtc_calendar_t *new_rtc_value\r
+);\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+  The MSS_RTC_set_binary_count() function sets the current value of the RTC\r
+  binary counter.\r
+  Note: This function must only be used when the RTC is configured to operate in\r
+        binary counter mode.\r
+        \r
+  @param new_rtc_value\r
+    The new_rtc_value parameter specifies the new count value from which the RTC\r
+    will increment. The binary counter is 43 bits wide, so the maximum allowed\r
+    binary value is 2^43.\r
+\r
+  @return\r
+    This function does not return a value.\r
+ */\r
+\r
+void\r
+MSS_RTC_set_binary_count\r
+(\r
+    uint64_t new_rtc_value\r
+);\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+  The MSS_RTC_get_calendar_count() function returns the current value of the RTC\r
+  calendar counter via the data structure pointed to by the p_rtc_calendar\r
+  parameter.\r
+  Note: This function must only be used when the RTC is configured to operate in\r
+        calendar counter mode.\r
+        \r
+  @param p_rtc_calendar\r
+    The p_rtc_calendar parameter is a pointer to an mss_rtc_calendar_t data\r
+    structure where the current value of the calendar counter will be written by\r
+    the MSS_RTC_get_calendar_count() function\r
+    \r
+  @return\r
+    This function does not return a value.\r
+ */\r
+void\r
+MSS_RTC_get_calendar_count\r
+(\r
+    mss_rtc_calendar_t *p_rtc_calendar\r
+);\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+  The MSS_RTC_get_binary_count() function returns the current value of the RTC\r
+  binary counter. \r
+  Note: This function must only be used when the RTC is configured to operate in\r
+        binary counter mode.\r
+        \r
+  @param\r
+    This function takes no parameters.\r
+\r
+  @return\r
+    This function returns the current value of the RTC binary counter as an\r
+    unsigned 64-bit integer.\r
+ */\r
+uint64_t\r
+MSS_RTC_get_binary_count(void);\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+  The MSS_RTC_start() function starts the RTC incrementing.\r
+\r
+  @param\r
+    This function takes no parameters.\r
+\r
+  @return\r
+    This function does not return a value.\r
+ */\r
+void MSS_RTC_start(void);\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+  The MSS_RTC_stop() function stops the RTC from incrementing.\r
+\r
+  @param\r
+    This function takes no parameters.\r
+\r
+  @return\r
+    This function does not return a value.\r
+ */\r
+void MSS_RTC_stop(void);\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+  The MSS_RTC_reset_counter() function resets the RTC counters. If the counter\r
+  was running before calling this function, then it continues incrementing from\r
+  the counter\92s reset value.\r
+  \r
+  @param\r
+    This function takes no parameters.\r
+\r
+  @return\r
+    This function does not return a value.\r
+ */\r
+void MSS_RTC_reset_counter(void);\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+  The MSS_RTC_enable_irq() function enables the RTC wakeup output to interrupt\r
+  the Cortex-M3 when an alarm occurs. It enables the RTC wakeup interrupt\r
+  (RTC_Wakeup_IRQn) in the Cortex-M3 interrupt controller (NVIC). The\r
+  RTC_Wakeup_IRQHandler() function will be called when an RTC wakeup interrupt\r
+  occurs.\r
+  Note: An RTC_Wakeup_IRQHandler() default implementation is defined, with weak\r
+        linkage, in the SmartFusion2 CMSIS HAL. You must provide your own\r
+        implementation of the RTC_Wakeup_IRQHandler() function, which will\r
+        override the default implementation, to suit your application.\r
+  Note: This function only enables the RTC wakeup interrupt at the Cortex-M3\r
+        NVIC level. The alarm setting functions enable the wakeup interrupt\r
+        output from the RTC.\r
+ */\r
+void MSS_RTC_enable_irq(void);\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+  The MSS_RTC_disable_irq() function disables the RTC wakeup interrupt\r
+  (RTC_Wakeup_IRQn) in the Cortex-M3 interrupt controller (NVIC).\r
+  Note: This function only disables the RTC wakeup interrupt at the Cortex-M3\r
+        NVIC level. It does not disable the wakeup interrupt output from the\r
+        RTC.\r
+        \r
+   @param\r
+     This function takes no parameters.\r
+\r
+   @return\r
+     This function does not return a value.\r
+ */\r
+void MSS_RTC_disable_irq(void);\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+  The MSS_RTC_clear_irq() function clears a pending wakeup interrupt from the\r
+  RTC. This function does not clear the interrupt in the Cortex-M3 interrupt\r
+  controller (NVIC); it only clears the wakeup output from the RTC.\r
+  Note: You must call the MSS_RTC_clear_irq() function as part of your\r
+        implementation of the RTC_Wakeup_IRQHandler() RTC wakeup interrupt\r
+        service routine (ISR) in order to prevent the same interrupt event\r
+        retriggering a call to the ISR.\r
+        \r
+  @param\r
+    This function takes no parameters.\r
+\r
+  @return\r
+    This function does not return a value.\r
+  \r
+  Example:\r
+  The example code below demoinstrates how the MSS_RTC_clear_irq() function is\r
+  intended to be used as part of the RTC wakeup interrupt servicer routine used\r
+  by an application to handle RTC alarms.\r
+  @code\r
+    #if defined(__GNUC__)\r
+    __attribute__((__interrupt__)) void RTC_Wakeup_IRQHandler( void )\r
+    #else\r
+    void RTC_Wakeup_IRQHandler( void )\r
+    #endif\r
+    {\r
+        process_alarm();\r
+        MSS_RTC_clear_irq();\r
+    }\r
+  @endcode\r
+*/\r
+void MSS_RTC_clear_irq(void);\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+  The MSS_RTC_set_calendar_count_alarm() function sets up the RTC to generate an\r
+  alarm when the RTC count reaches the time/date specified by the alarm_value\r
+  parameter. The alarm asserts a wakeup interrupt to the Cortex-M3. This\r
+  function enables the RTC\92s wakeup interrupt output, however the RTC wakeup\r
+  interrupt input to the Cortex-M3 NVIC must be enabled separately by calling\r
+  the MSS_RTC_enable_irq() function. The alarm can be disabled at any time by\r
+  calling the MSS_RTC_disable_irq() function.\r
+  \r
+  Single-shot alarm\r
+  The alarm can be a single-shot alarm, which will generate a single wakeup\r
+  interrupt the first time the RTC count reaches the time/date specified by\r
+  alarm_value. A single shot alarm is achieved by specifying a value for every\r
+  field of the mss_rtc_calendar_t data structure pointed to by the alarm_value\r
+  parameter. The RTC counter will keep incrementing after a single shot alarm\r
+  occurs.\r
+  \r
+  Periodic alarm\r
+  The alarm can also be a periodic alarm, which will generate a wakeup interrupt\r
+  every time the RTC count reaches the time/date specified by alarm_value, with\r
+  the counter running in a continuous loop. The periodic alarm can be set to\r
+  occur every minute, hour, day, month, year, week, day of the week, or any\r
+  valid combination of these. This is achieved by setting some of the fields of\r
+  the mss_rtc_calendar_t data structure pointed to by the alarm_value parameter,\r
+  to MSS_RTC_CALENDAR_DONT_CARE. For example, setting the weekday field to\r
+  MSS_RTC_MONDAY and all other fields to MSS_RTC_CALENDAR_DONT_CARE will result\r
+  in an alarm occurring every Monday. You can refine the time at which the alarm\r
+  will occur by specifying values for the hour, minute and second fields.\r
+  Note: This function must only be used when the RTC is configured to operate in\r
+        calendar counter mode.\r
+  \r
+  @param alarm_value\r
+    The alarm_value parameter is a pointer to an mss_rtc_calendar_t data\r
+    structure specifying the date and time at which the alarm is to occur. You\r
+    must assign the required date and time values to the mss_rtc_calendar_t\r
+    structure before calling this function. Some of the fields within the\r
+    mss_rtc_calendar_t structure can be set to MSS_RTC_CALENDAR_DONT_CARE, to\r
+    indicate that they are not to be considered in deciding when the alarm will\r
+    occur; this is necessary when setting periodic alarms.\r
+  \r
+  @return\r
+    This function does not return a value.\r
+     \r
+  Examples:\r
+  \r
+  The following example code demonstrates how to configure the RTC to generate a\r
+  single calendar alarm at a specific date and time. The alarm will only occur\r
+  once and the RTC will keep incrementing regardless of the alarm taking place.\r
+  \r
+  @code\r
+    const mss_rtc_calendar_t initial_calendar_count =\r
+    {\r
+        15u,     second\r
+        30u,     minute\r
+        6u,      hour\r
+        6u,      day\r
+        9u,      month\r
+        12u,     year\r
+        5u,      weekday\r
+        37u      week\r
+    };\r
+    \r
+    mss_rtc_calendar_t alarm_calendar_count =\r
+    {\r
+        17u,     second\r
+        30u,     minute\r
+        6u,      hour\r
+        6u,      day\r
+        9u,      month\r
+        12u,     year\r
+        5u,      weekday\r
+        37u      week\r
+    };\r
+    \r
+    MSS_RTC_init(MSS_RTC_CALENDAR_MODE, RTC_PRESCALER);\r
+    MSS_RTC_clear_irq();\r
+    MSS_RTC_set_calendar_count(&initial_calendar_count);\r
+    MSS_RTC_enable_irq();\r
+    MSS_RTC_start();\r
+    \r
+    MSS_RTC_set_calendar_count_alarm(&alarm_calendar_count);\r
+  @endcode\r
+  \r
+  The following example code demonstrates how to configure the RTC to generate a\r
+  periodic calendar alarm. The RTC is configured to generate an alarm every\r
+  Tuesday at 16:45:00. The alarm will reoccur every week until the RTC wakeup\r
+  interrupt is disabled using a call to MSS_RTC_disable_irq().\r
+  \r
+  @code\r
+    mss_rtc_calendar_t initial_calendar_count =\r
+    {\r
+        58u,                            <--second\r
+        59u,                            <--minute\r
+        23u,                            <--hour\r
+        10u,                            <--day\r
+        9u,                             <--month\r
+        12u,                            <--year\r
+        MSS_RTC_MONDAY,                 <--weekday\r
+        37u                             <--week\r
+    };\r
+    \r
+    mss_rtc_calendar_t alarm_calendar_count =\r
+    {\r
+        MSS_RTC_CALENDAR_DONT_CARE,     <--second\r
+        45u,                            <--minute\r
+        16u,                            <--hour\r
+        MSS_RTC_CALENDAR_DONT_CARE,     <--day\r
+        MSS_RTC_CALENDAR_DONT_CARE,     <--month\r
+        MSS_RTC_CALENDAR_DONT_CARE,     <--year\r
+        MSS_RTC_TUESDAY,                <--weekday\r
+        MSS_RTC_CALENDAR_DONT_CARE      <--week\r
+    };\r
+    \r
+    MSS_RTC_init(MSS_RTC_CALENDAR_MODE, RTC_PRESCALER);\r
+    MSS_RTC_set_calendar_count(&initial_calendar_count);\r
+    MSS_RTC_enable_irq();\r
+    MSS_RTC_start();\r
+    \r
+    MSS_RTC_set_calendar_count_alarm(&alarm_calendar_count);\r
+  @endcode\r
+  \r
+  The following example code demonstrates the code that you need to include in\r
+  your application to handle alarms. It is the interrupt service routine for the\r
+  RTC wakeup interrupt input to the Cortex-M3 NVIC. You need to add your\r
+  application code in this function in place of the process_alarm() function but\r
+  you must retain the call to MSS_RTC_clear_irq() to ensure that the same alarm\r
+  does not retrigger the interrupt.\r
+  \r
+  @code\r
+    #if defined(__GNUC__)\r
+    __attribute__((__interrupt__)) void RTC_Wakeup_IRQHandler( void )\r
+    #else\r
+    void RTC_Wakeup_IRQHandler( void )\r
+    #endif\r
+    {\r
+        process_alarm();\r
+        MSS_RTC_clear_irq();\r
+    }\r
+  @endcode\r
+ */\r
+void MSS_RTC_set_calendar_count_alarm\r
+(\r
+    const mss_rtc_calendar_t * alarm_value\r
+);\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+  The MSS_RTC_set_binary_count_alarm() function sets up the RTC to generate an\r
+  alarm when the RTC count reaches the value specified by the alarm_value\r
+  parameter. The alarm asserts a wakeup interrupt to the Cortex-M3. This\r
+  function enables the RTC\92s wakeup interrupt output, however the RTC wakeup\r
+  interrupt input to the Cortex-M3 NVIC must be enabled separately by calling\r
+  the MSS_RTC_enable_irq() function. The alarm can be disabled at any time by\r
+  calling the MSS_RTC_disable_irq() function.\r
+\r
+  Single-shot alarm\r
+  The alarm can be a single-shot alarm, which will generate a single wakeup\r
+  interrupt the first time the RTC count reaches the value specified by the\r
+  alarm_value parameter. Setting the alarm_value parameter to\r
+  MSS_RTC_PERIODIC_ALARM produces a single-shot alarm. The RTC counter continues\r
+  incrementing when a single shot alarm occurs.\r
+\r
+  Periodic alarm\r
+  The alarm can also be a periodic alarm, which will generate a wakeup interrupt\r
+  every time the RTC count reaches the value specified by the alarm_value\r
+  parameter. Setting the alarm_value parameter to MSS_RTC_SINGLE_SHOT_ALARM\r
+  produces a periodic alarm. The RTC counter automatically wraps around to zero\r
+  and continues incrementing when a periodic alarm occurs.\r
+  Note: This function must only be used when the RTC is configured to operate in\r
+        binary counter mode\r
+  \r
+  @param alarm_value\r
+    The alarm_value parameter is a 64-bit unsigned value specifying the RTC\r
+    counter value that must be reached for the requested alarm to occur.\r
+  \r
+  @param alarm_type\r
+    The alarm_type parameter specifies whether the requested alarm is a single\r
+    shot or periodic alarm. It can only take one of these two values:\r
+     - MSS_RTC_SINGLE_SHOT_ALARM,\r
+     - MSS_RTC_PERIODIC_ALARM\r
+  \r
+  @return\r
+    This function does not return a value.\r
+ */\r
+void MSS_RTC_set_binary_count_alarm\r
+(\r
+    uint64_t alarm_value,\r
+    mss_rtc_alarm_type_t alarm_type\r
+);\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+  The MSS_RTC_get_update_flag() function indicates if the RTC counter has\r
+  incremented since the last call to MSS_RTC_clear_update_flag(). It returns\r
+  zero if no RTC counter increment has occurred. It returns a non-zero value if\r
+  the RTC counter has incremented. This function can be used whether the RTC is\r
+  configured to operate in calendar or binary counter mode.\r
+  \r
+  @return\r
+   This function returns, \r
+   zero:     if the RTC has not incremented since the last call to\r
+             MSS_RTC_clear_update_flag(), \r
+   non-zero: if the RTC has incremented since the last call to\r
+             MSS_RTC_clear_update_flag().\r
+\r
+   \r
+  Example\r
+  This example waits for the RTC timer to increment by one second.\r
+  @code\r
+    void wait_start_of_second(void)\r
+    {\r
+        uint32_t rtc_count_updated;\r
+        MSS_RTC_clear_update_flag();\r
+        do {\r
+            rtc_count_updated = MSS_RTC_get_update_flag();\r
+        } while(!rtc_count_updated)\r
+    }\r
+  @endcode\r
+ */\r
+uint32_t MSS_RTC_get_update_flag(void);\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+  The MSS_RTC_clear_update_flag() function clears the CONTROL register flag that\r
+  is set when the RTC counter increments. It is used alongside function\r
+  MSS_RTC_get_update_flag() to detect RTC counter increments.\r
+  \r
+  @return\r
+    This function does not return a value.\r
+    \r
+  Example\r
+  The example below will wait for the RTC timer to increment by one second.\r
+  @code\r
+  void wait_start_of_second(void)\r
+  {\r
+      uint32_t rtc_count_updated;\r
+      MSS_RTC_clear_update_flag();\r
+      do {\r
+          rtc_count_updated = MSS_RTC_get_update_flag();\r
+      } while(!rtc_count_updated)\r
+  }\r
+  @endcode\r
+ */\r
+void MSS_RTC_clear_update_flag(void);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* MSS_RTC_H_ */\r
diff --git a/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers/mss_sys_services/mss_comblk.c b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers/mss_sys_services/mss_comblk.c
new file mode 100644 (file)
index 0000000..c0c2e3a
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers/mss_sys_services/mss_comblk.c
@@ -0,0 +1,703 @@
+/*******************************************************************************\r
+ * (c) Copyright 2012 Microsemi SoC Products Group.  All rights reserved.\r
+ *\r
+ * SmartFusion2 COMBLK access functions.\r
+ *\r
+ * SVN $Revision: 5615 $\r
+ * SVN $Date: 2013-04-05 14:48:10 +0100 (Fri, 05 Apr 2013) $\r
+ */\r
+ \r
+#include "mss_comblk.h"\r
+#include "../../CMSIS/mss_assert.h"\r
+\r
+/*==============================================================================\r
+ *\r
+ */\r
+/*------------------------------------------------------------------------------\r
+ * Control register bit masks.\r
+ */\r
+#define CR_FLUSHOUT_MASK    0x01u\r
+#define CR_SIZETX_MASK      0x04u\r
+#define CR_ENABLE_MASK      0x10u\r
+#define CR_LOOPBACK_MASK    0x20u\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Status and interrupt enable registers bit masks.\r
+ */\r
+#define TXTOKAY_MASK    0x01u\r
+#define RCVOKAY_MASK    0x02u\r
+\r
+/*------------------------------------------------------------------------------\r
+ * DATA8 register bit masks.\r
+ */\r
+#define DATA8_COMMAND_MASK  0x8000u\r
+\r
+/*------------------------------------------------------------------------------\r
+ * COMBLK driver states.\r
+ */\r
+#define COMBLK_IDLE             0u\r
+#define COMBLK_TX_CMD           1u\r
+#define COMBLK_TX_DATA          2u\r
+#define COMBLK_WAIT_RESPONSE    3u\r
+#define COMBLK_RX_RESPONSE      4u\r
+#define COMBLK_TX_PAGED_DATA    5u\r
+\r
+/*==============================================================================\r
+ * COMBLK interrupt servcie routine.\r
+ */\r
+void ComBlk_IRQHandler(void);\r
+\r
+/*==============================================================================\r
+ * Local functions.\r
+ */\r
+static void abort_current_cmd(void);\r
+static void send_cmd_opcode(uint8_t opcode);\r
+static uint32_t fill_tx_fifo(const uint8_t * p_cmd, uint32_t cmd_size);\r
+static void handle_tx_okay_irq(void);\r
+static void handle_rx_okay_irq(void);\r
+static void complete_request(uint16_t response_length);\r
+static void process_sys_ctrl_command(uint8_t cmd_opcode);\r
+\r
+/*==============================================================================\r
+ * Global variables:\r
+ */\r
+static volatile uint8_t g_comblk_cmd_opcode = 0u;\r
+static const uint8_t * g_comblk_p_cmd = 0u;\r
+static volatile uint16_t g_comblk_cmd_size = 0u;\r
+static const uint8_t * g_comblk_p_data = 0u;\r
+static volatile uint32_t g_comblk_data_size = 0u;\r
+static uint8_t * g_comblk_p_response = 0u;\r
+static uint16_t g_comblk_response_size = 0u;\r
+static volatile uint16_t g_comblk_response_idx = 0u;\r
+static comblk_completion_handler_t g_comblk_completion_handler = 0;\r
+\r
+/*typedef uint32_t (*comblk_page_handler_t)(uint8_t const ** pp_next_page);\r
+*/\r
+static uint32_t (*g_comblk_page_handler)(uint8_t const ** pp_next_page) = 0;\r
+\r
+static uint8_t g_request_in_progress = 0u;\r
+\r
+static uint8_t g_comblk_state = COMBLK_IDLE;\r
+\r
+static comblk_async_event_handler_t g_async_event_handler = 0;\r
+\r
+/*==============================================================================\r
+ *\r
+ */\r
+void MSS_COMBLK_init(comblk_async_event_handler_t async_event_handler)\r
+{\r
+    /*\r
+     * Disable and clear previous interrupts.\r
+     */\r
+    NVIC_DisableIRQ(ComBlk_IRQn);\r
+    COMBLK->INT_ENABLE = 0u;\r
+    NVIC_ClearPendingIRQ(ComBlk_IRQn);\r
+    \r
+    g_async_event_handler = async_event_handler;\r
+    \r
+    /*\r
+     * Initialialize COMBLK driver state variables:\r
+     */\r
+    g_request_in_progress = 0u;\r
+    g_comblk_cmd_opcode = 0u;\r
+    g_comblk_p_cmd = 0u;\r
+    g_comblk_cmd_size = 0u;\r
+    g_comblk_p_data = 0u;\r
+    g_comblk_data_size = 0u;\r
+    g_comblk_p_response = 0u;\r
+    g_comblk_response_size = 0u;\r
+    g_comblk_response_idx = 0u;\r
+    g_comblk_completion_handler = 0;\r
+    \r
+    g_comblk_state = COMBLK_IDLE;\r
+    \r
+    COMBLK->CONTROL |= CR_ENABLE_MASK;\r
+    COMBLK->CONTROL &= ~CR_LOOPBACK_MASK;\r
+    \r
+    /*--------------------------------------------------------------------------\r
+     * Enable receive interrupt to receive asynchronous events from the system\r
+     * controller.\r
+     */\r
+    COMBLK->INT_ENABLE &= ~TXTOKAY_MASK;\r
+    COMBLK->INT_ENABLE |= RCVOKAY_MASK;\r
+    NVIC_EnableIRQ(ComBlk_IRQn);\r
+}\r
+\r
+/*==============================================================================\r
+ *\r
+ */\r
+void MSS_COMBLK_send_cmd_with_ptr\r
+(\r
+    uint8_t cmd_opcode,\r
+    uint32_t cmd_params_ptr,\r
+    uint8_t * p_response,\r
+    uint16_t response_size,\r
+    comblk_completion_handler_t completion_handler\r
+)\r
+{\r
+    uint32_t tx_okay;\r
+    \r
+    /*--------------------------------------------------------------------------\r
+     * Disable and clear previous interrupts.\r
+     */\r
+    NVIC_DisableIRQ(ComBlk_IRQn);\r
+    COMBLK->INT_ENABLE = 0u;\r
+    NVIC_ClearPendingIRQ(ComBlk_IRQn);\r
+    \r
+    /*--------------------------------------------------------------------------\r
+     * Abort current command if any.\r
+     */\r
+    abort_current_cmd();\r
+    \r
+    /*--------------------------------------------------------------------------\r
+     * Initialialize COMBLK driver state variables:\r
+     */\r
+    g_request_in_progress = 1u;\r
+    g_comblk_cmd_opcode = cmd_opcode;\r
+    g_comblk_p_cmd = 0u;\r
+    g_comblk_cmd_size = 0u;\r
+    g_comblk_p_data = 0u;\r
+    g_comblk_data_size = 0u;\r
+    g_comblk_p_response = p_response;\r
+    g_comblk_response_size = response_size;\r
+    g_comblk_response_idx = 0u;\r
+    g_comblk_page_handler = 0u;\r
+    g_comblk_completion_handler = completion_handler;\r
+    \r
+    /*--------------------------------------------------------------------------\r
+     * Send command opcode as a single byte write to the Tx FIFO.\r
+     */\r
+    send_cmd_opcode(g_comblk_cmd_opcode);\r
+    \r
+    /*--------------------------------------------------------------------------\r
+     * Send the command parameters pointer to the Tx FIFO as a single 4 bytes\r
+     * write to the Tx FIFO.\r
+     */\r
+    COMBLK->CONTROL |= CR_SIZETX_MASK;\r
+    \r
+    /* Wait for space to become available in Tx FIFO. */\r
+    do {\r
+        tx_okay = COMBLK->STATUS & TXTOKAY_MASK;\r
+    } while(0u == tx_okay);\r
+    \r
+    /* Send command opcode. */\r
+    COMBLK->DATA32 = cmd_params_ptr;\r
+    \r
+    COMBLK->CONTROL &= ~CR_SIZETX_MASK;\r
+    \r
+    g_comblk_state = COMBLK_WAIT_RESPONSE;\r
+    \r
+    /*--------------------------------------------------------------------------\r
+     * Enable interrupt.\r
+     */\r
+    COMBLK->INT_ENABLE |= RCVOKAY_MASK;\r
+    NVIC_EnableIRQ(ComBlk_IRQn);\r
+}\r
+\r
+/*==============================================================================\r
+ *\r
+ */\r
+void MSS_COMBLK_send_cmd\r
+(\r
+    const uint8_t * p_cmd,\r
+    uint16_t cmd_size,\r
+    const uint8_t * p_data,\r
+    uint32_t data_size,\r
+    uint8_t * p_response,\r
+    uint16_t response_size,\r
+    comblk_completion_handler_t completion_handler\r
+)\r
+{\r
+    uint32_t size_sent;\r
+    \r
+    ASSERT(cmd_size > 0);\r
+    \r
+    /*\r
+     * Disable and clear previous interrupts.\r
+     */\r
+    NVIC_DisableIRQ(ComBlk_IRQn);\r
+    COMBLK->INT_ENABLE = 0u;\r
+    NVIC_ClearPendingIRQ(ComBlk_IRQn);\r
+    \r
+    /*\r
+     * Abort current command if any.\r
+     */\r
+    abort_current_cmd();\r
+    \r
+    /*\r
+     * Initialialize COMBLK driver state variables:\r
+     */\r
+    g_request_in_progress = 1u;\r
+    g_comblk_cmd_opcode = p_cmd[0];\r
+    g_comblk_p_cmd = p_cmd;\r
+    g_comblk_cmd_size = cmd_size;\r
+    g_comblk_p_data = p_data;\r
+    g_comblk_data_size = data_size;\r
+    g_comblk_p_response = p_response;\r
+    g_comblk_response_size = response_size;\r
+    g_comblk_response_idx = 0u;\r
+    g_comblk_page_handler = 0u;\r
+    g_comblk_completion_handler = completion_handler;\r
+    \r
+    COMBLK->INT_ENABLE |= RCVOKAY_MASK;\r
+\r
+    /*\r
+     * Fill FIFO with command.\r
+     */\r
+    send_cmd_opcode(g_comblk_cmd_opcode);\r
+    size_sent = fill_tx_fifo(&p_cmd[1], cmd_size - 1u);\r
+    ++size_sent;    /* Adjust for opcode byte sent. */\r
+    if(size_sent < cmd_size)\r
+    {\r
+        g_comblk_cmd_size = g_comblk_cmd_size - (uint16_t)size_sent;\r
+        g_comblk_p_cmd = &g_comblk_p_cmd[size_sent];\r
+        \r
+        g_comblk_state = COMBLK_TX_CMD;\r
+    }\r
+    else\r
+    {\r
+        g_comblk_cmd_size = 0u;\r
+        if(g_comblk_data_size > 0u)\r
+        {\r
+            g_comblk_state = COMBLK_TX_DATA;\r
+        }\r
+        else\r
+        {\r
+            g_comblk_state = COMBLK_WAIT_RESPONSE;\r
+        }\r
+    }\r
+\r
+    /*\r
+     * Enable interrupt.\r
+     */\r
+    NVIC_EnableIRQ(ComBlk_IRQn);\r
+}\r
+\r
+/*==============================================================================\r
+ *\r
+ */\r
+void MSS_COMBLK_send_paged_cmd\r
+(\r
+    const uint8_t * p_cmd,\r
+    uint16_t cmd_size,\r
+    uint8_t * p_response,\r
+    uint16_t response_size,\r
+    uint32_t (*page_read_handler)(uint8_t const **),\r
+    void (*completion_handler)(uint8_t *, uint16_t)\r
+)\r
+{\r
+    uint32_t size_sent;\r
+    uint8_t irq_enable = 0u;\r
+    \r
+    ASSERT(cmd_size > 0u);\r
+    \r
+    /*\r
+     * Disable and clear previous interrupts.\r
+     */\r
+    NVIC_DisableIRQ(ComBlk_IRQn);\r
+    COMBLK->INT_ENABLE = 0u;\r
+    NVIC_ClearPendingIRQ(ComBlk_IRQn);\r
+    \r
+    /*\r
+     * Abort current command if any.\r
+     */\r
+    abort_current_cmd();\r
+    \r
+    /*\r
+     * Initialialize COMBLK driver state variables:\r
+     */\r
+    g_request_in_progress = 1u;\r
+    g_comblk_cmd_opcode = p_cmd[0];\r
+    g_comblk_p_cmd = p_cmd;\r
+    g_comblk_cmd_size = cmd_size;\r
+    g_comblk_p_data = 0;\r
+    g_comblk_data_size = 0u;\r
+    g_comblk_p_response = p_response;\r
+    g_comblk_response_size = response_size;\r
+    g_comblk_response_idx = 0u;\r
+    g_comblk_page_handler = page_read_handler;\r
+    g_comblk_completion_handler = completion_handler;\r
+    \r
+    /*\r
+     * Fill FIFO with command.\r
+     */\r
+    send_cmd_opcode(g_comblk_cmd_opcode);\r
+    size_sent = fill_tx_fifo(&p_cmd[1], cmd_size - 1u);\r
+    ++size_sent;    /* Adjust for opcode byte sent. */\r
+    if(size_sent < cmd_size)\r
+    {\r
+        g_comblk_cmd_size = g_comblk_cmd_size - (uint16_t)size_sent;\r
+        g_comblk_p_cmd = &g_comblk_p_cmd[size_sent];\r
+        \r
+        g_comblk_state = COMBLK_TX_CMD;\r
+        irq_enable = TXTOKAY_MASK | RCVOKAY_MASK;\r
+    }\r
+    else\r
+    {\r
+        g_comblk_cmd_size = 0u;\r
+        g_comblk_state = COMBLK_TX_PAGED_DATA;\r
+        irq_enable = TXTOKAY_MASK | RCVOKAY_MASK;\r
+    }\r
+\r
+    /*\r
+     * Enable interrupt.\r
+     */\r
+    COMBLK->INT_ENABLE |= irq_enable;\r
+    NVIC_EnableIRQ(ComBlk_IRQn);\r
+}\r
+\r
+/*==============================================================================\r
+ * COMBLK interrupt handler.\r
+ */\r
+void ComBlk_IRQHandler(void)\r
+{\r
+    uint8_t status;\r
+    uint8_t tx_okay;\r
+    uint8_t rcv_okay;\r
+    \r
+    status = (uint8_t)COMBLK->STATUS;\r
+    \r
+    /* Mask off interrupt that are not enabled.*/\r
+    status &= COMBLK->INT_ENABLE;\r
+    \r
+    rcv_okay = status & RCVOKAY_MASK;\r
+    if(rcv_okay)\r
+    {\r
+        handle_rx_okay_irq();\r
+    }\r
+        \r
+    tx_okay = status & TXTOKAY_MASK;\r
+    if(tx_okay)\r
+    {\r
+        handle_tx_okay_irq();\r
+    }\r
+}\r
+\r
+/*==============================================================================\r
+ *\r
+ */\r
+static void handle_tx_okay_irq(void)\r
+{\r
+    switch(g_comblk_state)\r
+    {\r
+        /*----------------------------------------------------------------------\r
+         * The TX_OKAY interrupt should only be enabled for states COMBLK_TX_CMD\r
+         * and COMBLK_TX_DATA. \r
+         */\r
+        case COMBLK_TX_CMD:\r
+            if(g_comblk_cmd_size > 0u)\r
+            {\r
+                uint32_t size_sent;\r
+                size_sent = fill_tx_fifo(g_comblk_p_cmd, g_comblk_cmd_size);\r
+                if(size_sent < g_comblk_cmd_size)\r
+                {\r
+                    g_comblk_cmd_size = g_comblk_cmd_size - (uint16_t)size_sent;\r
+                    g_comblk_p_cmd = &g_comblk_p_cmd[size_sent];\r
+                }\r
+                else\r
+                {\r
+                    g_comblk_cmd_size = 0u;\r
+                    if(g_comblk_data_size > 0u)\r
+                    {\r
+                        g_comblk_state = COMBLK_TX_DATA;\r
+                    }\r
+                    else\r
+                    {\r
+                        g_comblk_state = COMBLK_WAIT_RESPONSE;\r
+                    }\r
+                }\r
+            }\r
+            else\r
+            {\r
+                /*\r
+                 * This is an invalid situation indicating a bug in the driver\r
+                 * or corrupted memory.\r
+                 */\r
+                ASSERT(0);\r
+                abort_current_cmd();\r
+            }\r
+        break;\r
+            \r
+        case COMBLK_TX_DATA:\r
+            if(g_comblk_data_size > 0u)\r
+            {\r
+                uint32_t size_sent;\r
+                size_sent = fill_tx_fifo(g_comblk_p_data, g_comblk_data_size);\r
+                if(size_sent < g_comblk_data_size)\r
+                {\r
+                    g_comblk_data_size = g_comblk_data_size - size_sent;\r
+                    g_comblk_p_data = &g_comblk_p_data[size_sent];\r
+                }\r
+                else\r
+                {\r
+                    COMBLK->INT_ENABLE &= ~TXTOKAY_MASK;\r
+                    g_comblk_state = COMBLK_WAIT_RESPONSE;\r
+                }\r
+            }\r
+            else\r
+            {\r
+                /*\r
+                 * This is an invalid situation indicating a bug in the driver\r
+                 * or corrupted memory.\r
+                 */\r
+                ASSERT(0);\r
+                abort_current_cmd();\r
+            }\r
+        break;\r
+           \r
+        case COMBLK_TX_PAGED_DATA:\r
+            /*\r
+             * Read a page of data if required.\r
+             */\r
+            if(0u == g_comblk_data_size)\r
+            {\r
+                if(g_comblk_page_handler != 0)\r
+                {\r
+                    g_comblk_data_size = g_comblk_page_handler(&g_comblk_p_data);\r
+                    if(0u == g_comblk_data_size)\r
+                    {\r
+                        COMBLK->INT_ENABLE &= ~TXTOKAY_MASK;\r
+                        g_comblk_state = COMBLK_WAIT_RESPONSE;\r
+                    }\r
+                }\r
+                else\r
+                {\r
+                    ASSERT(0);\r
+                    abort_current_cmd();\r
+                }\r
+            }\r
+            \r
+            /*\r
+             * Transmit the page data or move to COMBLK_WAIT_RESPONSE state if\r
+             * no further page data could be obtained by the call to the page\r
+             * handler above.\r
+             */\r
+            if(0u == g_comblk_data_size)\r
+            {\r
+                COMBLK->INT_ENABLE &= ~TXTOKAY_MASK;\r
+                g_comblk_state = COMBLK_WAIT_RESPONSE;\r
+            }\r
+            else\r
+            {\r
+                uint32_t size_sent;\r
+                size_sent = fill_tx_fifo(g_comblk_p_data, g_comblk_data_size);\r
+                g_comblk_data_size = g_comblk_data_size - size_sent;\r
+                g_comblk_p_data = &g_comblk_p_data[size_sent];\r
+            }\r
+        break;\r
+            \r
+        /*----------------------------------------------------------------------\r
+         * The TX_OKAY interrupt should NOT be enabled for states COMBLK_IDLE,\r
+         * COMBLK_WAIT_RESPONSE and COMBLK_RX_RESPONSE.\r
+         */\r
+        case COMBLK_IDLE:\r
+            /* Fall through */\r
+        case COMBLK_WAIT_RESPONSE:\r
+            /* Fall through */\r
+        case COMBLK_RX_RESPONSE:\r
+            /* Fall through */\r
+        default:\r
+            COMBLK->INT_ENABLE &= ~TXTOKAY_MASK;\r
+            complete_request(0u);\r
+            g_comblk_state = COMBLK_IDLE;\r
+        break;\r
+    }\r
+}\r
+\r
+/*==============================================================================\r
+ *\r
+ */\r
+static void handle_rx_okay_irq(void)\r
+{\r
+    uint16_t data16;\r
+    uint16_t is_command;\r
+    \r
+    data16 = (uint16_t)COMBLK->DATA8;\r
+    is_command = data16 & DATA8_COMMAND_MASK;\r
+            \r
+    switch(g_comblk_state)\r
+    {\r
+        /*----------------------------------------------------------------------\r
+         * The RCV_OKAY interrupt should only be enabled for states\r
+         * COMBLK_WAIT_RESPONSE and COMBLK_RX_RESPONSE. \r
+         */\r
+        case COMBLK_WAIT_RESPONSE:\r
+            if(is_command)\r
+            {\r
+                uint8_t rxed_opcode;\r
+                rxed_opcode = (uint8_t)data16;\r
+                if(rxed_opcode == g_comblk_cmd_opcode)\r
+                {\r
+                    g_comblk_response_idx = 0u;\r
+                    g_comblk_p_response[g_comblk_response_idx] = rxed_opcode;\r
+                    ++g_comblk_response_idx;\r
+                    g_comblk_state = COMBLK_RX_RESPONSE;\r
+                }\r
+                else\r
+                {\r
+                    process_sys_ctrl_command(rxed_opcode);\r
+                }\r
+            }\r
+        break;\r
+            \r
+        case COMBLK_RX_RESPONSE:\r
+            if(is_command)\r
+            {\r
+                uint8_t rxed_opcode;\r
+                rxed_opcode = (uint8_t)data16;\r
+                process_sys_ctrl_command(rxed_opcode);\r
+            }\r
+            else\r
+            {\r
+                if(g_comblk_response_idx < g_comblk_response_size)\r
+                {\r
+                    uint8_t rxed_data;\r
+                    \r
+                    rxed_data = (uint8_t)data16;\r
+                    g_comblk_p_response[g_comblk_response_idx] = rxed_data;\r
+                    ++g_comblk_response_idx;\r
+                }\r
+                \r
+                if(g_comblk_response_idx == g_comblk_response_size)\r
+                {\r
+                    complete_request(g_comblk_response_idx);\r
+                    g_comblk_state = COMBLK_IDLE;\r
+                }\r
+            }\r
+        break;\r
+            \r
+        /*----------------------------------------------------------------------\r
+         * The RCV_OKAY interrupt should NOT be enabled for states\r
+         * COMBLK_IDLE, COMBLK_TX_CMD and COMBLK_TX_DATA. \r
+         */\r
+        case COMBLK_TX_PAGED_DATA:\r
+            /* This is needed because when there is an error, we need to terminate loading the data */\r
+            if(!is_command)\r
+            {\r
+                g_comblk_p_response[1] = (uint8_t)data16;\r
+                complete_request(2u);\r
+                g_comblk_state = COMBLK_IDLE;\r
+            }\r
+        break;\r
+        case COMBLK_IDLE:\r
+            /* Fall through */\r
+        case COMBLK_TX_CMD:\r
+            /* Fall through */\r
+        case COMBLK_TX_DATA:\r
+            /* Fall through */\r
+            if(is_command)\r
+            {\r
+                uint8_t rxed_opcode;\r
+                rxed_opcode = (uint8_t)data16;\r
+                process_sys_ctrl_command(rxed_opcode);\r
+            }\r
+        break;\r
+        \r
+        default:\r
+            complete_request(0u);\r
+            g_comblk_state = COMBLK_IDLE;\r
+        break;\r
+    }\r
+}\r
+\r
+/*==============================================================================\r
+ *\r
+ */\r
+static void complete_request\r
+(\r
+    uint16_t response_length\r
+)\r
+{\r
+    if(g_comblk_completion_handler != 0)\r
+    {\r
+        g_comblk_completion_handler(g_comblk_p_response, response_length);\r
+        g_comblk_completion_handler = 0;\r
+        g_request_in_progress = 0u;\r
+    }\r
+}\r
+\r
+/*==============================================================================\r
+ *\r
+ */\r
+static void abort_current_cmd(void)\r
+{\r
+    if(g_request_in_progress)\r
+    {\r
+        uint32_t flush_in_progress;\r
+        \r
+        /*\r
+         * Call completion handler just in case we are in a multi threaded system\r
+         * to avoid a task lockup.\r
+         */\r
+        complete_request(g_comblk_response_idx);\r
+        \r
+        /*\r
+         * Flush the FIFOs\r
+         */\r
+        COMBLK->CONTROL |= CR_FLUSHOUT_MASK;\r
+        do {\r
+            flush_in_progress = COMBLK->CONTROL & CR_FLUSHOUT_MASK;\r
+        } while(flush_in_progress);\r
+    }\r
+}\r
+\r
+/*==============================================================================\r
+ *\r
+ */\r
+static void send_cmd_opcode\r
+(\r
+    uint8_t opcode\r
+)\r
+{\r
+    uint32_t tx_okay;\r
+    \r
+    /* Set transmit FIFO to transfer bytes. */\r
+    COMBLK->CONTROL &= ~CR_SIZETX_MASK;\r
+    \r
+    /* Wait for space to become available in Tx FIFO. */\r
+    do {\r
+        tx_okay = COMBLK->STATUS & TXTOKAY_MASK;\r
+    } while(0u == tx_okay);\r
+    \r
+    /* Send command opcode. */\r
+    COMBLK->FRAME_START8 = opcode;\r
+}\r
+\r
+/*==============================================================================\r
+ *\r
+ */\r
+static uint32_t fill_tx_fifo\r
+(\r
+    const uint8_t * p_cmd,\r
+    uint32_t cmd_size\r
+)\r
+{\r
+    volatile uint32_t tx_okay;\r
+    uint32_t size_sent;\r
+\r
+    /* Set transmit FIFO to transfer bytes. */\r
+    COMBLK->CONTROL &= ~CR_SIZETX_MASK;\r
+    \r
+    size_sent = 0u;\r
+    tx_okay = COMBLK->STATUS & TXTOKAY_MASK;\r
+    while((tx_okay != 0u) && (size_sent < cmd_size))\r
+    {\r
+        COMBLK->DATA8 = p_cmd[size_sent];\r
+        ++size_sent;\r
+        tx_okay = COMBLK->STATUS & TXTOKAY_MASK;\r
+    }\r
+    \r
+    return size_sent;\r
+}\r
+\r
+/*==============================================================================\r
+ *\r
+ */\r
+static void process_sys_ctrl_command(uint8_t cmd_opcode)\r
+{\r
+    if(g_async_event_handler != 0)\r
+    {\r
+        g_async_event_handler(cmd_opcode);\r
+    }\r
+}\r
+\r
diff --git a/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers/mss_sys_services/mss_comblk.h b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers/mss_sys_services/mss_comblk.h
new file mode 100644 (file)
index 0000000..7f9ba7f
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers/mss_sys_services/mss_comblk.h
@@ -0,0 +1,87 @@
+/*******************************************************************************\r
+ * (c) Copyright 2012 Microsemi SoC Products Group.  All rights reserved.\r
+ *\r
+ * SmartFusion2 COMBLK access functions.\r
+ *\r
+ * SVN $Revision: 5160 $\r
+ * SVN $Date: 2013-03-14 14:50:49 +0000 (Thu, 14 Mar 2013) $\r
+ */\r
+#ifndef __MSS_COMBLK_H_\r
+#define __MSS_COMBLK_H_ 1\r
+\r
+#include "../../CMSIS/m2sxxx.h"\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/*------------------------------------------------------------------------------\r
+ *\r
+ */\r
+typedef void(*comblk_completion_handler_t)(uint8_t * p_response, uint16_t response_size);\r
+\r
+typedef uint32_t (*comblk_page_handler_t)(uint8_t const ** pp_next_page);\r
+\r
+typedef void (*comblk_async_event_handler_t)(uint8_t event_opcode);\r
+\r
+/*------------------------------------------------------------------------------\r
+ *\r
+ */\r
+void MSS_COMBLK_init(comblk_async_event_handler_t async_event_handler);\r
+\r
+/*------------------------------------------------------------------------------\r
+ *\r
+ */\r
+void MSS_COMBLK_send_cmd_with_ptr\r
+(\r
+    uint8_t cmd_opcode,\r
+    uint32_t cmd_params_ptr,\r
+    uint8_t * p_response,\r
+    uint16_t response_size,\r
+    comblk_completion_handler_t completion_handler\r
+);\r
+\r
+/*------------------------------------------------------------------------------\r
+ *\r
+ */\r
+void MSS_COMBLK_send_cmd\r
+(\r
+    const uint8_t * p_cmd,\r
+    uint16_t cmd_size,\r
+    const uint8_t * p_data,\r
+    uint32_t data_size,\r
+    uint8_t * p_response,\r
+    uint16_t response_size,\r
+    comblk_completion_handler_t completion_handler\r
+);\r
+\r
+/*------------------------------------------------------------------------------\r
+ *\r
+ */\r
+void MSS_COMBLK_read\r
+(\r
+    const uint8_t * p_data,\r
+    uint16_t cmd_size,\r
+    uint8_t * p_response,\r
+    uint16_t response_size,\r
+    comblk_completion_handler_t completion_handler\r
+);\r
+\r
+/*------------------------------------------------------------------------------\r
+ *\r
+ */\r
+void MSS_COMBLK_send_paged_cmd\r
+(\r
+    const uint8_t * p_cmd,\r
+    uint16_t cmd_size,\r
+    uint8_t * p_response,\r
+    uint16_t response_size,\r
+    uint32_t (*)(uint8_t const **),\r
+    void (*completion_handler)(uint8_t *, uint16_t)\r
+);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __MSS_COMBLK_H_ */\r
diff --git a/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers/mss_sys_services/mss_sys_services.c b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers/mss_sys_services/mss_sys_services.c
new file mode 100644 (file)
index 0000000..e7453b5
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers/mss_sys_services/mss_sys_services.c
@@ -0,0 +1,813 @@
+/*******************************************************************************\r
+ * (c) Copyright 2012 Microsemi SoC Products Group.  All rights reserved.\r
+ *\r
+ * SmartFusion2 system services.\r
+ *\r
+ * SVN $Revision: 5615 $\r
+ * SVN $Date: 2013-04-05 14:48:10 +0100 (Fri, 05 Apr 2013) $\r
+ */\r
+#include "mss_sys_services.h"\r
+#include "mss_comblk.h"\r
+#include "../../CMSIS/mss_assert.h"\r
+#include <string.h>\r
+\r
+/*==============================================================================\r
+ *\r
+ */\r
+/*\r
+ * Service request command opcodes:\r
+ */\r
+#define DEVICE_CERTIFICATE_REQUEST_CMD      0u\r
+#define SERIAL_NUMBER_REQUEST_CMD           1u\r
+#define FLASH_FREEZE_REQUEST_CMD            2u\r
+#define AES128_REQUEST_CMD                  3u\r
+#define USERCODE_REQUEST_CMD                4u\r
+#define DESIGNVER_REQUEST_CMD               5u\r
+#define AES256_REQUEST_CMD                  6u\r
+#define KEYTREE_REQUEST_CMD                 9u\r
+#define SHA256_REQUEST_CMD                  10u\r
+#define HMAC_REQUEST_CMD                    12u\r
+#define PPUF_CHALLENGE_RESP_REQUEST_CMD     14u\r
+#define ISP_PROGRAMMING_REQUEST_CMD         21u\r
+#define DIGEST_CHECK_REQUEST_CMD            23u\r
+#define NRBG_SELF_TEST_REQUEST_CMD          40u\r
+#define NRBG_INSTANTIATE_REQUEST_CMD        41u\r
+#define NRBG_GENERATE_REQUEST_CMD           42u\r
+#define NRBG_RESEED_REQUEST_CMD             43u\r
+#define NRBG_UNINSTANTIATE_REQUEST_CMD      44u\r
+#define NRBG_RESET_REQUEST_CMD              45u\r
+#define FLASHFREEZE_SHUTDOWN_CMD            224u\r
+#define ZEROIZATION_REQUEST_CMD             240u\r
+\r
+#define POWER_ON_RESET_DIGEST_ERROR_CMD     241u\r
+\r
+/*\r
+ * System Services requests length:\r
+ */\r
+#define FLASH_FREEZE_REQUEST_LENGTH         2u\r
+\r
+/*\r
+ * Service response lengths:\r
+ */\r
+#define STANDARD_SERV_RESP_LENGTH           6u\r
+\r
+#define SERIAL_NUMBER_SERV_RESP_LENGTH      6u\r
+#define USERCODE_SERV_RESP_LENGTH           6u\r
+#define DESIGNVER_SERV_RESP_LENGTH          6u\r
+#define DEVICE_CERT_SERV_RESP_LENGTH        6u\r
+#define ISP_PROG_SERV_RESP_LENGTH           2u\r
+#define NRBG_RESET_SERV_RESP_LENGTH         2u\r
+#define NRBG_SELF_TEST_SERV_RESP_LENGTH     2u\r
+#define NRBG_UNINST_SERV_RESP_LENGTH        3u\r
+\r
+#define DIGEST_CHECK_SERV_RESP_LENGTH       2u\r
+#define FLASH_FREEZE_SERV_RESP_LENGTH       2u\r
+\r
+/*\r
+ * Non Deterministic Random Bit Generator defines:\r
+ */\r
+#define INVALID_NRBG_HANDLE     0xFFu\r
+\r
+/*\r
+ * RTC_WAKEUP_CR system register bit masks:\r
+ */\r
+#define RTC_WAKEUP_G4C_EN_MASK      0x00000004u\r
+#define RTC_WAKEUP_FAB_EN_MASK      0x00000002u\r
+\r
+/*==============================================================================\r
+ * Local functions.\r
+ */\r
+static void request_completion_handler(uint8_t * p_response, uint16_t response_size);\r
+static void signal_request_start(void);\r
+static uint16_t wait_for_request_completion(void);\r
+static uint8_t execute_service\r
+(\r
+    uint8_t cmd_opcode,\r
+    uint8_t * cmd_params_ptr,\r
+    uint8_t * response,\r
+    uint16_t response_length\r
+);\r
+\r
+static void asynchronous_event_handler(uint8_t event_opcode);\r
+\r
+static void write_ptr_value_into_array\r
+(\r
+    const uint8_t * pointer,\r
+    uint8_t target_array[],\r
+    uint32_t array_index\r
+);\r
+\r
+/*==============================================================================\r
+ * Global variables\r
+ */\r
+static volatile uint8_t g_request_in_progress = 0u;\r
+static volatile uint16_t g_last_response_length = 0u;\r
+static sys_serv_async_event_handler_t g_event_handler = 0;\r
+\r
+/*==============================================================================\r
+ *\r
+ */\r
+void MSS_SYS_init(sys_serv_async_event_handler_t event_handler)\r
+{\r
+    MSS_COMBLK_init(asynchronous_event_handler);\r
+    \r
+    g_event_handler = event_handler;\r
+    \r
+    g_request_in_progress = 0u;\r
+    g_last_response_length = 0u;\r
+}\r
+\r
+/*==============================================================================\r
+ *\r
+ */\r
+static void asynchronous_event_handler(uint8_t event_opcode)\r
+{\r
+    if(g_event_handler != 0)\r
+    {\r
+    switch(event_opcode)\r
+        {\r
+            case FLASH_FREEZE_SHUTDOWN_OPCODE:\r
+            case FLASH_FREEZE_EXIT_OPCODE:\r
+                g_event_handler(event_opcode);\r
+            break;\r
+            \r
+            default:\r
+                /* Ignore all other events. */\r
+            break;\r
+        }\r
+    }\r
+}\r
+\r
+/*==============================================================================\r
+ * See mss_sys_services.h for details.\r
+ */\r
+uint8_t MSS_SYS_get_serial_number\r
+(\r
+    uint8_t * p_serial_number\r
+)\r
+{\r
+    uint8_t response[SERIAL_NUMBER_SERV_RESP_LENGTH];\r
+    uint8_t status;\r
+    \r
+    status = execute_service(SERIAL_NUMBER_REQUEST_CMD,\r
+                             p_serial_number,\r
+                             response,\r
+                             SERIAL_NUMBER_SERV_RESP_LENGTH);\r
+    \r
+    return status;\r
+}\r
+\r
+/*==============================================================================\r
+ * See mss_sys_services.h for details.\r
+ */\r
+uint8_t MSS_SYS_get_user_code\r
+(\r
+    uint8_t * p_user_code\r
+)\r
+{\r
+    uint8_t response[USERCODE_SERV_RESP_LENGTH];\r
+    uint8_t status;\r
+    \r
+    status = execute_service(USERCODE_REQUEST_CMD,\r
+                             p_user_code,\r
+                             response,\r
+                             USERCODE_SERV_RESP_LENGTH);\r
+    \r
+    return status;\r
+}\r
+\r
+/*==============================================================================\r
+ * See mss_sys_services.h for details.\r
+ */\r
+uint8_t MSS_SYS_get_design_version\r
+(\r
+    uint8_t * p_design_version\r
+)\r
+{\r
+    uint8_t response[DESIGNVER_SERV_RESP_LENGTH];\r
+    uint8_t status;\r
+    \r
+    status = execute_service(DESIGNVER_REQUEST_CMD,\r
+                             p_design_version,\r
+                             response,\r
+                             DESIGNVER_SERV_RESP_LENGTH);\r
+    \r
+    return status;\r
+}\r
+\r
+/*==============================================================================\r
+ * See mss_sys_services.h for details.\r
+ */\r
+uint8_t MSS_SYS_get_device_certificate\r
+(\r
+    uint8_t * p_device_certificate\r
+)\r
+{\r
+    uint8_t response[DEVICE_CERT_SERV_RESP_LENGTH];\r
+    uint8_t status;\r
+    \r
+    status = execute_service(DEVICE_CERTIFICATE_REQUEST_CMD,\r
+                             p_device_certificate,\r
+                             response,\r
+                             DEVICE_CERT_SERV_RESP_LENGTH);\r
+    \r
+    return status;\r
+}\r
+\r
+/*==============================================================================\r
+ * See mss_sys_services.h for details.\r
+ */\r
+uint8_t MSS_SYS_flash_freeze(uint8_t options)\r
+{\r
+    uint8_t status;\r
+    uint16_t actual_response_length;\r
+    uint8_t flash_freeze_req[FLASH_FREEZE_REQUEST_LENGTH];\r
+    uint8_t response[FLASH_FREEZE_SERV_RESP_LENGTH];\r
+\r
+    /*\r
+     * The Flash Freeze system service is not available on M2S050 rev A and rev B.\r
+     */\r
+    ASSERT(0x0000F802u != SYSREG->DEVICE_VERSION);\r
+    ASSERT(0x0001F802u != SYSREG->DEVICE_VERSION);\r
+    \r
+    /*\r
+     * Enable RTC wake-up interrupt to System Controller and FPGA fabric.\r
+     */\r
+    SYSREG->RTC_WAKEUP_CR |= (RTC_WAKEUP_G4C_EN_MASK | RTC_WAKEUP_FAB_EN_MASK);\r
+\r
+    signal_request_start();\r
+\r
+    flash_freeze_req[0] = FLASH_FREEZE_REQUEST_CMD;\r
+    flash_freeze_req[1] = options;\r
+\r
+    MSS_COMBLK_send_cmd(flash_freeze_req,               /* p_cmd */\r
+                        FLASH_FREEZE_REQUEST_LENGTH,    /* cmd_size */\r
+                        0,                              /* p_data */\r
+                        0u,                             /* data_size */\r
+                        response,                       /* p_response */\r
+                        FLASH_FREEZE_SERV_RESP_LENGTH,  /* response_size */\r
+                        request_completion_handler);    /* completion_handler */\r
+\r
+    actual_response_length = wait_for_request_completion();\r
+    \r
+    if((FLASH_FREEZE_SERV_RESP_LENGTH == actual_response_length) &&\r
+       (FLASH_FREEZE_REQUEST_CMD == response[0]))\r
+    {\r
+        status = response[1];\r
+    }\r
+    else\r
+    {\r
+        status = MSS_SYS_UNEXPECTED_ERROR;\r
+    }\r
+    \r
+    return status;\r
+}\r
+\r
+/*==============================================================================\r
+ * See mss_sys_services.h for details.\r
+ */\r
+#define AES128_KEY_LENGTH   16u\r
+#define IV_LENGTH           16u\r
+\r
+#define AES256_KEY_LENGTH   32u\r
+\r
+#define HMAC_KEY_LENGTH     32u\r
+\r
+uint8_t MSS_SYS_128bit_aes\r
+(\r
+    const uint8_t * key,\r
+    const uint8_t * iv,\r
+    uint16_t nb_blocks,\r
+    uint8_t mode,\r
+    uint8_t * dest_addr,\r
+    const uint8_t * src_addr)\r
+{\r
+    uint8_t response[STANDARD_SERV_RESP_LENGTH];\r
+    uint8_t params[44];\r
+    uint8_t status;\r
+    \r
+    memcpy(&params[0], key, AES128_KEY_LENGTH);\r
+    memcpy(&params[16], iv, IV_LENGTH);\r
+    \r
+    params[32] = (uint8_t)nb_blocks;\r
+    params[33] = (uint8_t)(nb_blocks >> 8u);\r
+    params[34] = mode;\r
+    params[35] = 0u;\r
+#if 1\r
+    write_ptr_value_into_array(dest_addr, params, 36u);\r
+    write_ptr_value_into_array(src_addr, params, 40u);\r
+#else    \r
+    params[36] = (uint8_t)((uint32_t)dest_addr);\r
+    params[37] = (uint8_t)((uint32_t)dest_addr >> 8u);\r
+    params[38] = (uint8_t)((uint32_t)dest_addr >> 16u);\r
+    params[39] = (uint8_t)((uint32_t)dest_addr >> 24u);\r
+\r
+    params[40] = (uint8_t)((uint32_t)src_addr);\r
+    params[41] = (uint8_t)((uint32_t)src_addr >> 8u);\r
+    params[42] = (uint8_t)((uint32_t)src_addr >> 16u);\r
+    params[43] = (uint8_t)((uint32_t)src_addr >> 24u);\r
+#endif\r
+    status = execute_service(AES128_REQUEST_CMD,\r
+                             params,\r
+                             response,\r
+                             STANDARD_SERV_RESP_LENGTH);\r
+                             \r
+    return status;\r
+}\r
+\r
+/*==============================================================================\r
+ * See mss_sys_services.h for details.\r
+ */\r
+uint8_t MSS_SYS_256bit_aes\r
+( \r
+    const uint8_t * key,\r
+    const uint8_t * iv,\r
+    uint16_t nb_blocks,\r
+    uint8_t mode,\r
+    uint8_t * dest_addr,\r
+    const uint8_t * src_addr\r
+)\r
+{\r
+    uint8_t response[STANDARD_SERV_RESP_LENGTH];\r
+    uint8_t params[60];\r
+    uint8_t status;\r
+    \r
+    memcpy(&params[0], key, AES256_KEY_LENGTH);\r
+    memcpy(&params[32], iv, IV_LENGTH);\r
+    \r
+    params[48] = (uint8_t)nb_blocks;\r
+    params[49] = (uint8_t)(nb_blocks >> 8u);\r
+    params[50] = mode;\r
+    params[51] = 0u;\r
+#if 1\r
+    write_ptr_value_into_array(dest_addr, params, 52u);\r
+    write_ptr_value_into_array(src_addr, params, 56u);\r
+#else    \r
+    params[52] = (uint8_t)((uint32_t)dest_addr);\r
+    params[53] = (uint8_t)((uint32_t)dest_addr >> 8u);\r
+    params[54] = (uint8_t)((uint32_t)dest_addr >> 16u);\r
+    params[55] = (uint8_t)((uint32_t)dest_addr >> 24u);\r
+\r
+    params[56] = (uint8_t)((uint32_t)src_addr);\r
+    params[57] = (uint8_t)((uint32_t)src_addr >> 8u);\r
+    params[58] = (uint8_t)((uint32_t)src_addr >> 16u);\r
+    params[59] = (uint8_t)((uint32_t)src_addr >> 24u);\r
+#endif\r
+    status = execute_service(AES256_REQUEST_CMD,\r
+                             params,\r
+                             response,\r
+                             STANDARD_SERV_RESP_LENGTH);\r
+                             \r
+    return status;\r
+}\r
+\r
+/*==============================================================================\r
+ * See mss_sys_services.h for details.\r
+ */\r
+uint8_t MSS_SYS_sha256\r
+(\r
+    const uint8_t * p_data_in,\r
+    uint32_t length,\r
+    uint8_t * result\r
+)\r
+{\r
+    uint8_t response[STANDARD_SERV_RESP_LENGTH];\r
+    uint8_t params[12];\r
+    uint8_t status;\r
+    \r
+    params[0] = (uint8_t)((uint32_t)length);\r
+    params[1] = (uint8_t)((uint32_t)length >> 8u);\r
+    params[2] = (uint8_t)((uint32_t)length >> 16u);\r
+    params[3] = (uint8_t)((uint32_t)length >> 24u);\r
+    \r
+#if 1\r
+    write_ptr_value_into_array(result, params, 4u);\r
+    write_ptr_value_into_array(p_data_in, params, 8u);\r
+#else\r
+    params[4] = (uint8_t)((uint32_t)result);\r
+    params[5] = (uint8_t)((uint32_t)result >> 8u);\r
+    params[6] = (uint8_t)((uint32_t)result >> 16u);\r
+    params[7] = (uint8_t)((uint32_t)result >> 24u);\r
+\r
+    params[8] = (uint8_t)((uint32_t)p_data_in);\r
+    params[9] = (uint8_t)((uint32_t)p_data_in >> 8u);\r
+    params[10] = (uint8_t)((uint32_t)p_data_in >> 16u);\r
+    params[11] = (uint8_t)((uint32_t)p_data_in >> 24u);\r
+#endif\r
+    status = execute_service(SHA256_REQUEST_CMD,\r
+                             params,\r
+                             response,\r
+                             STANDARD_SERV_RESP_LENGTH);\r
+                             \r
+    return status;\r
+}\r
+\r
+/*==============================================================================\r
+ * See mss_sys_services.h for details.\r
+ */\r
+uint8_t MSS_SYS_hmac\r
+(\r
+    const uint8_t * key,\r
+    const uint8_t * p_data_in,\r
+    uint32_t length,\r
+    uint8_t * p_result\r
+)\r
+{\r
+    uint8_t response[STANDARD_SERV_RESP_LENGTH];\r
+    uint8_t params[58];\r
+    uint8_t status;\r
+    \r
+    memcpy(&params[0], key, HMAC_KEY_LENGTH);\r
+    \r
+    params[32] = (uint8_t)((uint32_t)length);\r
+    params[33] = (uint8_t)((uint32_t)length >> 8u);\r
+    params[34] = (uint8_t)((uint32_t)length >> 16u);\r
+    params[35] = (uint8_t)((uint32_t)length >> 24u);\r
+#if 1\r
+    write_ptr_value_into_array(p_data_in, params, 36u);\r
+    write_ptr_value_into_array(p_result, params, 40u);\r
+#else    \r
+    params[36] = (uint8_t)((uint32_t)p_data_in);\r
+    params[37] = (uint8_t)((uint32_t)p_data_in >> 8u);\r
+    params[38] = (uint8_t)((uint32_t)p_data_in >> 16u);\r
+    params[39] = (uint8_t)((uint32_t)p_data_in >> 24u);\r
+\r
+    params[40] = (uint8_t)((uint32_t)p_result);\r
+    params[41] = (uint8_t)((uint32_t)p_result >> 8u);\r
+    params[42] = (uint8_t)((uint32_t)p_result >> 16u);\r
+    params[43] = (uint8_t)((uint32_t)p_result >> 24u);\r
+#endif\r
+    status = execute_service(HMAC_REQUEST_CMD,\r
+                             params,\r
+                             response,\r
+                             STANDARD_SERV_RESP_LENGTH);\r
+                             \r
+    return status;\r
+}\r
+\r
+/*==============================================================================\r
+ * See mss_sys_services.h for details.\r
+ */\r
+uint8_t MSS_SYS_nrbg_self_test(void)\r
+{\r
+    uint8_t status;\r
+    uint16_t actual_response_length;\r
+    uint8_t self_test;\r
+    uint8_t response[NRBG_SELF_TEST_SERV_RESP_LENGTH];\r
+    \r
+    signal_request_start();\r
+    \r
+    self_test = NRBG_SELF_TEST_REQUEST_CMD;\r
+\r
+    MSS_COMBLK_send_cmd(&self_test,                         /* p_cmd */\r
+                        sizeof(self_test),                  /* cmd_size */\r
+                        0,                                  /* p_data */\r
+                        0,                                  /* data_size */\r
+                        response,                           /* p_response */\r
+                        NRBG_SELF_TEST_SERV_RESP_LENGTH,    /* response_size */\r
+                        request_completion_handler);        /* completion_handler */\r
+    \r
+    actual_response_length = wait_for_request_completion();\r
+    \r
+    if((NRBG_SELF_TEST_SERV_RESP_LENGTH == actual_response_length) &&\r
+       (NRBG_SELF_TEST_REQUEST_CMD == response[0]))\r
+    {\r
+        status = response[1];\r
+    }\r
+    else\r
+    {\r
+        status = MSS_SYS_UNEXPECTED_ERROR;\r
+    }\r
+    \r
+    return status;\r
+}\r
+\r
+/*==============================================================================\r
+ * See mss_sys_services.h for details.\r
+ */\r
+uint8_t MSS_SYS_nrbg_instantiate\r
+(\r
+    const uint8_t * personalization_str,\r
+    uint16_t personalization_str_length,\r
+    uint8_t * p_nrbg_handle\r
+)\r
+{\r
+    uint8_t response[STANDARD_SERV_RESP_LENGTH];\r
+    uint8_t intantiate_params[7];\r
+    uint8_t status;\r
+#if 1\r
+    write_ptr_value_into_array(personalization_str, intantiate_params, 0u);\r
+#else    \r
+    intantiate_params[0] = (uint8_t)((uint32_t)personalization_str);\r
+    intantiate_params[1] = (uint8_t)((uint32_t)personalization_str >> 8u);\r
+    intantiate_params[2] = (uint8_t)((uint32_t)personalization_str >> 16u);\r
+    intantiate_params[3] = (uint8_t)((uint32_t)personalization_str >> 24u);\r
+#endif\r
+    intantiate_params[4] = (uint8_t)personalization_str_length;\r
+    intantiate_params[5] = (uint8_t)(personalization_str_length >> 8u);\r
+    intantiate_params[6] = INVALID_NRBG_HANDLE;\r
+    \r
+    status = execute_service(NRBG_INSTANTIATE_REQUEST_CMD,\r
+                             intantiate_params,\r
+                             response,\r
+                             STANDARD_SERV_RESP_LENGTH);\r
+                             \r
+    if(MSS_SYS_SUCCESS == status)\r
+    {\r
+        *p_nrbg_handle = intantiate_params[6];\r
+    }\r
+    \r
+    return status;\r
+}\r
+\r
+/*==============================================================================\r
+ * See mss_sys_services.h for details.\r
+ */\r
+uint8_t MSS_SYS_nrbg_generate\r
+(\r
+    const uint8_t * p_requested_data,\r
+    const uint8_t * p_additional_input,\r
+    uint8_t requested_length,\r
+    uint8_t additional_input_length,\r
+    uint8_t pr_req,\r
+    uint8_t nrbg_handle\r
+)\r
+{\r
+    uint8_t response[STANDARD_SERV_RESP_LENGTH];\r
+    uint8_t generate_params[12];\r
+    uint8_t status;\r
+#if 1\r
+    write_ptr_value_into_array(p_requested_data, generate_params, 0u);\r
+    write_ptr_value_into_array(p_additional_input, generate_params, 4u);\r
+#else\r
+    generate_params[0] = (uint8_t)((uint32_t)p_requested_data);\r
+    generate_params[1] = (uint8_t)((uint32_t)p_requested_data >> 8u);\r
+    generate_params[2] = (uint8_t)((uint32_t)p_requested_data >> 16u);\r
+    generate_params[3] = (uint8_t)((uint32_t)p_requested_data >> 24u);\r
+    generate_params[4] = (uint8_t)((uint32_t)p_additional_input);\r
+    generate_params[5] = (uint8_t)((uint32_t)p_additional_input >> 8u);\r
+    generate_params[6] = (uint8_t)((uint32_t)p_additional_input >> 16u);\r
+    generate_params[7] = (uint8_t)((uint32_t)p_additional_input >> 24u);\r
+#endif\r
+    generate_params[8] = requested_length;\r
+    generate_params[9] = additional_input_length;\r
+    generate_params[10] = pr_req;\r
+    generate_params[11] = nrbg_handle;\r
+    \r
+    status = execute_service(NRBG_GENERATE_REQUEST_CMD,\r
+                             generate_params,\r
+                             response,\r
+                             STANDARD_SERV_RESP_LENGTH);\r
+    \r
+    return status;\r
+}\r
+\r
+/*==============================================================================\r
+ * See mss_sys_services.h for details.\r
+ */\r
+uint8_t MSS_SYS_nrbg_reseed\r
+(\r
+    const uint8_t * p_additional_input,\r
+    uint8_t additional_input_length,\r
+    uint8_t nrbg_handle\r
+)\r
+{\r
+    uint8_t response[STANDARD_SERV_RESP_LENGTH];\r
+    uint8_t params[6];\r
+    uint8_t status;\r
+#if 1\r
+    write_ptr_value_into_array(p_additional_input, params, 0u);\r
+#else\r
+    params[0] = (uint8_t)((uint32_t)p_additional_input);\r
+    params[1] = (uint8_t)((uint32_t)p_additional_input >> 8u);\r
+    params[2] = (uint8_t)((uint32_t)p_additional_input >> 16u);\r
+    params[3] = (uint8_t)((uint32_t)p_additional_input >> 24u);\r
+#endif\r
+    params[4] = (uint8_t)additional_input_length;\r
+    params[5] = nrbg_handle;\r
+    \r
+    status = execute_service(NRBG_RESEED_REQUEST_CMD,\r
+                             params,\r
+                             response,\r
+                             STANDARD_SERV_RESP_LENGTH);\r
+    \r
+    return status;\r
+}\r
+\r
+/*==============================================================================\r
+ * See mss_sys_services.h for details.\r
+ */\r
+uint8_t MSS_SYS_nrbg_uninstantiate\r
+(\r
+    uint8_t nrbg_handle\r
+)\r
+{\r
+    uint8_t status;\r
+    uint16_t actual_response_length;\r
+    uint8_t uninstantiate_req[2];\r
+    uint8_t response[NRBG_UNINST_SERV_RESP_LENGTH];\r
+    \r
+    signal_request_start();\r
+    \r
+    uninstantiate_req[0] = NRBG_UNINSTANTIATE_REQUEST_CMD;\r
+    uninstantiate_req[1] = nrbg_handle;\r
+\r
+    MSS_COMBLK_send_cmd(uninstantiate_req,              /* p_cmd */\r
+                        sizeof(uninstantiate_req),      /* cmd_size */\r
+                        0,                              /* p_data */\r
+                        0,                              /* data_size */\r
+                        response,                       /* p_response */\r
+                        NRBG_UNINST_SERV_RESP_LENGTH,   /* response_size */\r
+                        request_completion_handler);    /* completion_handler */\r
+    \r
+    actual_response_length = wait_for_request_completion();\r
+    \r
+    if((NRBG_UNINST_SERV_RESP_LENGTH == actual_response_length) &&\r
+       (NRBG_UNINSTANTIATE_REQUEST_CMD == response[0]))\r
+    {\r
+        status = response[1];\r
+    }\r
+    else\r
+    {\r
+        status = MSS_SYS_UNEXPECTED_ERROR;\r
+    }\r
+    \r
+    return status;\r
+}\r
+\r
+/*==============================================================================\r
+ * See mss_sys_services.h for details.\r
+ */\r
+static uint8_t g_isp_response[ISP_PROG_SERV_RESP_LENGTH];\r
+void (*g_isp_completion_handler)(uint32_t) = 0;\r
+\r
+static void isp_sys_completion_handler\r
+(\r
+    uint8_t * p_response, \r
+    uint16_t length\r
+)\r
+{\r
+    if(g_isp_completion_handler != 0)\r
+    {\r
+        g_isp_completion_handler(p_response[1]);\r
+    }\r
+}\r
+\r
+void MSS_SYS_start_isp\r
+(\r
+    uint8_t mode,\r
+    uint32_t (*page_read_handler)(uint8_t const **),\r
+    void (*isp_completion_handler)(uint32_t)\r
+)\r
+{\r
+    uint8_t isp_prog_request[2];\r
+    \r
+    signal_request_start();\r
+    \r
+    isp_prog_request[0] = ISP_PROGRAMMING_REQUEST_CMD;\r
+    isp_prog_request[1] = mode;\r
+    \r
+    g_isp_completion_handler = isp_completion_handler;\r
+\r
+    MSS_COMBLK_send_paged_cmd(isp_prog_request,                 /* p_cmd */\r
+                              sizeof(isp_prog_request),         /* cmd_size */\r
+                              g_isp_response,                   /* p_response */\r
+                              ISP_PROG_SERV_RESP_LENGTH, /* response_size */\r
+                              page_read_handler,                /* page_handler */\r
+                              isp_sys_completion_handler);      /* completion_handler */\r
+}\r
+\r
+/*==============================================================================\r
+ * See mss_sys_services.h for details.\r
+ */\r
+uint8_t MSS_SYS_check_digest\r
+(\r
+    uint8_t options\r
+)\r
+{\r
+    uint8_t status;\r
+    uint16_t actual_response_length;\r
+    uint8_t digest_check_req[2];\r
+    uint8_t response[DIGEST_CHECK_SERV_RESP_LENGTH];\r
+    \r
+    signal_request_start();\r
+    \r
+    digest_check_req[0] = DIGEST_CHECK_REQUEST_CMD;\r
+    digest_check_req[1] = options;\r
+\r
+    MSS_COMBLK_send_cmd(digest_check_req,               /* p_cmd */\r
+                        sizeof(digest_check_req),       /* cmd_size */\r
+                        0,                              /* p_data */\r
+                        0u,                             /* data_size */\r
+                        response,                       /* p_response */\r
+                        DIGEST_CHECK_SERV_RESP_LENGTH,  /* response_size */\r
+                        request_completion_handler);    /* completion_handler */\r
+    \r
+    actual_response_length = wait_for_request_completion();\r
+    \r
+    if((DIGEST_CHECK_SERV_RESP_LENGTH == actual_response_length) &&\r
+       (DIGEST_CHECK_REQUEST_CMD == response[0]))\r
+    {\r
+        status = response[1];\r
+    }\r
+    else\r
+    {\r
+        status = MSS_SYS_UNEXPECTED_ERROR;\r
+    }\r
+    \r
+    return status;\r
+}\r
+\r
+/*==============================================================================\r
+ *\r
+ */\r
+static uint8_t execute_service\r
+(\r
+    uint8_t cmd_opcode,\r
+    uint8_t * cmd_params_ptr,\r
+    uint8_t * response,\r
+    uint16_t response_length\r
+)\r
+{\r
+    uint8_t status;\r
+    uint16_t actual_response_length;\r
+    \r
+    signal_request_start();\r
+    \r
+    MSS_COMBLK_send_cmd_with_ptr(cmd_opcode,                    /* cmd_opcode */\r
+                                 (uint32_t)cmd_params_ptr,      /* cmd_params_ptr */\r
+                                 response,                      /* p_response */\r
+                                 response_length,               /* response_size */\r
+                                 request_completion_handler);   /* completion_handler */\r
+    \r
+    actual_response_length = wait_for_request_completion();\r
+    \r
+    if((response_length == actual_response_length) && (cmd_opcode == response[0]))\r
+    {\r
+        status = response[1];\r
+    }\r
+    else\r
+    {\r
+        status = MSS_SYS_UNEXPECTED_ERROR;\r
+    }\r
+    \r
+    return status;\r
+}\r
+\r
+/*==============================================================================\r
+ *\r
+ */\r
+static void request_completion_handler\r
+(\r
+    uint8_t * p_response,\r
+    uint16_t response_size\r
+)\r
+{\r
+    g_request_in_progress = 0u;\r
+    g_last_response_length = response_size;\r
+}\r
+\r
+/*==============================================================================\r
+ *\r
+ */\r
+static void signal_request_start(void)\r
+{\r
+    /* Wait for current request to complete. */\r
+    while(g_request_in_progress)\r
+    {\r
+        ;\r
+    }\r
+    \r
+    g_request_in_progress = 1u;\r
+    g_last_response_length = 0u;\r
+}\r
+\r
+/*==============================================================================\r
+ *\r
+ */\r
+static uint16_t wait_for_request_completion(void)\r
+{\r
+    while(g_request_in_progress)\r
+    {\r
+        ;\r
+    }\r
+    \r
+    return g_last_response_length;\r
+}\r
+\r
+/*==============================================================================\r
+ *\r
+ */\r
+static void write_ptr_value_into_array\r
+(\r
+    const uint8_t * pointer,\r
+    uint8_t target_array[],\r
+    uint32_t array_index\r
+)\r
+{\r
+    target_array[array_index] = (uint8_t)((uint32_t)pointer);\r
+    target_array[array_index + 1] = (uint8_t)((uint32_t)pointer >> 8u);\r
+    target_array[array_index + 2] = (uint8_t)((uint32_t)pointer >> 16u);\r
+    target_array[array_index + 3] = (uint8_t)((uint32_t)pointer >> 24u);\r
+}\r
+\r
diff --git a/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers/mss_sys_services/mss_sys_services.h b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers/mss_sys_services/mss_sys_services.h
new file mode 100644 (file)
index 0000000..c8efcc3
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers/mss_sys_services/mss_sys_services.h
@@ -0,0 +1,883 @@
+/*******************************************************************************\r
+ * (c) Copyright 2012 Microsemi SoC Products Group.  All rights reserved.\r
+ *\r
+ * SmartFusion2 MSS System Services bare metal software driver public API.\r
+ *\r
+ * SVN $Revision: 5591 $\r
+ * SVN $Date: 2013-04-04 15:55:11 +0100 (Thu, 04 Apr 2013) $\r
+ */\r
+\r
+/*=========================================================================*//**\r
+  @mainpage SmartFusion2 MSS System Services Bare Metal Driver.\r
+\r
+  @section intro_sec Introduction\r
+  The SmartFusion2 microcontroller subsystem (MSS) includes a communication\r
+  block (COMM_BLK) allowing it to communicate with the SmartFusion2 System\r
+  Controller. The SmartFusion2 System Controller performs a variety of system\r
+  wide services. This software driver provides a set of functions to access\r
+  these System Services. The driver can be adapted for use as part of an\r
+  operating system, but the implementation of the adaptation layer between the\r
+  driver and the operating system's driver model is outside the scope of the\r
+  driver.\r
+  \r
+  @section hw_dependencies Hardware Flow Dependencies\r
+  The MSS System Services driver does not require any configuration. It relies\r
+  on the SmartFusion2 communication block (MSS_COMM_BLK) to communicate with the\r
+  System Controller. The MSS_COMM_BLK is always enabled.\r
+  The base address, register addresses and interrupt number assignment for the\r
+  MSS_COMM_BLK are defined as constants in the SmartFusion2 CMSIS HAL. You must\r
+  ensure that the latest SmartFusion2 CMSIS HAL is included in the project\r
+  settings of the software tool chain used to build your project and that it is\r
+  generated into your project.\r
+  \r
+  @section theory_op Theory of Operation\r
+  The System Services driver provides access to the SmartFusion2 System\r
+  Controller services. These system services are loosely grouped into the\r
+  following features:\r
+    - Reading system information\r
+    - Cryptography\r
+    - Non-deterministic random bit generator\r
+    - Flash*Freeze\r
+  Note: Refer to the function descriptions for further details about the\r
+        features of each individual service.\r
+\r
+  Reading System Information\r
+  The System Services driver can be used to read information about the\r
+  SmartFusion2 device and the design programmed into it using the following\r
+  functions:\r
+    - MSS_SYS_get_serial_number()\r
+    - MSS_SYS_get_user_code()\r
+    - MSS_SYS_get_design_version()\r
+    - MSS_SYS_get_device_certificate()\r
+    \r
+  Cryptography Services\r
+  The System Services driver provides cryptographic services using the following\r
+  functions:\r
+    - MSS_SYS_128bit_aes()\r
+    - MSS_SYS_256bit_aes()\r
+    - MSS_SYS_sha256()\r
+    - MSS_SYS_hmac()\r
+    \r
+  Non-Deterministic Random Bit Generator\r
+  The System Services driver provides random number generation services using\r
+  the following functions:\r
+    - MSS_SYS_nrbg_instantiate()\r
+    - MSS_SYS_nrbg_self_test()\r
+    - MSS_SYS_nrbg_generate()\r
+    - MSS_SYS_nrbg_reseed()\r
+    - MSS_SYS_nrbg_uninstantiate()\r
+    \r
+  Flash*Freeze\r
+  The System Services driver can be used to request the system to enter\r
+  Flash*Freeze mode using the following function:\r
+    - MSS_SYS_flash_freeze()\r
+    \r
+ *//*=========================================================================*/\r
+\r
+#ifndef __MSS_SYS_SERVICES_H_\r
+#define __MSS_SYS_SERVICES_H_ 1\r
+\r
+#include "../../CMSIS/m2sxxx.h"\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/*==============================================================================\r
+ * Status codes:\r
+ */\r
+/*-------------------------------------------------------------------------*//**\r
+  These constants are used by multiple services to communicate the outcome of a\r
+  system services request. These status codes are used across all types of\r
+  services.\r
+  \r
+  - MSS_SYS_SUCCESS:\r
+      Indicates that the system services completed successfully. \r
+      \r
+  - MSS_SYS_UNEXPECTED_ERROR:\r
+      Indicates that the system failed in an unexpected way.\r
+      \r
+  - MSS_SYS_MEM_ACCESS_ERROR:\r
+      Indicates that the System Controller could not access the memory used to\r
+      pass parameters to the System Controller or to return a service result to\r
+      the Cortex-M3.\r
+      \r
+  - MSS_SYS_SERVICE_DISABLED_BY_FACTORY:\r
+      Indicates that the requested system service is not available on the\r
+      SmartFusion2 device.\r
+      \r
+  - MSS_SYS_SERVICE_DISABLED_BY_USER:\r
+      Indicates that the requested system service has been disabled as part of\r
+      the hardware design.\r
+ */\r
+#define MSS_SYS_SUCCESS                         0u\r
+#define MSS_SYS_UNEXPECTED_ERROR                200u\r
+\r
+#define MSS_SYS_MEM_ACCESS_ERROR                127u\r
+#define MSS_SYS_SERVICE_DISABLED_BY_FACTORY     254u\r
+#define MSS_SYS_SERVICE_DISABLED_BY_USER        255u\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ * Programming services specific status codes:\r
+ */\r
+#define MSS_SYS_CHAINING_MISMATCH                   1u\r
+#define MSS_SYS_UNEXPECTED_DATA_RECEIVED            2u\r
+#define MSS_SYS_INVALID_ENCRYPTION_KEY              3u\r
+#define MSS_SYS_INVALID_COMPONENT_HEADER            4u\r
+#define MSS_SYS_BACK_LEVEL_NOT_SATISFIED            5u\r
+#define MSS_SYS_DSN_BINDING_MISMATCH                7u\r
+#define MSS_SYS_ILLEGAL_COMPONENT_SEQUENCE          8u\r
+#define MSS_SYS_INSUFFICIENT_DEV_CAPABILITIES       9u\r
+#define MSS_SYS_INCORRECT_DEVICE_ID                 10u\r
+#define MSS_SYS_UNSUPPORTED_BITSTREAM_PROT_VER      11u\r
+#define MSS_SYS_VERIFY_NOT_PERMITTED_ON_BITSTR      12u\r
+#define MSS_SYS_ABORT                               127u\r
+#define MSS_SYS_NVM_VERIFY_FAILED                   129u\r
+#define MSS_SYS_DEVICE_SECURITY_PROTECTED           130u\r
+#define MSS_SYS_PROGRAMMING_MODE_NOT_ENABLED        131u\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+  These constants are used to specify the event_opcode parameter for the\r
+  event_handler() function registered with the MSS_SYS_init() function. They are\r
+  used to specify which asynchronous event is notified to the Cortex-M3 software\r
+  by the System Controller. Asynchronous events are sent by the System\r
+  Controller to the Cortex-M3 when some system events of interest occur.\r
+  \r
+  - FLASH_FREEZE_SHUTDOWN_OPCODE:\r
+      Indicates that the system is being shutdown as a result of entering the\r
+      Flash*Freeze mode.\r
+      \r
+  - FLASH_FREEZE_EXIT_OPCODE:\r
+      Indicates that the system is exiting Flash*Freeze mode.\r
+ */\r
+#define FLASH_FREEZE_SHUTDOWN_OPCODE    0xE0u\r
+#define FLASH_FREEZE_EXIT_OPCODE        0xE1u\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+  These constants are used to specify the options parameter for the\r
+  MSS_SYS_flash_freeze() function.\r
+  \r
+  - MSS_SYS_FPGA_POWER_DOWN:\r
+      Indicates that the MSS_SYS_flash_freeze() function should request the FPGA\r
+      fabric to enter Flash*Freeze mode.\r
+      \r
+  - MSS_SYS_ENVM0_POWER_DOWN:\r
+      Indicates that the MSS_SYS_flash_freeze() function should request eNVM0 to\r
+      enter Flash*Freeze mode.\r
+      \r
+  - MSS_SYS_ENVM1_POWER_DOWN:\r
+      Indicates that the MSS_SYS_flash_freeze() function should request eNVM1 to\r
+      enter Flash*Freeze mode.\r
+      \r
+  - MSS_SYS_MPLL_POWER_DOWN:\r
+      Indicates that the MSS_SYS_flash_freeze() function should request the MSS\r
+      PLL to enter Flash*Freeze mode.\r
+ */\r
+#define MSS_SYS_FPGA_POWER_DOWN     0x00u\r
+#define MSS_SYS_ENVM0_POWER_DOWN    0x01u\r
+#define MSS_SYS_ENVM1_POWER_DOWN    0x02u\r
+#define MSS_SYS_MPLL_POWER_DOWN     0x04u\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+  These constants are used to specify the mode parameter for the\r
+  MSS_SYS_128aes() and MSS_SYS_256bit_aes() functions.\r
+  \r
+  - MSS_SYS_ECB_ENCRYPT:\r
+      Indicates that the cryptography function should perform encryption using\r
+      the Electronic Codebook (ECB) mode.\r
+      \r
+  - MSS_SYS_ECB_DECRYPT:\r
+      Indicates that the cryptography function should perform decryption using\r
+      the Electronic Codebook (ECB) mode.\r
+      \r
+  - MSS_SYS_CBC_ENCRYPT:\r
+      Indicates that the cryptography function should perform encryption using\r
+      the Cipher-Block Chaining (CBC) mode.\r
+      \r
+  - MSS_SYS_CBC_DECRYPT:\r
+      Indicates that the cryptography function should perform decryption using\r
+      the Cipher-Block Chaining (CBC) mode.\r
+      \r
+  - MSS_SYS_OFB_ENCRYPT:\r
+      Indicates that the cryptography function should perform encryption using\r
+      the Output Feedback (OFB) mode.\r
+      \r
+  - MSS_SYS_OFB_DECRYPT:\r
+      Indicates that the cryptography function should perform decryption using\r
+      the Output Feedback (OFB) mode.\r
+      \r
+  - MSS_SYS_CTR_ENCRYPT:\r
+      Indicates that the cryptography function should perform encryption using\r
+      the Counter (CTR) mode.\r
+      \r
+  - MSS_SYS_CTR_DECRYPT:\r
+      Indicates that the cryptography function should perform decryption using\r
+      the Counter (CTR) mode.\r
+ */\r
+#define MSS_SYS_ECB_ENCRYPT     0x00u\r
+#define MSS_SYS_ECB_DECRYPT     0x80u\r
+#define MSS_SYS_CBC_ENCRYPT     0x01u\r
+#define MSS_SYS_CBC_DECRYPT     0x81u\r
+#define MSS_SYS_OFB_ENCRYPT     0x02u\r
+#define MSS_SYS_OFB_DECRYPT     0x82u\r
+#define MSS_SYS_CTR_ENCRYPT     0x03u\r
+#define MSS_SYS_CTR_DECRYPT     0x83u\r
+\r
+/*------------------------------------------------------------------------------\r
+  These constants are used by non deterministic random bit generator (NDRBG)\r
+  services to communicate the outcome of a system services request. These status\r
+  codes are only used by NDRBG services.\r
+  \r
+  - MSS_SYS_NRBG_CATASTROPHIC_ERROR:\r
+      Indicates that a catastrophic error occurred. \r
+      \r
+  - MSS_SYS_NRBG_MAX_INST_EXCEEDED:\r
+      Indicates that the maximum number of NDRBG instances has been exceeded.\r
+      You need to release already instantiated NDRBG instances using the\r
+      MSS_SYS_ndrbg_uninstantiate() function.\r
+      \r
+  - MSS_SYS_NRBG_INVALID_HANDLE:\r
+      Indicates that the handle parameter has an invalid value.\r
+      \r
+  - MSS_SYS_NRBG_GEN_REQ_TOO_BIG:\r
+      Indicates that the requested random number is too long. The requested\r
+      length is larger than the maximum number of digits that can be generated.\r
+      \r
+  - MSS_SYS_NRBG_MAX_LENGTH_EXCEEDED:\r
+      Indicates that the supplied additional data length is exceeded.\r
+ */\r
+#define MSS_SYS_NRBG_CATASTROPHIC_ERROR     1u\r
+#define MSS_SYS_NRBG_MAX_INST_EXCEEDED      2u\r
+#define MSS_SYS_NRBG_INVALID_HANDLE         3u\r
+#define MSS_SYS_NRBG_GEN_REQ_TOO_BIG        4u\r
+#define MSS_SYS_NRBG_MAX_LENGTH_EXCEEDED    5u\r
+\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+  The sys_serv_async_event_handler_t typedef specifies the function prototype of\r
+  an asynchronous event handler that can be registered with the System Services\r
+  driver to handle asynchronous events. This is the prototype of a function can\r
+  be optionally implemented by the application to handle asynchronous events\r
+  such as Flash*Freeze shutdown and Flash*Freeze exit.\r
+ */\r
+typedef void (*sys_serv_async_event_handler_t)(uint8_t event_opcode);\r
+ \r
+/*-------------------------------------------------------------------------*//**\r
+  This constant is used as parameter to the MSS_SYS_init() function to indicate\r
+  that the application code does not supply an asynchronous event handler\r
+  function.\r
+ */\r
+#define MSS_SYS_NO_EVENT_HANDLER    ((sys_serv_async_event_handler_t)0)\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+  The MSS_SYS_init function initializes the system services communication with\r
+  the System Controller.\r
+   \r
+  @param\r
+    The event_handler parameter specifies an optional asynchronous event\r
+    handler function. This event handler function is provided by the\r
+    application. It will be called by the System Services driver whenever an\r
+    asynchronous event is received from the SmartFusion2 System controller.\r
+    This event handler is typically used to handle entry and exit of\r
+    Flash*Freeze mode.\r
+    \r
+  @return\r
+    This function does not return a value.\r
+ */\r
+void MSS_SYS_init(sys_serv_async_event_handler_t event_handler);\r
+\r
+/*==============================================================================\r
+ * Device and Design Information Services.\r
+ */\r
+ \r
+/*-------------------------------------------------------------------------*//**\r
+  The MSS_SYS_get_serial_number function fetches the 128-bit Device Serial\r
+  Number (DSN).\r
+  \r
+  @param p_serial_number\r
+    The p_serial_number parameter is a pointer to the 16-bytes buffer where the\r
+    serial number will be written by this system service.\r
+  \r
+  @return\r
+    The MSS_SYS_get_serial_number function returns one of following status codes:\r
+        - MSS_SYS_SUCCESS\r
+        - MSS_SYS_MEM_ACCESS_ERROR\r
+        - MSS_SYS_UNEXPECTED_ERROR\r
+ */\r
+uint8_t MSS_SYS_get_serial_number\r
+(\r
+    uint8_t * p_serial_number\r
+);\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+   The MSS_SYS_get_user_code functions fetches the 32-bit USERCODE.\r
+  \r
+  @param p_user_code\r
+    The p_user_code parameter is a pointer to the 4-bytes buffer where the\r
+    USERCODE will be written by this system service.\r
+  \r
+  @return\r
+    The MSS_SYS_get_user_code function returns one of following status codes:\r
+        - MSS_SYS_SUCCESS\r
+        - MSS_SYS_MEM_ACCESS_ERROR\r
+        - MSS_SYS_UNEXPECTED_ERROR\r
+ */\r
+uint8_t MSS_SYS_get_user_code\r
+(\r
+    uint8_t * p_user_code\r
+);\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+  The MSS_SYS_get_design_version function fetches the design version.\r
+  \r
+  @param p_design_version\r
+    The p_design_version parameter is a pointer to the 2-bytes buffer where the\r
+    design version will be written by this system service.\r
+  \r
+  @return\r
+    The MSS_SYS_get_design_version function returns one of following status codes:\r
+        - MSS_SYS_SUCCESS\r
+        - MSS_SYS_MEM_ACCESS_ERROR\r
+        - MSS_SYS_UNEXPECTED_ERROR\r
+ */\r
+uint8_t MSS_SYS_get_design_version\r
+(\r
+    uint8_t * p_design_version\r
+);\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+  The MSS_SYS_get_device_certificate function fetches the device certificate.\r
+  \r
+  @param p_device_certificate\r
+    The p_device_certificate parameter is a pointer to the 512-bytes buffer\r
+    where the device certificate will be written by this system service.\r
+  \r
+  @return\r
+    The MSS_SYS_get_device_certificate function returns one of following status\r
+    codes:\r
+        - MSS_SYS_SUCCESS\r
+        - MSS_SYS_MEM_ACCESS_ERROR\r
+        - MSS_SYS_UNEXPECTED_ERROR\r
+ */\r
+uint8_t MSS_SYS_get_device_certificate\r
+(\r
+    uint8_t * p_device_certificate\r
+);\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+  The MSS_SYS_flash_freeze function requests the FPGA to enter the Flash*Freeze\r
+  mode.\r
+  \r
+  @param options\r
+    The options parameter can be used to power down additional parts of\r
+    SmartFusion2 when the FPGA fabric enters Flash*Freeze mode. This parameter\r
+    is a bit mask of the following options:\r
+        - MSS_SYS_FPGA_POWER_DOWN\r
+        - MSS_SYS_ENVM0_POWER_DOWN\r
+        - MSS_SYS_ENVM1_POWER_DOWN\r
+        - MSS_SYS_MPLL_POWER_DOWN\r
+    MSS_SYS_FPGA_POWER_DOWN on its own will only power down the FPGA fabric.\r
+    MSS_SYS_ENVM0_POWER_DOWN and MSS_SYS_ENVM1_POWER_DOWN specify that eNVM\r
+    blocks 0 and 1 respectively should enter the deep power down state during\r
+    Flash*Freeze.\r
+    MSS_SYS_MPLL_POWER_DOWN specifies that the MSS PLL is powered down during\r
+    the Flash*Freeze period.\r
+    \r
+  @return\r
+    The MSS_SYS_flash_freeze function returns one of following status codes:\r
+        - MSS_SYS_SUCCESS\r
+        - MSS_SYS_MEM_ACCESS_ERROR\r
+        - MSS_SYS_UNEXPECTED_ERROR\r
+        \r
+  The following example demonstrates how to request the FPGA fabric and both\r
+  eNVM0 and eNVM1 to enter the Flash*Freeze mode:\r
+  @code\r
+    MSS_SYS_flash_freeze(MSS_SYS_FPGA_POWER_DOWN | MSS_SYS_ENVM0_POWER_DOWN | MSS_SYS_MPLL_POWER_DOWN);\r
+  @endcode\r
+ */\r
+uint8_t MSS_SYS_flash_freeze(uint8_t options);\r
+\r
+/*==============================================================================\r
+ * Cryptographic Services.\r
+ */\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+  The MSS_SYS_128bit_aes function provides access to the SmartFusion2 AES-128\r
+  cryptography service.\r
+  \r
+  @param key\r
+    The key parameter is a pointer to a 16-bytes array containing the key to use\r
+    for the requested encryption/decryption operation.\r
+  \r
+  @param iv\r
+    The iv parameter is a pointer to a 16-bytes array containing the\r
+    intialization vector that will be used as part of the requested \r
+    encryption/decryption operation. Its use is different depending on the mode.\r
+        -----------------------------------------\r
+        | Mode |             Usage              |\r
+        -----------------------------------------\r
+        | ECB  | Ignored.                       |\r
+        -----------------------------------------\r
+        | CBC  | Randomization.                 |\r
+        -----------------------------------------\r
+        | OFB  | Randomization.                 |\r
+        -----------------------------------------\r
+        | CTR  | Used as initial counter value. |\r
+        -----------------------------------------\r
+  \r
+  @param nb_blocks\r
+    The nb_blocks parameter specifies the number of 128-bit blocks of\r
+    plaintext/ciphertext to be processed by the AES-128 system service.\r
+  \r
+  @param mode\r
+    The mode parameter specifies the cipher mode of operation and whether the\r
+    source text must be encrypted or decrypted. The modes of operation are:\r
+        - Electronic Codebook (ECB)\r
+        - Cipher-Block Chaining (CBC)\r
+        - Output Feedback (OFB)\r
+        - Counter (CTR)\r
+    The CTR mode uses the content of the initialization vector as its intial\r
+    counter value. The counter increment is 2^64.\r
+    Allowed values for the mode parameter are:\r
+        - MSS_SYS_ECB_ENCRYPT\r
+        - MSS_SYS_ECB_DECRYPT\r
+        - MSS_SYS_CBC_ENCRYPT\r
+        - MSS_SYS_CBC_DECRYPT\r
+        - MSS_SYS_OFB_ENCRYPT\r
+        - MSS_SYS_OFB_DECRYPT\r
+        - MSS_SYS_CTR_ENCRYPT\r
+        - MSS_SYS_CTR_DECRYPT\r
+    \r
+  @param dest_addr\r
+    The dest_addr parameter is a pointer to the memory buffer where the result\r
+    of the encryption/decryption operation will be stored.\r
+  \r
+  @param src_addr\r
+    The src_addr parameter is a pointer to the memory buffer containg the source\r
+    plaintext/ciphertext to be encrypted/decrypted.\r
+  \r
+  @return\r
+    The MSS_SYS_128bit_aes function returns one of following status codes:\r
+        - MSS_SYS_SUCCESS\r
+        - MSS_SYS_MEM_ACCESS_ERROR\r
+        - MSS_SYS_SERVICE_DISABLED_BY_USER\r
+ */\r
+uint8_t MSS_SYS_128bit_aes\r
+(\r
+    const uint8_t * key,\r
+    const uint8_t * iv,\r
+    uint16_t nb_blocks,\r
+    uint8_t mode,\r
+    uint8_t * dest_addr,\r
+    const uint8_t * src_addr\r
+);\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+  The MSS_SYS_256bit_aes function provides access to the SmartFusion2 AES-256\r
+  cryptography service.\r
+  \r
+  @param key\r
+    The key parameter is a pointer to a 32-bytes array containing the key to use\r
+    for the requested encryption/decryption operation.\r
+  \r
+  @param iv\r
+    The iv parameter is a pointer to a 16-bytes array containing the\r
+    intialization vector that will be used as part of the requested \r
+    encryption/decryption operation. Its use is different depending on the mode.\r
+        -----------------------------------------\r
+        | Mode |             Usage              |\r
+        -----------------------------------------\r
+        | ECB  | Ignored.                       |\r
+        -----------------------------------------\r
+        | CBC  | Randomization.                 |\r
+        -----------------------------------------\r
+        | OFB  | Randomization.                 |\r
+        -----------------------------------------\r
+        | CTR  | Used as initial counter value. |\r
+        -----------------------------------------\r
+  \r
+  @param nb_blocks\r
+    The nb_blocks parameter specifies the number of 128-bit blocks of\r
+    plaintext/ciphertext requested to be processed by the AES-128 system service.\r
+  \r
+  @param mode\r
+    The mode parameter specifies the cipher mode of operation and whether the\r
+    source text must be encrypted or decrypted. The modes of operation are:\r
+        - Electronic Codebook (ECB)\r
+        - Cypher-Block Chaining (CBC)\r
+        - Output Feedback (OFB)\r
+        - Counter (CTR)\r
+    The CTR mode uses the content of the initialization vector as its intial\r
+    counter value. The counter increment is 2^64.\r
+    Allowed values for the mode parameter are:\r
+        - MSS_SYS_ECB_ENCRYPT\r
+        - MSS_SYS_ECB_DECRYPT\r
+        - MSS_SYS_CBC_ENCRYPT\r
+        - MSS_SYS_CBC_DECRYPT\r
+        - MSS_SYS_OFB_ENCRYPT\r
+        - MSS_SYS_OFB_DECRYPT\r
+        - MSS_SYS_CTR_ENCRYPT\r
+        - MSS_SYS_CTR_DECRYPT\r
+    \r
+  @param dest_addr\r
+    The dest_addr parameter is a pointer to the memory buffer where the result\r
+    of the encryption/decryption operation will be stored.\r
+  \r
+  @param src_addr\r
+    The src_addr parameter is a pointer to the memory buffer containg the source\r
+    plaintext/ciphertext to be encrypted/decrypted.\r
+  \r
+  @return\r
+    The MSS_SYS_256bit_aes function returns one of following status codes:\r
+        - MSS_SYS_SUCCESS\r
+        - MSS_SYS_MEM_ACCESS_ERROR\r
+        - MSS_SYS_SERVICE_DISABLED_BY_USER\r
+ */\r
+uint8_t MSS_SYS_256bit_aes\r
+( \r
+    const uint8_t * key,\r
+    const uint8_t * iv,\r
+    uint16_t nb_blocks,\r
+    uint8_t mode,\r
+    uint8_t * dest_addr,\r
+    const uint8_t * src_addr\r
+);\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+  The MSS_SYS_sha256 function provides access to the SmartFusion2 SHA-256\r
+  cryptography service.\r
+  \r
+  @param p_data_in\r
+    The p_data_in parameter is a pointer to the memory location containing the\r
+    data that will be hashed using the SHA-256 system service.\r
+  \r
+  @param length\r
+    The length parameter specifies the length in bits of the data to hash.\r
+  \r
+  @param result\r
+    The result parameter is a pointer to a 32 bytes buffer where the hash result\r
+    will be stored.\r
+  \r
+  @return\r
+    The MSS_SYS_sha256 function returns one of following status codes:\r
+        - MSS_SYS_SUCCESS\r
+        - MSS_SYS_MEM_ACCESS_ERROR\r
+        - MSS_SYS_SERVICE_DISABLED_BY_USER\r
+ */\r
+uint8_t MSS_SYS_sha256\r
+(\r
+    const uint8_t * p_data_in,\r
+    uint32_t length,\r
+    uint8_t * result\r
+);\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+  The MSS_SYS_hmac function provides access to the SmartFusion2 HMAC\r
+  cryptography service. The HMAC system service generates message authentication\r
+  codes using the SHA-256 hash function.\r
+  \r
+  @param key\r
+    The key parameter is a pointer to a 32 bytes array containing the key used\r
+    to generate the message authentication code.\r
+  \r
+  @param p_data_in\r
+    The p_data_in parameter is a pointer to the data to be authenticated.\r
+  \r
+  @param length\r
+    The length parameter specifies the number of data bytes for which to generate\r
+    the authentication code. It is the size of the data pointed to by the\r
+    p_data_in parameter.\r
+  \r
+  @param p_result\r
+    The p_result parameter is a pointer to a 32 bytes buffer where the\r
+    authentication code generated by the HMAC system service will be stored.\r
+  \r
+  @return\r
+    The MSS_SYS_hmac function returns one of following status codes:\r
+        - MSS_SYS_SUCCESS\r
+        - MSS_SYS_MEM_ACCESS_ERROR\r
+        - MSS_SYS_SERVICE_DISABLED_BY_USER\r
+ */\r
+uint8_t MSS_SYS_hmac\r
+(\r
+    const uint8_t * key,\r
+    const uint8_t * p_data_in,\r
+    uint32_t length,\r
+    uint8_t * p_result\r
+);\r
+\r
+/*==============================================================================\r
+ * CRI Licensed Services.\r
+ */\r
+#define SYS_SERVICE_NOT_LICENCED        243u\r
+\r
+/*==============================================================================\r
+ * Non Deterministic Random Bit Generator Services.\r
+ */\r
+/*-------------------------------------------------------------------------*//**\r
+  The MSS_SYS_nrbg_self_test() function performs a self test of the\r
+  non-deterministic random bit generator (NRBG).\r
+  \r
+  @return\r
+    The MSS_SYS_nrbg_self_test function returns one of following status codes:\r
+        - MSS_SYS_SUCCESS\r
+        - MSS_SYS_NRBG_CATASTROPHIC_ERROR\r
+        - MSS_SYS_NRBG_MAX_INST_EXCEEDED\r
+        - MSS_SYS_NRBG_INVALID_HANDLE\r
+        - MSS_SYS_NRBG_GEN_REQ_TOO_BIG\r
+        - MSS_SYS_NRBG_MAX_LENGTH_EXCEEDED\r
+        - MSS_SYS_SERVICE_DISABLED_BY_FACTORY\r
+        - MSS_SYS_SERVICE_DISABLED_BY_USER\r
+ */\r
+uint8_t MSS_SYS_nrbg_self_test(void);\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+  The MSS_SYS_nrbg_instantiate() function instantiates a non-deterministic\r
+  random bit generator (NRBG) instance. A maximum of two concurrent instances\r
+  are available.\r
+  \r
+  @param personalization_str\r
+    The personalization_str parameter is a pointer to a buffer containing a\r
+    random bit generator personalization string. The personalization string\r
+    can be up to 128 bytes long.\r
+  \r
+  @param personalization_str_length\r
+    The personalization_str_length parameter specifies the byte length of the\r
+    personalization string pointed to by personalization_str.\r
+  \r
+  @param p_nrbg_handle\r
+    The p_nrbg_handle parameter is a pointer to a byte that will contain the\r
+    handle of the instantiated NRBG if this function call suceeds.\r
+  \r
+  @return\r
+    The MSS_SYS_nrbg_instantiate function returns one of following status codes:\r
+        - MSS_SYS_SUCCESS\r
+        - MSS_SYS_NRBG_CATASTROPHIC_ERROR\r
+        - MSS_SYS_NRBG_MAX_INST_EXCEEDED\r
+        - MSS_SYS_NRBG_INVALID_HANDLE\r
+        - MSS_SYS_NRBG_GEN_REQ_TOO_BIG\r
+        - MSS_SYS_NRBG_MAX_LENGTH_EXCEEDED\r
+        - MSS_SYS_SERVICE_DISABLED_BY_FACTORY\r
+        - MSS_SYS_SERVICE_DISABLED_BY_USER\r
+ */\r
+uint8_t MSS_SYS_nrbg_instantiate\r
+(\r
+    const uint8_t * personalization_str,\r
+    uint16_t personalization_str_length,\r
+    uint8_t * p_nrbg_handle\r
+);\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+  The MSS_SYS_nrbg_generate function generates a random bit sequence up to\r
+  128 bytes long.\r
+  \r
+  @param p_requested_data\r
+    The p_requested_data parameter is a pointer to the buffer where the requested\r
+    random data will be stored on completion of this system servide.\r
+  \r
+  @param p_additional_input\r
+    The p_additional_input parameter is a pointer to the buffer containing\r
+    additional input data for the random bit generation.\r
+  \r
+  @param requested_length\r
+    The requested_length parameter specifies the number of random data bytes\r
+    requested to be generated. The maximum generated data length is 128 bytes.\r
+  \r
+  @param additional_input_length\r
+    The additional_input_length parameter specifies the number of addditonal\r
+    input bytes to use in the random data generation.\r
+  \r
+  @param pr_req\r
+    The pr_req parameter specifies if prediction resistance is requested.\r
+  \r
+  @param nrbg_handle\r
+    The nrbg_handle parameter specifies which non-deterministic random bit\r
+    generator (NRBG) instance will be used to generate the random data. The\r
+    value of nrbg_handle is obtained as a result of a previous call to the\r
+    MSS_SYS_nrbg_instantiate() function.\r
+  \r
+  @return\r
+    The MSS_SYS_nrbg_generate function returns one of following status codes:\r
+        - MSS_SYS_SUCCESS\r
+        - MSS_SYS_NRBG_CATASTROPHIC_ERROR\r
+        - MSS_SYS_NRBG_MAX_INST_EXCEEDED\r
+        - MSS_SYS_NRBG_INVALID_HANDLE\r
+        - MSS_SYS_NRBG_GEN_REQ_TOO_BIG\r
+        - MSS_SYS_NRBG_MAX_LENGTH_EXCEEDED\r
+        - MSS_SYS_SERVICE_DISABLED_BY_FACTORY\r
+        - MSS_SYS_SERVICE_DISABLED_BY_USER\r
+   \r
+ */\r
+uint8_t MSS_SYS_nrbg_generate\r
+(\r
+    const uint8_t * p_requested_data,\r
+    const uint8_t * p_additional_input,\r
+    uint8_t requested_length,\r
+    uint8_t additional_input_length,\r
+    uint8_t pr_req,\r
+    uint8_t nrbg_handle\r
+);\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+  The MSS_SYS_nrbg_reseed() function is used to reseed the non-deterministic\r
+  random bit generator (NRBG) identified by the nrbg_handle parameter.\r
+  \r
+  @param p_additional_input\r
+    The additional_input_length parameter specifies the number of additional\r
+    input bytes used to reseed the NRBG identified by the nrbg_handle parameter.\r
+  \r
+  @param additional_input_length\r
+    The additional_input_length parameter specifies the number of additional\r
+    input bytes used to reseed the NRBG.\r
+  \r
+  @param nrbg_handle\r
+    The nrbg_handle parameter specifies which NRBG instance to reseed. The value\r
+    of nrbg_handle is obtained as a result of a previous call to the\r
+    MSS_SYS_nrbg_instantiate() function.\r
+  \r
+  @return\r
+    The MSS_SYS_nrbg_reseed function returns one of following status codes:\r
+        - MSS_SYS_SUCCESS\r
+        - MSS_SYS_NRBG_CATASTROPHIC_ERROR\r
+        - MSS_SYS_NRBG_MAX_INST_EXCEEDED\r
+        - MSS_SYS_NRBG_INVALID_HANDLE\r
+        - MSS_SYS_NRBG_GEN_REQ_TOO_BIG\r
+        - MSS_SYS_NRBG_MAX_LENGTH_EXCEEDED\r
+        - MSS_SYS_SERVICE_DISABLED_BY_FACTORY\r
+        - MSS_SYS_SERVICE_DISABLED_BY_USER\r
+   \r
+ */\r
+uint8_t MSS_SYS_nrbg_reseed\r
+(\r
+    const uint8_t * p_additional_input,\r
+    uint8_t additional_input_length,\r
+    uint8_t nrbg_handle\r
+);\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+  The MSS_SYS_nrbg_uninstantiate() function releases the non-deterministic\r
+  random bit generator (NRBG) identified by the nrbg_handle parameter.\r
+  \r
+  @param nrbg_handle\r
+    The nrbg_handle parameter specifies which NRBG instance will be released.\r
+    The value of nrbg_handle is obtained as a result of a previous call to the\r
+    MSS_SYS_nrbg_instantiate() function.\r
+  \r
+  @return\r
+    The MSS_SYS_nrbg_uninstantiate function returns one of following status codes:\r
+        - MSS_SYS_SUCCESS\r
+        - MSS_SYS_NRBG_CATASTROPHIC_ERROR\r
+        - MSS_SYS_NRBG_MAX_INST_EXCEEDED\r
+        - MSS_SYS_NRBG_INVALID_HANDLE\r
+        - MSS_SYS_NRBG_GEN_REQ_TOO_BIG\r
+        - MSS_SYS_NRBG_MAX_LENGTH_EXCEEDED\r
+        - MSS_SYS_SERVICE_DISABLED_BY_FACTORY\r
+        - MSS_SYS_SERVICE_DISABLED_BY_USER\r
+   \r
+ */\r
+uint8_t MSS_SYS_nrbg_uninstantiate\r
+(\r
+    uint8_t nrbg_handle\r
+);\r
+\r
+/*==============================================================================\r
+ * Programming Services.\r
+ */\r
+\r
+#define MSS_SYS_PROG_AUTHENTICATE    0u\r
+#define MSS_SYS_PROG_PROGRAM         1u\r
+#define MSS_SYS_PROG_VERIFY          2u\r
+   \r
+/*-------------------------------------------------------------------------*//**\r
+  The ISP Service allows the MSS Cortex-M3 processor to directly provide a\r
+  bitstream for programming. The ISP Service is initiated by a call to\r
+  MSS_SYS_start_isp(). The ISP Service can:\r
+    - authenticate a programming bitstream\r
+    - program a bitstream\r
+    - verify that a programming bitstream has been correctly programmed\r
+\r
+  The application must provide two functions as parameter to the\r
+  MSS_SYS_start_isp() function. The first function will be used by the ISP\r
+  Service to read the programming bitstream. The second function will be used by\r
+  the ISP Service to notify the application that the ISP Service completed.\r
+  \r
+  @param mode\r
+    The mode parameter specifies ISP service to perform. It can be one of:\r
+        - MSS_SYS_PROG_AUTHENTICATE\r
+        - MSS_SYS_PROG_PROGRAM\r
+        - MSS_SYS_PROG_VERIFY\r
+ \r
+  @param page_read_handler\r
+    The page_read_handler parameter is a pointer to a function with the\r
+    following prototype:\r
+        uint32_t page_read_handler(uint8 const ** pp_next_page);\r
+ \r
+  @param isp_completion_handler\r
+    The isp_completion_handler parameter is a pointer to a function with the\r
+    following prototype. This function will be called when the ISP service\r
+    completes.\r
+ \r
+    The isp_completion_handler function will receive one of the following status\r
+    codes:\r
+        - MSS_SYS_SUCCESS\r
+        - MSS_SYS_CHAINING_MISMATCH\r
+        - MSS_SYS_UNEXPECTED_DATA_RECEIVED\r
+        - MSS_SYS_INVALID_ENCRYPTION_KEY\r
+        - MSS_SYS_INVALID_COMPONENT_HEADER\r
+        - MSS_SYS_BACK_LEVEL_NOT_SATISFIED\r
+        - MSS_SYS_DSN_BINDING_MISMATCH\r
+        - MSS_SYS_ILLEGAL_COMPONENT_SEQUENCE\r
+        - MSS_SYS_INSUFFICIENT_DEV_CAPABILITIES\r
+        - MSS_SYS_INCORRECT_DEVICE_ID\r
+        - MSS_SYS_UNSUPPORTED_BITSTREAM_PROT_VER\r
+        - MSS_SYS_VERIFY_NOT_PERMITTED_ON_BITSTR\r
+        - MSS_SYS_ABORT\r
+        - MSS_SYS_NVM_VERIFY_FAILED\r
+        - MSS_SYS_DEVICE_SECURITY_PROTECTED\r
+        - MSS_SYS_PROGRAMMING_MODE_NOT_ENABLED\r
+        - MSS_SYS_SERVICE_DISABLED_BY_USER\r
+        \r
+  @return\r
+    This function does not return a value.\r
+ */\r
+void MSS_SYS_start_isp\r
+(\r
+    uint8_t mode,\r
+    uint32_t (*page_read_handler)(uint8_t const **),\r
+    void (*isp_completion_handler)(uint32_t)\r
+);\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+  Recalculates and compares digests of selected components.\r
+  \r
+  @param options\r
+    The options parameter specifies which components' digest will be recalculated\r
+    and checked. Each bit is used to identify a componetn as follows:\r
+        - bit 0: FPGA fabric\r
+        - bit 1: eNVM0\r
+        - bit 2: eNVM1\r
+    Note: The FPGA fabric will enter the FlashFreeze state if powered up when\r
+          its digest is checked.\r
+ \r
+  @return\r
+    The MSS_SYS_check_digest function returns the result of the digest check. The\r
+    meaning of the digest check return value is as follows:\r
+        bit 0: Fabric digest error\r
+        bit 1: ENVM0 digest error\r
+        bit 2: ENVM1 digest error\r
+    A '1' in one of the above bits indicates a digest mismatch.\r
+ */\r
+#define MSS_SYS_DIGEST_CHECK_FABRIC     0x01u\r
+#define MSS_SYS_DIGEST_CHECK_ENVM0      0x02u\r
+#define MSS_SYS_DIGEST_CHECK_ENVM1      0x04u\r
+\r
+uint8_t MSS_SYS_check_digest\r
+(\r
+    uint8_t options\r
+);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __MSS_SYS_SERVICES_H_ */\r
diff --git a/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers/mss_timer/mss_timer.h b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers/mss_timer/mss_timer.h
new file mode 100644 (file)
index 0000000..cb5e051
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers/mss_timer/mss_timer.h
@@ -0,0 +1,595 @@
+/*******************************************************************************\r
+ * (c) Copyright 2010-2013 Microsemi SoC Products Group.  All rights reserved.\r
+ * \r
+ * SmartFusion2 microcontroller subsystem (MSS) timer driver API.\r
+ *\r
+ * SVN $Revision: 5111 $\r
+ * SVN $Date: 2013-02-18 17:03:09 +0000 (Mon, 18 Feb 2013) $\r
+ */\r
+/*=========================================================================*//**\r
+  @mainpage SmartFusion2 MSS Timer Bare Metal Driver.\r
+\r
+  @section intro_sec Introduction\r
+  The SmartFusion2 Microcontroller Subsystem (MSS) includes a timer hardware\r
+  block which can be used as two independent 32-bits timers or as a single\r
+  64-bits timer in periodic or one-shot mode. \r
+\r
+  This driver provides a set of functions for controlling the MSS timer as part\r
+  of a bare metal system where no operating system is available. These drivers\r
+  can be adapted for use as part of an operating system but the implementation\r
+  of the adaptation layer between this driver and the operating system's driver\r
+  model is outside the scope of this driver.\r
+  \r
+  @section theory_op Theory of Operation\r
+  The MSS Timer driver uses the SmartFusion2 "Cortex Microcontroler Software\r
+  Interface Standard - Peripheral Access Layer" (CMSIS-PAL) to access hadware\r
+  registers. You must ensure that the SmartFusion2 CMSIS-PAL is either included\r
+  in the software toolchain used to build your project or is included in your\r
+  project. The most up-to-date SmartFusion2 CMSIS-PAL files can be obtained using\r
+  the Actel Firmware Catalog.\r
+  The SmartFusion2 MSS Timer can be used in one of two mutually exclusive modes;\r
+  either as a single 64-bits timer or as two independent 32-bits timers. The MSS\r
+  Timer can be used in either periodic mode or one-shot mode. A timer configured\r
+  for periodic mode operations will generate an interrupt and reload its\r
+  down-counter when it reaches 0. The timer will then continue decrementing from\r
+  its reload value without waiting for the interrupt to be cleared. A timer\r
+  configured for one-shot mode will only generate an interrupt once when its\r
+  down-counter reaches 0. It must be explitcitly reloaded to start decrementing\r
+  again.\r
+  \r
+  The MSS Timer driver functions are grouped into the following categories:\r
+    - Initialization and Configuration\r
+    - Timer control\r
+    - Interrupt control\r
+  \r
+  The MSS Timer driver provides three initialization functions:\r
+    - MSS_TIM1_init()\r
+    - MSS_TIM2_init()\r
+    - MSS_TIM64_init()\r
+  The MSS Timer driver is initialized through calls to these functions and at\r
+  least one of them must be called before any other MSS Timer driver functions\r
+  can be called.\r
+  You should only use the MSS_TIM1_init() and MSS_TIM2_init() functions if you\r
+  intend to use the timer in 32-bits mode. Use the MSS_TIM64_init() function is\r
+  you intend to use the MSS Timer as a single 64-bits timer. The initialization\r
+  functions take a single parameter specifying the operating mode of the timer\r
+  being initialized.\r
+  \r
+  Once initialized a timer can be controlled using the following functions:\r
+    - MSS_TIM1_load_immediate()\r
+    - MSS_TIM1_load_background()\r
+    - MSS_TIM1_get_current_value()\r
+    - MSS_TIM1_start()\r
+    - MSS_TIM1_stop()\r
+    - MSS_TIM2_load_immediate()\r
+    - MSS_TIM2_load_background()\r
+    - MSS_TIM2_get_current_value()\r
+    - MSS_TIM2_start()\r
+    - MSS_TIM2_stop()\r
+    - MSS_TIM64_load_immediate()\r
+    - MSS_TIM64_load_background()\r
+    - MSS_TIM64_get_current_value()\r
+    - MSS_TIM64_start()\r
+    - MSS_TIM64_stop()\r
+  \r
+  Timer interrupts are controlled using the following functions:\r
+    - MSS_TIM1_enable_irq()\r
+    - MSS_TIM1_disable_irq()\r
+    - MSS_TIM1_clear_irq()\r
+    - MSS_TIM2_enable_irq()\r
+    - MSS_TIM2_disable_irq()\r
+    - MSS_TIM2_clear_irq()\r
+    - MSS_TIM64_enable_irq()\r
+    - MSS_TIM64_disable_irq()\r
+    - MSS_TIM64_clear_irq()\r
+  \r
+  The function prototypes for the timer interrupt handlers are:\r
+    - void Timer1_IRQHandler( void )\r
+    - void Timer2_IRQHandler( void )\r
+  Entries for these interrupt handlers are provided in the SmartFusion2 CMSIS-PAL\r
+  vector table. To add a Timer 1 interrupt handler, you must implement a\r
+  Timer1_IRQHandler( ) function as part of your application code. To add a\r
+  Timer 2 interrupt handler, you must implement a Timer2_IRQHandler( ) function\r
+  as part of your application code. When using the MSS Timer as a 64-bit timer,\r
+  you must implement a Timer1_IRQHandler( ) function as part of your\r
+  application code. The Timer 2 interrupt is not used when the MSS Timer is\r
+  configured as a 64-bit timer.\r
+  \r
+ *//*=========================================================================*/\r
+#ifndef MSS_TIMER_H_\r
+#define MSS_TIMER_H_\r
+\r
+\r
+#include "../../CMSIS/m2sxxx.h"\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif \r
+\r
+/*-------------------------------------------------------------------------*//**\r
+ * Timer mode selection. This enumeration is used to select between the two\r
+ * possible timer modes of operation: periodic and one-shot mode. It is used as\r
+ * an argument to the MSS_TIM1_init(), MSS_TIM2_init() and MSS_TIM64_init()\r
+ * functions.\r
+ * MSS_TIMER_PERIODIC_MODE:\r
+ *  In periodic mode the timer generates interrupts at constant intervals. On \r
+ *  reaching zero, the timer's counter is reloaded with a value held in a\r
+ *  register and begins counting down again.\r
+ * MSS_TIMER_ONE_SHOT_MODE:\r
+ *  The timer generates a single interrupt in this mode. On reaching zero, the\r
+ *  timer's counter halts until reprogrammed by the user.\r
+ */\r
+typedef enum __mss_timer_mode_t\r
+{\r
+    MSS_TIMER_PERIODIC_MODE = 0,\r
+    MSS_TIMER_ONE_SHOT_MODE = 1\r
+} mss_timer_mode_t;\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+  The MSS_TIM1_init() function initializes the SmartFusion2 MSS Timer block for\r
+  use as a 32-bit timer and selects the operating mode for Timer 1. This function\r
+  takes the MSS Timer block out of reset in case this hasn\92t been done already,\r
+  stops Timer 1, disables its interrupt and sets the Timer 1 operating mode.\r
+  Please note that the SmartFusion2 MSS Timer block cannot be used both as a\r
+  64-bit and 32-bit timer. Calling MSS_TIM1_init() will overwrite any previous\r
+  configuration of the MSS Timer as a 64-bit timer.\r
+\r
+ \r
+  @param mode\r
+    The mode parameter specifies whether the timer will operate in periodic or\r
+    one-shot mode. Allowed values for this parameter are:\r
+        - MSS_TIMER_PERIODIC_MODE\r
+        - MSS_TIMER_ONE_SHOT_MODE\r
+ */\r
+static __INLINE void MSS_TIM1_init(mss_timer_mode_t mode)\r
+{\r
+    NVIC_DisableIRQ(Timer1_IRQn);             /* Disable timer 1 irq in the Cortex-M3 NVIC */  \r
+    \r
+    SYSREG->SOFT_RST_CR &= ~SYSREG_TIMER_SOFTRESET_MASK; /* Take timer block out of reset */\r
+    \r
+    TIMER->TIM64_MODE = 0u;                     /* switch to 32 bits mode */\r
+    \r
+    TIMER_BITBAND->TIM1ENABLE = 0u;             /* disable timer */\r
+    TIMER_BITBAND->TIM1INTEN = 0u;              /* disable interrupt */\r
+    TIMER_BITBAND->TIM1MODE = (uint32_t)mode;   /* set mode (continuous/one-shot) */\r
+    \r
+    TIMER->TIM1_RIS = 1u;                       /* clear timer 1 interrupt */\r
+    NVIC_ClearPendingIRQ(Timer1_IRQn);        /* clear timer 1 interrupt within NVIC */\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+  The MSS_TIM1_start() function enables Timer 1 and starts its down-counter\r
+  decrementing from the load_value specified in previous calls to the\r
+  MSS_TIM1_load_immediate() or MSS_TIM1_load_background() functions.\r
+ */\r
+static __INLINE void MSS_TIM1_start(void)\r
+{\r
+    TIMER_BITBAND->TIM1ENABLE = 1u;    /* enable timer */\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+  The MSS_TIM1_stop() function disables Timer 1 and stops its down-counter\r
+  decrementing.\r
+ */\r
+static __INLINE void MSS_TIM1_stop(void)\r
+{\r
+    TIMER_BITBAND->TIM1ENABLE = 0u;    /* disable timer */\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+  The MSS_TIM1_get_current_value() returns the current value of the Timer 1\r
+  down-counter.\r
+  \r
+  @return\r
+    This function returns the 32-bits current value of the Timer 1 down-counter.\r
+ */\r
+static __INLINE uint32_t MSS_TIM1_get_current_value(void)\r
+{\r
+    return TIMER->TIM1_VAL;\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+  The MSS_TIM1_load_immediate() function loads the value passed by the\r
+  load_value parameter into the Timer 1 down-counter. The counter will decrement\r
+  immediately from this value once Timer 1 is enabled. The MSS Timer will\r
+  generate an interrupt when the counter reaches zero if Timer 1 interrupts are\r
+  enabled. This function is intended to be used when Timer 1 is configured for\r
+  one-shot mode to time a single delay.\r
+ \r
+  @param load_value\r
+    The load_value parameter specifies the value from which the Timer 1 down-counter\r
+    will start decrementing from.\r
+ */\r
+static __INLINE void MSS_TIM1_load_immediate(uint32_t load_value)\r
+{\r
+    TIMER->TIM1_LOADVAL = load_value;\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+  The MSS_TIM1_load_background() function is used to specify the value that will\r
+  be reloaded into the Timer 1 down-counter the next time the counter reaches\r
+  zero. This function is typically used when Timer 1 is configured for periodic\r
+  mode operation to select or change the delay period between the interrupts\r
+  generated by Timer 1.\r
+ \r
+  @param load_value\r
+    The load_value parameter specifies the value that will be loaded into the\r
+    Timer 1 down-counter the next time the down-counter reaches zero. The Timer\r
+    1 down-counter will start decrementing from this value after the current\r
+    count expires.\r
+ */\r
+static __INLINE void MSS_TIM1_load_background(uint32_t load_value)\r
+{\r
+    TIMER->TIM1_BGLOADVAL = load_value;\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+  The MSS_TIM1_enable_irq() function is used to enable interrupt generation for\r
+  Timer 1. This function also enables the interrupt in the Cortex-M3 interrupt\r
+  controller. The Timer1_IRQHandler() function will be called when a Timer 1\r
+  interrupt occurs.\r
+  Note: Note:  A Timer1_IRQHandler() default implementation is defined, with\r
+  weak linkage, in the SmartFusion2 CMSIS-PAL. You must provide your own\r
+  implementation of the Timer1_IRQHandler() function, that will override the\r
+  default implementation, to suit your application.\r
+\r
+ */\r
+static __INLINE void MSS_TIM1_enable_irq(void)\r
+{\r
+    TIMER_BITBAND->TIM1INTEN = 1u;\r
+    NVIC_EnableIRQ(Timer1_IRQn);\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+  The MSS_TIM1_disable_irq() function is used to disable interrupt generation\r
+  for Timer 1. This function also disables the interrupt in the Cortex-M3\r
+  interrupt controller.\r
+ */\r
+static __INLINE void MSS_TIM1_disable_irq(void)\r
+{\r
+    TIMER_BITBAND->TIM1INTEN = 0u;\r
+    NVIC_DisableIRQ(Timer1_IRQn);\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+  The MSS_TIM1_clear_irq() function is used to clear a pending interrupt from\r
+  Timer 1. This function also clears the interrupt in the Cortex-M3 interrupt\r
+  controller.\r
+  Note: You must call the MSS_TIM1_clear_irq() function as part of your\r
+  implementation of the Timer1_IRQHandler() Timer 1 interrupt service routine\r
+  (ISR) in order to prevent the same interrupt event retriggering a call to the\r
+  ISR.\r
+\r
+ */\r
+static __INLINE void MSS_TIM1_clear_irq(void)\r
+{\r
+    TIMER->TIM1_RIS = 1u;\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+  The MSS_TIM2_init() function initializes the SmartFusion2 MSS Timer block for\r
+  use as a 32-bit timer and selects the operating mode for Timer 2. This function\r
+  takes the MSS Timer block out of reset in case this hasn\92t been done already,\r
+  stops Timer 2, disables its interrupt and sets the Timer 2 operating mode.\r
+  Note: Please note that the SmartFusion2 MSS Timer block cannot be used both as\r
+  a 64-bit and 32-bit timer. Calling MSS_TIM2_init() will overwrite any previous\r
+  configuration of the MSS Timer as a 64-bit timer.\r
+  \r
+  @param mode\r
+    The mode parameter specifies whether the timer will operate in periodic or\r
+    one-shot mode. Allowed values for this parameter are:\r
+        - MSS_TIMER_PERIODIC_MODE\r
+        - MSS_TIMER_ONE_SHOT_MODE \r
+ */\r
+static __INLINE void MSS_TIM2_init(mss_timer_mode_t mode)\r
+{\r
+    NVIC_DisableIRQ(Timer2_IRQn);             /* Disable timer 2 irq in the Cortex-M3 NVIC */  \r
+    \r
+    SYSREG->SOFT_RST_CR &= ~SYSREG_TIMER_SOFTRESET_MASK; /* Take timer block out of reset */\r
+    \r
+    TIMER->TIM64_MODE = 0u;                     /* switch to 32 bits mode */\r
+    \r
+    TIMER_BITBAND->TIM2ENABLE = 0u;             /* disable timer */\r
+    TIMER_BITBAND->TIM2INTEN = 0u;              /* disable interrupt */\r
+    TIMER_BITBAND->TIM2MODE = (uint32_t)mode;   /* set mode (continuous/one-shot) */\r
+    \r
+    TIMER->TIM2_RIS = 1u;                       /* clear timer 2 interrupt */\r
+    NVIC_ClearPendingIRQ(Timer2_IRQn);        /* clear timer 2 interrupt within NVIC */\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+  The MSS_TIM2_start() function enables Timer 2 and  starts its down-counter\r
+  decrementing from the load_value specified in previous calls to the\r
+  MSS_TIM2_load_immediate() or MSS_TIM2_load_background() functions.\r
+ */\r
+static __INLINE void MSS_TIM2_start(void)\r
+{\r
+    TIMER_BITBAND->TIM2ENABLE = 1u;    /* enable timer */\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+  The MSS_TIM2_stop() function disables Timer 2 and stops its down-counter\r
+  decrementing.\r
+ */\r
+static __INLINE void MSS_TIM2_stop(void)\r
+{\r
+    TIMER_BITBAND->TIM2ENABLE = 0u;    /* disable timer */\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+  The MSS_TIM2_get_current_value() returns the current value of the Timer 2\r
+  down-counter.\r
+ */\r
+static __INLINE uint32_t MSS_TIM2_get_current_value(void)\r
+{\r
+    return TIMER->TIM2_VAL;\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+  The MSS_TIM2_load_immediate() function loads the value passed by the\r
+  load_value parameter into the Timer 2 down-counter. The counter will decrement\r
+  immediately from this value once Timer 2 is enabled. The MSS Timer will\r
+  generate an interrupt when the counter reaches zero if Timer 2 interrupts are\r
+  enabled. This function is intended to be used when Timer 2 is configured for\r
+  one-shot mode to time a single delay.\r
+  \r
+  @param load_value\r
+    The load_value parameter specifies the value from which the Timer 2\r
+    down-counter will start decrementing. \r
+ */\r
+static __INLINE void MSS_TIM2_load_immediate(uint32_t load_value)\r
+{\r
+    TIMER->TIM2_LOADVAL = load_value;\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+  The MSS_TIM2_load_background() function is used to specify the value that will\r
+  be reloaded into the Timer 2 down-counter the next time the counter reaches\r
+  zero. This function is typically used when Timer 2 is configured for periodic\r
+  mode operation to select or change the delay period between the interrupts\r
+  generated by Timer 2.\r
+  \r
+  @param load_value\r
+    The load_value parameter specifies the value that will be loaded into the\r
+    Timer 2 down-counter the next time the down-counter reaches zero. The Timer\r
+    2 down-counter will start decrementing from this value after the current\r
+    count expires.\r
+ */\r
+static __INLINE void MSS_TIM2_load_background(uint32_t load_value)\r
+{\r
+    TIMER->TIM2_BGLOADVAL = load_value;\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+  The MSS_TIM2_enable_irq() function is used to enable interrupt generation for\r
+  Timer 2. This function also enables the interrupt in the Cortex-M3 interrupt\r
+  controller. The Timer2_IRQHandler() function will be called when a Timer 2\r
+  interrupt occurs.\r
+  Note: A Timer2_IRQHandler() default implementation is defined, with weak\r
+  linkage, in the SmartFusion2 CMSIS-PAL. You must provide your own implementation\r
+  of the Timer2_IRQHandler() function, that will override the default\r
+  implementation, to suit your application.\r
+ */\r
+static __INLINE void MSS_TIM2_enable_irq(void)\r
+{\r
+    TIMER_BITBAND->TIM2INTEN = 1u;\r
+    NVIC_EnableIRQ( Timer2_IRQn );\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+  The MSS_TIM2_disable_irq() function is used to disable interrupt generation\r
+  for Timer 2. This function also disables the interrupt in the Cortex-M3\r
+  interrupt controller.\r
+ */\r
+static __INLINE void MSS_TIM2_disable_irq(void)\r
+{\r
+    TIMER_BITBAND->TIM2INTEN = 0u;\r
+    NVIC_DisableIRQ(Timer2_IRQn);\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+  The MSS_TIM2_clear_irq() function is used to clear a pending interrupt from\r
+  Timer 2. This function also clears the interrupt in the Cortex-M3 interrupt\r
+  controller.\r
+  Note: You must call the MSS_TIM2_clear_irq() function as part of your\r
+  implementation of the Timer2_IRQHandler() Timer 2 interrupt service routine\r
+  (ISR) in order to prevent the same interrupt event retriggering a call to the\r
+  ISR.\r
+ */\r
+static __INLINE void MSS_TIM2_clear_irq(void)\r
+{\r
+    TIMER->TIM2_RIS = 1u;\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+  The MSS_TIM64_init() function initializes the SmartFusion2 MSS Timer block for\r
+  use as a single 64-bit timer and selects the operating mode of the timer. This\r
+  function takes the MSS Timer block out of reset in case this hasn\92t been done\r
+  already, stops the timer, disables its interrupts and sets the timer's\r
+  operating mode.\r
+  Note: Please note that the SmartFusion2 MSS Timer block cannot be used both as\r
+  a 64-bit and 32-bit timer. Calling MSS_TIM64_init() will overwrite any previous\r
+  configuration of the MSS Timer as a 32-bit timer.\r
+\r
+  @param mode\r
+    The mode parameter specifies whether the timer will operate in periodic or\r
+    one-shot mode. Allowed values for this parameter are:\r
+        - MSS_TIMER_PERIODIC_MODE\r
+        - MSS_TIMER_ONE_SHOT_MODE \r
+ */\r
+static __INLINE void MSS_TIM64_init(mss_timer_mode_t mode)\r
+{\r
+    NVIC_DisableIRQ(Timer1_IRQn);         /* disable timer 1 interrupt within NVIC */\r
+    NVIC_DisableIRQ(Timer2_IRQn);         /* disable timer 2 interrupt within NVIC */\r
+    \r
+    SYSREG->SOFT_RST_CR &= ~SYSREG_TIMER_SOFTRESET_MASK; /* Take timer block out of reset */\r
+    \r
+    TIMER->TIM64_MODE = 1u;                     /* switch to 64 bits mode */\r
+    \r
+    TIMER_BITBAND->TIM64ENABLE = 0u;            /* disable timer */\r
+    TIMER_BITBAND->TIM64INTEN = 0u;             /* disable interrupt */\r
+    TIMER_BITBAND->TIM64MODE = (uint32_t)mode;  /* set mode (continuous/one-shot) */\r
+    \r
+    TIMER->TIM1_RIS = 1u;                   /* clear timer 1 interrupt */\r
+    TIMER->TIM2_RIS = 1u;                   /* clear timer 2 interrupt */\r
+    NVIC_ClearPendingIRQ(Timer1_IRQn);    /* clear timer 1 interrupt within NVIC */\r
+    NVIC_ClearPendingIRQ(Timer2_IRQn);    /* clear timer 2 interrupt within NVIC */\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+  The MSS_TIM64_start() function enables the 64-bit timer and starts its\r
+  down-counter decrementing from the load_value specified in previous calls to\r
+  the MSS_TIM64_load_immediate() or MSS_TIM64_load_background() functions.\r
+ */\r
+static __INLINE void MSS_TIM64_start(void)\r
+{\r
+    TIMER_BITBAND->TIM64ENABLE = 1u;    /* enable timer */\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+  The MSS_TIM64_stop() function disables the 64-bit timer and stops its\r
+  down-counter decrementing.\r
+ */\r
+static __INLINE void MSS_TIM64_stop(void)\r
+{\r
+    TIMER_BITBAND->TIM64ENABLE = 0u;    /* disable timer */\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+  The MSS_TIM64_get_current_value() is used to read the current value of the\r
+  64-bit timer down-counter. \r
+ \r
+  @param load_value_u\r
+    The load_value_u parameter is a pointer to a 32-bit variable where the upper\r
+    32 bits of the current value of the 64-bit timer down-counter will be copied.\r
+    \r
+  @param load_value_l\r
+    The load_value_l parameter is a pointer to a 32-bit variable where the lower\r
+    32 bits of the current value of the 64-bit timer down-counter will be copied.\r
+    \r
+  Example:\r
+  @code\r
+    uint32_t current_value_u = 0;\r
+    uint32_t current_value_l = 0;\r
+    MSS_TIM64_get_current_value( &current_value_u, &current_value_l );\r
+  @endcode\r
+ */\r
+static __INLINE void MSS_TIM64_get_current_value\r
+(\r
+    uint32_t * load_value_u,\r
+    uint32_t * load_value_l\r
+)\r
+{\r
+    *load_value_l = TIMER->TIM64_VAL_L;\r
+    *load_value_u = TIMER->TIM64_VAL_U;\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+  The MSS_TIM64_load_immediate() function loads the values passed by the\r
+  load_value_u and load_value_l parameters into the 64-bit timer down-counter.\r
+  The counter will decrement immediately from the concatenated 64-bit value once\r
+  the 64-bit timer is enabled. The MSS Timer will generate an interrupt when the\r
+  counter reaches zero if 64-bit timer interrupts are enabled. This function is\r
+  intended to be used when the 64-bit timer is configured for one-shot mode to\r
+  time a single delay.\r
+ \r
+  @param load_value_u\r
+    The load_value_u parameter specifies the upper 32 bits of the 64-bit timer\r
+    load value from which the 64-bit timer down-counter will start decrementing.\r
+    \r
+  @param load_value_l\r
+    The load_value_l parameter specifies the lower 32 bits of the 64-bit timer\r
+    load value from which the 64-bit timer down-counter will start decrementing.\r
+ */\r
+static __INLINE void MSS_TIM64_load_immediate\r
+(\r
+    uint32_t load_value_u,\r
+    uint32_t load_value_l\r
+)\r
+{\r
+    TIMER->TIM64_LOADVAL_U = load_value_u;\r
+    TIMER->TIM64_LOADVAL_L = load_value_l;\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+  The MSS_TIM64_load_background() function is used to specify the 64-bit value\r
+  that will be reloaded into the 64-bit timer down-counter the next time the\r
+  counter reaches zero. This function is typically used when the 64-bit timer is\r
+  configured for periodic mode operation to select or change the delay period\r
+  between the interrupts generated by the 64-bit timer.\r
+ \r
+  @param load_value_u\r
+    The load_value_u parameter specifies the upper 32 bits of the 64-bit timer\r
+    load value. The concatenated 64-bit value formed from load_value_u and\r
+    load_value_l will be loaded into the 64-bit timer down-counter the next\r
+    time the down-counter reaches zero. The 64-bit timer down-counter will start\r
+    decrementing from the concatenated 64-bit value after the current count\r
+    expires.\r
+    \r
+  @param load_value_l\r
+    The load_value_l parameter specifies the lower 32 bits of the 64-bit timer\r
+    load value. The concatenated 64-bit value formed from load_value_u and\r
+    load_value_l will be loaded into the 64-bit timer down-counter the next time\r
+    the down-counter reaches zero. The 64-bit timer down-counter will start\r
+    decrementing from the concatenated 64-bit value after the current count\r
+    expires.\r
+ \r
+ */\r
+static __INLINE void MSS_TIM64_load_background\r
+(\r
+    uint32_t load_value_u,\r
+    uint32_t load_value_l\r
+)\r
+{\r
+    TIMER->TIM64_BGLOADVAL_U = load_value_u;\r
+    TIMER->TIM64_BGLOADVAL_L = load_value_l;\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+  The MSS_TIM64_enable_irq() function is used to enable interrupt generation for\r
+  the 64-bit timer. This function also enables the interrupt in the Cortex-M3\r
+  interrupt controller. The Timer1_IRQHandler() function will be called when a\r
+  64-bit timer interrupt occurs.\r
+  Note: A Timer1_IRQHandler() default implementation is defined, with weak\r
+  linkage, in the SmartFusion2 CMSIS-PAL. You must provide your own\r
+  implementation of the Timer1_IRQHandler() function, that will override the\r
+  default implementation, to suit your application.\r
+  Note: The MSS_TIM64_enable_irq() function enables and uses Timer 1 interrupts\r
+  for the 64-bit timer. Timer 2 interrupts remain disabled.\r
+ */\r
+static __INLINE void MSS_TIM64_enable_irq(void)\r
+{\r
+    TIMER_BITBAND->TIM64INTEN = 1u;\r
+    NVIC_EnableIRQ(Timer1_IRQn);\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+  The MSS_TIM64_disable_irq() function is used to disable interrupt generation\r
+  for the 64-bit timer. This function also disables the interrupt in the\r
+  Cortex-M3 interrupt controller.\r
+ */\r
+static __INLINE void MSS_TIM64_disable_irq(void)\r
+{\r
+    TIMER_BITBAND->TIM64INTEN = 0u;\r
+    NVIC_DisableIRQ(Timer1_IRQn);\r
+}\r
+\r
+/*-------------------------------------------------------------------------*//**\r
+  The MSS_TIM64_clear_irq() function is used to clear a pending interrupt from\r
+  the 64-bit timer. This function also clears the interrupt in the Cortex-M3\r
+  interrupt controller.\r
+  Note: You must call the MSS_TIM64_clear_irq() function as part of your\r
+  implementation of the Timer1_IRQHandler() 64-bit timer interrupt service\r
+  routine (ISR) in order to prevent the same interrupt event retriggering a\r
+  call to the ISR.\r
+ */\r
+static __INLINE void MSS_TIM64_clear_irq(void)\r
+{\r
+    TIMER->TIM64_RIS = 1u;\r
+}\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /*MSS_TIMER_H_*/\r
diff --git a/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers/mss_uart/mss_uart.c b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers/mss_uart/mss_uart.c
new file mode 100644 (file)
index 0000000..5b00acc
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers/mss_uart/mss_uart.c
@@ -0,0 +1,1762 @@
+/*******************************************************************************\r
+ * (c) Copyright 2011-2013 Microsemi SoC Products Group.  All rights reserved.\r
+ *\r
+ * SmartFusion2 Microcontroller Subsystem MMUART bare metal software driver\r
+ * implementation.\r
+ *\r
+ * SVN $Revision: 5610 $\r
+ * SVN $Date: 2013-04-05 14:19:30 +0100 (Fri, 05 Apr 2013) $\r
+ */\r
+#include "mss_uart.h"\r
+#include "mss_uart_regs.h"\r
+#include "../../CMSIS/mss_assert.h"\r
+#include "../../CMSIS/hw_reg_io.h"\r
+#include "../../CMSIS/system_m2sxxx.h"\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/*******************************************************************************\r
+ * Defines\r
+ */\r
+#define TX_COMPLETE            0u\r
+#define TX_FIFO_SIZE           16u\r
+\r
+#define FCR_TRIG_LEVEL_MASK    0xC0u\r
+\r
+#define IIRF_MASK              0x0Fu\r
+\r
+#define INVALID_INTERRUPT      0u\r
+#define INVALID_IRQ_HANDLER    ((mss_uart_irq_handler_t) 0)\r
+#define NULL_HANDLER           ((mss_uart_irq_handler_t) 0)\r
+\r
+#define MSS_UART_DATA_READY    ((uint8_t) 0x01)\r
+\r
+#define SYNC_ASYNC_MODE_MASK   (0x7u)\r
+\r
+/*******************************************************************************\r
+ * Possible values for Interrupt Identification Register Field.\r
+ */\r
+#define IIRF_MODEM_STATUS   0x00u\r
+#define IIRF_THRE           0x02u\r
+#define IIRF_MMI            0x03u\r
+#define IIRF_RX_DATA        0x04u\r
+#define IIRF_RX_LINE_STATUS 0x06u\r
+#define IIRF_DATA_TIMEOUT   0x0Cu\r
+\r
+/*******************************************************************************\r
+ * Receiver error status mask.\r
+ */\r
+#define STATUS_ERROR_MASK    ( MSS_UART_OVERUN_ERROR | MSS_UART_PARITY_ERROR | \\r
+                               MSS_UART_FRAMING_ERROR  | MSS_UART_BREAK_ERROR | \\r
+                               MSS_UART_FIFO_ERROR)\r
+\r
+/*******************************************************************************\r
+ * Cortex-M3 interrupt handler functions implemented as part of the MSS UART\r
+ * driver.\r
+ */\r
+#if defined(__GNUC__)\r
+__attribute__((__interrupt__)) void UART0_IRQHandler(void);\r
+#else\r
+void UART0_IRQHandler(void);\r
+#endif\r
+\r
+#if defined(__GNUC__)\r
+__attribute__((__interrupt__)) void UART1_IRQHandler(void);\r
+#else\r
+void UART1_IRQHandler(void);\r
+#endif\r
+\r
+/*******************************************************************************\r
+ * Local functions.\r
+ */\r
+static void global_init(mss_uart_instance_t * this_uart, uint32_t baud_rate,\r
+                        uint8_t line_config);\r
+static void MSS_UART_isr(mss_uart_instance_t * this_uart);\r
+static void default_tx_handler(mss_uart_instance_t * this_uart);\r
+\r
+static void config_baud_divisors\r
+(\r
+    mss_uart_instance_t * this_uart,\r
+    uint32_t baudrate\r
+);\r
+\r
+/*******************************************************************************\r
+ * Instance definitions\r
+ */\r
+mss_uart_instance_t g_mss_uart0;\r
+mss_uart_instance_t g_mss_uart1;\r
+\r
+\r
+/*******************************************************************************\r
+ * Public Functions\r
+ *******************************************************************************/\r
+/***************************************************************************//**\r
+ * See mss_uart.h for details of how to use this function.\r
+ */\r
+void\r
+MSS_UART_init\r
+(\r
+    mss_uart_instance_t* this_uart,\r
+    uint32_t baud_rate,\r
+    uint8_t line_config\r
+)\r
+{\r
+    /* The driver expects g_mss_uart0 and g_mss_uart1 to be the only\r
+     * mss_uart_instance_t instances used to identify UART0 and UART1. */\r
+    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));\r
+\r
+    /* Perform generic initialization */\r
+    global_init(this_uart, baud_rate, line_config);\r
+\r
+    /* Disable LIN mode */\r
+    clear_bit_reg8(&this_uart->hw_reg->MM0, ELIN);\r
+\r
+    /* Disable IrDA mode */\r
+    clear_bit_reg8(&this_uart->hw_reg->MM1, EIRD);\r
+\r
+    /* Disable SmartCard Mode */\r
+    clear_bit_reg8(&this_uart->hw_reg->MM2, EERR);\r
+\r
+    /* set default tx handler for automated TX using interrupt in USART mode */\r
+    this_uart->tx_handler = default_tx_handler;\r
+}\r
+\r
+/***************************************************************************//**\r
+ * See mss_uart.h for details of how to use this function.\r
+ */\r
+void MSS_UART_lin_init\r
+(\r
+    mss_uart_instance_t* this_uart,\r
+    uint32_t baud_rate,\r
+    uint8_t line_config\r
+)\r
+{\r
+    /* The driver expects g_mss_uart0 and g_mss_uart1 to be the only\r
+     * mss_uart_instance_t instances used to identify UART0 and UART1. */\r
+    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));\r
+\r
+    /* Perform generic initialization */\r
+    global_init(this_uart, baud_rate, line_config);\r
+\r
+     /* Enable LIN mode */\r
+    set_bit_reg8(&this_uart->hw_reg->MM0, ELIN);\r
+\r
+    /* Disable IrDA mode */\r
+    clear_bit_reg8(&this_uart->hw_reg->MM1, EIRD);\r
+\r
+    /* Disable SmartCard Mode */\r
+    clear_bit_reg8(&this_uart->hw_reg->MM2, EERR);\r
+}\r
+\r
+/***************************************************************************//**\r
+ * See mss_uart.h for details of how to use this function.\r
+ */\r
+void\r
+MSS_UART_irda_init\r
+(\r
+    mss_uart_instance_t* this_uart,\r
+    uint32_t baud_rate,\r
+    uint8_t line_config,\r
+    mss_uart_rzi_polarity_t rxpol,\r
+    mss_uart_rzi_polarity_t txpol,\r
+    mss_uart_rzi_pulsewidth_t pw\r
+)\r
+{\r
+    /* The driver expects g_mss_uart0 and g_mss_uart1 to be the only\r
+     * mss_uart_instance_t instances used to identify UART0 and UART1. */\r
+    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));\r
+\r
+    /* Perform generic initialization */\r
+    global_init(this_uart, baud_rate, line_config);\r
+\r
+     /* Enable LIN mode */\r
+    clear_bit_reg8(&this_uart->hw_reg->MM0, ELIN);\r
+\r
+    /* Disable IrDA mode */\r
+    set_bit_reg8(&this_uart->hw_reg->MM1, EIRD);\r
+    ((rxpol == MSS_UART_ACTIVE_LOW) ? clear_bit_reg8(&this_uart->hw_reg->MM1,EIRX) :\r
+                                      set_bit_reg8(&this_uart->hw_reg->MM1,EIRX));\r
+\r
+    ((txpol == MSS_UART_ACTIVE_LOW) ? clear_bit_reg8(&this_uart->hw_reg->MM1,EITX) :\r
+                                      set_bit_reg8(&this_uart->hw_reg->MM1,EITX));\r
+\r
+    ((pw == MSS_UART_3_BY_16) ? clear_bit_reg8(&this_uart->hw_reg->MM1,EITP) :\r
+                                      set_bit_reg8(&this_uart->hw_reg->MM1,EITP));\r
+    /* Disable SmartCard Mode */\r
+    clear_bit_reg8(&this_uart->hw_reg->MM2, EERR);\r
+}\r
+\r
+/***************************************************************************//**\r
+ * See mss_uart.h for details of how to use this function.\r
+ */\r
+void\r
+MSS_UART_smartcard_init\r
+(\r
+    mss_uart_instance_t* this_uart,\r
+    uint32_t baud_rate,\r
+    uint8_t line_config\r
+)\r
+{\r
+    /* The driver expects g_mss_uart0 and g_mss_uart1 to be the only\r
+     * mss_uart_instance_t instances used to identify UART0 and UART1. */\r
+    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));\r
+\r
+    /* Perform generic initialization */\r
+    global_init(this_uart, baud_rate, line_config);\r
+\r
+    /* Disable LIN mode */\r
+    clear_bit_reg8(&this_uart->hw_reg->MM0, ELIN);\r
+\r
+    /* Disable IrDA mode */\r
+    clear_bit_reg8(&this_uart->hw_reg->MM1, EIRD);\r
+\r
+    /* Enable SmartCard Mode : Only when data is 8-bit and 2 stop bits*/\r
+    if( ( MSS_UART_DATA_8_BITS | MSS_UART_TWO_STOP_BITS) ==\r
+        (line_config & (MSS_UART_DATA_8_BITS | MSS_UART_TWO_STOP_BITS)))\r
+    {\r
+        set_bit_reg8(&this_uart->hw_reg->MM2, EERR);\r
+        /* Enable single wire half-duplex mode */\r
+        set_bit_reg8(&this_uart->hw_reg->MM2,ESWM);\r
+    }\r
+}\r
+\r
+/***************************************************************************//**\r
+ * See mss_uart.h for details of how to use this function.\r
+ */\r
+void\r
+MSS_UART_polled_tx\r
+(\r
+    mss_uart_instance_t * this_uart,\r
+    const uint8_t * pbuff,\r
+    uint32_t tx_size\r
+)\r
+{\r
+    uint32_t char_idx = 0u;\r
+    uint32_t size_sent;\r
+    uint8_t status;\r
+\r
+    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));\r
+    ASSERT(pbuff != ( (uint8_t *)0));\r
+    ASSERT(tx_size > 0u);\r
+\r
+    if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) &&\r
+        (pbuff != ((uint8_t *)0)) && (tx_size > 0u))\r
+    {\r
+         /* Remain in this loop until the entire input buffer\r
+          * has been transferred to the UART.\r
+          */\r
+        do {\r
+            /* Read the Line Status Register and update the sticky record */\r
+            status = this_uart->hw_reg->LSR;\r
+            this_uart->status |= status;\r
+\r
+            /* Check if TX FIFO is empty. */\r
+            if(status & MSS_UART_THRE)\r
+            {\r
+                uint32_t fill_size = TX_FIFO_SIZE;\r
+\r
+                /* Calculate the number of bytes to transmit. */\r
+                if(tx_size < TX_FIFO_SIZE)\r
+                {\r
+                    fill_size = tx_size;\r
+                }\r
+\r
+                /* Fill the TX FIFO with the calculated the number of bytes. */\r
+                for(size_sent = 0u; size_sent < fill_size; ++size_sent)\r
+                {\r
+                    /* Send next character in the buffer. */\r
+                    this_uart->hw_reg->THR = pbuff[char_idx];\r
+                    char_idx++;\r
+                }\r
+\r
+                /* Calculate the number of untransmitted bytes remaining. */\r
+                tx_size -= size_sent;\r
+            }\r
+        } while(tx_size);\r
+    }\r
+}\r
+\r
+/***************************************************************************//**\r
+ * See mss_uart.h for details of how to use this function.\r
+ */\r
+void\r
+MSS_UART_polled_tx_string\r
+(\r
+    mss_uart_instance_t * this_uart,\r
+    const uint8_t * p_sz_string\r
+)\r
+{\r
+    uint32_t char_idx = 0u;\r
+    uint32_t fill_size;\r
+    uint8_t data_byte;\r
+    uint8_t status;\r
+\r
+    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));\r
+    ASSERT(p_sz_string != ((uint8_t *)0));\r
+\r
+    if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) &&\r
+       (p_sz_string != ((uint8_t *)0)))\r
+    {\r
+        /* Get the first data byte from the input buffer */\r
+        data_byte = p_sz_string[char_idx];\r
+\r
+        /* First check for the NULL terminator byte.\r
+         * Then remain in this loop until the entire string in the input buffer\r
+         * has been transferred to the UART.\r
+         */\r
+        while(0u != data_byte)\r
+        {\r
+            /* Wait until TX FIFO is empty. */\r
+            do {\r
+                status = this_uart->hw_reg->LSR;\r
+                this_uart->status |= status;\r
+            } while (0u == (status & MSS_UART_THRE));\r
+\r
+            /* Send bytes from the input buffer until the TX FIFO is full\r
+             * or we reach the NULL terminator byte.\r
+             */\r
+            fill_size = 0u;\r
+            while((0u != data_byte) && (fill_size < TX_FIFO_SIZE))\r
+            {\r
+                /* Send the data byte */\r
+                this_uart->hw_reg->THR = data_byte;\r
+                ++fill_size;\r
+                char_idx++;\r
+                /* Get the next data byte from the input buffer */\r
+                data_byte = p_sz_string[char_idx];\r
+            }\r
+        }\r
+    }\r
+}\r
+\r
+/***************************************************************************//**\r
+ * See mss_uart.h for details of how to use this function.\r
+ */\r
+void\r
+MSS_UART_irq_tx\r
+(\r
+    mss_uart_instance_t * this_uart,\r
+    const uint8_t * pbuff,\r
+    uint32_t tx_size\r
+)\r
+{\r
+    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));\r
+    ASSERT(pbuff != ((uint8_t *)0));\r
+    ASSERT(tx_size > 0u);\r
+\r
+    if((tx_size > 0u) && ( pbuff != ((uint8_t *)0)) &&\r
+      ((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)))\r
+    {\r
+        /*Initialise the transmit info for the UART instance with the arguments.*/\r
+        this_uart->tx_buffer = pbuff;\r
+        this_uart->tx_buff_size = tx_size;\r
+        this_uart->tx_idx = (uint16_t)0;\r
+\r
+        /* Clear any previously pended interrupts */\r
+        NVIC_ClearPendingIRQ(this_uart->irqn);\r
+\r
+        /* assign default handler for data transfer */\r
+        this_uart->tx_handler = default_tx_handler;\r
+\r
+        /* enables TX interrupt */\r
+        set_bit_reg8(&this_uart->hw_reg->IER,ETBEI);\r
+\r
+        /* Enable UART instance interrupt in Cortex-M3 NVIC. */\r
+        NVIC_EnableIRQ(this_uart->irqn);\r
+    }\r
+}\r
+\r
+/***************************************************************************//**\r
+ * See mss_uart.h for details of how to use this function.\r
+ */\r
+int8_t\r
+MSS_UART_tx_complete\r
+(\r
+    mss_uart_instance_t * this_uart\r
+)\r
+{\r
+    int8_t ret_value = 0;\r
+    uint8_t status = 0u;\r
+\r
+    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));\r
+\r
+    if((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1))\r
+    {\r
+        /* Read the Line Status Register and update the sticky record. */\r
+        status = this_uart->hw_reg->LSR;\r
+        this_uart->status |= status;\r
+\r
+        if((TX_COMPLETE == this_uart->tx_buff_size) &&\r
+           ((status & MSS_UART_TEMT) != 0u))\r
+        {\r
+            ret_value = (int8_t)1;\r
+        }\r
+    }\r
+    return ret_value;\r
+}\r
+\r
+\r
+/***************************************************************************//**\r
+ * See mss_uart.h for details of how to use this function.\r
+ */\r
+size_t\r
+MSS_UART_get_rx\r
+(\r
+    mss_uart_instance_t * this_uart,\r
+    uint8_t * rx_buff,\r
+    size_t buff_size\r
+)\r
+{\r
+    size_t rx_size = 0u;\r
+    uint8_t status = 0u;\r
+\r
+    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));\r
+    ASSERT(rx_buff != ((uint8_t *)0));\r
+    ASSERT(buff_size > 0u);\r
+\r
+    if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) &&\r
+       (rx_buff != ((uint8_t *)0)) && (buff_size > 0u))\r
+    {\r
+        status = this_uart->hw_reg->LSR;\r
+        this_uart->status |= status;\r
+\r
+        while(((status & MSS_UART_DATA_READY) != 0u) &&\r
+              (rx_size < buff_size))\r
+        {\r
+            rx_buff[rx_size] = this_uart->hw_reg->RBR;\r
+            ++rx_size;\r
+            status = this_uart->hw_reg->LSR;\r
+            this_uart->status |= status;\r
+        }\r
+    }\r
+    return rx_size;\r
+}\r
+/***************************************************************************//**\r
+ * See mss_uart.h for details of how to use this function.\r
+ */\r
+void\r
+MSS_UART_enable_irq\r
+(\r
+    mss_uart_instance_t * this_uart,\r
+    mss_uart_irq_t irq_mask\r
+)\r
+{\r
+    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));\r
+    ASSERT(MSS_UART_INVALID_IRQ > irq_mask);\r
+\r
+    if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) &&\r
+       (MSS_UART_INVALID_IRQ > irq_mask))\r
+    {\r
+        /* Clear any previously pended interrupts */\r
+        NVIC_ClearPendingIRQ(this_uart->irqn);\r
+\r
+        /* irq_mask encoding: 1- enable\r
+         * bit 0 - Receive Data Available Interrupt\r
+         * bit 1 - Transmitter Holding  Register Empty Interrupt\r
+         * bit 2 - Receiver Line Status Interrupt\r
+         * bit 3 - Modem Status Interrupt\r
+         */\r
+        this_uart->hw_reg->IER |= (uint8_t)irq_mask & IIRF_MASK;\r
+\r
+        /*\r
+         * bit 4 - Receiver time-out interrupt\r
+         * bit 5 - NACK / ERR signal interrupt\r
+         * bit 6 - PID parity error interrupt\r
+         * bit 7 - LIN break detection interrupt\r
+         * bit 8 - LIN Sync detection interrupt\r
+         */\r
+        this_uart->hw_reg->IEM |= (uint8_t)(((uint32_t)irq_mask & ~((uint32_t)IIRF_MASK)) >> 4u);\r
+\r
+        /* Enable UART instance interrupt in Cortex-M3 NVIC. */\r
+        NVIC_EnableIRQ(this_uart->irqn);\r
+    }\r
+}\r
+\r
+/***************************************************************************//**\r
+ * See mss_uart.h for details of how to use this function.\r
+ */\r
+void\r
+MSS_UART_disable_irq\r
+(\r
+    mss_uart_instance_t * this_uart,\r
+    mss_uart_irq_t irq_mask\r
+)\r
+{\r
+    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));\r
+\r
+    if((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1))\r
+    {\r
+        /* irq_mask encoding: 1 - disable\r
+         * bit 0 - Receive Data Available Interrupt\r
+         * bit 1 - Transmitter Holding  Register Empty Interrupt\r
+         * bit 2 - Receiver Line Status Interrupt\r
+         * bit 3 - Modem Status Interrupt\r
+         */\r
+        this_uart->hw_reg->IER &= ((uint8_t)(~((uint32_t)irq_mask & (uint32_t)IIRF_MASK)));\r
+\r
+        /*\r
+         * bit 4 - Receiver time-out interrupt\r
+         * bit 5 - NACK / ERR signal interrupt\r
+         * bit 6 - PID parity error interrupt\r
+         * bit 7 - LIN break detection interrupt\r
+         * bit 8 - LIN Sync detection interrupt\r
+         */\r
+        this_uart->hw_reg->IEM |= (uint8_t)(~(((uint32_t)irq_mask & ~((uint32_t)IIRF_MASK)) >> 8u));\r
+\r
+        /* Clear any previously pended interrupts */\r
+        NVIC_ClearPendingIRQ(this_uart->irqn);\r
+\r
+        if(irq_mask == IIRF_MASK)\r
+        {\r
+            /* Disable UART instance interrupt in Cortex-M3 NVIC. */\r
+            NVIC_DisableIRQ(this_uart->irqn);\r
+\r
+        }\r
+    }\r
+}\r
+\r
+/***************************************************************************//**\r
+ * See mss_uart.h for details of how to use this function.\r
+ */\r
+void\r
+MSS_UART_set_rx_handler\r
+(\r
+    mss_uart_instance_t *       this_uart,\r
+    mss_uart_irq_handler_t      handler,\r
+    mss_uart_rx_trig_level_t    trigger_level\r
+)\r
+{\r
+    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));\r
+    ASSERT(handler != INVALID_IRQ_HANDLER );\r
+    ASSERT(trigger_level < MSS_UART_FIFO_INVALID_TRIG_LEVEL);\r
+\r
+    if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) &&\r
+       (handler != INVALID_IRQ_HANDLER) &&\r
+       (trigger_level < MSS_UART_FIFO_INVALID_TRIG_LEVEL))\r
+    {\r
+        this_uart->rx_handler = handler;\r
+\r
+        /* Set the receive interrupt trigger level. */\r
+        this_uart->hw_reg->FCR = (this_uart->hw_reg->FCR &\r
+                                 (uint8_t)(~((uint8_t)FCR_TRIG_LEVEL_MASK))) |\r
+                                 (uint8_t)trigger_level;\r
+        /* Clear any previously pended interrupts */\r
+        NVIC_ClearPendingIRQ(this_uart->irqn);\r
+\r
+        /* Enable receive interrupt. */\r
+        set_bit_reg8(&this_uart->hw_reg->IER,ERBFI);\r
+\r
+        /* Enable UART instance interrupt in Cortex-M3 NVIC. */\r
+        NVIC_EnableIRQ(this_uart->irqn);\r
+    }\r
+}\r
+\r
+/***************************************************************************//**\r
+ * See mss_uart.h for details of how to use this function.\r
+ */\r
+void\r
+MSS_UART_set_loopback\r
+(\r
+    mss_uart_instance_t *   this_uart,\r
+    mss_uart_loopback_t     loopback\r
+)\r
+{\r
+    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));\r
+    ASSERT(MSS_UART_INVALID_LOOPBACK > loopback);\r
+\r
+    if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) ||\r
+       (MSS_UART_INVALID_LOOPBACK > loopback))\r
+    {\r
+        switch(loopback)\r
+        {\r
+            case MSS_UART_LOCAL_LOOPBACK_OFF:\r
+                /* Disable local loopback */\r
+                clear_bit_reg8(&this_uart->hw_reg->MCR,LOOP);\r
+                break;\r
+\r
+            case MSS_UART_LOCAL_LOOPBACK_ON:\r
+                /* Enable local loopback */\r
+                set_bit_reg8(&this_uart->hw_reg->MCR,LOOP);\r
+                break;\r
+\r
+            case MSS_UART_REMOTE_LOOPBACK_OFF:\r
+            case MSS_UART_AUTO_ECHO_OFF:\r
+                /* Disable remote loopback & automatic echo*/\r
+                this_uart->hw_reg->MCR &= ~RLOOP_MASK;\r
+                break;\r
+\r
+            case MSS_UART_REMOTE_LOOPBACK_ON:\r
+                /* Enable remote loopback */\r
+                this_uart->hw_reg->MCR |= (1u << RLOOP);\r
+                break;\r
+\r
+            case MSS_UART_AUTO_ECHO_ON:\r
+                /* Enable automatic echo */\r
+                this_uart->hw_reg->MCR |= (1u << ECHO);\r
+                break;\r
+\r
+            case MSS_UART_INVALID_LOOPBACK:\r
+                /* Fall through to default. */\r
+            default:\r
+                ASSERT(0);\r
+                break;\r
+        }\r
+    }\r
+}\r
+\r
+/***************************************************************************//**\r
+ * UART0 interrupt service routine.\r
+ * UART0_IRQHandler is included within the Cortex-M3 vector table as part of the\r
+ * Fusion 2 CMSIS.\r
+ */\r
+#if defined(__GNUC__)\r
+__attribute__((__interrupt__)) void UART0_IRQHandler(void)\r
+#else\r
+void UART0_IRQHandler(void)\r
+#endif\r
+{\r
+    MSS_UART_isr(&g_mss_uart0);\r
+}\r
+\r
+/***************************************************************************//**\r
+ * UART1 interrupt service routine.\r
+ * UART2_IRQHandler is included within the Cortex-M3 vector table as part of the\r
+ * Fusion 2 CMSIS.\r
+ */\r
+#if defined(__GNUC__)\r
+__attribute__((__interrupt__)) void UART1_IRQHandler(void)\r
+#else\r
+void UART1_IRQHandler(void)\r
+#endif\r
+{\r
+    MSS_UART_isr(&g_mss_uart1);\r
+}\r
+\r
+/***************************************************************************//**\r
+ * See mss_uart.h for details of how to use this function.\r
+ */\r
+void\r
+MSS_UART_set_rxstatus_handler\r
+(\r
+    mss_uart_instance_t * this_uart,\r
+    mss_uart_irq_handler_t handler\r
+)\r
+{\r
+    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));\r
+    ASSERT(handler != INVALID_IRQ_HANDLER);\r
+\r
+    if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) &&\r
+       (handler != INVALID_IRQ_HANDLER))\r
+    {\r
+        this_uart->linests_handler = handler;\r
+\r
+        /* Clear any previously pended interrupts */\r
+        NVIC_ClearPendingIRQ(this_uart->irqn);\r
+\r
+        /* Enable receiver line status interrupt. */\r
+        set_bit_reg8(&this_uart->hw_reg->IER,ELSI);\r
+\r
+        /* Enable UART instance interrupt in Cortex-M3 NVIC. */\r
+        NVIC_EnableIRQ(this_uart->irqn);\r
+    }\r
+}\r
+\r
+/***************************************************************************//**\r
+ * See mss_uart.h for details of how to use this function.\r
+ */\r
+void\r
+MSS_UART_set_tx_handler\r
+(\r
+    mss_uart_instance_t * this_uart,\r
+    mss_uart_irq_handler_t handler\r
+)\r
+{\r
+    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));\r
+    ASSERT(handler != INVALID_IRQ_HANDLER);\r
+\r
+    if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) &&\r
+       (handler != INVALID_IRQ_HANDLER))\r
+    {\r
+        this_uart->tx_handler = handler;\r
+\r
+        /* Make TX buffer info invalid */\r
+        this_uart->tx_buffer = (const uint8_t *)0;\r
+        this_uart->tx_buff_size = 0u;\r
+\r
+        /* Clear any previously pended interrupts */\r
+        NVIC_ClearPendingIRQ(this_uart->irqn);\r
+\r
+        /* Enable transmitter holding register Empty interrupt. */\r
+        set_bit_reg8(&this_uart->hw_reg->IER,ETBEI);\r
+\r
+        /* Enable UART instance interrupt in Cortex-M3 NVIC. */\r
+        NVIC_EnableIRQ(this_uart->irqn);\r
+    }\r
+}\r
+\r
+/***************************************************************************//**\r
+ * See mss_uart.h for details of how to use this function.\r
+ */\r
+void\r
+MSS_UART_set_modemstatus_handler\r
+(\r
+    mss_uart_instance_t * this_uart,\r
+    mss_uart_irq_handler_t handler\r
+)\r
+{\r
+    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));\r
+    ASSERT(handler != INVALID_IRQ_HANDLER);\r
+\r
+    if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) &&\r
+       (handler != INVALID_IRQ_HANDLER))\r
+    {\r
+        this_uart->modemsts_handler = handler;\r
+\r
+        /* Clear any previously pended interrupts */\r
+        NVIC_ClearPendingIRQ(this_uart->irqn);\r
+\r
+        /* Enable modem status interrupt. */\r
+        set_bit_reg8(&this_uart->hw_reg->IER,EDSSI);\r
+\r
+        /* Enable UART instance interrupt in Cortex-M3 NVIC. */\r
+        NVIC_EnableIRQ(this_uart->irqn);\r
+    }\r
+}\r
+\r
+/***************************************************************************//**\r
+ * See mss_uart.h for details of how to use this function.\r
+ */\r
+size_t\r
+MSS_UART_fill_tx_fifo\r
+(\r
+    mss_uart_instance_t * this_uart,\r
+    const uint8_t * tx_buffer,\r
+    size_t tx_size\r
+)\r
+{\r
+    uint8_t status = 0u;\r
+    size_t size_sent = 0u;\r
+\r
+    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));\r
+    ASSERT(tx_buffer != ( (uint8_t *)0));\r
+    ASSERT(tx_size > 0);\r
+\r
+    /* Fill the UART's Tx FIFO until the FIFO is full or the complete input\r
+     * buffer has been written. */\r
+    if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) &&\r
+       (tx_buffer != ((uint8_t *)0))   &&\r
+       (tx_size > 0u))\r
+    {\r
+        status = this_uart->hw_reg->LSR;\r
+        this_uart->status |= status;\r
+\r
+        if(status & MSS_UART_THRE)\r
+        {\r
+            uint32_t fill_size = TX_FIFO_SIZE;\r
+\r
+            if(tx_size < TX_FIFO_SIZE)\r
+            {\r
+                fill_size = tx_size;\r
+            }\r
+            /* Fill up FIFO */\r
+            for(size_sent = 0u; size_sent < fill_size; ++size_sent)\r
+            {\r
+\r
+                /* Send next character in the buffer. */\r
+                this_uart->hw_reg->THR = tx_buffer[size_sent];\r
+            }\r
+        }\r
+    }\r
+    return size_sent;\r
+}\r
+\r
+/***************************************************************************//**\r
+ * See mss_uart.h for details of how to use this function.\r
+ */\r
+uint8_t\r
+MSS_UART_get_rx_status\r
+(\r
+    mss_uart_instance_t * this_uart\r
+)\r
+{\r
+    uint8_t status = MSS_UART_INVALID_PARAM;\r
+\r
+    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));\r
+\r
+    if((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1))\r
+    {\r
+        /*\r
+         * Extract UART receive error status.\r
+         * Bit 1 - Overflow error status\r
+         * Bit 2 - Parity error status\r
+         * Bit 3 - Frame error status\r
+         * Bit 4 - Break interrupt indicator\r
+         * Bit 7 - FIFO data error status\r
+         */\r
+        this_uart->status |= (this_uart->hw_reg->LSR);\r
+        status = (this_uart->status & STATUS_ERROR_MASK);\r
+        /* Clear the sticky status after reading */\r
+        this_uart->status = 0u;\r
+    }\r
+    return status;\r
+}\r
+\r
+/***************************************************************************//**\r
+ * See mss_uart.h for details of how to use this function.\r
+ */\r
+uint8_t\r
+MSS_UART_get_modem_status\r
+(\r
+    mss_uart_instance_t * this_uart\r
+)\r
+{\r
+    uint8_t status = MSS_UART_INVALID_PARAM;\r
+\r
+    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));\r
+\r
+    if((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1))\r
+    {\r
+        /*\r
+         * Extract UART modem status and place in lower bits of "status".\r
+         * Bit 0 - Delta Clear to Send Indicator\r
+         * Bit 1 - Delta Clear to Receive Indicator\r
+         * Bit 2 - Trailing edge of Ring Indicator detector\r
+         * Bit 3 - Delta Data Carrier Detect indicator\r
+         * Bit 4 - Clear To Send\r
+         * Bit 5 - Data Set Ready\r
+         * Bit 6 - Ring Indicator\r
+         * Bit 7 - Data Carrier Detect\r
+         */\r
+        status = this_uart->hw_reg->MSR;\r
+    }\r
+    return status;\r
+}\r
+\r
+/***************************************************************************//**\r
+ * MSS_UART_get_tx_status.\r
+ * See mss_uart.h for details of how to use this function.\r
+ */\r
+uint8_t\r
+MSS_UART_get_tx_status\r
+(\r
+    mss_uart_instance_t * this_uart\r
+)\r
+{\r
+    uint8_t status = MSS_UART_TX_BUSY;\r
+\r
+    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));\r
+\r
+    if((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1))\r
+    {\r
+        /* Read the Line Status Register and update the sticky record. */\r
+        status = this_uart->hw_reg->LSR;\r
+        this_uart->status |= status;\r
+        /*\r
+         * Extract the transmit status bits from the UART's Line Status Register.\r
+         * Bit 5 - Transmitter Holding Register/FIFO Empty (THRE) status. (If = 1, TX FIFO is empty)\r
+         * Bit 6 - Transmitter Empty (TEMT) status. (If = 1, both TX FIFO and shift register are empty)\r
+         */\r
+        status &= (MSS_UART_THRE | MSS_UART_TEMT);\r
+    }\r
+    return status;\r
+}\r
+\r
+/***************************************************************************//**\r
+ * See mss_uart.h for details of how to use this function.\r
+ */\r
+void\r
+MSS_UART_set_break\r
+(\r
+    mss_uart_instance_t * this_uart\r
+)\r
+{\r
+    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));\r
+    if((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1))\r
+    {\r
+        /* set break charecter on Tx line */\r
+        set_bit_reg8(&this_uart->hw_reg->LCR,SB);\r
+    }\r
+}\r
+\r
+/***************************************************************************//**\r
+ * See mss_uart.h for details of how to use this function.\r
+ */\r
+void\r
+MSS_UART_clear_break\r
+(\r
+    mss_uart_instance_t * this_uart\r
+)\r
+{\r
+    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));\r
+    if((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1))\r
+    {\r
+        /* remove break charecter from Tx line */\r
+        clear_bit_reg8(&this_uart->hw_reg->LCR,SB);\r
+    }\r
+}\r
+\r
+/***************************************************************************//**\r
+ * See mss_uart.h for details of how to use this function.\r
+ */\r
+void\r
+MSS_UART_set_pidpei_handler\r
+(\r
+    mss_uart_instance_t * this_uart,\r
+    mss_uart_irq_handler_t handler\r
+)\r
+{\r
+    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));\r
+    ASSERT(handler != INVALID_IRQ_HANDLER);\r
+\r
+    if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) &&\r
+       (handler != INVALID_IRQ_HANDLER))\r
+    {\r
+        this_uart->pid_pei_handler = handler;\r
+\r
+        /* Clear any previously pended interrupts */\r
+        NVIC_ClearPendingIRQ( this_uart->irqn );\r
+\r
+        /* Enable PID parity error interrupt. */\r
+        set_bit_reg8(&this_uart->hw_reg->IEM,EPID_PEI);\r
+\r
+        /* Enable UART instance interrupt in Cortex-M3 NVIC. */\r
+        NVIC_EnableIRQ(this_uart->irqn);\r
+    }\r
+}\r
+\r
+/***************************************************************************//**\r
+ * See mss_uart.h for details of how to use this function.\r
+ */\r
+void\r
+MSS_UART_set_linbreak_handler\r
+(\r
+    mss_uart_instance_t * this_uart,\r
+    mss_uart_irq_handler_t handler\r
+)\r
+{\r
+    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));\r
+    ASSERT(handler != INVALID_IRQ_HANDLER);\r
+\r
+    if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) &&\r
+       (handler != INVALID_IRQ_HANDLER))\r
+    {\r
+        this_uart->break_handler = handler;\r
+\r
+        /* Clear any previously pended interrupts */\r
+        NVIC_ClearPendingIRQ( this_uart->irqn );\r
+\r
+        /* Enable LIN break detection interrupt. */\r
+        set_bit_reg8(&this_uart->hw_reg->IEM,ELINBI);\r
+\r
+        /* Enable UART instance interrupt in Cortex-M3 NVIC. */\r
+        NVIC_EnableIRQ(this_uart->irqn);\r
+    }\r
+}\r
+\r
+/***************************************************************************//**\r
+ * See mss_uart.h for details of how to use this function.\r
+ */\r
+void\r
+MSS_UART_set_linsync_handler\r
+(\r
+    mss_uart_instance_t * this_uart,\r
+    mss_uart_irq_handler_t handler\r
+)\r
+{\r
+    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));\r
+    ASSERT(handler != INVALID_IRQ_HANDLER);\r
+\r
+    if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) &&\r
+       (handler != INVALID_IRQ_HANDLER))\r
+    {\r
+        this_uart->sync_handler = handler;\r
+\r
+        /* Clear any previously pended interrupts */\r
+        NVIC_ClearPendingIRQ( this_uart->irqn );\r
+\r
+        /* Enable LIN sync detection interrupt. */\r
+        set_bit_reg8(&this_uart->hw_reg->IEM,ELINSI);\r
+\r
+        /* Enable UART instance interrupt in Cortex-M3 NVIC. */\r
+        NVIC_EnableIRQ(this_uart->irqn);\r
+    }\r
+}\r
+\r
+/***************************************************************************//**\r
+ * See mss_uart.h for details of how to use this function.\r
+ */\r
+void\r
+MSS_UART_set_nack_handler\r
+(\r
+    mss_uart_instance_t * this_uart,\r
+    mss_uart_irq_handler_t handler\r
+)\r
+{\r
+    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));\r
+    ASSERT(handler != INVALID_IRQ_HANDLER);\r
+\r
+    if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) &&\r
+       (handler != INVALID_IRQ_HANDLER))\r
+    {\r
+        this_uart->nack_handler = handler;\r
+\r
+        /* Clear any previously pended interrupts */\r
+        NVIC_ClearPendingIRQ( this_uart->irqn );\r
+\r
+        /* Enable LIN sync detection interrupt. */\r
+        set_bit_reg8(&this_uart->hw_reg->IEM,ENACKI);\r
+\r
+        /* Enable UART instance interrupt in Cortex-M3 NVIC. */\r
+        NVIC_EnableIRQ(this_uart->irqn);\r
+    }\r
+}\r
+\r
+/***************************************************************************//**\r
+ * See mss_uart.h for details of how to use this function.\r
+ */\r
+void\r
+MSS_UART_set_rx_timeout_handler\r
+(\r
+    mss_uart_instance_t * this_uart,\r
+    mss_uart_irq_handler_t handler\r
+)\r
+{\r
+    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));\r
+    ASSERT(handler != INVALID_IRQ_HANDLER);\r
+\r
+    if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) &&\r
+       (handler != INVALID_IRQ_HANDLER))\r
+    {\r
+        this_uart->rto_handler = handler;\r
+\r
+        /* Clear any previously pended interrupts */\r
+        NVIC_ClearPendingIRQ( this_uart->irqn );\r
+\r
+        /* Enable receiver timeout interrupt. */\r
+        set_bit_reg8(&this_uart->hw_reg->IEM,ERTOI);\r
+\r
+        /* Enable UART instance interrupt in Cortex-M3 NVIC. */\r
+        NVIC_EnableIRQ(this_uart->irqn);\r
+    }\r
+}\r
+\r
+/***************************************************************************//**\r
+ * See mss_uart.h for details of how to use this function.\r
+ */\r
+void\r
+MSS_UART_enable_half_duplex\r
+(\r
+    mss_uart_instance_t * this_uart\r
+)\r
+{\r
+    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));\r
+    if((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1))\r
+    {\r
+        /* enable single wire half-duplex mode */\r
+        set_bit_reg8(&this_uart->hw_reg->MM2,ESWM);\r
+    }\r
+}\r
+\r
+/***************************************************************************//**\r
+ * See mss_uart.h for details of how to use this function.\r
+ */\r
+void\r
+MSS_UART_disable_half_duplex\r
+(\r
+    mss_uart_instance_t * this_uart\r
+)\r
+{\r
+    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));\r
+    if((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1))\r
+    {\r
+        /* enable single wire half-duplex mode */\r
+        clear_bit_reg8(&this_uart->hw_reg->MM2,ESWM);\r
+    }\r
+}\r
+\r
+/***************************************************************************//**\r
+ * See mss_uart.h for details of how to use this function.\r
+ */\r
+void\r
+MSS_UART_set_rx_endian\r
+(\r
+    mss_uart_instance_t * this_uart,\r
+    mss_uart_endian_t endian\r
+)\r
+{\r
+    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));\r
+    ASSERT(MSS_UART_INVALID_ENDIAN > endian);\r
+\r
+    if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) &&\r
+       (MSS_UART_INVALID_ENDIAN > endian))\r
+    {\r
+        /* Configure MSB first / LSB first for receiver */\r
+        ((MSS_UART_LITTLEEND == endian) ? (clear_bit_reg8(&this_uart->hw_reg->MM1,E_MSB_RX)) :\r
+                                          (set_bit_reg8(&this_uart->hw_reg->MM1,E_MSB_RX)));\r
+    }\r
+}\r
+\r
+/***************************************************************************//**\r
+ * See mss_uart.h for details of how to use this function.\r
+ */\r
+void\r
+MSS_UART_set_tx_endian\r
+(\r
+    mss_uart_instance_t * this_uart,\r
+    mss_uart_endian_t endian\r
+)\r
+{\r
+    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));\r
+    ASSERT(MSS_UART_INVALID_ENDIAN > endian);\r
+\r
+    if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) &&\r
+       (MSS_UART_INVALID_ENDIAN > endian))\r
+    {\r
+        /* Configure MSB first / LSB first for transmitter */\r
+        ((MSS_UART_LITTLEEND == endian) ? (clear_bit_reg8(&this_uart->hw_reg->MM1,E_MSB_TX)) :\r
+                                          (set_bit_reg8(&this_uart->hw_reg->MM1,E_MSB_TX)) ) ;\r
+    }\r
+}\r
+\r
+/***************************************************************************//**\r
+ * See mss_uart.h for details of how to use this function.\r
+ */\r
+void\r
+MSS_UART_set_filter_length\r
+(\r
+    mss_uart_instance_t * this_uart,\r
+    mss_uart_filter_length_t length\r
+)\r
+{\r
+    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));\r
+    ASSERT(MSS_UART_INVALID_FILTER_LENGTH > length);\r
+\r
+    if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) &&\r
+       (MSS_UART_INVALID_FILTER_LENGTH > length))\r
+    {\r
+        /* Configure glitch filter length */\r
+        this_uart->hw_reg->GFR = (uint8_t)length;\r
+    }\r
+}\r
+\r
+/***************************************************************************//**\r
+ * See mss_uart.h for details of how to use this function.\r
+ */\r
+void\r
+MSS_UART_enable_afm\r
+(\r
+     mss_uart_instance_t * this_uart\r
+)\r
+{\r
+    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));\r
+\r
+    if((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1))\r
+    {\r
+        /* Disable RX FIFO till address flag with correct address is received */\r
+        set_bit_reg8(&this_uart->hw_reg->MM2,EAFM);\r
+    }\r
+}\r
+\r
+/***************************************************************************//**\r
+ * See mss_uart.h for details of how to use this function.\r
+ */\r
+void\r
+MSS_UART_disable_afm\r
+(\r
+     mss_uart_instance_t * this_uart\r
+)\r
+{\r
+    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));\r
+\r
+    if((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1))\r
+    {\r
+        /* Enable RX FIFO irrespective of address flag and\r
+           correct address is received */\r
+        clear_bit_reg8(&this_uart->hw_reg->MM2,EAFM);\r
+    }\r
+}\r
+\r
+/***************************************************************************//**\r
+ * See mss_uart.h for details of how to use this function.\r
+ */\r
+void\r
+MSS_UART_enable_afclear\r
+(\r
+     mss_uart_instance_t * this_uart\r
+)\r
+{\r
+    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));\r
+\r
+    if((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1))\r
+    {\r
+        /* Enable address flag clearing */\r
+        /* Disable RX FIFO till another address flag with\r
+           correct address is received */\r
+        set_bit_reg8(&this_uart->hw_reg->MM2,EAFC);\r
+    }\r
+}\r
+\r
+/***************************************************************************//**\r
+ * See mss_uart.h for details of how to use this function.\r
+ */\r
+void\r
+MSS_UART_disable_afclear\r
+(\r
+     mss_uart_instance_t * this_uart\r
+)\r
+{\r
+    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));\r
+\r
+    if((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1))\r
+    {\r
+        /* Disable address flag clearing */\r
+        clear_bit_reg8(&this_uart->hw_reg->MM2,EAFC);\r
+    }\r
+}\r
+\r
+/***************************************************************************//**\r
+ * See mss_uart.h for details of how to use this function.\r
+ */\r
+void\r
+MSS_UART_enable_rx_timeout\r
+(\r
+    mss_uart_instance_t * this_uart,\r
+    uint8_t timeout\r
+)\r
+{\r
+    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));\r
+\r
+    if((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1))\r
+    {\r
+        /* Load the receive timeout value */\r
+        this_uart->hw_reg->RTO = timeout;\r
+        /*Enable receiver time-out */\r
+        set_bit_reg8(&this_uart->hw_reg->MM0,ERTO);\r
+    }\r
+}\r
+\r
+/***************************************************************************//**\r
+ * See mss_uart.h for details of how to use this function.\r
+ */\r
+void\r
+MSS_UART_disable_rx_timeout\r
+(\r
+    mss_uart_instance_t * this_uart\r
+)\r
+{\r
+    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));\r
+\r
+    if((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1))\r
+    {\r
+        /*Disable receiver time-out */\r
+        clear_bit_reg8(&this_uart->hw_reg->MM0,ERTO);\r
+    }\r
+}\r
+\r
+/***************************************************************************//**\r
+ * See mss_uart.h for details of how to use this function.\r
+ */\r
+void\r
+MSS_UART_enable_tx_time_guard\r
+(\r
+    mss_uart_instance_t * this_uart,\r
+    uint8_t timeguard\r
+)\r
+{\r
+    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));\r
+\r
+    if((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1))\r
+    {\r
+        /* Load the transmitter time guard value */\r
+        this_uart->hw_reg->TTG = timeguard;\r
+        /*Enable transmitter time guard */\r
+        set_bit_reg8(&this_uart->hw_reg->MM0,ETTG);\r
+    }\r
+}\r
+\r
+/***************************************************************************//**\r
+ * See mss_uart.h for details of how to use this function.\r
+ */\r
+void\r
+MSS_UART_disable_tx_time_guard\r
+(\r
+    mss_uart_instance_t * this_uart\r
+)\r
+{\r
+    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));\r
+\r
+    if((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1))\r
+    {\r
+        /*Disable transmitter time guard */\r
+        clear_bit_reg8(&this_uart->hw_reg->MM0,ETTG);\r
+    }\r
+}\r
+\r
+/***************************************************************************//**\r
+ * See mss_uart.h for details of how to use this function.\r
+ */\r
+void\r
+MSS_UART_set_address\r
+(\r
+    mss_uart_instance_t * this_uart,\r
+    uint8_t address\r
+)\r
+{\r
+    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));\r
+\r
+    if((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1))\r
+    {\r
+        this_uart->hw_reg->ADR = address;\r
+    }\r
+}\r
+\r
+/***************************************************************************//**\r
+ * See mss_uart.h for details of how to use this function.\r
+ */\r
+void\r
+MSS_UART_set_ready_mode\r
+(\r
+    mss_uart_instance_t * this_uart,\r
+    mss_uart_ready_mode_t mode\r
+)\r
+{\r
+    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));\r
+    ASSERT(MSS_UART_INVALID_READY_MODE > mode);\r
+\r
+    if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) &&\r
+       (MSS_UART_INVALID_READY_MODE > mode ) )\r
+    {\r
+        /* Configure mode 0 or mode 1 for TXRDY and RXRDY */\r
+        ((MSS_UART_READY_MODE0 == mode) ? clear_bit_reg8(&this_uart->hw_reg->FCR,RDYMODE) :\r
+                                 set_bit_reg8(&this_uart->hw_reg->FCR,RDYMODE) );\r
+    }\r
+}\r
+\r
+/***************************************************************************//**\r
+ * Configure baud divisors using fractional baud rate if possible.\r
+ */\r
+static void\r
+config_baud_divisors\r
+(\r
+    mss_uart_instance_t * this_uart,\r
+    uint32_t baudrate\r
+)\r
+{\r
+    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));\r
+\r
+    if((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1))\r
+    {\r
+        uint32_t baud_value;\r
+        uint32_t baud_value_by_64;\r
+        uint32_t baud_value_by_128;\r
+        uint32_t fractional_baud_value;\r
+        uint32_t pclk_freq;\r
+\r
+        this_uart->baudrate = baudrate;\r
+\r
+        /* Force the value of the CMSIS global variables holding the various system\r
+          * clock frequencies to be updated. */\r
+        SystemCoreClockUpdate();\r
+        if(this_uart == &g_mss_uart0)\r
+        {\r
+            pclk_freq = g_FrequencyPCLK0;\r
+        }\r
+        else\r
+        {\r
+            pclk_freq = g_FrequencyPCLK1;\r
+        }\r
+\r
+        /*\r
+         * Compute baud value based on requested baud rate and PCLK frequency.\r
+         * The baud value is computed using the following equation:\r
+         *      baud_value = PCLK_Frequency / (baud_rate * 16)\r
+         */\r
+        baud_value_by_128 = (8u * pclk_freq) / baudrate;\r
+        baud_value_by_64 = baud_value_by_128 / 2u;\r
+        baud_value = baud_value_by_64 / 64u;\r
+        fractional_baud_value = baud_value_by_64 - (baud_value * 64u);\r
+        fractional_baud_value += (baud_value_by_128 - (baud_value * 128u)) - (fractional_baud_value * 2u);\r
+\r
+        /* Assert if integer baud value fits in 16-bit. */\r
+        ASSERT(baud_value <= UINT16_MAX);\r
+\r
+        if(baud_value <= (uint32_t)UINT16_MAX)\r
+        {\r
+            if(baud_value > 1u)\r
+            {\r
+                /*\r
+                 * Use Frational baud rate divisors\r
+                 */\r
+                /* set divisor latch */\r
+                set_bit_reg8(&this_uart->hw_reg->LCR,DLAB);\r
+\r
+                /* msb of baud value */\r
+                this_uart->hw_reg->DMR = (uint8_t)(baud_value >> 8);\r
+                /* lsb of baud value */\r
+                this_uart->hw_reg->DLR = (uint8_t)baud_value;\r
+\r
+                /* reset divisor latch */\r
+                clear_bit_reg8(&this_uart->hw_reg->LCR,DLAB);\r
+\r
+                /* Enable Fractional baud rate */\r
+                set_bit_reg8(&this_uart->hw_reg->MM0,EFBR);\r
+\r
+                /* Load the fractional baud rate register */\r
+                ASSERT(fractional_baud_value <= (uint32_t)UINT8_MAX);\r
+                this_uart->hw_reg->DFR = (uint8_t)fractional_baud_value;\r
+            }\r
+            else\r
+            {\r
+                /*\r
+                 * Do NOT use Frational baud rate divisors.\r
+                 */\r
+                /* set divisor latch */\r
+                set_bit_reg8(&this_uart->hw_reg->LCR,DLAB);\r
+\r
+                /* msb of baud value */\r
+                this_uart->hw_reg->DMR = (uint8_t)(baud_value >> 8u);\r
+                /* lsb of baud value */\r
+                this_uart->hw_reg->DLR = (uint8_t)baud_value;\r
+\r
+                /* reset divisor latch */\r
+                clear_bit_reg8(&this_uart->hw_reg->LCR,DLAB);\r
+\r
+                /* Disable Fractional baud rate */\r
+                clear_bit_reg8(&this_uart->hw_reg->MM0,EFBR);\r
+            }\r
+        }\r
+    }\r
+}\r
+\r
+/***************************************************************************//**\r
+ * See mss_uart.h for details of how to use this function.\r
+ */\r
+void\r
+MSS_UART_set_usart_mode\r
+(\r
+    mss_uart_instance_t * this_uart,\r
+    mss_uart_usart_mode_t mode\r
+)\r
+{\r
+    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));\r
+    ASSERT(MSS_UART_INVALID_SYNC_MODE > mode);\r
+\r
+    if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) &&\r
+       (MSS_UART_INVALID_SYNC_MODE > mode))\r
+    {\r
+        /* Nothing to do for the baudrate: operates at PCLK / 2 + glitch filter length */\r
+        /* Clear the ESYN bits 2:0 */\r
+        this_uart->hw_reg->MM0 &= ~SYNC_ASYNC_MODE_MASK;\r
+        this_uart->hw_reg->MM0 |= (uint8_t)mode;\r
+    }\r
+}\r
+\r
+/*******************************************************************************\r
+ * Local Functions\r
+ *******************************************************************************/\r
+/*******************************************************************************\r
+ * Global initialization for all modes\r
+ */\r
+static void global_init\r
+(\r
+    mss_uart_instance_t * this_uart,\r
+    uint32_t baud_rate,\r
+    uint8_t line_config\r
+)\r
+{\r
+    /* The driver expects g_mss_uart0 and g_mss_uart1 to be the only\r
+     * mss_uart_instance_t instances used to identify UART0 and UART1. */\r
+    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));\r
+\r
+    if(this_uart == &g_mss_uart0)\r
+    {\r
+        this_uart->hw_reg = UART0;\r
+        this_uart->irqn = UART0_IRQn;\r
+        /* reset UART0 */\r
+        SYSREG->SOFT_RST_CR |= SYSREG_MMUART0_SOFTRESET_MASK;\r
+        /* Clear any previously pended UART0 interrupt */\r
+        NVIC_ClearPendingIRQ(UART0_IRQn);\r
+        /* Take UART0 out of reset. */\r
+        SYSREG->SOFT_RST_CR &= ~SYSREG_MMUART0_SOFTRESET_MASK;\r
+    }\r
+    else\r
+    {\r
+        this_uart->hw_reg = UART1;\r
+        this_uart->irqn = UART1_IRQn;\r
+        /* Reset UART1 */\r
+        SYSREG->SOFT_RST_CR |= SYSREG_MMUART1_SOFTRESET_MASK;\r
+        /* Clear any previously pended UART1 interrupt */\r
+        NVIC_ClearPendingIRQ(UART1_IRQn);\r
+        /* Take UART1 out of reset. */\r
+        SYSREG->SOFT_RST_CR &= ~SYSREG_MMUART1_SOFTRESET_MASK;\r
+    }\r
+\r
+    /* disable interrupts */\r
+    this_uart->hw_reg->IER = 0u;\r
+\r
+    /* FIFO configuration */\r
+    this_uart->hw_reg->FCR = (uint8_t)MSS_UART_FIFO_SINGLE_BYTE;\r
+    /* clear receiver FIFO */\r
+    set_bit_reg8(&this_uart->hw_reg->FCR,CLEAR_RX_FIFO);\r
+    /* clear transmitter FIFO */\r
+    set_bit_reg8(&this_uart->hw_reg->FCR,CLEAR_TX_FIFO);\r
+\r
+    /* set default READY mode : Mode 0*/\r
+    /* enable RXRDYN and TXRDYN pins. The earlier FCR write to set the TX FIFO\r
+     * trigger level inadvertently disabled the FCR_RXRDY_TXRDYN_EN bit. */\r
+    set_bit_reg8(&this_uart->hw_reg->FCR,RXRDY_TXRDYN_EN);\r
+\r
+    /* disable loopback : local * remote */\r
+    clear_bit_reg8(&this_uart->hw_reg->MCR,LOOP);\r
+    clear_bit_reg8(&this_uart->hw_reg->MCR,RLOOP);\r
+\r
+    /* set default TX endian */\r
+    clear_bit_reg8(&this_uart->hw_reg->MM1,E_MSB_TX);\r
+    /* set default RX endian */\r
+    clear_bit_reg8(&this_uart->hw_reg->MM1,E_MSB_RX);\r
+\r
+    /* default AFM : disabled */\r
+    clear_bit_reg8(&this_uart->hw_reg->MM2,EAFM);\r
+\r
+    /* disable TX time gaurd */\r
+    clear_bit_reg8(&this_uart->hw_reg->MM0,ETTG);\r
+\r
+    /* set default RX timeout */\r
+    clear_bit_reg8(&this_uart->hw_reg->MM0,ERTO);\r
+\r
+    /* disable fractional baud-rate */\r
+    clear_bit_reg8(&this_uart->hw_reg->MM0,EFBR);\r
+\r
+    /* disable single wire mode */\r
+    clear_bit_reg8(&this_uart->hw_reg->MM2,ESWM);\r
+\r
+    /* set filter to minimum value */\r
+    this_uart->hw_reg->GFR = 0u;\r
+    /* set default TX time gaurd */\r
+    this_uart->hw_reg->TTG = 0u;\r
+    /* set default RX timeout */\r
+    this_uart->hw_reg->RTO = 0u;\r
+\r
+    /*\r
+     * Configure baud rate divisors. This uses the frational baud rate divisor\r
+     * where possible to provide the most accurate baud rat possible.\r
+     */\r
+    config_baud_divisors(this_uart, baud_rate);\r
+\r
+    /* set the line control register (bit length, stop bits, parity) */\r
+    this_uart->hw_reg->LCR = line_config;\r
+\r
+    /* Instance setup */\r
+    this_uart->baudrate = baud_rate;\r
+    this_uart->lineconfig = line_config;\r
+    this_uart->tx_buff_size = TX_COMPLETE;\r
+    this_uart->tx_buffer = (const uint8_t *)0;\r
+    this_uart->tx_idx = 0u;\r
+\r
+    /* Default handlers for MSS UART interrupts */\r
+    this_uart->rx_handler       = NULL_HANDLER;\r
+    this_uart->tx_handler       = NULL_HANDLER;\r
+    this_uart->linests_handler  = NULL_HANDLER;\r
+    this_uart->modemsts_handler = NULL_HANDLER;\r
+    this_uart->rto_handler      = NULL_HANDLER;\r
+    this_uart->nack_handler     = NULL_HANDLER;\r
+    this_uart->pid_pei_handler  = NULL_HANDLER;\r
+    this_uart->break_handler    = NULL_HANDLER;\r
+    this_uart->sync_handler     = NULL_HANDLER;\r
+\r
+    /* Initialize the sticky status */\r
+    this_uart->status = 0u;\r
+}\r
+\r
+/***************************************************************************//**\r
+ * Interrupt service routine triggered by any MSS UART interrupt. This routine\r
+ * will call the handler function appropriate to the interrupt from the\r
+ * handlers previously registered with the driver through calls to the\r
+ * MSS_UART_set_*_handler() functions, or it will call the default_tx_handler()\r
+ * function in response to transmit interrupts if MSS_UART_irq_tx() is used to\r
+ * transmit data.\r
+ */\r
+static void\r
+MSS_UART_isr\r
+(\r
+    mss_uart_instance_t * this_uart\r
+)\r
+{\r
+    uint8_t iirf;\r
+\r
+    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));\r
+\r
+    if((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1))\r
+    {\r
+        iirf = this_uart->hw_reg->IIR & IIRF_MASK;\r
+\r
+        switch (iirf)\r
+        {\r
+            case IIRF_MODEM_STATUS:  /* Modem status interrupt */\r
+            {\r
+                ASSERT(NULL_HANDLER != this_uart->modemsts_handler);\r
+                if(NULL_HANDLER != this_uart->modemsts_handler)\r
+                {\r
+                   (*(this_uart->modemsts_handler))(this_uart);\r
+                }\r
+            }\r
+            break;\r
+\r
+            case IIRF_THRE: /* Transmitter Holding Register Empty */\r
+            {\r
+                ASSERT(NULL_HANDLER != this_uart->tx_handler);\r
+                if(NULL_HANDLER != this_uart->tx_handler)\r
+                {\r
+                    (*(this_uart->tx_handler))(this_uart);\r
+                }\r
+            }\r
+            break;\r
+\r
+            case IIRF_RX_DATA:      /* Received Data Available */\r
+            case IIRF_DATA_TIMEOUT: /* Received Data Timed-out */\r
+            {\r
+                ASSERT(NULL_HANDLER != this_uart->rx_handler);\r
+                if(NULL_HANDLER != this_uart->rx_handler)\r
+                {\r
+                    (*(this_uart->rx_handler))(this_uart);\r
+                }\r
+            }\r
+            break;\r
+\r
+            case IIRF_RX_LINE_STATUS:  /* Line Status Interrupt */\r
+            {\r
+                ASSERT(NULL_HANDLER != this_uart->linests_handler);\r
+                if(NULL_HANDLER != this_uart->linests_handler)\r
+                {\r
+                   (*(this_uart->linests_handler))(this_uart);\r
+                }\r
+            }\r
+            break;\r
+\r
+            case IIRF_MMI:\r
+            {\r
+                /* Identify multimode interrupts and handle */\r
+\r
+                /* Receiver time-out interrupt */\r
+                if(read_bit_reg8(&this_uart->hw_reg->IIM,ERTOI))\r
+                {\r
+                    ASSERT(NULL_HANDLER != this_uart->rto_handler);\r
+                    if(NULL_HANDLER != this_uart->rto_handler)\r
+                    {\r
+                        (*(this_uart->rto_handler))(this_uart);\r
+                    }\r
+                }\r
+                /* NACK interrupt */\r
+                if(read_bit_reg8(&this_uart->hw_reg->IIM,ENACKI))\r
+                {\r
+                    ASSERT(NULL_HANDLER != this_uart->nack_handler);\r
+                    if(NULL_HANDLER != this_uart->nack_handler)\r
+                    {\r
+                        (*(this_uart->nack_handler))(this_uart);\r
+                    }\r
+                }\r
+\r
+                /* PID parity error interrupt */\r
+                if(read_bit_reg8(&this_uart->hw_reg->IIM,EPID_PEI))\r
+                {\r
+                    ASSERT(NULL_HANDLER != this_uart->pid_pei_handler);\r
+                    if(NULL_HANDLER != this_uart->pid_pei_handler)\r
+                    {\r
+                        (*(this_uart->pid_pei_handler))(this_uart);\r
+                    }\r
+                }\r
+\r
+                /* LIN break detection interrupt */\r
+                if(read_bit_reg8(&this_uart->hw_reg->IIM,ELINBI))\r
+                {\r
+                    ASSERT(NULL_HANDLER != this_uart->break_handler);\r
+                    if(NULL_HANDLER != this_uart->break_handler)\r
+                    {\r
+                        (*(this_uart->break_handler))(this_uart);\r
+                    }\r
+                }\r
+\r
+                /* LIN Sync detection interrupt */\r
+                if(read_bit_reg8(&this_uart->hw_reg->IIM,ELINSI))\r
+                {\r
+                    ASSERT(NULL_HANDLER != this_uart->sync_handler);\r
+                    if(NULL_HANDLER != this_uart->sync_handler)\r
+                    {\r
+                        (*(this_uart->sync_handler))(this_uart);\r
+                    }\r
+                }\r
+                break;\r
+            }\r
+\r
+            default:\r
+            {\r
+                ASSERT(INVALID_INTERRUPT);\r
+            }\r
+            break;\r
+        }\r
+    }\r
+}\r
+\r
+/***************************************************************************//**\r
+ * See mss_uart.h for details of how to use this function.\r
+ */\r
+static void\r
+default_tx_handler\r
+(\r
+    mss_uart_instance_t * this_uart\r
+)\r
+{\r
+    uint8_t status;\r
+\r
+    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));\r
+    ASSERT(( (uint8_t *)0 ) != this_uart->tx_buffer);\r
+    ASSERT(0u < this_uart->tx_buff_size);\r
+\r
+    if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) &&\r
+       (((uint8_t *)0 ) != this_uart->tx_buffer) &&\r
+       (0u < this_uart->tx_buff_size))\r
+    {\r
+        /* Read the Line Status Register and update the sticky record. */\r
+        status = this_uart->hw_reg->LSR;\r
+        this_uart->status |= status;\r
+\r
+        /*\r
+         * This function should only be called as a result of a THRE interrupt.\r
+         * Verify that this is true before proceeding to transmit data.\r
+         */\r
+        if(status & MSS_UART_THRE)\r
+        {\r
+            uint32_t i;\r
+            uint32_t fill_size = TX_FIFO_SIZE;\r
+            uint32_t tx_remain = this_uart->tx_buff_size - this_uart->tx_idx;\r
+\r
+            /* Calculate the number of bytes to transmit. */\r
+            if(tx_remain < TX_FIFO_SIZE)\r
+            {\r
+                fill_size = tx_remain;\r
+            }\r
+\r
+            /* Fill the TX FIFO with the calculated the number of bytes. */\r
+            for(i = 0u; i < fill_size; ++i)\r
+            {\r
+                /* Send next character in the buffer. */\r
+                this_uart->hw_reg->THR = this_uart->tx_buffer[this_uart->tx_idx];\r
+                ++this_uart->tx_idx;\r
+            }\r
+        }\r
+\r
+        /* Flag Tx as complete if all data has been pushed into the Tx FIFO. */\r
+        if(this_uart->tx_idx == this_uart->tx_buff_size)\r
+        {\r
+            this_uart->tx_buff_size = TX_COMPLETE;\r
+            /* disables TX interrupt */\r
+            clear_bit_reg8(&this_uart->hw_reg->IER,ETBEI);\r
+        }\r
+    }\r
+}\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
diff --git a/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers/mss_uart/mss_uart.h b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers/mss_uart/mss_uart.h
new file mode 100644 (file)
index 0000000..cdabb78
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers/mss_uart/mss_uart.h
@@ -0,0 +1,2639 @@
+/*******************************************************************************\r
+ * (c) Copyright 2011-2013 Microsemi SoC Products Group.  All rights reserved.\r
+ *\r
+ * SmartFusion2 Microcontroller Subsystem MMUART bare metal software driver\r
+ * public API.\r
+ *\r
+ * SVN $Revision: 5610 $\r
+ * SVN $Date: 2013-04-05 14:19:30 +0100 (Fri, 05 Apr 2013) $\r
+ */\r
+/*=========================================================================*//**\r
+  @mainpage SmartFusion2 MSS UART Bare Metal Driver.\r
+  ==============================================================================\r
+  @section intro_sec Introduction\r
+  ==============================================================================\r
+  The SmartFusion2 microcontroller subsystem (MSS) includes two multi-mode UART\r
+  (MMUART) peripherals for serial communication. This driver provides a set of\r
+  functions for controlling the MSS MMUARTs  as part of a bare metal system\r
+  where no operating system is available. These drivers can be adapted for use\r
+  as part of an operating system, but the implementation of the adaptation layer\r
+  between this driver and the operating system's driver model is outside the\r
+  scope of this driver.\r
+  Note: MSS UART is synonymous with MSS MMUART in this document.\r
+  \r
+  ==============================================================================\r
+  @section hw_dependencies Hardware Flow Dependencies\r
+  ==============================================================================\r
+  The configuration of all features of the MSS MMUART peripherals is covered by\r
+  this driver with the exception of the SmartFusion2 IOMUX configuration.\r
+  SmartFusion2 allows multiple non-concurrent uses of some external pins through\r
+  IOMUX configuration. This feature allows optimization of external pin usage by\r
+  assigning external pins for use by either the microcontroller subsystem or the\r
+  FPGA fabric. The MSS MMUART serial signals are routed through IOMUXs to the\r
+  SmartFusion2 device external pins. The MSS MMUART serial signals may also be\r
+  routed through IOMUXs to the SmartFusion2 FPGA fabric. For more information on\r
+  IOMUX, refer to the IOMUX section of the SmartFusion2 Microcontroller\r
+  Subsystem (MSS) User\92s Guide.\r
+  The IOMUXs are configured using the SmartFusion2 MSS configurator tool. You\r
+  must ensure that the MSS MMUART peripherals are enabled and configured in the\r
+  SmartFusion2 MSS configurator if you wish to use them. For more information on\r
+  IOMUXs, refer to the IOMUX section of the SmartFusion2 Microcontroller\r
+  Subsystem (MSS) User\92s Guide.\r
+  The base address, register addresses and interrupt number assignment for the\r
+  MSS MMUART peripherals are defined as constants in the SmartFusion2 CMSIS HAL.\r
+  You must ensure that the latest SmartFusion2 CMSIS HAL is included in the\r
+  project settings of the software tool chain used to build your project and\r
+  that it is generated into your project.\r
+  \r
+  ==============================================================================\r
+  @section theory_op Theory of Operation\r
+  ==============================================================================\r
+  The MSS MMUART driver functions are grouped into the following categories:\r
+    - Initialization and configuration functions\r
+    - Polled transmit and receive functions\r
+    - Interrupt driven transmit and receive functions\r
+    \r
+  --------------------------------\r
+  Initialization and Configuration\r
+  --------------------------------\r
+  The MSS MMUART supports the following four broad modes of operation:\r
+    - UART or USART mode\r
+    - LIN mode\r
+    - IrDA mode\r
+    - Smartcard or ISO 7816 mode\r
+  The MSS MMUART driver provides the MSS_UART_init(), MSS_UART_lin_init(),\r
+  MSS_UART_irda_init() and MSS_UART_smartcard_init() functions to initialize the\r
+  MSS MMUARTs for operation in one of these modes. One of these initialization\r
+  functions must be called before any other MSS MMUART driver functions can be\r
+  called. The MSS MMUART operating modes are mutually exclusive; therefore only\r
+  one of the initialization functions must be called. The first parameter of the\r
+  initialization functions is a pointer to one of two global data structures\r
+  used to store state information for each MSS MMUART. A pointer to these data\r
+  structures is also used as the first parameter to many of the driver functions\r
+  to identify which MSS MMUART will be used by the called function. The names of\r
+  these two data structures are g_mss_uart0 and g_mss_uart1. Therefore, any call\r
+  to an MSS MMUART function should be of the form \r
+  MSS_UART_function_name( &g_mss_uart0, ... ) or\r
+  MSS_UART_function_name( &g_mss_uart1, ... ).\r
+  \r
+  UART or USART Mode\r
+  For the UART or USART modes of operation, the MSS MMUART driver is initialized\r
+  through a call to the MSS_UART_init() function. This function takes the UART\92s\r
+  configuration as its parameters. The MSS_UART_init() function must be called\r
+  before any other MSS MMUART driver functions can be called.\r
+  The MSS_UART_init() function configures the baud rate based on the input baud\r
+  rate parameter and if possible uses a fractional baud rate for greater\r
+  precision. This function disables the LIN, IrDA and SmartCard modes.\r
+  \r
+  LIN mode\r
+  For the LIN mode of operation, the MSS MMUART driver is initialized through a\r
+  call to the MSS_UART_lin_init() function. This function takes the LIN node\92s\r
+  configuration as its parameters. The MSS_UART_lin_init() function must be\r
+  called before any other MSS MMUART driver functions can be called. The\r
+  MSS_UART_lin_init() function configures the baud rate based on the input baud\r
+  rate parameter and if possible uses a fractional baud rate for greater\r
+  precision. This function disables the IrDA and SmartCard modes.\r
+  The driver also provides the following LIN mode configuration functions:\r
+    - MSS_UART_set_break()\r
+    - MSS_UART_clear_break()\r
+    - MSS_UART_set_pidpei_handler()\r
+    - MSS_UART_set_linbreak_handler()\r
+    - MSS_UART_set_linsync_handler()\r
+  Note: These LIN mode configuration functions can only be called after the\r
+  MSS_UART_lin_init() function is called.\r
+  \r
+  IrDA mode\r
+  For the IrDA mode of operation, the driver is initialized through a call to\r
+  the MSS_UART_irda_init() function. This function takes the IrDA node\92s\r
+  configuration as its parameters. The MSS_UART_irda_init() function must be\r
+  called before any other MSS MMUART driver functions can be called. The\r
+  MSS_UART_irda_init() function configures the baud rate based on the input baud\r
+  rate parameter and if possible uses a fractional baud rate for greater\r
+  precision. This function disables the LIN and SmartCard modes.\r
+  \r
+  Smartcard or ISO 7816 mode\r
+  For the Smartcard or ISO 7816 mode of operation, the driver is initialized\r
+  through a call to the MSS_UART_smartcard_init() function. This function takes\r
+  the smartcard configuration as its parameters. The MSS_UART_smartcard_init()\r
+  function must be called before any other MSS MMUART driver functions can be\r
+  called. The MSS_UART_smartcard_init() function configures the baud rate based\r
+  on the input baud rate parameter and if possible uses a fractional baud rate\r
+  for greater precision. This function disables the LIN and IrDA modes.\r
+  The driver also provides the following Smartcard mode configuration functions:\r
+    - MSS_UART_enable_halfduplex()\r
+    - MSS_UART_disable_halfduplex()\r
+    - MSS_UART_set_nack_handler()\r
+  Note: These Smartcard mode configuration functions can only be called after\r
+  the MSS_UART_smartcard_init() function is called.\r
+  \r
+  Common Configuration Functions\r
+  The driver also provides the configuration functions that can be used with all\r
+  MSS MMUART operating modes. These common configuration functions are as\r
+  follows:\r
+    - MSS_UART_set_rx_endian()\r
+    - MSS_UART_set_tx_endian()\r
+    - MSS_UART_enable_afclear()\r
+    - MSS_UART_disable_afclear()\r
+    - MSS_UART_enable_rx_timeout()\r
+    - MSS_UART_disable_rx_timeout()\r
+    - MSS_UART_enable_tx_time_guard()\r
+    - MSS_UART_disable_tx_time_guard()\r
+    - MSS_UART_set_address()\r
+    - MSS_UART_set_ready_mode()\r
+    - MSS_UART_set_usart_mode()\r
+    - MSS_UART_set_filter_length()\r
+    - MSS_UART_enable_afm()\r
+    - MSS_UART_disable_afm()\r
+  Note: These configuration functions can only be called after one of the\r
+        MSS_UART_init(), MSS_UART_lin_init(), MSS_UART_irda_init() or\r
+        MSS_UART_smartcard_init() functions is called.\r
+  \r
+  --------------------------------------  \r
+  Polled Transmit and Receive Operations\r
+  --------------------------------------\r
+  The driver can be used to transmit and receive data once initialized. \r
+  Data is transmitted using the MSS_UART_polled_tx() function. This function is\r
+  blocking, meaning that it will only return once the data passed to the\r
+  function has been sent to the MSS MMUART hardware transmitter. Data received\r
+  by the MSS MMUART hardware receiver can be read by the MSS_UART_get_rx()\r
+  function.\r
+  The MSS_UART_polled_tx_string() function is provided to transmit a NULL (\91\0\92)\r
+  terminated string in polled mode. This function is blocking, meaning that it\r
+  will only return once the data passed to the function has been sent to the MSS\r
+  MMUART hardware transmitter.\r
+  The MSS_UART_fill_tx_fifo() function fills the MSS MMUART hardware transmit\r
+  FIFO with data from a buffer passed as a parameter and returns the number of\r
+  bytes transferred to the FIFO. If the transmit FIFO is not empty when the\r
+  MSS_UART_fill_tx_fifo() function is called it returns immediately without\r
+  transferring any data to the FIFO.\r
+  \r
+  ---------------------------\r
+  Interrupt Driven Operations\r
+  ---------------------------\r
+  The driver can also transmit or receive data under interrupt control, freeing\r
+  your application to perform other tasks until an interrupt occurs indicating\r
+  that the driver\92s attention is required.\r
+  \r
+  Interrupt Handlers\r
+  The MSS MMUART driver supports all types of interrupt triggered by the MSS\r
+  MMUART. The driver\92s internal top level interrupt handler identifies the\r
+  source of the MSS MMUART interrupt and calls the corresponding lower level\r
+  handler function that you previously registered with the driver through calls\r
+  to the MSS_UART_set_rx_handler(), MSS_UART_set_tx_handler(),\r
+  MSS_UART_set_rxstatus_handler(), and MSS_UART_set_modemstatus_handler()\r
+  functions. You are responsible for creating these lower level interrupt\r
+  handlers as part of your application program and registering them with the\r
+  driver.\r
+  Note: The SmartFusion2 CMSIS-PAL defines the UART0_IRQHandler() and\r
+        UART1_IRQHandler() functions (with weak linkage) and assigns them as the\r
+        interrupt service routines (ISR) for the MSS MMUART interrupt inputs to\r
+        the Cortex-M3 NVIC. The MSS MMUART driver provides the implementation\r
+        functions for both of these ISRs from which it calls its own internal\r
+        top level, interrupt handler function.\r
+  The MSS_UART_enable_irq() and MSS_UART_disable_irq() functions are used to\r
+  enable or disable the received line status, received data available/character\r
+  timeout, transmit holding register empty and modem status interrupts at the\r
+  MSS MMUART level. The MSS_UART_enable_irq() function also enables the MSS\r
+  MMUART instance interrupt at the Cortex-M3 level.\r
+  \r
+  Transmitting Data\r
+  Interrupt-driven transmit is initiated by a call to MSS_UART_irq_tx(),\r
+  specifying the block of data to transmit. Your application is then free to\r
+  perform other tasks and inquire later whether transmit has completed by\r
+  calling the MSS_UART_tx_complete() function. The MSS_UART_irq_tx() function\r
+  enables the UART\92s transmit holding register empty (THRE) interrupt and then,\r
+  when the interrupt goes active, the driver\92s default THRE interrupt handler\r
+  transfers the data block to the UART until the entire block is transmitted.\r
+  Note: You can use the MSS_UART_set_tx_handler() function to assign an\r
+        alternative handler to the THRE interrupt. In this case, you must not\r
+        use the MSS_UART_irq_tx() function to initiate the transmit, as this\r
+        will re-assign the driver\92s default THRE interrupt handler to the THRE\r
+        interrupt. Instead, your alternative THRE interrupt handler must include\r
+        a call to the MSS_UART_fill_tx_fifo() function to transfer the data to\r
+        the UART.\r
+  \r
+  Receiving Data\r
+  Interrupt-driven receive is performed by first calling\r
+  MSS_UART_set_rx_handler() to register a receive handler function that will be\r
+  called by the driver whenever receive data is available. You must provide this\r
+  receive handler function which must include a call to the MSS_UART_get_rx()\r
+  function to actually read the received data.\r
+  \r
+  -----------\r
+  UART Status\r
+  -----------\r
+  The function MSS_UART_get_rx_status() is used to read the receiver error\r
+  status. This function returns the overrun, parity, framing, break, and FIFO\r
+  error status of the receiver.\r
+  The function MSS_UART_get_tx_status() is used to read the transmitter status.\r
+  This function returns the transmit empty (TEMT) and transmit holding register\r
+  empty (THRE) status of the transmitter.\r
+  The function MSS_UART_get_modem_status() is used to read the modem status\r
+  flags. This function returns the current value of the modem status register.\r
+  \r
+  --------\r
+  Loopback\r
+  --------\r
+  The MSS_UART_set_loopback() function can be used to locally loopback the Tx\r
+  and Rx lines of a UART. This is not to be confused with the loopback of UART0\r
+  to UART1, which can be achieved through the microcontroller subsystem\92s system\r
+  registers.\r
+  \r
+ *//*=========================================================================*/\r
+#ifndef __MSS_UART_H_\r
+#define __MSS_UART_H_ 1\r
+\r
+#include "../../CMSIS/m2sxxx.h"\r
+#include <stddef.h>\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/***************************************************************************//**\r
+  Baud rates\r
+  The following definitions are used to specify standard baud rates as a\r
+  parameter to the MSS_UART_init() function.\r
+ */\r
+#define MSS_UART_110_BAUD       110\r
+#define MSS_UART_300_BAUD       300\r
+#define MSS_UART_1200_BAUD      1200\r
+#define MSS_UART_2400_BAUD      2400\r
+#define MSS_UART_4800_BAUD      4800\r
+#define MSS_UART_9600_BAUD      9600\r
+#define MSS_UART_19200_BAUD     19200\r
+#define MSS_UART_38400_BAUD     38400\r
+#define MSS_UART_57600_BAUD     57600\r
+#define MSS_UART_115200_BAUD    115200\r
+#define MSS_UART_230400_BAUD    230400\r
+#define MSS_UART_460800_BAUD    460800\r
+#define MSS_UART_921600_BAUD    921600\r
+\r
+/***************************************************************************//**\r
+  Data Bits Length\r
+  The following defines are used to build the value of the MSS_UART_init()\r
+  function line_config parameter.\r
+ */\r
+#define MSS_UART_DATA_5_BITS     ( (uint8_t) 0x00 )\r
+#define MSS_UART_DATA_6_BITS     ( (uint8_t) 0x01 )\r
+#define MSS_UART_DATA_7_BITS     ( (uint8_t) 0x02 )\r
+#define MSS_UART_DATA_8_BITS     ( (uint8_t) 0x03 )\r
+\r
+/***************************************************************************//**\r
+  Parity\r
+  The following defines are used to build the value of the MSS_UART_init()\r
+  function line_config parameter.\r
+ */\r
+#define MSS_UART_NO_PARITY           ( (uint8_t) 0x00 )\r
+#define MSS_UART_ODD_PARITY          ( (uint8_t) 0x08 )\r
+#define MSS_UART_EVEN_PARITY         ( (uint8_t) 0x18 )\r
+#define MSS_UART_STICK_PARITY_0      ( (uint8_t) 0x38 )\r
+#define MSS_UART_STICK_PARITY_1      ( (uint8_t) 0x28 )\r
+\r
+/***************************************************************************//**\r
+  Number of Stop Bits\r
+  The following defines are used to build the value of the MSS_UART_init()\r
+  function line_config parameter.\r
+ */\r
+#define MSS_UART_ONE_STOP_BIT        ( (uint8_t) 0x00 )\r
+#define MSS_UART_ONEHALF_STOP_BIT    ( (uint8_t) 0x04 )\r
+#define MSS_UART_TWO_STOP_BITS       ( (uint8_t) 0x04 )\r
+\r
+/***************************************************************************//**\r
+  Receiver Error Status\r
+  The following defines are used to determine the UART receiver error type.\r
+  These bit mask constants are used with the return value of the\r
+  MSS_UART_get_rx_status() function to find out if any errors occurred while\r
+  receiving data.\r
+ */\r
+#define MSS_UART_INVALID_PARAM    ( (uint8_t)0xFF )\r
+#define MSS_UART_NO_ERROR         ( (uint8_t)0x00 )\r
+#define MSS_UART_OVERUN_ERROR     ( (uint8_t)0x02 )\r
+#define MSS_UART_PARITY_ERROR     ( (uint8_t)0x04 )\r
+#define MSS_UART_FRAMING_ERROR    ( (uint8_t)0x08 )\r
+#define MSS_UART_BREAK_ERROR      ( (uint8_t)0x10 )\r
+#define MSS_UART_FIFO_ERROR       ( (uint8_t)0x80 )\r
+\r
+/***************************************************************************//**\r
+  Transmitter Status\r
+  The following definitions are used to determine the UART transmitter status.\r
+  These bit mask constants are used with the return value of the\r
+  MSS_UART_get_tx_status() function to find out the status of the transmitter.\r
+ */\r
+#define MSS_UART_TX_BUSY          ( (uint8_t) 0x00 )\r
+#define MSS_UART_THRE             ( (uint8_t) 0x20 )\r
+#define MSS_UART_TEMT             ( (uint8_t) 0x40 )\r
+\r
+/***************************************************************************//**\r
+  Modem Status\r
+  The following defines are used to determine the modem status. These bit\r
+  mask constants are used with the return value of the\r
+  MSS_UART_get_modem_status() function to find out the modem status of\r
+  the UART.\r
+ */\r
+#define MSS_UART_DCTS             ( (uint8_t) 0x01 )\r
+#define MSS_UART_DDSR             ( (uint8_t) 0x02 )\r
+#define MSS_UART_TERI             ( (uint8_t) 0x04 )\r
+#define MSS_UART_DDCD             ( (uint8_t) 0x08 )\r
+#define MSS_UART_CTS              ( (uint8_t) 0x10 )\r
+#define MSS_UART_DSR              ( (uint8_t) 0x20 )\r
+#define MSS_UART_RI               ( (uint8_t) 0x40 )\r
+#define MSS_UART_DCD              ( (uint8_t) 0x80 )\r
+\r
+/***************************************************************************//**\r
+  This typedef specifies the irq_mask parameter for the MSS_UART_enable_irq()\r
+  and MSS_UART_disable_irq() functions. The driver defines a set of bit masks\r
+  that are used to build the value of the irq_mask parameter. A bitwise OR of\r
+  these bit masks is used to enable or disable multiple MSS MMUART interrupts.\r
+ */\r
+typedef uint16_t mss_uart_irq_t;\r
+\r
+/***************************************************************************//**\r
+  The following defines specify the interrupt masks to enable and disable MSS\r
+  MMUART interrupts. They are used to build the value of the irq_mask parameter\r
+  for the MSS_UART_enable_irq() and MSS_UART_disable_irq() functions. A bitwise\r
+  OR of these constants is used to enable or disable multiple interrupts.\r
+ */\r
+#define MSS_UART_RBF_IRQ        0x001\r
+#define MSS_UART_TBE_IRQ        0x002\r
+#define MSS_UART_LS_IRQ         0x004\r
+#define MSS_UART_MS_IRQ         0x008\r
+#define MSS_UART_RTO_IRQ        0x010\r
+#define MSS_UART_NACK_IRQ       0x020\r
+#define MSS_UART_PIDPE_IRQ      0x040\r
+#define MSS_UART_LINB_IRQ       0x080\r
+#define MSS_UART_LINS_IRQ       0x100\r
+#define MSS_UART_INVALID_IRQ    UINT16_MAX\r
+\r
+/***************************************************************************//**\r
+  This enumeration specifies the receiver FIFO trigger level. This is the number\r
+  of bytes that must be received before the UART generates a receive data\r
+  available interrupt. It provides the allowed values for the\r
+  MSS_UART_set_rx_handler() function trigger_level parameter.\r
+ */\r
+typedef enum {\r
+    MSS_UART_FIFO_SINGLE_BYTE    = 0x00,\r
+    MSS_UART_FIFO_FOUR_BYTES     = 0x40,\r
+    MSS_UART_FIFO_EIGHT_BYTES    = 0x80,\r
+    MSS_UART_FIFO_FOURTEEN_BYTES = 0xC0,\r
+    MSS_UART_FIFO_INVALID_TRIG_LEVEL\r
+} mss_uart_rx_trig_level_t;\r
+\r
+/***************************************************************************//**\r
+  This enumeration specifies the loopback configuration of the UART. It provides\r
+  the allowed values for the MSS_UART_set_loopback() function\92s loopback\r
+  parameter. Use MSS_UART_LOCAL_LOOPBACK_ON to set up the UART to locally\r
+  loopback its Tx and Rx lines. Use MSS_UART_REMOTE_LOOPBACK_ON to set up the\r
+  UART in remote loopback mode.\r
+ */\r
+typedef enum {\r
+    MSS_UART_LOCAL_LOOPBACK_OFF,\r
+    MSS_UART_LOCAL_LOOPBACK_ON,\r
+    MSS_UART_REMOTE_LOOPBACK_OFF,\r
+    MSS_UART_REMOTE_LOOPBACK_ON,\r
+    MSS_UART_AUTO_ECHO_OFF,\r
+    MSS_UART_AUTO_ECHO_ON,\r
+    MSS_UART_INVALID_LOOPBACK\r
+} mss_uart_loopback_t;\r
+\r
+/***************************************************************************//**\r
+  IrDA input / output polarity.\r
+  This enumeration specifies the RZI modem polarity for input and output signals. \r
+  This is passed as parameters in MSS_UART_irda_init() function.\r
+ */\r
+typedef enum {\r
+    MSS_UART_ACTIVE_LOW = 0u,\r
+    MSS_UART_ACTIVE_HIGH = 1u,\r
+    MSS_UART_INVALID_POLARITY\r
+} mss_uart_rzi_polarity_t;\r
+\r
+/***************************************************************************//**\r
+  IrDA input / output pulse width.\r
+  This enumeration specifies the RZI modem pulse width for input and output signals. \r
+  This is passed as parameters in MSS_UART_irda_init() function.\r
+ */\r
+typedef enum {\r
+    MSS_UART_3_BY_16 = 0u,\r
+    MSS_UART_1_BY_4 = 1u,\r
+    MSS_UART_INVALID_PW\r
+} mss_uart_rzi_pulsewidth_t;\r
+\r
+/***************************************************************************//**\r
+  Tx / Rx endianess.\r
+  This enumeration specifies the MSB first or LSB first for MSS UART transmitter \r
+  and receiver. The parameter of this type shall be passed in \r
+  MSS_UART_set_rx_endian()and MSS_UART_set_tx_endian() functions.\r
+ */\r
+typedef enum {\r
+    MSS_UART_LITTLEEND,\r
+    MSS_UART_BIGEND,\r
+    MSS_UART_INVALID_ENDIAN\r
+} mss_uart_endian_t;\r
+\r
+/***************************************************************************//**\r
+  Glitch filter length.\r
+  This enumeration specifies the glitch filter length. The function \r
+  MSS_UART_set_filter_length() accepts the parameter of this type.\r
+ */\r
+typedef enum {\r
+    MSS_UART_LEN0 = 0,\r
+    MSS_UART_LEN1 = 1,\r
+    MSS_UART_LEN2 = 2,\r
+    MSS_UART_LEN3 = 3,\r
+    MSS_UART_LEN4 = 4,\r
+    MSS_UART_LEN5 = 5,\r
+    MSS_UART_LEN6 = 6,\r
+    MSS_UART_LEN7 = 7,\r
+    MSS_UART_INVALID_FILTER_LENGTH = 8\r
+} mss_uart_filter_length_t;\r
+\r
+/***************************************************************************//**\r
+  TXRDY and RXRDY mode.\r
+  This enumeration specifies the TXRDY and RXRDY signal modes. The function \r
+  MSS_UART_set_ready_mode() accepts the parameter of this type.\r
+ */\r
+typedef enum {\r
+    MSS_UART_READY_MODE0,\r
+    MSS_UART_READY_MODE1,\r
+    MSS_UART_INVALID_READY_MODE\r
+} mss_uart_ready_mode_t;\r
+\r
+/***************************************************************************//**\r
+  USART mode of operation.\r
+  This enumeration specifies the mode of operation of MSS UART when operating \r
+  as USART. The function MSS_UART_set_usart_mode() accepts the parameter of this type.\r
+ */\r
+typedef enum {\r
+    MSS_UART_ASYNC_MODE               = 0,\r
+    MSS_UART_SYNC_SLAVE_POS_EDGE_CLK  = 1,\r
+    MSS_UART_SYNC_SLAVE_NEG_EDGE_CLK  = 2,\r
+    MSS_UART_SYNC_MASTER_POS_EDGE_CLK = 3,\r
+    MSS_UART_SYNC_MASTER_NEG_EDGE_CLK = 4,\r
+    MSS_UART_INVALID_SYNC_MODE        = 5\r
+} mss_uart_usart_mode_t;\r
+\r
+\r
+/***************************************************************************//**\r
+  MSS UART instance type.\r
+  This is type definition for MSS UART instance. You need to create and\r
+  maintain a record of this type. This holds all data regarding the MSS UART\r
+  instance\r
+ */\r
+typedef struct  mss_uart_instance mss_uart_instance_t;\r
+\r
+/***************************************************************************//**\r
+  Interrupt handler prototype.\r
+  This typedef specifies the function prototype for MSS UART interrupt handlers.\r
+  All interrupt handlers registered with the MSS UART driver must be of this type.\r
+  The interrupt handlers are registered with the driver through the\r
+  MSS_UART_set_rx_handler(), MSS_UART_set_tx_handler(),\r
+  MSS_UART_set_rxstatus_handler(), and MSS_UART_set_modemstatus_handler()\r
+  functions.\r
+  The this_uart parameter is a pointer to either g_mss_uart0 or g_mss_uart1 to\r
+  identify the MSS UART to associate with the handler function.\r
+ */\r
+typedef void (*mss_uart_irq_handler_t)( mss_uart_instance_t * this_uart );\r
+\r
+/***************************************************************************//**\r
+  mss_uart_instance.\r
+  There is one instance of this structure for each instance of the\r
+  microcontroller subsystem\92s UARTs. Instances of this structure are used to\r
+  identify a specific UART. A pointer to an initialized instance of the\r
+  mss_uart_instance_t structure is passed as the first parameter to\r
+  MSS UART driver functions to identify which UART should perform the\r
+  requested operation.\r
+ */\r
+struct mss_uart_instance{\r
+    /* CMSIS related defines identifying the UART hardware. */\r
+    UART_TypeDef *          hw_reg;     /*!< Pointer to UART registers. */\r
+    IRQn_Type               irqn;       /*!< UART's Cortex-M3 NVIC interrupt number. */\r
+    uint32_t                baudrate;   /*!< Operating baud rate. */\r
+    uint8_t                 lineconfig; /*!< Line configuration parameters. */\r
+    uint8_t                 status;     /*!< Sticky line status. */\r
+\r
+    /* transmit related info (used with interrupt driven transmit): */\r
+    const uint8_t * tx_buffer;          /*!< Pointer to transmit buffer. */\r
+    uint32_t        tx_buff_size;       /*!< Transmit buffer size. */\r
+    uint32_t        tx_idx;             /*!< Index within transmit buffer of next byte to transmit.*/\r
+\r
+    /* line status interrupt handler:*/\r
+    mss_uart_irq_handler_t linests_handler;   /*!< Pointer to user registered line status handler. */\r
+    /* receive interrupt handler:*/\r
+    mss_uart_irq_handler_t rx_handler;        /*!< Pointer to user registered receiver handler. */\r
+    /* transmit interrupt handler:*/\r
+    mss_uart_irq_handler_t tx_handler;        /*!< Pointer to user registered transmit handler. */\r
+    /* modem status interrupt handler:*/\r
+    mss_uart_irq_handler_t modemsts_handler;  /*!< Pointer to user registered modem status handler. */\r
+    /* receiver timeout interrupt handler */\r
+    mss_uart_irq_handler_t rto_handler;       /*!< Pointer to user registered receiver timeout handler. */\r
+    /* NACK interrupt handler */\r
+    mss_uart_irq_handler_t nack_handler;      /*!< Pointer to user registered NACK handler. */\r
+    /* PID parity prror interrup handler */\r
+    mss_uart_irq_handler_t pid_pei_handler;   /*!< Pointer to user registered PID parity error handler. */\r
+    /* LIN break interrupt handler */\r
+    mss_uart_irq_handler_t break_handler;     /*!< Pointer to user registered LIN break handler. */\r
+    /* LIN sync detection interrupt handler */\r
+    mss_uart_irq_handler_t sync_handler;      /*!< Pointer to user registered LIN sync dectection handler. */\r
+};\r
+\r
+/***************************************************************************//**\r
+  This instance of mss_uart_instance_t holds all data related to the operations\r
+  performed by UART0. The function MSS_UART_init() initializes this structure.\r
+  A pointer to g_mss_uart0 is passed as the first parameter to MSS UART driver\r
+  functions to indicate that UART0 should perform the requested operation.\r
+ */\r
+extern mss_uart_instance_t g_mss_uart0;\r
+\r
+/***************************************************************************//**\r
+  This instance of mss_uart_instance_t holds all data related to the operations\r
+  performed by UART1. The function MSS_UART_init() initializes this structure.\r
+  A pointer to g_mss_uart1 is passed as the first parameter to MSS UART driver\r
+  functions to indicate that UART1 should perform the requested operation.\r
+ */\r
+extern mss_uart_instance_t g_mss_uart1;\r
+\r
+/***************************************************************************//**\r
+  The MSS_UART_init() function initializes and configures one of the SmartFusion2\r
+  MSS UARTs with the configuration passed as a parameter. The configuration\r
+  parameters are the baud_rate which is used to generate the baud value and the\r
+  line_config which is used to specify the line configuration (bit length,\r
+  stop bits and parity).\r
+\r
+  @param this_uart\r
+    The this_uart parameter is a pointer to an mss_uart_instance_t structure\r
+    identifying the MSS UART hardware block to be initialized. There are two\r
+    such data structures, g_mss_uart0 and g_mss_uart1, associated with MSS\r
+    UART0 and MSS UART1 respectively. This parameter must point to either\r
+    the g_mss_uart0 or g_mss_uart1 global data structure defined within\r
+    the UART driver..\r
+\r
+  @param baud_rate\r
+    The baud_rate parameter specifies the baud rate. It can be specified for\r
+    common baud rates\92 using the following defines:\r
+    \95   MSS_UART_110_BAUD\r
+    \95   MSS_UART_300_BAUD\r
+    \95   MSS_UART_1200_BAUD\r
+    \95   MSS_UART_2400_BAUD\r
+    \95   MSS_UART_4800_BAUD\r
+    \95   MSS_UART_9600_BAUD\r
+    \95   MSS_UART_19200_BAUD\r
+    \95   MSS_UART_38400_BAUD\r
+    \95   MSS_UART_57600_BAUD\r
+    \95   MSS_UART_115200_BAUD\r
+    \95   MSS_UART_230400_BAUD\r
+    \95   MSS_UART_460800_BAUD\r
+    \95   MSS_UART_921600_BAUD\r
+    Alternatively, any nonstandard baud rate can be specified by simply passing\r
+    the actual required baud rate as the value for this parameter.\r
+\r
+  @param line_config\r
+    The line_config parameter is the line configuration specifying the bit length,\r
+    number of stop bits and parity settings. This is a bitwise OR of one value\r
+    from each of the following groups of allowed values:\r
+    \95   One of the following to specify the transmit/receive data bit length:\r
+        MSS_UART_DATA_5_BITS\r
+        MSS_UART_DATA_6_BITS,\r
+        MSS_UART_DATA_7_BITS\r
+        MSS_UART_DATA_8_BITS\r
+    \95   One of the following to specify the parity setting:\r
+        MSS_UART_NO_PARITY\r
+        MSS_UART_EVEN_PARITY\r
+        MSS_UART_ODD_PARITY\r
+        MSS_UART_STICK_PARITY_0\r
+        MSS_UART_STICK_PARITY_1\r
+    \95   One of the following to specify the number of stop bits:\r
+        MSS_UART_ONE_STOP_BIT\r
+        MSS_UART_ONEHALF_STOP_BIT\r
+        MSS_UART_TWO_STOP_BITS\r
+\r
+  @return\r
+    This function does not return a value.\r
+\r
+  Example:\r
+  @code\r
+  #include "mss_uart.h"\r
+\r
+  int main(void)\r
+  {\r
+     MSS_UART_init(&g_mss_uart0,\r
+                   MSS_UART_57600_BAUD,\r
+                   MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT);\r
+                   \r
+     return(0);\r
+  }\r
+  @endcode\r
+ */\r
+void\r
+MSS_UART_init\r
+(\r
+    mss_uart_instance_t* this_uart,\r
+    uint32_t baud_rate,\r
+    uint8_t line_config\r
+);\r
+\r
+/***************************************************************************//**\r
+ The MSS_UART_lin_init() function is used to initialize the MSS UART for \r
+ LIN mode of operation. The configuration parameters are the baud_rate which is \r
+ used to generate the baud value and the line_config which is used to specify \r
+ the line configuration (bit length, stop bits and parity).\r
+\r
+  @param this_uart\r
+    The this_uart parameter is a pointer to an mss_uart_instance_t\r
+    structure identifying the MSS UART hardware block that will perform\r
+    the requested function. There are two such data structures,\r
+    g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1.\r
+    This parameter must point to either the g_mss_uart0 or g_mss_uart1\r
+    global data structure defined within the UART driver.\r
+\r
+  @param baud_rate\r
+    The baud_rate parameter specifies the baud rate. It can be specified for\r
+    common baud rates\92 using the following defines:\r
+    \95   MSS_UART_110_BAUD\r
+    \95   MSS_UART_300_BAUD\r
+    \95   MSS_UART_1200_BAUD\r
+    \95   MSS_UART_2400_BAUD\r
+    \95   MSS_UART_4800_BAUD\r
+    \95   MSS_UART_9600_BAUD\r
+    \95   MSS_UART_19200_BAUD\r
+    \95   MSS_UART_38400_BAUD\r
+    \95   MSS_UART_57600_BAUD\r
+    \95   MSS_UART_115200_BAUD\r
+    \95   MSS_UART_230400_BAUD\r
+    \95   MSS_UART_460800_BAUD\r
+    \95   MSS_UART_921600_BAUD\r
+    Alternatively, any nonstandard baud rate can be specified by simply passing\r
+    the actual required baud rate as the value for this parameter.\r
+\r
+  @param line_config\r
+    The line_config parameter is the line configuration specifying the bit length,\r
+    number of stop bits and parity settings. This is a bitwise OR of one value\r
+    from each of the following groups of allowed values:\r
+    \95   One of the following to specify the transmit/receive data bit length:\r
+        MSS_UART_DATA_5_BITS\r
+        MSS_UART_DATA_6_BITS,\r
+        MSS_UART_DATA_7_BITS\r
+        MSS_UART_DATA_8_BITS\r
+    \95   One of the following to specify the parity setting:\r
+        MSS_UART_NO_PARITY\r
+        MSS_UART_EVEN_PARITY\r
+        MSS_UART_ODD_PARITY\r
+        MSS_UART_STICK_PARITY_0\r
+        MSS_UART_STICK_PARITY_1\r
+    \95   One of the following to specify the number of stop bits:\r
+        MSS_UART_ONE_STOP_BIT\r
+        MSS_UART_ONEHALF_STOP_BIT\r
+        MSS_UART_TWO_STOP_BITS\r
+\r
+  @return\r
+    This function does not return a value.\r
+\r
+  Example:\r
+  @code\r
+  #include "mss_uart.h"\r
+\r
+  int main(void)\r
+  {\r
+     MSS_UART_lin_init(&g_mss_uart0,\r
+                       MSS_UART_57600_BAUD,\r
+                       MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT);\r
+                       \r
+     return(0);\r
+  }\r
+  @endcode\r
+ */\r
+void \r
+MSS_UART_lin_init\r
+(\r
+    mss_uart_instance_t* this_uart, \r
+    uint32_t baud_rate,\r
+    uint8_t line_config\r
+);\r
+\r
+/***************************************************************************//**\r
+  The MSS_UART_irda_init() function is used to initialize the MSS UART instance \r
+  referenced by the parameter this_uart  for IrDA mode of operation. This \r
+  function must be called before calling any other IrDA functionality specific \r
+  functions.\r
+\r
+  @param this_uart\r
+    The this_uart parameter is a pointer to an mss_uart_instance_t\r
+    structure identifying the MSS UART hardware block that will perform\r
+    the requested function. There are two such data structures,\r
+    g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1.\r
+    This parameter must point to either the g_mss_uart0 or g_mss_uart1\r
+    global data structure defined within the UART driver.\r
+\r
+  @param baud_rate\r
+    The baud_rate parameter specifies the baud rate. It can be specified for\r
+    common baud rates\92 using the following defines:\r
+    \95   MSS_UART_110_BAUD\r
+    \95   MSS_UART_300_BAUD\r
+    \95   MSS_UART_1200_BAUD\r
+    \95   MSS_UART_2400_BAUD\r
+    \95   MSS_UART_4800_BAUD\r
+    \95   MSS_UART_9600_BAUD\r
+    \95   MSS_UART_19200_BAUD\r
+    \95   MSS_UART_38400_BAUD\r
+    \95   MSS_UART_57600_BAUD\r
+    \95   MSS_UART_115200_BAUD\r
+    \95   MSS_UART_230400_BAUD\r
+    \95   MSS_UART_460800_BAUD\r
+    \95   MSS_UART_921600_BAUD\r
+    Alternatively, any nonstandard baud rate can be specified by simply passing\r
+    the actual required baud rate as the value for this parameter.\r
+\r
+  @param line_config\r
+    The line_config parameter is the line configuration specifying the bit length,\r
+    number of stop bits and parity settings. This is a bitwise OR of one value\r
+    from each of the following groups of allowed values:\r
+    \95   One of the following to specify the transmit/receive data bit length:\r
+        MSS_UART_DATA_5_BITS\r
+        MSS_UART_DATA_6_BITS,\r
+        MSS_UART_DATA_7_BITS\r
+        MSS_UART_DATA_8_BITS\r
+    \95   One of the following to specify the parity setting:\r
+        MSS_UART_NO_PARITY\r
+        MSS_UART_EVEN_PARITY\r
+        MSS_UART_ODD_PARITY\r
+        MSS_UART_STICK_PARITY_0\r
+        MSS_UART_STICK_PARITY_1\r
+    \95   One of the following to specify the number of stop bits:\r
+        MSS_UART_ONE_STOP_BIT\r
+        MSS_UART_ONEHALF_STOP_BIT\r
+        MSS_UART_TWO_STOP_BITS\r
+\r
+  @return\r
+    This function does not return a value.\r
+\r
+  Example:\r
+  @code\r
+    MSS_UART_irda_init(&g_mss_uart0,\r
+                       MSS_UART_57600_BAUD,\r
+                       MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT,\r
+                       MSS_UART_ACTIVE_LOW,\r
+                       MSS_UART_ACTIVE_LOW,\r
+                       MSS_UART_3_BY_16);\r
+  @endcode\r
+ */\r
+void \r
+MSS_UART_irda_init\r
+(\r
+    mss_uart_instance_t* this_uart, \r
+    uint32_t baud_rate,\r
+    uint8_t line_config,\r
+    mss_uart_rzi_polarity_t rxpol,\r
+    mss_uart_rzi_polarity_t txpol,\r
+    mss_uart_rzi_pulsewidth_t pw\r
+);\r
+\r
+/***************************************************************************//**\r
+  The MSS_UART_smartcard_init() function is used to initialize the MSS UART \r
+  for ISO 7816 (smartcard) mode of operation. The configuration parameters are \r
+  the baud_rate which is used to generate the baud value and the line_config \r
+  which is used to specify the line configuration (bit length, stop bits and parity). \r
+  This function disables all other modes of the MSS UART instance pointed by \r
+  the parameter this_uart.\r
+  \r
+  @param this_uart\r
+    The this_uart parameter is a pointer to an mss_uart_instance_t\r
+    structure identifying the MSS UART hardware block that will perform\r
+    the requested function. There are two such data structures,\r
+    g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1.\r
+    This parameter must point to either the g_mss_uart0 or g_mss_uart1\r
+    global data structure defined within the UART driver.\r
+\r
+  @param baud_rate\r
+    The baud_rate parameter specifies the baud rate. It can be specified for\r
+    common baud rates\92 using the following defines:\r
+    \95   MSS_UART_110_BAUD\r
+    \95   MSS_UART_300_BAUD\r
+    \95   MSS_UART_1200_BAUD\r
+    \95   MSS_UART_2400_BAUD\r
+    \95   MSS_UART_4800_BAUD\r
+    \95   MSS_UART_9600_BAUD\r
+    \95   MSS_UART_19200_BAUD\r
+    \95   MSS_UART_38400_BAUD\r
+    \95   MSS_UART_57600_BAUD\r
+    \95   MSS_UART_115200_BAUD\r
+    \95   MSS_UART_230400_BAUD\r
+    \95   MSS_UART_460800_BAUD\r
+    \95   MSS_UART_921600_BAUD\r
+    Alternatively, any nonstandard baud rate can be specified by simply passing\r
+    the actual required baud rate as the value for this parameter.\r
+\r
+  @param line_config\r
+    The line_config parameter is the line configuration specifying the bit length,\r
+    number of stop bits and parity settings. This is a bitwise OR of one value\r
+    from each of the following groups of allowed values:\r
+    \95   One of the following to specify the transmit/receive data bit length:\r
+        MSS_UART_DATA_5_BITS\r
+        MSS_UART_DATA_6_BITS,\r
+        MSS_UART_DATA_7_BITS\r
+        MSS_UART_DATA_8_BITS\r
+    \95   One of the following to specify the parity setting:\r
+        MSS_UART_NO_PARITY\r
+        MSS_UART_EVEN_PARITY\r
+        MSS_UART_ODD_PARITY\r
+        MSS_UART_STICK_PARITY_0\r
+        MSS_UART_STICK_PARITY_1\r
+    \95   One of the following to specify the number of stop bits:\r
+        MSS_UART_ONE_STOP_BIT\r
+        MSS_UART_ONEHALF_STOP_BIT\r
+        MSS_UART_TWO_STOP_BITS\r
+\r
+  @return\r
+    This function does not return a value.\r
+\r
+  Example:\r
+  @code\r
+    #include "mss_uart.h"\r
+\r
+      int main(void)\r
+      {\r
+         MSS_UART_smartcard_init(&g_mss_uart0,\r
+                                 MSS_UART_57600_BAUD,\r
+                                 MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT);\r
+                                 \r
+         return(0);\r
+      }\r
+  @endcode\r
+ */\r
+void \r
+MSS_UART_smartcard_init\r
+(\r
+    mss_uart_instance_t* this_uart, \r
+    uint32_t baud_rate,\r
+    uint8_t line_config\r
+);\r
+\r
+/***************************************************************************//**\r
+  The function MSS_UART_polled_tx() is used to transmit data. It transfers the\r
+  contents of the transmitter data buffer, passed as a function parameter, into\r
+  the UART\92s hardware transmitter FIFO. It returns when the full content of the\r
+  transmit data buffer has been transferred to the UART\92s transmit FIFO. It is\r
+  safe to release or reuse the memory used as the transmitter data buffer once\r
+  this function returns.\r
+\r
+  Note:     This function reads the UART\92s line status register (LSR) to poll\r
+  for the active state of the transmitter holding register empty (THRE) bit\r
+  before transferring data from the data buffer to the transmitter FIFO. It\r
+  transfers data to the transmitter FIFO in blocks of 16 bytes or less and\r
+  allows the FIFO to empty before transferring the next block of data.\r
+\r
+  Note:     The actual transmission over the serial connection will still be\r
+  in progress when this function returns. Use the MSS_UART_get_tx_status()\r
+  function if you need to know when the transmitter is empty.\r
+\r
+  @param this_uart\r
+    The this_uart parameter is a pointer to an mss_uart_instance_t\r
+    structure identifying the MSS UART hardware block that will perform\r
+    the requested function. There are two such data structures,\r
+    g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1.\r
+    This parameter must point to either the g_mss_uart0 or g_mss_uart1\r
+    global data structure defined within the UART driver.\r
+\r
+  @param pbuff\r
+    The pbuff parameter is a pointer to a buffer containing the data to\r
+    be transmitted.\r
+\r
+  @param tx_size\r
+    The tx_size parameter specifies the size, in bytes, of the data to\r
+    be transmitted.\r
+\r
+  @return\r
+    This function does not return a value.\r
+\r
+  Example:\r
+  @code\r
+  #include "mss_uart.h"\r
+\r
+  int main(void)\r
+  {\r
+     uint8_t message[12] = "Hello World";\r
+\r
+     MSS_UART_init(&g_mss_uart0,\r
+                   MSS_UART_57600_BAUD,\r
+                   MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT);\r
+                   \r
+     MSS_UART_polled_tx(&g_mss_uart0, message, sizeof(message));\r
+     \r
+     return(0);\r
+  }\r
+  @endcode\r
+ */\r
+void\r
+MSS_UART_polled_tx\r
+(\r
+    mss_uart_instance_t * this_uart,\r
+    const uint8_t * pbuff,\r
+    uint32_t tx_size\r
+);\r
+\r
+/***************************************************************************//**\r
+  The function MSS_UART_polled_tx_string() is used to transmit a NULL ('\0')\r
+  terminated string. It transfers the text string, from the buffer starting at\r
+  the address pointed to by p_sz_string into the UART\92s hardware transmitter\r
+  FIFO. It returns when the complete string has been transferred to the UART's\r
+  transmit FIFO. It is safe to release or reuse the memory used as the string\r
+  buffer once this function returns.\r
+\r
+  Note:     This function reads the UART\92s line status register (LSR) to poll\r
+  for the active state of the transmitter holding register empty (THRE) bit\r
+  before transferring data from the data buffer to the transmitter FIFO. It\r
+  transfers data to the transmitter FIFO in blocks of 16 bytes or less and\r
+  allows the FIFO to empty before transferring the next block of data.\r
+\r
+  Note:     The actual transmission over the serial connection will still be\r
+  in progress when this function returns. Use the MSS_UART_get_tx_status()\r
+  function if you need to know when the transmitter is empty.\r
+\r
+  @param this_uart\r
+    The this_uart parameter is a pointer to an mss_uart_instance_t\r
+    structure identifying the MSS UART hardware block that will perform\r
+    the requested function. There are two such data structures,\r
+    g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1.\r
+    This parameter must point to either the g_mss_uart0 or g_mss_uart1\r
+    global data structure defined within the UART driver.\r
+\r
+  @param p_sz_string\r
+    The p_sz_string parameter is a pointer to a buffer containing the NULL\r
+    ('\0') terminated string to be transmitted.\r
+\r
+  @return\r
+    This function does not return a value.\r
+\r
+  Example:\r
+  @code\r
+  #include "mss_uart.h"\r
+\r
+  int main(void)\r
+  {\r
+     uint8_t message[12] = "Hello World";\r
+\r
+     MSS_UART_init(&g_mss_uart0,\r
+                   MSS_UART_57600_BAUD,\r
+                   MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT);\r
+                   \r
+     MSS_UART_polled_tx_string(&g_mss_uart0, message);\r
+     \r
+     return(0);\r
+  }\r
+  @endcode\r
+\r
+ */\r
+void\r
+MSS_UART_polled_tx_string\r
+(\r
+    mss_uart_instance_t * this_uart,\r
+    const uint8_t * p_sz_string\r
+);\r
+\r
+\r
+/***************************************************************************//**\r
+  The function MSS_UART_irq_tx() is used to initiate an interrupt-driven\r
+  transmit. It returns immediately after making a note of the transmit buffer\r
+  location and enabling transmit interrupts both at the UART and Cortex-M3 NVIC\r
+  level. This function takes a pointer via the pbuff parameter to a memory\r
+  buffer containing the data to transmit. The memory buffer specified through\r
+  this pointer must remain allocated and contain the data to transmit until\r
+  the transmit completion has been detected through calls to function\r
+  MSS_UART_tx_complete(). The actual transmission over the serial connection\r
+  is still in progress until calls to the MSS_UART_tx_complete() function\r
+  indicate transmit completion.\r
+\r
+  Note:     The MSS_UART_irq_tx() function enables both the transmit holding\r
+  register empty (THRE) interrupt in the UART and the MSS UART instance\r
+  interrupt in the Cortex-M3 NVIC as part of its implementation.\r
+\r
+  Note:     The MSS_UART_irq_tx() function assigns an internal default transmit\r
+  interrupt handler function to the UART\92s THRE interrupt. This interrupt\r
+  handler overrides any custom interrupt handler that you may have previously\r
+  registered using the MSS_UART_set_tx_handler() function.\r
+\r
+  Note:     The MSS_UART_irq_tx() function\92s default transmit interrupt\r
+  handler disables the UART\92s THRE interrupt when all of the data has\r
+  been transferred to the UART's transmit FIFO.\r
+\r
+\r
+  @param this_uart\r
+    The this_uart parameter is a pointer to an mss_uart_instance_t\r
+    structure identifying the MSS UART hardware block that will perform\r
+    the requested function. There are two such data structures,\r
+    g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1.\r
+    This parameter must point to either the g_mss_uart0 or g_mss_uart1\r
+    global data structure defined within the UART driver.\r
+\r
+  @param pbuff\r
+    The pbuff parameter is a pointer to a buffer containing the data\r
+    to be transmitted.\r
+\r
+  @param tx_size\r
+    The tx_size parameter specifies the size, in bytes, of the data\r
+    to be transmitted.\r
+\r
+  @return\r
+    This function does not return a value.\r
+\r
+  Example:\r
+  @code\r
+  #include "mss_uart.h"\r
+\r
+  int main(void)\r
+  {\r
+     uint8_t tx_buff[10] = "abcdefghi";\r
+     \r
+     MSS_UART_init(&g_mss_uart0,\r
+                   MSS_UART_57600_BAUD,\r
+                   MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT);\r
+                   \r
+     MSS_UART_irq_tx(&g_mss_uart0, tx_buff, sizeof(tx_buff));\r
+     \r
+     while(0 == MSS_UART_tx_complete(&g_mss_uart0))\r
+     {\r
+         ;\r
+     }\r
+     return(0);\r
+  }\r
+  @endcode\r
+ */\r
+void\r
+MSS_UART_irq_tx\r
+(\r
+    mss_uart_instance_t * this_uart,\r
+    const uint8_t * pbuff,\r
+    uint32_t tx_size\r
+);\r
+\r
+/***************************************************************************//**\r
+  The MSS_UART_tx_complete() function is used to find out if the interrupt-driven\r
+  transmit previously initiated through a call to MSS_UART_irq_tx() is complete.\r
+  This is typically used to find out when it is safe to reuse or release the\r
+  memory buffer holding transmit data.\r
+\r
+  Note:     The transfer of all of the data from the memory buffer to the UART\92s\r
+  transmit FIFO and the actual transmission over the serial connection are both\r
+  complete when a call to the MSS_UART_tx_complete() function indicates transmit\r
+  completion.\r
+\r
+  @param this_uart\r
+    The this_uart parameter is a pointer to an mss_uart_instance_t\r
+    structure identifying the MSS UART hardware block that will perform\r
+    the requested function. There are two such data structures,\r
+    g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1.\r
+    This parameter must point to either the g_mss_uart0 or g_mss_uart1\r
+    global data structure defined within the UART driver.\r
+\r
+  @return\r
+    This function return a non-zero value if transmit has completed, otherwise\r
+    it returns zero.\r
+\r
+  Example:\r
+    See the MSS_UART_irq_tx() function for an example that uses the\r
+    MSS_UART_tx_complete() function.\r
+ */\r
+int8_t\r
+MSS_UART_tx_complete\r
+(\r
+   mss_uart_instance_t * this_uart\r
+);\r
+\r
+/***************************************************************************//**\r
+  The MSS_UART_get_rx() function reads the content of the UART receiver\92s FIFO\r
+  and stores it in the receive buffer that is passed via the rx_buff function\r
+  parameter. It copies either the full contents of the FIFO into the receive\r
+  buffer, or just enough data from the FIFO to fill the receive buffer,\r
+  dependent upon the size of the receive buffer passed by the buff_size\r
+  parameter. The MSS_UART_get_rx() function returns the number of bytes copied\r
+  into the receive buffer .This function is non-blocking and will return 0\r
+  immediately if no data has been received.\r
+\r
+  Note:     The MSS_UART_get_rx() function reads and accumulates the receiver\r
+  status of the MSS UART instance before reading each byte from the receiver's\r
+  data register/FIFO. This allows the driver to maintain a sticky record of any\r
+  receiver errors that occur as the UART receives each data byte; receiver\r
+  errors would otherwise be lost after each read from the receiver's data register.\r
+  A call to the MSS_UART_get_rx_status() function returns any receiver errors\r
+  accumulated during the execution of the MSS_UART_get_rx() function.\r
+\r
+  Note:     If you need to read the error status for each byte received, set\r
+  the buff_size to 1 and read the receive line error status for each byte\r
+  using the MSS_UART_get_rx_status() function.\r
+  The MSS_UART_get_rx() function can be used in polled mode, where it is called\r
+  at regular intervals to find out if any data has been received, or in interrupt\r
+  driven-mode, where it is called as part of a receive handler that is called\r
+  by the driver as a result of data being received.\r
+\r
+  Note:     In interrupt driven mode you should call the MSS_UART_get_rx()\r
+  function as part of the receive handler function that you register with\r
+  the MSS UART driver through a call to MSS_UART_set_rx_handler().\r
+\r
+  @param this_uart\r
+    The this_uart parameter is a pointer to an mss_uart_instance_t\r
+    structure identifying the MSS UART hardware block that will perform\r
+    the requested function. There are two such data structures,\r
+    g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1.\r
+    This parameter must point to either the g_mss_uart0 or g_mss_uart1\r
+    global data structure defined within the UART driver.\r
+\r
+  @param rx_buff\r
+    The rx_buff parameter is a pointer to a buffer where the received\r
+    data is copied.\r
+\r
+  @param buff_size\r
+    The buff_size parameter specifies the size of the receive buffer in bytes.\r
+\r
+  @return\r
+    This function returns the number of bytes that were copied into the\r
+    rx_buff buffer. It returns 0 if no data has been received.\r
+\r
+  Polled mode example:\r
+  @code\r
+   int main( void )\r
+   {\r
+      uint8_t rx_buff[RX_BUFF_SIZE];\r
+      uint32_t rx_idx  = 0;\r
+\r
+      MSS_UART_init(&g_mss_uart0,\r
+                    MSS_UART_57600_BAUD,\r
+                    MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT);\r
+                    \r
+      while(1)\r
+      {\r
+          rx_size = MSS_UART_get_rx(&g_mss_uart0, rx_buff, sizeof(rx_buff));\r
+          if(rx_size > 0)\r
+          {\r
+              process_rx_data(rx_buff, rx_size);\r
+          }\r
+          task_a();\r
+          task_b();\r
+      }\r
+      return 0;\r
+   }\r
+  @endcode\r
+\r
+  Interrupt driven example:\r
+  @code\r
+   int main( void )\r
+   {\r
+      MSS_UART_init(&g_mss_uart1,\r
+                    MSS_UART_57600_BAUD,\r
+                    MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT);\r
+                    \r
+      MSS_UART_set_rx_handler(&g_mss_uart1,\r
+                              uart1_rx_handler,\r
+                              MSS_UART_FIFO_SINGLE_BYTE);\r
+      \r
+      while(1)\r
+      {\r
+          task_a();\r
+          task_b();\r
+      }\r
+      return 0;\r
+   }\r
+\r
+   void uart1_rx_handler(mss_uart_instance_t * this_uart)\r
+   {\r
+      uint8_t rx_buff[RX_BUFF_SIZE];\r
+      uint32_t rx_idx  = 0;\r
+      rx_size = MSS_UART_get_rx(this_uart, rx_buff, sizeof(rx_buff));\r
+      process_rx_data(rx_buff, rx_size);\r
+   }\r
+  @endcode\r
+ */\r
+size_t\r
+MSS_UART_get_rx\r
+(\r
+   mss_uart_instance_t * this_uart,\r
+   uint8_t * rx_buff,\r
+   size_t buff_size\r
+);\r
+\r
+/***************************************************************************//**\r
+  The MSS_UART_set_rx_handler() function is used to register a receive handler\r
+  function that is called by the driver when a UART receive data available (RDA)\r
+  interrupt occurs. You must create and register the receive handler function\r
+  to suit your application and it must include a call to the MSS_UART_get_rx()\r
+  function to actually read the received data.\r
+\r
+  Note:     The MSS_UART_set_rx_handler() function enables both the RDA\r
+  interrupt in the UART and the MSS UART instance interrupt in the Cortex-M3\r
+  NVIC as part\r
+  of its implementation.\r
+\r
+  Note:     You can disable the RDA interrupt once the data is received by\r
+  calling the MSS_UART_disable_irq() function. This is your choice and is\r
+  dependent upon your application.\r
+\r
+\r
+  @param this_uart\r
+    The this_uart parameter is a pointer to an mss_uart_instance_t\r
+    structure identifying the MSS UART hardware block that will perform\r
+    the requested function. There are two such data structures,\r
+    g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1.\r
+    This parameter must point to either the g_mss_uart0 or g_mss_uart1\r
+    global data structure defined within the UART driver.\r
+\r
+  @param handler\r
+    The handler parameter is a pointer to a receive interrupt handler function\r
+    provided by your application that will be called as a result of a UART RDA\r
+    interrupt. This handler function must be of type mss_uart_irq_handler_t.\r
+\r
+  @param trigger_level\r
+    The trigger_level parameter is the receive FIFO trigger level. This\r
+    specifies the number of bytes that must be received before the UART\r
+    triggers an RDA interrupt.\r
+\r
+  @return\r
+    This function does not return a value.\r
+\r
+  Example:\r
+  @code\r
+  #include "mss_uart.h"\r
+\r
+  #define RX_BUFF_SIZE    64\r
+\r
+  uint8_t g_rx_buff[RX_BUFF_SIZE];\r
+\r
+  void uart0_rx_handler(mss_uart_instance_t * this_uart)\r
+  {\r
+      MSS_UART_get_rx(this_uart, &g_rx_buff[g_rx_idx], sizeof(g_rx_buff));\r
+  }\r
+\r
+  int main(void)\r
+  {\r
+      MSS_UART_init(&g_mss_uart0,\r
+                    MSS_UART_57600_BAUD,\r
+                    MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT);\r
+                    \r
+      MSS_UART_set_rx_handler(&g_mss_uart0,\r
+                              uart0_rx_handler,\r
+                              MSS_UART_FIFO_SINGLE_BYTE);\r
+                              \r
+      while(1)\r
+      {\r
+         ;\r
+      }\r
+      return(0);\r
+   }\r
+  @endcode\r
+ */\r
+void\r
+MSS_UART_set_rx_handler\r
+(\r
+    mss_uart_instance_t *       this_uart,\r
+    mss_uart_irq_handler_t          handler,\r
+    mss_uart_rx_trig_level_t    trigger_level\r
+);\r
+\r
+/***************************************************************************//**\r
+  The MSS_UART_set_loopback() function is used to locally loopback the Tx and\r
+  Rx lines of a UART. This is not to be confused with the loopback of UART0\r
+  to UART1, which can be achieved through the microcontroller subsystem\92s\r
+  system registers.\r
+\r
+  @param this_uart\r
+    The this_uart parameter is a pointer to an mss_uart_instance_t\r
+    structure identifying the MSS UART hardware block that will perform\r
+    the requested function. There are two such data structures,\r
+    g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1.\r
+    This parameter must point to either the g_mss_uart0 or g_mss_uart1\r
+    global data structure defined within the UART driver.\r
+\r
+  @param loopback\r
+    The loopback parameter indicates whether or not the UART\92s transmit\r
+    and receive lines should be looped back. Allowed values are as follows:\r
+      - MSS_UART_LOCAL_LOOPBACK_ON\r
+      - MSS_UART_LOCAL_LOOPBACK_OFF \r
+      - MSS_UART_REMOTE_LOOPBACK_ON\r
+      - MSS_UART_REMOTE_LOOPBACK_OFF \r
+      - MSS_UART_AUTO_ECHO_ON\r
+      - MSS_UART_AUTO_ECHO_OFF\r
+      \r
+  @return\r
+    This function does not return a value.\r
+\r
+  Example:\r
+  @code\r
+    MSS_UART_init(&g_mss_uart0,\r
+                  MSS_UART_57600_BAUD,\r
+                  MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT); \r
+\r
+      MSS_UART_set_loopback(&g_mss_uart0, MSS_UART_LOCAL_LOOPBACK_OFF);\r
+  @endcode\r
+ */\r
+void\r
+MSS_UART_set_loopback\r
+(\r
+    mss_uart_instance_t *   this_uart,\r
+    mss_uart_loopback_t     loopback\r
+);\r
+\r
+/***************************************************************************//**\r
+  The MSS_UART_enable_irq() function enables the MSS UART interrupts specified\r
+  by the irq_mask parameter. The irq_mask parameter identifies the MSS UART\r
+  interrupts by bit position, as defined in the interrupt enable register (IER)\r
+  of MSS UART. The MSS UART interrupts and their identifying irq_mask bit\r
+  positions are as follows:\r
+  When an irq_mask bit position is set to 1, this function enables the\r
+  corresponding MSS UART interrupt in the IER register. When an irq_mask bit\r
+  position is set to 0, the corresponding interrupt\92s state remains unchanged in\r
+  the IER register.\r
+  Note: The MSS_UART_enable_irq() function also enables the MSS UART instance\r
+        interrupt in the Cortex-M3 NVIC.\r
+        \r
+  @param this_uart\r
+    The this_uart parameter is a pointer to an mss_uart_instance_t structure\r
+    identifying the MSS UART hardware block that will perform the requested\r
+    function. There are two such data structures, g_mss_uart0 and g_mss_uart1,\r
+    associated with MSS UART0 and MSS UART1. This parameter must point to either\r
+    the g_mss_uart0 or g_mss_uart1 global data structure defined within the UART\r
+    driver.\r
+\r
+  @param irq_mask\r
+    The irq_mask parameter is used to select which of the MSS UART\92s interrupts\r
+    you want to enable. The allowed value for the irq_mask parameter is one of\r
+    the following constants or a bitwise OR of more than one:\r
+      - MSS_UART_RBF_IRQ               (bit mask = 0x001)\r
+      - MSS_UART_TBE_IRQ               (bit mask = 0x002)\r
+      - MSS_UART_LS_IRQ                (bit mask = 0x004)\r
+      - MSS_UART_MS_IRQ                (bit mask = 0x008)\r
+      - MSS_UART_RTO_IRQ               (bit mask = 0x010)\r
+      - MSS_UART_NACK_IRQ      (bit mask = 0x020)\r
+      - MSS_UART_PIDPE_IRQ     (bit mask = 0x040)\r
+      - MSS_UART_LINB_IRQ              (bit mask = 0x080)\r
+      - MSS_UART_LINS_IRQ              (bit mask = 0x100)\r
+      \r
+  @return\r
+     This function does not return a value.\r
+\r
+  Example:\r
+  @code\r
+    MSS_UART_enable_irq(&g_mss_uart0,(MSS_UART_RBF_IRQ | MSS_UART_TBE_IRQ));\r
+  @endcode\r
+ */\r
+void\r
+MSS_UART_enable_irq\r
+(\r
+    mss_uart_instance_t * this_uart,\r
+    mss_uart_irq_t irq_mask\r
+);\r
+\r
+/***************************************************************************//**\r
+  The MSS_UART_disable_irq() function disables the MSS UART interrupts specified\r
+  by the irq_mask parameter. The irq_mask parameter identifies the MSS UART\r
+  interrupts by bit position, as defined in the interrupt enable register (IER)\r
+  of MSS UART. The MSS UART interrupts and their identifying bit positions are\r
+  as follows:\r
+  When an irq_mask bit position is set to 1, this function disables the\r
+  corresponding MSS UART interrupt in the IER register. When an irq_mask bit\r
+  position is set to 0, the corresponding interrupt\92s state remains unchanged in\r
+  the IER register.\r
+  Note: If you disable all four of the UART\92s interrupts, the\r
+        MSS_UART_disable_irq() function also disables the MSS UART instance\r
+        interrupt in the Cortex-M3 NVIC.\r
+        \r
+  @param this_uart\r
+    The this_uart parameter is a pointer to an mss_uart_instance_t\r
+    structure identifying the MSS UART hardware block that will perform\r
+    the requested function. There are two such data structures,\r
+    g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1.\r
+    This parameter must point to either the g_mss_uart0 or g_mss_uart1\r
+    global data structure defined within the UART driver.\r
+\r
+  @param irq_mask\r
+    The irq_mask parameter is used to select which of the MSS UART\92s interrupts\r
+    you want to disable. The allowed value for the irq_mask parameter is one of\r
+    the following constants or a bitwise OR of more than one:\r
+      - MSS_UART_RBF_IRQ    (bit mask = 0x001)\r
+      - MSS_UART_TBE_IRQ    (bit mask = 0x002)\r
+      - MSS_UART_LS_IRQ     (bit mask = 0x004)\r
+      - MSS_UART_MS_IRQ     (bit mask = 0x008)\r
+      - MSS_UART_RTO_IRQ    (bit mask = 0x010)\r
+      - MSS_UART_NACK_IRQ   (bit mask = 0x020)\r
+      - MSS_UART_PIDPE_IRQ  (bit mask = 0x040)\r
+      - MSS_UART_LINB_IRQ   (bit mask = 0x080)\r
+      - MSS_UART_LINS_IRQ   (bit mask = 0x100)\r
+      \r
+  @return\r
+     This function does not return a value.\r
+\r
+  Example:\r
+  @code\r
+    MSS_UART_disable_irq(&g_mss_uart0, (MSS_UART_RBF_IRQ | MSS_UART_TBE_IRQ));\r
+  @endcode\r
+ */\r
+void\r
+MSS_UART_disable_irq\r
+(\r
+    mss_uart_instance_t * this_uart,\r
+    mss_uart_irq_t irq_mask\r
+);\r
+\r
+/***************************************************************************//**\r
+  The MSS_UART_set_pidpei_handler() function is used assign a custom interrupt \r
+  handler for the PIDPEI (PID parity error interrupt) when the MSS UART is \r
+  operating in LIN mode.\r
+\r
+  @param this_uart\r
+    The this_uart parameter is a pointer to an mss_uart_instance_t\r
+    structure identifying the MSS UART hardware block that will perform\r
+    the requested function. There are two such data structures,\r
+    g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1.\r
+    This parameter must point to either the g_mss_uart0 or g_mss_uart1\r
+    global data structure defined within the UART driver.\r
+\r
+  @param handler\r
+    The handler parameter is the pointer to the custom handler function. \r
+    This parameter is of type mss_uart_irq_handler_t.\r
+\r
+  @return\r
+    This function does not return a value.\r
+\r
+  Example:\r
+  @code\r
+    MSS_UART_ set_pidpei_handler(&g_mss_uart0, my_pidpei_handler);\r
+  @endcode\r
+ */\r
+void\r
+MSS_UART_set_pidpei_handler\r
+(\r
+    mss_uart_instance_t * this_uart,\r
+    mss_uart_irq_handler_t handler\r
+);\r
+\r
+/***************************************************************************//**\r
+  The MSS_UART_set_linbreak_handler () function is used assign a custom \r
+  interrupt handler for the LIN Break detection interrupt  when the MSS UART \r
+  is operating in LIN mode.\r
+\r
+  @param this_uart\r
+    The this_uart parameter is a pointer to an mss_uart_instance_t\r
+    structure identifying the MSS UART hardware block that will perform\r
+    the requested function. There are two such data structures,\r
+    g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1.\r
+    This parameter must point to either the g_mss_uart0 or g_mss_uart1\r
+    global data structure defined within the UART driver.\r
+\r
+  @param handler\r
+    The handler parameter is the pointer to the custom handler function. \r
+    This parameter is of type mss_uart_irq_handler_t.\r
+\r
+  @return\r
+    This function does not return a value.\r
+  Example:\r
+  @code\r
+    MSS_UART_set_linbreak_handler(&g_mss_uart0, my_break_handler);\r
+  @endcode\r
+ */\r
+void\r
+MSS_UART_set_linbreak_handler\r
+(\r
+    mss_uart_instance_t * this_uart,\r
+    mss_uart_irq_handler_t handler\r
+);\r
+\r
+/***************************************************************************//**\r
+  The MSS_UART_set_linsync_handler() function is used assign a custom interrupt \r
+  handler for the LIN Sync character detection interrupt  when the MSS UART \r
+  is operating in LIN mode.\r
+\r
+  @param this_uart\r
+    The this_uart parameter is a pointer to an mss_uart_instance_t\r
+    structure identifying the MSS UART hardware block that will perform\r
+    the requested function. There are two such data structures,\r
+    g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1.\r
+    This parameter must point to either the g_mss_uart0 or g_mss_uart1\r
+    global data structure defined within the UART driver.\r
+\r
+  @param handler\r
+    The handler parameter is the pointer to the custom handler function. \r
+    This parameter is of type mss_uart_irq_handler_t.\r
+\r
+  @return\r
+    This function does not return a value.\r
+  Example:\r
+  @code\r
+    MSS_UART_set_linsync_handler(&g_mss_uart0, my_linsync_handler);\r
+  @endcode\r
+ */\r
+void\r
+MSS_UART_set_linsync_handler\r
+(\r
+    mss_uart_instance_t * this_uart,\r
+    mss_uart_irq_handler_t handler\r
+);\r
+\r
+/***************************************************************************//**\r
+  The MSS_UART_set_nack_handler() function is used assign a custom interrupt \r
+  handler for the NACK character detection interrupt  when the MSS UART \r
+  is operating in Smartcard mode.\r
+\r
+  @param this_uart\r
+    The this_uart parameter is a pointer to an mss_uart_instance_t\r
+    structure identifying the MSS UART hardware block that will perform\r
+    the requested function. There are two such data structures,\r
+    g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1.\r
+    This parameter must point to either the g_mss_uart0 or g_mss_uart1\r
+    global data structure defined within the UART driver.\r
+\r
+  @param handler\r
+    The handler parameter is the pointer to the custom handler function. \r
+    This parameter is of type mss_uart_irq_handler_t.\r
+\r
+  @return\r
+    This function does not return a value.\r
+  Example:\r
+  @code\r
+    MSS_UART_set_nack_handler(&g_mss_uart0, my_nack_handler);\r
+  @endcode\r
+ */\r
+void\r
+MSS_UART_set_nack_handler\r
+(\r
+    mss_uart_instance_t * this_uart,\r
+    mss_uart_irq_handler_t handler\r
+);\r
+\r
+/***************************************************************************//**\r
+  The MSS_UART_set_rx_timeout_handler() function is used assign a custom \r
+  interrupt handler for the receiver timeout interrupt  when the MSS UART is \r
+  operating in mode. It finds application in IrDA mode of operation.\r
+\r
+  @param this_uart\r
+    The this_uart parameter is a pointer to an mss_uart_instance_t\r
+    structure identifying the MSS UART hardware block that will perform\r
+    the requested function. There are two such data structures,\r
+    g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1.\r
+    This parameter must point to either the g_mss_uart0 or g_mss_uart1\r
+    global data structure defined within the UART driver.\r
+\r
+  @param handler\r
+    The handler parameter is the pointer to the custom handler function. \r
+    This parameter is of type mss_uart_irq_handler_t.\r
+\r
+  @return\r
+    This function does not return a value.\r
+  Example:\r
+  @code\r
+    MSS_UART_set_rx_timeout_handler(&g_mss_uart0, my_rxtimeout_handler);\r
+  @endcode\r
+ */\r
+void\r
+MSS_UART_set_rx_timeout_handler\r
+(\r
+    mss_uart_instance_t * this_uart,\r
+    mss_uart_irq_handler_t handler\r
+);\r
+\r
+/***************************************************************************//**\r
+  The MSS_UART_set_rxstatus_handler() function is used to register a receiver\r
+  status handler function that is called by the driver when a UART receiver\r
+  line status (RLS) interrupt occurs. You must create and register the handler\r
+  function to suit your application.\r
+\r
+  Note:     The MSS_UART_set_rxstatus_handler() function enables both the RLS\r
+  interrupt in the UART and the MSS UART instance interrupt in the Cortex-M3\r
+  NVIC as part of its implementation.\r
+\r
+  Note:     You can disable the RLS interrupt when required by calling the\r
+  MSS_UART_disable_irq() function. This is your choice and is dependent upon\r
+  your application.\r
+\r
+  @param this_uart\r
+    The this_uart parameter is a pointer to an mss_uart_instance_t\r
+    structure identifying the MSS UART hardware block that will perform\r
+    the requested function. There are two such data structures,\r
+    g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1.\r
+    This parameter must point to either the g_mss_uart0 or g_mss_uart1\r
+    global data structure defined within the UART driver.\r
+\r
+  @param handler\r
+     The handler parameter is a pointer to a receiver line status interrupt\r
+     handler function provided by your application that will be called as a\r
+     result of a UART RLS interrupt. This handler function must be of type\r
+     mss_uart_irq_handler_t.\r
+\r
+  @return\r
+     This function does not return a value.\r
+\r
+  Example:\r
+  @code\r
+  #include "mss_uart.h"\r
+\r
+  void uart_rxsts_handler(mss_uart_instance_t * this_uart)\r
+  {\r
+    uint8_t status;\r
+    status = MSS_UART_get_rx_status(this_uart);\r
+    if(status & MSS_UART_OVERUN_ERROR)\r
+    {\r
+        discard_rx_data();\r
+    }\r
+  }\r
+\r
+  int main(void)\r
+  {\r
+    MSS_UART_init( &g_mss_uart0,\r
+                   MSS_UART_57600_BAUD,\r
+                   MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY |\r
+                                       MSS_UART_ONE_STOP_BIT );\r
+                                       \r
+    MSS_UART_set_rxstatus_handler(&g_mss_uart0, uart_rxsts_handler);\r
+\r
+    while(1)\r
+    {\r
+        ;\r
+    }\r
+    return(0);\r
+  }\r
+  @endcode\r
+ */\r
+void\r
+MSS_UART_set_rxstatus_handler\r
+(\r
+    mss_uart_instance_t * this_uart,\r
+    mss_uart_irq_handler_t handler\r
+);\r
+\r
+/***************************************************************************//**\r
+  The MSS_UART_set_tx_handler() function is used to register a transmit handler\r
+  function that is called by the driver when a UART transmit holding register\r
+  empty (THRE) interrupt occurs. You must create and register the transmit\r
+  handler function to suit your application. You can use the\r
+  MSS_UART_fill_tx_fifo() function in your transmit handler function to\r
+  write data to the transmitter.\r
+\r
+  Note:     The MSS_UART_set_tx_handler() function enables both the THRE\r
+  interrupt in the UART and the MSS UART instance interrupt in the Cortex-M3\r
+  NVIC as part of its implementation.\r
+\r
+  Note:     You can disable the THRE interrupt when required by calling the\r
+  MSS_UART_disable_irq() function. This is your choice and is dependent upon\r
+  your application.\r
+\r
+  Note:     The MSS_UART_irq_tx() function does not use the transmit handler\r
+  function that you register with the MSS_UART_set_tx_handler() function.\r
+  It uses its own internal THRE interrupt handler function that overrides\r
+  any custom interrupt handler that you register using the\r
+  MSS_UART_set_tx_handler() function.\r
+\r
+  @param this_uart\r
+    The this_uart parameter is a pointer to an mss_uart_instance_t\r
+    structure identifying the MSS UART hardware block that will perform\r
+    the requested function. There are two such data structures,\r
+    g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1.\r
+    This parameter must point to either the g_mss_uart0 or g_mss_uart1\r
+    global data structure defined within the UART driver.\r
+\r
+   @param handler\r
+     The handler parameter is a pointer to a transmit interrupt handler\r
+     function provided by your application that will be called as a result\r
+     of a UART THRE interrupt. This handler function must be of type\r
+     mss_uart_irq_handler_t.\r
+\r
+   @return\r
+     This function does not return a value.\r
+\r
+   Example:\r
+   @code\r
+    #include "mss_uart.h"\r
+\r
+    uint8_t * g_tx_buffer;\r
+    size_t g_tx_size = 0;\r
+\r
+    void uart_tx_handler(mss_uart_instance_t * this_uart)\r
+    {\r
+        size_t size_in_fifo;\r
+        size_in_fifo = MSS_UART_fill_tx_fifo(this_uart,\r
+                                             (const uint8_t *)g_tx_buffer,\r
+                                             g_tx_size);\r
+                                             \r
+        if(size_in_fifo  ==  g_tx_size)\r
+        {\r
+            g_tx_size = 0;\r
+            MSS_UART_disable_irq(this_uart, MSS_UART_TBE_IRQ);\r
+        }\r
+        else\r
+        {\r
+            g_tx_buffer = &g_tx_buffer[size_in_fifo];\r
+            g_tx_size = g_tx_size - size_in_fifo;\r
+        }\r
+    }\r
+\r
+    int main(void)\r
+    {\r
+        uint8_t message[12] = "Hello world";\r
+\r
+        MSS_UART_init(&g_mss_uart0,\r
+                      MSS_UART_57600_BAUD,\r
+                      MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY |\r
+                                           MSS_UART_ONE_STOP_BIT);\r
+\r
+        g_tx_buffer = message;\r
+        g_tx_size = sizeof(message);\r
+\r
+        MSS_UART_set_tx_handler(&g_mss_uart0, uart_tx_handler);\r
+\r
+        while(1)\r
+        {\r
+            ;\r
+        }\r
+        return(0);\r
+    }\r
+   @endcode\r
+ */\r
+void\r
+MSS_UART_set_tx_handler\r
+(\r
+    mss_uart_instance_t * this_uart,\r
+    mss_uart_irq_handler_t handler\r
+);\r
+\r
+/***************************************************************************//**\r
+  The MSS_UART_set_modemstatus_handler() function is used to register a modem\r
+  status handler function that is called by the driver when a UART modem status\r
+  (MS) interrupt occurs. You must create and register the handler function to\r
+  suit your application.\r
+\r
+  Note:     The MSS_UART_set_modemstatus_handler() function enables both the MS\r
+  interrupt in the UART and the MSS UART instance interrupt in the Cortex-M3 NVIC\r
+  as part of its implementation.\r
+\r
+  Note:     You can disable the MS interrupt when required by calling the\r
+  MSS_UART_disable_irq() function. This is your choice and is dependent\r
+  upon your application.\r
+\r
+  @param this_uart\r
+    The this_uart parameter is a pointer to an mss_uart_instance_t\r
+    structure identifying the MSS UART hardware block that will perform\r
+    the requested function. There are two such data structures,\r
+    g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1.\r
+    This parameter must point to either the g_mss_uart0 or g_mss_uart1\r
+    global data structure defined within the UART driver.\r
+\r
+   @param handler\r
+     The handler parameter is a pointer to a modem status interrupt handler\r
+     function provided by your application that will be called as a result\r
+     of a UART MS interrupt. This handler function must be of type\r
+     mss_uart_irq_handler_t.\r
+\r
+   @return\r
+     This function does not return a value.\r
+\r
+   Example:\r
+   @code\r
+   #include "mss_uart.h"\r
+\r
+   void uart_modem_handler(mss_uart_instance_t * this_uart)\r
+   {\r
+     uint8_t status;\r
+     status = MSS_UART_get_modem_status(this_uart);\r
+     if(status & MSS_UART_CTS)\r
+     {\r
+        uart_cts_handler();\r
+     }\r
+   }\r
+\r
+   int main(void)\r
+   {\r
+      MSS_UART_init(&g_mss_uart0,\r
+                    MSS_UART_57600_BAUD,\r
+                    MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY |\r
+                                       MSS_UART_ONE_STOP_BIT);\r
+      MSS_UART_set_modemstatus_handler(&g_mss_uart0, uart_modem_handler);\r
+\r
+      while(1)\r
+      {\r
+        ;\r
+      }\r
+      return(0);\r
+   }\r
+   @endcode\r
+ */\r
+\r
+void\r
+MSS_UART_set_modemstatus_handler\r
+(\r
+    mss_uart_instance_t * this_uart,\r
+    mss_uart_irq_handler_t handler\r
+);\r
+\r
+/***************************************************************************//**\r
+  The MSS_UART_fill_tx_fifo() function fills the UART's hardware transmitter\r
+  FIFO with the data found in the transmitter buffer that is passed via the\r
+  tx_buffer function parameter. If the transmitter FIFO is not empty when\r
+  the function is called, the function returns immediately without transferring\r
+  any data to the FIFO; otherwise, the function transfers data from the\r
+  transmitter buffer to the FIFO until it is full or until the complete\r
+  contents of the transmitter buffer have been copied into the FIFO. The\r
+  function returns the number of bytes copied into the UART's transmitter FIFO.\r
+\r
+  Note:     This function reads the UART\92s line status register (LSR) to check\r
+  for the active state of the transmitter holding register empty (THRE) bit\r
+  before transferring data from the data buffer to the transmitter FIFO. If\r
+  THRE is 0, the function returns immediately, without transferring any data\r
+  to the FIFO. If THRE is 1, the function transfers up to 16 bytes of data\r
+  to the FIFO and then returns.\r
+\r
+  Note:     The actual transmission over the serial connection will still be\r
+  in progress when this function returns. Use the MSS_UART_get_tx_status()\r
+  function if you need to know when the transmitter is empty.\r
+\r
+  @param this_uart\r
+    The this_uart parameter is a pointer to an mss_uart_instance_t\r
+    structure identifying the MSS UART hardware block that will perform\r
+    the requested function. There are two such data structures,\r
+    g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1.\r
+    This parameter must point to either the g_mss_uart0 or g_mss_uart1\r
+    global data structure defined within the UART driver.\r
+\r
+  @param tx_buffer\r
+    The tx_buffer parameter is a pointer to a buffer containing the data\r
+    to be transmitted.\r
+\r
+  @param tx_size\r
+    The tx_size parameter is the size in bytes, of the data to be transmitted.\r
+\r
+  @return\r
+    This function returns the number of bytes copied into the UART's\r
+    transmitter FIFO.\r
+\r
+  Example:\r
+  @code\r
+     void send_using_interrupt(uint8_t * pbuff, size_t tx_size)\r
+     {\r
+        size_t size_in_fifo;\r
+        size_in_fifo = MSS_UART_fill_tx_fifo(&g_mss_uart0, pbuff, tx_size);\r
+     }\r
+  @endcode\r
+ */\r
+size_t\r
+MSS_UART_fill_tx_fifo\r
+(\r
+    mss_uart_instance_t * this_uart,\r
+    const uint8_t * tx_buffer,\r
+    size_t tx_size\r
+);\r
+\r
+/***************************************************************************//**\r
+  The MSS_UART_get_rx_status() function returns the receiver error status of the\r
+  MSS UART instance. It reads both the current error status of the receiver from\r
+  the UART\92s line status register (LSR) and the accumulated error status from\r
+  preceding calls to the MSS_UART_get_rx() function, and it combines them using\r
+  a bitwise OR. It returns the cumulative overrun, parity, framing, break and\r
+  FIFO error status of the receiver, since the previous call to\r
+  MSS_UART_get_rx_status(), as an 8-bit encoded value.\r
+\r
+  Note:     The MSS_UART_get_rx() function reads and accumulates the receiver\r
+  status of the MSS UART instance before reading each byte from the receiver\92s\r
+  data register/FIFO. The driver maintains a sticky record of the cumulative\r
+  receiver error status, which persists after the MSS_UART_get_rx() function\r
+  returns. The MSS_UART_get_rx_status() function clears the driver\92s sticky\r
+  receiver error record before returning.\r
+\r
+  Note:     The driver\92s transmit functions also read the line status\r
+  register (LSR) as part of their implementation. When the driver reads the\r
+  LSR, the UART clears any active receiver error bits in the LSR. This could\r
+  result in the driver losing receiver errors. To avoid any loss of receiver\r
+  errors, the transmit functions also update the driver\92s sticky record of the\r
+  cumulative receiver error status whenever they read the LSR.\r
+\r
+  @param this_uart\r
+    The this_uart parameter is a pointer to an mss_uart_instance_t\r
+    structure identifying the MSS UART hardware block that will perform\r
+    the requested function. There are two such data structures,\r
+    g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1.\r
+    This parameter must point to either the g_mss_uart0 or g_mss_uart1\r
+    global data structure defined within the UART driver.\r
+\r
+  @return\r
+    This function returns the UART\92s receiver error status as an 8-bit unsigned\r
+    integer. The returned value is 0 if no receiver errors occurred. The driver\r
+    provides a set of bit mask constants that should be compared with and/or\r
+    used to mask the returned value to determine the receiver error status.\r
+    When the return value is compared to the following bit masks, a non-zero\r
+    result indicates that the corresponding error occurred:\r
+        \95   MSS_UART_OVERRUN_ERROR      (bit mask = 0x02)\r
+        \95   MSS_UART_PARITY_ERROR       (bit mask = 0x04)\r
+        \95   MSS_UART_FRAMING_ERROR      (bit mask = 0x08)\r
+        \95   MSS_UART_BREAK_ERROR        (bit mask = 0x10)\r
+        \95   MSS_UART_FIFO_ERROR     (bit mask = 0x80)\r
+    When the return value is compared to the following bit mask, a non-zero\r
+    result indicates that no error occurred:\r
+        \95   MSS_UART_NO_ERROR       (bit mask = 0x00)\r
+    Upon unsuccessful execution, this function returns:\r
+        \95   MSS_UART_INVALID_PARAM      (bit mask = 0xFF)\r
+\r
+  Example:\r
+  @code\r
+    uint8_t rx_data[MAX_RX_DATA_SIZE];\r
+    uint8_t err_status;\r
+    err_status = MSS_UART_get_rx_status(&g_mss_uart0);\r
+\r
+    if(MSS_UART_NO_ERROR == err_status)\r
+    {\r
+       rx_size = MSS_UART_get_rx(&g_mss_uart0, rx_data, MAX_RX_DATA_SIZE);\r
+    }\r
+  @endcode\r
+ */\r
+uint8_t\r
+MSS_UART_get_rx_status\r
+(\r
+    mss_uart_instance_t * this_uart\r
+);\r
+\r
+/***************************************************************************//**\r
+  The MSS_UART_get_modem_status() function returns the modem status of the\r
+  MSS UART instance. It reads the modem status register (MSR) and returns\r
+  the 8 bit value. The bit encoding of the returned value is exactly the\r
+  same as the definition of the bits in the MSR.\r
+\r
+  @param this_uart\r
+    The this_uart parameter is a pointer to an mss_uart_instance_t\r
+    structure identifying the MSS UART hardware block that will perform\r
+    the requested function. There are two such data structures,\r
+    g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1.\r
+    This parameter must point to either the g_mss_uart0 or g_mss_uart1\r
+    global data structure defined within the UART driver.\r
+\r
+  @return\r
+    This function returns current state of the UART's MSR as an 8 bit\r
+    unsigned integer. The driver provides the following set of bit mask\r
+    constants that should be compared with and/or used to mask the\r
+    returned value to determine the modem status:\r
+        \95   MSS_UART_DCTS   (bit mask = 0x01)\r
+        \95   MSS_UART_DDSR   (bit mask = 0x02)\r
+        \95   MSS_UART_TERI   (bit mask = 0x04)\r
+        \95   MSS_UART_DDCD   (bit mask = 0x08)\r
+        \95   MSS_UART_CTS    (bit mask = 0x10)\r
+        \95   MSS_UART_DSR    (bit mask = 0x20)\r
+        \95   MSS_UART_RI     (bit mask = 0x40)\r
+        \95   MSS_UART_DCD    (bit mask = 0x80)\r
+\r
+  Example:\r
+  @code\r
+    void uart_modem_status_isr(mss_uart_instance_t * this_uart)\r
+    {\r
+        uint8_t status;\r
+        status = MSS_UART_get_modem_status(this_uart);\r
+        if( status & MSS_UART_DCTS )\r
+        {\r
+            uart_dcts_handler();\r
+        }\r
+        if( status & MSS_UART_CTS )\r
+        {\r
+            uart_cts_handler();\r
+        }\r
+    }\r
+  @endcode\r
+ */\r
+uint8_t\r
+MSS_UART_get_modem_status\r
+(\r
+    mss_uart_instance_t * this_uart\r
+);\r
+\r
+/***************************************************************************//**\r
+  The MSS_UART_get_tx_status() function returns the transmitter status of the\r
+  MSS UART instance. It reads both the UART\92s line status register (LSR) and\r
+  returns the status of the transmit holding register empty (THRE) and\r
+  transmitter empty (TEMT) bits.*\r
+\r
+  @param this_uart\r
+    The this_uart parameter is a pointer to an mss_uart_instance_t\r
+    structure identifying the MSS UART hardware block that will perform\r
+    the requested function. There are two such data structures,\r
+    g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1.\r
+    This parameter must point to either the g_mss_uart0 or g_mss_uart1\r
+    global data structure defined within the UART driver.\r
+\r
+  @return\r
+    This function returns the UART\92s transmitter status as an 8-bit unsigned\r
+    integer. The returned value is 0 if the transmitter status bits are not\r
+    set or the function execution failed. The driver provides a set of bit\r
+    mask constants that should be compared with and/or used to mask the\r
+    returned value to determine the transmitter status.\r
+    When the return value is compared to the following bit mask, a non-zero\r
+    result indicates that the corresponding transmitter status bit is set:\r
+        \95   MSS_UART_THRE       (bit mask = 0x20)\r
+        \95   MSS_UART_TEMT       (bit mask = 0x40)\r
+    When the return value is compared to the following bit mask, a non-zero\r
+    result indicates that the transmitter is busy or the function execution\r
+    failed.\r
+        \95   MSS_UART_TX_BUSY        (bit mask = 0x00)\r
+\r
+  Example:\r
+  @code\r
+    uint8_t tx_buff[10] = "abcdefghi";\r
+    MSS_UART_init(&g_mss_uart0,\r
+                  MSS_UART_57600_BAUD,\r
+                  MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT); \r
+\r
+    MSS_UART_polled_tx(&g_mss_uart0, tx_buff, sizeof(tx_buff));\r
+\r
+    while(!(MSS_UART_TEMT & MSS_UART_get_tx_status(&g_mss_uart0)))\r
+    {\r
+        ;\r
+    }\r
+  @endcode\r
+ */\r
+uint8_t\r
+MSS_UART_get_tx_status\r
+(\r
+    mss_uart_instance_t * this_uart\r
+);\r
+\r
+/***************************************************************************//**\r
+  The MSS_UART_set_break() function is used to send the break \r
+  (9 zeros after stop bit) signal on the TX line. This function can be used \r
+  only when the MSS UART is initialized in LIN mode by using MSS_UART_lin_init().\r
+\r
+  @param this_uart\r
+    The this_uart parameter is a pointer to an mss_uart_instance_t\r
+    structure identifying the MSS UART hardware block that will perform\r
+    the requested function. There are two such data structures,\r
+    g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1.\r
+    This parameter must point to either the g_mss_uart0 or g_mss_uart1\r
+    global data structure defined within the UART driver.\r
+\r
+  @return\r
+    This function does not return a value. \r
+\r
+  Example:\r
+  @code\r
+    MSS_UART_init(&g_mss_uart0,\r
+                  MSS_UART_57600_BAUD,\r
+                  MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT); \r
+  \r
+    MSS_UART_set_break(&g_mss_uart0);\r
+  @endcode\r
+ */\r
+void\r
+MSS_UART_set_break\r
+(\r
+    mss_uart_instance_t * this_uart\r
+);\r
+\r
+/***************************************************************************//**\r
+  The MSS_UART_clear_break() function is used to remove the break signal on the \r
+  TX line. This function can be used only when the MSS UART is initialized in \r
+  LIN mode by using MSS_UART_lin_init().\r
+\r
+  @param this_uart\r
+    The this_uart parameter is a pointer to an mss_uart_instance_t\r
+    structure identifying the MSS UART hardware block that will perform\r
+    the requested function. There are two such data structures,\r
+    g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1.\r
+    This parameter must point to either the g_mss_uart0 or g_mss_uart1\r
+    global data structure defined within the UART driver.\r
+\r
+  @return\r
+    This function does not return a value. \r
+\r
+  Example:\r
+  @code\r
+    MSS_UART_init(&g_mss_uart0,\r
+                  MSS_UART_57600_BAUD,\r
+                  MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT); \r
+\r
+    MSS_UART_clear_break(&g_mss_uart0);\r
+  @endcode\r
+ */\r
+void\r
+MSS_UART_clear_break\r
+(\r
+    mss_uart_instance_t * this_uart\r
+);\r
+\r
+/***************************************************************************//**\r
+  The MSS_UART_enable_half_duplex() function is used to enable the half-duplex \r
+  (single wire) mode for the MSS UART. Though it finds application in Smartcard \r
+  mode, half-duplex mode can be used in other modes as well.\r
+\r
+  @param this_uart\r
+    The this_uart parameter is a pointer to an mss_uart_instance_t\r
+    structure identifying the MSS UART hardware block that will perform\r
+    the requested function. There are two such data structures,\r
+    g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1.\r
+    This parameter must point to either the g_mss_uart0 or g_mss_uart1\r
+    global data structure defined within the UART driver.\r
+\r
+  @return\r
+    This function does not return a value.\r
+\r
+  Example:\r
+  @code\r
+    MSS_UART_init(&g_mss_uart0,\r
+                  MSS_UART_57600_BAUD,\r
+                  MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT); \r
+\r
+    MSS_UART_enable_half_duplex(&g_mss_uart0);\r
+  @endcode\r
+ */\r
+void \r
+MSS_UART_enable_half_duplex\r
+(\r
+    mss_uart_instance_t * this_uart\r
+);\r
+\r
+/***************************************************************************//**\r
+  The MSS_UART_disable_half_duplex() function is used to disable the half-duplex \r
+  (single wire) mode for the MSS UART. Though it finds application in Smartcard \r
+  mode, half-duplex mode can be used in other modes as well.\r
+\r
+  @param this_uart\r
+    The this_uart parameter is a pointer to an mss_uart_instance_t\r
+    structure identifying the MSS UART hardware block that will perform\r
+    the requested function. There are two such data structures,\r
+    g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1.\r
+    This parameter must point to either the g_mss_uart0 or g_mss_uart1\r
+    global data structure defined within the UART driver.\r
+\r
+  @return\r
+    This function does not return a value.\r
+\r
+  Example:\r
+  @code\r
+    MSS_UART_init(&g_mss_uart0,\r
+                  MSS_UART_57600_BAUD,\r
+                  MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT); \r
+\r
+    MSS_UART_disable_half_duplex(&g_mss_uart0);\r
+  @endcode\r
+ */\r
+void \r
+MSS_UART_disable_half_duplex\r
+(\r
+    mss_uart_instance_t * this_uart\r
+);\r
+\r
+/***************************************************************************//**\r
+  The MSS_UART_set_rx_endian() function is used to configure the LSB first or \r
+  MSB first setting for MSS UART receiver\r
+\r
+  @param this_uart\r
+    The this_uart parameter is a pointer to an mss_uart_instance_t\r
+    structure identifying the MSS UART hardware block that will perform\r
+    the requested function. There are two such data structures,\r
+    g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1.\r
+    This parameter must point to either the g_mss_uart0 or g_mss_uart1\r
+    global data structure defined within the UART driver.\r
+  \r
+  @param endian\r
+    The endian parameter tells the LSB first or MSB first configuration. \r
+    This parameter is of type mss_uart_endian_t.\r
+\r
+  @return\r
+    This function does not return a value.\r
+\r
+  Example:\r
+  @code\r
+    MSS_UART_init(&g_mss_uart0,\r
+                  MSS_UART_57600_BAUD,\r
+                  MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT); \r
+\r
+    MSS_UART_set_rx_endian(&g_mss_uart0, MSS_UART_LITTLEEND);\r
+  @endcode\r
+ */\r
+void\r
+MSS_UART_set_rx_endian\r
+(\r
+    mss_uart_instance_t * this_uart,\r
+    mss_uart_endian_t endian    \r
+);\r
+\r
+/***************************************************************************//**\r
+  The MSS_UART_set_tx_endian() function is used to configure the LSB first or \r
+  MSB first setting for MSS UART transmitter.\r
+\r
+  @param this_uart\r
+    The this_uart parameter is a pointer to an mss_uart_instance_t\r
+    structure identifying the MSS UART hardware block that will perform\r
+    the requested function. There are two such data structures,\r
+    g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1.\r
+    This parameter must point to either the g_mss_uart0 or g_mss_uart1\r
+    global data structure defined within the UART driver.\r
+\r
+  @param endian\r
+    The endian parameter tells the LSB first or MSB first configuration. \r
+    This parameter is of type mss_uart_endian_t.\r
+\r
+  @return\r
+    This function does not return a value.\r
+\r
+  Example:\r
+  @code\r
+    MSS_UART_init(&g_mss_uart0,\r
+                  MSS_UART_57600_BAUD,\r
+                  MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT); \r
+\r
+    MSS_UART_set_tx_endian(&g_mss_uart0, MSS_UART_LITTLEEND);\r
+  @endcode\r
+ */\r
+void\r
+MSS_UART_set_tx_endian\r
+(\r
+    mss_uart_instance_t * this_uart,\r
+    mss_uart_endian_t endian    \r
+);\r
+\r
+/***************************************************************************//**\r
+  The MSS_UART_set_filter_length () function is used to configure the glitch \r
+  filter length of the MSS UART. This should be configured in accordance with \r
+  the chosen baud rate.\r
+\r
+  @param this_uart\r
+    The this_uart parameter is a pointer to an mss_uart_instance_t\r
+    structure identifying the MSS UART hardware block that will perform\r
+    the requested function. There are two such data structures,\r
+    g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1.\r
+    This parameter must point to either the g_mss_uart0 or g_mss_uart1\r
+    global data structure defined within the UART driver.\r
+\r
+  @param length\r
+    The length parameter is of mss_uart_filter_length_t type that determines \r
+    the length of the glitch filter.\r
+\r
+  @return\r
+    This function does not return a value.\r
+\r
+  Example:\r
+  @code\r
+    MSS_UART_init(&g_mss_uart0,\r
+                  MSS_UART_57600_BAUD,\r
+                  MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT); \r
+\r
+    MSS_UART_set_filter_length(&g_mss_uart0, MSS_UART_LEN2);\r
+  @endcode\r
+ */\r
+void\r
+MSS_UART_set_filter_length\r
+(\r
+    mss_uart_instance_t * this_uart,\r
+    mss_uart_filter_length_t length\r
+);\r
+\r
+/***************************************************************************//**\r
+  The MSS_UART_enable_afm() function is used to enable address flag detection \r
+  mode of the MSS UART\r
+\r
+  @param this_uart\r
+    The this_uart parameter is a pointer to an mss_uart_instance_t\r
+    structure identifying the MSS UART hardware block that will perform\r
+    the requested function. There are two such data structures,\r
+    g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1.\r
+    This parameter must point to either the g_mss_uart0 or g_mss_uart1\r
+    global data structure defined within the UART driver.\r
+\r
+  @return\r
+    This function does not return a value.\r
+\r
+  Example:\r
+  @code\r
+    MSS_UART_init(&g_mss_uart0,\r
+                  MSS_UART_57600_BAUD,\r
+                  MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT); \r
+\r
+    MSS_UART_enable_afm(&g_mss_uart0);\r
+  @endcode\r
+ */\r
+void\r
+MSS_UART_enable_afm\r
+(\r
+     mss_uart_instance_t * this_uart\r
+);\r
+\r
+/***************************************************************************//**\r
+  The MSS_UART_disable_afm() function is used to disable address flag detection \r
+  mode of the MSS UART.\r
+\r
+  @param this_uart\r
+    The this_uart parameter is a pointer to an mss_uart_instance_t\r
+    structure identifying the MSS UART hardware block that will perform\r
+    the requested function. There are two such data structures,\r
+    g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1.\r
+    This parameter must point to either the g_mss_uart0 or g_mss_uart1\r
+    global data structure defined within the UART driver.\r
+\r
+  @return\r
+    This function does not return a value.\r
+\r
+  Example:\r
+  @code\r
+    MSS_UART_init(&g_mss_uart0,\r
+                  MSS_UART_57600_BAUD,\r
+                  MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT); \r
+\r
+    MSS_UART_disable_afm(&g_mss_uart0);\r
+  @endcode\r
+ */\r
+void\r
+MSS_UART_disable_afm\r
+(\r
+     mss_uart_instance_t * this_uart\r
+);\r
+\r
+/***************************************************************************//**\r
+  The MSS_UART_enable_afclear () function is used to enable address flag clear \r
+  of the MSS UART. This should be used in conjunction with address flag \r
+  detection mode (AFM).\r
+\r
+  @param this_uart\r
+    The this_uart parameter is a pointer to an mss_uart_instance_t\r
+    structure identifying the MSS UART hardware block that will perform\r
+    the requested function. There are two such data structures,\r
+    g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1.\r
+    This parameter must point to either the g_mss_uart0 or g_mss_uart1\r
+    global data structure defined within the UART driver.\r
+\r
+  @return\r
+    This function does not return a value.\r
+\r
+  Example:\r
+  @code\r
+    MSS_UART_init(&g_mss_uart0,\r
+                  MSS_UART_57600_BAUD,\r
+                  MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT); \r
+\r
+    MSS_UART_enable_afclear(&g_mss_uart0);\r
+  @endcode\r
+ */\r
+void\r
+MSS_UART_enable_afclear\r
+(\r
+     mss_uart_instance_t * this_uart\r
+);\r
+\r
+/***************************************************************************//**\r
+  The MSS_UART_disable_afclear () function is used to disable address flag \r
+  clear of the MSS UART. This should be used in conjunction with address flag \r
+  detection mode (AFM).\r
+\r
+  @param this_uart\r
+    The this_uart parameter is a pointer to an mss_uart_instance_t\r
+    structure identifying the MSS UART hardware block that will perform\r
+    the requested function. There are two such data structures,\r
+    g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1.\r
+    This parameter must point to either the g_mss_uart0 or g_mss_uart1\r
+    global data structure defined within the UART driver.\r
+\r
+  @return\r
+    This function does not return a value.\r
+  \r
+  Example:\r
+  @code\r
+    MSS_UART_init(&g_mss_uart0,\r
+                  MSS_UART_57600_BAUD,\r
+                  MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT); \r
+\r
+    MSS_UART_disable_afclear(&g_mss_uart0);\r
+  @endcode\r
+ */\r
+void\r
+MSS_UART_disable_afclear\r
+(\r
+     mss_uart_instance_t * this_uart\r
+);\r
+\r
+/***************************************************************************//**\r
+  The MSS_UART_enable_rx_timeout() function is used to enable and configure \r
+  the receiver timeout functionality of MSS UART. This function accepts the \r
+  timeout parameter and applies the timeout based up on the baud rate as per \r
+  the formula 4 x timeout x bit time.\r
+\r
+  @param this_uart\r
+    The this_uart parameter is a pointer to an mss_uart_instance_t\r
+    structure identifying the MSS UART hardware block that will perform\r
+    the requested function. There are two such data structures,\r
+    g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1.\r
+    This parameter must point to either the g_mss_uart0 or g_mss_uart1\r
+    global data structure defined within the UART driver.\r
+\r
+  @param timeout\r
+    The timeout parameter specifies the receiver timeout multiple. \r
+    It should be configured according to the baud rate in use.\r
+\r
+  @return\r
+    This function does not return a value.\r
+\r
+  Example:\r
+  @code\r
+    MSS_UART_init(&g_mss_uart0,\r
+                  MSS_UART_57600_BAUD,\r
+                  MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT); \r
+\r
+    MSS_UART_enable_rx_timeout(&g_mss_uart0 , 24);\r
+  @endcode\r
+ */\r
+void \r
+MSS_UART_enable_rx_timeout\r
+(\r
+    mss_uart_instance_t * this_uart,\r
+    uint8_t timeout\r
+);\r
+\r
+/***************************************************************************//**\r
+  The MSS_UART_disable_rx_timeout() function is used to disable the receiver \r
+  timeout functionality of MSS UART. \r
+\r
+  @param this_uart\r
+    The this_uart parameter is a pointer to an mss_uart_instance_t\r
+    structure identifying the MSS UART hardware block that will perform\r
+    the requested function. There are two such data structures,\r
+    g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1.\r
+    This parameter must point to either the g_mss_uart0 or g_mss_uart1\r
+    global data structure defined within the UART driver.\r
+\r
+  @return\r
+    This function does not return a value.\r
+\r
+  Example:\r
+  @code\r
+    MSS_UART_init(&g_mss_uart0,\r
+                  MSS_UART_57600_BAUD,\r
+                  MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT); \r
+\r
+    MSS_UART_disable_rx_timeout(&g_mss_uart0);\r
+  @endcode\r
+ */\r
+void \r
+MSS_UART_disable_rx_timeout\r
+(\r
+    mss_uart_instance_t * this_uart\r
+);\r
+\r
+/***************************************************************************//**\r
+  The MSS_UART_enable_tx_time_guard() function is used to enable and configure \r
+  the transmitter time guard functionality of MSS UART. This function accepts \r
+  the timeguard parameter and applies the timeguard based up on the baud rate\r
+  as per the formula timeguard x bit time.\r
+\r
+  @param this_uart\r
+    The this_uart parameter is a pointer to an mss_uart_instance_t\r
+    structure identifying the MSS UART hardware block that will perform\r
+    the requested function. There are two such data structures,\r
+    g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1.\r
+    This parameter must point to either the g_mss_uart0 or g_mss_uart1\r
+    global data structure defined within the UART driver.\r
+\r
+  @return\r
+    This function does not return a value.\r
+\r
+  Example:\r
+  @code\r
+    MSS_UART_init(&g_mss_uart0,\r
+                  MSS_UART_57600_BAUD,\r
+                  MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT); \r
+\r
+    MSS_UART_enable_tx_time_guard(&g_mss_uart0 , 24);\r
+  @endcode\r
+ */\r
+void \r
+MSS_UART_enable_tx_time_guard\r
+(\r
+    mss_uart_instance_t * this_uart,\r
+    uint8_t timeguard\r
+);\r
+\r
+/***************************************************************************//**\r
+  The MSS_UART_disable_tx_time_guard() function is used to disable the \r
+  transmitter time guard functionality of MSS UART. \r
+\r
+  @param this_uart\r
+    The this_uart parameter is a pointer to an mss_uart_instance_t\r
+    structure identifying the MSS UART hardware block that will perform\r
+    the requested function. There are two such data structures,\r
+    g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1.\r
+    This parameter must point to either the g_mss_uart0 or g_mss_uart1\r
+    global data structure defined within the UART driver.\r
+\r
+  @return\r
+    This function does not return a value.\r
+\r
+  Example:\r
+  @code\r
+    MSS_UART_init(&g_mss_uart0,\r
+                  MSS_UART_57600_BAUD,\r
+                  MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT); \r
+                  \r
+    MSS_UART_disable_tx_time_guard(&g_mss_uart0);\r
+  @endcode\r
+ */\r
+void \r
+MSS_UART_disable_tx_time_guard\r
+(\r
+    mss_uart_instance_t * this_uart\r
+);\r
+\r
+/***************************************************************************//**\r
+  The MSS_UART_set_address() function is used to set the 8-bit address for \r
+  the MSS UART referenced by this_uart parameter. \r
+\r
+  @param this_uart\r
+    The this_uart parameter is a pointer to an mss_uart_instance_t\r
+    structure identifying the MSS UART hardware block that will perform\r
+    the requested function. There are two such data structures,\r
+    g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1.\r
+    This parameter must point to either the g_mss_uart0 or g_mss_uart1\r
+    global data structure defined within the UART driver.\r
+\r
+  @param address\r
+    The address parameter is the 8-bit address which is to be configured \r
+    to the MSS UART referenced by this_uart parameter.\r
+\r
+  @return\r
+    This function does not return a value.\r
+\r
+  Example:\r
+  @code\r
+    MSS_UART_init(&g_mss_uart0,\r
+                  MSS_UART_57600_BAUD,\r
+                  MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT); \r
+                  \r
+    MSS_UART_set_address(&g_mss_uart0, 0xAA);\r
+  @endcode\r
+ */\r
+void\r
+MSS_UART_set_address\r
+(\r
+    mss_uart_instance_t * this_uart,\r
+    uint8_t address\r
+);\r
+\r
+/***************************************************************************//**\r
+  The MSS_UART_set_ready_mode() function is used to configure the MODE0 or MODE1 \r
+  to the TXRDY and RXRDY signals of the MSS UART referenced by this_uart \r
+  parameter. The mode parameter is used to provide the mode to be configured.\r
+\r
+  @param this_uart\r
+    The this_uart parameter is a pointer to an mss_uart_instance_t\r
+    structure identifying the MSS UART hardware block that will perform\r
+    the requested function. There are two such data structures,\r
+    g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1.\r
+    This parameter must point to either the g_mss_uart0 or g_mss_uart1\r
+    global data structure defined within the UART driver.\r
+\r
+  @param mode\r
+    The mode parameter is the mss_uart_ready_mode_t type which is used to \r
+    configure the TXRDY and RXRDY signal modes.\r
+\r
+  @return\r
+    This function does not return a value.\r
+\r
+  Example:\r
+  @code\r
+    MSS_UART_init(&g_mss_uart0,\r
+                  MSS_UART_57600_BAUD,\r
+                  MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT); \r
+\r
+    MSS_UART_set_ready_mode(&g_mss_uart0, MSS_UART_READY_MODE0);    \r
+  @endcode\r
+ */\r
+void \r
+MSS_UART_set_ready_mode\r
+(\r
+    mss_uart_instance_t * this_uart,\r
+    mss_uart_ready_mode_t mode    \r
+);\r
+\r
+/***************************************************************************//**\r
+  The MSS_UART_set_usart_mode() function is used to configure the MSS UART \r
+  referenced by the parameter this_uart in USART mode. Various USART modes \r
+  are supported which can be configured by the parameter mode of type \r
+  mss_uart_usart_mode_t.\r
+\r
+  @param this_uart\r
+    The this_uart parameter is a pointer to an mss_uart_instance_t\r
+    structure identifying the MSS UART hardware block that will perform\r
+    the requested function. There are two such data structures,\r
+    g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1.\r
+    This parameter must point to either the g_mss_uart0 or g_mss_uart1\r
+    global data structure defined within the UART driver.\r
+\r
+  @param mode\r
+    The mode parameter is the USART mode to be configured. \r
+    This parameter is of type mss_uart_usart_mode_t.\r
+\r
+  @return\r
+    This function does not return a value.\r
+\r
+  Example:\r
+  @code\r
+    MSS_UART_init(&g_mss_uart0,\r
+                  MSS_UART_57600_BAUD,\r
+                  MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT);  \r
+\r
+    MSS_UART_set_usart_mode(&g_mss_uart0, MSS_UART_SYNC_MASTER_POS_EDGE_CLK);\r
+  @endcode\r
+ */\r
+void \r
+MSS_UART_set_usart_mode\r
+(\r
+    mss_uart_instance_t * this_uart,\r
+    mss_uart_usart_mode_t mode\r
+);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __MSS_UART_H_ */\r
diff --git a/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers/mss_uart/mss_uart_regs.h b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers/mss_uart/mss_uart_regs.h
new file mode 100644 (file)
index 0000000..2367525
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers/mss_uart/mss_uart_regs.h
@@ -0,0 +1,83 @@
+/*******************************************************************************\r
+ * (c) Copyright 2011-2013 Microsemi SoC Products Group.  All rights reserved.\r
+ * \r
+ * Register bit offsets and masks defintions for SmartFusion2 MSS MMUART.\r
+ * \r
+ * SVN $Revision: 5610 $\r
+ * SVN $Date: 2013-04-05 14:19:30 +0100 (Fri, 05 Apr 2013) $\r
+ */\r
+#ifndef MSS_UART_REGS_H_\r
+#define MSS_UART_REGS_H_\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/*******************************************************************************\r
+ Register Bit definitions\r
+ */\r
+\r
+/* Line Control register bit definitions */\r
+#define SB                  6u      /* Set break */\r
+#define DLAB                7u      /* Divisor latch access bit */\r
+\r
+/* FIFO Control register bit definitions */\r
+#define RXRDY_TXRDYN_EN     0u      /* Enable TXRDY and RXRDY signals */\r
+#define CLEAR_RX_FIFO       1u      /* Clear receiver FIFO */\r
+#define CLEAR_TX_FIFO       2u      /* Clear transimtter FIFO */\r
+#define RDYMODE             3u      /* Mode 0 or Mode 1 for TXRDY and RXRDY */\r
+\r
+/* Modem Control register bit definitions */\r
+#define LOOP                4u      /* Local loopback */\r
+#define RLOOP               5u      /* Remote loopback */\r
+#define ECHO                6u      /* Automatic echo */\r
+#define RLOOP_MASK          0x6u    /* Remote loopback & Automatic echo*/\r
+\r
+/* Line Status register bit definitions   */\r
+#define DR                  0u      /* Data ready */\r
+#define THRE                5u      /* Transmitter holding register empty */\r
+#define TEMT                6u      /* Transitter empty */\r
+\r
+/* Interrupt Enable register bit definitions */\r
+#define ERBFI               0u      /* Enable receiver buffer full interrupt */\r
+#define ETBEI               1u      /* Enable transmitter buffer empty interrupt */\r
+#define ELSI                2u      /* Enable line status interrupt */\r
+#define EDSSI               3u      /* Enable modem status interrupt */\r
+\r
+/* Multimode register 0 bit definitions */\r
+#define ELIN                3u      /* Enable LIN header detection */\r
+#define ETTG                5u      /* Enable transmitter time guard */\r
+#define ERTO                6u      /* Enable receiver time-out */\r
+#define EFBR                7u      /* Enable fractional baud rate mode */\r
+\r
+/* Multimode register 1 bit definitions */\r
+#define E_MSB_RX            0u      /* MSB / LSB first for receiver */\r
+#define E_MSB_TX            1u      /* MSB / LSB first for transmitter */\r
+#define EIRD                2u      /* Enable IrDA modem */\r
+#define EIRX                3u      /* Input polarity for IrDA modem */\r
+#define EITX                4u      /* Output polarity for IrDA modem */\r
+#define EITP                5u      /* Output pulse width for IrDA modem */      \r
+\r
+/* Multimode register 2 bit definitions */\r
+#define EERR                0u      /* Enable ERR / NACK during stop time */\r
+#define EAFM                1u      /* Enable 9-bit address flag mode */\r
+#define EAFC                2u      /* Enable address flag clear */\r
+#define ESWM                3u      /* Enable single wire half-duplex mode */\r
+\r
+/* Multimode Interrupt Enable register and\r
+   Multimode Interrupt Identification register definitions */\r
+#define ERTOI               0u      /* Enable receiver timeout interrupt */\r
+#define ENACKI              1u      /* Enable NACK / ERR interrupt */\r
+#define EPID_PEI            2u      /* Enable PID parity error interrupt */\r
+#define ELINBI              3u      /* Enable LIN break interrupt */\r
+#define ELINSI              4u      /* Enable LIN sync detection interrupt */\r
+\r
+\r
+#ifdef __cplusplus                       \r
+}\r
+#endif\r
+\r
+#endif /* MSS_UART_REGS_H_ */\r
+\r
+\r
+\r
diff --git a/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers_config/sys_config/sys_config.c b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers_config/sys_config/sys_config.c
new file mode 100644 (file)
index 0000000..9184e99
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers_config/sys_config/sys_config.c
@@ -0,0 +1,385 @@
+/*******************************************************************************\r
+ * (c) Copyright 2012 Microsemi SoC Products Group.  All rights reserved.\r
+ *\r
+ *  Smartfusion2 system configuration. This file is automatically generated\r
+ *  by the Libero tools. It contains the Smartfusion2 system configuration that\r
+ *  was selected during the hardware configuration flow. \r
+ *\r
+ */\r
+\r
+#include "../../CMSIS/m2sxxx.h"\r
+#include "../../CMSIS/sys_init_cfg_types.h"\r
+#include "sys_config.h"\r
+\r
+/*==============================================================================\r
+ *                             !!! WARNING !!!\r
+ *==============================================================================\r
+ * The project including this file must be linked so that the content of this\r
+ * file is located in internal eNVM at run time. The content of this file is\r
+ * used to configure the system prior to RAM content initialization. This means\r
+ * that the content of the data structures below will be used before the copy\r
+ * from LMA to VMA takes place. The LMA and VMA locations of the content of this\r
+ * file must be identical for the system to be seamlessly configured as part of\r
+ * the CMSIS boot process.\r
+ */\r
+ \r
+/*==============================================================================\r
+ * Clock configuration\r
+ */\r
+/* No configuration data structure required. */\r
+\r
+/*==============================================================================\r
+ * Memory remapping configuration\r
+ */\r
+/* TBD. */\r
+\r
+/*==============================================================================\r
+ * MDDR configuration\r
+ */\r
+#if MSS_SYS_MDDR_CONFIG_BY_CORTEX\r
+\r
+#include "sys_config_mddr_define.h"\r
+\r
+MDDR_TypeDef * const g_m2s_mddr_addr = (MDDR_TypeDef *)0x40020800;\r
+\r
+const ddr_subsys_cfg_t g_m2s_mddr_subsys_config =\r
+{\r
+    /*---------------------------------------------------------------------\r
+     * DDR Controller registers.\r
+     * All registers are 16-bit wide unless mentioned beside the definition.\r
+     */\r
+    {\r
+        MDDR_DDRC_DYN_SOFT_RESET_CR,\r
+        MDDR_DDRC_RESERVED0,\r
+        MDDR_DDRC_DYN_REFRESH_1_CR,\r
+        MDDR_DDRC_DYN_REFRESH_2_CR,\r
+        MDDR_DDRC_DYN_POWERDOWN_CR,\r
+        MDDR_DDRC_DYN_DEBUG_CR,\r
+        MDDR_DDRC_MODE_CR,\r
+        MDDR_DDRC_ADDR_MAP_BANK_CR,\r
+        MDDR_DDRC_ECC_DATA_MASK_CR,\r
+        MDDR_DDRC_ADDR_MAP_COL_1_CR,\r
+        MDDR_DDRC_ADDR_MAP_COL_2_CR,\r
+        MDDR_DDRC_ADDR_MAP_ROW_1_CR,\r
+        MDDR_DDRC_ADDR_MAP_ROW_2_CR,\r
+        MDDR_DDRC_INIT_1_CR,\r
+        MDDR_DDRC_CKE_RSTN_CYCLES_1_CR,\r
+        MDDR_DDRC_CKE_RSTN_CYCLES_2_CR,\r
+        MDDR_DDRC_INIT_MR_CR,\r
+        MDDR_DDRC_INIT_EMR_CR,\r
+        MDDR_DDRC_INIT_EMR2_CR,\r
+        MDDR_DDRC_INIT_EMR3_CR,\r
+        MDDR_DDRC_DRAM_BANK_TIMING_PARAM_CR,\r
+        MDDR_DDRC_DRAM_RD_WR_LATENCY_CR,\r
+        MDDR_DDRC_DRAM_RD_WR_PRE_CR,\r
+        MDDR_DDRC_DRAM_MR_TIMING_PARAM_CR,\r
+        MDDR_DDRC_DRAM_RAS_TIMING_CR,\r
+        MDDR_DDRC_DRAM_RD_WR_TRNARND_TIME_CR,\r
+        MDDR_DDRC_DRAM_T_PD_CR,\r
+        MDDR_DDRC_DRAM_BANK_ACT_TIMING_CR,\r
+        MDDR_DDRC_ODT_PARAM_1_CR,\r
+        MDDR_DDRC_ODT_PARAM_2_CR,\r
+        MDDR_DDRC_ADDR_MAP_COL_3_CR,\r
+        MDDR_DDRC_MODE_REG_RD_WR_CR,\r
+        MDDR_DDRC_MODE_REG_DATA_CR,\r
+        MDDR_DDRC_PWR_SAVE_1_CR,\r
+        MDDR_DDRC_PWR_SAVE_2_CR,\r
+        MDDR_DDRC_ZQ_LONG_TIME_CR,\r
+        MDDR_DDRC_ZQ_SHORT_TIME_CR,\r
+        MDDR_DDRC_ZQ_SHORT_INT_REFRESH_MARGIN_1_CR,\r
+        MDDR_DDRC_ZQ_SHORT_INT_REFRESH_MARGIN_2_CR,\r
+        MDDR_DDRC_PERF_PARAM_1_CR,\r
+        MDDR_DDRC_HPR_QUEUE_PARAM_1_CR,\r
+        MDDR_DDRC_HPR_QUEUE_PARAM_2_CR,\r
+        MDDR_DDRC_LPR_QUEUE_PARAM_1_CR,\r
+        MDDR_DDRC_LPR_QUEUE_PARAM_2_CR,\r
+        MDDR_DDRC_WR_QUEUE_PARAM_CR,\r
+        MDDR_DDRC_PERF_PARAM_2_CR,\r
+        MDDR_DDRC_PERF_PARAM_3_CR,\r
+        MDDR_DDRC_DFI_RDDATA_EN_CR,\r
+        MDDR_DDRC_DFI_MIN_CTRLUPD_TIMING_CR,\r
+        MDDR_DDRC_DFI_MAX_CTRLUPD_TIMING_CR,\r
+        MDDR_DDRC_DFI_WR_LVL_CONTROL_1_CR,\r
+        MDDR_DDRC_DFI_WR_LVL_CONTROL_2_CR,\r
+        MDDR_DDRC_DFI_RD_LVL_CONTROL_1_CR,\r
+        MDDR_DDRC_DFI_RD_LVL_CONTROL_2_CR,\r
+        MDDR_DDRC_DFI_CTRLUPD_TIME_INTERVAL_CR,\r
+        MDDR_DDRC_DYN_SOFT_RESET_ALIAS_CR,\r
+        MDDR_DDRC_AXI_FABRIC_PRI_ID_CR,\r
+    },\r
+\r
+    /*---------------------------------------------------------------------\r
+     * DDR PHY configuration registers\r
+     */\r
+    {\r
+        MDDR_PHY_LOOPBACK_TEST_CR,\r
+        MDDR_PHY_BOARD_LOOPBACK_CR,\r
+        MDDR_PHY_CTRL_SLAVE_RATIO_CR,\r
+        MDDR_PHY_CTRL_SLAVE_FORCE_CR,\r
+        MDDR_PHY_CTRL_SLAVE_DELAY_CR,\r
+        MDDR_PHY_DATA_SLICE_IN_USE_CR,\r
+        MDDR_PHY_LVL_NUM_OF_DQ0_CR,\r
+        MDDR_PHY_DQ_OFFSET_1_CR,\r
+        MDDR_PHY_DQ_OFFSET_2_CR,\r
+        MDDR_PHY_DQ_OFFSET_3_CR,\r
+        MDDR_PHY_DIS_CALIB_RST_CR,\r
+        MDDR_PHY_DLL_LOCK_DIFF_CR,\r
+        MDDR_PHY_FIFO_WE_IN_DELAY_1_CR,\r
+        MDDR_PHY_FIFO_WE_IN_DELAY_2_CR,\r
+        MDDR_PHY_FIFO_WE_IN_DELAY_3_CR,\r
+        MDDR_PHY_FIFO_WE_IN_FORCE_CR,\r
+        MDDR_PHY_FIFO_WE_SLAVE_RATIO_1_CR,\r
+        MDDR_PHY_FIFO_WE_SLAVE_RATIO_2_CR,\r
+        MDDR_PHY_FIFO_WE_SLAVE_RATIO_3_CR,\r
+        MDDR_PHY_FIFO_WE_SLAVE_RATIO_4_CR,\r
+        MDDR_PHY_GATELVL_INIT_MODE_CR,\r
+        MDDR_PHY_GATELVL_INIT_RATIO_1_CR,\r
+        MDDR_PHY_GATELVL_INIT_RATIO_2_CR,\r
+        MDDR_PHY_GATELVL_INIT_RATIO_3_CR,\r
+        MDDR_PHY_GATELVL_INIT_RATIO_4_CR,\r
+        MDDR_PHY_LOCAL_ODT_CR,\r
+        MDDR_PHY_INVERT_CLKOUT_CR,\r
+        MDDR_PHY_RD_DQS_SLAVE_DELAY_1_CR,\r
+        MDDR_PHY_RD_DQS_SLAVE_DELAY_2_CR,\r
+        MDDR_PHY_RD_DQS_SLAVE_DELAY_3_CR,\r
+        MDDR_PHY_RD_DQS_SLAVE_FORCE_CR,\r
+        MDDR_PHY_RD_DQS_SLAVE_RATIO_1_CR,\r
+        MDDR_PHY_RD_DQS_SLAVE_RATIO_2_CR,\r
+        MDDR_PHY_RD_DQS_SLAVE_RATIO_3_CR,\r
+        MDDR_PHY_RD_DQS_SLAVE_RATIO_4_CR,\r
+        MDDR_PHY_WR_DQS_SLAVE_DELAY_1_CR,\r
+        MDDR_PHY_WR_DQS_SLAVE_DELAY_2_CR,\r
+        MDDR_PHY_WR_DQS_SLAVE_DELAY_3_CR,\r
+        MDDR_PHY_WR_DQS_SLAVE_FORCE_CR,\r
+        MDDR_PHY_WR_DQS_SLAVE_RATIO_1_CR,\r
+        MDDR_PHY_WR_DQS_SLAVE_RATIO_2_CR,\r
+        MDDR_PHY_WR_DQS_SLAVE_RATIO_3_CR,\r
+        MDDR_PHY_WR_DQS_SLAVE_RATIO_4_CR,\r
+        MDDR_PHY_WR_DATA_SLAVE_DELAY_1_CR,\r
+        MDDR_PHY_WR_DATA_SLAVE_DELAY_2_CR,\r
+        MDDR_PHY_WR_DATA_SLAVE_DELAY_3_CR,\r
+        MDDR_PHY_WR_DATA_SLAVE_FORCE_CR,\r
+        MDDR_PHY_WR_DATA_SLAVE_RATIO_1_CR,\r
+        MDDR_PHY_WR_DATA_SLAVE_RATIO_2_CR,\r
+        MDDR_PHY_WR_DATA_SLAVE_RATIO_3_CR,\r
+        MDDR_PHY_WR_DATA_SLAVE_RATIO_4_CR,\r
+        MDDR_PHY_WRLVL_INIT_MODE_CR,\r
+        MDDR_PHY_WRLVL_INIT_RATIO_1_CR,\r
+        MDDR_PHY_WRLVL_INIT_RATIO_2_CR,\r
+        MDDR_PHY_WRLVL_INIT_RATIO_3_CR,\r
+        MDDR_PHY_WRLVL_INIT_RATIO_4_CR,\r
+        MDDR_PHY_WR_RD_RL_CR,\r
+        MDDR_PHY_RDC_FIFO_RST_ERR_CNT_CLR_CR,\r
+        MDDR_PHY_RDC_WE_TO_RE_DELAY_CR,\r
+        MDDR_PHY_USE_FIXED_RE_CR,\r
+        MDDR_PHY_USE_RANK0_DELAYS_CR,\r
+        MDDR_PHY_USE_LVL_TRNG_LEVEL_CR,\r
+        MDDR_PHY_DYN_CONFIG_CR,\r
+        MDDR_PHY_RD_WR_GATE_LVL_CR,\r
+        MDDR_PHY_DYN_RESET_CR\r
+    },\r
+    \r
+    /*---------------------------------------------------------------------\r
+     * FIC-64 registers\r
+     * These registers are 16-bit wide and 32-bit aligned.\r
+     */\r
+    {\r
+        MDDR_DDR_FIC_NB_ADDR_CR,\r
+        MDDR_DDR_FIC_NBRWB_SIZE_CR,\r
+        MDDR_DDR_FIC_WB_TIMEOUT_CR,\r
+        MDDR_DDR_FIC_HPD_SW_RW_EN_CR,\r
+        MDDR_DDR_FIC_HPD_SW_RW_INVAL_CR,\r
+        MDDR_DDR_FIC_SW_WR_ERCLR_CR,\r
+        MDDR_DDR_FIC_ERR_INT_ENABLE_CR,\r
+        MDDR_DDR_FIC_NUM_AHB_MASTERS_CR,\r
+        MDDR_DDR_FIC_LOCK_TIMEOUTVAL_1_CR,\r
+        MDDR_DDR_FIC_LOCK_TIMEOUTVAL_2_CR,\r
+        MDDR_DDR_FIC_LOCK_TIMEOUT_EN_CR\r
+    }\r
+};\r
+\r
+#endif\r
+\r
+/*==============================================================================\r
+ * FDDR configuration\r
+ */\r
+#if MSS_SYS_FDDR_CONFIG_BY_CORTEX\r
+\r
+#include "sys_config_fddr_define.h"\r
+\r
+FDDR_TypeDef * const g_m2s_fddr_addr = (FDDR_TypeDef *)0x40021000;\r
+\r
+const fddr_sysreg_t g_m2s_fddr_sysreg_subsys_config =\r
+{\r
+    0x0001u,    /* PLL_CONFIG_LOW_1 */\r
+    0x0002u,    /* PLL_CONFIG_LOW_2 */\r
+    0x0003u,    /* PLL_CONFIG_HIGH */\r
+    0x0004u,    /* FACC_CLK_EN */\r
+    0x0005u,    /* FACC_MUX_CONFIG */\r
+    0x0006u,    /* FACC_DIVISOR_RATIO */\r
+    0x0007u,    /* PLL_DELAY_LINE_SEL */\r
+    0x0008u,    /* SOFT_RESET */\r
+    0x0009u,    /* IO_CALIB */\r
+    0x000Au,    /* INTERRUPT_ENABLE */\r
+    0x000Bu,    /* AXI_AHB_MODE_SEL */\r
+    0x000Cu     /* PHY_SELF_REF_EN */\r
+};\r
+\r
+const ddr_subsys_cfg_t g_m2s_fddr_subsys_config = \r
+{\r
+    /*---------------------------------------------------------------------\r
+     * DDR Controller registers.\r
+     * All registers are 16-bit wide unless mentioned beside the definition.\r
+     */\r
+    {\r
+        FDDR_DDRC_DYN_SOFT_RESET_CR,\r
+        FDDR_DDRC_RESERVED0,\r
+        FDDR_DDRC_DYN_REFRESH_1_CR,\r
+        FDDR_DDRC_DYN_REFRESH_2_CR,\r
+        FDDR_DDRC_DYN_POWERDOWN_CR,\r
+        FDDR_DDRC_DYN_DEBUG_CR,\r
+        FDDR_DDRC_MODE_CR,\r
+        FDDR_DDRC_ADDR_MAP_BANK_CR,\r
+        FDDR_DDRC_ECC_DATA_MASK_CR,\r
+        FDDR_DDRC_ADDR_MAP_COL_1_CR,\r
+        FDDR_DDRC_ADDR_MAP_COL_2_CR,\r
+        FDDR_DDRC_ADDR_MAP_ROW_1_CR,\r
+        FDDR_DDRC_ADDR_MAP_ROW_2_CR,\r
+        FDDR_DDRC_INIT_1_CR,\r
+        FDDR_DDRC_CKE_RSTN_CYCLES_1_CR,\r
+        FDDR_DDRC_CKE_RSTN_CYCLES_2_CR,\r
+        FDDR_DDRC_INIT_MR_CR,\r
+        FDDR_DDRC_INIT_EMR_CR,\r
+        FDDR_DDRC_INIT_EMR2_CR,\r
+        FDDR_DDRC_INIT_EMR3_CR,\r
+        FDDR_DDRC_DRAM_BANK_TIMING_PARAM_CR,\r
+        FDDR_DDRC_DRAM_RD_WR_LATENCY_CR,\r
+        FDDR_DDRC_DRAM_RD_WR_PRE_CR,\r
+        FDDR_DDRC_DRAM_MR_TIMING_PARAM_CR,\r
+        FDDR_DDRC_DRAM_RAS_TIMING_CR,\r
+        FDDR_DDRC_DRAM_RD_WR_TRNARND_TIME_CR,\r
+        FDDR_DDRC_DRAM_T_PD_CR,\r
+        FDDR_DDRC_DRAM_BANK_ACT_TIMING_CR,\r
+        FDDR_DDRC_ODT_PARAM_1_CR,\r
+        FDDR_DDRC_ODT_PARAM_2_CR,\r
+        FDDR_DDRC_ADDR_MAP_COL_3_CR,\r
+        FDDR_DDRC_MODE_REG_RD_WR_CR,\r
+        FDDR_DDRC_MODE_REG_DATA_CR,\r
+        FDDR_DDRC_PWR_SAVE_1_CR,\r
+        FDDR_DDRC_PWR_SAVE_2_CR,\r
+        FDDR_DDRC_ZQ_LONG_TIME_CR,\r
+        FDDR_DDRC_ZQ_SHORT_TIME_CR,\r
+        FDDR_DDRC_ZQ_SHORT_INT_REFRESH_MARGIN_1_CR,\r
+        FDDR_DDRC_ZQ_SHORT_INT_REFRESH_MARGIN_2_CR,\r
+        FDDR_DDRC_PERF_PARAM_1_CR,\r
+        FDDR_DDRC_HPR_QUEUE_PARAM_1_CR,\r
+        FDDR_DDRC_HPR_QUEUE_PARAM_2_CR,\r
+        FDDR_DDRC_LPR_QUEUE_PARAM_1_CR,\r
+        FDDR_DDRC_LPR_QUEUE_PARAM_2_CR,\r
+        FDDR_DDRC_WR_QUEUE_PARAM_CR,\r
+        FDDR_DDRC_PERF_PARAM_2_CR,\r
+        FDDR_DDRC_PERF_PARAM_3_CR,\r
+        FDDR_DDRC_DFI_RDDATA_EN_CR,\r
+        FDDR_DDRC_DFI_MIN_CTRLUPD_TIMING_CR,\r
+        FDDR_DDRC_DFI_MAX_CTRLUPD_TIMING_CR,\r
+        FDDR_DDRC_DFI_WR_LVL_CONTROL_1_CR,\r
+        FDDR_DDRC_DFI_WR_LVL_CONTROL_2_CR,\r
+        FDDR_DDRC_DFI_RD_LVL_CONTROL_1_CR,\r
+        FDDR_DDRC_DFI_RD_LVL_CONTROL_2_CR,\r
+        FDDR_DDRC_DFI_CTRLUPD_TIME_INTERVAL_CR,\r
+        FDDR_DDRC_DYN_SOFT_RESET_ALIAS_CR,\r
+        FDDR_DDRC_AXI_FABRIC_PRI_ID_CR\r
+    },\r
+\r
+    /*---------------------------------------------------------------------\r
+     * DDR PHY configuration registers\r
+     */\r
+    {\r
+        FDDR_PHY_LOOPBACK_TEST_CR,\r
+        FDDR_PHY_BOARD_LOOPBACK_CR,\r
+        FDDR_PHY_CTRL_SLAVE_RATIO_CR,\r
+        FDDR_PHY_CTRL_SLAVE_FORCE_CR,\r
+        FDDR_PHY_CTRL_SLAVE_DELAY_CR,\r
+        FDDR_PHY_DATA_SLICE_IN_USE_CR,\r
+        FDDR_PHY_LVL_NUM_OF_DQ0_CR,\r
+        FDDR_PHY_DQ_OFFSET_1_CR,\r
+        FDDR_PHY_DQ_OFFSET_2_CR,\r
+        FDDR_PHY_DQ_OFFSET_3_CR,\r
+        FDDR_PHY_DIS_CALIB_RST_CR,\r
+        FDDR_PHY_DLL_LOCK_DIFF_CR,\r
+        FDDR_PHY_FIFO_WE_IN_DELAY_1_CR,\r
+        FDDR_PHY_FIFO_WE_IN_DELAY_2_CR,\r
+        FDDR_PHY_FIFO_WE_IN_DELAY_3_CR,\r
+        FDDR_PHY_FIFO_WE_IN_FORCE_CR,\r
+        FDDR_PHY_FIFO_WE_SLAVE_RATIO_1_CR,\r
+        FDDR_PHY_FIFO_WE_SLAVE_RATIO_2_CR,\r
+        FDDR_PHY_FIFO_WE_SLAVE_RATIO_3_CR,\r
+        FDDR_PHY_FIFO_WE_SLAVE_RATIO_4_CR,\r
+        FDDR_PHY_GATELVL_INIT_MODE_CR,\r
+        FDDR_PHY_GATELVL_INIT_RATIO_1_CR,\r
+        FDDR_PHY_GATELVL_INIT_RATIO_2_CR,\r
+        FDDR_PHY_GATELVL_INIT_RATIO_3_CR,\r
+        FDDR_PHY_GATELVL_INIT_RATIO_4_CR,\r
+        FDDR_PHY_LOCAL_ODT_CR,\r
+        FDDR_PHY_INVERT_CLKOUT_CR,\r
+        FDDR_PHY_RD_DQS_SLAVE_DELAY_1_CR,\r
+        FDDR_PHY_RD_DQS_SLAVE_DELAY_2_CR,\r
+        FDDR_PHY_RD_DQS_SLAVE_DELAY_3_CR,\r
+        FDDR_PHY_RD_DQS_SLAVE_FORCE_CR,\r
+        FDDR_PHY_RD_DQS_SLAVE_RATIO_1_CR,\r
+        FDDR_PHY_RD_DQS_SLAVE_RATIO_2_CR,\r
+        FDDR_PHY_RD_DQS_SLAVE_RATIO_3_CR,\r
+        FDDR_PHY_RD_DQS_SLAVE_RATIO_4_CR,\r
+        FDDR_PHY_WR_DQS_SLAVE_DELAY_1_CR,\r
+        FDDR_PHY_WR_DQS_SLAVE_DELAY_2_CR,\r
+        FDDR_PHY_WR_DQS_SLAVE_DELAY_3_CR,\r
+        FDDR_PHY_WR_DQS_SLAVE_FORCE_CR,\r
+        FDDR_PHY_WR_DQS_SLAVE_RATIO_1_CR,\r
+        FDDR_PHY_WR_DQS_SLAVE_RATIO_2_CR,\r
+        FDDR_PHY_WR_DQS_SLAVE_RATIO_3_CR,\r
+        FDDR_PHY_WR_DQS_SLAVE_RATIO_4_CR,\r
+        FDDR_PHY_WR_DATA_SLAVE_DELAY_1_CR,\r
+        FDDR_PHY_WR_DATA_SLAVE_DELAY_2_CR,\r
+        FDDR_PHY_WR_DATA_SLAVE_DELAY_3_CR,\r
+        FDDR_PHY_WR_DATA_SLAVE_FORCE_CR,\r
+        FDDR_PHY_WR_DATA_SLAVE_RATIO_1_CR,\r
+        FDDR_PHY_WR_DATA_SLAVE_RATIO_2_CR,\r
+        FDDR_PHY_WR_DATA_SLAVE_RATIO_3_CR,\r
+        FDDR_PHY_WR_DATA_SLAVE_RATIO_4_CR,\r
+        FDDR_PHY_WRLVL_INIT_MODE_CR,\r
+        FDDR_PHY_WRLVL_INIT_RATIO_1_CR,\r
+        FDDR_PHY_WRLVL_INIT_RATIO_2_CR,\r
+        FDDR_PHY_WRLVL_INIT_RATIO_3_CR,\r
+        FDDR_PHY_WRLVL_INIT_RATIO_4_CR,\r
+        FDDR_PHY_WR_RD_RL_CR,\r
+        FDDR_PHY_RDC_FIFO_RST_ERR_CNT_CLR_CR,\r
+        FDDR_PHY_RDC_WE_TO_RE_DELAY_CR,\r
+        FDDR_PHY_USE_FIXED_RE_CR,\r
+        FDDR_PHY_USE_RANK0_DELAYS_CR,\r
+        FDDR_PHY_USE_LVL_TRNG_LEVEL_CR,\r
+        FDDR_PHY_DYN_CONFIG_CR,\r
+        FDDR_PHY_RD_WR_GATE_LVL_CR,\r
+        FDDR_PHY_DYN_RESET_CR,\r
+    },\r
+    \r
+    /*---------------------------------------------------------------------\r
+     * FIC-64 registers\r
+     * These registers are 16-bit wide and 32-bit aligned.\r
+     */\r
+    {\r
+        FDDR_DDR_FIC_NB_ADDR_CR,\r
+        FDDR_DDR_FIC_NBRWB_SIZE_CR,\r
+        FDDR_DDR_FIC_WB_TIMEOUT_CR,\r
+        FDDR_DDR_FIC_HPD_SW_RW_EN_CR,\r
+        FDDR_DDR_FIC_HPD_SW_RW_INVAL_CR,\r
+        FDDR_DDR_FIC_SW_WR_ERCLR_CR,\r
+        FDDR_DDR_FIC_ERR_INT_ENABLE_CR,\r
+        FDDR_DDR_FIC_NUM_AHB_MASTERS_CR,\r
+        FDDR_DDR_FIC_LOCK_TIMEOUTVAL_1_CR,\r
+        FDDR_DDR_FIC_LOCK_TIMEOUTVAL_2_CR,\r
+        FDDR_DDR_FIC_LOCK_TIMEOUT_EN_CR\r
+    }\r
+};\r
+\r
+#endif\r
+\r
diff --git a/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers_config/sys_config/sys_config.h b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers_config/sys_config/sys_config.h
new file mode 100644 (file)
index 0000000..2bea18b
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers_config/sys_config/sys_config.h
@@ -0,0 +1,67 @@
+/*******************************************************************************\r
+ * (c) Copyright 2012 Microsemi SoC Products Group.  All rights reserved.\r
+ *\r
+ *  Smartfusion2 system configuration. This file is automatically generated\r
+ *  by the Libero tools.\r
+ *\r
+ */\r
+#ifndef MSS_SYSTEM_CONFIGURATION\r
+#define MSS_SYSTEM_CONFIGURATION\r
+\r
+/*==============================================================================\r
+ * Clock configuration\r
+ */\r
+#include "sys_config_mss_clocks.h"\r
+ \r
+/*==============================================================================\r
+ * Memory remapping configuration\r
+ */\r
+/* TBD */\r
+\r
+/*==============================================================================\r
+ * FACC_INIT (Cortex-M3 runs the FACC INIT procedure)\r
+ * Only set to 1 for design targeting the M2S050T_ES device\r
+ */\r
+#define MSS_SYS_FACC_INIT_BY_CORTEX         1\r
+\r
+/*==============================================================================\r
+ * MDDR configuration\r
+ */\r
+#define MSS_SYS_MDDR_CONFIG_BY_CORTEX       0\r
+\r
+/*==============================================================================\r
+ * FDDR configuration\r
+ */\r
+#define MSS_SYS_FDDR_CONFIG_BY_CORTEX       0\r
+\r
+/*==============================================================================\r
+ * SERDES Interface configuration\r
+ */\r
+#define MSS_SYS_SERDES_0_CONFIG_BY_CORTEX   0\r
+#if MSS_SYS_SERDES_0_CONFIG_BY_CORTEX\r
+#include "sys_config_SERDESIF_0.h"\r
+#endif\r
+\r
+#define MSS_SYS_SERDES_1_CONFIG_BY_CORTEX   0\r
+#if MSS_SYS_SERDES_1_CONFIG_BY_CORTEX\r
+#include "sys_config_SERDESIF_1.h"\r
+#endif\r
+\r
+#define MSS_SYS_SERDES_2_CONFIG_BY_CORTEX   0\r
+#if MSS_SYS_SERDES_2_CONFIG_BY_CORTEX\r
+#include "sys_config_SERDESIF_2.h"\r
+#endif\r
+\r
+#define MSS_SYS_SERDES_3_CONFIG_BY_CORTEX   0\r
+#if MSS_SYS_SERDES_3_CONFIG_BY_CORTEX\r
+#include "sys_config_SERDESIF_3.h"\r
+#endif\r
+\r
+/*==============================================================================\r
+ * Cache configuration\r
+ */\r
+#define MSS_SYS_CACHE_CONFIG_BY_CORTEX      0\r
+\r
+#endif  /* MSS_SYSTEM_CONFIGURATION */\r
+\r
+\r
diff --git a/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers_config/sys_config/sys_config_mss_clocks.h b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers_config/sys_config/sys_config_mss_clocks.h
new file mode 100644 (file)
index 0000000..0bb0bcb
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers_config/sys_config/sys_config_mss_clocks.h
@@ -0,0 +1,22 @@
+/**************************************************************************\r
+ * (c) Copyright 2012 Microsemi SoC Products Group.  All rights reserved.\r
+ *\r
+ * Smartfusion2 system configuration.\r
+ *   - Automatically created by Microsemi Libero SoC Sun May 05 13:12:03 2013\r
+ *\r
+ * Warning:  Do not modify this file, it may lead to unexpected\r
+ *           functional failures in your Microcontroller Subsystem.\r
+ */\r
+#ifndef SYS_CONFIG_MSS_CLOCKS\r
+#define SYS_CONFIG_MSS_CLOCKS\r
+\r
+#define MSS_SYS_M3_CLK_FREQ             50000000u\r
+#define MSS_SYS_MDDR_CLK_FREQ           200000000u\r
+#define MSS_SYS_APB_0_CLK_FREQ          50000000u\r
+#define MSS_SYS_APB_1_CLK_FREQ          50000000u\r
+#define MSS_SYS_APB_2_CLK_FREQ          12500000u\r
+#define MSS_SYS_FIC_0_CLK_FREQ          50000000u\r
+#define MSS_SYS_FIC_1_CLK_FREQ          50000000u\r
+#define MSS_SYS_FIC64_CLK_FREQ          50000000u\r
+\r
+#endif /* SYS_CONFIG_MSS_CLOCKS */\r
diff --git a/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/hal/CortexM3/GNU/cpu_types.h b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/hal/CortexM3/GNU/cpu_types.h
new file mode 100644 (file)
index 0000000..322764b
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/hal/CortexM3/GNU/cpu_types.h
@@ -0,0 +1,30 @@
+/*******************************************************************************\r
+ * (c) Copyright 2007-2013 Microsemi SoC Products Group. All rights reserved.\r
+ * \r
+ * SVN $Revision: 5258 $\r
+ * SVN $Date: 2013-03-21 12:41:02 +0000 (Thu, 21 Mar 2013) $\r
+ */\r
+#ifndef __CPU_TYPES_H\r
+#define __CPU_TYPES_H   1\r
+\r
+#include <stdint.h>\r
+\r
+/*------------------------------------------------------------------------------\r
+ */\r
+typedef unsigned int size_t;\r
+\r
+/*------------------------------------------------------------------------------\r
+ * addr_t: address type.\r
+ * Used to specify the address of peripherals present in the processor's memory\r
+ * map.\r
+ */\r
+typedef unsigned int addr_t;\r
+\r
+/*------------------------------------------------------------------------------\r
+ * psr_t: processor state register.\r
+ * Used by HAL_disable_interrupts() and HAL_restore_interrupts() to store the\r
+ * processor's state between disabling and restoring interrupts.\r
+ */\r
+typedef unsigned int psr_t;\r
+\r
+#endif  /* __CPU_TYPES_H */\r
diff --git a/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/hal/CortexM3/GNU/hal.s b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/hal/CortexM3/GNU/hal.s
new file mode 100644 (file)
index 0000000..36753b6
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/hal/CortexM3/GNU/hal.s
@@ -0,0 +1,31 @@
+#-------------------------------------------------------------------------------\r
+# (c) Copyright 2007-2013 Microsemi SoC Products Group. All rights reserved.\r
+# \r
+# Interrupt disabling/restoration for critical section protection.\r
+#\r
+# SVN $Revision: 5258 $\r
+# SVN $Date: 2013-03-21 12:41:02 +0000 (Thu, 21 Mar 2013) $\r
+#\r
+    .text\r
+    .global HAL_disable_interrupts\r
+    .global HAL_restore_interrupts\r
+    .code 16\r
+    .syntax unified\r
+    .type HAL_disable_interrupts, function\r
+    .type HAL_restore_interrupts, function\r
+#-------------------------------------------------------------------------------\r
+# \r
+#\r
+HAL_disable_interrupts:    \r
+    mrs r0, PRIMASK\r
+    cpsid I\r
+    bx lr\r
+\r
+#-------------------------------------------------------------------------------\r
+#\r
+#\r
+HAL_restore_interrupts:    \r
+    msr PRIMASK, r0\r
+    bx lr\r
+\r
+.end\r
diff --git a/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/hal/CortexM3/GNU/hw_macros.h b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/hal/CortexM3/GNU/hw_macros.h
new file mode 100644 (file)
index 0000000..2142cb2
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/hal/CortexM3/GNU/hw_macros.h
@@ -0,0 +1,96 @@
+/*******************************************************************************\r
+ * (c) Copyright 2007-2013 Microsemi SoC Products Group. All rights reserved.\r
+ * \r
+ *  Hardware registers access macros.\r
+ * \r
+ *  THE MACROS DEFINED IN THIS FILE ARE DEPRECATED. DO NOT USED FOR NEW \r
+ *  DEVELOPMENT.\r
+ *\r
+ * These macros are used to access peripheral's registers. They allow access to\r
+ * 8, 16 and 32 bit wide registers. All accesses to peripheral registers should\r
+ * be done through these macros in order to ease porting accross different \r
+ * processors/bus architectures.\r
+ * \r
+ * Some of these macros also allow to access a specific register field.\r
+ * \r
+ * SVN $Revision: 5258 $\r
+ * SVN $Date: 2013-03-21 12:41:02 +0000 (Thu, 21 Mar 2013) $\r
+ */\r
+#ifndef __HW_REGISTER_MACROS_H\r
+#define __HW_REGISTER_MACROS_H 1\r
+\r
+/*------------------------------------------------------------------------------\r
+ * 32 bits registers access:\r
+ */\r
+#define HW_get_uint32_reg(BASE_ADDR, REG_OFFSET) (*((uint32_t volatile *)(BASE_ADDR + REG_OFFSET##_REG_OFFSET)))\r
+\r
+#define HW_set_uint32_reg(BASE_ADDR, REG_OFFSET, VALUE) (*((uint32_t volatile *)(BASE_ADDR + REG_OFFSET##_REG_OFFSET)) = (VALUE))\r
+\r
+#define HW_set_uint32_reg_field(BASE_ADDR, FIELD, VALUE) \\r
+            (*((uint32_t volatile *)(BASE_ADDR + FIELD##_OFFSET)) =  \\r
+                ( \\r
+                    (uint32_t) \\r
+                    ( \\r
+                    (*((uint32_t volatile *)(BASE_ADDR + FIELD##_OFFSET))) & ~FIELD##_MASK) | \\r
+                    (uint32_t)(((VALUE) << FIELD##_SHIFT) & FIELD##_MASK) \\r
+                ) \\r
+            )\r
+\r
+#define HW_get_uint32_reg_field( BASE_ADDR, FIELD ) \\r
+            (( (*((uint32_t volatile *)(BASE_ADDR + FIELD##_OFFSET))) & FIELD##_MASK) >> FIELD##_SHIFT)\r
+\r
+/*------------------------------------------------------------------------------\r
+ * 32 bits memory access:\r
+ */\r
+#define HW_get_uint32(BASE_ADDR) (*((uint32_t volatile *)(BASE_ADDR)))\r
+\r
+#define HW_set_uint32(BASE_ADDR, VALUE) (*((uint32_t volatile *)(BASE_ADDR)) = (VALUE))\r
+\r
+/*------------------------------------------------------------------------------\r
+ * 16 bits registers access:\r
+ */\r
+#define HW_get_uint16_reg(BASE_ADDR, REG_OFFSET) (*((uint16_t volatile *)(BASE_ADDR + REG_OFFSET##_REG_OFFSET)))\r
+\r
+#define HW_set_uint16_reg(BASE_ADDR, REG_OFFSET, VALUE) (*((uint16_t volatile *)(BASE_ADDR + REG_OFFSET##_REG_OFFSET)) = (VALUE))\r
+\r
+#define HW_set_uint16_reg_field(BASE_ADDR, FIELD, VALUE) \\r
+            (*((uint16_t volatile *)(BASE_ADDR + FIELD##_OFFSET)) =  \\r
+                ( \\r
+                    (uint16_t) \\r
+                    ( \\r
+                    (*((uint16_t volatile *)(BASE_ADDR + FIELD##_OFFSET))) & ~FIELD##_MASK) | \\r
+                    (uint16_t)(((VALUE) << FIELD##_SHIFT) & FIELD##_MASK) \\r
+                ) \\r
+            )\r
+\r
+#define HW_get_uint16_reg_field( BASE_ADDR, FIELD ) \\r
+            (( (*((uint16_t volatile *)(BASE_ADDR + FIELD##_OFFSET))) & FIELD##_MASK) >> FIELD##_SHIFT)\r
+\r
+/*------------------------------------------------------------------------------\r
+ * 8 bits registers access:\r
+ */\r
+#define HW_get_uint8_reg(BASE_ADDR, REG_OFFSET) (*((uint8_t volatile *)(BASE_ADDR + REG_OFFSET##_REG_OFFSET)))\r
+\r
+#define HW_set_uint8_reg(BASE_ADDR, REG_OFFSET, VALUE) (*((uint8_t volatile *)(BASE_ADDR + REG_OFFSET##_REG_OFFSET)) = (VALUE))\r
+ \r
+#define HW_set_uint8_reg_field(BASE_ADDR, FIELD, VALUE) \\r
+            (*((uint8_t volatile *)(BASE_ADDR + FIELD##_OFFSET)) =  \\r
+                ( \\r
+                    (uint8_t) \\r
+                    ( \\r
+                    (*((uint8_t volatile *)(BASE_ADDR + FIELD##_OFFSET))) & ~FIELD##_MASK) | \\r
+                    (uint8_t)(((VALUE) << FIELD##_SHIFT) & FIELD##_MASK) \\r
+                ) \\r
+            )\r
+\r
+#define HW_get_uint8_reg_field( BASE_ADDR, FIELD ) \\r
+            (( (*((uint8_t volatile *)(BASE_ADDR + FIELD##_OFFSET))) & FIELD##_MASK) >> FIELD##_SHIFT)\r
+\r
+/*------------------------------------------------------------------------------\r
+ * 8 bits memory access:\r
+ */\r
+#define HW_get_uint8(BASE_ADDR) (*((uint8_t volatile *)(BASE_ADDR)))\r
+\r
+#define HW_set_uint8(BASE_ADDR, VALUE) (*((uint8_t volatile *)(BASE_ADDR)) = (VALUE))\r
+ \r
+#endif  /* __HW_REGISTER_MACROS_H */\r
diff --git a/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/hal/CortexM3/GNU/hw_reg_access.s b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/hal/CortexM3/GNU/hw_reg_access.s
new file mode 100644 (file)
index 0000000..3a0b254
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/hal/CortexM3/GNU/hw_reg_access.s
@@ -0,0 +1,165 @@
+/*******************************************************************************\r
+ * (c) Copyright 2008-2013 Microsemi SoC Products Group. All rights reserved.\r
+ * \r
+ * SVN $Revision: 5258 $\r
+ * SVN $Date: 2013-03-21 12:41:02 +0000 (Thu, 21 Mar 2013) $\r
+ */\r
+\r
+    .text\r
+    .global HW_set_32bit_reg\r
+    .global HW_get_32bit_reg\r
+    .global HW_set_32bit_reg_field\r
+    .global HW_get_32bit_reg_field\r
+    .global HW_set_16bit_reg\r
+    .global HW_get_16bit_reg\r
+    .global HW_set_16bit_reg_field\r
+    .global HW_get_16bit_reg_field\r
+    .global HW_set_8bit_reg\r
+    .global HW_get_8bit_reg\r
+    .global HW_set_8bit_reg_field\r
+    .global HW_get_8bit_reg_field\r
+    .code 16\r
+    .syntax unified\r
+    .type HW_set_32bit_reg, function\r
+    .type HW_get_32bit_reg, function\r
+    .type HW_set_32bit_reg_field, function\r
+    .type HW_get_32bit_reg_field, function\r
+    .type HW_set_16bit_reg, function\r
+    .type HW_get_16bit_reg, function\r
+    .type HW_set_16bit_reg_field, function\r
+    .type HW_get_16bit_reg_field, function\r
+    .type HW_set_8bit_reg, function\r
+    .type HW_get_8bit_reg, function\r
+    .type HW_set_8bit_reg_field, function\r
+    .type HW_get_8bit_reg_field, function\r
+\r
+/*------------------------------------------------------------------------------\r
+ * R0:   addr_t reg_addr\r
+ * R1:   uint32_t value\r
+ */\r
+HW_set_32bit_reg:\r
+    STR R1, [R0]\r
+    BX LR\r
+\r
+/*------------------------------------------------------------------------------\r
+ * R0:   addr_t reg_addr\r
+ */      \r
+HW_get_32bit_reg:\r
+    LDR R0, [R0]\r
+    BX LR\r
+\r
+/*------------------------------------------------------------------------------\r
+ * R0:   addr_t reg_addr\r
+ * R1:   int_fast8_t shift\r
+ * R2:   uint32_t mask\r
+ * R3:   uint32_t value\r
+ */\r
+HW_set_32bit_reg_field:\r
+    PUSH {R1,R2,R3,LR}\r
+    LSL.W R3, R3, R1\r
+    AND.W R3, R3, R2\r
+    LDR R1, [R0]\r
+    MVN.W R2, R2\r
+    AND.W R1, R1, R2\r
+    ORR.W R1, R1, R3\r
+    STR R1, [R0]\r
+    POP {R1,R2,R3,PC}\r
+\r
+/*------------------------------------------------------------------------------\r
+ * R0:   addr_t reg_addr\r
+ * R1:   int_fast8_t shift\r
+ * R2:   uint32_t mask\r
+ */\r
+HW_get_32bit_reg_field:\r
+    LDR R0, [R0]\r
+    AND.W R0, R0, R2\r
+    LSR.W R0, R0, R1\r
+    BX LR\r
+\r
+/*------------------------------------------------------------------------------\r
+ * R0:   addr_t reg_addr\r
+ * R1:   uint_fast16_t value\r
+ */\r
+HW_set_16bit_reg:\r
+    STRH R1, [R0]\r
+    BX LR\r
+        \r
+/*------------------------------------------------------------------------------\r
+ * R0:   addr_t reg_addr\r
+ */\r
+HW_get_16bit_reg:\r
+    LDRH R0, [R0]\r
+    BX LR\r
+\r
+/*------------------------------------------------------------------------------\r
+ * R0:   addr_t reg_addr\r
+ * R1:   int_fast8_t shift\r
+ * R2:   uint_fast16_t mask\r
+ * R3:   uint_fast16_t value\r
+ */\r
+HW_set_16bit_reg_field:\r
+    PUSH {R1,R2,R3,LR}\r
+    LSL.W R3, R3, R1\r
+    AND.W R3, R3, R2\r
+    LDRH R1, [R0]\r
+    MVN.W R2, R2\r
+    AND.W R1, R1, R2\r
+    ORR.W R1, R1, R3\r
+    STRH R1, [R0]\r
+    POP {R1,R2,R3,PC}\r
+\r
+/*------------------------------------------------------------------------------\r
+ * R0:   addr_t reg_addr\r
+ * R1:   int_fast8_t shift\r
+ * R2:   uint_fast16_t mask\r
+ */\r
+HW_get_16bit_reg_field:\r
+    LDRH R0, [R0]\r
+    AND.W R0, R0, R2\r
+    LSR.W R0, R0, R1\r
+    BX LR\r
+\r
+/*------------------------------------------------------------------------------\r
+ * R0:   addr_t reg_addr\r
+ * R1:   uint_fast8_t value\r
+ */\r
+HW_set_8bit_reg:\r
+    STRB R1, [R0]\r
+    BX LR\r
+        \r
+/*------------------------------------------------------------------------------\r
+ * R0:   addr_t reg_addr\r
+ */\r
+HW_get_8bit_reg:\r
+    LDRB R0, [R0]\r
+    BX LR\r
+\r
+/*------------------------------------------------------------------------------\r
+ * R0:   addr_t reg_addr,\r
+ * R1:   int_fast8_t shift\r
+ * R2:   uint_fast8_t mask\r
+ * R3:   uint_fast8_t value\r
+ */\r
+HW_set_8bit_reg_field:\r
+    PUSH {R1,R2,R3,LR}\r
+    LSL.W R3, R3, R1\r
+    AND.W R3, R3, R2\r
+    LDRB R1, [R0]\r
+    MVN.W R2, R2\r
+    AND.W R1, R1, R2\r
+    ORR.W R1, R1, R3\r
+    STRB R1, [R0]\r
+    POP {R1,R2,R3,PC}\r
+\r
+/*------------------------------------------------------------------------------\r
+ * R0:   addr_t reg_addr\r
+ * R1:   int_fast8_t shift\r
+ * R2:   uint_fast8_t mask\r
+ */\r
+HW_get_8bit_reg_field:\r
+    LDRB R0, [R0]\r
+    AND.W R0, R0, R2\r
+    LSR.W R0, R0, R1\r
+    BX LR\r
+\r
+.end\r
diff --git a/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/hal/CortexM3/cortex_nvic.c b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/hal/CortexM3/cortex_nvic.c
new file mode 100644 (file)
index 0000000..dc7c00f
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/hal/CortexM3/cortex_nvic.c
@@ -0,0 +1,205 @@
+/*******************************************************************************\r
+ * (c) Copyright 2007-2013 Microsemi SoC Products Group.  All rights reserved.\r
+ * \r
+ * Legacy Actel HAL Cortex NVIC control functions.\r
+ * The use of these functions should be replaced by calls to the equivalent\r
+ * CMSIS function in your application code.\r
+ *\r
+ * SVN $Revision: 5259 $\r
+ * SVN $Date: 2013-03-21 12:58:05 +0000 (Thu, 21 Mar 2013) $\r
+ */\r
+#include "cortex_nvic.h"\r
+#include "../../CMSIS/mss_assert.h"\r
+\r
+\r
+/***************************************************************************//**\r
+ * \r
+ */\r
+void NVIC_init( void )\r
+{\r
+    /*\r
+     * Please use the NVIC control functions provided by the SmartFusion2 CMSIS\r
+     * Hardware Abstraction Layer. The use of the Actel HAL NVIC control\r
+     * functions is obsolete on SmartFusion2 devices.\r
+     *\r
+     * Simply remove the call to NVIC_init() from your application code.\r
+     */\r
+    ASSERT(0);\r
+}\r
+\r
+/***************************************************************************//**\r
+ * \r
+ */\r
+void NVIC_set_handler\r
+(\r
+    uint32_t interrupt_number,\r
+    hal_nvic_irq_handler_t handler\r
+)\r
+{\r
+    /*\r
+     * Please use the NVIC control functions provided by the SmartFusion2 CMSIS\r
+     * Hardware Abstraction Layer. The use of the Actel HAL NVIC control\r
+     * functions is obsolete on SmartFusion2 devices.\r
+     *\r
+     * Please remove the call to NVIC_set_handler() from your application code\r
+     * and provide a function using one of the following function prototypes to\r
+     * handle interrupts from peripherals implemeted in the SmartFusion2 FPGA\r
+     * fabric:\r
+     *      - void FabricIrq0_IRQHandler(void)\r
+     *      - void FabricIrq1_IRQHandler(void)\r
+     *      - void FabricIrq2_IRQHandler(void)\r
+     *      - void FabricIrq3_IRQHandler(void)\r
+     *      - void FabricIrq4_IRQHandler(void)\r
+     *      - void FabricIrq5_IRQHandler(void)\r
+     *      - void FabricIrq6_IRQHandler(void)\r
+     *      - void FabricIrq7_IRQHandler(void)\r
+     *      - void FabricIrq8_IRQHandler(void)\r
+     *      - void FabricIrq9_IRQHandler(void)\r
+     *      - void FabricIrq10_IRQHandler(void)\r
+     *      - void FabricIrq11_IRQHandler(void)\r
+     *      - void FabricIrq12_IRQHandler(void)\r
+     *      - void FabricIrq13_IRQHandler(void)\r
+     *      - void FabricIrq14_IRQHandler(void)\r
+     *      - void FabricIrq15_IRQHandler(void)\r
+     * The function to implement depends on which MSS_INT_F2M[n] signal is used\r
+     * in your Libero design to connect the interrupt signal of the peripheral\r
+     * generating the interrupt.\r
+     */\r
+    ASSERT(0);\r
+}\r
+\r
+/***************************************************************************//**\r
+ * \r
+ */\r
+void NVIC_set_priority\r
+(\r
+    uint32_t interrupt_number,\r
+    uint8_t priority_level\r
+)\r
+{\r
+    /*\r
+     * Please use the NVIC control functions provided by the SmartFusion2 CMSIS\r
+     * Hardware Abstraction Layer. The use of the Actel HAL NVIC control\r
+     * functions is obsolete on SmartFusion2 devices.\r
+     *\r
+     * Please replace calls to NVIC_set_priority() with a call to the CMSIS\r
+     * void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) function where\r
+     * IRQn is one of the following values:\r
+     *      - FabricIrq0_IRQn\r
+     *      - FabricIrq1_IRQn\r
+     *      - FabricIrq2_IRQn\r
+     *      - FabricIrq3_IRQn\r
+     *      - FabricIrq4_IRQn\r
+     *      - FabricIrq5_IRQn\r
+     *      - FabricIrq6_IRQn\r
+     *      - FabricIrq7_IRQn\r
+     *      - FabricIrq8_IRQn\r
+     *      - FabricIrq9_IRQn\r
+     *      - FabricIrq10_IRQn\r
+     *      - FabricIrq11_IRQn\r
+     *      - FabricIrq12_IRQn\r
+     *      - FabricIrq13_IRQn\r
+     *      - FabricIrq14_IRQn\r
+     *      - FabricIrq15_IRQn\r
+     */\r
+    ASSERT(0);\r
+}\r
+\r
+/***************************************************************************//**\r
+ * \r
+ */\r
+void NVIC_enable_interrupt( uint32_t interrupt_number )\r
+{\r
+    /*\r
+     * Please use the NVIC control functions provided by the SmartFusion2 CMSIS\r
+     * Hardware Abstraction Layer. The use of the Actel HAL NVIC control\r
+     * functions is obsolete on SmartFusion2 devices.\r
+     *\r
+     * Please replace calls to NVIC_enable_interrupt() with a call to the CMSIS\r
+     * void NVIC_EnableIRQ(IRQn_Type IRQn) function where IRQn is one of the\r
+     * following values:\r
+     *      - FabricIrq0_IRQn\r
+     *      - FabricIrq1_IRQn\r
+     *      - FabricIrq2_IRQn\r
+     *      - FabricIrq3_IRQn\r
+     *      - FabricIrq4_IRQn\r
+     *      - FabricIrq5_IRQn\r
+     *      - FabricIrq6_IRQn\r
+     *      - FabricIrq7_IRQn\r
+     *      - FabricIrq8_IRQn\r
+     *      - FabricIrq9_IRQn\r
+     *      - FabricIrq10_IRQn\r
+     *      - FabricIrq11_IRQn\r
+     *      - FabricIrq12_IRQn\r
+     *      - FabricIrq13_IRQn\r
+     *      - FabricIrq14_IRQn\r
+     *      - FabricIrq15_IRQn\r
+     */\r
+    ASSERT(0);\r
+}\r
+\r
+/***************************************************************************//**\r
+ * \r
+ */\r
+void NVIC_disable_interrupt( uint32_t interrupt_number )\r
+{\r
+    /*\r
+     * Please use the NVIC control functions provided by the SmartFusion2 CMSIS\r
+     * Hardware Abstraction Layer. The use of the Actel HAL NVIC control\r
+     * functions is obsolete on SmartFusion2 devices.\r
+     *\r
+     * Please replace calls to NVIC_disable_interrupt() with a call to the CMSIS\r
+     * void NVIC_DisableIRQ(IRQn_Type IRQn) function where IRQn is one of the\r
+     * following values:\r
+     *      - FabricIrq0_IRQn\r
+     *      - FabricIrq1_IRQn\r
+     *      - FabricIrq2_IRQn\r
+     *      - FabricIrq3_IRQn\r
+     *      - FabricIrq4_IRQn\r
+     *      - FabricIrq5_IRQn\r
+     *      - FabricIrq6_IRQn\r
+     *      - FabricIrq7_IRQn\r
+     *      - FabricIrq8_IRQn\r
+     *      - FabricIrq9_IRQn\r
+     *      - FabricIrq10_IRQn\r
+     *      - FabricIrq11_IRQn\r
+     *      - FabricIrq12_IRQn\r
+     *      - FabricIrq13_IRQn\r
+     *      - FabricIrq14_IRQn\r
+     *      - FabricIrq15_IRQn\r
+     */\r
+    ASSERT(0);\r
+}\r
+\r
+/***************************************************************************//**\r
+ * \r
+ */\r
+void NVIC_clear_interrupt( uint32_t interrupt_number )\r
+{\r
+    /*\r
+     * Please use the NVIC control functions provided by the SmartFusion2 CMSIS\r
+     * Hardware Abstraction Layer. The use of the Actel HAL NVIC control\r
+     * functions is obsolete on SmartFusion2 devices.\r
+     *\r
+     * Please replace calls to NVIC_clear_interrupt() with a call to the CMSIS\r
+     * void NVIC_ClearPendingIRQ(IRQn_Type IRQn) function where IRQn is one of the\r
+     * following values:\r
+     *      - FabricIrq0_IRQn\r
+     *      - FabricIrq1_IRQn\r
+     *      - FabricIrq2_IRQn\r
+     *      - FabricIrq3_IRQn\r
+     *      - FabricIrq4_IRQn\r
+     *      - FabricIrq5_IRQn\r
+     *      - FabricIrq6_IRQn\r
+     *      - FabricIrq7_IRQn\r
+     *      - FabricIrq8_IRQn\r
+     *      - FabricIrq9_IRQn\r
+     *      - FabricIrq10_IRQn\r
+     *      - FabricIrq11_IRQn\r
+     *      - FabricIrq12_IRQn\r
+     *      - FabricIrq13_IRQn\r
+     *      - FabricIrq14_IRQn\r
+     *      - FabricIrq15_IRQn\r
+     */\r
+    ASSERT(0);\r
+}\r
diff --git a/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/hal/CortexM3/cortex_nvic.h b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/hal/CortexM3/cortex_nvic.h
new file mode 100644 (file)
index 0000000..1c5b948
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/hal/CortexM3/cortex_nvic.h
@@ -0,0 +1,56 @@
+/*******************************************************************************\r
+ * (c) Copyright 2007-2013 Microsemi SoC Products Group.  All rights reserved.\r
+ * \r
+ * Legacy Actel HAL Cortex NVIC control functions.\r
+ * The use of these functions should be replaced by calls to the equivalent\r
+ * CMSIS function in your application code.\r
+ *\r
+ * SVN $Revision: 5257 $\r
+ * SVN $Date: 2013-03-21 12:24:10 +0000 (Thu, 21 Mar 2013) $\r
+ */\r
+#ifndef CORTEX_NVIC_H_\r
+#define CORTEX_NVIC_H_\r
+\r
+#include <stdint.h>\r
+\r
+typedef void (*hal_nvic_irq_handler_t)(void);\r
+\r
+/*------------------------------------------------------------------------------\r
+ * \r
+ */\r
+void NVIC_init( void );\r
+\r
+/*------------------------------------------------------------------------------\r
+ * \r
+ */\r
+void NVIC_set_handler\r
+(\r
+    uint32_t interrupt_number,\r
+    hal_nvic_irq_handler_t handler\r
+);\r
+\r
+/*------------------------------------------------------------------------------\r
+ * \r
+ */\r
+void NVIC_set_priority\r
+(\r
+    uint32_t interrupt_number,\r
+    uint8_t priority_level\r
+);\r
+\r
+/*------------------------------------------------------------------------------\r
+ * \r
+ */\r
+void NVIC_enable_interrupt( uint32_t interrupt_number );\r
+\r
+/*------------------------------------------------------------------------------\r
+ * \r
+ */\r
+void NVIC_disable_interrupt( uint32_t interrupt_number );\r
+\r
+/*------------------------------------------------------------------------------\r
+ * \r
+ */\r
+void NVIC_clear_interrupt( uint32_t interrupt_number );\r
+\r
+#endif /*CORTEX_NVIC_H_*/\r
diff --git a/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/hal/hal.h b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/hal/hal.h
new file mode 100644 (file)
index 0000000..4722d15
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/hal/hal.h
@@ -0,0 +1,206 @@
+/***************************************************************************//**\r
+ * (c) Copyright 2007-2013 Microsemi SoC Products Group. All rights reserved.\r
+ * \r
+ * Hardware abstraction layer functions.\r
+ * \r
+ * SVN $Revision: 5258 $\r
+ * SVN $Date: 2013-03-21 12:41:02 +0000 (Thu, 21 Mar 2013) $\r
+ */\r
+#ifndef HAL_H_\r
+#define HAL_H_\r
+\r
+#include "cpu_types.h"\r
+#include "hw_reg_access.h"\r
+\r
+/***************************************************************************//**\r
+ * Enable all interrupts at the processor level.\r
+ */\r
+void HAL_enable_interrupts( void );\r
+\r
+/***************************************************************************//**\r
+ * Disable all interrupts at the processor core level.\r
+ * Return the interrupts enable state before disabling occured so that it can \r
+ * later be restored. \r
+ */\r
+psr_t HAL_disable_interrupts( void );\r
+\r
+/***************************************************************************//**\r
+ * Restore the interrupts enable state at the processor core level.\r
+ * This function is normally passed the value returned from a previous call to\r
+ * HAL_disable_interrupts(). \r
+ */\r
+void HAL_restore_interrupts( psr_t saved_psr );\r
+\r
+/***************************************************************************//**\r
+ */\r
+#define FIELD_OFFSET(FIELD_NAME)  (FIELD_NAME##_OFFSET)\r
+#define FIELD_SHIFT(FIELD_NAME)   (FIELD_NAME##_SHIFT)\r
+#define FIELD_MASK(FIELD_NAME)    (FIELD_NAME##_MASK)\r
+\r
+/***************************************************************************//**\r
+ * The macro HAL_set_32bit_reg() allows writing a 32 bits wide register.\r
+ *\r
+ * BASE_ADDR:   A variable of type addr_t specifying the base address of the\r
+ *              peripheral containing the register.\r
+ * REG_NAME:    A string identifying the register to write. These strings are\r
+ *              specified in a header file associated with the peripheral.\r
+ * VALUE:       A variable of type uint32_t containing the value to write.\r
+ */\r
+#define HAL_set_32bit_reg(BASE_ADDR, REG_NAME, VALUE) \\r
+          (HW_set_32bit_reg( ((BASE_ADDR) + (REG_NAME##_REG_OFFSET)), (VALUE) ))\r
+\r
+/***************************************************************************//**\r
+ * The macro HAL_get_32bit_reg() is used to read the value  of a 32 bits wide\r
+ * register.\r
+ * \r
+ * BASE_ADDR:   A variable of type addr_t specifying the base address of the\r
+ *              peripheral containing the register.\r
+ * REG_NAME:    A string identifying the register to read. These strings are\r
+ *              specified in a header file associated with the peripheral.\r
+ * RETURN:             This function-like macro returns a uint32_t value.\r
+ */\r
+#define HAL_get_32bit_reg(BASE_ADDR, REG_NAME) \\r
+          (HW_get_32bit_reg( ((BASE_ADDR) + (REG_NAME##_REG_OFFSET)) ))\r
+\r
+/***************************************************************************//**\r
+ * The macro HAL_set_32bit_reg_field() is used to write a field within a\r
+ * 32 bits wide register. The field written can be one or more bits.\r
+ * \r
+ * BASE_ADDR:   A variable of type addr_t specifying the base address of the\r
+ *              peripheral containing the register.\r
+ * FIELD_NAME:  A string identifying the register field to write. These strings\r
+ *                             are specified in a header file associated with the peripheral.\r
+ * VALUE:       A variable of type uint32_t containing the field value to write.\r
+ */\r
+#define HAL_set_32bit_reg_field(BASE_ADDR, FIELD_NAME, VALUE) \\r
+            (HW_set_32bit_reg_field(\\r
+                (BASE_ADDR) + FIELD_OFFSET(FIELD_NAME),\\r
+                FIELD_SHIFT(FIELD_NAME),\\r
+                FIELD_MASK(FIELD_NAME),\\r
+                (VALUE)))\r
+  \r
+/***************************************************************************//**\r
+ * The macro HAL_get_32bit_reg_field() is used to read a register field from\r
+ * within a 32 bit wide peripheral register. The field can be one or more bits.\r
+ * \r
+ * BASE_ADDR:   A variable of type addr_t specifying the base address of the\r
+ *              peripheral containing the register.\r
+ * FIELD_NAME:  A string identifying the register field to write. These strings\r
+ *                             are specified in a header file associated with the peripheral.\r
+ * RETURN:             This function-like macro returns a uint32_t value.\r
+ */\r
+#define HAL_get_32bit_reg_field(BASE_ADDR, FIELD_NAME) \\r
+            (HW_get_32bit_reg_field(\\r
+                (BASE_ADDR) + FIELD_OFFSET(FIELD_NAME),\\r
+                FIELD_SHIFT(FIELD_NAME),\\r
+                FIELD_MASK(FIELD_NAME)))\r
+  \r
+/***************************************************************************//**\r
+ * The macro HAL_set_16bit_reg() allows writing a 16 bits wide register.\r
+ *\r
+ * BASE_ADDR:   A variable of type addr_t specifying the base address of the\r
+ *              peripheral containing the register.\r
+ * REG_NAME:    A string identifying the register to write. These strings are\r
+ *              specified in a header file associated with the peripheral.\r
+ * VALUE:       A variable of type uint_fast16_t containing the value to write.\r
+ */\r
+#define HAL_set_16bit_reg(BASE_ADDR, REG_NAME, VALUE) \\r
+            (HW_set_16bit_reg( ((BASE_ADDR) + (REG_NAME##_REG_OFFSET)), (VALUE) ))\r
+\r
+/***************************************************************************//**\r
+ * The macro HAL_get_16bit_reg() is used to read the value  of a 16 bits wide\r
+ * register.\r
+ * \r
+ * BASE_ADDR:   A variable of type addr_t specifying the base address of the\r
+ *              peripheral containing the register.\r
+ * REG_NAME:    A string identifying the register to read. These strings are\r
+ *              specified in a header file associated with the peripheral.\r
+ * RETURN:             This function-like macro returns a uint16_t value.\r
+ */\r
+#define HAL_get_16bit_reg(BASE_ADDR, REG_NAME) \\r
+            (HW_get_16bit_reg( (BASE_ADDR) + (REG_NAME##_REG_OFFSET) ))\r
+\r
+/***************************************************************************//**\r
+ * The macro HAL_set_16bit_reg_field() is used to write a field within a\r
+ * 16 bits wide register. The field written can be one or more bits.\r
+ * \r
+ * BASE_ADDR:   A variable of type addr_t specifying the base address of the\r
+ *              peripheral containing the register.\r
+ * FIELD_NAME:  A string identifying the register field to write. These strings\r
+ *                             are specified in a header file associated with the peripheral.\r
+ * VALUE:       A variable of type uint16_t containing the field value to write.\r
+ */\r
+#define HAL_set_16bit_reg_field(BASE_ADDR, FIELD_NAME, VALUE) \\r
+            (HW_set_16bit_reg_field(\\r
+                (BASE_ADDR) + FIELD_OFFSET(FIELD_NAME),\\r
+                FIELD_SHIFT(FIELD_NAME),\\r
+                FIELD_MASK(FIELD_NAME),\\r
+                (VALUE)))  \r
+\r
+/***************************************************************************//**\r
+ * The macro HAL_get_16bit_reg_field() is used to read a register field from\r
+ * within a 8 bit wide peripheral register. The field can be one or more bits.\r
+ * \r
+ * BASE_ADDR:   A variable of type addr_t specifying the base address of the\r
+ *              peripheral containing the register.\r
+ * FIELD_NAME:  A string identifying the register field to write. These strings\r
+ *                             are specified in a header file associated with the peripheral.\r
+ * RETURN:             This function-like macro returns a uint16_t value.\r
+ */\r
+#define HAL_get_16bit_reg_field(BASE_ADDR, FIELD_NAME) \\r
+            (HW_get_16bit_reg_field(\\r
+                (BASE_ADDR) + FIELD_OFFSET(FIELD_NAME),\\r
+                FIELD_SHIFT(FIELD_NAME),\\r
+                FIELD_MASK(FIELD_NAME)))\r
+\r
+/***************************************************************************//**\r
+ * The macro HAL_set_8bit_reg() allows writing a 8 bits wide register.\r
+ *\r
+ * BASE_ADDR:   A variable of type addr_t specifying the base address of the\r
+ *              peripheral containing the register.\r
+ * REG_NAME:    A string identifying the register to write. These strings are\r
+ *              specified in a header file associated with the peripheral.\r
+ * VALUE:       A variable of type uint_fast8_t containing the value to write.\r
+ */\r
+#define HAL_set_8bit_reg(BASE_ADDR, REG_NAME, VALUE) \\r
+          (HW_set_8bit_reg( ((BASE_ADDR) + (REG_NAME##_REG_OFFSET)), (VALUE) ))\r
+\r
+/***************************************************************************//**\r
+ * The macro HAL_get_8bit_reg() is used to read the value of a 8 bits wide\r
+ * register.\r
+ * \r
+ * BASE_ADDR:   A variable of type addr_t specifying the base address of the\r
+ *              peripheral containing the register.\r
+ * REG_NAME:    A string identifying the register to read. These strings are\r
+ *              specified in a header file associated with the peripheral.\r
+ * RETURN:             This function-like macro returns a uint8_t value.\r
+ */\r
+#define HAL_get_8bit_reg(BASE_ADDR, REG_NAME) \\r
+          (HW_get_8bit_reg( (BASE_ADDR) + (REG_NAME##_REG_OFFSET) ))\r
+\r
+/***************************************************************************//**\r
+ */\r
+#define HAL_set_8bit_reg_field(BASE_ADDR, FIELD_NAME, VALUE) \\r
+            (HW_set_8bit_reg_field(\\r
+                (BASE_ADDR) + FIELD_OFFSET(FIELD_NAME),\\r
+                FIELD_SHIFT(FIELD_NAME),\\r
+                FIELD_MASK(FIELD_NAME),\\r
+                (VALUE)))\r
+\r
+/***************************************************************************//**\r
+ * The macro HAL_get_8bit_reg_field() is used to read a register field from\r
+ * within a 8 bit wide peripheral register. The field can be one or more bits.\r
+ * \r
+ * BASE_ADDR:   A variable of type addr_t specifying the base address of the\r
+ *              peripheral containing the register.\r
+ * FIELD_NAME:  A string identifying the register field to write. These strings\r
+ *                             are specified in a header file associated with the peripheral.\r
+ * RETURN:             This function-like macro returns a uint8_t value.\r
+ */\r
+#define HAL_get_8bit_reg_field(BASE_ADDR, FIELD_NAME) \\r
+            (HW_get_8bit_reg_field(\\r
+                (BASE_ADDR) + FIELD_OFFSET(FIELD_NAME),\\r
+                FIELD_SHIFT(FIELD_NAME),\\r
+                FIELD_MASK(FIELD_NAME)))\r
+  \r
+#endif /*HAL_H_*/\r
diff --git a/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/hal/hal_assert.h b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/hal/hal_assert.h
new file mode 100644 (file)
index 0000000..f669dc9
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/hal/hal_assert.h
@@ -0,0 +1,30 @@
+/*******************************************************************************\r
+ * (c) Copyright 2008-2013 Microsemi SoC Products Group. All rights reserved.\r
+ * \r
+ * SVN $Revision: 5274 $\r
+ * SVN $Date: 2013-03-22 13:18:44 +0000 (Fri, 22 Mar 2013) $\r
+ */\r
+#ifndef HAL_ASSERT_HEADER\r
+#define HAL_ASSERT_HEADER\r
+\r
+#include "../CMSIS/mss_assert.h"\r
+\r
+#if defined(NDEBUG)\r
+/***************************************************************************//**\r
+ * HAL_ASSERT() is defined out when the NDEBUG symbol is used.\r
+ ******************************************************************************/\r
+#define HAL_ASSERT(CHECK)\r
+\r
+#else\r
+/***************************************************************************//**\r
+ * Default behaviour for HAL_ASSERT() macro:\r
+ *------------------------------------------------------------------------------\r
+ * Using the HAL_ASSERT() macro is the same as directly using the SmartFusion2\r
+ * CMSIS ASSERT() macro. The behaviour is toolchain specific and project\r
+ * setting specific.\r
+ ******************************************************************************/\r
+#define HAL_ASSERT(CHECK)     ASSERT(CHECK);\r
+\r
+#endif  /* NDEBUG */\r
+\r
+#endif  /* HAL_ASSERT_HEADER */\r
diff --git a/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/hal/hw_reg_access.h b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/hal/hw_reg_access.h
new file mode 100644 (file)
index 0000000..8719ffe
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M2S050_Development_Kit_SoftConsole/RTOSDemo_Hardware_Platform/hal/hw_reg_access.h
@@ -0,0 +1,227 @@
+/***************************************************************************//**\r
+ * (c) Copyright 2007-2013 Microsemi SoC Products Group. All rights reserved.\r
+ * \r
+ * Hardware registers access functions.\r
+ * The implementation of these function is platform and toolchain specific.\r
+ * The functions declared here are implemented using assembler as part of the \r
+ * processor/toolchain specific HAL.\r
+ * \r
+ * SVN $Revision: 5258 $\r
+ * SVN $Date: 2013-03-21 12:41:02 +0000 (Thu, 21 Mar 2013) $\r
+ */\r
+#ifndef HW_REG_ACCESS\r
+#define HW_REG_ACCESS\r
+\r
+/***************************************************************************//**\r
+ * HW_set_32bit_reg is used to write the content of a 32 bits wide peripheral\r
+ * register.\r
+ * \r
+ * @param reg_addr  Address in the processor's memory map of the register to\r
+ *                  write.\r
+ * @param value     Value to be written into the peripheral register.\r
+ */\r
+void\r
+HW_set_32bit_reg\r
+(\r
+       addr_t reg_addr,\r
+       uint32_t value\r
+);\r
+\r
+/***************************************************************************//**\r
+ * HW_get_32bit_reg is used to read the content of a 32 bits wide peripheral\r
+ * register.\r
+ * \r
+ * @param reg_addr  Address in the processor's memory map of the register to\r
+ *                  read.\r
+ * @return          32 bits value read from the peripheral register.\r
+ */\r
+uint32_t\r
+HW_get_32bit_reg\r
+(\r
+       addr_t reg_addr\r
+);\r
+\r
+/***************************************************************************//**\r
+ * HW_set_32bit_reg_field is used to set the content of a field in a 32 bits \r
+ * wide peripheral register.\r
+ * \r
+ * @param reg_addr  Address in the processor's memory map of the register to\r
+ *                  be written.\r
+ * @param shift     Bit offset of the register field to be read within the \r
+ *                  register.\r
+ * @param mask      Bit mask to be applied to the raw register value to filter\r
+ *                  out the other register fields values.\r
+ * @param value     Value to be written in the specified field.\r
+ */\r
+void\r
+HW_set_32bit_reg_field\r
+(\r
+    addr_t reg_addr,\r
+    int_fast8_t shift,\r
+    uint32_t mask,\r
+    uint32_t value\r
+);\r
+\r
+/***************************************************************************//**\r
+ * HW_get_32bit_reg_field is used to read the content of a field out of a \r
+ * 32 bits wide peripheral register.\r
+ * \r
+ * @param reg_addr  Address in the processor's memory map of the register to\r
+ *                  read.\r
+ * @param shift     Bit offset of the register field to be written within the \r
+ *                  register.\r
+ * @param mask      Bit mask to be applied to the raw register value to filter\r
+ *                  out the other register fields values.\r
+ *\r
+ * @return          32 bits value containing the register field value specified\r
+ *                  as parameter.\r
+ */\r
+uint32_t \r
+HW_get_32bit_reg_field\r
+(\r
+    addr_t reg_addr,\r
+    int_fast8_t shift,\r
+    uint32_t mask\r
+);\r
+\r
+/***************************************************************************//**\r
+ * HW_set_16bit_reg is used to write the content of a 16 bits wide peripheral\r
+ * register.\r
+ * \r
+ * @param reg_addr  Address in the processor's memory map of the register to\r
+ *                  write.\r
+ * @param value     Value to be written into the peripheral register.\r
+ */\r
+void\r
+HW_set_16bit_reg\r
+(\r
+       addr_t reg_addr,\r
+       uint_fast16_t value\r
+);\r
+\r
+/***************************************************************************//**\r
+ * HW_get_16bit_reg is used to read the content of a 16 bits wide peripheral\r
+ * register.\r
+ * \r
+ * @param reg_addr  Address in the processor's memory map of the register to\r
+ *                  read.\r
+ * @return          16 bits value read from the peripheral register.\r
+ */\r
+uint16_t\r
+HW_get_16bit_reg\r
+(\r
+       addr_t reg_addr\r
+);\r
+\r
+/***************************************************************************//**\r
+ * HW_set_16bit_reg_field is used to set the content of a field in a 16 bits \r
+ * wide peripheral register.\r
+ * \r
+ * @param reg_addr  Address in the processor's memory map of the register to\r
+ *                  be written.\r
+ * @param shift     Bit offset of the register field to be read within the \r
+ *                  register.\r
+ * @param mask      Bit mask to be applied to the raw register value to filter\r
+ *                  out the other register fields values.\r
+ * @param value     Value to be written in the specified field.\r
+ */\r
+void HW_set_16bit_reg_field\r
+(\r
+    addr_t reg_addr,\r
+    int_fast8_t shift,\r
+    uint_fast16_t mask,\r
+    uint_fast16_t value\r
+);\r
+\r
+/***************************************************************************//**\r
+ * HW_get_16bit_reg_field is used to read the content of a field from a \r
+ * 16 bits wide peripheral register.\r
+ * \r
+ * @param reg_addr  Address in the processor's memory map of the register to\r
+ *                  read.\r
+ * @param shift     Bit offset of the register field to be written within the \r
+ *                  register.\r
+ * @param mask      Bit mask to be applied to the raw register value to filter\r
+ *                  out the other register fields values.\r
+ *\r
+ * @return          16 bits value containing the register field value specified\r
+ *                  as parameter.\r
+ */\r
+uint16_t HW_get_16bit_reg_field\r
+(\r
+    addr_t reg_addr,\r
+    int_fast8_t shift,\r
+    uint_fast16_t mask\r
+);\r
+\r
+/***************************************************************************//**\r
+ * HW_set_8bit_reg is used to write the content of a 8 bits wide peripheral\r
+ * register.\r
+ * \r
+ * @param reg_addr  Address in the processor's memory map of the register to\r
+ *                  write.\r
+ * @param value     Value to be written into the peripheral register.\r
+ */\r
+void\r
+HW_set_8bit_reg\r
+(\r
+       addr_t reg_addr,\r
+       uint_fast8_t value\r
+);\r
+\r
+/***************************************************************************//**\r
+ * HW_get_8bit_reg is used to read the content of a 8 bits wide peripheral\r
+ * register.\r
+ * \r
+ * @param reg_addr  Address in the processor's memory map of the register to\r
+ *                  read.\r
+ * @return          8 bits value read from the peripheral register.\r
+ */\r
+uint8_t\r
+HW_get_8bit_reg\r
+(\r
+    addr_t reg_addr\r
+);\r
+\r
+/***************************************************************************//**\r
+ * HW_set_8bit_reg_field is used to set the content of a field in a 8 bits \r
+ * wide peripheral register.\r
+ * \r
+ * @param reg_addr  Address in the processor's memory map of the register to\r
+ *                  be written.\r
+ * @param shift     Bit offset of the register field to be read within the \r
+ *                  register.\r
+ * @param mask      Bit mask to be applied to the raw register value to filter\r
+ *                  out the other register fields values.\r
+ * @param value     Value to be written in the specified field.\r
+ */\r
+void HW_set_8bit_reg_field\r
+(\r
+    addr_t reg_addr,\r
+    int_fast8_t shift,\r
+    uint_fast8_t mask,\r
+    uint_fast8_t value\r
+);\r
+\r
+/***************************************************************************//**\r
+ * HW_get_8bit_reg_field is used to read the content of a field from a \r
+ * 8 bits wide peripheral register.\r
+ * \r
+ * @param reg_addr  Address in the processor's memory map of the register to\r
+ *                  read.\r
+ * @param shift     Bit offset of the register field to be written within the \r
+ *                  register.\r
+ * @param mask      Bit mask to be applied to the raw register value to filter\r
+ *                  out the other register fields values.\r
+ *\r
+ * @return          16 bits value containing the register field value specified\r
+ *                  as parameter.\r
+ */\r
+uint8_t HW_get_8bit_reg_field\r
+(\r
+    addr_t reg_addr,\r
+    int_fast8_t shift,\r
+    uint_fast8_t mask\r
+);\r
+\r
+#endif /* HW_REG_ACCESS */\r
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