Add new demo files.

git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@765 1d2547de-c912-0410-9cb9-b8ca96c0e9e2

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/cmsis/core_cm3.c b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/cmsis/core_cm3.c
new file mode 100644 (file)
index 0000000..a64aa5c
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/cmsis/core_cm3.c
@@ -0,0 +1,805 @@
+/******************************************************************************\r
+ * @file:    core_cm3.c\r
+ * @purpose: CMSIS Cortex-M3 Core Peripheral Access Layer Source File\r
+ * @version: V1.10\r
+ * @date:    24. Feb. 2009\r
+ *----------------------------------------------------------------------------\r
+ *\r
+ * Copyright (C) 2009 ARM Limited. All rights reserved.\r
+ *\r
+ * ARM Limited (ARM) is supplying this software for use with Cortex-Mx \r
+ * processor based microcontrollers.  This file can be freely distributed \r
+ * within development tools that are supporting such ARM based processors. \r
+ *\r
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+ *\r
+ ******************************************************************************/\r
+\r
+\r
+\r
+#include <stdint.h>\r
+\r
+\r
+/* define compiler specific symbols */\r
+#if defined   ( __CC_ARM   )\r
+  #define __ASM            __asm           /*!< asm keyword for armcc          */\r
+  #define __INLINE         __inline        /*!< inline keyword for armcc        */\r
+\r
+#elif defined ( __ICCARM__ )\r
+  #define __ASM           __asm            /*!< asm keyword for iarcc           */\r
+  #define __INLINE        inline           /*!< inline keyword for iarcc. Only avaiable in High optimization mode! */\r
+  #define __nop           __no_operation   /*!< no operation intrinsic in iarcc */\r
+\r
+#elif defined (  __GNUC__  )\r
+  #define __ASM             asm            /*!< asm keyword for gcc            */\r
+  #define __INLINE          inline         /*!< inline keyword for gcc         */\r
+#endif\r
+\r
+\r
+\r
+#if defined ( __CC_ARM   ) /*------------------RealView Compiler -----------------*/\r
+\r
+/**\r
+ * @brief  Return the Process Stack Pointer\r
+ *\r
+ * @param  none\r
+ * @return uint32_t ProcessStackPointer\r
+ *\r
+ * Return the actual process stack pointer\r
+ */\r
+__ASM uint32_t __get_PSP(void)\r
+{\r
+  mrs r0, psp\r
+  bx lr\r
+}\r
+\r
+/**\r
+ * @brief  Set the Process Stack Pointer\r
+ *\r
+ * @param  uint32_t Process Stack Pointer\r
+ * @return none\r
+ *\r
+ * Assign the value ProcessStackPointer to the MSP \r
+ * (process stack pointer) Cortex processor register\r
+ */\r
+__ASM void __set_PSP(uint32_t topOfProcStack)\r
+{\r
+  msr psp, r0\r
+  bx lr\r
+}\r
+\r
+/**\r
+ * @brief  Return the Main Stack Pointer\r
+ *\r
+ * @param  none\r
+ * @return uint32_t Main Stack Pointer\r
+ *\r
+ * Return the current value of the MSP (main stack pointer)\r
+ * Cortex processor register\r
+ */\r
+__ASM uint32_t __get_MSP(void)\r
+{\r
+  mrs r0, msp\r
+  bx lr\r
+}\r
+\r
+/**\r
+ * @brief  Set the Main Stack Pointer\r
+ *\r
+ * @param  uint32_t Main Stack Pointer\r
+ * @return none\r
+ *\r
+ * Assign the value mainStackPointer to the MSP \r
+ * (main stack pointer) Cortex processor register\r
+ */\r
+__ASM void __set_MSP(uint32_t mainStackPointer)\r
+{\r
+  msr msp, r0\r
+  bx lr\r
+}\r
+\r
+/**\r
+ * @brief  Reverse byte order in unsigned short value\r
+ *\r
+ * @param  uint16_t value to reverse\r
+ * @return uint32_t reversed value\r
+ *\r
+ * Reverse byte order in unsigned short value\r
+ */\r
+__ASM uint32_t __REV16(uint16_t value)\r
+{\r
+  rev16 r0, r0\r
+  bx lr\r
+}\r
+\r
+/**\r
+ * @brief  Reverse byte order in signed short value with sign extension to integer\r
+ *\r
+ * @param  int16_t value to reverse\r
+ * @return int32_t reversed value\r
+ *\r
+ * Reverse byte order in signed short value with sign extension to integer\r
+ */\r
+__ASM int32_t __REVSH(int16_t value)\r
+{\r
+  revsh r0, r0\r
+  bx lr\r
+}\r
+\r
+\r
+#if (__ARMCC_VERSION < 400000)\r
+\r
+/**\r
+ * @brief  Remove the exclusive lock created by ldrex\r
+ *\r
+ * @param  none\r
+ * @return none\r
+ *\r
+ * Removes the exclusive lock which is created by ldrex.\r
+ */\r
+__ASM void __CLREX(void)\r
+{\r
+  clrex\r
+}\r
+\r
+/**\r
+ * @brief  Return the Base Priority value\r
+ *\r
+ * @param  none\r
+ * @return uint32_t BasePriority\r
+ *\r
+ * Return the content of the base priority register\r
+ */\r
+__ASM uint32_t  __get_BASEPRI(void)\r
+{\r
+  mrs r0, basepri\r
+  bx lr\r
+}\r
+\r
+/**\r
+ * @brief  Set the Base Priority value\r
+ *\r
+ * @param  uint32_t BasePriority\r
+ * @return none\r
+ *\r
+ * Set the base priority register\r
+ */\r
+__ASM void __set_BASEPRI(uint32_t basePri)\r
+{\r
+  msr basepri, r0\r
+  bx lr\r
+}\r
+\r
+/**\r
+ * @brief  Return the Priority Mask value\r
+ *\r
+ * @param  none\r
+ * @return uint32_t PriMask\r
+ *\r
+ * Return the state of the priority mask bit from the priority mask\r
+ * register\r
+ */\r
+__ASM uint32_t __get_PRIMASK(void)\r
+{\r
+  mrs r0, primask\r
+  bx lr\r
+}\r
+\r
+/**\r
+ * @brief  Set the Priority Mask value\r
+ *\r
+ * @param  uint32_t PriMask\r
+ * @return none\r
+ *\r
+ * Set the priority mask bit in the priority mask register\r
+ */\r
+__ASM void __set_PRIMASK(uint32_t priMask)\r
+{\r
+  msr primask, r0\r
+  bx lr\r
+}\r
+\r
+/**\r
+ * @brief  Return the Fault Mask value\r
+ *\r
+ * @param  none\r
+ * @return uint32_t FaultMask\r
+ *\r
+ * Return the content of the fault mask register\r
+ */\r
+__ASM uint32_t  __get_FAULTMASK(void)\r
+{\r
+  mrs r0, faultmask\r
+  bx lr\r
+}\r
+\r
+/**\r
+ * @brief  Set the Fault Mask value\r
+ *\r
+ * @param  uint32_t faultMask value\r
+ * @return none\r
+ *\r
+ * Set the fault mask register\r
+ */\r
+__ASM void __set_FAULTMASK(uint32_t faultMask)\r
+{\r
+  msr faultmask, r0\r
+  bx lr\r
+}\r
+\r
+/**\r
+ * @brief  Return the Control Register value\r
+ * \r
+ * @param  none\r
+ * @return uint32_t Control value\r
+ *\r
+ * Return the content of the control register\r
+ */\r
+__ASM uint32_t  __get_CONTROL(void)\r
+{\r
+  mrs r0, control\r
+  bx lr\r
+}\r
+\r
+/**\r
+ * @brief  Set the Control Register value\r
+ *\r
+ * @param  uint32_t Control value\r
+ * @return none\r
+ *\r
+ * Set the control register\r
+ */\r
+__ASM void __set_CONTROL(uint32_t control)\r
+{\r
+  msr control, r0\r
+  bx lr\r
+}\r
+\r
+#endif /* __ARMCC_VERSION  */ \r
+\r
+\r
+#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/\r
+#pragma diag_suppress=Pe940\r
+\r
+/**\r
+ * @brief  Return the Process Stack Pointer\r
+ *\r
+ * @param  none\r
+ * @return uint32_t ProcessStackPointer\r
+ *\r
+ * Return the actual process stack pointer\r
+ */\r
+uint32_t __get_PSP(void)\r
+{\r
+  __ASM("mrs r0, psp");\r
+  __ASM("bx lr");\r
+}\r
+\r
+/**\r
+ * @brief  Set the Process Stack Pointer\r
+ *\r
+ * @param  uint32_t Process Stack Pointer\r
+ * @return none\r
+ *\r
+ * Assign the value ProcessStackPointer to the MSP \r
+ * (process stack pointer) Cortex processor register\r
+ */\r
+void __set_PSP(uint32_t topOfProcStack)\r
+{\r
+  __ASM("msr psp, r0");\r
+  __ASM("bx lr");\r
+}\r
+\r
+/**\r
+ * @brief  Return the Main Stack Pointer\r
+ *\r
+ * @param  none\r
+ * @return uint32_t Main Stack Pointer\r
+ *\r
+ * Return the current value of the MSP (main stack pointer)\r
+ * Cortex processor register\r
+ */\r
+uint32_t __get_MSP(void)\r
+{\r
+  __ASM("mrs r0, msp");\r
+  __ASM("bx lr");\r
+}\r
+\r
+/**\r
+ * @brief  Set the Main Stack Pointer\r
+ *\r
+ * @param  uint32_t Main Stack Pointer\r
+ * @return none\r
+ *\r
+ * Assign the value mainStackPointer to the MSP \r
+ * (main stack pointer) Cortex processor register\r
+ */\r
+void __set_MSP(uint32_t topOfMainStack)\r
+{\r
+  __ASM("msr msp, r0");\r
+  __ASM("bx lr");\r
+}\r
+\r
+/**\r
+ * @brief  Reverse byte order in unsigned short value\r
+ *\r
+ * @param  uint16_t value to reverse\r
+ * @return uint32_t reversed value\r
+ *\r
+ * Reverse byte order in unsigned short value\r
+ */\r
+uint32_t __REV16(uint16_t value)\r
+{\r
+  __ASM("rev16 r0, r0");\r
+  __ASM("bx lr");\r
+}\r
+\r
+/**\r
+ * @brief  Reverse bit order of value\r
+ *\r
+ * @param  uint32_t value to reverse\r
+ * @return uint32_t reversed value\r
+ *\r
+ * Reverse bit order of value\r
+ */\r
+uint32_t __RBIT(uint32_t value)\r
+{\r
+  __ASM("rbit r0, r0");\r
+  __ASM("bx lr");\r
+}\r
+\r
+/**\r
+ * @brief  LDR Exclusive\r
+ *\r
+ * @param  uint8_t* address\r
+ * @return uint8_t value of (*address)\r
+ *\r
+ * Exclusive LDR command\r
+ */\r
+uint8_t __LDREXB(uint8_t *addr)\r
+{\r
+  __ASM("ldrexb r0, [r0]");\r
+  __ASM("bx lr"); \r
+}\r
+\r
+/**\r
+ * @brief  LDR Exclusive\r
+ *\r
+ * @param  uint16_t* address\r
+ * @return uint16_t value of (*address)\r
+ *\r
+ * Exclusive LDR command\r
+ */\r
+uint16_t __LDREXH(uint16_t *addr)\r
+{\r
+  __ASM("ldrexh r0, [r0]");\r
+  __ASM("bx lr");\r
+}\r
+\r
+/**\r
+ * @brief  LDR Exclusive\r
+ *\r
+ * @param  uint32_t* address\r
+ * @return uint32_t value of (*address)\r
+ *\r
+ * Exclusive LDR command\r
+ */\r
+uint32_t __LDREXW(uint32_t *addr)\r
+{\r
+  __ASM("ldrex r0, [r0]");\r
+  __ASM("bx lr");\r
+}\r
+\r
+/**\r
+ * @brief  STR Exclusive\r
+ *\r
+ * @param  uint8_t *address\r
+ * @param  uint8_t value to store\r
+ * @return uint32_t successful / failed\r
+ *\r
+ * Exclusive STR command\r
+ */\r
+uint32_t __STREXB(uint8_t value, uint8_t *addr)\r
+{\r
+  __ASM("strexb r0, r0, [r1]");\r
+  __ASM("bx lr");\r
+}\r
+\r
+/**\r
+ * @brief  STR Exclusive\r
+ *\r
+ * @param  uint16_t *address\r
+ * @param  uint16_t value to store\r
+ * @return uint32_t successful / failed\r
+ *\r
+ * Exclusive STR command\r
+ */\r
+uint32_t __STREXH(uint16_t value, uint16_t *addr)\r
+{\r
+  __ASM("strexh r0, r0, [r1]");\r
+  __ASM("bx lr");\r
+}\r
+\r
+/**\r
+ * @brief  STR Exclusive\r
+ *\r
+ * @param  uint32_t *address\r
+ * @param  uint32_t value to store\r
+ * @return uint32_t successful / failed\r
+ *\r
+ * Exclusive STR command\r
+ */\r
+uint32_t __STREXW(uint32_t value, uint32_t *addr)\r
+{\r
+  __ASM("strex r0, r0, [r1]");\r
+  __ASM("bx lr");\r
+}\r
+\r
+#pragma diag_default=Pe940\r
+\r
+\r
+#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/\r
+\r
+/**\r
+ * @brief  Return the Process Stack Pointer\r
+ *\r
+ * @param  none\r
+ * @return uint32_t ProcessStackPointer\r
+ *\r
+ * Return the actual process stack pointer\r
+ */\r
+uint32_t __get_PSP(void)\r
+{\r
+  uint32_t result=0;\r
+\r
+  __ASM volatile ("MRS %0, psp" : "=r" (result) );\r
+  return(result);\r
+}\r
+\r
+/**\r
+ * @brief  Set the Process Stack Pointer\r
+ *\r
+ * @param  uint32_t Process Stack Pointer\r
+ * @return none\r
+ *\r
+ * Assign the value ProcessStackPointer to the MSP \r
+ * (process stack pointer) Cortex processor register\r
+ */\r
+void __set_PSP(uint32_t topOfProcStack)\r
+{\r
+  __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) );\r
+}\r
+\r
+/**\r
+ * @brief  Return the Main Stack Pointer\r
+ *\r
+ * @param  none\r
+ * @return uint32_t Main Stack Pointer\r
+ *\r
+ * Return the current value of the MSP (main stack pointer)\r
+ * Cortex processor register\r
+ */\r
+uint32_t __get_MSP(void)\r
+{\r
+  uint32_t result=0;\r
+\r
+  __ASM volatile ("MRS %0, msp" : "=r" (result) );\r
+  return(result);\r
+}\r
+\r
+/**\r
+ * @brief  Set the Main Stack Pointer\r
+ *\r
+ * @param  uint32_t Main Stack Pointer\r
+ * @return none\r
+ *\r
+ * Assign the value mainStackPointer to the MSP \r
+ * (main stack pointer) Cortex processor register\r
+ */\r
+void __set_MSP(uint32_t topOfMainStack)\r
+{\r
+  __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) );\r
+}\r
+\r
+/**\r
+ * @brief  Return the Base Priority value\r
+ *\r
+ * @param  none\r
+ * @return uint32_t BasePriority\r
+ *\r
+ * Return the content of the base priority register\r
+ */\r
+uint32_t __get_BASEPRI(void)\r
+{\r
+  uint32_t result=0;\r
+  \r
+  __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );\r
+  return(result);\r
+}\r
+\r
+/**\r
+ * @brief  Set the Base Priority value\r
+ *\r
+ * @param  uint32_t BasePriority\r
+ * @return none\r
+ *\r
+ * Set the base priority register\r
+ */\r
+void __set_BASEPRI(uint32_t value)\r
+{\r
+  __ASM volatile ("MSR basepri, %0" : : "r" (value) );\r
+}\r
+\r
+/**\r
+ * @brief  Return the Priority Mask value\r
+ *\r
+ * @param  none\r
+ * @return uint32_t PriMask\r
+ *\r
+ * Return the state of the priority mask bit from the priority mask\r
+ * register\r
+ */\r
+uint32_t __get_PRIMASK(void)\r
+{\r
+  uint32_t result=0;\r
+\r
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );\r
+  return(result);\r
+}\r
+\r
+/**\r
+ * @brief  Set the Priority Mask value\r
+ *\r
+ * @param  uint32_t PriMask\r
+ * @return none\r
+ *\r
+ * Set the priority mask bit in the priority mask register\r
+ */\r
+void __set_PRIMASK(uint32_t priMask)\r
+{\r
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) );\r
+}\r
+\r
+/**\r
+ * @brief  Return the Fault Mask value\r
+ *\r
+ * @param  none\r
+ * @return uint32_t FaultMask\r
+ *\r
+ * Return the content of the fault mask register\r
+ */\r
+uint32_t __get_FAULTMASK(void)\r
+{\r
+  uint32_t result=0;\r
+  \r
+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );\r
+  return(result);\r
+}\r
+\r
+/**\r
+ * @brief  Set the Fault Mask value\r
+ *\r
+ * @param  uint32_t faultMask value\r
+ * @return none\r
+ *\r
+ * Set the fault mask register\r
+ */\r
+void __set_FAULTMASK(uint32_t faultMask)\r
+{\r
+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );\r
+}\r
+\r
+/**\r
+ * @brief  Reverse byte order in integer value\r
+ *\r
+ * @param  uint32_t value to reverse\r
+ * @return uint32_t reversed value\r
+ *\r
+ * Reverse byte order in integer value\r
+ */\r
+uint32_t __REV(uint32_t value)\r
+{\r
+  uint32_t result=0;\r
+  \r
+  __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );\r
+  return(result);\r
+}\r
+\r
+/**\r
+ * @brief  Reverse byte order in unsigned short value\r
+ *\r
+ * @param  uint16_t value to reverse\r
+ * @return uint32_t reversed value\r
+ *\r
+ * Reverse byte order in unsigned short value\r
+ */\r
+uint32_t __REV16(uint16_t value)\r
+{\r
+  uint32_t result=0;\r
+  \r
+  __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );\r
+  return(result);\r
+}\r
+\r
+/**\r
+ * @brief  Reverse byte order in signed short value with sign extension to integer\r
+ *\r
+ * @param  int32_t value to reverse\r
+ * @return int32_t reversed value\r
+ *\r
+ * Reverse byte order in signed short value with sign extension to integer\r
+ */\r
+int32_t __REVSH(int16_t value)\r
+{\r
+  uint32_t result=0;\r
+  \r
+  __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );\r
+  return(result);\r
+}\r
+\r
+/**\r
+ * @brief  Reverse bit order of value\r
+ *\r
+ * @param  uint32_t value to reverse\r
+ * @return uint32_t reversed value\r
+ *\r
+ * Reverse bit order of value\r
+ */\r
+uint32_t __RBIT(uint32_t value)\r
+{\r
+  uint32_t result=0;\r
+  \r
+   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );\r
+   return(result);\r
+}\r
+\r
+/**\r
+ * @brief  LDR Exclusive\r
+ *\r
+ * @param  uint8_t* address\r
+ * @return uint8_t value of (*address)\r
+ *\r
+ * Exclusive LDR command\r
+ */\r
+uint8_t __LDREXB(uint8_t *addr)\r
+{\r
+    uint8_t result=0;\r
+  \r
+   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );\r
+   return(result);\r
+}\r
+\r
+/**\r
+ * @brief  LDR Exclusive\r
+ *\r
+ * @param  uint16_t* address\r
+ * @return uint16_t value of (*address)\r
+ *\r
+ * Exclusive LDR command\r
+ */\r
+uint16_t __LDREXH(uint16_t *addr)\r
+{\r
+    uint16_t result=0;\r
+  \r
+   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );\r
+   return(result);\r
+}\r
+\r
+/**\r
+ * @brief  LDR Exclusive\r
+ *\r
+ * @param  uint32_t* address\r
+ * @return uint32_t value of (*address)\r
+ *\r
+ * Exclusive LDR command\r
+ */\r
+uint32_t __LDREXW(uint32_t *addr)\r
+{\r
+    uint32_t result=0;\r
+  \r
+   __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );\r
+   return(result);\r
+}\r
+\r
+/**\r
+ * @brief  STR Exclusive\r
+ *\r
+ * @param  uint8_t *address\r
+ * @param  uint8_t value to store\r
+ * @return uint32_t successful / failed\r
+ *\r
+ * Exclusive STR command\r
+ */\r
+uint32_t __STREXB(uint8_t value, uint8_t *addr)\r
+{\r
+   uint32_t result=0;\r
+  \r
+   __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );\r
+   return(result);\r
+}\r
+\r
+/**\r
+ * @brief  STR Exclusive\r
+ *\r
+ * @param  uint16_t *address\r
+ * @param  uint16_t value to store\r
+ * @return uint32_t successful / failed\r
+ *\r
+ * Exclusive STR command\r
+ */\r
+uint32_t __STREXH(uint16_t value, uint16_t *addr)\r
+{\r
+   uint32_t result=0;\r
+  \r
+   __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );\r
+   return(result);\r
+}\r
+\r
+/**\r
+ * @brief  STR Exclusive\r
+ *\r
+ * @param  uint32_t *address\r
+ * @param  uint32_t value to store\r
+ * @return uint32_t successful / failed\r
+ *\r
+ * Exclusive STR command\r
+ */\r
+uint32_t __STREXW(uint32_t value, uint32_t *addr)\r
+{\r
+   uint32_t result=0;\r
+  \r
+   __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );\r
+   return(result);\r
+}\r
+\r
+/**\r
+ * @brief  Return the Control Register value\r
+ * \r
+ * @param  none\r
+ * @return uint32_t Control value\r
+ *\r
+ * Return the content of the control register\r
+ */\r
+uint32_t __get_CONTROL(void)\r
+{\r
+  uint32_t result=0;\r
+\r
+  __ASM volatile ("MRS %0, control" : "=r" (result) );\r
+  return(result);\r
+}\r
+\r
+/**\r
+ * @brief  Set the Control Register value\r
+ *\r
+ * @param  uint32_t Control value\r
+ * @return none\r
+ *\r
+ * Set the control register\r
+ */\r
+void __set_CONTROL(uint32_t control)\r
+{\r
+  __ASM volatile ("MSR control, %0" : : "r" (control) );\r
+}\r
+\r
+#endif\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/cmsis/core_cm3.h b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/cmsis/core_cm3.h
new file mode 100644 (file)
index 0000000..9f83c1c
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/cmsis/core_cm3.h
@@ -0,0 +1,1265 @@
+/******************************************************************************\r
+ * @file:    core_cm3.h\r
+ * @purpose: CMSIS Cortex-M3 Core Peripheral Access Layer Header File\r
+ * @version: V1.10\r
+ * @date:    24. Feb. 2009\r
+ *----------------------------------------------------------------------------\r
+ *\r
+ * Copyright (C) 2009 ARM Limited. All rights reserved.\r
+ *\r
+ * ARM Limited (ARM) is supplying this software for use with Cortex-Mx \r
+ * processor based microcontrollers.  This file can be freely distributed \r
+ * within development tools that are supporting such ARM based processors. \r
+ *\r
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+ *\r
+ ******************************************************************************/\r
+\r
+\r
+\r
+\r
+#ifndef __CM3_CORE_H__\r
+#define __CM3_CORE_H__\r
+\r
+\r
+#define __CM3_CMSIS_VERSION_MAIN  (0x01)                                                       /*!< [31:16] CMSIS HAL main version */\r
+#define __CM3_CMSIS_VERSION_SUB   (0x10)                                                       /*!< [15:0]  CMSIS HAL sub version  */\r
+#define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number       */\r
+\r
+#define __CORTEX_M                (0x03)                                                       /*!< Cortex core                    */\r
+\r
+/**\r
+ *  Lint configuration \n\r
+ *  ----------------------- \n\r
+ *\r
+ *  The following Lint messages will be suppressed and not shown: \n\r
+ *  \n\r
+ *    --- Error 10: --- \n\r
+ *    register uint32_t __regBasePri         __asm("basepri"); \n\r
+ *    Error 10: Expecting ';' \n\r
+ *     \n\r
+ *    --- Error 530: --- \n\r
+ *    return(__regBasePri); \n\r
+ *    Warning 530: Symbol '__regBasePri' (line 264) not initialized \n\r
+ *     \n\r
+ *    --- Error 550: --- \n\r
+ *      __regBasePri = (basePri & 0x1ff); \n\r
+ *    } \n\r
+ *    Warning 550: Symbol '__regBasePri' (line 271) not accessed \n\r
+ *     \n\r
+ *    --- Error 754: --- \n\r
+ *    uint32_t RESERVED0[24]; \n\r
+ *    Info 754: local structure member '<some, not used in the HAL>' (line 109, file ./cm3_core.h) not referenced \n\r
+ *     \n\r
+ *    --- Error 750: --- \n\r
+ *    #define __CM3_CORE_H__ \n\r
+ *    Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced \n\r
+ *     \n\r
+ *    --- Error 528: --- \n\r
+ *    static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n\r
+ *    Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced \n\r
+ *     \n\r
+ *    --- Error 751: --- \n\r
+ *    } InterruptType_Type; \n\r
+ *    Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced \n\r
+ * \n\r
+ * \n\r
+ *    Note:  To re-enable a Message, insert a space before 'lint' * \n\r
+ *\r
+ */\r
+\r
+/*lint -save */\r
+/*lint -e10  */\r
+/*lint -e530 */\r
+/*lint -e550 */\r
+/*lint -e754 */\r
+/*lint -e750 */\r
+/*lint -e528 */\r
+/*lint -e751 */\r
+\r
+\r
+#include <stdint.h>                           /* Include standard types */\r
+\r
+#if defined (__ICCARM__)\r
+  #include <intrinsics.h>                     /* IAR Intrinsics   */\r
+#endif\r
+\r
+\r
+#ifndef __NVIC_PRIO_BITS\r
+  #define __NVIC_PRIO_BITS    4               /*!< standard definition for NVIC Priority Bits */\r
+#endif\r
+\r
+\r
+\r
+\r
+/**\r
+ * IO definitions\r
+ *\r
+ * define access restrictions to peripheral registers\r
+ */\r
+\r
+#define     __I     volatile const            /*!< defines 'read only' permissions      */\r
+#define     __O     volatile                  /*!< defines 'write only' permissions     */\r
+#define     __IO    volatile                  /*!< defines 'read / write' permissions   */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ *                 Register Abstraction\r
+ ******************************************************************************/\r
+\r
+\r
+/* System Reset */\r
+#define NVIC_VECTRESET              0         /*!< Vector Reset Bit             */\r
+#define NVIC_SYSRESETREQ            2         /*!< System Reset Request         */\r
+#define NVIC_AIRCR_VECTKEY    (0x5FA << 16)   /*!< AIRCR Key for write access   */\r
+#define NVIC_AIRCR_ENDIANESS        15        /*!< Endianess                    */\r
+\r
+/* Core Debug */\r
+#define CoreDebug_DEMCR_TRCENA (1 << 24)      /*!< DEMCR TRCENA enable          */\r
+#define ITM_TCR_ITMENA              1         /*!< ITM enable                   */\r
+\r
+\r
+\r
+\r
+/* memory mapping struct for Nested Vectored Interrupt Controller (NVIC) */\r
+typedef struct\r
+{\r
+  __IO uint32_t ISER[8];                      /*!< Interrupt Set Enable Register            */\r
+       uint32_t RESERVED0[24];\r
+  __IO uint32_t ICER[8];                      /*!< Interrupt Clear Enable Register          */\r
+       uint32_t RSERVED1[24];\r
+  __IO uint32_t ISPR[8];                      /*!< Interrupt Set Pending Register           */\r
+       uint32_t RESERVED2[24];\r
+  __IO uint32_t ICPR[8];                      /*!< Interrupt Clear Pending Register         */\r
+       uint32_t RESERVED3[24];\r
+  __IO uint32_t IABR[8];                      /*!< Interrupt Active bit Register            */\r
+       uint32_t RESERVED4[56];\r
+  __IO uint8_t  IP[240];                      /*!< Interrupt Priority Register, 8Bit wide   */\r
+       uint32_t RESERVED5[644];\r
+  __O  uint32_t STIR;                         /*!< Software Trigger Interrupt Register      */\r
+}  NVIC_Type;\r
+\r
+\r
+/* memory mapping struct for System Control Block */\r
+typedef struct\r
+{\r
+  __I  uint32_t CPUID;                        /*!< CPU ID Base Register                                     */\r
+  __IO uint32_t ICSR;                         /*!< Interrupt Control State Register                         */\r
+  __IO uint32_t VTOR;                         /*!< Vector Table Offset Register                             */\r
+  __IO uint32_t AIRCR;                        /*!< Application Interrupt / Reset Control Register           */\r
+  __IO uint32_t SCR;                          /*!< System Control Register                                  */\r
+  __IO uint32_t CCR;                          /*!< Configuration Control Register                           */\r
+  __IO uint8_t  SHP[12];                      /*!< System Handlers Priority Registers (4-7, 8-11, 12-15)    */\r
+  __IO uint32_t SHCSR;                        /*!< System Handler Control and State Register                */\r
+  __IO uint32_t CFSR;                         /*!< Configurable Fault Status Register                       */\r
+  __IO uint32_t HFSR;                         /*!< Hard Fault Status Register                               */\r
+  __IO uint32_t DFSR;                         /*!< Debug Fault Status Register                              */\r
+  __IO uint32_t MMFAR;                        /*!< Mem Manage Address Register                              */\r
+  __IO uint32_t BFAR;                         /*!< Bus Fault Address Register                               */\r
+  __IO uint32_t AFSR;                         /*!< Auxiliary Fault Status Register                          */\r
+  __I  uint32_t PFR[2];                       /*!< Processor Feature Register                               */\r
+  __I  uint32_t DFR;                          /*!< Debug Feature Register                                   */\r
+  __I  uint32_t ADR;                          /*!< Auxiliary Feature Register                               */\r
+  __I  uint32_t MMFR[4];                      /*!< Memory Model Feature Register                            */\r
+  __I  uint32_t ISAR[5];                      /*!< ISA Feature Register                                     */\r
+} SCB_Type;\r
+\r
+\r
+/* memory mapping struct for SysTick */\r
+typedef struct\r
+{\r
+  __IO uint32_t CTRL;                         /*!< SysTick Control and Status Register */\r
+  __IO uint32_t LOAD;                         /*!< SysTick Reload Value Register       */\r
+  __IO uint32_t VAL;                          /*!< SysTick Current Value Register      */\r
+  __I  uint32_t CALIB;                        /*!< SysTick Calibration Register        */\r
+} SysTick_Type;\r
+\r
+\r
+/* memory mapping structur for ITM */\r
+typedef struct\r
+{\r
+  __O  union  \r
+  {\r
+    __O  uint8_t    u8;                       /*!< ITM Stimulus Port 8-bit               */\r
+    __O  uint16_t   u16;                      /*!< ITM Stimulus Port 16-bit              */\r
+    __O  uint32_t   u32;                      /*!< ITM Stimulus Port 32-bit              */\r
+  }  PORT [32];                               /*!< ITM Stimulus Port Registers           */\r
+       uint32_t RESERVED0[864];\r
+  __IO uint32_t TER;                          /*!< ITM Trace Enable Register             */\r
+       uint32_t RESERVED1[15];\r
+  __IO uint32_t TPR;                          /*!< ITM Trace Privilege Register          */\r
+       uint32_t RESERVED2[15];\r
+  __IO uint32_t TCR;                          /*!< ITM Trace Control Register            */\r
+       uint32_t RESERVED3[29];\r
+  __IO uint32_t IWR;                          /*!< ITM Integration Write Register        */\r
+  __IO uint32_t IRR;                          /*!< ITM Integration Read Register         */\r
+  __IO uint32_t IMCR;                         /*!< ITM Integration Mode Control Register */\r
+       uint32_t RESERVED4[43];\r
+  __IO uint32_t LAR;                          /*!< ITM Lock Access Register              */\r
+  __IO uint32_t LSR;                          /*!< ITM Lock Status Register              */\r
+       uint32_t RESERVED5[6];\r
+  __I  uint32_t PID4;                         /*!< ITM Product ID Registers              */\r
+  __I  uint32_t PID5;\r
+  __I  uint32_t PID6;\r
+  __I  uint32_t PID7;\r
+  __I  uint32_t PID0;\r
+  __I  uint32_t PID1;\r
+  __I  uint32_t PID2;\r
+  __I  uint32_t PID3;\r
+  __I  uint32_t CID0;\r
+  __I  uint32_t CID1;\r
+  __I  uint32_t CID2;\r
+  __I  uint32_t CID3;\r
+} ITM_Type;\r
+\r
+\r
+/* memory mapped struct for Interrupt Type */\r
+typedef struct\r
+{\r
+       uint32_t RESERVED0;\r
+  __I  uint32_t ICTR;                         /*!< Interrupt Control Type Register  */\r
+#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))\r
+  __IO uint32_t ACTLR;                        /*!< Auxiliary Control Register       */\r
+#else\r
+       uint32_t RESERVED1;\r
+#endif\r
+} InterruptType_Type;\r
+\r
+\r
+/* Memory Protection Unit */\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)\r
+typedef struct\r
+{\r
+  __I  uint32_t TYPE;                         /*!< MPU Type Register                               */\r
+  __IO uint32_t CTRL;                         /*!< MPU Control Register                            */\r
+  __IO uint32_t RNR;                          /*!< MPU Region RNRber Register                      */\r
+  __IO uint32_t RBAR;                         /*!< MPU Region Base Address Register                */\r
+  __IO uint32_t RASR;                         /*!< MPU Region Attribute and Size Register          */\r
+  __IO uint32_t RBAR_A1;                      /*!< MPU Alias 1 Region Base Address Register        */\r
+  __IO uint32_t RASR_A1;                      /*!< MPU Alias 1 Region Attribute and Size Register  */\r
+  __IO uint32_t RBAR_A2;                      /*!< MPU Alias 2 Region Base Address Register        */\r
+  __IO uint32_t RASR_A2;                      /*!< MPU Alias 2 Region Attribute and Size Register  */\r
+  __IO uint32_t RBAR_A3;                      /*!< MPU Alias 3 Region Base Address Register        */\r
+  __IO uint32_t RASR_A3;                      /*!< MPU Alias 3 Region Attribute and Size Register  */\r
+} MPU_Type;\r
+#endif\r
+\r
+\r
+/* Core Debug Register */\r
+typedef struct\r
+{\r
+  __IO uint32_t DHCSR;                        /*!< Debug Halting Control and Status Register       */\r
+  __O  uint32_t DCRSR;                        /*!< Debug Core Register Selector Register           */\r
+  __IO uint32_t DCRDR;                        /*!< Debug Core Register Data Register               */\r
+  __IO uint32_t DEMCR;                        /*!< Debug Exception and Monitor Control Register    */\r
+} CoreDebug_Type;\r
+\r
+\r
+/* Memory mapping of Cortex-M3 Hardware */\r
+#define SCS_BASE            (0xE000E000)                              /*!< System Control Space Base Address    */\r
+#define ITM_BASE            (0xE0000000)                              /*!< ITM Base Address                     */\r
+#define CoreDebug_BASE      (0xE000EDF0)                              /*!< Core Debug Base Address              */\r
+#define SysTick_BASE        (SCS_BASE +  0x0010)                      /*!< SysTick Base Address                 */\r
+#define NVIC_BASE           (SCS_BASE +  0x0100)                      /*!< NVIC Base Address                    */\r
+#define SCB_BASE            (SCS_BASE +  0x0D00)                      /*!< System Control Block Base Address    */\r
+\r
+#define InterruptType       ((InterruptType_Type *) SCS_BASE)         /*!< Interrupt Type Register              */\r
+#define SCB                 ((SCB_Type *)           SCB_BASE)         /*!< SCB configuration struct             */\r
+#define SysTick             ((SysTick_Type *)       SysTick_BASE)     /*!< SysTick configuration struct         */\r
+#define NVIC                ((NVIC_Type *)          NVIC_BASE)        /*!< NVIC configuration struct            */\r
+#define ITM                 ((ITM_Type *)           ITM_BASE)         /*!< ITM configuration struct             */\r
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct      */\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)\r
+  #define MPU_BASE          (SCS_BASE +  0x0D90)                      /*!< Memory Protection Unit               */\r
+  #define MPU               ((MPU_Type*)            MPU_BASE)         /*!< Memory Protection Unit               */\r
+#endif\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ *                Hardware Abstraction Layer\r
+ ******************************************************************************/\r
+\r
+\r
+#if defined ( __CC_ARM   )\r
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */\r
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */\r
+\r
+#elif defined ( __ICCARM__ )\r
+  #define __ASM           __asm                                       /*!< asm keyword for IAR Compiler           */\r
+  #define __INLINE        inline                                      /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */\r
+  #define __NOP           __no_operation                              /*!< no operation intrinsic in IAR Compiler */\r
+\r
+#elif defined   (  __GNUC__  )\r
+  #define __ASM            asm                                        /*!< asm keyword for GNU Compiler          */\r
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */\r
+\r
+#endif\r
+\r
+\r
+/* ###################  Compiler specific Intrinsics  ########################### */\r
+\r
+#if defined ( __CC_ARM   ) /*------------------RealView Compiler -----------------*/\r
+/* ARM armcc specific functions */\r
+\r
+#define __enable_fault_irq                __enable_fiq\r
+#define __disable_fault_irq               __disable_fiq\r
+\r
+#define __NOP                             __nop\r
+#define __WFI                             __wfi\r
+#define __WFE                             __wfe\r
+#define __SEV                             __sev\r
+#define __ISB()                           __isb(0)\r
+#define __DSB()                           __dsb(0)\r
+#define __DMB()                           __dmb(0)\r
+#define __REV                             __rev\r
+#define __RBIT                            __rbit\r
+#define __LDREXB(ptr)                     ((unsigned char ) __ldrex(ptr))\r
+#define __LDREXH(ptr)                     ((unsigned short) __ldrex(ptr))\r
+#define __LDREXW(ptr)                     ((unsigned int  ) __ldrex(ptr))\r
+#define __STREXB(value, ptr)              __strex(value, ptr)\r
+#define __STREXH(value, ptr)              __strex(value, ptr)\r
+#define __STREXW(value, ptr)              __strex(value, ptr)\r
+\r
+\r
+  /* intrinsic unsigned long long __ldrexd(volatile void *ptr) */\r
+  /* intrinsic int __strexd(unsigned long long val, volatile void *ptr) */\r
+  /* intrinsic void __enable_irq();     */\r
+  /* intrinsic void __disable_irq();    */\r
+\r
+\r
+/**\r
+ * @brief  Return the Process Stack Pointer\r
+ *\r
+ * @param  none\r
+ * @return uint32_t ProcessStackPointer\r
+ *\r
+ * Return the actual process stack pointer\r
+ */\r
+extern uint32_t __get_PSP(void);\r
+\r
+/**\r
+ * @brief  Set the Process Stack Pointer\r
+ *\r
+ * @param  uint32_t Process Stack Pointer\r
+ * @return none\r
+ *\r
+ * Assign the value ProcessStackPointer to the MSP \r
+ * (process stack pointer) Cortex processor register\r
+ */\r
+extern void __set_PSP(uint32_t topOfProcStack);\r
+\r
+/**\r
+ * @brief  Return the Main Stack Pointer\r
+ *\r
+ * @param  none\r
+ * @return uint32_t Main Stack Pointer\r
+ *\r
+ * Return the current value of the MSP (main stack pointer)\r
+ * Cortex processor register\r
+ */\r
+extern uint32_t __get_MSP(void);\r
+\r
+/**\r
+ * @brief  Set the Main Stack Pointer\r
+ *\r
+ * @param  uint32_t Main Stack Pointer\r
+ * @return none\r
+ *\r
+ * Assign the value mainStackPointer to the MSP \r
+ * (main stack pointer) Cortex processor register\r
+ */\r
+extern void __set_MSP(uint32_t topOfMainStack);\r
+\r
+/**\r
+ * @brief  Reverse byte order in unsigned short value\r
+ *\r
+ * @param  uint16_t value to reverse\r
+ * @return uint32_t reversed value\r
+ *\r
+ * Reverse byte order in unsigned short value\r
+ */\r
+extern uint32_t __REV16(uint16_t value);\r
+\r
+/*\r
+ * @brief  Reverse byte order in signed short value with sign extension to integer\r
+ *\r
+ * @param  int16_t value to reverse\r
+ * @return int32_t reversed value\r
+ *\r
+ * Reverse byte order in signed short value with sign extension to integer\r
+ */\r
+extern int32_t __REVSH(int16_t value);\r
+\r
+\r
+#if (__ARMCC_VERSION < 400000)\r
+\r
+/**\r
+ * @brief  Remove the exclusive lock created by ldrex\r
+ *\r
+ * @param  none\r
+ * @return none\r
+ *\r
+ * Removes the exclusive lock which is created by ldrex.\r
+ */\r
+extern void __CLREX(void);\r
+\r
+/**\r
+ * @brief  Return the Base Priority value\r
+ *\r
+ * @param  none\r
+ * @return uint32_t BasePriority\r
+ *\r
+ * Return the content of the base priority register\r
+ */\r
+extern uint32_t __get_BASEPRI(void);\r
+\r
+/**\r
+ * @brief  Set the Base Priority value\r
+ *\r
+ * @param  uint32_t BasePriority\r
+ * @return none\r
+ *\r
+ * Set the base priority register\r
+ */\r
+extern void __set_BASEPRI(uint32_t basePri);\r
+\r
+/**\r
+ * @brief  Return the Priority Mask value\r
+ *\r
+ * @param  none\r
+ * @return uint32_t PriMask\r
+ *\r
+ * Return the state of the priority mask bit from the priority mask\r
+ * register\r
+ */\r
+extern uint32_t __get_PRIMASK(void);\r
+\r
+/**\r
+ * @brief  Set the Priority Mask value\r
+ *\r
+ * @param  uint32_t PriMask\r
+ * @return none\r
+ *\r
+ * Set the priority mask bit in the priority mask register\r
+ */\r
+extern void __set_PRIMASK(uint32_t priMask);\r
+\r
+/**\r
+ * @brief  Return the Fault Mask value\r
+ *\r
+ * @param  none\r
+ * @return uint32_t FaultMask\r
+ *\r
+ * Return the content of the fault mask register\r
+ */\r
+extern uint32_t __get_FAULTMASK(void);\r
+\r
+/**\r
+ * @brief  Set the Fault Mask value\r
+ *\r
+ * @param  uint32_t faultMask value\r
+ * @return none\r
+ *\r
+ * Set the fault mask register\r
+ */\r
+extern void __set_FAULTMASK(uint32_t faultMask);\r
+\r
+/**\r
+ * @brief  Return the Control Register value\r
+ * \r
+ * @param  none\r
+ * @return uint32_t Control value\r
+ *\r
+ * Return the content of the control register\r
+ */\r
+extern uint32_t __get_CONTROL(void);\r
+\r
+/**\r
+ * @brief  Set the Control Register value\r
+ *\r
+ * @param  uint32_t Control value\r
+ * @return none\r
+ *\r
+ * Set the control register\r
+ */\r
+extern void __set_CONTROL(uint32_t control);\r
+\r
+#else  /* (__ARMCC_VERSION >= 400000)  */\r
+\r
+\r
+/**\r
+ * @brief  Remove the exclusive lock created by ldrex\r
+ *\r
+ * @param  none\r
+ * @return none\r
+ *\r
+ * Removes the exclusive lock which is created by ldrex.\r
+ */\r
+#define __CLREX                           __clrex\r
+\r
+/**\r
+ * @brief  Return the Base Priority value\r
+ *\r
+ * @param  none\r
+ * @return uint32_t BasePriority\r
+ *\r
+ * Return the content of the base priority register\r
+ */\r
+static __INLINE uint32_t  __get_BASEPRI(void)\r
+{\r
+  register uint32_t __regBasePri         __ASM("basepri");\r
+  return(__regBasePri);\r
+}\r
+\r
+/**\r
+ * @brief  Set the Base Priority value\r
+ *\r
+ * @param  uint32_t BasePriority\r
+ * @return none\r
+ *\r
+ * Set the base priority register\r
+ */\r
+static __INLINE void __set_BASEPRI(uint32_t basePri)\r
+{\r
+  register uint32_t __regBasePri         __ASM("basepri");\r
+  __regBasePri = (basePri & 0x1ff);\r
+}\r
+\r
+/**\r
+ * @brief  Return the Priority Mask value\r
+ *\r
+ * @param  none\r
+ * @return uint32_t PriMask\r
+ *\r
+ * Return the state of the priority mask bit from the priority mask\r
+ * register\r
+ */\r
+static __INLINE uint32_t __get_PRIMASK(void)\r
+{\r
+  register uint32_t __regPriMask         __ASM("primask");\r
+  return(__regPriMask);\r
+}\r
+\r
+/**\r
+ * @brief  Set the Priority Mask value\r
+ *\r
+ * @param  uint32_t PriMask\r
+ * @return none\r
+ *\r
+ * Set the priority mask bit in the priority mask register\r
+ */\r
+static __INLINE void __set_PRIMASK(uint32_t priMask)\r
+{\r
+  register uint32_t __regPriMask         __ASM("primask");\r
+  __regPriMask = (priMask);\r
+}\r
+\r
+/**\r
+ * @brief  Return the Fault Mask value\r
+ *\r
+ * @param  none\r
+ * @return uint32_t FaultMask\r
+ *\r
+ * Return the content of the fault mask register\r
+ */\r
+static __INLINE uint32_t __get_FAULTMASK(void)\r
+{\r
+  register uint32_t __regFaultMask       __ASM("faultmask");\r
+  return(__regFaultMask);\r
+}\r
+\r
+/**\r
+ * @brief  Set the Fault Mask value\r
+ *\r
+ * @param  uint32_t faultMask value\r
+ * @return none\r
+ *\r
+ * Set the fault mask register\r
+ */\r
+static __INLINE void __set_FAULTMASK(uint32_t faultMask)\r
+{\r
+  register uint32_t __regFaultMask       __ASM("faultmask");\r
+  __regFaultMask = (faultMask & 1);\r
+}\r
+\r
+/**\r
+ * @brief  Return the Control Register value\r
+ * \r
+ * @param  none\r
+ * @return uint32_t Control value\r
+ *\r
+ * Return the content of the control register\r
+ */\r
+static __INLINE uint32_t __get_CONTROL(void)\r
+{\r
+  register uint32_t __regControl         __ASM("control");\r
+  return(__regControl);\r
+}\r
+\r
+/**\r
+ * @brief  Set the Control Register value\r
+ *\r
+ * @param  uint32_t Control value\r
+ * @return none\r
+ *\r
+ * Set the control register\r
+ */\r
+static __INLINE void __set_CONTROL(uint32_t control)\r
+{\r
+  register uint32_t __regControl         __ASM("control");\r
+  __regControl = control;\r
+}\r
+\r
+#endif /* __ARMCC_VERSION  */ \r
+\r
+\r
+\r
+#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/\r
+/* IAR iccarm specific functions */\r
+\r
+#define __enable_irq                              __enable_interrupt        /*!< global Interrupt enable */\r
+#define __disable_irq                             __disable_interrupt       /*!< global Interrupt disable */\r
+\r
+static __INLINE void __enable_fault_irq()         { __ASM ("cpsie f"); }\r
+static __INLINE void __disable_fault_irq()        { __ASM ("cpsid f"); }\r
+\r
+static __INLINE  void __WFI()                     { __ASM ("wfi"); }\r
+static __INLINE  void __WFE()                     { __ASM ("wfe"); }\r
+static __INLINE  void __SEV()                     { __ASM ("sev"); }\r
+static __INLINE  void __CLREX()                   { __ASM ("clrex"); }\r
+\r
+/**\r
+ * @brief  Return the Process Stack Pointer\r
+ *\r
+ * @param  none\r
+ * @return uint32_t ProcessStackPointer\r
+ *\r
+ * Return the actual process stack pointer\r
+ */\r
+extern uint32_t __get_PSP(void);\r
+\r
+/**\r
+ * @brief  Set the Process Stack Pointer\r
+ *\r
+ * @param  uint32_t Process Stack Pointer\r
+ * @return none\r
+ *\r
+ * Assign the value ProcessStackPointer to the MSP \r
+ * (process stack pointer) Cortex processor register\r
+ */\r
+extern void __set_PSP(uint32_t topOfProcStack);\r
+\r
+/**\r
+ * @brief  Return the Main Stack Pointer\r
+ *\r
+ * @param  none\r
+ * @return uint32_t Main Stack Pointer\r
+ *\r
+ * Return the current value of the MSP (main stack pointer)\r
+ * Cortex processor register\r
+ */\r
+extern uint32_t __get_MSP(void);\r
+\r
+/**\r
+ * @brief  Set the Main Stack Pointer\r
+ *\r
+ * @param  uint32_t Main Stack Pointer\r
+ * @return none\r
+ *\r
+ * Assign the value mainStackPointer to the MSP \r
+ * (main stack pointer) Cortex processor register\r
+ */\r
+extern void __set_MSP(uint32_t topOfMainStack);\r
+\r
+/**\r
+ * @brief  Reverse byte order in unsigned short value\r
+ *\r
+ * @param  uint16_t value to reverse\r
+ * @return uint32_t reversed value\r
+ *\r
+ * Reverse byte order in unsigned short value\r
+ */\r
+extern uint32_t __REV16(uint16_t value);\r
+\r
+/**\r
+ * @brief  Reverse bit order of value\r
+ *\r
+ * @param  uint32_t value to reverse\r
+ * @return uint32_t reversed value\r
+ *\r
+ * Reverse bit order of value\r
+ */\r
+extern uint32_t __RBIT(uint32_t value);\r
+\r
+/**\r
+ * @brief  LDR Exclusive\r
+ *\r
+ * @param  uint8_t* address\r
+ * @return uint8_t value of (*address)\r
+ *\r
+ * Exclusive LDR command\r
+ */\r
+extern uint8_t __LDREXB(uint8_t *addr);\r
+\r
+/**\r
+ * @brief  LDR Exclusive\r
+ *\r
+ * @param  uint16_t* address\r
+ * @return uint16_t value of (*address)\r
+ *\r
+ * Exclusive LDR command\r
+ */\r
+extern uint16_t __LDREXH(uint16_t *addr);\r
+\r
+/**\r
+ * @brief  LDR Exclusive\r
+ *\r
+ * @param  uint32_t* address\r
+ * @return uint32_t value of (*address)\r
+ *\r
+ * Exclusive LDR command\r
+ */\r
+extern uint32_t __LDREXW(uint32_t *addr);\r
+\r
+/**\r
+ * @brief  STR Exclusive\r
+ *\r
+ * @param  uint8_t *address\r
+ * @param  uint8_t value to store\r
+ * @return uint32_t successful / failed\r
+ *\r
+ * Exclusive STR command\r
+ */\r
+extern uint32_t __STREXB(uint8_t value, uint8_t *addr);\r
+\r
+/**\r
+ * @brief  STR Exclusive\r
+ *\r
+ * @param  uint16_t *address\r
+ * @param  uint16_t value to store\r
+ * @return uint32_t successful / failed\r
+ *\r
+ * Exclusive STR command\r
+ */\r
+extern uint32_t __STREXH(uint16_t value, uint16_t *addr);\r
+\r
+/**\r
+ * @brief  STR Exclusive\r
+ *\r
+ * @param  uint32_t *address\r
+ * @param  uint32_t value to store\r
+ * @return uint32_t successful / failed\r
+ *\r
+ * Exclusive STR command\r
+ */\r
+extern uint32_t __STREXW(uint32_t value, uint32_t *addr);\r
+\r
+\r
+/* intrinsic void __set_PRIMASK();                                    */\r
+/* intrinsic void __get_PRIMASK();                                    */\r
+/* intrinsic void __set_FAULTMASK();                                  */\r
+/* intrinsic void __get_FAULTMASK();                                  */\r
+/* intrinsic uint32_t __REV(uint32_t value);                          */\r
+/* intrinsic uint32_t __REVSH(uint32_t value);                        */\r
+/* intrinsic unsigned long __STREX(unsigned long, unsigned long);     */\r
+/* intrinsic unsigned long __LDREX(unsigned long *);                  */\r
+\r
+\r
+\r
+#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/\r
+/* GNU gcc specific functions */\r
+\r
+static __INLINE void __NOP()                      { __ASM volatile ("nop"); }\r
+static __INLINE void __enable_irq()               { __ASM volatile ("cpsie i"); }\r
+static __INLINE void __disable_irq()              { __ASM volatile ("cpsid i"); }\r
+\r
+static __INLINE void __enable_fault_irq()         { __ASM volatile ("cpsie f"); }\r
+static __INLINE void __disable_fault_irq()        { __ASM volatile ("cpsid f"); }\r
+\r
+static __INLINE void __WFI()                      { __ASM volatile ("wfi");   }\r
+static __INLINE void __WFE()                      { __ASM volatile ("wfe");   }\r
+static __INLINE void __SEV()                      { __ASM volatile ("sev");   }\r
+static __INLINE void __ISB(arg)                   { __ASM volatile ("isb");   }\r
+static __INLINE void __DSB(arg)                   { __ASM volatile ("dsb");   }\r
+static __INLINE void __DMB(arg)                   { __ASM volatile ("dmb");   }\r
+static __INLINE void __CLREX()                    { __ASM volatile ("clrex"); }\r
+\r
+\r
+/**\r
+ * @brief  Return the Process Stack Pointer\r
+ *\r
+ * @param  none\r
+ * @return uint32_t ProcessStackPointer\r
+ *\r
+ * Return the actual process stack pointer\r
+ */\r
+extern uint32_t __get_PSP(void);\r
+\r
+/**\r
+ * @brief  Set the Process Stack Pointer\r
+ *\r
+ * @param  uint32_t Process Stack Pointer\r
+ * @return none\r
+ *\r
+ * Assign the value ProcessStackPointer to the MSP \r
+ * (process stack pointer) Cortex processor register\r
+ */\r
+extern void __set_PSP(uint32_t topOfProcStack);\r
+\r
+/**\r
+ * @brief  Return the Main Stack Pointer\r
+ *\r
+ * @param  none\r
+ * @return uint32_t Main Stack Pointer\r
+ *\r
+ * Return the current value of the MSP (main stack pointer)\r
+ * Cortex processor register\r
+ */\r
+extern uint32_t __get_MSP(void);\r
+\r
+/**\r
+ * @brief  Set the Main Stack Pointer\r
+ *\r
+ * @param  uint32_t Main Stack Pointer\r
+ * @return none\r
+ *\r
+ * Assign the value mainStackPointer to the MSP \r
+ * (main stack pointer) Cortex processor register\r
+ */\r
+extern void __set_MSP(uint32_t topOfMainStack);\r
+\r
+/**\r
+ * @brief  Return the Base Priority value\r
+ *\r
+ * @param  none\r
+ * @return uint32_t BasePriority\r
+ *\r
+ * Return the content of the base priority register\r
+ */\r
+extern uint32_t __get_BASEPRI(void);\r
+\r
+/**\r
+ * @brief  Set the Base Priority value\r
+ *\r
+ * @param  uint32_t BasePriority\r
+ * @return none\r
+ *\r
+ * Set the base priority register\r
+ */\r
+extern void __set_BASEPRI(uint32_t basePri);\r
+\r
+/**\r
+ * @brief  Return the Priority Mask value\r
+ *\r
+ * @param  none\r
+ * @return uint32_t PriMask\r
+ *\r
+ * Return the state of the priority mask bit from the priority mask\r
+ * register\r
+ */\r
+extern uint32_t  __get_PRIMASK(void);\r
+\r
+/**\r
+ * @brief  Set the Priority Mask value\r
+ *\r
+ * @param  uint32_t PriMask\r
+ * @return none\r
+ *\r
+ * Set the priority mask bit in the priority mask register\r
+ */\r
+extern void __set_PRIMASK(uint32_t priMask);\r
+\r
+/**\r
+ * @brief  Return the Fault Mask value\r
+ *\r
+ * @param  none\r
+ * @return uint32_t FaultMask\r
+ *\r
+ * Return the content of the fault mask register\r
+ */\r
+extern uint32_t __get_FAULTMASK(void);\r
+\r
+/**\r
+ * @brief  Set the Fault Mask value\r
+ *\r
+ * @param  uint32_t faultMask value\r
+ * @return none\r
+ *\r
+ * Set the fault mask register\r
+ */\r
+extern void __set_FAULTMASK(uint32_t faultMask);\r
+\r
+/**\r
+ * @brief  Return the Control Register value\r
+* \r
+*  @param  none\r
+*  @return uint32_t Control value\r
+ *\r
+ * Return the content of the control register\r
+ */\r
+extern uint32_t __get_CONTROL(void);\r
+\r
+/**\r
+ * @brief  Set the Control Register value\r
+ *\r
+ * @param  uint32_t Control value\r
+ * @return none\r
+ *\r
+ * Set the control register\r
+ */\r
+extern void __set_CONTROL(uint32_t control);\r
+\r
+/**\r
+ * @brief  Reverse byte order in integer value\r
+ *\r
+ * @param  uint32_t value to reverse\r
+ * @return uint32_t reversed value\r
+ *\r
+ * Reverse byte order in integer value\r
+ */\r
+extern uint32_t __REV(uint32_t value);\r
+\r
+/**\r
+ * @brief  Reverse byte order in unsigned short value\r
+ *\r
+ * @param  uint16_t value to reverse\r
+ * @return uint32_t reversed value\r
+ *\r
+ * Reverse byte order in unsigned short value\r
+ */\r
+extern uint32_t __REV16(uint16_t value);\r
+\r
+/*\r
+ * Reverse byte order in signed short value with sign extension to integer\r
+ *\r
+ * @param  int16_t value to reverse\r
+ * @return int32_t reversed value\r
+ *\r
+ * @brief  Reverse byte order in signed short value with sign extension to integer\r
+ */\r
+extern int32_t __REVSH(int16_t value);\r
+\r
+/**\r
+ * @brief  Reverse bit order of value\r
+ *\r
+ * @param  uint32_t value to reverse\r
+ * @return uint32_t reversed value\r
+ *\r
+ * Reverse bit order of value\r
+ */\r
+extern uint32_t __RBIT(uint32_t value);\r
+\r
+/**\r
+ * @brief  LDR Exclusive\r
+ *\r
+ * @param  uint8_t* address\r
+ * @return uint8_t value of (*address)\r
+ *\r
+ * Exclusive LDR command\r
+ */\r
+extern uint8_t __LDREXB(uint8_t *addr);\r
+\r
+/**\r
+ * @brief  LDR Exclusive\r
+ *\r
+ * @param  uint16_t* address\r
+ * @return uint16_t value of (*address)\r
+ *\r
+ * Exclusive LDR command\r
+ */\r
+extern uint16_t __LDREXH(uint16_t *addr);\r
+\r
+/**\r
+ * @brief  LDR Exclusive\r
+ *\r
+ * @param  uint32_t* address\r
+ * @return uint32_t value of (*address)\r
+ *\r
+ * Exclusive LDR command\r
+ */\r
+extern uint32_t __LDREXW(uint32_t *addr);\r
+\r
+/**\r
+ * @brief  STR Exclusive\r
+ *\r
+ * @param  uint8_t *address\r
+ * @param  uint8_t value to store\r
+ * @return uint32_t successful / failed\r
+ *\r
+ * Exclusive STR command\r
+ */\r
+extern uint32_t __STREXB(uint8_t value, uint8_t *addr);\r
+\r
+/**\r
+ * @brief  STR Exclusive\r
+ *\r
+ * @param  uint16_t *address\r
+ * @param  uint16_t value to store\r
+ * @return uint32_t successful / failed\r
+ *\r
+ * Exclusive STR command\r
+ */\r
+extern uint32_t __STREXH(uint16_t value, uint16_t *addr);\r
+\r
+/**\r
+ * @brief  STR Exclusive\r
+ *\r
+ * @param  uint32_t *address\r
+ * @param  uint32_t value to store\r
+ * @return uint32_t successful / failed\r
+ *\r
+ * Exclusive STR command\r
+ */\r
+extern uint32_t __STREXW(uint32_t value, uint32_t *addr);\r
+\r
+\r
+#endif\r
+\r
+\r
+\r
+/* ##########################   NVIC functions  #################################### */\r
+\r
+/**\r
+ * @brief  Set the Priority Grouping in NVIC Interrupt Controller\r
+ *\r
+ * @param  uint32_t priority_grouping is priority grouping field\r
+ * @return  \r
+ *\r
+ * Set the priority grouping field using the required unlock sequence.\r
+ * The parameter priority_grouping is assigned to the field \r
+ * SCB->AIRCR [10:8] PRIGROUP field.\r
+ */\r
+static __INLINE void NVIC_SetPriorityGrouping(uint32_t priority_grouping)\r
+{\r
+  uint32_t reg_value=0;\r
+  \r
+  reg_value  = SCB->AIRCR;                                                                            /* read old register configuration    */\r
+  reg_value &= ~((0xFFFFU << 16) | (0x0F << 8));                                                      /* clear bits to change               */\r
+  reg_value  = ((reg_value | NVIC_AIRCR_VECTKEY | (priority_grouping << 8)));                         /* Insert write key and priorty group */\r
+  SCB->AIRCR = reg_value;\r
+}\r
+\r
+/**\r
+ * @brief  Enable Interrupt in NVIC Interrupt Controller\r
+ *\r
+ * @param  IRQn_Type IRQn specifies the interrupt number\r
+ * @return none \r
+ *\r
+ * Enable a device specific interupt in the NVIC interrupt controller.\r
+ * The interrupt number cannot be a negative value.\r
+ */\r
+static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)\r
+{\r
+  NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));                             /* enable interrupt */\r
+}\r
+\r
+/**\r
+ * @brief  Disable the interrupt line for external interrupt specified\r
+ * \r
+ * @param  IRQn_Type IRQn is the positive number of the external interrupt\r
+ * @return  none\r
+ * \r
+ * Disable a device specific interupt in the NVIC interrupt controller.\r
+ * The interrupt number cannot be a negative value.\r
+ */\r
+static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)\r
+{\r
+  NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));                             /* disable interrupt */\r
+}\r
+\r
+/**\r
+ * @brief  Read the interrupt pending bit for a device specific interrupt source\r
+ * \r
+ * @param  IRQn_Type IRQn is the number of the device specifc interrupt\r
+ * @return IRQn_Type Number of pending interrupt or zero\r
+ *\r
+ * Read the pending register in NVIC and return the number of the\r
+ * specified interrupt if its status is pending, otherwise it returns \r
+ * zero. The interrupt number cannot be a negative value.\r
+ */\r
+static __INLINE IRQn_Type NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+  return((IRQn_Type) (NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F))));         /* Return Interrupt bit or 'zero' */\r
+}\r
+\r
+/**\r
+ * @brief  Set the pending bit for an external interrupt\r
+ * \r
+ * @param  IRQn_Type IRQn is the Number of the interrupt\r
+ * @return  none\r
+ *\r
+ * Set the pending bit for the specified interrupt.\r
+ * The interrupt number cannot be a negative value.\r
+ */\r
+static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+  NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));                             /* set interrupt pending */\r
+}\r
+\r
+/**\r
+ * @brief  Clear the pending bit for an external interrupt\r
+ *\r
+ * @param  IRQn_Type IRQn is the Number of the interrupt\r
+ * @return  none\r
+ *\r
+ * Clear the pending bit for the specified interrupt. \r
+ * The interrupt number cannot be a negative value.\r
+ */\r
+static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
+{\r
+  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));                             /* Clear pending interrupt */\r
+}\r
+\r
+/**\r
+ * @brief  Read the active bit for an external interrupt\r
+ *\r
+ * @param  IRQn_Type IRQn is the Number of the interrupt\r
+ * @return IRQn_Type Number of pending interrupt or zero\r
+ *\r
+ * Read the active register in NVIC and returns the number of the\r
+ * specified interrupt if its status is active, otherwise it \r
+ * returns zero. The interrupt number cannot be a negative value.\r
+ */\r
+static __INLINE IRQn_Type NVIC_GetActive(IRQn_Type IRQn)\r
+{\r
+  return((IRQn_Type)(NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F))));                        /* Return Interruptnumber or 'zero' */\r
+}\r
+\r
+/**\r
+ * @brief  Set the priority for an interrupt\r
+ *\r
+ * @param  IRQn_Type IRQn is the Number of the interrupt\r
+ * @param  priority is the priority for the interrupt\r
+ * @return  none\r
+ *\r
+ * Set the priority for the specified interrupt. The interrupt \r
+ * number can be positive to specify an external (device specific) \r
+ * interrupt, or negative to specify an internal (core) interrupt. \n\r
+ *\r
+ * Note: The priority cannot be set for every core interrupt.\r
+ */\r
+static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, int32_t priority)\r
+{\r
+  if(IRQn < 0) {\r
+    SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); }  /* set Priority for Cortex-M3 System Interrupts */\r
+  else {\r
+    //NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);    }         /* set Priority for device specific Interrupts      */\r
+    NVIC->IP[(uint32_t)(IRQn)] = (priority & 0xff);    }         /* set Priority for device specific Interrupts      */\r
+}\r
+\r
+/**\r
+ * @brief  Read the priority for an interrupt\r
+ *\r
+ * @param  IRQn_Type IRQn is the Number of the interrupt\r
+ * @return priority is the priority for the interrupt\r
+ *\r
+ * Read the priority for the specified interrupt. The interrupt \r
+ * number can be positive to specify an external (device specific) \r
+ * interrupt, or negative to specify an internal (core) interrupt.\r
+ *\r
+ * The returned priority value is automatically aligned to the implemented\r
+ * priority bits of the microcontroller.\r
+ *\r
+ * Note: The priority cannot be set for every core interrupt.\r
+ */\r
+static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)\r
+{\r
+\r
+  if(IRQn < 0) {\r
+    return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS)));  }              /* get priority for Cortex-M3 system interrupts   */\r
+  else {\r
+    return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)]           >> (8 - __NVIC_PRIO_BITS)));  }              /* get priority for device specific interrupts    */\r
+}\r
+\r
+\r
+\r
+/* ##################################    SysTick function  ############################################ */\r
+\r
+#if (!defined (__Vendor_SysTickConfig)) || (__Vendor_SysTickConfig == 0)\r
+\r
+/* SysTick constants */\r
+#define SYSTICK_ENABLE              0                                          /* Config-Bit to start or stop the SysTick Timer                         */\r
+#define SYSTICK_TICKINT             1                                          /* Config-Bit to enable or disable the SysTick interrupt                 */\r
+#define SYSTICK_CLKSOURCE           2                                          /* Clocksource has the offset 2 in SysTick Control and Status Register   */\r
+#define SYSTICK_MAXCOUNT       ((1<<24) -1)                                    /* SysTick MaxCount                                                      */\r
+\r
+/**\r
+ * @brief  Initialize and start the SysTick counter and its interrupt.\r
+ *\r
+ * @param  uint32_t ticks is the number of ticks between two interrupts\r
+ * @return  none\r
+ *\r
+ * Initialise the system tick timer and its interrupt and start the\r
+ * system tick timer / counter in free running mode to generate \r
+ * periodical interrupts.\r
+ */\r
+static __INLINE uint32_t SysTick_Config(uint32_t ticks)\r
+{ \r
+  if (ticks > SYSTICK_MAXCOUNT)  return (1);                                                /* Reload value impossible */\r
+\r
+  SysTick->LOAD  =  (ticks & SYSTICK_MAXCOUNT) - 1;                                         /* set reload register */\r
+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);                               /* set Priority for Cortex-M0 System Interrupts */\r
+  SysTick->VAL   =  (0x00);                                                                 /* Load the SysTick Counter Value */\r
+  SysTick->CTRL = (1 << SYSTICK_CLKSOURCE) | (1<<SYSTICK_ENABLE) | (1<<SYSTICK_TICKINT);    /* Enable SysTick IRQ and SysTick Timer */\r
+  return (0);                                                                               /* Function successful */\r
+}\r
+\r
+#endif\r
+\r
+\r
+\r
+\r
+\r
+/* ##################################    Reset function  ############################################ */\r
+\r
+/**\r
+ * @brief  Initiate a system reset request.\r
+ *\r
+ * @param   none\r
+ * @return  none\r
+ *\r
+ * Initialize a system reset request to reset the MCU\r
+ */\r
+static __INLINE void NVIC_SystemReset(void)\r
+{\r
+  SCB->AIRCR  = (NVIC_AIRCR_VECTKEY | (SCB->AIRCR & (0x700)) | (1<<NVIC_SYSRESETREQ));      /* Keep priority group unchanged */\r
+}\r
+\r
+\r
+/* ##################################    Debug Output  function  ############################################ */\r
+\r
+\r
+/**\r
+ * @brief  Outputs a character via the ITM channel 0\r
+ *\r
+ * @param   uint32_t character to output\r
+ * @return  uint32_t input character\r
+ *\r
+ * The function outputs a character via the ITM channel 0. \r
+ * The function returns when no debugger is connected that has booked the output.  \r
+ * It is blocking when a debugger is connected, but the previous character send is not transmitted. \r
+ */\r
+static __INLINE uint32_t ITM_SendChar (uint32_t ch)\r
+{\r
+  if(ch == '\n') ITM_SendChar('\r');\r
+  \r
+  if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA)  &&\r
+      (ITM->TCR & ITM_TCR_ITMENA)                  &&\r
+      (ITM->TER & (1UL << 0))  ) \r
+  {\r
+    while (ITM->PORT[0].u32 == 0);\r
+    ITM->PORT[0].u8 = (uint8_t) ch;\r
+  }  \r
+  return (ch);\r
+}\r
+\r
+#endif\r
+\r
+/*lint -restore */\r

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/components/hx8347/hx8347.c b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/components/hx8347/hx8347.c
new file mode 100644 (file)
index 0000000..6c99d52
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/components/hx8347/hx8347.c
@@ -0,0 +1,376 @@
+/* ----------------------------------------------------------------------------\r
+ *         ATMEL Microcontroller Software Support\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+//------------------------------------------------------------------------------\r
+/// \unit\r
+///\r
+/// !Purpose\r
+///\r
+/// HX8347 driver\r
+///\r
+/// !Usage\r
+///\r
+/// Explanation on the usage of the code made available through the header file.\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+//         Headers\r
+//------------------------------------------------------------------------------\r
+#include <board.h>\r
+#include <stdio.h>\r
+\r
+#ifdef BOARD_LCD_HX8347\r
+\r
+#include "hx8347.h"\r
+\r
+//------------------------------------------------------------------------------\r
+//         Types\r
+//------------------------------------------------------------------------------\r
+typedef volatile unsigned short REG16;\r
+\r
+//------------------------------------------------------------------------------\r
+//         Definitions\r
+//------------------------------------------------------------------------------\r
+/// LCD index register address\r
+#define LCD_IR(baseAddr) (*((REG16 *)(baseAddr)))\r
+/// LCD status register address\r
+#define LCD_SR(baseAddr) (*((REG16 *)(baseAddr)))\r
+/// LCD data address\r
+#define LCD_D(baseAddr)  (*((REG16 *)((unsigned int)(baseAddr) + BOARD_LCD_RS)))\r
+\r
+/// HX8347 ID code\r
+#define HX8347_HIMAXID_CODE    0x47\r
+\r
+/// HX8347 LCD Registers\r
+#define HX8347_R00H        0x00\r
+#define HX8347_R01H        0x01\r
+#define HX8347_R02H        0x02\r
+#define HX8347_R03H        0x03\r
+#define HX8347_R04H        0x04\r
+#define HX8347_R05H        0x05\r
+#define HX8347_R06H        0x06\r
+#define HX8347_R07H        0x07\r
+#define HX8347_R08H        0x08\r
+#define HX8347_R09H        0x09\r
+#define HX8347_R0AH        0x0A\r
+#define HX8347_R0CH        0x0C\r
+#define HX8347_R0DH        0x0D\r
+#define HX8347_R0EH        0x0E\r
+#define HX8347_R0FH        0x0F\r
+#define HX8347_R10H        0x10\r
+#define HX8347_R11H        0x11\r
+#define HX8347_R12H        0x12\r
+#define HX8347_R13H        0x13\r
+#define HX8347_R14H        0x14\r
+#define HX8347_R15H        0x15\r
+#define HX8347_R16H        0x16\r
+#define HX8347_R18H        0x18\r
+#define HX8347_R19H        0x19\r
+#define HX8347_R1AH        0x1A\r
+#define HX8347_R1BH        0x1B\r
+#define HX8347_R1CH        0x1C\r
+#define HX8347_R1DH        0x1D\r
+#define HX8347_R1EH        0x1E\r
+#define HX8347_R1FH        0x1F\r
+#define HX8347_R20H        0x20\r
+#define HX8347_R21H        0x21\r
+#define HX8347_R22H        0x22\r
+#define HX8347_R23H        0x23\r
+#define HX8347_R24H        0x24\r
+#define HX8347_R25H        0x25\r
+#define HX8347_R26H        0x26\r
+#define HX8347_R27H        0x27\r
+#define HX8347_R28H        0x28\r
+#define HX8347_R29H        0x29\r
+#define HX8347_R2AH        0x2A\r
+#define HX8347_R2BH        0x2B\r
+#define HX8347_R2CH        0x2C\r
+#define HX8347_R2DH        0x2D\r
+#define HX8347_R35H        0x35\r
+#define HX8347_R36H        0x36\r
+#define HX8347_R37H        0x37\r
+#define HX8347_R38H        0x38\r
+#define HX8347_R39H        0x39\r
+#define HX8347_R3AH        0x3A\r
+#define HX8347_R3BH        0x3B\r
+#define HX8347_R3CH        0x3C\r
+#define HX8347_R3DH        0x3D\r
+#define HX8347_R3EH        0x3E\r
+#define HX8347_R40H        0x40\r
+#define HX8347_R41H        0x41\r
+#define HX8347_R42H        0x42\r
+#define HX8347_R43H        0x43\r
+#define HX8347_R44H        0x44\r
+#define HX8347_R45H        0x45\r
+#define HX8347_R46H        0x46\r
+#define HX8347_R47H        0x47\r
+#define HX8347_R48H        0x48\r
+#define HX8347_R49H        0x49\r
+#define HX8347_R4AH        0x4A\r
+#define HX8347_R4BH        0x4B\r
+#define HX8347_R4CH        0x4C\r
+#define HX8347_R4DH        0x4D\r
+#define HX8347_R4EH        0x4E\r
+#define HX8347_R4FH        0x4F\r
+#define HX8347_R50H        0x50\r
+#define HX8347_R51H        0x51\r
+#define HX8347_R64H        0x64\r
+#define HX8347_R65H        0x65\r
+#define HX8347_R66H        0x66\r
+#define HX8347_R67H        0x67\r
+#define HX8347_R70H        0x70\r
+#define HX8347_R72H        0x72\r
+#define HX8347_R90H        0x90\r
+#define HX8347_R91H        0x91\r
+#define HX8347_R93H        0x93\r
+#define HX8347_R94H        0x94\r
+#define HX8347_R95H        0x95\r
+\r
+//------------------------------------------------------------------------------\r
+//         External functions\r
+//------------------------------------------------------------------------------\r
+// External delay 1 ms function\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#define Delay(ms) vTaskDelay(ms/portTICK_RATE_MS)\r
+\r
+//------------------------------------------------------------------------------\r
+//         Global functions\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+/// Write data to LCD Register.\r
+/// \param pLcdBase   LCD base address.\r
+/// \param reg        Register address.\r
+/// \param data       Data to be written.\r
+//------------------------------------------------------------------------------\r
+void LCD_WriteReg(void *pLcdBase, unsigned char reg, unsigned short data)\r
+{\r
+    LCD_IR(pLcdBase) = reg;\r
+    LCD_D(pLcdBase)  = data;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Read data from LCD Register.\r
+/// \param pLcdBase   LCD base address.\r
+/// \param reg        Register address.\r
+/// \return data      Data to be read.\r
+//------------------------------------------------------------------------------\r
+unsigned short LCD_ReadReg(void *pLcdBase, unsigned char reg)\r
+{\r
+    LCD_IR(pLcdBase) = reg;\r
+    return LCD_D(pLcdBase);\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Read LCD status Register.\r
+/// \param pLcdBase   LCD base address.\r
+/// \param reg        Register address.\r
+/// \return data      Status Data.\r
+//------------------------------------------------------------------------------\r
+unsigned short LCD_ReadStatus(void *pLcdBase)\r
+{\r
+    return LCD_SR(pLcdBase);\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Prepare to write GRAM data.\r
+/// \param pLcdBase   LCD base address.\r
+//------------------------------------------------------------------------------\r
+void LCD_WriteRAM_Prepare(void *pLcdBase)\r
+{\r
+    LCD_IR(pLcdBase) = HX8347_R22H;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Write data to LCD GRAM.\r
+/// \param pLcdBase   LCD base address.\r
+/// \param color      16-bits RGB color.\r
+//------------------------------------------------------------------------------\r
+void LCD_WriteRAM(void *pLcdBase, unsigned short color)\r
+{\r
+    // Write 16-bit GRAM Reg\r
+    LCD_D(pLcdBase) = color;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Read GRAM data.\r
+/// \param pLcdBase   LCD base address.\r
+/// \return           16-bits RGB color.\r
+//------------------------------------------------------------------------------\r
+unsigned short LCD_ReadRAM(void *pLcdBase)\r
+{\r
+    // Read 16-bit GRAM Reg\r
+    return LCD_D(pLcdBase);\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Dump register data.\r
+/// \param pLcdBase   LCD base address.\r
+/// \param startAddr  Register start address.\r
+/// \param endAddr    Register end address.\r
+//------------------------------------------------------------------------------\r
+void LCD_DumpReg(void *pLcdBase, unsigned char startAddr, unsigned char endAddr)\r
+{\r
+    unsigned short tmp;\r
+    unsigned char addr;\r
+\r
+    for (addr = startAddr; addr <= endAddr; addr++) {\r
+\r
+        tmp = LCD_ReadReg(pLcdBase, addr);\r
+        printf("LCD.r 0x%x = 0x%x\n\r", addr, tmp);\r
+    }\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Initialize the LCD controller.\r
+/// \param pLcdBase   LCD base address.\r
+//------------------------------------------------------------------------------\r
+void LCD_Initialize(void *pLcdBase)\r
+{\r
+    unsigned short chipid;\r
+\r
+    // Check HX8347 chipid\r
+    chipid = LCD_ReadReg(pLcdBase, HX8347_R67H);\r
+    if(chipid != HX8347_HIMAXID_CODE) {\r
+\r
+        printf("Read HX8347 chip ID error, skip initialization.\r\n");\r
+        return ;\r
+    }\r
+\r
+    // Start internal OSC\r
+    LCD_WriteReg(pLcdBase, HX8347_R19H, 0x49); // OSCADJ=10 0000, OSD_EN=1 //60Hz\r
+    LCD_WriteReg(pLcdBase, HX8347_R93H, 0x0C); // RADJ=1100\r
+\r
+    // Power on flow\r
+    LCD_WriteReg(pLcdBase, HX8347_R44H, 0x4D); // VCM=100 1101\r
+    LCD_WriteReg(pLcdBase, HX8347_R45H, 0x11); // VDV=1 0001\r
+    LCD_WriteReg(pLcdBase, HX8347_R20H, 0x40); // BT=0100\r
+    LCD_WriteReg(pLcdBase, HX8347_R1DH, 0x07); // VC1=111\r
+    LCD_WriteReg(pLcdBase, HX8347_R1EH, 0x00); // VC3=000\r
+    LCD_WriteReg(pLcdBase, HX8347_R1FH, 0x04); // VRH=0100\r
+\r
+    LCD_WriteReg(pLcdBase, HX8347_R1CH, 0x04); // AP=100\r
+    LCD_WriteReg(pLcdBase, HX8347_R1BH, 0x10); // GASENB=0, PON=1, DK=0, XDK=0, DDVDH_TRI=0, STB=0\r
+    Delay(50);\r
+\r
+    LCD_WriteReg(pLcdBase, HX8347_R43H, 0x80); // Set VCOMG=1\r
+    Delay(50);\r
+\r
+    // Gamma for CMO 2.8\r
+    LCD_WriteReg(pLcdBase, HX8347_R46H, 0x95);\r
+    LCD_WriteReg(pLcdBase, HX8347_R47H, 0x51);\r
+    LCD_WriteReg(pLcdBase, HX8347_R48H, 0x00);\r
+    LCD_WriteReg(pLcdBase, HX8347_R49H, 0x36);\r
+    LCD_WriteReg(pLcdBase, HX8347_R4AH, 0x11);\r
+    LCD_WriteReg(pLcdBase, HX8347_R4BH, 0x66);\r
+    LCD_WriteReg(pLcdBase, HX8347_R4CH, 0x14);\r
+    LCD_WriteReg(pLcdBase, HX8347_R4DH, 0x77);\r
+    LCD_WriteReg(pLcdBase, HX8347_R4EH, 0x13);\r
+    LCD_WriteReg(pLcdBase, HX8347_R4FH, 0x4C);\r
+    LCD_WriteReg(pLcdBase, HX8347_R50H, 0x46);\r
+    LCD_WriteReg(pLcdBase, HX8347_R51H, 0x46);\r
+\r
+    //240x320 window setting\r
+    LCD_WriteReg(pLcdBase, HX8347_R02H, 0x00); // Column address start2\r
+    LCD_WriteReg(pLcdBase, HX8347_R03H, 0x00); // Column address start1\r
+    LCD_WriteReg(pLcdBase, HX8347_R04H, 0x00); // Column address end2\r
+    LCD_WriteReg(pLcdBase, HX8347_R05H, 0xEF); // Column address end1\r
+    LCD_WriteReg(pLcdBase, HX8347_R06H, 0x00); // Row address start2\r
+    LCD_WriteReg(pLcdBase, HX8347_R07H, 0x00); // Row address start1\r
+    LCD_WriteReg(pLcdBase, HX8347_R08H, 0x01); // Row address end2\r
+    LCD_WriteReg(pLcdBase, HX8347_R09H, 0x3F); // Row address end1\r
+\r
+    // Display Setting\r
+    LCD_WriteReg(pLcdBase, HX8347_R01H, 0x06); // IDMON=0, INVON=1, NORON=1, PTLON=0\r
+    LCD_WriteReg(pLcdBase, HX8347_R16H, 0xC8); // MY=1, MX=1, MV=0, BGR=1\r
+    LCD_WriteReg(pLcdBase, HX8347_R23H, 0x95); // N_DC=1001 0101\r
+    LCD_WriteReg(pLcdBase, HX8347_R24H, 0x95); // P_DC=1001 0101\r
+    LCD_WriteReg(pLcdBase, HX8347_R25H, 0xFF); // I_DC=1111 1111\r
+    LCD_WriteReg(pLcdBase, HX8347_R27H, 0x06); // N_BP=0000 0110\r
+    LCD_WriteReg(pLcdBase, HX8347_R28H, 0x06); // N_FP=0000 0110\r
+    LCD_WriteReg(pLcdBase, HX8347_R29H, 0x06); // P_BP=0000 0110\r
+    LCD_WriteReg(pLcdBase, HX8347_R2AH, 0x06); // P_FP=0000 0110\r
+    LCD_WriteReg(pLcdBase, HX8347_R2CH, 0x06); // I_BP=0000 0110\r
+    LCD_WriteReg(pLcdBase, HX8347_R2DH, 0x06); // I_FP=0000 0110\r
+    LCD_WriteReg(pLcdBase, HX8347_R3AH, 0x01); // N_RTN=0000, N_NW=001\r
+    LCD_WriteReg(pLcdBase, HX8347_R3BH, 0x01); // P_RTN=0000, P_NW=001\r
+    LCD_WriteReg(pLcdBase, HX8347_R3CH, 0xF0); // I_RTN=1111, I_NW=000\r
+    LCD_WriteReg(pLcdBase, HX8347_R3DH, 0x00); // DIV=00\r
+    LCD_WriteReg(pLcdBase, HX8347_R3EH, 0x38); // SON=38h\r
+    LCD_WriteReg(pLcdBase, HX8347_R40H, 0x0F); // GDON=0Fh\r
+    LCD_WriteReg(pLcdBase, HX8347_R41H, 0xF0); // GDOF=F0h\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Turn on the LCD.\r
+/// \param pLcdBase   LCD base address.\r
+//------------------------------------------------------------------------------\r
+void LCD_On(void *pLcdBase)\r
+{\r
+    // Display ON Setting\r
+    LCD_WriteReg(pLcdBase, HX8347_R90H, 0x7F); // SAP=0111 1111\r
+    LCD_WriteReg(pLcdBase, HX8347_R26H, 0x04); // GON=0, DTE=0, D=01\r
+    Delay(100);\r
+    LCD_WriteReg(pLcdBase, HX8347_R26H, 0x24); // GON=1, DTE=0, D=01\r
+    LCD_WriteReg(pLcdBase, HX8347_R26H, 0x2C); // GON=1, DTE=0, D=11\r
+    Delay(100);\r
+    LCD_WriteReg(pLcdBase, HX8347_R26H, 0x3C); // GON=1, DTE=1, D=11\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Turn off the LCD.\r
+/// \param pLcdBase   LCD base address.\r
+//------------------------------------------------------------------------------\r
+void LCD_Off(void *pLcdBase)\r
+{\r
+    LCD_WriteReg(pLcdBase, HX8347_R90H, 0x00); // SAP=0000 0000\r
+    LCD_WriteReg(pLcdBase, HX8347_R26H, 0x00); // GON=0, DTE=0, D=00\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Set cursor of LCD srceen.\r
+/// \param pLcdBase   LCD base address.\r
+/// \param x          X-coordinate of upper-left corner on LCD.\r
+/// \param y          Y-coordinate of upper-left corner on LCD.\r
+//------------------------------------------------------------------------------\r
+void LCD_SetCursor(void *pLcdBase, unsigned short x, unsigned short y)\r
+{\r
+    unsigned char x1, x2, y1, y2;\r
+\r
+    x1 = x & 0xff;\r
+    x2 = (x & 0xff00) >>8;\r
+    y1 = y & 0xff;\r
+    y2 = (y & 0xff00) >>8;\r
+    LCD_WriteReg(pLcdBase, HX8347_R02H, x2); // column high\r
+    LCD_WriteReg(pLcdBase, HX8347_R03H, x1); // column low\r
+    LCD_WriteReg(pLcdBase, HX8347_R06H, y2); // row high\r
+    LCD_WriteReg(pLcdBase, HX8347_R07H, y1); // row low\r
+}\r
+#endif //#ifdef BOARD_LCD_HX8347\r

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/components/hx8347/hx8347.h b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/components/hx8347/hx8347.h
new file mode 100644 (file)
index 0000000..6affa9e
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/components/hx8347/hx8347.h
@@ -0,0 +1,87 @@
+/* ----------------------------------------------------------------------------\r
+ *         ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+//------------------------------------------------------------------------------\r
+/// \unit\r
+///\r
+/// !!!Purpose\r
+///\r
+/// Definition of methods for HX8347 driver.\r
+///\r
+/// !!!Usage\r
+///\r
+/// -# LCD_WriteReg\r
+/// -# LCD_ReadReg\r
+/// -# LCD_ReadStatus\r
+/// -# LCD_DumpReg\r
+/// -# LCD_WriteRAM_Prepare\r
+/// -# LCD_WriteRAM\r
+/// -# LCD_ReadRAM\r
+/// -# LCD_Initialize\r
+/// -# LCD_SetCursor\r
+/// -# LCD_On\r
+/// -# LCD_Off\r
+//------------------------------------------------------------------------------\r
+\r
+#ifndef HX8347_H\r
+#define HX8347_H\r
+\r
+//------------------------------------------------------------------------------\r
+//         Headers\r
+//------------------------------------------------------------------------------\r
+#include <board.h>\r
+\r
+#ifdef BOARD_LCD_HX8347\r
+\r
+//------------------------------------------------------------------------------\r
+//         Definitions\r
+//------------------------------------------------------------------------------\r
+/// Convert 24-bits color to 16-bits color\r
+#define RGB24ToRGB16(color) (((color >> 8) & 0xF800) | \\r
+    ((color >> 5) & 0x7E0) | \\r
+    ((color >> 3) & 0x1F))\r
+\r
+//------------------------------------------------------------------------------\r
+//         Global functions\r
+//------------------------------------------------------------------------------\r
+\r
+void LCD_WriteReg(void *pLcdBase, unsigned char reg, unsigned short data);\r
+unsigned short LCD_ReadReg(void *pLcdBase, unsigned char reg);\r
+unsigned short LCD_ReadStatus(void *pLcdBase);\r
+void LCD_DumpReg(void *pLcdBase, unsigned char startAddr, unsigned char endAddr);\r
+void LCD_WriteRAM_Prepare(void *pLcdBase);\r
+void LCD_WriteRAM(void *pLcdBase, unsigned short color);\r
+unsigned short LCD_ReadRAM(void *pLcdBase);\r
+void LCD_Initialize(void *pLcdBase);\r
+void LCD_SetCursor(void *pLcdBase, unsigned short x, unsigned short y);\r
+void LCD_On(void *pLcdBase);\r
+void LCD_Off(void *pLcdBase);\r
+\r
+#endif //#ifdef BOARD_LCD_HX8347\r
+#endif //#ifndef HX8347_H\r

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/drivers/lcd/color.h b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/drivers/lcd/color.h
new file mode 100644 (file)
index 0000000..68128c2
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/drivers/lcd/color.h
@@ -0,0 +1,132 @@
+/* ----------------------------------------------------------------------------\r
+ *         ATMEL Microcontroller Software Support\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+#ifndef COLOR_H\r
+#define COLOR_H\r
+\r
+//------------------------------------------------------------------------------\r
+/// RGB 24 Bpp\r
+/// RGB 888\r
+/// R7R6R5R4 R3R2R1R0 G7G6G5G4 G3G2G1G0 B7B6B5B4 B3B2B1B0\r
+//------------------------------------------------------------------------------\r
+#define COLOR_BLACK          0x000000\r
+#define COLOR_WHITE          0xFFFFFF\r
+\r
+#define COLOR_BLUE           0x0000FF\r
+#define COLOR_GREEN          0x00FF00\r
+#define COLOR_RED            0xFF0000\r
+\r
+#define COLOR_NAVY           0x000080\r
+#define COLOR_DARKBLUE       0x00008B\r
+#define COLOR_DARKGREEN      0x006400\r
+#define COLOR_DARKCYAN       0x008B8B\r
+#define COLOR_CYAN           0x00FFFF\r
+#define COLOR_TURQUOISE      0x40E0D0\r
+#define COLOR_INDIGO         0x4B0082\r
+#define COLOR_DARKRED        0x800000\r
+#define COLOR_OLIVE          0x808000\r
+#define COLOR_GRAY           0x808080\r
+#define COLOR_SKYBLUE        0x87CEEB\r
+#define COLOR_BLUEVIOLET     0x8A2BE2\r
+#define COLOR_LIGHTGREEN     0x90EE90\r
+#define COLOR_DARKVIOLET     0x9400D3\r
+#define COLOR_YELLOWGREEN    0x9ACD32\r
+#define COLOR_BROWN          0xA52A2A\r
+#define COLOR_DARKGRAY       0xA9A9A9\r
+#define COLOR_SIENNA         0xA0522D\r
+#define COLOR_LIGHTBLUE      0xADD8E6\r
+#define COLOR_GREENYELLOW    0xADFF2F\r
+#define COLOR_SILVER         0xC0C0C0\r
+#define COLOR_LIGHTGREY      0xD3D3D3\r
+#define COLOR_LIGHTCYAN      0xE0FFFF\r
+#define COLOR_VIOLET         0xEE82EE\r
+#define COLOR_AZUR           0xF0FFFF\r
+#define COLOR_BEIGE          0xF5F5DC\r
+#define COLOR_MAGENTA        0xFF00FF\r
+#define COLOR_TOMATO         0xFF6347\r
+#define COLOR_GOLD           0xFFD700\r
+#define COLOR_ORANGE         0xFFA500\r
+#define COLOR_SNOW           0xFFFAFA\r
+#define COLOR_YELLOW         0xFFFF00\r
+\r
+#endif // #define COLOR_H\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/drivers/lcd/draw.h b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/drivers/lcd/draw.h
new file mode 100644 (file)
index 0000000..f74e04b
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/drivers/lcd/draw.h
@@ -0,0 +1,81 @@
+/* ----------------------------------------------------------------------------\r
+ *         ATMEL Microcontroller Software Support\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+//------------------------------------------------------------------------------\r
+/// \unit\r
+///\r
+/// !!!Purpose\r
+///\r
+/// Provides simple drawing function to use with the LCD.\r
+///\r
+/// !!!Usage\r
+///\r
+/// -# Use LCDD_Fill to fill the LCD buffer with a specific color.\r
+/// -# Draw a pixel on the screen at the specified coordinates using\r
+///    LCDD_DrawPixel.\r
+/// -# Draw a rectangle with LCDD_DrawRectangle.\r
+/// -# Draw a string on the LCD with LCDD_DrawString.\r
+//------------------------------------------------------------------------------\r
+\r
+#ifndef DRAW_H\r
+#define DRAW_H\r
+\r
+//------------------------------------------------------------------------------\r
+//         Global functions\r
+//------------------------------------------------------------------------------\r
+\r
+extern void LCDD_Fill(void *pBuffer, unsigned int color);\r
+\r
+extern void LCDD_DrawPixel(\r
+    void *pBuffer,\r
+    unsigned int x,\r
+    unsigned int y,\r
+    unsigned int c);\r
+\r
+extern void LCDD_DrawRectangle(\r
+    void *pBuffer,\r
+    unsigned int x,\r
+    unsigned int y,\r
+    unsigned int width,\r
+    unsigned int height,\r
+    unsigned int color);\r
+\r
+extern void LCDD_DrawString(\r
+    void *pBuffer,\r
+    unsigned int x,\r
+    unsigned int y,\r
+    const char *pString,\r
+    unsigned int color);\r
+\r
+extern void LCDD_GetStringSize(\r
+    const char *pString,\r
+    unsigned int *pWidth,\r
+    unsigned int *pHeight);\r
+\r
+#endif //#ifndef DRAW_H\r

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/drivers/lcd/draw_hx8347.c b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/drivers/lcd/draw_hx8347.c
new file mode 100644 (file)
index 0000000..87e07a8
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/drivers/lcd/draw_hx8347.c
@@ -0,0 +1,181 @@
+/* ----------------------------------------------------------------------------\r
+ *         ATMEL Microcontroller Software Support\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+//------------------------------------------------------------------------------\r
+//         Headers\r
+//------------------------------------------------------------------------------\r
+\r
+#include "draw.h"\r
+#include "font.h"\r
+#include <board.h>\r
+#include <utility/assert.h>\r
+#include <hx8347/hx8347.h>\r
+\r
+#include <string.h>\r
+\r
+//------------------------------------------------------------------------------\r
+//         Global functions\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+/// Fills the given LCD buffer with a particular color.\r
+/// Only works in 24-bits packed mode for now.\r
+/// \param pBuffer  LCD buffer to fill.\r
+/// \param color  Fill color.\r
+//------------------------------------------------------------------------------\r
+void LCDD_Fill(void *pBuffer, unsigned int color)\r
+{\r
+    unsigned int i;\r
+    unsigned short color16 = RGB24ToRGB16(color);\r
+\r
+\r
+    LCD_SetCursor((void *)BOARD_LCD_BASE, 0, 0);\r
+    LCD_WriteRAM_Prepare((void *)BOARD_LCD_BASE);\r
+    for (i = 0; i < (BOARD_LCD_WIDTH * BOARD_LCD_HEIGHT); i++) {\r
+\r
+        LCD_WriteRAM((void *)BOARD_LCD_BASE, color16);\r
+    }\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Sets the specified pixel to the given color.\r
+/// !!! Only works in 24-bits packed mode for now. !!!\r
+/// \param pBuffer  LCD buffer to draw on.\r
+/// \param x  X-coordinate of pixel.\r
+/// \param y  Y-coordinate of pixel.\r
+/// \param color  Pixel color.\r
+//------------------------------------------------------------------------------\r
+void LCDD_DrawPixel(\r
+    void *pBuffer,\r
+    unsigned int x,\r
+    unsigned int y,\r
+    unsigned int color)\r
+{\r
+    unsigned short color16 = RGB24ToRGB16(color);\r
+\r
+    LCD_SetCursor(pBuffer, x, y);\r
+    LCD_WriteRAM_Prepare(pBuffer);\r
+    LCD_WriteRAM(pBuffer, color16);\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Draws a rectangle inside a LCD buffer, at the given coordinates.\r
+/// \param pBuffer  LCD buffer to draw on.\r
+/// \param x  X-coordinate of upper-left rectangle corner.\r
+/// \param y  Y-coordinate of upper-left rectangle corner.\r
+/// \param width  Rectangle width in pixels.\r
+/// \param height  Rectangle height in pixels.\r
+/// \param color  Rectangle color.\r
+//------------------------------------------------------------------------------\r
+void LCDD_DrawRectangle(\r
+    void *pBuffer,\r
+    unsigned int x,\r
+    unsigned int y,\r
+    unsigned int width,\r
+    unsigned int height,\r
+    unsigned int color)\r
+{\r
+    unsigned int rx, ry;\r
+\r
+    for (ry=0; ry < height; ry++) {\r
+\r
+        for (rx=0; rx < width; rx++) {\r
+\r
+            LCDD_DrawPixel(pBuffer, x+rx, y+ry, color);\r
+        }\r
+    }\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Draws a string inside a LCD buffer, at the given coordinates. Line breaks\r
+/// will be honored.\r
+/// \param pBuffer  Buffer to draw on.\r
+/// \param x  X-coordinate of string top-left corner.\r
+/// \param y  Y-coordinate of string top-left corner.\r
+/// \param pString  String to display.\r
+/// \param color  String color.\r
+//------------------------------------------------------------------------------\r
+void LCDD_DrawString(\r
+    void *pBuffer,\r
+    unsigned int x,\r
+    unsigned int y,\r
+    const char *pString,\r
+    unsigned int color)\r
+{\r
+    unsigned xorg = x;\r
+\r
+    while (*pString != 0) {\r
+        if (*pString == '\n') {\r
+\r
+            y += gFont.height + 2;\r
+            x = xorg;\r
+        }\r
+        else {\r
+\r
+            LCDD_DrawChar(pBuffer, x, y, *pString, color);\r
+            x += gFont.width + 2;\r
+        }\r
+        pString++;\r
+    }\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Returns the width & height in pixels that a string will occupy on the screen\r
+/// if drawn using LCDD_DrawString.\r
+/// \param pString  String.\r
+/// \param pWidth  Pointer for storing the string width (optional).\r
+/// \param pHeight  Pointer for storing the string height (optional).\r
+/// \return String width in pixels.\r
+//------------------------------------------------------------------------------\r
+void LCDD_GetStringSize(\r
+    const char *pString,\r
+    unsigned int *pWidth,\r
+    unsigned int *pHeight)\r
+{\r
+    unsigned int width = 0;\r
+    unsigned int height = gFont.height;\r
+\r
+    while (*pString != 0) {\r
+\r
+        if (*pString == '\n') {\r
+\r
+            height += gFont.height + 2;\r
+        }\r
+        else {\r
+\r
+            width += gFont.width + 2;\r
+        }\r
+        pString++;\r
+    }\r
+\r
+    if (width > 0) width -= 2;\r
+\r
+    if (pWidth) *pWidth = width;\r
+    if (pHeight) *pHeight = height;\r
+}\r

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/drivers/lcd/font.c b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/drivers/lcd/font.c
new file mode 100644 (file)
index 0000000..95c528e
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/drivers/lcd/font.c
@@ -0,0 +1,86 @@
+/* ----------------------------------------------------------------------------\r
+ *     ATMEL Microcontroller Software Support\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+//------------------------------------------------------------------------------\r
+//     Headers\r
+//------------------------------------------------------------------------------\r
+\r
+#include "font.h"\r
+#include "draw.h"\r
+#include "font10x14.h"\r
+#include <utility/assert.h>\r
+\r
+//------------------------------------------------------------------------------\r
+//     Local variables\r
+//------------------------------------------------------------------------------\r
+\r
+/// Global variable describing the font being instancied.\r
+const Font gFont = {10, 14};\r
+\r
+//------------------------------------------------------------------------------\r
+//     Global functions\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+/// Draws an ASCII character on the given LCD buffer.\r
+/// \param pBuffer  Buffer to write on.\r
+/// \param x  X-coordinate of character upper-left corner.\r
+/// \param y  Y-coordinate of character upper-left corner.\r
+/// \param c  Character to output.\r
+/// \param color  Character color.\r
+//------------------------------------------------------------------------------\r
+void LCDD_DrawChar(\r
+    void *pBuffer,\r
+    unsigned int x,\r
+    unsigned int y,\r
+    char c,\r
+    unsigned int color)\r
+{\r
+    unsigned int row, col;\r
+\r
+    SANITY_CHECK((c >= 0x20) && (c <= 0x7F));\r
+\r
+    for (col = 0; col < 10; col++) {\r
+\r
+        for (row = 0; row < 8; row++) {\r
+\r
+            if ((pCharset10x14[((c - 0x20) * 20) + col * 2] >> (7 - row)) & 0x1) {\r
+\r
+                LCDD_DrawPixel(pBuffer, x+col, y+row, color);\r
+            }\r
+        }\r
+        for (row = 0; row < 6; row++) {\r
+\r
+            if ((pCharset10x14[((c - 0x20) * 20) + col * 2 + 1] >> (7 - row)) & 0x1) {\r
+\r
+                LCDD_DrawPixel(pBuffer, x+col, y+row+8, color);\r
+            }\r
+        }\r
+    }\r
+}\r

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/drivers/lcd/font.h b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/drivers/lcd/font.h
new file mode 100644 (file)
index 0000000..37321b5
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/drivers/lcd/font.h
@@ -0,0 +1,89 @@
+/* ----------------------------------------------------------------------------\r
+ *         ATMEL Microcontroller Software Support\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+//------------------------------------------------------------------------------\r
+/// \unit\r
+///\r
+/// !!!Purpose\r
+///\r
+/// The font.h files declares a font structure and a LCDD_DrawChar function\r
+/// that must be implemented by a font definition file to be used with the\r
+/// LCDD_DrawString method of draw.h.\r
+///\r
+/// The font10x14.c implements the necessary variable and function for a 10x14\r
+/// font.\r
+///\r
+/// !!!Usage\r
+///\r
+/// -# Declare a gFont global variable with the necessary Font information.\r
+/// -# Implement an LCDD_DrawChar function which displays the specified\r
+///    character on the LCD.\r
+/// -# Use the LCDD_DrawString method defined in draw.h to display a complete\r
+///    string.\r
+//------------------------------------------------------------------------------\r
+\r
+#ifndef FONT_H\r
+#define FONT_H\r
+\r
+//------------------------------------------------------------------------------\r
+//         Global types\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+/// Describes the font (width, height, supported characters, etc.) used by\r
+/// the LCD driver draw API.\r
+//------------------------------------------------------------------------------\r
+typedef struct _Font {\r
+\r
+       /// Font width in pixels.\r
+       unsigned char width;\r
+       /// Font height in pixels.\r
+       unsigned char height;\r
+\r
+} Font;\r
+\r
+//------------------------------------------------------------------------------\r
+//         Global variables\r
+//------------------------------------------------------------------------------\r
+\r
+/// Global variable describing the font being instancied.\r
+extern const Font gFont;\r
+\r
+//------------------------------------------------------------------------------\r
+//         Global functions\r
+//------------------------------------------------------------------------------\r
+\r
+extern void LCDD_DrawChar(\r
+       void *pBuffer,\r
+       unsigned int x,\r
+       unsigned int y,\r
+       char c,\r
+       unsigned int color);\r
+\r
+#endif //#ifndef FONT_H\r

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/drivers/lcd/font10x14.h b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/drivers/lcd/font10x14.h
new file mode 100644 (file)
index 0000000..b86612a
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/drivers/lcd/font10x14.h
@@ -0,0 +1,237 @@
+/* ----------------------------------------------------------------------------\r
+ *         ATMEL Microcontroller Software Support\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+#ifndef LCD_FONT_10x14_H\r
+#define LCD_FONT_10x14_H\r
+\r
+//------------------------------------------------------------------------------\r
+//         Headers\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+//         Definitions\r
+//------------------------------------------------------------------------------\r
+\r
+const unsigned char pCharset10x14[] = {\r
+       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xCC,\r
+       0xFF, 0xCC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+       0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0xF0, 0x00, 0x00, 0x00,\r
+       0x00, 0x00, 0xF0, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+       0x0C, 0xC0, 0x0C, 0xC0, 0xFF, 0xFC, 0xFF, 0xFC, 0x0C, 0xC0,\r
+       0x0C, 0xC0, 0xFF, 0xFC, 0xFF, 0xFC, 0x0C, 0xC0, 0x0C, 0xC0,\r
+       0x0C, 0x60, 0x1E, 0x70, 0x3F, 0x30, 0x33, 0x30, 0xFF, 0xFC,\r
+       0xFF, 0xFC, 0x33, 0x30, 0x33, 0xF0, 0x39, 0xE0, 0x18, 0xC0,\r
+       0x60, 0x00, 0xF0, 0x0C, 0xF0, 0x3C, 0x60, 0xF0, 0x03, 0xC0,\r
+       0x0F, 0x00, 0x3C, 0x18, 0xF0, 0x3C, 0xC0, 0x3C, 0x00, 0x18,\r
+       0x3C, 0xF0, 0x7F, 0xF8, 0xC3, 0x1C, 0xC7, 0x8C, 0xCF, 0xCC,\r
+       0xDC, 0xEC, 0x78, 0x78, 0x30, 0x30, 0x00, 0xFC, 0x00, 0xCC,\r
+       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x44, 0x00, 0xEC, 0x00,\r
+       0xF8, 0x00, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+       0x00, 0x00, 0x00, 0x00, 0x0F, 0xC0, 0x3F, 0xF0, 0x78, 0x78,\r
+       0x60, 0x18, 0xC0, 0x0C, 0xC0, 0x0C, 0x00, 0x00, 0x00, 0x00,\r
+       0x00, 0x00, 0x00, 0x00, 0xC0, 0x0C, 0xC0, 0x0C, 0x60, 0x18,\r
+       0x78, 0x78, 0x3F, 0xF0, 0x0F, 0xC0, 0x00, 0x00, 0x00, 0x00,\r
+       0x0C, 0x60, 0x0E, 0xE0, 0x07, 0xC0, 0x03, 0x80, 0x3F, 0xF8,\r
+       0x3F, 0xF8, 0x03, 0x80, 0x07, 0xC0, 0x0E, 0xE0, 0x0C, 0x60,\r
+       0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0x3F, 0xF0,\r
+       0x3F, 0xF0, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00,\r
+       0x00, 0x44, 0x00, 0xEC, 0x00, 0xF8, 0x00, 0x70, 0x00, 0x00,\r
+       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+       0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00,\r
+       0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00,\r
+       0x00, 0x18, 0x00, 0x3C, 0x00, 0x3C, 0x00, 0x18, 0x00, 0x00,\r
+       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+       0x00, 0x00, 0x00, 0x0C, 0x00, 0x3C, 0x00, 0xF0, 0x03, 0xC0,\r
+       0x0F, 0x00, 0x3C, 0x00, 0xF0, 0x00, 0xC0, 0x00, 0x00, 0x00,\r
+       0x3F, 0xF0, 0x7F, 0xF8, 0xE0, 0xFC, 0xC1, 0xCC, 0xC3, 0x8C,\r
+       0xC7, 0x0C, 0xCE, 0x0C, 0xFC, 0x1C, 0x7F, 0xF8, 0x3F, 0xF0,\r
+       0x00, 0x00, 0x00, 0x00, 0x30, 0x0C, 0x70, 0x0C, 0xFF, 0xFC,\r
+       0xFF, 0xFC, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x00,\r
+       0x30, 0x0C, 0x70, 0x1C, 0xE0, 0x3C, 0xC0, 0x7C, 0xC0, 0xEC,\r
+       0xC1, 0xCC, 0xC3, 0x8C, 0xE7, 0x0C, 0x7E, 0x0C, 0x3C, 0x0C,\r
+       0x30, 0x30, 0x70, 0x38, 0xE0, 0x1C, 0xC0, 0x0C, 0xC0, 0x0C,\r
+       0xC3, 0x0C, 0xC3, 0x0C, 0xE3, 0x1C, 0x7F, 0xF8, 0x3C, 0xF0,\r
+       0x03, 0xC0, 0x07, 0xC0, 0x0E, 0xC0, 0x1C, 0xC0, 0x38, 0xC0,\r
+       0x70, 0xC0, 0xFF, 0xFC, 0xFF, 0xFC, 0x00, 0xC0, 0x00, 0xC0,\r
+       0xFC, 0x30, 0xFC, 0x38, 0xCC, 0x1C, 0xCC, 0x0C, 0xCC, 0x0C,\r
+       0xCC, 0x0C, 0xCC, 0x0C, 0xCE, 0x1C, 0xC7, 0xF8, 0xC3, 0xF0,\r
+       0x3F, 0xF0, 0x7F, 0xF8, 0xE3, 0x1C, 0xC3, 0x0C, 0xC3, 0x0C,\r
+       0xC3, 0x0C, 0xC3, 0x0C, 0xE3, 0x9C, 0x71, 0xF8, 0x30, 0xF0,\r
+       0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC3, 0xFC,\r
+       0xC7, 0xFC, 0xCE, 0x00, 0xDC, 0x00, 0xF8, 0x00, 0xF0, 0x00,\r
+       0x3C, 0xF0, 0x7F, 0xF8, 0xE7, 0x9C, 0xC3, 0x0C, 0xC3, 0x0C,\r
+       0xC3, 0x0C, 0xC3, 0x0C, 0xE7, 0x9C, 0x7F, 0xF8, 0x3C, 0xF0,\r
+       0x3C, 0x00, 0x7E, 0x00, 0xE7, 0x0C, 0xC3, 0x0C, 0xC3, 0x1C,\r
+       0xC3, 0x38, 0xC3, 0x70, 0xE7, 0xE0, 0x7F, 0xC0, 0x3F, 0x80,\r
+       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x60, 0x3C, 0xF0,\r
+       0x3C, 0xF0, 0x18, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x44, 0x3C, 0xEC,\r
+       0x3C, 0xF8, 0x18, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+       0x00, 0x00, 0x03, 0x00, 0x07, 0x80, 0x0F, 0xC0, 0x1C, 0xE0,\r
+       0x38, 0x70, 0x70, 0x38, 0xE0, 0x1C, 0xC0, 0x0C, 0x00, 0x00,\r
+       0x0C, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0,\r
+       0x0C, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0,\r
+       0x00, 0x00, 0xC0, 0x0C, 0xE0, 0x1C, 0x70, 0x38, 0x38, 0x70,\r
+       0x1C, 0xE0, 0x0F, 0xC0, 0x07, 0x80, 0x03, 0x00, 0x00, 0x00,\r
+       0x30, 0x00, 0x70, 0x00, 0xE0, 0x00, 0xC0, 0x00, 0xC1, 0xEC,\r
+       0xC3, 0xEC, 0xC3, 0x00, 0xE6, 0x00, 0x7E, 0x00, 0x3C, 0x00,\r
+       0x30, 0xF0, 0x71, 0xF8, 0xE3, 0x9C, 0xC3, 0x0C, 0xC3, 0xFC,\r
+       0xC3, 0xFC, 0xC0, 0x0C, 0xE0, 0x1C, 0x7F, 0xF8, 0x3F, 0xF0,\r
+       0x3F, 0xFC, 0x7F, 0xFC, 0xE0, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0,\r
+       0xC0, 0xC0, 0xC0, 0xC0, 0xE0, 0xC0, 0x7F, 0xFC, 0x3F, 0xFC,\r
+       0xFF, 0xFC, 0xFF, 0xFC, 0xC3, 0x0C, 0xC3, 0x0C, 0xC3, 0x0C,\r
+       0xC3, 0x0C, 0xC3, 0x0C, 0xE7, 0x9C, 0x7F, 0xF8, 0x3C, 0xF0,\r
+       0x3F, 0xF0, 0x7F, 0xF8, 0xE0, 0x1C, 0xC0, 0x0C, 0xC0, 0x0C,\r
+       0xC0, 0x0C, 0xC0, 0x0C, 0xE0, 0x1C, 0x70, 0x38, 0x30, 0x30,\r
+       0xFF, 0xFC, 0xFF, 0xFC, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0, 0x0C,\r
+       0xC0, 0x0C, 0xC0, 0x0C, 0xE0, 0x1C, 0x7F, 0xF8, 0x3F, 0xF0,\r
+       0xFF, 0xFC, 0xFF, 0xFC, 0xC3, 0x0C, 0xC3, 0x0C, 0xC3, 0x0C,\r
+       0xC3, 0x0C, 0xC3, 0x0C, 0xC3, 0x0C, 0xC0, 0x0C, 0xC0, 0x0C,\r
+       0xFF, 0xFC, 0xFF, 0xFC, 0xC3, 0x00, 0xC3, 0x00, 0xC3, 0x00,\r
+       0xC3, 0x00, 0xC3, 0x00, 0xC3, 0x00, 0xC0, 0x00, 0xC0, 0x00,\r
+       0x3F, 0xF0, 0x7F, 0xF8, 0xE0, 0x1C, 0xC0, 0x0C, 0xC0, 0x0C,\r
+       0xC3, 0x0C, 0xC3, 0x0C, 0xE3, 0x1C, 0x73, 0xF8, 0x33, 0xF0,\r
+       0xFF, 0xFC, 0xFF, 0xFC, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00,\r
+       0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0xFF, 0xFC, 0xFF, 0xFC,\r
+       0x00, 0x00, 0x00, 0x00, 0xC0, 0x0C, 0xC0, 0x0C, 0xFF, 0xFC,\r
+       0xFF, 0xFC, 0xC0, 0x0C, 0xC0, 0x0C, 0x00, 0x00, 0x00, 0x00,\r
+       0x00, 0x30, 0x00, 0x38, 0xC0, 0x1C, 0xC0, 0x0C, 0xC0, 0x0C,\r
+       0xC0, 0x1C, 0xFF, 0xF8, 0xFF, 0xF0, 0xC0, 0x00, 0xC0, 0x00,\r
+       0xFF, 0xFC, 0xFF, 0xFC, 0x07, 0x80, 0x07, 0x80, 0x0F, 0xC0,\r
+       0x1C, 0xE0, 0x38, 0x70, 0x70, 0x38, 0xE0, 0x1C, 0xC0, 0x0C,\r
+       0xFF, 0xFC, 0xFF, 0xFC, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C,\r
+       0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C,\r
+       0xFF, 0xFC, 0xFF, 0xFC, 0x70, 0x00, 0x38, 0x00, 0x1F, 0x00,\r
+       0x1F, 0x00, 0x38, 0x00, 0x70, 0x00, 0xFF, 0xFC, 0xFF, 0xFC,\r
+       0xFF, 0xFC, 0xFF, 0xFC, 0x1C, 0x00, 0x0E, 0x00, 0x07, 0x00,\r
+       0x03, 0x80, 0x01, 0xC0, 0x00, 0xE0, 0xFF, 0xFC, 0xFF, 0xFC,\r
+       0x3F, 0xF0, 0x7F, 0xF8, 0xE0, 0x1C, 0xC0, 0x0C, 0xC0, 0x0C,\r
+       0xC0, 0x0C, 0xC0, 0x0C, 0xE0, 0x1C, 0x7F, 0xF8, 0x3F, 0xF0,\r
+       0xFF, 0xFC, 0xFF, 0xFC, 0xC3, 0x00, 0xC3, 0x00, 0xC3, 0x00,\r
+       0xC3, 0x00, 0xC3, 0x00, 0xE7, 0x00, 0x7E, 0x00, 0x3C, 0x00,\r
+       0x3F, 0xF0, 0x7F, 0xF8, 0xE0, 0x1C, 0xC0, 0x0C, 0xC0, 0xCC,\r
+       0xC0, 0xEC, 0xC0, 0x7C, 0xE0, 0x38, 0x7F, 0xFC, 0x3F, 0xEC,\r
+       0xFF, 0xFC, 0xFF, 0xFC, 0xC3, 0x00, 0xC3, 0x80, 0xC3, 0x80,\r
+       0xC3, 0xC0, 0xC3, 0xC0, 0xE7, 0x70, 0x7E, 0x3C, 0x3C, 0x1C,\r
+       0x3C, 0x18, 0x7E, 0x1C, 0xE7, 0x0C, 0xC3, 0x0C, 0xC3, 0x0C,\r
+       0xC3, 0x0C, 0xC3, 0x0C, 0xC3, 0x9C, 0xE1, 0xF8, 0x60, 0xF0,\r
+       0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xFF, 0xFC,\r
+       0xFF, 0xFC, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00,\r
+       0xFF, 0xF0, 0xFF, 0xF8, 0x00, 0x1C, 0x00, 0x0C, 0x00, 0x0C,\r
+       0x00, 0x0C, 0x00, 0x0C, 0x00, 0x1C, 0xFF, 0xF8, 0xFF, 0xF0,\r
+       0xFF, 0xC0, 0xFF, 0xE0, 0x00, 0x70, 0x00, 0x38, 0x00, 0x1C,\r
+       0x00, 0x1C, 0x00, 0x38, 0x00, 0x70, 0xFF, 0xE0, 0xFF, 0xC0,\r
+       0xFF, 0xF0, 0xFF, 0xF8, 0x00, 0x1C, 0x00, 0x3C, 0x00, 0xF8,\r
+       0x00, 0xF8, 0x00, 0x3C, 0x00, 0x1C, 0xFF, 0xF8, 0xFF, 0xF0,\r
+       0xF0, 0x3C, 0xF8, 0x7C, 0x1C, 0xE0, 0x0F, 0xC0, 0x07, 0x80,\r
+       0x07, 0x80, 0x0F, 0xC0, 0x1C, 0xE0, 0xF8, 0x7C, 0xF0, 0x3C,\r
+       0xFC, 0x00, 0xFE, 0x00, 0x07, 0x00, 0x03, 0x80, 0x01, 0xFC,\r
+       0x01, 0xFC, 0x03, 0x80, 0x07, 0x00, 0xFE, 0x00, 0xFC, 0x00,\r
+       0xC0, 0x3C, 0xC0, 0x7C, 0xC0, 0xEC, 0xC1, 0xCC, 0xC3, 0x8C,\r
+       0xC7, 0x0C, 0xCE, 0x0C, 0xDC, 0x0C, 0xF8, 0x0C, 0xF0, 0x0C,\r
+       0x00, 0x00, 0x00, 0x00, 0xFF, 0xFC, 0xFF, 0xFC, 0xC0, 0x0C,\r
+       0xC0, 0x0C, 0xC0, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+       0x30, 0x00, 0x30, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x03, 0x00,\r
+       0x03, 0x00, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0x30, 0x00, 0x30,\r
+       0x00, 0x00, 0x00, 0x00, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0, 0x0C,\r
+       0xFF, 0xFC, 0xFF, 0xFC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+       0x0C, 0x00, 0x1C, 0x00, 0x38, 0x00, 0x70, 0x00, 0xE0, 0x00,\r
+       0xE0, 0x00, 0x70, 0x00, 0x38, 0x00, 0x1C, 0x00, 0x0C, 0x00,\r
+       0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C,\r
+       0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C,\r
+       0x00, 0x00, 0x00, 0x00, 0xC0, 0x00, 0xE0, 0x00, 0x70, 0x00,\r
+       0x38, 0x00, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+       0x00, 0x30, 0x06, 0x78, 0x0E, 0xFC, 0x0C, 0xCC, 0x0C, 0xCC,\r
+       0x0C, 0xCC, 0x0C, 0xCC, 0x0E, 0xCC, 0x07, 0xFC, 0x03, 0xF8,\r
+       0xFF, 0xFC, 0xFF, 0xFC, 0x03, 0x0C, 0x03, 0x0C, 0x03, 0x0C,\r
+       0x03, 0x0C, 0x03, 0x0C, 0x03, 0x9C, 0x01, 0xF8, 0x00, 0xF0,\r
+       0x03, 0xF0, 0x07, 0xF8, 0x0E, 0x1C, 0x0C, 0x0C, 0x0C, 0x0C,\r
+       0x0C, 0x0C, 0x0C, 0x0C, 0x0E, 0x1C, 0x07, 0x38, 0x03, 0x30,\r
+       0x00, 0xF0, 0x01, 0xF8, 0x03, 0x9C, 0x03, 0x0C, 0x03, 0x0C,\r
+       0x03, 0x0C, 0x03, 0x0C, 0x03, 0x0C, 0xFF, 0xFC, 0xFF, 0xFC,\r
+       0x03, 0xF0, 0x07, 0xF8, 0x0E, 0xDC, 0x0C, 0xCC, 0x0C, 0xCC,\r
+       0x0C, 0xCC, 0x0C, 0xCC, 0x0E, 0xDC, 0x07, 0xD8, 0x03, 0x90,\r
+       0x00, 0x00, 0x03, 0x00, 0x3F, 0xFC, 0x7F, 0xFC, 0xE3, 0x00,\r
+       0xE3, 0x00, 0x70, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+       0x03, 0x18, 0x07, 0x9C, 0x0F, 0xCC, 0x0C, 0xCC, 0x0C, 0xCC,\r
+       0x0C, 0xCC, 0x0C, 0xCC, 0x0C, 0xDC, 0x0F, 0xF8, 0x07, 0xF0,\r
+       0xFF, 0xFC, 0xFF, 0xFC, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00,\r
+       0x03, 0x00, 0x03, 0x80, 0x01, 0xFC, 0x00, 0xFC, 0x00, 0x00,\r
+       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1B, 0xFC,\r
+       0x1B, 0xFC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+       0x00, 0x00, 0x00, 0x30, 0x00, 0x38, 0x00, 0x1C, 0x00, 0x0C,\r
+       0x00, 0x0C, 0x00, 0x1C, 0xCF, 0xF8, 0xCF, 0xF0, 0x00, 0x00,\r
+       0x00, 0x00, 0xFF, 0xFC, 0xFF, 0xFC, 0x00, 0xE0, 0x01, 0xE0,\r
+       0x03, 0xF0, 0x07, 0x38, 0x0E, 0x1C, 0x0C, 0x0C, 0x00, 0x00,\r
+       0x00, 0x00, 0x00, 0x00, 0xC0, 0x0C, 0xC0, 0x0C, 0xFF, 0xFC,\r
+       0xFF, 0xFC, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x00,\r
+       0x0F, 0xFC, 0x0F, 0xFC, 0x0E, 0x00, 0x07, 0x00, 0x03, 0xC0,\r
+       0x03, 0xC0, 0x07, 0x00, 0x0E, 0x00, 0x0F, 0xFC, 0x0F, 0xFC,\r
+       0x0F, 0xFC, 0x0F, 0xFC, 0x03, 0x00, 0x07, 0x00, 0x0E, 0x00,\r
+       0x0C, 0x00, 0x0C, 0x00, 0x0E, 0x00, 0x07, 0xFC, 0x03, 0xFC,\r
+       0x03, 0xF0, 0x07, 0xF8, 0x0E, 0x1C, 0x0C, 0x0C, 0x0C, 0x0C,\r
+       0x0C, 0x0C, 0x0C, 0x0C, 0x0E, 0x1C, 0x07, 0xF8, 0x03, 0xF0,\r
+       0x0F, 0xFC, 0x0F, 0xFC, 0x0C, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0,\r
+       0x0C, 0xC0, 0x0C, 0xC0, 0x0F, 0xC0, 0x07, 0x80, 0x03, 0x00,\r
+       0x03, 0x00, 0x07, 0x80, 0x0F, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0,\r
+       0x0C, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0, 0x0F, 0xFC, 0x0F, 0xFC,\r
+       0x0F, 0xFC, 0x0F, 0xFC, 0x03, 0x80, 0x07, 0x00, 0x0E, 0x00,\r
+       0x0C, 0x00, 0x0C, 0x00, 0x0E, 0x00, 0x07, 0x00, 0x03, 0x00,\r
+       0x03, 0x18, 0x07, 0x9C, 0x0F, 0xCC, 0x0C, 0xCC, 0x0C, 0xCC,\r
+       0x0C, 0xCC, 0x0C, 0xCC, 0x0C, 0xFC, 0x0E, 0x78, 0x06, 0x30,\r
+       0x00, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0xFF, 0xF0, 0xFF, 0xF8,\r
+       0x0C, 0x1C, 0x0C, 0x1C, 0x0C, 0x38, 0x0C, 0x30, 0x00, 0x00,\r
+       0x0F, 0xF0, 0x0F, 0xF8, 0x00, 0x1C, 0x00, 0x0C, 0x00, 0x0C,\r
+       0x00, 0x0C, 0x00, 0x0C, 0x00, 0x1C, 0x0F, 0xF8, 0x0F, 0xF0,\r
+       0x0F, 0xC0, 0x0F, 0xE0, 0x00, 0x70, 0x00, 0x38, 0x00, 0x1C,\r
+       0x00, 0x1C, 0x00, 0x38, 0x00, 0x70, 0x0F, 0xE0, 0x0F, 0xC0,\r
+       0x0F, 0xF0, 0x0F, 0xF8, 0x00, 0x1C, 0x00, 0x1C, 0x00, 0xF8,\r
+       0x00, 0xF8, 0x00, 0x1C, 0x00, 0x1C, 0x0F, 0xF8, 0x0F, 0xF0,\r
+       0x0C, 0x0C, 0x0E, 0x1C, 0x07, 0x38, 0x03, 0xF0, 0x01, 0xE0,\r
+       0x01, 0xE0, 0x03, 0xF0, 0x07, 0x38, 0x0E, 0x1C, 0x0C, 0x0C,\r
+       0x0C, 0x00, 0x0E, 0x00, 0x07, 0x0C, 0x03, 0x9C, 0x01, 0xF8,\r
+       0x01, 0xF0, 0x03, 0x80, 0x07, 0x00, 0x0E, 0x00, 0x0C, 0x00,\r
+       0x0C, 0x0C, 0x0C, 0x1C, 0x0C, 0x3C, 0x0C, 0x7C, 0x0C, 0xEC,\r
+       0x0D, 0xCC, 0x0F, 0x8C, 0x0F, 0x0C, 0x0E, 0x0C, 0x0C, 0x0C,\r
+       0x00, 0x00, 0x03, 0x00, 0x07, 0x80, 0x3F, 0xF0, 0x7C, 0xF8,\r
+       0xE0, 0x1C, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0, 0x0C, 0x00, 0x00,\r
+       0x03, 0x0C, 0x03, 0x0C, 0x3F, 0xFC, 0x7F, 0xFC, 0xE3, 0x0C,\r
+       0xC3, 0x0C, 0xC0, 0x0C, 0xE0, 0x0C, 0x70, 0x0C, 0x30, 0x0C,\r
+       0x00, 0x00, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0, 0x0C, 0xE0, 0x1C,\r
+       0x7C, 0xF8, 0x3F, 0xF0, 0x07, 0x80, 0x03, 0x00, 0x00, 0x00,\r
+       0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00,\r
+       0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00,\r
+       0xFF, 0xFC, 0xFF, 0xFC, 0xFF, 0xFC, 0xFF, 0xFC, 0xFF, 0xFC,\r
+       0xFF, 0xFC, 0xFF, 0xFC, 0xFF, 0xFC, 0xFF, 0xFC, 0xFF, 0xFC\r
+};\r
+\r
+\r
+#endif // #ifdef _LCD_FONT_10x14_h\r

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/drivers/lcd/lcdd.h b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/drivers/lcd/lcdd.h
new file mode 100644 (file)
index 0000000..27da073
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/drivers/lcd/lcdd.h
@@ -0,0 +1,61 @@
+/* ----------------------------------------------------------------------------\r
+ *         ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+//------------------------------------------------------------------------------\r
+/// \unit\r
+///\r
+/// !!!Purpose\r
+/// \r
+/// Simple driver for the LCD, which takes care of the initialization.\r
+/// \r
+/// !!!Usage\r
+/// \r
+/// -# Call LCDD_Initialize to configure the LCD controller.\r
+/// -# Set the buffer displayed by the LCD with LCDD_DisplayBuffer if using\r
+///    peripheral LCDC, or start displaying with LCDD_Start if using HX8347.\r
+//------------------------------------------------------------------------------\r
+ \r
+#ifndef LCDD_H\r
+#define LCDD_H\r
+ \r
+//------------------------------------------------------------------------------\r
+//         Global functions\r
+//------------------------------------------------------------------------------\r
+\r
+extern void LCDD_Initialize(void);                 // For peripheral LCDC & HX8347\r
+\r
+extern void * LCDD_DisplayBuffer(void *pBuffer);   // For peripheral LCDC only\r
+\r
+extern void LCDD_Start(void);                      // For HX8347 only\r
+\r
+extern void LCDD_Stop(void);                       // For peripheral LCDC & HX8347\r
+\r
+extern void LCDD_SetBacklight (unsigned int step); // For peripheral LCDC only\r
+\r
+#endif //#ifndef LCDD_H\r

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/drivers/lcd/lcdd_hx8347.c b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/drivers/lcd/lcdd_hx8347.c
new file mode 100644 (file)
index 0000000..7d0c90f
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/drivers/lcd/lcdd_hx8347.c
@@ -0,0 +1,143 @@
+/* ----------------------------------------------------------------------------\r
+ *         ATMEL Microcontroller Software Support\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+//------------------------------------------------------------------------------\r
+//         Headers\r
+//------------------------------------------------------------------------------\r
+\r
+#include "lcdd.h"\r
+\r
+#include <board.h>\r
+#include <pmc/pmc.h>\r
+#include <hx8347/hx8347.h>\r
+#include <pio/pio.h>\r
+\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+//------------------------------------------------------------------------------\r
+//         Global functions\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+/// Initializes the LCD controller.\r
+/// \param pLcdBase   LCD base address.\r
+//------------------------------------------------------------------------------\r
+void LCDD_Initialize(void)\r
+{\r
+    const Pin pPins[] = {BOARD_LCD_PINS};\r
+    AT91PS_HSMC4_CS pSMC = AT91C_BASE_HSMC4_CS2;\r
+    unsigned int rMode;\r
+\r
+    // Enable pins\r
+    PIO_Configure(pPins, PIO_LISTSIZE(pPins));\r
+\r
+    // Enable peripheral clock\r
+    PMC_EnablePeripheral(AT91C_ID_HSMC4);\r
+\r
+    // EBI SMC Configuration\r
+    pSMC->HSMC4_SETUP = 0\r
+                    | ((4 <<  0) & AT91C_HSMC4_NWE_SETUP)\r
+                    | ((2 <<  8) & AT91C_HSMC4_NCS_WR_SETUP)\r
+                    | ((4 << 16) & AT91C_HSMC4_NRD_SETUP)\r
+                    | ((2 << 24) & AT91C_HSMC4_NCS_RD_SETUP)\r
+                    ;\r
+\r
+    pSMC->HSMC4_PULSE = 0\r
+                    | (( 5 <<  0) & AT91C_HSMC4_NWE_PULSE)\r
+                    | (( 18 <<  8) & AT91C_HSMC4_NCS_WR_PULSE)\r
+                    | (( 5 << 16) & AT91C_HSMC4_NRD_PULSE)\r
+                    | (( 18 << 24) & AT91C_HSMC4_NCS_RD_PULSE)\r
+                    ;\r
+\r
+    pSMC->HSMC4_CYCLE = 0\r
+                  | ((22 <<  0) & AT91C_HSMC4_NWE_CYCLE)\r
+                  | ((22 << 16) & AT91C_HSMC4_NRD_CYCLE)\r
+                  ;\r
+\r
+    rMode = pSMC->HSMC4_MODE;\r
+    pSMC->HSMC4_MODE = (rMode & ~(AT91C_HSMC4_DBW | AT91C_HSMC4_READ_MODE\r
+                 | AT91C_HSMC4_WRITE_MODE | AT91C_HSMC4_PMEN))\r
+                 | (AT91C_HSMC4_READ_MODE)\r
+                 | (AT91C_HSMC4_WRITE_MODE)\r
+                 | (AT91C_HSMC4_DBW_WIDTH_SIXTEEN_BITS)\r
+                 ;\r
+\r
+    // Initialize LCD controller (HX8347)\r
+    LCD_Initialize((void *)BOARD_LCD_BASE);\r
+\r
+    // Set LCD backlight\r
+    LCDD_SetBacklight(25);\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Turn on the LCD\r
+//------------------------------------------------------------------------------\r
+void LCDD_Start(void)\r
+{\r
+    LCD_On((void *)BOARD_LCD_BASE);\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Turn off the LCD\r
+//------------------------------------------------------------------------------\r
+void LCDD_Stop(void)\r
+{\r
+    LCD_Off((void *)BOARD_LCD_BASE);\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Set the backlight of the LCD.\r
+/// \param level   Backlight brightness level [1..32], 32 is maximum level.\r
+//------------------------------------------------------------------------------\r
+void LCDD_SetBacklight (unsigned int level)\r
+{\r
+    unsigned int i;\r
+    const Pin pPins[] = {BOARD_BACKLIGHT_PIN};\r
+\r
+    // Enable pins\r
+    PIO_Configure(pPins, PIO_LISTSIZE(pPins));\r
+\r
+    // Switch off backlight\r
+    PIO_Clear(pPins);\r
+       vTaskDelay( 2 );\r
+\r
+    // Set new backlight level\r
+    for (i = 0; i < level; i++) {\r
+\r
+        PIO_Set(pPins);\r
+        PIO_Set(pPins);\r
+        PIO_Set(pPins);\r
+\r
+        PIO_Clear(pPins);\r
+        PIO_Clear(pPins);\r
+        PIO_Clear(pPins);\r
+    }\r
+    PIO_Set(pPins);\r
+}\r

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/ac97c/ac97c.c b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/ac97c/ac97c.c
new file mode 100644 (file)
index 0000000..d9b1771
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/ac97c/ac97c.c
@@ -0,0 +1,692 @@
+/* ----------------------------------------------------------------------------\r
+ *         ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+//------------------------------------------------------------------------------\r
+//         Headers\r
+//------------------------------------------------------------------------------\r
+\r
+#include "ac97c.h"\r
+#include <board.h>\r
+#include <aic/aic.h>\r
+#include <utility/assert.h>\r
+#include <utility/trace.h>\r
+#include <utility/math.h>\r
+\r
+//------------------------------------------------------------------------------\r
+//         Local constants\r
+//------------------------------------------------------------------------------\r
+\r
+/// Maximum size of one PDC buffer (in bytes).\r
+#define MAX_PDC_COUNTER 65535\r
+\r
+//------------------------------------------------------------------------------\r
+//         Local types\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+/// AC97 transfer descriptor. Tracks the status and parameters of a transfer\r
+/// on the AC97 bus.\r
+//------------------------------------------------------------------------------\r
+typedef struct _Ac97Transfer {\r
+\r
+    /// Buffer containing the slots to send.\r
+    unsigned char *pBuffer;\r
+    /// Total number of samples to send.\r
+    volatile unsigned int numSamples;\r
+    /// Optional callback function.\r
+    Ac97Callback callback;\r
+    /// Optional argument to the callback function.\r
+    void *pArg;\r
+\r
+} Ac97Transfer;\r
+\r
+//------------------------------------------------------------------------------\r
+/// AC97 controller driver structure. Monitors the status of transfers on all\r
+/// AC97 channels.\r
+//------------------------------------------------------------------------------\r
+typedef struct _Ac97c {\r
+\r
+    /// List of transfers occuring on each channel.\r
+    Ac97Transfer transfers[5];\r
+} Ac97c;\r
+\r
+//------------------------------------------------------------------------------\r
+//         Local variables\r
+//------------------------------------------------------------------------------\r
+\r
+/// Global AC97 controller instance.\r
+static Ac97c ac97c;\r
+\r
+//------------------------------------------------------------------------------\r
+//         Local functions\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+/// Returns the size of one sample (in bytes) on the given channel.\r
+/// \param channel  Channel number.\r
+//------------------------------------------------------------------------------\r
+static unsigned char GetSampleSize(unsigned char channel)\r
+{\r
+    unsigned int size = 0;\r
+\r
+    SANITY_CHECK((channel == AC97C_CHANNEL_A)\r
+                 || (channel == AC97C_CHANNEL_B)\r
+                 || (channel == AC97C_CHANNEL_CODEC));\r
+\r
+    // Check selected channel\r
+    switch (channel) {\r
+        case AC97C_CHANNEL_CODEC: return 2;\r
+\r
+        case AC97C_CHANNEL_A:\r
+            size = (AT91C_BASE_AC97C->AC97C_CAMR & AT91C_AC97C_SIZE) >> 16;\r
+            break;\r
+\r
+        case AC97C_CHANNEL_B:\r
+            size = (AT91C_BASE_AC97C->AC97C_CBMR & AT91C_AC97C_SIZE) >> 16;\r
+            break;\r
+    }\r
+\r
+    // Compute size in bytes given SIZE field\r
+    if ((size & 2) != 0) {\r
+\r
+        return 2;\r
+    }\r
+    else {\r
+\r
+        return 4;\r
+    }\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Interrupt service routine for Codec, is invoked by AC97C_Handler.\r
+//------------------------------------------------------------------------------\r
+static void CodecHandler(void)\r
+{\r
+    unsigned int status;\r
+    unsigned int data;\r
+    Ac97Transfer *pTransfer = &(ac97c.transfers[AC97C_CODEC_TRANSFER]);\r
+\r
+    // Read CODEC status register\r
+    status = AT91C_BASE_AC97C->AC97C_COSR;\r
+    status &= AT91C_BASE_AC97C->AC97C_COMR;\r
+\r
+    // A sample has been transmitted\r
+    if (status & AT91C_AC97C_TXRDY) {\r
+\r
+        pTransfer->numSamples--;\r
+\r
+        // If there are remaining samples, transmit one\r
+        if (pTransfer->numSamples > 0) {\r
+\r
+            data = *((unsigned int *) pTransfer->pBuffer);\r
+            AT91C_BASE_AC97C->AC97C_COMR &= ~(AT91C_AC97C_TXRDY);\r
+            AT91C_BASE_AC97C->AC97C_COTHR = data;\r
+\r
+            // Check if transfer is read or write\r
+            if ((data & AT91C_AC97C_READ) != 0) {\r
+    \r
+                AT91C_BASE_AC97C->AC97C_COMR |= AT91C_AC97C_RXRDY;\r
+            }\r
+            else {\r
+            \r
+                pTransfer->pBuffer += sizeof(unsigned int);\r
+                AT91C_BASE_AC97C->AC97C_COMR |= AT91C_AC97C_TXRDY;\r
+            }\r
+        }\r
+        // Transfer finished\r
+        else {\r
+\r
+            AT91C_BASE_AC97C->AC97C_IDR = AT91C_AC97C_COEVT;\r
+            AT91C_BASE_AC97C->AC97C_COMR &= ~(AT91C_AC97C_TXRDY);\r
+            if (pTransfer->callback) {\r
+\r
+                pTransfer->callback(pTransfer->pArg, 0, 0);\r
+            }\r
+        }   \r
+    }\r
+\r
+    // A sample has been received\r
+    if (status & AT91C_AC97C_RXRDY) {\r
+\r
+        // Store sample\r
+        data = AT91C_BASE_AC97C->AC97C_CORHR;\r
+        *((unsigned int *) pTransfer->pBuffer) = data;\r
+\r
+        pTransfer->pBuffer += sizeof(unsigned int);\r
+        pTransfer->numSamples--;\r
+\r
+        // Transfer finished\r
+        if (pTransfer->numSamples > 0) {\r
+\r
+            data = *((unsigned int *) pTransfer->pBuffer);\r
+            AT91C_BASE_AC97C->AC97C_COMR &= ~(AT91C_AC97C_RXRDY);\r
+            AT91C_BASE_AC97C->AC97C_COTHR = data;\r
+\r
+            // Check if transfer is read or write\r
+            if ((data & AT91C_AC97C_READ) != 0) {\r
+    \r
+                AT91C_BASE_AC97C->AC97C_COMR |= AT91C_AC97C_RXRDY;\r
+            }\r
+            else {\r
+            \r
+                pTransfer->pBuffer += sizeof(unsigned int);\r
+                AT91C_BASE_AC97C->AC97C_COMR |= AT91C_AC97C_TXRDY;\r
+            }\r
+        }\r
+        else {\r
+\r
+            AT91C_BASE_AC97C->AC97C_IDR = AT91C_AC97C_COEVT;\r
+            AT91C_BASE_AC97C->AC97C_COMR &= ~(AT91C_AC97C_RXRDY);\r
+            if (pTransfer->callback) {\r
+\r
+                pTransfer->callback(pTransfer->pArg, 0, 0);\r
+            }\r
+        }\r
+    }\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Interrupt service routine for channel A, is invoked by AC97C_Handler.\r
+//------------------------------------------------------------------------------\r
+static void ChannelAHandler(void)\r
+{\r
+    unsigned int status;\r
+    Ac97Transfer *pTransmit = &(ac97c.transfers[AC97C_CHANNEL_A_TRANSMIT]);\r
+    Ac97Transfer *pReceive = &(ac97c.transfers[AC97C_CHANNEL_A_RECEIVE]);\r
+\r
+    // Read channel A status register\r
+    status = AT91C_BASE_AC97C->AC97C_CASR;\r
+\r
+    // A buffer has been transmitted\r
+    if ((status & AT91C_AC97C_ENDTX) != 0) {\r
+\r
+        // Update transfer information\r
+        if (pTransmit->numSamples > MAX_PDC_COUNTER) {\r
+\r
+            pTransmit->numSamples -= MAX_PDC_COUNTER;\r
+        }\r
+        else {\r
+\r
+            pTransmit->numSamples = 0;\r
+        }\r
+\r
+        // Transmit new buffers if necessary\r
+        if (pTransmit->numSamples > MAX_PDC_COUNTER) {\r
+\r
+            // Fill next PDC\r
+            AT91C_BASE_AC97C->AC97C_TNPR = (unsigned int) pTransmit->pBuffer;\r
+            if (pTransmit->numSamples > 2 * MAX_PDC_COUNTER) {\r
+\r
+                AT91C_BASE_AC97C->AC97C_TNCR = MAX_PDC_COUNTER;\r
+                pTransmit->pBuffer += MAX_PDC_COUNTER\r
+                                            * GetSampleSize(AC97C_CHANNEL_A);\r
+            }\r
+            else {\r
+\r
+                AT91C_BASE_AC97C->AC97C_TNCR = pTransmit->numSamples\r
+                                                            - MAX_PDC_COUNTER;\r
+            }\r
+        }\r
+        // Only one buffer remaining\r
+        else {\r
+\r
+            AT91C_BASE_AC97C->AC97C_CAMR &= ~AT91C_AC97C_ENDTX;\r
+            AT91C_BASE_AC97C->AC97C_CAMR |= AT91C_AC97C_TXBUFE;\r
+        }\r
+    }\r
+\r
+    // Transmit completed\r
+    if ((status & AT91C_AC97C_TXBUFE) != 0) {\r
+\r
+        pTransmit->numSamples = 0;\r
+        AT91C_BASE_AC97C->AC97C_PTCR = AT91C_PDC_TXTDIS;\r
+        AT91C_BASE_AC97C->AC97C_CAMR &= ~AT91C_AC97C_TXBUFE;\r
+        if (pTransmit->callback) {\r
+\r
+            pTransmit->callback(pTransmit->pArg, 0, 0);\r
+        }\r
+    }\r
+\r
+    // A buffer has been received\r
+    if (status & AT91C_AC97C_ENDRX) {\r
+\r
+        if (pReceive->numSamples > MAX_PDC_COUNTER) {\r
+        \r
+            pReceive->numSamples -= MAX_PDC_COUNTER;\r
+        }\r
+        else {\r
+\r
+            pReceive->numSamples = 0;\r
+        }\r
+\r
+        // Transfer remaining samples\r
+        if (pReceive->numSamples > MAX_PDC_COUNTER) {\r
+\r
+            AT91C_BASE_AC97C->AC97C_RNPR = (unsigned int) pReceive->pBuffer;\r
+            if (pReceive->numSamples > 2 * MAX_PDC_COUNTER) {\r
+            \r
+                AT91C_BASE_AC97C->AC97C_RNCR = MAX_PDC_COUNTER;\r
+                pReceive->pBuffer += MAX_PDC_COUNTER\r
+                                            * GetSampleSize(AC97C_CHANNEL_A);\r
+            }\r
+            else {\r
+\r
+                AT91C_BASE_AC97C->AC97C_RNCR = pReceive->numSamples \r
+                                                            - MAX_PDC_COUNTER;\r
+            }\r
+        }\r
+        // Only one buffer remaining\r
+        else {\r
+\r
+            AT91C_BASE_AC97C->AC97C_CAMR &= ~(AT91C_AC97C_ENDRX);\r
+            AT91C_BASE_AC97C->AC97C_CAMR |= AT91C_AC97C_RXBUFF;\r
+        }\r
+    }\r
+\r
+    // Receive complete\r
+    if ((status & AT91C_AC97C_RXBUFF) != 0) {\r
+\r
+        pReceive->numSamples = 0;\r
+        AT91C_BASE_AC97C->AC97C_PTCR = AT91C_PDC_RXTDIS;\r
+        AT91C_BASE_AC97C->AC97C_CAMR &= ~AT91C_AC97C_RXBUFF;\r
+        if (pReceive->callback) {\r
+\r
+            pReceive->callback(pReceive->pArg, 0, 0);\r
+        }\r
+    }\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+//         Exported functions\r
+//------------------------------------------------------------------------------\r
+//------------------------------------------------------------------------------\r
+/// This handler function must be called by the AC97C interrupt service routine.\r
+/// Identifies which event was activated and calls the associated function.\r
+//------------------------------------------------------------------------------ \r
+void AC97C_Handler(void)\r
+{\r
+    unsigned int status;\r
+\r
+    // Get the real interrupt source\r
+    status = AT91C_BASE_AC97C->AC97C_SR;\r
+    status &= AT91C_BASE_AC97C->AC97C_IMR;\r
+    \r
+    // Check if an event on the codec channel is active\r
+    if ((status & AT91C_AC97C_COEVT) != 0) {\r
+\r
+        CodecHandler();    \r
+    }\r
+    // Check if an event on channel A is active\r
+    if ((status & AT91C_AC97C_CAEVT) != 0) {\r
+\r
+        ChannelAHandler();  \r
+    }\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Starts a read or write transfer on the given channel\r
+/// \param channel particular channel (AC97C_CODEC_TRANSFER, \r
+///                AC97C_CHANNEL_A_RECEIVE, AC97C_CHANNEL_A_TRANSMIT,\r
+///                AC97C_CHANNEL_B_RECEIVE or AC97C_CHANNEL_B_TRANSMIT).\r
+/// \param pBuffer buffer containing the slots to send.\r
+/// \param numSamples total number of samples to send.  \r
+/// \param callback optional callback function.\r
+/// \param pArg optional argument to the callback function.\r
+//------------------------------------------------------------------------------\r
+unsigned char AC97C_Transfer(\r
+    unsigned char channel,\r
+    unsigned char *pBuffer,\r
+    unsigned int numSamples,\r
+    Ac97Callback callback,\r
+    void *pArg)\r
+{\r
+    unsigned int size;\r
+    unsigned int data;\r
+    Ac97Transfer *pTransfer;\r
+\r
+    SANITY_CHECK(channel <= 5);\r
+    SANITY_CHECK(pBuffer);\r
+    SANITY_CHECK(numSamples > 0);\r
+\r
+    // Check that no transfer is pending on the channel\r
+    pTransfer = &(ac97c.transfers[channel]);\r
+    if (pTransfer->numSamples > 0) {\r
+\r
+        TRACE_WARNING(\r
+            "AC97C_Transfer: Channel %d is busy\n\r", channel);\r
+        return AC97C_ERROR_BUSY;\r
+    }\r
+\r
+    // Fill transfer information\r
+    pTransfer->pBuffer = pBuffer;\r
+    pTransfer->numSamples = numSamples;\r
+    pTransfer->callback = callback;\r
+    pTransfer->pArg = pArg;\r
+\r
+    // Transmit or receive over codec channel\r
+    if (channel == AC97C_CODEC_TRANSFER) {\r
+\r
+        // Send command\r
+        data = *((unsigned int *) pTransfer->pBuffer); \r
+        AT91C_BASE_AC97C->AC97C_COTHR = data;\r
+\r
+        // Check if transfer is read or write\r
+        if ((data & AT91C_AC97C_READ) != 0) {\r
+\r
+            AT91C_BASE_AC97C->AC97C_COMR |= AT91C_AC97C_RXRDY;\r
+        }\r
+        else {\r
+        \r
+            pTransfer->pBuffer += sizeof(unsigned int);\r
+            AT91C_BASE_AC97C->AC97C_COMR |= AT91C_AC97C_TXRDY;\r
+        }\r
+\r
+        // Enable interrupts\r
+        AT91C_BASE_AC97C->AC97C_IER |= AT91C_AC97C_COEVT;\r
+    }\r
+    // Transmit over channel A\r
+    else if (channel == AC97C_CHANNEL_A_TRANSMIT) {\r
+\r
+        // Disable PDC\r
+        AT91C_BASE_AC97C->AC97C_PTCR = AT91C_PDC_TXTDIS;\r
+\r
+        // Fill PDC buffers\r
+        size = min(pTransfer->numSamples, MAX_PDC_COUNTER);\r
+        AT91C_BASE_AC97C->AC97C_TPR = (unsigned int) pTransfer->pBuffer;\r
+        AT91C_BASE_AC97C->AC97C_TCR = size;\r
+        pTransfer->pBuffer += size * GetSampleSize(AC97C_CHANNEL_A);\r
+\r
+        size = min(pTransfer->numSamples - size, MAX_PDC_COUNTER);\r
+        if (size > 0) {\r
+\r
+            AT91C_BASE_AC97C->AC97C_TNPR = (unsigned int) pTransfer->pBuffer;\r
+            AT91C_BASE_AC97C->AC97C_TNCR = size;\r
+            pTransfer->pBuffer += size * GetSampleSize(AC97C_CHANNEL_A);\r
+        }\r
+\r
+        // Enable interrupts\r
+        AT91C_BASE_AC97C->AC97C_CAMR |= AT91C_AC97C_PDCEN | AT91C_AC97C_ENDTX;\r
+        AT91C_BASE_AC97C->AC97C_IER |= AT91C_AC97C_CAEVT;\r
+\r
+        // Start transfer\r
+        AT91C_BASE_AC97C->AC97C_PTCR = AT91C_PDC_TXTEN;\r
+    }\r
+    // Receive over channel A\r
+    else if (channel == AC97C_CHANNEL_A_RECEIVE) {\r
+\r
+        // Disable PDC\r
+        AT91C_BASE_AC97C->AC97C_PTCR = AT91C_PDC_RXTDIS;\r
+\r
+        // Fill PDC buffers\r
+        size = min(pTransfer->numSamples, MAX_PDC_COUNTER);\r
+        AT91C_BASE_AC97C->AC97C_RPR = (unsigned int) pTransfer->pBuffer;\r
+        AT91C_BASE_AC97C->AC97C_RCR = size;\r
+        pTransfer->pBuffer += size * GetSampleSize(AC97C_CHANNEL_A);\r
+\r
+        size = min(pTransfer->numSamples - size, MAX_PDC_COUNTER);\r
+        if (size > 0) {\r
+\r
+            AT91C_BASE_AC97C->AC97C_RNPR = (unsigned int) pTransfer->pBuffer;\r
+            AT91C_BASE_AC97C->AC97C_RNCR = size;\r
+            pTransfer->pBuffer += size * GetSampleSize(AC97C_CHANNEL_A);\r
+        }\r
+\r
+        // Enable interrupts\r
+        AT91C_BASE_AC97C->AC97C_CAMR |= AT91C_AC97C_PDCEN | AT91C_AC97C_ENDRX;\r
+        AT91C_BASE_AC97C->AC97C_IER |= AT91C_AC97C_CAEVT;\r
+\r
+        // Start transfer\r
+        AT91C_BASE_AC97C->AC97C_PTCR = AT91C_PDC_RXTEN;\r
+    }\r
+\r
+    return 0;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Stop read or write transfer on the given channel.\r
+/// \param channel  Channel number.\r
+//------------------------------------------------------------------------------\r
+void AC97C_CancelTransfer(unsigned char channel)\r
+{    \r
+    unsigned int size = 0;\r
+    Ac97Transfer *pTransfer;\r
+\r
+    SANITY_CHECK(channel <= AC97C_CHANNEL_B_TRANSMIT);\r
+\r
+    // Save remaining size\r
+    pTransfer = &(ac97c.transfers[channel]);\r
+    size = pTransfer->numSamples;\r
+    pTransfer->numSamples = 0;\r
+\r
+    // Stop PDC\r
+    if (channel == AC97C_CHANNEL_A_TRANSMIT) {\r
+\r
+        AT91C_BASE_AC97C->AC97C_PTCR = AT91C_PDC_TXTDIS;\r
+        size -= min(size, MAX_PDC_COUNTER) - AT91C_BASE_AC97C->AC97C_TCR;\r
+    }\r
+    if (channel == AC97C_CHANNEL_A_RECEIVE) {\r
+\r
+        AT91C_BASE_AC97C->AC97C_PTCR = AT91C_PDC_RXTDIS;\r
+        size -= min(size, MAX_PDC_COUNTER) - AT91C_BASE_AC97C->AC97C_RCR;\r
+    }\r
+\r
+    // Invoke callback if provided\r
+    if (pTransfer->callback) {\r
+\r
+        pTransfer->callback(pTransfer->pArg, AC97C_ERROR_STOPPED, size);\r
+    }\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Initializes the AC97 controller.\r
+//------------------------------------------------------------------------------\r
+void AC97C_Configure(void)\r
+{\r
+    unsigned char channel;\r
+\r
+    // Enable the AC97 controller peripheral clock\r
+    AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_AC97C);   \r
+    \r
+    // Enable the peripheral and variable rate adjustment\r
+    AT91C_BASE_AC97C->AC97C_MR = AT91C_AC97C_ENA  | AT91C_AC97C_VRA;\r
+\r
+    // Unassigns all input & output slots\r
+    AC97C_AssignInputSlots(0, 0xFFFF);\r
+    AC97C_AssignOutputSlots(0, 0xFFFF);\r
+\r
+    // Install the AC97C interrupt handler\r
+    AT91C_BASE_AC97C->AC97C_IDR = 0xFFFFFFFF;\r
+    AIC_ConfigureIT(AT91C_ID_AC97C, 0, AC97C_Handler);\r
+    AIC_EnableIT(AT91C_ID_AC97C);  \r
+\r
+    // Disable PDC transfers\r
+    AT91C_BASE_AC97C->AC97C_PTCR = AT91C_PDC_TXTDIS | AT91C_PDC_RXTDIS;\r
+\r
+    // Clear channel transfers\r
+    for (channel = 0; channel < AC97C_CHANNEL_B_TRANSMIT; channel++) {\r
+\r
+        ac97c.transfers[channel].numSamples = 0;\r
+    }\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Configures the desired channel with the given value.\r
+/// \param channel  Channel number.\r
+/// \param cfg  Configuration value.\r
+//------------------------------------------------------------------------------\r
+void AC97C_ConfigureChannel(unsigned char channel, unsigned int cfg)\r
+{\r
+    SANITY_CHECK((channel == AC97C_CHANNEL_A) || (channel == AC97C_CHANNEL_B));\r
+\r
+    if (channel == AC97C_CHANNEL_A) {\r
+\r
+        AT91C_BASE_AC97C->AC97C_CAMR = cfg;\r
+    }\r
+    else {\r
+\r
+        AT91C_BASE_AC97C->AC97C_CBMR = cfg;\r
+    }\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Assigns the desired input slots to a particular channel.\r
+/// \param channel  Channel number (or 0 to unassign slots).\r
+/// \param slots  Bitfield value of slots to assign.\r
+//------------------------------------------------------------------------------\r
+void AC97C_AssignInputSlots(unsigned char channel, unsigned int slots)\r
+{\r
+    unsigned int value;\r
+    unsigned int i;\r
+\r
+    SANITY_CHECK(channel <= AC97C_CHANNEL_B);\r
+\r
+    // Assign all slots\r
+    slots >>= 3;\r
+    for (i = 3; i < 15; i++) {\r
+\r
+        // Check if slots is selected\r
+        if (slots & 1) {\r
+\r
+            value = AT91C_BASE_AC97C->AC97C_ICA;\r
+            value &= ~(0x07 << ((i - 3) * 3));\r
+            value |= channel << ((i - 3) * 3);\r
+            AT91C_BASE_AC97C->AC97C_ICA = value;\r
+        }\r
+        slots >>= 1;\r
+    }\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Assigns the desired output slots to a particular channel.\r
+/// \param channel  Channel number (or 0 to unassign slots).\r
+/// \param slots  Bitfield value of slots to assign.\r
+//------------------------------------------------------------------------------\r
+void AC97C_AssignOutputSlots(unsigned char channel, unsigned int slots)\r
+{\r
+    unsigned int value;\r
+    unsigned int i;\r
+\r
+    SANITY_CHECK(channel <= AC97C_CHANNEL_B);\r
+\r
+    // Assign all slots\r
+    slots >>= 3;\r
+    for (i = 3; i < 15; i++) {\r
+\r
+        // Check if slots is selected\r
+        if (slots & 1) {\r
+\r
+            value = AT91C_BASE_AC97C->AC97C_OCA;\r
+            value &= ~(0x07 << ((i - 3) * 3));\r
+            value |= channel << ((i - 3) * 3);\r
+            AT91C_BASE_AC97C->AC97C_OCA = value;\r
+        }\r
+        slots >>= 1;\r
+    }\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Returns 1 if no transfer is currently pending on the given channel;\r
+/// otherwise, returns 0.\r
+/// \param channel  Channel number.\r
+//------------------------------------------------------------------------------\r
+unsigned char AC97C_IsFinished(unsigned char channel)\r
+{\r
+    SANITY_CHECK(channel <= AC97C_CHANNEL_B_TRANSMIT);\r
+\r
+    if (ac97c.transfers[channel].numSamples > 0) {\r
+\r
+        return 0;\r
+    }\r
+    else {\r
+\r
+        return 1;\r
+    }\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Convenience function for synchronously sending commands to the codec.\r
+/// \param address  Register address.\r
+/// \param data  Command data.\r
+//------------------------------------------------------------------------------\r
+void AC97C_WriteCodec(unsigned char address, unsigned short data)\r
+{\r
+    unsigned int sample;\r
+\r
+    sample = (address << 16) | data;\r
+    AC97C_Transfer(AC97C_CODEC_TRANSFER, (unsigned char *) &sample, 1, 0, 0);\r
+    while (!AC97C_IsFinished(AC97C_CODEC_TRANSFER));\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Convenience function for receiving data from the AC97 codec.\r
+/// \param address  Register address.\r
+//------------------------------------------------------------------------------\r
+unsigned short AC97C_ReadCodec(unsigned char address)\r
+{\r
+    unsigned int sample;\r
+\r
+    sample = AT91C_AC97C_READ | (address << 16);\r
+    AC97C_Transfer(AC97C_CODEC_TRANSFER, (unsigned char *) &sample, 1, 0, 0);\r
+    while (!AC97C_IsFinished(AC97C_CODEC_TRANSFER));\r
+\r
+    return sample;\r
+}\r
+            \r
+//------------------------------------------------------------------------------\r
+/// Sets the size in bits of one sample on the given channel.\r
+/// \param channel  Channel number.\r
+/// \param size  Size of one sample in bits (10, 16, 18 or 24).\r
+//------------------------------------------------------------------------------\r
+void AC97C_SetChannelSize(unsigned char channel, unsigned char size)\r
+{\r
+    unsigned int bits = 0;\r
+\r
+    SANITY_CHECK((size == 10) || (size == 16) || (size == 18) || (size == 24));\r
+    SANITY_CHECK((channel == AC97C_CHANNEL_A) || (channel == AC97C_CHANNEL_B));\r
+\r
+    switch (size) {\r
+\r
+        case 10 : bits = AT91C_AC97C_SIZE_10_BITS; break;\r
+        case 16 : bits = AT91C_AC97C_SIZE_16_BITS; break;\r
+        case 18 : bits = AT91C_AC97C_SIZE_18_BITS; break;\r
+        case 20 : bits = AT91C_AC97C_SIZE_20_BITS; break;\r
+    }\r
+\r
+    if (channel == AC97C_CHANNEL_A) {\r
+\r
+        AT91C_BASE_AC97C->AC97C_CAMR &= ~(AT91C_AC97C_SIZE);\r
+        AT91C_BASE_AC97C->AC97C_CAMR |= bits;\r
+    }\r
+    else {\r
+\r
+        AT91C_BASE_AC97C->AC97C_CBMR &= ~(AT91C_AC97C_SIZE);\r
+        AT91C_BASE_AC97C->AC97C_CBMR |= bits;\r
+    }\r
+}\r
+\r

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/ac97c/ac97c.h b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/ac97c/ac97c.h
new file mode 100644 (file)
index 0000000..1dbb1a8
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/ac97c/ac97c.h
@@ -0,0 +1,168 @@
+/* ----------------------------------------------------------------------------\r
+ *         ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+//------------------------------------------------------------------------------\r
+/// \unit\r
+///\r
+/// !!!Purpose\r
+/// \r
+/// This module provides definitions and functions for using the AC'97\r
+/// controller (AC97C).\r
+/// \r
+/// !!!Usage\r
+/// \r
+/// -# Enable the AC'97 interface pins (see pio & board.h).\r
+/// -# Configure the AC'97 controller using AC97C_Configure\r
+/// -# Assign the input and output slots to channels, and the data size used to\r
+///    transfer AC97 data stream.\r
+///    - Three functions can be used:\r
+///       - AC97C_AssignInputSlots: set slots for AC'97 data in, recording.\r
+///       - AC97C_AssignOutputSlots: set slots for AC'97 data out, playing.\r
+///       - AC97C_SetChannelSize: set data sizes in bits for AC'97 data stream.\r
+///    - Three different channels can be configured:\r
+///       - AC97C_CHANNEL_CODEC: AC'97 register access channel, its size is\r
+///         fixed and #must not# change by AC97C_SetChannelSize\r
+///       - AC97C_CHANNEL_A: AC'97 stream channel, with PDC support.\r
+///       - AC97C_CHANNEL_B: AC'97 data channel, without PDC support.\r
+/// -# Configure the used AC97 channel with AC97C_ConfigureChannel, to enable\r
+///    the channel.\r
+/// -# Then you can operate the connected AC'97 codec:\r
+///    - AC97C_ReadCodec / AC97C_WriteCodec: Read / Write codec register.\r
+///    - AC97C_Transfer: Transfer through AC97C channels to setup codec register\r
+///     or transfer %audio data stream.\r
+///       - AC97C_CODEC_TRANSFER: access the codec register.\r
+///       - AC97C_CHANNEL_A_RECEIVE, AC97C_CHANNEL_B_RECEIVE: start reading.\r
+///       - AC97C_CHANNEL_A_TRANSMIT, AC97C_CHANNEL_B_TRANSMIT: start writing.\r
+///    Normally you can initialize a set of AC'97 codec registers to initialize\r
+///    the codec for %audio playing and recording.\r
+/// -# Example code for playing & recording:\r
+///    - General process:\r
+///       -# Configure the codec registers for the %audio settings and formats;\r
+///       -# Setup the channel size if necessery;\r
+///       -# Start %audio stream transfer.\r
+///    - Audio playing sample:\r
+/// \code\r
+///    // Configure sample rate of codec\r
+///    AC97C_WriteCodec(AD1981B_PMC_DAC, expectedSampleRate);\r
+///    // Set channel size\r
+///    AC97C_SetChannelSize(AC97C_CHANNEL_A, bitsPerSample);\r
+///    // Start channel A transfer\r
+///    AC97C_Transfer(AC97C_CHANNEL_A_TRANSMIT, \r
+///                   (unsigned char *) (pointerToAudioDataBuffer),\r
+///                   numberOfSamplesToSend,\r
+///                   (Ac97Callback) PlayingFinished, \r
+///                   0);\r
+/// \endcode\r
+///    - Audio recording sample:\r
+/// \code\r
+///    // Enable recording\r
+///    AC97C_WriteCodec(AD1981B_REC_SEL, 0);\r
+///    // Set sample rate\r
+///    AC97C_WriteCodec(AD1981B_PMC_ADC, 7000);\r
+///    // Always use 16-bits recording\r
+///    AC97C_SetChannelSize(AC97C_CHANNEL_A, 16);\r
+///    // Start recording\r
+///    AC97C_Transfer(AC97C_CHANNEL_A_RECEIVE, \r
+///                   (unsigned char *) RECORD_ADDRESS,\r
+///                   MAX_RECORD_SIZE,\r
+///                   (Ac97Callback) RecordFinished,\r
+///                   0);\r
+/// \endcode\r
+//------------------------------------------------------------------------------\r
+\r
+#ifndef AC97C_H\r
+#define AC97C_H\r
+\r
+//------------------------------------------------------------------------------\r
+//         Constants\r
+//------------------------------------------------------------------------------\r
+\r
+/// The channel is already busy with a transfer.\r
+#define AC97C_ERROR_BUSY            1\r
+/// The transfer has been stopped by the user.\r
+#define AC97C_ERROR_STOPPED         2\r
+\r
+/// Codec channel index.\r
+#define AC97C_CHANNEL_CODEC         0\r
+/// Channel A index.\r
+#define AC97C_CHANNEL_A             1\r
+/// Channel B index.\r
+#define AC97C_CHANNEL_B             2\r
+\r
+/// Codec transmit/receive transfer index.\r
+#define AC97C_CODEC_TRANSFER        0\r
+/// Channel A receive transfer index.\r
+#define AC97C_CHANNEL_A_RECEIVE     1\r
+/// Channel A transmit transfer index.\r
+#define AC97C_CHANNEL_A_TRANSMIT    2\r
+/// Channel B receive transfer index.\r
+#define AC97C_CHANNEL_B_RECEIVE     3\r
+/// Channel B transmit transfer index.\r
+#define AC97C_CHANNEL_B_TRANSMIT    4\r
+\r
+//------------------------------------------------------------------------------\r
+//         Types\r
+//------------------------------------------------------------------------------\r
+\r
+/// AC97C transfer callback function.\r
+typedef void (*Ac97Callback)(void *pArg,\r
+                             unsigned char status,\r
+                             unsigned int remaining);\r
+\r
+//------------------------------------------------------------------------------\r
+//         Exported functions\r
+//------------------------------------------------------------------------------\r
+\r
+extern void AC97C_Configure();\r
+\r
+extern void AC97C_ConfigureChannel(unsigned char channel, unsigned int cfg);\r
+\r
+extern void AC97C_AssignInputSlots(unsigned char channel, unsigned int slots);\r
+\r
+extern void AC97C_AssignOutputSlots(unsigned char channel, unsigned int slots);\r
+\r
+extern unsigned char AC97C_Transfer(\r
+                unsigned char channel,\r
+                unsigned char *pBuffer,\r
+                unsigned int numSamples,\r
+                Ac97Callback callback,\r
+                void *pArg);\r
+\r
+extern unsigned char AC97C_IsFinished(unsigned char channel);\r
+\r
+extern void AC97C_WriteCodec(unsigned char address, unsigned short data);\r
+\r
+extern unsigned short AC97C_ReadCodec(unsigned char address);\r
+\r
+extern void AC97C_SetChannelSize(unsigned char channel, unsigned char size);\r
+\r
+extern void AC97C_CancelTransfer(unsigned char channel);\r
+\r
+#endif //#ifndef AC97C_H\r
+\r

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/adc/adc.c b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/adc/adc.c
new file mode 100644 (file)
index 0000000..8c12836
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/adc/adc.c
@@ -0,0 +1,346 @@
+/* ----------------------------------------------------------------------------\r
+ *         ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+//------------------------------------------------------------------------------\r
+//         Headers\r
+//------------------------------------------------------------------------------\r
+\r
+#include <board.h>\r
+#include <adc/adc.h>\r
+#include <utility/trace.h>\r
+#include <utility/assert.h>\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Configure the Mode Register of the ADC controller\r
+/// \param pAdc Pointer to an AT91S_ADC instance.\r
+/// \param mode value to write in mode register\r
+//-----------------------------------------------------------------------------\r
+\r
+//replaced with macro definition in adc.h\r
+\r
+//void ADC_CfgModeReg(AT91S_ADC *pAdc, unsigned int mode, unsigned int extmode)\r
+//{\r
+//    ASSERT((mode&0xF00000C0)== 0, "ADC Bad configuration ADC MR");\r
+//\r
+//    // Write to the MR register\r
+//    pAdc->ADC_MR = mode;\r
+//}\r
+\r
+//------------------------------------------------------------------------------\r
+//         Global Functions\r
+//------------------------------------------------------------------------------\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Initialize the ADC controller\r
+/// \param pAdc Pointer to an AT91S_ADC instance.\r
+/// \param trgEn trigger mode, software or Hardware\r
+/// \param trgSel hardware trigger selection\r
+/// \param sleepMode sleep mode selection\r
+/// \param resolution resolution selection 8 bits or 10 bits\r
+/// \param mckClock value of MCK in Hz\r
+/// \param adcClock value of the ADC clock in Hz\r
+/// \param startupTime value of the start up time (in µs) (see datasheet)\r
+/// \param sampleAndHoldTime (in ns)\r
+//-----------------------------------------------------------------------------\r
+void ADC_Initialize (AT91S_ADC *pAdc,\r
+                     unsigned char idAdc,\r
+                     unsigned char trgEn,\r
+                     unsigned char trgSel,\r
+                     unsigned char sleepMode,\r
+                     unsigned char resolution,        \r
+                     unsigned int mckClock,\r
+                     unsigned int adcClock,\r
+                     unsigned int startupTime,\r
+                     unsigned int sampleAndHoldTime)\r
+{\r
+    unsigned int prescal;\r
+    unsigned int startup;\r
+    unsigned int shtim;\r
+\r
+    ASSERT(startupTime<=ADC_STARTUP_TIME_MAX, "ADC Bad startupTime\n\r");\r
+    ASSERT(sampleAndHoldTime>=ADC_TRACK_HOLD_TIME_MIN, "ADC Bad sampleAndHoldTime\n\r");\r
+\r
+    // Example:\r
+    // 5 MHz operation, 20µs startup time, 600ns track and hold time\r
+    // PRESCAL: Prescaler Rate Selection ADCClock = MCK / ( (PRESCAL+1) * 2 )\r
+    // PRESCAL = [MCK / (ADCClock * 2)] -1 = [48/(5*2)]-1 = 3,8\r
+    // PRESCAL =  4 -> 48/((4+1)*2) = 48/10 = 4.8MHz\r
+    // 48/((3+1)*2) = 48/8 = 6MHz\r
+    // Startup Time = (STARTUP+1) * 8 / ADCClock\r
+    // STARTUP = [(Startup Time * ADCClock)/8]-1 = [(20 10e-6 * 5000000)/8]-1 = 11,5\r
+    // STARTUP = 11 -> (11+1)*8/48000000 = 96/4800000 = 20µs\r
+    //\r
+    // Sample & Hold Time = (SHTIM+1) / ADCClock\r
+    // SHTIM = (HoldTime * ADCClock)-1 = (600 10e-9 * 5000000)-1 = 2\r
+    // SHTIM   =  2 -> (2+1)/4800000 = 1/1200000 = 833ns\r
+    prescal = (mckClock / (2*adcClock)) - 1;\r
+    startup = ((adcClock/1000000) * startupTime / 8) - 1;\r
+    shtim = (((adcClock/1000000) * sampleAndHoldTime)/1000) - 1;\r
+\r
+    ASSERT( (prescal<0x3F), "ADC Bad PRESCAL\n\r");\r
+    ASSERT(startup<0x7F, "ADC Bad STARTUP\n\r");\r
+    ASSERT(shtim<0xF, "ADC Bad SampleAndHoldTime\n\r");\r
+\r
+    TRACE_DEBUG("adcClock:%d MasterClock:%d\n\r", (mckClock/((prescal+1)*2)), mckClock);\r
+    TRACE_DEBUG("prescal:0x%X startup:0x%X shtim:0x%X\n\r", prescal, startup, shtim);\r
+    \r
+    if( adcClock != (mckClock/((prescal+1)*2)) ) {\r
+        TRACE_WARNING("User and calculated adcClocks are different : user=%d calc=%d\n\r", \r
+            adcClock, (mckClock/((prescal+1)*2)));\r
+    }\r
+\r
+    // Enable peripheral clock    \r
+    AT91C_BASE_PMC->PMC_PCER = 1 << idAdc;    \r
+    \r
+    // Reset the controller\r
+    ADC_SoftReset(pAdc);\r
+\r
+    // Write to the MR register\r
+    ADC_CfgModeReg( pAdc,\r
+                    ( trgEn & AT91C_ADC_TRGEN)\r
+                  | ( trgSel & AT91C_ADC_TRGSEL)\r
+                  | ( resolution & AT91C_ADC_LOWRES)            \r
+                  | ( sleepMode & AT91C_ADC_SLEEP)\r
+                  | ( (prescal<<8) & AT91C_ADC_PRESCAL) \r
+                  | ( (startup<<16) & AT91C_ADC_STARTUP) \r
+                  | ( (shtim<<24) & AT91C_ADC_SHTIM) );\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Return the Mode Register of the ADC controller value\r
+/// \param pAdc Pointer to an AT91S_ADC instance.\r
+/// \return ADC Mode register\r
+//-----------------------------------------------------------------------------\r
+\r
+//replaced with macro definition in adc.h\r
+\r
+//unsigned int ADC_GetModeReg(AT91S_ADC *pAdc)\r
+//{\r
+//    return pAdc->ADC_MR;    \r
+//}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Enable Channel\r
+/// \param pAdc Pointer to an AT91S_ADC instance.\r
+/// \param channel channel to enable\r
+//-----------------------------------------------------------------------------\r
+//void ADC_EnableChannel(AT91S_ADC *pAdc, unsigned int channel)\r
+//{\r
+//    ASSERT(channel < 8, "ADC Channel not exist");\r
+//\r
+//    // Write to the CHER register\r
+//    pAdc->ADC_CHER = (1 << channel);\r
+//}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Disable Channel\r
+/// \param pAdc Pointer to an AT91S_ADC instance.\r
+/// \param channel channel to disable\r
+//-----------------------------------------------------------------------------\r
+//void ADC_DisableChannel (AT91S_ADC *pAdc, unsigned int channel)\r
+//{\r
+//    ASSERT(channel < 8, "ADC Channel not exist");\r
+//\r
+//    // Write to the CHDR register\r
+//    pAdc->ADC_CHDR = (1 << channel);\r
+//}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Return chanel status\r
+/// \param pAdc Pointer to an AT91S_ADC instance.\r
+/// \return ADC Channel Status Register\r
+//-----------------------------------------------------------------------------\r
+//unsigned int ADC_GetChannelStatus(AT91S_ADC *pAdc)\r
+//{\r
+//    return pAdc->ADC_CHSR;    \r
+//}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Software request for a analog to digital conversion \r
+/// \param pAdc Pointer to an AT91S_ADC instance.\r
+//-----------------------------------------------------------------------------\r
+//void ADC_StartConversion(AT91S_ADC *pAdc)\r
+//{\r
+//    pAdc->ADC_CR = AT91C_ADC_START;    \r
+//}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Software reset\r
+/// \param pAdc Pointer to an AT91S_ADC instance.\r
+//-----------------------------------------------------------------------------\r
+//void ADC_SoftReset(AT91S_ADC *pAdc)\r
+//{\r
+//    pAdc->ADC_CR = AT91C_ADC_SWRST;    \r
+//}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Return the Last Converted Data\r
+/// \param pAdc Pointer to an AT91S_ADC instance.\r
+/// \return Last Converted Data\r
+//-----------------------------------------------------------------------------\r
+//unsigned int ADC_GetLastConvertedData(AT91S_ADC *pAdc)\r
+//{\r
+//    return pAdc->ADC_LCDR;    \r
+//}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Return the Channel Converted Data\r
+/// \param pAdc Pointer to an AT91S_ADC instance.\r
+/// \param channel channel to get converted value\r
+/// \return Channel converted data of the specified channel\r
+//-----------------------------------------------------------------------------\r
+unsigned int ADC_GetConvertedData(AT91S_ADC *pAdc, unsigned int channel)\r
+{\r
+    unsigned int data=0;\r
+    \r
+    ASSERT(channel < 8, "ADC channel not exist");\r
+    \r
+    switch(channel) {\r
+        case 0: data = pAdc->ADC_CDR0; break;\r
+        case 1: data = pAdc->ADC_CDR1; break;\r
+        case 2: data = pAdc->ADC_CDR2; break;\r
+        case 3: data = pAdc->ADC_CDR3; break;\r
+        #ifdef AT91C_ADC_CDR4\r
+        case 4: data = pAdc->ADC_CDR4; break;\r
+        #endif\r
+        #ifdef AT91C_ADC_CDR5\r
+        case 5: data = pAdc->ADC_CDR5; break;\r
+        #endif\r
+        #ifdef AT91C_ADC_CDR6\r
+        case 6: data = pAdc->ADC_CDR6; break;\r
+        #endif\r
+        #ifdef AT91C_ADC_CDR7\r
+        case 7: data = pAdc->ADC_CDR7; break;    \r
+        #endif\r
+    }\r
+    return data;    \r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Enable ADC interrupt\r
+/// \param pAdc Pointer to an AT91S_ADC instance.\r
+/// \param flag IT to be enabled\r
+//-----------------------------------------------------------------------------\r
+//void ADC_EnableIt(AT91S_ADC *pAdc, unsigned int flag)\r
+//{\r
+//    ASSERT((flag&0xFFF00000)== 0, "ADC bad interrupt IER");\r
+//\r
+//    // Write to the IER register\r
+//    pAdc->ADC_IER = flag;\r
+//}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Enable ADC Data Ready interrupt\r
+/// \param pAdc Pointer to an AT91S_ADC instance.\r
+//-----------------------------------------------------------------------------\r
+\r
+//void ADC_EnableDataReadyIt(AT91S_ADC *pAdc)\r
+//{\r
+//    pAdc->ADC_IER = AT91C_ADC_DRDY;\r
+//}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Disable ADC interrupt\r
+/// \param pAdc Pointer to an AT91S_ADC instance.\r
+/// \param flag IT to be disabled\r
+//-----------------------------------------------------------------------------\r
+//void ADC_DisableIt(AT91S_ADC *pAdc, unsigned int flag)\r
+//{\r
+//    ASSERT((flag&0xFFF00000)== 0, "ADC bad interrupt IDR");\r
+//\r
+//    // Write to the IDR register\r
+//    pAdc->ADC_IDR = flag;\r
+//}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Return ADC Interrupt Status\r
+/// \param pAdc Pointer to an AT91S_ADC instance.\r
+/// \return ADC Stats register\r
+//-----------------------------------------------------------------------------\r
+//unsigned int ADC_GetStatus(AT91S_ADC *pAdc)\r
+//{\r
+//    return pAdc->ADC_SR;\r
+//}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Return ADC Interrupt Mask Status\r
+/// \param pAdc Pointer to an AT91S_ADC instance.\r
+/// \return ADC Interrupt Mask Register\r
+//-----------------------------------------------------------------------------\r
+//unsigned int ADC_GetInterruptMaskStatus(AT91S_ADC *pAdc)\r
+//{\r
+//    return pAdc->ADC_IMR;\r
+//}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Test if ADC Interrupt is Masked \r
+/// \param pAdc Pointer to an AT91S_ADC instance.\r
+/// \param flag flag to be tested\r
+/// \return 1 if interrupt is masked, otherwise 0\r
+//-----------------------------------------------------------------------------\r
+unsigned int ADC_IsInterruptMasked(AT91S_ADC *pAdc, unsigned int flag)\r
+{\r
+    return (ADC_GetInterruptMaskStatus(pAdc) & flag);\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Test if ADC Status is Set\r
+/// \param pAdc Pointer to an AT91S_ADC instance.\r
+/// \param flag flag to be tested\r
+/// \return 1 if the staus is set; 0 otherwise\r
+//-----------------------------------------------------------------------------\r
+unsigned int ADC_IsStatusSet(AT91S_ADC *pAdc, unsigned int flag)\r
+{\r
+    return (ADC_GetStatus(pAdc) & flag);\r
+}\r
+\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Test if ADC channel interrupt Status is Set\r
+/// \param adc_sr Value of SR register\r
+/// \param channel Channel to be tested\r
+/// \return 1 if interrupt status is set, otherwise 0\r
+//-----------------------------------------------------------------------------\r
+unsigned char ADC_IsChannelInterruptStatusSet(unsigned int adc_sr, \r
+                                              unsigned int channel)\r
+{\r
+    unsigned char status;\r
+    \r
+    if((adc_sr & (1<<channel)) == (1<<channel)) {\r
+        status = 1;\r
+    }\r
+    else {\r
+        status = 0;\r
+    }\r
+    return status;\r
+}\r
+\r
+\r
+\r
+\r

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/adc/adc.h b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/adc/adc.h
new file mode 100644 (file)
index 0000000..331ceae
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/adc/adc.h
@@ -0,0 +1,145 @@
+/* ----------------------------------------------------------------------------\r
+ *         ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+//------------------------------------------------------------------------------\r
+/// \unit\r
+///\r
+/// !Purpose\r
+///\r
+/// Interface for configuration the Analog-to-Digital Converter (ADC) peripheral.\r
+///\r
+/// !Usage\r
+///\r
+/// -# Configurate the pins for ADC\r
+/// -# Initialize the ADC with ADC_Initialize().\r
+/// -# Select the active channel using ADC_EnableChannel()\r
+/// -# Start the conversion with ADC_StartConversion()\r
+//  -# Wait the end of the conversion by polling status with ADC_GetStatus()\r
+//  -# Finally, get the converted data using ADC_GetConvertedData()\r
+///\r
+//------------------------------------------------------------------------------\r
+#ifndef ADC_H\r
+#define ADC_H\r
+\r
+//------------------------------------------------------------------------------\r
+//         Headers\r
+//------------------------------------------------------------------------------\r
+#include <utility/assert.h>\r
+\r
+//------------------------------------------------------------------------------\r
+//         Definitions\r
+//------------------------------------------------------------------------------\r
+#define ADC_CHANNEL_0 0\r
+#define ADC_CHANNEL_1 1\r
+#define ADC_CHANNEL_2 2\r
+#define ADC_CHANNEL_3 3\r
+#define ADC_CHANNEL_4 4\r
+#define ADC_CHANNEL_5 5\r
+#define ADC_CHANNEL_6 6\r
+#define ADC_CHANNEL_7 7\r
+\r
+//------------------------------------------------------------------------------\r
+//         Macros function of register access\r
+//------------------------------------------------------------------------------\r
+#define ADC_CfgModeReg(pAdc, mode)  { \\r
+            ASSERT(((mode)&0xF00000C0)== 0, "ADC Bad configuration ADC MR");\\r
+            (pAdc)->ADC_MR = (mode);\\r
+        }\r
+\r
+#define ADC_GetModeReg(pAdc)                ((pAdc)->ADC_MR)\r
+\r
+#define ADC_StartConversion(pAdc)           ((pAdc)->ADC_CR = AT91C_ADC_START)\r
+\r
+#define ADC_SoftReset(pAdc)                 ((pAdc)->ADC_CR = AT91C_ADC_SWRST)\r
+\r
+#define ADC_EnableChannel(pAdc, channel)    {\\r
+            ASSERT(channel < 8, "ADC Channel not exist");\\r
+            (pAdc)->ADC_CHER = (1 << (channel));\\r
+        }\r
+\r
+#define ADC_DisableChannel (pAdc, channel)  {\\r
+            ASSERT((channel) < 8, "ADC Channel not exist");\\r
+            (pAdc)->ADC_CHDR = (1 << (channel));\\r
+        }\r
+\r
+\r
+#define ADC_EnableIt(pAdc, mode)            {\\r
+            ASSERT(((mode)&0xFFF00000)== 0, "ADC bad interrupt IER");\\r
+            (pAdc)->ADC_IER = (mode);\\r
+        }\r
+\r
+#define ADC_DisableIt(pAdc, mode)           {\\r
+            ASSERT(((mode)&0xFFF00000)== 0, "ADC bad interrupt IDR");\\r
+            (pAdc)->ADC_IDR = (mode);\\r
+        }\r
+\r
+#define ADC_EnableDataReadyIt(pAdc)         ((pAdc)->ADC_IER = AT91C_ADC_DRDY)\r
+\r
+#define ADC_GetStatus(pAdc)                 ((pAdc)->ADC_SR)\r
+\r
+#define ADC_GetChannelStatus(pAdc)          ((pAdc)->ADC_CHSR)\r
+\r
+#define ADC_GetInterruptMaskStatus(pAdc)    ((pAdc)->ADC_IMR)\r
+\r
+#define ADC_GetLastConvertedData(pAdc)      ((pAdc)->ADC_LCDR)\r
+\r
+\r
+//------------------------------------------------------------------------------\r
+//         Exported functions\r
+//------------------------------------------------------------------------------\r
+extern void ADC_Initialize (AT91S_ADC *pAdc,\r
+                     unsigned char idAdc,\r
+                     unsigned char trgEn,\r
+                     unsigned char trgSel,\r
+                     unsigned char sleepMode,\r
+                     unsigned char resolution,        \r
+                     unsigned int mckClock,\r
+                     unsigned int adcClock,\r
+                     unsigned int startupTime,\r
+                     unsigned int sampleAndHoldTime);\r
+//extern void ADC_CfgModeReg(AT91S_ADC *pAdc, unsigned int mode);\r
+//extern unsigned int ADC_GetModeReg(AT91S_ADC *pAdc);\r
+//extern void ADC_EnableChannel(AT91S_ADC *pAdc, unsigned int channel);\r
+//extern void ADC_DisableChannel (AT91S_ADC *pAdc, unsigned int channel);\r
+//extern unsigned int ADC_GetChannelStatus(AT91S_ADC *pAdc);\r
+//extern void ADC_StartConversion(AT91S_ADC *pAdc);\r
+//extern void ADC_SoftReset(AT91S_ADC *pAdc);\r
+//extern unsigned int ADC_GetLastConvertedData(AT91S_ADC *pAdc);\r
+extern unsigned int ADC_GetConvertedData(AT91S_ADC *pAdc, unsigned int channel);\r
+//extern void ADC_EnableIt(AT91S_ADC *pAdc, unsigned int flag);\r
+//extern void ADC_EnableDataReadyIt(AT91S_ADC *pAdc);\r
+//extern void ADC_DisableIt(AT91S_ADC *pAdc, unsigned int flag);\r
+//extern unsigned int ADC_GetStatus(AT91S_ADC *pAdc);\r
+//extern unsigned int ADC_GetInterruptMaskStatus(AT91S_ADC *pAdc);\r
+extern unsigned int ADC_IsInterruptMasked(AT91S_ADC *pAdc, unsigned int flag);\r
+extern unsigned int ADC_IsStatusSet(AT91S_ADC *pAdc, unsigned int flag);\r
+extern unsigned char ADC_IsChannelInterruptStatusSet(unsigned int adc_sr, \r
+                                              unsigned int channel);\r
+\r
+#endif //#ifndef ADC_H\r

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/adc/adc12.h b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/adc/adc12.h
new file mode 100644 (file)
index 0000000..bbf3b46
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/adc/adc12.h
@@ -0,0 +1,142 @@
+/* ----------------------------------------------------------------------------\r
+ *         ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+//------------------------------------------------------------------------------\r
+/// \unit\r
+///\r
+/// !Purpose\r
+///\r
+/// Interface for configuration the Analog-to-Digital Converter (ADC) peripheral.\r
+///\r
+/// !Usage\r
+///\r
+/// -# Configurate the pins for ADC\r
+/// -# Initialize the ADC with ADC_Initialize().\r
+/// -# Select the active channel using ADC_EnableChannel()\r
+/// -# Start the conversion with ADC_StartConversion()\r
+//  -# Wait the end of the conversion by polling status with ADC_GetStatus()\r
+//  -# Finally, get the converted data using ADC_GetConvertedData()\r
+///\r
+//------------------------------------------------------------------------------\r
+#ifndef ADC12_H\r
+#define ADC12_H\r
+\r
+//------------------------------------------------------------------------------\r
+//         Headers\r
+//------------------------------------------------------------------------------\r
+#include <utility/assert.h>\r
+\r
+//------------------------------------------------------------------------------\r
+//         Definitions\r
+//------------------------------------------------------------------------------\r
+#define ADC_CHANNEL_0 0\r
+#define ADC_CHANNEL_1 1\r
+#define ADC_CHANNEL_2 2\r
+#define ADC_CHANNEL_3 3\r
+#define ADC_CHANNEL_4 4\r
+#define ADC_CHANNEL_5 5\r
+#define ADC_CHANNEL_6 6\r
+#define ADC_CHANNEL_7 7\r
+\r
+//------------------------------------------------------------------------------\r
+//         Macros function of register access\r
+//------------------------------------------------------------------------------\r
+#define ADC12_CfgModeReg(pAdc, mode)  { \\r
+            ASSERT(((mode)&0xF00000C0)== 0, "ADC Bad configuration ADC MR");\\r
+            (pAdc)->ADC_MR = (mode);\\r
+        }\r
+\r
+#define ADC12_GetModeReg(pAdc)                ((pAdc)->ADC_MR)\r
+\r
+#define ADC12_StartConversion(pAdc)           ((pAdc)->ADC_CR = AT91C_ADC_START)\r
+\r
+#define ADC12_SoftReset(pAdc)                 ((pAdc)->ADC_CR = AT91C_ADC_SWRST)\r
+\r
+#define ADC12_EnableChannel(pAdc, channel)    {\\r
+            ASSERT(channel < 8, "ADC Channel not exist");\\r
+            (pAdc)->ADC_CHER = (1 << (channel));\\r
+        }\r
+\r
+#define ADC12_DisableChannel (pAdc, channel)  {\\r
+            ASSERT((channel) < 8, "ADC Channel not exist");\\r
+            (pAdc)->ADC_CHDR = (1 << (channel));\\r
+        }\r
+\r
+#define ADC12_EnableIt(pAdc, mode)            {\\r
+            ASSERT(((mode)&0xFFF00000)== 0, "ADC bad interrupt IER");\\r
+            (pAdc)->ADC_IER = (mode);\\r
+        }\r
+\r
+#define ADC12_DisableIt(pAdc, mode)           {\\r
+            ASSERT(((mode)&0xFFF00000)== 0, "ADC bad interrupt IDR");\\r
+            (pAdc)->ADC_IDR = (mode);\\r
+        }\r
+\r
+#define ADC12_EnableDataReadyIt(pAdc)         ((pAdc)->ADC_IER = AT91C_ADC_DRDY)\r
+\r
+#define ADC12_GetStatus(pAdc)                 ((pAdc)->ADC_SR)\r
+\r
+#define ADC12_GetChannelStatus(pAdc)          ((pAdc)->ADC_CHSR)\r
+\r
+#define ADC12_GetInterruptMaskStatus(pAdc)    ((pAdc)->ADC_IMR)\r
+\r
+#define ADC12_GetLastConvertedData(pAdc)      ((pAdc)->ADC_LCDR)\r
+\r
+#define ADC12_CfgAnalogCtrlReg(pAdc,mode)     {\\r
+            ASSERT(((mode) & 0xFFFCFF3C)==0, "ADC bad analog control config");\\r
+            (pAdc)->ADC_ACR = (mode);\\r
+        }\r
+\r
+#define ADC12_CfgExtModeReg(pAdc, extmode)    {\\r
+            ASSERT(((extmode) & 0xFF00FFFE)==0, "ADC bad extended mode config");\\r
+            (pAdc)->ADC_EMR = (extmode);\\r
+        }\r
+\r
+#define ADC12_GetAnalogCtrlReg(pAdc)          ((pAdc)->ADC_ACR)\r
+\r
+//------------------------------------------------------------------------------\r
+//         Exported functions\r
+//------------------------------------------------------------------------------\r
+extern void ADC12_Initialize (AT91S_ADC *pAdc,\r
+                     unsigned char idAdc,\r
+                     unsigned char trgEn,\r
+                     unsigned char trgSel,\r
+                     unsigned char sleepMode,\r
+                     unsigned char resolution,        \r
+                     unsigned int mckClock,\r
+                     unsigned int adcClock,\r
+                     unsigned int startupTime,\r
+                     unsigned int sampleAndHoldTime);\r
+extern unsigned int ADC12_GetConvertedData(AT91S_ADC *pAdc, unsigned int channel);\r
+extern unsigned int ADC12_IsInterruptMasked(AT91S_ADC *pAdc, unsigned int flag);\r
+extern unsigned int ADC12_IsStatusSet(AT91S_ADC *pAdc, unsigned int flag);\r
+extern unsigned char ADC12_IsChannelInterruptStatusSet(unsigned int adc_sr, \r
+                                              unsigned int channel);\r
+\r
+#endif //#ifndef ADC12_H\r

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/aes/aes.c b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/aes/aes.c
new file mode 100644 (file)
index 0000000..09848f8
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/aes/aes.c
@@ -0,0 +1,192 @@
+/* ----------------------------------------------------------------------------\r
+ *         ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+//------------------------------------------------------------------------------\r
+//         Headers\r
+//------------------------------------------------------------------------------\r
+\r
+#include "aes.h"\r
+#include <board.h>\r
+#include <utility/trace.h>\r
+#include <utility/assert.h>\r
+\r
+//------------------------------------------------------------------------------\r
+//         Global functions\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+/// Configures the AES peripheral to encrypt/decrypt, start mode (manual, auto,\r
+/// PDC) and operating mode (ECB, CBC, OFB, CFB, CTR).\r
+/// \param cipher  Indicates if the peripheral should encrypt or decrypt data.\r
+/// \param smode  Start mode.\r
+/// \param opmode  Operating mode.\r
+//------------------------------------------------------------------------------\r
+void AES_Configure(\r
+    unsigned char cipher,\r
+    unsigned int smode,\r
+    unsigned int opmode)\r
+{\r
+    TRACE_DEBUG("AES_Configure()\n\r");\r
+    SANITY_CHECK((cipher & 0xFFFFFFFE) == 0);\r
+    SANITY_CHECK((smode & 0xFFFFFCFF) == 0);\r
+    SANITY_CHECK((opmode & 0xFFFF8FFF) == 0);\r
+\r
+    // Reset the peripheral first\r
+    AT91C_BASE_AES->AES_CR = AT91C_AES_SWRST;\r
+\r
+    // Configure mode register\r
+    AT91C_BASE_AES->AES_MR = cipher | smode | opmode;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Sets the key used by the AES algorithm to cipher the plain text or\r
+/// decipher the encrypted text.\r
+/// \param pKey  Pointer to a 16-bytes cipher key.\r
+//------------------------------------------------------------------------------\r
+void AES_SetKey(const unsigned int *pKey)\r
+{\r
+    TRACE_DEBUG("AES_SetKey()\n\r");\r
+    SANITY_CHECK(pKey);\r
+\r
+    AT91C_BASE_AES->AES_KEYWxR[0] = pKey[0];\r
+    AT91C_BASE_AES->AES_KEYWxR[1] = pKey[1];\r
+    AT91C_BASE_AES->AES_KEYWxR[2] = pKey[2];\r
+    AT91C_BASE_AES->AES_KEYWxR[3] = pKey[3];\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Sets the initialization vector that is used to encrypt the plain text or\r
+/// decrypt the cipher text in chained block modes (CBC, CFB, OFB & CTR).\r
+/// \param pVector  Pointer to a 16-bytes initialization vector.\r
+//------------------------------------------------------------------------------\r
+void AES_SetVector(const unsigned int *pVector)\r
+{\r
+    TRACE_DEBUG("AES_SetVector()\n\r");\r
+    SANITY_CHECK(pVector);\r
+\r
+    AT91C_BASE_AES->AES_IVxR[0] = pVector[0];\r
+    AT91C_BASE_AES->AES_IVxR[1] = pVector[1];\r
+    AT91C_BASE_AES->AES_IVxR[2] = pVector[2];\r
+    AT91C_BASE_AES->AES_IVxR[3] = pVector[3];\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Sets the input data of the AES algorithm (i.e. plain text in cipher mode,\r
+/// ciphered text in decipher mode). If auto mode is active, the encryption is\r
+/// started automatically after writing the last word.\r
+/// \param pData  Pointer to the 16-bytes data to cipher/decipher.\r
+//------------------------------------------------------------------------------\r
+void AES_SetInputData(const unsigned int *pData)\r
+{\r
+    TRACE_DEBUG("AES_SetInputData()\n\r");\r
+    SANITY_CHECK(pData);\r
+\r
+    AT91C_BASE_AES->AES_IDATAxR[0] = pData[0];\r
+    AT91C_BASE_AES->AES_IDATAxR[1] = pData[1];\r
+    AT91C_BASE_AES->AES_IDATAxR[2] = pData[2];\r
+    AT91C_BASE_AES->AES_IDATAxR[3] = pData[3];\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Stores the result of the last AES operation (encrypt/decrypt) in the\r
+/// provided buffer.\r
+/// \param pData  Pointer to a 16-bytes buffer.\r
+//------------------------------------------------------------------------------\r
+void AES_GetOutputData(unsigned int *pData)\r
+{\r
+    TRACE_DEBUG("AES_GetOutputData()\n\r");\r
+    SANITY_CHECK(pData);\r
+\r
+    pData[0] = AT91C_BASE_AES->AES_ODATAxR[0];\r
+    pData[1] = AT91C_BASE_AES->AES_ODATAxR[1];\r
+    pData[2] = AT91C_BASE_AES->AES_ODATAxR[2];\r
+    pData[3] = AT91C_BASE_AES->AES_ODATAxR[3];\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Sets the input buffer to use when in PDC mode.\r
+/// \param pInput  Pointer to the input buffer.\r
+//------------------------------------------------------------------------------\r
+void AES_SetInputBuffer(const unsigned int *pInput)\r
+{\r
+    TRACE_DEBUG("AES_SetInputBuffer()\n\r");\r
+    SANITY_CHECK(pInput);\r
+\r
+    AT91C_BASE_AES->AES_TPR = (unsigned int) pInput;\r
+    AT91C_BASE_AES->AES_TCR = 4;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Sets the output buffer to use when in PDC mode.\r
+/// \param pOutput  Pointer to the output buffer.\r
+//------------------------------------------------------------------------------\r
+void AES_SetOutputBuffer(unsigned int *pOutput)\r
+{\r
+    TRACE_DEBUG("AES_SetOutputBuffer()\n\r");\r
+    SANITY_CHECK(pOutput);\r
+\r
+    AT91C_BASE_AES->AES_RPR = (unsigned int) pOutput;\r
+    AT91C_BASE_AES->AES_RCR = 4;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Starts the encryption/decryption process when in manual or PDC mode. In\r
+/// manual mode, the key and input data must have been entered using\r
+/// AES_SetKey() and AES_SetInputData(). In PDC mode, the key, input & output\r
+/// buffer must have been set using AES_SetKey(), AES_SetInputBuffer() and\r
+/// AES_SetOutputBuffer().\r
+//------------------------------------------------------------------------------\r
+void AES_Start(void)\r
+{\r
+    TRACE_DEBUG("AES_Start()\n\r");\r
+    SANITY_CHECK(((AT91C_BASE_AES->AES_MR & AT91C_AES_SMOD) == AT91C_AES_SMOD_MANUAL)\r
+                 || ((AT91C_BASE_AES->AES_MR & AT91C_AES_SMOD) == AT91C_AES_SMOD_PDC));\r
+\r
+    // Manual mode\r
+    if ((AT91C_BASE_AES->AES_MR & AT91C_AES_SMOD) == AT91C_AES_SMOD_MANUAL) {\r
+\r
+        AT91C_BASE_AES->AES_CR = AT91C_AES_START;\r
+    }\r
+    // PDC\r
+    else {\r
+\r
+        AT91C_BASE_AES->AES_PTCR = AT91C_PDC_RXTEN | AT91C_PDC_TXTEN;\r
+    }\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Returns the current value of the AES interrupt status register.\r
+//------------------------------------------------------------------------------\r
+unsigned int AES_GetStatus(void)\r
+{\r
+    TRACE_DEBUG("AES_GetStatus()\n\r");\r
+\r
+    return AT91C_BASE_AES->AES_ISR;\r
+}\r
+\r

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/aes/aes.h b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/aes/aes.h
new file mode 100644 (file)
index 0000000..9f2f857
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/aes/aes.h
@@ -0,0 +1,76 @@
+/* ----------------------------------------------------------------------------\r
+ *         ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+#ifndef AES_H\r
+#define AES_H\r
+\r
+//------------------------------------------------------------------------------\r
+/// \unit\r
+///\r
+/// !Purpose\r
+/// \r
+/// Methods to manage the Advanced Encryption Standard (AES)\r
+/// \r
+/// !Usage\r
+///\r
+/// -# Configure AES\r
+/// -# Sets the key used by the AES algorithm\r
+/// -# Sets the input data of the AES algorithm\r
+/// -# Starts the encryption/decryption process\r
+/// -# Stores the result of the last AES operation\r
+///\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+//         Global functions\r
+//------------------------------------------------------------------------------\r
+\r
+extern void AES_Configure(\r
+    unsigned char cipher,\r
+    unsigned int smode,\r
+    unsigned int opmode);\r
+\r
+extern void AES_SetKey(const unsigned int *pKey);\r
+\r
+extern void AES_SetVector(const unsigned int *pVector);\r
+\r
+extern void AES_SetInputData(const unsigned int *pData);\r
+\r
+extern void AES_GetOutputData(unsigned int *pData);\r
+\r
+extern void AES_SetInputBuffer(const unsigned int *pInput);\r
+\r
+extern void AES_SetOutputBuffer(unsigned int *pOutput);\r
+\r
+extern void AES_Start(void);\r
+\r
+extern unsigned int AES_GetStatus(void);\r
+\r
+#endif //#ifndef AES_H\r
+\r

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/aic/aic.c b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/aic/aic.c
new file mode 100644 (file)
index 0000000..4ff52c2
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/aic/aic.c
@@ -0,0 +1,87 @@
+/* ----------------------------------------------------------------------------\r
+ *         ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+//------------------------------------------------------------------------------\r
+//         Headers\r
+//------------------------------------------------------------------------------\r
+\r
+#include "aic.h"\r
+#include <board.h>\r
+\r
+//------------------------------------------------------------------------------\r
+//         Global functions\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+/// Configures an interrupt in the AIC. The interrupt is identified by its\r
+/// source (AT91C_ID_xxx) and is configured to use the specified mode and\r
+/// interrupt handler function. Mode is the value that will be put in AIC_SMRx\r
+/// and the function address will be set in AIC_SVRx.\r
+/// The interrupt is disabled before configuration, so it is useless\r
+/// to do it before calling this function. When AIC_ConfigureIT returns, the\r
+/// interrupt will always be disabled and cleared; it must be enabled by a\r
+/// call to AIC_EnableIT().\r
+/// \param source  Interrupt source to configure.\r
+/// \param mode  Triggering mode and priority of the interrupt.\r
+/// \param handler  Interrupt handler function.\r
+//------------------------------------------------------------------------------\r
+void AIC_ConfigureIT(\r
+    unsigned int source,\r
+    unsigned int mode,\r
+    void (*handler)(void))\r
+{\r
+    // Disable the interrupt first\r
+    AT91C_BASE_AIC->AIC_IDCR = 1 << source;\r
+\r
+    // Configure mode and handler\r
+    AT91C_BASE_AIC->AIC_SMR[source] = mode;\r
+    AT91C_BASE_AIC->AIC_SVR[source] = (unsigned int) handler;\r
+\r
+    // Clear interrupt\r
+    AT91C_BASE_AIC->AIC_ICCR = 1 << source;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Enables interrupts coming from the given (unique) source (AT91C_ID_xxx).\r
+/// \param source  Interrupt source to enable.\r
+//------------------------------------------------------------------------------\r
+void AIC_EnableIT(unsigned int source)\r
+{\r
+    AT91C_BASE_AIC->AIC_IECR = 1 << source;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Disables interrupts coming from the given (unique) source (AT91C_ID_xxx).\r
+/// \param source  Interrupt source to enable.\r
+//------------------------------------------------------------------------------\r
+void AIC_DisableIT(unsigned int source)\r
+{\r
+    AT91C_BASE_AIC->AIC_IDCR = 1 << source;\r
+}\r
+\r

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/aic/aic.h b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/aic/aic.h
new file mode 100644 (file)
index 0000000..bddf787
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/aic/aic.h
@@ -0,0 +1,79 @@
+/* ----------------------------------------------------------------------------\r
+ *         ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+//------------------------------------------------------------------------------\r
+/// \unit\r
+///\r
+/// !Purpose\r
+/// \r
+/// Methods and definitions for configuring interrupts using the Advanced\r
+/// Interrupt Controller (AIC).\r
+/// \r
+/// !Usage\r
+///\r
+/// -# Configure an interrupt source using AIC_ConfigureIT\r
+/// -# Enable or disable interrupt generation of a particular source with\r
+///    AIC_EnableIT and AIC_DisableIT.\r
+///\r
+/// \note Most of the time, peripheral interrupts must be also configured\r
+/// inside the peripheral itself.\r
+//------------------------------------------------------------------------------\r
+\r
+#ifndef AIC_H\r
+#define AIC_H\r
+\r
+//------------------------------------------------------------------------------\r
+//         Headers\r
+//------------------------------------------------------------------------------\r
+\r
+#include <board.h>\r
+\r
+//------------------------------------------------------------------------------\r
+//         Definitions\r
+//------------------------------------------------------------------------------\r
+\r
+#ifndef AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL\r
+    /// Interrupt is internal and uses a logical 1 level.\r
+    #define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+//         Global functions\r
+//------------------------------------------------------------------------------\r
+\r
+extern void AIC_ConfigureIT(unsigned int source,\r
+                                   unsigned int mode,\r
+                                   void (*handler)( void ));\r
+\r
+extern void AIC_EnableIT(unsigned int source);\r
+\r
+extern void AIC_DisableIT(unsigned int source);\r
+\r
+#endif //#ifndef AIC_H\r
+\r

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/can/can.c b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/can/can.c
new file mode 100644 (file)
index 0000000..3c26835
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/can/can.c
@@ -0,0 +1,1066 @@
+/* ----------------------------------------------------------------------------\r
+ *         ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+//------------------------------------------------------------------------------\r
+//         Headers\r
+//------------------------------------------------------------------------------\r
+\r
+#include <board.h>\r
+#include <pio/pio.h>\r
+#include <utility/trace.h>\r
+#include <aic/aic.h>\r
+#include "can.h"\r
+\r
+//------------------------------------------------------------------------------\r
+//         Local definitions\r
+//------------------------------------------------------------------------------\r
+// CAN state\r
+#define CAN_DISABLED       0\r
+#define CAN_HALTED         1\r
+#define CAN_IDLE           2\r
+#define CAN_SENDING        3\r
+#define CAN_RECEIVING      4\r
+\r
+// MOT: Mailbox Object Type\r
+#define CAN_MOT_DISABLE    0 // Mailbox is disabled\r
+#define CAN_MOT_RECEPT     1 // Reception Mailbox\r
+#define CAN_MOT_RECEPT_OW  2 // Reception mailbox with overwrite\r
+#define CAN_MOT_TRANSMIT   3 // Transmit mailbox\r
+#define CAN_MOT_CONSUMER   4 // Consumer mailbox\r
+#define CAN_MOT_PRODUCER   5 // Producer mailbox\r
+\r
+//------------------------------------------------------------------------------\r
+//         Local variables\r
+//------------------------------------------------------------------------------\r
+#if defined (PINS_CAN_TRANSCEIVER_TXD)\r
+static const Pin pins_can_transceiver_txd[] = {PINS_CAN_TRANSCEIVER_TXD};\r
+#endif\r
+#if defined (PINS_CAN_TRANSCEIVER_RXD)\r
+static const Pin pins_can_transceiver_rxd[] = {PINS_CAN_TRANSCEIVER_RXD};\r
+#endif\r
+static const Pin pin_can_transceiver_rs   = PIN_CAN_TRANSCEIVER_RS;\r
+#if defined (PIN_CAN_TRANSCEIVER_RXEN)\r
+static const Pin pin_can_transceiver_rxen = PIN_CAN_TRANSCEIVER_RXEN;\r
+#endif\r
+\r
+static CanTransfer *pCAN0Transfer=NULL;\r
+#ifdef AT91C_BASE_CAN1\r
+static CanTransfer *pCAN1Transfer=NULL;\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+//         Local functions\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+/// CAN Error Detection\r
+/// \param status     error type\r
+/// \param can_number can nulber\r
+//------------------------------------------------------------------------------\r
+static void CAN_ErrorHandling( unsigned int status, unsigned char can_number)\r
+{\r
+    if( (status&AT91C_CAN_ERRA) ==  AT91C_CAN_ERRA) {\r
+        TRACE_ERROR("(CAN) CAN is in active Error Active mode\n\r");\r
+    }\r
+    else if( (status&AT91C_CAN_ERRP) ==  AT91C_CAN_ERRP) {\r
+        TRACE_ERROR("(CAN) CAN is in Error Passive mode\n\r");\r
+    }\r
+    else if( (status&AT91C_CAN_BOFF) ==  AT91C_CAN_BOFF) {\r
+        TRACE_ERROR("(CAN) CAN is in Buff Off mode\n\r");\r
+        // CAN reset\r
+        TRACE_ERROR("(CAN) CAN%d reset\n\r", can_number);\r
+        // CAN Controller Disable\r
+        if (can_number == 0) {\r
+            AT91C_BASE_CAN0->CAN_MR &= ~AT91C_CAN_CANEN;\r
+            // CAN Controller Enable\r
+            AT91C_BASE_CAN0->CAN_MR |= AT91C_CAN_CANEN;\r
+        }\r
+#ifdef AT91C_BASE_CAN1\r
+        else if (can_number == 1) {\r
+            AT91C_BASE_CAN1->CAN_MR &= ~AT91C_CAN_CANEN;\r
+            // CAN Controller Enable\r
+            AT91C_BASE_CAN1->CAN_MR |= AT91C_CAN_CANEN;\r
+        }\r
+#endif\r
+    }\r
+\r
+    // Error for Frame dataframe\r
+    // CRC error\r
+    if( (status&AT91C_CAN_CERR) ==  AT91C_CAN_CERR) {\r
+        TRACE_ERROR("(CAN) CRC Error\n\r");\r
+    }\r
+    // Bit-stuffing error\r
+    else if( (status&AT91C_CAN_SERR) ==  AT91C_CAN_SERR) {\r
+        TRACE_ERROR("(CAN) Stuffing Error\n\r");\r
+    }\r
+    // Bit error\r
+    else if( (status&AT91C_CAN_BERR) ==  AT91C_CAN_BERR) {\r
+        TRACE_ERROR("(CAN) Bit Error\n\r");\r
+    }\r
+    // Form error\r
+    else if( (status&AT91C_CAN_FERR) ==  AT91C_CAN_FERR) {\r
+        TRACE_ERROR("(CAN) Form Error\n\r");\r
+    }\r
+    // Acknowledgment error\r
+    else if( (status&AT91C_CAN_AERR) ==  AT91C_CAN_AERR) {\r
+        TRACE_ERROR("(CAN) Acknowledgment Error\n\r");\r
+    }\r
+\r
+    // Error interrupt handler\r
+    // Represent the current status of the CAN bus and are not latched.\r
+    // See CAN, par. Error Interrupt Handler\r
+    // AT91C_CAN_WARN\r
+    // AT91C_CAN_ERRA\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+// Generic CAN Interrupt handler\r
+/// \param can_number can nulber\r
+//------------------------------------------------------------------------------\r
+static void CAN_Handler( unsigned char can_number ) \r
+{\r
+    AT91PS_CAN base_can;\r
+    AT91PS_CAN_MB CAN_Mailbox;\r
+\r
+    unsigned int status;\r
+    unsigned int can_msr;\r
+    unsigned int* pCan_mcr;\r
+    unsigned int message_mode;\r
+    unsigned char numMailbox;\r
+    unsigned char state0=CAN_DISABLED;\r
+    unsigned char state1=CAN_DISABLED;\r
+\r
+    if( can_number == 0 ) {\r
+        base_can = AT91C_BASE_CAN0;\r
+        CAN_Mailbox = AT91C_BASE_CAN0_MB0;\r
+        state0 = pCAN0Transfer->state;\r
+    }\r
+#ifdef AT91C_BASE_CAN1\r
+    else {\r
+        base_can = AT91C_BASE_CAN1;\r
+        CAN_Mailbox = AT91C_BASE_CAN1_MB0;\r
+        state1 = pCAN1Transfer->state;\r
+    }\r
+#endif\r
+    status = (base_can->CAN_SR) & (base_can->CAN_IMR);\r
+    base_can->CAN_IDR = status;\r
+\r
+    TRACE_DEBUG("CAN0 status=0x%X\n\r", status);\r
+    if(status & AT91C_CAN_WAKEUP) {\r
+        if( can_number == 0 ) {\r
+            pCAN0Transfer->test_can = AT91C_TEST_OK;\r
+            pCAN0Transfer->state = CAN_IDLE;\r
+        }\r
+#ifdef AT91C_BASE_CAN1\r
+        else {\r
+            pCAN1Transfer->test_can = AT91C_TEST_OK;\r
+            pCAN1Transfer->state = CAN_IDLE;\r
+        }\r
+#endif\r
+    }\r
+    // Mailbox event ?\r
+    else if ((status&0x0000FFFF) != 0) {\r
+        TRACE_DEBUG("Mailbox event\n\r");\r
+\r
+        // Handle Mailbox interrupts\r
+        for (numMailbox = 0; numMailbox < NUM_MAILBOX_MAX; numMailbox++) {\r
+\r
+            can_msr = *(unsigned int*)((unsigned int)CAN_Mailbox+(unsigned int)(0x10+(0x20*numMailbox)));\r
+            if ((AT91C_CAN_MRDY & can_msr) == AT91C_CAN_MRDY) {\r
+                // Mailbox object type\r
+                message_mode =  ((*(unsigned int*)((unsigned int)CAN_Mailbox+(unsigned int)(0x00+(0x20*numMailbox))))>>24)&0x7;\r
+                TRACE_DEBUG("message_mode 0x%X\n\r", message_mode);\r
+                TRACE_DEBUG("numMailbox 0x%X\n\r", numMailbox);\r
+\r
+                if( message_mode == 0 ) {\r
+                    TRACE_ERROR("Error in MOT\n\r");\r
+                }\r
+                else if( ( message_mode == CAN_MOT_RECEPT ) \r
+                      || ( message_mode == CAN_MOT_RECEPT_OW ) \r
+                      || ( message_mode == CAN_MOT_PRODUCER ) ) {\r
+                    TRACE_DEBUG("Mailbox is in RECEPTION\n\r");\r
+                    TRACE_DEBUG("Length 0x%X\n\r", (can_msr>>16)&0xF);\r
+                    TRACE_DEBUG("CAN_MB_MID 0x%X\n\r", ((*(unsigned int*)((unsigned int)CAN_Mailbox+(unsigned int)(0x08+(0x20*numMailbox)))&AT91C_CAN_MIDvA)>>18));\r
+\r
+                    TRACE_DEBUG("can_number %d\n\r", can_number);\r
+                    if( can_number == 0 ) {\r
+                        //CAN_MB_MDLx\r
+                        pCAN0Transfer->data_low_reg = \r
+                           (*(unsigned int*)((unsigned int)CAN_Mailbox+(unsigned int)(0x14+(0x20*numMailbox))));\r
+                        //CAN_MB_MDHx\r
+                        pCAN0Transfer->data_high_reg = \r
+                           (*(unsigned int*)((unsigned int)CAN_Mailbox+(unsigned int)(0x18+(0x20*numMailbox))));\r
+                        pCAN0Transfer->size = (can_msr>>16)&0xF;\r
+                        pCAN0Transfer->mailbox_number = numMailbox;\r
+                        state0 = CAN_IDLE;\r
+                    }\r
+#ifdef AT91C_BASE_CAN1\r
+                    else {\r
+                        //CAN_MB_MDLx\r
+                        pCAN1Transfer->data_low_reg = \r
+                           (*(unsigned int*)((unsigned int)CAN_Mailbox+(unsigned int)(0x14+(0x20*numMailbox))));\r
+                        //CAN_MB_MDHx\r
+                        pCAN1Transfer->data_high_reg = \r
+                           (*(unsigned int*)((unsigned int)CAN_Mailbox+(unsigned int)(0x18+(0x20*numMailbox))));\r
+                        pCAN1Transfer->size = (can_msr>>16)&0xF;\r
+                        pCAN1Transfer->mailbox_number = numMailbox;\r
+                        state1 = CAN_IDLE;\r
+                    }\r
+#endif\r
+                    // Message Data has been received\r
+                    pCan_mcr = (unsigned int*)((unsigned int)CAN_Mailbox+0x1C+(0x20*numMailbox));\r
+                    *pCan_mcr = AT91C_CAN_MTCR;\r
+\r
+                }\r
+                else {\r
+                    TRACE_DEBUG("Mailbox is in TRANSMIT\n\r");\r
+                    TRACE_DEBUG("Length 0x%X\n\r", (can_msr>>16)&0xF);\r
+                    TRACE_DEBUG("can_number %d\n\r", can_number);\r
+                    if( can_number == 0 ) {\r
+                        state0 = CAN_IDLE;\r
+                    }\r
+                    else {\r
+                        state1 = CAN_IDLE;\r
+                    }\r
+                }\r
+            }\r
+        }\r
+        if( can_number == 0 ) {\r
+            pCAN0Transfer->state = state0;\r
+        }\r
+#ifdef AT91C_BASE_CAN1\r
+        else {\r
+            pCAN1Transfer->state = state1;\r
+        }\r
+#endif\r
+    }\r
+    if ((status&0xFFCF0000) != 0) {\r
+        CAN_ErrorHandling(status, 0);\r
+    }\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// CAN 0 Interrupt handler\r
+//------------------------------------------------------------------------------\r
+static void CAN0_Handler(void)\r
+{\r
+    CAN_Handler( 0 );\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// CAN 1 Interrupt handler\r
+//------------------------------------------------------------------------------\r
+#if defined AT91C_BASE_CAN1\r
+static void CAN1_Handler(void)\r
+{\r
+    CAN_Handler( 1 );\r
+}\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+//         Global functions\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+/// Configure the corresponding mailbox\r
+/// \param pTransfer can transfer structure\r
+//------------------------------------------------------------------------------\r
+void CAN_InitMailboxRegisters( CanTransfer *pTransfer )\r
+{\r
+    AT91PS_CAN    base_can;\r
+    AT91PS_CAN_MB CAN_Mailbox;\r
+\r
+    if( pTransfer->can_number == 0 ) {\r
+        base_can = AT91C_BASE_CAN0;\r
+        CAN_Mailbox = AT91C_BASE_CAN0_MB0;\r
+    }\r
+#ifdef AT91C_BASE_CAN1\r
+    else {\r
+        base_can = AT91C_BASE_CAN1;\r
+        CAN_Mailbox = AT91C_BASE_CAN1_MB0;\r
+    }\r
+#endif\r
+    CAN_Mailbox = (AT91PS_CAN_MB)((unsigned int)CAN_Mailbox+(unsigned int)(0x20*pTransfer->mailbox_number));\r
+\r
+    pTransfer->mailbox_in_use |= 1<<(pTransfer->mailbox_number);\r
+    // MailBox Control Register\r
+    CAN_Mailbox->CAN_MB_MCR = 0x0;\r
+    // MailBox Mode Register\r
+    CAN_Mailbox->CAN_MB_MMR = 0x00;\r
+    // CAN Message Acceptance Mask Register\r
+    CAN_Mailbox->CAN_MB_MAM = pTransfer->acceptance_mask_reg;\r
+    // MailBox ID Register\r
+    // Disable the mailbox before writing to CAN_MIDx registers\r
+    if( (pTransfer->identifier & AT91C_CAN_MIDE) == AT91C_CAN_MIDE ) {\r
+        // Extended\r
+        CAN_Mailbox->CAN_MB_MAM |= AT91C_CAN_MIDE;\r
+    }\r
+    else {\r
+        CAN_Mailbox->CAN_MB_MAM &= ~AT91C_CAN_MIDE;\r
+    }\r
+    CAN_Mailbox->CAN_MB_MID = pTransfer->identifier;\r
+\r
+    // MailBox Mode Register\r
+    CAN_Mailbox->CAN_MB_MMR = pTransfer->mode_reg;\r
+    // MailBox Data Low Register\r
+    CAN_Mailbox->CAN_MB_MDL = pTransfer->data_low_reg;\r
+    // MailBox Data High Register\r
+    CAN_Mailbox->CAN_MB_MDH = pTransfer->data_high_reg;\r
+    // MailBox Control Register\r
+    CAN_Mailbox->CAN_MB_MCR = pTransfer->control_reg;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Reset the MBx\r
+//------------------------------------------------------------------------------\r
+void CAN_ResetAllMailbox( void )\r
+{\r
+    unsigned char i;\r
+  \r
+#if defined (AT91C_BASE_CAN0_MB0)\r
+    CAN_ResetTransfer( pCAN0Transfer );\r
+    for( i=0; i<8; i++ ) {\r
+        pCAN0Transfer->can_number = 0;\r
+        pCAN0Transfer->mailbox_number = i;\r
+        pCAN0Transfer->mode_reg = AT91C_CAN_MOT_DIS;\r
+        pCAN0Transfer->acceptance_mask_reg = 0;\r
+        pCAN0Transfer->identifier = 0;\r
+        pCAN0Transfer->data_low_reg = 0x00000000;\r
+        pCAN0Transfer->data_high_reg = 0x00000000;\r
+        pCAN0Transfer->control_reg = 0x00000000;\r
+        CAN_InitMailboxRegisters( pCAN0Transfer );\r
+    }\r
+#endif\r
+#if defined (AT91C_BASE_CAN0_MB8)\r
+    for( i=0; i<8; i++ ) {\r
+        pCAN0Transfer->can_number = 0;\r
+        pCAN0Transfer->mailbox_number = i+8;\r
+        pCAN0Transfer->mode_reg = AT91C_CAN_MOT_DIS;\r
+        pCAN0Transfer->acceptance_mask_reg = 0;\r
+        pCAN0Transfer->identifier = 0;\r
+        pCAN0Transfer->data_low_reg = 0x00000000;\r
+        pCAN0Transfer->data_high_reg = 0x00000000;\r
+        pCAN0Transfer->control_reg = 0x00000000;\r
+        CAN_InitMailboxRegisters( pCAN0Transfer );\r
+    }\r
+#endif\r
+\r
+#if defined (AT91C_BASE_CAN1_MB0)\r
+    if( pCAN1Transfer != NULL ) {\r
+        CAN_ResetTransfer( pCAN1Transfer );\r
+        for( i=0; i<8; i++ ) {\r
+            pCAN1Transfer->can_number = 1;\r
+            pCAN1Transfer->mailbox_number = i;\r
+            pCAN1Transfer->mode_reg = AT91C_CAN_MOT_DIS;\r
+            pCAN1Transfer->acceptance_mask_reg = 0;\r
+            pCAN1Transfer->identifier = 0;\r
+            pCAN1Transfer->data_low_reg = 0x00000000;\r
+            pCAN1Transfer->data_high_reg = 0x00000000;\r
+            pCAN1Transfer->control_reg = 0x00000000;\r
+            CAN_InitMailboxRegisters( pCAN1Transfer );\r
+        }\r
+    }\r
+#endif\r
+#if defined (AT91C_BASE_CAN1_MB8)\r
+    if( pCAN1Transfer != NULL ) {\r
+        for( i=0; i<8; i++ ) {\r
+            pCAN1Transfer->can_number = 1;\r
+            pCAN1Transfer->mailbox_number = i+8;\r
+            pCAN1Transfer->mode_reg = AT91C_CAN_MOT_DIS;\r
+            pCAN1Transfer->acceptance_mask_reg = 0;\r
+            pCAN1Transfer->identifier = 0;\r
+            pCAN1Transfer->data_low_reg = 0x00000000;\r
+            pCAN1Transfer->data_high_reg = 0x00000000;\r
+            pCAN1Transfer->control_reg = 0x00000000;\r
+            CAN_InitMailboxRegisters( pCAN1Transfer );\r
+        }\r
+    }\r
+#endif\r
+\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// CAN reset Transfer descriptor\r
+/// \param pTransfer can transfer structure\r
+//------------------------------------------------------------------------------\r
+void CAN_ResetTransfer( CanTransfer *pTransfer )\r
+{\r
+    pTransfer->state = CAN_IDLE;\r
+    pTransfer->can_number = 0;\r
+    pTransfer->mailbox_number = 0;\r
+    pTransfer->test_can = 0;\r
+    pTransfer->mode_reg = 0;\r
+    pTransfer->acceptance_mask_reg = 0;\r
+    pTransfer->identifier = 0;\r
+    pTransfer->data_low_reg = 0;\r
+    pTransfer->data_high_reg = 0;\r
+    pTransfer->control_reg = 0;\r
+    pTransfer->mailbox_in_use = 0;\r
+    pTransfer->size = 0;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Wait for CAN synchronisation\r
+/// \return return 1 for good initialisation, otherwise return 0\r
+//------------------------------------------------------------------------------\r
+static unsigned char CAN_Synchronisation( void )\r
+{\r
+    unsigned int tick=0;\r
+\r
+    TRACE_INFO("CAN_Synchronisation\n\r");\r
+\r
+    pCAN0Transfer->test_can = AT91C_TEST_NOK;\r
+#ifdef AT91C_BASE_CAN1\r
+    if( pCAN1Transfer != NULL ) {\r
+        pCAN1Transfer->test_can = AT91C_TEST_NOK;\r
+    }\r
+#endif\r
+    // Enable CAN and Wait for WakeUp Interrupt\r
+    AT91C_BASE_CAN0->CAN_IER = AT91C_CAN_WAKEUP;\r
+    // CAN Controller Enable\r
+    AT91C_BASE_CAN0->CAN_MR = AT91C_CAN_CANEN;\r
+    // Enable Autobaud/Listen mode\r
+    // dangerous, CAN not answer in this mode\r
+\r
+     while( (pCAN0Transfer->test_can != AT91C_TEST_OK)\r
+         && (tick < AT91C_CAN_TIMEOUT) ) {\r
+        tick++;\r
+    }\r
+    if (tick == AT91C_CAN_TIMEOUT) {\r
+        TRACE_ERROR("CAN0 Initialisations FAILED\n\r");\r
+        return 0;\r
+    } else {\r
+        TRACE_INFO("CAN0 Initialisations Completed\n\r");\r
+    }\r
+\r
+#if defined AT91C_BASE_CAN1\r
+    if( pCAN1Transfer != NULL ) {\r
+        AT91C_BASE_CAN1->CAN_IER = AT91C_CAN_WAKEUP;\r
+        // CAN Controller Enable\r
+        AT91C_BASE_CAN1->CAN_MR = AT91C_CAN_CANEN;\r
+\r
+        tick = 0;\r
+        // Wait for WAKEUP flag raising <=> 11-recessive-bit were scanned by the transceiver\r
+        while( ((pCAN1Transfer->test_can != AT91C_TEST_OK)) \r
+            && (tick < AT91C_CAN_TIMEOUT) ) {\r
+            tick++;\r
+        }\r
+\r
+        if (tick == AT91C_CAN_TIMEOUT) {\r
+            TRACE_ERROR("CAN1 Initialisations FAILED\n\r");\r
+            return 0;\r
+        } else {\r
+            TRACE_INFO("CAN1 Initialisations Completed\n\r");\r
+        }\r
+    }\r
+#endif\r
+    return 1;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Write a CAN transfer\r
+/// \param pTransfer can transfer structure\r
+/// \return return CAN_STATUS_SUCCESS if command passed, otherwise \r
+///         return CAN_STATUS_LOCKED\r
+//------------------------------------------------------------------------------\r
+unsigned char CAN_Write( CanTransfer *pTransfer )\r
+{\r
+    AT91PS_CAN base_can;\r
+\r
+    if (pTransfer->state == CAN_RECEIVING)  {\r
+        pTransfer->state = CAN_IDLE;\r
+    }\r
+\r
+    if (pTransfer->state != CAN_IDLE)  {\r
+        return CAN_STATUS_LOCKED;\r
+    }\r
+\r
+    TRACE_DEBUG("CAN_Write\n\r");\r
+    pTransfer->state = CAN_SENDING;\r
+    if( pTransfer->can_number == 0 ) {\r
+        base_can = AT91C_BASE_CAN0;\r
+    }\r
+#ifdef AT91C_BASE_CAN1\r
+    else {\r
+        base_can = AT91C_BASE_CAN1;\r
+    }\r
+#endif\r
+    base_can->CAN_TCR = pTransfer->mailbox_in_use;\r
+    base_can->CAN_IER = pTransfer->mailbox_in_use;\r
+\r
+    return CAN_STATUS_SUCCESS;\r
+\r
+}\r
+\r
+\r
+//------------------------------------------------------------------------------\r
+/// Read a CAN transfer\r
+/// \param pTransfer can transfer structure\r
+/// \return return CAN_STATUS_SUCCESS if command passed, otherwise \r
+///         return CAN_STATUS_LOCKED\r
+//------------------------------------------------------------------------------\r
+unsigned char CAN_Read( CanTransfer *pTransfer )\r
+{\r
+    AT91PS_CAN base_can;\r
+\r
+    if (pTransfer->state != CAN_IDLE)  {\r
+        return CAN_STATUS_LOCKED;\r
+    }\r
+\r
+    TRACE_DEBUG("CAN_Read\n\r");\r
+    pTransfer->state = CAN_RECEIVING;\r
+\r
+\r
+    if( pTransfer->can_number == 0 ) {\r
+        base_can = AT91C_BASE_CAN0;\r
+    }\r
+#ifdef AT91C_BASE_CAN1\r
+    else {\r
+        base_can = AT91C_BASE_CAN1;\r
+    }\r
+#endif\r
+    // enable interrupt\r
+    base_can->CAN_IER = pTransfer->mailbox_in_use;\r
+\r
+    return CAN_STATUS_SUCCESS;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Test if CAN is in IDLE state\r
+/// \param pTransfer can transfer structure\r
+/// \return return 0 if CAN is in IDLE, otherwise return 1\r
+//------------------------------------------------------------------------------\r
+unsigned char CAN_IsInIdle( CanTransfer *pTransfer )\r
+{\r
+  return( pTransfer->state != CAN_IDLE );\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Basic CAN test without Interrupt\r
+//------------------------------------------------------------------------------\r
+void CAN_BasicTestSuiteWithoutInterrupt(void)\r
+{\r
+#if defined AT91C_BASE_CAN1\r
+    unsigned int status;\r
+    unsigned int tick=0;\r
+\r
+    TRACE_INFO("Without Interrupt ");\r
+    TRACE_INFO("CAN0 Mailbox 0 transmitting to CAN1 Mailbox 0\n\r");\r
+    // Init CAN0 Mailbox 0, transmit\r
+    CAN_ResetTransfer( pCAN0Transfer );\r
+    pCAN0Transfer->can_number = 0;\r
+    pCAN0Transfer->mailbox_number = 0;\r
+    pCAN0Transfer->mode_reg = AT91C_CAN_MOT_TX | AT91C_CAN_PRIOR;\r
+    pCAN0Transfer->acceptance_mask_reg = 0x00000000;\r
+    pCAN0Transfer->identifier = AT91C_CAN_MIDvA & (0x07<<18);\r
+    pCAN0Transfer->data_low_reg = 0x11223344;\r
+    pCAN0Transfer->data_high_reg = 0x01234567;\r
+    pCAN0Transfer->control_reg = (AT91C_CAN_MDLC & (0x8<<16));\r
+    CAN_InitMailboxRegisters( pCAN0Transfer );\r
+\r
+    // Init CAN1 Mailbox 0, receive, \r
+    CAN_ResetTransfer( pCAN1Transfer );\r
+    pCAN1Transfer->can_number = 1;\r
+    pCAN1Transfer->mailbox_number = 0;\r
+    pCAN1Transfer->mode_reg = AT91C_CAN_MOT_RX;\r
+    pCAN1Transfer->acceptance_mask_reg = AT91C_CAN_MIDvA | AT91C_CAN_MIDvB;\r
+    pCAN1Transfer->identifier = AT91C_CAN_MIDvA & (0x07<<18);\r
+    pCAN1Transfer->data_low_reg = 0x00000000;\r
+    pCAN1Transfer->data_high_reg = 0x00000000;\r
+    pCAN1Transfer->control_reg = 0x00000000;\r
+    CAN_InitMailboxRegisters( pCAN1Transfer );\r
+\r
+    // Transfer Request for Mailbox 0\r
+    AT91C_BASE_CAN0->CAN_TCR = AT91C_CAN_MB0;\r
+\r
+    tick = 0;\r
+    do {\r
+        // CAN Message Status Register\r
+        status = AT91C_BASE_CAN0_MB0->CAN_MB_MSR;\r
+    }\r
+    while( !(status & AT91C_CAN_MRDY) && (++tick < AT91C_CAN_TIMEOUT) );\r
+\r
+    if (tick == AT91C_CAN_TIMEOUT) {\r
+        TRACE_ERROR("Test FAILED\n\r");\r
+    } \r
+    else {\r
+        TRACE_DEBUG("Transfer completed: CAN1 Mailbox 0 MRDY flag has raised\n\r");\r
+        if( AT91C_BASE_CAN0_MB0->CAN_MB_MDL != AT91C_BASE_CAN1_MB0->CAN_MB_MDL ) {\r
+            TRACE_ERROR("Data Corrupted\n\r");\r
+        }\r
+        else if( AT91C_BASE_CAN0_MB0->CAN_MB_MDH != AT91C_BASE_CAN1_MB0->CAN_MB_MDH ) {\r
+            TRACE_ERROR("Data Corrupted\n\r");\r
+        }\r
+        else {\r
+            TRACE_INFO("Test passed\n\r");\r
+        }\r
+    }\r
+\r
+    CAN_ResetAllMailbox();\r
+\r
+    TRACE_INFO("Without Interrupt ");\r
+    TRACE_INFO("CAN0 Mailboxes 1 & 2 transmitting to CAN1 Mailbox 15\n\r");\r
+    // Init CAN0 Mailbox 1, transmit\r
+    CAN_ResetTransfer( pCAN0Transfer );\r
+    pCAN0Transfer->can_number = 0;\r
+    pCAN0Transfer->mailbox_number = 1;\r
+    pCAN0Transfer->mode_reg = AT91C_CAN_MOT_TX | AT91C_CAN_PRIOR;\r
+    pCAN0Transfer->acceptance_mask_reg = 0x00000000;\r
+    pCAN0Transfer->identifier = AT91C_CAN_MIDvA & (0x09<<18);      // ID 9\r
+    pCAN0Transfer->data_low_reg = 0xAABBCCDD;\r
+    pCAN0Transfer->data_high_reg = 0xCAFEDECA;\r
+    pCAN0Transfer->control_reg = (AT91C_CAN_MDLC & (0x8<<16)); // Mailbox Data Length Code\r
+    CAN_InitMailboxRegisters( pCAN0Transfer );\r
+\r
+    // Init CAN0 Mailbox 2, transmit\r
+    pCAN0Transfer->can_number = 0;\r
+    pCAN0Transfer->mailbox_number = 2;\r
+    pCAN0Transfer->mode_reg = AT91C_CAN_MOT_TX | (AT91C_CAN_PRIOR-(1<<16));\r
+    pCAN0Transfer->acceptance_mask_reg = 0x00000000;\r
+    pCAN0Transfer->identifier = AT91C_CAN_MIDvA & (0x0A<<18);      // ID 10\r
+    pCAN0Transfer->data_low_reg = 0x55667788;\r
+    pCAN0Transfer->data_high_reg = 0x99AABBCC;\r
+    pCAN0Transfer->control_reg = (AT91C_CAN_MDLC & (0x8<<16)); // Mailbox Data Length Code\r
+    CAN_InitMailboxRegisters( pCAN0Transfer );\r
+\r
+    // Init CAN1 Mailbox 15, reception with overwrite\r
+    CAN_ResetTransfer( pCAN1Transfer );\r
+    pCAN1Transfer->can_number = 1;\r
+    pCAN1Transfer->mailbox_number = 15;\r
+    pCAN1Transfer->mode_reg = AT91C_CAN_MOT_RXOVERWRITE;\r
+    pCAN1Transfer->acceptance_mask_reg = 0;\r
+    pCAN1Transfer->identifier = 0x0;\r
+    pCAN1Transfer->data_low_reg = 0x00000000;\r
+    pCAN1Transfer->data_high_reg = 0x00000000;\r
+    pCAN1Transfer->control_reg = 0x00000000;\r
+    CAN_InitMailboxRegisters( pCAN1Transfer );\r
+\r
+    // Ask Transmissions on Mailbox 1 & 2 --> AT91C_CAN_MRDY & AT91C_CAN_MMI raises for Mailbox 15 CAN_MB_SR\r
+    AT91C_BASE_CAN0->CAN_TCR = AT91C_CAN_MB1 | AT91C_CAN_MB2;\r
+    \r
+    // Wait for Last Transmit Mailbox\r
+    tick = 0;\r
+    do  {\r
+        status = AT91C_BASE_CAN1_MB15->CAN_MB_MSR;\r
+    }\r
+    while( !(status & AT91C_CAN_MMI) && (++tick < AT91C_CAN_TIMEOUT) );\r
+\r
+    if (tick == AT91C_CAN_TIMEOUT) {\r
+    }\r
+    else {\r
+        TRACE_DEBUG("Transfer completed: CAN1 Mailbox 15 MRDY and MMI flags have raised\n\r");\r
+        if( AT91C_BASE_CAN0_MB1->CAN_MB_MDL != AT91C_BASE_CAN1_MB15->CAN_MB_MDL ) {\r
+            TRACE_ERROR("Data Corrupted\n\r");\r
+        }\r
+        else if( AT91C_BASE_CAN0_MB1->CAN_MB_MDH != AT91C_BASE_CAN1_MB15->CAN_MB_MDH ) {\r
+            TRACE_ERROR("Data Corrupted\n\r");\r
+        }\r
+        else {\r
+            TRACE_INFO("Test passed\n\r");\r
+        }\r
+    }\r
+\r
+    CAN_ResetAllMailbox();\r
+    TRACE_INFO("Without Interrupt ");\r
+    TRACE_INFO("CAN0 Mailboxes 1 & 2 transmitting to CAN1 Mailbox 15\n\r");\r
+    // Init CAN0 Mailbox 1, transmit\r
+    CAN_ResetTransfer( pCAN0Transfer );\r
+    pCAN0Transfer->can_number = 0;\r
+    pCAN0Transfer->mailbox_number = 1;\r
+    pCAN0Transfer->mode_reg = AT91C_CAN_MOT_TX | AT91C_CAN_PRIOR;\r
+    pCAN0Transfer->acceptance_mask_reg = 0x00000000;\r
+    pCAN0Transfer->identifier = AT91C_CAN_MIDvA & (0x09<<18);      // ID 9\r
+    pCAN0Transfer->data_low_reg = 0xAABBCCDD;\r
+    pCAN0Transfer->data_high_reg = 0xCAFEDECA;\r
+    pCAN0Transfer->control_reg = (AT91C_CAN_MDLC & (0x8<<16)); // Mailbox Data Length Code\r
+    CAN_InitMailboxRegisters( pCAN0Transfer );\r
+\r
+    // Init CAN0 Mailbox 2, transmit\r
+    pCAN0Transfer->can_number = 0;\r
+    pCAN0Transfer->mailbox_number = 2;\r
+    pCAN0Transfer->mode_reg = AT91C_CAN_MOT_TX | (AT91C_CAN_PRIOR-(1<<16));\r
+    pCAN0Transfer->acceptance_mask_reg = 0x00000000;\r
+    pCAN0Transfer->identifier = AT91C_CAN_MIDvA & (0x0A<<18);      // ID 10\r
+    pCAN0Transfer->data_low_reg = 0x55667788;\r
+    pCAN0Transfer->data_high_reg = 0x99AABBCC;\r
+    pCAN0Transfer->control_reg = (AT91C_CAN_MDLC & (0x8<<16)); // Mailbox Data Length Code\r
+    CAN_InitMailboxRegisters( pCAN0Transfer );\r
+\r
+    // Init CAN1 Mailbox 15, reception with overwrite\r
+    CAN_ResetTransfer( pCAN1Transfer );\r
+    pCAN1Transfer->can_number = 1;\r
+    pCAN1Transfer->mailbox_number = 15;\r
+    pCAN1Transfer->mode_reg = AT91C_CAN_MOT_RX;\r
+    pCAN1Transfer->acceptance_mask_reg = 0;\r
+    pCAN1Transfer->identifier = 0x0;\r
+    pCAN1Transfer->data_low_reg = 0x00000000;\r
+    pCAN1Transfer->data_high_reg = 0x00000000;\r
+    pCAN1Transfer->control_reg = 0x00000000;\r
+    CAN_InitMailboxRegisters( pCAN1Transfer );\r
+\r
+    // Ask Transmissions on Mailbox 1 & 2 --> AT91C_CAN_MRDY & AT91C_CAN_MMI raises for Mailbox 15 CAN_MB_SR\r
+    AT91C_BASE_CAN0->CAN_TCR = AT91C_CAN_MB1 | AT91C_CAN_MB2;\r
+    \r
+    // Wait for Last Transmit Mailbox\r
+    tick = 0;\r
+    do  {\r
+        status = AT91C_BASE_CAN1_MB15->CAN_MB_MSR;\r
+    }\r
+    while( !(status & AT91C_CAN_MMI) && (++tick < AT91C_CAN_TIMEOUT) );\r
+\r
+    if (tick == AT91C_CAN_TIMEOUT) {\r
+    TRACE_ERROR("Test FAILED\n\r");\r
+    }\r
+    else {\r
+        TRACE_DEBUG("Transfer completed: CAN1 Mailbox 15 MRDY and MMI flags have raised\n\r");\r
+        TRACE_DEBUG("MB_MDL: 0x%X\n\r", AT91C_BASE_CAN1_MB15->CAN_MB_MDL);\r
+        TRACE_DEBUG("MB_MDLH: 0x%X\n\r", AT91C_BASE_CAN1_MB15->CAN_MB_MDH);\r
+        if( AT91C_BASE_CAN0_MB2->CAN_MB_MDL != AT91C_BASE_CAN1_MB15->CAN_MB_MDL ) {\r
+            TRACE_ERROR("Data Corrupted\n\r");\r
+        }\r
+        else if( AT91C_BASE_CAN0_MB2->CAN_MB_MDH != AT91C_BASE_CAN1_MB15->CAN_MB_MDH ) {\r
+            TRACE_ERROR("Data Corrupted\n\r");\r
+        }\r
+        else {\r
+            TRACE_INFO("Test passed\n\r");\r
+        }\r
+    }\r
+\r
+    CAN_ResetAllMailbox();\r
+    TRACE_INFO("Without Interrupt ");\r
+    TRACE_INFO("CAN0 Mailbox 3 asking for CAN1 Mailbox 3 transmission\n\r");\r
+    // Init CAN0 Mailbox 3, consumer mailbox\r
+    // Sends a remote frame and waits for an answer\r
+    CAN_ResetTransfer( pCAN0Transfer );\r
+    pCAN0Transfer->can_number = 0;\r
+    pCAN0Transfer->mailbox_number = 3;\r
+    pCAN0Transfer->mode_reg = AT91C_CAN_MOT_CONSUMER | AT91C_CAN_PRIOR;\r
+    pCAN0Transfer->acceptance_mask_reg = AT91C_CAN_MIDvA | AT91C_CAN_MIDvB;\r
+    pCAN0Transfer->identifier = AT91C_CAN_MIDvA & (0x0B<<18);     // ID 11\r
+    pCAN0Transfer->data_low_reg = 0x00000000;\r
+    pCAN0Transfer->data_high_reg = 0x00000000;\r
+    pCAN0Transfer->control_reg = 0x00000000;\r
+    CAN_InitMailboxRegisters( pCAN0Transfer );\r
+\r
+    // Init CAN1 Mailbox 3, porducer mailbox\r
+    // Waits to receive a Remote Frame before sending its contents\r
+    CAN_ResetTransfer( pCAN1Transfer );\r
+    pCAN1Transfer->can_number = 1;\r
+    pCAN1Transfer->mailbox_number = 3;\r
+    pCAN1Transfer->mode_reg = AT91C_CAN_MOT_PRODUCER | AT91C_CAN_PRIOR;\r
+    pCAN1Transfer->acceptance_mask_reg = 0;\r
+    pCAN1Transfer->identifier = AT91C_CAN_MIDvA & (0x0B<<18);     // ID 11\r
+    pCAN1Transfer->data_low_reg = 0xEEDDFF00;\r
+    pCAN1Transfer->data_high_reg = 0x34560022;\r
+    pCAN1Transfer->control_reg = (AT91C_CAN_MDLC & (0x8<<16));\r
+    CAN_InitMailboxRegisters( pCAN1Transfer );\r
+\r
+    // Ask Transmissions on Mailbox 3 --> AT91C_CAN_MRDY raises for Mailbox 3 CAN_MB_SR\r
+    AT91C_BASE_CAN1->CAN_TCR = AT91C_CAN_MB3;\r
+    AT91C_BASE_CAN0->CAN_TCR = AT91C_CAN_MB3;\r
+\r
+    // Wait for Last Transmit Mailbox\r
+    tick = 0;\r
+    do  {\r
+        status = AT91C_BASE_CAN0_MB3->CAN_MB_MSR;\r
+    }\r
+    while( !(status & AT91C_CAN_MRDY) && (++tick < AT91C_CAN_TIMEOUT) );\r
+\r
+    if (tick == AT91C_CAN_TIMEOUT) {\r
+        TRACE_ERROR("Test FAILED\n\r");\r
+    }\r
+    else {\r
+        TRACE_DEBUG("Transfer Completed: CAN0 & CAN1 Mailboxes 3 MRDY flags have raised\n\r");\r
+        if( AT91C_BASE_CAN0_MB3->CAN_MB_MDL != AT91C_BASE_CAN1_MB3->CAN_MB_MDL ) {\r
+            TRACE_ERROR("Data Corrupted\n\r");\r
+        }\r
+        else if( AT91C_BASE_CAN0_MB3->CAN_MB_MDH != AT91C_BASE_CAN1_MB3->CAN_MB_MDH ) {\r
+            TRACE_ERROR("Data Corrupted\n\r");\r
+        }\r
+        else {\r
+            TRACE_INFO("Test passed\n\r");\r
+        }\r
+    }\r
+#endif // AT91C_BASE_CAN1\r
+\r
+  return;\r
+}\r
+\r
+\r
+//------------------------------------------------------------------------------\r
+/// Disable CAN and enter in low power\r
+//------------------------------------------------------------------------------\r
+void CAN_disable( void )\r
+{\r
+    // Disable the interrupt on the interrupt controller\r
+    AIC_DisableIT(AT91C_ID_CAN0);\r
+    // disable all IT\r
+    AT91C_BASE_CAN0->CAN_IDR = 0x1FFFFFFF;\r
+#if defined AT91C_BASE_CAN1\r
+    AIC_DisableIT(AT91C_ID_CAN1);\r
+    // disable all IT\r
+    AT91C_BASE_CAN1->CAN_IDR = 0x1FFFFFFF;\r
+#endif\r
+\r
+    // Enable Low Power mode\r
+    AT91C_BASE_CAN0->CAN_MR |= AT91C_CAN_LPM;\r
+\r
+    // Disable CANs Transceivers\r
+    // Enter standby mode\r
+    PIO_Set(&pin_can_transceiver_rs);\r
+#if defined (PIN_CAN_TRANSCEIVER_RXEN)\r
+    // Enable ultra Low Power mode\r
+    PIO_Clear(&pin_can_transceiver_rxen);\r
+#endif\r
+\r
+    // Disable clock for CAN PIO\r
+#if defined(AT91C_ID_PIOA)    \r
+    AT91C_BASE_PMC->PMC_PCDR = (1 << AT91C_ID_PIOA);\r
+#elif defined(AT91C_ID_PIOABCD)\r
+    AT91C_BASE_PMC->PMC_PCDR = (1 << AT91C_ID_PIOABCD);\r
+#elif defined(AT91C_ID_PIOABCDE)\r
+    AT91C_BASE_PMC->PMC_PCDR = (1 << AT91C_ID_PIOABCDE);\r
+#endif\r
+    \r
+    // Disable the CAN0 controller peripheral clock\r
+    AT91C_BASE_PMC->PMC_PCDR = (1 << AT91C_ID_CAN0);\r
+\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// baudrate calcul\r
+/// \param base_CAN CAN base address\r
+/// \param baudrate Baudrate value (kB/s)\r
+///                 allowed values: 1000, 800, 500, 250, 125, 50, 25, 10\r
+/// \return return 1 in success, otherwise return 0\r
+//------------------------------------------------------------------------------\r
+unsigned char CAN_BaudRateCalculate( AT91PS_CAN   base_CAN, \r
+                                     unsigned int baudrate )\r
+{\r
+    unsigned int BRP;\r
+    unsigned int PROPAG;\r
+    unsigned int PHASE1;\r
+    unsigned int PHASE2;\r
+    unsigned int SJW;\r
+    unsigned int t1t2;\r
+    unsigned char TimeQuanta;\r
+\r
+    base_CAN->CAN_BR = 0;\r
+\r
+    if( baudrate == 1000) {\r
+        TimeQuanta = 8;\r
+    }\r
+    else {\r
+        TimeQuanta = 16;\r
+    }\r
+\r
+    BRP = (BOARD_MCK / (baudrate*1000*TimeQuanta))-1;\r
+    //TRACE_DEBUG("BRP = 0x%X\n\r", BRP);\r
+    // timing Delay:\r
+    // Delay Bus Driver: 50 ns\r
+    // Delay Receiver:   30 ns\r
+    // Delay Bus Line (20m):  110 ns\r
+    if( (TimeQuanta*baudrate*2*(50+30+110)/1000000) >= 1) {\r
+        PROPAG = (TimeQuanta*baudrate*2*(50+30+110)/1000000)-1;\r
+    }\r
+    else {\r
+        PROPAG = 0;\r
+    }\r
+    //TRACE_DEBUG("PROPAG = 0x%X\n\r", PROPAG);\r
+\r
+    t1t2 = TimeQuanta-1-(PROPAG+1);\r
+    //TRACE_DEBUG("t1t2 = 0x%X\n\r", t1t2);\r
+\r
+    if( (t1t2 & 0x01) == 0x01 ) {\r
+        // ODD\r
+        //TRACE_DEBUG("ODD\n\r");\r
+        PHASE1 = ((t1t2-1)/2)-1;\r
+        PHASE2 = PHASE1+1;\r
+    }\r
+    else {\r
+        // EVEN\r
+        //TRACE_DEBUG("EVEN\n\r");\r
+        PHASE1 = (t1t2/2)-1;\r
+        PHASE2 = PHASE1;\r
+    }\r
+    //TRACE_DEBUG("PHASE1 = 0x%X\n\r", PHASE1);\r
+    //TRACE_DEBUG("PHASE2 = 0x%X\n\r", PHASE2);\r
+\r
+    if( 1 > (4/(PHASE1+1)) ) {\r
+        //TRACE_DEBUG("4*Tcsc\n\r");\r
+        SJW = 3;\r
+    }\r
+    else {\r
+        //TRACE_DEBUG("Tphs1\n\r");\r
+        SJW = PHASE1;\r
+    }\r
+    //TRACE_DEBUG("SJW = 0x%X\n\r", SJW);\r
+    // Verif\r
+    if( BRP == 0 ) {\r
+        TRACE_DEBUG("BRP = 0 is not authorized\n\r");\r
+        return 0;\r
+    }\r
+\r
+    if( (PROPAG + PHASE1 + PHASE2) != (TimeQuanta-4) ) {\r
+        TRACE_DEBUG("Pb (PROPAG + PHASE1 + PHASE2) = %d\n\r", PROPAG + PHASE1 + PHASE2);\r
+        TRACE_DEBUG("with TimeQuanta-4 = %d\n\r", TimeQuanta-4);\r
+        return 0;\r
+    }\r
+    base_CAN->CAN_BR = (AT91C_CAN_PHASE2 & (PHASE2 <<  0))\r
+                     + (AT91C_CAN_PHASE1 & (PHASE1 <<  4))\r
+                     + (AT91C_CAN_PROPAG & (PROPAG <<  8))\r
+                     + (AT91C_CAN_SYNC   & (SJW << 12))\r
+                     + (AT91C_CAN_BRP    & (BRP << 16))\r
+                     + (AT91C_CAN_SMP    & (0 << 24));\r
+    return 1;\r
+\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+//------------------------------------------------------------------------------\r
+//------------------------------------------------------------------------------\r
+/// Init of the CAN peripheral\r
+/// \param baudrate Baudrate value (kB/s)\r
+///                 allowed values: 1000, 800, 500, 250, 125, 50, 25, 10\r
+/// \param canTransfer0 CAN0 structure transfer\r
+/// \param canTransfer1 CAN1 structure transfer\r
+/// \return return 1 if CAN has good baudrate and CAN is synchronized, \r
+///         otherwise return 0\r
+//------------------------------------------------------------------------------\r
+unsigned char CAN_Init( unsigned int baudrate, \r
+                        CanTransfer *canTransfer0, \r
+                        CanTransfer *canTransfer1 ) \r
+{\r
+    unsigned char ret;\r
+\r
+    // CAN Transmit Serial Data\r
+#if defined (PINS_CAN_TRANSCEIVER_TXD)\r
+    PIO_Configure(pins_can_transceiver_txd, PIO_LISTSIZE(pins_can_transceiver_txd));\r
+#endif\r
+#if defined (PINS_CAN_TRANSCEIVER_RXD)\r
+    // CAN Receive Serial Data\r
+    PIO_Configure(pins_can_transceiver_rxd, PIO_LISTSIZE(pins_can_transceiver_rxd));\r
+#endif\r
+    // CAN RS\r
+    PIO_Configure(&pin_can_transceiver_rs, PIO_LISTSIZE(pin_can_transceiver_rs));\r
+#if defined (PIN_CAN_TRANSCEIVER_RXEN)\r
+    // CAN RXEN\r
+    PIO_Configure(&pin_can_transceiver_rxen, PIO_LISTSIZE(pin_can_transceiver_rxen));\r
+#endif\r
+\r
+    // Enable clock for CAN PIO\r
+#if defined(AT91C_ID_PIOA)    \r
+    AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_PIOA);\r
+#elif defined(AT91C_ID_PIOABCD)\r
+    AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_PIOABCD);\r
+#elif defined(AT91C_ID_PIOABCDE)\r
+    AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_PIOABCDE);\r
+#endif\r
+\r
+    // Enable the CAN0 controller peripheral clock\r
+    AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_CAN0);\r
+\r
+    // disable all IT\r
+    AT91C_BASE_CAN0->CAN_IDR = 0x1FFFFFFF;\r
+\r
+    // Enable CANs Transceivers\r
+#if defined (PIN_CAN_TRANSCEIVER_RXEN)\r
+    // Disable ultra Low Power mode\r
+    PIO_Set(&pin_can_transceiver_rxen);\r
+#endif\r
+    // Normal Mode (versus Standby mode)\r
+    PIO_Clear(&pin_can_transceiver_rs);\r
+\r
+    // Configure the AIC for CAN interrupts\r
+    AIC_ConfigureIT(AT91C_ID_CAN0, AT91C_AIC_PRIOR_HIGHEST, CAN0_Handler);\r
+\r
+    // Enable the interrupt on the interrupt controller\r
+    AIC_EnableIT(AT91C_ID_CAN0);\r
+\r
+    if( CAN_BaudRateCalculate(AT91C_BASE_CAN0, baudrate) == 0 ) {\r
+        // Baudrate problem\r
+        TRACE_DEBUG("Baudrate CAN0 problem\n\r");\r
+        return 0;\r
+    }\r
+\r
+    pCAN0Transfer = canTransfer0;\r
+\r
+#if defined AT91C_BASE_CAN1\r
+    if( canTransfer1 != NULL ) {\r
+        pCAN1Transfer = canTransfer1;\r
+        // Enable CAN1 Clocks\r
+        AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_CAN1);\r
+\r
+        // disable all IT\r
+        AT91C_BASE_CAN1->CAN_IDR = 0x1FFFFFFF;\r
+\r
+        // Configure the AIC for CAN interrupts\r
+        AIC_ConfigureIT(AT91C_ID_CAN1, AT91C_AIC_PRIOR_HIGHEST, CAN1_Handler);\r
+\r
+        // Enable the interrupt on the interrupt controller\r
+        AIC_EnableIT(AT91C_ID_CAN1);\r
+\r
+        if( CAN_BaudRateCalculate(AT91C_BASE_CAN1, baudrate) == 0 ) {\r
+            // Baudrate problem\r
+            TRACE_DEBUG("Baudrate CAN1 problem\n\r");\r
+            return 0;\r
+        }\r
+    }\r
+#endif\r
+    // Reset all mailbox\r
+    CAN_ResetAllMailbox();\r
+\r
+    // Enable the interrupt with all error cases\r
+    AT91C_BASE_CAN0->CAN_IER =  AT91C_CAN_CERR  // (CAN) CRC Error\r
+                             |  AT91C_CAN_SERR  // (CAN) Stuffing Error\r
+                             |  AT91C_CAN_BERR  // (CAN) Bit Error\r
+                             |  AT91C_CAN_FERR  // (CAN) Form Error\r
+                             |  AT91C_CAN_AERR; // (CAN) Acknowledgment Error\r
+\r
+#if defined AT91C_BASE_CAN1\r
+    if( canTransfer1 != NULL ) {\r
+        AT91C_BASE_CAN1->CAN_IER =  AT91C_CAN_CERR  // (CAN) CRC Error\r
+                                 |  AT91C_CAN_SERR  // (CAN) Stuffing Error\r
+                                 |  AT91C_CAN_BERR  // (CAN) Bit Error\r
+                                 |  AT91C_CAN_FERR  // (CAN) Form Error\r
+                                 |  AT91C_CAN_AERR; // (CAN) Acknowledgment Error\r
+    }\r
+#endif\r
+\r
+    // Wait for CAN synchronisation\r
+    if( CAN_Synchronisation( ) == 1 ) {\r
+        ret = 1;\r
+    }\r
+    else {\r
+        ret = 0;\r
+    }\r
+\r
+    return ret;\r
+}\r
+\r

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/can/can.h b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/can/can.h
new file mode 100644 (file)
index 0000000..63a83b3
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/can/can.h
@@ -0,0 +1,113 @@
+/* ----------------------------------------------------------------------------\r
+ *         ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+#ifndef _CAN_H\r
+#define _CAN_H\r
+\r
+//------------------------------------------------------------------------------\r
+//      Definitions\r
+//------------------------------------------------------------------------------\r
+#define AT91C_CAN_TIMEOUT         100000\r
+\r
+#define AT91C_TEST_NOK                 0\r
+#define AT91C_TEST_OK                  1\r
+\r
+#define CAN_STATUS_SUCCESS             0\r
+#define CAN_STATUS_LOCKED              1\r
+#define CAN_STATUS_ABORTED             2\r
+#define CAN_STATUS_RESET               3\r
+\r
+#if defined (AT91C_BASE_CAN)\r
+    #define AT91C_BASE_CAN0      AT91C_BASE_CAN\r
+#endif\r
+#if defined (AT91C_ID_CAN)\r
+    #define AT91C_ID_CAN0        AT91C_ID_CAN\r
+#endif\r
+#if defined (AT91C_BASE_CAN_MB0)\r
+    #define AT91C_BASE_CAN0_MB0  AT91C_BASE_CAN_MB0\r
+    #define AT91C_BASE_CAN0_MB1  AT91C_BASE_CAN_MB1\r
+    #define AT91C_BASE_CAN0_MB2  AT91C_BASE_CAN_MB2\r
+    #define AT91C_BASE_CAN0_MB3  AT91C_BASE_CAN_MB3\r
+    #define AT91C_BASE_CAN0_MB4  AT91C_BASE_CAN_MB4\r
+    #define AT91C_BASE_CAN0_MB5  AT91C_BASE_CAN_MB5\r
+    #define AT91C_BASE_CAN0_MB6  AT91C_BASE_CAN_MB6\r
+    #define AT91C_BASE_CAN0_MB7  AT91C_BASE_CAN_MB7\r
+#endif\r
+#if defined (AT91C_BASE_CAN_MB8)\r
+    #define AT91C_BASE_CAN0_MB8   AT91C_BASE_CAN_MB8\r
+    #define AT91C_BASE_CAN0_MB9   AT91C_BASE_CAN_MB9\r
+    #define AT91C_BASE_CAN0_MB10  AT91C_BASE_CAN_MB10\r
+    #define AT91C_BASE_CAN0_MB11  AT91C_BASE_CAN_MB11\r
+    #define AT91C_BASE_CAN0_MB12  AT91C_BASE_CAN_MB12\r
+    #define AT91C_BASE_CAN0_MB13  AT91C_BASE_CAN_MB13\r
+    #define AT91C_BASE_CAN0_MB14  AT91C_BASE_CAN_MB14\r
+    #define AT91C_BASE_CAN0_MB15  AT91C_BASE_CAN_MB15\r
+#endif\r
+\r
+#define NUM_MAILBOX_MAX 16\r
+\r
+//------------------------------------------------------------------------------\r
+//         Types\r
+//------------------------------------------------------------------------------\r
+typedef struct\r
+{\r
+    volatile unsigned char state;\r
+    volatile unsigned char can_number;\r
+    volatile unsigned char mailbox_number;\r
+    volatile unsigned char test_can;\r
+    volatile unsigned int  mode_reg;\r
+    volatile unsigned int  acceptance_mask_reg;\r
+    volatile unsigned int  identifier;\r
+    volatile unsigned int  data_low_reg;\r
+    volatile unsigned int  data_high_reg;\r
+    volatile unsigned int  control_reg;\r
+    volatile unsigned int  mailbox_in_use;\r
+    volatile int           size;\r
+} CanTransfer;\r
+\r
+//------------------------------------------------------------------------------\r
+//         Exported functions\r
+//------------------------------------------------------------------------------\r
+extern unsigned char CAN_Init( unsigned int baudrate, \r
+                               CanTransfer *canTransferRead, \r
+                               CanTransfer *canTransferWrite );\r
+extern void CAN_BasicTestSuite(void);\r
+extern void CAN_disable( void );\r
+extern void CAN_ResetAllMailbox( void );\r
+extern void CAN_ResetTransfer( CanTransfer *pTransfer );\r
+extern void CAN_InitMailboxRegisters( CanTransfer *pTransfer );\r
+extern unsigned char CAN_IsInIdle( CanTransfer *pTransfer );\r
+\r
+extern unsigned char CAN_Write( CanTransfer *pTransfer );\r
+extern unsigned char CAN_Read( CanTransfer *pTransfer );\r
+\r
+extern void CAN_BasicTestSuiteWithoutInterrupt( void );\r
+extern unsigned char CAN_IsInIdle( CanTransfer *pTransfer );\r
+#endif // _CAN_H\r
+\r

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/cp15/cp15.c b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/cp15/cp15.c
new file mode 100644 (file)
index 0000000..17a1f70
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/cp15/cp15.c
@@ -0,0 +1,268 @@
+/* ----------------------------------------------------------------------------\r
+ *         ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+//-----------------------------------------------------------------------------\r
+//         Headers\r
+//-----------------------------------------------------------------------------\r
+\r
+#include <board.h>\r
+\r
+#ifdef CP15_PRESENT\r
+\r
+#include <utility/trace.h>\r
+#include "cp15.h"\r
+\r
+#if defined(__ICCARM__)\r
+#include <intrinsics.h>\r
+#endif\r
+\r
+\r
+//-----------------------------------------------------------------------------\r
+//         Macros\r
+//-----------------------------------------------------------------------------\r
+\r
+//-----------------------------------------------------------------------------\r
+//         Defines\r
+//-----------------------------------------------------------------------------\r
+/*\r
+#define CP15_RR_BIT 14 // RR bit Replacement strategy for ICache and DCache: \r
+                       // 0 = Random replacement \r
+                       // 1 = Round-robin replacement.\r
+                      \r
+#define CP15_V_BIT  13 // V bit Location of exception vectors: \r
+                       // 0 = Normal exception vectors selected address range = 0x0000 0000 to 0x0000 001C \r
+                       // 1 = High exception vect selected, address range = 0xFFFF 0000 to 0xFFFF 001C\r
+*/                       \r
+#define CP15_I_BIT  12 // I bit ICache enable/disable: \r
+                       // 0 = ICache disabled \r
+                       // 1 = ICache enabled\r
+/*                       \r
+#define CP15_R_BIT   9 // R bit ROM protection\r
+\r
+#define CP15_S_BIT   8 // S bit System protection\r
+                  \r
+#define CP15_B_BIT   7 // B bit Endianness: \r
+                       // 0 = Little-endian operation \r
+                       // 1 = Big-endian operation.                  \r
+*/                     \r
+#define CP15_C_BIT   2 // C bit DCache enable/disable: \r
+                       // 0 = Cache disabled \r
+                       // 1 = Cache enabled\r
+/*\r
+#define CP15_A_BIT   1 // A bit Alignment fault enable/disable:\r
+                       // 0 = Data address alignment fault checking disabled\r
+                       // 1 = Data address alignment fault checking enabled\r
+*/\r
+#define CP15_M_BIT   0 // M bit MMU enable/disable: 0 = disabled 1 = enabled.\r
+                       // 0 = disabled \r
+                       // 1 = enabled\r
+\r
+\r
+//-----------------------------------------------------------------------------\r
+//         Global functions\r
+//-----------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+/// Check Instruction Cache\r
+/// \return 0 if I_Cache disable, 1 if I_Cache enable\r
+//------------------------------------------------------------------------------\r
+unsigned int CP15_Is_I_CacheEnabled(void)\r
+{\r
+    unsigned int control;\r
+\r
+    control = _readControlRegister();\r
+    return ((control & (1 << CP15_I_BIT)) != 0);\r
+} \r
+\r
+//------------------------------------------------------------------------------\r
+/// Enable Instruction Cache\r
+//------------------------------------------------------------------------------\r
+void CP15_Enable_I_Cache(void)\r
+{\r
+    unsigned int control;\r
+\r
+    control = _readControlRegister();\r
+\r
+    // Check if cache is disabled\r
+    if ((control & (1 << CP15_I_BIT)) == 0) {\r
+\r
+        control |= (1 << CP15_I_BIT);\r
+        _writeControlRegister(control);        \r
+        TRACE_INFO("I cache enabled.\n\r");\r
+    }\r
+#if !defined(OP_BOOTSTRAP_on)\r
+    else {\r
+\r
+        TRACE_INFO("I cache is already enabled.\n\r");\r
+    }\r
+#endif\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Disable Instruction Cache\r
+//------------------------------------------------------------------------------\r
+void CP15_Disable_I_Cache(void)\r
+{\r
+    unsigned int control;\r
+\r
+    control = _readControlRegister();\r
+\r
+    // Check if cache is enabled\r
+    if ((control & (1 << CP15_I_BIT)) != 0) {\r
+\r
+        control &= ~(1 << CP15_I_BIT);\r
+        _writeControlRegister(control);        \r
+        TRACE_INFO("I cache disabled.\n\r");\r
+    }\r
+    else {\r
+\r
+        TRACE_INFO("I cache is already disabled.\n\r");\r
+    }\r
+} \r
+\r
+//------------------------------------------------------------------------------\r
+/// Check MMU\r
+/// \return 0 if MMU disable, 1 if MMU enable\r
+//------------------------------------------------------------------------------\r
+unsigned int CP15_Is_MMUEnabled(void)\r
+{\r
+    unsigned int control;\r
+\r
+    control = _readControlRegister();\r
+    return ((control & (1 << CP15_M_BIT)) != 0);\r
+} \r
+\r
+//------------------------------------------------------------------------------\r
+/// Enable MMU\r
+//------------------------------------------------------------------------------\r
+void CP15_EnableMMU(void)\r
+{\r
+    unsigned int control;\r
+\r
+    control = _readControlRegister();\r
+\r
+    // Check if MMU is disabled\r
+    if ((control & (1 << CP15_M_BIT)) == 0) {\r
+\r
+        control |= (1 << CP15_M_BIT);\r
+        _writeControlRegister(control);        \r
+        TRACE_INFO("MMU enabled.\n\r");\r
+    }\r
+    else {\r
+\r
+        TRACE_INFO("MMU is already enabled.\n\r");\r
+    }\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Disable MMU\r
+//------------------------------------------------------------------------------\r
+void CP15_DisableMMU(void)\r
+{\r
+    unsigned int control;\r
+\r
+    control = _readControlRegister();\r
+\r
+    // Check if MMU is enabled\r
+    if ((control & (1 << CP15_M_BIT)) != 0) {\r
+\r
+        control &= ~(1 << CP15_M_BIT);\r
+        control &= ~(1 << CP15_C_BIT);\r
+        _writeControlRegister(control);        \r
+        TRACE_INFO("MMU disabled.\n\r");\r
+    }\r
+    else {\r
+\r
+        TRACE_INFO("MMU is already disabled.\n\r");\r
+    }\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Check D_Cache\r
+/// \return 0 if D_Cache disable, 1 if D_Cache enable (with MMU of course)\r
+//------------------------------------------------------------------------------\r
+unsigned int CP15_Is_DCacheEnabled(void)\r
+{\r
+    unsigned int control;\r
+\r
+    control = _readControlRegister();\r
+    return ((control & ((1 << CP15_C_BIT)||(1 << CP15_M_BIT))) != 0);\r
+} \r
+\r
+//------------------------------------------------------------------------------\r
+/// Enable Data Cache\r
+//------------------------------------------------------------------------------\r
+void CP15_Enable_D_Cache(void)\r
+{\r
+    unsigned int control;\r
+\r
+    control = _readControlRegister();\r
+\r
+    if( !CP15_Is_MMUEnabled() ) {\r
+        TRACE_ERROR("Do nothing: MMU not enabled\n\r");\r
+    }\r
+    else {\r
+        // Check if cache is disabled\r
+        if ((control & (1 << CP15_C_BIT)) == 0) {\r
+\r
+            control |= (1 << CP15_C_BIT);\r
+            _writeControlRegister(control);        \r
+            TRACE_INFO("D cache enabled.\n\r");\r
+        }\r
+        else {\r
+\r
+            TRACE_INFO("D cache is already enabled.\n\r");\r
+        }\r
+    }\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Disable Data Cache\r
+//------------------------------------------------------------------------------\r
+void CP15_Disable_D_Cache(void)\r
+{\r
+    unsigned int control;\r
+\r
+    control = _readControlRegister();\r
+\r
+    // Check if cache is enabled\r
+    if ((control & (1 << CP15_C_BIT)) != 0) {\r
+\r
+        control &= ~(1 << CP15_C_BIT);\r
+        _writeControlRegister(control);        \r
+        TRACE_INFO("D cache disabled.\n\r");\r
+    }\r
+    else {\r
+\r
+        TRACE_INFO("D cache is already disabled.\n\r");\r
+    }\r
+}\r
+\r
+#endif // CP15_PRESENT\r
+\r

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/cp15/cp15.h b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/cp15/cp15.h
new file mode 100644 (file)
index 0000000..ddaaeb6
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/cp15/cp15.h
@@ -0,0 +1,84 @@
+/* ----------------------------------------------------------------------------\r
+ *         ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+//------------------------------------------------------------------------------\r
+/// \unit\r
+///\r
+/// !Purpose\r
+/// \r
+/// Methods to manage the Coprocessor 15. Coprocessor 15, or System Control \r
+/// Coprocessor CP15, is used to configure and control all the items in the \r
+/// list below:\r
+/// \95 ARM core\r
+/// \95 Caches (ICache, DCache and write buffer)\r
+/// \95 TCM\r
+/// \95 MMU\r
+/// \95 Other system options\r
+/// \r
+/// !Usage\r
+///\r
+/// -# Enable or disable D cache with Enable_D_Cache and Disable_D_Cache\r
+/// -# Enable or disable I cache with Enable_I_Cache and Disable_I_Cache\r
+///\r
+//------------------------------------------------------------------------------\r
+\r
+#ifndef _CP15_H\r
+#define _CP15_H\r
+\r
+#ifdef CP15_PRESENT\r
+\r
+//-----------------------------------------------------------------------------\r
+//         Exported functions\r
+//-----------------------------------------------------------------------------\r
+extern void CP15_Enable_I_Cache(void);\r
+extern unsigned int CP15_Is_I_CacheEnabled(void);\r
+extern void CP15_Enable_I_Cache(void);\r
+extern void CP15_Disable_I_Cache(void);\r
+extern unsigned int CP15_Is_MMUEnabled(void);\r
+extern void CP15_EnableMMU(void);\r
+extern void CP15_DisableMMU(void);\r
+extern unsigned int CP15_Is_DCacheEnabled(void);\r
+extern void CP15_Enable_D_Cache(void);\r
+extern void CP15_Disable_D_Cache(void);\r
+\r
+//-----------------------------------------------------------------------------\r
+//         External functions defined in cp15.S\r
+//-----------------------------------------------------------------------------\r
+extern unsigned int _readControlRegister(void);\r
+extern void _writeControlRegister(unsigned int value);\r
+extern void _waitForInterrupt(void);\r
+extern void _writeTTB(unsigned int value);\r
+extern void _writeDomain(unsigned int value);\r
+extern void _writeITLBLockdown(unsigned int value);\r
+extern void _prefetchICacheLine(unsigned int value);\r
+\r
+#endif // CP15_PRESENT\r
+\r
+#endif // #ifndef _CP15_H\r
+\r

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/cp15/cp15_asm_iar.s b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/cp15/cp15_asm_iar.s
new file mode 100644 (file)
index 0000000..0c76139
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/cp15/cp15_asm_iar.s
@@ -0,0 +1,145 @@
+/* ----------------------------------------------------------------------------\r
+ *         ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+        MODULE  ?cp15\r
+\r
+        ;; Forward declaration of sections.\r
+        SECTION IRQ_STACK:DATA:NOROOT(2)\r
+        SECTION CSTACK:DATA:NOROOT(3)\r
+\r
+//------------------------------------------------------------------------------\r
+//         Headers\r
+//------------------------------------------------------------------------------\r
+\r
+#define __ASSEMBLY__\r
+#include "board.h"\r
+\r
+#ifdef CP15_PRESENT\r
+\r
+//------------------------------------------------------------------------------\r
+/// Functions to access CP15 coprocessor register\r
+//------------------------------------------------------------------------------\r
+\r
+        PUBLIC  _readControlRegister\r
+        PUBLIC  _writeControlRegister\r
+        PUBLIC  _waitForInterrupt\r
+        PUBLIC  _writeTTB\r
+        PUBLIC  _writeDomain\r
+        PUBLIC  _writeITLBLockdown\r
+        PUBLIC  _prefetchICacheLine\r
+\r
+//------------------------------------------------------------------------------\r
+/// Control Register c1\r
+/// Register c1 is the Control Register for the ARM926EJ-S processor. \r
+/// This register specifies the configuration used to enable and disable the \r
+/// caches and MMU. It is recommended that you access this register using a \r
+/// read-modify-write sequence.\r
+//------------------------------------------------------------------------------\r
+// CP15 Read Control Register\r
+_readControlRegister:\r
+        mov     r0, #0\r
+        mrc     p15, 0, r0, c1, c0, 0\r
+        bx      lr\r
+\r
+// CP15 Write Control Register\r
+_writeControlRegister:\r
+        mcr     p15, 0, r0, c1, c0, 0\r
+        bx      lr\r
+\r
+//------------------------------------------------------------------------------\r
+/// CP15 Wait For Interrupt operation\r
+/// The purpose of the Wait For Interrupt operation is to put the processor in\r
+/// to a low power state.\r
+/// This puts the processor into a low-power state and stops it executing more\r
+/// instructions until an interrupt, or debug request occurs, regardless of\r
+/// whether the interrupts are disabled by the masks in the CPSR. \r
+/// When an interrupt does occur, the MCR instruction completes and the IRQ or\r
+/// FIQ handler is entered as normal. The return link in r14_irq or r14_fiq \r
+/// contains the address of the MCR instruction plus 8, so that the normal \r
+/// instruction used for interrupt return (SUBS PC,R14,#4) returns to the \r
+/// instruction following the MCR.\r
+/// Wait For Interrupt : MCR p15, 0, <Rd>, c7, c0, 4\r
+//------------------------------------------------------------------------------\r
+_waitForInterrupt:\r
+        mov     r0, #0\r
+        mcr     p15, 0, r0, c7, c0, 4\r
+        bx      lr\r
+\r
+//------------------------------------------------------------------------------\r
+/// CP15 Translation Table Base Register c2\r
+/// Register c2 is the Translation Table Base Register (TTBR), for the base \r
+/// address of the first-level translation table.\r
+/// Reading from c2 returns the pointer to the currently active first-level\r
+/// translation table in bits [31:14] and an Unpredictable value in bits [13:0]. \r
+/// Writing to register c2 updates the pointer to the first-level translation \r
+/// table from the value in bits [31:14] of the written value. Bits [13:0] \r
+/// Should Be Zero.\r
+/// You can use the following instructions to access the TTBR:\r
+/// Read TTBR  : MRC p15, 0, <Rd>, c2, c0, 0\r
+/// Write TTBR : MCR p15, 0, <Rd>, c2, c0, 0\r
+//------------------------------------------------------------------------------\r
+_writeTTB:\r
+        MCR     p15, 0, r0, c2, c0, 0\r
+        bx      lr\r
+\r
+//------------------------------------------------------------------------------\r
+/// Domain Access Control Register c3\r
+/// Read domain access permissions  : MRC p15, 0, <Rd>, c3, c0, 0\r
+/// Write domain access permissions : MCR p15, 0, <Rd>, c3, c0, 0\r
+//------------------------------------------------------------------------------\r
+_writeDomain:\r
+        MCR     p15, 0, r0, c3, c0, 0\r
+        bx      lr\r
+\r
+//------------------------------------------------------------------------------\r
+/// TLB Lockdown Register c10\r
+/// The TLB Lockdown Register controls where hardware page table walks place the\r
+/// TLB entry, in the set associative region or the lockdown region of the TLB, \r
+/// and if in the lockdown region, which entry is written. The lockdown region \r
+/// of the TLB contains eight entries. See TLB structure for a description of \r
+/// the structure of the TLB.\r
+/// Read data TLB lockdown victim  : MRC p15,0,<Rd>,c10,c0,0\r
+/// Write data TLB lockdown victim : MCR p15,0,<Rd>,c10,c0,0\r
+//------------------------------------------------------------------------------\r
+_writeITLBLockdown:\r
+        MCR     p15, 0, r0, c10, c0, 0\r
+        bx      lr\r
+\r
+//------------------------------------------------------------------------------\r
+/// Prefetch ICache line\r
+/// Performs an ICache lookup of the specified modified virtual address.\r
+/// If the cache misses, and the region is cacheable, a linefill is performed.\r
+/// Prefetch ICache line (MVA): MCR p15, 0, <Rd>, c7, c13, 1\r
+//------------------------------------------------------------------------------\r
+_prefetchICacheLine:\r
+        MCR     p15, 0, r0, c7, c13, 1\r
+        bx      lr\r
+#endif\r
+    END\r
+\r

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/dbgu/dbgu.c b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/dbgu/dbgu.c
new file mode 100644 (file)
index 0000000..2034730
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/dbgu/dbgu.c
@@ -0,0 +1,174 @@
+/* ----------------------------------------------------------------------------\r
+ *         ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+//------------------------------------------------------------------------------\r
+//         Headers\r
+//------------------------------------------------------------------------------\r
+\r
+#include "dbgu.h"\r
+#include <stdarg.h>\r
+#include <board.h>\r
+\r
+//------------------------------------------------------------------------------\r
+//         Global functions\r
+//------------------------------------------------------------------------------\r
+//------------------------------------------------------------------------------\r
+/// Initializes the DBGU with the given parameters, and enables both the\r
+/// transmitter and the receiver. The mode parameter contains the value of the\r
+/// DBGU_MR register.\r
+/// Value DBGU_STANDARD can be used for mode to get the most common configuration\r
+/// (i.e. aysnchronous, 8bits, no parity, 1 stop bit, no flow control).\r
+/// \param mode  Operating mode to configure.\r
+/// \param baudrate  Desired baudrate (e.g. 115200).\r
+/// \param mck  Frequency of the system master clock in Hz.\r
+//------------------------------------------------------------------------------\r
+void DBGU_Configure(\r
+    unsigned int mode,\r
+    unsigned int baudrate,\r
+    unsigned int mck)\r
+{   \r
+    // Reset & disable receiver and transmitter, disable interrupts\r
+    AT91C_BASE_DBGU->DBGU_CR = AT91C_US_RSTRX | AT91C_US_RSTTX;\r
+    AT91C_BASE_DBGU->DBGU_IDR = 0xFFFFFFFF;\r
+    \r
+    // Configure baud rate\r
+    AT91C_BASE_DBGU->DBGU_BRGR = mck / (baudrate * 16);\r
+    \r
+    // Configure mode register\r
+    AT91C_BASE_DBGU->DBGU_MR = mode;\r
+    \r
+    // Disable DMA channel\r
+    AT91C_BASE_DBGU->DBGU_PTCR = AT91C_PDC_RXTDIS | AT91C_PDC_TXTDIS;\r
+\r
+    // Enable receiver and transmitter\r
+    AT91C_BASE_DBGU->DBGU_CR = AT91C_US_RXEN | AT91C_US_TXEN;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Outputs a character on the DBGU line.\r
+/// \note This function is synchronous (i.e. uses polling).\r
+/// \param c  Character to send.\r
+//------------------------------------------------------------------------------\r
+void DBGU_PutChar(unsigned char c)\r
+{\r
+    // Wait for the transmitter to be ready\r
+    while ((AT91C_BASE_DBGU->DBGU_CSR & AT91C_US_TXEMPTY) == 0);\r
+    \r
+    // Send character\r
+    AT91C_BASE_DBGU->DBGU_THR = c;\r
+    \r
+    // Wait for the transfer to complete\r
+    while ((AT91C_BASE_DBGU->DBGU_CSR & AT91C_US_TXEMPTY) == 0);\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Return 1 if a character can be read in DBGU\r
+//------------------------------------------------------------------------------\r
+unsigned int DBGU_IsRxReady()\r
+{\r
+    return (AT91C_BASE_DBGU->DBGU_CSR & AT91C_US_RXRDY);\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Reads and returns a character from the DBGU.\r
+/// \note This function is synchronous (i.e. uses polling).\r
+/// \return Character received.\r
+//------------------------------------------------------------------------------\r
+unsigned char DBGU_GetChar(void)\r
+{\r
+    while ((AT91C_BASE_DBGU->DBGU_CSR & AT91C_US_RXRDY) == 0);\r
+    return AT91C_BASE_DBGU->DBGU_RHR;\r
+}\r
+\r
+#ifndef NOFPUT\r
+#include <stdio.h>\r
+\r
+//------------------------------------------------------------------------------\r
+/// \exclude\r
+/// Implementation of fputc using the DBGU as the standard output. Required\r
+/// for printf().\r
+/// \param c  Character to write.\r
+/// \param pStream  Output stream.\r
+/// \param The character written if successful, or -1 if the output stream is\r
+/// not stdout or stderr.\r
+//------------------------------------------------------------------------------\r
+signed int fputc(signed int c, FILE *pStream)\r
+{\r
+    if ((pStream == stdout) || (pStream == stderr)) {\r
+    \r
+        DBGU_PutChar(c);\r
+        return c;\r
+    }\r
+    else {\r
+\r
+        return EOF;\r
+    }\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// \exclude\r
+/// Implementation of fputs using the DBGU as the standard output. Required\r
+/// for printf(). Does NOT currently use the PDC.\r
+/// \param pStr  String to write.\r
+/// \param pStream  Output stream.\r
+/// \return Number of characters written if successful, or -1 if the output\r
+/// stream is not stdout or stderr.\r
+//------------------------------------------------------------------------------\r
+signed int fputs(const char *pStr, FILE *pStream)\r
+{\r
+    signed int num = 0;\r
+\r
+    while (*pStr != 0) {\r
+\r
+        if (fputc(*pStr, pStream) == -1) {\r
+\r
+            return -1;\r
+        }\r
+        num++;\r
+        pStr++;\r
+    }\r
+\r
+    return num;\r
+}\r
+\r
+#undef putchar\r
+\r
+//------------------------------------------------------------------------------\r
+/// \exclude\r
+/// Outputs a character on the DBGU.\r
+/// \param c  Character to output.\r
+/// \return The character that was output.\r
+//------------------------------------------------------------------------------\r
+signed int putchar(signed int c)\r
+{\r
+    return fputc(c, stdout);\r
+}\r
+\r
+#endif //#ifndef NOFPUT\r
+\r

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/dbgu/dbgu.h b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/dbgu/dbgu.h
new file mode 100644 (file)
index 0000000..816f11d
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/dbgu/dbgu.h
@@ -0,0 +1,79 @@
+/* ----------------------------------------------------------------------------\r
+ *         ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+//------------------------------------------------------------------------------\r
+/// \unit\r
+///\r
+/// !Purpose\r
+/// \r
+/// This module provides definitions and functions for using the Debug Unit\r
+/// (DBGU).\r
+///\r
+/// It also overloads the fputc(), fputs() & putchar() functions so the printf()\r
+/// method outputs its data on the DBGU. This behavior can be suppressed by\r
+/// defining NOFPUT during compilation.\r
+///\r
+/// !Usage\r
+/// \r
+/// -# Enable the DBGU pins (see pio & board.h).\r
+/// -# Configure the DBGU using DBGU_Configure with the desired operating mode.\r
+/// -# Send characters using DBGU_PutChar() or the printf() method.\r
+/// -# Receive characters using DBGU_GetChar().\r
+///\r
+/// \note Unless specified, all the functions defined here operate synchronously;\r
+/// i.e. they all wait the data is sent/received before returning.\r
+//------------------------------------------------------------------------------\r
+\r
+#ifndef DBGU_H\r
+#define DBGU_H\r
+\r
+//------------------------------------------------------------------------------\r
+//         Definitions\r
+//------------------------------------------------------------------------------\r
+ \r
+/// Standard operating mode (asynchronous, 8bit, no parity, 1 stop bit)\r
+#define DBGU_STANDARD           AT91C_US_PAR_NONE\r
+\r
+//------------------------------------------------------------------------------\r
+//         Global functions\r
+//------------------------------------------------------------------------------\r
+\r
+extern void DBGU_Configure(\r
+    unsigned int mode,\r
+    unsigned int baudrate,\r
+    unsigned int mck);\r
+\r
+extern unsigned char DBGU_GetChar(void);\r
+\r
+extern void DBGU_PutChar(unsigned char c);\r
+\r
+extern unsigned int DBGU_IsRxReady(void);\r
+\r
+#endif //#ifndef DBGU_H\r
+\r

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/dma/dma.c b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/dma/dma.c
new file mode 100644 (file)
index 0000000..e78a7c5
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/dma/dma.c
@@ -0,0 +1,355 @@
+/* ----------------------------------------------------------------------------\r
+ *         ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+//------------------------------------------------------------------------------\r
+//         Headers\r
+//------------------------------------------------------------------------------\r
+\r
+#include "dma.h"\r
+#include <utility/assert.h>\r
+#include <utility/trace.h>\r
+\r
+//------------------------------------------------------------------------------\r
+//         Global functions\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+/// Configure a DMAC peripheral\r
+//------------------------------------------------------------------------------\r
+void DMA_Config(unsigned int flag)\r
+{\r
+    AT91C_BASE_HDMA->HDMA_GCFG = flag;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Enables a DMAC peripheral\r
+//------------------------------------------------------------------------------\r
+void DMA_Enable(void)\r
+{\r
+    AT91C_BASE_HDMA->HDMA_EN = AT91C_HDMA_ENABLE;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Disables DMAC peripheral\r
+//------------------------------------------------------------------------------\r
+void DMA_Disable(void)\r
+{\r
+    AT91C_BASE_HDMA->HDMA_EN = ~(AT91C_HDMA_ENABLE);\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Enable DMA interrupt\r
+/// \param flag IT to be enabled\r
+//-----------------------------------------------------------------------------\r
+void DMA_EnableIt (unsigned int flag)\r
+{\r
+    AT91C_BASE_HDMA->HDMA_EBCIER = flag;\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Disable DMA interrupt\r
+/// \param flag IT to be enabled\r
+//-----------------------------------------------------------------------------\r
+void DMA_DisableIt (unsigned int flag)\r
+{\r
+    AT91C_BASE_HDMA->HDMA_EBCIDR = flag;\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Return DMA Interrupt Status\r
+//-----------------------------------------------------------------------------\r
+unsigned int DMA_GetStatus(void)\r
+{\r
+    return (AT91C_BASE_HDMA->HDMA_EBCISR);\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Return DMA Interrupt Mask Status\r
+//-----------------------------------------------------------------------------\r
+unsigned int DMA_GetInterruptMask(void)\r
+{\r
+    return (AT91C_BASE_HDMA->HDMA_EBCIMR);\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Returns the current status register of the given DMA peripheral, but\r
+/// masking interrupt sources which are not currently enabled.\r
+//-----------------------------------------------------------------------------\r
+unsigned int DMA_GetMaskedStatus(void)\r
+{\r
+    unsigned int status;\r
+    status = AT91C_BASE_HDMA->HDMA_EBCISR;\r
+    status &= AT91C_BASE_HDMA->HDMA_EBCIMR;\r
+    return status;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Enables DMAC channel \r
+/// \param channel Particular channel number.\r
+//------------------------------------------------------------------------------\r
+void DMA_EnableChannel(unsigned int channel)\r
+{\r
+    ASSERT(channel < DMA_CHANNEL_NUM, "this channel does not exist");\r
+    AT91C_BASE_HDMA->HDMA_CHER |= DMA_ENA << channel;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Disables a DMAC channel \r
+/// \param channel Particular channel number.\r
+//------------------------------------------------------------------------------\r
+void DMA_DisableChannel(unsigned int channel)\r
+{\r
+    ASSERT(channel < DMA_CHANNEL_NUM, "this channel does not exist");\r
+    AT91C_BASE_HDMA->HDMA_CHDR |= DMA_DIS << channel;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Resume DMAC channel from an stall state.\r
+/// \param channel Particular channel number.\r
+//------------------------------------------------------------------------------\r
+void DMA_KeeponChannel(unsigned int channel)\r
+{\r
+    ASSERT(channel < DMA_CHANNEL_NUM, "this channel does not exist");\r
+    AT91C_BASE_HDMA->HDMA_CHER |= DMA_KEEPON << channel;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Clear automatic mode for multi-buffer transfer.\r
+/// \param channel Particular channel number.\r
+//------------------------------------------------------------------------------\r
+void DMA_ClearAutoMode(unsigned int channel)\r
+{\r
+    ASSERT(channel < DMA_CHANNEL_NUM, "this channel does not exist");\r
+    AT91C_BASE_HDMA->HDMA_CH[channel].HDMA_CTRLB &= 0x7FFFFFFF;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Return DMAC channel status \r
+//------------------------------------------------------------------------------\r
+unsigned int DMA_GetChannelStatus(void)\r
+{\r
+   return( AT91C_BASE_HDMA->HDMA_CHSR);\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Set DMA source address used by a HDMA channel.\r
+/// \param channel Particular channel number.\r
+/// \param sources sources address.\r
+//-----------------------------------------------------------------------------\r
+void DMA_SetSourceAddr(unsigned char channel, unsigned int address)\r
+{\r
+    ASSERT(channel < DMA_CHANNEL_NUM, "this channel does not exist");\r
+    AT91C_BASE_HDMA->HDMA_CH[channel].HDMA_SADDR = address;\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Set DMA destination address used by a HDMA channel.\r
+/// \param channel Particular channel number.\r
+/// \param sources destination address.\r
+//-----------------------------------------------------------------------------\r
+void DMA_SetDestinationAddr(unsigned char channel, unsigned int address)\r
+{\r
+    ASSERT(channel < DMA_CHANNEL_NUM, "this channel does not exist");\r
+    AT91C_BASE_HDMA->HDMA_CH[channel].HDMA_DADDR = address;\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Set DMA descriptor address used by a HDMA channel.\r
+/// \param channel Particular channel number.\r
+/// \param sources destination address.\r
+//-----------------------------------------------------------------------------\r
+void DMA_SetDescriptorAddr(unsigned char channel, unsigned int address)\r
+{\r
+    ASSERT(channel < DMA_CHANNEL_NUM, "this channel does not exist");\r
+    AT91C_BASE_HDMA->HDMA_CH[channel].HDMA_DSCR = address ;\r
+}\r
+\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Set DMA control A register used by a HDMA channel.\r
+/// \param channel Particular channel number.\r
+/// \param size Dma transfer size in byte.\r
+/// \param sourceWidth Single transfer width for source.\r
+/// \param destWidth Single transfer width for destination.\r
+/// \param done Transfer done field.\r
+//-----------------------------------------------------------------------------\r
+void DMA_SetSourceBufferSize(unsigned char channel,\r
+                             unsigned int size, \r
+                             unsigned char sourceWidth, \r
+                             unsigned char destWidth,\r
+                             unsigned char done)\r
+{\r
+    ASSERT(channel < DMA_CHANNEL_NUM, "this channel does not exist");\r
+    ASSERT(sourceWidth < 4, "width does not support");\r
+    ASSERT(destWidth < 4, "width does not support");\r
+    AT91C_BASE_HDMA->HDMA_CH[channel].HDMA_CTRLA = (size |\r
+                                                   sourceWidth << 24 |\r
+                                                   destWidth << 28 |\r
+                                                   done << 31);\r
+}\r
+                                \r
+//-----------------------------------------------------------------------------\r
+/// Set DMA transfer mode for source used by a HDMA channel.\r
+/// \param channel Particular channel number.\r
+/// \param transferMode Transfer buffer mode (single, LLI, reload or contiguous)\r
+/// \param addressingType Type of addrassing mode\r
+///                       0 : incrementing, 1: decrementing, 2: fixed.\r
+//-----------------------------------------------------------------------------\r
+void DMA_SetSourceBufferMode(unsigned char channel, \r
+                             unsigned char transferMode,\r
+                             unsigned char addressingType)\r
+{\r
+    unsigned int value;\r
+    \r
+    ASSERT(channel < DMA_CHANNEL_NUM, "this channel does not exist");\r
+    \r
+    value = AT91C_BASE_HDMA->HDMA_CH[channel].HDMA_CTRLB;\r
+    value &= ~ (AT91C_SRC_DSCR | AT91C_SRC_INCR | 1<<31);\r
+    switch(transferMode){\r
+        case DMA_TRANSFER_SINGLE:\r
+             value |= AT91C_SRC_DSCR | addressingType << 24;\r
+             break;\r
+        case DMA_TRANSFER_LLI:\r
+             value |= addressingType << 24;\r
+             break;\r
+        case DMA_TRANSFER_RELOAD:\r
+        case DMA_TRANSFER_CONTIGUOUS:\r
+             value |= AT91C_SRC_DSCR | addressingType << 24 | 1<<31;\r
+             break;\r
+    }             \r
+    AT91C_BASE_HDMA->HDMA_CH[channel].HDMA_CTRLB = value;\r
+    \r
+    if(transferMode == DMA_TRANSFER_RELOAD || transferMode == DMA_TRANSFER_CONTIGUOUS){\r
+        value = AT91C_BASE_HDMA->HDMA_CH[channel].HDMA_CFG;\r
+        value &= ~ (AT91C_SRC_REP);\r
+        // When automatic mode is activated, the source address and the control register are reloaded from previous transfer.\r
+        if(transferMode == DMA_TRANSFER_RELOAD) {\r
+            value |= AT91C_SRC_REP;\r
+        }\r
+        AT91C_BASE_HDMA->HDMA_CH[channel].HDMA_CFG = value;\r
+    }\r
+    else {\r
+        AT91C_BASE_HDMA->HDMA_CH[channel].HDMA_CFG = 0;\r
+    }\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Set DMA transfer mode for destination used by a HDMA channel.\r
+/// \param channel Particular channel number.\r
+/// \param transferMode Transfer buffer mode (single, LLI, reload or contiguous)\r
+/// \param addressingType Type of addrassing mode\r
+///                       0 : incrementing, 1: decrementing, 2: fixed.\r
+//-----------------------------------------------------------------------------\r
+void DMA_SetDestBufferMode(unsigned char channel, \r
+                             unsigned char transferMode,\r
+                             unsigned char addressingType)\r
+{\r
+    unsigned int value;\r
+    \r
+    ASSERT(channel < DMA_CHANNEL_NUM, "this channel does not exist");\r
+    \r
+    value = AT91C_BASE_HDMA->HDMA_CH[channel].HDMA_CTRLB;\r
+    value &= ~ (AT91C_DST_DSCR | AT91C_DST_INCR);\r
+    \r
+    switch(transferMode){\r
+        case DMA_TRANSFER_SINGLE:\r
+        case DMA_TRANSFER_RELOAD:\r
+        case DMA_TRANSFER_CONTIGUOUS:\r
+             value |= AT91C_DST_DSCR | addressingType << 24;\r
+             break;\r
+        case DMA_TRANSFER_LLI:\r
+             value |= addressingType << 24;\r
+             break;\r
+    }             \r
+    AT91C_BASE_HDMA->HDMA_CH[channel].HDMA_CTRLB = value;\r
+    if(transferMode == DMA_TRANSFER_RELOAD || transferMode == DMA_TRANSFER_CONTIGUOUS){\r
+        value = AT91C_BASE_HDMA->HDMA_CH[channel].HDMA_CFG;\r
+        value &= ~ (AT91C_DST_REP);\r
+        // When automatic mode is activated, the source address and the control register are reloaded from previous transfer.\r
+        if(transferMode == DMA_TRANSFER_RELOAD) {\r
+            value |= AT91C_DST_REP;\r
+        }\r
+        AT91C_BASE_HDMA->HDMA_CH[channel].HDMA_CFG = value;\r
+    }\r
+    else {\r
+        AT91C_BASE_HDMA->HDMA_CH[channel].HDMA_CFG = 0;\r
+    }\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Set DMA configuration registe used by a HDMA channel.\r
+/// \param channel Particular channel number.\r
+/// \param value configuration value.\r
+//------------------------------------------------------------------------------\r
+void DMA_SetConfiguration(unsigned char channel, unsigned int value)\r
+{\r
+    ASSERT(channel < DMA_CHANNEL_NUM, "this channel does not exist");\r
+    AT91C_BASE_HDMA->HDMA_CH[channel].HDMA_CFG = value;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Set DMA source PIP configuration used by a HDMA channel.\r
+/// \param channel Particular channel number.\r
+/// \param pipHole stop on done mode.\r
+/// \param pipBoundary lock mode.\r
+//------------------------------------------------------------------------------\r
+void DMA_SPIPconfiguration(unsigned char channel, \r
+                           unsigned int pipHole, \r
+                           unsigned int pipBoundary)\r
+                     \r
+{\r
+    unsigned int value;\r
+    ASSERT(channel < DMA_CHANNEL_NUM, "this channel does not exist");\r
+    value = AT91C_BASE_HDMA->HDMA_CH[channel].HDMA_CTRLB;\r
+    value &= ~ (AT91C_SRC_PIP);\r
+    value |= AT91C_SRC_PIP;\r
+    AT91C_BASE_HDMA->HDMA_CH[channel].HDMA_CTRLB = value;\r
+    AT91C_BASE_HDMA->HDMA_CH[channel].HDMA_SPIP = (pipHole + 1) | pipBoundary <<16;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Set DMA destination PIP configuration used by a HDMA channel.\r
+/// \param channel Particular channel number.\r
+/// \param pipHole stop on done mode.\r
+/// \param pipBoundary lock mode.\r
+//------------------------------------------------------------------------------\r
+void DMA_DPIPconfiguration(unsigned char channel, \r
+                           unsigned int pipHole, \r
+                           unsigned int pipBoundary)\r
+                     \r
+{\r
+    unsigned int value;\r
+    ASSERT(channel < DMA_CHANNEL_NUM, "this channel does not exist");\r
+    value = AT91C_BASE_HDMA->HDMA_CH[channel].HDMA_CTRLB;\r
+    value &= ~ (AT91C_DST_PIP);\r
+    value |= AT91C_DST_PIP;\r
+    AT91C_BASE_HDMA->HDMA_CH[channel].HDMA_CTRLB = value;\r
+    AT91C_BASE_HDMA->HDMA_CH[channel].HDMA_DPIP = (pipHole + 1) | pipBoundary <<16;\r
+}\r
+\r

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/dma/dma.h b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/dma/dma.h
new file mode 100644 (file)
index 0000000..0bd46f8
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/dma/dma.h
@@ -0,0 +1,171 @@
+/* ----------------------------------------------------------------------------\r
+ *         ATMEL Microcontroller Software Support  -  ROUSSET  -\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2006, Atmel Corporation\r
+\r
+ * All rights reserved.\r
+ * \r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ * \r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaiimer below.\r
+ * \r
+ * - Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the disclaimer below in the documentation and/or\r
+ * other materials provided with the distribution. \r
+ * \r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission. \r
+ * \r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+//------------------------------------------------------------------------------\r
+/// \dir\r
+/// !Purpose\r
+/// \r
+/// Interface for configuration the %DMA controller(DMAC).\r
+///\r
+/// !Usage\r
+///\r
+/// -# Enable or disable the a DMAC controller with \r
+///    DMA_Enable() and or DMA_Disable().\r
+/// -# Enable or disable %Dma interrupt using DMA_EnableIt()\r
+///    or DMA_DisableIt().\r
+/// -# Get %Dma interrupt status by DMA_GetStatus().\r
+/// -# Enable or disable specified %Dma channel with \r
+///    DMA_EnableChannel() or DMA_DisableChannel().\r
+/// -# Get %Dma channel status by DMA_GetChannelStatus().\r
+/// -# Configure source and/or destination start address with\r
+///    DMA_SetSourceAddr() and/or DMA_SetDestAddr().\r
+/// -# Set %Dma descriptor address using DMA_SetDescriptorAddr().\r
+/// -# Set source transfer buffer size with DMA_SetSourceBufferSize().\r
+/// -# Configure source and/or destination transfer mode with\r
+///    DMA_SetSourceBufferMode() and/or DMA_SetDestBufferMode().\r
+/// -# Configure source and/or destination Picture-In-Picutre \r
+///    mode with DMA_SPIPconfiguration() and/or DMA_DPIPconfiguration().\r
+//------------------------------------------------------------------------------\r
+\r
+#ifndef DMA_H\r
+#define DMA_H\r
+\r
+#include <board.h>\r
+\r
+//------------------------------------------------------------------------------\r
+//         Definitions\r
+//------------------------------------------------------------------------------\r
+#define DMA_CHANNEL_0            0\r
+#define DMA_CHANNEL_1            1\r
+#define DMA_CHANNEL_2            2\r
+#define DMA_CHANNEL_3            3\r
+#define DMA_CHANNEL_4            4\r
+#define DMA_CHANNEL_5            5\r
+#define DMA_CHANNEL_6            6\r
+#define DMA_CHANNEL_7            7\r
+\r
+#if defined(CHIP_DMA_CHANNEL_NUM)\r
+#define DMA_CHANNEL_NUM      CHIP_DMA_CHANNEL_NUM\r
+#endif\r
+\r
+#define DMA_TRANSFER_SINGLE      0\r
+#define DMA_TRANSFER_LLI         1  \r
+#define DMA_TRANSFER_RELOAD      2\r
+#define DMA_TRANSFER_CONTIGUOUS  3\r
+\r
+\r
+#define DMA_ENA                  (1 << 0)\r
+#define DMA_DIS                  (1 << 0)\r
+#define DMA_SUSP                 (1 << 8)\r
+#define DMA_KEEPON               (1 << 24)\r
+\r
+#define DMA_BTC                  (1 << 0)\r
+#define DMA_CBTC                 (1 << 8)\r
+#define DMA_ERR                  (1 << 16)\r
+\r
+#if defined(at91sam9m10) || defined(at91sam9m11) || defined(at91sam3u4)\r
+    #define AT91C_SRC_DSCR AT91C_HDMA_SRC_DSCR\r
+    #define AT91C_DST_DSCR AT91C_HDMA_DST_DSCR\r
+    #define AT91C_SRC_INCR AT91C_HDMA_SRC_ADDRESS_MODE\r
+    #define AT91C_DST_INCR AT91C_HDMA_DST_ADDRESS_MODE\r
+    #define AT91C_SRC_PER  AT91C_HDMA_SRC_PER\r
+    #define AT91C_DST_PER  AT91C_HDMA_DST_PER\r
+    #define AT91C_SRC_REP  AT91C_HDMA_SRC_REP\r
+    #define AT91C_DST_REP  AT91C_HDMA_DST_REP\r
+    #define AT91C_SRC_PIP  AT91C_HDMA_SRC_PIP\r
+    #define AT91C_DST_PIP  AT91C_HDMA_DST_PIP\r
+    \r
+    #define AT91C_BTC             (0xFF <<  0) \r
+    #define AT91C_CBTC            (0xFF <<  8) \r
+    #define AT91C_ERR             (0xFF << 16) \r
+#endif    \r
+\r
+//------------------------------------------------------------------------------\r
+//         Exported functions\r
+//------------------------------------------------------------------------------\r
+\r
+extern void DMA_Config(unsigned int flag);\r
+\r
+extern void DMA_Enable(void);\r
+\r
+extern void DMA_Disable(void);\r
+\r
+extern void DMA_EnableChannel(unsigned int channel);\r
+\r
+extern void DMA_DisableChannel(unsigned int channel);\r
+\r
+extern void DMA_KeeponChannel(unsigned int channel);\r
+\r
+extern void DMA_ClearAutoMode(unsigned int channel);\r
+\r
+extern unsigned int DMA_GetChannelStatus(void);\r
+\r
+extern unsigned int DMA_GetStatus(void);\r
+\r
+extern unsigned int DMA_GetInterruptMask(void);\r
+\r
+extern unsigned int DMA_GetMaskedStatus(void);\r
+\r
+extern void DMA_EnableIt (unsigned int flag);\r
+\r
+extern void DMA_DisableIt (unsigned int flag);\r
+\r
+extern void DMA_SetSourceAddr(unsigned char channel, unsigned int address);\r
+\r
+extern void DMA_SetDestinationAddr(unsigned char channel, unsigned int address);\r
+\r
+extern void DMA_SetDescriptorAddr(unsigned char channel, unsigned int address);\r
+\r
+extern void DMA_SetSourceBufferSize(unsigned char channel,\r
+                             unsigned int size, \r
+                             unsigned char sourceWidth, \r
+                             unsigned char desDMAdth,\r
+                             unsigned char done);\r
+\r
+extern void DMA_SetSourceBufferMode(unsigned char channel, \r
+                             unsigned char transferMode,\r
+                             unsigned char addressingType);\r
+                             \r
+extern void DMA_SetDestBufferMode(unsigned char channel, \r
+                             unsigned char transferMode,\r
+                             unsigned char addressingType);\r
+                             \r
+extern void DMA_SetConfiguration(unsigned char channel, unsigned int value);\r
+\r
+extern void DMA_SPIPconfiguration(unsigned char channel, \r
+                     unsigned int pipHole, unsigned int pipBoundary);\r
+\r
+extern void DMA_DPIPconfiguration(unsigned char channel, \r
+                     unsigned int pipHole, unsigned int pipBoundary);\r
+\r
+#endif //#ifndef DMA_H\r

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/eefc/eefc.c b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/eefc/eefc.c
new file mode 100644 (file)
index 0000000..4ca75f8
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/eefc/eefc.c
@@ -0,0 +1,274 @@
+/* ----------------------------------------------------------------------------\r
+ *         ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2009, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+ \r
+//------------------------------------------------------------------------------\r
+//         Headers\r
+//------------------------------------------------------------------------------\r
+\r
+#include <board.h>\r
+#include "eefc.h"\r
+\r
+#if !defined (CHIP_FLASH_EEFC)\r
+#error eefc not supported\r
+#endif\r
+\r
+#include <utility/assert.h>\r
+#include <utility/trace.h>\r
+\r
+//------------------------------------------------------------------------------\r
+//         Global functions\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+/// Enables the flash ready interrupt source on the EEFC peripheral.\r
+/// \param pEfc  Pointer to an AT91S_EFC structure.\r
+//------------------------------------------------------------------------------\r
+void EFC_EnableFrdyIt(AT91S_EFC *pEfc)\r
+{\r
+    pEfc->EFC_FMR |= AT91C_EFC_FRDY;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Disables the flash ready interrupt source on the EEFC peripheral.\r
+/// \param pEfc  Pointer to an AT91S_EFC structure.\r
+//------------------------------------------------------------------------------\r
+void EFC_DisableFrdyIt(AT91S_EFC *pEfc)\r
+{\r
+    pEfc->EFC_FMR &= ~AT91C_EFC_FRDY;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Translates the given address page and offset values. The resulting\r
+/// values are stored in the provided variables if they are not null.\r
+/// \param ppEfc  Pointer to target EFC peripheral.\r
+/// \param address  Address to translate.\r
+/// \param pPage  First page accessed.\r
+/// \param pOffset  Byte offset in first page.\r
+//------------------------------------------------------------------------------\r
+void EFC_TranslateAddress(\r
+    AT91S_EFC **ppEfc,\r
+    unsigned int address,\r
+    unsigned short *pPage,\r
+    unsigned short *pOffset)\r
+{\r
+    AT91S_EFC *pEfc;\r
+    unsigned short page;\r
+    unsigned short offset;\r
+    \r
+#if defined(AT91C_BASE_EFC1)\r
+    SANITY_CHECK(address >= AT91C_IFLASH);\r
+    if (address >= AT91C_IFLASH1) {\r
+        SANITY_CHECK(address <= (AT91C_IFLASH1 + AT91C_IFLASH1_SIZE));    \r
+    }\r
+    else {\r
+        SANITY_CHECK(address <= (AT91C_IFLASH + AT91C_IFLASH_SIZE));\r
+    }\r
+#else\r
+    SANITY_CHECK(address >= AT91C_IFLASH);\r
+    SANITY_CHECK(address <= (AT91C_IFLASH + AT91C_IFLASH_SIZE));\r
+#endif\r
+\r
+    pEfc = AT91C_BASE_EFC;\r
+    page = (address - AT91C_IFLASH) / AT91C_IFLASH_PAGE_SIZE;\r
+    offset = (address - AT91C_IFLASH) % AT91C_IFLASH_PAGE_SIZE;\r
+    \r
+#if defined(AT91C_BASE_EFC1)\r
+    if (address >= AT91C_IFLASH1) {\r
+        pEfc = AT91C_BASE_EFC1;\r
+        page = (address - AT91C_IFLASH1) / AT91C_IFLASH1_PAGE_SIZE;\r
+        offset = (address - AT91C_IFLASH1) % AT91C_IFLASH1_PAGE_SIZE;\r
+    }\r
+#endif\r
+   \r
+    TRACE_DEBUG("Translated 0x%08X to page=%d and offset=%d\n\r",\r
+              address, page, offset);\r
+\r
+    // Store values\r
+    if (ppEfc) {\r
+        *ppEfc = pEfc;\r
+    }\r
+    if (pPage) {\r
+\r
+        *pPage = page;\r
+    }\r
+    if (pOffset) {\r
+\r
+        *pOffset = offset;\r
+    }\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Computes the address of a flash access given the page and offset.\r
+/// \param pEfc  Pointer to an AT91S_EFC structure.\r
+/// \param page  Page number.\r
+/// \param offset  Byte offset inside page.\r
+/// \param pAddress  Computed address (optional).\r
+//------------------------------------------------------------------------------\r
+void EFC_ComputeAddress(\r
+    AT91S_EFC *pEfc,\r
+    unsigned short page,\r
+    unsigned short offset,\r
+    unsigned int *pAddress)\r
+{\r
+    unsigned int address;\r
+    SANITY_CHECK(pEfc);\r
+    SANITY_CHECK(page <= AT91C_IFLASH_NB_OF_PAGES);\r
+    SANITY_CHECK(offset < AT91C_IFLASH_PAGE_SIZE);\r
+\r
+    // Compute address\r
+    address = AT91C_IFLASH + page * AT91C_IFLASH_PAGE_SIZE + offset;\r
+#if defined(AT91C_BASE_EFC1)\r
+    if (pEfc == AT91C_BASE_EFC1) {\r
+        address = AT91C_IFLASH1 + page * AT91C_IFLASH1_PAGE_SIZE + offset;\r
+    }\r
+#endif    \r
+\r
+    // Store result\r
+    if (pAddress) {\r
+\r
+        *pAddress = address;\r
+    }\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Starts the executing the given command on the EEFC. This function returns\r
+/// as soon as the command is started. It does NOT set the FMCN field automatically.\r
+/// \param pEfc  Pointer to an AT91S_EFC structure.\r
+/// \param command  Command to execute.\r
+/// \param argument  Command argument (should be 0 if not used).\r
+//------------------------------------------------------------------------------\r
+#if defined(flash) || defined (USE_FLASH)\r
+   #ifdef __ICCARM__\r
+__ramfunc\r
+   #else\r
+__attribute__ ((section (".ramfunc")))\r
+   #endif\r
+#endif\r
+void EFC_StartCommand(AT91S_EFC *pEfc, unsigned char command, unsigned short argument)\r
+{\r
+    // Check command & argument\r
+    switch (command) {\r
+\r
+        case AT91C_EFC_FCMD_WP:\r
+        case AT91C_EFC_FCMD_WPL:\r
+        case AT91C_EFC_FCMD_EWP: \r
+        case AT91C_EFC_FCMD_EWPL:\r
+        case AT91C_EFC_FCMD_EPL:\r
+        case AT91C_EFC_FCMD_EPA:\r
+        case AT91C_EFC_FCMD_SLB:\r
+        case AT91C_EFC_FCMD_CLB:\r
+            ASSERT(argument < AT91C_IFLASH_NB_OF_PAGES,\r
+                   "-F- Embedded flash has only %d pages\n\r",\r
+                   AT91C_IFLASH_NB_OF_PAGES);\r
+            break;\r
+\r
+        case AT91C_EFC_FCMD_SFB:\r
+        case AT91C_EFC_FCMD_CFB:\r
+            ASSERT(argument < CHIP_EFC_NUM_GPNVMS, "-F- Embedded flash has only %d GPNVMs\n\r", CHIP_EFC_NUM_GPNVMS);\r
+            break;\r
+\r
+        case AT91C_EFC_FCMD_GETD:\r
+        case AT91C_EFC_FCMD_EA:\r
+        case AT91C_EFC_FCMD_GLB:\r
+        case AT91C_EFC_FCMD_GFB:\r
+#ifdef AT91C_EFC_FCMD_STUI\r
+        case AT91C_EFC_FCMD_STUI:\r
+#endif\r
+            ASSERT(argument == 0, "-F- Argument is meaningless for the given command.\n\r");\r
+            break;\r
+\r
+        default: ASSERT(0, "-F- Unknown command %d\n\r", command);\r
+    }\r
+\r
+    // Start commandEmbedded flash \r
+    ASSERT((pEfc->EFC_FSR & AT91C_EFC_FRDY) == AT91C_EFC_FRDY, "-F- EEFC is not ready\n\r");\r
+    pEfc->EFC_FCR = (0x5A << 24) | (argument << 8) | command;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Performs the given command and wait until its completion (or an error).\r
+/// Returns 0 if successful; otherwise returns an error code.\r
+/// \param pEfc  Pointer to an AT91S_EFC structure.\r
+/// \param command  Command to perform.\r
+/// \param argument  Optional command argument.\r
+//------------------------------------------------------------------------------\r
+#if defined(flash) || defined (USE_FLASH)\r
+   #ifdef __ICCARM__\r
+__ramfunc\r
+   #else\r
+__attribute__ ((section (".ramfunc")))\r
+   #endif\r
+#endif\r
+unsigned char EFC_PerformCommand(AT91S_EFC *pEfc, unsigned char command, unsigned short argument)\r
+{\r
+    unsigned int status;\r
+\r
+#ifdef CHIP_FLASH_IAP_ADDRESS\r
+    // Pointer on IAP function in ROM\r
+    static void (*IAP_PerformCommand)(unsigned int);\r
+    IAP_PerformCommand = (void (*)(unsigned int)) *((unsigned int *) CHIP_FLASH_IAP_ADDRESS);\r
+\r
+    // Check if IAP function is implemented (opcode in SWI != 'b' or 'ldr') */\r
+    if ((((((unsigned long) IAP_PerformCommand >> 24) & 0xFF) != 0xEA) &&\r
+        (((unsigned long) IAP_PerformCommand >> 24) & 0xFF) != 0xE5)) {\r
+\r
+        IAP_PerformCommand((0x5A << 24) | (argument << 8) | command);\r
+        return (pEfc->EFC_FSR & (AT91C_EFC_LOCKE | AT91C_EFC_FCMDE));\r
+    }\r
+#endif\r
+\r
+    pEfc->EFC_FCR = (0x5A << 24) | (argument << 8) | command;\r
+    do {\r
+\r
+        status = pEfc->EFC_FSR;\r
+    }\r
+    while ((status & AT91C_EFC_FRDY) != AT91C_EFC_FRDY);\r
+\r
+    return (status & (AT91C_EFC_LOCKE | AT91C_EFC_FCMDE));\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Returns the current status of the EEFC. Keep in mind that this function clears\r
+/// the value of some status bits (LOCKE, PROGE).\r
+/// \param pEfc  Pointer to an AT91S_EFC structure.\r
+//------------------------------------------------------------------------------\r
+unsigned int EFC_GetStatus(AT91S_EFC *pEfc)\r
+{\r
+    return pEfc->EFC_FSR;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Returns the result of the last executed command.\r
+/// \param pEfc  Pointer to an AT91S_EFC structure.\r
+//------------------------------------------------------------------------------\r
+unsigned int EFC_GetResult(AT91S_EFC *pEfc) {\r
+\r
+    return pEfc->EFC_FRR;\r
+}\r
+\r

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/eefc/eefc.h b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/eefc/eefc.h
new file mode 100644 (file)
index 0000000..a5ebd09
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/eefc/eefc.h
@@ -0,0 +1,147 @@
+/* ----------------------------------------------------------------------------\r
+ *         ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2009, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+//------------------------------------------------------------------------------\r
+/// \unit\r
+///\r
+/// !Purpose\r
+///\r
+/// Interface for configuration the Enhanced Embedded Flash Controller (EEFC)\r
+/// peripheral.\r
+///\r
+/// !Usage\r
+///\r
+/// -# Enable/disable %flash ready interrupt sources using EFC_EnableFrdyIt() \r
+///    and EFC_DisableFrdyIt().\r
+/// -# Translates the given address into which EEFC, page and offset values \r
+///    for difference density %flash memory using EFC_TranslateAddress().\r
+/// -# Computes the address of a %flash access given the EFC, page and offset \r
+///    for difference density %flash memory using EFC_ComputeAddress().\r
+/// -# Start the executing command with EFC_StartCommand()\r
+/// -# Retrieve the current status of the EFC using EFC_GetStatus().\r
+/// -# Retrieve the result of the last executed command with EFC_GetResult().\r
+//------------------------------------------------------------------------------\r
+#ifndef EEFC_H\r
+#define EEFC_H\r
+\r
+//------------------------------------------------------------------------------\r
+//         Headers\r
+//------------------------------------------------------------------------------\r
+\r
+#include <board.h>\r
+\r
+#if !defined (CHIP_FLASH_EEFC)\r
+#error eefc not supported\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+//         Constants\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+//         Types\r
+//------------------------------------------------------------------------------\r
+\r
+// Needed when EEFC is integrated in MC.\r
+#if !defined(AT91C_BASE_EFC) && defined(AT91C_BASE_MC)\r
+typedef struct _AT91S_EFC {\r
+       AT91_REG         EFC_FMR;       // EFC Flash Mode Register\r
+       AT91_REG         EFC_FCR;       // EFC Flash Command Register\r
+       AT91_REG         EFC_FSR;       // EFC Flash Status Register\r
+       AT91_REG         EFC_FRR;       // EFC Flash Result Register\r
+       AT91_REG         EFC_FVR;       // EFC Flash Version Register\r
+} AT91S_EFC, *AT91PS_EFC;\r
+\r
+#define AT91C_EFC_FRDY              AT91C_MC_FRDY\r
+#define AT91C_EFC_FWS               AT91C_MC_FWS\r
+#define AT91C_EFC_FWS_0WS           AT91C_MC_FWS_0WS\r
+#define AT91C_EFC_FWS_1WS           AT91C_MC_FWS_1WS\r
+#define AT91C_EFC_FWS_2WS           AT91C_MC_FWS_2WS\r
+#define AT91C_EFC_FWS_3WS           AT91C_MC_FWS_3WS\r
+#define AT91C_EFC_FCMD              AT91C_MC_FCMD\r
+#define AT91C_EFC_FCMD_GETD         AT91C_MC_FCMD_GETD\r
+#define AT91C_EFC_FCMD_WP           AT91C_MC_FCMD_WP  \r
+#define AT91C_EFC_FCMD_WPL          AT91C_MC_FCMD_WPL \r
+#define AT91C_EFC_FCMD_EWP          AT91C_MC_FCMD_EWP \r
+#define AT91C_EFC_FCMD_EWPL         AT91C_MC_FCMD_EWPL\r
+#define AT91C_EFC_FCMD_EA           AT91C_MC_FCMD_EA  \r
+#define AT91C_EFC_FCMD_EPL          AT91C_MC_FCMD_EPL \r
+#define AT91C_EFC_FCMD_EPA          AT91C_MC_FCMD_EPA \r
+#define AT91C_EFC_FCMD_SLB          AT91C_MC_FCMD_SLB \r
+#define AT91C_EFC_FCMD_CLB          AT91C_MC_FCMD_CLB \r
+#define AT91C_EFC_FCMD_GLB          AT91C_MC_FCMD_GLB \r
+#define AT91C_EFC_FCMD_SFB          AT91C_MC_FCMD_SFB \r
+#define AT91C_EFC_FCMD_CFB          AT91C_MC_FCMD_CFB \r
+#define AT91C_EFC_FCMD_GFB          AT91C_MC_FCMD_GFB \r
+#define AT91C_EFC_FARG              AT91C_MC_FARG     \r
+#define AT91C_EFC_FKEY              AT91C_MC_FKEY     \r
+#define AT91C_EFC_FRDY_S            AT91C_MC_FRDY_S   \r
+#define AT91C_EFC_FCMDE             AT91C_MC_FCMDE   \r
+#define AT91C_EFC_LOCKE             AT91C_MC_LOCKE    \r
+#define AT91C_EFC_FVALUE            AT91C_MC_FVALUE   \r
+\r
+#define AT91C_BASE_EFC              (AT91_CAST(AT91PS_EFC)     0xFFFFFF60)    \r
+\r
+#endif //#if !defined(AT91C_BASE_EFC) && defined(AT91C_BASE_MC)\r
+\r
+//------------------------------------------------------------------------------\r
+//         Functions\r
+//------------------------------------------------------------------------------\r
+\r
+extern void EFC_EnableFrdyIt(AT91S_EFC *pEfc);\r
+\r
+extern void EFC_DisableFrdyIt(AT91S_EFC *pEfc);\r
+\r
+extern void EFC_TranslateAddress(\r
+    AT91S_EFC **ppEfc,\r
+    unsigned int address,\r
+    unsigned short *pPage,\r
+    unsigned short *pOffset);\r
+\r
+extern void EFC_ComputeAddress(\r
+    AT91S_EFC *pEfc,\r
+    unsigned short page,\r
+    unsigned short offset,\r
+    unsigned int *pAddress);\r
+\r
+extern void EFC_StartCommand(\r
+    AT91S_EFC *pEfc,\r
+    unsigned char command,\r
+    unsigned short argument);\r
+\r
+extern unsigned char EFC_PerformCommand(\r
+    AT91S_EFC *pEfc,\r
+    unsigned char command,\r
+    unsigned short argument);\r
+\r
+extern unsigned int EFC_GetStatus(AT91S_EFC *pEfc);\r
+\r
+extern unsigned int EFC_GetResult(AT91S_EFC *pEfc);\r
+\r
+#endif //#ifndef EEFC_H\r
+\r

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/efc/efc.c b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/efc/efc.c
new file mode 100644 (file)
index 0000000..c12a60a
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/efc/efc.c
@@ -0,0 +1,395 @@
+/* ----------------------------------------------------------------------------\r
+ *         ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+//------------------------------------------------------------------------------\r
+//         Headers\r
+//------------------------------------------------------------------------------\r
+\r
+#include "efc.h"\r
+\r
+#ifdef BOARD_FLASH_EFC\r
+\r
+#include <utility/assert.h>\r
+#include <utility/trace.h>\r
+\r
+//------------------------------------------------------------------------------\r
+//         Local definitions\r
+//------------------------------------------------------------------------------\r
+\r
+// Round a number to the nearest integral value (number must have been\r
+// multiplied by 10, e.g. to round 10.3 enter 103).\r
+#define ROUND(n)    ((((n) % 10) >= 5) ? (((n) / 10) + 1) : ((n) / 10))\r
+\r
+// Returns the FMCN field value when manipulating lock bits, given MCK.\r
+#if defined(at91sam7a3)\r
+    #define FMCN_BITS(mck)      (ROUND((mck) / 1000000) << 16)\r
+#else\r
+    #define FMCN_BITS(mck)      (ROUND((mck) / 100000) << 16)\r
+#endif\r
+\r
+// Returns the FMCN field value when manipulating the rest of the flash.\r
+#define FMCN_FLASH(mck)         ((((mck) / 2000000) * 3) << 16)\r
+\r
+//------------------------------------------------------------------------------\r
+//         Local functions\r
+//------------------------------------------------------------------------------\r
+\r
+/// Master clock frequency, used to infer the value of the FMCN field.\r
+#ifdef MCK_VARIABLE\r
+static unsigned int lMck = 0;\r
+#else\r
+static const unsigned int lMck = BOARD_MCK;\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+//         Global functions\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+/// Sets the system master clock so the FMCN field of the EFC(s) can be\r
+/// programmed properly.\r
+/// \param mck  Master clock frequency in Hz.\r
+//------------------------------------------------------------------------------\r
+void EFC_SetMasterClock(unsigned int mck)\r
+{\r
+#ifdef MCK_VARIABLE\r
+    lMck = mck;\r
+#else\r
+    ASSERT(mck == BOARD_MCK, "-F- EFC has not been configured to work at a freq. different from %dMHz", BOARD_MCK);\r
+#endif\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Enables the given interrupt sources on an EFC peripheral.\r
+/// \param pEfc  Pointer to an AT91S_EFC structure.\r
+/// \param sources  Interrupt sources to enable.\r
+//------------------------------------------------------------------------------\r
+void EFC_EnableIt(AT91S_EFC *pEfc, unsigned int sources)\r
+{\r
+    SANITY_CHECK(pEfc);\r
+    SANITY_CHECK((sources & ~0x0000000D) == 0);\r
+\r
+    pEfc->EFC_FMR |= sources;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Disables the given interrupt sources on an EFC peripheral.\r
+/// \param pEfc  Pointer to an AT91S_EFC structure.\r
+/// \param sources  Interrupt sources to disable.\r
+//------------------------------------------------------------------------------\r
+void EFC_DisableIt(AT91S_EFC *pEfc, unsigned int sources)\r
+{\r
+    SANITY_CHECK(pEfc);\r
+    SANITY_CHECK((sources & ~(AT91C_MC_FRDY | AT91C_MC_LOCKE | AT91C_MC_PROGE)) == 0);\r
+\r
+    pEfc->EFC_FMR &= ~sources;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Enables or disable the "Erase before programming" feature of an EFC.\r
+/// \param pEfc  Pointer to an AT91S_EFC structure.\r
+/// \param enable  If 1, the feature is enabled; otherwise it is disabled.\r
+//------------------------------------------------------------------------------\r
+void EFC_SetEraseBeforeProgramming(AT91S_EFC *pEfc, unsigned char enable)\r
+{\r
+    SANITY_CHECK(pEfc);\r
+\r
+    if (enable) {\r
+\r
+        pEfc->EFC_FMR &= ~AT91C_MC_NEBP;\r
+    }\r
+    else {\r
+\r
+        pEfc->EFC_FMR |= AT91C_MC_NEBP;\r
+    }\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Translates the given address into EFC, page and offset values. The resulting\r
+/// values are stored in the provided variables if they are not null.\r
+/// \param address  Address to translate.\r
+/// \param ppEfc  Pointer to target EFC peripheral.\r
+/// \param pPage  First page accessed.\r
+/// \param pOffset  Byte offset in first page.\r
+//------------------------------------------------------------------------------\r
+void EFC_TranslateAddress(\r
+    unsigned int address,\r
+    AT91S_EFC **ppEfc,\r
+    unsigned short *pPage,\r
+    unsigned short *pOffset)\r
+{\r
+    AT91S_EFC *pEfc;\r
+    unsigned short page;\r
+    unsigned short offset;\r
+\r
+    SANITY_CHECK(address >= AT91C_IFLASH);\r
+    SANITY_CHECK(address <= (AT91C_IFLASH + AT91C_IFLASH_SIZE));\r
+\r
+#if defined(AT91C_BASE_EFC0)\r
+    if (address >= (AT91C_IFLASH + AT91C_IFLASH_SIZE / 2)) {\r
+\r
+        pEfc = AT91C_BASE_EFC1;\r
+        page = (address - AT91C_IFLASH - AT91C_IFLASH_SIZE / 2) / AT91C_IFLASH_PAGE_SIZE;\r
+        offset = (address - AT91C_IFLASH - AT91C_IFLASH_SIZE / 2) % AT91C_IFLASH_PAGE_SIZE;\r
+    }\r
+    else {\r
+\r
+        pEfc = AT91C_BASE_EFC0;\r
+        page = (address - AT91C_IFLASH) / AT91C_IFLASH_PAGE_SIZE;\r
+        offset = (address - AT91C_IFLASH) % AT91C_IFLASH_PAGE_SIZE;\r
+    }\r
+#else\r
+    pEfc = AT91C_BASE_EFC;\r
+    page = (address - AT91C_IFLASH) / AT91C_IFLASH_PAGE_SIZE;\r
+    offset = (address - AT91C_IFLASH) % AT91C_IFLASH_PAGE_SIZE;\r
+#endif\r
+    TRACE_DEBUG("Translated 0x%08X to EFC=0x%08X, page=%d and offset=%d\n\r",\r
+              address, (unsigned int) pEfc, page, offset);\r
+\r
+    // Store values\r
+    if (ppEfc) {\r
+\r
+        *ppEfc = pEfc;\r
+    }\r
+    if (pPage) {\r
+\r
+        *pPage = page;\r
+    }\r
+    if (pOffset) {\r
+\r
+        *pOffset = offset;\r
+    }\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Computes the address of a flash access given the EFC, page and offset.\r
+/// \param pEfc  Pointer to an AT91S_EFC structure.\r
+/// \param page  Page number.\r
+/// \param offset  Byte offset inside page.\r
+/// \param pAddress  Computed address (optional).\r
+//------------------------------------------------------------------------------\r
+void EFC_ComputeAddress(\r
+    AT91S_EFC *pEfc,\r
+    unsigned short page,\r
+    unsigned short offset,\r
+    unsigned int *pAddress)\r
+{\r
+    unsigned int address;\r
+\r
+    SANITY_CHECK(pEfc);\r
+#if defined(AT91C_BASE_EFC1)\r
+    SANITY_CHECK(page <= (AT91C_IFLASH_NB_OF_PAGES / 2));\r
+#else\r
+    SANITY_CHECK(page <= AT91C_IFLASH_NB_OF_PAGES);\r
+#endif\r
+    SANITY_CHECK(offset < AT91C_IFLASH_PAGE_SIZE);\r
+\r
+    // Compute address\r
+    address = AT91C_IFLASH + page * AT91C_IFLASH_PAGE_SIZE + offset;\r
+#if defined(AT91C_BASE_EFC1)\r
+    if (pEfc == AT91C_BASE_EFC1) {\r
+\r
+        address += AT91C_IFLASH_SIZE / 2;\r
+    }\r
+#endif\r
+\r
+    // Store result\r
+    if (pAddress) {\r
+\r
+        *pAddress = address;\r
+    }\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Starts the executing the given command on an EFC. This function returns\r
+/// as soon as the command is started. It does NOT set the FMCN field automatically.\r
+/// \param pEfc  Pointer to an AT91S_EFC structure.\r
+/// \param command  Command to execute.\r
+/// \param argument  Command argument (should be 0 if not used).\r
+//------------------------------------------------------------------------------\r
+#if defined(flash)\r
+   #ifdef __ICCARM__\r
+__ramfunc\r
+   #else\r
+__attribute__ ((section (".ramfunc")))\r
+   #endif\r
+#endif\r
+void EFC_StartCommand(\r
+    AT91S_EFC *pEfc,\r
+    unsigned char command,\r
+    unsigned short argument)\r
+{\r
+    SANITY_CHECK(pEfc);\r
+    ASSERT(lMck != 0, "-F- Master clock not set.\n\r");\r
+    \r
+    // Check command & argument\r
+    switch (command) {\r
+\r
+        case AT91C_MC_FCMD_PROG_AND_LOCK:\r
+            ASSERT(0, "-F- Write and lock command cannot be carried out.\n\r");\r
+            break;\r
+\r
+        case AT91C_MC_FCMD_START_PROG:\r
+        case AT91C_MC_FCMD_LOCK:\r
+        case AT91C_MC_FCMD_UNLOCK:\r
+            ASSERT(argument < AT91C_IFLASH_NB_OF_PAGES,\r
+                   "-F- Maximum number of pages is %d (argument was %d)\n\r",\r
+                   AT91C_IFLASH_NB_OF_PAGES,\r
+                   argument);\r
+            break;\r
+\r
+#if (EFC_NUM_GPNVMS > 0)\r
+        case AT91C_MC_FCMD_SET_GP_NVM:\r
+        case AT91C_MC_FCMD_CLR_GP_NVM:\r
+            ASSERT(argument < EFC_NUM_GPNVMS, "-F- A maximum of %d GPNVMs are available on the chip.\n\r", EFC_NUM_GPNVMS);\r
+            break;\r
+#endif\r
+\r
+        case AT91C_MC_FCMD_ERASE_ALL:\r
+\r
+#if !defined(EFC_NO_SECURITY_BIT)\r
+        case AT91C_MC_FCMD_SET_SECURITY:\r
+#endif\r
+            ASSERT(argument == 0, "-F- Argument is meaningless for the given command\n\r");\r
+            break;\r
+\r
+        default: ASSERT(0, "-F- Unknown command %d\n\r", command);\r
+    }\r
+\r
+    // Set FMCN\r
+    switch (command) {\r
+\r
+        case AT91C_MC_FCMD_LOCK:\r
+        case AT91C_MC_FCMD_UNLOCK:\r
+#if (EFC_NUM_GPNVMS > 0)\r
+        case AT91C_MC_FCMD_SET_GP_NVM:\r
+        case AT91C_MC_FCMD_CLR_GP_NVM:\r
+#endif\r
+#if !defined(EFC_NO_SECURITY_BIT)\r
+        case AT91C_MC_FCMD_SET_SECURITY:\r
+#endif\r
+            pEfc->EFC_FMR = (pEfc->EFC_FMR & ~AT91C_MC_FMCN) | FMCN_BITS(lMck);\r
+            break;\r
+\r
+        case AT91C_MC_FCMD_START_PROG:\r
+        case AT91C_MC_FCMD_ERASE_ALL:\r
+            pEfc->EFC_FMR = (pEfc->EFC_FMR & ~AT91C_MC_FMCN) | FMCN_FLASH(lMck);\r
+            break;\r
+    }\r
+\r
+    // Start command\r
+    ASSERT((pEfc->EFC_FSR & AT91C_MC_FRDY) != 0, "-F- Efc is not ready\n\r");\r
+    pEfc->EFC_FCR = (0x5A << 24) | (argument << 8) | command;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Performs the given command and wait until its completion (or an error).\r
+/// Returns 0 if successful; otherwise returns an error code.\r
+/// \param pEfc  Pointer to an AT91S_EFC structure.\r
+/// \param command  Command to perform.\r
+/// \param argument  Optional command argument.\r
+//------------------------------------------------------------------------------\r
+#if defined(flash)\r
+   #ifdef __ICCARM__\r
+__ramfunc\r
+   #else\r
+__attribute__ ((section (".ramfunc")))\r
+   #endif\r
+#endif\r
+unsigned char EFC_PerformCommand(\r
+    AT91S_EFC *pEfc,\r
+    unsigned char command,\r
+    unsigned short argument)\r
+{\r
+    unsigned int status;\r
+\r
+    // Set FMCN\r
+    switch (command) {\r
+\r
+        case AT91C_MC_FCMD_LOCK:\r
+        case AT91C_MC_FCMD_UNLOCK:\r
+#if (EFC_NUM_GPNVMS > 0)\r
+        case AT91C_MC_FCMD_SET_GP_NVM:\r
+        case AT91C_MC_FCMD_CLR_GP_NVM:\r
+#endif\r
+#if !defined(EFC_NO_SECURITY_BIT)\r
+        case AT91C_MC_FCMD_SET_SECURITY:\r
+#endif\r
+            pEfc->EFC_FMR = (pEfc->EFC_FMR & ~AT91C_MC_FMCN) | FMCN_BITS(lMck);\r
+            break;\r
+\r
+        case AT91C_MC_FCMD_START_PROG:\r
+        case AT91C_MC_FCMD_ERASE_ALL:\r
+            pEfc->EFC_FMR = (pEfc->EFC_FMR & ~AT91C_MC_FMCN) | FMCN_FLASH(lMck);\r
+            break;\r
+    }\r
+\r
+#ifdef BOARD_FLASH_IAP_ADDRESS\r
+    // Pointer on IAP function in ROM\r
+    static void (*IAP_PerformCommand)(unsigned int, unsigned int);\r
+    unsigned int index = 0;\r
+#ifdef AT91C_BASE_EFC1\r
+    if (pEfc == AT91C_BASE_EFC1) {\r
+\r
+        index = 1;\r
+    }\r
+#endif\r
+    IAP_PerformCommand = (void (*)(unsigned int, unsigned int)) *((unsigned int *) BOARD_FLASH_IAP_ADDRESS);\r
+\r
+    // Check if IAP function is implemented (opcode in SWI != 'b' or 'ldr') */\r
+    if ((((((unsigned long) IAP_PerformCommand >> 24) & 0xFF) != 0xEA) &&\r
+        (((unsigned long) IAP_PerformCommand >> 24) & 0xFF) != 0xE5)) {\r
+\r
+        IAP_PerformCommand(index, (0x5A << 24) | (argument << 8) | command);\r
+        return (pEfc->EFC_FSR & (AT91C_MC_LOCKE | AT91C_MC_PROGE));\r
+    }\r
+#endif\r
+\r
+    pEfc->EFC_FCR = (0x5A << 24) | (argument << 8) | command;\r
+    do {\r
+\r
+        status = pEfc->EFC_FSR;\r
+    }\r
+    while ((status & AT91C_MC_FRDY) == 0);\r
+\r
+    return (status & (AT91C_MC_PROGE | AT91C_MC_LOCKE));\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Returns the current status of an EFC. Keep in mind that this function clears\r
+/// the value of some status bits (LOCKE, PROGE).\r
+/// \param pEfc  Pointer to an AT91S_EFC structure.\r
+//------------------------------------------------------------------------------\r
+unsigned int EFC_GetStatus(AT91S_EFC *pEfc)\r
+{\r
+    return pEfc->EFC_FSR;\r
+}\r
+\r
+#endif //#ifdef BOARD_FLASH_EFC\r
+\r

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/efc/efc.h b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/efc/efc.h
new file mode 100644 (file)
index 0000000..ecf7a69
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/efc/efc.h
@@ -0,0 +1,147 @@
+/* ----------------------------------------------------------------------------\r
+ *         ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+//------------------------------------------------------------------------------\r
+/// \unit\r
+///\r
+/// !Purpose\r
+///\r
+/// Interface for configuration the Embedded Flash Controller (EFC) peripheral.\r
+///\r
+/// !Usage\r
+///\r
+/// -# Initialize system master clock of the EFC with EFC_SetMasterClock().\r
+/// -# Enable/disable interrupt sources using EFC_EnableIt() and EFC_DisableIt().\r
+/// -# Enables or disable the "Erase before programming" feature using \r
+///    EFC_SetEraseBeforeProgramming().\r
+/// -# Translates the given address into which EFC, page and offset values for \r
+///    difference density %flash memory using EFC_TranslateAddress().\r
+/// -# Computes the address of a %flash access given the EFC, page and offset \r
+///    for difference density %flash memory using EFC_ComputeAddress().\r
+/// -# Start the executing command with EFC_StartCommand()\r
+/// -# Retrieve the current status of the EFC using EFC_GetStatus().\r
+///\r
+//------------------------------------------------------------------------------\r
+#ifndef EFC_H\r
+#define EFC_H\r
+\r
+//------------------------------------------------------------------------------\r
+//         Headers\r
+//------------------------------------------------------------------------------\r
+\r
+#include <board.h>\r
+\r
+#ifdef BOARD_FLASH_EFC\r
+\r
+//------------------------------------------------------------------------------\r
+//         Constants\r
+//------------------------------------------------------------------------------\r
+\r
+/// Number of GPNVMs available on each chip.\r
+#if defined(at91sam7s16) || defined(at91sam7s161) || defined(at91sam7s32) \\r
+    || defined(at91sam7s321) || defined(at91sam7s64) || defined(at91sam7s128) \\r
+    || defined(at91sam7s256) || defined(at91sam7s512)\r
+\r
+    #define EFC_NUM_GPNVMS          2\r
+\r
+#elif defined(at91sam7se32) || defined(at91sam7se256) || defined(at91sam7se512) \\r
+      || defined(at91sam7x128) || defined(at91sam7x256) || defined(at91sam7x512) \\r
+      || defined(at91sam7xc128) || defined(at91sam7xc256) || defined(at91sam7xc512) \\r
+\r
+    #define EFC_NUM_GPNVMS          3\r
+\r
+#elif defined(at91sam7a3)\r
+\r
+    #define EFC_NUM_GPNVMS          0\r
+#endif\r
+\r
+// Missing FRDY bit for SAM7A3\r
+#if defined(at91sam7a3)\r
+    #define AT91C_MC_FRDY       (AT91C_MC_EOP | AT91C_MC_EOL)\r
+#endif\r
+\r
+// No security bit on SAM7A3\r
+#if defined(at91sam7a3)\r
+    #define EFC_NO_SECURITY_BIT\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+//         Types\r
+//------------------------------------------------------------------------------\r
+\r
+// For chips which do not define AT91S_EFC\r
+#if !defined(AT91C_BASE_EFC) && !defined(AT91C_BASE_EFC0)\r
+typedef struct _AT91S_EFC {\r
+\r
+    AT91_REG EFC_FMR;\r
+    AT91_REG EFC_FCR;\r
+    AT91_REG EFC_FSR;\r
+\r
+} AT91S_EFC, *AT91PS_EFC;\r
+       #define AT91C_BASE_EFC       (AT91_CAST(AT91PS_EFC)     0xFFFFFF60) \r
+#endif \r
+\r
+//------------------------------------------------------------------------------\r
+//         Functions\r
+//------------------------------------------------------------------------------\r
+\r
+extern void EFC_SetMasterClock(unsigned int mck);\r
+\r
+extern void EFC_EnableIt(AT91S_EFC *pEfc, unsigned int sources);\r
+\r
+extern void EFC_DisableIt(AT91S_EFC *pEfc, unsigned int sources);\r
+\r
+extern void EFC_SetEraseBeforeProgramming(AT91S_EFC *pEfc, unsigned char enable);\r
+\r
+extern void EFC_TranslateAddress(\r
+    unsigned int address,\r
+    AT91S_EFC **ppEfc,\r
+    unsigned short *pPage,\r
+    unsigned short *pOffset);\r
+\r
+extern void EFC_ComputeAddress(\r
+    AT91S_EFC *pEfc,\r
+    unsigned short page,\r
+    unsigned short offset,\r
+    unsigned int *pAddress);\r
+\r
+extern void EFC_StartCommand(\r
+    AT91S_EFC *pEfc,\r
+    unsigned char command,\r
+    unsigned short argument);\r
+\r
+extern unsigned char EFC_PerformCommand(\r
+    AT91S_EFC *pEfc,\r
+    unsigned char command,\r
+    unsigned short argument);\r
+\r
+extern unsigned int EFC_GetStatus(AT91S_EFC *pEfc);\r
+\r
+#endif //#ifdef BOARD_FLASH_EFC\r
+#endif //#ifndef EFC_H\r
+\r

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/emac/emac.c b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/emac/emac.c
new file mode 100644 (file)
index 0000000..93ba2d5
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/emac/emac.c
@@ -0,0 +1,832 @@
+/* ----------------------------------------------------------------------------\r
+ *         ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+//-----------------------------------------------------------------------------\r
+//         Headers\r
+//-----------------------------------------------------------------------------\r
+#include <board.h>\r
+#include "emac.h"\r
+#include <utility/trace.h>\r
+#include <utility/assert.h>\r
+#include <string.h>\r
+\r
+//------------------------------------------------------------------------------\r
+//         Definitions\r
+//------------------------------------------------------------------------------\r
+/// The buffer addresses written into the descriptors must be aligned so the\r
+/// last few bits are zero.  These bits have special meaning for the EMAC\r
+/// peripheral and cannot be used as part of the address.\r
+#define EMAC_ADDRESS_MASK   ((unsigned int)0xFFFFFFFC)\r
+#define EMAC_LENGTH_FRAME   ((unsigned int)0x0FFF)    /// Length of frame mask\r
+\r
+// receive buffer descriptor bits\r
+#define EMAC_RX_OWNERSHIP_BIT   (1 <<  0)\r
+#define EMAC_RX_WRAP_BIT        (1 <<  1)\r
+#define EMAC_RX_SOF_BIT         (1 << 14)\r
+#define EMAC_RX_EOF_BIT         (1 << 15)\r
+\r
+// Transmit buffer descriptor bits\r
+#define EMAC_TX_LAST_BUFFER_BIT (1 << 15)\r
+#define EMAC_TX_WRAP_BIT        (1 << 30)\r
+#define EMAC_TX_USED_BIT        (1 << 31)\r
+\r
+//-----------------------------------------------------------------------------\r
+// Circular buffer management\r
+//-----------------------------------------------------------------------------\r
+// Return count in buffer\r
+#define CIRC_CNT(head,tail,size) (((head) - (tail)) & ((size)-1))\r
+\r
+// Return space available, 0..size-1\r
+// We always leave one free char as a completely full buffer \r
+// has head == tail, which is the same as empty\r
+#define CIRC_SPACE(head,tail,size) CIRC_CNT((tail),((head)+1),(size))\r
+\r
+// Return count up to the end of the buffer.  \r
+// Carefully avoid accessing head and tail more than once,\r
+// so they can change underneath us without returning inconsistent results\r
+#define CIRC_CNT_TO_END(head,tail,size) \\r
+   ({int end = (size) - (tail); \\r
+     int n = ((head) + end) & ((size)-1); \\r
+     n < end ? n : end;})\r
+\r
+// Return space available up to the end of the buffer\r
+#define CIRC_SPACE_TO_END(head,tail,size) \\r
+   ({int end = (size) - 1 - (head); \\r
+     int n = (end + (tail)) & ((size)-1); \\r
+     n <= end ? n : end+1;})\r
+\r
+// Increment head or tail\r
+#define CIRC_INC(headortail,size) \\r
+        headortail++;             \\r
+        if(headortail >= size) {  \\r
+            headortail = 0;       \\r
+        }\r
+\r
+#define CIRC_EMPTY(circ)     ((circ)->head == (circ)->tail)\r
+#define CIRC_CLEAR(circ)     ((circ)->head = (circ)->tail = 0)\r
+\r
+\r
+//------------------------------------------------------------------------------\r
+//      Structures\r
+//------------------------------------------------------------------------------\r
+#ifdef __ICCARM__          // IAR\r
+#pragma pack(4)            // IAR\r
+#define __attribute__(...) // IAR\r
+#endif                     // IAR\r
+/// Describes the type and attribute of Receive Transfer descriptor.\r
+typedef struct _EmacRxTDescriptor {\r
+    unsigned int addr;\r
+    unsigned int status;\r
+} __attribute__((packed, aligned(8))) EmacRxTDescriptor, *PEmacRxTDescriptor;\r
+\r
+/// Describes the type and attribute of Transmit Transfer descriptor.\r
+typedef struct _EmacTxTDescriptor {\r
+    unsigned int addr;\r
+    unsigned int status;\r
+} __attribute__((packed, aligned(8))) EmacTxTDescriptor, *PEmacTxTDescriptor;\r
+#ifdef __ICCARM__          // IAR\r
+#pragma pack()             // IAR\r
+#endif                     // IAR\r
+\r
+#ifdef __ICCARM__          // IAR\r
+#pragma data_alignment=8   // IAR\r
+#endif                     // IAR\r
+/// Descriptors for RX (required aligned by 8)\r
+typedef struct {\r
+   volatile EmacRxTDescriptor td[RX_BUFFERS];\r
+   EMAC_RxCallback rxCb; /// Callback function to be invoked once a frame has been received\r
+   unsigned short idx;\r
+} RxTd;\r
+\r
+#ifdef __ICCARM__          // IAR\r
+#pragma data_alignment=8   // IAR\r
+#endif                     // IAR\r
+/// Descriptors for TX (required aligned by 8)\r
+typedef struct {\r
+   volatile EmacTxTDescriptor td[TX_BUFFERS];\r
+   EMAC_TxCallback txCb[TX_BUFFERS];    /// Callback function to be invoked once TD has been processed\r
+   EMAC_WakeupCallback wakeupCb;        /// Callback function to be invoked once several TD have been released\r
+   unsigned short wakeupThreshold; /// Number of free TD before wakeupCb is invoked\r
+   unsigned short head;            /// Circular buffer head pointer incremented by the upper layer (buffer to be sent)\r
+   unsigned short tail;            /// Circular buffer head pointer incremented by the IT handler (buffer sent)\r
+} TxTd;\r
+\r
+//------------------------------------------------------------------------------\r
+//         Internal variables\r
+//------------------------------------------------------------------------------\r
+// Receive Transfer Descriptor buffer\r
+static volatile RxTd rxTd; \r
+// Transmit Transfer Descriptor buffer\r
+static volatile TxTd txTd; \r
+/// Send Buffer\r
+// Section 3.6 of AMBA 2.0 spec states that burst should not cross 1K Boundaries.\r
+// Receive buffer manager writes are burst of 2 words => 3 lsb bits of the address shall be set to 0\r
+#ifdef __ICCARM__          // IAR\r
+#pragma data_alignment=8   // IAR\r
+#endif                     // IAR\r
+static volatile unsigned char pTxBuffer[TX_BUFFERS * EMAC_TX_UNITSIZE] __attribute__((aligned(8)));\r
+\r
+#ifdef __ICCARM__          // IAR\r
+#pragma data_alignment=8   // IAR\r
+#endif                     // IAR\r
+/// Receive Buffer\r
+static volatile unsigned char pRxBuffer[RX_BUFFERS * EMAC_RX_UNITSIZE] __attribute__((aligned(8)));\r
+/// Statistics\r
+static volatile EmacStats EmacStatistics;\r
+\r
+//-----------------------------------------------------------------------------\r
+//         Internal functions\r
+//-----------------------------------------------------------------------------\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Wait PHY operation complete.\r
+/// Return 1 if the operation completed successfully.\r
+/// May be need to re-implemented to reduce CPU load.\r
+/// \param retry: the retry times, 0 to wait forever until complete.\r
+//-----------------------------------------------------------------------------\r
+static unsigned char EMAC_WaitPhy( unsigned int retry )\r
+{\r
+    unsigned int retry_count = 0;\r
+\r
+    while((AT91C_BASE_EMAC->EMAC_NSR & AT91C_EMAC_IDLE) == 0) {\r
+\r
+        // Dead LOOP!\r
+        if (retry == 0) {\r
+\r
+            continue;\r
+        }\r
+\r
+        // Timeout check\r
+        retry_count++;\r
+        if(retry_count >= retry) {\r
+\r
+            TRACE_ERROR("E: Wait PHY time out\n\r");\r
+            return 0;\r
+        }\r
+    }\r
+\r
+    return 1;\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+//         Exported functions\r
+//-----------------------------------------------------------------------------\r
+\r
+//-----------------------------------------------------------------------------\r
+//          PHY management functions\r
+//-----------------------------------------------------------------------------\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Set MDC clock according to current board clock. Per 802.3, MDC should be \r
+/// less then 2.5MHz.\r
+/// Return 1 if successfully, 0 if MDC clock not found.\r
+//-----------------------------------------------------------------------------\r
+unsigned char EMAC_SetMdcClock( unsigned int mck )\r
+{\r
+    int clock_dividor;\r
+\r
+    if (mck <= 20000000) {\r
+        clock_dividor = AT91C_EMAC_CLK_HCLK_8;          /// MDC clock = MCK/8\r
+    }\r
+    else if (mck <= 40000000) {\r
+        clock_dividor = AT91C_EMAC_CLK_HCLK_16;         /// MDC clock = MCK/16\r
+    }\r
+    else if (mck <= 80000000) {\r
+        clock_dividor = AT91C_EMAC_CLK_HCLK_32;         /// MDC clock = MCK/32\r
+    }\r
+    else if (mck <= 160000000) {\r
+        clock_dividor = AT91C_EMAC_CLK_HCLK_64;         /// MDC clock = MCK/64\r
+    }\r
+    else {\r
+        TRACE_ERROR("E: No valid MDC clock.\n\r");\r
+        return 0;\r
+    }\r
+    AT91C_BASE_EMAC->EMAC_NCFGR = (AT91C_BASE_EMAC->EMAC_NCFGR & (~AT91C_EMAC_CLK))\r
+                                 | clock_dividor;\r
+    return 1;\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Enable MDI with PHY\r
+//-----------------------------------------------------------------------------\r
+void EMAC_EnableMdio( void )\r
+{\r
+    AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_MPE;\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Enable MDI with PHY\r
+//-----------------------------------------------------------------------------\r
+void EMAC_DisableMdio( void )\r
+{\r
+    AT91C_BASE_EMAC->EMAC_NCR &= ~AT91C_EMAC_MPE;\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Enable MII mode for EMAC, called once after autonegotiate\r
+//-----------------------------------------------------------------------------\r
+void EMAC_EnableMII( void )\r
+{\r
+    AT91C_BASE_EMAC->EMAC_USRIO = AT91C_EMAC_CLKEN;\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Enable RMII mode for EMAC, called once after autonegotiate\r
+//-----------------------------------------------------------------------------\r
+void EMAC_EnableRMII( void )\r
+{\r
+    AT91C_BASE_EMAC->EMAC_USRIO = AT91C_EMAC_CLKEN | AT91C_EMAC_RMII;\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Read PHY register.\r
+/// Return 1 if successfully, 0 if timeout.\r
+/// \param PhyAddress PHY Address\r
+/// \param Address Register Address\r
+/// \param pValue Pointer to a 32 bit location to store read data\r
+/// \param retry The retry times, 0 to wait forever until complete.\r
+//-----------------------------------------------------------------------------\r
+unsigned char EMAC_ReadPhy(unsigned char PhyAddress,\r
+                           unsigned char Address,\r
+                           unsigned int *pValue,\r
+                           unsigned int retry)\r
+{\r
+    AT91C_BASE_EMAC->EMAC_MAN = (AT91C_EMAC_SOF & (0x01 << 30))\r
+                              | (AT91C_EMAC_CODE & (2 << 16))\r
+                              | (AT91C_EMAC_RW & (2 << 28))\r
+                              | (AT91C_EMAC_PHYA & ((PhyAddress & 0x1f) << 23))\r
+                              | (AT91C_EMAC_REGA & (Address << 18));\r
+\r
+    if ( EMAC_WaitPhy(retry) == 0 ) {\r
+\r
+        TRACE_ERROR("TimeOut EMAC_ReadPhy\n\r");\r
+        return 0;\r
+    }\r
+    *pValue = ( AT91C_BASE_EMAC->EMAC_MAN & 0x0000ffff );\r
+    return 1;\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Write PHY register\r
+/// Return 1 if successfully, 0 if timeout.\r
+/// \param PhyAddress PHY Address\r
+/// \param Address Register Address\r
+/// \param Value Data to write ( Actually 16 bit data )\r
+/// \param retry The retry times, 0 to wait forever until complete.\r
+//-----------------------------------------------------------------------------\r
+unsigned char EMAC_WritePhy(unsigned char PhyAddress,\r
+                            unsigned char Address,\r
+                            unsigned int  Value,\r
+                            unsigned int  retry)\r
+{\r
+    AT91C_BASE_EMAC->EMAC_MAN = (AT91C_EMAC_SOF & (0x01 << 30))\r
+                              | (AT91C_EMAC_CODE & (2 << 16))\r
+                              | (AT91C_EMAC_RW & (1 << 28))\r
+                              | (AT91C_EMAC_PHYA & ((PhyAddress & 0x1f) << 23))\r
+                              | (AT91C_EMAC_REGA & (Address << 18))\r
+                              | (AT91C_EMAC_DATA & Value) ;\r
+    if ( EMAC_WaitPhy(retry) == 0 ) {\r
+\r
+        TRACE_ERROR("TimeOut EMAC_WritePhy\n\r");\r
+        return 0;\r
+    }\r
+    return 1;\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Setup the EMAC for the link : speed 100M/10M and Full/Half duplex\r
+/// \param speed        Link speed, 0 for 10M, 1 for 100M\r
+/// \param fullduplex   1 for Full Duplex mode\r
+//-----------------------------------------------------------------------------\r
+void EMAC_SetLinkSpeed(unsigned char speed, unsigned char fullduplex)\r
+{\r
+    unsigned int ncfgr;\r
+\r
+    ncfgr = AT91C_BASE_EMAC->EMAC_NCFGR;\r
+    ncfgr &= ~(AT91C_EMAC_SPD | AT91C_EMAC_FD);\r
+    if (speed) {\r
+\r
+        ncfgr |= AT91C_EMAC_SPD;\r
+    }\r
+    if (fullduplex) {\r
+\r
+        ncfgr |= AT91C_EMAC_FD;\r
+    }\r
+    AT91C_BASE_EMAC->EMAC_NCFGR = ncfgr;\r
+}\r
+\r
+\r
+\r
+//-----------------------------------------------------------------------------\r
+//          EMAC functions\r
+//-----------------------------------------------------------------------------\r
+\r
+//-----------------------------------------------------------------------------\r
+/// EMAC Interrupt handler\r
+//-----------------------------------------------------------------------------\r
+void EMAC_Handler(void)\r
+{\r
+    volatile EmacTxTDescriptor *pTxTd;\r
+    volatile EMAC_TxCallback   *pTxCb;\r
+    unsigned int isr;\r
+    unsigned int rsr;\r
+    unsigned int tsr;\r
+    unsigned int rxStatusFlag;\r
+    unsigned int txStatusFlag;\r
+\r
+    //TRACE_DEBUG("EMAC_Handler\n\r");\r
+    isr = AT91C_BASE_EMAC->EMAC_ISR & AT91C_BASE_EMAC->EMAC_IMR;\r
+    rsr = AT91C_BASE_EMAC->EMAC_RSR;\r
+    tsr = AT91C_BASE_EMAC->EMAC_TSR;\r
+\r
+    // RX packet\r
+    if ((isr & AT91C_EMAC_RCOMP) || (rsr & AT91C_EMAC_REC)) {\r
+        rxStatusFlag = AT91C_EMAC_REC;\r
+\r
+        // Frame received\r
+        EmacStatistics.rx_packets++;\r
+\r
+        // Check OVR\r
+        if (rsr & AT91C_EMAC_OVR) {\r
+            rxStatusFlag |= AT91C_EMAC_OVR;\r
+            EmacStatistics.rx_ovrs++;\r
+        }\r
+        // Check BNA\r
+        if (rsr & AT91C_EMAC_BNA) {\r
+            rxStatusFlag |= AT91C_EMAC_BNA;\r
+            EmacStatistics.rx_bnas++;\r
+        }\r
+        // Clear status\r
+        AT91C_BASE_EMAC->EMAC_RSR |= rxStatusFlag;\r
+\r
+        // Invoke callbacks\r
+        if (rxTd.rxCb) {\r
+            rxTd.rxCb(rxStatusFlag);\r
+        }\r
+    }\r
+\r
+    // TX packet\r
+    if ((isr & AT91C_EMAC_TCOMP) || (tsr & AT91C_EMAC_COMP)) {\r
+\r
+        txStatusFlag = AT91C_EMAC_COMP;\r
+        EmacStatistics.tx_comp ++;\r
+\r
+        // A frame transmitted\r
+        // Check RLE\r
+        if (tsr & AT91C_EMAC_RLES) {\r
+            txStatusFlag |= AT91C_EMAC_RLES;\r
+            EmacStatistics.tx_errors++;\r
+        }\r
+        // Check COL\r
+        if (tsr & AT91C_EMAC_COL) {\r
+            txStatusFlag |= AT91C_EMAC_COL;\r
+            EmacStatistics.collisions++;\r
+        }\r
+        // Check BEX\r
+        if (tsr & AT91C_EMAC_BEX) {\r
+            txStatusFlag |= AT91C_EMAC_BEX;\r
+            EmacStatistics.tx_exausts++;\r
+        }\r
+        // Check UND\r
+        if (tsr & AT91C_EMAC_UND) {\r
+            txStatusFlag |= AT91C_EMAC_UND;\r
+            EmacStatistics.tx_underruns++;\r
+        }\r
+        // Clear status\r
+        AT91C_BASE_EMAC->EMAC_TSR |= txStatusFlag;\r
+\r
+        // Sanity check: Tx buffers have to be scheduled\r
+        ASSERT(!CIRC_EMPTY(&txTd),\r
+            "-F- EMAC Tx interrupt received meanwhile no TX buffers has been scheduled\n\r");\r
+        \r
+        // Check the buffers\r
+        while (CIRC_CNT(txTd.head, txTd.tail, TX_BUFFERS)) {\r
+            pTxTd = txTd.td + txTd.tail;\r
+            pTxCb = txTd.txCb + txTd.tail;\r
+\r
+            // Exit if buffer has not been sent yet\r
+            if ((pTxTd->status & EMAC_TX_USED_BIT) == 0) {\r
+                break;\r
+            }\r
+            \r
+            // Notify upper layer that packet has been sent\r
+            if (*pTxCb) {\r
+                (*pTxCb)(txStatusFlag);\r
+            }\r
+            \r
+            CIRC_INC( txTd.tail, TX_BUFFERS );\r
+        }\r
+\r
+        // If a wakeup has been scheduled, notify upper layer that it can send \r
+        // other packets, send will be successfull.\r
+        if( (CIRC_SPACE(txTd.head, txTd.tail, TX_BUFFERS) >= txTd.wakeupThreshold)\r
+         &&  txTd.wakeupCb) {\r
+            txTd.wakeupCb();\r
+        }\r
+    }\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Initialize the EMAC with the emac controller address\r
+/// \param id     HW ID for power management\r
+/// \param pTxWakeUpfct Thresold TX Wakeup Callback\r
+/// \param pRxfct       RX Wakeup Callback\r
+/// \param pMacAddress  Mac Address\r
+/// \param enableCAF    enable AT91C_EMAC_CAF if needed by application\r
+/// \param enableNBC    AT91C_EMAC_NBC if needed by application\r
+//-----------------------------------------------------------------------------\r
+void EMAC_Init( unsigned char id, const unsigned char *pMacAddress, \r
+                unsigned char enableCAF, unsigned char enableNBC )\r
+{\r
+    int Index;\r
+    unsigned int Address;\r
+\r
+    // Check parameters\r
+    ASSERT(RX_BUFFERS * EMAC_RX_UNITSIZE > EMAC_FRAME_LENTGH_MAX,\r
+           "E: RX buffers too small\n\r");\r
+\r
+    TRACE_DEBUG("EMAC_Init\n\r");\r
+\r
+    // Power ON\r
+    AT91C_BASE_PMC->PMC_PCER = 1 << id;\r
+\r
+    // Disable TX & RX and more\r
+    AT91C_BASE_EMAC->EMAC_NCR = 0;\r
+\r
+    // disable \r
+    AT91C_BASE_EMAC->EMAC_IDR = ~0;\r
+\r
+    rxTd.idx = 0;\r
+    CIRC_CLEAR(&txTd);\r
+\r
+    // Setup the RX descriptors.\r
+    for(Index = 0; Index < RX_BUFFERS; Index++) {\r
+\r
+        Address = (unsigned int)(&(pRxBuffer[Index * EMAC_RX_UNITSIZE]));\r
+        // Remove EMAC_RX_OWNERSHIP_BIT and EMAC_RX_WRAP_BIT\r
+        rxTd.td[Index].addr = Address & EMAC_ADDRESS_MASK;\r
+        rxTd.td[Index].status = 0;\r
+    }\r
+    rxTd.td[RX_BUFFERS - 1].addr |= EMAC_RX_WRAP_BIT;\r
+\r
+    // Setup the TX descriptors.\r
+    for(Index = 0; Index < TX_BUFFERS; Index++) {\r
+\r
+        Address = (unsigned int)(&(pTxBuffer[Index * EMAC_TX_UNITSIZE]));\r
+        txTd.td[Index].addr = Address;\r
+        txTd.td[Index].status = EMAC_TX_USED_BIT;\r
+    }\r
+    txTd.td[TX_BUFFERS - 1].status = EMAC_TX_USED_BIT | EMAC_TX_WRAP_BIT;\r
+\r
+    // Set the MAC address\r
+    if( pMacAddress != (unsigned char *)0 ) {\r
+        AT91C_BASE_EMAC->EMAC_SA1L = ( ((unsigned int)pMacAddress[3] << 24)\r
+                                     | ((unsigned int)pMacAddress[2] << 16)\r
+                                     | ((unsigned int)pMacAddress[1] << 8 )\r
+                                     |                pMacAddress[0] );\r
+\r
+        AT91C_BASE_EMAC->EMAC_SA1H = ( ((unsigned int)pMacAddress[5] << 8 )\r
+                                     |                pMacAddress[4] );\r
+    }\r
+    // Now setup the descriptors\r
+    // Receive Buffer Queue Pointer Register\r
+    AT91C_BASE_EMAC->EMAC_RBQP = (unsigned int) (rxTd.td);\r
+    // Transmit Buffer Queue Pointer Register\r
+    AT91C_BASE_EMAC->EMAC_TBQP = (unsigned int) (txTd.td);\r
+\r
+    AT91C_BASE_EMAC->EMAC_NCR = AT91C_EMAC_CLRSTAT;\r
+\r
+    // Clear all status bits in the receive status register.\r
+    AT91C_BASE_EMAC->EMAC_RSR = (AT91C_EMAC_OVR | AT91C_EMAC_REC | AT91C_EMAC_BNA);\r
+\r
+    // Clear all status bits in the transmit status register\r
+    AT91C_BASE_EMAC->EMAC_TSR = ( AT91C_EMAC_UBR | AT91C_EMAC_COL | AT91C_EMAC_RLES\r
+                                | AT91C_EMAC_BEX | AT91C_EMAC_COMP\r
+                                | AT91C_EMAC_UND );\r
+\r
+    // Clear interrupts\r
+    AT91C_BASE_EMAC->EMAC_ISR;\r
+\r
+    // Enable the copy of data into the buffers\r
+    // ignore broadcasts, and don't copy FCS.\r
+    AT91C_BASE_EMAC->EMAC_NCFGR |= (AT91C_EMAC_DRFCS | AT91C_EMAC_PAE);\r
+\r
+    if( enableCAF == EMAC_CAF_ENABLE ) {\r
+        AT91C_BASE_EMAC->EMAC_NCFGR |= AT91C_EMAC_CAF;\r
+    }\r
+    if( enableNBC == EMAC_NBC_ENABLE ) {\r
+        AT91C_BASE_EMAC->EMAC_NCFGR |= AT91C_EMAC_NBC;\r
+    }\r
+\r
+    // Enable Rx and Tx, plus the stats register.\r
+    AT91C_BASE_EMAC->EMAC_NCR |= (AT91C_EMAC_TE | AT91C_EMAC_RE | AT91C_EMAC_WESTAT);\r
+\r
+    // Setup the interrupts for TX (and errors)\r
+    AT91C_BASE_EMAC->EMAC_IER = AT91C_EMAC_RXUBR\r
+                              | AT91C_EMAC_TUNDR\r
+                              | AT91C_EMAC_RLEX\r
+                              | AT91C_EMAC_TXERR\r
+                              | AT91C_EMAC_TCOMP\r
+                              | AT91C_EMAC_ROVR\r
+                              | AT91C_EMAC_HRESP;\r
+\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Get the statstic information & reset it\r
+/// \param pStats   Pointer to EmacStats structure to copy the informations\r
+/// \param reset    Reset the statistics after copy it\r
+//-----------------------------------------------------------------------------\r
+void EMAC_GetStatistics(EmacStats *pStats, unsigned char reset)\r
+{\r
+    unsigned int ncrBackup = 0;\r
+\r
+    TRACE_DEBUG("EMAC_GetStatistics\n\r");\r
+\r
+    // Sanity check\r
+    if (pStats == (EmacStats *) 0) {\r
+        return;\r
+    }\r
+    \r
+    ncrBackup = AT91C_BASE_EMAC->EMAC_NCR & (AT91C_EMAC_TE | AT91C_EMAC_RE);\r
+\r
+    // Disable TX/RX\r
+    AT91C_BASE_EMAC->EMAC_NCR = ncrBackup & ~(AT91C_EMAC_TE | AT91C_EMAC_RE);\r
+\r
+    // Copy the informations\r
+    memcpy(pStats, (void*)&EmacStatistics, sizeof(EmacStats));\r
+\r
+    // Reset the statistics\r
+    if (reset) {\r
+        memset((void*)&EmacStatistics, 0x00, sizeof(EmacStats));\r
+        AT91C_BASE_EMAC->EMAC_NCR = ncrBackup | AT91C_EMAC_CLRSTAT;\r
+    }\r
+\r
+    // restore NCR\r
+    AT91C_BASE_EMAC->EMAC_NCR = ncrBackup;\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Send a packet with EMAC.\r
+/// If the packet size is larger than transfer buffer size error returned.\r
+/// \param buffer   The buffer to be send\r
+/// \param size     The size of buffer to be send\r
+/// \param fEMAC_TxCallback Threshold Wakeup callback\r
+/// \param fWakeUpCb   TX Wakeup\r
+/// \return         OK, Busy or invalid packet\r
+//-----------------------------------------------------------------------------\r
+unsigned char EMAC_Send(void *pBuffer, \r
+                        unsigned int size, \r
+                        EMAC_TxCallback fEMAC_TxCallback)\r
+{\r
+    volatile EmacTxTDescriptor *pTxTd;\r
+    volatile EMAC_TxCallback   *pTxCb;\r
+\r
+    //TRACE_DEBUG("EMAC_Send\n\r");\r
+\r
+    // Check parameter\r
+    if (size > EMAC_TX_UNITSIZE) {\r
+\r
+        TRACE_ERROR("EMAC driver does not split send packets.");\r
+        TRACE_ERROR(" It can send %d bytes max in one packet (%d bytes requested)\n\r",\r
+            EMAC_TX_UNITSIZE, size);\r
+        return EMAC_TX_INVALID_PACKET;\r
+    }\r
+\r
+    // If no free TxTd, buffer can't be sent, schedule the wakeup callback\r
+    if( CIRC_SPACE(txTd.head, txTd.tail, TX_BUFFERS) == 0) {\r
+        return EMAC_TX_BUFFER_BUSY;\r
+\r
+    }\r
+\r
+    // Pointers to the current TxTd\r
+    pTxTd = txTd.td + txTd.head;\r
+    pTxCb = txTd.txCb + txTd.head;\r
+\r
+    // Sanity check\r
+    ASSERT((pTxTd->status & EMAC_TX_USED_BIT) != 0, \r
+        "-F- Buffer is still under EMAC control\n\r");\r
+\r
+    // Setup/Copy data to transmition buffer\r
+    if (pBuffer && size) {\r
+        // Driver manage the ring buffer\r
+        memcpy((void *)pTxTd->addr, pBuffer, size);\r
+    }\r
+    \r
+    // Tx Callback\r
+    *pTxCb = fEMAC_TxCallback;\r
+\r
+    // Update TD status\r
+    // The buffer size defined is length of ethernet frame\r
+    // so it's always the last buffer of the frame.\r
+    if (txTd.head == TX_BUFFERS-1) {\r
+        pTxTd->status = \r
+            (size & EMAC_LENGTH_FRAME) | EMAC_TX_LAST_BUFFER_BIT | EMAC_TX_WRAP_BIT;\r
+    }\r
+    else {\r
+        pTxTd->status = (size & EMAC_LENGTH_FRAME) | EMAC_TX_LAST_BUFFER_BIT;\r
+    }\r
+    \r
+    CIRC_INC(txTd.head, TX_BUFFERS)\r
+\r
+    // Tx packets count\r
+    EmacStatistics.tx_packets++;\r
+\r
+    // Now start to transmit if it is not already done\r
+    AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_TSTART;\r
+\r
+    return EMAC_TX_OK;\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Receive a packet with EMAC\r
+/// If not enough buffer for the packet, the remaining data is lost but right\r
+/// frame length is returned.\r
+/// \param pFrame           Buffer to store the frame\r
+/// \param frameSize        Size of the frame\r
+/// \param pRcvSize         Received size\r
+/// \return                 OK, no data, or frame too small\r
+//-----------------------------------------------------------------------------\r
+unsigned char EMAC_Poll(unsigned char *pFrame,\r
+                        unsigned int frameSize,\r
+                        unsigned int *pRcvSize)\r
+{\r
+    unsigned short bufferLength;\r
+    unsigned int   tmpFrameSize=0;\r
+    unsigned char  *pTmpFrame=0;\r
+    unsigned int   tmpIdx = rxTd.idx;\r
+    volatile EmacRxTDescriptor *pRxTd = rxTd.td + rxTd.idx;\r
+\r
+    ASSERT(pFrame, "F: EMAC_Poll\n\r");\r
+\r
+    char isFrame = 0;\r
+    // Set the default return value\r
+    *pRcvSize = 0;\r
+\r
+    // Process received RxTd\r
+    while ((pRxTd->addr & EMAC_RX_OWNERSHIP_BIT) == EMAC_RX_OWNERSHIP_BIT) {\r
+\r
+        // A start of frame has been received, discard previous fragments\r
+        if ((pRxTd->status & EMAC_RX_SOF_BIT) == EMAC_RX_SOF_BIT) {\r
+            // Skip previous fragment\r
+            while (tmpIdx != rxTd.idx) {\r
+                pRxTd = rxTd.td + rxTd.idx;\r
+                pRxTd->addr &= ~(EMAC_RX_OWNERSHIP_BIT);\r
+                CIRC_INC(rxTd.idx, RX_BUFFERS);\r
+            }\r
+            // Reset the temporary frame pointer\r
+            pTmpFrame = pFrame;\r
+            tmpFrameSize = 0;\r
+            // Start to gather buffers in a frame\r
+            isFrame = 1;\r
+        }\r
+\r
+        // Increment the pointer\r
+        CIRC_INC(tmpIdx, RX_BUFFERS);\r
+\r
+        // Copy data in the frame buffer\r
+        if (isFrame) {\r
+            if (tmpIdx == rxTd.idx) {\r
+                TRACE_INFO("no EOF (Invalid of buffers too small)\n\r");\r
+\r
+                do {\r
+\r
+                    pRxTd = rxTd.td + rxTd.idx;\r
+                    pRxTd->addr &= ~(EMAC_RX_OWNERSHIP_BIT);\r
+                    CIRC_INC(rxTd.idx, RX_BUFFERS);\r
+                } while(tmpIdx != rxTd.idx);\r
+                return EMAC_RX_NO_DATA;\r
+            }\r
+            // Copy the buffer into the application frame\r
+            bufferLength = EMAC_RX_UNITSIZE;\r
+            if ((tmpFrameSize + bufferLength) > frameSize) {\r
+                bufferLength = frameSize - tmpFrameSize;\r
+            }\r
+\r
+            memcpy(pTmpFrame, (void*)(pRxTd->addr & EMAC_ADDRESS_MASK), bufferLength);\r
+            pTmpFrame += bufferLength;\r
+            tmpFrameSize += bufferLength;\r
+            \r
+            // An end of frame has been received, return the data\r
+            if ((pRxTd->status & EMAC_RX_EOF_BIT) == EMAC_RX_EOF_BIT) {\r
+                // Frame size from the EMAC\r
+                *pRcvSize = (pRxTd->status & EMAC_LENGTH_FRAME);\r
+                \r
+                // Application frame buffer is too small all data have not been copied\r
+                if (tmpFrameSize < *pRcvSize) {\r
+                    printf("size req %d size allocated %d\n\r", *pRcvSize, frameSize);\r
+                    \r
+                    return EMAC_RX_FRAME_SIZE_TOO_SMALL;\r
+                }\r
+                \r
+                TRACE_DEBUG("packet %d-%d (%d)\n\r", rxTd.idx, tmpIdx, *pRcvSize);\r
+                // All data have been copied in the application frame buffer => release TD\r
+                while (rxTd.idx != tmpIdx) {\r
+                    pRxTd = rxTd.td + rxTd.idx;\r
+                    pRxTd->addr &= ~(EMAC_RX_OWNERSHIP_BIT);\r
+                    CIRC_INC(rxTd.idx, RX_BUFFERS);\r
+                }\r
+                EmacStatistics.rx_packets++;\r
+                return EMAC_RX_OK;\r
+            }\r
+        }\r
+        \r
+        // SOF has not been detected, skip the fragment\r
+        else {\r
+           pRxTd->addr &= ~(EMAC_RX_OWNERSHIP_BIT);\r
+           rxTd.idx = tmpIdx;\r
+        }\r
+       \r
+        // Process the next buffer\r
+        pRxTd = rxTd.td + tmpIdx;\r
+    }\r
+    \r
+    //TRACE_DEBUG("E");\r
+    return EMAC_RX_NO_DATA;\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Registers pRxCb callback. Callback will be invoked after the next received\r
+/// frame.\r
+/// When EMAC_Poll() returns EMAC_RX_NO_DATA the application task call EMAC_Set_RxCb()\r
+/// to register pRxCb() callback and enters suspend state. The callback is in charge \r
+/// to resume the task once a new frame has been received. The next time EMAC_Poll()\r
+/// is called, it will be successfull.\r
+/// \param pRxCb            Pointer to callback function\r
+//-----------------------------------------------------------------------------\r
+void EMAC_Set_RxCb(EMAC_RxCallback pRxCb)\r
+{\r
+    rxTd.rxCb = pRxCb;\r
+    AT91C_BASE_EMAC->EMAC_IER = AT91C_EMAC_RCOMP; \r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Remove the RX callback function.\r
+/// This function is usually invoked from the RX callback itself. Once the callback \r
+/// has resumed the application task, there is no need to invoke the callback again.\r
+//-----------------------------------------------------------------------------\r
+void EMAC_Clear_RxCb(void)\r
+{\r
+    AT91C_BASE_EMAC->EMAC_IDR = AT91C_EMAC_RCOMP; \r
+    rxTd.rxCb = (EMAC_RxCallback) 0;\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Registers TX wakeup callback callback. Callback will be invoked once several\r
+/// transfer descriptors are available.\r
+/// When EMAC_Send() returns EMAC_TX_BUFFER_BUSY (all TD busy) the application \r
+/// task calls EMAC_Set_TxWakeUpCb() to register pTxWakeUpCb() callback and \r
+/// enters suspend state. The callback is in charge to resume the task once \r
+/// several TD have been released. The next time EMAC_Send() will be called, it\r
+/// shall be successfull.\r
+/// \param pTxWakeUpCb   Pointer to callback function\r
+/// \param threshold     Minimum number of available transfer descriptors before pTxWakeUpCb() is invoked\r
+/// \return              0= success, 1 = threshold exceeds nuber of transfer descriptors\r
+//-----------------------------------------------------------------------------\r
+char EMAC_Set_TxWakeUpCb(EMAC_WakeupCallback pTxWakeUpCb, unsigned short threshold)\r
+{\r
+    if (threshold <= TX_BUFFERS) {\r
+        txTd.wakeupCb = pTxWakeUpCb;\r
+        txTd.wakeupThreshold = threshold;\r
+        return 0;\r
+    }\r
+    return 1;\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Remove the TX wakeup callback function.\r
+/// This function is usually invoked from the TX wakeup callback itself. Once the callback \r
+/// has resumed the application task, there is no need to invoke the callback again.\r
+//-----------------------------------------------------------------------------\r
+void EMAC_Clear_TxWakeUpCb(void)\r
+{\r
+    txTd.wakeupCb = (EMAC_WakeupCallback) 0;\r
+}\r
+    \r
+\r

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/emac/emac.h b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/emac/emac.h
new file mode 100644 (file)
index 0000000..ccaa539
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/emac/emac.h
@@ -0,0 +1,163 @@
+/* ----------------------------------------------------------------------------\r
+ *         ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+// peripherals/emac/emac.h\r
+\r
+#ifndef EMAC_H\r
+#define EMAC_H\r
+\r
+//-----------------------------------------------------------------------------\r
+/// \dir\r
+/// !Purpose\r
+///\r
+///     Definition of methods and structures for using EMAC\r
+///     \r
+/// !Usage\r
+///\r
+/// -# Initialize EMAC with EMAC_Init with MAC address.\r
+/// -# Then the caller application need to initialize the PHY driver before further calling EMAC\r
+///      driver.\r
+/// -# Get a packet from network\r
+///      -# Interrupt mode: EMAC_Set_RxCb to register a function to process the frame packet\r
+///      -# Polling mode: EMAC_Poll for a data packet from network \r
+/// -# Send a packet to network with EMAC_Send.\r
+///\r
+/// Please refer to the list of functions in the #Overview# tab of this unit\r
+/// for more detailed information.\r
+//-----------------------------------------------------------------------------\r
+\r
+\r
+//-----------------------------------------------------------------------------\r
+//         Headers\r
+//-----------------------------------------------------------------------------\r
+\r
+//-----------------------------------------------------------------------------\r
+//         Definitions\r
+//-----------------------------------------------------------------------------\r
+/// Number of buffer for RX, be carreful: MUST be 2^n\r
+#define RX_BUFFERS  16\r
+/// Number of buffer for TX, be carreful: MUST be 2^n\r
+#define TX_BUFFERS   8\r
+\r
+/// Buffer Size\r
+#define EMAC_RX_UNITSIZE            128     /// Fixed size for RX buffer\r
+#define EMAC_TX_UNITSIZE            1518    /// Size for ETH frame length\r
+\r
+// The MAC can support frame lengths up to 1536 bytes.\r
+#define EMAC_FRAME_LENTGH_MAX       1536\r
+\r
+\r
+//-----------------------------------------------------------------------------\r
+//         Types\r
+//-----------------------------------------------------------------------------\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Describes the statistics of the EMAC.\r
+//-----------------------------------------------------------------------------\r
+typedef struct _EmacStats {\r
+\r
+    // TX errors\r
+    unsigned int tx_packets;    /// Total Number of packets sent\r
+    unsigned int tx_comp;       /// Packet complete\r
+    unsigned int tx_errors;     /// TX errors ( Retry Limit Exceed )\r
+    unsigned int collisions;    /// Collision\r
+    unsigned int tx_exausts;    /// Buffer exhausted\r
+    unsigned int tx_underruns;  /// Under Run, not able to read from memory\r
+    // RX errors\r
+    unsigned int rx_packets;    /// Total Number of packets RX\r
+    unsigned int rx_eof;        /// No EOF error\r
+    unsigned int rx_ovrs;       /// Over Run, not able to store to memory\r
+    unsigned int rx_bnas;       /// Buffer is not available\r
+\r
+} EmacStats, *PEmacStats;\r
+\r
+//-----------------------------------------------------------------------------\r
+//         PHY Exported functions\r
+//-----------------------------------------------------------------------------\r
+extern unsigned char EMAC_SetMdcClock( unsigned int mck );\r
+\r
+extern void EMAC_EnableMdio( void );\r
+\r
+extern void EMAC_DisableMdio( void );\r
+\r
+extern void EMAC_EnableMII( void );\r
+\r
+extern void EMAC_EnableRMII( void );\r
+\r
+extern unsigned char EMAC_ReadPhy(unsigned char PhyAddress,\r
+                                  unsigned char Address,\r
+                                  unsigned int *pValue,\r
+                                  unsigned int retry);\r
+\r
+extern unsigned char EMAC_WritePhy(unsigned char PhyAddress,\r
+                                   unsigned char Address,\r
+                                   unsigned int Value,\r
+                                   unsigned int retry);\r
+\r
+extern void EMAC_SetLinkSpeed(unsigned char speed,\r
+                              unsigned char fullduplex);\r
+\r
+//-----------------------------------------------------------------------------\r
+//         EMAC Exported functions\r
+//-----------------------------------------------------------------------------\r
+/// Callback used by send function\r
+typedef void (*EMAC_TxCallback)(unsigned int status);\r
+typedef void (*EMAC_RxCallback)(unsigned int status);\r
+typedef void (*EMAC_WakeupCallback)(void);\r
+\r
+extern void EMAC_Init( unsigned char id, const unsigned char *pMacAddress,\r
+                unsigned char enableCAF, unsigned char enableNBC );\r
+#define EMAC_CAF_DISABLE  0\r
+#define EMAC_CAF_ENABLE   1\r
+#define EMAC_NBC_DISABLE  0\r
+#define EMAC_NBC_ENABLE   1\r
+\r
+extern void EMAC_Handler(void);\r
+\r
+extern unsigned char EMAC_Send(void *pBuffer, \r
+                               unsigned int size, \r
+                               EMAC_TxCallback fEMAC_TxCallback);\r
+/// Return for EMAC_Send function\r
+#define EMAC_TX_OK                     0\r
+#define EMAC_TX_BUFFER_BUSY            1\r
+#define EMAC_TX_INVALID_PACKET         2\r
+\r
+\r
+extern unsigned char EMAC_Poll(unsigned char *pFrame,\r
+                               unsigned int frameSize,\r
+                               unsigned int *pRcvSize);\r
+/// Return for EMAC_Poll function\r
+#define EMAC_RX_OK                   0\r
+#define EMAC_RX_NO_DATA              1\r
+#define EMAC_RX_FRAME_SIZE_TOO_SMALL 2\r
+\r
+extern void EMAC_GetStatistics(EmacStats *pStats, unsigned char reset);\r
+\r
+#endif // #ifndef EMAC_H\r
+\r

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/irq/irq.h b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/irq/irq.h
new file mode 100644 (file)
index 0000000..b85990c
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/irq/irq.h
@@ -0,0 +1,82 @@
+/* ----------------------------------------------------------------------------\r
+ *         ATMEL Microcontroller Software Support\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+//------------------------------------------------------------------------------\r
+/// \unit\r
+///\r
+/// !Purpose\r
+///\r
+/// Methods and definitions for configuring interrupts.\r
+///\r
+/// !Usage\r
+///\r
+/// -# Configure an interrupt source using IRQ_ConfigureIT\r
+/// -# Enable or disable interrupt generation of a particular source with\r
+///    IRQ_EnableIT and IRQ_DisableIT.\r
+///\r
+/// \note Most of the time, peripheral interrupts must be also configured\r
+/// inside the peripheral itself.\r
+//------------------------------------------------------------------------------\r
+\r
+#ifndef IRQ_H\r
+#define IRQ_H\r
+\r
+//------------------------------------------------------------------------------\r
+//         Headers\r
+//------------------------------------------------------------------------------\r
+\r
+#include <board.h>\r
+#if defined(cortexm3)\r
+#include <cmsis/core_cm3.h>\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+//         Definitions\r
+//------------------------------------------------------------------------------\r
+#if defined(cortexm3)\r
+#ifdef __NVIC_PRIO_BITS\r
+#undef __NVIC_PRIO_BITS\r
+#define __NVIC_PRIO_BITS           ((SCB->AIRCR & 0x700) >> 8)\r
+#endif\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+//         Global functions\r
+//------------------------------------------------------------------------------\r
+\r
+extern void IRQ_ConfigureIT(unsigned int source,\r
+                            unsigned int mode,         // mode for AIC, priority for NVIC\r
+                            void( *handler )( void )); // ISR\r
+\r
+extern void IRQ_EnableIT(unsigned int source);\r
+\r
+extern void IRQ_DisableIT(unsigned int source);\r
+\r
+#endif //#ifndef IRQ_H\r
+\r

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/irq/nvic.c b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/irq/nvic.c
new file mode 100644 (file)
index 0000000..1e61aa1
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/irq/nvic.c
@@ -0,0 +1,144 @@
+/* ----------------------------------------------------------------------------\r
+ *         ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+//------------------------------------------------------------------------------\r
+//         Headers\r
+//------------------------------------------------------------------------------\r
+\r
+#include "board.h"\r
+#include "irq.h"\r
+#include "exceptions.h"\r
+#include <utility/trace.h>\r
+\r
+/// The index of IRQ handler in the exception table\r
+#define NVIC_IRQ_HANDLER_INDEX     16\r
+\r
+//------------------------------------------------------------------------------\r
+//         Global functions\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+/// Configures an interrupt in the NVIC. The interrupt is identified by its\r
+/// source (AT91C_ID_xxx) and is configured to a specified priority and\r
+/// interrupt handler function. priority is the value that will be put in NVIC_IPRx\r
+/// and the function address will be set in "ExceptionTable". The parameter priority\r
+/// will include the preemptionPriority and the subPriority, where the subPriority\r
+/// defined in the B[7:0] of the parameter "priority", and the preemptionPriority defined\r
+/// in the B[15:8] of the parameter "priority". \r
+/// The interrupt is disabled before configuration, so it is useless\r
+/// to do it before calling this function. When NVIC_ConfigureIT returns, the\r
+/// interrupt will always be disabled and cleared; it must be enabled by a\r
+/// call to NVIC_EnableIT().\r
+/// \param source               Interrupt source to configure.\r
+/// \param priority              Pre-emption priority (B[15:8] )+ subPriority (B[7:0])\r
+/// \param handler              Interrupt handler function.\r
+//------------------------------------------------------------------------------\r
+void IRQ_ConfigureIT(\r
+    unsigned int source,\r
+    //unsigned int preemptionPriority,\r
+    //unsigned int subPriority,\r
+    unsigned int priority,\r
+    IntFunc handler)\r
+{\r
+    unsigned int priGroup = __NVIC_PRIO_BITS;\r
+    unsigned int nPre = 7 - priGroup;\r
+    unsigned int nSub = priGroup + 1;\r
+    unsigned int preemptionPriority;\r
+    unsigned int subPriority;\r
+    unsigned int IRQpriority;\r
+\r
+    preemptionPriority = (priority & 0xff00) >> 8;\r
+    subPriority = (priority & 0xff);\r
+\r
+    // Disable the interrupt first\r
+    NVIC_DisableIRQ((IRQn_Type)source);\r
+\r
+    // Clear any pending status\r
+    NVIC_ClearPendingIRQ((IRQn_Type)source);\r
+\r
+    // Configure interrupt handler\r
+    //if (handler == 0) handler = IrqHandlerNotUsed;\r
+      //  GetExceptionTable()[NVIC_IRQ_HANDLER_INDEX + source] = handler;\r
+\r
+    if (subPriority >= (0x01 << nSub))\r
+      subPriority = (0x01 << nSub) - 1;\r
+    if (preemptionPriority >= (0x01 << nPre))\r
+      preemptionPriority = (0x01 << nPre) - 1;\r
+\r
+    IRQpriority = (subPriority | (preemptionPriority << nSub));\r
+    NVIC_SetPriority((IRQn_Type)source, IRQpriority);\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Enables interrupt coming from the given (unique) source (AT91C_ID_xxx).\r
+/// \param source  Interrupt source to enable.\r
+//------------------------------------------------------------------------------\r
+void IRQ_EnableIT(unsigned int source)\r
+{\r
+    NVIC_EnableIRQ((IRQn_Type)source);\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Disables interrupt coming from the given (unique) source (AT91C_ID_xxx).\r
+/// \param source  Interrupt source to disable.\r
+//------------------------------------------------------------------------------\r
+void IRQ_DisableIT(unsigned int source)\r
+{\r
+    NVIC_DisableIRQ((IRQn_Type)source);\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Set interrupt pending bit from the given (unique) source (AT91C_ID_xxx).\r
+/// \param source  Interrupt source to set.\r
+//------------------------------------------------------------------------------\r
+void NVIC_SetPending(unsigned int source)\r
+{\r
+    NVIC_SetPendingIRQ((IRQn_Type)source);\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Clear interrupt pending bit from the given (unique) source (AT91C_ID_xxx).\r
+/// \param source  Interrupt source to clear.\r
+//------------------------------------------------------------------------------\r
+void NVIC_ClrPending(unsigned int source)\r
+{\r
+    NVIC_ClearPendingIRQ((IRQn_Type)source);\r
+}\r
+\r
+#if !defined(USE_CMSIS_on)\r
+//------------------------------------------------------------------------------\r
+/// Use the Software Trigger Interrupt Register to pend an interrupt.\r
+/// \param source Interrupt source to trigger.\r
+//------------------------------------------------------------------------------\r
+void NVIC_Swi(unsigned int source)\r
+{\r
+    AT91C_BASE_NVIC->NVIC_STIR = source;\r
+}\r
+#endif\r
+\r

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/isi/isi.c b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/isi/isi.c
new file mode 100644 (file)
index 0000000..05feb4b
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/isi/isi.c
@@ -0,0 +1,261 @@
+/* ----------------------------------------------------------------------------\r
+ *         ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+//------------------------------------------------------------------------------\r
+/// \unit\r
+///\r
+/// !Purpose\r
+/// \r
+/// Image Sensor Interface (ISI) driver\r
+/// \r
+/// !Usage\r
+/// \r
+/// Explanation on the usage of the code made available through the header file.\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+//         Headers\r
+//------------------------------------------------------------------------------\r
+\r
+#include <board.h>\r
+#include <utility/trace.h>\r
+#include <utility/video.h>\r
+#include "isi.h"\r
+\r
+#if !defined (BOARD_ISI_V200)\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Enable ISI\r
+//-----------------------------------------------------------------------------\r
+void ISI_Enable(void)\r
+{\r
+    AT91C_BASE_ISI->ISI_CR1 &= ~AT91C_ISI_DIS;\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Disable ISI\r
+//-----------------------------------------------------------------------------\r
+void ISI_Disable(void)\r
+{\r
+    AT91C_BASE_ISI->ISI_CR1 |= AT91C_ISI_DIS;\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Enable ISI interrupt\r
+/// \param  flag of interrupt to enable\r
+//-----------------------------------------------------------------------------\r
+void ISI_EnableInterrupt(unsigned int flag)\r
+{\r
+    AT91C_BASE_ISI->ISI_IER = flag;\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Disable ISI interrupt\r
+/// \param  flag of interrupt to disable\r
+//-----------------------------------------------------------------------------\r
+void ISI_DisableInterrupt(unsigned int flag)\r
+{\r
+    AT91C_BASE_ISI->ISI_IDR = flag;\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Return ISI status register\r
+/// \return Status of ISI register\r
+//-----------------------------------------------------------------------------\r
+unsigned int ISI_StatusRegister(void)\r
+{\r
+    return(AT91C_BASE_ISI->ISI_SR);\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Enable Codec path for capture next frame\r
+//-----------------------------------------------------------------------------\r
+void ISI_CodecPathFull(void)\r
+{\r
+    // The codec path is enabled and the next frame is captured.\r
+    // Both codec and preview datapaths are working simultaneously\r
+    AT91C_BASE_ISI->ISI_CR1 |= AT91C_ISI_CODEC_ON | AT91C_ISI_FULL;\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Set frame rate\r
+/// \param  frate frame rate capture\r
+/// \return \r
+//-----------------------------------------------------------------------------\r
+void ISI_SetFrame(unsigned int frate)\r
+{\r
+    if( frate > 7 ) {\r
+        TRACE_ERROR("FRate too big\n\r");\r
+        frate = 7;\r
+    }\r
+    AT91C_BASE_ISI->ISI_CR1 |= ((frate<<8) & AT91C_ISI_FRATE);\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Get the number of byte per pixels\r
+/// \param  bmpRgb BMP type can be YUV or RGB\r
+/// \return Number of byte for one pixel\r
+//-----------------------------------------------------------------------------\r
+unsigned char ISI_BytesForOnePixel(unsigned char bmpRgb)\r
+{\r
+    unsigned char nbByte_Pixel;\r
+\r
+    if (bmpRgb == RGB) {\r
+        if ((AT91C_BASE_ISI->ISI_CR2 & AT91C_ISI_RGB_MODE) == AT91C_ISI_RGB_MODE_RGB_565){\r
+            // RGB: 5:6:5 16bits/pixels\r
+            nbByte_Pixel = 2;\r
+        } \r
+        else {\r
+            // RGB: 8:8:8 24bits/pixels\r
+            nbByte_Pixel = 3;\r
+        }\r
+    } \r
+    else {\r
+        // YUV: 2 pixels for 4 bytes\r
+        nbByte_Pixel = 2;\r
+    }\r
+    return nbByte_Pixel;\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Reset ISI\r
+//-----------------------------------------------------------------------------\r
+void ISI_Reset(void)\r
+{\r
+    unsigned int timeout=0;\r
+\r
+    // Resets the image sensor interface.\r
+    // Finish capturing the current frame and then shut down the module.\r
+    AT91C_BASE_ISI->ISI_CR1 = AT91C_ISI_RST | AT91C_ISI_DIS;\r
+    // wait Software reset has completed successfully.\r
+    while( (!(volatile int)AT91C_BASE_ISI->ISI_SR & AT91C_ISI_SOFTRST)\r
+        && (timeout < 0x5000) ){\r
+        timeout++;\r
+    }\r
+    if( timeout == 0x5000 ) {\r
+        TRACE_ERROR("ISI-Reset timeout\n\r");\r
+    }\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// ISI initialize with the pVideo parameters.\r
+/// By default, put ISI in RGB mode 565, YCC mode 3, different value for\r
+/// Color Space Conversion Matrix Coefficient\r
+/// \param pVideo structure of video driver\r
+//-----------------------------------------------------------------------------\r
+void ISI_Init(AT91PS_VIDEO pVideo)\r
+{\r
+    ISI_Reset();\r
+\r
+    // AT91C_ISI_HSYNC_POL    Horizontal synchronisation polarity\r
+    // AT91C_ISI_VSYNC_POL    Vertical synchronisation polarity\r
+    // AT91C_ISI_PIXCLK_POL   Pixel Clock Polarity\r
+\r
+    // SLD pixel clock periods to wait before the beginning of a line.\r
+    // SFD lines are skipped at the beginning of the frame.\r
+    AT91C_BASE_ISI->ISI_CR1 |= ((pVideo->Hblank << 16) & AT91C_ISI_SLD)\r
+                             + ((pVideo->Vblank << 24) & AT91C_ISI_SFD);\r
+    TRACE_DEBUG("ISI_CR1=0x%X\n\r", AT91C_BASE_ISI->ISI_CR1);\r
+\r
+    // IM_VSIZE: Vertical size of the Image sensor [0..2047]\r
+    // Vertical size = IM_VSIZE + 1\r
+    // IM_HSIZE: Horizontal size of the Image sensor [0..2047]\r
+    // Horizontal size = IM_HSIZE + 1\r
+    // YCC_SWAP : YCC image data    \r
+    AT91C_BASE_ISI->ISI_CR2 =  ((pVideo->codec_vsize-1) & AT91C_ISI_IM_VSIZE)\r
+                            + (((pVideo->codec_hsize-1) << 16) & AT91C_ISI_IM_HSIZE)\r
+                            + AT91C_ISI_YCC_SWAP_YCC_MODE2;\r
+\r
+    if (pVideo->rgb_or_yuv == RGB) {\r
+        AT91C_BASE_ISI->ISI_CR2 |= AT91C_ISI_COL_SPACE | AT91C_ISI_RGB_MODE_RGB_565\r
+            | AT91C_ISI_RGB_CFG_RGB_DEFAULT;\r
+    }\r
+    else {\r
+    //    AT91C_BASE_HISI->ISI_CR2 &=  ~AT91C_ISI_COL_SPACE;    \r
+    }\r
+    TRACE_DEBUG("ISI_CR2=0x%X\n\r", AT91C_BASE_ISI->ISI_CR2);\r
+\r
+    // Vertical Preview size = PREV_VSIZE + 1 (480 max only in RGB mode).\r
+    // Horizontal Preview size = PREV_HSIZE + 1 (640 max only in RGB mode).    \r
+#if defined (AT91C_ID_LCDC)\r
+    if( (pVideo->lcd_vsize > 480) || (pVideo->lcd_hsize > 640)) {\r
+        TRACE_ERROR("Size LCD bad define\n\r");\r
+        AT91C_BASE_ISI->ISI_PSIZE = ((BOARD_LCD_HEIGHT-1) & AT91C_ISI_PREV_VSIZE)\r
+                                  + (((BOARD_LCD_WIDTH-1) << 16) & AT91C_ISI_PREV_HSIZE);\r
+    }\r
+    else {\r
+\r
+        AT91C_BASE_ISI->ISI_PSIZE = ((pVideo->lcd_vsize -1) & AT91C_ISI_PREV_VSIZE)\r
+                                  + (((pVideo->lcd_hsize -1) << 16) & AT91C_ISI_PREV_HSIZE);\r
+    }\r
+#endif\r
+\r
+\r
+    // DEC_FACTOR is 8-bit width, range is from 16 to 255. \r
+    // Values from 0 to 16 do not perform any decimation.\r
+    AT91C_BASE_ISI->ISI_PDECF = (16 * pVideo->codec_hsize) / pVideo->lcd_hsize;\r
+\r
+    TRACE_DEBUG("codec_hsize: %d\n\r", pVideo->codec_hsize);\r
+    TRACE_DEBUG("lcd_hsize: %d\n\r", pVideo->lcd_hsize);\r
+    TRACE_DEBUG("ISI_PDECF: %d\n\r", AT91C_BASE_ISI->ISI_PDECF);\r
+    if( AT91C_BASE_ISI->ISI_PDECF <16) {\r
+        TRACE_ERROR("ISI_PDECF, forbidden value: %d\n\r", AT91C_BASE_ISI->ISI_PDECF);\r
+        AT91C_BASE_ISI->ISI_PDECF = 16;\r
+    }\r
+\r
+    // Written with the address of the start of the preview frame buffer queue,\r
+    // reads as a pointer to the current buffer being used.\r
+    // The frame buffer is forced to word alignment.\r
+    AT91C_BASE_ISI->ISI_PPFBD = pVideo->Isi_fbd_base;\r
+\r
+    // This register contains codec datapath start address of buffer location.\r
+    // CODEC_DMA_ADDR: Base address for codec DMA\r
+    AT91C_BASE_ISI->ISI_CDBA  = pVideo->codec_fb_addr;\r
+\r
+    // C0: Color Space Conversion Matrix Coefficient C0\r
+    // C1: Color Space Conversion Matrix Coefficient C1\r
+    // C2: Color Space Conversion Matrix Coefficient C2\r
+    // C3: Color Space Conversion Matrix Coefficient C3\r
+    AT91C_BASE_ISI->ISI_Y2RSET0  = ( (0x95<< 0) & AT91C_ISI_Y2R_C0)\r
+                                 + ( (0xFF<< 8) & AT91C_ISI_Y2R_C1)\r
+                                 + ( (0x68<<16) & AT91C_ISI_Y2R_C2)\r
+                                 + ( (0x32<<24) & AT91C_ISI_Y2R_C3);\r
+\r
+    // C4: Color Space Conversion Matrix coefficient C4\r
+    // Yoff: Color Space Conversion Luminance 128 offset\r
+    // Croff: Color Space Conversion Red Chrominance 16 offset\r
+    // Cboff: Color Space Conversion Blue Chrominance 16 offset\r
+    AT91C_BASE_ISI->ISI_Y2RSET1  = ( (0xCC<< 0) & AT91C_ISI_Y2R_C4)\r
+                                 + ( AT91C_ISI_Y2R_YOFF_128)\r
+                                 + ( AT91C_ISI_Y2R_CROFF_16)\r
+                                 + ( AT91C_ISI_Y2R_CBOFF_16);\r
+}\r
+\r
+#endif // !defined (BOARD_ISI_V200)\r
+\r

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/isi/isi.h b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/isi/isi.h
new file mode 100644 (file)
index 0000000..0a81437
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/isi/isi.h
@@ -0,0 +1,99 @@
+/* ----------------------------------------------------------------------------\r
+ *         ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+//------------------------------------------------------------------------------\r
+/// \unit\r
+///\r
+/// !Purpose\r
+/// \r
+/// Interface for configuration the Image Sensor Interface (ISI) peripheral.\r
+/// \r
+/// !Usage\r
+/// \r
+/// -# ISI_Init: initialize ISI with default parameters\r
+/// -# ISI_EnableInterrupt: enable one or more interrupts\r
+/// -# ISI_DisableInterrupt: disable one or more interrupts\r
+/// -# ISI_Enable: enable isi module\r
+/// -# ISI_Disable: disable isi module\r
+/// -# ISI_CodecPathFull: enable codec path\r
+/// -# ISI_SetFrame: set frame rate\r
+/// -# ISI_BytesForOnePixel: return number of byte for one pixel\r
+/// -# ISI_StatusRegister: return ISI status register\r
+/// -# ISI_Reset: make a software reset\r
+//------------------------------------------------------------------------------\r
+\r
+#ifndef ISI_H\r
+#define ISI_H\r
+\r
+//------------------------------------------------------------------------------\r
+//         Types\r
+//------------------------------------------------------------------------------\r
+\r
+/// ISI descriptors\r
+typedef struct\r
+{\r
+    /// Current LCD index, used with AT91C_ISI_MAX_PREV_BUFFER\r
+    unsigned int CurrentLcdIndex;\r
+    /// set if Fifo Codec Empty is present\r
+    volatile unsigned int DisplayCodec;\r
+    /// upgrade for each Fifo Codec Overflow (statistics use)\r
+    unsigned int nb_codec_ovf;\r
+    /// upgrade for each Fifo Preview Overflow (statistics use)\r
+    unsigned int nb_prev_ovf;\r
+}ISI_Descriptors;\r
+\r
+/// Frame Buffer Descriptors\r
+typedef struct\r
+{\r
+    /// Address of the Current FrameBuffer\r
+    unsigned int Current;\r
+#if defined (BOARD_ISI_V200)\r
+    /// Address of the Control\r
+    unsigned int Control;\r
+#endif\r
+    /// Address of the Next FrameBuffer\r
+    unsigned int Next;\r
+}ISI_FrameBufferDescriptors;\r
+\r
+//------------------------------------------------------------------------------\r
+//         Exported functions\r
+//------------------------------------------------------------------------------\r
+extern void ISI_Enable(void);\r
+extern void ISI_Disable(void);\r
+extern void ISI_EnableInterrupt(unsigned int flag);\r
+extern void ISI_DisableInterrupt(unsigned int flag);\r
+extern void ISI_CodecPathFull(void);\r
+extern void ISI_SetFrame(unsigned int frate);\r
+extern unsigned char ISI_BytesForOnePixel(unsigned char bmpRgb);\r
+extern void ISI_Reset(void);\r
+extern void ISI_Init(AT91PS_VIDEO pVideo);\r
+extern unsigned int ISI_StatusRegister(void);\r
+\r
+#endif //#ifndef ISI_H\r
+\r

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/isi/isi2.c b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/isi/isi2.c
new file mode 100644 (file)
index 0000000..9ed61f8
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/isi/isi2.c
@@ -0,0 +1,246 @@
+/* ----------------------------------------------------------------------------\r
+ *         ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+//------------------------------------------------------------------------------\r
+//         Headers\r
+//------------------------------------------------------------------------------\r
+\r
+#include <board.h>\r
+#include <utility/trace.h>\r
+#include <utility/video.h>\r
+#include "isi.h"\r
+\r
+#if defined (BOARD_ISI_V200)\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Enable ISI\r
+//-----------------------------------------------------------------------------\r
+void ISI_Enable(void)\r
+{\r
+    AT91C_BASE_ISI->ISI_CTRL |= AT91C_ISI_EN_1;\r
+    while( (AT91C_BASE_ISI->ISI_SR & AT91C_ISI_EN_1)!=AT91C_ISI_EN_1);\r
+    AT91C_BASE_ISI->ISI_DMACHER |= AT91C_ISI_P_CH_EN_1;\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Disable ISI\r
+//-----------------------------------------------------------------------------\r
+void ISI_Disable(void)\r
+{\r
+    AT91C_BASE_ISI->ISI_CTRL |= AT91C_ISI_DIS_1;\r
+    AT91C_BASE_ISI->ISI_DMACHDR &= ~AT91C_ISI_P_CH_DIS_1;\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Enable ISI interrupt\r
+/// \param  flag of interrupt to enable\r
+//-----------------------------------------------------------------------------\r
+void ISI_EnableInterrupt(unsigned int flag)\r
+{\r
+    AT91C_BASE_ISI->ISI_IER = flag;\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Disable ISI interrupt\r
+/// \param  flag of interrupt to disable\r
+//-----------------------------------------------------------------------------\r
+void ISI_DisableInterrupt(unsigned int flag)\r
+{\r
+    AT91C_BASE_ISI->ISI_IDR = flag;\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Return ISI status register\r
+/// \return Status of ISI register\r
+//-----------------------------------------------------------------------------\r
+unsigned int ISI_StatusRegister(void)\r
+{\r
+    return(AT91C_BASE_ISI->ISI_SR);\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Enable Codec path for capture next frame\r
+//-----------------------------------------------------------------------------\r
+void ISI_CodecPathFull(void)\r
+{\r
+    // The codec path is enabled and the next frame is captured.\r
+    // Both codec and preview datapaths are working simultaneously\r
+    AT91C_BASE_ISI->ISI_CTRL |= AT91C_ISI_CDC_1;\r
+    AT91C_BASE_ISI->ISI_CFG1 |= AT91C_ISI_FULL;\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Set frame rate\r
+/// \param  frate frame rate capture\r
+/// \return \r
+//-----------------------------------------------------------------------------\r
+void ISI_SetFrame(unsigned int frate)\r
+{\r
+    if( frate > 7 ) {\r
+        TRACE_ERROR("FRate too big\n\r");\r
+        frate = 7;\r
+    }\r
+    AT91C_BASE_ISI->ISI_CFG1 |= ((frate<<8) & AT91C_ISI_FRATE);\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Get the number of byte per pixels\r
+/// \param  bmpRgb BMP type can be YUV or RGB\r
+/// \return Number of byte for one pixel\r
+//-----------------------------------------------------------------------------\r
+unsigned char ISI_BytesForOnePixel(unsigned char bmpRgb)\r
+{\r
+    unsigned char nbByte_Pixel;\r
+\r
+    if (bmpRgb == RGB) {\r
+        if ((AT91C_BASE_ISI->ISI_CFG2 & AT91C_ISI_RGB_MODE) == AT91C_ISI_RGB_MODE_RGB_565){\r
+            // RGB: 5:6:5 16bits/pixels\r
+            nbByte_Pixel = 2;\r
+        } \r
+        else {\r
+            // RGB: 8:8:8 24bits/pixels\r
+            nbByte_Pixel = 3;\r
+        }\r
+    } \r
+    else {\r
+        // YUV: 2 pixels for 4 bytes\r
+        nbByte_Pixel = 2;\r
+    }\r
+    return nbByte_Pixel;\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Reset ISI\r
+//-----------------------------------------------------------------------------\r
+void ISI_Reset(void)\r
+{\r
+    unsigned int timeout=0;\r
+\r
+    // Resets the image sensor interface.\r
+    // Finish capturing the current frame and then shut down the module.\r
+    AT91C_BASE_ISI->ISI_CTRL = AT91C_ISI_SRST_1 | AT91C_ISI_DIS_1;\r
+    // wait Software reset has completed successfully.\r
+    while( (!(volatile int)AT91C_BASE_ISI->ISI_SR & AT91C_ISI_SRST)\r
+        && (timeout < 0x5000) ){\r
+        timeout++;\r
+    }\r
+    if( timeout == 0x5000 ) {\r
+        TRACE_ERROR("ISI-Reset timeout\n\r");\r
+    }\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// ISI initialize\r
+/// \param pVideo structure of video driver\r
+//-----------------------------------------------------------------------------\r
+void ISI_Init(AT91PS_VIDEO pVideo)\r
+{\r
+    ISI_Reset();\r
+\r
+    // AT91C_ISI_HSYNC_POL    Horizontal synchronisation polarity\r
+    // AT91C_ISI_VSYNC_POL    Vertical synchronisation polarity\r
+    // AT91C_ISI_PIXCLK_POL   Pixel Clock Polarity\r
+\r
+    // SLD pixel clock periods to wait before the beginning of a line.\r
+    // SFD lines are skipped at the beginning of the frame.\r
+    AT91C_BASE_ISI->ISI_CFG1 |= ((pVideo->Hblank << 16) & AT91C_ISI_SLD)\r
+                              + ((pVideo->Vblank << 24) & AT91C_ISI_SFD);\r
+    TRACE_DEBUG("ISI_CFG1=0x%X\n\r", AT91C_BASE_ISI->ISI_CFG1);\r
+\r
+    // IM_VSIZE: Vertical size of the Image sensor [0..2047]\r
+    // Vertical size = IM_VSIZE + 1\r
+    // IM_HSIZE: Horizontal size of the Image sensor [0..2047]\r
+    // Horizontal size = IM_HSIZE + 1\r
+    // YCC_SWAP : YCC image data    \r
+    AT91C_BASE_ISI->ISI_CFG2 = ((pVideo->codec_vsize-1) & AT91C_ISI_IM_VSIZE)\r
+                            + (((pVideo->codec_hsize-1) << 16) & AT91C_ISI_IM_HSIZE)\r
+                            + AT91C_ISI_YCC_SWAP_YCC_MODE2;\r
+\r
+    if (pVideo->rgb_or_yuv == RGB) {\r
+        AT91C_BASE_ISI->ISI_CFG2 |= AT91C_ISI_COL_SPACE | AT91C_ISI_RGB_MODE_RGB_565\r
+            | AT91C_ISI_RGB_CFG_RGB_DEFAULT;\r
+    }\r
+    else {\r
+    //    AT91C_BASE_HISI->ISI_CFG2 &=  ~AT91C_ISI_COL_SPACE;    \r
+    }\r
+    TRACE_DEBUG("ISI_CFG2=0x%X\n\r", AT91C_BASE_ISI->ISI_CFG2);\r
+\r
+    // Vertical Preview size = PREV_VSIZE + 1 (480 max only in RGB mode).\r
+    // Horizontal Preview size = PREV_HSIZE + 1 (640 max only in RGB mode).    \r
+#if defined (AT91C_ID_LCDC)\r
+    if( (pVideo->lcd_vsize > 480) || (pVideo->lcd_hsize > 640)) {\r
+        TRACE_ERROR("Size LCD bad define\n\r");\r
+        AT91C_BASE_ISI->ISI_PSIZE = ((BOARD_LCD_HEIGHT-1) & AT91C_ISI_PREV_VSIZE)\r
+                                  + (((BOARD_LCD_WIDTH-1) << 16) & AT91C_ISI_PREV_HSIZE);\r
+    }\r
+    else {\r
+\r
+        AT91C_BASE_ISI->ISI_PSIZE = ((pVideo->lcd_vsize -1) & AT91C_ISI_PREV_VSIZE)\r
+                                  + (((pVideo->lcd_hsize -1) << 16) & AT91C_ISI_PREV_HSIZE);\r
+    }\r
+#endif\r
+\r
+\r
+    // DEC_FACTOR is 8-bit width, range is from 16 to 255. \r
+    // Values from 0 to 16 do not perform any decimation.\r
+    AT91C_BASE_ISI->ISI_PDECF = (16 * pVideo->codec_hsize) / pVideo->lcd_hsize;\r
+\r
+    TRACE_DEBUG("codec_hsize: %d\n\r", pVideo->codec_hsize);\r
+    TRACE_DEBUG("lcd_hsize: %d\n\r", pVideo->lcd_hsize);\r
+    TRACE_DEBUG("ISI_PDECF: %d\n\r", AT91C_BASE_ISI->ISI_PDECF);\r
+    if( AT91C_BASE_ISI->ISI_PDECF <16) {\r
+        TRACE_ERROR("ISI_PDECF, forbidden value: %d\n\r", AT91C_BASE_ISI->ISI_PDECF);\r
+        AT91C_BASE_ISI->ISI_PDECF = 16;\r
+    }\r
+\r
+    AT91C_BASE_ISI->ISI_DMAPDSCR = pVideo->Isi_fbd_base;\r
+    AT91C_BASE_ISI->ISI_DMAPCTRL = AT91C_ISI_P_FETCH_ENABLE;\r
+    AT91C_BASE_ISI->ISI_DMAPADDR = pVideo->lcd_fb_addr;\r
+\r
+    // C0: Color Space Conversion Matrix Coefficient C0\r
+    // C1: Color Space Conversion Matrix Coefficient C1\r
+    // C2: Color Space Conversion Matrix Coefficient C2\r
+    // C3: Color Space Conversion Matrix Coefficient C3\r
+    AT91C_BASE_ISI->ISI_Y2RSET0  = ( (0x95<< 0) & AT91C_ISI_Y2R_C0)\r
+                                 + ( (0xFF<< 8) & AT91C_ISI_Y2R_C1)\r
+                                 + ( (0x68<<16) & AT91C_ISI_Y2R_C2)\r
+                                 + ( (0x32<<24) & AT91C_ISI_Y2R_C3);\r
+\r
+    // C4: Color Space Conversion Matrix coefficient C4\r
+    // Yoff: Color Space Conversion Luminance 128 offset\r
+    // Croff: Color Space Conversion Red Chrominance 16 offset\r
+    // Cboff: Color Space Conversion Blue Chrominance 16 offset\r
+    AT91C_BASE_ISI->ISI_Y2RSET1  = ( (0xCC<< 0) & AT91C_ISI_Y2R_C4)\r
+                                 + ( AT91C_ISI_Y2R_YOFF_128)\r
+                                 + ( AT91C_ISI_Y2R_CROFF_16)\r
+                                 + ( AT91C_ISI_Y2R_CBOFF_16);\r
+}\r
+\r
+#endif // defined (BOARD_ISI_V200)\r
+\r

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/lcd/lcd.c b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/lcd/lcd.c
new file mode 100644 (file)
index 0000000..f5fab92
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/lcd/lcd.c
@@ -0,0 +1,466 @@
+/* ----------------------------------------------------------------------------\r
+ *         ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+#include <board.h>\r
+\r
+#if defined (AT91C_ID_LCDC)\r
+\r
+//------------------------------------------------------------------------------\r
+//         Headers\r
+//------------------------------------------------------------------------------\r
+\r
+#include "lcd.h"\r
+#include <utility/assert.h>\r
+#include <utility/trace.h>\r
+\r
+\r
+//------------------------------------------------------------------------------\r
+//         Exported functions\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+/// Enables the LCD controller, after waiting for the specified number of\r
+/// frames.\r
+/// \param frames  Number of frames before the LCD is enabled.\r
+//------------------------------------------------------------------------------\r
+void LCD_Enable(unsigned int frames)\r
+{\r
+    TRACE_DEBUG("LCD enable\n\r");\r
+    ASSERT((frames & 0xFFFFFF80) == 0,\r
+           "LCD_Enable: Wrong frames value.\n\r");\r
+    if( (AT91C_BASE_LCDC->LCDC_PWRCON & AT91C_LCDC_BUSY) == AT91C_LCDC_BUSY ) {\r
+        TRACE_DEBUG("LCD BUSY E\n\r");\r
+    }\r
+    AT91C_BASE_LCDC->LCDC_PWRCON = AT91C_LCDC_PWR | (frames << 1);\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Disables the LCD controller, after waiting for the specified number of\r
+/// frames.\r
+/// \param frames  Number of frames before the LCD is shut down.\r
+//------------------------------------------------------------------------------\r
+void LCD_Disable(unsigned int frames)\r
+{\r
+    TRACE_DEBUG("LCD disable\n\r");\r
+    ASSERT((frames & 0xFFFFFF80) == 0,\r
+           "LCD_Disable: Wrong frames value.\n\r");\r
+    // Remove AT91C_LCDC_PWR\r
+    AT91C_BASE_LCDC->LCDC_PWRCON = frames << 1;\r
+    // wait LCDC Core is in idle state\r
+    while( (AT91C_BASE_LCDC->LCDC_PWRCON & AT91C_LCDC_BUSY) == AT91C_LCDC_BUSY ) {\r
+    }\r
+    TRACE_DEBUG("LCD is in IDLE state\n\r");\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Enables the DMA of the LCD controller.\r
+//------------------------------------------------------------------------------\r
+void LCD_EnableDma(void)\r
+{\r
+    if( (AT91C_BASE_LCDC->LCDC_DMACON & AT91C_LCDC_DMABUSY) == AT91C_LCDC_DMABUSY ) {\r
+        TRACE_DEBUG("LCD DMA BUSY E\n\r");\r
+    }\r
+    AT91C_BASE_LCDC->LCDC_DMACON = AT91C_LCDC_DMAEN;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Disables the DMA of the LCD controller.\r
+//------------------------------------------------------------------------------\r
+void LCD_DisableDma(void)\r
+{\r
+    AT91C_BASE_LCDC->LCDC_DMACON = 0;\r
+    // wait LCDC DMA is in idle state\r
+    while( (AT91C_BASE_LCDC->LCDC_DMACON & AT91C_LCDC_DMABUSY) == AT91C_LCDC_DMABUSY ) {\r
+    }\r
+    TRACE_DEBUG("LCD DMA is in IDLE state\n\r");\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Enables the selected LDC interrupt sources.\r
+/// \param sources  Interrupt sources to enable.\r
+//------------------------------------------------------------------------------\r
+void LCD_EnableInterrupts(unsigned int sources)\r
+{\r
+    AT91C_BASE_LCDC->LCDC_IER = sources;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Configures the internal clock of the LCD controller given the master clock of\r
+/// the system and the desired pixel clock in MHz.\r
+/// \param masterClock  Master clock frequency.\r
+/// \param pixelClock  Pixel clock frequency.\r
+//------------------------------------------------------------------------------\r
+void LCD_SetPixelClock(unsigned int masterClock, unsigned int pixelClock)\r
+{\r
+    AT91C_BASE_LCDC->LCDC_LCDCON1 = ((masterClock / 2 / pixelClock) - 2) << 12;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// DMA reset\r
+//------------------------------------------------------------------------------\r
+void LCD_DMAReset(void)\r
+{\r
+    // DMA Module should be reset only when disabled and in idle state\r
+    if( AT91C_LCDC_DMABUSY == (AT91C_BASE_LCDC->LCDC_DMACON & AT91C_LCDC_DMABUSY)) {\r
+        TRACE_ERROR("LCD BUSY so NO DMA RESET\n\r");\r
+    }\r
+    if( AT91C_LCDC_DMAEN == (AT91C_BASE_LCDC->LCDC_DMACON & AT91C_LCDC_DMAEN)) {\r
+        TRACE_ERROR("DMA Enabled, so NO DMA RESET\n\r");\r
+    }\r
+    AT91C_BASE_LCDC->LCDC_DMACON = AT91C_LCDC_DMARST;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Sets the type of display used with the LCD controller.\r
+/// \param displayType  Type of display used.\r
+//------------------------------------------------------------------------------\r
+void LCD_SetDisplayType(unsigned int displayType)\r
+{\r
+    unsigned int value;\r
+\r
+    ASSERT((displayType & ~AT91C_LCDC_DISTYPE) == 0,\r
+           "LCD_SetDisplayType: Wrong display type value.\n\r");\r
+\r
+    value = AT91C_BASE_LCDC->LCDC_LCDCON2;\r
+    value &= ~AT91C_LCDC_DISTYPE;\r
+    value |= displayType;\r
+    AT91C_BASE_LCDC->LCDC_LCDCON2 = value;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Sets the scan mode used by the LCD (either single scan or double-scan).\r
+/// \param scanMode  Scan mode to use.\r
+//------------------------------------------------------------------------------\r
+void LCD_SetScanMode(unsigned int scanMode)\r
+{\r
+    unsigned int value;\r
+\r
+    ASSERT((scanMode & ~AT91C_LCDC_SCANMOD) == 0,\r
+           "LCD_SetScanMode: Wrong scan mode value.\n\r");\r
+\r
+    value = AT91C_BASE_LCDC->LCDC_LCDCON2;\r
+    value &= ~AT91C_LCDC_SCANMOD;\r
+    value |= scanMode;\r
+    AT91C_BASE_LCDC->LCDC_LCDCON2 = value;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Sets the number of bits per pixel used by the LCD display.\r
+/// \param bitsPerPixel  Number of bits per pixel to use.\r
+//------------------------------------------------------------------------------\r
+void LCD_SetBitsPerPixel(unsigned int bitsPerPixel)\r
+{\r
+    unsigned int value;\r
+\r
+    ASSERT((bitsPerPixel & ~AT91C_LCDC_PIXELSIZE) == 0,\r
+           "LCD_SetScanMode: Wrong bitsPerPixel value.\n\r");\r
+\r
+    value = AT91C_BASE_LCDC->LCDC_LCDCON2;\r
+    value &= ~AT91C_LCDC_PIXELSIZE;\r
+    value |= bitsPerPixel;\r
+    AT91C_BASE_LCDC->LCDC_LCDCON2 = value;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Sets the LCDD, LCDVSYNC, LCDHSYNC, LCDDOTCLK and LCDDEN signal polarities.\r
+/// \param lcdd  LCDD signal polarity.\r
+/// \param lcdvsync  LCDVSYNC signal polarity.\r
+/// \param lcdhsync  LCDHSYNC signal polarity.\r
+/// \param lcddotclk  LCDDOTCLK signal polarity.\r
+/// \param lcdden  LCDDEN signal polarity.\r
+//------------------------------------------------------------------------------\r
+void LCD_SetPolarities(\r
+    unsigned int lcdd,\r
+    unsigned int lcdvsync,\r
+    unsigned int lcdhsync,\r
+    unsigned int lcddotclk,\r
+    unsigned int lcdden)\r
+{\r
+    unsigned int value;\r
+\r
+    ASSERT((lcdd & ~AT91C_LCDC_INVVD) == 0,\r
+           "LCD_SetPolarities: Wrong lcdd value.\n\r");\r
+    ASSERT((lcdvsync & ~AT91C_LCDC_INVFRAME) == 0,\r
+           "LCD_SetPolarities: Wrong lcdvsync value.\n\r");\r
+    ASSERT((lcdhsync & ~AT91C_LCDC_INVLINE) == 0,\r
+           "LCD_SetPolarities: Wrong lcdhsync value.\n\r");\r
+    ASSERT((lcddotclk & ~AT91C_LCDC_INVCLK) == 0,\r
+           "LCD_SetPolarities: Wrong lcddotclk value.\n\r");\r
+    ASSERT((lcdden & ~AT91C_LCDC_INVDVAL) == 0,\r
+           "LCD_SetPolarities: Wrong lcdden value.\n\r");\r
+\r
+    value = AT91C_BASE_LCDC->LCDC_LCDCON2;\r
+    value &= 0xFFFFE0FF;\r
+    value |= lcdd | lcdvsync | lcdhsync | lcddotclk | lcdden;\r
+    AT91C_BASE_LCDC->LCDC_LCDCON2 = value;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Sets the LCD clock mode, i.e. always active or active only during display\r
+/// period.\r
+/// \param clockMode  Clock mode to use.\r
+//------------------------------------------------------------------------------\r
+void LCD_SetClockMode(unsigned int clockMode)\r
+{\r
+    unsigned int value;\r
+\r
+    ASSERT((clockMode & ~AT91C_LCDC_CLKMOD) == 0,\r
+           "LCD_SetScanMode: Wrong scan mode value.\n\r");\r
+\r
+    value = AT91C_BASE_LCDC->LCDC_LCDCON2;\r
+    value &= ~AT91C_LCDC_CLKMOD;\r
+    value |= clockMode;\r
+    AT91C_BASE_LCDC->LCDC_LCDCON2 = value;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Sets the format of the frame buffer memory.\r
+/// \param format  Memory ordering format.\r
+//------------------------------------------------------------------------------\r
+void LCD_SetMemoryFormat(unsigned int format)\r
+{\r
+    unsigned int value;\r
+\r
+    ASSERT((format & ~AT91C_LCDC_MEMOR) == 0,\r
+           "LCD_SetMemoryFormat: Wrong memory format value.\n\r");\r
+\r
+    value = AT91C_BASE_LCDC->LCDC_LCDCON2;\r
+    value &= ~AT91C_LCDC_MEMOR;\r
+    value |= format;\r
+    AT91C_BASE_LCDC->LCDC_LCDCON2 = value;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Sets the size in pixel of the LCD display.\r
+/// \param width  Width in pixel of the LCD display.\r
+/// \param height  Height in pixel of the LCD display.\r
+//------------------------------------------------------------------------------\r
+void LCD_SetSize(unsigned int width, unsigned int height)\r
+{\r
+    ASSERT(((width - 1) & 0xFFFFF800) == 0,\r
+           "LCD_SetSize: Wrong width value.\n\r");\r
+    ASSERT(((height - 1) & 0xFFFFF800) == 0,\r
+           "LCD_SetSize: Wrong height value.\n\r");\r
+\r
+    AT91C_BASE_LCDC->LCDC_LCDFRCFG = ((width - 1) << 21) | (height - 1);\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Sets the vertical timings of the LCD controller. Only meaningful when\r
+/// using a TFT display.\r
+/// \param vfp  Number of idle lines at the end of a frame.\r
+/// \param vbp  Number of idle lines at the beginning of a frame.\r
+/// \param vpw  Vertical synchronization pulse width in number of lines.\r
+/// \param vhdly  Delay between LCDVSYNC edge and LCDHSYNC rising edge, in\r
+///               LCDDOTCLK cycles.\r
+//------------------------------------------------------------------------------\r
+void LCD_SetVerticalTimings(\r
+    unsigned int vfp,\r
+    unsigned int vbp,\r
+    unsigned int vpw,\r
+    unsigned int vhdly)\r
+{\r
+    ASSERT((vfp & 0xFFFFFF00) == 0,\r
+           "LCD_SetVerticalTimings: Wrong vfp value.\n\r");\r
+    ASSERT((vbp & 0xFFFFFF00) == 0,\r
+           "LCD_SetVerticalTimings: Wrong vbp value.\n\r");\r
+    ASSERT(((vpw-1) & 0xFFFFFFC0) == 0,\r
+           "LCD_SetVerticalTimings: Wrong vpw value.\n\r");\r
+    ASSERT(((vhdly-1) & 0xFFFFFFF0) == 0,\r
+           "LCD_SetVerticalTimings: Wrong vhdly value.\n\r");\r
+\r
+    AT91C_BASE_LCDC->LCDC_TIM1 = vfp\r
+                                 | (vbp << 8)\r
+                                 | ((vpw-1) << 16)\r
+                                 | ((vhdly-1) << 24);\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Sets the horizontal timings of the LCD controller. Meaningful for both\r
+/// STN and TFT displays.\r
+/// \param hbp  Number of idle LCDDOTCLK cycles at the beginning of a line.\r
+/// \param hpw  Width of the LCDHSYNC pulse, in LCDDOTCLK cycles.\r
+/// \param hfp  Number of idel LCDDOTCLK cycles at the end of a line.\r
+//------------------------------------------------------------------------------\r
+void LCD_SetHorizontalTimings(\r
+    unsigned int hbp,\r
+    unsigned int hpw,\r
+    unsigned int hfp)\r
+{\r
+    ASSERT(((hbp-1) & 0xFFFFFF00) == 0,\r
+           "LCD_SetHorizontalTimings: Wrong hbp value.\n\r");\r
+    ASSERT(((hpw-1) & 0xFFFFFFC0) == 0,\r
+           "LCD_SetHorizontalTimings: Wrong hpw value.\n\r");\r
+    ASSERT(((hfp-1) & 0xFFFFFF00) == 0,\r
+           "LCD_SetHorizontalTimings: Wrong hfp value.\n\r");\r
+\r
+    AT91C_BASE_LCDC->LCDC_TIM2 = (hbp-1) | ((hpw-1) << 8) | ((hfp-1) << 24);\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Sets the address of the frame buffer in the LCD controller DMA. When using\r
+/// dual-scan mode, this is the upper frame buffer.\r
+/// \param address  Frame buffer address.\r
+//------------------------------------------------------------------------------\r
+void* LCD_SetFrameBufferAddress(void *address)\r
+{\r
+    void *pOldBuffer;\r
+    \r
+    pOldBuffer = (void *) AT91C_BASE_LCDC->LCDC_BA1;\r
+    AT91C_BASE_LCDC->LCDC_BA1 = (unsigned int) address;\r
+    \r
+    return pOldBuffer;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Sets the size in pixels of a frame (height * width * bpp).\r
+/// \param frameSize  Size of frame in pixels.\r
+//------------------------------------------------------------------------------\r
+void LCD_SetFrameSize(unsigned int frameSize)\r
+{\r
+    ASSERT((frameSize & 0xFF800000) == 0,\r
+           "LCD_SetFrameSize: Wrong frameSize value.\n\r");\r
+\r
+    AT91C_BASE_LCDC->LCDC_FRMCFG = (frameSize& AT91C_LCDC_FRSIZE)\r
+                                 | (AT91C_BASE_LCDC->LCDC_FRMCFG & AT91C_LCDC_BLENGTH);\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Sets the DMA controller burst length.\r
+/// \param burstLength  Desired burst length.\r
+//------------------------------------------------------------------------------\r
+void LCD_SetBurstLength(unsigned int burstLength)\r
+{\r
+    ASSERT(((burstLength-1) & 0xFFFFFF80) == 0,\r
+           "LCD_SetBurstLength: Wrong burstLength value.\n\r");\r
+\r
+    AT91C_BASE_LCDC->LCDC_FRMCFG &= ~AT91C_LCDC_BLENGTH;\r
+    AT91C_BASE_LCDC->LCDC_FRMCFG |= (((burstLength-1) << 24) & AT91C_LCDC_BLENGTH);\r
+\r
+    AT91C_BASE_LCDC->LCDC_FIFO = (2048 - (2 * burstLength + 3)) & AT91C_LCDC_FIFOTH;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Sets the prescaler value of the contrast control PWM.\r
+/// \param prescaler  Desired prescaler value.\r
+//------------------------------------------------------------------------------\r
+void LCD_SetContrastPrescaler(unsigned int prescaler)\r
+{\r
+    ASSERT((prescaler & ~AT91C_LCDC_PS) == 0,\r
+           "LCD_SetContrastPrescaler: Wrong prescaler value\n\r");\r
+\r
+    AT91C_BASE_LCDC->LCDC_CTRSTCON &= ~AT91C_LCDC_PS;\r
+    AT91C_BASE_LCDC->LCDC_CTRSTCON |= prescaler;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Sets the polarity of the contrast PWM.\r
+/// \param polarity  PWM polarity\r
+//------------------------------------------------------------------------------\r
+void LCD_SetContrastPolarity(unsigned int polarity)\r
+{\r
+    ASSERT((polarity & ~AT91C_LCDC_POL) == 0,\r
+           "LCD_SetContrastPolarity: Wrong polarity value\n\r");\r
+\r
+    AT91C_BASE_LCDC->LCDC_CTRSTCON &= ~AT91C_LCDC_POL;\r
+    AT91C_BASE_LCDC->LCDC_CTRSTCON |= polarity;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Sets the threshold value of the constrast PWM.\r
+/// \param value  PWM threshold value.\r
+//------------------------------------------------------------------------------\r
+void LCD_SetContrastValue(unsigned int value)\r
+{\r
+    ASSERT((value & ~AT91C_LCDC_CVAL) == 0,\r
+           "LCD_SetContrastValue: Wrong value.\n\r");\r
+\r
+    AT91C_BASE_LCDC->LCDC_CTRSTVAL = value;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Enables the contrast PWM generator.\r
+//------------------------------------------------------------------------------\r
+void LCD_EnableContrast(void)\r
+{\r
+    AT91C_BASE_LCDC->LCDC_CTRSTCON |= AT91C_LCDC_ENA_PWMGEMENABLED;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Decode the RGB file\r
+/// \param file  Buffer which holds the RGB file.\r
+/// \param bufferLCD  Buffer in which to store the decoded image adapted to LCD.\r
+/// \param width  Buffer width in pixels.\r
+/// \param height  Buffer height in pixels.\r
+/// \param bpp  Number of bits per pixels that the buffer stores.\r
+//------------------------------------------------------------------------------\r
+void LCD_DecodeRGB(\r
+    unsigned char *file,\r
+    unsigned char *bufferLCD,\r
+    unsigned int width,\r
+    unsigned int height,\r
+    unsigned char bpp)\r
+{\r
+    unsigned int offsetLine=0, offsetLCD=0;\r
+    unsigned int offset=1;\r
+\r
+    while( offset < (BOARD_LCD_HEIGHT)) {\r
+        //TRACE_DEBUG("LCD:%d LINE:%d off:%d\n\r", offsetLCD,  offsetLine, offset);\r
+        if( width < BOARD_LCD_WIDTH ) {\r
+            //TRACE_DEBUG("width < BOARD_LCD_WIDTH\n\r");\r
+            while( offsetLine < (width*offset*(bpp/8)) ) {\r
+                bufferLCD[offsetLCD] = file[offsetLine];\r
+                offsetLine++;\r
+                offsetLCD++;\r
+            }\r
+            //TRACE_DEBUG("add white\n\r");\r
+            while( offsetLCD < (BOARD_LCD_WIDTH*offset*(bpp/8)) ) {\r
+                bufferLCD[offsetLCD] = 0;\r
+                //offsetLine++;\r
+                offsetLCD++;\r
+            }\r
+        }\r
+        else {\r
+            //TRACE_DEBUG(">");\r
+            while( offsetLCD < (BOARD_LCD_WIDTH*offset*(bpp/8)) ) {\r
+                bufferLCD[offsetLCD] = file[offsetLine];\r
+                offsetLine++;\r
+                offsetLCD++;\r
+            }\r
+            //TRACE_DEBUG("r ");\r
+            while( offsetLine < (width*offset*(bpp/8)) ) {\r
+                offsetLine++;\r
+            }            \r
+        }\r
+        offset++;\r
+    }        \r
+}\r
+\r
+#endif\r
+\r

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/lcd/lcd.h b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/lcd/lcd.h
new file mode 100644 (file)
index 0000000..5974aaa
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/lcd/lcd.h
@@ -0,0 +1,124 @@
+/* ----------------------------------------------------------------------------\r
+ *         ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+//------------------------------------------------------------------------------\r
+/// \unit\r
+///\r
+/// !Purpose\r
+///\r
+/// Interface for configuration the LCD Controller (LCDC) peripheral.\r
+///\r
+/// !Usage\r
+///\r
+/// -# Decode the RGB file to designated buffer using LCD_DecodeRGB().\r
+/// -# Sets the address of the frame buffer in the LCD controller DMA using\r
+/// LCD_SetFrameBufferAddress().\r
+/// -# LCD Configuration functions prefixed with "LCD_Set" refer to \r
+/// the functions in the #Overview# tab.\r
+/// \r
+/// Please refer to the list of functions in the #Overview# tab of this unit\r
+/// for more detailed information.\r
+//------------------------------------------------------------------------------\r
+\r
+#ifndef LCD_H\r
+#define LCD_H\r
+\r
+//------------------------------------------------------------------------------\r
+//         Exported functions\r
+//------------------------------------------------------------------------------\r
+\r
+extern void LCD_Enable(unsigned int frames);\r
+\r
+extern void LCD_Disable(unsigned int frames);\r
+\r
+extern void LCD_EnableDma(void);\r
+\r
+extern void LCD_DisableDma(void);\r
+\r
+extern void LCD_EnableInterrupts(unsigned int sources);\r
+\r
+extern void LCD_SetPixelClock(unsigned int masterClock, unsigned int pixelClock);\r
+\r
+extern void LCD_SetDisplayType(unsigned int displayType);\r
+\r
+extern void LCD_SetScanMode(unsigned int scanMode);\r
+\r
+extern void LCD_SetBitsPerPixel(unsigned int bitsPerPixel);\r
+\r
+extern void LCD_SetPolarities(\r
+    unsigned int lcdd,\r
+    unsigned int lcdvsync,\r
+    unsigned int lcdhsync,\r
+    unsigned int lcddotclk,\r
+    unsigned int lcdden);\r
+\r
+extern void LCD_SetClockMode(unsigned int clockMode);\r
+\r
+extern void LCD_SetMemoryFormat(unsigned int format);\r
+\r
+extern void LCD_SetSize(unsigned int width, unsigned int height);\r
+\r
+extern void LCD_SetVerticalTimings(\r
+    unsigned int vfp,\r
+    unsigned int vbp,\r
+    unsigned int vpw,\r
+    unsigned int vhdly);\r
+\r
+extern void LCD_SetHorizontalTimings(\r
+    unsigned int hbp,\r
+    unsigned int hpw,\r
+    unsigned int hfp);\r
+\r
+extern void* LCD_SetFrameBufferAddress(void *address);\r
+\r
+extern void LCD_SetFrameSize(unsigned int frameSize);\r
+\r
+extern void LCD_SetBurstLength(unsigned int burstLength);\r
+\r
+extern void LCD_SetContrastPrescaler(unsigned int prescaler);\r
+\r
+extern void LCD_SetContrastPolarity(unsigned int polarity);\r
+\r
+extern void LCD_SetContrastValue(unsigned int value);\r
+\r
+extern void LCD_EnableContrast(void);\r
+\r
+extern void LCD_SetPixelClock(unsigned int masterClock, unsigned int pixelClock);\r
+\r
+extern void LCD_DMAReset(void);\r
+\r
+extern void LCD_DecodeRGB(\r
+    unsigned char *file,\r
+    unsigned char *bufferLCD,\r
+    unsigned int width,\r
+    unsigned int height,\r
+    unsigned char bpp);\r
+\r
+#endif //#ifndef LCD_H\r
+\r

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/mci/mci.c b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/mci/mci.c
new file mode 100644 (file)
index 0000000..6ec35d4
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/mci/mci.c
@@ -0,0 +1,580 @@
+/* ----------------------------------------------------------------------------\r
+ *         ATMEL Microcontroller Software Support\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+//------------------------------------------------------------------------------\r
+//         Headers\r
+//------------------------------------------------------------------------------\r
+\r
+#include "mci.h"\r
+#include <utility/assert.h>\r
+#include <utility/trace.h>\r
+\r
+//------------------------------------------------------------------------------\r
+//         Local constants\r
+//------------------------------------------------------------------------------\r
+\r
+/// Bit mask for status register errors.\r
+#define STATUS_ERRORS (AT91C_MCI_UNRE  \\r
+                       | AT91C_MCI_OVRE \\r
+                       | AT91C_MCI_DTOE \\r
+                       | AT91C_MCI_DCRCE \\r
+                       | AT91C_MCI_RTOE \\r
+                       | AT91C_MCI_RENDE \\r
+                       | AT91C_MCI_RCRCE \\r
+                       | AT91C_MCI_RDIRE \\r
+                       | AT91C_MCI_RINDE)\r
+\r
+/// MCI data timeout configuration with 1048576 MCK cycles between 2 data transfers.\r
+#define DTOR_1MEGA_CYCLES           (AT91C_MCI_DTOCYC | AT91C_MCI_DTOMUL)\r
+\r
+/// MCI MR: disable MCI Clock when FIFO is full\r
+#ifndef AT91C_MCI_WRPROOF\r
+    #define AT91C_MCI_WRPROOF 0\r
+#endif\r
+#ifndef AT91C_MCI_RDPROOF\r
+    #define AT91C_MCI_RDPROOF 0\r
+#endif\r
+\r
+#define SDCARD_APP_OP_COND_CMD      (41 | AT91C_MCI_SPCMD_NONE  | AT91C_MCI_RSPTYP_48   | AT91C_MCI_TRCMD_NO )\r
+#define MMC_SEND_OP_COND_CMD        (1  | AT91C_MCI_TRCMD_NO    | AT91C_MCI_SPCMD_NONE  | AT91C_MCI_RSPTYP_48 | AT91C_MCI_OPDCMD)\r
+\r
+\r
+#define DISABLE    0    // Disable MCI interface\r
+#define ENABLE     1    // Enable MCI interface\r
+\r
+\r
+//------------------------------------------------------------------------------\r
+//         Local macros\r
+//------------------------------------------------------------------------------\r
+\r
+/// Used to write in PMC registers.\r
+#define WRITE_PMC(pPmc, regName, value)     pPmc->regName = (value)\r
+\r
+/// Used to write in MCI registers.\r
+#define WRITE_MCI(pMci, regName, value)     pMci->regName = (value)\r
+\r
+/// Used to read from MCI registers.\r
+#define READ_MCI(pMci, regName)             (pMci->regName)\r
+\r
+//------------------------------------------------------------------------------\r
+//         Global functions\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+/// Enable/disable a MCI driver instance.\r
+/// \param pMci  Pointer to a MCI driver instance.\r
+/// \param enb  0 for disable MCI and 1 for enable MCI.\r
+//------------------------------------------------------------------------------\r
+void MCI_Enable(Mci *pMci, unsigned char enb)\r
+{\r
+    AT91S_MCI *pMciHw = pMci->pMciHw;\r
+\r
+    SANITY_CHECK(pMci);\r
+    SANITY_CHECK(pMci->pMciHw);\r
+\r
+    // Set the Control Register: Enable/Disable MCI interface clock\r
+    if(enb == DISABLE) {\r
+        WRITE_MCI(pMciHw, MCI_CR, AT91C_MCI_MCIDIS);\r
+    }\r
+    else {\r
+        WRITE_MCI(pMciHw, MCI_CR, AT91C_MCI_MCIEN);\r
+    }\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Initializes a MCI driver instance and the underlying peripheral.\r
+/// \param pMci  Pointer to a MCI driver instance.\r
+/// \param pMciHw  Pointer to a MCI peripheral.\r
+/// \param mciId  MCI peripheral identifier.\r
+/// \param mode  Slot and type of connected card.\r
+//------------------------------------------------------------------------------\r
+void MCI_Init(\r
+    Mci *pMci,\r
+    AT91S_MCI *pMciHw,\r
+    unsigned char mciId,\r
+    unsigned int mode)\r
+{\r
+    unsigned short clkDiv;\r
+\r
+    SANITY_CHECK(pMci);\r
+    SANITY_CHECK(pMciHw);\r
+    SANITY_CHECK((mode == MCI_MMC_SLOTA) || (mode == MCI_MMC_SLOTB)\r
+                 || (mode == MCI_SD_SLOTA) || (mode == MCI_SD_SLOTB));\r
+\r
+    // Initialize the MCI driver structure\r
+    pMci->pMciHw = pMciHw;\r
+    pMci->mciId  = mciId;\r
+    pMci->semaphore = 1;\r
+    pMci->pCommand = 0;\r
+\r
+    // Enable the MCI clock\r
+    WRITE_PMC(AT91C_BASE_PMC, PMC_PCER, (1 << mciId));\r
+\r
+     // Reset the MCI\r
+    WRITE_MCI(pMciHw, MCI_CR, AT91C_MCI_SWRST);\r
+\r
+    // Disable the MCI\r
+    WRITE_MCI(pMciHw, MCI_CR, AT91C_MCI_MCIDIS | AT91C_MCI_PWSDIS);\r
+\r
+    // Disable all the interrupts\r
+    WRITE_MCI(pMciHw, MCI_IDR, 0xFFFFFFFF);\r
+\r
+    // Set the Data Timeout Register\r
+    WRITE_MCI(pMciHw, MCI_DTOR, DTOR_1MEGA_CYCLES);\r
+\r
+    // Set the Mode Register: 400KHz for MCK = 48MHz (CLKDIV = 58)\r
+    clkDiv = (BOARD_MCK / (400000 * 2)) - 1;\r
+    WRITE_MCI(pMciHw, MCI_MR, (clkDiv | (AT91C_MCI_PWSDIV & (0x7 << 8))));\r
+\r
+    // Set the SDCard Register\r
+    WRITE_MCI(pMciHw, MCI_SDCR, mode);\r
+\r
+    // Enable the MCI and the Power Saving\r
+    WRITE_MCI(pMciHw, MCI_CR, AT91C_MCI_MCIEN);\r
+\r
+    // Disable the MCI peripheral clock.\r
+    WRITE_PMC(AT91C_BASE_PMC, PMC_PCDR, (1 << mciId));\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Close a MCI driver instance and the underlying peripheral.\r
+/// \param pMci  Pointer to a MCI driver instance.\r
+/// \param pMciHw  Pointer to a MCI peripheral.\r
+/// \param mciId  MCI peripheral identifier.\r
+//------------------------------------------------------------------------------\r
+void MCI_Close(Mci *pMci)\r
+{\r
+    AT91S_MCI *pMciHw = pMci->pMciHw;\r
+\r
+    SANITY_CHECK(pMci);\r
+    SANITY_CHECK(pMciHw);\r
+\r
+    // Initialize the MCI driver structure\r
+    pMci->semaphore = 1;\r
+    pMci->pCommand = 0;\r
+\r
+    // Disable the MCI peripheral clock.\r
+    WRITE_PMC(AT91C_BASE_PMC, PMC_PCDR, (1 << pMci->mciId));\r
+\r
+    // Disable the MCI\r
+    WRITE_MCI(pMciHw, MCI_CR, AT91C_MCI_MCIDIS);\r
+\r
+    // Disable all the interrupts\r
+    WRITE_MCI(pMciHw, MCI_IDR, 0xFFFFFFFF);\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Configure the  MCI CLKDIV in the MCI_MR register. The max. for MCI clock is\r
+/// MCK/2 and corresponds to CLKDIV = 0\r
+/// \param pMci  Pointer to the low level MCI driver.\r
+/// \param mciSpeed  MCI clock speed in Hz.\r
+//------------------------------------------------------------------------------\r
+void MCI_SetSpeed(Mci *pMci, unsigned int mciSpeed)\r
+{\r
+    AT91S_MCI *pMciHw = pMci->pMciHw;\r
+    unsigned int mciMr;\r
+    unsigned int clkdiv;\r
+\r
+    SANITY_CHECK(pMci);\r
+    SANITY_CHECK(pMci->pMciHw);\r
+\r
+    // Set the Mode Register: 400KHz for MCK = 48MHz (CLKDIV = 58)\r
+    mciMr = READ_MCI(pMciHw, MCI_MR) & (~AT91C_MCI_CLKDIV);\r
+\r
+    // Multimedia Card Interface clock (MCCK or MCI_CK) is Master Clock (MCK)\r
+    // divided by (2*(CLKDIV+1))\r
+    if (mciSpeed > 0) {\r
+\r
+        clkdiv = (BOARD_MCK / (mciSpeed * 2));\r
+        if (clkdiv > 0) {\r
+\r
+            clkdiv -= 1;\r
+        }\r
+        ASSERT( (clkdiv & 0xFFFFFF00) == 0, "mciSpeed too small");\r
+    }\r
+    else {\r
+\r
+        clkdiv = 0;\r
+    }\r
+\r
+    WRITE_MCI(pMciHw, MCI_MR, mciMr | clkdiv);\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Configure the  MCI SDCBUS in the MCI_SDCR register. Only two modes available\r
+///\r
+/// \param pMci  Pointer to the low level MCI driver.\r
+/// \param busWidth  MCI bus width mode.\r
+//------------------------------------------------------------------------------\r
+void MCI_SetBusWidth(Mci *pMci, unsigned char busWidth)\r
+{\r
+    AT91S_MCI *pMciHw = pMci->pMciHw;\r
+    unsigned int mciSdcr;\r
+\r
+    SANITY_CHECK(pMci);\r
+    SANITY_CHECK(pMci->pMciHw);\r
+\r
+    mciSdcr = (READ_MCI(pMciHw, MCI_SDCR) & ~(AT91C_MCI_SCDBUS));\r
+\r
+    WRITE_MCI(pMciHw, MCI_SDCR, mciSdcr | busWidth);\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Starts a MCI  transfer. This is a non blocking function. It will return\r
+/// as soon as the transfer is started.\r
+/// Return 0 if successful; otherwise returns MCI_ERROR_LOCK if the driver is\r
+/// already in use.\r
+/// \param pMci  Pointer to an MCI driver instance.\r
+/// \param pCommand  Pointer to the command to execute.\r
+//------------------------------------------------------------------------------\r
+unsigned char MCI_SendCommand(Mci *pMci, MciCmd *pCommand)\r
+{\r
+    AT91PS_MCI pMciHw = pMci->pMciHw;\r
+    unsigned int mciIer, mciMr;\r
+\r
+    SANITY_CHECK(pMci);\r
+    SANITY_CHECK(pMciHw);\r
+    SANITY_CHECK(pCommand);\r
+\r
+    // Try to acquire the MCI semaphore\r
+    if (pMci->semaphore == 0) {\r
+\r
+        return MCI_ERROR_LOCK;\r
+    }\r
+    pMci->semaphore--;\r
+    // TRACE_DEBUG("MCI_SendCommand %x %d\n\r", READ_MCI(pMciHw, MCI_SR), pCommand->cmd & 0x3f);\r
+\r
+    // Command is now being executed\r
+    pMci->pCommand = pCommand;\r
+    pCommand->status = MCI_STATUS_PENDING;\r
+\r
+    // Enable the MCI clock\r
+    WRITE_PMC(AT91C_BASE_PMC, PMC_PCER, (1 << pMci->mciId));\r
+\r
+    //Disable MCI clock, for multi-block data transfer\r
+    MCI_Enable(pMci, DISABLE);\r
+\r
+    // Set PDC data transfer direction\r
+    if(pCommand->blockSize > 0) {\r
+        if(pCommand->isRead) {\r
+            WRITE_MCI(pMciHw, MCI_PTCR, AT91C_PDC_RXTEN);\r
+        }\r
+        else {\r
+            WRITE_MCI(pMciHw, MCI_PTCR, AT91C_PDC_TXTEN);\r
+        }\r
+    }\r
+    // Disable transmitter and receiver\r
+    WRITE_MCI(pMciHw, MCI_PTCR, AT91C_PDC_RXTDIS | AT91C_PDC_TXTDIS);\r
+\r
+    mciMr = READ_MCI(pMciHw, MCI_MR) & (~(AT91C_MCI_WRPROOF|AT91C_MCI_RDPROOF|AT91C_MCI_BLKLEN | AT91C_MCI_PDCMODE));\r
+\r
+    // Command with DATA stage\r
+    if (pCommand->blockSize > 0) {\r
+        // Enable PDC mode and set block size\r
+        if(pCommand->conTrans != MCI_CONTINUE_TRANSFER) {\r
+\r
+            WRITE_MCI(pMciHw, MCI_MR, mciMr | AT91C_MCI_PDCMODE |AT91C_MCI_RDPROOF|AT91C_MCI_WRPROOF|(pCommand->blockSize << 16));\r
+        }\r
+\r
+        // DATA transfer from card to host\r
+        if (pCommand->isRead) {\r
+            WRITE_MCI(pMciHw, MCI_RPR, (int) pCommand->pData);\r
+\r
+            // Sanity check\r
+            if (pCommand->nbBlock == 0)\r
+                pCommand->nbBlock = 1;\r
+            ////////\r
+            if ((pCommand->blockSize & 0x3) != 0) {\r
+                WRITE_MCI(pMciHw, MCI_RCR, (pCommand->nbBlock * pCommand->blockSize) / 4 + 1);\r
+            }\r
+            else {\r
+                WRITE_MCI(pMciHw, MCI_RCR, (pCommand->nbBlock * pCommand->blockSize) / 4);\r
+            }\r
+\r
+            WRITE_MCI(pMciHw, MCI_PTCR, AT91C_PDC_RXTEN);\r
+            mciIer = AT91C_MCI_ENDRX | STATUS_ERRORS;\r
+            // mciIer = AT91C_MCI_RXBUFF | STATUS_ERRORS;\r
+        }\r
+\r
+        // DATA transfer from host to card\r
+        else {\r
+            // Sanity check\r
+            if (pCommand->nbBlock == 0)\r
+                pCommand->nbBlock = 1;\r
+            WRITE_MCI(pMciHw, MCI_TPR, (int) pCommand->pData);\r
+            // Update the PDC counter\r
+            if ((pCommand->blockSize & 0x3) != 0) {\r
+                WRITE_MCI(pMciHw, MCI_TCR, (pCommand->nbBlock * pCommand->blockSize) / 4 + 1);\r
+            }\r
+            else {\r
+                WRITE_MCI(pMciHw, MCI_TCR, (pCommand->nbBlock * pCommand->blockSize) / 4);\r
+            }\r
+            // MCI_BLKE notifies the end of Multiblock command\r
+            mciIer = AT91C_MCI_BLKE | STATUS_ERRORS;\r
+        }\r
+    }\r
+    // No data transfer: stop at the end of the command\r
+    else {\r
+        WRITE_MCI(pMciHw, MCI_MR, mciMr);\r
+        mciIer = AT91C_MCI_CMDRDY | STATUS_ERRORS;\r
+    }\r
+    // Enable MCI clock\r
+    MCI_Enable(pMci, ENABLE);\r
+\r
+    // Send the command\r
+    if((pCommand->conTrans != MCI_CONTINUE_TRANSFER)\r
+        || (pCommand->blockSize == 0)) {\r
+\r
+        WRITE_MCI(pMciHw, MCI_ARGR, pCommand->arg);\r
+        WRITE_MCI(pMciHw, MCI_CMDR, pCommand->cmd);\r
+    }\r
+\r
+    // In case of transmit, the PDC shall be enabled after sending the command\r
+    if ((pCommand->blockSize > 0) && !(pCommand->isRead)) {\r
+        WRITE_MCI(pMciHw, MCI_PTCR, AT91C_PDC_TXTEN);\r
+    }\r
+\r
+    // Ignore data error\r
+    mciIer &= ~(AT91C_MCI_UNRE | AT91C_MCI_OVRE \\r
+              | AT91C_MCI_DTOE | AT91C_MCI_DCRCE);\r
+\r
+    // Interrupt enable shall be done after PDC TXTEN and RXTEN\r
+    WRITE_MCI(pMciHw, MCI_IER, mciIer);\r
+\r
+    return 0;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Check NOTBUSY and DTIP bits of status register on the given MCI driver.\r
+/// Return value, 0 for bus ready, 1 for bus busy\r
+/// \param pMci  Pointer to a MCI driver instance.\r
+//------------------------------------------------------------------------------\r
+unsigned char MCI_CheckBusy(Mci *pMci)\r
+{\r
+    AT91S_MCI *pMciHw = pMci->pMciHw;\r
+    unsigned int status;\r
+\r
+    // Enable MCI clock\r
+    MCI_Enable(pMci, ENABLE);\r
+\r
+    status = READ_MCI(pMciHw, MCI_SR);\r
+    // TRACE_DEBUG("status %x\n\r",status);\r
+\r
+\r
+    if(((status & AT91C_MCI_NOTBUSY)!=0)\r
+        && ((status & AT91C_MCI_DTIP)==0)) {\r
+\r
+        // Disable MCI clock\r
+        MCI_Enable(pMci, DISABLE);\r
+\r
+        return 0;\r
+    }\r
+    else {\r
+        return 1;\r
+    }\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Check BLKE bit of status register on the given MCI driver.\r
+/// \param pMci  Pointer to a MCI driver instance.\r
+//------------------------------------------------------------------------------\r
+unsigned char MCI_CheckBlke(Mci *pMci)\r
+{\r
+    AT91S_MCI *pMciHw = pMci->pMciHw;\r
+    unsigned int status;\r
+\r
+    status = READ_MCI(pMciHw, MCI_SR);\r
+    // TRACE_DEBUG("status %x\n\r",status);\r
+\r
+    if((status & AT91C_MCI_BLKE)!=0) {\r
+        return 0;\r
+    }\r
+    else {\r
+        return 1;\r
+    }\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Processes pending events on the given MCI driver.\r
+/// \param pMci  Pointer to a MCI driver instance.\r
+//------------------------------------------------------------------------------\r
+void MCI_Handler(Mci *pMci)\r
+{\r
+    AT91S_MCI *pMciHw = pMci->pMciHw;\r
+    MciCmd *pCommand = pMci->pCommand;\r
+    unsigned int status;\r
+    unsigned char i;\r
+    #if defined(at91rm9200)\r
+    unsigned int mciCr, mciSdcr, mciMr, mciDtor;\r
+    #endif\r
+\r
+    SANITY_CHECK(pMci);\r
+    SANITY_CHECK(pMciHw);\r
+    SANITY_CHECK(pCommand);\r
+\r
+    // Read the status register\r
+    status = READ_MCI(pMciHw, MCI_SR) & READ_MCI(pMciHw, MCI_IMR);\r
+    // TRACE_DEBUG("status %x\n\r", status);\r
+\r
+    // Check if an error has occured\r
+    if ((status & STATUS_ERRORS) != 0) {\r
+\r
+        // Check error code\r
+        if ((status & STATUS_ERRORS) == AT91C_MCI_RTOE) {\r
+\r
+            pCommand->status = MCI_STATUS_NORESPONSE;\r
+        }\r
+        // if the command is SEND_OP_COND the CRC error flag is always present\r
+        // (cf : R3 response)\r
+        else if (((status & STATUS_ERRORS) != AT91C_MCI_RCRCE)\r
+                  || ((pCommand->cmd != SDCARD_APP_OP_COND_CMD)\r
+                      && (pCommand->cmd != MMC_SEND_OP_COND_CMD))) {\r
+\r
+            pCommand->status = MCI_STATUS_ERROR;\r
+        }\r
+    }\r
+\r
+    // Check if a transfer has been completed\r
+    if (((status & AT91C_MCI_CMDRDY) != 0)\r
+        || ((status & AT91C_MCI_ENDRX) != 0)\r
+        || ((status & AT91C_MCI_RXBUFF) != 0)\r
+        || ((status & AT91C_MCI_ENDTX) != 0)\r
+        || ((status & AT91C_MCI_BLKE) != 0)\r
+        || ((status & AT91C_MCI_RTOE) != 0)) {\r
+\r
+        if (((status & AT91C_MCI_ENDRX) != 0)\r
+            || ((status & AT91C_MCI_RXBUFF) != 0)\r
+            || ((status & AT91C_MCI_ENDTX) != 0)) {\r
+\r
+            MCI_Enable(pMci, DISABLE);\r
+        }\r
+\r
+        /// On AT91RM9200-EK, if stop transmission, software reset MCI.\r
+        #if defined(at91rm9200)\r
+        if ((pCommand->cmd & AT91C_MCI_TRCMD_STOP) != 0) {\r
+            mciMr = READ_MCI(pMciHw, MCI_MR);\r
+            mciSdcr = READ_MCI(pMciHw, MCI_SDCR);\r
+            mciDtor = READ_MCI(pMciHw, MCI_DTOR);\r
+            WRITE_MCI(pMciHw, MCI_CR, AT91C_MCI_SWRST);\r
+            // TRACE_DEBUG("reset MCI\n\r");\r
+\r
+            WRITE_MCI(pMciHw, MCI_CR, AT91C_MCI_MCIDIS | AT91C_MCI_PWSDIS);\r
+            WRITE_MCI(pMciHw, MCI_MR, mciMr);\r
+            WRITE_MCI(pMciHw, MCI_SDCR, mciSdcr);\r
+            WRITE_MCI(pMciHw, MCI_DTOR, mciDtor);\r
+        }\r
+        #endif\r
+\r
+        // If no error occured, the transfer is successful\r
+        if (pCommand->status == MCI_STATUS_PENDING) {\r
+            pCommand->status = 0;\r
+        }\r
+#if 0\r
+        if ((status & AT91C_MCI_CMDRDY) != 0)\r
+            TRACE_DEBUG_WP(".");\r
+        if ((status & AT91C_MCI_ENDRX) != 0)\r
+            TRACE_DEBUG_WP("<");\r
+        if ((status & AT91C_MCI_ENDTX) != 0)\r
+            TRACE_DEBUG_WP("-");\r
+        if ((status & AT91C_MCI_BLKE) != 0)\r
+            TRACE_DEBUG_WP(">");\r
+        TRACE_DEBUG_WP("\n\r");\r
+#endif\r
+        // Store the card response in the provided buffer\r
+        if (pCommand->pResp) {\r
+            unsigned char resSize;\r
+\r
+            switch (pCommand->resType) {\r
+                case 1:\r
+                resSize = 1;\r
+                break;\r
+\r
+                case 2:\r
+                resSize = 4;\r
+                break;\r
+\r
+                case 3:\r
+                resSize = 1;\r
+                break;\r
+\r
+                case 4:\r
+                resSize = 1;\r
+                break;\r
+\r
+                case 5:\r
+                resSize = 1;\r
+                break;\r
+\r
+                case 6:\r
+                resSize = 1;\r
+                break;\r
+\r
+                case 7:\r
+                resSize = 1;\r
+                break;\r
+\r
+                default:\r
+                resSize = 0;\r
+                break;\r
+            }\r
+            for (i=0; i < resSize; i++) {\r
+\r
+                pCommand->pResp[i] = READ_MCI(pMciHw, MCI_RSPR[0]);\r
+            }\r
+        }\r
+\r
+        // Disable interrupts\r
+        WRITE_MCI(pMciHw, MCI_IDR, READ_MCI(pMciHw, MCI_IMR));\r
+\r
+        // Release the semaphore\r
+        pMci->semaphore++;\r
+\r
+        // Invoke the callback associated with the current command (if any)\r
+        if (pCommand->callback) {\r
+            (pCommand->callback)(pCommand->status, pCommand);\r
+        }\r
+    }\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Returns 1 if the given MCI transfer is complete; otherwise returns 0.\r
+/// \param pCommand  Pointer to a MciCmd instance.\r
+//------------------------------------------------------------------------------\r
+unsigned char MCI_IsTxComplete(MciCmd *pCommand)\r
+{\r
+    if (pCommand->status != MCI_STATUS_PENDING) {\r
+        if (pCommand->status != 0) {\r
+            TRACE_DEBUG("MCI_IsTxComplete %d\n\r", pCommand->status);\r
+        }\r
+        return 1;\r
+    }\r
+    else {\r
+        return 0;\r
+    }\r
+}\r

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/mci/mci.h b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/mci/mci.h
new file mode 100644 (file)
index 0000000..a972184
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/mci/mci.h
@@ -0,0 +1,172 @@
+/* ----------------------------------------------------------------------------\r
+ *         ATMEL Microcontroller Software Support\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+//------------------------------------------------------------------------------\r
+/// \page "mci"\r
+///\r
+/// !Purpose\r
+///  \r
+/// mci-interface driver\r
+///\r
+/// !Usage\r
+///\r
+/// -# MCI_Init: Initializes a MCI driver instance and the underlying peripheral.\r
+/// -# MCI_SetSpeed : Configure the  MCI CLKDIV in the MCI_MR register.\r
+/// -# MCI_SendCommand: Starts a MCI  transfer.\r
+/// -# MCI_Handler : Interrupt handler which is called by ISR handler.\r
+/// -# MCI_SetBusWidth : Configure the  MCI SDCBUS in the MCI_SDCR register.\r
+//------------------------------------------------------------------------------\r
+\r
+\r
+#ifndef MCI_H\r
+#define MCI_H\r
+\r
+//------------------------------------------------------------------------------\r
+//         Headers\r
+//------------------------------------------------------------------------------\r
+\r
+#include <board.h>\r
+\r
+//------------------------------------------------------------------------------\r
+//         Constants\r
+//------------------------------------------------------------------------------\r
+\r
+/// Transfer is pending.\r
+#define MCI_STATUS_PENDING      1\r
+/// Transfer has been aborted because an error occured.\r
+#define MCI_STATUS_ERROR        2\r
+/// Card did not answer command.\r
+#define MCI_STATUS_NORESPONSE   3\r
+\r
+/// MCI driver is currently in use.\r
+#define MCI_ERROR_LOCK    1\r
+\r
+/// MCI configuration with 1-bit data bus on slot A (for MMC cards).\r
+#define MCI_MMC_SLOTA          0\r
+/// MCI configuration with 1-bit data bus on slot B (for MMC cards).\r
+#define MCI_MMC_SLOTB          1\r
+/// MCI configuration with 4-bit data bus on slot A (for SD cards).\r
+#define MCI_SD_SLOTA           AT91C_MCI_SCDBUS\r
+/// MCI configuration with 4-bit data bus on slot B (for SD cards).\r
+#define MCI_SD_SLOTB           (AT91C_MCI_SCDBUS | 1)\r
+\r
+/// Start new data transfer\r
+#define MCI_NEW_TRANSFER        0\r
+/// Continue data transfer\r
+#define MCI_CONTINUE_TRANSFER   1\r
+\r
+/// MCI SD Bus Width 1-bit\r
+#define MCI_SDCBUS_1BIT (0 << 7)\r
+/// MCI SD Bus Width 4-bit\r
+#define MCI_SDCBUS_4BIT (1 << 7)\r
+\r
+//------------------------------------------------------------------------------\r
+//         Types\r
+//------------------------------------------------------------------------------\r
+\r
+/// MCI end-of-transfer callback function.\r
+typedef void (*MciCallback)(unsigned char status, void *pCommand);\r
+\r
+//------------------------------------------------------------------------------\r
+/// MCI Transfer Request prepared by the application upper layer. This structure\r
+/// is sent to the MCI_SendCommand function to start the transfer. At the end of\r
+/// the transfer, the callback is invoked by the interrupt handler.\r
+//------------------------------------------------------------------------------\r
+typedef struct _MciCmd {\r
+\r
+    /// Command status.\r
+       volatile char status;\r
+    /// Command code.\r
+       unsigned int cmd;\r
+    /// Command argument.\r
+       unsigned int arg;\r
+    /// Data buffer.\r
+       unsigned char *pData;\r
+    /// Size of data buffer in bytes.\r
+       unsigned short blockSize;\r
+       /// Number of blocks to be transfered\r
+       unsigned short nbBlock;\r
+       /// Indicate if continue to transfer data\r
+       unsigned char conTrans;\r
+    /// Indicates if the command is a read operation.\r
+       unsigned char isRead;\r
+    /// Response buffer.\r
+    unsigned int  *pResp;\r
+    /// SD card response type.\r
+       unsigned char  resType;\r
+       /// Optional user-provided callback function.\r
+       MciCallback callback;\r
+    /// Optional argument to the callback function.\r
+       void *pArg;\r
+\r
+} MciCmd;\r
+\r
+//------------------------------------------------------------------------------\r
+/// MCI driver structure. Holds the internal state of the MCI driver and\r
+/// prevents parallel access to a MCI peripheral.\r
+//------------------------------------------------------------------------------\r
+typedef struct {\r
+\r
+    /// Pointer to a MCI peripheral.\r
+       AT91S_MCI *pMciHw;\r
+    /// MCI peripheral identifier.\r
+    unsigned char mciId;\r
+    /// Pointer to currently executing command.\r
+       MciCmd *pCommand;\r
+       /// Mutex.\r
+       volatile char semaphore;\r
+\r
+} Mci;\r
+\r
+//------------------------------------------------------------------------------\r
+//         Global functions\r
+//------------------------------------------------------------------------------\r
+\r
+extern void MCI_Init(\r
+    Mci *pMci,\r
+    AT91PS_MCI pMciHw,\r
+    unsigned char mciId,\r
+    unsigned int mode);\r
+\r
+extern void MCI_SetSpeed(Mci *pMci, unsigned int mciSpeed);\r
+\r
+extern unsigned char MCI_SendCommand(Mci *pMci, MciCmd *pMciCmd);\r
+\r
+extern void MCI_Handler(Mci *pMci);\r
+\r
+extern unsigned char MCI_IsTxComplete(MciCmd *pMciCmd);\r
+\r
+extern unsigned char MCI_CheckBusy(Mci *pMci);\r
+\r
+extern void MCI_Close(Mci *pMci);\r
+\r
+extern void MCI_SetBusWidth(Mci *pMci, unsigned char busWidth);\r
+\r
+#endif //#ifndef MCI_H\r
+\r

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/mci/mci_hs.c b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/mci/mci_hs.c
new file mode 100644 (file)
index 0000000..04ce94d
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/mci/mci_hs.c
@@ -0,0 +1,1027 @@
+/* ----------------------------------------------------------------------------\r
+ *         ATMEL Microcontroller Software Support\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+//------------------------------------------------------------------------------\r
+//         Headers\r
+//------------------------------------------------------------------------------\r
+\r
+#include "mci_hs.h"\r
+#include <utility/assert.h>\r
+#include <utility/trace.h>\r
+\r
+#include <dmad/dmad.h>\r
+#include <dma/dma.h>\r
+\r
+//------------------------------------------------------------------------------\r
+//         Local constants\r
+//------------------------------------------------------------------------------\r
+\r
+/// Bit mask for status register errors.\r
+#define STATUS_ERRORS (AT91C_MCI_UNRE  \\r
+                       | AT91C_MCI_OVRE \\r
+                       | AT91C_MCI_BLKOVRE \\r
+                       | AT91C_MCI_CSTOE \\r
+                       | AT91C_MCI_DTOE \\r
+                       | AT91C_MCI_DCRCE \\r
+                       | AT91C_MCI_RTOE \\r
+                       | AT91C_MCI_RENDE \\r
+                       | AT91C_MCI_RCRCE \\r
+                       | AT91C_MCI_RDIRE \\r
+                       | AT91C_MCI_RINDE)\r
+\r
+#define STATUS_ERRORS_RESP (AT91C_MCI_CSTOE \\r
+                            | AT91C_MCI_RTOE \\r
+                            | AT91C_MCI_RENDE \\r
+                            | AT91C_MCI_RCRCE \\r
+                            | AT91C_MCI_RDIRE \\r
+                            | AT91C_MCI_RINDE)\r
+\r
+#define STATUS_ERRORS_DATA (AT91C_MCI_UNRE \\r
+                            | AT91C_MCI_OVRE \\r
+                            | AT91C_MCI_BLKOVRE \\r
+                            | AT91C_MCI_CSTOE \\r
+                            | AT91C_MCI_DTOE \\r
+                            | AT91C_MCI_DCRCE)\r
+\r
+\r
+/// MCI data timeout configuration with 1048576 MCK cycles between 2 data transfers.\r
+#define DTOR_1MEGA_CYCLES           (AT91C_MCI_DTOCYC | AT91C_MCI_DTOMUL)\r
+\r
+/// MCI MR: disable MCI Clock when FIFO is full\r
+#ifndef AT91C_MCI_WRPROOF\r
+    #define AT91C_MCI_WRPROOF 0\r
+#endif\r
+#ifndef AT91C_MCI_RDPROOF\r
+    #define AT91C_MCI_RDPROOF 0\r
+#endif\r
+\r
+#define SDCARD_APP_OP_COND_CMD      (41 | AT91C_MCI_SPCMD_NONE  | AT91C_MCI_RSPTYP_48   | AT91C_MCI_TRCMD_NO )\r
+#define MMC_SEND_OP_COND_CMD        (1  | AT91C_MCI_TRCMD_NO    | AT91C_MCI_SPCMD_NONE  | AT91C_MCI_RSPTYP_48 | AT91C_MCI_OPDCMD)\r
+\r
+\r
+#define DISABLE    0    // Disable MCI interface\r
+#define ENABLE     1    // Enable MCI interface\r
+\r
+\r
+//------------------------------------------------------------------------------\r
+//         Local macros\r
+//------------------------------------------------------------------------------\r
+\r
+/// Used to write in PMC registers.\r
+#define WRITE_PMC(pPmc, regName, value)     pPmc->regName = (value)\r
+\r
+/// Used to write in MCI registers.\r
+#define WRITE_MCI(pMci, regName, value)     pMci->regName = (value)\r
+\r
+/// Used to read from MCI registers.\r
+#define READ_MCI(pMci, regName)             (pMci->regName)\r
+\r
+/// Enable MCI Clock\r
+#define MCICK_ENABLE(pMciHw)      WRITE_MCI(pMciHw, MCI_CR, AT91C_MCI_MCIEN)\r
+\r
+/// Disable MCI Clock\r
+#define MCICK_DISABLE(pMciHw)     WRITE_MCI(pMciHw, MCI_CR, AT91C_MCI_MCIDIS)\r
+\r
+\r
+//------------------------------------------------------------------------------\r
+//         Local variables\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+//         Internal Functions\r
+//------------------------------------------------------------------------------\r
+#if defined(MCI_DMA_ENABLE)\r
+#define FIFO_SIZE (0x4000 - 0x200)\r
+static DmaLinkList  LLI_CH [4];\r
+#define     LAST_ROW            0x100\r
+static void AT91F_Prepare_Multiple_Transfer(unsigned int Channel,\r
+                                            unsigned int LLI_rownumber,\r
+                                            unsigned int LLI_Last_Row,\r
+                                            unsigned int From_add,\r
+                                            unsigned int To_add,\r
+                                            unsigned int Ctrla,\r
+                                            unsigned int Ctrlb)\r
+{\r
+    LLI_CH[LLI_rownumber].sourceAddress =  From_add;\r
+    LLI_CH[LLI_rownumber].destAddress =  To_add;\r
+    LLI_CH[LLI_rownumber].controlA =  Ctrla;\r
+    LLI_CH[LLI_rownumber].controlB =  Ctrlb;\r
+    if (LLI_Last_Row != LAST_ROW)\r
+        LLI_CH[LLI_rownumber].descriptor =\r
+             (unsigned int)&LLI_CH[LLI_rownumber + 1] + 0;\r
+    else\r
+        LLI_CH[LLI_rownumber].descriptor = 0;\r
+}\r
+\r
+static unsigned int DMACH_MCI_P2M(unsigned int channel_index,\r
+                                  unsigned int* src_addr,\r
+                                  unsigned int* dest_addr,\r
+                                  unsigned int trans_size,\r
+                                  unsigned char fifoForP)\r
+{\r
+    unsigned int srcAddress;\r
+    unsigned int destAddress;\r
+    unsigned int buffSize;\r
+    unsigned int LLI_rownumber = 0;\r
+    unsigned int srcAddressMode = fifoForP ?\r
+                                  (AT91C_HDMA_SRC_ADDRESS_MODE_INCR)\r
+                                : (AT91C_HDMA_SRC_ADDRESS_MODE_FIXED);\r
+\r
+    // Disable dma channel\r
+    DMA_DisableChannel(channel_index);\r
+\r
+    // DMA channel configuration\r
+    srcAddress  = (unsigned int)src_addr;    // Set the data start address\r
+    destAddress = (unsigned int)dest_addr; //(unsigned int)SSC_THR_ADD; \r
+    buffSize    = trans_size;\r
+\r
+    if(buffSize >= 0x10000){\r
+        buffSize = 0xffff;\r
+    }\r
+\r
+    // Set DMA channel source address\r
+    DMA_SetSourceAddr(channel_index, srcAddress);\r
+\r
+    // Set DMA channel destination address\r
+    DMA_SetDestinationAddr(channel_index,destAddress);\r
+\r
+    // Set DMA channel DSCR\r
+    DMA_SetDescriptorAddr(channel_index, (unsigned int)&LLI_CH[0]);\r
+\r
+    // Set DMA channel control A \r
+    DMA_SetSourceBufferSize(channel_index, buffSize,\r
+            (AT91C_HDMA_SRC_WIDTH_WORD >> 24),\r
+            (AT91C_HDMA_DST_WIDTH_WORD >> 28), 0);\r
+\r
+       //Set DMA channel control B\r
+    DMA_SetSourceBufferMode(channel_index, DMA_TRANSFER_LLI,\r
+                            srcAddressMode >> 24);\r
+    DMA_SetDestBufferMode(channel_index, DMA_TRANSFER_LLI,\r
+                            (AT91C_HDMA_DST_ADDRESS_MODE_INCR >> 28));\r
+\r
+    // Set DMA channel config\r
+    DMA_SetConfiguration(channel_index, BOARD_SD_DMA_HW_SRC_REQ_ID \\r
+                                        | BOARD_SD_DMA_HW_DEST_REQ_ID \\r
+                                        | AT91C_HDMA_SRC_REP_CONTIGUOUS_ADDR \\r
+                                        | AT91C_HDMA_SRC_H2SEL_HW \\r
+                                        | AT91C_HDMA_DST_REP_CONTIGUOUS_ADDR \\r
+                                        | AT91C_HDMA_DST_H2SEL_SW \\r
+                                        | AT91C_HDMA_SOD_DISABLE \\r
+                                        | AT91C_HDMA_FIFOCFG_LARGESTBURST);\r
+\r
+    // Set link list\r
+    while(destAddress < ((unsigned int)(dest_addr + buffSize))) {\r
+        if(((unsigned int)(dest_addr + buffSize)) - destAddress <= (4*0xFFF) )\r
+        {\r
+            AT91F_Prepare_Multiple_Transfer(channel_index, LLI_rownumber, LAST_ROW,\r
+                                        srcAddress,\r
+                                        destAddress,\r
+                                        (((((unsigned int)(dest_addr + buffSize))\r
+                                               - destAddress)/4)\r
+                                                | AT91C_HDMA_SRC_WIDTH_WORD\r
+                                                | AT91C_HDMA_DST_WIDTH_WORD),\r
+                                        ( AT91C_HDMA_SIF_0\r
+                                           | AT91C_HDMA_DIF_0\r
+                                           | AT91C_HDMA_DST_DSCR_FETCH_FROM_MEM\r
+                                           //| AT91C_HDMA_DST_DSCR_FETCH_DISABLE\r
+                                           | AT91C_HDMA_DST_ADDRESS_MODE_INCR\r
+                                           //| AT91C_HDMA_SRC_DSCR_FETCH_FROM_MEM\r
+                                           | AT91C_HDMA_SRC_DSCR_FETCH_DISABLE\r
+                                           | srcAddressMode\r
+                                           | AT91C_HDMA_AUTO_DISABLE\r
+                                           | AT91C_HDMA_FC_PER2MEM));\r
+        }\r
+        else\r
+        {\r
+            AT91F_Prepare_Multiple_Transfer(channel_index, LLI_rownumber, 0,\r
+                                        srcAddress,\r
+                                        destAddress,\r
+                                        ( 0xFFF\r
+                                            | AT91C_HDMA_SRC_WIDTH_WORD\r
+                                            | AT91C_HDMA_DST_WIDTH_WORD),\r
+                                        (AT91C_HDMA_SIF_0\r
+                                            | AT91C_HDMA_DIF_0\r
+                                            | AT91C_HDMA_DST_DSCR_FETCH_FROM_MEM\r
+                                            //| AT91C_HDMA_DST_DSCR_FETCH_DISABLE\r
+                                            | AT91C_HDMA_DST_ADDRESS_MODE_INCR\r
+                                            //| AT91C_HDMA_SRC_DSCR_FETCH_FROM_MEM\r
+                                            | AT91C_HDMA_SRC_DSCR_FETCH_DISABLE\r
+                                            | srcAddressMode\r
+                                            | AT91C_HDMA_AUTO_DISABLE\r
+                                            | AT91C_HDMA_FC_PER2MEM));\r
+\r
+        }\r
+\r
+        destAddress += 4*0xFFF;\r
+\r
+        LLI_rownumber++;\r
+    }\r
+\r
+    return 0;\r
+}\r
+\r
+\r
+static unsigned int DMACH_MCI_M2P(unsigned int channel_index,\r
+                                  unsigned int* src_addr,\r
+                                  unsigned int* dest_addr,\r
+                                  unsigned int trans_size,\r
+                                  unsigned char fifoForP)\r
+{\r
+    unsigned int srcAddress;\r
+    unsigned int destAddress;\r
+    unsigned int buffSize;\r
+    unsigned int LLI_rownumber = 0;\r
+    unsigned int dstAddressMode = fifoForP ?\r
+                                  (AT91C_HDMA_DST_ADDRESS_MODE_INCR)\r
+                                : (AT91C_HDMA_DST_ADDRESS_MODE_FIXED);\r
+\r
+    // Disable dma channel\r
+    DMA_DisableChannel(channel_index);\r
+\r
+    buffSize = trans_size;\r
+    if(buffSize >= 0x10000){\r
+        buffSize = 0xffff;\r
+    }\r
+\r
+    // DMA channel configuration\r
+    srcAddress  = (unsigned int)src_addr;    // Set the data start address\r
+    destAddress = (unsigned int)dest_addr;\r
+\r
+    // Set DMA channel source address\r
+    DMA_SetSourceAddr(channel_index, srcAddress);\r
+\r
+    // Set DMA channel destination address\r
+    DMA_SetDestinationAddr(channel_index,destAddress);\r
+\r
+    // Set DMA channel DSCR\r
+    DMA_SetDescriptorAddr(channel_index, (unsigned int)&LLI_CH[0]);\r
+\r
+    // Set DMA channel control A \r
+    DMA_SetSourceBufferSize(channel_index, buffSize,\r
+                              (AT91C_HDMA_SRC_WIDTH_WORD >> 24),\r
+                              (AT91C_HDMA_DST_WIDTH_WORD >> 28), 0);\r
+\r
+    //Set DMA channel control B\r
+    DMA_SetSourceBufferMode(channel_index,\r
+                            DMA_TRANSFER_LLI,\r
+                            (AT91C_HDMA_SRC_ADDRESS_MODE_INCR >> 24));\r
+    DMA_SetDestBufferMode(channel_index,\r
+                          DMA_TRANSFER_LLI,\r
+                          dstAddressMode >> 28);\r
+\r
+    // Set DMA channel config\r
+    DMA_SetConfiguration(channel_index, BOARD_SD_DMA_HW_SRC_REQ_ID \\r
+                                        | BOARD_SD_DMA_HW_DEST_REQ_ID \\r
+                                        | AT91C_HDMA_SRC_REP_CONTIGUOUS_ADDR \\r
+                                        | AT91C_HDMA_SRC_H2SEL_SW \\r
+                                        | AT91C_HDMA_DST_REP_CONTIGUOUS_ADDR \\r
+                                        | AT91C_HDMA_DST_H2SEL_HW \\r
+                                        | AT91C_HDMA_SOD_DISABLE \\r
+                                        | AT91C_HDMA_FIFOCFG_LARGESTBURST);\r
+\r
+    // Set link list\r
+    while(srcAddress < ((unsigned int)(src_addr + buffSize)))\r
+    {\r
+        if(((unsigned int)(src_addr + buffSize)) - srcAddress <= (4*0xFFF) )\r
+        {\r
+            AT91F_Prepare_Multiple_Transfer(channel_index, LLI_rownumber, LAST_ROW,\r
+                                        srcAddress,\r
+                                        destAddress,\r
+                                        (((((unsigned int)(src_addr + buffSize))\r
+                                                - srcAddress)/4)\r
+                                                  | AT91C_HDMA_SRC_WIDTH_WORD\r
+                                                  | AT91C_HDMA_DST_WIDTH_WORD),\r
+                                        ( AT91C_HDMA_SIF_0\r
+                                        | AT91C_HDMA_DIF_0\r
+                                        //| AT91C_HDMA_DST_DSCR_FETCH_FROM_MEM\r
+                                        | AT91C_HDMA_DST_DSCR_FETCH_DISABLE\r
+                                        | dstAddressMode\r
+                                        //| AT91C_HDMA_SRC_DSCR_FETCH_FROM_MEM\r
+                                        | AT91C_HDMA_SRC_DSCR_FETCH_DISABLE\r
+                                        | AT91C_HDMA_SRC_ADDRESS_MODE_INCR\r
+                                        | AT91C_HDMA_AUTO_DISABLE\r
+                                        | AT91C_HDMA_FC_MEM2PER));\r
+        }\r
+        else\r
+        {\r
+            AT91F_Prepare_Multiple_Transfer(channel_index, LLI_rownumber, 0,\r
+                                        srcAddress,\r
+                                        destAddress,\r
+                                        ( 0xFFF\r
+                                            | AT91C_HDMA_SRC_WIDTH_WORD\r
+                                            | AT91C_HDMA_DST_WIDTH_WORD),\r
+                                        ( AT91C_HDMA_SIF_0\r
+                                        | AT91C_HDMA_DIF_0\r
+                                        //| AT91C_HDMA_DST_DSCR_FETCH_FROM_MEM\r
+                                        | AT91C_HDMA_DST_DSCR_FETCH_DISABLE\r
+                                        | dstAddressMode\r
+                                        | AT91C_HDMA_SRC_DSCR_FETCH_FROM_MEM\r
+                                        //| AT91C_HDMA_SRC_DSCR_FETCH_DISABLE\r
+                                        | AT91C_HDMA_SRC_ADDRESS_MODE_INCR\r
+                                        | AT91C_HDMA_AUTO_DISABLE\r
+                                        | AT91C_HDMA_FC_MEM2PER));\r
+\r
+        }\r
+\r
+        srcAddress += 4*0xFFF;\r
+\r
+        \r
+        LLI_rownumber++;\r
+    }\r
+    \r
+    return 0;\r
+}\r
+\r
+static inline void DMACH_EnableIt(AT91S_MCI *pMciHw,\r
+                                 unsigned int channel)\r
+{\r
+    unsigned int intFlag;\r
+\r
+    intFlag = DMA_GetInterruptMask();\r
+    intFlag |= (AT91C_HDMA_BTC0 << channel);\r
+    DMA_EnableIt(intFlag);\r
+}\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+//         Global functions\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+/// Enable/disable a MCI driver instance.\r
+/// \param pMci  Pointer to a MCI driver instance.\r
+/// \param enb  0 for disable MCI and 1 for enable MCI.\r
+//------------------------------------------------------------------------------\r
+void MCI_Enable(Mci *pMci, unsigned char enb)\r
+{\r
+    AT91S_MCI *pMciHw = pMci->pMciHw;\r
+\r
+    SANITY_CHECK(pMci);\r
+    SANITY_CHECK(pMci->pMciHw);\r
+\r
+    // Set the Control Register: Enable/Disable MCI interface clock\r
+    if(enb == DISABLE) {\r
+        MCICK_DISABLE(pMciHw);\r
+    }\r
+    else {\r
+        MCICK_ENABLE(pMciHw);\r
+    }\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Initializes a MCI driver instance and the underlying peripheral.\r
+/// \param pMci    Pointer to a MCI driver instance.\r
+/// \param pMciHw  Pointer to a MCI peripheral.\r
+/// \param mciId   MCI peripheral identifier.\r
+/// \param mode    Slot and type of supported card (max bus width).\r
+//------------------------------------------------------------------------------\r
+void MCI_Init(\r
+    Mci *pMci,\r
+    AT91S_MCI *pMciHw,\r
+    unsigned char mciId,\r
+    unsigned int mode)\r
+{\r
+    unsigned short clkDiv;\r
+    unsigned int mciCfg = 0;\r
+\r
+    SANITY_CHECK(pMci);\r
+    SANITY_CHECK(pMciHw);\r
+    SANITY_CHECK(   (mode == MCI_MMC_SLOTA)  || (mode == MCI_SD_SLOTA)\r
+                 || (mode == MCI_MMC_SLOTB)  || (mode == MCI_SD_SLOTB)\r
+                 || (mode == MCI_MMC4_SLOTA) || (mode == MCI_MMC4_SLOTB));\r
+\r
+    // Initialize the MCI driver structure\r
+    pMci->pMciHw    = pMciHw;\r
+    pMci->mciId     = mciId;\r
+    pMci->mciMode   = mode;\r
+    pMci->semaphore = 1;\r
+    pMci->pCommand  = 0;\r
+\r
+    // Enable the MCI clock\r
+    WRITE_PMC(AT91C_BASE_PMC, PMC_PCER, (1 << mciId));\r
+\r
+     // Reset the MCI\r
+    WRITE_MCI(pMciHw, MCI_CR, AT91C_MCI_SWRST);\r
+\r
+    // Disable the MCI\r
+    WRITE_MCI(pMciHw, MCI_CR, AT91C_MCI_MCIDIS | AT91C_MCI_PWSDIS);\r
+\r
+    // Disable all the interrupts\r
+    WRITE_MCI(pMciHw, MCI_IDR, 0xFFFFFFFF);\r
+\r
+    // Set the Data Timeout Register\r
+    WRITE_MCI(pMciHw, MCI_DTOR, DTOR_1MEGA_CYCLES);\r
+\r
+    // Set the Mode Register: 400KHz for MCK = 48MHz (CLKDIV = 58)\r
+    clkDiv = (BOARD_MCK / (MCI_INITIAL_SPEED * 2)) - 1;\r
+    WRITE_MCI(pMciHw, MCI_MR, (clkDiv | (AT91C_MCI_PWSDIV & (0x7 << 8))));\r
+\r
+    // Set the SDCard Register\r
+    WRITE_MCI(pMciHw, MCI_SDCR, mode);\r
+\r
+    // Enable the MCI and the Power Saving\r
+    WRITE_MCI(pMciHw, MCI_CR, AT91C_MCI_MCIEN);\r
+\r
+    // Disable the DMA interface\r
+    WRITE_MCI(pMciHw, MCI_DMA, AT91C_MCI_DMAEN_DISABLE);\r
+\r
+    // Configure MCI\r
+    //mciCfg = AT91C_MCI_FIFOMODE_AMOUNTDATA | AT91C_MCI_FERRCTRL_RWCMD;\r
+    mciCfg = AT91C_MCI_FIFOMODE_ONEDATA | AT91C_MCI_FERRCTRL_RWCMD;\r
+    \r
+    WRITE_MCI(pMciHw, MCI_CFG, mciCfg);\r
+\r
+    // Disable the MCI peripheral clock.\r
+    WRITE_PMC(AT91C_BASE_PMC, PMC_PCDR, (1 << mciId));\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Close a MCI driver instance and the underlying peripheral.\r
+/// \param pMci  Pointer to a MCI driver instance.\r
+/// \param pMciHw  Pointer to a MCI peripheral.\r
+/// \param mciId  MCI peripheral identifier.\r
+//------------------------------------------------------------------------------\r
+void MCI_Close(Mci *pMci)\r
+{\r
+    AT91S_MCI *pMciHw = pMci->pMciHw;\r
+\r
+    SANITY_CHECK(pMci);\r
+    SANITY_CHECK(pMciHw);\r
+\r
+    // Initialize the MCI driver structure\r
+    pMci->semaphore = 1;\r
+    pMci->pCommand = 0;\r
+\r
+    // Disable the MCI peripheral clock.\r
+    WRITE_PMC(AT91C_BASE_PMC, PMC_PCDR, (1 << pMci->mciId));\r
+\r
+    // Disable the MCI\r
+    WRITE_MCI(pMciHw, MCI_CR, AT91C_MCI_MCIDIS);\r
+\r
+    // Disable all the interrupts\r
+    WRITE_MCI(pMciHw, MCI_IDR, 0xFFFFFFFF);\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Get the  MCI CLKDIV in the MCI_MR register. The max. for MCI clock is\r
+/// MCK/2 and corresponds to CLKDIV = 0\r
+/// \param pMci  Pointer to the low level MCI driver.\r
+/// \param mciSpeed  MCI clock speed in Hz.\r
+//------------------------------------------------------------------------------\r
+unsigned int MCI_GetSpeed(Mci *pMci, unsigned int *mciDiv)\r
+{\r
+    AT91S_MCI *pMciHw = pMci->pMciHw;\r
+    unsigned int mciMr;\r
+\r
+    SANITY_CHECK(pMci);\r
+    SANITY_CHECK(pMci->pMciHw);\r
+\r
+    // Get the Mode Register\r
+    mciMr  = READ_MCI(pMciHw, MCI_MR);\r
+    mciMr &= AT91C_MCI_CLKDIV;\r
+    if (mciDiv) *mciDiv = mciMr;\r
+    return (BOARD_MCK / 2 / (mciMr + 1));\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Configure the  MCI CLKDIV in the MCI_MR register. The max. for MCI clock is\r
+/// MCK/2 and corresponds to CLKDIV = 0\r
+/// \param pMci  Pointer to the low level MCI driver.\r
+/// \param mciSpeed  MCI clock speed in Hz.\r
+/// \param mciLimit  MCI clock limit in Hz, if not limit, set mciLimit to zero.\r
+/// \return The actual speed used, 0 for fail.\r
+//------------------------------------------------------------------------------\r
+unsigned int MCI_SetSpeed(Mci *pMci,\r
+                          unsigned int mciSpeed,\r
+                          unsigned int mciLimit)\r
+{\r
+    AT91S_MCI *pMciHw = pMci->pMciHw;\r
+    unsigned int mciMr;\r
+    unsigned int clkdiv;\r
+    unsigned int divLimit = 0;\r
+\r
+    SANITY_CHECK(pMci);\r
+    SANITY_CHECK(pMci->pMciHw);\r
+\r
+    mciMr = READ_MCI(pMciHw, MCI_MR) & (~AT91C_MCI_CLKDIV);\r
+\r
+    // Multimedia Card Interface clock (MCCK or MCI_CK) is Master Clock (MCK)\r
+    // divided by (2*(CLKDIV+1))\r
+    // mciSpeed = MCK / (2*(CLKDIV+1))\r
+    if (mciLimit)   divLimit = (BOARD_MCK / 2 / mciLimit);\r
+    if (mciSpeed > 0) {\r
+        clkdiv = (BOARD_MCK / 2 / mciSpeed);\r
+        if (mciLimit && clkdiv < divLimit)\r
+            clkdiv = divLimit;\r
+        if (clkdiv > 0) \r
+            clkdiv -= 1;\r
+        ASSERT( (clkdiv & 0xFFFFFF00) == 0, "mciSpeed too small");\r
+    }\r
+    else    clkdiv = 0;\r
+\r
+    WRITE_MCI(pMciHw, MCI_MR, mciMr | clkdiv);\r
+    return (BOARD_MCK / 2 / (clkdiv + 1));\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Configure the MCI_CFG to enable the HS mode\r
+/// \param pMci     Pointer to the low level MCI driver.\r
+/// \param hsEnable 1 to enable, 0 to disable HS mode.\r
+//------------------------------------------------------------------------------\r
+void MCI_EnableHsMode(Mci *pMci, unsigned char hsEnable)\r
+{\r
+    AT91S_MCI *pMciHw = pMci->pMciHw;\r
+    unsigned int cfgr;\r
+\r
+    SANITY_CHECK(pMci);\r
+    SANITY_CHECK(pMci->pMciHw);\r
+\r
+    cfgr = READ_MCI(pMciHw, MCI_CFG);\r
+    if (hsEnable)   cfgr |=  AT91C_MCI_HSMODE_ENABLE;\r
+    else            cfgr &= ~AT91C_MCI_HSMODE_ENABLE;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Configure the  MCI SDCBUS in the MCI_SDCR register. Only two modes available\r
+///\r
+/// \param pMci  Pointer to the low level MCI driver.\r
+/// \param busWidth  MCI bus width mode.\r
+//------------------------------------------------------------------------------\r
+void MCI_SetBusWidth(Mci *pMci, unsigned char busWidth)\r
+{\r
+    AT91S_MCI *pMciHw = pMci->pMciHw;\r
+    unsigned int mciSdcr;\r
+\r
+    SANITY_CHECK(pMci);\r
+    SANITY_CHECK(pMci->pMciHw);\r
+\r
+    mciSdcr = (READ_MCI(pMciHw, MCI_SDCR) & ~(AT91C_MCI_SCDBUS));\r
+\r
+    WRITE_MCI(pMciHw, MCI_SDCR, mciSdcr | busWidth);\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Starts a MCI  transfer. This is a non blocking function. It will return\r
+/// as soon as the transfer is started.\r
+/// Return 0 if successful; otherwise returns MCI_ERROR_LOCK if the driver is\r
+/// already in use.\r
+/// \param pMci  Pointer to an MCI driver instance.\r
+/// \param pCommand  Pointer to the command to execute.\r
+//------------------------------------------------------------------------------\r
+unsigned char MCI_SendCommand(Mci *pMci, MciCmd *pCommand)\r
+{\r
+    AT91PS_MCI pMciHw = pMci->pMciHw;\r
+    unsigned int mciIer, mciMr;\r
+    unsigned int transSize;\r
+    unsigned int mciBlkr;\r
+\r
+  #if defined(MCI_DMA_ENABLE)\r
+    unsigned int mciDma;\r
+  #endif\r
+\r
+    SANITY_CHECK(pMci);\r
+    SANITY_CHECK(pMciHw);\r
+    SANITY_CHECK(pCommand);\r
+\r
+    // Try to acquire the MCI semaphore\r
+    if (pMci->semaphore == 0) {\r
+\r
+        return MCI_ERROR_LOCK;\r
+    }\r
+    pMci->semaphore--;\r
+\r
+    // Command is now being executed\r
+    pMci->pCommand = pCommand;\r
+    pCommand->status = MCI_STATUS_PENDING;\r
+\r
+    // Enable the MCI peripheral clock\r
+    WRITE_PMC(AT91C_BASE_PMC, PMC_PCER, (1 << pMci->mciId));\r
+\r
+    // Disable MCI clock, for multi-block data transfer\r
+    MCICK_DISABLE(pMciHw);\r
+\r
+    // Set Default Mode register value\r
+    mciMr = READ_MCI(pMciHw, MCI_MR) & (~( AT91C_MCI_WRPROOF\r
+                                          |AT91C_MCI_RDPROOF\r
+                                          |AT91C_MCI_BLKLEN));\r
+    // Command with DATA stage\r
+    if (pCommand->blockSize && pCommand->nbBlock) {\r
+        // Enable dma\r
+      #if defined(MCI_DMA_ENABLE)\r
+        mciDma = READ_MCI(pMciHw, MCI_DMA) | AT91C_MCI_DMAEN_ENABLE;\r
+        WRITE_MCI(pMciHw, MCI_DMA, mciDma);\r
+      #endif\r
+\r
+        // New transfer\r
+        if(pCommand->tranType == MCI_NEW_TRANSFER) {\r
+\r
+            // Set block size\r
+            WRITE_MCI(pMciHw, MCI_MR, mciMr | AT91C_MCI_RDPROOF\r
+                                            | AT91C_MCI_WRPROOF\r
+                                            |(pCommand->blockSize << 16));\r
+\r
+            mciBlkr = READ_MCI(pMciHw, MCI_BLKR) & (~AT91C_MCI_BCNT);\r
+            WRITE_MCI(pMciHw, MCI_BLKR, mciBlkr | pCommand->nbBlock);\r
+        }\r
+\r
+        transSize = (pCommand->nbBlock * pCommand->blockSize) / 4;\r
+        if ((pCommand->blockSize & 0x3) != 0)\r
+            transSize++;\r
+\r
+        // DATA transfer from card to host\r
+        if (pCommand->isRead) {\r
+            \r
+          #if defined(MCI_DMA_ENABLE)\r
+            DMACH_MCI_P2M(BOARD_MCI_DMA_CHANNEL,\r
+                          (unsigned int*)&pMciHw->MCI_FIFO,\r
+                          (unsigned int*) pCommand->pData,\r
+                          transSize, 1);\r
+            DMACH_EnableIt(pMciHw, BOARD_MCI_DMA_CHANNEL);\r
+            DMA_EnableChannel(BOARD_MCI_DMA_CHANNEL);\r
+            mciIer = AT91C_MCI_DMADONE | STATUS_ERRORS;\r
+          #else \r
+            mciIer = AT91C_MCI_CMDRDY | STATUS_ERRORS;\r
+          #endif\r
+        }\r
+        // DATA transfer from host to card\r
+        else {\r
+\r
+          #if defined(MCI_DMA_ENABLE)\r
+            DMACH_MCI_M2P(BOARD_MCI_DMA_CHANNEL,\r
+                          (unsigned int*) pCommand->pData,\r
+                          (unsigned int*)&pMciHw->MCI_FIFO,\r
+                          transSize, 1);\r
+            DMACH_EnableIt(pMciHw, BOARD_MCI_DMA_CHANNEL);\r
+            DMA_EnableChannel(BOARD_MCI_DMA_CHANNEL);\r
+            mciIer = AT91C_MCI_DMADONE | STATUS_ERRORS;\r
+          #else\r
+            mciIer = AT91C_MCI_CMDRDY | STATUS_ERRORS;\r
+          #endif\r
+        }\r
+    }\r
+    // Start an infinite block transfer (but no data in current command)\r
+    else if (pCommand->dataTran) {\r
+        // Set block size\r
+        WRITE_MCI(pMciHw, MCI_MR, mciMr | AT91C_MCI_RDPROOF\r
+                                        | AT91C_MCI_WRPROOF\r
+                                        |(pCommand->blockSize << 16));\r
+        // Set data length: 0\r
+        mciBlkr = READ_MCI(pMciHw, MCI_BLKR) & (~AT91C_MCI_BCNT);\r
+        WRITE_MCI(pMciHw, MCI_BLKR, mciBlkr);\r
+        mciIer = AT91C_MCI_CMDRDY | STATUS_ERRORS;\r
+    }\r
+    // No data transfer: stop at the end of the command\r
+    else{\r
+        WRITE_MCI(pMciHw, MCI_MR, mciMr);\r
+        mciIer = AT91C_MCI_CMDRDY | STATUS_ERRORS;\r
+    }\r
+\r
+    // Enable MCI clock\r
+    MCICK_ENABLE(pMciHw);\r
+\r
+    // Send the command\r
+    if((pCommand->tranType != MCI_CONTINUE_TRANSFER)\r
+        || (pCommand->blockSize == 0)) {\r
+\r
+        WRITE_MCI(pMciHw, MCI_ARGR, pCommand->arg);\r
+        WRITE_MCI(pMciHw, MCI_CMDR, pCommand->cmd);\r
+    }\r
+\r
+    // Ignore data error\r
+    mciIer &= ~(  AT91C_MCI_UNRE\r
+                | AT91C_MCI_OVRE\r
+                | AT91C_MCI_DTOE\r
+                | AT91C_MCI_DCRCE\r
+                | AT91C_MCI_BLKOVRE\r
+                | AT91C_MCI_CSTOE);\r
+\r
+    // Interrupt enable shall be done after PDC TXTEN and RXTEN\r
+    WRITE_MCI(pMciHw, MCI_IER, mciIer);\r
+\r
+    return 0;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Check NOTBUSY and DTIP bits of status register on the given MCI driver.\r
+/// Return value, 0 for bus ready, 1 for bus busy\r
+/// \param pMci  Pointer to a MCI driver instance.\r
+//------------------------------------------------------------------------------\r
+unsigned char MCI_CheckBusy(Mci *pMci)\r
+{\r
+    AT91S_MCI *pMciHw = pMci->pMciHw;\r
+    volatile unsigned int status;\r
+\r
+    // Enable MCI clock\r
+    MCICK_ENABLE(pMciHw);\r
+\r
+    status = READ_MCI(pMciHw, MCI_SR);\r
+\r
+    if(    ((status & AT91C_MCI_NOTBUSY)!=0)\r
+        && ((status & AT91C_MCI_DTIP)==0)\r
+        ) {\r
+\r
+        // Disable MCI clock\r
+        MCICK_DISABLE(pMciHw);\r
+\r
+        return 0;\r
+    }\r
+    else {\r
+        return 1;\r
+    }\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Check BLKE bit of status register on the given MCI driver.\r
+/// \param pMci  Pointer to a MCI driver instance.\r
+//------------------------------------------------------------------------------\r
+unsigned char MCI_CheckBlke(Mci *pMci)\r
+{\r
+    AT91S_MCI *pMciHw = pMci->pMciHw;\r
+    unsigned int status;\r
+\r
+    status = READ_MCI(pMciHw, MCI_SR);\r
+    // TRACE_DEBUG("status %x\n\r",status);\r
+\r
+    if((status & AT91C_MCI_BLKE)!=0) {\r
+        return 0;\r
+    }\r
+    else {\r
+        return 1;\r
+    }\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Processes pending events on the given MCI driver.\r
+/// \param pMci  Pointer to a MCI driver instance.\r
+//------------------------------------------------------------------------------\r
+void MCI_Handler(Mci *pMci)\r
+{\r
+    AT91S_MCI *pMciHw = pMci->pMciHw;\r
+    volatile MciCmd *pCommand = pMci->pCommand;\r
+    volatile unsigned int status, status0, mask;\r
+    unsigned char i;\r
+\r
+    SANITY_CHECK(pMci);\r
+    SANITY_CHECK(pMciHw);\r
+    SANITY_CHECK(pCommand);\r
+\r
+    // Read the status register\r
+    status0 = READ_MCI(pMciHw, MCI_SR);\r
+    mask    = READ_MCI(pMciHw, MCI_IMR);\r
+    //TRACE_INFO("iST %x\n\r", status);\r
+    status  = status0 & mask;\r
+    //TRACE_INFO("iSM %x\n\r", status);\r
+\r
+    // Check if an error has occured\r
+    if ((status & STATUS_ERRORS) != 0) {\r
+\r
+        // Check error code\r
+        if ((status & STATUS_ERRORS) == AT91C_MCI_RTOE) {\r
+\r
+            pCommand->status = MCI_STATUS_NORESPONSE;\r
+        }\r
+        // if the command is SEND_OP_COND the CRC error flag is always present\r
+        // (cf : R3 response)\r
+        else if ((   (status & STATUS_ERRORS) != AT91C_MCI_RCRCE)\r
+                  || (   (pCommand->cmd != SDCARD_APP_OP_COND_CMD)\r
+                      && (pCommand->cmd != MMC_SEND_OP_COND_CMD))) {\r
+\r
+            pCommand->status = MCI_STATUS_ERROR;\r
+        }\r
+        // printf("iErr%x\n\r", (status & STATUS_ERRORS));\r
+    }\r
+    mask &= ~STATUS_ERRORS;\r
+\r
+    // Check if a command has been completed\r
+    if (status & AT91C_MCI_CMDRDY) {\r
+\r
+        WRITE_MCI(pMciHw, MCI_IDR, AT91C_MCI_CMDRDY);\r
+        if (pCommand->isRead == 0 &&\r
+            pCommand->tranType == MCI_STOP_TRANSFER) {\r
+            if (status0 & AT91C_MCI_XFRDONE) {\r
+                MCICK_DISABLE(pMciHw);\r
+            }\r
+            else {\r
+                WRITE_MCI(pMciHw, MCI_IER, AT91C_MCI_XFRDONE);\r
+            }\r
+        }\r
+        else {\r
+            mask &= ~AT91C_MCI_CMDRDY;\r
+            if (pCommand->dataTran == 0) {\r
+                MCICK_DISABLE(pMciHw);\r
+            }\r
+        }\r
+    }\r
+\r
+    // Check if transfer stopped\r
+    if (status & AT91C_MCI_XFRDONE) {\r
+        mask &= ~AT91C_MCI_XFRDONE;\r
+        MCICK_DISABLE(pMciHw);\r
+    }\r
+\r
+#if defined(MCI_DMA_ENABLE)\r
+\r
+    // Check FIFOEMPTY\r
+    if (status & AT91C_MCI_FIFOEMPTY) {\r
+        mask &= ~AT91C_MCI_FIFOEMPTY;\r
+        MCICK_DISABLE(pMciHw);\r
+    }\r
+\r
+    // Check if a DMA transfer has been completed\r
+    if (status & AT91C_MCI_DMADONE) {\r
+\r
+        unsigned int intFlag;\r
+        intFlag = DMA_GetInterruptMask();\r
+        intFlag = ~intFlag;\r
+        intFlag |= (AT91C_HDMA_BTC0 << BOARD_MCI_DMA_CHANNEL);\r
+        DMA_DisableIt(intFlag);\r
+\r
+        WRITE_MCI(pMciHw, MCI_IDR, AT91C_MCI_DMADONE);\r
+        if ( pCommand->isRead == 0 &&\r
+            (status0 & AT91C_MCI_FIFOEMPTY) == 0 ) {\r
+            WRITE_MCI(pMciHw, MCI_IER, AT91C_MCI_FIFOEMPTY);\r
+        }\r
+        else {\r
+            MCICK_DISABLE(pMciHw);\r
+            mask &= ~AT91C_MCI_DMADONE;\r
+        }\r
+    }\r
+#endif\r
+\r
+    // All non-error mask done, complete the command\r
+    if (!mask || pCommand->status != MCI_STATUS_PENDING) {\r
+\r
+        // Store the card response in the provided buffer\r
+        if (pCommand->pResp) {\r
+            unsigned char resSize;\r
+            switch (pCommand->resType) {\r
+            case 1: case 3: case 4: case 5: case 6: case 7:\r
+                     resSize = 1;           break;\r
+            case 2:  resSize = 4;           break;\r
+            default: resSize = 0;           break;\r
+            }\r
+            for (i=0; i < resSize; i++) {\r
+                pCommand->pResp[i] = READ_MCI(pMciHw, MCI_RSPR[0]);\r
+            }\r
+        }\r
+\r
+        // If no error occured, the transfer is successful\r
+        if (pCommand->status == MCI_STATUS_PENDING)\r
+            pCommand->status = 0;\r
+\r
+        // Disable interrupts\r
+        WRITE_MCI(pMciHw, MCI_IDR, READ_MCI(pMciHw, MCI_IMR));\r
+        \r
+        // Release the semaphore\r
+        pMci->semaphore++;\r
+\r
+        // Invoke the callback associated with the current command (if any)\r
+        if (pCommand->callback) {\r
+            (pCommand->callback)(pCommand->status, (void*)pCommand);\r
+        }\r
+    }\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Returns 1 if the given MCI transfer is complete; otherwise returns 0.\r
+/// \param pCommand  Pointer to a MciCmd instance.\r
+//------------------------------------------------------------------------------\r
+unsigned char MCI_IsTxComplete(MciCmd *pCommand)\r
+{\r
+    if (pCommand->status != MCI_STATUS_PENDING) {\r
+        if (pCommand->status != 0) {\r
+            TRACE_DEBUG("MCI_IsTxComplete %d\n\r", pCommand->status);\r
+        }\r
+        return 1;\r
+    }\r
+    else {\r
+        return 0;\r
+    }\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Check whether the MCI is using the FIFO transfer mode\r
+/// \param pMci  Pointer to a Mci instance.\r
+/// \param pCommand  Pointer to a MciCmd instance.\r
+//------------------------------------------------------------------------------\r
+unsigned int MCI_FifoTransfer(Mci *pMci, MciCmd *pCommand)\r
+{\r
+    unsigned int status=0;\r
+    unsigned int nbTransfer=0;\r
+    unsigned int i;\r
+    AT91S_MCI *pMciHw = pMci->pMciHw;\r
+    unsigned int *pMem;\r
+\r
+    SANITY_CHECK(pMci);\r
+    SANITY_CHECK(pCommand);\r
+\r
+    // If using DMA mode, return\r
+#if defined(MCI_DMA_ENABLE)\r
+    return 0;\r
+#endif\r
+\r
+    TRACE_DEBUG("MCIFifo:%d,%d\n\r", pCommand->isRead, pCommand->nbBlock);\r
+\r
+    if (pCommand->nbBlock == 0 || pCommand->blockSize == 0)\r
+        return 0;\r
+\r
+    pMem = (unsigned int*)pCommand->pData;\r
+\r
+    // Get transfer size\r
+    nbTransfer = (pCommand->blockSize) * (pCommand->nbBlock) / 4;\r
+    if((pCommand->blockSize) * (pCommand->nbBlock) % 4) {\r
+        nbTransfer++;\r
+    }\r
+\r
+    if (pCommand->isRead) {\r
+\r
+        // Read RDR loop\r
+        for(i=0; i<nbTransfer; i++) {\r
+            while(1) {\r
+                status = READ_MCI(pMciHw, MCI_SR);\r
+                if (status & AT91C_MCI_RXRDY)\r
+                    break;\r
+              #if 1\r
+                if (status & STATUS_ERRORS_DATA) {\r
+                    TRACE_ERROR("MCI_FifoTransfer.R: 0x%x\n\r", status);\r
+                    return status;\r
+                }\r
+              #endif\r
+            }\r
+            *pMem = READ_MCI(pMciHw, MCI_RDR);\r
+            pMem++;\r
+        }\r
+    }\r
+    else {\r
+\r
+        // Write TDR loop\r
+        for(i=0; i<nbTransfer; i++) {\r
+            while(1) {\r
+                status = READ_MCI(pMciHw, MCI_SR);\r
+                if (status & (AT91C_MCI_TXRDY | AT91C_MCI_NOTBUSY))\r
+                    break;\r
+              #if 0\r
+                if (status & STATUS_ERRORS_DATA) {\r
+                    TRACE_ERROR("MCI_FifoTransfer.W: 0x%x\n\r", status);\r
+                    return status;\r
+                }\r
+              #endif\r
+            }\r
+            WRITE_MCI(pMciHw, MCI_TDR, *pMem);\r
+            pMem++;\r
+        }\r
+    }\r
+\r
+    status = READ_MCI(pMciHw, MCI_SR);\r
+    TRACE_DEBUG("MCI_FifoTransfer : All status %x\n\r", status);\r
+    status &= READ_MCI(pMciHw, MCI_IMR);\r
+    TRACE_DEBUG("MCI_FifoTransfer : Masked status %x\n\r", status);\r
+\r
+  #if 0\r
+  { unsigned int old = status;\r
+    while(status & AT91C_MCI_DTIP) {\r
+        status = READ_MCI(pMciHw, MCI_SR);\r
+        if (status != old) {\r
+            old = status;\r
+            TRACE_DEBUG_WP(" -> %x", status);\r
+        }\r
+    }\r
+    TRACE_DEBUG_WP("\n\r");\r
+    TRACE_DEBUG(" DPIT 0 stat %x\n\r", status);\r
+    while((status & (AT91C_MCI_FIFOEMPTY\r
+                        | AT91C_MCI_BLKE\r
+                        | AT91C_MCI_XFRDONE)) == 0) {\r
+        status = READ_MCI(pMciHw, MCI_SR);\r
+    }\r
+    TRACE_DEBUG(" FIFO EMPTY stat %x\n\r", status);\r
+  }\r
+  #endif\r
+\r
+    return status;\r
+}\r

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/mci/mci_hs.h b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/mci/mci_hs.h
new file mode 100644 (file)
index 0000000..bab2794
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/mci/mci_hs.h
@@ -0,0 +1,205 @@
+/* ----------------------------------------------------------------------------\r
+ *         ATMEL Microcontroller Software Support\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+//------------------------------------------------------------------------------\r
+/// \page "mci"\r
+///\r
+/// !Purpose\r
+///  \r
+/// mci-interface driver\r
+///\r
+/// !Usage\r
+///\r
+/// -# MCI_Init: Initializes a MCI driver instance and the underlying peripheral.\r
+/// -# MCI_SetSpeed : Configure the  MCI CLKDIV in the MCI_MR register.\r
+/// -# MCI_SendCommand: Starts a MCI  transfer.\r
+/// -# MCI_Handler : Interrupt handler which is called by ISR handler.\r
+/// -# MCI_SetBusWidth : Configure the  MCI SDCBUS in the MCI_SDCR register.\r
+//------------------------------------------------------------------------------\r
+\r
+\r
+#ifndef MCI_HS_H\r
+#define MCI_HS_H\r
+\r
+//------------------------------------------------------------------------------\r
+//         Headers\r
+//------------------------------------------------------------------------------\r
+\r
+#include <board.h>\r
+\r
+//------------------------------------------------------------------------------\r
+//         Constants\r
+//------------------------------------------------------------------------------\r
+\r
+/// Transfer is pending.\r
+#define MCI_STATUS_PENDING      1\r
+/// Transfer has been aborted because an error occured.\r
+#define MCI_STATUS_ERROR        2\r
+/// Card did not answer command.\r
+#define MCI_STATUS_NORESPONSE   3\r
+\r
+/// MCI driver is currently in use.\r
+#define MCI_ERROR_LOCK    1\r
+\r
+/// MCI configuration with 1-bit data bus on slot A (for MMC cards).\r
+#define MCI_MMC_SLOTA           (AT91C_MCI_SCDSEL_SLOTA | AT91C_MCI_SCDBUS_1BIT)\r
+/// MCI configuration with 4-bit data bus on slot A (for SD cards).\r
+#define MCI_SD_SLOTA            (AT91C_MCI_SCDSEL_SLOTA | AT91C_MCI_SCDBUS_4BITS)\r
+#ifdef AT91C_MCI_SCDBUS_8BITS\r
+/// MCI configuration with 1-bit data bus on slot A (for MMC cards).\r
+#define MCI_MMC4_SLOTA          (AT91C_MCI_SCDSEL_SLOTA | AT91C_MCI_SCDBUS_8BITS)\r
+#endif\r
+#ifdef AT91C_MCI_SCDSEL_SLOTB\r
+/// MCI configuration with 1-bit data bus on slot B (for MMC cards).\r
+#define MCI_MMC_SLOTB           (AT91C_MCI_SCDSEL_SLOTB | AT91C_MCI_SCDBUS_1BIT)\r
+/// MCI configuration with 4-bit data bus on slot B (for SD cards).\r
+#define MCI_SD_SLOTB            (AT91C_MCI_SCDSEL_SLOTB | AT91C_MCI_SCDBUS_4BITS)\r
+#ifdef AT91C_MCI_SCDBUS_8BITS\r
+/// MCI configuration with 1-bit data bus on slot A (for MMC cards).\r
+#define MCI_MMC4_SLOTB          (AT91C_MCI_SCDSEL_SLOTB | AT91C_MCI_SCDBUS_8BITS)\r
+#endif\r
+#else\r
+#define MCI_MMC_SLOTB           MCI_MMC_SLOTA\r
+#define MCI_SD_SLOTB            MCI_SD_SLOTA\r
+#endif\r
+\r
+/// Start new data transfer\r
+#define MCI_NEW_TRANSFER        0\r
+/// Continue data transfer\r
+#define MCI_CONTINUE_TRANSFER   1\r
+/// Stop data transfer\r
+#define MCI_STOP_TRANSFER       2\r
+\r
+/// MCI SD Bus Width 1-bit\r
+#define MCI_SDCBUS_1BIT (0 << 7)\r
+/// MCI SD Bus Width 4-bit\r
+#define MCI_SDCBUS_4BIT (1 << 7)\r
+/// MCI SD Bus Width 8-bit\r
+#define MCI_SDCBUS_8BIT (3 << 6)\r
+\r
+/// The MCI Clock Speed after initialize (400K)\r
+#define MCI_INITIAL_SPEED       400000\r
+\r
+/// MCI using DMA?\r
+#define MCI_DMA_ENABLE          1\r
+\r
+//------------------------------------------------------------------------------\r
+//         Types\r
+//------------------------------------------------------------------------------\r
+\r
+/// MCI end-of-transfer callback function.\r
+typedef void (*MciCallback)(unsigned char status, void *pCommand);\r
+\r
+//------------------------------------------------------------------------------\r
+/// MCI Transfer Request prepared by the application upper layer. This structure\r
+/// is sent to the MCI_SendCommand function to start the transfer. At the end of\r
+/// the transfer, the callback is invoked by the interrupt handler.\r
+//------------------------------------------------------------------------------\r
+typedef struct _MciCmd {\r
+\r
+    /// Command code.\r
+    unsigned int cmd;\r
+    /// Command argument.\r
+    unsigned int arg;\r
+    /// Data buffer.\r
+    unsigned char *pData;\r
+    /// Size of data block in bytes.\r
+    unsigned short blockSize;\r
+    /// Number of blocks to be transfered\r
+    unsigned short nbBlock;\r
+    /// Response buffer.\r
+    unsigned int  *pResp;\r
+    /// Optional user-provided callback function.\r
+    MciCallback callback;\r
+    /// Optional argument to the callback function.\r
+    void *pArg;\r
+    /// SD card response type.\r
+    unsigned char  resType;\r
+    /// Indicate if there is data transfer\r
+    unsigned char dataTran;\r
+    /// Indicate if continue to transfer data\r
+    unsigned char tranType;\r
+    /// Indicates if the command is a read operation.\r
+    unsigned char isRead;\r
+\r
+    /// Command status.\r
+    volatile int status;\r
+} MciCmd;\r
+\r
+//------------------------------------------------------------------------------\r
+/// MCI driver structure. Holds the internal state of the MCI driver and\r
+/// prevents parallel access to a MCI peripheral.\r
+//------------------------------------------------------------------------------\r
+typedef struct {\r
+\r
+    /// Pointer to a MCI peripheral.\r
+    AT91S_MCI *pMciHw;\r
+    /// Pointer to currently executing command.\r
+    MciCmd *pCommand;\r
+    /// MCI peripheral identifier.\r
+    unsigned char mciId;\r
+    /// MCI HW mode\r
+    unsigned char mciMode;\r
+    /// Mutex.\r
+    volatile char semaphore;\r
+} Mci;\r
+\r
+//------------------------------------------------------------------------------\r
+//         Global functions\r
+//------------------------------------------------------------------------------\r
+\r
+extern void MCI_Init(\r
+    Mci *pMci,\r
+    AT91PS_MCI pMciHw,\r
+    unsigned char mciId,\r
+    unsigned int mode);\r
+extern unsigned int MCI_GetSpeed(Mci *pMci, unsigned int *mciDiv);\r
+\r
+extern unsigned int MCI_SetSpeed(Mci *pMci,\r
+                                 unsigned int mciSpeed,\r
+                                 unsigned int mciLimit);\r
+\r
+extern unsigned char MCI_SendCommand(Mci *pMci, MciCmd *pMciCmd);\r
+\r
+extern void MCI_Handler(Mci *pMci);\r
+\r
+extern unsigned char MCI_IsTxComplete(MciCmd *pMciCmd);\r
+\r
+extern unsigned char MCI_CheckBusy(Mci *pMci);\r
+\r
+extern void MCI_Close(Mci *pMci);\r
+\r
+extern void MCI_EnableHsMode(Mci * pMci, unsigned char hsEnable);\r
+\r
+extern void MCI_SetBusWidth(Mci *pMci, unsigned char busWidth);\r
+\r
+extern unsigned int MCI_FifoTransfer(Mci * pMci, MciCmd * pCommand);\r
+\r
+#endif //#ifndef MCI_HS_H\r
+\r

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/pio/pio.c b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/pio/pio.c
new file mode 100644 (file)
index 0000000..288e6bb
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/pio/pio.c
@@ -0,0 +1,382 @@
+/* ----------------------------------------------------------------------------\r
+ *         ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+//------------------------------------------------------------------------------\r
+//         Headers\r
+//------------------------------------------------------------------------------\r
+\r
+#include "pio.h"\r
+#include <board.h>\r
+\r
+//------------------------------------------------------------------------------\r
+//         Local Functions\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+/// Configures one or more pin(s) of a PIO controller as being controlled by\r
+/// peripheral A. Optionally, the corresponding internal pull-up(s) can be\r
+/// enabled.\r
+/// \param pio  Pointer to a PIO controller.\r
+/// \param mask  Bitmask of one or more pin(s) to configure.\r
+/// \param enablePullUp  Indicates if the pin(s) internal pull-up shall be\r
+///                      configured.\r
+//------------------------------------------------------------------------------\r
+static void PIO_SetPeripheralA(\r
+    AT91S_PIO *pio,\r
+    unsigned int mask,\r
+    unsigned char enablePullUp)\r
+{\r
+#if !defined(AT91C_PIOA_ASR)\r
+    unsigned int abmr;\r
+#endif\r
+\r
+    // Disable interrupts on the pin(s)\r
+    pio->PIO_IDR = mask;\r
+\r
+    // Enable the pull-up(s) if necessary\r
+    if (enablePullUp) {\r
+\r
+        pio->PIO_PPUER = mask;\r
+    }\r
+    else {\r
+\r
+        pio->PIO_PPUDR = mask;\r
+    }\r
+\r
+    // Configure pin\r
+#if defined(AT91C_PIOA_ASR)\r
+    pio->PIO_ASR = mask;\r
+#else\r
+    abmr = pio->PIO_ABSR;\r
+    pio->PIO_ABSR &= (~mask & abmr);\r
+#endif\r
+    pio->PIO_PDR = mask;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Configures one or more pin(s) of a PIO controller as being controlled by\r
+/// peripheral B. Optionally, the corresponding internal pull-up(s) can be\r
+/// enabled.\r
+/// \param pio  Pointer to a PIO controller.\r
+/// \param mask  Bitmask of one or more pin(s) to configure.\r
+/// \param enablePullUp  Indicates if the pin(s) internal pull-up shall be\r
+///                      configured.\r
+//------------------------------------------------------------------------------\r
+static void PIO_SetPeripheralB(\r
+    AT91S_PIO *pio,\r
+    unsigned int mask,\r
+    unsigned char enablePullUp)\r
+{\r
+#if !defined(AT91C_PIOA_BSR)\r
+    unsigned int abmr;\r
+#endif\r
+\r
+    // Disable interrupts on the pin(s)\r
+    pio->PIO_IDR = mask;\r
+\r
+    // Enable the pull-up(s) if necessary\r
+    if (enablePullUp) {\r
+\r
+        pio->PIO_PPUER = mask;\r
+    }\r
+    else {\r
+\r
+        pio->PIO_PPUDR = mask;\r
+    }\r
+\r
+    // Configure pin\r
+#if defined(AT91C_PIOA_BSR)\r
+    pio->PIO_BSR = mask;\r
+#else\r
+    abmr = pio->PIO_ABSR;\r
+    pio->PIO_ABSR = mask | abmr;\r
+#endif\r
+    pio->PIO_PDR = mask;\r
+}\r
+\r
+#if defined(AT91C_PIOA_IFDGSR) //Glitch or Debouncing filter selection supported\r
+//------------------------------------------------------------------------------\r
+/// Configures Glitch or Debouncing filter for input\r
+/// \param pio      Pointer to a PIO controller.\r
+/// \param mask   Bitmask for filter selection.\r
+///                     each of 32 bit field, 0 is Glitch, 1 is Debouncing\r
+/// \param clkDiv  Clock divider if Debouncing select, using the lowest 14 bits\r
+///                     common for all PIO line of selecting deboucing filter\r
+//------------------------------------------------------------------------------\r
+static void PIO_SetFilter(\r
+    AT91S_PIO *pio,\r
+    unsigned int filterSel,\r
+    unsigned int clkDiv)\r
+{\r
+    pio->PIO_DIFSR = filterSel;//set Debouncing, 0 bit field no effect\r
+    pio->PIO_SCIFSR = ~filterSel;//set Glitch, 0 bit field no effect\r
+\r
+    pio->PIO_SCDR = clkDiv & 0x3FFF;//the lowest 14 bits work\r
+}\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+/// Configures one or more pin(s) or a PIO controller as inputs. Optionally,\r
+/// the corresponding internal pull-up(s) and glitch filter(s) can be\r
+/// enabled.\r
+/// \param pio  Pointer to a PIO controller.\r
+/// \param mask  Bitmask indicating which pin(s) to configure as input(s).\r
+/// \param enablePullUp  Indicates if the internal pull-up(s) must be enabled.\r
+/// \param enableFilter  Indicates if the glitch filter(s) must be enabled.\r
+//------------------------------------------------------------------------------\r
+static void PIO_SetInput(\r
+    AT91S_PIO *pio,\r
+    unsigned int mask,\r
+    unsigned char enablePullUp,\r
+    unsigned char enableFilter)\r
+{\r
+    // Disable interrupts\r
+    pio->PIO_IDR = mask;\r
+\r
+    // Enable pull-up(s) if necessary\r
+    if (enablePullUp) {\r
+    \r
+        pio->PIO_PPUER = mask;\r
+    }\r
+    else {\r
+    \r
+        pio->PIO_PPUDR = mask;\r
+    }\r
+\r
+    // Enable filter(s) if necessary\r
+    if (enableFilter) {\r
+    \r
+        pio->PIO_IFER = mask;\r
+    }\r
+    else {\r
+    \r
+        pio->PIO_IFDR = mask;\r
+    }\r
+\r
+    // Configure pin as input\r
+    pio->PIO_ODR = mask;\r
+    pio->PIO_PER = mask;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Configures one or more pin(s) of a PIO controller as outputs, with the\r
+/// given default value. Optionally, the multi-drive feature can be enabled\r
+/// on the pin(s).\r
+/// \param pio  Pointer to a PIO controller.\r
+/// \param mask  Bitmask indicating which pin(s) to configure.\r
+/// \param defaultValue  Default level on the pin(s).\r
+/// \param enableMultiDrive  Indicates if the pin(s) shall be configured as\r
+///                          open-drain.\r
+/// \param enablePullUp  Indicates if the pin shall have its pull-up activated.\r
+//------------------------------------------------------------------------------\r
+static void PIO_SetOutput(\r
+    AT91S_PIO *pio,\r
+    unsigned int mask,\r
+    unsigned char defaultValue,\r
+    unsigned char enableMultiDrive,\r
+    unsigned char enablePullUp)\r
+{\r
+    // Disable interrupts\r
+    pio->PIO_IDR = mask;\r
+\r
+    // Enable pull-up(s) if necessary\r
+    if (enablePullUp) {\r
+    \r
+        pio->PIO_PPUER = mask;\r
+    }\r
+    else {\r
+    \r
+        pio->PIO_PPUDR = mask;\r
+    }\r
+\r
+    // Enable multi-drive if necessary\r
+    if (enableMultiDrive) {\r
+    \r
+        pio->PIO_MDER = mask;\r
+    }\r
+    else {\r
+    \r
+        pio->PIO_MDDR = mask;\r
+    }\r
+\r
+    // Set default value\r
+    if (defaultValue) {\r
+\r
+        pio->PIO_SODR = mask;\r
+    }\r
+    else {\r
+\r
+        pio->PIO_CODR = mask;\r
+    }\r
+\r
+    // Configure pin(s) as output(s)\r
+    pio->PIO_OER = mask;\r
+    pio->PIO_PER = mask;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+//         Global Functions\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+/// Configures a list of Pin instances, each of which can either hold a single\r
+/// pin or a group of pins, depending on the mask value; all pins are configured\r
+/// by this function. The size of the array must also be provided and is easily\r
+/// computed using PIO_LISTSIZE whenever its length is not known in advance.\r
+/// \param list  Pointer to a list of Pin instances.\r
+/// \param size  Size of the Pin list (calculated using PIO_LISTSIZE).\r
+/// \return 1 if the pins have been configured properly; otherwise 0.\r
+//------------------------------------------------------------------------------\r
+unsigned char PIO_Configure(const Pin *list, unsigned int size)\r
+{\r
+    // Configure pins\r
+    while (size > 0) {\r
+    \r
+        switch (list->type) {\r
+    \r
+            case PIO_PERIPH_A:\r
+                PIO_SetPeripheralA(list->pio,\r
+                                   list->mask,\r
+                                   (list->attribute & PIO_PULLUP) ? 1 : 0);\r
+                break;\r
+    \r
+            case PIO_PERIPH_B:\r
+                PIO_SetPeripheralB(list->pio,\r
+                                   list->mask,\r
+                                   (list->attribute & PIO_PULLUP) ? 1 : 0);\r
+                break;\r
+    \r
+            case PIO_INPUT:\r
+                AT91C_BASE_PMC->PMC_PCER = 1 << list->id;\r
+                PIO_SetInput(list->pio,\r
+                             list->mask,\r
+                             (list->attribute & PIO_PULLUP) ? 1 : 0,\r
+                             (list->attribute & PIO_DEGLITCH)? 1 : 0);\r
+\r
+                #if defined(AT91C_PIOA_IFDGSR) //PIO3 with Glitch or Debouncing selection\r
+                //if glitch input filter enabled, set it\r
+                if(list->attribute & PIO_DEGLITCH)//Glitch input filter enabled\r
+                    PIO_SetFilter(list->pio,\r
+                        list->inFilter.filterSel,\r
+                        list->inFilter.clkDivider);\r
+                #endif\r
+                break;\r
+    \r
+            case PIO_OUTPUT_0:\r
+            case PIO_OUTPUT_1:\r
+                PIO_SetOutput(list->pio,\r
+                              list->mask,\r
+                              (list->type == PIO_OUTPUT_1),\r
+                              (list->attribute & PIO_OPENDRAIN) ? 1 : 0,\r
+                              (list->attribute & PIO_PULLUP) ? 1 : 0);\r
+                break;\r
+    \r
+            default: return 0;\r
+        }\r
+\r
+        list++;\r
+        size--;\r
+    }\r
+\r
+    return 1;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Sets a high output level on all the PIOs defined in the given Pin instance.\r
+/// This has no immediate effects on PIOs that are not output, but the PIO\r
+/// controller will memorize the value they are changed to outputs.\r
+/// \param pin  Pointer to a Pin instance describing one or more pins.\r
+//------------------------------------------------------------------------------\r
+void PIO_Set(const Pin *pin)\r
+{\r
+    pin->pio->PIO_SODR = pin->mask;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Sets a low output level on all the PIOs defined in the given Pin instance.\r
+/// This has no immediate effects on PIOs that are not output, but the PIO\r
+/// controller will memorize the value they are changed to outputs.\r
+/// \param pin  Pointer to a Pin instance describing one or more pins.\r
+//------------------------------------------------------------------------------\r
+void PIO_Clear(const Pin *pin)\r
+{\r
+    pin->pio->PIO_CODR = pin->mask;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Returns 1 if one or more PIO of the given Pin instance currently have a high\r
+/// level; otherwise returns 0. This method returns the actual value that is\r
+/// being read on the pin. To return the supposed output value of a pin, use\r
+/// PIO_GetOutputDataStatus() instead.\r
+/// \param pin  Pointer to a Pin instance describing one or more pins.\r
+/// \return 1 if the Pin instance contains at least one PIO that currently has\r
+/// a high level; otherwise 0.\r
+//------------------------------------------------------------------------------\r
+unsigned char PIO_Get(const Pin *pin)\r
+{\r
+    unsigned int reg;\r
+    if ((pin->type == PIO_OUTPUT_0) || (pin->type == PIO_OUTPUT_1)) {\r
+\r
+        reg = pin->pio->PIO_ODSR;\r
+    }\r
+    else {\r
+\r
+        reg = pin->pio->PIO_PDSR;\r
+    }\r
+\r
+    if ((reg & pin->mask) == 0) {\r
+\r
+        return 0;\r
+    }\r
+    else {\r
+\r
+        return 1;\r
+    }\r
+}\r
+\r
+\r
+//------------------------------------------------------------------------------\r
+/// Returns 1 if one or more PIO of the given Pin are configured to output a\r
+/// high level (even if they are not output).\r
+/// To get the actual value of the pin, use PIO_Get() instead.\r
+/// \param pin  Pointer to a Pin instance describing one or more pins.\r
+/// \return 1 if the Pin instance contains at least one PIO that is configured\r
+/// to output a high level; otherwise 0.\r
+//------------------------------------------------------------------------------\r
+unsigned char PIO_GetOutputDataStatus(const Pin *pin)\r
+{\r
+    if ((pin->pio->PIO_ODSR & pin->mask) == 0) {\r
+\r
+        return 0;\r
+    }\r
+    else {\r
+\r
+        return 1;\r
+    }\r
+}\r

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/pio/pio.h b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/pio/pio.h
new file mode 100644 (file)
index 0000000..2c78d73
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/pio/pio.h
@@ -0,0 +1,225 @@
+/* ----------------------------------------------------------------------------\r
+ *         ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+//------------------------------------------------------------------------------\r
+/// \unit\r
+///\r
+/// !!!Purpose\r
+/// \r
+/// This file provides a basic API for PIO configuration and usage of\r
+/// user-controlled pins. Please refer to the board.h file for a list of\r
+/// available pin definitions.\r
+/// \r
+/// !!!Usage\r
+/// \r
+/// -# Define a constant pin description array such as the following one, using\r
+///    the existing definitions provided by the board.h file if possible:\r
+///    \code\r
+///       const Pin pPins[] = {PIN_USART0_TXD, PIN_USART0_RXD};\r
+///    \endcode\r
+///    Alternatively, it is possible to add new pins by provided the full Pin\r
+///    structure:\r
+///    \code\r
+///    // Pin instance to configure PA10 & PA11 as inputs with the internal\r
+///    // pull-up enabled.\r
+///    const Pin pPins = {\r
+///         (1 << 10) | (1 << 11),\r
+///         AT91C_BASE_PIOA,\r
+///         AT91C_ID_PIOA,\r
+///         PIO_INPUT,\r
+///         PIO_PULLUP\r
+///    };\r
+///    \endcode\r
+/// -# Configure a pin array by calling PIO_Configure() with a pointer to the\r
+///    array and its size (which is computed using the PIO_LISTSIZE macro).\r
+/// -# Change and get the value of a user-controlled pin using the PIO_Set,\r
+///    PIO_Clear and PIO_Get methods.\r
+/// -# Get the level being currently output by a user-controlled pin configured\r
+///    as an output using PIO_GetOutputDataStatus().\r
+//------------------------------------------------------------------------------\r
+ \r
+#ifndef PIO_H\r
+#define PIO_H\r
+\r
+//------------------------------------------------------------------------------\r
+//         Headers\r
+//------------------------------------------------------------------------------\r
+\r
+#include <board.h>\r
+\r
+//------------------------------------------------------------------------------\r
+//         Global Definitions\r
+//------------------------------------------------------------------------------\r
+\r
+/// The pin is controlled by the associated signal of peripheral A.\r
+#define PIO_PERIPH_A                0\r
+/// The pin is controlled by the associated signal of peripheral B.\r
+#define PIO_PERIPH_B                1\r
+/// The pin is an input.\r
+#define PIO_INPUT                   2\r
+/// The pin is an output and has a default level of 0.\r
+#define PIO_OUTPUT_0                3\r
+/// The pin is an output and has a default level of 1.\r
+#define PIO_OUTPUT_1                4\r
+\r
+/// Default pin configuration (no attribute).\r
+#define PIO_DEFAULT                 (0 << 0)\r
+/// The internal pin pull-up is active.\r
+#define PIO_PULLUP                  (1 << 0)\r
+/// The internal glitch filter is active.\r
+#define PIO_DEGLITCH                (1 << 1)\r
+/// The pin is open-drain.\r
+#define PIO_OPENDRAIN               (1 << 2)\r
+\r
+//------------------------------------------------------------------------------\r
+//         Global Macros\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+/// Calculates the size of an array of Pin instances. The array must be defined\r
+/// locally (i.e. not a pointer), otherwise the computation will not be correct.\r
+/// \param pPins  Local array of Pin instances.\r
+/// \return Number of elements in array.\r
+//------------------------------------------------------------------------------\r
+#define PIO_LISTSIZE(pPins)    (sizeof(pPins) / sizeof(Pin))\r
+\r
+//------------------------------------------------------------------------------\r
+//         Global Types\r
+//------------------------------------------------------------------------------\r
+typedef struct _ExtIntMode {\r
+  ///indicate which pin to enable/disable additional Interrupt mode\r
+  ///each of 32 bit field represents one PIO line.\r
+  unsigned int itMask;\r
+  ///select Edge or level interrupt detection source\r
+  ///each of 32 bit field represents one PIO line, 0 is Edge, 1 is Level\r
+  unsigned int edgeLvlSel;\r
+  ///select rising/high or falling/low detection event\r
+  ///each of 32 bit field represents one PIO line:\r
+  ///0 is Falling Edge detection event (if selected Edge interrupt \r
+  ///   detection source, or Low Level detection (if selected\r
+  ///   Level interrupt detection source;\r
+  ///1 is Rising Edge detection(if selected Edge interrupt \r
+  ///   source, or Low Level detection event(if selected Level\r
+  ///   interrupt detection source.\r
+  unsigned int lowFallOrRiseHighSel;\r
+\r
+} ExtIntMode;\r
+\r
+typedef struct _GlitchDeBounceFilter {\r
+  ///Select Glitch/Debounce filtering for PIO input\r
+  ///each of 32 bit field represents one PIO line\r
+  ///0 is Glitch, 1 is Debouncing\r
+  unsigned int filterSel;\r
+  ///slow clock divider selection for Debouncing filter\r
+  unsigned int clkDivider:14;\r
+\r
+} GlitchDebounceFilter;\r
+\r
+//------------------------------------------------------------------------------\r
+/// Describes the type and attribute of one PIO pin or a group of similar pins.\r
+/// The #type# field can have the following values:\r
+///    - PIO_PERIPH_A\r
+///    - PIO_PERIPH_B\r
+///    - PIO_OUTPUT_0\r
+///    - PIO_OUTPUT_1\r
+///    - PIO_INPUT\r
+///\r
+/// The #attribute# field is a bitmask that can either be set to PIO_DEFAULt,\r
+/// or combine (using bitwise OR '|') any number of the following constants:\r
+///    - PIO_PULLUP\r
+///    - PIO_DEGLITCH\r
+///    - PIO_OPENDRAIN\r
+//------------------------------------------------------------------------------\r
+typedef struct {\r
+\r
+    /// Bitmask indicating which pin(s) to configure.\r
+    unsigned int mask; \r
+    /// Pointer to the PIO controller which has the pin(s).\r
+    AT91S_PIO    *pio;\r
+    /// Peripheral ID of the PIO controller which has the pin(s).\r
+    unsigned char id;\r
+    /// Pin type.\r
+    unsigned char type;\r
+    /// Pin attribute.\r
+    unsigned char attribute;\r
+#if defined(AT91C_PIOA_AIMMR)\r
+    ///Additional Interrupt Mode\r
+    ExtIntMode itMode;\r
+#endif\r
+\r
+#if defined(AT91C_PIOA_IFDGSR)\r
+    ///Glitch/Debouncing filter\r
+    GlitchDebounceFilter inFilter;\r
+#endif\r
+\r
+} Pin;\r
+\r
+//------------------------------------------------------------------------------\r
+//         Global Access Macros \r
+//------------------------------------------------------------------------------\r
+\r
+//Get Glitch input filter enable/disable status\r
+#define PIO_GetIFSR(pPin)      ((pPin)->pio->PIO_IFSR)\r
+\r
+//Get Glitch/Deboucing selection status\r
+#define PIO_GetIFDGSR(pPin) ((pPin)->pio->PIO_IFDGSR)\r
+\r
+//Get Additional PIO interrupt mode mask status\r
+#define PIO_GetAIMMR(pPin)  ((pPin)->pio->PIO_AIMMR)\r
+\r
+//Get Interrupt status\r
+#define PIO_GetISR(pPin)       ((pPin)->pio->PIO_ISR)\r
+\r
+//Get Edge or Level selection status\r
+#define PIO_GetELSR(pPin)      ((pPin)->pio->PIO_ELSR)\r
+\r
+//Get Fall/Rise or Low/High selection status\r
+#define PIO_GetFRLHSR(pPin)    ((pPin)->pio->PIO_FRLHSR)\r
+\r
+//Get PIO Lock Status\r
+#define PIO_GetLockStatus(pPin) ((pPin)->pio->PIO_LOCKSR)\r
+\r
+//------------------------------------------------------------------------------\r
+//         Global Functions\r
+//------------------------------------------------------------------------------\r
+\r
+extern unsigned char PIO_Configure(const Pin *list, unsigned int size);\r
+\r
+extern void PIO_Set(const Pin *pin);\r
+\r
+extern void PIO_Clear(const Pin *pin);\r
+\r
+extern unsigned char PIO_Get(const Pin *pin);\r
+\r
+//extern unsigned int PIO_GetISR(const Pin *pin);\r
+\r
+extern unsigned char PIO_GetOutputDataStatus(const Pin *pin);\r
+\r
+#endif //#ifndef PIO_H\r
+\r

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/pio/pio_it.c b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/pio/pio_it.c
new file mode 100644 (file)
index 0000000..cdd8a0b
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/pio/pio_it.c
@@ -0,0 +1,461 @@
+/* ----------------------------------------------------------------------------\r
+ *         ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/// Disable traces for this file\r
+#undef TRACE_LEVEL\r
+#define TRACE_LEVEL 0\r
+\r
+//------------------------------------------------------------------------------\r
+//         Headers\r
+//------------------------------------------------------------------------------\r
+\r
+#include "pio_it.h"\r
+#include "pio.h"\r
+#include <board.h>\r
+#include <irq/irq.h>\r
+#include <utility/assert.h>\r
+#include <utility/trace.h>\r
+\r
+//------------------------------------------------------------------------------\r
+//         Local definitions\r
+//------------------------------------------------------------------------------\r
+\r
+/// \exclude\r
+/// Maximum number of interrupt sources that can be defined. This\r
+/// constant can be increased, but the current value is the smallest possible\r
+/// that will be compatible with all existing projects.\r
+#define MAX_INTERRUPT_SOURCES       7\r
+\r
+//------------------------------------------------------------------------------\r
+//         Local types\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+/// \exclude\r
+/// Describes a PIO interrupt source, including the PIO instance triggering the\r
+/// interrupt and the associated interrupt handler.\r
+//------------------------------------------------------------------------------\r
+typedef struct {\r
+\r
+    /// Pointer to the source pin instance.\r
+    const Pin *pPin;\r
+\r
+    /// Interrupt handler.\r
+    void (*handler)(const Pin *);\r
+\r
+} InterruptSource;\r
+\r
+//------------------------------------------------------------------------------\r
+//         Local variables\r
+//------------------------------------------------------------------------------\r
+\r
+/// List of interrupt sources.\r
+static InterruptSource pSources[MAX_INTERRUPT_SOURCES];\r
+\r
+/// Number of currently defined interrupt sources.\r
+static unsigned int numSources;\r
+\r
+//------------------------------------------------------------------------------\r
+//         Local functions\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+/// Handles all interrupts on the given PIO controller.\r
+/// \param id  PIO controller ID.\r
+/// \param pPio  PIO controller base address.\r
+//------------------------------------------------------------------------------\r
+static void PioInterruptHandler(unsigned int id, AT91S_PIO *pPio)\r
+{\r
+    unsigned int status;\r
+    unsigned int i;\r
+\r
+    // Read PIO controller status\r
+    status = pPio->PIO_ISR;\r
+    status &= pPio->PIO_IMR;\r
+\r
+    // Check pending events\r
+    if (status != 0) {\r
+\r
+        TRACE_DEBUG("PIO interrupt on PIO controller #%d\n\r", id);\r
+\r
+        // Find triggering source\r
+        i = 0;\r
+        while (status != 0) {\r
+\r
+            // There cannot be an unconfigured source enabled.\r
+            SANITY_CHECK(i < numSources);\r
+\r
+            // Source is configured on the same controller\r
+            if (pSources[i].pPin->id == id) {\r
+\r
+                // Source has PIOs whose statuses have changed\r
+                if ((status & pSources[i].pPin->mask) != 0) {\r
+\r
+                    TRACE_DEBUG("Interrupt source #%d triggered\n\r", i);\r
+\r
+                    pSources[i].handler(pSources[i].pPin);\r
+                    status &= ~(pSources[i].pPin->mask);\r
+                }\r
+            }\r
+            i++;\r
+        }\r
+    }\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Generic PIO interrupt handler. Single entry point for interrupts coming\r
+/// from any PIO controller (PIO A, B, C ...). Dispatches the interrupt to\r
+/// the user-configured handlers.\r
+//------------------------------------------------------------------------------\r
+void PIO_IT_InterruptHandler(void)\r
+{\r
+#if defined(AT91C_ID_PIOA)\r
+    // Treat PIOA interrupts\r
+    PioInterruptHandler(AT91C_ID_PIOA, AT91C_BASE_PIOA);\r
+#endif\r
+\r
+#if defined(AT91C_ID_PIOB)\r
+    // Treat PIOB interrupts\r
+    PioInterruptHandler(AT91C_ID_PIOB, AT91C_BASE_PIOB);\r
+#endif\r
+\r
+#if defined(AT91C_ID_PIOC)\r
+    // Treat PIOC interrupts\r
+    PioInterruptHandler(AT91C_ID_PIOC, AT91C_BASE_PIOC);\r
+#endif\r
+\r
+#if defined(AT91C_ID_PIOD)\r
+    // Treat PIOD interrupts\r
+    PioInterruptHandler(AT91C_ID_PIOD, AT91C_BASE_PIOD);\r
+#endif\r
+\r
+#if defined(AT91C_ID_PIOE)\r
+    // Treat PIOE interrupts\r
+    PioInterruptHandler(AT91C_ID_PIOE, AT91C_BASE_PIOE);\r
+#endif\r
+\r
+#if defined(AT91C_ID_PIOABCD)\r
+    // Treat PIOABCD interrupts\r
+    #if !defined(AT91C_ID_PIOA)\r
+        PioInterruptHandler(AT91C_ID_PIOABCD, AT91C_BASE_PIOA);\r
+    #endif\r
+    #if !defined(AT91C_ID_PIOB)\r
+        PioInterruptHandler(AT91C_ID_PIOABCD, AT91C_BASE_PIOB);\r
+    #endif\r
+    #if !defined(AT91C_ID_PIOC)\r
+        PioInterruptHandler(AT91C_ID_PIOABCD, AT91C_BASE_PIOC);\r
+    #endif\r
+    #if !defined(AT91C_ID_PIOD)\r
+        PioInterruptHandler(AT91C_ID_PIOABCD, AT91C_BASE_PIOD);\r
+    #endif\r
+#endif\r
+\r
+#if defined(AT91C_ID_PIOABCDE)\r
+    // Treat PIOABCDE interrupts\r
+    #if !defined(AT91C_ID_PIOA)\r
+        PioInterruptHandler(AT91C_ID_PIOABCDE, AT91C_BASE_PIOA);\r
+    #endif\r
+    #if !defined(AT91C_ID_PIOB)\r
+        PioInterruptHandler(AT91C_ID_PIOABCDE, AT91C_BASE_PIOB);\r
+    #endif\r
+    #if !defined(AT91C_ID_PIOC)\r
+        PioInterruptHandler(AT91C_ID_PIOABCDE, AT91C_BASE_PIOC);\r
+    #endif\r
+    #if !defined(AT91C_ID_PIOD)\r
+        PioInterruptHandler(AT91C_ID_PIOABCDE, AT91C_BASE_PIOD);\r
+    #endif\r
+    #if !defined(AT91C_ID_PIOE)\r
+        PioInterruptHandler(AT91C_ID_PIOABCDE, AT91C_BASE_PIOE);\r
+    #endif\r
+#endif\r
+\r
+#if defined(AT91C_ID_PIOCDE)\r
+    // Treat PIOCDE interrupts\r
+    #if !defined(AT91C_ID_PIOC)\r
+        PioInterruptHandler(AT91C_ID_PIOCDE, AT91C_BASE_PIOC);\r
+    #endif\r
+    #if !defined(AT91C_ID_PIOD)\r
+        PioInterruptHandler(AT91C_ID_PIOCDE, AT91C_BASE_PIOD);\r
+    #endif\r
+    #if !defined(AT91C_ID_PIOE)\r
+        PioInterruptHandler(AT91C_ID_PIOCDE, AT91C_BASE_PIOE);\r
+    #endif\r
+#endif\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+//         Global functions\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+/// Initializes the PIO interrupt management logic. The desired priority of PIO\r
+/// interrupts must be provided. Calling this function multiple times result in\r
+/// the reset of currently configured interrupts.\r
+/// \param priority  PIO controller interrupts priority.\r
+//------------------------------------------------------------------------------\r
+void PIO_InitializeInterrupts(unsigned int priority)\r
+{\r
+    TRACE_DEBUG("PIO_Initialize()\n\r");\r
+\r
+//    SANITY_CHECK((priority & ~AT91C_AIC_PRIOR) == 0);\r
+\r
+    // Reset sources\r
+    numSources = 0;\r
+\r
+#ifdef AT91C_ID_PIOA\r
+    // Configure PIO interrupt sources\r
+    TRACE_DEBUG("PIO_Initialize: Configuring PIOA\n\r");\r
+    AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_PIOA;\r
+    AT91C_BASE_PIOA->PIO_ISR;\r
+    AT91C_BASE_PIOA->PIO_IDR = 0xFFFFFFFF;\r
+    IRQ_ConfigureIT(AT91C_ID_PIOA, priority, PIO_IT_InterruptHandler);\r
+    IRQ_EnableIT(AT91C_ID_PIOA);\r
+#endif\r
+\r
+#ifdef AT91C_ID_PIOB\r
+    TRACE_DEBUG("PIO_Initialize: Configuring PIOB\n\r");\r
+    AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_PIOB;\r
+    AT91C_BASE_PIOB->PIO_ISR;\r
+    AT91C_BASE_PIOB->PIO_IDR = 0xFFFFFFFF;\r
+    IRQ_ConfigureIT(AT91C_ID_PIOB, priority, PIO_IT_InterruptHandler);\r
+    IRQ_EnableIT(AT91C_ID_PIOB);\r
+#endif\r
+\r
+#ifdef AT91C_ID_PIOC\r
+    TRACE_DEBUG("PIO_Initialize: Configuring PIOC\n\r");\r
+    AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_PIOC;\r
+    AT91C_BASE_PIOC->PIO_ISR;\r
+    AT91C_BASE_PIOC->PIO_IDR = 0xFFFFFFFF;\r
+    IRQ_ConfigureIT(AT91C_ID_PIOC, priority, PIO_IT_InterruptHandler);\r
+    IRQ_EnableIT(AT91C_ID_PIOC);\r
+#endif\r
+\r
+#ifdef AT91C_ID_PIOD\r
+    TRACE_DEBUG("PIO_Initialize: Configuring PIOD\n\r");\r
+    AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_PIOD;\r
+    AT91C_BASE_PIOC->PIO_ISR;\r
+    AT91C_BASE_PIOC->PIO_IDR = 0xFFFFFFFF;\r
+    IRQ_ConfigureIT(AT91C_ID_PIOD, priority, PIO_IT_InterruptHandler);\r
+    IRQ_EnableIT(AT91C_ID_PIOD);\r
+#endif\r
+\r
+#ifdef AT91C_ID_PIOE\r
+    TRACE_DEBUG("PIO_Initialize: Configuring PIOE\n\r");\r
+    AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_PIOE;\r
+    AT91C_BASE_PIOC->PIO_ISR;\r
+    AT91C_BASE_PIOC->PIO_IDR = 0xFFFFFFFF;\r
+    IRQ_ConfigureIT(AT91C_ID_PIOE, priority, PIO_IT_InterruptHandler);\r
+    IRQ_EnableIT(AT91C_ID_PIOE);\r
+#endif\r
+\r
+#if defined(AT91C_ID_PIOABCD)\r
+    // Treat PIOABCD interrupts\r
+    #if !defined(AT91C_ID_PIOA) \\r
+     && !defined(AT91C_ID_PIOB) \\r
+     && !defined(AT91C_ID_PIOC) \\r
+     && !defined(AT91C_ID_PIOD)\r
+\r
+        TRACE_DEBUG("PIO_Initialize: Configuring PIOABCD\n\r");\r
+        AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_PIOABCD;\r
+        AT91C_BASE_PIOA->PIO_ISR;\r
+        AT91C_BASE_PIOA->PIO_IDR = 0xFFFFFFFF;\r
+        IRQ_ConfigureIT(AT91C_ID_PIOABCD, priority, PIO_IT_InterruptHandler);\r
+        IRQ_EnableIT(AT91C_ID_PIOABCD);\r
+    #endif\r
+#endif\r
+\r
+#if defined(AT91C_ID_PIOABCDE)\r
+    // Treat PIOABCDE interrupts\r
+    #if !defined(AT91C_ID_PIOA) \\r
+     && !defined(AT91C_ID_PIOB) \\r
+     && !defined(AT91C_ID_PIOC) \\r
+     && !defined(AT91C_ID_PIOD) \\r
+     && !defined(AT91C_ID_PIOE)\r
+\r
+        TRACE_DEBUG("PIO_Initialize: Configuring PIOABCDE\n\r");\r
+        AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_PIOABCDE;\r
+        AT91C_BASE_PIOA->PIO_ISR;\r
+        AT91C_BASE_PIOA->PIO_IDR = 0xFFFFFFFF;\r
+        IRQ_ConfigureIT(AT91C_ID_PIOABCDE, priority, PIO_IT_InterruptHandler);\r
+        IRQ_EnableIT(AT91C_ID_PIOABCDE);\r
+    #endif\r
+#endif\r
+\r
+#if defined(AT91C_ID_PIOCDE)\r
+    // Treat PIOCDE interrupts\r
+    #if !defined(AT91C_ID_PIOC) \\r
+     && !defined(AT91C_ID_PIOD) \\r
+     && !defined(AT91C_ID_PIOE)\r
+\r
+        TRACE_DEBUG("PIO_Initialize: Configuring PIOC\n\r");\r
+        AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_PIOCDE;\r
+        AT91C_BASE_PIOC->PIO_ISR;\r
+        AT91C_BASE_PIOC->PIO_IDR = 0xFFFFFFFF;\r
+        IRQ_ConfigureIT(AT91C_ID_PIOCDE, priority, PIO_IT_InterruptHandler);\r
+        IRQ_EnableIT(AT91C_ID_PIOCDE);\r
+    #endif\r
+#endif\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Configures a PIO or a group of PIO to generate an interrupt on status\r
+/// change. The provided interrupt handler will be called with the triggering\r
+/// pin as its parameter (enabling different pin instances to share the same\r
+/// handler).\r
+/// \param pPin  Pointer to a Pin instance.\r
+/// \param handler  Interrupt handler function pointer.\r
+//------------------------------------------------------------------------------\r
+void PIO_ConfigureIt(const Pin *pPin, void (*handler)(const Pin *))\r
+{\r
+    InterruptSource *pSource;\r
+\r
+    TRACE_DEBUG("PIO_ConfigureIt()\n\r");\r
+\r
+    SANITY_CHECK(pPin);\r
+    ASSERT(numSources < MAX_INTERRUPT_SOURCES,\r
+           "-F- PIO_ConfigureIt: Increase MAX_INTERRUPT_SOURCES\n\r");\r
+\r
+    // Define new source\r
+    TRACE_DEBUG("PIO_ConfigureIt: Defining new source #%d.\n\r",  numSources);\r
+\r
+    pSource = &(pSources[numSources]);\r
+    pSource->pPin = pPin;\r
+    pSource->handler = handler;\r
+    numSources++;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Enables the given interrupt source if it has been configured. The status\r
+/// register of the corresponding PIO controller is cleared prior to enabling\r
+/// the interrupt.\r
+/// \param pPin  Interrupt source to enable.\r
+//------------------------------------------------------------------------------\r
+void PIO_EnableIt(const Pin *pPin)\r
+{\r
+    TRACE_DEBUG("PIO_EnableIt()\n\r");\r
+\r
+    SANITY_CHECK(pPin);\r
+\r
+#ifndef NOASSERT\r
+    unsigned int i = 0;\r
+    unsigned char found = 0;\r
+    while ((i < numSources) && !found) {\r
+\r
+        if (pSources[i].pPin == pPin) {\r
+\r
+            found = 1;\r
+        }\r
+        i++;\r
+    }\r
+    ASSERT(found, "-F- PIO_EnableIt: Interrupt source has not been configured\n\r");\r
+#endif\r
+\r
+    pPin->pio->PIO_ISR;\r
+    pPin->pio->PIO_IER = pPin->mask;\r
+    \r
+\r
+#if defined(AT91C_PIOA_AIMMR)\r
+    //PIO3 with additional interrupt support\r
+    //configure additional interrupt mode registers\r
+    if(pPin->mask&pPin->itMode.itMask) {\r
+   \r
+    //enable additional interrupt mode\r
+    pPin->pio->PIO_AIMER  = pPin->itMode.itMask;\r
+    \r
+    if(pPin->mask&pPin->itMode.edgeLvlSel)\r
+        //if bit field of selected pin is 1, set as Level detection source\r
+        pPin->pio->PIO_LSR = pPin->itMode.edgeLvlSel;\r
+    else\r
+        //if bit field of selected pin is 0, set as Edge detection source\r
+        pPin->pio->PIO_ESR = ~(pPin->itMode.edgeLvlSel);\r
+\r
+    if(pPin->mask&pPin->itMode.lowFallOrRiseHighSel)\r
+        //if bit field of selected pin is 1, set as Rising Edge/High level detection event\r
+        pPin->pio->PIO_REHLSR     = pPin->itMode.lowFallOrRiseHighSel;\r
+    else\r
+        //if bit field of selected pin is 0, set as Falling Edge/Low level detection event\r
+        pPin->pio->PIO_FELLSR     = ~(pPin->itMode.lowFallOrRiseHighSel);\r
+    }\r
+\r
+#endif\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Disables a given interrupt source, with no added side effects.\r
+/// \param pPin  Interrupt source to disable.\r
+//------------------------------------------------------------------------------\r
+void PIO_DisableIt(const Pin *pPin)\r
+{\r
+    SANITY_CHECK(pPin);\r
+\r
+    TRACE_DEBUG("PIO_DisableIt()\n\r");\r
+\r
+    pPin->pio->PIO_IDR = pPin->mask;\r
+#if defined(AT91C_PIOA_AIMMR)\r
+    if(pPin->mask & pPin->itMode.itMask)\r
+        //disable additional interrupt mode\r
+        pPin->pio->PIO_AIMDR = pPin->mask & pPin->itMode.itMask;\r
+#endif\r
+\r
+}\r
+\r
+#if defined(cortexm3)\r
+//------------------------------------------------------------------------------\r
+/// Override cortex-m3's default PIOA irq handler\r
+//------------------------------------------------------------------------------\r
+void PIOA_IrqHandler(void)\r
+{\r
+    #if defined(AT91C_ID_PIOA)\r
+    // Treat PIOA interrupts\r
+    PioInterruptHandler(AT91C_ID_PIOA, AT91C_BASE_PIOA);\r
+    #endif\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Override cortex-m3's default PIOB irq handler\r
+//------------------------------------------------------------------------------\r
+void PIOB_IrqHandler(void)\r
+{\r
+    #if defined(AT91C_ID_PIOB)\r
+    // Treat PIOA interrupts\r
+    PioInterruptHandler(AT91C_ID_PIOB, AT91C_BASE_PIOB);\r
+    #endif\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Override cortex-m3's default PIOC irq handler\r
+//------------------------------------------------------------------------------\r
+void PIOC_IrqHandler(void)\r
+{\r
+    #if defined(AT91C_ID_PIOC)\r
+    // Treat PIOA interrupts\r
+    PioInterruptHandler(AT91C_ID_PIOC, AT91C_BASE_PIOC);\r
+    #endif\r
+}\r
+#endif\r

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/pio/pio_it.h b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/pio/pio_it.h
new file mode 100644 (file)
index 0000000..782e911
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/pio/pio_it.h
@@ -0,0 +1,85 @@
+/* ----------------------------------------------------------------------------\r
+ *         ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+//------------------------------------------------------------------------------\r
+/// \unit\r
+///\r
+/// !!!Purpose\r
+/// \r
+/// Configuration and handling of interrupts on PIO status changes. The API\r
+/// provided here have several advantages over the traditional PIO interrupt\r
+/// configuration approach:\r
+///    - It is highly portable\r
+///    - It automatically demultiplexes interrupts when multiples pins have been\r
+///      configured on a single PIO controller\r
+///    - It allows a group of pins to share the same interrupt\r
+/// \r
+/// However, it also has several minor drawbacks that may prevent from using it\r
+/// in particular applications:\r
+///    - It enables the clocks of all PIO controllers\r
+///    - PIO controllers all share the same interrupt handler, which does the\r
+///      demultiplexing and can be slower than direct configuration\r
+///    - It reserves space for a fixed number of interrupts, which can be\r
+///      increased by modifying the appropriate constant in pio_it.c.\r
+///\r
+/// !!!Usage\r
+/// \r
+/// -# Initialize the PIO interrupt mechanism using PIO_InitializeInterrupts()\r
+///    with the desired priority (0 ... 7).\r
+/// -# Configure a status change interrupt on one or more pin(s) with\r
+///    PIO_ConfigureIt().\r
+/// -# Enable & disable interrupts on pins using PIO_EnableIt() and\r
+///    PIO_DisableIt().\r
+//------------------------------------------------------------------------------\r
+\r
+#ifndef PIO_IT_H\r
+#define PIO_IT_H\r
+\r
+//------------------------------------------------------------------------------\r
+//         Headers\r
+//------------------------------------------------------------------------------\r
+\r
+#include "pio.h"\r
+\r
+//------------------------------------------------------------------------------\r
+//         Global functions\r
+//------------------------------------------------------------------------------\r
+\r
+extern void PIO_InitializeInterrupts(unsigned int priority);\r
+\r
+extern void PIO_ConfigureIt(const Pin *pPin, void (*handler)(const Pin *));\r
+\r
+extern void PIO_EnableIt(const Pin *pPin);\r
+\r
+extern void PIO_DisableIt(const Pin *pPin);\r
+\r
+extern void PIO_IT_InterruptHandler(void);\r
+\r
+#endif //#ifndef PIO_IT_H\r
+\r

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/pit/pit.c b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/pit/pit.c
new file mode 100644 (file)
index 0000000..f15610c
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/pit/pit.c
@@ -0,0 +1,122 @@
+/* ----------------------------------------------------------------------------\r
+ *         ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+//------------------------------------------------------------------------------\r
+//         Headers\r
+//------------------------------------------------------------------------------\r
+\r
+#include "pit.h"\r
+#include <board.h>\r
+\r
+//------------------------------------------------------------------------------\r
+//         Global functions\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+/// Initialize the Periodic Interval Timer to generate a tick at the specified\r
+/// period, given the current master clock frequency.\r
+/// \param period  Period in µsecond.\r
+/// \param pit_frequency  Master clock frequency in MHz.\r
+//------------------------------------------------------------------------------\r
+void PIT_Init(unsigned int period, unsigned int pit_frequency)\r
+{\r
+    AT91C_BASE_PITC->PITC_PIMR = period? (period * pit_frequency + 8) >> 4 : 0;\r
+    AT91C_BASE_PITC->PITC_PIMR |= AT91C_PITC_PITEN;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Set the Periodic Interval Value of the PIT.\r
+/// \param piv  PIV value to set.\r
+//------------------------------------------------------------------------------\r
+void PIT_SetPIV(unsigned int piv)\r
+{\r
+    AT91C_BASE_PITC->PITC_PIMR = (AT91C_BASE_PITC->PITC_PIMR & AT91C_PITC_PIV)\r
+                                 | piv;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Enables the PIT if this is not already the case.\r
+//------------------------------------------------------------------------------\r
+void PIT_Enable(void)\r
+{\r
+    AT91C_BASE_PITC->PITC_PIMR |= AT91C_PITC_PITEN;\r
+}\r
+\r
+//----------------------------------------------------------------------------\r
+/// Enable the PIT periodic interrupt.\r
+//----------------------------------------------------------------------------\r
+void PIT_EnableIT(void)\r
+{\r
+    AT91C_BASE_PITC->PITC_PIMR |= AT91C_PITC_PITIEN;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Disables the PIT periodic interrupt.\r
+//------------------------------------------------------------------------------\r
+void PIT_DisableIT(void)\r
+{\r
+    AT91C_BASE_PITC->PITC_PIMR &= ~AT91C_PITC_PITIEN;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Returns the value of the PIT mode register.\r
+/// \return PIT_MR value.\r
+//------------------------------------------------------------------------------\r
+unsigned int PIT_GetMode(void)\r
+{\r
+    return AT91C_BASE_PITC->PITC_PIMR;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Returns the value of the PIT status register, clearing it as a side effect.\r
+/// \return PIT_SR value.\r
+//------------------------------------------------------------------------------\r
+unsigned int PIT_GetStatus(void)\r
+{\r
+    return AT91C_BASE_PITC->PITC_PISR;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Returns the value of the PIT Image Register, to read PICNT and CPIV without\r
+/// clearing the current values.\r
+/// \return PIT_PIIR value.\r
+//------------------------------------------------------------------------------\r
+unsigned int PIT_GetPIIR(void)\r
+{\r
+    return AT91C_BASE_PITC->PITC_PIIR;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Returns the value of the PIT Value Register, clearing it as a side effect.\r
+/// \return PIT_PIVR value.\r
+//------------------------------------------------------------------------------\r
+unsigned int PIT_GetPIVR(void)\r
+{\r
+    return AT91C_BASE_PITC->PITC_PIVR;\r
+}\r

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/pit/pit.h b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/pit/pit.h
new file mode 100644 (file)
index 0000000..12aad31
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/pit/pit.h
@@ -0,0 +1,77 @@
+/* ----------------------------------------------------------------------------\r
+ *         ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+//------------------------------------------------------------------------------\r
+/// \unit\r
+///\r
+/// !Purpose\r
+///\r
+/// Interface for configuration the Periodic Interval Timer (PIT) peripheral.\r
+///\r
+/// !Usage\r
+///\r
+/// -# Initialize the PIT with the desired period using PIT_Init().\r
+///    Alternatively, the Periodic Interval Value (PIV) can be configured\r
+///    manually using PIT_SetPIV().\r
+/// -# Start the PIT counting using PIT_Enable().\r
+/// -# Enable & disable the PIT interrupt using PIT_EnableIT() and\r
+///    PIT_DisableIT().\r
+/// -# Retrieve the current status of the PIT using PIT_GetStatus().\r
+/// -# To get the current value of the internal counter and the number of ticks\r
+///    that have occurred, use either PIT_GetPIVR() or PIT_GetPIIR() depending\r
+///    on whether you want the values to be cleared or not.\r
+//------------------------------------------------------------------------------\r
+\r
+#ifndef PIT_H\r
+#define PIT_H\r
+\r
+//------------------------------------------------------------------------------\r
+//         Global Functions\r
+//------------------------------------------------------------------------------\r
+\r
+extern void PIT_Init(unsigned int period, unsigned int pit_frequency);\r
+\r
+extern void PIT_SetPIV(unsigned int piv);\r
+\r
+extern void PIT_Enable(void);\r
+\r
+extern void PIT_EnableIT(void);\r
+\r
+extern void PIT_DisableIT(void);\r
+\r
+extern unsigned int PIT_GetMode(void);\r
+\r
+extern unsigned int PIT_GetStatus(void);\r
+\r
+extern unsigned int PIT_GetPIIR(void);\r
+\r
+extern unsigned int PIT_GetPIVR(void);\r
+\r
+#endif //#ifndef PIT_H\r
+\r

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/pmc/pmc.c b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/pmc/pmc.c
new file mode 100644 (file)
index 0000000..d464d51
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/pmc/pmc.c
@@ -0,0 +1,188 @@
+/* ----------------------------------------------------------------------------\r
+ *         ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+//------------------------------------------------------------------------------\r
+//         Headers\r
+//------------------------------------------------------------------------------\r
+\r
+#include "pmc.h"\r
+#include <board.h>\r
+#include <utility/assert.h>\r
+#include <utility/trace.h>\r
+\r
+#ifdef CP15_PRESENT\r
+#include <cp15/cp15.h>\r
+#endif\r
+\r
+#define MASK_STATUS 0x3FFFFFFC\r
+\r
+//------------------------------------------------------------------------------\r
+//         Global functions\r
+//------------------------------------------------------------------------------\r
+\r
+#if defined(at91sam7l64) || defined(at91sam7l128)\r
+//------------------------------------------------------------------------------\r
+/// Sets the fast wake-up inputs that can get the device out of Wait mode.\r
+/// \param inputs  Fast wake-up inputs to enable.\r
+//------------------------------------------------------------------------------\r
+void PMC_SetFastWakeUpInputs(unsigned int inputs)\r
+{\r
+    SANITY_CHECK((inputs & ~0xFF) == 0);\r
+    AT91C_BASE_PMC->PMC_FSMR = inputs;\r
+}\r
+\r
+#if !defined(__ICCARM__)\r
+__attribute__ ((section (".ramfunc"))) // GCC\r
+#endif\r
+//------------------------------------------------------------------------------\r
+/// Disables the main oscillator, making the device enter Wait mode.\r
+//------------------------------------------------------------------------------\r
+void PMC_DisableMainOscillatorForWaitMode(void)\r
+{\r
+    AT91C_BASE_PMC->PMC_MOR = 0x37 << 16;\r
+    while ((AT91C_BASE_PMC->PMC_MOR & AT91C_PMC_MAINSELS) != AT91C_PMC_MAINSELS);\r
+}\r
+\r
+#endif\r
+\r
+#if defined(at91sam7l)\r
+//------------------------------------------------------------------------------\r
+/// Disables the main oscillator when NOT running on it.\r
+//------------------------------------------------------------------------------\r
+void PMC_DisableMainOscillator(void)\r
+{\r
+    AT91C_BASE_PMC->PMC_MOR = 0x37 << 16;\r
+    while ((AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MAINSELS) == AT91C_PMC_MAINSELS);\r
+}\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+/// Disables the processor clock\r
+//------------------------------------------------------------------------------\r
+void PMC_DisableProcessorClock(void)\r
+{    \r
+    AT91C_BASE_PMC->PMC_SCDR = AT91C_PMC_PCK;   \r
+    while ((AT91C_BASE_PMC->PMC_SCSR & AT91C_PMC_PCK) != AT91C_PMC_PCK); \r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Enables the clock of a peripheral. The peripheral ID (AT91C_ID_xxx) is used\r
+/// to identify which peripheral is targetted.\r
+/// Note that the ID must NOT be shifted (i.e. 1 << AT91C_ID_xxx).\r
+/// \param id  Peripheral ID (AT91C_ID_xxx).\r
+//------------------------------------------------------------------------------\r
+void PMC_EnablePeripheral(unsigned int id)\r
+{\r
+    SANITY_CHECK(id < 32);\r
+\r
+    if ((AT91C_BASE_PMC->PMC_PCSR & (1 << id)) == (1 << id)) {\r
+\r
+        TRACE_INFO("PMC_EnablePeripheral: clock of peripheral"\r
+                   " %u is already enabled\n\r",\r
+                   id);\r
+    }\r
+    else {\r
+\r
+        AT91C_BASE_PMC->PMC_PCER = 1 << id;\r
+    }\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Disables the clock of a peripheral. The peripheral ID (AT91C_ID_xxx) is used\r
+/// to identify which peripheral is targetted.\r
+/// Note that the ID must NOT be shifted (i.e. 1 << AT91C_ID_xxx).\r
+/// \param id  Peripheral ID (AT91C_ID_xxx).\r
+//------------------------------------------------------------------------------\r
+void PMC_DisablePeripheral(unsigned int id)\r
+{\r
+    SANITY_CHECK(id < 32);\r
+\r
+    if ((AT91C_BASE_PMC->PMC_PCSR & (1 << id)) != (1 << id)) {\r
+\r
+        TRACE_INFO("PMC_DisablePeripheral: clock of peripheral"\r
+                   " %u is not enabled\n\r",\r
+                   id);\r
+    }\r
+    else {\r
+\r
+        AT91C_BASE_PMC->PMC_PCDR = 1 << id;\r
+    }\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Enable all the periph clock via PMC\r
+/// (Becareful of the last 2 bits, it is not periph clock)\r
+//------------------------------------------------------------------------------\r
+void PMC_EnableAllPeripherals(void)\r
+{\r
+    AT91C_BASE_PMC->PMC_PCER = MASK_STATUS;\r
+    while( (AT91C_BASE_PMC->PMC_PCSR & MASK_STATUS) != MASK_STATUS);\r
+    TRACE_INFO("Enable all periph clocks\n\r"); \r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Disable all the periph clock via PMC\r
+/// (Becareful of the last 2 bits, it is not periph clock)\r
+//------------------------------------------------------------------------------\r
+void PMC_DisableAllPeripherals(void)\r
+{\r
+    AT91C_BASE_PMC->PMC_PCDR = MASK_STATUS;\r
+    while((AT91C_BASE_PMC->PMC_PCSR & MASK_STATUS) != 0);\r
+    TRACE_INFO("Disable all periph clocks\n\r");\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Get Periph Status\r
+//-----------------------------------------------------------------------------\r
+unsigned int PMC_IsAllPeriphEnabled(void)\r
+{\r
+    return (AT91C_BASE_PMC->PMC_PCSR == MASK_STATUS);\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Get Periph Status\r
+//-----------------------------------------------------------------------------\r
+unsigned int PMC_IsPeriphEnabled(unsigned int id)\r
+{\r
+    return (AT91C_BASE_PMC->PMC_PCSR & (1 << id));  \r
+}\r
+//------------------------------------------------------------------------------\r
+/// Put the CPU in Idle Mode for lower consumption\r
+//------------------------------------------------------------------------------\r
+void PMC_CPUInIdleMode(void)\r
+{\r
+#ifndef CP15_PRESENT   \r
+    PMC_DisableProcessorClock();\r
+#else\r
+    AT91C_BASE_PMC->PMC_SCDR = AT91C_PMC_PCK; \r
+    CP15_WaitForInterrupt();\r
+#endif\r
+}\r
+\r
+\r

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/pmc/pmc.h b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/pmc/pmc.h
new file mode 100644 (file)
index 0000000..a53b365
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/pmc/pmc.h
@@ -0,0 +1,62 @@
+/* ----------------------------------------------------------------------------\r
+ *         ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+#ifndef PMC_H\r
+#define PMC_H\r
+\r
+//------------------------------------------------------------------------------\r
+//         Global functions\r
+//------------------------------------------------------------------------------\r
+\r
+#if defined(at91sam7l64) || defined(at91sam7l128)\r
+extern void PMC_SetFastWakeUpInputs(unsigned int inputs);\r
+extern void PMC_DisableMainOscillator(void);\r
+extern\r
+#ifdef __ICCARM__\r
+__ramfunc\r
+#endif //__ICCARM__\r
+void PMC_DisableMainOscillatorForWaitMode(void);\r
+#endif // at91sam7l64 at91sam7l128\r
+\r
+extern void PMC_DisableProcessorClock(void);\r
+extern void PMC_EnablePeripheral(unsigned int id);\r
+extern void PMC_DisablePeripheral(unsigned int id);\r
+extern void PMC_CPUInIdleMode(void);\r
+\r
+\r
+extern void PMC_EnableAllPeripherals(void);\r
+\r
+extern void PMC_DisableAllPeripherals(void);\r
+\r
+extern unsigned int PMC_IsAllPeriphEnabled(void);\r
+\r
+extern unsigned int PMC_IsPeriphEnabled(unsigned int id);\r
+\r
+#endif //#ifndef PMC_H\r
+\r

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/pwmc/pwmc.c b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/pwmc/pwmc.c
new file mode 100644 (file)
index 0000000..98ca5cf
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/pwmc/pwmc.c
@@ -0,0 +1,245 @@
+/* ----------------------------------------------------------------------------\r
+ *         ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+//------------------------------------------------------------------------------\r
+//         Headers\r
+//------------------------------------------------------------------------------\r
+\r
+#include "pwmc.h"\r
+#include <board.h>\r
+#include <utility/assert.h>\r
+#include <utility/trace.h>\r
+\r
+//------------------------------------------------------------------------------\r
+//         Local functions\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+/// Finds a prescaler/divisor couple to generate the desired frequency from\r
+/// MCK.\r
+/// Returns the value to enter in PWMC_MR or 0 if the configuration cannot be\r
+/// met.\r
+/// \param frequency  Desired frequency in Hz.\r
+/// \param mck  Master clock frequency in Hz.\r
+//------------------------------------------------------------------------------\r
+static unsigned short FindClockConfiguration(\r
+    unsigned int frequency,\r
+    unsigned int mck)\r
+{\r
+    unsigned int divisors[11] = {1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024};\r
+    unsigned char divisor = 0;\r
+    unsigned int prescaler;\r
+\r
+    SANITY_CHECK(frequency < mck);\r
+\r
+    // Find prescaler and divisor values\r
+    prescaler = (mck / divisors[divisor]) / frequency;\r
+    while ((prescaler > 255) && (divisor < 11)) {\r
+\r
+        divisor++;\r
+        prescaler = (mck / divisors[divisor]) / frequency;\r
+    }\r
+\r
+    // Return result\r
+    if (divisor < 11) {\r
+\r
+        TRACE_DEBUG("Found divisor=%u and prescaler=%u for freq=%uHz\n\r",\r
+                  divisors[divisor], prescaler, frequency);\r
+        return prescaler | (divisor << 8);\r
+    }\r
+    else {\r
+\r
+        return 0;\r
+    }\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+//         Global functions\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+/// Configures PWM a channel with the given parameters.\r
+/// The PWM controller must have been clocked in the PMC prior to calling this\r
+/// function. \r
+/// Beware: this function disables the channel. It waits until disable is effective.\r
+/// \param channel  Channel number.\r
+/// \param prescaler  Channel prescaler.\r
+/// \param alignment  Channel alignment.\r
+/// \param polarity  Channel polarity.\r
+//------------------------------------------------------------------------------\r
+void PWMC_ConfigureChannel(\r
+    unsigned char channel,\r
+    unsigned int prescaler,\r
+    unsigned int alignment,\r
+    unsigned int polarity)\r
+{\r
+    SANITY_CHECK(prescaler < AT91C_PWMC_CPRE_MCKB);\r
+    SANITY_CHECK((alignment & ~AT91C_PWMC_CALG) == 0);\r
+    SANITY_CHECK((polarity & ~AT91C_PWMC_CPOL) == 0);\r
+\r
+    // Disable channel (effective at the end of the current period)\r
+    if ((AT91C_BASE_PWMC->PWMC_SR & (1 << channel)) != 0) {\r
+        AT91C_BASE_PWMC->PWMC_DIS = 1 << channel;\r
+        while ((AT91C_BASE_PWMC->PWMC_SR & (1 << channel)) != 0);\r
+    }\r
+\r
+    // Configure channel\r
+    AT91C_BASE_PWMC->PWMC_CH[channel].PWMC_CMR = prescaler | alignment | polarity;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Configures PWM clocks A & B to run at the given frequencies. This function\r
+/// finds the best MCK divisor and prescaler values automatically.\r
+/// \param clka  Desired clock A frequency (0 if not used).\r
+/// \param clkb  Desired clock B frequency (0 if not used).\r
+/// \param mck  Master clock frequency.\r
+//------------------------------------------------------------------------------\r
+void PWMC_ConfigureClocks(unsigned int clka, unsigned int clkb, unsigned int mck)\r
+{\r
+    unsigned int mode = 0;\r
+    unsigned int result;\r
+\r
+    // Clock A\r
+    if (clka != 0) {\r
+\r
+        result = FindClockConfiguration(clka, mck);\r
+        ASSERT(result != 0, "-F- Could not generate the desired PWM frequency (%uHz)\n\r", clka);\r
+        mode |= result;\r
+    }\r
+\r
+    // Clock B\r
+    if (clkb != 0) {\r
+\r
+        result = FindClockConfiguration(clkb, mck);\r
+        ASSERT(result != 0, "-F- Could not generate the desired PWM frequency (%uHz)\n\r", clkb);\r
+        mode |= (result << 16);\r
+    }\r
+\r
+    // Configure clocks\r
+    TRACE_DEBUG("Setting PWMC_MR = 0x%08X\n\r", mode);\r
+    AT91C_BASE_PWMC->PWMC_MR = mode;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Sets the period value used by a PWM channel. This function writes directly\r
+/// to the CPRD register if the channel is disabled; otherwise, it uses the\r
+/// update register CUPD.\r
+/// \param channel  Channel number.\r
+/// \param period  Period value.\r
+//------------------------------------------------------------------------------\r
+void PWMC_SetPeriod(unsigned char channel, unsigned short period)\r
+{\r
+    // If channel is disabled, write to CPRD\r
+    if ((AT91C_BASE_PWMC->PWMC_SR & (1 << channel)) == 0) {\r
+\r
+        AT91C_BASE_PWMC->PWMC_CH[channel].PWMC_CPRDR = period;\r
+    }\r
+    // Otherwise use update register\r
+    else {\r
+\r
+        AT91C_BASE_PWMC->PWMC_CH[channel].PWMC_CMR |= AT91C_PWMC_CPD;\r
+        AT91C_BASE_PWMC->PWMC_CH[channel].PWMC_CUPDR = period;\r
+    }\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Sets the duty cycle used by a PWM channel. This function writes directly to\r
+/// the CDTY register if the channel is disabled; otherwise it uses the\r
+/// update register CUPD.\r
+/// Note that the duty cycle must always be inferior or equal to the channel\r
+/// period.\r
+/// \param channel  Channel number.\r
+/// \param duty  Duty cycle value.\r
+//------------------------------------------------------------------------------\r
+void PWMC_SetDutyCycle(unsigned char channel, unsigned short duty)\r
+{\r
+    SANITY_CHECK(duty <= AT91C_BASE_PWMC->PWMC_CH[channel].PWMC_CPRDR);\r
+\r
+    // SAM7S errata\r
+#if defined(at91sam7s16) || defined(at91sam7s161) || defined(at91sam7s32) \\r
+    || defined(at91sam7s321) || defined(at91sam7s64) || defined(at91sam7s128) \\r
+    || defined(at91sam7s256) || defined(at91sam7s512)\r
+    ASSERT(duty > 0, "-F- Duty cycle value 0 is not permitted on SAM7S chips.\n\r");\r
+    ASSERT((duty > 1) || (AT91C_BASE_PWMC->PWMC_CH[channel].PWMC_CMR & AT91C_PWMC_CALG),\r
+           "-F- Duty cycle value 1 is not permitted in left-aligned mode on SAM7S chips.\n\r");\r
+#endif\r
+\r
+    // If channel is disabled, write to CDTY\r
+    if ((AT91C_BASE_PWMC->PWMC_SR & (1 << channel)) == 0) {\r
+\r
+        AT91C_BASE_PWMC->PWMC_CH[channel].PWMC_CDTYR = duty;\r
+    }\r
+    // Otherwise use update register\r
+    else {\r
+\r
+        AT91C_BASE_PWMC->PWMC_CH[channel].PWMC_CMR &= ~AT91C_PWMC_CPD;\r
+        AT91C_BASE_PWMC->PWMC_CH[channel].PWMC_CUPDR = duty;\r
+    }\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Enables the given PWM channel. This does NOT enable the corresponding pin;\r
+/// this must be done in the user code.\r
+/// \param channel  Channel number.\r
+//------------------------------------------------------------------------------\r
+void PWMC_EnableChannel(unsigned char channel)\r
+{\r
+    AT91C_BASE_PWMC->PWMC_ENA = 1 << channel;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Disables the given PWM channel.\r
+/// Beware, channel will be effectively disabled at the end of the current period.\r
+/// Application can check channel is disabled using the following wait loop:\r
+/// while ((AT91C_BASE_PWMC->PWMC_SR & (1 << channel)) != 0);\r
+/// \param channel  Channel number.\r
+//------------------------------------------------------------------------------\r
+void PWMC_DisableChannel(unsigned char channel)\r
+{\r
+    AT91C_BASE_PWMC->PWMC_DIS = 1 << channel;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Enables the period interrupt for the given PWM channel.\r
+/// \param channel  Channel number.\r
+//------------------------------------------------------------------------------\r
+void PWMC_EnableChannelIt(unsigned char channel)\r
+{\r
+    AT91C_BASE_PWMC->PWMC_IER = 1 << channel;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Disables the period interrupt for the given PWM channel.\r
+/// \param channel  Channel number.\r
+//------------------------------------------------------------------------------\r
+void PWMC_DisableChannelIt(unsigned char channel)\r
+{\r
+    AT91C_BASE_PWMC->PWMC_IDR = 1 << channel;\r
+}\r
+\r

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/pwmc/pwmc.h b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/pwmc/pwmc.h
new file mode 100644 (file)
index 0000000..fe2b440
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/pwmc/pwmc.h
@@ -0,0 +1,83 @@
+/* ----------------------------------------------------------------------------\r
+ *         ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+//------------------------------------------------------------------------------\r
+/// \unit\r
+///\r
+/// !Purpose\r
+///\r
+/// Interface for configuration the Pulse Width Modulation Controller (PWM) peripheral.\r
+///\r
+/// !Usage\r
+///\r
+///    -# Configures PWM clocks A & B to run at the given frequencies using\r
+///       PWMC_ConfigureClocks().\r
+///    -# Configure PWMC channel using PWMC_ConfigureChannel(), PWMC_SetPeriod()\r
+///       and PWMC_SetDutyCycle().\r
+///    -# Enable & disable channel using PWMC_EnableChannel() and \r
+///       PWMC_DisableChannel().\r
+///    -# Enable & disable the period interrupt for the given PWM channel using \r
+///       PWMC_EnableChannelIt() and PWMC_DisableChannelIt().\r
+///\r
+/// Please refer to the list of functions in the #Overview# tab of this unit\r
+/// for more detailed information.\r
+//------------------------------------------------------------------------------\r
+\r
+#ifndef PWMC_H\r
+#define PWMC_H\r
+\r
+//------------------------------------------------------------------------------\r
+//         Global functions\r
+//------------------------------------------------------------------------------\r
+\r
+extern void PWMC_ConfigureChannel(\r
+    unsigned char channel,\r
+    unsigned int prescaler,\r
+    unsigned int alignment,\r
+    unsigned int polarity);\r
+\r
+extern void PWMC_ConfigureClocks\r
+    (unsigned int clka,\r
+     unsigned int clkb,\r
+     unsigned int mck);\r
+\r
+extern void PWMC_SetPeriod(unsigned char channel, unsigned short period);\r
+\r
+extern void PWMC_SetDutyCycle(unsigned char channel, unsigned short duty);\r
+\r
+extern void PWMC_EnableChannel(unsigned char channel);\r
+\r
+extern void PWMC_DisableChannel(unsigned char channel);\r
+\r
+extern void PWMC_EnableChannelIt(unsigned char channel);\r
+\r
+extern void PWMC_DisableChannelIt(unsigned char channel);\r
+\r
+#endif //#ifndef PWMC_H\r
+\r

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/rstc/rstc.c b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/rstc/rstc.c
new file mode 100644 (file)
index 0000000..7f6ceca
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/rstc/rstc.c
@@ -0,0 +1,176 @@
+/* ----------------------------------------------------------------------------\r
+ *         ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+//-----------------------------------------------------------------------------\r
+//         Headers\r
+//-----------------------------------------------------------------------------\r
+\r
+#include <board.h>\r
+\r
+//-----------------------------------------------------------------------------\r
+//         Defines\r
+//-----------------------------------------------------------------------------\r
+\r
+/// Keywords to write to the reset registers\r
+#define RSTC_KEY_PASSWORD       (0xA5 << 24)\r
+\r
+//-----------------------------------------------------------------------------\r
+//         Exported functions\r
+//-----------------------------------------------------------------------------\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Configure the mode of the RSTC peripheral.\r
+/// The configuration is computed by the lib (AT91C_RSTC_*).\r
+/// \param rmr Desired mode configuration.\r
+//-----------------------------------------------------------------------------\r
+void RSTC_ConfigureMode(unsigned int rmr)\r
+{\r
+    rmr &= ~AT91C_RSTC_KEY;\r
+    AT91C_BASE_RSTC->RSTC_RMR = rmr | RSTC_KEY_PASSWORD;\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Enable/Disable the detection of a low level on the pin NRST as User Reset\r
+/// \param enable 1 to enable & 0 to disable.\r
+//-----------------------------------------------------------------------------\r
+void RSTC_SetUserResetEnable(unsigned char enable)\r
+{\r
+    unsigned int rmr = AT91C_BASE_RSTC->RSTC_RMR & (~AT91C_RSTC_KEY);\r
+    if (enable) {\r
+\r
+        rmr |=  AT91C_RSTC_URSTEN;\r
+    }\r
+    else {\r
+\r
+        rmr &= ~AT91C_RSTC_URSTEN;\r
+    }\r
+    AT91C_BASE_RSTC->RSTC_RMR = rmr | RSTC_KEY_PASSWORD;\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Enable/Disable the interrupt of a User Reset (USRTS bit in RSTC_RST).\r
+/// \param enable 1 to enable & 0 to disable.\r
+//-----------------------------------------------------------------------------\r
+void RSTC_SetUserResetInterruptEnable(unsigned char enable)\r
+{\r
+    unsigned int rmr = AT91C_BASE_RSTC->RSTC_RMR & (~AT91C_RSTC_KEY);\r
+    if (enable) {\r
+\r
+        rmr |=  AT91C_RSTC_URSTIEN;\r
+    }\r
+    else {\r
+\r
+        rmr &= ~AT91C_RSTC_URSTIEN;\r
+    }\r
+    AT91C_BASE_RSTC->RSTC_RMR = rmr | RSTC_KEY_PASSWORD;\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Setup the external reset length. The length is asserted during a time of\r
+/// pow(2, powl+1) Slow Clock(32KHz). The duration is between 60us and 2s.\r
+/// \param powl   Power length defined.\r
+//-----------------------------------------------------------------------------\r
+void RSTC_SetExtResetLength(unsigned char powl)\r
+{\r
+    unsigned int rmr = AT91C_BASE_RSTC->RSTC_RMR;\r
+    rmr &= ~(AT91C_RSTC_KEY | AT91C_RSTC_ERSTL);\r
+    rmr |=  (powl << 8) & AT91C_RSTC_ERSTL;\r
+    AT91C_BASE_RSTC->RSTC_RMR = rmr | RSTC_KEY_PASSWORD;\r
+}\r
+\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Resets the processor.\r
+//-----------------------------------------------------------------------------\r
+void RSTC_ProcessorReset(void)\r
+{\r
+    AT91C_BASE_RSTC->RSTC_RCR = AT91C_RSTC_PROCRST | RSTC_KEY_PASSWORD;\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Resets the peripherals.\r
+//-----------------------------------------------------------------------------\r
+void RSTC_PeripheralReset(void)\r
+{\r
+    AT91C_BASE_RSTC->RSTC_RCR = AT91C_RSTC_PERRST | RSTC_KEY_PASSWORD;\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Asserts the NRST pin for external resets.\r
+//-----------------------------------------------------------------------------\r
+void RSTC_ExtReset(void)\r
+{\r
+    AT91C_BASE_RSTC->RSTC_RCR = AT91C_RSTC_EXTRST | RSTC_KEY_PASSWORD;\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Return NRST pin level ( 1 or 0 ).\r
+//-----------------------------------------------------------------------------\r
+unsigned char RSTC_GetNrstLevel(void)\r
+{\r
+    if (AT91C_BASE_RSTC->RSTC_RSR & AT91C_RSTC_NRSTL) {\r
+\r
+        return 1;\r
+    }\r
+    return 0;\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Returns 1 if at least one high-to-low transition of NRST (User Reset) has\r
+/// been detected since the last read of RSTC_RSR.\r
+//-----------------------------------------------------------------------------\r
+unsigned char RSTC_IsUserResetDetected(void)\r
+{\r
+    if (AT91C_BASE_RSTC->RSTC_RSR & AT91C_RSTC_URSTS) {\r
+\r
+        return 1;\r
+    }\r
+    return 0;\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Return 1 if a software reset command is being performed by the reset\r
+/// controller. The reset controller is busy.\r
+//-----------------------------------------------------------------------------\r
+unsigned char RSTC_IsBusy(void)\r
+{\r
+    if (AT91C_BASE_RSTC->RSTC_RSR & AT91C_RSTC_SRCMP) {\r
+\r
+        return 1;\r
+    }\r
+    return 0;\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Get the status\r
+//-----------------------------------------------------------------------------\r
+unsigned char RSTC_GetStatus(void)\r
+{\r
+    return (AT91C_BASE_RSTC->RSTC_RSR);\r
+}\r

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/rstc/rstc.h b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/rstc/rstc.h
new file mode 100644 (file)
index 0000000..d3dbb16
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/rstc/rstc.h
@@ -0,0 +1,58 @@
+/* ----------------------------------------------------------------------------\r
+ *         ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+#ifndef _RSTC_H\r
+#define _RSTC_H\r
+\r
+//-----------------------------------------------------------------------------\r
+//         Exported functions\r
+//-----------------------------------------------------------------------------\r
+\r
+extern void RSTC_ConfigureMode(unsigned int rmr);\r
+\r
+extern void RSTC_SetUserResetEnable(unsigned char enable);\r
+\r
+extern void RSTC_SetUserResetInterruptEnable(unsigned char enable);\r
+\r
+extern void RSTC_SetExtResetLength(unsigned char powl);\r
+\r
+extern void RSTC_ProcessorReset(void);\r
+\r
+extern void RSTC_PeripheralReset(void);\r
+\r
+extern void RSTC_ExtReset(void);\r
+\r
+extern unsigned char RSTC_GetNrstLevel(void);\r
+\r
+extern unsigned char RSTC_IsUserResetDetected(void);\r
+\r
+extern unsigned char RSTC_IsBusy(void);\r
+\r
+\r
+#endif // #ifndef _RSTC_H\r

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/rtc/rtc.c b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/rtc/rtc.c
new file mode 100644 (file)
index 0000000..189c6d5
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/rtc/rtc.c
@@ -0,0 +1,403 @@
+/* ----------------------------------------------------------------------------\r
+ *         ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+//------------------------------------------------------------------------------\r
+//         Headers\r
+//------------------------------------------------------------------------------\r
+\r
+#include "rtc.h"\r
+#include <board.h>\r
+#include <utility/assert.h>\r
+#include <utility/trace.h>\r
+\r
+//------------------------------------------------------------------------------\r
+//         Exported functions\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+/// Sets the RTC in either 12- or 24-hour mode.\r
+/// \param mode  Hour mode.\r
+//------------------------------------------------------------------------------\r
+void RTC_SetHourMode(unsigned int mode)\r
+{\r
+    SANITY_CHECK((mode & 0xFFFFFFFE) == 0);\r
+\r
+    TRACE_DEBUG("RTC_SetHourMode()\n\r");\r
+\r
+    AT91C_BASE_RTC->RTC_MR = mode;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Gets the RTC mode.\r
+/// \return Hour mode.\r
+//------------------------------------------------------------------------------\r
+unsigned int RTC_GetHourMode()\r
+{\r
+    unsigned int hmode;\r
+\r
+    TRACE_DEBUG("RTC_SetHourMode()\n\r");\r
+\r
+    hmode = AT91C_BASE_RTC->RTC_MR;\r
+    hmode &= 0xFFFFFFFE;\r
+\r
+    return hmode;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Enables the selected interrupt sources of the RTC.\r
+/// \param sources  Interrupt sources to enable.\r
+//------------------------------------------------------------------------------\r
+void RTC_EnableIt(unsigned int sources)\r
+{\r
+    SANITY_CHECK((sources & ~0x1F) == 0);\r
+\r
+    TRACE_DEBUG("RTC_EnableIt()\n\r");\r
+\r
+    AT91C_BASE_RTC->RTC_IER = sources;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Disables the selected interrupt sources of the RTC.\r
+/// \param sources  Interrupt sources to disable.\r
+//------------------------------------------------------------------------------\r
+void RTC_DisableIt(unsigned int sources)\r
+{\r
+    SANITY_CHECK((sources & ~0x1F) == 0);\r
+\r
+    TRACE_DEBUG("RTC_DisableIt()\n\r");\r
+\r
+    AT91C_BASE_RTC->RTC_IDR = sources;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Sets the current time in the RTC.\r
+/// \param hour  Current hour in 24 hour mode.\r
+/// \param minute  Current minute.\r
+/// \param second  Current second.\r
+/// \return 0 sucess, 1 fail to set\r
+//------------------------------------------------------------------------------\r
+int RTC_SetTime(unsigned char hour, unsigned char minute, unsigned char second)\r
+{\r
+    unsigned int time=0;\r
+    unsigned char hour_bcd;\r
+    unsigned char min_bcd;\r
+    unsigned char sec_bcd;\r
+\r
+    TRACE_DEBUG("RTC_SetTime(%02d:%02d:%02d)\n\r", hour, minute, second);\r
+   \r
+    // if 12-hour mode, set AMPM bit\r
+    if ((AT91C_BASE_RTC->RTC_MR & AT91C_RTC_HRMOD) == AT91C_RTC_HRMOD) {\r
+          \r
+        if (hour > 12) {\r
+\r
+            hour -= 12;\r
+            time |= AT91C_RTC_AMPM;\r
+        }\r
+    }\r
+    hour_bcd  = (hour%10) | ((hour/10)<<4);\r
+    min_bcd   = (minute%10) | ((minute/10)<<4);\r
+    sec_bcd   = (second%10) | ((second/10)<<4);\r
+    \r
+    //value overflow\r
+    if((hour_bcd & (unsigned char)(~RTC_HOUR_BIT_LEN_MASK)) |\r
+       (min_bcd & (unsigned char)(~RTC_MIN_BIT_LEN_MASK)) |\r
+         (sec_bcd & (unsigned char)(~RTC_SEC_BIT_LEN_MASK)))\r
+            return 1;\r
+    \r
+    time = sec_bcd | (min_bcd << 8) | (hour_bcd<<16);\r
+\r
+//    time |= ((hour % 10) << 16) | ((hour / 10) << 20);\r
+\r
+    // Set time\r
+    //if((AT91C_BASE_RTC->RTC_SR & AT91C_RTC_SECEV) != AT91C_RTC_SECEV) return 1;\r
+    while ((AT91C_BASE_RTC->RTC_SR & AT91C_RTC_SECEV) != AT91C_RTC_SECEV);//wait from previous set\r
+    AT91C_BASE_RTC->RTC_CR |= AT91C_RTC_UPDTIM;\r
+    while ((AT91C_BASE_RTC->RTC_SR & AT91C_RTC_ACKUPD) != AT91C_RTC_ACKUPD);\r
+    AT91C_BASE_RTC->RTC_SCCR = AT91C_RTC_ACKUPD;\r
+    AT91C_BASE_RTC->RTC_TIMR = time;\r
+    AT91C_BASE_RTC->RTC_CR &= ~AT91C_RTC_UPDTIM;\r
+    AT91C_BASE_RTC->RTC_SCCR |= AT91C_RTC_SECEV;//clear SECENV in SCCR\r
+        \r
+    return (int)(AT91C_BASE_RTC->RTC_VER & AT91C_RTC_NVTIM);\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Retrieves the current time as stored in the RTC in several variables.\r
+/// \param pHour  If not null, current hour is stored in this variable.\r
+/// \param pMinute  If not null, current minute is stored in this variable.\r
+/// \param pSecond  If not null, current second is stored in this variable.\r
+//------------------------------------------------------------------------------\r
+void RTC_GetTime(\r
+    unsigned char *pHour,\r
+    unsigned char *pMinute,\r
+    unsigned char *pSecond)\r
+{\r
+    unsigned int time;\r
+\r
+    TRACE_DEBUG("RTC_GetTime()\n\r");\r
+\r
+    // Get current RTC time\r
+    time = AT91C_BASE_RTC->RTC_TIMR;\r
+    while (time != AT91C_BASE_RTC->RTC_TIMR) {\r
+\r
+        time = AT91C_BASE_RTC->RTC_TIMR;\r
+    }\r
+\r
+    // Hour\r
+    if (pHour) {\r
+\r
+        *pHour = ((time & 0x00300000) >> 20) * 10\r
+                 + ((time & 0x000F0000) >> 16);\r
+        if ((time & AT91C_RTC_AMPM) == AT91C_RTC_AMPM) {\r
+\r
+            *pHour += 12;\r
+        }\r
+    }\r
+    \r
+    // Minute\r
+    if (pMinute) {\r
+\r
+        *pMinute = ((time & 0x00007000) >> 12) * 10\r
+                   + ((time & 0x00000F00) >> 8);\r
+    }\r
+\r
+    // Second\r
+    if (pSecond) {\r
+\r
+        *pSecond = ((time & 0x00000070) >> 4) * 10\r
+                   + (time & 0x0000000F);\r
+    }\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Sets a time alarm on the RTC. The match is performed only on the provided\r
+/// variables; setting all pointers to 0 disables the time alarm.\r
+/// Note: in AM/PM mode, the hour value must have bit #7 set for PM, cleared for\r
+/// AM (as expected in the time registers).\r
+/// \param pHour  If not null, the time alarm will hour-match this value.\r
+/// \param pMinute  If not null, the time alarm will minute-match this value.\r
+/// \param pSecond  If not null, the time alarm will second-match this value.\r
+/// \return 0 success, 1 fail to set\r
+//------------------------------------------------------------------------------\r
+int RTC_SetTimeAlarm(\r
+    unsigned char *pHour,\r
+    unsigned char *pMinute,\r
+    unsigned char *pSecond)\r
+{\r
+    unsigned int alarm = 0;\r
+\r
+    TRACE_DEBUG("RTC_SetTimeAlarm()\n\r");\r
+\r
+    // Hour\r
+    if (pHour) {\r
+\r
+        alarm |= AT91C_RTC_HOUREN | ((*pHour / 10) << 20) | ((*pHour % 10) << 16);\r
+    }\r
+\r
+    // Minute\r
+    if (pMinute) {\r
+\r
+        alarm |= AT91C_RTC_MINEN | ((*pMinute / 10) << 12) | ((*pMinute % 10) << 8);\r
+    }\r
+\r
+    // Second\r
+    if (pSecond) {\r
+\r
+        alarm |= AT91C_RTC_SECEN | ((*pSecond / 10) << 4) | (*pSecond % 10);\r
+    }\r
+\r
+    AT91C_BASE_RTC->RTC_TIMALR = alarm;\r
+    \r
+    return (int)(AT91C_BASE_RTC->RTC_VER & AT91C_RTC_NVTIMALR);\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Retrieves the current year, month and day from the RTC. Month, day and week\r
+/// values are numbered starting at 1.\r
+/// \param pYear  Current year (optional).\r
+/// \param pMonth  Current month (optional).\r
+/// \param pDay  Current day (optional).\r
+/// \param pWeek  Current day in current week (optional).\r
+//------------------------------------------------------------------------------\r
+void RTC_GetDate(\r
+    unsigned short *pYear,\r
+    unsigned char *pMonth,\r
+    unsigned char *pDay,\r
+    unsigned char *pWeek)\r
+{\r
+    unsigned int date;\r
+\r
+    // Get current date (multiple reads are necessary to insure a stable value)\r
+    do {\r
+\r
+        date = AT91C_BASE_RTC->RTC_CALR;\r
+    }\r
+    while (date != AT91C_BASE_RTC->RTC_CALR);\r
+\r
+    // Retrieve year\r
+    if (pYear) {\r
+\r
+        *pYear = (((date  >> 4) & 0x7) * 1000)\r
+                 + ((date & 0xF) * 100)\r
+                 + (((date >> 12) & 0xF) * 10)\r
+                 + ((date >> 8) & 0xF);\r
+    }\r
+\r
+    // Retrieve month\r
+    if (pMonth) {\r
+\r
+        *pMonth = (((date >> 20) & 1) * 10) + ((date >> 16) & 0xF);\r
+    }\r
+\r
+    // Retrieve day\r
+    if (pDay) {\r
+\r
+        *pDay = (((date >> 28) & 0x3) * 10) + ((date >> 24) & 0xF);\r
+    }\r
+\r
+    // Retrieve week\r
+    if (pWeek) {\r
+\r
+        *pWeek = ((date >> 21) & 0x7);\r
+    }\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Sets the current year, month and day in the RTC. Month, day and week values\r
+/// must be numbered starting from 1.\r
+/// \param year  Current year.\r
+/// \param month  Current month.\r
+/// \param day  Current day.\r
+/// \param week  Day number in current week.\r
+/// \return 0 success, 1 fail to set\r
+//------------------------------------------------------------------------------\r
+int RTC_SetDate(\r
+    unsigned short year,\r
+    unsigned char month,\r
+    unsigned char day,\r
+    unsigned char week)\r
+{\r
+    unsigned int date;\r
+    unsigned char cent_bcd;\r
+    unsigned char year_bcd;\r
+    unsigned char month_bcd;\r
+    unsigned char day_bcd;\r
+    unsigned char week_bcd;\r
+    \r
+    cent_bcd  = ((year/100)%10) | ((year/1000)<<4);\r
+    year_bcd  = (year%10) | ((year/10)%10);\r
+    month_bcd = ((month%10) | (month/10)<<4);\r
+    day_bcd   = ((day%10) | (day/10)<<4);\r
+    week_bcd  = ((week%10) | (week/10)<<4);\r
+    \r
+    //value over flow\r
+    if((cent_bcd & (unsigned char)(~RTC_CENT_BIT_LEN_MASK)) |\r
+        (year_bcd & (unsigned char)(~RTC_YEAR_BIT_LEN_MASK)) |\r
+          (month_bcd & (unsigned char)(~RTC_MONTH_BIT_LEN_MASK)) |\r
+            (week_bcd & (unsigned char)(~RTC_WEEK_BIT_LEN_MASK)) |\r
+              (day_bcd & (unsigned char)(~RTC_DATE_BIT_LEN_MASK)))\r
+                return 1;\r
+\r
+\r
+    // Convert values to date register value\r
+    date = cent_bcd |\r
+            (year_bcd << 8) |\r
+              (month_bcd << 16) |\r
+                (week_bcd << 21) |\r
+                  (day_bcd << 24);\r
+    \r
+           \r
+    // Update calendar register\r
+    //if((AT91C_BASE_RTC->RTC_SR & AT91C_RTC_SECEV) != AT91C_RTC_SECEV) return 1;\r
+    while ((AT91C_BASE_RTC->RTC_SR & AT91C_RTC_SECEV) != AT91C_RTC_SECEV);//wait from previous set\r
+    AT91C_BASE_RTC->RTC_CR |= AT91C_RTC_UPDCAL;\r
+    while ((AT91C_BASE_RTC->RTC_SR & AT91C_RTC_ACKUPD) != AT91C_RTC_ACKUPD);\r
+    AT91C_BASE_RTC->RTC_SCCR = AT91C_RTC_ACKUPD;\r
+    AT91C_BASE_RTC->RTC_CALR = date;\r
+    AT91C_BASE_RTC->RTC_CR &= ~AT91C_RTC_UPDCAL;\r
+    AT91C_BASE_RTC->RTC_SCCR |= AT91C_RTC_SECEV;//clear SECENV in SCCR\r
+    \r
+    return (int)(AT91C_BASE_RTC->RTC_VER & AT91C_RTC_NVCAL);\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Sets a date alarm in the RTC. The alarm will match only the provided values;\r
+/// passing a null-pointer disables the corresponding field match.\r
+/// \param pMonth  If not null, the RTC alarm will month-match this value.\r
+/// \param pDay  If not null, the RTC alarm will day-match this value.\r
+/// \return 0 success, 1 fail to set\r
+//------------------------------------------------------------------------------\r
+int RTC_SetDateAlarm(unsigned char *pMonth, unsigned char *pDay)\r
+{\r
+    unsigned int alarm = 0x01010000;\r
+\r
+    TRACE_DEBUG("RTC_SetDateAlarm()\n\r");\r
+\r
+    // Compute alarm field value\r
+    if (pMonth) {\r
+\r
+        alarm |= AT91C_RTC_MONTHEN | ((*pMonth / 10) << 20) | ((*pMonth % 10) << 16);\r
+    }\r
+    if (pDay) {\r
+\r
+        alarm |= AT91C_RTC_DATEEN | ((*pDay / 10) << 28) | ((*pDay % 10) << 24);\r
+    }\r
+\r
+    // Set alarm\r
+    AT91C_BASE_RTC->RTC_CALALR = alarm;\r
+    \r
+    return (int)(AT91C_BASE_RTC->RTC_VER & AT91C_RTC_NVCALALR);\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Clear flag bits of status clear command register in the RTC. \r
+/// \param mask Bits mask of cleared events\r
+//------------------------------------------------------------------------------\r
+void RTC_ClearSCCR(unsigned int mask)\r
+{\r
+    // Clear all flag bits in status clear command register\r
+    mask &= AT91C_RTC_ACKUPD | AT91C_RTC_ALARM | AT91C_RTC_SECEV | \\r
+                                    AT91C_RTC_TIMEV | AT91C_RTC_CALEV;\r
+    \r
+    AT91C_BASE_RTC->RTC_SCCR = mask;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Get flag bits of status register in the RTC. \r
+/// \param mask Bits mask of Status Register\r
+/// \return Status register & mask\r
+//------------------------------------------------------------------------------\r
+unsigned int RTC_GetSR(unsigned int mask)\r
+{\r
+    unsigned int event;\r
+    \r
+    event = AT91C_BASE_RTC->RTC_SR;\r
+    \r
+    return (event & mask);\r
+}\r

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/rtc/rtc.h b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/rtc/rtc.h
new file mode 100644 (file)
index 0000000..e98890f
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/rtc/rtc.h
@@ -0,0 +1,90 @@
+/* ----------------------------------------------------------------------------\r
+ *         ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+#ifndef RTC_H\r
+#define RTC_H\r
+\r
+//------------------------------------------------------------------------------\r
+//         Macro used\r
+//------------------------------------------------------------------------------\r
+#define RTC_HOUR_BIT_LEN_MASK   0x3F\r
+#define RTC_MIN_BIT_LEN_MASK    0x7F\r
+#define RTC_SEC_BIT_LEN_MASK    0x7F\r
+#define RTC_CENT_BIT_LEN_MASK   0x7F\r
+#define RTC_YEAR_BIT_LEN_MASK   0xFF\r
+#define RTC_MONTH_BIT_LEN_MASK  0x1F\r
+#define RTC_DATE_BIT_LEN_MASK   0x3F\r
+#define RTC_WEEK_BIT_LEN_MASK   0x07\r
+\r
+//------------------------------------------------------------------------------\r
+//         Exported functions\r
+//------------------------------------------------------------------------------\r
+\r
+extern void RTC_SetHourMode(unsigned int mode);\r
+\r
+extern unsigned int RTC_GetHourMode();\r
+\r
+extern void RTC_EnableIt(unsigned int sources);\r
+\r
+extern void RTC_DisableIt(unsigned int sources);\r
+\r
+extern int RTC_SetTime(\r
+       unsigned char hour,\r
+       unsigned char minute,\r
+       unsigned char second);\r
+\r
+extern void RTC_GetTime(\r
+       unsigned char *pHour,\r
+       unsigned char *pMinute,\r
+       unsigned char *pSecond);\r
+\r
+extern int RTC_SetTimeAlarm(\r
+       unsigned char *pHour,\r
+       unsigned char *pMinute,\r
+       unsigned char *pSecond);\r
+\r
+void RTC_GetDate(\r
+    unsigned short *pYear,\r
+    unsigned char *pMonth,\r
+    unsigned char *pDay,\r
+    unsigned char *pWeek);\r
+\r
+extern int RTC_SetDate(\r
+    unsigned short year,\r
+    unsigned char month,\r
+    unsigned char day,\r
+    unsigned char week);\r
+\r
+extern int RTC_SetDateAlarm(unsigned char *pMonth, unsigned char *pDay);\r
+\r
+extern void RTC_ClearSCCR(unsigned int mask);\r
+\r
+extern unsigned int RTC_GetSR(unsigned int mask);\r
+#endif //#ifndef RTC_H\r
+\r

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/rtt/rtt.c b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/rtt/rtt.c
new file mode 100644 (file)
index 0000000..5322108
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/rtt/rtt.c
@@ -0,0 +1,93 @@
+/* ----------------------------------------------------------------------------\r
+ *         ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+//------------------------------------------------------------------------------\r
+//         Headers\r
+//------------------------------------------------------------------------------\r
+\r
+#include "rtt.h"\r
+#include <utility/assert.h>\r
+\r
+//------------------------------------------------------------------------------\r
+//         Exported functions\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+/// Changes the prescaler value of the given RTT and restarts it. This function\r
+/// disables RTT interrupt sources.\r
+/// \param rtt  Pointer to a AT91S_RTTC instance.\r
+/// \param prescaler  Prescaler value for the RTT.\r
+//------------------------------------------------------------------------------\r
+void RTT_SetPrescaler(AT91S_RTTC *rtt, unsigned short prescaler)\r
+{\r
+    rtt->RTTC_RTMR = (prescaler | AT91C_RTTC_RTTRST);\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Returns the current value of the RTT timer value.\r
+/// \param rtt  Pointer to a AT91S_RTTC instance.\r
+//------------------------------------------------------------------------------\r
+unsigned int RTT_GetTime(AT91S_RTTC *rtt)\r
+{\r
+    return rtt->RTTC_RTVR;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Enables the specified RTT interrupt sources.\r
+/// \param rtt  Pointer to a AT91S_RTTC instance.\r
+/// \param sources  Bitmask of interrupts to enable.\r
+//------------------------------------------------------------------------------\r
+void RTT_EnableIT(AT91S_RTTC *rtt, unsigned int sources)\r
+{\r
+    ASSERT((sources & 0x0004FFFF) == 0,\r
+           "RTT_EnableIT: Wrong sources value.\n\r");\r
+    rtt->RTTC_RTMR |= sources;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Returns the status register value of the given RTT.\r
+/// \param rtt  Pointer to an AT91S_RTTC instance.\r
+//------------------------------------------------------------------------------\r
+unsigned int RTT_GetStatus(AT91S_RTTC *rtt)\r
+{\r
+    return rtt->RTTC_RTSR;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Configures the RTT to generate an alarm at the given time.\r
+/// \param pRtt  Pointer to an AT91S_RTTC instance.\r
+/// \param time  Alarm time.\r
+//------------------------------------------------------------------------------\r
+void RTT_SetAlarm(AT91S_RTTC *pRtt, unsigned int time)\r
+{\r
+    SANITY_CHECK(time > 0);\r
+\r
+    pRtt->RTTC_RTAR = time - 1;\r
+}\r
+\r

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/rtt/rtt.h b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/rtt/rtt.h
new file mode 100644 (file)
index 0000000..54843c4
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/rtt/rtt.h
@@ -0,0 +1,76 @@
+/* ----------------------------------------------------------------------------\r
+ *         ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+//-----------------------------------------------------------------------------\r
+/// \unit\r
+///\r
+/// !Purpose\r
+///\r
+/// Implementation of RTT Real Time Timer controller.\r
+///\r
+/// !Contents\r
+///\r
+/// Please refer to the list of functions in the #Overview# tab of this unit\r
+/// for more detailed information.\r
+//-----------------------------------------------------------------------------\r
+\r
+\r
+#ifndef RTT_H\r
+#define RTT_H\r
+\r
+//------------------------------------------------------------------------------\r
+//         Headers\r
+//------------------------------------------------------------------------------\r
+\r
+#include <board.h>\r
+\r
+//------------------------------------------------------------------------------\r
+//         Definitions\r
+//------------------------------------------------------------------------------\r
+\r
+#ifndef AT91C_BASE_RTTC\r
+    #define AT91C_BASE_RTTC         AT91C_BASE_RTTC0\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+//         Exported functions\r
+//------------------------------------------------------------------------------\r
+\r
+extern void RTT_SetPrescaler(AT91S_RTTC *rtt, unsigned short prescaler);\r
+\r
+extern unsigned int RTT_GetTime(AT91S_RTTC *rtt);\r
+\r
+extern void RTT_EnableIT(AT91S_RTTC *rtt, unsigned int sources);\r
+\r
+extern unsigned int RTT_GetStatus(AT91S_RTTC *rtt);\r
+\r
+extern void RTT_SetAlarm(AT91S_RTTC *pRtt, unsigned int time);\r
+\r
+#endif //#ifndef RTT_H\r
+\r

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/shdwc/shdwc.c b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/shdwc/shdwc.c
new file mode 100644 (file)
index 0000000..09875c4
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/shdwc/shdwc.c
@@ -0,0 +1,68 @@
+/* ----------------------------------------------------------------------------\r
+ *         ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+//------------------------------------------------------------------------------\r
+//         Headers\r
+//------------------------------------------------------------------------------\r
+\r
+#include "shdwc.h"\r
+#include <utility/assert.h>\r
+#include <utility/trace.h>\r
+#include <utility/util.h>\r
+\r
+//------------------------------------------------------------------------------\r
+//         Global functions\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+/// Configure the Shut Down  and do it\r
+/// \param rtt_enable\r
+/// \param wk0_mode\r
+/// \param wk0_debounce\r
+//------------------------------------------------------------------------------  \r
+void SHDWC_DoShutDown(\r
+    unsigned char rtt_enable,\r
+    unsigned char wk0_mode,\r
+    unsigned char wk0_debounce\r
+    )\r
+{\r
+    AT91C_BASE_SHDWC->SHDWC_SHMR =  (rtt_enable << 16) | \r
+                                  wk0_mode | ( (wk0_debounce & 0xF) << 4); \r
+    \r
+   AT91C_BASE_SHDWC->SHDWC_SHCR = (0xA5 << 24) | 1;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Get Status\r
+//------------------------------------------------------------------------------  \r
+unsigned int SHDWC_GetStatus(void)\r
+{\r
+    return AT91C_BASE_SHDWC->SHDWC_SHSR;\r
+}\r
+\r

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/shdwc/shdwc.h b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/shdwc/shdwc.h
new file mode 100644 (file)
index 0000000..f89f6e1
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/shdwc/shdwc.h
@@ -0,0 +1,43 @@
+/* ----------------------------------------------------------------------------\r
+ *         ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+#ifndef SHDWC_H\r
+#define SHDWC_H\r
+\r
+//------------------------------------------------------------------------------\r
+//         Global functions\r
+//------------------------------------------------------------------------------\r
+\r
+extern void SHDWC_DoShutDown(unsigned char rtt_enable, \r
+                             unsigned char wk0_mode, \r
+                             unsigned char wk0_debounce);\r
+\r
+unsigned int SHDWC_GetStatus(void);\r
+\r
+#endif //#ifndef SHDWC_H\r

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/slcdc/slcdc.c b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/slcdc/slcdc.c
new file mode 100644 (file)
index 0000000..59fc238
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/slcdc/slcdc.c
@@ -0,0 +1,192 @@
+/* ----------------------------------------------------------------------------\r
+ *         ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+//------------------------------------------------------------------------------\r
+//         Headers\r
+//------------------------------------------------------------------------------\r
+\r
+#include "slcdc.h"\r
+#include <board.h>\r
+#include <utility/assert.h>\r
+\r
+#include <string.h>\r
+\r
+//------------------------------------------------------------------------------\r
+//         Local definitions\r
+//------------------------------------------------------------------------------\r
+\r
+/// Size of SLCDC buffer in bytes.\r
+#define BUFFER_SIZE     320\r
+\r
+//------------------------------------------------------------------------------\r
+//         Global functions\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+/// Initializes the Segment LCD controller.\r
+/// \param commons  Number of commons used by the display.\r
+/// \param segments  Number of segments used by the display.\r
+/// \param bias  Bias value.\r
+/// \param timeSetting  Buffer timing value.\r
+//------------------------------------------------------------------------------\r
+void SLCDC_Configure(\r
+    unsigned int commons,\r
+    unsigned int segments,\r
+    unsigned int bias,\r
+    unsigned int timeSetting)\r
+{\r
+    SANITY_CHECK((commons > 0) && (commons <= 10));\r
+    SANITY_CHECK((segments > 0) && (segments <= 40));\r
+    SANITY_CHECK((bias & ~AT91C_SLCDC_BIAS) == 0);\r
+    SANITY_CHECK((timeSetting & ~(0xF << 16)) == 0);  \r
+    SANITY_CHECK((timeSetting >> 16) < 0x0A);\r
+\r
+    // Enable peripheral clock\r
+    AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_SLCD;\r
+    AT91C_BASE_SLCDC->SLCDC_MR = (commons - 1) | ((segments - 1) << 8) | bias | timeSetting;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Clears the SLCD display buffer.\r
+//------------------------------------------------------------------------------\r
+void SLCDC_Clear(void)\r
+{\r
+    memset((void *) AT91C_BASE_SLCDC->SLCDC_MEM, 0, BUFFER_SIZE);\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Enables the SLCD controller.\r
+//------------------------------------------------------------------------------\r
+void SLCDC_Enable(void)\r
+{\r
+    AT91C_BASE_SLCDC->SLCDC_CR = AT91C_SLCDC_LCDEN;\r
+    while (AT91C_BASE_SLCDC -> SLCDC_SR != AT91C_SLCDC_ENA);\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Disables the SLCD controller.\r
+//------------------------------------------------------------------------------\r
+void SLCDC_Disable(void)\r
+{\r
+    AT91C_BASE_SLCDC->SLCDC_CR = AT91C_SLCDC_LCDDIS;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Enables the SLCD low power mode.\r
+//------------------------------------------------------------------------------\r
+void SLCDC_EnableLowPowerMode(void)\r
+{\r
+    unsigned int value;\r
+\r
+    value = AT91C_BASE_SLCDC->SLCDC_MR;\r
+    value &= ~AT91C_SLCDC_LPMODE;\r
+    value |=AT91C_SLCDC_LPMODE;\r
+    AT91C_BASE_SLCDC->SLCDC_MR = value;\r
+}\r
+ \r
+//------------------------------------------------------------------------------\r
+/// Disables the SLCD low power mode\r
+//------------------------------------------------------------------------------\r
+void SLCDC_DisableLowPowerMode(void)\r
+{\r
+    unsigned int value;\r
+\r
+    value = AT91C_BASE_SLCDC->SLCDC_MR;\r
+    value &= ~AT91C_SLCDC_LPMODE;\r
+    AT91C_BASE_SLCDC->SLCDC_MR = value;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Adjusts the frame frequency. Frequency = FsCLK / (prescaler * divider . NCOM)\r
+/// \param prescalerValue  Prescaler value\r
+/// \param dividerValue  Divider value\r
+//------------------------------------------------------------------------------\r
+void SLCDC_SetFrameFreq(unsigned int prescalerValue, unsigned int dividerValue)\r
+{\r
+    SANITY_CHECK((prescalerValue & ~AT91C_SLCDC_PRESC) == 0);\r
+    SANITY_CHECK((dividerValue & (~(0x07 << 8))) == 0);\r
+\r
+    AT91C_BASE_SLCDC->SLCDC_FRR = prescalerValue | dividerValue;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Sets the display mode (normal/force off/force on/blinking).\r
+/// \param mode  Display mode to be set\r
+//------------------------------------------------------------------------------\r
+void SLCDC_SetDisplayMode(unsigned int mode)\r
+{\r
+    unsigned int value;\r
+\r
+    SANITY_CHECK(mode < 8);\r
+           \r
+    value = AT91C_BASE_SLCDC->SLCDC_DR;\r
+    value &= ~AT91C_SLCDC_DISPMODE;\r
+    value |= mode;\r
+    AT91C_BASE_SLCDC->SLCDC_DR = value;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Adjusts the display blinking frequency.\r
+/// Blinking frequency = Frame Frequency / LCDBLKFREQ.\r
+/// \param frequency  Frequency value.\r
+//------------------------------------------------------------------------------\r
+void SLCDC_SetBlinkFreq(unsigned int frequency)\r
+{\r
+    unsigned int value;\r
+\r
+    SANITY_CHECK((frequency & ~(0xFF << 8)) == 0);\r
+\r
+    value = AT91C_BASE_SLCDC->SLCDC_DR;\r
+    value &= ~AT91C_SLCDC_BLKFREQ;\r
+    value |= frequency;           \r
+    AT91C_BASE_SLCDC->SLCDC_DR = frequency;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Enables the selected SLCDC interrupt sources.\r
+/// \param sources  Interrupt sources to enable.\r
+//------------------------------------------------------------------------------\r
+void SLCDC_EnableInterrupts(unsigned int sources)\r
+{\r
+    SANITY_CHECK((sources & 0xFFFFFFFA) == 0);\r
+\r
+    AT91C_BASE_SLCDC->SLCDC_IER = sources;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Disables the selected SLCDC interrupt sources.\r
+/// \param sources  Interrupt sources to disable.\r
+//------------------------------------------------------------------------------\r
+void SLCDC_DisableInterrupts(unsigned int sources)\r
+{\r
+    SANITY_CHECK((sources & 0xFFFFFFFA) == 0);\r
+\r
+    AT91C_BASE_SLCDC->SLCDC_IDR = sources;\r
+}\r
+\r

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/slcdc/slcdc.h b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/slcdc/slcdc.h
new file mode 100644 (file)
index 0000000..2b18960
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/slcdc/slcdc.h
@@ -0,0 +1,93 @@
+/* ----------------------------------------------------------------------------\r
+ *         ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+//------------------------------------------------------------------------------\r
+/// \unit\r
+///\r
+/// !Purpose\r
+///\r
+/// Interface for configuration the Segment LCD Controller (SLCDC) peripheral.\r
+///\r
+/// !Usage\r
+///\r
+/// -# Initializes the Segment LCD controller using SLCDC_Configure().\r
+/// -# Clears the SLCD display buffer using SLCDC_Clear().\r
+/// -# Enable & disable SLCD controller using SLCDC_Enable() and SLCDC_Disable().\r
+/// -# Enables & disable the SLCD low power mode using SLCDC_EnableLowPowerMode () \r
+/// and SLCDC_DisableLowPowerMode().   \r
+/// -# Adjusts the frame frequency using SLCDC_SetFrameFreq().\r
+/// -# Sets the display mode (normal/force off/force on/blinking) using \r
+/// SLCDC_SetDisplayMode().\r
+/// -# Adjusts the display blinking frequency using SLCDC_SetBlinkFreq().\r
+/// -# Enables & disable the selected SLCDC interrupt sources using\r
+/// SLCDC_EnableInterrupts() and SLCDC_DisableInterrupts().\r
+//------------------------------------------------------------------------------\r
+\r
+#ifndef SLCDC_H\r
+#define SLCDC_H\r
+\r
+//------------------------------------------------------------------------------\r
+//         Global definitions\r
+//------------------------------------------------------------------------------\r
+\r
+/// Number of segments in SLCD.\r
+#define S7LEKLCD_NUM_SEGMENTS       40\r
+/// Number of commons in SLCD.\r
+#define S7LEKLCD_NUM_COMMONS        10\r
+\r
+//------------------------------------------------------------------------------\r
+//         Global functions\r
+//------------------------------------------------------------------------------\r
+\r
+extern void SLCDC_Configure(\r
+    unsigned int commons,\r
+    unsigned int segments,\r
+    unsigned int bias,\r
+    unsigned int timeSetting);\r
+\r
+extern void SLCDC_Clear(void);\r
+\r
+extern void SLCDC_Enable(void);\r
+\r
+extern void SLCDC_Disable(void);\r
+\r
+extern void SLCDC_SetFrameFreq(\r
+    unsigned int prescalerValue,\r
+    unsigned int dividerValue);\r
+\r
+extern void SLCDC_SetDisplayMode(unsigned int mode);\r
+\r
+extern void SLCDC_SetBlinkFreq(unsigned int frequency);\r
+\r
+extern void SLCDC_EnableInterrupts(unsigned int sources);\r
+\r
+extern void SLCDC_DisableInterrupts(unsigned int sources);\r
+\r
+#endif //#ifndef SLCDC_H\r
+\r

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/slck/slck.c b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/slck/slck.c
new file mode 100644 (file)
index 0000000..bb530ad
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/slck/slck.c
@@ -0,0 +1,251 @@
+/* ----------------------------------------------------------------------------\r
+ *         ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+#if defined(at91cap9)\r
+//------------------------------------------------------------------------------\r
+//         Headers\r
+//------------------------------------------------------------------------------\r
+\r
+#include "slck.h"\r
+#include <utility/assert.h>\r
+#include <utility/trace.h>\r
+#include <utility/util.h>\r
+\r
+//------------------------------------------------------------------------------\r
+//         Local definitions\r
+//------------------------------------------------------------------------------\r
+\r
+/// Start Up Time Slow Clock 32K Oscillator // see DC characteritics in Datasheet\r
+#define T_ST_SLCK_32K_IN_MS  1200 \r
+\r
+/// Start Up Time Slow Clock RC Oscillator  // see DC characteritics in Datasheet\r
+#define T_ST_SLCK_RC_IN_US     75 \r
+\r
+#define FREQ_SLCK_32K     32768 // see DC characteritics in Datasheet\r
+#define MIN_FREQ_SLCK_RC  20000 // see DC characteritics in Datasheet\r
+\r
+#define TIME_5_CYCLES_32K_IN_US     ((2 * 5 * 1000000) / FREQ_SLCK_32K)\r
+#define TIME_5_CYCLES_RC_IN_US      ((2 * 5 * 1000000) / MIN_FREQ_SLCK_RC)\r
+\r
+//------------------------------------------------------------------------------\r
+//         Local functions\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+/// Wait time in ms\r
+//------------------------------------------------------------------------------\r
+// not precise, depends on the compiler and on the options\r
+static void WaitTimeInMs(unsigned int pck, unsigned int time_ms)\r
+{\r
+    register unsigned int i = 0;\r
+    i = (pck / 1000) * time_ms;\r
+    i = i / 4;    \r
+    while(i--);\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Wait time in us\r
+//------------------------------------------------------------------------------\r
+// not precise, depends on the compiler and on the options\r
+static void WaitTimeInUs(unsigned int pck, unsigned int time_us)\r
+{\r
+    volatile unsigned int i = 0;\r
+    i = (pck / 1000000) * time_us;  \r
+    i = i / 4;    \r
+    while(i--);\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+//         Global functions\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+/// Return 1 if the slow clock is 32k\r
+//------------------------------------------------------------------------------\r
+unsigned char SLCK_Is32k(void)\r
+{\r
+    return ((*AT91C_SYS_SLCKSEL & AT91C_SLCKSEL_OSCSEL) != 0);\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Configure the 32kHz oscillator for the slow clock\r
+//------------------------------------------------------------------------------\r
+void SLCK_RCto32k(void)\r
+{\r
+    // Check that the master clock has a different source than slow clock. If no,\r
+    if( (AT91C_BASE_PMC->PMC_MCKR & AT91C_PMC_CSS) == 0)\r
+    {\r
+        TRACE_WARNING("The master clock use the slow clock. " \\r
+            "Not possible to change Slow clock\n\r");       \r
+        return;\r
+    }\r
+\r
+    // Check that the slow clock source is RC\r
+    if( SLCK_Is32k() )\r
+    {\r
+        TRACE_WARNING("The slow clock is already the external 32.768kHz crystal\n\r");             \r
+        return;\r
+    }    \r
+    \r
+    // Enable the 32,768 Hz oscillator by setting the bit OSC32EN to 1.\r
+    *AT91C_SYS_SLCKSEL |= AT91C_SLCKSEL_OSC32EN;\r
+    \r
+    // Wait 32,768 Hz Startup Time for clock stabilization (software loop).    \r
+    WaitTimeInMs(BOARD_MCK*2, T_ST_SLCK_32K_IN_MS);\r
+    \r
+    // Switch from internal RC to 32,768 Hz oscillator by setting the bit OSCSEL to 1.\r
+    *AT91C_SYS_SLCKSEL |= AT91C_SLCKSEL_OSCSEL;    \r
+    \r
+    // Wait 5 slow clock cycles for internal resynchronization.   \r
+    WaitTimeInUs(BOARD_MCK*2, TIME_5_CYCLES_32K_IN_US);     \r
+    \r
+    // Disable the RC oscillator by setting the bit RCEN to 0.    \r
+    *AT91C_SYS_SLCKSEL &= (0xFFFFFFFF ^ AT91C_SLCKSEL_RCEN);\r
+    \r
+    TRACE_INFO("The slow clock is now the external 32.768kHz crystal\n\r");    \r
+}\r
+\r
+\r
+//------------------------------------------------------------------------------\r
+/// Configure the RC oscillator for the slow clock\r
+//------------------------------------------------------------------------------\r
+void SLCK_32ktoRC(void)\r
+{\r
+    // Check that the master clock has a different source than slow clock.\r
+    if( (AT91C_BASE_PMC->PMC_MCKR & AT91C_PMC_CSS) == 0)\r
+    {\r
+        TRACE_WARNING("The master clock use the slow clock. " \\r
+            "Not possible to change Slow clock\n\r");             \r
+        return;\r
+    }\r
+    \r
+    // Check that the slow clock source is RC\r
+    if( !SLCK_Is32k() )\r
+    {\r
+        TRACE_WARNING("The slow clock is already the internal RC oscillator\n\r");       \r
+        return;\r
+    }        \r
+    \r
+    // Enable the internal RC oscillator by setting the bit RCEN to 1\r
+    *AT91C_SYS_SLCKSEL |= AT91C_SLCKSEL_RCEN;\r
+    \r
+    // Wait internal RC Startup Time for clock stabilization (software loop).\r
+    WaitTimeInUs(BOARD_MCK*2, T_ST_SLCK_RC_IN_US);\r
+    \r
+    // Switch from 32768 Hz oscillator to internal RC by setting the bit OSCSEL to 0.\r
+    *AT91C_SYS_SLCKSEL &= (0xFFFFFFFF ^ AT91C_SLCKSEL_OSCSEL);\r
+    \r
+    // Wait 5 slow clock cycles for internal resynchronization.\r
+    WaitTimeInUs(BOARD_MCK*2, TIME_5_CYCLES_RC_IN_US);  \r
+    \r
+    // Disable the 32768 Hz oscillator by setting the bit OSC32EN to 0.   \r
+    *AT91C_SYS_SLCKSEL &= (0xFFFFFFFF ^ AT91C_SLCKSEL_OSC32EN);\r
+    \r
+    TRACE_INFO("The slow clock is now the internal RC oscillator\n\r");      \r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// by pass the 32kHz oscillator\r
+//------------------------------------------------------------------------------\r
+void SLCK_bypass32Kosc(void)\r
+{\r
+    // Enable the bypass path OSC32BYP bit set to 1\r
+    *AT91C_SYS_SLCKSEL |= AT91C_SLCKSEL_OSC32BYP;\r
+  \r
+    // Disable the 32,768 Hz oscillator by setting the bit OSC32EN to 0\r
+    *AT91C_SYS_SLCKSEL &= (0xFFFFFFFF ^ AT91C_SLCKSEL_OSC32EN);     \r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// set Slow Clock Mode\r
+//------------------------------------------------------------------------------\r
+#define TIMEOUT             10000000\r
+void SLCK_UtilSetSlowClockMode(unsigned int timeInSlowClockMode)\r
+{\r
+    unsigned int oldPll;\r
+    unsigned int oldMck;  \r
+    unsigned int timeout = 0;  \r
+    \r
+    // Save previous values for PLL A and Master Clock configuration\r
+    oldPll = AT91C_BASE_CKGR->CKGR_PLLAR;\r
+    oldMck = AT91C_BASE_PMC->PMC_MCKR;\r
+     \r
+    // Slow clock is selected for Master Clock \r
+    // 32kKz / 64 = 500Hz\r
+    // PCK = 500Hz, MCK = 250 MHz\r
+    AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_CSS_SLOW_CLK | AT91C_PMC_PRES_CLK_64 | AT91C_PMC_MDIV_2;\r
+    timeout = 0;\r
+    while ( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY) && timeout++ < TIMEOUT);\r
+      \r
+    // Stop PLL A\r
+    // MULA: PLL A Multiplier 0 = The PLL A is deactivated.\r
+    AT91C_BASE_CKGR->CKGR_PLLAR = 0x00003f00; \r
+   \r
+    // Stop Main Oscillator\r
+    AT91C_BASE_CKGR->CKGR_MOR = AT91C_BASE_CKGR->CKGR_MOR & (~AT91C_CKGR_MOSCEN);  \r
+    \r
+    // Wait a while. The clock is at 500Hz...\r
+    while( timeInSlowClockMode-- );\r
+    // End !  \r
+    \r
+    // Restart Main Oscillator    \r
+    AT91C_BASE_CKGR->CKGR_MOR = AT91C_BASE_CKGR->CKGR_MOR | (AT91C_CKGR_OSCOUNT & (0x32<<8) );\r
+    AT91C_BASE_CKGR->CKGR_MOR = AT91C_BASE_CKGR->CKGR_MOR | (AT91C_CKGR_MOSCEN);\r
+\r
+    // Restart PLL A\r
+    AT91C_BASE_CKGR->CKGR_PLLAR = oldPll;        \r
+    timeout = 0;\r
+    while( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_LOCKA) && timeout++ < TIMEOUT);\r
+    \r
+    // Selection of Master Clock MCK (so Processor Clock PCK)\r
+    AT91C_BASE_PMC->PMC_MCKR = oldMck;  \r
+    timeout = 0;\r
+    while( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY) && timeout++ < TIMEOUT);    \r
+        \r
+    // Reconfigure DBGU\r
+    TRACE_CONFIGURE(DBGU_STANDARD, 115200, BOARD_MCK);                 \r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// get the slow clock frequency\r
+//------------------------------------------------------------------------------\r
+unsigned int SLCK_UtilGetFreq(void)\r
+{\r
+    unsigned int freq = 0;\r
+    \r
+    SLCK_UtilSetSlowClockMode(0);\r
+    \r
+    if(AT91C_BASE_PMC->PMC_MCFR & (1<<16)) {\r
+        freq = BOARD_MAINOSC / (AT91C_BASE_PMC->PMC_MCFR & 0x0000FFFF);\r
+        freq *= 16;        \r
+    }\r
+    return freq;\r
+}\r
+\r
+#endif //#if defined(at91cap9)
\ No newline at end of file

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/slck/slck.h b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/slck/slck.h
new file mode 100644 (file)
index 0000000..5814492
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/slck/slck.h
@@ -0,0 +1,49 @@
+/* ----------------------------------------------------------------------------\r
+ *         ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+#ifndef SLCK_H\r
+#define SLCK_H\r
+\r
+//------------------------------------------------------------------------------\r
+//         Global functions\r
+//------------------------------------------------------------------------------\r
+\r
+extern unsigned char SLCK_Is32k(void);\r
+\r
+extern void SLCK_RCto32k(void);\r
+\r
+extern void SLCK_32ktoRC(void);\r
+\r
+extern void SLCK_bypass32Kosc(void);\r
+\r
+extern void SLCK_UtilSetSlowClockMode(unsigned int timeInSlowClockMode);\r
+\r
+extern unsigned int SLCK_UtilGetFreq(void);\r
+\r
+#endif //#ifndef SLCK_H\r

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/spi/spi.c b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/spi/spi.c
new file mode 100644 (file)
index 0000000..98b9e9d
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/spi/spi.c
@@ -0,0 +1,192 @@
+/* ----------------------------------------------------------------------------\r
+ *         ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+//------------------------------------------------------------------------------\r
+//         Headers\r
+//------------------------------------------------------------------------------\r
+\r
+#include "spi.h"\r
+\r
+//------------------------------------------------------------------------------\r
+//         Exported functions\r
+//------------------------------------------------------------------------------\r
+//------------------------------------------------------------------------------\r
+/// Enables a SPI peripheral\r
+/// \param spi  Pointer to an AT91S_SPI instance.\r
+//------------------------------------------------------------------------------\r
+void SPI_Enable(AT91S_SPI *spi)\r
+{\r
+    spi->SPI_CR = AT91C_SPI_SPIEN;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Disables a SPI peripheral.\r
+/// \param spi  Pointer to an AT91S_SPI instance.\r
+//------------------------------------------------------------------------------\r
+void SPI_Disable(AT91S_SPI *spi)\r
+{\r
+    spi->SPI_CR = AT91C_SPI_SPIDIS;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Configures a SPI peripheral as specified. The configuration can be computed\r
+/// using several macros (see "SPI configuration macros") and the constants\r
+/// defined in LibV3 (AT91C_SPI_*).\r
+/// \param spi  Pointer to an AT91S_SPI instance.\r
+/// \param id  Peripheral ID of the SPI.\r
+/// \param configuration  Value of the SPI configuration register.\r
+//------------------------------------------------------------------------------\r
+void SPI_Configure(AT91S_SPI *spi,\r
+                          unsigned int id,\r
+                          unsigned int configuration)\r
+{\r
+    AT91C_BASE_PMC->PMC_PCER = 1 << id;\r
+    spi->SPI_CR = AT91C_SPI_SPIDIS;\r
+    // Execute a software reset of the SPI twice\r
+    spi->SPI_CR = AT91C_SPI_SWRST;\r
+    spi->SPI_CR = AT91C_SPI_SWRST;\r
+    spi->SPI_MR = configuration;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Configures a chip select of a SPI peripheral. The chip select configuration\r
+/// is computed using the definition provided by the LibV3 (AT91C_SPI_*).\r
+/// \param spi  Pointer to an AT91S_SPI instance.\r
+/// \param npcs  Chip select to configure (1, 2, 3 or 4).\r
+/// \param configuration  Desired chip select configuration.\r
+//------------------------------------------------------------------------------\r
+void SPI_ConfigureNPCS(AT91S_SPI *spi,\r
+                              unsigned int npcs,\r
+                              unsigned int configuration)\r
+{\r
+    spi->SPI_CSR[npcs] = configuration;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Sends data through a SPI peripheral. If the SPI is configured to use a fixed\r
+/// peripheral select, the npcs value is meaningless. Otherwise, it identifies\r
+/// the component which shall be addressed.\r
+/// \param spi  Pointer to an AT91S_SPI instance.\r
+/// \param npcs  Chip select of the component to address (1, 2, 3 or 4).\r
+/// \param data  Word of data to send.\r
+//------------------------------------------------------------------------------\r
+void SPI_Write(AT91S_SPI *spi, unsigned int npcs, unsigned short data)\r
+{\r
+    // Discard contents of RDR register\r
+    //volatile unsigned int discard = spi->SPI_RDR;\r
+\r
+    // Send data\r
+    while ((spi->SPI_SR & AT91C_SPI_TXEMPTY) == 0);\r
+    spi->SPI_TDR = data | SPI_PCS(npcs);\r
+    while ((spi->SPI_SR & AT91C_SPI_TDRE) == 0);\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Sends the contents of buffer through a SPI peripheral, using the PDC to\r
+/// take care of the transfer.\r
+/// \param spi  Pointer to an AT91S_SPI instance.\r
+/// \param buffer  Data buffer to send.\r
+/// \param length  Length of the data buffer.\r
+//------------------------------------------------------------------------------\r
+unsigned char SPI_WriteBuffer(AT91S_SPI *spi,\r
+                                     void *buffer,\r
+                                     unsigned int length)\r
+{\r
+    // Check if first bank is free\r
+    if (spi->SPI_TCR == 0) {\r
+\r
+        spi->SPI_TPR = (unsigned int) buffer;\r
+        spi->SPI_TCR = length;\r
+        spi->SPI_PTCR = AT91C_PDC_TXTEN;\r
+        return 1;\r
+    }\r
+    // Check if second bank is free\r
+    else if (spi->SPI_TNCR == 0) {\r
+\r
+        spi->SPI_TNPR = (unsigned int) buffer;\r
+        spi->SPI_TNCR = length;\r
+        return 1;\r
+    }\r
+      \r
+    // No free banks\r
+    return 0;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Returns 1 if there is no pending write operation on the SPI; otherwise\r
+/// returns 0.\r
+/// \param pSpi  Pointer to an AT91S_SPI instance.\r
+//------------------------------------------------------------------------------\r
+unsigned char SPI_IsFinished(AT91S_SPI *pSpi)\r
+{\r
+    return ((pSpi->SPI_SR & AT91C_SPI_TXEMPTY) != 0);\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Reads and returns the last word of data received by a SPI peripheral. This\r
+/// method must be called after a successful SPI_Write call.\r
+/// \param spi  Pointer to an AT91S_SPI instance.\r
+//------------------------------------------------------------------------------\r
+unsigned short SPI_Read(AT91S_SPI *spi)\r
+{\r
+    while ((spi->SPI_SR & AT91C_SPI_RDRF) == 0);\r
+    return spi->SPI_RDR & 0xFFFF;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Reads data from a SPI peripheral until the provided buffer is filled. This\r
+/// method does NOT need to be called after SPI_Write or SPI_WriteBuffer.\r
+/// \param spi  Pointer to an AT91S_SPI instance.\r
+/// \param buffer  Data buffer to store incoming bytes.\r
+/// \param length  Length in bytes of the data buffer.\r
+//------------------------------------------------------------------------------\r
+unsigned char SPI_ReadBuffer(AT91S_SPI *spi,\r
+                                    void *buffer,\r
+                                    unsigned int length)\r
+{\r
+    // Check if the first bank is free\r
+    if (spi->SPI_RCR == 0) {\r
+\r
+        spi->SPI_RPR = (unsigned int) buffer;\r
+        spi->SPI_RCR = length;\r
+        spi->SPI_PTCR = AT91C_PDC_RXTEN;\r
+        return 1;\r
+    }\r
+    // Check if second bank is free\r
+    else if (spi->SPI_RNCR == 0) {\r
+\r
+        spi->SPI_RNPR = (unsigned int) buffer;\r
+        spi->SPI_RNCR = length;\r
+        return 1;\r
+    }\r
+\r
+    // No free bank\r
+    return 0;\r
+}\r
+\r

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/spi/spi.h b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/spi/spi.h
new file mode 100644 (file)
index 0000000..f4e2557
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/spi/spi.h
@@ -0,0 +1,114 @@
+/* ----------------------------------------------------------------------------\r
+ *         ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+//------------------------------------------------------------------------------\r
+/// \dir\r
+/// !Purpose\r
+/// \r
+/// Definitions for SPI peripheral usage.\r
+///\r
+/// !Usage\r
+///\r
+/// -# Enable the SPI pins required by the application (see pio.h).\r
+/// -# Configure the SPI using the SPI_Configure function. This enables the\r
+///    peripheral clock. The mode register is loaded with the given value.\r
+/// -# Configure all the necessary chip selects with SPI_ConfigureNPCS.\r
+/// -# Enable the SPI by calling SPI_Enable.\r
+/// -# Send/receive data using SPI_Write and SPI_Read. Note that SPI_Read\r
+///    must be called after SPI_Write to retrieve the last value read.\r
+/// -# Send/receive data using the PDC with the SPI_WriteBuffer and\r
+///    SPI_ReadBuffer functions.\r
+/// -# Disable the SPI by calling SPI_Disable.\r
+//------------------------------------------------------------------------------\r
+\r
+#ifndef SPI_H\r
+#define SPI_H\r
+\r
+//------------------------------------------------------------------------------\r
+//         Headers\r
+//------------------------------------------------------------------------------\r
+\r
+#include <board.h>\r
+\r
+//------------------------------------------------------------------------------\r
+//         Definitions\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+/// \page "SPI configuration macros"\r
+/// This page lists several macros which should be used when configuring a SPI\r
+/// peripheral.\r
+/// \r
+/// !Macros\r
+/// - SPI_PCS\r
+/// - SPI_SCBR\r
+/// - SPI_DLYBS\r
+/// - SPI_DLYBCT\r
+\r
+/// Calculate the PCS field value given the chip select NPCS value\r
+#define SPI_PCS(npcs)       ((~(1 << npcs) & 0xF) << 16)\r
+\r
+/// Calculates the value of the CSR SCBR field given the baudrate and MCK.\r
+#define SPI_SCBR(baudrate, masterClock) \\r
+            ((unsigned int) (masterClock / baudrate) << 8)\r
+\r
+/// Calculates the value of the CSR DLYBS field given the desired delay (in ns)\r
+#define SPI_DLYBS(delay, masterClock) \\r
+            ((unsigned int) (((masterClock / 1000000) * delay) / 1000) << 16)\r
+\r
+/// Calculates the value of the CSR DLYBCT field given the desired delay (in ns)\r
+#define SPI_DLYBCT(delay, masterClock) \\r
+            ((unsigned int) (((masterClock / 1000000) * delay) / 32000) << 24)\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+//         Exported functions\r
+//------------------------------------------------------------------------------\r
+extern void SPI_Enable(AT91S_SPI *spi);\r
+extern void SPI_Disable(AT91S_SPI *spi);\r
+extern void SPI_Configure(AT91S_SPI *spi,\r
+                                 unsigned int id,\r
+                                 unsigned int configuration);\r
+extern void SPI_ConfigureNPCS(AT91S_SPI *spi,\r
+                                     unsigned int npcs,\r
+                                     unsigned int configuration);\r
+extern void SPI_Write(AT91S_SPI *spi, unsigned int npcs, unsigned short data);\r
+extern unsigned char SPI_WriteBuffer(AT91S_SPI *spi,\r
+                                            void *buffer,\r
+                                            unsigned int length);\r
+\r
+extern unsigned char SPI_IsFinished(AT91S_SPI *pSpi);\r
+\r
+extern unsigned short SPI_Read(AT91S_SPI *spi);\r
+extern unsigned char SPI_ReadBuffer(AT91S_SPI *spi,\r
+                                           void *buffer,\r
+                                           unsigned int length);\r
+\r
+#endif //#ifndef SPI_H\r
+\r

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/ssc/ssc.c b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/ssc/ssc.c
new file mode 100644 (file)
index 0000000..c0cb000
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/ssc/ssc.c
@@ -0,0 +1,243 @@
+/* ----------------------------------------------------------------------------\r
+ *         ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+//------------------------------------------------------------------------------\r
+//         Headers\r
+//------------------------------------------------------------------------------\r
+\r
+#include "ssc.h"\r
+#include <utility/trace.h>\r
+\r
+//------------------------------------------------------------------------------\r
+//         Exported functions\r
+//------------------------------------------------------------------------------\r
+//------------------------------------------------------------------------------\r
+/// Configures a SSC peripheral. If the divided clock is not used, the master\r
+/// clock frequency can be set to 0.\r
+/// \note The emitter and transmitter are disabled by this function.\r
+/// \param ssc  Pointer to an AT91S_SSC instance.\r
+/// \param id  Peripheral ID of the SSC.\r
+//------------------------------------------------------------------------------\r
+void SSC_Configure(AT91S_SSC *ssc,\r
+                          unsigned int id,\r
+                          unsigned int bitRate,\r
+                          unsigned int masterClock)\r
+{\r
+    // Enable SSC peripheral clock\r
+    AT91C_BASE_PMC->PMC_PCER = 1 << id;\r
+\r
+    // Reset, disable receiver & transmitter\r
+    ssc->SSC_CR = AT91C_SSC_RXDIS | AT91C_SSC_TXDIS | AT91C_SSC_SWRST;\r
+    ssc->SSC_PTCR = AT91C_PDC_RXTDIS | AT91C_PDC_TXTDIS;\r
+\r
+    // Configure clock frequency\r
+    if (bitRate != 0) {\r
+    \r
+        ssc->SSC_CMR = masterClock / (2 * bitRate);\r
+    }\r
+    else {\r
+\r
+        ssc->SSC_CMR = 0;\r
+    }\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Configures the transmitter of a SSC peripheral. Several macros can be used\r
+/// to compute the values of the Transmit Clock Mode Register (TCMR) and the\r
+/// Transmit Frame Mode Register (TFMR) (see "SSC configuration macros").\r
+/// \param ssc  Pointer to a AT91S_SSC instance.\r
+/// \param tcmr  Transmit Clock Mode Register value.\r
+/// \param tfmr  Transmit Frame Mode Register value.\r
+//------------------------------------------------------------------------------\r
+void SSC_ConfigureTransmitter(AT91S_SSC *ssc,\r
+                                     unsigned int tcmr,\r
+                                     unsigned int tfmr)\r
+{\r
+    ssc->SSC_TCMR = tcmr;\r
+    ssc->SSC_TFMR = tfmr;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Configures the receiver of a SSC peripheral. Several macros can be used\r
+/// to compute the values of the Receive Clock Mode Register (TCMR) and the\r
+/// Receive Frame Mode Register (TFMR) (see "SSC configuration macros").\r
+/// \param ssc  Pointer to a AT91S_SSC instance.\r
+/// \param rcmr  Receive Clock Mode Register value.\r
+/// \param rfmr  Receive Frame Mode Register value.\r
+//------------------------------------------------------------------------------\r
+void SSC_ConfigureReceiver(AT91S_SSC *ssc,\r
+                                  unsigned int rcmr,\r
+                                  unsigned int rfmr)\r
+{\r
+    ssc->SSC_RCMR = rcmr;\r
+    ssc->SSC_RFMR = rfmr;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Enables the transmitter of a SSC peripheral.\r
+/// \param ssc  Pointer to an AT91S_SSC instance.\r
+//------------------------------------------------------------------------------\r
+void SSC_EnableTransmitter(AT91S_SSC *ssc)\r
+{\r
+    ssc->SSC_CR = AT91C_SSC_TXEN;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Disables the transmitter of a SSC peripheral.\r
+/// \param ssc  Pointer to an AT91S_SSC instance.\r
+//------------------------------------------------------------------------------\r
+void SSC_DisableTransmitter(AT91S_SSC *ssc)\r
+{\r
+    ssc->SSC_CR = AT91C_SSC_TXDIS;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Enables the receiver of a SSC peripheral.\r
+/// \param ssc  Pointer to an AT91S_SSC instance.\r
+//------------------------------------------------------------------------------\r
+void SSC_EnableReceiver(AT91S_SSC *ssc)\r
+{\r
+    ssc->SSC_CR = AT91C_SSC_RXEN;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Disables the receiver of a SSC peripheral.\r
+/// \param ssc  Pointer to an AT91S_SSC instance.\r
+//------------------------------------------------------------------------------\r
+void SSC_DisableReceiver(AT91S_SSC *ssc)\r
+{\r
+    ssc->SSC_CR = AT91C_SSC_RXDIS;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Enables one or more interrupt sources of a SSC peripheral.\r
+/// \param ssc  Pointer to an AT91S_SSC instance.\r
+/// \param sources  Interrupt sources to enable.\r
+//------------------------------------------------------------------------------\r
+void SSC_EnableInterrupts(AT91S_SSC *ssc, unsigned int sources)\r
+{\r
+    ssc->SSC_IER = sources;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Disables one or more interrupt sources of a SSC peripheral.\r
+/// \param ssc  Pointer to an AT91S_SSC instance.\r
+/// \param sources  Interrupt source to disable.\r
+//------------------------------------------------------------------------------\r
+void SSC_DisableInterrupts(AT91S_SSC *ssc, unsigned int sources)\r
+{\r
+    ssc->SSC_IDR = sources;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Sends one data frame through a SSC peripheral. If another frame is currently\r
+/// being sent, this function waits for the previous transfer to complete.\r
+/// \param ssc  Pointer to an AT91S_SSC instance.\r
+/// \param frame  Data frame to send.\r
+//------------------------------------------------------------------------------\r
+void SSC_Write(AT91S_SSC *ssc, unsigned int frame)\r
+{\r
+    while ((ssc->SSC_SR & AT91C_SSC_TXRDY) == 0);\r
+    ssc->SSC_THR = frame;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Sends the contents of a data buffer a SSC peripheral, using the PDC. Returns\r
+/// true if the buffer has been queued for transmission; otherwise returns\r
+/// false.\r
+/// \param ssc  Pointer to an AT91S_SSC instance.\r
+/// \param buffer  Data buffer to send.\r
+/// \param length  Size of the data buffer.\r
+//------------------------------------------------------------------------------\r
+unsigned char SSC_WriteBuffer(AT91S_SSC *ssc,\r
+                                     void *buffer,\r
+                                     unsigned int length)\r
+{\r
+    // Check if first bank is free\r
+    if (ssc->SSC_TCR == 0) {\r
+\r
+        ssc->SSC_TPR = (unsigned int) buffer;\r
+        ssc->SSC_TCR = length;\r
+        ssc->SSC_PTCR = AT91C_PDC_TXTEN;\r
+        return 1;\r
+    }\r
+    // Check if second bank is free\r
+    else if (ssc->SSC_TNCR == 0) {\r
+\r
+        ssc->SSC_TNPR = (unsigned int) buffer;\r
+        ssc->SSC_TNCR = length;\r
+        return 1;\r
+    }\r
+      \r
+    // No free banks\r
+    return 0;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Waits until one frame is received on a SSC peripheral, and returns it.\r
+/// \param ssc  Pointer to an AT91S_SSC instance.\r
+//------------------------------------------------------------------------------\r
+unsigned int SSC_Read(AT91S_SSC *ssc)\r
+{\r
+    while ((ssc->SSC_SR & AT91C_SSC_RXRDY) == 0);\r
+    return ssc->SSC_RHR;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Reads data coming from a SSC peripheral receiver and stores it into the\r
+/// provided buffer. Returns true if the buffer has been queued for reception;\r
+/// otherwise returns false.\r
+/// \param ssc  Pointer to an AT91S_SSC instance.\r
+/// \param buffer  Data buffer used for reception.\r
+/// \param length  Size in bytes of the data buffer.\r
+//------------------------------------------------------------------------------\r
+unsigned char SSC_ReadBuffer(AT91S_SSC *ssc,\r
+                                    void *buffer,\r
+                                    unsigned int length)\r
+{\r
+    // Check if the first bank is free\r
+    if (ssc->SSC_RCR == 0) {\r
+\r
+        ssc->SSC_RPR = (unsigned int) buffer;\r
+        ssc->SSC_RCR = length;\r
+        ssc->SSC_PTCR = AT91C_PDC_RXTEN;\r
+        return 1;\r
+    }\r
+    // Check if second bank is free\r
+    else if (ssc->SSC_RNCR == 0) {\r
+\r
+        ssc->SSC_RNPR = (unsigned int) buffer;\r
+        ssc->SSC_RNCR = length;\r
+        return 1;\r
+    }\r
+\r
+    // No free bank\r
+    return 0;\r
+}\r
+\r

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/ssc/ssc.h b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/ssc/ssc.h
new file mode 100644 (file)
index 0000000..330fa18
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/ssc/ssc.h
@@ -0,0 +1,132 @@
+/* ----------------------------------------------------------------------------\r
+ *         ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+//------------------------------------------------------------------------------\r
+/// \dir\r
+/// !Purpose\r
+///\r
+/// Set of functions and definition for using a SSC peripheral.\r
+///\r
+/// !Usage\r
+///\r
+/// -# Enable the SSC interface pins (see pio & board.h).\r
+/// -# Configure the SSC to operate at a specific frequency by calling\r
+///    SSC_Configure(). This function enables the peripheral clock of the SSC,\r
+///    but not its PIOs.\r
+/// -# Configure the transmitter and/or the receiver using the\r
+///    SSC_ConfigureTransmitter() and SSC_ConfigureEmitter() functions.\r
+/// -# Enable the PIOs or the transmitter and/or the received.\r
+/// -# Enable the transmitter and/or the receiver using SSC_EnableTransmitter()\r
+///    and SSC_EnableReceiver()\r
+/// -# Send data through the transmitter using SSC_Write() and SSC_WriteBuffer()\r
+/// -# Receive data from the receiver using SSC_Read() and SSC_ReadBuffer()\r
+/// -# Disable the transmitter and/or the receiver using SSC_DisableTransmitter()\r
+///    and SSC_DisableReceiver()\r
+//------------------------------------------------------------------------------\r
+\r
+#ifndef SSC_H\r
+#define SSC_H\r
+\r
+//------------------------------------------------------------------------------\r
+//         Headers\r
+//------------------------------------------------------------------------------\r
+\r
+#include <board.h>\r
+\r
+//------------------------------------------------------------------------------\r
+//         Definitions\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+/// \page "SSC configuration macros"\r
+/// This page lists several macros which are used when configuring a SSC\r
+/// peripheral.\r
+/// \r
+/// !Macros\r
+/// - SSC_STTDLY\r
+/// - SSC_PERIOD\r
+/// - SSC_DATLEN\r
+/// - SSC_DATNB\r
+/// - SSC_FSLEN\r
+\r
+/// Calculates the value of the STTDLY field given the number of clock cycles\r
+/// before the first bit of a new frame is transmitted.\r
+#define SSC_STTDLY(bits)        (bits << 16)\r
+\r
+/// Calculates the value of the PERIOD field of the Transmit Clock Mode Register\r
+/// of an SSC interface, given the desired clock divider.\r
+#define SSC_PERIOD(divider)     (((divider / 2) - 1) << 24)\r
+\r
+/// Calculates the value of the DATLEN field of the Transmit Frame Mode Register\r
+/// of an SSC interface, given the number of bits in one sample.\r
+#define SSC_DATLEN(bits)        (bits - 1)\r
+\r
+/// Calculates the value of the DATNB field of the Transmit Frame Mode Register\r
+/// of an SSC interface, given the number of samples in one frame.\r
+#define SSC_DATNB(samples)      ((samples -1) << 8)\r
+\r
+/// Calculates the value of the FSLEN field of the Transmit Frame Mode Register\r
+/// of an SSC interface, given the number of transmit clock periods that the \r
+/// frame sync signal should take.\r
+#define SSC_FSLEN(periods)      ((periods - 1) << 16)\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+//         Exported functions\r
+//------------------------------------------------------------------------------\r
+extern void SSC_Configure(AT91S_SSC *ssc,\r
+                                 unsigned int id,\r
+                                 unsigned int bitRate,\r
+                                 unsigned int masterClock);\r
+extern void SSC_ConfigureTransmitter(AT91S_SSC *ssc,\r
+                                            unsigned int tcmr,\r
+                                            unsigned int tfmr);\r
+extern void SSC_ConfigureReceiver(AT91S_SSC *ssc,\r
+                                         unsigned int rcmr,\r
+                                         unsigned int rfmr);\r
+\r
+extern void SSC_EnableTransmitter(AT91S_SSC *ssc);\r
+extern void SSC_DisableTransmitter(AT91S_SSC *ssc);\r
+extern void SSC_EnableReceiver(AT91S_SSC *ssc);\r
+extern void SSC_DisableReceiver(AT91S_SSC *ssc);\r
+\r
+extern void SSC_EnableInterrupts(AT91S_SSC *ssc, unsigned int sources);\r
+extern void SSC_DisableInterrupts(AT91S_SSC *ssc, unsigned int sources);\r
+\r
+extern void SSC_Write(AT91S_SSC *ssc, unsigned int frame);\r
+extern unsigned char SSC_WriteBuffer(AT91S_SSC *ssc,\r
+                                            void *buffer,\r
+                                            unsigned int length);\r
+extern unsigned int SSC_Read(AT91S_SSC *ssc);\r
+extern unsigned char SSC_ReadBuffer(AT91S_SSC *ssc,\r
+                                           void *buffer,\r
+                                           unsigned int length);\r
+\r
+#endif //#ifndef SSC_H\r
+\r

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/supc/supc.c b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/supc/supc.c
new file mode 100644 (file)
index 0000000..b63194c
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/supc/supc.c
@@ -0,0 +1,223 @@
+/* ----------------------------------------------------------------------------\r
+ *         ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+//------------------------------------------------------------------------------\r
+//         Headers\r
+//------------------------------------------------------------------------------\r
+\r
+#include "supc.h"\r
+#include <board.h>\r
+#include <utility/assert.h>\r
+\r
+//------------------------------------------------------------------------------\r
+//         Local definitions\r
+//------------------------------------------------------------------------------\r
+\r
+/// Key value for the SUPC_MR register.\r
+#define SUPC_KEY            ((unsigned int) (0xA5 << 24))\r
+\r
+//------------------------------------------------------------------------------\r
+//         Global functions\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+/// Enables the SLCD power supply.\r
+/// \param internal  If 1, the power supply is configured as internal; otherwise\r
+///                  it is set at external.\r
+//------------------------------------------------------------------------------\r
+void SUPC_EnableSlcd(unsigned char internal)\r
+{\r
+    if (internal) {\r
+\r
+         AT91C_BASE_SUPC->SUPC_MR = SUPC_KEY | (AT91C_BASE_SUPC->SUPC_MR & ~AT91C_SUPC_LCDMODE) | AT91C_SUPC_LCDMODE_INTERNAL;\r
+    }\r
+    else {\r
+\r
+        AT91C_BASE_SUPC->SUPC_MR = SUPC_KEY | (AT91C_BASE_SUPC->SUPC_MR & ~AT91C_SUPC_LCDMODE) | AT91C_SUPC_LCDMODE_EXTERNAL;\r
+    }\r
+    while ((AT91C_BASE_SUPC->SUPC_SR & AT91C_SUPC_LCDS) != AT91C_SUPC_LCDS);\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Disables the SLCD power supply.\r
+//------------------------------------------------------------------------------\r
+void SUPC_DisableSlcd(void)\r
+{\r
+    AT91C_BASE_SUPC->SUPC_MR = SUPC_KEY | (AT91C_BASE_SUPC->SUPC_MR & ~AT91C_SUPC_LCDMODE);\r
+    while ((AT91C_BASE_SUPC->SUPC_SR & AT91C_SUPC_LCDS) == AT91C_SUPC_LCDS);\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Sets the output voltage of the SLCD charge pump.\r
+/// \param voltage  Output voltage.\r
+//------------------------------------------------------------------------------\r
+void SUPC_SetSlcdVoltage(unsigned int voltage)\r
+{\r
+    SANITY_CHECK((voltage & ~AT91C_SUPC_LCDOUT) == 0);\r
+    AT91C_BASE_SUPC->SUPC_MR = SUPC_KEY | (AT91C_BASE_SUPC->SUPC_MR & ~AT91C_SUPC_LCDOUT) | voltage;\r
+}\r
+\r
+#if !defined(__ICCARM__)\r
+__attribute__ ((section (".ramfunc"))) // GCC\r
+#endif\r
+//------------------------------------------------------------------------------\r
+/// Enables the flash power supply with the given wake-up setting.\r
+/// \param time  Wake-up time.\r
+//------------------------------------------------------------------------------\r
+void SUPC_EnableFlash(unsigned int time)\r
+{\r
+    AT91C_BASE_SUPC->SUPC_FWUTR = time;\r
+    AT91C_BASE_SUPC->SUPC_MR = SUPC_KEY | AT91C_BASE_SUPC->SUPC_MR | AT91C_SUPC_FLASHON;\r
+    while ((AT91C_BASE_SUPC->SUPC_SR & AT91C_SUPC_FLASHS) != AT91C_SUPC_FLASHS);\r
+}\r
+\r
+#if !defined(__ICCARM__)\r
+__attribute__ ((section (".ramfunc"))) // GCC\r
+#endif\r
+//------------------------------------------------------------------------------\r
+/// Disables the flash power supply.\r
+//------------------------------------------------------------------------------\r
+void SUPC_DisableFlash(void)\r
+{\r
+    AT91C_BASE_SUPC->SUPC_MR = SUPC_KEY | (AT91C_BASE_SUPC->SUPC_MR & ~AT91C_SUPC_FLASHON);\r
+    while ((AT91C_BASE_SUPC->SUPC_SR & AT91C_SUPC_FLASHS) == AT91C_SUPC_FLASHS);\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Sets the voltage regulator output voltage.\r
+/// \param voltage  Voltage to set.\r
+//------------------------------------------------------------------------------\r
+void SUPC_SetVoltageOutput(unsigned int voltage)\r
+{\r
+    SANITY_CHECK((voltage & ~AT91C_SUPC_VRVDD) == 0);\r
+    AT91C_BASE_SUPC->SUPC_MR = SUPC_KEY | (AT91C_BASE_SUPC->SUPC_MR & ~AT91C_SUPC_VRVDD) | voltage;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Puts the voltage regulator in deep mode.\r
+//------------------------------------------------------------------------------\r
+void SUPC_EnableDeepMode(void)\r
+{\r
+    AT91C_BASE_SUPC->SUPC_MR = SUPC_KEY | AT91C_BASE_SUPC->SUPC_MR | AT91C_SUPC_VRDEEP;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Puts the voltage regulator in normal mode.\r
+//------------------------------------------------------------------------------\r
+void SUPC_DisableDeepMode(void)\r
+{\r
+    AT91C_BASE_SUPC->SUPC_MR = SUPC_KEY | (AT91C_BASE_SUPC->SUPC_MR & ~AT91C_SUPC_VRDEEP);\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Enables the backup SRAM power supply, so its data is saved while the device\r
+/// is in backup mode.\r
+//-----------------------------------------------------------------------------\r
+void SUPC_EnableSram(void)\r
+{\r
+    AT91C_BASE_SUPC->SUPC_MR = SUPC_KEY | AT91C_BASE_SUPC->SUPC_MR | AT91C_SUPC_SRAMON;\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Disables the backup SRAM power supply.\r
+//-----------------------------------------------------------------------------\r
+void SUPC_DisableSram(void)\r
+{\r
+    AT91C_BASE_SUPC->SUPC_MR = SUPC_KEY | (AT91C_BASE_SUPC->SUPC_MR & ~AT91C_SUPC_SRAMON);\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Enables the RTC power supply.\r
+//-----------------------------------------------------------------------------\r
+void SUPC_EnableRtc(void)\r
+{\r
+    AT91C_BASE_SUPC->SUPC_MR = SUPC_KEY | AT91C_BASE_SUPC->SUPC_MR | AT91C_SUPC_RTCON;\r
+    while ((AT91C_BASE_SUPC->SUPC_SR & AT91C_SUPC_RTS) != AT91C_SUPC_RTS);\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Disables the RTC power supply.\r
+//-----------------------------------------------------------------------------\r
+void SUPC_DisableRtc(void)\r
+{\r
+    AT91C_BASE_SUPC->SUPC_MR = SUPC_KEY | (AT91C_BASE_SUPC->SUPC_MR & ~AT91C_SUPC_RTCON);\r
+    while ((AT91C_BASE_SUPC->SUPC_SR & AT91C_SUPC_RTS) == AT91C_SUPC_RTS);\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Sets the BOD sampling mode (or disables it).\r
+/// \param mode  BOD sampling mode.\r
+//-----------------------------------------------------------------------------\r
+void SUPC_SetBodSampling(unsigned int mode)\r
+{\r
+    SANITY_CHECK((mode & ~AT91C_SUPC_BODSMPL) == 0);\r
+    AT91C_BASE_SUPC->SUPC_BOMR &= ~AT91C_SUPC_BODSMPL;\r
+    AT91C_BASE_SUPC->SUPC_BOMR |= mode;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Disables the voltage regulator, which makes the device enter backup mode.\r
+//------------------------------------------------------------------------------\r
+void SUPC_DisableVoltageRegulator(void)\r
+{\r
+    AT91C_BASE_SUPC->SUPC_CR = SUPC_KEY | AT91C_SUPC_VROFF;\r
+    while (1);\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Shuts the device down so it enters Off mode.\r
+//------------------------------------------------------------------------------\r
+void SUPC_Shutdown(void)\r
+{\r
+    AT91C_BASE_SUPC->SUPC_CR = SUPC_KEY | AT91C_SUPC_SHDW;\r
+    while (1);\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Sets the wake-up sources when in backup mode.\r
+/// \param sources  Wake-up sources to enable.\r
+//------------------------------------------------------------------------------\r
+void SUPC_SetWakeUpSources(unsigned int sources)\r
+{\r
+    SANITY_CHECK((sources & ~0x0000000B) == 0);\r
+    AT91C_BASE_SUPC->SUPC_WUMR &= ~0x0000000B;\r
+    AT91C_BASE_SUPC->SUPC_WUMR |= sources;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Sets the wake-up inputs when in backup mode.\r
+/// \param inputs  Wake up inputs to enable.\r
+//------------------------------------------------------------------------------\r
+void SUPC_SetWakeUpInputs(unsigned int inputs)\r
+{\r
+    SANITY_CHECK((inputs & ~0xFFFF) == 0);\r
+    AT91C_BASE_SUPC->SUPC_WUIR &= ~0xFFFF;\r
+    AT91C_BASE_SUPC->SUPC_WUIR |= inputs;\r
+}\r
+\r

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/supc/supc.h b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/supc/supc.h
new file mode 100644 (file)
index 0000000..f90df93
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/supc/supc.h
@@ -0,0 +1,80 @@
+/* ----------------------------------------------------------------------------\r
+ *         ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+#ifndef SUPC_H\r
+#define SUPC_H\r
+\r
+//------------------------------------------------------------------------------\r
+//         Global functions\r
+//------------------------------------------------------------------------------\r
+\r
+extern void SUPC_EnableSlcd(unsigned char internal);\r
+\r
+extern void SUPC_DisableSlcd(void);\r
+\r
+extern void SUPC_SetSlcdVoltage(unsigned int voltage);\r
+\r
+extern\r
+#ifdef __ICCARM__\r
+__ramfunc // IAR\r
+#endif\r
+void SUPC_EnableFlash(unsigned int time);\r
+\r
+extern\r
+#ifdef __ICCARM__\r
+__ramfunc // IAR\r
+#endif\r
+void SUPC_DisableFlash(void);\r
+\r
+extern void SUPC_SetVoltageOutput(unsigned int voltage);\r
+\r
+extern void SUPC_EnableDeepMode(void);\r
+\r
+extern void SUPC_EnableSram(void);\r
+\r
+extern void SUPC_DisableSram(void);\r
+\r
+extern void SUPC_EnableRtc(void);\r
+\r
+extern void SUPC_DisableRtc(void);\r
+\r
+extern void SUPC_SetBodSampling(unsigned int mode);\r
+\r
+extern void SUPC_DisableDeepMode(void);\r
+\r
+extern void SUPC_DisableVoltageRegulator(void);\r
+\r
+extern void SUPC_Shutdown(void);\r
+\r
+extern void SUPC_SetWakeUpSources(unsigned int sources);\r
+\r
+extern void SUPC_SetWakeUpInputs(unsigned int inputs);\r
+\r
+#endif //#ifndef SUPC_H\r
+\r

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/systick/systick.c b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/systick/systick.c
new file mode 100644 (file)
index 0000000..ffd9fbf
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/systick/systick.c
@@ -0,0 +1,63 @@
+/* ----------------------------------------------------------------------------\r
+ *         ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+//------------------------------------------------------------------------------\r
+//         Headers\r
+//------------------------------------------------------------------------------\r
+\r
+#include "systick.h"\r
+\r
+//------------------------------------------------------------------------------\r
+/// Configures the SysTick in .\r
+/// \param countEnable  Enable SysTick counting.\r
+/// \param reloadValue  Value used for tick counter to reload.\r
+/// \param handler      Interrupt handler function, 0 to disable interrupt.\r
+//------------------------------------------------------------------------------\r
+void SysTick_Configure(unsigned char countEnable,\r
+                           unsigned int reloadValue,\r
+                           void( *handler )( void ))\r
+{\r
+    unsigned int intEnable = handler ? AT91C_NVIC_STICKINT : 0;\r
+\r
+    // Disable the SysTick & using core source\r
+    AT91C_BASE_NVIC->NVIC_STICKCSR = AT91C_NVIC_STICKCLKSOURCE;\r
+\r
+    // Reset the current value\r
+    AT91C_BASE_NVIC->NVIC_STICKCVR &= ~AT91C_NVIC_STICKCURRENT;\r
+\r
+    // Setup the reload value\r
+    AT91C_BASE_NVIC->NVIC_STICKRVR = reloadValue;\r
+\r
+    // Enable the SysTick\r
+    AT91C_BASE_NVIC->NVIC_STICKCSR =  AT91C_NVIC_STICKCLKSOURCE\r
+                                    | AT91C_NVIC_STICKENABLE\r
+                                    | intEnable;\r
+\r
+}\r
+\r

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/systick/systick.h b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/systick/systick.h
new file mode 100644 (file)
index 0000000..e3d8439
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/systick/systick.h
@@ -0,0 +1,68 @@
+/* ----------------------------------------------------------------------------\r
+ *         ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+//------------------------------------------------------------------------------\r
+/// \unit\r
+///\r
+/// !Purpose\r
+/// \r
+/// Methods and definitions for configuring System Tick in Cortex-M3.\r
+/// \r
+/// !Usage\r
+///\r
+/// -# Configure the System Tick with SysTick_Configure\r
+///\r
+//------------------------------------------------------------------------------\r
+\r
+#ifndef SYSTICK_H\r
+#define SYSTICK_H\r
+\r
+//------------------------------------------------------------------------------\r
+//         Headers\r
+//------------------------------------------------------------------------------\r
+\r
+#include <board.h>\r
+#include <cmsis/core_cm3.h>\r
+\r
+//------------------------------------------------------------------------------\r
+//         Definitions\r
+//------------------------------------------------------------------------------\r
+\r
+/// Vendor define it's own SysTickConfig function\r
+#define __Vendor_SysTickConfig     1\r
+\r
+//------------------------------------------------------------------------------\r
+//         Global functions\r
+//------------------------------------------------------------------------------\r
+\r
+extern void SysTick_Configure(unsigned char countEnable,\r
+                           unsigned int reloadValue,\r
+                           void( *handler )( void ));\r
+\r
+#endif //#ifndef SYSTICK_H\r

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/tc/tc.c b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/tc/tc.c
new file mode 100644 (file)
index 0000000..00e85fb
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/tc/tc.c
@@ -0,0 +1,143 @@
+/* ----------------------------------------------------------------------------\r
+ *         ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+//------------------------------------------------------------------------------\r
+//         Headers\r
+//------------------------------------------------------------------------------\r
+\r
+#include "tc.h"\r
+\r
+//------------------------------------------------------------------------------\r
+//         Global Functions\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+/// Configures a Timer Counter to operate in the given mode. Timer is stopped\r
+/// after configuration and must be restarted with TC_Start(). All the\r
+/// interrupts of the timer are also disabled.\r
+/// \param pTc  Pointer to an AT91S_TC instance.\r
+/// \param mode  Operating mode (TC_CMR value).\r
+//------------------------------------------------------------------------------\r
+void TC_Configure(AT91S_TC *pTc, unsigned int mode)\r
+{\r
+    // Disable TC clock\r
+    pTc->TC_CCR = AT91C_TC_CLKDIS;\r
+\r
+    // Disable interrupts\r
+    pTc->TC_IDR = 0xFFFFFFFF;\r
+\r
+    // Clear status register\r
+    pTc->TC_SR;\r
+\r
+    // Set mode\r
+    pTc->TC_CMR = mode;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Enables the timer clock and performs a software reset to start the counting.\r
+/// \param pTc  Pointer to an AT91S_TC instance.\r
+//------------------------------------------------------------------------------\r
+void TC_Start(AT91S_TC *pTc)\r
+{\r
+    pTc->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Disables the timer clock, stopping the counting.\r
+/// \param pTc  Pointer to an AT91S_TC instance.\r
+//------------------------------------------------------------------------------\r
+void TC_Stop(AT91S_TC *pTc)\r
+{\r
+    pTc->TC_CCR = AT91C_TC_CLKDIS;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Finds the best MCK divisor given the timer frequency and MCK. The result\r
+/// is guaranteed to satisfy the following equation:\r
+/// \pre\r
+///   (MCK / (DIV * 65536)) <= freq <= (MCK / DIV)\r
+/// \endpre\r
+/// with DIV being the highest possible value.\r
+/// \param freq  Desired timer frequency.\r
+/// \param mck  Master clock frequency.\r
+/// \param div  Divisor value.\r
+/// \param tcclks  TCCLKS field value for divisor.\r
+/// \return 1 if a proper divisor has been found; otherwise 0.\r
+//------------------------------------------------------------------------------\r
+unsigned char TC_FindMckDivisor(\r
+    unsigned int freq,\r
+    unsigned int mck,\r
+    unsigned int *div,\r
+    unsigned int *tcclks)\r
+{\r
+    const unsigned int divisors[5] = {2, 8, 32, 128,\r
+#if defined(at91sam9260) || defined(at91sam9261) || defined(at91sam9263) \\r
+    || defined(at91sam9xe) || defined(at91sam9rl64) || defined(at91cap9) \\r
+    || defined(at91sam9m10) || defined(at91sam9m11)\r
+        BOARD_MCK / 32768};\r
+#else\r
+        1024};\r
+#endif\r
+    unsigned int index = 0;\r
+\r
+    // Satisfy lower bound\r
+    while (freq < ((mck / divisors[index]) / 65536)) {\r
+\r
+        index++;\r
+\r
+        // If no divisor can be found, return 0\r
+        if (index == 5) {\r
+\r
+            return 0;\r
+        }\r
+    }\r
+\r
+    // Try to maximise DIV while satisfying upper bound\r
+    while (index < 4) {\r
+\r
+        if (freq > (mck / divisors[index + 1])) {\r
+\r
+            break;\r
+        }\r
+        index++;\r
+    }\r
+\r
+    // Store results\r
+    if (div) {\r
+\r
+        *div = divisors[index];\r
+    }\r
+    if (tcclks) {\r
+\r
+        *tcclks = index;\r
+    }\r
+\r
+    return 1;\r
+}\r
+\r

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/tc/tc.h b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/tc/tc.h
new file mode 100644 (file)
index 0000000..ea71d54
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/tc/tc.h
@@ -0,0 +1,80 @@
+/* ----------------------------------------------------------------------------\r
+ *         ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+//------------------------------------------------------------------------------\r
+/// \unit\r
+///\r
+/// !Purpose\r
+///\r
+/// API for configuring and using Timer Counter (TC) peripherals.\r
+///\r
+/// !Usage\r
+/// -# Optionally, use TC_FindMckDivisor() to let the program find the best\r
+///    TCCLKS field value automatically.\r
+/// -# Configure a Timer Counter in the desired mode using TC_Configure().\r
+/// -# Start or stop the timer clock using TC_Start() and TC_Stop().\r
+//------------------------------------------------------------------------------\r
+\r
+#ifndef TC_H\r
+#define TC_H\r
+\r
+//------------------------------------------------------------------------------\r
+//         Headers\r
+//------------------------------------------------------------------------------\r
+\r
+#include <board.h>\r
+\r
+#if defined(AT91C_ID_TC0)\r
+    // nothing to do\r
+#elif defined(AT91C_ID_TC012)\r
+    #define AT91C_ID_TC0 AT91C_ID_TC012\r
+#elif defined(AT91C_ID_TC)\r
+    #define AT91C_ID_TC0 AT91C_ID_TC\r
+#else\r
+    #error Pb define ID_TC\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+//         Global functions\r
+//------------------------------------------------------------------------------\r
+\r
+extern void TC_Configure(AT91S_TC *pTc, unsigned int mode);\r
+\r
+extern void TC_Start(AT91S_TC *pTc);\r
+\r
+extern void TC_Stop(AT91S_TC *pTc);\r
+\r
+extern unsigned char TC_FindMckDivisor(\r
+    unsigned int freq,\r
+    unsigned int mck,\r
+    unsigned int *div,\r
+    unsigned int *tcclks);\r
+\r
+#endif //#ifndef TC_H\r
+\r

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/tdes/tdes.c b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/tdes/tdes.c
new file mode 100644 (file)
index 0000000..4d78e1a
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/tdes/tdes.c
@@ -0,0 +1,228 @@
+/* ----------------------------------------------------------------------------\r
+ *         ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+//------------------------------------------------------------------------------\r
+//         Headers\r
+//------------------------------------------------------------------------------\r
+\r
+#include "tdes.h"\r
+#include <board.h>\r
+#include <utility/assert.h>\r
+#include <utility/trace.h>\r
+\r
+//------------------------------------------------------------------------------\r
+//         Global functions\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+/// Configures the triple-DES peripheral to cipher/decipher, use single-DES or\r
+/// triple-DES, use two or three keys (when in triple-DES mode), start manually,\r
+/// automatically or via the PDC and use the given operating mode (ECB, CBC,\r
+/// CFB or OFB).\r
+/// \param cipher  Encrypts if 1, decrypts if 0.\r
+/// \param tdesmod  Single- or triple-DES mode.\r
+/// \param keymod  Use two or three keys (must be 0 in single-DES mode).\r
+/// \param smod  Start mode.\r
+/// \param opmod  Encryption/decryption mode.\r
+//------------------------------------------------------------------------------\r
+void TDES_Configure(\r
+    unsigned char cipher,\r
+    unsigned int tdesmod,\r
+    unsigned int keymod,\r
+    unsigned int smod,\r
+    unsigned int opmod)\r
+{\r
+    TRACE_DEBUG("TDES_Configure()\n\r");\r
+    SANITY_CHECK((cipher & 0xFFFFFFFE) == 0);\r
+    SANITY_CHECK((tdesmod & 0xFFFFFFFD) == 0);\r
+    SANITY_CHECK((keymod & 0xFFFFFFEF) == 0);\r
+    SANITY_CHECK((smod & 0xFFFFFCFF) == 0);\r
+    SANITY_CHECK((opmod & 0xFFFFCFFF) == 0);\r
+\r
+    // Reset peripheral\r
+    AT91C_BASE_TDES->TDES_CR = AT91C_TDES_SWRST;\r
+\r
+    // Configure mode register\r
+    AT91C_BASE_TDES->TDES_MR = cipher | tdesmod | keymod | smod | opmod;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Starts the encryption or decryption process if the TDES peripheral is\r
+/// configured in manual or PDC mode.\r
+//------------------------------------------------------------------------------\r
+void TDES_Start(void)\r
+{\r
+    TRACE_DEBUG("TDES_Start()\n\r");\r
+    SANITY_CHECK(((AT91C_BASE_TDES->TDES_MR & AT91C_TDES_SMOD) == AT91C_TDES_SMOD_MANUAL)\r
+                 || ((AT91C_BASE_TDES->TDES_MR & AT91C_TDES_SMOD) == AT91C_TDES_SMOD_PDC));\r
+\r
+    // Manual mode\r
+    if ((AT91C_BASE_TDES->TDES_MR & AT91C_TDES_SMOD) == AT91C_TDES_SMOD_MANUAL) {\r
+\r
+        AT91C_BASE_TDES->TDES_CR = AT91C_TDES_START;\r
+    }\r
+    // PDC mode\r
+    else {\r
+\r
+        AT91C_BASE_TDES->TDES_PTCR = AT91C_PDC_RXTEN | AT91C_PDC_TXTEN;\r
+    }\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Returns the current status register value of the TDES peripheral.\r
+//------------------------------------------------------------------------------\r
+unsigned int TDES_GetStatus(void)\r
+{\r
+    TRACE_DEBUG("TDES_GetStatus()\n\r");\r
+\r
+    return AT91C_BASE_TDES->TDES_ISR;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Sets the 64-bits keys (one, two or three depending on the configuration)\r
+/// that shall be used by the TDES algorithm.\r
+/// \param pKey1  Pointer to key #1.\r
+/// \param pKey2  Pointer to key #2 (shall be 0 in single-DES mode).\r
+/// \param pKey3  Pointer to key #3 (shall be 0 when using two keys).\r
+//------------------------------------------------------------------------------\r
+void TDES_SetKeys(\r
+    const unsigned int *pKey1,\r
+    const unsigned int *pKey2,\r
+    const unsigned int *pKey3)\r
+{\r
+    TRACE_DEBUG("TDES_SetKeys()\n\r");\r
+    SANITY_CHECK(pKey1);\r
+    SANITY_CHECK((pKey2 && ((AT91C_BASE_TDES->TDES_MR & AT91C_TDES_TDESMOD) == AT91C_TDES_TDESMOD))\r
+                 || (!pKey2 && ((AT91C_BASE_TDES->TDES_MR & AT91C_TDES_TDESMOD) == 0)));\r
+    SANITY_CHECK((pKey3\r
+                  && ((AT91C_BASE_TDES->TDES_MR & AT91C_TDES_TDESMOD) == AT91C_TDES_TDESMOD)\r
+                  && ((AT91C_BASE_TDES->TDES_MR & AT91C_TDES_KEYMOD) == 0))\r
+                 ||\r
+                 (!pKey3\r
+                  && ((AT91C_BASE_TDES->TDES_MR & AT91C_TDES_TDESMOD) == AT91C_TDES_TDESMOD)\r
+                  && ((AT91C_BASE_TDES->TDES_MR & AT91C_TDES_KEYMOD) == AT91C_TDES_KEYMOD))\r
+                 ||\r
+                 (!pKey3\r
+                  && ((AT91C_BASE_TDES->TDES_MR & AT91C_TDES_TDESMOD) == 0)\r
+                  && ((AT91C_BASE_TDES->TDES_MR & AT91C_TDES_KEYMOD) == 0)));\r
+\r
+    // Write key #1\r
+    if (pKey1) {\r
+\r
+        AT91C_BASE_TDES->TDES_KEY1WxR[0] = pKey1[0];\r
+        AT91C_BASE_TDES->TDES_KEY1WxR[1] = pKey1[1];\r
+    }\r
+\r
+    // Write key #2\r
+    if (pKey1) {\r
+\r
+        AT91C_BASE_TDES->TDES_KEY2WxR[0] = pKey2[0];\r
+        AT91C_BASE_TDES->TDES_KEY2WxR[1] = pKey2[1];\r
+    }\r
+\r
+    // Write key #2\r
+    if (pKey1) {\r
+\r
+        AT91C_BASE_TDES->TDES_KEY3WxR[0] = pKey3[0];\r
+        AT91C_BASE_TDES->TDES_KEY3WxR[1] = pKey3[1];\r
+    }\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Sets the input data to encrypt/decrypt using TDES.\r
+/// \param pInput  Pointer to the 64-bits input data.\r
+//------------------------------------------------------------------------------\r
+void TDES_SetInputData(const unsigned int *pInput)\r
+{\r
+    TRACE_DEBUG("TDES_SetInputData()\n\r");\r
+    SANITY_CHECK(pInput);\r
+\r
+    AT91C_BASE_TDES->TDES_IDATAxR[0] = pInput[0];\r
+    AT91C_BASE_TDES->TDES_IDATAxR[1] = pInput[1];\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Sets the input data buffer to encrypt/decrypt when in PDC mode.\r
+/// \param pInput  Pointer to the input data.\r
+/// \param size  Size of buffer in bytes.\r
+//------------------------------------------------------------------------------\r
+void TDES_SetInputBuffer(const unsigned int *pInput, unsigned int size)\r
+{\r
+    TRACE_DEBUG("TDES_SetInputBuffer()\n\r");\r
+    SANITY_CHECK(pInput);\r
+    SANITY_CHECK((size > 0) && ((size % 8) == 0));\r
+\r
+    AT91C_BASE_TDES->TDES_TPR = (unsigned int) pInput;\r
+    AT91C_BASE_TDES->TDES_TCR = size / 4;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Stores the output data from the last TDES operation into the given 64-bits\r
+/// buffers.\r
+/// \param pOutput  Pointer to a 64-bits output buffer.\r
+//------------------------------------------------------------------------------\r
+void TDES_GetOutputData(unsigned int *pOutput)\r
+{\r
+    TRACE_DEBUG("TDES_GetOutputData()\n\r");\r
+    SANITY_CHECK(pOutput);\r
+\r
+    pOutput[0] = AT91C_BASE_TDES->TDES_ODATAxR[0];\r
+    pOutput[1] = AT91C_BASE_TDES->TDES_ODATAxR[1];\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Sets the output buffer which will receive the encrypted/decrypted data when\r
+/// using the PDC.\r
+/// \param pOutput  Pointer to the output data.\r
+/// \param size  Size of buffer in bytes.\r
+//------------------------------------------------------------------------------\r
+void TDES_SetOutputBuffer(unsigned int *pOutput, unsigned int size)\r
+{\r
+    TRACE_DEBUG("TDES_SetOutputBuffer()\n\r");\r
+    SANITY_CHECK(pOutput);\r
+    SANITY_CHECK((size > 0) && ((size % 8) == 0));\r
+\r
+    AT91C_BASE_TDES->TDES_RPR = (unsigned int) pOutput;\r
+    AT91C_BASE_TDES->TDES_RCR = size / 4;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Sets the initialization vector to use when the TDES algorithm is configured\r
+/// in a chained block mode (CBC, CFB or OFB).\r
+/// \param pVector  Pointer to the 64-bits vector.\r
+//------------------------------------------------------------------------------\r
+void TDES_SetVector(const unsigned int *pVector)\r
+{\r
+    TRACE_DEBUG("TDES_SetVector()\n\r");\r
+    SANITY_CHECK(pVector);\r
+\r
+    AT91C_BASE_TDES->TDES_IVxR[0] = pVector[0];\r
+    AT91C_BASE_TDES->TDES_IVxR[1] = pVector[1];\r
+}\r
+\r

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/tdes/tdes.h b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/tdes/tdes.h
new file mode 100644 (file)
index 0000000..cc0b9f6
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/tdes/tdes.h
@@ -0,0 +1,80 @@
+/* ----------------------------------------------------------------------------\r
+ *         ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+#ifndef TDES_H\r
+#define TDES_H\r
+\r
+//------------------------------------------------------------------------------\r
+/// \unit\r
+///\r
+/// !Purpose\r
+/// \r
+/// Methods to manage the Triple DES (3DES)\r
+/// \r
+/// !Usage\r
+///\r
+/// -# Configure TDES\r
+/// -# Sets the key used by the TDES algorithm\r
+/// -# Sets the input data of the TDES algorithm\r
+/// -# Starts the encryption/decryption process\r
+/// -# Stores the result of the last TDES operation\r
+///\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+//         Global functions\r
+//------------------------------------------------------------------------------\r
+\r
+extern void TDES_Configure(\r
+    unsigned char cipher,\r
+    unsigned int tdesmod,\r
+    unsigned int keymod,\r
+    unsigned int smod,\r
+    unsigned int opmod);\r
+\r
+extern void TDES_Start(void);\r
+\r
+extern unsigned int TDES_GetStatus(void);\r
+\r
+extern void TDES_SetKeys(\r
+    const unsigned int *pKey1,\r
+    const unsigned int *pKey2,\r
+    const unsigned int *pKey3);\r
+\r
+extern void TDES_SetInputData(const unsigned int *pInput);\r
+\r
+extern void TDES_SetInputBuffer(const unsigned int *pInput, unsigned int size);\r
+\r
+extern void TDES_GetOutputData(unsigned int *pOutput);\r
+\r
+extern void TDES_SetOutputBuffer(unsigned int *pOutput, unsigned int size);\r
+\r
+extern void TDES_SetVector(const unsigned int *pVector);\r
+\r
+#endif //#ifndef TDES_H\r

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/tsadcc/tsadcc.c b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/tsadcc/tsadcc.c
new file mode 100644 (file)
index 0000000..86b5680
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/tsadcc/tsadcc.c
@@ -0,0 +1,324 @@
+/* ----------------------------------------------------------------------------\r
+ *         ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+//------------------------------------------------------------------------------\r
+//         Headers\r
+//------------------------------------------------------------------------------\r
+\r
+#include <board.h>\r
+\r
+#ifdef AT91C_BASE_TSADC\r
+\r
+#include <utility/trace.h>\r
+#include <utility/assert.h>\r
+\r
+//------------------------------------------------------------------------------\r
+//         Local variables\r
+//------------------------------------------------------------------------------\r
+\r
+/// TSADC clock frequency in Hz.\r
+static unsigned int lAdcclk = 0;\r
+\r
+//------------------------------------------------------------------------------\r
+//         Global functions\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+/// Sets the operating mode of the TSADCC peripheral. The mode value can be\r
+/// one of the following:\r
+/// - AT91C_TSADC_TSAMOD_ADC_ONLY_MODE\r
+/// - AT91C_TSADC_TSAMOD_TS_ONLY_MODE\r
+/// \param mode  Desired mode for the TSADCC.\r
+//------------------------------------------------------------------------------\r
+void TSADCC_SetOperatingMode(unsigned int mode)\r
+{\r
+    SANITY_CHECK(  (mode == AT91C_TSADC_TSAMOD_ADC_ONLY_MODE)\r
+                 | (mode == AT91C_TSADC_TSAMOD_TS_ONLY_MODE));\r
+                 \r
+    AT91C_BASE_TSADC->TSADC_MR = (AT91C_BASE_TSADC->TSADC_MR\r
+                                  & ~AT91C_TSADC_TSAMOD)\r
+                                 | mode;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Enables or disables the low resolution precision on the TSADC.\r
+/// \param enable  If true, low resolution (8 bit) is used; otherwise the TSADC\r
+///                will use a 10-bit resolution.\r
+//------------------------------------------------------------------------------\r
+void TSADCC_SetLowResolution(unsigned char enable)\r
+{\r
+    if (enable) {\r
+    \r
+        AT91C_BASE_TSADC->TSADC_MR |= AT91C_TSADC_LOWRES;\r
+    }\r
+    else {\r
+    \r
+        AT91C_BASE_TSADC->TSADC_MR &= ~AT91C_TSADC_LOWRES;\r
+    }\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Enables or disable SLEEP mode on the TSADC.\r
+/// \param enable  If true, the TSADC is put into sleep mode; in normal mode\r
+///                otherwise.\r
+//------------------------------------------------------------------------------\r
+void TSADCC_SetSleepMode(unsigned char enable)\r
+{\r
+    if (enable) {\r
+    \r
+        AT91C_BASE_TSADC->TSADC_MR |= AT91C_TSADC_SLEEP;\r
+    }\r
+    else {\r
+    \r
+        AT91C_BASE_TSADC->TSADC_MR &= ~AT91C_TSADC_SLEEP;\r
+    }\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Enables or disables pen detection on the TSADC.\r
+/// \param enable  If true, pen detection is enabled; otherwise it is disabled.\r
+//------------------------------------------------------------------------------\r
+void TSADCC_SetPenDetect(unsigned char enable)\r
+{\r
+    if (enable) {\r
+    \r
+        AT91C_BASE_TSADC->TSADC_MR |= AT91C_TSADC_PENDET;\r
+    }\r
+    else {\r
+        \r
+        AT91C_BASE_TSADC->TSADC_MR &= ~AT91C_TSADC_PENDET;\r
+    }\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Sets the TSADC clock to the desired frequency. The prescaler is calculated\r
+/// by this function so the resulting frequency is equal or inferior to the\r
+/// desired one.\r
+/// \param adcclk  Desired ADC clock frequency in Hz.\r
+/// \param mck  Master clock frequency in Hz.\r
+//------------------------------------------------------------------------------\r
+void TSADCC_SetAdcFrequency(unsigned int adcclk, unsigned int mck)\r
+{\r
+    unsigned int prescal;\r
+    \r
+    // Formula for PRESCAL is:\r
+    // PRESCAL = (MCK / (2 * ADCCLK)) + 1\r
+    // First, we do the division, multiplied by 10 to get higher precision\r
+    // If the last digit is not zero, we round up to avoid generating a higher\r
+    // than required frequency.\r
+    prescal = (mck * 5) / adcclk;\r
+    if ((prescal % 10) > 0) {\r
+    \r
+        prescal = (prescal / 10);\r
+    }\r
+    else {\r
+    \r
+        SANITY_CHECK((prescal / 10) != 0);\r
+        prescal = (prescal / 10) - 1;\r
+    }\r
+    SANITY_CHECK((prescal & ~0x3F) == 0);\r
+    \r
+    AT91C_BASE_TSADC->TSADC_MR = (  AT91C_BASE_TSADC->TSADC_MR\r
+                                  & ~AT91C_TSADC_PRESCAL)\r
+                                 | (prescal << 8);\r
+                                 \r
+    // Save clock frequency for further timing calculations\r
+    lAdcclk = adcclk;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Sets the TSADC startup time. This function relies on the ADCCLK frequency\r
+/// that has been set using TSADCC_SetAdcFrequency(), so it must have been\r
+/// called first.\r
+/// \param time  Startup time in µseconds.\r
+//------------------------------------------------------------------------------\r
+void TSADCC_SetStartupTime(unsigned int time)\r
+{\r
+    unsigned int startup;\r
+    \r
+    SANITY_CHECK(lAdcclk != 0);\r
+        \r
+    // Formula for STARTUP is:\r
+    // STARTUP = (time x ADCCLK) / (1000000 x 8) - 1\r
+    // Division multiplied by 10 for higher precision\r
+    startup = (time * lAdcclk) / (800000);\r
+    if ((startup % 10) > 0) {\r
+    \r
+        startup /= 10;\r
+    }\r
+    else {\r
+    \r
+        startup /= 10;\r
+        if (startup > 0) {\r
+        \r
+            startup--;\r
+        }\r
+    }\r
+    \r
+    SANITY_CHECK((startup & ~0x7F) == 0);\r
+    AT91C_BASE_TSADC->TSADC_MR = (  AT91C_BASE_TSADC->TSADC_MR\r
+                                  & ~AT91C_TSADC_STARTUP)\r
+                                 | (startup << 16);\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Sets the TSADC track and hold time. This function relies on the ADCCLK\r
+/// frequency that has been set with TSADCC_SetAdcFrequency(), to it must be\r
+/// called first.\r
+/// This function also sets the track and hold time in the TSADC_TSR register.\r
+/// \param time  Track and hold time in nanoseconds.\r
+//------------------------------------------------------------------------------\r
+void TSADCC_SetTrackAndHoldTime(unsigned int time)\r
+{\r
+    unsigned int shtim;\r
+    \r
+    SANITY_CHECK(lAdcclk != 0);\r
+    \r
+    // Formula for SHTIM:\r
+    // SHTIM = (time x ADCCLK) / 1000000000 - 1\r
+    // Since 1 billion is close to the maximum value for an integer, we first\r
+    // divide ADCCLK by 1000 to avoid an overflow\r
+    shtim = (time * (lAdcclk / 1000)) / 100000;\r
+    if ((shtim % 10) > 0) {\r
+    \r
+        shtim /= 10;\r
+    }\r
+    else {\r
+    \r
+        shtim /= 10;\r
+        if (shtim > 0) shtim--;\r
+    }\r
+    \r
+    SANITY_CHECK((shtim & ~0xF) == 0);\r
+    AT91C_BASE_TSADC->TSADC_MR = (  AT91C_BASE_TSADC->TSADC_MR\r
+                                  & ~AT91C_TSADC_SHTIM)\r
+                                 | (shtim << 24);\r
+    AT91C_BASE_TSADC->TSADC_TSR = shtim << 24;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Sets the TSADC debounce time. This function relies on the ADCCLK\r
+/// frequency that has been set with TSADCC_SetAdcFrequency(), to it must be\r
+/// called first.\r
+/// \param time  Debounce time in nanoseconds (cannot be 0).\r
+//------------------------------------------------------------------------------\r
+void TSADCC_SetDebounceTime(unsigned int time)\r
+{\r
+    unsigned int divisor = 1000000000;\r
+    unsigned int clock = lAdcclk;\r
+    unsigned int pendbc = 0;\r
+    unsigned int targetValue;\r
+    unsigned int currentValue;\r
+    \r
+    SANITY_CHECK(lAdcclk != 0);\r
+    SANITY_CHECK(time != 0);\r
+    \r
+    // Divide time & ADCCLK first to avoid overflows\r
+    while ((divisor > 1) && ((time % 10) == 0)) {\r
+    \r
+        time /= 10;\r
+        divisor /= 10;\r
+    }\r
+    while ((divisor > 1) && ((clock % 10) == 0)) {\r
+    \r
+        clock /= 10;\r
+        divisor /= 10;\r
+    }\r
+    \r
+    // Compute PENDBC value\r
+    targetValue = time * clock / divisor;\r
+    currentValue = 1;\r
+    while (currentValue < targetValue) {\r
+    \r
+        pendbc++;\r
+        currentValue *= 2;\r
+    }\r
+    \r
+    SANITY_CHECK((pendbc & ~0xF) == 0);\r
+    AT91C_BASE_TSADC->TSADC_MR = (  AT91C_BASE_TSADC->TSADC_MR\r
+                                  & ~AT91C_TSADC_PENDBC)\r
+                                 | (pendbc << 28);\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Sets the trigger mode of the TSADCC to one of the following values:\r
+/// - AT91C_TSADC_TRGMOD_NO_TRIGGER\r
+/// - AT91C_TSADC_TRGMOD_EXTERNAL_TRIGGER_RE\r
+/// - AT91C_TSADC_TRGMOD_EXTERNAL_TRIGGER_FE\r
+/// - AT91C_TSADC_TRGMOD_EXTERNAL_TRIGGER_AE\r
+/// - AT91C_TSADC_TRGMOD_PENDET_TRIGGER\r
+/// - AT91C_TSADC_TRGMOD_PERIODIC_TRIGGER\r
+/// - AT91C_TSADC_TRGMOD_CONT_TRIGGER\r
+/// \param mode  Trigger mode.\r
+//------------------------------------------------------------------------------\r
+void TSADCC_SetTriggerMode(unsigned int mode)\r
+{\r
+    SANITY_CHECK(((mode & ~AT91C_TSADC_TRGMOD) == 0)\r
+                 | ((mode & AT91C_TSADC_TRGMOD) != 0x7));\r
+    \r
+    AT91C_BASE_TSADC->TSADC_TRGR = (AT91C_BASE_TSADC->TSADC_TRGR\r
+                                    & ~AT91C_TSADC_TRGMOD)\r
+                                   | mode;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Sets the trigger period when using the TSADCC in periodic trigger mode.\r
+/// As usual, this function requires TSADCC_SetAdcFrequency() to be called\r
+/// before it.\r
+/// \param period  Trigger period in nanoseconds.\r
+//------------------------------------------------------------------------------\r
+void TSADCC_SetTriggerPeriod(unsigned int period)\r
+{\r
+    unsigned int trgper;\r
+    unsigned int divisor = 100000000;\r
+    \r
+    while ((period >= 10) && (divisor >= 10)) {\r
+    \r
+        period /= 10;\r
+        divisor /= 10;\r
+    }\r
+    \r
+    trgper = (period * lAdcclk) / divisor;\r
+    if ((trgper % 10) > 0) {\r
+    \r
+        trgper /= 10;\r
+    }\r
+    else {\r
+    \r
+        trgper /= 10;\r
+        if (trgper > 0) trgper--;\r
+    }\r
+    \r
+    SANITY_CHECK((trgper & ~0xFFFF) == 0);\r
+    AT91C_BASE_TSADC->TSADC_TRGR = (AT91C_BASE_TSADC->TSADC_TRGR\r
+                                    & ~AT91C_TSADC_TRGPER)\r
+                                   | (trgper << 16);\r
+}\r
+\r
+#endif //#ifdef AT91C_BASE_TSADC\r

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/tsadcc/tsadcc.h b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/tsadcc/tsadcc.h
new file mode 100644 (file)
index 0000000..57dde4d
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/tsadcc/tsadcc.h
@@ -0,0 +1,60 @@
+/* ----------------------------------------------------------------------------\r
+ *         ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+#ifndef TSADCC_H\r
+#define TSADCC_H\r
+ \r
+//------------------------------------------------------------------------------\r
+//         Global functions\r
+//------------------------------------------------------------------------------\r
+\r
+#ifdef AT91C_BASE_TSADC\r
+\r
+extern void TSADCC_SetOperatingMode(unsigned int mode);\r
+\r
+extern void TSADCC_SetLowResolution(unsigned char enable);\r
+\r
+extern void TSADCC_SetSleepMode(unsigned char enable);\r
+\r
+extern void TSADCC_SetPenDetect(unsigned char enable);\r
+\r
+extern void TSADCC_SetAdcFrequency(unsigned int adcclk, unsigned int mck);\r
+\r
+extern void TSADCC_SetStartupTime(unsigned int time);\r
+\r
+extern void TSADCC_SetTrackAndHoldTime(unsigned int time);\r
+\r
+extern void TSADCC_SetDebounceTime(unsigned int time);\r
+\r
+extern void TSADCC_SetTriggerMode(unsigned int mode);\r
+\r
+extern void TSADCC_SetTriggerPeriod(unsigned int period);\r
+\r
+#endif //#ifdef AT91C_BASE_TSADC\r
+#endif //#ifndef TSADCC_H\r

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/twi/twi.c b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/twi/twi.c
new file mode 100644 (file)
index 0000000..6437b73
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/twi/twi.c
@@ -0,0 +1,372 @@
+/* ----------------------------------------------------------------------------\r
+ *         ATMEL Microcontroller Software Support\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+//------------------------------------------------------------------------------\r
+/// \unit\r
+///\r
+/// !Purpose\r
+///\r
+/// Interface for configuration the Two Wire Interface (TWI) peripheral.\r
+///\r
+/// !Usage\r
+///\r
+/// -# Configures a TWI peripheral to operate in master mode, at the given\r
+/// frequency (in Hz) using TWI_Configure().\r
+/// -# Sends a STOP condition on the TWI using TWI_Stop().\r
+/// -# Starts a read operation on the TWI bus with the specified slave using\r
+/// TWI_StartRead(). Data must then be read using TWI_ReadByte() whenever\r
+/// a byte is available (poll using TWI_ByteReceived()).\r
+/// -# Starts a write operation on the TWI to access the selected slave using\r
+/// TWI_StartWrite(). A byte of data must be provided to start the write;\r
+/// other bytes are written next.\r
+/// -# Sends a byte of data to one of the TWI slaves on the bus using TWI_WriteByte().\r
+/// This function must be called once before TWI_StartWrite() with the first byte of data\r
+/// to send, then it shall be called repeatedly after that to send the remaining bytes.\r
+/// -# Check if a byte has been received and can be read on the given TWI\r
+/// peripheral using TWI_ByteReceived().\r
+/// Check if a byte has been sent using TWI_ByteSent().\r
+/// -# Check if the current transmission is complete (the STOP has been sent)\r
+/// using TWI_TransferComplete().\r
+/// -# Enables & disable the selected interrupts sources on a TWI peripheral\r
+/// using TWI_EnableIt() and TWI_DisableIt().\r
+/// -# Get current status register of the given TWI peripheral using\r
+/// TWI_GetStatus(). Get current status register of the given TWI peripheral, but\r
+/// masking interrupt sources which are not currently enabled using\r
+/// TWI_GetMaskedStatus().\r
+//------------------------------------------------------------------------------\r
+\r
+\r
+//------------------------------------------------------------------------------\r
+//         Headers\r
+//------------------------------------------------------------------------------\r
+\r
+#include "twi.h"\r
+#include <utility/math.h>\r
+#include <utility/assert.h>\r
+#include <utility/trace.h>\r
+\r
+//------------------------------------------------------------------------------\r
+//         Global functions\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+/// Configures a TWI peripheral to operate in master mode, at the given\r
+/// frequency (in Hz). The duty cycle of the TWI clock is set to 50%.\r
+/// \param pTwi  Pointer to an AT91S_TWI instance.\r
+/// \param twck  Desired TWI clock frequency.\r
+/// \param mck  Master clock frequency.\r
+//------------------------------------------------------------------------------\r
+void TWI_ConfigureMaster(AT91S_TWI *pTwi, unsigned int twck, unsigned int mck)\r
+{\r
+    unsigned int ckdiv = 0;\r
+    unsigned int cldiv;\r
+    unsigned char ok = 0;\r
+\r
+    TRACE_DEBUG("TWI_ConfigureMaster()\n\r");\r
+    SANITY_CHECK(pTwi);\r
+\r
+#ifdef AT91C_TWI_SVEN  // TWI slave\r
+    // SVEN: TWI Slave Mode Enabled\r
+    pTwi->TWI_CR = AT91C_TWI_SVEN;\r
+#endif\r
+    // Reset the TWI\r
+    pTwi->TWI_CR = AT91C_TWI_SWRST;\r
+    pTwi->TWI_RHR;\r
+\r
+    // TWI Slave Mode Disabled, TWI Master Mode Disabled\r
+#ifdef AT91C_TWI_SVEN  // TWI slave\r
+    pTwi->TWI_CR = AT91C_TWI_SVDIS;\r
+#endif\r
+    pTwi->TWI_CR = AT91C_TWI_MSDIS;\r
+\r
+    // Set master mode\r
+    pTwi->TWI_CR = AT91C_TWI_MSEN;\r
+\r
+    // Configure clock\r
+    while (!ok) {\r
+        cldiv = ((mck / (2 * twck)) - 3) / power(2, ckdiv);\r
+        if (cldiv <= 255) {\r
+\r
+            ok = 1;\r
+        }\r
+        else {\r
+\r
+            ckdiv++;\r
+        }\r
+    }\r
+\r
+    ASSERT(ckdiv < 8, "-F- Cannot find valid TWI clock parameters\n\r");\r
+    TRACE_DEBUG("Using CKDIV = %u and CLDIV/CHDIV = %u\n\r", ckdiv, cldiv);\r
+    pTwi->TWI_CWGR = 0;\r
+    pTwi->TWI_CWGR = (ckdiv << 16) | (cldiv << 8) | cldiv;\r
+}\r
+\r
+\r
+\r
+#ifdef AT91C_TWI_SVEN  // TWI slave\r
+//------------------------------------------------------------------------------\r
+/// Configures a TWI peripheral to operate in slave mode\r
+/// \param pTwi  Pointer to an AT91S_TWI instance.\r
+//------------------------------------------------------------------------------\r
+void TWI_ConfigureSlave(AT91S_TWI *pTwi, unsigned char slaveAddress)\r
+{\r
+    unsigned int i;\r
+\r
+    // TWI software reset\r
+    pTwi->TWI_CR = AT91C_TWI_SWRST;\r
+    pTwi->TWI_RHR;\r
+\r
+    // Wait at least 10 ms\r
+    for (i=0; i < 1000000; i++);\r
+\r
+    // TWI Slave Mode Disabled, TWI Master Mode Disabled\r
+    pTwi->TWI_CR = AT91C_TWI_SVDIS | AT91C_TWI_MSDIS;\r
+\r
+    // Slave Address\r
+    pTwi->TWI_SMR = 0;\r
+    pTwi->TWI_SMR = (slaveAddress << 16) & AT91C_TWI_SADR;\r
+\r
+    // SVEN: TWI Slave Mode Enabled\r
+    pTwi->TWI_CR = AT91C_TWI_SVEN;\r
+\r
+    // Wait at least 10 ms\r
+    for (i=0; i < 1000000; i++);\r
+    ASSERT( (pTwi->TWI_CR & AT91C_TWI_SVDIS)!=AT91C_TWI_SVDIS, "Problem slave mode");\r
+}\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+/// Sends a STOP condition on the TWI.\r
+/// \param pTwi  Pointer to an AT91S_TWI instance.\r
+//------------------------------------------------------------------------------\r
+void TWI_Stop(AT91S_TWI *pTwi)\r
+{\r
+    SANITY_CHECK(pTwi);\r
+\r
+    pTwi->TWI_CR = AT91C_TWI_STOP;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Starts a read operation on the TWI bus with the specified slave, and returns\r
+/// immediately. Data must then be read using TWI_ReadByte() whenever a byte is\r
+/// available (poll using TWI_ByteReceived()).\r
+/// \param pTwi  Pointer to an AT91S_TWI instance.\r
+/// \param address  Slave address on the bus.\r
+/// \param iaddress  Optional internal address bytes.\r
+/// \param isize  Number of internal address bytes.\r
+//-----------------------------------------------------------------------------\r
+void TWI_StartRead(\r
+    AT91S_TWI *pTwi,\r
+    unsigned char address,\r
+    unsigned int iaddress,\r
+    unsigned char isize)\r
+{\r
+    //TRACE_DEBUG("TWI_StartRead()\n\r");\r
+    SANITY_CHECK(pTwi);\r
+    SANITY_CHECK((address & 0x80) == 0);\r
+    SANITY_CHECK((iaddress & 0xFF000000) == 0);\r
+    SANITY_CHECK(isize < 4);\r
+\r
+    // Set slave address and number of internal address bytes\r
+    pTwi->TWI_MMR = 0;\r
+    pTwi->TWI_MMR = (isize << 8) | AT91C_TWI_MREAD | (address << 16);\r
+\r
+    // Set internal address bytes\r
+    pTwi->TWI_IADR = 0;\r
+    pTwi->TWI_IADR = iaddress;\r
+\r
+    // Send START condition\r
+    pTwi->TWI_CR = AT91C_TWI_START;\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Reads a byte from the TWI bus. The read operation must have been started\r
+/// using TWI_StartRead() and a byte must be available (check with\r
+/// TWI_ByteReceived()).\r
+/// Returns the byte read.\r
+/// \param pTwi  Pointer to an AT91S_TWI instance.\r
+//-----------------------------------------------------------------------------\r
+unsigned char TWI_ReadByte(AT91S_TWI *pTwi)\r
+{\r
+    SANITY_CHECK(pTwi);\r
+\r
+    return pTwi->TWI_RHR;\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Sends a byte of data to one of the TWI slaves on the bus. This function\r
+/// must be called once before TWI_StartWrite() with the first byte of data\r
+/// to send, then it shall be called repeatedly after that to send the\r
+/// remaining bytes.\r
+/// \param pTwi  Pointer to an AT91S_TWI instance.\r
+/// \param byte  Byte to send.\r
+//-----------------------------------------------------------------------------\r
+void TWI_WriteByte(AT91S_TWI *pTwi, unsigned char byte)\r
+{\r
+    SANITY_CHECK(pTwi);\r
+\r
+    pTwi->TWI_THR = byte;\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Starts a write operation on the TWI to access the selected slave, then\r
+/// returns immediately. A byte of data must be provided to start the write;\r
+/// other bytes are written next.\r
+/// \param pTwi  Pointer to an AT91S_TWI instance.\r
+/// \param address  Address of slave to acccess on the bus.\r
+/// \param iaddress  Optional slave internal address.\r
+/// \param isize  Number of internal address bytes.\r
+/// \param byte  First byte to send.\r
+//-----------------------------------------------------------------------------\r
+void TWI_StartWrite(\r
+    AT91S_TWI *pTwi,\r
+    unsigned char address,\r
+    unsigned int iaddress,\r
+    unsigned char isize,\r
+    unsigned char byte)\r
+{\r
+    //TRACE_DEBUG("TWI_StartWrite()\n\r");\r
+    SANITY_CHECK(pTwi);\r
+    SANITY_CHECK((address & 0x80) == 0);\r
+    SANITY_CHECK((iaddress & 0xFF000000) == 0);\r
+    SANITY_CHECK(isize < 4);\r
+\r
+    // Set slave address and number of internal address bytes\r
+    pTwi->TWI_MMR = 0;\r
+    pTwi->TWI_MMR = (isize << 8) | (address << 16);\r
+\r
+    // Set internal address bytes\r
+    pTwi->TWI_IADR = 0;\r
+    pTwi->TWI_IADR = iaddress;\r
+\r
+    // Write first byte to send\r
+    TWI_WriteByte(pTwi, byte);\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Returns 1 if a byte has been received and can be read on the given TWI\r
+/// peripheral; otherwise, returns 0. This function resets the status register\r
+/// of the TWI.\r
+/// \param pTwi  Pointer to an AT91S_TWI instance.\r
+//-----------------------------------------------------------------------------\r
+unsigned char TWI_ByteReceived(AT91S_TWI *pTwi)\r
+{\r
+    return ((pTwi->TWI_SR & AT91C_TWI_RXRDY) == AT91C_TWI_RXRDY);\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Returns 1 if a byte has been sent, so another one can be stored for\r
+/// transmission; otherwise returns 0. This function clears the status register\r
+/// of the TWI.\r
+/// \param pTwi  Pointer to an AT91S_TWI instance.\r
+//-----------------------------------------------------------------------------\r
+unsigned char TWI_ByteSent(AT91S_TWI *pTwi)\r
+{\r
+    return ((pTwi->TWI_SR & AT91C_TWI_TXRDY) == AT91C_TWI_TXRDY);\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Returns 1 if the current transmission is complete (the STOP has been sent);\r
+/// otherwise returns 0.\r
+/// \param pTwi  Pointer to an AT91S_TWI instance.\r
+//-----------------------------------------------------------------------------\r
+unsigned char TWI_TransferComplete(AT91S_TWI *pTwi)\r
+{\r
+    return ((pTwi->TWI_SR & AT91C_TWI_TXCOMP) == AT91C_TWI_TXCOMP);\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Enables the selected interrupts sources on a TWI peripheral.\r
+/// \param pTwi  Pointer to an AT91S_TWI instance.\r
+/// \param sources  Bitwise OR of selected interrupt sources.\r
+//-----------------------------------------------------------------------------\r
+void TWI_EnableIt(AT91S_TWI *pTwi, unsigned int sources)\r
+{\r
+    SANITY_CHECK(pTwi);\r
+    SANITY_CHECK((sources & 0xFFFFF088) == 0);\r
+\r
+    pTwi->TWI_IER = sources;\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Disables the selected interrupts sources on a TWI peripheral.\r
+/// \param pTwi  Pointer to an AT91S_TWI instance.\r
+/// \param sources  Bitwise OR of selected interrupt sources.\r
+//-----------------------------------------------------------------------------\r
+void TWI_DisableIt(AT91S_TWI *pTwi, unsigned int sources)\r
+{\r
+    SANITY_CHECK(pTwi);\r
+    SANITY_CHECK((sources & 0xFFFFF088) == 0);\r
+\r
+    pTwi->TWI_IDR = sources;\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Returns the current status register of the given TWI peripheral. This\r
+/// resets the internal value of the status register, so further read may yield\r
+/// different values.\r
+/// \param pTwi  Pointer to an AT91S_TWI instance.\r
+//-----------------------------------------------------------------------------\r
+unsigned int TWI_GetStatus(AT91S_TWI *pTwi)\r
+{\r
+    SANITY_CHECK(pTwi);\r
+\r
+    return pTwi->TWI_SR;\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Returns the current status register of the given TWI peripheral, but\r
+/// masking interrupt sources which are not currently enabled.\r
+/// This resets the internal value of the status register, so further read may\r
+/// yield different values.\r
+/// \param pTwi  Pointer to an AT91S_TWI instance.\r
+//-----------------------------------------------------------------------------\r
+unsigned int TWI_GetMaskedStatus(AT91S_TWI *pTwi)\r
+{\r
+    unsigned int status;\r
+\r
+    SANITY_CHECK(pTwi);\r
+\r
+    status = pTwi->TWI_SR;\r
+    status &= pTwi->TWI_IMR;\r
+\r
+    return status;\r
+}\r
+//-----------------------------------------------------------------------------\r
+/// Sends a STOP condition. STOP Condition is sent just after completing\r
+/// the current byte transmission in master read mode.\r
+/// \param pTwi  Pointer to an AT91S_TWI instance.\r
+//-----------------------------------------------------------------------------\r
+void TWI_SendSTOPCondition(AT91S_TWI *pTwi)\r
+{\r
+    SANITY_CHECK(pTwi);\r
+\r
+    pTwi->TWI_CR |= AT91C_TWI_STOP;\r
+}\r
+\r

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/twi/twi.h b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/twi/twi.h
new file mode 100644 (file)
index 0000000..721b7c5
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/twi/twi.h
@@ -0,0 +1,150 @@
+/* ----------------------------------------------------------------------------\r
+ *         ATMEL Microcontroller Software Support\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+//------------------------------------------------------------------------------\r
+/// \unit\r
+///\r
+/// !Purpose\r
+///\r
+/// Interface for configuration the Two Wire Interface (TWI) peripheral.\r
+///\r
+/// !Usage\r
+///\r
+/// -# Configures a TWI peripheral to operate in master mode, at the given\r
+/// frequency (in Hz) using TWI_ConfigureMaster().\r
+/// -# or if hardware possible, configures a TWI peripheral to operate in \r
+/// slave mode, at the given frequency (in Hz) using TWI_ConfigureSlave().\r
+/// -# Sends a STOP condition on the TWI using TWI_Stop().\r
+/// -# Starts a read operation on the TWI bus with the specified slave using\r
+/// TWI_StartRead(). Data must then be read using TWI_ReadByte() whenever \r
+/// a byte is available (poll using TWI_ByteReceived()).\r
+/// -# Starts a write operation on the TWI to access the selected slave using\r
+/// TWI_StartWrite(). A byte of data must be provided to start the write;\r
+/// other bytes are written next. \r
+/// -# Sends a byte of data to one of the TWI slaves on the bus using TWI_WriteByte().\r
+/// This function must be called once before TWI_StartWrite() with the first byte of data\r
+/// to send, then it shall be called repeatedly after that to send the remaining bytes.\r
+/// -# Check if a byte has been received and can be read on the given TWI\r
+/// peripheral using TWI_ByteReceived(). \r
+/// Check if a byte has been sent using TWI_ByteSent().\r
+/// -# Check if the current transmission is complete (the STOP has been sent)\r
+/// using TWI_TransferComplete().\r
+/// -# Enables & disable the selected interrupts sources on a TWI peripheral\r
+/// using TWI_EnableIt() and TWI_DisableIt().\r
+/// -# Get current status register of the given TWI peripheral using\r
+/// TWI_GetStatus(). Get current status register of the given TWI peripheral, but\r
+/// masking interrupt sources which are not currently enabled using \r
+/// TWI_GetMaskedStatus().\r
+//------------------------------------------------------------------------------\r
+\r
+#ifndef TWI_H\r
+#define TWI_H\r
+\r
+//------------------------------------------------------------------------------\r
+//         Headers\r
+//------------------------------------------------------------------------------\r
+\r
+#include <board.h>\r
+\r
+//------------------------------------------------------------------------------\r
+//         Global definitions\r
+//------------------------------------------------------------------------------\r
+\r
+// Missing AT91C_TWI_TXRDY definition.\r
+#ifndef AT91C_TWI_TXRDY\r
+    #define AT91C_TWI_TXRDY   AT91C_TWI_TXRDY_MASTER\r
+#endif\r
+\r
+// Missing AT91C_TWI_TXCOMP definition.\r
+#ifndef AT91C_TWI_TXCOMP\r
+    #define AT91C_TWI_TXCOMP  AT91C_TWI_TXCOMP_MASTER\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+//         Global macros\r
+//------------------------------------------------------------------------------\r
+\r
+/// Returns 1 if the TXRDY bit (ready to transmit data) is set in the given\r
+/// status register value.\r
+#define TWI_STATUS_TXRDY(status) ((status & AT91C_TWI_TXRDY) == AT91C_TWI_TXRDY)\r
+\r
+/// Returns 1 if the RXRDY bit (ready to receive data) is set in the given\r
+/// status register value.\r
+#define TWI_STATUS_RXRDY(status) ((status & AT91C_TWI_RXRDY) == AT91C_TWI_RXRDY)\r
+\r
+/// Returns 1 if the TXCOMP bit (transfer complete) is set in the given\r
+/// status register value.\r
+#define TWI_STATUS_TXCOMP(status) ((status & AT91C_TWI_TXCOMP) == AT91C_TWI_TXCOMP)\r
+\r
+//------------------------------------------------------------------------------\r
+//         Global functions\r
+//------------------------------------------------------------------------------\r
+\r
+extern void TWI_ConfigureMaster(AT91S_TWI *pTwi, unsigned int twck, unsigned int mck);\r
+\r
+#ifdef AT91C_TWI_SVEN  // TWI slave\r
+extern void TWI_ConfigureSlave(AT91S_TWI *pTwi, unsigned char slaveAddress);\r
+#endif\r
+\r
+extern void TWI_Stop(AT91S_TWI *pTwi);\r
+\r
+extern void TWI_StartRead(\r
+    AT91S_TWI *pTwi,\r
+    unsigned char address,\r
+    unsigned int iaddress,\r
+    unsigned char isize);\r
+\r
+extern unsigned char TWI_ReadByte(AT91S_TWI *pTwi);\r
+\r
+extern void TWI_WriteByte(AT91S_TWI *pTwi, unsigned char byte);\r
+\r
+extern void TWI_StartWrite(\r
+    AT91S_TWI *pTwi,\r
+    unsigned char address,\r
+    unsigned int iaddress,\r
+    unsigned char isize,\r
+    unsigned char byte);\r
+\r
+extern unsigned char TWI_ByteReceived(AT91S_TWI *pTwi);\r
+\r
+extern unsigned char TWI_ByteSent(AT91S_TWI *pTwi);\r
+\r
+extern unsigned char TWI_TransferComplete(AT91S_TWI *pTwi);\r
+\r
+extern void TWI_EnableIt(AT91S_TWI *pTwi, unsigned int sources);\r
+\r
+extern void TWI_DisableIt(AT91S_TWI *pTwi, unsigned int sources);\r
+\r
+extern unsigned int TWI_GetStatus(AT91S_TWI *pTwi);\r
+\r
+extern unsigned int TWI_GetMaskedStatus(AT91S_TWI *pTwi);\r
+\r
+extern void TWI_SendSTOPCondition(AT91S_TWI *pTwi);\r
+\r
+#endif //#ifndef TWI_H\r

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/usart/usart.c b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/usart/usart.c
new file mode 100644 (file)
index 0000000..3f6d0e3
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/usart/usart.c
@@ -0,0 +1,272 @@
+/* ----------------------------------------------------------------------------\r
+ *         ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+//------------------------------------------------------------------------------\r
+//         Headers\r
+//------------------------------------------------------------------------------\r
+\r
+#include "usart.h"\r
+#include <utility/trace.h>\r
+#include <utility/assert.h>\r
+\r
+//------------------------------------------------------------------------------\r
+//         Exported functions\r
+//------------------------------------------------------------------------------\r
+//------------------------------------------------------------------------------\r
+/// Configures an USART peripheral with the specified parameters.\r
+/// \param usart  Pointer to the USART peripheral to configure.\r
+/// \param mode  Desired value for the USART mode register (see the datasheet).\r
+/// \param baudrate  Baudrate at which the USART should operate (in Hz).\r
+/// \param masterClock  Frequency of the system master clock (in Hz).\r
+//------------------------------------------------------------------------------\r
+void USART_Configure(AT91S_USART *usart,\r
+                            unsigned int mode,\r
+                            unsigned int baudrate,\r
+                            unsigned int masterClock)\r
+{\r
+    // Reset and disable receiver & transmitter\r
+    usart->US_CR = AT91C_US_RSTRX | AT91C_US_RSTTX\r
+                   | AT91C_US_RXDIS | AT91C_US_TXDIS;\r
+\r
+    // Configure mode\r
+    usart->US_MR = mode;\r
+\r
+    // Configure baudrate\r
+    // Asynchronous, no oversampling\r
+    if (((mode & AT91C_US_SYNC) == 0)\r
+        && ((mode & AT91C_US_OVER) == 0)) {\r
+    \r
+        usart->US_BRGR = (masterClock / baudrate) / 16;\r
+    }\r
+    // TODO other modes\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Enables or disables the transmitter of an USART peripheral.\r
+/// \param usart  Pointer to an USART peripheral\r
+/// \param enabled  If true, the transmitter is enabled; otherwise it is\r
+///                 disabled.\r
+//------------------------------------------------------------------------------\r
+void USART_SetTransmitterEnabled(AT91S_USART *usart,\r
+                                        unsigned char enabled)\r
+{\r
+    if (enabled) {\r
+\r
+        usart->US_CR = AT91C_US_TXEN;\r
+    }\r
+    else {\r
+\r
+        usart->US_CR = AT91C_US_TXDIS;\r
+    }\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Enables or disables the receiver of an USART peripheral\r
+/// \param usart  Pointer to an USART peripheral\r
+/// \param enabled  If true, the receiver is enabled; otherwise it is disabled.\r
+//------------------------------------------------------------------------------\r
+void USART_SetReceiverEnabled(AT91S_USART *usart,\r
+                                     unsigned char enabled)\r
+{\r
+    if (enabled) {\r
+\r
+        usart->US_CR = AT91C_US_RXEN;\r
+    }\r
+    else {\r
+\r
+        usart->US_CR = AT91C_US_RXDIS;\r
+    }\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Sends one packet of data through the specified USART peripheral. This\r
+/// function operates synchronously, so it only returns when the data has been\r
+/// actually sent.\r
+/// \param usart  Pointer to an USART peripheral.\r
+/// \param data  Data to send including 9nth bit and sync field if necessary (in\r
+///              the same format as the US_THR register in the datasheet).\r
+/// \param timeOut  Time out value (0 = no timeout).\r
+//------------------------------------------------------------------------------\r
+void USART_Write(\r
+    AT91S_USART *usart,\r
+    unsigned short data,\r
+    volatile unsigned int timeOut)\r
+{\r
+    if (timeOut == 0) {\r
+\r
+        while ((usart->US_CSR & AT91C_US_TXEMPTY) == 0);\r
+    }\r
+    else {\r
+\r
+        while ((usart->US_CSR & AT91C_US_TXEMPTY) == 0) {\r
+\r
+            if (timeOut == 0) {\r
+\r
+                TRACE_ERROR("USART_Write: Timed out.\n\r");\r
+                return;\r
+            }\r
+            timeOut--;\r
+        }\r
+    }\r
+\r
+    usart->US_THR = data;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Sends the contents of a data buffer through the specified USART peripheral.\r
+/// This function returns immediately (1 if the buffer has been queued, 0\r
+/// otherwise); poll the ENDTX and TXBUFE bits of the USART status register\r
+/// to check for the transfer completion.\r
+/// \param usart  Pointer to an USART peripheral.\r
+/// \param buffer  Pointer to the data buffer to send.\r
+/// \param size  Size of the data buffer (in bytes).\r
+//------------------------------------------------------------------------------\r
+unsigned char USART_WriteBuffer(\r
+    AT91S_USART *usart,\r
+    void *buffer,\r
+    unsigned int size)\r
+{\r
+    // Check if the first PDC bank is free\r
+    if ((usart->US_TCR == 0) && (usart->US_TNCR == 0)) {\r
+\r
+        usart->US_TPR = (unsigned int) buffer;\r
+        usart->US_TCR = size;\r
+        usart->US_PTCR = AT91C_PDC_TXTEN;\r
+\r
+        return 1;\r
+    }\r
+    // Check if the second PDC bank is free\r
+    else if (usart->US_TNCR == 0) {\r
+\r
+        usart->US_TNPR = (unsigned int) buffer;\r
+        usart->US_TNCR = size;\r
+\r
+        return 1;\r
+    }\r
+    else {\r
+\r
+        return 0;\r
+    }\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Reads and return a packet of data on the specified USART peripheral. This\r
+/// function operates asynchronously, so it waits until some data has been\r
+/// received.\r
+/// \param usart  Pointer to an USART peripheral.\r
+/// \param timeOut  Time out value (0 -> no timeout).\r
+//------------------------------------------------------------------------------\r
+unsigned short USART_Read(\r
+    AT91S_USART *usart,\r
+    volatile unsigned int timeOut)\r
+{\r
+    if (timeOut == 0) {\r
+\r
+        while ((usart->US_CSR & AT91C_US_RXRDY) == 0);\r
+    }\r
+    else {\r
+\r
+        while ((usart->US_CSR & AT91C_US_RXRDY) == 0) {\r
+\r
+            if (timeOut == 0) {\r
+\r
+                TRACE_ERROR("USART_Read: Timed out.\n\r");\r
+                return 0;\r
+            }\r
+            timeOut--;\r
+        }\r
+    }\r
+\r
+    return usart->US_RHR;\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Reads data from an USART peripheral, filling the provided buffer until it\r
+/// becomes full. This function returns immediately with 1 if the buffer has\r
+/// been queued for transmission; otherwise 0.\r
+/// \param usart  Pointer to an USART peripheral.\r
+/// \param buffer  Pointer to the buffer where the received data will be stored.\r
+/// \param size  Size of the data buffer (in bytes).\r
+//------------------------------------------------------------------------------\r
+unsigned char USART_ReadBuffer(AT91S_USART *usart,\r
+                                      void *buffer,\r
+                                      unsigned int size)\r
+{\r
+    // Check if the first PDC bank is free\r
+    if ((usart->US_RCR == 0) && (usart->US_RNCR == 0)) {\r
+\r
+        usart->US_RPR = (unsigned int) buffer;\r
+        usart->US_RCR = size;\r
+        usart->US_PTCR = AT91C_PDC_RXTEN;\r
+\r
+        return 1;\r
+    }\r
+    // Check if the second PDC bank is free\r
+    else if (usart->US_RNCR == 0) {\r
+\r
+        usart->US_RNPR = (unsigned int) buffer;\r
+        usart->US_RNCR = size;\r
+\r
+        return 1;\r
+    }\r
+    else {\r
+\r
+        return 0;\r
+    }\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Returns 1 if some data has been received and can be read from an USART;\r
+/// otherwise returns 0.\r
+/// \param usart  Pointer to an AT91S_USART instance.\r
+//------------------------------------------------------------------------------\r
+unsigned char USART_IsDataAvailable(AT91S_USART *usart)\r
+{\r
+    if ((usart->US_CSR & AT91C_US_RXRDY) != 0) {\r
+\r
+        return 1;\r
+    }\r
+    else {\r
+\r
+        return 0;\r
+    }\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Sets the filter value for the IRDA demodulator.\r
+/// \param pUsart  Pointer to an AT91S_USART instance.\r
+/// \param filter  Filter value.\r
+//------------------------------------------------------------------------------\r
+void USART_SetIrdaFilter(AT91S_USART *pUsart, unsigned char filter)\r
+{\r
+    SANITY_CHECK(pUsart);\r
+\r
+    pUsart->US_IF = filter;\r
+}\r
+\r

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/usart/usart.h b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/usart/usart.h
new file mode 100644 (file)
index 0000000..84a633c
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/peripherals/usart/usart.h
@@ -0,0 +1,118 @@
+/* ----------------------------------------------------------------------------\r
+ *         ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+//------------------------------------------------------------------------------\r
+/// \dir\r
+/// !Purpose\r
+/// \r
+/// This module provides several definitions and methods for using an USART\r
+/// peripheral.\r
+///\r
+/// !Usage\r
+/// -# Enable the USART peripheral clock in the PMC.\r
+/// -# Enable the required USART PIOs (see pio.h).\r
+/// -# Configure the UART by calling USART_Configure.\r
+/// -# Enable the transmitter and/or the receiver of the USART using\r
+///    USART_SetTransmitterEnabled and USART_SetReceiverEnabled.\r
+/// -# Send data through the USART using the USART_Write and\r
+///    USART_WriteBuffer methods.\r
+/// -# Receive data from the USART using the USART_Read and\r
+///    USART_ReadBuffer functions; the availability of data can be polled\r
+///    with USART_IsDataAvailable.\r
+/// -# Disable the transmitter and/or the receiver of the USART with\r
+///    USART_SetTransmitterEnabled and USART_SetReceiverEnabled.\r
+//------------------------------------------------------------------------------\r
+\r
+#ifndef USART_H\r
+#define USART_H\r
+\r
+//------------------------------------------------------------------------------\r
+//         Headers\r
+//------------------------------------------------------------------------------\r
+\r
+#include <board.h>\r
+\r
+//------------------------------------------------------------------------------\r
+//         Definitions\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+/// \page "USART modes"\r
+/// This page lists several common operating modes for an USART peripheral.\r
+/// \r
+/// !Modes\r
+/// - USART_MODE_ASYNCHRONOUS\r
+/// - USART_MODE_IRDA\r
+\r
+/// Basic asynchronous mode, i.e. 8 bits no parity.\r
+#define USART_MODE_ASYNCHRONOUS (AT91C_US_CHRL_8_BITS | AT91C_US_PAR_NONE)\r
+\r
+/// IRDA mode\r
+#define USART_MODE_IRDA         (AT91C_US_USMODE_IRDA | AT91C_US_CHRL_8_BITS | AT91C_US_PAR_NONE | AT91C_US_FILTER)\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+//         Exported functions\r
+//------------------------------------------------------------------------------\r
+\r
+extern void USART_Configure(\r
+    AT91S_USART *usart,\r
+    unsigned int mode,\r
+    unsigned int baudrate,\r
+    unsigned int masterClock);\r
+\r
+extern void USART_SetTransmitterEnabled(AT91S_USART *usart, unsigned char enabled);\r
+\r
+extern void USART_SetReceiverEnabled(AT91S_USART *usart, unsigned char enabled);\r
+\r
+extern void USART_Write(\r
+    AT91S_USART *usart, \r
+    unsigned short data, \r
+    volatile unsigned int timeOut);\r
+\r
+extern unsigned char USART_WriteBuffer(\r
+    AT91S_USART *usart,\r
+    void *buffer,\r
+    unsigned int size);\r
+\r
+extern unsigned short USART_Read(\r
+    AT91S_USART *usart, \r
+    volatile unsigned int timeOut);\r
+\r
+extern unsigned char USART_ReadBuffer(\r
+    AT91S_USART *usart,\r
+    void *buffer,\r
+    unsigned int size);\r
+\r
+extern unsigned char USART_IsDataAvailable(AT91S_USART *usart);\r
+\r
+extern void USART_SetIrdaFilter(AT91S_USART *pUsart, unsigned char filter);\r
+\r
+#endif //#ifndef USART_H\r
+\r

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/utility/assert.h b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/utility/assert.h
new file mode 100644 (file)
index 0000000..5cccb61
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/utility/assert.h
@@ -0,0 +1,114 @@
+/* ----------------------------------------------------------------------------\r
+ *         ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+//------------------------------------------------------------------------------\r
+/// \unit\r
+///\r
+/// !Purpose\r
+///\r
+/// Definition of the ASSERT() and SANITY_CHECK() macros, which are used for\r
+/// runtime condition & parameter verifying.\r
+///\r
+/// !Usage\r
+///\r
+/// -# Use ASSERT() in your code to check the value of function parameters,\r
+///    return values, etc. *Warning:* the ASSERT() condition must not have\r
+///    any side-effect; otherwise, the program may not work properly\r
+///    anymore when assertions are disabled.\r
+/// -# Use SANITY_CHECK() to perform checks with a default error message\r
+///    (outputs the file and line number where the error occured). This \r
+///    reduces memory overhead caused by assertion error strings.\r
+/// -# Initialize the dbgu to see failed assertions at run-time.\r
+/// -# Assertions can be entirely disabled by defining the NOASSERT symbol\r
+///    at compilation time.\r
+//------------------------------------------------------------------------------\r
+\r
+#ifndef ASSERT_H\r
+#define ASSERT_H\r
+\r
+//------------------------------------------------------------------------------\r
+//         Headers\r
+//------------------------------------------------------------------------------\r
+\r
+#include <stdio.h>\r
+#include "trace.h"\r
+\r
+//------------------------------------------------------------------------------\r
+//         Definitions\r
+//------------------------------------------------------------------------------\r
+#if defined(NOASSERT)\r
+    #define ASSERT(...)\r
+    #define SANITY_CHECK(...)\r
+#else\r
+\r
+    #if (TRACE_LEVEL == 0)\r
+        /// Checks that the given condition is true, \r
+        /// otherwise stops the program execution.\r
+        /// \param condition  Condition to verify.\r
+        #define ASSERT(condition, ...)  { \\r
+            if (!(condition)) { \\r
+                while (1); \\r
+            } \\r
+        }\r
+\r
+        /// Performs the same duty as the ASSERT() macro\r
+        /// \param condition  Condition to verify.\r
+        #define SANITY_CHECK(condition) ASSERT(condition, ...)\r
+\r
+    #else\r
+        /// Checks that the given condition is true, otherwise displays an error\r
+        /// message and stops the program execution.\r
+        /// \param condition  Condition to verify.\r
+        #define ASSERT(condition, ...)  { \\r
+            if (!(condition)) { \\r
+                printf("-F- ASSERT: "); \\r
+                printf(__VA_ARGS__); \\r
+                while (1); \\r
+            } \\r
+        }\r
+        #define SANITY_ERROR            "Sanity check failed at %s:%d\n\r"\r
+    \r
+        /// Performs the same duty as the ASSERT() macro, except a default error\r
+        /// message is output if the condition is false.\r
+        /// \param condition  Condition to verify.\r
+        #define SANITY_CHECK(condition) ASSERT(condition, SANITY_ERROR, __FILE__, __LINE__)\r
+    #endif\r
+#endif\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+#endif //#ifndef ASSERT_H\r
+\r

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/utility/trace.h b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/utility/trace.h
new file mode 100644 (file)
index 0000000..921ac97
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/utility/trace.h
@@ -0,0 +1,238 @@
+/* ----------------------------------------------------------------------------\r
+ *         ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+//------------------------------------------------------------------------------\r
+/// \unit\r
+///\r
+/// !Purpose\r
+///\r
+/// Standard output methods for reporting debug information, warnings and\r
+/// errors, which can be easily be turned on/off.\r
+///\r
+/// !Usage\r
+/// -# Initialize the DBGU using TRACE_CONFIGURE() if you intend to eventually\r
+///    disable ALL traces; otherwise use DBGU_Configure().\r
+/// -# Uses the TRACE_DEBUG(), TRACE_INFO(), TRACE_WARNING(), TRACE_ERROR()\r
+///    TRACE_FATAL() macros to output traces throughout the program.\r
+/// -# Each type of trace has a level : Debug 5, Info 4, Warning 3, Error 2\r
+///    and Fatal 1. Disable a group of traces by changing the value of \r
+///    TRACE_LEVEL during compilation; traces with a level bigger than TRACE_LEVEL \r
+///    are not generated. To generate no trace, use the reserved value 0.\r
+/// -# Trace disabling can be static or dynamic. If dynamic disabling is selected\r
+///    the trace level can be modified in runtime. If static disabling is selected\r
+///    the disabled traces are not compiled.\r
+///\r
+/// !Trace level description\r
+/// -# TRACE_DEBUG (5): Traces whose only purpose is for debugging the program, \r
+///    and which do not produce meaningful information otherwise.\r
+/// -# TRACE_INFO (4): Informational trace about the program execution. Should  \r
+///    enable the user to see the execution flow.\r
+/// -# TRACE_WARNING (3): Indicates that a minor error has happened. In most case\r
+///    it can be discarded safely; it may even be expected.\r
+/// -# TRACE_ERROR (2): Indicates an error which may not stop the program execution, \r
+///    but which indicates there is a problem with the code.\r
+/// -# TRACE_FATAL (1): Indicates a major error which prevents the program from going\r
+///    any further.\r
+\r
+//------------------------------------------------------------------------------\r
+\r
+#ifndef TRACE_H\r
+#define TRACE_H\r
+\r
+//------------------------------------------------------------------------------\r
+//         Headers\r
+//------------------------------------------------------------------------------\r
+\r
+#include <board.h>\r
+#include <dbgu/dbgu.h>\r
+#include <pio/pio.h>\r
+#include <stdio.h>\r
+\r
+//------------------------------------------------------------------------------\r
+//         Global Definitions\r
+//------------------------------------------------------------------------------\r
+\r
+/// Softpack Version\r
+#define SOFTPACK_VERSION "1.6RC1"\r
+\r
+#define TRACE_LEVEL_DEBUG      5\r
+#define TRACE_LEVEL_INFO       4\r
+#define TRACE_LEVEL_WARNING    3\r
+#define TRACE_LEVEL_ERROR      2\r
+#define TRACE_LEVEL_FATAL      1\r
+#define TRACE_LEVEL_NO_TRACE   0\r
+\r
+// By default, all traces are output except the debug one.\r
+#if !defined(TRACE_LEVEL)    \r
+#define TRACE_LEVEL TRACE_LEVEL_INFO\r
+#endif\r
+\r
+// By default, trace level is static (not dynamic)\r
+#if !defined(DYN_TRACES)\r
+#define DYN_TRACES 0\r
+#endif\r
+\r
+#if defined(NOTRACE)\r
+#error "Error: NOTRACE has to be not defined !"\r
+#endif\r
+\r
+#undef NOTRACE\r
+#if (DYN_TRACES==0)\r
+    #if (TRACE_LEVEL == TRACE_LEVEL_NO_TRACE)\r
+        #define NOTRACE\r
+    #endif\r
+#endif\r
+\r
+\r
+\r
+//------------------------------------------------------------------------------\r
+//         Global Macros\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+/// Initializes the DBGU\r
+/// \param mode  DBGU mode.\r
+/// \param baudrate  DBGU baudrate.\r
+/// \param mck  Master clock frequency.\r
+//------------------------------------------------------------------------------\r
+#define TRACE_CONFIGURE(mode, baudrate, mck) { \\r
+    const Pin pinsDbgu[] = {PINS_DBGU}; \\r
+    PIO_Configure(pinsDbgu, PIO_LISTSIZE(pinsDbgu)); \\r
+    DBGU_Configure(mode, baudrate, mck); \\r
+    }\r
+\r
+//------------------------------------------------------------------------------\r
+/// Initializes the DBGU for ISP project\r
+/// \param mode  DBGU mode.\r
+/// \param baudrate  DBGU baudrate.\r
+/// \param mck  Master clock frequency.\r
+//------------------------------------------------------------------------------\r
+#if (TRACE_LEVEL==0) && (DYNTRACE==0)\r
+#define TRACE_CONFIGURE_ISP(mode, baudrate, mck) {}\r
+#else\r
+#define TRACE_CONFIGURE_ISP(mode, baudrate, mck) { \\r
+    const Pin pinsDbgu[] = {PINS_DBGU}; \\r
+    PIO_Configure(pinsDbgu, PIO_LISTSIZE(pinsDbgu)); \\r
+    DBGU_Configure(mode, baudrate, mck); \\r
+    }\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+/// Outputs a formatted string using <printf> if the log level is high\r
+/// enough. Can be disabled by defining TRACE_LEVEL=0 during compilation.\r
+/// \param format  Formatted string to output.\r
+/// \param ...  Additional parameters depending on formatted string.\r
+//------------------------------------------------------------------------------\r
+#if defined(NOTRACE)\r
+\r
+// Empty macro\r
+#define TRACE_DEBUG(...)      { }\r
+#define TRACE_INFO(...)       { }\r
+#define TRACE_WARNING(...)    { }               \r
+#define TRACE_ERROR(...)      { }\r
+#define TRACE_FATAL(...)      { while(1); }\r
+\r
+#define TRACE_DEBUG_WP(...)   { }\r
+#define TRACE_INFO_WP(...)    { }\r
+#define TRACE_WARNING_WP(...) { }\r
+#define TRACE_ERROR_WP(...)   { }\r
+#define TRACE_FATAL_WP(...)   { while(1); }\r
+\r
+#elif (DYN_TRACES == 1)\r
+\r
+// Trace output depends on traceLevel value\r
+#define TRACE_DEBUG(...)      { if (traceLevel >= TRACE_LEVEL_DEBUG)   { printf("-D- " __VA_ARGS__); } }\r
+#define TRACE_INFO(...)       { if (traceLevel >= TRACE_LEVEL_INFO)    { printf("-I- " __VA_ARGS__); } }\r
+#define TRACE_WARNING(...)    { if (traceLevel >= TRACE_LEVEL_WARNING) { printf("-W- " __VA_ARGS__); } }\r
+#define TRACE_ERROR(...)      { if (traceLevel >= TRACE_LEVEL_ERROR)   { printf("-E- " __VA_ARGS__); } }\r
+#define TRACE_FATAL(...)      { if (traceLevel >= TRACE_LEVEL_FATAL)   { printf("-F- " __VA_ARGS__); while(1); } }\r
+\r
+#define TRACE_DEBUG_WP(...)   { if (traceLevel >= TRACE_LEVEL_DEBUG)   { printf(__VA_ARGS__); } }\r
+#define TRACE_INFO_WP(...)    { if (traceLevel >= TRACE_LEVEL_INFO)    { printf(__VA_ARGS__); } }\r
+#define TRACE_WARNING_WP(...) { if (traceLevel >= TRACE_LEVEL_WARNING) { printf(__VA_ARGS__); } }\r
+#define TRACE_ERROR_WP(...)   { if (traceLevel >= TRACE_LEVEL_ERROR)   { printf(__VA_ARGS__); } }\r
+#define TRACE_FATAL_WP(...)   { if (traceLevel >= TRACE_LEVEL_FATAL)   { printf(__VA_ARGS__); while(1); } }\r
+\r
+#else\r
+\r
+// Trace compilation depends on TRACE_LEVEL value\r
+#if (TRACE_LEVEL >= TRACE_LEVEL_DEBUG)\r
+#define TRACE_DEBUG(...)      { printf("-D- " __VA_ARGS__); }\r
+#define TRACE_DEBUG_WP(...)   { printf(__VA_ARGS__); }\r
+#else\r
+#define TRACE_DEBUG(...)      { }\r
+#define TRACE_DEBUG_WP(...)   { }\r
+#endif\r
+\r
+#if (TRACE_LEVEL >= TRACE_LEVEL_INFO)\r
+#define TRACE_INFO(...)       { printf("-I- " __VA_ARGS__); }\r
+#define TRACE_INFO_WP(...)    { printf(__VA_ARGS__); }\r
+#else\r
+#define TRACE_INFO(...)       { }\r
+#define TRACE_INFO_WP(...)    { }\r
+#endif\r
+\r
+#if (TRACE_LEVEL >= TRACE_LEVEL_WARNING)\r
+#define TRACE_WARNING(...)    { printf("-W- " __VA_ARGS__); }\r
+#define TRACE_WARNING_WP(...) { printf(__VA_ARGS__); }\r
+#else\r
+#define TRACE_WARNING(...)    { }\r
+#define TRACE_WARNING_WP(...) { }\r
+#endif\r
+\r
+#if (TRACE_LEVEL >= TRACE_LEVEL_ERROR)\r
+#define TRACE_ERROR(...)      { printf("-E- " __VA_ARGS__); }\r
+#define TRACE_ERROR_WP(...)   { printf(__VA_ARGS__); }\r
+#else\r
+#define TRACE_ERROR(...)      { }\r
+#define TRACE_ERROR_WP(...)   { }\r
+#endif\r
+\r
+#if (TRACE_LEVEL >= TRACE_LEVEL_FATAL)\r
+#define TRACE_FATAL(...)      { printf("-F- " __VA_ARGS__); while(1); }\r
+#define TRACE_FATAL_WP(...)   { printf(__VA_ARGS__); while(1); }\r
+#else\r
+#define TRACE_FATAL(...)      { while(1); }\r
+#define TRACE_FATAL_WP(...)   { while(1); }\r
+#endif\r
+\r
+#endif\r
+\r
+\r
+//------------------------------------------------------------------------------\r
+//         Exported variables\r
+//------------------------------------------------------------------------------\r
+// Depending on DYN_TRACES, traceLevel is a modifable runtime variable\r
+// or a define\r
+#if !defined(NOTRACE) && (DYN_TRACES == 1)\r
+    extern unsigned int traceLevel;\r
+#endif\r
+\r
+#endif //#ifndef TRACE_H\r
+\r

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/FreeRTOSConfig.h b/Demo/CORTEX_AT91SAM3U256_IAR/FreeRTOSConfig.h
new file mode 100644 (file)
index 0000000..9d5ea63
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/FreeRTOSConfig.h
@@ -0,0 +1,105 @@
+/*\r
+       FreeRTOS.org V5.3.0 - Copyright (C) 2003-2009 Richard Barry.\r
+\r
+       This file is part of the FreeRTOS.org distribution.\r
+\r
+       FreeRTOS.org is free software; you can redistribute it and/or modify it\r
+       under the terms of the GNU General Public License (version 2) as published\r
+       by the Free Software Foundation and modified by the FreeRTOS exception.\r
+       **NOTE** The exception to the GPL is included to allow you to distribute a\r
+       combined work that includes FreeRTOS.org without being obliged to provide\r
+       the source code for any proprietary components.  Alternative commercial\r
+       license and support terms are also available upon request.  See the \r
+       licensing section of http://www.FreeRTOS.org for full details.\r
+\r
+       FreeRTOS.org is distributed in the hope that it will be useful, but WITHOUT\r
+       ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\r
+       FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\r
+       more details.\r
+\r
+       You should have received a copy of the GNU General Public License along\r
+       with FreeRTOS.org; if not, write to the Free Software Foundation, Inc., 59\r
+       Temple Place, Suite 330, Boston, MA  02111-1307  USA.\r
+\r
+\r
+       ***************************************************************************\r
+       *                                                                         *\r
+       * Get the FreeRTOS eBook!  See http://www.FreeRTOS.org/Documentation      *\r
+       *                                                                         *\r
+       * This is a concise, step by step, 'hands on' guide that describes both   *\r
+       * general multitasking concepts and FreeRTOS specifics. It presents and   *\r
+       * explains numerous examples that are written using the FreeRTOS API.     *\r
+       * Full source code for all the examples is provided in an accompanying    *\r
+       * .zip file.                                                              *\r
+       *                                                                         *\r
+       ***************************************************************************\r
+\r
+       1 tab == 4 spaces!\r
+\r
+       Please ensure to read the configuration and relevant port sections of the\r
+       online documentation.\r
+\r
+       http://www.FreeRTOS.org - Documentation, latest information, license and\r
+       contact details.\r
+\r
+       http://www.SafeRTOS.com - A version that is certified for use in safety\r
+       critical systems.\r
+\r
+       http://www.OpenRTOS.com - Commercial support, development, porting,\r
+       licensing and training services.\r
+*/\r
+\r
+#ifndef FREERTOS_CONFIG_H\r
+#define FREERTOS_CONFIG_H\r
+\r
+/*-----------------------------------------------------------\r
+ * Application specific definitions.\r
+ *\r
+ * These definitions should be adjusted for your particular hardware and\r
+ * application requirements.\r
+ *\r
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\r
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.\r
+ *\r
+ * See http://www.freertos.org/a00110.html.\r
+ *----------------------------------------------------------*/\r
+\r
+#define configUSE_PREEMPTION                   1\r
+#define configUSE_IDLE_HOOK                            0\r
+#define configUSE_TICK_HOOK                            1\r
+#define configCPU_CLOCK_HZ                             ( ( unsigned portLONG ) 48000000 )\r
+#define configTICK_RATE_HZ                             ( ( portTickType ) 1000 )\r
+#define configMINIMAL_STACK_SIZE               ( ( unsigned portSHORT ) 70 )\r
+#define configTOTAL_HEAP_SIZE                  ( ( size_t ) ( 24000 ) )\r
+#define configMAX_TASK_NAME_LEN                        ( 12 )\r
+#define configUSE_TRACE_FACILITY               1\r
+#define configUSE_16_BIT_TICKS                 0\r
+#define configIDLE_SHOULD_YIELD                        0\r
+#define configUSE_CO_ROUTINES                  0\r
+#define configUSE_MUTEXES                              1\r
+#define configUSE_RECURSIVE_MUTEXES            1\r
+#define configCHECK_FOR_STACK_OVERFLOW 2\r
+\r
+#define configMAX_PRIORITIES           ( ( unsigned portBASE_TYPE ) 5 )\r
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )\r
+#define configQUEUE_REGISTRY_SIZE                      10\r
+\r
+/* Set the following definitions to 1 to include the API function, or zero\r
+to exclude the API function. */\r
+\r
+#define INCLUDE_vTaskPrioritySet                       1\r
+#define INCLUDE_uxTaskPriorityGet                      1\r
+#define INCLUDE_vTaskDelete                                    1\r
+#define INCLUDE_vTaskCleanUpResources          0\r
+#define INCLUDE_vTaskSuspend                           1\r
+#define INCLUDE_vTaskDelayUntil                                1\r
+#define INCLUDE_vTaskDelay                                     1\r
+#define INCLUDE_uxTaskGetStackHighWaterMark    1\r
+\r
+\r
+\r
+#define configKERNEL_INTERRUPT_PRIORITY                ( 0x0f << 4 )   /* Priority 15, or 255 as only the top four bits are implemented.  This is the lowest priority. */\r
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY   ( 5 << 4 )      /* Priority 5, or 80 as only the top four bits are implemented. */\r
+\r
+\r
+#endif /* FREERTOS_CONFIG_H */\r

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/ParTest/ParTest.c b/Demo/CORTEX_AT91SAM3U256_IAR/ParTest/ParTest.c
new file mode 100644 (file)
index 0000000..91e2bd9
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/ParTest/ParTest.c
@@ -0,0 +1,140 @@
+/*\r
+       FreeRTOS.org V5.3.0 - Copyright (C) 2003-2009 Richard Barry.\r
+\r
+       This file is part of the FreeRTOS.org distribution.\r
+\r
+       FreeRTOS.org is free software; you can redistribute it and/or modify it\r
+       under the terms of the GNU General Public License (version 2) as published\r
+       by the Free Software Foundation and modified by the FreeRTOS exception.\r
+       **NOTE** The exception to the GPL is included to allow you to distribute a\r
+       combined work that includes FreeRTOS.org without being obliged to provide\r
+       the source code for any proprietary components.  Alternative commercial\r
+       license and support terms are also available upon request.  See the \r
+       licensing section of http://www.FreeRTOS.org for full details.\r
+\r
+       FreeRTOS.org is distributed in the hope that it will be useful, but WITHOUT\r
+       ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\r
+       FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\r
+       more details.\r
+\r
+       You should have received a copy of the GNU General Public License along\r
+       with FreeRTOS.org; if not, write to the Free Software Foundation, Inc., 59\r
+       Temple Place, Suite 330, Boston, MA  02111-1307  USA.\r
+\r
+\r
+       ***************************************************************************\r
+       *                                                                         *\r
+       * Get the FreeRTOS eBook!  See http://www.FreeRTOS.org/Documentation      *\r
+       *                                                                         *\r
+       * This is a concise, step by step, 'hands on' guide that describes both   *\r
+       * general multitasking concepts and FreeRTOS specifics. It presents and   *\r
+       * explains numerous examples that are written using the FreeRTOS API.     *\r
+       * Full source code for all the examples is provided in an accompanying    *\r
+       * .zip file.                                                              *\r
+       *                                                                         *\r
+       ***************************************************************************\r
+\r
+       1 tab == 4 spaces!\r
+\r
+       Please ensure to read the configuration and relevant port sections of the\r
+       online documentation.\r
+\r
+       http://www.FreeRTOS.org - Documentation, latest information, license and\r
+       contact details.\r
+\r
+       http://www.SafeRTOS.com - A version that is certified for use in safety\r
+       critical systems.\r
+\r
+       http://www.OpenRTOS.com - Commercial support, development, porting,\r
+       licensing and training services.\r
+*/\r
+\r
+/*-----------------------------------------------------------\r
+ * Simple IO routines to control the LEDs.\r
+ *-----------------------------------------------------------*/\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Demo includes. */\r
+#include "partest.h"\r
+\r
+/* Library includes. */\r
+#include <board.h>\r
+#include <pio/pio.h>\r
+\r
+#define partestNUM_LEDS ( sizeof( xLEDPins ) / sizeof( Pin ) )\r
+\r
+static const Pin xLEDPins[] = { PINS_LEDS };\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestInitialise( void )\r
+{\r
+long l;\r
+\r
+       for( l = 0; l < partestNUM_LEDS; l++ )\r
+       {\r
+               PIO_Configure( &( xLEDPins[ l ] ), pdTRUE );\r
+       }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue )\r
+{\r
+       if( uxLED < partestNUM_LEDS )\r
+       {\r
+               if( xValue )\r
+               {\r
+                       /* Turn the LED on. */\r
+                       portENTER_CRITICAL();\r
+                       {\r
+                               if( xLEDPins[ uxLED ].type == PIO_OUTPUT_0 )\r
+                               {                       \r
+                                       PIO_Set( &( xLEDPins[ uxLED ]) );\r
+                               }\r
+                               else\r
+                               {                       \r
+                                       PIO_Clear( &( xLEDPins[ uxLED ] ) );\r
+                               }\r
+                       }\r
+                       portEXIT_CRITICAL();\r
+               }\r
+               else\r
+               {\r
+                       /* Turn the LED off. */\r
+                       portENTER_CRITICAL();\r
+                       {\r
+                               if( xLEDPins[ uxLED ].type == PIO_OUTPUT_0 )\r
+                               {                       \r
+                                       PIO_Clear( &( xLEDPins[ uxLED ] ) );\r
+                               }\r
+                               else\r
+                               {                       \r
+                                       PIO_Set( &( xLEDPins[ uxLED ] ) );\r
+                               }\r
+                       }\r
+                       portEXIT_CRITICAL();\r
+               }\r
+       }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestToggleLED( unsigned portBASE_TYPE uxLED )\r
+{\r
+       if( uxLED < partestNUM_LEDS )\r
+       {\r
+               if( PIO_GetOutputDataStatus( &( xLEDPins[ uxLED ] ) ) )\r
+               {               \r
+                       PIO_Clear( &( xLEDPins[ uxLED ] ) );\r
+               }\r
+               else\r
+               {               \r
+                       PIO_Set( &( xLEDPins[ uxLED ] ) );\r
+               }               \r
+       }\r
+}\r
+                                                       \r
+\r
+\r

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/RTOSDemo.ewd b/Demo/CORTEX_AT91SAM3U256_IAR/RTOSDemo.ewd
new file mode 100644 (file)
index 0000000..9cf6a61
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/RTOSDemo.ewd
@@ -0,0 +1,1307 @@
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<project>\r
+  <fileVersion>2</fileVersion>\r
+  <configuration>\r
+    <name>Debug</name>\r
+    <toolchain>\r
+      <name>ARM</name>\r
+    </toolchain>\r
+    <debug>1</debug>\r
+    <settings>\r
+      <name>C-SPY</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>18</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>CInput</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CEndian</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CProcessor</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OCVariant</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>MacOverride</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>MacFile</name>\r
+          <state>$PROJ_DIR$\system\at91sam3u-ek-flash.mac</state>\r
+        </option>\r
+        <option>\r
+          <name>MemOverride</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>MemFile</name>\r
+          <state>$TOOLKIT_DIR$\CONFIG\debugger\Atmel\ioAT91SAM3U4.ddf</state>\r
+        </option>\r
+        <option>\r
+          <name>RunToEnable</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>RunToName</name>\r
+          <state>main</state>\r
+        </option>\r
+        <option>\r
+          <name>CExtraOptionsCheck</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CExtraOptions</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CFpuProcessor</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDDFArgumentProducer</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>OCDownloadSuppressDownload</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDownloadVerifyAll</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OCProductVersion</name>\r
+          <state>5.30.0.51236</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDynDriverList</name>\r
+          <state>JLINK_ID</state>\r
+        </option>\r
+        <option>\r
+          <name>OCLastSavedByProductVersion</name>\r
+          <state>5.30.0.51236</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDownloadAttachToProgram</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>UseFlashLoader</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CLowLevel</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OCBE8Slave</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>MacFile2</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CDevice</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>FlashLoadersV2</name>\r
+          <state>,,,,(default),</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>ARMSIM_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>1</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>OCSimDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OCSimEnablePSP</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCSimPspOverrideConfig</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCSimPspConfigFile</name>\r
+          <state></state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>ANGEL_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>0</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>CCAngelHeartbeat</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CAngelCommunication</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CAngelCommBaud</name>\r
+          <version>0</version>\r
+          <state>3</state>\r
+        </option>\r
+        <option>\r
+          <name>CAngelCommPort</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>ANGELTCPIP</name>\r
+          <state>aaa.bbb.ccc.ddd</state>\r
+        </option>\r
+        <option>\r
+          <name>DoAngelLogfile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>AngelLogFile</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>GDBSERVER_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>0</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>TCPIP</name>\r
+          <state>aaa.bbb.ccc.ddd</state>\r
+        </option>\r
+        <option>\r
+          <name>DoLogfile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>LogFile</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJTagBreakpointRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJTagDoUpdateBreakpoints</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJTagUpdateBreakpoints</name>\r
+          <state>main</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>IARROM_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>0</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>CRomLogFileCheck</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CRomLogFileEditB</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>CRomCommunication</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CRomCommPort</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CRomCommBaud</name>\r
+          <version>0</version>\r
+          <state>7</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>JLINK_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>10</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>JLinkSpeed</name>\r
+          <state>32</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkDoLogfile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkLogFile</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkHWResetDelay</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>JLinkInitialSpeed</name>\r
+          <state>32</state>\r
+        </option>\r
+        <option>\r
+          <name>CCDoJlinkMultiTarget</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCScanChainNonARMDevices</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkMultiTarget</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkIRLength</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkCommRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkTCPIP</name>\r
+          <state>aaa.bbb.ccc.ddd</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkSpeedRadioV2</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCUSBDevice</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchReset</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchUndef</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchSWI</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchData</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchPrefetch</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchIRQ</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchFIQ</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkBreakpointRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkDoUpdateBreakpoints</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkUpdateBreakpoints</name>\r
+          <state>main</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkInterfaceRadio</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OCJLinkAttachSlave</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkResetList</name>\r
+          <version>0</version>\r
+          <state>7</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkInterfaceCmdLine</name>\r
+          <state>0</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>LMIFTDI_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>1</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>LmiftdiSpeed</name>\r
+          <state>500</state>\r
+        </option>\r
+        <option>\r
+          <name>CCLmiftdiDoLogfile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCLmiftdiLogFile</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>MACRAIGOR_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>3</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>jtag</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>EmuSpeed</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>TCPIP</name>\r
+          <state>aaa.bbb.ccc.ddd</state>\r
+        </option>\r
+        <option>\r
+          <name>DoLogfile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>LogFile</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>DoEmuMultiTarget</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>EmuMultiTarget</name>\r
+          <state>0@ARM7TDMI</state>\r
+        </option>\r
+        <option>\r
+          <name>EmuHWReset</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CEmuCommBaud</name>\r
+          <version>0</version>\r
+          <state>4</state>\r
+        </option>\r
+        <option>\r
+          <name>CEmuCommPort</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>jtago</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>UnusedAddr</name>\r
+          <state>0x00800000</state>\r
+        </option>\r
+        <option>\r
+          <name>CCMacraigorHWResetDelay</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CCJTagBreakpointRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJTagDoUpdateBreakpoints</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJTagUpdateBreakpoints</name>\r
+          <state>main</state>\r
+        </option>\r
+        <option>\r
+          <name>CCMacraigorInterfaceRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCMacraigorInterfaceCmdLine</name>\r
+          <state>0</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>RDI_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>1</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>CRDIDriverDll</name>\r
+          <state>###Uninitialized###</state>\r
+        </option>\r
+        <option>\r
+          <name>CRDILogFileCheck</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CRDILogFileEdit</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDIHWReset</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchReset</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchUndef</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchSWI</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchData</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchPrefetch</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchIRQ</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchFIQ</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDIUseETM</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>STLINK_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>0</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>THIRDPARTY_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>0</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>CThirdPartyDriverDll</name>\r
+          <state>###Uninitialized###</state>\r
+        </option>\r
+        <option>\r
+          <name>CThirdPartyLogFileCheck</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CThirdPartyLogFileEditB</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <debuggerPlugins>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\OSE\OseEpsilonPlugin.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>\r
+        <loadFlag>1</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$EW_DIR$\common\plugins\FreeRTOS\FreeRTOSPlugin.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$EW_DIR$\common\plugins\Profiling\Profiling.ENU.ewplugin</file>\r
+        <loadFlag>1</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$EW_DIR$\common\plugins\Stack\Stack.ENU.ewplugin</file>\r
+        <loadFlag>1</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>\r
+        <loadFlag>1</loadFlag>\r
+      </plugin>\r
+    </debuggerPlugins>\r
+  </configuration>\r
+  <configuration>\r
+    <name>Release</name>\r
+    <toolchain>\r
+      <name>ARM</name>\r
+    </toolchain>\r
+    <debug>1</debug>\r
+    <settings>\r
+      <name>C-SPY</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>18</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>CInput</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CEndian</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CProcessor</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OCVariant</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>MacOverride</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>MacFile</name>\r
+          <state>$PROJ_DIR$\system\at91sam3u-ek-flash.mac</state>\r
+        </option>\r
+        <option>\r
+          <name>MemOverride</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>MemFile</name>\r
+          <state>$TOOLKIT_DIR$\CONFIG\debugger\Atmel\ioAT91SAM3U4.ddf</state>\r
+        </option>\r
+        <option>\r
+          <name>RunToEnable</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>RunToName</name>\r
+          <state>main</state>\r
+        </option>\r
+        <option>\r
+          <name>CExtraOptionsCheck</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CExtraOptions</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CFpuProcessor</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDDFArgumentProducer</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>OCDownloadSuppressDownload</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDownloadVerifyAll</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OCProductVersion</name>\r
+          <state>5.30.0.51236</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDynDriverList</name>\r
+          <state>JLINK_ID</state>\r
+        </option>\r
+        <option>\r
+          <name>OCLastSavedByProductVersion</name>\r
+          <state>5.30.0.51236</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDownloadAttachToProgram</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>UseFlashLoader</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CLowLevel</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OCBE8Slave</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>MacFile2</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CDevice</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>FlashLoadersV2</name>\r
+          <state>,,,,(default),</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>ARMSIM_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>1</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>OCSimDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OCSimEnablePSP</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCSimPspOverrideConfig</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCSimPspConfigFile</name>\r
+          <state></state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>ANGEL_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>0</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>CCAngelHeartbeat</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CAngelCommunication</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CAngelCommBaud</name>\r
+          <version>0</version>\r
+          <state>3</state>\r
+        </option>\r
+        <option>\r
+          <name>CAngelCommPort</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>ANGELTCPIP</name>\r
+          <state>aaa.bbb.ccc.ddd</state>\r
+        </option>\r
+        <option>\r
+          <name>DoAngelLogfile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>AngelLogFile</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>GDBSERVER_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>0</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>TCPIP</name>\r
+          <state>aaa.bbb.ccc.ddd</state>\r
+        </option>\r
+        <option>\r
+          <name>DoLogfile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>LogFile</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJTagBreakpointRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJTagDoUpdateBreakpoints</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJTagUpdateBreakpoints</name>\r
+          <state>main</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>IARROM_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>0</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>CRomLogFileCheck</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CRomLogFileEditB</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>CRomCommunication</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CRomCommPort</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CRomCommBaud</name>\r
+          <version>0</version>\r
+          <state>7</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>JLINK_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>10</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>JLinkSpeed</name>\r
+          <state>32</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkDoLogfile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkLogFile</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkHWResetDelay</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>JLinkInitialSpeed</name>\r
+          <state>32</state>\r
+        </option>\r
+        <option>\r
+          <name>CCDoJlinkMultiTarget</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCScanChainNonARMDevices</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkMultiTarget</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkIRLength</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkCommRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkTCPIP</name>\r
+          <state>aaa.bbb.ccc.ddd</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkSpeedRadioV2</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCUSBDevice</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchReset</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchUndef</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchSWI</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchData</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchPrefetch</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchIRQ</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchFIQ</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkBreakpointRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkDoUpdateBreakpoints</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkUpdateBreakpoints</name>\r
+          <state>main</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkInterfaceRadio</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OCJLinkAttachSlave</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkResetList</name>\r
+          <version>0</version>\r
+          <state>7</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkInterfaceCmdLine</name>\r
+          <state>0</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>LMIFTDI_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>1</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>LmiftdiSpeed</name>\r
+          <state>500</state>\r
+        </option>\r
+        <option>\r
+          <name>CCLmiftdiDoLogfile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCLmiftdiLogFile</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>MACRAIGOR_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>3</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>jtag</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>EmuSpeed</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>TCPIP</name>\r
+          <state>aaa.bbb.ccc.ddd</state>\r
+        </option>\r
+        <option>\r
+          <name>DoLogfile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>LogFile</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>DoEmuMultiTarget</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>EmuMultiTarget</name>\r
+          <state>0@ARM7TDMI</state>\r
+        </option>\r
+        <option>\r
+          <name>EmuHWReset</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CEmuCommBaud</name>\r
+          <version>0</version>\r
+          <state>4</state>\r
+        </option>\r
+        <option>\r
+          <name>CEmuCommPort</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>jtago</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>UnusedAddr</name>\r
+          <state>0x00800000</state>\r
+        </option>\r
+        <option>\r
+          <name>CCMacraigorHWResetDelay</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CCJTagBreakpointRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJTagDoUpdateBreakpoints</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJTagUpdateBreakpoints</name>\r
+          <state>main</state>\r
+        </option>\r
+        <option>\r
+          <name>CCMacraigorInterfaceRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCMacraigorInterfaceCmdLine</name>\r
+          <state>0</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>RDI_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>1</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>CRDIDriverDll</name>\r
+          <state>###Uninitialized###</state>\r
+        </option>\r
+        <option>\r
+          <name>CRDILogFileCheck</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CRDILogFileEdit</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDIHWReset</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchReset</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchUndef</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchSWI</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchData</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchPrefetch</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchIRQ</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchFIQ</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDIUseETM</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>STLINK_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>0</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>THIRDPARTY_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>0</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>CThirdPartyDriverDll</name>\r
+          <state>###Uninitialized###</state>\r
+        </option>\r
+        <option>\r
+          <name>CThirdPartyLogFileCheck</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CThirdPartyLogFileEditB</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <debuggerPlugins>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\OSE\OseEpsilonPlugin.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>\r
+        <loadFlag>1</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$EW_DIR$\common\plugins\FreeRTOS\FreeRTOSPlugin.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$EW_DIR$\common\plugins\Profiling\Profiling.ENU.ewplugin</file>\r
+        <loadFlag>1</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$EW_DIR$\common\plugins\Stack\Stack.ENU.ewplugin</file>\r
+        <loadFlag>1</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>\r
+        <loadFlag>1</loadFlag>\r
+      </plugin>\r
+    </debuggerPlugins>\r
+  </configuration>\r
+</project>\r
+\r
+\r

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/RTOSDemo.ewp b/Demo/CORTEX_AT91SAM3U256_IAR/RTOSDemo.ewp
new file mode 100644 (file)
index 0000000..5687e0d
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/RTOSDemo.ewp
@@ -0,0 +1,1712 @@
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<project>\r
+  <fileVersion>2</fileVersion>\r
+  <configuration>\r
+    <name>Debug</name>\r
+    <toolchain>\r
+      <name>ARM</name>\r
+    </toolchain>\r
+    <debug>1</debug>\r
+    <settings>\r
+      <name>General</name>\r
+      <archiveVersion>3</archiveVersion>\r
+      <data>\r
+        <version>17</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>ExePath</name>\r
+          <state>Debug\Exe</state>\r
+        </option>\r
+        <option>\r
+          <name>ObjPath</name>\r
+          <state>Debug\Obj</state>\r
+        </option>\r
+        <option>\r
+          <name>ListPath</name>\r
+          <state>Debug\List</state>\r
+        </option>\r
+        <option>\r
+          <name>Variant</name>\r
+          <version>9</version>\r
+          <state>33</state>\r
+        </option>\r
+        <option>\r
+          <name>GEndianMode</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>Input variant</name>\r
+          <version>1</version>\r
+          <state>3</state>\r
+        </option>\r
+        <option>\r
+          <name>Input description</name>\r
+          <state>No specifier n, no float nor long long, no scan set, no assignment suppressing.</state>\r
+        </option>\r
+        <option>\r
+          <name>Output variant</name>\r
+          <version>0</version>\r
+          <state>3</state>\r
+        </option>\r
+        <option>\r
+          <name>Output description</name>\r
+          <state>No specifier a, A, no specifier n, no float nor long long, no flags.</state>\r
+        </option>\r
+        <option>\r
+          <name>GOutputBinary</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>FPU</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OGCoreOrChip</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>GRuntimeLibSelect</name>\r
+          <version>0</version>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>GRuntimeLibSelectSlave</name>\r
+          <version>0</version>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>RTDescription</name>\r
+          <state>Use the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>\r
+        </option>\r
+        <option>\r
+          <name>RTConfigPath</name>\r
+          <state>$TOOLKIT_DIR$\INC\DLib_Config_Normal.h</state>\r
+        </option>\r
+        <option>\r
+          <name>OGProductVersion</name>\r
+          <state>5.10.0.159</state>\r
+        </option>\r
+        <option>\r
+          <name>OGLastSavedByProductVersion</name>\r
+          <state>5.30.0.51236</state>\r
+        </option>\r
+        <option>\r
+          <name>GeneralEnableMisra</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>GeneralMisraVerbose</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OGChipSelectEditMenu</name>\r
+          <state>AT91SAM3U4    Atmel AT91SAM3U4</state>\r
+        </option>\r
+        <option>\r
+          <name>GenLowLevelInterface</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>GEndianModeBE</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OGBufferedTerminalOutput</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>GenStdoutInterface</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>GeneralMisraRules98</name>\r
+          <version>0</version>\r
+          <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>\r
+        </option>\r
+        <option>\r
+          <name>GeneralMisraVer</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>GeneralMisraRules04</name>\r
+          <version>0</version>\r
+          <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>ICCARM</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>21</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>CCDefines</name>\r
+          <state>at91sam3u4</state>\r
+          <state>flash</state>\r
+        </option>\r
+        <option>\r
+          <name>CCPreprocFile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCPreprocComments</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCPreprocLine</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCListCFile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCListCMnemonics</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCListCMessages</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCListAssFile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCListAssSource</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCEnableRemarks</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCDiagSuppress</name>\r
+          <state>pa082</state>\r
+        </option>\r
+        <option>\r
+          <name>CCDiagRemark</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CCDiagWarning</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CCDiagError</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CCObjPrefix</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CCAllowList</name>\r
+          <version>1</version>\r
+          <state>0000000</state>\r
+        </option>\r
+        <option>\r
+          <name>CCDebugInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IEndianMode</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IProcessor</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IExtraOptionsCheck</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IExtraOptions</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CCLangConformance</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCSignedPlainChar</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRequirePrototypes</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCMultibyteSupport</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCDiagWarnAreErr</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCompilerRuntimeInfo</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IFpuProcessor</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OutputFile</name>\r
+          <state>$FILE_BNAME$.o</state>\r
+        </option>\r
+        <option>\r
+          <name>CCLangSelect</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCLibConfigHeader</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>PreInclude</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CompilerMisraOverride</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCIncludePath2</name>\r
+          <state>$PROJ_DIR$/system</state>\r
+          <state>$PROJ_DIR$/AT91Lib/peripherals</state>\r
+          <state>$PROJ_DIR$/AT91Lib/components</state>\r
+          <state>$PROJ_DIR$/AT91Lib/drivers</state>\r
+          <state>$PROJ_DIR$/AT91Lib</state>\r
+          <state>$PROJ_DIR$/../../Source/include</state>\r
+          <state>$PROJ_DIR$/../../Source/portable/IAR/ARM_CM3</state>\r
+          <state>$PROJ_DIR$/.</state>\r
+          <state>$PROJ_DIR$/../common/include</state>\r
+        </option>\r
+        <option>\r
+          <name>CCStdIncCheck</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCStdIncludePath</name>\r
+          <state>$TOOLKIT_DIR$\INC\</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCodeSection</name>\r
+          <state>.text</state>\r
+        </option>\r
+        <option>\r
+          <name>IInterwork2</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IProcessorMode2</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CCOptLevel</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CCOptStrategy</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCOptLevelSlave</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CompilerMisraRules98</name>\r
+          <version>0</version>\r
+          <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>\r
+        </option>\r
+        <option>\r
+          <name>CompilerMisraRules04</name>\r
+          <version>0</version>\r
+          <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>AARM</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>7</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>AObjPrefix</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>AEndian</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>ACaseSensitivity</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>MacroChars</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>AWarnEnable</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>AWarnWhat</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>AWarnOne</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>AWarnRange1</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>AWarnRange2</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>ADebug</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>AltRegisterNames</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>ADefines</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>AList</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>AListHeader</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>AListing</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>Includes</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>MacDefs</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>MacExps</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>MacExec</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OnlyAssed</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>MultiLine</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>PageLengthCheck</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>PageLength</name>\r
+          <state>80</state>\r
+        </option>\r
+        <option>\r
+          <name>TabSpacing</name>\r
+          <state>8</state>\r
+        </option>\r
+        <option>\r
+          <name>AXRef</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>AXRefDefines</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>AXRefInternal</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>AXRefDual</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>AProcessor</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>AFpuProcessor</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>AOutputFile</name>\r
+          <state>$FILE_BNAME$.o</state>\r
+        </option>\r
+        <option>\r
+          <name>AMultibyteSupport</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>ALimitErrorsCheck</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>ALimitErrorsEdit</name>\r
+          <state>100</state>\r
+        </option>\r
+        <option>\r
+          <name>AIgnoreStdInclude</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>AStdIncludes</name>\r
+          <state>$TOOLKIT_DIR$\INC\</state>\r
+        </option>\r
+        <option>\r
+          <name>AUserIncludes</name>\r
+          <state>$PROJ_DIR$/.</state>\r
+        </option>\r
+        <option>\r
+          <name>AExtraOptionsCheckV2</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>AExtraOptionsV2</name>\r
+          <state></state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>OBJCOPY</name>\r
+      <archiveVersion>0</archiveVersion>\r
+      <data>\r
+        <version>1</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>OOCOutputFormat</name>\r
+          <version>2</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCOutputOverride</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OOCOutputFile</name>\r
+          <state>RTOSDemo.srec</state>\r
+        </option>\r
+        <option>\r
+          <name>OOCCommandLineProducer</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OOCObjCopyEnable</name>\r
+          <state>0</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>CUSTOM</name>\r
+      <archiveVersion>3</archiveVersion>\r
+      <data>\r
+        <extensions></extensions>\r
+        <cmdline></cmdline>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>BICOMP</name>\r
+      <archiveVersion>0</archiveVersion>\r
+      <data/>\r
+    </settings>\r
+    <settings>\r
+      <name>BUILDACTION</name>\r
+      <archiveVersion>1</archiveVersion>\r
+      <data>\r
+        <prebuild></prebuild>\r
+        <postbuild></postbuild>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>ILINK</name>\r
+      <archiveVersion>0</archiveVersion>\r
+      <data>\r
+        <version>7</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>IlinkOutputFile</name>\r
+          <state>RTOSDemo.out</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkLibIOConfig</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>XLinkMisraHandler</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkInputFileSlave</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkDebugInfoEnable</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkKeepSymbols</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkRawBinaryFile</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkRawBinarySymbol</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkRawBinarySegment</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkRawBinaryAlign</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkDefines</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkConfigDefines</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkMapFile</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkLogFile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkLogInitialization</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkLogModule</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkLogSection</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkLogVeneer</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkIcfOverride</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkIcfFile</name>\r
+          <state>$PROJ_DIR$\system\flash.icf</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkIcfFileSlave</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkEnableRemarks</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkSuppressDiags</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkTreatAsRem</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkTreatAsWarn</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkTreatAsErr</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkWarningsAreErrors</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkUseExtraOptions</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkExtraOptions</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkLowLevelInterfaceSlave</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkAutoLibEnable</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkAdditionalLibs</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkOverrideProgramEntryLabel</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkProgramEntryLabelSelect</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkProgramEntryLabel</name>\r
+          <state>__iar_program_start</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkNXPLPCChecksum</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>DoFill</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>FillerByte</name>\r
+          <state>0xFF</state>\r
+        </option>\r
+        <option>\r
+          <name>FillerStart</name>\r
+          <state>0x0</state>\r
+        </option>\r
+        <option>\r
+          <name>FillerEnd</name>\r
+          <state>0x0</state>\r
+        </option>\r
+        <option>\r
+          <name>CrcSize</name>\r
+          <version>0</version>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CrcAlign</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CrcAlgo</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CrcPoly</name>\r
+          <state>0x11021</state>\r
+        </option>\r
+        <option>\r
+          <name>CrcCompl</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CrcBitOrder</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CrcInitialValue</name>\r
+          <state>0x0</state>\r
+        </option>\r
+        <option>\r
+          <name>DoCrc</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkBE8Slave</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkBufferedTerminalOutput</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkStdoutInterfaceSlave</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CrcFullSize</name>\r
+          <state>0</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>IARCHIVE</name>\r
+      <archiveVersion>0</archiveVersion>\r
+      <data>\r
+        <version>0</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>IarchiveInputs</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IarchiveOverride</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IarchiveOutput</name>\r
+          <state>###Unitialized###</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>BILINK</name>\r
+      <archiveVersion>0</archiveVersion>\r
+      <data/>\r
+    </settings>\r
+  </configuration>\r
+  <configuration>\r
+    <name>Release</name>\r
+    <toolchain>\r
+      <name>ARM</name>\r
+    </toolchain>\r
+    <debug>1</debug>\r
+    <settings>\r
+      <name>General</name>\r
+      <archiveVersion>3</archiveVersion>\r
+      <data>\r
+        <version>17</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>ExePath</name>\r
+          <state>Release\Exe</state>\r
+        </option>\r
+        <option>\r
+          <name>ObjPath</name>\r
+          <state>Release\Obj</state>\r
+        </option>\r
+        <option>\r
+          <name>ListPath</name>\r
+          <state>Release\List</state>\r
+        </option>\r
+        <option>\r
+          <name>Variant</name>\r
+          <version>9</version>\r
+          <state>33</state>\r
+        </option>\r
+        <option>\r
+          <name>GEndianMode</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>Input variant</name>\r
+          <version>1</version>\r
+          <state>3</state>\r
+        </option>\r
+        <option>\r
+          <name>Input description</name>\r
+          <state>No specifier n, no float nor long long, no scan set, no assignment suppressing.</state>\r
+        </option>\r
+        <option>\r
+          <name>Output variant</name>\r
+          <version>0</version>\r
+          <state>3</state>\r
+        </option>\r
+        <option>\r
+          <name>Output description</name>\r
+          <state>No specifier a, A, no specifier n, no float nor long long, no flags.</state>\r
+        </option>\r
+        <option>\r
+          <name>GOutputBinary</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>FPU</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OGCoreOrChip</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>GRuntimeLibSelect</name>\r
+          <version>0</version>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>GRuntimeLibSelectSlave</name>\r
+          <version>0</version>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>RTDescription</name>\r
+          <state>Use the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>\r
+        </option>\r
+        <option>\r
+          <name>RTConfigPath</name>\r
+          <state>$TOOLKIT_DIR$\INC\DLib_Config_Normal.h</state>\r
+        </option>\r
+        <option>\r
+          <name>OGProductVersion</name>\r
+          <state>5.10.0.159</state>\r
+        </option>\r
+        <option>\r
+          <name>OGLastSavedByProductVersion</name>\r
+          <state>5.30.0.51236</state>\r
+        </option>\r
+        <option>\r
+          <name>GeneralEnableMisra</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>GeneralMisraVerbose</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OGChipSelectEditMenu</name>\r
+          <state>AT91SAM3U4    Atmel AT91SAM3U4</state>\r
+        </option>\r
+        <option>\r
+          <name>GenLowLevelInterface</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>GEndianModeBE</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OGBufferedTerminalOutput</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>GenStdoutInterface</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>GeneralMisraRules98</name>\r
+          <version>0</version>\r
+          <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>\r
+        </option>\r
+        <option>\r
+          <name>GeneralMisraVer</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>GeneralMisraRules04</name>\r
+          <version>0</version>\r
+          <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>ICCARM</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>21</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>CCDefines</name>\r
+          <state>at91sam3u4</state>\r
+          <state>flash</state>\r
+        </option>\r
+        <option>\r
+          <name>CCPreprocFile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCPreprocComments</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCPreprocLine</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCListCFile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCListCMnemonics</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCListCMessages</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCListAssFile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCListAssSource</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCEnableRemarks</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCDiagSuppress</name>\r
+          <state>pa082</state>\r
+        </option>\r
+        <option>\r
+          <name>CCDiagRemark</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CCDiagWarning</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CCDiagError</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CCObjPrefix</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CCAllowList</name>\r
+          <version>1</version>\r
+          <state>1111101</state>\r
+        </option>\r
+        <option>\r
+          <name>CCDebugInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IEndianMode</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IProcessor</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IExtraOptionsCheck</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IExtraOptions</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CCLangConformance</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCSignedPlainChar</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRequirePrototypes</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCMultibyteSupport</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCDiagWarnAreErr</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCompilerRuntimeInfo</name>\r
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+          <name>AOutputFile</name>\r
+          <state>$FILE_BNAME$.o</state>\r
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+          <name>AMultibyteSupport</name>\r
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+          <state>$TOOLKIT_DIR$\INC\</state>\r
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+          <name>AUserIncludes</name>\r
+          <state>$PROJ_DIR$/.</state>\r
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+          <state>0</state>\r
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+        <option>\r
+          <name>AExtraOptionsV2</name>\r
+          <state></state>\r
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+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>OBJCOPY</name>\r
+      <archiveVersion>0</archiveVersion>\r
+      <data>\r
+        <version>1</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
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+          <name>OCOutputOverride</name>\r
+          <state>0</state>\r
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+          <name>OOCOutputFile</name>\r
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+          <state>1</state>\r
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+        <option>\r
+          <name>OOCObjCopyEnable</name>\r
+          <state>0</state>\r
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+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>CUSTOM</name>\r
+      <archiveVersion>3</archiveVersion>\r
+      <data>\r
+        <extensions></extensions>\r
+        <cmdline></cmdline>\r
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+    </settings>\r
+    <settings>\r
+      <name>BICOMP</name>\r
+      <archiveVersion>0</archiveVersion>\r
+      <data/>\r
+    </settings>\r
+    <settings>\r
+      <name>BUILDACTION</name>\r
+      <archiveVersion>1</archiveVersion>\r
+      <data>\r
+        <prebuild></prebuild>\r
+        <postbuild></postbuild>\r
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+    </settings>\r
+    <settings>\r
+      <name>ILINK</name>\r
+      <archiveVersion>0</archiveVersion>\r
+      <data>\r
+        <version>7</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>IlinkOutputFile</name>\r
+          <state>RTOSDemo.out</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkLibIOConfig</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>XLinkMisraHandler</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkInputFileSlave</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkDebugInfoEnable</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkKeepSymbols</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkRawBinaryFile</name>\r
+          <state></state>\r
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+        <option>\r
+          <name>IlinkRawBinarySymbol</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkRawBinarySegment</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkRawBinaryAlign</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkDefines</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkConfigDefines</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkMapFile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkLogFile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkLogInitialization</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkLogModule</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkLogSection</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkLogVeneer</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkIcfOverride</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkIcfFile</name>\r
+          <state>C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\CORTEX_AT91SAM3U256_IAR\system\flash.icf</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkIcfFileSlave</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkEnableRemarks</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkSuppressDiags</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkTreatAsRem</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkTreatAsWarn</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkTreatAsErr</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkWarningsAreErrors</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkUseExtraOptions</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkExtraOptions</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkLowLevelInterfaceSlave</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkAutoLibEnable</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkAdditionalLibs</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkOverrideProgramEntryLabel</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkProgramEntryLabelSelect</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkProgramEntryLabel</name>\r
+          <state>__iar_program_start</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkNXPLPCChecksum</name>\r
+          <state>0</state>\r
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+        <option>\r
+          <name>DoFill</name>\r
+          <state>0</state>\r
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+        <option>\r
+          <name>FillerByte</name>\r
+          <state>0xFF</state>\r
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+          <name>FillerStart</name>\r
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+          <name>FillerEnd</name>\r
+          <state>0x0</state>\r
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+        <option>\r
+          <name>CrcSize</name>\r
+          <version>0</version>\r
+          <state>1</state>\r
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+        <option>\r
+          <name>CrcAlign</name>\r
+          <state>1</state>\r
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+        <option>\r
+          <name>CrcAlgo</name>\r
+          <state>1</state>\r
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+          <name>CrcPoly</name>\r
+          <state>0x11021</state>\r
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+          <version>0</version>\r
+          <state>0</state>\r
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+        <option>\r
+          <name>CrcBitOrder</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CrcInitialValue</name>\r
+          <state>0x0</state>\r
+        </option>\r
+        <option>\r
+          <name>DoCrc</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkBE8Slave</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkBufferedTerminalOutput</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkStdoutInterfaceSlave</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CrcFullSize</name>\r
+          <state>0</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>IARCHIVE</name>\r
+      <archiveVersion>0</archiveVersion>\r
+      <data>\r
+        <version>0</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>IarchiveInputs</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IarchiveOverride</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IarchiveOutput</name>\r
+          <state>###Unitialized###</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>BILINK</name>\r
+      <archiveVersion>0</archiveVersion>\r
+      <data/>\r
+    </settings>\r
+  </configuration>\r
+  <group>\r
+    <name>AT91Lib</name>\r
+    <file>\r
+      <name>$PROJ_DIR$\AT91Lib\drivers\lcd\draw_hx8347.c</name>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\AT91Lib\drivers\lcd\font.c</name>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\AT91Lib\components\hx8347\hx8347.c</name>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\AT91Lib\peripherals\lcd\lcd.c</name>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\AT91Lib\drivers\lcd\lcdd_hx8347.c</name>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\AT91Lib\peripherals\irq\nvic.c</name>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\AT91Lib\peripherals\pio\pio.c</name>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\AT91Lib\peripherals\pmc\pmc.c</name>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\AT91Lib\peripherals\usart\usart.c</name>\r
+    </file>\r
+  </group>\r
+  <group>\r
+    <name>Common Demo Source</name>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\Common\Minimal\BlockQ.c</name>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\Common\Minimal\blocktim.c</name>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\Common\Minimal\comtest.c</name>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\Common\Minimal\flash.c</name>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\Common\Minimal\GenQTest.c</name>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\Common\Minimal\integer.c</name>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\Common\Minimal\PollQ.c</name>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\Common\Minimal\QPeek.c</name>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\Common\Minimal\recmutex.c</name>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\Common\Minimal\semtest.c</name>\r
+    </file>\r
+  </group>\r
+  <group>\r
+    <name>FreeRTOS Source</name>\r
+    <group>\r
+      <name>port layer</name>\r
+      <file>\r
+        <name>$PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM3\port.c</name>\r
+      </file>\r
+      <file>\r
+        <name>$PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM3\portasm.s</name>\r
+      </file>\r
+    </group>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\..\Source\portable\MemMang\heap_2.c</name>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\..\Source\list.c</name>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\..\Source\queue.c</name>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\serial\serial.c</name>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\..\Source\tasks.c</name>\r
+    </file>\r
+  </group>\r
+  <group>\r
+    <name>System</name>\r
+    <file>\r
+      <name>$PROJ_DIR$\system\board_cstartup_iar.c</name>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\system\board_lowlevel.c</name>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\system\board_memories.c</name>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\system\exceptions.c</name>\r
+    </file>\r
+  </group>\r
+  <file>\r
+    <name>$PROJ_DIR$\main.c</name>\r
+  </file>\r
+  <file>\r
+    <name>$PROJ_DIR$\ParTest\ParTest.c</name>\r
+  </file>\r
+</project>\r
+\r
+\r

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/RTOSDemo.eww b/Demo/CORTEX_AT91SAM3U256_IAR/RTOSDemo.eww
new file mode 100644 (file)
index 0000000..239a938
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/RTOSDemo.eww
@@ -0,0 +1,10 @@
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<workspace>\r
+  <project>\r
+    <path>$WS_DIR$\RTOSDemo.ewp</path>\r
+  </project>\r
+  <batchBuild/>\r
+</workspace>\r
+\r
+\r

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/Release/Exe/RTOSDemo.sim b/Demo/CORTEX_AT91SAM3U256_IAR/Release/Exe/RTOSDemo.sim
new file mode 100644 (file)
index 0000000..0aef29c
Binary files /dev/null and b/Demo/CORTEX_AT91SAM3U256_IAR/Release/Exe/RTOSDemo.sim differ

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/Release/Exe/RTOSDemo.sim._1 b/Demo/CORTEX_AT91SAM3U256_IAR/Release/Exe/RTOSDemo.sim._1
new file mode 100644 (file)
index 0000000..0aef29c
Binary files /dev/null and b/Demo/CORTEX_AT91SAM3U256_IAR/Release/Exe/RTOSDemo.sim._1 differ

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/Release/Obj/RTOSDemo.pbd b/Demo/CORTEX_AT91SAM3U256_IAR/Release/Obj/RTOSDemo.pbd
new file mode 100644 (file)
index 0000000..c8d765a
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/Release/Obj/RTOSDemo.pbd
@@ -0,0 +1,33 @@
+This is an internal working file generated by the Source Browser.\r
+13:26 47s\r
+C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\CORTEX_AT91SAM3U256_IAR\Release\Obj\BlockQ.pbi\r
+C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\CORTEX_AT91SAM3U256_IAR\Release\Obj\GenQTest.pbi\r
+C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\CORTEX_AT91SAM3U256_IAR\Release\Obj\ParTest.pbi\r
+C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\CORTEX_AT91SAM3U256_IAR\Release\Obj\PollQ.pbi\r
+C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\CORTEX_AT91SAM3U256_IAR\Release\Obj\QPeek.pbi\r
+C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\CORTEX_AT91SAM3U256_IAR\Release\Obj\blocktim.pbi\r
+C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\CORTEX_AT91SAM3U256_IAR\Release\Obj\board_cstartup_iar.pbi\r
+C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\CORTEX_AT91SAM3U256_IAR\Release\Obj\board_lowlevel.pbi\r
+C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\CORTEX_AT91SAM3U256_IAR\Release\Obj\board_memories.pbi\r
+C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\CORTEX_AT91SAM3U256_IAR\Release\Obj\comtest.pbi\r
+C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\CORTEX_AT91SAM3U256_IAR\Release\Obj\draw_hx8347.pbi\r
+C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\CORTEX_AT91SAM3U256_IAR\Release\Obj\exceptions.pbi\r
+C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\CORTEX_AT91SAM3U256_IAR\Release\Obj\flash.pbi\r
+C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\CORTEX_AT91SAM3U256_IAR\Release\Obj\font.pbi\r
+C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\CORTEX_AT91SAM3U256_IAR\Release\Obj\heap_2.pbi\r
+C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\CORTEX_AT91SAM3U256_IAR\Release\Obj\hx8347.pbi\r
+C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\CORTEX_AT91SAM3U256_IAR\Release\Obj\integer.pbi\r
+C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\CORTEX_AT91SAM3U256_IAR\Release\Obj\lcd.pbi\r
+C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\CORTEX_AT91SAM3U256_IAR\Release\Obj\lcdd_hx8347.pbi\r
+C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\CORTEX_AT91SAM3U256_IAR\Release\Obj\list.pbi\r
+C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\CORTEX_AT91SAM3U256_IAR\Release\Obj\main.pbi\r
+C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\CORTEX_AT91SAM3U256_IAR\Release\Obj\nvic.pbi\r
+C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\CORTEX_AT91SAM3U256_IAR\Release\Obj\pio.pbi\r
+C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\CORTEX_AT91SAM3U256_IAR\Release\Obj\pmc.pbi\r
+C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\CORTEX_AT91SAM3U256_IAR\Release\Obj\port.pbi\r
+C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\CORTEX_AT91SAM3U256_IAR\Release\Obj\queue.pbi\r
+C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\CORTEX_AT91SAM3U256_IAR\Release\Obj\recmutex.pbi\r
+C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\CORTEX_AT91SAM3U256_IAR\Release\Obj\semtest.pbi\r
+C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\CORTEX_AT91SAM3U256_IAR\Release\Obj\serial.pbi\r
+C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\CORTEX_AT91SAM3U256_IAR\Release\Obj\tasks.pbi\r
+C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\CORTEX_AT91SAM3U256_IAR\Release\Obj\usart.pbi\r

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/lcd_message.h b/Demo/CORTEX_AT91SAM3U256_IAR/lcd_message.h
new file mode 100644 (file)
index 0000000..d9b5210
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/lcd_message.h
@@ -0,0 +1,60 @@
+/*\r
+       FreeRTOS.org V5.3.0 - Copyright (C) 2003-2009 Richard Barry.\r
+\r
+       This file is part of the FreeRTOS.org distribution.\r
+\r
+       FreeRTOS.org is free software; you can redistribute it and/or modify it\r
+       under the terms of the GNU General Public License (version 2) as published\r
+       by the Free Software Foundation and modified by the FreeRTOS exception.\r
+       **NOTE** The exception to the GPL is included to allow you to distribute a\r
+       combined work that includes FreeRTOS.org without being obliged to provide\r
+       the source code for any proprietary components.  Alternative commercial\r
+       license and support terms are also available upon request.  See the \r
+       licensing section of http://www.FreeRTOS.org for full details.\r
+\r
+       FreeRTOS.org is distributed in the hope that it will be useful, but WITHOUT\r
+       ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\r
+       FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\r
+       more details.\r
+\r
+       You should have received a copy of the GNU General Public License along\r
+       with FreeRTOS.org; if not, write to the Free Software Foundation, Inc., 59\r
+       Temple Place, Suite 330, Boston, MA  02111-1307  USA.\r
+\r
+\r
+       ***************************************************************************\r
+       *                                                                         *\r
+       * Get the FreeRTOS eBook!  See http://www.FreeRTOS.org/Documentation      *\r
+       *                                                                         *\r
+       * This is a concise, step by step, 'hands on' guide that describes both   *\r
+       * general multitasking concepts and FreeRTOS specifics. It presents and   *\r
+       * explains numerous examples that are written using the FreeRTOS API.     *\r
+       * Full source code for all the examples is provided in an accompanying    *\r
+       * .zip file.                                                              *\r
+       *                                                                         *\r
+       ***************************************************************************\r
+\r
+       1 tab == 4 spaces!\r
+\r
+       Please ensure to read the configuration and relevant port sections of the\r
+       online documentation.\r
+\r
+       http://www.FreeRTOS.org - Documentation, latest information, license and\r
+       contact details.\r
+\r
+       http://www.SafeRTOS.com - A version that is certified for use in safety\r
+       critical systems.\r
+\r
+       http://www.OpenRTOS.com - Commercial support, development, porting,\r
+       licensing and training services.\r
+*/\r
+\r
+#ifndef LCD_MESSAGE_H\r
+#define LCD_MESSAGE_H\r
+\r
+typedef struct\r
+{\r
+       char const *pcMessage;\r
+} xLCDMessage;\r
+\r
+#endif /* LCD_MESSAGE_H */\r

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/main.c b/Demo/CORTEX_AT91SAM3U256_IAR/main.c
new file mode 100644 (file)
index 0000000..6a8095d
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/main.c
@@ -0,0 +1,317 @@
+/*\r
+       FreeRTOS.org V5.3.0 - Copyright (C) 2003-2009 Richard Barry.\r
+\r
+       This file is part of the FreeRTOS.org distribution.\r
+\r
+       FreeRTOS.org is free software; you can redistribute it and/or modify it\r
+       under the terms of the GNU General Public License (version 2) as published\r
+       by the Free Software Foundation and modified by the FreeRTOS exception.\r
+       **NOTE** The exception to the GPL is included to allow you to distribute a\r
+       combined work that includes FreeRTOS.org without being obliged to provide\r
+       the source code for any proprietary components.  Alternative commercial\r
+       license and support terms are also available upon request.  See the \r
+       licensing section of http://www.FreeRTOS.org for full details.\r
+\r
+       FreeRTOS.org is distributed in the hope that it will be useful, but WITHOUT\r
+       ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\r
+       FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\r
+       more details.\r
+\r
+       You should have received a copy of the GNU General Public License along\r
+       with FreeRTOS.org; if not, write to the Free Software Foundation, Inc., 59\r
+       Temple Place, Suite 330, Boston, MA  02111-1307  USA.\r
+\r
+\r
+       ***************************************************************************\r
+       *                                                                         *\r
+       * Get the FreeRTOS eBook!  See http://www.FreeRTOS.org/Documentation      *\r
+       *                                                                         *\r
+       * This is a concise, step by step, 'hands on' guide that describes both   *\r
+       * general multitasking concepts and FreeRTOS specifics. It presents and   *\r
+       * explains numerous examples that are written using the FreeRTOS API.     *\r
+       * Full source code for all the examples is provided in an accompanying    *\r
+       * .zip file.                                                              *\r
+       *                                                                         *\r
+       ***************************************************************************\r
+\r
+       1 tab == 4 spaces!\r
+\r
+       Please ensure to read the configuration and relevant port sections of the\r
+       online documentation.\r
+\r
+       http://www.FreeRTOS.org - Documentation, latest information, license and\r
+       contact details.\r
+\r
+       http://www.SafeRTOS.com - A version that is certified for use in safety\r
+       critical systems.\r
+\r
+       http://www.OpenRTOS.com - Commercial support, development, porting,\r
+       licensing and training services.\r
+*/\r
+\r
+/*\r
+ * Creates all the demo application tasks, then starts the scheduler.  The WEB\r
+ * documentation provides more details of the standard demo application tasks\r
+ * (which just exist to test the kernel port and provide an example of how to use\r
+ * each FreeRTOS API function).\r
+ *\r
+ * In addition to the standard demo tasks, the following tasks and tests are\r
+ * defined and/or created within this file:\r
+ *\r
+ * "LCD" task - the LCD task is a 'gatekeeper' task.  It is the only task that\r
+ * is permitted to access the display directly.  Other tasks wishing to write a\r
+ * message to the LCD send the message on a queue to the LCD task instead of\r
+ * accessing the LCD themselves.  The LCD task just blocks on the queue waiting\r
+ * for messages - waking and displaying the messages as they arrive.  The use\r
+ * of a gatekeeper in this manner permits both tasks and interrupts to write to\r
+ * the LCD without worrying about mutual exclusion.  This is demonstrated by the\r
+ * check hook (see below) which sends messages to the display even though it\r
+ * executes from an interrupt context.\r
+ *\r
+ * "Check" hook -  This only executes fully every five seconds from the tick\r
+ * hook.  Its main function is to check that all the standard demo tasks are\r
+ * still operational.  Should any unexpected behaviour be discovered within a\r
+ * demo task then the tick hook will write an error to the LCD (via the LCD task).\r
+ * If all the demo tasks are executing with their expected behaviour then the\r
+ * check task writes PASS to the LCD (again via the LCD task), as described above.\r
+ *\r
+ */\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "queue.h"\r
+#include "semphr.h"\r
+\r
+/* Demo app includes. */\r
+#include "BlockQ.h"\r
+#include "integer.h"\r
+#include "blocktim.h"\r
+#include "flash.h"\r
+#include "partest.h"\r
+#include "semtest.h"\r
+#include "PollQ.h"\r
+#include "lcd_message.h"\r
+#include "GenQTest.h"\r
+#include "QPeek.h"\r
+#include "recmutex.h"\r
+#include "flash.h"\r
+#include "comtest2.h"\r
+\r
+/* Atmel library includes. */\r
+#include <board.h>\r
+#include <lcd/color.h>\r
+#include <lcd/lcdd.h>\r
+#include <lcd/draw.h>\r
+\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The time between cycles of the 'check' functionality (defined within the\r
+tick hook). */\r
+#define mainCHECK_DELAY                                                ( ( portTickType ) 5000 / portTICK_RATE_MS )\r
+\r
+/* The LCD task uses the sprintf function so requires a little more stack too. */\r
+#define mainLCD_TASK_STACK_SIZE                                ( configMINIMAL_STACK_SIZE * 2 )\r
+\r
+/* Task priorities. */\r
+#define mainQUEUE_POLL_PRIORITY                                ( tskIDLE_PRIORITY + 2 )\r
+#define mainSEM_TEST_PRIORITY                          ( tskIDLE_PRIORITY + 1 )\r
+#define mainBLOCK_Q_PRIORITY                           ( tskIDLE_PRIORITY + 2 )\r
+#define mainLED_TASK_PRIORITY                          ( tskIDLE_PRIORITY + 1 )\r
+#define mainCOM_TEST_PRIORITY                          ( tskIDLE_PRIORITY + 2 )\r
+#define mainINTEGER_TASK_PRIORITY           ( tskIDLE_PRIORITY )\r
+#define mainGEN_QUEUE_TASK_PRIORITY                    ( tskIDLE_PRIORITY )\r
+\r
+/* The maximum number of message that can be waiting for display at any one\r
+time. */\r
+#define mainLCD_QUEUE_SIZE                                     ( 3 )\r
+\r
+/* Constants used by the comtest tasks.  There isn't a spare LED so an invalid\r
+LED is specified. */\r
+#define mainBAUD_RATE                                          ( 115200 )\r
+#define mainCOM_TEST_LED                                       ( 10 )\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Configure the hardware for the demo.\r
+ */\r
+static void prvSetupHardware( void );\r
+\r
+/*\r
+ * The LCD gatekeeper task.  Tasks wishing to write to the LCD do not access\r
+ * the LCD directly, but instead send the message to the LCD gatekeeper task.\r
+ */\r
+static void prvLCDTask( void *pvParameters );\r
+\r
+/*\r
+ * Hook functions that can get called by the kernel.  The 'check' functionality\r
+ * is implemented within the tick hook.\r
+ */\r
+void vApplicationStackOverflowHook( xTaskHandle *pxTask, signed char *pcTaskName );\r
+\r
+/*\r
+ * The tick hook function as described in the comments at the top of this file.\r
+ * The tick hook is used to monitor all the standard demo tasks to look for\r
+ * errors.  The tick hook is also used to demonstrate how the LCD gatekeeper\r
+ * task can be used to allow interrupts to write to the LCD.\r
+ */\r
+void vApplicationTickHook( void );\r
+\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The queue used to send messages to the LCD task. */\r
+static xQueueHandle xLCDQueue;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+int main( void )\r
+{\r
+       /* Prepare the hardware. */\r
+       prvSetupHardware();\r
+\r
+       /* Create the queue used by the LCD task.  Messages for display on the LCD\r
+       are received via this queue. */\r
+       xLCDQueue = xQueueCreate( mainLCD_QUEUE_SIZE, sizeof( xLCDMessage ) );\r
+\r
+       /* Start the standard demo tasks.  These do nothing other than test the\r
+       port and provide some APU usage examples. */\r
+    vStartIntegerMathTasks( mainINTEGER_TASK_PRIORITY );\r
+    vStartGenericQueueTasks( mainGEN_QUEUE_TASK_PRIORITY );\r
+       vStartRecursiveMutexTasks();    \r
+       vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );\r
+       vCreateBlockTimeTasks();\r
+       vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );\r
+       vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );\r
+       vStartQueuePeekTasks(); \r
+       vStartLEDFlashTasks( mainLED_TASK_PRIORITY );   \r
+       vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainBAUD_RATE, mainCOM_TEST_LED );\r
+\r
+       /* Start the tasks defined within this file/specific to this demo. */\r
+       xTaskCreate( prvLCDTask, ( signed char * ) "LCD", mainLCD_TASK_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );\r
+\r
+       /* Start the scheduler. */\r
+       vTaskStartScheduler();\r
+\r
+    /* Will only get here if there was insufficient memory to create the idle\r
+    task. */\r
+       return 0;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void prvSetupHardware( void )\r
+{\r
+       /* Initialise the port used for the LED outputs. */\r
+       vParTestInitialise();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationTickHook( void )\r
+{\r
+static xLCDMessage xMessage = { "PASS" };\r
+static unsigned portLONG ulTicksSinceLastDisplay = 0;\r
+portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE;\r
+\r
+       /* Called from every tick interrupt.  Have enough ticks passed to make it\r
+       time to perform our health status check again? */\r
+       ulTicksSinceLastDisplay++;\r
+       if( ulTicksSinceLastDisplay >= mainCHECK_DELAY )\r
+       {\r
+               ulTicksSinceLastDisplay = 0;\r
+               \r
+               /* Has an error been found in any task? */\r
+               if( xAreGenericQueueTasksStillRunning() != pdTRUE )\r
+               {\r
+                       xMessage.pcMessage = "ERROR IN GEN Q";\r
+               }\r
+           if( xAreIntegerMathsTaskStillRunning() != pdTRUE )\r
+           {\r
+               xMessage.pcMessage = "ERROR IN MATH";\r
+           }\r
+               else if( xAreBlockingQueuesStillRunning() != pdTRUE )\r
+               {\r
+                       xMessage.pcMessage = "ERROR IN BLOCK Q";\r
+               }\r
+               else if( xAreBlockTimeTestTasksStillRunning() != pdTRUE )\r
+               {\r
+                       xMessage.pcMessage = "ERROR IN BLOCK TIME";\r
+               }\r
+               else if( xAreSemaphoreTasksStillRunning() != pdTRUE )\r
+               {\r
+                       xMessage.pcMessage = "ERROR IN SEMAPHORE";\r
+               }\r
+               else if( xArePollingQueuesStillRunning() != pdTRUE )\r
+               {\r
+                       xMessage.pcMessage = "ERROR IN POLL Q";\r
+               }\r
+               else if( xAreQueuePeekTasksStillRunning() != pdTRUE )\r
+               {\r
+                       xMessage.pcMessage = "ERROR IN PEEK Q";\r
+               }                       \r
+               else if( xAreRecursiveMutexTasksStillRunning() != pdTRUE )\r
+               {\r
+                       xMessage.pcMessage = "ERROR IN REC MUTEX";\r
+               }               \r
+               else if( xAreComTestTasksStillRunning() != pdTRUE )\r
+               {\r
+                       xMessage.pcMessage = "ERROR IN COMTEST";\r
+               }\r
+               \r
+               /* Send the message to the LCD gatekeeper for display. */\r
+               xHigherPriorityTaskWoken = pdFALSE;\r
+               xQueueSendFromISR( xLCDQueue, &xMessage, &xHigherPriorityTaskWoken );\r
+       }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationStackOverflowHook( xTaskHandle *pxTask, signed portCHAR *pcTaskName )\r
+{\r
+       ( void ) pxTask;\r
+       ( void ) pcTaskName;\r
+\r
+       /* If the parameters have been corrupted then inspect pxCurrentTCB to\r
+       identify which task has overflowed its stack. */\r
+       for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvLCDTask( void *pvParameters )\r
+{\r
+xLCDMessage xMessage;\r
+unsigned long ulY = 0;\r
+const unsigned long ulX = 5;\r
+const unsigned long ulMaxY = 250, ulYIncrement = 22, ulWidth = 250, ulHeight = 20;;\r
+\r
+    /* Initialize LCD. */\r
+    LCDD_Initialize();\r
+    LCDD_Start();      \r
+       LCDD_Fill( ( void * ) BOARD_LCD_BASE, COLOR_WHITE );\r
+       LCDD_DrawString( ( void * ) BOARD_LCD_BASE, 1, ulY + 3, "  www.FreeRTOS.org", COLOR_BLACK );\r
+       \r
+       for( ;; )\r
+       {\r
+               /* Wait for a message from the check function (which is executed in\r
+               the tick hook). */\r
+               xQueueReceive( xLCDQueue, &xMessage, portMAX_DELAY );\r
+\r
+               /* Clear the space where the old message was. */\r
+        LCDD_DrawRectangle( ( void * ) BOARD_LCD_BASE, 0, ulY, ulWidth, ulHeight, COLOR_WHITE );\r
+               \r
+               /* Increment to the next drawing position. */\r
+               ulY += ulYIncrement;\r
+               \r
+               /* Have the Y position moved past the end of the LCD? */\r
+               if( ulY >= ulMaxY )\r
+               {\r
+                       ulY = 0;\r
+               }\r
+\r
+               /* Draw a new rectangle, in which the message will be written. */\r
+        LCDD_DrawRectangle( ( void * ) BOARD_LCD_BASE, 0, ulY, ulWidth, ulHeight, COLOR_GREEN );\r
+               \r
+               /* Write the message. */\r
+        LCDD_DrawString( ( void * ) BOARD_LCD_BASE, ulX, ulY + 3, xMessage.pcMessage, COLOR_BLACK );\r
+       }\r
+}\r

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/printf-stdarg.c b/Demo/CORTEX_AT91SAM3U256_IAR/printf-stdarg.c
new file mode 100644 (file)
index 0000000..f6139dc
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/printf-stdarg.c
@@ -0,0 +1,293 @@
+/*\r
+       Copyright 2001, 2002 Georges Menie (www.menie.org)\r
+       stdarg version contributed by Christian Ettinger\r
+\r
+    This program is free software; you can redistribute it and/or modify\r
+    it under the terms of the GNU Lesser General Public License as published by\r
+    the Free Software Foundation; either version 2 of the License, or\r
+    (at your option) any later version.\r
+\r
+    This program is distributed in the hope that it will be useful,\r
+    but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\r
+    GNU Lesser General Public License for more details.\r
+\r
+    You should have received a copy of the GNU Lesser General Public License\r
+    along with this program; if not, write to the Free Software\r
+    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA\r
+*/\r
+\r
+/*\r
+       putchar is the only external dependency for this file,\r
+       if you have a working putchar, leave it commented out.\r
+       If not, uncomment the define below and\r
+       replace outbyte(c) by your own function call.\r
+\r
+*/\r
+\r
+#define putchar(c) c\r
+\r
+#include <stdarg.h>\r
+\r
+static void printchar(char **str, int c)\r
+{\r
+       //extern int putchar(int c);\r
+       \r
+       if (str) {\r
+               **str = (char)c;\r
+               ++(*str);\r
+       }\r
+       else\r
+       { \r
+               (void)putchar(c);\r
+       }\r
+}\r
+\r
+#define PAD_RIGHT 1\r
+#define PAD_ZERO 2\r
+\r
+static int prints(char **out, const char *string, int width, int pad)\r
+{\r
+       register int pc = 0, padchar = ' ';\r
+\r
+       if (width > 0) {\r
+               register int len = 0;\r
+               register const char *ptr;\r
+               for (ptr = string; *ptr; ++ptr) ++len;\r
+               if (len >= width) width = 0;\r
+               else width -= len;\r
+               if (pad & PAD_ZERO) padchar = '0';\r
+       }\r
+       if (!(pad & PAD_RIGHT)) {\r
+               for ( ; width > 0; --width) {\r
+                       printchar (out, padchar);\r
+                       ++pc;\r
+               }\r
+       }\r
+       for ( ; *string ; ++string) {\r
+               printchar (out, *string);\r
+               ++pc;\r
+       }\r
+       for ( ; width > 0; --width) {\r
+               printchar (out, padchar);\r
+               ++pc;\r
+       }\r
+\r
+       return pc;\r
+}\r
+\r
+/* the following should be enough for 32 bit int */\r
+#define PRINT_BUF_LEN 12\r
+\r
+static int printi(char **out, int i, int b, int sg, int width, int pad, int letbase)\r
+{\r
+       char print_buf[PRINT_BUF_LEN];\r
+       register char *s;\r
+       register int t, neg = 0, pc = 0;\r
+       register unsigned int u = (unsigned int)i;\r
+\r
+       if (i == 0) {\r
+               print_buf[0] = '0';\r
+               print_buf[1] = '\0';\r
+               return prints (out, print_buf, width, pad);\r
+       }\r
+\r
+       if (sg && b == 10 && i < 0) {\r
+               neg = 1;\r
+               u = (unsigned int)-i;\r
+       }\r
+\r
+       s = print_buf + PRINT_BUF_LEN-1;\r
+       *s = '\0';\r
+\r
+       while (u) {\r
+               t = (int)u % b;\r
+               if( t >= 10 )\r
+                       t += letbase - '0' - 10;\r
+               *--s = (char)(t + '0');\r
+               u /= b;\r
+       }\r
+\r
+       if (neg) {\r
+               if( width && (pad & PAD_ZERO) ) {\r
+                       printchar (out, '-');\r
+                       ++pc;\r
+                       --width;\r
+               }\r
+               else {\r
+                       *--s = '-';\r
+               }\r
+       }\r
+\r
+       return pc + prints (out, s, width, pad);\r
+}\r
+\r
+static int print( char **out, const char *format, va_list args )\r
+{\r
+       register int width, pad;\r
+       register int pc = 0;\r
+       char scr[2];\r
+\r
+       for (; *format != 0; ++format) {\r
+               if (*format == '%') {\r
+                       ++format;\r
+                       width = pad = 0;\r
+                       if (*format == '\0') break;\r
+                       if (*format == '%') goto out;\r
+                       if (*format == '-') {\r
+                               ++format;\r
+                               pad = PAD_RIGHT;\r
+                       }\r
+                       while (*format == '0') {\r
+                               ++format;\r
+                               pad |= PAD_ZERO;\r
+                       }\r
+                       for ( ; *format >= '0' && *format <= '9'; ++format) {\r
+                               width *= 10;\r
+                               width += *format - '0';\r
+                       }\r
+                       if( *format == 's' ) {\r
+                               register char *s = (char *)va_arg( args, int );\r
+                               pc += prints (out, s?s:"(null)", width, pad);\r
+                               continue;\r
+                       }\r
+                       if( *format == 'd' ) {\r
+                               pc += printi (out, va_arg( args, int ), 10, 1, width, pad, 'a');\r
+                               continue;\r
+                       }\r
+                       if( *format == 'x' ) {\r
+                               pc += printi (out, va_arg( args, int ), 16, 0, width, pad, 'a');\r
+                               continue;\r
+                       }\r
+                       if( *format == 'X' ) {\r
+                               pc += printi (out, va_arg( args, int ), 16, 0, width, pad, 'A');\r
+                               continue;\r
+                       }\r
+                       if( *format == 'u' ) {\r
+                               pc += printi (out, va_arg( args, int ), 10, 0, width, pad, 'a');\r
+                               continue;\r
+                       }\r
+                       if( *format == 'c' ) {\r
+                               /* char are converted to int then pushed on the stack */\r
+                               scr[0] = (char)va_arg( args, int );\r
+                               scr[1] = '\0';\r
+                               pc += prints (out, scr, width, pad);\r
+                               continue;\r
+                       }\r
+               }\r
+               else {\r
+               out:\r
+                       printchar (out, *format);\r
+                       ++pc;\r
+               }\r
+       }\r
+       if (out) **out = '\0';\r
+       va_end( args );\r
+       return pc;\r
+}\r
+\r
+int printf(const char *format, ...)\r
+{\r
+        va_list args;\r
+        \r
+        va_start( args, format );\r
+        return print( 0, format, args );\r
+}\r
+\r
+int sprintf(char *out, const char *format, ...)\r
+{\r
+        va_list args;\r
+        \r
+        va_start( args, format );\r
+        return print( &out, format, args );\r
+}\r
+\r
+\r
+int snprintf( char *buf, unsigned int count, const char *format, ... )\r
+{\r
+        va_list args;\r
+        \r
+        ( void ) count;\r
+        \r
+        va_start( args, format );\r
+        return print( &buf, format, args );\r
+}\r
+\r
+\r
+#ifdef TEST_PRINTF\r
+int main(void)\r
+{\r
+       char *ptr = "Hello world!";\r
+       char *np = 0;\r
+       int i = 5;\r
+       unsigned int bs = sizeof(int)*8;\r
+       int mi;\r
+       char buf[80];\r
+\r
+       mi = (1 << (bs-1)) + 1;\r
+       printf("%s\n", ptr);\r
+       printf("printf test\n");\r
+       printf("%s is null pointer\n", np);\r
+       printf("%d = 5\n", i);\r
+       printf("%d = - max int\n", mi);\r
+       printf("char %c = 'a'\n", 'a');\r
+       printf("hex %x = ff\n", 0xff);\r
+       printf("hex %02x = 00\n", 0);\r
+       printf("signed %d = unsigned %u = hex %x\n", -3, -3, -3);\r
+       printf("%d %s(s)%", 0, "message");\r
+       printf("\n");\r
+       printf("%d %s(s) with %%\n", 0, "message");\r
+       sprintf(buf, "justif: \"%-10s\"\n", "left"); printf("%s", buf);\r
+       sprintf(buf, "justif: \"%10s\"\n", "right"); printf("%s", buf);\r
+       sprintf(buf, " 3: %04d zero padded\n", 3); printf("%s", buf);\r
+       sprintf(buf, " 3: %-4d left justif.\n", 3); printf("%s", buf);\r
+       sprintf(buf, " 3: %4d right justif.\n", 3); printf("%s", buf);\r
+       sprintf(buf, "-3: %04d zero padded\n", -3); printf("%s", buf);\r
+       sprintf(buf, "-3: %-4d left justif.\n", -3); printf("%s", buf);\r
+       sprintf(buf, "-3: %4d right justif.\n", -3); printf("%s", buf);\r
+\r
+       return 0;\r
+}\r
+\r
+/*\r
+ * if you compile this file with\r
+ *   gcc -Wall $(YOUR_C_OPTIONS) -DTEST_PRINTF -c printf.c\r
+ * you will get a normal warning:\r
+ *   printf.c:214: warning: spurious trailing `%' in format\r
+ * this line is testing an invalid % at the end of the format string.\r
+ *\r
+ * this should display (on 32bit int machine) :\r
+ *\r
+ * Hello world!\r
+ * printf test\r
+ * (null) is null pointer\r
+ * 5 = 5\r
+ * -2147483647 = - max int\r
+ * char a = 'a'\r
+ * hex ff = ff\r
+ * hex 00 = 00\r
+ * signed -3 = unsigned 4294967293 = hex fffffffd\r
+ * 0 message(s)\r
+ * 0 message(s) with %\r
+ * justif: "left      "\r
+ * justif: "     right"\r
+ *  3: 0003 zero padded\r
+ *  3: 3    left justif.\r
+ *  3:    3 right justif.\r
+ * -3: -003 zero padded\r
+ * -3: -3   left justif.\r
+ * -3:   -3 right justif.\r
+ */\r
+\r
+#endif\r
+\r
+\r
+/* To keep linker happy. */\r
+int    write( int i, char* c, int n)\r
+{\r
+       (void)i;\r
+       (void)n;\r
+       (void)c;\r
+       return 0;\r
+}\r
+\r

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/serial/serial.c b/Demo/CORTEX_AT91SAM3U256_IAR/serial/serial.c
new file mode 100644 (file)
index 0000000..0bd73fb
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/serial/serial.c
@@ -0,0 +1,259 @@
+/*\r
+       FreeRTOS.org V5.3.0 - Copyright (C) 2003-2009 Richard Barry.\r
+\r
+       This file is part of the FreeRTOS.org distribution.\r
+\r
+       FreeRTOS.org is free software; you can redistribute it and/or modify it\r
+       under the terms of the GNU General Public License (version 2) as published\r
+       by the Free Software Foundation and modified by the FreeRTOS exception.\r
+       **NOTE** The exception to the GPL is included to allow you to distribute a\r
+       combined work that includes FreeRTOS.org without being obliged to provide\r
+       the source code for any proprietary components.  Alternative commercial\r
+       license and support terms are also available upon request.  See the \r
+       licensing section of http://www.FreeRTOS.org for full details.\r
+\r
+       FreeRTOS.org is distributed in the hope that it will be useful, but WITHOUT\r
+       ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\r
+       FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\r
+       more details.\r
+\r
+       You should have received a copy of the GNU General Public License along\r
+       with FreeRTOS.org; if not, write to the Free Software Foundation, Inc., 59\r
+       Temple Place, Suite 330, Boston, MA  02111-1307  USA.\r
+\r
+\r
+       ***************************************************************************\r
+       *                                                                         *\r
+       * Get the FreeRTOS eBook!  See http://www.FreeRTOS.org/Documentation      *\r
+       *                                                                         *\r
+       * This is a concise, step by step, 'hands on' guide that describes both   *\r
+       * general multitasking concepts and FreeRTOS specifics. It presents and   *\r
+       * explains numerous examples that are written using the FreeRTOS API.     *\r
+       * Full source code for all the examples is provided in an accompanying    *\r
+       * .zip file.                                                              *\r
+       *                                                                         *\r
+       ***************************************************************************\r
+\r
+       1 tab == 4 spaces!\r
+\r
+       Please ensure to read the configuration and relevant port sections of the\r
+       online documentation.\r
+\r
+       http://www.FreeRTOS.org - Documentation, latest information, license and\r
+       contact details.\r
+\r
+       http://www.SafeRTOS.com - A version that is certified for use in safety\r
+       critical systems.\r
+\r
+       http://www.OpenRTOS.com - Commercial support, development, porting,\r
+       licensing and training services.\r
+*/\r
+\r
+/*\r
+       BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR UART0.\r
+*/\r
+\r
+/* Standard includes. */\r
+#include <stdlib.h>\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "queue.h"\r
+\r
+/* Demo application includes. */\r
+#include "serial.h"\r
+\r
+/* Library includes. */\r
+#include "usart/usart.h"\r
+#include "pmc/pmc.h"\r
+#include "irq/irq.h"\r
+#include "pio/pio.h"\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Interrupt control macros. */\r
+#define serINTERRUPT_LEVEL                             ( 5 )\r
+#define vInterruptOn()                                 BOARD_USART_BASE->US_IER = ( AT91C_US_TXRDY | AT91C_US_RXRDY )\r
+#define vInterruptOff()                                        BOARD_USART_BASE->US_IDR = AT91C_US_TXRDY\r
+\r
+/* Misc constants. */\r
+#define serINVALID_QUEUE                               ( ( xQueueHandle ) 0 )\r
+#define serHANDLE                                              ( ( xComPortHandle ) 1 )\r
+#define serNO_BLOCK                                            ( ( portTickType ) 0 )\r
+#define serNO_TIMEGUARD                                        ( ( unsigned portLONG ) 0 )\r
+#define serNO_PERIPHERAL_B_SETUP               ( ( unsigned portLONG ) 0 )\r
+\r
+\r
+/* Queues used to hold received characters, and characters waiting to be\r
+transmitted. */\r
+static xQueueHandle xRxedChars;\r
+static xQueueHandle xCharsForTx;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The interrupt service routine - called from the assembly entry point. */\r
+void vSerialISR( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * See the serial2.h header file.\r
+ */\r
+xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength )\r
+{\r
+xComPortHandle xReturn = serHANDLE;\r
+extern void ( vUART_ISR )( void );\r
+const Pin xUSART_Pins[] = { BOARD_PIN_USART_RXD, BOARD_PIN_USART_TXD };\r
+\r
+\r
+       /* Create the queues used to hold Rx and Tx characters. */\r
+       xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) );\r
+       xCharsForTx = xQueueCreate( uxQueueLength + 1, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) );\r
+\r
+       /* If the queues were created correctly then setup the serial port\r
+       hardware. */\r
+       if( ( xRxedChars != serINVALID_QUEUE ) && ( xCharsForTx != serINVALID_QUEUE ) )\r
+       {\r
+               portENTER_CRITICAL();\r
+               {\r
+                       /* Enable the peripheral clock in the PMC. */\r
+                       PMC_EnablePeripheral( BOARD_ID_USART );\r
+               \r
+                       /* Configure the USART. */\r
+                       USART_Configure( BOARD_USART_BASE, AT91C_US_CHRL_8_BITS | AT91C_US_PAR_NONE | AT91C_US_NBSTOP_1_BIT, ulWantedBaud, configCPU_CLOCK_HZ );\r
+               \r
+                       /* Configure the interrupt.  Note the pre-emption priority is set\r
+                       in bits [8:15] of the priority value passed as the parameter. */\r
+                       IRQ_ConfigureIT( BOARD_ID_USART, ( configMAX_SYSCALL_INTERRUPT_PRIORITY << 8 ), vSerialISR );\r
+                       IRQ_EnableIT( BOARD_ID_USART );\r
+               \r
+                       /* Enable receiver & transmitter. */\r
+                       USART_SetTransmitterEnabled( BOARD_USART_BASE, pdTRUE );\r
+                       USART_SetReceiverEnabled( BOARD_USART_BASE, pdTRUE );\r
+                       \r
+                       /* Configure IO for USART use. */\r
+                       PIO_Configure( xUSART_Pins, PIO_LISTSIZE( xUSART_Pins ) );\r
+               }\r
+               portEXIT_CRITICAL();\r
+       }\r
+       else\r
+       {\r
+               xReturn = ( xComPortHandle ) 0;\r
+       }\r
+\r
+       /* This demo file only supports a single port but we have to return\r
+       something to comply with the standard demo header file. */\r
+       return xReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime )\r
+{\r
+       /* The port handle is not required as this driver only supports one port. */\r
+       ( void ) pxPort;\r
+\r
+       /* Get the next character from the buffer.  Return false if no characters\r
+       are available, or arrive before xBlockTime expires. */\r
+       if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) )\r
+       {\r
+               return pdTRUE;\r
+       }\r
+       else\r
+       {\r
+               return pdFALSE;\r
+       }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vSerialPutString( xComPortHandle pxPort, const signed portCHAR * const pcString, unsigned portSHORT usStringLength )\r
+{\r
+signed portCHAR *pxNext;\r
+\r
+       /* A couple of parameters that this port does not use. */\r
+       ( void ) usStringLength;\r
+       ( void ) pxPort;\r
+\r
+       /* NOTE: This implementation does not handle the queue being full as no\r
+       block time is used! */\r
+\r
+       /* The port handle is not required as this driver only supports UART0. */\r
+       ( void ) pxPort;\r
+\r
+       /* Send each character in the string, one at a time. */\r
+       pxNext = ( signed portCHAR * ) pcString;\r
+       while( *pxNext )\r
+       {\r
+               xSerialPutChar( pxPort, *pxNext, serNO_BLOCK );\r
+               pxNext++;\r
+       }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime )\r
+{\r
+       /* Place the character in the queue of characters to be transmitted. */\r
+       if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) != pdPASS )\r
+       {\r
+               return pdFAIL;\r
+       }\r
+\r
+       /* Turn on the Tx interrupt so the ISR will remove the character from the\r
+       queue and send it.   This does not need to be in a critical section as\r
+       if the interrupt has already removed the character the next interrupt\r
+       will simply turn off the Tx interrupt again. */\r
+       vInterruptOn();\r
+\r
+       return pdPASS;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vSerialClose( xComPortHandle xPort )\r
+{\r
+       /* Not supported as not required by the demo application. */\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vSerialISR( void )\r
+{\r
+unsigned portLONG ulStatus;\r
+signed portCHAR cChar;\r
+portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE;\r
+\r
+       /* What caused the interrupt? */\r
+       ulStatus = BOARD_USART_BASE->US_CSR &= BOARD_USART_BASE->US_IMR;\r
+\r
+       if( ulStatus & AT91C_US_TXRDY )\r
+       {\r
+               /* The interrupt was caused by the THR becoming empty.  Are there any\r
+               more characters to transmit? */\r
+               if( xQueueReceiveFromISR( xCharsForTx, &cChar, &xHigherPriorityTaskWoken ) == pdTRUE )\r
+               {\r
+                       /* A character was retrieved from the queue so can be sent to the\r
+                       THR now. */\r
+                       BOARD_USART_BASE->US_THR = cChar;\r
+               }\r
+               else\r
+               {\r
+                       /* Queue empty, nothing to send so turn off the Tx interrupt. */\r
+                       vInterruptOff();\r
+               }               \r
+       }\r
+\r
+       if( ulStatus & AT91C_US_RXRDY )\r
+       {\r
+               /* The interrupt was caused by a character being received.  Grab the\r
+               character from the RHR and place it in the queue or received\r
+               characters. */\r
+               cChar = BOARD_USART_BASE->US_RHR;\r
+               xQueueSendFromISR( xRxedChars, &cChar, &xHigherPriorityTaskWoken );\r
+       }\r
+\r
+       /* If a task was woken by either a character being received or a character\r
+       being transmitted then we may need to switch to another task. */\r
+       portEND_SWITCHING_ISR( xHigherPriorityTaskWoken );\r
+}\r
+\r
+\r
+\r
+\r
+       \r

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/settings/RTOSDemo.cspy.bat b/Demo/CORTEX_AT91SAM3U256_IAR/settings/RTOSDemo.cspy.bat
new file mode 100644 (file)
index 0000000..a63a3a2
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/settings/RTOSDemo.cspy.bat
@@ -0,0 +1,33 @@
+@REM This bat file has been generated by the IAR Embeddded Workbench\r
+@REM C-SPY interactive debugger,as an aid to preparing a command\r
+@REM line for running the cspybat command line utility with the\r
+@REM appropriate settings.\r
+@REM\r
+@REM After making some adjustments to this file, you can launch cspybat\r
+@REM by typing the name of this file followed by the name of the debug\r
+@REM file (usually an ubrof file). Note that this file is generated\r
+@REM every time a new debug session is initialized, so you may want to\r
+@REM move or rename the file before making changes.\r
+@REM\r
+@REM Note: some command line arguments cannot be properly generated\r
+@REM by this process. Specifically, the plugin which is responsible\r
+@REM for the Terminal I/O window (and other C runtime functionality)\r
+@REM comes in a special version for cspybat, and the name of that\r
+@REM plugin dll is not known when generating this file. It resides in\r
+@REM the $TOOLKIT_DIR$\bin folder and is usually called XXXbat.dll or\r
+@REM XXXlibsupportbat.dll, where XXX is the name of the corresponding\r
+@REM tool chain. Replace the '<libsupport_plugin>' parameter\r
+@REM below with the appropriate file name. Other plugins loaded by\r
+@REM C-SPY are usually not needed by, or will not work in, cspybat\r
+@REM but they are listed at the end of this file for reference.\r
+\r
+\r
+"C:\devtools\IAR Systems\Embedded Workbench 5.4\common\bin\cspybat" "C:\devtools\IAR Systems\Embedded Workbench 5.4\arm\bin\armproc.dll" "C:\devtools\IAR Systems\Embedded Workbench 5.4\arm\bin\armjlink.dll"  %1 --plugin "C:\devtools\IAR Systems\Embedded Workbench 5.4\arm\bin\<libsupport_plugin>" --macro "C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\CORTEX_AT91SAM3U256_IAR\system\at91sam3u-ek-flash.mac" --backend -B "--endian=little" "--cpu=Cortex-M3" "--fpu=None" "-p" "C:\devtools\IAR Systems\Embedded Workbench 5.4\arm\CONFIG\debugger\Atmel\ioAT91SAM3U4.ddf" "--drv_verify_download" "--semihosting" "--device=AT91SAM3U4" "-d" "jlink" "--drv_communication=USB0" "--jlink_speed=auto" "--jlink_initial_speed=32" "--jlink_reset_strategy=0,0" "--jlink_interface=SWD" \r
+\r
+\r
+@REM Loaded plugins:\r
+@REM    C:\devtools\IAR Systems\Embedded Workbench 5.4\arm\bin\armlibsupport.dll\r
+@REM    C:\devtools\IAR Systems\Embedded Workbench 5.4\common\plugins\CodeCoverage\CodeCoverage.dll\r
+@REM    C:\devtools\IAR Systems\Embedded Workbench 5.4\common\plugins\Profiling\Profiling.dll\r
+@REM    C:\devtools\IAR Systems\Embedded Workbench 5.4\common\plugins\stack\stack.dll\r
+@REM    C:\devtools\IAR Systems\Embedded Workbench 5.4\common\plugins\SymList\SymList.dll\r

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/settings/RTOSDemo.dbgdt b/Demo/CORTEX_AT91SAM3U256_IAR/settings/RTOSDemo.dbgdt
new file mode 100644 (file)
index 0000000..357584c
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/settings/RTOSDemo.dbgdt
@@ -0,0 +1,68 @@
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<Project>\r
+  <Desktop>\r
+    <Static>\r
+      <Debug-Log>\r
+        \r
+        \r
+      <PreferedWindows><Position>3</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows/></PreferedWindows><ColumnWidth0>20</ColumnWidth0><ColumnWidth1>1622</ColumnWidth1></Debug-Log>\r
+      <Build>\r
+        <ColumnWidth0>20</ColumnWidth0>\r
+        <ColumnWidth1>1216</ColumnWidth1>\r
+        <ColumnWidth2>324</ColumnWidth2>\r
+        <ColumnWidth3>81</ColumnWidth3>\r
+      <PreferedWindows><Position>3</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows><Window><Factory>Debug-Log</Factory></Window></Windows></PreferedWindows></Build>\r
+      <Workspace>\r
+        <ColumnWidths>\r
+          \r
+          \r
+          \r
+          \r
+        <Column0>263</Column0><Column1>27</Column1><Column2>27</Column2><Column3>27</Column3></ColumnWidths>\r
+      </Workspace>\r
+      <Disassembly>\r
+        <PreferedWindows>\r
+          \r
+          \r
+          \r
+          \r
+        <Position>2</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows/></PreferedWindows>\r
+        \r
+        \r
+        \r
+      <MixedMode>1</MixedMode><CodeCovShow>0</CodeCovShow><InstrProfShow>0</InstrProfShow></Disassembly>\r
+    <TASKVIEW><PreferedWindows><Position>3</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows/></PreferedWindows><Column0>200</Column0><Column1>100</Column1><Column2>100</Column2><Column3>100</Column3><Column4>100</Column4><Column5>100</Column5><Column6>100</Column6><Column7>100</Column7><Column8>150</Column8></TASKVIEW><QUEUEVIEW><PreferedWindows><Position>3</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows/></PreferedWindows><Column0>200</Column0><Column1>100</Column1><Column2>100</Column2><Column3>100</Column3><Column4>100</Column4><Column5>100</Column5><Column6>100</Column6></QUEUEVIEW><Watch><Format><struct_types/><watch_formats/></Format><PreferedWindows><Position>2</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows/></PreferedWindows><Column0>125</Column0><Column1>150</Column1><Column2>100</Column2><Column3>100</Column3></Watch><Register><PreferedWindows><Position>2</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows/></PreferedWindows></Register><Breakpoints><PreferedWindows><Position>3</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows><Window><Factory>Debug-Log</Factory></Window></Windows></PreferedWindows></Breakpoints></Static>\r
+    <Windows>\r
+      \r
+      \r
+    <Wnd0>\r
+        <Tabs>\r
+          <Tab>\r
+            <Identity>TabID-16062-16922</Identity>\r
+            <TabName>Workspace</TabName>\r
+            <Factory>Workspace</Factory>\r
+            <Session>\r
+              \r
+            <NodeDict><ExpandedNode>RTOSDemo</ExpandedNode><ExpandedNode>RTOSDemo/Output</ExpandedNode></NodeDict></Session>\r
+          </Tab>\r
+        </Tabs>\r
+        \r
+      <SelectedTab>0</SelectedTab></Wnd0><Wnd1><Tabs><Tab><Identity>TabID-27988-1208</Identity><TabName>Debug Log</TabName><Factory>Debug-Log</Factory><Session/></Tab></Tabs><SelectedTab>0</SelectedTab></Wnd1></Windows>\r
+    <Editor>\r
+      \r
+      \r
+      \r
+      \r
+    <Pane><Tab><Factory>TextEditor</Factory><Filename>C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\CORTEX_AT91SAM3U256_IAR\main.c</Filename><XPos>0</XPos><YPos>148</YPos><SelStart>6647</SelStart><SelEnd>6647</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>C:\E\Dev\FreeRTOS\WorkingCopy3\Source\portable\IAR\ARM_CM3\port.c</Filename><XPos>0</XPos><YPos>155</YPos><SelStart>6219</SelStart><SelEnd>6219</SelEnd></Tab><ActiveTab>1</ActiveTab></Pane><ActivePane>0</ActivePane><Sizes><Pane><X>1000000</X><Y>1000000</Y></Pane></Sizes><SplitMode>1</SplitMode></Editor>\r
+    <Positions>\r
+      \r
+      \r
+      \r
+      \r
+      \r
+    <Top><Row0><Sizes><Toolbar-00ab91e8><key>iaridepm.enu1</key></Toolbar-00ab91e8><Toolbar-03d251c0><key>debuggergui.enu1</key></Toolbar-03d251c0></Sizes></Row0></Top><Left><Row0><Sizes><Wnd0><Rect><Top>-2</Top><Left>-2</Left><Bottom>742</Bottom><Right>337</Right><x>-2</x><y>-2</y><xscreen>167</xscreen><yscreen>200</yscreen><sizeHorzCX>119286</sizeHorzCX><sizeHorzCY>203252</sizeHorzCY><sizeVertCX>242143</sizeVertCX><sizeVertCY>756098</sizeVertCY></Rect></Wnd0></Sizes></Row0></Left><Right><Row0><Sizes/></Row0></Right><Bottom><Row0><Sizes><Wnd1><Rect><Top>-2</Top><Left>-2</Left><Bottom>198</Bottom><Right>1402</Right><x>-2</x><y>-2</y><xscreen>1404</xscreen><yscreen>200</yscreen><sizeHorzCX>1002857</sizeHorzCX><sizeHorzCY>203252</sizeHorzCY><sizeVertCX>142857</sizeVertCX><sizeVertCY>203252</sizeVertCY></Rect></Wnd1></Sizes></Row0></Bottom><Float><Sizes/></Float></Positions>\r
+  </Desktop>\r
+</Project>\r
+\r
+\r

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/settings/RTOSDemo.dni b/Demo/CORTEX_AT91SAM3U256_IAR/settings/RTOSDemo.dni
new file mode 100644 (file)
index 0000000..959ff6c
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/settings/RTOSDemo.dni
@@ -0,0 +1,87 @@
+[DebugChecksum]\r
+Checksum=1342314454\r
+[DisAssemblyWindow]\r
+NumStates=_ 1\r
+State 1=_ 1\r
+[InstructionProfiling]\r
+Enabled=_ 0\r
+[CodeCoverage]\r
+Enabled=_ 0\r
+[Profiling]\r
+Enabled=0\r
+[StackPlugin]\r
+Enabled=0\r
+OverflowWarningsEnabled=1\r
+WarningThreshold=90\r
+SpWarningsEnabled=0\r
+WarnHow=0\r
+UseTrigger=1\r
+TriggerName=main\r
+LimitSize=0\r
+ByteLimit=50\r
+[Interrupts]\r
+Enabled=1\r
+[MemoryMap]\r
+Enabled=0\r
+Base=0\r
+UseAuto=0\r
+TypeViolation=1\r
+UnspecRange=1\r
+ActionState=1\r
+[TraceHelper]\r
+Enabled=0\r
+ShowSource=1\r
+[JLinkDriver]\r
+SWOInfo_CpuClock=0x044AA200\r
+SWOInfo_SWOClockAutoDetect=0\r
+SWOInfo_JtagSpeed=0x001E8480\r
+SWOInfo_SWOPrescaler=0x00000024\r
+SWOInfo_SWOClockWanted=0x001E8480\r
+SWOInfo_HWTraceEnabled=0\r
+SWOInfo_TimestampsEnabled=0\r
+SWOInfo_TimestampsPrescalerIndex=0x00000000\r
+SWOInfo_TimestampsPrescalerData=0x00000000\r
+SWOInfo_PCSamplingEnabled=0\r
+SWOInfo_PCSamplingCYCTAP=0x00000001\r
+SWOInfo_PCSamplingPOSTCNT=0x0000000F\r
+SWOInfo_DataLogMode=0x00000000\r
+SWOInfo_CPIEnabled=0\r
+SWOInfo_EXCEnabled=0\r
+SWOInfo_SLEEPEnabled=0\r
+SWOInfo_LSUEnabled=0\r
+SWOInfo_FOLDEnabled=0\r
+SWOInfo_EXCTRCEnabled=0\r
+SWOInfo_ITMPortsEnabled=0x00000001\r
+SWOInfo_ITMPortsTermIO=0x00000001\r
+SWOInfo_ITMPortsLogFile=0x00000000\r
+SWOInfo_ITMLogFile=$PROJ_DIR$\ITM.log\r
+[DataLog]\r
+LogEnabled=0\r
+SumEnabled=0\r
+ShowTimeLog=1\r
+ShowTimeSum=1\r
+[InterruptLog]\r
+LogEnabled=0\r
+SumEnabled=0\r
+GraphEnabled=0\r
+ShowTimeLog=1\r
+ShowTimeSum=1\r
+SumSortOrder=0\r
+[TraceHelperExtra]\r
+Enabled=0\r
+ShowSource=1\r
+[DriverProfiling]\r
+Enabled=0\r
+Source=4\r
+Graph=0\r
+[Disassemble mode]\r
+mode=0\r
+[Breakpoints]\r
+Count=0\r
+[Log file]\r
+LoggingEnabled=_ 0\r
+LogFile=_ ""\r
+Category=_ 0\r
+[TermIOLog]\r
+LoggingEnabled=_ 0\r
+LogFile=_ ""\r

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/settings/RTOSDemo.wsdt b/Demo/CORTEX_AT91SAM3U256_IAR/settings/RTOSDemo.wsdt
new file mode 100644 (file)
index 0000000..9e4e0b2
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/settings/RTOSDemo.wsdt
@@ -0,0 +1,49 @@
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<Workspace>\r
+  <ConfigDictionary>\r
+    \r
+  <CurrentConfigs><Project>RTOSDemo/Debug</Project></CurrentConfigs></ConfigDictionary>\r
+  <Desktop>\r
+    <Static>\r
+      <Workspace>\r
+        <ColumnWidths>\r
+          \r
+          \r
+          \r
+          \r
+        <Column0>202</Column0><Column1>27</Column1><Column2>27</Column2><Column3>27</Column3></ColumnWidths>\r
+      </Workspace>\r
+    <Build><ColumnWidth0>20</ColumnWidth0><ColumnWidth1>1216</ColumnWidth1><ColumnWidth2>324</ColumnWidth2><ColumnWidth3>81</ColumnWidth3></Build><TerminalIO/><Debug-Log><ColumnWidth0>20</ColumnWidth0><ColumnWidth1>1622</ColumnWidth1></Debug-Log><Find-in-Files><ColumnWidth0>580</ColumnWidth0><ColumnWidth1>82</ColumnWidth1><ColumnWidth2>994</ColumnWidth2></Find-in-Files></Static>\r
+    <Windows>\r
+      \r
+    <Wnd0>\r
+        <Tabs>\r
+          <Tab>\r
+            <Identity>TabID-16570-17725</Identity>\r
+            <TabName>Workspace</TabName>\r
+            <Factory>Workspace</Factory>\r
+            <Session>\r
+              \r
+            <NodeDict><ExpandedNode>RTOSDemo</ExpandedNode><ExpandedNode>RTOSDemo/Atmel_and_system</ExpandedNode></NodeDict></Session>\r
+          </Tab>\r
+        </Tabs>\r
+        \r
+      <SelectedTab>0</SelectedTab></Wnd0><Wnd1><Tabs><Tab><Identity>TabID-13247-26794</Identity><TabName>Build</TabName><Factory>Build</Factory><Session/></Tab><Tab><Identity>TabID-4179-11901</Identity><TabName>Debug Log</TabName><Factory>Debug-Log</Factory><Session/></Tab><Tab><Identity>TabID-30005-19605</Identity><TabName>Find in Files</TabName><Factory>Find-in-Files</Factory><Session/></Tab><Tab><Identity>TabID-6552-24144</Identity><TabName>Breakpoints</TabName><Factory>Breakpoints</Factory></Tab></Tabs><SelectedTab>1</SelectedTab></Wnd1></Windows>\r
+    <Editor>\r
+      \r
+      \r
+      \r
+      \r
+    <Pane><Tab><Factory>TextEditor</Factory><Filename>C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\CORTEX_AT91SAM3U256_IAR\main.c</Filename><XPos>0</XPos><YPos>46</YPos><SelStart>6647</SelStart><SelEnd>6647</SelEnd></Tab><ActiveTab>0</ActiveTab></Pane><ActivePane>0</ActivePane><Sizes><Pane><X>1000000</X><Y>1000000</Y></Pane></Sizes><SplitMode>1</SplitMode></Editor>\r
+    <Positions>\r
+      \r
+      \r
+      \r
+      \r
+      \r
+    <Top><Row0><Sizes><Toolbar-00ab9de0><key>iaridepm.enu1</key></Toolbar-00ab9de0></Sizes></Row0></Top><Left><Row0><Sizes><Wnd0><Rect><Top>-2</Top><Left>-2</Left><Bottom>671</Bottom><Right>276</Right><x>-2</x><y>-2</y><xscreen>200</xscreen><yscreen>200</yscreen><sizeHorzCX>142857</sizeHorzCX><sizeHorzCY>203252</sizeHorzCY><sizeVertCX>198571</sizeVertCX><sizeVertCY>683943</sizeVertCY></Rect></Wnd0></Sizes></Row0></Left><Right><Row0><Sizes/></Row0></Right><Bottom><Row0><Sizes><Wnd1><Rect><Top>-2</Top><Left>-2</Left><Bottom>269</Bottom><Right>1402</Right><x>-2</x><y>-2</y><xscreen>1404</xscreen><yscreen>271</yscreen><sizeHorzCX>1002857</sizeHorzCX><sizeHorzCY>275407</sizeHorzCY><sizeVertCX>142857</sizeVertCX><sizeVertCY>203252</sizeVertCY></Rect></Wnd1></Sizes></Row0></Bottom><Float><Sizes/></Float></Positions>\r
+  </Desktop>\r
+</Workspace>\r
+\r
+\r

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/settings/RTOSDemo_Debug.jlink b/Demo/CORTEX_AT91SAM3U256_IAR/settings/RTOSDemo_Debug.jlink
new file mode 100644 (file)
index 0000000..e97aaa4
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/settings/RTOSDemo_Debug.jlink
@@ -0,0 +1,12 @@
+[FLASH]\r
+SkipProgOnCRCMatch = 1\r
+VerifyDownload = 1\r
+AllowCaching = 1\r
+EnableFlashDL = 2\r
+Override = 0\r
+Device="ADUC7020X62"\r
+[BREAKPOINTS]\r
+ShowInfoWin = 1\r
+EnableFlashBP = 2\r
+[CPU]\r
+AllowSimulation = 1\r

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/settings/RTOSDemo_Release.jlink b/Demo/CORTEX_AT91SAM3U256_IAR/settings/RTOSDemo_Release.jlink
new file mode 100644 (file)
index 0000000..e97aaa4
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/settings/RTOSDemo_Release.jlink
@@ -0,0 +1,12 @@
+[FLASH]\r
+SkipProgOnCRCMatch = 1\r
+VerifyDownload = 1\r
+AllowCaching = 1\r
+EnableFlashDL = 2\r
+Override = 0\r
+Device="ADUC7020X62"\r
+[BREAKPOINTS]\r
+ShowInfoWin = 1\r
+EnableFlashBP = 2\r
+[CPU]\r
+AllowSimulation = 1\r

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/system/AT91SAM3U4.h b/Demo/CORTEX_AT91SAM3U256_IAR/system/AT91SAM3U4.h
new file mode 100644 (file)
index 0000000..a7cb9a6
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/system/AT91SAM3U4.h
@@ -0,0 +1,6517 @@
+//  ----------------------------------------------------------------------------\r
+//          ATMEL Microcontroller Software Support  -  ROUSSET  -\r
+//  ----------------------------------------------------------------------------\r
+//  Copyright (c) 2008, Atmel Corporation\r
+// \r
+//  All rights reserved.\r
+// \r
+//  Redistribution and use in source and binary forms, with or without\r
+//  modification, are permitted provided that the following conditions are met:\r
+// \r
+//  - Redistributions of source code must retain the above copyright notice,\r
+//  this list of conditions and the disclaimer below.\r
+// \r
+//  Atmel's name may not be used to endorse or promote products derived from\r
+//  this software without specific prior written permission. \r
+//  \r
+//  DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+//  IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+//  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+//  DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+//  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+//  OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+//  LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+//  NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+//  EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+//  ----------------------------------------------------------------------------\r
+// File Name           : AT91SAM3U4.h\r
+// Object              : AT91SAM3U4 definitions\r
+// Generated           : AT91 SW Application Group  03/09/2009 (11:49:34)\r
+// \r
+// CVS Reference       : /AT91SAM3U4.pl/1.32/Mon Feb  9 14:20:58 2009//\r
+// CVS Reference       : /SYS_SAM3U4.pl/1.4/Fri Oct 17 13:27:57 2008//\r
+// CVS Reference       : /HMATRIX2_SAM3U4.pl/1.3/Mon Mar  2 10:12:07 2009//\r
+// CVS Reference       : /PMC_SAM3U4.pl/1.7/Fri Oct 17 13:27:54 2008//\r
+// CVS Reference       : /EBI_SAM9260.pl/1.1/Fri Sep 30 12:12:14 2005//\r
+// CVS Reference       : /EFC2_SAM3U4.pl/1.3/Mon Mar  2 10:12:06 2009//\r
+// CVS Reference       : /HSDRAMC1_6100A.pl/1.2/Mon Aug  9 10:52:25 2004//\r
+// CVS Reference       : /HSMC4_xxxx.pl/1.9/Fri Oct 17 13:27:56 2008//\r
+// CVS Reference       : /HECC_6143A.pl/1.1/Wed Feb  9 17:16:57 2005//\r
+// CVS Reference       : /CORTEX_M3_NVIC.pl/1.7/Tue Jan 27 16:16:24 2009//\r
+// CVS Reference       : /CORTEX_M3_MPU.pl/1.3/Fri Oct 17 13:27:48 2008//\r
+// CVS Reference       : /CORTEX_M3.pl/1.1/Mon Sep 15 15:22:06 2008//\r
+// CVS Reference       : /PDC_6074C.pl/1.2/Thu Feb  3 09:02:11 2005//\r
+// CVS Reference       : /DBGU_SAM3U4.pl/1.2/Fri Oct 17 13:27:49 2008//\r
+// CVS Reference       : /PIO3_xxxx.pl/1.6/Mon Mar  9 10:43:37 2009//\r
+// CVS Reference       : /RSTC_6098A.pl/1.4/Fri Oct 17 13:27:55 2008//\r
+// CVS Reference       : /SHDWC_6122A.pl/1.3/Wed Oct  6 14:16:58 2004//\r
+// CVS Reference       : /SUPC_SAM3U4.pl/1.2/Thu Jun  5 15:27:27 2008//\r
+// CVS Reference       : /RTTC_6081A.pl/1.2/Thu Nov  4 13:57:22 2004//\r
+// CVS Reference       : /PITC_6079A.pl/1.2/Thu Nov  4 13:56:22 2004//\r
+// CVS Reference       : /WDTC_6080A.pl/1.3/Thu Nov  4 13:58:52 2004//\r
+// CVS Reference       : /TC_6082A.pl/1.8/Fri Oct 17 13:27:58 2008//\r
+// CVS Reference       : /MCI_6101F.pl/1.3/Fri Jan 23 09:15:32 2009//\r
+// CVS Reference       : /TWI_6061B.pl/1.3/Fri Oct 17 13:27:59 2008//\r
+// CVS Reference       : /US_6089J.pl/1.3/Fri Oct 17 13:27:59 2008//\r
+// CVS Reference       : /SSC_6078B.pl/1.3/Fri Oct 17 13:27:57 2008//\r
+// CVS Reference       : /SPI2.pl/1.4/Mon Mar  9 08:56:28 2009//\r
+// CVS Reference       : /PWM_6343B_V400.pl/1.3/Fri Oct 17 13:27:54 2008//\r
+// CVS Reference       : /HDMA_SAM3U4.pl/1.3/Fri Oct 17 13:27:51 2008//\r
+// CVS Reference       : /UDPHS_SAM9_7ept6dma4iso.pl/1.4/Tue Jun 24 13:05:14 2008//\r
+// CVS Reference       : /ADC_SAM3UE.pl/1.4/Fri Feb 20 12:19:18 2009//\r
+// CVS Reference       : /RTC_1245D.pl/1.3/Fri Sep 17 14:01:31 2004//\r
+//  ----------------------------------------------------------------------------\r
+\r
+#ifndef AT91SAM3U4_H\r
+#define AT91SAM3U4_H\r
+\r
+#ifndef __ASSEMBLY__\r
+typedef volatile unsigned int AT91_REG;// Hardware register definition\r
+#define AT91_CAST(a) (a)\r
+#else\r
+#define AT91_CAST(a)\r
+#endif\r
+\r
+// *****************************************************************************\r
+//              SOFTWARE API DEFINITION  FOR System Peripherals\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_SYS {\r
+       AT91_REG         HSMC4_CFG;     // Configuration Register\r
+       AT91_REG         HSMC4_CTRL;    // Control Register\r
+       AT91_REG         HSMC4_SR;      // Status Register\r
+       AT91_REG         HSMC4_IER;     // Interrupt Enable Register\r
+       AT91_REG         HSMC4_IDR;     // Interrupt Disable Register\r
+       AT91_REG         HSMC4_IMR;     // Interrupt Mask Register\r
+       AT91_REG         HSMC4_ADDR;    // Address Cycle Zero Register\r
+       AT91_REG         HSMC4_BANK;    // Bank Register\r
+       AT91_REG         HSMC4_ECCCR;   // ECC reset register\r
+       AT91_REG         HSMC4_ECCCMD;  // ECC Page size register\r
+       AT91_REG         HSMC4_ECCSR1;  // ECC Status register 1\r
+       AT91_REG         HSMC4_ECCPR0;  // ECC Parity register 0\r
+       AT91_REG         HSMC4_ECCPR1;  // ECC Parity register 1\r
+       AT91_REG         HSMC4_ECCSR2;  // ECC Status register 2\r
+       AT91_REG         HSMC4_ECCPR2;  // ECC Parity register 2\r
+       AT91_REG         HSMC4_ECCPR3;  // ECC Parity register 3\r
+       AT91_REG         HSMC4_ECCPR4;  // ECC Parity register 4\r
+       AT91_REG         HSMC4_ECCPR5;  // ECC Parity register 5\r
+       AT91_REG         HSMC4_ECCPR6;  // ECC Parity register 6\r
+       AT91_REG         HSMC4_ECCPR7;  // ECC Parity register 7\r
+       AT91_REG         HSMC4_ECCPR8;  // ECC Parity register 8\r
+       AT91_REG         HSMC4_ECCPR9;  // ECC Parity register 9\r
+       AT91_REG         HSMC4_ECCPR10;         // ECC Parity register 10\r
+       AT91_REG         HSMC4_ECCPR11;         // ECC Parity register 11\r
+       AT91_REG         HSMC4_ECCPR12;         // ECC Parity register 12\r
+       AT91_REG         HSMC4_ECCPR13;         // ECC Parity register 13\r
+       AT91_REG         HSMC4_ECCPR14;         // ECC Parity register 14\r
+       AT91_REG         HSMC4_Eccpr15;         // ECC Parity register 15\r
+       AT91_REG         Reserved0[40];         // \r
+       AT91_REG         HSMC4_OCMS;    // OCMS MODE register\r
+       AT91_REG         HSMC4_KEY1;    // KEY1 Register\r
+       AT91_REG         HSMC4_KEY2;    // KEY2 Register\r
+       AT91_REG         Reserved1[50];         // \r
+       AT91_REG         HSMC4_WPCR;    // Write Protection Control register\r
+       AT91_REG         HSMC4_WPSR;    // Write Protection Status Register\r
+       AT91_REG         HSMC4_ADDRSIZE;        // Write Protection Status Register\r
+       AT91_REG         HSMC4_IPNAME1;         // Write Protection Status Register\r
+       AT91_REG         HSMC4_IPNAME2;         // Write Protection Status Register\r
+       AT91_REG         HSMC4_FEATURES;        // Write Protection Status Register\r
+       AT91_REG         HSMC4_VER;     // HSMC4 Version Register\r
+       AT91_REG         HMATRIX_MCFG0;         //  Master Configuration Register 0 : ARM I and D\r
+       AT91_REG         HMATRIX_MCFG1;         //  Master Configuration Register 1 : ARM S\r
+       AT91_REG         HMATRIX_MCFG2;         //  Master Configuration Register 2\r
+       AT91_REG         HMATRIX_MCFG3;         //  Master Configuration Register 3\r
+       AT91_REG         HMATRIX_MCFG4;         //  Master Configuration Register 4\r
+       AT91_REG         HMATRIX_MCFG5;         //  Master Configuration Register 5\r
+       AT91_REG         HMATRIX_MCFG6;         //  Master Configuration Register 6\r
+       AT91_REG         HMATRIX_MCFG7;         //  Master Configuration Register 7\r
+       AT91_REG         Reserved2[8];  // \r
+       AT91_REG         HMATRIX_SCFG0;         //  Slave Configuration Register 0\r
+       AT91_REG         HMATRIX_SCFG1;         //  Slave Configuration Register 1\r
+       AT91_REG         HMATRIX_SCFG2;         //  Slave Configuration Register 2\r
+       AT91_REG         HMATRIX_SCFG3;         //  Slave Configuration Register 3\r
+       AT91_REG         HMATRIX_SCFG4;         //  Slave Configuration Register 4\r
+       AT91_REG         HMATRIX_SCFG5;         //  Slave Configuration Register 5\r
+       AT91_REG         HMATRIX_SCFG6;         //  Slave Configuration Register 6\r
+       AT91_REG         HMATRIX_SCFG7;         //  Slave Configuration Register 5\r
+       AT91_REG         HMATRIX_SCFG8;         //  Slave Configuration Register 8\r
+       AT91_REG         Reserved3[43];         // \r
+       AT91_REG         HMATRIX_SFR0 ;         //  Special Function Register 0\r
+       AT91_REG         HMATRIX_SFR1 ;         //  Special Function Register 1\r
+       AT91_REG         HMATRIX_SFR2 ;         //  Special Function Register 2\r
+       AT91_REG         HMATRIX_SFR3 ;         //  Special Function Register 3\r
+       AT91_REG         HMATRIX_SFR4 ;         //  Special Function Register 4\r
+       AT91_REG         HMATRIX_SFR5 ;         //  Special Function Register 5\r
+       AT91_REG         HMATRIX_SFR6 ;         //  Special Function Register 6\r
+       AT91_REG         HMATRIX_SFR7 ;         //  Special Function Register 7\r
+       AT91_REG         HMATRIX_SFR8 ;         //  Special Function Register 8\r
+       AT91_REG         HMATRIX_SFR9 ;         //  Special Function Register 9\r
+       AT91_REG         HMATRIX_SFR10;         //  Special Function Register 10\r
+       AT91_REG         HMATRIX_SFR11;         //  Special Function Register 11\r
+       AT91_REG         HMATRIX_SFR12;         //  Special Function Register 12\r
+       AT91_REG         HMATRIX_SFR13;         //  Special Function Register 13\r
+       AT91_REG         HMATRIX_SFR14;         //  Special Function Register 14\r
+       AT91_REG         HMATRIX_SFR15;         //  Special Function Register 15\r
+       AT91_REG         Reserved4[39];         // \r
+       AT91_REG         HMATRIX_ADDRSIZE;      // HMATRIX2 ADDRSIZE REGISTER \r
+       AT91_REG         HMATRIX_IPNAME1;       // HMATRIX2 IPNAME1 REGISTER \r
+       AT91_REG         HMATRIX_IPNAME2;       // HMATRIX2 IPNAME2 REGISTER \r
+       AT91_REG         HMATRIX_FEATURES;      // HMATRIX2 FEATURES REGISTER \r
+       AT91_REG         HMATRIX_VER;   // HMATRIX2 VERSION REGISTER \r
+       AT91_REG         PMC_SCER;      // System Clock Enable Register\r
+       AT91_REG         PMC_SCDR;      // System Clock Disable Register\r
+       AT91_REG         PMC_SCSR;      // System Clock Status Register\r
+       AT91_REG         Reserved5[1];  // \r
+       AT91_REG         PMC_PCER;      // Peripheral Clock Enable Register\r
+       AT91_REG         PMC_PCDR;      // Peripheral Clock Disable Register\r
+       AT91_REG         PMC_PCSR;      // Peripheral Clock Status Register\r
+       AT91_REG         PMC_UCKR;      // UTMI Clock Configuration Register\r
+       AT91_REG         PMC_MOR;       // Main Oscillator Register\r
+       AT91_REG         PMC_MCFR;      // Main Clock  Frequency Register\r
+       AT91_REG         PMC_PLLAR;     // PLL Register\r
+       AT91_REG         Reserved6[1];  // \r
+       AT91_REG         PMC_MCKR;      // Master Clock Register\r
+       AT91_REG         Reserved7[3];  // \r
+       AT91_REG         PMC_PCKR[8];   // Programmable Clock Register\r
+       AT91_REG         PMC_IER;       // Interrupt Enable Register\r
+       AT91_REG         PMC_IDR;       // Interrupt Disable Register\r
+       AT91_REG         PMC_SR;        // Status Register\r
+       AT91_REG         PMC_IMR;       // Interrupt Mask Register\r
+       AT91_REG         PMC_FSMR;      // Fast Startup Mode Register\r
+       AT91_REG         PMC_FSPR;      // Fast Startup Polarity Register\r
+       AT91_REG         PMC_FOCR;      // Fault Output Clear Register\r
+       AT91_REG         Reserved8[28];         // \r
+       AT91_REG         PMC_ADDRSIZE;  // PMC ADDRSIZE REGISTER \r
+       AT91_REG         PMC_IPNAME1;   // PMC IPNAME1 REGISTER \r
+       AT91_REG         PMC_IPNAME2;   // PMC IPNAME2 REGISTER \r
+       AT91_REG         PMC_FEATURES;  // PMC FEATURES REGISTER \r
+       AT91_REG         PMC_VER;       // APMC VERSION REGISTER\r
+       AT91_REG         Reserved9[64];         // \r
+       AT91_REG         DBGU_CR;       // Control Register\r
+       AT91_REG         DBGU_MR;       // Mode Register\r
+       AT91_REG         DBGU_IER;      // Interrupt Enable Register\r
+       AT91_REG         DBGU_IDR;      // Interrupt Disable Register\r
+       AT91_REG         DBGU_IMR;      // Interrupt Mask Register\r
+       AT91_REG         DBGU_CSR;      // Channel Status Register\r
+       AT91_REG         DBGU_RHR;      // Receiver Holding Register\r
+       AT91_REG         DBGU_THR;      // Transmitter Holding Register\r
+       AT91_REG         DBGU_BRGR;     // Baud Rate Generator Register\r
+       AT91_REG         Reserved10[9];         // \r
+       AT91_REG         DBGU_FNTR;     // Force NTRST Register\r
+       AT91_REG         Reserved11[40];        // \r
+       AT91_REG         DBGU_ADDRSIZE;         // DBGU ADDRSIZE REGISTER \r
+       AT91_REG         DBGU_IPNAME1;  // DBGU IPNAME1 REGISTER \r
+       AT91_REG         DBGU_IPNAME2;  // DBGU IPNAME2 REGISTER \r
+       AT91_REG         DBGU_FEATURES;         // DBGU FEATURES REGISTER \r
+       AT91_REG         DBGU_VER;      // DBGU VERSION REGISTER \r
+       AT91_REG         DBGU_RPR;      // Receive Pointer Register\r
+       AT91_REG         DBGU_RCR;      // Receive Counter Register\r
+       AT91_REG         DBGU_TPR;      // Transmit Pointer Register\r
+       AT91_REG         DBGU_TCR;      // Transmit Counter Register\r
+       AT91_REG         DBGU_RNPR;     // Receive Next Pointer Register\r
+       AT91_REG         DBGU_RNCR;     // Receive Next Counter Register\r
+       AT91_REG         DBGU_TNPR;     // Transmit Next Pointer Register\r
+       AT91_REG         DBGU_TNCR;     // Transmit Next Counter Register\r
+       AT91_REG         DBGU_PTCR;     // PDC Transfer Control Register\r
+       AT91_REG         DBGU_PTSR;     // PDC Transfer Status Register\r
+       AT91_REG         Reserved12[6];         // \r
+       AT91_REG         DBGU_CIDR;     // Chip ID Register\r
+       AT91_REG         DBGU_EXID;     // Chip ID Extension Register\r
+       AT91_REG         Reserved13[46];        // \r
+       AT91_REG         EFC0_FMR;      // EFC Flash Mode Register\r
+       AT91_REG         EFC0_FCR;      // EFC Flash Command Register\r
+       AT91_REG         EFC0_FSR;      // EFC Flash Status Register\r
+       AT91_REG         EFC0_FRR;      // EFC Flash Result Register\r
+       AT91_REG         Reserved14[1];         // \r
+       AT91_REG         EFC0_FVR;      // EFC Flash Version Register\r
+       AT91_REG         Reserved15[122];       // \r
+       AT91_REG         EFC1_FMR;      // EFC Flash Mode Register\r
+       AT91_REG         EFC1_FCR;      // EFC Flash Command Register\r
+       AT91_REG         EFC1_FSR;      // EFC Flash Status Register\r
+       AT91_REG         EFC1_FRR;      // EFC Flash Result Register\r
+       AT91_REG         Reserved16[1];         // \r
+       AT91_REG         EFC1_FVR;      // EFC Flash Version Register\r
+       AT91_REG         Reserved17[122];       // \r
+       AT91_REG         PIOA_PER;      // PIO Enable Register\r
+       AT91_REG         PIOA_PDR;      // PIO Disable Register\r
+       AT91_REG         PIOA_PSR;      // PIO Status Register\r
+       AT91_REG         Reserved18[1];         // \r
+       AT91_REG         PIOA_OER;      // Output Enable Register\r
+       AT91_REG         PIOA_ODR;      // Output Disable Registerr\r
+       AT91_REG         PIOA_OSR;      // Output Status Register\r
+       AT91_REG         Reserved19[1];         // \r
+       AT91_REG         PIOA_IFER;     // Input Filter Enable Register\r
+       AT91_REG         PIOA_IFDR;     // Input Filter Disable Register\r
+       AT91_REG         PIOA_IFSR;     // Input Filter Status Register\r
+       AT91_REG         Reserved20[1];         // \r
+       AT91_REG         PIOA_SODR;     // Set Output Data Register\r
+       AT91_REG         PIOA_CODR;     // Clear Output Data Register\r
+       AT91_REG         PIOA_ODSR;     // Output Data Status Register\r
+       AT91_REG         PIOA_PDSR;     // Pin Data Status Register\r
+       AT91_REG         PIOA_IER;      // Interrupt Enable Register\r
+       AT91_REG         PIOA_IDR;      // Interrupt Disable Register\r
+       AT91_REG         PIOA_IMR;      // Interrupt Mask Register\r
+       AT91_REG         PIOA_ISR;      // Interrupt Status Register\r
+       AT91_REG         PIOA_MDER;     // Multi-driver Enable Register\r
+       AT91_REG         PIOA_MDDR;     // Multi-driver Disable Register\r
+       AT91_REG         PIOA_MDSR;     // Multi-driver Status Register\r
+       AT91_REG         Reserved21[1];         // \r
+       AT91_REG         PIOA_PPUDR;    // Pull-up Disable Register\r
+       AT91_REG         PIOA_PPUER;    // Pull-up Enable Register\r
+       AT91_REG         PIOA_PPUSR;    // Pull-up Status Register\r
+       AT91_REG         Reserved22[1];         // \r
+       AT91_REG         PIOA_ABSR;     // Peripheral AB Select Register\r
+       AT91_REG         Reserved23[3];         // \r
+       AT91_REG         PIOA_SCIFSR;   // System Clock Glitch Input Filter Select Register\r
+       AT91_REG         PIOA_DIFSR;    // Debouncing Input Filter Select Register\r
+       AT91_REG         PIOA_IFDGSR;   // Glitch or Debouncing Input Filter Clock Selection Status Register\r
+       AT91_REG         PIOA_SCDR;     // Slow Clock Divider Debouncing Register\r
+       AT91_REG         Reserved24[4];         // \r
+       AT91_REG         PIOA_OWER;     // Output Write Enable Register\r
+       AT91_REG         PIOA_OWDR;     // Output Write Disable Register\r
+       AT91_REG         PIOA_OWSR;     // Output Write Status Register\r
+       AT91_REG         Reserved25[1];         // \r
+       AT91_REG         PIOA_AIMER;    // Additional Interrupt Modes Enable Register\r
+       AT91_REG         PIOA_AIMDR;    // Additional Interrupt Modes Disables Register\r
+       AT91_REG         PIOA_AIMMR;    // Additional Interrupt Modes Mask Register\r
+       AT91_REG         Reserved26[1];         // \r
+       AT91_REG         PIOA_ESR;      // Edge Select Register\r
+       AT91_REG         PIOA_LSR;      // Level Select Register\r
+       AT91_REG         PIOA_ELSR;     // Edge/Level Status Register\r
+       AT91_REG         Reserved27[1];         // \r
+       AT91_REG         PIOA_FELLSR;   // Falling Edge/Low Level Select Register\r
+       AT91_REG         PIOA_REHLSR;   // Rising Edge/ High Level Select Register\r
+       AT91_REG         PIOA_FRLHSR;   // Fall/Rise - Low/High Status Register\r
+       AT91_REG         Reserved28[1];         // \r
+       AT91_REG         PIOA_LOCKSR;   // Lock Status Register\r
+       AT91_REG         Reserved29[6];         // \r
+       AT91_REG         PIOA_VER;      // PIO VERSION REGISTER \r
+       AT91_REG         Reserved30[8];         // \r
+       AT91_REG         PIOA_KER;      // Keypad Controller Enable Register\r
+       AT91_REG         PIOA_KRCR;     // Keypad Controller Row Column Register\r
+       AT91_REG         PIOA_KDR;      // Keypad Controller Debouncing Register\r
+       AT91_REG         Reserved31[1];         // \r
+       AT91_REG         PIOA_KIER;     // Keypad Controller Interrupt Enable Register\r
+       AT91_REG         PIOA_KIDR;     // Keypad Controller Interrupt Disable Register\r
+       AT91_REG         PIOA_KIMR;     // Keypad Controller Interrupt Mask Register\r
+       AT91_REG         PIOA_KSR;      // Keypad Controller Status Register\r
+       AT91_REG         PIOA_KKPR;     // Keypad Controller Key Press Register\r
+       AT91_REG         PIOA_KKRR;     // Keypad Controller Key Release Register\r
+       AT91_REG         Reserved32[46];        // \r
+       AT91_REG         PIOB_PER;      // PIO Enable Register\r
+       AT91_REG         PIOB_PDR;      // PIO Disable Register\r
+       AT91_REG         PIOB_PSR;      // PIO Status Register\r
+       AT91_REG         Reserved33[1];         // \r
+       AT91_REG         PIOB_OER;      // Output Enable Register\r
+       AT91_REG         PIOB_ODR;      // Output Disable Registerr\r
+       AT91_REG         PIOB_OSR;      // Output Status Register\r
+       AT91_REG         Reserved34[1];         // \r
+       AT91_REG         PIOB_IFER;     // Input Filter Enable Register\r
+       AT91_REG         PIOB_IFDR;     // Input Filter Disable Register\r
+       AT91_REG         PIOB_IFSR;     // Input Filter Status Register\r
+       AT91_REG         Reserved35[1];         // \r
+       AT91_REG         PIOB_SODR;     // Set Output Data Register\r
+       AT91_REG         PIOB_CODR;     // Clear Output Data Register\r
+       AT91_REG         PIOB_ODSR;     // Output Data Status Register\r
+       AT91_REG         PIOB_PDSR;     // Pin Data Status Register\r
+       AT91_REG         PIOB_IER;      // Interrupt Enable Register\r
+       AT91_REG         PIOB_IDR;      // Interrupt Disable Register\r
+       AT91_REG         PIOB_IMR;      // Interrupt Mask Register\r
+       AT91_REG         PIOB_ISR;      // Interrupt Status Register\r
+       AT91_REG         PIOB_MDER;     // Multi-driver Enable Register\r
+       AT91_REG         PIOB_MDDR;     // Multi-driver Disable Register\r
+       AT91_REG         PIOB_MDSR;     // Multi-driver Status Register\r
+       AT91_REG         Reserved36[1];         // \r
+       AT91_REG         PIOB_PPUDR;    // Pull-up Disable Register\r
+       AT91_REG         PIOB_PPUER;    // Pull-up Enable Register\r
+       AT91_REG         PIOB_PPUSR;    // Pull-up Status Register\r
+       AT91_REG         Reserved37[1];         // \r
+       AT91_REG         PIOB_ABSR;     // Peripheral AB Select Register\r
+       AT91_REG         Reserved38[3];         // \r
+       AT91_REG         PIOB_SCIFSR;   // System Clock Glitch Input Filter Select Register\r
+       AT91_REG         PIOB_DIFSR;    // Debouncing Input Filter Select Register\r
+       AT91_REG         PIOB_IFDGSR;   // Glitch or Debouncing Input Filter Clock Selection Status Register\r
+       AT91_REG         PIOB_SCDR;     // Slow Clock Divider Debouncing Register\r
+       AT91_REG         Reserved39[4];         // \r
+       AT91_REG         PIOB_OWER;     // Output Write Enable Register\r
+       AT91_REG         PIOB_OWDR;     // Output Write Disable Register\r
+       AT91_REG         PIOB_OWSR;     // Output Write Status Register\r
+       AT91_REG         Reserved40[1];         // \r
+       AT91_REG         PIOB_AIMER;    // Additional Interrupt Modes Enable Register\r
+       AT91_REG         PIOB_AIMDR;    // Additional Interrupt Modes Disables Register\r
+       AT91_REG         PIOB_AIMMR;    // Additional Interrupt Modes Mask Register\r
+       AT91_REG         Reserved41[1];         // \r
+       AT91_REG         PIOB_ESR;      // Edge Select Register\r
+       AT91_REG         PIOB_LSR;      // Level Select Register\r
+       AT91_REG         PIOB_ELSR;     // Edge/Level Status Register\r
+       AT91_REG         Reserved42[1];         // \r
+       AT91_REG         PIOB_FELLSR;   // Falling Edge/Low Level Select Register\r
+       AT91_REG         PIOB_REHLSR;   // Rising Edge/ High Level Select Register\r
+       AT91_REG         PIOB_FRLHSR;   // Fall/Rise - Low/High Status Register\r
+       AT91_REG         Reserved43[1];         // \r
+       AT91_REG         PIOB_LOCKSR;   // Lock Status Register\r
+       AT91_REG         Reserved44[6];         // \r
+       AT91_REG         PIOB_VER;      // PIO VERSION REGISTER \r
+       AT91_REG         Reserved45[8];         // \r
+       AT91_REG         PIOB_KER;      // Keypad Controller Enable Register\r
+       AT91_REG         PIOB_KRCR;     // Keypad Controller Row Column Register\r
+       AT91_REG         PIOB_KDR;      // Keypad Controller Debouncing Register\r
+       AT91_REG         Reserved46[1];         // \r
+       AT91_REG         PIOB_KIER;     // Keypad Controller Interrupt Enable Register\r
+       AT91_REG         PIOB_KIDR;     // Keypad Controller Interrupt Disable Register\r
+       AT91_REG         PIOB_KIMR;     // Keypad Controller Interrupt Mask Register\r
+       AT91_REG         PIOB_KSR;      // Keypad Controller Status Register\r
+       AT91_REG         PIOB_KKPR;     // Keypad Controller Key Press Register\r
+       AT91_REG         PIOB_KKRR;     // Keypad Controller Key Release Register\r
+       AT91_REG         Reserved47[46];        // \r
+       AT91_REG         PIOC_PER;      // PIO Enable Register\r
+       AT91_REG         PIOC_PDR;      // PIO Disable Register\r
+       AT91_REG         PIOC_PSR;      // PIO Status Register\r
+       AT91_REG         Reserved48[1];         // \r
+       AT91_REG         PIOC_OER;      // Output Enable Register\r
+       AT91_REG         PIOC_ODR;      // Output Disable Registerr\r
+       AT91_REG         PIOC_OSR;      // Output Status Register\r
+       AT91_REG         Reserved49[1];         // \r
+       AT91_REG         PIOC_IFER;     // Input Filter Enable Register\r
+       AT91_REG         PIOC_IFDR;     // Input Filter Disable Register\r
+       AT91_REG         PIOC_IFSR;     // Input Filter Status Register\r
+       AT91_REG         Reserved50[1];         // \r
+       AT91_REG         PIOC_SODR;     // Set Output Data Register\r
+       AT91_REG         PIOC_CODR;     // Clear Output Data Register\r
+       AT91_REG         PIOC_ODSR;     // Output Data Status Register\r
+       AT91_REG         PIOC_PDSR;     // Pin Data Status Register\r
+       AT91_REG         PIOC_IER;      // Interrupt Enable Register\r
+       AT91_REG         PIOC_IDR;      // Interrupt Disable Register\r
+       AT91_REG         PIOC_IMR;      // Interrupt Mask Register\r
+       AT91_REG         PIOC_ISR;      // Interrupt Status Register\r
+       AT91_REG         PIOC_MDER;     // Multi-driver Enable Register\r
+       AT91_REG         PIOC_MDDR;     // Multi-driver Disable Register\r
+       AT91_REG         PIOC_MDSR;     // Multi-driver Status Register\r
+       AT91_REG         Reserved51[1];         // \r
+       AT91_REG         PIOC_PPUDR;    // Pull-up Disable Register\r
+       AT91_REG         PIOC_PPUER;    // Pull-up Enable Register\r
+       AT91_REG         PIOC_PPUSR;    // Pull-up Status Register\r
+       AT91_REG         Reserved52[1];         // \r
+       AT91_REG         PIOC_ABSR;     // Peripheral AB Select Register\r
+       AT91_REG         Reserved53[3];         // \r
+       AT91_REG         PIOC_SCIFSR;   // System Clock Glitch Input Filter Select Register\r
+       AT91_REG         PIOC_DIFSR;    // Debouncing Input Filter Select Register\r
+       AT91_REG         PIOC_IFDGSR;   // Glitch or Debouncing Input Filter Clock Selection Status Register\r
+       AT91_REG         PIOC_SCDR;     // Slow Clock Divider Debouncing Register\r
+       AT91_REG         Reserved54[4];         // \r
+       AT91_REG         PIOC_OWER;     // Output Write Enable Register\r
+       AT91_REG         PIOC_OWDR;     // Output Write Disable Register\r
+       AT91_REG         PIOC_OWSR;     // Output Write Status Register\r
+       AT91_REG         Reserved55[1];         // \r
+       AT91_REG         PIOC_AIMER;    // Additional Interrupt Modes Enable Register\r
+       AT91_REG         PIOC_AIMDR;    // Additional Interrupt Modes Disables Register\r
+       AT91_REG         PIOC_AIMMR;    // Additional Interrupt Modes Mask Register\r
+       AT91_REG         Reserved56[1];         // \r
+       AT91_REG         PIOC_ESR;      // Edge Select Register\r
+       AT91_REG         PIOC_LSR;      // Level Select Register\r
+       AT91_REG         PIOC_ELSR;     // Edge/Level Status Register\r
+       AT91_REG         Reserved57[1];         // \r
+       AT91_REG         PIOC_FELLSR;   // Falling Edge/Low Level Select Register\r
+       AT91_REG         PIOC_REHLSR;   // Rising Edge/ High Level Select Register\r
+       AT91_REG         PIOC_FRLHSR;   // Fall/Rise - Low/High Status Register\r
+       AT91_REG         Reserved58[1];         // \r
+       AT91_REG         PIOC_LOCKSR;   // Lock Status Register\r
+       AT91_REG         Reserved59[6];         // \r
+       AT91_REG         PIOC_VER;      // PIO VERSION REGISTER \r
+       AT91_REG         Reserved60[8];         // \r
+       AT91_REG         PIOC_KER;      // Keypad Controller Enable Register\r
+       AT91_REG         PIOC_KRCR;     // Keypad Controller Row Column Register\r
+       AT91_REG         PIOC_KDR;      // Keypad Controller Debouncing Register\r
+       AT91_REG         Reserved61[1];         // \r
+       AT91_REG         PIOC_KIER;     // Keypad Controller Interrupt Enable Register\r
+       AT91_REG         PIOC_KIDR;     // Keypad Controller Interrupt Disable Register\r
+       AT91_REG         PIOC_KIMR;     // Keypad Controller Interrupt Mask Register\r
+       AT91_REG         PIOC_KSR;      // Keypad Controller Status Register\r
+       AT91_REG         PIOC_KKPR;     // Keypad Controller Key Press Register\r
+       AT91_REG         PIOC_KKRR;     // Keypad Controller Key Release Register\r
+       AT91_REG         Reserved62[46];        // \r
+       AT91_REG         RSTC_RCR;      // Reset Control Register\r
+       AT91_REG         RSTC_RSR;      // Reset Status Register\r
+       AT91_REG         RSTC_RMR;      // Reset Mode Register\r
+       AT91_REG         Reserved63[1];         // \r
+       AT91_REG         SUPC_CR;       // Control Register\r
+       AT91_REG         SUPC_BOMR;     // Brown Out Mode Register\r
+       AT91_REG         SUPC_MR;       // Mode Register\r
+       AT91_REG         SUPC_WUMR;     // Wake Up Mode Register\r
+       AT91_REG         SUPC_WUIR;     // Wake Up Inputs Register\r
+       AT91_REG         SUPC_SR;       // Status Register\r
+       AT91_REG         SUPC_FWUTR;    // Flash Wake-up Timer Register\r
+       AT91_REG         Reserved64[1];         // \r
+       AT91_REG         RTTC_RTMR;     // Real-time Mode Register\r
+       AT91_REG         RTTC_RTAR;     // Real-time Alarm Register\r
+       AT91_REG         RTTC_RTVR;     // Real-time Value Register\r
+       AT91_REG         RTTC_RTSR;     // Real-time Status Register\r
+       AT91_REG         Reserved65[4];         // \r
+       AT91_REG         WDTC_WDCR;     // Watchdog Control Register\r
+       AT91_REG         WDTC_WDMR;     // Watchdog Mode Register\r
+       AT91_REG         WDTC_WDSR;     // Watchdog Status Register\r
+       AT91_REG         Reserved66[1];         // \r
+       AT91_REG         RTC_CR;        // Control Register\r
+       AT91_REG         RTC_MR;        // Mode Register\r
+       AT91_REG         RTC_TIMR;      // Time Register\r
+       AT91_REG         RTC_CALR;      // Calendar Register\r
+       AT91_REG         RTC_TIMALR;    // Time Alarm Register\r
+       AT91_REG         RTC_CALALR;    // Calendar Alarm Register\r
+       AT91_REG         RTC_SR;        // Status Register\r
+       AT91_REG         RTC_SCCR;      // Status Clear Command Register\r
+       AT91_REG         RTC_IER;       // Interrupt Enable Register\r
+       AT91_REG         RTC_IDR;       // Interrupt Disable Register\r
+       AT91_REG         RTC_IMR;       // Interrupt Mask Register\r
+       AT91_REG         RTC_VER;       // Valid Entry Register\r
+       AT91_REG         SYS_GPBR[8];   // General Purpose Register\r
+       AT91_REG         Reserved67[19];        // \r
+       AT91_REG         RSTC_VER;      // Version Register\r
+} AT91S_SYS, *AT91PS_SYS;\r
+#else\r
+#define GPBR            (AT91_CAST(AT91_REG *)         0x00001290) // (GPBR) General Purpose Register\r
+\r
+#endif\r
+// -------- GPBR : (SYS Offset: 0x1290) GPBR General Purpose Register -------- \r
+#define AT91C_GPBR_GPRV       (0x0 <<  0) // (SYS) General Purpose Register Value\r
+\r
+// *****************************************************************************\r
+//              SOFTWARE API DEFINITION  FOR HSMC4 Chip Select interface\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_HSMC4_CS {\r
+       AT91_REG         HSMC4_SETUP;   // Setup Register\r
+       AT91_REG         HSMC4_PULSE;   // Pulse Register\r
+       AT91_REG         HSMC4_CYCLE;   // Cycle Register\r
+       AT91_REG         HSMC4_TIMINGS;         // Timmings Register\r
+       AT91_REG         HSMC4_MODE;    // Mode Register\r
+} AT91S_HSMC4_CS, *AT91PS_HSMC4_CS;\r
+#else\r
+#define HSMC4_SETUP     (AT91_CAST(AT91_REG *)         0x00000000) // (HSMC4_SETUP) Setup Register\r
+#define HSMC4_PULSE     (AT91_CAST(AT91_REG *)         0x00000004) // (HSMC4_PULSE) Pulse Register\r
+#define HSMC4_CYCLE     (AT91_CAST(AT91_REG *)         0x00000008) // (HSMC4_CYCLE) Cycle Register\r
+#define HSMC4_TIMINGS   (AT91_CAST(AT91_REG *)         0x0000000C) // (HSMC4_TIMINGS) Timmings Register\r
+#define HSMC4_MODE      (AT91_CAST(AT91_REG *)         0x00000010) // (HSMC4_MODE) Mode Register\r
+\r
+#endif\r
+// -------- HSMC4_SETUP : (HSMC4_CS Offset: 0x0) HSMC4 SETUP -------- \r
+#define AT91C_HSMC4_NWE_SETUP (0x3F <<  0) // (HSMC4_CS) NWE Setup length\r
+#define AT91C_HSMC4_NCS_WR_SETUP (0x3F <<  8) // (HSMC4_CS) NCS Setup length in Write access\r
+#define AT91C_HSMC4_NRD_SETUP (0x3F << 16) // (HSMC4_CS) NRD Setup length\r
+#define AT91C_HSMC4_NCS_RD_SETUP (0x3F << 24) // (HSMC4_CS) NCS Setup legnth in Read access\r
+// -------- HSMC4_PULSE : (HSMC4_CS Offset: 0x4) HSMC4 PULSE -------- \r
+#define AT91C_HSMC4_NWE_PULSE (0x3F <<  0) // (HSMC4_CS) NWE Pulse Length\r
+#define AT91C_HSMC4_NCS_WR_PULSE (0x3F <<  8) // (HSMC4_CS) NCS Pulse length in WRITE access\r
+#define AT91C_HSMC4_NRD_PULSE (0x3F << 16) // (HSMC4_CS) NRD Pulse length\r
+#define AT91C_HSMC4_NCS_RD_PULSE (0x3F << 24) // (HSMC4_CS) NCS Pulse length in READ access\r
+// -------- HSMC4_CYCLE : (HSMC4_CS Offset: 0x8) HSMC4 CYCLE -------- \r
+#define AT91C_HSMC4_NWE_CYCLE (0x1FF <<  0) // (HSMC4_CS) Total Write Cycle Length\r
+#define AT91C_HSMC4_NRD_CYCLE (0x1FF << 16) // (HSMC4_CS) Total Read Cycle Length\r
+// -------- HSMC4_TIMINGS : (HSMC4_CS Offset: 0xc) HSMC4 TIMINGS -------- \r
+#define AT91C_HSMC4_TCLR      (0xF <<  0) // (HSMC4_CS) CLE to REN low delay\r
+#define AT91C_HSMC4_TADL      (0xF <<  4) // (HSMC4_CS) ALE to data start\r
+#define AT91C_HSMC4_TAR       (0xF <<  8) // (HSMC4_CS) ALE to REN low delay\r
+#define AT91C_HSMC4_OCMSEN    (0x1 << 12) // (HSMC4_CS) Off Chip Memory Scrambling Enable\r
+#define AT91C_HSMC4_TRR       (0xF << 16) // (HSMC4_CS) Ready to REN low delay\r
+#define AT91C_HSMC4_TWB       (0xF << 24) // (HSMC4_CS) WEN high to REN to busy\r
+#define AT91C_HSMC4_RBNSEL    (0x7 << 28) // (HSMC4_CS) Ready/Busy Line Selection\r
+#define AT91C_HSMC4_NFSEL     (0x1 << 31) // (HSMC4_CS) Nand Flash Selection\r
+// -------- HSMC4_MODE : (HSMC4_CS Offset: 0x10) HSMC4 MODE -------- \r
+#define AT91C_HSMC4_READ_MODE (0x1 <<  0) // (HSMC4_CS) Read Mode\r
+#define AT91C_HSMC4_WRITE_MODE (0x1 <<  1) // (HSMC4_CS) Write Mode\r
+#define AT91C_HSMC4_EXNW_MODE (0x3 <<  4) // (HSMC4_CS) NWAIT Mode\r
+#define        AT91C_HSMC4_EXNW_MODE_NWAIT_DISABLE        (0x0 <<  4) // (HSMC4_CS) External NWAIT disabled.\r
+#define        AT91C_HSMC4_EXNW_MODE_NWAIT_ENABLE_FROZEN  (0x2 <<  4) // (HSMC4_CS) External NWAIT enabled in frozen mode.\r
+#define        AT91C_HSMC4_EXNW_MODE_NWAIT_ENABLE_READY   (0x3 <<  4) // (HSMC4_CS) External NWAIT enabled in ready mode.\r
+#define AT91C_HSMC4_BAT       (0x1 <<  8) // (HSMC4_CS) Byte Access Type\r
+#define        AT91C_HSMC4_BAT_BYTE_SELECT          (0x0 <<  8) // (HSMC4_CS) Write controled by ncs, nbs0, nbs1, nbs2, nbs3. Read controled by ncs, nrd, nbs0, nbs1, nbs2, nbs3.\r
+#define        AT91C_HSMC4_BAT_BYTE_WRITE           (0x1 <<  8) // (HSMC4_CS) Write controled by ncs, nwe0, nwe1, nwe2, nwe3. Read controled by ncs and nrd.\r
+#define AT91C_HSMC4_DBW       (0x3 << 12) // (HSMC4_CS) Data Bus Width\r
+#define        AT91C_HSMC4_DBW_WIDTH_EIGTH_BITS     (0x0 << 12) // (HSMC4_CS) 8 bits.\r
+#define        AT91C_HSMC4_DBW_WIDTH_SIXTEEN_BITS   (0x1 << 12) // (HSMC4_CS) 16 bits.\r
+#define        AT91C_HSMC4_DBW_WIDTH_THIRTY_TWO_BITS (0x2 << 12) // (HSMC4_CS) 32 bits.\r
+#define AT91C_HSMC4_TDF_CYCLES (0xF << 16) // (HSMC4_CS) Data Float Time.\r
+#define AT91C_HSMC4_TDF_MODE  (0x1 << 20) // (HSMC4_CS) TDF Enabled.\r
+#define AT91C_HSMC4_PMEN      (0x1 << 24) // (HSMC4_CS) Page Mode Enabled.\r
+#define AT91C_HSMC4_PS        (0x3 << 28) // (HSMC4_CS) Page Size\r
+#define        AT91C_HSMC4_PS_SIZE_FOUR_BYTES      (0x0 << 28) // (HSMC4_CS) 4 bytes.\r
+#define        AT91C_HSMC4_PS_SIZE_EIGHT_BYTES     (0x1 << 28) // (HSMC4_CS) 8 bytes.\r
+#define        AT91C_HSMC4_PS_SIZE_SIXTEEN_BYTES   (0x2 << 28) // (HSMC4_CS) 16 bytes.\r
+#define        AT91C_HSMC4_PS_SIZE_THIRTY_TWO_BYTES (0x3 << 28) // (HSMC4_CS) 32 bytes.\r
+\r
+// *****************************************************************************\r
+//              SOFTWARE API DEFINITION  FOR AHB Static Memory Controller 4 Interface\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_HSMC4 {\r
+       AT91_REG         HSMC4_CFG;     // Configuration Register\r
+       AT91_REG         HSMC4_CTRL;    // Control Register\r
+       AT91_REG         HSMC4_SR;      // Status Register\r
+       AT91_REG         HSMC4_IER;     // Interrupt Enable Register\r
+       AT91_REG         HSMC4_IDR;     // Interrupt Disable Register\r
+       AT91_REG         HSMC4_IMR;     // Interrupt Mask Register\r
+       AT91_REG         HSMC4_ADDR;    // Address Cycle Zero Register\r
+       AT91_REG         HSMC4_BANK;    // Bank Register\r
+       AT91_REG         HSMC4_ECCCR;   // ECC reset register\r
+       AT91_REG         HSMC4_ECCCMD;  // ECC Page size register\r
+       AT91_REG         HSMC4_ECCSR1;  // ECC Status register 1\r
+       AT91_REG         HSMC4_ECCPR0;  // ECC Parity register 0\r
+       AT91_REG         HSMC4_ECCPR1;  // ECC Parity register 1\r
+       AT91_REG         HSMC4_ECCSR2;  // ECC Status register 2\r
+       AT91_REG         HSMC4_ECCPR2;  // ECC Parity register 2\r
+       AT91_REG         HSMC4_ECCPR3;  // ECC Parity register 3\r
+       AT91_REG         HSMC4_ECCPR4;  // ECC Parity register 4\r
+       AT91_REG         HSMC4_ECCPR5;  // ECC Parity register 5\r
+       AT91_REG         HSMC4_ECCPR6;  // ECC Parity register 6\r
+       AT91_REG         HSMC4_ECCPR7;  // ECC Parity register 7\r
+       AT91_REG         HSMC4_ECCPR8;  // ECC Parity register 8\r
+       AT91_REG         HSMC4_ECCPR9;  // ECC Parity register 9\r
+       AT91_REG         HSMC4_ECCPR10;         // ECC Parity register 10\r
+       AT91_REG         HSMC4_ECCPR11;         // ECC Parity register 11\r
+       AT91_REG         HSMC4_ECCPR12;         // ECC Parity register 12\r
+       AT91_REG         HSMC4_ECCPR13;         // ECC Parity register 13\r
+       AT91_REG         HSMC4_ECCPR14;         // ECC Parity register 14\r
+       AT91_REG         HSMC4_Eccpr15;         // ECC Parity register 15\r
+       AT91_REG         Reserved0[40];         // \r
+       AT91_REG         HSMC4_OCMS;    // OCMS MODE register\r
+       AT91_REG         HSMC4_KEY1;    // KEY1 Register\r
+       AT91_REG         HSMC4_KEY2;    // KEY2 Register\r
+       AT91_REG         Reserved1[50];         // \r
+       AT91_REG         HSMC4_WPCR;    // Write Protection Control register\r
+       AT91_REG         HSMC4_WPSR;    // Write Protection Status Register\r
+       AT91_REG         HSMC4_ADDRSIZE;        // Write Protection Status Register\r
+       AT91_REG         HSMC4_IPNAME1;         // Write Protection Status Register\r
+       AT91_REG         HSMC4_IPNAME2;         // Write Protection Status Register\r
+       AT91_REG         HSMC4_FEATURES;        // Write Protection Status Register\r
+       AT91_REG         HSMC4_VER;     // HSMC4 Version Register\r
+       AT91_REG         HSMC4_DUMMY;   // This rtegister was created only ti have AHB constants\r
+} AT91S_HSMC4, *AT91PS_HSMC4;\r
+#else\r
+#define HSMC4_CFG       (AT91_CAST(AT91_REG *)         0x00000000) // (HSMC4_CFG) Configuration Register\r
+#define HSMC4_CTRL      (AT91_CAST(AT91_REG *)         0x00000004) // (HSMC4_CTRL) Control Register\r
+#define HSMC4_SR        (AT91_CAST(AT91_REG *)         0x00000008) // (HSMC4_SR) Status Register\r
+#define HSMC4_IER       (AT91_CAST(AT91_REG *)         0x0000000C) // (HSMC4_IER) Interrupt Enable Register\r
+#define HSMC4_IDR       (AT91_CAST(AT91_REG *)         0x00000010) // (HSMC4_IDR) Interrupt Disable Register\r
+#define HSMC4_IMR       (AT91_CAST(AT91_REG *)         0x00000014) // (HSMC4_IMR) Interrupt Mask Register\r
+#define HSMC4_ADDR      (AT91_CAST(AT91_REG *)         0x00000018) // (HSMC4_ADDR) Address Cycle Zero Register\r
+#define HSMC4_BANK      (AT91_CAST(AT91_REG *)         0x0000001C) // (HSMC4_BANK) Bank Register\r
+#define HSMC4_ECCCR     (AT91_CAST(AT91_REG *)         0x00000020) // (HSMC4_ECCCR) ECC reset register\r
+#define HSMC4_ECCCMD    (AT91_CAST(AT91_REG *)         0x00000024) // (HSMC4_ECCCMD) ECC Page size register\r
+#define HSMC4_ECCSR1    (AT91_CAST(AT91_REG *)         0x00000028) // (HSMC4_ECCSR1) ECC Status register 1\r
+#define HSMC4_ECCPR0    (AT91_CAST(AT91_REG *)         0x0000002C) // (HSMC4_ECCPR0) ECC Parity register 0\r
+#define HSMC4_ECCPR1    (AT91_CAST(AT91_REG *)         0x00000030) // (HSMC4_ECCPR1) ECC Parity register 1\r
+#define HSMC4_ECCSR2    (AT91_CAST(AT91_REG *)         0x00000034) // (HSMC4_ECCSR2) ECC Status register 2\r
+#define HSMC4_ECCPR2    (AT91_CAST(AT91_REG *)         0x00000038) // (HSMC4_ECCPR2) ECC Parity register 2\r
+#define HSMC4_ECCPR3    (AT91_CAST(AT91_REG *)         0x0000003C) // (HSMC4_ECCPR3) ECC Parity register 3\r
+#define HSMC4_ECCPR4    (AT91_CAST(AT91_REG *)         0x00000040) // (HSMC4_ECCPR4) ECC Parity register 4\r
+#define HSMC4_ECCPR5    (AT91_CAST(AT91_REG *)         0x00000044) // (HSMC4_ECCPR5) ECC Parity register 5\r
+#define HSMC4_ECCPR6    (AT91_CAST(AT91_REG *)         0x00000048) // (HSMC4_ECCPR6) ECC Parity register 6\r
+#define HSMC4_ECCPR7    (AT91_CAST(AT91_REG *)         0x0000004C) // (HSMC4_ECCPR7) ECC Parity register 7\r
+#define HSMC4_ECCPR8    (AT91_CAST(AT91_REG *)         0x00000050) // (HSMC4_ECCPR8) ECC Parity register 8\r
+#define HSMC4_ECCPR9    (AT91_CAST(AT91_REG *)         0x00000054) // (HSMC4_ECCPR9) ECC Parity register 9\r
+#define HSMC4_ECCPR10   (AT91_CAST(AT91_REG *)         0x00000058) // (HSMC4_ECCPR10) ECC Parity register 10\r
+#define HSMC4_ECCPR11   (AT91_CAST(AT91_REG *)         0x0000005C) // (HSMC4_ECCPR11) ECC Parity register 11\r
+#define HSMC4_ECCPR12   (AT91_CAST(AT91_REG *)         0x00000060) // (HSMC4_ECCPR12) ECC Parity register 12\r
+#define HSMC4_ECCPR13   (AT91_CAST(AT91_REG *)         0x00000064) // (HSMC4_ECCPR13) ECC Parity register 13\r
+#define HSMC4_ECCPR14   (AT91_CAST(AT91_REG *)         0x00000068) // (HSMC4_ECCPR14) ECC Parity register 14\r
+#define Hsmc4_Eccpr15   (AT91_CAST(AT91_REG *)         0x0000006C) // (Hsmc4_Eccpr15) ECC Parity register 15\r
+#define HSMC4_OCMS      (AT91_CAST(AT91_REG *)         0x00000110) // (HSMC4_OCMS) OCMS MODE register\r
+#define HSMC4_KEY1      (AT91_CAST(AT91_REG *)         0x00000114) // (HSMC4_KEY1) KEY1 Register\r
+#define HSMC4_KEY2      (AT91_CAST(AT91_REG *)         0x00000118) // (HSMC4_KEY2) KEY2 Register\r
+#define HSMC4_WPCR      (AT91_CAST(AT91_REG *)         0x000001E4) // (HSMC4_WPCR) Write Protection Control register\r
+#define HSMC4_WPSR      (AT91_CAST(AT91_REG *)         0x000001E8) // (HSMC4_WPSR) Write Protection Status Register\r
+#define HSMC4_ADDRSIZE  (AT91_CAST(AT91_REG *)         0x000001EC) // (HSMC4_ADDRSIZE) Write Protection Status Register\r
+#define HSMC4_IPNAME1   (AT91_CAST(AT91_REG *)         0x000001F0) // (HSMC4_IPNAME1) Write Protection Status Register\r
+#define HSMC4_IPNAME2   (AT91_CAST(AT91_REG *)         0x000001F4) // (HSMC4_IPNAME2) Write Protection Status Register\r
+#define HSMC4_FEATURES  (AT91_CAST(AT91_REG *)         0x000001F8) // (HSMC4_FEATURES) Write Protection Status Register\r
+#define HSMC4_VER       (AT91_CAST(AT91_REG *)         0x000001FC) // (HSMC4_VER) HSMC4 Version Register\r
+#define HSMC4_DUMMY     (AT91_CAST(AT91_REG *)         0x00000200) // (HSMC4_DUMMY) This rtegister was created only ti have AHB constants\r
+\r
+#endif\r
+// -------- HSMC4_CFG : (HSMC4 Offset: 0x0) Configuration Register -------- \r
+#define AT91C_HSMC4_PAGESIZE  (0x3 <<  0) // (HSMC4) PAGESIZE field description\r
+#define        AT91C_HSMC4_PAGESIZE_528_Bytes            (0x0) // (HSMC4) 512 bytes plus 16 bytes page size\r
+#define        AT91C_HSMC4_PAGESIZE_1056_Bytes           (0x1) // (HSMC4) 1024 bytes plus 32 bytes page size\r
+#define        AT91C_HSMC4_PAGESIZE_2112_Bytes           (0x2) // (HSMC4) 2048 bytes plus 64 bytes page size\r
+#define        AT91C_HSMC4_PAGESIZE_4224_Bytes           (0x3) // (HSMC4) 4096 bytes plus 128 bytes page size\r
+#define AT91C_HSMC4_WSPARE    (0x1 <<  8) // (HSMC4) Spare area access in Write Mode\r
+#define AT91C_HSMC4_RSPARE    (0x1 <<  9) // (HSMC4) Spare area access in Read Mode\r
+#define AT91C_HSMC4_EDGECTRL  (0x1 << 12) // (HSMC4) Rising/Falling Edge Detection Control\r
+#define AT91C_HSMC4_RBEDGE    (0x1 << 13) // (HSMC4) Ready/Busy Signal edge Detection\r
+#define AT91C_HSMC4_DTOCYC    (0xF << 16) // (HSMC4) Data Timeout Cycle Number\r
+#define AT91C_HSMC4_DTOMUL    (0x7 << 20) // (HSMC4) Data Timeout Multiplier\r
+#define        AT91C_HSMC4_DTOMUL_1                    (0x0 << 20) // (HSMC4) DTOCYC x 1\r
+#define        AT91C_HSMC4_DTOMUL_16                   (0x1 << 20) // (HSMC4) DTOCYC x 16\r
+#define        AT91C_HSMC4_DTOMUL_128                  (0x2 << 20) // (HSMC4) DTOCYC x 128\r
+#define        AT91C_HSMC4_DTOMUL_256                  (0x3 << 20) // (HSMC4) DTOCYC x 256\r
+#define        AT91C_HSMC4_DTOMUL_1024                 (0x4 << 20) // (HSMC4) DTOCYC x 1024\r
+#define        AT91C_HSMC4_DTOMUL_4096                 (0x5 << 20) // (HSMC4) DTOCYC x 4096\r
+#define        AT91C_HSMC4_DTOMUL_65536                (0x6 << 20) // (HSMC4) DTOCYC x 65536\r
+#define        AT91C_HSMC4_DTOMUL_1048576              (0x7 << 20) // (HSMC4) DTOCYC x 1048576\r
+// -------- HSMC4_CTRL : (HSMC4 Offset: 0x4) Control Register -------- \r
+#define AT91C_HSMC4_NFCEN     (0x1 <<  0) // (HSMC4) Nand Flash Controller Host Enable\r
+#define AT91C_HSMC4_NFCDIS    (0x1 <<  1) // (HSMC4) Nand Flash Controller Host Disable\r
+#define AT91C_HSMC4_HOSTEN    (0x1 <<  8) // (HSMC4) If set to one, the Host controller is activated and perform a data transfer phase.\r
+#define AT91C_HSMC4_HOSTWR    (0x1 << 11) // (HSMC4) If this field is set to one, the host transfers data from the internal SRAM to the Memory Device.\r
+#define AT91C_HSMC4_HOSTCSID  (0x7 << 12) // (HSMC4) Host Controller Chip select Id\r
+#define        AT91C_HSMC4_HOSTCSID_0                    (0x0 << 12) // (HSMC4) CS0\r
+#define        AT91C_HSMC4_HOSTCSID_1                    (0x1 << 12) // (HSMC4) CS1\r
+#define        AT91C_HSMC4_HOSTCSID_2                    (0x2 << 12) // (HSMC4) CS2\r
+#define        AT91C_HSMC4_HOSTCSID_3                    (0x3 << 12) // (HSMC4) CS3\r
+#define        AT91C_HSMC4_HOSTCSID_4                    (0x4 << 12) // (HSMC4) CS4\r
+#define        AT91C_HSMC4_HOSTCSID_5                    (0x5 << 12) // (HSMC4) CS5\r
+#define        AT91C_HSMC4_HOSTCSID_6                    (0x6 << 12) // (HSMC4) CS6\r
+#define        AT91C_HSMC4_HOSTCSID_7                    (0x7 << 12) // (HSMC4) CS7\r
+#define AT91C_HSMC4_VALID     (0x1 << 15) // (HSMC4) When set to 1, a write operation modifies both HOSTCSID and HOSTWR fields.\r
+// -------- HSMC4_SR : (HSMC4 Offset: 0x8) HSMC4 Status Register -------- \r
+#define AT91C_HSMC4_NFCSTS    (0x1 <<  0) // (HSMC4) Nand Flash Controller status\r
+#define AT91C_HSMC4_RBRISE    (0x1 <<  4) // (HSMC4) Selected Ready Busy Rising Edge Detected flag\r
+#define AT91C_HSMC4_RBFALL    (0x1 <<  5) // (HSMC4) Selected Ready Busy Falling Edge Detected flag\r
+#define AT91C_HSMC4_HOSTBUSY  (0x1 <<  8) // (HSMC4) Host Busy\r
+#define AT91C_HSMC4_HOSTW     (0x1 << 11) // (HSMC4) Host Write/Read Operation\r
+#define AT91C_HSMC4_HOSTCS    (0x7 << 12) // (HSMC4) Host Controller Chip select Id\r
+#define        AT91C_HSMC4_HOSTCS_0                    (0x0 << 12) // (HSMC4) CS0\r
+#define        AT91C_HSMC4_HOSTCS_1                    (0x1 << 12) // (HSMC4) CS1\r
+#define        AT91C_HSMC4_HOSTCS_2                    (0x2 << 12) // (HSMC4) CS2\r
+#define        AT91C_HSMC4_HOSTCS_3                    (0x3 << 12) // (HSMC4) CS3\r
+#define        AT91C_HSMC4_HOSTCS_4                    (0x4 << 12) // (HSMC4) CS4\r
+#define        AT91C_HSMC4_HOSTCS_5                    (0x5 << 12) // (HSMC4) CS5\r
+#define        AT91C_HSMC4_HOSTCS_6                    (0x6 << 12) // (HSMC4) CS6\r
+#define        AT91C_HSMC4_HOSTCS_7                    (0x7 << 12) // (HSMC4) CS7\r
+#define AT91C_HSMC4_XFRDONE   (0x1 << 16) // (HSMC4) Host Data Transfer Terminated\r
+#define AT91C_HSMC4_CMDDONE   (0x1 << 17) // (HSMC4) Command Done\r
+#define AT91C_HSMC4_ECCRDY    (0x1 << 18) // (HSMC4) ECC ready\r
+#define AT91C_HSMC4_DTOE      (0x1 << 20) // (HSMC4) Data timeout Error\r
+#define AT91C_HSMC4_UNDEF     (0x1 << 21) // (HSMC4) Undefined Area Error\r
+#define AT91C_HSMC4_AWB       (0x1 << 22) // (HSMC4) Accessing While Busy Error\r
+#define AT91C_HSMC4_HASE      (0x1 << 23) // (HSMC4) Host Controller Access Size Error\r
+#define AT91C_HSMC4_RBEDGE0   (0x1 << 24) // (HSMC4) Ready Busy line 0 Edge detected\r
+#define AT91C_HSMC4_RBEDGE1   (0x1 << 25) // (HSMC4) Ready Busy line 1 Edge detected\r
+#define AT91C_HSMC4_RBEDGE2   (0x1 << 26) // (HSMC4) Ready Busy line 2 Edge detected\r
+#define AT91C_HSMC4_RBEDGE3   (0x1 << 27) // (HSMC4) Ready Busy line 3 Edge detected\r
+#define AT91C_HSMC4_RBEDGE4   (0x1 << 28) // (HSMC4) Ready Busy line 4 Edge detected\r
+#define AT91C_HSMC4_RBEDGE5   (0x1 << 29) // (HSMC4) Ready Busy line 5 Edge detected\r
+#define AT91C_HSMC4_RBEDGE6   (0x1 << 30) // (HSMC4) Ready Busy line 6 Edge detected\r
+#define AT91C_HSMC4_RBEDGE7   (0x1 << 31) // (HSMC4) Ready Busy line 7 Edge detected\r
+// -------- HSMC4_IER : (HSMC4 Offset: 0xc) HSMC4 Interrupt Enable Register -------- \r
+// -------- HSMC4_IDR : (HSMC4 Offset: 0x10) HSMC4 Interrupt Disable Register -------- \r
+// -------- HSMC4_IMR : (HSMC4 Offset: 0x14) HSMC4 Interrupt Mask Register -------- \r
+// -------- HSMC4_ADDR : (HSMC4 Offset: 0x18) Address Cycle Zero Register -------- \r
+#define AT91C_HSMC4_ADDRCYCLE0 (0xFF <<  0) // (HSMC4) Nand Flash Array Address cycle 0\r
+// -------- HSMC4_BANK : (HSMC4 Offset: 0x1c) Bank Register -------- \r
+#define AT91C_BANK            (0x7 <<  0) // (HSMC4) Bank identifier\r
+#define        AT91C_BANK_0                    (0x0) // (HSMC4) BANK0\r
+#define        AT91C_BANK_1                    (0x1) // (HSMC4) BANK1\r
+#define        AT91C_BANK_2                    (0x2) // (HSMC4) BANK2\r
+#define        AT91C_BANK_3                    (0x3) // (HSMC4) BANK3\r
+#define        AT91C_BANK_4                    (0x4) // (HSMC4) BANK4\r
+#define        AT91C_BANK_5                    (0x5) // (HSMC4) BANK5\r
+#define        AT91C_BANK_6                    (0x6) // (HSMC4) BANK6\r
+#define        AT91C_BANK_7                    (0x7) // (HSMC4) BANK7\r
+// -------- HSMC4_ECCCR : (HSMC4 Offset: 0x20) ECC Control Register -------- \r
+#define AT91C_HSMC4_ECCRESET  (0x1 <<  0) // (HSMC4) Reset ECC\r
+// -------- HSMC4_ECCCMD : (HSMC4 Offset: 0x24) ECC mode register -------- \r
+#define AT91C_ECC_PAGE_SIZE   (0x3 <<  0) // (HSMC4) Nand Flash page size\r
+#define AT91C_ECC_TYPCORRECT  (0x3 <<  4) // (HSMC4) Nand Flash page size\r
+#define        AT91C_ECC_TYPCORRECT_ONE_PER_PAGE         (0x0 <<  4) // (HSMC4) \r
+#define        AT91C_ECC_TYPCORRECT_ONE_EVERY_256_BYTES  (0x1 <<  4) // (HSMC4) \r
+#define        AT91C_ECC_TYPCORRECT_ONE_EVERY_512_BYTES  (0x2 <<  4) // (HSMC4) \r
+// -------- HSMC4_ECCSR1 : (HSMC4 Offset: 0x28) ECC Status Register 1 -------- \r
+#define AT91C_HSMC4_ECC_RECERR0 (0x1 <<  0) // (HSMC4) Recoverable Error\r
+#define AT91C_HSMC4_ECC_ECCERR0 (0x1 <<  1) // (HSMC4) ECC Error\r
+#define AT91C_HSMC4_ECC_MULERR0 (0x1 <<  2) // (HSMC4) Multiple Error\r
+#define AT91C_HSMC4_ECC_RECERR1 (0x1 <<  4) // (HSMC4) Recoverable Error\r
+#define AT91C_HSMC4_ECC_ECCERR1 (0x1 <<  5) // (HSMC4) ECC Error\r
+#define AT91C_HSMC4_ECC_MULERR1 (0x1 <<  6) // (HSMC4) Multiple Error\r
+#define AT91C_HSMC4_ECC_RECERR2 (0x1 <<  8) // (HSMC4) Recoverable Error\r
+#define AT91C_HSMC4_ECC_ECCERR2 (0x1 <<  9) // (HSMC4) ECC Error\r
+#define AT91C_HSMC4_ECC_MULERR2 (0x1 << 10) // (HSMC4) Multiple Error\r
+#define AT91C_HSMC4_ECC_RECERR3 (0x1 << 12) // (HSMC4) Recoverable Error\r
+#define AT91C_HSMC4_ECC_ECCERR3 (0x1 << 13) // (HSMC4) ECC Error\r
+#define AT91C_HSMC4_ECC_MULERR3 (0x1 << 14) // (HSMC4) Multiple Error\r
+#define AT91C_HSMC4_ECC_RECERR4 (0x1 << 16) // (HSMC4) Recoverable Error\r
+#define AT91C_HSMC4_ECC_ECCERR4 (0x1 << 17) // (HSMC4) ECC Error\r
+#define AT91C_HSMC4_ECC_MULERR4 (0x1 << 18) // (HSMC4) Multiple Error\r
+#define AT91C_HSMC4_ECC_RECERR5 (0x1 << 20) // (HSMC4) Recoverable Error\r
+#define AT91C_HSMC4_ECC_ECCERR5 (0x1 << 21) // (HSMC4) ECC Error\r
+#define AT91C_HSMC4_ECC_MULERR5 (0x1 << 22) // (HSMC4) Multiple Error\r
+#define AT91C_HSMC4_ECC_RECERR6 (0x1 << 24) // (HSMC4) Recoverable Error\r
+#define AT91C_HSMC4_ECC_ECCERR6 (0x1 << 25) // (HSMC4) ECC Error\r
+#define AT91C_HSMC4_ECC_MULERR6 (0x1 << 26) // (HSMC4) Multiple Error\r
+#define AT91C_HSMC4_ECC_RECERR7 (0x1 << 28) // (HSMC4) Recoverable Error\r
+#define AT91C_HSMC4_ECC_ECCERR7 (0x1 << 29) // (HSMC4) ECC Error\r
+#define AT91C_HSMC4_ECC_MULERR7 (0x1 << 30) // (HSMC4) Multiple Error\r
+// -------- HSMC4_ECCPR0 : (HSMC4 Offset: 0x2c) HSMC4 ECC parity Register 0 -------- \r
+#define AT91C_HSMC4_ECC_BITADDR (0x7 <<  0) // (HSMC4) Corrupted Bit Address in the page\r
+#define AT91C_HSMC4_ECC_WORDADDR (0xFF <<  3) // (HSMC4) Corrupted Word Address in the page\r
+#define AT91C_HSMC4_ECC_NPARITY (0x7FF << 12) // (HSMC4) Parity N\r
+// -------- HSMC4_ECCPR1 : (HSMC4 Offset: 0x30) HSMC4 ECC parity Register 1 -------- \r
+// -------- HSMC4_ECCSR2 : (HSMC4 Offset: 0x34) ECC Status Register 2 -------- \r
+#define AT91C_HSMC4_ECC_RECERR8 (0x1 <<  0) // (HSMC4) Recoverable Error\r
+#define AT91C_HSMC4_ECC_ECCERR8 (0x1 <<  1) // (HSMC4) ECC Error\r
+#define AT91C_HSMC4_ECC_MULERR8 (0x1 <<  2) // (HSMC4) Multiple Error\r
+#define AT91C_HSMC4_ECC_RECERR9 (0x1 <<  4) // (HSMC4) Recoverable Error\r
+#define AT91C_HSMC4_ECC_ECCERR9 (0x1 <<  5) // (HSMC4) ECC Error\r
+#define AT91C_HSMC4_ECC_MULERR9 (0x1 <<  6) // (HSMC4) Multiple Error\r
+#define AT91C_HSMC4_ECC_RECERR10 (0x1 <<  8) // (HSMC4) Recoverable Error\r
+#define AT91C_HSMC4_ECC_ECCERR10 (0x1 <<  9) // (HSMC4) ECC Error\r
+#define AT91C_HSMC4_ECC_MULERR10 (0x1 << 10) // (HSMC4) Multiple Error\r
+#define AT91C_HSMC4_ECC_RECERR11 (0x1 << 12) // (HSMC4) Recoverable Error\r
+#define AT91C_HSMC4_ECC_ECCERR11 (0x1 << 13) // (HSMC4) ECC Error\r
+#define AT91C_HSMC4_ECC_MULERR11 (0x1 << 14) // (HSMC4) Multiple Error\r
+#define AT91C_HSMC4_ECC_RECERR12 (0x1 << 16) // (HSMC4) Recoverable Error\r
+#define AT91C_HSMC4_ECC_ECCERR12 (0x1 << 17) // (HSMC4) ECC Error\r
+#define AT91C_HSMC4_ECC_MULERR12 (0x1 << 18) // (HSMC4) Multiple Error\r
+#define AT91C_HSMC4_ECC_RECERR13 (0x1 << 20) // (HSMC4) Recoverable Error\r
+#define AT91C_HSMC4_ECC_ECCERR13 (0x1 << 21) // (HSMC4) ECC Error\r
+#define AT91C_HSMC4_ECC_MULERR13 (0x1 << 22) // (HSMC4) Multiple Error\r
+#define AT91C_HSMC4_ECC_RECERR14 (0x1 << 24) // (HSMC4) Recoverable Error\r
+#define AT91C_HSMC4_ECC_ECCERR14 (0x1 << 25) // (HSMC4) ECC Error\r
+#define AT91C_HSMC4_ECC_MULERR14 (0x1 << 26) // (HSMC4) Multiple Error\r
+#define AT91C_HSMC4_ECC_RECERR15 (0x1 << 28) // (HSMC4) Recoverable Error\r
+#define AT91C_HSMC4_ECC_ECCERR15 (0x1 << 29) // (HSMC4) ECC Error\r
+#define AT91C_HSMC4_ECC_MULERR15 (0x1 << 30) // (HSMC4) Multiple Error\r
+// -------- HSMC4_ECCPR2 : (HSMC4 Offset: 0x38) HSMC4 ECC parity Register 2 -------- \r
+// -------- HSMC4_ECCPR3 : (HSMC4 Offset: 0x3c) HSMC4 ECC parity Register 3 -------- \r
+// -------- HSMC4_ECCPR4 : (HSMC4 Offset: 0x40) HSMC4 ECC parity Register 4 -------- \r
+// -------- HSMC4_ECCPR5 : (HSMC4 Offset: 0x44) HSMC4 ECC parity Register 5 -------- \r
+// -------- HSMC4_ECCPR6 : (HSMC4 Offset: 0x48) HSMC4 ECC parity Register 6 -------- \r
+// -------- HSMC4_ECCPR7 : (HSMC4 Offset: 0x4c) HSMC4 ECC parity Register 7 -------- \r
+// -------- HSMC4_ECCPR8 : (HSMC4 Offset: 0x50) HSMC4 ECC parity Register 8 -------- \r
+// -------- HSMC4_ECCPR9 : (HSMC4 Offset: 0x54) HSMC4 ECC parity Register 9 -------- \r
+// -------- HSMC4_ECCPR10 : (HSMC4 Offset: 0x58) HSMC4 ECC parity Register 10 -------- \r
+// -------- HSMC4_ECCPR11 : (HSMC4 Offset: 0x5c) HSMC4 ECC parity Register 11 -------- \r
+// -------- HSMC4_ECCPR12 : (HSMC4 Offset: 0x60) HSMC4 ECC parity Register 12 -------- \r
+// -------- HSMC4_ECCPR13 : (HSMC4 Offset: 0x64) HSMC4 ECC parity Register 13 -------- \r
+// -------- HSMC4_ECCPR14 : (HSMC4 Offset: 0x68) HSMC4 ECC parity Register 14 -------- \r
+// -------- HSMC4_ECCPR15 : (HSMC4 Offset: 0x6c) HSMC4 ECC parity Register 15 -------- \r
+// -------- HSMC4_OCMS : (HSMC4 Offset: 0x110) HSMC4 OCMS Register -------- \r
+#define AT91C_HSMC4_OCMS_SRSE (0x1 <<  0) // (HSMC4) Static Memory Controller Scrambling Enable\r
+#define AT91C_HSMC4_OCMS_SMSE (0x1 <<  1) // (HSMC4) SRAM Scramling Enable\r
+// -------- HSMC4_KEY1 : (HSMC4 Offset: 0x114) HSMC4 OCMS KEY1 Register -------- \r
+#define AT91C_HSMC4_OCMS_KEY1 (0x0 <<  0) // (HSMC4) OCMS Key 2\r
+// -------- HSMC4_OCMS_KEY2 : (HSMC4 Offset: 0x118) HSMC4 OCMS KEY2 Register -------- \r
+#define AT91C_HSMC4_OCMS_KEY2 (0x0 <<  0) // (HSMC4) OCMS Key 2\r
+// -------- HSMC4_WPCR : (HSMC4 Offset: 0x1e4) HSMC4 Witre Protection Control Register -------- \r
+#define AT91C_HSMC4_WP_EN     (0x1 <<  0) // (HSMC4) Write Protection Enable\r
+#define AT91C_HSMC4_WP_KEY    (0xFFFFFF <<  8) // (HSMC4) Protection Password\r
+// -------- HSMC4_WPSR : (HSMC4 Offset: 0x1e8) HSMC4 WPSR Register -------- \r
+#define AT91C_HSMC4_WP_VS     (0xF <<  0) // (HSMC4) Write Protection Violation Status\r
+#define        AT91C_HSMC4_WP_VS_WP_VS0               (0x0) // (HSMC4) No write protection violation since the last read of this register\r
+#define        AT91C_HSMC4_WP_VS_WP_VS1               (0x1) // (HSMC4) write protection detected unauthorized attempt to write a control register had occured (since the last read)\r
+#define        AT91C_HSMC4_WP_VS_WP_VS2               (0x2) // (HSMC4) Software reset had been performed while write protection was enabled (since the last read)\r
+#define        AT91C_HSMC4_WP_VS_WP_VS3               (0x3) // (HSMC4) Both write protection violation and software reset with write protection enabled had occured since the last read\r
+#define AT91C_                (0x0 <<  8) // (HSMC4) \r
+// -------- HSMC4_VER : (HSMC4 Offset: 0x1fc) HSMC4 VERSION Register -------- \r
+// -------- HSMC4_DUMMY : (HSMC4 Offset: 0x200) HSMC4 DUMMY REGISTER -------- \r
+#define AT91C_HSMC4_CMD1      (0xFF <<  2) // (HSMC4) Command Register Value for Cycle 1\r
+#define AT91C_HSMC4_CMD2      (0xFF << 10) // (HSMC4) Command Register Value for Cycle 2\r
+#define AT91C_HSMC4_VCMD2     (0x1 << 18) // (HSMC4) Valid Cycle 2 Command\r
+#define AT91C_HSMC4_ACYCLE    (0x7 << 19) // (HSMC4) Number of Address required for the current command\r
+#define        AT91C_HSMC4_ACYCLE_HSMC4_ACYCLE_NONE    (0x0 << 19) // (HSMC4) No address cycle\r
+#define        AT91C_HSMC4_ACYCLE_HSMC4_ACYCLE_ONE     (0x1 << 19) // (HSMC4) One address cycle\r
+#define        AT91C_HSMC4_ACYCLE_HSMC4_ACYCLE_TWO     (0x2 << 19) // (HSMC4) Two address cycles\r
+#define        AT91C_HSMC4_ACYCLE_HSMC4_ACYCLE_THREE   (0x3 << 19) // (HSMC4) Three address cycles\r
+#define        AT91C_HSMC4_ACYCLE_HSMC4_ACYCLE_FOUR    (0x4 << 19) // (HSMC4) Four address cycles\r
+#define        AT91C_HSMC4_ACYCLE_HSMC4_ACYCLE_FIVE    (0x5 << 19) // (HSMC4) Five address cycles\r
+#define AT91C_HSMC4_CSID      (0x7 << 22) // (HSMC4) Chip Select Identifier\r
+#define        AT91C_HSMC4_CSID_0                    (0x0 << 22) // (HSMC4) CS0\r
+#define        AT91C_HSMC4_CSID_1                    (0x1 << 22) // (HSMC4) CS1\r
+#define        AT91C_HSMC4_CSID_2                    (0x2 << 22) // (HSMC4) CS2\r
+#define        AT91C_HSMC4_CSID_3                    (0x3 << 22) // (HSMC4) CS3\r
+#define        AT91C_HSMC4_CSID_4                    (0x4 << 22) // (HSMC4) CS4\r
+#define        AT91C_HSMC4_CSID_5                    (0x5 << 22) // (HSMC4) CS5\r
+#define        AT91C_HSMC4_CSID_6                    (0x6 << 22) // (HSMC4) CS6\r
+#define        AT91C_HSMC4_CSID_7                    (0x7 << 22) // (HSMC4) CS7\r
+#define AT91C_HSMC4_HOST_EN   (0x1 << 25) // (HSMC4) Host Main Controller Enable\r
+#define AT91C_HSMC4_HOST_WR   (0x1 << 26) // (HSMC4) HOSTWR : Host Main Controller Write Enable\r
+#define AT91C_HSMC4_HOSTCMD   (0x1 << 27) // (HSMC4) Host Command Enable\r
+\r
+// *****************************************************************************\r
+//              SOFTWARE API DEFINITION  FOR AHB Matrix2 Interface\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_HMATRIX2 {\r
+       AT91_REG         HMATRIX2_MCFG0;        //  Master Configuration Register 0 : ARM I and D\r
+       AT91_REG         HMATRIX2_MCFG1;        //  Master Configuration Register 1 : ARM S\r
+       AT91_REG         HMATRIX2_MCFG2;        //  Master Configuration Register 2\r
+       AT91_REG         HMATRIX2_MCFG3;        //  Master Configuration Register 3\r
+       AT91_REG         HMATRIX2_MCFG4;        //  Master Configuration Register 4\r
+       AT91_REG         HMATRIX2_MCFG5;        //  Master Configuration Register 5\r
+       AT91_REG         HMATRIX2_MCFG6;        //  Master Configuration Register 6\r
+       AT91_REG         HMATRIX2_MCFG7;        //  Master Configuration Register 7\r
+       AT91_REG         Reserved0[8];  // \r
+       AT91_REG         HMATRIX2_SCFG0;        //  Slave Configuration Register 0\r
+       AT91_REG         HMATRIX2_SCFG1;        //  Slave Configuration Register 1\r
+       AT91_REG         HMATRIX2_SCFG2;        //  Slave Configuration Register 2\r
+       AT91_REG         HMATRIX2_SCFG3;        //  Slave Configuration Register 3\r
+       AT91_REG         HMATRIX2_SCFG4;        //  Slave Configuration Register 4\r
+       AT91_REG         HMATRIX2_SCFG5;        //  Slave Configuration Register 5\r
+       AT91_REG         HMATRIX2_SCFG6;        //  Slave Configuration Register 6\r
+       AT91_REG         HMATRIX2_SCFG7;        //  Slave Configuration Register 5\r
+       AT91_REG         HMATRIX2_SCFG8;        //  Slave Configuration Register 8\r
+       AT91_REG         Reserved1[43];         // \r
+       AT91_REG         HMATRIX2_SFR0 ;        //  Special Function Register 0\r
+       AT91_REG         HMATRIX2_SFR1 ;        //  Special Function Register 1\r
+       AT91_REG         HMATRIX2_SFR2 ;        //  Special Function Register 2\r
+       AT91_REG         HMATRIX2_SFR3 ;        //  Special Function Register 3\r
+       AT91_REG         HMATRIX2_SFR4 ;        //  Special Function Register 4\r
+       AT91_REG         HMATRIX2_SFR5 ;        //  Special Function Register 5\r
+       AT91_REG         HMATRIX2_SFR6 ;        //  Special Function Register 6\r
+       AT91_REG         HMATRIX2_SFR7 ;        //  Special Function Register 7\r
+       AT91_REG         HMATRIX2_SFR8 ;        //  Special Function Register 8\r
+       AT91_REG         HMATRIX2_SFR9 ;        //  Special Function Register 9\r
+       AT91_REG         HMATRIX2_SFR10;        //  Special Function Register 10\r
+       AT91_REG         HMATRIX2_SFR11;        //  Special Function Register 11\r
+       AT91_REG         HMATRIX2_SFR12;        //  Special Function Register 12\r
+       AT91_REG         HMATRIX2_SFR13;        //  Special Function Register 13\r
+       AT91_REG         HMATRIX2_SFR14;        //  Special Function Register 14\r
+       AT91_REG         HMATRIX2_SFR15;        //  Special Function Register 15\r
+       AT91_REG         Reserved2[39];         // \r
+       AT91_REG         HMATRIX2_ADDRSIZE;     // HMATRIX2 ADDRSIZE REGISTER \r
+       AT91_REG         HMATRIX2_IPNAME1;      // HMATRIX2 IPNAME1 REGISTER \r
+       AT91_REG         HMATRIX2_IPNAME2;      // HMATRIX2 IPNAME2 REGISTER \r
+       AT91_REG         HMATRIX2_FEATURES;     // HMATRIX2 FEATURES REGISTER \r
+       AT91_REG         HMATRIX2_VER;  // HMATRIX2 VERSION REGISTER \r
+} AT91S_HMATRIX2, *AT91PS_HMATRIX2;\r
+#else\r
+#define MATRIX_MCFG0    (AT91_CAST(AT91_REG *)         0x00000000) // (MATRIX_MCFG0)  Master Configuration Register 0 : ARM I and D\r
+#define MATRIX_MCFG1    (AT91_CAST(AT91_REG *)         0x00000004) // (MATRIX_MCFG1)  Master Configuration Register 1 : ARM S\r
+#define MATRIX_MCFG2    (AT91_CAST(AT91_REG *)         0x00000008) // (MATRIX_MCFG2)  Master Configuration Register 2\r
+#define MATRIX_MCFG3    (AT91_CAST(AT91_REG *)         0x0000000C) // (MATRIX_MCFG3)  Master Configuration Register 3\r
+#define MATRIX_MCFG4    (AT91_CAST(AT91_REG *)         0x00000010) // (MATRIX_MCFG4)  Master Configuration Register 4\r
+#define MATRIX_MCFG5    (AT91_CAST(AT91_REG *)         0x00000014) // (MATRIX_MCFG5)  Master Configuration Register 5\r
+#define MATRIX_MCFG6    (AT91_CAST(AT91_REG *)         0x00000018) // (MATRIX_MCFG6)  Master Configuration Register 6\r
+#define MATRIX_MCFG7    (AT91_CAST(AT91_REG *)         0x0000001C) // (MATRIX_MCFG7)  Master Configuration Register 7\r
+#define MATRIX_SCFG0    (AT91_CAST(AT91_REG *)         0x00000040) // (MATRIX_SCFG0)  Slave Configuration Register 0\r
+#define MATRIX_SCFG1    (AT91_CAST(AT91_REG *)         0x00000044) // (MATRIX_SCFG1)  Slave Configuration Register 1\r
+#define MATRIX_SCFG2    (AT91_CAST(AT91_REG *)         0x00000048) // (MATRIX_SCFG2)  Slave Configuration Register 2\r
+#define MATRIX_SCFG3    (AT91_CAST(AT91_REG *)         0x0000004C) // (MATRIX_SCFG3)  Slave Configuration Register 3\r
+#define MATRIX_SCFG4    (AT91_CAST(AT91_REG *)         0x00000050) // (MATRIX_SCFG4)  Slave Configuration Register 4\r
+#define MATRIX_SCFG5    (AT91_CAST(AT91_REG *)         0x00000054) // (MATRIX_SCFG5)  Slave Configuration Register 5\r
+#define MATRIX_SCFG6    (AT91_CAST(AT91_REG *)         0x00000058) // (MATRIX_SCFG6)  Slave Configuration Register 6\r
+#define MATRIX_SCFG7    (AT91_CAST(AT91_REG *)         0x0000005C) // (MATRIX_SCFG7)  Slave Configuration Register 5\r
+#define MATRIX_SCFG8    (AT91_CAST(AT91_REG *)         0x00000060) // (MATRIX_SCFG8)  Slave Configuration Register 8\r
+#define MATRIX_SFR0     (AT91_CAST(AT91_REG *)         0x00000110) // (MATRIX_SFR0 )  Special Function Register 0\r
+#define MATRIX_SFR1     (AT91_CAST(AT91_REG *)         0x00000114) // (MATRIX_SFR1 )  Special Function Register 1\r
+#define MATRIX_SFR2     (AT91_CAST(AT91_REG *)         0x00000118) // (MATRIX_SFR2 )  Special Function Register 2\r
+#define MATRIX_SFR3     (AT91_CAST(AT91_REG *)         0x0000011C) // (MATRIX_SFR3 )  Special Function Register 3\r
+#define MATRIX_SFR4     (AT91_CAST(AT91_REG *)         0x00000120) // (MATRIX_SFR4 )  Special Function Register 4\r
+#define MATRIX_SFR5     (AT91_CAST(AT91_REG *)         0x00000124) // (MATRIX_SFR5 )  Special Function Register 5\r
+#define MATRIX_SFR6     (AT91_CAST(AT91_REG *)         0x00000128) // (MATRIX_SFR6 )  Special Function Register 6\r
+#define MATRIX_SFR7     (AT91_CAST(AT91_REG *)         0x0000012C) // (MATRIX_SFR7 )  Special Function Register 7\r
+#define MATRIX_SFR8     (AT91_CAST(AT91_REG *)         0x00000130) // (MATRIX_SFR8 )  Special Function Register 8\r
+#define MATRIX_SFR9     (AT91_CAST(AT91_REG *)         0x00000134) // (MATRIX_SFR9 )  Special Function Register 9\r
+#define MATRIX_SFR10    (AT91_CAST(AT91_REG *)         0x00000138) // (MATRIX_SFR10)  Special Function Register 10\r
+#define MATRIX_SFR11    (AT91_CAST(AT91_REG *)         0x0000013C) // (MATRIX_SFR11)  Special Function Register 11\r
+#define MATRIX_SFR12    (AT91_CAST(AT91_REG *)         0x00000140) // (MATRIX_SFR12)  Special Function Register 12\r
+#define MATRIX_SFR13    (AT91_CAST(AT91_REG *)         0x00000144) // (MATRIX_SFR13)  Special Function Register 13\r
+#define MATRIX_SFR14    (AT91_CAST(AT91_REG *)         0x00000148) // (MATRIX_SFR14)  Special Function Register 14\r
+#define MATRIX_SFR15    (AT91_CAST(AT91_REG *)         0x0000014C) // (MATRIX_SFR15)  Special Function Register 15\r
+#define HMATRIX2_ADDRSIZE (AT91_CAST(AT91_REG *)       0x000001EC) // (HMATRIX2_ADDRSIZE) HMATRIX2 ADDRSIZE REGISTER \r
+#define HMATRIX2_IPNAME1 (AT91_CAST(AT91_REG *)        0x000001F0) // (HMATRIX2_IPNAME1) HMATRIX2 IPNAME1 REGISTER \r
+#define HMATRIX2_IPNAME2 (AT91_CAST(AT91_REG *)        0x000001F4) // (HMATRIX2_IPNAME2) HMATRIX2 IPNAME2 REGISTER \r
+#define HMATRIX2_FEATURES (AT91_CAST(AT91_REG *)       0x000001F8) // (HMATRIX2_FEATURES) HMATRIX2 FEATURES REGISTER \r
+#define HMATRIX2_VER    (AT91_CAST(AT91_REG *)         0x000001FC) // (HMATRIX2_VER) HMATRIX2 VERSION REGISTER \r
+\r
+#endif\r
+// -------- MATRIX_MCFG0 : (HMATRIX2 Offset: 0x0) Master Configuration Register ARM bus I and D -------- \r
+#define AT91C_MATRIX_ULBT     (0x7 <<  0) // (HMATRIX2) Undefined Length Burst Type\r
+#define        AT91C_MATRIX_ULBT_INFINIT_LENGTH       (0x0) // (HMATRIX2) infinite length burst\r
+#define        AT91C_MATRIX_ULBT_SINGLE_ACCESS        (0x1) // (HMATRIX2) Single Access\r
+#define        AT91C_MATRIX_ULBT_4_BEAT               (0x2) // (HMATRIX2) 4 Beat Burst\r
+#define        AT91C_MATRIX_ULBT_8_BEAT               (0x3) // (HMATRIX2) 8 Beat Burst\r
+#define        AT91C_MATRIX_ULBT_16_BEAT              (0x4) // (HMATRIX2) 16 Beat Burst\r
+#define        AT91C_MATRIX_ULBT_32_BEAT              (0x5) // (HMATRIX2) 32 Beat Burst\r
+#define        AT91C_MATRIX_ULBT_64_BEAT              (0x6) // (HMATRIX2) 64 Beat Burst\r
+#define        AT91C_MATRIX_ULBT_128_BEAT             (0x7) // (HMATRIX2) 128 Beat Burst\r
+// -------- MATRIX_MCFG1 : (HMATRIX2 Offset: 0x4) Master Configuration Register ARM bus S -------- \r
+// -------- MATRIX_MCFG2 : (HMATRIX2 Offset: 0x8) Master Configuration Register -------- \r
+// -------- MATRIX_MCFG3 : (HMATRIX2 Offset: 0xc) Master Configuration Register -------- \r
+// -------- MATRIX_MCFG4 : (HMATRIX2 Offset: 0x10) Master Configuration Register -------- \r
+// -------- MATRIX_MCFG5 : (HMATRIX2 Offset: 0x14) Master Configuration Register -------- \r
+// -------- MATRIX_MCFG6 : (HMATRIX2 Offset: 0x18) Master Configuration Register -------- \r
+// -------- MATRIX_MCFG7 : (HMATRIX2 Offset: 0x1c) Master Configuration Register -------- \r
+// -------- MATRIX_SCFG0 : (HMATRIX2 Offset: 0x40) Slave Configuration Register 0 -------- \r
+#define AT91C_MATRIX_SLOT_CYCLE (0xFF <<  0) // (HMATRIX2) Maximum Number of Allowed Cycles for a Burst\r
+#define AT91C_MATRIX_DEFMSTR_TYPE (0x3 << 16) // (HMATRIX2) Default Master Type\r
+#define        AT91C_MATRIX_DEFMSTR_TYPE_NO_DEFMSTR           (0x0 << 16) // (HMATRIX2) No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This results in having a one cycle latency for the first transfer of a burst.\r
+#define        AT91C_MATRIX_DEFMSTR_TYPE_LAST_DEFMSTR         (0x1 << 16) // (HMATRIX2) Last Default Master. At the end of current slave access, if no other master request is pending, the slave stay connected with the last master having accessed it. This results in not having the one cycle latency when the last master re-trying access on the slave.\r
+#define        AT91C_MATRIX_DEFMSTR_TYPE_FIXED_DEFMSTR        (0x2 << 16) // (HMATRIX2) Fixed Default Master. At the end of current slave access, if no other master request is pending, the slave connects with fixed which number is in FIXED_DEFMSTR field. This results in not having the one cycle latency when the fixed master re-trying access on the slave.\r
+#define AT91C_MATRIX_FIXED_DEFMSTR_SCFG0 (0x7 << 18) // (HMATRIX2) Fixed Index of Default Master\r
+#define        AT91C_MATRIX_FIXED_DEFMSTR_SCFG0_ARMS                 (0x1 << 18) // (HMATRIX2) ARMS is Default Master\r
+// -------- MATRIX_SCFG1 : (HMATRIX2 Offset: 0x44) Slave Configuration Register 1 -------- \r
+#define AT91C_MATRIX_FIXED_DEFMSTR_SCFG1 (0x7 << 18) // (HMATRIX2) Fixed Index of Default Master\r
+#define        AT91C_MATRIX_FIXED_DEFMSTR_SCFG1_ARMS                 (0x1 << 18) // (HMATRIX2) ARMS is Default Master\r
+// -------- MATRIX_SCFG2 : (HMATRIX2 Offset: 0x48) Slave Configuration Register 2 -------- \r
+#define AT91C_MATRIX_FIXED_DEFMSTR_SCFG2 (0x7 << 18) // (HMATRIX2) Fixed Index of Default Master\r
+#define        AT91C_MATRIX_FIXED_DEFMSTR_SCFG2_ARMS                 (0x1 << 18) // (HMATRIX2) ARMS is Default Master\r
+// -------- MATRIX_SCFG3 : (HMATRIX2 Offset: 0x4c) Slave Configuration Register 3 -------- \r
+#define AT91C_MATRIX_FIXED_DEFMSTR_SCFG3 (0x7 << 18) // (HMATRIX2) Fixed Index of Default Master\r
+#define        AT91C_MATRIX_FIXED_DEFMSTR_SCFG3_ARMC                 (0x0 << 18) // (HMATRIX2) ARMC is Default Master\r
+// -------- MATRIX_SCFG4 : (HMATRIX2 Offset: 0x50) Slave Configuration Register 4 -------- \r
+#define AT91C_MATRIX_FIXED_DEFMSTR_SCFG4 (0x7 << 18) // (HMATRIX2) Fixed Index of Default Master\r
+#define        AT91C_MATRIX_FIXED_DEFMSTR_SCFG4_ARMS                 (0x1 << 18) // (HMATRIX2) ARMS is Default Master\r
+// -------- MATRIX_SCFG5 : (HMATRIX2 Offset: 0x54) Slave Configuration Register 5 -------- \r
+#define AT91C_MATRIX_FIXED_DEFMSTR_SCFG5 (0x7 << 18) // (HMATRIX2) Fixed Index of Default Master\r
+#define        AT91C_MATRIX_FIXED_DEFMSTR_SCFG5_ARMS                 (0x1 << 18) // (HMATRIX2) ARMS is Default Master\r
+// -------- MATRIX_SCFG6 : (HMATRIX2 Offset: 0x58) Slave Configuration Register 6 -------- \r
+#define AT91C_MATRIX_FIXED_DEFMSTR_SCFG6 (0x7 << 18) // (HMATRIX2) Fixed Index of Default Master\r
+#define        AT91C_MATRIX_FIXED_DEFMSTR_SCFG6_ARMS                 (0x1 << 18) // (HMATRIX2) ARMS is Default Master\r
+// -------- MATRIX_SCFG7 : (HMATRIX2 Offset: 0x5c) Slave Configuration Register 7 -------- \r
+#define AT91C_MATRIX_FIXED_DEFMSTR_SCFG7 (0x7 << 18) // (HMATRIX2) Fixed Index of Default Master\r
+#define        AT91C_MATRIX_FIXED_DEFMSTR_SCFG7_ARMS                 (0x1 << 18) // (HMATRIX2) ARMS is Default Master\r
+// -------- MATRIX_SCFG8 : (HMATRIX2 Offset: 0x60) Slave Configuration Register 8 -------- \r
+#define AT91C_MATRIX_FIXED_DEFMSTR_SCFG8 (0x7 << 18) // (HMATRIX2) Fixed Index of Default Master\r
+#define        AT91C_MATRIX_FIXED_DEFMSTR_SCFG8_ARMS                 (0x1 << 18) // (HMATRIX2) ARMS is Default Master\r
+#define        AT91C_MATRIX_FIXED_DEFMSTR_SCFG8_HDMA                 (0x4 << 18) // (HMATRIX2) HDMA is Default Master\r
+// -------- MATRIX_SFR0 : (HMATRIX2 Offset: 0x110) Special Function Register 0 -------- \r
+// -------- MATRIX_SFR0 : (HMATRIX2 Offset: 0x114) Special Function Register 0 -------- \r
+// -------- MATRIX_SFR0 : (HMATRIX2 Offset: 0x118) Special Function Register 0 -------- \r
+// -------- MATRIX_SFR0 : (HMATRIX2 Offset: 0x11c) Special Function Register 0 -------- \r
+// -------- MATRIX_SFR0 : (HMATRIX2 Offset: 0x120) Special Function Register 0 -------- \r
+// -------- MATRIX_SFR0 : (HMATRIX2 Offset: 0x124) Special Function Register 0 -------- \r
+// -------- MATRIX_SFR0 : (HMATRIX2 Offset: 0x128) Special Function Register 0 -------- \r
+// -------- MATRIX_SFR0 : (HMATRIX2 Offset: 0x12c) Special Function Register 0 -------- \r
+// -------- MATRIX_SFR0 : (HMATRIX2 Offset: 0x130) Special Function Register 0 -------- \r
+// -------- MATRIX_SFR0 : (HMATRIX2 Offset: 0x134) Special Function Register 0 -------- \r
+// -------- MATRIX_SFR0 : (HMATRIX2 Offset: 0x138) Special Function Register 0 -------- \r
+// -------- MATRIX_SFR0 : (HMATRIX2 Offset: 0x13c) Special Function Register 0 -------- \r
+// -------- MATRIX_SFR0 : (HMATRIX2 Offset: 0x140) Special Function Register 0 -------- \r
+// -------- MATRIX_SFR0 : (HMATRIX2 Offset: 0x144) Special Function Register 0 -------- \r
+// -------- MATRIX_SFR0 : (HMATRIX2 Offset: 0x148) Special Function Register 0 -------- \r
+// -------- MATRIX_SFR0 : (HMATRIX2 Offset: 0x14c) Special Function Register 0 -------- \r
+// -------- HMATRIX2_VER : (HMATRIX2 Offset: 0x1fc)  VERSION  Register -------- \r
+#define AT91C_HMATRIX2_VER    (0xF <<  0) // (HMATRIX2)  VERSION  Register\r
+\r
+// *****************************************************************************\r
+//              SOFTWARE API DEFINITION  FOR NESTED vector Interrupt Controller\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_NVIC {\r
+       AT91_REG         Reserved0[1];  // \r
+       AT91_REG         NVIC_ICTR;     // Interrupt Control Type Register\r
+       AT91_REG         Reserved1[2];  // \r
+       AT91_REG         NVIC_STICKCSR;         // SysTick Control and Status Register\r
+       AT91_REG         NVIC_STICKRVR;         // SysTick Reload Value Register\r
+       AT91_REG         NVIC_STICKCVR;         // SysTick Current Value Register\r
+       AT91_REG         NVIC_STICKCALVR;       // SysTick Calibration Value Register\r
+       AT91_REG         Reserved2[56];         // \r
+       AT91_REG         NVIC_ISER[8];  // Set Enable Register\r
+       AT91_REG         Reserved3[24];         // \r
+       AT91_REG         NVIC_ICER[8];  // Clear enable Register\r
+       AT91_REG         Reserved4[24];         // \r
+       AT91_REG         NVIC_ISPR[8];  // Set Pending Register\r
+       AT91_REG         Reserved5[24];         // \r
+       AT91_REG         NVIC_ICPR[8];  // Clear Pending Register\r
+       AT91_REG         Reserved6[24];         // \r
+       AT91_REG         NVIC_ABR[8];   // Active Bit Register\r
+       AT91_REG         Reserved7[56];         // \r
+       AT91_REG         NVIC_IPR[60];  // Interrupt Mask Register\r
+       AT91_REG         Reserved8[516];        // \r
+       AT91_REG         NVIC_CPUID;    // CPUID Base Register\r
+       AT91_REG         NVIC_ICSR;     // Interrupt Control State Register\r
+       AT91_REG         NVIC_VTOFFR;   // Vector Table Offset Register\r
+       AT91_REG         NVIC_AIRCR;    // Application Interrupt/Reset Control Reg\r
+       AT91_REG         NVIC_SCR;      // System Control Register\r
+       AT91_REG         NVIC_CCR;      // Configuration Control Register\r
+       AT91_REG         NVIC_HAND4PR;  // System Handlers 4-7 Priority Register\r
+       AT91_REG         NVIC_HAND8PR;  // System Handlers 8-11 Priority Register\r
+       AT91_REG         NVIC_HAND12PR;         // System Handlers 12-15 Priority Register\r
+       AT91_REG         NVIC_HANDCSR;  // System Handler Control and State Register\r
+       AT91_REG         NVIC_CFSR;     // Configurable Fault Status Register\r
+       AT91_REG         NVIC_HFSR;     // Hard Fault Status Register\r
+       AT91_REG         NVIC_DFSR;     // Debug Fault Status Register\r
+       AT91_REG         NVIC_MMAR;     // Mem Manage Address Register\r
+       AT91_REG         NVIC_BFAR;     // Bus Fault Address Register\r
+       AT91_REG         NVIC_AFSR;     // Auxiliary Fault Status Register\r
+       AT91_REG         NVIC_PFR0;     // Processor Feature register0\r
+       AT91_REG         NVIC_PFR1;     // Processor Feature register1\r
+       AT91_REG         NVIC_DFR0;     // Debug Feature register0\r
+       AT91_REG         NVIC_AFR0;     // Auxiliary Feature register0\r
+       AT91_REG         NVIC_MMFR0;    // Memory Model Feature register0\r
+       AT91_REG         NVIC_MMFR1;    // Memory Model Feature register1\r
+       AT91_REG         NVIC_MMFR2;    // Memory Model Feature register2\r
+       AT91_REG         NVIC_MMFR3;    // Memory Model Feature register3\r
+       AT91_REG         NVIC_ISAR0;    // ISA Feature register0\r
+       AT91_REG         NVIC_ISAR1;    // ISA Feature register1\r
+       AT91_REG         NVIC_ISAR2;    // ISA Feature register2\r
+       AT91_REG         NVIC_ISAR3;    // ISA Feature register3\r
+       AT91_REG         NVIC_ISAR4;    // ISA Feature register4\r
+       AT91_REG         Reserved9[99];         // \r
+       AT91_REG         NVIC_STIR;     // Software Trigger Interrupt Register\r
+       AT91_REG         Reserved10[51];        // \r
+       AT91_REG         NVIC_PID4;     // Peripheral identification register\r
+       AT91_REG         NVIC_PID5;     // Peripheral identification register\r
+       AT91_REG         NVIC_PID6;     // Peripheral identification register\r
+       AT91_REG         NVIC_PID7;     // Peripheral identification register\r
+       AT91_REG         NVIC_PID0;     // Peripheral identification register b7:0\r
+       AT91_REG         NVIC_PID1;     // Peripheral identification register b15:8\r
+       AT91_REG         NVIC_PID2;     // Peripheral identification register b23:16\r
+       AT91_REG         NVIC_PID3;     // Peripheral identification register b31:24\r
+       AT91_REG         NVIC_CID0;     // Component identification register b7:0\r
+       AT91_REG         NVIC_CID1;     // Component identification register b15:8\r
+       AT91_REG         NVIC_CID2;     // Component identification register b23:16\r
+       AT91_REG         NVIC_CID3;     // Component identification register b31:24\r
+} AT91S_NVIC, *AT91PS_NVIC;\r
+#else\r
+#define NVIC_ICTR       (AT91_CAST(AT91_REG *)         0x00000004) // (NVIC_ICTR) Interrupt Control Type Register\r
+#define NVIC_STICKCSR   (AT91_CAST(AT91_REG *)         0x00000010) // (NVIC_STICKCSR) SysTick Control and Status Register\r
+#define NVIC_STICKRVR   (AT91_CAST(AT91_REG *)         0x00000014) // (NVIC_STICKRVR) SysTick Reload Value Register\r
+#define NVIC_STICKCVR   (AT91_CAST(AT91_REG *)         0x00000018) // (NVIC_STICKCVR) SysTick Current Value Register\r
+#define NVIC_STICKCALVR (AT91_CAST(AT91_REG *)         0x0000001C) // (NVIC_STICKCALVR) SysTick Calibration Value Register\r
+#define NVIC_ISER       (AT91_CAST(AT91_REG *)         0x00000100) // (NVIC_ISER) Set Enable Register\r
+#define NVIC_ICER       (AT91_CAST(AT91_REG *)         0x00000180) // (NVIC_ICER) Clear enable Register\r
+#define NVIC_ISPR       (AT91_CAST(AT91_REG *)         0x00000200) // (NVIC_ISPR) Set Pending Register\r
+#define NVIC_ICPR       (AT91_CAST(AT91_REG *)         0x00000280) // (NVIC_ICPR) Clear Pending Register\r
+#define NVIC_IABR       (AT91_CAST(AT91_REG *)         0x00000300) // (NVIC_IABR) Active Bit Register\r
+#define NVIC_IPR        (AT91_CAST(AT91_REG *)         0x00000400) // (NVIC_IPR) Interrupt Mask Register\r
+#define NVIC_CPUID      (AT91_CAST(AT91_REG *)         0x00000D00) // (NVIC_CPUID) CPUID Base Register\r
+#define NVIC_ICSR       (AT91_CAST(AT91_REG *)         0x00000D04) // (NVIC_ICSR) Interrupt Control State Register\r
+#define NVIC_VTOFFR     (AT91_CAST(AT91_REG *)         0x00000D08) // (NVIC_VTOFFR) Vector Table Offset Register\r
+#define NVIC_AIRCR      (AT91_CAST(AT91_REG *)         0x00000D0C) // (NVIC_AIRCR) Application Interrupt/Reset Control Reg\r
+#define NVIC_SCR        (AT91_CAST(AT91_REG *)         0x00000D10) // (NVIC_SCR) System Control Register\r
+#define NVIC_CCR        (AT91_CAST(AT91_REG *)         0x00000D14) // (NVIC_CCR) Configuration Control Register\r
+#define NVIC_HAND4PR    (AT91_CAST(AT91_REG *)         0x00000D18) // (NVIC_HAND4PR) System Handlers 4-7 Priority Register\r
+#define NVIC_HAND8PR    (AT91_CAST(AT91_REG *)         0x00000D1C) // (NVIC_HAND8PR) System Handlers 8-11 Priority Register\r
+#define NVIC_HAND12PR   (AT91_CAST(AT91_REG *)         0x00000D20) // (NVIC_HAND12PR) System Handlers 12-15 Priority Register\r
+#define NVIC_HANDCSR    (AT91_CAST(AT91_REG *)         0x00000D24) // (NVIC_HANDCSR) System Handler Control and State Register\r
+#define NVIC_CFSR       (AT91_CAST(AT91_REG *)         0x00000D28) // (NVIC_CFSR) Configurable Fault Status Register\r
+#define NVIC_HFSR       (AT91_CAST(AT91_REG *)         0x00000D2C) // (NVIC_HFSR) Hard Fault Status Register\r
+#define NVIC_DFSR       (AT91_CAST(AT91_REG *)         0x00000D30) // (NVIC_DFSR) Debug Fault Status Register\r
+#define NVIC_MMAR       (AT91_CAST(AT91_REG *)         0x00000D34) // (NVIC_MMAR) Mem Manage Address Register\r
+#define NVIC_BFAR       (AT91_CAST(AT91_REG *)         0x00000D38) // (NVIC_BFAR) Bus Fault Address Register\r
+#define NVIC_AFSR       (AT91_CAST(AT91_REG *)         0x00000D3C) // (NVIC_AFSR) Auxiliary Fault Status Register\r
+#define NVIC_PFR0       (AT91_CAST(AT91_REG *)         0x00000D40) // (NVIC_PFR0) Processor Feature register0\r
+#define NVIC_PFR1       (AT91_CAST(AT91_REG *)         0x00000D44) // (NVIC_PFR1) Processor Feature register1\r
+#define NVIC_DFR0       (AT91_CAST(AT91_REG *)         0x00000D48) // (NVIC_DFR0) Debug Feature register0\r
+#define NVIC_AFR0       (AT91_CAST(AT91_REG *)         0x00000D4C) // (NVIC_AFR0) Auxiliary Feature register0\r
+#define NVIC_MMFR0      (AT91_CAST(AT91_REG *)         0x00000D50) // (NVIC_MMFR0) Memory Model Feature register0\r
+#define NVIC_MMFR1      (AT91_CAST(AT91_REG *)         0x00000D54) // (NVIC_MMFR1) Memory Model Feature register1\r
+#define NVIC_MMFR2      (AT91_CAST(AT91_REG *)         0x00000D58) // (NVIC_MMFR2) Memory Model Feature register2\r
+#define NVIC_MMFR3      (AT91_CAST(AT91_REG *)         0x00000D5C) // (NVIC_MMFR3) Memory Model Feature register3\r
+#define NVIC_ISAR0      (AT91_CAST(AT91_REG *)         0x00000D60) // (NVIC_ISAR0) ISA Feature register0\r
+#define NVIC_ISAR1      (AT91_CAST(AT91_REG *)         0x00000D64) // (NVIC_ISAR1) ISA Feature register1\r
+#define NVIC_ISAR2      (AT91_CAST(AT91_REG *)         0x00000D68) // (NVIC_ISAR2) ISA Feature register2\r
+#define NVIC_ISAR3      (AT91_CAST(AT91_REG *)         0x00000D6C) // (NVIC_ISAR3) ISA Feature register3\r
+#define NVIC_ISAR4      (AT91_CAST(AT91_REG *)         0x00000D70) // (NVIC_ISAR4) ISA Feature register4\r
+#define NVIC_STIR       (AT91_CAST(AT91_REG *)         0x00000F00) // (NVIC_STIR) Software Trigger Interrupt Register\r
+#define NVIC_PID4       (AT91_CAST(AT91_REG *)         0x00000FD0) // (NVIC_PID4) Peripheral identification register\r
+#define NVIC_PID5       (AT91_CAST(AT91_REG *)         0x00000FD4) // (NVIC_PID5) Peripheral identification register\r
+#define NVIC_PID6       (AT91_CAST(AT91_REG *)         0x00000FD8) // (NVIC_PID6) Peripheral identification register\r
+#define NVIC_PID7       (AT91_CAST(AT91_REG *)         0x00000FDC) // (NVIC_PID7) Peripheral identification register\r
+#define NVIC_PID0       (AT91_CAST(AT91_REG *)         0x00000FE0) // (NVIC_PID0) Peripheral identification register b7:0\r
+#define NVIC_PID1       (AT91_CAST(AT91_REG *)         0x00000FE4) // (NVIC_PID1) Peripheral identification register b15:8\r
+#define NVIC_PID2       (AT91_CAST(AT91_REG *)         0x00000FE8) // (NVIC_PID2) Peripheral identification register b23:16\r
+#define NVIC_PID3       (AT91_CAST(AT91_REG *)         0x00000FEC) // (NVIC_PID3) Peripheral identification register b31:24\r
+#define NVIC_CID0       (AT91_CAST(AT91_REG *)         0x00000FF0) // (NVIC_CID0) Component identification register b7:0\r
+#define NVIC_CID1       (AT91_CAST(AT91_REG *)         0x00000FF4) // (NVIC_CID1) Component identification register b15:8\r
+#define NVIC_CID2       (AT91_CAST(AT91_REG *)         0x00000FF8) // (NVIC_CID2) Component identification register b23:16\r
+#define NVIC_CID3       (AT91_CAST(AT91_REG *)         0x00000FFC) // (NVIC_CID3) Component identification register b31:24\r
+\r
+#endif\r
+// -------- NVIC_ICTR : (NVIC Offset: 0x4) Interrupt Controller Type Register -------- \r
+#define AT91C_NVIC_INTLINESNUM (0xF <<  0) // (NVIC) Total number of interrupt lines\r
+#define        AT91C_NVIC_INTLINESNUM_32                   (0x0) // (NVIC) up to 32 interrupt lines supported\r
+#define        AT91C_NVIC_INTLINESNUM_64                   (0x1) // (NVIC) up to 64 interrupt lines supported\r
+#define        AT91C_NVIC_INTLINESNUM_96                   (0x2) // (NVIC) up to 96 interrupt lines supported\r
+#define        AT91C_NVIC_INTLINESNUM_128                  (0x3) // (NVIC) up to 128 interrupt lines supported\r
+#define        AT91C_NVIC_INTLINESNUM_160                  (0x4) // (NVIC) up to 160 interrupt lines supported\r
+#define        AT91C_NVIC_INTLINESNUM_192                  (0x5) // (NVIC) up to 192 interrupt lines supported\r
+#define        AT91C_NVIC_INTLINESNUM_224                  (0x6) // (NVIC) up to 224 interrupt lines supported\r
+#define        AT91C_NVIC_INTLINESNUM_256                  (0x7) // (NVIC) up to 256 interrupt lines supported\r
+#define        AT91C_NVIC_INTLINESNUM_288                  (0x8) // (NVIC) up to 288 interrupt lines supported\r
+#define        AT91C_NVIC_INTLINESNUM_320                  (0x9) // (NVIC) up to 320 interrupt lines supported\r
+#define        AT91C_NVIC_INTLINESNUM_352                  (0xA) // (NVIC) up to 352 interrupt lines supported\r
+#define        AT91C_NVIC_INTLINESNUM_384                  (0xB) // (NVIC) up to 384 interrupt lines supported\r
+#define        AT91C_NVIC_INTLINESNUM_416                  (0xC) // (NVIC) up to 416 interrupt lines supported\r
+#define        AT91C_NVIC_INTLINESNUM_448                  (0xD) // (NVIC) up to 448 interrupt lines supported\r
+#define        AT91C_NVIC_INTLINESNUM_480                  (0xE) // (NVIC) up to 480 interrupt lines supported\r
+#define        AT91C_NVIC_INTLINESNUM_496                  (0xF) // (NVIC) up to 496 interrupt lines supported)\r
+// -------- NVIC_STICKCSR : (NVIC Offset: 0x10) SysTick Control and Status Register -------- \r
+#define AT91C_NVIC_STICKENABLE (0x1 <<  0) // (NVIC) SysTick counter enable.\r
+#define AT91C_NVIC_STICKINT   (0x1 <<  1) // (NVIC) SysTick interrupt enable.\r
+#define AT91C_NVIC_STICKCLKSOURCE (0x1 <<  2) // (NVIC) Reference clock selection.\r
+#define AT91C_NVIC_STICKCOUNTFLAG (0x1 << 16) // (NVIC) Return 1 if timer counted to 0 since last read.\r
+// -------- NVIC_STICKRVR : (NVIC Offset: 0x14) SysTick Reload Value Register -------- \r
+#define AT91C_NVIC_STICKRELOAD (0xFFFFFF <<  0) // (NVIC) SysTick reload value.\r
+// -------- NVIC_STICKCVR : (NVIC Offset: 0x18) SysTick Current Value Register -------- \r
+#define AT91C_NVIC_STICKCURRENT (0x7FFFFFFF <<  0) // (NVIC) SysTick current value.\r
+// -------- NVIC_STICKCALVR : (NVIC Offset: 0x1c) SysTick Calibration Value Register -------- \r
+#define AT91C_NVIC_STICKTENMS (0xFFFFFF <<  0) // (NVIC) Reload value to use for 10ms timing.\r
+#define AT91C_NVIC_STICKSKEW  (0x1 << 30) // (NVIC) Read as 1 if the calibration value is not exactly 10ms because of clock frequency.\r
+#define AT91C_NVIC_STICKNOREF (0x1 << 31) // (NVIC) Read as 1 if the reference clock is not provided.\r
+// -------- NVIC_IPR : (NVIC Offset: 0x400) Interrupt Priority Registers -------- \r
+#define AT91C_NVIC_PRI_N      (0xFF <<  0) // (NVIC) Priority of interrupt N (0, 4, 8, etc)\r
+#define AT91C_NVIC_PRI_N1     (0xFF <<  8) // (NVIC) Priority of interrupt N+1 (1, 5, 9, etc)\r
+#define AT91C_NVIC_PRI_N2     (0xFF << 16) // (NVIC) Priority of interrupt N+2 (2, 6, 10, etc)\r
+#define AT91C_NVIC_PRI_N3     (0xFF << 24) // (NVIC) Priority of interrupt N+3 (3, 7, 11, etc)\r
+// -------- NVIC_CPUID : (NVIC Offset: 0xd00) CPU ID Base Register -------- \r
+#define AT91C_NVIC_REVISION   (0xF <<  0) // (NVIC) Implementation defined revision number.\r
+#define AT91C_NVIC_PARTNO     (0xFFF <<  4) // (NVIC) Number of processor within family\r
+#define AT91C_NVIC_CONSTANT   (0xF << 16) // (NVIC) Reads as 0xF\r
+#define AT91C_NVIC_VARIANT    (0xF << 20) // (NVIC) Implementation defined variant number.\r
+#define AT91C_NVIC_IMPLEMENTER (0xFF << 24) // (NVIC) Implementer code. ARM is 0x41\r
+// -------- NVIC_ICSR : (NVIC Offset: 0xd04) Interrupt Control State Register -------- \r
+#define AT91C_NVIC_VECTACTIVE (0x1FF <<  0) // (NVIC) Read-only Active ISR number field\r
+#define AT91C_NVIC_RETTOBASE  (0x1 << 11) // (NVIC) Read-only\r
+#define AT91C_NVIC_VECTPENDING (0x1FF << 12) // (NVIC) Read-only Pending ISR number field\r
+#define AT91C_NVIC_ISRPENDING (0x1 << 22) // (NVIC) Read-only Interrupt pending flag.\r
+#define AT91C_NVIC_ISRPREEMPT (0x1 << 23) // (NVIC) Read-only You must only use this at debug time\r
+#define AT91C_NVIC_PENDSTCLR  (0x1 << 25) // (NVIC) Write-only Clear pending SysTick bit\r
+#define AT91C_NVIC_PENDSTSET  (0x1 << 26) // (NVIC) Read/write Set a pending SysTick bit\r
+#define AT91C_NVIC_PENDSVCLR  (0x1 << 27) // (NVIC) Write-only Clear pending pendSV bit\r
+#define AT91C_NVIC_PENDSVSET  (0x1 << 28) // (NVIC) Read/write Set pending pendSV bit\r
+#define AT91C_NVIC_NMIPENDSET (0x1 << 31) // (NVIC) Read/write Set pending NMI\r
+// -------- NVIC_VTOFFR : (NVIC Offset: 0xd08) Vector Table Offset Register -------- \r
+#define AT91C_NVIC_TBLOFF     (0x3FFFFF <<  7) // (NVIC) Vector table base offset field\r
+#define AT91C_NVIC_TBLBASE    (0x1 << 29) // (NVIC) Table base is in Code (0) or RAM (1)\r
+#define        AT91C_NVIC_TBLBASE_CODE                 (0x0 << 29) // (NVIC) Table base is in CODE\r
+#define        AT91C_NVIC_TBLBASE_RAM                  (0x1 << 29) // (NVIC) Table base is in RAM\r
+// -------- NVIC_AIRCR : (NVIC Offset: 0xd0c) Application Interrupt and Reset Control Register -------- \r
+#define AT91C_NVIC_VECTRESET  (0x1 <<  0) // (NVIC) System Reset bit\r
+#define AT91C_NVIC_VECTCLRACTIVE (0x1 <<  1) // (NVIC) Clear active vector bit\r
+#define AT91C_NVIC_SYSRESETREQ (0x1 <<  2) // (NVIC) Causes a signal to be asserted to the outer system that indicates a reset is requested\r
+#define AT91C_NVIC_PRIGROUP   (0x7 <<  8) // (NVIC) Interrupt priority grouping field\r
+#define        AT91C_NVIC_PRIGROUP_0                    (0x0 <<  8) // (NVIC) indicates seven bits of pre-emption priority, one bit of subpriority\r
+#define        AT91C_NVIC_PRIGROUP_1                    (0x1 <<  8) // (NVIC) indicates six bits of pre-emption priority, two bits of subpriority\r
+#define        AT91C_NVIC_PRIGROUP_2                    (0x2 <<  8) // (NVIC) indicates five bits of pre-emption priority, three bits of subpriority\r
+#define        AT91C_NVIC_PRIGROUP_3                    (0x3 <<  8) // (NVIC) indicates four bits of pre-emption priority, four bits of subpriority\r
+#define        AT91C_NVIC_PRIGROUP_4                    (0x4 <<  8) // (NVIC) indicates three bits of pre-emption priority, five bits of subpriority\r
+#define        AT91C_NVIC_PRIGROUP_5                    (0x5 <<  8) // (NVIC) indicates two bits of pre-emption priority, six bits of subpriority\r
+#define        AT91C_NVIC_PRIGROUP_6                    (0x6 <<  8) // (NVIC) indicates one bit of pre-emption priority, seven bits of subpriority\r
+#define        AT91C_NVIC_PRIGROUP_7                    (0x7 <<  8) // (NVIC) indicates no pre-emption priority, eight bits of subpriority\r
+#define AT91C_NVIC_ENDIANESS  (0x1 << 15) // (NVIC) Data endianness bit\r
+#define AT91C_NVIC_VECTKEY    (0xFFFF << 16) // (NVIC) Register key\r
+// -------- NVIC_SCR : (NVIC Offset: 0xd10) System Control Register -------- \r
+#define AT91C_NVIC_SLEEPONEXIT (0x1 <<  1) // (NVIC) Sleep on exit when returning from Handler mode to Thread mode\r
+#define AT91C_NVIC_SLEEPDEEP  (0x1 <<  2) // (NVIC) Sleep deep bit\r
+#define AT91C_NVIC_SEVONPEND  (0x1 <<  4) // (NVIC) When enabled, this causes WFE to wake up when an interrupt moves from inactive to pended\r
+// -------- NVIC_CCR : (NVIC Offset: 0xd14) Configuration Control Register -------- \r
+#define AT91C_NVIC_NONEBASETHRDENA (0x1 <<  0) // (NVIC) When 0, default, It is only possible to enter Thread mode when returning from the last exception\r
+#define AT91C_NVIC_USERSETMPEND (0x1 <<  1) // (NVIC) \r
+#define AT91C_NVIC_UNALIGN_TRP (0x1 <<  3) // (NVIC) Trap for unaligned access\r
+#define AT91C_NVIC_DIV_0_TRP  (0x1 <<  4) // (NVIC) Trap on Divide by 0\r
+#define AT91C_NVIC_BFHFNMIGN  (0x1 <<  8) // (NVIC) \r
+#define AT91C_NVIC_STKALIGN   (0x1 <<  9) // (NVIC) \r
+// -------- NVIC_HAND4PR : (NVIC Offset: 0xd18) System Handlers 4-7 Priority Register -------- \r
+#define AT91C_NVIC_PRI_4      (0xFF <<  0) // (NVIC) \r
+#define AT91C_NVIC_PRI_5      (0xFF <<  8) // (NVIC) \r
+#define AT91C_NVIC_PRI_6      (0xFF << 16) // (NVIC) \r
+#define AT91C_NVIC_PRI_7      (0xFF << 24) // (NVIC) \r
+// -------- NVIC_HAND8PR : (NVIC Offset: 0xd1c) System Handlers 8-11 Priority Register -------- \r
+#define AT91C_NVIC_PRI_8      (0xFF <<  0) // (NVIC) \r
+#define AT91C_NVIC_PRI_9      (0xFF <<  8) // (NVIC) \r
+#define AT91C_NVIC_PRI_10     (0xFF << 16) // (NVIC) \r
+#define AT91C_NVIC_PRI_11     (0xFF << 24) // (NVIC) \r
+// -------- NVIC_HAND12PR : (NVIC Offset: 0xd20) System Handlers 12-15 Priority Register -------- \r
+#define AT91C_NVIC_PRI_12     (0xFF <<  0) // (NVIC) \r
+#define AT91C_NVIC_PRI_13     (0xFF <<  8) // (NVIC) \r
+#define AT91C_NVIC_PRI_14     (0xFF << 16) // (NVIC) \r
+#define AT91C_NVIC_PRI_15     (0xFF << 24) // (NVIC) \r
+// -------- NVIC_HANDCSR : (NVIC Offset: 0xd24) System Handler Control and State Register -------- \r
+#define AT91C_NVIC_MEMFAULTACT (0x1 <<  0) // (NVIC) \r
+#define AT91C_NVIC_BUSFAULTACT (0x1 <<  1) // (NVIC) \r
+#define AT91C_NVIC_USGFAULTACT (0x1 <<  3) // (NVIC) \r
+#define AT91C_NVIC_SVCALLACT  (0x1 <<  7) // (NVIC) \r
+#define AT91C_NVIC_MONITORACT (0x1 <<  8) // (NVIC) \r
+#define AT91C_NVIC_PENDSVACT  (0x1 << 10) // (NVIC) \r
+#define AT91C_NVIC_SYSTICKACT (0x1 << 11) // (NVIC) \r
+#define AT91C_NVIC_USGFAULTPENDED (0x1 << 12) // (NVIC) \r
+#define AT91C_NVIC_MEMFAULTPENDED (0x1 << 13) // (NVIC) \r
+#define AT91C_NVIC_BUSFAULTPENDED (0x1 << 14) // (NVIC) \r
+#define AT91C_NVIC_SVCALLPENDED (0x1 << 15) // (NVIC) \r
+#define AT91C_NVIC_MEMFAULTENA (0x1 << 16) // (NVIC) \r
+#define AT91C_NVIC_BUSFAULTENA (0x1 << 17) // (NVIC) \r
+#define AT91C_NVIC_USGFAULTENA (0x1 << 18) // (NVIC) \r
+// -------- NVIC_CFSR : (NVIC Offset: 0xd28) Configurable Fault Status Registers -------- \r
+#define AT91C_NVIC_MEMMANAGE  (0xFF <<  0) // (NVIC) \r
+#define AT91C_NVIC_BUSFAULT   (0xFF <<  8) // (NVIC) \r
+#define AT91C_NVIC_USAGEFAULT (0xFF << 16) // (NVIC) \r
+// -------- NVIC_BFAR : (NVIC Offset: 0xd38) Bus Fault Address Register -------- \r
+#define AT91C_NVIC_IBUSERR    (0x1 <<  0) // (NVIC) This bit indicates a bus fault on an instruction prefetch\r
+#define AT91C_NVIC_PRECISERR  (0x1 <<  1) // (NVIC) Precise data access error. The BFAR is written with the faulting address\r
+#define AT91C_NVIC_IMPRECISERR (0x1 <<  2) // (NVIC) Imprecise data access error\r
+#define AT91C_NVIC_UNSTKERR   (0x1 <<  3) // (NVIC) This bit indicates a derived bus fault has occurred on exception return\r
+#define AT91C_NVIC_STKERR     (0x1 <<  4) // (NVIC) This bit indicates a derived bus fault has occurred on exception entry\r
+#define AT91C_NVIC_BFARVALID  (0x1 <<  7) // (NVIC) This bit is set if the BFAR register has valid contents\r
+// -------- NVIC_PFR0 : (NVIC Offset: 0xd40) Processor Feature register0 (ID_PFR0) -------- \r
+#define AT91C_NVIC_ID_PFR0_0  (0xF <<  0) // (NVIC) State0 (T-bit == 0)\r
+#define AT91C_NVIC_ID_PRF0_1  (0xF <<  4) // (NVIC) State1 (T-bit == 1)\r
+// -------- NVIC_PFR1 : (NVIC Offset: 0xd44) Processor Feature register1 (ID_PFR1) -------- \r
+#define AT91C_NVIC_ID_PRF1_MODEL (0xF <<  8) // (NVIC) Microcontroller programmer\92s model\r
+// -------- NVIC_DFR0 : (NVIC Offset: 0xd48) Debug Feature register0 (ID_DFR0) -------- \r
+#define AT91C_NVIC_ID_DFR0_MODEL (0xF << 20) // (NVIC) Microcontroller Debug Model \96 memory mapped\r
+// -------- NVIC_MMFR0 : (NVIC Offset: 0xd50) Memory Model Feature register0 (ID_MMFR0) -------- \r
+#define AT91C_NVIC_ID_MMFR0_PMSA (0xF <<  4) // (NVIC) Microcontroller Debug Model \96 memory mapped\r
+#define AT91C_NVIC_ID_MMFR0_CACHE (0xF <<  8) // (NVIC) Microcontroller Debug Model \96 memory mapped\r
+\r
+// *****************************************************************************\r
+//              SOFTWARE API DEFINITION  FOR NESTED vector Interrupt Controller\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_MPU {\r
+       AT91_REG         MPU_TYPE;      // MPU Type Register\r
+       AT91_REG         MPU_CTRL;      // MPU Control Register\r
+       AT91_REG         MPU_REG_NB;    // MPU Region Number Register\r
+       AT91_REG         MPU_REG_BASE_ADDR;     // MPU Region Base Address Register\r
+       AT91_REG         MPU_ATTR_SIZE;         // MPU  Attribute and Size Register\r
+       AT91_REG         MPU_REG_BASE_ADDR1;    // MPU Region Base Address Register alias 1\r
+       AT91_REG         MPU_ATTR_SIZE1;        // MPU  Attribute and Size Register alias 1\r
+       AT91_REG         MPU_REG_BASE_ADDR2;    // MPU Region Base Address Register alias 2\r
+       AT91_REG         MPU_ATTR_SIZE2;        // MPU  Attribute and Size Register alias 2\r
+       AT91_REG         MPU_REG_BASE_ADDR3;    // MPU Region Base Address Register alias 3\r
+       AT91_REG         MPU_ATTR_SIZE3;        // MPU  Attribute and Size Register alias 3\r
+} AT91S_MPU, *AT91PS_MPU;\r
+#else\r
+#define MPU_TYPE        (AT91_CAST(AT91_REG *)         0x00000000) // (MPU_TYPE) MPU Type Register\r
+#define MPU_CTRL        (AT91_CAST(AT91_REG *)         0x00000004) // (MPU_CTRL) MPU Control Register\r
+#define MPU_REG_NB      (AT91_CAST(AT91_REG *)         0x00000008) // (MPU_REG_NB) MPU Region Number Register\r
+#define MPU_REG_BASE_ADDR (AT91_CAST(AT91_REG *)       0x0000000C) // (MPU_REG_BASE_ADDR) MPU Region Base Address Register\r
+#define MPU_ATTR_SIZE   (AT91_CAST(AT91_REG *)         0x00000010) // (MPU_ATTR_SIZE) MPU  Attribute and Size Register\r
+#define MPU_REG_BASE_ADDR1 (AT91_CAST(AT91_REG *)      0x00000014) // (MPU_REG_BASE_ADDR1) MPU Region Base Address Register alias 1\r
+#define MPU_ATTR_SIZE1  (AT91_CAST(AT91_REG *)         0x00000018) // (MPU_ATTR_SIZE1) MPU  Attribute and Size Register alias 1\r
+#define MPU_REG_BASE_ADDR2 (AT91_CAST(AT91_REG *)      0x0000001C) // (MPU_REG_BASE_ADDR2) MPU Region Base Address Register alias 2\r
+#define MPU_ATTR_SIZE2  (AT91_CAST(AT91_REG *)         0x00000020) // (MPU_ATTR_SIZE2) MPU  Attribute and Size Register alias 2\r
+#define MPU_REG_BASE_ADDR3 (AT91_CAST(AT91_REG *)      0x00000024) // (MPU_REG_BASE_ADDR3) MPU Region Base Address Register alias 3\r
+#define MPU_ATTR_SIZE3  (AT91_CAST(AT91_REG *)         0x00000028) // (MPU_ATTR_SIZE3) MPU  Attribute and Size Register alias 3\r
+\r
+#endif\r
+// -------- MPU_TYPE : (MPU Offset: 0x0)  -------- \r
+#define AT91C_MPU_SEPARATE    (0x1 <<  0) // (MPU) \r
+#define AT91C_MPU_DREGION     (0xFF <<  8) // (MPU) \r
+#define AT91C_MPU_IREGION     (0xFF << 16) // (MPU) \r
+// -------- MPU_CTRL : (MPU Offset: 0x4)  -------- \r
+#define AT91C_MPU_ENABLE      (0x1 <<  0) // (MPU) \r
+#define AT91C_MPU_HFNMIENA    (0x1 <<  1) // (MPU) \r
+#define AT91C_MPU_PRIVDEFENA  (0x1 <<  2) // (MPU) \r
+// -------- MPU_REG_NB : (MPU Offset: 0x8)  -------- \r
+#define AT91C_MPU_REGION      (0xFF <<  0) // (MPU) \r
+// -------- MPU_REG_BASE_ADDR : (MPU Offset: 0xc)  -------- \r
+#define AT91C_MPU_REG         (0xF <<  0) // (MPU) \r
+#define AT91C_MPU_VALID       (0x1 <<  4) // (MPU) \r
+#define AT91C_MPU_ADDR        (0x3FFFFFF <<  5) // (MPU) \r
+// -------- MPU_ATTR_SIZE : (MPU Offset: 0x10)  -------- \r
+#define AT91C_MPU_ENA         (0x1 <<  0) // (MPU) \r
+#define AT91C_MPU_SIZE        (0xF <<  1) // (MPU) \r
+#define AT91C_MPU_SRD         (0xFF <<  8) // (MPU) \r
+#define AT91C_MPU_B           (0x1 << 16) // (MPU) \r
+#define AT91C_MPU_C           (0x1 << 17) // (MPU) \r
+#define AT91C_MPU_S           (0x1 << 18) // (MPU) \r
+#define AT91C_MPU_TEX         (0x7 << 19) // (MPU) \r
+#define AT91C_MPU_AP          (0x7 << 24) // (MPU) \r
+#define AT91C_MPU_XN          (0x7 << 28) // (MPU) \r
+\r
+// *****************************************************************************\r
+//              SOFTWARE API DEFINITION  FOR CORTEX_M3 Registers\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_CM3 {\r
+       AT91_REG         CM3_CPUID;     // CPU ID Base Register\r
+       AT91_REG         CM3_ICSR;      // Interrupt Control State Register\r
+       AT91_REG         CM3_VTOR;      // Vector Table Offset Register\r
+       AT91_REG         CM3_AIRCR;     // Application Interrupt and Reset Control Register\r
+       AT91_REG         CM3_SCR;       // System Controller Register\r
+       AT91_REG         CM3_CCR;       // Configuration Control Register\r
+       AT91_REG         CM3_SHPR[3];   // System Handler Priority Register\r
+       AT91_REG         CM3_SHCSR;     // System Handler Control and State Register\r
+} AT91S_CM3, *AT91PS_CM3;\r
+#else\r
+#define CM3_CPUID       (AT91_CAST(AT91_REG *)         0x00000000) // (CM3_CPUID) CPU ID Base Register\r
+#define CM3_ICSR        (AT91_CAST(AT91_REG *)         0x00000004) // (CM3_ICSR) Interrupt Control State Register\r
+#define CM3_VTOR        (AT91_CAST(AT91_REG *)         0x00000008) // (CM3_VTOR) Vector Table Offset Register\r
+#define CM3_AIRCR       (AT91_CAST(AT91_REG *)         0x0000000C) // (CM3_AIRCR) Application Interrupt and Reset Control Register\r
+#define CM3_SCR         (AT91_CAST(AT91_REG *)         0x00000010) // (CM3_SCR) System Controller Register\r
+#define CM3_CCR         (AT91_CAST(AT91_REG *)         0x00000014) // (CM3_CCR) Configuration Control Register\r
+#define CM3_SHPR        (AT91_CAST(AT91_REG *)         0x00000018) // (CM3_SHPR) System Handler Priority Register\r
+#define CM3_SHCSR       (AT91_CAST(AT91_REG *)         0x00000024) // (CM3_SHCSR) System Handler Control and State Register\r
+\r
+#endif\r
+// -------- CM3_CPUID : (CM3 Offset: 0x0)  -------- \r
+// -------- CM3_AIRCR : (CM3 Offset: 0xc)  -------- \r
+#define AT91C_CM3_SYSRESETREQ (0x1 <<  2) // (CM3) A reset is requested by the processor.\r
+// -------- CM3_SCR : (CM3 Offset: 0x10)  -------- \r
+#define AT91C_CM3_SLEEPONEXIT (0x1 <<  1) // (CM3) Sleep on exit when returning from Handler mode to Thread mode. Enables interrupt driven applications to avoid returning to empty main application.\r
+#define AT91C_CM3_SLEEPDEEP   (0x1 <<  2) // (CM3) Sleep deep bit.\r
+#define AT91C_CM3_SEVONPEND   (0x1 <<  4) // (CM3) When enabled, this causes WFE to wake up when an interrupt moves from inactive to pended.\r
+// -------- CM3_SHCSR : (CM3 Offset: 0x24)  -------- \r
+#define AT91C_CM3_SYSTICKACT  (0x1 << 11) // (CM3) Reads as 1 if SysTick is active.\r
+\r
+// *****************************************************************************\r
+//              SOFTWARE API DEFINITION  FOR Peripheral DMA Controller\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_PDC {\r
+       AT91_REG         PDC_RPR;       // Receive Pointer Register\r
+       AT91_REG         PDC_RCR;       // Receive Counter Register\r
+       AT91_REG         PDC_TPR;       // Transmit Pointer Register\r
+       AT91_REG         PDC_TCR;       // Transmit Counter Register\r
+       AT91_REG         PDC_RNPR;      // Receive Next Pointer Register\r
+       AT91_REG         PDC_RNCR;      // Receive Next Counter Register\r
+       AT91_REG         PDC_TNPR;      // Transmit Next Pointer Register\r
+       AT91_REG         PDC_TNCR;      // Transmit Next Counter Register\r
+       AT91_REG         PDC_PTCR;      // PDC Transfer Control Register\r
+       AT91_REG         PDC_PTSR;      // PDC Transfer Status Register\r
+} AT91S_PDC, *AT91PS_PDC;\r
+#else\r
+#define PDC_RPR         (AT91_CAST(AT91_REG *)         0x00000000) // (PDC_RPR) Receive Pointer Register\r
+#define PDC_RCR         (AT91_CAST(AT91_REG *)         0x00000004) // (PDC_RCR) Receive Counter Register\r
+#define PDC_TPR         (AT91_CAST(AT91_REG *)         0x00000008) // (PDC_TPR) Transmit Pointer Register\r
+#define PDC_TCR         (AT91_CAST(AT91_REG *)         0x0000000C) // (PDC_TCR) Transmit Counter Register\r
+#define PDC_RNPR        (AT91_CAST(AT91_REG *)         0x00000010) // (PDC_RNPR) Receive Next Pointer Register\r
+#define PDC_RNCR        (AT91_CAST(AT91_REG *)         0x00000014) // (PDC_RNCR) Receive Next Counter Register\r
+#define PDC_TNPR        (AT91_CAST(AT91_REG *)         0x00000018) // (PDC_TNPR) Transmit Next Pointer Register\r
+#define PDC_TNCR        (AT91_CAST(AT91_REG *)         0x0000001C) // (PDC_TNCR) Transmit Next Counter Register\r
+#define PDC_PTCR        (AT91_CAST(AT91_REG *)         0x00000020) // (PDC_PTCR) PDC Transfer Control Register\r
+#define PDC_PTSR        (AT91_CAST(AT91_REG *)         0x00000024) // (PDC_PTSR) PDC Transfer Status Register\r
+\r
+#endif\r
+// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- \r
+#define AT91C_PDC_RXTEN       (0x1 <<  0) // (PDC) Receiver Transfer Enable\r
+#define AT91C_PDC_RXTDIS      (0x1 <<  1) // (PDC) Receiver Transfer Disable\r
+#define AT91C_PDC_TXTEN       (0x1 <<  8) // (PDC) Transmitter Transfer Enable\r
+#define AT91C_PDC_TXTDIS      (0x1 <<  9) // (PDC) Transmitter Transfer Disable\r
+// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- \r
+\r
+// *****************************************************************************\r
+//              SOFTWARE API DEFINITION  FOR Debug Unit\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_DBGU {\r
+       AT91_REG         DBGU_CR;       // Control Register\r
+       AT91_REG         DBGU_MR;       // Mode Register\r
+       AT91_REG         DBGU_IER;      // Interrupt Enable Register\r
+       AT91_REG         DBGU_IDR;      // Interrupt Disable Register\r
+       AT91_REG         DBGU_IMR;      // Interrupt Mask Register\r
+       AT91_REG         DBGU_CSR;      // Channel Status Register\r
+       AT91_REG         DBGU_RHR;      // Receiver Holding Register\r
+       AT91_REG         DBGU_THR;      // Transmitter Holding Register\r
+       AT91_REG         DBGU_BRGR;     // Baud Rate Generator Register\r
+       AT91_REG         Reserved0[9];  // \r
+       AT91_REG         DBGU_FNTR;     // Force NTRST Register\r
+       AT91_REG         Reserved1[40];         // \r
+       AT91_REG         DBGU_ADDRSIZE;         // DBGU ADDRSIZE REGISTER \r
+       AT91_REG         DBGU_IPNAME1;  // DBGU IPNAME1 REGISTER \r
+       AT91_REG         DBGU_IPNAME2;  // DBGU IPNAME2 REGISTER \r
+       AT91_REG         DBGU_FEATURES;         // DBGU FEATURES REGISTER \r
+       AT91_REG         DBGU_VER;      // DBGU VERSION REGISTER \r
+       AT91_REG         DBGU_RPR;      // Receive Pointer Register\r
+       AT91_REG         DBGU_RCR;      // Receive Counter Register\r
+       AT91_REG         DBGU_TPR;      // Transmit Pointer Register\r
+       AT91_REG         DBGU_TCR;      // Transmit Counter Register\r
+       AT91_REG         DBGU_RNPR;     // Receive Next Pointer Register\r
+       AT91_REG         DBGU_RNCR;     // Receive Next Counter Register\r
+       AT91_REG         DBGU_TNPR;     // Transmit Next Pointer Register\r
+       AT91_REG         DBGU_TNCR;     // Transmit Next Counter Register\r
+       AT91_REG         DBGU_PTCR;     // PDC Transfer Control Register\r
+       AT91_REG         DBGU_PTSR;     // PDC Transfer Status Register\r
+       AT91_REG         Reserved2[6];  // \r
+       AT91_REG         DBGU_CIDR;     // Chip ID Register\r
+       AT91_REG         DBGU_EXID;     // Chip ID Extension Register\r
+} AT91S_DBGU, *AT91PS_DBGU;\r
+#else\r
+#define DBGU_CR         (AT91_CAST(AT91_REG *)         0x00000000) // (DBGU_CR) Control Register\r
+#define DBGU_MR         (AT91_CAST(AT91_REG *)         0x00000004) // (DBGU_MR) Mode Register\r
+#define DBGU_IER        (AT91_CAST(AT91_REG *)         0x00000008) // (DBGU_IER) Interrupt Enable Register\r
+#define DBGU_IDR        (AT91_CAST(AT91_REG *)         0x0000000C) // (DBGU_IDR) Interrupt Disable Register\r
+#define DBGU_IMR        (AT91_CAST(AT91_REG *)         0x00000010) // (DBGU_IMR) Interrupt Mask Register\r
+#define DBGU_CSR        (AT91_CAST(AT91_REG *)         0x00000014) // (DBGU_CSR) Channel Status Register\r
+#define DBGU_RHR        (AT91_CAST(AT91_REG *)         0x00000018) // (DBGU_RHR) Receiver Holding Register\r
+#define DBGU_THR        (AT91_CAST(AT91_REG *)         0x0000001C) // (DBGU_THR) Transmitter Holding Register\r
+#define DBGU_BRGR       (AT91_CAST(AT91_REG *)         0x00000020) // (DBGU_BRGR) Baud Rate Generator Register\r
+#define DBGU_FNTR       (AT91_CAST(AT91_REG *)         0x00000048) // (DBGU_FNTR) Force NTRST Register\r
+#define DBGU_ADDRSIZE   (AT91_CAST(AT91_REG *)         0x000000EC) // (DBGU_ADDRSIZE) DBGU ADDRSIZE REGISTER \r
+#define DBGU_IPNAME1    (AT91_CAST(AT91_REG *)         0x000000F0) // (DBGU_IPNAME1) DBGU IPNAME1 REGISTER \r
+#define DBGU_IPNAME2    (AT91_CAST(AT91_REG *)         0x000000F4) // (DBGU_IPNAME2) DBGU IPNAME2 REGISTER \r
+#define DBGU_FEATURES   (AT91_CAST(AT91_REG *)         0x000000F8) // (DBGU_FEATURES) DBGU FEATURES REGISTER \r
+#define DBGU_VER        (AT91_CAST(AT91_REG *)         0x000000FC) // (DBGU_VER) DBGU VERSION REGISTER \r
+#define DBGU_CIDR       (AT91_CAST(AT91_REG *)         0x00000140) // (DBGU_CIDR) Chip ID Register\r
+#define DBGU_EXID       (AT91_CAST(AT91_REG *)         0x00000144) // (DBGU_EXID) Chip ID Extension Register\r
+\r
+#endif\r
+// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- \r
+#define AT91C_US_RSTRX        (0x1 <<  2) // (DBGU) Reset Receiver\r
+#define AT91C_US_RSTTX        (0x1 <<  3) // (DBGU) Reset Transmitter\r
+#define AT91C_US_RXEN         (0x1 <<  4) // (DBGU) Receiver Enable\r
+#define AT91C_US_RXDIS        (0x1 <<  5) // (DBGU) Receiver Disable\r
+#define AT91C_US_TXEN         (0x1 <<  6) // (DBGU) Transmitter Enable\r
+#define AT91C_US_TXDIS        (0x1 <<  7) // (DBGU) Transmitter Disable\r
+#define AT91C_US_RSTSTA       (0x1 <<  8) // (DBGU) Reset Status Bits\r
+// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- \r
+#define AT91C_US_PAR          (0x7 <<  9) // (DBGU) Parity type\r
+#define        AT91C_US_PAR_EVEN                 (0x0 <<  9) // (DBGU) Even Parity\r
+#define        AT91C_US_PAR_ODD                  (0x1 <<  9) // (DBGU) Odd Parity\r
+#define        AT91C_US_PAR_SPACE                (0x2 <<  9) // (DBGU) Parity forced to 0 (Space)\r
+#define        AT91C_US_PAR_MARK                 (0x3 <<  9) // (DBGU) Parity forced to 1 (Mark)\r
+#define        AT91C_US_PAR_NONE                 (0x4 <<  9) // (DBGU) No Parity\r
+#define        AT91C_US_PAR_MULTI_DROP           (0x6 <<  9) // (DBGU) Multi-drop mode\r
+#define AT91C_US_CHMODE       (0x3 << 14) // (DBGU) Channel Mode\r
+#define        AT91C_US_CHMODE_NORMAL               (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.\r
+#define        AT91C_US_CHMODE_AUTO                 (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.\r
+#define        AT91C_US_CHMODE_LOCAL                (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.\r
+#define        AT91C_US_CHMODE_REMOTE               (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.\r
+// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- \r
+#define AT91C_US_RXRDY        (0x1 <<  0) // (DBGU) RXRDY Interrupt\r
+#define AT91C_US_TXRDY        (0x1 <<  1) // (DBGU) TXRDY Interrupt\r
+#define AT91C_US_ENDRX        (0x1 <<  3) // (DBGU) End of Receive Transfer Interrupt\r
+#define AT91C_US_ENDTX        (0x1 <<  4) // (DBGU) End of Transmit Interrupt\r
+#define AT91C_US_OVRE         (0x1 <<  5) // (DBGU) Overrun Interrupt\r
+#define AT91C_US_FRAME        (0x1 <<  6) // (DBGU) Framing Error Interrupt\r
+#define AT91C_US_PARE         (0x1 <<  7) // (DBGU) Parity Error Interrupt\r
+#define AT91C_US_TXEMPTY      (0x1 <<  9) // (DBGU) TXEMPTY Interrupt\r
+#define AT91C_US_TXBUFE       (0x1 << 11) // (DBGU) TXBUFE Interrupt\r
+#define AT91C_US_RXBUFF       (0x1 << 12) // (DBGU) RXBUFF Interrupt\r
+#define AT91C_US_COMM_TX      (0x1 << 30) // (DBGU) COMM_TX Interrupt\r
+#define AT91C_US_COMM_RX      (0x1 << 31) // (DBGU) COMM_RX Interrupt\r
+// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- \r
+// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- \r
+// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- \r
+// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- \r
+#define AT91C_US_FORCE_NTRST  (0x1 <<  0) // (DBGU) Force NTRST in JTAG\r
+\r
+// *****************************************************************************\r
+//              SOFTWARE API DEFINITION  FOR Parallel Input Output Controler\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_PIO {\r
+       AT91_REG         PIO_PER;       // PIO Enable Register\r
+       AT91_REG         PIO_PDR;       // PIO Disable Register\r
+       AT91_REG         PIO_PSR;       // PIO Status Register\r
+       AT91_REG         Reserved0[1];  // \r
+       AT91_REG         PIO_OER;       // Output Enable Register\r
+       AT91_REG         PIO_ODR;       // Output Disable Registerr\r
+       AT91_REG         PIO_OSR;       // Output Status Register\r
+       AT91_REG         Reserved1[1];  // \r
+       AT91_REG         PIO_IFER;      // Input Filter Enable Register\r
+       AT91_REG         PIO_IFDR;      // Input Filter Disable Register\r
+       AT91_REG         PIO_IFSR;      // Input Filter Status Register\r
+       AT91_REG         Reserved2[1];  // \r
+       AT91_REG         PIO_SODR;      // Set Output Data Register\r
+       AT91_REG         PIO_CODR;      // Clear Output Data Register\r
+       AT91_REG         PIO_ODSR;      // Output Data Status Register\r
+       AT91_REG         PIO_PDSR;      // Pin Data Status Register\r
+       AT91_REG         PIO_IER;       // Interrupt Enable Register\r
+       AT91_REG         PIO_IDR;       // Interrupt Disable Register\r
+       AT91_REG         PIO_IMR;       // Interrupt Mask Register\r
+       AT91_REG         PIO_ISR;       // Interrupt Status Register\r
+       AT91_REG         PIO_MDER;      // Multi-driver Enable Register\r
+       AT91_REG         PIO_MDDR;      // Multi-driver Disable Register\r
+       AT91_REG         PIO_MDSR;      // Multi-driver Status Register\r
+       AT91_REG         Reserved3[1];  // \r
+       AT91_REG         PIO_PPUDR;     // Pull-up Disable Register\r
+       AT91_REG         PIO_PPUER;     // Pull-up Enable Register\r
+       AT91_REG         PIO_PPUSR;     // Pull-up Status Register\r
+       AT91_REG         Reserved4[1];  // \r
+       AT91_REG         PIO_ABSR;      // Peripheral AB Select Register\r
+       AT91_REG         Reserved5[3];  // \r
+       AT91_REG         PIO_SCIFSR;    // System Clock Glitch Input Filter Select Register\r
+       AT91_REG         PIO_DIFSR;     // Debouncing Input Filter Select Register\r
+       AT91_REG         PIO_IFDGSR;    // Glitch or Debouncing Input Filter Clock Selection Status Register\r
+       AT91_REG         PIO_SCDR;      // Slow Clock Divider Debouncing Register\r
+       AT91_REG         Reserved6[4];  // \r
+       AT91_REG         PIO_OWER;      // Output Write Enable Register\r
+       AT91_REG         PIO_OWDR;      // Output Write Disable Register\r
+       AT91_REG         PIO_OWSR;      // Output Write Status Register\r
+       AT91_REG         Reserved7[1];  // \r
+       AT91_REG         PIO_AIMER;     // Additional Interrupt Modes Enable Register\r
+       AT91_REG         PIO_AIMDR;     // Additional Interrupt Modes Disables Register\r
+       AT91_REG         PIO_AIMMR;     // Additional Interrupt Modes Mask Register\r
+       AT91_REG         Reserved8[1];  // \r
+       AT91_REG         PIO_ESR;       // Edge Select Register\r
+       AT91_REG         PIO_LSR;       // Level Select Register\r
+       AT91_REG         PIO_ELSR;      // Edge/Level Status Register\r
+       AT91_REG         Reserved9[1];  // \r
+       AT91_REG         PIO_FELLSR;    // Falling Edge/Low Level Select Register\r
+       AT91_REG         PIO_REHLSR;    // Rising Edge/ High Level Select Register\r
+       AT91_REG         PIO_FRLHSR;    // Fall/Rise - Low/High Status Register\r
+       AT91_REG         Reserved10[1];         // \r
+       AT91_REG         PIO_LOCKSR;    // Lock Status Register\r
+       AT91_REG         Reserved11[6];         // \r
+       AT91_REG         PIO_VER;       // PIO VERSION REGISTER \r
+       AT91_REG         Reserved12[8];         // \r
+       AT91_REG         PIO_KER;       // Keypad Controller Enable Register\r
+       AT91_REG         PIO_KRCR;      // Keypad Controller Row Column Register\r
+       AT91_REG         PIO_KDR;       // Keypad Controller Debouncing Register\r
+       AT91_REG         Reserved13[1];         // \r
+       AT91_REG         PIO_KIER;      // Keypad Controller Interrupt Enable Register\r
+       AT91_REG         PIO_KIDR;      // Keypad Controller Interrupt Disable Register\r
+       AT91_REG         PIO_KIMR;      // Keypad Controller Interrupt Mask Register\r
+       AT91_REG         PIO_KSR;       // Keypad Controller Status Register\r
+       AT91_REG         PIO_KKPR;      // Keypad Controller Key Press Register\r
+       AT91_REG         PIO_KKRR;      // Keypad Controller Key Release Register\r
+} AT91S_PIO, *AT91PS_PIO;\r
+#else\r
+#define PIO_PER         (AT91_CAST(AT91_REG *)         0x00000000) // (PIO_PER) PIO Enable Register\r
+#define PIO_PDR         (AT91_CAST(AT91_REG *)         0x00000004) // (PIO_PDR) PIO Disable Register\r
+#define PIO_PSR         (AT91_CAST(AT91_REG *)         0x00000008) // (PIO_PSR) PIO Status Register\r
+#define PIO_OER         (AT91_CAST(AT91_REG *)         0x00000010) // (PIO_OER) Output Enable Register\r
+#define PIO_ODR         (AT91_CAST(AT91_REG *)         0x00000014) // (PIO_ODR) Output Disable Registerr\r
+#define PIO_OSR         (AT91_CAST(AT91_REG *)         0x00000018) // (PIO_OSR) Output Status Register\r
+#define PIO_IFER        (AT91_CAST(AT91_REG *)         0x00000020) // (PIO_IFER) Input Filter Enable Register\r
+#define PIO_IFDR        (AT91_CAST(AT91_REG *)         0x00000024) // (PIO_IFDR) Input Filter Disable Register\r
+#define PIO_IFSR        (AT91_CAST(AT91_REG *)         0x00000028) // (PIO_IFSR) Input Filter Status Register\r
+#define PIO_SODR        (AT91_CAST(AT91_REG *)         0x00000030) // (PIO_SODR) Set Output Data Register\r
+#define PIO_CODR        (AT91_CAST(AT91_REG *)         0x00000034) // (PIO_CODR) Clear Output Data Register\r
+#define PIO_ODSR        (AT91_CAST(AT91_REG *)         0x00000038) // (PIO_ODSR) Output Data Status Register\r
+#define PIO_PDSR        (AT91_CAST(AT91_REG *)         0x0000003C) // (PIO_PDSR) Pin Data Status Register\r
+#define PIO_IER         (AT91_CAST(AT91_REG *)         0x00000040) // (PIO_IER) Interrupt Enable Register\r
+#define PIO_IDR         (AT91_CAST(AT91_REG *)         0x00000044) // (PIO_IDR) Interrupt Disable Register\r
+#define PIO_IMR         (AT91_CAST(AT91_REG *)         0x00000048) // (PIO_IMR) Interrupt Mask Register\r
+#define PIO_ISR         (AT91_CAST(AT91_REG *)         0x0000004C) // (PIO_ISR) Interrupt Status Register\r
+#define PIO_MDER        (AT91_CAST(AT91_REG *)         0x00000050) // (PIO_MDER) Multi-driver Enable Register\r
+#define PIO_MDDR        (AT91_CAST(AT91_REG *)         0x00000054) // (PIO_MDDR) Multi-driver Disable Register\r
+#define PIO_MDSR        (AT91_CAST(AT91_REG *)         0x00000058) // (PIO_MDSR) Multi-driver Status Register\r
+#define PIO_PPUDR       (AT91_CAST(AT91_REG *)         0x00000060) // (PIO_PPUDR) Pull-up Disable Register\r
+#define PIO_PPUER       (AT91_CAST(AT91_REG *)         0x00000064) // (PIO_PPUER) Pull-up Enable Register\r
+#define PIO_PPUSR       (AT91_CAST(AT91_REG *)         0x00000068) // (PIO_PPUSR) Pull-up Status Register\r
+#define PIO_ABSR        (AT91_CAST(AT91_REG *)         0x00000070) // (PIO_ABSR) Peripheral AB Select Register\r
+#define PIO_SCIFSR      (AT91_CAST(AT91_REG *)         0x00000080) // (PIO_SCIFSR) System Clock Glitch Input Filter Select Register\r
+#define PIO_DIFSR       (AT91_CAST(AT91_REG *)         0x00000084) // (PIO_DIFSR) Debouncing Input Filter Select Register\r
+#define PIO_IFDGSR      (AT91_CAST(AT91_REG *)         0x00000088) // (PIO_IFDGSR) Glitch or Debouncing Input Filter Clock Selection Status Register\r
+#define PIO_SCDR        (AT91_CAST(AT91_REG *)         0x0000008C) // (PIO_SCDR) Slow Clock Divider Debouncing Register\r
+#define PIO_OWER        (AT91_CAST(AT91_REG *)         0x000000A0) // (PIO_OWER) Output Write Enable Register\r
+#define PIO_OWDR        (AT91_CAST(AT91_REG *)         0x000000A4) // (PIO_OWDR) Output Write Disable Register\r
+#define PIO_OWSR        (AT91_CAST(AT91_REG *)         0x000000A8) // (PIO_OWSR) Output Write Status Register\r
+#define PIO_AIMER       (AT91_CAST(AT91_REG *)         0x000000B0) // (PIO_AIMER) Additional Interrupt Modes Enable Register\r
+#define PIO_AIMDR       (AT91_CAST(AT91_REG *)         0x000000B4) // (PIO_AIMDR) Additional Interrupt Modes Disables Register\r
+#define PIO_AIMMR       (AT91_CAST(AT91_REG *)         0x000000B8) // (PIO_AIMMR) Additional Interrupt Modes Mask Register\r
+#define PIO_ESR         (AT91_CAST(AT91_REG *)         0x000000C0) // (PIO_ESR) Edge Select Register\r
+#define PIO_LSR         (AT91_CAST(AT91_REG *)         0x000000C4) // (PIO_LSR) Level Select Register\r
+#define PIO_ELSR        (AT91_CAST(AT91_REG *)         0x000000C8) // (PIO_ELSR) Edge/Level Status Register\r
+#define PIO_FELLSR      (AT91_CAST(AT91_REG *)         0x000000D0) // (PIO_FELLSR) Falling Edge/Low Level Select Register\r
+#define PIO_REHLSR      (AT91_CAST(AT91_REG *)         0x000000D4) // (PIO_REHLSR) Rising Edge/ High Level Select Register\r
+#define PIO_FRLHSR      (AT91_CAST(AT91_REG *)         0x000000D8) // (PIO_FRLHSR) Fall/Rise - Low/High Status Register\r
+#define PIO_LOCKSR      (AT91_CAST(AT91_REG *)         0x000000E0) // (PIO_LOCKSR) Lock Status Register\r
+#define PIO_VER         (AT91_CAST(AT91_REG *)         0x000000FC) // (PIO_VER) PIO VERSION REGISTER \r
+#define PIO_KER         (AT91_CAST(AT91_REG *)         0x00000120) // (PIO_KER) Keypad Controller Enable Register\r
+#define PIO_KRCR        (AT91_CAST(AT91_REG *)         0x00000124) // (PIO_KRCR) Keypad Controller Row Column Register\r
+#define PIO_KDR         (AT91_CAST(AT91_REG *)         0x00000128) // (PIO_KDR) Keypad Controller Debouncing Register\r
+#define PIO_KIER        (AT91_CAST(AT91_REG *)         0x00000130) // (PIO_KIER) Keypad Controller Interrupt Enable Register\r
+#define PIO_KIDR        (AT91_CAST(AT91_REG *)         0x00000134) // (PIO_KIDR) Keypad Controller Interrupt Disable Register\r
+#define PIO_KIMR        (AT91_CAST(AT91_REG *)         0x00000138) // (PIO_KIMR) Keypad Controller Interrupt Mask Register\r
+#define PIO_KSR         (AT91_CAST(AT91_REG *)         0x0000013C) // (PIO_KSR) Keypad Controller Status Register\r
+#define PIO_KKPR        (AT91_CAST(AT91_REG *)         0x00000140) // (PIO_KKPR) Keypad Controller Key Press Register\r
+#define PIO_KKRR        (AT91_CAST(AT91_REG *)         0x00000144) // (PIO_KKRR) Keypad Controller Key Release Register\r
+\r
+#endif\r
+// -------- PIO_KER : (PIO Offset: 0x120) Keypad Controller Enable Register -------- \r
+#define AT91C_PIO_KCE         (0x1 <<  0) // (PIO) Keypad Controller Enable\r
+// -------- PIO_KRCR : (PIO Offset: 0x124) Keypad Controller Row Column Register -------- \r
+#define AT91C_PIO_NBR         (0x7 <<  0) // (PIO) Number of Columns of the Keypad Matrix\r
+#define AT91C_PIO_NBC         (0x7 <<  8) // (PIO) Number of Rows of the Keypad Matrix\r
+// -------- PIO_KDR : (PIO Offset: 0x128) Keypad Controller Debouncing Register -------- \r
+#define AT91C_PIO_DBC         (0x3FF <<  0) // (PIO) Debouncing Value\r
+// -------- PIO_KIER : (PIO Offset: 0x130) Keypad Controller Interrupt Enable Register -------- \r
+#define AT91C_PIO_KPR         (0x1 <<  0) // (PIO) Key Press Interrupt Enable\r
+#define AT91C_PIO_KRL         (0x1 <<  1) // (PIO) Key Release Interrupt Enable\r
+// -------- PIO_KIDR : (PIO Offset: 0x134) Keypad Controller Interrupt Disable Register -------- \r
+// -------- PIO_KIMR : (PIO Offset: 0x138) Keypad Controller Interrupt Mask Register -------- \r
+// -------- PIO_KSR : (PIO Offset: 0x13c) Keypad Controller Status Register -------- \r
+#define AT91C_PIO_NBKPR       (0x3 <<  8) // (PIO) Number of Simultaneous Key Presses\r
+#define AT91C_PIO_NBKRL       (0x3 << 16) // (PIO) Number of Simultaneous Key Releases\r
+// -------- PIO_KKPR : (PIO Offset: 0x140) Keypad Controller Key Press Register -------- \r
+#define AT91C_KEY0ROW         (0x7 <<  0) // (PIO) Row index of the first detected Key Press\r
+#define AT91C_KEY0COL         (0x7 <<  4) // (PIO) Column index of the first detected Key Press\r
+#define AT91C_KEY1ROW         (0x7 <<  8) // (PIO) Row index of the second detected Key Press\r
+#define AT91C_KEY1COL         (0x7 << 12) // (PIO) Column index of the second detected Key Press\r
+#define AT91C_KEY2ROW         (0x7 << 16) // (PIO) Row index of the third detected Key Press\r
+#define AT91C_KEY2COL         (0x7 << 20) // (PIO) Column index of the third detected Key Press\r
+#define AT91C_KEY3ROW         (0x7 << 24) // (PIO) Row index of the fourth detected Key Press\r
+#define AT91C_KEY3COL         (0x7 << 28) // (PIO) Column index of the fourth detected Key Press\r
+// -------- PIO_KKRR : (PIO Offset: 0x144) Keypad Controller Key Release Register -------- \r
+\r
+// *****************************************************************************\r
+//              SOFTWARE API DEFINITION  FOR Power Management Controler\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_PMC {\r
+       AT91_REG         PMC_SCER;      // System Clock Enable Register\r
+       AT91_REG         PMC_SCDR;      // System Clock Disable Register\r
+       AT91_REG         PMC_SCSR;      // System Clock Status Register\r
+       AT91_REG         Reserved0[1];  // \r
+       AT91_REG         PMC_PCER;      // Peripheral Clock Enable Register\r
+       AT91_REG         PMC_PCDR;      // Peripheral Clock Disable Register\r
+       AT91_REG         PMC_PCSR;      // Peripheral Clock Status Register\r
+       AT91_REG         PMC_UCKR;      // UTMI Clock Configuration Register\r
+       AT91_REG         PMC_MOR;       // Main Oscillator Register\r
+       AT91_REG         PMC_MCFR;      // Main Clock  Frequency Register\r
+       AT91_REG         PMC_PLLAR;     // PLL Register\r
+       AT91_REG         Reserved1[1];  // \r
+       AT91_REG         PMC_MCKR;      // Master Clock Register\r
+       AT91_REG         Reserved2[3];  // \r
+       AT91_REG         PMC_PCKR[8];   // Programmable Clock Register\r
+       AT91_REG         PMC_IER;       // Interrupt Enable Register\r
+       AT91_REG         PMC_IDR;       // Interrupt Disable Register\r
+       AT91_REG         PMC_SR;        // Status Register\r
+       AT91_REG         PMC_IMR;       // Interrupt Mask Register\r
+       AT91_REG         PMC_FSMR;      // Fast Startup Mode Register\r
+       AT91_REG         PMC_FSPR;      // Fast Startup Polarity Register\r
+       AT91_REG         PMC_FOCR;      // Fault Output Clear Register\r
+       AT91_REG         Reserved3[28];         // \r
+       AT91_REG         PMC_ADDRSIZE;  // PMC ADDRSIZE REGISTER \r
+       AT91_REG         PMC_IPNAME1;   // PMC IPNAME1 REGISTER \r
+       AT91_REG         PMC_IPNAME2;   // PMC IPNAME2 REGISTER \r
+       AT91_REG         PMC_FEATURES;  // PMC FEATURES REGISTER \r
+       AT91_REG         PMC_VER;       // APMC VERSION REGISTER\r
+} AT91S_PMC, *AT91PS_PMC;\r
+#else\r
+#define PMC_SCER        (AT91_CAST(AT91_REG *)         0x00000000) // (PMC_SCER) System Clock Enable Register\r
+#define PMC_SCDR        (AT91_CAST(AT91_REG *)         0x00000004) // (PMC_SCDR) System Clock Disable Register\r
+#define PMC_SCSR        (AT91_CAST(AT91_REG *)         0x00000008) // (PMC_SCSR) System Clock Status Register\r
+#define PMC_PCER        (AT91_CAST(AT91_REG *)         0x00000010) // (PMC_PCER) Peripheral Clock Enable Register\r
+#define PMC_PCDR        (AT91_CAST(AT91_REG *)         0x00000014) // (PMC_PCDR) Peripheral Clock Disable Register\r
+#define PMC_PCSR        (AT91_CAST(AT91_REG *)         0x00000018) // (PMC_PCSR) Peripheral Clock Status Register\r
+#define CKGR_UCKR       (AT91_CAST(AT91_REG *)         0x0000001C) // (CKGR_UCKR) UTMI Clock Configuration Register\r
+#define CKGR_MOR        (AT91_CAST(AT91_REG *)         0x00000020) // (CKGR_MOR) Main Oscillator Register\r
+#define CKGR_MCFR       (AT91_CAST(AT91_REG *)         0x00000024) // (CKGR_MCFR) Main Clock  Frequency Register\r
+#define CKGR_PLLAR      (AT91_CAST(AT91_REG *)         0x00000028) // (CKGR_PLLAR) PLL Register\r
+#define PMC_MCKR        (AT91_CAST(AT91_REG *)         0x00000030) // (PMC_MCKR) Master Clock Register\r
+#define PMC_PCKR        (AT91_CAST(AT91_REG *)         0x00000040) // (PMC_PCKR) Programmable Clock Register\r
+#define PMC_IER         (AT91_CAST(AT91_REG *)         0x00000060) // (PMC_IER) Interrupt Enable Register\r
+#define PMC_IDR         (AT91_CAST(AT91_REG *)         0x00000064) // (PMC_IDR) Interrupt Disable Register\r
+#define PMC_SR          (AT91_CAST(AT91_REG *)         0x00000068) // (PMC_SR) Status Register\r
+#define PMC_IMR         (AT91_CAST(AT91_REG *)         0x0000006C) // (PMC_IMR) Interrupt Mask Register\r
+#define PMC_FSMR        (AT91_CAST(AT91_REG *)         0x00000070) // (PMC_FSMR) Fast Startup Mode Register\r
+#define PMC_FSPR        (AT91_CAST(AT91_REG *)         0x00000074) // (PMC_FSPR) Fast Startup Polarity Register\r
+#define PMC_FOCR        (AT91_CAST(AT91_REG *)         0x00000078) // (PMC_FOCR) Fault Output Clear Register\r
+#define PMC_ADDRSIZE    (AT91_CAST(AT91_REG *)         0x000000EC) // (PMC_ADDRSIZE) PMC ADDRSIZE REGISTER \r
+#define PMC_IPNAME1     (AT91_CAST(AT91_REG *)         0x000000F0) // (PMC_IPNAME1) PMC IPNAME1 REGISTER \r
+#define PMC_IPNAME2     (AT91_CAST(AT91_REG *)         0x000000F4) // (PMC_IPNAME2) PMC IPNAME2 REGISTER \r
+#define PMC_FEATURES    (AT91_CAST(AT91_REG *)         0x000000F8) // (PMC_FEATURES) PMC FEATURES REGISTER \r
+#define PMC_VER         (AT91_CAST(AT91_REG *)         0x000000FC) // (PMC_VER) APMC VERSION REGISTER\r
+\r
+#endif\r
+// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- \r
+#define AT91C_PMC_PCK         (0x1 <<  0) // (PMC) Processor Clock\r
+#define AT91C_PMC_PCK0        (0x1 <<  8) // (PMC) Programmable Clock Output\r
+#define AT91C_PMC_PCK1        (0x1 <<  9) // (PMC) Programmable Clock Output\r
+#define AT91C_PMC_PCK2        (0x1 << 10) // (PMC) Programmable Clock Output\r
+// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- \r
+// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- \r
+// -------- CKGR_UCKR : (PMC Offset: 0x1c) UTMI Clock Configuration Register -------- \r
+#define AT91C_CKGR_UPLLEN     (0x1 << 16) // (PMC) UTMI PLL Enable\r
+#define        AT91C_CKGR_UPLLEN_DISABLED             (0x0 << 16) // (PMC) The UTMI PLL is disabled\r
+#define        AT91C_CKGR_UPLLEN_ENABLED              (0x1 << 16) // (PMC) The UTMI PLL is enabled\r
+#define AT91C_CKGR_UPLLCOUNT  (0xF << 20) // (PMC) UTMI Oscillator Start-up Time\r
+#define AT91C_CKGR_BIASEN     (0x1 << 24) // (PMC) UTMI BIAS Enable\r
+#define        AT91C_CKGR_BIASEN_DISABLED             (0x0 << 24) // (PMC) The UTMI BIAS is disabled\r
+#define        AT91C_CKGR_BIASEN_ENABLED              (0x1 << 24) // (PMC) The UTMI BIAS is enabled\r
+#define AT91C_CKGR_BIASCOUNT  (0xF << 28) // (PMC) UTMI BIAS Start-up Time\r
+// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- \r
+#define AT91C_CKGR_MOSCXTEN   (0x1 <<  0) // (PMC) Main Crystal Oscillator Enable\r
+#define AT91C_CKGR_MOSCXTBY   (0x1 <<  1) // (PMC) Main Crystal Oscillator Bypass\r
+#define AT91C_CKGR_WAITMODE   (0x1 <<  2) // (PMC) Main Crystal Oscillator Bypass\r
+#define AT91C_CKGR_MOSCRCEN   (0x1 <<  3) // (PMC) Main On-Chip RC Oscillator Enable\r
+#define AT91C_CKGR_MOSCRCF    (0x7 <<  4) // (PMC) Main On-Chip RC Oscillator Frequency Selection\r
+#define AT91C_CKGR_MOSCXTST   (0xFF <<  8) // (PMC) Main Crystal Oscillator Start-up Time\r
+#define AT91C_CKGR_KEY        (0xFF << 16) // (PMC) Clock Generator Controller Writing Protection Key\r
+#define AT91C_CKGR_MOSCSEL    (0x1 << 24) // (PMC) Main Oscillator Selection\r
+#define AT91C_CKGR_CFDEN      (0x1 << 25) // (PMC) Clock Failure Detector Enable\r
+// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- \r
+#define AT91C_CKGR_MAINF      (0xFFFF <<  0) // (PMC) Main Clock Frequency\r
+#define AT91C_CKGR_MAINRDY    (0x1 << 16) // (PMC) Main Clock Ready\r
+// -------- CKGR_PLLAR : (PMC Offset: 0x28) PLL A Register -------- \r
+#define AT91C_CKGR_DIVA       (0xFF <<  0) // (PMC) Divider Selected\r
+#define        AT91C_CKGR_DIVA_0                    (0x0) // (PMC) Divider output is 0\r
+#define        AT91C_CKGR_DIVA_BYPASS               (0x1) // (PMC) Divider is bypassed\r
+#define AT91C_CKGR_PLLACOUNT  (0x3F <<  8) // (PMC) PLLA Counter\r
+#define AT91C_CKGR_STMODE     (0x3 << 14) // (PMC) Start Mode\r
+#define        AT91C_CKGR_STMODE_0                    (0x0 << 14) // (PMC) Fast startup\r
+#define        AT91C_CKGR_STMODE_1                    (0x1 << 14) // (PMC) Reserved\r
+#define        AT91C_CKGR_STMODE_2                    (0x2 << 14) // (PMC) Normal startup\r
+#define        AT91C_CKGR_STMODE_3                    (0x3 << 14) // (PMC) Reserved\r
+#define AT91C_CKGR_MULA       (0x7FF << 16) // (PMC) PLL Multiplier\r
+#define AT91C_CKGR_SRC        (0x1 << 29) // (PMC) \r
+// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- \r
+#define AT91C_PMC_CSS         (0x7 <<  0) // (PMC) Programmable Clock Selection\r
+#define        AT91C_PMC_CSS_SLOW_CLK             (0x0) // (PMC) Slow Clock is selected\r
+#define        AT91C_PMC_CSS_MAIN_CLK             (0x1) // (PMC) Main Clock is selected\r
+#define        AT91C_PMC_CSS_PLLA_CLK             (0x2) // (PMC) Clock from PLL A is selected\r
+#define        AT91C_PMC_CSS_UPLL_CLK             (0x3) // (PMC) Clock from UPLL is selected\r
+#define        AT91C_PMC_CSS_SYS_CLK              (0x4) // (PMC) System clock is selected\r
+#define AT91C_PMC_PRES        (0x7 <<  4) // (PMC) Programmable Clock Prescaler\r
+#define        AT91C_PMC_PRES_CLK                  (0x0 <<  4) // (PMC) Selected clock\r
+#define        AT91C_PMC_PRES_CLK_2                (0x1 <<  4) // (PMC) Selected clock divided by 2\r
+#define        AT91C_PMC_PRES_CLK_4                (0x2 <<  4) // (PMC) Selected clock divided by 4\r
+#define        AT91C_PMC_PRES_CLK_8                (0x3 <<  4) // (PMC) Selected clock divided by 8\r
+#define        AT91C_PMC_PRES_CLK_16               (0x4 <<  4) // (PMC) Selected clock divided by 16\r
+#define        AT91C_PMC_PRES_CLK_32               (0x5 <<  4) // (PMC) Selected clock divided by 32\r
+#define        AT91C_PMC_PRES_CLK_64               (0x6 <<  4) // (PMC) Selected clock divided by 64\r
+#define        AT91C_PMC_PRES_CLK_6                (0x7 <<  4) // (PMC) Selected clock divided by 6\r
+// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- \r
+// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- \r
+#define AT91C_PMC_MOSCXTS     (0x1 <<  0) // (PMC) Main Crystal Oscillator Status/Enable/Disable/Mask\r
+#define AT91C_PMC_LOCKA       (0x1 <<  1) // (PMC) PLL A Status/Enable/Disable/Mask\r
+#define AT91C_PMC_MCKRDY      (0x1 <<  3) // (PMC) Master Clock Status/Enable/Disable/Mask\r
+#define AT91C_PMC_LOCKU       (0x1 <<  6) // (PMC) PLL UTMI Status/Enable/Disable/Mask\r
+#define AT91C_PMC_PCKRDY0     (0x1 <<  8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask\r
+#define AT91C_PMC_PCKRDY1     (0x1 <<  9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask\r
+#define AT91C_PMC_PCKRDY2     (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask\r
+#define AT91C_PMC_MOSCSELS    (0x1 << 16) // (PMC) Main Oscillator Selection Status\r
+#define AT91C_PMC_MOSCRCS     (0x1 << 17) // (PMC) Main On-Chip RC Oscillator Status\r
+#define AT91C_PMC_CFDEV       (0x1 << 18) // (PMC) Clock Failure Detector Event\r
+// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- \r
+// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- \r
+#define AT91C_PMC_OSCSELS     (0x1 <<  7) // (PMC) Slow Clock Oscillator Selection\r
+#define AT91C_PMC_CFDS        (0x1 << 19) // (PMC) Clock Failure Detector Status\r
+#define AT91C_PMC_FOS         (0x1 << 20) // (PMC) Clock Failure Detector Fault Output Status\r
+// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- \r
+// -------- PMC_FSMR : (PMC Offset: 0x70) Fast Startup Mode Register -------- \r
+#define AT91C_PMC_FSTT        (0xFFFF <<  0) // (PMC) Fast Start-up Input Enable 0 to 15\r
+#define AT91C_PMC_RTTAL       (0x1 << 16) // (PMC) RTT Alarm Enable\r
+#define AT91C_PMC_RTCAL       (0x1 << 17) // (PMC) RTC Alarm Enable\r
+#define AT91C_PMC_USBAL       (0x1 << 18) // (PMC) USB Alarm Enable\r
+#define AT91C_PMC_LPM         (0x1 << 20) // (PMC) Low Power Mode\r
+// -------- PMC_FSPR : (PMC Offset: 0x74) Fast Startup Polarity Register -------- \r
+#define AT91C_PMC_FSTP        (0xFFFF <<  0) // (PMC) Fast Start-up Input Polarity 0 to 15\r
+// -------- PMC_FOCR : (PMC Offset: 0x78) Fault Output Clear Register -------- \r
+#define AT91C_PMC_FOCLR       (0x1 <<  0) // (PMC) Fault Output Clear\r
+\r
+// *****************************************************************************\r
+//              SOFTWARE API DEFINITION  FOR Clock Generator Controler\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_CKGR {\r
+       AT91_REG         CKGR_UCKR;     // UTMI Clock Configuration Register\r
+       AT91_REG         CKGR_MOR;      // Main Oscillator Register\r
+       AT91_REG         CKGR_MCFR;     // Main Clock  Frequency Register\r
+       AT91_REG         CKGR_PLLAR;    // PLL Register\r
+} AT91S_CKGR, *AT91PS_CKGR;\r
+#else\r
+\r
+#endif\r
+// -------- CKGR_UCKR : (CKGR Offset: 0x0) UTMI Clock Configuration Register -------- \r
+// -------- CKGR_MOR : (CKGR Offset: 0x4) Main Oscillator Register -------- \r
+// -------- CKGR_MCFR : (CKGR Offset: 0x8) Main Clock Frequency Register -------- \r
+// -------- CKGR_PLLAR : (CKGR Offset: 0xc) PLL A Register -------- \r
+\r
+// *****************************************************************************\r
+//              SOFTWARE API DEFINITION  FOR Reset Controller Interface\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_RSTC {\r
+       AT91_REG         RSTC_RCR;      // Reset Control Register\r
+       AT91_REG         RSTC_RSR;      // Reset Status Register\r
+       AT91_REG         RSTC_RMR;      // Reset Mode Register\r
+       AT91_REG         Reserved0[60];         // \r
+       AT91_REG         RSTC_VER;      // Version Register\r
+} AT91S_RSTC, *AT91PS_RSTC;\r
+#else\r
+#define RSTC_RCR        (AT91_CAST(AT91_REG *)         0x00000000) // (RSTC_RCR) Reset Control Register\r
+#define RSTC_RSR        (AT91_CAST(AT91_REG *)         0x00000004) // (RSTC_RSR) Reset Status Register\r
+#define RSTC_RMR        (AT91_CAST(AT91_REG *)         0x00000008) // (RSTC_RMR) Reset Mode Register\r
+#define RSTC_VER        (AT91_CAST(AT91_REG *)         0x000000FC) // (RSTC_VER) Version Register\r
+\r
+#endif\r
+// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- \r
+#define AT91C_RSTC_PROCRST    (0x1 <<  0) // (RSTC) Processor Reset\r
+#define AT91C_RSTC_ICERST     (0x1 <<  1) // (RSTC) ICE Interface Reset\r
+#define AT91C_RSTC_PERRST     (0x1 <<  2) // (RSTC) Peripheral Reset\r
+#define AT91C_RSTC_EXTRST     (0x1 <<  3) // (RSTC) External Reset\r
+#define AT91C_RSTC_KEY        (0xFF << 24) // (RSTC) Password\r
+// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- \r
+#define AT91C_RSTC_URSTS      (0x1 <<  0) // (RSTC) User Reset Status\r
+#define AT91C_RSTC_RSTTYP     (0x7 <<  8) // (RSTC) Reset Type\r
+#define        AT91C_RSTC_RSTTYP_GENERAL              (0x0 <<  8) // (RSTC) General reset. Both VDDCORE and VDDBU rising.\r
+#define        AT91C_RSTC_RSTTYP_WAKEUP               (0x1 <<  8) // (RSTC) WakeUp Reset. VDDCORE rising.\r
+#define        AT91C_RSTC_RSTTYP_WATCHDOG             (0x2 <<  8) // (RSTC) Watchdog Reset. Watchdog overflow occured.\r
+#define        AT91C_RSTC_RSTTYP_SOFTWARE             (0x3 <<  8) // (RSTC) Software Reset. Processor reset required by the software.\r
+#define        AT91C_RSTC_RSTTYP_USER                 (0x4 <<  8) // (RSTC) User Reset. NRST pin detected low.\r
+#define AT91C_RSTC_NRSTL      (0x1 << 16) // (RSTC) NRST pin level\r
+#define AT91C_RSTC_SRCMP      (0x1 << 17) // (RSTC) Software Reset Command in Progress.\r
+// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- \r
+#define AT91C_RSTC_URSTEN     (0x1 <<  0) // (RSTC) User Reset Enable\r
+#define AT91C_RSTC_URSTIEN    (0x1 <<  4) // (RSTC) User Reset Interrupt Enable\r
+#define AT91C_RSTC_ERSTL      (0xF <<  8) // (RSTC) User Reset Enable\r
+\r
+// *****************************************************************************\r
+//              SOFTWARE API DEFINITION  FOR Supply Controller Interface\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_SUPC {\r
+       AT91_REG         SUPC_CR;       // Control Register\r
+       AT91_REG         SUPC_BOMR;     // Brown Out Mode Register\r
+       AT91_REG         SUPC_MR;       // Mode Register\r
+       AT91_REG         SUPC_WUMR;     // Wake Up Mode Register\r
+       AT91_REG         SUPC_WUIR;     // Wake Up Inputs Register\r
+       AT91_REG         SUPC_SR;       // Status Register\r
+       AT91_REG         SUPC_FWUTR;    // Flash Wake-up Timer Register\r
+} AT91S_SUPC, *AT91PS_SUPC;\r
+#else\r
+#define SUPC_CR         (AT91_CAST(AT91_REG *)         0x00000000) // (SUPC_CR) Control Register\r
+#define SUPC_BOMR       (AT91_CAST(AT91_REG *)         0x00000004) // (SUPC_BOMR) Brown Out Mode Register\r
+#define SUPC_MR         (AT91_CAST(AT91_REG *)         0x00000008) // (SUPC_MR) Mode Register\r
+#define SUPC_WUMR       (AT91_CAST(AT91_REG *)         0x0000000C) // (SUPC_WUMR) Wake Up Mode Register\r
+#define SUPC_WUIR       (AT91_CAST(AT91_REG *)         0x00000010) // (SUPC_WUIR) Wake Up Inputs Register\r
+#define SUPC_SR         (AT91_CAST(AT91_REG *)         0x00000014) // (SUPC_SR) Status Register\r
+#define SUPC_FWUTR      (AT91_CAST(AT91_REG *)         0x00000018) // (SUPC_FWUTR) Flash Wake-up Timer Register\r
+\r
+#endif\r
+// -------- SUPC_CR : (SUPC Offset: 0x0) Control Register -------- \r
+#define AT91C_SUPC_SHDW       (0x1 <<  0) // (SUPC) Shut Down Command\r
+#define AT91C_SUPC_SHDWEOF    (0x1 <<  1) // (SUPC) Shut Down after End Of Frame\r
+#define AT91C_SUPC_VROFF      (0x1 <<  2) // (SUPC) Voltage Regulator Off\r
+#define AT91C_SUPC_XTALSEL    (0x1 <<  3) // (SUPC) Crystal Oscillator Select\r
+#define AT91C_SUPC_KEY        (0xFF << 24) // (SUPC) Supply Controller Writing Protection Key\r
+// -------- SUPC_BOMR : (SUPC Offset: 0x4) Brown Out Mode Register -------- \r
+#define AT91C_SUPC_BODTH      (0xF <<  0) // (SUPC) Brown Out Threshold\r
+#define AT91C_SUPC_BODSMPL    (0x7 <<  8) // (SUPC) Brown Out Sampling Period\r
+#define        AT91C_SUPC_BODSMPL_DISABLED             (0x0 <<  8) // (SUPC) Brown Out Detector disabled\r
+#define        AT91C_SUPC_BODSMPL_CONTINUOUS           (0x1 <<  8) // (SUPC) Continuous Brown Out Detector\r
+#define        AT91C_SUPC_BODSMPL_32_SLCK              (0x2 <<  8) // (SUPC) Brown Out Detector enabled one SLCK period every 32 SLCK periods\r
+#define        AT91C_SUPC_BODSMPL_256_SLCK             (0x3 <<  8) // (SUPC) Brown Out Detector enabled one SLCK period every 256 SLCK periods\r
+#define        AT91C_SUPC_BODSMPL_2048_SLCK            (0x4 <<  8) // (SUPC) Brown Out Detector enabled one SLCK period every 2048 SLCK periods\r
+#define AT91C_SUPC_BODRSTEN   (0x1 << 12) // (SUPC) Brownout Reset Enable\r
+// -------- SUPC_MR : (SUPC Offset: 0x8) Supply Controller Mode Register -------- \r
+#define AT91C_SUPC_LCDOUT     (0xF <<  0) // (SUPC) LCD Charge Pump Output Voltage Selection\r
+#define AT91C_SUPC_LCDMODE    (0x3 <<  4) // (SUPC) Segment LCD Supply Mode\r
+#define        AT91C_SUPC_LCDMODE_OFF                  (0x0 <<  4) // (SUPC) The internal and external supply sources are both deselected and the on-chip charge pump is turned off\r
+#define        AT91C_SUPC_LCDMODE_OFF_AFTER_EOF        (0x1 <<  4) // (SUPC) At the End Of Frame from LCD controller, the internal and external supply sources are both deselected and the on-chip charge pump is turned off\r
+#define        AT91C_SUPC_LCDMODE_EXTERNAL             (0x2 <<  4) // (SUPC) The external supply source is selected\r
+#define        AT91C_SUPC_LCDMODE_INTERNAL             (0x3 <<  4) // (SUPC) The internal supply source is selected and the on-chip charge pump is turned on\r
+#define AT91C_SUPC_VRDEEP     (0x1 <<  8) // (SUPC) Voltage Regulator Deep Mode\r
+#define AT91C_SUPC_VRVDD      (0x7 <<  9) // (SUPC) Voltage Regulator Output Voltage Selection\r
+#define AT91C_SUPC_VRRSTEN    (0x1 << 12) // (SUPC) Voltage Regulation Loss Reset Enable\r
+#define AT91C_SUPC_GPBRON     (0x1 << 16) // (SUPC) GPBR ON\r
+#define AT91C_SUPC_SRAMON     (0x1 << 17) // (SUPC) SRAM ON\r
+#define AT91C_SUPC_RTCON      (0x1 << 18) // (SUPC) Real Time Clock Power switch ON\r
+#define AT91C_SUPC_FLASHON    (0x1 << 19) // (SUPC) Flash Power switch On\r
+#define AT91C_SUPC_BYPASS     (0x1 << 20) // (SUPC) 32kHz oscillator bypass\r
+#define AT91C_SUPC_MKEY       (0xFF << 24) // (SUPC) Supply Controller Writing Protection Key\r
+// -------- SUPC_WUMR : (SUPC Offset: 0xc) Wake Up Mode Register -------- \r
+#define AT91C_SUPC_FWUPEN     (0x1 <<  0) // (SUPC) Force Wake Up Enable\r
+#define AT91C_SUPC_BODEN      (0x1 <<  1) // (SUPC) Brown Out Wake Up Enable\r
+#define AT91C_SUPC_RTTEN      (0x1 <<  2) // (SUPC) Real Time Timer Wake Up Enable\r
+#define AT91C_SUPC_RTCEN      (0x1 <<  3) // (SUPC) Real Time Clock Wake Up Enable\r
+#define AT91C_SUPC_FWUPDBC    (0x7 <<  8) // (SUPC) Force Wake Up debouncer\r
+#define        AT91C_SUPC_FWUPDBC_IMMEDIATE            (0x0 <<  8) // (SUPC) Immediate, No debouncing, detected active at least one Slow clock edge\r
+#define        AT91C_SUPC_FWUPDBC_3_SLCK               (0x1 <<  8) // (SUPC) An enabled Wake Up input shall be low for at least 3 SLCK periods\r
+#define        AT91C_SUPC_FWUPDBC_32_SLCK              (0x2 <<  8) // (SUPC) An enabled Wake Up input  shall be low for at least 32 SLCK periods\r
+#define        AT91C_SUPC_FWUPDBC_512_SLCK             (0x3 <<  8) // (SUPC) An enabled Wake Up input  shall be low for at least 512 SLCK periods\r
+#define        AT91C_SUPC_FWUPDBC_4096_SLCK            (0x4 <<  8) // (SUPC) An enabled Wake Up input  shall be low for at least 4096 SLCK periods\r
+#define        AT91C_SUPC_FWUPDBC_32768_SLCK           (0x5 <<  8) // (SUPC) An enabled Wake Up input  shall be low for at least 32768 SLCK periods\r
+#define AT91C_SUPC_WKUPDBC    (0x7 << 12) // (SUPC) Force Wake Up debouncer\r
+#define        AT91C_SUPC_WKUPDBC_IMMEDIATE            (0x0 << 12) // (SUPC) Immediate, No debouncing, detected active at least one Slow clock edge\r
+#define        AT91C_SUPC_WKUPDBC_3_SLCK               (0x1 << 12) // (SUPC) FWUP shall be low for at least 3 SLCK periods\r
+#define        AT91C_SUPC_WKUPDBC_32_SLCK              (0x2 << 12) // (SUPC) FWUP shall be low for at least 32 SLCK periods\r
+#define        AT91C_SUPC_WKUPDBC_512_SLCK             (0x3 << 12) // (SUPC) FWUP shall be low for at least 512 SLCK periods\r
+#define        AT91C_SUPC_WKUPDBC_4096_SLCK            (0x4 << 12) // (SUPC) FWUP shall be low for at least 4096 SLCK periods\r
+#define        AT91C_SUPC_WKUPDBC_32768_SLCK           (0x5 << 12) // (SUPC) FWUP shall be low for at least 32768 SLCK periods\r
+// -------- SUPC_WUIR : (SUPC Offset: 0x10) Wake Up Inputs Register -------- \r
+#define AT91C_SUPC_WKUPEN0    (0x1 <<  0) // (SUPC) Wake Up Input Enable 0\r
+#define AT91C_SUPC_WKUPEN1    (0x1 <<  1) // (SUPC) Wake Up Input Enable 1\r
+#define AT91C_SUPC_WKUPEN2    (0x1 <<  2) // (SUPC) Wake Up Input Enable 2\r
+#define AT91C_SUPC_WKUPEN3    (0x1 <<  3) // (SUPC) Wake Up Input Enable 3\r
+#define AT91C_SUPC_WKUPEN4    (0x1 <<  4) // (SUPC) Wake Up Input Enable 4\r
+#define AT91C_SUPC_WKUPEN5    (0x1 <<  5) // (SUPC) Wake Up Input Enable 5\r
+#define AT91C_SUPC_WKUPEN6    (0x1 <<  6) // (SUPC) Wake Up Input Enable 6\r
+#define AT91C_SUPC_WKUPEN7    (0x1 <<  7) // (SUPC) Wake Up Input Enable 7\r
+#define AT91C_SUPC_WKUPEN8    (0x1 <<  8) // (SUPC) Wake Up Input Enable 8\r
+#define AT91C_SUPC_WKUPEN9    (0x1 <<  9) // (SUPC) Wake Up Input Enable 9\r
+#define AT91C_SUPC_WKUPEN10   (0x1 << 10) // (SUPC) Wake Up Input Enable 10\r
+#define AT91C_SUPC_WKUPEN11   (0x1 << 11) // (SUPC) Wake Up Input Enable 11\r
+#define AT91C_SUPC_WKUPEN12   (0x1 << 12) // (SUPC) Wake Up Input Enable 12\r
+#define AT91C_SUPC_WKUPEN13   (0x1 << 13) // (SUPC) Wake Up Input Enable 13\r
+#define AT91C_SUPC_WKUPEN14   (0x1 << 14) // (SUPC) Wake Up Input Enable 14\r
+#define AT91C_SUPC_WKUPEN15   (0x1 << 15) // (SUPC) Wake Up Input Enable 15\r
+#define AT91C_SUPC_WKUPT0     (0x1 << 16) // (SUPC) Wake Up Input Transition 0\r
+#define AT91C_SUPC_WKUPT1     (0x1 << 17) // (SUPC) Wake Up Input Transition 1\r
+#define AT91C_SUPC_WKUPT2     (0x1 << 18) // (SUPC) Wake Up Input Transition 2\r
+#define AT91C_SUPC_WKUPT3     (0x1 << 19) // (SUPC) Wake Up Input Transition 3\r
+#define AT91C_SUPC_WKUPT4     (0x1 << 20) // (SUPC) Wake Up Input Transition 4\r
+#define AT91C_SUPC_WKUPT5     (0x1 << 21) // (SUPC) Wake Up Input Transition 5\r
+#define AT91C_SUPC_WKUPT6     (0x1 << 22) // (SUPC) Wake Up Input Transition 6\r
+#define AT91C_SUPC_WKUPT7     (0x1 << 23) // (SUPC) Wake Up Input Transition 7\r
+#define AT91C_SUPC_WKUPT8     (0x1 << 24) // (SUPC) Wake Up Input Transition 8\r
+#define AT91C_SUPC_WKUPT9     (0x1 << 25) // (SUPC) Wake Up Input Transition 9\r
+#define AT91C_SUPC_WKUPT10    (0x1 << 26) // (SUPC) Wake Up Input Transition 10\r
+#define AT91C_SUPC_WKUPT11    (0x1 << 27) // (SUPC) Wake Up Input Transition 11\r
+#define AT91C_SUPC_WKUPT12    (0x1 << 28) // (SUPC) Wake Up Input Transition 12\r
+#define AT91C_SUPC_WKUPT13    (0x1 << 29) // (SUPC) Wake Up Input Transition 13\r
+#define AT91C_SUPC_WKUPT14    (0x1 << 30) // (SUPC) Wake Up Input Transition 14\r
+#define AT91C_SUPC_WKUPT15    (0x1 << 31) // (SUPC) Wake Up Input Transition 15\r
+// -------- SUPC_SR : (SUPC Offset: 0x14) Status Register -------- \r
+#define AT91C_SUPC_FWUPS      (0x1 <<  0) // (SUPC) Force Wake Up Status\r
+#define AT91C_SUPC_WKUPS      (0x1 <<  1) // (SUPC) Wake Up Status\r
+#define AT91C_SUPC_BODWS      (0x1 <<  2) // (SUPC) BOD Detection Wake Up Status\r
+#define AT91C_SUPC_VRRSTS     (0x1 <<  3) // (SUPC) Voltage regulation Loss Reset Status\r
+#define AT91C_SUPC_BODRSTS    (0x1 <<  4) // (SUPC) BOD detection Reset Status\r
+#define AT91C_SUPC_BODS       (0x1 <<  5) // (SUPC) BOD Status\r
+#define AT91C_SUPC_BROWNOUT   (0x1 <<  6) // (SUPC) BOD Output Status\r
+#define AT91C_SUPC_OSCSEL     (0x1 <<  7) // (SUPC) 32kHz Oscillator Selection Status\r
+#define AT91C_SUPC_LCDS       (0x1 <<  8) // (SUPC) LCD Status\r
+#define AT91C_SUPC_GPBRS      (0x1 <<  9) // (SUPC) General Purpose Back-up registers Status\r
+#define AT91C_SUPC_RTS        (0x1 << 10) // (SUPC) Clock Status\r
+#define AT91C_SUPC_FLASHS     (0x1 << 11) // (SUPC) FLASH Memory Status\r
+#define AT91C_SUPC_FWUPIS     (0x1 << 12) // (SUPC) WKUP Input Status\r
+#define AT91C_SUPC_WKUPIS0    (0x1 << 16) // (SUPC) WKUP Input 0 Status\r
+#define AT91C_SUPC_WKUPIS1    (0x1 << 17) // (SUPC) WKUP Input 1 Status\r
+#define AT91C_SUPC_WKUPIS2    (0x1 << 18) // (SUPC) WKUP Input 2 Status\r
+#define AT91C_SUPC_WKUPIS3    (0x1 << 19) // (SUPC) WKUP Input 3 Status\r
+#define AT91C_SUPC_WKUPIS4    (0x1 << 20) // (SUPC) WKUP Input 4 Status\r
+#define AT91C_SUPC_WKUPIS5    (0x1 << 21) // (SUPC) WKUP Input 5 Status\r
+#define AT91C_SUPC_WKUPIS6    (0x1 << 22) // (SUPC) WKUP Input 6 Status\r
+#define AT91C_SUPC_WKUPIS7    (0x1 << 23) // (SUPC) WKUP Input 7 Status\r
+#define AT91C_SUPC_WKUPIS8    (0x1 << 24) // (SUPC) WKUP Input 8 Status\r
+#define AT91C_SUPC_WKUPIS9    (0x1 << 25) // (SUPC) WKUP Input 9 Status\r
+#define AT91C_SUPC_WKUPIS10   (0x1 << 26) // (SUPC) WKUP Input 10 Status\r
+#define AT91C_SUPC_WKUPIS11   (0x1 << 27) // (SUPC) WKUP Input 11 Status\r
+#define AT91C_SUPC_WKUPIS12   (0x1 << 28) // (SUPC) WKUP Input 12 Status\r
+#define AT91C_SUPC_WKUPIS13   (0x1 << 29) // (SUPC) WKUP Input 13 Status\r
+#define AT91C_SUPC_WKUPIS14   (0x1 << 30) // (SUPC) WKUP Input 14 Status\r
+#define AT91C_SUPC_WKUPIS15   (0x1 << 31) // (SUPC) WKUP Input 15 Status\r
+// -------- SUPC_FWUTR : (SUPC Offset: 0x18) Flash Wake Up Timer Register -------- \r
+#define AT91C_SUPC_FWUT       (0x3FF <<  0) // (SUPC) Flash Wake Up Timer\r
+\r
+// *****************************************************************************\r
+//              SOFTWARE API DEFINITION  FOR Real Time Timer Controller Interface\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_RTTC {\r
+       AT91_REG         RTTC_RTMR;     // Real-time Mode Register\r
+       AT91_REG         RTTC_RTAR;     // Real-time Alarm Register\r
+       AT91_REG         RTTC_RTVR;     // Real-time Value Register\r
+       AT91_REG         RTTC_RTSR;     // Real-time Status Register\r
+} AT91S_RTTC, *AT91PS_RTTC;\r
+#else\r
+#define RTTC_RTMR       (AT91_CAST(AT91_REG *)         0x00000000) // (RTTC_RTMR) Real-time Mode Register\r
+#define RTTC_RTAR       (AT91_CAST(AT91_REG *)         0x00000004) // (RTTC_RTAR) Real-time Alarm Register\r
+#define RTTC_RTVR       (AT91_CAST(AT91_REG *)         0x00000008) // (RTTC_RTVR) Real-time Value Register\r
+#define RTTC_RTSR       (AT91_CAST(AT91_REG *)         0x0000000C) // (RTTC_RTSR) Real-time Status Register\r
+\r
+#endif\r
+// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- \r
+#define AT91C_RTTC_RTPRES     (0xFFFF <<  0) // (RTTC) Real-time Timer Prescaler Value\r
+#define AT91C_RTTC_ALMIEN     (0x1 << 16) // (RTTC) Alarm Interrupt Enable\r
+#define AT91C_RTTC_RTTINCIEN  (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable\r
+#define AT91C_RTTC_RTTRST     (0x1 << 18) // (RTTC) Real Time Timer Restart\r
+// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- \r
+#define AT91C_RTTC_ALMV       (0x0 <<  0) // (RTTC) Alarm Value\r
+// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- \r
+#define AT91C_RTTC_CRTV       (0x0 <<  0) // (RTTC) Current Real-time Value\r
+// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- \r
+#define AT91C_RTTC_ALMS       (0x1 <<  0) // (RTTC) Real-time Alarm Status\r
+#define AT91C_RTTC_RTTINC     (0x1 <<  1) // (RTTC) Real-time Timer Increment\r
+\r
+// *****************************************************************************\r
+//              SOFTWARE API DEFINITION  FOR Watchdog Timer Controller Interface\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_WDTC {\r
+       AT91_REG         WDTC_WDCR;     // Watchdog Control Register\r
+       AT91_REG         WDTC_WDMR;     // Watchdog Mode Register\r
+       AT91_REG         WDTC_WDSR;     // Watchdog Status Register\r
+} AT91S_WDTC, *AT91PS_WDTC;\r
+#else\r
+#define WDTC_WDCR       (AT91_CAST(AT91_REG *)         0x00000000) // (WDTC_WDCR) Watchdog Control Register\r
+#define WDTC_WDMR       (AT91_CAST(AT91_REG *)         0x00000004) // (WDTC_WDMR) Watchdog Mode Register\r
+#define WDTC_WDSR       (AT91_CAST(AT91_REG *)         0x00000008) // (WDTC_WDSR) Watchdog Status Register\r
+\r
+#endif\r
+// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- \r
+#define AT91C_WDTC_WDRSTT     (0x1 <<  0) // (WDTC) Watchdog Restart\r
+#define AT91C_WDTC_KEY        (0xFF << 24) // (WDTC) Watchdog KEY Password\r
+// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- \r
+#define AT91C_WDTC_WDV        (0xFFF <<  0) // (WDTC) Watchdog Timer Restart\r
+#define AT91C_WDTC_WDFIEN     (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable\r
+#define AT91C_WDTC_WDRSTEN    (0x1 << 13) // (WDTC) Watchdog Reset Enable\r
+#define AT91C_WDTC_WDRPROC    (0x1 << 14) // (WDTC) Watchdog Timer Restart\r
+#define AT91C_WDTC_WDDIS      (0x1 << 15) // (WDTC) Watchdog Disable\r
+#define AT91C_WDTC_WDD        (0xFFF << 16) // (WDTC) Watchdog Delta Value\r
+#define AT91C_WDTC_WDDBGHLT   (0x1 << 28) // (WDTC) Watchdog Debug Halt\r
+#define AT91C_WDTC_WDIDLEHLT  (0x1 << 29) // (WDTC) Watchdog Idle Halt\r
+// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- \r
+#define AT91C_WDTC_WDUNF      (0x1 <<  0) // (WDTC) Watchdog Underflow\r
+#define AT91C_WDTC_WDERR      (0x1 <<  1) // (WDTC) Watchdog Error\r
+\r
+// *****************************************************************************\r
+//              SOFTWARE API DEFINITION  FOR Real-time Clock Alarm and Parallel Load Interface\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_RTC {\r
+       AT91_REG         RTC_CR;        // Control Register\r
+       AT91_REG         RTC_MR;        // Mode Register\r
+       AT91_REG         RTC_TIMR;      // Time Register\r
+       AT91_REG         RTC_CALR;      // Calendar Register\r
+       AT91_REG         RTC_TIMALR;    // Time Alarm Register\r
+       AT91_REG         RTC_CALALR;    // Calendar Alarm Register\r
+       AT91_REG         RTC_SR;        // Status Register\r
+       AT91_REG         RTC_SCCR;      // Status Clear Command Register\r
+       AT91_REG         RTC_IER;       // Interrupt Enable Register\r
+       AT91_REG         RTC_IDR;       // Interrupt Disable Register\r
+       AT91_REG         RTC_IMR;       // Interrupt Mask Register\r
+       AT91_REG         RTC_VER;       // Valid Entry Register\r
+} AT91S_RTC, *AT91PS_RTC;\r
+#else\r
+#define RTC_CR          (AT91_CAST(AT91_REG *)         0x00000000) // (RTC_CR) Control Register\r
+#define RTC_MR          (AT91_CAST(AT91_REG *)         0x00000004) // (RTC_MR) Mode Register\r
+#define RTC_TIMR        (AT91_CAST(AT91_REG *)         0x00000008) // (RTC_TIMR) Time Register\r
+#define RTC_CALR        (AT91_CAST(AT91_REG *)         0x0000000C) // (RTC_CALR) Calendar Register\r
+#define RTC_TIMALR      (AT91_CAST(AT91_REG *)         0x00000010) // (RTC_TIMALR) Time Alarm Register\r
+#define RTC_CALALR      (AT91_CAST(AT91_REG *)         0x00000014) // (RTC_CALALR) Calendar Alarm Register\r
+#define RTC_SR          (AT91_CAST(AT91_REG *)         0x00000018) // (RTC_SR) Status Register\r
+#define RTC_SCCR        (AT91_CAST(AT91_REG *)         0x0000001C) // (RTC_SCCR) Status Clear Command Register\r
+#define RTC_IER         (AT91_CAST(AT91_REG *)         0x00000020) // (RTC_IER) Interrupt Enable Register\r
+#define RTC_IDR         (AT91_CAST(AT91_REG *)         0x00000024) // (RTC_IDR) Interrupt Disable Register\r
+#define RTC_IMR         (AT91_CAST(AT91_REG *)         0x00000028) // (RTC_IMR) Interrupt Mask Register\r
+#define RTC_VER         (AT91_CAST(AT91_REG *)         0x0000002C) // (RTC_VER) Valid Entry Register\r
+\r
+#endif\r
+// -------- RTC_CR : (RTC Offset: 0x0) RTC Control Register -------- \r
+#define AT91C_RTC_UPDTIM      (0x1 <<  0) // (RTC) Update Request Time Register\r
+#define AT91C_RTC_UPDCAL      (0x1 <<  1) // (RTC) Update Request Calendar Register\r
+#define AT91C_RTC_TIMEVSEL    (0x3 <<  8) // (RTC) Time Event Selection\r
+#define        AT91C_RTC_TIMEVSEL_MINUTE               (0x0 <<  8) // (RTC) Minute change.\r
+#define        AT91C_RTC_TIMEVSEL_HOUR                 (0x1 <<  8) // (RTC) Hour change.\r
+#define        AT91C_RTC_TIMEVSEL_DAY24                (0x2 <<  8) // (RTC) Every day at midnight.\r
+#define        AT91C_RTC_TIMEVSEL_DAY12                (0x3 <<  8) // (RTC) Every day at noon.\r
+#define AT91C_RTC_CALEVSEL    (0x3 << 16) // (RTC) Calendar Event Selection\r
+#define        AT91C_RTC_CALEVSEL_WEEK                 (0x0 << 16) // (RTC) Week change (every Monday at time 00:00:00).\r
+#define        AT91C_RTC_CALEVSEL_MONTH                (0x1 << 16) // (RTC) Month change (every 01 of each month at time 00:00:00).\r
+#define        AT91C_RTC_CALEVSEL_YEAR                 (0x2 << 16) // (RTC) Year change (every January 1 at time 00:00:00).\r
+// -------- RTC_MR : (RTC Offset: 0x4) RTC Mode Register -------- \r
+#define AT91C_RTC_HRMOD       (0x1 <<  0) // (RTC) 12-24 hour Mode\r
+// -------- RTC_TIMR : (RTC Offset: 0x8) RTC Time Register -------- \r
+#define AT91C_RTC_SEC         (0x7F <<  0) // (RTC) Current Second\r
+#define AT91C_RTC_MIN         (0x7F <<  8) // (RTC) Current Minute\r
+#define AT91C_RTC_HOUR        (0x3F << 16) // (RTC) Current Hour\r
+#define AT91C_RTC_AMPM        (0x1 << 22) // (RTC) Ante Meridiem, Post Meridiem Indicator\r
+// -------- RTC_CALR : (RTC Offset: 0xc) RTC Calendar Register -------- \r
+#define AT91C_RTC_CENT        (0x3F <<  0) // (RTC) Current Century\r
+#define AT91C_RTC_YEAR        (0xFF <<  8) // (RTC) Current Year\r
+#define AT91C_RTC_MONTH       (0x1F << 16) // (RTC) Current Month\r
+#define AT91C_RTC_DAY         (0x7 << 21) // (RTC) Current Day\r
+#define AT91C_RTC_DATE        (0x3F << 24) // (RTC) Current Date\r
+// -------- RTC_TIMALR : (RTC Offset: 0x10) RTC Time Alarm Register -------- \r
+#define AT91C_RTC_SECEN       (0x1 <<  7) // (RTC) Second Alarm Enable\r
+#define AT91C_RTC_MINEN       (0x1 << 15) // (RTC) Minute Alarm\r
+#define AT91C_RTC_HOUREN      (0x1 << 23) // (RTC) Current Hour\r
+// -------- RTC_CALALR : (RTC Offset: 0x14) RTC Calendar Alarm Register -------- \r
+#define AT91C_RTC_MONTHEN     (0x1 << 23) // (RTC) Month Alarm Enable\r
+#define AT91C_RTC_DATEEN      (0x1 << 31) // (RTC) Date Alarm Enable\r
+// -------- RTC_SR : (RTC Offset: 0x18) RTC Status Register -------- \r
+#define AT91C_RTC_ACKUPD      (0x1 <<  0) // (RTC) Acknowledge for Update\r
+#define AT91C_RTC_ALARM       (0x1 <<  1) // (RTC) Alarm Flag\r
+#define AT91C_RTC_SECEV       (0x1 <<  2) // (RTC) Second Event\r
+#define AT91C_RTC_TIMEV       (0x1 <<  3) // (RTC) Time Event\r
+#define AT91C_RTC_CALEV       (0x1 <<  4) // (RTC) Calendar event\r
+// -------- RTC_SCCR : (RTC Offset: 0x1c) RTC Status Clear Command Register -------- \r
+// -------- RTC_IER : (RTC Offset: 0x20) RTC Interrupt Enable Register -------- \r
+// -------- RTC_IDR : (RTC Offset: 0x24) RTC Interrupt Disable Register -------- \r
+// -------- RTC_IMR : (RTC Offset: 0x28) RTC Interrupt Mask Register -------- \r
+// -------- RTC_VER : (RTC Offset: 0x2c) RTC Valid Entry Register -------- \r
+#define AT91C_RTC_NVTIM       (0x1 <<  0) // (RTC) Non valid Time\r
+#define AT91C_RTC_NVCAL       (0x1 <<  1) // (RTC) Non valid Calendar\r
+#define AT91C_RTC_NVTIMALR    (0x1 <<  2) // (RTC) Non valid time Alarm\r
+#define AT91C_RTC_NVCALALR    (0x1 <<  3) // (RTC) Nonvalid Calendar Alarm\r
+\r
+// *****************************************************************************\r
+//              SOFTWARE API DEFINITION  FOR Analog to Digital Convertor\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_ADC {\r
+       AT91_REG         ADC_CR;        // ADC Control Register\r
+       AT91_REG         ADC_MR;        // ADC Mode Register\r
+       AT91_REG         Reserved0[2];  // \r
+       AT91_REG         ADC_CHER;      // ADC Channel Enable Register\r
+       AT91_REG         ADC_CHDR;      // ADC Channel Disable Register\r
+       AT91_REG         ADC_CHSR;      // ADC Channel Status Register\r
+       AT91_REG         ADC_SR;        // ADC Status Register\r
+       AT91_REG         ADC_LCDR;      // ADC Last Converted Data Register\r
+       AT91_REG         ADC_IER;       // ADC Interrupt Enable Register\r
+       AT91_REG         ADC_IDR;       // ADC Interrupt Disable Register\r
+       AT91_REG         ADC_IMR;       // ADC Interrupt Mask Register\r
+       AT91_REG         ADC_CDR0;      // ADC Channel Data Register 0\r
+       AT91_REG         ADC_CDR1;      // ADC Channel Data Register 1\r
+       AT91_REG         ADC_CDR2;      // ADC Channel Data Register 2\r
+       AT91_REG         ADC_CDR3;      // ADC Channel Data Register 3\r
+       AT91_REG         ADC_CDR4;      // ADC Channel Data Register 4\r
+       AT91_REG         ADC_CDR5;      // ADC Channel Data Register 5\r
+       AT91_REG         ADC_CDR6;      // ADC Channel Data Register 6\r
+       AT91_REG         ADC_CDR7;      // ADC Channel Data Register 7\r
+       AT91_REG         Reserved1[5];  // \r
+       AT91_REG         ADC_ACR;       // Analog Control Register\r
+       AT91_REG         ADC_EMR;       // Extended Mode Register\r
+       AT91_REG         Reserved2[32];         // \r
+       AT91_REG         ADC_ADDRSIZE;  // ADC ADDRSIZE REGISTER \r
+       AT91_REG         ADC_IPNAME1;   // ADC IPNAME1 REGISTER \r
+       AT91_REG         ADC_IPNAME2;   // ADC IPNAME2 REGISTER \r
+       AT91_REG         ADC_FEATURES;  // ADC FEATURES REGISTER \r
+       AT91_REG         ADC_VER;       // ADC VERSION REGISTER\r
+       AT91_REG         ADC_RPR;       // Receive Pointer Register\r
+       AT91_REG         ADC_RCR;       // Receive Counter Register\r
+       AT91_REG         ADC_TPR;       // Transmit Pointer Register\r
+       AT91_REG         ADC_TCR;       // Transmit Counter Register\r
+       AT91_REG         ADC_RNPR;      // Receive Next Pointer Register\r
+       AT91_REG         ADC_RNCR;      // Receive Next Counter Register\r
+       AT91_REG         ADC_TNPR;      // Transmit Next Pointer Register\r
+       AT91_REG         ADC_TNCR;      // Transmit Next Counter Register\r
+       AT91_REG         ADC_PTCR;      // PDC Transfer Control Register\r
+       AT91_REG         ADC_PTSR;      // PDC Transfer Status Register\r
+} AT91S_ADC, *AT91PS_ADC;\r
+#else\r
+#define ADC_CR          (AT91_CAST(AT91_REG *)         0x00000000) // (ADC_CR) ADC Control Register\r
+#define ADC_MR          (AT91_CAST(AT91_REG *)         0x00000004) // (ADC_MR) ADC Mode Register\r
+#define ADC_CHER        (AT91_CAST(AT91_REG *)         0x00000010) // (ADC_CHER) ADC Channel Enable Register\r
+#define ADC_CHDR        (AT91_CAST(AT91_REG *)         0x00000014) // (ADC_CHDR) ADC Channel Disable Register\r
+#define ADC_CHSR        (AT91_CAST(AT91_REG *)         0x00000018) // (ADC_CHSR) ADC Channel Status Register\r
+#define ADC_SR          (AT91_CAST(AT91_REG *)         0x0000001C) // (ADC_SR) ADC Status Register\r
+#define ADC_LCDR        (AT91_CAST(AT91_REG *)         0x00000020) // (ADC_LCDR) ADC Last Converted Data Register\r
+#define ADC_IER         (AT91_CAST(AT91_REG *)         0x00000024) // (ADC_IER) ADC Interrupt Enable Register\r
+#define ADC_IDR         (AT91_CAST(AT91_REG *)         0x00000028) // (ADC_IDR) ADC Interrupt Disable Register\r
+#define ADC_IMR         (AT91_CAST(AT91_REG *)         0x0000002C) // (ADC_IMR) ADC Interrupt Mask Register\r
+#define ADC_CDR0        (AT91_CAST(AT91_REG *)         0x00000030) // (ADC_CDR0) ADC Channel Data Register 0\r
+#define ADC_CDR1        (AT91_CAST(AT91_REG *)         0x00000034) // (ADC_CDR1) ADC Channel Data Register 1\r
+#define ADC_CDR2        (AT91_CAST(AT91_REG *)         0x00000038) // (ADC_CDR2) ADC Channel Data Register 2\r
+#define ADC_CDR3        (AT91_CAST(AT91_REG *)         0x0000003C) // (ADC_CDR3) ADC Channel Data Register 3\r
+#define ADC_CDR4        (AT91_CAST(AT91_REG *)         0x00000040) // (ADC_CDR4) ADC Channel Data Register 4\r
+#define ADC_CDR5        (AT91_CAST(AT91_REG *)         0x00000044) // (ADC_CDR5) ADC Channel Data Register 5\r
+#define ADC_CDR6        (AT91_CAST(AT91_REG *)         0x00000048) // (ADC_CDR6) ADC Channel Data Register 6\r
+#define ADC_CDR7        (AT91_CAST(AT91_REG *)         0x0000004C) // (ADC_CDR7) ADC Channel Data Register 7\r
+#define ADC_ACR         (AT91_CAST(AT91_REG *)         0x00000064) // (ADC_ACR) Analog Control Register\r
+#define ADC_EMR         (AT91_CAST(AT91_REG *)         0x00000068) // (ADC_EMR) Extended Mode Register\r
+#define ADC_ADDRSIZE    (AT91_CAST(AT91_REG *)         0x000000EC) // (ADC_ADDRSIZE) ADC ADDRSIZE REGISTER \r
+#define ADC_IPNAME1     (AT91_CAST(AT91_REG *)         0x000000F0) // (ADC_IPNAME1) ADC IPNAME1 REGISTER \r
+#define ADC_IPNAME2     (AT91_CAST(AT91_REG *)         0x000000F4) // (ADC_IPNAME2) ADC IPNAME2 REGISTER \r
+#define ADC_FEATURES    (AT91_CAST(AT91_REG *)         0x000000F8) // (ADC_FEATURES) ADC FEATURES REGISTER \r
+#define ADC_VER         (AT91_CAST(AT91_REG *)         0x000000FC) // (ADC_VER) ADC VERSION REGISTER\r
+\r
+#endif\r
+// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- \r
+#define AT91C_ADC_SWRST       (0x1 <<  0) // (ADC) Software Reset\r
+#define AT91C_ADC_START       (0x1 <<  1) // (ADC) Start Conversion\r
+// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- \r
+#define AT91C_ADC_TRGEN       (0x1 <<  0) // (ADC) Trigger Enable\r
+#define        AT91C_ADC_TRGEN_DIS                  (0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software\r
+#define        AT91C_ADC_TRGEN_EN                   (0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled.\r
+#define AT91C_ADC_TRGSEL      (0x7 <<  1) // (ADC) Trigger Selection\r
+#define        AT91C_ADC_TRGSEL_EXT                  (0x0 <<  1) // (ADC) Selected TRGSEL = External Trigger\r
+#define        AT91C_ADC_TRGSEL_TIOA0                (0x1 <<  1) // (ADC) Selected TRGSEL = TIAO0\r
+#define        AT91C_ADC_TRGSEL_TIOA1                (0x2 <<  1) // (ADC) Selected TRGSEL = TIAO1\r
+#define        AT91C_ADC_TRGSEL_TIOA2                (0x3 <<  1) // (ADC) Selected TRGSEL = TIAO2\r
+#define        AT91C_ADC_TRGSEL_PWM0_TRIG            (0x4 <<  1) // (ADC) Selected TRGSEL = PWM trigger\r
+#define        AT91C_ADC_TRGSEL_PWM1_TRIG            (0x5 <<  1) // (ADC) Selected TRGSEL = PWM Trigger\r
+#define        AT91C_ADC_TRGSEL_RESERVED             (0x6 <<  1) // (ADC) Selected TRGSEL = Reserved\r
+#define AT91C_ADC_LOWRES      (0x1 <<  4) // (ADC) Resolution.\r
+#define        AT91C_ADC_LOWRES_10_BIT               (0x0 <<  4) // (ADC) 10-bit resolution\r
+#define        AT91C_ADC_LOWRES_8_BIT                (0x1 <<  4) // (ADC) 8-bit resolution\r
+#define AT91C_ADC_SLEEP       (0x1 <<  5) // (ADC) Sleep Mode\r
+#define        AT91C_ADC_SLEEP_NORMAL_MODE          (0x0 <<  5) // (ADC) Normal Mode\r
+#define        AT91C_ADC_SLEEP_MODE                 (0x1 <<  5) // (ADC) Sleep Mode\r
+#define AT91C_ADC_PRESCAL     (0x3F <<  8) // (ADC) Prescaler rate selection\r
+#define AT91C_ADC_STARTUP     (0x1F << 16) // (ADC) Startup Time\r
+#define AT91C_ADC_SHTIM       (0xF << 24) // (ADC) Sample & Hold Time\r
+// --------    ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- \r
+#define AT91C_ADC_CH0         (0x1 <<  0) // (ADC) Channel 0\r
+#define AT91C_ADC_CH1         (0x1 <<  1) // (ADC) Channel 1\r
+#define AT91C_ADC_CH2         (0x1 <<  2) // (ADC) Channel 2\r
+#define AT91C_ADC_CH3         (0x1 <<  3) // (ADC) Channel 3\r
+#define AT91C_ADC_CH4         (0x1 <<  4) // (ADC) Channel 4\r
+#define AT91C_ADC_CH5         (0x1 <<  5) // (ADC) Channel 5\r
+#define AT91C_ADC_CH6         (0x1 <<  6) // (ADC) Channel 6\r
+#define AT91C_ADC_CH7         (0x1 <<  7) // (ADC) Channel 7\r
+// --------    ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- \r
+// --------    ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- \r
+// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- \r
+#define AT91C_ADC_EOC0        (0x1 <<  0) // (ADC) End of Conversion\r
+#define AT91C_ADC_EOC1        (0x1 <<  1) // (ADC) End of Conversion\r
+#define AT91C_ADC_EOC2        (0x1 <<  2) // (ADC) End of Conversion\r
+#define AT91C_ADC_EOC3        (0x1 <<  3) // (ADC) End of Conversion\r
+#define AT91C_ADC_EOC4        (0x1 <<  4) // (ADC) End of Conversion\r
+#define AT91C_ADC_EOC5        (0x1 <<  5) // (ADC) End of Conversion\r
+#define AT91C_ADC_EOC6        (0x1 <<  6) // (ADC) End of Conversion\r
+#define AT91C_ADC_EOC7        (0x1 <<  7) // (ADC) End of Conversion\r
+#define AT91C_ADC_OVRE0       (0x1 <<  8) // (ADC) Overrun Error\r
+#define AT91C_ADC_OVRE1       (0x1 <<  9) // (ADC) Overrun Error\r
+#define AT91C_ADC_OVRE2       (0x1 << 10) // (ADC) Overrun Error\r
+#define AT91C_ADC_OVRE3       (0x1 << 11) // (ADC) Overrun Error\r
+#define AT91C_ADC_OVRE4       (0x1 << 12) // (ADC) Overrun Error\r
+#define AT91C_ADC_OVRE5       (0x1 << 13) // (ADC) Overrun Error\r
+#define AT91C_ADC_OVRE6       (0x1 << 14) // (ADC) Overrun Error\r
+#define AT91C_ADC_OVRE7       (0x1 << 15) // (ADC) Overrun Error\r
+#define AT91C_ADC_DRDY        (0x1 << 16) // (ADC) Data Ready\r
+#define AT91C_ADC_GOVRE       (0x1 << 17) // (ADC) General Overrun\r
+#define AT91C_ADC_ENDRX       (0x1 << 18) // (ADC) End of Receiver Transfer\r
+#define AT91C_ADC_RXBUFF      (0x1 << 19) // (ADC) RXBUFF Interrupt\r
+// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- \r
+#define AT91C_ADC_LDATA       (0x3FF <<  0) // (ADC) Last Data Converted\r
+// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- \r
+// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- \r
+// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- \r
+// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- \r
+#define AT91C_ADC_DATA        (0x3FF <<  0) // (ADC) Converted Data\r
+// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- \r
+// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- \r
+// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- \r
+// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- \r
+// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- \r
+// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- \r
+// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- \r
+// -------- ADC_ACR : (ADC Offset: 0x64) ADC Analog Controler Register -------- \r
+#define AT91C_ADC_GAIN        (0x3 <<  0) // (ADC) Input Gain\r
+#define AT91C_ADC_IBCTL       (0x3 <<  6) // (ADC) Bias Current Control\r
+#define        AT91C_ADC_IBCTL_00                   (0x0 <<  6) // (ADC) typ - 20%\r
+#define        AT91C_ADC_IBCTL_01                   (0x1 <<  6) // (ADC) typ\r
+#define        AT91C_ADC_IBCTL_10                   (0x2 <<  6) // (ADC) typ + 20%\r
+#define        AT91C_ADC_IBCTL_11                   (0x3 <<  6) // (ADC) typ + 40%\r
+#define AT91C_ADC_DIFF        (0x1 << 16) // (ADC) Differential Mode\r
+#define AT91C_ADC_OFFSET      (0x1 << 17) // (ADC) Input OFFSET\r
+// -------- ADC_EMR : (ADC Offset: 0x68) ADC Extended Mode Register -------- \r
+#define AT91C_OFFMODES        (0x1 <<  0) // (ADC) Off Mode if\r
+#define AT91C_OFF_MODE_STARTUP_TIME (0x1 << 16) // (ADC) Startup Time\r
+// -------- ADC_VER : (ADC Offset: 0xfc) ADC VER -------- \r
+#define AT91C_ADC_VER         (0xF <<  0) // (ADC) ADC VER\r
+\r
+// *****************************************************************************\r
+//              SOFTWARE API DEFINITION  FOR Timer Counter Channel Interface\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_TC {\r
+       AT91_REG         TC_CCR;        // Channel Control Register\r
+       AT91_REG         TC_CMR;        // Channel Mode Register (Capture Mode / Waveform Mode)\r
+       AT91_REG         Reserved0[2];  // \r
+       AT91_REG         TC_CV;         // Counter Value\r
+       AT91_REG         TC_RA;         // Register A\r
+       AT91_REG         TC_RB;         // Register B\r
+       AT91_REG         TC_RC;         // Register C\r
+       AT91_REG         TC_SR;         // Status Register\r
+       AT91_REG         TC_IER;        // Interrupt Enable Register\r
+       AT91_REG         TC_IDR;        // Interrupt Disable Register\r
+       AT91_REG         TC_IMR;        // Interrupt Mask Register\r
+} AT91S_TC, *AT91PS_TC;\r
+#else\r
+#define TC_CCR          (AT91_CAST(AT91_REG *)         0x00000000) // (TC_CCR) Channel Control Register\r
+#define TC_CMR          (AT91_CAST(AT91_REG *)         0x00000004) // (TC_CMR) Channel Mode Register (Capture Mode / Waveform Mode)\r
+#define TC_CV           (AT91_CAST(AT91_REG *)         0x00000010) // (TC_CV) Counter Value\r
+#define TC_RA           (AT91_CAST(AT91_REG *)         0x00000014) // (TC_RA) Register A\r
+#define TC_RB           (AT91_CAST(AT91_REG *)         0x00000018) // (TC_RB) Register B\r
+#define TC_RC           (AT91_CAST(AT91_REG *)         0x0000001C) // (TC_RC) Register C\r
+#define TC_SR           (AT91_CAST(AT91_REG *)         0x00000020) // (TC_SR) Status Register\r
+#define TC_IER          (AT91_CAST(AT91_REG *)         0x00000024) // (TC_IER) Interrupt Enable Register\r
+#define TC_IDR          (AT91_CAST(AT91_REG *)         0x00000028) // (TC_IDR) Interrupt Disable Register\r
+#define TC_IMR          (AT91_CAST(AT91_REG *)         0x0000002C) // (TC_IMR) Interrupt Mask Register\r
+\r
+#endif\r
+// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- \r
+#define AT91C_TC_CLKEN        (0x1 <<  0) // (TC) Counter Clock Enable Command\r
+#define AT91C_TC_CLKDIS       (0x1 <<  1) // (TC) Counter Clock Disable Command\r
+#define AT91C_TC_SWTRG        (0x1 <<  2) // (TC) Software Trigger Command\r
+// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- \r
+#define AT91C_TC_CLKS         (0x7 <<  0) // (TC) Clock Selection\r
+#define        AT91C_TC_CLKS_TIMER_DIV1_CLOCK     (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK\r
+#define        AT91C_TC_CLKS_TIMER_DIV2_CLOCK     (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK\r
+#define        AT91C_TC_CLKS_TIMER_DIV3_CLOCK     (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK\r
+#define        AT91C_TC_CLKS_TIMER_DIV4_CLOCK     (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK\r
+#define        AT91C_TC_CLKS_TIMER_DIV5_CLOCK     (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK\r
+#define        AT91C_TC_CLKS_XC0                  (0x5) // (TC) Clock selected: XC0\r
+#define        AT91C_TC_CLKS_XC1                  (0x6) // (TC) Clock selected: XC1\r
+#define        AT91C_TC_CLKS_XC2                  (0x7) // (TC) Clock selected: XC2\r
+#define AT91C_TC_CLKI         (0x1 <<  3) // (TC) Clock Invert\r
+#define AT91C_TC_BURST        (0x3 <<  4) // (TC) Burst Signal Selection\r
+#define        AT91C_TC_BURST_NONE                 (0x0 <<  4) // (TC) The clock is not gated by an external signal\r
+#define        AT91C_TC_BURST_XC0                  (0x1 <<  4) // (TC) XC0 is ANDed with the selected clock\r
+#define        AT91C_TC_BURST_XC1                  (0x2 <<  4) // (TC) XC1 is ANDed with the selected clock\r
+#define        AT91C_TC_BURST_XC2                  (0x3 <<  4) // (TC) XC2 is ANDed with the selected clock\r
+#define AT91C_TC_CPCSTOP      (0x1 <<  6) // (TC) Counter Clock Stopped with RC Compare\r
+#define AT91C_TC_LDBSTOP      (0x1 <<  6) // (TC) Counter Clock Stopped with RB Loading\r
+#define AT91C_TC_CPCDIS       (0x1 <<  7) // (TC) Counter Clock Disable with RC Compare\r
+#define AT91C_TC_LDBDIS       (0x1 <<  7) // (TC) Counter Clock Disabled with RB Loading\r
+#define AT91C_TC_ETRGEDG      (0x3 <<  8) // (TC) External Trigger Edge Selection\r
+#define        AT91C_TC_ETRGEDG_NONE                 (0x0 <<  8) // (TC) Edge: None\r
+#define        AT91C_TC_ETRGEDG_RISING               (0x1 <<  8) // (TC) Edge: rising edge\r
+#define        AT91C_TC_ETRGEDG_FALLING              (0x2 <<  8) // (TC) Edge: falling edge\r
+#define        AT91C_TC_ETRGEDG_BOTH                 (0x3 <<  8) // (TC) Edge: each edge\r
+#define AT91C_TC_EEVTEDG      (0x3 <<  8) // (TC) External Event Edge Selection\r
+#define        AT91C_TC_EEVTEDG_NONE                 (0x0 <<  8) // (TC) Edge: None\r
+#define        AT91C_TC_EEVTEDG_RISING               (0x1 <<  8) // (TC) Edge: rising edge\r
+#define        AT91C_TC_EEVTEDG_FALLING              (0x2 <<  8) // (TC) Edge: falling edge\r
+#define        AT91C_TC_EEVTEDG_BOTH                 (0x3 <<  8) // (TC) Edge: each edge\r
+#define AT91C_TC_EEVT         (0x3 << 10) // (TC) External Event  Selection\r
+#define        AT91C_TC_EEVT_TIOB                 (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input\r
+#define        AT91C_TC_EEVT_XC0                  (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output\r
+#define        AT91C_TC_EEVT_XC1                  (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output\r
+#define        AT91C_TC_EEVT_XC2                  (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output\r
+#define AT91C_TC_ABETRG       (0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection\r
+#define AT91C_TC_ENETRG       (0x1 << 12) // (TC) External Event Trigger enable\r
+#define AT91C_TC_WAVESEL      (0x3 << 13) // (TC) Waveform  Selection\r
+#define        AT91C_TC_WAVESEL_UP                   (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare\r
+#define        AT91C_TC_WAVESEL_UPDOWN               (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare\r
+#define        AT91C_TC_WAVESEL_UP_AUTO              (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare\r
+#define        AT91C_TC_WAVESEL_UPDOWN_AUTO          (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare\r
+#define AT91C_TC_CPCTRG       (0x1 << 14) // (TC) RC Compare Trigger Enable\r
+#define AT91C_TC_WAVE         (0x1 << 15) // (TC) \r
+#define AT91C_TC_ACPA         (0x3 << 16) // (TC) RA Compare Effect on TIOA\r
+#define        AT91C_TC_ACPA_NONE                 (0x0 << 16) // (TC) Effect: none\r
+#define        AT91C_TC_ACPA_SET                  (0x1 << 16) // (TC) Effect: set\r
+#define        AT91C_TC_ACPA_CLEAR                (0x2 << 16) // (TC) Effect: clear\r
+#define        AT91C_TC_ACPA_TOGGLE               (0x3 << 16) // (TC) Effect: toggle\r
+#define AT91C_TC_LDRA         (0x3 << 16) // (TC) RA Loading Selection\r
+#define        AT91C_TC_LDRA_NONE                 (0x0 << 16) // (TC) Edge: None\r
+#define        AT91C_TC_LDRA_RISING               (0x1 << 16) // (TC) Edge: rising edge of TIOA\r
+#define        AT91C_TC_LDRA_FALLING              (0x2 << 16) // (TC) Edge: falling edge of TIOA\r
+#define        AT91C_TC_LDRA_BOTH                 (0x3 << 16) // (TC) Edge: each edge of TIOA\r
+#define AT91C_TC_ACPC         (0x3 << 18) // (TC) RC Compare Effect on TIOA\r
+#define        AT91C_TC_ACPC_NONE                 (0x0 << 18) // (TC) Effect: none\r
+#define        AT91C_TC_ACPC_SET                  (0x1 << 18) // (TC) Effect: set\r
+#define        AT91C_TC_ACPC_CLEAR                (0x2 << 18) // (TC) Effect: clear\r
+#define        AT91C_TC_ACPC_TOGGLE               (0x3 << 18) // (TC) Effect: toggle\r
+#define AT91C_TC_LDRB         (0x3 << 18) // (TC) RB Loading Selection\r
+#define        AT91C_TC_LDRB_NONE                 (0x0 << 18) // (TC) Edge: None\r
+#define        AT91C_TC_LDRB_RISING               (0x1 << 18) // (TC) Edge: rising edge of TIOA\r
+#define        AT91C_TC_LDRB_FALLING              (0x2 << 18) // (TC) Edge: falling edge of TIOA\r
+#define        AT91C_TC_LDRB_BOTH                 (0x3 << 18) // (TC) Edge: each edge of TIOA\r
+#define AT91C_TC_AEEVT        (0x3 << 20) // (TC) External Event Effect on TIOA\r
+#define        AT91C_TC_AEEVT_NONE                 (0x0 << 20) // (TC) Effect: none\r
+#define        AT91C_TC_AEEVT_SET                  (0x1 << 20) // (TC) Effect: set\r
+#define        AT91C_TC_AEEVT_CLEAR                (0x2 << 20) // (TC) Effect: clear\r
+#define        AT91C_TC_AEEVT_TOGGLE               (0x3 << 20) // (TC) Effect: toggle\r
+#define AT91C_TC_ASWTRG       (0x3 << 22) // (TC) Software Trigger Effect on TIOA\r
+#define        AT91C_TC_ASWTRG_NONE                 (0x0 << 22) // (TC) Effect: none\r
+#define        AT91C_TC_ASWTRG_SET                  (0x1 << 22) // (TC) Effect: set\r
+#define        AT91C_TC_ASWTRG_CLEAR                (0x2 << 22) // (TC) Effect: clear\r
+#define        AT91C_TC_ASWTRG_TOGGLE               (0x3 << 22) // (TC) Effect: toggle\r
+#define AT91C_TC_BCPB         (0x3 << 24) // (TC) RB Compare Effect on TIOB\r
+#define        AT91C_TC_BCPB_NONE                 (0x0 << 24) // (TC) Effect: none\r
+#define        AT91C_TC_BCPB_SET                  (0x1 << 24) // (TC) Effect: set\r
+#define        AT91C_TC_BCPB_CLEAR                (0x2 << 24) // (TC) Effect: clear\r
+#define        AT91C_TC_BCPB_TOGGLE               (0x3 << 24) // (TC) Effect: toggle\r
+#define AT91C_TC_BCPC         (0x3 << 26) // (TC) RC Compare Effect on TIOB\r
+#define        AT91C_TC_BCPC_NONE                 (0x0 << 26) // (TC) Effect: none\r
+#define        AT91C_TC_BCPC_SET                  (0x1 << 26) // (TC) Effect: set\r
+#define        AT91C_TC_BCPC_CLEAR                (0x2 << 26) // (TC) Effect: clear\r
+#define        AT91C_TC_BCPC_TOGGLE               (0x3 << 26) // (TC) Effect: toggle\r
+#define AT91C_TC_BEEVT        (0x3 << 28) // (TC) External Event Effect on TIOB\r
+#define        AT91C_TC_BEEVT_NONE                 (0x0 << 28) // (TC) Effect: none\r
+#define        AT91C_TC_BEEVT_SET                  (0x1 << 28) // (TC) Effect: set\r
+#define        AT91C_TC_BEEVT_CLEAR                (0x2 << 28) // (TC) Effect: clear\r
+#define        AT91C_TC_BEEVT_TOGGLE               (0x3 << 28) // (TC) Effect: toggle\r
+#define AT91C_TC_BSWTRG       (0x3 << 30) // (TC) Software Trigger Effect on TIOB\r
+#define        AT91C_TC_BSWTRG_NONE                 (0x0 << 30) // (TC) Effect: none\r
+#define        AT91C_TC_BSWTRG_SET                  (0x1 << 30) // (TC) Effect: set\r
+#define        AT91C_TC_BSWTRG_CLEAR                (0x2 << 30) // (TC) Effect: clear\r
+#define        AT91C_TC_BSWTRG_TOGGLE               (0x3 << 30) // (TC) Effect: toggle\r
+// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- \r
+#define AT91C_TC_COVFS        (0x1 <<  0) // (TC) Counter Overflow\r
+#define AT91C_TC_LOVRS        (0x1 <<  1) // (TC) Load Overrun\r
+#define AT91C_TC_CPAS         (0x1 <<  2) // (TC) RA Compare\r
+#define AT91C_TC_CPBS         (0x1 <<  3) // (TC) RB Compare\r
+#define AT91C_TC_CPCS         (0x1 <<  4) // (TC) RC Compare\r
+#define AT91C_TC_LDRAS        (0x1 <<  5) // (TC) RA Loading\r
+#define AT91C_TC_LDRBS        (0x1 <<  6) // (TC) RB Loading\r
+#define AT91C_TC_ETRGS        (0x1 <<  7) // (TC) External Trigger\r
+#define AT91C_TC_CLKSTA       (0x1 << 16) // (TC) Clock Enabling\r
+#define AT91C_TC_MTIOA        (0x1 << 17) // (TC) TIOA Mirror\r
+#define AT91C_TC_MTIOB        (0x1 << 18) // (TC) TIOA Mirror\r
+// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- \r
+// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- \r
+// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- \r
+\r
+// *****************************************************************************\r
+//              SOFTWARE API DEFINITION  FOR Timer Counter Interface\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_TCB {\r
+       AT91S_TC         TCB_TC0;       // TC Channel 0\r
+       AT91_REG         Reserved0[4];  // \r
+       AT91S_TC         TCB_TC1;       // TC Channel 1\r
+       AT91_REG         Reserved1[4];  // \r
+       AT91S_TC         TCB_TC2;       // TC Channel 2\r
+       AT91_REG         Reserved2[4];  // \r
+       AT91_REG         TCB_BCR;       // TC Block Control Register\r
+       AT91_REG         TCB_BMR;       // TC Block Mode Register\r
+       AT91_REG         Reserved3[9];  // \r
+       AT91_REG         TCB_ADDRSIZE;  // TC ADDRSIZE REGISTER \r
+       AT91_REG         TCB_IPNAME1;   // TC IPNAME1 REGISTER \r
+       AT91_REG         TCB_IPNAME2;   // TC IPNAME2 REGISTER \r
+       AT91_REG         TCB_FEATURES;  // TC FEATURES REGISTER \r
+       AT91_REG         TCB_VER;       //  Version Register\r
+} AT91S_TCB, *AT91PS_TCB;\r
+#else\r
+#define TCB_BCR         (AT91_CAST(AT91_REG *)         0x000000C0) // (TCB_BCR) TC Block Control Register\r
+#define TCB_BMR         (AT91_CAST(AT91_REG *)         0x000000C4) // (TCB_BMR) TC Block Mode Register\r
+#define TC_ADDRSIZE     (AT91_CAST(AT91_REG *)         0x000000EC) // (TC_ADDRSIZE) TC ADDRSIZE REGISTER \r
+#define TC_IPNAME1      (AT91_CAST(AT91_REG *)         0x000000F0) // (TC_IPNAME1) TC IPNAME1 REGISTER \r
+#define TC_IPNAME2      (AT91_CAST(AT91_REG *)         0x000000F4) // (TC_IPNAME2) TC IPNAME2 REGISTER \r
+#define TC_FEATURES     (AT91_CAST(AT91_REG *)         0x000000F8) // (TC_FEATURES) TC FEATURES REGISTER \r
+#define TC_VER          (AT91_CAST(AT91_REG *)         0x000000FC) // (TC_VER)  Version Register\r
+\r
+#endif\r
+// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- \r
+#define AT91C_TCB_SYNC        (0x1 <<  0) // (TCB) Synchro Command\r
+// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- \r
+#define AT91C_TCB_TC0XC0S     (0x3 <<  0) // (TCB) External Clock Signal 0 Selection\r
+#define        AT91C_TCB_TC0XC0S_TCLK0                (0x0) // (TCB) TCLK0 connected to XC0\r
+#define        AT91C_TCB_TC0XC0S_NONE                 (0x1) // (TCB) None signal connected to XC0\r
+#define        AT91C_TCB_TC0XC0S_TIOA1                (0x2) // (TCB) TIOA1 connected to XC0\r
+#define        AT91C_TCB_TC0XC0S_TIOA2                (0x3) // (TCB) TIOA2 connected to XC0\r
+#define AT91C_TCB_TC1XC1S     (0x3 <<  2) // (TCB) External Clock Signal 1 Selection\r
+#define        AT91C_TCB_TC1XC1S_TCLK1                (0x0 <<  2) // (TCB) TCLK1 connected to XC1\r
+#define        AT91C_TCB_TC1XC1S_NONE                 (0x1 <<  2) // (TCB) None signal connected to XC1\r
+#define        AT91C_TCB_TC1XC1S_TIOA0                (0x2 <<  2) // (TCB) TIOA0 connected to XC1\r
+#define        AT91C_TCB_TC1XC1S_TIOA2                (0x3 <<  2) // (TCB) TIOA2 connected to XC1\r
+#define AT91C_TCB_TC2XC2S     (0x3 <<  4) // (TCB) External Clock Signal 2 Selection\r
+#define        AT91C_TCB_TC2XC2S_TCLK2                (0x0 <<  4) // (TCB) TCLK2 connected to XC2\r
+#define        AT91C_TCB_TC2XC2S_NONE                 (0x1 <<  4) // (TCB) None signal connected to XC2\r
+#define        AT91C_TCB_TC2XC2S_TIOA0                (0x2 <<  4) // (TCB) TIOA0 connected to XC2\r
+#define        AT91C_TCB_TC2XC2S_TIOA1                (0x3 <<  4) // (TCB) TIOA2 connected to XC2\r
+\r
+// *****************************************************************************\r
+//              SOFTWARE API DEFINITION  FOR Embedded Flash Controller 2.0\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_EFC {\r
+       AT91_REG         EFC_FMR;       // EFC Flash Mode Register\r
+       AT91_REG         EFC_FCR;       // EFC Flash Command Register\r
+       AT91_REG         EFC_FSR;       // EFC Flash Status Register\r
+       AT91_REG         EFC_FRR;       // EFC Flash Result Register\r
+       AT91_REG         Reserved0[1];  // \r
+       AT91_REG         EFC_FVR;       // EFC Flash Version Register\r
+} AT91S_EFC, *AT91PS_EFC;\r
+#else\r
+#define EFC_FMR         (AT91_CAST(AT91_REG *)         0x00000000) // (EFC_FMR) EFC Flash Mode Register\r
+#define EFC_FCR         (AT91_CAST(AT91_REG *)         0x00000004) // (EFC_FCR) EFC Flash Command Register\r
+#define EFC_FSR         (AT91_CAST(AT91_REG *)         0x00000008) // (EFC_FSR) EFC Flash Status Register\r
+#define EFC_FRR         (AT91_CAST(AT91_REG *)         0x0000000C) // (EFC_FRR) EFC Flash Result Register\r
+#define EFC_FVR         (AT91_CAST(AT91_REG *)         0x00000014) // (EFC_FVR) EFC Flash Version Register\r
+\r
+#endif\r
+// -------- EFC_FMR : (EFC Offset: 0x0) EFC Flash Mode Register -------- \r
+#define AT91C_EFC_FRDY        (0x1 <<  0) // (EFC) Ready Interrupt Enable\r
+#define AT91C_EFC_FWS         (0xF <<  8) // (EFC) Flash Wait State.\r
+#define        AT91C_EFC_FWS_0WS                  (0x0 <<  8) // (EFC) 0 Wait State\r
+#define        AT91C_EFC_FWS_1WS                  (0x1 <<  8) // (EFC) 1 Wait State\r
+#define        AT91C_EFC_FWS_2WS                  (0x2 <<  8) // (EFC) 2 Wait States\r
+#define        AT91C_EFC_FWS_3WS                  (0x3 <<  8) // (EFC) 3 Wait States\r
+// -------- EFC_FCR : (EFC Offset: 0x4) EFC Flash Command Register -------- \r
+#define AT91C_EFC_FCMD        (0xFF <<  0) // (EFC) Flash Command\r
+#define        AT91C_EFC_FCMD_GETD                 (0x0) // (EFC) Get Flash Descriptor\r
+#define        AT91C_EFC_FCMD_WP                   (0x1) // (EFC) Write Page\r
+#define        AT91C_EFC_FCMD_WPL                  (0x2) // (EFC) Write Page and Lock\r
+#define        AT91C_EFC_FCMD_EWP                  (0x3) // (EFC) Erase Page and Write Page\r
+#define        AT91C_EFC_FCMD_EWPL                 (0x4) // (EFC) Erase Page and Write Page then Lock\r
+#define        AT91C_EFC_FCMD_EA                   (0x5) // (EFC) Erase All\r
+#define        AT91C_EFC_FCMD_EPL                  (0x6) // (EFC) Erase Plane\r
+#define        AT91C_EFC_FCMD_EPA                  (0x7) // (EFC) Erase Pages\r
+#define        AT91C_EFC_FCMD_SLB                  (0x8) // (EFC) Set Lock Bit\r
+#define        AT91C_EFC_FCMD_CLB                  (0x9) // (EFC) Clear Lock Bit\r
+#define        AT91C_EFC_FCMD_GLB                  (0xA) // (EFC) Get Lock Bit\r
+#define        AT91C_EFC_FCMD_SFB                  (0xB) // (EFC) Set Fuse Bit\r
+#define        AT91C_EFC_FCMD_CFB                  (0xC) // (EFC) Clear Fuse Bit\r
+#define        AT91C_EFC_FCMD_GFB                  (0xD) // (EFC) Get Fuse Bit\r
+#define        AT91C_EFC_FCMD_STUI                 (0xE) // (EFC) Start Read Unique ID\r
+#define        AT91C_EFC_FCMD_SPUI                 (0xF) // (EFC) Stop Read Unique ID\r
+#define AT91C_EFC_FARG        (0xFFFF <<  8) // (EFC) Flash Command Argument\r
+#define AT91C_EFC_FKEY        (0xFF << 24) // (EFC) Flash Writing Protection Key\r
+// -------- EFC_FSR : (EFC Offset: 0x8) EFC Flash Status Register -------- \r
+#define AT91C_EFC_FRDY_S      (0x1 <<  0) // (EFC) Flash Ready Status\r
+#define AT91C_EFC_FCMDE       (0x1 <<  1) // (EFC) Flash Command Error Status\r
+#define AT91C_EFC_LOCKE       (0x1 <<  2) // (EFC) Flash Lock Error Status\r
+// -------- EFC_FRR : (EFC Offset: 0xc) EFC Flash Result Register -------- \r
+#define AT91C_EFC_FVALUE      (0x0 <<  0) // (EFC) Flash Result Value\r
+\r
+// *****************************************************************************\r
+//              SOFTWARE API DEFINITION  FOR Multimedia Card Interface\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_MCI {\r
+       AT91_REG         MCI_CR;        // MCI Control Register\r
+       AT91_REG         MCI_MR;        // MCI Mode Register\r
+       AT91_REG         MCI_DTOR;      // MCI Data Timeout Register\r
+       AT91_REG         MCI_SDCR;      // MCI SD/SDIO Card Register\r
+       AT91_REG         MCI_ARGR;      // MCI Argument Register\r
+       AT91_REG         MCI_CMDR;      // MCI Command Register\r
+       AT91_REG         MCI_BLKR;      // MCI Block Register\r
+       AT91_REG         MCI_CSTOR;     // MCI Completion Signal Timeout Register\r
+       AT91_REG         MCI_RSPR[4];   // MCI Response Register\r
+       AT91_REG         MCI_RDR;       // MCI Receive Data Register\r
+       AT91_REG         MCI_TDR;       // MCI Transmit Data Register\r
+       AT91_REG         Reserved0[2];  // \r
+       AT91_REG         MCI_SR;        // MCI Status Register\r
+       AT91_REG         MCI_IER;       // MCI Interrupt Enable Register\r
+       AT91_REG         MCI_IDR;       // MCI Interrupt Disable Register\r
+       AT91_REG         MCI_IMR;       // MCI Interrupt Mask Register\r
+       AT91_REG         MCI_DMA;       // MCI DMA Configuration Register\r
+       AT91_REG         MCI_CFG;       // MCI Configuration Register\r
+       AT91_REG         Reserved1[35];         // \r
+       AT91_REG         MCI_WPCR;      // MCI Write Protection Control Register\r
+       AT91_REG         MCI_WPSR;      // MCI Write Protection Status Register\r
+       AT91_REG         MCI_ADDRSIZE;  // MCI ADDRSIZE REGISTER \r
+       AT91_REG         MCI_IPNAME1;   // MCI IPNAME1 REGISTER \r
+       AT91_REG         MCI_IPNAME2;   // MCI IPNAME2 REGISTER \r
+       AT91_REG         MCI_FEATURES;  // MCI FEATURES REGISTER \r
+       AT91_REG         MCI_VER;       // MCI VERSION REGISTER \r
+       AT91_REG         MCI_RPR;       // Receive Pointer Register\r
+       AT91_REG         MCI_RCR;       // Receive Counter Register\r
+       AT91_REG         MCI_TPR;       // Transmit Pointer Register\r
+       AT91_REG         MCI_TCR;       // Transmit Counter Register\r
+       AT91_REG         MCI_RNPR;      // Receive Next Pointer Register\r
+       AT91_REG         MCI_RNCR;      // Receive Next Counter Register\r
+       AT91_REG         MCI_TNPR;      // Transmit Next Pointer Register\r
+       AT91_REG         MCI_TNCR;      // Transmit Next Counter Register\r
+       AT91_REG         MCI_PTCR;      // PDC Transfer Control Register\r
+       AT91_REG         MCI_PTSR;      // PDC Transfer Status Register\r
+       AT91_REG         Reserved2[54];         // \r
+       AT91_REG         MCI_FIFO;      // MCI FIFO Aperture Register\r
+} AT91S_MCI, *AT91PS_MCI;\r
+#else\r
+#define MCI_CR          (AT91_CAST(AT91_REG *)         0x00000000) // (MCI_CR) MCI Control Register\r
+#define MCI_MR          (AT91_CAST(AT91_REG *)         0x00000004) // (MCI_MR) MCI Mode Register\r
+#define MCI_DTOR        (AT91_CAST(AT91_REG *)         0x00000008) // (MCI_DTOR) MCI Data Timeout Register\r
+#define MCI_SDCR        (AT91_CAST(AT91_REG *)         0x0000000C) // (MCI_SDCR) MCI SD/SDIO Card Register\r
+#define MCI_ARGR        (AT91_CAST(AT91_REG *)         0x00000010) // (MCI_ARGR) MCI Argument Register\r
+#define MCI_CMDR        (AT91_CAST(AT91_REG *)         0x00000014) // (MCI_CMDR) MCI Command Register\r
+#define MCI_BLKR        (AT91_CAST(AT91_REG *)         0x00000018) // (MCI_BLKR) MCI Block Register\r
+#define MCI_CSTOR       (AT91_CAST(AT91_REG *)         0x0000001C) // (MCI_CSTOR) MCI Completion Signal Timeout Register\r
+#define MCI_RSPR        (AT91_CAST(AT91_REG *)         0x00000020) // (MCI_RSPR) MCI Response Register\r
+#define MCI_RDR         (AT91_CAST(AT91_REG *)         0x00000030) // (MCI_RDR) MCI Receive Data Register\r
+#define MCI_TDR         (AT91_CAST(AT91_REG *)         0x00000034) // (MCI_TDR) MCI Transmit Data Register\r
+#define MCI_SR          (AT91_CAST(AT91_REG *)         0x00000040) // (MCI_SR) MCI Status Register\r
+#define MCI_IER         (AT91_CAST(AT91_REG *)         0x00000044) // (MCI_IER) MCI Interrupt Enable Register\r
+#define MCI_IDR         (AT91_CAST(AT91_REG *)         0x00000048) // (MCI_IDR) MCI Interrupt Disable Register\r
+#define MCI_IMR         (AT91_CAST(AT91_REG *)         0x0000004C) // (MCI_IMR) MCI Interrupt Mask Register\r
+#define MCI_DMA         (AT91_CAST(AT91_REG *)         0x00000050) // (MCI_DMA) MCI DMA Configuration Register\r
+#define MCI_CFG         (AT91_CAST(AT91_REG *)         0x00000054) // (MCI_CFG) MCI Configuration Register\r
+#define MCI_WPCR        (AT91_CAST(AT91_REG *)         0x000000E4) // (MCI_WPCR) MCI Write Protection Control Register\r
+#define MCI_WPSR        (AT91_CAST(AT91_REG *)         0x000000E8) // (MCI_WPSR) MCI Write Protection Status Register\r
+#define MCI_ADDRSIZE    (AT91_CAST(AT91_REG *)         0x000000EC) // (MCI_ADDRSIZE) MCI ADDRSIZE REGISTER \r
+#define MCI_IPNAME1     (AT91_CAST(AT91_REG *)         0x000000F0) // (MCI_IPNAME1) MCI IPNAME1 REGISTER \r
+#define MCI_IPNAME2     (AT91_CAST(AT91_REG *)         0x000000F4) // (MCI_IPNAME2) MCI IPNAME2 REGISTER \r
+#define MCI_FEATURES    (AT91_CAST(AT91_REG *)         0x000000F8) // (MCI_FEATURES) MCI FEATURES REGISTER \r
+#define MCI_VER         (AT91_CAST(AT91_REG *)         0x000000FC) // (MCI_VER) MCI VERSION REGISTER \r
+#define MCI_FIFO        (AT91_CAST(AT91_REG *)         0x00000200) // (MCI_FIFO) MCI FIFO Aperture Register\r
+\r
+#endif\r
+// -------- MCI_CR : (MCI Offset: 0x0) MCI Control Register -------- \r
+#define AT91C_MCI_MCIEN       (0x1 <<  0) // (MCI) Multimedia Interface Enable\r
+#define        AT91C_MCI_MCIEN_0                    (0x0) // (MCI) No effect\r
+#define        AT91C_MCI_MCIEN_1                    (0x1) // (MCI) Enable the MultiMedia Interface if MCIDIS is 0\r
+#define AT91C_MCI_MCIDIS      (0x1 <<  1) // (MCI) Multimedia Interface Disable\r
+#define        AT91C_MCI_MCIDIS_0                    (0x0 <<  1) // (MCI) No effect\r
+#define        AT91C_MCI_MCIDIS_1                    (0x1 <<  1) // (MCI) Disable the MultiMedia Interface\r
+#define AT91C_MCI_PWSEN       (0x1 <<  2) // (MCI) Power Save Mode Enable\r
+#define        AT91C_MCI_PWSEN_0                    (0x0 <<  2) // (MCI) No effect\r
+#define        AT91C_MCI_PWSEN_1                    (0x1 <<  2) // (MCI) Enable the Power-saving mode if PWSDIS is 0.\r
+#define AT91C_MCI_PWSDIS      (0x1 <<  3) // (MCI) Power Save Mode Disable\r
+#define        AT91C_MCI_PWSDIS_0                    (0x0 <<  3) // (MCI) No effect\r
+#define        AT91C_MCI_PWSDIS_1                    (0x1 <<  3) // (MCI) Disable the Power-saving mode.\r
+#define AT91C_MCI_IOWAITEN    (0x1 <<  4) // (MCI) SDIO Read Wait Enable\r
+#define        AT91C_MCI_IOWAITEN_0                    (0x0 <<  4) // (MCI) No effect\r
+#define        AT91C_MCI_IOWAITEN_1                    (0x1 <<  4) // (MCI) Enables the SDIO Read Wait Operation.\r
+#define AT91C_MCI_IOWAITDIS   (0x1 <<  5) // (MCI) SDIO Read Wait Disable\r
+#define        AT91C_MCI_IOWAITDIS_0                    (0x0 <<  5) // (MCI) No effect\r
+#define        AT91C_MCI_IOWAITDIS_1                    (0x1 <<  5) // (MCI) Disables the SDIO Read Wait Operation.\r
+#define AT91C_MCI_SWRST       (0x1 <<  7) // (MCI) MCI Software reset\r
+#define        AT91C_MCI_SWRST_0                    (0x0 <<  7) // (MCI) No effect\r
+#define        AT91C_MCI_SWRST_1                    (0x1 <<  7) // (MCI) Resets the MCI\r
+// -------- MCI_MR : (MCI Offset: 0x4) MCI Mode Register -------- \r
+#define AT91C_MCI_CLKDIV      (0xFF <<  0) // (MCI) Clock Divider\r
+#define AT91C_MCI_PWSDIV      (0x7 <<  8) // (MCI) Power Saving Divider\r
+#define AT91C_MCI_RDPROOF     (0x1 << 11) // (MCI) Read Proof Enable\r
+#define        AT91C_MCI_RDPROOF_DISABLE              (0x0 << 11) // (MCI) Disables Read Proof\r
+#define        AT91C_MCI_RDPROOF_ENABLE               (0x1 << 11) // (MCI) Enables Read Proof\r
+#define AT91C_MCI_WRPROOF     (0x1 << 12) // (MCI) Write Proof Enable\r
+#define        AT91C_MCI_WRPROOF_DISABLE              (0x0 << 12) // (MCI) Disables Write Proof\r
+#define        AT91C_MCI_WRPROOF_ENABLE               (0x1 << 12) // (MCI) Enables Write Proof\r
+#define AT91C_MCI_PDCFBYTE    (0x1 << 13) // (MCI) PDC Force Byte Transfer\r
+#define        AT91C_MCI_PDCFBYTE_DISABLE              (0x0 << 13) // (MCI) Disables PDC Force Byte Transfer\r
+#define        AT91C_MCI_PDCFBYTE_ENABLE               (0x1 << 13) // (MCI) Enables PDC Force Byte Transfer\r
+#define AT91C_MCI_PDCPADV     (0x1 << 14) // (MCI) PDC Padding Value\r
+#define AT91C_MCI_PDCMODE     (0x1 << 15) // (MCI) PDC Oriented Mode\r
+#define        AT91C_MCI_PDCMODE_DISABLE              (0x0 << 15) // (MCI) Disables PDC Transfer\r
+#define        AT91C_MCI_PDCMODE_ENABLE               (0x1 << 15) // (MCI) Enables PDC Transfer\r
+#define AT91C_MCI_BLKLEN      (0xFFFF << 16) // (MCI) Data Block Length\r
+// -------- MCI_DTOR : (MCI Offset: 0x8) MCI Data Timeout Register -------- \r
+#define AT91C_MCI_DTOCYC      (0xF <<  0) // (MCI) Data Timeout Cycle Number\r
+#define AT91C_MCI_DTOMUL      (0x7 <<  4) // (MCI) Data Timeout Multiplier\r
+#define        AT91C_MCI_DTOMUL_1                    (0x0 <<  4) // (MCI) DTOCYC x 1\r
+#define        AT91C_MCI_DTOMUL_16                   (0x1 <<  4) // (MCI) DTOCYC x 16\r
+#define        AT91C_MCI_DTOMUL_128                  (0x2 <<  4) // (MCI) DTOCYC x 128\r
+#define        AT91C_MCI_DTOMUL_256                  (0x3 <<  4) // (MCI) DTOCYC x 256\r
+#define        AT91C_MCI_DTOMUL_1024                 (0x4 <<  4) // (MCI) DTOCYC x 1024\r
+#define        AT91C_MCI_DTOMUL_4096                 (0x5 <<  4) // (MCI) DTOCYC x 4096\r
+#define        AT91C_MCI_DTOMUL_65536                (0x6 <<  4) // (MCI) DTOCYC x 65536\r
+#define        AT91C_MCI_DTOMUL_1048576              (0x7 <<  4) // (MCI) DTOCYC x 1048576\r
+// -------- MCI_SDCR : (MCI Offset: 0xc) MCI SD Card Register -------- \r
+#define AT91C_MCI_SCDSEL      (0x3 <<  0) // (MCI) SD Card/SDIO Selector\r
+#define        AT91C_MCI_SCDSEL_SLOTA                (0x0) // (MCI) Slot A selected\r
+#define        AT91C_MCI_SCDSEL_SLOTB                (0x1) // (MCI) Slot B selected\r
+#define        AT91C_MCI_SCDSEL_SLOTC                (0x2) // (MCI) Slot C selected\r
+#define        AT91C_MCI_SCDSEL_SLOTD                (0x3) // (MCI) Slot D selected\r
+#define AT91C_MCI_SCDBUS      (0x3 <<  6) // (MCI) SDCard/SDIO Bus Width\r
+#define        AT91C_MCI_SCDBUS_1BIT                 (0x0 <<  6) // (MCI) 1-bit data bus\r
+#define        AT91C_MCI_SCDBUS_4BITS                (0x2 <<  6) // (MCI) 4-bits data bus\r
+#define        AT91C_MCI_SCDBUS_8BITS                (0x3 <<  6) // (MCI) 8-bits data bus\r
+// -------- MCI_CMDR : (MCI Offset: 0x14) MCI Command Register -------- \r
+#define AT91C_MCI_CMDNB       (0x3F <<  0) // (MCI) Command Number\r
+#define AT91C_MCI_RSPTYP      (0x3 <<  6) // (MCI) Response Type\r
+#define        AT91C_MCI_RSPTYP_NO                   (0x0 <<  6) // (MCI) No response\r
+#define        AT91C_MCI_RSPTYP_48                   (0x1 <<  6) // (MCI) 48-bit response\r
+#define        AT91C_MCI_RSPTYP_136                  (0x2 <<  6) // (MCI) 136-bit response\r
+#define        AT91C_MCI_RSPTYP_R1B                  (0x3 <<  6) // (MCI) R1b response\r
+#define AT91C_MCI_SPCMD       (0x7 <<  8) // (MCI) Special CMD\r
+#define        AT91C_MCI_SPCMD_NONE                 (0x0 <<  8) // (MCI) Not a special CMD\r
+#define        AT91C_MCI_SPCMD_INIT                 (0x1 <<  8) // (MCI) Initialization CMD\r
+#define        AT91C_MCI_SPCMD_SYNC                 (0x2 <<  8) // (MCI) Synchronized CMD\r
+#define        AT91C_MCI_SPCMD_CE_ATA               (0x3 <<  8) // (MCI) CE-ATA Completion Signal disable CMD\r
+#define        AT91C_MCI_SPCMD_IT_CMD               (0x4 <<  8) // (MCI) Interrupt command\r
+#define        AT91C_MCI_SPCMD_IT_REP               (0x5 <<  8) // (MCI) Interrupt response\r
+#define     AT91C_MCI_SPCMD_BOOTREQ              (0x6 <<  8) // (MCI) Boot Operation Request\r
+#define     AT91C_MCI_SPCMD_BOOTEND              (0x7 <<  8) // (MCI) End Boot Operation\r
+#define AT91C_MCI_OPDCMD      (0x1 << 11) // (MCI) Open Drain Command\r
+#define        AT91C_MCI_OPDCMD_PUSHPULL             (0x0 << 11) // (MCI) Push/pull command\r
+#define        AT91C_MCI_OPDCMD_OPENDRAIN            (0x1 << 11) // (MCI) Open drain command\r
+#define AT91C_MCI_MAXLAT      (0x1 << 12) // (MCI) Maximum Latency for Command to respond\r
+#define        AT91C_MCI_MAXLAT_5                    (0x0 << 12) // (MCI) 5 cycles maximum latency\r
+#define        AT91C_MCI_MAXLAT_64                   (0x1 << 12) // (MCI) 64 cycles maximum latency\r
+#define AT91C_MCI_TRCMD       (0x3 << 16) // (MCI) Transfer CMD\r
+#define        AT91C_MCI_TRCMD_NO                   (0x0 << 16) // (MCI) No transfer\r
+#define        AT91C_MCI_TRCMD_START                (0x1 << 16) // (MCI) Start transfer\r
+#define        AT91C_MCI_TRCMD_STOP                 (0x2 << 16) // (MCI) Stop transfer\r
+#define AT91C_MCI_TRDIR       (0x1 << 18) // (MCI) Transfer Direction\r
+#define        AT91C_MCI_TRDIR_WRITE                (0x0 << 18) // (MCI) Write\r
+#define        AT91C_MCI_TRDIR_READ                 (0x1 << 18) // (MCI) Read\r
+#define AT91C_MCI_TRTYP       (0x7 << 19) // (MCI) Transfer Type\r
+#define        AT91C_MCI_TRTYP_BLOCK                (0x0 << 19) // (MCI) MMC/SDCard Single Block Transfer type\r
+#define        AT91C_MCI_TRTYP_MULTIPLE             (0x1 << 19) // (MCI) MMC/SDCard Multiple Block transfer type\r
+#define        AT91C_MCI_TRTYP_STREAM               (0x2 << 19) // (MCI) MMC Stream transfer type\r
+#define        AT91C_MCI_TRTYP_SDIO_BYTE            (0x4 << 19) // (MCI) SDIO Byte transfer type\r
+#define        AT91C_MCI_TRTYP_SDIO_BLOCK           (0x5 << 19) // (MCI) SDIO Block transfer type\r
+#define AT91C_MCI_IOSPCMD     (0x3 << 24) // (MCI) SDIO Special Command\r
+#define        AT91C_MCI_IOSPCMD_NONE                 (0x0 << 24) // (MCI) NOT a special command\r
+#define        AT91C_MCI_IOSPCMD_SUSPEND              (0x1 << 24) // (MCI) SDIO Suspend Command\r
+#define        AT91C_MCI_IOSPCMD_RESUME               (0x2 << 24) // (MCI) SDIO Resume Command\r
+#define AT91C_MCI_ATACS       (0x1 << 26) // (MCI) ATA with command completion signal\r
+#define        AT91C_MCI_ATACS_NORMAL               (0x0 << 26) // (MCI) normal operation mode\r
+#define        AT91C_MCI_ATACS_COMPLETION           (0x1 << 26) // (MCI) completion signal is expected within MCI_CSTOR\r
+#define AT91C_MCI_BOOTACK     (0x1 << 27) // (MCI) Boot Operation Acknowledge\r
+#define     AT91C_MCI_BOOTACK_DISABLE           (0x0 << 27) // (MCI) Boot Operation Acknowledge Disabled\r
+#define     AT91C_MCI_BOOTACK_ENABLE            (0x1 << 27) // (MCI) Boot Operation Acknowledge Enabled\r
+// -------- MCI_BLKR : (MCI Offset: 0x18) MCI Block Register -------- \r
+#define AT91C_MCI_BCNT        (0xFFFF <<  0) // (MCI) MMC/SDIO Block Count / SDIO Byte Count\r
+// -------- MCI_CSTOR : (MCI Offset: 0x1c) MCI Completion Signal Timeout Register -------- \r
+#define AT91C_MCI_CSTOCYC     (0xF <<  0) // (MCI) Completion Signal Timeout Cycle Number\r
+#define AT91C_MCI_CSTOMUL     (0x7 <<  4) // (MCI) Completion Signal Timeout Multiplier\r
+#define        AT91C_MCI_CSTOMUL_1                    (0x0 <<  4) // (MCI) CSTOCYC x 1\r
+#define        AT91C_MCI_CSTOMUL_16                   (0x1 <<  4) // (MCI) CSTOCYC x  16\r
+#define        AT91C_MCI_CSTOMUL_128                  (0x2 <<  4) // (MCI) CSTOCYC x  128\r
+#define        AT91C_MCI_CSTOMUL_256                  (0x3 <<  4) // (MCI) CSTOCYC x  256\r
+#define        AT91C_MCI_CSTOMUL_1024                 (0x4 <<  4) // (MCI) CSTOCYC x  1024\r
+#define        AT91C_MCI_CSTOMUL_4096                 (0x5 <<  4) // (MCI) CSTOCYC x  4096\r
+#define        AT91C_MCI_CSTOMUL_65536                (0x6 <<  4) // (MCI) CSTOCYC x  65536\r
+#define        AT91C_MCI_CSTOMUL_1048576              (0x7 <<  4) // (MCI) CSTOCYC x  1048576\r
+// -------- MCI_SR : (MCI Offset: 0x40) MCI Status Register -------- \r
+#define AT91C_MCI_CMDRDY      (0x1 <<  0) // (MCI) Command Ready flag\r
+#define AT91C_MCI_RXRDY       (0x1 <<  1) // (MCI) RX Ready flag\r
+#define AT91C_MCI_TXRDY       (0x1 <<  2) // (MCI) TX Ready flag\r
+#define AT91C_MCI_BLKE        (0x1 <<  3) // (MCI) Data Block Transfer Ended flag\r
+#define AT91C_MCI_DTIP        (0x1 <<  4) // (MCI) Data Transfer in Progress flag\r
+#define AT91C_MCI_NOTBUSY     (0x1 <<  5) // (MCI) Data Line Not Busy flag\r
+#define AT91C_MCI_ENDRX       (0x1 <<  6) // (MCI) End of RX Buffer flag\r
+#define AT91C_MCI_ENDTX       (0x1 <<  7) // (MCI) End of TX Buffer flag\r
+#define AT91C_MCI_SDIOIRQA    (0x1 <<  8) // (MCI) SDIO Interrupt for Slot A\r
+#define AT91C_MCI_SDIOIRQB    (0x1 <<  9) // (MCI) SDIO Interrupt for Slot B\r
+#define AT91C_MCI_SDIOIRQC    (0x1 << 10) // (MCI) SDIO Interrupt for Slot C\r
+#define AT91C_MCI_SDIOIRQD    (0x1 << 11) // (MCI) SDIO Interrupt for Slot D\r
+#define AT91C_MCI_SDIOWAIT    (0x1 << 12) // (MCI) SDIO Read Wait operation flag\r
+#define AT91C_MCI_CSRCV       (0x1 << 13) // (MCI) CE-ATA Completion Signal flag\r
+#define AT91C_MCI_RXBUFF      (0x1 << 14) // (MCI) RX Buffer Full flag\r
+#define AT91C_MCI_TXBUFE      (0x1 << 15) // (MCI) TX Buffer Empty flag\r
+#define AT91C_MCI_RINDE       (0x1 << 16) // (MCI) Response Index Error flag\r
+#define AT91C_MCI_RDIRE       (0x1 << 17) // (MCI) Response Direction Error flag\r
+#define AT91C_MCI_RCRCE       (0x1 << 18) // (MCI) Response CRC Error flag\r
+#define AT91C_MCI_RENDE       (0x1 << 19) // (MCI) Response End Bit Error flag\r
+#define AT91C_MCI_RTOE        (0x1 << 20) // (MCI) Response Time-out Error flag\r
+#define AT91C_MCI_DCRCE       (0x1 << 21) // (MCI) data CRC Error flag\r
+#define AT91C_MCI_DTOE        (0x1 << 22) // (MCI) Data timeout Error flag\r
+#define AT91C_MCI_CSTOE       (0x1 << 23) // (MCI) Completion Signal timeout Error flag\r
+#define AT91C_MCI_BLKOVRE     (0x1 << 24) // (MCI) DMA Block Overrun Error flag\r
+#define AT91C_MCI_DMADONE     (0x1 << 25) // (MCI) DMA Transfer Done flag\r
+#define AT91C_MCI_FIFOEMPTY   (0x1 << 26) // (MCI) FIFO Empty flag\r
+#define AT91C_MCI_XFRDONE     (0x1 << 27) // (MCI) Transfer Done flag\r
+#define AT91C_MCI_OVRE        (0x1 << 30) // (MCI) Overrun flag\r
+#define AT91C_MCI_UNRE        (0x1 << 31) // (MCI) Underrun flag\r
+// -------- MCI_IER : (MCI Offset: 0x44) MCI Interrupt Enable Register -------- \r
+// -------- MCI_IDR : (MCI Offset: 0x48) MCI Interrupt Disable Register -------- \r
+// -------- MCI_IMR : (MCI Offset: 0x4c) MCI Interrupt Mask Register -------- \r
+// -------- MCI_DMA : (MCI Offset: 0x50) MCI DMA Configuration Register -------- \r
+#define AT91C_MCI_OFFSET      (0x3 <<  0) // (MCI) DMA Write Buffer Offset\r
+#define AT91C_MCI_CHKSIZE     (0x7 <<  4) // (MCI) DMA Channel Read/Write Chunk Size\r
+#define        AT91C_MCI_CHKSIZE_1                    (0x0 <<  4) // (MCI) Number of data transferred is 1\r
+#define        AT91C_MCI_CHKSIZE_4                    (0x1 <<  4) // (MCI) Number of data transferred is 4\r
+#define        AT91C_MCI_CHKSIZE_8                    (0x2 <<  4) // (MCI) Number of data transferred is 8\r
+#define        AT91C_MCI_CHKSIZE_16                   (0x3 <<  4) // (MCI) Number of data transferred is 16\r
+#define        AT91C_MCI_CHKSIZE_32                   (0x4 <<  4) // (MCI) Number of data transferred is 32\r
+#define AT91C_MCI_DMAEN       (0x1 <<  8) // (MCI) DMA Hardware Handshaking Enable\r
+#define        AT91C_MCI_DMAEN_DISABLE              (0x0 <<  8) // (MCI) DMA interface is disabled\r
+#define        AT91C_MCI_DMAEN_ENABLE               (0x1 <<  8) // (MCI) DMA interface is enabled\r
+// -------- MCI_CFG : (MCI Offset: 0x54) MCI Configuration Register -------- \r
+#define AT91C_MCI_FIFOMODE    (0x1 <<  0) // (MCI) MCI Internal FIFO Control Mode\r
+#define        AT91C_MCI_FIFOMODE_AMOUNTDATA           (0x0) // (MCI) A write transfer starts when a sufficient amount of datas is written into the FIFO\r
+#define        AT91C_MCI_FIFOMODE_ONEDATA              (0x1) // (MCI) A write transfer starts as soon as one data is written into the FIFO\r
+#define AT91C_MCI_FERRCTRL    (0x1 <<  4) // (MCI) Flow Error Flag Reset Control Mode\r
+#define        AT91C_MCI_FERRCTRL_RWCMD                (0x0 <<  4) // (MCI) When an underflow/overflow condition flag is set, a new Write/Read command is needed to reset the flag\r
+#define        AT91C_MCI_FERRCTRL_READSR               (0x1 <<  4) // (MCI) When an underflow/overflow condition flag is set, a read status resets the flag\r
+#define AT91C_MCI_HSMODE      (0x1 <<  8) // (MCI) High Speed Mode\r
+#define        AT91C_MCI_HSMODE_DISABLE              (0x0 <<  8) // (MCI) Default Bus Timing Mode\r
+#define        AT91C_MCI_HSMODE_ENABLE               (0x1 <<  8) // (MCI) High Speed Mode\r
+#define AT91C_MCI_LSYNC       (0x1 << 12) // (MCI) Synchronize on last block\r
+#define        AT91C_MCI_LSYNC_CURRENT              (0x0 << 12) // (MCI) Pending command sent at end of current data block\r
+#define        AT91C_MCI_LSYNC_INFINITE             (0x1 << 12) // (MCI) Pending command sent at end of block transfer when transfer length is not infinite\r
+// -------- MCI_WPCR : (MCI Offset: 0xe4) Write Protection Control Register -------- \r
+#define AT91C_MCI_WP_EN       (0x1 <<  0) // (MCI) Write Protection Enable\r
+#define        AT91C_MCI_WP_EN_DISABLE              (0x0) // (MCI) Write Operation is disabled (if WP_KEY corresponds)\r
+#define        AT91C_MCI_WP_EN_ENABLE               (0x1) // (MCI) Write Operation is enabled (if WP_KEY corresponds)\r
+#define AT91C_MCI_WP_KEY      (0xFFFFFF <<  8) // (MCI) Write Protection Key\r
+// -------- MCI_WPSR : (MCI Offset: 0xe8) Write Protection Status Register -------- \r
+#define AT91C_MCI_WP_VS       (0xF <<  0) // (MCI) Write Protection Violation Status\r
+#define        AT91C_MCI_WP_VS_NO_VIOLATION         (0x0) // (MCI) No Write Protection Violation detected since last read\r
+#define        AT91C_MCI_WP_VS_ON_WRITE             (0x1) // (MCI) Write Protection Violation detected since last read\r
+#define        AT91C_MCI_WP_VS_ON_RESET             (0x2) // (MCI) Software Reset Violation detected since last read\r
+#define        AT91C_MCI_WP_VS_ON_BOTH              (0x3) // (MCI) Write Protection and Software Reset Violation detected since last read\r
+#define AT91C_MCI_WP_VSRC     (0xF <<  8) // (MCI) Write Protection Violation Source\r
+#define        AT91C_MCI_WP_VSRC_NO_VIOLATION         (0x0 <<  8) // (MCI) No Write Protection Violation detected since last read\r
+#define        AT91C_MCI_WP_VSRC_MCI_MR               (0x1 <<  8) // (MCI) Write Protection Violation detected on MCI_MR since last read\r
+#define        AT91C_MCI_WP_VSRC_MCI_DTOR             (0x2 <<  8) // (MCI) Write Protection Violation detected on MCI_DTOR since last read\r
+#define        AT91C_MCI_WP_VSRC_MCI_SDCR             (0x3 <<  8) // (MCI) Write Protection Violation detected on MCI_SDCR since last read\r
+#define        AT91C_MCI_WP_VSRC_MCI_CSTOR            (0x4 <<  8) // (MCI) Write Protection Violation detected on MCI_CSTOR since last read\r
+#define        AT91C_MCI_WP_VSRC_MCI_DMA              (0x5 <<  8) // (MCI) Write Protection Violation detected on MCI_DMA since last read\r
+#define        AT91C_MCI_WP_VSRC_MCI_CFG              (0x6 <<  8) // (MCI) Write Protection Violation detected on MCI_CFG since last read\r
+#define        AT91C_MCI_WP_VSRC_MCI_DEL              (0x7 <<  8) // (MCI) Write Protection Violation detected on MCI_DEL since last read\r
+// -------- MCI_VER : (MCI Offset: 0xfc)  VERSION  Register -------- \r
+#define AT91C_MCI_VER         (0xF <<  0) // (MCI)  VERSION  Register\r
+\r
+// *****************************************************************************\r
+//              SOFTWARE API DEFINITION  FOR Two-wire Interface\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_TWI {\r
+       AT91_REG         TWI_CR;        // Control Register\r
+       AT91_REG         TWI_MMR;       // Master Mode Register\r
+       AT91_REG         TWI_SMR;       // Slave Mode Register\r
+       AT91_REG         TWI_IADR;      // Internal Address Register\r
+       AT91_REG         TWI_CWGR;      // Clock Waveform Generator Register\r
+       AT91_REG         Reserved0[3];  // \r
+       AT91_REG         TWI_SR;        // Status Register\r
+       AT91_REG         TWI_IER;       // Interrupt Enable Register\r
+       AT91_REG         TWI_IDR;       // Interrupt Disable Register\r
+       AT91_REG         TWI_IMR;       // Interrupt Mask Register\r
+       AT91_REG         TWI_RHR;       // Receive Holding Register\r
+       AT91_REG         TWI_THR;       // Transmit Holding Register\r
+       AT91_REG         Reserved1[45];         // \r
+       AT91_REG         TWI_ADDRSIZE;  // TWI ADDRSIZE REGISTER \r
+       AT91_REG         TWI_IPNAME1;   // TWI IPNAME1 REGISTER \r
+       AT91_REG         TWI_IPNAME2;   // TWI IPNAME2 REGISTER \r
+       AT91_REG         TWI_FEATURES;  // TWI FEATURES REGISTER \r
+       AT91_REG         TWI_VER;       // Version Register\r
+       AT91_REG         TWI_RPR;       // Receive Pointer Register\r
+       AT91_REG         TWI_RCR;       // Receive Counter Register\r
+       AT91_REG         TWI_TPR;       // Transmit Pointer Register\r
+       AT91_REG         TWI_TCR;       // Transmit Counter Register\r
+       AT91_REG         TWI_RNPR;      // Receive Next Pointer Register\r
+       AT91_REG         TWI_RNCR;      // Receive Next Counter Register\r
+       AT91_REG         TWI_TNPR;      // Transmit Next Pointer Register\r
+       AT91_REG         TWI_TNCR;      // Transmit Next Counter Register\r
+       AT91_REG         TWI_PTCR;      // PDC Transfer Control Register\r
+       AT91_REG         TWI_PTSR;      // PDC Transfer Status Register\r
+} AT91S_TWI, *AT91PS_TWI;\r
+#else\r
+#define TWI_CR          (AT91_CAST(AT91_REG *)         0x00000000) // (TWI_CR) Control Register\r
+#define TWI_MMR         (AT91_CAST(AT91_REG *)         0x00000004) // (TWI_MMR) Master Mode Register\r
+#define TWI_SMR         (AT91_CAST(AT91_REG *)         0x00000008) // (TWI_SMR) Slave Mode Register\r
+#define TWI_IADR        (AT91_CAST(AT91_REG *)         0x0000000C) // (TWI_IADR) Internal Address Register\r
+#define TWI_CWGR        (AT91_CAST(AT91_REG *)         0x00000010) // (TWI_CWGR) Clock Waveform Generator Register\r
+#define TWI_SR          (AT91_CAST(AT91_REG *)         0x00000020) // (TWI_SR) Status Register\r
+#define TWI_IER         (AT91_CAST(AT91_REG *)         0x00000024) // (TWI_IER) Interrupt Enable Register\r
+#define TWI_IDR         (AT91_CAST(AT91_REG *)         0x00000028) // (TWI_IDR) Interrupt Disable Register\r
+#define TWI_IMR         (AT91_CAST(AT91_REG *)         0x0000002C) // (TWI_IMR) Interrupt Mask Register\r
+#define TWI_RHR         (AT91_CAST(AT91_REG *)         0x00000030) // (TWI_RHR) Receive Holding Register\r
+#define TWI_THR         (AT91_CAST(AT91_REG *)         0x00000034) // (TWI_THR) Transmit Holding Register\r
+#define TWI_ADDRSIZE    (AT91_CAST(AT91_REG *)         0x000000EC) // (TWI_ADDRSIZE) TWI ADDRSIZE REGISTER \r
+#define TWI_IPNAME1     (AT91_CAST(AT91_REG *)         0x000000F0) // (TWI_IPNAME1) TWI IPNAME1 REGISTER \r
+#define TWI_IPNAME2     (AT91_CAST(AT91_REG *)         0x000000F4) // (TWI_IPNAME2) TWI IPNAME2 REGISTER \r
+#define TWI_FEATURES    (AT91_CAST(AT91_REG *)         0x000000F8) // (TWI_FEATURES) TWI FEATURES REGISTER \r
+#define TWI_VER         (AT91_CAST(AT91_REG *)         0x000000FC) // (TWI_VER) Version Register\r
+\r
+#endif\r
+// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- \r
+#define AT91C_TWI_START       (0x1 <<  0) // (TWI) Send a START Condition\r
+#define AT91C_TWI_STOP        (0x1 <<  1) // (TWI) Send a STOP Condition\r
+#define AT91C_TWI_MSEN        (0x1 <<  2) // (TWI) TWI Master Transfer Enabled\r
+#define AT91C_TWI_MSDIS       (0x1 <<  3) // (TWI) TWI Master Transfer Disabled\r
+#define AT91C_TWI_SVEN        (0x1 <<  4) // (TWI) TWI Slave mode Enabled\r
+#define AT91C_TWI_SVDIS       (0x1 <<  5) // (TWI) TWI Slave mode Disabled\r
+#define AT91C_TWI_SWRST       (0x1 <<  7) // (TWI) Software Reset\r
+// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- \r
+#define AT91C_TWI_IADRSZ      (0x3 <<  8) // (TWI) Internal Device Address Size\r
+#define        AT91C_TWI_IADRSZ_NO                   (0x0 <<  8) // (TWI) No internal device address\r
+#define        AT91C_TWI_IADRSZ_1_BYTE               (0x1 <<  8) // (TWI) One-byte internal device address\r
+#define        AT91C_TWI_IADRSZ_2_BYTE               (0x2 <<  8) // (TWI) Two-byte internal device address\r
+#define        AT91C_TWI_IADRSZ_3_BYTE               (0x3 <<  8) // (TWI) Three-byte internal device address\r
+#define AT91C_TWI_MREAD       (0x1 << 12) // (TWI) Master Read Direction\r
+#define AT91C_TWI_DADR        (0x7F << 16) // (TWI) Device Address\r
+// -------- TWI_SMR : (TWI Offset: 0x8) TWI Slave Mode Register -------- \r
+#define AT91C_TWI_SADR        (0x7F << 16) // (TWI) Slave Address\r
+// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- \r
+#define AT91C_TWI_CLDIV       (0xFF <<  0) // (TWI) Clock Low Divider\r
+#define AT91C_TWI_CHDIV       (0xFF <<  8) // (TWI) Clock High Divider\r
+#define AT91C_TWI_CKDIV       (0x7 << 16) // (TWI) Clock Divider\r
+// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- \r
+#define AT91C_TWI_TXCOMP_SLAVE (0x1 <<  0) // (TWI) Transmission Completed\r
+#define AT91C_TWI_TXCOMP_MASTER (0x1 <<  0) // (TWI) Transmission Completed\r
+#define AT91C_TWI_RXRDY       (0x1 <<  1) // (TWI) Receive holding register ReaDY\r
+#define AT91C_TWI_TXRDY_MASTER (0x1 <<  2) // (TWI) Transmit holding register ReaDY\r
+#define AT91C_TWI_TXRDY_SLAVE (0x1 <<  2) // (TWI) Transmit holding register ReaDY\r
+#define AT91C_TWI_SVREAD      (0x1 <<  3) // (TWI) Slave READ (used only in Slave mode)\r
+#define AT91C_TWI_SVACC       (0x1 <<  4) // (TWI) Slave ACCess (used only in Slave mode)\r
+#define AT91C_TWI_GACC        (0x1 <<  5) // (TWI) General Call ACcess (used only in Slave mode)\r
+#define AT91C_TWI_OVRE        (0x1 <<  6) // (TWI) Overrun Error (used only in Master and Multi-master mode)\r
+#define AT91C_TWI_NACK_SLAVE  (0x1 <<  8) // (TWI) Not Acknowledged\r
+#define AT91C_TWI_NACK_MASTER (0x1 <<  8) // (TWI) Not Acknowledged\r
+#define AT91C_TWI_ARBLST_MULTI_MASTER (0x1 <<  9) // (TWI) Arbitration Lost (used only in Multimaster mode)\r
+#define AT91C_TWI_SCLWS       (0x1 << 10) // (TWI) Clock Wait State (used only in Slave mode)\r
+#define AT91C_TWI_EOSACC      (0x1 << 11) // (TWI) End Of Slave ACCess (used only in Slave mode)\r
+#define AT91C_TWI_ENDRX       (0x1 << 12) // (TWI) End of Receiver Transfer\r
+#define AT91C_TWI_ENDTX       (0x1 << 13) // (TWI) End of Receiver Transfer\r
+#define AT91C_TWI_RXBUFF      (0x1 << 14) // (TWI) RXBUFF Interrupt\r
+#define AT91C_TWI_TXBUFE      (0x1 << 15) // (TWI) TXBUFE Interrupt\r
+// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- \r
+// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- \r
+// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- \r
+\r
+// *****************************************************************************\r
+//              SOFTWARE API DEFINITION  FOR Usart\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_USART {\r
+       AT91_REG         US_CR;         // Control Register\r
+       AT91_REG         US_MR;         // Mode Register\r
+       AT91_REG         US_IER;        // Interrupt Enable Register\r
+       AT91_REG         US_IDR;        // Interrupt Disable Register\r
+       AT91_REG         US_IMR;        // Interrupt Mask Register\r
+       AT91_REG         US_CSR;        // Channel Status Register\r
+       AT91_REG         US_RHR;        // Receiver Holding Register\r
+       AT91_REG         US_THR;        // Transmitter Holding Register\r
+       AT91_REG         US_BRGR;       // Baud Rate Generator Register\r
+       AT91_REG         US_RTOR;       // Receiver Time-out Register\r
+       AT91_REG         US_TTGR;       // Transmitter Time-guard Register\r
+       AT91_REG         Reserved0[5];  // \r
+       AT91_REG         US_FIDI;       // FI_DI_Ratio Register\r
+       AT91_REG         US_NER;        // Nb Errors Register\r
+       AT91_REG         Reserved1[1];  // \r
+       AT91_REG         US_IF;         // IRDA_FILTER Register\r
+       AT91_REG         US_MAN;        // Manchester Encoder Decoder Register\r
+       AT91_REG         Reserved2[38];         // \r
+       AT91_REG         US_ADDRSIZE;   // US ADDRSIZE REGISTER \r
+       AT91_REG         US_IPNAME1;    // US IPNAME1 REGISTER \r
+       AT91_REG         US_IPNAME2;    // US IPNAME2 REGISTER \r
+       AT91_REG         US_FEATURES;   // US FEATURES REGISTER \r
+       AT91_REG         US_VER;        // VERSION Register\r
+       AT91_REG         US_RPR;        // Receive Pointer Register\r
+       AT91_REG         US_RCR;        // Receive Counter Register\r
+       AT91_REG         US_TPR;        // Transmit Pointer Register\r
+       AT91_REG         US_TCR;        // Transmit Counter Register\r
+       AT91_REG         US_RNPR;       // Receive Next Pointer Register\r
+       AT91_REG         US_RNCR;       // Receive Next Counter Register\r
+       AT91_REG         US_TNPR;       // Transmit Next Pointer Register\r
+       AT91_REG         US_TNCR;       // Transmit Next Counter Register\r
+       AT91_REG         US_PTCR;       // PDC Transfer Control Register\r
+       AT91_REG         US_PTSR;       // PDC Transfer Status Register\r
+} AT91S_USART, *AT91PS_USART;\r
+#else\r
+#define US_CR           (AT91_CAST(AT91_REG *)         0x00000000) // (US_CR) Control Register\r
+#define US_MR           (AT91_CAST(AT91_REG *)         0x00000004) // (US_MR) Mode Register\r
+#define US_IER          (AT91_CAST(AT91_REG *)         0x00000008) // (US_IER) Interrupt Enable Register\r
+#define US_IDR          (AT91_CAST(AT91_REG *)         0x0000000C) // (US_IDR) Interrupt Disable Register\r
+#define US_IMR          (AT91_CAST(AT91_REG *)         0x00000010) // (US_IMR) Interrupt Mask Register\r
+#define US_CSR          (AT91_CAST(AT91_REG *)         0x00000014) // (US_CSR) Channel Status Register\r
+#define US_RHR          (AT91_CAST(AT91_REG *)         0x00000018) // (US_RHR) Receiver Holding Register\r
+#define US_THR          (AT91_CAST(AT91_REG *)         0x0000001C) // (US_THR) Transmitter Holding Register\r
+#define US_BRGR         (AT91_CAST(AT91_REG *)         0x00000020) // (US_BRGR) Baud Rate Generator Register\r
+#define US_RTOR         (AT91_CAST(AT91_REG *)         0x00000024) // (US_RTOR) Receiver Time-out Register\r
+#define US_TTGR         (AT91_CAST(AT91_REG *)         0x00000028) // (US_TTGR) Transmitter Time-guard Register\r
+#define US_FIDI         (AT91_CAST(AT91_REG *)         0x00000040) // (US_FIDI) FI_DI_Ratio Register\r
+#define US_NER          (AT91_CAST(AT91_REG *)         0x00000044) // (US_NER) Nb Errors Register\r
+#define US_IF           (AT91_CAST(AT91_REG *)         0x0000004C) // (US_IF) IRDA_FILTER Register\r
+#define US_MAN          (AT91_CAST(AT91_REG *)         0x00000050) // (US_MAN) Manchester Encoder Decoder Register\r
+#define US_ADDRSIZE     (AT91_CAST(AT91_REG *)         0x000000EC) // (US_ADDRSIZE) US ADDRSIZE REGISTER \r
+#define US_IPNAME1      (AT91_CAST(AT91_REG *)         0x000000F0) // (US_IPNAME1) US IPNAME1 REGISTER \r
+#define US_IPNAME2      (AT91_CAST(AT91_REG *)         0x000000F4) // (US_IPNAME2) US IPNAME2 REGISTER \r
+#define US_FEATURES     (AT91_CAST(AT91_REG *)         0x000000F8) // (US_FEATURES) US FEATURES REGISTER \r
+#define US_VER          (AT91_CAST(AT91_REG *)         0x000000FC) // (US_VER) VERSION Register\r
+\r
+#endif\r
+// -------- US_CR : (USART Offset: 0x0)  Control Register -------- \r
+#define AT91C_US_STTBRK       (0x1 <<  9) // (USART) Start Break\r
+#define AT91C_US_STPBRK       (0x1 << 10) // (USART) Stop Break\r
+#define AT91C_US_STTTO        (0x1 << 11) // (USART) Start Time-out\r
+#define AT91C_US_SENDA        (0x1 << 12) // (USART) Send Address\r
+#define AT91C_US_RSTIT        (0x1 << 13) // (USART) Reset Iterations\r
+#define AT91C_US_RSTNACK      (0x1 << 14) // (USART) Reset Non Acknowledge\r
+#define AT91C_US_RETTO        (0x1 << 15) // (USART) Rearm Time-out\r
+#define AT91C_US_DTREN        (0x1 << 16) // (USART) Data Terminal ready Enable\r
+#define AT91C_US_DTRDIS       (0x1 << 17) // (USART) Data Terminal ready Disable\r
+#define AT91C_US_RTSEN        (0x1 << 18) // (USART) Request to Send enable\r
+#define AT91C_US_RTSDIS       (0x1 << 19) // (USART) Request to Send Disable\r
+// -------- US_MR : (USART Offset: 0x4)  Mode Register -------- \r
+#define AT91C_US_USMODE       (0xF <<  0) // (USART) Usart mode\r
+#define        AT91C_US_USMODE_NORMAL               (0x0) // (USART) Normal\r
+#define        AT91C_US_USMODE_RS485                (0x1) // (USART) RS485\r
+#define        AT91C_US_USMODE_HWHSH                (0x2) // (USART) Hardware Handshaking\r
+#define        AT91C_US_USMODE_MODEM                (0x3) // (USART) Modem\r
+#define        AT91C_US_USMODE_ISO7816_0            (0x4) // (USART) ISO7816 protocol: T = 0\r
+#define        AT91C_US_USMODE_ISO7816_1            (0x6) // (USART) ISO7816 protocol: T = 1\r
+#define        AT91C_US_USMODE_IRDA                 (0x8) // (USART) IrDA\r
+#define        AT91C_US_USMODE_SWHSH                (0xC) // (USART) Software Handshaking\r
+#define AT91C_US_CLKS         (0x3 <<  4) // (USART) Clock Selection (Baud Rate generator Input Clock\r
+#define        AT91C_US_CLKS_CLOCK                (0x0 <<  4) // (USART) Clock\r
+#define        AT91C_US_CLKS_FDIV1                (0x1 <<  4) // (USART) fdiv1\r
+#define        AT91C_US_CLKS_SLOW                 (0x2 <<  4) // (USART) slow_clock (ARM)\r
+#define        AT91C_US_CLKS_EXT                  (0x3 <<  4) // (USART) External (SCK)\r
+#define AT91C_US_CHRL         (0x3 <<  6) // (USART) Clock Selection (Baud Rate generator Input Clock\r
+#define        AT91C_US_CHRL_5_BITS               (0x0 <<  6) // (USART) Character Length: 5 bits\r
+#define        AT91C_US_CHRL_6_BITS               (0x1 <<  6) // (USART) Character Length: 6 bits\r
+#define        AT91C_US_CHRL_7_BITS               (0x2 <<  6) // (USART) Character Length: 7 bits\r
+#define        AT91C_US_CHRL_8_BITS               (0x3 <<  6) // (USART) Character Length: 8 bits\r
+#define AT91C_US_SYNC         (0x1 <<  8) // (USART) Synchronous Mode Select\r
+#define AT91C_US_NBSTOP       (0x3 << 12) // (USART) Number of Stop bits\r
+#define        AT91C_US_NBSTOP_1_BIT                (0x0 << 12) // (USART) 1 stop bit\r
+#define        AT91C_US_NBSTOP_15_BIT               (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits\r
+#define        AT91C_US_NBSTOP_2_BIT                (0x2 << 12) // (USART) 2 stop bits\r
+#define AT91C_US_MSBF         (0x1 << 16) // (USART) Bit Order\r
+#define AT91C_US_MODE9        (0x1 << 17) // (USART) 9-bit Character length\r
+#define AT91C_US_CKLO         (0x1 << 18) // (USART) Clock Output Select\r
+#define AT91C_US_OVER         (0x1 << 19) // (USART) Over Sampling Mode\r
+#define AT91C_US_INACK        (0x1 << 20) // (USART) Inhibit Non Acknowledge\r
+#define AT91C_US_DSNACK       (0x1 << 21) // (USART) Disable Successive NACK\r
+#define AT91C_US_VAR_SYNC     (0x1 << 22) // (USART) Variable synchronization of command/data sync Start Frame Delimiter\r
+#define AT91C_US_MAX_ITER     (0x1 << 24) // (USART) Number of Repetitions\r
+#define AT91C_US_FILTER       (0x1 << 28) // (USART) Receive Line Filter\r
+#define AT91C_US_MANMODE      (0x1 << 29) // (USART) Manchester Encoder/Decoder Enable\r
+#define AT91C_US_MODSYNC      (0x1 << 30) // (USART) Manchester Synchronization mode\r
+#define AT91C_US_ONEBIT       (0x1 << 31) // (USART) Start Frame Delimiter selector\r
+// -------- US_IER : (USART Offset: 0x8)  Interrupt Enable Register -------- \r
+#define AT91C_US_RXBRK        (0x1 <<  2) // (USART) Break Received/End of Break\r
+#define AT91C_US_TIMEOUT      (0x1 <<  8) // (USART) Receiver Time-out\r
+#define AT91C_US_ITERATION    (0x1 << 10) // (USART) Max number of Repetitions Reached\r
+#define AT91C_US_NACK         (0x1 << 13) // (USART) Non Acknowledge\r
+#define AT91C_US_RIIC         (0x1 << 16) // (USART) Ring INdicator Input Change Flag\r
+#define AT91C_US_DSRIC        (0x1 << 17) // (USART) Data Set Ready Input Change Flag\r
+#define AT91C_US_DCDIC        (0x1 << 18) // (USART) Data Carrier Flag\r
+#define AT91C_US_CTSIC        (0x1 << 19) // (USART) Clear To Send Input Change Flag\r
+#define AT91C_US_MANE         (0x1 << 20) // (USART) Manchester Error Interrupt\r
+// -------- US_IDR : (USART Offset: 0xc)  Interrupt Disable Register -------- \r
+// -------- US_IMR : (USART Offset: 0x10)  Interrupt Mask Register -------- \r
+// -------- US_CSR : (USART Offset: 0x14)  Channel Status Register -------- \r
+#define AT91C_US_RI           (0x1 << 20) // (USART) Image of RI Input\r
+#define AT91C_US_DSR          (0x1 << 21) // (USART) Image of DSR Input\r
+#define AT91C_US_DCD          (0x1 << 22) // (USART) Image of DCD Input\r
+#define AT91C_US_CTS          (0x1 << 23) // (USART) Image of CTS Input\r
+#define AT91C_US_MANERR       (0x1 << 24) // (USART) Manchester Error\r
+// -------- US_MAN : (USART Offset: 0x50) Manchester Encoder Decoder Register -------- \r
+#define AT91C_US_TX_PL        (0xF <<  0) // (USART) Transmitter Preamble Length\r
+#define AT91C_US_TX_PP        (0x3 <<  8) // (USART) Transmitter Preamble Pattern\r
+#define        AT91C_US_TX_PP_ALL_ONE              (0x0 <<  8) // (USART) ALL_ONE\r
+#define        AT91C_US_TX_PP_ALL_ZERO             (0x1 <<  8) // (USART) ALL_ZERO\r
+#define        AT91C_US_TX_PP_ZERO_ONE             (0x2 <<  8) // (USART) ZERO_ONE\r
+#define        AT91C_US_TX_PP_ONE_ZERO             (0x3 <<  8) // (USART) ONE_ZERO\r
+#define AT91C_US_TX_MPOL      (0x1 << 12) // (USART) Transmitter Manchester Polarity\r
+#define AT91C_US_RX_PL        (0xF << 16) // (USART) Receiver Preamble Length\r
+#define AT91C_US_RX_PP        (0x3 << 24) // (USART) Receiver Preamble Pattern detected\r
+#define        AT91C_US_RX_PP_ALL_ONE              (0x0 << 24) // (USART) ALL_ONE\r
+#define        AT91C_US_RX_PP_ALL_ZERO             (0x1 << 24) // (USART) ALL_ZERO\r
+#define        AT91C_US_RX_PP_ZERO_ONE             (0x2 << 24) // (USART) ZERO_ONE\r
+#define        AT91C_US_RX_PP_ONE_ZERO             (0x3 << 24) // (USART) ONE_ZERO\r
+#define AT91C_US_RX_MPOL      (0x1 << 28) // (USART) Receiver Manchester Polarity\r
+#define AT91C_US_DRIFT        (0x1 << 30) // (USART) Drift compensation\r
+\r
+// *****************************************************************************\r
+//              SOFTWARE API DEFINITION  FOR Synchronous Serial Controller Interface\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_SSC {\r
+       AT91_REG         SSC_CR;        // Control Register\r
+       AT91_REG         SSC_CMR;       // Clock Mode Register\r
+       AT91_REG         Reserved0[2];  // \r
+       AT91_REG         SSC_RCMR;      // Receive Clock ModeRegister\r
+       AT91_REG         SSC_RFMR;      // Receive Frame Mode Register\r
+       AT91_REG         SSC_TCMR;      // Transmit Clock Mode Register\r
+       AT91_REG         SSC_TFMR;      // Transmit Frame Mode Register\r
+       AT91_REG         SSC_RHR;       // Receive Holding Register\r
+       AT91_REG         SSC_THR;       // Transmit Holding Register\r
+       AT91_REG         Reserved1[2];  // \r
+       AT91_REG         SSC_RSHR;      // Receive Sync Holding Register\r
+       AT91_REG         SSC_TSHR;      // Transmit Sync Holding Register\r
+       AT91_REG         Reserved2[2];  // \r
+       AT91_REG         SSC_SR;        // Status Register\r
+       AT91_REG         SSC_IER;       // Interrupt Enable Register\r
+       AT91_REG         SSC_IDR;       // Interrupt Disable Register\r
+       AT91_REG         SSC_IMR;       // Interrupt Mask Register\r
+       AT91_REG         Reserved3[39];         // \r
+       AT91_REG         SSC_ADDRSIZE;  // SSC ADDRSIZE REGISTER \r
+       AT91_REG         SSC_IPNAME1;   // SSC IPNAME1 REGISTER \r
+       AT91_REG         SSC_IPNAME2;   // SSC IPNAME2 REGISTER \r
+       AT91_REG         SSC_FEATURES;  // SSC FEATURES REGISTER \r
+       AT91_REG         SSC_VER;       // Version Register\r
+       AT91_REG         SSC_RPR;       // Receive Pointer Register\r
+       AT91_REG         SSC_RCR;       // Receive Counter Register\r
+       AT91_REG         SSC_TPR;       // Transmit Pointer Register\r
+       AT91_REG         SSC_TCR;       // Transmit Counter Register\r
+       AT91_REG         SSC_RNPR;      // Receive Next Pointer Register\r
+       AT91_REG         SSC_RNCR;      // Receive Next Counter Register\r
+       AT91_REG         SSC_TNPR;      // Transmit Next Pointer Register\r
+       AT91_REG         SSC_TNCR;      // Transmit Next Counter Register\r
+       AT91_REG         SSC_PTCR;      // PDC Transfer Control Register\r
+       AT91_REG         SSC_PTSR;      // PDC Transfer Status Register\r
+} AT91S_SSC, *AT91PS_SSC;\r
+#else\r
+#define SSC_CR          (AT91_CAST(AT91_REG *)         0x00000000) // (SSC_CR) Control Register\r
+#define SSC_CMR         (AT91_CAST(AT91_REG *)         0x00000004) // (SSC_CMR) Clock Mode Register\r
+#define SSC_RCMR        (AT91_CAST(AT91_REG *)         0x00000010) // (SSC_RCMR) Receive Clock ModeRegister\r
+#define SSC_RFMR        (AT91_CAST(AT91_REG *)         0x00000014) // (SSC_RFMR) Receive Frame Mode Register\r
+#define SSC_TCMR        (AT91_CAST(AT91_REG *)         0x00000018) // (SSC_TCMR) Transmit Clock Mode Register\r
+#define SSC_TFMR        (AT91_CAST(AT91_REG *)         0x0000001C) // (SSC_TFMR) Transmit Frame Mode Register\r
+#define SSC_RHR         (AT91_CAST(AT91_REG *)         0x00000020) // (SSC_RHR) Receive Holding Register\r
+#define SSC_THR         (AT91_CAST(AT91_REG *)         0x00000024) // (SSC_THR) Transmit Holding Register\r
+#define SSC_RSHR        (AT91_CAST(AT91_REG *)         0x00000030) // (SSC_RSHR) Receive Sync Holding Register\r
+#define SSC_TSHR        (AT91_CAST(AT91_REG *)         0x00000034) // (SSC_TSHR) Transmit Sync Holding Register\r
+#define SSC_SR          (AT91_CAST(AT91_REG *)         0x00000040) // (SSC_SR) Status Register\r
+#define SSC_IER         (AT91_CAST(AT91_REG *)         0x00000044) // (SSC_IER) Interrupt Enable Register\r
+#define SSC_IDR         (AT91_CAST(AT91_REG *)         0x00000048) // (SSC_IDR) Interrupt Disable Register\r
+#define SSC_IMR         (AT91_CAST(AT91_REG *)         0x0000004C) // (SSC_IMR) Interrupt Mask Register\r
+#define SSC_ADDRSIZE    (AT91_CAST(AT91_REG *)         0x000000EC) // (SSC_ADDRSIZE) SSC ADDRSIZE REGISTER \r
+#define SSC_IPNAME1     (AT91_CAST(AT91_REG *)         0x000000F0) // (SSC_IPNAME1) SSC IPNAME1 REGISTER \r
+#define SSC_IPNAME2     (AT91_CAST(AT91_REG *)         0x000000F4) // (SSC_IPNAME2) SSC IPNAME2 REGISTER \r
+#define SSC_FEATURES    (AT91_CAST(AT91_REG *)         0x000000F8) // (SSC_FEATURES) SSC FEATURES REGISTER \r
+#define SSC_VER         (AT91_CAST(AT91_REG *)         0x000000FC) // (SSC_VER) Version Register\r
+\r
+#endif\r
+// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- \r
+#define AT91C_SSC_RXEN        (0x1 <<  0) // (SSC) Receive Enable\r
+#define AT91C_SSC_RXDIS       (0x1 <<  1) // (SSC) Receive Disable\r
+#define AT91C_SSC_TXEN        (0x1 <<  8) // (SSC) Transmit Enable\r
+#define AT91C_SSC_TXDIS       (0x1 <<  9) // (SSC) Transmit Disable\r
+#define AT91C_SSC_SWRST       (0x1 << 15) // (SSC) Software Reset\r
+// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- \r
+#define AT91C_SSC_CKS         (0x3 <<  0) // (SSC) Receive/Transmit Clock Selection\r
+#define        AT91C_SSC_CKS_DIV                  (0x0) // (SSC) Divided Clock\r
+#define        AT91C_SSC_CKS_TK                   (0x1) // (SSC) TK Clock signal\r
+#define        AT91C_SSC_CKS_RK                   (0x2) // (SSC) RK pin\r
+#define AT91C_SSC_CKO         (0x7 <<  2) // (SSC) Receive/Transmit Clock Output Mode Selection\r
+#define        AT91C_SSC_CKO_NONE                 (0x0 <<  2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only\r
+#define        AT91C_SSC_CKO_CONTINOUS            (0x1 <<  2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output\r
+#define        AT91C_SSC_CKO_DATA_TX              (0x2 <<  2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output\r
+#define AT91C_SSC_CKI         (0x1 <<  5) // (SSC) Receive/Transmit Clock Inversion\r
+#define AT91C_SSC_CKG         (0x3 <<  6) // (SSC) Receive/Transmit Clock Gating Selection\r
+#define        AT91C_SSC_CKG_NONE                 (0x0 <<  6) // (SSC) Receive/Transmit Clock Gating: None, continuous clock\r
+#define        AT91C_SSC_CKG_LOW                  (0x1 <<  6) // (SSC) Receive/Transmit Clock enabled only if RF Low\r
+#define        AT91C_SSC_CKG_HIGH                 (0x2 <<  6) // (SSC) Receive/Transmit Clock enabled only if RF High\r
+#define AT91C_SSC_START       (0xF <<  8) // (SSC) Receive/Transmit Start Selection\r
+#define        AT91C_SSC_START_CONTINOUS            (0x0 <<  8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.\r
+#define        AT91C_SSC_START_TX                   (0x1 <<  8) // (SSC) Transmit/Receive start\r
+#define        AT91C_SSC_START_LOW_RF               (0x2 <<  8) // (SSC) Detection of a low level on RF input\r
+#define        AT91C_SSC_START_HIGH_RF              (0x3 <<  8) // (SSC) Detection of a high level on RF input\r
+#define        AT91C_SSC_START_FALL_RF              (0x4 <<  8) // (SSC) Detection of a falling edge on RF input\r
+#define        AT91C_SSC_START_RISE_RF              (0x5 <<  8) // (SSC) Detection of a rising edge on RF input\r
+#define        AT91C_SSC_START_LEVEL_RF             (0x6 <<  8) // (SSC) Detection of any level change on RF input\r
+#define        AT91C_SSC_START_EDGE_RF              (0x7 <<  8) // (SSC) Detection of any edge on RF input\r
+#define        AT91C_SSC_START_0                    (0x8 <<  8) // (SSC) Compare 0\r
+#define AT91C_SSC_STOP        (0x1 << 12) // (SSC) Receive Stop Selection\r
+#define AT91C_SSC_STTDLY      (0xFF << 16) // (SSC) Receive/Transmit Start Delay\r
+#define AT91C_SSC_PERIOD      (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection\r
+// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- \r
+#define AT91C_SSC_DATLEN      (0x1F <<  0) // (SSC) Data Length\r
+#define AT91C_SSC_LOOP        (0x1 <<  5) // (SSC) Loop Mode\r
+#define AT91C_SSC_MSBF        (0x1 <<  7) // (SSC) Most Significant Bit First\r
+#define AT91C_SSC_DATNB       (0xF <<  8) // (SSC) Data Number per Frame\r
+#define AT91C_SSC_FSLEN       (0xF << 16) // (SSC) Receive/Transmit Frame Sync length\r
+#define AT91C_SSC_FSOS        (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection\r
+#define        AT91C_SSC_FSOS_NONE                 (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only\r
+#define        AT91C_SSC_FSOS_NEGATIVE             (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse\r
+#define        AT91C_SSC_FSOS_POSITIVE             (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse\r
+#define        AT91C_SSC_FSOS_LOW                  (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer\r
+#define        AT91C_SSC_FSOS_HIGH                 (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer\r
+#define        AT91C_SSC_FSOS_TOGGLE               (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer\r
+#define AT91C_SSC_FSEDGE      (0x1 << 24) // (SSC) Frame Sync Edge Detection\r
+// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- \r
+// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- \r
+#define AT91C_SSC_DATDEF      (0x1 <<  5) // (SSC) Data Default Value\r
+#define AT91C_SSC_FSDEN       (0x1 << 23) // (SSC) Frame Sync Data Enable\r
+// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- \r
+#define AT91C_SSC_TXRDY       (0x1 <<  0) // (SSC) Transmit Ready\r
+#define AT91C_SSC_TXEMPTY     (0x1 <<  1) // (SSC) Transmit Empty\r
+#define AT91C_SSC_ENDTX       (0x1 <<  2) // (SSC) End Of Transmission\r
+#define AT91C_SSC_TXBUFE      (0x1 <<  3) // (SSC) Transmit Buffer Empty\r
+#define AT91C_SSC_RXRDY       (0x1 <<  4) // (SSC) Receive Ready\r
+#define AT91C_SSC_OVRUN       (0x1 <<  5) // (SSC) Receive Overrun\r
+#define AT91C_SSC_ENDRX       (0x1 <<  6) // (SSC) End of Reception\r
+#define AT91C_SSC_RXBUFF      (0x1 <<  7) // (SSC) Receive Buffer Full\r
+#define AT91C_SSC_CP0         (0x1 <<  8) // (SSC) Compare 0\r
+#define AT91C_SSC_CP1         (0x1 <<  9) // (SSC) Compare 1\r
+#define AT91C_SSC_TXSYN       (0x1 << 10) // (SSC) Transmit Sync\r
+#define AT91C_SSC_RXSYN       (0x1 << 11) // (SSC) Receive Sync\r
+#define AT91C_SSC_TXENA       (0x1 << 16) // (SSC) Transmit Enable\r
+#define AT91C_SSC_RXENA       (0x1 << 17) // (SSC) Receive Enable\r
+// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- \r
+// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- \r
+// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- \r
+\r
+// *****************************************************************************\r
+//              SOFTWARE API DEFINITION  FOR PWMC Channel Interface\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_PWMC_CH {\r
+       AT91_REG         PWMC_CMR;      // Channel Mode Register\r
+       AT91_REG         PWMC_CDTYR;    // Channel Duty Cycle Register\r
+       AT91_REG         PWMC_CDTYUPDR;         // Channel Duty Cycle Update Register\r
+       AT91_REG         PWMC_CPRDR;    // Channel Period Register\r
+       AT91_REG         PWMC_CPRDUPDR;         // Channel Period Update Register\r
+       AT91_REG         PWMC_CCNTR;    // Channel Counter Register\r
+       AT91_REG         PWMC_DTR;      // Channel Dead Time Value Register\r
+       AT91_REG         PWMC_DTUPDR;   // Channel Dead Time Update Value Register\r
+} AT91S_PWMC_CH, *AT91PS_PWMC_CH;\r
+#else\r
+#define PWMC_CMR        (AT91_CAST(AT91_REG *)         0x00000000) // (PWMC_CMR) Channel Mode Register\r
+#define PWMC_CDTYR      (AT91_CAST(AT91_REG *)         0x00000004) // (PWMC_CDTYR) Channel Duty Cycle Register\r
+#define PWMC_CDTYUPDR   (AT91_CAST(AT91_REG *)         0x00000008) // (PWMC_CDTYUPDR) Channel Duty Cycle Update Register\r
+#define PWMC_CPRDR      (AT91_CAST(AT91_REG *)         0x0000000C) // (PWMC_CPRDR) Channel Period Register\r
+#define PWMC_CPRDUPDR   (AT91_CAST(AT91_REG *)         0x00000010) // (PWMC_CPRDUPDR) Channel Period Update Register\r
+#define PWMC_CCNTR      (AT91_CAST(AT91_REG *)         0x00000014) // (PWMC_CCNTR) Channel Counter Register\r
+#define PWMC_DTR        (AT91_CAST(AT91_REG *)         0x00000018) // (PWMC_DTR) Channel Dead Time Value Register\r
+#define PWMC_DTUPDR     (AT91_CAST(AT91_REG *)         0x0000001C) // (PWMC_DTUPDR) Channel Dead Time Update Value Register\r
+\r
+#endif\r
+// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- \r
+#define AT91C_PWMC_CPRE       (0xF <<  0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx\r
+#define        AT91C_PWMC_CPRE_MCK                  (0x0) // (PWMC_CH) \r
+#define        AT91C_PWMC_CPRE_MCK_DIV_2            (0x1) // (PWMC_CH) \r
+#define        AT91C_PWMC_CPRE_MCK_DIV_4            (0x2) // (PWMC_CH) \r
+#define        AT91C_PWMC_CPRE_MCK_DIV_8            (0x3) // (PWMC_CH) \r
+#define        AT91C_PWMC_CPRE_MCK_DIV_16           (0x4) // (PWMC_CH) \r
+#define        AT91C_PWMC_CPRE_MCK_DIV_32           (0x5) // (PWMC_CH) \r
+#define        AT91C_PWMC_CPRE_MCK_DIV_64           (0x6) // (PWMC_CH) \r
+#define        AT91C_PWMC_CPRE_MCK_DIV_128          (0x7) // (PWMC_CH) \r
+#define        AT91C_PWMC_CPRE_MCK_DIV_256          (0x8) // (PWMC_CH) \r
+#define        AT91C_PWMC_CPRE_MCK_DIV_512          (0x9) // (PWMC_CH) \r
+#define        AT91C_PWMC_CPRE_MCK_DIV_1024         (0xA) // (PWMC_CH) \r
+#define        AT91C_PWMC_CPRE_MCKA                 (0xB) // (PWMC_CH) \r
+#define        AT91C_PWMC_CPRE_MCKB                 (0xC) // (PWMC_CH) \r
+#define AT91C_PWMC_CALG       (0x1 <<  8) // (PWMC_CH) Channel Alignment\r
+#define AT91C_PWMC_CPOL       (0x1 <<  9) // (PWMC_CH) Channel Polarity\r
+#define AT91C_PWMC_CES        (0x1 << 10) // (PWMC_CH) Counter Event Selection\r
+#define AT91C_PWMC_DTE        (0x1 << 16) // (PWMC_CH) Dead Time Genrator Enable\r
+#define AT91C_PWMC_DTHI       (0x1 << 17) // (PWMC_CH) Dead Time PWMHx Output Inverted\r
+#define AT91C_PWMC_DTLI       (0x1 << 18) // (PWMC_CH) Dead Time PWMLx Output Inverted\r
+// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- \r
+#define AT91C_PWMC_CDTY       (0xFFFFFF <<  0) // (PWMC_CH) Channel Duty Cycle\r
+// -------- PWMC_CDTYUPDR : (PWMC_CH Offset: 0x8) PWMC Channel Duty Cycle Update Register -------- \r
+#define AT91C_PWMC_CDTYUPD    (0xFFFFFF <<  0) // (PWMC_CH) Channel Duty Cycle Update\r
+// -------- PWMC_CPRDR : (PWMC_CH Offset: 0xc) PWMC Channel Period Register -------- \r
+#define AT91C_PWMC_CPRD       (0xFFFFFF <<  0) // (PWMC_CH) Channel Period\r
+// -------- PWMC_CPRDUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Period Update Register -------- \r
+#define AT91C_PWMC_CPRDUPD    (0xFFFFFF <<  0) // (PWMC_CH) Channel Period Update\r
+// -------- PWMC_CCNTR : (PWMC_CH Offset: 0x14) PWMC Channel Counter Register -------- \r
+#define AT91C_PWMC_CCNT       (0xFFFFFF <<  0) // (PWMC_CH) Channel Counter\r
+// -------- PWMC_DTR : (PWMC_CH Offset: 0x18) Channel Dead Time Value Register -------- \r
+#define AT91C_PWMC_DTL        (0xFFFF <<  0) // (PWMC_CH) Channel Dead Time for PWML\r
+#define AT91C_PWMC_DTH        (0xFFFF << 16) // (PWMC_CH) Channel Dead Time for PWMH\r
+// -------- PWMC_DTUPDR : (PWMC_CH Offset: 0x1c) Channel Dead Time Value Register -------- \r
+#define AT91C_PWMC_DTLUPD     (0xFFFF <<  0) // (PWMC_CH) Channel Dead Time Update for PWML.\r
+#define AT91C_PWMC_DTHUPD     (0xFFFF << 16) // (PWMC_CH) Channel Dead Time Update for PWMH.\r
+\r
+// *****************************************************************************\r
+//              SOFTWARE API DEFINITION  FOR Pulse Width Modulation Controller Interface\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_PWMC {\r
+       AT91_REG         PWMC_MR;       // PWMC Mode Register\r
+       AT91_REG         PWMC_ENA;      // PWMC Enable Register\r
+       AT91_REG         PWMC_DIS;      // PWMC Disable Register\r
+       AT91_REG         PWMC_SR;       // PWMC Status Register\r
+       AT91_REG         PWMC_IER1;     // PWMC Interrupt Enable Register 1\r
+       AT91_REG         PWMC_IDR1;     // PWMC Interrupt Disable Register 1\r
+       AT91_REG         PWMC_IMR1;     // PWMC Interrupt Mask Register 1\r
+       AT91_REG         PWMC_ISR1;     // PWMC Interrupt Status Register 1\r
+       AT91_REG         PWMC_SYNC;     // PWM Synchronized Channels Register\r
+       AT91_REG         Reserved0[1];  // \r
+       AT91_REG         PWMC_UPCR;     // PWM Update Control Register\r
+       AT91_REG         PWMC_SCUP;     // PWM Update Period Register\r
+       AT91_REG         PWMC_SCUPUPD;  // PWM Update Period Update Register\r
+       AT91_REG         PWMC_IER2;     // PWMC Interrupt Enable Register 2\r
+       AT91_REG         PWMC_IDR2;     // PWMC Interrupt Disable Register 2\r
+       AT91_REG         PWMC_IMR2;     // PWMC Interrupt Mask Register 2\r
+       AT91_REG         PWMC_ISR2;     // PWMC Interrupt Status Register 2\r
+       AT91_REG         PWMC_OOV;      // PWM Output Override Value Register\r
+       AT91_REG         PWMC_OS;       // PWM Output Selection Register\r
+       AT91_REG         PWMC_OSS;      // PWM Output Selection Set Register\r
+       AT91_REG         PWMC_OSC;      // PWM Output Selection Clear Register\r
+       AT91_REG         PWMC_OSSUPD;   // PWM Output Selection Set Update Register\r
+       AT91_REG         PWMC_OSCUPD;   // PWM Output Selection Clear Update Register\r
+       AT91_REG         PWMC_FMR;      // PWM Fault Mode Register\r
+       AT91_REG         PWMC_FSR;      // PWM Fault Mode Status Register\r
+       AT91_REG         PWMC_FCR;      // PWM Fault Mode Clear Register\r
+       AT91_REG         PWMC_FPV;      // PWM Fault Protection Value Register\r
+       AT91_REG         PWMC_FPER1;    // PWM Fault Protection Enable Register 1\r
+       AT91_REG         PWMC_FPER2;    // PWM Fault Protection Enable Register 2\r
+       AT91_REG         PWMC_FPER3;    // PWM Fault Protection Enable Register 3\r
+       AT91_REG         PWMC_FPER4;    // PWM Fault Protection Enable Register 4\r
+       AT91_REG         PWMC_EL0MR;    // PWM Event Line 0 Mode Register\r
+       AT91_REG         PWMC_EL1MR;    // PWM Event Line 1 Mode Register\r
+       AT91_REG         PWMC_EL2MR;    // PWM Event Line 2 Mode Register\r
+       AT91_REG         PWMC_EL3MR;    // PWM Event Line 3 Mode Register\r
+       AT91_REG         PWMC_EL4MR;    // PWM Event Line 4 Mode Register\r
+       AT91_REG         PWMC_EL5MR;    // PWM Event Line 5 Mode Register\r
+       AT91_REG         PWMC_EL6MR;    // PWM Event Line 6 Mode Register\r
+       AT91_REG         PWMC_EL7MR;    // PWM Event Line 7 Mode Register\r
+       AT91_REG         Reserved1[18];         // \r
+       AT91_REG         PWMC_WPCR;     // PWM Write Protection Enable Register\r
+       AT91_REG         PWMC_WPSR;     // PWM Write Protection Status Register\r
+       AT91_REG         PWMC_ADDRSIZE;         // PWMC ADDRSIZE REGISTER \r
+       AT91_REG         PWMC_IPNAME1;  // PWMC IPNAME1 REGISTER \r
+       AT91_REG         PWMC_IPNAME2;  // PWMC IPNAME2 REGISTER \r
+       AT91_REG         PWMC_FEATURES;         // PWMC FEATURES REGISTER \r
+       AT91_REG         PWMC_VER;      // PWMC Version Register\r
+       AT91_REG         PWMC_RPR;      // Receive Pointer Register\r
+       AT91_REG         PWMC_RCR;      // Receive Counter Register\r
+       AT91_REG         PWMC_TPR;      // Transmit Pointer Register\r
+       AT91_REG         PWMC_TCR;      // Transmit Counter Register\r
+       AT91_REG         PWMC_RNPR;     // Receive Next Pointer Register\r
+       AT91_REG         PWMC_RNCR;     // Receive Next Counter Register\r
+       AT91_REG         PWMC_TNPR;     // Transmit Next Pointer Register\r
+       AT91_REG         PWMC_TNCR;     // Transmit Next Counter Register\r
+       AT91_REG         PWMC_PTCR;     // PDC Transfer Control Register\r
+       AT91_REG         PWMC_PTSR;     // PDC Transfer Status Register\r
+       AT91_REG         Reserved2[2];  // \r
+       AT91_REG         PWMC_CMP0V;    // PWM Comparison Value 0 Register\r
+       AT91_REG         PWMC_CMP0VUPD;         // PWM Comparison Value 0 Update Register\r
+       AT91_REG         PWMC_CMP0M;    // PWM Comparison Mode 0 Register\r
+       AT91_REG         PWMC_CMP0MUPD;         // PWM Comparison Mode 0 Update Register\r
+       AT91_REG         PWMC_CMP1V;    // PWM Comparison Value 1 Register\r
+       AT91_REG         PWMC_CMP1VUPD;         // PWM Comparison Value 1 Update Register\r
+       AT91_REG         PWMC_CMP1M;    // PWM Comparison Mode 1 Register\r
+       AT91_REG         PWMC_CMP1MUPD;         // PWM Comparison Mode 1 Update Register\r
+       AT91_REG         PWMC_CMP2V;    // PWM Comparison Value 2 Register\r
+       AT91_REG         PWMC_CMP2VUPD;         // PWM Comparison Value 2 Update Register\r
+       AT91_REG         PWMC_CMP2M;    // PWM Comparison Mode 2 Register\r
+       AT91_REG         PWMC_CMP2MUPD;         // PWM Comparison Mode 2 Update Register\r
+       AT91_REG         PWMC_CMP3V;    // PWM Comparison Value 3 Register\r
+       AT91_REG         PWMC_CMP3VUPD;         // PWM Comparison Value 3 Update Register\r
+       AT91_REG         PWMC_CMP3M;    // PWM Comparison Mode 3 Register\r
+       AT91_REG         PWMC_CMP3MUPD;         // PWM Comparison Mode 3 Update Register\r
+       AT91_REG         PWMC_CMP4V;    // PWM Comparison Value 4 Register\r
+       AT91_REG         PWMC_CMP4VUPD;         // PWM Comparison Value 4 Update Register\r
+       AT91_REG         PWMC_CMP4M;    // PWM Comparison Mode 4 Register\r
+       AT91_REG         PWMC_CMP4MUPD;         // PWM Comparison Mode 4 Update Register\r
+       AT91_REG         PWMC_CMP5V;    // PWM Comparison Value 5 Register\r
+       AT91_REG         PWMC_CMP5VUPD;         // PWM Comparison Value 5 Update Register\r
+       AT91_REG         PWMC_CMP5M;    // PWM Comparison Mode 5 Register\r
+       AT91_REG         PWMC_CMP5MUPD;         // PWM Comparison Mode 5 Update Register\r
+       AT91_REG         PWMC_CMP6V;    // PWM Comparison Value 6 Register\r
+       AT91_REG         PWMC_CMP6VUPD;         // PWM Comparison Value 6 Update Register\r
+       AT91_REG         PWMC_CMP6M;    // PWM Comparison Mode 6 Register\r
+       AT91_REG         PWMC_CMP6MUPD;         // PWM Comparison Mode 6 Update Register\r
+       AT91_REG         PWMC_CMP7V;    // PWM Comparison Value 7 Register\r
+       AT91_REG         PWMC_CMP7VUPD;         // PWM Comparison Value 7 Update Register\r
+       AT91_REG         PWMC_CMP7M;    // PWM Comparison Mode 7 Register\r
+       AT91_REG         PWMC_CMP7MUPD;         // PWM Comparison Mode 7 Update Register\r
+       AT91_REG         Reserved3[20];         // \r
+       AT91S_PWMC_CH    PWMC_CH[8];    // PWMC Channel 0\r
+} AT91S_PWMC, *AT91PS_PWMC;\r
+#else\r
+#define PWMC_MR         (AT91_CAST(AT91_REG *)         0x00000000) // (PWMC_MR) PWMC Mode Register\r
+#define PWMC_ENA        (AT91_CAST(AT91_REG *)         0x00000004) // (PWMC_ENA) PWMC Enable Register\r
+#define PWMC_DIS        (AT91_CAST(AT91_REG *)         0x00000008) // (PWMC_DIS) PWMC Disable Register\r
+#define PWMC_SR         (AT91_CAST(AT91_REG *)         0x0000000C) // (PWMC_SR) PWMC Status Register\r
+#define PWMC_IER1       (AT91_CAST(AT91_REG *)         0x00000010) // (PWMC_IER1) PWMC Interrupt Enable Register 1\r
+#define PWMC_IDR1       (AT91_CAST(AT91_REG *)         0x00000014) // (PWMC_IDR1) PWMC Interrupt Disable Register 1\r
+#define PWMC_IMR1       (AT91_CAST(AT91_REG *)         0x00000018) // (PWMC_IMR1) PWMC Interrupt Mask Register 1\r
+#define PWMC_ISR1       (AT91_CAST(AT91_REG *)         0x0000001C) // (PWMC_ISR1) PWMC Interrupt Status Register 1\r
+#define PWMC_SYNC       (AT91_CAST(AT91_REG *)         0x00000020) // (PWMC_SYNC) PWM Synchronized Channels Register\r
+#define PWMC_UPCR       (AT91_CAST(AT91_REG *)         0x00000028) // (PWMC_UPCR) PWM Update Control Register\r
+#define PWMC_SCUP       (AT91_CAST(AT91_REG *)         0x0000002C) // (PWMC_SCUP) PWM Update Period Register\r
+#define PWMC_SCUPUPD    (AT91_CAST(AT91_REG *)         0x00000030) // (PWMC_SCUPUPD) PWM Update Period Update Register\r
+#define PWMC_IER2       (AT91_CAST(AT91_REG *)         0x00000034) // (PWMC_IER2) PWMC Interrupt Enable Register 2\r
+#define PWMC_IDR2       (AT91_CAST(AT91_REG *)         0x00000038) // (PWMC_IDR2) PWMC Interrupt Disable Register 2\r
+#define PWMC_IMR2       (AT91_CAST(AT91_REG *)         0x0000003C) // (PWMC_IMR2) PWMC Interrupt Mask Register 2\r
+#define PWMC_ISR2       (AT91_CAST(AT91_REG *)         0x00000040) // (PWMC_ISR2) PWMC Interrupt Status Register 2\r
+#define PWMC_OOV        (AT91_CAST(AT91_REG *)         0x00000044) // (PWMC_OOV) PWM Output Override Value Register\r
+#define PWMC_OS         (AT91_CAST(AT91_REG *)         0x00000048) // (PWMC_OS) PWM Output Selection Register\r
+#define PWMC_OSS        (AT91_CAST(AT91_REG *)         0x0000004C) // (PWMC_OSS) PWM Output Selection Set Register\r
+#define PWMC_OSC        (AT91_CAST(AT91_REG *)         0x00000050) // (PWMC_OSC) PWM Output Selection Clear Register\r
+#define PWMC_OSSUPD     (AT91_CAST(AT91_REG *)         0x00000054) // (PWMC_OSSUPD) PWM Output Selection Set Update Register\r
+#define PWMC_OSCUPD     (AT91_CAST(AT91_REG *)         0x00000058) // (PWMC_OSCUPD) PWM Output Selection Clear Update Register\r
+#define PWMC_FMR        (AT91_CAST(AT91_REG *)         0x0000005C) // (PWMC_FMR) PWM Fault Mode Register\r
+#define PWMC_FSR        (AT91_CAST(AT91_REG *)         0x00000060) // (PWMC_FSR) PWM Fault Mode Status Register\r
+#define PWMC_FCR        (AT91_CAST(AT91_REG *)         0x00000064) // (PWMC_FCR) PWM Fault Mode Clear Register\r
+#define PWMC_FPV        (AT91_CAST(AT91_REG *)         0x00000068) // (PWMC_FPV) PWM Fault Protection Value Register\r
+#define PWMC_FPER1      (AT91_CAST(AT91_REG *)         0x0000006C) // (PWMC_FPER1) PWM Fault Protection Enable Register 1\r
+#define PWMC_FPER2      (AT91_CAST(AT91_REG *)         0x00000070) // (PWMC_FPER2) PWM Fault Protection Enable Register 2\r
+#define PWMC_FPER3      (AT91_CAST(AT91_REG *)         0x00000074) // (PWMC_FPER3) PWM Fault Protection Enable Register 3\r
+#define PWMC_FPER4      (AT91_CAST(AT91_REG *)         0x00000078) // (PWMC_FPER4) PWM Fault Protection Enable Register 4\r
+#define PWMC_EL0MR      (AT91_CAST(AT91_REG *)         0x0000007C) // (PWMC_EL0MR) PWM Event Line 0 Mode Register\r
+#define PWMC_EL1MR      (AT91_CAST(AT91_REG *)         0x00000080) // (PWMC_EL1MR) PWM Event Line 1 Mode Register\r
+#define PWMC_EL2MR      (AT91_CAST(AT91_REG *)         0x00000084) // (PWMC_EL2MR) PWM Event Line 2 Mode Register\r
+#define PWMC_EL3MR      (AT91_CAST(AT91_REG *)         0x00000088) // (PWMC_EL3MR) PWM Event Line 3 Mode Register\r
+#define PWMC_EL4MR      (AT91_CAST(AT91_REG *)         0x0000008C) // (PWMC_EL4MR) PWM Event Line 4 Mode Register\r
+#define PWMC_EL5MR      (AT91_CAST(AT91_REG *)         0x00000090) // (PWMC_EL5MR) PWM Event Line 5 Mode Register\r
+#define PWMC_EL6MR      (AT91_CAST(AT91_REG *)         0x00000094) // (PWMC_EL6MR) PWM Event Line 6 Mode Register\r
+#define PWMC_EL7MR      (AT91_CAST(AT91_REG *)         0x00000098) // (PWMC_EL7MR) PWM Event Line 7 Mode Register\r
+#define PWMC_WPCR       (AT91_CAST(AT91_REG *)         0x000000E4) // (PWMC_WPCR) PWM Write Protection Enable Register\r
+#define PWMC_WPSR       (AT91_CAST(AT91_REG *)         0x000000E8) // (PWMC_WPSR) PWM Write Protection Status Register\r
+#define PWMC_ADDRSIZE   (AT91_CAST(AT91_REG *)         0x000000EC) // (PWMC_ADDRSIZE) PWMC ADDRSIZE REGISTER \r
+#define PWMC_IPNAME1    (AT91_CAST(AT91_REG *)         0x000000F0) // (PWMC_IPNAME1) PWMC IPNAME1 REGISTER \r
+#define PWMC_IPNAME2    (AT91_CAST(AT91_REG *)         0x000000F4) // (PWMC_IPNAME2) PWMC IPNAME2 REGISTER \r
+#define PWMC_FEATURES   (AT91_CAST(AT91_REG *)         0x000000F8) // (PWMC_FEATURES) PWMC FEATURES REGISTER \r
+#define PWMC_VER        (AT91_CAST(AT91_REG *)         0x000000FC) // (PWMC_VER) PWMC Version Register\r
+#define PWMC_CMP0V      (AT91_CAST(AT91_REG *)         0x00000130) // (PWMC_CMP0V) PWM Comparison Value 0 Register\r
+#define PWMC_CMP0VUPD   (AT91_CAST(AT91_REG *)         0x00000134) // (PWMC_CMP0VUPD) PWM Comparison Value 0 Update Register\r
+#define PWMC_CMP0M      (AT91_CAST(AT91_REG *)         0x00000138) // (PWMC_CMP0M) PWM Comparison Mode 0 Register\r
+#define PWMC_CMP0MUPD   (AT91_CAST(AT91_REG *)         0x0000013C) // (PWMC_CMP0MUPD) PWM Comparison Mode 0 Update Register\r
+#define PWMC_CMP1V      (AT91_CAST(AT91_REG *)         0x00000140) // (PWMC_CMP1V) PWM Comparison Value 1 Register\r
+#define PWMC_CMP1VUPD   (AT91_CAST(AT91_REG *)         0x00000144) // (PWMC_CMP1VUPD) PWM Comparison Value 1 Update Register\r
+#define PWMC_CMP1M      (AT91_CAST(AT91_REG *)         0x00000148) // (PWMC_CMP1M) PWM Comparison Mode 1 Register\r
+#define PWMC_CMP1MUPD   (AT91_CAST(AT91_REG *)         0x0000014C) // (PWMC_CMP1MUPD) PWM Comparison Mode 1 Update Register\r
+#define PWMC_CMP2V      (AT91_CAST(AT91_REG *)         0x00000150) // (PWMC_CMP2V) PWM Comparison Value 2 Register\r
+#define PWMC_CMP2VUPD   (AT91_CAST(AT91_REG *)         0x00000154) // (PWMC_CMP2VUPD) PWM Comparison Value 2 Update Register\r
+#define PWMC_CMP2M      (AT91_CAST(AT91_REG *)         0x00000158) // (PWMC_CMP2M) PWM Comparison Mode 2 Register\r
+#define PWMC_CMP2MUPD   (AT91_CAST(AT91_REG *)         0x0000015C) // (PWMC_CMP2MUPD) PWM Comparison Mode 2 Update Register\r
+#define PWMC_CMP3V      (AT91_CAST(AT91_REG *)         0x00000160) // (PWMC_CMP3V) PWM Comparison Value 3 Register\r
+#define PWMC_CMP3VUPD   (AT91_CAST(AT91_REG *)         0x00000164) // (PWMC_CMP3VUPD) PWM Comparison Value 3 Update Register\r
+#define PWMC_CMP3M      (AT91_CAST(AT91_REG *)         0x00000168) // (PWMC_CMP3M) PWM Comparison Mode 3 Register\r
+#define PWMC_CMP3MUPD   (AT91_CAST(AT91_REG *)         0x0000016C) // (PWMC_CMP3MUPD) PWM Comparison Mode 3 Update Register\r
+#define PWMC_CMP4V      (AT91_CAST(AT91_REG *)         0x00000170) // (PWMC_CMP4V) PWM Comparison Value 4 Register\r
+#define PWMC_CMP4VUPD   (AT91_CAST(AT91_REG *)         0x00000174) // (PWMC_CMP4VUPD) PWM Comparison Value 4 Update Register\r
+#define PWMC_CMP4M      (AT91_CAST(AT91_REG *)         0x00000178) // (PWMC_CMP4M) PWM Comparison Mode 4 Register\r
+#define PWMC_CMP4MUPD   (AT91_CAST(AT91_REG *)         0x0000017C) // (PWMC_CMP4MUPD) PWM Comparison Mode 4 Update Register\r
+#define PWMC_CMP5V      (AT91_CAST(AT91_REG *)         0x00000180) // (PWMC_CMP5V) PWM Comparison Value 5 Register\r
+#define PWMC_CMP5VUPD   (AT91_CAST(AT91_REG *)         0x00000184) // (PWMC_CMP5VUPD) PWM Comparison Value 5 Update Register\r
+#define PWMC_CMP5M      (AT91_CAST(AT91_REG *)         0x00000188) // (PWMC_CMP5M) PWM Comparison Mode 5 Register\r
+#define PWMC_CMP5MUPD   (AT91_CAST(AT91_REG *)         0x0000018C) // (PWMC_CMP5MUPD) PWM Comparison Mode 5 Update Register\r
+#define PWMC_CMP6V      (AT91_CAST(AT91_REG *)         0x00000190) // (PWMC_CMP6V) PWM Comparison Value 6 Register\r
+#define PWMC_CMP6VUPD   (AT91_CAST(AT91_REG *)         0x00000194) // (PWMC_CMP6VUPD) PWM Comparison Value 6 Update Register\r
+#define PWMC_CMP6M      (AT91_CAST(AT91_REG *)         0x00000198) // (PWMC_CMP6M) PWM Comparison Mode 6 Register\r
+#define PWMC_CMP6MUPD   (AT91_CAST(AT91_REG *)         0x0000019C) // (PWMC_CMP6MUPD) PWM Comparison Mode 6 Update Register\r
+#define PWMC_CMP7V      (AT91_CAST(AT91_REG *)         0x000001A0) // (PWMC_CMP7V) PWM Comparison Value 7 Register\r
+#define PWMC_CMP7VUPD   (AT91_CAST(AT91_REG *)         0x000001A4) // (PWMC_CMP7VUPD) PWM Comparison Value 7 Update Register\r
+#define PWMC_CMP7M      (AT91_CAST(AT91_REG *)         0x000001A8) // (PWMC_CMP7M) PWM Comparison Mode 7 Register\r
+#define PWMC_CMP7MUPD   (AT91_CAST(AT91_REG *)         0x000001AC) // (PWMC_CMP7MUPD) PWM Comparison Mode 7 Update Register\r
+\r
+#endif\r
+// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- \r
+#define AT91C_PWMC_DIVA       (0xFF <<  0) // (PWMC) CLKA divide factor.\r
+#define AT91C_PWMC_PREA       (0xF <<  8) // (PWMC) Divider Input Clock Prescaler A\r
+#define        AT91C_PWMC_PREA_MCK                  (0x0 <<  8) // (PWMC) \r
+#define        AT91C_PWMC_PREA_MCK_DIV_2            (0x1 <<  8) // (PWMC) \r
+#define        AT91C_PWMC_PREA_MCK_DIV_4            (0x2 <<  8) // (PWMC) \r
+#define        AT91C_PWMC_PREA_MCK_DIV_8            (0x3 <<  8) // (PWMC) \r
+#define        AT91C_PWMC_PREA_MCK_DIV_16           (0x4 <<  8) // (PWMC) \r
+#define        AT91C_PWMC_PREA_MCK_DIV_32           (0x5 <<  8) // (PWMC) \r
+#define        AT91C_PWMC_PREA_MCK_DIV_64           (0x6 <<  8) // (PWMC) \r
+#define        AT91C_PWMC_PREA_MCK_DIV_128          (0x7 <<  8) // (PWMC) \r
+#define        AT91C_PWMC_PREA_MCK_DIV_256          (0x8 <<  8) // (PWMC) \r
+#define AT91C_PWMC_DIVB       (0xFF << 16) // (PWMC) CLKB divide factor.\r
+#define AT91C_PWMC_PREB       (0xF << 24) // (PWMC) Divider Input Clock Prescaler B\r
+#define        AT91C_PWMC_PREB_MCK                  (0x0 << 24) // (PWMC) \r
+#define        AT91C_PWMC_PREB_MCK_DIV_2            (0x1 << 24) // (PWMC) \r
+#define        AT91C_PWMC_PREB_MCK_DIV_4            (0x2 << 24) // (PWMC) \r
+#define        AT91C_PWMC_PREB_MCK_DIV_8            (0x3 << 24) // (PWMC) \r
+#define        AT91C_PWMC_PREB_MCK_DIV_16           (0x4 << 24) // (PWMC) \r
+#define        AT91C_PWMC_PREB_MCK_DIV_32           (0x5 << 24) // (PWMC) \r
+#define        AT91C_PWMC_PREB_MCK_DIV_64           (0x6 << 24) // (PWMC) \r
+#define        AT91C_PWMC_PREB_MCK_DIV_128          (0x7 << 24) // (PWMC) \r
+#define        AT91C_PWMC_PREB_MCK_DIV_256          (0x8 << 24) // (PWMC) \r
+#define AT91C_PWMC_CLKSEL     (0x1 << 31) // (PWMC) CCK Source Clock Selection\r
+// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- \r
+#define AT91C_PWMC_CHID0      (0x1 <<  0) // (PWMC) Channel ID 0\r
+#define AT91C_PWMC_CHID1      (0x1 <<  1) // (PWMC) Channel ID 1\r
+#define AT91C_PWMC_CHID2      (0x1 <<  2) // (PWMC) Channel ID 2\r
+#define AT91C_PWMC_CHID3      (0x1 <<  3) // (PWMC) Channel ID 3\r
+#define AT91C_PWMC_CHID4      (0x1 <<  4) // (PWMC) Channel ID 4\r
+#define AT91C_PWMC_CHID5      (0x1 <<  5) // (PWMC) Channel ID 5\r
+#define AT91C_PWMC_CHID6      (0x1 <<  6) // (PWMC) Channel ID 6\r
+#define AT91C_PWMC_CHID7      (0x1 <<  7) // (PWMC) Channel ID 7\r
+#define AT91C_PWMC_CHID8      (0x1 <<  8) // (PWMC) Channel ID 8\r
+#define AT91C_PWMC_CHID9      (0x1 <<  9) // (PWMC) Channel ID 9\r
+#define AT91C_PWMC_CHID10     (0x1 << 10) // (PWMC) Channel ID 10\r
+#define AT91C_PWMC_CHID11     (0x1 << 11) // (PWMC) Channel ID 11\r
+#define AT91C_PWMC_CHID12     (0x1 << 12) // (PWMC) Channel ID 12\r
+#define AT91C_PWMC_CHID13     (0x1 << 13) // (PWMC) Channel ID 13\r
+#define AT91C_PWMC_CHID14     (0x1 << 14) // (PWMC) Channel ID 14\r
+#define AT91C_PWMC_CHID15     (0x1 << 15) // (PWMC) Channel ID 15\r
+// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- \r
+// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- \r
+// -------- PWMC_IER1 : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- \r
+#define AT91C_PWMC_FCHID0     (0x1 << 16) // (PWMC) Fault Event Channel ID 0\r
+#define AT91C_PWMC_FCHID1     (0x1 << 17) // (PWMC) Fault Event Channel ID 1\r
+#define AT91C_PWMC_FCHID2     (0x1 << 18) // (PWMC) Fault Event Channel ID 2\r
+#define AT91C_PWMC_FCHID3     (0x1 << 19) // (PWMC) Fault Event Channel ID 3\r
+#define AT91C_PWMC_FCHID4     (0x1 << 20) // (PWMC) Fault Event Channel ID 4\r
+#define AT91C_PWMC_FCHID5     (0x1 << 21) // (PWMC) Fault Event Channel ID 5\r
+#define AT91C_PWMC_FCHID6     (0x1 << 22) // (PWMC) Fault Event Channel ID 6\r
+#define AT91C_PWMC_FCHID7     (0x1 << 23) // (PWMC) Fault Event Channel ID 7\r
+#define AT91C_PWMC_FCHID8     (0x1 << 24) // (PWMC) Fault Event Channel ID 8\r
+#define AT91C_PWMC_FCHID9     (0x1 << 25) // (PWMC) Fault Event Channel ID 9\r
+#define AT91C_PWMC_FCHID10    (0x1 << 26) // (PWMC) Fault Event Channel ID 10\r
+#define AT91C_PWMC_FCHID11    (0x1 << 27) // (PWMC) Fault Event Channel ID 11\r
+#define AT91C_PWMC_FCHID12    (0x1 << 28) // (PWMC) Fault Event Channel ID 12\r
+#define AT91C_PWMC_FCHID13    (0x1 << 29) // (PWMC) Fault Event Channel ID 13\r
+#define AT91C_PWMC_FCHID14    (0x1 << 30) // (PWMC) Fault Event Channel ID 14\r
+#define AT91C_PWMC_FCHID15    (0x1 << 31) // (PWMC) Fault Event Channel ID 15\r
+// -------- PWMC_IDR1 : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- \r
+// -------- PWMC_IMR1 : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- \r
+// -------- PWMC_ISR1 : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- \r
+// -------- PWMC_SYNC : (PWMC Offset: 0x20) PWMC Synchronous Channels Register -------- \r
+#define AT91C_PWMC_SYNC0      (0x1 <<  0) // (PWMC) Synchronous Channel ID 0\r
+#define AT91C_PWMC_SYNC1      (0x1 <<  1) // (PWMC) Synchronous Channel ID 1\r
+#define AT91C_PWMC_SYNC2      (0x1 <<  2) // (PWMC) Synchronous Channel ID 2\r
+#define AT91C_PWMC_SYNC3      (0x1 <<  3) // (PWMC) Synchronous Channel ID 3\r
+#define AT91C_PWMC_SYNC4      (0x1 <<  4) // (PWMC) Synchronous Channel ID 4\r
+#define AT91C_PWMC_SYNC5      (0x1 <<  5) // (PWMC) Synchronous Channel ID 5\r
+#define AT91C_PWMC_SYNC6      (0x1 <<  6) // (PWMC) Synchronous Channel ID 6\r
+#define AT91C_PWMC_SYNC7      (0x1 <<  7) // (PWMC) Synchronous Channel ID 7\r
+#define AT91C_PWMC_SYNC8      (0x1 <<  8) // (PWMC) Synchronous Channel ID 8\r
+#define AT91C_PWMC_SYNC9      (0x1 <<  9) // (PWMC) Synchronous Channel ID 9\r
+#define AT91C_PWMC_SYNC10     (0x1 << 10) // (PWMC) Synchronous Channel ID 10\r
+#define AT91C_PWMC_SYNC11     (0x1 << 11) // (PWMC) Synchronous Channel ID 11\r
+#define AT91C_PWMC_SYNC12     (0x1 << 12) // (PWMC) Synchronous Channel ID 12\r
+#define AT91C_PWMC_SYNC13     (0x1 << 13) // (PWMC) Synchronous Channel ID 13\r
+#define AT91C_PWMC_SYNC14     (0x1 << 14) // (PWMC) Synchronous Channel ID 14\r
+#define AT91C_PWMC_SYNC15     (0x1 << 15) // (PWMC) Synchronous Channel ID 15\r
+#define AT91C_PWMC_UPDM       (0x3 << 16) // (PWMC) Synchronous Channels Update mode\r
+#define        AT91C_PWMC_UPDM_MODE0                (0x0 << 16) // (PWMC) Manual write of data and manual trigger of the update\r
+#define        AT91C_PWMC_UPDM_MODE1                (0x1 << 16) // (PWMC) Manual write of data and automatic trigger of the update\r
+#define        AT91C_PWMC_UPDM_MODE2                (0x2 << 16) // (PWMC) Automatic write of data and automatic trigger of the update\r
+// -------- PWMC_UPCR : (PWMC Offset: 0x28) PWMC Update Control Register -------- \r
+#define AT91C_PWMC_UPDULOCK   (0x1 <<  0) // (PWMC) Synchronized Channels Duty Cycle Update Unlock\r
+// -------- PWMC_SCUP : (PWMC Offset: 0x2c) PWM Update Period Register -------- \r
+#define AT91C_PWMC_UPR        (0xF <<  0) // (PWMC) PWM Update Period.\r
+#define AT91C_PWMC_UPRCNT     (0xF <<  4) // (PWMC) PWM Update Period Counter.\r
+// -------- PWMC_SCUPUPD : (PWMC Offset: 0x30) PWM Update Period Update Register -------- \r
+#define AT91C_PWMC_UPVUPDAL   (0xF <<  0) // (PWMC) PWM Update Period Update.\r
+// -------- PWMC_IER2 : (PWMC Offset: 0x34) PWMC Interrupt Enable Register -------- \r
+#define AT91C_PWMC_WRDY       (0x1 <<  0) // (PWMC) PDC Write Ready\r
+#define AT91C_PWMC_ENDTX      (0x1 <<  1) // (PWMC) PDC End of TX Buffer\r
+#define AT91C_PWMC_TXBUFE     (0x1 <<  2) // (PWMC) PDC End of TX Buffer\r
+#define AT91C_PWMC_UNRE       (0x1 <<  3) // (PWMC) PDC End of TX Buffer\r
+// -------- PWMC_IDR2 : (PWMC Offset: 0x38) PWMC Interrupt Disable Register -------- \r
+// -------- PWMC_IMR2 : (PWMC Offset: 0x3c) PWMC Interrupt Mask Register -------- \r
+// -------- PWMC_ISR2 : (PWMC Offset: 0x40) PWMC Interrupt Status Register -------- \r
+#define AT91C_PWMC_CMPM0      (0x1 <<  8) // (PWMC) Comparison x Match\r
+#define AT91C_PWMC_CMPM1      (0x1 <<  9) // (PWMC) Comparison x Match\r
+#define AT91C_PWMC_CMPM2      (0x1 << 10) // (PWMC) Comparison x Match\r
+#define AT91C_PWMC_CMPM3      (0x1 << 11) // (PWMC) Comparison x Match\r
+#define AT91C_PWMC_CMPM4      (0x1 << 12) // (PWMC) Comparison x Match\r
+#define AT91C_PWMC_CMPM5      (0x1 << 13) // (PWMC) Comparison x Match\r
+#define AT91C_PWMC_CMPM6      (0x1 << 14) // (PWMC) Comparison x Match\r
+#define AT91C_PWMC_CMPM7      (0x1 << 15) // (PWMC) Comparison x Match\r
+#define AT91C_PWMC_CMPU0      (0x1 << 16) // (PWMC) Comparison x Update\r
+#define AT91C_PWMC_CMPU1      (0x1 << 17) // (PWMC) Comparison x Update\r
+#define AT91C_PWMC_CMPU2      (0x1 << 18) // (PWMC) Comparison x Update\r
+#define AT91C_PWMC_CMPU3      (0x1 << 19) // (PWMC) Comparison x Update\r
+#define AT91C_PWMC_CMPU4      (0x1 << 20) // (PWMC) Comparison x Update\r
+#define AT91C_PWMC_CMPU5      (0x1 << 21) // (PWMC) Comparison x Update\r
+#define AT91C_PWMC_CMPU6      (0x1 << 22) // (PWMC) Comparison x Update\r
+#define AT91C_PWMC_CMPU7      (0x1 << 23) // (PWMC) Comparison x Update\r
+// -------- PWMC_OOV : (PWMC Offset: 0x44) PWM Output Override Value Register -------- \r
+#define AT91C_PWMC_OOVH0      (0x1 <<  0) // (PWMC) Output Override Value for PWMH output of the channel 0\r
+#define AT91C_PWMC_OOVH1      (0x1 <<  1) // (PWMC) Output Override Value for PWMH output of the channel 1\r
+#define AT91C_PWMC_OOVH2      (0x1 <<  2) // (PWMC) Output Override Value for PWMH output of the channel 2\r
+#define AT91C_PWMC_OOVH3      (0x1 <<  3) // (PWMC) Output Override Value for PWMH output of the channel 3\r
+#define AT91C_PWMC_OOVH4      (0x1 <<  4) // (PWMC) Output Override Value for PWMH output of the channel 4\r
+#define AT91C_PWMC_OOVH5      (0x1 <<  5) // (PWMC) Output Override Value for PWMH output of the channel 5\r
+#define AT91C_PWMC_OOVH6      (0x1 <<  6) // (PWMC) Output Override Value for PWMH output of the channel 6\r
+#define AT91C_PWMC_OOVH7      (0x1 <<  7) // (PWMC) Output Override Value for PWMH output of the channel 7\r
+#define AT91C_PWMC_OOVH8      (0x1 <<  8) // (PWMC) Output Override Value for PWMH output of the channel 8\r
+#define AT91C_PWMC_OOVH9      (0x1 <<  9) // (PWMC) Output Override Value for PWMH output of the channel 9\r
+#define AT91C_PWMC_OOVH10     (0x1 << 10) // (PWMC) Output Override Value for PWMH output of the channel 10\r
+#define AT91C_PWMC_OOVH11     (0x1 << 11) // (PWMC) Output Override Value for PWMH output of the channel 11\r
+#define AT91C_PWMC_OOVH12     (0x1 << 12) // (PWMC) Output Override Value for PWMH output of the channel 12\r
+#define AT91C_PWMC_OOVH13     (0x1 << 13) // (PWMC) Output Override Value for PWMH output of the channel 13\r
+#define AT91C_PWMC_OOVH14     (0x1 << 14) // (PWMC) Output Override Value for PWMH output of the channel 14\r
+#define AT91C_PWMC_OOVH15     (0x1 << 15) // (PWMC) Output Override Value for PWMH output of the channel 15\r
+#define AT91C_PWMC_OOVL0      (0x1 << 16) // (PWMC) Output Override Value for PWML output of the channel 0\r
+#define AT91C_PWMC_OOVL1      (0x1 << 17) // (PWMC) Output Override Value for PWML output of the channel 1\r
+#define AT91C_PWMC_OOVL2      (0x1 << 18) // (PWMC) Output Override Value for PWML output of the channel 2\r
+#define AT91C_PWMC_OOVL3      (0x1 << 19) // (PWMC) Output Override Value for PWML output of the channel 3\r
+#define AT91C_PWMC_OOVL4      (0x1 << 20) // (PWMC) Output Override Value for PWML output of the channel 4\r
+#define AT91C_PWMC_OOVL5      (0x1 << 21) // (PWMC) Output Override Value for PWML output of the channel 5\r
+#define AT91C_PWMC_OOVL6      (0x1 << 22) // (PWMC) Output Override Value for PWML output of the channel 6\r
+#define AT91C_PWMC_OOVL7      (0x1 << 23) // (PWMC) Output Override Value for PWML output of the channel 7\r
+#define AT91C_PWMC_OOVL8      (0x1 << 24) // (PWMC) Output Override Value for PWML output of the channel 8\r
+#define AT91C_PWMC_OOVL9      (0x1 << 25) // (PWMC) Output Override Value for PWML output of the channel 9\r
+#define AT91C_PWMC_OOVL10     (0x1 << 26) // (PWMC) Output Override Value for PWML output of the channel 10\r
+#define AT91C_PWMC_OOVL11     (0x1 << 27) // (PWMC) Output Override Value for PWML output of the channel 11\r
+#define AT91C_PWMC_OOVL12     (0x1 << 28) // (PWMC) Output Override Value for PWML output of the channel 12\r
+#define AT91C_PWMC_OOVL13     (0x1 << 29) // (PWMC) Output Override Value for PWML output of the channel 13\r
+#define AT91C_PWMC_OOVL14     (0x1 << 30) // (PWMC) Output Override Value for PWML output of the channel 14\r
+#define AT91C_PWMC_OOVL15     (0x1 << 31) // (PWMC) Output Override Value for PWML output of the channel 15\r
+// -------- PWMC_OS : (PWMC Offset: 0x48) PWM Output Selection Register -------- \r
+#define AT91C_PWMC_OSH0       (0x1 <<  0) // (PWMC) Output Selection for PWMH output of the channel 0\r
+#define AT91C_PWMC_OSH1       (0x1 <<  1) // (PWMC) Output Selection for PWMH output of the channel 1\r
+#define AT91C_PWMC_OSH2       (0x1 <<  2) // (PWMC) Output Selection for PWMH output of the channel 2\r
+#define AT91C_PWMC_OSH3       (0x1 <<  3) // (PWMC) Output Selection for PWMH output of the channel 3\r
+#define AT91C_PWMC_OSH4       (0x1 <<  4) // (PWMC) Output Selection for PWMH output of the channel 4\r
+#define AT91C_PWMC_OSH5       (0x1 <<  5) // (PWMC) Output Selection for PWMH output of the channel 5\r
+#define AT91C_PWMC_OSH6       (0x1 <<  6) // (PWMC) Output Selection for PWMH output of the channel 6\r
+#define AT91C_PWMC_OSH7       (0x1 <<  7) // (PWMC) Output Selection for PWMH output of the channel 7\r
+#define AT91C_PWMC_OSH8       (0x1 <<  8) // (PWMC) Output Selection for PWMH output of the channel 8\r
+#define AT91C_PWMC_OSH9       (0x1 <<  9) // (PWMC) Output Selection for PWMH output of the channel 9\r
+#define AT91C_PWMC_OSH10      (0x1 << 10) // (PWMC) Output Selection for PWMH output of the channel 10\r
+#define AT91C_PWMC_OSH11      (0x1 << 11) // (PWMC) Output Selection for PWMH output of the channel 11\r
+#define AT91C_PWMC_OSH12      (0x1 << 12) // (PWMC) Output Selection for PWMH output of the channel 12\r
+#define AT91C_PWMC_OSH13      (0x1 << 13) // (PWMC) Output Selection for PWMH output of the channel 13\r
+#define AT91C_PWMC_OSH14      (0x1 << 14) // (PWMC) Output Selection for PWMH output of the channel 14\r
+#define AT91C_PWMC_OSH15      (0x1 << 15) // (PWMC) Output Selection for PWMH output of the channel 15\r
+#define AT91C_PWMC_OSL0       (0x1 << 16) // (PWMC) Output Selection for PWML output of the channel 0\r
+#define AT91C_PWMC_OSL1       (0x1 << 17) // (PWMC) Output Selection for PWML output of the channel 1\r
+#define AT91C_PWMC_OSL2       (0x1 << 18) // (PWMC) Output Selection for PWML output of the channel 2\r
+#define AT91C_PWMC_OSL3       (0x1 << 19) // (PWMC) Output Selection for PWML output of the channel 3\r
+#define AT91C_PWMC_OSL4       (0x1 << 20) // (PWMC) Output Selection for PWML output of the channel 4\r
+#define AT91C_PWMC_OSL5       (0x1 << 21) // (PWMC) Output Selection for PWML output of the channel 5\r
+#define AT91C_PWMC_OSL6       (0x1 << 22) // (PWMC) Output Selection for PWML output of the channel 6\r
+#define AT91C_PWMC_OSL7       (0x1 << 23) // (PWMC) Output Selection for PWML output of the channel 7\r
+#define AT91C_PWMC_OSL8       (0x1 << 24) // (PWMC) Output Selection for PWML output of the channel 8\r
+#define AT91C_PWMC_OSL9       (0x1 << 25) // (PWMC) Output Selection for PWML output of the channel 9\r
+#define AT91C_PWMC_OSL10      (0x1 << 26) // (PWMC) Output Selection for PWML output of the channel 10\r
+#define AT91C_PWMC_OSL11      (0x1 << 27) // (PWMC) Output Selection for PWML output of the channel 11\r
+#define AT91C_PWMC_OSL12      (0x1 << 28) // (PWMC) Output Selection for PWML output of the channel 12\r
+#define AT91C_PWMC_OSL13      (0x1 << 29) // (PWMC) Output Selection for PWML output of the channel 13\r
+#define AT91C_PWMC_OSL14      (0x1 << 30) // (PWMC) Output Selection for PWML output of the channel 14\r
+#define AT91C_PWMC_OSL15      (0x1 << 31) // (PWMC) Output Selection for PWML output of the channel 15\r
+// -------- PWMC_OSS : (PWMC Offset: 0x4c) PWM Output Selection Set Register -------- \r
+#define AT91C_PWMC_OSSH0      (0x1 <<  0) // (PWMC) Output Selection Set for PWMH output of the channel 0\r
+#define AT91C_PWMC_OSSH1      (0x1 <<  1) // (PWMC) Output Selection Set for PWMH output of the channel 1\r
+#define AT91C_PWMC_OSSH2      (0x1 <<  2) // (PWMC) Output Selection Set for PWMH output of the channel 2\r
+#define AT91C_PWMC_OSSH3      (0x1 <<  3) // (PWMC) Output Selection Set for PWMH output of the channel 3\r
+#define AT91C_PWMC_OSSH4      (0x1 <<  4) // (PWMC) Output Selection Set for PWMH output of the channel 4\r
+#define AT91C_PWMC_OSSH5      (0x1 <<  5) // (PWMC) Output Selection Set for PWMH output of the channel 5\r
+#define AT91C_PWMC_OSSH6      (0x1 <<  6) // (PWMC) Output Selection Set for PWMH output of the channel 6\r
+#define AT91C_PWMC_OSSH7      (0x1 <<  7) // (PWMC) Output Selection Set for PWMH output of the channel 7\r
+#define AT91C_PWMC_OSSH8      (0x1 <<  8) // (PWMC) Output Selection Set for PWMH output of the channel 8\r
+#define AT91C_PWMC_OSSH9      (0x1 <<  9) // (PWMC) Output Selection Set for PWMH output of the channel 9\r
+#define AT91C_PWMC_OSSH10     (0x1 << 10) // (PWMC) Output Selection Set for PWMH output of the channel 10\r
+#define AT91C_PWMC_OSSH11     (0x1 << 11) // (PWMC) Output Selection Set for PWMH output of the channel 11\r
+#define AT91C_PWMC_OSSH12     (0x1 << 12) // (PWMC) Output Selection Set for PWMH output of the channel 12\r
+#define AT91C_PWMC_OSSH13     (0x1 << 13) // (PWMC) Output Selection Set for PWMH output of the channel 13\r
+#define AT91C_PWMC_OSSH14     (0x1 << 14) // (PWMC) Output Selection Set for PWMH output of the channel 14\r
+#define AT91C_PWMC_OSSH15     (0x1 << 15) // (PWMC) Output Selection Set for PWMH output of the channel 15\r
+#define AT91C_PWMC_OSSL0      (0x1 << 16) // (PWMC) Output Selection Set for PWML output of the channel 0\r
+#define AT91C_PWMC_OSSL1      (0x1 << 17) // (PWMC) Output Selection Set for PWML output of the channel 1\r
+#define AT91C_PWMC_OSSL2      (0x1 << 18) // (PWMC) Output Selection Set for PWML output of the channel 2\r
+#define AT91C_PWMC_OSSL3      (0x1 << 19) // (PWMC) Output Selection Set for PWML output of the channel 3\r
+#define AT91C_PWMC_OSSL4      (0x1 << 20) // (PWMC) Output Selection Set for PWML output of the channel 4\r
+#define AT91C_PWMC_OSSL5      (0x1 << 21) // (PWMC) Output Selection Set for PWML output of the channel 5\r
+#define AT91C_PWMC_OSSL6      (0x1 << 22) // (PWMC) Output Selection Set for PWML output of the channel 6\r
+#define AT91C_PWMC_OSSL7      (0x1 << 23) // (PWMC) Output Selection Set for PWML output of the channel 7\r
+#define AT91C_PWMC_OSSL8      (0x1 << 24) // (PWMC) Output Selection Set for PWML output of the channel 8\r
+#define AT91C_PWMC_OSSL9      (0x1 << 25) // (PWMC) Output Selection Set for PWML output of the channel 9\r
+#define AT91C_PWMC_OSSL10     (0x1 << 26) // (PWMC) Output Selection Set for PWML output of the channel 10\r
+#define AT91C_PWMC_OSSL11     (0x1 << 27) // (PWMC) Output Selection Set for PWML output of the channel 11\r
+#define AT91C_PWMC_OSSL12     (0x1 << 28) // (PWMC) Output Selection Set for PWML output of the channel 12\r
+#define AT91C_PWMC_OSSL13     (0x1 << 29) // (PWMC) Output Selection Set for PWML output of the channel 13\r
+#define AT91C_PWMC_OSSL14     (0x1 << 30) // (PWMC) Output Selection Set for PWML output of the channel 14\r
+#define AT91C_PWMC_OSSL15     (0x1 << 31) // (PWMC) Output Selection Set for PWML output of the channel 15\r
+// -------- PWMC_OSC : (PWMC Offset: 0x50) PWM Output Selection Clear Register -------- \r
+#define AT91C_PWMC_OSCH0      (0x1 <<  0) // (PWMC) Output Selection Clear for PWMH output of the channel 0\r
+#define AT91C_PWMC_OSCH1      (0x1 <<  1) // (PWMC) Output Selection Clear for PWMH output of the channel 1\r
+#define AT91C_PWMC_OSCH2      (0x1 <<  2) // (PWMC) Output Selection Clear for PWMH output of the channel 2\r
+#define AT91C_PWMC_OSCH3      (0x1 <<  3) // (PWMC) Output Selection Clear for PWMH output of the channel 3\r
+#define AT91C_PWMC_OSCH4      (0x1 <<  4) // (PWMC) Output Selection Clear for PWMH output of the channel 4\r
+#define AT91C_PWMC_OSCH5      (0x1 <<  5) // (PWMC) Output Selection Clear for PWMH output of the channel 5\r
+#define AT91C_PWMC_OSCH6      (0x1 <<  6) // (PWMC) Output Selection Clear for PWMH output of the channel 6\r
+#define AT91C_PWMC_OSCH7      (0x1 <<  7) // (PWMC) Output Selection Clear for PWMH output of the channel 7\r
+#define AT91C_PWMC_OSCH8      (0x1 <<  8) // (PWMC) Output Selection Clear for PWMH output of the channel 8\r
+#define AT91C_PWMC_OSCH9      (0x1 <<  9) // (PWMC) Output Selection Clear for PWMH output of the channel 9\r
+#define AT91C_PWMC_OSCH10     (0x1 << 10) // (PWMC) Output Selection Clear for PWMH output of the channel 10\r
+#define AT91C_PWMC_OSCH11     (0x1 << 11) // (PWMC) Output Selection Clear for PWMH output of the channel 11\r
+#define AT91C_PWMC_OSCH12     (0x1 << 12) // (PWMC) Output Selection Clear for PWMH output of the channel 12\r
+#define AT91C_PWMC_OSCH13     (0x1 << 13) // (PWMC) Output Selection Clear for PWMH output of the channel 13\r
+#define AT91C_PWMC_OSCH14     (0x1 << 14) // (PWMC) Output Selection Clear for PWMH output of the channel 14\r
+#define AT91C_PWMC_OSCH15     (0x1 << 15) // (PWMC) Output Selection Clear for PWMH output of the channel 15\r
+#define AT91C_PWMC_OSCL0      (0x1 << 16) // (PWMC) Output Selection Clear for PWML output of the channel 0\r
+#define AT91C_PWMC_OSCL1      (0x1 << 17) // (PWMC) Output Selection Clear for PWML output of the channel 1\r
+#define AT91C_PWMC_OSCL2      (0x1 << 18) // (PWMC) Output Selection Clear for PWML output of the channel 2\r
+#define AT91C_PWMC_OSCL3      (0x1 << 19) // (PWMC) Output Selection Clear for PWML output of the channel 3\r
+#define AT91C_PWMC_OSCL4      (0x1 << 20) // (PWMC) Output Selection Clear for PWML output of the channel 4\r
+#define AT91C_PWMC_OSCL5      (0x1 << 21) // (PWMC) Output Selection Clear for PWML output of the channel 5\r
+#define AT91C_PWMC_OSCL6      (0x1 << 22) // (PWMC) Output Selection Clear for PWML output of the channel 6\r
+#define AT91C_PWMC_OSCL7      (0x1 << 23) // (PWMC) Output Selection Clear for PWML output of the channel 7\r
+#define AT91C_PWMC_OSCL8      (0x1 << 24) // (PWMC) Output Selection Clear for PWML output of the channel 8\r
+#define AT91C_PWMC_OSCL9      (0x1 << 25) // (PWMC) Output Selection Clear for PWML output of the channel 9\r
+#define AT91C_PWMC_OSCL10     (0x1 << 26) // (PWMC) Output Selection Clear for PWML output of the channel 10\r
+#define AT91C_PWMC_OSCL11     (0x1 << 27) // (PWMC) Output Selection Clear for PWML output of the channel 11\r
+#define AT91C_PWMC_OSCL12     (0x1 << 28) // (PWMC) Output Selection Clear for PWML output of the channel 12\r
+#define AT91C_PWMC_OSCL13     (0x1 << 29) // (PWMC) Output Selection Clear for PWML output of the channel 13\r
+#define AT91C_PWMC_OSCL14     (0x1 << 30) // (PWMC) Output Selection Clear for PWML output of the channel 14\r
+#define AT91C_PWMC_OSCL15     (0x1 << 31) // (PWMC) Output Selection Clear for PWML output of the channel 15\r
+// -------- PWMC_OSSUPD : (PWMC Offset: 0x54) Output Selection Set for PWMH / PWML output of the channel x -------- \r
+#define AT91C_PWMC_OSSUPDH0   (0x1 <<  0) // (PWMC) Output Selection Set for PWMH output of the channel 0\r
+#define AT91C_PWMC_OSSUPDH1   (0x1 <<  1) // (PWMC) Output Selection Set for PWMH output of the channel 1\r
+#define AT91C_PWMC_OSSUPDH2   (0x1 <<  2) // (PWMC) Output Selection Set for PWMH output of the channel 2\r
+#define AT91C_PWMC_OSSUPDH3   (0x1 <<  3) // (PWMC) Output Selection Set for PWMH output of the channel 3\r
+#define AT91C_PWMC_OSSUPDH4   (0x1 <<  4) // (PWMC) Output Selection Set for PWMH output of the channel 4\r
+#define AT91C_PWMC_OSSUPDH5   (0x1 <<  5) // (PWMC) Output Selection Set for PWMH output of the channel 5\r
+#define AT91C_PWMC_OSSUPDH6   (0x1 <<  6) // (PWMC) Output Selection Set for PWMH output of the channel 6\r
+#define AT91C_PWMC_OSSUPDH7   (0x1 <<  7) // (PWMC) Output Selection Set for PWMH output of the channel 7\r
+#define AT91C_PWMC_OSSUPDH8   (0x1 <<  8) // (PWMC) Output Selection Set for PWMH output of the channel 8\r
+#define AT91C_PWMC_OSSUPDH9   (0x1 <<  9) // (PWMC) Output Selection Set for PWMH output of the channel 9\r
+#define AT91C_PWMC_OSSUPDH10  (0x1 << 10) // (PWMC) Output Selection Set for PWMH output of the channel 10\r
+#define AT91C_PWMC_OSSUPDH11  (0x1 << 11) // (PWMC) Output Selection Set for PWMH output of the channel 11\r
+#define AT91C_PWMC_OSSUPDH12  (0x1 << 12) // (PWMC) Output Selection Set for PWMH output of the channel 12\r
+#define AT91C_PWMC_OSSUPDH13  (0x1 << 13) // (PWMC) Output Selection Set for PWMH output of the channel 13\r
+#define AT91C_PWMC_OSSUPDH14  (0x1 << 14) // (PWMC) Output Selection Set for PWMH output of the channel 14\r
+#define AT91C_PWMC_OSSUPDH15  (0x1 << 15) // (PWMC) Output Selection Set for PWMH output of the channel 15\r
+#define AT91C_PWMC_OSSUPDL0   (0x1 << 16) // (PWMC) Output Selection Set for PWML output of the channel 0\r
+#define AT91C_PWMC_OSSUPDL1   (0x1 << 17) // (PWMC) Output Selection Set for PWML output of the channel 1\r
+#define AT91C_PWMC_OSSUPDL2   (0x1 << 18) // (PWMC) Output Selection Set for PWML output of the channel 2\r
+#define AT91C_PWMC_OSSUPDL3   (0x1 << 19) // (PWMC) Output Selection Set for PWML output of the channel 3\r
+#define AT91C_PWMC_OSSUPDL4   (0x1 << 20) // (PWMC) Output Selection Set for PWML output of the channel 4\r
+#define AT91C_PWMC_OSSUPDL5   (0x1 << 21) // (PWMC) Output Selection Set for PWML output of the channel 5\r
+#define AT91C_PWMC_OSSUPDL6   (0x1 << 22) // (PWMC) Output Selection Set for PWML output of the channel 6\r
+#define AT91C_PWMC_OSSUPDL7   (0x1 << 23) // (PWMC) Output Selection Set for PWML output of the channel 7\r
+#define AT91C_PWMC_OSSUPDL8   (0x1 << 24) // (PWMC) Output Selection Set for PWML output of the channel 8\r
+#define AT91C_PWMC_OSSUPDL9   (0x1 << 25) // (PWMC) Output Selection Set for PWML output of the channel 9\r
+#define AT91C_PWMC_OSSUPDL10  (0x1 << 26) // (PWMC) Output Selection Set for PWML output of the channel 10\r
+#define AT91C_PWMC_OSSUPDL11  (0x1 << 27) // (PWMC) Output Selection Set for PWML output of the channel 11\r
+#define AT91C_PWMC_OSSUPDL12  (0x1 << 28) // (PWMC) Output Selection Set for PWML output of the channel 12\r
+#define AT91C_PWMC_OSSUPDL13  (0x1 << 29) // (PWMC) Output Selection Set for PWML output of the channel 13\r
+#define AT91C_PWMC_OSSUPDL14  (0x1 << 30) // (PWMC) Output Selection Set for PWML output of the channel 14\r
+#define AT91C_PWMC_OSSUPDL15  (0x1 << 31) // (PWMC) Output Selection Set for PWML output of the channel 15\r
+// -------- PWMC_OSCUPD : (PWMC Offset: 0x58) Output Selection Clear for PWMH / PWML output of the channel x -------- \r
+#define AT91C_PWMC_OSCUPDH0   (0x1 <<  0) // (PWMC) Output Selection Clear for PWMH output of the channel 0\r
+#define AT91C_PWMC_OSCUPDH1   (0x1 <<  1) // (PWMC) Output Selection Clear for PWMH output of the channel 1\r
+#define AT91C_PWMC_OSCUPDH2   (0x1 <<  2) // (PWMC) Output Selection Clear for PWMH output of the channel 2\r
+#define AT91C_PWMC_OSCUPDH3   (0x1 <<  3) // (PWMC) Output Selection Clear for PWMH output of the channel 3\r
+#define AT91C_PWMC_OSCUPDH4   (0x1 <<  4) // (PWMC) Output Selection Clear for PWMH output of the channel 4\r
+#define AT91C_PWMC_OSCUPDH5   (0x1 <<  5) // (PWMC) Output Selection Clear for PWMH output of the channel 5\r
+#define AT91C_PWMC_OSCUPDH6   (0x1 <<  6) // (PWMC) Output Selection Clear for PWMH output of the channel 6\r
+#define AT91C_PWMC_OSCUPDH7   (0x1 <<  7) // (PWMC) Output Selection Clear for PWMH output of the channel 7\r
+#define AT91C_PWMC_OSCUPDH8   (0x1 <<  8) // (PWMC) Output Selection Clear for PWMH output of the channel 8\r
+#define AT91C_PWMC_OSCUPDH9   (0x1 <<  9) // (PWMC) Output Selection Clear for PWMH output of the channel 9\r
+#define AT91C_PWMC_OSCUPDH10  (0x1 << 10) // (PWMC) Output Selection Clear for PWMH output of the channel 10\r
+#define AT91C_PWMC_OSCUPDH11  (0x1 << 11) // (PWMC) Output Selection Clear for PWMH output of the channel 11\r
+#define AT91C_PWMC_OSCUPDH12  (0x1 << 12) // (PWMC) Output Selection Clear for PWMH output of the channel 12\r
+#define AT91C_PWMC_OSCUPDH13  (0x1 << 13) // (PWMC) Output Selection Clear for PWMH output of the channel 13\r
+#define AT91C_PWMC_OSCUPDH14  (0x1 << 14) // (PWMC) Output Selection Clear for PWMH output of the channel 14\r
+#define AT91C_PWMC_OSCUPDH15  (0x1 << 15) // (PWMC) Output Selection Clear for PWMH output of the channel 15\r
+#define AT91C_PWMC_OSCUPDL0   (0x1 << 16) // (PWMC) Output Selection Clear for PWML output of the channel 0\r
+#define AT91C_PWMC_OSCUPDL1   (0x1 << 17) // (PWMC) Output Selection Clear for PWML output of the channel 1\r
+#define AT91C_PWMC_OSCUPDL2   (0x1 << 18) // (PWMC) Output Selection Clear for PWML output of the channel 2\r
+#define AT91C_PWMC_OSCUPDL3   (0x1 << 19) // (PWMC) Output Selection Clear for PWML output of the channel 3\r
+#define AT91C_PWMC_OSCUPDL4   (0x1 << 20) // (PWMC) Output Selection Clear for PWML output of the channel 4\r
+#define AT91C_PWMC_OSCUPDL5   (0x1 << 21) // (PWMC) Output Selection Clear for PWML output of the channel 5\r
+#define AT91C_PWMC_OSCUPDL6   (0x1 << 22) // (PWMC) Output Selection Clear for PWML output of the channel 6\r
+#define AT91C_PWMC_OSCUPDL7   (0x1 << 23) // (PWMC) Output Selection Clear for PWML output of the channel 7\r
+#define AT91C_PWMC_OSCUPDL8   (0x1 << 24) // (PWMC) Output Selection Clear for PWML output of the channel 8\r
+#define AT91C_PWMC_OSCUPDL9   (0x1 << 25) // (PWMC) Output Selection Clear for PWML output of the channel 9\r
+#define AT91C_PWMC_OSCUPDL10  (0x1 << 26) // (PWMC) Output Selection Clear for PWML output of the channel 10\r
+#define AT91C_PWMC_OSCUPDL11  (0x1 << 27) // (PWMC) Output Selection Clear for PWML output of the channel 11\r
+#define AT91C_PWMC_OSCUPDL12  (0x1 << 28) // (PWMC) Output Selection Clear for PWML output of the channel 12\r
+#define AT91C_PWMC_OSCUPDL13  (0x1 << 29) // (PWMC) Output Selection Clear for PWML output of the channel 13\r
+#define AT91C_PWMC_OSCUPDL14  (0x1 << 30) // (PWMC) Output Selection Clear for PWML output of the channel 14\r
+#define AT91C_PWMC_OSCUPDL15  (0x1 << 31) // (PWMC) Output Selection Clear for PWML output of the channel 15\r
+// -------- PWMC_FMR : (PWMC Offset: 0x5c) PWM Fault Mode Register -------- \r
+#define AT91C_PWMC_FPOL0      (0x1 <<  0) // (PWMC) Fault Polarity on fault input 0\r
+#define AT91C_PWMC_FPOL1      (0x1 <<  1) // (PWMC) Fault Polarity on fault input 1\r
+#define AT91C_PWMC_FPOL2      (0x1 <<  2) // (PWMC) Fault Polarity on fault input 2\r
+#define AT91C_PWMC_FPOL3      (0x1 <<  3) // (PWMC) Fault Polarity on fault input 3\r
+#define AT91C_PWMC_FPOL4      (0x1 <<  4) // (PWMC) Fault Polarity on fault input 4\r
+#define AT91C_PWMC_FPOL5      (0x1 <<  5) // (PWMC) Fault Polarity on fault input 5\r
+#define AT91C_PWMC_FPOL6      (0x1 <<  6) // (PWMC) Fault Polarity on fault input 6\r
+#define AT91C_PWMC_FPOL7      (0x1 <<  7) // (PWMC) Fault Polarity on fault input 7\r
+#define AT91C_PWMC_FMOD0      (0x1 <<  8) // (PWMC) Fault Activation Mode on fault input 0\r
+#define AT91C_PWMC_FMOD1      (0x1 <<  9) // (PWMC) Fault Activation Mode on fault input 1\r
+#define AT91C_PWMC_FMOD2      (0x1 << 10) // (PWMC) Fault Activation Mode on fault input 2\r
+#define AT91C_PWMC_FMOD3      (0x1 << 11) // (PWMC) Fault Activation Mode on fault input 3\r
+#define AT91C_PWMC_FMOD4      (0x1 << 12) // (PWMC) Fault Activation Mode on fault input 4\r
+#define AT91C_PWMC_FMOD5      (0x1 << 13) // (PWMC) Fault Activation Mode on fault input 5\r
+#define AT91C_PWMC_FMOD6      (0x1 << 14) // (PWMC) Fault Activation Mode on fault input 6\r
+#define AT91C_PWMC_FMOD7      (0x1 << 15) // (PWMC) Fault Activation Mode on fault input 7\r
+#define AT91C_PWMC_FFIL00     (0x1 << 16) // (PWMC) Fault Filtering on fault input 0\r
+#define AT91C_PWMC_FFIL01     (0x1 << 17) // (PWMC) Fault Filtering on fault input 1\r
+#define AT91C_PWMC_FFIL02     (0x1 << 18) // (PWMC) Fault Filtering on fault input 2\r
+#define AT91C_PWMC_FFIL03     (0x1 << 19) // (PWMC) Fault Filtering on fault input 3\r
+#define AT91C_PWMC_FFIL04     (0x1 << 20) // (PWMC) Fault Filtering on fault input 4\r
+#define AT91C_PWMC_FFIL05     (0x1 << 21) // (PWMC) Fault Filtering on fault input 5\r
+#define AT91C_PWMC_FFIL06     (0x1 << 22) // (PWMC) Fault Filtering on fault input 6\r
+#define AT91C_PWMC_FFIL07     (0x1 << 23) // (PWMC) Fault Filtering on fault input 7\r
+// -------- PWMC_FSR : (PWMC Offset: 0x60) Fault Input x Value -------- \r
+#define AT91C_PWMC_FIV0       (0x1 <<  0) // (PWMC) Fault Input 0 Value\r
+#define AT91C_PWMC_FIV1       (0x1 <<  1) // (PWMC) Fault Input 1 Value\r
+#define AT91C_PWMC_FIV2       (0x1 <<  2) // (PWMC) Fault Input 2 Value\r
+#define AT91C_PWMC_FIV3       (0x1 <<  3) // (PWMC) Fault Input 3 Value\r
+#define AT91C_PWMC_FIV4       (0x1 <<  4) // (PWMC) Fault Input 4 Value\r
+#define AT91C_PWMC_FIV5       (0x1 <<  5) // (PWMC) Fault Input 5 Value\r
+#define AT91C_PWMC_FIV6       (0x1 <<  6) // (PWMC) Fault Input 6 Value\r
+#define AT91C_PWMC_FIV7       (0x1 <<  7) // (PWMC) Fault Input 7 Value\r
+#define AT91C_PWMC_FS0        (0x1 <<  8) // (PWMC) Fault 0 Status\r
+#define AT91C_PWMC_FS1        (0x1 <<  9) // (PWMC) Fault 1 Status\r
+#define AT91C_PWMC_FS2        (0x1 << 10) // (PWMC) Fault 2 Status\r
+#define AT91C_PWMC_FS3        (0x1 << 11) // (PWMC) Fault 3 Status\r
+#define AT91C_PWMC_FS4        (0x1 << 12) // (PWMC) Fault 4 Status\r
+#define AT91C_PWMC_FS5        (0x1 << 13) // (PWMC) Fault 5 Status\r
+#define AT91C_PWMC_FS6        (0x1 << 14) // (PWMC) Fault 6 Status\r
+#define AT91C_PWMC_FS7        (0x1 << 15) // (PWMC) Fault 7 Status\r
+// -------- PWMC_FCR : (PWMC Offset: 0x64) Fault y Clear -------- \r
+#define AT91C_PWMC_FCLR0      (0x1 <<  0) // (PWMC) Fault 0 Clear\r
+#define AT91C_PWMC_FCLR1      (0x1 <<  1) // (PWMC) Fault 1 Clear\r
+#define AT91C_PWMC_FCLR2      (0x1 <<  2) // (PWMC) Fault 2 Clear\r
+#define AT91C_PWMC_FCLR3      (0x1 <<  3) // (PWMC) Fault 3 Clear\r
+#define AT91C_PWMC_FCLR4      (0x1 <<  4) // (PWMC) Fault 4 Clear\r
+#define AT91C_PWMC_FCLR5      (0x1 <<  5) // (PWMC) Fault 5 Clear\r
+#define AT91C_PWMC_FCLR6      (0x1 <<  6) // (PWMC) Fault 6 Clear\r
+#define AT91C_PWMC_FCLR7      (0x1 <<  7) // (PWMC) Fault 7 Clear\r
+// -------- PWMC_FPV : (PWMC Offset: 0x68) PWM Fault Protection Value -------- \r
+#define AT91C_PWMC_FPVH0      (0x1 <<  0) // (PWMC) Fault Protection Value for PWMH output on channel 0\r
+#define AT91C_PWMC_FPVH1      (0x1 <<  1) // (PWMC) Fault Protection Value for PWMH output on channel 1\r
+#define AT91C_PWMC_FPVH2      (0x1 <<  2) // (PWMC) Fault Protection Value for PWMH output on channel 2\r
+#define AT91C_PWMC_FPVH3      (0x1 <<  3) // (PWMC) Fault Protection Value for PWMH output on channel 3\r
+#define AT91C_PWMC_FPVH4      (0x1 <<  4) // (PWMC) Fault Protection Value for PWMH output on channel 4\r
+#define AT91C_PWMC_FPVH5      (0x1 <<  5) // (PWMC) Fault Protection Value for PWMH output on channel 5\r
+#define AT91C_PWMC_FPVH6      (0x1 <<  6) // (PWMC) Fault Protection Value for PWMH output on channel 6\r
+#define AT91C_PWMC_FPVH7      (0x1 <<  7) // (PWMC) Fault Protection Value for PWMH output on channel 7\r
+#define AT91C_PWMC_FPVL0      (0x1 << 16) // (PWMC) Fault Protection Value for PWML output on channel 0\r
+#define AT91C_PWMC_FPVL1      (0x1 << 17) // (PWMC) Fault Protection Value for PWML output on channel 1\r
+#define AT91C_PWMC_FPVL2      (0x1 << 18) // (PWMC) Fault Protection Value for PWML output on channel 2\r
+#define AT91C_PWMC_FPVL3      (0x1 << 19) // (PWMC) Fault Protection Value for PWML output on channel 3\r
+#define AT91C_PWMC_FPVL4      (0x1 << 20) // (PWMC) Fault Protection Value for PWML output on channel 4\r
+#define AT91C_PWMC_FPVL5      (0x1 << 21) // (PWMC) Fault Protection Value for PWML output on channel 5\r
+#define AT91C_PWMC_FPVL6      (0x1 << 22) // (PWMC) Fault Protection Value for PWML output on channel 6\r
+#define AT91C_PWMC_FPVL7      (0x1 << 23) // (PWMC) Fault Protection Value for PWML output on channel 7\r
+// -------- PWMC_FPER1 : (PWMC Offset: 0x6c) PWM Fault Protection Enable Register 1 -------- \r
+#define AT91C_PWMC_FPE0       (0xFF <<  0) // (PWMC) Fault Protection Enable with Fault Input y for PWM channel 0\r
+#define AT91C_PWMC_FPE1       (0xFF <<  8) // (PWMC) Fault Protection Enable with Fault Input y for PWM channel 1\r
+#define AT91C_PWMC_FPE2       (0xFF << 16) // (PWMC) Fault Protection Enable with Fault Input y for PWM channel 2\r
+#define AT91C_PWMC_FPE3       (0xFF << 24) // (PWMC) Fault Protection Enable with Fault Input y for PWM channel 3\r
+// -------- PWMC_FPER2 : (PWMC Offset: 0x70) PWM Fault Protection Enable Register 2 -------- \r
+#define AT91C_PWMC_FPE4       (0xFF <<  0) // (PWMC) Fault Protection Enable with Fault Input y for PWM channel 4\r
+#define AT91C_PWMC_FPE5       (0xFF <<  8) // (PWMC) Fault Protection Enable with Fault Input y for PWM channel 5\r
+#define AT91C_PWMC_FPE6       (0xFF << 16) // (PWMC) Fault Protection Enable with Fault Input y for PWM channel 6\r
+#define AT91C_PWMC_FPE7       (0xFF << 24) // (PWMC) Fault Protection Enable with Fault Input y for PWM channel 7\r
+// -------- PWMC_FPER3 : (PWMC Offset: 0x74) PWM Fault Protection Enable Register 3 -------- \r
+#define AT91C_PWMC_FPE8       (0xFF <<  0) // (PWMC) Fault Protection Enable with Fault Input y for PWM channel 8\r
+#define AT91C_PWMC_FPE9       (0xFF <<  8) // (PWMC) Fault Protection Enable with Fault Input y for PWM channel 9\r
+#define AT91C_PWMC_FPE10      (0xFF << 16) // (PWMC) Fault Protection Enable with Fault Input y for PWM channel 10\r
+#define AT91C_PWMC_FPE11      (0xFF << 24) // (PWMC) Fault Protection Enable with Fault Input y for PWM channel 11\r
+// -------- PWMC_FPER4 : (PWMC Offset: 0x78) PWM Fault Protection Enable Register 4 -------- \r
+#define AT91C_PWMC_FPE12      (0xFF <<  0) // (PWMC) Fault Protection Enable with Fault Input y for PWM channel 12\r
+#define AT91C_PWMC_FPE13      (0xFF <<  8) // (PWMC) Fault Protection Enable with Fault Input y for PWM channel 13\r
+#define AT91C_PWMC_FPE14      (0xFF << 16) // (PWMC) Fault Protection Enable with Fault Input y for PWM channel 14\r
+#define AT91C_PWMC_FPE15      (0xFF << 24) // (PWMC) Fault Protection Enable with Fault Input y for PWM channel 15\r
+// -------- PWMC_EL0MR : (PWMC Offset: 0x7c) PWM Event Line 0 Mode Register -------- \r
+#define AT91C_PWMC_L0CSEL0    (0x1 <<  0) // (PWMC) Comparison 0 Selection\r
+#define AT91C_PWMC_L0CSEL1    (0x1 <<  1) // (PWMC) Comparison 1 Selection\r
+#define AT91C_PWMC_L0CSEL2    (0x1 <<  2) // (PWMC) Comparison 2 Selection\r
+#define AT91C_PWMC_L0CSEL3    (0x1 <<  3) // (PWMC) Comparison 3 Selection\r
+#define AT91C_PWMC_L0CSEL4    (0x1 <<  4) // (PWMC) Comparison 4 Selection\r
+#define AT91C_PWMC_L0CSEL5    (0x1 <<  5) // (PWMC) Comparison 5 Selection\r
+#define AT91C_PWMC_L0CSEL6    (0x1 <<  6) // (PWMC) Comparison 6 Selection\r
+#define AT91C_PWMC_L0CSEL7    (0x1 <<  7) // (PWMC) Comparison 7 Selection\r
+// -------- PWMC_EL1MR : (PWMC Offset: 0x80) PWM Event Line 1 Mode Register -------- \r
+#define AT91C_PWMC_L1CSEL0    (0x1 <<  0) // (PWMC) Comparison 0 Selection\r
+#define AT91C_PWMC_L1CSEL1    (0x1 <<  1) // (PWMC) Comparison 1 Selection\r
+#define AT91C_PWMC_L1CSEL2    (0x1 <<  2) // (PWMC) Comparison 2 Selection\r
+#define AT91C_PWMC_L1CSEL3    (0x1 <<  3) // (PWMC) Comparison 3 Selection\r
+#define AT91C_PWMC_L1CSEL4    (0x1 <<  4) // (PWMC) Comparison 4 Selection\r
+#define AT91C_PWMC_L1CSEL5    (0x1 <<  5) // (PWMC) Comparison 5 Selection\r
+#define AT91C_PWMC_L1CSEL6    (0x1 <<  6) // (PWMC) Comparison 6 Selection\r
+#define AT91C_PWMC_L1CSEL7    (0x1 <<  7) // (PWMC) Comparison 7 Selection\r
+// -------- PWMC_EL2MR : (PWMC Offset: 0x84) PWM Event line 2 Mode Register -------- \r
+#define AT91C_PWMC_L2CSEL0    (0x1 <<  0) // (PWMC) Comparison 0 Selection\r
+#define AT91C_PWMC_L2CSEL1    (0x1 <<  1) // (PWMC) Comparison 1 Selection\r
+#define AT91C_PWMC_L2CSEL2    (0x1 <<  2) // (PWMC) Comparison 2 Selection\r
+#define AT91C_PWMC_L2CSEL3    (0x1 <<  3) // (PWMC) Comparison 3 Selection\r
+#define AT91C_PWMC_L2CSEL4    (0x1 <<  4) // (PWMC) Comparison 4 Selection\r
+#define AT91C_PWMC_L2CSEL5    (0x1 <<  5) // (PWMC) Comparison 5 Selection\r
+#define AT91C_PWMC_L2CSEL6    (0x1 <<  6) // (PWMC) Comparison 6 Selection\r
+#define AT91C_PWMC_L2CSEL7    (0x1 <<  7) // (PWMC) Comparison 7 Selection\r
+// -------- PWMC_EL3MR : (PWMC Offset: 0x88) PWM Event line 3 Mode Register -------- \r
+#define AT91C_PWMC_L3CSEL0    (0x1 <<  0) // (PWMC) Comparison 0 Selection\r
+#define AT91C_PWMC_L3CSEL1    (0x1 <<  1) // (PWMC) Comparison 1 Selection\r
+#define AT91C_PWMC_L3CSEL2    (0x1 <<  2) // (PWMC) Comparison 2 Selection\r
+#define AT91C_PWMC_L3CSEL3    (0x1 <<  3) // (PWMC) Comparison 3 Selection\r
+#define AT91C_PWMC_L3CSEL4    (0x1 <<  4) // (PWMC) Comparison 4 Selection\r
+#define AT91C_PWMC_L3CSEL5    (0x1 <<  5) // (PWMC) Comparison 5 Selection\r
+#define AT91C_PWMC_L3CSEL6    (0x1 <<  6) // (PWMC) Comparison 6 Selection\r
+#define AT91C_PWMC_L3CSEL7    (0x1 <<  7) // (PWMC) Comparison 7 Selection\r
+// -------- PWMC_EL4MR : (PWMC Offset: 0x8c) PWM Event line 4 Mode Register -------- \r
+#define AT91C_PWMC_L4CSEL0    (0x1 <<  0) // (PWMC) Comparison 0 Selection\r
+#define AT91C_PWMC_L4CSEL1    (0x1 <<  1) // (PWMC) Comparison 1 Selection\r
+#define AT91C_PWMC_L4CSEL2    (0x1 <<  2) // (PWMC) Comparison 2 Selection\r
+#define AT91C_PWMC_L4CSEL3    (0x1 <<  3) // (PWMC) Comparison 3 Selection\r
+#define AT91C_PWMC_L4CSEL4    (0x1 <<  4) // (PWMC) Comparison 4 Selection\r
+#define AT91C_PWMC_L4CSEL5    (0x1 <<  5) // (PWMC) Comparison 5 Selection\r
+#define AT91C_PWMC_L4CSEL6    (0x1 <<  6) // (PWMC) Comparison 6 Selection\r
+#define AT91C_PWMC_L4CSEL7    (0x1 <<  7) // (PWMC) Comparison 7 Selection\r
+// -------- PWMC_EL5MR : (PWMC Offset: 0x90) PWM Event line 5 Mode Register -------- \r
+#define AT91C_PWMC_L5CSEL0    (0x1 <<  0) // (PWMC) Comparison 0 Selection\r
+#define AT91C_PWMC_L5CSEL1    (0x1 <<  1) // (PWMC) Comparison 1 Selection\r
+#define AT91C_PWMC_L5CSEL2    (0x1 <<  2) // (PWMC) Comparison 2 Selection\r
+#define AT91C_PWMC_L5CSEL3    (0x1 <<  3) // (PWMC) Comparison 3 Selection\r
+#define AT91C_PWMC_L5CSEL4    (0x1 <<  4) // (PWMC) Comparison 4 Selection\r
+#define AT91C_PWMC_L5CSEL5    (0x1 <<  5) // (PWMC) Comparison 5 Selection\r
+#define AT91C_PWMC_L5CSEL6    (0x1 <<  6) // (PWMC) Comparison 6 Selection\r
+#define AT91C_PWMC_L5CSEL7    (0x1 <<  7) // (PWMC) Comparison 7 Selection\r
+// -------- PWMC_EL6MR : (PWMC Offset: 0x94) PWM Event line 6 Mode Register -------- \r
+#define AT91C_PWMC_L6CSEL0    (0x1 <<  0) // (PWMC) Comparison 0 Selection\r
+#define AT91C_PWMC_L6CSEL1    (0x1 <<  1) // (PWMC) Comparison 1 Selection\r
+#define AT91C_PWMC_L6CSEL2    (0x1 <<  2) // (PWMC) Comparison 2 Selection\r
+#define AT91C_PWMC_L6CSEL3    (0x1 <<  3) // (PWMC) Comparison 3 Selection\r
+#define AT91C_PWMC_L6CSEL4    (0x1 <<  4) // (PWMC) Comparison 4 Selection\r
+#define AT91C_PWMC_L6CSEL5    (0x1 <<  5) // (PWMC) Comparison 5 Selection\r
+#define AT91C_PWMC_L6CSEL6    (0x1 <<  6) // (PWMC) Comparison 6 Selection\r
+#define AT91C_PWMC_L6CSEL7    (0x1 <<  7) // (PWMC) Comparison 7 Selection\r
+// -------- PWMC_EL7MR : (PWMC Offset: 0x98) PWM Event line 7 Mode Register -------- \r
+#define AT91C_PWMC_L7CSEL0    (0x1 <<  0) // (PWMC) Comparison 0 Selection\r
+#define AT91C_PWMC_L7CSEL1    (0x1 <<  1) // (PWMC) Comparison 1 Selection\r
+#define AT91C_PWMC_L7CSEL2    (0x1 <<  2) // (PWMC) Comparison 2 Selection\r
+#define AT91C_PWMC_L7CSEL3    (0x1 <<  3) // (PWMC) Comparison 3 Selection\r
+#define AT91C_PWMC_L7CSEL4    (0x1 <<  4) // (PWMC) Comparison 4 Selection\r
+#define AT91C_PWMC_L7CSEL5    (0x1 <<  5) // (PWMC) Comparison 5 Selection\r
+#define AT91C_PWMC_L7CSEL6    (0x1 <<  6) // (PWMC) Comparison 6 Selection\r
+#define AT91C_PWMC_L7CSEL7    (0x1 <<  7) // (PWMC) Comparison 7 Selection\r
+// -------- PWMC_WPCR : (PWMC Offset: 0xe4) PWM Write Protection Control Register -------- \r
+#define AT91C_PWMC_WPCMD      (0x3 <<  0) // (PWMC) Write Protection Command\r
+#define AT91C_PWMC_WPRG0      (0x1 <<  2) // (PWMC) Write Protect Register Group 0\r
+#define AT91C_PWMC_WPRG1      (0x1 <<  3) // (PWMC) Write Protect Register Group 1\r
+#define AT91C_PWMC_WPRG2      (0x1 <<  4) // (PWMC) Write Protect Register Group 2\r
+#define AT91C_PWMC_WPRG3      (0x1 <<  5) // (PWMC) Write Protect Register Group 3\r
+#define AT91C_PWMC_WPRG4      (0x1 <<  6) // (PWMC) Write Protect Register Group 4\r
+#define AT91C_PWMC_WPRG5      (0x1 <<  7) // (PWMC) Write Protect Register Group 5\r
+#define AT91C_PWMC_WPKEY      (0xFFFFFF <<  8) // (PWMC) Protection Password\r
+// -------- PWMC_WPVS : (PWMC Offset: 0xe8) Write Protection Status Register -------- \r
+#define AT91C_PWMC_WPSWS0     (0x1 <<  0) // (PWMC) Write Protect SW Group 0 Status \r
+#define AT91C_PWMC_WPSWS1     (0x1 <<  1) // (PWMC) Write Protect SW Group 1 Status \r
+#define AT91C_PWMC_WPSWS2     (0x1 <<  2) // (PWMC) Write Protect SW Group 2 Status \r
+#define AT91C_PWMC_WPSWS3     (0x1 <<  3) // (PWMC) Write Protect SW Group 3 Status \r
+#define AT91C_PWMC_WPSWS4     (0x1 <<  4) // (PWMC) Write Protect SW Group 4 Status \r
+#define AT91C_PWMC_WPSWS5     (0x1 <<  5) // (PWMC) Write Protect SW Group 5 Status \r
+#define AT91C_PWMC_WPVS       (0x1 <<  7) // (PWMC) Write Protection Enable\r
+#define AT91C_PWMC_WPHWS0     (0x1 <<  8) // (PWMC) Write Protect HW Group 0 Status \r
+#define AT91C_PWMC_WPHWS1     (0x1 <<  9) // (PWMC) Write Protect HW Group 1 Status \r
+#define AT91C_PWMC_WPHWS2     (0x1 << 10) // (PWMC) Write Protect HW Group 2 Status \r
+#define AT91C_PWMC_WPHWS3     (0x1 << 11) // (PWMC) Write Protect HW Group 3 Status \r
+#define AT91C_PWMC_WPHWS4     (0x1 << 12) // (PWMC) Write Protect HW Group 4 Status \r
+#define AT91C_PWMC_WPHWS5     (0x1 << 13) // (PWMC) Write Protect HW Group 5 Status \r
+#define AT91C_PWMC_WPVSRC     (0xFFFF << 16) // (PWMC) Write Protection Violation Source\r
+// -------- PWMC_CMP0V : (PWMC Offset: 0x130) PWM Comparison Value 0 Register -------- \r
+#define AT91C_PWMC_CV         (0xFFFFFF <<  0) // (PWMC) PWM Comparison Value 0.\r
+#define AT91C_PWMC_CVM        (0x1 << 24) // (PWMC) Comparison Value 0 Mode.\r
+// -------- PWMC_CMP0VUPD : (PWMC Offset: 0x134) PWM Comparison Value 0 Update Register -------- \r
+#define AT91C_PWMC_CVUPD      (0xFFFFFF <<  0) // (PWMC) PWM Comparison Value Update.\r
+#define AT91C_PWMC_CVMUPD     (0x1 << 24) // (PWMC) Comparison Value Update Mode.\r
+// -------- PWMC_CMP0M : (PWMC Offset: 0x138) PWM Comparison 0 Mode Register -------- \r
+#define AT91C_PWMC_CEN        (0x1 <<  0) // (PWMC) Comparison Enable.\r
+#define AT91C_PWMC_CTR        (0xF <<  4) // (PWMC) PWM Comparison Trigger.\r
+#define AT91C_PWMC_CPR        (0xF <<  8) // (PWMC) PWM Comparison Period.\r
+#define AT91C_PWMC_CPRCNT     (0xF << 12) // (PWMC) PWM Comparison Period Counter.\r
+#define AT91C_PWMC_CUPR       (0xF << 16) // (PWMC) PWM Comparison Update Period.\r
+#define AT91C_PWMC_CUPRCNT    (0xF << 20) // (PWMC) PWM Comparison Update Period Counter.\r
+// -------- PWMC_CMP0MUPD : (PWMC Offset: 0x13c) PWM Comparison 0 Mode Update Register -------- \r
+#define AT91C_PWMC_CENUPD     (0x1 <<  0) // (PWMC) Comparison Enable Update.\r
+#define AT91C_PWMC_CTRUPD     (0xF <<  4) // (PWMC) PWM Comparison Trigger Update.\r
+#define AT91C_PWMC_CPRUPD     (0xF <<  8) // (PWMC) PWM Comparison Period Update.\r
+#define AT91C_PWMC_CUPRUPD    (0xF << 16) // (PWMC) PWM Comparison Update Period Update.\r
+// -------- PWMC_CMP1V : (PWMC Offset: 0x140) PWM Comparison Value 1 Register -------- \r
+// -------- PWMC_CMP1VUPD : (PWMC Offset: 0x144) PWM Comparison Value 1 Update Register -------- \r
+// -------- PWMC_CMP1M : (PWMC Offset: 0x148) PWM Comparison 1 Mode Register -------- \r
+// -------- PWMC_CMP1MUPD : (PWMC Offset: 0x14c) PWM Comparison 1 Mode Update Register -------- \r
+// -------- PWMC_CMP2V : (PWMC Offset: 0x150) PWM Comparison Value 2 Register -------- \r
+// -------- PWMC_CMP2VUPD : (PWMC Offset: 0x154) PWM Comparison Value 2 Update Register -------- \r
+// -------- PWMC_CMP2M : (PWMC Offset: 0x158) PWM Comparison 2 Mode Register -------- \r
+// -------- PWMC_CMP2MUPD : (PWMC Offset: 0x15c) PWM Comparison 2 Mode Update Register -------- \r
+// -------- PWMC_CMP3V : (PWMC Offset: 0x160) PWM Comparison Value 3 Register -------- \r
+// -------- PWMC_CMP3VUPD : (PWMC Offset: 0x164) PWM Comparison Value 3 Update Register -------- \r
+// -------- PWMC_CMP3M : (PWMC Offset: 0x168) PWM Comparison 3 Mode Register -------- \r
+// -------- PWMC_CMP3MUPD : (PWMC Offset: 0x16c) PWM Comparison 3 Mode Update Register -------- \r
+// -------- PWMC_CMP4V : (PWMC Offset: 0x170) PWM Comparison Value 4 Register -------- \r
+// -------- PWMC_CMP4VUPD : (PWMC Offset: 0x174) PWM Comparison Value 4 Update Register -------- \r
+// -------- PWMC_CMP4M : (PWMC Offset: 0x178) PWM Comparison 4 Mode Register -------- \r
+// -------- PWMC_CMP4MUPD : (PWMC Offset: 0x17c) PWM Comparison 4 Mode Update Register -------- \r
+// -------- PWMC_CMP5V : (PWMC Offset: 0x180) PWM Comparison Value 5 Register -------- \r
+// -------- PWMC_CMP5VUPD : (PWMC Offset: 0x184) PWM Comparison Value 5 Update Register -------- \r
+// -------- PWMC_CMP5M : (PWMC Offset: 0x188) PWM Comparison 5 Mode Register -------- \r
+// -------- PWMC_CMP5MUPD : (PWMC Offset: 0x18c) PWM Comparison 5 Mode Update Register -------- \r
+// -------- PWMC_CMP6V : (PWMC Offset: 0x190) PWM Comparison Value 6 Register -------- \r
+// -------- PWMC_CMP6VUPD : (PWMC Offset: 0x194) PWM Comparison Value 6 Update Register -------- \r
+// -------- PWMC_CMP6M : (PWMC Offset: 0x198) PWM Comparison 6 Mode Register -------- \r
+// -------- PWMC_CMP6MUPD : (PWMC Offset: 0x19c) PWM Comparison 6 Mode Update Register -------- \r
+// -------- PWMC_CMP7V : (PWMC Offset: 0x1a0) PWM Comparison Value 7 Register -------- \r
+// -------- PWMC_CMP7VUPD : (PWMC Offset: 0x1a4) PWM Comparison Value 7 Update Register -------- \r
+// -------- PWMC_CMP7M : (PWMC Offset: 0x1a8) PWM Comparison 7 Mode Register -------- \r
+// -------- PWMC_CMP7MUPD : (PWMC Offset: 0x1ac) PWM Comparison 7 Mode Update Register -------- \r
+\r
+// *****************************************************************************\r
+//              SOFTWARE API DEFINITION  FOR Serial Parallel Interface\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_SPI {\r
+       AT91_REG         SPI_CR;        // Control Register\r
+       AT91_REG         SPI_MR;        // Mode Register\r
+       AT91_REG         SPI_RDR;       // Receive Data Register\r
+       AT91_REG         SPI_TDR;       // Transmit Data Register\r
+       AT91_REG         SPI_SR;        // Status Register\r
+       AT91_REG         SPI_IER;       // Interrupt Enable Register\r
+       AT91_REG         SPI_IDR;       // Interrupt Disable Register\r
+       AT91_REG         SPI_IMR;       // Interrupt Mask Register\r
+       AT91_REG         Reserved0[4];  // \r
+       AT91_REG         SPI_CSR[4];    // Chip Select Register\r
+       AT91_REG         Reserved1[43];         // \r
+       AT91_REG         SPI_ADDRSIZE;  // SPI ADDRSIZE REGISTER \r
+       AT91_REG         SPI_IPNAME1;   // SPI IPNAME1 REGISTER \r
+       AT91_REG         SPI_IPNAME2;   // SPI IPNAME2 REGISTER \r
+       AT91_REG         SPI_FEATURES;  // SPI FEATURES REGISTER \r
+       AT91_REG         SPI_VER;       // Version Register\r
+       AT91_REG         SPI_RPR;       // Receive Pointer Register\r
+       AT91_REG         SPI_RCR;       // Receive Counter Register\r
+       AT91_REG         SPI_TPR;       // Transmit Pointer Register\r
+       AT91_REG         SPI_TCR;       // Transmit Counter Register\r
+       AT91_REG         SPI_RNPR;      // Receive Next Pointer Register\r
+       AT91_REG         SPI_RNCR;      // Receive Next Counter Register\r
+       AT91_REG         SPI_TNPR;      // Transmit Next Pointer Register\r
+       AT91_REG         SPI_TNCR;      // Transmit Next Counter Register\r
+       AT91_REG         SPI_PTCR;      // PDC Transfer Control Register\r
+       AT91_REG         SPI_PTSR;      // PDC Transfer Status Register\r
+} AT91S_SPI, *AT91PS_SPI;\r
+#else\r
+#define SPI_CR          (AT91_CAST(AT91_REG *)         0x00000000) // (SPI_CR) Control Register\r
+#define SPI_MR          (AT91_CAST(AT91_REG *)         0x00000004) // (SPI_MR) Mode Register\r
+#define SPI_RDR         (AT91_CAST(AT91_REG *)         0x00000008) // (SPI_RDR) Receive Data Register\r
+#define SPI_TDR         (AT91_CAST(AT91_REG *)         0x0000000C) // (SPI_TDR) Transmit Data Register\r
+#define SPI_SR          (AT91_CAST(AT91_REG *)         0x00000010) // (SPI_SR) Status Register\r
+#define SPI_IER         (AT91_CAST(AT91_REG *)         0x00000014) // (SPI_IER) Interrupt Enable Register\r
+#define SPI_IDR         (AT91_CAST(AT91_REG *)         0x00000018) // (SPI_IDR) Interrupt Disable Register\r
+#define SPI_IMR         (AT91_CAST(AT91_REG *)         0x0000001C) // (SPI_IMR) Interrupt Mask Register\r
+#define SPI_CSR         (AT91_CAST(AT91_REG *)         0x00000030) // (SPI_CSR) Chip Select Register\r
+#define SPI_ADDRSIZE    (AT91_CAST(AT91_REG *)         0x000000EC) // (SPI_ADDRSIZE) SPI ADDRSIZE REGISTER \r
+#define SPI_IPNAME1     (AT91_CAST(AT91_REG *)         0x000000F0) // (SPI_IPNAME1) SPI IPNAME1 REGISTER \r
+#define SPI_IPNAME2     (AT91_CAST(AT91_REG *)         0x000000F4) // (SPI_IPNAME2) SPI IPNAME2 REGISTER \r
+#define SPI_FEATURES    (AT91_CAST(AT91_REG *)         0x000000F8) // (SPI_FEATURES) SPI FEATURES REGISTER \r
+#define SPI_VER         (AT91_CAST(AT91_REG *)         0x000000FC) // (SPI_VER) Version Register\r
+\r
+#endif\r
+// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- \r
+#define AT91C_SPI_SPIEN       (0x1 <<  0) // (SPI) SPI Enable\r
+#define AT91C_SPI_SPIDIS      (0x1 <<  1) // (SPI) SPI Disable\r
+#define AT91C_SPI_SWRST       (0x1 <<  7) // (SPI) SPI Software reset\r
+#define AT91C_SPI_LASTXFER    (0x1 << 24) // (SPI) SPI Last Transfer\r
+// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- \r
+#define AT91C_SPI_MSTR        (0x1 <<  0) // (SPI) Master/Slave Mode\r
+#define AT91C_SPI_PS          (0x1 <<  1) // (SPI) Peripheral Select\r
+#define        AT91C_SPI_PS_FIXED                (0x0 <<  1) // (SPI) Fixed Peripheral Select\r
+#define        AT91C_SPI_PS_VARIABLE             (0x1 <<  1) // (SPI) Variable Peripheral Select\r
+#define AT91C_SPI_PCSDEC      (0x1 <<  2) // (SPI) Chip Select Decode\r
+#define AT91C_SPI_FDIV        (0x1 <<  3) // (SPI) Clock Selection\r
+#define AT91C_SPI_MODFDIS     (0x1 <<  4) // (SPI) Mode Fault Detection\r
+#define AT91C_SPI_LLB         (0x1 <<  7) // (SPI) Clock Selection\r
+#define AT91C_SPI_PCS         (0xF << 16) // (SPI) Peripheral Chip Select\r
+#define AT91C_SPI_DLYBCS      (0xFF << 24) // (SPI) Delay Between Chip Selects\r
+// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- \r
+#define AT91C_SPI_RD          (0xFFFF <<  0) // (SPI) Receive Data\r
+#define AT91C_SPI_RPCS        (0xF << 16) // (SPI) Peripheral Chip Select Status\r
+// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- \r
+#define AT91C_SPI_TD          (0xFFFF <<  0) // (SPI) Transmit Data\r
+#define AT91C_SPI_TPCS        (0xF << 16) // (SPI) Peripheral Chip Select Status\r
+// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- \r
+#define AT91C_SPI_RDRF        (0x1 <<  0) // (SPI) Receive Data Register Full\r
+#define AT91C_SPI_TDRE        (0x1 <<  1) // (SPI) Transmit Data Register Empty\r
+#define AT91C_SPI_MODF        (0x1 <<  2) // (SPI) Mode Fault Error\r
+#define AT91C_SPI_OVRES       (0x1 <<  3) // (SPI) Overrun Error Status\r
+#define AT91C_SPI_ENDRX       (0x1 <<  4) // (SPI) End of Receiver Transfer\r
+#define AT91C_SPI_ENDTX       (0x1 <<  5) // (SPI) End of Receiver Transfer\r
+#define AT91C_SPI_RXBUFF      (0x1 <<  6) // (SPI) RXBUFF Interrupt\r
+#define AT91C_SPI_TXBUFE      (0x1 <<  7) // (SPI) TXBUFE Interrupt\r
+#define AT91C_SPI_NSSR        (0x1 <<  8) // (SPI) NSSR Interrupt\r
+#define AT91C_SPI_TXEMPTY     (0x1 <<  9) // (SPI) TXEMPTY Interrupt\r
+#define AT91C_SPI_SPIENS      (0x1 << 16) // (SPI) Enable Status\r
+// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- \r
+// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- \r
+// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- \r
+// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- \r
+#define AT91C_SPI_CPOL        (0x1 <<  0) // (SPI) Clock Polarity\r
+#define AT91C_SPI_NCPHA       (0x1 <<  1) // (SPI) Clock Phase\r
+#define AT91C_SPI_CSNAAT      (0x1 <<  2) // (SPI) Chip Select Not Active After Transfer (Ignored if CSAAT = 1)\r
+#define AT91C_SPI_CSAAT       (0x1 <<  3) // (SPI) Chip Select Active After Transfer\r
+#define AT91C_SPI_BITS        (0xF <<  4) // (SPI) Bits Per Transfer\r
+#define        AT91C_SPI_BITS_8                    (0x0 <<  4) // (SPI) 8 Bits Per transfer\r
+#define        AT91C_SPI_BITS_9                    (0x1 <<  4) // (SPI) 9 Bits Per transfer\r
+#define        AT91C_SPI_BITS_10                   (0x2 <<  4) // (SPI) 10 Bits Per transfer\r
+#define        AT91C_SPI_BITS_11                   (0x3 <<  4) // (SPI) 11 Bits Per transfer\r
+#define        AT91C_SPI_BITS_12                   (0x4 <<  4) // (SPI) 12 Bits Per transfer\r
+#define        AT91C_SPI_BITS_13                   (0x5 <<  4) // (SPI) 13 Bits Per transfer\r
+#define        AT91C_SPI_BITS_14                   (0x6 <<  4) // (SPI) 14 Bits Per transfer\r
+#define        AT91C_SPI_BITS_15                   (0x7 <<  4) // (SPI) 15 Bits Per transfer\r
+#define        AT91C_SPI_BITS_16                   (0x8 <<  4) // (SPI) 16 Bits Per transfer\r
+#define AT91C_SPI_SCBR        (0xFF <<  8) // (SPI) Serial Clock Baud Rate\r
+#define AT91C_SPI_DLYBS       (0xFF << 16) // (SPI) Serial Clock Baud Rate\r
+#define AT91C_SPI_DLYBCT      (0xFF << 24) // (SPI) Delay Between Consecutive Transfers\r
+\r
+// *****************************************************************************\r
+//              SOFTWARE API DEFINITION  FOR UDPHS Enpoint FIFO data register\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_UDPHS_EPTFIFO {\r
+       AT91_REG         UDPHS_READEPT0[16384];         // FIFO Endpoint Data Register 0\r
+       AT91_REG         UDPHS_READEPT1[16384];         // FIFO Endpoint Data Register 1\r
+       AT91_REG         UDPHS_READEPT2[16384];         // FIFO Endpoint Data Register 2\r
+       AT91_REG         UDPHS_READEPT3[16384];         // FIFO Endpoint Data Register 3\r
+       AT91_REG         UDPHS_READEPT4[16384];         // FIFO Endpoint Data Register 4\r
+       AT91_REG         UDPHS_READEPT5[16384];         // FIFO Endpoint Data Register 5\r
+       AT91_REG         UDPHS_READEPT6[16384];         // FIFO Endpoint Data Register 6\r
+} AT91S_UDPHS_EPTFIFO, *AT91PS_UDPHS_EPTFIFO;\r
+#else\r
+#define UDPHS_READEPT0  (AT91_CAST(AT91_REG *)         0x00000000) // (UDPHS_READEPT0) FIFO Endpoint Data Register 0\r
+#define UDPHS_READEPT1  (AT91_CAST(AT91_REG *)         0x00010000) // (UDPHS_READEPT1) FIFO Endpoint Data Register 1\r
+#define UDPHS_READEPT2  (AT91_CAST(AT91_REG *)         0x00020000) // (UDPHS_READEPT2) FIFO Endpoint Data Register 2\r
+#define UDPHS_READEPT3  (AT91_CAST(AT91_REG *)         0x00030000) // (UDPHS_READEPT3) FIFO Endpoint Data Register 3\r
+#define UDPHS_READEPT4  (AT91_CAST(AT91_REG *)         0x00040000) // (UDPHS_READEPT4) FIFO Endpoint Data Register 4\r
+#define UDPHS_READEPT5  (AT91_CAST(AT91_REG *)         0x00050000) // (UDPHS_READEPT5) FIFO Endpoint Data Register 5\r
+#define UDPHS_READEPT6  (AT91_CAST(AT91_REG *)         0x00060000) // (UDPHS_READEPT6) FIFO Endpoint Data Register 6\r
+\r
+#endif\r
+\r
+// *****************************************************************************\r
+//              SOFTWARE API DEFINITION  FOR UDPHS Endpoint struct\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_UDPHS_EPT {\r
+       AT91_REG         UDPHS_EPTCFG;  // UDPHS Endpoint Config Register\r
+       AT91_REG         UDPHS_EPTCTLENB;       // UDPHS Endpoint Control Enable Register\r
+       AT91_REG         UDPHS_EPTCTLDIS;       // UDPHS Endpoint Control Disable Register\r
+       AT91_REG         UDPHS_EPTCTL;  // UDPHS Endpoint Control Register\r
+       AT91_REG         Reserved0[1];  // \r
+       AT91_REG         UDPHS_EPTSETSTA;       // UDPHS Endpoint Set Status Register\r
+       AT91_REG         UDPHS_EPTCLRSTA;       // UDPHS Endpoint Clear Status Register\r
+       AT91_REG         UDPHS_EPTSTA;  // UDPHS Endpoint Status Register\r
+} AT91S_UDPHS_EPT, *AT91PS_UDPHS_EPT;\r
+#else\r
+#define UDPHS_EPTCFG    (AT91_CAST(AT91_REG *)         0x00000000) // (UDPHS_EPTCFG) UDPHS Endpoint Config Register\r
+#define UDPHS_EPTCTLENB (AT91_CAST(AT91_REG *)         0x00000004) // (UDPHS_EPTCTLENB) UDPHS Endpoint Control Enable Register\r
+#define UDPHS_EPTCTLDIS (AT91_CAST(AT91_REG *)         0x00000008) // (UDPHS_EPTCTLDIS) UDPHS Endpoint Control Disable Register\r
+#define UDPHS_EPTCTL    (AT91_CAST(AT91_REG *)         0x0000000C) // (UDPHS_EPTCTL) UDPHS Endpoint Control Register\r
+#define UDPHS_EPTSETSTA (AT91_CAST(AT91_REG *)         0x00000014) // (UDPHS_EPTSETSTA) UDPHS Endpoint Set Status Register\r
+#define UDPHS_EPTCLRSTA (AT91_CAST(AT91_REG *)         0x00000018) // (UDPHS_EPTCLRSTA) UDPHS Endpoint Clear Status Register\r
+#define UDPHS_EPTSTA    (AT91_CAST(AT91_REG *)         0x0000001C) // (UDPHS_EPTSTA) UDPHS Endpoint Status Register\r
+\r
+#endif\r
+// -------- UDPHS_EPTCFG : (UDPHS_EPT Offset: 0x0) UDPHS Endpoint Config Register -------- \r
+#define AT91C_UDPHS_EPT_SIZE  (0x7 <<  0) // (UDPHS_EPT) Endpoint Size\r
+#define        AT91C_UDPHS_EPT_SIZE_8                    (0x0) // (UDPHS_EPT)    8 bytes\r
+#define        AT91C_UDPHS_EPT_SIZE_16                   (0x1) // (UDPHS_EPT)   16 bytes\r
+#define        AT91C_UDPHS_EPT_SIZE_32                   (0x2) // (UDPHS_EPT)   32 bytes\r
+#define        AT91C_UDPHS_EPT_SIZE_64                   (0x3) // (UDPHS_EPT)   64 bytes\r
+#define        AT91C_UDPHS_EPT_SIZE_128                  (0x4) // (UDPHS_EPT)  128 bytes\r
+#define        AT91C_UDPHS_EPT_SIZE_256                  (0x5) // (UDPHS_EPT)  256 bytes (if possible)\r
+#define        AT91C_UDPHS_EPT_SIZE_512                  (0x6) // (UDPHS_EPT)  512 bytes (if possible)\r
+#define        AT91C_UDPHS_EPT_SIZE_1024                 (0x7) // (UDPHS_EPT) 1024 bytes (if possible)\r
+#define AT91C_UDPHS_EPT_DIR   (0x1 <<  3) // (UDPHS_EPT) Endpoint Direction 0:OUT, 1:IN\r
+#define        AT91C_UDPHS_EPT_DIR_OUT                  (0x0 <<  3) // (UDPHS_EPT) Direction OUT\r
+#define        AT91C_UDPHS_EPT_DIR_IN                   (0x1 <<  3) // (UDPHS_EPT) Direction IN\r
+#define AT91C_UDPHS_EPT_TYPE  (0x3 <<  4) // (UDPHS_EPT) Endpoint Type\r
+#define        AT91C_UDPHS_EPT_TYPE_CTL_EPT              (0x0 <<  4) // (UDPHS_EPT) Control endpoint\r
+#define        AT91C_UDPHS_EPT_TYPE_ISO_EPT              (0x1 <<  4) // (UDPHS_EPT) Isochronous endpoint\r
+#define        AT91C_UDPHS_EPT_TYPE_BUL_EPT              (0x2 <<  4) // (UDPHS_EPT) Bulk endpoint\r
+#define        AT91C_UDPHS_EPT_TYPE_INT_EPT              (0x3 <<  4) // (UDPHS_EPT) Interrupt endpoint\r
+#define AT91C_UDPHS_BK_NUMBER (0x3 <<  6) // (UDPHS_EPT) Number of Banks\r
+#define        AT91C_UDPHS_BK_NUMBER_0                    (0x0 <<  6) // (UDPHS_EPT) Zero Bank, the EndPoint is not mapped in memory\r
+#define        AT91C_UDPHS_BK_NUMBER_1                    (0x1 <<  6) // (UDPHS_EPT) One Bank (Bank0)\r
+#define        AT91C_UDPHS_BK_NUMBER_2                    (0x2 <<  6) // (UDPHS_EPT) Double bank (Ping-Pong : Bank0 / Bank1)\r
+#define        AT91C_UDPHS_BK_NUMBER_3                    (0x3 <<  6) // (UDPHS_EPT) Triple Bank (Bank0 / Bank1 / Bank2) (if possible)\r
+#define AT91C_UDPHS_NB_TRANS  (0x3 <<  8) // (UDPHS_EPT) Number Of Transaction per Micro-Frame (High-Bandwidth iso only)\r
+#define AT91C_UDPHS_EPT_MAPD  (0x1 << 31) // (UDPHS_EPT) Endpoint Mapped (read only\r
+// -------- UDPHS_EPTCTLENB : (UDPHS_EPT Offset: 0x4) UDPHS Endpoint Control Enable Register -------- \r
+#define AT91C_UDPHS_EPT_ENABL (0x1 <<  0) // (UDPHS_EPT) Endpoint Enable\r
+#define AT91C_UDPHS_AUTO_VALID (0x1 <<  1) // (UDPHS_EPT) Packet Auto-Valid Enable/Disable\r
+#define AT91C_UDPHS_INTDIS_DMA (0x1 <<  3) // (UDPHS_EPT) Endpoint Interrupts DMA Request Enable/Disable\r
+#define AT91C_UDPHS_NYET_DIS  (0x1 <<  4) // (UDPHS_EPT) NYET Enable/Disable\r
+#define AT91C_UDPHS_DATAX_RX  (0x1 <<  6) // (UDPHS_EPT) DATAx Interrupt Enable/Disable\r
+#define AT91C_UDPHS_MDATA_RX  (0x1 <<  7) // (UDPHS_EPT) MDATA Interrupt Enabled/Disable\r
+#define AT91C_UDPHS_ERR_OVFLW (0x1 <<  8) // (UDPHS_EPT) OverFlow Error Interrupt Enable/Disable/Status\r
+#define AT91C_UDPHS_RX_BK_RDY (0x1 <<  9) // (UDPHS_EPT) Received OUT Data\r
+#define AT91C_UDPHS_TX_COMPLT (0x1 << 10) // (UDPHS_EPT) Transmitted IN Data Complete Interrupt Enable/Disable or Transmitted IN Data Complete (clear)\r
+#define AT91C_UDPHS_ERR_TRANS (0x1 << 11) // (UDPHS_EPT) Transaction Error Interrupt Enable/Disable\r
+#define AT91C_UDPHS_TX_PK_RDY (0x1 << 11) // (UDPHS_EPT) TX Packet Ready Interrupt Enable/Disable\r
+#define AT91C_UDPHS_RX_SETUP  (0x1 << 12) // (UDPHS_EPT) Received SETUP Interrupt Enable/Disable\r
+#define AT91C_UDPHS_ERR_FL_ISO (0x1 << 12) // (UDPHS_EPT) Error Flow Clear/Interrupt Enable/Disable\r
+#define AT91C_UDPHS_STALL_SNT (0x1 << 13) // (UDPHS_EPT) Stall Sent Clear\r
+#define AT91C_UDPHS_ERR_CRISO (0x1 << 13) // (UDPHS_EPT) CRC error / Error NB Trans / Interrupt Enable/Disable\r
+#define AT91C_UDPHS_NAK_IN    (0x1 << 14) // (UDPHS_EPT) NAKIN ERROR FLUSH / Clear / Interrupt Enable/Disable\r
+#define AT91C_UDPHS_NAK_OUT   (0x1 << 15) // (UDPHS_EPT) NAKOUT / Clear / Interrupt Enable/Disable\r
+#define AT91C_UDPHS_BUSY_BANK (0x1 << 18) // (UDPHS_EPT) Busy Bank Interrupt Enable/Disable\r
+#define AT91C_UDPHS_SHRT_PCKT (0x1 << 31) // (UDPHS_EPT) Short Packet / Interrupt Enable/Disable\r
+// -------- UDPHS_EPTCTLDIS : (UDPHS_EPT Offset: 0x8) UDPHS Endpoint Control Disable Register -------- \r
+#define AT91C_UDPHS_EPT_DISABL (0x1 <<  0) // (UDPHS_EPT) Endpoint Disable\r
+// -------- UDPHS_EPTCTL : (UDPHS_EPT Offset: 0xc) UDPHS Endpoint Control Register -------- \r
+// -------- UDPHS_EPTSETSTA : (UDPHS_EPT Offset: 0x14) UDPHS Endpoint Set Status Register -------- \r
+#define AT91C_UDPHS_FRCESTALL (0x1 <<  5) // (UDPHS_EPT) Stall Handshake Request Set/Clear/Status\r
+#define AT91C_UDPHS_KILL_BANK (0x1 <<  9) // (UDPHS_EPT) KILL Bank\r
+// -------- UDPHS_EPTCLRSTA : (UDPHS_EPT Offset: 0x18) UDPHS Endpoint Clear Status Register -------- \r
+#define AT91C_UDPHS_TOGGLESQ  (0x1 <<  6) // (UDPHS_EPT) Data Toggle Clear\r
+// -------- UDPHS_EPTSTA : (UDPHS_EPT Offset: 0x1c) UDPHS Endpoint Status Register -------- \r
+#define AT91C_UDPHS_TOGGLESQ_STA (0x3 <<  6) // (UDPHS_EPT) Toggle Sequencing\r
+#define        AT91C_UDPHS_TOGGLESQ_STA_00                   (0x0 <<  6) // (UDPHS_EPT) Data0\r
+#define        AT91C_UDPHS_TOGGLESQ_STA_01                   (0x1 <<  6) // (UDPHS_EPT) Data1\r
+#define        AT91C_UDPHS_TOGGLESQ_STA_10                   (0x2 <<  6) // (UDPHS_EPT) Data2 (only for High-Bandwidth Isochronous EndPoint)\r
+#define        AT91C_UDPHS_TOGGLESQ_STA_11                   (0x3 <<  6) // (UDPHS_EPT) MData (only for High-Bandwidth Isochronous EndPoint)\r
+#define AT91C_UDPHS_CONTROL_DIR (0x3 << 16) // (UDPHS_EPT) \r
+#define        AT91C_UDPHS_CONTROL_DIR_00                   (0x0 << 16) // (UDPHS_EPT) Bank 0\r
+#define        AT91C_UDPHS_CONTROL_DIR_01                   (0x1 << 16) // (UDPHS_EPT) Bank 1\r
+#define        AT91C_UDPHS_CONTROL_DIR_10                   (0x2 << 16) // (UDPHS_EPT) Bank 2\r
+#define        AT91C_UDPHS_CONTROL_DIR_11                   (0x3 << 16) // (UDPHS_EPT) Invalid\r
+#define AT91C_UDPHS_CURRENT_BANK (0x3 << 16) // (UDPHS_EPT) \r
+#define        AT91C_UDPHS_CURRENT_BANK_00                   (0x0 << 16) // (UDPHS_EPT) Bank 0\r
+#define        AT91C_UDPHS_CURRENT_BANK_01                   (0x1 << 16) // (UDPHS_EPT) Bank 1\r
+#define        AT91C_UDPHS_CURRENT_BANK_10                   (0x2 << 16) // (UDPHS_EPT) Bank 2\r
+#define        AT91C_UDPHS_CURRENT_BANK_11                   (0x3 << 16) // (UDPHS_EPT) Invalid\r
+#define AT91C_UDPHS_BUSY_BANK_STA (0x3 << 18) // (UDPHS_EPT) Busy Bank Number\r
+#define        AT91C_UDPHS_BUSY_BANK_STA_00                   (0x0 << 18) // (UDPHS_EPT) All banks are free\r
+#define        AT91C_UDPHS_BUSY_BANK_STA_01                   (0x1 << 18) // (UDPHS_EPT) 1 busy bank\r
+#define        AT91C_UDPHS_BUSY_BANK_STA_10                   (0x2 << 18) // (UDPHS_EPT) 2 busy banks\r
+#define        AT91C_UDPHS_BUSY_BANK_STA_11                   (0x3 << 18) // (UDPHS_EPT) 3 busy banks (if possible)\r
+#define AT91C_UDPHS_BYTE_COUNT (0x7FF << 20) // (UDPHS_EPT) UDPHS Byte Count\r
+\r
+// *****************************************************************************\r
+//              SOFTWARE API DEFINITION  FOR UDPHS DMA struct\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_UDPHS_DMA {\r
+       AT91_REG         UDPHS_DMANXTDSC;       // UDPHS DMA Channel Next Descriptor Address\r
+       AT91_REG         UDPHS_DMAADDRESS;      // UDPHS DMA Channel Address Register\r
+       AT91_REG         UDPHS_DMACONTROL;      // UDPHS DMA Channel Control Register\r
+       AT91_REG         UDPHS_DMASTATUS;       // UDPHS DMA Channel Status Register\r
+} AT91S_UDPHS_DMA, *AT91PS_UDPHS_DMA;\r
+#else\r
+#define UDPHS_DMANXTDSC (AT91_CAST(AT91_REG *)         0x00000000) // (UDPHS_DMANXTDSC) UDPHS DMA Channel Next Descriptor Address\r
+#define UDPHS_DMAADDRESS (AT91_CAST(AT91_REG *)        0x00000004) // (UDPHS_DMAADDRESS) UDPHS DMA Channel Address Register\r
+#define UDPHS_DMACONTROL (AT91_CAST(AT91_REG *)        0x00000008) // (UDPHS_DMACONTROL) UDPHS DMA Channel Control Register\r
+#define UDPHS_DMASTATUS (AT91_CAST(AT91_REG *)         0x0000000C) // (UDPHS_DMASTATUS) UDPHS DMA Channel Status Register\r
+\r
+#endif\r
+// -------- UDPHS_DMANXTDSC : (UDPHS_DMA Offset: 0x0) UDPHS DMA Next Descriptor Address Register -------- \r
+#define AT91C_UDPHS_NXT_DSC_ADD (0xFFFFFFF <<  4) // (UDPHS_DMA) next Channel Descriptor\r
+// -------- UDPHS_DMAADDRESS : (UDPHS_DMA Offset: 0x4) UDPHS DMA Channel Address Register -------- \r
+#define AT91C_UDPHS_BUFF_ADD  (0x0 <<  0) // (UDPHS_DMA) starting address of a DMA Channel transfer\r
+// -------- UDPHS_DMACONTROL : (UDPHS_DMA Offset: 0x8) UDPHS DMA Channel Control Register -------- \r
+#define AT91C_UDPHS_CHANN_ENB (0x1 <<  0) // (UDPHS_DMA) Channel Enabled\r
+#define AT91C_UDPHS_LDNXT_DSC (0x1 <<  1) // (UDPHS_DMA) Load Next Channel Transfer Descriptor Enable\r
+#define AT91C_UDPHS_END_TR_EN (0x1 <<  2) // (UDPHS_DMA) Buffer Close Input Enable\r
+#define AT91C_UDPHS_END_B_EN  (0x1 <<  3) // (UDPHS_DMA) End of DMA Buffer Packet Validation\r
+#define AT91C_UDPHS_END_TR_IT (0x1 <<  4) // (UDPHS_DMA) End Of Transfer Interrupt Enable\r
+#define AT91C_UDPHS_END_BUFFIT (0x1 <<  5) // (UDPHS_DMA) End Of Channel Buffer Interrupt Enable\r
+#define AT91C_UDPHS_DESC_LD_IT (0x1 <<  6) // (UDPHS_DMA) Descriptor Loaded Interrupt Enable\r
+#define AT91C_UDPHS_BURST_LCK (0x1 <<  7) // (UDPHS_DMA) Burst Lock Enable\r
+#define AT91C_UDPHS_BUFF_LENGTH (0xFFFF << 16) // (UDPHS_DMA) Buffer Byte Length (write only)\r
+// -------- UDPHS_DMASTATUS : (UDPHS_DMA Offset: 0xc) UDPHS DMA Channelx Status Register -------- \r
+#define AT91C_UDPHS_CHANN_ACT (0x1 <<  1) // (UDPHS_DMA) \r
+#define AT91C_UDPHS_END_TR_ST (0x1 <<  4) // (UDPHS_DMA) \r
+#define AT91C_UDPHS_END_BF_ST (0x1 <<  5) // (UDPHS_DMA) \r
+#define AT91C_UDPHS_DESC_LDST (0x1 <<  6) // (UDPHS_DMA) \r
+#define AT91C_UDPHS_BUFF_COUNT (0xFFFF << 16) // (UDPHS_DMA) \r
+\r
+// *****************************************************************************\r
+//              SOFTWARE API DEFINITION  FOR UDPHS High Speed Device Interface\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_UDPHS {\r
+       AT91_REG         UDPHS_CTRL;    // UDPHS Control Register\r
+       AT91_REG         UDPHS_FNUM;    // UDPHS Frame Number Register\r
+       AT91_REG         Reserved0[2];  // \r
+       AT91_REG         UDPHS_IEN;     // UDPHS Interrupt Enable Register\r
+       AT91_REG         UDPHS_INTSTA;  // UDPHS Interrupt Status Register\r
+       AT91_REG         UDPHS_CLRINT;  // UDPHS Clear Interrupt Register\r
+       AT91_REG         UDPHS_EPTRST;  // UDPHS Endpoints Reset Register\r
+       AT91_REG         Reserved1[44];         // \r
+       AT91_REG         UDPHS_TSTSOFCNT;       // UDPHS Test SOF Counter Register\r
+       AT91_REG         UDPHS_TSTCNTA;         // UDPHS Test A Counter Register\r
+       AT91_REG         UDPHS_TSTCNTB;         // UDPHS Test B Counter Register\r
+       AT91_REG         UDPHS_TSTMODREG;       // UDPHS Test Mode Register\r
+       AT91_REG         UDPHS_TST;     // UDPHS Test Register\r
+       AT91_REG         Reserved2[2];  // \r
+       AT91_REG         UDPHS_RIPPADDRSIZE;    // UDPHS PADDRSIZE Register\r
+       AT91_REG         UDPHS_RIPNAME1;        // UDPHS Name1 Register\r
+       AT91_REG         UDPHS_RIPNAME2;        // UDPHS Name2 Register\r
+       AT91_REG         UDPHS_IPFEATURES;      // UDPHS Features Register\r
+       AT91_REG         UDPHS_IPVERSION;       // UDPHS Version Register\r
+       AT91S_UDPHS_EPT  UDPHS_EPT[7];  // UDPHS Endpoint struct\r
+       AT91_REG         Reserved3[72];         // \r
+       AT91S_UDPHS_DMA  UDPHS_DMA[6];  // UDPHS DMA channel struct (not use [0])\r
+} AT91S_UDPHS, *AT91PS_UDPHS;\r
+#else\r
+#define UDPHS_CTRL      (AT91_CAST(AT91_REG *)         0x00000000) // (UDPHS_CTRL) UDPHS Control Register\r
+#define UDPHS_FNUM      (AT91_CAST(AT91_REG *)         0x00000004) // (UDPHS_FNUM) UDPHS Frame Number Register\r
+#define UDPHS_IEN       (AT91_CAST(AT91_REG *)         0x00000010) // (UDPHS_IEN) UDPHS Interrupt Enable Register\r
+#define UDPHS_INTSTA    (AT91_CAST(AT91_REG *)         0x00000014) // (UDPHS_INTSTA) UDPHS Interrupt Status Register\r
+#define UDPHS_CLRINT    (AT91_CAST(AT91_REG *)         0x00000018) // (UDPHS_CLRINT) UDPHS Clear Interrupt Register\r
+#define UDPHS_EPTRST    (AT91_CAST(AT91_REG *)         0x0000001C) // (UDPHS_EPTRST) UDPHS Endpoints Reset Register\r
+#define UDPHS_TSTSOFCNT (AT91_CAST(AT91_REG *)         0x000000D0) // (UDPHS_TSTSOFCNT) UDPHS Test SOF Counter Register\r
+#define UDPHS_TSTCNTA   (AT91_CAST(AT91_REG *)         0x000000D4) // (UDPHS_TSTCNTA) UDPHS Test A Counter Register\r
+#define UDPHS_TSTCNTB   (AT91_CAST(AT91_REG *)         0x000000D8) // (UDPHS_TSTCNTB) UDPHS Test B Counter Register\r
+#define UDPHS_TSTMODREG (AT91_CAST(AT91_REG *)         0x000000DC) // (UDPHS_TSTMODREG) UDPHS Test Mode Register\r
+#define UDPHS_TST       (AT91_CAST(AT91_REG *)         0x000000E0) // (UDPHS_TST) UDPHS Test Register\r
+#define UDPHS_RIPPADDRSIZE (AT91_CAST(AT91_REG *)      0x000000EC) // (UDPHS_RIPPADDRSIZE) UDPHS PADDRSIZE Register\r
+#define UDPHS_RIPNAME1  (AT91_CAST(AT91_REG *)         0x000000F0) // (UDPHS_RIPNAME1) UDPHS Name1 Register\r
+#define UDPHS_RIPNAME2  (AT91_CAST(AT91_REG *)         0x000000F4) // (UDPHS_RIPNAME2) UDPHS Name2 Register\r
+#define UDPHS_IPFEATURES (AT91_CAST(AT91_REG *)        0x000000F8) // (UDPHS_IPFEATURES) UDPHS Features Register\r
+#define UDPHS_IPVERSION (AT91_CAST(AT91_REG *)         0x000000FC) // (UDPHS_IPVERSION) UDPHS Version Register\r
+\r
+#endif\r
+// -------- UDPHS_CTRL : (UDPHS Offset: 0x0) UDPHS Control Register -------- \r
+#define AT91C_UDPHS_DEV_ADDR  (0x7F <<  0) // (UDPHS) UDPHS Address\r
+#define AT91C_UDPHS_FADDR_EN  (0x1 <<  7) // (UDPHS) Function Address Enable\r
+#define AT91C_UDPHS_EN_UDPHS  (0x1 <<  8) // (UDPHS) UDPHS Enable\r
+#define AT91C_UDPHS_DETACH    (0x1 <<  9) // (UDPHS) Detach Command\r
+#define AT91C_UDPHS_REWAKEUP  (0x1 << 10) // (UDPHS) Send Remote Wake Up\r
+#define AT91C_UDPHS_PULLD_DIS (0x1 << 11) // (UDPHS) PullDown Disable\r
+// -------- UDPHS_FNUM : (UDPHS Offset: 0x4) UDPHS Frame Number Register -------- \r
+#define AT91C_UDPHS_MICRO_FRAME_NUM (0x7 <<  0) // (UDPHS) Micro Frame Number\r
+#define AT91C_UDPHS_FRAME_NUMBER (0x7FF <<  3) // (UDPHS) Frame Number as defined in the Packet Field Formats\r
+#define AT91C_UDPHS_FNUM_ERR  (0x1 << 31) // (UDPHS) Frame Number CRC Error\r
+// -------- UDPHS_IEN : (UDPHS Offset: 0x10) UDPHS Interrupt Enable Register -------- \r
+#define AT91C_UDPHS_DET_SUSPD (0x1 <<  1) // (UDPHS) Suspend Interrupt Enable/Clear/Status\r
+#define AT91C_UDPHS_MICRO_SOF (0x1 <<  2) // (UDPHS) Micro-SOF Interrupt Enable/Clear/Status\r
+#define AT91C_UDPHS_IEN_SOF   (0x1 <<  3) // (UDPHS) SOF Interrupt Enable/Clear/Status\r
+#define AT91C_UDPHS_ENDRESET  (0x1 <<  4) // (UDPHS) End Of Reset Interrupt Enable/Clear/Status\r
+#define AT91C_UDPHS_WAKE_UP   (0x1 <<  5) // (UDPHS) Wake Up CPU Interrupt Enable/Clear/Status\r
+#define AT91C_UDPHS_ENDOFRSM  (0x1 <<  6) // (UDPHS) End Of Resume Interrupt Enable/Clear/Status\r
+#define AT91C_UDPHS_UPSTR_RES (0x1 <<  7) // (UDPHS) Upstream Resume Interrupt Enable/Clear/Status\r
+#define AT91C_UDPHS_EPT_INT_0 (0x1 <<  8) // (UDPHS) Endpoint 0 Interrupt Enable/Status\r
+#define AT91C_UDPHS_EPT_INT_1 (0x1 <<  9) // (UDPHS) Endpoint 1 Interrupt Enable/Status\r
+#define AT91C_UDPHS_EPT_INT_2 (0x1 << 10) // (UDPHS) Endpoint 2 Interrupt Enable/Status\r
+#define AT91C_UDPHS_EPT_INT_3 (0x1 << 11) // (UDPHS) Endpoint 3 Interrupt Enable/Status\r
+#define AT91C_UDPHS_EPT_INT_4 (0x1 << 12) // (UDPHS) Endpoint 4 Interrupt Enable/Status\r
+#define AT91C_UDPHS_EPT_INT_5 (0x1 << 13) // (UDPHS) Endpoint 5 Interrupt Enable/Status\r
+#define AT91C_UDPHS_EPT_INT_6 (0x1 << 14) // (UDPHS) Endpoint 6 Interrupt Enable/Status\r
+#define AT91C_UDPHS_DMA_INT_1 (0x1 << 25) // (UDPHS) DMA Channel 1 Interrupt Enable/Status\r
+#define AT91C_UDPHS_DMA_INT_2 (0x1 << 26) // (UDPHS) DMA Channel 2 Interrupt Enable/Status\r
+#define AT91C_UDPHS_DMA_INT_3 (0x1 << 27) // (UDPHS) DMA Channel 3 Interrupt Enable/Status\r
+#define AT91C_UDPHS_DMA_INT_4 (0x1 << 28) // (UDPHS) DMA Channel 4 Interrupt Enable/Status\r
+#define AT91C_UDPHS_DMA_INT_5 (0x1 << 29) // (UDPHS) DMA Channel 5 Interrupt Enable/Status\r
+#define AT91C_UDPHS_DMA_INT_6 (0x1 << 30) // (UDPHS) DMA Channel 6 Interrupt Enable/Status\r
+// -------- UDPHS_INTSTA : (UDPHS Offset: 0x14) UDPHS Interrupt Status Register -------- \r
+#define AT91C_UDPHS_SPEED     (0x1 <<  0) // (UDPHS) Speed Status\r
+// -------- UDPHS_CLRINT : (UDPHS Offset: 0x18) UDPHS Clear Interrupt Register -------- \r
+// -------- UDPHS_EPTRST : (UDPHS Offset: 0x1c) UDPHS Endpoints Reset Register -------- \r
+#define AT91C_UDPHS_RST_EPT_0 (0x1 <<  0) // (UDPHS) Endpoint Reset 0\r
+#define AT91C_UDPHS_RST_EPT_1 (0x1 <<  1) // (UDPHS) Endpoint Reset 1\r
+#define AT91C_UDPHS_RST_EPT_2 (0x1 <<  2) // (UDPHS) Endpoint Reset 2\r
+#define AT91C_UDPHS_RST_EPT_3 (0x1 <<  3) // (UDPHS) Endpoint Reset 3\r
+#define AT91C_UDPHS_RST_EPT_4 (0x1 <<  4) // (UDPHS) Endpoint Reset 4\r
+#define AT91C_UDPHS_RST_EPT_5 (0x1 <<  5) // (UDPHS) Endpoint Reset 5\r
+#define AT91C_UDPHS_RST_EPT_6 (0x1 <<  6) // (UDPHS) Endpoint Reset 6\r
+// -------- UDPHS_TSTSOFCNT : (UDPHS Offset: 0xd0) UDPHS Test SOF Counter Register -------- \r
+#define AT91C_UDPHS_SOFCNTMAX (0x3 <<  0) // (UDPHS) SOF Counter Max Value\r
+#define AT91C_UDPHS_SOFCTLOAD (0x1 <<  7) // (UDPHS) SOF Counter Load\r
+// -------- UDPHS_TSTCNTA : (UDPHS Offset: 0xd4) UDPHS Test A Counter Register -------- \r
+#define AT91C_UDPHS_CNTAMAX   (0x7FFF <<  0) // (UDPHS) A Counter Max Value\r
+#define AT91C_UDPHS_CNTALOAD  (0x1 << 15) // (UDPHS) A Counter Load\r
+// -------- UDPHS_TSTCNTB : (UDPHS Offset: 0xd8) UDPHS Test B Counter Register -------- \r
+#define AT91C_UDPHS_CNTBMAX   (0x7FFF <<  0) // (UDPHS) B Counter Max Value\r
+#define AT91C_UDPHS_CNTBLOAD  (0x1 << 15) // (UDPHS) B Counter Load\r
+// -------- UDPHS_TSTMODREG : (UDPHS Offset: 0xdc) UDPHS Test Mode Register -------- \r
+#define AT91C_UDPHS_TSTMODE   (0x1F <<  1) // (UDPHS) UDPHS Core TestModeReg\r
+// -------- UDPHS_TST : (UDPHS Offset: 0xe0) UDPHS Test Register -------- \r
+#define AT91C_UDPHS_SPEED_CFG (0x3 <<  0) // (UDPHS) Speed Configuration\r
+#define        AT91C_UDPHS_SPEED_CFG_NM                   (0x0) // (UDPHS) Normal Mode\r
+#define        AT91C_UDPHS_SPEED_CFG_RS                   (0x1) // (UDPHS) Reserved\r
+#define        AT91C_UDPHS_SPEED_CFG_HS                   (0x2) // (UDPHS) Force High Speed\r
+#define        AT91C_UDPHS_SPEED_CFG_FS                   (0x3) // (UDPHS) Force Full-Speed\r
+#define AT91C_UDPHS_TST_J     (0x1 <<  2) // (UDPHS) TestJMode\r
+#define AT91C_UDPHS_TST_K     (0x1 <<  3) // (UDPHS) TestKMode\r
+#define AT91C_UDPHS_TST_PKT   (0x1 <<  4) // (UDPHS) TestPacketMode\r
+#define AT91C_UDPHS_OPMODE2   (0x1 <<  5) // (UDPHS) OpMode2\r
+// -------- UDPHS_RIPPADDRSIZE : (UDPHS Offset: 0xec) UDPHS PADDRSIZE Register -------- \r
+#define AT91C_UDPHS_IPPADDRSIZE (0x0 <<  0) // (UDPHS) 2^UDPHSDEV_PADDR_SIZE\r
+// -------- UDPHS_RIPNAME1 : (UDPHS Offset: 0xf0) UDPHS Name Register -------- \r
+#define AT91C_UDPHS_IPNAME1   (0x0 <<  0) // (UDPHS) ASCII string HUSB\r
+// -------- UDPHS_RIPNAME2 : (UDPHS Offset: 0xf4) UDPHS Name Register -------- \r
+#define AT91C_UDPHS_IPNAME2   (0x0 <<  0) // (UDPHS) ASCII string 2DEV\r
+// -------- UDPHS_IPFEATURES : (UDPHS Offset: 0xf8) UDPHS Features Register -------- \r
+#define AT91C_UDPHS_EPT_NBR_MAX (0xF <<  0) // (UDPHS) Max Number of Endpoints\r
+#define AT91C_UDPHS_DMA_CHANNEL_NBR (0x7 <<  4) // (UDPHS) Number of DMA Channels\r
+#define AT91C_UDPHS_DMA_B_SIZ (0x1 <<  7) // (UDPHS) DMA Buffer Size\r
+#define AT91C_UDPHS_DMA_FIFO_WORD_DEPTH (0xF <<  8) // (UDPHS) DMA FIFO Depth in words\r
+#define AT91C_UDPHS_FIFO_MAX_SIZE (0x7 << 12) // (UDPHS) DPRAM size\r
+#define AT91C_UDPHS_BW_DPRAM  (0x1 << 15) // (UDPHS) DPRAM byte write capability\r
+#define AT91C_UDPHS_DATAB16_8 (0x1 << 16) // (UDPHS) UTMI DataBus16_8\r
+#define AT91C_UDPHS_ISO_EPT_1 (0x1 << 17) // (UDPHS) Endpoint 1 High Bandwidth Isochronous Capability\r
+#define AT91C_UDPHS_ISO_EPT_2 (0x1 << 18) // (UDPHS) Endpoint 2 High Bandwidth Isochronous Capability\r
+#define AT91C_UDPHS_ISO_EPT_5 (0x1 << 21) // (UDPHS) Endpoint 5 High Bandwidth Isochronous Capability\r
+#define AT91C_UDPHS_ISO_EPT_6 (0x1 << 22) // (UDPHS) Endpoint 6 High Bandwidth Isochronous Capability\r
+// -------- UDPHS_IPVERSION : (UDPHS Offset: 0xfc) UDPHS Version Register -------- \r
+#define AT91C_UDPHS_VERSION_NUM (0xFFFF <<  0) // (UDPHS) Give the IP version\r
+#define AT91C_UDPHS_METAL_FIX_NUM (0x7 << 16) // (UDPHS) Give the number of metal fixes\r
+\r
+// *****************************************************************************\r
+//              SOFTWARE API DEFINITION  FOR HDMA Channel structure\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_HDMA_CH {\r
+       AT91_REG         HDMA_SADDR;    // HDMA Channel Source Address Register\r
+       AT91_REG         HDMA_DADDR;    // HDMA Channel Destination Address Register\r
+       AT91_REG         HDMA_DSCR;     // HDMA Channel Descriptor Address Register\r
+       AT91_REG         HDMA_CTRLA;    // HDMA Channel Control A Register\r
+       AT91_REG         HDMA_CTRLB;    // HDMA Channel Control B Register\r
+       AT91_REG         HDMA_CFG;      // HDMA Channel Configuration Register\r
+       AT91_REG         HDMA_SPIP;     // HDMA Channel Source Picture in Picture Configuration Register\r
+       AT91_REG         HDMA_DPIP;     // HDMA Channel Destination Picture in Picture Configuration Register\r
+       AT91_REG         HDMA_BDSCR;    // HDMA Reserved\r
+       AT91_REG         HDMA_CADDR;    // HDMA Reserved\r
+} AT91S_HDMA_CH, *AT91PS_HDMA_CH;\r
+#else\r
+#define HDMA_SADDR      (AT91_CAST(AT91_REG *)         0x00000000) // (HDMA_SADDR) HDMA Channel Source Address Register\r
+#define HDMA_DADDR      (AT91_CAST(AT91_REG *)         0x00000004) // (HDMA_DADDR) HDMA Channel Destination Address Register\r
+#define HDMA_DSCR       (AT91_CAST(AT91_REG *)         0x00000008) // (HDMA_DSCR) HDMA Channel Descriptor Address Register\r
+#define HDMA_CTRLA      (AT91_CAST(AT91_REG *)         0x0000000C) // (HDMA_CTRLA) HDMA Channel Control A Register\r
+#define HDMA_CTRLB      (AT91_CAST(AT91_REG *)         0x00000010) // (HDMA_CTRLB) HDMA Channel Control B Register\r
+#define HDMA_CFG        (AT91_CAST(AT91_REG *)         0x00000014) // (HDMA_CFG) HDMA Channel Configuration Register\r
+#define HDMA_SPIP       (AT91_CAST(AT91_REG *)         0x00000018) // (HDMA_SPIP) HDMA Channel Source Picture in Picture Configuration Register\r
+#define HDMA_DPIP       (AT91_CAST(AT91_REG *)         0x0000001C) // (HDMA_DPIP) HDMA Channel Destination Picture in Picture Configuration Register\r
+#define HDMA_BDSCR      (AT91_CAST(AT91_REG *)         0x00000020) // (HDMA_BDSCR) HDMA Reserved\r
+#define HDMA_CADDR      (AT91_CAST(AT91_REG *)         0x00000024) // (HDMA_CADDR) HDMA Reserved\r
+\r
+#endif\r
+// -------- HDMA_SADDR : (HDMA_CH Offset: 0x0)  -------- \r
+#define AT91C_SADDR           (0x0 <<  0) // (HDMA_CH) \r
+// -------- HDMA_DADDR : (HDMA_CH Offset: 0x4)  -------- \r
+#define AT91C_DADDR           (0x0 <<  0) // (HDMA_CH) \r
+// -------- HDMA_DSCR : (HDMA_CH Offset: 0x8)  -------- \r
+#define AT91C_HDMA_DSCR_IF    (0x3 <<  0) // (HDMA_CH) Select AHB-Lite Interface for current channel\r
+#define        AT91C_HDMA_DSCR_IF_0                    (0x0) // (HDMA_CH) The Buffer Transfer descriptor is fetched via AHB-Lite Interface 0.\r
+#define        AT91C_HDMA_DSCR_IF_1                    (0x1) // (HDMA_CH) The Buffer Transfer descriptor is fetched via AHB-Lite Interface 1.\r
+#define        AT91C_HDMA_DSCR_IF_2                    (0x2) // (HDMA_CH) The Buffer Transfer descriptor is fetched via AHB-Lite Interface 2.\r
+#define        AT91C_HDMA_DSCR_IF_3                    (0x3) // (HDMA_CH) The Buffer Transfer descriptor is fetched via AHB-Lite Interface 3.\r
+#define AT91C_HDMA_DSCR       (0x3FFFFFFF <<  2) // (HDMA_CH) Buffer Transfer descriptor address. This address is word aligned.\r
+// -------- HDMA_CTRLA : (HDMA_CH Offset: 0xc)  -------- \r
+#define AT91C_HDMA_BTSIZE     (0xFFFF <<  0) // (HDMA_CH) Buffer Transfer Size.\r
+#define AT91C_HDMA_SCSIZE     (0x7 << 16) // (HDMA_CH) Source Chunk Transfer Size.\r
+#define        AT91C_HDMA_SCSIZE_1                    (0x0 << 16) // (HDMA_CH) 1.\r
+#define        AT91C_HDMA_SCSIZE_4                    (0x1 << 16) // (HDMA_CH) 4.\r
+#define        AT91C_HDMA_SCSIZE_8                    (0x2 << 16) // (HDMA_CH) 8.\r
+#define        AT91C_HDMA_SCSIZE_16                   (0x3 << 16) // (HDMA_CH) 16.\r
+#define        AT91C_HDMA_SCSIZE_32                   (0x4 << 16) // (HDMA_CH) 32.\r
+#define        AT91C_HDMA_SCSIZE_64                   (0x5 << 16) // (HDMA_CH) 64.\r
+#define        AT91C_HDMA_SCSIZE_128                  (0x6 << 16) // (HDMA_CH) 128.\r
+#define        AT91C_HDMA_SCSIZE_256                  (0x7 << 16) // (HDMA_CH) 256.\r
+#define AT91C_HDMA_DCSIZE     (0x7 << 20) // (HDMA_CH) Destination Chunk Transfer Size\r
+#define        AT91C_HDMA_DCSIZE_1                    (0x0 << 20) // (HDMA_CH) 1.\r
+#define        AT91C_HDMA_DCSIZE_4                    (0x1 << 20) // (HDMA_CH) 4.\r
+#define        AT91C_HDMA_DCSIZE_8                    (0x2 << 20) // (HDMA_CH) 8.\r
+#define        AT91C_HDMA_DCSIZE_16                   (0x3 << 20) // (HDMA_CH) 16.\r
+#define        AT91C_HDMA_DCSIZE_32                   (0x4 << 20) // (HDMA_CH) 32.\r
+#define        AT91C_HDMA_DCSIZE_64                   (0x5 << 20) // (HDMA_CH) 64.\r
+#define        AT91C_HDMA_DCSIZE_128                  (0x6 << 20) // (HDMA_CH) 128.\r
+#define        AT91C_HDMA_DCSIZE_256                  (0x7 << 20) // (HDMA_CH) 256.\r
+#define AT91C_HDMA_SRC_WIDTH  (0x3 << 24) // (HDMA_CH) Source Single Transfer Size\r
+#define        AT91C_HDMA_SRC_WIDTH_BYTE                 (0x0 << 24) // (HDMA_CH) BYTE.\r
+#define        AT91C_HDMA_SRC_WIDTH_HALFWORD             (0x1 << 24) // (HDMA_CH) HALF-WORD.\r
+#define        AT91C_HDMA_SRC_WIDTH_WORD                 (0x2 << 24) // (HDMA_CH) WORD.\r
+#define AT91C_HDMA_DST_WIDTH  (0x3 << 28) // (HDMA_CH) Destination Single Transfer Size\r
+#define        AT91C_HDMA_DST_WIDTH_BYTE                 (0x0 << 28) // (HDMA_CH) BYTE.\r
+#define        AT91C_HDMA_DST_WIDTH_HALFWORD             (0x1 << 28) // (HDMA_CH) HALF-WORD.\r
+#define        AT91C_HDMA_DST_WIDTH_WORD                 (0x2 << 28) // (HDMA_CH) WORD.\r
+#define AT91C_HDMA_DONE       (0x1 << 31) // (HDMA_CH) \r
+// -------- HDMA_CTRLB : (HDMA_CH Offset: 0x10)  -------- \r
+#define AT91C_HDMA_SIF        (0x3 <<  0) // (HDMA_CH) Source Interface Selection Field.\r
+#define        AT91C_HDMA_SIF_0                    (0x0) // (HDMA_CH) The Source Transfer is done via AHB-Lite Interface 0.\r
+#define        AT91C_HDMA_SIF_1                    (0x1) // (HDMA_CH) The Source Transfer is done via AHB-Lite Interface 1.\r
+#define        AT91C_HDMA_SIF_2                    (0x2) // (HDMA_CH) The Source Transfer is done via AHB-Lite Interface 2.\r
+#define        AT91C_HDMA_SIF_3                    (0x3) // (HDMA_CH) The Source Transfer is done via AHB-Lite Interface 3.\r
+#define AT91C_HDMA_DIF        (0x3 <<  4) // (HDMA_CH) Destination Interface Selection Field.\r
+#define        AT91C_HDMA_DIF_0                    (0x0 <<  4) // (HDMA_CH) The Destination Transfer is done via AHB-Lite Interface 0.\r
+#define        AT91C_HDMA_DIF_1                    (0x1 <<  4) // (HDMA_CH) The Destination Transfer is done via AHB-Lite Interface 1.\r
+#define        AT91C_HDMA_DIF_2                    (0x2 <<  4) // (HDMA_CH) The Destination Transfer is done via AHB-Lite Interface 2.\r
+#define        AT91C_HDMA_DIF_3                    (0x3 <<  4) // (HDMA_CH) The Destination Transfer is done via AHB-Lite Interface 3.\r
+#define AT91C_HDMA_SRC_PIP    (0x1 <<  8) // (HDMA_CH) Source Picture-in-Picture Mode\r
+#define        AT91C_HDMA_SRC_PIP_DISABLE              (0x0 <<  8) // (HDMA_CH) Source Picture-in-Picture mode is disabled.\r
+#define        AT91C_HDMA_SRC_PIP_ENABLE               (0x1 <<  8) // (HDMA_CH) Source Picture-in-Picture mode is enabled.\r
+#define AT91C_HDMA_DST_PIP    (0x1 << 12) // (HDMA_CH) Destination Picture-in-Picture Mode\r
+#define        AT91C_HDMA_DST_PIP_DISABLE              (0x0 << 12) // (HDMA_CH) Destination Picture-in-Picture mode is disabled.\r
+#define        AT91C_HDMA_DST_PIP_ENABLE               (0x1 << 12) // (HDMA_CH) Destination Picture-in-Picture mode is enabled.\r
+#define AT91C_HDMA_SRC_DSCR   (0x1 << 16) // (HDMA_CH) Source Buffer Descriptor Fetch operation\r
+#define        AT91C_HDMA_SRC_DSCR_FETCH_FROM_MEM       (0x0 << 16) // (HDMA_CH) Source address is updated when the descriptor is fetched from the memory.\r
+#define        AT91C_HDMA_SRC_DSCR_FETCH_DISABLE        (0x1 << 16) // (HDMA_CH) Buffer Descriptor Fetch operation is disabled for the Source.\r
+#define AT91C_HDMA_DST_DSCR   (0x1 << 20) // (HDMA_CH) Destination Buffer Descriptor operation\r
+#define        AT91C_HDMA_DST_DSCR_FETCH_FROM_MEM       (0x0 << 20) // (HDMA_CH) Destination address is updated when the descriptor is fetched from the memory.\r
+#define        AT91C_HDMA_DST_DSCR_FETCH_DISABLE        (0x1 << 20) // (HDMA_CH) Buffer Descriptor Fetch operation is disabled for the destination.\r
+#define AT91C_HDMA_FC         (0x7 << 21) // (HDMA_CH) This field defines which devices controls the size of the buffer transfer, also referred as to the Flow Controller.\r
+#define        AT91C_HDMA_FC_MEM2MEM              (0x0 << 21) // (HDMA_CH) Memory-to-Memory (DMA Controller).\r
+#define        AT91C_HDMA_FC_MEM2PER              (0x1 << 21) // (HDMA_CH) Memory-to-Peripheral (DMA Controller).\r
+#define        AT91C_HDMA_FC_PER2MEM              (0x2 << 21) // (HDMA_CH) Peripheral-to-Memory (DMA Controller).\r
+#define        AT91C_HDMA_FC_PER2PER              (0x3 << 21) // (HDMA_CH) Peripheral-to-Peripheral (DMA Controller).\r
+#define        AT91C_HDMA_FC_PER2MEM_PER          (0x4 << 21) // (HDMA_CH) Peripheral-to-Memory (Peripheral).\r
+#define        AT91C_HDMA_FC_MEM2PER_PER          (0x5 << 21) // (HDMA_CH) Memory-to-Peripheral (Peripheral).\r
+#define        AT91C_HDMA_FC_PER2PER_PER          (0x6 << 21) // (HDMA_CH) Peripheral-to-Peripheral (Source Peripheral).\r
+#define AT91C_HDMA_SRC_ADDRESS_MODE (0x3 << 24) // (HDMA_CH) Type of addressing mode\r
+#define        AT91C_HDMA_SRC_ADDRESS_MODE_INCR                 (0x0 << 24) // (HDMA_CH) Incrementing Mode.\r
+#define        AT91C_HDMA_SRC_ADDRESS_MODE_DECR                 (0x1 << 24) // (HDMA_CH) Decrementing Mode.\r
+#define        AT91C_HDMA_SRC_ADDRESS_MODE_FIXED                (0x2 << 24) // (HDMA_CH) Fixed Mode.\r
+#define AT91C_HDMA_DST_ADDRESS_MODE (0x3 << 28) // (HDMA_CH) Type of addressing mode\r
+#define        AT91C_HDMA_DST_ADDRESS_MODE_INCR                 (0x0 << 28) // (HDMA_CH) Incrementing Mode.\r
+#define        AT91C_HDMA_DST_ADDRESS_MODE_DECR                 (0x1 << 28) // (HDMA_CH) Decrementing Mode.\r
+#define        AT91C_HDMA_DST_ADDRESS_MODE_FIXED                (0x2 << 28) // (HDMA_CH) Fixed Mode.\r
+#define AT91C_HDMA_AUTO       (0x1 << 31) // (HDMA_CH) Automatic multiple buffer transfer enable\r
+#define        AT91C_HDMA_AUTO_DISABLE              (0x0 << 31) // (HDMA_CH) Automatic multiple buffer transfer is disabled.\r
+#define        AT91C_HDMA_AUTO_ENABLE               (0x1 << 31) // (HDMA_CH) Automatic multiple buffer transfer is enabled. This enables replay mode or contiguous mode when several buffers are transferred.\r
+// -------- HDMA_CFG : (HDMA_CH Offset: 0x14)  -------- \r
+#define AT91C_HDMA_SRC_PER    (0xF <<  0) // (HDMA_CH) Channel Source Request is associated with peripheral identifier coded SRC_PER handshaking interface.\r
+#define        AT91C_HDMA_SRC_PER_0                    (0x0) // (HDMA_CH) HW Handshaking Interface number 0.\r
+#define        AT91C_HDMA_SRC_PER_1                    (0x1) // (HDMA_CH) HW Handshaking Interface number 1.\r
+#define        AT91C_HDMA_SRC_PER_2                    (0x2) // (HDMA_CH) HW Handshaking Interface number 2.\r
+#define        AT91C_HDMA_SRC_PER_3                    (0x3) // (HDMA_CH) HW Handshaking Interface number 3.\r
+#define        AT91C_HDMA_SRC_PER_4                    (0x4) // (HDMA_CH) HW Handshaking Interface number 4.\r
+#define        AT91C_HDMA_SRC_PER_5                    (0x5) // (HDMA_CH) HW Handshaking Interface number 5.\r
+#define        AT91C_HDMA_SRC_PER_6                    (0x6) // (HDMA_CH) HW Handshaking Interface number 6.\r
+#define        AT91C_HDMA_SRC_PER_7                    (0x7) // (HDMA_CH) HW Handshaking Interface number 7.\r
+#define        AT91C_HDMA_SRC_PER_8                    (0x8) // (HDMA_CH) HW Handshaking Interface number 8.\r
+#define        AT91C_HDMA_SRC_PER_9                    (0x9) // (HDMA_CH) HW Handshaking Interface number 9.\r
+#define        AT91C_HDMA_SRC_PER_10                   (0xA) // (HDMA_CH) HW Handshaking Interface number 10.\r
+#define        AT91C_HDMA_SRC_PER_11                   (0xB) // (HDMA_CH) HW Handshaking Interface number 11.\r
+#define        AT91C_HDMA_SRC_PER_12                   (0xC) // (HDMA_CH) HW Handshaking Interface number 12.\r
+#define        AT91C_HDMA_SRC_PER_13                   (0xD) // (HDMA_CH) HW Handshaking Interface number 13.\r
+#define        AT91C_HDMA_SRC_PER_14                   (0xE) // (HDMA_CH) HW Handshaking Interface number 14.\r
+#define        AT91C_HDMA_SRC_PER_15                   (0xF) // (HDMA_CH) HW Handshaking Interface number 15.\r
+#define AT91C_HDMA_DST_PER    (0xF <<  4) // (HDMA_CH) Channel Destination Request is associated with peripheral identifier coded DST_PER handshaking interface.\r
+#define        AT91C_HDMA_DST_PER_0                    (0x0 <<  4) // (HDMA_CH) HW Handshaking Interface number 0.\r
+#define        AT91C_HDMA_DST_PER_1                    (0x1 <<  4) // (HDMA_CH) HW Handshaking Interface number 1.\r
+#define        AT91C_HDMA_DST_PER_2                    (0x2 <<  4) // (HDMA_CH) HW Handshaking Interface number 2.\r
+#define        AT91C_HDMA_DST_PER_3                    (0x3 <<  4) // (HDMA_CH) HW Handshaking Interface number 3.\r
+#define        AT91C_HDMA_DST_PER_4                    (0x4 <<  4) // (HDMA_CH) HW Handshaking Interface number 4.\r
+#define        AT91C_HDMA_DST_PER_5                    (0x5 <<  4) // (HDMA_CH) HW Handshaking Interface number 5.\r
+#define        AT91C_HDMA_DST_PER_6                    (0x6 <<  4) // (HDMA_CH) HW Handshaking Interface number 6.\r
+#define        AT91C_HDMA_DST_PER_7                    (0x7 <<  4) // (HDMA_CH) HW Handshaking Interface number 7.\r
+#define        AT91C_HDMA_DST_PER_8                    (0x8 <<  4) // (HDMA_CH) HW Handshaking Interface number 8.\r
+#define        AT91C_HDMA_DST_PER_9                    (0x9 <<  4) // (HDMA_CH) HW Handshaking Interface number 9.\r
+#define        AT91C_HDMA_DST_PER_10                   (0xA <<  4) // (HDMA_CH) HW Handshaking Interface number 10.\r
+#define        AT91C_HDMA_DST_PER_11                   (0xB <<  4) // (HDMA_CH) HW Handshaking Interface number 11.\r
+#define        AT91C_HDMA_DST_PER_12                   (0xC <<  4) // (HDMA_CH) HW Handshaking Interface number 12.\r
+#define        AT91C_HDMA_DST_PER_13                   (0xD <<  4) // (HDMA_CH) HW Handshaking Interface number 13.\r
+#define        AT91C_HDMA_DST_PER_14                   (0xE <<  4) // (HDMA_CH) HW Handshaking Interface number 14.\r
+#define        AT91C_HDMA_DST_PER_15                   (0xF <<  4) // (HDMA_CH) HW Handshaking Interface number 15.\r
+#define AT91C_HDMA_SRC_REP    (0x1 <<  8) // (HDMA_CH) Source Replay Mode\r
+#define        AT91C_HDMA_SRC_REP_CONTIGUOUS_ADDR      (0x0 <<  8) // (HDMA_CH) When automatic mode is activated, source address is contiguous between two buffers.\r
+#define        AT91C_HDMA_SRC_REP_RELOAD_ADDR          (0x1 <<  8) // (HDMA_CH) When automatic mode is activated, the source address and the control register are reloaded from previous transfer..\r
+#define AT91C_HDMA_SRC_H2SEL  (0x1 <<  9) // (HDMA_CH) Source Handshaking Mode\r
+#define        AT91C_HDMA_SRC_H2SEL_SW                   (0x0 <<  9) // (HDMA_CH) Software handshaking interface is used to trigger a transfer request.\r
+#define        AT91C_HDMA_SRC_H2SEL_HW                   (0x1 <<  9) // (HDMA_CH) Hardware handshaking interface is used to trigger a transfer request.\r
+#define AT91C_HDMA_DST_REP    (0x1 << 12) // (HDMA_CH) Destination Replay Mode\r
+#define        AT91C_HDMA_DST_REP_CONTIGUOUS_ADDR      (0x0 << 12) // (HDMA_CH) When automatic mode is activated, destination address is contiguous between two buffers.\r
+#define        AT91C_HDMA_DST_REP_RELOAD_ADDR          (0x1 << 12) // (HDMA_CH) When automatic mode is activated, the destination address and the control register are reloaded from previous transfer..\r
+#define AT91C_HDMA_DST_H2SEL  (0x1 << 13) // (HDMA_CH) Destination Handshaking Mode\r
+#define        AT91C_HDMA_DST_H2SEL_SW                   (0x0 << 13) // (HDMA_CH) Software handshaking interface is used to trigger a transfer request.\r
+#define        AT91C_HDMA_DST_H2SEL_HW                   (0x1 << 13) // (HDMA_CH) Hardware handshaking interface is used to trigger a transfer request.\r
+#define AT91C_HDMA_SOD        (0x1 << 16) // (HDMA_CH) STOP ON DONE\r
+#define        AT91C_HDMA_SOD_DISABLE              (0x0 << 16) // (HDMA_CH) STOP ON DONE disabled, the descriptor fetch operation ignores DONE Field of CTRLA register.\r
+#define        AT91C_HDMA_SOD_ENABLE               (0x1 << 16) // (HDMA_CH) STOP ON DONE activated, the DMAC module is automatically disabled if DONE FIELD is set to 1.\r
+#define AT91C_HDMA_LOCK_IF    (0x1 << 20) // (HDMA_CH) Interface Lock\r
+#define        AT91C_HDMA_LOCK_IF_DISABLE              (0x0 << 20) // (HDMA_CH) Interface Lock capability is disabled.\r
+#define        AT91C_HDMA_LOCK_IF_ENABLE               (0x1 << 20) // (HDMA_CH) Interface Lock capability is enabled.\r
+#define AT91C_HDMA_LOCK_B     (0x1 << 21) // (HDMA_CH) AHB Bus Lock\r
+#define        AT91C_HDMA_LOCK_B_DISABLE              (0x0 << 21) // (HDMA_CH) AHB Bus Locking capability is disabled.\r
+#define        AT91C_HDMA_LOCK_B_ENABLE               (0x1 << 21) // (HDMA_CH) AHB Bus Locking capability is enabled.\r
+#define AT91C_HDMA_LOCK_IF_L  (0x1 << 22) // (HDMA_CH) Master Interface Arbiter Lock\r
+#define        AT91C_HDMA_LOCK_IF_L_CHUNK                (0x0 << 22) // (HDMA_CH) The Master Interface Arbiter is locked by the channel x for a chunk transfer.\r
+#define        AT91C_HDMA_LOCK_IF_L_BUFFER               (0x1 << 22) // (HDMA_CH) The Master Interface Arbiter is locked by the channel x for a buffer transfer.\r
+#define AT91C_HDMA_AHB_PROT   (0x7 << 24) // (HDMA_CH) AHB Prot\r
+#define AT91C_HDMA_FIFOCFG    (0x3 << 28) // (HDMA_CH) FIFO Request Configuration\r
+#define        AT91C_HDMA_FIFOCFG_LARGESTBURST         (0x0 << 28) // (HDMA_CH) The largest defined length AHB burst is performed on the destination AHB interface.\r
+#define        AT91C_HDMA_FIFOCFG_HALFFIFO             (0x1 << 28) // (HDMA_CH) When half fifo size is available/filled a source/destination request is serviced.\r
+#define        AT91C_HDMA_FIFOCFG_ENOUGHSPACE          (0x2 << 28) // (HDMA_CH) When there is enough space/data available to perfom a single AHB access then the request is serviced.\r
+// -------- HDMA_SPIP : (HDMA_CH Offset: 0x18)  -------- \r
+#define AT91C_SPIP_HOLE       (0xFFFF <<  0) // (HDMA_CH) This field indicates the value to add to the address when the programmable boundary has been reached.\r
+#define AT91C_SPIP_BOUNDARY   (0x3FF << 16) // (HDMA_CH) This field indicates the number of source transfers to perform before the automatic address increment operation.\r
+// -------- HDMA_DPIP : (HDMA_CH Offset: 0x1c)  -------- \r
+#define AT91C_DPIP_HOLE       (0xFFFF <<  0) // (HDMA_CH) This field indicates the value to add to the address when the programmable boundary has been reached.\r
+#define AT91C_DPIP_BOUNDARY   (0x3FF << 16) // (HDMA_CH) This field indicates the number of source transfers to perform before the automatic address increment operation.\r
+// -------- HDMA_BDSCR : (HDMA_CH Offset: 0x20)  -------- \r
+// -------- HDMA_CADDR : (HDMA_CH Offset: 0x24)  -------- \r
+\r
+// *****************************************************************************\r
+//              SOFTWARE API DEFINITION  FOR HDMA controller\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_HDMA {\r
+       AT91_REG         HDMA_GCFG;     // HDMA Global Configuration Register\r
+       AT91_REG         HDMA_EN;       // HDMA Controller Enable Register\r
+       AT91_REG         HDMA_SREQ;     // HDMA Software Single Request Register\r
+       AT91_REG         HDMA_CREQ;     // HDMA Software Chunk Transfer Request Register\r
+       AT91_REG         HDMA_LAST;     // HDMA Software Last Transfer Flag Register\r
+       AT91_REG         HDMA_SYNC;     // HDMA Request Synchronization Register\r
+       AT91_REG         HDMA_EBCIER;   // HDMA Error, Chained Buffer transfer completed and Buffer transfer completed Interrupt Enable register\r
+       AT91_REG         HDMA_EBCIDR;   // HDMA Error, Chained Buffer transfer completed and Buffer transfer completed Interrupt Disable register\r
+       AT91_REG         HDMA_EBCIMR;   // HDMA Error, Chained Buffer transfer completed and Buffer transfer completed Mask Register\r
+       AT91_REG         HDMA_EBCISR;   // HDMA Error, Chained Buffer transfer completed and Buffer transfer completed Status Register\r
+       AT91_REG         HDMA_CHER;     // HDMA Channel Handler Enable Register\r
+       AT91_REG         HDMA_CHDR;     // HDMA Channel Handler Disable Register\r
+       AT91_REG         HDMA_CHSR;     // HDMA Channel Handler Status Register\r
+       AT91_REG         HDMA_RSVD0;    // HDMA Reserved\r
+       AT91_REG         HDMA_RSVD1;    // HDMA Reserved\r
+       AT91S_HDMA_CH    HDMA_CH[4];    // HDMA Channel structure\r
+       AT91_REG         Reserved0[68];         // \r
+       AT91_REG         HDMA_ADDRSIZE;         // HDMA ADDRSIZE REGISTER \r
+       AT91_REG         HDMA_IPNAME1;  // HDMA IPNAME1 REGISTER \r
+       AT91_REG         HDMA_IPNAME2;  // HDMA IPNAME2 REGISTER \r
+       AT91_REG         HDMA_FEATURES;         // HDMA FEATURES REGISTER \r
+       AT91_REG         HDMA_VER;      // HDMA VERSION REGISTER \r
+} AT91S_HDMA, *AT91PS_HDMA;\r
+#else\r
+#define HDMA_GCFG       (AT91_CAST(AT91_REG *)         0x00000000) // (HDMA_GCFG) HDMA Global Configuration Register\r
+#define HDMA_EN         (AT91_CAST(AT91_REG *)         0x00000004) // (HDMA_EN) HDMA Controller Enable Register\r
+#define HDMA_SREQ       (AT91_CAST(AT91_REG *)         0x00000008) // (HDMA_SREQ) HDMA Software Single Request Register\r
+#define HDMA_CREQ       (AT91_CAST(AT91_REG *)         0x0000000C) // (HDMA_CREQ) HDMA Software Chunk Transfer Request Register\r
+#define HDMA_LAST       (AT91_CAST(AT91_REG *)         0x00000010) // (HDMA_LAST) HDMA Software Last Transfer Flag Register\r
+#define HDMA_SYNC       (AT91_CAST(AT91_REG *)         0x00000014) // (HDMA_SYNC) HDMA Request Synchronization Register\r
+#define HDMA_EBCIER     (AT91_CAST(AT91_REG *)         0x00000018) // (HDMA_EBCIER) HDMA Error, Chained Buffer transfer completed and Buffer transfer completed Interrupt Enable register\r
+#define HDMA_EBCIDR     (AT91_CAST(AT91_REG *)         0x0000001C) // (HDMA_EBCIDR) HDMA Error, Chained Buffer transfer completed and Buffer transfer completed Interrupt Disable register\r
+#define HDMA_EBCIMR     (AT91_CAST(AT91_REG *)         0x00000020) // (HDMA_EBCIMR) HDMA Error, Chained Buffer transfer completed and Buffer transfer completed Mask Register\r
+#define HDMA_EBCISR     (AT91_CAST(AT91_REG *)         0x00000024) // (HDMA_EBCISR) HDMA Error, Chained Buffer transfer completed and Buffer transfer completed Status Register\r
+#define HDMA_CHER       (AT91_CAST(AT91_REG *)         0x00000028) // (HDMA_CHER) HDMA Channel Handler Enable Register\r
+#define HDMA_CHDR       (AT91_CAST(AT91_REG *)         0x0000002C) // (HDMA_CHDR) HDMA Channel Handler Disable Register\r
+#define HDMA_CHSR       (AT91_CAST(AT91_REG *)         0x00000030) // (HDMA_CHSR) HDMA Channel Handler Status Register\r
+#define HDMA_RSVD0      (AT91_CAST(AT91_REG *)         0x00000034) // (HDMA_RSVD0) HDMA Reserved\r
+#define HDMA_RSVD1      (AT91_CAST(AT91_REG *)         0x00000038) // (HDMA_RSVD1) HDMA Reserved\r
+#define HDMA_ADDRSIZE   (AT91_CAST(AT91_REG *)         0x000001EC) // (HDMA_ADDRSIZE) HDMA ADDRSIZE REGISTER \r
+#define HDMA_IPNAME1    (AT91_CAST(AT91_REG *)         0x000001F0) // (HDMA_IPNAME1) HDMA IPNAME1 REGISTER \r
+#define HDMA_IPNAME2    (AT91_CAST(AT91_REG *)         0x000001F4) // (HDMA_IPNAME2) HDMA IPNAME2 REGISTER \r
+#define HDMA_FEATURES   (AT91_CAST(AT91_REG *)         0x000001F8) // (HDMA_FEATURES) HDMA FEATURES REGISTER \r
+#define HDMA_VER        (AT91_CAST(AT91_REG *)         0x000001FC) // (HDMA_VER) HDMA VERSION REGISTER \r
+\r
+#endif\r
+// -------- HDMA_GCFG : (HDMA Offset: 0x0)  -------- \r
+#define AT91C_HDMA_IF0_BIGEND (0x1 <<  0) // (HDMA) AHB-Lite Interface 0 endian mode.\r
+#define        AT91C_HDMA_IF0_BIGEND_IS_LITTLE_ENDIAN     (0x0) // (HDMA) AHB-Lite Interface 0 is little endian.\r
+#define        AT91C_HDMA_IF0_BIGEND_IS_BIG_ENDIAN        (0x1) // (HDMA) AHB-Lite Interface 0 is big endian.\r
+#define AT91C_HDMA_IF1_BIGEND (0x1 <<  1) // (HDMA) AHB-Lite Interface 1 endian mode.\r
+#define        AT91C_HDMA_IF1_BIGEND_IS_LITTLE_ENDIAN     (0x0 <<  1) // (HDMA) AHB-Lite Interface 1 is little endian.\r
+#define        AT91C_HDMA_IF1_BIGEND_IS_BIG_ENDIAN        (0x1 <<  1) // (HDMA) AHB-Lite Interface 1 is big endian.\r
+#define AT91C_HDMA_IF2_BIGEND (0x1 <<  2) // (HDMA) AHB-Lite Interface 2 endian mode.\r
+#define        AT91C_HDMA_IF2_BIGEND_IS_LITTLE_ENDIAN     (0x0 <<  2) // (HDMA) AHB-Lite Interface 2 is little endian.\r
+#define        AT91C_HDMA_IF2_BIGEND_IS_BIG_ENDIAN        (0x1 <<  2) // (HDMA) AHB-Lite Interface 2 is big endian.\r
+#define AT91C_HDMA_IF3_BIGEND (0x1 <<  3) // (HDMA) AHB-Lite Interface 3 endian mode.\r
+#define        AT91C_HDMA_IF3_BIGEND_IS_LITTLE_ENDIAN     (0x0 <<  3) // (HDMA) AHB-Lite Interface 3 is little endian.\r
+#define        AT91C_HDMA_IF3_BIGEND_IS_BIG_ENDIAN        (0x1 <<  3) // (HDMA) AHB-Lite Interface 3 is big endian.\r
+#define AT91C_HDMA_ARB_CFG    (0x1 <<  4) // (HDMA) Arbiter mode.\r
+#define        AT91C_HDMA_ARB_CFG_FIXED                (0x0 <<  4) // (HDMA) Fixed priority arbiter.\r
+#define        AT91C_HDMA_ARB_CFG_ROUND_ROBIN          (0x1 <<  4) // (HDMA) Modified round robin arbiter.\r
+// -------- HDMA_EN : (HDMA Offset: 0x4)  -------- \r
+#define AT91C_HDMA_ENABLE     (0x1 <<  0) // (HDMA) \r
+#define        AT91C_HDMA_ENABLE_DISABLE              (0x0) // (HDMA) Disables HDMA.\r
+#define        AT91C_HDMA_ENABLE_ENABLE               (0x1) // (HDMA) Enables HDMA.\r
+// -------- HDMA_SREQ : (HDMA Offset: 0x8)  -------- \r
+#define AT91C_HDMA_SSREQ0     (0x1 <<  0) // (HDMA) Request a source single transfer on channel 0\r
+#define        AT91C_HDMA_SSREQ0_0                    (0x0) // (HDMA) No effect.\r
+#define        AT91C_HDMA_SSREQ0_1                    (0x1) // (HDMA) Request a source single transfer on channel 0.\r
+#define AT91C_HDMA_DSREQ0     (0x1 <<  1) // (HDMA) Request a destination single transfer on channel 0\r
+#define        AT91C_HDMA_DSREQ0_0                    (0x0 <<  1) // (HDMA) No effect.\r
+#define        AT91C_HDMA_DSREQ0_1                    (0x1 <<  1) // (HDMA) Request a destination single transfer on channel 0.\r
+#define AT91C_HDMA_SSREQ1     (0x1 <<  2) // (HDMA) Request a source single transfer on channel 1\r
+#define        AT91C_HDMA_SSREQ1_0                    (0x0 <<  2) // (HDMA) No effect.\r
+#define        AT91C_HDMA_SSREQ1_1                    (0x1 <<  2) // (HDMA) Request a source single transfer on channel 1.\r
+#define AT91C_HDMA_DSREQ1     (0x1 <<  3) // (HDMA) Request a destination single transfer on channel 1\r
+#define        AT91C_HDMA_DSREQ1_0                    (0x0 <<  3) // (HDMA) No effect.\r
+#define        AT91C_HDMA_DSREQ1_1                    (0x1 <<  3) // (HDMA) Request a destination single transfer on channel 1.\r
+#define AT91C_HDMA_SSREQ2     (0x1 <<  4) // (HDMA) Request a source single transfer on channel 2\r
+#define        AT91C_HDMA_SSREQ2_0                    (0x0 <<  4) // (HDMA) No effect.\r
+#define        AT91C_HDMA_SSREQ2_1                    (0x1 <<  4) // (HDMA) Request a source single transfer on channel 2.\r
+#define AT91C_HDMA_DSREQ2     (0x1 <<  5) // (HDMA) Request a destination single transfer on channel 2\r
+#define        AT91C_HDMA_DSREQ2_0                    (0x0 <<  5) // (HDMA) No effect.\r
+#define        AT91C_HDMA_DSREQ2_1                    (0x1 <<  5) // (HDMA) Request a destination single transfer on channel 2.\r
+#define AT91C_HDMA_SSREQ3     (0x1 <<  6) // (HDMA) Request a source single transfer on channel 3\r
+#define        AT91C_HDMA_SSREQ3_0                    (0x0 <<  6) // (HDMA) No effect.\r
+#define        AT91C_HDMA_SSREQ3_1                    (0x1 <<  6) // (HDMA) Request a source single transfer on channel 3.\r
+#define AT91C_HDMA_DSREQ3     (0x1 <<  7) // (HDMA) Request a destination single transfer on channel 3\r
+#define        AT91C_HDMA_DSREQ3_0                    (0x0 <<  7) // (HDMA) No effect.\r
+#define        AT91C_HDMA_DSREQ3_1                    (0x1 <<  7) // (HDMA) Request a destination single transfer on channel 3.\r
+#define AT91C_HDMA_SSREQ4     (0x1 <<  8) // (HDMA) Request a source single transfer on channel 4\r
+#define        AT91C_HDMA_SSREQ4_0                    (0x0 <<  8) // (HDMA) No effect.\r
+#define        AT91C_HDMA_SSREQ4_1                    (0x1 <<  8) // (HDMA) Request a source single transfer on channel 4.\r
+#define AT91C_HDMA_DSREQ4     (0x1 <<  9) // (HDMA) Request a destination single transfer on channel 4\r
+#define        AT91C_HDMA_DSREQ4_0                    (0x0 <<  9) // (HDMA) No effect.\r
+#define        AT91C_HDMA_DSREQ4_1                    (0x1 <<  9) // (HDMA) Request a destination single transfer on channel 4.\r
+#define AT91C_HDMA_SSREQ5     (0x1 << 10) // (HDMA) Request a source single transfer on channel 5\r
+#define        AT91C_HDMA_SSREQ5_0                    (0x0 << 10) // (HDMA) No effect.\r
+#define        AT91C_HDMA_SSREQ5_1                    (0x1 << 10) // (HDMA) Request a source single transfer on channel 5.\r
+#define AT91C_HDMA_DSREQ6     (0x1 << 11) // (HDMA) Request a destination single transfer on channel 5\r
+#define        AT91C_HDMA_DSREQ6_0                    (0x0 << 11) // (HDMA) No effect.\r
+#define        AT91C_HDMA_DSREQ6_1                    (0x1 << 11) // (HDMA) Request a destination single transfer on channel 5.\r
+#define AT91C_HDMA_SSREQ6     (0x1 << 12) // (HDMA) Request a source single transfer on channel 6\r
+#define        AT91C_HDMA_SSREQ6_0                    (0x0 << 12) // (HDMA) No effect.\r
+#define        AT91C_HDMA_SSREQ6_1                    (0x1 << 12) // (HDMA) Request a source single transfer on channel 6.\r
+#define AT91C_HDMA_SSREQ7     (0x1 << 14) // (HDMA) Request a source single transfer on channel 7\r
+#define        AT91C_HDMA_SSREQ7_0                    (0x0 << 14) // (HDMA) No effect.\r
+#define        AT91C_HDMA_SSREQ7_1                    (0x1 << 14) // (HDMA) Request a source single transfer on channel 7.\r
+#define AT91C_HDMA_DSREQ7     (0x1 << 15) // (HDMA) Request a destination single transfer on channel 7\r
+#define        AT91C_HDMA_DSREQ7_0                    (0x0 << 15) // (HDMA) No effect.\r
+#define        AT91C_HDMA_DSREQ7_1                    (0x1 << 15) // (HDMA) Request a destination single transfer on channel 7.\r
+// -------- HDMA_CREQ : (HDMA Offset: 0xc)  -------- \r
+#define AT91C_HDMA_SCREQ0     (0x1 <<  0) // (HDMA) Request a source chunk transfer on channel 0\r
+#define        AT91C_HDMA_SCREQ0_0                    (0x0) // (HDMA) No effect.\r
+#define        AT91C_HDMA_SCREQ0_1                    (0x1) // (HDMA) Request a source chunk transfer on channel 0.\r
+#define AT91C_HDMA_DCREQ0     (0x1 <<  1) // (HDMA) Request a destination chunk transfer on channel 0\r
+#define        AT91C_HDMA_DCREQ0_0                    (0x0 <<  1) // (HDMA) No effect.\r
+#define        AT91C_HDMA_DCREQ0_1                    (0x1 <<  1) // (HDMA) Request a destination chunk transfer on channel 0.\r
+#define AT91C_HDMA_SCREQ1     (0x1 <<  2) // (HDMA) Request a source chunk transfer on channel 1\r
+#define        AT91C_HDMA_SCREQ1_0                    (0x0 <<  2) // (HDMA) No effect.\r
+#define        AT91C_HDMA_SCREQ1_1                    (0x1 <<  2) // (HDMA) Request a source chunk transfer on channel 1.\r
+#define AT91C_HDMA_DCREQ1     (0x1 <<  3) // (HDMA) Request a destination chunk transfer on channel 1\r
+#define        AT91C_HDMA_DCREQ1_0                    (0x0 <<  3) // (HDMA) No effect.\r
+#define        AT91C_HDMA_DCREQ1_1                    (0x1 <<  3) // (HDMA) Request a destination chunk transfer on channel 1.\r
+#define AT91C_HDMA_SCREQ2     (0x1 <<  4) // (HDMA) Request a source chunk transfer on channel 2\r
+#define        AT91C_HDMA_SCREQ2_0                    (0x0 <<  4) // (HDMA) No effect.\r
+#define        AT91C_HDMA_SCREQ2_1                    (0x1 <<  4) // (HDMA) Request a source chunk transfer on channel 2.\r
+#define AT91C_HDMA_DCREQ2     (0x1 <<  5) // (HDMA) Request a destination chunk transfer on channel 2\r
+#define        AT91C_HDMA_DCREQ2_0                    (0x0 <<  5) // (HDMA) No effect.\r
+#define        AT91C_HDMA_DCREQ2_1                    (0x1 <<  5) // (HDMA) Request a destination chunk transfer on channel 2.\r
+#define AT91C_HDMA_SCREQ3     (0x1 <<  6) // (HDMA) Request a source chunk transfer on channel 3\r
+#define        AT91C_HDMA_SCREQ3_0                    (0x0 <<  6) // (HDMA) No effect.\r
+#define        AT91C_HDMA_SCREQ3_1                    (0x1 <<  6) // (HDMA) Request a source chunk transfer on channel 3.\r
+#define AT91C_HDMA_DCREQ3     (0x1 <<  7) // (HDMA) Request a destination chunk transfer on channel 3\r
+#define        AT91C_HDMA_DCREQ3_0                    (0x0 <<  7) // (HDMA) No effect.\r
+#define        AT91C_HDMA_DCREQ3_1                    (0x1 <<  7) // (HDMA) Request a destination chunk transfer on channel 3.\r
+#define AT91C_HDMA_SCREQ4     (0x1 <<  8) // (HDMA) Request a source chunk transfer on channel 4\r
+#define        AT91C_HDMA_SCREQ4_0                    (0x0 <<  8) // (HDMA) No effect.\r
+#define        AT91C_HDMA_SCREQ4_1                    (0x1 <<  8) // (HDMA) Request a source chunk transfer on channel 4.\r
+#define AT91C_HDMA_DCREQ4     (0x1 <<  9) // (HDMA) Request a destination chunk transfer on channel 4\r
+#define        AT91C_HDMA_DCREQ4_0                    (0x0 <<  9) // (HDMA) No effect.\r
+#define        AT91C_HDMA_DCREQ4_1                    (0x1 <<  9) // (HDMA) Request a destination chunk transfer on channel 4.\r
+#define AT91C_HDMA_SCREQ5     (0x1 << 10) // (HDMA) Request a source chunk transfer on channel 5\r
+#define        AT91C_HDMA_SCREQ5_0                    (0x0 << 10) // (HDMA) No effect.\r
+#define        AT91C_HDMA_SCREQ5_1                    (0x1 << 10) // (HDMA) Request a source chunk transfer on channel 5.\r
+#define AT91C_HDMA_DCREQ6     (0x1 << 11) // (HDMA) Request a destination chunk transfer on channel 5\r
+#define        AT91C_HDMA_DCREQ6_0                    (0x0 << 11) // (HDMA) No effect.\r
+#define        AT91C_HDMA_DCREQ6_1                    (0x1 << 11) // (HDMA) Request a destination chunk transfer on channel 5.\r
+#define AT91C_HDMA_SCREQ6     (0x1 << 12) // (HDMA) Request a source chunk transfer on channel 6\r
+#define        AT91C_HDMA_SCREQ6_0                    (0x0 << 12) // (HDMA) No effect.\r
+#define        AT91C_HDMA_SCREQ6_1                    (0x1 << 12) // (HDMA) Request a source chunk transfer on channel 6.\r
+#define AT91C_HDMA_SCREQ7     (0x1 << 14) // (HDMA) Request a source chunk transfer on channel 7\r
+#define        AT91C_HDMA_SCREQ7_0                    (0x0 << 14) // (HDMA) No effect.\r
+#define        AT91C_HDMA_SCREQ7_1                    (0x1 << 14) // (HDMA) Request a source chunk transfer on channel 7.\r
+#define AT91C_HDMA_DCREQ7     (0x1 << 15) // (HDMA) Request a destination chunk transfer on channel 7\r
+#define        AT91C_HDMA_DCREQ7_0                    (0x0 << 15) // (HDMA) No effect.\r
+#define        AT91C_HDMA_DCREQ7_1                    (0x1 << 15) // (HDMA) Request a destination chunk transfer on channel 7.\r
+// -------- HDMA_LAST : (HDMA Offset: 0x10)  -------- \r
+#define AT91C_HDMA_SLAST0     (0x1 <<  0) // (HDMA) Indicates that this source request is the last transfer of the buffer on channel 0\r
+#define        AT91C_HDMA_SLAST0_0                    (0x0) // (HDMA) No effect.\r
+#define        AT91C_HDMA_SLAST0_1                    (0x1) // (HDMA) Writing one to SLASTx prior to writing one to SSREQx or SCREQx indicates that this source request is the last transfer of the buffer on channel 0.\r
+#define AT91C_HDMA_DLAST0     (0x1 <<  1) // (HDMA) Indicates that this destination request is the last transfer of the buffer on channel 0\r
+#define        AT91C_HDMA_DLAST0_0                    (0x0 <<  1) // (HDMA) No effect.\r
+#define        AT91C_HDMA_DLAST0_1                    (0x1 <<  1) // (HDMA) Writing one to DLASTx prior to writing one to DSREQx or DCREQx indicates that this destination request is the last transfer of the buffer on channel 0.\r
+#define AT91C_HDMA_SLAST1     (0x1 <<  2) // (HDMA) Indicates that this source request is the last transfer of the buffer on channel 1\r
+#define        AT91C_HDMA_SLAST1_0                    (0x0 <<  2) // (HDMA) No effect.\r
+#define        AT91C_HDMA_SLAST1_1                    (0x1 <<  2) // (HDMA) Writing one to SLASTx prior to writing one to SSREQx or SCREQx indicates that this source request is the last transfer of the buffer on channel 1.\r
+#define AT91C_HDMA_DLAST1     (0x1 <<  3) // (HDMA) Indicates that this destination request is the last transfer of the buffer on channel 1\r
+#define        AT91C_HDMA_DLAST1_0                    (0x0 <<  3) // (HDMA) No effect.\r
+#define        AT91C_HDMA_DLAST1_1                    (0x1 <<  3) // (HDMA) Writing one to DLASTx prior to writing one to DSREQx or DCREQx indicates that this destination request is the last transfer of the buffer on channel 1.\r
+#define AT91C_HDMA_SLAST2     (0x1 <<  4) // (HDMA) Indicates that this source request is the last transfer of the buffer on channel 2\r
+#define        AT91C_HDMA_SLAST2_0                    (0x0 <<  4) // (HDMA) No effect.\r
+#define        AT91C_HDMA_SLAST2_1                    (0x1 <<  4) // (HDMA) Writing one to SLASTx prior to writing one to SSREQx or SCREQx indicates that this source request is the last transfer of the buffer on channel 2.\r
+#define AT91C_HDMA_DLAST2     (0x1 <<  5) // (HDMA) Indicates that this destination request is the last transfer of the buffer on channel 2\r
+#define        AT91C_HDMA_DLAST2_0                    (0x0 <<  5) // (HDMA) No effect.\r
+#define        AT91C_HDMA_DLAST2_1                    (0x1 <<  5) // (HDMA) Writing one to DLASTx prior to writing one to DSREQx or DCREQx indicates that this destination request is the last transfer of the buffer on channel 2.\r
+#define AT91C_HDMA_SLAST3     (0x1 <<  6) // (HDMA) Indicates that this source request is the last transfer of the buffer on channel 3\r
+#define        AT91C_HDMA_SLAST3_0                    (0x0 <<  6) // (HDMA) No effect.\r
+#define        AT91C_HDMA_SLAST3_1                    (0x1 <<  6) // (HDMA) Writing one to SLASTx prior to writing one to SSREQx or SCREQx indicates that this source request is the last transfer of the buffer on channel 3.\r
+#define AT91C_HDMA_DLAST3     (0x1 <<  7) // (HDMA) Indicates that this destination request is the last transfer of the buffer on channel 3\r
+#define        AT91C_HDMA_DLAST3_0                    (0x0 <<  7) // (HDMA) No effect.\r
+#define        AT91C_HDMA_DLAST3_1                    (0x1 <<  7) // (HDMA) Writing one to DLASTx prior to writing one to DSREQx or DCREQx indicates that this destination request is the last transfer of the buffer on channel 3.\r
+#define AT91C_HDMA_SLAST4     (0x1 <<  8) // (HDMA) Indicates that this source request is the last transfer of the buffer on channel 4\r
+#define        AT91C_HDMA_SLAST4_0                    (0x0 <<  8) // (HDMA) No effect.\r
+#define        AT91C_HDMA_SLAST4_1                    (0x1 <<  8) // (HDMA) Writing one to SLASTx prior to writing one to SSREQx or SCREQx indicates that this source request is the last transfer of the buffer on channel 4.\r
+#define AT91C_HDMA_DLAST4     (0x1 <<  9) // (HDMA) Indicates that this destination request is the last transfer of the buffer on channel 4\r
+#define        AT91C_HDMA_DLAST4_0                    (0x0 <<  9) // (HDMA) No effect.\r
+#define        AT91C_HDMA_DLAST4_1                    (0x1 <<  9) // (HDMA) Writing one to DLASTx prior to writing one to DSREQx or DCREQx indicates that this destination request is the last transfer of the buffer on channel 4.\r
+#define AT91C_HDMA_SLAST5     (0x1 << 10) // (HDMA) Indicates that this source request is the last transfer of the buffer on channel 5\r
+#define        AT91C_HDMA_SLAST5_0                    (0x0 << 10) // (HDMA) No effect.\r
+#define        AT91C_HDMA_SLAST5_1                    (0x1 << 10) // (HDMA) Writing one to SLASTx prior to writing one to SSREQx or SCREQx indicates that this source request is the last transfer of the buffer on channel 5.\r
+#define AT91C_HDMA_DLAST6     (0x1 << 11) // (HDMA) Indicates that this destination request is the last transfer of the buffer on channel 5\r
+#define        AT91C_HDMA_DLAST6_0                    (0x0 << 11) // (HDMA) No effect.\r
+#define        AT91C_HDMA_DLAST6_1                    (0x1 << 11) // (HDMA) Writing one to DLASTx prior to writing one to DSREQx or DCREQx indicates that this destination request is the last transfer of the buffer on channel 5.\r
+#define AT91C_HDMA_SLAST6     (0x1 << 12) // (HDMA) Indicates that this source request is the last transfer of the buffer on channel 6\r
+#define        AT91C_HDMA_SLAST6_0                    (0x0 << 12) // (HDMA) No effect.\r
+#define        AT91C_HDMA_SLAST6_1                    (0x1 << 12) // (HDMA) Writing one to SLASTx prior to writing one to SSREQx or SCREQx indicates that this source request is the last transfer of the buffer on channel 6.\r
+#define AT91C_HDMA_SLAST7     (0x1 << 14) // (HDMA) Indicates that this source request is the last transfer of the buffer on channel 7\r
+#define        AT91C_HDMA_SLAST7_0                    (0x0 << 14) // (HDMA) No effect.\r
+#define        AT91C_HDMA_SLAST7_1                    (0x1 << 14) // (HDMA) Writing one to SLASTx prior to writing one to SSREQx or SCREQx indicates that this source request is the last transfer of the buffer on channel 7.\r
+#define AT91C_HDMA_DLAST7     (0x1 << 15) // (HDMA) Indicates that this destination request is the last transfer of the buffer on channel 7\r
+#define        AT91C_HDMA_DLAST7_0                    (0x0 << 15) // (HDMA) No effect.\r
+#define        AT91C_HDMA_DLAST7_1                    (0x1 << 15) // (HDMA) Writing one to DLASTx prior to writing one to DSREQx or DCREQx indicates that this destination request is the last transfer of the buffer on channel 7.\r
+// -------- HDMA_SYNC : (HDMA Offset: 0x14)  -------- \r
+#define AT91C_SYNC_REQ        (0xFFFF <<  0) // (HDMA) \r
+// -------- HDMA_EBCIER : (HDMA Offset: 0x18) Buffer Transfer Completed/Chained Buffer Transfer Completed/Access Error Interrupt Enable Register -------- \r
+#define AT91C_HDMA_BTC0       (0x1 <<  0) // (HDMA) Buffer Transfer Completed Interrupt Enable/Disable/Status Register\r
+#define AT91C_HDMA_BTC1       (0x1 <<  1) // (HDMA) Buffer Transfer Completed Interrupt Enable/Disable/Status Register\r
+#define AT91C_HDMA_BTC2       (0x1 <<  2) // (HDMA) Buffer Transfer Completed Interrupt Enable/Disable/Status Register\r
+#define AT91C_HDMA_BTC3       (0x1 <<  3) // (HDMA) Buffer Transfer Completed Interrupt Enable/Disable/Status Register\r
+#define AT91C_HDMA_BTC4       (0x1 <<  4) // (HDMA) Buffer Transfer Completed Interrupt Enable/Disable/Status Register\r
+#define AT91C_HDMA_BTC5       (0x1 <<  5) // (HDMA) Buffer Transfer Completed Interrupt Enable/Disable/Status Register\r
+#define AT91C_HDMA_BTC6       (0x1 <<  6) // (HDMA) Buffer Transfer Completed Interrupt Enable/Disable/Status Register\r
+#define AT91C_HDMA_BTC7       (0x1 <<  7) // (HDMA) Buffer Transfer Completed Interrupt Enable/Disable/Status Register\r
+#define AT91C_HDMA_CBTC0      (0x1 <<  8) // (HDMA) Chained Buffer Transfer Completed Interrupt Enable/Disable/Status Register\r
+#define AT91C_HDMA_CBTC1      (0x1 <<  9) // (HDMA) Chained Buffer Transfer Completed Interrupt Enable/Disable/Status Register\r
+#define AT91C_HDMA_CBTC2      (0x1 << 10) // (HDMA) Chained Buffer Transfer Completed Interrupt Enable/Disable/Status Register\r
+#define AT91C_HDMA_CBTC3      (0x1 << 11) // (HDMA) Chained Buffer Transfer Completed Interrupt Enable/Disable/Status Register\r
+#define AT91C_HDMA_CBTC4      (0x1 << 12) // (HDMA) Chained Buffer Transfer Completed Interrupt Enable/Disable/Status Register\r
+#define AT91C_HDMA_CBTC5      (0x1 << 13) // (HDMA) Chained Buffer Transfer Completed Interrupt Enable/Disable/Status Register\r
+#define AT91C_HDMA_CBTC6      (0x1 << 14) // (HDMA) Chained Buffer Transfer Completed Interrupt Enable/Disable/Status Register\r
+#define AT91C_HDMA_CBTC7      (0x1 << 15) // (HDMA) Chained Buffer Transfer Completed Interrupt Enable/Disable/Status Register\r
+#define AT91C_HDMA_ERR0       (0x1 << 16) // (HDMA) Access HDMA_Error Interrupt Enable/Disable/Status Register\r
+#define AT91C_HDMA_ERR1       (0x1 << 17) // (HDMA) Access HDMA_Error Interrupt Enable/Disable/Status Register\r
+#define AT91C_HDMA_ERR2       (0x1 << 18) // (HDMA) Access HDMA_Error Interrupt Enable/Disable/Status Register\r
+#define AT91C_HDMA_ERR3       (0x1 << 19) // (HDMA) Access HDMA_Error Interrupt Enable/Disable/Status Register\r
+#define AT91C_HDMA_ERR4       (0x1 << 20) // (HDMA) Access HDMA_Error Interrupt Enable/Disable/Status Register\r
+#define AT91C_HDMA_ERR5       (0x1 << 21) // (HDMA) Access HDMA_Error Interrupt Enable/Disable/Status Register\r
+#define AT91C_HDMA_ERR6       (0x1 << 22) // (HDMA) Access HDMA_Error Interrupt Enable/Disable/Status Register\r
+#define AT91C_HDMA_ERR7       (0x1 << 23) // (HDMA) Access HDMA_Error Interrupt Enable/Disable/Status Register\r
+// -------- HDMA_EBCIDR : (HDMA Offset: 0x1c)  -------- \r
+// -------- HDMA_EBCIMR : (HDMA Offset: 0x20)  -------- \r
+// -------- HDMA_EBCISR : (HDMA Offset: 0x24)  -------- \r
+// -------- HDMA_CHER : (HDMA Offset: 0x28)  -------- \r
+#define AT91C_HDMA_ENA0       (0x1 <<  0) // (HDMA) When set, channel 0 enabled.\r
+#define        AT91C_HDMA_ENA0_0                    (0x0) // (HDMA) No effect.\r
+#define        AT91C_HDMA_ENA0_1                    (0x1) // (HDMA) Channel 0 enabled.\r
+#define AT91C_HDMA_ENA1       (0x1 <<  1) // (HDMA) When set, channel 1 enabled.\r
+#define        AT91C_HDMA_ENA1_0                    (0x0 <<  1) // (HDMA) No effect.\r
+#define        AT91C_HDMA_ENA1_1                    (0x1 <<  1) // (HDMA) Channel 1 enabled.\r
+#define AT91C_HDMA_ENA2       (0x1 <<  2) // (HDMA) When set, channel 2 enabled.\r
+#define        AT91C_HDMA_ENA2_0                    (0x0 <<  2) // (HDMA) No effect.\r
+#define        AT91C_HDMA_ENA2_1                    (0x1 <<  2) // (HDMA) Channel 2 enabled.\r
+#define AT91C_HDMA_ENA3       (0x1 <<  3) // (HDMA) When set, channel 3 enabled.\r
+#define        AT91C_HDMA_ENA3_0                    (0x0 <<  3) // (HDMA) No effect.\r
+#define        AT91C_HDMA_ENA3_1                    (0x1 <<  3) // (HDMA) Channel 3 enabled.\r
+#define AT91C_HDMA_ENA4       (0x1 <<  4) // (HDMA) When set, channel 4 enabled.\r
+#define        AT91C_HDMA_ENA4_0                    (0x0 <<  4) // (HDMA) No effect.\r
+#define        AT91C_HDMA_ENA4_1                    (0x1 <<  4) // (HDMA) Channel 4 enabled.\r
+#define AT91C_HDMA_ENA5       (0x1 <<  5) // (HDMA) When set, channel 5 enabled.\r
+#define        AT91C_HDMA_ENA5_0                    (0x0 <<  5) // (HDMA) No effect.\r
+#define        AT91C_HDMA_ENA5_1                    (0x1 <<  5) // (HDMA) Channel 5 enabled.\r
+#define AT91C_HDMA_ENA6       (0x1 <<  6) // (HDMA) When set, channel 6 enabled.\r
+#define        AT91C_HDMA_ENA6_0                    (0x0 <<  6) // (HDMA) No effect.\r
+#define        AT91C_HDMA_ENA6_1                    (0x1 <<  6) // (HDMA) Channel 6 enabled.\r
+#define AT91C_HDMA_ENA7       (0x1 <<  7) // (HDMA) When set, channel 7 enabled.\r
+#define        AT91C_HDMA_ENA7_0                    (0x0 <<  7) // (HDMA) No effect.\r
+#define        AT91C_HDMA_ENA7_1                    (0x1 <<  7) // (HDMA) Channel 7 enabled.\r
+#define AT91C_HDMA_SUSP0      (0x1 <<  8) // (HDMA) When set, channel 0 freezed and its current context.\r
+#define        AT91C_HDMA_SUSP0_0                    (0x0 <<  8) // (HDMA) No effect.\r
+#define        AT91C_HDMA_SUSP0_1                    (0x1 <<  8) // (HDMA) Channel 0 freezed.\r
+#define AT91C_HDMA_SUSP1      (0x1 <<  9) // (HDMA) When set, channel 1 freezed and its current context.\r
+#define        AT91C_HDMA_SUSP1_0                    (0x0 <<  9) // (HDMA) No effect.\r
+#define        AT91C_HDMA_SUSP1_1                    (0x1 <<  9) // (HDMA) Channel 1 freezed.\r
+#define AT91C_HDMA_SUSP2      (0x1 << 10) // (HDMA) When set, channel 2 freezed and its current context.\r
+#define        AT91C_HDMA_SUSP2_0                    (0x0 << 10) // (HDMA) No effect.\r
+#define        AT91C_HDMA_SUSP2_1                    (0x1 << 10) // (HDMA) Channel 2 freezed.\r
+#define AT91C_HDMA_SUSP3      (0x1 << 11) // (HDMA) When set, channel 3 freezed and its current context.\r
+#define        AT91C_HDMA_SUSP3_0                    (0x0 << 11) // (HDMA) No effect.\r
+#define        AT91C_HDMA_SUSP3_1                    (0x1 << 11) // (HDMA) Channel 3 freezed.\r
+#define AT91C_HDMA_SUSP4      (0x1 << 12) // (HDMA) When set, channel 4 freezed and its current context.\r
+#define        AT91C_HDMA_SUSP4_0                    (0x0 << 12) // (HDMA) No effect.\r
+#define        AT91C_HDMA_SUSP4_1                    (0x1 << 12) // (HDMA) Channel 4 freezed.\r
+#define AT91C_HDMA_SUSP5      (0x1 << 13) // (HDMA) When set, channel 5 freezed and its current context.\r
+#define        AT91C_HDMA_SUSP5_0                    (0x0 << 13) // (HDMA) No effect.\r
+#define        AT91C_HDMA_SUSP5_1                    (0x1 << 13) // (HDMA) Channel 5 freezed.\r
+#define AT91C_HDMA_SUSP6      (0x1 << 14) // (HDMA) When set, channel 6 freezed and its current context.\r
+#define        AT91C_HDMA_SUSP6_0                    (0x0 << 14) // (HDMA) No effect.\r
+#define        AT91C_HDMA_SUSP6_1                    (0x1 << 14) // (HDMA) Channel 6 freezed.\r
+#define AT91C_HDMA_SUSP7      (0x1 << 15) // (HDMA) When set, channel 7 freezed and its current context.\r
+#define        AT91C_HDMA_SUSP7_0                    (0x0 << 15) // (HDMA) No effect.\r
+#define        AT91C_HDMA_SUSP7_1                    (0x1 << 15) // (HDMA) Channel 7 freezed.\r
+#define AT91C_HDMA_KEEP0      (0x1 << 24) // (HDMA) When set, it resumes the channel 0 from an automatic stall state.\r
+#define        AT91C_HDMA_KEEP0_0                    (0x0 << 24) // (HDMA) No effect.\r
+#define        AT91C_HDMA_KEEP0_1                    (0x1 << 24) // (HDMA) Resumes the channel 0.\r
+#define AT91C_HDMA_KEEP1      (0x1 << 25) // (HDMA) When set, it resumes the channel 1 from an automatic stall state.\r
+#define        AT91C_HDMA_KEEP1_0                    (0x0 << 25) // (HDMA) No effect.\r
+#define        AT91C_HDMA_KEEP1_1                    (0x1 << 25) // (HDMA) Resumes the channel 1.\r
+#define AT91C_HDMA_KEEP2      (0x1 << 26) // (HDMA) When set, it resumes the channel 2 from an automatic stall state.\r
+#define        AT91C_HDMA_KEEP2_0                    (0x0 << 26) // (HDMA) No effect.\r
+#define        AT91C_HDMA_KEEP2_1                    (0x1 << 26) // (HDMA) Resumes the channel 2.\r
+#define AT91C_HDMA_KEEP3      (0x1 << 27) // (HDMA) When set, it resumes the channel 3 from an automatic stall state.\r
+#define        AT91C_HDMA_KEEP3_0                    (0x0 << 27) // (HDMA) No effect.\r
+#define        AT91C_HDMA_KEEP3_1                    (0x1 << 27) // (HDMA) Resumes the channel 3.\r
+#define AT91C_HDMA_KEEP4      (0x1 << 28) // (HDMA) When set, it resumes the channel 4 from an automatic stall state.\r
+#define        AT91C_HDMA_KEEP4_0                    (0x0 << 28) // (HDMA) No effect.\r
+#define        AT91C_HDMA_KEEP4_1                    (0x1 << 28) // (HDMA) Resumes the channel 4.\r
+#define AT91C_HDMA_KEEP5      (0x1 << 29) // (HDMA) When set, it resumes the channel 5 from an automatic stall state.\r
+#define        AT91C_HDMA_KEEP5_0                    (0x0 << 29) // (HDMA) No effect.\r
+#define        AT91C_HDMA_KEEP5_1                    (0x1 << 29) // (HDMA) Resumes the channel 5.\r
+#define AT91C_HDMA_KEEP6      (0x1 << 30) // (HDMA) When set, it resumes the channel 6 from an automatic stall state.\r
+#define        AT91C_HDMA_KEEP6_0                    (0x0 << 30) // (HDMA) No effect.\r
+#define        AT91C_HDMA_KEEP6_1                    (0x1 << 30) // (HDMA) Resumes the channel 6.\r
+#define AT91C_HDMA_KEEP7      (0x1 << 31) // (HDMA) When set, it resumes the channel 7 from an automatic stall state.\r
+#define        AT91C_HDMA_KEEP7_0                    (0x0 << 31) // (HDMA) No effect.\r
+#define        AT91C_HDMA_KEEP7_1                    (0x1 << 31) // (HDMA) Resumes the channel 7.\r
+// -------- HDMA_CHDR : (HDMA Offset: 0x2c)  -------- \r
+#define AT91C_HDMA_DIS0       (0x1 <<  0) // (HDMA) Write one to this field to disable the channel 0.\r
+#define        AT91C_HDMA_DIS0_0                    (0x0) // (HDMA) No effect.\r
+#define        AT91C_HDMA_DIS0_1                    (0x1) // (HDMA) Disables the channel 0.\r
+#define AT91C_HDMA_DIS1       (0x1 <<  1) // (HDMA) Write one to this field to disable the channel 1.\r
+#define        AT91C_HDMA_DIS1_0                    (0x0 <<  1) // (HDMA) No effect.\r
+#define        AT91C_HDMA_DIS1_1                    (0x1 <<  1) // (HDMA) Disables the channel 1.\r
+#define AT91C_HDMA_DIS2       (0x1 <<  2) // (HDMA) Write one to this field to disable the channel 2.\r
+#define        AT91C_HDMA_DIS2_0                    (0x0 <<  2) // (HDMA) No effect.\r
+#define        AT91C_HDMA_DIS2_1                    (0x1 <<  2) // (HDMA) Disables the channel 2.\r
+#define AT91C_HDMA_DIS3       (0x1 <<  3) // (HDMA) Write one to this field to disable the channel 3.\r
+#define        AT91C_HDMA_DIS3_0                    (0x0 <<  3) // (HDMA) No effect.\r
+#define        AT91C_HDMA_DIS3_1                    (0x1 <<  3) // (HDMA) Disables the channel 3.\r
+#define AT91C_HDMA_DIS4       (0x1 <<  4) // (HDMA) Write one to this field to disable the channel 4.\r
+#define        AT91C_HDMA_DIS4_0                    (0x0 <<  4) // (HDMA) No effect.\r
+#define        AT91C_HDMA_DIS4_1                    (0x1 <<  4) // (HDMA) Disables the channel 4.\r
+#define AT91C_HDMA_DIS5       (0x1 <<  5) // (HDMA) Write one to this field to disable the channel 5.\r
+#define        AT91C_HDMA_DIS5_0                    (0x0 <<  5) // (HDMA) No effect.\r
+#define        AT91C_HDMA_DIS5_1                    (0x1 <<  5) // (HDMA) Disables the channel 5.\r
+#define AT91C_HDMA_DIS6       (0x1 <<  6) // (HDMA) Write one to this field to disable the channel 6.\r
+#define        AT91C_HDMA_DIS6_0                    (0x0 <<  6) // (HDMA) No effect.\r
+#define        AT91C_HDMA_DIS6_1                    (0x1 <<  6) // (HDMA) Disables the channel 6.\r
+#define AT91C_HDMA_DIS7       (0x1 <<  7) // (HDMA) Write one to this field to disable the channel 7.\r
+#define        AT91C_HDMA_DIS7_0                    (0x0 <<  7) // (HDMA) No effect.\r
+#define        AT91C_HDMA_DIS7_1                    (0x1 <<  7) // (HDMA) Disables the channel 7.\r
+#define AT91C_HDMA_RES0       (0x1 <<  8) // (HDMA) Write one to this field to resume the channel 0 transfer restoring its context.\r
+#define        AT91C_HDMA_RES0_0                    (0x0 <<  8) // (HDMA) No effect.\r
+#define        AT91C_HDMA_RES0_1                    (0x1 <<  8) // (HDMA) Resumes the channel 0.\r
+#define AT91C_HDMA_RES1       (0x1 <<  9) // (HDMA) Write one to this field to resume the channel 1 transfer restoring its context.\r
+#define        AT91C_HDMA_RES1_0                    (0x0 <<  9) // (HDMA) No effect.\r
+#define        AT91C_HDMA_RES1_1                    (0x1 <<  9) // (HDMA) Resumes the channel 1.\r
+#define AT91C_HDMA_RES2       (0x1 << 10) // (HDMA) Write one to this field to resume the channel 2 transfer restoring its context.\r
+#define        AT91C_HDMA_RES2_0                    (0x0 << 10) // (HDMA) No effect.\r
+#define        AT91C_HDMA_RES2_1                    (0x1 << 10) // (HDMA) Resumes the channel 2.\r
+#define AT91C_HDMA_RES3       (0x1 << 11) // (HDMA) Write one to this field to resume the channel 3 transfer restoring its context.\r
+#define        AT91C_HDMA_RES3_0                    (0x0 << 11) // (HDMA) No effect.\r
+#define        AT91C_HDMA_RES3_1                    (0x1 << 11) // (HDMA) Resumes the channel 3.\r
+#define AT91C_HDMA_RES4       (0x1 << 12) // (HDMA) Write one to this field to resume the channel 4 transfer restoring its context.\r
+#define        AT91C_HDMA_RES4_0                    (0x0 << 12) // (HDMA) No effect.\r
+#define        AT91C_HDMA_RES4_1                    (0x1 << 12) // (HDMA) Resumes the channel 4.\r
+#define AT91C_HDMA_RES5       (0x1 << 13) // (HDMA) Write one to this field to resume the channel 5 transfer restoring its context.\r
+#define        AT91C_HDMA_RES5_0                    (0x0 << 13) // (HDMA) No effect.\r
+#define        AT91C_HDMA_RES5_1                    (0x1 << 13) // (HDMA) Resumes the channel 5.\r
+#define AT91C_HDMA_RES6       (0x1 << 14) // (HDMA) Write one to this field to resume the channel 6 transfer restoring its context.\r
+#define        AT91C_HDMA_RES6_0                    (0x0 << 14) // (HDMA) No effect.\r
+#define        AT91C_HDMA_RES6_1                    (0x1 << 14) // (HDMA) Resumes the channel 6.\r
+#define AT91C_HDMA_RES7       (0x1 << 15) // (HDMA) Write one to this field to resume the channel 7 transfer restoring its context.\r
+#define        AT91C_HDMA_RES7_0                    (0x0 << 15) // (HDMA) No effect.\r
+#define        AT91C_HDMA_RES7_1                    (0x1 << 15) // (HDMA) Resumes the channel 7.\r
+// -------- HDMA_CHSR : (HDMA Offset: 0x30)  -------- \r
+#define AT91C_HDMA_EMPT0      (0x1 << 16) // (HDMA) When set, channel 0 is empty.\r
+#define        AT91C_HDMA_EMPT0_0                    (0x0 << 16) // (HDMA) No effect.\r
+#define        AT91C_HDMA_EMPT0_1                    (0x1 << 16) // (HDMA) Channel 0 empty.\r
+#define AT91C_HDMA_EMPT1      (0x1 << 17) // (HDMA) When set, channel 1 is empty.\r
+#define        AT91C_HDMA_EMPT1_0                    (0x0 << 17) // (HDMA) No effect.\r
+#define        AT91C_HDMA_EMPT1_1                    (0x1 << 17) // (HDMA) Channel 1 empty.\r
+#define AT91C_HDMA_EMPT2      (0x1 << 18) // (HDMA) When set, channel 2 is empty.\r
+#define        AT91C_HDMA_EMPT2_0                    (0x0 << 18) // (HDMA) No effect.\r
+#define        AT91C_HDMA_EMPT2_1                    (0x1 << 18) // (HDMA) Channel 2 empty.\r
+#define AT91C_HDMA_EMPT3      (0x1 << 19) // (HDMA) When set, channel 3 is empty.\r
+#define        AT91C_HDMA_EMPT3_0                    (0x0 << 19) // (HDMA) No effect.\r
+#define        AT91C_HDMA_EMPT3_1                    (0x1 << 19) // (HDMA) Channel 3 empty.\r
+#define AT91C_HDMA_EMPT4      (0x1 << 20) // (HDMA) When set, channel 4 is empty.\r
+#define        AT91C_HDMA_EMPT4_0                    (0x0 << 20) // (HDMA) No effect.\r
+#define        AT91C_HDMA_EMPT4_1                    (0x1 << 20) // (HDMA) Channel 4 empty.\r
+#define AT91C_HDMA_EMPT5      (0x1 << 21) // (HDMA) When set, channel 5 is empty.\r
+#define        AT91C_HDMA_EMPT5_0                    (0x0 << 21) // (HDMA) No effect.\r
+#define        AT91C_HDMA_EMPT5_1                    (0x1 << 21) // (HDMA) Channel 5 empty.\r
+#define AT91C_HDMA_EMPT6      (0x1 << 22) // (HDMA) When set, channel 6 is empty.\r
+#define        AT91C_HDMA_EMPT6_0                    (0x0 << 22) // (HDMA) No effect.\r
+#define        AT91C_HDMA_EMPT6_1                    (0x1 << 22) // (HDMA) Channel 6 empty.\r
+#define AT91C_HDMA_EMPT7      (0x1 << 23) // (HDMA) When set, channel 7 is empty.\r
+#define        AT91C_HDMA_EMPT7_0                    (0x0 << 23) // (HDMA) No effect.\r
+#define        AT91C_HDMA_EMPT7_1                    (0x1 << 23) // (HDMA) Channel 7 empty.\r
+#define AT91C_HDMA_STAL0      (0x1 << 24) // (HDMA) When set, channel 0 is stalled.\r
+#define        AT91C_HDMA_STAL0_0                    (0x0 << 24) // (HDMA) No effect.\r
+#define        AT91C_HDMA_STAL0_1                    (0x1 << 24) // (HDMA) Channel 0 stalled.\r
+#define AT91C_HDMA_STAL1      (0x1 << 25) // (HDMA) When set, channel 1 is stalled.\r
+#define        AT91C_HDMA_STAL1_0                    (0x0 << 25) // (HDMA) No effect.\r
+#define        AT91C_HDMA_STAL1_1                    (0x1 << 25) // (HDMA) Channel 1 stalled.\r
+#define AT91C_HDMA_STAL2      (0x1 << 26) // (HDMA) When set, channel 2 is stalled.\r
+#define        AT91C_HDMA_STAL2_0                    (0x0 << 26) // (HDMA) No effect.\r
+#define        AT91C_HDMA_STAL2_1                    (0x1 << 26) // (HDMA) Channel 2 stalled.\r
+#define AT91C_HDMA_STAL3      (0x1 << 27) // (HDMA) When set, channel 3 is stalled.\r
+#define        AT91C_HDMA_STAL3_0                    (0x0 << 27) // (HDMA) No effect.\r
+#define        AT91C_HDMA_STAL3_1                    (0x1 << 27) // (HDMA) Channel 3 stalled.\r
+#define AT91C_HDMA_STAL4      (0x1 << 28) // (HDMA) When set, channel 4 is stalled.\r
+#define        AT91C_HDMA_STAL4_0                    (0x0 << 28) // (HDMA) No effect.\r
+#define        AT91C_HDMA_STAL4_1                    (0x1 << 28) // (HDMA) Channel 4 stalled.\r
+#define AT91C_HDMA_STAL5      (0x1 << 29) // (HDMA) When set, channel 5 is stalled.\r
+#define        AT91C_HDMA_STAL5_0                    (0x0 << 29) // (HDMA) No effect.\r
+#define        AT91C_HDMA_STAL5_1                    (0x1 << 29) // (HDMA) Channel 5 stalled.\r
+#define AT91C_HDMA_STAL6      (0x1 << 30) // (HDMA) When set, channel 6 is stalled.\r
+#define        AT91C_HDMA_STAL6_0                    (0x0 << 30) // (HDMA) No effect.\r
+#define        AT91C_HDMA_STAL6_1                    (0x1 << 30) // (HDMA) Channel 6 stalled.\r
+#define AT91C_HDMA_STAL7      (0x1 << 31) // (HDMA) When set, channel 7 is stalled.\r
+#define        AT91C_HDMA_STAL7_0                    (0x0 << 31) // (HDMA) No effect.\r
+#define        AT91C_HDMA_STAL7_1                    (0x1 << 31) // (HDMA) Channel 7 stalled.\r
+// -------- HDMA_RSVD : (HDMA Offset: 0x34)  -------- \r
+// -------- HDMA_RSVD : (HDMA Offset: 0x38)  -------- \r
+// -------- HDMA_VER : (HDMA Offset: 0x1fc)  -------- \r
+\r
+// *****************************************************************************\r
+//               REGISTER ADDRESS DEFINITION FOR AT91SAM3U4\r
+// *****************************************************************************\r
+// ========== Register definition for SYS peripheral ========== \r
+#define AT91C_SYS_GPBR  (AT91_CAST(AT91_REG *)         0x400E1290) // (SYS) General Purpose Register\r
+// ========== Register definition for HSMC4_CS0 peripheral ========== \r
+#define AT91C_CS0_MODE  (AT91_CAST(AT91_REG *)         0x400E0080) // (HSMC4_CS0) Mode Register\r
+#define AT91C_CS0_PULSE (AT91_CAST(AT91_REG *)         0x400E0074) // (HSMC4_CS0) Pulse Register\r
+#define AT91C_CS0_CYCLE (AT91_CAST(AT91_REG *)         0x400E0078) // (HSMC4_CS0) Cycle Register\r
+#define AT91C_CS0_TIMINGS (AT91_CAST(AT91_REG *)       0x400E007C) // (HSMC4_CS0) Timmings Register\r
+#define AT91C_CS0_SETUP (AT91_CAST(AT91_REG *)         0x400E0070) // (HSMC4_CS0) Setup Register\r
+// ========== Register definition for HSMC4_CS1 peripheral ========== \r
+#define AT91C_CS1_CYCLE (AT91_CAST(AT91_REG *)         0x400E008C) // (HSMC4_CS1) Cycle Register\r
+#define AT91C_CS1_PULSE (AT91_CAST(AT91_REG *)         0x400E0088) // (HSMC4_CS1) Pulse Register\r
+#define AT91C_CS1_MODE  (AT91_CAST(AT91_REG *)         0x400E0094) // (HSMC4_CS1) Mode Register\r
+#define AT91C_CS1_SETUP (AT91_CAST(AT91_REG *)         0x400E0084) // (HSMC4_CS1) Setup Register\r
+#define AT91C_CS1_TIMINGS (AT91_CAST(AT91_REG *)       0x400E0090) // (HSMC4_CS1) Timmings Register\r
+// ========== Register definition for HSMC4_CS2 peripheral ========== \r
+#define AT91C_CS2_PULSE (AT91_CAST(AT91_REG *)         0x400E009C) // (HSMC4_CS2) Pulse Register\r
+#define AT91C_CS2_TIMINGS (AT91_CAST(AT91_REG *)       0x400E00A4) // (HSMC4_CS2) Timmings Register\r
+#define AT91C_CS2_CYCLE (AT91_CAST(AT91_REG *)         0x400E00A0) // (HSMC4_CS2) Cycle Register\r
+#define AT91C_CS2_MODE  (AT91_CAST(AT91_REG *)         0x400E00A8) // (HSMC4_CS2) Mode Register\r
+#define AT91C_CS2_SETUP (AT91_CAST(AT91_REG *)         0x400E0098) // (HSMC4_CS2) Setup Register\r
+// ========== Register definition for HSMC4_CS3 peripheral ========== \r
+#define AT91C_CS3_MODE  (AT91_CAST(AT91_REG *)         0x400E00BC) // (HSMC4_CS3) Mode Register\r
+#define AT91C_CS3_TIMINGS (AT91_CAST(AT91_REG *)       0x400E00B8) // (HSMC4_CS3) Timmings Register\r
+#define AT91C_CS3_SETUP (AT91_CAST(AT91_REG *)         0x400E00AC) // (HSMC4_CS3) Setup Register\r
+#define AT91C_CS3_CYCLE (AT91_CAST(AT91_REG *)         0x400E00B4) // (HSMC4_CS3) Cycle Register\r
+#define AT91C_CS3_PULSE (AT91_CAST(AT91_REG *)         0x400E00B0) // (HSMC4_CS3) Pulse Register\r
+// ========== Register definition for HSMC4_NFC peripheral ========== \r
+#define AT91C_NFC_MODE  (AT91_CAST(AT91_REG *)         0x400E010C) // (HSMC4_NFC) Mode Register\r
+#define AT91C_NFC_CYCLE (AT91_CAST(AT91_REG *)         0x400E0104) // (HSMC4_NFC) Cycle Register\r
+#define AT91C_NFC_PULSE (AT91_CAST(AT91_REG *)         0x400E0100) // (HSMC4_NFC) Pulse Register\r
+#define AT91C_NFC_SETUP (AT91_CAST(AT91_REG *)         0x400E00FC) // (HSMC4_NFC) Setup Register\r
+#define AT91C_NFC_TIMINGS (AT91_CAST(AT91_REG *)       0x400E0108) // (HSMC4_NFC) Timmings Register\r
+// ========== Register definition for HSMC4 peripheral ========== \r
+#define AT91C_HSMC4_IPNAME1 (AT91_CAST(AT91_REG *)     0x400E01F0) // (HSMC4) Write Protection Status Register\r
+#define AT91C_HSMC4_ECCPR6 (AT91_CAST(AT91_REG *)      0x400E0048) // (HSMC4) ECC Parity register 6\r
+#define AT91C_HSMC4_ADDRSIZE (AT91_CAST(AT91_REG *)    0x400E01EC) // (HSMC4) Write Protection Status Register\r
+#define AT91C_HSMC4_ECCPR11 (AT91_CAST(AT91_REG *)     0x400E005C) // (HSMC4) ECC Parity register 11\r
+#define AT91C_HSMC4_SR  (AT91_CAST(AT91_REG *)         0x400E0008) // (HSMC4) Status Register\r
+#define AT91C_HSMC4_IMR (AT91_CAST(AT91_REG *)         0x400E0014) // (HSMC4) Interrupt Mask Register\r
+#define AT91C_HSMC4_WPSR (AT91_CAST(AT91_REG *)        0x400E01E8) // (HSMC4) Write Protection Status Register\r
+#define AT91C_HSMC4_BANK (AT91_CAST(AT91_REG *)        0x400E001C) // (HSMC4) Bank Register\r
+#define AT91C_HSMC4_ECCPR8 (AT91_CAST(AT91_REG *)      0x400E0050) // (HSMC4) ECC Parity register 8\r
+#define AT91C_HSMC4_WPCR (AT91_CAST(AT91_REG *)        0x400E01E4) // (HSMC4) Write Protection Control register\r
+#define AT91C_HSMC4_ECCPR2 (AT91_CAST(AT91_REG *)      0x400E0038) // (HSMC4) ECC Parity register 2\r
+#define AT91C_HSMC4_ECCPR1 (AT91_CAST(AT91_REG *)      0x400E0030) // (HSMC4) ECC Parity register 1\r
+#define AT91C_HSMC4_ECCSR2 (AT91_CAST(AT91_REG *)      0x400E0034) // (HSMC4) ECC Status register 2\r
+#define AT91C_HSMC4_OCMS (AT91_CAST(AT91_REG *)        0x400E0110) // (HSMC4) OCMS MODE register\r
+#define AT91C_HSMC4_ECCPR9 (AT91_CAST(AT91_REG *)      0x400E0054) // (HSMC4) ECC Parity register 9\r
+#define AT91C_HSMC4_DUMMY (AT91_CAST(AT91_REG *)       0x400E0200) // (HSMC4) This rtegister was created only ti have AHB constants\r
+#define AT91C_HSMC4_ECCPR5 (AT91_CAST(AT91_REG *)      0x400E0044) // (HSMC4) ECC Parity register 5\r
+#define AT91C_HSMC4_ECCCR (AT91_CAST(AT91_REG *)       0x400E0020) // (HSMC4) ECC reset register\r
+#define AT91C_HSMC4_KEY2 (AT91_CAST(AT91_REG *)        0x400E0118) // (HSMC4) KEY2 Register\r
+#define AT91C_HSMC4_IER (AT91_CAST(AT91_REG *)         0x400E000C) // (HSMC4) Interrupt Enable Register\r
+#define AT91C_HSMC4_ECCSR1 (AT91_CAST(AT91_REG *)      0x400E0028) // (HSMC4) ECC Status register 1\r
+#define AT91C_HSMC4_IDR (AT91_CAST(AT91_REG *)         0x400E0010) // (HSMC4) Interrupt Disable Register\r
+#define AT91C_HSMC4_ECCPR0 (AT91_CAST(AT91_REG *)      0x400E002C) // (HSMC4) ECC Parity register 0\r
+#define AT91C_HSMC4_FEATURES (AT91_CAST(AT91_REG *)    0x400E01F8) // (HSMC4) Write Protection Status Register\r
+#define AT91C_HSMC4_ECCPR7 (AT91_CAST(AT91_REG *)      0x400E004C) // (HSMC4) ECC Parity register 7\r
+#define AT91C_HSMC4_ECCPR12 (AT91_CAST(AT91_REG *)     0x400E0060) // (HSMC4) ECC Parity register 12\r
+#define AT91C_HSMC4_ECCPR10 (AT91_CAST(AT91_REG *)     0x400E0058) // (HSMC4) ECC Parity register 10\r
+#define AT91C_HSMC4_KEY1 (AT91_CAST(AT91_REG *)        0x400E0114) // (HSMC4) KEY1 Register\r
+#define AT91C_HSMC4_VER (AT91_CAST(AT91_REG *)         0x400E01FC) // (HSMC4) HSMC4 Version Register\r
+#define AT91C_HSMC4_Eccpr15 (AT91_CAST(AT91_REG *)     0x400E006C) // (HSMC4) ECC Parity register 15\r
+#define AT91C_HSMC4_ECCPR4 (AT91_CAST(AT91_REG *)      0x400E0040) // (HSMC4) ECC Parity register 4\r
+#define AT91C_HSMC4_IPNAME2 (AT91_CAST(AT91_REG *)     0x400E01F4) // (HSMC4) Write Protection Status Register\r
+#define AT91C_HSMC4_ECCCMD (AT91_CAST(AT91_REG *)      0x400E0024) // (HSMC4) ECC Page size register\r
+#define AT91C_HSMC4_ADDR (AT91_CAST(AT91_REG *)        0x400E0018) // (HSMC4) Address Cycle Zero Register\r
+#define AT91C_HSMC4_ECCPR3 (AT91_CAST(AT91_REG *)      0x400E003C) // (HSMC4) ECC Parity register 3\r
+#define AT91C_HSMC4_CFG (AT91_CAST(AT91_REG *)         0x400E0000) // (HSMC4) Configuration Register\r
+#define AT91C_HSMC4_CTRL (AT91_CAST(AT91_REG *)        0x400E0004) // (HSMC4) Control Register\r
+#define AT91C_HSMC4_ECCPR13 (AT91_CAST(AT91_REG *)     0x400E0064) // (HSMC4) ECC Parity register 13\r
+#define AT91C_HSMC4_ECCPR14 (AT91_CAST(AT91_REG *)     0x400E0068) // (HSMC4) ECC Parity register 14\r
+// ========== Register definition for MATRIX peripheral ========== \r
+#define AT91C_MATRIX_SFR2  (AT91_CAST(AT91_REG *)      0x400E0318) // (MATRIX)  Special Function Register 2\r
+#define AT91C_MATRIX_SFR3  (AT91_CAST(AT91_REG *)      0x400E031C) // (MATRIX)  Special Function Register 3\r
+#define AT91C_MATRIX_SCFG8 (AT91_CAST(AT91_REG *)      0x400E0260) // (MATRIX)  Slave Configuration Register 8\r
+#define AT91C_MATRIX_MCFG2 (AT91_CAST(AT91_REG *)      0x400E0208) // (MATRIX)  Master Configuration Register 2\r
+#define AT91C_MATRIX_MCFG7 (AT91_CAST(AT91_REG *)      0x400E021C) // (MATRIX)  Master Configuration Register 7\r
+#define AT91C_MATRIX_SCFG3 (AT91_CAST(AT91_REG *)      0x400E024C) // (MATRIX)  Slave Configuration Register 3\r
+#define AT91C_MATRIX_SCFG0 (AT91_CAST(AT91_REG *)      0x400E0240) // (MATRIX)  Slave Configuration Register 0\r
+#define AT91C_MATRIX_SFR12 (AT91_CAST(AT91_REG *)      0x400E0340) // (MATRIX)  Special Function Register 12\r
+#define AT91C_MATRIX_SCFG1 (AT91_CAST(AT91_REG *)      0x400E0244) // (MATRIX)  Slave Configuration Register 1\r
+#define AT91C_MATRIX_SFR8  (AT91_CAST(AT91_REG *)      0x400E0330) // (MATRIX)  Special Function Register 8\r
+#define AT91C_MATRIX_VER (AT91_CAST(AT91_REG *)        0x400E03FC) // (MATRIX) HMATRIX2 VERSION REGISTER \r
+#define AT91C_MATRIX_SFR13 (AT91_CAST(AT91_REG *)      0x400E0344) // (MATRIX)  Special Function Register 13\r
+#define AT91C_MATRIX_SFR5  (AT91_CAST(AT91_REG *)      0x400E0324) // (MATRIX)  Special Function Register 5\r
+#define AT91C_MATRIX_MCFG0 (AT91_CAST(AT91_REG *)      0x400E0200) // (MATRIX)  Master Configuration Register 0 : ARM I and D\r
+#define AT91C_MATRIX_SCFG6 (AT91_CAST(AT91_REG *)      0x400E0258) // (MATRIX)  Slave Configuration Register 6\r
+#define AT91C_MATRIX_SFR1  (AT91_CAST(AT91_REG *)      0x400E0314) // (MATRIX)  Special Function Register 1\r
+#define AT91C_MATRIX_SFR14 (AT91_CAST(AT91_REG *)      0x400E0348) // (MATRIX)  Special Function Register 14\r
+#define AT91C_MATRIX_SFR15 (AT91_CAST(AT91_REG *)      0x400E034C) // (MATRIX)  Special Function Register 15\r
+#define AT91C_MATRIX_SFR6  (AT91_CAST(AT91_REG *)      0x400E0328) // (MATRIX)  Special Function Register 6\r
+#define AT91C_MATRIX_SFR11 (AT91_CAST(AT91_REG *)      0x400E033C) // (MATRIX)  Special Function Register 11\r
+#define AT91C_MATRIX_IPNAME2 (AT91_CAST(AT91_REG *)    0x400E03F4) // (MATRIX) HMATRIX2 IPNAME2 REGISTER \r
+#define AT91C_MATRIX_ADDRSIZE (AT91_CAST(AT91_REG *)   0x400E03EC) // (MATRIX) HMATRIX2 ADDRSIZE REGISTER \r
+#define AT91C_MATRIX_MCFG5 (AT91_CAST(AT91_REG *)      0x400E0214) // (MATRIX)  Master Configuration Register 5\r
+#define AT91C_MATRIX_SFR9  (AT91_CAST(AT91_REG *)      0x400E0334) // (MATRIX)  Special Function Register 9\r
+#define AT91C_MATRIX_MCFG3 (AT91_CAST(AT91_REG *)      0x400E020C) // (MATRIX)  Master Configuration Register 3\r
+#define AT91C_MATRIX_SCFG4 (AT91_CAST(AT91_REG *)      0x400E0250) // (MATRIX)  Slave Configuration Register 4\r
+#define AT91C_MATRIX_MCFG1 (AT91_CAST(AT91_REG *)      0x400E0204) // (MATRIX)  Master Configuration Register 1 : ARM S\r
+#define AT91C_MATRIX_SCFG7 (AT91_CAST(AT91_REG *)      0x400E025C) // (MATRIX)  Slave Configuration Register 5\r
+#define AT91C_MATRIX_SFR10 (AT91_CAST(AT91_REG *)      0x400E0338) // (MATRIX)  Special Function Register 10\r
+#define AT91C_MATRIX_SCFG2 (AT91_CAST(AT91_REG *)      0x400E0248) // (MATRIX)  Slave Configuration Register 2\r
+#define AT91C_MATRIX_SFR7  (AT91_CAST(AT91_REG *)      0x400E032C) // (MATRIX)  Special Function Register 7\r
+#define AT91C_MATRIX_IPNAME1 (AT91_CAST(AT91_REG *)    0x400E03F0) // (MATRIX) HMATRIX2 IPNAME1 REGISTER \r
+#define AT91C_MATRIX_MCFG4 (AT91_CAST(AT91_REG *)      0x400E0210) // (MATRIX)  Master Configuration Register 4\r
+#define AT91C_MATRIX_SFR0  (AT91_CAST(AT91_REG *)      0x400E0310) // (MATRIX)  Special Function Register 0\r
+#define AT91C_MATRIX_FEATURES (AT91_CAST(AT91_REG *)   0x400E03F8) // (MATRIX) HMATRIX2 FEATURES REGISTER \r
+#define AT91C_MATRIX_SCFG5 (AT91_CAST(AT91_REG *)      0x400E0254) // (MATRIX)  Slave Configuration Register 5\r
+#define AT91C_MATRIX_MCFG6 (AT91_CAST(AT91_REG *)      0x400E0218) // (MATRIX)  Master Configuration Register 6\r
+#define AT91C_MATRIX_SFR4  (AT91_CAST(AT91_REG *)      0x400E0320) // (MATRIX)  Special Function Register 4\r
+// ========== Register definition for NVIC peripheral ========== \r
+#define AT91C_NVIC_MMAR (AT91_CAST(AT91_REG *)         0xE000ED34) // (NVIC) Mem Manage Address Register\r
+#define AT91C_NVIC_STIR (AT91_CAST(AT91_REG *)         0xE000EF00) // (NVIC) Software Trigger Interrupt Register\r
+#define AT91C_NVIC_MMFR2 (AT91_CAST(AT91_REG *)        0xE000ED58) // (NVIC) Memory Model Feature register2\r
+#define AT91C_NVIC_CPUID (AT91_CAST(AT91_REG *)        0xE000ED00) // (NVIC) CPUID Base Register\r
+#define AT91C_NVIC_DFSR (AT91_CAST(AT91_REG *)         0xE000ED30) // (NVIC) Debug Fault Status Register\r
+#define AT91C_NVIC_HAND4PR (AT91_CAST(AT91_REG *)      0xE000ED18) // (NVIC) System Handlers 4-7 Priority Register\r
+#define AT91C_NVIC_HFSR (AT91_CAST(AT91_REG *)         0xE000ED2C) // (NVIC) Hard Fault Status Register\r
+#define AT91C_NVIC_PID6 (AT91_CAST(AT91_REG *)         0xE000EFD8) // (NVIC) Peripheral identification register\r
+#define AT91C_NVIC_PFR0 (AT91_CAST(AT91_REG *)         0xE000ED40) // (NVIC) Processor Feature register0\r
+#define AT91C_NVIC_VTOFFR (AT91_CAST(AT91_REG *)       0xE000ED08) // (NVIC) Vector Table Offset Register\r
+#define AT91C_NVIC_ISPR (AT91_CAST(AT91_REG *)         0xE000E200) // (NVIC) Set Pending Register\r
+#define AT91C_NVIC_PID0 (AT91_CAST(AT91_REG *)         0xE000EFE0) // (NVIC) Peripheral identification register b7:0\r
+#define AT91C_NVIC_PID7 (AT91_CAST(AT91_REG *)         0xE000EFDC) // (NVIC) Peripheral identification register\r
+#define AT91C_NVIC_STICKRVR (AT91_CAST(AT91_REG *)     0xE000E014) // (NVIC) SysTick Reload Value Register\r
+#define AT91C_NVIC_PID2 (AT91_CAST(AT91_REG *)         0xE000EFE8) // (NVIC) Peripheral identification register b23:16\r
+#define AT91C_NVIC_ISAR0 (AT91_CAST(AT91_REG *)        0xE000ED60) // (NVIC) ISA Feature register0\r
+#define AT91C_NVIC_SCR  (AT91_CAST(AT91_REG *)         0xE000ED10) // (NVIC) System Control Register\r
+#define AT91C_NVIC_PID4 (AT91_CAST(AT91_REG *)         0xE000EFD0) // (NVIC) Peripheral identification register\r
+#define AT91C_NVIC_ISAR2 (AT91_CAST(AT91_REG *)        0xE000ED68) // (NVIC) ISA Feature register2\r
+#define AT91C_NVIC_ISER (AT91_CAST(AT91_REG *)         0xE000E100) // (NVIC) Set Enable Register\r
+#define AT91C_NVIC_IPR  (AT91_CAST(AT91_REG *)         0xE000E400) // (NVIC) Interrupt Mask Register\r
+#define AT91C_NVIC_AIRCR (AT91_CAST(AT91_REG *)        0xE000ED0C) // (NVIC) Application Interrupt/Reset Control Reg\r
+#define AT91C_NVIC_CID2 (AT91_CAST(AT91_REG *)         0xE000EFF8) // (NVIC) Component identification register b23:16\r
+#define AT91C_NVIC_ICPR (AT91_CAST(AT91_REG *)         0xE000E280) // (NVIC) Clear Pending Register\r
+#define AT91C_NVIC_CID3 (AT91_CAST(AT91_REG *)         0xE000EFFC) // (NVIC) Component identification register b31:24\r
+#define AT91C_NVIC_CFSR (AT91_CAST(AT91_REG *)         0xE000ED28) // (NVIC) Configurable Fault Status Register\r
+#define AT91C_NVIC_AFR0 (AT91_CAST(AT91_REG *)         0xE000ED4C) // (NVIC) Auxiliary Feature register0\r
+#define AT91C_NVIC_ICSR (AT91_CAST(AT91_REG *)         0xE000ED04) // (NVIC) Interrupt Control State Register\r
+#define AT91C_NVIC_CCR  (AT91_CAST(AT91_REG *)         0xE000ED14) // (NVIC) Configuration Control Register\r
+#define AT91C_NVIC_CID0 (AT91_CAST(AT91_REG *)         0xE000EFF0) // (NVIC) Component identification register b7:0\r
+#define AT91C_NVIC_ISAR1 (AT91_CAST(AT91_REG *)        0xE000ED64) // (NVIC) ISA Feature register1\r
+#define AT91C_NVIC_STICKCVR (AT91_CAST(AT91_REG *)     0xE000E018) // (NVIC) SysTick Current Value Register\r
+#define AT91C_NVIC_STICKCSR (AT91_CAST(AT91_REG *)     0xE000E010) // (NVIC) SysTick Control and Status Register\r
+#define AT91C_NVIC_CID1 (AT91_CAST(AT91_REG *)         0xE000EFF4) // (NVIC) Component identification register b15:8\r
+#define AT91C_NVIC_DFR0 (AT91_CAST(AT91_REG *)         0xE000ED48) // (NVIC) Debug Feature register0\r
+#define AT91C_NVIC_MMFR3 (AT91_CAST(AT91_REG *)        0xE000ED5C) // (NVIC) Memory Model Feature register3\r
+#define AT91C_NVIC_MMFR0 (AT91_CAST(AT91_REG *)        0xE000ED50) // (NVIC) Memory Model Feature register0\r
+#define AT91C_NVIC_STICKCALVR (AT91_CAST(AT91_REG *)   0xE000E01C) // (NVIC) SysTick Calibration Value Register\r
+#define AT91C_NVIC_PID1 (AT91_CAST(AT91_REG *)         0xE000EFE4) // (NVIC) Peripheral identification register b15:8\r
+#define AT91C_NVIC_HAND12PR (AT91_CAST(AT91_REG *)     0xE000ED20) // (NVIC) System Handlers 12-15 Priority Register\r
+#define AT91C_NVIC_MMFR1 (AT91_CAST(AT91_REG *)        0xE000ED54) // (NVIC) Memory Model Feature register1\r
+#define AT91C_NVIC_AFSR (AT91_CAST(AT91_REG *)         0xE000ED3C) // (NVIC) Auxiliary Fault Status Register\r
+#define AT91C_NVIC_HANDCSR (AT91_CAST(AT91_REG *)      0xE000ED24) // (NVIC) System Handler Control and State Register\r
+#define AT91C_NVIC_ISAR4 (AT91_CAST(AT91_REG *)        0xE000ED70) // (NVIC) ISA Feature register4\r
+#define AT91C_NVIC_ABR  (AT91_CAST(AT91_REG *)         0xE000E300) // (NVIC) Active Bit Register\r
+#define AT91C_NVIC_PFR1 (AT91_CAST(AT91_REG *)         0xE000ED44) // (NVIC) Processor Feature register1\r
+#define AT91C_NVIC_PID5 (AT91_CAST(AT91_REG *)         0xE000EFD4) // (NVIC) Peripheral identification register\r
+#define AT91C_NVIC_ICTR (AT91_CAST(AT91_REG *)         0xE000E004) // (NVIC) Interrupt Control Type Register\r
+#define AT91C_NVIC_ICER (AT91_CAST(AT91_REG *)         0xE000E180) // (NVIC) Clear enable Register\r
+#define AT91C_NVIC_PID3 (AT91_CAST(AT91_REG *)         0xE000EFEC) // (NVIC) Peripheral identification register b31:24\r
+#define AT91C_NVIC_ISAR3 (AT91_CAST(AT91_REG *)        0xE000ED6C) // (NVIC) ISA Feature register3\r
+#define AT91C_NVIC_HAND8PR (AT91_CAST(AT91_REG *)      0xE000ED1C) // (NVIC) System Handlers 8-11 Priority Register\r
+#define AT91C_NVIC_BFAR (AT91_CAST(AT91_REG *)         0xE000ED38) // (NVIC) Bus Fault Address Register\r
+// ========== Register definition for MPU peripheral ========== \r
+#define AT91C_MPU_REG_BASE_ADDR3 (AT91_CAST(AT91_REG *)        0xE000EDB4) // (MPU) MPU Region Base Address Register alias 3\r
+#define AT91C_MPU_REG_NB (AT91_CAST(AT91_REG *)        0xE000ED98) // (MPU) MPU Region Number Register\r
+#define AT91C_MPU_ATTR_SIZE1 (AT91_CAST(AT91_REG *)    0xE000EDA8) // (MPU) MPU  Attribute and Size Register alias 1\r
+#define AT91C_MPU_REG_BASE_ADDR1 (AT91_CAST(AT91_REG *)        0xE000EDA4) // (MPU) MPU Region Base Address Register alias 1\r
+#define AT91C_MPU_ATTR_SIZE3 (AT91_CAST(AT91_REG *)    0xE000EDB8) // (MPU) MPU  Attribute and Size Register alias 3\r
+#define AT91C_MPU_CTRL  (AT91_CAST(AT91_REG *)         0xE000ED94) // (MPU) MPU Control Register\r
+#define AT91C_MPU_ATTR_SIZE2 (AT91_CAST(AT91_REG *)    0xE000EDB0) // (MPU) MPU  Attribute and Size Register alias 2\r
+#define AT91C_MPU_REG_BASE_ADDR (AT91_CAST(AT91_REG *)         0xE000ED9C) // (MPU) MPU Region Base Address Register\r
+#define AT91C_MPU_REG_BASE_ADDR2 (AT91_CAST(AT91_REG *)        0xE000EDAC) // (MPU) MPU Region Base Address Register alias 2\r
+#define AT91C_MPU_ATTR_SIZE (AT91_CAST(AT91_REG *)     0xE000EDA0) // (MPU) MPU  Attribute and Size Register\r
+#define AT91C_MPU_TYPE  (AT91_CAST(AT91_REG *)         0xE000ED90) // (MPU) MPU Type Register\r
+// ========== Register definition for CM3 peripheral ========== \r
+#define AT91C_CM3_SHCSR (AT91_CAST(AT91_REG *)         0xE000ED24) // (CM3) System Handler Control and State Register\r
+#define AT91C_CM3_CCR   (AT91_CAST(AT91_REG *)         0xE000ED14) // (CM3) Configuration Control Register\r
+#define AT91C_CM3_ICSR  (AT91_CAST(AT91_REG *)         0xE000ED04) // (CM3) Interrupt Control State Register\r
+#define AT91C_CM3_CPUID (AT91_CAST(AT91_REG *)         0xE000ED00) // (CM3) CPU ID Base Register\r
+#define AT91C_CM3_SCR   (AT91_CAST(AT91_REG *)         0xE000ED10) // (CM3) System Controller Register\r
+#define AT91C_CM3_AIRCR (AT91_CAST(AT91_REG *)         0xE000ED0C) // (CM3) Application Interrupt and Reset Control Register\r
+#define AT91C_CM3_SHPR  (AT91_CAST(AT91_REG *)         0xE000ED18) // (CM3) System Handler Priority Register\r
+#define AT91C_CM3_VTOR  (AT91_CAST(AT91_REG *)         0xE000ED08) // (CM3) Vector Table Offset Register\r
+// ========== Register definition for PDC_DBGU peripheral ========== \r
+#define AT91C_DBGU_TPR  (AT91_CAST(AT91_REG *)         0x400E0708) // (PDC_DBGU) Transmit Pointer Register\r
+#define AT91C_DBGU_PTCR (AT91_CAST(AT91_REG *)         0x400E0720) // (PDC_DBGU) PDC Transfer Control Register\r
+#define AT91C_DBGU_TNCR (AT91_CAST(AT91_REG *)         0x400E071C) // (PDC_DBGU) Transmit Next Counter Register\r
+#define AT91C_DBGU_PTSR (AT91_CAST(AT91_REG *)         0x400E0724) // (PDC_DBGU) PDC Transfer Status Register\r
+#define AT91C_DBGU_RNCR (AT91_CAST(AT91_REG *)         0x400E0714) // (PDC_DBGU) Receive Next Counter Register\r
+#define AT91C_DBGU_RPR  (AT91_CAST(AT91_REG *)         0x400E0700) // (PDC_DBGU) Receive Pointer Register\r
+#define AT91C_DBGU_TCR  (AT91_CAST(AT91_REG *)         0x400E070C) // (PDC_DBGU) Transmit Counter Register\r
+#define AT91C_DBGU_RNPR (AT91_CAST(AT91_REG *)         0x400E0710) // (PDC_DBGU) Receive Next Pointer Register\r
+#define AT91C_DBGU_TNPR (AT91_CAST(AT91_REG *)         0x400E0718) // (PDC_DBGU) Transmit Next Pointer Register\r
+#define AT91C_DBGU_RCR  (AT91_CAST(AT91_REG *)         0x400E0704) // (PDC_DBGU) Receive Counter Register\r
+// ========== Register definition for DBGU peripheral ========== \r
+#define AT91C_DBGU_CR   (AT91_CAST(AT91_REG *)         0x400E0600) // (DBGU) Control Register\r
+#define AT91C_DBGU_IDR  (AT91_CAST(AT91_REG *)         0x400E060C) // (DBGU) Interrupt Disable Register\r
+#define AT91C_DBGU_CIDR (AT91_CAST(AT91_REG *)         0x400E0740) // (DBGU) Chip ID Register\r
+#define AT91C_DBGU_IPNAME2 (AT91_CAST(AT91_REG *)      0x400E06F4) // (DBGU) DBGU IPNAME2 REGISTER \r
+#define AT91C_DBGU_FEATURES (AT91_CAST(AT91_REG *)     0x400E06F8) // (DBGU) DBGU FEATURES REGISTER \r
+#define AT91C_DBGU_FNTR (AT91_CAST(AT91_REG *)         0x400E0648) // (DBGU) Force NTRST Register\r
+#define AT91C_DBGU_RHR  (AT91_CAST(AT91_REG *)         0x400E0618) // (DBGU) Receiver Holding Register\r
+#define AT91C_DBGU_THR  (AT91_CAST(AT91_REG *)         0x400E061C) // (DBGU) Transmitter Holding Register\r
+#define AT91C_DBGU_ADDRSIZE (AT91_CAST(AT91_REG *)     0x400E06EC) // (DBGU) DBGU ADDRSIZE REGISTER \r
+#define AT91C_DBGU_MR   (AT91_CAST(AT91_REG *)         0x400E0604) // (DBGU) Mode Register\r
+#define AT91C_DBGU_IER  (AT91_CAST(AT91_REG *)         0x400E0608) // (DBGU) Interrupt Enable Register\r
+#define AT91C_DBGU_BRGR (AT91_CAST(AT91_REG *)         0x400E0620) // (DBGU) Baud Rate Generator Register\r
+#define AT91C_DBGU_CSR  (AT91_CAST(AT91_REG *)         0x400E0614) // (DBGU) Channel Status Register\r
+#define AT91C_DBGU_VER  (AT91_CAST(AT91_REG *)         0x400E06FC) // (DBGU) DBGU VERSION REGISTER \r
+#define AT91C_DBGU_IMR  (AT91_CAST(AT91_REG *)         0x400E0610) // (DBGU) Interrupt Mask Register\r
+#define AT91C_DBGU_IPNAME1 (AT91_CAST(AT91_REG *)      0x400E06F0) // (DBGU) DBGU IPNAME1 REGISTER \r
+#define AT91C_DBGU_EXID (AT91_CAST(AT91_REG *)         0x400E0744) // (DBGU) Chip ID Extension Register\r
+// ========== Register definition for PIOA peripheral ========== \r
+#define AT91C_PIOA_PDR  (AT91_CAST(AT91_REG *)         0x400E0C04) // (PIOA) PIO Disable Register\r
+#define AT91C_PIOA_FRLHSR (AT91_CAST(AT91_REG *)       0x400E0CD8) // (PIOA) Fall/Rise - Low/High Status Register\r
+#define AT91C_PIOA_KIMR (AT91_CAST(AT91_REG *)         0x400E0D38) // (PIOA) Keypad Controller Interrupt Mask Register\r
+#define AT91C_PIOA_LSR  (AT91_CAST(AT91_REG *)         0x400E0CC4) // (PIOA) Level Select Register\r
+#define AT91C_PIOA_IFSR (AT91_CAST(AT91_REG *)         0x400E0C28) // (PIOA) Input Filter Status Register\r
+#define AT91C_PIOA_KKRR (AT91_CAST(AT91_REG *)         0x400E0D44) // (PIOA) Keypad Controller Key Release Register\r
+#define AT91C_PIOA_ODR  (AT91_CAST(AT91_REG *)         0x400E0C14) // (PIOA) Output Disable Registerr\r
+#define AT91C_PIOA_SCIFSR (AT91_CAST(AT91_REG *)       0x400E0C80) // (PIOA) System Clock Glitch Input Filter Select Register\r
+#define AT91C_PIOA_PER  (AT91_CAST(AT91_REG *)         0x400E0C00) // (PIOA) PIO Enable Register\r
+#define AT91C_PIOA_VER  (AT91_CAST(AT91_REG *)         0x400E0CFC) // (PIOA) PIO VERSION REGISTER \r
+#define AT91C_PIOA_OWSR (AT91_CAST(AT91_REG *)         0x400E0CA8) // (PIOA) Output Write Status Register\r
+#define AT91C_PIOA_KSR  (AT91_CAST(AT91_REG *)         0x400E0D3C) // (PIOA) Keypad Controller Status Register\r
+#define AT91C_PIOA_IMR  (AT91_CAST(AT91_REG *)         0x400E0C48) // (PIOA) Interrupt Mask Register\r
+#define AT91C_PIOA_OWDR (AT91_CAST(AT91_REG *)         0x400E0CA4) // (PIOA) Output Write Disable Register\r
+#define AT91C_PIOA_MDSR (AT91_CAST(AT91_REG *)         0x400E0C58) // (PIOA) Multi-driver Status Register\r
+#define AT91C_PIOA_IFDR (AT91_CAST(AT91_REG *)         0x400E0C24) // (PIOA) Input Filter Disable Register\r
+#define AT91C_PIOA_AIMDR (AT91_CAST(AT91_REG *)        0x400E0CB4) // (PIOA) Additional Interrupt Modes Disables Register\r
+#define AT91C_PIOA_CODR (AT91_CAST(AT91_REG *)         0x400E0C34) // (PIOA) Clear Output Data Register\r
+#define AT91C_PIOA_SCDR (AT91_CAST(AT91_REG *)         0x400E0C8C) // (PIOA) Slow Clock Divider Debouncing Register\r
+#define AT91C_PIOA_KIER (AT91_CAST(AT91_REG *)         0x400E0D30) // (PIOA) Keypad Controller Interrupt Enable Register\r
+#define AT91C_PIOA_REHLSR (AT91_CAST(AT91_REG *)       0x400E0CD4) // (PIOA) Rising Edge/ High Level Select Register\r
+#define AT91C_PIOA_ISR  (AT91_CAST(AT91_REG *)         0x400E0C4C) // (PIOA) Interrupt Status Register\r
+#define AT91C_PIOA_ESR  (AT91_CAST(AT91_REG *)         0x400E0CC0) // (PIOA) Edge Select Register\r
+#define AT91C_PIOA_PPUDR (AT91_CAST(AT91_REG *)        0x400E0C60) // (PIOA) Pull-up Disable Register\r
+#define AT91C_PIOA_MDDR (AT91_CAST(AT91_REG *)         0x400E0C54) // (PIOA) Multi-driver Disable Register\r
+#define AT91C_PIOA_PSR  (AT91_CAST(AT91_REG *)         0x400E0C08) // (PIOA) PIO Status Register\r
+#define AT91C_PIOA_PDSR (AT91_CAST(AT91_REG *)         0x400E0C3C) // (PIOA) Pin Data Status Register\r
+#define AT91C_PIOA_IFDGSR (AT91_CAST(AT91_REG *)       0x400E0C88) // (PIOA) Glitch or Debouncing Input Filter Clock Selection Status Register\r
+#define AT91C_PIOA_FELLSR (AT91_CAST(AT91_REG *)       0x400E0CD0) // (PIOA) Falling Edge/Low Level Select Register\r
+#define AT91C_PIOA_PPUSR (AT91_CAST(AT91_REG *)        0x400E0C68) // (PIOA) Pull-up Status Register\r
+#define AT91C_PIOA_OER  (AT91_CAST(AT91_REG *)         0x400E0C10) // (PIOA) Output Enable Register\r
+#define AT91C_PIOA_OSR  (AT91_CAST(AT91_REG *)         0x400E0C18) // (PIOA) Output Status Register\r
+#define AT91C_PIOA_KKPR (AT91_CAST(AT91_REG *)         0x400E0D40) // (PIOA) Keypad Controller Key Press Register\r
+#define AT91C_PIOA_AIMMR (AT91_CAST(AT91_REG *)        0x400E0CB8) // (PIOA) Additional Interrupt Modes Mask Register\r
+#define AT91C_PIOA_KRCR (AT91_CAST(AT91_REG *)         0x400E0D24) // (PIOA) Keypad Controller Row Column Register\r
+#define AT91C_PIOA_IER  (AT91_CAST(AT91_REG *)         0x400E0C40) // (PIOA) Interrupt Enable Register\r
+#define AT91C_PIOA_KER  (AT91_CAST(AT91_REG *)         0x400E0D20) // (PIOA) Keypad Controller Enable Register\r
+#define AT91C_PIOA_PPUER (AT91_CAST(AT91_REG *)        0x400E0C64) // (PIOA) Pull-up Enable Register\r
+#define AT91C_PIOA_KIDR (AT91_CAST(AT91_REG *)         0x400E0D34) // (PIOA) Keypad Controller Interrupt Disable Register\r
+#define AT91C_PIOA_ABSR (AT91_CAST(AT91_REG *)         0x400E0C70) // (PIOA) Peripheral AB Select Register\r
+#define AT91C_PIOA_LOCKSR (AT91_CAST(AT91_REG *)       0x400E0CE0) // (PIOA) Lock Status Register\r
+#define AT91C_PIOA_DIFSR (AT91_CAST(AT91_REG *)        0x400E0C84) // (PIOA) Debouncing Input Filter Select Register\r
+#define AT91C_PIOA_MDER (AT91_CAST(AT91_REG *)         0x400E0C50) // (PIOA) Multi-driver Enable Register\r
+#define AT91C_PIOA_AIMER (AT91_CAST(AT91_REG *)        0x400E0CB0) // (PIOA) Additional Interrupt Modes Enable Register\r
+#define AT91C_PIOA_ELSR (AT91_CAST(AT91_REG *)         0x400E0CC8) // (PIOA) Edge/Level Status Register\r
+#define AT91C_PIOA_IFER (AT91_CAST(AT91_REG *)         0x400E0C20) // (PIOA) Input Filter Enable Register\r
+#define AT91C_PIOA_KDR  (AT91_CAST(AT91_REG *)         0x400E0D28) // (PIOA) Keypad Controller Debouncing Register\r
+#define AT91C_PIOA_IDR  (AT91_CAST(AT91_REG *)         0x400E0C44) // (PIOA) Interrupt Disable Register\r
+#define AT91C_PIOA_OWER (AT91_CAST(AT91_REG *)         0x400E0CA0) // (PIOA) Output Write Enable Register\r
+#define AT91C_PIOA_ODSR (AT91_CAST(AT91_REG *)         0x400E0C38) // (PIOA) Output Data Status Register\r
+#define AT91C_PIOA_SODR (AT91_CAST(AT91_REG *)         0x400E0C30) // (PIOA) Set Output Data Register\r
+// ========== Register definition for PIOB peripheral ========== \r
+#define AT91C_PIOB_KIDR (AT91_CAST(AT91_REG *)         0x400E0F34) // (PIOB) Keypad Controller Interrupt Disable Register\r
+#define AT91C_PIOB_OWSR (AT91_CAST(AT91_REG *)         0x400E0EA8) // (PIOB) Output Write Status Register\r
+#define AT91C_PIOB_PSR  (AT91_CAST(AT91_REG *)         0x400E0E08) // (PIOB) PIO Status Register\r
+#define AT91C_PIOB_MDER (AT91_CAST(AT91_REG *)         0x400E0E50) // (PIOB) Multi-driver Enable Register\r
+#define AT91C_PIOB_ODR  (AT91_CAST(AT91_REG *)         0x400E0E14) // (PIOB) Output Disable Registerr\r
+#define AT91C_PIOB_IDR  (AT91_CAST(AT91_REG *)         0x400E0E44) // (PIOB) Interrupt Disable Register\r
+#define AT91C_PIOB_AIMER (AT91_CAST(AT91_REG *)        0x400E0EB0) // (PIOB) Additional Interrupt Modes Enable Register\r
+#define AT91C_PIOB_DIFSR (AT91_CAST(AT91_REG *)        0x400E0E84) // (PIOB) Debouncing Input Filter Select Register\r
+#define AT91C_PIOB_PDR  (AT91_CAST(AT91_REG *)         0x400E0E04) // (PIOB) PIO Disable Register\r
+#define AT91C_PIOB_REHLSR (AT91_CAST(AT91_REG *)       0x400E0ED4) // (PIOB) Rising Edge/ High Level Select Register\r
+#define AT91C_PIOB_PDSR (AT91_CAST(AT91_REG *)         0x400E0E3C) // (PIOB) Pin Data Status Register\r
+#define AT91C_PIOB_PPUDR (AT91_CAST(AT91_REG *)        0x400E0E60) // (PIOB) Pull-up Disable Register\r
+#define AT91C_PIOB_LSR  (AT91_CAST(AT91_REG *)         0x400E0EC4) // (PIOB) Level Select Register\r
+#define AT91C_PIOB_OWDR (AT91_CAST(AT91_REG *)         0x400E0EA4) // (PIOB) Output Write Disable Register\r
+#define AT91C_PIOB_FELLSR (AT91_CAST(AT91_REG *)       0x400E0ED0) // (PIOB) Falling Edge/Low Level Select Register\r
+#define AT91C_PIOB_IFER (AT91_CAST(AT91_REG *)         0x400E0E20) // (PIOB) Input Filter Enable Register\r
+#define AT91C_PIOB_ABSR (AT91_CAST(AT91_REG *)         0x400E0E70) // (PIOB) Peripheral AB Select Register\r
+#define AT91C_PIOB_KIMR (AT91_CAST(AT91_REG *)         0x400E0F38) // (PIOB) Keypad Controller Interrupt Mask Register\r
+#define AT91C_PIOB_KKPR (AT91_CAST(AT91_REG *)         0x400E0F40) // (PIOB) Keypad Controller Key Press Register\r
+#define AT91C_PIOB_FRLHSR (AT91_CAST(AT91_REG *)       0x400E0ED8) // (PIOB) Fall/Rise - Low/High Status Register\r
+#define AT91C_PIOB_AIMDR (AT91_CAST(AT91_REG *)        0x400E0EB4) // (PIOB) Additional Interrupt Modes Disables Register\r
+#define AT91C_PIOB_SCIFSR (AT91_CAST(AT91_REG *)       0x400E0E80) // (PIOB) System Clock Glitch Input Filter Select Register\r
+#define AT91C_PIOB_VER  (AT91_CAST(AT91_REG *)         0x400E0EFC) // (PIOB) PIO VERSION REGISTER \r
+#define AT91C_PIOB_PER  (AT91_CAST(AT91_REG *)         0x400E0E00) // (PIOB) PIO Enable Register\r
+#define AT91C_PIOB_ELSR (AT91_CAST(AT91_REG *)         0x400E0EC8) // (PIOB) Edge/Level Status Register\r
+#define AT91C_PIOB_IMR  (AT91_CAST(AT91_REG *)         0x400E0E48) // (PIOB) Interrupt Mask Register\r
+#define AT91C_PIOB_PPUSR (AT91_CAST(AT91_REG *)        0x400E0E68) // (PIOB) Pull-up Status Register\r
+#define AT91C_PIOB_SCDR (AT91_CAST(AT91_REG *)         0x400E0E8C) // (PIOB) Slow Clock Divider Debouncing Register\r
+#define AT91C_PIOB_KSR  (AT91_CAST(AT91_REG *)         0x400E0F3C) // (PIOB) Keypad Controller Status Register\r
+#define AT91C_PIOB_IFDGSR (AT91_CAST(AT91_REG *)       0x400E0E88) // (PIOB) Glitch or Debouncing Input Filter Clock Selection Status Register\r
+#define AT91C_PIOB_ESR  (AT91_CAST(AT91_REG *)         0x400E0EC0) // (PIOB) Edge Select Register\r
+#define AT91C_PIOB_ODSR (AT91_CAST(AT91_REG *)         0x400E0E38) // (PIOB) Output Data Status Register\r
+#define AT91C_PIOB_IFDR (AT91_CAST(AT91_REG *)         0x400E0E24) // (PIOB) Input Filter Disable Register\r
+#define AT91C_PIOB_SODR (AT91_CAST(AT91_REG *)         0x400E0E30) // (PIOB) Set Output Data Register\r
+#define AT91C_PIOB_IER  (AT91_CAST(AT91_REG *)         0x400E0E40) // (PIOB) Interrupt Enable Register\r
+#define AT91C_PIOB_MDSR (AT91_CAST(AT91_REG *)         0x400E0E58) // (PIOB) Multi-driver Status Register\r
+#define AT91C_PIOB_ISR  (AT91_CAST(AT91_REG *)         0x400E0E4C) // (PIOB) Interrupt Status Register\r
+#define AT91C_PIOB_IFSR (AT91_CAST(AT91_REG *)         0x400E0E28) // (PIOB) Input Filter Status Register\r
+#define AT91C_PIOB_KER  (AT91_CAST(AT91_REG *)         0x400E0F20) // (PIOB) Keypad Controller Enable Register\r
+#define AT91C_PIOB_KKRR (AT91_CAST(AT91_REG *)         0x400E0F44) // (PIOB) Keypad Controller Key Release Register\r
+#define AT91C_PIOB_PPUER (AT91_CAST(AT91_REG *)        0x400E0E64) // (PIOB) Pull-up Enable Register\r
+#define AT91C_PIOB_LOCKSR (AT91_CAST(AT91_REG *)       0x400E0EE0) // (PIOB) Lock Status Register\r
+#define AT91C_PIOB_OWER (AT91_CAST(AT91_REG *)         0x400E0EA0) // (PIOB) Output Write Enable Register\r
+#define AT91C_PIOB_KIER (AT91_CAST(AT91_REG *)         0x400E0F30) // (PIOB) Keypad Controller Interrupt Enable Register\r
+#define AT91C_PIOB_MDDR (AT91_CAST(AT91_REG *)         0x400E0E54) // (PIOB) Multi-driver Disable Register\r
+#define AT91C_PIOB_KRCR (AT91_CAST(AT91_REG *)         0x400E0F24) // (PIOB) Keypad Controller Row Column Register\r
+#define AT91C_PIOB_CODR (AT91_CAST(AT91_REG *)         0x400E0E34) // (PIOB) Clear Output Data Register\r
+#define AT91C_PIOB_KDR  (AT91_CAST(AT91_REG *)         0x400E0F28) // (PIOB) Keypad Controller Debouncing Register\r
+#define AT91C_PIOB_AIMMR (AT91_CAST(AT91_REG *)        0x400E0EB8) // (PIOB) Additional Interrupt Modes Mask Register\r
+#define AT91C_PIOB_OER  (AT91_CAST(AT91_REG *)         0x400E0E10) // (PIOB) Output Enable Register\r
+#define AT91C_PIOB_OSR  (AT91_CAST(AT91_REG *)         0x400E0E18) // (PIOB) Output Status Register\r
+// ========== Register definition for PIOC peripheral ========== \r
+#define AT91C_PIOC_FELLSR (AT91_CAST(AT91_REG *)       0x400E10D0) // (PIOC) Falling Edge/Low Level Select Register\r
+#define AT91C_PIOC_FRLHSR (AT91_CAST(AT91_REG *)       0x400E10D8) // (PIOC) Fall/Rise - Low/High Status Register\r
+#define AT91C_PIOC_MDDR (AT91_CAST(AT91_REG *)         0x400E1054) // (PIOC) Multi-driver Disable Register\r
+#define AT91C_PIOC_IFDGSR (AT91_CAST(AT91_REG *)       0x400E1088) // (PIOC) Glitch or Debouncing Input Filter Clock Selection Status Register\r
+#define AT91C_PIOC_ABSR (AT91_CAST(AT91_REG *)         0x400E1070) // (PIOC) Peripheral AB Select Register\r
+#define AT91C_PIOC_KIMR (AT91_CAST(AT91_REG *)         0x400E1138) // (PIOC) Keypad Controller Interrupt Mask Register\r
+#define AT91C_PIOC_KRCR (AT91_CAST(AT91_REG *)         0x400E1124) // (PIOC) Keypad Controller Row Column Register\r
+#define AT91C_PIOC_ODSR (AT91_CAST(AT91_REG *)         0x400E1038) // (PIOC) Output Data Status Register\r
+#define AT91C_PIOC_OSR  (AT91_CAST(AT91_REG *)         0x400E1018) // (PIOC) Output Status Register\r
+#define AT91C_PIOC_IFER (AT91_CAST(AT91_REG *)         0x400E1020) // (PIOC) Input Filter Enable Register\r
+#define AT91C_PIOC_KKPR (AT91_CAST(AT91_REG *)         0x400E1140) // (PIOC) Keypad Controller Key Press Register\r
+#define AT91C_PIOC_MDSR (AT91_CAST(AT91_REG *)         0x400E1058) // (PIOC) Multi-driver Status Register\r
+#define AT91C_PIOC_IFDR (AT91_CAST(AT91_REG *)         0x400E1024) // (PIOC) Input Filter Disable Register\r
+#define AT91C_PIOC_MDER (AT91_CAST(AT91_REG *)         0x400E1050) // (PIOC) Multi-driver Enable Register\r
+#define AT91C_PIOC_SCDR (AT91_CAST(AT91_REG *)         0x400E108C) // (PIOC) Slow Clock Divider Debouncing Register\r
+#define AT91C_PIOC_SCIFSR (AT91_CAST(AT91_REG *)       0x400E1080) // (PIOC) System Clock Glitch Input Filter Select Register\r
+#define AT91C_PIOC_IER  (AT91_CAST(AT91_REG *)         0x400E1040) // (PIOC) Interrupt Enable Register\r
+#define AT91C_PIOC_KDR  (AT91_CAST(AT91_REG *)         0x400E1128) // (PIOC) Keypad Controller Debouncing Register\r
+#define AT91C_PIOC_OWDR (AT91_CAST(AT91_REG *)         0x400E10A4) // (PIOC) Output Write Disable Register\r
+#define AT91C_PIOC_IFSR (AT91_CAST(AT91_REG *)         0x400E1028) // (PIOC) Input Filter Status Register\r
+#define AT91C_PIOC_ISR  (AT91_CAST(AT91_REG *)         0x400E104C) // (PIOC) Interrupt Status Register\r
+#define AT91C_PIOC_PPUDR (AT91_CAST(AT91_REG *)        0x400E1060) // (PIOC) Pull-up Disable Register\r
+#define AT91C_PIOC_PDSR (AT91_CAST(AT91_REG *)         0x400E103C) // (PIOC) Pin Data Status Register\r
+#define AT91C_PIOC_KKRR (AT91_CAST(AT91_REG *)         0x400E1144) // (PIOC) Keypad Controller Key Release Register\r
+#define AT91C_PIOC_AIMDR (AT91_CAST(AT91_REG *)        0x400E10B4) // (PIOC) Additional Interrupt Modes Disables Register\r
+#define AT91C_PIOC_LSR  (AT91_CAST(AT91_REG *)         0x400E10C4) // (PIOC) Level Select Register\r
+#define AT91C_PIOC_PPUER (AT91_CAST(AT91_REG *)        0x400E1064) // (PIOC) Pull-up Enable Register\r
+#define AT91C_PIOC_AIMER (AT91_CAST(AT91_REG *)        0x400E10B0) // (PIOC) Additional Interrupt Modes Enable Register\r
+#define AT91C_PIOC_OER  (AT91_CAST(AT91_REG *)         0x400E1010) // (PIOC) Output Enable Register\r
+#define AT91C_PIOC_CODR (AT91_CAST(AT91_REG *)         0x400E1034) // (PIOC) Clear Output Data Register\r
+#define AT91C_PIOC_AIMMR (AT91_CAST(AT91_REG *)        0x400E10B8) // (PIOC) Additional Interrupt Modes Mask Register\r
+#define AT91C_PIOC_OWER (AT91_CAST(AT91_REG *)         0x400E10A0) // (PIOC) Output Write Enable Register\r
+#define AT91C_PIOC_VER  (AT91_CAST(AT91_REG *)         0x400E10FC) // (PIOC) PIO VERSION REGISTER \r
+#define AT91C_PIOC_IMR  (AT91_CAST(AT91_REG *)         0x400E1048) // (PIOC) Interrupt Mask Register\r
+#define AT91C_PIOC_PPUSR (AT91_CAST(AT91_REG *)        0x400E1068) // (PIOC) Pull-up Status Register\r
+#define AT91C_PIOC_IDR  (AT91_CAST(AT91_REG *)         0x400E1044) // (PIOC) Interrupt Disable Register\r
+#define AT91C_PIOC_DIFSR (AT91_CAST(AT91_REG *)        0x400E1084) // (PIOC) Debouncing Input Filter Select Register\r
+#define AT91C_PIOC_KIDR (AT91_CAST(AT91_REG *)         0x400E1134) // (PIOC) Keypad Controller Interrupt Disable Register\r
+#define AT91C_PIOC_KSR  (AT91_CAST(AT91_REG *)         0x400E113C) // (PIOC) Keypad Controller Status Register\r
+#define AT91C_PIOC_REHLSR (AT91_CAST(AT91_REG *)       0x400E10D4) // (PIOC) Rising Edge/ High Level Select Register\r
+#define AT91C_PIOC_ESR  (AT91_CAST(AT91_REG *)         0x400E10C0) // (PIOC) Edge Select Register\r
+#define AT91C_PIOC_KIER (AT91_CAST(AT91_REG *)         0x400E1130) // (PIOC) Keypad Controller Interrupt Enable Register\r
+#define AT91C_PIOC_ELSR (AT91_CAST(AT91_REG *)         0x400E10C8) // (PIOC) Edge/Level Status Register\r
+#define AT91C_PIOC_SODR (AT91_CAST(AT91_REG *)         0x400E1030) // (PIOC) Set Output Data Register\r
+#define AT91C_PIOC_PSR  (AT91_CAST(AT91_REG *)         0x400E1008) // (PIOC) PIO Status Register\r
+#define AT91C_PIOC_KER  (AT91_CAST(AT91_REG *)         0x400E1120) // (PIOC) Keypad Controller Enable Register\r
+#define AT91C_PIOC_ODR  (AT91_CAST(AT91_REG *)         0x400E1014) // (PIOC) Output Disable Registerr\r
+#define AT91C_PIOC_OWSR (AT91_CAST(AT91_REG *)         0x400E10A8) // (PIOC) Output Write Status Register\r
+#define AT91C_PIOC_PDR  (AT91_CAST(AT91_REG *)         0x400E1004) // (PIOC) PIO Disable Register\r
+#define AT91C_PIOC_LOCKSR (AT91_CAST(AT91_REG *)       0x400E10E0) // (PIOC) Lock Status Register\r
+#define AT91C_PIOC_PER  (AT91_CAST(AT91_REG *)         0x400E1000) // (PIOC) PIO Enable Register\r
+// ========== Register definition for PMC peripheral ========== \r
+#define AT91C_PMC_PLLAR (AT91_CAST(AT91_REG *)         0x400E0428) // (PMC) PLL Register\r
+#define AT91C_PMC_UCKR  (AT91_CAST(AT91_REG *)         0x400E041C) // (PMC) UTMI Clock Configuration Register\r
+#define AT91C_PMC_FSMR  (AT91_CAST(AT91_REG *)         0x400E0470) // (PMC) Fast Startup Mode Register\r
+#define AT91C_PMC_MCKR  (AT91_CAST(AT91_REG *)         0x400E0430) // (PMC) Master Clock Register\r
+#define AT91C_PMC_SCER  (AT91_CAST(AT91_REG *)         0x400E0400) // (PMC) System Clock Enable Register\r
+#define AT91C_PMC_PCSR  (AT91_CAST(AT91_REG *)         0x400E0418) // (PMC) Peripheral Clock Status Register\r
+#define AT91C_PMC_MCFR  (AT91_CAST(AT91_REG *)         0x400E0424) // (PMC) Main Clock  Frequency Register\r
+#define AT91C_PMC_FOCR  (AT91_CAST(AT91_REG *)         0x400E0478) // (PMC) Fault Output Clear Register\r
+#define AT91C_PMC_FSPR  (AT91_CAST(AT91_REG *)         0x400E0474) // (PMC) Fast Startup Polarity Register\r
+#define AT91C_PMC_SCSR  (AT91_CAST(AT91_REG *)         0x400E0408) // (PMC) System Clock Status Register\r
+#define AT91C_PMC_IDR   (AT91_CAST(AT91_REG *)         0x400E0464) // (PMC) Interrupt Disable Register\r
+#define AT91C_PMC_VER   (AT91_CAST(AT91_REG *)         0x400E04FC) // (PMC) APMC VERSION REGISTER\r
+#define AT91C_PMC_IMR   (AT91_CAST(AT91_REG *)         0x400E046C) // (PMC) Interrupt Mask Register\r
+#define AT91C_PMC_IPNAME2 (AT91_CAST(AT91_REG *)       0x400E04F4) // (PMC) PMC IPNAME2 REGISTER \r
+#define AT91C_PMC_SCDR  (AT91_CAST(AT91_REG *)         0x400E0404) // (PMC) System Clock Disable Register\r
+#define AT91C_PMC_PCKR  (AT91_CAST(AT91_REG *)         0x400E0440) // (PMC) Programmable Clock Register\r
+#define AT91C_PMC_ADDRSIZE (AT91_CAST(AT91_REG *)      0x400E04EC) // (PMC) PMC ADDRSIZE REGISTER \r
+#define AT91C_PMC_PCDR  (AT91_CAST(AT91_REG *)         0x400E0414) // (PMC) Peripheral Clock Disable Register\r
+#define AT91C_PMC_MOR   (AT91_CAST(AT91_REG *)         0x400E0420) // (PMC) Main Oscillator Register\r
+#define AT91C_PMC_SR    (AT91_CAST(AT91_REG *)         0x400E0468) // (PMC) Status Register\r
+#define AT91C_PMC_IER   (AT91_CAST(AT91_REG *)         0x400E0460) // (PMC) Interrupt Enable Register\r
+#define AT91C_PMC_IPNAME1 (AT91_CAST(AT91_REG *)       0x400E04F0) // (PMC) PMC IPNAME1 REGISTER \r
+#define AT91C_PMC_PCER  (AT91_CAST(AT91_REG *)         0x400E0410) // (PMC) Peripheral Clock Enable Register\r
+#define AT91C_PMC_FEATURES (AT91_CAST(AT91_REG *)      0x400E04F8) // (PMC) PMC FEATURES REGISTER \r
+// ========== Register definition for CKGR peripheral ========== \r
+#define AT91C_CKGR_PLLAR (AT91_CAST(AT91_REG *)        0x400E0428) // (CKGR) PLL Register\r
+#define AT91C_CKGR_UCKR (AT91_CAST(AT91_REG *)         0x400E041C) // (CKGR) UTMI Clock Configuration Register\r
+#define AT91C_CKGR_MOR  (AT91_CAST(AT91_REG *)         0x400E0420) // (CKGR) Main Oscillator Register\r
+#define AT91C_CKGR_MCFR (AT91_CAST(AT91_REG *)         0x400E0424) // (CKGR) Main Clock  Frequency Register\r
+// ========== Register definition for RSTC peripheral ========== \r
+#define AT91C_RSTC_VER  (AT91_CAST(AT91_REG *)         0x400E12FC) // (RSTC) Version Register\r
+#define AT91C_RSTC_RCR  (AT91_CAST(AT91_REG *)         0x400E1200) // (RSTC) Reset Control Register\r
+#define AT91C_RSTC_RMR  (AT91_CAST(AT91_REG *)         0x400E1208) // (RSTC) Reset Mode Register\r
+#define AT91C_RSTC_RSR  (AT91_CAST(AT91_REG *)         0x400E1204) // (RSTC) Reset Status Register\r
+// ========== Register definition for SUPC peripheral ========== \r
+#define AT91C_SUPC_WUIR (AT91_CAST(AT91_REG *)         0x400E1220) // (SUPC) Wake Up Inputs Register\r
+#define AT91C_SUPC_CR   (AT91_CAST(AT91_REG *)         0x400E1210) // (SUPC) Control Register\r
+#define AT91C_SUPC_MR   (AT91_CAST(AT91_REG *)         0x400E1218) // (SUPC) Mode Register\r
+#define AT91C_SUPC_FWUTR (AT91_CAST(AT91_REG *)        0x400E1228) // (SUPC) Flash Wake-up Timer Register\r
+#define AT91C_SUPC_SR   (AT91_CAST(AT91_REG *)         0x400E1224) // (SUPC) Status Register\r
+#define AT91C_SUPC_WUMR (AT91_CAST(AT91_REG *)         0x400E121C) // (SUPC) Wake Up Mode Register\r
+#define AT91C_SUPC_BOMR (AT91_CAST(AT91_REG *)         0x400E1214) // (SUPC) Brown Out Mode Register\r
+// ========== Register definition for RTTC peripheral ========== \r
+#define AT91C_RTTC_RTVR (AT91_CAST(AT91_REG *)         0x400E1238) // (RTTC) Real-time Value Register\r
+#define AT91C_RTTC_RTAR (AT91_CAST(AT91_REG *)         0x400E1234) // (RTTC) Real-time Alarm Register\r
+#define AT91C_RTTC_RTMR (AT91_CAST(AT91_REG *)         0x400E1230) // (RTTC) Real-time Mode Register\r
+#define AT91C_RTTC_RTSR (AT91_CAST(AT91_REG *)         0x400E123C) // (RTTC) Real-time Status Register\r
+// ========== Register definition for WDTC peripheral ========== \r
+#define AT91C_WDTC_WDSR (AT91_CAST(AT91_REG *)         0x400E1258) // (WDTC) Watchdog Status Register\r
+#define AT91C_WDTC_WDMR (AT91_CAST(AT91_REG *)         0x400E1254) // (WDTC) Watchdog Mode Register\r
+#define AT91C_WDTC_WDCR (AT91_CAST(AT91_REG *)         0x400E1250) // (WDTC) Watchdog Control Register\r
+// ========== Register definition for RTC peripheral ========== \r
+#define AT91C_RTC_IMR   (AT91_CAST(AT91_REG *)         0x400E1288) // (RTC) Interrupt Mask Register\r
+#define AT91C_RTC_SCCR  (AT91_CAST(AT91_REG *)         0x400E127C) // (RTC) Status Clear Command Register\r
+#define AT91C_RTC_CALR  (AT91_CAST(AT91_REG *)         0x400E126C) // (RTC) Calendar Register\r
+#define AT91C_RTC_MR    (AT91_CAST(AT91_REG *)         0x400E1264) // (RTC) Mode Register\r
+#define AT91C_RTC_TIMR  (AT91_CAST(AT91_REG *)         0x400E1268) // (RTC) Time Register\r
+#define AT91C_RTC_CALALR (AT91_CAST(AT91_REG *)        0x400E1274) // (RTC) Calendar Alarm Register\r
+#define AT91C_RTC_VER   (AT91_CAST(AT91_REG *)         0x400E128C) // (RTC) Valid Entry Register\r
+#define AT91C_RTC_CR    (AT91_CAST(AT91_REG *)         0x400E1260) // (RTC) Control Register\r
+#define AT91C_RTC_IDR   (AT91_CAST(AT91_REG *)         0x400E1284) // (RTC) Interrupt Disable Register\r
+#define AT91C_RTC_TIMALR (AT91_CAST(AT91_REG *)        0x400E1270) // (RTC) Time Alarm Register\r
+#define AT91C_RTC_IER   (AT91_CAST(AT91_REG *)         0x400E1280) // (RTC) Interrupt Enable Register\r
+#define AT91C_RTC_SR    (AT91_CAST(AT91_REG *)         0x400E1278) // (RTC) Status Register\r
+// ========== Register definition for ADC0 peripheral ========== \r
+#define AT91C_ADC0_CDR4 (AT91_CAST(AT91_REG *)         0x400A8040) // (ADC0) ADC Channel Data Register 4\r
+#define AT91C_ADC0_CDR2 (AT91_CAST(AT91_REG *)         0x400A8038) // (ADC0) ADC Channel Data Register 2\r
+#define AT91C_ADC0_CHER (AT91_CAST(AT91_REG *)         0x400A8010) // (ADC0) ADC Channel Enable Register\r
+#define AT91C_ADC0_SR   (AT91_CAST(AT91_REG *)         0x400A801C) // (ADC0) ADC Status Register\r
+#define AT91C_ADC0_IPNAME1 (AT91_CAST(AT91_REG *)      0x400A80F0) // (ADC0) ADC IPNAME1 REGISTER \r
+#define AT91C_ADC0_IER  (AT91_CAST(AT91_REG *)         0x400A8024) // (ADC0) ADC Interrupt Enable Register\r
+#define AT91C_ADC0_CR   (AT91_CAST(AT91_REG *)         0x400A8000) // (ADC0) ADC Control Register\r
+#define AT91C_ADC0_CDR6 (AT91_CAST(AT91_REG *)         0x400A8048) // (ADC0) ADC Channel Data Register 6\r
+#define AT91C_ADC0_CHDR (AT91_CAST(AT91_REG *)         0x400A8014) // (ADC0) ADC Channel Disable Register\r
+#define AT91C_ADC0_CDR3 (AT91_CAST(AT91_REG *)         0x400A803C) // (ADC0) ADC Channel Data Register 3\r
+#define AT91C_ADC0_ACR  (AT91_CAST(AT91_REG *)         0x400A8064) // (ADC0) Analog Control Register\r
+#define AT91C_ADC0_IDR  (AT91_CAST(AT91_REG *)         0x400A8028) // (ADC0) ADC Interrupt Disable Register\r
+#define AT91C_ADC0_VER  (AT91_CAST(AT91_REG *)         0x400A80FC) // (ADC0) ADC VERSION REGISTER\r
+#define AT91C_ADC0_CDR7 (AT91_CAST(AT91_REG *)         0x400A804C) // (ADC0) ADC Channel Data Register 7\r
+#define AT91C_ADC0_CHSR (AT91_CAST(AT91_REG *)         0x400A8018) // (ADC0) ADC Channel Status Register\r
+#define AT91C_ADC0_CDR5 (AT91_CAST(AT91_REG *)         0x400A8044) // (ADC0) ADC Channel Data Register 5\r
+#define AT91C_ADC0_IPNAME2 (AT91_CAST(AT91_REG *)      0x400A80F4) // (ADC0) ADC IPNAME2 REGISTER \r
+#define AT91C_ADC0_MR   (AT91_CAST(AT91_REG *)         0x400A8004) // (ADC0) ADC Mode Register\r
+#define AT91C_ADC0_FEATURES (AT91_CAST(AT91_REG *)     0x400A80F8) // (ADC0) ADC FEATURES REGISTER \r
+#define AT91C_ADC0_EMR  (AT91_CAST(AT91_REG *)         0x400A8068) // (ADC0) Extended Mode Register\r
+#define AT91C_ADC0_CDR0 (AT91_CAST(AT91_REG *)         0x400A8030) // (ADC0) ADC Channel Data Register 0\r
+#define AT91C_ADC0_LCDR (AT91_CAST(AT91_REG *)         0x400A8020) // (ADC0) ADC Last Converted Data Register\r
+#define AT91C_ADC0_IMR  (AT91_CAST(AT91_REG *)         0x400A802C) // (ADC0) ADC Interrupt Mask Register\r
+#define AT91C_ADC0_ADDRSIZE (AT91_CAST(AT91_REG *)     0x400A80EC) // (ADC0) ADC ADDRSIZE REGISTER \r
+#define AT91C_ADC0_CDR1 (AT91_CAST(AT91_REG *)         0x400A8034) // (ADC0) ADC Channel Data Register 1\r
+// ========== Register definition for ADC1 peripheral ========== \r
+#define AT91C_ADC1_IPNAME2 (AT91_CAST(AT91_REG *)      0x400AC0F4) // (ADC1) ADC IPNAME2 REGISTER \r
+#define AT91C_ADC1_ADDRSIZE (AT91_CAST(AT91_REG *)     0x400AC0EC) // (ADC1) ADC ADDRSIZE REGISTER \r
+#define AT91C_ADC1_IDR  (AT91_CAST(AT91_REG *)         0x400AC028) // (ADC1) ADC Interrupt Disable Register\r
+#define AT91C_ADC1_CHSR (AT91_CAST(AT91_REG *)         0x400AC018) // (ADC1) ADC Channel Status Register\r
+#define AT91C_ADC1_FEATURES (AT91_CAST(AT91_REG *)     0x400AC0F8) // (ADC1) ADC FEATURES REGISTER \r
+#define AT91C_ADC1_CDR0 (AT91_CAST(AT91_REG *)         0x400AC030) // (ADC1) ADC Channel Data Register 0\r
+#define AT91C_ADC1_LCDR (AT91_CAST(AT91_REG *)         0x400AC020) // (ADC1) ADC Last Converted Data Register\r
+#define AT91C_ADC1_EMR  (AT91_CAST(AT91_REG *)         0x400AC068) // (ADC1) Extended Mode Register\r
+#define AT91C_ADC1_CDR3 (AT91_CAST(AT91_REG *)         0x400AC03C) // (ADC1) ADC Channel Data Register 3\r
+#define AT91C_ADC1_CDR7 (AT91_CAST(AT91_REG *)         0x400AC04C) // (ADC1) ADC Channel Data Register 7\r
+#define AT91C_ADC1_SR   (AT91_CAST(AT91_REG *)         0x400AC01C) // (ADC1) ADC Status Register\r
+#define AT91C_ADC1_ACR  (AT91_CAST(AT91_REG *)         0x400AC064) // (ADC1) Analog Control Register\r
+#define AT91C_ADC1_CDR5 (AT91_CAST(AT91_REG *)         0x400AC044) // (ADC1) ADC Channel Data Register 5\r
+#define AT91C_ADC1_IPNAME1 (AT91_CAST(AT91_REG *)      0x400AC0F0) // (ADC1) ADC IPNAME1 REGISTER \r
+#define AT91C_ADC1_CDR6 (AT91_CAST(AT91_REG *)         0x400AC048) // (ADC1) ADC Channel Data Register 6\r
+#define AT91C_ADC1_MR   (AT91_CAST(AT91_REG *)         0x400AC004) // (ADC1) ADC Mode Register\r
+#define AT91C_ADC1_CDR1 (AT91_CAST(AT91_REG *)         0x400AC034) // (ADC1) ADC Channel Data Register 1\r
+#define AT91C_ADC1_CDR2 (AT91_CAST(AT91_REG *)         0x400AC038) // (ADC1) ADC Channel Data Register 2\r
+#define AT91C_ADC1_CDR4 (AT91_CAST(AT91_REG *)         0x400AC040) // (ADC1) ADC Channel Data Register 4\r
+#define AT91C_ADC1_CHER (AT91_CAST(AT91_REG *)         0x400AC010) // (ADC1) ADC Channel Enable Register\r
+#define AT91C_ADC1_VER  (AT91_CAST(AT91_REG *)         0x400AC0FC) // (ADC1) ADC VERSION REGISTER\r
+#define AT91C_ADC1_CHDR (AT91_CAST(AT91_REG *)         0x400AC014) // (ADC1) ADC Channel Disable Register\r
+#define AT91C_ADC1_CR   (AT91_CAST(AT91_REG *)         0x400AC000) // (ADC1) ADC Control Register\r
+#define AT91C_ADC1_IMR  (AT91_CAST(AT91_REG *)         0x400AC02C) // (ADC1) ADC Interrupt Mask Register\r
+#define AT91C_ADC1_IER  (AT91_CAST(AT91_REG *)         0x400AC024) // (ADC1) ADC Interrupt Enable Register\r
+// ========== Register definition for TC0 peripheral ========== \r
+#define AT91C_TC0_IER   (AT91_CAST(AT91_REG *)         0x40080024) // (TC0) Interrupt Enable Register\r
+#define AT91C_TC0_CV    (AT91_CAST(AT91_REG *)         0x40080010) // (TC0) Counter Value\r
+#define AT91C_TC0_RA    (AT91_CAST(AT91_REG *)         0x40080014) // (TC0) Register A\r
+#define AT91C_TC0_RB    (AT91_CAST(AT91_REG *)         0x40080018) // (TC0) Register B\r
+#define AT91C_TC0_IDR   (AT91_CAST(AT91_REG *)         0x40080028) // (TC0) Interrupt Disable Register\r
+#define AT91C_TC0_SR    (AT91_CAST(AT91_REG *)         0x40080020) // (TC0) Status Register\r
+#define AT91C_TC0_IMR   (AT91_CAST(AT91_REG *)         0x4008002C) // (TC0) Interrupt Mask Register\r
+#define AT91C_TC0_CMR   (AT91_CAST(AT91_REG *)         0x40080004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode)\r
+#define AT91C_TC0_RC    (AT91_CAST(AT91_REG *)         0x4008001C) // (TC0) Register C\r
+#define AT91C_TC0_CCR   (AT91_CAST(AT91_REG *)         0x40080000) // (TC0) Channel Control Register\r
+// ========== Register definition for TC1 peripheral ========== \r
+#define AT91C_TC1_SR    (AT91_CAST(AT91_REG *)         0x40080060) // (TC1) Status Register\r
+#define AT91C_TC1_RA    (AT91_CAST(AT91_REG *)         0x40080054) // (TC1) Register A\r
+#define AT91C_TC1_IER   (AT91_CAST(AT91_REG *)         0x40080064) // (TC1) Interrupt Enable Register\r
+#define AT91C_TC1_RB    (AT91_CAST(AT91_REG *)         0x40080058) // (TC1) Register B\r
+#define AT91C_TC1_IDR   (AT91_CAST(AT91_REG *)         0x40080068) // (TC1) Interrupt Disable Register\r
+#define AT91C_TC1_CCR   (AT91_CAST(AT91_REG *)         0x40080040) // (TC1) Channel Control Register\r
+#define AT91C_TC1_IMR   (AT91_CAST(AT91_REG *)         0x4008006C) // (TC1) Interrupt Mask Register\r
+#define AT91C_TC1_RC    (AT91_CAST(AT91_REG *)         0x4008005C) // (TC1) Register C\r
+#define AT91C_TC1_CMR   (AT91_CAST(AT91_REG *)         0x40080044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode)\r
+#define AT91C_TC1_CV    (AT91_CAST(AT91_REG *)         0x40080050) // (TC1) Counter Value\r
+// ========== Register definition for TC2 peripheral ========== \r
+#define AT91C_TC2_RA    (AT91_CAST(AT91_REG *)         0x40080094) // (TC2) Register A\r
+#define AT91C_TC2_RB    (AT91_CAST(AT91_REG *)         0x40080098) // (TC2) Register B\r
+#define AT91C_TC2_CMR   (AT91_CAST(AT91_REG *)         0x40080084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode)\r
+#define AT91C_TC2_SR    (AT91_CAST(AT91_REG *)         0x400800A0) // (TC2) Status Register\r
+#define AT91C_TC2_CCR   (AT91_CAST(AT91_REG *)         0x40080080) // (TC2) Channel Control Register\r
+#define AT91C_TC2_IMR   (AT91_CAST(AT91_REG *)         0x400800AC) // (TC2) Interrupt Mask Register\r
+#define AT91C_TC2_CV    (AT91_CAST(AT91_REG *)         0x40080090) // (TC2) Counter Value\r
+#define AT91C_TC2_RC    (AT91_CAST(AT91_REG *)         0x4008009C) // (TC2) Register C\r
+#define AT91C_TC2_IER   (AT91_CAST(AT91_REG *)         0x400800A4) // (TC2) Interrupt Enable Register\r
+#define AT91C_TC2_IDR   (AT91_CAST(AT91_REG *)         0x400800A8) // (TC2) Interrupt Disable Register\r
+// ========== Register definition for TCB0 peripheral ========== \r
+#define AT91C_TCB0_BCR  (AT91_CAST(AT91_REG *)         0x400800C0) // (TCB0) TC Block Control Register\r
+#define AT91C_TCB0_IPNAME2 (AT91_CAST(AT91_REG *)      0x400800F4) // (TCB0) TC IPNAME2 REGISTER \r
+#define AT91C_TCB0_IPNAME1 (AT91_CAST(AT91_REG *)      0x400800F0) // (TCB0) TC IPNAME1 REGISTER \r
+#define AT91C_TCB0_ADDRSIZE (AT91_CAST(AT91_REG *)     0x400800EC) // (TCB0) TC ADDRSIZE REGISTER \r
+#define AT91C_TCB0_FEATURES (AT91_CAST(AT91_REG *)     0x400800F8) // (TCB0) TC FEATURES REGISTER \r
+#define AT91C_TCB0_BMR  (AT91_CAST(AT91_REG *)         0x400800C4) // (TCB0) TC Block Mode Register\r
+#define AT91C_TCB0_VER  (AT91_CAST(AT91_REG *)         0x400800FC) // (TCB0)  Version Register\r
+// ========== Register definition for TCB1 peripheral ========== \r
+#define AT91C_TCB1_BCR  (AT91_CAST(AT91_REG *)         0x40080100) // (TCB1) TC Block Control Register\r
+#define AT91C_TCB1_VER  (AT91_CAST(AT91_REG *)         0x4008013C) // (TCB1)  Version Register\r
+#define AT91C_TCB1_FEATURES (AT91_CAST(AT91_REG *)     0x40080138) // (TCB1) TC FEATURES REGISTER \r
+#define AT91C_TCB1_IPNAME2 (AT91_CAST(AT91_REG *)      0x40080134) // (TCB1) TC IPNAME2 REGISTER \r
+#define AT91C_TCB1_BMR  (AT91_CAST(AT91_REG *)         0x40080104) // (TCB1) TC Block Mode Register\r
+#define AT91C_TCB1_ADDRSIZE (AT91_CAST(AT91_REG *)     0x4008012C) // (TCB1) TC ADDRSIZE REGISTER \r
+#define AT91C_TCB1_IPNAME1 (AT91_CAST(AT91_REG *)      0x40080130) // (TCB1) TC IPNAME1 REGISTER \r
+// ========== Register definition for TCB2 peripheral ========== \r
+#define AT91C_TCB2_FEATURES (AT91_CAST(AT91_REG *)     0x40080178) // (TCB2) TC FEATURES REGISTER \r
+#define AT91C_TCB2_VER  (AT91_CAST(AT91_REG *)         0x4008017C) // (TCB2)  Version Register\r
+#define AT91C_TCB2_ADDRSIZE (AT91_CAST(AT91_REG *)     0x4008016C) // (TCB2) TC ADDRSIZE REGISTER \r
+#define AT91C_TCB2_IPNAME1 (AT91_CAST(AT91_REG *)      0x40080170) // (TCB2) TC IPNAME1 REGISTER \r
+#define AT91C_TCB2_IPNAME2 (AT91_CAST(AT91_REG *)      0x40080174) // (TCB2) TC IPNAME2 REGISTER \r
+#define AT91C_TCB2_BMR  (AT91_CAST(AT91_REG *)         0x40080144) // (TCB2) TC Block Mode Register\r
+#define AT91C_TCB2_BCR  (AT91_CAST(AT91_REG *)         0x40080140) // (TCB2) TC Block Control Register\r
+// ========== Register definition for EFC0 peripheral ========== \r
+#define AT91C_EFC0_FCR  (AT91_CAST(AT91_REG *)         0x400E0804) // (EFC0) EFC Flash Command Register\r
+#define AT91C_EFC0_FRR  (AT91_CAST(AT91_REG *)         0x400E080C) // (EFC0) EFC Flash Result Register\r
+#define AT91C_EFC0_FMR  (AT91_CAST(AT91_REG *)         0x400E0800) // (EFC0) EFC Flash Mode Register\r
+#define AT91C_EFC0_FSR  (AT91_CAST(AT91_REG *)         0x400E0808) // (EFC0) EFC Flash Status Register\r
+#define AT91C_EFC0_FVR  (AT91_CAST(AT91_REG *)         0x400E0814) // (EFC0) EFC Flash Version Register\r
+// ========== Register definition for EFC1 peripheral ========== \r
+#define AT91C_EFC1_FMR  (AT91_CAST(AT91_REG *)         0x400E0A00) // (EFC1) EFC Flash Mode Register\r
+#define AT91C_EFC1_FVR  (AT91_CAST(AT91_REG *)         0x400E0A14) // (EFC1) EFC Flash Version Register\r
+#define AT91C_EFC1_FSR  (AT91_CAST(AT91_REG *)         0x400E0A08) // (EFC1) EFC Flash Status Register\r
+#define AT91C_EFC1_FCR  (AT91_CAST(AT91_REG *)         0x400E0A04) // (EFC1) EFC Flash Command Register\r
+#define AT91C_EFC1_FRR  (AT91_CAST(AT91_REG *)         0x400E0A0C) // (EFC1) EFC Flash Result Register\r
+// ========== Register definition for MCI0 peripheral ========== \r
+#define AT91C_MCI0_DMA  (AT91_CAST(AT91_REG *)         0x40000050) // (MCI0) MCI DMA Configuration Register\r
+#define AT91C_MCI0_SDCR (AT91_CAST(AT91_REG *)         0x4000000C) // (MCI0) MCI SD/SDIO Card Register\r
+#define AT91C_MCI0_IPNAME1 (AT91_CAST(AT91_REG *)      0x400000F0) // (MCI0) MCI IPNAME1 REGISTER \r
+#define AT91C_MCI0_CSTOR (AT91_CAST(AT91_REG *)        0x4000001C) // (MCI0) MCI Completion Signal Timeout Register\r
+#define AT91C_MCI0_RDR  (AT91_CAST(AT91_REG *)         0x40000030) // (MCI0) MCI Receive Data Register\r
+#define AT91C_MCI0_CMDR (AT91_CAST(AT91_REG *)         0x40000014) // (MCI0) MCI Command Register\r
+#define AT91C_MCI0_IDR  (AT91_CAST(AT91_REG *)         0x40000048) // (MCI0) MCI Interrupt Disable Register\r
+#define AT91C_MCI0_ADDRSIZE (AT91_CAST(AT91_REG *)     0x400000EC) // (MCI0) MCI ADDRSIZE REGISTER \r
+#define AT91C_MCI0_WPCR (AT91_CAST(AT91_REG *)         0x400000E4) // (MCI0) MCI Write Protection Control Register\r
+#define AT91C_MCI0_RSPR (AT91_CAST(AT91_REG *)         0x40000020) // (MCI0) MCI Response Register\r
+#define AT91C_MCI0_IPNAME2 (AT91_CAST(AT91_REG *)      0x400000F4) // (MCI0) MCI IPNAME2 REGISTER \r
+#define AT91C_MCI0_CR   (AT91_CAST(AT91_REG *)         0x40000000) // (MCI0) MCI Control Register\r
+#define AT91C_MCI0_IMR  (AT91_CAST(AT91_REG *)         0x4000004C) // (MCI0) MCI Interrupt Mask Register\r
+#define AT91C_MCI0_WPSR (AT91_CAST(AT91_REG *)         0x400000E8) // (MCI0) MCI Write Protection Status Register\r
+#define AT91C_MCI0_DTOR (AT91_CAST(AT91_REG *)         0x40000008) // (MCI0) MCI Data Timeout Register\r
+#define AT91C_MCI0_MR   (AT91_CAST(AT91_REG *)         0x40000004) // (MCI0) MCI Mode Register\r
+#define AT91C_MCI0_SR   (AT91_CAST(AT91_REG *)         0x40000040) // (MCI0) MCI Status Register\r
+#define AT91C_MCI0_IER  (AT91_CAST(AT91_REG *)         0x40000044) // (MCI0) MCI Interrupt Enable Register\r
+#define AT91C_MCI0_VER  (AT91_CAST(AT91_REG *)         0x400000FC) // (MCI0) MCI VERSION REGISTER \r
+#define AT91C_MCI0_FEATURES (AT91_CAST(AT91_REG *)     0x400000F8) // (MCI0) MCI FEATURES REGISTER \r
+#define AT91C_MCI0_BLKR (AT91_CAST(AT91_REG *)         0x40000018) // (MCI0) MCI Block Register\r
+#define AT91C_MCI0_ARGR (AT91_CAST(AT91_REG *)         0x40000010) // (MCI0) MCI Argument Register\r
+#define AT91C_MCI0_FIFO (AT91_CAST(AT91_REG *)         0x40000200) // (MCI0) MCI FIFO Aperture Register\r
+#define AT91C_MCI0_TDR  (AT91_CAST(AT91_REG *)         0x40000034) // (MCI0) MCI Transmit Data Register\r
+#define AT91C_MCI0_CFG  (AT91_CAST(AT91_REG *)         0x40000054) // (MCI0) MCI Configuration Register\r
+// ========== Register definition for PDC_TWI0 peripheral ========== \r
+#define AT91C_TWI0_TNCR (AT91_CAST(AT91_REG *)         0x4008411C) // (PDC_TWI0) Transmit Next Counter Register\r
+#define AT91C_TWI0_PTCR (AT91_CAST(AT91_REG *)         0x40084120) // (PDC_TWI0) PDC Transfer Control Register\r
+#define AT91C_TWI0_PTSR (AT91_CAST(AT91_REG *)         0x40084124) // (PDC_TWI0) PDC Transfer Status Register\r
+#define AT91C_TWI0_RCR  (AT91_CAST(AT91_REG *)         0x40084104) // (PDC_TWI0) Receive Counter Register\r
+#define AT91C_TWI0_TNPR (AT91_CAST(AT91_REG *)         0x40084118) // (PDC_TWI0) Transmit Next Pointer Register\r
+#define AT91C_TWI0_RNPR (AT91_CAST(AT91_REG *)         0x40084110) // (PDC_TWI0) Receive Next Pointer Register\r
+#define AT91C_TWI0_RPR  (AT91_CAST(AT91_REG *)         0x40084100) // (PDC_TWI0) Receive Pointer Register\r
+#define AT91C_TWI0_RNCR (AT91_CAST(AT91_REG *)         0x40084114) // (PDC_TWI0) Receive Next Counter Register\r
+#define AT91C_TWI0_TPR  (AT91_CAST(AT91_REG *)         0x40084108) // (PDC_TWI0) Transmit Pointer Register\r
+#define AT91C_TWI0_TCR  (AT91_CAST(AT91_REG *)         0x4008410C) // (PDC_TWI0) Transmit Counter Register\r
+// ========== Register definition for PDC_TWI1 peripheral ========== \r
+#define AT91C_TWI1_TNCR (AT91_CAST(AT91_REG *)         0x4008811C) // (PDC_TWI1) Transmit Next Counter Register\r
+#define AT91C_TWI1_PTCR (AT91_CAST(AT91_REG *)         0x40088120) // (PDC_TWI1) PDC Transfer Control Register\r
+#define AT91C_TWI1_RNCR (AT91_CAST(AT91_REG *)         0x40088114) // (PDC_TWI1) Receive Next Counter Register\r
+#define AT91C_TWI1_RCR  (AT91_CAST(AT91_REG *)         0x40088104) // (PDC_TWI1) Receive Counter Register\r
+#define AT91C_TWI1_RPR  (AT91_CAST(AT91_REG *)         0x40088100) // (PDC_TWI1) Receive Pointer Register\r
+#define AT91C_TWI1_TNPR (AT91_CAST(AT91_REG *)         0x40088118) // (PDC_TWI1) Transmit Next Pointer Register\r
+#define AT91C_TWI1_RNPR (AT91_CAST(AT91_REG *)         0x40088110) // (PDC_TWI1) Receive Next Pointer Register\r
+#define AT91C_TWI1_TCR  (AT91_CAST(AT91_REG *)         0x4008810C) // (PDC_TWI1) Transmit Counter Register\r
+#define AT91C_TWI1_TPR  (AT91_CAST(AT91_REG *)         0x40088108) // (PDC_TWI1) Transmit Pointer Register\r
+#define AT91C_TWI1_PTSR (AT91_CAST(AT91_REG *)         0x40088124) // (PDC_TWI1) PDC Transfer Status Register\r
+// ========== Register definition for TWI0 peripheral ========== \r
+#define AT91C_TWI0_FEATURES (AT91_CAST(AT91_REG *)     0x400840F8) // (TWI0) TWI FEATURES REGISTER \r
+#define AT91C_TWI0_IPNAME1 (AT91_CAST(AT91_REG *)      0x400840F0) // (TWI0) TWI IPNAME1 REGISTER \r
+#define AT91C_TWI0_SMR  (AT91_CAST(AT91_REG *)         0x40084008) // (TWI0) Slave Mode Register\r
+#define AT91C_TWI0_MMR  (AT91_CAST(AT91_REG *)         0x40084004) // (TWI0) Master Mode Register\r
+#define AT91C_TWI0_SR   (AT91_CAST(AT91_REG *)         0x40084020) // (TWI0) Status Register\r
+#define AT91C_TWI0_IPNAME2 (AT91_CAST(AT91_REG *)      0x400840F4) // (TWI0) TWI IPNAME2 REGISTER \r
+#define AT91C_TWI0_CR   (AT91_CAST(AT91_REG *)         0x40084000) // (TWI0) Control Register\r
+#define AT91C_TWI0_IER  (AT91_CAST(AT91_REG *)         0x40084024) // (TWI0) Interrupt Enable Register\r
+#define AT91C_TWI0_RHR  (AT91_CAST(AT91_REG *)         0x40084030) // (TWI0) Receive Holding Register\r
+#define AT91C_TWI0_ADDRSIZE (AT91_CAST(AT91_REG *)     0x400840EC) // (TWI0) TWI ADDRSIZE REGISTER \r
+#define AT91C_TWI0_THR  (AT91_CAST(AT91_REG *)         0x40084034) // (TWI0) Transmit Holding Register\r
+#define AT91C_TWI0_VER  (AT91_CAST(AT91_REG *)         0x400840FC) // (TWI0) Version Register\r
+#define AT91C_TWI0_IADR (AT91_CAST(AT91_REG *)         0x4008400C) // (TWI0) Internal Address Register\r
+#define AT91C_TWI0_IMR  (AT91_CAST(AT91_REG *)         0x4008402C) // (TWI0) Interrupt Mask Register\r
+#define AT91C_TWI0_CWGR (AT91_CAST(AT91_REG *)         0x40084010) // (TWI0) Clock Waveform Generator Register\r
+#define AT91C_TWI0_IDR  (AT91_CAST(AT91_REG *)         0x40084028) // (TWI0) Interrupt Disable Register\r
+// ========== Register definition for TWI1 peripheral ========== \r
+#define AT91C_TWI1_VER  (AT91_CAST(AT91_REG *)         0x400880FC) // (TWI1) Version Register\r
+#define AT91C_TWI1_IDR  (AT91_CAST(AT91_REG *)         0x40088028) // (TWI1) Interrupt Disable Register\r
+#define AT91C_TWI1_IPNAME2 (AT91_CAST(AT91_REG *)      0x400880F4) // (TWI1) TWI IPNAME2 REGISTER \r
+#define AT91C_TWI1_CWGR (AT91_CAST(AT91_REG *)         0x40088010) // (TWI1) Clock Waveform Generator Register\r
+#define AT91C_TWI1_CR   (AT91_CAST(AT91_REG *)         0x40088000) // (TWI1) Control Register\r
+#define AT91C_TWI1_ADDRSIZE (AT91_CAST(AT91_REG *)     0x400880EC) // (TWI1) TWI ADDRSIZE REGISTER \r
+#define AT91C_TWI1_IADR (AT91_CAST(AT91_REG *)         0x4008800C) // (TWI1) Internal Address Register\r
+#define AT91C_TWI1_IER  (AT91_CAST(AT91_REG *)         0x40088024) // (TWI1) Interrupt Enable Register\r
+#define AT91C_TWI1_SMR  (AT91_CAST(AT91_REG *)         0x40088008) // (TWI1) Slave Mode Register\r
+#define AT91C_TWI1_RHR  (AT91_CAST(AT91_REG *)         0x40088030) // (TWI1) Receive Holding Register\r
+#define AT91C_TWI1_FEATURES (AT91_CAST(AT91_REG *)     0x400880F8) // (TWI1) TWI FEATURES REGISTER \r
+#define AT91C_TWI1_IMR  (AT91_CAST(AT91_REG *)         0x4008802C) // (TWI1) Interrupt Mask Register\r
+#define AT91C_TWI1_SR   (AT91_CAST(AT91_REG *)         0x40088020) // (TWI1) Status Register\r
+#define AT91C_TWI1_THR  (AT91_CAST(AT91_REG *)         0x40088034) // (TWI1) Transmit Holding Register\r
+#define AT91C_TWI1_MMR  (AT91_CAST(AT91_REG *)         0x40088004) // (TWI1) Master Mode Register\r
+#define AT91C_TWI1_IPNAME1 (AT91_CAST(AT91_REG *)      0x400880F0) // (TWI1) TWI IPNAME1 REGISTER \r
+// ========== Register definition for PDC_US0 peripheral ========== \r
+#define AT91C_US0_RNCR  (AT91_CAST(AT91_REG *)         0x40090114) // (PDC_US0) Receive Next Counter Register\r
+#define AT91C_US0_TNPR  (AT91_CAST(AT91_REG *)         0x40090118) // (PDC_US0) Transmit Next Pointer Register\r
+#define AT91C_US0_TPR   (AT91_CAST(AT91_REG *)         0x40090108) // (PDC_US0) Transmit Pointer Register\r
+#define AT91C_US0_RCR   (AT91_CAST(AT91_REG *)         0x40090104) // (PDC_US0) Receive Counter Register\r
+#define AT91C_US0_RNPR  (AT91_CAST(AT91_REG *)         0x40090110) // (PDC_US0) Receive Next Pointer Register\r
+#define AT91C_US0_TNCR  (AT91_CAST(AT91_REG *)         0x4009011C) // (PDC_US0) Transmit Next Counter Register\r
+#define AT91C_US0_PTSR  (AT91_CAST(AT91_REG *)         0x40090124) // (PDC_US0) PDC Transfer Status Register\r
+#define AT91C_US0_RPR   (AT91_CAST(AT91_REG *)         0x40090100) // (PDC_US0) Receive Pointer Register\r
+#define AT91C_US0_PTCR  (AT91_CAST(AT91_REG *)         0x40090120) // (PDC_US0) PDC Transfer Control Register\r
+#define AT91C_US0_TCR   (AT91_CAST(AT91_REG *)         0x4009010C) // (PDC_US0) Transmit Counter Register\r
+// ========== Register definition for US0 peripheral ========== \r
+#define AT91C_US0_NER   (AT91_CAST(AT91_REG *)         0x40090044) // (US0) Nb Errors Register\r
+#define AT91C_US0_RHR   (AT91_CAST(AT91_REG *)         0x40090018) // (US0) Receiver Holding Register\r
+#define AT91C_US0_IPNAME1 (AT91_CAST(AT91_REG *)       0x400900F0) // (US0) US IPNAME1 REGISTER \r
+#define AT91C_US0_MR    (AT91_CAST(AT91_REG *)         0x40090004) // (US0) Mode Register\r
+#define AT91C_US0_RTOR  (AT91_CAST(AT91_REG *)         0x40090024) // (US0) Receiver Time-out Register\r
+#define AT91C_US0_IF    (AT91_CAST(AT91_REG *)         0x4009004C) // (US0) IRDA_FILTER Register\r
+#define AT91C_US0_ADDRSIZE (AT91_CAST(AT91_REG *)      0x400900EC) // (US0) US ADDRSIZE REGISTER \r
+#define AT91C_US0_IDR   (AT91_CAST(AT91_REG *)         0x4009000C) // (US0) Interrupt Disable Register\r
+#define AT91C_US0_IMR   (AT91_CAST(AT91_REG *)         0x40090010) // (US0) Interrupt Mask Register\r
+#define AT91C_US0_IER   (AT91_CAST(AT91_REG *)         0x40090008) // (US0) Interrupt Enable Register\r
+#define AT91C_US0_TTGR  (AT91_CAST(AT91_REG *)         0x40090028) // (US0) Transmitter Time-guard Register\r
+#define AT91C_US0_IPNAME2 (AT91_CAST(AT91_REG *)       0x400900F4) // (US0) US IPNAME2 REGISTER \r
+#define AT91C_US0_FIDI  (AT91_CAST(AT91_REG *)         0x40090040) // (US0) FI_DI_Ratio Register\r
+#define AT91C_US0_CR    (AT91_CAST(AT91_REG *)         0x40090000) // (US0) Control Register\r
+#define AT91C_US0_BRGR  (AT91_CAST(AT91_REG *)         0x40090020) // (US0) Baud Rate Generator Register\r
+#define AT91C_US0_MAN   (AT91_CAST(AT91_REG *)         0x40090050) // (US0) Manchester Encoder Decoder Register\r
+#define AT91C_US0_VER   (AT91_CAST(AT91_REG *)         0x400900FC) // (US0) VERSION Register\r
+#define AT91C_US0_FEATURES (AT91_CAST(AT91_REG *)      0x400900F8) // (US0) US FEATURES REGISTER \r
+#define AT91C_US0_CSR   (AT91_CAST(AT91_REG *)         0x40090014) // (US0) Channel Status Register\r
+#define AT91C_US0_THR   (AT91_CAST(AT91_REG *)         0x4009001C) // (US0) Transmitter Holding Register\r
+// ========== Register definition for PDC_US1 peripheral ========== \r
+#define AT91C_US1_TNPR  (AT91_CAST(AT91_REG *)         0x40094118) // (PDC_US1) Transmit Next Pointer Register\r
+#define AT91C_US1_TPR   (AT91_CAST(AT91_REG *)         0x40094108) // (PDC_US1) Transmit Pointer Register\r
+#define AT91C_US1_RNCR  (AT91_CAST(AT91_REG *)         0x40094114) // (PDC_US1) Receive Next Counter Register\r
+#define AT91C_US1_TNCR  (AT91_CAST(AT91_REG *)         0x4009411C) // (PDC_US1) Transmit Next Counter Register\r
+#define AT91C_US1_RNPR  (AT91_CAST(AT91_REG *)         0x40094110) // (PDC_US1) Receive Next Pointer Register\r
+#define AT91C_US1_TCR   (AT91_CAST(AT91_REG *)         0x4009410C) // (PDC_US1) Transmit Counter Register\r
+#define AT91C_US1_PTSR  (AT91_CAST(AT91_REG *)         0x40094124) // (PDC_US1) PDC Transfer Status Register\r
+#define AT91C_US1_RCR   (AT91_CAST(AT91_REG *)         0x40094104) // (PDC_US1) Receive Counter Register\r
+#define AT91C_US1_RPR   (AT91_CAST(AT91_REG *)         0x40094100) // (PDC_US1) Receive Pointer Register\r
+#define AT91C_US1_PTCR  (AT91_CAST(AT91_REG *)         0x40094120) // (PDC_US1) PDC Transfer Control Register\r
+// ========== Register definition for US1 peripheral ========== \r
+#define AT91C_US1_IMR   (AT91_CAST(AT91_REG *)         0x40094010) // (US1) Interrupt Mask Register\r
+#define AT91C_US1_RTOR  (AT91_CAST(AT91_REG *)         0x40094024) // (US1) Receiver Time-out Register\r
+#define AT91C_US1_RHR   (AT91_CAST(AT91_REG *)         0x40094018) // (US1) Receiver Holding Register\r
+#define AT91C_US1_IPNAME1 (AT91_CAST(AT91_REG *)       0x400940F0) // (US1) US IPNAME1 REGISTER \r
+#define AT91C_US1_VER   (AT91_CAST(AT91_REG *)         0x400940FC) // (US1) VERSION Register\r
+#define AT91C_US1_MR    (AT91_CAST(AT91_REG *)         0x40094004) // (US1) Mode Register\r
+#define AT91C_US1_FEATURES (AT91_CAST(AT91_REG *)      0x400940F8) // (US1) US FEATURES REGISTER \r
+#define AT91C_US1_NER   (AT91_CAST(AT91_REG *)         0x40094044) // (US1) Nb Errors Register\r
+#define AT91C_US1_IPNAME2 (AT91_CAST(AT91_REG *)       0x400940F4) // (US1) US IPNAME2 REGISTER \r
+#define AT91C_US1_CR    (AT91_CAST(AT91_REG *)         0x40094000) // (US1) Control Register\r
+#define AT91C_US1_BRGR  (AT91_CAST(AT91_REG *)         0x40094020) // (US1) Baud Rate Generator Register\r
+#define AT91C_US1_IF    (AT91_CAST(AT91_REG *)         0x4009404C) // (US1) IRDA_FILTER Register\r
+#define AT91C_US1_IER   (AT91_CAST(AT91_REG *)         0x40094008) // (US1) Interrupt Enable Register\r
+#define AT91C_US1_TTGR  (AT91_CAST(AT91_REG *)         0x40094028) // (US1) Transmitter Time-guard Register\r
+#define AT91C_US1_FIDI  (AT91_CAST(AT91_REG *)         0x40094040) // (US1) FI_DI_Ratio Register\r
+#define AT91C_US1_MAN   (AT91_CAST(AT91_REG *)         0x40094050) // (US1) Manchester Encoder Decoder Register\r
+#define AT91C_US1_ADDRSIZE (AT91_CAST(AT91_REG *)      0x400940EC) // (US1) US ADDRSIZE REGISTER \r
+#define AT91C_US1_CSR   (AT91_CAST(AT91_REG *)         0x40094014) // (US1) Channel Status Register\r
+#define AT91C_US1_THR   (AT91_CAST(AT91_REG *)         0x4009401C) // (US1) Transmitter Holding Register\r
+#define AT91C_US1_IDR   (AT91_CAST(AT91_REG *)         0x4009400C) // (US1) Interrupt Disable Register\r
+// ========== Register definition for PDC_US2 peripheral ========== \r
+#define AT91C_US2_RPR   (AT91_CAST(AT91_REG *)         0x40098100) // (PDC_US2) Receive Pointer Register\r
+#define AT91C_US2_TPR   (AT91_CAST(AT91_REG *)         0x40098108) // (PDC_US2) Transmit Pointer Register\r
+#define AT91C_US2_TCR   (AT91_CAST(AT91_REG *)         0x4009810C) // (PDC_US2) Transmit Counter Register\r
+#define AT91C_US2_PTSR  (AT91_CAST(AT91_REG *)         0x40098124) // (PDC_US2) PDC Transfer Status Register\r
+#define AT91C_US2_PTCR  (AT91_CAST(AT91_REG *)         0x40098120) // (PDC_US2) PDC Transfer Control Register\r
+#define AT91C_US2_RNPR  (AT91_CAST(AT91_REG *)         0x40098110) // (PDC_US2) Receive Next Pointer Register\r
+#define AT91C_US2_TNCR  (AT91_CAST(AT91_REG *)         0x4009811C) // (PDC_US2) Transmit Next Counter Register\r
+#define AT91C_US2_RNCR  (AT91_CAST(AT91_REG *)         0x40098114) // (PDC_US2) Receive Next Counter Register\r
+#define AT91C_US2_TNPR  (AT91_CAST(AT91_REG *)         0x40098118) // (PDC_US2) Transmit Next Pointer Register\r
+#define AT91C_US2_RCR   (AT91_CAST(AT91_REG *)         0x40098104) // (PDC_US2) Receive Counter Register\r
+// ========== Register definition for US2 peripheral ========== \r
+#define AT91C_US2_MAN   (AT91_CAST(AT91_REG *)         0x40098050) // (US2) Manchester Encoder Decoder Register\r
+#define AT91C_US2_ADDRSIZE (AT91_CAST(AT91_REG *)      0x400980EC) // (US2) US ADDRSIZE REGISTER \r
+#define AT91C_US2_MR    (AT91_CAST(AT91_REG *)         0x40098004) // (US2) Mode Register\r
+#define AT91C_US2_IPNAME1 (AT91_CAST(AT91_REG *)       0x400980F0) // (US2) US IPNAME1 REGISTER \r
+#define AT91C_US2_IF    (AT91_CAST(AT91_REG *)         0x4009804C) // (US2) IRDA_FILTER Register\r
+#define AT91C_US2_BRGR  (AT91_CAST(AT91_REG *)         0x40098020) // (US2) Baud Rate Generator Register\r
+#define AT91C_US2_FIDI  (AT91_CAST(AT91_REG *)         0x40098040) // (US2) FI_DI_Ratio Register\r
+#define AT91C_US2_IER   (AT91_CAST(AT91_REG *)         0x40098008) // (US2) Interrupt Enable Register\r
+#define AT91C_US2_RTOR  (AT91_CAST(AT91_REG *)         0x40098024) // (US2) Receiver Time-out Register\r
+#define AT91C_US2_CR    (AT91_CAST(AT91_REG *)         0x40098000) // (US2) Control Register\r
+#define AT91C_US2_THR   (AT91_CAST(AT91_REG *)         0x4009801C) // (US2) Transmitter Holding Register\r
+#define AT91C_US2_CSR   (AT91_CAST(AT91_REG *)         0x40098014) // (US2) Channel Status Register\r
+#define AT91C_US2_VER   (AT91_CAST(AT91_REG *)         0x400980FC) // (US2) VERSION Register\r
+#define AT91C_US2_FEATURES (AT91_CAST(AT91_REG *)      0x400980F8) // (US2) US FEATURES REGISTER \r
+#define AT91C_US2_IDR   (AT91_CAST(AT91_REG *)         0x4009800C) // (US2) Interrupt Disable Register\r
+#define AT91C_US2_TTGR  (AT91_CAST(AT91_REG *)         0x40098028) // (US2) Transmitter Time-guard Register\r
+#define AT91C_US2_IPNAME2 (AT91_CAST(AT91_REG *)       0x400980F4) // (US2) US IPNAME2 REGISTER \r
+#define AT91C_US2_RHR   (AT91_CAST(AT91_REG *)         0x40098018) // (US2) Receiver Holding Register\r
+#define AT91C_US2_NER   (AT91_CAST(AT91_REG *)         0x40098044) // (US2) Nb Errors Register\r
+#define AT91C_US2_IMR   (AT91_CAST(AT91_REG *)         0x40098010) // (US2) Interrupt Mask Register\r
+// ========== Register definition for PDC_US3 peripheral ========== \r
+#define AT91C_US3_TPR   (AT91_CAST(AT91_REG *)         0x4009C108) // (PDC_US3) Transmit Pointer Register\r
+#define AT91C_US3_PTCR  (AT91_CAST(AT91_REG *)         0x4009C120) // (PDC_US3) PDC Transfer Control Register\r
+#define AT91C_US3_TCR   (AT91_CAST(AT91_REG *)         0x4009C10C) // (PDC_US3) Transmit Counter Register\r
+#define AT91C_US3_RCR   (AT91_CAST(AT91_REG *)         0x4009C104) // (PDC_US3) Receive Counter Register\r
+#define AT91C_US3_RNCR  (AT91_CAST(AT91_REG *)         0x4009C114) // (PDC_US3) Receive Next Counter Register\r
+#define AT91C_US3_RNPR  (AT91_CAST(AT91_REG *)         0x4009C110) // (PDC_US3) Receive Next Pointer Register\r
+#define AT91C_US3_RPR   (AT91_CAST(AT91_REG *)         0x4009C100) // (PDC_US3) Receive Pointer Register\r
+#define AT91C_US3_PTSR  (AT91_CAST(AT91_REG *)         0x4009C124) // (PDC_US3) PDC Transfer Status Register\r
+#define AT91C_US3_TNCR  (AT91_CAST(AT91_REG *)         0x4009C11C) // (PDC_US3) Transmit Next Counter Register\r
+#define AT91C_US3_TNPR  (AT91_CAST(AT91_REG *)         0x4009C118) // (PDC_US3) Transmit Next Pointer Register\r
+// ========== Register definition for US3 peripheral ========== \r
+#define AT91C_US3_MAN   (AT91_CAST(AT91_REG *)         0x4009C050) // (US3) Manchester Encoder Decoder Register\r
+#define AT91C_US3_CSR   (AT91_CAST(AT91_REG *)         0x4009C014) // (US3) Channel Status Register\r
+#define AT91C_US3_BRGR  (AT91_CAST(AT91_REG *)         0x4009C020) // (US3) Baud Rate Generator Register\r
+#define AT91C_US3_IPNAME2 (AT91_CAST(AT91_REG *)       0x4009C0F4) // (US3) US IPNAME2 REGISTER \r
+#define AT91C_US3_RTOR  (AT91_CAST(AT91_REG *)         0x4009C024) // (US3) Receiver Time-out Register\r
+#define AT91C_US3_ADDRSIZE (AT91_CAST(AT91_REG *)      0x4009C0EC) // (US3) US ADDRSIZE REGISTER \r
+#define AT91C_US3_CR    (AT91_CAST(AT91_REG *)         0x4009C000) // (US3) Control Register\r
+#define AT91C_US3_IF    (AT91_CAST(AT91_REG *)         0x4009C04C) // (US3) IRDA_FILTER Register\r
+#define AT91C_US3_FEATURES (AT91_CAST(AT91_REG *)      0x4009C0F8) // (US3) US FEATURES REGISTER \r
+#define AT91C_US3_VER   (AT91_CAST(AT91_REG *)         0x4009C0FC) // (US3) VERSION Register\r
+#define AT91C_US3_RHR   (AT91_CAST(AT91_REG *)         0x4009C018) // (US3) Receiver Holding Register\r
+#define AT91C_US3_TTGR  (AT91_CAST(AT91_REG *)         0x4009C028) // (US3) Transmitter Time-guard Register\r
+#define AT91C_US3_NER   (AT91_CAST(AT91_REG *)         0x4009C044) // (US3) Nb Errors Register\r
+#define AT91C_US3_IMR   (AT91_CAST(AT91_REG *)         0x4009C010) // (US3) Interrupt Mask Register\r
+#define AT91C_US3_THR   (AT91_CAST(AT91_REG *)         0x4009C01C) // (US3) Transmitter Holding Register\r
+#define AT91C_US3_IDR   (AT91_CAST(AT91_REG *)         0x4009C00C) // (US3) Interrupt Disable Register\r
+#define AT91C_US3_MR    (AT91_CAST(AT91_REG *)         0x4009C004) // (US3) Mode Register\r
+#define AT91C_US3_IER   (AT91_CAST(AT91_REG *)         0x4009C008) // (US3) Interrupt Enable Register\r
+#define AT91C_US3_FIDI  (AT91_CAST(AT91_REG *)         0x4009C040) // (US3) FI_DI_Ratio Register\r
+#define AT91C_US3_IPNAME1 (AT91_CAST(AT91_REG *)       0x4009C0F0) // (US3) US IPNAME1 REGISTER \r
+// ========== Register definition for PDC_SSC0 peripheral ========== \r
+#define AT91C_SSC0_RNCR (AT91_CAST(AT91_REG *)         0x40004114) // (PDC_SSC0) Receive Next Counter Register\r
+#define AT91C_SSC0_TPR  (AT91_CAST(AT91_REG *)         0x40004108) // (PDC_SSC0) Transmit Pointer Register\r
+#define AT91C_SSC0_TCR  (AT91_CAST(AT91_REG *)         0x4000410C) // (PDC_SSC0) Transmit Counter Register\r
+#define AT91C_SSC0_PTCR (AT91_CAST(AT91_REG *)         0x40004120) // (PDC_SSC0) PDC Transfer Control Register\r
+#define AT91C_SSC0_TNPR (AT91_CAST(AT91_REG *)         0x40004118) // (PDC_SSC0) Transmit Next Pointer Register\r
+#define AT91C_SSC0_RPR  (AT91_CAST(AT91_REG *)         0x40004100) // (PDC_SSC0) Receive Pointer Register\r
+#define AT91C_SSC0_TNCR (AT91_CAST(AT91_REG *)         0x4000411C) // (PDC_SSC0) Transmit Next Counter Register\r
+#define AT91C_SSC0_RNPR (AT91_CAST(AT91_REG *)         0x40004110) // (PDC_SSC0) Receive Next Pointer Register\r
+#define AT91C_SSC0_RCR  (AT91_CAST(AT91_REG *)         0x40004104) // (PDC_SSC0) Receive Counter Register\r
+#define AT91C_SSC0_PTSR (AT91_CAST(AT91_REG *)         0x40004124) // (PDC_SSC0) PDC Transfer Status Register\r
+// ========== Register definition for SSC0 peripheral ========== \r
+#define AT91C_SSC0_FEATURES (AT91_CAST(AT91_REG *)     0x400040F8) // (SSC0) SSC FEATURES REGISTER \r
+#define AT91C_SSC0_IPNAME1 (AT91_CAST(AT91_REG *)      0x400040F0) // (SSC0) SSC IPNAME1 REGISTER \r
+#define AT91C_SSC0_CR   (AT91_CAST(AT91_REG *)         0x40004000) // (SSC0) Control Register\r
+#define AT91C_SSC0_ADDRSIZE (AT91_CAST(AT91_REG *)     0x400040EC) // (SSC0) SSC ADDRSIZE REGISTER \r
+#define AT91C_SSC0_RHR  (AT91_CAST(AT91_REG *)         0x40004020) // (SSC0) Receive Holding Register\r
+#define AT91C_SSC0_VER  (AT91_CAST(AT91_REG *)         0x400040FC) // (SSC0) Version Register\r
+#define AT91C_SSC0_TSHR (AT91_CAST(AT91_REG *)         0x40004034) // (SSC0) Transmit Sync Holding Register\r
+#define AT91C_SSC0_RFMR (AT91_CAST(AT91_REG *)         0x40004014) // (SSC0) Receive Frame Mode Register\r
+#define AT91C_SSC0_IDR  (AT91_CAST(AT91_REG *)         0x40004048) // (SSC0) Interrupt Disable Register\r
+#define AT91C_SSC0_TFMR (AT91_CAST(AT91_REG *)         0x4000401C) // (SSC0) Transmit Frame Mode Register\r
+#define AT91C_SSC0_RSHR (AT91_CAST(AT91_REG *)         0x40004030) // (SSC0) Receive Sync Holding Register\r
+#define AT91C_SSC0_TCMR (AT91_CAST(AT91_REG *)         0x40004018) // (SSC0) Transmit Clock Mode Register\r
+#define AT91C_SSC0_RCMR (AT91_CAST(AT91_REG *)         0x40004010) // (SSC0) Receive Clock ModeRegister\r
+#define AT91C_SSC0_SR   (AT91_CAST(AT91_REG *)         0x40004040) // (SSC0) Status Register\r
+#define AT91C_SSC0_IPNAME2 (AT91_CAST(AT91_REG *)      0x400040F4) // (SSC0) SSC IPNAME2 REGISTER \r
+#define AT91C_SSC0_THR  (AT91_CAST(AT91_REG *)         0x40004024) // (SSC0) Transmit Holding Register\r
+#define AT91C_SSC0_CMR  (AT91_CAST(AT91_REG *)         0x40004004) // (SSC0) Clock Mode Register\r
+#define AT91C_SSC0_IER  (AT91_CAST(AT91_REG *)         0x40004044) // (SSC0) Interrupt Enable Register\r
+#define AT91C_SSC0_IMR  (AT91_CAST(AT91_REG *)         0x4000404C) // (SSC0) Interrupt Mask Register\r
+// ========== Register definition for PDC_PWMC peripheral ========== \r
+#define AT91C_PWMC_TNCR (AT91_CAST(AT91_REG *)         0x4008C11C) // (PDC_PWMC) Transmit Next Counter Register\r
+#define AT91C_PWMC_TPR  (AT91_CAST(AT91_REG *)         0x4008C108) // (PDC_PWMC) Transmit Pointer Register\r
+#define AT91C_PWMC_RPR  (AT91_CAST(AT91_REG *)         0x4008C100) // (PDC_PWMC) Receive Pointer Register\r
+#define AT91C_PWMC_TCR  (AT91_CAST(AT91_REG *)         0x4008C10C) // (PDC_PWMC) Transmit Counter Register\r
+#define AT91C_PWMC_PTSR (AT91_CAST(AT91_REG *)         0x4008C124) // (PDC_PWMC) PDC Transfer Status Register\r
+#define AT91C_PWMC_RNPR (AT91_CAST(AT91_REG *)         0x4008C110) // (PDC_PWMC) Receive Next Pointer Register\r
+#define AT91C_PWMC_RCR  (AT91_CAST(AT91_REG *)         0x4008C104) // (PDC_PWMC) Receive Counter Register\r
+#define AT91C_PWMC_RNCR (AT91_CAST(AT91_REG *)         0x4008C114) // (PDC_PWMC) Receive Next Counter Register\r
+#define AT91C_PWMC_PTCR (AT91_CAST(AT91_REG *)         0x4008C120) // (PDC_PWMC) PDC Transfer Control Register\r
+#define AT91C_PWMC_TNPR (AT91_CAST(AT91_REG *)         0x4008C118) // (PDC_PWMC) Transmit Next Pointer Register\r
+// ========== Register definition for PWMC_CH0 peripheral ========== \r
+#define AT91C_PWMC_CH0_DTR (AT91_CAST(AT91_REG *)      0x4008C218) // (PWMC_CH0) Channel Dead Time Value Register\r
+#define AT91C_PWMC_CH0_CMR (AT91_CAST(AT91_REG *)      0x4008C200) // (PWMC_CH0) Channel Mode Register\r
+#define AT91C_PWMC_CH0_CCNTR (AT91_CAST(AT91_REG *)    0x4008C214) // (PWMC_CH0) Channel Counter Register\r
+#define AT91C_PWMC_CH0_CPRDR (AT91_CAST(AT91_REG *)    0x4008C20C) // (PWMC_CH0) Channel Period Register\r
+#define AT91C_PWMC_CH0_DTUPDR (AT91_CAST(AT91_REG *)   0x4008C21C) // (PWMC_CH0) Channel Dead Time Update Value Register\r
+#define AT91C_PWMC_CH0_CPRDUPDR (AT91_CAST(AT91_REG *)         0x4008C210) // (PWMC_CH0) Channel Period Update Register\r
+#define AT91C_PWMC_CH0_CDTYUPDR (AT91_CAST(AT91_REG *)         0x4008C208) // (PWMC_CH0) Channel Duty Cycle Update Register\r
+#define AT91C_PWMC_CH0_CDTYR (AT91_CAST(AT91_REG *)    0x4008C204) // (PWMC_CH0) Channel Duty Cycle Register\r
+// ========== Register definition for PWMC_CH1 peripheral ========== \r
+#define AT91C_PWMC_CH1_CCNTR (AT91_CAST(AT91_REG *)    0x4008C234) // (PWMC_CH1) Channel Counter Register\r
+#define AT91C_PWMC_CH1_DTR (AT91_CAST(AT91_REG *)      0x4008C238) // (PWMC_CH1) Channel Dead Time Value Register\r
+#define AT91C_PWMC_CH1_CDTYUPDR (AT91_CAST(AT91_REG *)         0x4008C228) // (PWMC_CH1) Channel Duty Cycle Update Register\r
+#define AT91C_PWMC_CH1_DTUPDR (AT91_CAST(AT91_REG *)   0x4008C23C) // (PWMC_CH1) Channel Dead Time Update Value Register\r
+#define AT91C_PWMC_CH1_CDTYR (AT91_CAST(AT91_REG *)    0x4008C224) // (PWMC_CH1) Channel Duty Cycle Register\r
+#define AT91C_PWMC_CH1_CPRDR (AT91_CAST(AT91_REG *)    0x4008C22C) // (PWMC_CH1) Channel Period Register\r
+#define AT91C_PWMC_CH1_CPRDUPDR (AT91_CAST(AT91_REG *)         0x4008C230) // (PWMC_CH1) Channel Period Update Register\r
+#define AT91C_PWMC_CH1_CMR (AT91_CAST(AT91_REG *)      0x4008C220) // (PWMC_CH1) Channel Mode Register\r
+// ========== Register definition for PWMC_CH2 peripheral ========== \r
+#define AT91C_PWMC_CH2_CDTYR (AT91_CAST(AT91_REG *)    0x4008C244) // (PWMC_CH2) Channel Duty Cycle Register\r
+#define AT91C_PWMC_CH2_DTUPDR (AT91_CAST(AT91_REG *)   0x4008C25C) // (PWMC_CH2) Channel Dead Time Update Value Register\r
+#define AT91C_PWMC_CH2_CCNTR (AT91_CAST(AT91_REG *)    0x4008C254) // (PWMC_CH2) Channel Counter Register\r
+#define AT91C_PWMC_CH2_CMR (AT91_CAST(AT91_REG *)      0x4008C240) // (PWMC_CH2) Channel Mode Register\r
+#define AT91C_PWMC_CH2_CPRDR (AT91_CAST(AT91_REG *)    0x4008C24C) // (PWMC_CH2) Channel Period Register\r
+#define AT91C_PWMC_CH2_CPRDUPDR (AT91_CAST(AT91_REG *)         0x4008C250) // (PWMC_CH2) Channel Period Update Register\r
+#define AT91C_PWMC_CH2_CDTYUPDR (AT91_CAST(AT91_REG *)         0x4008C248) // (PWMC_CH2) Channel Duty Cycle Update Register\r
+#define AT91C_PWMC_CH2_DTR (AT91_CAST(AT91_REG *)      0x4008C258) // (PWMC_CH2) Channel Dead Time Value Register\r
+// ========== Register definition for PWMC_CH3 peripheral ========== \r
+#define AT91C_PWMC_CH3_CPRDUPDR (AT91_CAST(AT91_REG *)         0x4008C270) // (PWMC_CH3) Channel Period Update Register\r
+#define AT91C_PWMC_CH3_DTR (AT91_CAST(AT91_REG *)      0x4008C278) // (PWMC_CH3) Channel Dead Time Value Register\r
+#define AT91C_PWMC_CH3_CDTYR (AT91_CAST(AT91_REG *)    0x4008C264) // (PWMC_CH3) Channel Duty Cycle Register\r
+#define AT91C_PWMC_CH3_DTUPDR (AT91_CAST(AT91_REG *)   0x4008C27C) // (PWMC_CH3) Channel Dead Time Update Value Register\r
+#define AT91C_PWMC_CH3_CDTYUPDR (AT91_CAST(AT91_REG *)         0x4008C268) // (PWMC_CH3) Channel Duty Cycle Update Register\r
+#define AT91C_PWMC_CH3_CCNTR (AT91_CAST(AT91_REG *)    0x4008C274) // (PWMC_CH3) Channel Counter Register\r
+#define AT91C_PWMC_CH3_CMR (AT91_CAST(AT91_REG *)      0x4008C260) // (PWMC_CH3) Channel Mode Register\r
+#define AT91C_PWMC_CH3_CPRDR (AT91_CAST(AT91_REG *)    0x4008C26C) // (PWMC_CH3) Channel Period Register\r
+// ========== Register definition for PWMC peripheral ========== \r
+#define AT91C_PWMC_CMP6MUPD (AT91_CAST(AT91_REG *)     0x4008C19C) // (PWMC) PWM Comparison Mode 6 Update Register\r
+#define AT91C_PWMC_ISR1 (AT91_CAST(AT91_REG *)         0x4008C01C) // (PWMC) PWMC Interrupt Status Register 1\r
+#define AT91C_PWMC_CMP5V (AT91_CAST(AT91_REG *)        0x4008C180) // (PWMC) PWM Comparison Value 5 Register\r
+#define AT91C_PWMC_CMP4MUPD (AT91_CAST(AT91_REG *)     0x4008C17C) // (PWMC) PWM Comparison Mode 4 Update Register\r
+#define AT91C_PWMC_FMR  (AT91_CAST(AT91_REG *)         0x4008C05C) // (PWMC) PWM Fault Mode Register\r
+#define AT91C_PWMC_CMP6V (AT91_CAST(AT91_REG *)        0x4008C190) // (PWMC) PWM Comparison Value 6 Register\r
+#define AT91C_PWMC_EL4MR (AT91_CAST(AT91_REG *)        0x4008C08C) // (PWMC) PWM Event Line 4 Mode Register\r
+#define AT91C_PWMC_UPCR (AT91_CAST(AT91_REG *)         0x4008C028) // (PWMC) PWM Update Control Register\r
+#define AT91C_PWMC_CMP1VUPD (AT91_CAST(AT91_REG *)     0x4008C144) // (PWMC) PWM Comparison Value 1 Update Register\r
+#define AT91C_PWMC_CMP0M (AT91_CAST(AT91_REG *)        0x4008C138) // (PWMC) PWM Comparison Mode 0 Register\r
+#define AT91C_PWMC_CMP5VUPD (AT91_CAST(AT91_REG *)     0x4008C184) // (PWMC) PWM Comparison Value 5 Update Register\r
+#define AT91C_PWMC_FPER3 (AT91_CAST(AT91_REG *)        0x4008C074) // (PWMC) PWM Fault Protection Enable Register 3\r
+#define AT91C_PWMC_OSCUPD (AT91_CAST(AT91_REG *)       0x4008C058) // (PWMC) PWM Output Selection Clear Update Register\r
+#define AT91C_PWMC_FPER1 (AT91_CAST(AT91_REG *)        0x4008C06C) // (PWMC) PWM Fault Protection Enable Register 1\r
+#define AT91C_PWMC_SCUPUPD (AT91_CAST(AT91_REG *)      0x4008C030) // (PWMC) PWM Update Period Update Register\r
+#define AT91C_PWMC_DIS  (AT91_CAST(AT91_REG *)         0x4008C008) // (PWMC) PWMC Disable Register\r
+#define AT91C_PWMC_IER1 (AT91_CAST(AT91_REG *)         0x4008C010) // (PWMC) PWMC Interrupt Enable Register 1\r
+#define AT91C_PWMC_IMR2 (AT91_CAST(AT91_REG *)         0x4008C03C) // (PWMC) PWMC Interrupt Mask Register 2\r
+#define AT91C_PWMC_CMP0V (AT91_CAST(AT91_REG *)        0x4008C130) // (PWMC) PWM Comparison Value 0 Register\r
+#define AT91C_PWMC_SR   (AT91_CAST(AT91_REG *)         0x4008C00C) // (PWMC) PWMC Status Register\r
+#define AT91C_PWMC_CMP4M (AT91_CAST(AT91_REG *)        0x4008C178) // (PWMC) PWM Comparison Mode 4 Register\r
+#define AT91C_PWMC_CMP3M (AT91_CAST(AT91_REG *)        0x4008C168) // (PWMC) PWM Comparison Mode 3 Register\r
+#define AT91C_PWMC_IER2 (AT91_CAST(AT91_REG *)         0x4008C034) // (PWMC) PWMC Interrupt Enable Register 2\r
+#define AT91C_PWMC_CMP3VUPD (AT91_CAST(AT91_REG *)     0x4008C164) // (PWMC) PWM Comparison Value 3 Update Register\r
+#define AT91C_PWMC_CMP2M (AT91_CAST(AT91_REG *)        0x4008C158) // (PWMC) PWM Comparison Mode 2 Register\r
+#define AT91C_PWMC_IDR2 (AT91_CAST(AT91_REG *)         0x4008C038) // (PWMC) PWMC Interrupt Disable Register 2\r
+#define AT91C_PWMC_EL2MR (AT91_CAST(AT91_REG *)        0x4008C084) // (PWMC) PWM Event Line 2 Mode Register\r
+#define AT91C_PWMC_CMP7V (AT91_CAST(AT91_REG *)        0x4008C1A0) // (PWMC) PWM Comparison Value 7 Register\r
+#define AT91C_PWMC_CMP1M (AT91_CAST(AT91_REG *)        0x4008C148) // (PWMC) PWM Comparison Mode 1 Register\r
+#define AT91C_PWMC_CMP0VUPD (AT91_CAST(AT91_REG *)     0x4008C134) // (PWMC) PWM Comparison Value 0 Update Register\r
+#define AT91C_PWMC_WPSR (AT91_CAST(AT91_REG *)         0x4008C0E8) // (PWMC) PWM Write Protection Status Register\r
+#define AT91C_PWMC_CMP6VUPD (AT91_CAST(AT91_REG *)     0x4008C194) // (PWMC) PWM Comparison Value 6 Update Register\r
+#define AT91C_PWMC_CMP1MUPD (AT91_CAST(AT91_REG *)     0x4008C14C) // (PWMC) PWM Comparison Mode 1 Update Register\r
+#define AT91C_PWMC_CMP1V (AT91_CAST(AT91_REG *)        0x4008C140) // (PWMC) PWM Comparison Value 1 Register\r
+#define AT91C_PWMC_FCR  (AT91_CAST(AT91_REG *)         0x4008C064) // (PWMC) PWM Fault Mode Clear Register\r
+#define AT91C_PWMC_VER  (AT91_CAST(AT91_REG *)         0x4008C0FC) // (PWMC) PWMC Version Register\r
+#define AT91C_PWMC_EL1MR (AT91_CAST(AT91_REG *)        0x4008C080) // (PWMC) PWM Event Line 1 Mode Register\r
+#define AT91C_PWMC_EL6MR (AT91_CAST(AT91_REG *)        0x4008C094) // (PWMC) PWM Event Line 6 Mode Register\r
+#define AT91C_PWMC_ISR2 (AT91_CAST(AT91_REG *)         0x4008C040) // (PWMC) PWMC Interrupt Status Register 2\r
+#define AT91C_PWMC_CMP4VUPD (AT91_CAST(AT91_REG *)     0x4008C174) // (PWMC) PWM Comparison Value 4 Update Register\r
+#define AT91C_PWMC_CMP5MUPD (AT91_CAST(AT91_REG *)     0x4008C18C) // (PWMC) PWM Comparison Mode 5 Update Register\r
+#define AT91C_PWMC_OS   (AT91_CAST(AT91_REG *)         0x4008C048) // (PWMC) PWM Output Selection Register\r
+#define AT91C_PWMC_FPV  (AT91_CAST(AT91_REG *)         0x4008C068) // (PWMC) PWM Fault Protection Value Register\r
+#define AT91C_PWMC_FPER2 (AT91_CAST(AT91_REG *)        0x4008C070) // (PWMC) PWM Fault Protection Enable Register 2\r
+#define AT91C_PWMC_EL7MR (AT91_CAST(AT91_REG *)        0x4008C098) // (PWMC) PWM Event Line 7 Mode Register\r
+#define AT91C_PWMC_OSSUPD (AT91_CAST(AT91_REG *)       0x4008C054) // (PWMC) PWM Output Selection Set Update Register\r
+#define AT91C_PWMC_FEATURES (AT91_CAST(AT91_REG *)     0x4008C0F8) // (PWMC) PWMC FEATURES REGISTER \r
+#define AT91C_PWMC_CMP2V (AT91_CAST(AT91_REG *)        0x4008C150) // (PWMC) PWM Comparison Value 2 Register\r
+#define AT91C_PWMC_FSR  (AT91_CAST(AT91_REG *)         0x4008C060) // (PWMC) PWM Fault Mode Status Register\r
+#define AT91C_PWMC_ADDRSIZE (AT91_CAST(AT91_REG *)     0x4008C0EC) // (PWMC) PWMC ADDRSIZE REGISTER \r
+#define AT91C_PWMC_OSC  (AT91_CAST(AT91_REG *)         0x4008C050) // (PWMC) PWM Output Selection Clear Register\r
+#define AT91C_PWMC_SCUP (AT91_CAST(AT91_REG *)         0x4008C02C) // (PWMC) PWM Update Period Register\r
+#define AT91C_PWMC_CMP7MUPD (AT91_CAST(AT91_REG *)     0x4008C1AC) // (PWMC) PWM Comparison Mode 7 Update Register\r
+#define AT91C_PWMC_CMP2VUPD (AT91_CAST(AT91_REG *)     0x4008C154) // (PWMC) PWM Comparison Value 2 Update Register\r
+#define AT91C_PWMC_FPER4 (AT91_CAST(AT91_REG *)        0x4008C078) // (PWMC) PWM Fault Protection Enable Register 4\r
+#define AT91C_PWMC_IMR1 (AT91_CAST(AT91_REG *)         0x4008C018) // (PWMC) PWMC Interrupt Mask Register 1\r
+#define AT91C_PWMC_EL3MR (AT91_CAST(AT91_REG *)        0x4008C088) // (PWMC) PWM Event Line 3 Mode Register\r
+#define AT91C_PWMC_CMP3V (AT91_CAST(AT91_REG *)        0x4008C160) // (PWMC) PWM Comparison Value 3 Register\r
+#define AT91C_PWMC_IPNAME1 (AT91_CAST(AT91_REG *)      0x4008C0F0) // (PWMC) PWMC IPNAME1 REGISTER \r
+#define AT91C_PWMC_OSS  (AT91_CAST(AT91_REG *)         0x4008C04C) // (PWMC) PWM Output Selection Set Register\r
+#define AT91C_PWMC_CMP0MUPD (AT91_CAST(AT91_REG *)     0x4008C13C) // (PWMC) PWM Comparison Mode 0 Update Register\r
+#define AT91C_PWMC_CMP2MUPD (AT91_CAST(AT91_REG *)     0x4008C15C) // (PWMC) PWM Comparison Mode 2 Update Register\r
+#define AT91C_PWMC_CMP4V (AT91_CAST(AT91_REG *)        0x4008C170) // (PWMC) PWM Comparison Value 4 Register\r
+#define AT91C_PWMC_ENA  (AT91_CAST(AT91_REG *)         0x4008C004) // (PWMC) PWMC Enable Register\r
+#define AT91C_PWMC_CMP3MUPD (AT91_CAST(AT91_REG *)     0x4008C16C) // (PWMC) PWM Comparison Mode 3 Update Register\r
+#define AT91C_PWMC_EL0MR (AT91_CAST(AT91_REG *)        0x4008C07C) // (PWMC) PWM Event Line 0 Mode Register\r
+#define AT91C_PWMC_OOV  (AT91_CAST(AT91_REG *)         0x4008C044) // (PWMC) PWM Output Override Value Register\r
+#define AT91C_PWMC_WPCR (AT91_CAST(AT91_REG *)         0x4008C0E4) // (PWMC) PWM Write Protection Enable Register\r
+#define AT91C_PWMC_CMP7M (AT91_CAST(AT91_REG *)        0x4008C1A8) // (PWMC) PWM Comparison Mode 7 Register\r
+#define AT91C_PWMC_CMP6M (AT91_CAST(AT91_REG *)        0x4008C198) // (PWMC) PWM Comparison Mode 6 Register\r
+#define AT91C_PWMC_CMP5M (AT91_CAST(AT91_REG *)        0x4008C188) // (PWMC) PWM Comparison Mode 5 Register\r
+#define AT91C_PWMC_IPNAME2 (AT91_CAST(AT91_REG *)      0x4008C0F4) // (PWMC) PWMC IPNAME2 REGISTER \r
+#define AT91C_PWMC_CMP7VUPD (AT91_CAST(AT91_REG *)     0x4008C1A4) // (PWMC) PWM Comparison Value 7 Update Register\r
+#define AT91C_PWMC_SYNC (AT91_CAST(AT91_REG *)         0x4008C020) // (PWMC) PWM Synchronized Channels Register\r
+#define AT91C_PWMC_MR   (AT91_CAST(AT91_REG *)         0x4008C000) // (PWMC) PWMC Mode Register\r
+#define AT91C_PWMC_IDR1 (AT91_CAST(AT91_REG *)         0x4008C014) // (PWMC) PWMC Interrupt Disable Register 1\r
+#define AT91C_PWMC_EL5MR (AT91_CAST(AT91_REG *)        0x4008C090) // (PWMC) PWM Event Line 5 Mode Register\r
+// ========== Register definition for SPI0 peripheral ========== \r
+#define AT91C_SPI0_ADDRSIZE (AT91_CAST(AT91_REG *)     0x400080EC) // (SPI0) SPI ADDRSIZE REGISTER \r
+#define AT91C_SPI0_RDR  (AT91_CAST(AT91_REG *)         0x40008008) // (SPI0) Receive Data Register\r
+#define AT91C_SPI0_FEATURES (AT91_CAST(AT91_REG *)     0x400080F8) // (SPI0) SPI FEATURES REGISTER \r
+#define AT91C_SPI0_CR   (AT91_CAST(AT91_REG *)         0x40008000) // (SPI0) Control Register\r
+#define AT91C_SPI0_IPNAME1 (AT91_CAST(AT91_REG *)      0x400080F0) // (SPI0) SPI IPNAME1 REGISTER \r
+#define AT91C_SPI0_VER  (AT91_CAST(AT91_REG *)         0x400080FC) // (SPI0) Version Register\r
+#define AT91C_SPI0_IDR  (AT91_CAST(AT91_REG *)         0x40008018) // (SPI0) Interrupt Disable Register\r
+#define AT91C_SPI0_TDR  (AT91_CAST(AT91_REG *)         0x4000800C) // (SPI0) Transmit Data Register\r
+#define AT91C_SPI0_MR   (AT91_CAST(AT91_REG *)         0x40008004) // (SPI0) Mode Register\r
+#define AT91C_SPI0_IER  (AT91_CAST(AT91_REG *)         0x40008014) // (SPI0) Interrupt Enable Register\r
+#define AT91C_SPI0_IMR  (AT91_CAST(AT91_REG *)         0x4000801C) // (SPI0) Interrupt Mask Register\r
+#define AT91C_SPI0_IPNAME2 (AT91_CAST(AT91_REG *)      0x400080F4) // (SPI0) SPI IPNAME2 REGISTER \r
+#define AT91C_SPI0_CSR  (AT91_CAST(AT91_REG *)         0x40008030) // (SPI0) Chip Select Register\r
+#define AT91C_SPI0_SR   (AT91_CAST(AT91_REG *)         0x40008010) // (SPI0) Status Register\r
+// ========== Register definition for UDPHS_EPTFIFO peripheral ========== \r
+#define AT91C_UDPHS_EPTFIFO_READEPT6 (AT91_CAST(AT91_REG *)    0x201E0000) // (UDPHS_EPTFIFO) FIFO Endpoint Data Register 6\r
+#define AT91C_UDPHS_EPTFIFO_READEPT2 (AT91_CAST(AT91_REG *)    0x201A0000) // (UDPHS_EPTFIFO) FIFO Endpoint Data Register 2\r
+#define AT91C_UDPHS_EPTFIFO_READEPT1 (AT91_CAST(AT91_REG *)    0x20190000) // (UDPHS_EPTFIFO) FIFO Endpoint Data Register 1\r
+#define AT91C_UDPHS_EPTFIFO_READEPT0 (AT91_CAST(AT91_REG *)    0x20180000) // (UDPHS_EPTFIFO) FIFO Endpoint Data Register 0\r
+#define AT91C_UDPHS_EPTFIFO_READEPT5 (AT91_CAST(AT91_REG *)    0x201D0000) // (UDPHS_EPTFIFO) FIFO Endpoint Data Register 5\r
+#define AT91C_UDPHS_EPTFIFO_READEPT4 (AT91_CAST(AT91_REG *)    0x201C0000) // (UDPHS_EPTFIFO) FIFO Endpoint Data Register 4\r
+#define AT91C_UDPHS_EPTFIFO_READEPT3 (AT91_CAST(AT91_REG *)    0x201B0000) // (UDPHS_EPTFIFO) FIFO Endpoint Data Register 3\r
+// ========== Register definition for UDPHS_EPT_0 peripheral ========== \r
+#define AT91C_UDPHS_EPT_0_EPTCTL (AT91_CAST(AT91_REG *)        0x400A410C) // (UDPHS_EPT_0) UDPHS Endpoint Control Register\r
+#define AT91C_UDPHS_EPT_0_EPTSTA (AT91_CAST(AT91_REG *)        0x400A411C) // (UDPHS_EPT_0) UDPHS Endpoint Status Register\r
+#define AT91C_UDPHS_EPT_0_EPTCLRSTA (AT91_CAST(AT91_REG *)     0x400A4118) // (UDPHS_EPT_0) UDPHS Endpoint Clear Status Register\r
+#define AT91C_UDPHS_EPT_0_EPTCTLDIS (AT91_CAST(AT91_REG *)     0x400A4108) // (UDPHS_EPT_0) UDPHS Endpoint Control Disable Register\r
+#define AT91C_UDPHS_EPT_0_EPTCFG (AT91_CAST(AT91_REG *)        0x400A4100) // (UDPHS_EPT_0) UDPHS Endpoint Config Register\r
+#define AT91C_UDPHS_EPT_0_EPTSETSTA (AT91_CAST(AT91_REG *)     0x400A4114) // (UDPHS_EPT_0) UDPHS Endpoint Set Status Register\r
+#define AT91C_UDPHS_EPT_0_EPTCTLENB (AT91_CAST(AT91_REG *)     0x400A4104) // (UDPHS_EPT_0) UDPHS Endpoint Control Enable Register\r
+// ========== Register definition for UDPHS_EPT_1 peripheral ========== \r
+#define AT91C_UDPHS_EPT_1_EPTSTA (AT91_CAST(AT91_REG *)        0x400A413C) // (UDPHS_EPT_1) UDPHS Endpoint Status Register\r
+#define AT91C_UDPHS_EPT_1_EPTSETSTA (AT91_CAST(AT91_REG *)     0x400A4134) // (UDPHS_EPT_1) UDPHS Endpoint Set Status Register\r
+#define AT91C_UDPHS_EPT_1_EPTCTL (AT91_CAST(AT91_REG *)        0x400A412C) // (UDPHS_EPT_1) UDPHS Endpoint Control Register\r
+#define AT91C_UDPHS_EPT_1_EPTCFG (AT91_CAST(AT91_REG *)        0x400A4120) // (UDPHS_EPT_1) UDPHS Endpoint Config Register\r
+#define AT91C_UDPHS_EPT_1_EPTCTLDIS (AT91_CAST(AT91_REG *)     0x400A4128) // (UDPHS_EPT_1) UDPHS Endpoint Control Disable Register\r
+#define AT91C_UDPHS_EPT_1_EPTCLRSTA (AT91_CAST(AT91_REG *)     0x400A4138) // (UDPHS_EPT_1) UDPHS Endpoint Clear Status Register\r
+#define AT91C_UDPHS_EPT_1_EPTCTLENB (AT91_CAST(AT91_REG *)     0x400A4124) // (UDPHS_EPT_1) UDPHS Endpoint Control Enable Register\r
+// ========== Register definition for UDPHS_EPT_2 peripheral ========== \r
+#define AT91C_UDPHS_EPT_2_EPTCTLENB (AT91_CAST(AT91_REG *)     0x400A4144) // (UDPHS_EPT_2) UDPHS Endpoint Control Enable Register\r
+#define AT91C_UDPHS_EPT_2_EPTCLRSTA (AT91_CAST(AT91_REG *)     0x400A4158) // (UDPHS_EPT_2) UDPHS Endpoint Clear Status Register\r
+#define AT91C_UDPHS_EPT_2_EPTCFG (AT91_CAST(AT91_REG *)        0x400A4140) // (UDPHS_EPT_2) UDPHS Endpoint Config Register\r
+#define AT91C_UDPHS_EPT_2_EPTCTL (AT91_CAST(AT91_REG *)        0x400A414C) // (UDPHS_EPT_2) UDPHS Endpoint Control Register\r
+#define AT91C_UDPHS_EPT_2_EPTSETSTA (AT91_CAST(AT91_REG *)     0x400A4154) // (UDPHS_EPT_2) UDPHS Endpoint Set Status Register\r
+#define AT91C_UDPHS_EPT_2_EPTSTA (AT91_CAST(AT91_REG *)        0x400A415C) // (UDPHS_EPT_2) UDPHS Endpoint Status Register\r
+#define AT91C_UDPHS_EPT_2_EPTCTLDIS (AT91_CAST(AT91_REG *)     0x400A4148) // (UDPHS_EPT_2) UDPHS Endpoint Control Disable Register\r
+// ========== Register definition for UDPHS_EPT_3 peripheral ========== \r
+#define AT91C_UDPHS_EPT_3_EPTCTLDIS (AT91_CAST(AT91_REG *)     0x400A4168) // (UDPHS_EPT_3) UDPHS Endpoint Control Disable Register\r
+#define AT91C_UDPHS_EPT_3_EPTCTLENB (AT91_CAST(AT91_REG *)     0x400A4164) // (UDPHS_EPT_3) UDPHS Endpoint Control Enable Register\r
+#define AT91C_UDPHS_EPT_3_EPTSETSTA (AT91_CAST(AT91_REG *)     0x400A4174) // (UDPHS_EPT_3) UDPHS Endpoint Set Status Register\r
+#define AT91C_UDPHS_EPT_3_EPTCLRSTA (AT91_CAST(AT91_REG *)     0x400A4178) // (UDPHS_EPT_3) UDPHS Endpoint Clear Status Register\r
+#define AT91C_UDPHS_EPT_3_EPTCFG (AT91_CAST(AT91_REG *)        0x400A4160) // (UDPHS_EPT_3) UDPHS Endpoint Config Register\r
+#define AT91C_UDPHS_EPT_3_EPTSTA (AT91_CAST(AT91_REG *)        0x400A417C) // (UDPHS_EPT_3) UDPHS Endpoint Status Register\r
+#define AT91C_UDPHS_EPT_3_EPTCTL (AT91_CAST(AT91_REG *)        0x400A416C) // (UDPHS_EPT_3) UDPHS Endpoint Control Register\r
+// ========== Register definition for UDPHS_EPT_4 peripheral ========== \r
+#define AT91C_UDPHS_EPT_4_EPTSETSTA (AT91_CAST(AT91_REG *)     0x400A4194) // (UDPHS_EPT_4) UDPHS Endpoint Set Status Register\r
+#define AT91C_UDPHS_EPT_4_EPTCTLDIS (AT91_CAST(AT91_REG *)     0x400A4188) // (UDPHS_EPT_4) UDPHS Endpoint Control Disable Register\r
+#define AT91C_UDPHS_EPT_4_EPTCTL (AT91_CAST(AT91_REG *)        0x400A418C) // (UDPHS_EPT_4) UDPHS Endpoint Control Register\r
+#define AT91C_UDPHS_EPT_4_EPTCFG (AT91_CAST(AT91_REG *)        0x400A4180) // (UDPHS_EPT_4) UDPHS Endpoint Config Register\r
+#define AT91C_UDPHS_EPT_4_EPTCTLENB (AT91_CAST(AT91_REG *)     0x400A4184) // (UDPHS_EPT_4) UDPHS Endpoint Control Enable Register\r
+#define AT91C_UDPHS_EPT_4_EPTSTA (AT91_CAST(AT91_REG *)        0x400A419C) // (UDPHS_EPT_4) UDPHS Endpoint Status Register\r
+#define AT91C_UDPHS_EPT_4_EPTCLRSTA (AT91_CAST(AT91_REG *)     0x400A4198) // (UDPHS_EPT_4) UDPHS Endpoint Clear Status Register\r
+// ========== Register definition for UDPHS_EPT_5 peripheral ========== \r
+#define AT91C_UDPHS_EPT_5_EPTCFG (AT91_CAST(AT91_REG *)        0x400A41A0) // (UDPHS_EPT_5) UDPHS Endpoint Config Register\r
+#define AT91C_UDPHS_EPT_5_EPTCTL (AT91_CAST(AT91_REG *)        0x400A41AC) // (UDPHS_EPT_5) UDPHS Endpoint Control Register\r
+#define AT91C_UDPHS_EPT_5_EPTCTLENB (AT91_CAST(AT91_REG *)     0x400A41A4) // (UDPHS_EPT_5) UDPHS Endpoint Control Enable Register\r
+#define AT91C_UDPHS_EPT_5_EPTSTA (AT91_CAST(AT91_REG *)        0x400A41BC) // (UDPHS_EPT_5) UDPHS Endpoint Status Register\r
+#define AT91C_UDPHS_EPT_5_EPTSETSTA (AT91_CAST(AT91_REG *)     0x400A41B4) // (UDPHS_EPT_5) UDPHS Endpoint Set Status Register\r
+#define AT91C_UDPHS_EPT_5_EPTCTLDIS (AT91_CAST(AT91_REG *)     0x400A41A8) // (UDPHS_EPT_5) UDPHS Endpoint Control Disable Register\r
+#define AT91C_UDPHS_EPT_5_EPTCLRSTA (AT91_CAST(AT91_REG *)     0x400A41B8) // (UDPHS_EPT_5) UDPHS Endpoint Clear Status Register\r
+// ========== Register definition for UDPHS_EPT_6 peripheral ========== \r
+#define AT91C_UDPHS_EPT_6_EPTCLRSTA (AT91_CAST(AT91_REG *)     0x400A41D8) // (UDPHS_EPT_6) UDPHS Endpoint Clear Status Register\r
+#define AT91C_UDPHS_EPT_6_EPTCTL (AT91_CAST(AT91_REG *)        0x400A41CC) // (UDPHS_EPT_6) UDPHS Endpoint Control Register\r
+#define AT91C_UDPHS_EPT_6_EPTCFG (AT91_CAST(AT91_REG *)        0x400A41C0) // (UDPHS_EPT_6) UDPHS Endpoint Config Register\r
+#define AT91C_UDPHS_EPT_6_EPTCTLDIS (AT91_CAST(AT91_REG *)     0x400A41C8) // (UDPHS_EPT_6) UDPHS Endpoint Control Disable Register\r
+#define AT91C_UDPHS_EPT_6_EPTSTA (AT91_CAST(AT91_REG *)        0x400A41DC) // (UDPHS_EPT_6) UDPHS Endpoint Status Register\r
+#define AT91C_UDPHS_EPT_6_EPTCTLENB (AT91_CAST(AT91_REG *)     0x400A41C4) // (UDPHS_EPT_6) UDPHS Endpoint Control Enable Register\r
+#define AT91C_UDPHS_EPT_6_EPTSETSTA (AT91_CAST(AT91_REG *)     0x400A41D4) // (UDPHS_EPT_6) UDPHS Endpoint Set Status Register\r
+// ========== Register definition for UDPHS_DMA_1 peripheral ========== \r
+#define AT91C_UDPHS_DMA_1_DMASTATUS (AT91_CAST(AT91_REG *)     0x400A431C) // (UDPHS_DMA_1) UDPHS DMA Channel Status Register\r
+#define AT91C_UDPHS_DMA_1_DMACONTROL (AT91_CAST(AT91_REG *)    0x400A4318) // (UDPHS_DMA_1) UDPHS DMA Channel Control Register\r
+#define AT91C_UDPHS_DMA_1_DMANXTDSC (AT91_CAST(AT91_REG *)     0x400A4310) // (UDPHS_DMA_1) UDPHS DMA Channel Next Descriptor Address\r
+#define AT91C_UDPHS_DMA_1_DMAADDRESS (AT91_CAST(AT91_REG *)    0x400A4314) // (UDPHS_DMA_1) UDPHS DMA Channel Address Register\r
+// ========== Register definition for UDPHS_DMA_2 peripheral ========== \r
+#define AT91C_UDPHS_DMA_2_DMASTATUS (AT91_CAST(AT91_REG *)     0x400A432C) // (UDPHS_DMA_2) UDPHS DMA Channel Status Register\r
+#define AT91C_UDPHS_DMA_2_DMANXTDSC (AT91_CAST(AT91_REG *)     0x400A4320) // (UDPHS_DMA_2) UDPHS DMA Channel Next Descriptor Address\r
+#define AT91C_UDPHS_DMA_2_DMACONTROL (AT91_CAST(AT91_REG *)    0x400A4328) // (UDPHS_DMA_2) UDPHS DMA Channel Control Register\r
+#define AT91C_UDPHS_DMA_2_DMAADDRESS (AT91_CAST(AT91_REG *)    0x400A4324) // (UDPHS_DMA_2) UDPHS DMA Channel Address Register\r
+// ========== Register definition for UDPHS_DMA_3 peripheral ========== \r
+#define AT91C_UDPHS_DMA_3_DMACONTROL (AT91_CAST(AT91_REG *)    0x400A4338) // (UDPHS_DMA_3) UDPHS DMA Channel Control Register\r
+#define AT91C_UDPHS_DMA_3_DMANXTDSC (AT91_CAST(AT91_REG *)     0x400A4330) // (UDPHS_DMA_3) UDPHS DMA Channel Next Descriptor Address\r
+#define AT91C_UDPHS_DMA_3_DMASTATUS (AT91_CAST(AT91_REG *)     0x400A433C) // (UDPHS_DMA_3) UDPHS DMA Channel Status Register\r
+#define AT91C_UDPHS_DMA_3_DMAADDRESS (AT91_CAST(AT91_REG *)    0x400A4334) // (UDPHS_DMA_3) UDPHS DMA Channel Address Register\r
+// ========== Register definition for UDPHS_DMA_4 peripheral ========== \r
+#define AT91C_UDPHS_DMA_4_DMAADDRESS (AT91_CAST(AT91_REG *)    0x400A4344) // (UDPHS_DMA_4) UDPHS DMA Channel Address Register\r
+#define AT91C_UDPHS_DMA_4_DMANXTDSC (AT91_CAST(AT91_REG *)     0x400A4340) // (UDPHS_DMA_4) UDPHS DMA Channel Next Descriptor Address\r
+#define AT91C_UDPHS_DMA_4_DMASTATUS (AT91_CAST(AT91_REG *)     0x400A434C) // (UDPHS_DMA_4) UDPHS DMA Channel Status Register\r
+#define AT91C_UDPHS_DMA_4_DMACONTROL (AT91_CAST(AT91_REG *)    0x400A4348) // (UDPHS_DMA_4) UDPHS DMA Channel Control Register\r
+// ========== Register definition for UDPHS_DMA_5 peripheral ========== \r
+#define AT91C_UDPHS_DMA_5_DMACONTROL (AT91_CAST(AT91_REG *)    0x400A4358) // (UDPHS_DMA_5) UDPHS DMA Channel Control Register\r
+#define AT91C_UDPHS_DMA_5_DMAADDRESS (AT91_CAST(AT91_REG *)    0x400A4354) // (UDPHS_DMA_5) UDPHS DMA Channel Address Register\r
+#define AT91C_UDPHS_DMA_5_DMANXTDSC (AT91_CAST(AT91_REG *)     0x400A4350) // (UDPHS_DMA_5) UDPHS DMA Channel Next Descriptor Address\r
+#define AT91C_UDPHS_DMA_5_DMASTATUS (AT91_CAST(AT91_REG *)     0x400A435C) // (UDPHS_DMA_5) UDPHS DMA Channel Status Register\r
+// ========== Register definition for UDPHS_DMA_6 peripheral ========== \r
+#define AT91C_UDPHS_DMA_6_DMASTATUS (AT91_CAST(AT91_REG *)     0x400A436C) // (UDPHS_DMA_6) UDPHS DMA Channel Status Register\r
+#define AT91C_UDPHS_DMA_6_DMACONTROL (AT91_CAST(AT91_REG *)    0x400A4368) // (UDPHS_DMA_6) UDPHS DMA Channel Control Register\r
+#define AT91C_UDPHS_DMA_6_DMANXTDSC (AT91_CAST(AT91_REG *)     0x400A4360) // (UDPHS_DMA_6) UDPHS DMA Channel Next Descriptor Address\r
+#define AT91C_UDPHS_DMA_6_DMAADDRESS (AT91_CAST(AT91_REG *)    0x400A4364) // (UDPHS_DMA_6) UDPHS DMA Channel Address Register\r
+// ========== Register definition for UDPHS peripheral ========== \r
+#define AT91C_UDPHS_EPTRST (AT91_CAST(AT91_REG *)      0x400A401C) // (UDPHS) UDPHS Endpoints Reset Register\r
+#define AT91C_UDPHS_IEN (AT91_CAST(AT91_REG *)         0x400A4010) // (UDPHS) UDPHS Interrupt Enable Register\r
+#define AT91C_UDPHS_TSTCNTB (AT91_CAST(AT91_REG *)     0x400A40D8) // (UDPHS) UDPHS Test B Counter Register\r
+#define AT91C_UDPHS_RIPNAME2 (AT91_CAST(AT91_REG *)    0x400A40F4) // (UDPHS) UDPHS Name2 Register\r
+#define AT91C_UDPHS_RIPPADDRSIZE (AT91_CAST(AT91_REG *)        0x400A40EC) // (UDPHS) UDPHS PADDRSIZE Register\r
+#define AT91C_UDPHS_TSTMODREG (AT91_CAST(AT91_REG *)   0x400A40DC) // (UDPHS) UDPHS Test Mode Register\r
+#define AT91C_UDPHS_TST (AT91_CAST(AT91_REG *)         0x400A40E0) // (UDPHS) UDPHS Test Register\r
+#define AT91C_UDPHS_TSTSOFCNT (AT91_CAST(AT91_REG *)   0x400A40D0) // (UDPHS) UDPHS Test SOF Counter Register\r
+#define AT91C_UDPHS_FNUM (AT91_CAST(AT91_REG *)        0x400A4004) // (UDPHS) UDPHS Frame Number Register\r
+#define AT91C_UDPHS_TSTCNTA (AT91_CAST(AT91_REG *)     0x400A40D4) // (UDPHS) UDPHS Test A Counter Register\r
+#define AT91C_UDPHS_INTSTA (AT91_CAST(AT91_REG *)      0x400A4014) // (UDPHS) UDPHS Interrupt Status Register\r
+#define AT91C_UDPHS_IPFEATURES (AT91_CAST(AT91_REG *)  0x400A40F8) // (UDPHS) UDPHS Features Register\r
+#define AT91C_UDPHS_CLRINT (AT91_CAST(AT91_REG *)      0x400A4018) // (UDPHS) UDPHS Clear Interrupt Register\r
+#define AT91C_UDPHS_RIPNAME1 (AT91_CAST(AT91_REG *)    0x400A40F0) // (UDPHS) UDPHS Name1 Register\r
+#define AT91C_UDPHS_CTRL (AT91_CAST(AT91_REG *)        0x400A4000) // (UDPHS) UDPHS Control Register\r
+#define AT91C_UDPHS_IPVERSION (AT91_CAST(AT91_REG *)   0x400A40FC) // (UDPHS) UDPHS Version Register\r
+// ========== Register definition for HDMA_CH_0 peripheral ========== \r
+#define AT91C_HDMA_CH_0_CADDR (AT91_CAST(AT91_REG *)   0x400B0060) // (HDMA_CH_0) HDMA Reserved\r
+#define AT91C_HDMA_CH_0_DADDR (AT91_CAST(AT91_REG *)   0x400B0040) // (HDMA_CH_0) HDMA Channel Destination Address Register\r
+#define AT91C_HDMA_CH_0_BDSCR (AT91_CAST(AT91_REG *)   0x400B005C) // (HDMA_CH_0) HDMA Reserved\r
+#define AT91C_HDMA_CH_0_CFG (AT91_CAST(AT91_REG *)     0x400B0050) // (HDMA_CH_0) HDMA Channel Configuration Register\r
+#define AT91C_HDMA_CH_0_CTRLB (AT91_CAST(AT91_REG *)   0x400B004C) // (HDMA_CH_0) HDMA Channel Control B Register\r
+#define AT91C_HDMA_CH_0_CTRLA (AT91_CAST(AT91_REG *)   0x400B0048) // (HDMA_CH_0) HDMA Channel Control A Register\r
+#define AT91C_HDMA_CH_0_DSCR (AT91_CAST(AT91_REG *)    0x400B0044) // (HDMA_CH_0) HDMA Channel Descriptor Address Register\r
+#define AT91C_HDMA_CH_0_SADDR (AT91_CAST(AT91_REG *)   0x400B003C) // (HDMA_CH_0) HDMA Channel Source Address Register\r
+#define AT91C_HDMA_CH_0_DPIP (AT91_CAST(AT91_REG *)    0x400B0058) // (HDMA_CH_0) HDMA Channel Destination Picture in Picture Configuration Register\r
+#define AT91C_HDMA_CH_0_SPIP (AT91_CAST(AT91_REG *)    0x400B0054) // (HDMA_CH_0) HDMA Channel Source Picture in Picture Configuration Register\r
+// ========== Register definition for HDMA_CH_1 peripheral ========== \r
+#define AT91C_HDMA_CH_1_DSCR (AT91_CAST(AT91_REG *)    0x400B006C) // (HDMA_CH_1) HDMA Channel Descriptor Address Register\r
+#define AT91C_HDMA_CH_1_BDSCR (AT91_CAST(AT91_REG *)   0x400B0084) // (HDMA_CH_1) HDMA Reserved\r
+#define AT91C_HDMA_CH_1_CTRLB (AT91_CAST(AT91_REG *)   0x400B0074) // (HDMA_CH_1) HDMA Channel Control B Register\r
+#define AT91C_HDMA_CH_1_SPIP (AT91_CAST(AT91_REG *)    0x400B007C) // (HDMA_CH_1) HDMA Channel Source Picture in Picture Configuration Register\r
+#define AT91C_HDMA_CH_1_SADDR (AT91_CAST(AT91_REG *)   0x400B0064) // (HDMA_CH_1) HDMA Channel Source Address Register\r
+#define AT91C_HDMA_CH_1_DPIP (AT91_CAST(AT91_REG *)    0x400B0080) // (HDMA_CH_1) HDMA Channel Destination Picture in Picture Configuration Register\r
+#define AT91C_HDMA_CH_1_CFG (AT91_CAST(AT91_REG *)     0x400B0078) // (HDMA_CH_1) HDMA Channel Configuration Register\r
+#define AT91C_HDMA_CH_1_DADDR (AT91_CAST(AT91_REG *)   0x400B0068) // (HDMA_CH_1) HDMA Channel Destination Address Register\r
+#define AT91C_HDMA_CH_1_CADDR (AT91_CAST(AT91_REG *)   0x400B0088) // (HDMA_CH_1) HDMA Reserved\r
+#define AT91C_HDMA_CH_1_CTRLA (AT91_CAST(AT91_REG *)   0x400B0070) // (HDMA_CH_1) HDMA Channel Control A Register\r
+// ========== Register definition for HDMA_CH_2 peripheral ========== \r
+#define AT91C_HDMA_CH_2_BDSCR (AT91_CAST(AT91_REG *)   0x400B00AC) // (HDMA_CH_2) HDMA Reserved\r
+#define AT91C_HDMA_CH_2_CTRLB (AT91_CAST(AT91_REG *)   0x400B009C) // (HDMA_CH_2) HDMA Channel Control B Register\r
+#define AT91C_HDMA_CH_2_CADDR (AT91_CAST(AT91_REG *)   0x400B00B0) // (HDMA_CH_2) HDMA Reserved\r
+#define AT91C_HDMA_CH_2_CFG (AT91_CAST(AT91_REG *)     0x400B00A0) // (HDMA_CH_2) HDMA Channel Configuration Register\r
+#define AT91C_HDMA_CH_2_CTRLA (AT91_CAST(AT91_REG *)   0x400B0098) // (HDMA_CH_2) HDMA Channel Control A Register\r
+#define AT91C_HDMA_CH_2_SADDR (AT91_CAST(AT91_REG *)   0x400B008C) // (HDMA_CH_2) HDMA Channel Source Address Register\r
+#define AT91C_HDMA_CH_2_DPIP (AT91_CAST(AT91_REG *)    0x400B00A8) // (HDMA_CH_2) HDMA Channel Destination Picture in Picture Configuration Register\r
+#define AT91C_HDMA_CH_2_DADDR (AT91_CAST(AT91_REG *)   0x400B0090) // (HDMA_CH_2) HDMA Channel Destination Address Register\r
+#define AT91C_HDMA_CH_2_SPIP (AT91_CAST(AT91_REG *)    0x400B00A4) // (HDMA_CH_2) HDMA Channel Source Picture in Picture Configuration Register\r
+#define AT91C_HDMA_CH_2_DSCR (AT91_CAST(AT91_REG *)    0x400B0094) // (HDMA_CH_2) HDMA Channel Descriptor Address Register\r
+// ========== Register definition for HDMA_CH_3 peripheral ========== \r
+#define AT91C_HDMA_CH_3_DSCR (AT91_CAST(AT91_REG *)    0x400B00BC) // (HDMA_CH_3) HDMA Channel Descriptor Address Register\r
+#define AT91C_HDMA_CH_3_SADDR (AT91_CAST(AT91_REG *)   0x400B00B4) // (HDMA_CH_3) HDMA Channel Source Address Register\r
+#define AT91C_HDMA_CH_3_BDSCR (AT91_CAST(AT91_REG *)   0x400B00D4) // (HDMA_CH_3) HDMA Reserved\r
+#define AT91C_HDMA_CH_3_CTRLA (AT91_CAST(AT91_REG *)   0x400B00C0) // (HDMA_CH_3) HDMA Channel Control A Register\r
+#define AT91C_HDMA_CH_3_DPIP (AT91_CAST(AT91_REG *)    0x400B00D0) // (HDMA_CH_3) HDMA Channel Destination Picture in Picture Configuration Register\r
+#define AT91C_HDMA_CH_3_CTRLB (AT91_CAST(AT91_REG *)   0x400B00C4) // (HDMA_CH_3) HDMA Channel Control B Register\r
+#define AT91C_HDMA_CH_3_SPIP (AT91_CAST(AT91_REG *)    0x400B00CC) // (HDMA_CH_3) HDMA Channel Source Picture in Picture Configuration Register\r
+#define AT91C_HDMA_CH_3_CFG (AT91_CAST(AT91_REG *)     0x400B00C8) // (HDMA_CH_3) HDMA Channel Configuration Register\r
+#define AT91C_HDMA_CH_3_CADDR (AT91_CAST(AT91_REG *)   0x400B00D8) // (HDMA_CH_3) HDMA Reserved\r
+#define AT91C_HDMA_CH_3_DADDR (AT91_CAST(AT91_REG *)   0x400B00B8) // (HDMA_CH_3) HDMA Channel Destination Address Register\r
+// ========== Register definition for HDMA peripheral ========== \r
+#define AT91C_HDMA_SYNC (AT91_CAST(AT91_REG *)         0x400B0014) // (HDMA) HDMA Request Synchronization Register\r
+#define AT91C_HDMA_VER  (AT91_CAST(AT91_REG *)         0x400B01FC) // (HDMA) HDMA VERSION REGISTER \r
+#define AT91C_HDMA_RSVD0 (AT91_CAST(AT91_REG *)        0x400B0034) // (HDMA) HDMA Reserved\r
+#define AT91C_HDMA_CHSR (AT91_CAST(AT91_REG *)         0x400B0030) // (HDMA) HDMA Channel Handler Status Register\r
+#define AT91C_HDMA_IPNAME2 (AT91_CAST(AT91_REG *)      0x400B01F4) // (HDMA) HDMA IPNAME2 REGISTER \r
+#define AT91C_HDMA_EBCIMR (AT91_CAST(AT91_REG *)       0x400B0020) // (HDMA) HDMA Error, Chained Buffer transfer completed and Buffer transfer completed Mask Register\r
+#define AT91C_HDMA_CHDR (AT91_CAST(AT91_REG *)         0x400B002C) // (HDMA) HDMA Channel Handler Disable Register\r
+#define AT91C_HDMA_EN   (AT91_CAST(AT91_REG *)         0x400B0004) // (HDMA) HDMA Controller Enable Register\r
+#define AT91C_HDMA_GCFG (AT91_CAST(AT91_REG *)         0x400B0000) // (HDMA) HDMA Global Configuration Register\r
+#define AT91C_HDMA_IPNAME1 (AT91_CAST(AT91_REG *)      0x400B01F0) // (HDMA) HDMA IPNAME1 REGISTER \r
+#define AT91C_HDMA_LAST (AT91_CAST(AT91_REG *)         0x400B0010) // (HDMA) HDMA Software Last Transfer Flag Register\r
+#define AT91C_HDMA_FEATURES (AT91_CAST(AT91_REG *)     0x400B01F8) // (HDMA) HDMA FEATURES REGISTER \r
+#define AT91C_HDMA_CREQ (AT91_CAST(AT91_REG *)         0x400B000C) // (HDMA) HDMA Software Chunk Transfer Request Register\r
+#define AT91C_HDMA_EBCIER (AT91_CAST(AT91_REG *)       0x400B0018) // (HDMA) HDMA Error, Chained Buffer transfer completed and Buffer transfer completed Interrupt Enable register\r
+#define AT91C_HDMA_CHER (AT91_CAST(AT91_REG *)         0x400B0028) // (HDMA) HDMA Channel Handler Enable Register\r
+#define AT91C_HDMA_ADDRSIZE (AT91_CAST(AT91_REG *)     0x400B01EC) // (HDMA) HDMA ADDRSIZE REGISTER \r
+#define AT91C_HDMA_EBCISR (AT91_CAST(AT91_REG *)       0x400B0024) // (HDMA) HDMA Error, Chained Buffer transfer completed and Buffer transfer completed Status Register\r
+#define AT91C_HDMA_SREQ (AT91_CAST(AT91_REG *)         0x400B0008) // (HDMA) HDMA Software Single Request Register\r
+#define AT91C_HDMA_EBCIDR (AT91_CAST(AT91_REG *)       0x400B001C) // (HDMA) HDMA Error, Chained Buffer transfer completed and Buffer transfer completed Interrupt Disable register\r
+#define AT91C_HDMA_RSVD1 (AT91_CAST(AT91_REG *)        0x400B0038) // (HDMA) HDMA Reserved\r
+\r
+// *****************************************************************************\r
+//               PIO DEFINITIONS FOR AT91SAM3U4\r
+// *****************************************************************************\r
+#define AT91C_PIO_PA0        (1 <<  0) // Pin Controlled by PA0\r
+#define AT91C_PA0_TIOB0    (AT91C_PIO_PA0) //  \r
+#define AT91C_PA0_SPI0_NPCS1 (AT91C_PIO_PA0) //  \r
+#define AT91C_PIO_PA1        (1 <<  1) // Pin Controlled by PA1\r
+#define AT91C_PA1_TIOA0    (AT91C_PIO_PA1) //  \r
+#define AT91C_PA1_SPI0_NPCS2 (AT91C_PIO_PA1) //  \r
+#define AT91C_PIO_PA10       (1 << 10) // Pin Controlled by PA10\r
+#define AT91C_PA10_TWCK0    (AT91C_PIO_PA10) //  \r
+#define AT91C_PA10_PWML3    (AT91C_PIO_PA10) //  \r
+#define AT91C_PIO_PA11       (1 << 11) // Pin Controlled by PA11\r
+#define AT91C_PA11_DRXD     (AT91C_PIO_PA11) //  \r
+#define AT91C_PIO_PA12       (1 << 12) // Pin Controlled by PA12\r
+#define AT91C_PA12_DTXD     (AT91C_PIO_PA12) //  \r
+#define AT91C_PIO_PA13       (1 << 13) // Pin Controlled by PA13\r
+#define AT91C_PA13_SPI0_MISO (AT91C_PIO_PA13) //  \r
+#define AT91C_PIO_PA14       (1 << 14) // Pin Controlled by PA14\r
+#define AT91C_PA14_SPI0_MOSI (AT91C_PIO_PA14) //  \r
+#define AT91C_PIO_PA15       (1 << 15) // Pin Controlled by PA15\r
+#define AT91C_PA15_SPI0_SPCK (AT91C_PIO_PA15) //  \r
+#define AT91C_PA15_PWMH2    (AT91C_PIO_PA15) //  \r
+#define AT91C_PIO_PA16       (1 << 16) // Pin Controlled by PA16\r
+#define AT91C_PA16_SPI0_NPCS0 (AT91C_PIO_PA16) //  \r
+#define AT91C_PA16_NCS1     (AT91C_PIO_PA16) //  \r
+#define AT91C_PIO_PA17       (1 << 17) // Pin Controlled by PA17\r
+#define AT91C_PA17_SCK0     (AT91C_PIO_PA17) //  \r
+#define AT91C_PA17_ADTRG0   (AT91C_PIO_PA17) //  \r
+#define AT91C_PIO_PA18       (1 << 18) // Pin Controlled by PA18\r
+#define AT91C_PA18_TXD0     (AT91C_PIO_PA18) //  \r
+#define AT91C_PIO_PA19       (1 << 19) // Pin Controlled by PA19\r
+#define AT91C_PA19_RXD0     (AT91C_PIO_PA19) //  \r
+#define AT91C_PA19_SPI0_NPCS3 (AT91C_PIO_PA19) //  \r
+#define AT91C_PIO_PA2        (1 <<  2) // Pin Controlled by PA2\r
+#define AT91C_PA2_TCLK0    (AT91C_PIO_PA2) //  \r
+#define AT91C_PA2_ADTRG1   (AT91C_PIO_PA2) //  \r
+#define AT91C_PIO_PA20       (1 << 20) // Pin Controlled by PA20\r
+#define AT91C_PA20_TXD1     (AT91C_PIO_PA20) //  \r
+#define AT91C_PA20_PWMH3    (AT91C_PIO_PA20) //  \r
+#define AT91C_PIO_PA21       (1 << 21) // Pin Controlled by PA21\r
+#define AT91C_PA21_RXD1     (AT91C_PIO_PA21) //  \r
+#define AT91C_PA21_PCK0     (AT91C_PIO_PA21) //  \r
+#define AT91C_PIO_PA22       (1 << 22) // Pin Controlled by PA22\r
+#define AT91C_PA22_TXD2     (AT91C_PIO_PA22) //  \r
+#define AT91C_PA22_RTS1     (AT91C_PIO_PA22) //  \r
+#define AT91C_PIO_PA23       (1 << 23) // Pin Controlled by PA23\r
+#define AT91C_PA23_RXD2     (AT91C_PIO_PA23) //  \r
+#define AT91C_PA23_CTS1     (AT91C_PIO_PA23) //  \r
+#define AT91C_PIO_PA24       (1 << 24) // Pin Controlled by PA24\r
+#define AT91C_PA24_TWD1     (AT91C_PIO_PA24) //  \r
+#define AT91C_PA24_SCK1     (AT91C_PIO_PA24) //  \r
+#define AT91C_PIO_PA25       (1 << 25) // Pin Controlled by PA25\r
+#define AT91C_PA25_TWCK1    (AT91C_PIO_PA25) //  \r
+#define AT91C_PA25_SCK2     (AT91C_PIO_PA25) //  \r
+#define AT91C_PIO_PA26       (1 << 26) // Pin Controlled by PA26\r
+#define AT91C_PA26_TD0      (AT91C_PIO_PA26) //  \r
+#define AT91C_PA26_TCLK2    (AT91C_PIO_PA26) //  \r
+#define AT91C_PIO_PA27       (1 << 27) // Pin Controlled by PA27\r
+#define AT91C_PA27_RD0      (AT91C_PIO_PA27) //  \r
+#define AT91C_PA27_PCK0     (AT91C_PIO_PA27) //  \r
+#define AT91C_PIO_PA28       (1 << 28) // Pin Controlled by PA28\r
+#define AT91C_PA28_TK0      (AT91C_PIO_PA28) //  \r
+#define AT91C_PA28_PWMH0    (AT91C_PIO_PA28) //  \r
+#define AT91C_PIO_PA29       (1 << 29) // Pin Controlled by PA29\r
+#define AT91C_PA29_RK0      (AT91C_PIO_PA29) //  \r
+#define AT91C_PA29_PWMH1    (AT91C_PIO_PA29) //  \r
+#define AT91C_PIO_PA3        (1 <<  3) // Pin Controlled by PA3\r
+#define AT91C_PA3_MCI0_CK  (AT91C_PIO_PA3) //  \r
+#define AT91C_PA3_PCK1     (AT91C_PIO_PA3) //  \r
+#define AT91C_PIO_PA30       (1 << 30) // Pin Controlled by PA30\r
+#define AT91C_PA30_TF0      (AT91C_PIO_PA30) //  \r
+#define AT91C_PA30_TIOA2    (AT91C_PIO_PA30) //  \r
+#define AT91C_PIO_PA31       (1 << 31) // Pin Controlled by PA31\r
+#define AT91C_PA31_RF0      (AT91C_PIO_PA31) //  \r
+#define AT91C_PA31_TIOB2    (AT91C_PIO_PA31) //  \r
+#define AT91C_PIO_PA4        (1 <<  4) // Pin Controlled by PA4\r
+#define AT91C_PA4_MCI0_CDA (AT91C_PIO_PA4) //  \r
+#define AT91C_PA4_PWMH0    (AT91C_PIO_PA4) //  \r
+#define AT91C_PIO_PA5        (1 <<  5) // Pin Controlled by PA5\r
+#define AT91C_PA5_MCI0_DA0 (AT91C_PIO_PA5) //  \r
+#define AT91C_PA5_PWMH1    (AT91C_PIO_PA5) //  \r
+#define AT91C_PIO_PA6        (1 <<  6) // Pin Controlled by PA6\r
+#define AT91C_PA6_MCI0_DA1 (AT91C_PIO_PA6) //  \r
+#define AT91C_PA6_PWMH2    (AT91C_PIO_PA6) //  \r
+#define AT91C_PIO_PA7        (1 <<  7) // Pin Controlled by PA7\r
+#define AT91C_PA7_MCI0_DA2 (AT91C_PIO_PA7) //  \r
+#define AT91C_PA7_PWML0    (AT91C_PIO_PA7) //  \r
+#define AT91C_PIO_PA8        (1 <<  8) // Pin Controlled by PA8\r
+#define AT91C_PA8_MCI0_DA3 (AT91C_PIO_PA8) //  \r
+#define AT91C_PA8_PWML1    (AT91C_PIO_PA8) //  \r
+#define AT91C_PIO_PA9        (1 <<  9) // Pin Controlled by PA9\r
+#define AT91C_PA9_TWD0     (AT91C_PIO_PA9) //  \r
+#define AT91C_PA9_PWML2    (AT91C_PIO_PA9) //  \r
+#define AT91C_PIO_PB0        (1 <<  0) // Pin Controlled by PB0\r
+#define AT91C_PB0_PWMH0    (AT91C_PIO_PB0) //  \r
+#define AT91C_PB0_A2       (AT91C_PIO_PB0) //  \r
+#define AT91C_PIO_PB1        (1 <<  1) // Pin Controlled by PB1\r
+#define AT91C_PB1_PWMH1    (AT91C_PIO_PB1) //  \r
+#define AT91C_PB1_A3       (AT91C_PIO_PB1) //  \r
+#define AT91C_PIO_PB10       (1 << 10) // Pin Controlled by PB10\r
+#define AT91C_PB10_D1       (AT91C_PIO_PB10) //  \r
+#define AT91C_PB10_DSR0     (AT91C_PIO_PB10) //  \r
+#define AT91C_PIO_PB11       (1 << 11) // Pin Controlled by PB11\r
+#define AT91C_PB11_D2       (AT91C_PIO_PB11) //  \r
+#define AT91C_PB11_DCD0     (AT91C_PIO_PB11) //  \r
+#define AT91C_PIO_PB12       (1 << 12) // Pin Controlled by PB12\r
+#define AT91C_PB12_D3       (AT91C_PIO_PB12) //  \r
+#define AT91C_PB12_RI0      (AT91C_PIO_PB12) //  \r
+#define AT91C_PIO_PB13       (1 << 13) // Pin Controlled by PB13\r
+#define AT91C_PB13_D4       (AT91C_PIO_PB13) //  \r
+#define AT91C_PB13_PWMH0    (AT91C_PIO_PB13) //  \r
+#define AT91C_PIO_PB14       (1 << 14) // Pin Controlled by PB14\r
+#define AT91C_PB14_D5       (AT91C_PIO_PB14) //  \r
+#define AT91C_PB14_PWMH1    (AT91C_PIO_PB14) //  \r
+#define AT91C_PIO_PB15       (1 << 15) // Pin Controlled by PB15\r
+#define AT91C_PB15_D6       (AT91C_PIO_PB15) //  \r
+#define AT91C_PB15_PWMH2    (AT91C_PIO_PB15) //  \r
+#define AT91C_PIO_PB16       (1 << 16) // Pin Controlled by PB16\r
+#define AT91C_PB16_D7       (AT91C_PIO_PB16) //  \r
+#define AT91C_PB16_PWMH3    (AT91C_PIO_PB16) //  \r
+#define AT91C_PIO_PB17       (1 << 17) // Pin Controlled by PB17\r
+#define AT91C_PB17_NANDOE   (AT91C_PIO_PB17) //  \r
+#define AT91C_PB17_PWML0    (AT91C_PIO_PB17) //  \r
+#define AT91C_PIO_PB18       (1 << 18) // Pin Controlled by PB18\r
+#define AT91C_PB18_NANDWE   (AT91C_PIO_PB18) //  \r
+#define AT91C_PB18_PWML1    (AT91C_PIO_PB18) //  \r
+#define AT91C_PIO_PB19       (1 << 19) // Pin Controlled by PB19\r
+#define AT91C_PB19_NRD      (AT91C_PIO_PB19) //  \r
+#define AT91C_PB19_PWML2    (AT91C_PIO_PB19) //  \r
+#define AT91C_PIO_PB2        (1 <<  2) // Pin Controlled by PB2\r
+#define AT91C_PB2_PWMH2    (AT91C_PIO_PB2) //  \r
+#define AT91C_PB2_A4       (AT91C_PIO_PB2) //  \r
+#define AT91C_PIO_PB20       (1 << 20) // Pin Controlled by PB20\r
+#define AT91C_PB20_NCS0     (AT91C_PIO_PB20) //  \r
+#define AT91C_PB20_PWML3    (AT91C_PIO_PB20) //  \r
+#define AT91C_PIO_PB21       (1 << 21) // Pin Controlled by PB21\r
+#define AT91C_PB21_A21_NANDALE (AT91C_PIO_PB21) //  \r
+#define AT91C_PB21_RTS2     (AT91C_PIO_PB21) //  \r
+#define AT91C_PIO_PB22       (1 << 22) // Pin Controlled by PB22\r
+#define AT91C_PB22_A22_NANDCLE (AT91C_PIO_PB22) //  \r
+#define AT91C_PB22_CTS2     (AT91C_PIO_PB22) //  \r
+#define AT91C_PIO_PB23       (1 << 23) // Pin Controlled by PB23\r
+#define AT91C_PB23_NWR0_NWE (AT91C_PIO_PB23) //  \r
+#define AT91C_PB23_PCK2     (AT91C_PIO_PB23) //  \r
+#define AT91C_PIO_PB24       (1 << 24) // Pin Controlled by PB24\r
+#define AT91C_PB24_NANDRDY  (AT91C_PIO_PB24) //  \r
+#define AT91C_PB24_PCK1     (AT91C_PIO_PB24) //  \r
+#define AT91C_PIO_PB25       (1 << 25) // Pin Controlled by PB25\r
+#define AT91C_PB25_D8       (AT91C_PIO_PB25) //  \r
+#define AT91C_PB25_PWML0    (AT91C_PIO_PB25) //  \r
+#define AT91C_PIO_PB26       (1 << 26) // Pin Controlled by PB26\r
+#define AT91C_PB26_D9       (AT91C_PIO_PB26) //  \r
+#define AT91C_PB26_PWML1    (AT91C_PIO_PB26) //  \r
+#define AT91C_PIO_PB27       (1 << 27) // Pin Controlled by PB27\r
+#define AT91C_PB27_D10      (AT91C_PIO_PB27) //  \r
+#define AT91C_PB27_PWML2    (AT91C_PIO_PB27) //  \r
+#define AT91C_PIO_PB28       (1 << 28) // Pin Controlled by PB28\r
+#define AT91C_PB28_D11      (AT91C_PIO_PB28) //  \r
+#define AT91C_PB28_PWML3    (AT91C_PIO_PB28) //  \r
+#define AT91C_PIO_PB29       (1 << 29) // Pin Controlled by PB29\r
+#define AT91C_PB29_D12      (AT91C_PIO_PB29) //  \r
+#define AT91C_PIO_PB3        (1 <<  3) // Pin Controlled by PB3\r
+#define AT91C_PB3_PWMH3    (AT91C_PIO_PB3) //  \r
+#define AT91C_PB3_A5       (AT91C_PIO_PB3) //  \r
+#define AT91C_PIO_PB30       (1 << 30) // Pin Controlled by PB30\r
+#define AT91C_PB30_D13      (AT91C_PIO_PB30) //  \r
+#define AT91C_PIO_PB31       (1 << 31) // Pin Controlled by PB31\r
+#define AT91C_PB31_D14      (AT91C_PIO_PB31) //  \r
+#define AT91C_PIO_PB4        (1 <<  4) // Pin Controlled by PB4\r
+#define AT91C_PB4_TCLK1    (AT91C_PIO_PB4) //  \r
+#define AT91C_PB4_A6       (AT91C_PIO_PB4) //  \r
+#define AT91C_PIO_PB5        (1 <<  5) // Pin Controlled by PB5\r
+#define AT91C_PB5_TIOA1    (AT91C_PIO_PB5) //  \r
+#define AT91C_PB5_A7       (AT91C_PIO_PB5) //  \r
+#define AT91C_PIO_PB6        (1 <<  6) // Pin Controlled by PB6\r
+#define AT91C_PB6_TIOB1    (AT91C_PIO_PB6) //  \r
+#define AT91C_PB6_D15      (AT91C_PIO_PB6) //  \r
+#define AT91C_PIO_PB7        (1 <<  7) // Pin Controlled by PB7\r
+#define AT91C_PB7_RTS0     (AT91C_PIO_PB7) //  \r
+#define AT91C_PB7_A0_NBS0  (AT91C_PIO_PB7) //  \r
+#define AT91C_PIO_PB8        (1 <<  8) // Pin Controlled by PB8\r
+#define AT91C_PB8_CTS0     (AT91C_PIO_PB8) //  \r
+#define AT91C_PB8_A1       (AT91C_PIO_PB8) //  \r
+#define AT91C_PIO_PB9        (1 <<  9) // Pin Controlled by PB9\r
+#define AT91C_PB9_D0       (AT91C_PIO_PB9) //  \r
+#define AT91C_PB9_DTR0     (AT91C_PIO_PB9) //  \r
+#define AT91C_PIO_PC0        (1 <<  0) // Pin Controlled by PC0\r
+#define AT91C_PC0_A2       (AT91C_PIO_PC0) //  \r
+#define AT91C_PIO_PC1        (1 <<  1) // Pin Controlled by PC1\r
+#define AT91C_PC1_A3       (AT91C_PIO_PC1) //  \r
+#define AT91C_PIO_PC10       (1 << 10) // Pin Controlled by PC10\r
+#define AT91C_PC10_A12      (AT91C_PIO_PC10) //  \r
+#define AT91C_PC10_CTS3     (AT91C_PIO_PC10) //  \r
+#define AT91C_PIO_PC11       (1 << 11) // Pin Controlled by PC11\r
+#define AT91C_PC11_A13      (AT91C_PIO_PC11) //  \r
+#define AT91C_PC11_RTS3     (AT91C_PIO_PC11) //  \r
+#define AT91C_PIO_PC12       (1 << 12) // Pin Controlled by PC12\r
+#define AT91C_PC12_NCS1     (AT91C_PIO_PC12) //  \r
+#define AT91C_PC12_TXD3     (AT91C_PIO_PC12) //  \r
+#define AT91C_PIO_PC13       (1 << 13) // Pin Controlled by PC13\r
+#define AT91C_PC13_A2       (AT91C_PIO_PC13) //  \r
+#define AT91C_PC13_RXD3     (AT91C_PIO_PC13) //  \r
+#define AT91C_PIO_PC14       (1 << 14) // Pin Controlled by PC14\r
+#define AT91C_PC14_A3       (AT91C_PIO_PC14) //  \r
+#define AT91C_PC14_SPI0_NPCS2 (AT91C_PIO_PC14) //  \r
+#define AT91C_PIO_PC15       (1 << 15) // Pin Controlled by PC15\r
+#define AT91C_PC15_NWR1_NBS1 (AT91C_PIO_PC15) //  \r
+#define AT91C_PIO_PC16       (1 << 16) // Pin Controlled by PC16\r
+#define AT91C_PC16_NCS2     (AT91C_PIO_PC16) //  \r
+#define AT91C_PC16_PWML3    (AT91C_PIO_PC16) //  \r
+#define AT91C_PIO_PC17       (1 << 17) // Pin Controlled by PC17\r
+#define AT91C_PC17_NCS3     (AT91C_PIO_PC17) //  \r
+#define AT91C_PC17_A24      (AT91C_PIO_PC17) //  \r
+#define AT91C_PIO_PC18       (1 << 18) // Pin Controlled by PC18\r
+#define AT91C_PC18_NWAIT    (AT91C_PIO_PC18) //  \r
+#define AT91C_PIO_PC19       (1 << 19) // Pin Controlled by PC19\r
+#define AT91C_PC19_SCK3     (AT91C_PIO_PC19) //  \r
+#define AT91C_PC19_NPCS1    (AT91C_PIO_PC19) //  \r
+#define AT91C_PIO_PC2        (1 <<  2) // Pin Controlled by PC2\r
+#define AT91C_PC2_A4       (AT91C_PIO_PC2) //  \r
+#define AT91C_PIO_PC20       (1 << 20) // Pin Controlled by PC20\r
+#define AT91C_PC20_A14      (AT91C_PIO_PC20) //  \r
+#define AT91C_PIO_PC21       (1 << 21) // Pin Controlled by PC21\r
+#define AT91C_PC21_A15      (AT91C_PIO_PC21) //  \r
+#define AT91C_PIO_PC22       (1 << 22) // Pin Controlled by PC22\r
+#define AT91C_PC22_A16      (AT91C_PIO_PC22) //  \r
+#define AT91C_PIO_PC23       (1 << 23) // Pin Controlled by PC23\r
+#define AT91C_PC23_A17      (AT91C_PIO_PC23) //  \r
+#define AT91C_PIO_PC24       (1 << 24) // Pin Controlled by PC24\r
+#define AT91C_PC24_A18      (AT91C_PIO_PC24) //  \r
+#define AT91C_PC24_PWMH0    (AT91C_PIO_PC24) //  \r
+#define AT91C_PIO_PC25       (1 << 25) // Pin Controlled by PC25\r
+#define AT91C_PC25_A19      (AT91C_PIO_PC25) //  \r
+#define AT91C_PC25_PWMH1    (AT91C_PIO_PC25) //  \r
+#define AT91C_PIO_PC26       (1 << 26) // Pin Controlled by PC26\r
+#define AT91C_PC26_A20      (AT91C_PIO_PC26) //  \r
+#define AT91C_PC26_PWMH2    (AT91C_PIO_PC26) //  \r
+#define AT91C_PIO_PC27       (1 << 27) // Pin Controlled by PC27\r
+#define AT91C_PC27_A23      (AT91C_PIO_PC27) //  \r
+#define AT91C_PC27_PWMH3    (AT91C_PIO_PC27) //  \r
+#define AT91C_PIO_PC28       (1 << 28) // Pin Controlled by PC28\r
+#define AT91C_PC28_A24      (AT91C_PIO_PC28) //  \r
+#define AT91C_PC28_MCI0_DA4 (AT91C_PIO_PC28) //  \r
+#define AT91C_PIO_PC29       (1 << 29) // Pin Controlled by PC29\r
+#define AT91C_PC29_PWML0    (AT91C_PIO_PC29) //  \r
+#define AT91C_PC29_MCI0_DA5 (AT91C_PIO_PC29) //  \r
+#define AT91C_PIO_PC3        (1 <<  3) // Pin Controlled by PC3\r
+#define AT91C_PC3_A5       (AT91C_PIO_PC3) //  \r
+#define AT91C_PC3_SPI0_NPCS1 (AT91C_PIO_PC3) //  \r
+#define AT91C_PIO_PC30       (1 << 30) // Pin Controlled by PC30\r
+#define AT91C_PC30_PWML1    (AT91C_PIO_PC30) //  \r
+#define AT91C_PC30_MCI0_DA6 (AT91C_PIO_PC30) //  \r
+#define AT91C_PIO_PC31       (1 << 31) // Pin Controlled by PC31\r
+#define AT91C_PC31_PWML2    (AT91C_PIO_PC31) //  \r
+#define AT91C_PC31_MCI0_DA7 (AT91C_PIO_PC31) //  \r
+#define AT91C_PIO_PC4        (1 <<  4) // Pin Controlled by PC4\r
+#define AT91C_PC4_A6       (AT91C_PIO_PC4) //  \r
+#define AT91C_PC4_SPI0_NPCS2 (AT91C_PIO_PC4) //  \r
+#define AT91C_PIO_PC5        (1 <<  5) // Pin Controlled by PC5\r
+#define AT91C_PC5_A7       (AT91C_PIO_PC5) //  \r
+#define AT91C_PC5_SPI0_NPCS3 (AT91C_PIO_PC5) //  \r
+#define AT91C_PIO_PC6        (1 <<  6) // Pin Controlled by PC6\r
+#define AT91C_PC6_A8       (AT91C_PIO_PC6) //  \r
+#define AT91C_PC6_PWML0    (AT91C_PIO_PC6) //  \r
+#define AT91C_PIO_PC7        (1 <<  7) // Pin Controlled by PC7\r
+#define AT91C_PC7_A9       (AT91C_PIO_PC7) //  \r
+#define AT91C_PC7_PWML1    (AT91C_PIO_PC7) //  \r
+#define AT91C_PIO_PC8        (1 <<  8) // Pin Controlled by PC8\r
+#define AT91C_PC8_A10      (AT91C_PIO_PC8) //  \r
+#define AT91C_PC8_PWML2    (AT91C_PIO_PC8) //  \r
+#define AT91C_PIO_PC9        (1 <<  9) // Pin Controlled by PC9\r
+#define AT91C_PC9_A11      (AT91C_PIO_PC9) //  \r
+#define AT91C_PC9_PWML3    (AT91C_PIO_PC9) //  \r
+\r
+// *****************************************************************************\r
+//               PERIPHERAL ID DEFINITIONS FOR AT91SAM3U4\r
+// *****************************************************************************\r
+#define AT91C_ID_SUPC   ( 0) // SUPPLY CONTROLLER\r
+#define AT91C_ID_RSTC   ( 1) // RESET CONTROLLER\r
+#define AT91C_ID_RTC    ( 2) // REAL TIME CLOCK\r
+#define AT91C_ID_RTT    ( 3) // REAL TIME TIMER\r
+#define AT91C_ID_WDG    ( 4) // WATCHDOG TIMER\r
+#define AT91C_ID_PMC    ( 5) // PMC\r
+#define AT91C_ID_EFC0   ( 6) // EFC0\r
+#define AT91C_ID_EFC1   ( 7) // EFC1\r
+#define AT91C_ID_DBGU   ( 8) // DBGU\r
+#define AT91C_ID_HSMC4  ( 9) // HSMC4\r
+#define AT91C_ID_PIOA   (10) // Parallel IO Controller A\r
+#define AT91C_ID_PIOB   (11) // Parallel IO Controller B\r
+#define AT91C_ID_PIOC   (12) // Parallel IO Controller C\r
+#define AT91C_ID_US0    (13) // USART 0\r
+#define AT91C_ID_US1    (14) // USART 1\r
+#define AT91C_ID_US2    (15) // USART 2\r
+#define AT91C_ID_US3    (16) // USART 3\r
+#define AT91C_ID_MCI0   (17) // Multimedia Card Interface\r
+#define AT91C_ID_TWI0   (18) // TWI 0\r
+#define AT91C_ID_TWI1   (19) // TWI 1\r
+#define AT91C_ID_SPI0   (20) // Serial Peripheral Interface\r
+#define AT91C_ID_SSC0   (21) // Serial Synchronous Controller 0\r
+#define AT91C_ID_TC0    (22) // Timer Counter 0\r
+#define AT91C_ID_TC1    (23) // Timer Counter 1\r
+#define AT91C_ID_TC2    (24) // Timer Counter 2\r
+#define AT91C_ID_PWMC   (25) // Pulse Width Modulation Controller\r
+#define AT91C_ID_ADCC0  (26) // ADC controller0\r
+#define AT91C_ID_ADCC1  (27) // ADC controller1\r
+#define AT91C_ID_HDMA   (28) // HDMA\r
+#define AT91C_ID_UDPHS  (29) // USB Device High Speed\r
+#define AT91C_ALL_INT   (0x3FFFFFFF) // ALL VALID INTERRUPTS\r
+\r
+// *****************************************************************************\r
+//               BASE ADDRESS DEFINITIONS FOR AT91SAM3U4\r
+// *****************************************************************************\r
+#define AT91C_BASE_SYS       (AT91_CAST(AT91PS_SYS)    0x400E0000) // (SYS) Base Address\r
+#define AT91C_BASE_HSMC4_CS0 (AT91_CAST(AT91PS_HSMC4_CS)       0x400E0070) // (HSMC4_CS0) Base Address\r
+#define AT91C_BASE_HSMC4_CS1 (AT91_CAST(AT91PS_HSMC4_CS)       0x400E0084) // (HSMC4_CS1) Base Address\r
+#define AT91C_BASE_HSMC4_CS2 (AT91_CAST(AT91PS_HSMC4_CS)       0x400E0098) // (HSMC4_CS2) Base Address\r
+#define AT91C_BASE_HSMC4_CS3 (AT91_CAST(AT91PS_HSMC4_CS)       0x400E00AC) // (HSMC4_CS3) Base Address\r
+#define AT91C_BASE_HSMC4_NFC (AT91_CAST(AT91PS_HSMC4_CS)       0x400E00FC) // (HSMC4_NFC) Base Address\r
+#define AT91C_BASE_HSMC4     (AT91_CAST(AT91PS_HSMC4)  0x400E0000) // (HSMC4) Base Address\r
+#define AT91C_BASE_MATRIX    (AT91_CAST(AT91PS_HMATRIX2)       0x400E0200) // (MATRIX) Base Address\r
+#define AT91C_BASE_NVIC      (AT91_CAST(AT91PS_NVIC)   0xE000E000) // (NVIC) Base Address\r
+#define AT91C_BASE_MPU       (AT91_CAST(AT91PS_MPU)    0xE000ED90) // (MPU) Base Address\r
+#define AT91C_BASE_CM3       (AT91_CAST(AT91PS_CM3)    0xE000ED00) // (CM3) Base Address\r
+#define AT91C_BASE_PDC_DBGU  (AT91_CAST(AT91PS_PDC)    0x400E0700) // (PDC_DBGU) Base Address\r
+#define AT91C_BASE_DBGU      (AT91_CAST(AT91PS_DBGU)   0x400E0600) // (DBGU) Base Address\r
+#define AT91C_BASE_PIOA      (AT91_CAST(AT91PS_PIO)    0x400E0C00) // (PIOA) Base Address\r
+#define AT91C_BASE_PIOB      (AT91_CAST(AT91PS_PIO)    0x400E0E00) // (PIOB) Base Address\r
+#define AT91C_BASE_PIOC      (AT91_CAST(AT91PS_PIO)    0x400E1000) // (PIOC) Base Address\r
+#define AT91C_BASE_PMC       (AT91_CAST(AT91PS_PMC)    0x400E0400) // (PMC) Base Address\r
+#define AT91C_BASE_CKGR      (AT91_CAST(AT91PS_CKGR)   0x400E041C) // (CKGR) Base Address\r
+#define AT91C_BASE_RSTC      (AT91_CAST(AT91PS_RSTC)   0x400E1200) // (RSTC) Base Address\r
+#define AT91C_BASE_SUPC      (AT91_CAST(AT91PS_SUPC)   0x400E1210) // (SUPC) Base Address\r
+#define AT91C_BASE_RTTC      (AT91_CAST(AT91PS_RTTC)   0x400E1230) // (RTTC) Base Address\r
+#define AT91C_BASE_WDTC      (AT91_CAST(AT91PS_WDTC)   0x400E1250) // (WDTC) Base Address\r
+#define AT91C_BASE_RTC       (AT91_CAST(AT91PS_RTC)    0x400E1260) // (RTC) Base Address\r
+#define AT91C_BASE_ADC0      (AT91_CAST(AT91PS_ADC)    0x400A8000) // (ADC0) Base Address\r
+#define AT91C_BASE_ADC1      (AT91_CAST(AT91PS_ADC)    0x400AC000) // (ADC1) Base Address\r
+#define AT91C_BASE_TC0       (AT91_CAST(AT91PS_TC)     0x40080000) // (TC0) Base Address\r
+#define AT91C_BASE_TC1       (AT91_CAST(AT91PS_TC)     0x40080040) // (TC1) Base Address\r
+#define AT91C_BASE_TC2       (AT91_CAST(AT91PS_TC)     0x40080080) // (TC2) Base Address\r
+#define AT91C_BASE_TCB0      (AT91_CAST(AT91PS_TCB)    0x40080000) // (TCB0) Base Address\r
+#define AT91C_BASE_TCB1      (AT91_CAST(AT91PS_TCB)    0x40080040) // (TCB1) Base Address\r
+#define AT91C_BASE_TCB2      (AT91_CAST(AT91PS_TCB)    0x40080080) // (TCB2) Base Address\r
+#define AT91C_BASE_EFC0      (AT91_CAST(AT91PS_EFC)    0x400E0800) // (EFC0) Base Address\r
+#define AT91C_BASE_EFC1      (AT91_CAST(AT91PS_EFC)    0x400E0A00) // (EFC1) Base Address\r
+#define AT91C_BASE_MCI0      (AT91_CAST(AT91PS_MCI)    0x40000000) // (MCI0) Base Address\r
+#define AT91C_BASE_PDC_TWI0  (AT91_CAST(AT91PS_PDC)    0x40084100) // (PDC_TWI0) Base Address\r
+#define AT91C_BASE_PDC_TWI1  (AT91_CAST(AT91PS_PDC)    0x40088100) // (PDC_TWI1) Base Address\r
+#define AT91C_BASE_TWI0      (AT91_CAST(AT91PS_TWI)    0x40084000) // (TWI0) Base Address\r
+#define AT91C_BASE_TWI1      (AT91_CAST(AT91PS_TWI)    0x40088000) // (TWI1) Base Address\r
+#define AT91C_BASE_PDC_US0   (AT91_CAST(AT91PS_PDC)    0x40090100) // (PDC_US0) Base Address\r
+#define AT91C_BASE_US0       (AT91_CAST(AT91PS_USART)  0x40090000) // (US0) Base Address\r
+#define AT91C_BASE_PDC_US1   (AT91_CAST(AT91PS_PDC)    0x40094100) // (PDC_US1) Base Address\r
+#define AT91C_BASE_US1       (AT91_CAST(AT91PS_USART)  0x40094000) // (US1) Base Address\r
+#define AT91C_BASE_PDC_US2   (AT91_CAST(AT91PS_PDC)    0x40098100) // (PDC_US2) Base Address\r
+#define AT91C_BASE_US2       (AT91_CAST(AT91PS_USART)  0x40098000) // (US2) Base Address\r
+#define AT91C_BASE_PDC_US3   (AT91_CAST(AT91PS_PDC)    0x4009C100) // (PDC_US3) Base Address\r
+#define AT91C_BASE_US3       (AT91_CAST(AT91PS_USART)  0x4009C000) // (US3) Base Address\r
+#define AT91C_BASE_PDC_SSC0  (AT91_CAST(AT91PS_PDC)    0x40004100) // (PDC_SSC0) Base Address\r
+#define AT91C_BASE_SSC0      (AT91_CAST(AT91PS_SSC)    0x40004000) // (SSC0) Base Address\r
+#define AT91C_BASE_PDC_PWMC  (AT91_CAST(AT91PS_PDC)    0x4008C100) // (PDC_PWMC) Base Address\r
+#define AT91C_BASE_PWMC_CH0  (AT91_CAST(AT91PS_PWMC_CH)        0x4008C200) // (PWMC_CH0) Base Address\r
+#define AT91C_BASE_PWMC_CH1  (AT91_CAST(AT91PS_PWMC_CH)        0x4008C220) // (PWMC_CH1) Base Address\r
+#define AT91C_BASE_PWMC_CH2  (AT91_CAST(AT91PS_PWMC_CH)        0x4008C240) // (PWMC_CH2) Base Address\r
+#define AT91C_BASE_PWMC_CH3  (AT91_CAST(AT91PS_PWMC_CH)        0x4008C260) // (PWMC_CH3) Base Address\r
+#define AT91C_BASE_PWMC      (AT91_CAST(AT91PS_PWMC)   0x4008C000) // (PWMC) Base Address\r
+#define AT91C_BASE_SPI0      (AT91_CAST(AT91PS_SPI)    0x40008000) // (SPI0) Base Address\r
+#define AT91C_BASE_UDPHS_EPTFIFO (AT91_CAST(AT91PS_UDPHS_EPTFIFO)      0x20180000) // (UDPHS_EPTFIFO) Base Address\r
+#define AT91C_BASE_UDPHS_EPT_0 (AT91_CAST(AT91PS_UDPHS_EPT)    0x400A4100) // (UDPHS_EPT_0) Base Address\r
+#define AT91C_BASE_UDPHS_EPT_1 (AT91_CAST(AT91PS_UDPHS_EPT)    0x400A4120) // (UDPHS_EPT_1) Base Address\r
+#define AT91C_BASE_UDPHS_EPT_2 (AT91_CAST(AT91PS_UDPHS_EPT)    0x400A4140) // (UDPHS_EPT_2) Base Address\r
+#define AT91C_BASE_UDPHS_EPT_3 (AT91_CAST(AT91PS_UDPHS_EPT)    0x400A4160) // (UDPHS_EPT_3) Base Address\r
+#define AT91C_BASE_UDPHS_EPT_4 (AT91_CAST(AT91PS_UDPHS_EPT)    0x400A4180) // (UDPHS_EPT_4) Base Address\r
+#define AT91C_BASE_UDPHS_EPT_5 (AT91_CAST(AT91PS_UDPHS_EPT)    0x400A41A0) // (UDPHS_EPT_5) Base Address\r
+#define AT91C_BASE_UDPHS_EPT_6 (AT91_CAST(AT91PS_UDPHS_EPT)    0x400A41C0) // (UDPHS_EPT_6) Base Address\r
+#define AT91C_BASE_UDPHS_DMA_1 (AT91_CAST(AT91PS_UDPHS_DMA)    0x400A4310) // (UDPHS_DMA_1) Base Address\r
+#define AT91C_BASE_UDPHS_DMA_2 (AT91_CAST(AT91PS_UDPHS_DMA)    0x400A4320) // (UDPHS_DMA_2) Base Address\r
+#define AT91C_BASE_UDPHS_DMA_3 (AT91_CAST(AT91PS_UDPHS_DMA)    0x400A4330) // (UDPHS_DMA_3) Base Address\r
+#define AT91C_BASE_UDPHS_DMA_4 (AT91_CAST(AT91PS_UDPHS_DMA)    0x400A4340) // (UDPHS_DMA_4) Base Address\r
+#define AT91C_BASE_UDPHS_DMA_5 (AT91_CAST(AT91PS_UDPHS_DMA)    0x400A4350) // (UDPHS_DMA_5) Base Address\r
+#define AT91C_BASE_UDPHS_DMA_6 (AT91_CAST(AT91PS_UDPHS_DMA)    0x400A4360) // (UDPHS_DMA_6) Base Address\r
+#define AT91C_BASE_UDPHS     (AT91_CAST(AT91PS_UDPHS)  0x400A4000) // (UDPHS) Base Address\r
+#define AT91C_BASE_HDMA_CH_0 (AT91_CAST(AT91PS_HDMA_CH)        0x400B003C) // (HDMA_CH_0) Base Address\r
+#define AT91C_BASE_HDMA_CH_1 (AT91_CAST(AT91PS_HDMA_CH)        0x400B0064) // (HDMA_CH_1) Base Address\r
+#define AT91C_BASE_HDMA_CH_2 (AT91_CAST(AT91PS_HDMA_CH)        0x400B008C) // (HDMA_CH_2) Base Address\r
+#define AT91C_BASE_HDMA_CH_3 (AT91_CAST(AT91PS_HDMA_CH)        0x400B00B4) // (HDMA_CH_3) Base Address\r
+#define AT91C_BASE_HDMA      (AT91_CAST(AT91PS_HDMA)   0x400B0000) // (HDMA) Base Address\r
+\r
+// *****************************************************************************\r
+//               MEMORY MAPPING DEFINITIONS FOR AT91SAM3U4\r
+// *****************************************************************************\r
+// ITCM\r
+#define AT91C_ITCM      (0x00100000) // Maximum ITCM Area base address\r
+#define AT91C_ITCM_SIZE         (0x00010000) // Maximum ITCM Area size in byte (64 Kbytes)\r
+// DTCM\r
+#define AT91C_DTCM      (0x00200000) // Maximum DTCM Area base address\r
+#define AT91C_DTCM_SIZE         (0x00010000) // Maximum DTCM Area size in byte (64 Kbytes)\r
+// IRAM\r
+#define AT91C_IRAM      (0x20000000) // Maximum Internal SRAM base address\r
+#define AT91C_IRAM_SIZE         (0x00010000) // Maximum Internal SRAM size in byte (64 Kbytes)\r
+// IRAM_MIN\r
+#define AT91C_IRAM_MIN  (0x00300000) // Minimum Internal RAM base address\r
+#define AT91C_IRAM_MIN_SIZE     (0x00004000) // Minimum Internal RAM size in byte (16 Kbytes)\r
+// IROM\r
+#define AT91C_IROM      (0x00180000) // Internal ROM base address\r
+#define AT91C_IROM_SIZE         (0x00008000) // Internal ROM size in byte (32 Kbytes)\r
+// IFLASH0\r
+#define AT91C_IFLASH0   (0x00080000) // Maximum IFLASH Area : 128Kbyte base address\r
+#define AT91C_IFLASH0_SIZE      (0x00020000) // Maximum IFLASH Area : 128Kbyte size in byte (128 Kbytes)\r
+#define AT91C_IFLASH0_PAGE_SIZE         (256) // Maximum IFLASH Area : 128Kbyte Page Size: 256 bytes\r
+#define AT91C_IFLASH0_LOCK_REGION_SIZE  (8192) // Maximum IFLASH Area : 128Kbyte Lock Region Size: 8 Kbytes\r
+#define AT91C_IFLASH0_NB_OF_PAGES       (512) // Maximum IFLASH Area : 128Kbyte Number of Pages: 512 bytes\r
+#define AT91C_IFLASH0_NB_OF_LOCK_BITS   (16) // Maximum IFLASH Area : 128Kbyte Number of Lock Bits: 32 bytes\r
+// IFLASH1\r
+#define AT91C_IFLASH1   (0x0100000) // Maximum IFLASH Area : 128Kbyte base address\r
+#define AT91C_IFLASH1_SIZE      (0x00020000) // Maximum IFLASH Area : 128Kbyte size in byte (128 Kbytes)\r
+#define AT91C_IFLASH1_PAGE_SIZE         (256) // Maximum IFLASH Area : 128Kbyte Page Size: 256 bytes\r
+#define AT91C_IFLASH1_LOCK_REGION_SIZE  (8192) // Maximum IFLASH Area : 128Kbyte Lock Region Size: 8 Kbytes\r
+#define AT91C_IFLASH1_NB_OF_PAGES       (512) // Maximum IFLASH Area : 128Kbyte Number of Pages: 512 bytes\r
+#define AT91C_IFLASH1_NB_OF_LOCK_BITS   (16) // Maximum IFLASH Area : 128Kbyte Number of Lock Bits: 32 bytes\r
+// EBI_CS0\r
+#define AT91C_EBI_CS0   (0x10000000) // EBI Chip Select 0 base address\r
+#define AT91C_EBI_CS0_SIZE      (0x10000000) // EBI Chip Select 0 size in byte (262144 Kbytes)\r
+// EBI_CS1\r
+#define AT91C_EBI_CS1   (0x20000000) // EBI Chip Select 1 base address\r
+#define AT91C_EBI_CS1_SIZE      (0x10000000) // EBI Chip Select 1 size in byte (262144 Kbytes)\r
+// EBI_SDRAM\r
+#define AT91C_EBI_SDRAM         (0x20000000) // SDRAM on EBI Chip Select 1 base address\r
+#define AT91C_EBI_SDRAM_SIZE    (0x10000000) // SDRAM on EBI Chip Select 1 size in byte (262144 Kbytes)\r
+// EBI_SDRAM_16BIT\r
+#define AT91C_EBI_SDRAM_16BIT   (0x20000000) // SDRAM on EBI Chip Select 1 base address\r
+#define AT91C_EBI_SDRAM_16BIT_SIZE      (0x02000000) // SDRAM on EBI Chip Select 1 size in byte (32768 Kbytes)\r
+// EBI_SDRAM_32BIT\r
+#define AT91C_EBI_SDRAM_32BIT   (0x20000000) // SDRAM on EBI Chip Select 1 base address\r
+#define AT91C_EBI_SDRAM_32BIT_SIZE      (0x04000000) // SDRAM on EBI Chip Select 1 size in byte (65536 Kbytes)\r
+// EBI_CS2\r
+#define AT91C_EBI_CS2   (0x30000000) // EBI Chip Select 2 base address\r
+#define AT91C_EBI_CS2_SIZE      (0x10000000) // EBI Chip Select 2 size in byte (262144 Kbytes)\r
+// EBI_CS3\r
+#define AT91C_EBI_CS3   (0x40000000) // EBI Chip Select 3 base address\r
+#define AT91C_EBI_CS3_SIZE      (0x10000000) // EBI Chip Select 3 size in byte (262144 Kbytes)\r
+// EBI_SM\r
+#define AT91C_EBI_SM    (0x40000000) // NANDFLASH on EBI Chip Select 3 base address\r
+#define AT91C_EBI_SM_SIZE       (0x10000000) // NANDFLASH on EBI Chip Select 3 size in byte (262144 Kbytes)\r
+// EBI_CS4\r
+#define AT91C_EBI_CS4   (0x50000000) // EBI Chip Select 4 base address\r
+#define AT91C_EBI_CS4_SIZE      (0x10000000) // EBI Chip Select 4 size in byte (262144 Kbytes)\r
+// EBI_CF0\r
+#define AT91C_EBI_CF0   (0x50000000) // CompactFlash 0 on EBI Chip Select 4 base address\r
+#define AT91C_EBI_CF0_SIZE      (0x10000000) // CompactFlash 0 on EBI Chip Select 4 size in byte (262144 Kbytes)\r
+// EBI_CS5\r
+#define AT91C_EBI_CS5   (0x60000000) // EBI Chip Select 5 base address\r
+#define AT91C_EBI_CS5_SIZE      (0x10000000) // EBI Chip Select 5 size in byte (262144 Kbytes)\r
+// EBI_CF1\r
+#define AT91C_EBI_CF1   (0x60000000) // CompactFlash 1 on EBIChip Select 5 base address\r
+#define AT91C_EBI_CF1_SIZE      (0x10000000) // CompactFlash 1 on EBIChip Select 5 size in byte (262144 Kbytes)\r
+\r
+#endif\r

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/system/at91sam3u-ek-flash.mac b/Demo/CORTEX_AT91SAM3U256_IAR/system/at91sam3u-ek-flash.mac
new file mode 100644 (file)
index 0000000..0fec0a0
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/system/at91sam3u-ek-flash.mac
@@ -0,0 +1,35 @@
+// ---------------------------------------------------------\r
+//   ATMEL Microcontroller Software Support  -  ROUSSET  -\r
+// ---------------------------------------------------------\r
+// The software is delivered "AS IS" without warranty or\r
+// condition of any  kind, either express, implied or\r
+// statutory. This includes without limitation any warranty\r
+// or condition with respect to merchantability or fitness\r
+// for any particular purpose, or against the infringements of\r
+// intellectual property rights of others.\r
+// ---------------------------------------------------------\r
+//  File: at91sam3u-ek-flash.mac\r
+//  User setup file for CSPY debugger.\r
+// ---------------------------------------------------------\r
+__var __mac_i;\r
+__var __mac_pt;\r
+\r
+/*********************************************************************\r
+*\r
+*       execUserReset()\r
+*/\r
+execUserReset()\r
+{\r
+    __message "------------------------------ execUserReset ---------------------------------";\r
+    __message "-------------------------------Set PC Reset ----------------------------------";\r
+}\r
+\r
+/*********************************************************************\r
+*\r
+*       execUserPreload()\r
+*/\r
+execUserPreload()\r
+{\r
+    __message "------------------------------ execUserPreload ---------------------------------";\r
+    __hwReset(0);                          //* Hardware Reset: CPU is automatically halted after the reset\r
+}\r

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/system/at91sam3u4/AT91SAM3U4.h b/Demo/CORTEX_AT91SAM3U256_IAR/system/at91sam3u4/AT91SAM3U4.h
new file mode 100644 (file)
index 0000000..a7cb9a6
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/system/at91sam3u4/AT91SAM3U4.h
@@ -0,0 +1,6517 @@
+//  ----------------------------------------------------------------------------\r
+//          ATMEL Microcontroller Software Support  -  ROUSSET  -\r
+//  ----------------------------------------------------------------------------\r
+//  Copyright (c) 2008, Atmel Corporation\r
+// \r
+//  All rights reserved.\r
+// \r
+//  Redistribution and use in source and binary forms, with or without\r
+//  modification, are permitted provided that the following conditions are met:\r
+// \r
+//  - Redistributions of source code must retain the above copyright notice,\r
+//  this list of conditions and the disclaimer below.\r
+// \r
+//  Atmel's name may not be used to endorse or promote products derived from\r
+//  this software without specific prior written permission. \r
+//  \r
+//  DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+//  IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+//  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+//  DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+//  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+//  OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+//  LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+//  NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+//  EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+//  ----------------------------------------------------------------------------\r
+// File Name           : AT91SAM3U4.h\r
+// Object              : AT91SAM3U4 definitions\r
+// Generated           : AT91 SW Application Group  03/09/2009 (11:49:34)\r
+// \r
+// CVS Reference       : /AT91SAM3U4.pl/1.32/Mon Feb  9 14:20:58 2009//\r
+// CVS Reference       : /SYS_SAM3U4.pl/1.4/Fri Oct 17 13:27:57 2008//\r
+// CVS Reference       : /HMATRIX2_SAM3U4.pl/1.3/Mon Mar  2 10:12:07 2009//\r
+// CVS Reference       : /PMC_SAM3U4.pl/1.7/Fri Oct 17 13:27:54 2008//\r
+// CVS Reference       : /EBI_SAM9260.pl/1.1/Fri Sep 30 12:12:14 2005//\r
+// CVS Reference       : /EFC2_SAM3U4.pl/1.3/Mon Mar  2 10:12:06 2009//\r
+// CVS Reference       : /HSDRAMC1_6100A.pl/1.2/Mon Aug  9 10:52:25 2004//\r
+// CVS Reference       : /HSMC4_xxxx.pl/1.9/Fri Oct 17 13:27:56 2008//\r
+// CVS Reference       : /HECC_6143A.pl/1.1/Wed Feb  9 17:16:57 2005//\r
+// CVS Reference       : /CORTEX_M3_NVIC.pl/1.7/Tue Jan 27 16:16:24 2009//\r
+// CVS Reference       : /CORTEX_M3_MPU.pl/1.3/Fri Oct 17 13:27:48 2008//\r
+// CVS Reference       : /CORTEX_M3.pl/1.1/Mon Sep 15 15:22:06 2008//\r
+// CVS Reference       : /PDC_6074C.pl/1.2/Thu Feb  3 09:02:11 2005//\r
+// CVS Reference       : /DBGU_SAM3U4.pl/1.2/Fri Oct 17 13:27:49 2008//\r
+// CVS Reference       : /PIO3_xxxx.pl/1.6/Mon Mar  9 10:43:37 2009//\r
+// CVS Reference       : /RSTC_6098A.pl/1.4/Fri Oct 17 13:27:55 2008//\r
+// CVS Reference       : /SHDWC_6122A.pl/1.3/Wed Oct  6 14:16:58 2004//\r
+// CVS Reference       : /SUPC_SAM3U4.pl/1.2/Thu Jun  5 15:27:27 2008//\r
+// CVS Reference       : /RTTC_6081A.pl/1.2/Thu Nov  4 13:57:22 2004//\r
+// CVS Reference       : /PITC_6079A.pl/1.2/Thu Nov  4 13:56:22 2004//\r
+// CVS Reference       : /WDTC_6080A.pl/1.3/Thu Nov  4 13:58:52 2004//\r
+// CVS Reference       : /TC_6082A.pl/1.8/Fri Oct 17 13:27:58 2008//\r
+// CVS Reference       : /MCI_6101F.pl/1.3/Fri Jan 23 09:15:32 2009//\r
+// CVS Reference       : /TWI_6061B.pl/1.3/Fri Oct 17 13:27:59 2008//\r
+// CVS Reference       : /US_6089J.pl/1.3/Fri Oct 17 13:27:59 2008//\r
+// CVS Reference       : /SSC_6078B.pl/1.3/Fri Oct 17 13:27:57 2008//\r
+// CVS Reference       : /SPI2.pl/1.4/Mon Mar  9 08:56:28 2009//\r
+// CVS Reference       : /PWM_6343B_V400.pl/1.3/Fri Oct 17 13:27:54 2008//\r
+// CVS Reference       : /HDMA_SAM3U4.pl/1.3/Fri Oct 17 13:27:51 2008//\r
+// CVS Reference       : /UDPHS_SAM9_7ept6dma4iso.pl/1.4/Tue Jun 24 13:05:14 2008//\r
+// CVS Reference       : /ADC_SAM3UE.pl/1.4/Fri Feb 20 12:19:18 2009//\r
+// CVS Reference       : /RTC_1245D.pl/1.3/Fri Sep 17 14:01:31 2004//\r
+//  ----------------------------------------------------------------------------\r
+\r
+#ifndef AT91SAM3U4_H\r
+#define AT91SAM3U4_H\r
+\r
+#ifndef __ASSEMBLY__\r
+typedef volatile unsigned int AT91_REG;// Hardware register definition\r
+#define AT91_CAST(a) (a)\r
+#else\r
+#define AT91_CAST(a)\r
+#endif\r
+\r
+// *****************************************************************************\r
+//              SOFTWARE API DEFINITION  FOR System Peripherals\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_SYS {\r
+       AT91_REG         HSMC4_CFG;     // Configuration Register\r
+       AT91_REG         HSMC4_CTRL;    // Control Register\r
+       AT91_REG         HSMC4_SR;      // Status Register\r
+       AT91_REG         HSMC4_IER;     // Interrupt Enable Register\r
+       AT91_REG         HSMC4_IDR;     // Interrupt Disable Register\r
+       AT91_REG         HSMC4_IMR;     // Interrupt Mask Register\r
+       AT91_REG         HSMC4_ADDR;    // Address Cycle Zero Register\r
+       AT91_REG         HSMC4_BANK;    // Bank Register\r
+       AT91_REG         HSMC4_ECCCR;   // ECC reset register\r
+       AT91_REG         HSMC4_ECCCMD;  // ECC Page size register\r
+       AT91_REG         HSMC4_ECCSR1;  // ECC Status register 1\r
+       AT91_REG         HSMC4_ECCPR0;  // ECC Parity register 0\r
+       AT91_REG         HSMC4_ECCPR1;  // ECC Parity register 1\r
+       AT91_REG         HSMC4_ECCSR2;  // ECC Status register 2\r
+       AT91_REG         HSMC4_ECCPR2;  // ECC Parity register 2\r
+       AT91_REG         HSMC4_ECCPR3;  // ECC Parity register 3\r
+       AT91_REG         HSMC4_ECCPR4;  // ECC Parity register 4\r
+       AT91_REG         HSMC4_ECCPR5;  // ECC Parity register 5\r
+       AT91_REG         HSMC4_ECCPR6;  // ECC Parity register 6\r
+       AT91_REG         HSMC4_ECCPR7;  // ECC Parity register 7\r
+       AT91_REG         HSMC4_ECCPR8;  // ECC Parity register 8\r
+       AT91_REG         HSMC4_ECCPR9;  // ECC Parity register 9\r
+       AT91_REG         HSMC4_ECCPR10;         // ECC Parity register 10\r
+       AT91_REG         HSMC4_ECCPR11;         // ECC Parity register 11\r
+       AT91_REG         HSMC4_ECCPR12;         // ECC Parity register 12\r
+       AT91_REG         HSMC4_ECCPR13;         // ECC Parity register 13\r
+       AT91_REG         HSMC4_ECCPR14;         // ECC Parity register 14\r
+       AT91_REG         HSMC4_Eccpr15;         // ECC Parity register 15\r
+       AT91_REG         Reserved0[40];         // \r
+       AT91_REG         HSMC4_OCMS;    // OCMS MODE register\r
+       AT91_REG         HSMC4_KEY1;    // KEY1 Register\r
+       AT91_REG         HSMC4_KEY2;    // KEY2 Register\r
+       AT91_REG         Reserved1[50];         // \r
+       AT91_REG         HSMC4_WPCR;    // Write Protection Control register\r
+       AT91_REG         HSMC4_WPSR;    // Write Protection Status Register\r
+       AT91_REG         HSMC4_ADDRSIZE;        // Write Protection Status Register\r
+       AT91_REG         HSMC4_IPNAME1;         // Write Protection Status Register\r
+       AT91_REG         HSMC4_IPNAME2;         // Write Protection Status Register\r
+       AT91_REG         HSMC4_FEATURES;        // Write Protection Status Register\r
+       AT91_REG         HSMC4_VER;     // HSMC4 Version Register\r
+       AT91_REG         HMATRIX_MCFG0;         //  Master Configuration Register 0 : ARM I and D\r
+       AT91_REG         HMATRIX_MCFG1;         //  Master Configuration Register 1 : ARM S\r
+       AT91_REG         HMATRIX_MCFG2;         //  Master Configuration Register 2\r
+       AT91_REG         HMATRIX_MCFG3;         //  Master Configuration Register 3\r
+       AT91_REG         HMATRIX_MCFG4;         //  Master Configuration Register 4\r
+       AT91_REG         HMATRIX_MCFG5;         //  Master Configuration Register 5\r
+       AT91_REG         HMATRIX_MCFG6;         //  Master Configuration Register 6\r
+       AT91_REG         HMATRIX_MCFG7;         //  Master Configuration Register 7\r
+       AT91_REG         Reserved2[8];  // \r
+       AT91_REG         HMATRIX_SCFG0;         //  Slave Configuration Register 0\r
+       AT91_REG         HMATRIX_SCFG1;         //  Slave Configuration Register 1\r
+       AT91_REG         HMATRIX_SCFG2;         //  Slave Configuration Register 2\r
+       AT91_REG         HMATRIX_SCFG3;         //  Slave Configuration Register 3\r
+       AT91_REG         HMATRIX_SCFG4;         //  Slave Configuration Register 4\r
+       AT91_REG         HMATRIX_SCFG5;         //  Slave Configuration Register 5\r
+       AT91_REG         HMATRIX_SCFG6;         //  Slave Configuration Register 6\r
+       AT91_REG         HMATRIX_SCFG7;         //  Slave Configuration Register 5\r
+       AT91_REG         HMATRIX_SCFG8;         //  Slave Configuration Register 8\r
+       AT91_REG         Reserved3[43];         // \r
+       AT91_REG         HMATRIX_SFR0 ;         //  Special Function Register 0\r
+       AT91_REG         HMATRIX_SFR1 ;         //  Special Function Register 1\r
+       AT91_REG         HMATRIX_SFR2 ;         //  Special Function Register 2\r
+       AT91_REG         HMATRIX_SFR3 ;         //  Special Function Register 3\r
+       AT91_REG         HMATRIX_SFR4 ;         //  Special Function Register 4\r
+       AT91_REG         HMATRIX_SFR5 ;         //  Special Function Register 5\r
+       AT91_REG         HMATRIX_SFR6 ;         //  Special Function Register 6\r
+       AT91_REG         HMATRIX_SFR7 ;         //  Special Function Register 7\r
+       AT91_REG         HMATRIX_SFR8 ;         //  Special Function Register 8\r
+       AT91_REG         HMATRIX_SFR9 ;         //  Special Function Register 9\r
+       AT91_REG         HMATRIX_SFR10;         //  Special Function Register 10\r
+       AT91_REG         HMATRIX_SFR11;         //  Special Function Register 11\r
+       AT91_REG         HMATRIX_SFR12;         //  Special Function Register 12\r
+       AT91_REG         HMATRIX_SFR13;         //  Special Function Register 13\r
+       AT91_REG         HMATRIX_SFR14;         //  Special Function Register 14\r
+       AT91_REG         HMATRIX_SFR15;         //  Special Function Register 15\r
+       AT91_REG         Reserved4[39];         // \r
+       AT91_REG         HMATRIX_ADDRSIZE;      // HMATRIX2 ADDRSIZE REGISTER \r
+       AT91_REG         HMATRIX_IPNAME1;       // HMATRIX2 IPNAME1 REGISTER \r
+       AT91_REG         HMATRIX_IPNAME2;       // HMATRIX2 IPNAME2 REGISTER \r
+       AT91_REG         HMATRIX_FEATURES;      // HMATRIX2 FEATURES REGISTER \r
+       AT91_REG         HMATRIX_VER;   // HMATRIX2 VERSION REGISTER \r
+       AT91_REG         PMC_SCER;      // System Clock Enable Register\r
+       AT91_REG         PMC_SCDR;      // System Clock Disable Register\r
+       AT91_REG         PMC_SCSR;      // System Clock Status Register\r
+       AT91_REG         Reserved5[1];  // \r
+       AT91_REG         PMC_PCER;      // Peripheral Clock Enable Register\r
+       AT91_REG         PMC_PCDR;      // Peripheral Clock Disable Register\r
+       AT91_REG         PMC_PCSR;      // Peripheral Clock Status Register\r
+       AT91_REG         PMC_UCKR;      // UTMI Clock Configuration Register\r
+       AT91_REG         PMC_MOR;       // Main Oscillator Register\r
+       AT91_REG         PMC_MCFR;      // Main Clock  Frequency Register\r
+       AT91_REG         PMC_PLLAR;     // PLL Register\r
+       AT91_REG         Reserved6[1];  // \r
+       AT91_REG         PMC_MCKR;      // Master Clock Register\r
+       AT91_REG         Reserved7[3];  // \r
+       AT91_REG         PMC_PCKR[8];   // Programmable Clock Register\r
+       AT91_REG         PMC_IER;       // Interrupt Enable Register\r
+       AT91_REG         PMC_IDR;       // Interrupt Disable Register\r
+       AT91_REG         PMC_SR;        // Status Register\r
+       AT91_REG         PMC_IMR;       // Interrupt Mask Register\r
+       AT91_REG         PMC_FSMR;      // Fast Startup Mode Register\r
+       AT91_REG         PMC_FSPR;      // Fast Startup Polarity Register\r
+       AT91_REG         PMC_FOCR;      // Fault Output Clear Register\r
+       AT91_REG         Reserved8[28];         // \r
+       AT91_REG         PMC_ADDRSIZE;  // PMC ADDRSIZE REGISTER \r
+       AT91_REG         PMC_IPNAME1;   // PMC IPNAME1 REGISTER \r
+       AT91_REG         PMC_IPNAME2;   // PMC IPNAME2 REGISTER \r
+       AT91_REG         PMC_FEATURES;  // PMC FEATURES REGISTER \r
+       AT91_REG         PMC_VER;       // APMC VERSION REGISTER\r
+       AT91_REG         Reserved9[64];         // \r
+       AT91_REG         DBGU_CR;       // Control Register\r
+       AT91_REG         DBGU_MR;       // Mode Register\r
+       AT91_REG         DBGU_IER;      // Interrupt Enable Register\r
+       AT91_REG         DBGU_IDR;      // Interrupt Disable Register\r
+       AT91_REG         DBGU_IMR;      // Interrupt Mask Register\r
+       AT91_REG         DBGU_CSR;      // Channel Status Register\r
+       AT91_REG         DBGU_RHR;      // Receiver Holding Register\r
+       AT91_REG         DBGU_THR;      // Transmitter Holding Register\r
+       AT91_REG         DBGU_BRGR;     // Baud Rate Generator Register\r
+       AT91_REG         Reserved10[9];         // \r
+       AT91_REG         DBGU_FNTR;     // Force NTRST Register\r
+       AT91_REG         Reserved11[40];        // \r
+       AT91_REG         DBGU_ADDRSIZE;         // DBGU ADDRSIZE REGISTER \r
+       AT91_REG         DBGU_IPNAME1;  // DBGU IPNAME1 REGISTER \r
+       AT91_REG         DBGU_IPNAME2;  // DBGU IPNAME2 REGISTER \r
+       AT91_REG         DBGU_FEATURES;         // DBGU FEATURES REGISTER \r
+       AT91_REG         DBGU_VER;      // DBGU VERSION REGISTER \r
+       AT91_REG         DBGU_RPR;      // Receive Pointer Register\r
+       AT91_REG         DBGU_RCR;      // Receive Counter Register\r
+       AT91_REG         DBGU_TPR;      // Transmit Pointer Register\r
+       AT91_REG         DBGU_TCR;      // Transmit Counter Register\r
+       AT91_REG         DBGU_RNPR;     // Receive Next Pointer Register\r
+       AT91_REG         DBGU_RNCR;     // Receive Next Counter Register\r
+       AT91_REG         DBGU_TNPR;     // Transmit Next Pointer Register\r
+       AT91_REG         DBGU_TNCR;     // Transmit Next Counter Register\r
+       AT91_REG         DBGU_PTCR;     // PDC Transfer Control Register\r
+       AT91_REG         DBGU_PTSR;     // PDC Transfer Status Register\r
+       AT91_REG         Reserved12[6];         // \r
+       AT91_REG         DBGU_CIDR;     // Chip ID Register\r
+       AT91_REG         DBGU_EXID;     // Chip ID Extension Register\r
+       AT91_REG         Reserved13[46];        // \r
+       AT91_REG         EFC0_FMR;      // EFC Flash Mode Register\r
+       AT91_REG         EFC0_FCR;      // EFC Flash Command Register\r
+       AT91_REG         EFC0_FSR;      // EFC Flash Status Register\r
+       AT91_REG         EFC0_FRR;      // EFC Flash Result Register\r
+       AT91_REG         Reserved14[1];         // \r
+       AT91_REG         EFC0_FVR;      // EFC Flash Version Register\r
+       AT91_REG         Reserved15[122];       // \r
+       AT91_REG         EFC1_FMR;      // EFC Flash Mode Register\r
+       AT91_REG         EFC1_FCR;      // EFC Flash Command Register\r
+       AT91_REG         EFC1_FSR;      // EFC Flash Status Register\r
+       AT91_REG         EFC1_FRR;      // EFC Flash Result Register\r
+       AT91_REG         Reserved16[1];         // \r
+       AT91_REG         EFC1_FVR;      // EFC Flash Version Register\r
+       AT91_REG         Reserved17[122];       // \r
+       AT91_REG         PIOA_PER;      // PIO Enable Register\r
+       AT91_REG         PIOA_PDR;      // PIO Disable Register\r
+       AT91_REG         PIOA_PSR;      // PIO Status Register\r
+       AT91_REG         Reserved18[1];         // \r
+       AT91_REG         PIOA_OER;      // Output Enable Register\r
+       AT91_REG         PIOA_ODR;      // Output Disable Registerr\r
+       AT91_REG         PIOA_OSR;      // Output Status Register\r
+       AT91_REG         Reserved19[1];         // \r
+       AT91_REG         PIOA_IFER;     // Input Filter Enable Register\r
+       AT91_REG         PIOA_IFDR;     // Input Filter Disable Register\r
+       AT91_REG         PIOA_IFSR;     // Input Filter Status Register\r
+       AT91_REG         Reserved20[1];         // \r
+       AT91_REG         PIOA_SODR;     // Set Output Data Register\r
+       AT91_REG         PIOA_CODR;     // Clear Output Data Register\r
+       AT91_REG         PIOA_ODSR;     // Output Data Status Register\r
+       AT91_REG         PIOA_PDSR;     // Pin Data Status Register\r
+       AT91_REG         PIOA_IER;      // Interrupt Enable Register\r
+       AT91_REG         PIOA_IDR;      // Interrupt Disable Register\r
+       AT91_REG         PIOA_IMR;      // Interrupt Mask Register\r
+       AT91_REG         PIOA_ISR;      // Interrupt Status Register\r
+       AT91_REG         PIOA_MDER;     // Multi-driver Enable Register\r
+       AT91_REG         PIOA_MDDR;     // Multi-driver Disable Register\r
+       AT91_REG         PIOA_MDSR;     // Multi-driver Status Register\r
+       AT91_REG         Reserved21[1];         // \r
+       AT91_REG         PIOA_PPUDR;    // Pull-up Disable Register\r
+       AT91_REG         PIOA_PPUER;    // Pull-up Enable Register\r
+       AT91_REG         PIOA_PPUSR;    // Pull-up Status Register\r
+       AT91_REG         Reserved22[1];         // \r
+       AT91_REG         PIOA_ABSR;     // Peripheral AB Select Register\r
+       AT91_REG         Reserved23[3];         // \r
+       AT91_REG         PIOA_SCIFSR;   // System Clock Glitch Input Filter Select Register\r
+       AT91_REG         PIOA_DIFSR;    // Debouncing Input Filter Select Register\r
+       AT91_REG         PIOA_IFDGSR;   // Glitch or Debouncing Input Filter Clock Selection Status Register\r
+       AT91_REG         PIOA_SCDR;     // Slow Clock Divider Debouncing Register\r
+       AT91_REG         Reserved24[4];         // \r
+       AT91_REG         PIOA_OWER;     // Output Write Enable Register\r
+       AT91_REG         PIOA_OWDR;     // Output Write Disable Register\r
+       AT91_REG         PIOA_OWSR;     // Output Write Status Register\r
+       AT91_REG         Reserved25[1];         // \r
+       AT91_REG         PIOA_AIMER;    // Additional Interrupt Modes Enable Register\r
+       AT91_REG         PIOA_AIMDR;    // Additional Interrupt Modes Disables Register\r
+       AT91_REG         PIOA_AIMMR;    // Additional Interrupt Modes Mask Register\r
+       AT91_REG         Reserved26[1];         // \r
+       AT91_REG         PIOA_ESR;      // Edge Select Register\r
+       AT91_REG         PIOA_LSR;      // Level Select Register\r
+       AT91_REG         PIOA_ELSR;     // Edge/Level Status Register\r
+       AT91_REG         Reserved27[1];         // \r
+       AT91_REG         PIOA_FELLSR;   // Falling Edge/Low Level Select Register\r
+       AT91_REG         PIOA_REHLSR;   // Rising Edge/ High Level Select Register\r
+       AT91_REG         PIOA_FRLHSR;   // Fall/Rise - Low/High Status Register\r
+       AT91_REG         Reserved28[1];         // \r
+       AT91_REG         PIOA_LOCKSR;   // Lock Status Register\r
+       AT91_REG         Reserved29[6];         // \r
+       AT91_REG         PIOA_VER;      // PIO VERSION REGISTER \r
+       AT91_REG         Reserved30[8];         // \r
+       AT91_REG         PIOA_KER;      // Keypad Controller Enable Register\r
+       AT91_REG         PIOA_KRCR;     // Keypad Controller Row Column Register\r
+       AT91_REG         PIOA_KDR;      // Keypad Controller Debouncing Register\r
+       AT91_REG         Reserved31[1];         // \r
+       AT91_REG         PIOA_KIER;     // Keypad Controller Interrupt Enable Register\r
+       AT91_REG         PIOA_KIDR;     // Keypad Controller Interrupt Disable Register\r
+       AT91_REG         PIOA_KIMR;     // Keypad Controller Interrupt Mask Register\r
+       AT91_REG         PIOA_KSR;      // Keypad Controller Status Register\r
+       AT91_REG         PIOA_KKPR;     // Keypad Controller Key Press Register\r
+       AT91_REG         PIOA_KKRR;     // Keypad Controller Key Release Register\r
+       AT91_REG         Reserved32[46];        // \r
+       AT91_REG         PIOB_PER;      // PIO Enable Register\r
+       AT91_REG         PIOB_PDR;      // PIO Disable Register\r
+       AT91_REG         PIOB_PSR;      // PIO Status Register\r
+       AT91_REG         Reserved33[1];         // \r
+       AT91_REG         PIOB_OER;      // Output Enable Register\r
+       AT91_REG         PIOB_ODR;      // Output Disable Registerr\r
+       AT91_REG         PIOB_OSR;      // Output Status Register\r
+       AT91_REG         Reserved34[1];         // \r
+       AT91_REG         PIOB_IFER;     // Input Filter Enable Register\r
+       AT91_REG         PIOB_IFDR;     // Input Filter Disable Register\r
+       AT91_REG         PIOB_IFSR;     // Input Filter Status Register\r
+       AT91_REG         Reserved35[1];         // \r
+       AT91_REG         PIOB_SODR;     // Set Output Data Register\r
+       AT91_REG         PIOB_CODR;     // Clear Output Data Register\r
+       AT91_REG         PIOB_ODSR;     // Output Data Status Register\r
+       AT91_REG         PIOB_PDSR;     // Pin Data Status Register\r
+       AT91_REG         PIOB_IER;      // Interrupt Enable Register\r
+       AT91_REG         PIOB_IDR;      // Interrupt Disable Register\r
+       AT91_REG         PIOB_IMR;      // Interrupt Mask Register\r
+       AT91_REG         PIOB_ISR;      // Interrupt Status Register\r
+       AT91_REG         PIOB_MDER;     // Multi-driver Enable Register\r
+       AT91_REG         PIOB_MDDR;     // Multi-driver Disable Register\r
+       AT91_REG         PIOB_MDSR;     // Multi-driver Status Register\r
+       AT91_REG         Reserved36[1];         // \r
+       AT91_REG         PIOB_PPUDR;    // Pull-up Disable Register\r
+       AT91_REG         PIOB_PPUER;    // Pull-up Enable Register\r
+       AT91_REG         PIOB_PPUSR;    // Pull-up Status Register\r
+       AT91_REG         Reserved37[1];         // \r
+       AT91_REG         PIOB_ABSR;     // Peripheral AB Select Register\r
+       AT91_REG         Reserved38[3];         // \r
+       AT91_REG         PIOB_SCIFSR;   // System Clock Glitch Input Filter Select Register\r
+       AT91_REG         PIOB_DIFSR;    // Debouncing Input Filter Select Register\r
+       AT91_REG         PIOB_IFDGSR;   // Glitch or Debouncing Input Filter Clock Selection Status Register\r
+       AT91_REG         PIOB_SCDR;     // Slow Clock Divider Debouncing Register\r
+       AT91_REG         Reserved39[4];         // \r
+       AT91_REG         PIOB_OWER;     // Output Write Enable Register\r
+       AT91_REG         PIOB_OWDR;     // Output Write Disable Register\r
+       AT91_REG         PIOB_OWSR;     // Output Write Status Register\r
+       AT91_REG         Reserved40[1];         // \r
+       AT91_REG         PIOB_AIMER;    // Additional Interrupt Modes Enable Register\r
+       AT91_REG         PIOB_AIMDR;    // Additional Interrupt Modes Disables Register\r
+       AT91_REG         PIOB_AIMMR;    // Additional Interrupt Modes Mask Register\r
+       AT91_REG         Reserved41[1];         // \r
+       AT91_REG         PIOB_ESR;      // Edge Select Register\r
+       AT91_REG         PIOB_LSR;      // Level Select Register\r
+       AT91_REG         PIOB_ELSR;     // Edge/Level Status Register\r
+       AT91_REG         Reserved42[1];         // \r
+       AT91_REG         PIOB_FELLSR;   // Falling Edge/Low Level Select Register\r
+       AT91_REG         PIOB_REHLSR;   // Rising Edge/ High Level Select Register\r
+       AT91_REG         PIOB_FRLHSR;   // Fall/Rise - Low/High Status Register\r
+       AT91_REG         Reserved43[1];         // \r
+       AT91_REG         PIOB_LOCKSR;   // Lock Status Register\r
+       AT91_REG         Reserved44[6];         // \r
+       AT91_REG         PIOB_VER;      // PIO VERSION REGISTER \r
+       AT91_REG         Reserved45[8];         // \r
+       AT91_REG         PIOB_KER;      // Keypad Controller Enable Register\r
+       AT91_REG         PIOB_KRCR;     // Keypad Controller Row Column Register\r
+       AT91_REG         PIOB_KDR;      // Keypad Controller Debouncing Register\r
+       AT91_REG         Reserved46[1];         // \r
+       AT91_REG         PIOB_KIER;     // Keypad Controller Interrupt Enable Register\r
+       AT91_REG         PIOB_KIDR;     // Keypad Controller Interrupt Disable Register\r
+       AT91_REG         PIOB_KIMR;     // Keypad Controller Interrupt Mask Register\r
+       AT91_REG         PIOB_KSR;      // Keypad Controller Status Register\r
+       AT91_REG         PIOB_KKPR;     // Keypad Controller Key Press Register\r
+       AT91_REG         PIOB_KKRR;     // Keypad Controller Key Release Register\r
+       AT91_REG         Reserved47[46];        // \r
+       AT91_REG         PIOC_PER;      // PIO Enable Register\r
+       AT91_REG         PIOC_PDR;      // PIO Disable Register\r
+       AT91_REG         PIOC_PSR;      // PIO Status Register\r
+       AT91_REG         Reserved48[1];         // \r
+       AT91_REG         PIOC_OER;      // Output Enable Register\r
+       AT91_REG         PIOC_ODR;      // Output Disable Registerr\r
+       AT91_REG         PIOC_OSR;      // Output Status Register\r
+       AT91_REG         Reserved49[1];         // \r
+       AT91_REG         PIOC_IFER;     // Input Filter Enable Register\r
+       AT91_REG         PIOC_IFDR;     // Input Filter Disable Register\r
+       AT91_REG         PIOC_IFSR;     // Input Filter Status Register\r
+       AT91_REG         Reserved50[1];         // \r
+       AT91_REG         PIOC_SODR;     // Set Output Data Register\r
+       AT91_REG         PIOC_CODR;     // Clear Output Data Register\r
+       AT91_REG         PIOC_ODSR;     // Output Data Status Register\r
+       AT91_REG         PIOC_PDSR;     // Pin Data Status Register\r
+       AT91_REG         PIOC_IER;      // Interrupt Enable Register\r
+       AT91_REG         PIOC_IDR;      // Interrupt Disable Register\r
+       AT91_REG         PIOC_IMR;      // Interrupt Mask Register\r
+       AT91_REG         PIOC_ISR;      // Interrupt Status Register\r
+       AT91_REG         PIOC_MDER;     // Multi-driver Enable Register\r
+       AT91_REG         PIOC_MDDR;     // Multi-driver Disable Register\r
+       AT91_REG         PIOC_MDSR;     // Multi-driver Status Register\r
+       AT91_REG         Reserved51[1];         // \r
+       AT91_REG         PIOC_PPUDR;    // Pull-up Disable Register\r
+       AT91_REG         PIOC_PPUER;    // Pull-up Enable Register\r
+       AT91_REG         PIOC_PPUSR;    // Pull-up Status Register\r
+       AT91_REG         Reserved52[1];         // \r
+       AT91_REG         PIOC_ABSR;     // Peripheral AB Select Register\r
+       AT91_REG         Reserved53[3];         // \r
+       AT91_REG         PIOC_SCIFSR;   // System Clock Glitch Input Filter Select Register\r
+       AT91_REG         PIOC_DIFSR;    // Debouncing Input Filter Select Register\r
+       AT91_REG         PIOC_IFDGSR;   // Glitch or Debouncing Input Filter Clock Selection Status Register\r
+       AT91_REG         PIOC_SCDR;     // Slow Clock Divider Debouncing Register\r
+       AT91_REG         Reserved54[4];         // \r
+       AT91_REG         PIOC_OWER;     // Output Write Enable Register\r
+       AT91_REG         PIOC_OWDR;     // Output Write Disable Register\r
+       AT91_REG         PIOC_OWSR;     // Output Write Status Register\r
+       AT91_REG         Reserved55[1];         // \r
+       AT91_REG         PIOC_AIMER;    // Additional Interrupt Modes Enable Register\r
+       AT91_REG         PIOC_AIMDR;    // Additional Interrupt Modes Disables Register\r
+       AT91_REG         PIOC_AIMMR;    // Additional Interrupt Modes Mask Register\r
+       AT91_REG         Reserved56[1];         // \r
+       AT91_REG         PIOC_ESR;      // Edge Select Register\r
+       AT91_REG         PIOC_LSR;      // Level Select Register\r
+       AT91_REG         PIOC_ELSR;     // Edge/Level Status Register\r
+       AT91_REG         Reserved57[1];         // \r
+       AT91_REG         PIOC_FELLSR;   // Falling Edge/Low Level Select Register\r
+       AT91_REG         PIOC_REHLSR;   // Rising Edge/ High Level Select Register\r
+       AT91_REG         PIOC_FRLHSR;   // Fall/Rise - Low/High Status Register\r
+       AT91_REG         Reserved58[1];         // \r
+       AT91_REG         PIOC_LOCKSR;   // Lock Status Register\r
+       AT91_REG         Reserved59[6];         // \r
+       AT91_REG         PIOC_VER;      // PIO VERSION REGISTER \r
+       AT91_REG         Reserved60[8];         // \r
+       AT91_REG         PIOC_KER;      // Keypad Controller Enable Register\r
+       AT91_REG         PIOC_KRCR;     // Keypad Controller Row Column Register\r
+       AT91_REG         PIOC_KDR;      // Keypad Controller Debouncing Register\r
+       AT91_REG         Reserved61[1];         // \r
+       AT91_REG         PIOC_KIER;     // Keypad Controller Interrupt Enable Register\r
+       AT91_REG         PIOC_KIDR;     // Keypad Controller Interrupt Disable Register\r
+       AT91_REG         PIOC_KIMR;     // Keypad Controller Interrupt Mask Register\r
+       AT91_REG         PIOC_KSR;      // Keypad Controller Status Register\r
+       AT91_REG         PIOC_KKPR;     // Keypad Controller Key Press Register\r
+       AT91_REG         PIOC_KKRR;     // Keypad Controller Key Release Register\r
+       AT91_REG         Reserved62[46];        // \r
+       AT91_REG         RSTC_RCR;      // Reset Control Register\r
+       AT91_REG         RSTC_RSR;      // Reset Status Register\r
+       AT91_REG         RSTC_RMR;      // Reset Mode Register\r
+       AT91_REG         Reserved63[1];         // \r
+       AT91_REG         SUPC_CR;       // Control Register\r
+       AT91_REG         SUPC_BOMR;     // Brown Out Mode Register\r
+       AT91_REG         SUPC_MR;       // Mode Register\r
+       AT91_REG         SUPC_WUMR;     // Wake Up Mode Register\r
+       AT91_REG         SUPC_WUIR;     // Wake Up Inputs Register\r
+       AT91_REG         SUPC_SR;       // Status Register\r
+       AT91_REG         SUPC_FWUTR;    // Flash Wake-up Timer Register\r
+       AT91_REG         Reserved64[1];         // \r
+       AT91_REG         RTTC_RTMR;     // Real-time Mode Register\r
+       AT91_REG         RTTC_RTAR;     // Real-time Alarm Register\r
+       AT91_REG         RTTC_RTVR;     // Real-time Value Register\r
+       AT91_REG         RTTC_RTSR;     // Real-time Status Register\r
+       AT91_REG         Reserved65[4];         // \r
+       AT91_REG         WDTC_WDCR;     // Watchdog Control Register\r
+       AT91_REG         WDTC_WDMR;     // Watchdog Mode Register\r
+       AT91_REG         WDTC_WDSR;     // Watchdog Status Register\r
+       AT91_REG         Reserved66[1];         // \r
+       AT91_REG         RTC_CR;        // Control Register\r
+       AT91_REG         RTC_MR;        // Mode Register\r
+       AT91_REG         RTC_TIMR;      // Time Register\r
+       AT91_REG         RTC_CALR;      // Calendar Register\r
+       AT91_REG         RTC_TIMALR;    // Time Alarm Register\r
+       AT91_REG         RTC_CALALR;    // Calendar Alarm Register\r
+       AT91_REG         RTC_SR;        // Status Register\r
+       AT91_REG         RTC_SCCR;      // Status Clear Command Register\r
+       AT91_REG         RTC_IER;       // Interrupt Enable Register\r
+       AT91_REG         RTC_IDR;       // Interrupt Disable Register\r
+       AT91_REG         RTC_IMR;       // Interrupt Mask Register\r
+       AT91_REG         RTC_VER;       // Valid Entry Register\r
+       AT91_REG         SYS_GPBR[8];   // General Purpose Register\r
+       AT91_REG         Reserved67[19];        // \r
+       AT91_REG         RSTC_VER;      // Version Register\r
+} AT91S_SYS, *AT91PS_SYS;\r
+#else\r
+#define GPBR            (AT91_CAST(AT91_REG *)         0x00001290) // (GPBR) General Purpose Register\r
+\r
+#endif\r
+// -------- GPBR : (SYS Offset: 0x1290) GPBR General Purpose Register -------- \r
+#define AT91C_GPBR_GPRV       (0x0 <<  0) // (SYS) General Purpose Register Value\r
+\r
+// *****************************************************************************\r
+//              SOFTWARE API DEFINITION  FOR HSMC4 Chip Select interface\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_HSMC4_CS {\r
+       AT91_REG         HSMC4_SETUP;   // Setup Register\r
+       AT91_REG         HSMC4_PULSE;   // Pulse Register\r
+       AT91_REG         HSMC4_CYCLE;   // Cycle Register\r
+       AT91_REG         HSMC4_TIMINGS;         // Timmings Register\r
+       AT91_REG         HSMC4_MODE;    // Mode Register\r
+} AT91S_HSMC4_CS, *AT91PS_HSMC4_CS;\r
+#else\r
+#define HSMC4_SETUP     (AT91_CAST(AT91_REG *)         0x00000000) // (HSMC4_SETUP) Setup Register\r
+#define HSMC4_PULSE     (AT91_CAST(AT91_REG *)         0x00000004) // (HSMC4_PULSE) Pulse Register\r
+#define HSMC4_CYCLE     (AT91_CAST(AT91_REG *)         0x00000008) // (HSMC4_CYCLE) Cycle Register\r
+#define HSMC4_TIMINGS   (AT91_CAST(AT91_REG *)         0x0000000C) // (HSMC4_TIMINGS) Timmings Register\r
+#define HSMC4_MODE      (AT91_CAST(AT91_REG *)         0x00000010) // (HSMC4_MODE) Mode Register\r
+\r
+#endif\r
+// -------- HSMC4_SETUP : (HSMC4_CS Offset: 0x0) HSMC4 SETUP -------- \r
+#define AT91C_HSMC4_NWE_SETUP (0x3F <<  0) // (HSMC4_CS) NWE Setup length\r
+#define AT91C_HSMC4_NCS_WR_SETUP (0x3F <<  8) // (HSMC4_CS) NCS Setup length in Write access\r
+#define AT91C_HSMC4_NRD_SETUP (0x3F << 16) // (HSMC4_CS) NRD Setup length\r
+#define AT91C_HSMC4_NCS_RD_SETUP (0x3F << 24) // (HSMC4_CS) NCS Setup legnth in Read access\r
+// -------- HSMC4_PULSE : (HSMC4_CS Offset: 0x4) HSMC4 PULSE -------- \r
+#define AT91C_HSMC4_NWE_PULSE (0x3F <<  0) // (HSMC4_CS) NWE Pulse Length\r
+#define AT91C_HSMC4_NCS_WR_PULSE (0x3F <<  8) // (HSMC4_CS) NCS Pulse length in WRITE access\r
+#define AT91C_HSMC4_NRD_PULSE (0x3F << 16) // (HSMC4_CS) NRD Pulse length\r
+#define AT91C_HSMC4_NCS_RD_PULSE (0x3F << 24) // (HSMC4_CS) NCS Pulse length in READ access\r
+// -------- HSMC4_CYCLE : (HSMC4_CS Offset: 0x8) HSMC4 CYCLE -------- \r
+#define AT91C_HSMC4_NWE_CYCLE (0x1FF <<  0) // (HSMC4_CS) Total Write Cycle Length\r
+#define AT91C_HSMC4_NRD_CYCLE (0x1FF << 16) // (HSMC4_CS) Total Read Cycle Length\r
+// -------- HSMC4_TIMINGS : (HSMC4_CS Offset: 0xc) HSMC4 TIMINGS -------- \r
+#define AT91C_HSMC4_TCLR      (0xF <<  0) // (HSMC4_CS) CLE to REN low delay\r
+#define AT91C_HSMC4_TADL      (0xF <<  4) // (HSMC4_CS) ALE to data start\r
+#define AT91C_HSMC4_TAR       (0xF <<  8) // (HSMC4_CS) ALE to REN low delay\r
+#define AT91C_HSMC4_OCMSEN    (0x1 << 12) // (HSMC4_CS) Off Chip Memory Scrambling Enable\r
+#define AT91C_HSMC4_TRR       (0xF << 16) // (HSMC4_CS) Ready to REN low delay\r
+#define AT91C_HSMC4_TWB       (0xF << 24) // (HSMC4_CS) WEN high to REN to busy\r
+#define AT91C_HSMC4_RBNSEL    (0x7 << 28) // (HSMC4_CS) Ready/Busy Line Selection\r
+#define AT91C_HSMC4_NFSEL     (0x1 << 31) // (HSMC4_CS) Nand Flash Selection\r
+// -------- HSMC4_MODE : (HSMC4_CS Offset: 0x10) HSMC4 MODE -------- \r
+#define AT91C_HSMC4_READ_MODE (0x1 <<  0) // (HSMC4_CS) Read Mode\r
+#define AT91C_HSMC4_WRITE_MODE (0x1 <<  1) // (HSMC4_CS) Write Mode\r
+#define AT91C_HSMC4_EXNW_MODE (0x3 <<  4) // (HSMC4_CS) NWAIT Mode\r
+#define        AT91C_HSMC4_EXNW_MODE_NWAIT_DISABLE        (0x0 <<  4) // (HSMC4_CS) External NWAIT disabled.\r
+#define        AT91C_HSMC4_EXNW_MODE_NWAIT_ENABLE_FROZEN  (0x2 <<  4) // (HSMC4_CS) External NWAIT enabled in frozen mode.\r
+#define        AT91C_HSMC4_EXNW_MODE_NWAIT_ENABLE_READY   (0x3 <<  4) // (HSMC4_CS) External NWAIT enabled in ready mode.\r
+#define AT91C_HSMC4_BAT       (0x1 <<  8) // (HSMC4_CS) Byte Access Type\r
+#define        AT91C_HSMC4_BAT_BYTE_SELECT          (0x0 <<  8) // (HSMC4_CS) Write controled by ncs, nbs0, nbs1, nbs2, nbs3. Read controled by ncs, nrd, nbs0, nbs1, nbs2, nbs3.\r
+#define        AT91C_HSMC4_BAT_BYTE_WRITE           (0x1 <<  8) // (HSMC4_CS) Write controled by ncs, nwe0, nwe1, nwe2, nwe3. Read controled by ncs and nrd.\r
+#define AT91C_HSMC4_DBW       (0x3 << 12) // (HSMC4_CS) Data Bus Width\r
+#define        AT91C_HSMC4_DBW_WIDTH_EIGTH_BITS     (0x0 << 12) // (HSMC4_CS) 8 bits.\r
+#define        AT91C_HSMC4_DBW_WIDTH_SIXTEEN_BITS   (0x1 << 12) // (HSMC4_CS) 16 bits.\r
+#define        AT91C_HSMC4_DBW_WIDTH_THIRTY_TWO_BITS (0x2 << 12) // (HSMC4_CS) 32 bits.\r
+#define AT91C_HSMC4_TDF_CYCLES (0xF << 16) // (HSMC4_CS) Data Float Time.\r
+#define AT91C_HSMC4_TDF_MODE  (0x1 << 20) // (HSMC4_CS) TDF Enabled.\r
+#define AT91C_HSMC4_PMEN      (0x1 << 24) // (HSMC4_CS) Page Mode Enabled.\r
+#define AT91C_HSMC4_PS        (0x3 << 28) // (HSMC4_CS) Page Size\r
+#define        AT91C_HSMC4_PS_SIZE_FOUR_BYTES      (0x0 << 28) // (HSMC4_CS) 4 bytes.\r
+#define        AT91C_HSMC4_PS_SIZE_EIGHT_BYTES     (0x1 << 28) // (HSMC4_CS) 8 bytes.\r
+#define        AT91C_HSMC4_PS_SIZE_SIXTEEN_BYTES   (0x2 << 28) // (HSMC4_CS) 16 bytes.\r
+#define        AT91C_HSMC4_PS_SIZE_THIRTY_TWO_BYTES (0x3 << 28) // (HSMC4_CS) 32 bytes.\r
+\r
+// *****************************************************************************\r
+//              SOFTWARE API DEFINITION  FOR AHB Static Memory Controller 4 Interface\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_HSMC4 {\r
+       AT91_REG         HSMC4_CFG;     // Configuration Register\r
+       AT91_REG         HSMC4_CTRL;    // Control Register\r
+       AT91_REG         HSMC4_SR;      // Status Register\r
+       AT91_REG         HSMC4_IER;     // Interrupt Enable Register\r
+       AT91_REG         HSMC4_IDR;     // Interrupt Disable Register\r
+       AT91_REG         HSMC4_IMR;     // Interrupt Mask Register\r
+       AT91_REG         HSMC4_ADDR;    // Address Cycle Zero Register\r
+       AT91_REG         HSMC4_BANK;    // Bank Register\r
+       AT91_REG         HSMC4_ECCCR;   // ECC reset register\r
+       AT91_REG         HSMC4_ECCCMD;  // ECC Page size register\r
+       AT91_REG         HSMC4_ECCSR1;  // ECC Status register 1\r
+       AT91_REG         HSMC4_ECCPR0;  // ECC Parity register 0\r
+       AT91_REG         HSMC4_ECCPR1;  // ECC Parity register 1\r
+       AT91_REG         HSMC4_ECCSR2;  // ECC Status register 2\r
+       AT91_REG         HSMC4_ECCPR2;  // ECC Parity register 2\r
+       AT91_REG         HSMC4_ECCPR3;  // ECC Parity register 3\r
+       AT91_REG         HSMC4_ECCPR4;  // ECC Parity register 4\r
+       AT91_REG         HSMC4_ECCPR5;  // ECC Parity register 5\r
+       AT91_REG         HSMC4_ECCPR6;  // ECC Parity register 6\r
+       AT91_REG         HSMC4_ECCPR7;  // ECC Parity register 7\r
+       AT91_REG         HSMC4_ECCPR8;  // ECC Parity register 8\r
+       AT91_REG         HSMC4_ECCPR9;  // ECC Parity register 9\r
+       AT91_REG         HSMC4_ECCPR10;         // ECC Parity register 10\r
+       AT91_REG         HSMC4_ECCPR11;         // ECC Parity register 11\r
+       AT91_REG         HSMC4_ECCPR12;         // ECC Parity register 12\r
+       AT91_REG         HSMC4_ECCPR13;         // ECC Parity register 13\r
+       AT91_REG         HSMC4_ECCPR14;         // ECC Parity register 14\r
+       AT91_REG         HSMC4_Eccpr15;         // ECC Parity register 15\r
+       AT91_REG         Reserved0[40];         // \r
+       AT91_REG         HSMC4_OCMS;    // OCMS MODE register\r
+       AT91_REG         HSMC4_KEY1;    // KEY1 Register\r
+       AT91_REG         HSMC4_KEY2;    // KEY2 Register\r
+       AT91_REG         Reserved1[50];         // \r
+       AT91_REG         HSMC4_WPCR;    // Write Protection Control register\r
+       AT91_REG         HSMC4_WPSR;    // Write Protection Status Register\r
+       AT91_REG         HSMC4_ADDRSIZE;        // Write Protection Status Register\r
+       AT91_REG         HSMC4_IPNAME1;         // Write Protection Status Register\r
+       AT91_REG         HSMC4_IPNAME2;         // Write Protection Status Register\r
+       AT91_REG         HSMC4_FEATURES;        // Write Protection Status Register\r
+       AT91_REG         HSMC4_VER;     // HSMC4 Version Register\r
+       AT91_REG         HSMC4_DUMMY;   // This rtegister was created only ti have AHB constants\r
+} AT91S_HSMC4, *AT91PS_HSMC4;\r
+#else\r
+#define HSMC4_CFG       (AT91_CAST(AT91_REG *)         0x00000000) // (HSMC4_CFG) Configuration Register\r
+#define HSMC4_CTRL      (AT91_CAST(AT91_REG *)         0x00000004) // (HSMC4_CTRL) Control Register\r
+#define HSMC4_SR        (AT91_CAST(AT91_REG *)         0x00000008) // (HSMC4_SR) Status Register\r
+#define HSMC4_IER       (AT91_CAST(AT91_REG *)         0x0000000C) // (HSMC4_IER) Interrupt Enable Register\r
+#define HSMC4_IDR       (AT91_CAST(AT91_REG *)         0x00000010) // (HSMC4_IDR) Interrupt Disable Register\r
+#define HSMC4_IMR       (AT91_CAST(AT91_REG *)         0x00000014) // (HSMC4_IMR) Interrupt Mask Register\r
+#define HSMC4_ADDR      (AT91_CAST(AT91_REG *)         0x00000018) // (HSMC4_ADDR) Address Cycle Zero Register\r
+#define HSMC4_BANK      (AT91_CAST(AT91_REG *)         0x0000001C) // (HSMC4_BANK) Bank Register\r
+#define HSMC4_ECCCR     (AT91_CAST(AT91_REG *)         0x00000020) // (HSMC4_ECCCR) ECC reset register\r
+#define HSMC4_ECCCMD    (AT91_CAST(AT91_REG *)         0x00000024) // (HSMC4_ECCCMD) ECC Page size register\r
+#define HSMC4_ECCSR1    (AT91_CAST(AT91_REG *)         0x00000028) // (HSMC4_ECCSR1) ECC Status register 1\r
+#define HSMC4_ECCPR0    (AT91_CAST(AT91_REG *)         0x0000002C) // (HSMC4_ECCPR0) ECC Parity register 0\r
+#define HSMC4_ECCPR1    (AT91_CAST(AT91_REG *)         0x00000030) // (HSMC4_ECCPR1) ECC Parity register 1\r
+#define HSMC4_ECCSR2    (AT91_CAST(AT91_REG *)         0x00000034) // (HSMC4_ECCSR2) ECC Status register 2\r
+#define HSMC4_ECCPR2    (AT91_CAST(AT91_REG *)         0x00000038) // (HSMC4_ECCPR2) ECC Parity register 2\r
+#define HSMC4_ECCPR3    (AT91_CAST(AT91_REG *)         0x0000003C) // (HSMC4_ECCPR3) ECC Parity register 3\r
+#define HSMC4_ECCPR4    (AT91_CAST(AT91_REG *)         0x00000040) // (HSMC4_ECCPR4) ECC Parity register 4\r
+#define HSMC4_ECCPR5    (AT91_CAST(AT91_REG *)         0x00000044) // (HSMC4_ECCPR5) ECC Parity register 5\r
+#define HSMC4_ECCPR6    (AT91_CAST(AT91_REG *)         0x00000048) // (HSMC4_ECCPR6) ECC Parity register 6\r
+#define HSMC4_ECCPR7    (AT91_CAST(AT91_REG *)         0x0000004C) // (HSMC4_ECCPR7) ECC Parity register 7\r
+#define HSMC4_ECCPR8    (AT91_CAST(AT91_REG *)         0x00000050) // (HSMC4_ECCPR8) ECC Parity register 8\r
+#define HSMC4_ECCPR9    (AT91_CAST(AT91_REG *)         0x00000054) // (HSMC4_ECCPR9) ECC Parity register 9\r
+#define HSMC4_ECCPR10   (AT91_CAST(AT91_REG *)         0x00000058) // (HSMC4_ECCPR10) ECC Parity register 10\r
+#define HSMC4_ECCPR11   (AT91_CAST(AT91_REG *)         0x0000005C) // (HSMC4_ECCPR11) ECC Parity register 11\r
+#define HSMC4_ECCPR12   (AT91_CAST(AT91_REG *)         0x00000060) // (HSMC4_ECCPR12) ECC Parity register 12\r
+#define HSMC4_ECCPR13   (AT91_CAST(AT91_REG *)         0x00000064) // (HSMC4_ECCPR13) ECC Parity register 13\r
+#define HSMC4_ECCPR14   (AT91_CAST(AT91_REG *)         0x00000068) // (HSMC4_ECCPR14) ECC Parity register 14\r
+#define Hsmc4_Eccpr15   (AT91_CAST(AT91_REG *)         0x0000006C) // (Hsmc4_Eccpr15) ECC Parity register 15\r
+#define HSMC4_OCMS      (AT91_CAST(AT91_REG *)         0x00000110) // (HSMC4_OCMS) OCMS MODE register\r
+#define HSMC4_KEY1      (AT91_CAST(AT91_REG *)         0x00000114) // (HSMC4_KEY1) KEY1 Register\r
+#define HSMC4_KEY2      (AT91_CAST(AT91_REG *)         0x00000118) // (HSMC4_KEY2) KEY2 Register\r
+#define HSMC4_WPCR      (AT91_CAST(AT91_REG *)         0x000001E4) // (HSMC4_WPCR) Write Protection Control register\r
+#define HSMC4_WPSR      (AT91_CAST(AT91_REG *)         0x000001E8) // (HSMC4_WPSR) Write Protection Status Register\r
+#define HSMC4_ADDRSIZE  (AT91_CAST(AT91_REG *)         0x000001EC) // (HSMC4_ADDRSIZE) Write Protection Status Register\r
+#define HSMC4_IPNAME1   (AT91_CAST(AT91_REG *)         0x000001F0) // (HSMC4_IPNAME1) Write Protection Status Register\r
+#define HSMC4_IPNAME2   (AT91_CAST(AT91_REG *)         0x000001F4) // (HSMC4_IPNAME2) Write Protection Status Register\r
+#define HSMC4_FEATURES  (AT91_CAST(AT91_REG *)         0x000001F8) // (HSMC4_FEATURES) Write Protection Status Register\r
+#define HSMC4_VER       (AT91_CAST(AT91_REG *)         0x000001FC) // (HSMC4_VER) HSMC4 Version Register\r
+#define HSMC4_DUMMY     (AT91_CAST(AT91_REG *)         0x00000200) // (HSMC4_DUMMY) This rtegister was created only ti have AHB constants\r
+\r
+#endif\r
+// -------- HSMC4_CFG : (HSMC4 Offset: 0x0) Configuration Register -------- \r
+#define AT91C_HSMC4_PAGESIZE  (0x3 <<  0) // (HSMC4) PAGESIZE field description\r
+#define        AT91C_HSMC4_PAGESIZE_528_Bytes            (0x0) // (HSMC4) 512 bytes plus 16 bytes page size\r
+#define        AT91C_HSMC4_PAGESIZE_1056_Bytes           (0x1) // (HSMC4) 1024 bytes plus 32 bytes page size\r
+#define        AT91C_HSMC4_PAGESIZE_2112_Bytes           (0x2) // (HSMC4) 2048 bytes plus 64 bytes page size\r
+#define        AT91C_HSMC4_PAGESIZE_4224_Bytes           (0x3) // (HSMC4) 4096 bytes plus 128 bytes page size\r
+#define AT91C_HSMC4_WSPARE    (0x1 <<  8) // (HSMC4) Spare area access in Write Mode\r
+#define AT91C_HSMC4_RSPARE    (0x1 <<  9) // (HSMC4) Spare area access in Read Mode\r
+#define AT91C_HSMC4_EDGECTRL  (0x1 << 12) // (HSMC4) Rising/Falling Edge Detection Control\r
+#define AT91C_HSMC4_RBEDGE    (0x1 << 13) // (HSMC4) Ready/Busy Signal edge Detection\r
+#define AT91C_HSMC4_DTOCYC    (0xF << 16) // (HSMC4) Data Timeout Cycle Number\r
+#define AT91C_HSMC4_DTOMUL    (0x7 << 20) // (HSMC4) Data Timeout Multiplier\r
+#define        AT91C_HSMC4_DTOMUL_1                    (0x0 << 20) // (HSMC4) DTOCYC x 1\r
+#define        AT91C_HSMC4_DTOMUL_16                   (0x1 << 20) // (HSMC4) DTOCYC x 16\r
+#define        AT91C_HSMC4_DTOMUL_128                  (0x2 << 20) // (HSMC4) DTOCYC x 128\r
+#define        AT91C_HSMC4_DTOMUL_256                  (0x3 << 20) // (HSMC4) DTOCYC x 256\r
+#define        AT91C_HSMC4_DTOMUL_1024                 (0x4 << 20) // (HSMC4) DTOCYC x 1024\r
+#define        AT91C_HSMC4_DTOMUL_4096                 (0x5 << 20) // (HSMC4) DTOCYC x 4096\r
+#define        AT91C_HSMC4_DTOMUL_65536                (0x6 << 20) // (HSMC4) DTOCYC x 65536\r
+#define        AT91C_HSMC4_DTOMUL_1048576              (0x7 << 20) // (HSMC4) DTOCYC x 1048576\r
+// -------- HSMC4_CTRL : (HSMC4 Offset: 0x4) Control Register -------- \r
+#define AT91C_HSMC4_NFCEN     (0x1 <<  0) // (HSMC4) Nand Flash Controller Host Enable\r
+#define AT91C_HSMC4_NFCDIS    (0x1 <<  1) // (HSMC4) Nand Flash Controller Host Disable\r
+#define AT91C_HSMC4_HOSTEN    (0x1 <<  8) // (HSMC4) If set to one, the Host controller is activated and perform a data transfer phase.\r
+#define AT91C_HSMC4_HOSTWR    (0x1 << 11) // (HSMC4) If this field is set to one, the host transfers data from the internal SRAM to the Memory Device.\r
+#define AT91C_HSMC4_HOSTCSID  (0x7 << 12) // (HSMC4) Host Controller Chip select Id\r
+#define        AT91C_HSMC4_HOSTCSID_0                    (0x0 << 12) // (HSMC4) CS0\r
+#define        AT91C_HSMC4_HOSTCSID_1                    (0x1 << 12) // (HSMC4) CS1\r
+#define        AT91C_HSMC4_HOSTCSID_2                    (0x2 << 12) // (HSMC4) CS2\r
+#define        AT91C_HSMC4_HOSTCSID_3                    (0x3 << 12) // (HSMC4) CS3\r
+#define        AT91C_HSMC4_HOSTCSID_4                    (0x4 << 12) // (HSMC4) CS4\r
+#define        AT91C_HSMC4_HOSTCSID_5                    (0x5 << 12) // (HSMC4) CS5\r
+#define        AT91C_HSMC4_HOSTCSID_6                    (0x6 << 12) // (HSMC4) CS6\r
+#define        AT91C_HSMC4_HOSTCSID_7                    (0x7 << 12) // (HSMC4) CS7\r
+#define AT91C_HSMC4_VALID     (0x1 << 15) // (HSMC4) When set to 1, a write operation modifies both HOSTCSID and HOSTWR fields.\r
+// -------- HSMC4_SR : (HSMC4 Offset: 0x8) HSMC4 Status Register -------- \r
+#define AT91C_HSMC4_NFCSTS    (0x1 <<  0) // (HSMC4) Nand Flash Controller status\r
+#define AT91C_HSMC4_RBRISE    (0x1 <<  4) // (HSMC4) Selected Ready Busy Rising Edge Detected flag\r
+#define AT91C_HSMC4_RBFALL    (0x1 <<  5) // (HSMC4) Selected Ready Busy Falling Edge Detected flag\r
+#define AT91C_HSMC4_HOSTBUSY  (0x1 <<  8) // (HSMC4) Host Busy\r
+#define AT91C_HSMC4_HOSTW     (0x1 << 11) // (HSMC4) Host Write/Read Operation\r
+#define AT91C_HSMC4_HOSTCS    (0x7 << 12) // (HSMC4) Host Controller Chip select Id\r
+#define        AT91C_HSMC4_HOSTCS_0                    (0x0 << 12) // (HSMC4) CS0\r
+#define        AT91C_HSMC4_HOSTCS_1                    (0x1 << 12) // (HSMC4) CS1\r
+#define        AT91C_HSMC4_HOSTCS_2                    (0x2 << 12) // (HSMC4) CS2\r
+#define        AT91C_HSMC4_HOSTCS_3                    (0x3 << 12) // (HSMC4) CS3\r
+#define        AT91C_HSMC4_HOSTCS_4                    (0x4 << 12) // (HSMC4) CS4\r
+#define        AT91C_HSMC4_HOSTCS_5                    (0x5 << 12) // (HSMC4) CS5\r
+#define        AT91C_HSMC4_HOSTCS_6                    (0x6 << 12) // (HSMC4) CS6\r
+#define        AT91C_HSMC4_HOSTCS_7                    (0x7 << 12) // (HSMC4) CS7\r
+#define AT91C_HSMC4_XFRDONE   (0x1 << 16) // (HSMC4) Host Data Transfer Terminated\r
+#define AT91C_HSMC4_CMDDONE   (0x1 << 17) // (HSMC4) Command Done\r
+#define AT91C_HSMC4_ECCRDY    (0x1 << 18) // (HSMC4) ECC ready\r
+#define AT91C_HSMC4_DTOE      (0x1 << 20) // (HSMC4) Data timeout Error\r
+#define AT91C_HSMC4_UNDEF     (0x1 << 21) // (HSMC4) Undefined Area Error\r
+#define AT91C_HSMC4_AWB       (0x1 << 22) // (HSMC4) Accessing While Busy Error\r
+#define AT91C_HSMC4_HASE      (0x1 << 23) // (HSMC4) Host Controller Access Size Error\r
+#define AT91C_HSMC4_RBEDGE0   (0x1 << 24) // (HSMC4) Ready Busy line 0 Edge detected\r
+#define AT91C_HSMC4_RBEDGE1   (0x1 << 25) // (HSMC4) Ready Busy line 1 Edge detected\r
+#define AT91C_HSMC4_RBEDGE2   (0x1 << 26) // (HSMC4) Ready Busy line 2 Edge detected\r
+#define AT91C_HSMC4_RBEDGE3   (0x1 << 27) // (HSMC4) Ready Busy line 3 Edge detected\r
+#define AT91C_HSMC4_RBEDGE4   (0x1 << 28) // (HSMC4) Ready Busy line 4 Edge detected\r
+#define AT91C_HSMC4_RBEDGE5   (0x1 << 29) // (HSMC4) Ready Busy line 5 Edge detected\r
+#define AT91C_HSMC4_RBEDGE6   (0x1 << 30) // (HSMC4) Ready Busy line 6 Edge detected\r
+#define AT91C_HSMC4_RBEDGE7   (0x1 << 31) // (HSMC4) Ready Busy line 7 Edge detected\r
+// -------- HSMC4_IER : (HSMC4 Offset: 0xc) HSMC4 Interrupt Enable Register -------- \r
+// -------- HSMC4_IDR : (HSMC4 Offset: 0x10) HSMC4 Interrupt Disable Register -------- \r
+// -------- HSMC4_IMR : (HSMC4 Offset: 0x14) HSMC4 Interrupt Mask Register -------- \r
+// -------- HSMC4_ADDR : (HSMC4 Offset: 0x18) Address Cycle Zero Register -------- \r
+#define AT91C_HSMC4_ADDRCYCLE0 (0xFF <<  0) // (HSMC4) Nand Flash Array Address cycle 0\r
+// -------- HSMC4_BANK : (HSMC4 Offset: 0x1c) Bank Register -------- \r
+#define AT91C_BANK            (0x7 <<  0) // (HSMC4) Bank identifier\r
+#define        AT91C_BANK_0                    (0x0) // (HSMC4) BANK0\r
+#define        AT91C_BANK_1                    (0x1) // (HSMC4) BANK1\r
+#define        AT91C_BANK_2                    (0x2) // (HSMC4) BANK2\r
+#define        AT91C_BANK_3                    (0x3) // (HSMC4) BANK3\r
+#define        AT91C_BANK_4                    (0x4) // (HSMC4) BANK4\r
+#define        AT91C_BANK_5                    (0x5) // (HSMC4) BANK5\r
+#define        AT91C_BANK_6                    (0x6) // (HSMC4) BANK6\r
+#define        AT91C_BANK_7                    (0x7) // (HSMC4) BANK7\r
+// -------- HSMC4_ECCCR : (HSMC4 Offset: 0x20) ECC Control Register -------- \r
+#define AT91C_HSMC4_ECCRESET  (0x1 <<  0) // (HSMC4) Reset ECC\r
+// -------- HSMC4_ECCCMD : (HSMC4 Offset: 0x24) ECC mode register -------- \r
+#define AT91C_ECC_PAGE_SIZE   (0x3 <<  0) // (HSMC4) Nand Flash page size\r
+#define AT91C_ECC_TYPCORRECT  (0x3 <<  4) // (HSMC4) Nand Flash page size\r
+#define        AT91C_ECC_TYPCORRECT_ONE_PER_PAGE         (0x0 <<  4) // (HSMC4) \r
+#define        AT91C_ECC_TYPCORRECT_ONE_EVERY_256_BYTES  (0x1 <<  4) // (HSMC4) \r
+#define        AT91C_ECC_TYPCORRECT_ONE_EVERY_512_BYTES  (0x2 <<  4) // (HSMC4) \r
+// -------- HSMC4_ECCSR1 : (HSMC4 Offset: 0x28) ECC Status Register 1 -------- \r
+#define AT91C_HSMC4_ECC_RECERR0 (0x1 <<  0) // (HSMC4) Recoverable Error\r
+#define AT91C_HSMC4_ECC_ECCERR0 (0x1 <<  1) // (HSMC4) ECC Error\r
+#define AT91C_HSMC4_ECC_MULERR0 (0x1 <<  2) // (HSMC4) Multiple Error\r
+#define AT91C_HSMC4_ECC_RECERR1 (0x1 <<  4) // (HSMC4) Recoverable Error\r
+#define AT91C_HSMC4_ECC_ECCERR1 (0x1 <<  5) // (HSMC4) ECC Error\r
+#define AT91C_HSMC4_ECC_MULERR1 (0x1 <<  6) // (HSMC4) Multiple Error\r
+#define AT91C_HSMC4_ECC_RECERR2 (0x1 <<  8) // (HSMC4) Recoverable Error\r
+#define AT91C_HSMC4_ECC_ECCERR2 (0x1 <<  9) // (HSMC4) ECC Error\r
+#define AT91C_HSMC4_ECC_MULERR2 (0x1 << 10) // (HSMC4) Multiple Error\r
+#define AT91C_HSMC4_ECC_RECERR3 (0x1 << 12) // (HSMC4) Recoverable Error\r
+#define AT91C_HSMC4_ECC_ECCERR3 (0x1 << 13) // (HSMC4) ECC Error\r
+#define AT91C_HSMC4_ECC_MULERR3 (0x1 << 14) // (HSMC4) Multiple Error\r
+#define AT91C_HSMC4_ECC_RECERR4 (0x1 << 16) // (HSMC4) Recoverable Error\r
+#define AT91C_HSMC4_ECC_ECCERR4 (0x1 << 17) // (HSMC4) ECC Error\r
+#define AT91C_HSMC4_ECC_MULERR4 (0x1 << 18) // (HSMC4) Multiple Error\r
+#define AT91C_HSMC4_ECC_RECERR5 (0x1 << 20) // (HSMC4) Recoverable Error\r
+#define AT91C_HSMC4_ECC_ECCERR5 (0x1 << 21) // (HSMC4) ECC Error\r
+#define AT91C_HSMC4_ECC_MULERR5 (0x1 << 22) // (HSMC4) Multiple Error\r
+#define AT91C_HSMC4_ECC_RECERR6 (0x1 << 24) // (HSMC4) Recoverable Error\r
+#define AT91C_HSMC4_ECC_ECCERR6 (0x1 << 25) // (HSMC4) ECC Error\r
+#define AT91C_HSMC4_ECC_MULERR6 (0x1 << 26) // (HSMC4) Multiple Error\r
+#define AT91C_HSMC4_ECC_RECERR7 (0x1 << 28) // (HSMC4) Recoverable Error\r
+#define AT91C_HSMC4_ECC_ECCERR7 (0x1 << 29) // (HSMC4) ECC Error\r
+#define AT91C_HSMC4_ECC_MULERR7 (0x1 << 30) // (HSMC4) Multiple Error\r
+// -------- HSMC4_ECCPR0 : (HSMC4 Offset: 0x2c) HSMC4 ECC parity Register 0 -------- \r
+#define AT91C_HSMC4_ECC_BITADDR (0x7 <<  0) // (HSMC4) Corrupted Bit Address in the page\r
+#define AT91C_HSMC4_ECC_WORDADDR (0xFF <<  3) // (HSMC4) Corrupted Word Address in the page\r
+#define AT91C_HSMC4_ECC_NPARITY (0x7FF << 12) // (HSMC4) Parity N\r
+// -------- HSMC4_ECCPR1 : (HSMC4 Offset: 0x30) HSMC4 ECC parity Register 1 -------- \r
+// -------- HSMC4_ECCSR2 : (HSMC4 Offset: 0x34) ECC Status Register 2 -------- \r
+#define AT91C_HSMC4_ECC_RECERR8 (0x1 <<  0) // (HSMC4) Recoverable Error\r
+#define AT91C_HSMC4_ECC_ECCERR8 (0x1 <<  1) // (HSMC4) ECC Error\r
+#define AT91C_HSMC4_ECC_MULERR8 (0x1 <<  2) // (HSMC4) Multiple Error\r
+#define AT91C_HSMC4_ECC_RECERR9 (0x1 <<  4) // (HSMC4) Recoverable Error\r
+#define AT91C_HSMC4_ECC_ECCERR9 (0x1 <<  5) // (HSMC4) ECC Error\r
+#define AT91C_HSMC4_ECC_MULERR9 (0x1 <<  6) // (HSMC4) Multiple Error\r
+#define AT91C_HSMC4_ECC_RECERR10 (0x1 <<  8) // (HSMC4) Recoverable Error\r
+#define AT91C_HSMC4_ECC_ECCERR10 (0x1 <<  9) // (HSMC4) ECC Error\r
+#define AT91C_HSMC4_ECC_MULERR10 (0x1 << 10) // (HSMC4) Multiple Error\r
+#define AT91C_HSMC4_ECC_RECERR11 (0x1 << 12) // (HSMC4) Recoverable Error\r
+#define AT91C_HSMC4_ECC_ECCERR11 (0x1 << 13) // (HSMC4) ECC Error\r
+#define AT91C_HSMC4_ECC_MULERR11 (0x1 << 14) // (HSMC4) Multiple Error\r
+#define AT91C_HSMC4_ECC_RECERR12 (0x1 << 16) // (HSMC4) Recoverable Error\r
+#define AT91C_HSMC4_ECC_ECCERR12 (0x1 << 17) // (HSMC4) ECC Error\r
+#define AT91C_HSMC4_ECC_MULERR12 (0x1 << 18) // (HSMC4) Multiple Error\r
+#define AT91C_HSMC4_ECC_RECERR13 (0x1 << 20) // (HSMC4) Recoverable Error\r
+#define AT91C_HSMC4_ECC_ECCERR13 (0x1 << 21) // (HSMC4) ECC Error\r
+#define AT91C_HSMC4_ECC_MULERR13 (0x1 << 22) // (HSMC4) Multiple Error\r
+#define AT91C_HSMC4_ECC_RECERR14 (0x1 << 24) // (HSMC4) Recoverable Error\r
+#define AT91C_HSMC4_ECC_ECCERR14 (0x1 << 25) // (HSMC4) ECC Error\r
+#define AT91C_HSMC4_ECC_MULERR14 (0x1 << 26) // (HSMC4) Multiple Error\r
+#define AT91C_HSMC4_ECC_RECERR15 (0x1 << 28) // (HSMC4) Recoverable Error\r
+#define AT91C_HSMC4_ECC_ECCERR15 (0x1 << 29) // (HSMC4) ECC Error\r
+#define AT91C_HSMC4_ECC_MULERR15 (0x1 << 30) // (HSMC4) Multiple Error\r
+// -------- HSMC4_ECCPR2 : (HSMC4 Offset: 0x38) HSMC4 ECC parity Register 2 -------- \r
+// -------- HSMC4_ECCPR3 : (HSMC4 Offset: 0x3c) HSMC4 ECC parity Register 3 -------- \r
+// -------- HSMC4_ECCPR4 : (HSMC4 Offset: 0x40) HSMC4 ECC parity Register 4 -------- \r
+// -------- HSMC4_ECCPR5 : (HSMC4 Offset: 0x44) HSMC4 ECC parity Register 5 -------- \r
+// -------- HSMC4_ECCPR6 : (HSMC4 Offset: 0x48) HSMC4 ECC parity Register 6 -------- \r
+// -------- HSMC4_ECCPR7 : (HSMC4 Offset: 0x4c) HSMC4 ECC parity Register 7 -------- \r
+// -------- HSMC4_ECCPR8 : (HSMC4 Offset: 0x50) HSMC4 ECC parity Register 8 -------- \r
+// -------- HSMC4_ECCPR9 : (HSMC4 Offset: 0x54) HSMC4 ECC parity Register 9 -------- \r
+// -------- HSMC4_ECCPR10 : (HSMC4 Offset: 0x58) HSMC4 ECC parity Register 10 -------- \r
+// -------- HSMC4_ECCPR11 : (HSMC4 Offset: 0x5c) HSMC4 ECC parity Register 11 -------- \r
+// -------- HSMC4_ECCPR12 : (HSMC4 Offset: 0x60) HSMC4 ECC parity Register 12 -------- \r
+// -------- HSMC4_ECCPR13 : (HSMC4 Offset: 0x64) HSMC4 ECC parity Register 13 -------- \r
+// -------- HSMC4_ECCPR14 : (HSMC4 Offset: 0x68) HSMC4 ECC parity Register 14 -------- \r
+// -------- HSMC4_ECCPR15 : (HSMC4 Offset: 0x6c) HSMC4 ECC parity Register 15 -------- \r
+// -------- HSMC4_OCMS : (HSMC4 Offset: 0x110) HSMC4 OCMS Register -------- \r
+#define AT91C_HSMC4_OCMS_SRSE (0x1 <<  0) // (HSMC4) Static Memory Controller Scrambling Enable\r
+#define AT91C_HSMC4_OCMS_SMSE (0x1 <<  1) // (HSMC4) SRAM Scramling Enable\r
+// -------- HSMC4_KEY1 : (HSMC4 Offset: 0x114) HSMC4 OCMS KEY1 Register -------- \r
+#define AT91C_HSMC4_OCMS_KEY1 (0x0 <<  0) // (HSMC4) OCMS Key 2\r
+// -------- HSMC4_OCMS_KEY2 : (HSMC4 Offset: 0x118) HSMC4 OCMS KEY2 Register -------- \r
+#define AT91C_HSMC4_OCMS_KEY2 (0x0 <<  0) // (HSMC4) OCMS Key 2\r
+// -------- HSMC4_WPCR : (HSMC4 Offset: 0x1e4) HSMC4 Witre Protection Control Register -------- \r
+#define AT91C_HSMC4_WP_EN     (0x1 <<  0) // (HSMC4) Write Protection Enable\r
+#define AT91C_HSMC4_WP_KEY    (0xFFFFFF <<  8) // (HSMC4) Protection Password\r
+// -------- HSMC4_WPSR : (HSMC4 Offset: 0x1e8) HSMC4 WPSR Register -------- \r
+#define AT91C_HSMC4_WP_VS     (0xF <<  0) // (HSMC4) Write Protection Violation Status\r
+#define        AT91C_HSMC4_WP_VS_WP_VS0               (0x0) // (HSMC4) No write protection violation since the last read of this register\r
+#define        AT91C_HSMC4_WP_VS_WP_VS1               (0x1) // (HSMC4) write protection detected unauthorized attempt to write a control register had occured (since the last read)\r
+#define        AT91C_HSMC4_WP_VS_WP_VS2               (0x2) // (HSMC4) Software reset had been performed while write protection was enabled (since the last read)\r
+#define        AT91C_HSMC4_WP_VS_WP_VS3               (0x3) // (HSMC4) Both write protection violation and software reset with write protection enabled had occured since the last read\r
+#define AT91C_                (0x0 <<  8) // (HSMC4) \r
+// -------- HSMC4_VER : (HSMC4 Offset: 0x1fc) HSMC4 VERSION Register -------- \r
+// -------- HSMC4_DUMMY : (HSMC4 Offset: 0x200) HSMC4 DUMMY REGISTER -------- \r
+#define AT91C_HSMC4_CMD1      (0xFF <<  2) // (HSMC4) Command Register Value for Cycle 1\r
+#define AT91C_HSMC4_CMD2      (0xFF << 10) // (HSMC4) Command Register Value for Cycle 2\r
+#define AT91C_HSMC4_VCMD2     (0x1 << 18) // (HSMC4) Valid Cycle 2 Command\r
+#define AT91C_HSMC4_ACYCLE    (0x7 << 19) // (HSMC4) Number of Address required for the current command\r
+#define        AT91C_HSMC4_ACYCLE_HSMC4_ACYCLE_NONE    (0x0 << 19) // (HSMC4) No address cycle\r
+#define        AT91C_HSMC4_ACYCLE_HSMC4_ACYCLE_ONE     (0x1 << 19) // (HSMC4) One address cycle\r
+#define        AT91C_HSMC4_ACYCLE_HSMC4_ACYCLE_TWO     (0x2 << 19) // (HSMC4) Two address cycles\r
+#define        AT91C_HSMC4_ACYCLE_HSMC4_ACYCLE_THREE   (0x3 << 19) // (HSMC4) Three address cycles\r
+#define        AT91C_HSMC4_ACYCLE_HSMC4_ACYCLE_FOUR    (0x4 << 19) // (HSMC4) Four address cycles\r
+#define        AT91C_HSMC4_ACYCLE_HSMC4_ACYCLE_FIVE    (0x5 << 19) // (HSMC4) Five address cycles\r
+#define AT91C_HSMC4_CSID      (0x7 << 22) // (HSMC4) Chip Select Identifier\r
+#define        AT91C_HSMC4_CSID_0                    (0x0 << 22) // (HSMC4) CS0\r
+#define        AT91C_HSMC4_CSID_1                    (0x1 << 22) // (HSMC4) CS1\r
+#define        AT91C_HSMC4_CSID_2                    (0x2 << 22) // (HSMC4) CS2\r
+#define        AT91C_HSMC4_CSID_3                    (0x3 << 22) // (HSMC4) CS3\r
+#define        AT91C_HSMC4_CSID_4                    (0x4 << 22) // (HSMC4) CS4\r
+#define        AT91C_HSMC4_CSID_5                    (0x5 << 22) // (HSMC4) CS5\r
+#define        AT91C_HSMC4_CSID_6                    (0x6 << 22) // (HSMC4) CS6\r
+#define        AT91C_HSMC4_CSID_7                    (0x7 << 22) // (HSMC4) CS7\r
+#define AT91C_HSMC4_HOST_EN   (0x1 << 25) // (HSMC4) Host Main Controller Enable\r
+#define AT91C_HSMC4_HOST_WR   (0x1 << 26) // (HSMC4) HOSTWR : Host Main Controller Write Enable\r
+#define AT91C_HSMC4_HOSTCMD   (0x1 << 27) // (HSMC4) Host Command Enable\r
+\r
+// *****************************************************************************\r
+//              SOFTWARE API DEFINITION  FOR AHB Matrix2 Interface\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_HMATRIX2 {\r
+       AT91_REG         HMATRIX2_MCFG0;        //  Master Configuration Register 0 : ARM I and D\r
+       AT91_REG         HMATRIX2_MCFG1;        //  Master Configuration Register 1 : ARM S\r
+       AT91_REG         HMATRIX2_MCFG2;        //  Master Configuration Register 2\r
+       AT91_REG         HMATRIX2_MCFG3;        //  Master Configuration Register 3\r
+       AT91_REG         HMATRIX2_MCFG4;        //  Master Configuration Register 4\r
+       AT91_REG         HMATRIX2_MCFG5;        //  Master Configuration Register 5\r
+       AT91_REG         HMATRIX2_MCFG6;        //  Master Configuration Register 6\r
+       AT91_REG         HMATRIX2_MCFG7;        //  Master Configuration Register 7\r
+       AT91_REG         Reserved0[8];  // \r
+       AT91_REG         HMATRIX2_SCFG0;        //  Slave Configuration Register 0\r
+       AT91_REG         HMATRIX2_SCFG1;        //  Slave Configuration Register 1\r
+       AT91_REG         HMATRIX2_SCFG2;        //  Slave Configuration Register 2\r
+       AT91_REG         HMATRIX2_SCFG3;        //  Slave Configuration Register 3\r
+       AT91_REG         HMATRIX2_SCFG4;        //  Slave Configuration Register 4\r
+       AT91_REG         HMATRIX2_SCFG5;        //  Slave Configuration Register 5\r
+       AT91_REG         HMATRIX2_SCFG6;        //  Slave Configuration Register 6\r
+       AT91_REG         HMATRIX2_SCFG7;        //  Slave Configuration Register 5\r
+       AT91_REG         HMATRIX2_SCFG8;        //  Slave Configuration Register 8\r
+       AT91_REG         Reserved1[43];         // \r
+       AT91_REG         HMATRIX2_SFR0 ;        //  Special Function Register 0\r
+       AT91_REG         HMATRIX2_SFR1 ;        //  Special Function Register 1\r
+       AT91_REG         HMATRIX2_SFR2 ;        //  Special Function Register 2\r
+       AT91_REG         HMATRIX2_SFR3 ;        //  Special Function Register 3\r
+       AT91_REG         HMATRIX2_SFR4 ;        //  Special Function Register 4\r
+       AT91_REG         HMATRIX2_SFR5 ;        //  Special Function Register 5\r
+       AT91_REG         HMATRIX2_SFR6 ;        //  Special Function Register 6\r
+       AT91_REG         HMATRIX2_SFR7 ;        //  Special Function Register 7\r
+       AT91_REG         HMATRIX2_SFR8 ;        //  Special Function Register 8\r
+       AT91_REG         HMATRIX2_SFR9 ;        //  Special Function Register 9\r
+       AT91_REG         HMATRIX2_SFR10;        //  Special Function Register 10\r
+       AT91_REG         HMATRIX2_SFR11;        //  Special Function Register 11\r
+       AT91_REG         HMATRIX2_SFR12;        //  Special Function Register 12\r
+       AT91_REG         HMATRIX2_SFR13;        //  Special Function Register 13\r
+       AT91_REG         HMATRIX2_SFR14;        //  Special Function Register 14\r
+       AT91_REG         HMATRIX2_SFR15;        //  Special Function Register 15\r
+       AT91_REG         Reserved2[39];         // \r
+       AT91_REG         HMATRIX2_ADDRSIZE;     // HMATRIX2 ADDRSIZE REGISTER \r
+       AT91_REG         HMATRIX2_IPNAME1;      // HMATRIX2 IPNAME1 REGISTER \r
+       AT91_REG         HMATRIX2_IPNAME2;      // HMATRIX2 IPNAME2 REGISTER \r
+       AT91_REG         HMATRIX2_FEATURES;     // HMATRIX2 FEATURES REGISTER \r
+       AT91_REG         HMATRIX2_VER;  // HMATRIX2 VERSION REGISTER \r
+} AT91S_HMATRIX2, *AT91PS_HMATRIX2;\r
+#else\r
+#define MATRIX_MCFG0    (AT91_CAST(AT91_REG *)         0x00000000) // (MATRIX_MCFG0)  Master Configuration Register 0 : ARM I and D\r
+#define MATRIX_MCFG1    (AT91_CAST(AT91_REG *)         0x00000004) // (MATRIX_MCFG1)  Master Configuration Register 1 : ARM S\r
+#define MATRIX_MCFG2    (AT91_CAST(AT91_REG *)         0x00000008) // (MATRIX_MCFG2)  Master Configuration Register 2\r
+#define MATRIX_MCFG3    (AT91_CAST(AT91_REG *)         0x0000000C) // (MATRIX_MCFG3)  Master Configuration Register 3\r
+#define MATRIX_MCFG4    (AT91_CAST(AT91_REG *)         0x00000010) // (MATRIX_MCFG4)  Master Configuration Register 4\r
+#define MATRIX_MCFG5    (AT91_CAST(AT91_REG *)         0x00000014) // (MATRIX_MCFG5)  Master Configuration Register 5\r
+#define MATRIX_MCFG6    (AT91_CAST(AT91_REG *)         0x00000018) // (MATRIX_MCFG6)  Master Configuration Register 6\r
+#define MATRIX_MCFG7    (AT91_CAST(AT91_REG *)         0x0000001C) // (MATRIX_MCFG7)  Master Configuration Register 7\r
+#define MATRIX_SCFG0    (AT91_CAST(AT91_REG *)         0x00000040) // (MATRIX_SCFG0)  Slave Configuration Register 0\r
+#define MATRIX_SCFG1    (AT91_CAST(AT91_REG *)         0x00000044) // (MATRIX_SCFG1)  Slave Configuration Register 1\r
+#define MATRIX_SCFG2    (AT91_CAST(AT91_REG *)         0x00000048) // (MATRIX_SCFG2)  Slave Configuration Register 2\r
+#define MATRIX_SCFG3    (AT91_CAST(AT91_REG *)         0x0000004C) // (MATRIX_SCFG3)  Slave Configuration Register 3\r
+#define MATRIX_SCFG4    (AT91_CAST(AT91_REG *)         0x00000050) // (MATRIX_SCFG4)  Slave Configuration Register 4\r
+#define MATRIX_SCFG5    (AT91_CAST(AT91_REG *)         0x00000054) // (MATRIX_SCFG5)  Slave Configuration Register 5\r
+#define MATRIX_SCFG6    (AT91_CAST(AT91_REG *)         0x00000058) // (MATRIX_SCFG6)  Slave Configuration Register 6\r
+#define MATRIX_SCFG7    (AT91_CAST(AT91_REG *)         0x0000005C) // (MATRIX_SCFG7)  Slave Configuration Register 5\r
+#define MATRIX_SCFG8    (AT91_CAST(AT91_REG *)         0x00000060) // (MATRIX_SCFG8)  Slave Configuration Register 8\r
+#define MATRIX_SFR0     (AT91_CAST(AT91_REG *)         0x00000110) // (MATRIX_SFR0 )  Special Function Register 0\r
+#define MATRIX_SFR1     (AT91_CAST(AT91_REG *)         0x00000114) // (MATRIX_SFR1 )  Special Function Register 1\r
+#define MATRIX_SFR2     (AT91_CAST(AT91_REG *)         0x00000118) // (MATRIX_SFR2 )  Special Function Register 2\r
+#define MATRIX_SFR3     (AT91_CAST(AT91_REG *)         0x0000011C) // (MATRIX_SFR3 )  Special Function Register 3\r
+#define MATRIX_SFR4     (AT91_CAST(AT91_REG *)         0x00000120) // (MATRIX_SFR4 )  Special Function Register 4\r
+#define MATRIX_SFR5     (AT91_CAST(AT91_REG *)         0x00000124) // (MATRIX_SFR5 )  Special Function Register 5\r
+#define MATRIX_SFR6     (AT91_CAST(AT91_REG *)         0x00000128) // (MATRIX_SFR6 )  Special Function Register 6\r
+#define MATRIX_SFR7     (AT91_CAST(AT91_REG *)         0x0000012C) // (MATRIX_SFR7 )  Special Function Register 7\r
+#define MATRIX_SFR8     (AT91_CAST(AT91_REG *)         0x00000130) // (MATRIX_SFR8 )  Special Function Register 8\r
+#define MATRIX_SFR9     (AT91_CAST(AT91_REG *)         0x00000134) // (MATRIX_SFR9 )  Special Function Register 9\r
+#define MATRIX_SFR10    (AT91_CAST(AT91_REG *)         0x00000138) // (MATRIX_SFR10)  Special Function Register 10\r
+#define MATRIX_SFR11    (AT91_CAST(AT91_REG *)         0x0000013C) // (MATRIX_SFR11)  Special Function Register 11\r
+#define MATRIX_SFR12    (AT91_CAST(AT91_REG *)         0x00000140) // (MATRIX_SFR12)  Special Function Register 12\r
+#define MATRIX_SFR13    (AT91_CAST(AT91_REG *)         0x00000144) // (MATRIX_SFR13)  Special Function Register 13\r
+#define MATRIX_SFR14    (AT91_CAST(AT91_REG *)         0x00000148) // (MATRIX_SFR14)  Special Function Register 14\r
+#define MATRIX_SFR15    (AT91_CAST(AT91_REG *)         0x0000014C) // (MATRIX_SFR15)  Special Function Register 15\r
+#define HMATRIX2_ADDRSIZE (AT91_CAST(AT91_REG *)       0x000001EC) // (HMATRIX2_ADDRSIZE) HMATRIX2 ADDRSIZE REGISTER \r
+#define HMATRIX2_IPNAME1 (AT91_CAST(AT91_REG *)        0x000001F0) // (HMATRIX2_IPNAME1) HMATRIX2 IPNAME1 REGISTER \r
+#define HMATRIX2_IPNAME2 (AT91_CAST(AT91_REG *)        0x000001F4) // (HMATRIX2_IPNAME2) HMATRIX2 IPNAME2 REGISTER \r
+#define HMATRIX2_FEATURES (AT91_CAST(AT91_REG *)       0x000001F8) // (HMATRIX2_FEATURES) HMATRIX2 FEATURES REGISTER \r
+#define HMATRIX2_VER    (AT91_CAST(AT91_REG *)         0x000001FC) // (HMATRIX2_VER) HMATRIX2 VERSION REGISTER \r
+\r
+#endif\r
+// -------- MATRIX_MCFG0 : (HMATRIX2 Offset: 0x0) Master Configuration Register ARM bus I and D -------- \r
+#define AT91C_MATRIX_ULBT     (0x7 <<  0) // (HMATRIX2) Undefined Length Burst Type\r
+#define        AT91C_MATRIX_ULBT_INFINIT_LENGTH       (0x0) // (HMATRIX2) infinite length burst\r
+#define        AT91C_MATRIX_ULBT_SINGLE_ACCESS        (0x1) // (HMATRIX2) Single Access\r
+#define        AT91C_MATRIX_ULBT_4_BEAT               (0x2) // (HMATRIX2) 4 Beat Burst\r
+#define        AT91C_MATRIX_ULBT_8_BEAT               (0x3) // (HMATRIX2) 8 Beat Burst\r
+#define        AT91C_MATRIX_ULBT_16_BEAT              (0x4) // (HMATRIX2) 16 Beat Burst\r
+#define        AT91C_MATRIX_ULBT_32_BEAT              (0x5) // (HMATRIX2) 32 Beat Burst\r
+#define        AT91C_MATRIX_ULBT_64_BEAT              (0x6) // (HMATRIX2) 64 Beat Burst\r
+#define        AT91C_MATRIX_ULBT_128_BEAT             (0x7) // (HMATRIX2) 128 Beat Burst\r
+// -------- MATRIX_MCFG1 : (HMATRIX2 Offset: 0x4) Master Configuration Register ARM bus S -------- \r
+// -------- MATRIX_MCFG2 : (HMATRIX2 Offset: 0x8) Master Configuration Register -------- \r
+// -------- MATRIX_MCFG3 : (HMATRIX2 Offset: 0xc) Master Configuration Register -------- \r
+// -------- MATRIX_MCFG4 : (HMATRIX2 Offset: 0x10) Master Configuration Register -------- \r
+// -------- MATRIX_MCFG5 : (HMATRIX2 Offset: 0x14) Master Configuration Register -------- \r
+// -------- MATRIX_MCFG6 : (HMATRIX2 Offset: 0x18) Master Configuration Register -------- \r
+// -------- MATRIX_MCFG7 : (HMATRIX2 Offset: 0x1c) Master Configuration Register -------- \r
+// -------- MATRIX_SCFG0 : (HMATRIX2 Offset: 0x40) Slave Configuration Register 0 -------- \r
+#define AT91C_MATRIX_SLOT_CYCLE (0xFF <<  0) // (HMATRIX2) Maximum Number of Allowed Cycles for a Burst\r
+#define AT91C_MATRIX_DEFMSTR_TYPE (0x3 << 16) // (HMATRIX2) Default Master Type\r
+#define        AT91C_MATRIX_DEFMSTR_TYPE_NO_DEFMSTR           (0x0 << 16) // (HMATRIX2) No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This results in having a one cycle latency for the first transfer of a burst.\r
+#define        AT91C_MATRIX_DEFMSTR_TYPE_LAST_DEFMSTR         (0x1 << 16) // (HMATRIX2) Last Default Master. At the end of current slave access, if no other master request is pending, the slave stay connected with the last master having accessed it. This results in not having the one cycle latency when the last master re-trying access on the slave.\r
+#define        AT91C_MATRIX_DEFMSTR_TYPE_FIXED_DEFMSTR        (0x2 << 16) // (HMATRIX2) Fixed Default Master. At the end of current slave access, if no other master request is pending, the slave connects with fixed which number is in FIXED_DEFMSTR field. This results in not having the one cycle latency when the fixed master re-trying access on the slave.\r
+#define AT91C_MATRIX_FIXED_DEFMSTR_SCFG0 (0x7 << 18) // (HMATRIX2) Fixed Index of Default Master\r
+#define        AT91C_MATRIX_FIXED_DEFMSTR_SCFG0_ARMS                 (0x1 << 18) // (HMATRIX2) ARMS is Default Master\r
+// -------- MATRIX_SCFG1 : (HMATRIX2 Offset: 0x44) Slave Configuration Register 1 -------- \r
+#define AT91C_MATRIX_FIXED_DEFMSTR_SCFG1 (0x7 << 18) // (HMATRIX2) Fixed Index of Default Master\r
+#define        AT91C_MATRIX_FIXED_DEFMSTR_SCFG1_ARMS                 (0x1 << 18) // (HMATRIX2) ARMS is Default Master\r
+// -------- MATRIX_SCFG2 : (HMATRIX2 Offset: 0x48) Slave Configuration Register 2 -------- \r
+#define AT91C_MATRIX_FIXED_DEFMSTR_SCFG2 (0x7 << 18) // (HMATRIX2) Fixed Index of Default Master\r
+#define        AT91C_MATRIX_FIXED_DEFMSTR_SCFG2_ARMS                 (0x1 << 18) // (HMATRIX2) ARMS is Default Master\r
+// -------- MATRIX_SCFG3 : (HMATRIX2 Offset: 0x4c) Slave Configuration Register 3 -------- \r
+#define AT91C_MATRIX_FIXED_DEFMSTR_SCFG3 (0x7 << 18) // (HMATRIX2) Fixed Index of Default Master\r
+#define        AT91C_MATRIX_FIXED_DEFMSTR_SCFG3_ARMC                 (0x0 << 18) // (HMATRIX2) ARMC is Default Master\r
+// -------- MATRIX_SCFG4 : (HMATRIX2 Offset: 0x50) Slave Configuration Register 4 -------- \r
+#define AT91C_MATRIX_FIXED_DEFMSTR_SCFG4 (0x7 << 18) // (HMATRIX2) Fixed Index of Default Master\r
+#define        AT91C_MATRIX_FIXED_DEFMSTR_SCFG4_ARMS                 (0x1 << 18) // (HMATRIX2) ARMS is Default Master\r
+// -------- MATRIX_SCFG5 : (HMATRIX2 Offset: 0x54) Slave Configuration Register 5 -------- \r
+#define AT91C_MATRIX_FIXED_DEFMSTR_SCFG5 (0x7 << 18) // (HMATRIX2) Fixed Index of Default Master\r
+#define        AT91C_MATRIX_FIXED_DEFMSTR_SCFG5_ARMS                 (0x1 << 18) // (HMATRIX2) ARMS is Default Master\r
+// -------- MATRIX_SCFG6 : (HMATRIX2 Offset: 0x58) Slave Configuration Register 6 -------- \r
+#define AT91C_MATRIX_FIXED_DEFMSTR_SCFG6 (0x7 << 18) // (HMATRIX2) Fixed Index of Default Master\r
+#define        AT91C_MATRIX_FIXED_DEFMSTR_SCFG6_ARMS                 (0x1 << 18) // (HMATRIX2) ARMS is Default Master\r
+// -------- MATRIX_SCFG7 : (HMATRIX2 Offset: 0x5c) Slave Configuration Register 7 -------- \r
+#define AT91C_MATRIX_FIXED_DEFMSTR_SCFG7 (0x7 << 18) // (HMATRIX2) Fixed Index of Default Master\r
+#define        AT91C_MATRIX_FIXED_DEFMSTR_SCFG7_ARMS                 (0x1 << 18) // (HMATRIX2) ARMS is Default Master\r
+// -------- MATRIX_SCFG8 : (HMATRIX2 Offset: 0x60) Slave Configuration Register 8 -------- \r
+#define AT91C_MATRIX_FIXED_DEFMSTR_SCFG8 (0x7 << 18) // (HMATRIX2) Fixed Index of Default Master\r
+#define        AT91C_MATRIX_FIXED_DEFMSTR_SCFG8_ARMS                 (0x1 << 18) // (HMATRIX2) ARMS is Default Master\r
+#define        AT91C_MATRIX_FIXED_DEFMSTR_SCFG8_HDMA                 (0x4 << 18) // (HMATRIX2) HDMA is Default Master\r
+// -------- MATRIX_SFR0 : (HMATRIX2 Offset: 0x110) Special Function Register 0 -------- \r
+// -------- MATRIX_SFR0 : (HMATRIX2 Offset: 0x114) Special Function Register 0 -------- \r
+// -------- MATRIX_SFR0 : (HMATRIX2 Offset: 0x118) Special Function Register 0 -------- \r
+// -------- MATRIX_SFR0 : (HMATRIX2 Offset: 0x11c) Special Function Register 0 -------- \r
+// -------- MATRIX_SFR0 : (HMATRIX2 Offset: 0x120) Special Function Register 0 -------- \r
+// -------- MATRIX_SFR0 : (HMATRIX2 Offset: 0x124) Special Function Register 0 -------- \r
+// -------- MATRIX_SFR0 : (HMATRIX2 Offset: 0x128) Special Function Register 0 -------- \r
+// -------- MATRIX_SFR0 : (HMATRIX2 Offset: 0x12c) Special Function Register 0 -------- \r
+// -------- MATRIX_SFR0 : (HMATRIX2 Offset: 0x130) Special Function Register 0 -------- \r
+// -------- MATRIX_SFR0 : (HMATRIX2 Offset: 0x134) Special Function Register 0 -------- \r
+// -------- MATRIX_SFR0 : (HMATRIX2 Offset: 0x138) Special Function Register 0 -------- \r
+// -------- MATRIX_SFR0 : (HMATRIX2 Offset: 0x13c) Special Function Register 0 -------- \r
+// -------- MATRIX_SFR0 : (HMATRIX2 Offset: 0x140) Special Function Register 0 -------- \r
+// -------- MATRIX_SFR0 : (HMATRIX2 Offset: 0x144) Special Function Register 0 -------- \r
+// -------- MATRIX_SFR0 : (HMATRIX2 Offset: 0x148) Special Function Register 0 -------- \r
+// -------- MATRIX_SFR0 : (HMATRIX2 Offset: 0x14c) Special Function Register 0 -------- \r
+// -------- HMATRIX2_VER : (HMATRIX2 Offset: 0x1fc)  VERSION  Register -------- \r
+#define AT91C_HMATRIX2_VER    (0xF <<  0) // (HMATRIX2)  VERSION  Register\r
+\r
+// *****************************************************************************\r
+//              SOFTWARE API DEFINITION  FOR NESTED vector Interrupt Controller\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_NVIC {\r
+       AT91_REG         Reserved0[1];  // \r
+       AT91_REG         NVIC_ICTR;     // Interrupt Control Type Register\r
+       AT91_REG         Reserved1[2];  // \r
+       AT91_REG         NVIC_STICKCSR;         // SysTick Control and Status Register\r
+       AT91_REG         NVIC_STICKRVR;         // SysTick Reload Value Register\r
+       AT91_REG         NVIC_STICKCVR;         // SysTick Current Value Register\r
+       AT91_REG         NVIC_STICKCALVR;       // SysTick Calibration Value Register\r
+       AT91_REG         Reserved2[56];         // \r
+       AT91_REG         NVIC_ISER[8];  // Set Enable Register\r
+       AT91_REG         Reserved3[24];         // \r
+       AT91_REG         NVIC_ICER[8];  // Clear enable Register\r
+       AT91_REG         Reserved4[24];         // \r
+       AT91_REG         NVIC_ISPR[8];  // Set Pending Register\r
+       AT91_REG         Reserved5[24];         // \r
+       AT91_REG         NVIC_ICPR[8];  // Clear Pending Register\r
+       AT91_REG         Reserved6[24];         // \r
+       AT91_REG         NVIC_ABR[8];   // Active Bit Register\r
+       AT91_REG         Reserved7[56];         // \r
+       AT91_REG         NVIC_IPR[60];  // Interrupt Mask Register\r
+       AT91_REG         Reserved8[516];        // \r
+       AT91_REG         NVIC_CPUID;    // CPUID Base Register\r
+       AT91_REG         NVIC_ICSR;     // Interrupt Control State Register\r
+       AT91_REG         NVIC_VTOFFR;   // Vector Table Offset Register\r
+       AT91_REG         NVIC_AIRCR;    // Application Interrupt/Reset Control Reg\r
+       AT91_REG         NVIC_SCR;      // System Control Register\r
+       AT91_REG         NVIC_CCR;      // Configuration Control Register\r
+       AT91_REG         NVIC_HAND4PR;  // System Handlers 4-7 Priority Register\r
+       AT91_REG         NVIC_HAND8PR;  // System Handlers 8-11 Priority Register\r
+       AT91_REG         NVIC_HAND12PR;         // System Handlers 12-15 Priority Register\r
+       AT91_REG         NVIC_HANDCSR;  // System Handler Control and State Register\r
+       AT91_REG         NVIC_CFSR;     // Configurable Fault Status Register\r
+       AT91_REG         NVIC_HFSR;     // Hard Fault Status Register\r
+       AT91_REG         NVIC_DFSR;     // Debug Fault Status Register\r
+       AT91_REG         NVIC_MMAR;     // Mem Manage Address Register\r
+       AT91_REG         NVIC_BFAR;     // Bus Fault Address Register\r
+       AT91_REG         NVIC_AFSR;     // Auxiliary Fault Status Register\r
+       AT91_REG         NVIC_PFR0;     // Processor Feature register0\r
+       AT91_REG         NVIC_PFR1;     // Processor Feature register1\r
+       AT91_REG         NVIC_DFR0;     // Debug Feature register0\r
+       AT91_REG         NVIC_AFR0;     // Auxiliary Feature register0\r
+       AT91_REG         NVIC_MMFR0;    // Memory Model Feature register0\r
+       AT91_REG         NVIC_MMFR1;    // Memory Model Feature register1\r
+       AT91_REG         NVIC_MMFR2;    // Memory Model Feature register2\r
+       AT91_REG         NVIC_MMFR3;    // Memory Model Feature register3\r
+       AT91_REG         NVIC_ISAR0;    // ISA Feature register0\r
+       AT91_REG         NVIC_ISAR1;    // ISA Feature register1\r
+       AT91_REG         NVIC_ISAR2;    // ISA Feature register2\r
+       AT91_REG         NVIC_ISAR3;    // ISA Feature register3\r
+       AT91_REG         NVIC_ISAR4;    // ISA Feature register4\r
+       AT91_REG         Reserved9[99];         // \r
+       AT91_REG         NVIC_STIR;     // Software Trigger Interrupt Register\r
+       AT91_REG         Reserved10[51];        // \r
+       AT91_REG         NVIC_PID4;     // Peripheral identification register\r
+       AT91_REG         NVIC_PID5;     // Peripheral identification register\r
+       AT91_REG         NVIC_PID6;     // Peripheral identification register\r
+       AT91_REG         NVIC_PID7;     // Peripheral identification register\r
+       AT91_REG         NVIC_PID0;     // Peripheral identification register b7:0\r
+       AT91_REG         NVIC_PID1;     // Peripheral identification register b15:8\r
+       AT91_REG         NVIC_PID2;     // Peripheral identification register b23:16\r
+       AT91_REG         NVIC_PID3;     // Peripheral identification register b31:24\r
+       AT91_REG         NVIC_CID0;     // Component identification register b7:0\r
+       AT91_REG         NVIC_CID1;     // Component identification register b15:8\r
+       AT91_REG         NVIC_CID2;     // Component identification register b23:16\r
+       AT91_REG         NVIC_CID3;     // Component identification register b31:24\r
+} AT91S_NVIC, *AT91PS_NVIC;\r
+#else\r
+#define NVIC_ICTR       (AT91_CAST(AT91_REG *)         0x00000004) // (NVIC_ICTR) Interrupt Control Type Register\r
+#define NVIC_STICKCSR   (AT91_CAST(AT91_REG *)         0x00000010) // (NVIC_STICKCSR) SysTick Control and Status Register\r
+#define NVIC_STICKRVR   (AT91_CAST(AT91_REG *)         0x00000014) // (NVIC_STICKRVR) SysTick Reload Value Register\r
+#define NVIC_STICKCVR   (AT91_CAST(AT91_REG *)         0x00000018) // (NVIC_STICKCVR) SysTick Current Value Register\r
+#define NVIC_STICKCALVR (AT91_CAST(AT91_REG *)         0x0000001C) // (NVIC_STICKCALVR) SysTick Calibration Value Register\r
+#define NVIC_ISER       (AT91_CAST(AT91_REG *)         0x00000100) // (NVIC_ISER) Set Enable Register\r
+#define NVIC_ICER       (AT91_CAST(AT91_REG *)         0x00000180) // (NVIC_ICER) Clear enable Register\r
+#define NVIC_ISPR       (AT91_CAST(AT91_REG *)         0x00000200) // (NVIC_ISPR) Set Pending Register\r
+#define NVIC_ICPR       (AT91_CAST(AT91_REG *)         0x00000280) // (NVIC_ICPR) Clear Pending Register\r
+#define NVIC_IABR       (AT91_CAST(AT91_REG *)         0x00000300) // (NVIC_IABR) Active Bit Register\r
+#define NVIC_IPR        (AT91_CAST(AT91_REG *)         0x00000400) // (NVIC_IPR) Interrupt Mask Register\r
+#define NVIC_CPUID      (AT91_CAST(AT91_REG *)         0x00000D00) // (NVIC_CPUID) CPUID Base Register\r
+#define NVIC_ICSR       (AT91_CAST(AT91_REG *)         0x00000D04) // (NVIC_ICSR) Interrupt Control State Register\r
+#define NVIC_VTOFFR     (AT91_CAST(AT91_REG *)         0x00000D08) // (NVIC_VTOFFR) Vector Table Offset Register\r
+#define NVIC_AIRCR      (AT91_CAST(AT91_REG *)         0x00000D0C) // (NVIC_AIRCR) Application Interrupt/Reset Control Reg\r
+#define NVIC_SCR        (AT91_CAST(AT91_REG *)         0x00000D10) // (NVIC_SCR) System Control Register\r
+#define NVIC_CCR        (AT91_CAST(AT91_REG *)         0x00000D14) // (NVIC_CCR) Configuration Control Register\r
+#define NVIC_HAND4PR    (AT91_CAST(AT91_REG *)         0x00000D18) // (NVIC_HAND4PR) System Handlers 4-7 Priority Register\r
+#define NVIC_HAND8PR    (AT91_CAST(AT91_REG *)         0x00000D1C) // (NVIC_HAND8PR) System Handlers 8-11 Priority Register\r
+#define NVIC_HAND12PR   (AT91_CAST(AT91_REG *)         0x00000D20) // (NVIC_HAND12PR) System Handlers 12-15 Priority Register\r
+#define NVIC_HANDCSR    (AT91_CAST(AT91_REG *)         0x00000D24) // (NVIC_HANDCSR) System Handler Control and State Register\r
+#define NVIC_CFSR       (AT91_CAST(AT91_REG *)         0x00000D28) // (NVIC_CFSR) Configurable Fault Status Register\r
+#define NVIC_HFSR       (AT91_CAST(AT91_REG *)         0x00000D2C) // (NVIC_HFSR) Hard Fault Status Register\r
+#define NVIC_DFSR       (AT91_CAST(AT91_REG *)         0x00000D30) // (NVIC_DFSR) Debug Fault Status Register\r
+#define NVIC_MMAR       (AT91_CAST(AT91_REG *)         0x00000D34) // (NVIC_MMAR) Mem Manage Address Register\r
+#define NVIC_BFAR       (AT91_CAST(AT91_REG *)         0x00000D38) // (NVIC_BFAR) Bus Fault Address Register\r
+#define NVIC_AFSR       (AT91_CAST(AT91_REG *)         0x00000D3C) // (NVIC_AFSR) Auxiliary Fault Status Register\r
+#define NVIC_PFR0       (AT91_CAST(AT91_REG *)         0x00000D40) // (NVIC_PFR0) Processor Feature register0\r
+#define NVIC_PFR1       (AT91_CAST(AT91_REG *)         0x00000D44) // (NVIC_PFR1) Processor Feature register1\r
+#define NVIC_DFR0       (AT91_CAST(AT91_REG *)         0x00000D48) // (NVIC_DFR0) Debug Feature register0\r
+#define NVIC_AFR0       (AT91_CAST(AT91_REG *)         0x00000D4C) // (NVIC_AFR0) Auxiliary Feature register0\r
+#define NVIC_MMFR0      (AT91_CAST(AT91_REG *)         0x00000D50) // (NVIC_MMFR0) Memory Model Feature register0\r
+#define NVIC_MMFR1      (AT91_CAST(AT91_REG *)         0x00000D54) // (NVIC_MMFR1) Memory Model Feature register1\r
+#define NVIC_MMFR2      (AT91_CAST(AT91_REG *)         0x00000D58) // (NVIC_MMFR2) Memory Model Feature register2\r
+#define NVIC_MMFR3      (AT91_CAST(AT91_REG *)         0x00000D5C) // (NVIC_MMFR3) Memory Model Feature register3\r
+#define NVIC_ISAR0      (AT91_CAST(AT91_REG *)         0x00000D60) // (NVIC_ISAR0) ISA Feature register0\r
+#define NVIC_ISAR1      (AT91_CAST(AT91_REG *)         0x00000D64) // (NVIC_ISAR1) ISA Feature register1\r
+#define NVIC_ISAR2      (AT91_CAST(AT91_REG *)         0x00000D68) // (NVIC_ISAR2) ISA Feature register2\r
+#define NVIC_ISAR3      (AT91_CAST(AT91_REG *)         0x00000D6C) // (NVIC_ISAR3) ISA Feature register3\r
+#define NVIC_ISAR4      (AT91_CAST(AT91_REG *)         0x00000D70) // (NVIC_ISAR4) ISA Feature register4\r
+#define NVIC_STIR       (AT91_CAST(AT91_REG *)         0x00000F00) // (NVIC_STIR) Software Trigger Interrupt Register\r
+#define NVIC_PID4       (AT91_CAST(AT91_REG *)         0x00000FD0) // (NVIC_PID4) Peripheral identification register\r
+#define NVIC_PID5       (AT91_CAST(AT91_REG *)         0x00000FD4) // (NVIC_PID5) Peripheral identification register\r
+#define NVIC_PID6       (AT91_CAST(AT91_REG *)         0x00000FD8) // (NVIC_PID6) Peripheral identification register\r
+#define NVIC_PID7       (AT91_CAST(AT91_REG *)         0x00000FDC) // (NVIC_PID7) Peripheral identification register\r
+#define NVIC_PID0       (AT91_CAST(AT91_REG *)         0x00000FE0) // (NVIC_PID0) Peripheral identification register b7:0\r
+#define NVIC_PID1       (AT91_CAST(AT91_REG *)         0x00000FE4) // (NVIC_PID1) Peripheral identification register b15:8\r
+#define NVIC_PID2       (AT91_CAST(AT91_REG *)         0x00000FE8) // (NVIC_PID2) Peripheral identification register b23:16\r
+#define NVIC_PID3       (AT91_CAST(AT91_REG *)         0x00000FEC) // (NVIC_PID3) Peripheral identification register b31:24\r
+#define NVIC_CID0       (AT91_CAST(AT91_REG *)         0x00000FF0) // (NVIC_CID0) Component identification register b7:0\r
+#define NVIC_CID1       (AT91_CAST(AT91_REG *)         0x00000FF4) // (NVIC_CID1) Component identification register b15:8\r
+#define NVIC_CID2       (AT91_CAST(AT91_REG *)         0x00000FF8) // (NVIC_CID2) Component identification register b23:16\r
+#define NVIC_CID3       (AT91_CAST(AT91_REG *)         0x00000FFC) // (NVIC_CID3) Component identification register b31:24\r
+\r
+#endif\r
+// -------- NVIC_ICTR : (NVIC Offset: 0x4) Interrupt Controller Type Register -------- \r
+#define AT91C_NVIC_INTLINESNUM (0xF <<  0) // (NVIC) Total number of interrupt lines\r
+#define        AT91C_NVIC_INTLINESNUM_32                   (0x0) // (NVIC) up to 32 interrupt lines supported\r
+#define        AT91C_NVIC_INTLINESNUM_64                   (0x1) // (NVIC) up to 64 interrupt lines supported\r
+#define        AT91C_NVIC_INTLINESNUM_96                   (0x2) // (NVIC) up to 96 interrupt lines supported\r
+#define        AT91C_NVIC_INTLINESNUM_128                  (0x3) // (NVIC) up to 128 interrupt lines supported\r
+#define        AT91C_NVIC_INTLINESNUM_160                  (0x4) // (NVIC) up to 160 interrupt lines supported\r
+#define        AT91C_NVIC_INTLINESNUM_192                  (0x5) // (NVIC) up to 192 interrupt lines supported\r
+#define        AT91C_NVIC_INTLINESNUM_224                  (0x6) // (NVIC) up to 224 interrupt lines supported\r
+#define        AT91C_NVIC_INTLINESNUM_256                  (0x7) // (NVIC) up to 256 interrupt lines supported\r
+#define        AT91C_NVIC_INTLINESNUM_288                  (0x8) // (NVIC) up to 288 interrupt lines supported\r
+#define        AT91C_NVIC_INTLINESNUM_320                  (0x9) // (NVIC) up to 320 interrupt lines supported\r
+#define        AT91C_NVIC_INTLINESNUM_352                  (0xA) // (NVIC) up to 352 interrupt lines supported\r
+#define        AT91C_NVIC_INTLINESNUM_384                  (0xB) // (NVIC) up to 384 interrupt lines supported\r
+#define        AT91C_NVIC_INTLINESNUM_416                  (0xC) // (NVIC) up to 416 interrupt lines supported\r
+#define        AT91C_NVIC_INTLINESNUM_448                  (0xD) // (NVIC) up to 448 interrupt lines supported\r
+#define        AT91C_NVIC_INTLINESNUM_480                  (0xE) // (NVIC) up to 480 interrupt lines supported\r
+#define        AT91C_NVIC_INTLINESNUM_496                  (0xF) // (NVIC) up to 496 interrupt lines supported)\r
+// -------- NVIC_STICKCSR : (NVIC Offset: 0x10) SysTick Control and Status Register -------- \r
+#define AT91C_NVIC_STICKENABLE (0x1 <<  0) // (NVIC) SysTick counter enable.\r
+#define AT91C_NVIC_STICKINT   (0x1 <<  1) // (NVIC) SysTick interrupt enable.\r
+#define AT91C_NVIC_STICKCLKSOURCE (0x1 <<  2) // (NVIC) Reference clock selection.\r
+#define AT91C_NVIC_STICKCOUNTFLAG (0x1 << 16) // (NVIC) Return 1 if timer counted to 0 since last read.\r
+// -------- NVIC_STICKRVR : (NVIC Offset: 0x14) SysTick Reload Value Register -------- \r
+#define AT91C_NVIC_STICKRELOAD (0xFFFFFF <<  0) // (NVIC) SysTick reload value.\r
+// -------- NVIC_STICKCVR : (NVIC Offset: 0x18) SysTick Current Value Register -------- \r
+#define AT91C_NVIC_STICKCURRENT (0x7FFFFFFF <<  0) // (NVIC) SysTick current value.\r
+// -------- NVIC_STICKCALVR : (NVIC Offset: 0x1c) SysTick Calibration Value Register -------- \r
+#define AT91C_NVIC_STICKTENMS (0xFFFFFF <<  0) // (NVIC) Reload value to use for 10ms timing.\r
+#define AT91C_NVIC_STICKSKEW  (0x1 << 30) // (NVIC) Read as 1 if the calibration value is not exactly 10ms because of clock frequency.\r
+#define AT91C_NVIC_STICKNOREF (0x1 << 31) // (NVIC) Read as 1 if the reference clock is not provided.\r
+// -------- NVIC_IPR : (NVIC Offset: 0x400) Interrupt Priority Registers -------- \r
+#define AT91C_NVIC_PRI_N      (0xFF <<  0) // (NVIC) Priority of interrupt N (0, 4, 8, etc)\r
+#define AT91C_NVIC_PRI_N1     (0xFF <<  8) // (NVIC) Priority of interrupt N+1 (1, 5, 9, etc)\r
+#define AT91C_NVIC_PRI_N2     (0xFF << 16) // (NVIC) Priority of interrupt N+2 (2, 6, 10, etc)\r
+#define AT91C_NVIC_PRI_N3     (0xFF << 24) // (NVIC) Priority of interrupt N+3 (3, 7, 11, etc)\r
+// -------- NVIC_CPUID : (NVIC Offset: 0xd00) CPU ID Base Register -------- \r
+#define AT91C_NVIC_REVISION   (0xF <<  0) // (NVIC) Implementation defined revision number.\r
+#define AT91C_NVIC_PARTNO     (0xFFF <<  4) // (NVIC) Number of processor within family\r
+#define AT91C_NVIC_CONSTANT   (0xF << 16) // (NVIC) Reads as 0xF\r
+#define AT91C_NVIC_VARIANT    (0xF << 20) // (NVIC) Implementation defined variant number.\r
+#define AT91C_NVIC_IMPLEMENTER (0xFF << 24) // (NVIC) Implementer code. ARM is 0x41\r
+// -------- NVIC_ICSR : (NVIC Offset: 0xd04) Interrupt Control State Register -------- \r
+#define AT91C_NVIC_VECTACTIVE (0x1FF <<  0) // (NVIC) Read-only Active ISR number field\r
+#define AT91C_NVIC_RETTOBASE  (0x1 << 11) // (NVIC) Read-only\r
+#define AT91C_NVIC_VECTPENDING (0x1FF << 12) // (NVIC) Read-only Pending ISR number field\r
+#define AT91C_NVIC_ISRPENDING (0x1 << 22) // (NVIC) Read-only Interrupt pending flag.\r
+#define AT91C_NVIC_ISRPREEMPT (0x1 << 23) // (NVIC) Read-only You must only use this at debug time\r
+#define AT91C_NVIC_PENDSTCLR  (0x1 << 25) // (NVIC) Write-only Clear pending SysTick bit\r
+#define AT91C_NVIC_PENDSTSET  (0x1 << 26) // (NVIC) Read/write Set a pending SysTick bit\r
+#define AT91C_NVIC_PENDSVCLR  (0x1 << 27) // (NVIC) Write-only Clear pending pendSV bit\r
+#define AT91C_NVIC_PENDSVSET  (0x1 << 28) // (NVIC) Read/write Set pending pendSV bit\r
+#define AT91C_NVIC_NMIPENDSET (0x1 << 31) // (NVIC) Read/write Set pending NMI\r
+// -------- NVIC_VTOFFR : (NVIC Offset: 0xd08) Vector Table Offset Register -------- \r
+#define AT91C_NVIC_TBLOFF     (0x3FFFFF <<  7) // (NVIC) Vector table base offset field\r
+#define AT91C_NVIC_TBLBASE    (0x1 << 29) // (NVIC) Table base is in Code (0) or RAM (1)\r
+#define        AT91C_NVIC_TBLBASE_CODE                 (0x0 << 29) // (NVIC) Table base is in CODE\r
+#define        AT91C_NVIC_TBLBASE_RAM                  (0x1 << 29) // (NVIC) Table base is in RAM\r
+// -------- NVIC_AIRCR : (NVIC Offset: 0xd0c) Application Interrupt and Reset Control Register -------- \r
+#define AT91C_NVIC_VECTRESET  (0x1 <<  0) // (NVIC) System Reset bit\r
+#define AT91C_NVIC_VECTCLRACTIVE (0x1 <<  1) // (NVIC) Clear active vector bit\r
+#define AT91C_NVIC_SYSRESETREQ (0x1 <<  2) // (NVIC) Causes a signal to be asserted to the outer system that indicates a reset is requested\r
+#define AT91C_NVIC_PRIGROUP   (0x7 <<  8) // (NVIC) Interrupt priority grouping field\r
+#define        AT91C_NVIC_PRIGROUP_0                    (0x0 <<  8) // (NVIC) indicates seven bits of pre-emption priority, one bit of subpriority\r
+#define        AT91C_NVIC_PRIGROUP_1                    (0x1 <<  8) // (NVIC) indicates six bits of pre-emption priority, two bits of subpriority\r
+#define        AT91C_NVIC_PRIGROUP_2                    (0x2 <<  8) // (NVIC) indicates five bits of pre-emption priority, three bits of subpriority\r
+#define        AT91C_NVIC_PRIGROUP_3                    (0x3 <<  8) // (NVIC) indicates four bits of pre-emption priority, four bits of subpriority\r
+#define        AT91C_NVIC_PRIGROUP_4                    (0x4 <<  8) // (NVIC) indicates three bits of pre-emption priority, five bits of subpriority\r
+#define        AT91C_NVIC_PRIGROUP_5                    (0x5 <<  8) // (NVIC) indicates two bits of pre-emption priority, six bits of subpriority\r
+#define        AT91C_NVIC_PRIGROUP_6                    (0x6 <<  8) // (NVIC) indicates one bit of pre-emption priority, seven bits of subpriority\r
+#define        AT91C_NVIC_PRIGROUP_7                    (0x7 <<  8) // (NVIC) indicates no pre-emption priority, eight bits of subpriority\r
+#define AT91C_NVIC_ENDIANESS  (0x1 << 15) // (NVIC) Data endianness bit\r
+#define AT91C_NVIC_VECTKEY    (0xFFFF << 16) // (NVIC) Register key\r
+// -------- NVIC_SCR : (NVIC Offset: 0xd10) System Control Register -------- \r
+#define AT91C_NVIC_SLEEPONEXIT (0x1 <<  1) // (NVIC) Sleep on exit when returning from Handler mode to Thread mode\r
+#define AT91C_NVIC_SLEEPDEEP  (0x1 <<  2) // (NVIC) Sleep deep bit\r
+#define AT91C_NVIC_SEVONPEND  (0x1 <<  4) // (NVIC) When enabled, this causes WFE to wake up when an interrupt moves from inactive to pended\r
+// -------- NVIC_CCR : (NVIC Offset: 0xd14) Configuration Control Register -------- \r
+#define AT91C_NVIC_NONEBASETHRDENA (0x1 <<  0) // (NVIC) When 0, default, It is only possible to enter Thread mode when returning from the last exception\r
+#define AT91C_NVIC_USERSETMPEND (0x1 <<  1) // (NVIC) \r
+#define AT91C_NVIC_UNALIGN_TRP (0x1 <<  3) // (NVIC) Trap for unaligned access\r
+#define AT91C_NVIC_DIV_0_TRP  (0x1 <<  4) // (NVIC) Trap on Divide by 0\r
+#define AT91C_NVIC_BFHFNMIGN  (0x1 <<  8) // (NVIC) \r
+#define AT91C_NVIC_STKALIGN   (0x1 <<  9) // (NVIC) \r
+// -------- NVIC_HAND4PR : (NVIC Offset: 0xd18) System Handlers 4-7 Priority Register -------- \r
+#define AT91C_NVIC_PRI_4      (0xFF <<  0) // (NVIC) \r
+#define AT91C_NVIC_PRI_5      (0xFF <<  8) // (NVIC) \r
+#define AT91C_NVIC_PRI_6      (0xFF << 16) // (NVIC) \r
+#define AT91C_NVIC_PRI_7      (0xFF << 24) // (NVIC) \r
+// -------- NVIC_HAND8PR : (NVIC Offset: 0xd1c) System Handlers 8-11 Priority Register -------- \r
+#define AT91C_NVIC_PRI_8      (0xFF <<  0) // (NVIC) \r
+#define AT91C_NVIC_PRI_9      (0xFF <<  8) // (NVIC) \r
+#define AT91C_NVIC_PRI_10     (0xFF << 16) // (NVIC) \r
+#define AT91C_NVIC_PRI_11     (0xFF << 24) // (NVIC) \r
+// -------- NVIC_HAND12PR : (NVIC Offset: 0xd20) System Handlers 12-15 Priority Register -------- \r
+#define AT91C_NVIC_PRI_12     (0xFF <<  0) // (NVIC) \r
+#define AT91C_NVIC_PRI_13     (0xFF <<  8) // (NVIC) \r
+#define AT91C_NVIC_PRI_14     (0xFF << 16) // (NVIC) \r
+#define AT91C_NVIC_PRI_15     (0xFF << 24) // (NVIC) \r
+// -------- NVIC_HANDCSR : (NVIC Offset: 0xd24) System Handler Control and State Register -------- \r
+#define AT91C_NVIC_MEMFAULTACT (0x1 <<  0) // (NVIC) \r
+#define AT91C_NVIC_BUSFAULTACT (0x1 <<  1) // (NVIC) \r
+#define AT91C_NVIC_USGFAULTACT (0x1 <<  3) // (NVIC) \r
+#define AT91C_NVIC_SVCALLACT  (0x1 <<  7) // (NVIC) \r
+#define AT91C_NVIC_MONITORACT (0x1 <<  8) // (NVIC) \r
+#define AT91C_NVIC_PENDSVACT  (0x1 << 10) // (NVIC) \r
+#define AT91C_NVIC_SYSTICKACT (0x1 << 11) // (NVIC) \r
+#define AT91C_NVIC_USGFAULTPENDED (0x1 << 12) // (NVIC) \r
+#define AT91C_NVIC_MEMFAULTPENDED (0x1 << 13) // (NVIC) \r
+#define AT91C_NVIC_BUSFAULTPENDED (0x1 << 14) // (NVIC) \r
+#define AT91C_NVIC_SVCALLPENDED (0x1 << 15) // (NVIC) \r
+#define AT91C_NVIC_MEMFAULTENA (0x1 << 16) // (NVIC) \r
+#define AT91C_NVIC_BUSFAULTENA (0x1 << 17) // (NVIC) \r
+#define AT91C_NVIC_USGFAULTENA (0x1 << 18) // (NVIC) \r
+// -------- NVIC_CFSR : (NVIC Offset: 0xd28) Configurable Fault Status Registers -------- \r
+#define AT91C_NVIC_MEMMANAGE  (0xFF <<  0) // (NVIC) \r
+#define AT91C_NVIC_BUSFAULT   (0xFF <<  8) // (NVIC) \r
+#define AT91C_NVIC_USAGEFAULT (0xFF << 16) // (NVIC) \r
+// -------- NVIC_BFAR : (NVIC Offset: 0xd38) Bus Fault Address Register -------- \r
+#define AT91C_NVIC_IBUSERR    (0x1 <<  0) // (NVIC) This bit indicates a bus fault on an instruction prefetch\r
+#define AT91C_NVIC_PRECISERR  (0x1 <<  1) // (NVIC) Precise data access error. The BFAR is written with the faulting address\r
+#define AT91C_NVIC_IMPRECISERR (0x1 <<  2) // (NVIC) Imprecise data access error\r
+#define AT91C_NVIC_UNSTKERR   (0x1 <<  3) // (NVIC) This bit indicates a derived bus fault has occurred on exception return\r
+#define AT91C_NVIC_STKERR     (0x1 <<  4) // (NVIC) This bit indicates a derived bus fault has occurred on exception entry\r
+#define AT91C_NVIC_BFARVALID  (0x1 <<  7) // (NVIC) This bit is set if the BFAR register has valid contents\r
+// -------- NVIC_PFR0 : (NVIC Offset: 0xd40) Processor Feature register0 (ID_PFR0) -------- \r
+#define AT91C_NVIC_ID_PFR0_0  (0xF <<  0) // (NVIC) State0 (T-bit == 0)\r
+#define AT91C_NVIC_ID_PRF0_1  (0xF <<  4) // (NVIC) State1 (T-bit == 1)\r
+// -------- NVIC_PFR1 : (NVIC Offset: 0xd44) Processor Feature register1 (ID_PFR1) -------- \r
+#define AT91C_NVIC_ID_PRF1_MODEL (0xF <<  8) // (NVIC) Microcontroller programmer\92s model\r
+// -------- NVIC_DFR0 : (NVIC Offset: 0xd48) Debug Feature register0 (ID_DFR0) -------- \r
+#define AT91C_NVIC_ID_DFR0_MODEL (0xF << 20) // (NVIC) Microcontroller Debug Model \96 memory mapped\r
+// -------- NVIC_MMFR0 : (NVIC Offset: 0xd50) Memory Model Feature register0 (ID_MMFR0) -------- \r
+#define AT91C_NVIC_ID_MMFR0_PMSA (0xF <<  4) // (NVIC) Microcontroller Debug Model \96 memory mapped\r
+#define AT91C_NVIC_ID_MMFR0_CACHE (0xF <<  8) // (NVIC) Microcontroller Debug Model \96 memory mapped\r
+\r
+// *****************************************************************************\r
+//              SOFTWARE API DEFINITION  FOR NESTED vector Interrupt Controller\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_MPU {\r
+       AT91_REG         MPU_TYPE;      // MPU Type Register\r
+       AT91_REG         MPU_CTRL;      // MPU Control Register\r
+       AT91_REG         MPU_REG_NB;    // MPU Region Number Register\r
+       AT91_REG         MPU_REG_BASE_ADDR;     // MPU Region Base Address Register\r
+       AT91_REG         MPU_ATTR_SIZE;         // MPU  Attribute and Size Register\r
+       AT91_REG         MPU_REG_BASE_ADDR1;    // MPU Region Base Address Register alias 1\r
+       AT91_REG         MPU_ATTR_SIZE1;        // MPU  Attribute and Size Register alias 1\r
+       AT91_REG         MPU_REG_BASE_ADDR2;    // MPU Region Base Address Register alias 2\r
+       AT91_REG         MPU_ATTR_SIZE2;        // MPU  Attribute and Size Register alias 2\r
+       AT91_REG         MPU_REG_BASE_ADDR3;    // MPU Region Base Address Register alias 3\r
+       AT91_REG         MPU_ATTR_SIZE3;        // MPU  Attribute and Size Register alias 3\r
+} AT91S_MPU, *AT91PS_MPU;\r
+#else\r
+#define MPU_TYPE        (AT91_CAST(AT91_REG *)         0x00000000) // (MPU_TYPE) MPU Type Register\r
+#define MPU_CTRL        (AT91_CAST(AT91_REG *)         0x00000004) // (MPU_CTRL) MPU Control Register\r
+#define MPU_REG_NB      (AT91_CAST(AT91_REG *)         0x00000008) // (MPU_REG_NB) MPU Region Number Register\r
+#define MPU_REG_BASE_ADDR (AT91_CAST(AT91_REG *)       0x0000000C) // (MPU_REG_BASE_ADDR) MPU Region Base Address Register\r
+#define MPU_ATTR_SIZE   (AT91_CAST(AT91_REG *)         0x00000010) // (MPU_ATTR_SIZE) MPU  Attribute and Size Register\r
+#define MPU_REG_BASE_ADDR1 (AT91_CAST(AT91_REG *)      0x00000014) // (MPU_REG_BASE_ADDR1) MPU Region Base Address Register alias 1\r
+#define MPU_ATTR_SIZE1  (AT91_CAST(AT91_REG *)         0x00000018) // (MPU_ATTR_SIZE1) MPU  Attribute and Size Register alias 1\r
+#define MPU_REG_BASE_ADDR2 (AT91_CAST(AT91_REG *)      0x0000001C) // (MPU_REG_BASE_ADDR2) MPU Region Base Address Register alias 2\r
+#define MPU_ATTR_SIZE2  (AT91_CAST(AT91_REG *)         0x00000020) // (MPU_ATTR_SIZE2) MPU  Attribute and Size Register alias 2\r
+#define MPU_REG_BASE_ADDR3 (AT91_CAST(AT91_REG *)      0x00000024) // (MPU_REG_BASE_ADDR3) MPU Region Base Address Register alias 3\r
+#define MPU_ATTR_SIZE3  (AT91_CAST(AT91_REG *)         0x00000028) // (MPU_ATTR_SIZE3) MPU  Attribute and Size Register alias 3\r
+\r
+#endif\r
+// -------- MPU_TYPE : (MPU Offset: 0x0)  -------- \r
+#define AT91C_MPU_SEPARATE    (0x1 <<  0) // (MPU) \r
+#define AT91C_MPU_DREGION     (0xFF <<  8) // (MPU) \r
+#define AT91C_MPU_IREGION     (0xFF << 16) // (MPU) \r
+// -------- MPU_CTRL : (MPU Offset: 0x4)  -------- \r
+#define AT91C_MPU_ENABLE      (0x1 <<  0) // (MPU) \r
+#define AT91C_MPU_HFNMIENA    (0x1 <<  1) // (MPU) \r
+#define AT91C_MPU_PRIVDEFENA  (0x1 <<  2) // (MPU) \r
+// -------- MPU_REG_NB : (MPU Offset: 0x8)  -------- \r
+#define AT91C_MPU_REGION      (0xFF <<  0) // (MPU) \r
+// -------- MPU_REG_BASE_ADDR : (MPU Offset: 0xc)  -------- \r
+#define AT91C_MPU_REG         (0xF <<  0) // (MPU) \r
+#define AT91C_MPU_VALID       (0x1 <<  4) // (MPU) \r
+#define AT91C_MPU_ADDR        (0x3FFFFFF <<  5) // (MPU) \r
+// -------- MPU_ATTR_SIZE : (MPU Offset: 0x10)  -------- \r
+#define AT91C_MPU_ENA         (0x1 <<  0) // (MPU) \r
+#define AT91C_MPU_SIZE        (0xF <<  1) // (MPU) \r
+#define AT91C_MPU_SRD         (0xFF <<  8) // (MPU) \r
+#define AT91C_MPU_B           (0x1 << 16) // (MPU) \r
+#define AT91C_MPU_C           (0x1 << 17) // (MPU) \r
+#define AT91C_MPU_S           (0x1 << 18) // (MPU) \r
+#define AT91C_MPU_TEX         (0x7 << 19) // (MPU) \r
+#define AT91C_MPU_AP          (0x7 << 24) // (MPU) \r
+#define AT91C_MPU_XN          (0x7 << 28) // (MPU) \r
+\r
+// *****************************************************************************\r
+//              SOFTWARE API DEFINITION  FOR CORTEX_M3 Registers\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_CM3 {\r
+       AT91_REG         CM3_CPUID;     // CPU ID Base Register\r
+       AT91_REG         CM3_ICSR;      // Interrupt Control State Register\r
+       AT91_REG         CM3_VTOR;      // Vector Table Offset Register\r
+       AT91_REG         CM3_AIRCR;     // Application Interrupt and Reset Control Register\r
+       AT91_REG         CM3_SCR;       // System Controller Register\r
+       AT91_REG         CM3_CCR;       // Configuration Control Register\r
+       AT91_REG         CM3_SHPR[3];   // System Handler Priority Register\r
+       AT91_REG         CM3_SHCSR;     // System Handler Control and State Register\r
+} AT91S_CM3, *AT91PS_CM3;\r
+#else\r
+#define CM3_CPUID       (AT91_CAST(AT91_REG *)         0x00000000) // (CM3_CPUID) CPU ID Base Register\r
+#define CM3_ICSR        (AT91_CAST(AT91_REG *)         0x00000004) // (CM3_ICSR) Interrupt Control State Register\r
+#define CM3_VTOR        (AT91_CAST(AT91_REG *)         0x00000008) // (CM3_VTOR) Vector Table Offset Register\r
+#define CM3_AIRCR       (AT91_CAST(AT91_REG *)         0x0000000C) // (CM3_AIRCR) Application Interrupt and Reset Control Register\r
+#define CM3_SCR         (AT91_CAST(AT91_REG *)         0x00000010) // (CM3_SCR) System Controller Register\r
+#define CM3_CCR         (AT91_CAST(AT91_REG *)         0x00000014) // (CM3_CCR) Configuration Control Register\r
+#define CM3_SHPR        (AT91_CAST(AT91_REG *)         0x00000018) // (CM3_SHPR) System Handler Priority Register\r
+#define CM3_SHCSR       (AT91_CAST(AT91_REG *)         0x00000024) // (CM3_SHCSR) System Handler Control and State Register\r
+\r
+#endif\r
+// -------- CM3_CPUID : (CM3 Offset: 0x0)  -------- \r
+// -------- CM3_AIRCR : (CM3 Offset: 0xc)  -------- \r
+#define AT91C_CM3_SYSRESETREQ (0x1 <<  2) // (CM3) A reset is requested by the processor.\r
+// -------- CM3_SCR : (CM3 Offset: 0x10)  -------- \r
+#define AT91C_CM3_SLEEPONEXIT (0x1 <<  1) // (CM3) Sleep on exit when returning from Handler mode to Thread mode. Enables interrupt driven applications to avoid returning to empty main application.\r
+#define AT91C_CM3_SLEEPDEEP   (0x1 <<  2) // (CM3) Sleep deep bit.\r
+#define AT91C_CM3_SEVONPEND   (0x1 <<  4) // (CM3) When enabled, this causes WFE to wake up when an interrupt moves from inactive to pended.\r
+// -------- CM3_SHCSR : (CM3 Offset: 0x24)  -------- \r
+#define AT91C_CM3_SYSTICKACT  (0x1 << 11) // (CM3) Reads as 1 if SysTick is active.\r
+\r
+// *****************************************************************************\r
+//              SOFTWARE API DEFINITION  FOR Peripheral DMA Controller\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_PDC {\r
+       AT91_REG         PDC_RPR;       // Receive Pointer Register\r
+       AT91_REG         PDC_RCR;       // Receive Counter Register\r
+       AT91_REG         PDC_TPR;       // Transmit Pointer Register\r
+       AT91_REG         PDC_TCR;       // Transmit Counter Register\r
+       AT91_REG         PDC_RNPR;      // Receive Next Pointer Register\r
+       AT91_REG         PDC_RNCR;      // Receive Next Counter Register\r
+       AT91_REG         PDC_TNPR;      // Transmit Next Pointer Register\r
+       AT91_REG         PDC_TNCR;      // Transmit Next Counter Register\r
+       AT91_REG         PDC_PTCR;      // PDC Transfer Control Register\r
+       AT91_REG         PDC_PTSR;      // PDC Transfer Status Register\r
+} AT91S_PDC, *AT91PS_PDC;\r
+#else\r
+#define PDC_RPR         (AT91_CAST(AT91_REG *)         0x00000000) // (PDC_RPR) Receive Pointer Register\r
+#define PDC_RCR         (AT91_CAST(AT91_REG *)         0x00000004) // (PDC_RCR) Receive Counter Register\r
+#define PDC_TPR         (AT91_CAST(AT91_REG *)         0x00000008) // (PDC_TPR) Transmit Pointer Register\r
+#define PDC_TCR         (AT91_CAST(AT91_REG *)         0x0000000C) // (PDC_TCR) Transmit Counter Register\r
+#define PDC_RNPR        (AT91_CAST(AT91_REG *)         0x00000010) // (PDC_RNPR) Receive Next Pointer Register\r
+#define PDC_RNCR        (AT91_CAST(AT91_REG *)         0x00000014) // (PDC_RNCR) Receive Next Counter Register\r
+#define PDC_TNPR        (AT91_CAST(AT91_REG *)         0x00000018) // (PDC_TNPR) Transmit Next Pointer Register\r
+#define PDC_TNCR        (AT91_CAST(AT91_REG *)         0x0000001C) // (PDC_TNCR) Transmit Next Counter Register\r
+#define PDC_PTCR        (AT91_CAST(AT91_REG *)         0x00000020) // (PDC_PTCR) PDC Transfer Control Register\r
+#define PDC_PTSR        (AT91_CAST(AT91_REG *)         0x00000024) // (PDC_PTSR) PDC Transfer Status Register\r
+\r
+#endif\r
+// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- \r
+#define AT91C_PDC_RXTEN       (0x1 <<  0) // (PDC) Receiver Transfer Enable\r
+#define AT91C_PDC_RXTDIS      (0x1 <<  1) // (PDC) Receiver Transfer Disable\r
+#define AT91C_PDC_TXTEN       (0x1 <<  8) // (PDC) Transmitter Transfer Enable\r
+#define AT91C_PDC_TXTDIS      (0x1 <<  9) // (PDC) Transmitter Transfer Disable\r
+// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- \r
+\r
+// *****************************************************************************\r
+//              SOFTWARE API DEFINITION  FOR Debug Unit\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_DBGU {\r
+       AT91_REG         DBGU_CR;       // Control Register\r
+       AT91_REG         DBGU_MR;       // Mode Register\r
+       AT91_REG         DBGU_IER;      // Interrupt Enable Register\r
+       AT91_REG         DBGU_IDR;      // Interrupt Disable Register\r
+       AT91_REG         DBGU_IMR;      // Interrupt Mask Register\r
+       AT91_REG         DBGU_CSR;      // Channel Status Register\r
+       AT91_REG         DBGU_RHR;      // Receiver Holding Register\r
+       AT91_REG         DBGU_THR;      // Transmitter Holding Register\r
+       AT91_REG         DBGU_BRGR;     // Baud Rate Generator Register\r
+       AT91_REG         Reserved0[9];  // \r
+       AT91_REG         DBGU_FNTR;     // Force NTRST Register\r
+       AT91_REG         Reserved1[40];         // \r
+       AT91_REG         DBGU_ADDRSIZE;         // DBGU ADDRSIZE REGISTER \r
+       AT91_REG         DBGU_IPNAME1;  // DBGU IPNAME1 REGISTER \r
+       AT91_REG         DBGU_IPNAME2;  // DBGU IPNAME2 REGISTER \r
+       AT91_REG         DBGU_FEATURES;         // DBGU FEATURES REGISTER \r
+       AT91_REG         DBGU_VER;      // DBGU VERSION REGISTER \r
+       AT91_REG         DBGU_RPR;      // Receive Pointer Register\r
+       AT91_REG         DBGU_RCR;      // Receive Counter Register\r
+       AT91_REG         DBGU_TPR;      // Transmit Pointer Register\r
+       AT91_REG         DBGU_TCR;      // Transmit Counter Register\r
+       AT91_REG         DBGU_RNPR;     // Receive Next Pointer Register\r
+       AT91_REG         DBGU_RNCR;     // Receive Next Counter Register\r
+       AT91_REG         DBGU_TNPR;     // Transmit Next Pointer Register\r
+       AT91_REG         DBGU_TNCR;     // Transmit Next Counter Register\r
+       AT91_REG         DBGU_PTCR;     // PDC Transfer Control Register\r
+       AT91_REG         DBGU_PTSR;     // PDC Transfer Status Register\r
+       AT91_REG         Reserved2[6];  // \r
+       AT91_REG         DBGU_CIDR;     // Chip ID Register\r
+       AT91_REG         DBGU_EXID;     // Chip ID Extension Register\r
+} AT91S_DBGU, *AT91PS_DBGU;\r
+#else\r
+#define DBGU_CR         (AT91_CAST(AT91_REG *)         0x00000000) // (DBGU_CR) Control Register\r
+#define DBGU_MR         (AT91_CAST(AT91_REG *)         0x00000004) // (DBGU_MR) Mode Register\r
+#define DBGU_IER        (AT91_CAST(AT91_REG *)         0x00000008) // (DBGU_IER) Interrupt Enable Register\r
+#define DBGU_IDR        (AT91_CAST(AT91_REG *)         0x0000000C) // (DBGU_IDR) Interrupt Disable Register\r
+#define DBGU_IMR        (AT91_CAST(AT91_REG *)         0x00000010) // (DBGU_IMR) Interrupt Mask Register\r
+#define DBGU_CSR        (AT91_CAST(AT91_REG *)         0x00000014) // (DBGU_CSR) Channel Status Register\r
+#define DBGU_RHR        (AT91_CAST(AT91_REG *)         0x00000018) // (DBGU_RHR) Receiver Holding Register\r
+#define DBGU_THR        (AT91_CAST(AT91_REG *)         0x0000001C) // (DBGU_THR) Transmitter Holding Register\r
+#define DBGU_BRGR       (AT91_CAST(AT91_REG *)         0x00000020) // (DBGU_BRGR) Baud Rate Generator Register\r
+#define DBGU_FNTR       (AT91_CAST(AT91_REG *)         0x00000048) // (DBGU_FNTR) Force NTRST Register\r
+#define DBGU_ADDRSIZE   (AT91_CAST(AT91_REG *)         0x000000EC) // (DBGU_ADDRSIZE) DBGU ADDRSIZE REGISTER \r
+#define DBGU_IPNAME1    (AT91_CAST(AT91_REG *)         0x000000F0) // (DBGU_IPNAME1) DBGU IPNAME1 REGISTER \r
+#define DBGU_IPNAME2    (AT91_CAST(AT91_REG *)         0x000000F4) // (DBGU_IPNAME2) DBGU IPNAME2 REGISTER \r
+#define DBGU_FEATURES   (AT91_CAST(AT91_REG *)         0x000000F8) // (DBGU_FEATURES) DBGU FEATURES REGISTER \r
+#define DBGU_VER        (AT91_CAST(AT91_REG *)         0x000000FC) // (DBGU_VER) DBGU VERSION REGISTER \r
+#define DBGU_CIDR       (AT91_CAST(AT91_REG *)         0x00000140) // (DBGU_CIDR) Chip ID Register\r
+#define DBGU_EXID       (AT91_CAST(AT91_REG *)         0x00000144) // (DBGU_EXID) Chip ID Extension Register\r
+\r
+#endif\r
+// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- \r
+#define AT91C_US_RSTRX        (0x1 <<  2) // (DBGU) Reset Receiver\r
+#define AT91C_US_RSTTX        (0x1 <<  3) // (DBGU) Reset Transmitter\r
+#define AT91C_US_RXEN         (0x1 <<  4) // (DBGU) Receiver Enable\r
+#define AT91C_US_RXDIS        (0x1 <<  5) // (DBGU) Receiver Disable\r
+#define AT91C_US_TXEN         (0x1 <<  6) // (DBGU) Transmitter Enable\r
+#define AT91C_US_TXDIS        (0x1 <<  7) // (DBGU) Transmitter Disable\r
+#define AT91C_US_RSTSTA       (0x1 <<  8) // (DBGU) Reset Status Bits\r
+// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- \r
+#define AT91C_US_PAR          (0x7 <<  9) // (DBGU) Parity type\r
+#define        AT91C_US_PAR_EVEN                 (0x0 <<  9) // (DBGU) Even Parity\r
+#define        AT91C_US_PAR_ODD                  (0x1 <<  9) // (DBGU) Odd Parity\r
+#define        AT91C_US_PAR_SPACE                (0x2 <<  9) // (DBGU) Parity forced to 0 (Space)\r
+#define        AT91C_US_PAR_MARK                 (0x3 <<  9) // (DBGU) Parity forced to 1 (Mark)\r
+#define        AT91C_US_PAR_NONE                 (0x4 <<  9) // (DBGU) No Parity\r
+#define        AT91C_US_PAR_MULTI_DROP           (0x6 <<  9) // (DBGU) Multi-drop mode\r
+#define AT91C_US_CHMODE       (0x3 << 14) // (DBGU) Channel Mode\r
+#define        AT91C_US_CHMODE_NORMAL               (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.\r
+#define        AT91C_US_CHMODE_AUTO                 (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.\r
+#define        AT91C_US_CHMODE_LOCAL                (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.\r
+#define        AT91C_US_CHMODE_REMOTE               (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.\r
+// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- \r
+#define AT91C_US_RXRDY        (0x1 <<  0) // (DBGU) RXRDY Interrupt\r
+#define AT91C_US_TXRDY        (0x1 <<  1) // (DBGU) TXRDY Interrupt\r
+#define AT91C_US_ENDRX        (0x1 <<  3) // (DBGU) End of Receive Transfer Interrupt\r
+#define AT91C_US_ENDTX        (0x1 <<  4) // (DBGU) End of Transmit Interrupt\r
+#define AT91C_US_OVRE         (0x1 <<  5) // (DBGU) Overrun Interrupt\r
+#define AT91C_US_FRAME        (0x1 <<  6) // (DBGU) Framing Error Interrupt\r
+#define AT91C_US_PARE         (0x1 <<  7) // (DBGU) Parity Error Interrupt\r
+#define AT91C_US_TXEMPTY      (0x1 <<  9) // (DBGU) TXEMPTY Interrupt\r
+#define AT91C_US_TXBUFE       (0x1 << 11) // (DBGU) TXBUFE Interrupt\r
+#define AT91C_US_RXBUFF       (0x1 << 12) // (DBGU) RXBUFF Interrupt\r
+#define AT91C_US_COMM_TX      (0x1 << 30) // (DBGU) COMM_TX Interrupt\r
+#define AT91C_US_COMM_RX      (0x1 << 31) // (DBGU) COMM_RX Interrupt\r
+// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- \r
+// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- \r
+// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- \r
+// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- \r
+#define AT91C_US_FORCE_NTRST  (0x1 <<  0) // (DBGU) Force NTRST in JTAG\r
+\r
+// *****************************************************************************\r
+//              SOFTWARE API DEFINITION  FOR Parallel Input Output Controler\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_PIO {\r
+       AT91_REG         PIO_PER;       // PIO Enable Register\r
+       AT91_REG         PIO_PDR;       // PIO Disable Register\r
+       AT91_REG         PIO_PSR;       // PIO Status Register\r
+       AT91_REG         Reserved0[1];  // \r
+       AT91_REG         PIO_OER;       // Output Enable Register\r
+       AT91_REG         PIO_ODR;       // Output Disable Registerr\r
+       AT91_REG         PIO_OSR;       // Output Status Register\r
+       AT91_REG         Reserved1[1];  // \r
+       AT91_REG         PIO_IFER;      // Input Filter Enable Register\r
+       AT91_REG         PIO_IFDR;      // Input Filter Disable Register\r
+       AT91_REG         PIO_IFSR;      // Input Filter Status Register\r
+       AT91_REG         Reserved2[1];  // \r
+       AT91_REG         PIO_SODR;      // Set Output Data Register\r
+       AT91_REG         PIO_CODR;      // Clear Output Data Register\r
+       AT91_REG         PIO_ODSR;      // Output Data Status Register\r
+       AT91_REG         PIO_PDSR;      // Pin Data Status Register\r
+       AT91_REG         PIO_IER;       // Interrupt Enable Register\r
+       AT91_REG         PIO_IDR;       // Interrupt Disable Register\r
+       AT91_REG         PIO_IMR;       // Interrupt Mask Register\r
+       AT91_REG         PIO_ISR;       // Interrupt Status Register\r
+       AT91_REG         PIO_MDER;      // Multi-driver Enable Register\r
+       AT91_REG         PIO_MDDR;      // Multi-driver Disable Register\r
+       AT91_REG         PIO_MDSR;      // Multi-driver Status Register\r
+       AT91_REG         Reserved3[1];  // \r
+       AT91_REG         PIO_PPUDR;     // Pull-up Disable Register\r
+       AT91_REG         PIO_PPUER;     // Pull-up Enable Register\r
+       AT91_REG         PIO_PPUSR;     // Pull-up Status Register\r
+       AT91_REG         Reserved4[1];  // \r
+       AT91_REG         PIO_ABSR;      // Peripheral AB Select Register\r
+       AT91_REG         Reserved5[3];  // \r
+       AT91_REG         PIO_SCIFSR;    // System Clock Glitch Input Filter Select Register\r
+       AT91_REG         PIO_DIFSR;     // Debouncing Input Filter Select Register\r
+       AT91_REG         PIO_IFDGSR;    // Glitch or Debouncing Input Filter Clock Selection Status Register\r
+       AT91_REG         PIO_SCDR;      // Slow Clock Divider Debouncing Register\r
+       AT91_REG         Reserved6[4];  // \r
+       AT91_REG         PIO_OWER;      // Output Write Enable Register\r
+       AT91_REG         PIO_OWDR;      // Output Write Disable Register\r
+       AT91_REG         PIO_OWSR;      // Output Write Status Register\r
+       AT91_REG         Reserved7[1];  // \r
+       AT91_REG         PIO_AIMER;     // Additional Interrupt Modes Enable Register\r
+       AT91_REG         PIO_AIMDR;     // Additional Interrupt Modes Disables Register\r
+       AT91_REG         PIO_AIMMR;     // Additional Interrupt Modes Mask Register\r
+       AT91_REG         Reserved8[1];  // \r
+       AT91_REG         PIO_ESR;       // Edge Select Register\r
+       AT91_REG         PIO_LSR;       // Level Select Register\r
+       AT91_REG         PIO_ELSR;      // Edge/Level Status Register\r
+       AT91_REG         Reserved9[1];  // \r
+       AT91_REG         PIO_FELLSR;    // Falling Edge/Low Level Select Register\r
+       AT91_REG         PIO_REHLSR;    // Rising Edge/ High Level Select Register\r
+       AT91_REG         PIO_FRLHSR;    // Fall/Rise - Low/High Status Register\r
+       AT91_REG         Reserved10[1];         // \r
+       AT91_REG         PIO_LOCKSR;    // Lock Status Register\r
+       AT91_REG         Reserved11[6];         // \r
+       AT91_REG         PIO_VER;       // PIO VERSION REGISTER \r
+       AT91_REG         Reserved12[8];         // \r
+       AT91_REG         PIO_KER;       // Keypad Controller Enable Register\r
+       AT91_REG         PIO_KRCR;      // Keypad Controller Row Column Register\r
+       AT91_REG         PIO_KDR;       // Keypad Controller Debouncing Register\r
+       AT91_REG         Reserved13[1];         // \r
+       AT91_REG         PIO_KIER;      // Keypad Controller Interrupt Enable Register\r
+       AT91_REG         PIO_KIDR;      // Keypad Controller Interrupt Disable Register\r
+       AT91_REG         PIO_KIMR;      // Keypad Controller Interrupt Mask Register\r
+       AT91_REG         PIO_KSR;       // Keypad Controller Status Register\r
+       AT91_REG         PIO_KKPR;      // Keypad Controller Key Press Register\r
+       AT91_REG         PIO_KKRR;      // Keypad Controller Key Release Register\r
+} AT91S_PIO, *AT91PS_PIO;\r
+#else\r
+#define PIO_PER         (AT91_CAST(AT91_REG *)         0x00000000) // (PIO_PER) PIO Enable Register\r
+#define PIO_PDR         (AT91_CAST(AT91_REG *)         0x00000004) // (PIO_PDR) PIO Disable Register\r
+#define PIO_PSR         (AT91_CAST(AT91_REG *)         0x00000008) // (PIO_PSR) PIO Status Register\r
+#define PIO_OER         (AT91_CAST(AT91_REG *)         0x00000010) // (PIO_OER) Output Enable Register\r
+#define PIO_ODR         (AT91_CAST(AT91_REG *)         0x00000014) // (PIO_ODR) Output Disable Registerr\r
+#define PIO_OSR         (AT91_CAST(AT91_REG *)         0x00000018) // (PIO_OSR) Output Status Register\r
+#define PIO_IFER        (AT91_CAST(AT91_REG *)         0x00000020) // (PIO_IFER) Input Filter Enable Register\r
+#define PIO_IFDR        (AT91_CAST(AT91_REG *)         0x00000024) // (PIO_IFDR) Input Filter Disable Register\r
+#define PIO_IFSR        (AT91_CAST(AT91_REG *)         0x00000028) // (PIO_IFSR) Input Filter Status Register\r
+#define PIO_SODR        (AT91_CAST(AT91_REG *)         0x00000030) // (PIO_SODR) Set Output Data Register\r
+#define PIO_CODR        (AT91_CAST(AT91_REG *)         0x00000034) // (PIO_CODR) Clear Output Data Register\r
+#define PIO_ODSR        (AT91_CAST(AT91_REG *)         0x00000038) // (PIO_ODSR) Output Data Status Register\r
+#define PIO_PDSR        (AT91_CAST(AT91_REG *)         0x0000003C) // (PIO_PDSR) Pin Data Status Register\r
+#define PIO_IER         (AT91_CAST(AT91_REG *)         0x00000040) // (PIO_IER) Interrupt Enable Register\r
+#define PIO_IDR         (AT91_CAST(AT91_REG *)         0x00000044) // (PIO_IDR) Interrupt Disable Register\r
+#define PIO_IMR         (AT91_CAST(AT91_REG *)         0x00000048) // (PIO_IMR) Interrupt Mask Register\r
+#define PIO_ISR         (AT91_CAST(AT91_REG *)         0x0000004C) // (PIO_ISR) Interrupt Status Register\r
+#define PIO_MDER        (AT91_CAST(AT91_REG *)         0x00000050) // (PIO_MDER) Multi-driver Enable Register\r
+#define PIO_MDDR        (AT91_CAST(AT91_REG *)         0x00000054) // (PIO_MDDR) Multi-driver Disable Register\r
+#define PIO_MDSR        (AT91_CAST(AT91_REG *)         0x00000058) // (PIO_MDSR) Multi-driver Status Register\r
+#define PIO_PPUDR       (AT91_CAST(AT91_REG *)         0x00000060) // (PIO_PPUDR) Pull-up Disable Register\r
+#define PIO_PPUER       (AT91_CAST(AT91_REG *)         0x00000064) // (PIO_PPUER) Pull-up Enable Register\r
+#define PIO_PPUSR       (AT91_CAST(AT91_REG *)         0x00000068) // (PIO_PPUSR) Pull-up Status Register\r
+#define PIO_ABSR        (AT91_CAST(AT91_REG *)         0x00000070) // (PIO_ABSR) Peripheral AB Select Register\r
+#define PIO_SCIFSR      (AT91_CAST(AT91_REG *)         0x00000080) // (PIO_SCIFSR) System Clock Glitch Input Filter Select Register\r
+#define PIO_DIFSR       (AT91_CAST(AT91_REG *)         0x00000084) // (PIO_DIFSR) Debouncing Input Filter Select Register\r
+#define PIO_IFDGSR      (AT91_CAST(AT91_REG *)         0x00000088) // (PIO_IFDGSR) Glitch or Debouncing Input Filter Clock Selection Status Register\r
+#define PIO_SCDR        (AT91_CAST(AT91_REG *)         0x0000008C) // (PIO_SCDR) Slow Clock Divider Debouncing Register\r
+#define PIO_OWER        (AT91_CAST(AT91_REG *)         0x000000A0) // (PIO_OWER) Output Write Enable Register\r
+#define PIO_OWDR        (AT91_CAST(AT91_REG *)         0x000000A4) // (PIO_OWDR) Output Write Disable Register\r
+#define PIO_OWSR        (AT91_CAST(AT91_REG *)         0x000000A8) // (PIO_OWSR) Output Write Status Register\r
+#define PIO_AIMER       (AT91_CAST(AT91_REG *)         0x000000B0) // (PIO_AIMER) Additional Interrupt Modes Enable Register\r
+#define PIO_AIMDR       (AT91_CAST(AT91_REG *)         0x000000B4) // (PIO_AIMDR) Additional Interrupt Modes Disables Register\r
+#define PIO_AIMMR       (AT91_CAST(AT91_REG *)         0x000000B8) // (PIO_AIMMR) Additional Interrupt Modes Mask Register\r
+#define PIO_ESR         (AT91_CAST(AT91_REG *)         0x000000C0) // (PIO_ESR) Edge Select Register\r
+#define PIO_LSR         (AT91_CAST(AT91_REG *)         0x000000C4) // (PIO_LSR) Level Select Register\r
+#define PIO_ELSR        (AT91_CAST(AT91_REG *)         0x000000C8) // (PIO_ELSR) Edge/Level Status Register\r
+#define PIO_FELLSR      (AT91_CAST(AT91_REG *)         0x000000D0) // (PIO_FELLSR) Falling Edge/Low Level Select Register\r
+#define PIO_REHLSR      (AT91_CAST(AT91_REG *)         0x000000D4) // (PIO_REHLSR) Rising Edge/ High Level Select Register\r
+#define PIO_FRLHSR      (AT91_CAST(AT91_REG *)         0x000000D8) // (PIO_FRLHSR) Fall/Rise - Low/High Status Register\r
+#define PIO_LOCKSR      (AT91_CAST(AT91_REG *)         0x000000E0) // (PIO_LOCKSR) Lock Status Register\r
+#define PIO_VER         (AT91_CAST(AT91_REG *)         0x000000FC) // (PIO_VER) PIO VERSION REGISTER \r
+#define PIO_KER         (AT91_CAST(AT91_REG *)         0x00000120) // (PIO_KER) Keypad Controller Enable Register\r
+#define PIO_KRCR        (AT91_CAST(AT91_REG *)         0x00000124) // (PIO_KRCR) Keypad Controller Row Column Register\r
+#define PIO_KDR         (AT91_CAST(AT91_REG *)         0x00000128) // (PIO_KDR) Keypad Controller Debouncing Register\r
+#define PIO_KIER        (AT91_CAST(AT91_REG *)         0x00000130) // (PIO_KIER) Keypad Controller Interrupt Enable Register\r
+#define PIO_KIDR        (AT91_CAST(AT91_REG *)         0x00000134) // (PIO_KIDR) Keypad Controller Interrupt Disable Register\r
+#define PIO_KIMR        (AT91_CAST(AT91_REG *)         0x00000138) // (PIO_KIMR) Keypad Controller Interrupt Mask Register\r
+#define PIO_KSR         (AT91_CAST(AT91_REG *)         0x0000013C) // (PIO_KSR) Keypad Controller Status Register\r
+#define PIO_KKPR        (AT91_CAST(AT91_REG *)         0x00000140) // (PIO_KKPR) Keypad Controller Key Press Register\r
+#define PIO_KKRR        (AT91_CAST(AT91_REG *)         0x00000144) // (PIO_KKRR) Keypad Controller Key Release Register\r
+\r
+#endif\r
+// -------- PIO_KER : (PIO Offset: 0x120) Keypad Controller Enable Register -------- \r
+#define AT91C_PIO_KCE         (0x1 <<  0) // (PIO) Keypad Controller Enable\r
+// -------- PIO_KRCR : (PIO Offset: 0x124) Keypad Controller Row Column Register -------- \r
+#define AT91C_PIO_NBR         (0x7 <<  0) // (PIO) Number of Columns of the Keypad Matrix\r
+#define AT91C_PIO_NBC         (0x7 <<  8) // (PIO) Number of Rows of the Keypad Matrix\r
+// -------- PIO_KDR : (PIO Offset: 0x128) Keypad Controller Debouncing Register -------- \r
+#define AT91C_PIO_DBC         (0x3FF <<  0) // (PIO) Debouncing Value\r
+// -------- PIO_KIER : (PIO Offset: 0x130) Keypad Controller Interrupt Enable Register -------- \r
+#define AT91C_PIO_KPR         (0x1 <<  0) // (PIO) Key Press Interrupt Enable\r
+#define AT91C_PIO_KRL         (0x1 <<  1) // (PIO) Key Release Interrupt Enable\r
+// -------- PIO_KIDR : (PIO Offset: 0x134) Keypad Controller Interrupt Disable Register -------- \r
+// -------- PIO_KIMR : (PIO Offset: 0x138) Keypad Controller Interrupt Mask Register -------- \r
+// -------- PIO_KSR : (PIO Offset: 0x13c) Keypad Controller Status Register -------- \r
+#define AT91C_PIO_NBKPR       (0x3 <<  8) // (PIO) Number of Simultaneous Key Presses\r
+#define AT91C_PIO_NBKRL       (0x3 << 16) // (PIO) Number of Simultaneous Key Releases\r
+// -------- PIO_KKPR : (PIO Offset: 0x140) Keypad Controller Key Press Register -------- \r
+#define AT91C_KEY0ROW         (0x7 <<  0) // (PIO) Row index of the first detected Key Press\r
+#define AT91C_KEY0COL         (0x7 <<  4) // (PIO) Column index of the first detected Key Press\r
+#define AT91C_KEY1ROW         (0x7 <<  8) // (PIO) Row index of the second detected Key Press\r
+#define AT91C_KEY1COL         (0x7 << 12) // (PIO) Column index of the second detected Key Press\r
+#define AT91C_KEY2ROW         (0x7 << 16) // (PIO) Row index of the third detected Key Press\r
+#define AT91C_KEY2COL         (0x7 << 20) // (PIO) Column index of the third detected Key Press\r
+#define AT91C_KEY3ROW         (0x7 << 24) // (PIO) Row index of the fourth detected Key Press\r
+#define AT91C_KEY3COL         (0x7 << 28) // (PIO) Column index of the fourth detected Key Press\r
+// -------- PIO_KKRR : (PIO Offset: 0x144) Keypad Controller Key Release Register -------- \r
+\r
+// *****************************************************************************\r
+//              SOFTWARE API DEFINITION  FOR Power Management Controler\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_PMC {\r
+       AT91_REG         PMC_SCER;      // System Clock Enable Register\r
+       AT91_REG         PMC_SCDR;      // System Clock Disable Register\r
+       AT91_REG         PMC_SCSR;      // System Clock Status Register\r
+       AT91_REG         Reserved0[1];  // \r
+       AT91_REG         PMC_PCER;      // Peripheral Clock Enable Register\r
+       AT91_REG         PMC_PCDR;      // Peripheral Clock Disable Register\r
+       AT91_REG         PMC_PCSR;      // Peripheral Clock Status Register\r
+       AT91_REG         PMC_UCKR;      // UTMI Clock Configuration Register\r
+       AT91_REG         PMC_MOR;       // Main Oscillator Register\r
+       AT91_REG         PMC_MCFR;      // Main Clock  Frequency Register\r
+       AT91_REG         PMC_PLLAR;     // PLL Register\r
+       AT91_REG         Reserved1[1];  // \r
+       AT91_REG         PMC_MCKR;      // Master Clock Register\r
+       AT91_REG         Reserved2[3];  // \r
+       AT91_REG         PMC_PCKR[8];   // Programmable Clock Register\r
+       AT91_REG         PMC_IER;       // Interrupt Enable Register\r
+       AT91_REG         PMC_IDR;       // Interrupt Disable Register\r
+       AT91_REG         PMC_SR;        // Status Register\r
+       AT91_REG         PMC_IMR;       // Interrupt Mask Register\r
+       AT91_REG         PMC_FSMR;      // Fast Startup Mode Register\r
+       AT91_REG         PMC_FSPR;      // Fast Startup Polarity Register\r
+       AT91_REG         PMC_FOCR;      // Fault Output Clear Register\r
+       AT91_REG         Reserved3[28];         // \r
+       AT91_REG         PMC_ADDRSIZE;  // PMC ADDRSIZE REGISTER \r
+       AT91_REG         PMC_IPNAME1;   // PMC IPNAME1 REGISTER \r
+       AT91_REG         PMC_IPNAME2;   // PMC IPNAME2 REGISTER \r
+       AT91_REG         PMC_FEATURES;  // PMC FEATURES REGISTER \r
+       AT91_REG         PMC_VER;       // APMC VERSION REGISTER\r
+} AT91S_PMC, *AT91PS_PMC;\r
+#else\r
+#define PMC_SCER        (AT91_CAST(AT91_REG *)         0x00000000) // (PMC_SCER) System Clock Enable Register\r
+#define PMC_SCDR        (AT91_CAST(AT91_REG *)         0x00000004) // (PMC_SCDR) System Clock Disable Register\r
+#define PMC_SCSR        (AT91_CAST(AT91_REG *)         0x00000008) // (PMC_SCSR) System Clock Status Register\r
+#define PMC_PCER        (AT91_CAST(AT91_REG *)         0x00000010) // (PMC_PCER) Peripheral Clock Enable Register\r
+#define PMC_PCDR        (AT91_CAST(AT91_REG *)         0x00000014) // (PMC_PCDR) Peripheral Clock Disable Register\r
+#define PMC_PCSR        (AT91_CAST(AT91_REG *)         0x00000018) // (PMC_PCSR) Peripheral Clock Status Register\r
+#define CKGR_UCKR       (AT91_CAST(AT91_REG *)         0x0000001C) // (CKGR_UCKR) UTMI Clock Configuration Register\r
+#define CKGR_MOR        (AT91_CAST(AT91_REG *)         0x00000020) // (CKGR_MOR) Main Oscillator Register\r
+#define CKGR_MCFR       (AT91_CAST(AT91_REG *)         0x00000024) // (CKGR_MCFR) Main Clock  Frequency Register\r
+#define CKGR_PLLAR      (AT91_CAST(AT91_REG *)         0x00000028) // (CKGR_PLLAR) PLL Register\r
+#define PMC_MCKR        (AT91_CAST(AT91_REG *)         0x00000030) // (PMC_MCKR) Master Clock Register\r
+#define PMC_PCKR        (AT91_CAST(AT91_REG *)         0x00000040) // (PMC_PCKR) Programmable Clock Register\r
+#define PMC_IER         (AT91_CAST(AT91_REG *)         0x00000060) // (PMC_IER) Interrupt Enable Register\r
+#define PMC_IDR         (AT91_CAST(AT91_REG *)         0x00000064) // (PMC_IDR) Interrupt Disable Register\r
+#define PMC_SR          (AT91_CAST(AT91_REG *)         0x00000068) // (PMC_SR) Status Register\r
+#define PMC_IMR         (AT91_CAST(AT91_REG *)         0x0000006C) // (PMC_IMR) Interrupt Mask Register\r
+#define PMC_FSMR        (AT91_CAST(AT91_REG *)         0x00000070) // (PMC_FSMR) Fast Startup Mode Register\r
+#define PMC_FSPR        (AT91_CAST(AT91_REG *)         0x00000074) // (PMC_FSPR) Fast Startup Polarity Register\r
+#define PMC_FOCR        (AT91_CAST(AT91_REG *)         0x00000078) // (PMC_FOCR) Fault Output Clear Register\r
+#define PMC_ADDRSIZE    (AT91_CAST(AT91_REG *)         0x000000EC) // (PMC_ADDRSIZE) PMC ADDRSIZE REGISTER \r
+#define PMC_IPNAME1     (AT91_CAST(AT91_REG *)         0x000000F0) // (PMC_IPNAME1) PMC IPNAME1 REGISTER \r
+#define PMC_IPNAME2     (AT91_CAST(AT91_REG *)         0x000000F4) // (PMC_IPNAME2) PMC IPNAME2 REGISTER \r
+#define PMC_FEATURES    (AT91_CAST(AT91_REG *)         0x000000F8) // (PMC_FEATURES) PMC FEATURES REGISTER \r
+#define PMC_VER         (AT91_CAST(AT91_REG *)         0x000000FC) // (PMC_VER) APMC VERSION REGISTER\r
+\r
+#endif\r
+// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- \r
+#define AT91C_PMC_PCK         (0x1 <<  0) // (PMC) Processor Clock\r
+#define AT91C_PMC_PCK0        (0x1 <<  8) // (PMC) Programmable Clock Output\r
+#define AT91C_PMC_PCK1        (0x1 <<  9) // (PMC) Programmable Clock Output\r
+#define AT91C_PMC_PCK2        (0x1 << 10) // (PMC) Programmable Clock Output\r
+// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- \r
+// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- \r
+// -------- CKGR_UCKR : (PMC Offset: 0x1c) UTMI Clock Configuration Register -------- \r
+#define AT91C_CKGR_UPLLEN     (0x1 << 16) // (PMC) UTMI PLL Enable\r
+#define        AT91C_CKGR_UPLLEN_DISABLED             (0x0 << 16) // (PMC) The UTMI PLL is disabled\r
+#define        AT91C_CKGR_UPLLEN_ENABLED              (0x1 << 16) // (PMC) The UTMI PLL is enabled\r
+#define AT91C_CKGR_UPLLCOUNT  (0xF << 20) // (PMC) UTMI Oscillator Start-up Time\r
+#define AT91C_CKGR_BIASEN     (0x1 << 24) // (PMC) UTMI BIAS Enable\r
+#define        AT91C_CKGR_BIASEN_DISABLED             (0x0 << 24) // (PMC) The UTMI BIAS is disabled\r
+#define        AT91C_CKGR_BIASEN_ENABLED              (0x1 << 24) // (PMC) The UTMI BIAS is enabled\r
+#define AT91C_CKGR_BIASCOUNT  (0xF << 28) // (PMC) UTMI BIAS Start-up Time\r
+// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- \r
+#define AT91C_CKGR_MOSCXTEN   (0x1 <<  0) // (PMC) Main Crystal Oscillator Enable\r
+#define AT91C_CKGR_MOSCXTBY   (0x1 <<  1) // (PMC) Main Crystal Oscillator Bypass\r
+#define AT91C_CKGR_WAITMODE   (0x1 <<  2) // (PMC) Main Crystal Oscillator Bypass\r
+#define AT91C_CKGR_MOSCRCEN   (0x1 <<  3) // (PMC) Main On-Chip RC Oscillator Enable\r
+#define AT91C_CKGR_MOSCRCF    (0x7 <<  4) // (PMC) Main On-Chip RC Oscillator Frequency Selection\r
+#define AT91C_CKGR_MOSCXTST   (0xFF <<  8) // (PMC) Main Crystal Oscillator Start-up Time\r
+#define AT91C_CKGR_KEY        (0xFF << 16) // (PMC) Clock Generator Controller Writing Protection Key\r
+#define AT91C_CKGR_MOSCSEL    (0x1 << 24) // (PMC) Main Oscillator Selection\r
+#define AT91C_CKGR_CFDEN      (0x1 << 25) // (PMC) Clock Failure Detector Enable\r
+// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- \r
+#define AT91C_CKGR_MAINF      (0xFFFF <<  0) // (PMC) Main Clock Frequency\r
+#define AT91C_CKGR_MAINRDY    (0x1 << 16) // (PMC) Main Clock Ready\r
+// -------- CKGR_PLLAR : (PMC Offset: 0x28) PLL A Register -------- \r
+#define AT91C_CKGR_DIVA       (0xFF <<  0) // (PMC) Divider Selected\r
+#define        AT91C_CKGR_DIVA_0                    (0x0) // (PMC) Divider output is 0\r
+#define        AT91C_CKGR_DIVA_BYPASS               (0x1) // (PMC) Divider is bypassed\r
+#define AT91C_CKGR_PLLACOUNT  (0x3F <<  8) // (PMC) PLLA Counter\r
+#define AT91C_CKGR_STMODE     (0x3 << 14) // (PMC) Start Mode\r
+#define        AT91C_CKGR_STMODE_0                    (0x0 << 14) // (PMC) Fast startup\r
+#define        AT91C_CKGR_STMODE_1                    (0x1 << 14) // (PMC) Reserved\r
+#define        AT91C_CKGR_STMODE_2                    (0x2 << 14) // (PMC) Normal startup\r
+#define        AT91C_CKGR_STMODE_3                    (0x3 << 14) // (PMC) Reserved\r
+#define AT91C_CKGR_MULA       (0x7FF << 16) // (PMC) PLL Multiplier\r
+#define AT91C_CKGR_SRC        (0x1 << 29) // (PMC) \r
+// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- \r
+#define AT91C_PMC_CSS         (0x7 <<  0) // (PMC) Programmable Clock Selection\r
+#define        AT91C_PMC_CSS_SLOW_CLK             (0x0) // (PMC) Slow Clock is selected\r
+#define        AT91C_PMC_CSS_MAIN_CLK             (0x1) // (PMC) Main Clock is selected\r
+#define        AT91C_PMC_CSS_PLLA_CLK             (0x2) // (PMC) Clock from PLL A is selected\r
+#define        AT91C_PMC_CSS_UPLL_CLK             (0x3) // (PMC) Clock from UPLL is selected\r
+#define        AT91C_PMC_CSS_SYS_CLK              (0x4) // (PMC) System clock is selected\r
+#define AT91C_PMC_PRES        (0x7 <<  4) // (PMC) Programmable Clock Prescaler\r
+#define        AT91C_PMC_PRES_CLK                  (0x0 <<  4) // (PMC) Selected clock\r
+#define        AT91C_PMC_PRES_CLK_2                (0x1 <<  4) // (PMC) Selected clock divided by 2\r
+#define        AT91C_PMC_PRES_CLK_4                (0x2 <<  4) // (PMC) Selected clock divided by 4\r
+#define        AT91C_PMC_PRES_CLK_8                (0x3 <<  4) // (PMC) Selected clock divided by 8\r
+#define        AT91C_PMC_PRES_CLK_16               (0x4 <<  4) // (PMC) Selected clock divided by 16\r
+#define        AT91C_PMC_PRES_CLK_32               (0x5 <<  4) // (PMC) Selected clock divided by 32\r
+#define        AT91C_PMC_PRES_CLK_64               (0x6 <<  4) // (PMC) Selected clock divided by 64\r
+#define        AT91C_PMC_PRES_CLK_6                (0x7 <<  4) // (PMC) Selected clock divided by 6\r
+// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- \r
+// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- \r
+#define AT91C_PMC_MOSCXTS     (0x1 <<  0) // (PMC) Main Crystal Oscillator Status/Enable/Disable/Mask\r
+#define AT91C_PMC_LOCKA       (0x1 <<  1) // (PMC) PLL A Status/Enable/Disable/Mask\r
+#define AT91C_PMC_MCKRDY      (0x1 <<  3) // (PMC) Master Clock Status/Enable/Disable/Mask\r
+#define AT91C_PMC_LOCKU       (0x1 <<  6) // (PMC) PLL UTMI Status/Enable/Disable/Mask\r
+#define AT91C_PMC_PCKRDY0     (0x1 <<  8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask\r
+#define AT91C_PMC_PCKRDY1     (0x1 <<  9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask\r
+#define AT91C_PMC_PCKRDY2     (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask\r
+#define AT91C_PMC_MOSCSELS    (0x1 << 16) // (PMC) Main Oscillator Selection Status\r
+#define AT91C_PMC_MOSCRCS     (0x1 << 17) // (PMC) Main On-Chip RC Oscillator Status\r
+#define AT91C_PMC_CFDEV       (0x1 << 18) // (PMC) Clock Failure Detector Event\r
+// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- \r
+// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- \r
+#define AT91C_PMC_OSCSELS     (0x1 <<  7) // (PMC) Slow Clock Oscillator Selection\r
+#define AT91C_PMC_CFDS        (0x1 << 19) // (PMC) Clock Failure Detector Status\r
+#define AT91C_PMC_FOS         (0x1 << 20) // (PMC) Clock Failure Detector Fault Output Status\r
+// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- \r
+// -------- PMC_FSMR : (PMC Offset: 0x70) Fast Startup Mode Register -------- \r
+#define AT91C_PMC_FSTT        (0xFFFF <<  0) // (PMC) Fast Start-up Input Enable 0 to 15\r
+#define AT91C_PMC_RTTAL       (0x1 << 16) // (PMC) RTT Alarm Enable\r
+#define AT91C_PMC_RTCAL       (0x1 << 17) // (PMC) RTC Alarm Enable\r
+#define AT91C_PMC_USBAL       (0x1 << 18) // (PMC) USB Alarm Enable\r
+#define AT91C_PMC_LPM         (0x1 << 20) // (PMC) Low Power Mode\r
+// -------- PMC_FSPR : (PMC Offset: 0x74) Fast Startup Polarity Register -------- \r
+#define AT91C_PMC_FSTP        (0xFFFF <<  0) // (PMC) Fast Start-up Input Polarity 0 to 15\r
+// -------- PMC_FOCR : (PMC Offset: 0x78) Fault Output Clear Register -------- \r
+#define AT91C_PMC_FOCLR       (0x1 <<  0) // (PMC) Fault Output Clear\r
+\r
+// *****************************************************************************\r
+//              SOFTWARE API DEFINITION  FOR Clock Generator Controler\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_CKGR {\r
+       AT91_REG         CKGR_UCKR;     // UTMI Clock Configuration Register\r
+       AT91_REG         CKGR_MOR;      // Main Oscillator Register\r
+       AT91_REG         CKGR_MCFR;     // Main Clock  Frequency Register\r
+       AT91_REG         CKGR_PLLAR;    // PLL Register\r
+} AT91S_CKGR, *AT91PS_CKGR;\r
+#else\r
+\r
+#endif\r
+// -------- CKGR_UCKR : (CKGR Offset: 0x0) UTMI Clock Configuration Register -------- \r
+// -------- CKGR_MOR : (CKGR Offset: 0x4) Main Oscillator Register -------- \r
+// -------- CKGR_MCFR : (CKGR Offset: 0x8) Main Clock Frequency Register -------- \r
+// -------- CKGR_PLLAR : (CKGR Offset: 0xc) PLL A Register -------- \r
+\r
+// *****************************************************************************\r
+//              SOFTWARE API DEFINITION  FOR Reset Controller Interface\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_RSTC {\r
+       AT91_REG         RSTC_RCR;      // Reset Control Register\r
+       AT91_REG         RSTC_RSR;      // Reset Status Register\r
+       AT91_REG         RSTC_RMR;      // Reset Mode Register\r
+       AT91_REG         Reserved0[60];         // \r
+       AT91_REG         RSTC_VER;      // Version Register\r
+} AT91S_RSTC, *AT91PS_RSTC;\r
+#else\r
+#define RSTC_RCR        (AT91_CAST(AT91_REG *)         0x00000000) // (RSTC_RCR) Reset Control Register\r
+#define RSTC_RSR        (AT91_CAST(AT91_REG *)         0x00000004) // (RSTC_RSR) Reset Status Register\r
+#define RSTC_RMR        (AT91_CAST(AT91_REG *)         0x00000008) // (RSTC_RMR) Reset Mode Register\r
+#define RSTC_VER        (AT91_CAST(AT91_REG *)         0x000000FC) // (RSTC_VER) Version Register\r
+\r
+#endif\r
+// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- \r
+#define AT91C_RSTC_PROCRST    (0x1 <<  0) // (RSTC) Processor Reset\r
+#define AT91C_RSTC_ICERST     (0x1 <<  1) // (RSTC) ICE Interface Reset\r
+#define AT91C_RSTC_PERRST     (0x1 <<  2) // (RSTC) Peripheral Reset\r
+#define AT91C_RSTC_EXTRST     (0x1 <<  3) // (RSTC) External Reset\r
+#define AT91C_RSTC_KEY        (0xFF << 24) // (RSTC) Password\r
+// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- \r
+#define AT91C_RSTC_URSTS      (0x1 <<  0) // (RSTC) User Reset Status\r
+#define AT91C_RSTC_RSTTYP     (0x7 <<  8) // (RSTC) Reset Type\r
+#define        AT91C_RSTC_RSTTYP_GENERAL              (0x0 <<  8) // (RSTC) General reset. Both VDDCORE and VDDBU rising.\r
+#define        AT91C_RSTC_RSTTYP_WAKEUP               (0x1 <<  8) // (RSTC) WakeUp Reset. VDDCORE rising.\r
+#define        AT91C_RSTC_RSTTYP_WATCHDOG             (0x2 <<  8) // (RSTC) Watchdog Reset. Watchdog overflow occured.\r
+#define        AT91C_RSTC_RSTTYP_SOFTWARE             (0x3 <<  8) // (RSTC) Software Reset. Processor reset required by the software.\r
+#define        AT91C_RSTC_RSTTYP_USER                 (0x4 <<  8) // (RSTC) User Reset. NRST pin detected low.\r
+#define AT91C_RSTC_NRSTL      (0x1 << 16) // (RSTC) NRST pin level\r
+#define AT91C_RSTC_SRCMP      (0x1 << 17) // (RSTC) Software Reset Command in Progress.\r
+// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- \r
+#define AT91C_RSTC_URSTEN     (0x1 <<  0) // (RSTC) User Reset Enable\r
+#define AT91C_RSTC_URSTIEN    (0x1 <<  4) // (RSTC) User Reset Interrupt Enable\r
+#define AT91C_RSTC_ERSTL      (0xF <<  8) // (RSTC) User Reset Enable\r
+\r
+// *****************************************************************************\r
+//              SOFTWARE API DEFINITION  FOR Supply Controller Interface\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_SUPC {\r
+       AT91_REG         SUPC_CR;       // Control Register\r
+       AT91_REG         SUPC_BOMR;     // Brown Out Mode Register\r
+       AT91_REG         SUPC_MR;       // Mode Register\r
+       AT91_REG         SUPC_WUMR;     // Wake Up Mode Register\r
+       AT91_REG         SUPC_WUIR;     // Wake Up Inputs Register\r
+       AT91_REG         SUPC_SR;       // Status Register\r
+       AT91_REG         SUPC_FWUTR;    // Flash Wake-up Timer Register\r
+} AT91S_SUPC, *AT91PS_SUPC;\r
+#else\r
+#define SUPC_CR         (AT91_CAST(AT91_REG *)         0x00000000) // (SUPC_CR) Control Register\r
+#define SUPC_BOMR       (AT91_CAST(AT91_REG *)         0x00000004) // (SUPC_BOMR) Brown Out Mode Register\r
+#define SUPC_MR         (AT91_CAST(AT91_REG *)         0x00000008) // (SUPC_MR) Mode Register\r
+#define SUPC_WUMR       (AT91_CAST(AT91_REG *)         0x0000000C) // (SUPC_WUMR) Wake Up Mode Register\r
+#define SUPC_WUIR       (AT91_CAST(AT91_REG *)         0x00000010) // (SUPC_WUIR) Wake Up Inputs Register\r
+#define SUPC_SR         (AT91_CAST(AT91_REG *)         0x00000014) // (SUPC_SR) Status Register\r
+#define SUPC_FWUTR      (AT91_CAST(AT91_REG *)         0x00000018) // (SUPC_FWUTR) Flash Wake-up Timer Register\r
+\r
+#endif\r
+// -------- SUPC_CR : (SUPC Offset: 0x0) Control Register -------- \r
+#define AT91C_SUPC_SHDW       (0x1 <<  0) // (SUPC) Shut Down Command\r
+#define AT91C_SUPC_SHDWEOF    (0x1 <<  1) // (SUPC) Shut Down after End Of Frame\r
+#define AT91C_SUPC_VROFF      (0x1 <<  2) // (SUPC) Voltage Regulator Off\r
+#define AT91C_SUPC_XTALSEL    (0x1 <<  3) // (SUPC) Crystal Oscillator Select\r
+#define AT91C_SUPC_KEY        (0xFF << 24) // (SUPC) Supply Controller Writing Protection Key\r
+// -------- SUPC_BOMR : (SUPC Offset: 0x4) Brown Out Mode Register -------- \r
+#define AT91C_SUPC_BODTH      (0xF <<  0) // (SUPC) Brown Out Threshold\r
+#define AT91C_SUPC_BODSMPL    (0x7 <<  8) // (SUPC) Brown Out Sampling Period\r
+#define        AT91C_SUPC_BODSMPL_DISABLED             (0x0 <<  8) // (SUPC) Brown Out Detector disabled\r
+#define        AT91C_SUPC_BODSMPL_CONTINUOUS           (0x1 <<  8) // (SUPC) Continuous Brown Out Detector\r
+#define        AT91C_SUPC_BODSMPL_32_SLCK              (0x2 <<  8) // (SUPC) Brown Out Detector enabled one SLCK period every 32 SLCK periods\r
+#define        AT91C_SUPC_BODSMPL_256_SLCK             (0x3 <<  8) // (SUPC) Brown Out Detector enabled one SLCK period every 256 SLCK periods\r
+#define        AT91C_SUPC_BODSMPL_2048_SLCK            (0x4 <<  8) // (SUPC) Brown Out Detector enabled one SLCK period every 2048 SLCK periods\r
+#define AT91C_SUPC_BODRSTEN   (0x1 << 12) // (SUPC) Brownout Reset Enable\r
+// -------- SUPC_MR : (SUPC Offset: 0x8) Supply Controller Mode Register -------- \r
+#define AT91C_SUPC_LCDOUT     (0xF <<  0) // (SUPC) LCD Charge Pump Output Voltage Selection\r
+#define AT91C_SUPC_LCDMODE    (0x3 <<  4) // (SUPC) Segment LCD Supply Mode\r
+#define        AT91C_SUPC_LCDMODE_OFF                  (0x0 <<  4) // (SUPC) The internal and external supply sources are both deselected and the on-chip charge pump is turned off\r
+#define        AT91C_SUPC_LCDMODE_OFF_AFTER_EOF        (0x1 <<  4) // (SUPC) At the End Of Frame from LCD controller, the internal and external supply sources are both deselected and the on-chip charge pump is turned off\r
+#define        AT91C_SUPC_LCDMODE_EXTERNAL             (0x2 <<  4) // (SUPC) The external supply source is selected\r
+#define        AT91C_SUPC_LCDMODE_INTERNAL             (0x3 <<  4) // (SUPC) The internal supply source is selected and the on-chip charge pump is turned on\r
+#define AT91C_SUPC_VRDEEP     (0x1 <<  8) // (SUPC) Voltage Regulator Deep Mode\r
+#define AT91C_SUPC_VRVDD      (0x7 <<  9) // (SUPC) Voltage Regulator Output Voltage Selection\r
+#define AT91C_SUPC_VRRSTEN    (0x1 << 12) // (SUPC) Voltage Regulation Loss Reset Enable\r
+#define AT91C_SUPC_GPBRON     (0x1 << 16) // (SUPC) GPBR ON\r
+#define AT91C_SUPC_SRAMON     (0x1 << 17) // (SUPC) SRAM ON\r
+#define AT91C_SUPC_RTCON      (0x1 << 18) // (SUPC) Real Time Clock Power switch ON\r
+#define AT91C_SUPC_FLASHON    (0x1 << 19) // (SUPC) Flash Power switch On\r
+#define AT91C_SUPC_BYPASS     (0x1 << 20) // (SUPC) 32kHz oscillator bypass\r
+#define AT91C_SUPC_MKEY       (0xFF << 24) // (SUPC) Supply Controller Writing Protection Key\r
+// -------- SUPC_WUMR : (SUPC Offset: 0xc) Wake Up Mode Register -------- \r
+#define AT91C_SUPC_FWUPEN     (0x1 <<  0) // (SUPC) Force Wake Up Enable\r
+#define AT91C_SUPC_BODEN      (0x1 <<  1) // (SUPC) Brown Out Wake Up Enable\r
+#define AT91C_SUPC_RTTEN      (0x1 <<  2) // (SUPC) Real Time Timer Wake Up Enable\r
+#define AT91C_SUPC_RTCEN      (0x1 <<  3) // (SUPC) Real Time Clock Wake Up Enable\r
+#define AT91C_SUPC_FWUPDBC    (0x7 <<  8) // (SUPC) Force Wake Up debouncer\r
+#define        AT91C_SUPC_FWUPDBC_IMMEDIATE            (0x0 <<  8) // (SUPC) Immediate, No debouncing, detected active at least one Slow clock edge\r
+#define        AT91C_SUPC_FWUPDBC_3_SLCK               (0x1 <<  8) // (SUPC) An enabled Wake Up input shall be low for at least 3 SLCK periods\r
+#define        AT91C_SUPC_FWUPDBC_32_SLCK              (0x2 <<  8) // (SUPC) An enabled Wake Up input  shall be low for at least 32 SLCK periods\r
+#define        AT91C_SUPC_FWUPDBC_512_SLCK             (0x3 <<  8) // (SUPC) An enabled Wake Up input  shall be low for at least 512 SLCK periods\r
+#define        AT91C_SUPC_FWUPDBC_4096_SLCK            (0x4 <<  8) // (SUPC) An enabled Wake Up input  shall be low for at least 4096 SLCK periods\r
+#define        AT91C_SUPC_FWUPDBC_32768_SLCK           (0x5 <<  8) // (SUPC) An enabled Wake Up input  shall be low for at least 32768 SLCK periods\r
+#define AT91C_SUPC_WKUPDBC    (0x7 << 12) // (SUPC) Force Wake Up debouncer\r
+#define        AT91C_SUPC_WKUPDBC_IMMEDIATE            (0x0 << 12) // (SUPC) Immediate, No debouncing, detected active at least one Slow clock edge\r
+#define        AT91C_SUPC_WKUPDBC_3_SLCK               (0x1 << 12) // (SUPC) FWUP shall be low for at least 3 SLCK periods\r
+#define        AT91C_SUPC_WKUPDBC_32_SLCK              (0x2 << 12) // (SUPC) FWUP shall be low for at least 32 SLCK periods\r
+#define        AT91C_SUPC_WKUPDBC_512_SLCK             (0x3 << 12) // (SUPC) FWUP shall be low for at least 512 SLCK periods\r
+#define        AT91C_SUPC_WKUPDBC_4096_SLCK            (0x4 << 12) // (SUPC) FWUP shall be low for at least 4096 SLCK periods\r
+#define        AT91C_SUPC_WKUPDBC_32768_SLCK           (0x5 << 12) // (SUPC) FWUP shall be low for at least 32768 SLCK periods\r
+// -------- SUPC_WUIR : (SUPC Offset: 0x10) Wake Up Inputs Register -------- \r
+#define AT91C_SUPC_WKUPEN0    (0x1 <<  0) // (SUPC) Wake Up Input Enable 0\r
+#define AT91C_SUPC_WKUPEN1    (0x1 <<  1) // (SUPC) Wake Up Input Enable 1\r
+#define AT91C_SUPC_WKUPEN2    (0x1 <<  2) // (SUPC) Wake Up Input Enable 2\r
+#define AT91C_SUPC_WKUPEN3    (0x1 <<  3) // (SUPC) Wake Up Input Enable 3\r
+#define AT91C_SUPC_WKUPEN4    (0x1 <<  4) // (SUPC) Wake Up Input Enable 4\r
+#define AT91C_SUPC_WKUPEN5    (0x1 <<  5) // (SUPC) Wake Up Input Enable 5\r
+#define AT91C_SUPC_WKUPEN6    (0x1 <<  6) // (SUPC) Wake Up Input Enable 6\r
+#define AT91C_SUPC_WKUPEN7    (0x1 <<  7) // (SUPC) Wake Up Input Enable 7\r
+#define AT91C_SUPC_WKUPEN8    (0x1 <<  8) // (SUPC) Wake Up Input Enable 8\r
+#define AT91C_SUPC_WKUPEN9    (0x1 <<  9) // (SUPC) Wake Up Input Enable 9\r
+#define AT91C_SUPC_WKUPEN10   (0x1 << 10) // (SUPC) Wake Up Input Enable 10\r
+#define AT91C_SUPC_WKUPEN11   (0x1 << 11) // (SUPC) Wake Up Input Enable 11\r
+#define AT91C_SUPC_WKUPEN12   (0x1 << 12) // (SUPC) Wake Up Input Enable 12\r
+#define AT91C_SUPC_WKUPEN13   (0x1 << 13) // (SUPC) Wake Up Input Enable 13\r
+#define AT91C_SUPC_WKUPEN14   (0x1 << 14) // (SUPC) Wake Up Input Enable 14\r
+#define AT91C_SUPC_WKUPEN15   (0x1 << 15) // (SUPC) Wake Up Input Enable 15\r
+#define AT91C_SUPC_WKUPT0     (0x1 << 16) // (SUPC) Wake Up Input Transition 0\r
+#define AT91C_SUPC_WKUPT1     (0x1 << 17) // (SUPC) Wake Up Input Transition 1\r
+#define AT91C_SUPC_WKUPT2     (0x1 << 18) // (SUPC) Wake Up Input Transition 2\r
+#define AT91C_SUPC_WKUPT3     (0x1 << 19) // (SUPC) Wake Up Input Transition 3\r
+#define AT91C_SUPC_WKUPT4     (0x1 << 20) // (SUPC) Wake Up Input Transition 4\r
+#define AT91C_SUPC_WKUPT5     (0x1 << 21) // (SUPC) Wake Up Input Transition 5\r
+#define AT91C_SUPC_WKUPT6     (0x1 << 22) // (SUPC) Wake Up Input Transition 6\r
+#define AT91C_SUPC_WKUPT7     (0x1 << 23) // (SUPC) Wake Up Input Transition 7\r
+#define AT91C_SUPC_WKUPT8     (0x1 << 24) // (SUPC) Wake Up Input Transition 8\r
+#define AT91C_SUPC_WKUPT9     (0x1 << 25) // (SUPC) Wake Up Input Transition 9\r
+#define AT91C_SUPC_WKUPT10    (0x1 << 26) // (SUPC) Wake Up Input Transition 10\r
+#define AT91C_SUPC_WKUPT11    (0x1 << 27) // (SUPC) Wake Up Input Transition 11\r
+#define AT91C_SUPC_WKUPT12    (0x1 << 28) // (SUPC) Wake Up Input Transition 12\r
+#define AT91C_SUPC_WKUPT13    (0x1 << 29) // (SUPC) Wake Up Input Transition 13\r
+#define AT91C_SUPC_WKUPT14    (0x1 << 30) // (SUPC) Wake Up Input Transition 14\r
+#define AT91C_SUPC_WKUPT15    (0x1 << 31) // (SUPC) Wake Up Input Transition 15\r
+// -------- SUPC_SR : (SUPC Offset: 0x14) Status Register -------- \r
+#define AT91C_SUPC_FWUPS      (0x1 <<  0) // (SUPC) Force Wake Up Status\r
+#define AT91C_SUPC_WKUPS      (0x1 <<  1) // (SUPC) Wake Up Status\r
+#define AT91C_SUPC_BODWS      (0x1 <<  2) // (SUPC) BOD Detection Wake Up Status\r
+#define AT91C_SUPC_VRRSTS     (0x1 <<  3) // (SUPC) Voltage regulation Loss Reset Status\r
+#define AT91C_SUPC_BODRSTS    (0x1 <<  4) // (SUPC) BOD detection Reset Status\r
+#define AT91C_SUPC_BODS       (0x1 <<  5) // (SUPC) BOD Status\r
+#define AT91C_SUPC_BROWNOUT   (0x1 <<  6) // (SUPC) BOD Output Status\r
+#define AT91C_SUPC_OSCSEL     (0x1 <<  7) // (SUPC) 32kHz Oscillator Selection Status\r
+#define AT91C_SUPC_LCDS       (0x1 <<  8) // (SUPC) LCD Status\r
+#define AT91C_SUPC_GPBRS      (0x1 <<  9) // (SUPC) General Purpose Back-up registers Status\r
+#define AT91C_SUPC_RTS        (0x1 << 10) // (SUPC) Clock Status\r
+#define AT91C_SUPC_FLASHS     (0x1 << 11) // (SUPC) FLASH Memory Status\r
+#define AT91C_SUPC_FWUPIS     (0x1 << 12) // (SUPC) WKUP Input Status\r
+#define AT91C_SUPC_WKUPIS0    (0x1 << 16) // (SUPC) WKUP Input 0 Status\r
+#define AT91C_SUPC_WKUPIS1    (0x1 << 17) // (SUPC) WKUP Input 1 Status\r
+#define AT91C_SUPC_WKUPIS2    (0x1 << 18) // (SUPC) WKUP Input 2 Status\r
+#define AT91C_SUPC_WKUPIS3    (0x1 << 19) // (SUPC) WKUP Input 3 Status\r
+#define AT91C_SUPC_WKUPIS4    (0x1 << 20) // (SUPC) WKUP Input 4 Status\r
+#define AT91C_SUPC_WKUPIS5    (0x1 << 21) // (SUPC) WKUP Input 5 Status\r
+#define AT91C_SUPC_WKUPIS6    (0x1 << 22) // (SUPC) WKUP Input 6 Status\r
+#define AT91C_SUPC_WKUPIS7    (0x1 << 23) // (SUPC) WKUP Input 7 Status\r
+#define AT91C_SUPC_WKUPIS8    (0x1 << 24) // (SUPC) WKUP Input 8 Status\r
+#define AT91C_SUPC_WKUPIS9    (0x1 << 25) // (SUPC) WKUP Input 9 Status\r
+#define AT91C_SUPC_WKUPIS10   (0x1 << 26) // (SUPC) WKUP Input 10 Status\r
+#define AT91C_SUPC_WKUPIS11   (0x1 << 27) // (SUPC) WKUP Input 11 Status\r
+#define AT91C_SUPC_WKUPIS12   (0x1 << 28) // (SUPC) WKUP Input 12 Status\r
+#define AT91C_SUPC_WKUPIS13   (0x1 << 29) // (SUPC) WKUP Input 13 Status\r
+#define AT91C_SUPC_WKUPIS14   (0x1 << 30) // (SUPC) WKUP Input 14 Status\r
+#define AT91C_SUPC_WKUPIS15   (0x1 << 31) // (SUPC) WKUP Input 15 Status\r
+// -------- SUPC_FWUTR : (SUPC Offset: 0x18) Flash Wake Up Timer Register -------- \r
+#define AT91C_SUPC_FWUT       (0x3FF <<  0) // (SUPC) Flash Wake Up Timer\r
+\r
+// *****************************************************************************\r
+//              SOFTWARE API DEFINITION  FOR Real Time Timer Controller Interface\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_RTTC {\r
+       AT91_REG         RTTC_RTMR;     // Real-time Mode Register\r
+       AT91_REG         RTTC_RTAR;     // Real-time Alarm Register\r
+       AT91_REG         RTTC_RTVR;     // Real-time Value Register\r
+       AT91_REG         RTTC_RTSR;     // Real-time Status Register\r
+} AT91S_RTTC, *AT91PS_RTTC;\r
+#else\r
+#define RTTC_RTMR       (AT91_CAST(AT91_REG *)         0x00000000) // (RTTC_RTMR) Real-time Mode Register\r
+#define RTTC_RTAR       (AT91_CAST(AT91_REG *)         0x00000004) // (RTTC_RTAR) Real-time Alarm Register\r
+#define RTTC_RTVR       (AT91_CAST(AT91_REG *)         0x00000008) // (RTTC_RTVR) Real-time Value Register\r
+#define RTTC_RTSR       (AT91_CAST(AT91_REG *)         0x0000000C) // (RTTC_RTSR) Real-time Status Register\r
+\r
+#endif\r
+// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- \r
+#define AT91C_RTTC_RTPRES     (0xFFFF <<  0) // (RTTC) Real-time Timer Prescaler Value\r
+#define AT91C_RTTC_ALMIEN     (0x1 << 16) // (RTTC) Alarm Interrupt Enable\r
+#define AT91C_RTTC_RTTINCIEN  (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable\r
+#define AT91C_RTTC_RTTRST     (0x1 << 18) // (RTTC) Real Time Timer Restart\r
+// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- \r
+#define AT91C_RTTC_ALMV       (0x0 <<  0) // (RTTC) Alarm Value\r
+// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- \r
+#define AT91C_RTTC_CRTV       (0x0 <<  0) // (RTTC) Current Real-time Value\r
+// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- \r
+#define AT91C_RTTC_ALMS       (0x1 <<  0) // (RTTC) Real-time Alarm Status\r
+#define AT91C_RTTC_RTTINC     (0x1 <<  1) // (RTTC) Real-time Timer Increment\r
+\r
+// *****************************************************************************\r
+//              SOFTWARE API DEFINITION  FOR Watchdog Timer Controller Interface\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_WDTC {\r
+       AT91_REG         WDTC_WDCR;     // Watchdog Control Register\r
+       AT91_REG         WDTC_WDMR;     // Watchdog Mode Register\r
+       AT91_REG         WDTC_WDSR;     // Watchdog Status Register\r
+} AT91S_WDTC, *AT91PS_WDTC;\r
+#else\r
+#define WDTC_WDCR       (AT91_CAST(AT91_REG *)         0x00000000) // (WDTC_WDCR) Watchdog Control Register\r
+#define WDTC_WDMR       (AT91_CAST(AT91_REG *)         0x00000004) // (WDTC_WDMR) Watchdog Mode Register\r
+#define WDTC_WDSR       (AT91_CAST(AT91_REG *)         0x00000008) // (WDTC_WDSR) Watchdog Status Register\r
+\r
+#endif\r
+// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- \r
+#define AT91C_WDTC_WDRSTT     (0x1 <<  0) // (WDTC) Watchdog Restart\r
+#define AT91C_WDTC_KEY        (0xFF << 24) // (WDTC) Watchdog KEY Password\r
+// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- \r
+#define AT91C_WDTC_WDV        (0xFFF <<  0) // (WDTC) Watchdog Timer Restart\r
+#define AT91C_WDTC_WDFIEN     (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable\r
+#define AT91C_WDTC_WDRSTEN    (0x1 << 13) // (WDTC) Watchdog Reset Enable\r
+#define AT91C_WDTC_WDRPROC    (0x1 << 14) // (WDTC) Watchdog Timer Restart\r
+#define AT91C_WDTC_WDDIS      (0x1 << 15) // (WDTC) Watchdog Disable\r
+#define AT91C_WDTC_WDD        (0xFFF << 16) // (WDTC) Watchdog Delta Value\r
+#define AT91C_WDTC_WDDBGHLT   (0x1 << 28) // (WDTC) Watchdog Debug Halt\r
+#define AT91C_WDTC_WDIDLEHLT  (0x1 << 29) // (WDTC) Watchdog Idle Halt\r
+// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- \r
+#define AT91C_WDTC_WDUNF      (0x1 <<  0) // (WDTC) Watchdog Underflow\r
+#define AT91C_WDTC_WDERR      (0x1 <<  1) // (WDTC) Watchdog Error\r
+\r
+// *****************************************************************************\r
+//              SOFTWARE API DEFINITION  FOR Real-time Clock Alarm and Parallel Load Interface\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_RTC {\r
+       AT91_REG         RTC_CR;        // Control Register\r
+       AT91_REG         RTC_MR;        // Mode Register\r
+       AT91_REG         RTC_TIMR;      // Time Register\r
+       AT91_REG         RTC_CALR;      // Calendar Register\r
+       AT91_REG         RTC_TIMALR;    // Time Alarm Register\r
+       AT91_REG         RTC_CALALR;    // Calendar Alarm Register\r
+       AT91_REG         RTC_SR;        // Status Register\r
+       AT91_REG         RTC_SCCR;      // Status Clear Command Register\r
+       AT91_REG         RTC_IER;       // Interrupt Enable Register\r
+       AT91_REG         RTC_IDR;       // Interrupt Disable Register\r
+       AT91_REG         RTC_IMR;       // Interrupt Mask Register\r
+       AT91_REG         RTC_VER;       // Valid Entry Register\r
+} AT91S_RTC, *AT91PS_RTC;\r
+#else\r
+#define RTC_CR          (AT91_CAST(AT91_REG *)         0x00000000) // (RTC_CR) Control Register\r
+#define RTC_MR          (AT91_CAST(AT91_REG *)         0x00000004) // (RTC_MR) Mode Register\r
+#define RTC_TIMR        (AT91_CAST(AT91_REG *)         0x00000008) // (RTC_TIMR) Time Register\r
+#define RTC_CALR        (AT91_CAST(AT91_REG *)         0x0000000C) // (RTC_CALR) Calendar Register\r
+#define RTC_TIMALR      (AT91_CAST(AT91_REG *)         0x00000010) // (RTC_TIMALR) Time Alarm Register\r
+#define RTC_CALALR      (AT91_CAST(AT91_REG *)         0x00000014) // (RTC_CALALR) Calendar Alarm Register\r
+#define RTC_SR          (AT91_CAST(AT91_REG *)         0x00000018) // (RTC_SR) Status Register\r
+#define RTC_SCCR        (AT91_CAST(AT91_REG *)         0x0000001C) // (RTC_SCCR) Status Clear Command Register\r
+#define RTC_IER         (AT91_CAST(AT91_REG *)         0x00000020) // (RTC_IER) Interrupt Enable Register\r
+#define RTC_IDR         (AT91_CAST(AT91_REG *)         0x00000024) // (RTC_IDR) Interrupt Disable Register\r
+#define RTC_IMR         (AT91_CAST(AT91_REG *)         0x00000028) // (RTC_IMR) Interrupt Mask Register\r
+#define RTC_VER         (AT91_CAST(AT91_REG *)         0x0000002C) // (RTC_VER) Valid Entry Register\r
+\r
+#endif\r
+// -------- RTC_CR : (RTC Offset: 0x0) RTC Control Register -------- \r
+#define AT91C_RTC_UPDTIM      (0x1 <<  0) // (RTC) Update Request Time Register\r
+#define AT91C_RTC_UPDCAL      (0x1 <<  1) // (RTC) Update Request Calendar Register\r
+#define AT91C_RTC_TIMEVSEL    (0x3 <<  8) // (RTC) Time Event Selection\r
+#define        AT91C_RTC_TIMEVSEL_MINUTE               (0x0 <<  8) // (RTC) Minute change.\r
+#define        AT91C_RTC_TIMEVSEL_HOUR                 (0x1 <<  8) // (RTC) Hour change.\r
+#define        AT91C_RTC_TIMEVSEL_DAY24                (0x2 <<  8) // (RTC) Every day at midnight.\r
+#define        AT91C_RTC_TIMEVSEL_DAY12                (0x3 <<  8) // (RTC) Every day at noon.\r
+#define AT91C_RTC_CALEVSEL    (0x3 << 16) // (RTC) Calendar Event Selection\r
+#define        AT91C_RTC_CALEVSEL_WEEK                 (0x0 << 16) // (RTC) Week change (every Monday at time 00:00:00).\r
+#define        AT91C_RTC_CALEVSEL_MONTH                (0x1 << 16) // (RTC) Month change (every 01 of each month at time 00:00:00).\r
+#define        AT91C_RTC_CALEVSEL_YEAR                 (0x2 << 16) // (RTC) Year change (every January 1 at time 00:00:00).\r
+// -------- RTC_MR : (RTC Offset: 0x4) RTC Mode Register -------- \r
+#define AT91C_RTC_HRMOD       (0x1 <<  0) // (RTC) 12-24 hour Mode\r
+// -------- RTC_TIMR : (RTC Offset: 0x8) RTC Time Register -------- \r
+#define AT91C_RTC_SEC         (0x7F <<  0) // (RTC) Current Second\r
+#define AT91C_RTC_MIN         (0x7F <<  8) // (RTC) Current Minute\r
+#define AT91C_RTC_HOUR        (0x3F << 16) // (RTC) Current Hour\r
+#define AT91C_RTC_AMPM        (0x1 << 22) // (RTC) Ante Meridiem, Post Meridiem Indicator\r
+// -------- RTC_CALR : (RTC Offset: 0xc) RTC Calendar Register -------- \r
+#define AT91C_RTC_CENT        (0x3F <<  0) // (RTC) Current Century\r
+#define AT91C_RTC_YEAR        (0xFF <<  8) // (RTC) Current Year\r
+#define AT91C_RTC_MONTH       (0x1F << 16) // (RTC) Current Month\r
+#define AT91C_RTC_DAY         (0x7 << 21) // (RTC) Current Day\r
+#define AT91C_RTC_DATE        (0x3F << 24) // (RTC) Current Date\r
+// -------- RTC_TIMALR : (RTC Offset: 0x10) RTC Time Alarm Register -------- \r
+#define AT91C_RTC_SECEN       (0x1 <<  7) // (RTC) Second Alarm Enable\r
+#define AT91C_RTC_MINEN       (0x1 << 15) // (RTC) Minute Alarm\r
+#define AT91C_RTC_HOUREN      (0x1 << 23) // (RTC) Current Hour\r
+// -------- RTC_CALALR : (RTC Offset: 0x14) RTC Calendar Alarm Register -------- \r
+#define AT91C_RTC_MONTHEN     (0x1 << 23) // (RTC) Month Alarm Enable\r
+#define AT91C_RTC_DATEEN      (0x1 << 31) // (RTC) Date Alarm Enable\r
+// -------- RTC_SR : (RTC Offset: 0x18) RTC Status Register -------- \r
+#define AT91C_RTC_ACKUPD      (0x1 <<  0) // (RTC) Acknowledge for Update\r
+#define AT91C_RTC_ALARM       (0x1 <<  1) // (RTC) Alarm Flag\r
+#define AT91C_RTC_SECEV       (0x1 <<  2) // (RTC) Second Event\r
+#define AT91C_RTC_TIMEV       (0x1 <<  3) // (RTC) Time Event\r
+#define AT91C_RTC_CALEV       (0x1 <<  4) // (RTC) Calendar event\r
+// -------- RTC_SCCR : (RTC Offset: 0x1c) RTC Status Clear Command Register -------- \r
+// -------- RTC_IER : (RTC Offset: 0x20) RTC Interrupt Enable Register -------- \r
+// -------- RTC_IDR : (RTC Offset: 0x24) RTC Interrupt Disable Register -------- \r
+// -------- RTC_IMR : (RTC Offset: 0x28) RTC Interrupt Mask Register -------- \r
+// -------- RTC_VER : (RTC Offset: 0x2c) RTC Valid Entry Register -------- \r
+#define AT91C_RTC_NVTIM       (0x1 <<  0) // (RTC) Non valid Time\r
+#define AT91C_RTC_NVCAL       (0x1 <<  1) // (RTC) Non valid Calendar\r
+#define AT91C_RTC_NVTIMALR    (0x1 <<  2) // (RTC) Non valid time Alarm\r
+#define AT91C_RTC_NVCALALR    (0x1 <<  3) // (RTC) Nonvalid Calendar Alarm\r
+\r
+// *****************************************************************************\r
+//              SOFTWARE API DEFINITION  FOR Analog to Digital Convertor\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_ADC {\r
+       AT91_REG         ADC_CR;        // ADC Control Register\r
+       AT91_REG         ADC_MR;        // ADC Mode Register\r
+       AT91_REG         Reserved0[2];  // \r
+       AT91_REG         ADC_CHER;      // ADC Channel Enable Register\r
+       AT91_REG         ADC_CHDR;      // ADC Channel Disable Register\r
+       AT91_REG         ADC_CHSR;      // ADC Channel Status Register\r
+       AT91_REG         ADC_SR;        // ADC Status Register\r
+       AT91_REG         ADC_LCDR;      // ADC Last Converted Data Register\r
+       AT91_REG         ADC_IER;       // ADC Interrupt Enable Register\r
+       AT91_REG         ADC_IDR;       // ADC Interrupt Disable Register\r
+       AT91_REG         ADC_IMR;       // ADC Interrupt Mask Register\r
+       AT91_REG         ADC_CDR0;      // ADC Channel Data Register 0\r
+       AT91_REG         ADC_CDR1;      // ADC Channel Data Register 1\r
+       AT91_REG         ADC_CDR2;      // ADC Channel Data Register 2\r
+       AT91_REG         ADC_CDR3;      // ADC Channel Data Register 3\r
+       AT91_REG         ADC_CDR4;      // ADC Channel Data Register 4\r
+       AT91_REG         ADC_CDR5;      // ADC Channel Data Register 5\r
+       AT91_REG         ADC_CDR6;      // ADC Channel Data Register 6\r
+       AT91_REG         ADC_CDR7;      // ADC Channel Data Register 7\r
+       AT91_REG         Reserved1[5];  // \r
+       AT91_REG         ADC_ACR;       // Analog Control Register\r
+       AT91_REG         ADC_EMR;       // Extended Mode Register\r
+       AT91_REG         Reserved2[32];         // \r
+       AT91_REG         ADC_ADDRSIZE;  // ADC ADDRSIZE REGISTER \r
+       AT91_REG         ADC_IPNAME1;   // ADC IPNAME1 REGISTER \r
+       AT91_REG         ADC_IPNAME2;   // ADC IPNAME2 REGISTER \r
+       AT91_REG         ADC_FEATURES;  // ADC FEATURES REGISTER \r
+       AT91_REG         ADC_VER;       // ADC VERSION REGISTER\r
+       AT91_REG         ADC_RPR;       // Receive Pointer Register\r
+       AT91_REG         ADC_RCR;       // Receive Counter Register\r
+       AT91_REG         ADC_TPR;       // Transmit Pointer Register\r
+       AT91_REG         ADC_TCR;       // Transmit Counter Register\r
+       AT91_REG         ADC_RNPR;      // Receive Next Pointer Register\r
+       AT91_REG         ADC_RNCR;      // Receive Next Counter Register\r
+       AT91_REG         ADC_TNPR;      // Transmit Next Pointer Register\r
+       AT91_REG         ADC_TNCR;      // Transmit Next Counter Register\r
+       AT91_REG         ADC_PTCR;      // PDC Transfer Control Register\r
+       AT91_REG         ADC_PTSR;      // PDC Transfer Status Register\r
+} AT91S_ADC, *AT91PS_ADC;\r
+#else\r
+#define ADC_CR          (AT91_CAST(AT91_REG *)         0x00000000) // (ADC_CR) ADC Control Register\r
+#define ADC_MR          (AT91_CAST(AT91_REG *)         0x00000004) // (ADC_MR) ADC Mode Register\r
+#define ADC_CHER        (AT91_CAST(AT91_REG *)         0x00000010) // (ADC_CHER) ADC Channel Enable Register\r
+#define ADC_CHDR        (AT91_CAST(AT91_REG *)         0x00000014) // (ADC_CHDR) ADC Channel Disable Register\r
+#define ADC_CHSR        (AT91_CAST(AT91_REG *)         0x00000018) // (ADC_CHSR) ADC Channel Status Register\r
+#define ADC_SR          (AT91_CAST(AT91_REG *)         0x0000001C) // (ADC_SR) ADC Status Register\r
+#define ADC_LCDR        (AT91_CAST(AT91_REG *)         0x00000020) // (ADC_LCDR) ADC Last Converted Data Register\r
+#define ADC_IER         (AT91_CAST(AT91_REG *)         0x00000024) // (ADC_IER) ADC Interrupt Enable Register\r
+#define ADC_IDR         (AT91_CAST(AT91_REG *)         0x00000028) // (ADC_IDR) ADC Interrupt Disable Register\r
+#define ADC_IMR         (AT91_CAST(AT91_REG *)         0x0000002C) // (ADC_IMR) ADC Interrupt Mask Register\r
+#define ADC_CDR0        (AT91_CAST(AT91_REG *)         0x00000030) // (ADC_CDR0) ADC Channel Data Register 0\r
+#define ADC_CDR1        (AT91_CAST(AT91_REG *)         0x00000034) // (ADC_CDR1) ADC Channel Data Register 1\r
+#define ADC_CDR2        (AT91_CAST(AT91_REG *)         0x00000038) // (ADC_CDR2) ADC Channel Data Register 2\r
+#define ADC_CDR3        (AT91_CAST(AT91_REG *)         0x0000003C) // (ADC_CDR3) ADC Channel Data Register 3\r
+#define ADC_CDR4        (AT91_CAST(AT91_REG *)         0x00000040) // (ADC_CDR4) ADC Channel Data Register 4\r
+#define ADC_CDR5        (AT91_CAST(AT91_REG *)         0x00000044) // (ADC_CDR5) ADC Channel Data Register 5\r
+#define ADC_CDR6        (AT91_CAST(AT91_REG *)         0x00000048) // (ADC_CDR6) ADC Channel Data Register 6\r
+#define ADC_CDR7        (AT91_CAST(AT91_REG *)         0x0000004C) // (ADC_CDR7) ADC Channel Data Register 7\r
+#define ADC_ACR         (AT91_CAST(AT91_REG *)         0x00000064) // (ADC_ACR) Analog Control Register\r
+#define ADC_EMR         (AT91_CAST(AT91_REG *)         0x00000068) // (ADC_EMR) Extended Mode Register\r
+#define ADC_ADDRSIZE    (AT91_CAST(AT91_REG *)         0x000000EC) // (ADC_ADDRSIZE) ADC ADDRSIZE REGISTER \r
+#define ADC_IPNAME1     (AT91_CAST(AT91_REG *)         0x000000F0) // (ADC_IPNAME1) ADC IPNAME1 REGISTER \r
+#define ADC_IPNAME2     (AT91_CAST(AT91_REG *)         0x000000F4) // (ADC_IPNAME2) ADC IPNAME2 REGISTER \r
+#define ADC_FEATURES    (AT91_CAST(AT91_REG *)         0x000000F8) // (ADC_FEATURES) ADC FEATURES REGISTER \r
+#define ADC_VER         (AT91_CAST(AT91_REG *)         0x000000FC) // (ADC_VER) ADC VERSION REGISTER\r
+\r
+#endif\r
+// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- \r
+#define AT91C_ADC_SWRST       (0x1 <<  0) // (ADC) Software Reset\r
+#define AT91C_ADC_START       (0x1 <<  1) // (ADC) Start Conversion\r
+// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- \r
+#define AT91C_ADC_TRGEN       (0x1 <<  0) // (ADC) Trigger Enable\r
+#define        AT91C_ADC_TRGEN_DIS                  (0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software\r
+#define        AT91C_ADC_TRGEN_EN                   (0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled.\r
+#define AT91C_ADC_TRGSEL      (0x7 <<  1) // (ADC) Trigger Selection\r
+#define        AT91C_ADC_TRGSEL_EXT                  (0x0 <<  1) // (ADC) Selected TRGSEL = External Trigger\r
+#define        AT91C_ADC_TRGSEL_TIOA0                (0x1 <<  1) // (ADC) Selected TRGSEL = TIAO0\r
+#define        AT91C_ADC_TRGSEL_TIOA1                (0x2 <<  1) // (ADC) Selected TRGSEL = TIAO1\r
+#define        AT91C_ADC_TRGSEL_TIOA2                (0x3 <<  1) // (ADC) Selected TRGSEL = TIAO2\r
+#define        AT91C_ADC_TRGSEL_PWM0_TRIG            (0x4 <<  1) // (ADC) Selected TRGSEL = PWM trigger\r
+#define        AT91C_ADC_TRGSEL_PWM1_TRIG            (0x5 <<  1) // (ADC) Selected TRGSEL = PWM Trigger\r
+#define        AT91C_ADC_TRGSEL_RESERVED             (0x6 <<  1) // (ADC) Selected TRGSEL = Reserved\r
+#define AT91C_ADC_LOWRES      (0x1 <<  4) // (ADC) Resolution.\r
+#define        AT91C_ADC_LOWRES_10_BIT               (0x0 <<  4) // (ADC) 10-bit resolution\r
+#define        AT91C_ADC_LOWRES_8_BIT                (0x1 <<  4) // (ADC) 8-bit resolution\r
+#define AT91C_ADC_SLEEP       (0x1 <<  5) // (ADC) Sleep Mode\r
+#define        AT91C_ADC_SLEEP_NORMAL_MODE          (0x0 <<  5) // (ADC) Normal Mode\r
+#define        AT91C_ADC_SLEEP_MODE                 (0x1 <<  5) // (ADC) Sleep Mode\r
+#define AT91C_ADC_PRESCAL     (0x3F <<  8) // (ADC) Prescaler rate selection\r
+#define AT91C_ADC_STARTUP     (0x1F << 16) // (ADC) Startup Time\r
+#define AT91C_ADC_SHTIM       (0xF << 24) // (ADC) Sample & Hold Time\r
+// --------    ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- \r
+#define AT91C_ADC_CH0         (0x1 <<  0) // (ADC) Channel 0\r
+#define AT91C_ADC_CH1         (0x1 <<  1) // (ADC) Channel 1\r
+#define AT91C_ADC_CH2         (0x1 <<  2) // (ADC) Channel 2\r
+#define AT91C_ADC_CH3         (0x1 <<  3) // (ADC) Channel 3\r
+#define AT91C_ADC_CH4         (0x1 <<  4) // (ADC) Channel 4\r
+#define AT91C_ADC_CH5         (0x1 <<  5) // (ADC) Channel 5\r
+#define AT91C_ADC_CH6         (0x1 <<  6) // (ADC) Channel 6\r
+#define AT91C_ADC_CH7         (0x1 <<  7) // (ADC) Channel 7\r
+// --------    ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- \r
+// --------    ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- \r
+// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- \r
+#define AT91C_ADC_EOC0        (0x1 <<  0) // (ADC) End of Conversion\r
+#define AT91C_ADC_EOC1        (0x1 <<  1) // (ADC) End of Conversion\r
+#define AT91C_ADC_EOC2        (0x1 <<  2) // (ADC) End of Conversion\r
+#define AT91C_ADC_EOC3        (0x1 <<  3) // (ADC) End of Conversion\r
+#define AT91C_ADC_EOC4        (0x1 <<  4) // (ADC) End of Conversion\r
+#define AT91C_ADC_EOC5        (0x1 <<  5) // (ADC) End of Conversion\r
+#define AT91C_ADC_EOC6        (0x1 <<  6) // (ADC) End of Conversion\r
+#define AT91C_ADC_EOC7        (0x1 <<  7) // (ADC) End of Conversion\r
+#define AT91C_ADC_OVRE0       (0x1 <<  8) // (ADC) Overrun Error\r
+#define AT91C_ADC_OVRE1       (0x1 <<  9) // (ADC) Overrun Error\r
+#define AT91C_ADC_OVRE2       (0x1 << 10) // (ADC) Overrun Error\r
+#define AT91C_ADC_OVRE3       (0x1 << 11) // (ADC) Overrun Error\r
+#define AT91C_ADC_OVRE4       (0x1 << 12) // (ADC) Overrun Error\r
+#define AT91C_ADC_OVRE5       (0x1 << 13) // (ADC) Overrun Error\r
+#define AT91C_ADC_OVRE6       (0x1 << 14) // (ADC) Overrun Error\r
+#define AT91C_ADC_OVRE7       (0x1 << 15) // (ADC) Overrun Error\r
+#define AT91C_ADC_DRDY        (0x1 << 16) // (ADC) Data Ready\r
+#define AT91C_ADC_GOVRE       (0x1 << 17) // (ADC) General Overrun\r
+#define AT91C_ADC_ENDRX       (0x1 << 18) // (ADC) End of Receiver Transfer\r
+#define AT91C_ADC_RXBUFF      (0x1 << 19) // (ADC) RXBUFF Interrupt\r
+// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- \r
+#define AT91C_ADC_LDATA       (0x3FF <<  0) // (ADC) Last Data Converted\r
+// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- \r
+// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- \r
+// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- \r
+// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- \r
+#define AT91C_ADC_DATA        (0x3FF <<  0) // (ADC) Converted Data\r
+// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- \r
+// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- \r
+// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- \r
+// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- \r
+// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- \r
+// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- \r
+// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- \r
+// -------- ADC_ACR : (ADC Offset: 0x64) ADC Analog Controler Register -------- \r
+#define AT91C_ADC_GAIN        (0x3 <<  0) // (ADC) Input Gain\r
+#define AT91C_ADC_IBCTL       (0x3 <<  6) // (ADC) Bias Current Control\r
+#define        AT91C_ADC_IBCTL_00                   (0x0 <<  6) // (ADC) typ - 20%\r
+#define        AT91C_ADC_IBCTL_01                   (0x1 <<  6) // (ADC) typ\r
+#define        AT91C_ADC_IBCTL_10                   (0x2 <<  6) // (ADC) typ + 20%\r
+#define        AT91C_ADC_IBCTL_11                   (0x3 <<  6) // (ADC) typ + 40%\r
+#define AT91C_ADC_DIFF        (0x1 << 16) // (ADC) Differential Mode\r
+#define AT91C_ADC_OFFSET      (0x1 << 17) // (ADC) Input OFFSET\r
+// -------- ADC_EMR : (ADC Offset: 0x68) ADC Extended Mode Register -------- \r
+#define AT91C_OFFMODES        (0x1 <<  0) // (ADC) Off Mode if\r
+#define AT91C_OFF_MODE_STARTUP_TIME (0x1 << 16) // (ADC) Startup Time\r
+// -------- ADC_VER : (ADC Offset: 0xfc) ADC VER -------- \r
+#define AT91C_ADC_VER         (0xF <<  0) // (ADC) ADC VER\r
+\r
+// *****************************************************************************\r
+//              SOFTWARE API DEFINITION  FOR Timer Counter Channel Interface\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_TC {\r
+       AT91_REG         TC_CCR;        // Channel Control Register\r
+       AT91_REG         TC_CMR;        // Channel Mode Register (Capture Mode / Waveform Mode)\r
+       AT91_REG         Reserved0[2];  // \r
+       AT91_REG         TC_CV;         // Counter Value\r
+       AT91_REG         TC_RA;         // Register A\r
+       AT91_REG         TC_RB;         // Register B\r
+       AT91_REG         TC_RC;         // Register C\r
+       AT91_REG         TC_SR;         // Status Register\r
+       AT91_REG         TC_IER;        // Interrupt Enable Register\r
+       AT91_REG         TC_IDR;        // Interrupt Disable Register\r
+       AT91_REG         TC_IMR;        // Interrupt Mask Register\r
+} AT91S_TC, *AT91PS_TC;\r
+#else\r
+#define TC_CCR          (AT91_CAST(AT91_REG *)         0x00000000) // (TC_CCR) Channel Control Register\r
+#define TC_CMR          (AT91_CAST(AT91_REG *)         0x00000004) // (TC_CMR) Channel Mode Register (Capture Mode / Waveform Mode)\r
+#define TC_CV           (AT91_CAST(AT91_REG *)         0x00000010) // (TC_CV) Counter Value\r
+#define TC_RA           (AT91_CAST(AT91_REG *)         0x00000014) // (TC_RA) Register A\r
+#define TC_RB           (AT91_CAST(AT91_REG *)         0x00000018) // (TC_RB) Register B\r
+#define TC_RC           (AT91_CAST(AT91_REG *)         0x0000001C) // (TC_RC) Register C\r
+#define TC_SR           (AT91_CAST(AT91_REG *)         0x00000020) // (TC_SR) Status Register\r
+#define TC_IER          (AT91_CAST(AT91_REG *)         0x00000024) // (TC_IER) Interrupt Enable Register\r
+#define TC_IDR          (AT91_CAST(AT91_REG *)         0x00000028) // (TC_IDR) Interrupt Disable Register\r
+#define TC_IMR          (AT91_CAST(AT91_REG *)         0x0000002C) // (TC_IMR) Interrupt Mask Register\r
+\r
+#endif\r
+// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- \r
+#define AT91C_TC_CLKEN        (0x1 <<  0) // (TC) Counter Clock Enable Command\r
+#define AT91C_TC_CLKDIS       (0x1 <<  1) // (TC) Counter Clock Disable Command\r
+#define AT91C_TC_SWTRG        (0x1 <<  2) // (TC) Software Trigger Command\r
+// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- \r
+#define AT91C_TC_CLKS         (0x7 <<  0) // (TC) Clock Selection\r
+#define        AT91C_TC_CLKS_TIMER_DIV1_CLOCK     (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK\r
+#define        AT91C_TC_CLKS_TIMER_DIV2_CLOCK     (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK\r
+#define        AT91C_TC_CLKS_TIMER_DIV3_CLOCK     (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK\r
+#define        AT91C_TC_CLKS_TIMER_DIV4_CLOCK     (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK\r
+#define        AT91C_TC_CLKS_TIMER_DIV5_CLOCK     (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK\r
+#define        AT91C_TC_CLKS_XC0                  (0x5) // (TC) Clock selected: XC0\r
+#define        AT91C_TC_CLKS_XC1                  (0x6) // (TC) Clock selected: XC1\r
+#define        AT91C_TC_CLKS_XC2                  (0x7) // (TC) Clock selected: XC2\r
+#define AT91C_TC_CLKI         (0x1 <<  3) // (TC) Clock Invert\r
+#define AT91C_TC_BURST        (0x3 <<  4) // (TC) Burst Signal Selection\r
+#define        AT91C_TC_BURST_NONE                 (0x0 <<  4) // (TC) The clock is not gated by an external signal\r
+#define        AT91C_TC_BURST_XC0                  (0x1 <<  4) // (TC) XC0 is ANDed with the selected clock\r
+#define        AT91C_TC_BURST_XC1                  (0x2 <<  4) // (TC) XC1 is ANDed with the selected clock\r
+#define        AT91C_TC_BURST_XC2                  (0x3 <<  4) // (TC) XC2 is ANDed with the selected clock\r
+#define AT91C_TC_CPCSTOP      (0x1 <<  6) // (TC) Counter Clock Stopped with RC Compare\r
+#define AT91C_TC_LDBSTOP      (0x1 <<  6) // (TC) Counter Clock Stopped with RB Loading\r
+#define AT91C_TC_CPCDIS       (0x1 <<  7) // (TC) Counter Clock Disable with RC Compare\r
+#define AT91C_TC_LDBDIS       (0x1 <<  7) // (TC) Counter Clock Disabled with RB Loading\r
+#define AT91C_TC_ETRGEDG      (0x3 <<  8) // (TC) External Trigger Edge Selection\r
+#define        AT91C_TC_ETRGEDG_NONE                 (0x0 <<  8) // (TC) Edge: None\r
+#define        AT91C_TC_ETRGEDG_RISING               (0x1 <<  8) // (TC) Edge: rising edge\r
+#define        AT91C_TC_ETRGEDG_FALLING              (0x2 <<  8) // (TC) Edge: falling edge\r
+#define        AT91C_TC_ETRGEDG_BOTH                 (0x3 <<  8) // (TC) Edge: each edge\r
+#define AT91C_TC_EEVTEDG      (0x3 <<  8) // (TC) External Event Edge Selection\r
+#define        AT91C_TC_EEVTEDG_NONE                 (0x0 <<  8) // (TC) Edge: None\r
+#define        AT91C_TC_EEVTEDG_RISING               (0x1 <<  8) // (TC) Edge: rising edge\r
+#define        AT91C_TC_EEVTEDG_FALLING              (0x2 <<  8) // (TC) Edge: falling edge\r
+#define        AT91C_TC_EEVTEDG_BOTH                 (0x3 <<  8) // (TC) Edge: each edge\r
+#define AT91C_TC_EEVT         (0x3 << 10) // (TC) External Event  Selection\r
+#define        AT91C_TC_EEVT_TIOB                 (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input\r
+#define        AT91C_TC_EEVT_XC0                  (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output\r
+#define        AT91C_TC_EEVT_XC1                  (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output\r
+#define        AT91C_TC_EEVT_XC2                  (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output\r
+#define AT91C_TC_ABETRG       (0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection\r
+#define AT91C_TC_ENETRG       (0x1 << 12) // (TC) External Event Trigger enable\r
+#define AT91C_TC_WAVESEL      (0x3 << 13) // (TC) Waveform  Selection\r
+#define        AT91C_TC_WAVESEL_UP                   (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare\r
+#define        AT91C_TC_WAVESEL_UPDOWN               (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare\r
+#define        AT91C_TC_WAVESEL_UP_AUTO              (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare\r
+#define        AT91C_TC_WAVESEL_UPDOWN_AUTO          (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare\r
+#define AT91C_TC_CPCTRG       (0x1 << 14) // (TC) RC Compare Trigger Enable\r
+#define AT91C_TC_WAVE         (0x1 << 15) // (TC) \r
+#define AT91C_TC_ACPA         (0x3 << 16) // (TC) RA Compare Effect on TIOA\r
+#define        AT91C_TC_ACPA_NONE                 (0x0 << 16) // (TC) Effect: none\r
+#define        AT91C_TC_ACPA_SET                  (0x1 << 16) // (TC) Effect: set\r
+#define        AT91C_TC_ACPA_CLEAR                (0x2 << 16) // (TC) Effect: clear\r
+#define        AT91C_TC_ACPA_TOGGLE               (0x3 << 16) // (TC) Effect: toggle\r
+#define AT91C_TC_LDRA         (0x3 << 16) // (TC) RA Loading Selection\r
+#define        AT91C_TC_LDRA_NONE                 (0x0 << 16) // (TC) Edge: None\r
+#define        AT91C_TC_LDRA_RISING               (0x1 << 16) // (TC) Edge: rising edge of TIOA\r
+#define        AT91C_TC_LDRA_FALLING              (0x2 << 16) // (TC) Edge: falling edge of TIOA\r
+#define        AT91C_TC_LDRA_BOTH                 (0x3 << 16) // (TC) Edge: each edge of TIOA\r
+#define AT91C_TC_ACPC         (0x3 << 18) // (TC) RC Compare Effect on TIOA\r
+#define        AT91C_TC_ACPC_NONE                 (0x0 << 18) // (TC) Effect: none\r
+#define        AT91C_TC_ACPC_SET                  (0x1 << 18) // (TC) Effect: set\r
+#define        AT91C_TC_ACPC_CLEAR                (0x2 << 18) // (TC) Effect: clear\r
+#define        AT91C_TC_ACPC_TOGGLE               (0x3 << 18) // (TC) Effect: toggle\r
+#define AT91C_TC_LDRB         (0x3 << 18) // (TC) RB Loading Selection\r
+#define        AT91C_TC_LDRB_NONE                 (0x0 << 18) // (TC) Edge: None\r
+#define        AT91C_TC_LDRB_RISING               (0x1 << 18) // (TC) Edge: rising edge of TIOA\r
+#define        AT91C_TC_LDRB_FALLING              (0x2 << 18) // (TC) Edge: falling edge of TIOA\r
+#define        AT91C_TC_LDRB_BOTH                 (0x3 << 18) // (TC) Edge: each edge of TIOA\r
+#define AT91C_TC_AEEVT        (0x3 << 20) // (TC) External Event Effect on TIOA\r
+#define        AT91C_TC_AEEVT_NONE                 (0x0 << 20) // (TC) Effect: none\r
+#define        AT91C_TC_AEEVT_SET                  (0x1 << 20) // (TC) Effect: set\r
+#define        AT91C_TC_AEEVT_CLEAR                (0x2 << 20) // (TC) Effect: clear\r
+#define        AT91C_TC_AEEVT_TOGGLE               (0x3 << 20) // (TC) Effect: toggle\r
+#define AT91C_TC_ASWTRG       (0x3 << 22) // (TC) Software Trigger Effect on TIOA\r
+#define        AT91C_TC_ASWTRG_NONE                 (0x0 << 22) // (TC) Effect: none\r
+#define        AT91C_TC_ASWTRG_SET                  (0x1 << 22) // (TC) Effect: set\r
+#define        AT91C_TC_ASWTRG_CLEAR                (0x2 << 22) // (TC) Effect: clear\r
+#define        AT91C_TC_ASWTRG_TOGGLE               (0x3 << 22) // (TC) Effect: toggle\r
+#define AT91C_TC_BCPB         (0x3 << 24) // (TC) RB Compare Effect on TIOB\r
+#define        AT91C_TC_BCPB_NONE                 (0x0 << 24) // (TC) Effect: none\r
+#define        AT91C_TC_BCPB_SET                  (0x1 << 24) // (TC) Effect: set\r
+#define        AT91C_TC_BCPB_CLEAR                (0x2 << 24) // (TC) Effect: clear\r
+#define        AT91C_TC_BCPB_TOGGLE               (0x3 << 24) // (TC) Effect: toggle\r
+#define AT91C_TC_BCPC         (0x3 << 26) // (TC) RC Compare Effect on TIOB\r
+#define        AT91C_TC_BCPC_NONE                 (0x0 << 26) // (TC) Effect: none\r
+#define        AT91C_TC_BCPC_SET                  (0x1 << 26) // (TC) Effect: set\r
+#define        AT91C_TC_BCPC_CLEAR                (0x2 << 26) // (TC) Effect: clear\r
+#define        AT91C_TC_BCPC_TOGGLE               (0x3 << 26) // (TC) Effect: toggle\r
+#define AT91C_TC_BEEVT        (0x3 << 28) // (TC) External Event Effect on TIOB\r
+#define        AT91C_TC_BEEVT_NONE                 (0x0 << 28) // (TC) Effect: none\r
+#define        AT91C_TC_BEEVT_SET                  (0x1 << 28) // (TC) Effect: set\r
+#define        AT91C_TC_BEEVT_CLEAR                (0x2 << 28) // (TC) Effect: clear\r
+#define        AT91C_TC_BEEVT_TOGGLE               (0x3 << 28) // (TC) Effect: toggle\r
+#define AT91C_TC_BSWTRG       (0x3 << 30) // (TC) Software Trigger Effect on TIOB\r
+#define        AT91C_TC_BSWTRG_NONE                 (0x0 << 30) // (TC) Effect: none\r
+#define        AT91C_TC_BSWTRG_SET                  (0x1 << 30) // (TC) Effect: set\r
+#define        AT91C_TC_BSWTRG_CLEAR                (0x2 << 30) // (TC) Effect: clear\r
+#define        AT91C_TC_BSWTRG_TOGGLE               (0x3 << 30) // (TC) Effect: toggle\r
+// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- \r
+#define AT91C_TC_COVFS        (0x1 <<  0) // (TC) Counter Overflow\r
+#define AT91C_TC_LOVRS        (0x1 <<  1) // (TC) Load Overrun\r
+#define AT91C_TC_CPAS         (0x1 <<  2) // (TC) RA Compare\r
+#define AT91C_TC_CPBS         (0x1 <<  3) // (TC) RB Compare\r
+#define AT91C_TC_CPCS         (0x1 <<  4) // (TC) RC Compare\r
+#define AT91C_TC_LDRAS        (0x1 <<  5) // (TC) RA Loading\r
+#define AT91C_TC_LDRBS        (0x1 <<  6) // (TC) RB Loading\r
+#define AT91C_TC_ETRGS        (0x1 <<  7) // (TC) External Trigger\r
+#define AT91C_TC_CLKSTA       (0x1 << 16) // (TC) Clock Enabling\r
+#define AT91C_TC_MTIOA        (0x1 << 17) // (TC) TIOA Mirror\r
+#define AT91C_TC_MTIOB        (0x1 << 18) // (TC) TIOA Mirror\r
+// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- \r
+// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- \r
+// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- \r
+\r
+// *****************************************************************************\r
+//              SOFTWARE API DEFINITION  FOR Timer Counter Interface\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_TCB {\r
+       AT91S_TC         TCB_TC0;       // TC Channel 0\r
+       AT91_REG         Reserved0[4];  // \r
+       AT91S_TC         TCB_TC1;       // TC Channel 1\r
+       AT91_REG         Reserved1[4];  // \r
+       AT91S_TC         TCB_TC2;       // TC Channel 2\r
+       AT91_REG         Reserved2[4];  // \r
+       AT91_REG         TCB_BCR;       // TC Block Control Register\r
+       AT91_REG         TCB_BMR;       // TC Block Mode Register\r
+       AT91_REG         Reserved3[9];  // \r
+       AT91_REG         TCB_ADDRSIZE;  // TC ADDRSIZE REGISTER \r
+       AT91_REG         TCB_IPNAME1;   // TC IPNAME1 REGISTER \r
+       AT91_REG         TCB_IPNAME2;   // TC IPNAME2 REGISTER \r
+       AT91_REG         TCB_FEATURES;  // TC FEATURES REGISTER \r
+       AT91_REG         TCB_VER;       //  Version Register\r
+} AT91S_TCB, *AT91PS_TCB;\r
+#else\r
+#define TCB_BCR         (AT91_CAST(AT91_REG *)         0x000000C0) // (TCB_BCR) TC Block Control Register\r
+#define TCB_BMR         (AT91_CAST(AT91_REG *)         0x000000C4) // (TCB_BMR) TC Block Mode Register\r
+#define TC_ADDRSIZE     (AT91_CAST(AT91_REG *)         0x000000EC) // (TC_ADDRSIZE) TC ADDRSIZE REGISTER \r
+#define TC_IPNAME1      (AT91_CAST(AT91_REG *)         0x000000F0) // (TC_IPNAME1) TC IPNAME1 REGISTER \r
+#define TC_IPNAME2      (AT91_CAST(AT91_REG *)         0x000000F4) // (TC_IPNAME2) TC IPNAME2 REGISTER \r
+#define TC_FEATURES     (AT91_CAST(AT91_REG *)         0x000000F8) // (TC_FEATURES) TC FEATURES REGISTER \r
+#define TC_VER          (AT91_CAST(AT91_REG *)         0x000000FC) // (TC_VER)  Version Register\r
+\r
+#endif\r
+// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- \r
+#define AT91C_TCB_SYNC        (0x1 <<  0) // (TCB) Synchro Command\r
+// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- \r
+#define AT91C_TCB_TC0XC0S     (0x3 <<  0) // (TCB) External Clock Signal 0 Selection\r
+#define        AT91C_TCB_TC0XC0S_TCLK0                (0x0) // (TCB) TCLK0 connected to XC0\r
+#define        AT91C_TCB_TC0XC0S_NONE                 (0x1) // (TCB) None signal connected to XC0\r
+#define        AT91C_TCB_TC0XC0S_TIOA1                (0x2) // (TCB) TIOA1 connected to XC0\r
+#define        AT91C_TCB_TC0XC0S_TIOA2                (0x3) // (TCB) TIOA2 connected to XC0\r
+#define AT91C_TCB_TC1XC1S     (0x3 <<  2) // (TCB) External Clock Signal 1 Selection\r
+#define        AT91C_TCB_TC1XC1S_TCLK1                (0x0 <<  2) // (TCB) TCLK1 connected to XC1\r
+#define        AT91C_TCB_TC1XC1S_NONE                 (0x1 <<  2) // (TCB) None signal connected to XC1\r
+#define        AT91C_TCB_TC1XC1S_TIOA0                (0x2 <<  2) // (TCB) TIOA0 connected to XC1\r
+#define        AT91C_TCB_TC1XC1S_TIOA2                (0x3 <<  2) // (TCB) TIOA2 connected to XC1\r
+#define AT91C_TCB_TC2XC2S     (0x3 <<  4) // (TCB) External Clock Signal 2 Selection\r
+#define        AT91C_TCB_TC2XC2S_TCLK2                (0x0 <<  4) // (TCB) TCLK2 connected to XC2\r
+#define        AT91C_TCB_TC2XC2S_NONE                 (0x1 <<  4) // (TCB) None signal connected to XC2\r
+#define        AT91C_TCB_TC2XC2S_TIOA0                (0x2 <<  4) // (TCB) TIOA0 connected to XC2\r
+#define        AT91C_TCB_TC2XC2S_TIOA1                (0x3 <<  4) // (TCB) TIOA2 connected to XC2\r
+\r
+// *****************************************************************************\r
+//              SOFTWARE API DEFINITION  FOR Embedded Flash Controller 2.0\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_EFC {\r
+       AT91_REG         EFC_FMR;       // EFC Flash Mode Register\r
+       AT91_REG         EFC_FCR;       // EFC Flash Command Register\r
+       AT91_REG         EFC_FSR;       // EFC Flash Status Register\r
+       AT91_REG         EFC_FRR;       // EFC Flash Result Register\r
+       AT91_REG         Reserved0[1];  // \r
+       AT91_REG         EFC_FVR;       // EFC Flash Version Register\r
+} AT91S_EFC, *AT91PS_EFC;\r
+#else\r
+#define EFC_FMR         (AT91_CAST(AT91_REG *)         0x00000000) // (EFC_FMR) EFC Flash Mode Register\r
+#define EFC_FCR         (AT91_CAST(AT91_REG *)         0x00000004) // (EFC_FCR) EFC Flash Command Register\r
+#define EFC_FSR         (AT91_CAST(AT91_REG *)         0x00000008) // (EFC_FSR) EFC Flash Status Register\r
+#define EFC_FRR         (AT91_CAST(AT91_REG *)         0x0000000C) // (EFC_FRR) EFC Flash Result Register\r
+#define EFC_FVR         (AT91_CAST(AT91_REG *)         0x00000014) // (EFC_FVR) EFC Flash Version Register\r
+\r
+#endif\r
+// -------- EFC_FMR : (EFC Offset: 0x0) EFC Flash Mode Register -------- \r
+#define AT91C_EFC_FRDY        (0x1 <<  0) // (EFC) Ready Interrupt Enable\r
+#define AT91C_EFC_FWS         (0xF <<  8) // (EFC) Flash Wait State.\r
+#define        AT91C_EFC_FWS_0WS                  (0x0 <<  8) // (EFC) 0 Wait State\r
+#define        AT91C_EFC_FWS_1WS                  (0x1 <<  8) // (EFC) 1 Wait State\r
+#define        AT91C_EFC_FWS_2WS                  (0x2 <<  8) // (EFC) 2 Wait States\r
+#define        AT91C_EFC_FWS_3WS                  (0x3 <<  8) // (EFC) 3 Wait States\r
+// -------- EFC_FCR : (EFC Offset: 0x4) EFC Flash Command Register -------- \r
+#define AT91C_EFC_FCMD        (0xFF <<  0) // (EFC) Flash Command\r
+#define        AT91C_EFC_FCMD_GETD                 (0x0) // (EFC) Get Flash Descriptor\r
+#define        AT91C_EFC_FCMD_WP                   (0x1) // (EFC) Write Page\r
+#define        AT91C_EFC_FCMD_WPL                  (0x2) // (EFC) Write Page and Lock\r
+#define        AT91C_EFC_FCMD_EWP                  (0x3) // (EFC) Erase Page and Write Page\r
+#define        AT91C_EFC_FCMD_EWPL                 (0x4) // (EFC) Erase Page and Write Page then Lock\r
+#define        AT91C_EFC_FCMD_EA                   (0x5) // (EFC) Erase All\r
+#define        AT91C_EFC_FCMD_EPL                  (0x6) // (EFC) Erase Plane\r
+#define        AT91C_EFC_FCMD_EPA                  (0x7) // (EFC) Erase Pages\r
+#define        AT91C_EFC_FCMD_SLB                  (0x8) // (EFC) Set Lock Bit\r
+#define        AT91C_EFC_FCMD_CLB                  (0x9) // (EFC) Clear Lock Bit\r
+#define        AT91C_EFC_FCMD_GLB                  (0xA) // (EFC) Get Lock Bit\r
+#define        AT91C_EFC_FCMD_SFB                  (0xB) // (EFC) Set Fuse Bit\r
+#define        AT91C_EFC_FCMD_CFB                  (0xC) // (EFC) Clear Fuse Bit\r
+#define        AT91C_EFC_FCMD_GFB                  (0xD) // (EFC) Get Fuse Bit\r
+#define        AT91C_EFC_FCMD_STUI                 (0xE) // (EFC) Start Read Unique ID\r
+#define        AT91C_EFC_FCMD_SPUI                 (0xF) // (EFC) Stop Read Unique ID\r
+#define AT91C_EFC_FARG        (0xFFFF <<  8) // (EFC) Flash Command Argument\r
+#define AT91C_EFC_FKEY        (0xFF << 24) // (EFC) Flash Writing Protection Key\r
+// -------- EFC_FSR : (EFC Offset: 0x8) EFC Flash Status Register -------- \r
+#define AT91C_EFC_FRDY_S      (0x1 <<  0) // (EFC) Flash Ready Status\r
+#define AT91C_EFC_FCMDE       (0x1 <<  1) // (EFC) Flash Command Error Status\r
+#define AT91C_EFC_LOCKE       (0x1 <<  2) // (EFC) Flash Lock Error Status\r
+// -------- EFC_FRR : (EFC Offset: 0xc) EFC Flash Result Register -------- \r
+#define AT91C_EFC_FVALUE      (0x0 <<  0) // (EFC) Flash Result Value\r
+\r
+// *****************************************************************************\r
+//              SOFTWARE API DEFINITION  FOR Multimedia Card Interface\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_MCI {\r
+       AT91_REG         MCI_CR;        // MCI Control Register\r
+       AT91_REG         MCI_MR;        // MCI Mode Register\r
+       AT91_REG         MCI_DTOR;      // MCI Data Timeout Register\r
+       AT91_REG         MCI_SDCR;      // MCI SD/SDIO Card Register\r
+       AT91_REG         MCI_ARGR;      // MCI Argument Register\r
+       AT91_REG         MCI_CMDR;      // MCI Command Register\r
+       AT91_REG         MCI_BLKR;      // MCI Block Register\r
+       AT91_REG         MCI_CSTOR;     // MCI Completion Signal Timeout Register\r
+       AT91_REG         MCI_RSPR[4];   // MCI Response Register\r
+       AT91_REG         MCI_RDR;       // MCI Receive Data Register\r
+       AT91_REG         MCI_TDR;       // MCI Transmit Data Register\r
+       AT91_REG         Reserved0[2];  // \r
+       AT91_REG         MCI_SR;        // MCI Status Register\r
+       AT91_REG         MCI_IER;       // MCI Interrupt Enable Register\r
+       AT91_REG         MCI_IDR;       // MCI Interrupt Disable Register\r
+       AT91_REG         MCI_IMR;       // MCI Interrupt Mask Register\r
+       AT91_REG         MCI_DMA;       // MCI DMA Configuration Register\r
+       AT91_REG         MCI_CFG;       // MCI Configuration Register\r
+       AT91_REG         Reserved1[35];         // \r
+       AT91_REG         MCI_WPCR;      // MCI Write Protection Control Register\r
+       AT91_REG         MCI_WPSR;      // MCI Write Protection Status Register\r
+       AT91_REG         MCI_ADDRSIZE;  // MCI ADDRSIZE REGISTER \r
+       AT91_REG         MCI_IPNAME1;   // MCI IPNAME1 REGISTER \r
+       AT91_REG         MCI_IPNAME2;   // MCI IPNAME2 REGISTER \r
+       AT91_REG         MCI_FEATURES;  // MCI FEATURES REGISTER \r
+       AT91_REG         MCI_VER;       // MCI VERSION REGISTER \r
+       AT91_REG         MCI_RPR;       // Receive Pointer Register\r
+       AT91_REG         MCI_RCR;       // Receive Counter Register\r
+       AT91_REG         MCI_TPR;       // Transmit Pointer Register\r
+       AT91_REG         MCI_TCR;       // Transmit Counter Register\r
+       AT91_REG         MCI_RNPR;      // Receive Next Pointer Register\r
+       AT91_REG         MCI_RNCR;      // Receive Next Counter Register\r
+       AT91_REG         MCI_TNPR;      // Transmit Next Pointer Register\r
+       AT91_REG         MCI_TNCR;      // Transmit Next Counter Register\r
+       AT91_REG         MCI_PTCR;      // PDC Transfer Control Register\r
+       AT91_REG         MCI_PTSR;      // PDC Transfer Status Register\r
+       AT91_REG         Reserved2[54];         // \r
+       AT91_REG         MCI_FIFO;      // MCI FIFO Aperture Register\r
+} AT91S_MCI, *AT91PS_MCI;\r
+#else\r
+#define MCI_CR          (AT91_CAST(AT91_REG *)         0x00000000) // (MCI_CR) MCI Control Register\r
+#define MCI_MR          (AT91_CAST(AT91_REG *)         0x00000004) // (MCI_MR) MCI Mode Register\r
+#define MCI_DTOR        (AT91_CAST(AT91_REG *)         0x00000008) // (MCI_DTOR) MCI Data Timeout Register\r
+#define MCI_SDCR        (AT91_CAST(AT91_REG *)         0x0000000C) // (MCI_SDCR) MCI SD/SDIO Card Register\r
+#define MCI_ARGR        (AT91_CAST(AT91_REG *)         0x00000010) // (MCI_ARGR) MCI Argument Register\r
+#define MCI_CMDR        (AT91_CAST(AT91_REG *)         0x00000014) // (MCI_CMDR) MCI Command Register\r
+#define MCI_BLKR        (AT91_CAST(AT91_REG *)         0x00000018) // (MCI_BLKR) MCI Block Register\r
+#define MCI_CSTOR       (AT91_CAST(AT91_REG *)         0x0000001C) // (MCI_CSTOR) MCI Completion Signal Timeout Register\r
+#define MCI_RSPR        (AT91_CAST(AT91_REG *)         0x00000020) // (MCI_RSPR) MCI Response Register\r
+#define MCI_RDR         (AT91_CAST(AT91_REG *)         0x00000030) // (MCI_RDR) MCI Receive Data Register\r
+#define MCI_TDR         (AT91_CAST(AT91_REG *)         0x00000034) // (MCI_TDR) MCI Transmit Data Register\r
+#define MCI_SR          (AT91_CAST(AT91_REG *)         0x00000040) // (MCI_SR) MCI Status Register\r
+#define MCI_IER         (AT91_CAST(AT91_REG *)         0x00000044) // (MCI_IER) MCI Interrupt Enable Register\r
+#define MCI_IDR         (AT91_CAST(AT91_REG *)         0x00000048) // (MCI_IDR) MCI Interrupt Disable Register\r
+#define MCI_IMR         (AT91_CAST(AT91_REG *)         0x0000004C) // (MCI_IMR) MCI Interrupt Mask Register\r
+#define MCI_DMA         (AT91_CAST(AT91_REG *)         0x00000050) // (MCI_DMA) MCI DMA Configuration Register\r
+#define MCI_CFG         (AT91_CAST(AT91_REG *)         0x00000054) // (MCI_CFG) MCI Configuration Register\r
+#define MCI_WPCR        (AT91_CAST(AT91_REG *)         0x000000E4) // (MCI_WPCR) MCI Write Protection Control Register\r
+#define MCI_WPSR        (AT91_CAST(AT91_REG *)         0x000000E8) // (MCI_WPSR) MCI Write Protection Status Register\r
+#define MCI_ADDRSIZE    (AT91_CAST(AT91_REG *)         0x000000EC) // (MCI_ADDRSIZE) MCI ADDRSIZE REGISTER \r
+#define MCI_IPNAME1     (AT91_CAST(AT91_REG *)         0x000000F0) // (MCI_IPNAME1) MCI IPNAME1 REGISTER \r
+#define MCI_IPNAME2     (AT91_CAST(AT91_REG *)         0x000000F4) // (MCI_IPNAME2) MCI IPNAME2 REGISTER \r
+#define MCI_FEATURES    (AT91_CAST(AT91_REG *)         0x000000F8) // (MCI_FEATURES) MCI FEATURES REGISTER \r
+#define MCI_VER         (AT91_CAST(AT91_REG *)         0x000000FC) // (MCI_VER) MCI VERSION REGISTER \r
+#define MCI_FIFO        (AT91_CAST(AT91_REG *)         0x00000200) // (MCI_FIFO) MCI FIFO Aperture Register\r
+\r
+#endif\r
+// -------- MCI_CR : (MCI Offset: 0x0) MCI Control Register -------- \r
+#define AT91C_MCI_MCIEN       (0x1 <<  0) // (MCI) Multimedia Interface Enable\r
+#define        AT91C_MCI_MCIEN_0                    (0x0) // (MCI) No effect\r
+#define        AT91C_MCI_MCIEN_1                    (0x1) // (MCI) Enable the MultiMedia Interface if MCIDIS is 0\r
+#define AT91C_MCI_MCIDIS      (0x1 <<  1) // (MCI) Multimedia Interface Disable\r
+#define        AT91C_MCI_MCIDIS_0                    (0x0 <<  1) // (MCI) No effect\r
+#define        AT91C_MCI_MCIDIS_1                    (0x1 <<  1) // (MCI) Disable the MultiMedia Interface\r
+#define AT91C_MCI_PWSEN       (0x1 <<  2) // (MCI) Power Save Mode Enable\r
+#define        AT91C_MCI_PWSEN_0                    (0x0 <<  2) // (MCI) No effect\r
+#define        AT91C_MCI_PWSEN_1                    (0x1 <<  2) // (MCI) Enable the Power-saving mode if PWSDIS is 0.\r
+#define AT91C_MCI_PWSDIS      (0x1 <<  3) // (MCI) Power Save Mode Disable\r
+#define        AT91C_MCI_PWSDIS_0                    (0x0 <<  3) // (MCI) No effect\r
+#define        AT91C_MCI_PWSDIS_1                    (0x1 <<  3) // (MCI) Disable the Power-saving mode.\r
+#define AT91C_MCI_IOWAITEN    (0x1 <<  4) // (MCI) SDIO Read Wait Enable\r
+#define        AT91C_MCI_IOWAITEN_0                    (0x0 <<  4) // (MCI) No effect\r
+#define        AT91C_MCI_IOWAITEN_1                    (0x1 <<  4) // (MCI) Enables the SDIO Read Wait Operation.\r
+#define AT91C_MCI_IOWAITDIS   (0x1 <<  5) // (MCI) SDIO Read Wait Disable\r
+#define        AT91C_MCI_IOWAITDIS_0                    (0x0 <<  5) // (MCI) No effect\r
+#define        AT91C_MCI_IOWAITDIS_1                    (0x1 <<  5) // (MCI) Disables the SDIO Read Wait Operation.\r
+#define AT91C_MCI_SWRST       (0x1 <<  7) // (MCI) MCI Software reset\r
+#define        AT91C_MCI_SWRST_0                    (0x0 <<  7) // (MCI) No effect\r
+#define        AT91C_MCI_SWRST_1                    (0x1 <<  7) // (MCI) Resets the MCI\r
+// -------- MCI_MR : (MCI Offset: 0x4) MCI Mode Register -------- \r
+#define AT91C_MCI_CLKDIV      (0xFF <<  0) // (MCI) Clock Divider\r
+#define AT91C_MCI_PWSDIV      (0x7 <<  8) // (MCI) Power Saving Divider\r
+#define AT91C_MCI_RDPROOF     (0x1 << 11) // (MCI) Read Proof Enable\r
+#define        AT91C_MCI_RDPROOF_DISABLE              (0x0 << 11) // (MCI) Disables Read Proof\r
+#define        AT91C_MCI_RDPROOF_ENABLE               (0x1 << 11) // (MCI) Enables Read Proof\r
+#define AT91C_MCI_WRPROOF     (0x1 << 12) // (MCI) Write Proof Enable\r
+#define        AT91C_MCI_WRPROOF_DISABLE              (0x0 << 12) // (MCI) Disables Write Proof\r
+#define        AT91C_MCI_WRPROOF_ENABLE               (0x1 << 12) // (MCI) Enables Write Proof\r
+#define AT91C_MCI_PDCFBYTE    (0x1 << 13) // (MCI) PDC Force Byte Transfer\r
+#define        AT91C_MCI_PDCFBYTE_DISABLE              (0x0 << 13) // (MCI) Disables PDC Force Byte Transfer\r
+#define        AT91C_MCI_PDCFBYTE_ENABLE               (0x1 << 13) // (MCI) Enables PDC Force Byte Transfer\r
+#define AT91C_MCI_PDCPADV     (0x1 << 14) // (MCI) PDC Padding Value\r
+#define AT91C_MCI_PDCMODE     (0x1 << 15) // (MCI) PDC Oriented Mode\r
+#define        AT91C_MCI_PDCMODE_DISABLE              (0x0 << 15) // (MCI) Disables PDC Transfer\r
+#define        AT91C_MCI_PDCMODE_ENABLE               (0x1 << 15) // (MCI) Enables PDC Transfer\r
+#define AT91C_MCI_BLKLEN      (0xFFFF << 16) // (MCI) Data Block Length\r
+// -------- MCI_DTOR : (MCI Offset: 0x8) MCI Data Timeout Register -------- \r
+#define AT91C_MCI_DTOCYC      (0xF <<  0) // (MCI) Data Timeout Cycle Number\r
+#define AT91C_MCI_DTOMUL      (0x7 <<  4) // (MCI) Data Timeout Multiplier\r
+#define        AT91C_MCI_DTOMUL_1                    (0x0 <<  4) // (MCI) DTOCYC x 1\r
+#define        AT91C_MCI_DTOMUL_16                   (0x1 <<  4) // (MCI) DTOCYC x 16\r
+#define        AT91C_MCI_DTOMUL_128                  (0x2 <<  4) // (MCI) DTOCYC x 128\r
+#define        AT91C_MCI_DTOMUL_256                  (0x3 <<  4) // (MCI) DTOCYC x 256\r
+#define        AT91C_MCI_DTOMUL_1024                 (0x4 <<  4) // (MCI) DTOCYC x 1024\r
+#define        AT91C_MCI_DTOMUL_4096                 (0x5 <<  4) // (MCI) DTOCYC x 4096\r
+#define        AT91C_MCI_DTOMUL_65536                (0x6 <<  4) // (MCI) DTOCYC x 65536\r
+#define        AT91C_MCI_DTOMUL_1048576              (0x7 <<  4) // (MCI) DTOCYC x 1048576\r
+// -------- MCI_SDCR : (MCI Offset: 0xc) MCI SD Card Register -------- \r
+#define AT91C_MCI_SCDSEL      (0x3 <<  0) // (MCI) SD Card/SDIO Selector\r
+#define        AT91C_MCI_SCDSEL_SLOTA                (0x0) // (MCI) Slot A selected\r
+#define        AT91C_MCI_SCDSEL_SLOTB                (0x1) // (MCI) Slot B selected\r
+#define        AT91C_MCI_SCDSEL_SLOTC                (0x2) // (MCI) Slot C selected\r
+#define        AT91C_MCI_SCDSEL_SLOTD                (0x3) // (MCI) Slot D selected\r
+#define AT91C_MCI_SCDBUS      (0x3 <<  6) // (MCI) SDCard/SDIO Bus Width\r
+#define        AT91C_MCI_SCDBUS_1BIT                 (0x0 <<  6) // (MCI) 1-bit data bus\r
+#define        AT91C_MCI_SCDBUS_4BITS                (0x2 <<  6) // (MCI) 4-bits data bus\r
+#define        AT91C_MCI_SCDBUS_8BITS                (0x3 <<  6) // (MCI) 8-bits data bus\r
+// -------- MCI_CMDR : (MCI Offset: 0x14) MCI Command Register -------- \r
+#define AT91C_MCI_CMDNB       (0x3F <<  0) // (MCI) Command Number\r
+#define AT91C_MCI_RSPTYP      (0x3 <<  6) // (MCI) Response Type\r
+#define        AT91C_MCI_RSPTYP_NO                   (0x0 <<  6) // (MCI) No response\r
+#define        AT91C_MCI_RSPTYP_48                   (0x1 <<  6) // (MCI) 48-bit response\r
+#define        AT91C_MCI_RSPTYP_136                  (0x2 <<  6) // (MCI) 136-bit response\r
+#define        AT91C_MCI_RSPTYP_R1B                  (0x3 <<  6) // (MCI) R1b response\r
+#define AT91C_MCI_SPCMD       (0x7 <<  8) // (MCI) Special CMD\r
+#define        AT91C_MCI_SPCMD_NONE                 (0x0 <<  8) // (MCI) Not a special CMD\r
+#define        AT91C_MCI_SPCMD_INIT                 (0x1 <<  8) // (MCI) Initialization CMD\r
+#define        AT91C_MCI_SPCMD_SYNC                 (0x2 <<  8) // (MCI) Synchronized CMD\r
+#define        AT91C_MCI_SPCMD_CE_ATA               (0x3 <<  8) // (MCI) CE-ATA Completion Signal disable CMD\r
+#define        AT91C_MCI_SPCMD_IT_CMD               (0x4 <<  8) // (MCI) Interrupt command\r
+#define        AT91C_MCI_SPCMD_IT_REP               (0x5 <<  8) // (MCI) Interrupt response\r
+#define     AT91C_MCI_SPCMD_BOOTREQ              (0x6 <<  8) // (MCI) Boot Operation Request\r
+#define     AT91C_MCI_SPCMD_BOOTEND              (0x7 <<  8) // (MCI) End Boot Operation\r
+#define AT91C_MCI_OPDCMD      (0x1 << 11) // (MCI) Open Drain Command\r
+#define        AT91C_MCI_OPDCMD_PUSHPULL             (0x0 << 11) // (MCI) Push/pull command\r
+#define        AT91C_MCI_OPDCMD_OPENDRAIN            (0x1 << 11) // (MCI) Open drain command\r
+#define AT91C_MCI_MAXLAT      (0x1 << 12) // (MCI) Maximum Latency for Command to respond\r
+#define        AT91C_MCI_MAXLAT_5                    (0x0 << 12) // (MCI) 5 cycles maximum latency\r
+#define        AT91C_MCI_MAXLAT_64                   (0x1 << 12) // (MCI) 64 cycles maximum latency\r
+#define AT91C_MCI_TRCMD       (0x3 << 16) // (MCI) Transfer CMD\r
+#define        AT91C_MCI_TRCMD_NO                   (0x0 << 16) // (MCI) No transfer\r
+#define        AT91C_MCI_TRCMD_START                (0x1 << 16) // (MCI) Start transfer\r
+#define        AT91C_MCI_TRCMD_STOP                 (0x2 << 16) // (MCI) Stop transfer\r
+#define AT91C_MCI_TRDIR       (0x1 << 18) // (MCI) Transfer Direction\r
+#define        AT91C_MCI_TRDIR_WRITE                (0x0 << 18) // (MCI) Write\r
+#define        AT91C_MCI_TRDIR_READ                 (0x1 << 18) // (MCI) Read\r
+#define AT91C_MCI_TRTYP       (0x7 << 19) // (MCI) Transfer Type\r
+#define        AT91C_MCI_TRTYP_BLOCK                (0x0 << 19) // (MCI) MMC/SDCard Single Block Transfer type\r
+#define        AT91C_MCI_TRTYP_MULTIPLE             (0x1 << 19) // (MCI) MMC/SDCard Multiple Block transfer type\r
+#define        AT91C_MCI_TRTYP_STREAM               (0x2 << 19) // (MCI) MMC Stream transfer type\r
+#define        AT91C_MCI_TRTYP_SDIO_BYTE            (0x4 << 19) // (MCI) SDIO Byte transfer type\r
+#define        AT91C_MCI_TRTYP_SDIO_BLOCK           (0x5 << 19) // (MCI) SDIO Block transfer type\r
+#define AT91C_MCI_IOSPCMD     (0x3 << 24) // (MCI) SDIO Special Command\r
+#define        AT91C_MCI_IOSPCMD_NONE                 (0x0 << 24) // (MCI) NOT a special command\r
+#define        AT91C_MCI_IOSPCMD_SUSPEND              (0x1 << 24) // (MCI) SDIO Suspend Command\r
+#define        AT91C_MCI_IOSPCMD_RESUME               (0x2 << 24) // (MCI) SDIO Resume Command\r
+#define AT91C_MCI_ATACS       (0x1 << 26) // (MCI) ATA with command completion signal\r
+#define        AT91C_MCI_ATACS_NORMAL               (0x0 << 26) // (MCI) normal operation mode\r
+#define        AT91C_MCI_ATACS_COMPLETION           (0x1 << 26) // (MCI) completion signal is expected within MCI_CSTOR\r
+#define AT91C_MCI_BOOTACK     (0x1 << 27) // (MCI) Boot Operation Acknowledge\r
+#define     AT91C_MCI_BOOTACK_DISABLE           (0x0 << 27) // (MCI) Boot Operation Acknowledge Disabled\r
+#define     AT91C_MCI_BOOTACK_ENABLE            (0x1 << 27) // (MCI) Boot Operation Acknowledge Enabled\r
+// -------- MCI_BLKR : (MCI Offset: 0x18) MCI Block Register -------- \r
+#define AT91C_MCI_BCNT        (0xFFFF <<  0) // (MCI) MMC/SDIO Block Count / SDIO Byte Count\r
+// -------- MCI_CSTOR : (MCI Offset: 0x1c) MCI Completion Signal Timeout Register -------- \r
+#define AT91C_MCI_CSTOCYC     (0xF <<  0) // (MCI) Completion Signal Timeout Cycle Number\r
+#define AT91C_MCI_CSTOMUL     (0x7 <<  4) // (MCI) Completion Signal Timeout Multiplier\r
+#define        AT91C_MCI_CSTOMUL_1                    (0x0 <<  4) // (MCI) CSTOCYC x 1\r
+#define        AT91C_MCI_CSTOMUL_16                   (0x1 <<  4) // (MCI) CSTOCYC x  16\r
+#define        AT91C_MCI_CSTOMUL_128                  (0x2 <<  4) // (MCI) CSTOCYC x  128\r
+#define        AT91C_MCI_CSTOMUL_256                  (0x3 <<  4) // (MCI) CSTOCYC x  256\r
+#define        AT91C_MCI_CSTOMUL_1024                 (0x4 <<  4) // (MCI) CSTOCYC x  1024\r
+#define        AT91C_MCI_CSTOMUL_4096                 (0x5 <<  4) // (MCI) CSTOCYC x  4096\r
+#define        AT91C_MCI_CSTOMUL_65536                (0x6 <<  4) // (MCI) CSTOCYC x  65536\r
+#define        AT91C_MCI_CSTOMUL_1048576              (0x7 <<  4) // (MCI) CSTOCYC x  1048576\r
+// -------- MCI_SR : (MCI Offset: 0x40) MCI Status Register -------- \r
+#define AT91C_MCI_CMDRDY      (0x1 <<  0) // (MCI) Command Ready flag\r
+#define AT91C_MCI_RXRDY       (0x1 <<  1) // (MCI) RX Ready flag\r
+#define AT91C_MCI_TXRDY       (0x1 <<  2) // (MCI) TX Ready flag\r
+#define AT91C_MCI_BLKE        (0x1 <<  3) // (MCI) Data Block Transfer Ended flag\r
+#define AT91C_MCI_DTIP        (0x1 <<  4) // (MCI) Data Transfer in Progress flag\r
+#define AT91C_MCI_NOTBUSY     (0x1 <<  5) // (MCI) Data Line Not Busy flag\r
+#define AT91C_MCI_ENDRX       (0x1 <<  6) // (MCI) End of RX Buffer flag\r
+#define AT91C_MCI_ENDTX       (0x1 <<  7) // (MCI) End of TX Buffer flag\r
+#define AT91C_MCI_SDIOIRQA    (0x1 <<  8) // (MCI) SDIO Interrupt for Slot A\r
+#define AT91C_MCI_SDIOIRQB    (0x1 <<  9) // (MCI) SDIO Interrupt for Slot B\r
+#define AT91C_MCI_SDIOIRQC    (0x1 << 10) // (MCI) SDIO Interrupt for Slot C\r
+#define AT91C_MCI_SDIOIRQD    (0x1 << 11) // (MCI) SDIO Interrupt for Slot D\r
+#define AT91C_MCI_SDIOWAIT    (0x1 << 12) // (MCI) SDIO Read Wait operation flag\r
+#define AT91C_MCI_CSRCV       (0x1 << 13) // (MCI) CE-ATA Completion Signal flag\r
+#define AT91C_MCI_RXBUFF      (0x1 << 14) // (MCI) RX Buffer Full flag\r
+#define AT91C_MCI_TXBUFE      (0x1 << 15) // (MCI) TX Buffer Empty flag\r
+#define AT91C_MCI_RINDE       (0x1 << 16) // (MCI) Response Index Error flag\r
+#define AT91C_MCI_RDIRE       (0x1 << 17) // (MCI) Response Direction Error flag\r
+#define AT91C_MCI_RCRCE       (0x1 << 18) // (MCI) Response CRC Error flag\r
+#define AT91C_MCI_RENDE       (0x1 << 19) // (MCI) Response End Bit Error flag\r
+#define AT91C_MCI_RTOE        (0x1 << 20) // (MCI) Response Time-out Error flag\r
+#define AT91C_MCI_DCRCE       (0x1 << 21) // (MCI) data CRC Error flag\r
+#define AT91C_MCI_DTOE        (0x1 << 22) // (MCI) Data timeout Error flag\r
+#define AT91C_MCI_CSTOE       (0x1 << 23) // (MCI) Completion Signal timeout Error flag\r
+#define AT91C_MCI_BLKOVRE     (0x1 << 24) // (MCI) DMA Block Overrun Error flag\r
+#define AT91C_MCI_DMADONE     (0x1 << 25) // (MCI) DMA Transfer Done flag\r
+#define AT91C_MCI_FIFOEMPTY   (0x1 << 26) // (MCI) FIFO Empty flag\r
+#define AT91C_MCI_XFRDONE     (0x1 << 27) // (MCI) Transfer Done flag\r
+#define AT91C_MCI_OVRE        (0x1 << 30) // (MCI) Overrun flag\r
+#define AT91C_MCI_UNRE        (0x1 << 31) // (MCI) Underrun flag\r
+// -------- MCI_IER : (MCI Offset: 0x44) MCI Interrupt Enable Register -------- \r
+// -------- MCI_IDR : (MCI Offset: 0x48) MCI Interrupt Disable Register -------- \r
+// -------- MCI_IMR : (MCI Offset: 0x4c) MCI Interrupt Mask Register -------- \r
+// -------- MCI_DMA : (MCI Offset: 0x50) MCI DMA Configuration Register -------- \r
+#define AT91C_MCI_OFFSET      (0x3 <<  0) // (MCI) DMA Write Buffer Offset\r
+#define AT91C_MCI_CHKSIZE     (0x7 <<  4) // (MCI) DMA Channel Read/Write Chunk Size\r
+#define        AT91C_MCI_CHKSIZE_1                    (0x0 <<  4) // (MCI) Number of data transferred is 1\r
+#define        AT91C_MCI_CHKSIZE_4                    (0x1 <<  4) // (MCI) Number of data transferred is 4\r
+#define        AT91C_MCI_CHKSIZE_8                    (0x2 <<  4) // (MCI) Number of data transferred is 8\r
+#define        AT91C_MCI_CHKSIZE_16                   (0x3 <<  4) // (MCI) Number of data transferred is 16\r
+#define        AT91C_MCI_CHKSIZE_32                   (0x4 <<  4) // (MCI) Number of data transferred is 32\r
+#define AT91C_MCI_DMAEN       (0x1 <<  8) // (MCI) DMA Hardware Handshaking Enable\r
+#define        AT91C_MCI_DMAEN_DISABLE              (0x0 <<  8) // (MCI) DMA interface is disabled\r
+#define        AT91C_MCI_DMAEN_ENABLE               (0x1 <<  8) // (MCI) DMA interface is enabled\r
+// -------- MCI_CFG : (MCI Offset: 0x54) MCI Configuration Register -------- \r
+#define AT91C_MCI_FIFOMODE    (0x1 <<  0) // (MCI) MCI Internal FIFO Control Mode\r
+#define        AT91C_MCI_FIFOMODE_AMOUNTDATA           (0x0) // (MCI) A write transfer starts when a sufficient amount of datas is written into the FIFO\r
+#define        AT91C_MCI_FIFOMODE_ONEDATA              (0x1) // (MCI) A write transfer starts as soon as one data is written into the FIFO\r
+#define AT91C_MCI_FERRCTRL    (0x1 <<  4) // (MCI) Flow Error Flag Reset Control Mode\r
+#define        AT91C_MCI_FERRCTRL_RWCMD                (0x0 <<  4) // (MCI) When an underflow/overflow condition flag is set, a new Write/Read command is needed to reset the flag\r
+#define        AT91C_MCI_FERRCTRL_READSR               (0x1 <<  4) // (MCI) When an underflow/overflow condition flag is set, a read status resets the flag\r
+#define AT91C_MCI_HSMODE      (0x1 <<  8) // (MCI) High Speed Mode\r
+#define        AT91C_MCI_HSMODE_DISABLE              (0x0 <<  8) // (MCI) Default Bus Timing Mode\r
+#define        AT91C_MCI_HSMODE_ENABLE               (0x1 <<  8) // (MCI) High Speed Mode\r
+#define AT91C_MCI_LSYNC       (0x1 << 12) // (MCI) Synchronize on last block\r
+#define        AT91C_MCI_LSYNC_CURRENT              (0x0 << 12) // (MCI) Pending command sent at end of current data block\r
+#define        AT91C_MCI_LSYNC_INFINITE             (0x1 << 12) // (MCI) Pending command sent at end of block transfer when transfer length is not infinite\r
+// -------- MCI_WPCR : (MCI Offset: 0xe4) Write Protection Control Register -------- \r
+#define AT91C_MCI_WP_EN       (0x1 <<  0) // (MCI) Write Protection Enable\r
+#define        AT91C_MCI_WP_EN_DISABLE              (0x0) // (MCI) Write Operation is disabled (if WP_KEY corresponds)\r
+#define        AT91C_MCI_WP_EN_ENABLE               (0x1) // (MCI) Write Operation is enabled (if WP_KEY corresponds)\r
+#define AT91C_MCI_WP_KEY      (0xFFFFFF <<  8) // (MCI) Write Protection Key\r
+// -------- MCI_WPSR : (MCI Offset: 0xe8) Write Protection Status Register -------- \r
+#define AT91C_MCI_WP_VS       (0xF <<  0) // (MCI) Write Protection Violation Status\r
+#define        AT91C_MCI_WP_VS_NO_VIOLATION         (0x0) // (MCI) No Write Protection Violation detected since last read\r
+#define        AT91C_MCI_WP_VS_ON_WRITE             (0x1) // (MCI) Write Protection Violation detected since last read\r
+#define        AT91C_MCI_WP_VS_ON_RESET             (0x2) // (MCI) Software Reset Violation detected since last read\r
+#define        AT91C_MCI_WP_VS_ON_BOTH              (0x3) // (MCI) Write Protection and Software Reset Violation detected since last read\r
+#define AT91C_MCI_WP_VSRC     (0xF <<  8) // (MCI) Write Protection Violation Source\r
+#define        AT91C_MCI_WP_VSRC_NO_VIOLATION         (0x0 <<  8) // (MCI) No Write Protection Violation detected since last read\r
+#define        AT91C_MCI_WP_VSRC_MCI_MR               (0x1 <<  8) // (MCI) Write Protection Violation detected on MCI_MR since last read\r
+#define        AT91C_MCI_WP_VSRC_MCI_DTOR             (0x2 <<  8) // (MCI) Write Protection Violation detected on MCI_DTOR since last read\r
+#define        AT91C_MCI_WP_VSRC_MCI_SDCR             (0x3 <<  8) // (MCI) Write Protection Violation detected on MCI_SDCR since last read\r
+#define        AT91C_MCI_WP_VSRC_MCI_CSTOR            (0x4 <<  8) // (MCI) Write Protection Violation detected on MCI_CSTOR since last read\r
+#define        AT91C_MCI_WP_VSRC_MCI_DMA              (0x5 <<  8) // (MCI) Write Protection Violation detected on MCI_DMA since last read\r
+#define        AT91C_MCI_WP_VSRC_MCI_CFG              (0x6 <<  8) // (MCI) Write Protection Violation detected on MCI_CFG since last read\r
+#define        AT91C_MCI_WP_VSRC_MCI_DEL              (0x7 <<  8) // (MCI) Write Protection Violation detected on MCI_DEL since last read\r
+// -------- MCI_VER : (MCI Offset: 0xfc)  VERSION  Register -------- \r
+#define AT91C_MCI_VER         (0xF <<  0) // (MCI)  VERSION  Register\r
+\r
+// *****************************************************************************\r
+//              SOFTWARE API DEFINITION  FOR Two-wire Interface\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_TWI {\r
+       AT91_REG         TWI_CR;        // Control Register\r
+       AT91_REG         TWI_MMR;       // Master Mode Register\r
+       AT91_REG         TWI_SMR;       // Slave Mode Register\r
+       AT91_REG         TWI_IADR;      // Internal Address Register\r
+       AT91_REG         TWI_CWGR;      // Clock Waveform Generator Register\r
+       AT91_REG         Reserved0[3];  // \r
+       AT91_REG         TWI_SR;        // Status Register\r
+       AT91_REG         TWI_IER;       // Interrupt Enable Register\r
+       AT91_REG         TWI_IDR;       // Interrupt Disable Register\r
+       AT91_REG         TWI_IMR;       // Interrupt Mask Register\r
+       AT91_REG         TWI_RHR;       // Receive Holding Register\r
+       AT91_REG         TWI_THR;       // Transmit Holding Register\r
+       AT91_REG         Reserved1[45];         // \r
+       AT91_REG         TWI_ADDRSIZE;  // TWI ADDRSIZE REGISTER \r
+       AT91_REG         TWI_IPNAME1;   // TWI IPNAME1 REGISTER \r
+       AT91_REG         TWI_IPNAME2;   // TWI IPNAME2 REGISTER \r
+       AT91_REG         TWI_FEATURES;  // TWI FEATURES REGISTER \r
+       AT91_REG         TWI_VER;       // Version Register\r
+       AT91_REG         TWI_RPR;       // Receive Pointer Register\r
+       AT91_REG         TWI_RCR;       // Receive Counter Register\r
+       AT91_REG         TWI_TPR;       // Transmit Pointer Register\r
+       AT91_REG         TWI_TCR;       // Transmit Counter Register\r
+       AT91_REG         TWI_RNPR;      // Receive Next Pointer Register\r
+       AT91_REG         TWI_RNCR;      // Receive Next Counter Register\r
+       AT91_REG         TWI_TNPR;      // Transmit Next Pointer Register\r
+       AT91_REG         TWI_TNCR;      // Transmit Next Counter Register\r
+       AT91_REG         TWI_PTCR;      // PDC Transfer Control Register\r
+       AT91_REG         TWI_PTSR;      // PDC Transfer Status Register\r
+} AT91S_TWI, *AT91PS_TWI;\r
+#else\r
+#define TWI_CR          (AT91_CAST(AT91_REG *)         0x00000000) // (TWI_CR) Control Register\r
+#define TWI_MMR         (AT91_CAST(AT91_REG *)         0x00000004) // (TWI_MMR) Master Mode Register\r
+#define TWI_SMR         (AT91_CAST(AT91_REG *)         0x00000008) // (TWI_SMR) Slave Mode Register\r
+#define TWI_IADR        (AT91_CAST(AT91_REG *)         0x0000000C) // (TWI_IADR) Internal Address Register\r
+#define TWI_CWGR        (AT91_CAST(AT91_REG *)         0x00000010) // (TWI_CWGR) Clock Waveform Generator Register\r
+#define TWI_SR          (AT91_CAST(AT91_REG *)         0x00000020) // (TWI_SR) Status Register\r
+#define TWI_IER         (AT91_CAST(AT91_REG *)         0x00000024) // (TWI_IER) Interrupt Enable Register\r
+#define TWI_IDR         (AT91_CAST(AT91_REG *)         0x00000028) // (TWI_IDR) Interrupt Disable Register\r
+#define TWI_IMR         (AT91_CAST(AT91_REG *)         0x0000002C) // (TWI_IMR) Interrupt Mask Register\r
+#define TWI_RHR         (AT91_CAST(AT91_REG *)         0x00000030) // (TWI_RHR) Receive Holding Register\r
+#define TWI_THR         (AT91_CAST(AT91_REG *)         0x00000034) // (TWI_THR) Transmit Holding Register\r
+#define TWI_ADDRSIZE    (AT91_CAST(AT91_REG *)         0x000000EC) // (TWI_ADDRSIZE) TWI ADDRSIZE REGISTER \r
+#define TWI_IPNAME1     (AT91_CAST(AT91_REG *)         0x000000F0) // (TWI_IPNAME1) TWI IPNAME1 REGISTER \r
+#define TWI_IPNAME2     (AT91_CAST(AT91_REG *)         0x000000F4) // (TWI_IPNAME2) TWI IPNAME2 REGISTER \r
+#define TWI_FEATURES    (AT91_CAST(AT91_REG *)         0x000000F8) // (TWI_FEATURES) TWI FEATURES REGISTER \r
+#define TWI_VER         (AT91_CAST(AT91_REG *)         0x000000FC) // (TWI_VER) Version Register\r
+\r
+#endif\r
+// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- \r
+#define AT91C_TWI_START       (0x1 <<  0) // (TWI) Send a START Condition\r
+#define AT91C_TWI_STOP        (0x1 <<  1) // (TWI) Send a STOP Condition\r
+#define AT91C_TWI_MSEN        (0x1 <<  2) // (TWI) TWI Master Transfer Enabled\r
+#define AT91C_TWI_MSDIS       (0x1 <<  3) // (TWI) TWI Master Transfer Disabled\r
+#define AT91C_TWI_SVEN        (0x1 <<  4) // (TWI) TWI Slave mode Enabled\r
+#define AT91C_TWI_SVDIS       (0x1 <<  5) // (TWI) TWI Slave mode Disabled\r
+#define AT91C_TWI_SWRST       (0x1 <<  7) // (TWI) Software Reset\r
+// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- \r
+#define AT91C_TWI_IADRSZ      (0x3 <<  8) // (TWI) Internal Device Address Size\r
+#define        AT91C_TWI_IADRSZ_NO                   (0x0 <<  8) // (TWI) No internal device address\r
+#define        AT91C_TWI_IADRSZ_1_BYTE               (0x1 <<  8) // (TWI) One-byte internal device address\r
+#define        AT91C_TWI_IADRSZ_2_BYTE               (0x2 <<  8) // (TWI) Two-byte internal device address\r
+#define        AT91C_TWI_IADRSZ_3_BYTE               (0x3 <<  8) // (TWI) Three-byte internal device address\r
+#define AT91C_TWI_MREAD       (0x1 << 12) // (TWI) Master Read Direction\r
+#define AT91C_TWI_DADR        (0x7F << 16) // (TWI) Device Address\r
+// -------- TWI_SMR : (TWI Offset: 0x8) TWI Slave Mode Register -------- \r
+#define AT91C_TWI_SADR        (0x7F << 16) // (TWI) Slave Address\r
+// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- \r
+#define AT91C_TWI_CLDIV       (0xFF <<  0) // (TWI) Clock Low Divider\r
+#define AT91C_TWI_CHDIV       (0xFF <<  8) // (TWI) Clock High Divider\r
+#define AT91C_TWI_CKDIV       (0x7 << 16) // (TWI) Clock Divider\r
+// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- \r
+#define AT91C_TWI_TXCOMP_SLAVE (0x1 <<  0) // (TWI) Transmission Completed\r
+#define AT91C_TWI_TXCOMP_MASTER (0x1 <<  0) // (TWI) Transmission Completed\r
+#define AT91C_TWI_RXRDY       (0x1 <<  1) // (TWI) Receive holding register ReaDY\r
+#define AT91C_TWI_TXRDY_MASTER (0x1 <<  2) // (TWI) Transmit holding register ReaDY\r
+#define AT91C_TWI_TXRDY_SLAVE (0x1 <<  2) // (TWI) Transmit holding register ReaDY\r
+#define AT91C_TWI_SVREAD      (0x1 <<  3) // (TWI) Slave READ (used only in Slave mode)\r
+#define AT91C_TWI_SVACC       (0x1 <<  4) // (TWI) Slave ACCess (used only in Slave mode)\r
+#define AT91C_TWI_GACC        (0x1 <<  5) // (TWI) General Call ACcess (used only in Slave mode)\r
+#define AT91C_TWI_OVRE        (0x1 <<  6) // (TWI) Overrun Error (used only in Master and Multi-master mode)\r
+#define AT91C_TWI_NACK_SLAVE  (0x1 <<  8) // (TWI) Not Acknowledged\r
+#define AT91C_TWI_NACK_MASTER (0x1 <<  8) // (TWI) Not Acknowledged\r
+#define AT91C_TWI_ARBLST_MULTI_MASTER (0x1 <<  9) // (TWI) Arbitration Lost (used only in Multimaster mode)\r
+#define AT91C_TWI_SCLWS       (0x1 << 10) // (TWI) Clock Wait State (used only in Slave mode)\r
+#define AT91C_TWI_EOSACC      (0x1 << 11) // (TWI) End Of Slave ACCess (used only in Slave mode)\r
+#define AT91C_TWI_ENDRX       (0x1 << 12) // (TWI) End of Receiver Transfer\r
+#define AT91C_TWI_ENDTX       (0x1 << 13) // (TWI) End of Receiver Transfer\r
+#define AT91C_TWI_RXBUFF      (0x1 << 14) // (TWI) RXBUFF Interrupt\r
+#define AT91C_TWI_TXBUFE      (0x1 << 15) // (TWI) TXBUFE Interrupt\r
+// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- \r
+// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- \r
+// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- \r
+\r
+// *****************************************************************************\r
+//              SOFTWARE API DEFINITION  FOR Usart\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_USART {\r
+       AT91_REG         US_CR;         // Control Register\r
+       AT91_REG         US_MR;         // Mode Register\r
+       AT91_REG         US_IER;        // Interrupt Enable Register\r
+       AT91_REG         US_IDR;        // Interrupt Disable Register\r
+       AT91_REG         US_IMR;        // Interrupt Mask Register\r
+       AT91_REG         US_CSR;        // Channel Status Register\r
+       AT91_REG         US_RHR;        // Receiver Holding Register\r
+       AT91_REG         US_THR;        // Transmitter Holding Register\r
+       AT91_REG         US_BRGR;       // Baud Rate Generator Register\r
+       AT91_REG         US_RTOR;       // Receiver Time-out Register\r
+       AT91_REG         US_TTGR;       // Transmitter Time-guard Register\r
+       AT91_REG         Reserved0[5];  // \r
+       AT91_REG         US_FIDI;       // FI_DI_Ratio Register\r
+       AT91_REG         US_NER;        // Nb Errors Register\r
+       AT91_REG         Reserved1[1];  // \r
+       AT91_REG         US_IF;         // IRDA_FILTER Register\r
+       AT91_REG         US_MAN;        // Manchester Encoder Decoder Register\r
+       AT91_REG         Reserved2[38];         // \r
+       AT91_REG         US_ADDRSIZE;   // US ADDRSIZE REGISTER \r
+       AT91_REG         US_IPNAME1;    // US IPNAME1 REGISTER \r
+       AT91_REG         US_IPNAME2;    // US IPNAME2 REGISTER \r
+       AT91_REG         US_FEATURES;   // US FEATURES REGISTER \r
+       AT91_REG         US_VER;        // VERSION Register\r
+       AT91_REG         US_RPR;        // Receive Pointer Register\r
+       AT91_REG         US_RCR;        // Receive Counter Register\r
+       AT91_REG         US_TPR;        // Transmit Pointer Register\r
+       AT91_REG         US_TCR;        // Transmit Counter Register\r
+       AT91_REG         US_RNPR;       // Receive Next Pointer Register\r
+       AT91_REG         US_RNCR;       // Receive Next Counter Register\r
+       AT91_REG         US_TNPR;       // Transmit Next Pointer Register\r
+       AT91_REG         US_TNCR;       // Transmit Next Counter Register\r
+       AT91_REG         US_PTCR;       // PDC Transfer Control Register\r
+       AT91_REG         US_PTSR;       // PDC Transfer Status Register\r
+} AT91S_USART, *AT91PS_USART;\r
+#else\r
+#define US_CR           (AT91_CAST(AT91_REG *)         0x00000000) // (US_CR) Control Register\r
+#define US_MR           (AT91_CAST(AT91_REG *)         0x00000004) // (US_MR) Mode Register\r
+#define US_IER          (AT91_CAST(AT91_REG *)         0x00000008) // (US_IER) Interrupt Enable Register\r
+#define US_IDR          (AT91_CAST(AT91_REG *)         0x0000000C) // (US_IDR) Interrupt Disable Register\r
+#define US_IMR          (AT91_CAST(AT91_REG *)         0x00000010) // (US_IMR) Interrupt Mask Register\r
+#define US_CSR          (AT91_CAST(AT91_REG *)         0x00000014) // (US_CSR) Channel Status Register\r
+#define US_RHR          (AT91_CAST(AT91_REG *)         0x00000018) // (US_RHR) Receiver Holding Register\r
+#define US_THR          (AT91_CAST(AT91_REG *)         0x0000001C) // (US_THR) Transmitter Holding Register\r
+#define US_BRGR         (AT91_CAST(AT91_REG *)         0x00000020) // (US_BRGR) Baud Rate Generator Register\r
+#define US_RTOR         (AT91_CAST(AT91_REG *)         0x00000024) // (US_RTOR) Receiver Time-out Register\r
+#define US_TTGR         (AT91_CAST(AT91_REG *)         0x00000028) // (US_TTGR) Transmitter Time-guard Register\r
+#define US_FIDI         (AT91_CAST(AT91_REG *)         0x00000040) // (US_FIDI) FI_DI_Ratio Register\r
+#define US_NER          (AT91_CAST(AT91_REG *)         0x00000044) // (US_NER) Nb Errors Register\r
+#define US_IF           (AT91_CAST(AT91_REG *)         0x0000004C) // (US_IF) IRDA_FILTER Register\r
+#define US_MAN          (AT91_CAST(AT91_REG *)         0x00000050) // (US_MAN) Manchester Encoder Decoder Register\r
+#define US_ADDRSIZE     (AT91_CAST(AT91_REG *)         0x000000EC) // (US_ADDRSIZE) US ADDRSIZE REGISTER \r
+#define US_IPNAME1      (AT91_CAST(AT91_REG *)         0x000000F0) // (US_IPNAME1) US IPNAME1 REGISTER \r
+#define US_IPNAME2      (AT91_CAST(AT91_REG *)         0x000000F4) // (US_IPNAME2) US IPNAME2 REGISTER \r
+#define US_FEATURES     (AT91_CAST(AT91_REG *)         0x000000F8) // (US_FEATURES) US FEATURES REGISTER \r
+#define US_VER          (AT91_CAST(AT91_REG *)         0x000000FC) // (US_VER) VERSION Register\r
+\r
+#endif\r
+// -------- US_CR : (USART Offset: 0x0)  Control Register -------- \r
+#define AT91C_US_STTBRK       (0x1 <<  9) // (USART) Start Break\r
+#define AT91C_US_STPBRK       (0x1 << 10) // (USART) Stop Break\r
+#define AT91C_US_STTTO        (0x1 << 11) // (USART) Start Time-out\r
+#define AT91C_US_SENDA        (0x1 << 12) // (USART) Send Address\r
+#define AT91C_US_RSTIT        (0x1 << 13) // (USART) Reset Iterations\r
+#define AT91C_US_RSTNACK      (0x1 << 14) // (USART) Reset Non Acknowledge\r
+#define AT91C_US_RETTO        (0x1 << 15) // (USART) Rearm Time-out\r
+#define AT91C_US_DTREN        (0x1 << 16) // (USART) Data Terminal ready Enable\r
+#define AT91C_US_DTRDIS       (0x1 << 17) // (USART) Data Terminal ready Disable\r
+#define AT91C_US_RTSEN        (0x1 << 18) // (USART) Request to Send enable\r
+#define AT91C_US_RTSDIS       (0x1 << 19) // (USART) Request to Send Disable\r
+// -------- US_MR : (USART Offset: 0x4)  Mode Register -------- \r
+#define AT91C_US_USMODE       (0xF <<  0) // (USART) Usart mode\r
+#define        AT91C_US_USMODE_NORMAL               (0x0) // (USART) Normal\r
+#define        AT91C_US_USMODE_RS485                (0x1) // (USART) RS485\r
+#define        AT91C_US_USMODE_HWHSH                (0x2) // (USART) Hardware Handshaking\r
+#define        AT91C_US_USMODE_MODEM                (0x3) // (USART) Modem\r
+#define        AT91C_US_USMODE_ISO7816_0            (0x4) // (USART) ISO7816 protocol: T = 0\r
+#define        AT91C_US_USMODE_ISO7816_1            (0x6) // (USART) ISO7816 protocol: T = 1\r
+#define        AT91C_US_USMODE_IRDA                 (0x8) // (USART) IrDA\r
+#define        AT91C_US_USMODE_SWHSH                (0xC) // (USART) Software Handshaking\r
+#define AT91C_US_CLKS         (0x3 <<  4) // (USART) Clock Selection (Baud Rate generator Input Clock\r
+#define        AT91C_US_CLKS_CLOCK                (0x0 <<  4) // (USART) Clock\r
+#define        AT91C_US_CLKS_FDIV1                (0x1 <<  4) // (USART) fdiv1\r
+#define        AT91C_US_CLKS_SLOW                 (0x2 <<  4) // (USART) slow_clock (ARM)\r
+#define        AT91C_US_CLKS_EXT                  (0x3 <<  4) // (USART) External (SCK)\r
+#define AT91C_US_CHRL         (0x3 <<  6) // (USART) Clock Selection (Baud Rate generator Input Clock\r
+#define        AT91C_US_CHRL_5_BITS               (0x0 <<  6) // (USART) Character Length: 5 bits\r
+#define        AT91C_US_CHRL_6_BITS               (0x1 <<  6) // (USART) Character Length: 6 bits\r
+#define        AT91C_US_CHRL_7_BITS               (0x2 <<  6) // (USART) Character Length: 7 bits\r
+#define        AT91C_US_CHRL_8_BITS               (0x3 <<  6) // (USART) Character Length: 8 bits\r
+#define AT91C_US_SYNC         (0x1 <<  8) // (USART) Synchronous Mode Select\r
+#define AT91C_US_NBSTOP       (0x3 << 12) // (USART) Number of Stop bits\r
+#define        AT91C_US_NBSTOP_1_BIT                (0x0 << 12) // (USART) 1 stop bit\r
+#define        AT91C_US_NBSTOP_15_BIT               (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits\r
+#define        AT91C_US_NBSTOP_2_BIT                (0x2 << 12) // (USART) 2 stop bits\r
+#define AT91C_US_MSBF         (0x1 << 16) // (USART) Bit Order\r
+#define AT91C_US_MODE9        (0x1 << 17) // (USART) 9-bit Character length\r
+#define AT91C_US_CKLO         (0x1 << 18) // (USART) Clock Output Select\r
+#define AT91C_US_OVER         (0x1 << 19) // (USART) Over Sampling Mode\r
+#define AT91C_US_INACK        (0x1 << 20) // (USART) Inhibit Non Acknowledge\r
+#define AT91C_US_DSNACK       (0x1 << 21) // (USART) Disable Successive NACK\r
+#define AT91C_US_VAR_SYNC     (0x1 << 22) // (USART) Variable synchronization of command/data sync Start Frame Delimiter\r
+#define AT91C_US_MAX_ITER     (0x1 << 24) // (USART) Number of Repetitions\r
+#define AT91C_US_FILTER       (0x1 << 28) // (USART) Receive Line Filter\r
+#define AT91C_US_MANMODE      (0x1 << 29) // (USART) Manchester Encoder/Decoder Enable\r
+#define AT91C_US_MODSYNC      (0x1 << 30) // (USART) Manchester Synchronization mode\r
+#define AT91C_US_ONEBIT       (0x1 << 31) // (USART) Start Frame Delimiter selector\r
+// -------- US_IER : (USART Offset: 0x8)  Interrupt Enable Register -------- \r
+#define AT91C_US_RXBRK        (0x1 <<  2) // (USART) Break Received/End of Break\r
+#define AT91C_US_TIMEOUT      (0x1 <<  8) // (USART) Receiver Time-out\r
+#define AT91C_US_ITERATION    (0x1 << 10) // (USART) Max number of Repetitions Reached\r
+#define AT91C_US_NACK         (0x1 << 13) // (USART) Non Acknowledge\r
+#define AT91C_US_RIIC         (0x1 << 16) // (USART) Ring INdicator Input Change Flag\r
+#define AT91C_US_DSRIC        (0x1 << 17) // (USART) Data Set Ready Input Change Flag\r
+#define AT91C_US_DCDIC        (0x1 << 18) // (USART) Data Carrier Flag\r
+#define AT91C_US_CTSIC        (0x1 << 19) // (USART) Clear To Send Input Change Flag\r
+#define AT91C_US_MANE         (0x1 << 20) // (USART) Manchester Error Interrupt\r
+// -------- US_IDR : (USART Offset: 0xc)  Interrupt Disable Register -------- \r
+// -------- US_IMR : (USART Offset: 0x10)  Interrupt Mask Register -------- \r
+// -------- US_CSR : (USART Offset: 0x14)  Channel Status Register -------- \r
+#define AT91C_US_RI           (0x1 << 20) // (USART) Image of RI Input\r
+#define AT91C_US_DSR          (0x1 << 21) // (USART) Image of DSR Input\r
+#define AT91C_US_DCD          (0x1 << 22) // (USART) Image of DCD Input\r
+#define AT91C_US_CTS          (0x1 << 23) // (USART) Image of CTS Input\r
+#define AT91C_US_MANERR       (0x1 << 24) // (USART) Manchester Error\r
+// -------- US_MAN : (USART Offset: 0x50) Manchester Encoder Decoder Register -------- \r
+#define AT91C_US_TX_PL        (0xF <<  0) // (USART) Transmitter Preamble Length\r
+#define AT91C_US_TX_PP        (0x3 <<  8) // (USART) Transmitter Preamble Pattern\r
+#define        AT91C_US_TX_PP_ALL_ONE              (0x0 <<  8) // (USART) ALL_ONE\r
+#define        AT91C_US_TX_PP_ALL_ZERO             (0x1 <<  8) // (USART) ALL_ZERO\r
+#define        AT91C_US_TX_PP_ZERO_ONE             (0x2 <<  8) // (USART) ZERO_ONE\r
+#define        AT91C_US_TX_PP_ONE_ZERO             (0x3 <<  8) // (USART) ONE_ZERO\r
+#define AT91C_US_TX_MPOL      (0x1 << 12) // (USART) Transmitter Manchester Polarity\r
+#define AT91C_US_RX_PL        (0xF << 16) // (USART) Receiver Preamble Length\r
+#define AT91C_US_RX_PP        (0x3 << 24) // (USART) Receiver Preamble Pattern detected\r
+#define        AT91C_US_RX_PP_ALL_ONE              (0x0 << 24) // (USART) ALL_ONE\r
+#define        AT91C_US_RX_PP_ALL_ZERO             (0x1 << 24) // (USART) ALL_ZERO\r
+#define        AT91C_US_RX_PP_ZERO_ONE             (0x2 << 24) // (USART) ZERO_ONE\r
+#define        AT91C_US_RX_PP_ONE_ZERO             (0x3 << 24) // (USART) ONE_ZERO\r
+#define AT91C_US_RX_MPOL      (0x1 << 28) // (USART) Receiver Manchester Polarity\r
+#define AT91C_US_DRIFT        (0x1 << 30) // (USART) Drift compensation\r
+\r
+// *****************************************************************************\r
+//              SOFTWARE API DEFINITION  FOR Synchronous Serial Controller Interface\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_SSC {\r
+       AT91_REG         SSC_CR;        // Control Register\r
+       AT91_REG         SSC_CMR;       // Clock Mode Register\r
+       AT91_REG         Reserved0[2];  // \r
+       AT91_REG         SSC_RCMR;      // Receive Clock ModeRegister\r
+       AT91_REG         SSC_RFMR;      // Receive Frame Mode Register\r
+       AT91_REG         SSC_TCMR;      // Transmit Clock Mode Register\r
+       AT91_REG         SSC_TFMR;      // Transmit Frame Mode Register\r
+       AT91_REG         SSC_RHR;       // Receive Holding Register\r
+       AT91_REG         SSC_THR;       // Transmit Holding Register\r
+       AT91_REG         Reserved1[2];  // \r
+       AT91_REG         SSC_RSHR;      // Receive Sync Holding Register\r
+       AT91_REG         SSC_TSHR;      // Transmit Sync Holding Register\r
+       AT91_REG         Reserved2[2];  // \r
+       AT91_REG         SSC_SR;        // Status Register\r
+       AT91_REG         SSC_IER;       // Interrupt Enable Register\r
+       AT91_REG         SSC_IDR;       // Interrupt Disable Register\r
+       AT91_REG         SSC_IMR;       // Interrupt Mask Register\r
+       AT91_REG         Reserved3[39];         // \r
+       AT91_REG         SSC_ADDRSIZE;  // SSC ADDRSIZE REGISTER \r
+       AT91_REG         SSC_IPNAME1;   // SSC IPNAME1 REGISTER \r
+       AT91_REG         SSC_IPNAME2;   // SSC IPNAME2 REGISTER \r
+       AT91_REG         SSC_FEATURES;  // SSC FEATURES REGISTER \r
+       AT91_REG         SSC_VER;       // Version Register\r
+       AT91_REG         SSC_RPR;       // Receive Pointer Register\r
+       AT91_REG         SSC_RCR;       // Receive Counter Register\r
+       AT91_REG         SSC_TPR;       // Transmit Pointer Register\r
+       AT91_REG         SSC_TCR;       // Transmit Counter Register\r
+       AT91_REG         SSC_RNPR;      // Receive Next Pointer Register\r
+       AT91_REG         SSC_RNCR;      // Receive Next Counter Register\r
+       AT91_REG         SSC_TNPR;      // Transmit Next Pointer Register\r
+       AT91_REG         SSC_TNCR;      // Transmit Next Counter Register\r
+       AT91_REG         SSC_PTCR;      // PDC Transfer Control Register\r
+       AT91_REG         SSC_PTSR;      // PDC Transfer Status Register\r
+} AT91S_SSC, *AT91PS_SSC;\r
+#else\r
+#define SSC_CR          (AT91_CAST(AT91_REG *)         0x00000000) // (SSC_CR) Control Register\r
+#define SSC_CMR         (AT91_CAST(AT91_REG *)         0x00000004) // (SSC_CMR) Clock Mode Register\r
+#define SSC_RCMR        (AT91_CAST(AT91_REG *)         0x00000010) // (SSC_RCMR) Receive Clock ModeRegister\r
+#define SSC_RFMR        (AT91_CAST(AT91_REG *)         0x00000014) // (SSC_RFMR) Receive Frame Mode Register\r
+#define SSC_TCMR        (AT91_CAST(AT91_REG *)         0x00000018) // (SSC_TCMR) Transmit Clock Mode Register\r
+#define SSC_TFMR        (AT91_CAST(AT91_REG *)         0x0000001C) // (SSC_TFMR) Transmit Frame Mode Register\r
+#define SSC_RHR         (AT91_CAST(AT91_REG *)         0x00000020) // (SSC_RHR) Receive Holding Register\r
+#define SSC_THR         (AT91_CAST(AT91_REG *)         0x00000024) // (SSC_THR) Transmit Holding Register\r
+#define SSC_RSHR        (AT91_CAST(AT91_REG *)         0x00000030) // (SSC_RSHR) Receive Sync Holding Register\r
+#define SSC_TSHR        (AT91_CAST(AT91_REG *)         0x00000034) // (SSC_TSHR) Transmit Sync Holding Register\r
+#define SSC_SR          (AT91_CAST(AT91_REG *)         0x00000040) // (SSC_SR) Status Register\r
+#define SSC_IER         (AT91_CAST(AT91_REG *)         0x00000044) // (SSC_IER) Interrupt Enable Register\r
+#define SSC_IDR         (AT91_CAST(AT91_REG *)         0x00000048) // (SSC_IDR) Interrupt Disable Register\r
+#define SSC_IMR         (AT91_CAST(AT91_REG *)         0x0000004C) // (SSC_IMR) Interrupt Mask Register\r
+#define SSC_ADDRSIZE    (AT91_CAST(AT91_REG *)         0x000000EC) // (SSC_ADDRSIZE) SSC ADDRSIZE REGISTER \r
+#define SSC_IPNAME1     (AT91_CAST(AT91_REG *)         0x000000F0) // (SSC_IPNAME1) SSC IPNAME1 REGISTER \r
+#define SSC_IPNAME2     (AT91_CAST(AT91_REG *)         0x000000F4) // (SSC_IPNAME2) SSC IPNAME2 REGISTER \r
+#define SSC_FEATURES    (AT91_CAST(AT91_REG *)         0x000000F8) // (SSC_FEATURES) SSC FEATURES REGISTER \r
+#define SSC_VER         (AT91_CAST(AT91_REG *)         0x000000FC) // (SSC_VER) Version Register\r
+\r
+#endif\r
+// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- \r
+#define AT91C_SSC_RXEN        (0x1 <<  0) // (SSC) Receive Enable\r
+#define AT91C_SSC_RXDIS       (0x1 <<  1) // (SSC) Receive Disable\r
+#define AT91C_SSC_TXEN        (0x1 <<  8) // (SSC) Transmit Enable\r
+#define AT91C_SSC_TXDIS       (0x1 <<  9) // (SSC) Transmit Disable\r
+#define AT91C_SSC_SWRST       (0x1 << 15) // (SSC) Software Reset\r
+// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- \r
+#define AT91C_SSC_CKS         (0x3 <<  0) // (SSC) Receive/Transmit Clock Selection\r
+#define        AT91C_SSC_CKS_DIV                  (0x0) // (SSC) Divided Clock\r
+#define        AT91C_SSC_CKS_TK                   (0x1) // (SSC) TK Clock signal\r
+#define        AT91C_SSC_CKS_RK                   (0x2) // (SSC) RK pin\r
+#define AT91C_SSC_CKO         (0x7 <<  2) // (SSC) Receive/Transmit Clock Output Mode Selection\r
+#define        AT91C_SSC_CKO_NONE                 (0x0 <<  2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only\r
+#define        AT91C_SSC_CKO_CONTINOUS            (0x1 <<  2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output\r
+#define        AT91C_SSC_CKO_DATA_TX              (0x2 <<  2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output\r
+#define AT91C_SSC_CKI         (0x1 <<  5) // (SSC) Receive/Transmit Clock Inversion\r
+#define AT91C_SSC_CKG         (0x3 <<  6) // (SSC) Receive/Transmit Clock Gating Selection\r
+#define        AT91C_SSC_CKG_NONE                 (0x0 <<  6) // (SSC) Receive/Transmit Clock Gating: None, continuous clock\r
+#define        AT91C_SSC_CKG_LOW                  (0x1 <<  6) // (SSC) Receive/Transmit Clock enabled only if RF Low\r
+#define        AT91C_SSC_CKG_HIGH                 (0x2 <<  6) // (SSC) Receive/Transmit Clock enabled only if RF High\r
+#define AT91C_SSC_START       (0xF <<  8) // (SSC) Receive/Transmit Start Selection\r
+#define        AT91C_SSC_START_CONTINOUS            (0x0 <<  8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.\r
+#define        AT91C_SSC_START_TX                   (0x1 <<  8) // (SSC) Transmit/Receive start\r
+#define        AT91C_SSC_START_LOW_RF               (0x2 <<  8) // (SSC) Detection of a low level on RF input\r
+#define        AT91C_SSC_START_HIGH_RF              (0x3 <<  8) // (SSC) Detection of a high level on RF input\r
+#define        AT91C_SSC_START_FALL_RF              (0x4 <<  8) // (SSC) Detection of a falling edge on RF input\r
+#define        AT91C_SSC_START_RISE_RF              (0x5 <<  8) // (SSC) Detection of a rising edge on RF input\r
+#define        AT91C_SSC_START_LEVEL_RF             (0x6 <<  8) // (SSC) Detection of any level change on RF input\r
+#define        AT91C_SSC_START_EDGE_RF              (0x7 <<  8) // (SSC) Detection of any edge on RF input\r
+#define        AT91C_SSC_START_0                    (0x8 <<  8) // (SSC) Compare 0\r
+#define AT91C_SSC_STOP        (0x1 << 12) // (SSC) Receive Stop Selection\r
+#define AT91C_SSC_STTDLY      (0xFF << 16) // (SSC) Receive/Transmit Start Delay\r
+#define AT91C_SSC_PERIOD      (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection\r
+// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- \r
+#define AT91C_SSC_DATLEN      (0x1F <<  0) // (SSC) Data Length\r
+#define AT91C_SSC_LOOP        (0x1 <<  5) // (SSC) Loop Mode\r
+#define AT91C_SSC_MSBF        (0x1 <<  7) // (SSC) Most Significant Bit First\r
+#define AT91C_SSC_DATNB       (0xF <<  8) // (SSC) Data Number per Frame\r
+#define AT91C_SSC_FSLEN       (0xF << 16) // (SSC) Receive/Transmit Frame Sync length\r
+#define AT91C_SSC_FSOS        (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection\r
+#define        AT91C_SSC_FSOS_NONE                 (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only\r
+#define        AT91C_SSC_FSOS_NEGATIVE             (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse\r
+#define        AT91C_SSC_FSOS_POSITIVE             (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse\r
+#define        AT91C_SSC_FSOS_LOW                  (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer\r
+#define        AT91C_SSC_FSOS_HIGH                 (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer\r
+#define        AT91C_SSC_FSOS_TOGGLE               (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer\r
+#define AT91C_SSC_FSEDGE      (0x1 << 24) // (SSC) Frame Sync Edge Detection\r
+// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- \r
+// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- \r
+#define AT91C_SSC_DATDEF      (0x1 <<  5) // (SSC) Data Default Value\r
+#define AT91C_SSC_FSDEN       (0x1 << 23) // (SSC) Frame Sync Data Enable\r
+// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- \r
+#define AT91C_SSC_TXRDY       (0x1 <<  0) // (SSC) Transmit Ready\r
+#define AT91C_SSC_TXEMPTY     (0x1 <<  1) // (SSC) Transmit Empty\r
+#define AT91C_SSC_ENDTX       (0x1 <<  2) // (SSC) End Of Transmission\r
+#define AT91C_SSC_TXBUFE      (0x1 <<  3) // (SSC) Transmit Buffer Empty\r
+#define AT91C_SSC_RXRDY       (0x1 <<  4) // (SSC) Receive Ready\r
+#define AT91C_SSC_OVRUN       (0x1 <<  5) // (SSC) Receive Overrun\r
+#define AT91C_SSC_ENDRX       (0x1 <<  6) // (SSC) End of Reception\r
+#define AT91C_SSC_RXBUFF      (0x1 <<  7) // (SSC) Receive Buffer Full\r
+#define AT91C_SSC_CP0         (0x1 <<  8) // (SSC) Compare 0\r
+#define AT91C_SSC_CP1         (0x1 <<  9) // (SSC) Compare 1\r
+#define AT91C_SSC_TXSYN       (0x1 << 10) // (SSC) Transmit Sync\r
+#define AT91C_SSC_RXSYN       (0x1 << 11) // (SSC) Receive Sync\r
+#define AT91C_SSC_TXENA       (0x1 << 16) // (SSC) Transmit Enable\r
+#define AT91C_SSC_RXENA       (0x1 << 17) // (SSC) Receive Enable\r
+// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- \r
+// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- \r
+// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- \r
+\r
+// *****************************************************************************\r
+//              SOFTWARE API DEFINITION  FOR PWMC Channel Interface\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_PWMC_CH {\r
+       AT91_REG         PWMC_CMR;      // Channel Mode Register\r
+       AT91_REG         PWMC_CDTYR;    // Channel Duty Cycle Register\r
+       AT91_REG         PWMC_CDTYUPDR;         // Channel Duty Cycle Update Register\r
+       AT91_REG         PWMC_CPRDR;    // Channel Period Register\r
+       AT91_REG         PWMC_CPRDUPDR;         // Channel Period Update Register\r
+       AT91_REG         PWMC_CCNTR;    // Channel Counter Register\r
+       AT91_REG         PWMC_DTR;      // Channel Dead Time Value Register\r
+       AT91_REG         PWMC_DTUPDR;   // Channel Dead Time Update Value Register\r
+} AT91S_PWMC_CH, *AT91PS_PWMC_CH;\r
+#else\r
+#define PWMC_CMR        (AT91_CAST(AT91_REG *)         0x00000000) // (PWMC_CMR) Channel Mode Register\r
+#define PWMC_CDTYR      (AT91_CAST(AT91_REG *)         0x00000004) // (PWMC_CDTYR) Channel Duty Cycle Register\r
+#define PWMC_CDTYUPDR   (AT91_CAST(AT91_REG *)         0x00000008) // (PWMC_CDTYUPDR) Channel Duty Cycle Update Register\r
+#define PWMC_CPRDR      (AT91_CAST(AT91_REG *)         0x0000000C) // (PWMC_CPRDR) Channel Period Register\r
+#define PWMC_CPRDUPDR   (AT91_CAST(AT91_REG *)         0x00000010) // (PWMC_CPRDUPDR) Channel Period Update Register\r
+#define PWMC_CCNTR      (AT91_CAST(AT91_REG *)         0x00000014) // (PWMC_CCNTR) Channel Counter Register\r
+#define PWMC_DTR        (AT91_CAST(AT91_REG *)         0x00000018) // (PWMC_DTR) Channel Dead Time Value Register\r
+#define PWMC_DTUPDR     (AT91_CAST(AT91_REG *)         0x0000001C) // (PWMC_DTUPDR) Channel Dead Time Update Value Register\r
+\r
+#endif\r
+// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- \r
+#define AT91C_PWMC_CPRE       (0xF <<  0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx\r
+#define        AT91C_PWMC_CPRE_MCK                  (0x0) // (PWMC_CH) \r
+#define        AT91C_PWMC_CPRE_MCK_DIV_2            (0x1) // (PWMC_CH) \r
+#define        AT91C_PWMC_CPRE_MCK_DIV_4            (0x2) // (PWMC_CH) \r
+#define        AT91C_PWMC_CPRE_MCK_DIV_8            (0x3) // (PWMC_CH) \r
+#define        AT91C_PWMC_CPRE_MCK_DIV_16           (0x4) // (PWMC_CH) \r
+#define        AT91C_PWMC_CPRE_MCK_DIV_32           (0x5) // (PWMC_CH) \r
+#define        AT91C_PWMC_CPRE_MCK_DIV_64           (0x6) // (PWMC_CH) \r
+#define        AT91C_PWMC_CPRE_MCK_DIV_128          (0x7) // (PWMC_CH) \r
+#define        AT91C_PWMC_CPRE_MCK_DIV_256          (0x8) // (PWMC_CH) \r
+#define        AT91C_PWMC_CPRE_MCK_DIV_512          (0x9) // (PWMC_CH) \r
+#define        AT91C_PWMC_CPRE_MCK_DIV_1024         (0xA) // (PWMC_CH) \r
+#define        AT91C_PWMC_CPRE_MCKA                 (0xB) // (PWMC_CH) \r
+#define        AT91C_PWMC_CPRE_MCKB                 (0xC) // (PWMC_CH) \r
+#define AT91C_PWMC_CALG       (0x1 <<  8) // (PWMC_CH) Channel Alignment\r
+#define AT91C_PWMC_CPOL       (0x1 <<  9) // (PWMC_CH) Channel Polarity\r
+#define AT91C_PWMC_CES        (0x1 << 10) // (PWMC_CH) Counter Event Selection\r
+#define AT91C_PWMC_DTE        (0x1 << 16) // (PWMC_CH) Dead Time Genrator Enable\r
+#define AT91C_PWMC_DTHI       (0x1 << 17) // (PWMC_CH) Dead Time PWMHx Output Inverted\r
+#define AT91C_PWMC_DTLI       (0x1 << 18) // (PWMC_CH) Dead Time PWMLx Output Inverted\r
+// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- \r
+#define AT91C_PWMC_CDTY       (0xFFFFFF <<  0) // (PWMC_CH) Channel Duty Cycle\r
+// -------- PWMC_CDTYUPDR : (PWMC_CH Offset: 0x8) PWMC Channel Duty Cycle Update Register -------- \r
+#define AT91C_PWMC_CDTYUPD    (0xFFFFFF <<  0) // (PWMC_CH) Channel Duty Cycle Update\r
+// -------- PWMC_CPRDR : (PWMC_CH Offset: 0xc) PWMC Channel Period Register -------- \r
+#define AT91C_PWMC_CPRD       (0xFFFFFF <<  0) // (PWMC_CH) Channel Period\r
+// -------- PWMC_CPRDUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Period Update Register -------- \r
+#define AT91C_PWMC_CPRDUPD    (0xFFFFFF <<  0) // (PWMC_CH) Channel Period Update\r
+// -------- PWMC_CCNTR : (PWMC_CH Offset: 0x14) PWMC Channel Counter Register -------- \r
+#define AT91C_PWMC_CCNT       (0xFFFFFF <<  0) // (PWMC_CH) Channel Counter\r
+// -------- PWMC_DTR : (PWMC_CH Offset: 0x18) Channel Dead Time Value Register -------- \r
+#define AT91C_PWMC_DTL        (0xFFFF <<  0) // (PWMC_CH) Channel Dead Time for PWML\r
+#define AT91C_PWMC_DTH        (0xFFFF << 16) // (PWMC_CH) Channel Dead Time for PWMH\r
+// -------- PWMC_DTUPDR : (PWMC_CH Offset: 0x1c) Channel Dead Time Value Register -------- \r
+#define AT91C_PWMC_DTLUPD     (0xFFFF <<  0) // (PWMC_CH) Channel Dead Time Update for PWML.\r
+#define AT91C_PWMC_DTHUPD     (0xFFFF << 16) // (PWMC_CH) Channel Dead Time Update for PWMH.\r
+\r
+// *****************************************************************************\r
+//              SOFTWARE API DEFINITION  FOR Pulse Width Modulation Controller Interface\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_PWMC {\r
+       AT91_REG         PWMC_MR;       // PWMC Mode Register\r
+       AT91_REG         PWMC_ENA;      // PWMC Enable Register\r
+       AT91_REG         PWMC_DIS;      // PWMC Disable Register\r
+       AT91_REG         PWMC_SR;       // PWMC Status Register\r
+       AT91_REG         PWMC_IER1;     // PWMC Interrupt Enable Register 1\r
+       AT91_REG         PWMC_IDR1;     // PWMC Interrupt Disable Register 1\r
+       AT91_REG         PWMC_IMR1;     // PWMC Interrupt Mask Register 1\r
+       AT91_REG         PWMC_ISR1;     // PWMC Interrupt Status Register 1\r
+       AT91_REG         PWMC_SYNC;     // PWM Synchronized Channels Register\r
+       AT91_REG         Reserved0[1];  // \r
+       AT91_REG         PWMC_UPCR;     // PWM Update Control Register\r
+       AT91_REG         PWMC_SCUP;     // PWM Update Period Register\r
+       AT91_REG         PWMC_SCUPUPD;  // PWM Update Period Update Register\r
+       AT91_REG         PWMC_IER2;     // PWMC Interrupt Enable Register 2\r
+       AT91_REG         PWMC_IDR2;     // PWMC Interrupt Disable Register 2\r
+       AT91_REG         PWMC_IMR2;     // PWMC Interrupt Mask Register 2\r
+       AT91_REG         PWMC_ISR2;     // PWMC Interrupt Status Register 2\r
+       AT91_REG         PWMC_OOV;      // PWM Output Override Value Register\r
+       AT91_REG         PWMC_OS;       // PWM Output Selection Register\r
+       AT91_REG         PWMC_OSS;      // PWM Output Selection Set Register\r
+       AT91_REG         PWMC_OSC;      // PWM Output Selection Clear Register\r
+       AT91_REG         PWMC_OSSUPD;   // PWM Output Selection Set Update Register\r
+       AT91_REG         PWMC_OSCUPD;   // PWM Output Selection Clear Update Register\r
+       AT91_REG         PWMC_FMR;      // PWM Fault Mode Register\r
+       AT91_REG         PWMC_FSR;      // PWM Fault Mode Status Register\r
+       AT91_REG         PWMC_FCR;      // PWM Fault Mode Clear Register\r
+       AT91_REG         PWMC_FPV;      // PWM Fault Protection Value Register\r
+       AT91_REG         PWMC_FPER1;    // PWM Fault Protection Enable Register 1\r
+       AT91_REG         PWMC_FPER2;    // PWM Fault Protection Enable Register 2\r
+       AT91_REG         PWMC_FPER3;    // PWM Fault Protection Enable Register 3\r
+       AT91_REG         PWMC_FPER4;    // PWM Fault Protection Enable Register 4\r
+       AT91_REG         PWMC_EL0MR;    // PWM Event Line 0 Mode Register\r
+       AT91_REG         PWMC_EL1MR;    // PWM Event Line 1 Mode Register\r
+       AT91_REG         PWMC_EL2MR;    // PWM Event Line 2 Mode Register\r
+       AT91_REG         PWMC_EL3MR;    // PWM Event Line 3 Mode Register\r
+       AT91_REG         PWMC_EL4MR;    // PWM Event Line 4 Mode Register\r
+       AT91_REG         PWMC_EL5MR;    // PWM Event Line 5 Mode Register\r
+       AT91_REG         PWMC_EL6MR;    // PWM Event Line 6 Mode Register\r
+       AT91_REG         PWMC_EL7MR;    // PWM Event Line 7 Mode Register\r
+       AT91_REG         Reserved1[18];         // \r
+       AT91_REG         PWMC_WPCR;     // PWM Write Protection Enable Register\r
+       AT91_REG         PWMC_WPSR;     // PWM Write Protection Status Register\r
+       AT91_REG         PWMC_ADDRSIZE;         // PWMC ADDRSIZE REGISTER \r
+       AT91_REG         PWMC_IPNAME1;  // PWMC IPNAME1 REGISTER \r
+       AT91_REG         PWMC_IPNAME2;  // PWMC IPNAME2 REGISTER \r
+       AT91_REG         PWMC_FEATURES;         // PWMC FEATURES REGISTER \r
+       AT91_REG         PWMC_VER;      // PWMC Version Register\r
+       AT91_REG         PWMC_RPR;      // Receive Pointer Register\r
+       AT91_REG         PWMC_RCR;      // Receive Counter Register\r
+       AT91_REG         PWMC_TPR;      // Transmit Pointer Register\r
+       AT91_REG         PWMC_TCR;      // Transmit Counter Register\r
+       AT91_REG         PWMC_RNPR;     // Receive Next Pointer Register\r
+       AT91_REG         PWMC_RNCR;     // Receive Next Counter Register\r
+       AT91_REG         PWMC_TNPR;     // Transmit Next Pointer Register\r
+       AT91_REG         PWMC_TNCR;     // Transmit Next Counter Register\r
+       AT91_REG         PWMC_PTCR;     // PDC Transfer Control Register\r
+       AT91_REG         PWMC_PTSR;     // PDC Transfer Status Register\r
+       AT91_REG         Reserved2[2];  // \r
+       AT91_REG         PWMC_CMP0V;    // PWM Comparison Value 0 Register\r
+       AT91_REG         PWMC_CMP0VUPD;         // PWM Comparison Value 0 Update Register\r
+       AT91_REG         PWMC_CMP0M;    // PWM Comparison Mode 0 Register\r
+       AT91_REG         PWMC_CMP0MUPD;         // PWM Comparison Mode 0 Update Register\r
+       AT91_REG         PWMC_CMP1V;    // PWM Comparison Value 1 Register\r
+       AT91_REG         PWMC_CMP1VUPD;         // PWM Comparison Value 1 Update Register\r
+       AT91_REG         PWMC_CMP1M;    // PWM Comparison Mode 1 Register\r
+       AT91_REG         PWMC_CMP1MUPD;         // PWM Comparison Mode 1 Update Register\r
+       AT91_REG         PWMC_CMP2V;    // PWM Comparison Value 2 Register\r
+       AT91_REG         PWMC_CMP2VUPD;         // PWM Comparison Value 2 Update Register\r
+       AT91_REG         PWMC_CMP2M;    // PWM Comparison Mode 2 Register\r
+       AT91_REG         PWMC_CMP2MUPD;         // PWM Comparison Mode 2 Update Register\r
+       AT91_REG         PWMC_CMP3V;    // PWM Comparison Value 3 Register\r
+       AT91_REG         PWMC_CMP3VUPD;         // PWM Comparison Value 3 Update Register\r
+       AT91_REG         PWMC_CMP3M;    // PWM Comparison Mode 3 Register\r
+       AT91_REG         PWMC_CMP3MUPD;         // PWM Comparison Mode 3 Update Register\r
+       AT91_REG         PWMC_CMP4V;    // PWM Comparison Value 4 Register\r
+       AT91_REG         PWMC_CMP4VUPD;         // PWM Comparison Value 4 Update Register\r
+       AT91_REG         PWMC_CMP4M;    // PWM Comparison Mode 4 Register\r
+       AT91_REG         PWMC_CMP4MUPD;         // PWM Comparison Mode 4 Update Register\r
+       AT91_REG         PWMC_CMP5V;    // PWM Comparison Value 5 Register\r
+       AT91_REG         PWMC_CMP5VUPD;         // PWM Comparison Value 5 Update Register\r
+       AT91_REG         PWMC_CMP5M;    // PWM Comparison Mode 5 Register\r
+       AT91_REG         PWMC_CMP5MUPD;         // PWM Comparison Mode 5 Update Register\r
+       AT91_REG         PWMC_CMP6V;    // PWM Comparison Value 6 Register\r
+       AT91_REG         PWMC_CMP6VUPD;         // PWM Comparison Value 6 Update Register\r
+       AT91_REG         PWMC_CMP6M;    // PWM Comparison Mode 6 Register\r
+       AT91_REG         PWMC_CMP6MUPD;         // PWM Comparison Mode 6 Update Register\r
+       AT91_REG         PWMC_CMP7V;    // PWM Comparison Value 7 Register\r
+       AT91_REG         PWMC_CMP7VUPD;         // PWM Comparison Value 7 Update Register\r
+       AT91_REG         PWMC_CMP7M;    // PWM Comparison Mode 7 Register\r
+       AT91_REG         PWMC_CMP7MUPD;         // PWM Comparison Mode 7 Update Register\r
+       AT91_REG         Reserved3[20];         // \r
+       AT91S_PWMC_CH    PWMC_CH[8];    // PWMC Channel 0\r
+} AT91S_PWMC, *AT91PS_PWMC;\r
+#else\r
+#define PWMC_MR         (AT91_CAST(AT91_REG *)         0x00000000) // (PWMC_MR) PWMC Mode Register\r
+#define PWMC_ENA        (AT91_CAST(AT91_REG *)         0x00000004) // (PWMC_ENA) PWMC Enable Register\r
+#define PWMC_DIS        (AT91_CAST(AT91_REG *)         0x00000008) // (PWMC_DIS) PWMC Disable Register\r
+#define PWMC_SR         (AT91_CAST(AT91_REG *)         0x0000000C) // (PWMC_SR) PWMC Status Register\r
+#define PWMC_IER1       (AT91_CAST(AT91_REG *)         0x00000010) // (PWMC_IER1) PWMC Interrupt Enable Register 1\r
+#define PWMC_IDR1       (AT91_CAST(AT91_REG *)         0x00000014) // (PWMC_IDR1) PWMC Interrupt Disable Register 1\r
+#define PWMC_IMR1       (AT91_CAST(AT91_REG *)         0x00000018) // (PWMC_IMR1) PWMC Interrupt Mask Register 1\r
+#define PWMC_ISR1       (AT91_CAST(AT91_REG *)         0x0000001C) // (PWMC_ISR1) PWMC Interrupt Status Register 1\r
+#define PWMC_SYNC       (AT91_CAST(AT91_REG *)         0x00000020) // (PWMC_SYNC) PWM Synchronized Channels Register\r
+#define PWMC_UPCR       (AT91_CAST(AT91_REG *)         0x00000028) // (PWMC_UPCR) PWM Update Control Register\r
+#define PWMC_SCUP       (AT91_CAST(AT91_REG *)         0x0000002C) // (PWMC_SCUP) PWM Update Period Register\r
+#define PWMC_SCUPUPD    (AT91_CAST(AT91_REG *)         0x00000030) // (PWMC_SCUPUPD) PWM Update Period Update Register\r
+#define PWMC_IER2       (AT91_CAST(AT91_REG *)         0x00000034) // (PWMC_IER2) PWMC Interrupt Enable Register 2\r
+#define PWMC_IDR2       (AT91_CAST(AT91_REG *)         0x00000038) // (PWMC_IDR2) PWMC Interrupt Disable Register 2\r
+#define PWMC_IMR2       (AT91_CAST(AT91_REG *)         0x0000003C) // (PWMC_IMR2) PWMC Interrupt Mask Register 2\r
+#define PWMC_ISR2       (AT91_CAST(AT91_REG *)         0x00000040) // (PWMC_ISR2) PWMC Interrupt Status Register 2\r
+#define PWMC_OOV        (AT91_CAST(AT91_REG *)         0x00000044) // (PWMC_OOV) PWM Output Override Value Register\r
+#define PWMC_OS         (AT91_CAST(AT91_REG *)         0x00000048) // (PWMC_OS) PWM Output Selection Register\r
+#define PWMC_OSS        (AT91_CAST(AT91_REG *)         0x0000004C) // (PWMC_OSS) PWM Output Selection Set Register\r
+#define PWMC_OSC        (AT91_CAST(AT91_REG *)         0x00000050) // (PWMC_OSC) PWM Output Selection Clear Register\r
+#define PWMC_OSSUPD     (AT91_CAST(AT91_REG *)         0x00000054) // (PWMC_OSSUPD) PWM Output Selection Set Update Register\r
+#define PWMC_OSCUPD     (AT91_CAST(AT91_REG *)         0x00000058) // (PWMC_OSCUPD) PWM Output Selection Clear Update Register\r
+#define PWMC_FMR        (AT91_CAST(AT91_REG *)         0x0000005C) // (PWMC_FMR) PWM Fault Mode Register\r
+#define PWMC_FSR        (AT91_CAST(AT91_REG *)         0x00000060) // (PWMC_FSR) PWM Fault Mode Status Register\r
+#define PWMC_FCR        (AT91_CAST(AT91_REG *)         0x00000064) // (PWMC_FCR) PWM Fault Mode Clear Register\r
+#define PWMC_FPV        (AT91_CAST(AT91_REG *)         0x00000068) // (PWMC_FPV) PWM Fault Protection Value Register\r
+#define PWMC_FPER1      (AT91_CAST(AT91_REG *)         0x0000006C) // (PWMC_FPER1) PWM Fault Protection Enable Register 1\r
+#define PWMC_FPER2      (AT91_CAST(AT91_REG *)         0x00000070) // (PWMC_FPER2) PWM Fault Protection Enable Register 2\r
+#define PWMC_FPER3      (AT91_CAST(AT91_REG *)         0x00000074) // (PWMC_FPER3) PWM Fault Protection Enable Register 3\r
+#define PWMC_FPER4      (AT91_CAST(AT91_REG *)         0x00000078) // (PWMC_FPER4) PWM Fault Protection Enable Register 4\r
+#define PWMC_EL0MR      (AT91_CAST(AT91_REG *)         0x0000007C) // (PWMC_EL0MR) PWM Event Line 0 Mode Register\r
+#define PWMC_EL1MR      (AT91_CAST(AT91_REG *)         0x00000080) // (PWMC_EL1MR) PWM Event Line 1 Mode Register\r
+#define PWMC_EL2MR      (AT91_CAST(AT91_REG *)         0x00000084) // (PWMC_EL2MR) PWM Event Line 2 Mode Register\r
+#define PWMC_EL3MR      (AT91_CAST(AT91_REG *)         0x00000088) // (PWMC_EL3MR) PWM Event Line 3 Mode Register\r
+#define PWMC_EL4MR      (AT91_CAST(AT91_REG *)         0x0000008C) // (PWMC_EL4MR) PWM Event Line 4 Mode Register\r
+#define PWMC_EL5MR      (AT91_CAST(AT91_REG *)         0x00000090) // (PWMC_EL5MR) PWM Event Line 5 Mode Register\r
+#define PWMC_EL6MR      (AT91_CAST(AT91_REG *)         0x00000094) // (PWMC_EL6MR) PWM Event Line 6 Mode Register\r
+#define PWMC_EL7MR      (AT91_CAST(AT91_REG *)         0x00000098) // (PWMC_EL7MR) PWM Event Line 7 Mode Register\r
+#define PWMC_WPCR       (AT91_CAST(AT91_REG *)         0x000000E4) // (PWMC_WPCR) PWM Write Protection Enable Register\r
+#define PWMC_WPSR       (AT91_CAST(AT91_REG *)         0x000000E8) // (PWMC_WPSR) PWM Write Protection Status Register\r
+#define PWMC_ADDRSIZE   (AT91_CAST(AT91_REG *)         0x000000EC) // (PWMC_ADDRSIZE) PWMC ADDRSIZE REGISTER \r
+#define PWMC_IPNAME1    (AT91_CAST(AT91_REG *)         0x000000F0) // (PWMC_IPNAME1) PWMC IPNAME1 REGISTER \r
+#define PWMC_IPNAME2    (AT91_CAST(AT91_REG *)         0x000000F4) // (PWMC_IPNAME2) PWMC IPNAME2 REGISTER \r
+#define PWMC_FEATURES   (AT91_CAST(AT91_REG *)         0x000000F8) // (PWMC_FEATURES) PWMC FEATURES REGISTER \r
+#define PWMC_VER        (AT91_CAST(AT91_REG *)         0x000000FC) // (PWMC_VER) PWMC Version Register\r
+#define PWMC_CMP0V      (AT91_CAST(AT91_REG *)         0x00000130) // (PWMC_CMP0V) PWM Comparison Value 0 Register\r
+#define PWMC_CMP0VUPD   (AT91_CAST(AT91_REG *)         0x00000134) // (PWMC_CMP0VUPD) PWM Comparison Value 0 Update Register\r
+#define PWMC_CMP0M      (AT91_CAST(AT91_REG *)         0x00000138) // (PWMC_CMP0M) PWM Comparison Mode 0 Register\r
+#define PWMC_CMP0MUPD   (AT91_CAST(AT91_REG *)         0x0000013C) // (PWMC_CMP0MUPD) PWM Comparison Mode 0 Update Register\r
+#define PWMC_CMP1V      (AT91_CAST(AT91_REG *)         0x00000140) // (PWMC_CMP1V) PWM Comparison Value 1 Register\r
+#define PWMC_CMP1VUPD   (AT91_CAST(AT91_REG *)         0x00000144) // (PWMC_CMP1VUPD) PWM Comparison Value 1 Update Register\r
+#define PWMC_CMP1M      (AT91_CAST(AT91_REG *)         0x00000148) // (PWMC_CMP1M) PWM Comparison Mode 1 Register\r
+#define PWMC_CMP1MUPD   (AT91_CAST(AT91_REG *)         0x0000014C) // (PWMC_CMP1MUPD) PWM Comparison Mode 1 Update Register\r
+#define PWMC_CMP2V      (AT91_CAST(AT91_REG *)         0x00000150) // (PWMC_CMP2V) PWM Comparison Value 2 Register\r
+#define PWMC_CMP2VUPD   (AT91_CAST(AT91_REG *)         0x00000154) // (PWMC_CMP2VUPD) PWM Comparison Value 2 Update Register\r
+#define PWMC_CMP2M      (AT91_CAST(AT91_REG *)         0x00000158) // (PWMC_CMP2M) PWM Comparison Mode 2 Register\r
+#define PWMC_CMP2MUPD   (AT91_CAST(AT91_REG *)         0x0000015C) // (PWMC_CMP2MUPD) PWM Comparison Mode 2 Update Register\r
+#define PWMC_CMP3V      (AT91_CAST(AT91_REG *)         0x00000160) // (PWMC_CMP3V) PWM Comparison Value 3 Register\r
+#define PWMC_CMP3VUPD   (AT91_CAST(AT91_REG *)         0x00000164) // (PWMC_CMP3VUPD) PWM Comparison Value 3 Update Register\r
+#define PWMC_CMP3M      (AT91_CAST(AT91_REG *)         0x00000168) // (PWMC_CMP3M) PWM Comparison Mode 3 Register\r
+#define PWMC_CMP3MUPD   (AT91_CAST(AT91_REG *)         0x0000016C) // (PWMC_CMP3MUPD) PWM Comparison Mode 3 Update Register\r
+#define PWMC_CMP4V      (AT91_CAST(AT91_REG *)         0x00000170) // (PWMC_CMP4V) PWM Comparison Value 4 Register\r
+#define PWMC_CMP4VUPD   (AT91_CAST(AT91_REG *)         0x00000174) // (PWMC_CMP4VUPD) PWM Comparison Value 4 Update Register\r
+#define PWMC_CMP4M      (AT91_CAST(AT91_REG *)         0x00000178) // (PWMC_CMP4M) PWM Comparison Mode 4 Register\r
+#define PWMC_CMP4MUPD   (AT91_CAST(AT91_REG *)         0x0000017C) // (PWMC_CMP4MUPD) PWM Comparison Mode 4 Update Register\r
+#define PWMC_CMP5V      (AT91_CAST(AT91_REG *)         0x00000180) // (PWMC_CMP5V) PWM Comparison Value 5 Register\r
+#define PWMC_CMP5VUPD   (AT91_CAST(AT91_REG *)         0x00000184) // (PWMC_CMP5VUPD) PWM Comparison Value 5 Update Register\r
+#define PWMC_CMP5M      (AT91_CAST(AT91_REG *)         0x00000188) // (PWMC_CMP5M) PWM Comparison Mode 5 Register\r
+#define PWMC_CMP5MUPD   (AT91_CAST(AT91_REG *)         0x0000018C) // (PWMC_CMP5MUPD) PWM Comparison Mode 5 Update Register\r
+#define PWMC_CMP6V      (AT91_CAST(AT91_REG *)         0x00000190) // (PWMC_CMP6V) PWM Comparison Value 6 Register\r
+#define PWMC_CMP6VUPD   (AT91_CAST(AT91_REG *)         0x00000194) // (PWMC_CMP6VUPD) PWM Comparison Value 6 Update Register\r
+#define PWMC_CMP6M      (AT91_CAST(AT91_REG *)         0x00000198) // (PWMC_CMP6M) PWM Comparison Mode 6 Register\r
+#define PWMC_CMP6MUPD   (AT91_CAST(AT91_REG *)         0x0000019C) // (PWMC_CMP6MUPD) PWM Comparison Mode 6 Update Register\r
+#define PWMC_CMP7V      (AT91_CAST(AT91_REG *)         0x000001A0) // (PWMC_CMP7V) PWM Comparison Value 7 Register\r
+#define PWMC_CMP7VUPD   (AT91_CAST(AT91_REG *)         0x000001A4) // (PWMC_CMP7VUPD) PWM Comparison Value 7 Update Register\r
+#define PWMC_CMP7M      (AT91_CAST(AT91_REG *)         0x000001A8) // (PWMC_CMP7M) PWM Comparison Mode 7 Register\r
+#define PWMC_CMP7MUPD   (AT91_CAST(AT91_REG *)         0x000001AC) // (PWMC_CMP7MUPD) PWM Comparison Mode 7 Update Register\r
+\r
+#endif\r
+// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- \r
+#define AT91C_PWMC_DIVA       (0xFF <<  0) // (PWMC) CLKA divide factor.\r
+#define AT91C_PWMC_PREA       (0xF <<  8) // (PWMC) Divider Input Clock Prescaler A\r
+#define        AT91C_PWMC_PREA_MCK                  (0x0 <<  8) // (PWMC) \r
+#define        AT91C_PWMC_PREA_MCK_DIV_2            (0x1 <<  8) // (PWMC) \r
+#define        AT91C_PWMC_PREA_MCK_DIV_4            (0x2 <<  8) // (PWMC) \r
+#define        AT91C_PWMC_PREA_MCK_DIV_8            (0x3 <<  8) // (PWMC) \r
+#define        AT91C_PWMC_PREA_MCK_DIV_16           (0x4 <<  8) // (PWMC) \r
+#define        AT91C_PWMC_PREA_MCK_DIV_32           (0x5 <<  8) // (PWMC) \r
+#define        AT91C_PWMC_PREA_MCK_DIV_64           (0x6 <<  8) // (PWMC) \r
+#define        AT91C_PWMC_PREA_MCK_DIV_128          (0x7 <<  8) // (PWMC) \r
+#define        AT91C_PWMC_PREA_MCK_DIV_256          (0x8 <<  8) // (PWMC) \r
+#define AT91C_PWMC_DIVB       (0xFF << 16) // (PWMC) CLKB divide factor.\r
+#define AT91C_PWMC_PREB       (0xF << 24) // (PWMC) Divider Input Clock Prescaler B\r
+#define        AT91C_PWMC_PREB_MCK                  (0x0 << 24) // (PWMC) \r
+#define        AT91C_PWMC_PREB_MCK_DIV_2            (0x1 << 24) // (PWMC) \r
+#define        AT91C_PWMC_PREB_MCK_DIV_4            (0x2 << 24) // (PWMC) \r
+#define        AT91C_PWMC_PREB_MCK_DIV_8            (0x3 << 24) // (PWMC) \r
+#define        AT91C_PWMC_PREB_MCK_DIV_16           (0x4 << 24) // (PWMC) \r
+#define        AT91C_PWMC_PREB_MCK_DIV_32           (0x5 << 24) // (PWMC) \r
+#define        AT91C_PWMC_PREB_MCK_DIV_64           (0x6 << 24) // (PWMC) \r
+#define        AT91C_PWMC_PREB_MCK_DIV_128          (0x7 << 24) // (PWMC) \r
+#define        AT91C_PWMC_PREB_MCK_DIV_256          (0x8 << 24) // (PWMC) \r
+#define AT91C_PWMC_CLKSEL     (0x1 << 31) // (PWMC) CCK Source Clock Selection\r
+// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- \r
+#define AT91C_PWMC_CHID0      (0x1 <<  0) // (PWMC) Channel ID 0\r
+#define AT91C_PWMC_CHID1      (0x1 <<  1) // (PWMC) Channel ID 1\r
+#define AT91C_PWMC_CHID2      (0x1 <<  2) // (PWMC) Channel ID 2\r
+#define AT91C_PWMC_CHID3      (0x1 <<  3) // (PWMC) Channel ID 3\r
+#define AT91C_PWMC_CHID4      (0x1 <<  4) // (PWMC) Channel ID 4\r
+#define AT91C_PWMC_CHID5      (0x1 <<  5) // (PWMC) Channel ID 5\r
+#define AT91C_PWMC_CHID6      (0x1 <<  6) // (PWMC) Channel ID 6\r
+#define AT91C_PWMC_CHID7      (0x1 <<  7) // (PWMC) Channel ID 7\r
+#define AT91C_PWMC_CHID8      (0x1 <<  8) // (PWMC) Channel ID 8\r
+#define AT91C_PWMC_CHID9      (0x1 <<  9) // (PWMC) Channel ID 9\r
+#define AT91C_PWMC_CHID10     (0x1 << 10) // (PWMC) Channel ID 10\r
+#define AT91C_PWMC_CHID11     (0x1 << 11) // (PWMC) Channel ID 11\r
+#define AT91C_PWMC_CHID12     (0x1 << 12) // (PWMC) Channel ID 12\r
+#define AT91C_PWMC_CHID13     (0x1 << 13) // (PWMC) Channel ID 13\r
+#define AT91C_PWMC_CHID14     (0x1 << 14) // (PWMC) Channel ID 14\r
+#define AT91C_PWMC_CHID15     (0x1 << 15) // (PWMC) Channel ID 15\r
+// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- \r
+// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- \r
+// -------- PWMC_IER1 : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- \r
+#define AT91C_PWMC_FCHID0     (0x1 << 16) // (PWMC) Fault Event Channel ID 0\r
+#define AT91C_PWMC_FCHID1     (0x1 << 17) // (PWMC) Fault Event Channel ID 1\r
+#define AT91C_PWMC_FCHID2     (0x1 << 18) // (PWMC) Fault Event Channel ID 2\r
+#define AT91C_PWMC_FCHID3     (0x1 << 19) // (PWMC) Fault Event Channel ID 3\r
+#define AT91C_PWMC_FCHID4     (0x1 << 20) // (PWMC) Fault Event Channel ID 4\r
+#define AT91C_PWMC_FCHID5     (0x1 << 21) // (PWMC) Fault Event Channel ID 5\r
+#define AT91C_PWMC_FCHID6     (0x1 << 22) // (PWMC) Fault Event Channel ID 6\r
+#define AT91C_PWMC_FCHID7     (0x1 << 23) // (PWMC) Fault Event Channel ID 7\r
+#define AT91C_PWMC_FCHID8     (0x1 << 24) // (PWMC) Fault Event Channel ID 8\r
+#define AT91C_PWMC_FCHID9     (0x1 << 25) // (PWMC) Fault Event Channel ID 9\r
+#define AT91C_PWMC_FCHID10    (0x1 << 26) // (PWMC) Fault Event Channel ID 10\r
+#define AT91C_PWMC_FCHID11    (0x1 << 27) // (PWMC) Fault Event Channel ID 11\r
+#define AT91C_PWMC_FCHID12    (0x1 << 28) // (PWMC) Fault Event Channel ID 12\r
+#define AT91C_PWMC_FCHID13    (0x1 << 29) // (PWMC) Fault Event Channel ID 13\r
+#define AT91C_PWMC_FCHID14    (0x1 << 30) // (PWMC) Fault Event Channel ID 14\r
+#define AT91C_PWMC_FCHID15    (0x1 << 31) // (PWMC) Fault Event Channel ID 15\r
+// -------- PWMC_IDR1 : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- \r
+// -------- PWMC_IMR1 : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- \r
+// -------- PWMC_ISR1 : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- \r
+// -------- PWMC_SYNC : (PWMC Offset: 0x20) PWMC Synchronous Channels Register -------- \r
+#define AT91C_PWMC_SYNC0      (0x1 <<  0) // (PWMC) Synchronous Channel ID 0\r
+#define AT91C_PWMC_SYNC1      (0x1 <<  1) // (PWMC) Synchronous Channel ID 1\r
+#define AT91C_PWMC_SYNC2      (0x1 <<  2) // (PWMC) Synchronous Channel ID 2\r
+#define AT91C_PWMC_SYNC3      (0x1 <<  3) // (PWMC) Synchronous Channel ID 3\r
+#define AT91C_PWMC_SYNC4      (0x1 <<  4) // (PWMC) Synchronous Channel ID 4\r
+#define AT91C_PWMC_SYNC5      (0x1 <<  5) // (PWMC) Synchronous Channel ID 5\r
+#define AT91C_PWMC_SYNC6      (0x1 <<  6) // (PWMC) Synchronous Channel ID 6\r
+#define AT91C_PWMC_SYNC7      (0x1 <<  7) // (PWMC) Synchronous Channel ID 7\r
+#define AT91C_PWMC_SYNC8      (0x1 <<  8) // (PWMC) Synchronous Channel ID 8\r
+#define AT91C_PWMC_SYNC9      (0x1 <<  9) // (PWMC) Synchronous Channel ID 9\r
+#define AT91C_PWMC_SYNC10     (0x1 << 10) // (PWMC) Synchronous Channel ID 10\r
+#define AT91C_PWMC_SYNC11     (0x1 << 11) // (PWMC) Synchronous Channel ID 11\r
+#define AT91C_PWMC_SYNC12     (0x1 << 12) // (PWMC) Synchronous Channel ID 12\r
+#define AT91C_PWMC_SYNC13     (0x1 << 13) // (PWMC) Synchronous Channel ID 13\r
+#define AT91C_PWMC_SYNC14     (0x1 << 14) // (PWMC) Synchronous Channel ID 14\r
+#define AT91C_PWMC_SYNC15     (0x1 << 15) // (PWMC) Synchronous Channel ID 15\r
+#define AT91C_PWMC_UPDM       (0x3 << 16) // (PWMC) Synchronous Channels Update mode\r
+#define        AT91C_PWMC_UPDM_MODE0                (0x0 << 16) // (PWMC) Manual write of data and manual trigger of the update\r
+#define        AT91C_PWMC_UPDM_MODE1                (0x1 << 16) // (PWMC) Manual write of data and automatic trigger of the update\r
+#define        AT91C_PWMC_UPDM_MODE2                (0x2 << 16) // (PWMC) Automatic write of data and automatic trigger of the update\r
+// -------- PWMC_UPCR : (PWMC Offset: 0x28) PWMC Update Control Register -------- \r
+#define AT91C_PWMC_UPDULOCK   (0x1 <<  0) // (PWMC) Synchronized Channels Duty Cycle Update Unlock\r
+// -------- PWMC_SCUP : (PWMC Offset: 0x2c) PWM Update Period Register -------- \r
+#define AT91C_PWMC_UPR        (0xF <<  0) // (PWMC) PWM Update Period.\r
+#define AT91C_PWMC_UPRCNT     (0xF <<  4) // (PWMC) PWM Update Period Counter.\r
+// -------- PWMC_SCUPUPD : (PWMC Offset: 0x30) PWM Update Period Update Register -------- \r
+#define AT91C_PWMC_UPVUPDAL   (0xF <<  0) // (PWMC) PWM Update Period Update.\r
+// -------- PWMC_IER2 : (PWMC Offset: 0x34) PWMC Interrupt Enable Register -------- \r
+#define AT91C_PWMC_WRDY       (0x1 <<  0) // (PWMC) PDC Write Ready\r
+#define AT91C_PWMC_ENDTX      (0x1 <<  1) // (PWMC) PDC End of TX Buffer\r
+#define AT91C_PWMC_TXBUFE     (0x1 <<  2) // (PWMC) PDC End of TX Buffer\r
+#define AT91C_PWMC_UNRE       (0x1 <<  3) // (PWMC) PDC End of TX Buffer\r
+// -------- PWMC_IDR2 : (PWMC Offset: 0x38) PWMC Interrupt Disable Register -------- \r
+// -------- PWMC_IMR2 : (PWMC Offset: 0x3c) PWMC Interrupt Mask Register -------- \r
+// -------- PWMC_ISR2 : (PWMC Offset: 0x40) PWMC Interrupt Status Register -------- \r
+#define AT91C_PWMC_CMPM0      (0x1 <<  8) // (PWMC) Comparison x Match\r
+#define AT91C_PWMC_CMPM1      (0x1 <<  9) // (PWMC) Comparison x Match\r
+#define AT91C_PWMC_CMPM2      (0x1 << 10) // (PWMC) Comparison x Match\r
+#define AT91C_PWMC_CMPM3      (0x1 << 11) // (PWMC) Comparison x Match\r
+#define AT91C_PWMC_CMPM4      (0x1 << 12) // (PWMC) Comparison x Match\r
+#define AT91C_PWMC_CMPM5      (0x1 << 13) // (PWMC) Comparison x Match\r
+#define AT91C_PWMC_CMPM6      (0x1 << 14) // (PWMC) Comparison x Match\r
+#define AT91C_PWMC_CMPM7      (0x1 << 15) // (PWMC) Comparison x Match\r
+#define AT91C_PWMC_CMPU0      (0x1 << 16) // (PWMC) Comparison x Update\r
+#define AT91C_PWMC_CMPU1      (0x1 << 17) // (PWMC) Comparison x Update\r
+#define AT91C_PWMC_CMPU2      (0x1 << 18) // (PWMC) Comparison x Update\r
+#define AT91C_PWMC_CMPU3      (0x1 << 19) // (PWMC) Comparison x Update\r
+#define AT91C_PWMC_CMPU4      (0x1 << 20) // (PWMC) Comparison x Update\r
+#define AT91C_PWMC_CMPU5      (0x1 << 21) // (PWMC) Comparison x Update\r
+#define AT91C_PWMC_CMPU6      (0x1 << 22) // (PWMC) Comparison x Update\r
+#define AT91C_PWMC_CMPU7      (0x1 << 23) // (PWMC) Comparison x Update\r
+// -------- PWMC_OOV : (PWMC Offset: 0x44) PWM Output Override Value Register -------- \r
+#define AT91C_PWMC_OOVH0      (0x1 <<  0) // (PWMC) Output Override Value for PWMH output of the channel 0\r
+#define AT91C_PWMC_OOVH1      (0x1 <<  1) // (PWMC) Output Override Value for PWMH output of the channel 1\r
+#define AT91C_PWMC_OOVH2      (0x1 <<  2) // (PWMC) Output Override Value for PWMH output of the channel 2\r
+#define AT91C_PWMC_OOVH3      (0x1 <<  3) // (PWMC) Output Override Value for PWMH output of the channel 3\r
+#define AT91C_PWMC_OOVH4      (0x1 <<  4) // (PWMC) Output Override Value for PWMH output of the channel 4\r
+#define AT91C_PWMC_OOVH5      (0x1 <<  5) // (PWMC) Output Override Value for PWMH output of the channel 5\r
+#define AT91C_PWMC_OOVH6      (0x1 <<  6) // (PWMC) Output Override Value for PWMH output of the channel 6\r
+#define AT91C_PWMC_OOVH7      (0x1 <<  7) // (PWMC) Output Override Value for PWMH output of the channel 7\r
+#define AT91C_PWMC_OOVH8      (0x1 <<  8) // (PWMC) Output Override Value for PWMH output of the channel 8\r
+#define AT91C_PWMC_OOVH9      (0x1 <<  9) // (PWMC) Output Override Value for PWMH output of the channel 9\r
+#define AT91C_PWMC_OOVH10     (0x1 << 10) // (PWMC) Output Override Value for PWMH output of the channel 10\r
+#define AT91C_PWMC_OOVH11     (0x1 << 11) // (PWMC) Output Override Value for PWMH output of the channel 11\r
+#define AT91C_PWMC_OOVH12     (0x1 << 12) // (PWMC) Output Override Value for PWMH output of the channel 12\r
+#define AT91C_PWMC_OOVH13     (0x1 << 13) // (PWMC) Output Override Value for PWMH output of the channel 13\r
+#define AT91C_PWMC_OOVH14     (0x1 << 14) // (PWMC) Output Override Value for PWMH output of the channel 14\r
+#define AT91C_PWMC_OOVH15     (0x1 << 15) // (PWMC) Output Override Value for PWMH output of the channel 15\r
+#define AT91C_PWMC_OOVL0      (0x1 << 16) // (PWMC) Output Override Value for PWML output of the channel 0\r
+#define AT91C_PWMC_OOVL1      (0x1 << 17) // (PWMC) Output Override Value for PWML output of the channel 1\r
+#define AT91C_PWMC_OOVL2      (0x1 << 18) // (PWMC) Output Override Value for PWML output of the channel 2\r
+#define AT91C_PWMC_OOVL3      (0x1 << 19) // (PWMC) Output Override Value for PWML output of the channel 3\r
+#define AT91C_PWMC_OOVL4      (0x1 << 20) // (PWMC) Output Override Value for PWML output of the channel 4\r
+#define AT91C_PWMC_OOVL5      (0x1 << 21) // (PWMC) Output Override Value for PWML output of the channel 5\r
+#define AT91C_PWMC_OOVL6      (0x1 << 22) // (PWMC) Output Override Value for PWML output of the channel 6\r
+#define AT91C_PWMC_OOVL7      (0x1 << 23) // (PWMC) Output Override Value for PWML output of the channel 7\r
+#define AT91C_PWMC_OOVL8      (0x1 << 24) // (PWMC) Output Override Value for PWML output of the channel 8\r
+#define AT91C_PWMC_OOVL9      (0x1 << 25) // (PWMC) Output Override Value for PWML output of the channel 9\r
+#define AT91C_PWMC_OOVL10     (0x1 << 26) // (PWMC) Output Override Value for PWML output of the channel 10\r
+#define AT91C_PWMC_OOVL11     (0x1 << 27) // (PWMC) Output Override Value for PWML output of the channel 11\r
+#define AT91C_PWMC_OOVL12     (0x1 << 28) // (PWMC) Output Override Value for PWML output of the channel 12\r
+#define AT91C_PWMC_OOVL13     (0x1 << 29) // (PWMC) Output Override Value for PWML output of the channel 13\r
+#define AT91C_PWMC_OOVL14     (0x1 << 30) // (PWMC) Output Override Value for PWML output of the channel 14\r
+#define AT91C_PWMC_OOVL15     (0x1 << 31) // (PWMC) Output Override Value for PWML output of the channel 15\r
+// -------- PWMC_OS : (PWMC Offset: 0x48) PWM Output Selection Register -------- \r
+#define AT91C_PWMC_OSH0       (0x1 <<  0) // (PWMC) Output Selection for PWMH output of the channel 0\r
+#define AT91C_PWMC_OSH1       (0x1 <<  1) // (PWMC) Output Selection for PWMH output of the channel 1\r
+#define AT91C_PWMC_OSH2       (0x1 <<  2) // (PWMC) Output Selection for PWMH output of the channel 2\r
+#define AT91C_PWMC_OSH3       (0x1 <<  3) // (PWMC) Output Selection for PWMH output of the channel 3\r
+#define AT91C_PWMC_OSH4       (0x1 <<  4) // (PWMC) Output Selection for PWMH output of the channel 4\r
+#define AT91C_PWMC_OSH5       (0x1 <<  5) // (PWMC) Output Selection for PWMH output of the channel 5\r
+#define AT91C_PWMC_OSH6       (0x1 <<  6) // (PWMC) Output Selection for PWMH output of the channel 6\r
+#define AT91C_PWMC_OSH7       (0x1 <<  7) // (PWMC) Output Selection for PWMH output of the channel 7\r
+#define AT91C_PWMC_OSH8       (0x1 <<  8) // (PWMC) Output Selection for PWMH output of the channel 8\r
+#define AT91C_PWMC_OSH9       (0x1 <<  9) // (PWMC) Output Selection for PWMH output of the channel 9\r
+#define AT91C_PWMC_OSH10      (0x1 << 10) // (PWMC) Output Selection for PWMH output of the channel 10\r
+#define AT91C_PWMC_OSH11      (0x1 << 11) // (PWMC) Output Selection for PWMH output of the channel 11\r
+#define AT91C_PWMC_OSH12      (0x1 << 12) // (PWMC) Output Selection for PWMH output of the channel 12\r
+#define AT91C_PWMC_OSH13      (0x1 << 13) // (PWMC) Output Selection for PWMH output of the channel 13\r
+#define AT91C_PWMC_OSH14      (0x1 << 14) // (PWMC) Output Selection for PWMH output of the channel 14\r
+#define AT91C_PWMC_OSH15      (0x1 << 15) // (PWMC) Output Selection for PWMH output of the channel 15\r
+#define AT91C_PWMC_OSL0       (0x1 << 16) // (PWMC) Output Selection for PWML output of the channel 0\r
+#define AT91C_PWMC_OSL1       (0x1 << 17) // (PWMC) Output Selection for PWML output of the channel 1\r
+#define AT91C_PWMC_OSL2       (0x1 << 18) // (PWMC) Output Selection for PWML output of the channel 2\r
+#define AT91C_PWMC_OSL3       (0x1 << 19) // (PWMC) Output Selection for PWML output of the channel 3\r
+#define AT91C_PWMC_OSL4       (0x1 << 20) // (PWMC) Output Selection for PWML output of the channel 4\r
+#define AT91C_PWMC_OSL5       (0x1 << 21) // (PWMC) Output Selection for PWML output of the channel 5\r
+#define AT91C_PWMC_OSL6       (0x1 << 22) // (PWMC) Output Selection for PWML output of the channel 6\r
+#define AT91C_PWMC_OSL7       (0x1 << 23) // (PWMC) Output Selection for PWML output of the channel 7\r
+#define AT91C_PWMC_OSL8       (0x1 << 24) // (PWMC) Output Selection for PWML output of the channel 8\r
+#define AT91C_PWMC_OSL9       (0x1 << 25) // (PWMC) Output Selection for PWML output of the channel 9\r
+#define AT91C_PWMC_OSL10      (0x1 << 26) // (PWMC) Output Selection for PWML output of the channel 10\r
+#define AT91C_PWMC_OSL11      (0x1 << 27) // (PWMC) Output Selection for PWML output of the channel 11\r
+#define AT91C_PWMC_OSL12      (0x1 << 28) // (PWMC) Output Selection for PWML output of the channel 12\r
+#define AT91C_PWMC_OSL13      (0x1 << 29) // (PWMC) Output Selection for PWML output of the channel 13\r
+#define AT91C_PWMC_OSL14      (0x1 << 30) // (PWMC) Output Selection for PWML output of the channel 14\r
+#define AT91C_PWMC_OSL15      (0x1 << 31) // (PWMC) Output Selection for PWML output of the channel 15\r
+// -------- PWMC_OSS : (PWMC Offset: 0x4c) PWM Output Selection Set Register -------- \r
+#define AT91C_PWMC_OSSH0      (0x1 <<  0) // (PWMC) Output Selection Set for PWMH output of the channel 0\r
+#define AT91C_PWMC_OSSH1      (0x1 <<  1) // (PWMC) Output Selection Set for PWMH output of the channel 1\r
+#define AT91C_PWMC_OSSH2      (0x1 <<  2) // (PWMC) Output Selection Set for PWMH output of the channel 2\r
+#define AT91C_PWMC_OSSH3      (0x1 <<  3) // (PWMC) Output Selection Set for PWMH output of the channel 3\r
+#define AT91C_PWMC_OSSH4      (0x1 <<  4) // (PWMC) Output Selection Set for PWMH output of the channel 4\r
+#define AT91C_PWMC_OSSH5      (0x1 <<  5) // (PWMC) Output Selection Set for PWMH output of the channel 5\r
+#define AT91C_PWMC_OSSH6      (0x1 <<  6) // (PWMC) Output Selection Set for PWMH output of the channel 6\r
+#define AT91C_PWMC_OSSH7      (0x1 <<  7) // (PWMC) Output Selection Set for PWMH output of the channel 7\r
+#define AT91C_PWMC_OSSH8      (0x1 <<  8) // (PWMC) Output Selection Set for PWMH output of the channel 8\r
+#define AT91C_PWMC_OSSH9      (0x1 <<  9) // (PWMC) Output Selection Set for PWMH output of the channel 9\r
+#define AT91C_PWMC_OSSH10     (0x1 << 10) // (PWMC) Output Selection Set for PWMH output of the channel 10\r
+#define AT91C_PWMC_OSSH11     (0x1 << 11) // (PWMC) Output Selection Set for PWMH output of the channel 11\r
+#define AT91C_PWMC_OSSH12     (0x1 << 12) // (PWMC) Output Selection Set for PWMH output of the channel 12\r
+#define AT91C_PWMC_OSSH13     (0x1 << 13) // (PWMC) Output Selection Set for PWMH output of the channel 13\r
+#define AT91C_PWMC_OSSH14     (0x1 << 14) // (PWMC) Output Selection Set for PWMH output of the channel 14\r
+#define AT91C_PWMC_OSSH15     (0x1 << 15) // (PWMC) Output Selection Set for PWMH output of the channel 15\r
+#define AT91C_PWMC_OSSL0      (0x1 << 16) // (PWMC) Output Selection Set for PWML output of the channel 0\r
+#define AT91C_PWMC_OSSL1      (0x1 << 17) // (PWMC) Output Selection Set for PWML output of the channel 1\r
+#define AT91C_PWMC_OSSL2      (0x1 << 18) // (PWMC) Output Selection Set for PWML output of the channel 2\r
+#define AT91C_PWMC_OSSL3      (0x1 << 19) // (PWMC) Output Selection Set for PWML output of the channel 3\r
+#define AT91C_PWMC_OSSL4      (0x1 << 20) // (PWMC) Output Selection Set for PWML output of the channel 4\r
+#define AT91C_PWMC_OSSL5      (0x1 << 21) // (PWMC) Output Selection Set for PWML output of the channel 5\r
+#define AT91C_PWMC_OSSL6      (0x1 << 22) // (PWMC) Output Selection Set for PWML output of the channel 6\r
+#define AT91C_PWMC_OSSL7      (0x1 << 23) // (PWMC) Output Selection Set for PWML output of the channel 7\r
+#define AT91C_PWMC_OSSL8      (0x1 << 24) // (PWMC) Output Selection Set for PWML output of the channel 8\r
+#define AT91C_PWMC_OSSL9      (0x1 << 25) // (PWMC) Output Selection Set for PWML output of the channel 9\r
+#define AT91C_PWMC_OSSL10     (0x1 << 26) // (PWMC) Output Selection Set for PWML output of the channel 10\r
+#define AT91C_PWMC_OSSL11     (0x1 << 27) // (PWMC) Output Selection Set for PWML output of the channel 11\r
+#define AT91C_PWMC_OSSL12     (0x1 << 28) // (PWMC) Output Selection Set for PWML output of the channel 12\r
+#define AT91C_PWMC_OSSL13     (0x1 << 29) // (PWMC) Output Selection Set for PWML output of the channel 13\r
+#define AT91C_PWMC_OSSL14     (0x1 << 30) // (PWMC) Output Selection Set for PWML output of the channel 14\r
+#define AT91C_PWMC_OSSL15     (0x1 << 31) // (PWMC) Output Selection Set for PWML output of the channel 15\r
+// -------- PWMC_OSC : (PWMC Offset: 0x50) PWM Output Selection Clear Register -------- \r
+#define AT91C_PWMC_OSCH0      (0x1 <<  0) // (PWMC) Output Selection Clear for PWMH output of the channel 0\r
+#define AT91C_PWMC_OSCH1      (0x1 <<  1) // (PWMC) Output Selection Clear for PWMH output of the channel 1\r
+#define AT91C_PWMC_OSCH2      (0x1 <<  2) // (PWMC) Output Selection Clear for PWMH output of the channel 2\r
+#define AT91C_PWMC_OSCH3      (0x1 <<  3) // (PWMC) Output Selection Clear for PWMH output of the channel 3\r
+#define AT91C_PWMC_OSCH4      (0x1 <<  4) // (PWMC) Output Selection Clear for PWMH output of the channel 4\r
+#define AT91C_PWMC_OSCH5      (0x1 <<  5) // (PWMC) Output Selection Clear for PWMH output of the channel 5\r
+#define AT91C_PWMC_OSCH6      (0x1 <<  6) // (PWMC) Output Selection Clear for PWMH output of the channel 6\r
+#define AT91C_PWMC_OSCH7      (0x1 <<  7) // (PWMC) Output Selection Clear for PWMH output of the channel 7\r
+#define AT91C_PWMC_OSCH8      (0x1 <<  8) // (PWMC) Output Selection Clear for PWMH output of the channel 8\r
+#define AT91C_PWMC_OSCH9      (0x1 <<  9) // (PWMC) Output Selection Clear for PWMH output of the channel 9\r
+#define AT91C_PWMC_OSCH10     (0x1 << 10) // (PWMC) Output Selection Clear for PWMH output of the channel 10\r
+#define AT91C_PWMC_OSCH11     (0x1 << 11) // (PWMC) Output Selection Clear for PWMH output of the channel 11\r
+#define AT91C_PWMC_OSCH12     (0x1 << 12) // (PWMC) Output Selection Clear for PWMH output of the channel 12\r
+#define AT91C_PWMC_OSCH13     (0x1 << 13) // (PWMC) Output Selection Clear for PWMH output of the channel 13\r
+#define AT91C_PWMC_OSCH14     (0x1 << 14) // (PWMC) Output Selection Clear for PWMH output of the channel 14\r
+#define AT91C_PWMC_OSCH15     (0x1 << 15) // (PWMC) Output Selection Clear for PWMH output of the channel 15\r
+#define AT91C_PWMC_OSCL0      (0x1 << 16) // (PWMC) Output Selection Clear for PWML output of the channel 0\r
+#define AT91C_PWMC_OSCL1      (0x1 << 17) // (PWMC) Output Selection Clear for PWML output of the channel 1\r
+#define AT91C_PWMC_OSCL2      (0x1 << 18) // (PWMC) Output Selection Clear for PWML output of the channel 2\r
+#define AT91C_PWMC_OSCL3      (0x1 << 19) // (PWMC) Output Selection Clear for PWML output of the channel 3\r
+#define AT91C_PWMC_OSCL4      (0x1 << 20) // (PWMC) Output Selection Clear for PWML output of the channel 4\r
+#define AT91C_PWMC_OSCL5      (0x1 << 21) // (PWMC) Output Selection Clear for PWML output of the channel 5\r
+#define AT91C_PWMC_OSCL6      (0x1 << 22) // (PWMC) Output Selection Clear for PWML output of the channel 6\r
+#define AT91C_PWMC_OSCL7      (0x1 << 23) // (PWMC) Output Selection Clear for PWML output of the channel 7\r
+#define AT91C_PWMC_OSCL8      (0x1 << 24) // (PWMC) Output Selection Clear for PWML output of the channel 8\r
+#define AT91C_PWMC_OSCL9      (0x1 << 25) // (PWMC) Output Selection Clear for PWML output of the channel 9\r
+#define AT91C_PWMC_OSCL10     (0x1 << 26) // (PWMC) Output Selection Clear for PWML output of the channel 10\r
+#define AT91C_PWMC_OSCL11     (0x1 << 27) // (PWMC) Output Selection Clear for PWML output of the channel 11\r
+#define AT91C_PWMC_OSCL12     (0x1 << 28) // (PWMC) Output Selection Clear for PWML output of the channel 12\r
+#define AT91C_PWMC_OSCL13     (0x1 << 29) // (PWMC) Output Selection Clear for PWML output of the channel 13\r
+#define AT91C_PWMC_OSCL14     (0x1 << 30) // (PWMC) Output Selection Clear for PWML output of the channel 14\r
+#define AT91C_PWMC_OSCL15     (0x1 << 31) // (PWMC) Output Selection Clear for PWML output of the channel 15\r
+// -------- PWMC_OSSUPD : (PWMC Offset: 0x54) Output Selection Set for PWMH / PWML output of the channel x -------- \r
+#define AT91C_PWMC_OSSUPDH0   (0x1 <<  0) // (PWMC) Output Selection Set for PWMH output of the channel 0\r
+#define AT91C_PWMC_OSSUPDH1   (0x1 <<  1) // (PWMC) Output Selection Set for PWMH output of the channel 1\r
+#define AT91C_PWMC_OSSUPDH2   (0x1 <<  2) // (PWMC) Output Selection Set for PWMH output of the channel 2\r
+#define AT91C_PWMC_OSSUPDH3   (0x1 <<  3) // (PWMC) Output Selection Set for PWMH output of the channel 3\r
+#define AT91C_PWMC_OSSUPDH4   (0x1 <<  4) // (PWMC) Output Selection Set for PWMH output of the channel 4\r
+#define AT91C_PWMC_OSSUPDH5   (0x1 <<  5) // (PWMC) Output Selection Set for PWMH output of the channel 5\r
+#define AT91C_PWMC_OSSUPDH6   (0x1 <<  6) // (PWMC) Output Selection Set for PWMH output of the channel 6\r
+#define AT91C_PWMC_OSSUPDH7   (0x1 <<  7) // (PWMC) Output Selection Set for PWMH output of the channel 7\r
+#define AT91C_PWMC_OSSUPDH8   (0x1 <<  8) // (PWMC) Output Selection Set for PWMH output of the channel 8\r
+#define AT91C_PWMC_OSSUPDH9   (0x1 <<  9) // (PWMC) Output Selection Set for PWMH output of the channel 9\r
+#define AT91C_PWMC_OSSUPDH10  (0x1 << 10) // (PWMC) Output Selection Set for PWMH output of the channel 10\r
+#define AT91C_PWMC_OSSUPDH11  (0x1 << 11) // (PWMC) Output Selection Set for PWMH output of the channel 11\r
+#define AT91C_PWMC_OSSUPDH12  (0x1 << 12) // (PWMC) Output Selection Set for PWMH output of the channel 12\r
+#define AT91C_PWMC_OSSUPDH13  (0x1 << 13) // (PWMC) Output Selection Set for PWMH output of the channel 13\r
+#define AT91C_PWMC_OSSUPDH14  (0x1 << 14) // (PWMC) Output Selection Set for PWMH output of the channel 14\r
+#define AT91C_PWMC_OSSUPDH15  (0x1 << 15) // (PWMC) Output Selection Set for PWMH output of the channel 15\r
+#define AT91C_PWMC_OSSUPDL0   (0x1 << 16) // (PWMC) Output Selection Set for PWML output of the channel 0\r
+#define AT91C_PWMC_OSSUPDL1   (0x1 << 17) // (PWMC) Output Selection Set for PWML output of the channel 1\r
+#define AT91C_PWMC_OSSUPDL2   (0x1 << 18) // (PWMC) Output Selection Set for PWML output of the channel 2\r
+#define AT91C_PWMC_OSSUPDL3   (0x1 << 19) // (PWMC) Output Selection Set for PWML output of the channel 3\r
+#define AT91C_PWMC_OSSUPDL4   (0x1 << 20) // (PWMC) Output Selection Set for PWML output of the channel 4\r
+#define AT91C_PWMC_OSSUPDL5   (0x1 << 21) // (PWMC) Output Selection Set for PWML output of the channel 5\r
+#define AT91C_PWMC_OSSUPDL6   (0x1 << 22) // (PWMC) Output Selection Set for PWML output of the channel 6\r
+#define AT91C_PWMC_OSSUPDL7   (0x1 << 23) // (PWMC) Output Selection Set for PWML output of the channel 7\r
+#define AT91C_PWMC_OSSUPDL8   (0x1 << 24) // (PWMC) Output Selection Set for PWML output of the channel 8\r
+#define AT91C_PWMC_OSSUPDL9   (0x1 << 25) // (PWMC) Output Selection Set for PWML output of the channel 9\r
+#define AT91C_PWMC_OSSUPDL10  (0x1 << 26) // (PWMC) Output Selection Set for PWML output of the channel 10\r
+#define AT91C_PWMC_OSSUPDL11  (0x1 << 27) // (PWMC) Output Selection Set for PWML output of the channel 11\r
+#define AT91C_PWMC_OSSUPDL12  (0x1 << 28) // (PWMC) Output Selection Set for PWML output of the channel 12\r
+#define AT91C_PWMC_OSSUPDL13  (0x1 << 29) // (PWMC) Output Selection Set for PWML output of the channel 13\r
+#define AT91C_PWMC_OSSUPDL14  (0x1 << 30) // (PWMC) Output Selection Set for PWML output of the channel 14\r
+#define AT91C_PWMC_OSSUPDL15  (0x1 << 31) // (PWMC) Output Selection Set for PWML output of the channel 15\r
+// -------- PWMC_OSCUPD : (PWMC Offset: 0x58) Output Selection Clear for PWMH / PWML output of the channel x -------- \r
+#define AT91C_PWMC_OSCUPDH0   (0x1 <<  0) // (PWMC) Output Selection Clear for PWMH output of the channel 0\r
+#define AT91C_PWMC_OSCUPDH1   (0x1 <<  1) // (PWMC) Output Selection Clear for PWMH output of the channel 1\r
+#define AT91C_PWMC_OSCUPDH2   (0x1 <<  2) // (PWMC) Output Selection Clear for PWMH output of the channel 2\r
+#define AT91C_PWMC_OSCUPDH3   (0x1 <<  3) // (PWMC) Output Selection Clear for PWMH output of the channel 3\r
+#define AT91C_PWMC_OSCUPDH4   (0x1 <<  4) // (PWMC) Output Selection Clear for PWMH output of the channel 4\r
+#define AT91C_PWMC_OSCUPDH5   (0x1 <<  5) // (PWMC) Output Selection Clear for PWMH output of the channel 5\r
+#define AT91C_PWMC_OSCUPDH6   (0x1 <<  6) // (PWMC) Output Selection Clear for PWMH output of the channel 6\r
+#define AT91C_PWMC_OSCUPDH7   (0x1 <<  7) // (PWMC) Output Selection Clear for PWMH output of the channel 7\r
+#define AT91C_PWMC_OSCUPDH8   (0x1 <<  8) // (PWMC) Output Selection Clear for PWMH output of the channel 8\r
+#define AT91C_PWMC_OSCUPDH9   (0x1 <<  9) // (PWMC) Output Selection Clear for PWMH output of the channel 9\r
+#define AT91C_PWMC_OSCUPDH10  (0x1 << 10) // (PWMC) Output Selection Clear for PWMH output of the channel 10\r
+#define AT91C_PWMC_OSCUPDH11  (0x1 << 11) // (PWMC) Output Selection Clear for PWMH output of the channel 11\r
+#define AT91C_PWMC_OSCUPDH12  (0x1 << 12) // (PWMC) Output Selection Clear for PWMH output of the channel 12\r
+#define AT91C_PWMC_OSCUPDH13  (0x1 << 13) // (PWMC) Output Selection Clear for PWMH output of the channel 13\r
+#define AT91C_PWMC_OSCUPDH14  (0x1 << 14) // (PWMC) Output Selection Clear for PWMH output of the channel 14\r
+#define AT91C_PWMC_OSCUPDH15  (0x1 << 15) // (PWMC) Output Selection Clear for PWMH output of the channel 15\r
+#define AT91C_PWMC_OSCUPDL0   (0x1 << 16) // (PWMC) Output Selection Clear for PWML output of the channel 0\r
+#define AT91C_PWMC_OSCUPDL1   (0x1 << 17) // (PWMC) Output Selection Clear for PWML output of the channel 1\r
+#define AT91C_PWMC_OSCUPDL2   (0x1 << 18) // (PWMC) Output Selection Clear for PWML output of the channel 2\r
+#define AT91C_PWMC_OSCUPDL3   (0x1 << 19) // (PWMC) Output Selection Clear for PWML output of the channel 3\r
+#define AT91C_PWMC_OSCUPDL4   (0x1 << 20) // (PWMC) Output Selection Clear for PWML output of the channel 4\r
+#define AT91C_PWMC_OSCUPDL5   (0x1 << 21) // (PWMC) Output Selection Clear for PWML output of the channel 5\r
+#define AT91C_PWMC_OSCUPDL6   (0x1 << 22) // (PWMC) Output Selection Clear for PWML output of the channel 6\r
+#define AT91C_PWMC_OSCUPDL7   (0x1 << 23) // (PWMC) Output Selection Clear for PWML output of the channel 7\r
+#define AT91C_PWMC_OSCUPDL8   (0x1 << 24) // (PWMC) Output Selection Clear for PWML output of the channel 8\r
+#define AT91C_PWMC_OSCUPDL9   (0x1 << 25) // (PWMC) Output Selection Clear for PWML output of the channel 9\r
+#define AT91C_PWMC_OSCUPDL10  (0x1 << 26) // (PWMC) Output Selection Clear for PWML output of the channel 10\r
+#define AT91C_PWMC_OSCUPDL11  (0x1 << 27) // (PWMC) Output Selection Clear for PWML output of the channel 11\r
+#define AT91C_PWMC_OSCUPDL12  (0x1 << 28) // (PWMC) Output Selection Clear for PWML output of the channel 12\r
+#define AT91C_PWMC_OSCUPDL13  (0x1 << 29) // (PWMC) Output Selection Clear for PWML output of the channel 13\r
+#define AT91C_PWMC_OSCUPDL14  (0x1 << 30) // (PWMC) Output Selection Clear for PWML output of the channel 14\r
+#define AT91C_PWMC_OSCUPDL15  (0x1 << 31) // (PWMC) Output Selection Clear for PWML output of the channel 15\r
+// -------- PWMC_FMR : (PWMC Offset: 0x5c) PWM Fault Mode Register -------- \r
+#define AT91C_PWMC_FPOL0      (0x1 <<  0) // (PWMC) Fault Polarity on fault input 0\r
+#define AT91C_PWMC_FPOL1      (0x1 <<  1) // (PWMC) Fault Polarity on fault input 1\r
+#define AT91C_PWMC_FPOL2      (0x1 <<  2) // (PWMC) Fault Polarity on fault input 2\r
+#define AT91C_PWMC_FPOL3      (0x1 <<  3) // (PWMC) Fault Polarity on fault input 3\r
+#define AT91C_PWMC_FPOL4      (0x1 <<  4) // (PWMC) Fault Polarity on fault input 4\r
+#define AT91C_PWMC_FPOL5      (0x1 <<  5) // (PWMC) Fault Polarity on fault input 5\r
+#define AT91C_PWMC_FPOL6      (0x1 <<  6) // (PWMC) Fault Polarity on fault input 6\r
+#define AT91C_PWMC_FPOL7      (0x1 <<  7) // (PWMC) Fault Polarity on fault input 7\r
+#define AT91C_PWMC_FMOD0      (0x1 <<  8) // (PWMC) Fault Activation Mode on fault input 0\r
+#define AT91C_PWMC_FMOD1      (0x1 <<  9) // (PWMC) Fault Activation Mode on fault input 1\r
+#define AT91C_PWMC_FMOD2      (0x1 << 10) // (PWMC) Fault Activation Mode on fault input 2\r
+#define AT91C_PWMC_FMOD3      (0x1 << 11) // (PWMC) Fault Activation Mode on fault input 3\r
+#define AT91C_PWMC_FMOD4      (0x1 << 12) // (PWMC) Fault Activation Mode on fault input 4\r
+#define AT91C_PWMC_FMOD5      (0x1 << 13) // (PWMC) Fault Activation Mode on fault input 5\r
+#define AT91C_PWMC_FMOD6      (0x1 << 14) // (PWMC) Fault Activation Mode on fault input 6\r
+#define AT91C_PWMC_FMOD7      (0x1 << 15) // (PWMC) Fault Activation Mode on fault input 7\r
+#define AT91C_PWMC_FFIL00     (0x1 << 16) // (PWMC) Fault Filtering on fault input 0\r
+#define AT91C_PWMC_FFIL01     (0x1 << 17) // (PWMC) Fault Filtering on fault input 1\r
+#define AT91C_PWMC_FFIL02     (0x1 << 18) // (PWMC) Fault Filtering on fault input 2\r
+#define AT91C_PWMC_FFIL03     (0x1 << 19) // (PWMC) Fault Filtering on fault input 3\r
+#define AT91C_PWMC_FFIL04     (0x1 << 20) // (PWMC) Fault Filtering on fault input 4\r
+#define AT91C_PWMC_FFIL05     (0x1 << 21) // (PWMC) Fault Filtering on fault input 5\r
+#define AT91C_PWMC_FFIL06     (0x1 << 22) // (PWMC) Fault Filtering on fault input 6\r
+#define AT91C_PWMC_FFIL07     (0x1 << 23) // (PWMC) Fault Filtering on fault input 7\r
+// -------- PWMC_FSR : (PWMC Offset: 0x60) Fault Input x Value -------- \r
+#define AT91C_PWMC_FIV0       (0x1 <<  0) // (PWMC) Fault Input 0 Value\r
+#define AT91C_PWMC_FIV1       (0x1 <<  1) // (PWMC) Fault Input 1 Value\r
+#define AT91C_PWMC_FIV2       (0x1 <<  2) // (PWMC) Fault Input 2 Value\r
+#define AT91C_PWMC_FIV3       (0x1 <<  3) // (PWMC) Fault Input 3 Value\r
+#define AT91C_PWMC_FIV4       (0x1 <<  4) // (PWMC) Fault Input 4 Value\r
+#define AT91C_PWMC_FIV5       (0x1 <<  5) // (PWMC) Fault Input 5 Value\r
+#define AT91C_PWMC_FIV6       (0x1 <<  6) // (PWMC) Fault Input 6 Value\r
+#define AT91C_PWMC_FIV7       (0x1 <<  7) // (PWMC) Fault Input 7 Value\r
+#define AT91C_PWMC_FS0        (0x1 <<  8) // (PWMC) Fault 0 Status\r
+#define AT91C_PWMC_FS1        (0x1 <<  9) // (PWMC) Fault 1 Status\r
+#define AT91C_PWMC_FS2        (0x1 << 10) // (PWMC) Fault 2 Status\r
+#define AT91C_PWMC_FS3        (0x1 << 11) // (PWMC) Fault 3 Status\r
+#define AT91C_PWMC_FS4        (0x1 << 12) // (PWMC) Fault 4 Status\r
+#define AT91C_PWMC_FS5        (0x1 << 13) // (PWMC) Fault 5 Status\r
+#define AT91C_PWMC_FS6        (0x1 << 14) // (PWMC) Fault 6 Status\r
+#define AT91C_PWMC_FS7        (0x1 << 15) // (PWMC) Fault 7 Status\r
+// -------- PWMC_FCR : (PWMC Offset: 0x64) Fault y Clear -------- \r
+#define AT91C_PWMC_FCLR0      (0x1 <<  0) // (PWMC) Fault 0 Clear\r
+#define AT91C_PWMC_FCLR1      (0x1 <<  1) // (PWMC) Fault 1 Clear\r
+#define AT91C_PWMC_FCLR2      (0x1 <<  2) // (PWMC) Fault 2 Clear\r
+#define AT91C_PWMC_FCLR3      (0x1 <<  3) // (PWMC) Fault 3 Clear\r
+#define AT91C_PWMC_FCLR4      (0x1 <<  4) // (PWMC) Fault 4 Clear\r
+#define AT91C_PWMC_FCLR5      (0x1 <<  5) // (PWMC) Fault 5 Clear\r
+#define AT91C_PWMC_FCLR6      (0x1 <<  6) // (PWMC) Fault 6 Clear\r
+#define AT91C_PWMC_FCLR7      (0x1 <<  7) // (PWMC) Fault 7 Clear\r
+// -------- PWMC_FPV : (PWMC Offset: 0x68) PWM Fault Protection Value -------- \r
+#define AT91C_PWMC_FPVH0      (0x1 <<  0) // (PWMC) Fault Protection Value for PWMH output on channel 0\r
+#define AT91C_PWMC_FPVH1      (0x1 <<  1) // (PWMC) Fault Protection Value for PWMH output on channel 1\r
+#define AT91C_PWMC_FPVH2      (0x1 <<  2) // (PWMC) Fault Protection Value for PWMH output on channel 2\r
+#define AT91C_PWMC_FPVH3      (0x1 <<  3) // (PWMC) Fault Protection Value for PWMH output on channel 3\r
+#define AT91C_PWMC_FPVH4      (0x1 <<  4) // (PWMC) Fault Protection Value for PWMH output on channel 4\r
+#define AT91C_PWMC_FPVH5      (0x1 <<  5) // (PWMC) Fault Protection Value for PWMH output on channel 5\r
+#define AT91C_PWMC_FPVH6      (0x1 <<  6) // (PWMC) Fault Protection Value for PWMH output on channel 6\r
+#define AT91C_PWMC_FPVH7      (0x1 <<  7) // (PWMC) Fault Protection Value for PWMH output on channel 7\r
+#define AT91C_PWMC_FPVL0      (0x1 << 16) // (PWMC) Fault Protection Value for PWML output on channel 0\r
+#define AT91C_PWMC_FPVL1      (0x1 << 17) // (PWMC) Fault Protection Value for PWML output on channel 1\r
+#define AT91C_PWMC_FPVL2      (0x1 << 18) // (PWMC) Fault Protection Value for PWML output on channel 2\r
+#define AT91C_PWMC_FPVL3      (0x1 << 19) // (PWMC) Fault Protection Value for PWML output on channel 3\r
+#define AT91C_PWMC_FPVL4      (0x1 << 20) // (PWMC) Fault Protection Value for PWML output on channel 4\r
+#define AT91C_PWMC_FPVL5      (0x1 << 21) // (PWMC) Fault Protection Value for PWML output on channel 5\r
+#define AT91C_PWMC_FPVL6      (0x1 << 22) // (PWMC) Fault Protection Value for PWML output on channel 6\r
+#define AT91C_PWMC_FPVL7      (0x1 << 23) // (PWMC) Fault Protection Value for PWML output on channel 7\r
+// -------- PWMC_FPER1 : (PWMC Offset: 0x6c) PWM Fault Protection Enable Register 1 -------- \r
+#define AT91C_PWMC_FPE0       (0xFF <<  0) // (PWMC) Fault Protection Enable with Fault Input y for PWM channel 0\r
+#define AT91C_PWMC_FPE1       (0xFF <<  8) // (PWMC) Fault Protection Enable with Fault Input y for PWM channel 1\r
+#define AT91C_PWMC_FPE2       (0xFF << 16) // (PWMC) Fault Protection Enable with Fault Input y for PWM channel 2\r
+#define AT91C_PWMC_FPE3       (0xFF << 24) // (PWMC) Fault Protection Enable with Fault Input y for PWM channel 3\r
+// -------- PWMC_FPER2 : (PWMC Offset: 0x70) PWM Fault Protection Enable Register 2 -------- \r
+#define AT91C_PWMC_FPE4       (0xFF <<  0) // (PWMC) Fault Protection Enable with Fault Input y for PWM channel 4\r
+#define AT91C_PWMC_FPE5       (0xFF <<  8) // (PWMC) Fault Protection Enable with Fault Input y for PWM channel 5\r
+#define AT91C_PWMC_FPE6       (0xFF << 16) // (PWMC) Fault Protection Enable with Fault Input y for PWM channel 6\r
+#define AT91C_PWMC_FPE7       (0xFF << 24) // (PWMC) Fault Protection Enable with Fault Input y for PWM channel 7\r
+// -------- PWMC_FPER3 : (PWMC Offset: 0x74) PWM Fault Protection Enable Register 3 -------- \r
+#define AT91C_PWMC_FPE8       (0xFF <<  0) // (PWMC) Fault Protection Enable with Fault Input y for PWM channel 8\r
+#define AT91C_PWMC_FPE9       (0xFF <<  8) // (PWMC) Fault Protection Enable with Fault Input y for PWM channel 9\r
+#define AT91C_PWMC_FPE10      (0xFF << 16) // (PWMC) Fault Protection Enable with Fault Input y for PWM channel 10\r
+#define AT91C_PWMC_FPE11      (0xFF << 24) // (PWMC) Fault Protection Enable with Fault Input y for PWM channel 11\r
+// -------- PWMC_FPER4 : (PWMC Offset: 0x78) PWM Fault Protection Enable Register 4 -------- \r
+#define AT91C_PWMC_FPE12      (0xFF <<  0) // (PWMC) Fault Protection Enable with Fault Input y for PWM channel 12\r
+#define AT91C_PWMC_FPE13      (0xFF <<  8) // (PWMC) Fault Protection Enable with Fault Input y for PWM channel 13\r
+#define AT91C_PWMC_FPE14      (0xFF << 16) // (PWMC) Fault Protection Enable with Fault Input y for PWM channel 14\r
+#define AT91C_PWMC_FPE15      (0xFF << 24) // (PWMC) Fault Protection Enable with Fault Input y for PWM channel 15\r
+// -------- PWMC_EL0MR : (PWMC Offset: 0x7c) PWM Event Line 0 Mode Register -------- \r
+#define AT91C_PWMC_L0CSEL0    (0x1 <<  0) // (PWMC) Comparison 0 Selection\r
+#define AT91C_PWMC_L0CSEL1    (0x1 <<  1) // (PWMC) Comparison 1 Selection\r
+#define AT91C_PWMC_L0CSEL2    (0x1 <<  2) // (PWMC) Comparison 2 Selection\r
+#define AT91C_PWMC_L0CSEL3    (0x1 <<  3) // (PWMC) Comparison 3 Selection\r
+#define AT91C_PWMC_L0CSEL4    (0x1 <<  4) // (PWMC) Comparison 4 Selection\r
+#define AT91C_PWMC_L0CSEL5    (0x1 <<  5) // (PWMC) Comparison 5 Selection\r
+#define AT91C_PWMC_L0CSEL6    (0x1 <<  6) // (PWMC) Comparison 6 Selection\r
+#define AT91C_PWMC_L0CSEL7    (0x1 <<  7) // (PWMC) Comparison 7 Selection\r
+// -------- PWMC_EL1MR : (PWMC Offset: 0x80) PWM Event Line 1 Mode Register -------- \r
+#define AT91C_PWMC_L1CSEL0    (0x1 <<  0) // (PWMC) Comparison 0 Selection\r
+#define AT91C_PWMC_L1CSEL1    (0x1 <<  1) // (PWMC) Comparison 1 Selection\r
+#define AT91C_PWMC_L1CSEL2    (0x1 <<  2) // (PWMC) Comparison 2 Selection\r
+#define AT91C_PWMC_L1CSEL3    (0x1 <<  3) // (PWMC) Comparison 3 Selection\r
+#define AT91C_PWMC_L1CSEL4    (0x1 <<  4) // (PWMC) Comparison 4 Selection\r
+#define AT91C_PWMC_L1CSEL5    (0x1 <<  5) // (PWMC) Comparison 5 Selection\r
+#define AT91C_PWMC_L1CSEL6    (0x1 <<  6) // (PWMC) Comparison 6 Selection\r
+#define AT91C_PWMC_L1CSEL7    (0x1 <<  7) // (PWMC) Comparison 7 Selection\r
+// -------- PWMC_EL2MR : (PWMC Offset: 0x84) PWM Event line 2 Mode Register -------- \r
+#define AT91C_PWMC_L2CSEL0    (0x1 <<  0) // (PWMC) Comparison 0 Selection\r
+#define AT91C_PWMC_L2CSEL1    (0x1 <<  1) // (PWMC) Comparison 1 Selection\r
+#define AT91C_PWMC_L2CSEL2    (0x1 <<  2) // (PWMC) Comparison 2 Selection\r
+#define AT91C_PWMC_L2CSEL3    (0x1 <<  3) // (PWMC) Comparison 3 Selection\r
+#define AT91C_PWMC_L2CSEL4    (0x1 <<  4) // (PWMC) Comparison 4 Selection\r
+#define AT91C_PWMC_L2CSEL5    (0x1 <<  5) // (PWMC) Comparison 5 Selection\r
+#define AT91C_PWMC_L2CSEL6    (0x1 <<  6) // (PWMC) Comparison 6 Selection\r
+#define AT91C_PWMC_L2CSEL7    (0x1 <<  7) // (PWMC) Comparison 7 Selection\r
+// -------- PWMC_EL3MR : (PWMC Offset: 0x88) PWM Event line 3 Mode Register -------- \r
+#define AT91C_PWMC_L3CSEL0    (0x1 <<  0) // (PWMC) Comparison 0 Selection\r
+#define AT91C_PWMC_L3CSEL1    (0x1 <<  1) // (PWMC) Comparison 1 Selection\r
+#define AT91C_PWMC_L3CSEL2    (0x1 <<  2) // (PWMC) Comparison 2 Selection\r
+#define AT91C_PWMC_L3CSEL3    (0x1 <<  3) // (PWMC) Comparison 3 Selection\r
+#define AT91C_PWMC_L3CSEL4    (0x1 <<  4) // (PWMC) Comparison 4 Selection\r
+#define AT91C_PWMC_L3CSEL5    (0x1 <<  5) // (PWMC) Comparison 5 Selection\r
+#define AT91C_PWMC_L3CSEL6    (0x1 <<  6) // (PWMC) Comparison 6 Selection\r
+#define AT91C_PWMC_L3CSEL7    (0x1 <<  7) // (PWMC) Comparison 7 Selection\r
+// -------- PWMC_EL4MR : (PWMC Offset: 0x8c) PWM Event line 4 Mode Register -------- \r
+#define AT91C_PWMC_L4CSEL0    (0x1 <<  0) // (PWMC) Comparison 0 Selection\r
+#define AT91C_PWMC_L4CSEL1    (0x1 <<  1) // (PWMC) Comparison 1 Selection\r
+#define AT91C_PWMC_L4CSEL2    (0x1 <<  2) // (PWMC) Comparison 2 Selection\r
+#define AT91C_PWMC_L4CSEL3    (0x1 <<  3) // (PWMC) Comparison 3 Selection\r
+#define AT91C_PWMC_L4CSEL4    (0x1 <<  4) // (PWMC) Comparison 4 Selection\r
+#define AT91C_PWMC_L4CSEL5    (0x1 <<  5) // (PWMC) Comparison 5 Selection\r
+#define AT91C_PWMC_L4CSEL6    (0x1 <<  6) // (PWMC) Comparison 6 Selection\r
+#define AT91C_PWMC_L4CSEL7    (0x1 <<  7) // (PWMC) Comparison 7 Selection\r
+// -------- PWMC_EL5MR : (PWMC Offset: 0x90) PWM Event line 5 Mode Register -------- \r
+#define AT91C_PWMC_L5CSEL0    (0x1 <<  0) // (PWMC) Comparison 0 Selection\r
+#define AT91C_PWMC_L5CSEL1    (0x1 <<  1) // (PWMC) Comparison 1 Selection\r
+#define AT91C_PWMC_L5CSEL2    (0x1 <<  2) // (PWMC) Comparison 2 Selection\r
+#define AT91C_PWMC_L5CSEL3    (0x1 <<  3) // (PWMC) Comparison 3 Selection\r
+#define AT91C_PWMC_L5CSEL4    (0x1 <<  4) // (PWMC) Comparison 4 Selection\r
+#define AT91C_PWMC_L5CSEL5    (0x1 <<  5) // (PWMC) Comparison 5 Selection\r
+#define AT91C_PWMC_L5CSEL6    (0x1 <<  6) // (PWMC) Comparison 6 Selection\r
+#define AT91C_PWMC_L5CSEL7    (0x1 <<  7) // (PWMC) Comparison 7 Selection\r
+// -------- PWMC_EL6MR : (PWMC Offset: 0x94) PWM Event line 6 Mode Register -------- \r
+#define AT91C_PWMC_L6CSEL0    (0x1 <<  0) // (PWMC) Comparison 0 Selection\r
+#define AT91C_PWMC_L6CSEL1    (0x1 <<  1) // (PWMC) Comparison 1 Selection\r
+#define AT91C_PWMC_L6CSEL2    (0x1 <<  2) // (PWMC) Comparison 2 Selection\r
+#define AT91C_PWMC_L6CSEL3    (0x1 <<  3) // (PWMC) Comparison 3 Selection\r
+#define AT91C_PWMC_L6CSEL4    (0x1 <<  4) // (PWMC) Comparison 4 Selection\r
+#define AT91C_PWMC_L6CSEL5    (0x1 <<  5) // (PWMC) Comparison 5 Selection\r
+#define AT91C_PWMC_L6CSEL6    (0x1 <<  6) // (PWMC) Comparison 6 Selection\r
+#define AT91C_PWMC_L6CSEL7    (0x1 <<  7) // (PWMC) Comparison 7 Selection\r
+// -------- PWMC_EL7MR : (PWMC Offset: 0x98) PWM Event line 7 Mode Register -------- \r
+#define AT91C_PWMC_L7CSEL0    (0x1 <<  0) // (PWMC) Comparison 0 Selection\r
+#define AT91C_PWMC_L7CSEL1    (0x1 <<  1) // (PWMC) Comparison 1 Selection\r
+#define AT91C_PWMC_L7CSEL2    (0x1 <<  2) // (PWMC) Comparison 2 Selection\r
+#define AT91C_PWMC_L7CSEL3    (0x1 <<  3) // (PWMC) Comparison 3 Selection\r
+#define AT91C_PWMC_L7CSEL4    (0x1 <<  4) // (PWMC) Comparison 4 Selection\r
+#define AT91C_PWMC_L7CSEL5    (0x1 <<  5) // (PWMC) Comparison 5 Selection\r
+#define AT91C_PWMC_L7CSEL6    (0x1 <<  6) // (PWMC) Comparison 6 Selection\r
+#define AT91C_PWMC_L7CSEL7    (0x1 <<  7) // (PWMC) Comparison 7 Selection\r
+// -------- PWMC_WPCR : (PWMC Offset: 0xe4) PWM Write Protection Control Register -------- \r
+#define AT91C_PWMC_WPCMD      (0x3 <<  0) // (PWMC) Write Protection Command\r
+#define AT91C_PWMC_WPRG0      (0x1 <<  2) // (PWMC) Write Protect Register Group 0\r
+#define AT91C_PWMC_WPRG1      (0x1 <<  3) // (PWMC) Write Protect Register Group 1\r
+#define AT91C_PWMC_WPRG2      (0x1 <<  4) // (PWMC) Write Protect Register Group 2\r
+#define AT91C_PWMC_WPRG3      (0x1 <<  5) // (PWMC) Write Protect Register Group 3\r
+#define AT91C_PWMC_WPRG4      (0x1 <<  6) // (PWMC) Write Protect Register Group 4\r
+#define AT91C_PWMC_WPRG5      (0x1 <<  7) // (PWMC) Write Protect Register Group 5\r
+#define AT91C_PWMC_WPKEY      (0xFFFFFF <<  8) // (PWMC) Protection Password\r
+// -------- PWMC_WPVS : (PWMC Offset: 0xe8) Write Protection Status Register -------- \r
+#define AT91C_PWMC_WPSWS0     (0x1 <<  0) // (PWMC) Write Protect SW Group 0 Status \r
+#define AT91C_PWMC_WPSWS1     (0x1 <<  1) // (PWMC) Write Protect SW Group 1 Status \r
+#define AT91C_PWMC_WPSWS2     (0x1 <<  2) // (PWMC) Write Protect SW Group 2 Status \r
+#define AT91C_PWMC_WPSWS3     (0x1 <<  3) // (PWMC) Write Protect SW Group 3 Status \r
+#define AT91C_PWMC_WPSWS4     (0x1 <<  4) // (PWMC) Write Protect SW Group 4 Status \r
+#define AT91C_PWMC_WPSWS5     (0x1 <<  5) // (PWMC) Write Protect SW Group 5 Status \r
+#define AT91C_PWMC_WPVS       (0x1 <<  7) // (PWMC) Write Protection Enable\r
+#define AT91C_PWMC_WPHWS0     (0x1 <<  8) // (PWMC) Write Protect HW Group 0 Status \r
+#define AT91C_PWMC_WPHWS1     (0x1 <<  9) // (PWMC) Write Protect HW Group 1 Status \r
+#define AT91C_PWMC_WPHWS2     (0x1 << 10) // (PWMC) Write Protect HW Group 2 Status \r
+#define AT91C_PWMC_WPHWS3     (0x1 << 11) // (PWMC) Write Protect HW Group 3 Status \r
+#define AT91C_PWMC_WPHWS4     (0x1 << 12) // (PWMC) Write Protect HW Group 4 Status \r
+#define AT91C_PWMC_WPHWS5     (0x1 << 13) // (PWMC) Write Protect HW Group 5 Status \r
+#define AT91C_PWMC_WPVSRC     (0xFFFF << 16) // (PWMC) Write Protection Violation Source\r
+// -------- PWMC_CMP0V : (PWMC Offset: 0x130) PWM Comparison Value 0 Register -------- \r
+#define AT91C_PWMC_CV         (0xFFFFFF <<  0) // (PWMC) PWM Comparison Value 0.\r
+#define AT91C_PWMC_CVM        (0x1 << 24) // (PWMC) Comparison Value 0 Mode.\r
+// -------- PWMC_CMP0VUPD : (PWMC Offset: 0x134) PWM Comparison Value 0 Update Register -------- \r
+#define AT91C_PWMC_CVUPD      (0xFFFFFF <<  0) // (PWMC) PWM Comparison Value Update.\r
+#define AT91C_PWMC_CVMUPD     (0x1 << 24) // (PWMC) Comparison Value Update Mode.\r
+// -------- PWMC_CMP0M : (PWMC Offset: 0x138) PWM Comparison 0 Mode Register -------- \r
+#define AT91C_PWMC_CEN        (0x1 <<  0) // (PWMC) Comparison Enable.\r
+#define AT91C_PWMC_CTR        (0xF <<  4) // (PWMC) PWM Comparison Trigger.\r
+#define AT91C_PWMC_CPR        (0xF <<  8) // (PWMC) PWM Comparison Period.\r
+#define AT91C_PWMC_CPRCNT     (0xF << 12) // (PWMC) PWM Comparison Period Counter.\r
+#define AT91C_PWMC_CUPR       (0xF << 16) // (PWMC) PWM Comparison Update Period.\r
+#define AT91C_PWMC_CUPRCNT    (0xF << 20) // (PWMC) PWM Comparison Update Period Counter.\r
+// -------- PWMC_CMP0MUPD : (PWMC Offset: 0x13c) PWM Comparison 0 Mode Update Register -------- \r
+#define AT91C_PWMC_CENUPD     (0x1 <<  0) // (PWMC) Comparison Enable Update.\r
+#define AT91C_PWMC_CTRUPD     (0xF <<  4) // (PWMC) PWM Comparison Trigger Update.\r
+#define AT91C_PWMC_CPRUPD     (0xF <<  8) // (PWMC) PWM Comparison Period Update.\r
+#define AT91C_PWMC_CUPRUPD    (0xF << 16) // (PWMC) PWM Comparison Update Period Update.\r
+// -------- PWMC_CMP1V : (PWMC Offset: 0x140) PWM Comparison Value 1 Register -------- \r
+// -------- PWMC_CMP1VUPD : (PWMC Offset: 0x144) PWM Comparison Value 1 Update Register -------- \r
+// -------- PWMC_CMP1M : (PWMC Offset: 0x148) PWM Comparison 1 Mode Register -------- \r
+// -------- PWMC_CMP1MUPD : (PWMC Offset: 0x14c) PWM Comparison 1 Mode Update Register -------- \r
+// -------- PWMC_CMP2V : (PWMC Offset: 0x150) PWM Comparison Value 2 Register -------- \r
+// -------- PWMC_CMP2VUPD : (PWMC Offset: 0x154) PWM Comparison Value 2 Update Register -------- \r
+// -------- PWMC_CMP2M : (PWMC Offset: 0x158) PWM Comparison 2 Mode Register -------- \r
+// -------- PWMC_CMP2MUPD : (PWMC Offset: 0x15c) PWM Comparison 2 Mode Update Register -------- \r
+// -------- PWMC_CMP3V : (PWMC Offset: 0x160) PWM Comparison Value 3 Register -------- \r
+// -------- PWMC_CMP3VUPD : (PWMC Offset: 0x164) PWM Comparison Value 3 Update Register -------- \r
+// -------- PWMC_CMP3M : (PWMC Offset: 0x168) PWM Comparison 3 Mode Register -------- \r
+// -------- PWMC_CMP3MUPD : (PWMC Offset: 0x16c) PWM Comparison 3 Mode Update Register -------- \r
+// -------- PWMC_CMP4V : (PWMC Offset: 0x170) PWM Comparison Value 4 Register -------- \r
+// -------- PWMC_CMP4VUPD : (PWMC Offset: 0x174) PWM Comparison Value 4 Update Register -------- \r
+// -------- PWMC_CMP4M : (PWMC Offset: 0x178) PWM Comparison 4 Mode Register -------- \r
+// -------- PWMC_CMP4MUPD : (PWMC Offset: 0x17c) PWM Comparison 4 Mode Update Register -------- \r
+// -------- PWMC_CMP5V : (PWMC Offset: 0x180) PWM Comparison Value 5 Register -------- \r
+// -------- PWMC_CMP5VUPD : (PWMC Offset: 0x184) PWM Comparison Value 5 Update Register -------- \r
+// -------- PWMC_CMP5M : (PWMC Offset: 0x188) PWM Comparison 5 Mode Register -------- \r
+// -------- PWMC_CMP5MUPD : (PWMC Offset: 0x18c) PWM Comparison 5 Mode Update Register -------- \r
+// -------- PWMC_CMP6V : (PWMC Offset: 0x190) PWM Comparison Value 6 Register -------- \r
+// -------- PWMC_CMP6VUPD : (PWMC Offset: 0x194) PWM Comparison Value 6 Update Register -------- \r
+// -------- PWMC_CMP6M : (PWMC Offset: 0x198) PWM Comparison 6 Mode Register -------- \r
+// -------- PWMC_CMP6MUPD : (PWMC Offset: 0x19c) PWM Comparison 6 Mode Update Register -------- \r
+// -------- PWMC_CMP7V : (PWMC Offset: 0x1a0) PWM Comparison Value 7 Register -------- \r
+// -------- PWMC_CMP7VUPD : (PWMC Offset: 0x1a4) PWM Comparison Value 7 Update Register -------- \r
+// -------- PWMC_CMP7M : (PWMC Offset: 0x1a8) PWM Comparison 7 Mode Register -------- \r
+// -------- PWMC_CMP7MUPD : (PWMC Offset: 0x1ac) PWM Comparison 7 Mode Update Register -------- \r
+\r
+// *****************************************************************************\r
+//              SOFTWARE API DEFINITION  FOR Serial Parallel Interface\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_SPI {\r
+       AT91_REG         SPI_CR;        // Control Register\r
+       AT91_REG         SPI_MR;        // Mode Register\r
+       AT91_REG         SPI_RDR;       // Receive Data Register\r
+       AT91_REG         SPI_TDR;       // Transmit Data Register\r
+       AT91_REG         SPI_SR;        // Status Register\r
+       AT91_REG         SPI_IER;       // Interrupt Enable Register\r
+       AT91_REG         SPI_IDR;       // Interrupt Disable Register\r
+       AT91_REG         SPI_IMR;       // Interrupt Mask Register\r
+       AT91_REG         Reserved0[4];  // \r
+       AT91_REG         SPI_CSR[4];    // Chip Select Register\r
+       AT91_REG         Reserved1[43];         // \r
+       AT91_REG         SPI_ADDRSIZE;  // SPI ADDRSIZE REGISTER \r
+       AT91_REG         SPI_IPNAME1;   // SPI IPNAME1 REGISTER \r
+       AT91_REG         SPI_IPNAME2;   // SPI IPNAME2 REGISTER \r
+       AT91_REG         SPI_FEATURES;  // SPI FEATURES REGISTER \r
+       AT91_REG         SPI_VER;       // Version Register\r
+       AT91_REG         SPI_RPR;       // Receive Pointer Register\r
+       AT91_REG         SPI_RCR;       // Receive Counter Register\r
+       AT91_REG         SPI_TPR;       // Transmit Pointer Register\r
+       AT91_REG         SPI_TCR;       // Transmit Counter Register\r
+       AT91_REG         SPI_RNPR;      // Receive Next Pointer Register\r
+       AT91_REG         SPI_RNCR;      // Receive Next Counter Register\r
+       AT91_REG         SPI_TNPR;      // Transmit Next Pointer Register\r
+       AT91_REG         SPI_TNCR;      // Transmit Next Counter Register\r
+       AT91_REG         SPI_PTCR;      // PDC Transfer Control Register\r
+       AT91_REG         SPI_PTSR;      // PDC Transfer Status Register\r
+} AT91S_SPI, *AT91PS_SPI;\r
+#else\r
+#define SPI_CR          (AT91_CAST(AT91_REG *)         0x00000000) // (SPI_CR) Control Register\r
+#define SPI_MR          (AT91_CAST(AT91_REG *)         0x00000004) // (SPI_MR) Mode Register\r
+#define SPI_RDR         (AT91_CAST(AT91_REG *)         0x00000008) // (SPI_RDR) Receive Data Register\r
+#define SPI_TDR         (AT91_CAST(AT91_REG *)         0x0000000C) // (SPI_TDR) Transmit Data Register\r
+#define SPI_SR          (AT91_CAST(AT91_REG *)         0x00000010) // (SPI_SR) Status Register\r
+#define SPI_IER         (AT91_CAST(AT91_REG *)         0x00000014) // (SPI_IER) Interrupt Enable Register\r
+#define SPI_IDR         (AT91_CAST(AT91_REG *)         0x00000018) // (SPI_IDR) Interrupt Disable Register\r
+#define SPI_IMR         (AT91_CAST(AT91_REG *)         0x0000001C) // (SPI_IMR) Interrupt Mask Register\r
+#define SPI_CSR         (AT91_CAST(AT91_REG *)         0x00000030) // (SPI_CSR) Chip Select Register\r
+#define SPI_ADDRSIZE    (AT91_CAST(AT91_REG *)         0x000000EC) // (SPI_ADDRSIZE) SPI ADDRSIZE REGISTER \r
+#define SPI_IPNAME1     (AT91_CAST(AT91_REG *)         0x000000F0) // (SPI_IPNAME1) SPI IPNAME1 REGISTER \r
+#define SPI_IPNAME2     (AT91_CAST(AT91_REG *)         0x000000F4) // (SPI_IPNAME2) SPI IPNAME2 REGISTER \r
+#define SPI_FEATURES    (AT91_CAST(AT91_REG *)         0x000000F8) // (SPI_FEATURES) SPI FEATURES REGISTER \r
+#define SPI_VER         (AT91_CAST(AT91_REG *)         0x000000FC) // (SPI_VER) Version Register\r
+\r
+#endif\r
+// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- \r
+#define AT91C_SPI_SPIEN       (0x1 <<  0) // (SPI) SPI Enable\r
+#define AT91C_SPI_SPIDIS      (0x1 <<  1) // (SPI) SPI Disable\r
+#define AT91C_SPI_SWRST       (0x1 <<  7) // (SPI) SPI Software reset\r
+#define AT91C_SPI_LASTXFER    (0x1 << 24) // (SPI) SPI Last Transfer\r
+// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- \r
+#define AT91C_SPI_MSTR        (0x1 <<  0) // (SPI) Master/Slave Mode\r
+#define AT91C_SPI_PS          (0x1 <<  1) // (SPI) Peripheral Select\r
+#define        AT91C_SPI_PS_FIXED                (0x0 <<  1) // (SPI) Fixed Peripheral Select\r
+#define        AT91C_SPI_PS_VARIABLE             (0x1 <<  1) // (SPI) Variable Peripheral Select\r
+#define AT91C_SPI_PCSDEC      (0x1 <<  2) // (SPI) Chip Select Decode\r
+#define AT91C_SPI_FDIV        (0x1 <<  3) // (SPI) Clock Selection\r
+#define AT91C_SPI_MODFDIS     (0x1 <<  4) // (SPI) Mode Fault Detection\r
+#define AT91C_SPI_LLB         (0x1 <<  7) // (SPI) Clock Selection\r
+#define AT91C_SPI_PCS         (0xF << 16) // (SPI) Peripheral Chip Select\r
+#define AT91C_SPI_DLYBCS      (0xFF << 24) // (SPI) Delay Between Chip Selects\r
+// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- \r
+#define AT91C_SPI_RD          (0xFFFF <<  0) // (SPI) Receive Data\r
+#define AT91C_SPI_RPCS        (0xF << 16) // (SPI) Peripheral Chip Select Status\r
+// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- \r
+#define AT91C_SPI_TD          (0xFFFF <<  0) // (SPI) Transmit Data\r
+#define AT91C_SPI_TPCS        (0xF << 16) // (SPI) Peripheral Chip Select Status\r
+// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- \r
+#define AT91C_SPI_RDRF        (0x1 <<  0) // (SPI) Receive Data Register Full\r
+#define AT91C_SPI_TDRE        (0x1 <<  1) // (SPI) Transmit Data Register Empty\r
+#define AT91C_SPI_MODF        (0x1 <<  2) // (SPI) Mode Fault Error\r
+#define AT91C_SPI_OVRES       (0x1 <<  3) // (SPI) Overrun Error Status\r
+#define AT91C_SPI_ENDRX       (0x1 <<  4) // (SPI) End of Receiver Transfer\r
+#define AT91C_SPI_ENDTX       (0x1 <<  5) // (SPI) End of Receiver Transfer\r
+#define AT91C_SPI_RXBUFF      (0x1 <<  6) // (SPI) RXBUFF Interrupt\r
+#define AT91C_SPI_TXBUFE      (0x1 <<  7) // (SPI) TXBUFE Interrupt\r
+#define AT91C_SPI_NSSR        (0x1 <<  8) // (SPI) NSSR Interrupt\r
+#define AT91C_SPI_TXEMPTY     (0x1 <<  9) // (SPI) TXEMPTY Interrupt\r
+#define AT91C_SPI_SPIENS      (0x1 << 16) // (SPI) Enable Status\r
+// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- \r
+// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- \r
+// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- \r
+// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- \r
+#define AT91C_SPI_CPOL        (0x1 <<  0) // (SPI) Clock Polarity\r
+#define AT91C_SPI_NCPHA       (0x1 <<  1) // (SPI) Clock Phase\r
+#define AT91C_SPI_CSNAAT      (0x1 <<  2) // (SPI) Chip Select Not Active After Transfer (Ignored if CSAAT = 1)\r
+#define AT91C_SPI_CSAAT       (0x1 <<  3) // (SPI) Chip Select Active After Transfer\r
+#define AT91C_SPI_BITS        (0xF <<  4) // (SPI) Bits Per Transfer\r
+#define        AT91C_SPI_BITS_8                    (0x0 <<  4) // (SPI) 8 Bits Per transfer\r
+#define        AT91C_SPI_BITS_9                    (0x1 <<  4) // (SPI) 9 Bits Per transfer\r
+#define        AT91C_SPI_BITS_10                   (0x2 <<  4) // (SPI) 10 Bits Per transfer\r
+#define        AT91C_SPI_BITS_11                   (0x3 <<  4) // (SPI) 11 Bits Per transfer\r
+#define        AT91C_SPI_BITS_12                   (0x4 <<  4) // (SPI) 12 Bits Per transfer\r
+#define        AT91C_SPI_BITS_13                   (0x5 <<  4) // (SPI) 13 Bits Per transfer\r
+#define        AT91C_SPI_BITS_14                   (0x6 <<  4) // (SPI) 14 Bits Per transfer\r
+#define        AT91C_SPI_BITS_15                   (0x7 <<  4) // (SPI) 15 Bits Per transfer\r
+#define        AT91C_SPI_BITS_16                   (0x8 <<  4) // (SPI) 16 Bits Per transfer\r
+#define AT91C_SPI_SCBR        (0xFF <<  8) // (SPI) Serial Clock Baud Rate\r
+#define AT91C_SPI_DLYBS       (0xFF << 16) // (SPI) Serial Clock Baud Rate\r
+#define AT91C_SPI_DLYBCT      (0xFF << 24) // (SPI) Delay Between Consecutive Transfers\r
+\r
+// *****************************************************************************\r
+//              SOFTWARE API DEFINITION  FOR UDPHS Enpoint FIFO data register\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_UDPHS_EPTFIFO {\r
+       AT91_REG         UDPHS_READEPT0[16384];         // FIFO Endpoint Data Register 0\r
+       AT91_REG         UDPHS_READEPT1[16384];         // FIFO Endpoint Data Register 1\r
+       AT91_REG         UDPHS_READEPT2[16384];         // FIFO Endpoint Data Register 2\r
+       AT91_REG         UDPHS_READEPT3[16384];         // FIFO Endpoint Data Register 3\r
+       AT91_REG         UDPHS_READEPT4[16384];         // FIFO Endpoint Data Register 4\r
+       AT91_REG         UDPHS_READEPT5[16384];         // FIFO Endpoint Data Register 5\r
+       AT91_REG         UDPHS_READEPT6[16384];         // FIFO Endpoint Data Register 6\r
+} AT91S_UDPHS_EPTFIFO, *AT91PS_UDPHS_EPTFIFO;\r
+#else\r
+#define UDPHS_READEPT0  (AT91_CAST(AT91_REG *)         0x00000000) // (UDPHS_READEPT0) FIFO Endpoint Data Register 0\r
+#define UDPHS_READEPT1  (AT91_CAST(AT91_REG *)         0x00010000) // (UDPHS_READEPT1) FIFO Endpoint Data Register 1\r
+#define UDPHS_READEPT2  (AT91_CAST(AT91_REG *)         0x00020000) // (UDPHS_READEPT2) FIFO Endpoint Data Register 2\r
+#define UDPHS_READEPT3  (AT91_CAST(AT91_REG *)         0x00030000) // (UDPHS_READEPT3) FIFO Endpoint Data Register 3\r
+#define UDPHS_READEPT4  (AT91_CAST(AT91_REG *)         0x00040000) // (UDPHS_READEPT4) FIFO Endpoint Data Register 4\r
+#define UDPHS_READEPT5  (AT91_CAST(AT91_REG *)         0x00050000) // (UDPHS_READEPT5) FIFO Endpoint Data Register 5\r
+#define UDPHS_READEPT6  (AT91_CAST(AT91_REG *)         0x00060000) // (UDPHS_READEPT6) FIFO Endpoint Data Register 6\r
+\r
+#endif\r
+\r
+// *****************************************************************************\r
+//              SOFTWARE API DEFINITION  FOR UDPHS Endpoint struct\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_UDPHS_EPT {\r
+       AT91_REG         UDPHS_EPTCFG;  // UDPHS Endpoint Config Register\r
+       AT91_REG         UDPHS_EPTCTLENB;       // UDPHS Endpoint Control Enable Register\r
+       AT91_REG         UDPHS_EPTCTLDIS;       // UDPHS Endpoint Control Disable Register\r
+       AT91_REG         UDPHS_EPTCTL;  // UDPHS Endpoint Control Register\r
+       AT91_REG         Reserved0[1];  // \r
+       AT91_REG         UDPHS_EPTSETSTA;       // UDPHS Endpoint Set Status Register\r
+       AT91_REG         UDPHS_EPTCLRSTA;       // UDPHS Endpoint Clear Status Register\r
+       AT91_REG         UDPHS_EPTSTA;  // UDPHS Endpoint Status Register\r
+} AT91S_UDPHS_EPT, *AT91PS_UDPHS_EPT;\r
+#else\r
+#define UDPHS_EPTCFG    (AT91_CAST(AT91_REG *)         0x00000000) // (UDPHS_EPTCFG) UDPHS Endpoint Config Register\r
+#define UDPHS_EPTCTLENB (AT91_CAST(AT91_REG *)         0x00000004) // (UDPHS_EPTCTLENB) UDPHS Endpoint Control Enable Register\r
+#define UDPHS_EPTCTLDIS (AT91_CAST(AT91_REG *)         0x00000008) // (UDPHS_EPTCTLDIS) UDPHS Endpoint Control Disable Register\r
+#define UDPHS_EPTCTL    (AT91_CAST(AT91_REG *)         0x0000000C) // (UDPHS_EPTCTL) UDPHS Endpoint Control Register\r
+#define UDPHS_EPTSETSTA (AT91_CAST(AT91_REG *)         0x00000014) // (UDPHS_EPTSETSTA) UDPHS Endpoint Set Status Register\r
+#define UDPHS_EPTCLRSTA (AT91_CAST(AT91_REG *)         0x00000018) // (UDPHS_EPTCLRSTA) UDPHS Endpoint Clear Status Register\r
+#define UDPHS_EPTSTA    (AT91_CAST(AT91_REG *)         0x0000001C) // (UDPHS_EPTSTA) UDPHS Endpoint Status Register\r
+\r
+#endif\r
+// -------- UDPHS_EPTCFG : (UDPHS_EPT Offset: 0x0) UDPHS Endpoint Config Register -------- \r
+#define AT91C_UDPHS_EPT_SIZE  (0x7 <<  0) // (UDPHS_EPT) Endpoint Size\r
+#define        AT91C_UDPHS_EPT_SIZE_8                    (0x0) // (UDPHS_EPT)    8 bytes\r
+#define        AT91C_UDPHS_EPT_SIZE_16                   (0x1) // (UDPHS_EPT)   16 bytes\r
+#define        AT91C_UDPHS_EPT_SIZE_32                   (0x2) // (UDPHS_EPT)   32 bytes\r
+#define        AT91C_UDPHS_EPT_SIZE_64                   (0x3) // (UDPHS_EPT)   64 bytes\r
+#define        AT91C_UDPHS_EPT_SIZE_128                  (0x4) // (UDPHS_EPT)  128 bytes\r
+#define        AT91C_UDPHS_EPT_SIZE_256                  (0x5) // (UDPHS_EPT)  256 bytes (if possible)\r
+#define        AT91C_UDPHS_EPT_SIZE_512                  (0x6) // (UDPHS_EPT)  512 bytes (if possible)\r
+#define        AT91C_UDPHS_EPT_SIZE_1024                 (0x7) // (UDPHS_EPT) 1024 bytes (if possible)\r
+#define AT91C_UDPHS_EPT_DIR   (0x1 <<  3) // (UDPHS_EPT) Endpoint Direction 0:OUT, 1:IN\r
+#define        AT91C_UDPHS_EPT_DIR_OUT                  (0x0 <<  3) // (UDPHS_EPT) Direction OUT\r
+#define        AT91C_UDPHS_EPT_DIR_IN                   (0x1 <<  3) // (UDPHS_EPT) Direction IN\r
+#define AT91C_UDPHS_EPT_TYPE  (0x3 <<  4) // (UDPHS_EPT) Endpoint Type\r
+#define        AT91C_UDPHS_EPT_TYPE_CTL_EPT              (0x0 <<  4) // (UDPHS_EPT) Control endpoint\r
+#define        AT91C_UDPHS_EPT_TYPE_ISO_EPT              (0x1 <<  4) // (UDPHS_EPT) Isochronous endpoint\r
+#define        AT91C_UDPHS_EPT_TYPE_BUL_EPT              (0x2 <<  4) // (UDPHS_EPT) Bulk endpoint\r
+#define        AT91C_UDPHS_EPT_TYPE_INT_EPT              (0x3 <<  4) // (UDPHS_EPT) Interrupt endpoint\r
+#define AT91C_UDPHS_BK_NUMBER (0x3 <<  6) // (UDPHS_EPT) Number of Banks\r
+#define        AT91C_UDPHS_BK_NUMBER_0                    (0x0 <<  6) // (UDPHS_EPT) Zero Bank, the EndPoint is not mapped in memory\r
+#define        AT91C_UDPHS_BK_NUMBER_1                    (0x1 <<  6) // (UDPHS_EPT) One Bank (Bank0)\r
+#define        AT91C_UDPHS_BK_NUMBER_2                    (0x2 <<  6) // (UDPHS_EPT) Double bank (Ping-Pong : Bank0 / Bank1)\r
+#define        AT91C_UDPHS_BK_NUMBER_3                    (0x3 <<  6) // (UDPHS_EPT) Triple Bank (Bank0 / Bank1 / Bank2) (if possible)\r
+#define AT91C_UDPHS_NB_TRANS  (0x3 <<  8) // (UDPHS_EPT) Number Of Transaction per Micro-Frame (High-Bandwidth iso only)\r
+#define AT91C_UDPHS_EPT_MAPD  (0x1 << 31) // (UDPHS_EPT) Endpoint Mapped (read only\r
+// -------- UDPHS_EPTCTLENB : (UDPHS_EPT Offset: 0x4) UDPHS Endpoint Control Enable Register -------- \r
+#define AT91C_UDPHS_EPT_ENABL (0x1 <<  0) // (UDPHS_EPT) Endpoint Enable\r
+#define AT91C_UDPHS_AUTO_VALID (0x1 <<  1) // (UDPHS_EPT) Packet Auto-Valid Enable/Disable\r
+#define AT91C_UDPHS_INTDIS_DMA (0x1 <<  3) // (UDPHS_EPT) Endpoint Interrupts DMA Request Enable/Disable\r
+#define AT91C_UDPHS_NYET_DIS  (0x1 <<  4) // (UDPHS_EPT) NYET Enable/Disable\r
+#define AT91C_UDPHS_DATAX_RX  (0x1 <<  6) // (UDPHS_EPT) DATAx Interrupt Enable/Disable\r
+#define AT91C_UDPHS_MDATA_RX  (0x1 <<  7) // (UDPHS_EPT) MDATA Interrupt Enabled/Disable\r
+#define AT91C_UDPHS_ERR_OVFLW (0x1 <<  8) // (UDPHS_EPT) OverFlow Error Interrupt Enable/Disable/Status\r
+#define AT91C_UDPHS_RX_BK_RDY (0x1 <<  9) // (UDPHS_EPT) Received OUT Data\r
+#define AT91C_UDPHS_TX_COMPLT (0x1 << 10) // (UDPHS_EPT) Transmitted IN Data Complete Interrupt Enable/Disable or Transmitted IN Data Complete (clear)\r
+#define AT91C_UDPHS_ERR_TRANS (0x1 << 11) // (UDPHS_EPT) Transaction Error Interrupt Enable/Disable\r
+#define AT91C_UDPHS_TX_PK_RDY (0x1 << 11) // (UDPHS_EPT) TX Packet Ready Interrupt Enable/Disable\r
+#define AT91C_UDPHS_RX_SETUP  (0x1 << 12) // (UDPHS_EPT) Received SETUP Interrupt Enable/Disable\r
+#define AT91C_UDPHS_ERR_FL_ISO (0x1 << 12) // (UDPHS_EPT) Error Flow Clear/Interrupt Enable/Disable\r
+#define AT91C_UDPHS_STALL_SNT (0x1 << 13) // (UDPHS_EPT) Stall Sent Clear\r
+#define AT91C_UDPHS_ERR_CRISO (0x1 << 13) // (UDPHS_EPT) CRC error / Error NB Trans / Interrupt Enable/Disable\r
+#define AT91C_UDPHS_NAK_IN    (0x1 << 14) // (UDPHS_EPT) NAKIN ERROR FLUSH / Clear / Interrupt Enable/Disable\r
+#define AT91C_UDPHS_NAK_OUT   (0x1 << 15) // (UDPHS_EPT) NAKOUT / Clear / Interrupt Enable/Disable\r
+#define AT91C_UDPHS_BUSY_BANK (0x1 << 18) // (UDPHS_EPT) Busy Bank Interrupt Enable/Disable\r
+#define AT91C_UDPHS_SHRT_PCKT (0x1 << 31) // (UDPHS_EPT) Short Packet / Interrupt Enable/Disable\r
+// -------- UDPHS_EPTCTLDIS : (UDPHS_EPT Offset: 0x8) UDPHS Endpoint Control Disable Register -------- \r
+#define AT91C_UDPHS_EPT_DISABL (0x1 <<  0) // (UDPHS_EPT) Endpoint Disable\r
+// -------- UDPHS_EPTCTL : (UDPHS_EPT Offset: 0xc) UDPHS Endpoint Control Register -------- \r
+// -------- UDPHS_EPTSETSTA : (UDPHS_EPT Offset: 0x14) UDPHS Endpoint Set Status Register -------- \r
+#define AT91C_UDPHS_FRCESTALL (0x1 <<  5) // (UDPHS_EPT) Stall Handshake Request Set/Clear/Status\r
+#define AT91C_UDPHS_KILL_BANK (0x1 <<  9) // (UDPHS_EPT) KILL Bank\r
+// -------- UDPHS_EPTCLRSTA : (UDPHS_EPT Offset: 0x18) UDPHS Endpoint Clear Status Register -------- \r
+#define AT91C_UDPHS_TOGGLESQ  (0x1 <<  6) // (UDPHS_EPT) Data Toggle Clear\r
+// -------- UDPHS_EPTSTA : (UDPHS_EPT Offset: 0x1c) UDPHS Endpoint Status Register -------- \r
+#define AT91C_UDPHS_TOGGLESQ_STA (0x3 <<  6) // (UDPHS_EPT) Toggle Sequencing\r
+#define        AT91C_UDPHS_TOGGLESQ_STA_00                   (0x0 <<  6) // (UDPHS_EPT) Data0\r
+#define        AT91C_UDPHS_TOGGLESQ_STA_01                   (0x1 <<  6) // (UDPHS_EPT) Data1\r
+#define        AT91C_UDPHS_TOGGLESQ_STA_10                   (0x2 <<  6) // (UDPHS_EPT) Data2 (only for High-Bandwidth Isochronous EndPoint)\r
+#define        AT91C_UDPHS_TOGGLESQ_STA_11                   (0x3 <<  6) // (UDPHS_EPT) MData (only for High-Bandwidth Isochronous EndPoint)\r
+#define AT91C_UDPHS_CONTROL_DIR (0x3 << 16) // (UDPHS_EPT) \r
+#define        AT91C_UDPHS_CONTROL_DIR_00                   (0x0 << 16) // (UDPHS_EPT) Bank 0\r
+#define        AT91C_UDPHS_CONTROL_DIR_01                   (0x1 << 16) // (UDPHS_EPT) Bank 1\r
+#define        AT91C_UDPHS_CONTROL_DIR_10                   (0x2 << 16) // (UDPHS_EPT) Bank 2\r
+#define        AT91C_UDPHS_CONTROL_DIR_11                   (0x3 << 16) // (UDPHS_EPT) Invalid\r
+#define AT91C_UDPHS_CURRENT_BANK (0x3 << 16) // (UDPHS_EPT) \r
+#define        AT91C_UDPHS_CURRENT_BANK_00                   (0x0 << 16) // (UDPHS_EPT) Bank 0\r
+#define        AT91C_UDPHS_CURRENT_BANK_01                   (0x1 << 16) // (UDPHS_EPT) Bank 1\r
+#define        AT91C_UDPHS_CURRENT_BANK_10                   (0x2 << 16) // (UDPHS_EPT) Bank 2\r
+#define        AT91C_UDPHS_CURRENT_BANK_11                   (0x3 << 16) // (UDPHS_EPT) Invalid\r
+#define AT91C_UDPHS_BUSY_BANK_STA (0x3 << 18) // (UDPHS_EPT) Busy Bank Number\r
+#define        AT91C_UDPHS_BUSY_BANK_STA_00                   (0x0 << 18) // (UDPHS_EPT) All banks are free\r
+#define        AT91C_UDPHS_BUSY_BANK_STA_01                   (0x1 << 18) // (UDPHS_EPT) 1 busy bank\r
+#define        AT91C_UDPHS_BUSY_BANK_STA_10                   (0x2 << 18) // (UDPHS_EPT) 2 busy banks\r
+#define        AT91C_UDPHS_BUSY_BANK_STA_11                   (0x3 << 18) // (UDPHS_EPT) 3 busy banks (if possible)\r
+#define AT91C_UDPHS_BYTE_COUNT (0x7FF << 20) // (UDPHS_EPT) UDPHS Byte Count\r
+\r
+// *****************************************************************************\r
+//              SOFTWARE API DEFINITION  FOR UDPHS DMA struct\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_UDPHS_DMA {\r
+       AT91_REG         UDPHS_DMANXTDSC;       // UDPHS DMA Channel Next Descriptor Address\r
+       AT91_REG         UDPHS_DMAADDRESS;      // UDPHS DMA Channel Address Register\r
+       AT91_REG         UDPHS_DMACONTROL;      // UDPHS DMA Channel Control Register\r
+       AT91_REG         UDPHS_DMASTATUS;       // UDPHS DMA Channel Status Register\r
+} AT91S_UDPHS_DMA, *AT91PS_UDPHS_DMA;\r
+#else\r
+#define UDPHS_DMANXTDSC (AT91_CAST(AT91_REG *)         0x00000000) // (UDPHS_DMANXTDSC) UDPHS DMA Channel Next Descriptor Address\r
+#define UDPHS_DMAADDRESS (AT91_CAST(AT91_REG *)        0x00000004) // (UDPHS_DMAADDRESS) UDPHS DMA Channel Address Register\r
+#define UDPHS_DMACONTROL (AT91_CAST(AT91_REG *)        0x00000008) // (UDPHS_DMACONTROL) UDPHS DMA Channel Control Register\r
+#define UDPHS_DMASTATUS (AT91_CAST(AT91_REG *)         0x0000000C) // (UDPHS_DMASTATUS) UDPHS DMA Channel Status Register\r
+\r
+#endif\r
+// -------- UDPHS_DMANXTDSC : (UDPHS_DMA Offset: 0x0) UDPHS DMA Next Descriptor Address Register -------- \r
+#define AT91C_UDPHS_NXT_DSC_ADD (0xFFFFFFF <<  4) // (UDPHS_DMA) next Channel Descriptor\r
+// -------- UDPHS_DMAADDRESS : (UDPHS_DMA Offset: 0x4) UDPHS DMA Channel Address Register -------- \r
+#define AT91C_UDPHS_BUFF_ADD  (0x0 <<  0) // (UDPHS_DMA) starting address of a DMA Channel transfer\r
+// -------- UDPHS_DMACONTROL : (UDPHS_DMA Offset: 0x8) UDPHS DMA Channel Control Register -------- \r
+#define AT91C_UDPHS_CHANN_ENB (0x1 <<  0) // (UDPHS_DMA) Channel Enabled\r
+#define AT91C_UDPHS_LDNXT_DSC (0x1 <<  1) // (UDPHS_DMA) Load Next Channel Transfer Descriptor Enable\r
+#define AT91C_UDPHS_END_TR_EN (0x1 <<  2) // (UDPHS_DMA) Buffer Close Input Enable\r
+#define AT91C_UDPHS_END_B_EN  (0x1 <<  3) // (UDPHS_DMA) End of DMA Buffer Packet Validation\r
+#define AT91C_UDPHS_END_TR_IT (0x1 <<  4) // (UDPHS_DMA) End Of Transfer Interrupt Enable\r
+#define AT91C_UDPHS_END_BUFFIT (0x1 <<  5) // (UDPHS_DMA) End Of Channel Buffer Interrupt Enable\r
+#define AT91C_UDPHS_DESC_LD_IT (0x1 <<  6) // (UDPHS_DMA) Descriptor Loaded Interrupt Enable\r
+#define AT91C_UDPHS_BURST_LCK (0x1 <<  7) // (UDPHS_DMA) Burst Lock Enable\r
+#define AT91C_UDPHS_BUFF_LENGTH (0xFFFF << 16) // (UDPHS_DMA) Buffer Byte Length (write only)\r
+// -------- UDPHS_DMASTATUS : (UDPHS_DMA Offset: 0xc) UDPHS DMA Channelx Status Register -------- \r
+#define AT91C_UDPHS_CHANN_ACT (0x1 <<  1) // (UDPHS_DMA) \r
+#define AT91C_UDPHS_END_TR_ST (0x1 <<  4) // (UDPHS_DMA) \r
+#define AT91C_UDPHS_END_BF_ST (0x1 <<  5) // (UDPHS_DMA) \r
+#define AT91C_UDPHS_DESC_LDST (0x1 <<  6) // (UDPHS_DMA) \r
+#define AT91C_UDPHS_BUFF_COUNT (0xFFFF << 16) // (UDPHS_DMA) \r
+\r
+// *****************************************************************************\r
+//              SOFTWARE API DEFINITION  FOR UDPHS High Speed Device Interface\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_UDPHS {\r
+       AT91_REG         UDPHS_CTRL;    // UDPHS Control Register\r
+       AT91_REG         UDPHS_FNUM;    // UDPHS Frame Number Register\r
+       AT91_REG         Reserved0[2];  // \r
+       AT91_REG         UDPHS_IEN;     // UDPHS Interrupt Enable Register\r
+       AT91_REG         UDPHS_INTSTA;  // UDPHS Interrupt Status Register\r
+       AT91_REG         UDPHS_CLRINT;  // UDPHS Clear Interrupt Register\r
+       AT91_REG         UDPHS_EPTRST;  // UDPHS Endpoints Reset Register\r
+       AT91_REG         Reserved1[44];         // \r
+       AT91_REG         UDPHS_TSTSOFCNT;       // UDPHS Test SOF Counter Register\r
+       AT91_REG         UDPHS_TSTCNTA;         // UDPHS Test A Counter Register\r
+       AT91_REG         UDPHS_TSTCNTB;         // UDPHS Test B Counter Register\r
+       AT91_REG         UDPHS_TSTMODREG;       // UDPHS Test Mode Register\r
+       AT91_REG         UDPHS_TST;     // UDPHS Test Register\r
+       AT91_REG         Reserved2[2];  // \r
+       AT91_REG         UDPHS_RIPPADDRSIZE;    // UDPHS PADDRSIZE Register\r
+       AT91_REG         UDPHS_RIPNAME1;        // UDPHS Name1 Register\r
+       AT91_REG         UDPHS_RIPNAME2;        // UDPHS Name2 Register\r
+       AT91_REG         UDPHS_IPFEATURES;      // UDPHS Features Register\r
+       AT91_REG         UDPHS_IPVERSION;       // UDPHS Version Register\r
+       AT91S_UDPHS_EPT  UDPHS_EPT[7];  // UDPHS Endpoint struct\r
+       AT91_REG         Reserved3[72];         // \r
+       AT91S_UDPHS_DMA  UDPHS_DMA[6];  // UDPHS DMA channel struct (not use [0])\r
+} AT91S_UDPHS, *AT91PS_UDPHS;\r
+#else\r
+#define UDPHS_CTRL      (AT91_CAST(AT91_REG *)         0x00000000) // (UDPHS_CTRL) UDPHS Control Register\r
+#define UDPHS_FNUM      (AT91_CAST(AT91_REG *)         0x00000004) // (UDPHS_FNUM) UDPHS Frame Number Register\r
+#define UDPHS_IEN       (AT91_CAST(AT91_REG *)         0x00000010) // (UDPHS_IEN) UDPHS Interrupt Enable Register\r
+#define UDPHS_INTSTA    (AT91_CAST(AT91_REG *)         0x00000014) // (UDPHS_INTSTA) UDPHS Interrupt Status Register\r
+#define UDPHS_CLRINT    (AT91_CAST(AT91_REG *)         0x00000018) // (UDPHS_CLRINT) UDPHS Clear Interrupt Register\r
+#define UDPHS_EPTRST    (AT91_CAST(AT91_REG *)         0x0000001C) // (UDPHS_EPTRST) UDPHS Endpoints Reset Register\r
+#define UDPHS_TSTSOFCNT (AT91_CAST(AT91_REG *)         0x000000D0) // (UDPHS_TSTSOFCNT) UDPHS Test SOF Counter Register\r
+#define UDPHS_TSTCNTA   (AT91_CAST(AT91_REG *)         0x000000D4) // (UDPHS_TSTCNTA) UDPHS Test A Counter Register\r
+#define UDPHS_TSTCNTB   (AT91_CAST(AT91_REG *)         0x000000D8) // (UDPHS_TSTCNTB) UDPHS Test B Counter Register\r
+#define UDPHS_TSTMODREG (AT91_CAST(AT91_REG *)         0x000000DC) // (UDPHS_TSTMODREG) UDPHS Test Mode Register\r
+#define UDPHS_TST       (AT91_CAST(AT91_REG *)         0x000000E0) // (UDPHS_TST) UDPHS Test Register\r
+#define UDPHS_RIPPADDRSIZE (AT91_CAST(AT91_REG *)      0x000000EC) // (UDPHS_RIPPADDRSIZE) UDPHS PADDRSIZE Register\r
+#define UDPHS_RIPNAME1  (AT91_CAST(AT91_REG *)         0x000000F0) // (UDPHS_RIPNAME1) UDPHS Name1 Register\r
+#define UDPHS_RIPNAME2  (AT91_CAST(AT91_REG *)         0x000000F4) // (UDPHS_RIPNAME2) UDPHS Name2 Register\r
+#define UDPHS_IPFEATURES (AT91_CAST(AT91_REG *)        0x000000F8) // (UDPHS_IPFEATURES) UDPHS Features Register\r
+#define UDPHS_IPVERSION (AT91_CAST(AT91_REG *)         0x000000FC) // (UDPHS_IPVERSION) UDPHS Version Register\r
+\r
+#endif\r
+// -------- UDPHS_CTRL : (UDPHS Offset: 0x0) UDPHS Control Register -------- \r
+#define AT91C_UDPHS_DEV_ADDR  (0x7F <<  0) // (UDPHS) UDPHS Address\r
+#define AT91C_UDPHS_FADDR_EN  (0x1 <<  7) // (UDPHS) Function Address Enable\r
+#define AT91C_UDPHS_EN_UDPHS  (0x1 <<  8) // (UDPHS) UDPHS Enable\r
+#define AT91C_UDPHS_DETACH    (0x1 <<  9) // (UDPHS) Detach Command\r
+#define AT91C_UDPHS_REWAKEUP  (0x1 << 10) // (UDPHS) Send Remote Wake Up\r
+#define AT91C_UDPHS_PULLD_DIS (0x1 << 11) // (UDPHS) PullDown Disable\r
+// -------- UDPHS_FNUM : (UDPHS Offset: 0x4) UDPHS Frame Number Register -------- \r
+#define AT91C_UDPHS_MICRO_FRAME_NUM (0x7 <<  0) // (UDPHS) Micro Frame Number\r
+#define AT91C_UDPHS_FRAME_NUMBER (0x7FF <<  3) // (UDPHS) Frame Number as defined in the Packet Field Formats\r
+#define AT91C_UDPHS_FNUM_ERR  (0x1 << 31) // (UDPHS) Frame Number CRC Error\r
+// -------- UDPHS_IEN : (UDPHS Offset: 0x10) UDPHS Interrupt Enable Register -------- \r
+#define AT91C_UDPHS_DET_SUSPD (0x1 <<  1) // (UDPHS) Suspend Interrupt Enable/Clear/Status\r
+#define AT91C_UDPHS_MICRO_SOF (0x1 <<  2) // (UDPHS) Micro-SOF Interrupt Enable/Clear/Status\r
+#define AT91C_UDPHS_IEN_SOF   (0x1 <<  3) // (UDPHS) SOF Interrupt Enable/Clear/Status\r
+#define AT91C_UDPHS_ENDRESET  (0x1 <<  4) // (UDPHS) End Of Reset Interrupt Enable/Clear/Status\r
+#define AT91C_UDPHS_WAKE_UP   (0x1 <<  5) // (UDPHS) Wake Up CPU Interrupt Enable/Clear/Status\r
+#define AT91C_UDPHS_ENDOFRSM  (0x1 <<  6) // (UDPHS) End Of Resume Interrupt Enable/Clear/Status\r
+#define AT91C_UDPHS_UPSTR_RES (0x1 <<  7) // (UDPHS) Upstream Resume Interrupt Enable/Clear/Status\r
+#define AT91C_UDPHS_EPT_INT_0 (0x1 <<  8) // (UDPHS) Endpoint 0 Interrupt Enable/Status\r
+#define AT91C_UDPHS_EPT_INT_1 (0x1 <<  9) // (UDPHS) Endpoint 1 Interrupt Enable/Status\r
+#define AT91C_UDPHS_EPT_INT_2 (0x1 << 10) // (UDPHS) Endpoint 2 Interrupt Enable/Status\r
+#define AT91C_UDPHS_EPT_INT_3 (0x1 << 11) // (UDPHS) Endpoint 3 Interrupt Enable/Status\r
+#define AT91C_UDPHS_EPT_INT_4 (0x1 << 12) // (UDPHS) Endpoint 4 Interrupt Enable/Status\r
+#define AT91C_UDPHS_EPT_INT_5 (0x1 << 13) // (UDPHS) Endpoint 5 Interrupt Enable/Status\r
+#define AT91C_UDPHS_EPT_INT_6 (0x1 << 14) // (UDPHS) Endpoint 6 Interrupt Enable/Status\r
+#define AT91C_UDPHS_DMA_INT_1 (0x1 << 25) // (UDPHS) DMA Channel 1 Interrupt Enable/Status\r
+#define AT91C_UDPHS_DMA_INT_2 (0x1 << 26) // (UDPHS) DMA Channel 2 Interrupt Enable/Status\r
+#define AT91C_UDPHS_DMA_INT_3 (0x1 << 27) // (UDPHS) DMA Channel 3 Interrupt Enable/Status\r
+#define AT91C_UDPHS_DMA_INT_4 (0x1 << 28) // (UDPHS) DMA Channel 4 Interrupt Enable/Status\r
+#define AT91C_UDPHS_DMA_INT_5 (0x1 << 29) // (UDPHS) DMA Channel 5 Interrupt Enable/Status\r
+#define AT91C_UDPHS_DMA_INT_6 (0x1 << 30) // (UDPHS) DMA Channel 6 Interrupt Enable/Status\r
+// -------- UDPHS_INTSTA : (UDPHS Offset: 0x14) UDPHS Interrupt Status Register -------- \r
+#define AT91C_UDPHS_SPEED     (0x1 <<  0) // (UDPHS) Speed Status\r
+// -------- UDPHS_CLRINT : (UDPHS Offset: 0x18) UDPHS Clear Interrupt Register -------- \r
+// -------- UDPHS_EPTRST : (UDPHS Offset: 0x1c) UDPHS Endpoints Reset Register -------- \r
+#define AT91C_UDPHS_RST_EPT_0 (0x1 <<  0) // (UDPHS) Endpoint Reset 0\r
+#define AT91C_UDPHS_RST_EPT_1 (0x1 <<  1) // (UDPHS) Endpoint Reset 1\r
+#define AT91C_UDPHS_RST_EPT_2 (0x1 <<  2) // (UDPHS) Endpoint Reset 2\r
+#define AT91C_UDPHS_RST_EPT_3 (0x1 <<  3) // (UDPHS) Endpoint Reset 3\r
+#define AT91C_UDPHS_RST_EPT_4 (0x1 <<  4) // (UDPHS) Endpoint Reset 4\r
+#define AT91C_UDPHS_RST_EPT_5 (0x1 <<  5) // (UDPHS) Endpoint Reset 5\r
+#define AT91C_UDPHS_RST_EPT_6 (0x1 <<  6) // (UDPHS) Endpoint Reset 6\r
+// -------- UDPHS_TSTSOFCNT : (UDPHS Offset: 0xd0) UDPHS Test SOF Counter Register -------- \r
+#define AT91C_UDPHS_SOFCNTMAX (0x3 <<  0) // (UDPHS) SOF Counter Max Value\r
+#define AT91C_UDPHS_SOFCTLOAD (0x1 <<  7) // (UDPHS) SOF Counter Load\r
+// -------- UDPHS_TSTCNTA : (UDPHS Offset: 0xd4) UDPHS Test A Counter Register -------- \r
+#define AT91C_UDPHS_CNTAMAX   (0x7FFF <<  0) // (UDPHS) A Counter Max Value\r
+#define AT91C_UDPHS_CNTALOAD  (0x1 << 15) // (UDPHS) A Counter Load\r
+// -------- UDPHS_TSTCNTB : (UDPHS Offset: 0xd8) UDPHS Test B Counter Register -------- \r
+#define AT91C_UDPHS_CNTBMAX   (0x7FFF <<  0) // (UDPHS) B Counter Max Value\r
+#define AT91C_UDPHS_CNTBLOAD  (0x1 << 15) // (UDPHS) B Counter Load\r
+// -------- UDPHS_TSTMODREG : (UDPHS Offset: 0xdc) UDPHS Test Mode Register -------- \r
+#define AT91C_UDPHS_TSTMODE   (0x1F <<  1) // (UDPHS) UDPHS Core TestModeReg\r
+// -------- UDPHS_TST : (UDPHS Offset: 0xe0) UDPHS Test Register -------- \r
+#define AT91C_UDPHS_SPEED_CFG (0x3 <<  0) // (UDPHS) Speed Configuration\r
+#define        AT91C_UDPHS_SPEED_CFG_NM                   (0x0) // (UDPHS) Normal Mode\r
+#define        AT91C_UDPHS_SPEED_CFG_RS                   (0x1) // (UDPHS) Reserved\r
+#define        AT91C_UDPHS_SPEED_CFG_HS                   (0x2) // (UDPHS) Force High Speed\r
+#define        AT91C_UDPHS_SPEED_CFG_FS                   (0x3) // (UDPHS) Force Full-Speed\r
+#define AT91C_UDPHS_TST_J     (0x1 <<  2) // (UDPHS) TestJMode\r
+#define AT91C_UDPHS_TST_K     (0x1 <<  3) // (UDPHS) TestKMode\r
+#define AT91C_UDPHS_TST_PKT   (0x1 <<  4) // (UDPHS) TestPacketMode\r
+#define AT91C_UDPHS_OPMODE2   (0x1 <<  5) // (UDPHS) OpMode2\r
+// -------- UDPHS_RIPPADDRSIZE : (UDPHS Offset: 0xec) UDPHS PADDRSIZE Register -------- \r
+#define AT91C_UDPHS_IPPADDRSIZE (0x0 <<  0) // (UDPHS) 2^UDPHSDEV_PADDR_SIZE\r
+// -------- UDPHS_RIPNAME1 : (UDPHS Offset: 0xf0) UDPHS Name Register -------- \r
+#define AT91C_UDPHS_IPNAME1   (0x0 <<  0) // (UDPHS) ASCII string HUSB\r
+// -------- UDPHS_RIPNAME2 : (UDPHS Offset: 0xf4) UDPHS Name Register -------- \r
+#define AT91C_UDPHS_IPNAME2   (0x0 <<  0) // (UDPHS) ASCII string 2DEV\r
+// -------- UDPHS_IPFEATURES : (UDPHS Offset: 0xf8) UDPHS Features Register -------- \r
+#define AT91C_UDPHS_EPT_NBR_MAX (0xF <<  0) // (UDPHS) Max Number of Endpoints\r
+#define AT91C_UDPHS_DMA_CHANNEL_NBR (0x7 <<  4) // (UDPHS) Number of DMA Channels\r
+#define AT91C_UDPHS_DMA_B_SIZ (0x1 <<  7) // (UDPHS) DMA Buffer Size\r
+#define AT91C_UDPHS_DMA_FIFO_WORD_DEPTH (0xF <<  8) // (UDPHS) DMA FIFO Depth in words\r
+#define AT91C_UDPHS_FIFO_MAX_SIZE (0x7 << 12) // (UDPHS) DPRAM size\r
+#define AT91C_UDPHS_BW_DPRAM  (0x1 << 15) // (UDPHS) DPRAM byte write capability\r
+#define AT91C_UDPHS_DATAB16_8 (0x1 << 16) // (UDPHS) UTMI DataBus16_8\r
+#define AT91C_UDPHS_ISO_EPT_1 (0x1 << 17) // (UDPHS) Endpoint 1 High Bandwidth Isochronous Capability\r
+#define AT91C_UDPHS_ISO_EPT_2 (0x1 << 18) // (UDPHS) Endpoint 2 High Bandwidth Isochronous Capability\r
+#define AT91C_UDPHS_ISO_EPT_5 (0x1 << 21) // (UDPHS) Endpoint 5 High Bandwidth Isochronous Capability\r
+#define AT91C_UDPHS_ISO_EPT_6 (0x1 << 22) // (UDPHS) Endpoint 6 High Bandwidth Isochronous Capability\r
+// -------- UDPHS_IPVERSION : (UDPHS Offset: 0xfc) UDPHS Version Register -------- \r
+#define AT91C_UDPHS_VERSION_NUM (0xFFFF <<  0) // (UDPHS) Give the IP version\r
+#define AT91C_UDPHS_METAL_FIX_NUM (0x7 << 16) // (UDPHS) Give the number of metal fixes\r
+\r
+// *****************************************************************************\r
+//              SOFTWARE API DEFINITION  FOR HDMA Channel structure\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_HDMA_CH {\r
+       AT91_REG         HDMA_SADDR;    // HDMA Channel Source Address Register\r
+       AT91_REG         HDMA_DADDR;    // HDMA Channel Destination Address Register\r
+       AT91_REG         HDMA_DSCR;     // HDMA Channel Descriptor Address Register\r
+       AT91_REG         HDMA_CTRLA;    // HDMA Channel Control A Register\r
+       AT91_REG         HDMA_CTRLB;    // HDMA Channel Control B Register\r
+       AT91_REG         HDMA_CFG;      // HDMA Channel Configuration Register\r
+       AT91_REG         HDMA_SPIP;     // HDMA Channel Source Picture in Picture Configuration Register\r
+       AT91_REG         HDMA_DPIP;     // HDMA Channel Destination Picture in Picture Configuration Register\r
+       AT91_REG         HDMA_BDSCR;    // HDMA Reserved\r
+       AT91_REG         HDMA_CADDR;    // HDMA Reserved\r
+} AT91S_HDMA_CH, *AT91PS_HDMA_CH;\r
+#else\r
+#define HDMA_SADDR      (AT91_CAST(AT91_REG *)         0x00000000) // (HDMA_SADDR) HDMA Channel Source Address Register\r
+#define HDMA_DADDR      (AT91_CAST(AT91_REG *)         0x00000004) // (HDMA_DADDR) HDMA Channel Destination Address Register\r
+#define HDMA_DSCR       (AT91_CAST(AT91_REG *)         0x00000008) // (HDMA_DSCR) HDMA Channel Descriptor Address Register\r
+#define HDMA_CTRLA      (AT91_CAST(AT91_REG *)         0x0000000C) // (HDMA_CTRLA) HDMA Channel Control A Register\r
+#define HDMA_CTRLB      (AT91_CAST(AT91_REG *)         0x00000010) // (HDMA_CTRLB) HDMA Channel Control B Register\r
+#define HDMA_CFG        (AT91_CAST(AT91_REG *)         0x00000014) // (HDMA_CFG) HDMA Channel Configuration Register\r
+#define HDMA_SPIP       (AT91_CAST(AT91_REG *)         0x00000018) // (HDMA_SPIP) HDMA Channel Source Picture in Picture Configuration Register\r
+#define HDMA_DPIP       (AT91_CAST(AT91_REG *)         0x0000001C) // (HDMA_DPIP) HDMA Channel Destination Picture in Picture Configuration Register\r
+#define HDMA_BDSCR      (AT91_CAST(AT91_REG *)         0x00000020) // (HDMA_BDSCR) HDMA Reserved\r
+#define HDMA_CADDR      (AT91_CAST(AT91_REG *)         0x00000024) // (HDMA_CADDR) HDMA Reserved\r
+\r
+#endif\r
+// -------- HDMA_SADDR : (HDMA_CH Offset: 0x0)  -------- \r
+#define AT91C_SADDR           (0x0 <<  0) // (HDMA_CH) \r
+// -------- HDMA_DADDR : (HDMA_CH Offset: 0x4)  -------- \r
+#define AT91C_DADDR           (0x0 <<  0) // (HDMA_CH) \r
+// -------- HDMA_DSCR : (HDMA_CH Offset: 0x8)  -------- \r
+#define AT91C_HDMA_DSCR_IF    (0x3 <<  0) // (HDMA_CH) Select AHB-Lite Interface for current channel\r
+#define        AT91C_HDMA_DSCR_IF_0                    (0x0) // (HDMA_CH) The Buffer Transfer descriptor is fetched via AHB-Lite Interface 0.\r
+#define        AT91C_HDMA_DSCR_IF_1                    (0x1) // (HDMA_CH) The Buffer Transfer descriptor is fetched via AHB-Lite Interface 1.\r
+#define        AT91C_HDMA_DSCR_IF_2                    (0x2) // (HDMA_CH) The Buffer Transfer descriptor is fetched via AHB-Lite Interface 2.\r
+#define        AT91C_HDMA_DSCR_IF_3                    (0x3) // (HDMA_CH) The Buffer Transfer descriptor is fetched via AHB-Lite Interface 3.\r
+#define AT91C_HDMA_DSCR       (0x3FFFFFFF <<  2) // (HDMA_CH) Buffer Transfer descriptor address. This address is word aligned.\r
+// -------- HDMA_CTRLA : (HDMA_CH Offset: 0xc)  -------- \r
+#define AT91C_HDMA_BTSIZE     (0xFFFF <<  0) // (HDMA_CH) Buffer Transfer Size.\r
+#define AT91C_HDMA_SCSIZE     (0x7 << 16) // (HDMA_CH) Source Chunk Transfer Size.\r
+#define        AT91C_HDMA_SCSIZE_1                    (0x0 << 16) // (HDMA_CH) 1.\r
+#define        AT91C_HDMA_SCSIZE_4                    (0x1 << 16) // (HDMA_CH) 4.\r
+#define        AT91C_HDMA_SCSIZE_8                    (0x2 << 16) // (HDMA_CH) 8.\r
+#define        AT91C_HDMA_SCSIZE_16                   (0x3 << 16) // (HDMA_CH) 16.\r
+#define        AT91C_HDMA_SCSIZE_32                   (0x4 << 16) // (HDMA_CH) 32.\r
+#define        AT91C_HDMA_SCSIZE_64                   (0x5 << 16) // (HDMA_CH) 64.\r
+#define        AT91C_HDMA_SCSIZE_128                  (0x6 << 16) // (HDMA_CH) 128.\r
+#define        AT91C_HDMA_SCSIZE_256                  (0x7 << 16) // (HDMA_CH) 256.\r
+#define AT91C_HDMA_DCSIZE     (0x7 << 20) // (HDMA_CH) Destination Chunk Transfer Size\r
+#define        AT91C_HDMA_DCSIZE_1                    (0x0 << 20) // (HDMA_CH) 1.\r
+#define        AT91C_HDMA_DCSIZE_4                    (0x1 << 20) // (HDMA_CH) 4.\r
+#define        AT91C_HDMA_DCSIZE_8                    (0x2 << 20) // (HDMA_CH) 8.\r
+#define        AT91C_HDMA_DCSIZE_16                   (0x3 << 20) // (HDMA_CH) 16.\r
+#define        AT91C_HDMA_DCSIZE_32                   (0x4 << 20) // (HDMA_CH) 32.\r
+#define        AT91C_HDMA_DCSIZE_64                   (0x5 << 20) // (HDMA_CH) 64.\r
+#define        AT91C_HDMA_DCSIZE_128                  (0x6 << 20) // (HDMA_CH) 128.\r
+#define        AT91C_HDMA_DCSIZE_256                  (0x7 << 20) // (HDMA_CH) 256.\r
+#define AT91C_HDMA_SRC_WIDTH  (0x3 << 24) // (HDMA_CH) Source Single Transfer Size\r
+#define        AT91C_HDMA_SRC_WIDTH_BYTE                 (0x0 << 24) // (HDMA_CH) BYTE.\r
+#define        AT91C_HDMA_SRC_WIDTH_HALFWORD             (0x1 << 24) // (HDMA_CH) HALF-WORD.\r
+#define        AT91C_HDMA_SRC_WIDTH_WORD                 (0x2 << 24) // (HDMA_CH) WORD.\r
+#define AT91C_HDMA_DST_WIDTH  (0x3 << 28) // (HDMA_CH) Destination Single Transfer Size\r
+#define        AT91C_HDMA_DST_WIDTH_BYTE                 (0x0 << 28) // (HDMA_CH) BYTE.\r
+#define        AT91C_HDMA_DST_WIDTH_HALFWORD             (0x1 << 28) // (HDMA_CH) HALF-WORD.\r
+#define        AT91C_HDMA_DST_WIDTH_WORD                 (0x2 << 28) // (HDMA_CH) WORD.\r
+#define AT91C_HDMA_DONE       (0x1 << 31) // (HDMA_CH) \r
+// -------- HDMA_CTRLB : (HDMA_CH Offset: 0x10)  -------- \r
+#define AT91C_HDMA_SIF        (0x3 <<  0) // (HDMA_CH) Source Interface Selection Field.\r
+#define        AT91C_HDMA_SIF_0                    (0x0) // (HDMA_CH) The Source Transfer is done via AHB-Lite Interface 0.\r
+#define        AT91C_HDMA_SIF_1                    (0x1) // (HDMA_CH) The Source Transfer is done via AHB-Lite Interface 1.\r
+#define        AT91C_HDMA_SIF_2                    (0x2) // (HDMA_CH) The Source Transfer is done via AHB-Lite Interface 2.\r
+#define        AT91C_HDMA_SIF_3                    (0x3) // (HDMA_CH) The Source Transfer is done via AHB-Lite Interface 3.\r
+#define AT91C_HDMA_DIF        (0x3 <<  4) // (HDMA_CH) Destination Interface Selection Field.\r
+#define        AT91C_HDMA_DIF_0                    (0x0 <<  4) // (HDMA_CH) The Destination Transfer is done via AHB-Lite Interface 0.\r
+#define        AT91C_HDMA_DIF_1                    (0x1 <<  4) // (HDMA_CH) The Destination Transfer is done via AHB-Lite Interface 1.\r
+#define        AT91C_HDMA_DIF_2                    (0x2 <<  4) // (HDMA_CH) The Destination Transfer is done via AHB-Lite Interface 2.\r
+#define        AT91C_HDMA_DIF_3                    (0x3 <<  4) // (HDMA_CH) The Destination Transfer is done via AHB-Lite Interface 3.\r
+#define AT91C_HDMA_SRC_PIP    (0x1 <<  8) // (HDMA_CH) Source Picture-in-Picture Mode\r
+#define        AT91C_HDMA_SRC_PIP_DISABLE              (0x0 <<  8) // (HDMA_CH) Source Picture-in-Picture mode is disabled.\r
+#define        AT91C_HDMA_SRC_PIP_ENABLE               (0x1 <<  8) // (HDMA_CH) Source Picture-in-Picture mode is enabled.\r
+#define AT91C_HDMA_DST_PIP    (0x1 << 12) // (HDMA_CH) Destination Picture-in-Picture Mode\r
+#define        AT91C_HDMA_DST_PIP_DISABLE              (0x0 << 12) // (HDMA_CH) Destination Picture-in-Picture mode is disabled.\r
+#define        AT91C_HDMA_DST_PIP_ENABLE               (0x1 << 12) // (HDMA_CH) Destination Picture-in-Picture mode is enabled.\r
+#define AT91C_HDMA_SRC_DSCR   (0x1 << 16) // (HDMA_CH) Source Buffer Descriptor Fetch operation\r
+#define        AT91C_HDMA_SRC_DSCR_FETCH_FROM_MEM       (0x0 << 16) // (HDMA_CH) Source address is updated when the descriptor is fetched from the memory.\r
+#define        AT91C_HDMA_SRC_DSCR_FETCH_DISABLE        (0x1 << 16) // (HDMA_CH) Buffer Descriptor Fetch operation is disabled for the Source.\r
+#define AT91C_HDMA_DST_DSCR   (0x1 << 20) // (HDMA_CH) Destination Buffer Descriptor operation\r
+#define        AT91C_HDMA_DST_DSCR_FETCH_FROM_MEM       (0x0 << 20) // (HDMA_CH) Destination address is updated when the descriptor is fetched from the memory.\r
+#define        AT91C_HDMA_DST_DSCR_FETCH_DISABLE        (0x1 << 20) // (HDMA_CH) Buffer Descriptor Fetch operation is disabled for the destination.\r
+#define AT91C_HDMA_FC         (0x7 << 21) // (HDMA_CH) This field defines which devices controls the size of the buffer transfer, also referred as to the Flow Controller.\r
+#define        AT91C_HDMA_FC_MEM2MEM              (0x0 << 21) // (HDMA_CH) Memory-to-Memory (DMA Controller).\r
+#define        AT91C_HDMA_FC_MEM2PER              (0x1 << 21) // (HDMA_CH) Memory-to-Peripheral (DMA Controller).\r
+#define        AT91C_HDMA_FC_PER2MEM              (0x2 << 21) // (HDMA_CH) Peripheral-to-Memory (DMA Controller).\r
+#define        AT91C_HDMA_FC_PER2PER              (0x3 << 21) // (HDMA_CH) Peripheral-to-Peripheral (DMA Controller).\r
+#define        AT91C_HDMA_FC_PER2MEM_PER          (0x4 << 21) // (HDMA_CH) Peripheral-to-Memory (Peripheral).\r
+#define        AT91C_HDMA_FC_MEM2PER_PER          (0x5 << 21) // (HDMA_CH) Memory-to-Peripheral (Peripheral).\r
+#define        AT91C_HDMA_FC_PER2PER_PER          (0x6 << 21) // (HDMA_CH) Peripheral-to-Peripheral (Source Peripheral).\r
+#define AT91C_HDMA_SRC_ADDRESS_MODE (0x3 << 24) // (HDMA_CH) Type of addressing mode\r
+#define        AT91C_HDMA_SRC_ADDRESS_MODE_INCR                 (0x0 << 24) // (HDMA_CH) Incrementing Mode.\r
+#define        AT91C_HDMA_SRC_ADDRESS_MODE_DECR                 (0x1 << 24) // (HDMA_CH) Decrementing Mode.\r
+#define        AT91C_HDMA_SRC_ADDRESS_MODE_FIXED                (0x2 << 24) // (HDMA_CH) Fixed Mode.\r
+#define AT91C_HDMA_DST_ADDRESS_MODE (0x3 << 28) // (HDMA_CH) Type of addressing mode\r
+#define        AT91C_HDMA_DST_ADDRESS_MODE_INCR                 (0x0 << 28) // (HDMA_CH) Incrementing Mode.\r
+#define        AT91C_HDMA_DST_ADDRESS_MODE_DECR                 (0x1 << 28) // (HDMA_CH) Decrementing Mode.\r
+#define        AT91C_HDMA_DST_ADDRESS_MODE_FIXED                (0x2 << 28) // (HDMA_CH) Fixed Mode.\r
+#define AT91C_HDMA_AUTO       (0x1 << 31) // (HDMA_CH) Automatic multiple buffer transfer enable\r
+#define        AT91C_HDMA_AUTO_DISABLE              (0x0 << 31) // (HDMA_CH) Automatic multiple buffer transfer is disabled.\r
+#define        AT91C_HDMA_AUTO_ENABLE               (0x1 << 31) // (HDMA_CH) Automatic multiple buffer transfer is enabled. This enables replay mode or contiguous mode when several buffers are transferred.\r
+// -------- HDMA_CFG : (HDMA_CH Offset: 0x14)  -------- \r
+#define AT91C_HDMA_SRC_PER    (0xF <<  0) // (HDMA_CH) Channel Source Request is associated with peripheral identifier coded SRC_PER handshaking interface.\r
+#define        AT91C_HDMA_SRC_PER_0                    (0x0) // (HDMA_CH) HW Handshaking Interface number 0.\r
+#define        AT91C_HDMA_SRC_PER_1                    (0x1) // (HDMA_CH) HW Handshaking Interface number 1.\r
+#define        AT91C_HDMA_SRC_PER_2                    (0x2) // (HDMA_CH) HW Handshaking Interface number 2.\r
+#define        AT91C_HDMA_SRC_PER_3                    (0x3) // (HDMA_CH) HW Handshaking Interface number 3.\r
+#define        AT91C_HDMA_SRC_PER_4                    (0x4) // (HDMA_CH) HW Handshaking Interface number 4.\r
+#define        AT91C_HDMA_SRC_PER_5                    (0x5) // (HDMA_CH) HW Handshaking Interface number 5.\r
+#define        AT91C_HDMA_SRC_PER_6                    (0x6) // (HDMA_CH) HW Handshaking Interface number 6.\r
+#define        AT91C_HDMA_SRC_PER_7                    (0x7) // (HDMA_CH) HW Handshaking Interface number 7.\r
+#define        AT91C_HDMA_SRC_PER_8                    (0x8) // (HDMA_CH) HW Handshaking Interface number 8.\r
+#define        AT91C_HDMA_SRC_PER_9                    (0x9) // (HDMA_CH) HW Handshaking Interface number 9.\r
+#define        AT91C_HDMA_SRC_PER_10                   (0xA) // (HDMA_CH) HW Handshaking Interface number 10.\r
+#define        AT91C_HDMA_SRC_PER_11                   (0xB) // (HDMA_CH) HW Handshaking Interface number 11.\r
+#define        AT91C_HDMA_SRC_PER_12                   (0xC) // (HDMA_CH) HW Handshaking Interface number 12.\r
+#define        AT91C_HDMA_SRC_PER_13                   (0xD) // (HDMA_CH) HW Handshaking Interface number 13.\r
+#define        AT91C_HDMA_SRC_PER_14                   (0xE) // (HDMA_CH) HW Handshaking Interface number 14.\r
+#define        AT91C_HDMA_SRC_PER_15                   (0xF) // (HDMA_CH) HW Handshaking Interface number 15.\r
+#define AT91C_HDMA_DST_PER    (0xF <<  4) // (HDMA_CH) Channel Destination Request is associated with peripheral identifier coded DST_PER handshaking interface.\r
+#define        AT91C_HDMA_DST_PER_0                    (0x0 <<  4) // (HDMA_CH) HW Handshaking Interface number 0.\r
+#define        AT91C_HDMA_DST_PER_1                    (0x1 <<  4) // (HDMA_CH) HW Handshaking Interface number 1.\r
+#define        AT91C_HDMA_DST_PER_2                    (0x2 <<  4) // (HDMA_CH) HW Handshaking Interface number 2.\r
+#define        AT91C_HDMA_DST_PER_3                    (0x3 <<  4) // (HDMA_CH) HW Handshaking Interface number 3.\r
+#define        AT91C_HDMA_DST_PER_4                    (0x4 <<  4) // (HDMA_CH) HW Handshaking Interface number 4.\r
+#define        AT91C_HDMA_DST_PER_5                    (0x5 <<  4) // (HDMA_CH) HW Handshaking Interface number 5.\r
+#define        AT91C_HDMA_DST_PER_6                    (0x6 <<  4) // (HDMA_CH) HW Handshaking Interface number 6.\r
+#define        AT91C_HDMA_DST_PER_7                    (0x7 <<  4) // (HDMA_CH) HW Handshaking Interface number 7.\r
+#define        AT91C_HDMA_DST_PER_8                    (0x8 <<  4) // (HDMA_CH) HW Handshaking Interface number 8.\r
+#define        AT91C_HDMA_DST_PER_9                    (0x9 <<  4) // (HDMA_CH) HW Handshaking Interface number 9.\r
+#define        AT91C_HDMA_DST_PER_10                   (0xA <<  4) // (HDMA_CH) HW Handshaking Interface number 10.\r
+#define        AT91C_HDMA_DST_PER_11                   (0xB <<  4) // (HDMA_CH) HW Handshaking Interface number 11.\r
+#define        AT91C_HDMA_DST_PER_12                   (0xC <<  4) // (HDMA_CH) HW Handshaking Interface number 12.\r
+#define        AT91C_HDMA_DST_PER_13                   (0xD <<  4) // (HDMA_CH) HW Handshaking Interface number 13.\r
+#define        AT91C_HDMA_DST_PER_14                   (0xE <<  4) // (HDMA_CH) HW Handshaking Interface number 14.\r
+#define        AT91C_HDMA_DST_PER_15                   (0xF <<  4) // (HDMA_CH) HW Handshaking Interface number 15.\r
+#define AT91C_HDMA_SRC_REP    (0x1 <<  8) // (HDMA_CH) Source Replay Mode\r
+#define        AT91C_HDMA_SRC_REP_CONTIGUOUS_ADDR      (0x0 <<  8) // (HDMA_CH) When automatic mode is activated, source address is contiguous between two buffers.\r
+#define        AT91C_HDMA_SRC_REP_RELOAD_ADDR          (0x1 <<  8) // (HDMA_CH) When automatic mode is activated, the source address and the control register are reloaded from previous transfer..\r
+#define AT91C_HDMA_SRC_H2SEL  (0x1 <<  9) // (HDMA_CH) Source Handshaking Mode\r
+#define        AT91C_HDMA_SRC_H2SEL_SW                   (0x0 <<  9) // (HDMA_CH) Software handshaking interface is used to trigger a transfer request.\r
+#define        AT91C_HDMA_SRC_H2SEL_HW                   (0x1 <<  9) // (HDMA_CH) Hardware handshaking interface is used to trigger a transfer request.\r
+#define AT91C_HDMA_DST_REP    (0x1 << 12) // (HDMA_CH) Destination Replay Mode\r
+#define        AT91C_HDMA_DST_REP_CONTIGUOUS_ADDR      (0x0 << 12) // (HDMA_CH) When automatic mode is activated, destination address is contiguous between two buffers.\r
+#define        AT91C_HDMA_DST_REP_RELOAD_ADDR          (0x1 << 12) // (HDMA_CH) When automatic mode is activated, the destination address and the control register are reloaded from previous transfer..\r
+#define AT91C_HDMA_DST_H2SEL  (0x1 << 13) // (HDMA_CH) Destination Handshaking Mode\r
+#define        AT91C_HDMA_DST_H2SEL_SW                   (0x0 << 13) // (HDMA_CH) Software handshaking interface is used to trigger a transfer request.\r
+#define        AT91C_HDMA_DST_H2SEL_HW                   (0x1 << 13) // (HDMA_CH) Hardware handshaking interface is used to trigger a transfer request.\r
+#define AT91C_HDMA_SOD        (0x1 << 16) // (HDMA_CH) STOP ON DONE\r
+#define        AT91C_HDMA_SOD_DISABLE              (0x0 << 16) // (HDMA_CH) STOP ON DONE disabled, the descriptor fetch operation ignores DONE Field of CTRLA register.\r
+#define        AT91C_HDMA_SOD_ENABLE               (0x1 << 16) // (HDMA_CH) STOP ON DONE activated, the DMAC module is automatically disabled if DONE FIELD is set to 1.\r
+#define AT91C_HDMA_LOCK_IF    (0x1 << 20) // (HDMA_CH) Interface Lock\r
+#define        AT91C_HDMA_LOCK_IF_DISABLE              (0x0 << 20) // (HDMA_CH) Interface Lock capability is disabled.\r
+#define        AT91C_HDMA_LOCK_IF_ENABLE               (0x1 << 20) // (HDMA_CH) Interface Lock capability is enabled.\r
+#define AT91C_HDMA_LOCK_B     (0x1 << 21) // (HDMA_CH) AHB Bus Lock\r
+#define        AT91C_HDMA_LOCK_B_DISABLE              (0x0 << 21) // (HDMA_CH) AHB Bus Locking capability is disabled.\r
+#define        AT91C_HDMA_LOCK_B_ENABLE               (0x1 << 21) // (HDMA_CH) AHB Bus Locking capability is enabled.\r
+#define AT91C_HDMA_LOCK_IF_L  (0x1 << 22) // (HDMA_CH) Master Interface Arbiter Lock\r
+#define        AT91C_HDMA_LOCK_IF_L_CHUNK                (0x0 << 22) // (HDMA_CH) The Master Interface Arbiter is locked by the channel x for a chunk transfer.\r
+#define        AT91C_HDMA_LOCK_IF_L_BUFFER               (0x1 << 22) // (HDMA_CH) The Master Interface Arbiter is locked by the channel x for a buffer transfer.\r
+#define AT91C_HDMA_AHB_PROT   (0x7 << 24) // (HDMA_CH) AHB Prot\r
+#define AT91C_HDMA_FIFOCFG    (0x3 << 28) // (HDMA_CH) FIFO Request Configuration\r
+#define        AT91C_HDMA_FIFOCFG_LARGESTBURST         (0x0 << 28) // (HDMA_CH) The largest defined length AHB burst is performed on the destination AHB interface.\r
+#define        AT91C_HDMA_FIFOCFG_HALFFIFO             (0x1 << 28) // (HDMA_CH) When half fifo size is available/filled a source/destination request is serviced.\r
+#define        AT91C_HDMA_FIFOCFG_ENOUGHSPACE          (0x2 << 28) // (HDMA_CH) When there is enough space/data available to perfom a single AHB access then the request is serviced.\r
+// -------- HDMA_SPIP : (HDMA_CH Offset: 0x18)  -------- \r
+#define AT91C_SPIP_HOLE       (0xFFFF <<  0) // (HDMA_CH) This field indicates the value to add to the address when the programmable boundary has been reached.\r
+#define AT91C_SPIP_BOUNDARY   (0x3FF << 16) // (HDMA_CH) This field indicates the number of source transfers to perform before the automatic address increment operation.\r
+// -------- HDMA_DPIP : (HDMA_CH Offset: 0x1c)  -------- \r
+#define AT91C_DPIP_HOLE       (0xFFFF <<  0) // (HDMA_CH) This field indicates the value to add to the address when the programmable boundary has been reached.\r
+#define AT91C_DPIP_BOUNDARY   (0x3FF << 16) // (HDMA_CH) This field indicates the number of source transfers to perform before the automatic address increment operation.\r
+// -------- HDMA_BDSCR : (HDMA_CH Offset: 0x20)  -------- \r
+// -------- HDMA_CADDR : (HDMA_CH Offset: 0x24)  -------- \r
+\r
+// *****************************************************************************\r
+//              SOFTWARE API DEFINITION  FOR HDMA controller\r
+// *****************************************************************************\r
+#ifndef __ASSEMBLY__\r
+typedef struct _AT91S_HDMA {\r
+       AT91_REG         HDMA_GCFG;     // HDMA Global Configuration Register\r
+       AT91_REG         HDMA_EN;       // HDMA Controller Enable Register\r
+       AT91_REG         HDMA_SREQ;     // HDMA Software Single Request Register\r
+       AT91_REG         HDMA_CREQ;     // HDMA Software Chunk Transfer Request Register\r
+       AT91_REG         HDMA_LAST;     // HDMA Software Last Transfer Flag Register\r
+       AT91_REG         HDMA_SYNC;     // HDMA Request Synchronization Register\r
+       AT91_REG         HDMA_EBCIER;   // HDMA Error, Chained Buffer transfer completed and Buffer transfer completed Interrupt Enable register\r
+       AT91_REG         HDMA_EBCIDR;   // HDMA Error, Chained Buffer transfer completed and Buffer transfer completed Interrupt Disable register\r
+       AT91_REG         HDMA_EBCIMR;   // HDMA Error, Chained Buffer transfer completed and Buffer transfer completed Mask Register\r
+       AT91_REG         HDMA_EBCISR;   // HDMA Error, Chained Buffer transfer completed and Buffer transfer completed Status Register\r
+       AT91_REG         HDMA_CHER;     // HDMA Channel Handler Enable Register\r
+       AT91_REG         HDMA_CHDR;     // HDMA Channel Handler Disable Register\r
+       AT91_REG         HDMA_CHSR;     // HDMA Channel Handler Status Register\r
+       AT91_REG         HDMA_RSVD0;    // HDMA Reserved\r
+       AT91_REG         HDMA_RSVD1;    // HDMA Reserved\r
+       AT91S_HDMA_CH    HDMA_CH[4];    // HDMA Channel structure\r
+       AT91_REG         Reserved0[68];         // \r
+       AT91_REG         HDMA_ADDRSIZE;         // HDMA ADDRSIZE REGISTER \r
+       AT91_REG         HDMA_IPNAME1;  // HDMA IPNAME1 REGISTER \r
+       AT91_REG         HDMA_IPNAME2;  // HDMA IPNAME2 REGISTER \r
+       AT91_REG         HDMA_FEATURES;         // HDMA FEATURES REGISTER \r
+       AT91_REG         HDMA_VER;      // HDMA VERSION REGISTER \r
+} AT91S_HDMA, *AT91PS_HDMA;\r
+#else\r
+#define HDMA_GCFG       (AT91_CAST(AT91_REG *)         0x00000000) // (HDMA_GCFG) HDMA Global Configuration Register\r
+#define HDMA_EN         (AT91_CAST(AT91_REG *)         0x00000004) // (HDMA_EN) HDMA Controller Enable Register\r
+#define HDMA_SREQ       (AT91_CAST(AT91_REG *)         0x00000008) // (HDMA_SREQ) HDMA Software Single Request Register\r
+#define HDMA_CREQ       (AT91_CAST(AT91_REG *)         0x0000000C) // (HDMA_CREQ) HDMA Software Chunk Transfer Request Register\r
+#define HDMA_LAST       (AT91_CAST(AT91_REG *)         0x00000010) // (HDMA_LAST) HDMA Software Last Transfer Flag Register\r
+#define HDMA_SYNC       (AT91_CAST(AT91_REG *)         0x00000014) // (HDMA_SYNC) HDMA Request Synchronization Register\r
+#define HDMA_EBCIER     (AT91_CAST(AT91_REG *)         0x00000018) // (HDMA_EBCIER) HDMA Error, Chained Buffer transfer completed and Buffer transfer completed Interrupt Enable register\r
+#define HDMA_EBCIDR     (AT91_CAST(AT91_REG *)         0x0000001C) // (HDMA_EBCIDR) HDMA Error, Chained Buffer transfer completed and Buffer transfer completed Interrupt Disable register\r
+#define HDMA_EBCIMR     (AT91_CAST(AT91_REG *)         0x00000020) // (HDMA_EBCIMR) HDMA Error, Chained Buffer transfer completed and Buffer transfer completed Mask Register\r
+#define HDMA_EBCISR     (AT91_CAST(AT91_REG *)         0x00000024) // (HDMA_EBCISR) HDMA Error, Chained Buffer transfer completed and Buffer transfer completed Status Register\r
+#define HDMA_CHER       (AT91_CAST(AT91_REG *)         0x00000028) // (HDMA_CHER) HDMA Channel Handler Enable Register\r
+#define HDMA_CHDR       (AT91_CAST(AT91_REG *)         0x0000002C) // (HDMA_CHDR) HDMA Channel Handler Disable Register\r
+#define HDMA_CHSR       (AT91_CAST(AT91_REG *)         0x00000030) // (HDMA_CHSR) HDMA Channel Handler Status Register\r
+#define HDMA_RSVD0      (AT91_CAST(AT91_REG *)         0x00000034) // (HDMA_RSVD0) HDMA Reserved\r
+#define HDMA_RSVD1      (AT91_CAST(AT91_REG *)         0x00000038) // (HDMA_RSVD1) HDMA Reserved\r
+#define HDMA_ADDRSIZE   (AT91_CAST(AT91_REG *)         0x000001EC) // (HDMA_ADDRSIZE) HDMA ADDRSIZE REGISTER \r
+#define HDMA_IPNAME1    (AT91_CAST(AT91_REG *)         0x000001F0) // (HDMA_IPNAME1) HDMA IPNAME1 REGISTER \r
+#define HDMA_IPNAME2    (AT91_CAST(AT91_REG *)         0x000001F4) // (HDMA_IPNAME2) HDMA IPNAME2 REGISTER \r
+#define HDMA_FEATURES   (AT91_CAST(AT91_REG *)         0x000001F8) // (HDMA_FEATURES) HDMA FEATURES REGISTER \r
+#define HDMA_VER        (AT91_CAST(AT91_REG *)         0x000001FC) // (HDMA_VER) HDMA VERSION REGISTER \r
+\r
+#endif\r
+// -------- HDMA_GCFG : (HDMA Offset: 0x0)  -------- \r
+#define AT91C_HDMA_IF0_BIGEND (0x1 <<  0) // (HDMA) AHB-Lite Interface 0 endian mode.\r
+#define        AT91C_HDMA_IF0_BIGEND_IS_LITTLE_ENDIAN     (0x0) // (HDMA) AHB-Lite Interface 0 is little endian.\r
+#define        AT91C_HDMA_IF0_BIGEND_IS_BIG_ENDIAN        (0x1) // (HDMA) AHB-Lite Interface 0 is big endian.\r
+#define AT91C_HDMA_IF1_BIGEND (0x1 <<  1) // (HDMA) AHB-Lite Interface 1 endian mode.\r
+#define        AT91C_HDMA_IF1_BIGEND_IS_LITTLE_ENDIAN     (0x0 <<  1) // (HDMA) AHB-Lite Interface 1 is little endian.\r
+#define        AT91C_HDMA_IF1_BIGEND_IS_BIG_ENDIAN        (0x1 <<  1) // (HDMA) AHB-Lite Interface 1 is big endian.\r
+#define AT91C_HDMA_IF2_BIGEND (0x1 <<  2) // (HDMA) AHB-Lite Interface 2 endian mode.\r
+#define        AT91C_HDMA_IF2_BIGEND_IS_LITTLE_ENDIAN     (0x0 <<  2) // (HDMA) AHB-Lite Interface 2 is little endian.\r
+#define        AT91C_HDMA_IF2_BIGEND_IS_BIG_ENDIAN        (0x1 <<  2) // (HDMA) AHB-Lite Interface 2 is big endian.\r
+#define AT91C_HDMA_IF3_BIGEND (0x1 <<  3) // (HDMA) AHB-Lite Interface 3 endian mode.\r
+#define        AT91C_HDMA_IF3_BIGEND_IS_LITTLE_ENDIAN     (0x0 <<  3) // (HDMA) AHB-Lite Interface 3 is little endian.\r
+#define        AT91C_HDMA_IF3_BIGEND_IS_BIG_ENDIAN        (0x1 <<  3) // (HDMA) AHB-Lite Interface 3 is big endian.\r
+#define AT91C_HDMA_ARB_CFG    (0x1 <<  4) // (HDMA) Arbiter mode.\r
+#define        AT91C_HDMA_ARB_CFG_FIXED                (0x0 <<  4) // (HDMA) Fixed priority arbiter.\r
+#define        AT91C_HDMA_ARB_CFG_ROUND_ROBIN          (0x1 <<  4) // (HDMA) Modified round robin arbiter.\r
+// -------- HDMA_EN : (HDMA Offset: 0x4)  -------- \r
+#define AT91C_HDMA_ENABLE     (0x1 <<  0) // (HDMA) \r
+#define        AT91C_HDMA_ENABLE_DISABLE              (0x0) // (HDMA) Disables HDMA.\r
+#define        AT91C_HDMA_ENABLE_ENABLE               (0x1) // (HDMA) Enables HDMA.\r
+// -------- HDMA_SREQ : (HDMA Offset: 0x8)  -------- \r
+#define AT91C_HDMA_SSREQ0     (0x1 <<  0) // (HDMA) Request a source single transfer on channel 0\r
+#define        AT91C_HDMA_SSREQ0_0                    (0x0) // (HDMA) No effect.\r
+#define        AT91C_HDMA_SSREQ0_1                    (0x1) // (HDMA) Request a source single transfer on channel 0.\r
+#define AT91C_HDMA_DSREQ0     (0x1 <<  1) // (HDMA) Request a destination single transfer on channel 0\r
+#define        AT91C_HDMA_DSREQ0_0                    (0x0 <<  1) // (HDMA) No effect.\r
+#define        AT91C_HDMA_DSREQ0_1                    (0x1 <<  1) // (HDMA) Request a destination single transfer on channel 0.\r
+#define AT91C_HDMA_SSREQ1     (0x1 <<  2) // (HDMA) Request a source single transfer on channel 1\r
+#define        AT91C_HDMA_SSREQ1_0                    (0x0 <<  2) // (HDMA) No effect.\r
+#define        AT91C_HDMA_SSREQ1_1                    (0x1 <<  2) // (HDMA) Request a source single transfer on channel 1.\r
+#define AT91C_HDMA_DSREQ1     (0x1 <<  3) // (HDMA) Request a destination single transfer on channel 1\r
+#define        AT91C_HDMA_DSREQ1_0                    (0x0 <<  3) // (HDMA) No effect.\r
+#define        AT91C_HDMA_DSREQ1_1                    (0x1 <<  3) // (HDMA) Request a destination single transfer on channel 1.\r
+#define AT91C_HDMA_SSREQ2     (0x1 <<  4) // (HDMA) Request a source single transfer on channel 2\r
+#define        AT91C_HDMA_SSREQ2_0                    (0x0 <<  4) // (HDMA) No effect.\r
+#define        AT91C_HDMA_SSREQ2_1                    (0x1 <<  4) // (HDMA) Request a source single transfer on channel 2.\r
+#define AT91C_HDMA_DSREQ2     (0x1 <<  5) // (HDMA) Request a destination single transfer on channel 2\r
+#define        AT91C_HDMA_DSREQ2_0                    (0x0 <<  5) // (HDMA) No effect.\r
+#define        AT91C_HDMA_DSREQ2_1                    (0x1 <<  5) // (HDMA) Request a destination single transfer on channel 2.\r
+#define AT91C_HDMA_SSREQ3     (0x1 <<  6) // (HDMA) Request a source single transfer on channel 3\r
+#define        AT91C_HDMA_SSREQ3_0                    (0x0 <<  6) // (HDMA) No effect.\r
+#define        AT91C_HDMA_SSREQ3_1                    (0x1 <<  6) // (HDMA) Request a source single transfer on channel 3.\r
+#define AT91C_HDMA_DSREQ3     (0x1 <<  7) // (HDMA) Request a destination single transfer on channel 3\r
+#define        AT91C_HDMA_DSREQ3_0                    (0x0 <<  7) // (HDMA) No effect.\r
+#define        AT91C_HDMA_DSREQ3_1                    (0x1 <<  7) // (HDMA) Request a destination single transfer on channel 3.\r
+#define AT91C_HDMA_SSREQ4     (0x1 <<  8) // (HDMA) Request a source single transfer on channel 4\r
+#define        AT91C_HDMA_SSREQ4_0                    (0x0 <<  8) // (HDMA) No effect.\r
+#define        AT91C_HDMA_SSREQ4_1                    (0x1 <<  8) // (HDMA) Request a source single transfer on channel 4.\r
+#define AT91C_HDMA_DSREQ4     (0x1 <<  9) // (HDMA) Request a destination single transfer on channel 4\r
+#define        AT91C_HDMA_DSREQ4_0                    (0x0 <<  9) // (HDMA) No effect.\r
+#define        AT91C_HDMA_DSREQ4_1                    (0x1 <<  9) // (HDMA) Request a destination single transfer on channel 4.\r
+#define AT91C_HDMA_SSREQ5     (0x1 << 10) // (HDMA) Request a source single transfer on channel 5\r
+#define        AT91C_HDMA_SSREQ5_0                    (0x0 << 10) // (HDMA) No effect.\r
+#define        AT91C_HDMA_SSREQ5_1                    (0x1 << 10) // (HDMA) Request a source single transfer on channel 5.\r
+#define AT91C_HDMA_DSREQ6     (0x1 << 11) // (HDMA) Request a destination single transfer on channel 5\r
+#define        AT91C_HDMA_DSREQ6_0                    (0x0 << 11) // (HDMA) No effect.\r
+#define        AT91C_HDMA_DSREQ6_1                    (0x1 << 11) // (HDMA) Request a destination single transfer on channel 5.\r
+#define AT91C_HDMA_SSREQ6     (0x1 << 12) // (HDMA) Request a source single transfer on channel 6\r
+#define        AT91C_HDMA_SSREQ6_0                    (0x0 << 12) // (HDMA) No effect.\r
+#define        AT91C_HDMA_SSREQ6_1                    (0x1 << 12) // (HDMA) Request a source single transfer on channel 6.\r
+#define AT91C_HDMA_SSREQ7     (0x1 << 14) // (HDMA) Request a source single transfer on channel 7\r
+#define        AT91C_HDMA_SSREQ7_0                    (0x0 << 14) // (HDMA) No effect.\r
+#define        AT91C_HDMA_SSREQ7_1                    (0x1 << 14) // (HDMA) Request a source single transfer on channel 7.\r
+#define AT91C_HDMA_DSREQ7     (0x1 << 15) // (HDMA) Request a destination single transfer on channel 7\r
+#define        AT91C_HDMA_DSREQ7_0                    (0x0 << 15) // (HDMA) No effect.\r
+#define        AT91C_HDMA_DSREQ7_1                    (0x1 << 15) // (HDMA) Request a destination single transfer on channel 7.\r
+// -------- HDMA_CREQ : (HDMA Offset: 0xc)  -------- \r
+#define AT91C_HDMA_SCREQ0     (0x1 <<  0) // (HDMA) Request a source chunk transfer on channel 0\r
+#define        AT91C_HDMA_SCREQ0_0                    (0x0) // (HDMA) No effect.\r
+#define        AT91C_HDMA_SCREQ0_1                    (0x1) // (HDMA) Request a source chunk transfer on channel 0.\r
+#define AT91C_HDMA_DCREQ0     (0x1 <<  1) // (HDMA) Request a destination chunk transfer on channel 0\r
+#define        AT91C_HDMA_DCREQ0_0                    (0x0 <<  1) // (HDMA) No effect.\r
+#define        AT91C_HDMA_DCREQ0_1                    (0x1 <<  1) // (HDMA) Request a destination chunk transfer on channel 0.\r
+#define AT91C_HDMA_SCREQ1     (0x1 <<  2) // (HDMA) Request a source chunk transfer on channel 1\r
+#define        AT91C_HDMA_SCREQ1_0                    (0x0 <<  2) // (HDMA) No effect.\r
+#define        AT91C_HDMA_SCREQ1_1                    (0x1 <<  2) // (HDMA) Request a source chunk transfer on channel 1.\r
+#define AT91C_HDMA_DCREQ1     (0x1 <<  3) // (HDMA) Request a destination chunk transfer on channel 1\r
+#define        AT91C_HDMA_DCREQ1_0                    (0x0 <<  3) // (HDMA) No effect.\r
+#define        AT91C_HDMA_DCREQ1_1                    (0x1 <<  3) // (HDMA) Request a destination chunk transfer on channel 1.\r
+#define AT91C_HDMA_SCREQ2     (0x1 <<  4) // (HDMA) Request a source chunk transfer on channel 2\r
+#define        AT91C_HDMA_SCREQ2_0                    (0x0 <<  4) // (HDMA) No effect.\r
+#define        AT91C_HDMA_SCREQ2_1                    (0x1 <<  4) // (HDMA) Request a source chunk transfer on channel 2.\r
+#define AT91C_HDMA_DCREQ2     (0x1 <<  5) // (HDMA) Request a destination chunk transfer on channel 2\r
+#define        AT91C_HDMA_DCREQ2_0                    (0x0 <<  5) // (HDMA) No effect.\r
+#define        AT91C_HDMA_DCREQ2_1                    (0x1 <<  5) // (HDMA) Request a destination chunk transfer on channel 2.\r
+#define AT91C_HDMA_SCREQ3     (0x1 <<  6) // (HDMA) Request a source chunk transfer on channel 3\r
+#define        AT91C_HDMA_SCREQ3_0                    (0x0 <<  6) // (HDMA) No effect.\r
+#define        AT91C_HDMA_SCREQ3_1                    (0x1 <<  6) // (HDMA) Request a source chunk transfer on channel 3.\r
+#define AT91C_HDMA_DCREQ3     (0x1 <<  7) // (HDMA) Request a destination chunk transfer on channel 3\r
+#define        AT91C_HDMA_DCREQ3_0                    (0x0 <<  7) // (HDMA) No effect.\r
+#define        AT91C_HDMA_DCREQ3_1                    (0x1 <<  7) // (HDMA) Request a destination chunk transfer on channel 3.\r
+#define AT91C_HDMA_SCREQ4     (0x1 <<  8) // (HDMA) Request a source chunk transfer on channel 4\r
+#define        AT91C_HDMA_SCREQ4_0                    (0x0 <<  8) // (HDMA) No effect.\r
+#define        AT91C_HDMA_SCREQ4_1                    (0x1 <<  8) // (HDMA) Request a source chunk transfer on channel 4.\r
+#define AT91C_HDMA_DCREQ4     (0x1 <<  9) // (HDMA) Request a destination chunk transfer on channel 4\r
+#define        AT91C_HDMA_DCREQ4_0                    (0x0 <<  9) // (HDMA) No effect.\r
+#define        AT91C_HDMA_DCREQ4_1                    (0x1 <<  9) // (HDMA) Request a destination chunk transfer on channel 4.\r
+#define AT91C_HDMA_SCREQ5     (0x1 << 10) // (HDMA) Request a source chunk transfer on channel 5\r
+#define        AT91C_HDMA_SCREQ5_0                    (0x0 << 10) // (HDMA) No effect.\r
+#define        AT91C_HDMA_SCREQ5_1                    (0x1 << 10) // (HDMA) Request a source chunk transfer on channel 5.\r
+#define AT91C_HDMA_DCREQ6     (0x1 << 11) // (HDMA) Request a destination chunk transfer on channel 5\r
+#define        AT91C_HDMA_DCREQ6_0                    (0x0 << 11) // (HDMA) No effect.\r
+#define        AT91C_HDMA_DCREQ6_1                    (0x1 << 11) // (HDMA) Request a destination chunk transfer on channel 5.\r
+#define AT91C_HDMA_SCREQ6     (0x1 << 12) // (HDMA) Request a source chunk transfer on channel 6\r
+#define        AT91C_HDMA_SCREQ6_0                    (0x0 << 12) // (HDMA) No effect.\r
+#define        AT91C_HDMA_SCREQ6_1                    (0x1 << 12) // (HDMA) Request a source chunk transfer on channel 6.\r
+#define AT91C_HDMA_SCREQ7     (0x1 << 14) // (HDMA) Request a source chunk transfer on channel 7\r
+#define        AT91C_HDMA_SCREQ7_0                    (0x0 << 14) // (HDMA) No effect.\r
+#define        AT91C_HDMA_SCREQ7_1                    (0x1 << 14) // (HDMA) Request a source chunk transfer on channel 7.\r
+#define AT91C_HDMA_DCREQ7     (0x1 << 15) // (HDMA) Request a destination chunk transfer on channel 7\r
+#define        AT91C_HDMA_DCREQ7_0                    (0x0 << 15) // (HDMA) No effect.\r
+#define        AT91C_HDMA_DCREQ7_1                    (0x1 << 15) // (HDMA) Request a destination chunk transfer on channel 7.\r
+// -------- HDMA_LAST : (HDMA Offset: 0x10)  -------- \r
+#define AT91C_HDMA_SLAST0     (0x1 <<  0) // (HDMA) Indicates that this source request is the last transfer of the buffer on channel 0\r
+#define        AT91C_HDMA_SLAST0_0                    (0x0) // (HDMA) No effect.\r
+#define        AT91C_HDMA_SLAST0_1                    (0x1) // (HDMA) Writing one to SLASTx prior to writing one to SSREQx or SCREQx indicates that this source request is the last transfer of the buffer on channel 0.\r
+#define AT91C_HDMA_DLAST0     (0x1 <<  1) // (HDMA) Indicates that this destination request is the last transfer of the buffer on channel 0\r
+#define        AT91C_HDMA_DLAST0_0                    (0x0 <<  1) // (HDMA) No effect.\r
+#define        AT91C_HDMA_DLAST0_1                    (0x1 <<  1) // (HDMA) Writing one to DLASTx prior to writing one to DSREQx or DCREQx indicates that this destination request is the last transfer of the buffer on channel 0.\r
+#define AT91C_HDMA_SLAST1     (0x1 <<  2) // (HDMA) Indicates that this source request is the last transfer of the buffer on channel 1\r
+#define        AT91C_HDMA_SLAST1_0                    (0x0 <<  2) // (HDMA) No effect.\r
+#define        AT91C_HDMA_SLAST1_1                    (0x1 <<  2) // (HDMA) Writing one to SLASTx prior to writing one to SSREQx or SCREQx indicates that this source request is the last transfer of the buffer on channel 1.\r
+#define AT91C_HDMA_DLAST1     (0x1 <<  3) // (HDMA) Indicates that this destination request is the last transfer of the buffer on channel 1\r
+#define        AT91C_HDMA_DLAST1_0                    (0x0 <<  3) // (HDMA) No effect.\r
+#define        AT91C_HDMA_DLAST1_1                    (0x1 <<  3) // (HDMA) Writing one to DLASTx prior to writing one to DSREQx or DCREQx indicates that this destination request is the last transfer of the buffer on channel 1.\r
+#define AT91C_HDMA_SLAST2     (0x1 <<  4) // (HDMA) Indicates that this source request is the last transfer of the buffer on channel 2\r
+#define        AT91C_HDMA_SLAST2_0                    (0x0 <<  4) // (HDMA) No effect.\r
+#define        AT91C_HDMA_SLAST2_1                    (0x1 <<  4) // (HDMA) Writing one to SLASTx prior to writing one to SSREQx or SCREQx indicates that this source request is the last transfer of the buffer on channel 2.\r
+#define AT91C_HDMA_DLAST2     (0x1 <<  5) // (HDMA) Indicates that this destination request is the last transfer of the buffer on channel 2\r
+#define        AT91C_HDMA_DLAST2_0                    (0x0 <<  5) // (HDMA) No effect.\r
+#define        AT91C_HDMA_DLAST2_1                    (0x1 <<  5) // (HDMA) Writing one to DLASTx prior to writing one to DSREQx or DCREQx indicates that this destination request is the last transfer of the buffer on channel 2.\r
+#define AT91C_HDMA_SLAST3     (0x1 <<  6) // (HDMA) Indicates that this source request is the last transfer of the buffer on channel 3\r
+#define        AT91C_HDMA_SLAST3_0                    (0x0 <<  6) // (HDMA) No effect.\r
+#define        AT91C_HDMA_SLAST3_1                    (0x1 <<  6) // (HDMA) Writing one to SLASTx prior to writing one to SSREQx or SCREQx indicates that this source request is the last transfer of the buffer on channel 3.\r
+#define AT91C_HDMA_DLAST3     (0x1 <<  7) // (HDMA) Indicates that this destination request is the last transfer of the buffer on channel 3\r
+#define        AT91C_HDMA_DLAST3_0                    (0x0 <<  7) // (HDMA) No effect.\r
+#define        AT91C_HDMA_DLAST3_1                    (0x1 <<  7) // (HDMA) Writing one to DLASTx prior to writing one to DSREQx or DCREQx indicates that this destination request is the last transfer of the buffer on channel 3.\r
+#define AT91C_HDMA_SLAST4     (0x1 <<  8) // (HDMA) Indicates that this source request is the last transfer of the buffer on channel 4\r
+#define        AT91C_HDMA_SLAST4_0                    (0x0 <<  8) // (HDMA) No effect.\r
+#define        AT91C_HDMA_SLAST4_1                    (0x1 <<  8) // (HDMA) Writing one to SLASTx prior to writing one to SSREQx or SCREQx indicates that this source request is the last transfer of the buffer on channel 4.\r
+#define AT91C_HDMA_DLAST4     (0x1 <<  9) // (HDMA) Indicates that this destination request is the last transfer of the buffer on channel 4\r
+#define        AT91C_HDMA_DLAST4_0                    (0x0 <<  9) // (HDMA) No effect.\r
+#define        AT91C_HDMA_DLAST4_1                    (0x1 <<  9) // (HDMA) Writing one to DLASTx prior to writing one to DSREQx or DCREQx indicates that this destination request is the last transfer of the buffer on channel 4.\r
+#define AT91C_HDMA_SLAST5     (0x1 << 10) // (HDMA) Indicates that this source request is the last transfer of the buffer on channel 5\r
+#define        AT91C_HDMA_SLAST5_0                    (0x0 << 10) // (HDMA) No effect.\r
+#define        AT91C_HDMA_SLAST5_1                    (0x1 << 10) // (HDMA) Writing one to SLASTx prior to writing one to SSREQx or SCREQx indicates that this source request is the last transfer of the buffer on channel 5.\r
+#define AT91C_HDMA_DLAST6     (0x1 << 11) // (HDMA) Indicates that this destination request is the last transfer of the buffer on channel 5\r
+#define        AT91C_HDMA_DLAST6_0                    (0x0 << 11) // (HDMA) No effect.\r
+#define        AT91C_HDMA_DLAST6_1                    (0x1 << 11) // (HDMA) Writing one to DLASTx prior to writing one to DSREQx or DCREQx indicates that this destination request is the last transfer of the buffer on channel 5.\r
+#define AT91C_HDMA_SLAST6     (0x1 << 12) // (HDMA) Indicates that this source request is the last transfer of the buffer on channel 6\r
+#define        AT91C_HDMA_SLAST6_0                    (0x0 << 12) // (HDMA) No effect.\r
+#define        AT91C_HDMA_SLAST6_1                    (0x1 << 12) // (HDMA) Writing one to SLASTx prior to writing one to SSREQx or SCREQx indicates that this source request is the last transfer of the buffer on channel 6.\r
+#define AT91C_HDMA_SLAST7     (0x1 << 14) // (HDMA) Indicates that this source request is the last transfer of the buffer on channel 7\r
+#define        AT91C_HDMA_SLAST7_0                    (0x0 << 14) // (HDMA) No effect.\r
+#define        AT91C_HDMA_SLAST7_1                    (0x1 << 14) // (HDMA) Writing one to SLASTx prior to writing one to SSREQx or SCREQx indicates that this source request is the last transfer of the buffer on channel 7.\r
+#define AT91C_HDMA_DLAST7     (0x1 << 15) // (HDMA) Indicates that this destination request is the last transfer of the buffer on channel 7\r
+#define        AT91C_HDMA_DLAST7_0                    (0x0 << 15) // (HDMA) No effect.\r
+#define        AT91C_HDMA_DLAST7_1                    (0x1 << 15) // (HDMA) Writing one to DLASTx prior to writing one to DSREQx or DCREQx indicates that this destination request is the last transfer of the buffer on channel 7.\r
+// -------- HDMA_SYNC : (HDMA Offset: 0x14)  -------- \r
+#define AT91C_SYNC_REQ        (0xFFFF <<  0) // (HDMA) \r
+// -------- HDMA_EBCIER : (HDMA Offset: 0x18) Buffer Transfer Completed/Chained Buffer Transfer Completed/Access Error Interrupt Enable Register -------- \r
+#define AT91C_HDMA_BTC0       (0x1 <<  0) // (HDMA) Buffer Transfer Completed Interrupt Enable/Disable/Status Register\r
+#define AT91C_HDMA_BTC1       (0x1 <<  1) // (HDMA) Buffer Transfer Completed Interrupt Enable/Disable/Status Register\r
+#define AT91C_HDMA_BTC2       (0x1 <<  2) // (HDMA) Buffer Transfer Completed Interrupt Enable/Disable/Status Register\r
+#define AT91C_HDMA_BTC3       (0x1 <<  3) // (HDMA) Buffer Transfer Completed Interrupt Enable/Disable/Status Register\r
+#define AT91C_HDMA_BTC4       (0x1 <<  4) // (HDMA) Buffer Transfer Completed Interrupt Enable/Disable/Status Register\r
+#define AT91C_HDMA_BTC5       (0x1 <<  5) // (HDMA) Buffer Transfer Completed Interrupt Enable/Disable/Status Register\r
+#define AT91C_HDMA_BTC6       (0x1 <<  6) // (HDMA) Buffer Transfer Completed Interrupt Enable/Disable/Status Register\r
+#define AT91C_HDMA_BTC7       (0x1 <<  7) // (HDMA) Buffer Transfer Completed Interrupt Enable/Disable/Status Register\r
+#define AT91C_HDMA_CBTC0      (0x1 <<  8) // (HDMA) Chained Buffer Transfer Completed Interrupt Enable/Disable/Status Register\r
+#define AT91C_HDMA_CBTC1      (0x1 <<  9) // (HDMA) Chained Buffer Transfer Completed Interrupt Enable/Disable/Status Register\r
+#define AT91C_HDMA_CBTC2      (0x1 << 10) // (HDMA) Chained Buffer Transfer Completed Interrupt Enable/Disable/Status Register\r
+#define AT91C_HDMA_CBTC3      (0x1 << 11) // (HDMA) Chained Buffer Transfer Completed Interrupt Enable/Disable/Status Register\r
+#define AT91C_HDMA_CBTC4      (0x1 << 12) // (HDMA) Chained Buffer Transfer Completed Interrupt Enable/Disable/Status Register\r
+#define AT91C_HDMA_CBTC5      (0x1 << 13) // (HDMA) Chained Buffer Transfer Completed Interrupt Enable/Disable/Status Register\r
+#define AT91C_HDMA_CBTC6      (0x1 << 14) // (HDMA) Chained Buffer Transfer Completed Interrupt Enable/Disable/Status Register\r
+#define AT91C_HDMA_CBTC7      (0x1 << 15) // (HDMA) Chained Buffer Transfer Completed Interrupt Enable/Disable/Status Register\r
+#define AT91C_HDMA_ERR0       (0x1 << 16) // (HDMA) Access HDMA_Error Interrupt Enable/Disable/Status Register\r
+#define AT91C_HDMA_ERR1       (0x1 << 17) // (HDMA) Access HDMA_Error Interrupt Enable/Disable/Status Register\r
+#define AT91C_HDMA_ERR2       (0x1 << 18) // (HDMA) Access HDMA_Error Interrupt Enable/Disable/Status Register\r
+#define AT91C_HDMA_ERR3       (0x1 << 19) // (HDMA) Access HDMA_Error Interrupt Enable/Disable/Status Register\r
+#define AT91C_HDMA_ERR4       (0x1 << 20) // (HDMA) Access HDMA_Error Interrupt Enable/Disable/Status Register\r
+#define AT91C_HDMA_ERR5       (0x1 << 21) // (HDMA) Access HDMA_Error Interrupt Enable/Disable/Status Register\r
+#define AT91C_HDMA_ERR6       (0x1 << 22) // (HDMA) Access HDMA_Error Interrupt Enable/Disable/Status Register\r
+#define AT91C_HDMA_ERR7       (0x1 << 23) // (HDMA) Access HDMA_Error Interrupt Enable/Disable/Status Register\r
+// -------- HDMA_EBCIDR : (HDMA Offset: 0x1c)  -------- \r
+// -------- HDMA_EBCIMR : (HDMA Offset: 0x20)  -------- \r
+// -------- HDMA_EBCISR : (HDMA Offset: 0x24)  -------- \r
+// -------- HDMA_CHER : (HDMA Offset: 0x28)  -------- \r
+#define AT91C_HDMA_ENA0       (0x1 <<  0) // (HDMA) When set, channel 0 enabled.\r
+#define        AT91C_HDMA_ENA0_0                    (0x0) // (HDMA) No effect.\r
+#define        AT91C_HDMA_ENA0_1                    (0x1) // (HDMA) Channel 0 enabled.\r
+#define AT91C_HDMA_ENA1       (0x1 <<  1) // (HDMA) When set, channel 1 enabled.\r
+#define        AT91C_HDMA_ENA1_0                    (0x0 <<  1) // (HDMA) No effect.\r
+#define        AT91C_HDMA_ENA1_1                    (0x1 <<  1) // (HDMA) Channel 1 enabled.\r
+#define AT91C_HDMA_ENA2       (0x1 <<  2) // (HDMA) When set, channel 2 enabled.\r
+#define        AT91C_HDMA_ENA2_0                    (0x0 <<  2) // (HDMA) No effect.\r
+#define        AT91C_HDMA_ENA2_1                    (0x1 <<  2) // (HDMA) Channel 2 enabled.\r
+#define AT91C_HDMA_ENA3       (0x1 <<  3) // (HDMA) When set, channel 3 enabled.\r
+#define        AT91C_HDMA_ENA3_0                    (0x0 <<  3) // (HDMA) No effect.\r
+#define        AT91C_HDMA_ENA3_1                    (0x1 <<  3) // (HDMA) Channel 3 enabled.\r
+#define AT91C_HDMA_ENA4       (0x1 <<  4) // (HDMA) When set, channel 4 enabled.\r
+#define        AT91C_HDMA_ENA4_0                    (0x0 <<  4) // (HDMA) No effect.\r
+#define        AT91C_HDMA_ENA4_1                    (0x1 <<  4) // (HDMA) Channel 4 enabled.\r
+#define AT91C_HDMA_ENA5       (0x1 <<  5) // (HDMA) When set, channel 5 enabled.\r
+#define        AT91C_HDMA_ENA5_0                    (0x0 <<  5) // (HDMA) No effect.\r
+#define        AT91C_HDMA_ENA5_1                    (0x1 <<  5) // (HDMA) Channel 5 enabled.\r
+#define AT91C_HDMA_ENA6       (0x1 <<  6) // (HDMA) When set, channel 6 enabled.\r
+#define        AT91C_HDMA_ENA6_0                    (0x0 <<  6) // (HDMA) No effect.\r
+#define        AT91C_HDMA_ENA6_1                    (0x1 <<  6) // (HDMA) Channel 6 enabled.\r
+#define AT91C_HDMA_ENA7       (0x1 <<  7) // (HDMA) When set, channel 7 enabled.\r
+#define        AT91C_HDMA_ENA7_0                    (0x0 <<  7) // (HDMA) No effect.\r
+#define        AT91C_HDMA_ENA7_1                    (0x1 <<  7) // (HDMA) Channel 7 enabled.\r
+#define AT91C_HDMA_SUSP0      (0x1 <<  8) // (HDMA) When set, channel 0 freezed and its current context.\r
+#define        AT91C_HDMA_SUSP0_0                    (0x0 <<  8) // (HDMA) No effect.\r
+#define        AT91C_HDMA_SUSP0_1                    (0x1 <<  8) // (HDMA) Channel 0 freezed.\r
+#define AT91C_HDMA_SUSP1      (0x1 <<  9) // (HDMA) When set, channel 1 freezed and its current context.\r
+#define        AT91C_HDMA_SUSP1_0                    (0x0 <<  9) // (HDMA) No effect.\r
+#define        AT91C_HDMA_SUSP1_1                    (0x1 <<  9) // (HDMA) Channel 1 freezed.\r
+#define AT91C_HDMA_SUSP2      (0x1 << 10) // (HDMA) When set, channel 2 freezed and its current context.\r
+#define        AT91C_HDMA_SUSP2_0                    (0x0 << 10) // (HDMA) No effect.\r
+#define        AT91C_HDMA_SUSP2_1                    (0x1 << 10) // (HDMA) Channel 2 freezed.\r
+#define AT91C_HDMA_SUSP3      (0x1 << 11) // (HDMA) When set, channel 3 freezed and its current context.\r
+#define        AT91C_HDMA_SUSP3_0                    (0x0 << 11) // (HDMA) No effect.\r
+#define        AT91C_HDMA_SUSP3_1                    (0x1 << 11) // (HDMA) Channel 3 freezed.\r
+#define AT91C_HDMA_SUSP4      (0x1 << 12) // (HDMA) When set, channel 4 freezed and its current context.\r
+#define        AT91C_HDMA_SUSP4_0                    (0x0 << 12) // (HDMA) No effect.\r
+#define        AT91C_HDMA_SUSP4_1                    (0x1 << 12) // (HDMA) Channel 4 freezed.\r
+#define AT91C_HDMA_SUSP5      (0x1 << 13) // (HDMA) When set, channel 5 freezed and its current context.\r
+#define        AT91C_HDMA_SUSP5_0                    (0x0 << 13) // (HDMA) No effect.\r
+#define        AT91C_HDMA_SUSP5_1                    (0x1 << 13) // (HDMA) Channel 5 freezed.\r
+#define AT91C_HDMA_SUSP6      (0x1 << 14) // (HDMA) When set, channel 6 freezed and its current context.\r
+#define        AT91C_HDMA_SUSP6_0                    (0x0 << 14) // (HDMA) No effect.\r
+#define        AT91C_HDMA_SUSP6_1                    (0x1 << 14) // (HDMA) Channel 6 freezed.\r
+#define AT91C_HDMA_SUSP7      (0x1 << 15) // (HDMA) When set, channel 7 freezed and its current context.\r
+#define        AT91C_HDMA_SUSP7_0                    (0x0 << 15) // (HDMA) No effect.\r
+#define        AT91C_HDMA_SUSP7_1                    (0x1 << 15) // (HDMA) Channel 7 freezed.\r
+#define AT91C_HDMA_KEEP0      (0x1 << 24) // (HDMA) When set, it resumes the channel 0 from an automatic stall state.\r
+#define        AT91C_HDMA_KEEP0_0                    (0x0 << 24) // (HDMA) No effect.\r
+#define        AT91C_HDMA_KEEP0_1                    (0x1 << 24) // (HDMA) Resumes the channel 0.\r
+#define AT91C_HDMA_KEEP1      (0x1 << 25) // (HDMA) When set, it resumes the channel 1 from an automatic stall state.\r
+#define        AT91C_HDMA_KEEP1_0                    (0x0 << 25) // (HDMA) No effect.\r
+#define        AT91C_HDMA_KEEP1_1                    (0x1 << 25) // (HDMA) Resumes the channel 1.\r
+#define AT91C_HDMA_KEEP2      (0x1 << 26) // (HDMA) When set, it resumes the channel 2 from an automatic stall state.\r
+#define        AT91C_HDMA_KEEP2_0                    (0x0 << 26) // (HDMA) No effect.\r
+#define        AT91C_HDMA_KEEP2_1                    (0x1 << 26) // (HDMA) Resumes the channel 2.\r
+#define AT91C_HDMA_KEEP3      (0x1 << 27) // (HDMA) When set, it resumes the channel 3 from an automatic stall state.\r
+#define        AT91C_HDMA_KEEP3_0                    (0x0 << 27) // (HDMA) No effect.\r
+#define        AT91C_HDMA_KEEP3_1                    (0x1 << 27) // (HDMA) Resumes the channel 3.\r
+#define AT91C_HDMA_KEEP4      (0x1 << 28) // (HDMA) When set, it resumes the channel 4 from an automatic stall state.\r
+#define        AT91C_HDMA_KEEP4_0                    (0x0 << 28) // (HDMA) No effect.\r
+#define        AT91C_HDMA_KEEP4_1                    (0x1 << 28) // (HDMA) Resumes the channel 4.\r
+#define AT91C_HDMA_KEEP5      (0x1 << 29) // (HDMA) When set, it resumes the channel 5 from an automatic stall state.\r
+#define        AT91C_HDMA_KEEP5_0                    (0x0 << 29) // (HDMA) No effect.\r
+#define        AT91C_HDMA_KEEP5_1                    (0x1 << 29) // (HDMA) Resumes the channel 5.\r
+#define AT91C_HDMA_KEEP6      (0x1 << 30) // (HDMA) When set, it resumes the channel 6 from an automatic stall state.\r
+#define        AT91C_HDMA_KEEP6_0                    (0x0 << 30) // (HDMA) No effect.\r
+#define        AT91C_HDMA_KEEP6_1                    (0x1 << 30) // (HDMA) Resumes the channel 6.\r
+#define AT91C_HDMA_KEEP7      (0x1 << 31) // (HDMA) When set, it resumes the channel 7 from an automatic stall state.\r
+#define        AT91C_HDMA_KEEP7_0                    (0x0 << 31) // (HDMA) No effect.\r
+#define        AT91C_HDMA_KEEP7_1                    (0x1 << 31) // (HDMA) Resumes the channel 7.\r
+// -------- HDMA_CHDR : (HDMA Offset: 0x2c)  -------- \r
+#define AT91C_HDMA_DIS0       (0x1 <<  0) // (HDMA) Write one to this field to disable the channel 0.\r
+#define        AT91C_HDMA_DIS0_0                    (0x0) // (HDMA) No effect.\r
+#define        AT91C_HDMA_DIS0_1                    (0x1) // (HDMA) Disables the channel 0.\r
+#define AT91C_HDMA_DIS1       (0x1 <<  1) // (HDMA) Write one to this field to disable the channel 1.\r
+#define        AT91C_HDMA_DIS1_0                    (0x0 <<  1) // (HDMA) No effect.\r
+#define        AT91C_HDMA_DIS1_1                    (0x1 <<  1) // (HDMA) Disables the channel 1.\r
+#define AT91C_HDMA_DIS2       (0x1 <<  2) // (HDMA) Write one to this field to disable the channel 2.\r
+#define        AT91C_HDMA_DIS2_0                    (0x0 <<  2) // (HDMA) No effect.\r
+#define        AT91C_HDMA_DIS2_1                    (0x1 <<  2) // (HDMA) Disables the channel 2.\r
+#define AT91C_HDMA_DIS3       (0x1 <<  3) // (HDMA) Write one to this field to disable the channel 3.\r
+#define        AT91C_HDMA_DIS3_0                    (0x0 <<  3) // (HDMA) No effect.\r
+#define        AT91C_HDMA_DIS3_1                    (0x1 <<  3) // (HDMA) Disables the channel 3.\r
+#define AT91C_HDMA_DIS4       (0x1 <<  4) // (HDMA) Write one to this field to disable the channel 4.\r
+#define        AT91C_HDMA_DIS4_0                    (0x0 <<  4) // (HDMA) No effect.\r
+#define        AT91C_HDMA_DIS4_1                    (0x1 <<  4) // (HDMA) Disables the channel 4.\r
+#define AT91C_HDMA_DIS5       (0x1 <<  5) // (HDMA) Write one to this field to disable the channel 5.\r
+#define        AT91C_HDMA_DIS5_0                    (0x0 <<  5) // (HDMA) No effect.\r
+#define        AT91C_HDMA_DIS5_1                    (0x1 <<  5) // (HDMA) Disables the channel 5.\r
+#define AT91C_HDMA_DIS6       (0x1 <<  6) // (HDMA) Write one to this field to disable the channel 6.\r
+#define        AT91C_HDMA_DIS6_0                    (0x0 <<  6) // (HDMA) No effect.\r
+#define        AT91C_HDMA_DIS6_1                    (0x1 <<  6) // (HDMA) Disables the channel 6.\r
+#define AT91C_HDMA_DIS7       (0x1 <<  7) // (HDMA) Write one to this field to disable the channel 7.\r
+#define        AT91C_HDMA_DIS7_0                    (0x0 <<  7) // (HDMA) No effect.\r
+#define        AT91C_HDMA_DIS7_1                    (0x1 <<  7) // (HDMA) Disables the channel 7.\r
+#define AT91C_HDMA_RES0       (0x1 <<  8) // (HDMA) Write one to this field to resume the channel 0 transfer restoring its context.\r
+#define        AT91C_HDMA_RES0_0                    (0x0 <<  8) // (HDMA) No effect.\r
+#define        AT91C_HDMA_RES0_1                    (0x1 <<  8) // (HDMA) Resumes the channel 0.\r
+#define AT91C_HDMA_RES1       (0x1 <<  9) // (HDMA) Write one to this field to resume the channel 1 transfer restoring its context.\r
+#define        AT91C_HDMA_RES1_0                    (0x0 <<  9) // (HDMA) No effect.\r
+#define        AT91C_HDMA_RES1_1                    (0x1 <<  9) // (HDMA) Resumes the channel 1.\r
+#define AT91C_HDMA_RES2       (0x1 << 10) // (HDMA) Write one to this field to resume the channel 2 transfer restoring its context.\r
+#define        AT91C_HDMA_RES2_0                    (0x0 << 10) // (HDMA) No effect.\r
+#define        AT91C_HDMA_RES2_1                    (0x1 << 10) // (HDMA) Resumes the channel 2.\r
+#define AT91C_HDMA_RES3       (0x1 << 11) // (HDMA) Write one to this field to resume the channel 3 transfer restoring its context.\r
+#define        AT91C_HDMA_RES3_0                    (0x0 << 11) // (HDMA) No effect.\r
+#define        AT91C_HDMA_RES3_1                    (0x1 << 11) // (HDMA) Resumes the channel 3.\r
+#define AT91C_HDMA_RES4       (0x1 << 12) // (HDMA) Write one to this field to resume the channel 4 transfer restoring its context.\r
+#define        AT91C_HDMA_RES4_0                    (0x0 << 12) // (HDMA) No effect.\r
+#define        AT91C_HDMA_RES4_1                    (0x1 << 12) // (HDMA) Resumes the channel 4.\r
+#define AT91C_HDMA_RES5       (0x1 << 13) // (HDMA) Write one to this field to resume the channel 5 transfer restoring its context.\r
+#define        AT91C_HDMA_RES5_0                    (0x0 << 13) // (HDMA) No effect.\r
+#define        AT91C_HDMA_RES5_1                    (0x1 << 13) // (HDMA) Resumes the channel 5.\r
+#define AT91C_HDMA_RES6       (0x1 << 14) // (HDMA) Write one to this field to resume the channel 6 transfer restoring its context.\r
+#define        AT91C_HDMA_RES6_0                    (0x0 << 14) // (HDMA) No effect.\r
+#define        AT91C_HDMA_RES6_1                    (0x1 << 14) // (HDMA) Resumes the channel 6.\r
+#define AT91C_HDMA_RES7       (0x1 << 15) // (HDMA) Write one to this field to resume the channel 7 transfer restoring its context.\r
+#define        AT91C_HDMA_RES7_0                    (0x0 << 15) // (HDMA) No effect.\r
+#define        AT91C_HDMA_RES7_1                    (0x1 << 15) // (HDMA) Resumes the channel 7.\r
+// -------- HDMA_CHSR : (HDMA Offset: 0x30)  -------- \r
+#define AT91C_HDMA_EMPT0      (0x1 << 16) // (HDMA) When set, channel 0 is empty.\r
+#define        AT91C_HDMA_EMPT0_0                    (0x0 << 16) // (HDMA) No effect.\r
+#define        AT91C_HDMA_EMPT0_1                    (0x1 << 16) // (HDMA) Channel 0 empty.\r
+#define AT91C_HDMA_EMPT1      (0x1 << 17) // (HDMA) When set, channel 1 is empty.\r
+#define        AT91C_HDMA_EMPT1_0                    (0x0 << 17) // (HDMA) No effect.\r
+#define        AT91C_HDMA_EMPT1_1                    (0x1 << 17) // (HDMA) Channel 1 empty.\r
+#define AT91C_HDMA_EMPT2      (0x1 << 18) // (HDMA) When set, channel 2 is empty.\r
+#define        AT91C_HDMA_EMPT2_0                    (0x0 << 18) // (HDMA) No effect.\r
+#define        AT91C_HDMA_EMPT2_1                    (0x1 << 18) // (HDMA) Channel 2 empty.\r
+#define AT91C_HDMA_EMPT3      (0x1 << 19) // (HDMA) When set, channel 3 is empty.\r
+#define        AT91C_HDMA_EMPT3_0                    (0x0 << 19) // (HDMA) No effect.\r
+#define        AT91C_HDMA_EMPT3_1                    (0x1 << 19) // (HDMA) Channel 3 empty.\r
+#define AT91C_HDMA_EMPT4      (0x1 << 20) // (HDMA) When set, channel 4 is empty.\r
+#define        AT91C_HDMA_EMPT4_0                    (0x0 << 20) // (HDMA) No effect.\r
+#define        AT91C_HDMA_EMPT4_1                    (0x1 << 20) // (HDMA) Channel 4 empty.\r
+#define AT91C_HDMA_EMPT5      (0x1 << 21) // (HDMA) When set, channel 5 is empty.\r
+#define        AT91C_HDMA_EMPT5_0                    (0x0 << 21) // (HDMA) No effect.\r
+#define        AT91C_HDMA_EMPT5_1                    (0x1 << 21) // (HDMA) Channel 5 empty.\r
+#define AT91C_HDMA_EMPT6      (0x1 << 22) // (HDMA) When set, channel 6 is empty.\r
+#define        AT91C_HDMA_EMPT6_0                    (0x0 << 22) // (HDMA) No effect.\r
+#define        AT91C_HDMA_EMPT6_1                    (0x1 << 22) // (HDMA) Channel 6 empty.\r
+#define AT91C_HDMA_EMPT7      (0x1 << 23) // (HDMA) When set, channel 7 is empty.\r
+#define        AT91C_HDMA_EMPT7_0                    (0x0 << 23) // (HDMA) No effect.\r
+#define        AT91C_HDMA_EMPT7_1                    (0x1 << 23) // (HDMA) Channel 7 empty.\r
+#define AT91C_HDMA_STAL0      (0x1 << 24) // (HDMA) When set, channel 0 is stalled.\r
+#define        AT91C_HDMA_STAL0_0                    (0x0 << 24) // (HDMA) No effect.\r
+#define        AT91C_HDMA_STAL0_1                    (0x1 << 24) // (HDMA) Channel 0 stalled.\r
+#define AT91C_HDMA_STAL1      (0x1 << 25) // (HDMA) When set, channel 1 is stalled.\r
+#define        AT91C_HDMA_STAL1_0                    (0x0 << 25) // (HDMA) No effect.\r
+#define        AT91C_HDMA_STAL1_1                    (0x1 << 25) // (HDMA) Channel 1 stalled.\r
+#define AT91C_HDMA_STAL2      (0x1 << 26) // (HDMA) When set, channel 2 is stalled.\r
+#define        AT91C_HDMA_STAL2_0                    (0x0 << 26) // (HDMA) No effect.\r
+#define        AT91C_HDMA_STAL2_1                    (0x1 << 26) // (HDMA) Channel 2 stalled.\r
+#define AT91C_HDMA_STAL3      (0x1 << 27) // (HDMA) When set, channel 3 is stalled.\r
+#define        AT91C_HDMA_STAL3_0                    (0x0 << 27) // (HDMA) No effect.\r
+#define        AT91C_HDMA_STAL3_1                    (0x1 << 27) // (HDMA) Channel 3 stalled.\r
+#define AT91C_HDMA_STAL4      (0x1 << 28) // (HDMA) When set, channel 4 is stalled.\r
+#define        AT91C_HDMA_STAL4_0                    (0x0 << 28) // (HDMA) No effect.\r
+#define        AT91C_HDMA_STAL4_1                    (0x1 << 28) // (HDMA) Channel 4 stalled.\r
+#define AT91C_HDMA_STAL5      (0x1 << 29) // (HDMA) When set, channel 5 is stalled.\r
+#define        AT91C_HDMA_STAL5_0                    (0x0 << 29) // (HDMA) No effect.\r
+#define        AT91C_HDMA_STAL5_1                    (0x1 << 29) // (HDMA) Channel 5 stalled.\r
+#define AT91C_HDMA_STAL6      (0x1 << 30) // (HDMA) When set, channel 6 is stalled.\r
+#define        AT91C_HDMA_STAL6_0                    (0x0 << 30) // (HDMA) No effect.\r
+#define        AT91C_HDMA_STAL6_1                    (0x1 << 30) // (HDMA) Channel 6 stalled.\r
+#define AT91C_HDMA_STAL7      (0x1 << 31) // (HDMA) When set, channel 7 is stalled.\r
+#define        AT91C_HDMA_STAL7_0                    (0x0 << 31) // (HDMA) No effect.\r
+#define        AT91C_HDMA_STAL7_1                    (0x1 << 31) // (HDMA) Channel 7 stalled.\r
+// -------- HDMA_RSVD : (HDMA Offset: 0x34)  -------- \r
+// -------- HDMA_RSVD : (HDMA Offset: 0x38)  -------- \r
+// -------- HDMA_VER : (HDMA Offset: 0x1fc)  -------- \r
+\r
+// *****************************************************************************\r
+//               REGISTER ADDRESS DEFINITION FOR AT91SAM3U4\r
+// *****************************************************************************\r
+// ========== Register definition for SYS peripheral ========== \r
+#define AT91C_SYS_GPBR  (AT91_CAST(AT91_REG *)         0x400E1290) // (SYS) General Purpose Register\r
+// ========== Register definition for HSMC4_CS0 peripheral ========== \r
+#define AT91C_CS0_MODE  (AT91_CAST(AT91_REG *)         0x400E0080) // (HSMC4_CS0) Mode Register\r
+#define AT91C_CS0_PULSE (AT91_CAST(AT91_REG *)         0x400E0074) // (HSMC4_CS0) Pulse Register\r
+#define AT91C_CS0_CYCLE (AT91_CAST(AT91_REG *)         0x400E0078) // (HSMC4_CS0) Cycle Register\r
+#define AT91C_CS0_TIMINGS (AT91_CAST(AT91_REG *)       0x400E007C) // (HSMC4_CS0) Timmings Register\r
+#define AT91C_CS0_SETUP (AT91_CAST(AT91_REG *)         0x400E0070) // (HSMC4_CS0) Setup Register\r
+// ========== Register definition for HSMC4_CS1 peripheral ========== \r
+#define AT91C_CS1_CYCLE (AT91_CAST(AT91_REG *)         0x400E008C) // (HSMC4_CS1) Cycle Register\r
+#define AT91C_CS1_PULSE (AT91_CAST(AT91_REG *)         0x400E0088) // (HSMC4_CS1) Pulse Register\r
+#define AT91C_CS1_MODE  (AT91_CAST(AT91_REG *)         0x400E0094) // (HSMC4_CS1) Mode Register\r
+#define AT91C_CS1_SETUP (AT91_CAST(AT91_REG *)         0x400E0084) // (HSMC4_CS1) Setup Register\r
+#define AT91C_CS1_TIMINGS (AT91_CAST(AT91_REG *)       0x400E0090) // (HSMC4_CS1) Timmings Register\r
+// ========== Register definition for HSMC4_CS2 peripheral ========== \r
+#define AT91C_CS2_PULSE (AT91_CAST(AT91_REG *)         0x400E009C) // (HSMC4_CS2) Pulse Register\r
+#define AT91C_CS2_TIMINGS (AT91_CAST(AT91_REG *)       0x400E00A4) // (HSMC4_CS2) Timmings Register\r
+#define AT91C_CS2_CYCLE (AT91_CAST(AT91_REG *)         0x400E00A0) // (HSMC4_CS2) Cycle Register\r
+#define AT91C_CS2_MODE  (AT91_CAST(AT91_REG *)         0x400E00A8) // (HSMC4_CS2) Mode Register\r
+#define AT91C_CS2_SETUP (AT91_CAST(AT91_REG *)         0x400E0098) // (HSMC4_CS2) Setup Register\r
+// ========== Register definition for HSMC4_CS3 peripheral ========== \r
+#define AT91C_CS3_MODE  (AT91_CAST(AT91_REG *)         0x400E00BC) // (HSMC4_CS3) Mode Register\r
+#define AT91C_CS3_TIMINGS (AT91_CAST(AT91_REG *)       0x400E00B8) // (HSMC4_CS3) Timmings Register\r
+#define AT91C_CS3_SETUP (AT91_CAST(AT91_REG *)         0x400E00AC) // (HSMC4_CS3) Setup Register\r
+#define AT91C_CS3_CYCLE (AT91_CAST(AT91_REG *)         0x400E00B4) // (HSMC4_CS3) Cycle Register\r
+#define AT91C_CS3_PULSE (AT91_CAST(AT91_REG *)         0x400E00B0) // (HSMC4_CS3) Pulse Register\r
+// ========== Register definition for HSMC4_NFC peripheral ========== \r
+#define AT91C_NFC_MODE  (AT91_CAST(AT91_REG *)         0x400E010C) // (HSMC4_NFC) Mode Register\r
+#define AT91C_NFC_CYCLE (AT91_CAST(AT91_REG *)         0x400E0104) // (HSMC4_NFC) Cycle Register\r
+#define AT91C_NFC_PULSE (AT91_CAST(AT91_REG *)         0x400E0100) // (HSMC4_NFC) Pulse Register\r
+#define AT91C_NFC_SETUP (AT91_CAST(AT91_REG *)         0x400E00FC) // (HSMC4_NFC) Setup Register\r
+#define AT91C_NFC_TIMINGS (AT91_CAST(AT91_REG *)       0x400E0108) // (HSMC4_NFC) Timmings Register\r
+// ========== Register definition for HSMC4 peripheral ========== \r
+#define AT91C_HSMC4_IPNAME1 (AT91_CAST(AT91_REG *)     0x400E01F0) // (HSMC4) Write Protection Status Register\r
+#define AT91C_HSMC4_ECCPR6 (AT91_CAST(AT91_REG *)      0x400E0048) // (HSMC4) ECC Parity register 6\r
+#define AT91C_HSMC4_ADDRSIZE (AT91_CAST(AT91_REG *)    0x400E01EC) // (HSMC4) Write Protection Status Register\r
+#define AT91C_HSMC4_ECCPR11 (AT91_CAST(AT91_REG *)     0x400E005C) // (HSMC4) ECC Parity register 11\r
+#define AT91C_HSMC4_SR  (AT91_CAST(AT91_REG *)         0x400E0008) // (HSMC4) Status Register\r
+#define AT91C_HSMC4_IMR (AT91_CAST(AT91_REG *)         0x400E0014) // (HSMC4) Interrupt Mask Register\r
+#define AT91C_HSMC4_WPSR (AT91_CAST(AT91_REG *)        0x400E01E8) // (HSMC4) Write Protection Status Register\r
+#define AT91C_HSMC4_BANK (AT91_CAST(AT91_REG *)        0x400E001C) // (HSMC4) Bank Register\r
+#define AT91C_HSMC4_ECCPR8 (AT91_CAST(AT91_REG *)      0x400E0050) // (HSMC4) ECC Parity register 8\r
+#define AT91C_HSMC4_WPCR (AT91_CAST(AT91_REG *)        0x400E01E4) // (HSMC4) Write Protection Control register\r
+#define AT91C_HSMC4_ECCPR2 (AT91_CAST(AT91_REG *)      0x400E0038) // (HSMC4) ECC Parity register 2\r
+#define AT91C_HSMC4_ECCPR1 (AT91_CAST(AT91_REG *)      0x400E0030) // (HSMC4) ECC Parity register 1\r
+#define AT91C_HSMC4_ECCSR2 (AT91_CAST(AT91_REG *)      0x400E0034) // (HSMC4) ECC Status register 2\r
+#define AT91C_HSMC4_OCMS (AT91_CAST(AT91_REG *)        0x400E0110) // (HSMC4) OCMS MODE register\r
+#define AT91C_HSMC4_ECCPR9 (AT91_CAST(AT91_REG *)      0x400E0054) // (HSMC4) ECC Parity register 9\r
+#define AT91C_HSMC4_DUMMY (AT91_CAST(AT91_REG *)       0x400E0200) // (HSMC4) This rtegister was created only ti have AHB constants\r
+#define AT91C_HSMC4_ECCPR5 (AT91_CAST(AT91_REG *)      0x400E0044) // (HSMC4) ECC Parity register 5\r
+#define AT91C_HSMC4_ECCCR (AT91_CAST(AT91_REG *)       0x400E0020) // (HSMC4) ECC reset register\r
+#define AT91C_HSMC4_KEY2 (AT91_CAST(AT91_REG *)        0x400E0118) // (HSMC4) KEY2 Register\r
+#define AT91C_HSMC4_IER (AT91_CAST(AT91_REG *)         0x400E000C) // (HSMC4) Interrupt Enable Register\r
+#define AT91C_HSMC4_ECCSR1 (AT91_CAST(AT91_REG *)      0x400E0028) // (HSMC4) ECC Status register 1\r
+#define AT91C_HSMC4_IDR (AT91_CAST(AT91_REG *)         0x400E0010) // (HSMC4) Interrupt Disable Register\r
+#define AT91C_HSMC4_ECCPR0 (AT91_CAST(AT91_REG *)      0x400E002C) // (HSMC4) ECC Parity register 0\r
+#define AT91C_HSMC4_FEATURES (AT91_CAST(AT91_REG *)    0x400E01F8) // (HSMC4) Write Protection Status Register\r
+#define AT91C_HSMC4_ECCPR7 (AT91_CAST(AT91_REG *)      0x400E004C) // (HSMC4) ECC Parity register 7\r
+#define AT91C_HSMC4_ECCPR12 (AT91_CAST(AT91_REG *)     0x400E0060) // (HSMC4) ECC Parity register 12\r
+#define AT91C_HSMC4_ECCPR10 (AT91_CAST(AT91_REG *)     0x400E0058) // (HSMC4) ECC Parity register 10\r
+#define AT91C_HSMC4_KEY1 (AT91_CAST(AT91_REG *)        0x400E0114) // (HSMC4) KEY1 Register\r
+#define AT91C_HSMC4_VER (AT91_CAST(AT91_REG *)         0x400E01FC) // (HSMC4) HSMC4 Version Register\r
+#define AT91C_HSMC4_Eccpr15 (AT91_CAST(AT91_REG *)     0x400E006C) // (HSMC4) ECC Parity register 15\r
+#define AT91C_HSMC4_ECCPR4 (AT91_CAST(AT91_REG *)      0x400E0040) // (HSMC4) ECC Parity register 4\r
+#define AT91C_HSMC4_IPNAME2 (AT91_CAST(AT91_REG *)     0x400E01F4) // (HSMC4) Write Protection Status Register\r
+#define AT91C_HSMC4_ECCCMD (AT91_CAST(AT91_REG *)      0x400E0024) // (HSMC4) ECC Page size register\r
+#define AT91C_HSMC4_ADDR (AT91_CAST(AT91_REG *)        0x400E0018) // (HSMC4) Address Cycle Zero Register\r
+#define AT91C_HSMC4_ECCPR3 (AT91_CAST(AT91_REG *)      0x400E003C) // (HSMC4) ECC Parity register 3\r
+#define AT91C_HSMC4_CFG (AT91_CAST(AT91_REG *)         0x400E0000) // (HSMC4) Configuration Register\r
+#define AT91C_HSMC4_CTRL (AT91_CAST(AT91_REG *)        0x400E0004) // (HSMC4) Control Register\r
+#define AT91C_HSMC4_ECCPR13 (AT91_CAST(AT91_REG *)     0x400E0064) // (HSMC4) ECC Parity register 13\r
+#define AT91C_HSMC4_ECCPR14 (AT91_CAST(AT91_REG *)     0x400E0068) // (HSMC4) ECC Parity register 14\r
+// ========== Register definition for MATRIX peripheral ========== \r
+#define AT91C_MATRIX_SFR2  (AT91_CAST(AT91_REG *)      0x400E0318) // (MATRIX)  Special Function Register 2\r
+#define AT91C_MATRIX_SFR3  (AT91_CAST(AT91_REG *)      0x400E031C) // (MATRIX)  Special Function Register 3\r
+#define AT91C_MATRIX_SCFG8 (AT91_CAST(AT91_REG *)      0x400E0260) // (MATRIX)  Slave Configuration Register 8\r
+#define AT91C_MATRIX_MCFG2 (AT91_CAST(AT91_REG *)      0x400E0208) // (MATRIX)  Master Configuration Register 2\r
+#define AT91C_MATRIX_MCFG7 (AT91_CAST(AT91_REG *)      0x400E021C) // (MATRIX)  Master Configuration Register 7\r
+#define AT91C_MATRIX_SCFG3 (AT91_CAST(AT91_REG *)      0x400E024C) // (MATRIX)  Slave Configuration Register 3\r
+#define AT91C_MATRIX_SCFG0 (AT91_CAST(AT91_REG *)      0x400E0240) // (MATRIX)  Slave Configuration Register 0\r
+#define AT91C_MATRIX_SFR12 (AT91_CAST(AT91_REG *)      0x400E0340) // (MATRIX)  Special Function Register 12\r
+#define AT91C_MATRIX_SCFG1 (AT91_CAST(AT91_REG *)      0x400E0244) // (MATRIX)  Slave Configuration Register 1\r
+#define AT91C_MATRIX_SFR8  (AT91_CAST(AT91_REG *)      0x400E0330) // (MATRIX)  Special Function Register 8\r
+#define AT91C_MATRIX_VER (AT91_CAST(AT91_REG *)        0x400E03FC) // (MATRIX) HMATRIX2 VERSION REGISTER \r
+#define AT91C_MATRIX_SFR13 (AT91_CAST(AT91_REG *)      0x400E0344) // (MATRIX)  Special Function Register 13\r
+#define AT91C_MATRIX_SFR5  (AT91_CAST(AT91_REG *)      0x400E0324) // (MATRIX)  Special Function Register 5\r
+#define AT91C_MATRIX_MCFG0 (AT91_CAST(AT91_REG *)      0x400E0200) // (MATRIX)  Master Configuration Register 0 : ARM I and D\r
+#define AT91C_MATRIX_SCFG6 (AT91_CAST(AT91_REG *)      0x400E0258) // (MATRIX)  Slave Configuration Register 6\r
+#define AT91C_MATRIX_SFR1  (AT91_CAST(AT91_REG *)      0x400E0314) // (MATRIX)  Special Function Register 1\r
+#define AT91C_MATRIX_SFR14 (AT91_CAST(AT91_REG *)      0x400E0348) // (MATRIX)  Special Function Register 14\r
+#define AT91C_MATRIX_SFR15 (AT91_CAST(AT91_REG *)      0x400E034C) // (MATRIX)  Special Function Register 15\r
+#define AT91C_MATRIX_SFR6  (AT91_CAST(AT91_REG *)      0x400E0328) // (MATRIX)  Special Function Register 6\r
+#define AT91C_MATRIX_SFR11 (AT91_CAST(AT91_REG *)      0x400E033C) // (MATRIX)  Special Function Register 11\r
+#define AT91C_MATRIX_IPNAME2 (AT91_CAST(AT91_REG *)    0x400E03F4) // (MATRIX) HMATRIX2 IPNAME2 REGISTER \r
+#define AT91C_MATRIX_ADDRSIZE (AT91_CAST(AT91_REG *)   0x400E03EC) // (MATRIX) HMATRIX2 ADDRSIZE REGISTER \r
+#define AT91C_MATRIX_MCFG5 (AT91_CAST(AT91_REG *)      0x400E0214) // (MATRIX)  Master Configuration Register 5\r
+#define AT91C_MATRIX_SFR9  (AT91_CAST(AT91_REG *)      0x400E0334) // (MATRIX)  Special Function Register 9\r
+#define AT91C_MATRIX_MCFG3 (AT91_CAST(AT91_REG *)      0x400E020C) // (MATRIX)  Master Configuration Register 3\r
+#define AT91C_MATRIX_SCFG4 (AT91_CAST(AT91_REG *)      0x400E0250) // (MATRIX)  Slave Configuration Register 4\r
+#define AT91C_MATRIX_MCFG1 (AT91_CAST(AT91_REG *)      0x400E0204) // (MATRIX)  Master Configuration Register 1 : ARM S\r
+#define AT91C_MATRIX_SCFG7 (AT91_CAST(AT91_REG *)      0x400E025C) // (MATRIX)  Slave Configuration Register 5\r
+#define AT91C_MATRIX_SFR10 (AT91_CAST(AT91_REG *)      0x400E0338) // (MATRIX)  Special Function Register 10\r
+#define AT91C_MATRIX_SCFG2 (AT91_CAST(AT91_REG *)      0x400E0248) // (MATRIX)  Slave Configuration Register 2\r
+#define AT91C_MATRIX_SFR7  (AT91_CAST(AT91_REG *)      0x400E032C) // (MATRIX)  Special Function Register 7\r
+#define AT91C_MATRIX_IPNAME1 (AT91_CAST(AT91_REG *)    0x400E03F0) // (MATRIX) HMATRIX2 IPNAME1 REGISTER \r
+#define AT91C_MATRIX_MCFG4 (AT91_CAST(AT91_REG *)      0x400E0210) // (MATRIX)  Master Configuration Register 4\r
+#define AT91C_MATRIX_SFR0  (AT91_CAST(AT91_REG *)      0x400E0310) // (MATRIX)  Special Function Register 0\r
+#define AT91C_MATRIX_FEATURES (AT91_CAST(AT91_REG *)   0x400E03F8) // (MATRIX) HMATRIX2 FEATURES REGISTER \r
+#define AT91C_MATRIX_SCFG5 (AT91_CAST(AT91_REG *)      0x400E0254) // (MATRIX)  Slave Configuration Register 5\r
+#define AT91C_MATRIX_MCFG6 (AT91_CAST(AT91_REG *)      0x400E0218) // (MATRIX)  Master Configuration Register 6\r
+#define AT91C_MATRIX_SFR4  (AT91_CAST(AT91_REG *)      0x400E0320) // (MATRIX)  Special Function Register 4\r
+// ========== Register definition for NVIC peripheral ========== \r
+#define AT91C_NVIC_MMAR (AT91_CAST(AT91_REG *)         0xE000ED34) // (NVIC) Mem Manage Address Register\r
+#define AT91C_NVIC_STIR (AT91_CAST(AT91_REG *)         0xE000EF00) // (NVIC) Software Trigger Interrupt Register\r
+#define AT91C_NVIC_MMFR2 (AT91_CAST(AT91_REG *)        0xE000ED58) // (NVIC) Memory Model Feature register2\r
+#define AT91C_NVIC_CPUID (AT91_CAST(AT91_REG *)        0xE000ED00) // (NVIC) CPUID Base Register\r
+#define AT91C_NVIC_DFSR (AT91_CAST(AT91_REG *)         0xE000ED30) // (NVIC) Debug Fault Status Register\r
+#define AT91C_NVIC_HAND4PR (AT91_CAST(AT91_REG *)      0xE000ED18) // (NVIC) System Handlers 4-7 Priority Register\r
+#define AT91C_NVIC_HFSR (AT91_CAST(AT91_REG *)         0xE000ED2C) // (NVIC) Hard Fault Status Register\r
+#define AT91C_NVIC_PID6 (AT91_CAST(AT91_REG *)         0xE000EFD8) // (NVIC) Peripheral identification register\r
+#define AT91C_NVIC_PFR0 (AT91_CAST(AT91_REG *)         0xE000ED40) // (NVIC) Processor Feature register0\r
+#define AT91C_NVIC_VTOFFR (AT91_CAST(AT91_REG *)       0xE000ED08) // (NVIC) Vector Table Offset Register\r
+#define AT91C_NVIC_ISPR (AT91_CAST(AT91_REG *)         0xE000E200) // (NVIC) Set Pending Register\r
+#define AT91C_NVIC_PID0 (AT91_CAST(AT91_REG *)         0xE000EFE0) // (NVIC) Peripheral identification register b7:0\r
+#define AT91C_NVIC_PID7 (AT91_CAST(AT91_REG *)         0xE000EFDC) // (NVIC) Peripheral identification register\r
+#define AT91C_NVIC_STICKRVR (AT91_CAST(AT91_REG *)     0xE000E014) // (NVIC) SysTick Reload Value Register\r
+#define AT91C_NVIC_PID2 (AT91_CAST(AT91_REG *)         0xE000EFE8) // (NVIC) Peripheral identification register b23:16\r
+#define AT91C_NVIC_ISAR0 (AT91_CAST(AT91_REG *)        0xE000ED60) // (NVIC) ISA Feature register0\r
+#define AT91C_NVIC_SCR  (AT91_CAST(AT91_REG *)         0xE000ED10) // (NVIC) System Control Register\r
+#define AT91C_NVIC_PID4 (AT91_CAST(AT91_REG *)         0xE000EFD0) // (NVIC) Peripheral identification register\r
+#define AT91C_NVIC_ISAR2 (AT91_CAST(AT91_REG *)        0xE000ED68) // (NVIC) ISA Feature register2\r
+#define AT91C_NVIC_ISER (AT91_CAST(AT91_REG *)         0xE000E100) // (NVIC) Set Enable Register\r
+#define AT91C_NVIC_IPR  (AT91_CAST(AT91_REG *)         0xE000E400) // (NVIC) Interrupt Mask Register\r
+#define AT91C_NVIC_AIRCR (AT91_CAST(AT91_REG *)        0xE000ED0C) // (NVIC) Application Interrupt/Reset Control Reg\r
+#define AT91C_NVIC_CID2 (AT91_CAST(AT91_REG *)         0xE000EFF8) // (NVIC) Component identification register b23:16\r
+#define AT91C_NVIC_ICPR (AT91_CAST(AT91_REG *)         0xE000E280) // (NVIC) Clear Pending Register\r
+#define AT91C_NVIC_CID3 (AT91_CAST(AT91_REG *)         0xE000EFFC) // (NVIC) Component identification register b31:24\r
+#define AT91C_NVIC_CFSR (AT91_CAST(AT91_REG *)         0xE000ED28) // (NVIC) Configurable Fault Status Register\r
+#define AT91C_NVIC_AFR0 (AT91_CAST(AT91_REG *)         0xE000ED4C) // (NVIC) Auxiliary Feature register0\r
+#define AT91C_NVIC_ICSR (AT91_CAST(AT91_REG *)         0xE000ED04) // (NVIC) Interrupt Control State Register\r
+#define AT91C_NVIC_CCR  (AT91_CAST(AT91_REG *)         0xE000ED14) // (NVIC) Configuration Control Register\r
+#define AT91C_NVIC_CID0 (AT91_CAST(AT91_REG *)         0xE000EFF0) // (NVIC) Component identification register b7:0\r
+#define AT91C_NVIC_ISAR1 (AT91_CAST(AT91_REG *)        0xE000ED64) // (NVIC) ISA Feature register1\r
+#define AT91C_NVIC_STICKCVR (AT91_CAST(AT91_REG *)     0xE000E018) // (NVIC) SysTick Current Value Register\r
+#define AT91C_NVIC_STICKCSR (AT91_CAST(AT91_REG *)     0xE000E010) // (NVIC) SysTick Control and Status Register\r
+#define AT91C_NVIC_CID1 (AT91_CAST(AT91_REG *)         0xE000EFF4) // (NVIC) Component identification register b15:8\r
+#define AT91C_NVIC_DFR0 (AT91_CAST(AT91_REG *)         0xE000ED48) // (NVIC) Debug Feature register0\r
+#define AT91C_NVIC_MMFR3 (AT91_CAST(AT91_REG *)        0xE000ED5C) // (NVIC) Memory Model Feature register3\r
+#define AT91C_NVIC_MMFR0 (AT91_CAST(AT91_REG *)        0xE000ED50) // (NVIC) Memory Model Feature register0\r
+#define AT91C_NVIC_STICKCALVR (AT91_CAST(AT91_REG *)   0xE000E01C) // (NVIC) SysTick Calibration Value Register\r
+#define AT91C_NVIC_PID1 (AT91_CAST(AT91_REG *)         0xE000EFE4) // (NVIC) Peripheral identification register b15:8\r
+#define AT91C_NVIC_HAND12PR (AT91_CAST(AT91_REG *)     0xE000ED20) // (NVIC) System Handlers 12-15 Priority Register\r
+#define AT91C_NVIC_MMFR1 (AT91_CAST(AT91_REG *)        0xE000ED54) // (NVIC) Memory Model Feature register1\r
+#define AT91C_NVIC_AFSR (AT91_CAST(AT91_REG *)         0xE000ED3C) // (NVIC) Auxiliary Fault Status Register\r
+#define AT91C_NVIC_HANDCSR (AT91_CAST(AT91_REG *)      0xE000ED24) // (NVIC) System Handler Control and State Register\r
+#define AT91C_NVIC_ISAR4 (AT91_CAST(AT91_REG *)        0xE000ED70) // (NVIC) ISA Feature register4\r
+#define AT91C_NVIC_ABR  (AT91_CAST(AT91_REG *)         0xE000E300) // (NVIC) Active Bit Register\r
+#define AT91C_NVIC_PFR1 (AT91_CAST(AT91_REG *)         0xE000ED44) // (NVIC) Processor Feature register1\r
+#define AT91C_NVIC_PID5 (AT91_CAST(AT91_REG *)         0xE000EFD4) // (NVIC) Peripheral identification register\r
+#define AT91C_NVIC_ICTR (AT91_CAST(AT91_REG *)         0xE000E004) // (NVIC) Interrupt Control Type Register\r
+#define AT91C_NVIC_ICER (AT91_CAST(AT91_REG *)         0xE000E180) // (NVIC) Clear enable Register\r
+#define AT91C_NVIC_PID3 (AT91_CAST(AT91_REG *)         0xE000EFEC) // (NVIC) Peripheral identification register b31:24\r
+#define AT91C_NVIC_ISAR3 (AT91_CAST(AT91_REG *)        0xE000ED6C) // (NVIC) ISA Feature register3\r
+#define AT91C_NVIC_HAND8PR (AT91_CAST(AT91_REG *)      0xE000ED1C) // (NVIC) System Handlers 8-11 Priority Register\r
+#define AT91C_NVIC_BFAR (AT91_CAST(AT91_REG *)         0xE000ED38) // (NVIC) Bus Fault Address Register\r
+// ========== Register definition for MPU peripheral ========== \r
+#define AT91C_MPU_REG_BASE_ADDR3 (AT91_CAST(AT91_REG *)        0xE000EDB4) // (MPU) MPU Region Base Address Register alias 3\r
+#define AT91C_MPU_REG_NB (AT91_CAST(AT91_REG *)        0xE000ED98) // (MPU) MPU Region Number Register\r
+#define AT91C_MPU_ATTR_SIZE1 (AT91_CAST(AT91_REG *)    0xE000EDA8) // (MPU) MPU  Attribute and Size Register alias 1\r
+#define AT91C_MPU_REG_BASE_ADDR1 (AT91_CAST(AT91_REG *)        0xE000EDA4) // (MPU) MPU Region Base Address Register alias 1\r
+#define AT91C_MPU_ATTR_SIZE3 (AT91_CAST(AT91_REG *)    0xE000EDB8) // (MPU) MPU  Attribute and Size Register alias 3\r
+#define AT91C_MPU_CTRL  (AT91_CAST(AT91_REG *)         0xE000ED94) // (MPU) MPU Control Register\r
+#define AT91C_MPU_ATTR_SIZE2 (AT91_CAST(AT91_REG *)    0xE000EDB0) // (MPU) MPU  Attribute and Size Register alias 2\r
+#define AT91C_MPU_REG_BASE_ADDR (AT91_CAST(AT91_REG *)         0xE000ED9C) // (MPU) MPU Region Base Address Register\r
+#define AT91C_MPU_REG_BASE_ADDR2 (AT91_CAST(AT91_REG *)        0xE000EDAC) // (MPU) MPU Region Base Address Register alias 2\r
+#define AT91C_MPU_ATTR_SIZE (AT91_CAST(AT91_REG *)     0xE000EDA0) // (MPU) MPU  Attribute and Size Register\r
+#define AT91C_MPU_TYPE  (AT91_CAST(AT91_REG *)         0xE000ED90) // (MPU) MPU Type Register\r
+// ========== Register definition for CM3 peripheral ========== \r
+#define AT91C_CM3_SHCSR (AT91_CAST(AT91_REG *)         0xE000ED24) // (CM3) System Handler Control and State Register\r
+#define AT91C_CM3_CCR   (AT91_CAST(AT91_REG *)         0xE000ED14) // (CM3) Configuration Control Register\r
+#define AT91C_CM3_ICSR  (AT91_CAST(AT91_REG *)         0xE000ED04) // (CM3) Interrupt Control State Register\r
+#define AT91C_CM3_CPUID (AT91_CAST(AT91_REG *)         0xE000ED00) // (CM3) CPU ID Base Register\r
+#define AT91C_CM3_SCR   (AT91_CAST(AT91_REG *)         0xE000ED10) // (CM3) System Controller Register\r
+#define AT91C_CM3_AIRCR (AT91_CAST(AT91_REG *)         0xE000ED0C) // (CM3) Application Interrupt and Reset Control Register\r
+#define AT91C_CM3_SHPR  (AT91_CAST(AT91_REG *)         0xE000ED18) // (CM3) System Handler Priority Register\r
+#define AT91C_CM3_VTOR  (AT91_CAST(AT91_REG *)         0xE000ED08) // (CM3) Vector Table Offset Register\r
+// ========== Register definition for PDC_DBGU peripheral ========== \r
+#define AT91C_DBGU_TPR  (AT91_CAST(AT91_REG *)         0x400E0708) // (PDC_DBGU) Transmit Pointer Register\r
+#define AT91C_DBGU_PTCR (AT91_CAST(AT91_REG *)         0x400E0720) // (PDC_DBGU) PDC Transfer Control Register\r
+#define AT91C_DBGU_TNCR (AT91_CAST(AT91_REG *)         0x400E071C) // (PDC_DBGU) Transmit Next Counter Register\r
+#define AT91C_DBGU_PTSR (AT91_CAST(AT91_REG *)         0x400E0724) // (PDC_DBGU) PDC Transfer Status Register\r
+#define AT91C_DBGU_RNCR (AT91_CAST(AT91_REG *)         0x400E0714) // (PDC_DBGU) Receive Next Counter Register\r
+#define AT91C_DBGU_RPR  (AT91_CAST(AT91_REG *)         0x400E0700) // (PDC_DBGU) Receive Pointer Register\r
+#define AT91C_DBGU_TCR  (AT91_CAST(AT91_REG *)         0x400E070C) // (PDC_DBGU) Transmit Counter Register\r
+#define AT91C_DBGU_RNPR (AT91_CAST(AT91_REG *)         0x400E0710) // (PDC_DBGU) Receive Next Pointer Register\r
+#define AT91C_DBGU_TNPR (AT91_CAST(AT91_REG *)         0x400E0718) // (PDC_DBGU) Transmit Next Pointer Register\r
+#define AT91C_DBGU_RCR  (AT91_CAST(AT91_REG *)         0x400E0704) // (PDC_DBGU) Receive Counter Register\r
+// ========== Register definition for DBGU peripheral ========== \r
+#define AT91C_DBGU_CR   (AT91_CAST(AT91_REG *)         0x400E0600) // (DBGU) Control Register\r
+#define AT91C_DBGU_IDR  (AT91_CAST(AT91_REG *)         0x400E060C) // (DBGU) Interrupt Disable Register\r
+#define AT91C_DBGU_CIDR (AT91_CAST(AT91_REG *)         0x400E0740) // (DBGU) Chip ID Register\r
+#define AT91C_DBGU_IPNAME2 (AT91_CAST(AT91_REG *)      0x400E06F4) // (DBGU) DBGU IPNAME2 REGISTER \r
+#define AT91C_DBGU_FEATURES (AT91_CAST(AT91_REG *)     0x400E06F8) // (DBGU) DBGU FEATURES REGISTER \r
+#define AT91C_DBGU_FNTR (AT91_CAST(AT91_REG *)         0x400E0648) // (DBGU) Force NTRST Register\r
+#define AT91C_DBGU_RHR  (AT91_CAST(AT91_REG *)         0x400E0618) // (DBGU) Receiver Holding Register\r
+#define AT91C_DBGU_THR  (AT91_CAST(AT91_REG *)         0x400E061C) // (DBGU) Transmitter Holding Register\r
+#define AT91C_DBGU_ADDRSIZE (AT91_CAST(AT91_REG *)     0x400E06EC) // (DBGU) DBGU ADDRSIZE REGISTER \r
+#define AT91C_DBGU_MR   (AT91_CAST(AT91_REG *)         0x400E0604) // (DBGU) Mode Register\r
+#define AT91C_DBGU_IER  (AT91_CAST(AT91_REG *)         0x400E0608) // (DBGU) Interrupt Enable Register\r
+#define AT91C_DBGU_BRGR (AT91_CAST(AT91_REG *)         0x400E0620) // (DBGU) Baud Rate Generator Register\r
+#define AT91C_DBGU_CSR  (AT91_CAST(AT91_REG *)         0x400E0614) // (DBGU) Channel Status Register\r
+#define AT91C_DBGU_VER  (AT91_CAST(AT91_REG *)         0x400E06FC) // (DBGU) DBGU VERSION REGISTER \r
+#define AT91C_DBGU_IMR  (AT91_CAST(AT91_REG *)         0x400E0610) // (DBGU) Interrupt Mask Register\r
+#define AT91C_DBGU_IPNAME1 (AT91_CAST(AT91_REG *)      0x400E06F0) // (DBGU) DBGU IPNAME1 REGISTER \r
+#define AT91C_DBGU_EXID (AT91_CAST(AT91_REG *)         0x400E0744) // (DBGU) Chip ID Extension Register\r
+// ========== Register definition for PIOA peripheral ========== \r
+#define AT91C_PIOA_PDR  (AT91_CAST(AT91_REG *)         0x400E0C04) // (PIOA) PIO Disable Register\r
+#define AT91C_PIOA_FRLHSR (AT91_CAST(AT91_REG *)       0x400E0CD8) // (PIOA) Fall/Rise - Low/High Status Register\r
+#define AT91C_PIOA_KIMR (AT91_CAST(AT91_REG *)         0x400E0D38) // (PIOA) Keypad Controller Interrupt Mask Register\r
+#define AT91C_PIOA_LSR  (AT91_CAST(AT91_REG *)         0x400E0CC4) // (PIOA) Level Select Register\r
+#define AT91C_PIOA_IFSR (AT91_CAST(AT91_REG *)         0x400E0C28) // (PIOA) Input Filter Status Register\r
+#define AT91C_PIOA_KKRR (AT91_CAST(AT91_REG *)         0x400E0D44) // (PIOA) Keypad Controller Key Release Register\r
+#define AT91C_PIOA_ODR  (AT91_CAST(AT91_REG *)         0x400E0C14) // (PIOA) Output Disable Registerr\r
+#define AT91C_PIOA_SCIFSR (AT91_CAST(AT91_REG *)       0x400E0C80) // (PIOA) System Clock Glitch Input Filter Select Register\r
+#define AT91C_PIOA_PER  (AT91_CAST(AT91_REG *)         0x400E0C00) // (PIOA) PIO Enable Register\r
+#define AT91C_PIOA_VER  (AT91_CAST(AT91_REG *)         0x400E0CFC) // (PIOA) PIO VERSION REGISTER \r
+#define AT91C_PIOA_OWSR (AT91_CAST(AT91_REG *)         0x400E0CA8) // (PIOA) Output Write Status Register\r
+#define AT91C_PIOA_KSR  (AT91_CAST(AT91_REG *)         0x400E0D3C) // (PIOA) Keypad Controller Status Register\r
+#define AT91C_PIOA_IMR  (AT91_CAST(AT91_REG *)         0x400E0C48) // (PIOA) Interrupt Mask Register\r
+#define AT91C_PIOA_OWDR (AT91_CAST(AT91_REG *)         0x400E0CA4) // (PIOA) Output Write Disable Register\r
+#define AT91C_PIOA_MDSR (AT91_CAST(AT91_REG *)         0x400E0C58) // (PIOA) Multi-driver Status Register\r
+#define AT91C_PIOA_IFDR (AT91_CAST(AT91_REG *)         0x400E0C24) // (PIOA) Input Filter Disable Register\r
+#define AT91C_PIOA_AIMDR (AT91_CAST(AT91_REG *)        0x400E0CB4) // (PIOA) Additional Interrupt Modes Disables Register\r
+#define AT91C_PIOA_CODR (AT91_CAST(AT91_REG *)         0x400E0C34) // (PIOA) Clear Output Data Register\r
+#define AT91C_PIOA_SCDR (AT91_CAST(AT91_REG *)         0x400E0C8C) // (PIOA) Slow Clock Divider Debouncing Register\r
+#define AT91C_PIOA_KIER (AT91_CAST(AT91_REG *)         0x400E0D30) // (PIOA) Keypad Controller Interrupt Enable Register\r
+#define AT91C_PIOA_REHLSR (AT91_CAST(AT91_REG *)       0x400E0CD4) // (PIOA) Rising Edge/ High Level Select Register\r
+#define AT91C_PIOA_ISR  (AT91_CAST(AT91_REG *)         0x400E0C4C) // (PIOA) Interrupt Status Register\r
+#define AT91C_PIOA_ESR  (AT91_CAST(AT91_REG *)         0x400E0CC0) // (PIOA) Edge Select Register\r
+#define AT91C_PIOA_PPUDR (AT91_CAST(AT91_REG *)        0x400E0C60) // (PIOA) Pull-up Disable Register\r
+#define AT91C_PIOA_MDDR (AT91_CAST(AT91_REG *)         0x400E0C54) // (PIOA) Multi-driver Disable Register\r
+#define AT91C_PIOA_PSR  (AT91_CAST(AT91_REG *)         0x400E0C08) // (PIOA) PIO Status Register\r
+#define AT91C_PIOA_PDSR (AT91_CAST(AT91_REG *)         0x400E0C3C) // (PIOA) Pin Data Status Register\r
+#define AT91C_PIOA_IFDGSR (AT91_CAST(AT91_REG *)       0x400E0C88) // (PIOA) Glitch or Debouncing Input Filter Clock Selection Status Register\r
+#define AT91C_PIOA_FELLSR (AT91_CAST(AT91_REG *)       0x400E0CD0) // (PIOA) Falling Edge/Low Level Select Register\r
+#define AT91C_PIOA_PPUSR (AT91_CAST(AT91_REG *)        0x400E0C68) // (PIOA) Pull-up Status Register\r
+#define AT91C_PIOA_OER  (AT91_CAST(AT91_REG *)         0x400E0C10) // (PIOA) Output Enable Register\r
+#define AT91C_PIOA_OSR  (AT91_CAST(AT91_REG *)         0x400E0C18) // (PIOA) Output Status Register\r
+#define AT91C_PIOA_KKPR (AT91_CAST(AT91_REG *)         0x400E0D40) // (PIOA) Keypad Controller Key Press Register\r
+#define AT91C_PIOA_AIMMR (AT91_CAST(AT91_REG *)        0x400E0CB8) // (PIOA) Additional Interrupt Modes Mask Register\r
+#define AT91C_PIOA_KRCR (AT91_CAST(AT91_REG *)         0x400E0D24) // (PIOA) Keypad Controller Row Column Register\r
+#define AT91C_PIOA_IER  (AT91_CAST(AT91_REG *)         0x400E0C40) // (PIOA) Interrupt Enable Register\r
+#define AT91C_PIOA_KER  (AT91_CAST(AT91_REG *)         0x400E0D20) // (PIOA) Keypad Controller Enable Register\r
+#define AT91C_PIOA_PPUER (AT91_CAST(AT91_REG *)        0x400E0C64) // (PIOA) Pull-up Enable Register\r
+#define AT91C_PIOA_KIDR (AT91_CAST(AT91_REG *)         0x400E0D34) // (PIOA) Keypad Controller Interrupt Disable Register\r
+#define AT91C_PIOA_ABSR (AT91_CAST(AT91_REG *)         0x400E0C70) // (PIOA) Peripheral AB Select Register\r
+#define AT91C_PIOA_LOCKSR (AT91_CAST(AT91_REG *)       0x400E0CE0) // (PIOA) Lock Status Register\r
+#define AT91C_PIOA_DIFSR (AT91_CAST(AT91_REG *)        0x400E0C84) // (PIOA) Debouncing Input Filter Select Register\r
+#define AT91C_PIOA_MDER (AT91_CAST(AT91_REG *)         0x400E0C50) // (PIOA) Multi-driver Enable Register\r
+#define AT91C_PIOA_AIMER (AT91_CAST(AT91_REG *)        0x400E0CB0) // (PIOA) Additional Interrupt Modes Enable Register\r
+#define AT91C_PIOA_ELSR (AT91_CAST(AT91_REG *)         0x400E0CC8) // (PIOA) Edge/Level Status Register\r
+#define AT91C_PIOA_IFER (AT91_CAST(AT91_REG *)         0x400E0C20) // (PIOA) Input Filter Enable Register\r
+#define AT91C_PIOA_KDR  (AT91_CAST(AT91_REG *)         0x400E0D28) // (PIOA) Keypad Controller Debouncing Register\r
+#define AT91C_PIOA_IDR  (AT91_CAST(AT91_REG *)         0x400E0C44) // (PIOA) Interrupt Disable Register\r
+#define AT91C_PIOA_OWER (AT91_CAST(AT91_REG *)         0x400E0CA0) // (PIOA) Output Write Enable Register\r
+#define AT91C_PIOA_ODSR (AT91_CAST(AT91_REG *)         0x400E0C38) // (PIOA) Output Data Status Register\r
+#define AT91C_PIOA_SODR (AT91_CAST(AT91_REG *)         0x400E0C30) // (PIOA) Set Output Data Register\r
+// ========== Register definition for PIOB peripheral ========== \r
+#define AT91C_PIOB_KIDR (AT91_CAST(AT91_REG *)         0x400E0F34) // (PIOB) Keypad Controller Interrupt Disable Register\r
+#define AT91C_PIOB_OWSR (AT91_CAST(AT91_REG *)         0x400E0EA8) // (PIOB) Output Write Status Register\r
+#define AT91C_PIOB_PSR  (AT91_CAST(AT91_REG *)         0x400E0E08) // (PIOB) PIO Status Register\r
+#define AT91C_PIOB_MDER (AT91_CAST(AT91_REG *)         0x400E0E50) // (PIOB) Multi-driver Enable Register\r
+#define AT91C_PIOB_ODR  (AT91_CAST(AT91_REG *)         0x400E0E14) // (PIOB) Output Disable Registerr\r
+#define AT91C_PIOB_IDR  (AT91_CAST(AT91_REG *)         0x400E0E44) // (PIOB) Interrupt Disable Register\r
+#define AT91C_PIOB_AIMER (AT91_CAST(AT91_REG *)        0x400E0EB0) // (PIOB) Additional Interrupt Modes Enable Register\r
+#define AT91C_PIOB_DIFSR (AT91_CAST(AT91_REG *)        0x400E0E84) // (PIOB) Debouncing Input Filter Select Register\r
+#define AT91C_PIOB_PDR  (AT91_CAST(AT91_REG *)         0x400E0E04) // (PIOB) PIO Disable Register\r
+#define AT91C_PIOB_REHLSR (AT91_CAST(AT91_REG *)       0x400E0ED4) // (PIOB) Rising Edge/ High Level Select Register\r
+#define AT91C_PIOB_PDSR (AT91_CAST(AT91_REG *)         0x400E0E3C) // (PIOB) Pin Data Status Register\r
+#define AT91C_PIOB_PPUDR (AT91_CAST(AT91_REG *)        0x400E0E60) // (PIOB) Pull-up Disable Register\r
+#define AT91C_PIOB_LSR  (AT91_CAST(AT91_REG *)         0x400E0EC4) // (PIOB) Level Select Register\r
+#define AT91C_PIOB_OWDR (AT91_CAST(AT91_REG *)         0x400E0EA4) // (PIOB) Output Write Disable Register\r
+#define AT91C_PIOB_FELLSR (AT91_CAST(AT91_REG *)       0x400E0ED0) // (PIOB) Falling Edge/Low Level Select Register\r
+#define AT91C_PIOB_IFER (AT91_CAST(AT91_REG *)         0x400E0E20) // (PIOB) Input Filter Enable Register\r
+#define AT91C_PIOB_ABSR (AT91_CAST(AT91_REG *)         0x400E0E70) // (PIOB) Peripheral AB Select Register\r
+#define AT91C_PIOB_KIMR (AT91_CAST(AT91_REG *)         0x400E0F38) // (PIOB) Keypad Controller Interrupt Mask Register\r
+#define AT91C_PIOB_KKPR (AT91_CAST(AT91_REG *)         0x400E0F40) // (PIOB) Keypad Controller Key Press Register\r
+#define AT91C_PIOB_FRLHSR (AT91_CAST(AT91_REG *)       0x400E0ED8) // (PIOB) Fall/Rise - Low/High Status Register\r
+#define AT91C_PIOB_AIMDR (AT91_CAST(AT91_REG *)        0x400E0EB4) // (PIOB) Additional Interrupt Modes Disables Register\r
+#define AT91C_PIOB_SCIFSR (AT91_CAST(AT91_REG *)       0x400E0E80) // (PIOB) System Clock Glitch Input Filter Select Register\r
+#define AT91C_PIOB_VER  (AT91_CAST(AT91_REG *)         0x400E0EFC) // (PIOB) PIO VERSION REGISTER \r
+#define AT91C_PIOB_PER  (AT91_CAST(AT91_REG *)         0x400E0E00) // (PIOB) PIO Enable Register\r
+#define AT91C_PIOB_ELSR (AT91_CAST(AT91_REG *)         0x400E0EC8) // (PIOB) Edge/Level Status Register\r
+#define AT91C_PIOB_IMR  (AT91_CAST(AT91_REG *)         0x400E0E48) // (PIOB) Interrupt Mask Register\r
+#define AT91C_PIOB_PPUSR (AT91_CAST(AT91_REG *)        0x400E0E68) // (PIOB) Pull-up Status Register\r
+#define AT91C_PIOB_SCDR (AT91_CAST(AT91_REG *)         0x400E0E8C) // (PIOB) Slow Clock Divider Debouncing Register\r
+#define AT91C_PIOB_KSR  (AT91_CAST(AT91_REG *)         0x400E0F3C) // (PIOB) Keypad Controller Status Register\r
+#define AT91C_PIOB_IFDGSR (AT91_CAST(AT91_REG *)       0x400E0E88) // (PIOB) Glitch or Debouncing Input Filter Clock Selection Status Register\r
+#define AT91C_PIOB_ESR  (AT91_CAST(AT91_REG *)         0x400E0EC0) // (PIOB) Edge Select Register\r
+#define AT91C_PIOB_ODSR (AT91_CAST(AT91_REG *)         0x400E0E38) // (PIOB) Output Data Status Register\r
+#define AT91C_PIOB_IFDR (AT91_CAST(AT91_REG *)         0x400E0E24) // (PIOB) Input Filter Disable Register\r
+#define AT91C_PIOB_SODR (AT91_CAST(AT91_REG *)         0x400E0E30) // (PIOB) Set Output Data Register\r
+#define AT91C_PIOB_IER  (AT91_CAST(AT91_REG *)         0x400E0E40) // (PIOB) Interrupt Enable Register\r
+#define AT91C_PIOB_MDSR (AT91_CAST(AT91_REG *)         0x400E0E58) // (PIOB) Multi-driver Status Register\r
+#define AT91C_PIOB_ISR  (AT91_CAST(AT91_REG *)         0x400E0E4C) // (PIOB) Interrupt Status Register\r
+#define AT91C_PIOB_IFSR (AT91_CAST(AT91_REG *)         0x400E0E28) // (PIOB) Input Filter Status Register\r
+#define AT91C_PIOB_KER  (AT91_CAST(AT91_REG *)         0x400E0F20) // (PIOB) Keypad Controller Enable Register\r
+#define AT91C_PIOB_KKRR (AT91_CAST(AT91_REG *)         0x400E0F44) // (PIOB) Keypad Controller Key Release Register\r
+#define AT91C_PIOB_PPUER (AT91_CAST(AT91_REG *)        0x400E0E64) // (PIOB) Pull-up Enable Register\r
+#define AT91C_PIOB_LOCKSR (AT91_CAST(AT91_REG *)       0x400E0EE0) // (PIOB) Lock Status Register\r
+#define AT91C_PIOB_OWER (AT91_CAST(AT91_REG *)         0x400E0EA0) // (PIOB) Output Write Enable Register\r
+#define AT91C_PIOB_KIER (AT91_CAST(AT91_REG *)         0x400E0F30) // (PIOB) Keypad Controller Interrupt Enable Register\r
+#define AT91C_PIOB_MDDR (AT91_CAST(AT91_REG *)         0x400E0E54) // (PIOB) Multi-driver Disable Register\r
+#define AT91C_PIOB_KRCR (AT91_CAST(AT91_REG *)         0x400E0F24) // (PIOB) Keypad Controller Row Column Register\r
+#define AT91C_PIOB_CODR (AT91_CAST(AT91_REG *)         0x400E0E34) // (PIOB) Clear Output Data Register\r
+#define AT91C_PIOB_KDR  (AT91_CAST(AT91_REG *)         0x400E0F28) // (PIOB) Keypad Controller Debouncing Register\r
+#define AT91C_PIOB_AIMMR (AT91_CAST(AT91_REG *)        0x400E0EB8) // (PIOB) Additional Interrupt Modes Mask Register\r
+#define AT91C_PIOB_OER  (AT91_CAST(AT91_REG *)         0x400E0E10) // (PIOB) Output Enable Register\r
+#define AT91C_PIOB_OSR  (AT91_CAST(AT91_REG *)         0x400E0E18) // (PIOB) Output Status Register\r
+// ========== Register definition for PIOC peripheral ========== \r
+#define AT91C_PIOC_FELLSR (AT91_CAST(AT91_REG *)       0x400E10D0) // (PIOC) Falling Edge/Low Level Select Register\r
+#define AT91C_PIOC_FRLHSR (AT91_CAST(AT91_REG *)       0x400E10D8) // (PIOC) Fall/Rise - Low/High Status Register\r
+#define AT91C_PIOC_MDDR (AT91_CAST(AT91_REG *)         0x400E1054) // (PIOC) Multi-driver Disable Register\r
+#define AT91C_PIOC_IFDGSR (AT91_CAST(AT91_REG *)       0x400E1088) // (PIOC) Glitch or Debouncing Input Filter Clock Selection Status Register\r
+#define AT91C_PIOC_ABSR (AT91_CAST(AT91_REG *)         0x400E1070) // (PIOC) Peripheral AB Select Register\r
+#define AT91C_PIOC_KIMR (AT91_CAST(AT91_REG *)         0x400E1138) // (PIOC) Keypad Controller Interrupt Mask Register\r
+#define AT91C_PIOC_KRCR (AT91_CAST(AT91_REG *)         0x400E1124) // (PIOC) Keypad Controller Row Column Register\r
+#define AT91C_PIOC_ODSR (AT91_CAST(AT91_REG *)         0x400E1038) // (PIOC) Output Data Status Register\r
+#define AT91C_PIOC_OSR  (AT91_CAST(AT91_REG *)         0x400E1018) // (PIOC) Output Status Register\r
+#define AT91C_PIOC_IFER (AT91_CAST(AT91_REG *)         0x400E1020) // (PIOC) Input Filter Enable Register\r
+#define AT91C_PIOC_KKPR (AT91_CAST(AT91_REG *)         0x400E1140) // (PIOC) Keypad Controller Key Press Register\r
+#define AT91C_PIOC_MDSR (AT91_CAST(AT91_REG *)         0x400E1058) // (PIOC) Multi-driver Status Register\r
+#define AT91C_PIOC_IFDR (AT91_CAST(AT91_REG *)         0x400E1024) // (PIOC) Input Filter Disable Register\r
+#define AT91C_PIOC_MDER (AT91_CAST(AT91_REG *)         0x400E1050) // (PIOC) Multi-driver Enable Register\r
+#define AT91C_PIOC_SCDR (AT91_CAST(AT91_REG *)         0x400E108C) // (PIOC) Slow Clock Divider Debouncing Register\r
+#define AT91C_PIOC_SCIFSR (AT91_CAST(AT91_REG *)       0x400E1080) // (PIOC) System Clock Glitch Input Filter Select Register\r
+#define AT91C_PIOC_IER  (AT91_CAST(AT91_REG *)         0x400E1040) // (PIOC) Interrupt Enable Register\r
+#define AT91C_PIOC_KDR  (AT91_CAST(AT91_REG *)         0x400E1128) // (PIOC) Keypad Controller Debouncing Register\r
+#define AT91C_PIOC_OWDR (AT91_CAST(AT91_REG *)         0x400E10A4) // (PIOC) Output Write Disable Register\r
+#define AT91C_PIOC_IFSR (AT91_CAST(AT91_REG *)         0x400E1028) // (PIOC) Input Filter Status Register\r
+#define AT91C_PIOC_ISR  (AT91_CAST(AT91_REG *)         0x400E104C) // (PIOC) Interrupt Status Register\r
+#define AT91C_PIOC_PPUDR (AT91_CAST(AT91_REG *)        0x400E1060) // (PIOC) Pull-up Disable Register\r
+#define AT91C_PIOC_PDSR (AT91_CAST(AT91_REG *)         0x400E103C) // (PIOC) Pin Data Status Register\r
+#define AT91C_PIOC_KKRR (AT91_CAST(AT91_REG *)         0x400E1144) // (PIOC) Keypad Controller Key Release Register\r
+#define AT91C_PIOC_AIMDR (AT91_CAST(AT91_REG *)        0x400E10B4) // (PIOC) Additional Interrupt Modes Disables Register\r
+#define AT91C_PIOC_LSR  (AT91_CAST(AT91_REG *)         0x400E10C4) // (PIOC) Level Select Register\r
+#define AT91C_PIOC_PPUER (AT91_CAST(AT91_REG *)        0x400E1064) // (PIOC) Pull-up Enable Register\r
+#define AT91C_PIOC_AIMER (AT91_CAST(AT91_REG *)        0x400E10B0) // (PIOC) Additional Interrupt Modes Enable Register\r
+#define AT91C_PIOC_OER  (AT91_CAST(AT91_REG *)         0x400E1010) // (PIOC) Output Enable Register\r
+#define AT91C_PIOC_CODR (AT91_CAST(AT91_REG *)         0x400E1034) // (PIOC) Clear Output Data Register\r
+#define AT91C_PIOC_AIMMR (AT91_CAST(AT91_REG *)        0x400E10B8) // (PIOC) Additional Interrupt Modes Mask Register\r
+#define AT91C_PIOC_OWER (AT91_CAST(AT91_REG *)         0x400E10A0) // (PIOC) Output Write Enable Register\r
+#define AT91C_PIOC_VER  (AT91_CAST(AT91_REG *)         0x400E10FC) // (PIOC) PIO VERSION REGISTER \r
+#define AT91C_PIOC_IMR  (AT91_CAST(AT91_REG *)         0x400E1048) // (PIOC) Interrupt Mask Register\r
+#define AT91C_PIOC_PPUSR (AT91_CAST(AT91_REG *)        0x400E1068) // (PIOC) Pull-up Status Register\r
+#define AT91C_PIOC_IDR  (AT91_CAST(AT91_REG *)         0x400E1044) // (PIOC) Interrupt Disable Register\r
+#define AT91C_PIOC_DIFSR (AT91_CAST(AT91_REG *)        0x400E1084) // (PIOC) Debouncing Input Filter Select Register\r
+#define AT91C_PIOC_KIDR (AT91_CAST(AT91_REG *)         0x400E1134) // (PIOC) Keypad Controller Interrupt Disable Register\r
+#define AT91C_PIOC_KSR  (AT91_CAST(AT91_REG *)         0x400E113C) // (PIOC) Keypad Controller Status Register\r
+#define AT91C_PIOC_REHLSR (AT91_CAST(AT91_REG *)       0x400E10D4) // (PIOC) Rising Edge/ High Level Select Register\r
+#define AT91C_PIOC_ESR  (AT91_CAST(AT91_REG *)         0x400E10C0) // (PIOC) Edge Select Register\r
+#define AT91C_PIOC_KIER (AT91_CAST(AT91_REG *)         0x400E1130) // (PIOC) Keypad Controller Interrupt Enable Register\r
+#define AT91C_PIOC_ELSR (AT91_CAST(AT91_REG *)         0x400E10C8) // (PIOC) Edge/Level Status Register\r
+#define AT91C_PIOC_SODR (AT91_CAST(AT91_REG *)         0x400E1030) // (PIOC) Set Output Data Register\r
+#define AT91C_PIOC_PSR  (AT91_CAST(AT91_REG *)         0x400E1008) // (PIOC) PIO Status Register\r
+#define AT91C_PIOC_KER  (AT91_CAST(AT91_REG *)         0x400E1120) // (PIOC) Keypad Controller Enable Register\r
+#define AT91C_PIOC_ODR  (AT91_CAST(AT91_REG *)         0x400E1014) // (PIOC) Output Disable Registerr\r
+#define AT91C_PIOC_OWSR (AT91_CAST(AT91_REG *)         0x400E10A8) // (PIOC) Output Write Status Register\r
+#define AT91C_PIOC_PDR  (AT91_CAST(AT91_REG *)         0x400E1004) // (PIOC) PIO Disable Register\r
+#define AT91C_PIOC_LOCKSR (AT91_CAST(AT91_REG *)       0x400E10E0) // (PIOC) Lock Status Register\r
+#define AT91C_PIOC_PER  (AT91_CAST(AT91_REG *)         0x400E1000) // (PIOC) PIO Enable Register\r
+// ========== Register definition for PMC peripheral ========== \r
+#define AT91C_PMC_PLLAR (AT91_CAST(AT91_REG *)         0x400E0428) // (PMC) PLL Register\r
+#define AT91C_PMC_UCKR  (AT91_CAST(AT91_REG *)         0x400E041C) // (PMC) UTMI Clock Configuration Register\r
+#define AT91C_PMC_FSMR  (AT91_CAST(AT91_REG *)         0x400E0470) // (PMC) Fast Startup Mode Register\r
+#define AT91C_PMC_MCKR  (AT91_CAST(AT91_REG *)         0x400E0430) // (PMC) Master Clock Register\r
+#define AT91C_PMC_SCER  (AT91_CAST(AT91_REG *)         0x400E0400) // (PMC) System Clock Enable Register\r
+#define AT91C_PMC_PCSR  (AT91_CAST(AT91_REG *)         0x400E0418) // (PMC) Peripheral Clock Status Register\r
+#define AT91C_PMC_MCFR  (AT91_CAST(AT91_REG *)         0x400E0424) // (PMC) Main Clock  Frequency Register\r
+#define AT91C_PMC_FOCR  (AT91_CAST(AT91_REG *)         0x400E0478) // (PMC) Fault Output Clear Register\r
+#define AT91C_PMC_FSPR  (AT91_CAST(AT91_REG *)         0x400E0474) // (PMC) Fast Startup Polarity Register\r
+#define AT91C_PMC_SCSR  (AT91_CAST(AT91_REG *)         0x400E0408) // (PMC) System Clock Status Register\r
+#define AT91C_PMC_IDR   (AT91_CAST(AT91_REG *)         0x400E0464) // (PMC) Interrupt Disable Register\r
+#define AT91C_PMC_VER   (AT91_CAST(AT91_REG *)         0x400E04FC) // (PMC) APMC VERSION REGISTER\r
+#define AT91C_PMC_IMR   (AT91_CAST(AT91_REG *)         0x400E046C) // (PMC) Interrupt Mask Register\r
+#define AT91C_PMC_IPNAME2 (AT91_CAST(AT91_REG *)       0x400E04F4) // (PMC) PMC IPNAME2 REGISTER \r
+#define AT91C_PMC_SCDR  (AT91_CAST(AT91_REG *)         0x400E0404) // (PMC) System Clock Disable Register\r
+#define AT91C_PMC_PCKR  (AT91_CAST(AT91_REG *)         0x400E0440) // (PMC) Programmable Clock Register\r
+#define AT91C_PMC_ADDRSIZE (AT91_CAST(AT91_REG *)      0x400E04EC) // (PMC) PMC ADDRSIZE REGISTER \r
+#define AT91C_PMC_PCDR  (AT91_CAST(AT91_REG *)         0x400E0414) // (PMC) Peripheral Clock Disable Register\r
+#define AT91C_PMC_MOR   (AT91_CAST(AT91_REG *)         0x400E0420) // (PMC) Main Oscillator Register\r
+#define AT91C_PMC_SR    (AT91_CAST(AT91_REG *)         0x400E0468) // (PMC) Status Register\r
+#define AT91C_PMC_IER   (AT91_CAST(AT91_REG *)         0x400E0460) // (PMC) Interrupt Enable Register\r
+#define AT91C_PMC_IPNAME1 (AT91_CAST(AT91_REG *)       0x400E04F0) // (PMC) PMC IPNAME1 REGISTER \r
+#define AT91C_PMC_PCER  (AT91_CAST(AT91_REG *)         0x400E0410) // (PMC) Peripheral Clock Enable Register\r
+#define AT91C_PMC_FEATURES (AT91_CAST(AT91_REG *)      0x400E04F8) // (PMC) PMC FEATURES REGISTER \r
+// ========== Register definition for CKGR peripheral ========== \r
+#define AT91C_CKGR_PLLAR (AT91_CAST(AT91_REG *)        0x400E0428) // (CKGR) PLL Register\r
+#define AT91C_CKGR_UCKR (AT91_CAST(AT91_REG *)         0x400E041C) // (CKGR) UTMI Clock Configuration Register\r
+#define AT91C_CKGR_MOR  (AT91_CAST(AT91_REG *)         0x400E0420) // (CKGR) Main Oscillator Register\r
+#define AT91C_CKGR_MCFR (AT91_CAST(AT91_REG *)         0x400E0424) // (CKGR) Main Clock  Frequency Register\r
+// ========== Register definition for RSTC peripheral ========== \r
+#define AT91C_RSTC_VER  (AT91_CAST(AT91_REG *)         0x400E12FC) // (RSTC) Version Register\r
+#define AT91C_RSTC_RCR  (AT91_CAST(AT91_REG *)         0x400E1200) // (RSTC) Reset Control Register\r
+#define AT91C_RSTC_RMR  (AT91_CAST(AT91_REG *)         0x400E1208) // (RSTC) Reset Mode Register\r
+#define AT91C_RSTC_RSR  (AT91_CAST(AT91_REG *)         0x400E1204) // (RSTC) Reset Status Register\r
+// ========== Register definition for SUPC peripheral ========== \r
+#define AT91C_SUPC_WUIR (AT91_CAST(AT91_REG *)         0x400E1220) // (SUPC) Wake Up Inputs Register\r
+#define AT91C_SUPC_CR   (AT91_CAST(AT91_REG *)         0x400E1210) // (SUPC) Control Register\r
+#define AT91C_SUPC_MR   (AT91_CAST(AT91_REG *)         0x400E1218) // (SUPC) Mode Register\r
+#define AT91C_SUPC_FWUTR (AT91_CAST(AT91_REG *)        0x400E1228) // (SUPC) Flash Wake-up Timer Register\r
+#define AT91C_SUPC_SR   (AT91_CAST(AT91_REG *)         0x400E1224) // (SUPC) Status Register\r
+#define AT91C_SUPC_WUMR (AT91_CAST(AT91_REG *)         0x400E121C) // (SUPC) Wake Up Mode Register\r
+#define AT91C_SUPC_BOMR (AT91_CAST(AT91_REG *)         0x400E1214) // (SUPC) Brown Out Mode Register\r
+// ========== Register definition for RTTC peripheral ========== \r
+#define AT91C_RTTC_RTVR (AT91_CAST(AT91_REG *)         0x400E1238) // (RTTC) Real-time Value Register\r
+#define AT91C_RTTC_RTAR (AT91_CAST(AT91_REG *)         0x400E1234) // (RTTC) Real-time Alarm Register\r
+#define AT91C_RTTC_RTMR (AT91_CAST(AT91_REG *)         0x400E1230) // (RTTC) Real-time Mode Register\r
+#define AT91C_RTTC_RTSR (AT91_CAST(AT91_REG *)         0x400E123C) // (RTTC) Real-time Status Register\r
+// ========== Register definition for WDTC peripheral ========== \r
+#define AT91C_WDTC_WDSR (AT91_CAST(AT91_REG *)         0x400E1258) // (WDTC) Watchdog Status Register\r
+#define AT91C_WDTC_WDMR (AT91_CAST(AT91_REG *)         0x400E1254) // (WDTC) Watchdog Mode Register\r
+#define AT91C_WDTC_WDCR (AT91_CAST(AT91_REG *)         0x400E1250) // (WDTC) Watchdog Control Register\r
+// ========== Register definition for RTC peripheral ========== \r
+#define AT91C_RTC_IMR   (AT91_CAST(AT91_REG *)         0x400E1288) // (RTC) Interrupt Mask Register\r
+#define AT91C_RTC_SCCR  (AT91_CAST(AT91_REG *)         0x400E127C) // (RTC) Status Clear Command Register\r
+#define AT91C_RTC_CALR  (AT91_CAST(AT91_REG *)         0x400E126C) // (RTC) Calendar Register\r
+#define AT91C_RTC_MR    (AT91_CAST(AT91_REG *)         0x400E1264) // (RTC) Mode Register\r
+#define AT91C_RTC_TIMR  (AT91_CAST(AT91_REG *)         0x400E1268) // (RTC) Time Register\r
+#define AT91C_RTC_CALALR (AT91_CAST(AT91_REG *)        0x400E1274) // (RTC) Calendar Alarm Register\r
+#define AT91C_RTC_VER   (AT91_CAST(AT91_REG *)         0x400E128C) // (RTC) Valid Entry Register\r
+#define AT91C_RTC_CR    (AT91_CAST(AT91_REG *)         0x400E1260) // (RTC) Control Register\r
+#define AT91C_RTC_IDR   (AT91_CAST(AT91_REG *)         0x400E1284) // (RTC) Interrupt Disable Register\r
+#define AT91C_RTC_TIMALR (AT91_CAST(AT91_REG *)        0x400E1270) // (RTC) Time Alarm Register\r
+#define AT91C_RTC_IER   (AT91_CAST(AT91_REG *)         0x400E1280) // (RTC) Interrupt Enable Register\r
+#define AT91C_RTC_SR    (AT91_CAST(AT91_REG *)         0x400E1278) // (RTC) Status Register\r
+// ========== Register definition for ADC0 peripheral ========== \r
+#define AT91C_ADC0_CDR4 (AT91_CAST(AT91_REG *)         0x400A8040) // (ADC0) ADC Channel Data Register 4\r
+#define AT91C_ADC0_CDR2 (AT91_CAST(AT91_REG *)         0x400A8038) // (ADC0) ADC Channel Data Register 2\r
+#define AT91C_ADC0_CHER (AT91_CAST(AT91_REG *)         0x400A8010) // (ADC0) ADC Channel Enable Register\r
+#define AT91C_ADC0_SR   (AT91_CAST(AT91_REG *)         0x400A801C) // (ADC0) ADC Status Register\r
+#define AT91C_ADC0_IPNAME1 (AT91_CAST(AT91_REG *)      0x400A80F0) // (ADC0) ADC IPNAME1 REGISTER \r
+#define AT91C_ADC0_IER  (AT91_CAST(AT91_REG *)         0x400A8024) // (ADC0) ADC Interrupt Enable Register\r
+#define AT91C_ADC0_CR   (AT91_CAST(AT91_REG *)         0x400A8000) // (ADC0) ADC Control Register\r
+#define AT91C_ADC0_CDR6 (AT91_CAST(AT91_REG *)         0x400A8048) // (ADC0) ADC Channel Data Register 6\r
+#define AT91C_ADC0_CHDR (AT91_CAST(AT91_REG *)         0x400A8014) // (ADC0) ADC Channel Disable Register\r
+#define AT91C_ADC0_CDR3 (AT91_CAST(AT91_REG *)         0x400A803C) // (ADC0) ADC Channel Data Register 3\r
+#define AT91C_ADC0_ACR  (AT91_CAST(AT91_REG *)         0x400A8064) // (ADC0) Analog Control Register\r
+#define AT91C_ADC0_IDR  (AT91_CAST(AT91_REG *)         0x400A8028) // (ADC0) ADC Interrupt Disable Register\r
+#define AT91C_ADC0_VER  (AT91_CAST(AT91_REG *)         0x400A80FC) // (ADC0) ADC VERSION REGISTER\r
+#define AT91C_ADC0_CDR7 (AT91_CAST(AT91_REG *)         0x400A804C) // (ADC0) ADC Channel Data Register 7\r
+#define AT91C_ADC0_CHSR (AT91_CAST(AT91_REG *)         0x400A8018) // (ADC0) ADC Channel Status Register\r
+#define AT91C_ADC0_CDR5 (AT91_CAST(AT91_REG *)         0x400A8044) // (ADC0) ADC Channel Data Register 5\r
+#define AT91C_ADC0_IPNAME2 (AT91_CAST(AT91_REG *)      0x400A80F4) // (ADC0) ADC IPNAME2 REGISTER \r
+#define AT91C_ADC0_MR   (AT91_CAST(AT91_REG *)         0x400A8004) // (ADC0) ADC Mode Register\r
+#define AT91C_ADC0_FEATURES (AT91_CAST(AT91_REG *)     0x400A80F8) // (ADC0) ADC FEATURES REGISTER \r
+#define AT91C_ADC0_EMR  (AT91_CAST(AT91_REG *)         0x400A8068) // (ADC0) Extended Mode Register\r
+#define AT91C_ADC0_CDR0 (AT91_CAST(AT91_REG *)         0x400A8030) // (ADC0) ADC Channel Data Register 0\r
+#define AT91C_ADC0_LCDR (AT91_CAST(AT91_REG *)         0x400A8020) // (ADC0) ADC Last Converted Data Register\r
+#define AT91C_ADC0_IMR  (AT91_CAST(AT91_REG *)         0x400A802C) // (ADC0) ADC Interrupt Mask Register\r
+#define AT91C_ADC0_ADDRSIZE (AT91_CAST(AT91_REG *)     0x400A80EC) // (ADC0) ADC ADDRSIZE REGISTER \r
+#define AT91C_ADC0_CDR1 (AT91_CAST(AT91_REG *)         0x400A8034) // (ADC0) ADC Channel Data Register 1\r
+// ========== Register definition for ADC1 peripheral ========== \r
+#define AT91C_ADC1_IPNAME2 (AT91_CAST(AT91_REG *)      0x400AC0F4) // (ADC1) ADC IPNAME2 REGISTER \r
+#define AT91C_ADC1_ADDRSIZE (AT91_CAST(AT91_REG *)     0x400AC0EC) // (ADC1) ADC ADDRSIZE REGISTER \r
+#define AT91C_ADC1_IDR  (AT91_CAST(AT91_REG *)         0x400AC028) // (ADC1) ADC Interrupt Disable Register\r
+#define AT91C_ADC1_CHSR (AT91_CAST(AT91_REG *)         0x400AC018) // (ADC1) ADC Channel Status Register\r
+#define AT91C_ADC1_FEATURES (AT91_CAST(AT91_REG *)     0x400AC0F8) // (ADC1) ADC FEATURES REGISTER \r
+#define AT91C_ADC1_CDR0 (AT91_CAST(AT91_REG *)         0x400AC030) // (ADC1) ADC Channel Data Register 0\r
+#define AT91C_ADC1_LCDR (AT91_CAST(AT91_REG *)         0x400AC020) // (ADC1) ADC Last Converted Data Register\r
+#define AT91C_ADC1_EMR  (AT91_CAST(AT91_REG *)         0x400AC068) // (ADC1) Extended Mode Register\r
+#define AT91C_ADC1_CDR3 (AT91_CAST(AT91_REG *)         0x400AC03C) // (ADC1) ADC Channel Data Register 3\r
+#define AT91C_ADC1_CDR7 (AT91_CAST(AT91_REG *)         0x400AC04C) // (ADC1) ADC Channel Data Register 7\r
+#define AT91C_ADC1_SR   (AT91_CAST(AT91_REG *)         0x400AC01C) // (ADC1) ADC Status Register\r
+#define AT91C_ADC1_ACR  (AT91_CAST(AT91_REG *)         0x400AC064) // (ADC1) Analog Control Register\r
+#define AT91C_ADC1_CDR5 (AT91_CAST(AT91_REG *)         0x400AC044) // (ADC1) ADC Channel Data Register 5\r
+#define AT91C_ADC1_IPNAME1 (AT91_CAST(AT91_REG *)      0x400AC0F0) // (ADC1) ADC IPNAME1 REGISTER \r
+#define AT91C_ADC1_CDR6 (AT91_CAST(AT91_REG *)         0x400AC048) // (ADC1) ADC Channel Data Register 6\r
+#define AT91C_ADC1_MR   (AT91_CAST(AT91_REG *)         0x400AC004) // (ADC1) ADC Mode Register\r
+#define AT91C_ADC1_CDR1 (AT91_CAST(AT91_REG *)         0x400AC034) // (ADC1) ADC Channel Data Register 1\r
+#define AT91C_ADC1_CDR2 (AT91_CAST(AT91_REG *)         0x400AC038) // (ADC1) ADC Channel Data Register 2\r
+#define AT91C_ADC1_CDR4 (AT91_CAST(AT91_REG *)         0x400AC040) // (ADC1) ADC Channel Data Register 4\r
+#define AT91C_ADC1_CHER (AT91_CAST(AT91_REG *)         0x400AC010) // (ADC1) ADC Channel Enable Register\r
+#define AT91C_ADC1_VER  (AT91_CAST(AT91_REG *)         0x400AC0FC) // (ADC1) ADC VERSION REGISTER\r
+#define AT91C_ADC1_CHDR (AT91_CAST(AT91_REG *)         0x400AC014) // (ADC1) ADC Channel Disable Register\r
+#define AT91C_ADC1_CR   (AT91_CAST(AT91_REG *)         0x400AC000) // (ADC1) ADC Control Register\r
+#define AT91C_ADC1_IMR  (AT91_CAST(AT91_REG *)         0x400AC02C) // (ADC1) ADC Interrupt Mask Register\r
+#define AT91C_ADC1_IER  (AT91_CAST(AT91_REG *)         0x400AC024) // (ADC1) ADC Interrupt Enable Register\r
+// ========== Register definition for TC0 peripheral ========== \r
+#define AT91C_TC0_IER   (AT91_CAST(AT91_REG *)         0x40080024) // (TC0) Interrupt Enable Register\r
+#define AT91C_TC0_CV    (AT91_CAST(AT91_REG *)         0x40080010) // (TC0) Counter Value\r
+#define AT91C_TC0_RA    (AT91_CAST(AT91_REG *)         0x40080014) // (TC0) Register A\r
+#define AT91C_TC0_RB    (AT91_CAST(AT91_REG *)         0x40080018) // (TC0) Register B\r
+#define AT91C_TC0_IDR   (AT91_CAST(AT91_REG *)         0x40080028) // (TC0) Interrupt Disable Register\r
+#define AT91C_TC0_SR    (AT91_CAST(AT91_REG *)         0x40080020) // (TC0) Status Register\r
+#define AT91C_TC0_IMR   (AT91_CAST(AT91_REG *)         0x4008002C) // (TC0) Interrupt Mask Register\r
+#define AT91C_TC0_CMR   (AT91_CAST(AT91_REG *)         0x40080004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode)\r
+#define AT91C_TC0_RC    (AT91_CAST(AT91_REG *)         0x4008001C) // (TC0) Register C\r
+#define AT91C_TC0_CCR   (AT91_CAST(AT91_REG *)         0x40080000) // (TC0) Channel Control Register\r
+// ========== Register definition for TC1 peripheral ========== \r
+#define AT91C_TC1_SR    (AT91_CAST(AT91_REG *)         0x40080060) // (TC1) Status Register\r
+#define AT91C_TC1_RA    (AT91_CAST(AT91_REG *)         0x40080054) // (TC1) Register A\r
+#define AT91C_TC1_IER   (AT91_CAST(AT91_REG *)         0x40080064) // (TC1) Interrupt Enable Register\r
+#define AT91C_TC1_RB    (AT91_CAST(AT91_REG *)         0x40080058) // (TC1) Register B\r
+#define AT91C_TC1_IDR   (AT91_CAST(AT91_REG *)         0x40080068) // (TC1) Interrupt Disable Register\r
+#define AT91C_TC1_CCR   (AT91_CAST(AT91_REG *)         0x40080040) // (TC1) Channel Control Register\r
+#define AT91C_TC1_IMR   (AT91_CAST(AT91_REG *)         0x4008006C) // (TC1) Interrupt Mask Register\r
+#define AT91C_TC1_RC    (AT91_CAST(AT91_REG *)         0x4008005C) // (TC1) Register C\r
+#define AT91C_TC1_CMR   (AT91_CAST(AT91_REG *)         0x40080044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode)\r
+#define AT91C_TC1_CV    (AT91_CAST(AT91_REG *)         0x40080050) // (TC1) Counter Value\r
+// ========== Register definition for TC2 peripheral ========== \r
+#define AT91C_TC2_RA    (AT91_CAST(AT91_REG *)         0x40080094) // (TC2) Register A\r
+#define AT91C_TC2_RB    (AT91_CAST(AT91_REG *)         0x40080098) // (TC2) Register B\r
+#define AT91C_TC2_CMR   (AT91_CAST(AT91_REG *)         0x40080084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode)\r
+#define AT91C_TC2_SR    (AT91_CAST(AT91_REG *)         0x400800A0) // (TC2) Status Register\r
+#define AT91C_TC2_CCR   (AT91_CAST(AT91_REG *)         0x40080080) // (TC2) Channel Control Register\r
+#define AT91C_TC2_IMR   (AT91_CAST(AT91_REG *)         0x400800AC) // (TC2) Interrupt Mask Register\r
+#define AT91C_TC2_CV    (AT91_CAST(AT91_REG *)         0x40080090) // (TC2) Counter Value\r
+#define AT91C_TC2_RC    (AT91_CAST(AT91_REG *)         0x4008009C) // (TC2) Register C\r
+#define AT91C_TC2_IER   (AT91_CAST(AT91_REG *)         0x400800A4) // (TC2) Interrupt Enable Register\r
+#define AT91C_TC2_IDR   (AT91_CAST(AT91_REG *)         0x400800A8) // (TC2) Interrupt Disable Register\r
+// ========== Register definition for TCB0 peripheral ========== \r
+#define AT91C_TCB0_BCR  (AT91_CAST(AT91_REG *)         0x400800C0) // (TCB0) TC Block Control Register\r
+#define AT91C_TCB0_IPNAME2 (AT91_CAST(AT91_REG *)      0x400800F4) // (TCB0) TC IPNAME2 REGISTER \r
+#define AT91C_TCB0_IPNAME1 (AT91_CAST(AT91_REG *)      0x400800F0) // (TCB0) TC IPNAME1 REGISTER \r
+#define AT91C_TCB0_ADDRSIZE (AT91_CAST(AT91_REG *)     0x400800EC) // (TCB0) TC ADDRSIZE REGISTER \r
+#define AT91C_TCB0_FEATURES (AT91_CAST(AT91_REG *)     0x400800F8) // (TCB0) TC FEATURES REGISTER \r
+#define AT91C_TCB0_BMR  (AT91_CAST(AT91_REG *)         0x400800C4) // (TCB0) TC Block Mode Register\r
+#define AT91C_TCB0_VER  (AT91_CAST(AT91_REG *)         0x400800FC) // (TCB0)  Version Register\r
+// ========== Register definition for TCB1 peripheral ========== \r
+#define AT91C_TCB1_BCR  (AT91_CAST(AT91_REG *)         0x40080100) // (TCB1) TC Block Control Register\r
+#define AT91C_TCB1_VER  (AT91_CAST(AT91_REG *)         0x4008013C) // (TCB1)  Version Register\r
+#define AT91C_TCB1_FEATURES (AT91_CAST(AT91_REG *)     0x40080138) // (TCB1) TC FEATURES REGISTER \r
+#define AT91C_TCB1_IPNAME2 (AT91_CAST(AT91_REG *)      0x40080134) // (TCB1) TC IPNAME2 REGISTER \r
+#define AT91C_TCB1_BMR  (AT91_CAST(AT91_REG *)         0x40080104) // (TCB1) TC Block Mode Register\r
+#define AT91C_TCB1_ADDRSIZE (AT91_CAST(AT91_REG *)     0x4008012C) // (TCB1) TC ADDRSIZE REGISTER \r
+#define AT91C_TCB1_IPNAME1 (AT91_CAST(AT91_REG *)      0x40080130) // (TCB1) TC IPNAME1 REGISTER \r
+// ========== Register definition for TCB2 peripheral ========== \r
+#define AT91C_TCB2_FEATURES (AT91_CAST(AT91_REG *)     0x40080178) // (TCB2) TC FEATURES REGISTER \r
+#define AT91C_TCB2_VER  (AT91_CAST(AT91_REG *)         0x4008017C) // (TCB2)  Version Register\r
+#define AT91C_TCB2_ADDRSIZE (AT91_CAST(AT91_REG *)     0x4008016C) // (TCB2) TC ADDRSIZE REGISTER \r
+#define AT91C_TCB2_IPNAME1 (AT91_CAST(AT91_REG *)      0x40080170) // (TCB2) TC IPNAME1 REGISTER \r
+#define AT91C_TCB2_IPNAME2 (AT91_CAST(AT91_REG *)      0x40080174) // (TCB2) TC IPNAME2 REGISTER \r
+#define AT91C_TCB2_BMR  (AT91_CAST(AT91_REG *)         0x40080144) // (TCB2) TC Block Mode Register\r
+#define AT91C_TCB2_BCR  (AT91_CAST(AT91_REG *)         0x40080140) // (TCB2) TC Block Control Register\r
+// ========== Register definition for EFC0 peripheral ========== \r
+#define AT91C_EFC0_FCR  (AT91_CAST(AT91_REG *)         0x400E0804) // (EFC0) EFC Flash Command Register\r
+#define AT91C_EFC0_FRR  (AT91_CAST(AT91_REG *)         0x400E080C) // (EFC0) EFC Flash Result Register\r
+#define AT91C_EFC0_FMR  (AT91_CAST(AT91_REG *)         0x400E0800) // (EFC0) EFC Flash Mode Register\r
+#define AT91C_EFC0_FSR  (AT91_CAST(AT91_REG *)         0x400E0808) // (EFC0) EFC Flash Status Register\r
+#define AT91C_EFC0_FVR  (AT91_CAST(AT91_REG *)         0x400E0814) // (EFC0) EFC Flash Version Register\r
+// ========== Register definition for EFC1 peripheral ========== \r
+#define AT91C_EFC1_FMR  (AT91_CAST(AT91_REG *)         0x400E0A00) // (EFC1) EFC Flash Mode Register\r
+#define AT91C_EFC1_FVR  (AT91_CAST(AT91_REG *)         0x400E0A14) // (EFC1) EFC Flash Version Register\r
+#define AT91C_EFC1_FSR  (AT91_CAST(AT91_REG *)         0x400E0A08) // (EFC1) EFC Flash Status Register\r
+#define AT91C_EFC1_FCR  (AT91_CAST(AT91_REG *)         0x400E0A04) // (EFC1) EFC Flash Command Register\r
+#define AT91C_EFC1_FRR  (AT91_CAST(AT91_REG *)         0x400E0A0C) // (EFC1) EFC Flash Result Register\r
+// ========== Register definition for MCI0 peripheral ========== \r
+#define AT91C_MCI0_DMA  (AT91_CAST(AT91_REG *)         0x40000050) // (MCI0) MCI DMA Configuration Register\r
+#define AT91C_MCI0_SDCR (AT91_CAST(AT91_REG *)         0x4000000C) // (MCI0) MCI SD/SDIO Card Register\r
+#define AT91C_MCI0_IPNAME1 (AT91_CAST(AT91_REG *)      0x400000F0) // (MCI0) MCI IPNAME1 REGISTER \r
+#define AT91C_MCI0_CSTOR (AT91_CAST(AT91_REG *)        0x4000001C) // (MCI0) MCI Completion Signal Timeout Register\r
+#define AT91C_MCI0_RDR  (AT91_CAST(AT91_REG *)         0x40000030) // (MCI0) MCI Receive Data Register\r
+#define AT91C_MCI0_CMDR (AT91_CAST(AT91_REG *)         0x40000014) // (MCI0) MCI Command Register\r
+#define AT91C_MCI0_IDR  (AT91_CAST(AT91_REG *)         0x40000048) // (MCI0) MCI Interrupt Disable Register\r
+#define AT91C_MCI0_ADDRSIZE (AT91_CAST(AT91_REG *)     0x400000EC) // (MCI0) MCI ADDRSIZE REGISTER \r
+#define AT91C_MCI0_WPCR (AT91_CAST(AT91_REG *)         0x400000E4) // (MCI0) MCI Write Protection Control Register\r
+#define AT91C_MCI0_RSPR (AT91_CAST(AT91_REG *)         0x40000020) // (MCI0) MCI Response Register\r
+#define AT91C_MCI0_IPNAME2 (AT91_CAST(AT91_REG *)      0x400000F4) // (MCI0) MCI IPNAME2 REGISTER \r
+#define AT91C_MCI0_CR   (AT91_CAST(AT91_REG *)         0x40000000) // (MCI0) MCI Control Register\r
+#define AT91C_MCI0_IMR  (AT91_CAST(AT91_REG *)         0x4000004C) // (MCI0) MCI Interrupt Mask Register\r
+#define AT91C_MCI0_WPSR (AT91_CAST(AT91_REG *)         0x400000E8) // (MCI0) MCI Write Protection Status Register\r
+#define AT91C_MCI0_DTOR (AT91_CAST(AT91_REG *)         0x40000008) // (MCI0) MCI Data Timeout Register\r
+#define AT91C_MCI0_MR   (AT91_CAST(AT91_REG *)         0x40000004) // (MCI0) MCI Mode Register\r
+#define AT91C_MCI0_SR   (AT91_CAST(AT91_REG *)         0x40000040) // (MCI0) MCI Status Register\r
+#define AT91C_MCI0_IER  (AT91_CAST(AT91_REG *)         0x40000044) // (MCI0) MCI Interrupt Enable Register\r
+#define AT91C_MCI0_VER  (AT91_CAST(AT91_REG *)         0x400000FC) // (MCI0) MCI VERSION REGISTER \r
+#define AT91C_MCI0_FEATURES (AT91_CAST(AT91_REG *)     0x400000F8) // (MCI0) MCI FEATURES REGISTER \r
+#define AT91C_MCI0_BLKR (AT91_CAST(AT91_REG *)         0x40000018) // (MCI0) MCI Block Register\r
+#define AT91C_MCI0_ARGR (AT91_CAST(AT91_REG *)         0x40000010) // (MCI0) MCI Argument Register\r
+#define AT91C_MCI0_FIFO (AT91_CAST(AT91_REG *)         0x40000200) // (MCI0) MCI FIFO Aperture Register\r
+#define AT91C_MCI0_TDR  (AT91_CAST(AT91_REG *)         0x40000034) // (MCI0) MCI Transmit Data Register\r
+#define AT91C_MCI0_CFG  (AT91_CAST(AT91_REG *)         0x40000054) // (MCI0) MCI Configuration Register\r
+// ========== Register definition for PDC_TWI0 peripheral ========== \r
+#define AT91C_TWI0_TNCR (AT91_CAST(AT91_REG *)         0x4008411C) // (PDC_TWI0) Transmit Next Counter Register\r
+#define AT91C_TWI0_PTCR (AT91_CAST(AT91_REG *)         0x40084120) // (PDC_TWI0) PDC Transfer Control Register\r
+#define AT91C_TWI0_PTSR (AT91_CAST(AT91_REG *)         0x40084124) // (PDC_TWI0) PDC Transfer Status Register\r
+#define AT91C_TWI0_RCR  (AT91_CAST(AT91_REG *)         0x40084104) // (PDC_TWI0) Receive Counter Register\r
+#define AT91C_TWI0_TNPR (AT91_CAST(AT91_REG *)         0x40084118) // (PDC_TWI0) Transmit Next Pointer Register\r
+#define AT91C_TWI0_RNPR (AT91_CAST(AT91_REG *)         0x40084110) // (PDC_TWI0) Receive Next Pointer Register\r
+#define AT91C_TWI0_RPR  (AT91_CAST(AT91_REG *)         0x40084100) // (PDC_TWI0) Receive Pointer Register\r
+#define AT91C_TWI0_RNCR (AT91_CAST(AT91_REG *)         0x40084114) // (PDC_TWI0) Receive Next Counter Register\r
+#define AT91C_TWI0_TPR  (AT91_CAST(AT91_REG *)         0x40084108) // (PDC_TWI0) Transmit Pointer Register\r
+#define AT91C_TWI0_TCR  (AT91_CAST(AT91_REG *)         0x4008410C) // (PDC_TWI0) Transmit Counter Register\r
+// ========== Register definition for PDC_TWI1 peripheral ========== \r
+#define AT91C_TWI1_TNCR (AT91_CAST(AT91_REG *)         0x4008811C) // (PDC_TWI1) Transmit Next Counter Register\r
+#define AT91C_TWI1_PTCR (AT91_CAST(AT91_REG *)         0x40088120) // (PDC_TWI1) PDC Transfer Control Register\r
+#define AT91C_TWI1_RNCR (AT91_CAST(AT91_REG *)         0x40088114) // (PDC_TWI1) Receive Next Counter Register\r
+#define AT91C_TWI1_RCR  (AT91_CAST(AT91_REG *)         0x40088104) // (PDC_TWI1) Receive Counter Register\r
+#define AT91C_TWI1_RPR  (AT91_CAST(AT91_REG *)         0x40088100) // (PDC_TWI1) Receive Pointer Register\r
+#define AT91C_TWI1_TNPR (AT91_CAST(AT91_REG *)         0x40088118) // (PDC_TWI1) Transmit Next Pointer Register\r
+#define AT91C_TWI1_RNPR (AT91_CAST(AT91_REG *)         0x40088110) // (PDC_TWI1) Receive Next Pointer Register\r
+#define AT91C_TWI1_TCR  (AT91_CAST(AT91_REG *)         0x4008810C) // (PDC_TWI1) Transmit Counter Register\r
+#define AT91C_TWI1_TPR  (AT91_CAST(AT91_REG *)         0x40088108) // (PDC_TWI1) Transmit Pointer Register\r
+#define AT91C_TWI1_PTSR (AT91_CAST(AT91_REG *)         0x40088124) // (PDC_TWI1) PDC Transfer Status Register\r
+// ========== Register definition for TWI0 peripheral ========== \r
+#define AT91C_TWI0_FEATURES (AT91_CAST(AT91_REG *)     0x400840F8) // (TWI0) TWI FEATURES REGISTER \r
+#define AT91C_TWI0_IPNAME1 (AT91_CAST(AT91_REG *)      0x400840F0) // (TWI0) TWI IPNAME1 REGISTER \r
+#define AT91C_TWI0_SMR  (AT91_CAST(AT91_REG *)         0x40084008) // (TWI0) Slave Mode Register\r
+#define AT91C_TWI0_MMR  (AT91_CAST(AT91_REG *)         0x40084004) // (TWI0) Master Mode Register\r
+#define AT91C_TWI0_SR   (AT91_CAST(AT91_REG *)         0x40084020) // (TWI0) Status Register\r
+#define AT91C_TWI0_IPNAME2 (AT91_CAST(AT91_REG *)      0x400840F4) // (TWI0) TWI IPNAME2 REGISTER \r
+#define AT91C_TWI0_CR   (AT91_CAST(AT91_REG *)         0x40084000) // (TWI0) Control Register\r
+#define AT91C_TWI0_IER  (AT91_CAST(AT91_REG *)         0x40084024) // (TWI0) Interrupt Enable Register\r
+#define AT91C_TWI0_RHR  (AT91_CAST(AT91_REG *)         0x40084030) // (TWI0) Receive Holding Register\r
+#define AT91C_TWI0_ADDRSIZE (AT91_CAST(AT91_REG *)     0x400840EC) // (TWI0) TWI ADDRSIZE REGISTER \r
+#define AT91C_TWI0_THR  (AT91_CAST(AT91_REG *)         0x40084034) // (TWI0) Transmit Holding Register\r
+#define AT91C_TWI0_VER  (AT91_CAST(AT91_REG *)         0x400840FC) // (TWI0) Version Register\r
+#define AT91C_TWI0_IADR (AT91_CAST(AT91_REG *)         0x4008400C) // (TWI0) Internal Address Register\r
+#define AT91C_TWI0_IMR  (AT91_CAST(AT91_REG *)         0x4008402C) // (TWI0) Interrupt Mask Register\r
+#define AT91C_TWI0_CWGR (AT91_CAST(AT91_REG *)         0x40084010) // (TWI0) Clock Waveform Generator Register\r
+#define AT91C_TWI0_IDR  (AT91_CAST(AT91_REG *)         0x40084028) // (TWI0) Interrupt Disable Register\r
+// ========== Register definition for TWI1 peripheral ========== \r
+#define AT91C_TWI1_VER  (AT91_CAST(AT91_REG *)         0x400880FC) // (TWI1) Version Register\r
+#define AT91C_TWI1_IDR  (AT91_CAST(AT91_REG *)         0x40088028) // (TWI1) Interrupt Disable Register\r
+#define AT91C_TWI1_IPNAME2 (AT91_CAST(AT91_REG *)      0x400880F4) // (TWI1) TWI IPNAME2 REGISTER \r
+#define AT91C_TWI1_CWGR (AT91_CAST(AT91_REG *)         0x40088010) // (TWI1) Clock Waveform Generator Register\r
+#define AT91C_TWI1_CR   (AT91_CAST(AT91_REG *)         0x40088000) // (TWI1) Control Register\r
+#define AT91C_TWI1_ADDRSIZE (AT91_CAST(AT91_REG *)     0x400880EC) // (TWI1) TWI ADDRSIZE REGISTER \r
+#define AT91C_TWI1_IADR (AT91_CAST(AT91_REG *)         0x4008800C) // (TWI1) Internal Address Register\r
+#define AT91C_TWI1_IER  (AT91_CAST(AT91_REG *)         0x40088024) // (TWI1) Interrupt Enable Register\r
+#define AT91C_TWI1_SMR  (AT91_CAST(AT91_REG *)         0x40088008) // (TWI1) Slave Mode Register\r
+#define AT91C_TWI1_RHR  (AT91_CAST(AT91_REG *)         0x40088030) // (TWI1) Receive Holding Register\r
+#define AT91C_TWI1_FEATURES (AT91_CAST(AT91_REG *)     0x400880F8) // (TWI1) TWI FEATURES REGISTER \r
+#define AT91C_TWI1_IMR  (AT91_CAST(AT91_REG *)         0x4008802C) // (TWI1) Interrupt Mask Register\r
+#define AT91C_TWI1_SR   (AT91_CAST(AT91_REG *)         0x40088020) // (TWI1) Status Register\r
+#define AT91C_TWI1_THR  (AT91_CAST(AT91_REG *)         0x40088034) // (TWI1) Transmit Holding Register\r
+#define AT91C_TWI1_MMR  (AT91_CAST(AT91_REG *)         0x40088004) // (TWI1) Master Mode Register\r
+#define AT91C_TWI1_IPNAME1 (AT91_CAST(AT91_REG *)      0x400880F0) // (TWI1) TWI IPNAME1 REGISTER \r
+// ========== Register definition for PDC_US0 peripheral ========== \r
+#define AT91C_US0_RNCR  (AT91_CAST(AT91_REG *)         0x40090114) // (PDC_US0) Receive Next Counter Register\r
+#define AT91C_US0_TNPR  (AT91_CAST(AT91_REG *)         0x40090118) // (PDC_US0) Transmit Next Pointer Register\r
+#define AT91C_US0_TPR   (AT91_CAST(AT91_REG *)         0x40090108) // (PDC_US0) Transmit Pointer Register\r
+#define AT91C_US0_RCR   (AT91_CAST(AT91_REG *)         0x40090104) // (PDC_US0) Receive Counter Register\r
+#define AT91C_US0_RNPR  (AT91_CAST(AT91_REG *)         0x40090110) // (PDC_US0) Receive Next Pointer Register\r
+#define AT91C_US0_TNCR  (AT91_CAST(AT91_REG *)         0x4009011C) // (PDC_US0) Transmit Next Counter Register\r
+#define AT91C_US0_PTSR  (AT91_CAST(AT91_REG *)         0x40090124) // (PDC_US0) PDC Transfer Status Register\r
+#define AT91C_US0_RPR   (AT91_CAST(AT91_REG *)         0x40090100) // (PDC_US0) Receive Pointer Register\r
+#define AT91C_US0_PTCR  (AT91_CAST(AT91_REG *)         0x40090120) // (PDC_US0) PDC Transfer Control Register\r
+#define AT91C_US0_TCR   (AT91_CAST(AT91_REG *)         0x4009010C) // (PDC_US0) Transmit Counter Register\r
+// ========== Register definition for US0 peripheral ========== \r
+#define AT91C_US0_NER   (AT91_CAST(AT91_REG *)         0x40090044) // (US0) Nb Errors Register\r
+#define AT91C_US0_RHR   (AT91_CAST(AT91_REG *)         0x40090018) // (US0) Receiver Holding Register\r
+#define AT91C_US0_IPNAME1 (AT91_CAST(AT91_REG *)       0x400900F0) // (US0) US IPNAME1 REGISTER \r
+#define AT91C_US0_MR    (AT91_CAST(AT91_REG *)         0x40090004) // (US0) Mode Register\r
+#define AT91C_US0_RTOR  (AT91_CAST(AT91_REG *)         0x40090024) // (US0) Receiver Time-out Register\r
+#define AT91C_US0_IF    (AT91_CAST(AT91_REG *)         0x4009004C) // (US0) IRDA_FILTER Register\r
+#define AT91C_US0_ADDRSIZE (AT91_CAST(AT91_REG *)      0x400900EC) // (US0) US ADDRSIZE REGISTER \r
+#define AT91C_US0_IDR   (AT91_CAST(AT91_REG *)         0x4009000C) // (US0) Interrupt Disable Register\r
+#define AT91C_US0_IMR   (AT91_CAST(AT91_REG *)         0x40090010) // (US0) Interrupt Mask Register\r
+#define AT91C_US0_IER   (AT91_CAST(AT91_REG *)         0x40090008) // (US0) Interrupt Enable Register\r
+#define AT91C_US0_TTGR  (AT91_CAST(AT91_REG *)         0x40090028) // (US0) Transmitter Time-guard Register\r
+#define AT91C_US0_IPNAME2 (AT91_CAST(AT91_REG *)       0x400900F4) // (US0) US IPNAME2 REGISTER \r
+#define AT91C_US0_FIDI  (AT91_CAST(AT91_REG *)         0x40090040) // (US0) FI_DI_Ratio Register\r
+#define AT91C_US0_CR    (AT91_CAST(AT91_REG *)         0x40090000) // (US0) Control Register\r
+#define AT91C_US0_BRGR  (AT91_CAST(AT91_REG *)         0x40090020) // (US0) Baud Rate Generator Register\r
+#define AT91C_US0_MAN   (AT91_CAST(AT91_REG *)         0x40090050) // (US0) Manchester Encoder Decoder Register\r
+#define AT91C_US0_VER   (AT91_CAST(AT91_REG *)         0x400900FC) // (US0) VERSION Register\r
+#define AT91C_US0_FEATURES (AT91_CAST(AT91_REG *)      0x400900F8) // (US0) US FEATURES REGISTER \r
+#define AT91C_US0_CSR   (AT91_CAST(AT91_REG *)         0x40090014) // (US0) Channel Status Register\r
+#define AT91C_US0_THR   (AT91_CAST(AT91_REG *)         0x4009001C) // (US0) Transmitter Holding Register\r
+// ========== Register definition for PDC_US1 peripheral ========== \r
+#define AT91C_US1_TNPR  (AT91_CAST(AT91_REG *)         0x40094118) // (PDC_US1) Transmit Next Pointer Register\r
+#define AT91C_US1_TPR   (AT91_CAST(AT91_REG *)         0x40094108) // (PDC_US1) Transmit Pointer Register\r
+#define AT91C_US1_RNCR  (AT91_CAST(AT91_REG *)         0x40094114) // (PDC_US1) Receive Next Counter Register\r
+#define AT91C_US1_TNCR  (AT91_CAST(AT91_REG *)         0x4009411C) // (PDC_US1) Transmit Next Counter Register\r
+#define AT91C_US1_RNPR  (AT91_CAST(AT91_REG *)         0x40094110) // (PDC_US1) Receive Next Pointer Register\r
+#define AT91C_US1_TCR   (AT91_CAST(AT91_REG *)         0x4009410C) // (PDC_US1) Transmit Counter Register\r
+#define AT91C_US1_PTSR  (AT91_CAST(AT91_REG *)         0x40094124) // (PDC_US1) PDC Transfer Status Register\r
+#define AT91C_US1_RCR   (AT91_CAST(AT91_REG *)         0x40094104) // (PDC_US1) Receive Counter Register\r
+#define AT91C_US1_RPR   (AT91_CAST(AT91_REG *)         0x40094100) // (PDC_US1) Receive Pointer Register\r
+#define AT91C_US1_PTCR  (AT91_CAST(AT91_REG *)         0x40094120) // (PDC_US1) PDC Transfer Control Register\r
+// ========== Register definition for US1 peripheral ========== \r
+#define AT91C_US1_IMR   (AT91_CAST(AT91_REG *)         0x40094010) // (US1) Interrupt Mask Register\r
+#define AT91C_US1_RTOR  (AT91_CAST(AT91_REG *)         0x40094024) // (US1) Receiver Time-out Register\r
+#define AT91C_US1_RHR   (AT91_CAST(AT91_REG *)         0x40094018) // (US1) Receiver Holding Register\r
+#define AT91C_US1_IPNAME1 (AT91_CAST(AT91_REG *)       0x400940F0) // (US1) US IPNAME1 REGISTER \r
+#define AT91C_US1_VER   (AT91_CAST(AT91_REG *)         0x400940FC) // (US1) VERSION Register\r
+#define AT91C_US1_MR    (AT91_CAST(AT91_REG *)         0x40094004) // (US1) Mode Register\r
+#define AT91C_US1_FEATURES (AT91_CAST(AT91_REG *)      0x400940F8) // (US1) US FEATURES REGISTER \r
+#define AT91C_US1_NER   (AT91_CAST(AT91_REG *)         0x40094044) // (US1) Nb Errors Register\r
+#define AT91C_US1_IPNAME2 (AT91_CAST(AT91_REG *)       0x400940F4) // (US1) US IPNAME2 REGISTER \r
+#define AT91C_US1_CR    (AT91_CAST(AT91_REG *)         0x40094000) // (US1) Control Register\r
+#define AT91C_US1_BRGR  (AT91_CAST(AT91_REG *)         0x40094020) // (US1) Baud Rate Generator Register\r
+#define AT91C_US1_IF    (AT91_CAST(AT91_REG *)         0x4009404C) // (US1) IRDA_FILTER Register\r
+#define AT91C_US1_IER   (AT91_CAST(AT91_REG *)         0x40094008) // (US1) Interrupt Enable Register\r
+#define AT91C_US1_TTGR  (AT91_CAST(AT91_REG *)         0x40094028) // (US1) Transmitter Time-guard Register\r
+#define AT91C_US1_FIDI  (AT91_CAST(AT91_REG *)         0x40094040) // (US1) FI_DI_Ratio Register\r
+#define AT91C_US1_MAN   (AT91_CAST(AT91_REG *)         0x40094050) // (US1) Manchester Encoder Decoder Register\r
+#define AT91C_US1_ADDRSIZE (AT91_CAST(AT91_REG *)      0x400940EC) // (US1) US ADDRSIZE REGISTER \r
+#define AT91C_US1_CSR   (AT91_CAST(AT91_REG *)         0x40094014) // (US1) Channel Status Register\r
+#define AT91C_US1_THR   (AT91_CAST(AT91_REG *)         0x4009401C) // (US1) Transmitter Holding Register\r
+#define AT91C_US1_IDR   (AT91_CAST(AT91_REG *)         0x4009400C) // (US1) Interrupt Disable Register\r
+// ========== Register definition for PDC_US2 peripheral ========== \r
+#define AT91C_US2_RPR   (AT91_CAST(AT91_REG *)         0x40098100) // (PDC_US2) Receive Pointer Register\r
+#define AT91C_US2_TPR   (AT91_CAST(AT91_REG *)         0x40098108) // (PDC_US2) Transmit Pointer Register\r
+#define AT91C_US2_TCR   (AT91_CAST(AT91_REG *)         0x4009810C) // (PDC_US2) Transmit Counter Register\r
+#define AT91C_US2_PTSR  (AT91_CAST(AT91_REG *)         0x40098124) // (PDC_US2) PDC Transfer Status Register\r
+#define AT91C_US2_PTCR  (AT91_CAST(AT91_REG *)         0x40098120) // (PDC_US2) PDC Transfer Control Register\r
+#define AT91C_US2_RNPR  (AT91_CAST(AT91_REG *)         0x40098110) // (PDC_US2) Receive Next Pointer Register\r
+#define AT91C_US2_TNCR  (AT91_CAST(AT91_REG *)         0x4009811C) // (PDC_US2) Transmit Next Counter Register\r
+#define AT91C_US2_RNCR  (AT91_CAST(AT91_REG *)         0x40098114) // (PDC_US2) Receive Next Counter Register\r
+#define AT91C_US2_TNPR  (AT91_CAST(AT91_REG *)         0x40098118) // (PDC_US2) Transmit Next Pointer Register\r
+#define AT91C_US2_RCR   (AT91_CAST(AT91_REG *)         0x40098104) // (PDC_US2) Receive Counter Register\r
+// ========== Register definition for US2 peripheral ========== \r
+#define AT91C_US2_MAN   (AT91_CAST(AT91_REG *)         0x40098050) // (US2) Manchester Encoder Decoder Register\r
+#define AT91C_US2_ADDRSIZE (AT91_CAST(AT91_REG *)      0x400980EC) // (US2) US ADDRSIZE REGISTER \r
+#define AT91C_US2_MR    (AT91_CAST(AT91_REG *)         0x40098004) // (US2) Mode Register\r
+#define AT91C_US2_IPNAME1 (AT91_CAST(AT91_REG *)       0x400980F0) // (US2) US IPNAME1 REGISTER \r
+#define AT91C_US2_IF    (AT91_CAST(AT91_REG *)         0x4009804C) // (US2) IRDA_FILTER Register\r
+#define AT91C_US2_BRGR  (AT91_CAST(AT91_REG *)         0x40098020) // (US2) Baud Rate Generator Register\r
+#define AT91C_US2_FIDI  (AT91_CAST(AT91_REG *)         0x40098040) // (US2) FI_DI_Ratio Register\r
+#define AT91C_US2_IER   (AT91_CAST(AT91_REG *)         0x40098008) // (US2) Interrupt Enable Register\r
+#define AT91C_US2_RTOR  (AT91_CAST(AT91_REG *)         0x40098024) // (US2) Receiver Time-out Register\r
+#define AT91C_US2_CR    (AT91_CAST(AT91_REG *)         0x40098000) // (US2) Control Register\r
+#define AT91C_US2_THR   (AT91_CAST(AT91_REG *)         0x4009801C) // (US2) Transmitter Holding Register\r
+#define AT91C_US2_CSR   (AT91_CAST(AT91_REG *)         0x40098014) // (US2) Channel Status Register\r
+#define AT91C_US2_VER   (AT91_CAST(AT91_REG *)         0x400980FC) // (US2) VERSION Register\r
+#define AT91C_US2_FEATURES (AT91_CAST(AT91_REG *)      0x400980F8) // (US2) US FEATURES REGISTER \r
+#define AT91C_US2_IDR   (AT91_CAST(AT91_REG *)         0x4009800C) // (US2) Interrupt Disable Register\r
+#define AT91C_US2_TTGR  (AT91_CAST(AT91_REG *)         0x40098028) // (US2) Transmitter Time-guard Register\r
+#define AT91C_US2_IPNAME2 (AT91_CAST(AT91_REG *)       0x400980F4) // (US2) US IPNAME2 REGISTER \r
+#define AT91C_US2_RHR   (AT91_CAST(AT91_REG *)         0x40098018) // (US2) Receiver Holding Register\r
+#define AT91C_US2_NER   (AT91_CAST(AT91_REG *)         0x40098044) // (US2) Nb Errors Register\r
+#define AT91C_US2_IMR   (AT91_CAST(AT91_REG *)         0x40098010) // (US2) Interrupt Mask Register\r
+// ========== Register definition for PDC_US3 peripheral ========== \r
+#define AT91C_US3_TPR   (AT91_CAST(AT91_REG *)         0x4009C108) // (PDC_US3) Transmit Pointer Register\r
+#define AT91C_US3_PTCR  (AT91_CAST(AT91_REG *)         0x4009C120) // (PDC_US3) PDC Transfer Control Register\r
+#define AT91C_US3_TCR   (AT91_CAST(AT91_REG *)         0x4009C10C) // (PDC_US3) Transmit Counter Register\r
+#define AT91C_US3_RCR   (AT91_CAST(AT91_REG *)         0x4009C104) // (PDC_US3) Receive Counter Register\r
+#define AT91C_US3_RNCR  (AT91_CAST(AT91_REG *)         0x4009C114) // (PDC_US3) Receive Next Counter Register\r
+#define AT91C_US3_RNPR  (AT91_CAST(AT91_REG *)         0x4009C110) // (PDC_US3) Receive Next Pointer Register\r
+#define AT91C_US3_RPR   (AT91_CAST(AT91_REG *)         0x4009C100) // (PDC_US3) Receive Pointer Register\r
+#define AT91C_US3_PTSR  (AT91_CAST(AT91_REG *)         0x4009C124) // (PDC_US3) PDC Transfer Status Register\r
+#define AT91C_US3_TNCR  (AT91_CAST(AT91_REG *)         0x4009C11C) // (PDC_US3) Transmit Next Counter Register\r
+#define AT91C_US3_TNPR  (AT91_CAST(AT91_REG *)         0x4009C118) // (PDC_US3) Transmit Next Pointer Register\r
+// ========== Register definition for US3 peripheral ========== \r
+#define AT91C_US3_MAN   (AT91_CAST(AT91_REG *)         0x4009C050) // (US3) Manchester Encoder Decoder Register\r
+#define AT91C_US3_CSR   (AT91_CAST(AT91_REG *)         0x4009C014) // (US3) Channel Status Register\r
+#define AT91C_US3_BRGR  (AT91_CAST(AT91_REG *)         0x4009C020) // (US3) Baud Rate Generator Register\r
+#define AT91C_US3_IPNAME2 (AT91_CAST(AT91_REG *)       0x4009C0F4) // (US3) US IPNAME2 REGISTER \r
+#define AT91C_US3_RTOR  (AT91_CAST(AT91_REG *)         0x4009C024) // (US3) Receiver Time-out Register\r
+#define AT91C_US3_ADDRSIZE (AT91_CAST(AT91_REG *)      0x4009C0EC) // (US3) US ADDRSIZE REGISTER \r
+#define AT91C_US3_CR    (AT91_CAST(AT91_REG *)         0x4009C000) // (US3) Control Register\r
+#define AT91C_US3_IF    (AT91_CAST(AT91_REG *)         0x4009C04C) // (US3) IRDA_FILTER Register\r
+#define AT91C_US3_FEATURES (AT91_CAST(AT91_REG *)      0x4009C0F8) // (US3) US FEATURES REGISTER \r
+#define AT91C_US3_VER   (AT91_CAST(AT91_REG *)         0x4009C0FC) // (US3) VERSION Register\r
+#define AT91C_US3_RHR   (AT91_CAST(AT91_REG *)         0x4009C018) // (US3) Receiver Holding Register\r
+#define AT91C_US3_TTGR  (AT91_CAST(AT91_REG *)         0x4009C028) // (US3) Transmitter Time-guard Register\r
+#define AT91C_US3_NER   (AT91_CAST(AT91_REG *)         0x4009C044) // (US3) Nb Errors Register\r
+#define AT91C_US3_IMR   (AT91_CAST(AT91_REG *)         0x4009C010) // (US3) Interrupt Mask Register\r
+#define AT91C_US3_THR   (AT91_CAST(AT91_REG *)         0x4009C01C) // (US3) Transmitter Holding Register\r
+#define AT91C_US3_IDR   (AT91_CAST(AT91_REG *)         0x4009C00C) // (US3) Interrupt Disable Register\r
+#define AT91C_US3_MR    (AT91_CAST(AT91_REG *)         0x4009C004) // (US3) Mode Register\r
+#define AT91C_US3_IER   (AT91_CAST(AT91_REG *)         0x4009C008) // (US3) Interrupt Enable Register\r
+#define AT91C_US3_FIDI  (AT91_CAST(AT91_REG *)         0x4009C040) // (US3) FI_DI_Ratio Register\r
+#define AT91C_US3_IPNAME1 (AT91_CAST(AT91_REG *)       0x4009C0F0) // (US3) US IPNAME1 REGISTER \r
+// ========== Register definition for PDC_SSC0 peripheral ========== \r
+#define AT91C_SSC0_RNCR (AT91_CAST(AT91_REG *)         0x40004114) // (PDC_SSC0) Receive Next Counter Register\r
+#define AT91C_SSC0_TPR  (AT91_CAST(AT91_REG *)         0x40004108) // (PDC_SSC0) Transmit Pointer Register\r
+#define AT91C_SSC0_TCR  (AT91_CAST(AT91_REG *)         0x4000410C) // (PDC_SSC0) Transmit Counter Register\r
+#define AT91C_SSC0_PTCR (AT91_CAST(AT91_REG *)         0x40004120) // (PDC_SSC0) PDC Transfer Control Register\r
+#define AT91C_SSC0_TNPR (AT91_CAST(AT91_REG *)         0x40004118) // (PDC_SSC0) Transmit Next Pointer Register\r
+#define AT91C_SSC0_RPR  (AT91_CAST(AT91_REG *)         0x40004100) // (PDC_SSC0) Receive Pointer Register\r
+#define AT91C_SSC0_TNCR (AT91_CAST(AT91_REG *)         0x4000411C) // (PDC_SSC0) Transmit Next Counter Register\r
+#define AT91C_SSC0_RNPR (AT91_CAST(AT91_REG *)         0x40004110) // (PDC_SSC0) Receive Next Pointer Register\r
+#define AT91C_SSC0_RCR  (AT91_CAST(AT91_REG *)         0x40004104) // (PDC_SSC0) Receive Counter Register\r
+#define AT91C_SSC0_PTSR (AT91_CAST(AT91_REG *)         0x40004124) // (PDC_SSC0) PDC Transfer Status Register\r
+// ========== Register definition for SSC0 peripheral ========== \r
+#define AT91C_SSC0_FEATURES (AT91_CAST(AT91_REG *)     0x400040F8) // (SSC0) SSC FEATURES REGISTER \r
+#define AT91C_SSC0_IPNAME1 (AT91_CAST(AT91_REG *)      0x400040F0) // (SSC0) SSC IPNAME1 REGISTER \r
+#define AT91C_SSC0_CR   (AT91_CAST(AT91_REG *)         0x40004000) // (SSC0) Control Register\r
+#define AT91C_SSC0_ADDRSIZE (AT91_CAST(AT91_REG *)     0x400040EC) // (SSC0) SSC ADDRSIZE REGISTER \r
+#define AT91C_SSC0_RHR  (AT91_CAST(AT91_REG *)         0x40004020) // (SSC0) Receive Holding Register\r
+#define AT91C_SSC0_VER  (AT91_CAST(AT91_REG *)         0x400040FC) // (SSC0) Version Register\r
+#define AT91C_SSC0_TSHR (AT91_CAST(AT91_REG *)         0x40004034) // (SSC0) Transmit Sync Holding Register\r
+#define AT91C_SSC0_RFMR (AT91_CAST(AT91_REG *)         0x40004014) // (SSC0) Receive Frame Mode Register\r
+#define AT91C_SSC0_IDR  (AT91_CAST(AT91_REG *)         0x40004048) // (SSC0) Interrupt Disable Register\r
+#define AT91C_SSC0_TFMR (AT91_CAST(AT91_REG *)         0x4000401C) // (SSC0) Transmit Frame Mode Register\r
+#define AT91C_SSC0_RSHR (AT91_CAST(AT91_REG *)         0x40004030) // (SSC0) Receive Sync Holding Register\r
+#define AT91C_SSC0_TCMR (AT91_CAST(AT91_REG *)         0x40004018) // (SSC0) Transmit Clock Mode Register\r
+#define AT91C_SSC0_RCMR (AT91_CAST(AT91_REG *)         0x40004010) // (SSC0) Receive Clock ModeRegister\r
+#define AT91C_SSC0_SR   (AT91_CAST(AT91_REG *)         0x40004040) // (SSC0) Status Register\r
+#define AT91C_SSC0_IPNAME2 (AT91_CAST(AT91_REG *)      0x400040F4) // (SSC0) SSC IPNAME2 REGISTER \r
+#define AT91C_SSC0_THR  (AT91_CAST(AT91_REG *)         0x40004024) // (SSC0) Transmit Holding Register\r
+#define AT91C_SSC0_CMR  (AT91_CAST(AT91_REG *)         0x40004004) // (SSC0) Clock Mode Register\r
+#define AT91C_SSC0_IER  (AT91_CAST(AT91_REG *)         0x40004044) // (SSC0) Interrupt Enable Register\r
+#define AT91C_SSC0_IMR  (AT91_CAST(AT91_REG *)         0x4000404C) // (SSC0) Interrupt Mask Register\r
+// ========== Register definition for PDC_PWMC peripheral ========== \r
+#define AT91C_PWMC_TNCR (AT91_CAST(AT91_REG *)         0x4008C11C) // (PDC_PWMC) Transmit Next Counter Register\r
+#define AT91C_PWMC_TPR  (AT91_CAST(AT91_REG *)         0x4008C108) // (PDC_PWMC) Transmit Pointer Register\r
+#define AT91C_PWMC_RPR  (AT91_CAST(AT91_REG *)         0x4008C100) // (PDC_PWMC) Receive Pointer Register\r
+#define AT91C_PWMC_TCR  (AT91_CAST(AT91_REG *)         0x4008C10C) // (PDC_PWMC) Transmit Counter Register\r
+#define AT91C_PWMC_PTSR (AT91_CAST(AT91_REG *)         0x4008C124) // (PDC_PWMC) PDC Transfer Status Register\r
+#define AT91C_PWMC_RNPR (AT91_CAST(AT91_REG *)         0x4008C110) // (PDC_PWMC) Receive Next Pointer Register\r
+#define AT91C_PWMC_RCR  (AT91_CAST(AT91_REG *)         0x4008C104) // (PDC_PWMC) Receive Counter Register\r
+#define AT91C_PWMC_RNCR (AT91_CAST(AT91_REG *)         0x4008C114) // (PDC_PWMC) Receive Next Counter Register\r
+#define AT91C_PWMC_PTCR (AT91_CAST(AT91_REG *)         0x4008C120) // (PDC_PWMC) PDC Transfer Control Register\r
+#define AT91C_PWMC_TNPR (AT91_CAST(AT91_REG *)         0x4008C118) // (PDC_PWMC) Transmit Next Pointer Register\r
+// ========== Register definition for PWMC_CH0 peripheral ========== \r
+#define AT91C_PWMC_CH0_DTR (AT91_CAST(AT91_REG *)      0x4008C218) // (PWMC_CH0) Channel Dead Time Value Register\r
+#define AT91C_PWMC_CH0_CMR (AT91_CAST(AT91_REG *)      0x4008C200) // (PWMC_CH0) Channel Mode Register\r
+#define AT91C_PWMC_CH0_CCNTR (AT91_CAST(AT91_REG *)    0x4008C214) // (PWMC_CH0) Channel Counter Register\r
+#define AT91C_PWMC_CH0_CPRDR (AT91_CAST(AT91_REG *)    0x4008C20C) // (PWMC_CH0) Channel Period Register\r
+#define AT91C_PWMC_CH0_DTUPDR (AT91_CAST(AT91_REG *)   0x4008C21C) // (PWMC_CH0) Channel Dead Time Update Value Register\r
+#define AT91C_PWMC_CH0_CPRDUPDR (AT91_CAST(AT91_REG *)         0x4008C210) // (PWMC_CH0) Channel Period Update Register\r
+#define AT91C_PWMC_CH0_CDTYUPDR (AT91_CAST(AT91_REG *)         0x4008C208) // (PWMC_CH0) Channel Duty Cycle Update Register\r
+#define AT91C_PWMC_CH0_CDTYR (AT91_CAST(AT91_REG *)    0x4008C204) // (PWMC_CH0) Channel Duty Cycle Register\r
+// ========== Register definition for PWMC_CH1 peripheral ========== \r
+#define AT91C_PWMC_CH1_CCNTR (AT91_CAST(AT91_REG *)    0x4008C234) // (PWMC_CH1) Channel Counter Register\r
+#define AT91C_PWMC_CH1_DTR (AT91_CAST(AT91_REG *)      0x4008C238) // (PWMC_CH1) Channel Dead Time Value Register\r
+#define AT91C_PWMC_CH1_CDTYUPDR (AT91_CAST(AT91_REG *)         0x4008C228) // (PWMC_CH1) Channel Duty Cycle Update Register\r
+#define AT91C_PWMC_CH1_DTUPDR (AT91_CAST(AT91_REG *)   0x4008C23C) // (PWMC_CH1) Channel Dead Time Update Value Register\r
+#define AT91C_PWMC_CH1_CDTYR (AT91_CAST(AT91_REG *)    0x4008C224) // (PWMC_CH1) Channel Duty Cycle Register\r
+#define AT91C_PWMC_CH1_CPRDR (AT91_CAST(AT91_REG *)    0x4008C22C) // (PWMC_CH1) Channel Period Register\r
+#define AT91C_PWMC_CH1_CPRDUPDR (AT91_CAST(AT91_REG *)         0x4008C230) // (PWMC_CH1) Channel Period Update Register\r
+#define AT91C_PWMC_CH1_CMR (AT91_CAST(AT91_REG *)      0x4008C220) // (PWMC_CH1) Channel Mode Register\r
+// ========== Register definition for PWMC_CH2 peripheral ========== \r
+#define AT91C_PWMC_CH2_CDTYR (AT91_CAST(AT91_REG *)    0x4008C244) // (PWMC_CH2) Channel Duty Cycle Register\r
+#define AT91C_PWMC_CH2_DTUPDR (AT91_CAST(AT91_REG *)   0x4008C25C) // (PWMC_CH2) Channel Dead Time Update Value Register\r
+#define AT91C_PWMC_CH2_CCNTR (AT91_CAST(AT91_REG *)    0x4008C254) // (PWMC_CH2) Channel Counter Register\r
+#define AT91C_PWMC_CH2_CMR (AT91_CAST(AT91_REG *)      0x4008C240) // (PWMC_CH2) Channel Mode Register\r
+#define AT91C_PWMC_CH2_CPRDR (AT91_CAST(AT91_REG *)    0x4008C24C) // (PWMC_CH2) Channel Period Register\r
+#define AT91C_PWMC_CH2_CPRDUPDR (AT91_CAST(AT91_REG *)         0x4008C250) // (PWMC_CH2) Channel Period Update Register\r
+#define AT91C_PWMC_CH2_CDTYUPDR (AT91_CAST(AT91_REG *)         0x4008C248) // (PWMC_CH2) Channel Duty Cycle Update Register\r
+#define AT91C_PWMC_CH2_DTR (AT91_CAST(AT91_REG *)      0x4008C258) // (PWMC_CH2) Channel Dead Time Value Register\r
+// ========== Register definition for PWMC_CH3 peripheral ========== \r
+#define AT91C_PWMC_CH3_CPRDUPDR (AT91_CAST(AT91_REG *)         0x4008C270) // (PWMC_CH3) Channel Period Update Register\r
+#define AT91C_PWMC_CH3_DTR (AT91_CAST(AT91_REG *)      0x4008C278) // (PWMC_CH3) Channel Dead Time Value Register\r
+#define AT91C_PWMC_CH3_CDTYR (AT91_CAST(AT91_REG *)    0x4008C264) // (PWMC_CH3) Channel Duty Cycle Register\r
+#define AT91C_PWMC_CH3_DTUPDR (AT91_CAST(AT91_REG *)   0x4008C27C) // (PWMC_CH3) Channel Dead Time Update Value Register\r
+#define AT91C_PWMC_CH3_CDTYUPDR (AT91_CAST(AT91_REG *)         0x4008C268) // (PWMC_CH3) Channel Duty Cycle Update Register\r
+#define AT91C_PWMC_CH3_CCNTR (AT91_CAST(AT91_REG *)    0x4008C274) // (PWMC_CH3) Channel Counter Register\r
+#define AT91C_PWMC_CH3_CMR (AT91_CAST(AT91_REG *)      0x4008C260) // (PWMC_CH3) Channel Mode Register\r
+#define AT91C_PWMC_CH3_CPRDR (AT91_CAST(AT91_REG *)    0x4008C26C) // (PWMC_CH3) Channel Period Register\r
+// ========== Register definition for PWMC peripheral ========== \r
+#define AT91C_PWMC_CMP6MUPD (AT91_CAST(AT91_REG *)     0x4008C19C) // (PWMC) PWM Comparison Mode 6 Update Register\r
+#define AT91C_PWMC_ISR1 (AT91_CAST(AT91_REG *)         0x4008C01C) // (PWMC) PWMC Interrupt Status Register 1\r
+#define AT91C_PWMC_CMP5V (AT91_CAST(AT91_REG *)        0x4008C180) // (PWMC) PWM Comparison Value 5 Register\r
+#define AT91C_PWMC_CMP4MUPD (AT91_CAST(AT91_REG *)     0x4008C17C) // (PWMC) PWM Comparison Mode 4 Update Register\r
+#define AT91C_PWMC_FMR  (AT91_CAST(AT91_REG *)         0x4008C05C) // (PWMC) PWM Fault Mode Register\r
+#define AT91C_PWMC_CMP6V (AT91_CAST(AT91_REG *)        0x4008C190) // (PWMC) PWM Comparison Value 6 Register\r
+#define AT91C_PWMC_EL4MR (AT91_CAST(AT91_REG *)        0x4008C08C) // (PWMC) PWM Event Line 4 Mode Register\r
+#define AT91C_PWMC_UPCR (AT91_CAST(AT91_REG *)         0x4008C028) // (PWMC) PWM Update Control Register\r
+#define AT91C_PWMC_CMP1VUPD (AT91_CAST(AT91_REG *)     0x4008C144) // (PWMC) PWM Comparison Value 1 Update Register\r
+#define AT91C_PWMC_CMP0M (AT91_CAST(AT91_REG *)        0x4008C138) // (PWMC) PWM Comparison Mode 0 Register\r
+#define AT91C_PWMC_CMP5VUPD (AT91_CAST(AT91_REG *)     0x4008C184) // (PWMC) PWM Comparison Value 5 Update Register\r
+#define AT91C_PWMC_FPER3 (AT91_CAST(AT91_REG *)        0x4008C074) // (PWMC) PWM Fault Protection Enable Register 3\r
+#define AT91C_PWMC_OSCUPD (AT91_CAST(AT91_REG *)       0x4008C058) // (PWMC) PWM Output Selection Clear Update Register\r
+#define AT91C_PWMC_FPER1 (AT91_CAST(AT91_REG *)        0x4008C06C) // (PWMC) PWM Fault Protection Enable Register 1\r
+#define AT91C_PWMC_SCUPUPD (AT91_CAST(AT91_REG *)      0x4008C030) // (PWMC) PWM Update Period Update Register\r
+#define AT91C_PWMC_DIS  (AT91_CAST(AT91_REG *)         0x4008C008) // (PWMC) PWMC Disable Register\r
+#define AT91C_PWMC_IER1 (AT91_CAST(AT91_REG *)         0x4008C010) // (PWMC) PWMC Interrupt Enable Register 1\r
+#define AT91C_PWMC_IMR2 (AT91_CAST(AT91_REG *)         0x4008C03C) // (PWMC) PWMC Interrupt Mask Register 2\r
+#define AT91C_PWMC_CMP0V (AT91_CAST(AT91_REG *)        0x4008C130) // (PWMC) PWM Comparison Value 0 Register\r
+#define AT91C_PWMC_SR   (AT91_CAST(AT91_REG *)         0x4008C00C) // (PWMC) PWMC Status Register\r
+#define AT91C_PWMC_CMP4M (AT91_CAST(AT91_REG *)        0x4008C178) // (PWMC) PWM Comparison Mode 4 Register\r
+#define AT91C_PWMC_CMP3M (AT91_CAST(AT91_REG *)        0x4008C168) // (PWMC) PWM Comparison Mode 3 Register\r
+#define AT91C_PWMC_IER2 (AT91_CAST(AT91_REG *)         0x4008C034) // (PWMC) PWMC Interrupt Enable Register 2\r
+#define AT91C_PWMC_CMP3VUPD (AT91_CAST(AT91_REG *)     0x4008C164) // (PWMC) PWM Comparison Value 3 Update Register\r
+#define AT91C_PWMC_CMP2M (AT91_CAST(AT91_REG *)        0x4008C158) // (PWMC) PWM Comparison Mode 2 Register\r
+#define AT91C_PWMC_IDR2 (AT91_CAST(AT91_REG *)         0x4008C038) // (PWMC) PWMC Interrupt Disable Register 2\r
+#define AT91C_PWMC_EL2MR (AT91_CAST(AT91_REG *)        0x4008C084) // (PWMC) PWM Event Line 2 Mode Register\r
+#define AT91C_PWMC_CMP7V (AT91_CAST(AT91_REG *)        0x4008C1A0) // (PWMC) PWM Comparison Value 7 Register\r
+#define AT91C_PWMC_CMP1M (AT91_CAST(AT91_REG *)        0x4008C148) // (PWMC) PWM Comparison Mode 1 Register\r
+#define AT91C_PWMC_CMP0VUPD (AT91_CAST(AT91_REG *)     0x4008C134) // (PWMC) PWM Comparison Value 0 Update Register\r
+#define AT91C_PWMC_WPSR (AT91_CAST(AT91_REG *)         0x4008C0E8) // (PWMC) PWM Write Protection Status Register\r
+#define AT91C_PWMC_CMP6VUPD (AT91_CAST(AT91_REG *)     0x4008C194) // (PWMC) PWM Comparison Value 6 Update Register\r
+#define AT91C_PWMC_CMP1MUPD (AT91_CAST(AT91_REG *)     0x4008C14C) // (PWMC) PWM Comparison Mode 1 Update Register\r
+#define AT91C_PWMC_CMP1V (AT91_CAST(AT91_REG *)        0x4008C140) // (PWMC) PWM Comparison Value 1 Register\r
+#define AT91C_PWMC_FCR  (AT91_CAST(AT91_REG *)         0x4008C064) // (PWMC) PWM Fault Mode Clear Register\r
+#define AT91C_PWMC_VER  (AT91_CAST(AT91_REG *)         0x4008C0FC) // (PWMC) PWMC Version Register\r
+#define AT91C_PWMC_EL1MR (AT91_CAST(AT91_REG *)        0x4008C080) // (PWMC) PWM Event Line 1 Mode Register\r
+#define AT91C_PWMC_EL6MR (AT91_CAST(AT91_REG *)        0x4008C094) // (PWMC) PWM Event Line 6 Mode Register\r
+#define AT91C_PWMC_ISR2 (AT91_CAST(AT91_REG *)         0x4008C040) // (PWMC) PWMC Interrupt Status Register 2\r
+#define AT91C_PWMC_CMP4VUPD (AT91_CAST(AT91_REG *)     0x4008C174) // (PWMC) PWM Comparison Value 4 Update Register\r
+#define AT91C_PWMC_CMP5MUPD (AT91_CAST(AT91_REG *)     0x4008C18C) // (PWMC) PWM Comparison Mode 5 Update Register\r
+#define AT91C_PWMC_OS   (AT91_CAST(AT91_REG *)         0x4008C048) // (PWMC) PWM Output Selection Register\r
+#define AT91C_PWMC_FPV  (AT91_CAST(AT91_REG *)         0x4008C068) // (PWMC) PWM Fault Protection Value Register\r
+#define AT91C_PWMC_FPER2 (AT91_CAST(AT91_REG *)        0x4008C070) // (PWMC) PWM Fault Protection Enable Register 2\r
+#define AT91C_PWMC_EL7MR (AT91_CAST(AT91_REG *)        0x4008C098) // (PWMC) PWM Event Line 7 Mode Register\r
+#define AT91C_PWMC_OSSUPD (AT91_CAST(AT91_REG *)       0x4008C054) // (PWMC) PWM Output Selection Set Update Register\r
+#define AT91C_PWMC_FEATURES (AT91_CAST(AT91_REG *)     0x4008C0F8) // (PWMC) PWMC FEATURES REGISTER \r
+#define AT91C_PWMC_CMP2V (AT91_CAST(AT91_REG *)        0x4008C150) // (PWMC) PWM Comparison Value 2 Register\r
+#define AT91C_PWMC_FSR  (AT91_CAST(AT91_REG *)         0x4008C060) // (PWMC) PWM Fault Mode Status Register\r
+#define AT91C_PWMC_ADDRSIZE (AT91_CAST(AT91_REG *)     0x4008C0EC) // (PWMC) PWMC ADDRSIZE REGISTER \r
+#define AT91C_PWMC_OSC  (AT91_CAST(AT91_REG *)         0x4008C050) // (PWMC) PWM Output Selection Clear Register\r
+#define AT91C_PWMC_SCUP (AT91_CAST(AT91_REG *)         0x4008C02C) // (PWMC) PWM Update Period Register\r
+#define AT91C_PWMC_CMP7MUPD (AT91_CAST(AT91_REG *)     0x4008C1AC) // (PWMC) PWM Comparison Mode 7 Update Register\r
+#define AT91C_PWMC_CMP2VUPD (AT91_CAST(AT91_REG *)     0x4008C154) // (PWMC) PWM Comparison Value 2 Update Register\r
+#define AT91C_PWMC_FPER4 (AT91_CAST(AT91_REG *)        0x4008C078) // (PWMC) PWM Fault Protection Enable Register 4\r
+#define AT91C_PWMC_IMR1 (AT91_CAST(AT91_REG *)         0x4008C018) // (PWMC) PWMC Interrupt Mask Register 1\r
+#define AT91C_PWMC_EL3MR (AT91_CAST(AT91_REG *)        0x4008C088) // (PWMC) PWM Event Line 3 Mode Register\r
+#define AT91C_PWMC_CMP3V (AT91_CAST(AT91_REG *)        0x4008C160) // (PWMC) PWM Comparison Value 3 Register\r
+#define AT91C_PWMC_IPNAME1 (AT91_CAST(AT91_REG *)      0x4008C0F0) // (PWMC) PWMC IPNAME1 REGISTER \r
+#define AT91C_PWMC_OSS  (AT91_CAST(AT91_REG *)         0x4008C04C) // (PWMC) PWM Output Selection Set Register\r
+#define AT91C_PWMC_CMP0MUPD (AT91_CAST(AT91_REG *)     0x4008C13C) // (PWMC) PWM Comparison Mode 0 Update Register\r
+#define AT91C_PWMC_CMP2MUPD (AT91_CAST(AT91_REG *)     0x4008C15C) // (PWMC) PWM Comparison Mode 2 Update Register\r
+#define AT91C_PWMC_CMP4V (AT91_CAST(AT91_REG *)        0x4008C170) // (PWMC) PWM Comparison Value 4 Register\r
+#define AT91C_PWMC_ENA  (AT91_CAST(AT91_REG *)         0x4008C004) // (PWMC) PWMC Enable Register\r
+#define AT91C_PWMC_CMP3MUPD (AT91_CAST(AT91_REG *)     0x4008C16C) // (PWMC) PWM Comparison Mode 3 Update Register\r
+#define AT91C_PWMC_EL0MR (AT91_CAST(AT91_REG *)        0x4008C07C) // (PWMC) PWM Event Line 0 Mode Register\r
+#define AT91C_PWMC_OOV  (AT91_CAST(AT91_REG *)         0x4008C044) // (PWMC) PWM Output Override Value Register\r
+#define AT91C_PWMC_WPCR (AT91_CAST(AT91_REG *)         0x4008C0E4) // (PWMC) PWM Write Protection Enable Register\r
+#define AT91C_PWMC_CMP7M (AT91_CAST(AT91_REG *)        0x4008C1A8) // (PWMC) PWM Comparison Mode 7 Register\r
+#define AT91C_PWMC_CMP6M (AT91_CAST(AT91_REG *)        0x4008C198) // (PWMC) PWM Comparison Mode 6 Register\r
+#define AT91C_PWMC_CMP5M (AT91_CAST(AT91_REG *)        0x4008C188) // (PWMC) PWM Comparison Mode 5 Register\r
+#define AT91C_PWMC_IPNAME2 (AT91_CAST(AT91_REG *)      0x4008C0F4) // (PWMC) PWMC IPNAME2 REGISTER \r
+#define AT91C_PWMC_CMP7VUPD (AT91_CAST(AT91_REG *)     0x4008C1A4) // (PWMC) PWM Comparison Value 7 Update Register\r
+#define AT91C_PWMC_SYNC (AT91_CAST(AT91_REG *)         0x4008C020) // (PWMC) PWM Synchronized Channels Register\r
+#define AT91C_PWMC_MR   (AT91_CAST(AT91_REG *)         0x4008C000) // (PWMC) PWMC Mode Register\r
+#define AT91C_PWMC_IDR1 (AT91_CAST(AT91_REG *)         0x4008C014) // (PWMC) PWMC Interrupt Disable Register 1\r
+#define AT91C_PWMC_EL5MR (AT91_CAST(AT91_REG *)        0x4008C090) // (PWMC) PWM Event Line 5 Mode Register\r
+// ========== Register definition for SPI0 peripheral ========== \r
+#define AT91C_SPI0_ADDRSIZE (AT91_CAST(AT91_REG *)     0x400080EC) // (SPI0) SPI ADDRSIZE REGISTER \r
+#define AT91C_SPI0_RDR  (AT91_CAST(AT91_REG *)         0x40008008) // (SPI0) Receive Data Register\r
+#define AT91C_SPI0_FEATURES (AT91_CAST(AT91_REG *)     0x400080F8) // (SPI0) SPI FEATURES REGISTER \r
+#define AT91C_SPI0_CR   (AT91_CAST(AT91_REG *)         0x40008000) // (SPI0) Control Register\r
+#define AT91C_SPI0_IPNAME1 (AT91_CAST(AT91_REG *)      0x400080F0) // (SPI0) SPI IPNAME1 REGISTER \r
+#define AT91C_SPI0_VER  (AT91_CAST(AT91_REG *)         0x400080FC) // (SPI0) Version Register\r
+#define AT91C_SPI0_IDR  (AT91_CAST(AT91_REG *)         0x40008018) // (SPI0) Interrupt Disable Register\r
+#define AT91C_SPI0_TDR  (AT91_CAST(AT91_REG *)         0x4000800C) // (SPI0) Transmit Data Register\r
+#define AT91C_SPI0_MR   (AT91_CAST(AT91_REG *)         0x40008004) // (SPI0) Mode Register\r
+#define AT91C_SPI0_IER  (AT91_CAST(AT91_REG *)         0x40008014) // (SPI0) Interrupt Enable Register\r
+#define AT91C_SPI0_IMR  (AT91_CAST(AT91_REG *)         0x4000801C) // (SPI0) Interrupt Mask Register\r
+#define AT91C_SPI0_IPNAME2 (AT91_CAST(AT91_REG *)      0x400080F4) // (SPI0) SPI IPNAME2 REGISTER \r
+#define AT91C_SPI0_CSR  (AT91_CAST(AT91_REG *)         0x40008030) // (SPI0) Chip Select Register\r
+#define AT91C_SPI0_SR   (AT91_CAST(AT91_REG *)         0x40008010) // (SPI0) Status Register\r
+// ========== Register definition for UDPHS_EPTFIFO peripheral ========== \r
+#define AT91C_UDPHS_EPTFIFO_READEPT6 (AT91_CAST(AT91_REG *)    0x201E0000) // (UDPHS_EPTFIFO) FIFO Endpoint Data Register 6\r
+#define AT91C_UDPHS_EPTFIFO_READEPT2 (AT91_CAST(AT91_REG *)    0x201A0000) // (UDPHS_EPTFIFO) FIFO Endpoint Data Register 2\r
+#define AT91C_UDPHS_EPTFIFO_READEPT1 (AT91_CAST(AT91_REG *)    0x20190000) // (UDPHS_EPTFIFO) FIFO Endpoint Data Register 1\r
+#define AT91C_UDPHS_EPTFIFO_READEPT0 (AT91_CAST(AT91_REG *)    0x20180000) // (UDPHS_EPTFIFO) FIFO Endpoint Data Register 0\r
+#define AT91C_UDPHS_EPTFIFO_READEPT5 (AT91_CAST(AT91_REG *)    0x201D0000) // (UDPHS_EPTFIFO) FIFO Endpoint Data Register 5\r
+#define AT91C_UDPHS_EPTFIFO_READEPT4 (AT91_CAST(AT91_REG *)    0x201C0000) // (UDPHS_EPTFIFO) FIFO Endpoint Data Register 4\r
+#define AT91C_UDPHS_EPTFIFO_READEPT3 (AT91_CAST(AT91_REG *)    0x201B0000) // (UDPHS_EPTFIFO) FIFO Endpoint Data Register 3\r
+// ========== Register definition for UDPHS_EPT_0 peripheral ========== \r
+#define AT91C_UDPHS_EPT_0_EPTCTL (AT91_CAST(AT91_REG *)        0x400A410C) // (UDPHS_EPT_0) UDPHS Endpoint Control Register\r
+#define AT91C_UDPHS_EPT_0_EPTSTA (AT91_CAST(AT91_REG *)        0x400A411C) // (UDPHS_EPT_0) UDPHS Endpoint Status Register\r
+#define AT91C_UDPHS_EPT_0_EPTCLRSTA (AT91_CAST(AT91_REG *)     0x400A4118) // (UDPHS_EPT_0) UDPHS Endpoint Clear Status Register\r
+#define AT91C_UDPHS_EPT_0_EPTCTLDIS (AT91_CAST(AT91_REG *)     0x400A4108) // (UDPHS_EPT_0) UDPHS Endpoint Control Disable Register\r
+#define AT91C_UDPHS_EPT_0_EPTCFG (AT91_CAST(AT91_REG *)        0x400A4100) // (UDPHS_EPT_0) UDPHS Endpoint Config Register\r
+#define AT91C_UDPHS_EPT_0_EPTSETSTA (AT91_CAST(AT91_REG *)     0x400A4114) // (UDPHS_EPT_0) UDPHS Endpoint Set Status Register\r
+#define AT91C_UDPHS_EPT_0_EPTCTLENB (AT91_CAST(AT91_REG *)     0x400A4104) // (UDPHS_EPT_0) UDPHS Endpoint Control Enable Register\r
+// ========== Register definition for UDPHS_EPT_1 peripheral ========== \r
+#define AT91C_UDPHS_EPT_1_EPTSTA (AT91_CAST(AT91_REG *)        0x400A413C) // (UDPHS_EPT_1) UDPHS Endpoint Status Register\r
+#define AT91C_UDPHS_EPT_1_EPTSETSTA (AT91_CAST(AT91_REG *)     0x400A4134) // (UDPHS_EPT_1) UDPHS Endpoint Set Status Register\r
+#define AT91C_UDPHS_EPT_1_EPTCTL (AT91_CAST(AT91_REG *)        0x400A412C) // (UDPHS_EPT_1) UDPHS Endpoint Control Register\r
+#define AT91C_UDPHS_EPT_1_EPTCFG (AT91_CAST(AT91_REG *)        0x400A4120) // (UDPHS_EPT_1) UDPHS Endpoint Config Register\r
+#define AT91C_UDPHS_EPT_1_EPTCTLDIS (AT91_CAST(AT91_REG *)     0x400A4128) // (UDPHS_EPT_1) UDPHS Endpoint Control Disable Register\r
+#define AT91C_UDPHS_EPT_1_EPTCLRSTA (AT91_CAST(AT91_REG *)     0x400A4138) // (UDPHS_EPT_1) UDPHS Endpoint Clear Status Register\r
+#define AT91C_UDPHS_EPT_1_EPTCTLENB (AT91_CAST(AT91_REG *)     0x400A4124) // (UDPHS_EPT_1) UDPHS Endpoint Control Enable Register\r
+// ========== Register definition for UDPHS_EPT_2 peripheral ========== \r
+#define AT91C_UDPHS_EPT_2_EPTCTLENB (AT91_CAST(AT91_REG *)     0x400A4144) // (UDPHS_EPT_2) UDPHS Endpoint Control Enable Register\r
+#define AT91C_UDPHS_EPT_2_EPTCLRSTA (AT91_CAST(AT91_REG *)     0x400A4158) // (UDPHS_EPT_2) UDPHS Endpoint Clear Status Register\r
+#define AT91C_UDPHS_EPT_2_EPTCFG (AT91_CAST(AT91_REG *)        0x400A4140) // (UDPHS_EPT_2) UDPHS Endpoint Config Register\r
+#define AT91C_UDPHS_EPT_2_EPTCTL (AT91_CAST(AT91_REG *)        0x400A414C) // (UDPHS_EPT_2) UDPHS Endpoint Control Register\r
+#define AT91C_UDPHS_EPT_2_EPTSETSTA (AT91_CAST(AT91_REG *)     0x400A4154) // (UDPHS_EPT_2) UDPHS Endpoint Set Status Register\r
+#define AT91C_UDPHS_EPT_2_EPTSTA (AT91_CAST(AT91_REG *)        0x400A415C) // (UDPHS_EPT_2) UDPHS Endpoint Status Register\r
+#define AT91C_UDPHS_EPT_2_EPTCTLDIS (AT91_CAST(AT91_REG *)     0x400A4148) // (UDPHS_EPT_2) UDPHS Endpoint Control Disable Register\r
+// ========== Register definition for UDPHS_EPT_3 peripheral ========== \r
+#define AT91C_UDPHS_EPT_3_EPTCTLDIS (AT91_CAST(AT91_REG *)     0x400A4168) // (UDPHS_EPT_3) UDPHS Endpoint Control Disable Register\r
+#define AT91C_UDPHS_EPT_3_EPTCTLENB (AT91_CAST(AT91_REG *)     0x400A4164) // (UDPHS_EPT_3) UDPHS Endpoint Control Enable Register\r
+#define AT91C_UDPHS_EPT_3_EPTSETSTA (AT91_CAST(AT91_REG *)     0x400A4174) // (UDPHS_EPT_3) UDPHS Endpoint Set Status Register\r
+#define AT91C_UDPHS_EPT_3_EPTCLRSTA (AT91_CAST(AT91_REG *)     0x400A4178) // (UDPHS_EPT_3) UDPHS Endpoint Clear Status Register\r
+#define AT91C_UDPHS_EPT_3_EPTCFG (AT91_CAST(AT91_REG *)        0x400A4160) // (UDPHS_EPT_3) UDPHS Endpoint Config Register\r
+#define AT91C_UDPHS_EPT_3_EPTSTA (AT91_CAST(AT91_REG *)        0x400A417C) // (UDPHS_EPT_3) UDPHS Endpoint Status Register\r
+#define AT91C_UDPHS_EPT_3_EPTCTL (AT91_CAST(AT91_REG *)        0x400A416C) // (UDPHS_EPT_3) UDPHS Endpoint Control Register\r
+// ========== Register definition for UDPHS_EPT_4 peripheral ========== \r
+#define AT91C_UDPHS_EPT_4_EPTSETSTA (AT91_CAST(AT91_REG *)     0x400A4194) // (UDPHS_EPT_4) UDPHS Endpoint Set Status Register\r
+#define AT91C_UDPHS_EPT_4_EPTCTLDIS (AT91_CAST(AT91_REG *)     0x400A4188) // (UDPHS_EPT_4) UDPHS Endpoint Control Disable Register\r
+#define AT91C_UDPHS_EPT_4_EPTCTL (AT91_CAST(AT91_REG *)        0x400A418C) // (UDPHS_EPT_4) UDPHS Endpoint Control Register\r
+#define AT91C_UDPHS_EPT_4_EPTCFG (AT91_CAST(AT91_REG *)        0x400A4180) // (UDPHS_EPT_4) UDPHS Endpoint Config Register\r
+#define AT91C_UDPHS_EPT_4_EPTCTLENB (AT91_CAST(AT91_REG *)     0x400A4184) // (UDPHS_EPT_4) UDPHS Endpoint Control Enable Register\r
+#define AT91C_UDPHS_EPT_4_EPTSTA (AT91_CAST(AT91_REG *)        0x400A419C) // (UDPHS_EPT_4) UDPHS Endpoint Status Register\r
+#define AT91C_UDPHS_EPT_4_EPTCLRSTA (AT91_CAST(AT91_REG *)     0x400A4198) // (UDPHS_EPT_4) UDPHS Endpoint Clear Status Register\r
+// ========== Register definition for UDPHS_EPT_5 peripheral ========== \r
+#define AT91C_UDPHS_EPT_5_EPTCFG (AT91_CAST(AT91_REG *)        0x400A41A0) // (UDPHS_EPT_5) UDPHS Endpoint Config Register\r
+#define AT91C_UDPHS_EPT_5_EPTCTL (AT91_CAST(AT91_REG *)        0x400A41AC) // (UDPHS_EPT_5) UDPHS Endpoint Control Register\r
+#define AT91C_UDPHS_EPT_5_EPTCTLENB (AT91_CAST(AT91_REG *)     0x400A41A4) // (UDPHS_EPT_5) UDPHS Endpoint Control Enable Register\r
+#define AT91C_UDPHS_EPT_5_EPTSTA (AT91_CAST(AT91_REG *)        0x400A41BC) // (UDPHS_EPT_5) UDPHS Endpoint Status Register\r
+#define AT91C_UDPHS_EPT_5_EPTSETSTA (AT91_CAST(AT91_REG *)     0x400A41B4) // (UDPHS_EPT_5) UDPHS Endpoint Set Status Register\r
+#define AT91C_UDPHS_EPT_5_EPTCTLDIS (AT91_CAST(AT91_REG *)     0x400A41A8) // (UDPHS_EPT_5) UDPHS Endpoint Control Disable Register\r
+#define AT91C_UDPHS_EPT_5_EPTCLRSTA (AT91_CAST(AT91_REG *)     0x400A41B8) // (UDPHS_EPT_5) UDPHS Endpoint Clear Status Register\r
+// ========== Register definition for UDPHS_EPT_6 peripheral ========== \r
+#define AT91C_UDPHS_EPT_6_EPTCLRSTA (AT91_CAST(AT91_REG *)     0x400A41D8) // (UDPHS_EPT_6) UDPHS Endpoint Clear Status Register\r
+#define AT91C_UDPHS_EPT_6_EPTCTL (AT91_CAST(AT91_REG *)        0x400A41CC) // (UDPHS_EPT_6) UDPHS Endpoint Control Register\r
+#define AT91C_UDPHS_EPT_6_EPTCFG (AT91_CAST(AT91_REG *)        0x400A41C0) // (UDPHS_EPT_6) UDPHS Endpoint Config Register\r
+#define AT91C_UDPHS_EPT_6_EPTCTLDIS (AT91_CAST(AT91_REG *)     0x400A41C8) // (UDPHS_EPT_6) UDPHS Endpoint Control Disable Register\r
+#define AT91C_UDPHS_EPT_6_EPTSTA (AT91_CAST(AT91_REG *)        0x400A41DC) // (UDPHS_EPT_6) UDPHS Endpoint Status Register\r
+#define AT91C_UDPHS_EPT_6_EPTCTLENB (AT91_CAST(AT91_REG *)     0x400A41C4) // (UDPHS_EPT_6) UDPHS Endpoint Control Enable Register\r
+#define AT91C_UDPHS_EPT_6_EPTSETSTA (AT91_CAST(AT91_REG *)     0x400A41D4) // (UDPHS_EPT_6) UDPHS Endpoint Set Status Register\r
+// ========== Register definition for UDPHS_DMA_1 peripheral ========== \r
+#define AT91C_UDPHS_DMA_1_DMASTATUS (AT91_CAST(AT91_REG *)     0x400A431C) // (UDPHS_DMA_1) UDPHS DMA Channel Status Register\r
+#define AT91C_UDPHS_DMA_1_DMACONTROL (AT91_CAST(AT91_REG *)    0x400A4318) // (UDPHS_DMA_1) UDPHS DMA Channel Control Register\r
+#define AT91C_UDPHS_DMA_1_DMANXTDSC (AT91_CAST(AT91_REG *)     0x400A4310) // (UDPHS_DMA_1) UDPHS DMA Channel Next Descriptor Address\r
+#define AT91C_UDPHS_DMA_1_DMAADDRESS (AT91_CAST(AT91_REG *)    0x400A4314) // (UDPHS_DMA_1) UDPHS DMA Channel Address Register\r
+// ========== Register definition for UDPHS_DMA_2 peripheral ========== \r
+#define AT91C_UDPHS_DMA_2_DMASTATUS (AT91_CAST(AT91_REG *)     0x400A432C) // (UDPHS_DMA_2) UDPHS DMA Channel Status Register\r
+#define AT91C_UDPHS_DMA_2_DMANXTDSC (AT91_CAST(AT91_REG *)     0x400A4320) // (UDPHS_DMA_2) UDPHS DMA Channel Next Descriptor Address\r
+#define AT91C_UDPHS_DMA_2_DMACONTROL (AT91_CAST(AT91_REG *)    0x400A4328) // (UDPHS_DMA_2) UDPHS DMA Channel Control Register\r
+#define AT91C_UDPHS_DMA_2_DMAADDRESS (AT91_CAST(AT91_REG *)    0x400A4324) // (UDPHS_DMA_2) UDPHS DMA Channel Address Register\r
+// ========== Register definition for UDPHS_DMA_3 peripheral ========== \r
+#define AT91C_UDPHS_DMA_3_DMACONTROL (AT91_CAST(AT91_REG *)    0x400A4338) // (UDPHS_DMA_3) UDPHS DMA Channel Control Register\r
+#define AT91C_UDPHS_DMA_3_DMANXTDSC (AT91_CAST(AT91_REG *)     0x400A4330) // (UDPHS_DMA_3) UDPHS DMA Channel Next Descriptor Address\r
+#define AT91C_UDPHS_DMA_3_DMASTATUS (AT91_CAST(AT91_REG *)     0x400A433C) // (UDPHS_DMA_3) UDPHS DMA Channel Status Register\r
+#define AT91C_UDPHS_DMA_3_DMAADDRESS (AT91_CAST(AT91_REG *)    0x400A4334) // (UDPHS_DMA_3) UDPHS DMA Channel Address Register\r
+// ========== Register definition for UDPHS_DMA_4 peripheral ========== \r
+#define AT91C_UDPHS_DMA_4_DMAADDRESS (AT91_CAST(AT91_REG *)    0x400A4344) // (UDPHS_DMA_4) UDPHS DMA Channel Address Register\r
+#define AT91C_UDPHS_DMA_4_DMANXTDSC (AT91_CAST(AT91_REG *)     0x400A4340) // (UDPHS_DMA_4) UDPHS DMA Channel Next Descriptor Address\r
+#define AT91C_UDPHS_DMA_4_DMASTATUS (AT91_CAST(AT91_REG *)     0x400A434C) // (UDPHS_DMA_4) UDPHS DMA Channel Status Register\r
+#define AT91C_UDPHS_DMA_4_DMACONTROL (AT91_CAST(AT91_REG *)    0x400A4348) // (UDPHS_DMA_4) UDPHS DMA Channel Control Register\r
+// ========== Register definition for UDPHS_DMA_5 peripheral ========== \r
+#define AT91C_UDPHS_DMA_5_DMACONTROL (AT91_CAST(AT91_REG *)    0x400A4358) // (UDPHS_DMA_5) UDPHS DMA Channel Control Register\r
+#define AT91C_UDPHS_DMA_5_DMAADDRESS (AT91_CAST(AT91_REG *)    0x400A4354) // (UDPHS_DMA_5) UDPHS DMA Channel Address Register\r
+#define AT91C_UDPHS_DMA_5_DMANXTDSC (AT91_CAST(AT91_REG *)     0x400A4350) // (UDPHS_DMA_5) UDPHS DMA Channel Next Descriptor Address\r
+#define AT91C_UDPHS_DMA_5_DMASTATUS (AT91_CAST(AT91_REG *)     0x400A435C) // (UDPHS_DMA_5) UDPHS DMA Channel Status Register\r
+// ========== Register definition for UDPHS_DMA_6 peripheral ========== \r
+#define AT91C_UDPHS_DMA_6_DMASTATUS (AT91_CAST(AT91_REG *)     0x400A436C) // (UDPHS_DMA_6) UDPHS DMA Channel Status Register\r
+#define AT91C_UDPHS_DMA_6_DMACONTROL (AT91_CAST(AT91_REG *)    0x400A4368) // (UDPHS_DMA_6) UDPHS DMA Channel Control Register\r
+#define AT91C_UDPHS_DMA_6_DMANXTDSC (AT91_CAST(AT91_REG *)     0x400A4360) // (UDPHS_DMA_6) UDPHS DMA Channel Next Descriptor Address\r
+#define AT91C_UDPHS_DMA_6_DMAADDRESS (AT91_CAST(AT91_REG *)    0x400A4364) // (UDPHS_DMA_6) UDPHS DMA Channel Address Register\r
+// ========== Register definition for UDPHS peripheral ========== \r
+#define AT91C_UDPHS_EPTRST (AT91_CAST(AT91_REG *)      0x400A401C) // (UDPHS) UDPHS Endpoints Reset Register\r
+#define AT91C_UDPHS_IEN (AT91_CAST(AT91_REG *)         0x400A4010) // (UDPHS) UDPHS Interrupt Enable Register\r
+#define AT91C_UDPHS_TSTCNTB (AT91_CAST(AT91_REG *)     0x400A40D8) // (UDPHS) UDPHS Test B Counter Register\r
+#define AT91C_UDPHS_RIPNAME2 (AT91_CAST(AT91_REG *)    0x400A40F4) // (UDPHS) UDPHS Name2 Register\r
+#define AT91C_UDPHS_RIPPADDRSIZE (AT91_CAST(AT91_REG *)        0x400A40EC) // (UDPHS) UDPHS PADDRSIZE Register\r
+#define AT91C_UDPHS_TSTMODREG (AT91_CAST(AT91_REG *)   0x400A40DC) // (UDPHS) UDPHS Test Mode Register\r
+#define AT91C_UDPHS_TST (AT91_CAST(AT91_REG *)         0x400A40E0) // (UDPHS) UDPHS Test Register\r
+#define AT91C_UDPHS_TSTSOFCNT (AT91_CAST(AT91_REG *)   0x400A40D0) // (UDPHS) UDPHS Test SOF Counter Register\r
+#define AT91C_UDPHS_FNUM (AT91_CAST(AT91_REG *)        0x400A4004) // (UDPHS) UDPHS Frame Number Register\r
+#define AT91C_UDPHS_TSTCNTA (AT91_CAST(AT91_REG *)     0x400A40D4) // (UDPHS) UDPHS Test A Counter Register\r
+#define AT91C_UDPHS_INTSTA (AT91_CAST(AT91_REG *)      0x400A4014) // (UDPHS) UDPHS Interrupt Status Register\r
+#define AT91C_UDPHS_IPFEATURES (AT91_CAST(AT91_REG *)  0x400A40F8) // (UDPHS) UDPHS Features Register\r
+#define AT91C_UDPHS_CLRINT (AT91_CAST(AT91_REG *)      0x400A4018) // (UDPHS) UDPHS Clear Interrupt Register\r
+#define AT91C_UDPHS_RIPNAME1 (AT91_CAST(AT91_REG *)    0x400A40F0) // (UDPHS) UDPHS Name1 Register\r
+#define AT91C_UDPHS_CTRL (AT91_CAST(AT91_REG *)        0x400A4000) // (UDPHS) UDPHS Control Register\r
+#define AT91C_UDPHS_IPVERSION (AT91_CAST(AT91_REG *)   0x400A40FC) // (UDPHS) UDPHS Version Register\r
+// ========== Register definition for HDMA_CH_0 peripheral ========== \r
+#define AT91C_HDMA_CH_0_CADDR (AT91_CAST(AT91_REG *)   0x400B0060) // (HDMA_CH_0) HDMA Reserved\r
+#define AT91C_HDMA_CH_0_DADDR (AT91_CAST(AT91_REG *)   0x400B0040) // (HDMA_CH_0) HDMA Channel Destination Address Register\r
+#define AT91C_HDMA_CH_0_BDSCR (AT91_CAST(AT91_REG *)   0x400B005C) // (HDMA_CH_0) HDMA Reserved\r
+#define AT91C_HDMA_CH_0_CFG (AT91_CAST(AT91_REG *)     0x400B0050) // (HDMA_CH_0) HDMA Channel Configuration Register\r
+#define AT91C_HDMA_CH_0_CTRLB (AT91_CAST(AT91_REG *)   0x400B004C) // (HDMA_CH_0) HDMA Channel Control B Register\r
+#define AT91C_HDMA_CH_0_CTRLA (AT91_CAST(AT91_REG *)   0x400B0048) // (HDMA_CH_0) HDMA Channel Control A Register\r
+#define AT91C_HDMA_CH_0_DSCR (AT91_CAST(AT91_REG *)    0x400B0044) // (HDMA_CH_0) HDMA Channel Descriptor Address Register\r
+#define AT91C_HDMA_CH_0_SADDR (AT91_CAST(AT91_REG *)   0x400B003C) // (HDMA_CH_0) HDMA Channel Source Address Register\r
+#define AT91C_HDMA_CH_0_DPIP (AT91_CAST(AT91_REG *)    0x400B0058) // (HDMA_CH_0) HDMA Channel Destination Picture in Picture Configuration Register\r
+#define AT91C_HDMA_CH_0_SPIP (AT91_CAST(AT91_REG *)    0x400B0054) // (HDMA_CH_0) HDMA Channel Source Picture in Picture Configuration Register\r
+// ========== Register definition for HDMA_CH_1 peripheral ========== \r
+#define AT91C_HDMA_CH_1_DSCR (AT91_CAST(AT91_REG *)    0x400B006C) // (HDMA_CH_1) HDMA Channel Descriptor Address Register\r
+#define AT91C_HDMA_CH_1_BDSCR (AT91_CAST(AT91_REG *)   0x400B0084) // (HDMA_CH_1) HDMA Reserved\r
+#define AT91C_HDMA_CH_1_CTRLB (AT91_CAST(AT91_REG *)   0x400B0074) // (HDMA_CH_1) HDMA Channel Control B Register\r
+#define AT91C_HDMA_CH_1_SPIP (AT91_CAST(AT91_REG *)    0x400B007C) // (HDMA_CH_1) HDMA Channel Source Picture in Picture Configuration Register\r
+#define AT91C_HDMA_CH_1_SADDR (AT91_CAST(AT91_REG *)   0x400B0064) // (HDMA_CH_1) HDMA Channel Source Address Register\r
+#define AT91C_HDMA_CH_1_DPIP (AT91_CAST(AT91_REG *)    0x400B0080) // (HDMA_CH_1) HDMA Channel Destination Picture in Picture Configuration Register\r
+#define AT91C_HDMA_CH_1_CFG (AT91_CAST(AT91_REG *)     0x400B0078) // (HDMA_CH_1) HDMA Channel Configuration Register\r
+#define AT91C_HDMA_CH_1_DADDR (AT91_CAST(AT91_REG *)   0x400B0068) // (HDMA_CH_1) HDMA Channel Destination Address Register\r
+#define AT91C_HDMA_CH_1_CADDR (AT91_CAST(AT91_REG *)   0x400B0088) // (HDMA_CH_1) HDMA Reserved\r
+#define AT91C_HDMA_CH_1_CTRLA (AT91_CAST(AT91_REG *)   0x400B0070) // (HDMA_CH_1) HDMA Channel Control A Register\r
+// ========== Register definition for HDMA_CH_2 peripheral ========== \r
+#define AT91C_HDMA_CH_2_BDSCR (AT91_CAST(AT91_REG *)   0x400B00AC) // (HDMA_CH_2) HDMA Reserved\r
+#define AT91C_HDMA_CH_2_CTRLB (AT91_CAST(AT91_REG *)   0x400B009C) // (HDMA_CH_2) HDMA Channel Control B Register\r
+#define AT91C_HDMA_CH_2_CADDR (AT91_CAST(AT91_REG *)   0x400B00B0) // (HDMA_CH_2) HDMA Reserved\r
+#define AT91C_HDMA_CH_2_CFG (AT91_CAST(AT91_REG *)     0x400B00A0) // (HDMA_CH_2) HDMA Channel Configuration Register\r
+#define AT91C_HDMA_CH_2_CTRLA (AT91_CAST(AT91_REG *)   0x400B0098) // (HDMA_CH_2) HDMA Channel Control A Register\r
+#define AT91C_HDMA_CH_2_SADDR (AT91_CAST(AT91_REG *)   0x400B008C) // (HDMA_CH_2) HDMA Channel Source Address Register\r
+#define AT91C_HDMA_CH_2_DPIP (AT91_CAST(AT91_REG *)    0x400B00A8) // (HDMA_CH_2) HDMA Channel Destination Picture in Picture Configuration Register\r
+#define AT91C_HDMA_CH_2_DADDR (AT91_CAST(AT91_REG *)   0x400B0090) // (HDMA_CH_2) HDMA Channel Destination Address Register\r
+#define AT91C_HDMA_CH_2_SPIP (AT91_CAST(AT91_REG *)    0x400B00A4) // (HDMA_CH_2) HDMA Channel Source Picture in Picture Configuration Register\r
+#define AT91C_HDMA_CH_2_DSCR (AT91_CAST(AT91_REG *)    0x400B0094) // (HDMA_CH_2) HDMA Channel Descriptor Address Register\r
+// ========== Register definition for HDMA_CH_3 peripheral ========== \r
+#define AT91C_HDMA_CH_3_DSCR (AT91_CAST(AT91_REG *)    0x400B00BC) // (HDMA_CH_3) HDMA Channel Descriptor Address Register\r
+#define AT91C_HDMA_CH_3_SADDR (AT91_CAST(AT91_REG *)   0x400B00B4) // (HDMA_CH_3) HDMA Channel Source Address Register\r
+#define AT91C_HDMA_CH_3_BDSCR (AT91_CAST(AT91_REG *)   0x400B00D4) // (HDMA_CH_3) HDMA Reserved\r
+#define AT91C_HDMA_CH_3_CTRLA (AT91_CAST(AT91_REG *)   0x400B00C0) // (HDMA_CH_3) HDMA Channel Control A Register\r
+#define AT91C_HDMA_CH_3_DPIP (AT91_CAST(AT91_REG *)    0x400B00D0) // (HDMA_CH_3) HDMA Channel Destination Picture in Picture Configuration Register\r
+#define AT91C_HDMA_CH_3_CTRLB (AT91_CAST(AT91_REG *)   0x400B00C4) // (HDMA_CH_3) HDMA Channel Control B Register\r
+#define AT91C_HDMA_CH_3_SPIP (AT91_CAST(AT91_REG *)    0x400B00CC) // (HDMA_CH_3) HDMA Channel Source Picture in Picture Configuration Register\r
+#define AT91C_HDMA_CH_3_CFG (AT91_CAST(AT91_REG *)     0x400B00C8) // (HDMA_CH_3) HDMA Channel Configuration Register\r
+#define AT91C_HDMA_CH_3_CADDR (AT91_CAST(AT91_REG *)   0x400B00D8) // (HDMA_CH_3) HDMA Reserved\r
+#define AT91C_HDMA_CH_3_DADDR (AT91_CAST(AT91_REG *)   0x400B00B8) // (HDMA_CH_3) HDMA Channel Destination Address Register\r
+// ========== Register definition for HDMA peripheral ========== \r
+#define AT91C_HDMA_SYNC (AT91_CAST(AT91_REG *)         0x400B0014) // (HDMA) HDMA Request Synchronization Register\r
+#define AT91C_HDMA_VER  (AT91_CAST(AT91_REG *)         0x400B01FC) // (HDMA) HDMA VERSION REGISTER \r
+#define AT91C_HDMA_RSVD0 (AT91_CAST(AT91_REG *)        0x400B0034) // (HDMA) HDMA Reserved\r
+#define AT91C_HDMA_CHSR (AT91_CAST(AT91_REG *)         0x400B0030) // (HDMA) HDMA Channel Handler Status Register\r
+#define AT91C_HDMA_IPNAME2 (AT91_CAST(AT91_REG *)      0x400B01F4) // (HDMA) HDMA IPNAME2 REGISTER \r
+#define AT91C_HDMA_EBCIMR (AT91_CAST(AT91_REG *)       0x400B0020) // (HDMA) HDMA Error, Chained Buffer transfer completed and Buffer transfer completed Mask Register\r
+#define AT91C_HDMA_CHDR (AT91_CAST(AT91_REG *)         0x400B002C) // (HDMA) HDMA Channel Handler Disable Register\r
+#define AT91C_HDMA_EN   (AT91_CAST(AT91_REG *)         0x400B0004) // (HDMA) HDMA Controller Enable Register\r
+#define AT91C_HDMA_GCFG (AT91_CAST(AT91_REG *)         0x400B0000) // (HDMA) HDMA Global Configuration Register\r
+#define AT91C_HDMA_IPNAME1 (AT91_CAST(AT91_REG *)      0x400B01F0) // (HDMA) HDMA IPNAME1 REGISTER \r
+#define AT91C_HDMA_LAST (AT91_CAST(AT91_REG *)         0x400B0010) // (HDMA) HDMA Software Last Transfer Flag Register\r
+#define AT91C_HDMA_FEATURES (AT91_CAST(AT91_REG *)     0x400B01F8) // (HDMA) HDMA FEATURES REGISTER \r
+#define AT91C_HDMA_CREQ (AT91_CAST(AT91_REG *)         0x400B000C) // (HDMA) HDMA Software Chunk Transfer Request Register\r
+#define AT91C_HDMA_EBCIER (AT91_CAST(AT91_REG *)       0x400B0018) // (HDMA) HDMA Error, Chained Buffer transfer completed and Buffer transfer completed Interrupt Enable register\r
+#define AT91C_HDMA_CHER (AT91_CAST(AT91_REG *)         0x400B0028) // (HDMA) HDMA Channel Handler Enable Register\r
+#define AT91C_HDMA_ADDRSIZE (AT91_CAST(AT91_REG *)     0x400B01EC) // (HDMA) HDMA ADDRSIZE REGISTER \r
+#define AT91C_HDMA_EBCISR (AT91_CAST(AT91_REG *)       0x400B0024) // (HDMA) HDMA Error, Chained Buffer transfer completed and Buffer transfer completed Status Register\r
+#define AT91C_HDMA_SREQ (AT91_CAST(AT91_REG *)         0x400B0008) // (HDMA) HDMA Software Single Request Register\r
+#define AT91C_HDMA_EBCIDR (AT91_CAST(AT91_REG *)       0x400B001C) // (HDMA) HDMA Error, Chained Buffer transfer completed and Buffer transfer completed Interrupt Disable register\r
+#define AT91C_HDMA_RSVD1 (AT91_CAST(AT91_REG *)        0x400B0038) // (HDMA) HDMA Reserved\r
+\r
+// *****************************************************************************\r
+//               PIO DEFINITIONS FOR AT91SAM3U4\r
+// *****************************************************************************\r
+#define AT91C_PIO_PA0        (1 <<  0) // Pin Controlled by PA0\r
+#define AT91C_PA0_TIOB0    (AT91C_PIO_PA0) //  \r
+#define AT91C_PA0_SPI0_NPCS1 (AT91C_PIO_PA0) //  \r
+#define AT91C_PIO_PA1        (1 <<  1) // Pin Controlled by PA1\r
+#define AT91C_PA1_TIOA0    (AT91C_PIO_PA1) //  \r
+#define AT91C_PA1_SPI0_NPCS2 (AT91C_PIO_PA1) //  \r
+#define AT91C_PIO_PA10       (1 << 10) // Pin Controlled by PA10\r
+#define AT91C_PA10_TWCK0    (AT91C_PIO_PA10) //  \r
+#define AT91C_PA10_PWML3    (AT91C_PIO_PA10) //  \r
+#define AT91C_PIO_PA11       (1 << 11) // Pin Controlled by PA11\r
+#define AT91C_PA11_DRXD     (AT91C_PIO_PA11) //  \r
+#define AT91C_PIO_PA12       (1 << 12) // Pin Controlled by PA12\r
+#define AT91C_PA12_DTXD     (AT91C_PIO_PA12) //  \r
+#define AT91C_PIO_PA13       (1 << 13) // Pin Controlled by PA13\r
+#define AT91C_PA13_SPI0_MISO (AT91C_PIO_PA13) //  \r
+#define AT91C_PIO_PA14       (1 << 14) // Pin Controlled by PA14\r
+#define AT91C_PA14_SPI0_MOSI (AT91C_PIO_PA14) //  \r
+#define AT91C_PIO_PA15       (1 << 15) // Pin Controlled by PA15\r
+#define AT91C_PA15_SPI0_SPCK (AT91C_PIO_PA15) //  \r
+#define AT91C_PA15_PWMH2    (AT91C_PIO_PA15) //  \r
+#define AT91C_PIO_PA16       (1 << 16) // Pin Controlled by PA16\r
+#define AT91C_PA16_SPI0_NPCS0 (AT91C_PIO_PA16) //  \r
+#define AT91C_PA16_NCS1     (AT91C_PIO_PA16) //  \r
+#define AT91C_PIO_PA17       (1 << 17) // Pin Controlled by PA17\r
+#define AT91C_PA17_SCK0     (AT91C_PIO_PA17) //  \r
+#define AT91C_PA17_ADTRG0   (AT91C_PIO_PA17) //  \r
+#define AT91C_PIO_PA18       (1 << 18) // Pin Controlled by PA18\r
+#define AT91C_PA18_TXD0     (AT91C_PIO_PA18) //  \r
+#define AT91C_PIO_PA19       (1 << 19) // Pin Controlled by PA19\r
+#define AT91C_PA19_RXD0     (AT91C_PIO_PA19) //  \r
+#define AT91C_PA19_SPI0_NPCS3 (AT91C_PIO_PA19) //  \r
+#define AT91C_PIO_PA2        (1 <<  2) // Pin Controlled by PA2\r
+#define AT91C_PA2_TCLK0    (AT91C_PIO_PA2) //  \r
+#define AT91C_PA2_ADTRG1   (AT91C_PIO_PA2) //  \r
+#define AT91C_PIO_PA20       (1 << 20) // Pin Controlled by PA20\r
+#define AT91C_PA20_TXD1     (AT91C_PIO_PA20) //  \r
+#define AT91C_PA20_PWMH3    (AT91C_PIO_PA20) //  \r
+#define AT91C_PIO_PA21       (1 << 21) // Pin Controlled by PA21\r
+#define AT91C_PA21_RXD1     (AT91C_PIO_PA21) //  \r
+#define AT91C_PA21_PCK0     (AT91C_PIO_PA21) //  \r
+#define AT91C_PIO_PA22       (1 << 22) // Pin Controlled by PA22\r
+#define AT91C_PA22_TXD2     (AT91C_PIO_PA22) //  \r
+#define AT91C_PA22_RTS1     (AT91C_PIO_PA22) //  \r
+#define AT91C_PIO_PA23       (1 << 23) // Pin Controlled by PA23\r
+#define AT91C_PA23_RXD2     (AT91C_PIO_PA23) //  \r
+#define AT91C_PA23_CTS1     (AT91C_PIO_PA23) //  \r
+#define AT91C_PIO_PA24       (1 << 24) // Pin Controlled by PA24\r
+#define AT91C_PA24_TWD1     (AT91C_PIO_PA24) //  \r
+#define AT91C_PA24_SCK1     (AT91C_PIO_PA24) //  \r
+#define AT91C_PIO_PA25       (1 << 25) // Pin Controlled by PA25\r
+#define AT91C_PA25_TWCK1    (AT91C_PIO_PA25) //  \r
+#define AT91C_PA25_SCK2     (AT91C_PIO_PA25) //  \r
+#define AT91C_PIO_PA26       (1 << 26) // Pin Controlled by PA26\r
+#define AT91C_PA26_TD0      (AT91C_PIO_PA26) //  \r
+#define AT91C_PA26_TCLK2    (AT91C_PIO_PA26) //  \r
+#define AT91C_PIO_PA27       (1 << 27) // Pin Controlled by PA27\r
+#define AT91C_PA27_RD0      (AT91C_PIO_PA27) //  \r
+#define AT91C_PA27_PCK0     (AT91C_PIO_PA27) //  \r
+#define AT91C_PIO_PA28       (1 << 28) // Pin Controlled by PA28\r
+#define AT91C_PA28_TK0      (AT91C_PIO_PA28) //  \r
+#define AT91C_PA28_PWMH0    (AT91C_PIO_PA28) //  \r
+#define AT91C_PIO_PA29       (1 << 29) // Pin Controlled by PA29\r
+#define AT91C_PA29_RK0      (AT91C_PIO_PA29) //  \r
+#define AT91C_PA29_PWMH1    (AT91C_PIO_PA29) //  \r
+#define AT91C_PIO_PA3        (1 <<  3) // Pin Controlled by PA3\r
+#define AT91C_PA3_MCI0_CK  (AT91C_PIO_PA3) //  \r
+#define AT91C_PA3_PCK1     (AT91C_PIO_PA3) //  \r
+#define AT91C_PIO_PA30       (1 << 30) // Pin Controlled by PA30\r
+#define AT91C_PA30_TF0      (AT91C_PIO_PA30) //  \r
+#define AT91C_PA30_TIOA2    (AT91C_PIO_PA30) //  \r
+#define AT91C_PIO_PA31       (1 << 31) // Pin Controlled by PA31\r
+#define AT91C_PA31_RF0      (AT91C_PIO_PA31) //  \r
+#define AT91C_PA31_TIOB2    (AT91C_PIO_PA31) //  \r
+#define AT91C_PIO_PA4        (1 <<  4) // Pin Controlled by PA4\r
+#define AT91C_PA4_MCI0_CDA (AT91C_PIO_PA4) //  \r
+#define AT91C_PA4_PWMH0    (AT91C_PIO_PA4) //  \r
+#define AT91C_PIO_PA5        (1 <<  5) // Pin Controlled by PA5\r
+#define AT91C_PA5_MCI0_DA0 (AT91C_PIO_PA5) //  \r
+#define AT91C_PA5_PWMH1    (AT91C_PIO_PA5) //  \r
+#define AT91C_PIO_PA6        (1 <<  6) // Pin Controlled by PA6\r
+#define AT91C_PA6_MCI0_DA1 (AT91C_PIO_PA6) //  \r
+#define AT91C_PA6_PWMH2    (AT91C_PIO_PA6) //  \r
+#define AT91C_PIO_PA7        (1 <<  7) // Pin Controlled by PA7\r
+#define AT91C_PA7_MCI0_DA2 (AT91C_PIO_PA7) //  \r
+#define AT91C_PA7_PWML0    (AT91C_PIO_PA7) //  \r
+#define AT91C_PIO_PA8        (1 <<  8) // Pin Controlled by PA8\r
+#define AT91C_PA8_MCI0_DA3 (AT91C_PIO_PA8) //  \r
+#define AT91C_PA8_PWML1    (AT91C_PIO_PA8) //  \r
+#define AT91C_PIO_PA9        (1 <<  9) // Pin Controlled by PA9\r
+#define AT91C_PA9_TWD0     (AT91C_PIO_PA9) //  \r
+#define AT91C_PA9_PWML2    (AT91C_PIO_PA9) //  \r
+#define AT91C_PIO_PB0        (1 <<  0) // Pin Controlled by PB0\r
+#define AT91C_PB0_PWMH0    (AT91C_PIO_PB0) //  \r
+#define AT91C_PB0_A2       (AT91C_PIO_PB0) //  \r
+#define AT91C_PIO_PB1        (1 <<  1) // Pin Controlled by PB1\r
+#define AT91C_PB1_PWMH1    (AT91C_PIO_PB1) //  \r
+#define AT91C_PB1_A3       (AT91C_PIO_PB1) //  \r
+#define AT91C_PIO_PB10       (1 << 10) // Pin Controlled by PB10\r
+#define AT91C_PB10_D1       (AT91C_PIO_PB10) //  \r
+#define AT91C_PB10_DSR0     (AT91C_PIO_PB10) //  \r
+#define AT91C_PIO_PB11       (1 << 11) // Pin Controlled by PB11\r
+#define AT91C_PB11_D2       (AT91C_PIO_PB11) //  \r
+#define AT91C_PB11_DCD0     (AT91C_PIO_PB11) //  \r
+#define AT91C_PIO_PB12       (1 << 12) // Pin Controlled by PB12\r
+#define AT91C_PB12_D3       (AT91C_PIO_PB12) //  \r
+#define AT91C_PB12_RI0      (AT91C_PIO_PB12) //  \r
+#define AT91C_PIO_PB13       (1 << 13) // Pin Controlled by PB13\r
+#define AT91C_PB13_D4       (AT91C_PIO_PB13) //  \r
+#define AT91C_PB13_PWMH0    (AT91C_PIO_PB13) //  \r
+#define AT91C_PIO_PB14       (1 << 14) // Pin Controlled by PB14\r
+#define AT91C_PB14_D5       (AT91C_PIO_PB14) //  \r
+#define AT91C_PB14_PWMH1    (AT91C_PIO_PB14) //  \r
+#define AT91C_PIO_PB15       (1 << 15) // Pin Controlled by PB15\r
+#define AT91C_PB15_D6       (AT91C_PIO_PB15) //  \r
+#define AT91C_PB15_PWMH2    (AT91C_PIO_PB15) //  \r
+#define AT91C_PIO_PB16       (1 << 16) // Pin Controlled by PB16\r
+#define AT91C_PB16_D7       (AT91C_PIO_PB16) //  \r
+#define AT91C_PB16_PWMH3    (AT91C_PIO_PB16) //  \r
+#define AT91C_PIO_PB17       (1 << 17) // Pin Controlled by PB17\r
+#define AT91C_PB17_NANDOE   (AT91C_PIO_PB17) //  \r
+#define AT91C_PB17_PWML0    (AT91C_PIO_PB17) //  \r
+#define AT91C_PIO_PB18       (1 << 18) // Pin Controlled by PB18\r
+#define AT91C_PB18_NANDWE   (AT91C_PIO_PB18) //  \r
+#define AT91C_PB18_PWML1    (AT91C_PIO_PB18) //  \r
+#define AT91C_PIO_PB19       (1 << 19) // Pin Controlled by PB19\r
+#define AT91C_PB19_NRD      (AT91C_PIO_PB19) //  \r
+#define AT91C_PB19_PWML2    (AT91C_PIO_PB19) //  \r
+#define AT91C_PIO_PB2        (1 <<  2) // Pin Controlled by PB2\r
+#define AT91C_PB2_PWMH2    (AT91C_PIO_PB2) //  \r
+#define AT91C_PB2_A4       (AT91C_PIO_PB2) //  \r
+#define AT91C_PIO_PB20       (1 << 20) // Pin Controlled by PB20\r
+#define AT91C_PB20_NCS0     (AT91C_PIO_PB20) //  \r
+#define AT91C_PB20_PWML3    (AT91C_PIO_PB20) //  \r
+#define AT91C_PIO_PB21       (1 << 21) // Pin Controlled by PB21\r
+#define AT91C_PB21_A21_NANDALE (AT91C_PIO_PB21) //  \r
+#define AT91C_PB21_RTS2     (AT91C_PIO_PB21) //  \r
+#define AT91C_PIO_PB22       (1 << 22) // Pin Controlled by PB22\r
+#define AT91C_PB22_A22_NANDCLE (AT91C_PIO_PB22) //  \r
+#define AT91C_PB22_CTS2     (AT91C_PIO_PB22) //  \r
+#define AT91C_PIO_PB23       (1 << 23) // Pin Controlled by PB23\r
+#define AT91C_PB23_NWR0_NWE (AT91C_PIO_PB23) //  \r
+#define AT91C_PB23_PCK2     (AT91C_PIO_PB23) //  \r
+#define AT91C_PIO_PB24       (1 << 24) // Pin Controlled by PB24\r
+#define AT91C_PB24_NANDRDY  (AT91C_PIO_PB24) //  \r
+#define AT91C_PB24_PCK1     (AT91C_PIO_PB24) //  \r
+#define AT91C_PIO_PB25       (1 << 25) // Pin Controlled by PB25\r
+#define AT91C_PB25_D8       (AT91C_PIO_PB25) //  \r
+#define AT91C_PB25_PWML0    (AT91C_PIO_PB25) //  \r
+#define AT91C_PIO_PB26       (1 << 26) // Pin Controlled by PB26\r
+#define AT91C_PB26_D9       (AT91C_PIO_PB26) //  \r
+#define AT91C_PB26_PWML1    (AT91C_PIO_PB26) //  \r
+#define AT91C_PIO_PB27       (1 << 27) // Pin Controlled by PB27\r
+#define AT91C_PB27_D10      (AT91C_PIO_PB27) //  \r
+#define AT91C_PB27_PWML2    (AT91C_PIO_PB27) //  \r
+#define AT91C_PIO_PB28       (1 << 28) // Pin Controlled by PB28\r
+#define AT91C_PB28_D11      (AT91C_PIO_PB28) //  \r
+#define AT91C_PB28_PWML3    (AT91C_PIO_PB28) //  \r
+#define AT91C_PIO_PB29       (1 << 29) // Pin Controlled by PB29\r
+#define AT91C_PB29_D12      (AT91C_PIO_PB29) //  \r
+#define AT91C_PIO_PB3        (1 <<  3) // Pin Controlled by PB3\r
+#define AT91C_PB3_PWMH3    (AT91C_PIO_PB3) //  \r
+#define AT91C_PB3_A5       (AT91C_PIO_PB3) //  \r
+#define AT91C_PIO_PB30       (1 << 30) // Pin Controlled by PB30\r
+#define AT91C_PB30_D13      (AT91C_PIO_PB30) //  \r
+#define AT91C_PIO_PB31       (1 << 31) // Pin Controlled by PB31\r
+#define AT91C_PB31_D14      (AT91C_PIO_PB31) //  \r
+#define AT91C_PIO_PB4        (1 <<  4) // Pin Controlled by PB4\r
+#define AT91C_PB4_TCLK1    (AT91C_PIO_PB4) //  \r
+#define AT91C_PB4_A6       (AT91C_PIO_PB4) //  \r
+#define AT91C_PIO_PB5        (1 <<  5) // Pin Controlled by PB5\r
+#define AT91C_PB5_TIOA1    (AT91C_PIO_PB5) //  \r
+#define AT91C_PB5_A7       (AT91C_PIO_PB5) //  \r
+#define AT91C_PIO_PB6        (1 <<  6) // Pin Controlled by PB6\r
+#define AT91C_PB6_TIOB1    (AT91C_PIO_PB6) //  \r
+#define AT91C_PB6_D15      (AT91C_PIO_PB6) //  \r
+#define AT91C_PIO_PB7        (1 <<  7) // Pin Controlled by PB7\r
+#define AT91C_PB7_RTS0     (AT91C_PIO_PB7) //  \r
+#define AT91C_PB7_A0_NBS0  (AT91C_PIO_PB7) //  \r
+#define AT91C_PIO_PB8        (1 <<  8) // Pin Controlled by PB8\r
+#define AT91C_PB8_CTS0     (AT91C_PIO_PB8) //  \r
+#define AT91C_PB8_A1       (AT91C_PIO_PB8) //  \r
+#define AT91C_PIO_PB9        (1 <<  9) // Pin Controlled by PB9\r
+#define AT91C_PB9_D0       (AT91C_PIO_PB9) //  \r
+#define AT91C_PB9_DTR0     (AT91C_PIO_PB9) //  \r
+#define AT91C_PIO_PC0        (1 <<  0) // Pin Controlled by PC0\r
+#define AT91C_PC0_A2       (AT91C_PIO_PC0) //  \r
+#define AT91C_PIO_PC1        (1 <<  1) // Pin Controlled by PC1\r
+#define AT91C_PC1_A3       (AT91C_PIO_PC1) //  \r
+#define AT91C_PIO_PC10       (1 << 10) // Pin Controlled by PC10\r
+#define AT91C_PC10_A12      (AT91C_PIO_PC10) //  \r
+#define AT91C_PC10_CTS3     (AT91C_PIO_PC10) //  \r
+#define AT91C_PIO_PC11       (1 << 11) // Pin Controlled by PC11\r
+#define AT91C_PC11_A13      (AT91C_PIO_PC11) //  \r
+#define AT91C_PC11_RTS3     (AT91C_PIO_PC11) //  \r
+#define AT91C_PIO_PC12       (1 << 12) // Pin Controlled by PC12\r
+#define AT91C_PC12_NCS1     (AT91C_PIO_PC12) //  \r
+#define AT91C_PC12_TXD3     (AT91C_PIO_PC12) //  \r
+#define AT91C_PIO_PC13       (1 << 13) // Pin Controlled by PC13\r
+#define AT91C_PC13_A2       (AT91C_PIO_PC13) //  \r
+#define AT91C_PC13_RXD3     (AT91C_PIO_PC13) //  \r
+#define AT91C_PIO_PC14       (1 << 14) // Pin Controlled by PC14\r
+#define AT91C_PC14_A3       (AT91C_PIO_PC14) //  \r
+#define AT91C_PC14_SPI0_NPCS2 (AT91C_PIO_PC14) //  \r
+#define AT91C_PIO_PC15       (1 << 15) // Pin Controlled by PC15\r
+#define AT91C_PC15_NWR1_NBS1 (AT91C_PIO_PC15) //  \r
+#define AT91C_PIO_PC16       (1 << 16) // Pin Controlled by PC16\r
+#define AT91C_PC16_NCS2     (AT91C_PIO_PC16) //  \r
+#define AT91C_PC16_PWML3    (AT91C_PIO_PC16) //  \r
+#define AT91C_PIO_PC17       (1 << 17) // Pin Controlled by PC17\r
+#define AT91C_PC17_NCS3     (AT91C_PIO_PC17) //  \r
+#define AT91C_PC17_A24      (AT91C_PIO_PC17) //  \r
+#define AT91C_PIO_PC18       (1 << 18) // Pin Controlled by PC18\r
+#define AT91C_PC18_NWAIT    (AT91C_PIO_PC18) //  \r
+#define AT91C_PIO_PC19       (1 << 19) // Pin Controlled by PC19\r
+#define AT91C_PC19_SCK3     (AT91C_PIO_PC19) //  \r
+#define AT91C_PC19_NPCS1    (AT91C_PIO_PC19) //  \r
+#define AT91C_PIO_PC2        (1 <<  2) // Pin Controlled by PC2\r
+#define AT91C_PC2_A4       (AT91C_PIO_PC2) //  \r
+#define AT91C_PIO_PC20       (1 << 20) // Pin Controlled by PC20\r
+#define AT91C_PC20_A14      (AT91C_PIO_PC20) //  \r
+#define AT91C_PIO_PC21       (1 << 21) // Pin Controlled by PC21\r
+#define AT91C_PC21_A15      (AT91C_PIO_PC21) //  \r
+#define AT91C_PIO_PC22       (1 << 22) // Pin Controlled by PC22\r
+#define AT91C_PC22_A16      (AT91C_PIO_PC22) //  \r
+#define AT91C_PIO_PC23       (1 << 23) // Pin Controlled by PC23\r
+#define AT91C_PC23_A17      (AT91C_PIO_PC23) //  \r
+#define AT91C_PIO_PC24       (1 << 24) // Pin Controlled by PC24\r
+#define AT91C_PC24_A18      (AT91C_PIO_PC24) //  \r
+#define AT91C_PC24_PWMH0    (AT91C_PIO_PC24) //  \r
+#define AT91C_PIO_PC25       (1 << 25) // Pin Controlled by PC25\r
+#define AT91C_PC25_A19      (AT91C_PIO_PC25) //  \r
+#define AT91C_PC25_PWMH1    (AT91C_PIO_PC25) //  \r
+#define AT91C_PIO_PC26       (1 << 26) // Pin Controlled by PC26\r
+#define AT91C_PC26_A20      (AT91C_PIO_PC26) //  \r
+#define AT91C_PC26_PWMH2    (AT91C_PIO_PC26) //  \r
+#define AT91C_PIO_PC27       (1 << 27) // Pin Controlled by PC27\r
+#define AT91C_PC27_A23      (AT91C_PIO_PC27) //  \r
+#define AT91C_PC27_PWMH3    (AT91C_PIO_PC27) //  \r
+#define AT91C_PIO_PC28       (1 << 28) // Pin Controlled by PC28\r
+#define AT91C_PC28_A24      (AT91C_PIO_PC28) //  \r
+#define AT91C_PC28_MCI0_DA4 (AT91C_PIO_PC28) //  \r
+#define AT91C_PIO_PC29       (1 << 29) // Pin Controlled by PC29\r
+#define AT91C_PC29_PWML0    (AT91C_PIO_PC29) //  \r
+#define AT91C_PC29_MCI0_DA5 (AT91C_PIO_PC29) //  \r
+#define AT91C_PIO_PC3        (1 <<  3) // Pin Controlled by PC3\r
+#define AT91C_PC3_A5       (AT91C_PIO_PC3) //  \r
+#define AT91C_PC3_SPI0_NPCS1 (AT91C_PIO_PC3) //  \r
+#define AT91C_PIO_PC30       (1 << 30) // Pin Controlled by PC30\r
+#define AT91C_PC30_PWML1    (AT91C_PIO_PC30) //  \r
+#define AT91C_PC30_MCI0_DA6 (AT91C_PIO_PC30) //  \r
+#define AT91C_PIO_PC31       (1 << 31) // Pin Controlled by PC31\r
+#define AT91C_PC31_PWML2    (AT91C_PIO_PC31) //  \r
+#define AT91C_PC31_MCI0_DA7 (AT91C_PIO_PC31) //  \r
+#define AT91C_PIO_PC4        (1 <<  4) // Pin Controlled by PC4\r
+#define AT91C_PC4_A6       (AT91C_PIO_PC4) //  \r
+#define AT91C_PC4_SPI0_NPCS2 (AT91C_PIO_PC4) //  \r
+#define AT91C_PIO_PC5        (1 <<  5) // Pin Controlled by PC5\r
+#define AT91C_PC5_A7       (AT91C_PIO_PC5) //  \r
+#define AT91C_PC5_SPI0_NPCS3 (AT91C_PIO_PC5) //  \r
+#define AT91C_PIO_PC6        (1 <<  6) // Pin Controlled by PC6\r
+#define AT91C_PC6_A8       (AT91C_PIO_PC6) //  \r
+#define AT91C_PC6_PWML0    (AT91C_PIO_PC6) //  \r
+#define AT91C_PIO_PC7        (1 <<  7) // Pin Controlled by PC7\r
+#define AT91C_PC7_A9       (AT91C_PIO_PC7) //  \r
+#define AT91C_PC7_PWML1    (AT91C_PIO_PC7) //  \r
+#define AT91C_PIO_PC8        (1 <<  8) // Pin Controlled by PC8\r
+#define AT91C_PC8_A10      (AT91C_PIO_PC8) //  \r
+#define AT91C_PC8_PWML2    (AT91C_PIO_PC8) //  \r
+#define AT91C_PIO_PC9        (1 <<  9) // Pin Controlled by PC9\r
+#define AT91C_PC9_A11      (AT91C_PIO_PC9) //  \r
+#define AT91C_PC9_PWML3    (AT91C_PIO_PC9) //  \r
+\r
+// *****************************************************************************\r
+//               PERIPHERAL ID DEFINITIONS FOR AT91SAM3U4\r
+// *****************************************************************************\r
+#define AT91C_ID_SUPC   ( 0) // SUPPLY CONTROLLER\r
+#define AT91C_ID_RSTC   ( 1) // RESET CONTROLLER\r
+#define AT91C_ID_RTC    ( 2) // REAL TIME CLOCK\r
+#define AT91C_ID_RTT    ( 3) // REAL TIME TIMER\r
+#define AT91C_ID_WDG    ( 4) // WATCHDOG TIMER\r
+#define AT91C_ID_PMC    ( 5) // PMC\r
+#define AT91C_ID_EFC0   ( 6) // EFC0\r
+#define AT91C_ID_EFC1   ( 7) // EFC1\r
+#define AT91C_ID_DBGU   ( 8) // DBGU\r
+#define AT91C_ID_HSMC4  ( 9) // HSMC4\r
+#define AT91C_ID_PIOA   (10) // Parallel IO Controller A\r
+#define AT91C_ID_PIOB   (11) // Parallel IO Controller B\r
+#define AT91C_ID_PIOC   (12) // Parallel IO Controller C\r
+#define AT91C_ID_US0    (13) // USART 0\r
+#define AT91C_ID_US1    (14) // USART 1\r
+#define AT91C_ID_US2    (15) // USART 2\r
+#define AT91C_ID_US3    (16) // USART 3\r
+#define AT91C_ID_MCI0   (17) // Multimedia Card Interface\r
+#define AT91C_ID_TWI0   (18) // TWI 0\r
+#define AT91C_ID_TWI1   (19) // TWI 1\r
+#define AT91C_ID_SPI0   (20) // Serial Peripheral Interface\r
+#define AT91C_ID_SSC0   (21) // Serial Synchronous Controller 0\r
+#define AT91C_ID_TC0    (22) // Timer Counter 0\r
+#define AT91C_ID_TC1    (23) // Timer Counter 1\r
+#define AT91C_ID_TC2    (24) // Timer Counter 2\r
+#define AT91C_ID_PWMC   (25) // Pulse Width Modulation Controller\r
+#define AT91C_ID_ADCC0  (26) // ADC controller0\r
+#define AT91C_ID_ADCC1  (27) // ADC controller1\r
+#define AT91C_ID_HDMA   (28) // HDMA\r
+#define AT91C_ID_UDPHS  (29) // USB Device High Speed\r
+#define AT91C_ALL_INT   (0x3FFFFFFF) // ALL VALID INTERRUPTS\r
+\r
+// *****************************************************************************\r
+//               BASE ADDRESS DEFINITIONS FOR AT91SAM3U4\r
+// *****************************************************************************\r
+#define AT91C_BASE_SYS       (AT91_CAST(AT91PS_SYS)    0x400E0000) // (SYS) Base Address\r
+#define AT91C_BASE_HSMC4_CS0 (AT91_CAST(AT91PS_HSMC4_CS)       0x400E0070) // (HSMC4_CS0) Base Address\r
+#define AT91C_BASE_HSMC4_CS1 (AT91_CAST(AT91PS_HSMC4_CS)       0x400E0084) // (HSMC4_CS1) Base Address\r
+#define AT91C_BASE_HSMC4_CS2 (AT91_CAST(AT91PS_HSMC4_CS)       0x400E0098) // (HSMC4_CS2) Base Address\r
+#define AT91C_BASE_HSMC4_CS3 (AT91_CAST(AT91PS_HSMC4_CS)       0x400E00AC) // (HSMC4_CS3) Base Address\r
+#define AT91C_BASE_HSMC4_NFC (AT91_CAST(AT91PS_HSMC4_CS)       0x400E00FC) // (HSMC4_NFC) Base Address\r
+#define AT91C_BASE_HSMC4     (AT91_CAST(AT91PS_HSMC4)  0x400E0000) // (HSMC4) Base Address\r
+#define AT91C_BASE_MATRIX    (AT91_CAST(AT91PS_HMATRIX2)       0x400E0200) // (MATRIX) Base Address\r
+#define AT91C_BASE_NVIC      (AT91_CAST(AT91PS_NVIC)   0xE000E000) // (NVIC) Base Address\r
+#define AT91C_BASE_MPU       (AT91_CAST(AT91PS_MPU)    0xE000ED90) // (MPU) Base Address\r
+#define AT91C_BASE_CM3       (AT91_CAST(AT91PS_CM3)    0xE000ED00) // (CM3) Base Address\r
+#define AT91C_BASE_PDC_DBGU  (AT91_CAST(AT91PS_PDC)    0x400E0700) // (PDC_DBGU) Base Address\r
+#define AT91C_BASE_DBGU      (AT91_CAST(AT91PS_DBGU)   0x400E0600) // (DBGU) Base Address\r
+#define AT91C_BASE_PIOA      (AT91_CAST(AT91PS_PIO)    0x400E0C00) // (PIOA) Base Address\r
+#define AT91C_BASE_PIOB      (AT91_CAST(AT91PS_PIO)    0x400E0E00) // (PIOB) Base Address\r
+#define AT91C_BASE_PIOC      (AT91_CAST(AT91PS_PIO)    0x400E1000) // (PIOC) Base Address\r
+#define AT91C_BASE_PMC       (AT91_CAST(AT91PS_PMC)    0x400E0400) // (PMC) Base Address\r
+#define AT91C_BASE_CKGR      (AT91_CAST(AT91PS_CKGR)   0x400E041C) // (CKGR) Base Address\r
+#define AT91C_BASE_RSTC      (AT91_CAST(AT91PS_RSTC)   0x400E1200) // (RSTC) Base Address\r
+#define AT91C_BASE_SUPC      (AT91_CAST(AT91PS_SUPC)   0x400E1210) // (SUPC) Base Address\r
+#define AT91C_BASE_RTTC      (AT91_CAST(AT91PS_RTTC)   0x400E1230) // (RTTC) Base Address\r
+#define AT91C_BASE_WDTC      (AT91_CAST(AT91PS_WDTC)   0x400E1250) // (WDTC) Base Address\r
+#define AT91C_BASE_RTC       (AT91_CAST(AT91PS_RTC)    0x400E1260) // (RTC) Base Address\r
+#define AT91C_BASE_ADC0      (AT91_CAST(AT91PS_ADC)    0x400A8000) // (ADC0) Base Address\r
+#define AT91C_BASE_ADC1      (AT91_CAST(AT91PS_ADC)    0x400AC000) // (ADC1) Base Address\r
+#define AT91C_BASE_TC0       (AT91_CAST(AT91PS_TC)     0x40080000) // (TC0) Base Address\r
+#define AT91C_BASE_TC1       (AT91_CAST(AT91PS_TC)     0x40080040) // (TC1) Base Address\r
+#define AT91C_BASE_TC2       (AT91_CAST(AT91PS_TC)     0x40080080) // (TC2) Base Address\r
+#define AT91C_BASE_TCB0      (AT91_CAST(AT91PS_TCB)    0x40080000) // (TCB0) Base Address\r
+#define AT91C_BASE_TCB1      (AT91_CAST(AT91PS_TCB)    0x40080040) // (TCB1) Base Address\r
+#define AT91C_BASE_TCB2      (AT91_CAST(AT91PS_TCB)    0x40080080) // (TCB2) Base Address\r
+#define AT91C_BASE_EFC0      (AT91_CAST(AT91PS_EFC)    0x400E0800) // (EFC0) Base Address\r
+#define AT91C_BASE_EFC1      (AT91_CAST(AT91PS_EFC)    0x400E0A00) // (EFC1) Base Address\r
+#define AT91C_BASE_MCI0      (AT91_CAST(AT91PS_MCI)    0x40000000) // (MCI0) Base Address\r
+#define AT91C_BASE_PDC_TWI0  (AT91_CAST(AT91PS_PDC)    0x40084100) // (PDC_TWI0) Base Address\r
+#define AT91C_BASE_PDC_TWI1  (AT91_CAST(AT91PS_PDC)    0x40088100) // (PDC_TWI1) Base Address\r
+#define AT91C_BASE_TWI0      (AT91_CAST(AT91PS_TWI)    0x40084000) // (TWI0) Base Address\r
+#define AT91C_BASE_TWI1      (AT91_CAST(AT91PS_TWI)    0x40088000) // (TWI1) Base Address\r
+#define AT91C_BASE_PDC_US0   (AT91_CAST(AT91PS_PDC)    0x40090100) // (PDC_US0) Base Address\r
+#define AT91C_BASE_US0       (AT91_CAST(AT91PS_USART)  0x40090000) // (US0) Base Address\r
+#define AT91C_BASE_PDC_US1   (AT91_CAST(AT91PS_PDC)    0x40094100) // (PDC_US1) Base Address\r
+#define AT91C_BASE_US1       (AT91_CAST(AT91PS_USART)  0x40094000) // (US1) Base Address\r
+#define AT91C_BASE_PDC_US2   (AT91_CAST(AT91PS_PDC)    0x40098100) // (PDC_US2) Base Address\r
+#define AT91C_BASE_US2       (AT91_CAST(AT91PS_USART)  0x40098000) // (US2) Base Address\r
+#define AT91C_BASE_PDC_US3   (AT91_CAST(AT91PS_PDC)    0x4009C100) // (PDC_US3) Base Address\r
+#define AT91C_BASE_US3       (AT91_CAST(AT91PS_USART)  0x4009C000) // (US3) Base Address\r
+#define AT91C_BASE_PDC_SSC0  (AT91_CAST(AT91PS_PDC)    0x40004100) // (PDC_SSC0) Base Address\r
+#define AT91C_BASE_SSC0      (AT91_CAST(AT91PS_SSC)    0x40004000) // (SSC0) Base Address\r
+#define AT91C_BASE_PDC_PWMC  (AT91_CAST(AT91PS_PDC)    0x4008C100) // (PDC_PWMC) Base Address\r
+#define AT91C_BASE_PWMC_CH0  (AT91_CAST(AT91PS_PWMC_CH)        0x4008C200) // (PWMC_CH0) Base Address\r
+#define AT91C_BASE_PWMC_CH1  (AT91_CAST(AT91PS_PWMC_CH)        0x4008C220) // (PWMC_CH1) Base Address\r
+#define AT91C_BASE_PWMC_CH2  (AT91_CAST(AT91PS_PWMC_CH)        0x4008C240) // (PWMC_CH2) Base Address\r
+#define AT91C_BASE_PWMC_CH3  (AT91_CAST(AT91PS_PWMC_CH)        0x4008C260) // (PWMC_CH3) Base Address\r
+#define AT91C_BASE_PWMC      (AT91_CAST(AT91PS_PWMC)   0x4008C000) // (PWMC) Base Address\r
+#define AT91C_BASE_SPI0      (AT91_CAST(AT91PS_SPI)    0x40008000) // (SPI0) Base Address\r
+#define AT91C_BASE_UDPHS_EPTFIFO (AT91_CAST(AT91PS_UDPHS_EPTFIFO)      0x20180000) // (UDPHS_EPTFIFO) Base Address\r
+#define AT91C_BASE_UDPHS_EPT_0 (AT91_CAST(AT91PS_UDPHS_EPT)    0x400A4100) // (UDPHS_EPT_0) Base Address\r
+#define AT91C_BASE_UDPHS_EPT_1 (AT91_CAST(AT91PS_UDPHS_EPT)    0x400A4120) // (UDPHS_EPT_1) Base Address\r
+#define AT91C_BASE_UDPHS_EPT_2 (AT91_CAST(AT91PS_UDPHS_EPT)    0x400A4140) // (UDPHS_EPT_2) Base Address\r
+#define AT91C_BASE_UDPHS_EPT_3 (AT91_CAST(AT91PS_UDPHS_EPT)    0x400A4160) // (UDPHS_EPT_3) Base Address\r
+#define AT91C_BASE_UDPHS_EPT_4 (AT91_CAST(AT91PS_UDPHS_EPT)    0x400A4180) // (UDPHS_EPT_4) Base Address\r
+#define AT91C_BASE_UDPHS_EPT_5 (AT91_CAST(AT91PS_UDPHS_EPT)    0x400A41A0) // (UDPHS_EPT_5) Base Address\r
+#define AT91C_BASE_UDPHS_EPT_6 (AT91_CAST(AT91PS_UDPHS_EPT)    0x400A41C0) // (UDPHS_EPT_6) Base Address\r
+#define AT91C_BASE_UDPHS_DMA_1 (AT91_CAST(AT91PS_UDPHS_DMA)    0x400A4310) // (UDPHS_DMA_1) Base Address\r
+#define AT91C_BASE_UDPHS_DMA_2 (AT91_CAST(AT91PS_UDPHS_DMA)    0x400A4320) // (UDPHS_DMA_2) Base Address\r
+#define AT91C_BASE_UDPHS_DMA_3 (AT91_CAST(AT91PS_UDPHS_DMA)    0x400A4330) // (UDPHS_DMA_3) Base Address\r
+#define AT91C_BASE_UDPHS_DMA_4 (AT91_CAST(AT91PS_UDPHS_DMA)    0x400A4340) // (UDPHS_DMA_4) Base Address\r
+#define AT91C_BASE_UDPHS_DMA_5 (AT91_CAST(AT91PS_UDPHS_DMA)    0x400A4350) // (UDPHS_DMA_5) Base Address\r
+#define AT91C_BASE_UDPHS_DMA_6 (AT91_CAST(AT91PS_UDPHS_DMA)    0x400A4360) // (UDPHS_DMA_6) Base Address\r
+#define AT91C_BASE_UDPHS     (AT91_CAST(AT91PS_UDPHS)  0x400A4000) // (UDPHS) Base Address\r
+#define AT91C_BASE_HDMA_CH_0 (AT91_CAST(AT91PS_HDMA_CH)        0x400B003C) // (HDMA_CH_0) Base Address\r
+#define AT91C_BASE_HDMA_CH_1 (AT91_CAST(AT91PS_HDMA_CH)        0x400B0064) // (HDMA_CH_1) Base Address\r
+#define AT91C_BASE_HDMA_CH_2 (AT91_CAST(AT91PS_HDMA_CH)        0x400B008C) // (HDMA_CH_2) Base Address\r
+#define AT91C_BASE_HDMA_CH_3 (AT91_CAST(AT91PS_HDMA_CH)        0x400B00B4) // (HDMA_CH_3) Base Address\r
+#define AT91C_BASE_HDMA      (AT91_CAST(AT91PS_HDMA)   0x400B0000) // (HDMA) Base Address\r
+\r
+// *****************************************************************************\r
+//               MEMORY MAPPING DEFINITIONS FOR AT91SAM3U4\r
+// *****************************************************************************\r
+// ITCM\r
+#define AT91C_ITCM      (0x00100000) // Maximum ITCM Area base address\r
+#define AT91C_ITCM_SIZE         (0x00010000) // Maximum ITCM Area size in byte (64 Kbytes)\r
+// DTCM\r
+#define AT91C_DTCM      (0x00200000) // Maximum DTCM Area base address\r
+#define AT91C_DTCM_SIZE         (0x00010000) // Maximum DTCM Area size in byte (64 Kbytes)\r
+// IRAM\r
+#define AT91C_IRAM      (0x20000000) // Maximum Internal SRAM base address\r
+#define AT91C_IRAM_SIZE         (0x00010000) // Maximum Internal SRAM size in byte (64 Kbytes)\r
+// IRAM_MIN\r
+#define AT91C_IRAM_MIN  (0x00300000) // Minimum Internal RAM base address\r
+#define AT91C_IRAM_MIN_SIZE     (0x00004000) // Minimum Internal RAM size in byte (16 Kbytes)\r
+// IROM\r
+#define AT91C_IROM      (0x00180000) // Internal ROM base address\r
+#define AT91C_IROM_SIZE         (0x00008000) // Internal ROM size in byte (32 Kbytes)\r
+// IFLASH0\r
+#define AT91C_IFLASH0   (0x00080000) // Maximum IFLASH Area : 128Kbyte base address\r
+#define AT91C_IFLASH0_SIZE      (0x00020000) // Maximum IFLASH Area : 128Kbyte size in byte (128 Kbytes)\r
+#define AT91C_IFLASH0_PAGE_SIZE         (256) // Maximum IFLASH Area : 128Kbyte Page Size: 256 bytes\r
+#define AT91C_IFLASH0_LOCK_REGION_SIZE  (8192) // Maximum IFLASH Area : 128Kbyte Lock Region Size: 8 Kbytes\r
+#define AT91C_IFLASH0_NB_OF_PAGES       (512) // Maximum IFLASH Area : 128Kbyte Number of Pages: 512 bytes\r
+#define AT91C_IFLASH0_NB_OF_LOCK_BITS   (16) // Maximum IFLASH Area : 128Kbyte Number of Lock Bits: 32 bytes\r
+// IFLASH1\r
+#define AT91C_IFLASH1   (0x0100000) // Maximum IFLASH Area : 128Kbyte base address\r
+#define AT91C_IFLASH1_SIZE      (0x00020000) // Maximum IFLASH Area : 128Kbyte size in byte (128 Kbytes)\r
+#define AT91C_IFLASH1_PAGE_SIZE         (256) // Maximum IFLASH Area : 128Kbyte Page Size: 256 bytes\r
+#define AT91C_IFLASH1_LOCK_REGION_SIZE  (8192) // Maximum IFLASH Area : 128Kbyte Lock Region Size: 8 Kbytes\r
+#define AT91C_IFLASH1_NB_OF_PAGES       (512) // Maximum IFLASH Area : 128Kbyte Number of Pages: 512 bytes\r
+#define AT91C_IFLASH1_NB_OF_LOCK_BITS   (16) // Maximum IFLASH Area : 128Kbyte Number of Lock Bits: 32 bytes\r
+// EBI_CS0\r
+#define AT91C_EBI_CS0   (0x10000000) // EBI Chip Select 0 base address\r
+#define AT91C_EBI_CS0_SIZE      (0x10000000) // EBI Chip Select 0 size in byte (262144 Kbytes)\r
+// EBI_CS1\r
+#define AT91C_EBI_CS1   (0x20000000) // EBI Chip Select 1 base address\r
+#define AT91C_EBI_CS1_SIZE      (0x10000000) // EBI Chip Select 1 size in byte (262144 Kbytes)\r
+// EBI_SDRAM\r
+#define AT91C_EBI_SDRAM         (0x20000000) // SDRAM on EBI Chip Select 1 base address\r
+#define AT91C_EBI_SDRAM_SIZE    (0x10000000) // SDRAM on EBI Chip Select 1 size in byte (262144 Kbytes)\r
+// EBI_SDRAM_16BIT\r
+#define AT91C_EBI_SDRAM_16BIT   (0x20000000) // SDRAM on EBI Chip Select 1 base address\r
+#define AT91C_EBI_SDRAM_16BIT_SIZE      (0x02000000) // SDRAM on EBI Chip Select 1 size in byte (32768 Kbytes)\r
+// EBI_SDRAM_32BIT\r
+#define AT91C_EBI_SDRAM_32BIT   (0x20000000) // SDRAM on EBI Chip Select 1 base address\r
+#define AT91C_EBI_SDRAM_32BIT_SIZE      (0x04000000) // SDRAM on EBI Chip Select 1 size in byte (65536 Kbytes)\r
+// EBI_CS2\r
+#define AT91C_EBI_CS2   (0x30000000) // EBI Chip Select 2 base address\r
+#define AT91C_EBI_CS2_SIZE      (0x10000000) // EBI Chip Select 2 size in byte (262144 Kbytes)\r
+// EBI_CS3\r
+#define AT91C_EBI_CS3   (0x40000000) // EBI Chip Select 3 base address\r
+#define AT91C_EBI_CS3_SIZE      (0x10000000) // EBI Chip Select 3 size in byte (262144 Kbytes)\r
+// EBI_SM\r
+#define AT91C_EBI_SM    (0x40000000) // NANDFLASH on EBI Chip Select 3 base address\r
+#define AT91C_EBI_SM_SIZE       (0x10000000) // NANDFLASH on EBI Chip Select 3 size in byte (262144 Kbytes)\r
+// EBI_CS4\r
+#define AT91C_EBI_CS4   (0x50000000) // EBI Chip Select 4 base address\r
+#define AT91C_EBI_CS4_SIZE      (0x10000000) // EBI Chip Select 4 size in byte (262144 Kbytes)\r
+// EBI_CF0\r
+#define AT91C_EBI_CF0   (0x50000000) // CompactFlash 0 on EBI Chip Select 4 base address\r
+#define AT91C_EBI_CF0_SIZE      (0x10000000) // CompactFlash 0 on EBI Chip Select 4 size in byte (262144 Kbytes)\r
+// EBI_CS5\r
+#define AT91C_EBI_CS5   (0x60000000) // EBI Chip Select 5 base address\r
+#define AT91C_EBI_CS5_SIZE      (0x10000000) // EBI Chip Select 5 size in byte (262144 Kbytes)\r
+// EBI_CF1\r
+#define AT91C_EBI_CF1   (0x60000000) // CompactFlash 1 on EBIChip Select 5 base address\r
+#define AT91C_EBI_CF1_SIZE      (0x10000000) // CompactFlash 1 on EBIChip Select 5 size in byte (262144 Kbytes)\r
+\r
+#endif\r

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/system/at91sam3u4/chip.h b/Demo/CORTEX_AT91SAM3U256_IAR/system/at91sam3u4/chip.h
new file mode 100644 (file)
index 0000000..59f048a
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/system/at91sam3u4/chip.h
@@ -0,0 +1,99 @@
+/* ----------------------------------------------------------------------------\r
+ *         ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+ \r
+//------------------------------------------------------------------------------\r
+/// \unit\r
+/// !Purpose\r
+///\r
+/// Definition of AT91SAM3U4 characteristics and features\r
+///\r
+/// !Usage\r
+/// -# For ARM core feature, see "AT91SAM3U4 - ARM core features".\r
+/// -# For IP features, see "AT91SAM3U4 - IP features".\r
+/// -# For misc, see "AT91SAM3U4 - Misc".\r
+//------------------------------------------------------------------------------\r
+ \r
+#ifndef CHIP_H \r
+#define CHIP_H\r
+\r
+//------------------------------------------------------------------------------\r
+//         Headers\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+//         Definitions\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+/// \page "AT91SAM3U4 - ARM core features"\r
+/// This page lists several characteristics related to the ARM core\r
+///\r
+\r
+//ARM core features\r
+\r
+/// ARM core definition.\r
+#define cortexm3\r
+\r
+/// family definition.\r
+#define at91sam3u\r
+\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+/// \page "AT91SAM3U4 - IP features"\r
+/// This page lists several characteristics related to the embedded IP\r
+///\r
+\r
+//IP FEATURES\r
+\r
+// EFC GPNVM number\r
+#define CHIP_EFC_NUM_GPNVMS    3\r
+\r
+/// Indicates chip has an Enhanced EFC. \r
+#define CHIP_FLASH_EEFC \r
+\r
+// DMA channels number\r
+#define CHIP_DMA_CHANNEL_NUM   4\r
+\r
+// Indicate chip has a nandflash controller. \r
+#define CHIP_NAND_CTRL\r
+ \r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+/// \page "AT91SAM3U4 - Misc "\r
+/// This page lists misc features\r
+///\r
+\r
+//Misc \r
+\r
+//------------------------------------------------------------------------------\r
+\r
+#endif //#ifndef CHIP_H\r
+\r

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/system/at91sam3u4/flash.icf b/Demo/CORTEX_AT91SAM3U256_IAR/system/at91sam3u4/flash.icf
new file mode 100644 (file)
index 0000000..a7b3a93
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/system/at91sam3u4/flash.icf
@@ -0,0 +1,47 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/\r
+/*-Editor annotation file-*/\r
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */\r
+/*-Vector table start*/\r
+define symbol __ICFEDIT_vector_start__ = 0x00080000; /*Add for CMSIS*/\r
+/*-Memory Regions-*/\r
+define symbol __ICFEDIT_region_RAM0_start__  = 0x20000000;\r
+define symbol __ICFEDIT_region_RAM0_end__    = 0x20007FFF;\r
+define symbol __ICFEDIT_region_RAM1_start__  = 0x20080000;\r
+define symbol __ICFEDIT_region_RAM1_end__    = 0x20083FFF;\r
+define symbol __ICFEDIT_region_ROM0_start__  = 0x00080000;\r
+define symbol __ICFEDIT_region_ROM0_end__    = 0x0009FFFF;\r
+define symbol __ICFEDIT_region_ROM1_start__  = 0x00100000;\r
+define symbol __ICFEDIT_region_ROM1_end__    = 0x0011FFFF;\r
+/*-Sizes-*/\r
+define symbol __ICFEDIT_size_cstack__        = 0x800;\r
+define symbol __ICFEDIT_size_heap__          = 0x200;\r
+/*-Specials-*/\r
+/*define symbol __ICFEDIT_region_RAM_VECT_start__ = __ICFEDIT_region_RAM0_start__;*/ /*Referenced for CMSIS*/\r
+/*define symbol __ICFEDIT_size_vectors__          = 0x100;*/ /*Referenced for CMSIS*/\r
+/*-Exports-*/\r
+/*export symbol __ICFEDIT_region_RAM_VECT_start__;*/\r
+export symbol __ICFEDIT_vector_start__; /*Add for CMSIS*/\r
+/**** End of ICF editor section. ###ICF###*/\r
+\r
+define memory mem with size   = 4G;\r
+/*define region RAM_VECT_region = mem:[from __ICFEDIT_region_RAM_VECT_start__ size __ICFEDIT_size_vectors__];*/ /*Referenced for CMSIS*/\r
+/*define region RAM0_region     = mem:[from __ICFEDIT_region_RAM0_start__+__ICFEDIT_size_vectors__ to __ICFEDIT_region_RAM0_end__];*/ /*Referenced for CMSIS*/\r
+define region RAM0_region     = mem:[from __ICFEDIT_region_RAM0_start__ to __ICFEDIT_region_RAM0_end__];\r
+define region RAM1_region     = mem:[from __ICFEDIT_region_RAM1_start__ to __ICFEDIT_region_RAM1_end__];\r
+/*define region RAM_region      = mem:[from __ICFEDIT_region_RAM0_start__+__ICFEDIT_size_vectors__ to __ICFEDIT_region_RAM0_end__] |\r
+                                mem:[from __ICFEDIT_region_RAM1_start__ to __ICFEDIT_region_RAM1_end__];*/ /*Referenced for CMSIS*/\r
+define region ROM0_region     = mem:[from __ICFEDIT_region_ROM0_start__ to __ICFEDIT_region_ROM0_end__];\r
+define region ROM1_region     = mem:[from __ICFEDIT_region_ROM1_start__ to __ICFEDIT_region_ROM1_end__];\r
+\r
+/*define block RamVect   with alignment = 8, size = __ICFEDIT_size_vectors__  { };*/\r
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };\r
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };\r
+\r
+initialize by copy { readwrite };\r
+do not initialize  { section .noinit };\r
+\r
+/*place at start of ROM0_region { readonly section .vectors };*/ /*Referenced for CMSIS*/\r
+place at address mem:__ICFEDIT_vector_start__ { readonly section .vectors }; /*Add for CMSIS*/\r
+place in ROM0_region          { readonly };\r
+place in RAM0_region          { readwrite, block CSTACK, block HEAP };\r
+/*place in RAM_VECT_region      { block RamVect };*/ /*Referenced for CMSIS*/
\ No newline at end of file

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/system/at91sam3u4/sram.icf b/Demo/CORTEX_AT91SAM3U256_IAR/system/at91sam3u4/sram.icf
new file mode 100644 (file)
index 0000000..4290bf5
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/system/at91sam3u4/sram.icf
@@ -0,0 +1,33 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/\r
+/*-Editor annotation file-*/\r
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */\r
+/*-Vector table start*/\r
+define symbol __ICFEDIT_vector_start__ = 0x20000000;\r
+/*-Memory Regions-*/\r
+define symbol __ICFEDIT_region_RAM0_start__  = 0x20000000;\r
+define symbol __ICFEDIT_region_RAM0_end__    = 0x20007FFF;\r
+define symbol __ICFEDIT_region_RAM1_start__  = 0x20080000;\r
+define symbol __ICFEDIT_region_RAM1_end__    = 0x20083FFF;\r
+/*-Sizes-*/\r
+define symbol __ICFEDIT_size_cstack__        = 0x400;\r
+define symbol __ICFEDIT_size_heap__          = 0x200;\r
+/*-Exports-*/\r
+export symbol __ICFEDIT_vector_start__;\r
+/**** End of ICF editor section. ###ICF###*/\r
+\r
+define memory mem with size   = 4G;\r
+define region RAM0_region     = mem:[from __ICFEDIT_region_RAM0_start__ to __ICFEDIT_region_RAM0_end__];\r
+define region RAM1_region     = mem:[from __ICFEDIT_region_RAM1_start__ to __ICFEDIT_region_RAM1_end__];\r
+/*define region RAM_region      = mem:[from __ICFEDIT_region_RAM0_start__+__ICFEDIT_size_vectors__ to __ICFEDIT_region_RAM0_end__] |\r
+                                mem:[from __ICFEDIT_region_RAM1_start__ to __ICFEDIT_region_RAM1_end__];*/\r
+\r
+/* define block RamVect   with alignment = 8, size = __ICFEDIT_size_vectors__  { }; */\r
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };\r
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };\r
+\r
+initialize by copy { readwrite };\r
+do not initialize  { section .noinit };\r
+\r
+place at address mem:__ICFEDIT_vector_start__ { readonly section .vectors };\r
+place in RAM0_region          { readonly };\r
+place in RAM1_region          { readwrite, block CSTACK, block HEAP };\r

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/system/board.h b/Demo/CORTEX_AT91SAM3U256_IAR/system/board.h
new file mode 100644 (file)
index 0000000..694e003
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/system/board.h
@@ -0,0 +1,747 @@
+/* ----------------------------------------------------------------------------\r
+ *         ATMEL Microcontroller Software Support\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+//------------------------------------------------------------------------------\r
+/// \dir\r
+/// !Purpose\r
+///\r
+/// Definition and functions for using AT91SAM3UE-related features, such\r
+/// has PIO pins, memories, etc.\r
+///\r
+/// !Usage\r
+/// -# The code for booting the board is provided by board_cstartup.S and\r
+///    board_lowlevel.c.\r
+/// -# For using board PIOs, board characteristics (clock, etc.) and external\r
+///    components, see board.h.\r
+/// -# For manipulating memories (remapping, SDRAM, etc.), see board_memories.h.\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+/// \unit\r
+/// !Purpose\r
+///\r
+/// Definition of AT91SAM3UE-EK characteristics, AT91SAM3UE-dependant PIOs and\r
+/// external components interfacing.\r
+///\r
+/// !Usage\r
+/// -# For operating frequency information, see "SAM3UE-EK - Operating frequencies".\r
+/// -# For using portable PIO definitions, see "SAM3UE-EK - PIO definitions".\r
+/// -# Several USB definitions are included here (see "SAM3UE-EK - USB device").\r
+//------------------------------------------------------------------------------\r
+\r
+#ifndef BOARD_H\r
+#define BOARD_H\r
+\r
+//------------------------------------------------------------------------------\r
+//         Headers\r
+//------------------------------------------------------------------------------\r
+\r
+#if defined(at91sam3u4)\r
+    #include "at91sam3u4/chip.h"\r
+    #include "at91sam3u4/AT91SAM3U4.h"\r
+#else\r
+    #error Board does not support the specified chip.\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+//         Definitions\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+/// \page "SAM3UE-EK - Board Description"\r
+/// This page lists several definition related to the board description.\r
+///\r
+/// !Definitions\r
+/// - BOARD_NAME\r
+\r
+/// Name of the board.\r
+#define BOARD_NAME "AT91SAM3U-EK"\r
+/// Board definition.\r
+#define at91sam3uek\r
+/// Family definition (already defined).\r
+#define at91sam3u\r
+/// Core definition\r
+#define cortexm3\r
+// Chip type\r
+//#define fpgasimulation\r
+//------------------------------------------------------------------------------\r
+\r
+#if defined(fpgasimulation)\r
+#define PMC_BY_HARD\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+/// \page "SAM3UE-EK - Operating frequencies"\r
+/// This page lists several definition related to the board operating frequency\r
+/// (when using the initialization done by board_lowlevel.c).\r
+///\r
+/// !Definitions\r
+/// - BOARD_MAINOSC\r
+/// - BOARD_MCK\r
+\r
+/// Frequency of the board main oscillator.\r
+#define BOARD_MAINOSC           12000000\r
+\r
+/// Master clock frequency (when using board_lowlevel.c).\r
+#if !defined(fpgasimulation)\r
+#define BOARD_MCK               48000000\r
+#else\r
+#define BOARD_MCK               22579200\r
+#endif\r
+\r
+#if defined (fpgasimulation)\r
+//#define BOARD_ConfigureSdram(...) { }\r
+#endif // fpgasimulation\r
+\r
+//------------------------------------------------------------------------------\r
+// ADC\r
+//------------------------------------------------------------------------------\r
+/// ADC clock frequency, at 10-bit resolution (in Hz)\r
+#define ADC_MAX_CK_10BIT         5000000\r
+/// Startup time max, return from Idle mode (in µs)\r
+#define ADC_STARTUP_TIME_MAX       15\r
+/// Track and hold Acquisition Time min (in ns)\r
+#define ADC_TRACK_HOLD_TIME_MIN  1200\r
+\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+/// \page "SAM3UE-EK - USB device"\r
+/// This page lists constants describing several characteristics (controller\r
+/// type, D+ pull-up type, etc.) of the USB device controller of the chip/board.\r
+///\r
+/// !Constants\r
+/// - BOARD_USB_UDP\r
+/// - BOARD_USB_PULLUP_EXTERNAL\r
+/// - BOARD_USB_NUMENDPOINTS\r
+/// - BOARD_USB_ENDPOINTS_MAXPACKETSIZE\r
+/// - BOARD_USB_ENDPOINTS_BANKS\r
+\r
+/// Chip has a UDP controller.\r
+#define BOARD_USB_UDPHS\r
+\r
+/// Indicates the D+ pull-up is external.\r
+#define BOARD_USB_PULLUP_INTERNAL\r
+\r
+/// Number of endpoints in the USB controller.\r
+#define BOARD_USB_NUMENDPOINTS              7\r
+\r
+/// Returns the maximum packet size of the given endpoint.\r
+#define BOARD_USB_ENDPOINTS_MAXPACKETSIZE(i) (((i == 0)||(i == 3)||(i == 4)) ? 64 :\\r
+                                             (((i == 1) || (i == 2)) ? 512 : 1024))\r
+\r
+/// Returns the number of FIFO banks for the given endpoint.\r
+#define BOARD_USB_ENDPOINTS_BANKS(i)        ((i == 0) ? 1 : ((i == 1) || (i == 2)) ? 2 : 3)\r
+\r
+/// USB attributes configuration descriptor (bus or self powered, remote wakeup)\r
+#define BOARD_USB_BMATTRIBUTES              USBConfigurationDescriptor_SELFPOWERED_RWAKEUP\r
+//#define BOARD_USB_BMATTRIBUTES            USBConfigurationDescriptor_SELFPOWERED_NORWAKEUP\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+/// \page "SAM3UE-EK - PIO definitions"\r
+/// This pages lists all the pio definitions contained in board.h. The constants\r
+/// are named using the following convention: PIN_* for a constant which defines\r
+/// a single Pin instance (but may include several PIOs sharing the same\r
+/// controller), and PINS_* for a list of Pin instances.\r
+///\r
+/// !ADC\r
+/// - PIN_ADC0_AD0\r
+/// - PIN_ADC0_AD1\r
+/// - PIN_ADC0_AD2\r
+/// - PIN_ADC0_AD3\r
+/// - PIN_ADC0_AD4\r
+/// - PIN_ADC0_AD5\r
+/// - PIN_ADC0_AD6\r
+/// - PIN_ADC0_AD7\r
+/// - PINS_ADC0\r
+///\r
+/// !CAN\r
+/// - PIN_CAN_TRANSCEIVER_RS\r
+/// - PIN_CAN1_TRANSCEIVER_TXD\r
+/// - PIN_CAN1_TRANSCEIVER_RXD\r
+/// - PIN_CAN2_TRANSCEIVER_TXD\r
+/// - PIN_CAN2_TRANSCEIVER_RXD\r
+/// - PINS_CAN_TRANSCEIVER_TXD\r
+/// - PINS_CAN_TRANSCEIVER_RXD\r
+///\r
+/// !DBGU\r
+/// - PINS_DBGU\r
+///\r
+/// !Joystick buttons\r
+/// - PIN_JOYSTICK_UP\r
+/// - PIN_JOYSTICK_DOWN\r
+/// - PIN_JOYSTICK_LEFT\r
+/// - PIN_JOYSTICK_RIGHT\r
+/// - PIN_JOYSTICK_LCLIC, PIN_JOYSTICK_PUSH\r
+/// - PINS_JOYSTICK_MOVE, PINS_JOYSTICK_CLIC, PINS_JOYSTICK\r
+/// - JOYSTICK_UP\r
+/// - JOYSTICK_DOWN\r
+/// - JOYSTICK_LEFT\r
+/// - JOYSTICK_RIGHT\r
+/// - JOYSTICK_LCLIC, JOYSTICK_PUSH\r
+///\r
+/// !EBI\r
+/// - PIN_EBI_DATA_BUS\r
+/// - PIN_EBI_NCS0\r
+/// - PIN_EBI_NRD\r
+/// - PIN_EBI_NWE\r
+/// - PIN_EBI_ADDR_BUS\r
+/// - PIN_EBI_PSRAM_NBS\r
+/// - PIN_EBI_A1\r
+/// - PIN_EBI_LCD_RS\r
+///\r
+/// !LEDs\r
+/// - PIN_LED_DS1\r
+/// - PIN_LED_DS2\r
+/// - PIN_LED_DS3\r
+/// - PIN_LED_DS4\r
+/// - PINS_LEDS\r
+/// - LED_DS1\r
+/// - LED_DS2\r
+/// - LED_DS3\r
+/// - LED_DS4\r
+///\r
+/// !MCI\r
+/// - PINS_MCI\r
+///\r
+/// !Push buttons\r
+/// - PIN_PUSHBUTTON_1\r
+/// - PIN_PUSHBUTTON_2\r
+/// - PIN_PUSHBUTTON_3\r
+/// - PIN_PUSHBUTTON_4\r
+/// - PINS_PUSHBUTTONS\r
+/// - PUSHBUTTON_BP1\r
+/// - PUSHBUTTON_BP2\r
+/// - PUSHBUTTON_BP3\r
+/// - PUSHBUTTON_BP4\r
+///\r
+/// !PWMC\r
+/// - PIN_PWMC_PWM0\r
+/// - PIN_PWMC_PWM1\r
+/// - PIN_PWMC_PWM2\r
+/// - PIN_PWMC_PWM3\r
+/// - PIN_PWMC_PWM4\r
+/// - PIN_PWMC_PWM5\r
+/// - PIN_PWMC_PWM6\r
+/// - PIN_PWMC_PWM7\r
+/// - PIN_PWM_LED0\r
+/// - PIN_PWM_LED1\r
+/// - CHANNEL_PWM_LED0\r
+/// - CHANNEL_PWM_LED1\r
+///\r
+/// !SPI0\r
+/// - PIN_SPI0_MISO\r
+/// - PIN_SPI0_MOSI\r
+/// - PIN_SPI0_SPCK\r
+/// - PINS_SPI0\r
+/// - PIN_SPI0_NPCS3\r
+///\r
+/// !SPI1\r
+/// - PIN_SPI1_MISO\r
+/// - PIN_SPI1_MOSI\r
+/// - PIN_SPI1_SPCK\r
+/// - PINS_SPI1\r
+/// - PIN_SPI1_NPCS3\r
+///\r
+/// ! SSC\r
+/// - PIN_SSC_TD\r
+/// - PIN_SSC_TK\r
+/// - PIN_SSC_TF\r
+/// - PINS_SSC_CODEC\r
+///\r
+/// ! PCK0\r
+/// - PIN_PCK0\r
+///\r
+/// !TWI\r
+/// - PIN_TWI_TWD0\r
+/// - PIN_TWI_TWCK0\r
+/// - PINS_TWI\r
+///\r
+/// !USART0\r
+/// - PIN_USART0_RXD\r
+/// - PIN_USART0_TXD\r
+/// - PIN_USART0_CTS\r
+/// - PIN_USART0_RTS\r
+/// - PIN_USART0_SCK\r
+///\r
+/// !USB\r
+/// - PIN_USB_PULLUP\r
+///\r
+\r
+/// ADC_AD0 pin definition.\r
+#define PIN_ADC0_AD0 {1 << 21, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_INPUT, PIO_DEFAULT}\r
+/// ADC_AD1 pin definition.\r
+#define PIN_ADC0_AD1 {1 << 30, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_INPUT, PIO_DEFAULT}\r
+/// ADC_AD2 pin definition.\r
+#define PIN_ADC0_AD2 {1 << 3, AT91C_BASE_PIOB, AT91C_ID_PIOB, PIO_INPUT, PIO_DEFAULT}\r
+/// ADC_AD3 pin definition.\r
+#define PIN_ADC0_AD3 {1 << 4, AT91C_BASE_PIOB, AT91C_ID_PIOB, PIO_INPUT, PIO_DEFAULT}\r
+/// ADC_AD4 pin definition.\r
+#define PIN_ADC0_AD4 {1 << 15, AT91C_BASE_PIOC, AT91C_ID_PIOC, PIO_INPUT, PIO_DEFAULT}\r
+/// ADC_AD5 pin definition.\r
+#define PIN_ADC0_AD5 {1 << 16, AT91C_BASE_PIOC, AT91C_ID_PIOC, PIO_INPUT, PIO_DEFAULT}\r
+/// ADC_AD6 pin definition.\r
+#define PIN_ADC0_AD6 {1 << 17, AT91C_BASE_PIOC, AT91C_ID_PIOC, PIO_INPUT, PIO_DEFAULT}\r
+/// ADC_AD7 pin definition.\r
+#define PIN_ADC0_AD7 {1 << 18, AT91C_BASE_PIOC, AT91C_ID_PIOC, PIO_INPUT, PIO_DEFAULT}\r
+\r
+/// Pins ADC\r
+#define PINS_ADC PIN_ADC0_AD0, PIN_ADC0_AD1, PIN_ADC0_AD2, PIN_ADC0_AD3, PIN_ADC0_AD4, PIN_ADC0_AD5, PIN_ADC0_AD6, PIN_ADC0_AD7\r
+\r
+/// CAN Definition\r
+/// RS: Select input for high speed mode or silent mode\r
+//#define PIN_CAN_TRANSCEIVER_RS  {1<<23, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_OUTPUT_1, PIO_DEFAULT}\r
+//\r
+///// TXD: Transmit data input\r
+//#define PIN_CAN1_TRANSCEIVER_TXD  {1<<27, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}\r
+///// RXD: Receive data output\r
+//#define PIN_CAN1_TRANSCEIVER_RXD  {1<<26, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}\r
+/// TXD: Transmit data input\r
+//#define PIN_CAN2_TRANSCEIVER_TXD  {1<<29, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}\r
+///// RXD: Receive data output\r
+//#define PIN_CAN2_TRANSCEIVER_RXD  {1<<28, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}\r
+///// TXD pins\r
+//#define PINS_CAN_TRANSCEIVER_TXD  PIN_CAN1_TRANSCEIVER_TXD, PIN_CAN2_TRANSCEIVER_TXD\r
+///// RXD pins\r
+//#define PINS_CAN_TRANSCEIVER_RXD  PIN_CAN1_TRANSCEIVER_RXD, PIN_CAN2_TRANSCEIVER_RXD\r
+\r
+/// DBGU pins (DTXD and DRXD) definitions, PA11,12.\r
+#define PINS_DBGU  {0x00001800, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}\r
+\r
+/// EBI\r
+#define PIN_EBI_DATA_BUS            {0xfe01fe00, AT91C_BASE_PIOB, AT91C_ID_PIOB, PIO_PERIPH_A, PIO_PULLUP}, \\r
+                                        {1 << 6, AT91C_BASE_PIOB, AT91C_ID_PIOB, PIO_PERIPH_B, PIO_PULLUP}\r
+#define PIN_EBI_NCS0                {1 << 20, AT91C_BASE_PIOB, AT91C_ID_PIOB, PIO_PERIPH_A, PIO_PULLUP}\r
+#define PIN_EBI_NRD                 {1 << 19, AT91C_BASE_PIOB, AT91C_ID_PIOB, PIO_PERIPH_A, PIO_PULLUP}\r
+#define PIN_EBI_NWE                 {1 << 23, AT91C_BASE_PIOB, AT91C_ID_PIOB, PIO_PERIPH_A, PIO_PULLUP}\r
+#define PIN_EBI_PSRAM_ADDR_BUS      {0x3f00fff, AT91C_BASE_PIOC, AT91C_ID_PIOC, PIO_PERIPH_A, PIO_PULLUP}\r
+#define PIN_EBI_PSRAM_NBS           {1 << 7, AT91C_BASE_PIOB, AT91C_ID_PIOB, PIO_PERIPH_B, PIO_PULLUP}, \\r
+                                        {1 << 15, AT91C_BASE_PIOC, AT91C_ID_PIOC, PIO_PERIPH_A, PIO_PULLUP}\r
+#define PIN_EBI_A1                  {1 << 8, AT91C_BASE_PIOB, AT91C_ID_PIOB, PIO_PERIPH_B, PIO_PULLUP}\r
+\r
+#define PIN_EBI_NCS2                {1 << 16, AT91C_BASE_PIOC, AT91C_ID_PIOC, PIO_PERIPH_A, PIO_PULLUP}\r
+#define PIN_EBI_LCD_RS              {1 << 8, AT91C_BASE_PIOB, AT91C_ID_PIOB, PIO_PERIPH_B, PIO_PULLUP}\r
+\r
+\r
+/// LED #0 pin definition.\r
+#define PIN_LED_0   {1 << 0, AT91C_BASE_PIOB, AT91C_ID_PIOB, PIO_OUTPUT_0, PIO_DEFAULT}\r
+/// LED #1 pin definition.\r
+#define PIN_LED_1   {1 << 2, AT91C_BASE_PIOB, AT91C_ID_PIOB, PIO_OUTPUT_1, PIO_DEFAULT}\r
+/// LED #2 pin definition.\r
+#define PIN_LED_2   {1 << 1, AT91C_BASE_PIOB, AT91C_ID_PIOB, PIO_OUTPUT_1, PIO_DEFAULT}\r
+/// List of all LEDs definitions.\r
+#define PINS_LEDS   PIN_LED_0, PIN_LED_1, PIN_LED_2\r
+\r
+///// MCI pins definition.\r
+#define PINS_MCI  {0x1f8, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_PERIPH_A, PIO_PULLUP}, \\r
+                      {1 << 3, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}\r
+\r
+/// MCI pin Card Detect\r
+#define PIN_MCI_CD \\r
+    {AT91C_PIO_PA25, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_INPUT, PIO_PULLUP}\r
+\r
+/// Push button #0 definition.\r
+#define PIN_PUSHBUTTON_1    {1 << 18, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_INPUT, PIO_DEGLITCH | PIO_PULLUP}\r
+/// Push button #1 definition.\r
+#define PIN_PUSHBUTTON_2    {1 << 19, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_INPUT, PIO_DEGLITCH | PIO_PULLUP}\r
+/// Push button #2 definition\r
+/// List of all push button definitions.\r
+#define PINS_PUSHBUTTONS    PIN_PUSHBUTTON_1, PIN_PUSHBUTTON_2\r
+\r
+/// Push button #1 index.\r
+#define PUSHBUTTON_BP1   0\r
+/// Push button #2 index.\r
+#define PUSHBUTTON_BP2   1\r
+\r
+/// Simulated joystick LEFT index.\r
+#define JOYSTICK_LEFT       0\r
+/// Simulated joystick RIGHT index.\r
+#define JOYSTICK_RIGHT      1\r
+\r
+/// SPI0 MISO pin definition.\r
+#define PIN_SPI0_MISO  {1 << 13, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}\r
+/// SPI0 MOSI pin definition.\r
+#define PIN_SPI0_MOSI  {1 << 14, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}\r
+/// SPI0 SPCK pin definition.\r
+#define PIN_SPI0_SPCK  {1 << 15, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}\r
+/// SPI0 chip select 2 pin definition.\r
+//#define PIN_SPI0_NPCS2_PC14  {1 <<  14, AT91C_BASE_PIOC, AT91C_ID_PIOC, PIO_PERIPH_B, PIO_DEFAULT}\r
+#define PIN_SPI0_NPCS2_PC14  {1 <<  14, AT91C_BASE_PIOC, AT91C_ID_PIOC, PIO_OUTPUT_0, PIO_PULLUP}\r
+/// List of SPI0 pin definitions (MISO, MOSI & SPCK).\r
+#define PINS_SPI0      PIN_SPI0_MISO, PIN_SPI0_MOSI, PIN_SPI0_SPCK\r
+\r
+/// SSC pins definition.\r
+#define PIN_SSC_TD      {0x1 << 26, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}\r
+#define PIN_SSC_TK      {0x1 << 28, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}\r
+#define PIN_SSC_TF      {0x1 << 30, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}\r
+#define PINS_SSC_CODEC       PIN_SSC_TD,  PIN_SSC_TK, PIN_SSC_TF\r
+\r
+/// PCK0\r
+#define PIN_PCK0        {0x1 << 21, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_PERIPH_B, PIO_DEFAULT}\r
+\r
+/// TWI pins definition.\r
+#define TWI_V3XX\r
+#define PIN_TWI_TWD0    {0x1 << 9, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}\r
+#define PIN_TWI_TWCK0    {0x1 << 10, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}\r
+#define PINS_TWI0     PIN_TWI_TWD0, PIN_TWI_TWCK0\r
+#define PIN_TWI_TWD1    {0x1 << 24, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}\r
+#define PIN_TWI_TWCK1    {0x1 << 25, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}\r
+#define PINS_TWI1     PIN_TWI_TWD1, PIN_TWI_TWCK1\r
+\r
+/// USART0\r
+#define PIN_USART0_RXD    {0x1 << 19, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}\r
+#define PIN_USART0_TXD    {0x1 << 18, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}\r
+#define PIN_USART0_CTS    {0x1 << 8, AT91C_BASE_PIOB, AT91C_ID_PIOB, PIO_PERIPH_A, PIO_DEFAULT}\r
+#define PIN_USART0_RTS    {0x1 << 7, AT91C_BASE_PIOB, AT91C_ID_PIOB, PIO_PERIPH_A, PIO_DEFAULT}\r
+#define PIN_USART0_SCK    {0x1 << 17, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}\r
+\r
+/// USART1\r
+#define PIN_USART1_RXD    {0x1 << 21, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}\r
+#define PIN_USART1_TXD    {0x1 << 20, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}\r
+#define PIN_USART1_CTS    {0x1 << 23, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_PERIPH_B, PIO_DEFAULT}\r
+#define PIN_USART1_RTS    {0x1 << 22, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_PERIPH_B, PIO_DEFAULT}\r
+#define PIN_USART1_SCK    {0x1 << 24, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_PERIPH_B, PIO_DEFAULT}\r
+\r
+/// USB VBus monitoring pin definition.\r
+#define PIN_USB_VBUS    {1 << 31, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_INPUT, PIO_PULLUP}\r
+\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+/// \page "SAM3UE-EK - External components"\r
+/// This page lists the definitions related to external on-board components\r
+/// located in the board.h file for the AT91SAM3UE-EK.\r
+///\r
+/// !AT45 Dataflash Card\r
+/// - BOARD_AT45_A_SPI_BASE\r
+/// - BOARD_AT45_A_SPI_ID\r
+/// - BOARD_AT45_A_SPI_PINS\r
+/// - BOARD_AT45_A_SPI\r
+/// - BOARD_AT45_A_NPCS\r
+/// - BOARD_AT45_A_NPCS_PIN\r
+///\r
+/// !AT45 Dataflash (serial onboard DataFlash)\r
+/// - BOARD_AT45_B_SPI_BASE\r
+/// - BOARD_AT45_B_SPI_ID\r
+/// - BOARD_AT45_B_SPI_PINS\r
+/// - BOARD_AT45_B_SPI\r
+/// - BOARD_AT45_B_NPCS\r
+/// - BOARD_AT45_B_NPCS_PIN\r
+///\r
+/// !AT26 Serial Flash\r
+/// - BOARD_AT26_A_SPI_BASE\r
+/// - BOARD_AT26_A_SPI_ID\r
+/// - BOARD_AT26_A_SPI_PINS\r
+/// - BOARD_AT26_A_SPI\r
+/// - BOARD_AT26_A_NPCS\r
+/// - BOARD_AT26_A_NPCS_PIN\r
+///\r
+/// !SD Card\r
+/// - MCI2_INTERFACE\r
+/// - BOARD_SD_MCI_BASE\r
+/// - BOARD_SD_MCI_ID\r
+/// - BOARD_SD_PINS\r
+/// - BOARD_SD_SLOT\r
+///\r
+/// !PSRAM\r
+/// - BOARD_PSRAM_PINS\r
+/// - BOARD_LCD_PINS\r
+\r
+/// Base address of SPI peripheral connected to the dataflash.\r
+//#define BOARD_AT45_A_SPI_BASE         AT91C_BASE_SPI0\r
+///// Identifier of SPI peripheral connected to the dataflash.\r
+//#define BOARD_AT45_A_SPI_ID           AT91C_ID_SPI0\r
+///// Pins of the SPI peripheral connected to the dataflash.\r
+//#define BOARD_AT45_A_SPI_PINS         PINS_SPI0\r
+///// Dataflahs SPI number.\r
+//#define BOARD_AT45_A_SPI              0\r
+///// Chip select connected to the dataflash.\r
+//#define BOARD_AT45_A_NPCS             3\r
+///// Chip select pin connected to the dataflash.\r
+//#define BOARD_AT45_A_NPCS_PIN         PIN_SPI0_NPCS3\r
+\r
+/// Base address of SPI peripheral connected to the dataflash.\r
+//#define BOARD_AT45_B_SPI_BASE         AT91C_BASE_SPI1\r
+///// Identifier of SPI peripheral connected to the dataflash.\r
+//#define BOARD_AT45_B_SPI_ID           AT91C_ID_SPI1\r
+///// Pins of the SPI peripheral connected to the dataflash.\r
+//#define BOARD_AT45_B_SPI_PINS         PINS_SPI1\r
+///// Dataflahs SPI number.\r
+//#define BOARD_AT45_B_SPI              1\r
+///// Chip select connected to the dataflash.\r
+//#define BOARD_AT45_B_NPCS             3\r
+///// Chip select pin connected to the dataflash.\r
+//#define BOARD_AT45_B_NPCS_PIN         PIN_SPI1_NPCS3\r
+\r
+/// Base address of SPI peripheral connected to the serialflash.\r
+//#define BOARD_AT26_A_SPI_BASE         AT91C_BASE_SPI0\r
+///// Identifier of SPI peripheral connected to the serialflash.\r
+//#define BOARD_AT26_A_SPI_ID           AT91C_ID_SPI0\r
+///// Pins of the SPI peripheral connected to the serialflash.\r
+//#define BOARD_AT26_A_SPI_PINS         PINS_SPI0\r
+///// Serialflash SPI number.\r
+//#define BOARD_AT26_A_SPI              0\r
+///// Chip select connected to the serialflash.\r
+//#define BOARD_AT26_A_NPCS             3\r
+///// Chip select pin connected to the serialflash.\r
+//#define BOARD_AT26_A_NPCS_PIN         PIN_SPI0_NPCS3\r
+\r
+/// HS MCI interface\r
+#define MCI2_INTERFACE\r
+/// Base address of the MCI peripheral connected to the SD card.\r
+#define BOARD_SD_MCI_BASE           AT91C_BASE_MCI0//AT91C_BASE_MCI\r
+///// Peripheral identifier of the MCI connected to the SD card.\r
+#define BOARD_SD_MCI_ID             AT91C_ID_MCI0 //AT91C_ID_MCI\r
+///// MCI pins that shall be configured to access the SD card.\r
+#define BOARD_SD_PINS               PINS_MCI\r
+///// MCI slot to which the SD card is connected to.\r
+#define BOARD_SD_SLOT               MCI_SD_SLOTA\r
+///// MCI Card Detect pin.\r
+#define BOARD_SD_PIN_CD             PIN_MCI_CD\r
+\r
+#define BOARD_PSRAM_PINS            PIN_EBI_DATA_BUS, PIN_EBI_NCS0, PIN_EBI_NRD, PIN_EBI_NWE, \\r
+                                        PIN_EBI_PSRAM_ADDR_BUS, PIN_EBI_PSRAM_NBS, PIN_EBI_A1\r
+\r
+/// Indicates board has an HX8347 external component to manage LCD.\r
+#define BOARD_LCD_HX8347\r
+\r
+/// LCD pins definition.\r
+#define BOARD_LCD_PINS              PIN_EBI_DATA_BUS, PIN_EBI_LCD_RS, PIN_EBI_NRD, PIN_EBI_NWE, \\r
+                                        PIN_EBI_NCS2\r
+/// Backlight pin definition.\r
+#define BOARD_BACKLIGHT_PIN       {1 << 19, AT91C_BASE_PIOC, AT91C_ID_PIOC, \\r
+                                      PIO_OUTPUT_0, PIO_DEFAULT}\r
+/// Define HX8347 base address.\r
+#define BOARD_LCD_BASE            0x62000000\r
+/// Define HX8347 register select signal.\r
+#define BOARD_LCD_RS              (1 << 1)\r
+/// Display width in pixels.\r
+#define BOARD_LCD_WIDTH             240\r
+/// Display height in pixels.\r
+#define BOARD_LCD_HEIGHT            320\r
+\r
+/// Indicates board has an ADS7843 external component to manage Touch Screen\r
+#define BOARD_TSC_ADS7843\r
+\r
+/// Touchscreen controller IRQ pin definition.\r
+#define PIN_TCS_IRQ {AT91C_PIO_PA24, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_INPUT, PIO_PULLUP}\r
+/// Touchscreen controller Busy pin definition.\r
+#define PIN_TCS_BUSY {AT91C_PIO_PA2, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_INPUT, PIO_PULLUP}\r
+\r
+/// Base address of SPI peripheral connected to the touchscreen controller.\r
+#define BOARD_TSC_SPI_BASE         AT91C_BASE_SPI0\r
+/// Identifier of SPI peripheral connected to the touchscreen controller.\r
+#define BOARD_TSC_SPI_ID           AT91C_ID_SPI0\r
+/// Pins of the SPI peripheral connected to the touchscreen controller.\r
+#define BOARD_TSC_SPI_PINS         PINS_SPI0\r
+/// Chip select connected to the touchscreen controller.\r
+#define BOARD_TSC_NPCS             2//2\r
+/// Chip select pin connected to the touchscreen controller.\r
+#define BOARD_TSC_NPCS_PIN         PIN_SPI0_NPCS2_PC14\r
+\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+/// \page "SAM3UE-EK - Memories"\r
+/// This page lists definitions related to internal & external on-board memories.\r
+///\r
+/// !Embedded Flash\r
+/// - BOARD_FLASH_EFC\r
+\r
+/// Internal SRAM address\r
+#define AT91C_ISRAM                   AT91C_IRAM\r
+#define AT91C_ISRAM_SIZE         AT91C_IRAM_SIZE\r
+\r
+#define AT91C_IFLASH                   (0x80000)\r
+#define AT91C_IFLASH_SIZE              (0x20000)\r
+#define AT91C_IFLASH_PAGE_SIZE             (256) // Internal FLASH 0 Page Size: 256 bytes\r
+#define AT91C_IFLASH_NB_OF_PAGES           (512) // Internal FLASH 0 Number of Pages: 512\r
+#define AT91C_IFLASH_LOCK_REGION_SIZE     (8192) // Internal FLASH 0 Lock Region Size: 8 Kbytes\r
+#define AT91C_IFLASH_NB_OF_LOCK_BITS        (16) // Internal FLASH 0 Number of Lock Bits: 32\r
+#if 0\r
+#define AT91C_IFLASH1                 (0x100000)\r
+#define AT91C_IFLASH1_SIZE             (0x20000)\r
+#define AT91C_IFLASH1_PAGE_SIZE            (256) // Internal FLASH 1 Page Size: 256 bytes\r
+#define AT91C_IFLASH1_NB_OF_PAGES          (512) // Internal FLASH 1 Number of Pages: 512\r
+#define AT91C_IFLASH1_LOCK_REGION_SIZE   (8192) // Internal FLASH 1 Lock Region Size: 8 Kbytes\r
+#define AT91C_IFLASH1_NB_OF_LOCK_BITS       (16) // Internal FLASH 1 Number of Lock Bits: 32\r
+#endif\r
+/// Indicates chip has an EFC.\r
+#define AT91C_BASE_EFC    AT91C_BASE_EFC0\r
+//------------------------------------------------------------------------------\r
+\r
+\r
+//------------------------------------------------------------------------------\r
+/// \page "SAM3UE-EK - External components"\r
+/// This page lists the definitions related to external on-board components\r
+/// located in the board.h file for the SAM3UE-EK.\r
+///\r
+/// !ISO7816\r
+/// - PIN_SMARTCARD_CONNECT\r
+/// - PIN_ISO7816_RSTMC\r
+/// - PINS_ISO7816\r
+\r
+/// Smartcard detection pin\r
+//#define PIN_SMARTCARD_CONNECT   {1 << 5, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_INPUT, PIO_DEFAULT}\r
+/// PIN used for reset the smartcard\r
+//#define PIN_ISO7816_RSTMC       {1 << 7, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_OUTPUT_0, PIO_DEFAULT}\r
+/// Pins used for connect the smartcard\r
+//#define PINS_ISO7816            PIN_USART0_TXD, PIN_USART0_SCK, PIN_ISO7816_RSTMC\r
+\r
+/// Dma channel number\r
+#define BOARD_MCI_DMA_CHANNEL                         0\r
+/// MCI0 DMA hardware handshaking ID\r
+#define DMA_HW_SRC_REQ_ID_MCI0      AT91C_HDMA_SRC_PER_0\r
+#define DMA_HW_DEST_REQ_ID_MCI0     AT91C_HDMA_DST_PER_0\r
+/// MCI1 DMA hardware handshaking ID\r
+#define DMA_HW_SRC_REQ_ID_MCI1      AT91C_HDMA_SRC_PER_13\r
+#define DMA_HW_DEST_REQ_ID_MCI1     AT91C_HDMA_DST_PER_13\r
+/// SD DMA hardware handshaking ID\r
+#define BOARD_SD_DMA_HW_SRC_REQ_ID      DMA_HW_SRC_REQ_ID_MCI0\r
+#define BOARD_SD_DMA_HW_DEST_REQ_ID     DMA_HW_DEST_REQ_ID_MCI0\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+/// \page "SAM3UE-EK - Individual chip definition"\r
+/// This page lists the definitions related to different chip's definition\r
+/// located in the board.h file for the SAM3UE-EK.\r
+\r
+/// DBGU\r
+#define BOARD_DBGU_ID               AT91C_ID_DBGU\r
+\r
+/// Rtc\r
+#define BOARD_RTC_ID                AT91C_ID_RTC\r
+\r
+/// Twi eeprom\r
+#define BOARD_ID_TWI_EEPROM         AT91C_ID_TWI1\r
+#define BOARD_BASE_TWI_EEPROM       AT91C_BASE_TWI1\r
+#define BOARD_PINS_TWI_EEPROM       PINS_TWI1\r
+\r
+/// USART\r
+#define BOARD_PIN_USART_RXD        PIN_USART1_RXD\r
+#define BOARD_PIN_USART_TXD        PIN_USART1_TXD\r
+#define BOARD_PIN_USART_CTS        PIN_USART1_CTS\r
+#define BOARD_PIN_USART_RTS        PIN_USART1_RTS\r
+#define BOARD_USART_BASE           AT91C_BASE_US1\r
+#define BOARD_ID_USART             AT91C_ID_US1\r
+\r
+/// Interrupt source\r
+typedef enum IRQn\r
+{\r
+/******  Cortex-M3 Processor Exceptions Numbers ***************************************************/\r
+  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                             */\r
+  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M3 Memory Management Interrupt              */\r
+  BusFault_IRQn               = -11,    /*!< 5 Cortex-M3 Bus Fault Interrupt                      */\r
+  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M3 Usage Fault Interrupt                    */\r
+  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M3 SV Call Interrupt                       */\r
+  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M3 Debug Monitor Interrupt                 */\r
+  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M3 Pend SV Interrupt                       */\r
+  SysTick_IRQn                = -1,     /*!< 15 Cortex-M3 System Tick Interrupt                   */\r
+\r
+/******  AT91SAM3U4 specific Interrupt Numbers *********************************************************/\r
+ IROn_SUPC                = AT91C_ID_SUPC , // SUPPLY CONTROLLER\r
+ IROn_RSTC                = AT91C_ID_RSTC , // RESET CONTROLLER\r
+ IROn_RTC                 = AT91C_ID_RTC  , // REAL TIME CLOCK\r
+ IROn_RTT                 = AT91C_ID_RTT  , // REAL TIME TIMER\r
+ IROn_WDG                 = AT91C_ID_WDG  , // WATCHDOG TIMER\r
+ IROn_PMC                 = AT91C_ID_PMC  , // PMC\r
+ IROn_EFC0                = AT91C_ID_EFC0 , // EFC0\r
+ IROn_EFC1                = AT91C_ID_EFC1 , // EFC1\r
+ IROn_DBGU                = AT91C_ID_DBGU , // DBGU\r
+ IROn_HSMC4               = AT91C_ID_HSMC4, // HSMC4\r
+ IROn_PIOA                = AT91C_ID_PIOA , // Parallel IO Controller A\r
+ IROn_PIOB                = AT91C_ID_PIOB , // Parallel IO Controller B\r
+ IROn_PIOC                = AT91C_ID_PIOC , // Parallel IO Controller C\r
+ IROn_US0                 = AT91C_ID_US0  , // USART 0\r
+ IROn_US1                 = AT91C_ID_US1  , // USART 1\r
+ IROn_US2                 = AT91C_ID_US2  , // USART 2\r
+ IROn_US3                 = AT91C_ID_US3  , // USART 3\r
+ IROn_MCI0                = AT91C_ID_MCI0 , // Multimedia Card Interface\r
+ IROn_TWI0                = AT91C_ID_TWI0 , // TWI 0\r
+ IROn_TWI1                = AT91C_ID_TWI1 , // TWI 1\r
+ IROn_SPI0                = AT91C_ID_SPI0 , // Serial Peripheral Interface\r
+ IROn_SSC0                = AT91C_ID_SSC0 , // Serial Synchronous Controller 0\r
+ IROn_TC0                 = AT91C_ID_TC0  , // Timer Counter 0\r
+ IROn_TC1                 = AT91C_ID_TC1  , // Timer Counter 1\r
+ IROn_TC2                 = AT91C_ID_TC2  , // Timer Counter 2\r
+ IROn_PWMC                = AT91C_ID_PWMC , // Pulse Width Modulation Controller\r
+ IROn_ADCC0               = AT91C_ID_ADCC0, // ADC controller0\r
+ IROn_ADCC1               = AT91C_ID_ADCC1, // ADC controller1\r
+ IROn_HDMA                = AT91C_ID_HDMA , // HDMA\r
+ IROn_UDPHS               = AT91C_ID_UDPHS // USB Device High Speed\r
+} IRQn_Type;  \r
+\r
+/// Dummy define SDRAM bus width \r
+#define BOARD_SDRAM_BUSWIDTH    32\r
+\r
+//------------------------------------------------------------------------------\r
+\r
+\r
+#define PIN_EBI_NANDOE          {1 << 17, AT91C_BASE_PIOB, AT91C_ID_PIOB, PIO_PERIPH_A, PIO_PULLUP}\r
+#define PIN_EBI_NANDWE          {1 << 18, AT91C_BASE_PIOB, AT91C_ID_PIOB, PIO_PERIPH_A, PIO_PULLUP}\r
+#define PIN_EBI_NANDCLE         {1 << 22, AT91C_BASE_PIOB, AT91C_ID_PIOB, PIO_PERIPH_A, PIO_PULLUP}\r
+#define PIN_EBI_NANDALE         {1 << 21, AT91C_BASE_PIOB, AT91C_ID_PIOB, PIO_PERIPH_A, PIO_PULLUP}\r
+\r
+#ifdef CHIP_NAND_CTRL\r
+/// Nandflash chip enable pin definition.\r
+#define BOARD_NF_CE_PIN         {1 << 12, AT91C_BASE_PIOC, AT91C_ID_PIOC, PIO_PERIPH_A, PIO_PULLUP}\r
+/// Nandflash ready/busy pin definition.\r
+#define BOARD_NF_RB_PIN         {1 << 24, AT91C_BASE_PIOB, AT91C_ID_PIOB, PIO_PERIPH_A, PIO_PULLUP}\r
+\r
+/// Nandflash controller peripheral pins definition.\r
+#define PINS_NANDFLASH          BOARD_NF_CE_PIN, BOARD_NF_RB_PIN, PIN_EBI_NANDOE, PIN_EBI_NANDWE,\\r
+                                PIN_EBI_NANDCLE, PIN_EBI_NANDALE, PIN_EBI_DATA_BUS\r
+                                \r
+/// Address for transferring command bytes to the nandflash.\r
+#define BOARD_NF_COMMAND_ADDR   0x60000000\r
+/// Address for transferring address bytes to the nandflash.\r
+#define BOARD_NF_ADDRESS_ADDR   0x61200000\r
+/// Address for transferring data bytes to the nandflash.\r
+#define BOARD_NF_DATA_ADDR      0x61000000\r
+\r
+#else\r
+/// Nandflash controller peripheral pins definition.\r
+#define PINS_NANDFLASH          BOARD_NF_CE_PIN, BOARD_NF_RB_PIN, PIN_EBI_NANDOE, PIN_EBI_NANDWE,\\r
+                                PIN_EBI_NANDCLE, PIN_EBI_NANDALE\r
+/// Nandflash chip enable pin definition.\r
+#define BOARD_NF_CE_PIN         {1 << 12, AT91C_BASE_PIOC, AT91C_ID_PIOC, PIO_OUTPUT_1, PIO_DEFAULT}\r
+/// Nandflash ready/busy pin definition.\r
+#define BOARD_NF_RB_PIN         {1 << 24, AT91C_BASE_PIOB, AT91C_ID_PIOB, PIO_INPUT, PIO_PULLUP}\r
+/// Address for transferring command bytes to the nandflash.\r
+#define BOARD_NF_COMMAND_ADDR   0x61400000\r
+/// Address for transferring address bytes to the nandflash.\r
+#define BOARD_NF_ADDRESS_ADDR   0x61200000\r
+/// Address for transferring data bytes to the nandflash.\r
+#define BOARD_NF_DATA_ADDR      0x61000000\r
+\r
+#endif\r
+\r
+#endif //#ifndef BOARD_H\r
+\r

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/system/board_cstartup_iar.c b/Demo/CORTEX_AT91SAM3U256_IAR/system/board_cstartup_iar.c
new file mode 100644 (file)
index 0000000..ebe7650
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/system/board_cstartup_iar.c
@@ -0,0 +1,140 @@
+/* ----------------------------------------------------------------------------\r
+ *         ATMEL Microcontroller Software Support\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+//------------------------------------------------------------------------------\r
+//         Headers\r
+//------------------------------------------------------------------------------\r
+#include "board.h"\r
+#include "exceptions.h"\r
+#include "board_lowlevel.h"\r
+\r
+//------------------------------------------------------------------------------\r
+//         Types\r
+//------------------------------------------------------------------------------\r
+typedef union { IntFunc __fun; void * __ptr; } IntVector;\r
+\r
+//------------------------------------------------------------------------------\r
+//         ProtoTypes\r
+//------------------------------------------------------------------------------\r
+\r
+extern void __iar_program_start( void );\r
+extern void xPortPendSVHandler(void);\r
+extern void xPortSysTickHandler(void);\r
+extern void vPortSVCHandler(void);\r
+extern void vSerialISR( void );\r
+\r
+int __low_level_init( void );\r
+\r
+//------------------------------------------------------------------------------\r
+//         Variables\r
+//------------------------------------------------------------------------------\r
+extern unsigned int __ICFEDIT_vector_start__;\r
+\r
+//------------------------------------------------------------------------------\r
+//         Exception Table\r
+//------------------------------------------------------------------------------\r
+\r
+#pragma language=extended\r
+#pragma segment="CSTACK"\r
+\r
+// The name "__vector_table" has special meaning for C-SPY:\r
+// it is where the SP start value is found, and the NVIC vector\r
+// table register (VTOR) is initialized to this address if != 0.\r
+\r
+#pragma section = ".vectors"\r
+#pragma location = ".vectors"\r
+const IntVector __vector_table[] =\r
+{\r
+    { .__ptr = __sfe( "CSTACK" ) },\r
+    __iar_program_start,\r
+\r
+    NMI_Handler,\r
+    HardFault_Handler,\r
+    MemManage_Handler,\r
+    BusFault_Handler,\r
+    UsageFault_Handler,\r
+    0, 0, 0, 0,             // Reserved\r
+    vPortSVCHandler,        // SVCall handler\r
+    DebugMon_Handler,\r
+    0,                      // Reserved\r
+    xPortPendSVHandler,     // The PendSV handler\r
+    xPortSysTickHandler,    // The SysTick handler\r
+\r
+    // Configurable interrupts\r
+    SUPC_IrqHandler,    // 0  SUPPLY CONTROLLER\r
+    RSTC_IrqHandler,    // 1  RESET CONTROLLER\r
+    RTC_IrqHandler,     // 2  REAL TIME CLOCK\r
+    RTT_IrqHandler,     // 3  REAL TIME TIMER\r
+    WDT_IrqHandler,     // 4  WATCHDOG TIMER\r
+    PMC_IrqHandler,     // 5  PMC\r
+    EFC0_IrqHandler,    // 6  EFC0\r
+    EFC1_IrqHandler,    // 7  EFC1\r
+    DBGU_IrqHandler,    // 8  DBGU\r
+    HSMC4_IrqHandler,   // 9  HSMC4\r
+    PIOA_IrqHandler,    // 10 Parallel IO Controller A\r
+    PIOB_IrqHandler,    // 11 Parallel IO Controller B\r
+    PIOC_IrqHandler,    // 12 Parallel IO Controller C\r
+    USART0_IrqHandler,  // 13 USART 0\r
+    vSerialISR,                // 14 USART 1\r
+    USART2_IrqHandler,  // 15 USART 2\r
+    USART3_IrqHandler,  // 16 USART 3\r
+    MCI0_IrqHandler,    // 17 Multimedia Card Interface\r
+    TWI0_IrqHandler,    // 18 TWI 0\r
+    TWI1_IrqHandler,    // 19 TWI 1\r
+    SPI0_IrqHandler,    // 20 Serial Peripheral Interface\r
+    SSC0_IrqHandler,    // 21 Serial Synchronous Controller 0\r
+    TC0_IrqHandler,     // 22 Timer Counter 0\r
+    TC1_IrqHandler,     // 23 Timer Counter 1\r
+    TC2_IrqHandler,     // 24 Timer Counter 2\r
+    PWM_IrqHandler,     // 25 Pulse Width Modulation Controller\r
+    ADCC0_IrqHandler,   // 26 ADC controller0\r
+    ADCC1_IrqHandler,   // 27 ADC controller1\r
+    HDMA_IrqHandler,    // 28 HDMA\r
+    UDPD_IrqHandler,   // 29 USB Device High Speed UDP_HS\r
+    IrqHandlerNotUsed   // 30 not used\r
+};\r
+\r
+//------------------------------------------------------------------------------\r
+//         Exported functions\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+/// This is the code that gets called on processor reset. To initialize the\r
+/// device.\r
+//------------------------------------------------------------------------------\r
+int __low_level_init( void )\r
+{\r
+    unsigned int * src = __section_begin(".vectors");\r
+\r
+    LowLevelInit();\r
+\r
+    AT91C_BASE_NVIC->NVIC_VTOFFR = ((unsigned int)(src)) | (0x0 << 7);\r
+\r
+    return 1; // if return 0, the data sections will not be initialized.\r
+}\r

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/system/board_lowlevel.c b/Demo/CORTEX_AT91SAM3U256_IAR/system/board_lowlevel.c
new file mode 100644 (file)
index 0000000..fd4adf7
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/system/board_lowlevel.c
@@ -0,0 +1,209 @@
+/* ----------------------------------------------------------------------------\r
+ *         ATMEL Microcontroller Software Support\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+//------------------------------------------------------------------------------\r
+/// \unit\r
+///\r
+/// !Purpose\r
+///\r
+/// Provides the low-level initialization function that gets called on chip\r
+/// startup.\r
+///\r
+/// !Usage\r
+///\r
+/// LowLevelInit() is called in #board_cstartup_xxx.c#.\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+//         Headers\r
+//------------------------------------------------------------------------------\r
+\r
+#include "board.h"\r
+#include "board_memories.h"\r
+#include "board_lowlevel.h"\r
+#include <pio/pio.h>\r
+\r
+//------------------------------------------------------------------------------\r
+//         Local definitions\r
+//------------------------------------------------------------------------------\r
+// Settings at 48/48MHz\r
+#define AT91C_CKGR_MUL_SHIFT         16\r
+#define AT91C_CKGR_OUT_SHIFT         14\r
+#define AT91C_CKGR_PLLCOUNT_SHIFT     8\r
+#define AT91C_CKGR_DIV_SHIFT          0\r
+\r
+#define BOARD_OSCOUNT         (AT91C_CKGR_MOSCXTST & (0x3F << 8))\r
+#define BOARD_PLLR ((1 << 29) | (0x7 << AT91C_CKGR_MUL_SHIFT) \\r
+        | (0x0 << AT91C_CKGR_OUT_SHIFT) |(0x3f << AT91C_CKGR_PLLCOUNT_SHIFT) \\r
+        | (0x1 << AT91C_CKGR_DIV_SHIFT))\r
+#define BOARD_MCKR ( AT91C_PMC_PRES_CLK_2 | AT91C_PMC_CSS_PLLA_CLK)\r
+\r
+// Define clock timeout\r
+#define CLOCK_TIMEOUT           0xFFFFFFFF\r
+\r
+#define AT91C_SUPC_SR_OSCSEL_CRYST 0x80UL\r
+#define AT91C_SUPC_CR_XTALSEL_CRYSTAL_SEL 0x08UL\r
+\r
+void SetDefaultMaster(unsigned char enable);\r
+\r
+//------------------------------------------------------------------------------\r
+//         Local variables\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+//         Local functions\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+//         Exported functions\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+/// After POR, at91sam3u device is running on 4MHz internal RC\r
+/// At the end of the LowLevelInit procedure MCK = 48MHz PLLA = 96 CPU=48MHz\r
+/// Performs the low-level initialization of the chip. This includes EFC, master\r
+/// clock, IRQ & watchdog configuration.\r
+//------------------------------------------------------------------------------\r
+void LowLevelInit(void)\r
+{\r
+    unsigned int timeout = 0;\r
+\r
+    /* Set 2 WS for Embedded Flash Access\r
+     ************************************/\r
+    AT91C_BASE_EFC0->EFC_FMR = AT91C_EFC_FWS_2WS;\r
+    AT91C_BASE_EFC1->EFC_FMR = AT91C_EFC_FWS_2WS;\r
+\r
+    /* Watchdog initialization\r
+     *************************/\r
+    AT91C_BASE_WDTC->WDTC_WDMR = AT91C_WDTC_WDDIS;\r
+\r
+    /* Select external slow clock\r
+     ****************************/\r
+    if ((AT91C_BASE_SUPC->SUPC_SR & AT91C_SUPC_SR_OSCSEL_CRYST) != AT91C_SUPC_SR_OSCSEL_CRYST) {\r
+        AT91C_BASE_SUPC->SUPC_CR = AT91C_SUPC_CR_XTALSEL_CRYSTAL_SEL | (0xA5UL << 24UL);\r
+        timeout = 0;\r
+        while (!(AT91C_BASE_SUPC->SUPC_SR & AT91C_SUPC_SR_OSCSEL_CRYST) && (timeout++ < CLOCK_TIMEOUT));\r
+    }\r
+\r
+    /* Initialize main oscillator\r
+     ****************************/\r
+    if(!(AT91C_BASE_PMC->PMC_MOR & AT91C_CKGR_MOSCSEL))\r
+    {\r
+        AT91C_BASE_PMC->PMC_MOR = (0x37 << 16) | BOARD_OSCOUNT | AT91C_CKGR_MOSCRCEN | AT91C_CKGR_MOSCXTEN;\r
+        timeout = 0;\r
+        while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MOSCXTS) && (timeout++ < CLOCK_TIMEOUT));\r
+    }\r
+\r
+//    AT91C_BASE_PIOB->PIO_CODR = 1 << 1;\r
+//    AT91C_BASE_PIOB->PIO_OER =  1 << 1;\r
+//    AT91C_BASE_PIOB->PIO_PER =  1 << 1;\r
+\r
+    /* Switch to moscsel */\r
+    AT91C_BASE_PMC->PMC_MOR = (0x37 << 16) | BOARD_OSCOUNT | AT91C_CKGR_MOSCRCEN | AT91C_CKGR_MOSCXTEN | AT91C_CKGR_MOSCSEL;\r
+    timeout = 0;\r
+    while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MOSCSELS) && (timeout++ < CLOCK_TIMEOUT));\r
+    AT91C_BASE_PMC->PMC_MCKR = (AT91C_BASE_PMC->PMC_MCKR & ~AT91C_PMC_CSS) | AT91C_PMC_CSS_MAIN_CLK;\r
+    timeout = 0;\r
+    while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY) && (timeout++ < CLOCK_TIMEOUT));\r
+\r
+    /* Initialize PLLA */\r
+    AT91C_BASE_PMC->PMC_PLLAR = BOARD_PLLR;\r
+    timeout = 0;\r
+    while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_LOCKA) && (timeout++ < CLOCK_TIMEOUT));\r
+\r
+    /* Initialize UTMI for USB usage */\r
+    AT91C_BASE_CKGR->CKGR_UCKR |= (AT91C_CKGR_UPLLCOUNT & (3 << 20)) | AT91C_CKGR_UPLLEN;\r
+    timeout = 0;\r
+    while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_LOCKU) && (timeout++ < CLOCK_TIMEOUT));\r
+\r
+    /* Switch to fast clock\r
+     **********************/\r
+    AT91C_BASE_PMC->PMC_MCKR = (BOARD_MCKR & ~AT91C_PMC_CSS) | AT91C_PMC_CSS_MAIN_CLK;\r
+    timeout = 0;\r
+    while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY) && (timeout++ < CLOCK_TIMEOUT));\r
+\r
+    AT91C_BASE_PMC->PMC_MCKR = BOARD_MCKR;\r
+    timeout = 0;\r
+    while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY) && (timeout++ < CLOCK_TIMEOUT));\r
+\r
+    /* Enable clock for UART\r
+     ************************/\r
+    AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_DBGU);\r
+\r
+    /* Optimize CPU setting for speed */\r
+    SetDefaultMaster(1);\r
+\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Enable or disable default master access\r
+/// \param enalbe 1 enable defaultMaster settings, 0 disable it.\r
+//------------------------------------------------------------------------------\r
+void SetDefaultMaster(unsigned char enable)\r
+{\r
+    AT91PS_HMATRIX2 pMatrix = AT91C_BASE_MATRIX;\r
+\r
+    // Set default master\r
+    if (enable == 1) {\r
+\r
+        // Set default master: SRAM0 -> Cortex-M3 System\r
+        pMatrix->HMATRIX2_SCFG0 |= AT91C_MATRIX_FIXED_DEFMSTR_SCFG0_ARMS |\r
+                                   AT91C_MATRIX_DEFMSTR_TYPE_FIXED_DEFMSTR;\r
+\r
+        // Set default master: SRAM1 -> Cortex-M3 System\r
+        pMatrix->HMATRIX2_SCFG1 |= AT91C_MATRIX_FIXED_DEFMSTR_SCFG1_ARMS |\r
+                                   AT91C_MATRIX_DEFMSTR_TYPE_FIXED_DEFMSTR;\r
+\r
+        // Set default master: Internal flash0 -> Cortex-M3 Instruction/Data\r
+        pMatrix->HMATRIX2_SCFG3 |= AT91C_MATRIX_FIXED_DEFMSTR_SCFG3_ARMC |\r
+                                   AT91C_MATRIX_DEFMSTR_TYPE_FIXED_DEFMSTR;\r
+    } else {\r
+\r
+        // Clear default master: SRAM0 -> Cortex-M3 System\r
+        pMatrix->HMATRIX2_SCFG0 &= (~AT91C_MATRIX_DEFMSTR_TYPE);\r
+\r
+        // Clear default master: SRAM1 -> Cortex-M3 System\r
+        pMatrix->HMATRIX2_SCFG1 &= (~AT91C_MATRIX_DEFMSTR_TYPE);\r
+\r
+        // Clear default master: Internal flash0 -> Cortex-M3 Instruction/Data\r
+        pMatrix->HMATRIX2_SCFG3 &= (~AT91C_MATRIX_DEFMSTR_TYPE);\r
+    }\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Set flash wait state\r
+/// \param ws    Value of flash wait state\r
+//------------------------------------------------------------------------------\r
+void SetFlashWaitState(unsigned char ws)\r
+{\r
+    // Set Wait State for Embedded Flash Access\r
+       AT91C_BASE_EFC0->EFC_FMR = ((ws << 8) & AT91C_EFC_FWS);\r
+       AT91C_BASE_EFC1->EFC_FMR = ((ws << 8) & AT91C_EFC_FWS);\r
+}\r
+\r

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/system/board_lowlevel.h b/Demo/CORTEX_AT91SAM3U256_IAR/system/board_lowlevel.h
new file mode 100644 (file)
index 0000000..665449b
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/system/board_lowlevel.h
@@ -0,0 +1,49 @@
+/* ----------------------------------------------------------------------------\r
+ *         ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+//------------------------------------------------------------------------------\r
+/// \unit\r
+///\r
+/// !!!Purpose\r
+/// \r
+/// Collection of methods for lowlevel.\r
+/// \r
+//------------------------------------------------------------------------------\r
+\r
+#ifndef BOARD_LOWLEVEL_H\r
+#define BOARD_LOWLEVEL_H\r
+\r
+//------------------------------------------------------------------------------\r
+//         Exported functions\r
+//------------------------------------------------------------------------------\r
+extern void LowLevelInit(void);\r
+extern void OptimizeCpuSpeed(void);\r
+\r
+#endif // BOARD_LOWLEVEL_H\r
+\r

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/system/board_memories.c b/Demo/CORTEX_AT91SAM3U256_IAR/system/board_memories.c
new file mode 100644 (file)
index 0000000..e029a99
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/system/board_memories.c
@@ -0,0 +1,101 @@
+/* ----------------------------------------------------------------------------\r
+ *         ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2009, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/*\r
+    Title: Memories implementation\r
+*/\r
+\r
+//------------------------------------------------------------------------------\r
+//         Headers\r
+//------------------------------------------------------------------------------\r
+\r
+#include <board.h>\r
+\r
+//------------------------------------------------------------------------------\r
+//         Exported functions\r
+//------------------------------------------------------------------------------\r
+//------------------------------------------------------------------------------\r
+/// Dummy function to initialize and configure the SDRAM\r
+//------------------------------------------------------------------------------\r
+void BOARD_ConfigureSdram(unsigned char busWidth)\r
+{\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Configures the EBI for NandFlash access. Pins must be configured after or\r
+/// before calling this function.\r
+//------------------------------------------------------------------------------\r
+void BOARD_ConfigureNandFlash(unsigned char busWidth)\r
+{\r
+    AT91PS_HSMC4 pHSMC4 = AT91C_BASE_HSMC4;    \r
+    AT91PS_HSMC4_CS pSMC = AT91C_BASE_HSMC4_CS1;\r
+\r
+    // Open EBI clock\r
+    AT91C_BASE_PMC->PMC_PCER = (1<< AT91C_ID_HSMC4);\r
+ \r
+#ifdef CHIP_NAND_CTRL    \r
+    // Enable the Nand Flash Controller\r
+    pHSMC4 ->HSMC4_CTRL = AT91C_HSMC4_NFCEN;\r
+#endif\r
+    \r
+    pSMC->HSMC4_SETUP = 0\r
+                    | ((0 <<  0) & AT91C_HSMC4_NWE_SETUP)\r
+                    | ((1 <<  8) & AT91C_HSMC4_NCS_WR_SETUP)\r
+                    | ((0 << 16) & AT91C_HSMC4_NRD_SETUP)\r
+                    | ((1 << 24) & AT91C_HSMC4_NCS_RD_SETUP);\r
+\r
+    pSMC->HSMC4_PULSE = 0\r
+                    | ((2 <<  0) & AT91C_HSMC4_NWE_PULSE)\r
+                    | ((3 <<  8) & AT91C_HSMC4_NCS_WR_PULSE)\r
+                    | ((3 << 16) & AT91C_HSMC4_NRD_PULSE)\r
+                    | ((4 << 24) & AT91C_HSMC4_NCS_RD_PULSE);\r
+\r
+    pSMC->HSMC4_CYCLE = 0\r
+                  | ((4 <<  0) & AT91C_HSMC4_NWE_CYCLE)\r
+                  | ((7 << 16) & AT91C_HSMC4_NRD_CYCLE);\r
+\r
+    pSMC->HSMC4_TIMINGS = 0\r
+                    | ((1 <<  0) & AT91C_HSMC4_TCLR) // CLE to REN\r
+                    | ((2 <<  4) & AT91C_HSMC4_TADL) // ALE to Data\r
+                    | ((1 <<  8) & AT91C_HSMC4_TAR)  // ALE to REN\r
+                    | ((1 << 16) & AT91C_HSMC4_TRR)  // Ready to REN\r
+                    | ((2 << 24) & AT91C_HSMC4_TWB)  // WEN to REN\r
+                    | (7<<28)\r
+                    |(AT91C_HSMC4_NFSEL)              // Nand Flash Timing\r
+                    ;\r
+    \r
+        \r
+    if (busWidth == 8) {\r
+        pSMC->HSMC4_MODE = AT91C_HSMC4_DBW_WIDTH_EIGTH_BITS | AT91C_HSMC4_READ_MODE | AT91C_HSMC4_WRITE_MODE;\r
+    }\r
+    else if (busWidth == 16) {\r
+        pSMC->HSMC4_MODE = AT91C_HSMC4_DBW_WIDTH_SIXTEEN_BITS | AT91C_HSMC4_READ_MODE | AT91C_HSMC4_WRITE_MODE;\r
+    }\r
+}\r
+\r

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/system/board_memories.h b/Demo/CORTEX_AT91SAM3U256_IAR/system/board_memories.h
new file mode 100644 (file)
index 0000000..7767884
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/system/board_memories.h
@@ -0,0 +1,51 @@
+/* ----------------------------------------------------------------------------\r
+ *         ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+//------------------------------------------------------------------------------\r
+/// \unit\r
+/// !Purpose\r
+/// \r
+///\r
+/// !Usage\r
+/// \r
+//------------------------------------------------------------------------------\r
+\r
+#ifndef BOARD_MEMORIES_H\r
+#define BOARD_MEMORIES_H\r
+\r
+//------------------------------------------------------------------------------\r
+//         Exported functions\r
+//------------------------------------------------------------------------------\r
+\r
+extern void BOARD_ConfigureSdram(unsigned char busWidth);\r
+\r
+extern void BOARD_ConfigureNandFlash(unsigned char busWidth);\r
+\r
+#endif //#ifndef BOARD_MEMORIES_H\r
+\r

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/system/chip.h b/Demo/CORTEX_AT91SAM3U256_IAR/system/chip.h
new file mode 100644 (file)
index 0000000..59f048a
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/system/chip.h
@@ -0,0 +1,99 @@
+/* ----------------------------------------------------------------------------\r
+ *         ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+ \r
+//------------------------------------------------------------------------------\r
+/// \unit\r
+/// !Purpose\r
+///\r
+/// Definition of AT91SAM3U4 characteristics and features\r
+///\r
+/// !Usage\r
+/// -# For ARM core feature, see "AT91SAM3U4 - ARM core features".\r
+/// -# For IP features, see "AT91SAM3U4 - IP features".\r
+/// -# For misc, see "AT91SAM3U4 - Misc".\r
+//------------------------------------------------------------------------------\r
+ \r
+#ifndef CHIP_H \r
+#define CHIP_H\r
+\r
+//------------------------------------------------------------------------------\r
+//         Headers\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+//         Definitions\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+/// \page "AT91SAM3U4 - ARM core features"\r
+/// This page lists several characteristics related to the ARM core\r
+///\r
+\r
+//ARM core features\r
+\r
+/// ARM core definition.\r
+#define cortexm3\r
+\r
+/// family definition.\r
+#define at91sam3u\r
+\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+/// \page "AT91SAM3U4 - IP features"\r
+/// This page lists several characteristics related to the embedded IP\r
+///\r
+\r
+//IP FEATURES\r
+\r
+// EFC GPNVM number\r
+#define CHIP_EFC_NUM_GPNVMS    3\r
+\r
+/// Indicates chip has an Enhanced EFC. \r
+#define CHIP_FLASH_EEFC \r
+\r
+// DMA channels number\r
+#define CHIP_DMA_CHANNEL_NUM   4\r
+\r
+// Indicate chip has a nandflash controller. \r
+#define CHIP_NAND_CTRL\r
+ \r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+/// \page "AT91SAM3U4 - Misc "\r
+/// This page lists misc features\r
+///\r
+\r
+//Misc \r
+\r
+//------------------------------------------------------------------------------\r
+\r
+#endif //#ifndef CHIP_H\r
+\r

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/system/exceptions.c b/Demo/CORTEX_AT91SAM3U256_IAR/system/exceptions.c
new file mode 100644 (file)
index 0000000..9f4c76e
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/system/exceptions.c
@@ -0,0 +1,378 @@
+/* ----------------------------------------------------------------------------\r
+ *         ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/*\r
+** This file contains the default exception handlers\r
+** and exception table.\r
+*/\r
+\r
+//------------------------------------------------------------------------------\r
+//         Headers\r
+//------------------------------------------------------------------------------\r
+\r
+#include "exceptions.h"\r
+\r
+//------------------------------------------------------------------------------\r
+//         Types\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+//         Exception Handlers\r
+//------------------------------------------------------------------------------\r
+\r
+\r
+//------------------------------------------------------------------------------\r
+// Default irq handler\r
+//------------------------------------------------------------------------------\r
+void IrqHandlerNotUsed(void)\r
+{\r
+    while(1);\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+// Provide weak aliases for each Exception handler to the IrqHandlerNotUsed. \r
+// As they are weak aliases, any function with the same name will override \r
+// this definition.\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+// System interrupt\r
+//------------------------------------------------------------------------------\r
+WEAK void NMI_Handler(void)\r
+{   \r
+    while(1);\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+//------------------------------------------------------------------------------\r
+WEAK void HardFault_Handler(void)\r
+{\r
+    while(1);\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+//------------------------------------------------------------------------------\r
+WEAK void MemManage_Handler(void)\r
+{\r
+    while(1);\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+//------------------------------------------------------------------------------\r
+WEAK void BusFault_Handler(void)\r
+{\r
+    while(1);\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+//------------------------------------------------------------------------------\r
+WEAK void UsageFault_Handler(void)\r
+{\r
+    while(1);\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+//------------------------------------------------------------------------------\r
+WEAK void SVC_Handler(void)\r
+{\r
+    while(1);\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+//------------------------------------------------------------------------------\r
+WEAK void DebugMon_Handler(void)\r
+{\r
+    while(1);\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+//------------------------------------------------------------------------------\r
+WEAK void PendSV_Handler(void)\r
+{\r
+    while(1);\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+// for Cortex M3\r
+//------------------------------------------------------------------------------\r
+WEAK void SysTick_Handler(void)\r
+{\r
+    while(1);\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+// External interrupt\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+// for SAM7/9\r
+//------------------------------------------------------------------------------\r
+void SYS_IrqHandler( void )\r
+{\r
+    while(1);\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+// SUPPLY CONTROLLER\r
+//------------------------------------------------------------------------------\r
+WEAK void SUPC_IrqHandler(void)\r
+{\r
+    while(1);\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+// RESET CONTROLLER\r
+//------------------------------------------------------------------------------\r
+WEAK void RSTC_IrqHandler(void)\r
+{\r
+    while(1);\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+// REAL TIME CLOCK\r
+//------------------------------------------------------------------------------\r
+WEAK void RTC_IrqHandler(void)\r
+{\r
+    while(1);\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+// REAL TIME TIMER\r
+//------------------------------------------------------------------------------\r
+WEAK void RTT_IrqHandler(void)\r
+{\r
+    while(1);\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+// WATCHDOG TIMER\r
+//------------------------------------------------------------------------------\r
+WEAK void WDT_IrqHandler(void)\r
+{\r
+    while(1);\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+// PMC\r
+//------------------------------------------------------------------------------\r
+WEAK void PMC_IrqHandler(void)\r
+{\r
+    while(1);\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+// EFC0\r
+//------------------------------------------------------------------------------\r
+WEAK void EFC0_IrqHandler(void)\r
+{\r
+    while(1);\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+// EFC1\r
+//------------------------------------------------------------------------------\r
+WEAK void EFC1_IrqHandler(void)\r
+{\r
+    while(1);\r
+}\r
+//------------------------------------------------------------------------------\r
+// DBGU\r
+//------------------------------------------------------------------------------\r
+WEAK void DBGU_IrqHandler(void)\r
+{\r
+    while(1);\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+// HSMC4\r
+//------------------------------------------------------------------------------\r
+WEAK void HSMC4_IrqHandler(void)\r
+{\r
+    while(1);\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+// Parallel IO Controller A\r
+//------------------------------------------------------------------------------\r
+WEAK void PIOA_IrqHandler(void)\r
+{\r
+    while(1);\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+// Parallel IO Controller B\r
+//------------------------------------------------------------------------------\r
+WEAK void PIOB_IrqHandler(void)\r
+{\r
+    while(1);\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+// Parallel IO Controller C\r
+//------------------------------------------------------------------------------\r
+WEAK void PIOC_IrqHandler(void)\r
+{\r
+    while(1);\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+// USART 0\r
+//------------------------------------------------------------------------------\r
+WEAK void USART0_IrqHandler(void)\r
+{\r
+    while(1);\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+// USART 1\r
+//------------------------------------------------------------------------------\r
+WEAK void USART1_IrqHandler(void)\r
+{\r
+    while(1);\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+// USART 2\r
+//------------------------------------------------------------------------------\r
+WEAK void USART2_IrqHandler(void)\r
+{\r
+    while(1);\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+// USART 3\r
+//------------------------------------------------------------------------------\r
+WEAK void USART3_IrqHandler(void)\r
+{\r
+    while(1);\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+// Multimedia Card Interface\r
+//------------------------------------------------------------------------------\r
+WEAK void MCI0_IrqHandler(void)\r
+{\r
+    while(1);\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+// TWI 0\r
+//------------------------------------------------------------------------------\r
+WEAK void TWI0_IrqHandler(void)\r
+{\r
+    while(1);\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+// TWI 1\r
+//------------------------------------------------------------------------------\r
+WEAK void TWI1_IrqHandler(void)\r
+{\r
+    while(1);\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+// Serial Peripheral Interface 0\r
+//------------------------------------------------------------------------------\r
+WEAK void SPI0_IrqHandler(void)\r
+{\r
+    while(1);\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+// Serial Synchronous Controller 0\r
+//------------------------------------------------------------------------------\r
+WEAK void SSC0_IrqHandler(void)\r
+{\r
+    while(1);\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+// Timer Counter 0\r
+//------------------------------------------------------------------------------\r
+WEAK void TC0_IrqHandler(void)\r
+{\r
+    while(1);\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+// Timer Counter 1\r
+//------------------------------------------------------------------------------\r
+WEAK void TC1_IrqHandler(void)\r
+{\r
+    while(1);\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+// Timer Counter 2\r
+//------------------------------------------------------------------------------\r
+WEAK void TC2_IrqHandler(void)\r
+{\r
+    while(1);\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+// PWM Controller\r
+//------------------------------------------------------------------------------\r
+WEAK void PWM_IrqHandler(void)\r
+{\r
+    while(1);\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+// ADC controller0\r
+//------------------------------------------------------------------------------\r
+WEAK void ADCC0_IrqHandler(void)\r
+{\r
+    while(1);\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+// ADC controller1\r
+//------------------------------------------------------------------------------\r
+WEAK void ADCC1_IrqHandler(void)\r
+{\r
+    while(1);\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+// HDMA\r
+//------------------------------------------------------------------------------\r
+WEAK void HDMA_IrqHandler(void)\r
+{\r
+    while(1);\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+// USB Device High Speed UDP_HS\r
+//------------------------------------------------------------------------------\r
+WEAK void UDPD_IrqHandler(void)\r
+{\r
+    while(1);\r
+}\r

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/system/exceptions.h b/Demo/CORTEX_AT91SAM3U256_IAR/system/exceptions.h
new file mode 100644 (file)
index 0000000..3e16df0
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/system/exceptions.h
@@ -0,0 +1,135 @@
+/* ----------------------------------------------------------------------------\r
+ *         ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/*\r
+** This file contains the default exception handlers\r
+** and exception table.\r
+*/\r
+\r
+//------------------------------------------------------------------------------\r
+//         Types\r
+//------------------------------------------------------------------------------\r
+\r
+/// Function prototype for exception table items - interrupt handler.\r
+//typedef void( *IrqHandler )( void );\r
+typedef void( *IntFunc )( void );\r
+\r
+/// Weak attribute\r
+\r
+#if defined   ( __CC_ARM   )\r
+    #define WEAK __attribute__ ((weak))\r
+#elif defined ( __ICCARM__ )\r
+    #define WEAK __weak\r
+#elif defined (  __GNUC__  )\r
+    #define WEAK __attribute__ ((weak))\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+//         Global functions\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+//         Exception Handlers\r
+//------------------------------------------------------------------------------\r
+\r
+extern WEAK void NMI_Handler( void );\r
+extern WEAK void HardFault_Handler( void );\r
+extern WEAK void MemManage_Handler( void );\r
+extern WEAK void BusFault_Handler( void );\r
+extern WEAK void UsageFault_Handler( void );\r
+extern WEAK void SVC_Handler( void );\r
+extern WEAK void DebugMon_Handler( void );\r
+extern WEAK void PendSV_Handler( void );\r
+extern WEAK void SysTick_Handler( void );\r
+void IrqHandlerNotUsed(void);\r
+\r
+\r
+// System Controller\r
+extern void SYS_IrqHandler(void);\r
+// SUPPLY CONTROLLER\r
+extern WEAK void SUPC_IrqHandler(void);\r
+// RESET CONTROLLER\r
+extern WEAK void RSTC_IrqHandler(void);\r
+// REAL TIME CLOCK\r
+extern WEAK void RTC_IrqHandler(void);\r
+// REAL TIME TIMER\r
+extern WEAK void RTT_IrqHandler(void);\r
+// WATCHDOG TIMER\r
+extern WEAK void WDT_IrqHandler(void);\r
+// PMC\r
+extern WEAK void PMC_IrqHandler(void);\r
+// EFC0\r
+extern WEAK void EFC0_IrqHandler(void);\r
+// EFC1\r
+extern WEAK void EFC1_IrqHandler(void);\r
+// DBGU\r
+extern WEAK void DBGU_IrqHandler(void);\r
+// HSMC4\r
+extern WEAK void HSMC4_IrqHandler(void);\r
+// Parallel IO Controller A\r
+extern WEAK void PIOA_IrqHandler(void);\r
+// Parallel IO Controller B\r
+extern WEAK void PIOB_IrqHandler(void);\r
+// Parallel IO Controller C\r
+extern WEAK void PIOC_IrqHandler(void);\r
+// USART 0\r
+extern WEAK void USART0_IrqHandler(void);\r
+// USART 1\r
+extern WEAK void USART1_IrqHandler(void);\r
+// USART 2\r
+extern WEAK void USART2_IrqHandler(void);\r
+// USART 3\r
+extern WEAK void USART3_IrqHandler(void);\r
+// Multimedia Card Interface\r
+extern WEAK void MCI0_IrqHandler(void);\r
+// TWI 0\r
+extern WEAK void TWI0_IrqHandler(void);\r
+// TWI 1\r
+extern WEAK void TWI1_IrqHandler(void);\r
+// Serial Peripheral Interface 0\r
+extern WEAK void SPI0_IrqHandler(void);\r
+// Serial Synchronous Controller 0\r
+extern WEAK void SSC0_IrqHandler(void);\r
+// Timer Counter 0\r
+extern WEAK void TC0_IrqHandler(void);\r
+// Timer Counter 1\r
+extern WEAK void TC1_IrqHandler(void);\r
+// Timer Counter 2\r
+extern WEAK void TC2_IrqHandler(void);\r
+// PWM Controller\r
+extern WEAK void PWM_IrqHandler(void);\r
+// ADC controller0\r
+extern WEAK void ADCC0_IrqHandler(void);\r
+// ADC controller1\r
+extern WEAK void ADCC1_IrqHandler(void);\r
+// HDMA\r
+extern WEAK void HDMA_IrqHandler(void);\r
+// USB Device High Speed UDP_HS\r
+extern WEAK void UDPD_IrqHandler(void);\r
+\r

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/system/flash.icf b/Demo/CORTEX_AT91SAM3U256_IAR/system/flash.icf
new file mode 100644 (file)
index 0000000..a7b3a93
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/system/flash.icf
@@ -0,0 +1,47 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/\r
+/*-Editor annotation file-*/\r
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */\r
+/*-Vector table start*/\r
+define symbol __ICFEDIT_vector_start__ = 0x00080000; /*Add for CMSIS*/\r
+/*-Memory Regions-*/\r
+define symbol __ICFEDIT_region_RAM0_start__  = 0x20000000;\r
+define symbol __ICFEDIT_region_RAM0_end__    = 0x20007FFF;\r
+define symbol __ICFEDIT_region_RAM1_start__  = 0x20080000;\r
+define symbol __ICFEDIT_region_RAM1_end__    = 0x20083FFF;\r
+define symbol __ICFEDIT_region_ROM0_start__  = 0x00080000;\r
+define symbol __ICFEDIT_region_ROM0_end__    = 0x0009FFFF;\r
+define symbol __ICFEDIT_region_ROM1_start__  = 0x00100000;\r
+define symbol __ICFEDIT_region_ROM1_end__    = 0x0011FFFF;\r
+/*-Sizes-*/\r
+define symbol __ICFEDIT_size_cstack__        = 0x800;\r
+define symbol __ICFEDIT_size_heap__          = 0x200;\r
+/*-Specials-*/\r
+/*define symbol __ICFEDIT_region_RAM_VECT_start__ = __ICFEDIT_region_RAM0_start__;*/ /*Referenced for CMSIS*/\r
+/*define symbol __ICFEDIT_size_vectors__          = 0x100;*/ /*Referenced for CMSIS*/\r
+/*-Exports-*/\r
+/*export symbol __ICFEDIT_region_RAM_VECT_start__;*/\r
+export symbol __ICFEDIT_vector_start__; /*Add for CMSIS*/\r
+/**** End of ICF editor section. ###ICF###*/\r
+\r
+define memory mem with size   = 4G;\r
+/*define region RAM_VECT_region = mem:[from __ICFEDIT_region_RAM_VECT_start__ size __ICFEDIT_size_vectors__];*/ /*Referenced for CMSIS*/\r
+/*define region RAM0_region     = mem:[from __ICFEDIT_region_RAM0_start__+__ICFEDIT_size_vectors__ to __ICFEDIT_region_RAM0_end__];*/ /*Referenced for CMSIS*/\r
+define region RAM0_region     = mem:[from __ICFEDIT_region_RAM0_start__ to __ICFEDIT_region_RAM0_end__];\r
+define region RAM1_region     = mem:[from __ICFEDIT_region_RAM1_start__ to __ICFEDIT_region_RAM1_end__];\r
+/*define region RAM_region      = mem:[from __ICFEDIT_region_RAM0_start__+__ICFEDIT_size_vectors__ to __ICFEDIT_region_RAM0_end__] |\r
+                                mem:[from __ICFEDIT_region_RAM1_start__ to __ICFEDIT_region_RAM1_end__];*/ /*Referenced for CMSIS*/\r
+define region ROM0_region     = mem:[from __ICFEDIT_region_ROM0_start__ to __ICFEDIT_region_ROM0_end__];\r
+define region ROM1_region     = mem:[from __ICFEDIT_region_ROM1_start__ to __ICFEDIT_region_ROM1_end__];\r
+\r
+/*define block RamVect   with alignment = 8, size = __ICFEDIT_size_vectors__  { };*/\r
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };\r
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };\r
+\r
+initialize by copy { readwrite };\r
+do not initialize  { section .noinit };\r
+\r
+/*place at start of ROM0_region { readonly section .vectors };*/ /*Referenced for CMSIS*/\r
+place at address mem:__ICFEDIT_vector_start__ { readonly section .vectors }; /*Add for CMSIS*/\r
+place in ROM0_region          { readonly };\r
+place in RAM0_region          { readwrite, block CSTACK, block HEAP };\r
+/*place in RAM_VECT_region      { block RamVect };*/ /*Referenced for CMSIS*/
\ No newline at end of file

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/system/led.c b/Demo/CORTEX_AT91SAM3U256_IAR/system/led.c
new file mode 100644 (file)
index 0000000..7048b2a
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/system/led.c
@@ -0,0 +1,162 @@
+/* ----------------------------------------------------------------------------\r
+ *         ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+//------------------------------------------------------------------------------\r
+//         Headers\r
+//------------------------------------------------------------------------------\r
+\r
+#include "led.h"\r
+#include <board.h>\r
+#include <pio/pio.h>\r
+\r
+//------------------------------------------------------------------------------\r
+//         Local Variables\r
+//------------------------------------------------------------------------------\r
+\r
+#ifdef PINS_LEDS\r
+static const Pin pinsLeds[] = {PINS_LEDS};\r
+static const unsigned int numLeds = PIO_LISTSIZE(pinsLeds);\r
+#endif\r
+\r
+//------------------------------------------------------------------------------\r
+//         Global Functions\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+/// Configures the pin associated with the given LED number. If the LED does\r
+/// not exist on the board, the function does nothing.\r
+/// \param led  Number of the LED to configure.\r
+/// \return 1 if the LED exists and has been configured; otherwise 0.\r
+//------------------------------------------------------------------------------\r
+unsigned char LED_Configure(unsigned int led)\r
+{\r
+#ifdef PINS_LEDS\r
+    // Check that LED exists\r
+    if (led >= numLeds) {\r
+\r
+        return 0;\r
+    }\r
+\r
+    // Configure LED\r
+    return (PIO_Configure(&pinsLeds[led], 1));\r
+#else\r
+    return 0;\r
+#endif\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Turns the given LED on if it exists; otherwise does nothing.\r
+/// \param led  Number of the LED to turn on.\r
+/// \return 1 if the LED has been turned on; 0 otherwise.\r
+//------------------------------------------------------------------------------\r
+unsigned char LED_Set(unsigned int led)\r
+{\r
+#ifdef PINS_LEDS\r
+    // Check if LED exists\r
+    if (led >= numLeds) {\r
+\r
+        return 0;\r
+    }\r
+\r
+    // Turn LED on\r
+    if (pinsLeds[led].type == PIO_OUTPUT_0) {\r
+\r
+        PIO_Set(&pinsLeds[led]);\r
+    }\r
+    else {\r
+\r
+        PIO_Clear(&pinsLeds[led]);\r
+    }\r
+\r
+    return 1;\r
+#else\r
+    return 0;\r
+#endif\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Turns a LED off.\r
+/// \param led  Number of the LED to turn off.\r
+/// \param 1 if the LED has been turned off; 0 otherwise.\r
+//------------------------------------------------------------------------------\r
+unsigned char LED_Clear(unsigned int led)\r
+{\r
+#ifdef PINS_LEDS\r
+    // Check if LED exists\r
+    if (led >= numLeds) {\r
+\r
+        return 0;\r
+    }\r
+\r
+    // Turn LED off\r
+    if (pinsLeds[led].type == PIO_OUTPUT_0) {\r
+\r
+        PIO_Clear(&pinsLeds[led]);\r
+    }\r
+    else {\r
+\r
+        PIO_Set(&pinsLeds[led]);\r
+    }\r
+\r
+    return 1;\r
+#else\r
+    return 0;\r
+#endif\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+/// Toggles the current state of a LED.\r
+/// \param led  Number of the LED to toggle.\r
+/// \return 1 if the LED has been toggled; otherwise 0.\r
+//------------------------------------------------------------------------------\r
+unsigned char LED_Toggle(unsigned int led)\r
+{\r
+#ifdef PINS_LEDS\r
+    // Check if LED exists\r
+    if (led >= numLeds) {\r
+\r
+        return 0;\r
+    }\r
+\r
+    // Toggle LED\r
+    if (PIO_GetOutputDataStatus(&pinsLeds[led])) {\r
+\r
+        PIO_Clear(&pinsLeds[led]);\r
+    }\r
+    else {\r
+\r
+        PIO_Set(&pinsLeds[led]);\r
+    }\r
+\r
+    return 1;\r
+#else\r
+    return 0;\r
+#endif\r
+}\r
+\r

diff --git a/Demo/CORTEX_AT91SAM3U256_IAR/system/led.h b/Demo/CORTEX_AT91SAM3U256_IAR/system/led.h
new file mode 100644 (file)
index 0000000..3f4878f
--- /dev/null
+++ b/Demo/CORTEX_AT91SAM3U256_IAR/system/led.h
@@ -0,0 +1,70 @@
+/* ----------------------------------------------------------------------------\r
+ *         ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+//------------------------------------------------------------------------------\r
+/// \unit\r
+///\r
+/// !Purpose\r
+///\r
+/// Small set of functions for simple and portable LED usage.\r
+///\r
+/// !Usage\r
+///\r
+/// -# Configure one or more LEDs using LED_Configure and\r
+///    LED_ConfigureAll.\r
+/// -# Set, clear and toggle LEDs using LED_Set, LED_Clear and\r
+///    LED_Toggle.\r
+///\r
+/// LEDs are numbered starting from 0; the number of LEDs depend on the\r
+/// board being used. All the functions defined here will compile properly\r
+/// regardless of whether the LED is defined or not; they will simply\r
+/// return 0 when a LED which does not exist is given as an argument.\r
+/// Also, these functions take into account how each LED is connected on to\r
+/// board; thus, <LED_Set> might change the level on the corresponding pin\r
+/// to 0 or 1, but it will always light the LED on; same thing for the other\r
+/// methods.\r
+//------------------------------------------------------------------------------\r
+\r
+#ifndef LED_H\r
+#define LED_H\r
+\r
+//------------------------------------------------------------------------------\r
+//         Global Functions\r
+//------------------------------------------------------------------------------\r
+\r
+extern unsigned char LED_Configure(unsigned int led);\r
+\r
+extern unsigned char LED_Set(unsigned int led);\r
+\r
+extern unsigned char LED_Clear(unsigned int led);\r
+\r
+extern unsigned char LED_Toggle(unsigned int led);\r
+\r
+#endif //#ifndef LED_H\r
+\r