]> git.sur5r.net Git - freertos/commitdiff
Test the CCS4 demo project to CCS5 and make a minor change to ensure the power suppli...
authorrichardbarry <richardbarry@1d2547de-c912-0410-9cb9-b8ca96c0e9e2>
Mon, 2 Apr 2012 09:20:45 +0000 (09:20 +0000)
committerrichardbarry <richardbarry@1d2547de-c912-0410-9cb9-b8ca96c0e9e2>
Mon, 2 Apr 2012 09:20:45 +0000 (09:20 +0000)
git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@1708 1d2547de-c912-0410-9cb9-b8ca96c0e9e2

12 files changed:
Demo/MSP430X_MSP430F5438_CCS4/.ccsproject
Demo/MSP430X_MSP430F5438_CCS4/.cproject [new file with mode: 0644]
Demo/MSP430X_MSP430F5438_CCS4/.project
Demo/MSP430X_MSP430F5438_CCS4/CreateProjectDirectoryStructure.bat
Demo/MSP430X_MSP430F5438_CCS4/Demo_Source/F5XX_6XX_Core_Lib/HAL_PMM.c [new file with mode: 0644]
Demo/MSP430X_MSP430F5438_CCS4/Demo_Source/F5XX_6XX_Core_Lib/HAL_PMM.h [new file with mode: 0644]
Demo/MSP430X_MSP430F5438_CCS4/Demo_Source/FreeRTOSConfig.h
Demo/MSP430X_MSP430F5438_CCS4/Demo_Source/MSP-EXP430F5438_HAL/hal_MSP-EXP430F5438.h
Demo/MSP430X_MSP430F5438_CCS4/Demo_Source/MSP-EXP430F5438_HAL/hal_board.c
Demo/MSP430X_MSP430F5438_CCS4/Demo_Source/MSP-EXP430F5438_HAL/hal_board.h
Demo/MSP430X_MSP430F5438_CCS4/Demo_Source/main.c
Demo/MSP430X_MSP430F5438_CCS4/READ_ME_FIRST.txt [new file with mode: 0644]

index ac776e6da9deb6bdae3545f32a66905139543fe9..2b2a65d902e9ec94039842ae4aff123cf4fd42b4 100644 (file)
@@ -1,4 +1,4 @@
-<?xml version="1.0" encoding="UTF-8"?>\r
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>\r
 <?ccsproject version="1.0"?>\r
 \r
 <projectOptions>\r
@@ -8,4 +8,5 @@
 <isElfFormat value="false"/>\r
 <linkerCommandFile value="lnk_msp430f5438a.cmd"/>\r
 <rts value="libc.a"/>\r
+<connection value="common/targetdb/connections/TIMSP430-USB.xml"/>\r
 </projectOptions>\r
diff --git a/Demo/MSP430X_MSP430F5438_CCS4/.cproject b/Demo/MSP430X_MSP430F5438_CCS4/.cproject
new file mode 100644 (file)
index 0000000..f694fa4
--- /dev/null
@@ -0,0 +1,678 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>\r
+<?fileVersion 4.0.0?>\r
+\r
+<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">\r
+       <storageModule configRelations="2" moduleId="org.eclipse.cdt.core.settings">\r
+               <cconfiguration id="com.ti.ccstudio.buildDefinitions.MSP430.Debug.1203657382">\r
+                       <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.ti.ccstudio.buildDefinitions.MSP430.Debug.1203657382" moduleId="org.eclipse.cdt.core.settings" name="Debug_Large_Data_Model">\r
+                               <externalSettings/>\r
+                               <extensions>\r
+                                       <extension id="com.ti.ccstudio.binaryparser.CoffParser" point="org.eclipse.cdt.core.BinaryParser"/>\r
+                                       <extension id="com.ti.ccstudio.errorparser.CoffErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>\r
+                                       <extension id="com.ti.ccstudio.errorparser.LinkErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>\r
+                                       <extension id="com.ti.ccstudio.errorparser.AsmErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>\r
+                               </extensions>\r
+                       </storageModule>\r
+                       <storageModule moduleId="cdtBuildSystem" version="4.0.0">\r
+                               <configuration artifactExtension="out" artifactName="RTOSDemo" buildProperties="" description="" id="com.ti.ccstudio.buildDefinitions.MSP430.Debug.1203657382" name="Debug_Large_Data_Model" parent="com.ti.ccstudio.buildDefinitions.MSP430.Debug">\r
+                                       <folderInfo id="com.ti.ccstudio.buildDefinitions.MSP430.Debug.1203657382.2078353183" name="/" resourcePath="">\r
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+                       <content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cSource" language="com.ti.ccstudio.core.TIGCCLanguage"/>\r
+                       <content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cxxHeader" language="com.ti.ccstudio.core.TIGPPLanguage"/>\r
+                       <content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cxxSource" language="com.ti.ccstudio.core.TIGPPLanguage"/>\r
+               </project-mappings>\r
+       </storageModule>\r
+       <storageModule moduleId="refreshScope"/>\r
+       <storageModule moduleId="scannerConfiguration"/>\r
+</cproject>\r
index 5201cfb281ae25b9589afc649b6492bb89c66a68..61d8cf8647cfa368caa9a1536159a550e4141e80 100644 (file)
@@ -7,6 +7,68 @@
        <buildSpec>\r
                <buildCommand>\r
                        <name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>\r
+                       <arguments>\r
+                               <dictionary>\r
+                                       <key>?name?</key>\r
+                                       <value></value>\r
+                               </dictionary>\r
+                               <dictionary>\r
+                                       <key>org.eclipse.cdt.make.core.append_environment</key>\r
+                                       <value>true</value>\r
+                               </dictionary>\r
+                               <dictionary>\r
+                                       <key>org.eclipse.cdt.make.core.autoBuildTarget</key>\r
+                                       <value>all</value>\r
+                               </dictionary>\r
+                               <dictionary>\r
+                                       <key>org.eclipse.cdt.make.core.buildArguments</key>\r
+                                       <value>-k</value>\r
+                               </dictionary>\r
+                               <dictionary>\r
+                                       <key>org.eclipse.cdt.make.core.buildCommand</key>\r
+                                       <value>${CCS_UTILS_DIR}/bin/gmake</value>\r
+                               </dictionary>\r
+                               <dictionary>\r
+                                       <key>org.eclipse.cdt.make.core.buildLocation</key>\r
+                                       <value>${BuildDirectory}</value>\r
+                               </dictionary>\r
+                               <dictionary>\r
+                                       <key>org.eclipse.cdt.make.core.cleanBuildTarget</key>\r
+                                       <value>clean</value>\r
+                               </dictionary>\r
+                               <dictionary>\r
+                                       <key>org.eclipse.cdt.make.core.contents</key>\r
+                                       <value>org.eclipse.cdt.make.core.activeConfigSettings</value>\r
+                               </dictionary>\r
+                               <dictionary>\r
+                                       <key>org.eclipse.cdt.make.core.enableAutoBuild</key>\r
+                                       <value>true</value>\r
+                               </dictionary>\r
+                               <dictionary>\r
+                                       <key>org.eclipse.cdt.make.core.enableCleanBuild</key>\r
+                                       <value>true</value>\r
+                               </dictionary>\r
+                               <dictionary>\r
+                                       <key>org.eclipse.cdt.make.core.enableFullBuild</key>\r
+                                       <value>true</value>\r
+                               </dictionary>\r
+                               <dictionary>\r
+                                       <key>org.eclipse.cdt.make.core.fullBuildTarget</key>\r
+                                       <value>all</value>\r
+                               </dictionary>\r
+                               <dictionary>\r
+                                       <key>org.eclipse.cdt.make.core.stopOnError</key>\r
+                                       <value>false</value>\r
+                               </dictionary>\r
+                               <dictionary>\r
+                                       <key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>\r
+                                       <value>true</value>\r
+                               </dictionary>\r
+                       </arguments>\r
+               </buildCommand>\r
+               <buildCommand>\r
+                       <name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>\r
+                       <triggers>full,incremental,</triggers>\r
                        <arguments>\r
                        </arguments>\r
                </buildCommand>\r
@@ -15,6 +77,7 @@
                <nature>org.eclipse.cdt.core.cnature</nature>\r
                <nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>\r
                <nature>org.eclipse.cdt.core.ccnature</nature>\r
-               <nature>com.ti.ccstudio.managedbuild.core.ccsNature</nature>\r
+               <nature>com.ti.ccstudio.core.ccsNature</nature>\r
+               <nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>\r
        </natures>\r
 </projectDescription>\r
index 4955739fdee2951bb31135680bae8d66b361b87e..4033c21577ac4eed6420c086e1a3f575b7b62e52 100644 (file)
@@ -13,8 +13,8 @@ IF EXIST FreeRTOS_Source Goto END
        REM Create the required directory structure.\r
        MD FreeRTOS_Source\r
        MD FreeRTOS_Source\include      \r
-       MD FreeRTOS_Source\portable\CCS4\r
-       MD FreeRTOS_Source\portable\CCS4\MSP430X\r
+       MD FreeRTOS_Source\portable\CCS\r
+       MD FreeRTOS_Source\portable\CCS\MSP430X\r
        MD FreeRTOS_Source\portable\MemMang     \r
        MD Demo_Source\Common_Demo_Files\r
        MD Demo_Source\Common_Demo_Files\include\r
@@ -30,7 +30,7 @@ IF EXIST FreeRTOS_Source Goto END
        copy ..\..\Source\include\*.* FreeRTOS_Source\include\r
        \r
        REM Copy the portable layer files\r
-       copy ..\..\Source\portable\CCS4\MSP430X\*.* FreeRTOS_Source\portable\CCS4\MSP430X\r
+       copy ..\..\Source\portable\CCS\MSP430X\*.* FreeRTOS_Source\portable\CCS\MSP430X\r
        \r
        REM Copy the basic memory allocation files\r
        copy ..\..\Source\portable\MemMang\heap_1.c FreeRTOS_Source\portable\MemMang\r
diff --git a/Demo/MSP430X_MSP430F5438_CCS4/Demo_Source/F5XX_6XX_Core_Lib/HAL_PMM.c b/Demo/MSP430X_MSP430F5438_CCS4/Demo_Source/F5XX_6XX_Core_Lib/HAL_PMM.c
new file mode 100644 (file)
index 0000000..7e16eae
--- /dev/null
@@ -0,0 +1,248 @@
+/*******************************************************************************\r
+ *\r
+ * HAL_PMM.c\r
+ * Power Management Module Library for MSP430F5xx/6xx family\r
+ *\r
+ *\r
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/\r
+ *\r
+ *\r
+ *  Redistribution and use in source and binary forms, with or without\r
+ *  modification, are permitted provided that the following conditions\r
+ *  are met:\r
+ *\r
+ *    Redistributions of source code must retain the above copyright\r
+ *    notice, this list of conditions and the following disclaimer.\r
+ *\r
+ *    Redistributions in binary form must reproduce the above copyright\r
+ *    notice, this list of conditions and the following disclaimer in the\r
+ *    documentation and/or other materials provided with the\r
+ *    distribution.\r
+ *\r
+ *    Neither the name of Texas Instruments Incorporated nor the names of\r
+ *    its contributors may be used to endorse or promote products derived\r
+ *    from this software without specific prior written permission.\r
+ *\r
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\r
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************/\r
+\r
+#include "msp430.h"\r
+#include "HAL_PMM.h"\r
+\r
+/*******************************************************************************\r
+ * \brief   Increase Vcore by one level\r
+ *\r
+ * \param level     Level to which Vcore needs to be increased\r
+ * \return status   Success/failure\r
+ ******************************************************************************/\r
+\r
+static uint16_t SetVCoreUp(uint8_t level)\r
+{\r
+    uint16_t PMMRIE_backup, SVSMHCTL_backup, SVSMLCTL_backup;\r
+\r
+    // The code flow for increasing the Vcore has been altered to work around\r
+    // the erratum FLASH37.\r
+    // Please refer to the Errata sheet to know if a specific device is affected\r
+    // DO NOT ALTER THIS FUNCTION\r
+\r
+    // Open PMM registers for write access\r
+    PMMCTL0_H = 0xA5;\r
+\r
+    // Disable dedicated Interrupts\r
+    // Backup all registers\r
+    PMMRIE_backup = PMMRIE;\r
+    PMMRIE &= ~(SVMHVLRPE | SVSHPE | SVMLVLRPE | SVSLPE | SVMHVLRIE |\r
+                SVMHIE | SVSMHDLYIE | SVMLVLRIE | SVMLIE | SVSMLDLYIE);\r
+    SVSMHCTL_backup = SVSMHCTL;\r
+    SVSMLCTL_backup = SVSMLCTL;\r
+\r
+    // Clear flags\r
+    PMMIFG = 0;\r
+\r
+    // Set SVM highside to new level and check if a VCore increase is possible\r
+    SVSMHCTL = SVMHE | SVSHE | (SVSMHRRL0 * level);\r
+\r
+    // Wait until SVM highside is settled\r
+    while ((PMMIFG & SVSMHDLYIFG) == 0) ;\r
+\r
+    // Clear flag\r
+    PMMIFG &= ~SVSMHDLYIFG;\r
+\r
+    // Check if a VCore increase is possible\r
+    if ((PMMIFG & SVMHIFG) == SVMHIFG){     // -> Vcc is too low for a Vcore increase\r
+        // recover the previous settings\r
+        PMMIFG &= ~SVSMHDLYIFG;\r
+        SVSMHCTL = SVSMHCTL_backup;\r
+\r
+        // Wait until SVM highside is settled\r
+        while ((PMMIFG & SVSMHDLYIFG) == 0) ;\r
+\r
+        // Clear all Flags\r
+        PMMIFG &= ~(SVMHVLRIFG | SVMHIFG | SVSMHDLYIFG | SVMLVLRIFG | SVMLIFG | SVSMLDLYIFG);\r
+\r
+        PMMRIE = PMMRIE_backup;             // Restore PMM interrupt enable register\r
+        PMMCTL0_H = 0x00;                   // Lock PMM registers for write access\r
+        return PMM_STATUS_ERROR;            // return: voltage not set\r
+    }\r
+\r
+    // Set also SVS highside to new level\r
+    // Vcc is high enough for a Vcore increase\r
+    SVSMHCTL |= (SVSHRVL0 * level);\r
+\r
+    // Wait until SVM highside is settled\r
+    while ((PMMIFG & SVSMHDLYIFG) == 0) ;\r
+\r
+    // Clear flag\r
+    PMMIFG &= ~SVSMHDLYIFG;\r
+\r
+    // Set VCore to new level\r
+    PMMCTL0_L = PMMCOREV0 * level;\r
+\r
+    // Set SVM, SVS low side to new level\r
+    SVSMLCTL = SVMLE | (SVSMLRRL0 * level) | SVSLE | (SVSLRVL0 * level);\r
+\r
+    // Wait until SVM, SVS low side is settled\r
+    while ((PMMIFG & SVSMLDLYIFG) == 0) ;\r
+\r
+    // Clear flag\r
+    PMMIFG &= ~SVSMLDLYIFG;\r
+    // SVS, SVM core and high side are now set to protect for the new core level\r
+\r
+    // Restore Low side settings\r
+    // Clear all other bits _except_ level settings\r
+    SVSMLCTL &= (SVSLRVL0 + SVSLRVL1 + SVSMLRRL0 + SVSMLRRL1 + SVSMLRRL2);\r
+\r
+    // Clear level settings in the backup register,keep all other bits\r
+    SVSMLCTL_backup &= ~(SVSLRVL0 + SVSLRVL1 + SVSMLRRL0 + SVSMLRRL1 + SVSMLRRL2);\r
+\r
+    // Restore low-side SVS monitor settings\r
+    SVSMLCTL |= SVSMLCTL_backup;\r
+\r
+    // Restore High side settings\r
+    // Clear all other bits except level settings\r
+    SVSMHCTL &= (SVSHRVL0 + SVSHRVL1 + SVSMHRRL0 + SVSMHRRL1 + SVSMHRRL2);\r
+\r
+    // Clear level settings in the backup register,keep all other bits\r
+    SVSMHCTL_backup &= ~(SVSHRVL0 + SVSHRVL1 + SVSMHRRL0 + SVSMHRRL1 + SVSMHRRL2);\r
+\r
+    // Restore backup\r
+    SVSMHCTL |= SVSMHCTL_backup;\r
+\r
+    // Wait until high side, low side settled\r
+    while (((PMMIFG & SVSMLDLYIFG) == 0) && ((PMMIFG & SVSMHDLYIFG) == 0)) ;\r
+\r
+    // Clear all Flags\r
+    PMMIFG &= ~(SVMHVLRIFG | SVMHIFG | SVSMHDLYIFG | SVMLVLRIFG | SVMLIFG | SVSMLDLYIFG);\r
+\r
+    PMMRIE = PMMRIE_backup;                 // Restore PMM interrupt enable register\r
+    PMMCTL0_H = 0x00;                       // Lock PMM registers for write access\r
+\r
+    return PMM_STATUS_OK;\r
+}\r
+\r
+/*******************************************************************************\r
+ * \brief  Decrease Vcore by one level\r
+ *\r
+ * \param  level    Level to which Vcore needs to be decreased\r
+ * \return status   Success/failure\r
+ ******************************************************************************/\r
+\r
+static uint16_t SetVCoreDown(uint8_t level)\r
+{\r
+    uint16_t PMMRIE_backup, SVSMHCTL_backup, SVSMLCTL_backup;\r
+\r
+    // The code flow for decreasing the Vcore has been altered to work around\r
+    // the erratum FLASH37.\r
+    // Please refer to the Errata sheet to know if a specific device is affected\r
+    // DO NOT ALTER THIS FUNCTION\r
+\r
+    // Open PMM registers for write access\r
+    PMMCTL0_H = 0xA5;\r
+\r
+    // Disable dedicated Interrupts\r
+    // Backup all registers\r
+    PMMRIE_backup = PMMRIE;\r
+    PMMRIE &= ~(SVMHVLRPE | SVSHPE | SVMLVLRPE | SVSLPE | SVMHVLRIE |\r
+                SVMHIE | SVSMHDLYIE | SVMLVLRIE | SVMLIE | SVSMLDLYIE);\r
+    SVSMHCTL_backup = SVSMHCTL;\r
+    SVSMLCTL_backup = SVSMLCTL;\r
+\r
+    // Clear flags\r
+    PMMIFG &= ~(SVMHIFG | SVSMHDLYIFG | SVMLIFG | SVSMLDLYIFG);\r
+\r
+    // Set SVM, SVS high & low side to new settings in normal mode\r
+    SVSMHCTL = SVMHE | (SVSMHRRL0 * level) | SVSHE | (SVSHRVL0 * level);\r
+    SVSMLCTL = SVMLE | (SVSMLRRL0 * level) | SVSLE | (SVSLRVL0 * level);\r
+\r
+    // Wait until SVM high side and SVM low side is settled\r
+    while ((PMMIFG & SVSMHDLYIFG) == 0 || (PMMIFG & SVSMLDLYIFG) == 0) ;\r
+\r
+    // Clear flags\r
+    PMMIFG &= ~(SVSMHDLYIFG + SVSMLDLYIFG);\r
+    // SVS, SVM core and high side are now set to protect for the new core level\r
+\r
+    // Set VCore to new level\r
+    PMMCTL0_L = PMMCOREV0 * level;\r
+\r
+    // Restore Low side settings\r
+    // Clear all other bits _except_ level settings\r
+    SVSMLCTL &= (SVSLRVL0 + SVSLRVL1 + SVSMLRRL0 + SVSMLRRL1 + SVSMLRRL2);\r
+\r
+    // Clear level settings in the backup register,keep all other bits\r
+    SVSMLCTL_backup &= ~(SVSLRVL0 + SVSLRVL1 + SVSMLRRL0 + SVSMLRRL1 + SVSMLRRL2);\r
+\r
+    // Restore low-side SVS monitor settings\r
+    SVSMLCTL |= SVSMLCTL_backup;\r
+\r
+    // Restore High side settings\r
+    // Clear all other bits except level settings\r
+    SVSMHCTL &= (SVSHRVL0 + SVSHRVL1 + SVSMHRRL0 + SVSMHRRL1 + SVSMHRRL2);\r
+\r
+    // Clear level settings in the backup register, keep all other bits\r
+    SVSMHCTL_backup &= ~(SVSHRVL0 + SVSHRVL1 + SVSMHRRL0 + SVSMHRRL1 + SVSMHRRL2);\r
+\r
+    // Restore backup\r
+    SVSMHCTL |= SVSMHCTL_backup;\r
+\r
+    // Wait until high side, low side settled\r
+    while (((PMMIFG & SVSMLDLYIFG) == 0) && ((PMMIFG & SVSMHDLYIFG) == 0)) ;\r
+\r
+    // Clear all Flags\r
+    PMMIFG &= ~(SVMHVLRIFG | SVMHIFG | SVSMHDLYIFG | SVMLVLRIFG | SVMLIFG | SVSMLDLYIFG);\r
+\r
+    PMMRIE = PMMRIE_backup;                // Restore PMM interrupt enable register\r
+    PMMCTL0_H = 0x00;                      // Lock PMM registers for write access\r
+    return PMM_STATUS_OK;                  // Return: OK\r
+}\r
+\r
+uint16_t SetVCore(uint8_t level)\r
+{\r
+    uint16_t actlevel;\r
+    uint16_t status = 0;\r
+\r
+    level &= PMMCOREV_3;                   // Set Mask for Max. level\r
+    actlevel = (PMMCTL0 & PMMCOREV_3);     // Get actual VCore\r
+                                           // step by step increase or decrease\r
+    while ((level != actlevel) && (status == 0)) {\r
+        if (level > actlevel){\r
+            status = SetVCoreUp(++actlevel);\r
+        }\r
+        else {\r
+            status = SetVCoreDown(--actlevel);\r
+        }\r
+    }\r
+\r
+    return status;\r
+}\r
+\r
diff --git a/Demo/MSP430X_MSP430F5438_CCS4/Demo_Source/F5XX_6XX_Core_Lib/HAL_PMM.h b/Demo/MSP430X_MSP430F5438_CCS4/Demo_Source/F5XX_6XX_Core_Lib/HAL_PMM.h
new file mode 100644 (file)
index 0000000..ace1641
--- /dev/null
@@ -0,0 +1,113 @@
+/*******************************************************************************\r
+ *\r
+ * HAL_PMM.h\r
+ * Power Management Module Library for MSP430F5xx/6xx family\r
+ *\r
+ *\r
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/\r
+ *\r
+ *\r
+ *  Redistribution and use in source and binary forms, with or without\r
+ *  modification, are permitted provided that the following conditions\r
+ *  are met:\r
+ *\r
+ *    Redistributions of source code must retain the above copyright\r
+ *    notice, this list of conditions and the following disclaimer.\r
+ *\r
+ *    Redistributions in binary form must reproduce the above copyright\r
+ *    notice, this list of conditions and the following disclaimer in the\r
+ *    documentation and/or other materials provided with the\r
+ *    distribution.\r
+ *\r
+ *    Neither the name of Texas Instruments Incorporated nor the names of\r
+ *    its contributors may be used to endorse or promote products derived\r
+ *    from this software without specific prior written permission.\r
+ *\r
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\r
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************/\r
+\r
+#ifndef HAL_PMM_H\r
+#define HAL_PMM_H\r
+\r
+#include <stdint.h>\r
+#include "HAL_MACROS.h"\r
+\r
+/*******************************************************************************\r
+ * Macros\r
+ ******************************************************************************/\r
+#define ENABLE_SVSL()        st(PMMCTL0_H = 0xA5; SVSMLCTL |= SVSLE; PMMCTL0_H = 0x00; )\r
+#define DISABLE_SVSL()       st(PMMCTL0_H = 0xA5; SVSMLCTL &= ~SVSLE; PMMCTL0_H = 0x00; )\r
+#define ENABLE_SVML()        st(PMMCTL0_H = 0xA5; SVSMLCTL |= SVMLE; PMMCTL0_H = 0x00; )\r
+#define DISABLE_SVML()       st(PMMCTL0_H = 0xA5; SVSMLCTL &= ~SVMLE; PMMCTL0_H = 0x00; )\r
+#define ENABLE_SVSH()        st(PMMCTL0_H = 0xA5; SVSMHCTL |= SVSHE; PMMCTL0_H = 0x00; )\r
+#define DISABLE_SVSH()       st(PMMCTL0_H = 0xA5; SVSMHCTL &= ~SVSHE; PMMCTL0_H = 0x00; )\r
+#define ENABLE_SVMH()        st(PMMCTL0_H = 0xA5; SVSMHCTL |= SVMHE; PMMCTL0_H = 0x00; )\r
+#define DISABLE_SVMH()       st(PMMCTL0_H = 0xA5; SVSMHCTL &= ~SVMHE; PMMCTL0_H = 0x00; )\r
+#define ENABLE_SVSL_SVML()   st(PMMCTL0_H = 0xA5; SVSMLCTL |= (SVSLE + SVMLE); PMMCTL0_H = 0x00; )\r
+#define DISABLE_SVSL_SVML()  st(PMMCTL0_H = 0xA5; SVSMLCTL &= ~(SVSLE + SVMLE); PMMCTL0_H = 0x00; )\r
+#define ENABLE_SVSH_SVMH()   st(PMMCTL0_H = 0xA5; SVSMHCTL |= (SVSHE + SVMHE); PMMCTL0_H = 0x00; )\r
+#define DISABLE_SVSH_SVMH()  st(PMMCTL0_H = 0xA5; SVSMHCTL &= ~(SVSHE + SVMHE); PMMCTL0_H = 0x00; )\r
+\r
+#define ENABLE_SVSL_RESET()       st(PMMCTL0_H = 0xA5; PMMRIE |= SVSLPE; PMMCTL0_H = 0x00; )\r
+#define DISABLE_SVSL_RESET()      st(PMMCTL0_H = 0xA5; PMMRIE &= ~SVSLPE; PMMCTL0_H = 0x00; )\r
+#define ENABLE_SVML_INTERRUPT()   st(PMMCTL0_H = 0xA5; PMMRIE |= SVMLIE; PMMCTL0_H = 0x00; )\r
+#define DISABLE_SVML_INTERRUPT()  st(PMMCTL0_H = 0xA5; PMMRIE &= ~SVMLIE; PMMCTL0_H = 0x00; )\r
+#define ENABLE_SVSH_RESET()       st(PMMCTL0_H = 0xA5; PMMRIE |= SVSHPE; PMMCTL0_H = 0x00; )\r
+#define DISABLE_SVSH_RESET()      st(PMMCTL0_H = 0xA5; PMMRIE &= ~SVSHPE; PMMCTL0_H = 0x00; )\r
+#define ENABLE_SVMH_INTERRUPT()   st(PMMCTL0_H = 0xA5; PMMRIE |= SVMHIE; PMMCTL0_H = 0x00; )\r
+#define DISABLE_SVMH_INTERRUPT()  st(PMMCTL0_H = 0xA5; PMMRIE &= ~SVMHIE; PMMCTL0_H = 0x00; )\r
+#define CLEAR_PMM_IFGS()          st(PMMCTL0_H = 0xA5; PMMIFG = 0; PMMCTL0_H = 0x00; )\r
+\r
+// These settings use SVSH/LACE = 0\r
+#define SVSL_ENABLED_IN_LPM_FAST_WAKE()  st( \\r
+        PMMCTL0_H = 0xA5; SVSMLCTL |= (SVSLFP + SVSLMD); SVSMLCTL &= ~SVSMLACE; PMMCTL0_H = 0x00; )\r
+#define SVSL_ENABLED_IN_LPM_SLOW_WAKE()  st(PMMCTL0_H = 0xA5; SVSMLCTL |= SVSLMD; SVSMLCTL &= \\r
+                                                ~(SVSLFP + SVSMLACE); PMMCTL0_H = 0x00; )\r
+\r
+#define SVSL_DISABLED_IN_LPM_FAST_WAKE() st(PMMCTL0_H = 0xA5; SVSMLCTL |= SVSLFP; SVSMLCTL &= \\r
+                                                ~(SVSLMD + SVSMLACE); PMMCTL0_H = 0x00; )\r
+#define SVSL_DISABLED_IN_LPM_SLOW_WAKE() st(PMMCTL0_H = 0xA5; SVSMLCTL &= \\r
+                                                ~(SVSLFP + SVSMLACE + SVSLMD); PMMCTL0_H = 0x00; )\r
+\r
+#define SVSH_ENABLED_IN_LPM_NORM_PERF()  st(PMMCTL0_H = 0xA5; SVSMHCTL |= SVSHMD; SVSMHCTL &= \\r
+                                                ~(SVSMHACE + SVSHFP); PMMCTL0_H = 0x00; )\r
+#define SVSH_ENABLED_IN_LPM_FULL_PERF()  st( \\r
+        PMMCTL0_H = 0xA5; SVSMHCTL |= (SVSHMD + SVSHFP); SVSMHCTL &= ~SVSMHACE; PMMCTL0_H = 0x00; )\r
+\r
+#define SVSH_DISABLED_IN_LPM_NORM_PERF() st(PMMCTL0_H = 0xA5; SVSMHCTL &= \\r
+                                                ~(SVSMHACE + SVSHFP + SVSHMD); PMMCTL0_H = 0x00; )\r
+#define SVSH_DISABLED_IN_LPM_FULL_PERF() st(PMMCTL0_H = 0xA5; SVSMHCTL |= SVSHFP; SVSMHCTL &= \\r
+                                                ~(SVSMHACE + SVSHMD); PMMCTL0_H = 0x00; )\r
+\r
+// These setting use SVSH/LACE = 1\r
+#define SVSL_OPTIMIZED_IN_LPM_FAST_WAKE() st(PMMCTL0_H = 0xA5; SVSMLCTL |= \\r
+                                                 (SVSLFP + SVSLMD + SVSMLACE); PMMCTL0_H = 0x00; )\r
+#define SVSH_OPTIMIZED_IN_LPM_FULL_PERF() st(PMMCTL0_H = 0xA5; SVSMHCTL |= \\r
+                                                 (SVSHMD + SVSHFP + SVSMHACE); PMMCTL0_H = 0x00; )\r
+\r
+/*******************************************************************************\r
+ * Defines\r
+ ******************************************************************************/\r
+#define PMM_STATUS_OK     0\r
+#define PMM_STATUS_ERROR  1\r
+\r
+/*******************************************************************************\r
+ * \brief   Set Vcore to expected level\r
+ *\r
+ * \param level     Level to which Vcore needs to be increased/decreased\r
+ * \return status   Success/failure\r
+ ******************************************************************************/\r
+extern uint16_t SetVCore(uint8_t level);\r
+\r
+#endif /* HAL_PMM_H */\r
index b1c93d5a705b2ad1b616ceb377fffdd54ce88e26..e320f7590e50400e4f6f33198521b2d4296703a1 100644 (file)
@@ -1,6 +1,6 @@
 /*\r
     FreeRTOS V7.1.0 - Copyright (C) 2011 Real Time Engineers Ltd.\r
-       \r
+\r
 \r
     ***************************************************************************\r
      *                                                                       *\r
@@ -53,8 +53,8 @@
 \r
 \r
 /* The following #error directive is to remind users that a batch file must be\r
- * executed prior to this project being built.  The batch file *cannot* be \r
- * executed from within CCS4!  Once it has been executed, re-open or refresh \r
+ * executed prior to this project being built.  The batch file *cannot* be\r
+ * executed from within CCS4!  Once it has been executed, re-open or refresh\r
  * the CCS4 project and remove the #error line below.\r
  */\r
 //#error Ensure CreateProjectDirectoryStructure.bat has been executed before building.  See comment immediately above.\r
@@ -78,7 +78,8 @@
 #define configUSE_PREEMPTION                   1\r
 #define configUSE_IDLE_HOOK                            1\r
 #define configUSE_TICK_HOOK                            1\r
-#define configCPU_CLOCK_HZ                             ( 25000000UL )  \r
+#define configCPU_CLOCK_HZ                             ( 25000000UL )\r
+#define configLFXT_CLOCK_HZ                    ( 32768L )\r
 #define configTICK_RATE_HZ                             ( ( portTickType ) 1000 )\r
 #define configMAX_PRIORITIES                   ( ( unsigned portBASE_TYPE ) 5 )\r
 #define configTOTAL_HEAP_SIZE                  ( ( size_t ) ( 10 * 1024 ) )\r
@@ -128,8 +129,8 @@ vector for the chosen tick interrupt source.  This implementation of
 vApplicationSetupTimerInterrupt() generates the tick from timer A0, so in this\r
 case configTICK_VECTOR is set to TIMER0_A0_VECTOR. */\r
 #define configTICK_VECTOR                              TIMER0_A0_VECTOR\r
-       \r
-#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); for( ;; ); }    \r
-       \r
+\r
+#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); for( ;; ); }\r
+\r
 #endif /* FREERTOS_CONFIG_H */\r
 \r
index c1baa94ff38178d8ddef88fd8c10faf2de8cdee3..6d97edac0cc417517d50c19d0ed32be9bb5a884b 100644 (file)
@@ -23,5 +23,6 @@ in order to use MSP-EXP430F5438 HAL.
 //#include "hal_rf.h"\r
 //#include "hal_rtc.h"\r
 //#include "hal_tlv.h"\r
+#include "hal_pmm.h"\r
 \r
 #endif /* HAL_MSP_EXP430F5438_H */\r
index f44d7409a09d6a845bee99d65a46bf3e0c2f9b07..444741ab7ea7c3bfcbb4d11f7ebc6643a07589c2 100644 (file)
@@ -66,3 +66,43 @@ void halBoardInit(void)
   PJDIR  = 0xFF;\r
   P11SEL = 0;\r
 }\r
+\r
+/**********************************************************************//**\r
+ * @brief  Set function for MCLK frequency.\r
+ *\r
+ *\r
+ * @return none\r
+ *************************************************************************/\r
+void hal430SetSystemClock(unsigned long req_clock_rate, unsigned long ref_clock_rate)\r
+{\r
+  /* Convert a Hz value to a KHz value, as required\r
+   *  by the Init_FLL_Settle() function. */\r
+  unsigned long ulCPU_Clock_KHz = req_clock_rate / 1000UL;\r
+\r
+  //Make sure we aren't overclocking\r
+  if(ulCPU_Clock_KHz > 25000L)\r
+  {\r
+    ulCPU_Clock_KHz = 25000L;\r
+  }\r
+\r
+  //Set VCore to a level sufficient for the requested clock speed.\r
+  if(ulCPU_Clock_KHz <= 8000L)\r
+  {\r
+    SetVCore(PMMCOREV_0);\r
+  }\r
+  else if(ulCPU_Clock_KHz <= 12000L)\r
+  {\r
+    SetVCore(PMMCOREV_1);\r
+  }\r
+  else if(ulCPU_Clock_KHz <= 20000L)\r
+  {\r
+    SetVCore(PMMCOREV_2);\r
+  }\r
+  else\r
+  {\r
+    SetVCore(PMMCOREV_3);\r
+  }\r
+\r
+  //Set the DCO\r
+  Init_FLL_Settle( ( unsigned short )ulCPU_Clock_KHz, req_clock_rate / ref_clock_rate );\r
+}\r
index 603c728362ce068ee9d1340b44a0ed085bd2149b..c4fe6318de56c09992fab53744f918100ef7d943 100644 (file)
@@ -27,5 +27,6 @@ static void halBoardGetSystemClockSettings(unsigned char systemClockSpeed,
 extern void halBoardOutputSystemClock(void);\r
 extern void halBoardStopOutputSystemClock(void);\r
 extern void halBoardInit(void);\r
+void hal430SetSystemClock(unsigned long req_clock_rate, unsigned long ref_clock_rate);\r
 \r
 #endif /* HAL_BOARD_H */\r
index de69d0109adcb34791910ecfcbc1de8b67361093..90f173341f0a70709f4d4f3be94ab3b1d3798a76 100644 (file)
@@ -528,10 +528,6 @@ static xQueueMessage xStatusMessage = { mainMESSAGE_STATUS, pdPASS };
 \r
 static void prvSetupHardware( void )\r
 {\r
-/* Convert a Hz value to a KHz value, as required by the Init_FLL_Settle()\r
-function. */\r
-unsigned long ulCPU_Clock_KHz = ( configCPU_CLOCK_HZ / 1000UL );\r
-\r
        taskDISABLE_INTERRUPTS();\r
        \r
        /* Disable the watchdog. */\r
@@ -540,7 +536,7 @@ unsigned long ulCPU_Clock_KHz = ( configCPU_CLOCK_HZ / 1000UL );
        halBoardInit();\r
 \r
        LFXT_Start( XT1DRIVE_0 );\r
-       Init_FLL_Settle( ( unsigned short ) ulCPU_Clock_KHz, 488 );\r
+       hal430SetSystemClock( configCPU_CLOCK_HZ, configLFXT_CLOCK_HZ );\r
 \r
        halButtonsInit( BUTTON_ALL );\r
        halButtonsInterruptEnable( BUTTON_SELECT );\r
diff --git a/Demo/MSP430X_MSP430F5438_CCS4/READ_ME_FIRST.txt b/Demo/MSP430X_MSP430F5438_CCS4/READ_ME_FIRST.txt
new file mode 100644 (file)
index 0000000..2d6c226
--- /dev/null
@@ -0,0 +1,3 @@
+Import this project into code composer studio using File->Import->Code Composer Studio->Existing CCS/CCE Ecplise Projects.\r
+\r
+The project will *not* open correctly by selecting File->Import->Existing Projects into Workspace.
\ No newline at end of file