/*\r
- FreeRTOS.org V4.2.1 - Copyright (C) 2003-2007 Richard Barry.\r
+ FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
-# FreeRTOS.org V4.2.1 - Copyright (C) 2003-2007 Richard Barry.\r
+# FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry.\r
#\r
# This file is part of the FreeRTOS.org distribution.\r
#\r
/*\r
- FreeRTOS.org V4.2.1 - Copyright (C) 2003-2007 Richard Barry.\r
+ FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
-/*-------------------------------------------------------------------------
- Register Declarations for the Cygnal C8051F12x Processor Range
-
- Copyright (C) 2003 - Maarten Brock, sourceforge.brock@dse.nl
-
- This library is free software; you can redistribute it and/or
- modify it under the terms of the GNU Lesser General Public
- License as published by the Free Software Foundation; either
- version 2.1 of the License, or (at your option) any later version.
-
- This library is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- Lesser General Public License for more details.
-
- You should have received a copy of the GNU Lesser General Public
- License along with this library; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
--------------------------------------------------------------------------*/
-
-#ifndef C8051F120_H
-#define C8051F120_H
-
-
-/* BYTE Registers */
-
-/* All Pages */
-sfr at 0x80 P0 ; /* PORT 0 */
-sfr at 0x81 SP ; /* STACK POINTER */
-sfr at 0x82 DPL ; /* DATA POINTER - LOW BYTE */
-sfr at 0x83 DPH ; /* DATA POINTER - HIGH BYTE */
-sfr at 0x84 SFRPAGE ; /* SFR PAGE SELECT */
-sfr at 0x85 SFRNEXT ; /* SFR STACK NEXT PAGE */
-sfr at 0x86 SFRLAST ; /* SFR STACK LAST PAGE */
-sfr at 0x87 PCON ; /* POWER CONTROL */
-sfr at 0x90 P1 ; /* PORT 1 */
-sfr at 0xA0 P2 ; /* PORT 2 */
-sfr at 0xA8 IE ; /* INTERRUPT ENABLE */
-sfr at 0xB0 P3 ; /* PORT 3 */
-sfr at 0xB1 PSBANK ; /* FLASH BANK SELECT */
-sfr at 0xB8 IP ; /* INTERRUPT PRIORITY */
-sfr at 0xD0 PSW ; /* PROGRAM STATUS WORD */
-sfr at 0xE0 ACC ; /* ACCUMULATOR */
-sfr at 0xE6 EIE1 ; /* EXTERNAL INTERRUPT ENABLE 1 */
-sfr at 0xE7 EIE2 ; /* EXTERNAL INTERRUPT ENABLE 2 */
-sfr at 0xF0 B ; /* B REGISTER */
-sfr at 0xF6 EIP1 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */
-sfr at 0xF7 EIP2 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 2 */
-sfr at 0xFF WDTCN ; /* WATCHDOG TIMER CONTROL */
-
-/* Page 0x00 */
-sfr at 0x88 TCON ; /* TIMER CONTROL */
-sfr at 0x89 TMOD ; /* TIMER MODE */
-sfr at 0x8A TL0 ; /* TIMER 0 - LOW BYTE */
-sfr at 0x8B TL1 ; /* TIMER 1 - LOW BYTE */
-sfr at 0x8C TH0 ; /* TIMER 0 - HIGH BYTE */
-sfr at 0x8D TH1 ; /* TIMER 1 - HIGH BYTE */
-sfr at 0x8E CKCON ; /* TIMER 0/1 CLOCK CONTROL */
-sfr at 0x8F PSCTL ; /* FLASH WRITE/ERASE CONTROL */
-sfr at 0x91 SSTA0 ; /* UART 0 STATUS */
-sfr at 0x98 SCON0 ; /* UART 0 CONTROL */
-sfr at 0x98 SCON ; /* UART 0 CONTROL */
-sfr at 0x99 SBUF0 ; /* UART 0 BUFFER */
-sfr at 0x99 SBUF ; /* UART 0 BUFFER */
-sfr at 0x9A SPI0CFG ; /* SPI 0 CONFIGURATION */
-sfr at 0x9B SPI0DAT ; /* SPI 0 DATA */
-sfr at 0x9D SPI0CKR ; /* SPI 0 CLOCK RATE CONTROL */
-sfr at 0xA1 EMI0TC ; /* EMIF TIMING CONTROL */
-sfr at 0xA2 EMI0CN ; /* EMIF CONTROL */
-sfr at 0xA2 _XPAGE ; /* XDATA/PDATA PAGE */
-sfr at 0xA3 EMI0CF ; /* EMIF CONFIGURATION */
-sfr at 0xA9 SADDR0 ; /* UART 0 SLAVE ADDRESS */
-sfr at 0xB7 FLSCL ; /* FLASH SCALE */
-sfr at 0xB9 SADEN0 ; /* UART 0 SLAVE ADDRESS MASK */
-sfr at 0xBA AMX0CF ; /* ADC 0 MUX CONFIGURATION */
-sfr at 0xBB AMX0SL ; /* ADC 0 MUX CHANNEL SELECTION */
-sfr at 0xBC ADC0CF ; /* ADC 0 CONFIGURATION */
-sfr at 0xBE ADC0L ; /* ADC 0 DATA - LOW BYTE */
-sfr at 0xBF ADC0H ; /* ADC 0 DATA - HIGH BYTE */
-sfr at 0xC0 SMB0CN ; /* SMBUS 0 CONTROL */
-sfr at 0xC1 SMB0STA ; /* SMBUS 0 STATUS */
-sfr at 0xC2 SMB0DAT ; /* SMBUS 0 DATA */
-sfr at 0xC3 SMB0ADR ; /* SMBUS 0 SLAVE ADDRESS */
-sfr at 0xC4 ADC0GTL ; /* ADC 0 GREATER-THAN REGISTER - LOW BYTE */
-sfr at 0xC5 ADC0GTH ; /* ADC 0 GREATER-THAN REGISTER - HIGH BYTE */
-sfr at 0xC6 ADC0LTL ; /* ADC 0 LESS-THAN REGISTER - LOW BYTE */
-sfr at 0xC7 ADC0LTH ; /* ADC 0 LESS-THAN REGISTER - HIGH BYTE */
-sfr at 0xC8 TMR2CN ; /* TIMER 2 CONTROL */
-sfr at 0xC9 TMR2CF ; /* TIMER 2 CONFIGURATION */
-sfr at 0xCA RCAP2L ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
-sfr at 0xCB RCAP2H ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
-sfr at 0xCC TMR2L ; /* TIMER 2 - LOW BYTE */
-sfr at 0xCC TL2 ; /* TIMER 2 - LOW BYTE */
-sfr at 0xCD TMR2H ; /* TIMER 2 - HIGH BYTE */
-sfr at 0xCD TH2 ; /* TIMER 2 - HIGH BYTE */
-sfr at 0xCF SMB0CR ; /* SMBUS 0 CLOCK RATE */
-sfr at 0xD1 REF0CN ; /* VOLTAGE REFERENCE 0 CONTROL */
-sfr at 0xD2 DAC0L ; /* DAC 0 REGISTER - LOW BYTE */
-sfr at 0xD3 DAC0H ; /* DAC 0 REGISTER - HIGH BYTE */
-sfr at 0xD4 DAC0CN ; /* DAC 0 CONTROL */
-sfr at 0xD8 PCA0CN ; /* PCA 0 COUNTER CONTROL */
-sfr at 0xD9 PCA0MD ; /* PCA 0 COUNTER MODE */
-sfr at 0xDA PCA0CPM0 ; /* PCA 0 MODULE 0 CONTROL */
-sfr at 0xDB PCA0CPM1 ; /* PCA 0 MODULE 1 CONTROL */
-sfr at 0xDC PCA0CPM2 ; /* PCA 0 MODULE 2 CONTROL */
-sfr at 0xDD PCA0CPM3 ; /* PCA 0 MODULE 3 CONTROL */
-sfr at 0xDE PCA0CPM4 ; /* PCA 0 MODULE 4 CONTROL */
-sfr at 0xDF PCA0CPM5 ; /* PCA 0 MODULE 5 CONTROL */
-sfr at 0xE1 PCA0CPL5 ; /* PCA 0 MODULE 5 CAPTURE/COMPARE - LOW BYTE */
-sfr at 0xE2 PCA0CPH5 ; /* PCA 0 MODULE 5 CAPTURE/COMPARE - HIGH BYTE */
-sfr at 0xE8 ADC0CN ; /* ADC 0 CONTROL */
-sfr at 0xE9 PCA0CPL2 ; /* PCA 0 MODULE 2 CAPTURE/COMPARE - LOW BYTE */
-sfr at 0xEA PCA0CPH2 ; /* PCA 0 MODULE 2 CAPTURE/COMPARE - HIGH BYTE */
-sfr at 0xEB PCA0CPL3 ; /* PCA 0 MODULE 3 CAPTURE/COMPARE - LOW BYTE */
-sfr at 0xEC PCA0CPH3 ; /* PCA 0 MODULE 3 CAPTURE/COMPARE - HIGH BYTE */
-sfr at 0xED PCA0CPL4 ; /* PCA 0 MODULE 4 CAPTURE/COMPARE - LOW BYTE */
-sfr at 0xEE PCA0CPH4 ; /* PCA 0 MODULE 4 CAPTURE/COMPARE - HIGH BYTE */
-sfr at 0xEF RSTSRC ; /* RESET SOURCE */
-sfr at 0xF8 SPI0CN ; /* SPI 0 CONTROL */
-sfr at 0xF9 PCA0L ; /* PCA 0 TIMER - LOW BYTE */
-sfr at 0xFA PCA0H ; /* PCA 0 TIMER - HIGH BYTE */
-sfr at 0xFB PCA0CPL0 ; /* PCA 0 MODULE 0 CAPTURE/COMPARE - LOW BYTE */
-sfr at 0xFC PCA0CPH0 ; /* PCA 0 MODULE 0 CAPTURE/COMPARE - HIGH BYTE */
-sfr at 0xFD PCA0CPL1 ; /* PCA 0 MODULE 1 CAPTURE/COMPARE - LOW BYTE */
-sfr at 0xFE PCA0CPH1 ; /* PCA 0 MODULE 1 CAPTURE/COMPARE - HIGH BYTE */
-
-/* Page 0x01 */
-sfr at 0x88 CPT0CN ; /* COMPARATOR 0 CONTROL */
-sfr at 0x89 CPT0MD ; /* COMPARATOR 0 CONFIGURATION */
-sfr at 0x98 SCON1 ; /* UART 1 CONTROL */
-sfr at 0x99 SBUF1 ; /* UART 1 BUFFER */
-sfr at 0xC8 TMR3CN ; /* TIMER 3 CONTROL */
-sfr at 0xC9 TMR3CF ; /* TIMER 3 CONFIGURATION */
-sfr at 0xCA RCAP3L ; /* TIMER 3 CAPTURE REGISTER - LOW BYTE */
-sfr at 0xCB RCAP3H ; /* TIMER 3 CAPTURE REGISTER - HIGH BYTE */
-sfr at 0xCC TMR3L ; /* TIMER 3 - LOW BYTE */
-sfr at 0xCD TMR3H ; /* TIMER 3 - HIGH BYTE */
-sfr at 0xD2 DAC1L ; /* DAC 1 REGISTER - LOW BYTE */
-sfr at 0xD3 DAC1H ; /* DAC 1 REGISTER - HIGH BYTE */
-sfr at 0xD4 DAC1CN ; /* DAC 1 CONTROL */
-
-/* Page 0x02 */
-sfr at 0x88 CPT1CN ; /* COMPARATOR 1 CONTROL */
-sfr at 0x89 CPT1MD ; /* COMPARATOR 1 CONFIGURATION */
-sfr at 0xBA AMX2CF ; /* ADC 2 MUX CONFIGURATION */
-sfr at 0xBB AMX2SL ; /* ADC 2 MUX CHANNEL SELECTION */
-sfr at 0xBC ADC2CF ; /* ADC 2 CONFIGURATION */
-sfr at 0xBE ADC2 ; /* ADC 2 DATA */
-sfr at 0xC4 ADC2GT ; /* ADC 2 GREATER-THAN REGISTER */
-sfr at 0xC6 ADC2LT ; /* ADC 2 LESS-THAN REGISTER */
-sfr at 0xC8 TMR4CN ; /* TIMER 4 CONTROL */
-sfr at 0xC9 TMR4CF ; /* TIMER 4 CONFIGURATION */
-sfr at 0xCA RCAP4L ; /* TIMER 4 CAPTURE REGISTER - LOW BYTE */
-sfr at 0xCB RCAP4H ; /* TIMER 4 CAPTURE REGISTER - HIGH BYTE */
-sfr at 0xCC TMR4L ; /* TIMER 4 - LOW BYTE */
-sfr at 0xCD TMR4H ; /* TIMER 4 - HIGH BYTE */
-
-/* Page 0x02 */
-sfr at 0x91 MAC0BL ; /* MAC0 B Register Low Byte */
-sfr at 0x92 MAC0BH ; /* MAC0 B Register High Byte */
-sfr at 0x93 MAC0ACC0 ; /* MAC0 Accumulator Byte 0 (LSB) */
-sfr at 0x94 MAC0ACC1 ; /* MAC0 Accumulator Byte 1 */
-sfr at 0x95 MAC0ACC2 ; /* MAC0 Accumulator Byte 2 */
-sfr at 0x96 MAC0ACC3 ; /* MAC0 Accumulator Byte 3 (MSB) */
-sfr at 0x97 MAC0OVR ; /* MAC0 Accumulator Overflow */
-sfr at 0xC0 MAC0STA ; /* MAC0 Status Register */
-sfr at 0xC1 MAC0AL ; /* MAC0 A Register Low Byte */
-sfr at 0xC2 MAC0AH ; /* MAC0 A Register High Byte */
-sfr at 0xC3 MAC0CF ; /* MAC0 Configuration */
-sfr at 0xCE MAC0RNDL ; /* MAC0 Rounding Register Low Byte */
-sfr at 0xCF MAC0RNDH ; /* MAC0 Rounding Register High Byte */
-
-/* Page 0x0F */
-sfr at 0x88 FLSTAT ; /* FLASH STATUS */
-sfr at 0x89 PLL0CN ; /* PLL 0 CONTROL */
-sfr at 0x8A OSCICN ; /* INTERNAL OSCILLATOR CONTROL */
-sfr at 0x8B OSCICL ; /* INTERNAL OSCILLATOR CALIBRATION */
-sfr at 0x8C OSCXCN ; /* EXTERNAL OSCILLATOR CONTROL */
-sfr at 0x8D PLL0DIV ; /* PLL 0 DIVIDER */
-sfr at 0x8E PLL0MUL ; /* PLL 0 MULTIPLIER */
-sfr at 0x8F PLL0FLT ; /* PLL 0 FILTER */
-sfr at 0x96 SFRPGCN ; /* SFR PAGE CONTROL */
-sfr at 0x97 CLKSEL ; /* SYSTEM CLOCK SELECT */
-sfr at 0x9A CCH0MA ; /* CACHE MISS ACCUMULATOR */
-sfr at 0x9C P4MDOUT ; /* PORT 4 OUTPUT MODE */
-sfr at 0x9D P5MDOUT ; /* PORT 5 OUTPUT MODE */
-sfr at 0x9E P6MDOUT ; /* PORT 6 OUTPUT MODE */
-sfr at 0x9F P7MDOUT ; /* PORT 7 OUTPUT MODE */
-sfr at 0xA1 CCH0CN ; /* CACHE CONTROL */
-sfr at 0xA2 CCH0TN ; /* CACHE TUNING REGISTER */
-sfr at 0xA3 CCH0LC ; /* CACHE LOCK */
-sfr at 0xA4 P0MDOUT ; /* PORT 0 OUTPUT MODE */
-sfr at 0xA5 P1MDOUT ; /* PORT 1 OUTPUT MODE */
-sfr at 0xA6 P2MDOUT ; /* PORT 2 OUTPUT MODE CONFIGURATION */
-sfr at 0xA7 P3MDOUT ; /* PORT 3 OUTPUT MODE CONFIGURATION */
-sfr at 0xAD P1MDIN ; /* PORT 1 INPUT MODE */
-sfr at 0xB7 FLACL ; /* FLASH ACCESS LIMIT */
-sfr at 0xC8 P4 ; /* PORT 4 */
-sfr at 0xD8 P5 ; /* PORT 5 */
-sfr at 0xE1 XBR0 ; /* CROSSBAR CONFIGURATION REGISTER 0 */
-sfr at 0xE2 XBR1 ; /* CROSSBAR CONFIGURATION REGISTER 1 */
-sfr at 0xE3 XBR2 ; /* CROSSBAR CONFIGURATION REGISTER 2 */
-sfr at 0xE8 ADC2CN ; /* ADC 2 CONTROL */
-sfr at 0xE8 P6 ; /* PORT 6 */
-sfr at 0xF8 P7 ; /* PORT 7 */
-
-
-/* BIT Registers */
-
-/* P0 0x80 */
-sbit at 0x80 P0_0 ;
-sbit at 0x81 P0_1 ;
-sbit at 0x82 P0_2 ;
-sbit at 0x83 P0_3 ;
-sbit at 0x84 P0_4 ;
-sbit at 0x85 P0_5 ;
-sbit at 0x86 P0_6 ;
-sbit at 0x87 P0_7 ;
-
-/* TCON 0x88 */
-sbit at 0x88 IT0 ; /* EXT. INTERRUPT 0 TYPE */
-sbit at 0x89 IE0 ; /* EXT. INTERRUPT 0 EDGE FLAG */
-sbit at 0x8A IT1 ; /* EXT. INTERRUPT 1 TYPE */
-sbit at 0x8B IE1 ; /* EXT. INTERRUPT 1 EDGE FLAG */
-sbit at 0x8C TR0 ; /* TIMER 0 ON/OFF CONTROL */
-sbit at 0x8D TF0 ; /* TIMER 0 OVERFLOW FLAG */
-sbit at 0x8E TR1 ; /* TIMER 1 ON/OFF CONTROL */
-sbit at 0x8F TF1 ; /* TIMER 1 OVERFLOW FLAG */
-
-/* CPT0CN 0x88 */
-sbit at 0x88 CP0HYN0 ; /* COMPARATOR 0 NEGATIVE HYSTERESIS 0 */
-sbit at 0x89 CP0HYN1 ; /* COMPARATOR 0 NEGATIVE HYSTERESIS 1 */
-sbit at 0x8A CP0HYP0 ; /* COMPARATOR 0 POSITIVE HYSTERESIS 0 */
-sbit at 0x8B CP0HYP1 ; /* COMPARATOR 0 POSITIVE HYSTERESIS 1 */
-sbit at 0x8C CP0FIF ; /* COMPARATOR 0 FALLING EDGE INTERRUPT */
-sbit at 0x8D CP0RIF ; /* COMPARATOR 0 RISING EDGE INTERRUPT */
-sbit at 0x8E CP0OUT ; /* COMPARATOR 0 OUTPUT */
-sbit at 0x8F CP0EN ; /* COMPARATOR 0 ENABLE */
-
-/* CPT1CN 0x88 */
-sbit at 0x88 CP1HYN0 ; /* COMPARATOR 1 NEGATIVE HYSTERESIS 0 */
-sbit at 0x89 CP1HYN1 ; /* COMPARATOR 1 NEGATIVE HYSTERESIS 1 */
-sbit at 0x8A CP1HYP0 ; /* COMPARATOR 1 POSITIVE HYSTERESIS 0 */
-sbit at 0x8B CP1HYP1 ; /* COMPARATOR 1 POSITIVE HYSTERESIS 1 */
-sbit at 0x8C CP1FIF ; /* COMPARATOR 1 FALLING EDGE INTERRUPT */
-sbit at 0x8D CP1RIF ; /* COMPARATOR 1 RISING EDGE INTERRUPT */
-sbit at 0x8E CP1OUT ; /* COMPARATOR 1 OUTPUT */
-sbit at 0x8F CP1EN ; /* COMPARATOR 1 ENABLE */
-
-/* FLSTAT 0x88 */
-sbit at 0x88 FLHBUSY ; /* FLASH BUSY */
-
-/* SCON0 0x98 */
-sbit at 0x98 RI0 ; /* UART 0 RX INTERRUPT FLAG */
-sbit at 0x98 RI ; /* UART 0 RX INTERRUPT FLAG */
-sbit at 0x99 TI0 ; /* UART 0 TX INTERRUPT FLAG */
-sbit at 0x99 TI ; /* UART 0 TX INTERRUPT FLAG */
-sbit at 0x9A RB80 ; /* UART 0 RX BIT 8 */
-sbit at 0x9B TB80 ; /* UART 0 TX BIT 8 */
-sbit at 0x9C REN0 ; /* UART 0 RX ENABLE */
-sbit at 0x9C REN ; /* UART 0 RX ENABLE */
-sbit at 0x9D SM20 ; /* UART 0 MULTIPROCESSOR EN */
-sbit at 0x9E SM10 ; /* UART 0 MODE 1 */
-sbit at 0x9F SM00 ; /* UART 0 MODE 0 */
-
-/* SCON1 0x98 */
-sbit at 0x98 RI1 ; /* UART 1 RX INTERRUPT FLAG */
-sbit at 0x99 TI1 ; /* UART 1 TX INTERRUPT FLAG */
-sbit at 0x9A RB81 ; /* UART 1 RX BIT 8 */
-sbit at 0x9B TB81 ; /* UART 1 TX BIT 8 */
-sbit at 0x9C REN1 ; /* UART 1 RX ENABLE */
-sbit at 0x9D MCE1 ; /* UART 1 MCE */
-sbit at 0x9F S1MODE ; /* UART 1 MODE */
-
-/* IE 0xA8 */
-sbit at 0xA8 EX0 ; /* EXTERNAL INTERRUPT 0 ENABLE */
-sbit at 0xA9 ET0 ; /* TIMER 0 INTERRUPT ENABLE */
-sbit at 0xAA EX1 ; /* EXTERNAL INTERRUPT 1 ENABLE */
-sbit at 0xAB ET1 ; /* TIMER 1 INTERRUPT ENABLE */
-sbit at 0xAC ES0 ; /* UART0 INTERRUPT ENABLE */
-sbit at 0xAC ES ; /* UART0 INTERRUPT ENABLE */
-sbit at 0xAD ET2 ; /* TIMER 2 INTERRUPT ENABLE */
-sbit at 0xAF EA ; /* GLOBAL INTERRUPT ENABLE */
-
-/* IP 0xB8 */
-sbit at 0xB8 PX0 ; /* EXTERNAL INTERRUPT 0 PRIORITY */
-sbit at 0xB9 PT0 ; /* TIMER 0 PRIORITY */
-sbit at 0xBA PX1 ; /* EXTERNAL INTERRUPT 1 PRIORITY */
-sbit at 0xBB PT1 ; /* TIMER 1 PRIORITY */
-sbit at 0xBC PS ; /* SERIAL PORT PRIORITY */
-sbit at 0xBD PT2 ; /* TIMER 2 PRIORITY */
-
-/* SMB0CN 0xC0 */
-sbit at 0xC0 SMBTOE ; /* SMBUS 0 TIMEOUT ENABLE */
-sbit at 0xC1 SMBFTE ; /* SMBUS 0 FREE TIMER ENABLE */
-sbit at 0xC2 AA ; /* SMBUS 0 ASSERT/ACKNOWLEDGE FLAG */
-sbit at 0xC3 SI ; /* SMBUS 0 INTERRUPT PENDING FLAG */
-sbit at 0xC4 STO ; /* SMBUS 0 STOP FLAG */
-sbit at 0xC5 STA ; /* SMBUS 0 START FLAG */
-sbit at 0xC6 ENSMB ; /* SMBUS 0 ENABLE */
-sbit at 0xC7 BUSY ; /* SMBUS 0 BUSY */
-
-/* TMR2CN 0xC8 */
-sbit at 0xC8 CPRL2 ; /* TIMER 2 CAPTURE SELECT */
-sbit at 0xC9 CT2 ; /* TIMER 2 COUNTER SELECT */
-sbit at 0xCA TR2 ; /* TIMER 2 ON/OFF CONTROL */
-sbit at 0xCB EXEN2 ; /* TIMER 2 EXTERNAL ENABLE FLAG */
-sbit at 0xCE EXF2 ; /* TIMER 2 EXTERNAL FLAG */
-sbit at 0xCF TF2 ; /* TIMER 2 OVERFLOW FLAG */
-
-/* TMR3CN 0xC8 */
-sbit at 0xC8 CPRL3 ; /* TIMER 3 CAPTURE SELECT */
-sbit at 0xC9 CT3 ; /* TIMER 3 COUNTER SELECT */
-sbit at 0xCA TR3 ; /* TIMER 3 ON/OFF CONTROL */
-sbit at 0xCB EXEN3 ; /* TIMER 3 EXTERNAL ENABLE FLAG */
-sbit at 0xCE EXF3 ; /* TIMER 3 EXTERNAL FLAG */
-sbit at 0xCF TF3 ; /* TIMER 3 OVERFLOW FLAG */
-
-/* TMR4CN 0xC8 */
-sbit at 0xC8 CPRL4 ; /* TIMER 4 CAPTURE SELECT */
-sbit at 0xC9 CT4 ; /* TIMER 4 COUNTER SELECT */
-sbit at 0xCA TR4 ; /* TIMER 4 ON/OFF CONTROL */
-sbit at 0xCB EXEN4 ; /* TIMER 4 EXTERNAL ENABLE FLAG */
-sbit at 0xCE EXF4 ; /* TIMER 4 EXTERNAL FLAG */
-sbit at 0xCF TF4 ; /* TIMER 4 OVERFLOW FLAG */
-
-/* P4 0xC8 */
-sbit at 0xC8 P4_0 ;
-sbit at 0xC9 P4_1 ;
-sbit at 0xCA P4_2 ;
-sbit at 0xCB P4_3 ;
-sbit at 0xCC P4_4 ;
-sbit at 0xCD P4_5 ;
-sbit at 0xCE P4_6 ;
-sbit at 0xCF P4_7 ;
-
-/* PSW 0xD0 */
-sbit at 0xD0 P ; /* ACCUMULATOR PARITY FLAG */
-sbit at 0xD1 F1 ; /* USER FLAG 1 */
-sbit at 0xD2 OV ; /* OVERFLOW FLAG */
-sbit at 0xD3 RS0 ; /* REGISTER BANK SELECT 0 */
-sbit at 0xD4 RS1 ; /* REGISTER BANK SELECT 1 */
-sbit at 0xD5 F0 ; /* USER FLAG 0 */
-sbit at 0xD6 AC ; /* AUXILIARY CARRY FLAG */
-sbit at 0xD7 CY ; /* CARRY FLAG */
-
-/* PCA0CN D8H */
-sbit at 0xD8 CCF0 ; /* PCA 0 MODULE 0 INTERRUPT FLAG */
-sbit at 0xD9 CCF1 ; /* PCA 0 MODULE 1 INTERRUPT FLAG */
-sbit at 0xDA CCF2 ; /* PCA 0 MODULE 2 INTERRUPT FLAG */
-sbit at 0xDB CCF3 ; /* PCA 0 MODULE 3 INTERRUPT FLAG */
-sbit at 0xDC CCF4 ; /* PCA 0 MODULE 4 INTERRUPT FLAG */
-sbit at 0xDD CCF5 ; /* PCA 0 MODULE 5 INTERRUPT FLAG */
-sbit at 0xDE CR ; /* PCA 0 COUNTER RUN CONTROL BIT */
-sbit at 0xDF CF ; /* PCA 0 COUNTER OVERFLOW FLAG */
-
-/* P5 0xD8 */
-sbit at 0xD8 P5_0 ;
-sbit at 0xD9 P5_1 ;
-sbit at 0xDA P5_2 ;
-sbit at 0xDB P5_3 ;
-sbit at 0xDC P5_4 ;
-sbit at 0xDD P5_5 ;
-sbit at 0xDE P5_6 ;
-sbit at 0xDF P5_7 ;
-
-/* ADC0CN E8H */
-sbit at 0xE8 AD0LJST ; /* ADC 0 RIGHT JUSTIFY DATA BIT */
-sbit at 0xE9 AD0WINT ; /* ADC 0 WINDOW INTERRUPT FLAG */
-sbit at 0xEA AD0CM0 ; /* ADC 0 CONVERT START MODE BIT 0 */
-sbit at 0xEB AD0CM1 ; /* ADC 0 CONVERT START MODE BIT 1 */
-sbit at 0xEC AD0BUSY ; /* ADC 0 BUSY FLAG */
-sbit at 0xED AD0INT ; /* ADC 0 EOC INTERRUPT FLAG */
-sbit at 0xEE AD0TM ; /* ADC 0 TRACK MODE */
-sbit at 0xEF AD0EN ; /* ADC 0 ENABLE */
-
-/* ADC2CN E8H */
-sbit at 0xE8 AD2WINT ; /* ADC 2 WINDOW INTERRUPT FLAG */
-sbit at 0xE9 AD2CM0 ; /* ADC 2 CONVERT START MODE BIT 0 */
-sbit at 0xEA AD2CM1 ; /* ADC 2 CONVERT START MODE BIT 1 */
-sbit at 0xEB AD2CM2 ; /* ADC 2 CONVERT START MODE BIT 2 */
-sbit at 0xEC AD2BUSY ; /* ADC 2 BUSY FLAG */
-sbit at 0xED AD2INT ; /* ADC 2 EOC INTERRUPT FLAG */
-sbit at 0xEE AD2TM ; /* ADC 2 TRACK MODE */
-sbit at 0xEF AD2EN ; /* ADC 2 ENABLE */
-
-/* P6 0xE8 */
-sbit at 0xE8 P6_0 ;
-sbit at 0xE9 P6_1 ;
-sbit at 0xEA P6_2 ;
-sbit at 0xEB P6_3 ;
-sbit at 0xEC P6_4 ;
-sbit at 0xED P6_5 ;
-sbit at 0xEE P6_6 ;
-sbit at 0xEF P6_7 ;
-
-/* SPI0CN F8H */
-sbit at 0xF8 SPIEN ; /* SPI 0 SPI ENABLE */
-sbit at 0xF9 TXBMT ; /* SPI 0 TX BUFFER EMPTY FLAG */
-sbit at 0xFA NSSMD0 ; /* SPI 0 SLAVE SELECT MODE 0 */
-sbit at 0xFB NSSMD1 ; /* SPI 0 SLAVE SELECT MODE 1 */
-sbit at 0xFC RXOVRN ; /* SPI 0 RX OVERRUN FLAG */
-sbit at 0xFD MODF ; /* SPI 0 MODE FAULT FLAG */
-sbit at 0xFE WCOL ; /* SPI 0 WRITE COLLISION FLAG */
-sbit at 0xFF SPIF ; /* SPI 0 INTERRUPT FLAG */
-
-/* P7 0xF8 */
-sbit at 0xF8 P7_0 ;
-sbit at 0xF9 P7_1 ;
-sbit at 0xFA P7_2 ;
-sbit at 0xFB P7_3 ;
-sbit at 0xFC P7_4 ;
-sbit at 0xFD P7_5 ;
-sbit at 0xFE P7_6 ;
-sbit at 0xFF P7_7 ;
-
-
-/* Predefined SFR Bit Masks */
-
-#define IDLE 0x01 /* PCON */
-#define STOP 0x02 /* PCON */
-#define ECCF 0x01 /* PCA0CPMn */
-#define PWM 0x02 /* PCA0CPMn */
-#define TOG 0x04 /* PCA0CPMn */
-#define MAT 0x08 /* PCA0CPMn */
-#define CAPN 0x10 /* PCA0CPMn */
-#define CAPP 0x20 /* PCA0CPMn */
-#define ECOM 0x40 /* PCA0CPMn */
-#define PWM16 0x80 /* PCA0CPMn */
-#define PORSF 0x02 /* RSTSRC */
-#define SWRSF 0x10 /* RSTSRC */
-
-
-/* SFR PAGE DEFINITIONS */
-
-#define CONFIG_PAGE 0x0F /* SYSTEM AND PORT CONFIGURATION PAGE */
-#define LEGACY_PAGE 0x00 /* LEGACY SFR PAGE */
-#define TIMER01_PAGE 0x00 /* TIMER 0 AND TIMER 1 */
-#define CPT0_PAGE 0x01 /* COMPARATOR 0 */
-#define CPT1_PAGE 0x02 /* COMPARATOR 1 */
-#define UART0_PAGE 0x00 /* UART 0 */
-#define UART1_PAGE 0x01 /* UART 1 */
-#define SPI0_PAGE 0x00 /* SPI 0 */
-#define EMI0_PAGE 0x00 /* EXTERNAL MEMORY INTERFACE */
-#define ADC0_PAGE 0x00 /* ADC 0 */
-#define ADC2_PAGE 0x02 /* ADC 2 */
-#define SMB0_PAGE 0x00 /* SMBUS 0 */
-#define TMR2_PAGE 0x00 /* TIMER 2 */
-#define TMR3_PAGE 0x01 /* TIMER 3 */
-#define TMR4_PAGE 0x02 /* TIMER 4 */
-#define DAC0_PAGE 0x00 /* DAC 0 */
-#define DAC1_PAGE 0x01 /* DAC 1 */
-#define PCA0_PAGE 0x00 /* PCA 0 */
-#define PLL0_PAGE 0x0F /* PLL 0 */
-
-#endif
+/*-------------------------------------------------------------------------\r
+ Register Declarations for the Cygnal C8051F12x Processor Range\r
+\r
+ Copyright (C) 2003 - Maarten Brock, sourceforge.brock@dse.nl\r
+\r
+ This library is free software; you can redistribute it and/or\r
+ modify it under the terms of the GNU Lesser General Public\r
+ License as published by the Free Software Foundation; either\r
+ version 2.1 of the License, or (at your option) any later version.\r
+\r
+ This library is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU\r
+ Lesser General Public License for more details.\r
+\r
+ You should have received a copy of the GNU Lesser General Public\r
+ License along with this library; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+-------------------------------------------------------------------------*/\r
+\r
+#ifndef C8051F120_H\r
+#define C8051F120_H\r
+\r
+\r
+/* BYTE Registers */\r
+\r
+/* All Pages */\r
+sfr at 0x80 P0 ; /* PORT 0 */\r
+sfr at 0x81 SP ; /* STACK POINTER */\r
+sfr at 0x82 DPL ; /* DATA POINTER - LOW BYTE */\r
+sfr at 0x83 DPH ; /* DATA POINTER - HIGH BYTE */\r
+sfr at 0x84 SFRPAGE ; /* SFR PAGE SELECT */\r
+sfr at 0x85 SFRNEXT ; /* SFR STACK NEXT PAGE */\r
+sfr at 0x86 SFRLAST ; /* SFR STACK LAST PAGE */\r
+sfr at 0x87 PCON ; /* POWER CONTROL */\r
+sfr at 0x90 P1 ; /* PORT 1 */\r
+sfr at 0xA0 P2 ; /* PORT 2 */\r
+sfr at 0xA8 IE ; /* INTERRUPT ENABLE */\r
+sfr at 0xB0 P3 ; /* PORT 3 */\r
+sfr at 0xB1 PSBANK ; /* FLASH BANK SELECT */\r
+sfr at 0xB8 IP ; /* INTERRUPT PRIORITY */\r
+sfr at 0xD0 PSW ; /* PROGRAM STATUS WORD */\r
+sfr at 0xE0 ACC ; /* ACCUMULATOR */\r
+sfr at 0xE6 EIE1 ; /* EXTERNAL INTERRUPT ENABLE 1 */\r
+sfr at 0xE7 EIE2 ; /* EXTERNAL INTERRUPT ENABLE 2 */\r
+sfr at 0xF0 B ; /* B REGISTER */\r
+sfr at 0xF6 EIP1 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */\r
+sfr at 0xF7 EIP2 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 2 */\r
+sfr at 0xFF WDTCN ; /* WATCHDOG TIMER CONTROL */\r
+\r
+/* Page 0x00 */\r
+sfr at 0x88 TCON ; /* TIMER CONTROL */\r
+sfr at 0x89 TMOD ; /* TIMER MODE */\r
+sfr at 0x8A TL0 ; /* TIMER 0 - LOW BYTE */\r
+sfr at 0x8B TL1 ; /* TIMER 1 - LOW BYTE */\r
+sfr at 0x8C TH0 ; /* TIMER 0 - HIGH BYTE */\r
+sfr at 0x8D TH1 ; /* TIMER 1 - HIGH BYTE */\r
+sfr at 0x8E CKCON ; /* TIMER 0/1 CLOCK CONTROL */\r
+sfr at 0x8F PSCTL ; /* FLASH WRITE/ERASE CONTROL */\r
+sfr at 0x91 SSTA0 ; /* UART 0 STATUS */\r
+sfr at 0x98 SCON0 ; /* UART 0 CONTROL */\r
+sfr at 0x98 SCON ; /* UART 0 CONTROL */\r
+sfr at 0x99 SBUF0 ; /* UART 0 BUFFER */\r
+sfr at 0x99 SBUF ; /* UART 0 BUFFER */\r
+sfr at 0x9A SPI0CFG ; /* SPI 0 CONFIGURATION */\r
+sfr at 0x9B SPI0DAT ; /* SPI 0 DATA */\r
+sfr at 0x9D SPI0CKR ; /* SPI 0 CLOCK RATE CONTROL */\r
+sfr at 0xA1 EMI0TC ; /* EMIF TIMING CONTROL */\r
+sfr at 0xA2 EMI0CN ; /* EMIF CONTROL */\r
+sfr at 0xA2 _XPAGE ; /* XDATA/PDATA PAGE */\r
+sfr at 0xA3 EMI0CF ; /* EMIF CONFIGURATION */\r
+sfr at 0xA9 SADDR0 ; /* UART 0 SLAVE ADDRESS */\r
+sfr at 0xB7 FLSCL ; /* FLASH SCALE */\r
+sfr at 0xB9 SADEN0 ; /* UART 0 SLAVE ADDRESS MASK */\r
+sfr at 0xBA AMX0CF ; /* ADC 0 MUX CONFIGURATION */\r
+sfr at 0xBB AMX0SL ; /* ADC 0 MUX CHANNEL SELECTION */\r
+sfr at 0xBC ADC0CF ; /* ADC 0 CONFIGURATION */\r
+sfr at 0xBE ADC0L ; /* ADC 0 DATA - LOW BYTE */\r
+sfr at 0xBF ADC0H ; /* ADC 0 DATA - HIGH BYTE */\r
+sfr at 0xC0 SMB0CN ; /* SMBUS 0 CONTROL */\r
+sfr at 0xC1 SMB0STA ; /* SMBUS 0 STATUS */\r
+sfr at 0xC2 SMB0DAT ; /* SMBUS 0 DATA */\r
+sfr at 0xC3 SMB0ADR ; /* SMBUS 0 SLAVE ADDRESS */\r
+sfr at 0xC4 ADC0GTL ; /* ADC 0 GREATER-THAN REGISTER - LOW BYTE */\r
+sfr at 0xC5 ADC0GTH ; /* ADC 0 GREATER-THAN REGISTER - HIGH BYTE */\r
+sfr at 0xC6 ADC0LTL ; /* ADC 0 LESS-THAN REGISTER - LOW BYTE */\r
+sfr at 0xC7 ADC0LTH ; /* ADC 0 LESS-THAN REGISTER - HIGH BYTE */\r
+sfr at 0xC8 TMR2CN ; /* TIMER 2 CONTROL */\r
+sfr at 0xC9 TMR2CF ; /* TIMER 2 CONFIGURATION */\r
+sfr at 0xCA RCAP2L ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */\r
+sfr at 0xCB RCAP2H ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */\r
+sfr at 0xCC TMR2L ; /* TIMER 2 - LOW BYTE */\r
+sfr at 0xCC TL2 ; /* TIMER 2 - LOW BYTE */\r
+sfr at 0xCD TMR2H ; /* TIMER 2 - HIGH BYTE */\r
+sfr at 0xCD TH2 ; /* TIMER 2 - HIGH BYTE */\r
+sfr at 0xCF SMB0CR ; /* SMBUS 0 CLOCK RATE */\r
+sfr at 0xD1 REF0CN ; /* VOLTAGE REFERENCE 0 CONTROL */\r
+sfr at 0xD2 DAC0L ; /* DAC 0 REGISTER - LOW BYTE */\r
+sfr at 0xD3 DAC0H ; /* DAC 0 REGISTER - HIGH BYTE */\r
+sfr at 0xD4 DAC0CN ; /* DAC 0 CONTROL */\r
+sfr at 0xD8 PCA0CN ; /* PCA 0 COUNTER CONTROL */\r
+sfr at 0xD9 PCA0MD ; /* PCA 0 COUNTER MODE */\r
+sfr at 0xDA PCA0CPM0 ; /* PCA 0 MODULE 0 CONTROL */\r
+sfr at 0xDB PCA0CPM1 ; /* PCA 0 MODULE 1 CONTROL */\r
+sfr at 0xDC PCA0CPM2 ; /* PCA 0 MODULE 2 CONTROL */\r
+sfr at 0xDD PCA0CPM3 ; /* PCA 0 MODULE 3 CONTROL */\r
+sfr at 0xDE PCA0CPM4 ; /* PCA 0 MODULE 4 CONTROL */\r
+sfr at 0xDF PCA0CPM5 ; /* PCA 0 MODULE 5 CONTROL */\r
+sfr at 0xE1 PCA0CPL5 ; /* PCA 0 MODULE 5 CAPTURE/COMPARE - LOW BYTE */\r
+sfr at 0xE2 PCA0CPH5 ; /* PCA 0 MODULE 5 CAPTURE/COMPARE - HIGH BYTE */\r
+sfr at 0xE8 ADC0CN ; /* ADC 0 CONTROL */\r
+sfr at 0xE9 PCA0CPL2 ; /* PCA 0 MODULE 2 CAPTURE/COMPARE - LOW BYTE */\r
+sfr at 0xEA PCA0CPH2 ; /* PCA 0 MODULE 2 CAPTURE/COMPARE - HIGH BYTE */\r
+sfr at 0xEB PCA0CPL3 ; /* PCA 0 MODULE 3 CAPTURE/COMPARE - LOW BYTE */\r
+sfr at 0xEC PCA0CPH3 ; /* PCA 0 MODULE 3 CAPTURE/COMPARE - HIGH BYTE */\r
+sfr at 0xED PCA0CPL4 ; /* PCA 0 MODULE 4 CAPTURE/COMPARE - LOW BYTE */\r
+sfr at 0xEE PCA0CPH4 ; /* PCA 0 MODULE 4 CAPTURE/COMPARE - HIGH BYTE */\r
+sfr at 0xEF RSTSRC ; /* RESET SOURCE */\r
+sfr at 0xF8 SPI0CN ; /* SPI 0 CONTROL */\r
+sfr at 0xF9 PCA0L ; /* PCA 0 TIMER - LOW BYTE */\r
+sfr at 0xFA PCA0H ; /* PCA 0 TIMER - HIGH BYTE */\r
+sfr at 0xFB PCA0CPL0 ; /* PCA 0 MODULE 0 CAPTURE/COMPARE - LOW BYTE */\r
+sfr at 0xFC PCA0CPH0 ; /* PCA 0 MODULE 0 CAPTURE/COMPARE - HIGH BYTE */\r
+sfr at 0xFD PCA0CPL1 ; /* PCA 0 MODULE 1 CAPTURE/COMPARE - LOW BYTE */\r
+sfr at 0xFE PCA0CPH1 ; /* PCA 0 MODULE 1 CAPTURE/COMPARE - HIGH BYTE */\r
+\r
+/* Page 0x01 */\r
+sfr at 0x88 CPT0CN ; /* COMPARATOR 0 CONTROL */\r
+sfr at 0x89 CPT0MD ; /* COMPARATOR 0 CONFIGURATION */\r
+sfr at 0x98 SCON1 ; /* UART 1 CONTROL */\r
+sfr at 0x99 SBUF1 ; /* UART 1 BUFFER */\r
+sfr at 0xC8 TMR3CN ; /* TIMER 3 CONTROL */\r
+sfr at 0xC9 TMR3CF ; /* TIMER 3 CONFIGURATION */\r
+sfr at 0xCA RCAP3L ; /* TIMER 3 CAPTURE REGISTER - LOW BYTE */\r
+sfr at 0xCB RCAP3H ; /* TIMER 3 CAPTURE REGISTER - HIGH BYTE */\r
+sfr at 0xCC TMR3L ; /* TIMER 3 - LOW BYTE */\r
+sfr at 0xCD TMR3H ; /* TIMER 3 - HIGH BYTE */\r
+sfr at 0xD2 DAC1L ; /* DAC 1 REGISTER - LOW BYTE */\r
+sfr at 0xD3 DAC1H ; /* DAC 1 REGISTER - HIGH BYTE */\r
+sfr at 0xD4 DAC1CN ; /* DAC 1 CONTROL */\r
+\r
+/* Page 0x02 */\r
+sfr at 0x88 CPT1CN ; /* COMPARATOR 1 CONTROL */\r
+sfr at 0x89 CPT1MD ; /* COMPARATOR 1 CONFIGURATION */\r
+sfr at 0xBA AMX2CF ; /* ADC 2 MUX CONFIGURATION */\r
+sfr at 0xBB AMX2SL ; /* ADC 2 MUX CHANNEL SELECTION */\r
+sfr at 0xBC ADC2CF ; /* ADC 2 CONFIGURATION */\r
+sfr at 0xBE ADC2 ; /* ADC 2 DATA */\r
+sfr at 0xC4 ADC2GT ; /* ADC 2 GREATER-THAN REGISTER */\r
+sfr at 0xC6 ADC2LT ; /* ADC 2 LESS-THAN REGISTER */\r
+sfr at 0xC8 TMR4CN ; /* TIMER 4 CONTROL */\r
+sfr at 0xC9 TMR4CF ; /* TIMER 4 CONFIGURATION */\r
+sfr at 0xCA RCAP4L ; /* TIMER 4 CAPTURE REGISTER - LOW BYTE */\r
+sfr at 0xCB RCAP4H ; /* TIMER 4 CAPTURE REGISTER - HIGH BYTE */\r
+sfr at 0xCC TMR4L ; /* TIMER 4 - LOW BYTE */\r
+sfr at 0xCD TMR4H ; /* TIMER 4 - HIGH BYTE */\r
+\r
+/* Page 0x02 */\r
+sfr at 0x91 MAC0BL ; /* MAC0 B Register Low Byte */\r
+sfr at 0x92 MAC0BH ; /* MAC0 B Register High Byte */\r
+sfr at 0x93 MAC0ACC0 ; /* MAC0 Accumulator Byte 0 (LSB) */\r
+sfr at 0x94 MAC0ACC1 ; /* MAC0 Accumulator Byte 1 */\r
+sfr at 0x95 MAC0ACC2 ; /* MAC0 Accumulator Byte 2 */\r
+sfr at 0x96 MAC0ACC3 ; /* MAC0 Accumulator Byte 3 (MSB) */\r
+sfr at 0x97 MAC0OVR ; /* MAC0 Accumulator Overflow */\r
+sfr at 0xC0 MAC0STA ; /* MAC0 Status Register */\r
+sfr at 0xC1 MAC0AL ; /* MAC0 A Register Low Byte */\r
+sfr at 0xC2 MAC0AH ; /* MAC0 A Register High Byte */\r
+sfr at 0xC3 MAC0CF ; /* MAC0 Configuration */\r
+sfr at 0xCE MAC0RNDL ; /* MAC0 Rounding Register Low Byte */\r
+sfr at 0xCF MAC0RNDH ; /* MAC0 Rounding Register High Byte */\r
+\r
+/* Page 0x0F */\r
+sfr at 0x88 FLSTAT ; /* FLASH STATUS */\r
+sfr at 0x89 PLL0CN ; /* PLL 0 CONTROL */\r
+sfr at 0x8A OSCICN ; /* INTERNAL OSCILLATOR CONTROL */\r
+sfr at 0x8B OSCICL ; /* INTERNAL OSCILLATOR CALIBRATION */\r
+sfr at 0x8C OSCXCN ; /* EXTERNAL OSCILLATOR CONTROL */\r
+sfr at 0x8D PLL0DIV ; /* PLL 0 DIVIDER */\r
+sfr at 0x8E PLL0MUL ; /* PLL 0 MULTIPLIER */\r
+sfr at 0x8F PLL0FLT ; /* PLL 0 FILTER */\r
+sfr at 0x96 SFRPGCN ; /* SFR PAGE CONTROL */\r
+sfr at 0x97 CLKSEL ; /* SYSTEM CLOCK SELECT */\r
+sfr at 0x9A CCH0MA ; /* CACHE MISS ACCUMULATOR */\r
+sfr at 0x9C P4MDOUT ; /* PORT 4 OUTPUT MODE */\r
+sfr at 0x9D P5MDOUT ; /* PORT 5 OUTPUT MODE */\r
+sfr at 0x9E P6MDOUT ; /* PORT 6 OUTPUT MODE */\r
+sfr at 0x9F P7MDOUT ; /* PORT 7 OUTPUT MODE */\r
+sfr at 0xA1 CCH0CN ; /* CACHE CONTROL */\r
+sfr at 0xA2 CCH0TN ; /* CACHE TUNING REGISTER */\r
+sfr at 0xA3 CCH0LC ; /* CACHE LOCK */\r
+sfr at 0xA4 P0MDOUT ; /* PORT 0 OUTPUT MODE */\r
+sfr at 0xA5 P1MDOUT ; /* PORT 1 OUTPUT MODE */\r
+sfr at 0xA6 P2MDOUT ; /* PORT 2 OUTPUT MODE CONFIGURATION */\r
+sfr at 0xA7 P3MDOUT ; /* PORT 3 OUTPUT MODE CONFIGURATION */\r
+sfr at 0xAD P1MDIN ; /* PORT 1 INPUT MODE */\r
+sfr at 0xB7 FLACL ; /* FLASH ACCESS LIMIT */\r
+sfr at 0xC8 P4 ; /* PORT 4 */\r
+sfr at 0xD8 P5 ; /* PORT 5 */\r
+sfr at 0xE1 XBR0 ; /* CROSSBAR CONFIGURATION REGISTER 0 */\r
+sfr at 0xE2 XBR1 ; /* CROSSBAR CONFIGURATION REGISTER 1 */\r
+sfr at 0xE3 XBR2 ; /* CROSSBAR CONFIGURATION REGISTER 2 */\r
+sfr at 0xE8 ADC2CN ; /* ADC 2 CONTROL */\r
+sfr at 0xE8 P6 ; /* PORT 6 */\r
+sfr at 0xF8 P7 ; /* PORT 7 */\r
+\r
+\r
+/* BIT Registers */\r
+\r
+/* P0 0x80 */\r
+sbit at 0x80 P0_0 ;\r
+sbit at 0x81 P0_1 ;\r
+sbit at 0x82 P0_2 ;\r
+sbit at 0x83 P0_3 ;\r
+sbit at 0x84 P0_4 ;\r
+sbit at 0x85 P0_5 ;\r
+sbit at 0x86 P0_6 ;\r
+sbit at 0x87 P0_7 ;\r
+\r
+/* TCON 0x88 */\r
+sbit at 0x88 IT0 ; /* EXT. INTERRUPT 0 TYPE */\r
+sbit at 0x89 IE0 ; /* EXT. INTERRUPT 0 EDGE FLAG */\r
+sbit at 0x8A IT1 ; /* EXT. INTERRUPT 1 TYPE */\r
+sbit at 0x8B IE1 ; /* EXT. INTERRUPT 1 EDGE FLAG */\r
+sbit at 0x8C TR0 ; /* TIMER 0 ON/OFF CONTROL */\r
+sbit at 0x8D TF0 ; /* TIMER 0 OVERFLOW FLAG */\r
+sbit at 0x8E TR1 ; /* TIMER 1 ON/OFF CONTROL */\r
+sbit at 0x8F TF1 ; /* TIMER 1 OVERFLOW FLAG */\r
+\r
+/* CPT0CN 0x88 */\r
+sbit at 0x88 CP0HYN0 ; /* COMPARATOR 0 NEGATIVE HYSTERESIS 0 */\r
+sbit at 0x89 CP0HYN1 ; /* COMPARATOR 0 NEGATIVE HYSTERESIS 1 */\r
+sbit at 0x8A CP0HYP0 ; /* COMPARATOR 0 POSITIVE HYSTERESIS 0 */\r
+sbit at 0x8B CP0HYP1 ; /* COMPARATOR 0 POSITIVE HYSTERESIS 1 */\r
+sbit at 0x8C CP0FIF ; /* COMPARATOR 0 FALLING EDGE INTERRUPT */\r
+sbit at 0x8D CP0RIF ; /* COMPARATOR 0 RISING EDGE INTERRUPT */\r
+sbit at 0x8E CP0OUT ; /* COMPARATOR 0 OUTPUT */\r
+sbit at 0x8F CP0EN ; /* COMPARATOR 0 ENABLE */\r
+\r
+/* CPT1CN 0x88 */\r
+sbit at 0x88 CP1HYN0 ; /* COMPARATOR 1 NEGATIVE HYSTERESIS 0 */\r
+sbit at 0x89 CP1HYN1 ; /* COMPARATOR 1 NEGATIVE HYSTERESIS 1 */\r
+sbit at 0x8A CP1HYP0 ; /* COMPARATOR 1 POSITIVE HYSTERESIS 0 */\r
+sbit at 0x8B CP1HYP1 ; /* COMPARATOR 1 POSITIVE HYSTERESIS 1 */\r
+sbit at 0x8C CP1FIF ; /* COMPARATOR 1 FALLING EDGE INTERRUPT */\r
+sbit at 0x8D CP1RIF ; /* COMPARATOR 1 RISING EDGE INTERRUPT */\r
+sbit at 0x8E CP1OUT ; /* COMPARATOR 1 OUTPUT */\r
+sbit at 0x8F CP1EN ; /* COMPARATOR 1 ENABLE */\r
+\r
+/* FLSTAT 0x88 */\r
+sbit at 0x88 FLHBUSY ; /* FLASH BUSY */\r
+\r
+/* SCON0 0x98 */\r
+sbit at 0x98 RI0 ; /* UART 0 RX INTERRUPT FLAG */\r
+sbit at 0x98 RI ; /* UART 0 RX INTERRUPT FLAG */\r
+sbit at 0x99 TI0 ; /* UART 0 TX INTERRUPT FLAG */\r
+sbit at 0x99 TI ; /* UART 0 TX INTERRUPT FLAG */\r
+sbit at 0x9A RB80 ; /* UART 0 RX BIT 8 */\r
+sbit at 0x9B TB80 ; /* UART 0 TX BIT 8 */\r
+sbit at 0x9C REN0 ; /* UART 0 RX ENABLE */\r
+sbit at 0x9C REN ; /* UART 0 RX ENABLE */\r
+sbit at 0x9D SM20 ; /* UART 0 MULTIPROCESSOR EN */\r
+sbit at 0x9E SM10 ; /* UART 0 MODE 1 */\r
+sbit at 0x9F SM00 ; /* UART 0 MODE 0 */\r
+\r
+/* SCON1 0x98 */\r
+sbit at 0x98 RI1 ; /* UART 1 RX INTERRUPT FLAG */\r
+sbit at 0x99 TI1 ; /* UART 1 TX INTERRUPT FLAG */\r
+sbit at 0x9A RB81 ; /* UART 1 RX BIT 8 */\r
+sbit at 0x9B TB81 ; /* UART 1 TX BIT 8 */\r
+sbit at 0x9C REN1 ; /* UART 1 RX ENABLE */\r
+sbit at 0x9D MCE1 ; /* UART 1 MCE */\r
+sbit at 0x9F S1MODE ; /* UART 1 MODE */\r
+\r
+/* IE 0xA8 */\r
+sbit at 0xA8 EX0 ; /* EXTERNAL INTERRUPT 0 ENABLE */\r
+sbit at 0xA9 ET0 ; /* TIMER 0 INTERRUPT ENABLE */\r
+sbit at 0xAA EX1 ; /* EXTERNAL INTERRUPT 1 ENABLE */\r
+sbit at 0xAB ET1 ; /* TIMER 1 INTERRUPT ENABLE */\r
+sbit at 0xAC ES0 ; /* UART0 INTERRUPT ENABLE */\r
+sbit at 0xAC ES ; /* UART0 INTERRUPT ENABLE */\r
+sbit at 0xAD ET2 ; /* TIMER 2 INTERRUPT ENABLE */\r
+sbit at 0xAF EA ; /* GLOBAL INTERRUPT ENABLE */\r
+\r
+/* IP 0xB8 */\r
+sbit at 0xB8 PX0 ; /* EXTERNAL INTERRUPT 0 PRIORITY */\r
+sbit at 0xB9 PT0 ; /* TIMER 0 PRIORITY */\r
+sbit at 0xBA PX1 ; /* EXTERNAL INTERRUPT 1 PRIORITY */\r
+sbit at 0xBB PT1 ; /* TIMER 1 PRIORITY */\r
+sbit at 0xBC PS ; /* SERIAL PORT PRIORITY */\r
+sbit at 0xBD PT2 ; /* TIMER 2 PRIORITY */\r
+\r
+/* SMB0CN 0xC0 */\r
+sbit at 0xC0 SMBTOE ; /* SMBUS 0 TIMEOUT ENABLE */\r
+sbit at 0xC1 SMBFTE ; /* SMBUS 0 FREE TIMER ENABLE */\r
+sbit at 0xC2 AA ; /* SMBUS 0 ASSERT/ACKNOWLEDGE FLAG */\r
+sbit at 0xC3 SI ; /* SMBUS 0 INTERRUPT PENDING FLAG */\r
+sbit at 0xC4 STO ; /* SMBUS 0 STOP FLAG */\r
+sbit at 0xC5 STA ; /* SMBUS 0 START FLAG */\r
+sbit at 0xC6 ENSMB ; /* SMBUS 0 ENABLE */\r
+sbit at 0xC7 BUSY ; /* SMBUS 0 BUSY */\r
+\r
+/* TMR2CN 0xC8 */\r
+sbit at 0xC8 CPRL2 ; /* TIMER 2 CAPTURE SELECT */\r
+sbit at 0xC9 CT2 ; /* TIMER 2 COUNTER SELECT */\r
+sbit at 0xCA TR2 ; /* TIMER 2 ON/OFF CONTROL */\r
+sbit at 0xCB EXEN2 ; /* TIMER 2 EXTERNAL ENABLE FLAG */\r
+sbit at 0xCE EXF2 ; /* TIMER 2 EXTERNAL FLAG */\r
+sbit at 0xCF TF2 ; /* TIMER 2 OVERFLOW FLAG */\r
+\r
+/* TMR3CN 0xC8 */\r
+sbit at 0xC8 CPRL3 ; /* TIMER 3 CAPTURE SELECT */\r
+sbit at 0xC9 CT3 ; /* TIMER 3 COUNTER SELECT */\r
+sbit at 0xCA TR3 ; /* TIMER 3 ON/OFF CONTROL */\r
+sbit at 0xCB EXEN3 ; /* TIMER 3 EXTERNAL ENABLE FLAG */\r
+sbit at 0xCE EXF3 ; /* TIMER 3 EXTERNAL FLAG */\r
+sbit at 0xCF TF3 ; /* TIMER 3 OVERFLOW FLAG */\r
+\r
+/* TMR4CN 0xC8 */\r
+sbit at 0xC8 CPRL4 ; /* TIMER 4 CAPTURE SELECT */\r
+sbit at 0xC9 CT4 ; /* TIMER 4 COUNTER SELECT */\r
+sbit at 0xCA TR4 ; /* TIMER 4 ON/OFF CONTROL */\r
+sbit at 0xCB EXEN4 ; /* TIMER 4 EXTERNAL ENABLE FLAG */\r
+sbit at 0xCE EXF4 ; /* TIMER 4 EXTERNAL FLAG */\r
+sbit at 0xCF TF4 ; /* TIMER 4 OVERFLOW FLAG */\r
+\r
+/* P4 0xC8 */\r
+sbit at 0xC8 P4_0 ;\r
+sbit at 0xC9 P4_1 ;\r
+sbit at 0xCA P4_2 ;\r
+sbit at 0xCB P4_3 ;\r
+sbit at 0xCC P4_4 ;\r
+sbit at 0xCD P4_5 ;\r
+sbit at 0xCE P4_6 ;\r
+sbit at 0xCF P4_7 ;\r
+\r
+/* PSW 0xD0 */\r
+sbit at 0xD0 P ; /* ACCUMULATOR PARITY FLAG */\r
+sbit at 0xD1 F1 ; /* USER FLAG 1 */\r
+sbit at 0xD2 OV ; /* OVERFLOW FLAG */\r
+sbit at 0xD3 RS0 ; /* REGISTER BANK SELECT 0 */\r
+sbit at 0xD4 RS1 ; /* REGISTER BANK SELECT 1 */\r
+sbit at 0xD5 F0 ; /* USER FLAG 0 */\r
+sbit at 0xD6 AC ; /* AUXILIARY CARRY FLAG */\r
+sbit at 0xD7 CY ; /* CARRY FLAG */\r
+\r
+/* PCA0CN D8H */\r
+sbit at 0xD8 CCF0 ; /* PCA 0 MODULE 0 INTERRUPT FLAG */\r
+sbit at 0xD9 CCF1 ; /* PCA 0 MODULE 1 INTERRUPT FLAG */\r
+sbit at 0xDA CCF2 ; /* PCA 0 MODULE 2 INTERRUPT FLAG */\r
+sbit at 0xDB CCF3 ; /* PCA 0 MODULE 3 INTERRUPT FLAG */\r
+sbit at 0xDC CCF4 ; /* PCA 0 MODULE 4 INTERRUPT FLAG */\r
+sbit at 0xDD CCF5 ; /* PCA 0 MODULE 5 INTERRUPT FLAG */\r
+sbit at 0xDE CR ; /* PCA 0 COUNTER RUN CONTROL BIT */\r
+sbit at 0xDF CF ; /* PCA 0 COUNTER OVERFLOW FLAG */\r
+\r
+/* P5 0xD8 */\r
+sbit at 0xD8 P5_0 ;\r
+sbit at 0xD9 P5_1 ;\r
+sbit at 0xDA P5_2 ;\r
+sbit at 0xDB P5_3 ;\r
+sbit at 0xDC P5_4 ;\r
+sbit at 0xDD P5_5 ;\r
+sbit at 0xDE P5_6 ;\r
+sbit at 0xDF P5_7 ;\r
+\r
+/* ADC0CN E8H */\r
+sbit at 0xE8 AD0LJST ; /* ADC 0 RIGHT JUSTIFY DATA BIT */\r
+sbit at 0xE9 AD0WINT ; /* ADC 0 WINDOW INTERRUPT FLAG */\r
+sbit at 0xEA AD0CM0 ; /* ADC 0 CONVERT START MODE BIT 0 */\r
+sbit at 0xEB AD0CM1 ; /* ADC 0 CONVERT START MODE BIT 1 */\r
+sbit at 0xEC AD0BUSY ; /* ADC 0 BUSY FLAG */\r
+sbit at 0xED AD0INT ; /* ADC 0 EOC INTERRUPT FLAG */\r
+sbit at 0xEE AD0TM ; /* ADC 0 TRACK MODE */\r
+sbit at 0xEF AD0EN ; /* ADC 0 ENABLE */\r
+\r
+/* ADC2CN E8H */\r
+sbit at 0xE8 AD2WINT ; /* ADC 2 WINDOW INTERRUPT FLAG */\r
+sbit at 0xE9 AD2CM0 ; /* ADC 2 CONVERT START MODE BIT 0 */\r
+sbit at 0xEA AD2CM1 ; /* ADC 2 CONVERT START MODE BIT 1 */\r
+sbit at 0xEB AD2CM2 ; /* ADC 2 CONVERT START MODE BIT 2 */\r
+sbit at 0xEC AD2BUSY ; /* ADC 2 BUSY FLAG */\r
+sbit at 0xED AD2INT ; /* ADC 2 EOC INTERRUPT FLAG */\r
+sbit at 0xEE AD2TM ; /* ADC 2 TRACK MODE */\r
+sbit at 0xEF AD2EN ; /* ADC 2 ENABLE */\r
+\r
+/* P6 0xE8 */\r
+sbit at 0xE8 P6_0 ;\r
+sbit at 0xE9 P6_1 ;\r
+sbit at 0xEA P6_2 ;\r
+sbit at 0xEB P6_3 ;\r
+sbit at 0xEC P6_4 ;\r
+sbit at 0xED P6_5 ;\r
+sbit at 0xEE P6_6 ;\r
+sbit at 0xEF P6_7 ;\r
+\r
+/* SPI0CN F8H */\r
+sbit at 0xF8 SPIEN ; /* SPI 0 SPI ENABLE */\r
+sbit at 0xF9 TXBMT ; /* SPI 0 TX BUFFER EMPTY FLAG */\r
+sbit at 0xFA NSSMD0 ; /* SPI 0 SLAVE SELECT MODE 0 */\r
+sbit at 0xFB NSSMD1 ; /* SPI 0 SLAVE SELECT MODE 1 */\r
+sbit at 0xFC RXOVRN ; /* SPI 0 RX OVERRUN FLAG */\r
+sbit at 0xFD MODF ; /* SPI 0 MODE FAULT FLAG */\r
+sbit at 0xFE WCOL ; /* SPI 0 WRITE COLLISION FLAG */\r
+sbit at 0xFF SPIF ; /* SPI 0 INTERRUPT FLAG */\r
+\r
+/* P7 0xF8 */\r
+sbit at 0xF8 P7_0 ;\r
+sbit at 0xF9 P7_1 ;\r
+sbit at 0xFA P7_2 ;\r
+sbit at 0xFB P7_3 ;\r
+sbit at 0xFC P7_4 ;\r
+sbit at 0xFD P7_5 ;\r
+sbit at 0xFE P7_6 ;\r
+sbit at 0xFF P7_7 ;\r
+\r
+\r
+/* Predefined SFR Bit Masks */\r
+\r
+#define IDLE 0x01 /* PCON */\r
+#define STOP 0x02 /* PCON */\r
+#define ECCF 0x01 /* PCA0CPMn */\r
+#define PWM 0x02 /* PCA0CPMn */\r
+#define TOG 0x04 /* PCA0CPMn */\r
+#define MAT 0x08 /* PCA0CPMn */\r
+#define CAPN 0x10 /* PCA0CPMn */\r
+#define CAPP 0x20 /* PCA0CPMn */\r
+#define ECOM 0x40 /* PCA0CPMn */\r
+#define PWM16 0x80 /* PCA0CPMn */\r
+#define PORSF 0x02 /* RSTSRC */\r
+#define SWRSF 0x10 /* RSTSRC */\r
+\r
+\r
+/* SFR PAGE DEFINITIONS */\r
+\r
+#define CONFIG_PAGE 0x0F /* SYSTEM AND PORT CONFIGURATION PAGE */\r
+#define LEGACY_PAGE 0x00 /* LEGACY SFR PAGE */\r
+#define TIMER01_PAGE 0x00 /* TIMER 0 AND TIMER 1 */\r
+#define CPT0_PAGE 0x01 /* COMPARATOR 0 */\r
+#define CPT1_PAGE 0x02 /* COMPARATOR 1 */\r
+#define UART0_PAGE 0x00 /* UART 0 */\r
+#define UART1_PAGE 0x01 /* UART 1 */\r
+#define SPI0_PAGE 0x00 /* SPI 0 */\r
+#define EMI0_PAGE 0x00 /* EXTERNAL MEMORY INTERFACE */\r
+#define ADC0_PAGE 0x00 /* ADC 0 */\r
+#define ADC2_PAGE 0x02 /* ADC 2 */\r
+#define SMB0_PAGE 0x00 /* SMBUS 0 */\r
+#define TMR2_PAGE 0x00 /* TIMER 2 */\r
+#define TMR3_PAGE 0x01 /* TIMER 3 */\r
+#define TMR4_PAGE 0x02 /* TIMER 4 */\r
+#define DAC0_PAGE 0x00 /* DAC 0 */\r
+#define DAC1_PAGE 0x01 /* DAC 1 */\r
+#define PCA0_PAGE 0x00 /* PCA 0 */\r
+#define PLL0_PAGE 0x0F /* PLL 0 */\r
+\r
+#endif\r
/*\r
- FreeRTOS.org V4.2.1 - Copyright (C) 2003-2007 Richard Barry.\r
+ FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.2.1 - Copyright (C) 2003-2007 Richard Barry.\r
+ FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.2.1 - Copyright (C) 2003-2007 Richard Barry.\r
+ FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.2.1 - Copyright (C) 2003-2007 Richard Barry.\r
+ FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.2.1 - Copyright (C) 2003-2007 Richard Barry.\r
+ FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.2.1 - Copyright (C) 2003-2007 Richard Barry.\r
+ FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.2.1 - Copyright (C) 2003-2007 Richard Barry.\r
+ FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.2.1 - Copyright (C) 2003-2007 Richard Barry.\r
+ FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.2.1 - Copyright (C) 2003-2007 Richard Barry.\r
+ FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.2.1 - Copyright (C) 2003-2007 Richard Barry.\r
+ FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.2.1 - Copyright (C) 2003-2007 Richard Barry.\r
+ FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.2.1 - Copyright (C) 2003-2007 Richard Barry.\r
+ FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.2.1 - Copyright (C) 2003-2007 Richard Barry.\r
+ FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.2.1 - Copyright (C) 2003-2007 Richard Barry.\r
+ FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
\r
/*\r
- FreeRTOS.org V4.2.1 - Copyright (C) 2003-2007 Richard Barry.\r
+ FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.2.1 - Copyright (C) 2003-2007 Richard Barry.\r
+ FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.2.1 - Copyright (C) 2003-2007 Richard Barry.\r
+ FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.2.1 - Copyright (C) 2003-2007 Richard Barry.\r
+ FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.2.1 - Copyright (C) 2003-2007 Richard Barry.\r
+ FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.2.1 - Copyright (C) 2003-2007 Richard Barry.\r
+ FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.2.1 - Copyright (C) 2003-2007 Richard Barry.\r
+ FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.2.1 - Copyright (C) 2003-2007 Richard Barry.\r
+ FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
\r
/*\r
- FreeRTOS.org V4.2.1 - Copyright (C) 2003-2007 Richard Barry.\r
+ FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.2.1 - Copyright (C) 2003-2007 Richard Barry.\r
+ FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.2.1 - Copyright (C) 2003-2007 Richard Barry.\r
+ FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
#define INCLUDE_vTaskDelay 1\r
\r
\r
+#define configKERNEL_INTERRUPT_PRIORITY 0x01\r
+\r
#endif /* FREERTOS_CONFIG_H */\r
/*\r
- FreeRTOS.org V4.2.1 - Copyright (C) 2003-2007 Richard Barry.\r
+ FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
file_017=no\r
file_018=no\r
file_019=no\r
+file_020=no\r
+file_021=no\r
[FILE_INFO]\r
file_000=main.c\r
file_001=..\..\source\list.c\r
file_011=..\Common\Minimal\integer.c\r
file_012=..\Common\Minimal\comtest.c\r
file_013=serial\serial.c\r
-file_014=..\..\source\include\semphr.h\r
-file_015=..\..\source\include\task.h\r
-file_016=..\..\source\include\croutine.h\r
-file_017=..\..\source\include\queue.h\r
-file_018=FreeRTOSConfig.h\r
-file_019=p33FJ256GP710.gld\r
+file_014=timertest.c\r
+file_015=lcd.c\r
+file_016=..\..\source\include\semphr.h\r
+file_017=..\..\source\include\task.h\r
+file_018=..\..\source\include\croutine.h\r
+file_019=..\..\source\include\queue.h\r
+file_020=FreeRTOSConfig.h\r
+file_021=p33FJ256GP710.gld\r
[SUITE_INFO]\r
suite_guid={479DDE59-4D56-455E-855E-FFF59A3DB57E}\r
suite_state=\r
TS{25AC22BD-2378-4FDB-BFB6-7345A15512D3}=-g -Wall -DMPLAB_DSPIC_PORT -O2 -fomit-frame-pointer -fno-schedule-insns -fno-schedule-insns2\r
TS{7DAC9A1D-4C45-45D6-B25A-D117C74E8F5A}=--defsym=__ICD2RAM=1 -Map="$(TARGETBASE).map" -o"$(TARGETBASE).$(TARGETSUFFIX)"\r
TS{509E5861-1E2A-483B-8B6B-CA8DB7F2DD78}=\r
+[INSTRUMENTED_TRACE]\r
+enable=0\r
+transport=0\r
+format=0\r
--- /dev/null
+/*\r
+ FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS.org distribution.\r
+\r
+ FreeRTOS.org is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS.org is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS.org; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS.org, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+\r
+ Also see http://www.SafeRTOS.com for an IEC 61508 compliant version along\r
+ with commercial development and support options.\r
+ ***************************************************************************\r
+*/\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "queue.h"\r
+\r
+/* Demo includes. */\r
+#include "lcd.h"\r
+\r
+/*\r
+ * The LCD is written to by more than one task so is controlled by this\r
+ * 'gatekeeper' task. This is the only task that is actually permitted to\r
+ * access the LCD directly. Other tasks wanting to display a message send\r
+ * the message to the gatekeeper.\r
+ */\r
+static void vLCDTask( void *pvParameters );\r
+\r
+/*\r
+ * Setup the peripherals required to communicate with the LCD.\r
+ */\r
+static void prvSetupLCD( void );\r
+\r
+/* \r
+ * Move to the first (0) or second (1) row of the LCD. \r
+ */\r
+static void prvLCDGotoRow( unsigned portSHORT usRow );\r
+\r
+/* \r
+ * Write a string of text to the LCD. \r
+ */\r
+static void prvLCDPutString( portCHAR *pcString );\r
+\r
+/* \r
+ * Clear the LCD. \r
+ */\r
+static void prvLCDClear( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Brief delay to permit the LCD to catch up with commands. */\r
+#define lcdVERY_SHORT_DELAY ( 1 )\r
+#define lcdSHORT_DELAY ( 4 / portTICK_RATE_MS )\r
+#define lcdLONG_DELAY ( 15 / portTICK_RATE_MS )\r
+\r
+/* LCD commands. */\r
+#define lcdCLEAR ( 0x01 )\r
+#define lcdHOME ( 0x02 )\r
+#define lcdLINE2 ( 0xc0 )\r
+\r
+/* SFR that seems to be missing from the standard header files. */\r
+#define PMAEN *( ( unsigned short * ) 0x60c )\r
+\r
+/* LCD R/W signal. */\r
+#define lcdRW LATDbits.LATD5 \r
+\r
+/* LCD lcdRS signal. */\r
+#define lcdRS LATBbits.LATB15 \r
+\r
+/* LCD lcdE signal . */\r
+#define lcdE LATDbits.LATD4 \r
+\r
+/* Control signal pin direction. */\r
+#define RW_TRIS TRISDbits.TRISD5 \r
+#define RS_TRIS TRISBbits.TRISB15\r
+#define E_TRIS TRISDbits.TRISD4\r
+\r
+/* Port for LCD data */\r
+#define lcdDATA LATE \r
+#define lcdDATAPORT PORTE\r
+\r
+/* I/O setup for data Port. */\r
+#define TRISDATA TRISE \r
+\r
+/* The length of the queue used to send messages to the LCD gatekeeper task. */\r
+#define lcdQUEUE_SIZE 3\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The queue used to send messages to the LCD task. */\r
+xQueueHandle xLCDQueue;\r
+\r
+static void prvLCDCommand( portCHAR cCommand );\r
+static void prvLCDData( portCHAR cChar );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+xQueueHandle xStartLCDTask( void )\r
+{\r
+ /* Create the queue used by the LCD task. Messages for display on the LCD\r
+ are received via this queue. */\r
+ xLCDQueue = xQueueCreate( lcdQUEUE_SIZE, sizeof( xLCDMessage ) );\r
+\r
+ /* Start the task that will write to the LCD. The LCD hardware is\r
+ initialised from within the task itself so delays can be used. */\r
+ xTaskCreate( vLCDTask, ( signed portCHAR * ) "LCD", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY + 1, NULL );\r
+\r
+ return xLCDQueue;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvLCDGotoRow( unsigned portSHORT usRow )\r
+{\r
+ if( usRow == 0 )\r
+ {\r
+ prvLCDCommand( lcdHOME );\r
+ }\r
+ else\r
+ {\r
+ prvLCDCommand( lcdLINE2 );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvLCDCommand( portCHAR cCommand ) \r
+{\r
+ /* Prepare RD0 - RD7. */\r
+ lcdDATA &= 0xFF00; \r
+\r
+ /* Command byte to lcd. */\r
+ lcdDATA |= cCommand; \r
+\r
+ /* Ensure lcdRW is 0. */\r
+ lcdRW = 0; \r
+ lcdRS = 0;\r
+\r
+ /* Toggle lcdE line. */\r
+ lcdE = 1; \r
+ vTaskDelay( lcdVERY_SHORT_DELAY );\r
+ lcdE = 0;\r
+\r
+ vTaskDelay( lcdSHORT_DELAY );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvLCDData( portCHAR cChar )\r
+{\r
+ /* ensure lcdRW is 0. */\r
+ lcdRW = 0; \r
+\r
+ /* Assert register select to 1. */\r
+ lcdRS = 1; \r
+\r
+ /* Prepare RD0 - RD7. */\r
+ lcdDATA &= 0xFF00; \r
+\r
+ /* Data byte to lcd. */\r
+ lcdDATA |= cChar; \r
+ lcdE = 1; \r
+ Nop();\r
+ Nop();\r
+ Nop();\r
+\r
+ /* Toggle lcdE signal. */\r
+ lcdE = 0; \r
+\r
+ /* Negate register select to 0. */\r
+ lcdRS = 0; \r
+\r
+ vTaskDelay( lcdVERY_SHORT_DELAY );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvLCDPutString( portCHAR *pcString )\r
+{\r
+ /* Write out each character with appropriate delay between each. */\r
+ while( *pcString )\r
+ {\r
+ prvLCDData( *pcString );\r
+ pcString++;\r
+ vTaskDelay( lcdSHORT_DELAY );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvLCDClear( void )\r
+{\r
+ prvLCDCommand( lcdCLEAR );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSetupLCD( void )\r
+{\r
+ /* Wait for proper power up. */\r
+ vTaskDelay( lcdLONG_DELAY );\r
+ \r
+ /* Set initial states for the data and control pins */\r
+ LATE &= 0xFF00; \r
+\r
+ /* R/W state set low. */\r
+ lcdRW = 0; \r
+\r
+ /* lcdRS state set low. */\r
+ lcdRS = 0; \r
+\r
+ /* lcdE state set low. */\r
+ lcdE = 0; \r
+\r
+ /* Set data and control pins to outputs */\r
+ TRISE &= 0xFF00;\r
+\r
+ /* lcdRW pin set as output. */\r
+ RW_TRIS = 0; \r
+\r
+ /* lcdRS pin set as output. */\r
+ RS_TRIS = 0; \r
+\r
+ /* lcdE pin set as output. */\r
+ E_TRIS = 0; \r
+\r
+ /* 1st LCD initialization sequence */\r
+ lcdDATA &= 0xFF00;\r
+ lcdDATA |= 0x0038;\r
+ lcdE = 1; \r
+ Nop();\r
+ Nop();\r
+ Nop();\r
+\r
+ /* Toggle lcdE signal. */\r
+ lcdE = 0; \r
+\r
+ vTaskDelay( lcdSHORT_DELAY );\r
+ vTaskDelay( lcdSHORT_DELAY );\r
+ vTaskDelay( lcdSHORT_DELAY );\r
+ \r
+ /* 2nd LCD initialization sequence */\r
+ lcdDATA &= 0xFF00;\r
+ lcdDATA |= 0x0038;\r
+ lcdE = 1; \r
+ Nop();\r
+ Nop();\r
+ Nop(); \r
+\r
+ /* Toggle lcdE signal. */\r
+ lcdE = 0; \r
+\r
+ vTaskDelay( lcdSHORT_DELAY );\r
+\r
+ /* 3rd LCD initialization sequence */\r
+ lcdDATA &= 0xFF00;\r
+ lcdDATA |= 0x0038;\r
+ lcdE = 1; \r
+ Nop();\r
+ Nop();\r
+ Nop(); \r
+\r
+ /* Toggle lcdE signal. */\r
+ lcdE = 0; \r
+\r
+ vTaskDelay( lcdSHORT_DELAY );\r
+\r
+\r
+ /* Function set. */\r
+ prvLCDCommand( 0x38 ); \r
+\r
+ /* Display on/off control, cursor blink off (0x0C). */\r
+ prvLCDCommand( 0x0C ); \r
+\r
+ /* Entry mode set (0x06). */\r
+ prvLCDCommand( 0x06 ); \r
+\r
+ prvLCDCommand( lcdCLEAR ); \r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void vLCDTask( void *pvParameters )\r
+{\r
+xLCDMessage xMessage;\r
+unsigned portSHORT usRow = 0;\r
+\r
+ /* Initialise the hardware. This uses delays so must not be called prior\r
+ to the scheduler being started. */\r
+ prvSetupLCD();\r
+\r
+ /* Welcome message. */\r
+ prvLCDPutString( "www.FreeRTOS.org" );\r
+\r
+ for( ;; )\r
+ {\r
+ /* Wait for a message to arrive that requires displaying. */\r
+ while( xQueueReceive( xLCDQueue, &xMessage, portMAX_DELAY ) != pdPASS );\r
+\r
+ /* Clear the current display value. */\r
+ prvLCDClear();\r
+\r
+ /* Switch rows each time so we can see that the display is still being\r
+ updated. */\r
+ prvLCDGotoRow( usRow & 0x01 );\r
+ usRow++;\r
+ prvLCDPutString( xMessage.pcMessage );\r
+\r
+ /* Delay the requested amount of time to ensure the text just written \r
+ to the LCD is not overwritten. */\r
+ vTaskDelay( xMessage.xMinDisplayTime ); \r
+ }\r
+}\r
+\r
+\r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS.org distribution.\r
+\r
+ FreeRTOS.org is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS.org is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS.org; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS.org, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+\r
+ Also see http://www.SafeRTOS.com for an IEC 61508 compliant version along\r
+ with commercial development and support options.\r
+ ***************************************************************************\r
+*/\r
+\r
+#ifndef LCD_INC_H\r
+#define LCD_INC_H\r
+\r
+/* Create the task that will control the LCD. Returned is a handle to the queue\r
+on which messages to get written to the LCD should be written. */\r
+xQueueHandle xStartLCDTask( void );\r
+\r
+typedef struct\r
+{\r
+ /* The minimum amount of time the message should remain on the LCD without\r
+ being overwritten. */\r
+ portTickType xMinDisplayTime;\r
+\r
+ /* A pointer to the string to be displayed. */\r
+ portCHAR *pcMessage;\r
+\r
+} xLCDMessage;\r
+\r
+\r
+#endif /* LCD_INC_H */\r
+\r
+\r
/*\r
- FreeRTOS.org V4.2.1 - Copyright (C) 2003-2007 Richard Barry.\r
+ FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
* Creates all the demo application tasks, then starts the scheduler. The WEB\r
* documentation provides more details of the standard demo application tasks.\r
- * In addition to the standard demo tasks, the following tasks are defined\r
- * within this file:\r
- * \r
- * "Register test" tasks - These tasks first set all the general purpose \r
- * registers to a known value (with each register containing a different value)\r
- * then test each general purpose register to ensure it still contains the\r
- * set value. There are two register test tasks, with different values being\r
- * used by each. The register test tasks will be preempted frequently due to\r
- * their low priority. Setting then testing the value of each register in this\r
- * manner ensures the context of the tasks is being correctly saved and then\r
- * restored as the preemptive context switches occur. An error is flagged\r
- * should any register be found to contain an unexpected value. In addition\r
- * the register test tasks maintain a count of the number of times they cycle, \r
- * so an error can also be flagged should the cycle count not increment as\r
- * expected (indicating the the tasks are not executing at all).\r
+ * In addition to the standard demo tasks, the following tasks and tests are\r
+ * defined and/or created within this file:\r
+ *\r
+ * "Fast Interrupt Test" - A high frequency periodic interrupt is generated\r
+ * using a free running timer to demonstrate the use of the \r
+ * configKERNEL_INTERRUPT_PRIORITY configuration constant. The interrupt \r
+ * service routine measures the number of processor clocks that occur between\r
+ * each interrupt - and in so doing measures the jitter in the interrupt \r
+ * timing. The maximum measured jitter time is latched in the usMaxJitter \r
+ * variable, and displayed on the LCD by the 'Check' as described below. \r
+ * The fast interrupt is configured and handled in the timer_test.c source \r
+ * file.\r
*\r
+ * "LCD" task - the LCD task is a 'gatekeeper' task. It is the only task that\r
+ * is permitted to access the LCD directly. Other tasks wishing to write a\r
+ * message to the LCD send the message on a queue to the LCD task instead of \r
+ * accessing the LCD themselves. The LCD task just blocks on the queue waiting \r
+ * for messages - waking and displaying the messages as they arrive. The LCD\r
+ * task is defined in lcd.c. \r
+ * \r
* "Check" task - This only executes every three seconds but has the highest \r
* priority so is guaranteed to get processor time. Its main function is to \r
- * check that all the other tasks are still operational. Each task maintains a \r
- * unique count that is incremented each time the task successfully completes \r
- * its function. Should any error occur within such a task the count is \r
- * permanently halted. The check task inspects the count of each task to \r
- * ensure it has changed since the last time the check task executed. If all \r
- * the count variables have changed all the tasks are still executing error \r
- * free, and the check task toggles the onboard LED. Should any task contain \r
- * an error at any time check task cycle frequency is increased to 500ms, \r
- * causing the LED toggle rate to increase from 3 seconds to 500ms and in so\r
- * doing providing visual feedback that an error has occurred.\r
- *\r
+ * check that all the standard demo tasks are still operational. Should any\r
+ * unexpected behaviour within a demo task be discovered the 'check' task will\r
+ * write "FAIL #n" to the LCD (via the LCD task). If all the demo tasks are \r
+ * executing with their expected behaviour then the check task writes the max\r
+ * jitter time to the LCD (again via the LCD task), as described above.\r
*/\r
\r
+/* Standard includes. */\r
+#include <stdio.h>\r
+\r
/* Scheduler includes. */\r
#include "FreeRTOS.h"\r
#include "task.h"\r
+#include "queue.h"\r
#include "croutine.h"\r
\r
/* Demo application includes. */\r
#include "integer.h"\r
#include "comtest2.h"\r
#include "partest.h"\r
+#include "lcd.h"\r
+#include "timertest.h"\r
\r
/* Demo task priorities. */\r
#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 )\r
#define mainCOM_TEST_PRIORITY ( 2 )\r
\r
-/* Delay between check task cycles when an error has/has not been detected. */\r
-#define mainNO_ERROR_DELAY ( ( portTickType ) 3000 / portTICK_RATE_MS )\r
-#define mainERROR_DELAY ( ( portTickType ) 500 / portTICK_RATE_MS )\r
+/* The check task may require a bit more stack as it calls sprintf(). */\r
+#define mainCHECK_TAKS_STACK_SIZE ( configMINIMAL_STACK_SIZE * 2 )\r
+\r
+/* The execution period of the check task. */\r
+#define mainCHECK_TASK_PERIOD ( ( portTickType ) 3000 / portTICK_RATE_MS )\r
\r
/* The number of flash co-routines to create. */\r
-#define mainNUM_FLASH_COROUTINES ( 3 )\r
+#define mainNUM_FLASH_COROUTINES ( 5 )\r
\r
/* Baud rate used by the comtest tasks. */\r
#define mainCOM_TEST_BAUD_RATE ( 19200 )\r
\r
/* The LED used by the comtest tasks. mainCOM_TEST_LED + 1 is also used.\r
See the comtest.c file for more information. */\r
-#define mainCOM_TEST_LED ( 4 )\r
+#define mainCOM_TEST_LED ( 6 )\r
\r
-/* The LED used by the check task. */\r
-#define mainCHECK_LED ( 7 )\r
+/* The frequency at which the "fast interrupt test" interrupt will occur. */\r
+#define mainTEST_INTERRUPT_FREQUENCY ( 20000 )\r
\r
-/*-----------------------------------------------------------*/\r
+/* The number of processor clocks we expect to occur between each "fast\r
+interrupt test" interrupt. */\r
+#define mainEXPECTED_CLOCKS_BETWEEN_INTERRUPTS ( configCPU_CLOCK_HZ / mainTEST_INTERRUPT_FREQUENCY )\r
\r
-/*\r
- * The register test tasks as described at the top of this file. \r
- */ \r
-void xRegisterTest1( void *pvParameters );\r
-void xRegisterTest2( void *pvParameters );\r
+/* The number of nano seconds between each processor clock. */\r
+#define mainNS_PER_CLOCK ( ( unsigned portSHORT ) ( ( 1.0 / ( double ) configCPU_CLOCK_HZ ) * 1000000000.0 ) )\r
+\r
+/* Dimension the buffer used to hold the value of the maximum jitter time when\r
+it is converted to a string. */\r
+#define mainMAX_STRING_LENGTH ( 20 )\r
+\r
+/*-----------------------------------------------------------*/\r
\r
/*\r
* The check task as described at the top of this file.\r
\r
/*-----------------------------------------------------------*/\r
\r
-/* Variables used to detect errors within the register test tasks. */\r
-static volatile unsigned portSHORT usTest1CycleCounter = 0, usTest2CycleCounter = 0;\r
-static unsigned portSHORT usPreviousTest1Count = 0, usPreviousTest2Count = 0;\r
-\r
-/* Set to pdTRUE should an error be detected in any of the standard demo tasks\r
-or tasks defined within this file. */\r
-static unsigned portSHORT usErrorDetected = pdFALSE;\r
+/* The queue used to send messages to the LCD task. */\r
+static xQueueHandle xLCDQueue;\r
\r
/*-----------------------------------------------------------*/\r
\r
vCreateBlockTimeTasks();\r
\r
/* Create the test tasks defined within this file. */\r
- xTaskCreate( xRegisterTest1, "Reg1", configMINIMAL_STACK_SIZE, ( void * ) &usTest1CycleCounter, tskIDLE_PRIORITY, NULL );\r
- xTaskCreate( xRegisterTest2, "Reg2", configMINIMAL_STACK_SIZE, ( void * ) &usTest2CycleCounter, tskIDLE_PRIORITY, NULL );\r
- xTaskCreate( vCheckTask, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );\r
+ xTaskCreate( vCheckTask, ( signed portCHAR * ) "Check", mainCHECK_TAKS_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );\r
+\r
+ /* Start the task that will control the LCD. This returns the handle\r
+ to the queue used to write text out to the task. */\r
+ xLCDQueue = xStartLCDTask();\r
+\r
+ /* Start the high frequency interrupt test. */\r
+ vSetupTimerTest( mainTEST_INTERRUPT_FREQUENCY );\r
\r
/* Finally start the scheduler. */\r
vTaskStartScheduler();\r
\r
static void vCheckTask( void *pvParameters )\r
{\r
-portTickType xLastExecutionTime;\r
+/* Used to wake the task at the correct frequency. */\r
+portTickType xLastExecutionTime; \r
+\r
+/* The maximum jitter time measured by the fast interrupt test. */\r
+extern unsigned portSHORT usMaxJitter ;\r
\r
-/* Start with the no error delay. The long delay will cause the LED to flash\r
-slowly. */\r
-portTickType xDelay = mainNO_ERROR_DELAY;\r
+/* Buffer into which the maximum jitter time is written as a string. */\r
+static portCHAR cStringBuffer[ mainMAX_STRING_LENGTH ];\r
+\r
+/* The message that is sent on the queue to the LCD task. The first\r
+parameter is the minimum time (in ticks) that the message should be\r
+left on the LCD without being overwritten. The second parameter is a pointer\r
+to the message to display itself. */\r
+xLCDMessage xMessage = { 0, cStringBuffer };\r
+\r
+/* Set to pdTRUE should an error be detected in any of the standard demo tasks. */\r
+unsigned portSHORT usErrorDetected = pdFALSE;\r
\r
/* Initialise xLastExecutionTime so the first call to vTaskDelayUntil()\r
works correctly. */\r
for( ;; )\r
{\r
/* Wait until it is time for the next cycle. */\r
- vTaskDelayUntil( &xLastExecutionTime, xDelay );\r
+ vTaskDelayUntil( &xLastExecutionTime, mainCHECK_TASK_PERIOD );\r
\r
/* Has an error been found in any of the standard demo tasks? */\r
\r
if( xAreIntegerMathsTaskStillRunning() != pdTRUE )\r
{\r
usErrorDetected = pdTRUE;\r
+ sprintf( cStringBuffer, "FAIL #1" );\r
}\r
\r
if( xAreComTestTasksStillRunning() != pdTRUE )\r
{\r
usErrorDetected = pdTRUE;\r
+ sprintf( cStringBuffer, "FAIL #2" );\r
}\r
\r
if( xAreBlockTimeTestTasksStillRunning() != pdTRUE )\r
{\r
usErrorDetected = pdTRUE;\r
+ sprintf( cStringBuffer, "FAIL #3" );\r
}\r
\r
if( xAreBlockingQueuesStillRunning() != pdTRUE )\r
{\r
usErrorDetected = pdTRUE;\r
+ sprintf( cStringBuffer, "FAIL #4" );\r
}\r
\r
-\r
- /* Are the register test tasks still cycling? */\r
-\r
- if( usTest1CycleCounter == usPreviousTest1Count )\r
- {\r
- usErrorDetected = pdTRUE;\r
- }\r
-\r
- if( usTest2CycleCounter == usPreviousTest2Count )\r
+ if( usErrorDetected == pdFALSE )\r
{\r
- usErrorDetected = pdTRUE;\r
+ /* No errors have been discovered, so display the maximum jitter\r
+ timer discovered by the "fast interrupt test". */\r
+ sprintf( cStringBuffer, "%dns max jitter", ( portSHORT ) ( usMaxJitter - mainEXPECTED_CLOCKS_BETWEEN_INTERRUPTS ) * mainNS_PER_CLOCK );\r
}\r
\r
- usPreviousTest2Count = usTest2CycleCounter;\r
- usPreviousTest1Count = usTest1CycleCounter;\r
-\r
- \r
- /* If an error has been detected in any task then the delay will be\r
- reduced to increase the cycle rate of this task. This has the effect\r
- of causing the LED to flash much faster giving a visual indication of\r
- the error condition. */\r
- if( usErrorDetected != pdFALSE )\r
- {\r
- xDelay = mainERROR_DELAY;\r
- }\r
-\r
- /* Finally, toggle the LED before returning to delay to wait for the\r
- next cycle. */\r
- vParTestToggleLED( mainCHECK_LED );\r
- }\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-void xRegisterTest1( void *pvParameters )\r
-{\r
-/* This static so as not to use the frame pointer. They are volatile\r
-also to avoid it being stored in a register that we clobber during the test. */\r
-static unsigned portSHORT * volatile pusParameter;\r
-\r
- /* The variable incremented by this task is passed in as the parameter\r
- even though it is defined within this file. This is just to test the\r
- parameter passing mechanism. */\r
- pusParameter = pvParameters;\r
-\r
- for( ;; )\r
- {\r
- /* Increment the variable to show this task is still cycling. */\r
- ( *pusParameter )++;\r
-\r
- /* Set the w registers to known values, then check that each register\r
- contains the expected value. See the explanation at the top of this\r
- file for more information. */\r
- asm volatile( "mov.w #0x0101, W0 \n" \\r
- "mov.w #0x0102, W1 \n" \\r
- "mov.w #0x0103, W2 \n" \\r
- "mov.w #0x0104, W3 \n" \\r
- "mov.w #0x0105, W4 \n" \\r
- "mov.w #0x0106, W5 \n" \\r
- "mov.w #0x0107, W6 \n" \\r
- "mov.w #0x0108, W7 \n" \\r
- "mov.w #0x0109, W8 \n" \\r
- "mov.w #0x010a, W9 \n" \\r
- "mov.w #0x010b, W10 \n" \\r
- "mov.w #0x010c, W11 \n" \\r
- "mov.w #0x010d, W12 \n" \\r
- "mov.w #0x010e, W13 \n" \\r
- "mov.w #0x010f, W14 \n" \\r
- "sub #0x0101, W0 \n" \\r
- "cp0.w W0 \n" \\r
- "bra NZ, ERROR_TEST1 \n" \\r
- "sub #0x0102, W1 \n" \\r
- "cp0.w W1 \n" \\r
- "bra NZ, ERROR_TEST1 \n" \\r
- "sub #0x0103, W2 \n" \\r
- "cp0.w W2 \n" \\r
- "bra NZ, ERROR_TEST1 \n" \\r
- "sub #0x0104, W3 \n" \\r
- "cp0.w W3 \n" \\r
- "bra NZ, ERROR_TEST1 \n" \\r
- "sub #0x0105, W4 \n" \\r
- "cp0.w W4 \n" \\r
- "bra NZ, ERROR_TEST1 \n" \\r
- "sub #0x0106, W5 \n" \\r
- "cp0.w W5 \n" \\r
- "bra NZ, ERROR_TEST1 \n" \\r
- "sub #0x0107, W6 \n" \\r
- "cp0.w W6 \n" \\r
- "bra NZ, ERROR_TEST1 \n" \\r
- "sub #0x0108, W7 \n" \\r
- "cp0.w W7 \n" \\r
- "bra NZ, ERROR_TEST1 \n" \\r
- "sub #0x0109, W8 \n" \\r
- "cp0.w W8 \n" \\r
- "bra NZ, ERROR_TEST1 \n" \\r
- "sub #0x010a, W9 \n" \\r
- "cp0.w W9 \n" \\r
- "bra NZ, ERROR_TEST1 \n" \\r
- "sub #0x010b, W10 \n" \\r
- "cp0.w W10 \n" \\r
- "bra NZ, ERROR_TEST1 \n" \\r
- "sub #0x010c, W11 \n" \\r
- "cp0.w W11 \n" \\r
- "bra NZ, ERROR_TEST1 \n" \\r
- "sub #0x010d, W12 \n" \\r
- "cp0.w W12 \n" \\r
- "bra NZ, ERROR_TEST1 \n" \\r
- "sub #0x010e, W13 \n" \\r
- "cp0.w W13 \n" \\r
- "bra NZ, ERROR_TEST1 \n" \\r
- "sub #0x010f, W14 \n" \\r
- "cp0.w W14 \n" \\r
- "bra NZ, ERROR_TEST1 \n" \\r
- "bra NO_ERROR1 \n" \\r
- "ERROR_TEST1: \n" \\r
- "mov.w #1, W0 \n" \\r
- "mov.w W0, _usErrorDetected\n" \\r
- "NO_ERROR1: \n" );\r
- }\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-void xRegisterTest2( void *pvParameters )\r
-{\r
-/* This static so as not to use the frame pointer. They are volatile\r
-also to avoid it being stored in a register that we clobber during the test. */\r
-static unsigned portSHORT * volatile pusParameter;\r
-\r
- /* The variable incremented by this task is passed in as the parameter\r
- even though it is defined within this file. This is just to test the\r
- parameter passing mechanism. */\r
- pusParameter = pvParameters;\r
-\r
- for( ;; )\r
- {\r
- /* Increment the variable to show this task is still cycling. */\r
- ( *pusParameter )++;\r
-\r
- /* Set the w registers to known values, then check that each register\r
- contains the expected value. See the explanation at the top of this\r
- file for more information. */\r
- asm volatile( "mov.w #0x0100, W0 \n" \\r
- "mov.w #0x0101, W1 \n" \\r
- "mov.w #0x0102, W2 \n" \\r
- "mov.w #0x0103, W3 \n" \\r
- "mov.w #0x0104, W4 \n" \\r
- "mov.w #0x0105, W5 \n" \\r
- "mov.w #0x0106, W6 \n" \\r
- "mov.w #0x0107, W7 \n" \\r
- "mov.w #0x0108, W8 \n" \\r
- "mov.w #0x0109, W9 \n" \\r
- "mov.w #0x010a, W10 \n" \\r
- "mov.w #0x010b, W11 \n" \\r
- "mov.w #0x010c, W12 \n" \\r
- "mov.w #0x010d, W13 \n" \\r
- "mov.w #0x010e, W14 \n" \\r
- "sub #0x0100, W0 \n" \\r
- "cp0.w W0 \n" \\r
- "bra NZ, ERROR_TEST2 \n" \\r
- "sub #0x0101, W1 \n" \\r
- "cp0.w W1 \n" \\r
- "bra NZ, ERROR_TEST2 \n" \\r
- "sub #0x0102, W2 \n" \\r
- "cp0.w W2 \n" \\r
- "bra NZ, ERROR_TEST2 \n" \\r
- "sub #0x0103, W3 \n" \\r
- "cp0.w W3 \n" \\r
- "bra NZ, ERROR_TEST2 \n" \\r
- "sub #0x0104, W4 \n" \\r
- "cp0.w W4 \n" \\r
- "bra NZ, ERROR_TEST2 \n" \\r
- "sub #0x0105, W5 \n" \\r
- "cp0.w W5 \n" \\r
- "bra NZ, ERROR_TEST2 \n" \\r
- "sub #0x0106, W6 \n" \\r
- "cp0.w W6 \n" \\r
- "bra NZ, ERROR_TEST2 \n" \\r
- "sub #0x0107, W7 \n" \\r
- "cp0.w W7 \n" \\r
- "bra NZ, ERROR_TEST2 \n" \\r
- "sub #0x0108, W8 \n" \\r
- "cp0.w W8 \n" \\r
- "bra NZ, ERROR_TEST2 \n" \\r
- "sub #0x0109, W9 \n" \\r
- "cp0.w W9 \n" \\r
- "bra NZ, ERROR_TEST2 \n" \\r
- "sub #0x010a, W10 \n" \\r
- "cp0.w W10 \n" \\r
- "bra NZ, ERROR_TEST2 \n" \\r
- "sub #0x010b, W11 \n" \\r
- "cp0.w W11 \n" \\r
- "bra NZ, ERROR_TEST2 \n" \\r
- "sub #0x010c, W12 \n" \\r
- "cp0.w W12 \n" \\r
- "bra NZ, ERROR_TEST2 \n" \\r
- "sub #0x010d, W13 \n" \\r
- "cp0.w W13 \n" \\r
- "bra NZ, ERROR_TEST2 \n" \\r
- "sub #0x010e, W14 \n" \\r
- "cp0.w W14 \n" \\r
- "bra NZ, ERROR_TEST2 \n" \\r
- "bra NO_ERROR2 \n" \\r
- "ERROR_TEST2: \n" \\r
- "mov.w #1, W0 \n" \\r
- "mov.w W0, _usErrorDetected\n" \\r
- "NO_ERROR2: \n" );\r
+ /* Send the message to the LCD gatekeeper for display. */\r
+ xQueueSend( xLCDQueue, &xMessage, portMAX_DELAY );\r
}\r
}\r
/*-----------------------------------------------------------*/\r
vCoRoutineSchedule();\r
}\r
/*-----------------------------------------------------------*/\r
+\r
/*\r
- FreeRTOS.org V4.2.1 - Copyright (C) 2003-2007 Richard Barry.\r
+ FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
\r
IFS1bits.U2RXIF = serCLEAR_FLAG;\r
IFS1bits.U2TXIF = serCLEAR_FLAG;\r
- IPC7bits.U2RXIP = portKERNEL_INTERRUPT_PRIORITY;\r
- IPC7bits.U2TXIP = portKERNEL_INTERRUPT_PRIORITY;\r
+ IPC7bits.U2RXIP = configKERNEL_INTERRUPT_PRIORITY;\r
+ IPC7bits.U2TXIP = configKERNEL_INTERRUPT_PRIORITY;\r
IEC1bits.U2TXIE = serINTERRUPT_ENABLE;\r
IEC1bits.U2RXIE = serINTERRUPT_ENABLE;\r
\r
}\r
/*-----------------------------------------------------------*/\r
\r
-volatile short s = 0;\r
-char c[80] = {0};\r
-\r
-void __attribute__((__interrupt__)) _U2RXInterrupt( void )\r
+void __attribute__((__interrupt__, auto_psv)) _U2RXInterrupt( void )\r
{\r
portCHAR cChar;\r
portBASE_TYPE xYieldRequired = pdFALSE;\r
}\r
/*-----------------------------------------------------------*/\r
\r
-void __attribute__((__interrupt__)) _U2TXInterrupt( void )\r
+void __attribute__((__interrupt__, auto_psv)) _U2TXInterrupt( void )\r
{\r
signed portCHAR cChar;\r
portBASE_TYPE xTaskWoken = pdFALSE;\r
--- /dev/null
+/*\r
+ FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS.org distribution.\r
+\r
+ FreeRTOS.org is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS.org is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS.org; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS.org, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+\r
+ Also see http://www.SafeRTOS.com for an IEC 61508 compliant version along\r
+ with commercial development and support options.\r
+ ***************************************************************************\r
+*/\r
+\r
+/* High speed timer test as described in main.c. */\r
+\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+\r
+/* Demo includes. */\r
+#include "partest.h"\r
+\r
+/* The number of interrupts to pass before we start looking at the jitter. */\r
+#define timerSETTLE_TIME 5\r
+\r
+/* The maximum value the 16bit timer can contain. */\r
+#define timerMAX_COUNT 0xffff\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Measure the time between this interrupt and the previous interrupt to \r
+ * calculate the timing jitter. Remember the maximum value the jitter has\r
+ * ever been calculated to be.\r
+ */\r
+static void prvCalculateAndStoreJitter( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The maximum time (in processor clocks) between two consecutive timer\r
+interrupts so far. */\r
+unsigned portSHORT usMaxJitter = 0;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void vSetupTimerTest( unsigned portSHORT usFrequencyHz )\r
+{\r
+ /* T2 is used to generate interrupts. T4 is used to provide an accurate\r
+ time measurement. */\r
+ T2CON = 0;\r
+ T4CON = 0;\r
+ TMR2 = 0;\r
+ TMR4 = 0;\r
+\r
+ /* Timer 2 is going to interrupt at usFrequencyHz Hz. */\r
+ PR2 = ( unsigned portSHORT ) ( configCPU_CLOCK_HZ / ( unsigned portLONG ) usFrequencyHz );\r
+\r
+ /* Timer 4 is going to free run from minimum to maximum value. */\r
+ PR4 = ( unsigned portSHORT ) timerMAX_COUNT;\r
+\r
+ /* Setup timer 2 interrupt priority to be above the kernel priority so \r
+ the timer jitter is not effected by the kernel activity. */\r
+ IPC1bits.T2IP = configKERNEL_INTERRUPT_PRIORITY + 1;\r
+\r
+ /* Clear the interrupt as a starting condition. */\r
+ IFS0bits.T2IF = 0;\r
+\r
+ /* Enable the interrupt. */\r
+ IEC0bits.T2IE = 1;\r
+\r
+ /* Start both timers. */\r
+ T2CONbits.TON = 1;\r
+ T4CONbits.TON = 1;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvCalculateAndStoreJitter( void )\r
+{\r
+static unsigned portSHORT usLastCount = 0, usSettleCount = 0;\r
+unsigned portSHORT usThisCount, usDifference;\r
+\r
+ /* Capture the timer value as we enter the interrupt. */\r
+ usThisCount = TMR4;\r
+\r
+ if( usSettleCount >= timerSETTLE_TIME )\r
+ {\r
+ /* What is the difference between the timer value in this interrupt\r
+ and the value from the last interrupt. */\r
+ usDifference = usThisCount - usLastCount;\r
+\r
+ /* Store the difference in the timer values if it is larger than the\r
+ currently stored largest value. The difference over and above the \r
+ expected difference will give the 'jitter' in the processing of these\r
+ interrupts. */\r
+ if( usDifference > usMaxJitter )\r
+ {\r
+ usMaxJitter = usDifference;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Don't bother storing any values for the first couple of \r
+ interrupts. */\r
+ usSettleCount++;\r
+ }\r
+\r
+ /* Remember what the timer value was this time through, so we can calculate\r
+ the difference the next time through. */\r
+ usLastCount = usThisCount;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void __attribute__((__interrupt__, auto_psv)) _T2Interrupt( void )\r
+{\r
+ /* Work out the time between this and the previous interrupt. */\r
+ prvCalculateAndStoreJitter();\r
+\r
+ /* Clear the timer interrupt. */\r
+ IFS0bits.T2IF = 0;\r
+}\r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS.org distribution.\r
+\r
+ FreeRTOS.org is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS.org is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS.org; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS.org, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+\r
+ Also see http://www.SafeRTOS.com for an IEC 61508 compliant version along\r
+ with commercial development and support options.\r
+ ***************************************************************************\r
+*/\r
+\r
+#ifndef TIMER_TEST_H\r
+#define TIMER_TEST_H\r
+\r
+/* Setup the high frequency timer interrupt. */\r
+void vSetupTimerTest( unsigned portSHORT usFrequencyHz );\r
+\r
+#endif /* TIMER_TEST_H */\r
+\r
+\r
+\r
projects / freertos / commitdiff