]> git.sur5r.net Git - openocd/commitdiff
armv8: factor out generic bit set/clr for debug registers
authorMatthias Welwarsky <matthias.welwarsky@sysgo.com>
Wed, 15 Feb 2017 13:57:21 +0000 (14:57 +0100)
committerPaul Fertser <fercerpav@gmail.com>
Fri, 24 Feb 2017 09:15:18 +0000 (09:15 +0000)
introduce armv8_set_dbgreg_bits() function to make register
bit-field modifications easier to read.

Change-Id: I6b06f66262587fd301d848c9e0645e8327653de7
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/3989
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
src/target/aarch64.c
src/target/armv8.c
src/target/armv8.h

index 5dd6d7adea66d196af13f6d1612374bf2abd5b45..65a5278e3433ac6eefd05433f7c1c15c95eabd07 100644 (file)
@@ -238,23 +238,7 @@ static int aarch64_dpm_setup(struct aarch64_common *a8, uint64_t debug)
 static int aarch64_set_dscr_bits(struct target *target, unsigned long bit_mask, unsigned long value)
 {
        struct armv8_common *armv8 = target_to_armv8(target);
-       uint32_t dscr;
-
-       /* Read DSCR */
-       int retval = mem_ap_read_atomic_u32(armv8->debug_ap,
-                       armv8->debug_base + CPUV8_DBG_DSCR, &dscr);
-       if (ERROR_OK != retval)
-               return retval;
-
-       /* clear bitfield */
-       dscr &= ~bit_mask;
-       /* put new value */
-       dscr |= value & bit_mask;
-
-       /* write new DSCR */
-       retval = mem_ap_write_atomic_u32(armv8->debug_ap,
-                       armv8->debug_base + CPUV8_DBG_DSCR, dscr);
-       return retval;
+       return armv8_set_dbgreg_bits(armv8, CPUV8_DBG_DSCR, bit_mask, value);
 }
 
 static struct target *get_aarch64(struct target *target, int32_t coreid)
index 00ab6ed1288d180804e529f3b483bd1ab7dbadf9..2f1d5c10a5077af0cd8d1ffcef8405cd29811e00 100644 (file)
@@ -1292,3 +1292,24 @@ int armv8_get_gdb_reg_list(struct target *target,
                }
        }
 }
+
+int armv8_set_dbgreg_bits(struct armv8_common *armv8, unsigned int reg, unsigned long mask, unsigned long value)
+{
+       uint32_t tmp;
+
+       /* Read register */
+       int retval = mem_ap_read_atomic_u32(armv8->debug_ap,
+                       armv8->debug_base + reg, &tmp);
+       if (ERROR_OK != retval)
+               return retval;
+
+       /* clear bitfield */
+       tmp &= ~mask;
+       /* put new value */
+       tmp |= value & mask;
+
+       /* write new value */
+       retval = mem_ap_write_atomic_u32(armv8->debug_ap,
+                       armv8->debug_base + reg, tmp);
+       return retval;
+}
index 3b2fc59089ace07cb7720ce17c8b4662aa8d3127..1cb3a3b0f12d02561dc6fd833b6befcc2e61121a 100644 (file)
@@ -307,6 +307,7 @@ static inline unsigned int armv8_curel_from_core_mode(enum arm_mode core_mode)
 }
 
 void armv8_select_reg_access(struct armv8_common *armv8, bool is_aarch64);
+int armv8_set_dbgreg_bits(struct armv8_common *armv8, unsigned int reg, unsigned long mask, unsigned long value);
 
 extern const struct command_registration armv8_command_handlers[];