# Create M bytes values
# __1M ... to __2048K
for { set x 1 } { $x < 2048 } { set x [expr $x * 2]} {
- set vn [format "__%dM" $x]
+ set vn [format "__%dM" $x]
global $vn
set $vn [expr (1024 * 1024 * $x)]
}
source [find target/samsung_s3c4510.cfg]
-#
+#
# FIXME:
# Add (A) sdram configuration
# Add (B) flash cfi programing configuration
# Try to run at 1khz... Yea, that slow!
# Chip is really running @ 32khz
jtag_khz 8
-
+
mww 0xfffffc64 0xffffffff
## disable all clocks but system clock
mww 0xfffffc04 0xfffffffe
mww 0xfffffc30 0x202
## Sleep some - (go read)
sleep 100
-
+
#========================================
# CPU now runs at 180mhz
# SYS runs at 60mhz.
jtag_khz 40000
#========================================
-
-
+
+
## set memc for all memories
mww 0xffffff60 0x02
## program smc controller
mww 0xffffff80 0x02
## touch sdram chip to make it work
mww 0x20000000 0
- ## sdram controller mode register
+ ## sdram controller mode register
mww 0xffffff90 0x04
mww 0x20000000 0
mww 0x20000000 0
}
proc at91sam9g20_init { } {
-
+
# At reset AT91SAM9G20 chip runs on slow clock (32.768 kHz). To shift over to a normal clock requires
# a number of steps that must be carefully performed. The process outline below follows the
# recommended procedure outlined in the AT91SAM9G20 technical manual.
mww 0xfffffc30 0x00000101
while { [expr [read_register 0xfffffc68] & 0x08] != 8 } { sleep 1 }
-
+
# Now change PMC_MCKR register to select PLLA.
# Wait for MCKRDY signal from PMC_SR to assert.
# RSTC_MR : enable user reset, MMU may be enabled... use physical address
arm926ejs mww_phys 0xfffffd08 0xa5000501
}
-
+
$_TARGETNAME configure -event reset-init {
mww 0xfffffd44 0x00008000 # WDT_MR : disable watchdog
mww 0xfffff870 0xffff0000 # PIO_ASR : Select peripheral function for D15..D31
mww 0xfffff804 0xffff0000 # PIO_PDR : Disable PIO function for D15..D31
-
+
mww 0xffffef1c 0x00010002 # EBI_CSA : Assign EBI Chip Select 1 to SDRAM, VDDIOMSEL set for +3V3 memory
mww 0xffffea08 0x85227259 # SDRAMC_CR : Configure SDRAM (2 x Micron MT48LC16M16A2 : 4M x 16Bit x 4 Banks)
source [find target/pxa270.cfg]
# longer-than-normal reset delay
-jtag_nsrst_delay 800
+jtag_nsrst_delay 800
reset_config trst_and_srst separate
# Bare-bones initialization of core clocks and SDRAM
proc csb732_init { } {
-
+
# Disable fast writing only for init
memwrite burst disable
# Set ARM clock to 532 MHz, AHB to 133 MHz
mww 0x53F80004 0x1000
-
+
# Set core clock to 2 * 24 MHz * (11 + 1/12) = 532 MHz
mww 0x53F8001C 0xB2C01
-
+
set ESDMISC 0xB8001010
set ESDCFG0 0xB8001004
set ESDCTL0 0xB8001000
# Enable DDR
mww $ESDMISC 0x4
-
+
# Timing
mww $ESDCFG0 0x007fff3f
# Enable CS) auto-refresh
mww $ESDCTL0 0xA2120080
-
+
# Refresh twice (dummy writes)
mww 0x80000000 0
mww 0x80000000 0
# Enable CS0 load mode register
mww $ESDCTL0 0xB2120080
- # Dummy writes
+ # Dummy writes
mwb 0x80000033 0x01
mwb 0x81000000 0x01
reset_config trst_and_srst
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
set _CHIPNAME ns9360
}
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
# This config file was defaulting to big endian..
set _ENDIAN big
}
mww 0x90600104 0x33313333
mww 0xA0700000 0x00000001 # Enable the memory controller.
mww 0xA0700024 0x00000006 # Set the refresh counter 6
- mww 0xA0700028 0x00000001 #
+ mww 0xA0700028 0x00000001 #
mww 0xA0700030 0x00000001 # Set the precharge period
mww 0xA0700034 0x00000004 # Active to precharge command period is 16 clock cycles
mww 0xA070003C 0x00000001 # tAPR
mww 0xA0700040 0x00000005 # tDAL
mww 0xA0700044 0x00000001 # tWR
- mww 0xA0700048 0x00000006 # tRC 32 clock cycles
+ mww 0xA0700048 0x00000006 # tRC 32 clock cycles
mww 0xA070004C 0x00000006 # tRFC 32 clock cycles
mww 0xA0700054 0x00000001 # tRRD
mww 0xA0700058 0x00000001 # tMRD
- mww 0xA0700100 0x00004280 # Dynamic Config 0 (cs4)
+ mww 0xA0700100 0x00004280 # Dynamic Config 0 (cs4)
mww 0xA0700120 0x00004280 # Dynamic Config 1 (cs5)
mww 0xA0700140 0x00004280 # Dynamic Config 2 (cs6)
mww 0xA0700160 0x00004280 # Dynamic Config 3 (cs7)
mww 0xA0900000 0x00000002
mww 0xA0900000 0x00000002
#
- mdw 0xA0900000
- mdw 0xA0900000
- mdw 0xA0900000
- mdw 0xA0900000
- mdw 0xA0900000
+ mdw 0xA0900000
+ mdw 0xA0900000
+ mdw 0xA0900000
+ mdw 0xA0900000
+ mdw 0xA0900000
#
mww 0xA0700024 0x00000030 # Set the refresh counter to 30
mww 0xA0700020 0x00000083 # Issue SDRAM MODE command
source [find target/sam7se512.cfg]
$_TARGETNAME configure -event reset-init {
- # WDT_MR, disable watchdog
+ # WDT_MR, disable watchdog
mww 0xFFFFFD44 0x00008000
# RSTC_MR, enable user reset
# Issue 16 bit SDRAM command: NOP
mww 0xffffffb0 0x00000011 # SDRAMC_MR_OFF
- mww 0x20000000 0x00000000
+ mww 0x20000000 0x00000000
# Issue 16 bit SDRAM command: Precharge all
mww 0xffffffb0 0x00000012 # SDRAMC_MR_OFF
- mww 0x20000000 0x00000000
+ mww 0x20000000 0x00000000
# Issue 8 auto-refresh cycles
mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
- mww 0x20000000 0x00000000
+ mww 0x20000000 0x00000000
mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
- mww 0x20000000 0x00000000
+ mww 0x20000000 0x00000000
mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
- mww 0x20000000 0x00000000
+ mww 0x20000000 0x00000000
mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
- mww 0x20000000 0x00000000
+ mww 0x20000000 0x00000000
mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
- mww 0x20000000 0x00000000
+ mww 0x20000000 0x00000000
mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
- mww 0x20000000 0x00000000
+ mww 0x20000000 0x00000000
mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
- mww 0x20000000 0x00000000
+ mww 0x20000000 0x00000000
mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
- mww 0x20000000 0x00000000
+ mww 0x20000000 0x00000000
- # Issue 16 bit SDRAM command: Set mode register
+ # Issue 16 bit SDRAM command: Set mode register
mww 0xffffffb0 0x00000013 # SDRAMC_MR_OFF
mww 0x20000014 0xcafedede
#jtag scan chain
#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
set _CHIPNAME str912
}
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
set _ENDIAN little
}
$_TARGETNAME configure -event reset-init {
# We can increase speed now that we know the target is halted.
#jtag_rclk 3000
-
+
# -- Enable 96K RAM
# PFQBC enabled / DTCM & AHB wait-states disabled
- mww 0x5C002034 0x0191
+ mww 0x5C002034 0x0191
str9x flash_config 0 4 2 0 0x80000
flash protect 0 0 7 off
# ========================================
# Configure DDR on CSD0 -- initial reset
# ========================================
- mww 0xD8001010 0x00000008
+ mww 0xD8001010 0x00000008
# ========================================
- # Configure PSRAM on CS5
+ # Configure PSRAM on CS5
# ========================================
mww 0xd8002050 0x0000dcf6
- mww 0xd8002054 0x444a4541
- mww 0xd8002058 0x44443302
+ mww 0xd8002054 0x444a4541
+ mww 0xd8002058 0x44443302
# ========================================
# Configure16 bit NorFlash on CS0
# ========================================
- mww 0xd8002000 0x0000CC03
- mww 0xd8002004 0xa0330D01
- mww 0xd8002008 0x00220800
+ mww 0xd8002000 0x0000CC03
+ mww 0xd8002004 0xa0330D01
+ mww 0xd8002008 0x00220800
# ========================================
- # Configure CPLD on CS4
+ # Configure CPLD on CS4
# ========================================
- mww 0xd8002040 0x0000DCF6
- mww 0xd8002044 0x444A4541
- mww 0xd8002048 0x44443302
+ mww 0xd8002040 0x0000DCF6
+ mww 0xd8002044 0x444A4541
+ mww 0xd8002048 0x44443302
# ========================================
- # Configure DDR on CSD0 -- wait 5000 cycle
+ # Configure DDR on CSD0 -- wait 5000 cycle
# ========================================
- mww 0x10027828 0x55555555
- mww 0x10027830 0x55555555
- mww 0x10027834 0x55555555
- mww 0x10027838 0x00005005
- mww 0x1002783C 0x15555555
+ mww 0x10027828 0x55555555
+ mww 0x10027830 0x55555555
+ mww 0x10027834 0x55555555
+ mww 0x10027838 0x00005005
+ mww 0x1002783C 0x15555555
- mww 0xD8001010 0x00000004
+ mww 0xD8001010 0x00000004
- mww 0xD8001004 0x00795729
+ mww 0xD8001004 0x00795729
- mww 0xD8001000 0x92200000
+ mww 0xD8001000 0x92200000
mww 0xA0000F00 0x0
- mww 0xD8001000 0xA2200000
+ mww 0xD8001000 0xA2200000
mww 0xA0000F00 0x0
mww 0xA0000F00 0x0
- mww 0xD8001000 0xB2200000
+ mww 0xD8001000 0xB2200000
mwb 0xA0000033 0xFF
mwb 0xA1000000 0xAA
- mww 0xD8001000 0x82228085
+ mww 0xD8001000 0x82228085
}
# ========================================
# Configure DDR on CSD0 -- initial reset
# ========================================
- mww 0xD8001010 0x00000008
+ mww 0xD8001010 0x00000008
sleep 100
# ========================================
- # Configure DDR on CSD0 -- wait 5000 cycle
+ # Configure DDR on CSD0 -- wait 5000 cycle
# ========================================
- mww 0x10027828 0x55555555
- mww 0x10027830 0x55555555
- mww 0x10027834 0x55555555
- mww 0x10027838 0x00005005
- mww 0x1002783C 0x15555555
+ mww 0x10027828 0x55555555
+ mww 0x10027830 0x55555555
+ mww 0x10027834 0x55555555
+ mww 0x10027838 0x00005005
+ mww 0x1002783C 0x15555555
- mww 0xD8001010 0x00000004
+ mww 0xD8001010 0x00000004
- mww 0xD8001004 0x00795729
+ mww 0xD8001004 0x00795729
#mww 0xD8001000 0x92200000
mww 0xD8001000 0x91120000
mww 0xA0000F00 0x0
- #mww 0xD8001000 0xA2200000
+ #mww 0xD8001000 0xA2200000
mww 0xD8001000 0xA1120000
mww 0xA0000F00 0x0
mww 0xA0000F00 0x0
- #mww 0xD8001000 0xB2200000
+ #mww 0xD8001000 0xB2200000
mww 0xD8001000 0xB1120000
mwb 0xA0000033 0xFF
mwb 0xA1000000 0xAA
- #mww 0xD8001000 0x82228085
+ #mww 0xD8001000 0x82228085
mww 0xD8001000 0x81128080
}
mww 0x53F80010 0x00271C1B
# ========================================
- # Configure CPLD on CS5
+ # Configure CPLD on CS5
# ========================================
mww 0xb8002050 0x0000DCF6
mww 0xb8002054 0x444A4541
#-------------------------------------------------------------------------
# Mini2440 Samsung s3c2440A Processor with 64MB DRAM, 64MB NAND, 2 MB N0R
# NOTE: Configured for NAND boot (switch S2 in NANDBOOT)
-# 64 MB NAND (Samsung K9D1208V0M)
+# 64 MB NAND (Samsung K9D1208V0M)
# B Findlay 08/09
#
# ----------- Important notes to help you on your way ----------
# NOR/NAND Boot Switch - I have not read the vivi source, but from
# what I could tell from reading the registers it appears that vivi
# loads itself into DRAM and then flips NFCONT (0x4E000004) bits
-# Mode (bit 0 = 1), and REG_nCE (bit 1 = 0) which maps the NAND
-# FLASH at the bottom 64MB of memory. This essentially takes the
-# NOR Flash out of the circuit so you can't trash it.
+# Mode (bit 0 = 1), and REG_nCE (bit 1 = 0) which maps the NAND
+# FLASH at the bottom 64MB of memory. This essentially takes the
+# NOR Flash out of the circuit so you can't trash it.
#
# I adapted the samsung_s3c2440.cfg file which is why I did not
# include "source [find target/samsung_s3c2440.cfg]". I believe
# JTAG ADAPTER SPECIFIC
# IMPORTANT! Any JTAG device that uses ADAPTIVE CLOCKING will likely
# FAIL as the pin RTCK on the mini2440 10 pin JTAG Conn doesn't exist.
-# This is Pin 11 (RTCK) on 20 pin JTAG connector. Therefore it is
+# This is Pin 11 (RTCK) on 20 pin JTAG connector. Therefore it is
# necessary to FORCE setting the clock. Normally this should be configured
-# in the openocd.cfg file, but was placed here as it can be a tough
+# in the openocd.cfg file, but was placed here as it can be a tough
# problem to figure out. THIS MAY NOT FIX YOUR PROBLEM.. I modified
# the openOCD driver jlink.c and posted it here. It may eventually end
# up changed in openOCD, but its a hack in the driver and really should
# But it should get you way ahead of the game from where I started.
# If you find problems (and fixes) please post them to
# openocd-development@lists.berlios.de and join the developers and
-# check in fixes to this and anything else you find. I do not
-# provide support, but if you ask really nice and I see anything
+# check in fixes to this and anything else you find. I do not
+# provide support, but if you ask really nice and I see anything
# obvious I will tell you.. mostly just dig, fix, and submit to openocd.
-#
+#
# best! brfindla@yahoo.com Nashua, NH USA
#
# Recommended resources:
# - first two are the best Mini2440 resources anywhere
# - maintained by buserror... thanks guy!
#
-# http://bliterness.blogspot.com/
+# http://bliterness.blogspot.com/
# http://code.google.com/p/mini2440/
#
# others....
-#
+#
# http://forum.sparkfun.com/viewforum.php?f=18
# http://labs.kernelconcepts.de/Publications/Micro24401/
# http://www.friendlyarm.net/home
# Target configuration for the Samsung 2440 system on chip
# Tested on a S3C2440 Evaluation board by keesj
# Processor : ARM920Tid(wb) rev 0 (v4l)
-# Info: JTAG tap: s3c2440.cpu tap/device found: 0x0032409d
+# Info: JTAG tap: s3c2440.cpu tap/device found: 0x0032409d
# (Manufacturer: 0x04e, Part: 0x0324, Version: 0x0)
#-------------------------------------------------------------------------
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
set _CHIPNAME s3c2440
}
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
# this defaults to a bigendian
set _ENDIAN little
}
#reset configuration
jtag_nsrst_delay 100
-jtag_ntrst_delay 100
+jtag_ntrst_delay 100
reset_config trst_and_srst
#-------------------------------------------------------------------------
# JTAG ADAPTER SPECIFIC
-# IMPORTANT! See README at top of this file.
+# IMPORTANT! See README at top of this file.
#-------------------------------------------------------------------------
- jtag_khz 12000
- jtag interface
+ jtag_khz 12000
+ jtag interface
#-------------------------------------------------------------------------
# GDB Setup
gdb_port 3333
gdb_detach resume
- gdb_breakpoint_override hard
+ gdb_breakpoint_override hard
gdb_memory_map enable
- gdb_flash_program enable
+ gdb_flash_program enable
#------------------------------------------------
# ARM SPECIFIC
#------------------------------------------------
- targets
+ targets
# arm7_9 dcc_downloads enable
# arm7_9 fast_memory_access enable
-
-
- nand device s3c2440 0
+
+
+ nand device s3c2440 0
jtag_nsrst_delay 100
- jtag_ntrst_delay 100
+ jtag_ntrst_delay 100
reset_config trst_and_srst
init
# OM2 OM3 pulled to ground so main clock and
# usb clock are off 12mHz xtal
#-----------------------------------------------
-
+
arm920t mww_phys 0x4C000014 0x00000005 # Clock Divider control Reg
arm920t mww_phys 0x4C000000 0xFFFFFFFF # LOCKTIME count register
arm920t mww_phys 0x4C000008 0x00038022 # UPPLCON USB clock config Reg
arm920t mww_phys 0x4C000004 0x0007F021 # MPPLCON Proc clock config Reg
-
+
#-----------------------------------------------
# Configure Memory controller
# BWSCON configures all banks, NAND, NOR, DRAM
# DRAM - 64MB - 32 bit bus, uses BANKCON6 BANKCON7
#-----------------------------------------------
-
+
arm920t mww_phys 0x48000000 0x22111112 # BWSCON - Bank and Bus Width
arm920t mww_phys 0x48000010 0x00001112 # BANKCON4 - ?
- arm920t mww_phys 0x4800001c 0x00018009 # BANKCON6 - DRAM
- arm920t mww_phys 0x48000020 0x00018009 # BANKCON7 - DRAM
- arm920t mww_phys 0x48000024 0x008E04EB # REFRESH - DRAM
- arm920t mww_phys 0x48000028 0x000000B2 # BANKSIZE - DRAM
- arm920t mww_phys 0x4800002C 0x00000030 # MRSRB6 - DRAM
- arm920t mww_phys 0x48000030 0x00000030 # MRSRB7 - DRAM
-
+ arm920t mww_phys 0x4800001c 0x00018009 # BANKCON6 - DRAM
+ arm920t mww_phys 0x48000020 0x00018009 # BANKCON7 - DRAM
+ arm920t mww_phys 0x48000024 0x008E04EB # REFRESH - DRAM
+ arm920t mww_phys 0x48000028 0x000000B2 # BANKSIZE - DRAM
+ arm920t mww_phys 0x4800002C 0x00000030 # MRSRB6 - DRAM
+ arm920t mww_phys 0x48000030 0x00000030 # MRSRB7 - DRAM
+
#-----------------------------------------------
# Now port configuration for enables for memory
# and other stuff.
#-----------------------------------------------
-
+
arm920t mww_phys 0x56000000 0x007FFFFF # GPACON
-
- arm920t mww_phys 0x56000010 0x00295559 # GPBCON
+
+ arm920t mww_phys 0x56000010 0x00295559 # GPBCON
arm920t mww_phys 0x56000018 0x000003FF # GPBUP (PULLUP ENABLE)
- arm920t mww_phys 0x56000014 0x000007C2 # GPBDAT
-
- arm920t mww_phys 0x56000020 0xAAAAA6AA # GPCCON
+ arm920t mww_phys 0x56000014 0x000007C2 # GPBDAT
+
+ arm920t mww_phys 0x56000020 0xAAAAA6AA # GPCCON
arm920t mww_phys 0x56000028 0x0000FFFF # GPCUP
- arm920t mww_phys 0x56000024 0x00000020 # GPCDAT
-
- arm920t mww_phys 0x56000030 0xAAAAAAAA # GPDCON
- arm920t mww_phys 0x56000038 0x0000FFFF # GPDUP
-
- arm920t mww_phys 0x56000040 0xAAAAAAAA # GPECON
- arm920t mww_phys 0x56000048 0x0000FFFF # GPEUP
-
- arm920t mww_phys 0x56000050 0x00001555 # GPFCON
- arm920t mww_phys 0x56000058 0x0000007F # GPFUP
- arm920t mww_phys 0x56000054 0x00000000 # GPFDAT
-
- arm920t mww_phys 0x56000060 0x00150114 # GPGCON
- arm920t mww_phys 0x56000068 0x0000007F # GPGUP
-
- arm920t mww_phys 0x56000070 0x0015AAAA # GPHCON
- arm920t mww_phys 0x56000078 0x000003FF # GPGUP
-
-}
+ arm920t mww_phys 0x56000024 0x00000020 # GPCDAT
+
+ arm920t mww_phys 0x56000030 0xAAAAAAAA # GPDCON
+ arm920t mww_phys 0x56000038 0x0000FFFF # GPDUP
+
+ arm920t mww_phys 0x56000040 0xAAAAAAAA # GPECON
+ arm920t mww_phys 0x56000048 0x0000FFFF # GPEUP
+
+ arm920t mww_phys 0x56000050 0x00001555 # GPFCON
+ arm920t mww_phys 0x56000058 0x0000007F # GPFUP
+ arm920t mww_phys 0x56000054 0x00000000 # GPFDAT
+
+ arm920t mww_phys 0x56000060 0x00150114 # GPGCON
+ arm920t mww_phys 0x56000068 0x0000007F # GPGUP
+
+ arm920t mww_phys 0x56000070 0x0015AAAA # GPHCON
+ arm920t mww_phys 0x56000078 0x000003FF # GPGUP
+
+}
#-----------------------------------------
halt
-
+
#flash configuration (K9D1208V0M: 512Mbit, x8, 3.3V, Mode: Normal, 1st gen)
nand probe 0
nand list
echo "---- http://repo.or.cz/w/u-boot-openmoko/mini2440.git ---"
echo "---- Also this: ---"
echo "---- http://code.google.com/p/mini2440/wiki/MiniBringup --"
- echo "----------------------------------------------------------"
-
+ echo "----------------------------------------------------------"
+
init_2440
echo "Loading /tftpboot/u-boot-nand512.bin"
load_image /tftpboot/u-boot-nand512.bin 0x33f80000 bin
proc at91sam_init { } {
-
+
# at reset chip runs at 32 kHz => 1/8 * 32 kHz = 4 kHz
jtag_rclk 4
# A PXA255 test board with SST 39LF400A flash
#
# At reset the memory map is as follows. Note that
-# the memory map changes later on as the application
+# the memory map changes later on as the application
# starts...
#
# RAM at 0x4000000
-# Marvell SheevaPlug
+# Marvell SheevaPlug
source [find interface/sheevaplug.cfg]
source [find target/feroceon.cfg]
# str910-eval eval board
-#
-# Need reset scripts
+#
+# Need reset scripts
reset_config trst_and_srst
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
set _CHIPNAME str912
}
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
set _ENDIAN little
}
$_TARGETNAME configure -event reset-init {
# We can increase speed now that we know the target is halted.
#jtag_rclk 3000
-
+
# -- Enable 96K RAM
# PFQBC enabled / DTCM & AHB wait-states disabled
- mww 0x5C002034 0x0191
+ mww 0x5C002034 0x0191
str9x flash_config 0 4 2 0 0x80000
flash protect 0 0 7 off
# Telo board & C100 support trst and srst
-# however openocd does not support
+# however openocd does not support
# 1. setting srst reset pulse width
# 2. setting delay between srst pulse and JTAG access
# This really makes the srst useless for now.
# setup GPIO used as control signals for C100
setupGPIO
# This will allow acces to lower 8MB or NOR
- lowGPIO5
+ lowGPIO5
# setup NOR size,timing,etc.
setupNOR
# setup internals + PLL + DDR2
# Force target into ARM state.
# soft_reset_halt # not implemented on ARM11
puts "Detected SRSRT asserted on C100.CPU"
-
+
}
-proc power_restore {} { puts "Sensed power restore. No action." }
+proc power_restore {} { puts "Sensed power restore. No action." }
proc srst_deasserted {} { puts "Sensed nSRST deasserted. No action." }
-# Thanks to Pieter Conradie for this script!
+# Thanks to Pieter Conradie for this script!
#
# Unknown vendor board contains:
#
$_TARGETNAME configure -event reset-start {
# At reset CPU runs at 22 to 42 kHz.
# JTAG Frequency must be 6 times slower.
- jtag_rclk 3
+ jtag_rclk 3
halt
# RSTC_MR : enable user reset, MMU may be enabled... use physical address
arm926ejs mww_phys 0xfffffd08 0xa5000501
}
-
+
$_TARGETNAME configure -event reset-init {
mww 0xfffffd44 0x00008000 # WDT_MR : disable watchdog
sleep 10 # wait 10 ms
# Increase JTAG Speed to 6 MHz if RCLK is not supported
- jtag_rclk 6000
+ jtag_rclk 6000
arm7_9 dcc_downloads enable # Enable faster DCC downloads
mww 0xfffff870 0xffff0000 # PIO_ASR : Select peripheral function for D15..D31
mww 0xfffff804 0xffff0000 # PIO_PDR : Disable PIO function for D15..D31
mww 0xfffff860 0xffff0000 # PIO_PUDR : Disable D15..D31 pull-ups
-
+
mww 0xffffef1c 0x00010102 # EBI_CSA : Assign EBI Chip Select 1 to SDRAM
# VDDIOMSEL set for +3V3 memory
# Disable D0..D15 pull-ups
mww 0xa0030000 0xE34111BA
mww 0xa003fffc 0xa4444
mww 0xa003fffc 0
-
+
# remap boot vector in CPU local RAM
mww 0xa006f000 0x60000
-
+
# map flash to CPU address space REG_BASE_cpu_block+CPU_remap4
mww 0x0006f010 0x48000000
-
+
# map flash addr to REG_BASE_cpu_block + LR_XENV_LOCATION (normally done by XOS)
mww 0x00061ff0 0x48000000
}
reset_config srst_only srst_pulls_trst
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
set _CHIPNAME zy1000
}
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
set _ENDIAN little
}
-
+
#jtag scan chain
if { [info exists CPUTAPID ] } {
set _CPUTAPID $CPUTAPID
arm7_9 dcc_downloads enable
flash bank ecosflash 0x01000000 0x200000 2 2 0 ecos/at91eb40a.elf
-$_TARGETNAME configure -event reset-init {
+$_TARGETNAME configure -event reset-init {
# Set up chip selects & timings
mww 0xFFE00000 0x0100273D
mww 0xFFE00004 0x08002125
mww 0xFFE0001c 0x70000000
mww 0xFFE00020 0x00000001
mww 0xFFE00024 0x00000000
-
- # remap
- mww 0xFFFFF124 0xFFFFFFFF
+
+ # remap
+ mww 0xFFFFF124 0xFFFFFFFF
mww 0xffff0010 0x100
mww 0xffff0034 0x100
-
+
#disable 16x5x UART interrupts
mww 0x08020004 0
}
# There is no return value from this procedure. If it is
# successful it does not throw an exception
#
-# Progress messages are output via puts
+# Progress messages are output via puts
proc production {firmwarefile serialnumber} {
if {[string length $serialnumber]!=12} {
puts "Invalid serial number"
verify_image $firmwarefile 0x1000000 bin
# Big endian... weee!!!!
- puts "Setting MAC number to $serialnumber"
+ puts "Setting MAC number to $serialnumber"
flash fillw [expr 0x1030000-0x8] "0x[string range $serialnumber 2 3][string range $serialnumber 0 1]0000" 1
flash fillw [expr 0x1030000-0x4] "0x[string range $serialnumber 10 11][string range $serialnumber 8 9][string range $serialnumber 6 7][string range $serialnumber 4 5]" 1
puts "Production successful"
-}
+}
proc production_test {} {
incr x
puts [format "%2d: %5s 0x%08x" $x $AT91C_ID($x) $aaa($x)]
incr x
- }
+ }
foreach REG {
- AIC_IVR AIC_FVR AIC_ISR
+ AIC_IVR AIC_FVR AIC_ISR
AIC_IPR AIC_IMR AIC_CISR AIC_IECR AIC_IDCR
- AIC_ICCR AIC_ISCR AIC_EOICR AIC_SPU AIC_DCR
+ AIC_ICCR AIC_ISCR AIC_EOICR AIC_SPU AIC_DCR
AIC_FFER AIC_FFDR AIC_FFSR } {
if [catch { show_mmr32_reg $REG } msg ] {
error $msg
global BIT16 BIT17
if { $rtpres == 0 } {
set rtpres 65536;
- }
+ }
global AT91C_SLOWOSC_FREQ
# Nasty hack, make this a float by tacking a .0 on the end
# otherwise, jim makes the value an integer
}
proc show_RTTC { } {
-
+
show_mmr32_reg RTTC_RTMR
show_mmr32_reg RTTC_RTAR
show_mmr32_reg RTTC_RTVR
set x [show_normalize_bitfield $VAL 11 9]
set s "unknown"
- switch -exact $x {
+ switch -exact $x {
0 { set s "Even" }
1 { set s "Odd" }
2 { set s "Force=0" }
}
}
puts [format "\tParity: %s " $s]
-
+
set x [expr 5 + [show_normalize_bitfield $VAL 7 6]]
puts [format "\tDatabits: %d" $x]
set n AT91C_BASE_[set WHO]
set str ""
- # Only if it exists on the chip
+ # Only if it exists on the chip
if [ info exists $n ] {
# Hence: $n - is like AT91C_BASE_USx
# For every sub-register
# For every sub-register
-foreach REG {DBGU_CR DBGU_MR DBGU_IER DBGU_IDR DBGU_IMR
+foreach REG {DBGU_CR DBGU_MR DBGU_IER DBGU_IDR DBGU_IMR
DBGU_CSR DBGU_RHR DBGU_THR DBGU_BRGR DBGU_CIDR DBGU_EXID DBGU_FNTR} {
# Create a command for this specific register.
proc show_$REG { } "show_mmr32_reg $REG"
-
+
# Add this command to the Device(as a whole) command
set str "$str\nshow_$REG"
}
error $msg
}
- show_mmr_bitfield 0 0 $val HSI { OFF ON }
+ show_mmr_bitfield 0 0 $val HSI { OFF ON }
show_mmr_bitfield 1 1 $val HSIRDY { NOTRDY RDY }
show_mmr_bitfield 7 3 $val HSITRIM { _NUMBER_ }
show_mmr_bitfield 15 8 $val HSICAL { _NUMBER_ }
show_mmr_bitfield 19 19 $val CSSON { OFF ON }
show_mmr_bitfield 24 24 $val PLLON { OFF ON }
show_mmr_bitfield 25 25 $val PLLRDY { NOTRDY RDY }
-}
-
+}
+
proc show_RCC_CFGR { } {
if [ catch { set val [show_mmr32_reg RCC_CFGR] } msg ] {
error $msg
show_mmr_bitfield 26 24 $val MCO { none none none none SysClk HSI HSE PLL_div2 }
}
-
+
proc show_RCC_CIR { } {
if [ catch { set val [show_mmr32_reg RCC_CIR] } msg ] {
error $msg
}
-
+
}
proc show_RCC_APB2RSTR { } {
set bits(13) xxx
set bits(12) xxx
set bits(11) wwdg
- set bits(10) xxx
+ set bits(10) xxx
set bits(9) xxx
set bits(8) xxx
set bits(7) xxx
set bits(1) tim3
set bits(0) tim2
show_mmr32_bits bits $val
-
+
}
proc show_RCC_AHBENR { } {
set bits(18) xxx
set bits(17) xxx
set bits(16) xxx
- set bits(15) xxx
+ set bits(15) xxx
set bits(14) xxx
set bits(13) xxx
set bits(12) xxx
set bits(18) xxx
set bits(17) xxx
set bits(16) xxx
- set bits(15) adc3
+ set bits(15) adc3
set bits(14) usart1
set bits(13) tim8
set bits(12) spi1
-# MEMORY
+# MEMORY
#
# All Memory regions have two components.
# (1) A count of regions, in the form N_NAME
}
proc address_info { ADDRESS } {
-
+
foreach WHERE { FLASH RAM MMREGS XMEM UNKNOWN } {
if { info exists $WHERE } {
set lmt [set N_[set WHERE]]
} else {
error "memread32: $msg"
}
-}
+}
proc memread16 {ADDR} {
set foo(0) 0
} else {
error "memread16: $msg"
}
-}
+}
proc memread8 {ADDR} {
set foo(0) 0
} else {
error "memread8: $msg"
}
-}
+}
proc memwrite32 {ADDR DATA} {
set foo(0) $DATA
} else {
error "memwrite32: $msg"
}
-}
+}
proc memwrite16 {ADDR DATA} {
set foo(0) $DATA
} else {
error "memwrite16: $msg"
}
-}
+}
proc memwrite8 {ADDR DATA} {
set foo(0) $DATA
} else {
error "memwrite8: $msg"
}
-}
+}
# Give: REGISTER name - must be a global variable.
proc show_mmr32_reg { NAME } {
-
+
global $NAME
# we want $($NAME)
set a [set [set NAME]]
set l [string length $N]
if { $l > $w } { set w $l }
}
-
+
for { set x 24 } { $x >= 0 } { incr x -8 } {
puts -nonewline " "
for { set y 7 } { $y >= 0 } { incr y -1 } {
}
proc isreadable32 { ADDRESS } {
-
\ No newline at end of file
##
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
set _CHIPNAME aduc702x
}
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
# This config file was defaulting to big endian..
set _ENDIAN little
}
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
+if { [info exists CPUTAPID] } {
+ set _CPUTAPID $CPUTAPID
+} else {
set _CPUTAPID 0x3f0f0f0f
}
jtag_ntrst_delay 200
# This is for the case that TRST/SRST is not wired on your JTAG adaptor.
-# Don't really need them anyways.
+# Don't really need them anyways.
reset_config none
## JTAG scan chain
mww 0xb8050000 0x800f00e8 # clr pwrdwn & bypass
mww 0xb8050008 1 # set clock_switch bit
sleep 1 # wait for lock
-
+
# Setup DDR config and flash mapping
mww 0xb8000000 0xefbc8cd0 # DDR cfg cdl val (rst: 0x5bfc8d0)
mww 0xb8000004 0x8e7156a2 # DDR cfg2 cdl val (rst: 0x80d106a8)
-
+
mww 0xb8000010 8 # force precharge all banks
mww 0xb8000010 1 # force EMRS update cycle
mww 0xb800000c 0 # clr ext. mode register
mww 0xb8000020 0
mww 0xb8000024 0
mww 0xb8000028 0
-}
+}
# setup working area somewhere in RAM
$TARGETNAME configure -work-area-phys 0xa0600000 -work-area-size 0x20000
#Script for AT91EB40a
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
set _CHIPNAME at91eb40a
}
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
set _ENDIAN little
}
#SRST reset, which means that the CPU will run a number
#of cycles before it can be halted(as much as milliseconds).
reset_config srst_only srst_pulls_trst
-
+
#jtag scan chain
#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
# Reset script for AT91EB40a
reg cpsr 0x000000D3
mww 0xFFE00020 0x1
- mww 0xFFE00024 0x00000000
- mww 0xFFE00000 0x01002539
- mww 0xFFFFF124 0xFFFFFFFF
+ mww 0xFFE00024 0x00000000
+ mww 0xFFE00000 0x01002539
+ mww 0xFFFFF124 0xFFFFFFFF
mww 0xffff0010 0x100
mww 0xffff0034 0x100
}
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
set _CHIPNAME at9r40008
}
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
set _ENDIAN little
}
reset_config trst_and_srst
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
set _CHIPNAME at91rm9200
}
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
set _ENDIAN little
}
# Create the GDB Target.
set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME arm920t -endian $_ENDIAN -chain-position $_TARGETNAME
+target create $_TARGETNAME arm920t -endian $_ENDIAN -chain-position $_TARGETNAME
# AT91RM9200 has a 16K block of sram @ 0x0020.0000
$_TARGETNAME configure -work-area-virt 0x00200000 -work-area-phys 0x00200000 \
# at91sam3u2c
# at91sam3u1c
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
set _CHIPNAME sam3
}
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
set _ENDIAN little
}
#use combined on interfaces or targets that can't set TRST/SRST separately
reset_config srst_only srst_pulls_trst
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
set _CHIPNAME at91sam7s
}
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
set _ENDIAN little
}
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi
-$_TARGETNAME configure -event reset-init {
+$_TARGETNAME configure -event reset-init {
soft_reset_halt
# RSTC_CR : Reset peripherals
mww 0xfffffd00 0xa5000004
# disable watchdog
- mww 0xfffffd44 0x00008000
+ mww 0xfffffd44 0x00008000
# enable user reset
- mww 0xfffffd08 0xa5000001
+ mww 0xfffffd08 0xa5000001
# CKGR_MOR : enable the main oscillator
- mww 0xfffffc20 0x00000601
+ mww 0xfffffc20 0x00000601
sleep 10
# CKGR_PLLR: 96.1097 MHz
- mww 0xfffffc2c 0x00481c0e
+ mww 0xfffffc2c 0x00481c0e
sleep 10
# PMC_MCKR : MCK = PLL / 2 ~= 48 MHz
- mww 0xfffffc30 0x00000007
+ mww 0xfffffc30 0x00000007
sleep 10
# MC_FMR: flash mode (FWS=1,FMCN=73)
- mww 0xffffff60 0x00490100
- sleep 100
+ mww 0xffffff60 0x00490100
+ sleep 100
}
$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x00200000 -work-area-size 0x4000 -work-area-backup 0
# Target: Atmel AT91SAM9260
######################################
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
set _CHIPNAME at91sam9260
}
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
set _ENDIAN little
}
# Target: Atmel AT91SAM9260
######################################
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
set _CHIPNAME at91sam9260
}
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
set _ENDIAN little
}
proc at91sam_init { } {
-
+
# at reset chip runs at 32khz
jtag_khz 8
halt
# assume no PLL lock, start slowly
jtag_khz 100
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
set _CHIPNAME c100
}
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
set _ENDIAN little
}
# set CFG_REFCLKFREQ [configC100 CFG_REFCLKFREQ]
proc config {label} {
- return [dict get [configC100] $label ]
+ return [dict get [configC100] $label ]
}
# show the value for the param. with label
# when there are more then one board config
# use soft links to c100board-config.tcl
# so that only the right board-config gets
-# included (just like include/configs/board-configs.h
+# included (just like include/configs/board-configs.h
# in u-boot.
proc configC100 {} {
# xtal freq. 24MHz
# y = amba_clk * (w+1)*(x+1)*2/xtal_clk
dict set configC100 y_amba [expr ([dict get $configC100 CONFIG_SYS_HZ_CLOCK] * ( ([dict get $configC100 w_amba]+1 ) * ([dict get $configC100 x_amba]+1 ) *2 ) / [dict get $configC100 CFG_REFCLKFREQ]) ]
- # Arm Clk 450MHz, must be a multiple of 25 MHz
+ # Arm Clk 450MHz, must be a multiple of 25 MHz
dict set configC100 CFG_ARM_CLOCK 450000000
dict set configC100 w_arm 0
dict set configC100 x_arm 1
proc setupNOR {} {
puts "Setting up NOR: 16MB, 16-bit wide bus, CS0"
# this is taken from u-boot/boards/mindspeed/ooma-darwin/board.c:nor_hw_init()
- set EX_CSEN_REG [regs EX_CSEN_REG ]
- set EX_CS0_SEG_REG [regs EX_CS0_SEG_REG ]
- set EX_CS0_CFG_REG [regs EX_CS0_CFG_REG ]
- set EX_CS0_TMG1_REG [regs EX_CS0_TMG1_REG ]
- set EX_CS0_TMG2_REG [regs EX_CS0_TMG2_REG ]
- set EX_CS0_TMG3_REG [regs EX_CS0_TMG3_REG ]
+ set EX_CSEN_REG [regs EX_CSEN_REG ]
+ set EX_CS0_SEG_REG [regs EX_CS0_SEG_REG ]
+ set EX_CS0_CFG_REG [regs EX_CS0_CFG_REG ]
+ set EX_CS0_TMG1_REG [regs EX_CS0_TMG1_REG ]
+ set EX_CS0_TMG2_REG [regs EX_CS0_TMG2_REG ]
+ set EX_CS0_TMG3_REG [regs EX_CS0_TMG3_REG ]
set EX_CLOCK_DIV_REG [regs EX_CLOCK_DIV_REG ]
- set EX_MFSM_REG [regs EX_MFSM_REG ]
- set EX_CSFSM_REG [regs EX_CSFSM_REG ]
- set EX_WRFSM_REG [regs EX_WRFSM_REG ]
- set EX_RDFSM_REG [regs EX_RDFSM_REG ]
+ set EX_MFSM_REG [regs EX_MFSM_REG ]
+ set EX_CSFSM_REG [regs EX_CSFSM_REG ]
+ set EX_WRFSM_REG [regs EX_WRFSM_REG ]
+ set EX_RDFSM_REG [regs EX_RDFSM_REG ]
# enable Expansion Bus Clock + CS0 (NOR)
mww $EX_CSEN_REG 0x3
# set timings to NOR
mww $EX_CS0_TMG1_REG 0x03034006
mww $EX_CS0_TMG2_REG 0x04040002
- #mww $EX_CS0_TMG3_REG
+ #mww $EX_CS0_TMG3_REG
# set EBUS clock 165/5=33MHz
mww $EX_CLOCK_DIV_REG 0x5
# everthing else is OK with default
set EXP_CS0_BASEADDR [regs EXP_CS0_BASEADDR]
set BLOCK_RESET_REG [regs BLOCK_RESET_REG]
set DDR_RST [regs DDR_RST]
-
+
# put DDR controller in reset (so that it comes reset in u-boot)
mmw $BLOCK_RESET_REG 0x0 $DDR_RST
# setup CS0 controller for NOR
#GPIO17 reset for DECT module.
#GPIO29 CS_n for NAND
- set GPIO_OUTPUT_REG [regs GPIO_OUTPUT_REG]
- set GPIO_OE_REG [regs GPIO_OE_REG]
+ set GPIO_OUTPUT_REG [regs GPIO_OUTPUT_REG]
+ set GPIO_OE_REG [regs GPIO_OE_REG]
# set GPIO29=GPIO17=1, GPIO5=0
mww $GPIO_OUTPUT_REG [expr 1<<29 | 1<<17]
proc highGPIO5 {} {
puts "GPIO5 high"
- set GPIO_OUTPUT_REG [regs GPIO_OUTPUT_REG]
+ set GPIO_OUTPUT_REG [regs GPIO_OUTPUT_REG]
# set GPIO5=1
mmw $GPIO_OUTPUT_REG [expr 1 << 5] 0x0
}
proc lowGPIO5 {} {
puts "GPIO5 low"
- set GPIO_OUTPUT_REG [regs GPIO_OUTPUT_REG]
+ set GPIO_OUTPUT_REG [regs GPIO_OUTPUT_REG]
# set GPIO5=0
mmw $GPIO_OUTPUT_REG 0x0 [expr 1 << 5]
}
proc boardID {id} {
# so far built:
# 4'b1111
- dict set boardID 15 name "EVT1"
+ dict set boardID 15 name "EVT1"
dict set boardID 15 ddr2size 128M
# dict set boardID 15 nandsize 1G
# dict set boardID 15 norsize 16M
# 4'b0000
- dict set boardID 0 name "EVT2"
+ dict set boardID 0 name "EVT2"
dict set boardID 0 ddr2size 128M
# 4'b0001
- dict set boardID 1 name "EVT3"
+ dict set boardID 1 name "EVT3"
dict set boardID 1 ddr2size 256M
# 4'b1110
dict set boardID 14 name "EVT3_old"
dict set boardID 14 ddr2size 128M
# 4'b0010
- dict set boardID 2 name "EVT4"
+ dict set boardID 2 name "EVT4"
dict set boardID 2 ddr2size 256M
return $boardID
}
# converted from u-boot/boards/mindspeed/ooma-darwin/board.c:ooma_board_detect()
-# figure out what board revision this is, uses BOOTSTRAP register to read stuffed resistors
+# figure out what board revision this is, uses BOOTSTRAP register to read stuffed resistors
proc ooma_board_detect {} {
set GPIO_BOOTSTRAP_REG [regs GPIO_BOOTSTRAP_REG]
-
+
# read the current value of the BOOTSRAP pins
set tmp [mrw $GPIO_BOOTSTRAP_REG]
puts [format "GPIO_BOOTSTRAP_REG (0x%x): 0x%x" $GPIO_BOOTSTRAP_REG $tmp]
set DENALI_CTL_20_DATA [regs DENALI_CTL_20_DATA]
- set DENALI_CTL_02_VAL 0x0100010000010100
+ set DENALI_CTL_02_VAL 0x0100010000010100
set DENALI_CTL_11_VAL 0x433A42124A650A37
- # set some default values
+ # set some default values
mw64bit $DENALI_CTL_00_DATA 0x0100000101010101
mw64bit $DENALI_CTL_01_DATA 0x0100000100000101
mw64bit $DENALI_CTL_02_DATA $DENALI_CTL_02_VAL
# wait int_status[2] (DRAM init complete)
puts -nonewline "Waiting for DDR2 controller to init..."
set tmp [mrw [expr $DENALI_CTL_08_DATA + 4]]
- while { [expr $tmp & 0x040000] == 0 } {
+ while { [expr $tmp & 0x040000] == 0 } {
sleep 1
set tmp [mrw [expr $DENALI_CTL_08_DATA + 4]]
}
set GPIO_IOCTRL_REG [regs GPIO_IOCTRL_REG]
set GPIO_IOCTRL_VAL [regs GPIO_IOCTRL_VAL]
set GPIO_IOCTRL_UART0 [regs GPIO_IOCTRL_UART0]
- set UART0_LCR [regs UART0_LCR]
- set LCR_DLAB [regs LCR_DLAB]
- set UART0_DLL [regs UART0_DLL]
- set UART0_DLH [regs UART0_DLH]
- set UART0_IIR [regs UART0_IIR]
- set UART0_IER [regs UART0_IER]
- set LCR_ONE_STOP [regs LCR_ONE_STOP]
- set LCR_CHAR_LEN_8 [regs LCR_CHAR_LEN_8]
+ set UART0_LCR [regs UART0_LCR]
+ set LCR_DLAB [regs LCR_DLAB]
+ set UART0_DLL [regs UART0_DLL]
+ set UART0_DLH [regs UART0_DLH]
+ set UART0_IIR [regs UART0_IIR]
+ set UART0_IER [regs UART0_IER]
+ set LCR_ONE_STOP [regs LCR_ONE_STOP]
+ set LCR_CHAR_LEN_8 [regs LCR_CHAR_LEN_8]
set FCR_XMITRES [regs FCR_XMITRES]
- set FCR_RCVRRES [regs FCR_RCVRRES]
- set FCR_FIFOEN [regs FCR_FIFOEN]
- set IER_UUE [regs IER_UUE]
+ set FCR_RCVRRES [regs FCR_RCVRRES]
+ set FCR_FIFOEN [regs FCR_FIFOEN]
+ set IER_UUE [regs IER_UUE]
# unlock writing to IOCTRL register
mww $GPIO_LOCK_REG $GPIO_IOCTRL_VAL
proc putcUART0 {char} {
- set UART0_LSR [regs UART0_LSR]
+ set UART0_LSR [regs UART0_LSR]
set UART0_THR [regs UART0_THR]
set LSR_TEMT [regs LSR_TEMT]
proc flashUBOOT {} {
# this will update uboot on NOR partition
set EXP_CS0_BASEADDR [regs EXP_CS0_BASEADDR]
-
+
# setup CS0 controller for NOR
setupNOR
# make sure we are accessing the lower part of NOR
proc showNOR {} {
puts "This is the current NOR setup"
- set EX_CSEN_REG [regs EX_CSEN_REG ]
- set EX_CS0_SEG_REG [regs EX_CS0_SEG_REG ]
- set EX_CS0_CFG_REG [regs EX_CS0_CFG_REG ]
- set EX_CS0_TMG1_REG [regs EX_CS0_TMG1_REG ]
- set EX_CS0_TMG2_REG [regs EX_CS0_TMG2_REG ]
- set EX_CS0_TMG3_REG [regs EX_CS0_TMG3_REG ]
+ set EX_CSEN_REG [regs EX_CSEN_REG ]
+ set EX_CS0_SEG_REG [regs EX_CS0_SEG_REG ]
+ set EX_CS0_CFG_REG [regs EX_CS0_CFG_REG ]
+ set EX_CS0_TMG1_REG [regs EX_CS0_TMG1_REG ]
+ set EX_CS0_TMG2_REG [regs EX_CS0_TMG2_REG ]
+ set EX_CS0_TMG3_REG [regs EX_CS0_TMG3_REG ]
set EX_CLOCK_DIV_REG [regs EX_CLOCK_DIV_REG ]
- set EX_MFSM_REG [regs EX_MFSM_REG ]
- set EX_CSFSM_REG [regs EX_CSFSM_REG ]
- set EX_WRFSM_REG [regs EX_WRFSM_REG ]
- set EX_RDFSM_REG [regs EX_RDFSM_REG ]
+ set EX_MFSM_REG [regs EX_MFSM_REG ]
+ set EX_CSFSM_REG [regs EX_CSFSM_REG ]
+ set EX_WRFSM_REG [regs EX_WRFSM_REG ]
+ set EX_RDFSM_REG [regs EX_RDFSM_REG ]
puts [format "EX_CSEN_REG (0x%x): 0x%x" $EX_CSEN_REG [mrw $EX_CSEN_REG]]
puts [format "EX_CS0_SEG_REG (0x%x): 0x%x" $EX_CS0_SEG_REG [mrw $EX_CS0_SEG_REG]]
proc showGPIO {} {
puts "This is the current GPIO register setup"
# GPIO outputs register
- set GPIO_OUTPUT_REG [regs GPIO_OUTPUT_REG]
+ set GPIO_OUTPUT_REG [regs GPIO_OUTPUT_REG]
# GPIO Output Enable register
- set GPIO_OE_REG [regs GPIO_OE_REG]
- set GPIO_HI_INT_ENABLE_REG [regs GPIO_HI_INT_ENABLE_REG]
- set GPIO_LO_INT_ENABLE_REG [regs GPIO_LO_INT_ENABLE_REG]
+ set GPIO_OE_REG [regs GPIO_OE_REG]
+ set GPIO_HI_INT_ENABLE_REG [regs GPIO_HI_INT_ENABLE_REG]
+ set GPIO_LO_INT_ENABLE_REG [regs GPIO_LO_INT_ENABLE_REG]
# GPIO input register
- set GPIO_INPUT_REG [regs GPIO_INPUT_REG]
- set APB_ACCESS_WS_REG [regs APB_ACCESS_WS_REG]
- set MUX_CONF_REG [regs MUX_CONF_REG]
- set SYSCONF_REG [regs SYSCONF_REG]
- set GPIO_ARM_ID_REG [regs GPIO_ARM_ID_REG]
- set GPIO_BOOTSTRAP_REG [regs GPIO_BOOTSTRAP_REG]
- set GPIO_LOCK_REG [regs GPIO_LOCK_REG]
- set GPIO_IOCTRL_REG [regs GPIO_IOCTRL_REG]
- set GPIO_DEVID_REG [regs GPIO_DEVID_REG]
+ set GPIO_INPUT_REG [regs GPIO_INPUT_REG]
+ set APB_ACCESS_WS_REG [regs APB_ACCESS_WS_REG]
+ set MUX_CONF_REG [regs MUX_CONF_REG]
+ set SYSCONF_REG [regs SYSCONF_REG]
+ set GPIO_ARM_ID_REG [regs GPIO_ARM_ID_REG]
+ set GPIO_BOOTSTRAP_REG [regs GPIO_BOOTSTRAP_REG]
+ set GPIO_LOCK_REG [regs GPIO_LOCK_REG]
+ set GPIO_IOCTRL_REG [regs GPIO_IOCTRL_REG]
+ set GPIO_DEVID_REG [regs GPIO_DEVID_REG]
puts [format "GPIO_OUTPUT_REG (0x%x): 0x%x" $GPIO_OUTPUT_REG [mrw $GPIO_OUTPUT_REG]]
puts [format "GPIO_OE_REG (0x%x): 0x%x" $GPIO_OE_REG [mrw $GPIO_OE_REG]]
set CFG_REFCLKFREQ [config CFG_REFCLKFREQ]
set CLKCORE_AHB_CLK_CNTRL [regs CLKCORE_AHB_CLK_CNTRL]
set PLL_CLK_BYPASS [regs PLL_CLK_BYPASS]
-
+
puts [format "CLKCORE_AHB_CLK_CNTRL (0x%x): 0x%x" $CLKCORE_AHB_CLK_CNTRL [mrw $CLKCORE_AHB_CLK_CNTRL]]
ocd_mem2array value 32 $CLKCORE_AHB_CLK_CNTRL 1
# see if the PLL is in bypass mode
# converted from u-boot/cpu/arm1136/comcerto/bsp100.c (HAL_set_amba_clk())
# this clock is useb by all peripherals (DDR2, ethernet, ebus, etc)
proc setupAmbaClk {} {
- set CLKCORE_PLL_STATUS [regs CLKCORE_PLL_STATUS]
+ set CLKCORE_PLL_STATUS [regs CLKCORE_PLL_STATUS]
set CLKCORE_AHB_CLK_CNTRL [regs CLKCORE_AHB_CLK_CNTRL]
set ARM_PLL_BY_CTRL [regs ARM_PLL_BY_CTRL]
set ARM_AHB_BYP [regs ARM_AHB_BYP]
set PLL_DISABLE [regs PLL_DISABLE]
- set PLL_CLK_BYPASS [regs PLL_CLK_BYPASS]
- set AHB_PLL_BY_CTRL [regs AHB_PLL_BY_CTRL]
+ set PLL_CLK_BYPASS [regs PLL_CLK_BYPASS]
+ set AHB_PLL_BY_CTRL [regs AHB_PLL_BY_CTRL]
set DIV_BYPASS [regs DIV_BYPASS]
set AHBCLK_PLL_LOCK [regs AHBCLK_PLL_LOCK]
set CFG_REFCLKFREQ [config CFG_REFCLKFREQ]
set CFG_REFCLKFREQ [config CFG_REFCLKFREQ]
set CLKCORE_ARM_CLK_CNTRL [regs CLKCORE_ARM_CLK_CNTRL]
set PLL_CLK_BYPASS [regs PLL_CLK_BYPASS]
-
+
puts [format "CLKCORE_ARM_CLK_CNTRL (0x%x): 0x%x" $CLKCORE_ARM_CLK_CNTRL [mrw $CLKCORE_ARM_CLK_CNTRL]]
ocd_mem2array value 32 $CLKCORE_ARM_CLK_CNTRL 1
# see if the PLL is in bypass mode
set ARM_PLL_BY_CTRL [regs ARM_PLL_BY_CTRL]
set ARM_AHB_BYP [regs ARM_AHB_BYP]
set PLL_DISABLE [regs PLL_DISABLE]
- set PLL_CLK_BYPASS [regs PLL_CLK_BYPASS]
- set AHB_PLL_BY_CTRL [regs AHB_PLL_BY_CTRL]
+ set PLL_CLK_BYPASS [regs PLL_CLK_BYPASS]
+ set AHB_PLL_BY_CTRL [regs AHB_PLL_BY_CTRL]
set DIV_BYPASS [regs DIV_BYPASS]
set FCLK_PLL_LOCK [regs FCLK_PLL_LOCK]
set CFG_REFCLKFREQ [config CFG_REFCLKFREQ]
# converted from u-boot/cpu/arm1136/bsp100.c:SoC_mem_init()
proc setupDDR2 {} {
puts "Configuring DDR2"
-
+
set MEMORY_BASE_ADDR [regs MEMORY_BASE_ADDR]
- set MEMORY_MAX_ADDR [regs MEMORY_MAX_ADDR]
+ set MEMORY_MAX_ADDR [regs MEMORY_MAX_ADDR]
set MEMORY_CR [regs MEMORY_CR]
- set BLOCK_RESET_REG [regs BLOCK_RESET_REG]
- set DDR_RST [regs DDR_RST]
+ set BLOCK_RESET_REG [regs BLOCK_RESET_REG]
+ set DDR_RST [regs DDR_RST]
# put DDR controller in reset (so that it is reset and correctly configured)
# this is only necessary if DDR was previously confiured
proc showDDR2 {} {
-
+
set DENALI_CTL_00_DATA [regs DENALI_CTL_00_DATA]
set DENALI_CTL_01_DATA [regs DENALI_CTL_01_DATA]
set DENALI_CTL_02_DATA [regs DENALI_CTL_02_DATA]
puts [format "DENALI_CTL_19_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_19_DATA $tmp(1) $tmp(0)]
set tmp [mr64bit $DENALI_CTL_20_DATA]
puts [format "DENALI_CTL_20_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_20_DATA $tmp(1) $tmp(0)]
-
+
}
proc initC100 {} {
- # this follows u-boot/cpu/arm1136/start.S
- set GPIO_LOCK_REG [regs GPIO_LOCK_REG]
- set GPIO_IOCTRL_REG [regs GPIO_IOCTRL_REG]
- set GPIO_IOCTRL_VAL [regs GPIO_IOCTRL_VAL]
+ # this follows u-boot/cpu/arm1136/start.S
+ set GPIO_LOCK_REG [regs GPIO_LOCK_REG]
+ set GPIO_IOCTRL_REG [regs GPIO_IOCTRL_REG]
+ set GPIO_IOCTRL_VAL [regs GPIO_IOCTRL_VAL]
set APB_ACCESS_WS_REG [regs APB_ACCESS_WS_REG]
set ASA_ARAM_BASEADDR [regs ASA_ARAM_BASEADDR]
- set ASA_ARAM_TC_CR_REG [regs ASA_ARAM_TC_CR_REG]
+ set ASA_ARAM_TC_CR_REG [regs ASA_ARAM_TC_CR_REG]
set ASA_EBUS_BASEADDR [regs ASA_EBUS_BASEADDR]
- set ASA_EBUS_TC_CR_REG [regs ASA_EBUS_TC_CR_REG]
+ set ASA_EBUS_TC_CR_REG [regs ASA_EBUS_TC_CR_REG]
set ASA_TC_REQIDMAEN [regs ASA_TC_REQIDMAEN]
- set ASA_TC_REQTDMEN [regs ASA_TC_REQTDMEN]
- set ASA_TC_REQIPSECUSBEN [regs ASA_TC_REQIPSECUSBEN]
+ set ASA_TC_REQTDMEN [regs ASA_TC_REQTDMEN]
+ set ASA_TC_REQIPSECUSBEN [regs ASA_TC_REQIPSECUSBEN]
set ASA_TC_REQARM0EN [regs ASA_TC_REQARM0EN]
set ASA_TC_REQARM1EN [regs ASA_TC_REQARM1EN]
set ASA_TC_REQMDMAEN [regs ASA_TC_REQMDMAEN]
# set ARM into supervisor mode (SVC32)
# disable IRQ, FIQ
# Do I need this in JTAG mode?
- # it really should be done as 'and ~0x1f | 0xd3 but
+ # it really should be done as 'and ~0x1f | 0xd3 but
# openocd does not support this yet
reg cpsr 0xd3
# /*
# * disable MMU stuff and caches
# */
# mrc p15, 0, r0, c1, c0, 0
- arm11 mrc c100.cpu 15 0 1 0 0
+ arm11 mrc c100.cpu 15 0 1 0 0
# bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
# bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
# orr r0, r0, #0x00000002 @ set bit 2 (A) Align
# orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
- # orr r0, r0, #0x00400000 @ set bit 22 (U)
+ # orr r0, r0, #0x00400000 @ set bit 22 (U)
# mcr p15, 0, r0, c1, c0, 0
arm11 mcr c100.cpu 15 0 1 0 0 0x401002
# This is from bsp_init() in u-boot/boards/mindspeed/ooma-darwin/board.c
mmw $ASA_EBUS_TC_CR_REG [expr $ASA_TC_REQIDMAEN | $ASA_TC_REQTDMEN | $ASA_TC_REQIPSECUSBEN | $ASA_TC_REQARM0EN | $ASA_TC_REQARM1EN | $ASA_TC_REQMDMAEN] 0x0
# ARAM init
- # // disable pipeline mode in ARAM
+ # // disable pipeline mode in ARAM
# I don't think this is documented anywhere?
mww $INTC_ARM1_CONTROL_REG 0x1
- # configure clocks
+ # configure clocks
setupPLL
# enable cache
# ? (u-boot does nothing here)
# show current state of watchdog timer
proc showWatchdog {} {
set TIMER_WDT_HIGH_BOUND [regs TIMER_WDT_HIGH_BOUND]
- set TIMER_WDT_CONTROL [regs TIMER_WDT_CONTROL]
+ set TIMER_WDT_CONTROL [regs TIMER_WDT_CONTROL]
set TIMER_WDT_CURRENT_COUNT [regs TIMER_WDT_CURRENT_COUNT]
-
+
puts [format "TIMER_WDT_HIGH_BOUND (0x%x): 0x%x" $TIMER_WDT_HIGH_BOUND [mrw $TIMER_WDT_HIGH_BOUND]]
puts [format "TIMER_WDT_CONTROL (0x%x): 0x%x" $TIMER_WDT_CONTROL [mrw $TIMER_WDT_CONTROL]]
puts [format "TIMER_WDT_CURRENT_COUNT (0x%x): 0x%x" $TIMER_WDT_CURRENT_COUNT [mrw $TIMER_WDT_CURRENT_COUNT]]
# watchdog reset effectively works as hw. reset
proc reboot {} {
set TIMER_WDT_HIGH_BOUND [regs TIMER_WDT_HIGH_BOUND]
- set TIMER_WDT_CONTROL [regs TIMER_WDT_CONTROL]
+ set TIMER_WDT_CONTROL [regs TIMER_WDT_CONTROL]
set TIMER_WDT_CURRENT_COUNT [regs TIMER_WDT_CURRENT_COUNT]
# allow the counter to count to high value before triggering
mww $TIMER_WDT_CONTROL 0x1
# wait until the reset
puts -nonewline "Wating for watchdog to trigger..."
- #while {[mrw $TIMER_WDT_CONTROL] == 1} {
- # puts [format "TIMER_WDT_CURRENT_COUNT (0x%x): 0x%x" $TIMER_WDT_CURRENT_COUNT [mrw $TIMER_WDT_CURRENT_COUNT]]
- # sleep 1
- #
+ #while {[mrw $TIMER_WDT_CONTROL] == 1} {
+ # puts [format "TIMER_WDT_CURRENT_COUNT (0x%x): 0x%x" $TIMER_WDT_CURRENT_COUNT [mrw $TIMER_WDT_CURRENT_COUNT]]
+ # sleep 1
+ #
#}
while {[c100.cpu curstate] != "running"} { sleep 1}
puts "done."
# For example:
# set EX_CS_TMG1_REG [regs EX_CS0_TMG1_REG]
proc regs {reg} {
- return [dict get [regsC100] $reg ]
+ return [dict get [regsC100] $reg ]
}
proc showreg {reg} {
#/* device memory base addresses */
#// device memory sizes
#/* ARAM SIZE=64K */
-dict set regsC100 ARAM_SIZE 0x00010000
+dict set regsC100 ARAM_SIZE 0x00010000
dict set regsC100 ARAM_BASEADDR 0x0A000000
#/* Hardware Interface Units */
dict set regsC100 APB_BASEADDR 0x10000000
#/* APB_SIZE=16M address range */
-dict set regsC100 APB_SIZE 0x01000000
+dict set regsC100 APB_SIZE 0x01000000
dict set regsC100 EXP_CS0_BASEADDR 0x20000000
dict set regsC100 EXP_CS1_BASEADDR 0x24000000
# GPIO outputs register
dict set regsC100 GPIO_OUTPUT_REG [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x00]
-# GPIO Output Enable register
+# GPIO Output Enable register
dict set regsC100 GPIO_OE_REG [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x04]
dict set regsC100 GPIO_HI_INT_ENABLE_REG [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x08]
dict set regsC100 GPIO_LO_INT_ENABLE_REG [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x0C]
dict set regsC100 UART1_SCR [expr [dict get $regsC100 UART1_BASEADDR ] + 0x1C]
# /* default */
-dict set regsC100 LCR_CHAR_LEN_5 0x00
+dict set regsC100 LCR_CHAR_LEN_5 0x00
dict set regsC100 LCR_CHAR_LEN_6 0x01
dict set regsC100 LCR_CHAR_LEN_7 0x02
dict set regsC100 LCR_CHAR_LEN_8 0x03
#/* One stop bit! - default */
dict set regsC100 LCR_ONE_STOP 0x00
-#/* Two stop bit! */
-dict set regsC100 LCR_TWO_STOP 0x04
+#/* Two stop bit! */
+dict set regsC100 LCR_TWO_STOP 0x04
#/* Parity Enable */
-dict set regsC100 LCR_PEN 0x08
+dict set regsC100 LCR_PEN 0x08
dict set regsC100 LCR_PARITY_NONE 0x00
#/* Even Parity Select */
-dict set regsC100 LCR_EPS 0x10
+dict set regsC100 LCR_EPS 0x10
#/* Enable Parity Stuff */
-dict set regsC100 LCR_PS 0x20
+dict set regsC100 LCR_PS 0x20
#/* Start Break */
-dict set regsC100 LCR_SBRK 0x40
+dict set regsC100 LCR_SBRK 0x40
#/* Parity Stuff Bit */
-dict set regsC100 LCR_PSB 0x80
+dict set regsC100 LCR_PSB 0x80
#/* UART 16550 Divisor Latch Assess */
-dict set regsC100 LCR_DLAB 0x80
+dict set regsC100 LCR_DLAB 0x80
#/* FIFO Error Status */
-dict set regsC100 LSR_FIFOE [expr 1 << 7]
+dict set regsC100 LSR_FIFOE [expr 1 << 7]
#/* Transmitter Empty */
dict set regsC100 LSR_TEMT [expr 1 << 6]
#/* Transmit Data Request */
-dict set regsC100 LSR_TDRQ [expr 1 << 5]
+dict set regsC100 LSR_TDRQ [expr 1 << 5]
#/* Break Interrupt */
-dict set regsC100 LSR_BI [expr 1 << 4]
+dict set regsC100 LSR_BI [expr 1 << 4]
#/* Framing Error */
-dict set regsC100 LSR_FE [expr 1 << 3]
+dict set regsC100 LSR_FE [expr 1 << 3]
#/* Parity Error */
-dict set regsC100 LSR_PE [expr 1 << 2]
+dict set regsC100 LSR_PE [expr 1 << 2]
#/* Overrun Error */
-dict set regsC100 LSR_OE [expr 1 << 1]
+dict set regsC100 LSR_OE [expr 1 << 1]
#/* Data Ready */
-dict set regsC100 LSR_DR [expr 1 << 0]
+dict set regsC100 LSR_DR [expr 1 << 0]
#/* DMA Requests Enable */
-dict set regsC100 IER_DMAE [expr 1 << 7]
+dict set regsC100 IER_DMAE [expr 1 << 7]
#/* UART Unit Enable */
-dict set regsC100 IER_UUE [expr 1 << 6]
+dict set regsC100 IER_UUE [expr 1 << 6]
#/* NRZ coding Enable */
-dict set regsC100 IER_NRZE [expr 1 << 5]
+dict set regsC100 IER_NRZE [expr 1 << 5]
#/* Receiver Time Out Interrupt Enable */
-dict set regsC100 IER_RTIOE [expr 1 << 4]
+dict set regsC100 IER_RTIOE [expr 1 << 4]
#/* Modem Interrupt Enable */
-dict set regsC100 IER_MIE [expr 1 << 3]
+dict set regsC100 IER_MIE [expr 1 << 3]
#/* Receiver Line Status Interrupt Enable */
-dict set regsC100 IER_RLSE [expr 1 << 2]
+dict set regsC100 IER_RLSE [expr 1 << 2]
#/* Transmit Data request Interrupt Enable */
-dict set regsC100 IER_TIE [expr 1 << 1]
+dict set regsC100 IER_TIE [expr 1 << 1]
#/* Receiver Data Available Interrupt Enable */
-dict set regsC100 IER_RAVIE [expr 1 << 0]
+dict set regsC100 IER_RAVIE [expr 1 << 0]
#/* FIFO Mode Enable Status */
-dict set regsC100 IIR_FIFOES1 [expr 1 << 7]
+dict set regsC100 IIR_FIFOES1 [expr 1 << 7]
#/* FIFO Mode Enable Status */
-dict set regsC100 IIR_FIFOES0 [expr 1 << 6]
+dict set regsC100 IIR_FIFOES0 [expr 1 << 6]
#/* Time Out Detected */
-dict set regsC100 IIR_TOD [expr 1 << 3]
+dict set regsC100 IIR_TOD [expr 1 << 3]
#/* Interrupt Source Encoded */
-dict set regsC100 IIR_IID2 [expr 1 << 2]
+dict set regsC100 IIR_IID2 [expr 1 << 2]
#/* Interrupt Source Encoded */
-dict set regsC100 IIR_IID1 [expr 1 << 1]
+dict set regsC100 IIR_IID1 [expr 1 << 1]
#/* Interrupt Pending (active low) */
-dict set regsC100 IIR_IP [expr 1 << 0]
+dict set regsC100 IIR_IP [expr 1 << 0]
#/* UART 16550 FIFO Control Register */
dict set regsC100 FCR_FIFOEN 0x01
#/* Interrupt Enable Register */
#// UART 16550
#// Enable Received Data Available Interrupt
-dict set regsC100 IER_RXTH 0x01
+dict set regsC100 IER_RXTH 0x01
#// Enable Transmitter Empty Interrupt
-dict set regsC100 IER_TXTH 0x02
+dict set regsC100 IER_TXTH 0x02
#////////////////////////////////////////////////////////////
-#// CLK + RESET block
+#// CLK + RESET block
#////////////////////////////////////////////////////////////
dict set regsC100 CLKCORE_ARM_CLK_CNTRL [expr [dict get $regsC100 CLKCORE_BASEADDR ] + 0x00]
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
set _CHIPNAME cs351x
}
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
set _ENDIAN little
}
# Cirrus Logic EP9301 processor on an Olimex CS-E9301 board.
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
set _CHIPNAME ep9301
}
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
set _ENDIAN little
}
# Target: Marvell Feroceon CPU core
######################################
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
set _CHIPNAME feroceon
}
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
set _ENDIAN little
}
# Hmmm.... should srst_pulls_trst be used here like i.MX27???
reset_config trst_and_srst
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
set _CHIPNAME imx21
}
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
set _ENDIAN little
}
-# Note above there is 1 tap
+# Note above there is 1 tap
# The CPU tap
if { [info exists CPUTAPID ] } {
# failing, etc.
reset_config trst_and_srst srst_pulls_trst
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
set _CHIPNAME imx27
}
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
set _ENDIAN little
}
-# Note above there are 2 taps
+# Note above there are 2 taps
# The bs tap
if { [info exists BSTAPID ] } {
reset_config trst_and_srst
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
set _CHIPNAME imx31
}
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
set _ENDIAN little
}
}
#========================================
-# The "system jtag controller"
+# The "system jtag controller"
# IMX31 reference manual, page 6-28 - figure 6-14
if { [info exists SJCTAPID ] } {
set _SJCTAPID $SJCTAPID
# See diagram: 6-14
# SIGNAL NAME:
# SJC_MOD - controls multiplexer - disables ARM1136
-# SDMA_BYPASS - disables SDMA -
-#
+# SDMA_BYPASS - disables SDMA -
+#
# Per ARM: DDI0211J_arm1136_r1p5_trm.pdf - the ARM 1136 as a 5 bit IR register
jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUTAPID
target create $_TARGETNAME arm11 -endian $_ENDIAN -chain-position $_TARGETNAME
-proc power_restore {} { puts "Sensed power restore. No action." }
+proc power_restore {} { puts "Sensed power restore. No action." }
proc srst_deasserted {} { puts "Sensed nSRST deasserted. No action." }
# imx35 config
#
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
set _CHIPNAME imx35
}
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
set _ENDIAN little
}
}
#========================================
-# The "system jtag controller"
+# The "system jtag controller"
# IMX31 reference manual, page 6-28 - figure 6-14
if { [info exists SJCTAPID ] } {
set _SJCTAPID $SJCTAPID
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME arm11 -endian $_ENDIAN -chain-position $_TARGETNAME
-proc power_restore {} { puts "Sensed power restore. No action." }
+proc power_restore {} { puts "Sensed power restore. No action." }
proc srst_deasserted {} { puts "Sensed nSRST deasserted. No action." }
# AKA: Atmel AT76C114 - an ARM946 chip
# ATMEL sold his product line to Insilica...
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
set _CHIPNAME is5114
}
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
# this defaults to a little endian
set _ENDIAN little
}
# Do not specify a tap id here...
#OLD SYNTAX: jtag_device 8 0x1 0x1 0xfe
-jtag newtap $_CHIPNAME unknown1 -irlen 8 -ircapture 0x01 -irmask 1
+jtag newtap $_CHIPNAME unknown1 -irlen 8 -ircapture 0x01 -irmask 1
#OLD SYNTAX: jtag_device 4 0x1 0xf 0xe
# This is the "arm946" chip.
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x0e -irmask 0xf
jtag newtap $_CHIPNAME unknown2 -irlen 5 -ircapture 1 -irmask 1
-#arm946e-s and
+#arm946e-s and
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME arm966e -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm966e
#xscale ixp42x CPU
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
set _CHIPNAME ixp42x
}
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
# this defaults to a bigendian
set _ENDIAN big
}
# Script for TI/Luminary Stellaris LM3S1968
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
set _CHIPNAME lm3s1968
}
# TI/Luminary Stellaris lm3s3748
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
set _CHIPNAME lm3s3748
}
# TI/Luminary Stellaris lm3s6965
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
set _CHIPNAME lm3s6965
}
# Script for TI/Luminary Stellaris LM3S811
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
set _CHIPNAME lm3s811
}
# http://www.luminarymicro.com/products/lm3s9b92.htm
#
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
set _CHIPNAME lm3s9b9x
}
# NXP LPC2103 ARM7TDMI-S with 32kB Flash and 8kB SRAM, clocked with 12MHz crystal
-if { [info exists CHIPNAME] } {
+if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME lpc2103
if { [info exists CPUTAPID ] } {
set _CPUTAPID $CPUTAPID
} else {
- set _CPUTAPID 0x4f1f0f0f
+ set _CPUTAPID 0x4f1f0f0f
}
# LPC2000 -> SRST causes TRST
#LPC-2129 CPU
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
set _CHIPNAME lpc2129
}
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
set _ENDIAN little
}
-# Use RCLK. If RCLK is not available fall back to 500kHz.
-#
+# Use RCLK. If RCLK is not available fall back to 500kHz.
+#
# Depending on cabling you might be able to eek this up to 2000kHz.
jtag_rclk 500
-if { [info exists CHIPNAME] } {
+if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME lpc2148
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
set _CHIPNAME lpc2294
}
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
set _ENDIAN little
}
#Hilscher netX 500 CPU
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
set _CHIPNAME netx500
}
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
set _ENDIAN little
}
# http://focus.ti.com/docs/prod/folders/print/omap3530.html
# Other OMAP3 chips remove DSP and/or the OpenGL support
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
set _CHIPNAME omap3530
}
# TI OMAP5912 dual core processor
# http://focus.ti.com/docs/prod/folders/print/omap5912.html
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
set _CHIPNAME omap5912
}
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
# this defaults to a bigendian
set _ENDIAN little
}
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
set _CHIPNAME pic32mx
}
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
set _ENDIAN little
}
# PXA255 chip ... originally from Intel, PXA line was sold to Marvell.
# This chip is now at end-of-life. Final orders have been taken.
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
set _CHIPNAME pxa255
}
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
set _ENDIAN little
}
#Marvell/Intel PXA270 Script
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
set _CHIPNAME pxa270
}
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
set _ENDIAN little
}
Prerequisites:
-The users of OpenOCD as well as computer programs interacting with OpenOCD are expecting that certain commands
+The users of OpenOCD as well as computer programs interacting with OpenOCD are expecting that certain commands
do the same thing across all the targets.
Rules to follow when writing scripts:
reset
flash info <bank>
and
- reset
+ reset
flash erase_address <start> <len>
and
reset init
load
-
-In most cases this can be accomplished by specifying the default startup mode as reset_init (target command
+
+In most cases this can be accomplished by specifying the default startup mode as reset_init (target command
in the configuration file).
-
-2. If the target is correctly configured, flash must be writable without any other helper commands. It is
+
+2. If the target is correctly configured, flash must be writable without any other helper commands. It is
assumed that all write-protect mechanisms should be disabled.
3. The configuration scripts should be defined such as the binary that was written to flash verifies
-(turn off remapping, checksums, etc...)
+(turn off remapping, checksums, etc...)
flash write_image [file] <parameters>
verify_image [file] <parameters>
-# ATMEL sam7se512
+# ATMEL sam7se512
# Example: the "Elektor Internet Radio" - EIR
# http://www.ethernut.de/en/hardware/eir/index.html
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
set _CHIPNAME sam7se512
}
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
set _ENDIAN little
}
#use combined on interfaces or targets that can't set TRST/SRST separately
reset_config srst_only srst_pulls_trst
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
set _CHIPNAME sam7x256
}
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
set _ENDIAN little
}
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi
-$_TARGETNAME configure -event reset-init {
+$_TARGETNAME configure -event reset-init {
# disable watchdog
- mww 0xfffffd44 0x00008000
+ mww 0xfffffd44 0x00008000
# enable user reset
- mww 0xfffffd08 0xa5000001
+ mww 0xfffffd08 0xa5000001
# CKGR_MOR : enable the main oscillator
- mww 0xfffffc20 0x00000601
+ mww 0xfffffc20 0x00000601
sleep 10
# CKGR_PLLR: 96.1097 MHz
- mww 0xfffffc2c 0x00481c0e
+ mww 0xfffffc2c 0x00481c0e
sleep 10
# PMC_MCKR : MCK = PLL / 2 ~= 48 MHz
- mww 0xfffffc30 0x00000007
+ mww 0xfffffc30 0x00000007
sleep 10
# MC_FMR: flash mode (FWS=1,FMCN=60)
- mww 0xffffff60 0x003c0100
+ mww 0xffffff60 0x003c0100
sleep 100
}
# Found on the 'TinCanTools' Hammer board.
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
set _CHIPNAME s3c2410
}
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
# This config file was defaulting to big endian..
set _ENDIAN little
}
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
+if { [info exists CPUTAPID] } {
+ set _CPUTAPID $CPUTAPID
+} else {
set _CPUTAPID 0xffffffff
}
# Processor : ARM920Tid(wb) rev 0 (v4l)
# Info: JTAG tap: s3c2440.cpu tap/device found: 0x0032409d (Manufacturer: 0x04e, Part: 0x0324, Version: 0x0)
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
set _CHIPNAME s3c2440
}
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
# this defaults to a bigendian
set _ENDIAN little
}
# FIX!!! what to use here?
-#
+#
# RCLK?
-#
+#
# jtag_khz 0
#
# Really low clock during reset?
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
set _CHIPNAME s3c4510
}
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
set _ENDIAN little
}
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME
+target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME
# [Duane Ellis 27/nov/2008: Above 0x0032409d appears to be copy/paste from other places]
# [and I do not believe it to be accurate, hence the 0xffffffff below]
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
set _CHIPNAME s3c6410
}
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
# this defaults to a bigendian
set _ENDIAN little
}
reset_config srst_only srst_pulls_trst
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
set _CHIPNAME lh79532
}
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
set _ENDIAN little
}
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME
+target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME
# script for stm32
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
set _CHIPNAME stm32
}
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
set _ENDIAN little
}
set _BSTAPID4 0x06414041
# Connectivity line devices, Rev A and Rev Z
set _BSTAPID5 0x06418041
-}
+}
jtag newtap $_CHIPNAME bs -irlen 5 -ircapture 0x1 -irmask 0x1 -expected-id $_BSTAPID1 -expected-id $_BSTAPID2 -expected-id $_BSTAPID3 -expected-id $_BSTAPID4 -expected-id $_BSTAPID5
set _TARGETNAME $_CHIPNAME.cpu
#start slow, speed up after reset
jtag_khz 10
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
set _CHIPNAME str710
}
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
set _ENDIAN little
}
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
+if { [info exists CPUTAPID] } {
+ set _CPUTAPID $CPUTAPID
+} else {
set _CPUTAPID 0x3f0f0f0f
}
jtag_khz 3000
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
set _CHIPNAME str730
}
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
set _ENDIAN little
}
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
+if { [info exists CPUTAPID] } {
+ set _CPUTAPID $CPUTAPID
+} else {
set _CPUTAPID 0x3f0f0f0f
}
#STR750 CPU
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
set _CHIPNAME str750
}
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
set _ENDIAN little
}
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
+if { [info exists CPUTAPID] } {
+ set _CPUTAPID $CPUTAPID
+} else {
set _CPUTAPID 0x4f1f0041
}
# script for str9
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
set _CHIPNAME str912
}
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
set _ENDIAN little
}
$_TARGETNAME configure -event reset-init {
# We can increase speed now that we know the target is halted.
#jtag_rclk 3000
-
+
# -- Enable 96K RAM
# PFQBC enabled / DTCM & AHB wait-states disabled
- mww 0x5C002034 0x0191
+ mww 0x5C002034 0x0191
str9x flash_config 0 4 2 0 0x80000
flash protect 0 0 7 off
# it's really 16MB but the upper 8mb is controller via gpio?
flash bank cfi 0x20000000 0x01000000 2 2 $_TARGETNAME
-#
+#
gdb_memory_map enable
#jtag scan chain
set _CHIPNAME syntaxtest
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf
#target configuration
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi-s_r4
-$_TARGETNAME configure -event reset-init {
+$_TARGETNAME configure -event reset-init {
syntax error
}
-# This script tests a syntax error in the startup
+# This script tests a syntax error in the startup
# config script
syntax error here
#Written by: Michael Schwingen <rincewind@discworld.dascon.de>
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
set _CHIPNAME xba_reva3
}
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
# default to big endian
set _ENDIAN big
}
flash bank cfi 0x50000000 0x400000 2 2 0
-init
+init
reset init
# set big endian mode
reg XSCALE_CTRL 0xF8
set _TARGETNAME [format "%s.cpu" lpc2148]
target create lpc2148.cpu arm7tdmi -endian little -work-area-size 0x4000 -work-area-phys 0x40000000 -work-area-virt 0 -work-area-backup 0
-$_TARGETNAME configure -event reset-init {
-soft_reset_halt
-mvb 0xE01FC040 0x01
+$_TARGETNAME configure -event reset-init {
+soft_reset_halt
+mvb 0xE01FC040 0x01
}
projects / openocd / commitdiff