Only type 1 branch instruction has a condition code, not type 2.
Currently they're both tagged with ARM_B which doesn't allow for the
distinction.
Signed-off-by: Nicolas Pitre <nico@marvell.com>
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
return retval;
instruction_size = 2;
- /* check condition code (only for branch instructions) */
- if (instruction.type == ARM_B &&
+ /* check condition code (only for branch (1) instructions) */
+ if ((opcode & 0xf000) == 0xd000 &&
!thumb_pass_branch_condition(sim->get_cpsr(sim, 0, 32), opcode))
{
if (dry_run_pc)