John McCarthy <jgmcc@magma.ca> adds support for DMA mode access as supported by EJTAG...

git-svn-id: svn://svn.berlios.de/openocd/trunk@1029 b42882b7-edfa-0310-969c-e2dbd0fdcd60

diff --git a/src/target/Makefile.am b/src/target/Makefile.am
index b29b4005f8140f6fc2e6506e40d86186723bc9dc..6a7c3c7ede21c1298f090f41325959a0408f87e9 100644 (file)
--- a/src/target/Makefile.am
+++ b/src/target/Makefile.am
@@ -13,11 +13,11 @@ libtarget_a_SOURCES = target.c register.c breakpoints.c armv4_5.c embeddedice.c
        arm_jtag.c arm7_9_common.c algorithm.c arm920t.c arm720t.c armv4_5_mmu.c armv4_5_cache.c arm_disassembler.c \
        arm966e.c arm926ejs.c feroceon.c etb.c xscale.c arm_simulator.c image.c armv7m.c cortex_m3.c cortex_swjdp.c \
        etm_dummy.c $(OOCD_TRACE_FILES) target_request.c trace.c arm11.c arm11_dbgtap.c mips32.c mips_m4k.c \
-       mips32_pracc.c mips_ejtag.c
+       mips32_pracc.c mips32_dmaacc.c mips_ejtag.c
 noinst_HEADERS = target.h trace.h register.h armv4_5.h embeddedice.h etm.h arm7tdmi.h arm9tdmi.h \
        arm_jtag.h arm7_9_common.h arm920t.h arm720t.h armv4_5_mmu.h armv4_5_cache.h breakpoints.h algorithm.h \
        arm_disassembler.h arm966e.h arm926ejs.h etb.h xscale.h arm_simulator.h image.h armv7m.h cortex_m3.h cortex_swjdp.h \
-       etm_dummy.h oocd_trace.h target_request.h trace.h arm11.h mips32.h mips_m4k.h mips_ejtag.h mips32_pracc.h
+       etm_dummy.h oocd_trace.h target_request.h trace.h arm11.h mips32.h mips_m4k.h mips_ejtag.h mips32_pracc.h mips32_dmaacc.h
 
 nobase_dist_pkglib_DATA = xscale/debug_handler.bin target/at91eb40a.cfg \
        event/at91r40008_reset.script event/sam7x256_reset.script \

diff --git a/src/target/mips32_dmaacc.c b/src/target/mips32_dmaacc.c
new file mode 100644 (file)
index 0000000..96426c0
--- /dev/null
+++ b/src/target/mips32_dmaacc.c
@@ -0,0 +1,441 @@
+/***************************************************************************\r
+ *   Copyright (C) 2008 by John McCarthy                                   *\r
+ *   jgmcc@magma.ca                                                        *\r
+ *                                                                         *\r
+ *   Copyright (C) 2008 by Spencer Oliver                                  *\r
+ *   spen@spen-soft.co.uk                                                  *\r
+ *                                                                         *\r
+ *   Copyright (C) 2008 by David T.L. Wong                                 *\r
+ *                                                                         *\r
+ *   This program is free software; you can redistribute it and/or modify  *\r
+ *   it under the terms of the GNU General Public License as published by  *\r
+ *   the Free Software Foundation; either version 2 of the License, or     *\r
+ *   (at your option) any later version.                                   *\r
+ *                                                                         *\r
+ *   This program is distributed in the hope that it will be useful,       *\r
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *\r
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *\r
+ *   GNU General Public License for more details.                          *\r
+ *                                                                         *\r
+ *   You should have received a copy of the GNU General Public License     *\r
+ *   along with this program; if not, write to the                         *\r
+ *   Free Software Foundation, Inc.,                                       *\r
+ *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *\r
+ ***************************************************************************/\r
+#ifdef HAVE_CONFIG_H\r
+#include "config.h"\r
+#endif\r
+\r
+#include <string.h>\r
+#include "log.h"\r
+#include "mips32.h"\r
+#include "mips32_dmaacc.h"\r
+\r
+/*\r
+ * The following logic shamelessly cloned from HairyDairyMaid's wrt54g_debrick\r
+ * to support the Broadcom BCM5352 SoC in the Linksys WRT54GL wireless router\r
+ * (and any others that support EJTAG DMA transfers).\r
+ * Note: This only supports memory read/write. Since the BCM5352 doesn't\r
+ * appear to support PRACC accesses, all debug functions except halt\r
+ * do not work.  Still, this does allow erasing/writing flash as well as\r
+ * displaying/modifying memory and memory mapped registers.\r
+ */\r
+\r
+static int ejtag_dma_read(mips_ejtag_t *ejtag_info, u32 addr, u32 *data)\r
+{\r
+       u32 v;\r
+       u32 ctrl_reg;\r
+       int   retries = RETRY_ATTEMPTS;\r
+\r
+begin_ejtag_dma_read:\r
+\r
+       // Setup Address\r
+       v = addr;\r
+       mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL);\r
+       mips_ejtag_drscan_32(ejtag_info, &v);\r
+\r
+       // Initiate DMA Read & set DSTRT\r
+       mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);\r
+       ctrl_reg = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DRWN | EJTAG_CTRL_DMA_WORD | EJTAG_CTRL_DSTRT | EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;\r
+       mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);\r
+\r
+       // Wait for DSTRT to Clear\r
+       do {\r
+               ctrl_reg = EJTAG_CTRL_DMAACC | EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;\r
+               mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);\r
+       } while(ctrl_reg & EJTAG_CTRL_DSTRT);\r
+\r
+       // Read Data\r
+       mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL);\r
+       mips_ejtag_drscan_32(ejtag_info, data);\r
+\r
+       // Clear DMA & Check DERR\r
+       mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);\r
+       ctrl_reg = EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;\r
+       mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);\r
+       if (ctrl_reg  & EJTAG_CTRL_DERR)\r
+       {\r
+               if (retries--) {\r
+                       printf("DMA Read Addr = %08x  Data = ERROR ON READ (retrying)\n", addr);\r
+                       goto begin_ejtag_dma_read;\r
+               } else  printf("DMA Read Addr = %08x  Data = ERROR ON READ\n", addr);\r
+               return ERROR_JTAG_DEVICE_ERROR;\r
+       }\r
+\r
+       return ERROR_OK;\r
+}\r
+\r
+static int ejtag_dma_read_h(mips_ejtag_t *ejtag_info, u32 addr, u16 *data)\r
+{\r
+       u32 v;\r
+       u32 ctrl_reg;\r
+       int   retries = RETRY_ATTEMPTS;\r
+\r
+begin_ejtag_dma_read_h:\r
+\r
+       // Setup Address\r
+       v = addr;\r
+       mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL);\r
+       mips_ejtag_drscan_32(ejtag_info, &v);\r
+\r
+       // Initiate DMA Read & set DSTRT\r
+       mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);\r
+       ctrl_reg = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DRWN | EJTAG_CTRL_DMA_HALFWORD | EJTAG_CTRL_DSTRT | EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;\r
+       mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);\r
+\r
+       // Wait for DSTRT to Clear\r
+       do {\r
+               ctrl_reg = EJTAG_CTRL_DMAACC | EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;\r
+               mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);\r
+       } while(ctrl_reg & EJTAG_CTRL_DSTRT);\r
+\r
+       // Read Data\r
+       mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL);\r
+       mips_ejtag_drscan_32(ejtag_info, &v);\r
+\r
+       // Clear DMA & Check DERR\r
+       mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);\r
+       ctrl_reg = EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;\r
+       mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);\r
+       if (ctrl_reg  & EJTAG_CTRL_DERR)\r
+       {\r
+               if (retries--) {\r
+                       printf("DMA Read Addr = %08x  Data = ERROR ON READ (retrying)\n", addr);\r
+                       goto begin_ejtag_dma_read_h;\r
+               } else  printf("DMA Read Addr = %08x  Data = ERROR ON READ\n", addr);\r
+               return ERROR_JTAG_DEVICE_ERROR;\r
+       }\r
+\r
+       // Handle the bigendian/littleendian\r
+       if ( addr & 0x2 )  *data = (v>>16)&0xffff ;\r
+       else               *data = (v&0x0000ffff) ;\r
+\r
+       return ERROR_OK;\r
+}\r
+\r
+static int ejtag_dma_read_b(mips_ejtag_t *ejtag_info, u32 addr, u8 *data)\r
+{\r
+       u32 v;\r
+       u32 ctrl_reg;\r
+       int   retries = RETRY_ATTEMPTS;\r
+\r
+begin_ejtag_dma_read_b:\r
+\r
+       // Setup Address\r
+       v = addr;\r
+       mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL);\r
+       mips_ejtag_drscan_32(ejtag_info, &v);\r
+\r
+       // Initiate DMA Read & set DSTRT\r
+       mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);\r
+       ctrl_reg = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DRWN | EJTAG_CTRL_DMA_BYTE | EJTAG_CTRL_DSTRT | EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;\r
+       mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);\r
+\r
+       // Wait for DSTRT to Clear\r
+       do {\r
+               ctrl_reg = EJTAG_CTRL_DMAACC | EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;\r
+               mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);\r
+       } while(ctrl_reg & EJTAG_CTRL_DSTRT);\r
+\r
+       // Read Data\r
+       mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL);\r
+       mips_ejtag_drscan_32(ejtag_info, &v);\r
+\r
+       // Clear DMA & Check DERR\r
+       mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);\r
+       ctrl_reg = EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;\r
+       mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);\r
+       if (ctrl_reg  & EJTAG_CTRL_DERR)\r
+       {\r
+               if (retries--) {\r
+                       printf("DMA Read Addr = %08x  Data = ERROR ON READ (retrying)\n", addr);\r
+                       goto begin_ejtag_dma_read_b;\r
+               } else  printf("DMA Read Addr = %08x  Data = ERROR ON READ\n", addr);\r
+               return ERROR_JTAG_DEVICE_ERROR;\r
+       }\r
+\r
+       // Handle the bigendian/littleendian\r
+       switch(addr & 0x3) {\r
+       case 0:  *data =  v      & 0xff; break;\r
+       case 1:  *data = (v>>8)  & 0xff; break;\r
+       case 2:  *data = (v>>16) & 0xff; break;\r
+       case 3:  *data = (v>>24) & 0xff; break;\r
+       }\r
+\r
+       return ERROR_OK;\r
+}\r
+\r
+static int ejtag_dma_write(mips_ejtag_t *ejtag_info, u32 addr, u32 data)\r
+{\r
+       u32 v;\r
+       u32 ctrl_reg;\r
+       int   retries = RETRY_ATTEMPTS;\r
+\r
+begin_ejtag_dma_write:\r
+\r
+       // Setup Address\r
+       v = addr;\r
+       mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL);\r
+       mips_ejtag_drscan_32(ejtag_info, &v);\r
+\r
+       // Setup Data\r
+       v = data;\r
+       mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL);\r
+       mips_ejtag_drscan_32(ejtag_info, &v);\r
+\r
+       // Initiate DMA Write & set DSTRT\r
+       mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);\r
+       ctrl_reg = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DMA_WORD | EJTAG_CTRL_DSTRT | EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;\r
+       mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);\r
+\r
+       // Wait for DSTRT to Clear\r
+       do {\r
+               ctrl_reg = EJTAG_CTRL_DMAACC | EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;\r
+               mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);\r
+       } while(ctrl_reg & EJTAG_CTRL_DSTRT);\r
+\r
+       // Clear DMA & Check DERR\r
+       mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);\r
+       ctrl_reg = EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;\r
+       mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);\r
+       if (ctrl_reg  & EJTAG_CTRL_DERR)\r
+       {\r
+               if (retries--) {\r
+                       printf("DMA Write Addr = %08x  Data = ERROR ON WRITE (retrying)\n", addr);\r
+                       goto begin_ejtag_dma_write;\r
+               } else  printf("DMA Write Addr = %08x  Data = ERROR ON WRITE\n", addr);\r
+               return ERROR_JTAG_DEVICE_ERROR;\r
+       }\r
+\r
+       return ERROR_OK;\r
+}\r
+\r
+static int ejtag_dma_write_h(mips_ejtag_t *ejtag_info, u32 addr, u32 data)\r
+{\r
+       u32 v;\r
+       u32 ctrl_reg;\r
+       int   retries = RETRY_ATTEMPTS;\r
+\r
+\r
+       // Handle the bigendian/littleendian\r
+       data &= 0xffff;\r
+       data |= data<<16;\r
+\r
+begin_ejtag_dma_write_h:\r
+\r
+       // Setup Address\r
+       v = addr;\r
+       mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL);\r
+       mips_ejtag_drscan_32(ejtag_info, &v);\r
+\r
+       // Setup Data\r
+       v = data;\r
+       mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL);\r
+       mips_ejtag_drscan_32(ejtag_info, &v);\r
+\r
+       // Initiate DMA Write & set DSTRT\r
+       mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);\r
+       ctrl_reg = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DMA_HALFWORD | EJTAG_CTRL_DSTRT | EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;\r
+       mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);\r
+\r
+       // Wait for DSTRT to Clear\r
+       do {\r
+               ctrl_reg = EJTAG_CTRL_DMAACC | EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;\r
+               mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);\r
+       } while(ctrl_reg & EJTAG_CTRL_DSTRT);\r
+\r
+       // Clear DMA & Check DERR\r
+       mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);\r
+       ctrl_reg = EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;\r
+       mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);\r
+       if (ctrl_reg  & EJTAG_CTRL_DERR)\r
+       {\r
+               if (retries--) {\r
+                       printf("DMA Write Addr = %08x  Data = ERROR ON WRITE (retrying)\n", addr);\r
+                       goto begin_ejtag_dma_write_h;\r
+               } else  printf("DMA Write Addr = %08x  Data = ERROR ON WRITE\n", addr);\r
+               return ERROR_JTAG_DEVICE_ERROR;\r
+       }\r
+\r
+       return ERROR_OK;\r
+}\r
+\r
+static int ejtag_dma_write_b(mips_ejtag_t *ejtag_info, u32 addr, u32 data)\r
+{\r
+       u32 v;\r
+       u32 ctrl_reg;\r
+       int   retries = RETRY_ATTEMPTS;\r
+\r
+\r
+       // Handle the bigendian/littleendian\r
+       data &= 0xff;\r
+       data |= data<<8;\r
+       data |= data<<16;\r
+\r
+begin_ejtag_dma_write_b:\r
+\r
+       // Setup Address\r
+       v = addr;\r
+       mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL);\r
+       mips_ejtag_drscan_32(ejtag_info, &v);\r
+\r
+       // Setup Data\r
+       v = data;\r
+       mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL);\r
+       mips_ejtag_drscan_32(ejtag_info, &v);\r
+\r
+       // Initiate DMA Write & set DSTRT\r
+       mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);\r
+       ctrl_reg = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DMA_BYTE | EJTAG_CTRL_DSTRT | EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;\r
+       mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);\r
+\r
+       // Wait for DSTRT to Clear\r
+       do {\r
+               ctrl_reg = EJTAG_CTRL_DMAACC | EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;\r
+               mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);\r
+       } while(ctrl_reg & EJTAG_CTRL_DSTRT);\r
+\r
+       // Clear DMA & Check DERR\r
+       mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);\r
+       ctrl_reg = EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;\r
+       mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);\r
+       if (ctrl_reg  & EJTAG_CTRL_DERR)\r
+       {\r
+               if (retries--) {\r
+                       printf("DMA Write Addr = %08x  Data = ERROR ON WRITE (retrying)\n", addr);\r
+                       goto begin_ejtag_dma_write_b;\r
+               } else  printf("DMA Write Addr = %08x  Data = ERROR ON WRITE\n", addr);\r
+               return ERROR_JTAG_DEVICE_ERROR;\r
+       }\r
+\r
+       return ERROR_OK;\r
+}\r
+\r
+\r
+int mips32_dmaacc_read_mem(mips_ejtag_t *ejtag_info, u32 addr, int size, int count, void *buf)\r
+{\r
+       switch (size)\r
+       {\r
+               case 1:\r
+                       return mips32_dmaacc_read_mem8(ejtag_info, addr, count, (u8*)buf);\r
+               case 2:\r
+                       return mips32_dmaacc_read_mem16(ejtag_info, addr, count, (u16*)buf);\r
+               case 4:\r
+                       return mips32_dmaacc_read_mem32(ejtag_info, addr, count, (u32*)buf);\r
+       }\r
+\r
+       return ERROR_OK;\r
+}\r
+\r
+int mips32_dmaacc_read_mem32(mips_ejtag_t *ejtag_info, u32 addr, int count, u32 *buf)\r
+{\r
+       int i;\r
+       int     retval;\r
+\r
+       for(i=0; i<count; i++) {\r
+               if((retval=ejtag_dma_read(ejtag_info, addr+i*sizeof(*buf), &buf[i])) != ERROR_OK)\r
+                       return retval;\r
+       }\r
+\r
+       return ERROR_OK;\r
+}\r
+\r
+int mips32_dmaacc_read_mem16(mips_ejtag_t *ejtag_info, u32 addr, int count, u16 *buf)\r
+{\r
+       int i;\r
+       int retval;\r
+\r
+       for(i=0; i<count; i++) {\r
+               if((retval=ejtag_dma_read_h(ejtag_info, addr+i*sizeof(*buf), &buf[i])) != ERROR_OK)\r
+                       return retval;\r
+       }\r
+\r
+       return ERROR_OK;\r
+}\r
+\r
+int mips32_dmaacc_read_mem8(mips_ejtag_t *ejtag_info, u32 addr, int count, u8 *buf)\r
+{\r
+       int i;\r
+       int retval;\r
+\r
+       for(i=0; i<count; i++) {\r
+               if((retval=ejtag_dma_read_b(ejtag_info, addr+i*sizeof(*buf), &buf[i])) != ERROR_OK)\r
+                       return retval;\r
+       }\r
+\r
+       return ERROR_OK;\r
+}\r
+\r
+int mips32_dmaacc_write_mem(mips_ejtag_t *ejtag_info, u32 addr, int size, int count, void *buf)\r
+{\r
+       switch (size)\r
+       {\r
+               case 1:\r
+                       return mips32_dmaacc_write_mem8(ejtag_info, addr, count, (u8*)buf);\r
+               case 2:\r
+                       return mips32_dmaacc_write_mem16(ejtag_info, addr, count,(u16*)buf);\r
+               case 4:\r
+                       return mips32_dmaacc_write_mem32(ejtag_info, addr, count, (u32*)buf);\r
+       }\r
+\r
+       return ERROR_OK;\r
+}\r
+\r
+int mips32_dmaacc_write_mem32(mips_ejtag_t *ejtag_info, u32 addr, int count, u32 *buf)\r
+{\r
+       int i;\r
+       int retval;\r
+\r
+       for(i=0; i<count; i++) {\r
+               if((retval=ejtag_dma_write(ejtag_info, addr+i*sizeof(*buf), buf[i])) != ERROR_OK)\r
+                       return retval;\r
+       }\r
+\r
+       return ERROR_OK;\r
+}\r
+\r
+int mips32_dmaacc_write_mem16(mips_ejtag_t *ejtag_info, u32 addr, int count, u16 *buf)\r
+{\r
+       int i;\r
+       int retval;\r
+\r
+       for(i=0; i<count; i++) {\r
+               if((retval=ejtag_dma_write_h(ejtag_info, addr+i*sizeof(*buf), buf[i])) != ERROR_OK)\r
+                       return retval;\r
+       }\r
+\r
+       return ERROR_OK;\r
+}\r
+\r
+int mips32_dmaacc_write_mem8(mips_ejtag_t *ejtag_info, u32 addr, int count, u8 *buf)\r
+{\r
+       int i;\r
+       int retval;\r
+\r
+       for(i=0; i<count; i++) {\r
+               if((retval=ejtag_dma_write_b(ejtag_info, addr+i*sizeof(*buf), buf[i])) != ERROR_OK)\r
+                       return retval;\r
+       }\r
+\r
+       return ERROR_OK;\r
+}\r

diff --git a/src/target/mips32_dmaacc.h b/src/target/mips32_dmaacc.h
new file mode 100644 (file)
index 0000000..b6d544c
--- /dev/null
+++ b/src/target/mips32_dmaacc.h
@@ -0,0 +1,53 @@
+/***************************************************************************\r
+ *   Copyright (C) 2008 by John McCarthy                                   *\r
+ *   jgmcc@magma.ca                                                        *\r
+ *                                                                         *\r
+ *   Copyright (C) 2008 by Spencer Oliver                                  *\r
+ *   spen@spen-soft.co.uk                                                  *\r
+ *                                                                         *\r
+ *   Copyright (C) 2008 by David T.L. Wong                                 *\r
+ *                                                                         *\r
+ *   This program is free software; you can redistribute it and/or modify  *\r
+ *   it under the terms of the GNU General Public License as published by  *\r
+ *   the Free Software Foundation; either version 2 of the License, or     *\r
+ *   (at your option) any later version.                                   *\r
+ *                                                                         *\r
+ *   This program is distributed in the hope that it will be useful,       *\r
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *\r
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *\r
+ *   GNU General Public License for more details.                          *\r
+ *                                                                         *\r
+ *   You should have received a copy of the GNU General Public License     *\r
+ *   along with this program; if not, write to the                         *\r
+ *   Free Software Foundation, Inc.,                                       *\r
+ *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *\r
+ ***************************************************************************/\r
+#ifndef MIPS32_DMAACC_H\r
+#define MIPS32_DMAACC_H\r
+\r
+#include "mips_ejtag.h"\r
+\r
+#define EJTAG_CTRL_DMA_BYTE        0x00000000\r
+#define EJTAG_CTRL_DMA_HALFWORD    0x00000080\r
+#define EJTAG_CTRL_DMA_WORD        0x00000100\r
+#define EJTAG_CTRL_DMA_TRIPLEBYTE  0x00000180\r
+\r
+#define RETRY_ATTEMPTS 4\r
+\r
+extern int mips32_dmaacc_read_mem(mips_ejtag_t *ejtag_info, u32 addr, int size, int count, void *buf);\r
+extern int mips32_dmaacc_write_mem(mips_ejtag_t *ejtag_info, u32 addr, int size, int count, void *buf);\r
+\r
+extern int mips32_dmaacc_read_mem8(mips_ejtag_t *ejtag_info, u32 addr, int count, u8 *buf);\r
+extern int mips32_dmaacc_read_mem16(mips_ejtag_t *ejtag_info, u32 addr, int count, u16 *buf);\r
+extern int mips32_dmaacc_read_mem32(mips_ejtag_t *ejtag_info, u32 addr, int count, u32 *buf);\r
+\r
+extern int mips32_dmaacc_write_mem8(mips_ejtag_t *ejtag_info, u32 addr, int count, u8 *buf);\r
+extern int mips32_dmaacc_write_mem16(mips_ejtag_t *ejtag_info, u32 addr, int count, u16 *buf);\r
+extern int mips32_dmaacc_write_mem32(mips_ejtag_t *ejtag_info, u32 addr, int count, u32 *buf);\r
+\r
+#if 0\r
+extern int mips32_dmaacc_read_regs(mips_ejtag_t *ejtag_info, u32 *regs);\r
+extern int mips32_dmaacc_write_regs(mips_ejtag_t *ejtag_info, u32 *regs);\r
+#endif\r
+\r
+#endif\r

diff --git a/src/target/mips_ejtag.c b/src/target/mips_ejtag.c
index d22036859c493a3fcf8914d5000e5e0c9de32bf9..6e6bd934931387fff2bd6f9207c3d2a110e2c55e 100644 (file)
--- a/src/target/mips_ejtag.c
+++ b/src/target/mips_ejtag.c
@@ -204,6 +204,9 @@ int mips_ejtag_enter_debug(mips_ejtag_t *ejtag_info)
        /* break bit will be cleared by hardware */
        ejtag_info->ejtag_ctrl = EJTAG_CTRL_ROCC | EJTAG_CTRL_PRACC | EJTAG_CTRL_PROBEN | EJTAG_CTRL_SETDEV;
        mips_ejtag_drscan_32(ejtag_info, &ejtag_info->ejtag_ctrl);
+       LOG_DEBUG("ejtag_ctrl: 0x%8.8x", ejtag_info->ejtag_ctrl);
+       if((ejtag_info->ejtag_ctrl & EJTAG_CTRL_BRKST) == 0)
+               LOG_DEBUG("Failed to enter Debug Mode!");
        
        return ERROR_OK;
 }
@@ -275,6 +278,17 @@ int mips_ejtag_init(mips_ejtag_t *ejtag_info)
                        LOG_DEBUG("EJTAG: Unknown Version Detected");
                        break;
        }
+       LOG_DEBUG("EJTAG: features:%s%s%s%s%s%s%s",
+               ejtag_info->impcode & (1<<28) ? " R3k":    " R4k",
+               ejtag_info->impcode & (1<<24) ? " DINT":   "",
+               ejtag_info->impcode & (1<<22) ? " ASID_8": "",
+               ejtag_info->impcode & (1<<21) ? " ASID_6": "",
+               ejtag_info->impcode & (1<<16) ? " MIPS16": "",
+               ejtag_info->impcode & (1<<14) ? " noDMA":  " DMA",
+               ejtag_info->impcode & (1<<0)  ? " MIPS64": " MIPS32"
+       );
+       if((ejtag_info->impcode & (1<<14)) == 0)
+               LOG_DEBUG("EJTAG: DMA Access Mode Support Enabled");
        
        /* set initial state for ejtag control reg */
        ejtag_info->ejtag_ctrl = EJTAG_CTRL_ROCC | EJTAG_CTRL_PRACC | EJTAG_CTRL_PROBEN | EJTAG_CTRL_SETDEV;

diff --git a/src/target/mips_ejtag.h b/src/target/mips_ejtag.h
index b25bd0265299a4b0465fc0d36cf64d113376ca00..cd31d2334839cc3a45de7f735450065a92fe2d52 100644 (file)
--- a/src/target/mips_ejtag.h
+++ b/src/target/mips_ejtag.h
@@ -38,7 +38,7 @@
 #define EJTAG_INST_TCBCONTROLA 0x10
 #define EJTAG_INST_TCBCONTROLB 0x11
 #define EJTAG_INST_TCBDATA             0x12
-#define EJTAG_INST_BYPASS              0x1F
+#define EJTAG_INST_BYPASS              0xFF
 
 #define EJTAG_CTRL_TOF                 (1 << 1)
 #define EJTAG_CTRL_TIF                 (1 << 2)

diff --git a/src/target/mips_m4k.c b/src/target/mips_m4k.c
index 0db7a94bc5c8535f67d26b8386f6e569d712feda..03995b5e6cb50fd2c4d9e4e29e1fe7a6c0e55e7d 100644 (file)
--- a/src/target/mips_m4k.c
+++ b/src/target/mips_m4k.c
@@ -512,7 +512,11 @@ int mips_m4k_read_memory(struct target_s *target, u32 address, u32 size, u32 cou
                case 4:
                case 2:
                case 1:
-                       return mips32_pracc_read_mem(ejtag_info, address, size, count, (void *)buffer);
+                       /* if noDMA off, use DMAACC mode for memory read */
+                       if(ejtag_info->impcode & (1<<14))
+                               return mips32_pracc_read_mem(ejtag_info, address, size, count, (void *)buffer);
+                       else
+                               return mips32_dmaacc_read_mem(ejtag_info, address, size, count, (void *)buffer);
                default:
                        LOG_ERROR("BUG: we shouldn't get here");
                        exit(-1);
@@ -547,7 +551,11 @@ int mips_m4k_write_memory(struct target_s *target, u32 address, u32 size, u32 co
                case 4:
                case 2:
                case 1:
-                       mips32_pracc_write_mem(ejtag_info, address, size, count, (void *)buffer);
+                       /* if noDMA off, use DMAACC mode for memory write */
+                       if(ejtag_info->impcode & (1<<14))
+                               mips32_pracc_write_mem(ejtag_info, address, size, count, (void *)buffer);
+                       else
+                               mips32_dmaacc_write_mem(ejtag_info, address, size, count, (void *)buffer);
                        break;
                default:
                        LOG_ERROR("BUG: we shouldn't get here");