The testee target is usefull for certain non-cpu pass-through
situations, for example in the case of a spi flash mapped to the DR of
a JTAG tap, as is the case for most FPGAs with SPI flashs behind them.
We just manage the RUNNING/RESET/HALTED state in the testee driver to
support it being halted which is a requirement for flash banks.
Change-Id: I1b4d52c58a1f6bd753e126bfde74dcc5164d7b69
Signed-off-by: Robert Jordens <jordens@gmail.com>
Reviewed-on: http://openocd.zylin.com/2840
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
}
static int testee_poll(struct target *target)
{
+ if ((target->state == TARGET_RUNNING) || (target->state == TARGET_DEBUG_RUNNING))
+ target->state = TARGET_HALTED;
return ERROR_OK;
}
static int testee_halt(struct target *target)
{
+ target->state = TARGET_HALTED;
return ERROR_OK;
}
static int testee_reset_assert(struct target *target)
{
+ target->state = TARGET_RESET;
return ERROR_OK;
}
static int testee_reset_deassert(struct target *target)
{
+ target->state = TARGET_RUNNING;
return ERROR_OK;
}
struct target_type testee_target = {