--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_pwr.h\r
+ * @author MCD Application Team\r
+ * @version V1.0.0RC1\r
+ * @date 07/02/2010\r
+ * @brief This file contains all the functions prototypes for the PWR firmware \r
+ * library.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32L1xx_PWR_H\r
+#define __STM32L1xx_PWR_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup PWR\r
+ * @{\r
+ */ \r
+\r
+/** @defgroup PWR_Exported_Types\r
+ * @{\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup PWR_Exported_Constants\r
+ * @{\r
+ */ \r
+\r
+/** @defgroup PVD_detection_level \r
+ * @{\r
+ */ \r
+\r
+#define PWR_PVDLevel_0 PWR_CR_PLS_LEV0\r
+#define PWR_PVDLevel_1 PWR_CR_PLS_LEV1\r
+#define PWR_PVDLevel_2 PWR_CR_PLS_LEV2\r
+#define PWR_PVDLevel_3 PWR_CR_PLS_LEV3\r
+#define PWR_PVDLevel_4 PWR_CR_PLS_LEV4\r
+#define PWR_PVDLevel_5 PWR_CR_PLS_LEV5\r
+#define PWR_PVDLevel_6 PWR_CR_PLS_LEV6\r
+#define PWR_PVDLevel_7 PWR_CR_PLS_LEV7 /* External input analog voltage \r
+ (Compare internally to VREFINT) */\r
+#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_0) || ((LEVEL) == PWR_PVDLevel_1)|| \\r
+ ((LEVEL) == PWR_PVDLevel_2) || ((LEVEL) == PWR_PVDLevel_3)|| \\r
+ ((LEVEL) == PWR_PVDLevel_4) || ((LEVEL) == PWR_PVDLevel_5)|| \\r
+ ((LEVEL) == PWR_PVDLevel_6) || ((LEVEL) == PWR_PVDLevel_7))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup WakeUp_Pins \r
+ * @{\r
+ */\r
+\r
+#define PWR_WakeUpPin_1 ((uint32_t)0x00000000)\r
+#define PWR_WakeUpPin_2 ((uint32_t)0x00000004)\r
+#define PWR_WakeUpPin_3 ((uint32_t)0x00000008)\r
+#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WakeUpPin_1) || \\r
+ ((PIN) == PWR_WakeUpPin_2) || \\r
+ ((PIN) == PWR_WakeUpPin_3))\r
+/**\r
+ * @}\r
+ */\r
+\r
+ \r
+/** @defgroup Voltage_Scaling_Ranges\r
+ * @{\r
+ */\r
+\r
+#define PWR_VoltageScaling_Range1 PWR_CR_VOS_0\r
+#define PWR_VoltageScaling_Range2 PWR_CR_VOS_1\r
+#define PWR_VoltageScaling_Range3 PWR_CR_VOS\r
+\r
+#define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_VoltageScaling_Range1) || \\r
+ ((RANGE) == PWR_VoltageScaling_Range2) || \\r
+ ((RANGE) == PWR_VoltageScaling_Range3))\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/** @defgroup Regulator_state_is_Sleep_STOP_mode \r
+ * @{\r
+ */\r
+\r
+#define PWR_Regulator_ON ((uint32_t)0x00000000)\r
+#define PWR_Regulator_LowPower PWR_CR_LPSDSR\r
+#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_Regulator_ON) || \\r
+ ((REGULATOR) == PWR_Regulator_LowPower))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SLEEP_mode_entry \r
+ * @{\r
+ */\r
+\r
+#define PWR_SLEEPEntry_WFI ((uint8_t)0x01)\r
+#define PWR_SLEEPEntry_WFE ((uint8_t)0x02)\r
+#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPEntry_WFI) || ((ENTRY) == PWR_SLEEPEntry_WFE))\r
+ \r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup STOP_mode_entry \r
+ * @{\r
+ */\r
+\r
+#define PWR_STOPEntry_WFI ((uint8_t)0x01)\r
+#define PWR_STOPEntry_WFE ((uint8_t)0x02)\r
+#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE))\r
+ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PWR_Flag \r
+ * @{\r
+ */\r
+\r
+#define PWR_FLAG_WU PWR_CSR_WUF\r
+#define PWR_FLAG_SB PWR_CSR_SBF\r
+#define PWR_FLAG_PVDO PWR_CSR_PVDO\r
+#define PWR_FLAG_VREFINTRDY PWR_CSR_VREFINTRDYF\r
+#define PWR_FLAG_VOS PWR_CSR_VOSF\r
+#define PWR_FLAG_REGLP PWR_CSR_REGLPF\r
+\r
+#define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \\r
+ ((FLAG) == PWR_FLAG_PVDO) || ((FLAG) == PWR_FLAG_VREFINTRDY) || \\r
+ ((FLAG) == PWR_FLAG_VOS) || ((FLAG) == PWR_FLAG_REGLP))\r
+\r
+#define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PWR_Exported_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PWR_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+void PWR_DeInit(void);\r
+void PWR_RTCAccessCmd(FunctionalState NewState);\r
+void PWR_PVDCmd(FunctionalState NewState);\r
+void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel);\r
+void PWR_WakeUpPinCmd(uint32_t PWR_WakeUpPin, FunctionalState NewState);\r
+void PWR_FastWakeUpCmd(FunctionalState NewState);\r
+void PWR_UltraLowPowerCmd(FunctionalState NewState);\r
+void PWR_VoltageScalingConfig(uint32_t PWR_VoltageScaling);\r
+void PWR_EnterLowPowerRunMode(FunctionalState NewState);\r
+void PWR_EnterSleepMode(uint32_t PWR_Regulator, uint8_t PWR_SLEEPEntry);\r
+void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry);\r
+void PWR_EnterSTANDBYMode(void);\r
+FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG);\r
+void PWR_ClearFlag(uint32_t PWR_FLAG);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32L1xx_PWR_H */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_pwr.c\r
+ * @author MCD Application Team\r
+ * @version V1.0.0RC1\r
+ * @date 07/02/2010\r
+ * @brief This file provides all the PWR firmware functions.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx_pwr.h"\r
+#include "stm32l1xx_rcc.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup PWR \r
+ * @brief PWR driver modules\r
+ * @{\r
+ */ \r
+\r
+/** @defgroup PWR_Private_TypesDefinitions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PWR_Private_Defines\r
+ * @{\r
+ */\r
+\r
+/* --------- PWR registers bit address in the alias region ---------- */\r
+#define PWR_OFFSET (PWR_BASE - PERIPH_BASE)\r
+\r
+/* --- CR Register ---*/\r
+\r
+/* Alias word address of DBP bit */\r
+#define CR_OFFSET (PWR_OFFSET + 0x00)\r
+#define DBP_BitNumber 0x08\r
+#define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4))\r
+\r
+/* Alias word address of PVDE bit */\r
+#define PVDE_BitNumber 0x04\r
+#define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4))\r
+\r
+/* Alias word address of ULP bit */\r
+#define ULP_BitNumber 0x09\r
+#define CR_ULP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (ULP_BitNumber * 4))\r
+\r
+/* Alias word address of FWU bit */\r
+#define FWU_BitNumber 0x0A\r
+#define CR_FWU_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (FWU_BitNumber * 4))\r
+\r
+/* --- CSR Register ---*/\r
+\r
+/* Alias word address of EWUP bit */\r
+#define CSR_OFFSET (PWR_OFFSET + 0x04)\r
+#define EWUP_BitNumber 0x08\r
+#define CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4))\r
+\r
+/* ------------------ PWR registers bit mask ------------------------ */\r
+\r
+/* CR register bit mask */\r
+#define CR_DS_MASK ((uint32_t)0xFFFFFFFC)\r
+#define CR_PLS_MASK ((uint32_t)0xFFFFFF1F)\r
+#define CR_VOS_MASK ((uint32_t)0xFFFFE7FF)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PWR_Private_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PWR_Private_Variables\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PWR_Private_FunctionPrototypes\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PWR_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitializes the PWR peripheral registers to their default reset values.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void PWR_DeInit(void)\r
+{\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE);\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE);\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables access to the RTC and backup registers.\r
+ * @param NewState: new state of the access to the RTC and backup registers.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void PWR_RTCAccessCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ *(__IO uint32_t *) CR_DBP_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the Power Voltage Detector(PVD).\r
+ * @param NewState: new state of the PVD.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void PWR_PVDCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+ * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).\r
+ * @param PWR_PVDLevel: specifies the PVD detection level\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_PVDLevel_0: PVD detection level set to 1.9V\r
+ * @arg PWR_PVDLevel_1: PVD detection level set to 2.1V\r
+ * @arg PWR_PVDLevel_2: PVD detection level set to 2.3V\r
+ * @arg PWR_PVDLevel_3: PVD detection level set to 2.5V\r
+ * @arg PWR_PVDLevel_4: PVD detection level set to 2.7V\r
+ * @arg PWR_PVDLevel_5: PVD detection level set to 2.9V\r
+ * @arg PWR_PVDLevel_6: PVD detection level set to 3.1V\r
+ * @arg PWR_PVDLevel_7: External input analog voltage (Compare internally to VREFINT)\r
+ * @retval None\r
+ */\r
+void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel));\r
+ \r
+ tmpreg = PWR->CR;\r
+ \r
+ /* Clear PLS[7:5] bits */\r
+ tmpreg &= CR_PLS_MASK;\r
+ \r
+ /* Set PLS[7:5] bits according to PWR_PVDLevel value */\r
+ tmpreg |= PWR_PVDLevel;\r
+ \r
+ /* Store the new value */\r
+ PWR->CR = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the WakeUp Pin functionality.\r
+ * @param PWR_WakeUpPin: specifies the WakeUpPin.\r
+ * This parameter can be: PWR_WakeUpPin_1, PWR_WakeUpPin_2 or PWR_WakeUpPin_3.\r
+ * @param NewState: new state of the WakeUp Pin functionality.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void PWR_WakeUpPinCmd(uint32_t PWR_WakeUpPin, FunctionalState NewState)\r
+{\r
+ __IO uint32_t tmp = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_PWR_WAKEUP_PIN(PWR_WakeUpPin));\r
+ \r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ tmp = CSR_EWUP_BB + PWR_WakeUpPin;\r
+ \r
+ *(__IO uint32_t *) (tmp) = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the Fast WakeUp from Ultra Low Power mode.\r
+ * @param NewState: new state of the Fast WakeUp functionality.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void PWR_FastWakeUpCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ *(__IO uint32_t *) CR_FWU_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the Ultra Low Power mode.\r
+ * @param NewState: new state of the Ultra Low Power mode.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void PWR_UltraLowPowerCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ *(__IO uint32_t *) CR_ULP_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+ * @brief Configures the voltage scaling range.\r
+ * @param PWR_VoltageScaling: specifies the voltage scaling range.\r
+ * This parameter can be:\r
+ * @arg PWR_VoltageScaling_Range1: Voltage Scaling Range 1\r
+ * @arg PWR_VoltageScaling_Range2: Voltage Scaling Range 2\r
+ * @arg PWR_VoltageScaling_Range3: Voltage Scaling Range 3 \r
+ * @retval None\r
+ */\r
+void PWR_VoltageScalingConfig(uint32_t PWR_VoltageScaling)\r
+{\r
+ uint32_t tmp = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(PWR_VoltageScaling));\r
+ \r
+ tmp = PWR->CR;\r
+\r
+ tmp &= CR_VOS_MASK;\r
+ tmp |= PWR_VoltageScaling;\r
+ \r
+ PWR->CR = tmp & 0xFFFFFFF3;\r
+\r
+}\r
+\r
+/**\r
+ * @brief Enters/Exits the Low Power Run mode.\r
+ * @param NewState: new state of the Low Power Run mode.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void PWR_EnterLowPowerRunMode(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ PWR->CR |= PWR_CR_LPSDSR;\r
+ PWR->CR |= PWR_CR_LPRUN; \r
+ }\r
+ else\r
+ {\r
+ PWR->CR &= (uint32_t)~((uint32_t)PWR_CR_LPRUN); \r
+ PWR->CR &= (uint32_t)~((uint32_t)PWR_CR_LPSDSR); \r
+ } \r
+}\r
+\r
+/**\r
+ * @brief Enters Sleep mode.\r
+ * @param PWR_Regulator: specifies the regulator state in Sleep mode.\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_Regulator_ON: Sleep mode with regulator ON\r
+ * @arg PWR_Regulator_LowPower: Sleep mode with regulator in low power mode\r
+ * @param PWR_SLEEPEntry: specifies if SLEEP mode in entered with WFI or WFE instruction.\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_SLEEPEntry_WFI: enter SLEEP mode with WFI instruction\r
+ * @arg PWR_SLEEPEntry_WFE: enter SLEEP mode with WFE instruction\r
+ * @retval None\r
+ */\r
+void PWR_EnterSleepMode(uint32_t PWR_Regulator, uint8_t PWR_SLEEPEntry)\r
+{\r
+ uint32_t tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_PWR_REGULATOR(PWR_Regulator));\r
+\r
+ assert_param(IS_PWR_SLEEP_ENTRY(PWR_SLEEPEntry));\r
+ \r
+ /* Select the regulator state in Sleep mode ---------------------------------*/\r
+ tmpreg = PWR->CR;\r
+ \r
+ /* Clear PDDS and LPDSR bits */\r
+ tmpreg &= CR_DS_MASK;\r
+ \r
+ /* Set LPDSR bit according to PWR_Regulator value */\r
+ tmpreg |= PWR_Regulator;\r
+ \r
+ /* Store the new value */\r
+ PWR->CR = tmpreg;\r
+\r
+ /* Clear SLEEPDEEP bit of Cortex System Control Register */\r
+ SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP);\r
+ \r
+ /* Select SLEEP mode entry -------------------------------------------------*/\r
+ if(PWR_SLEEPEntry == PWR_SLEEPEntry_WFI)\r
+ { \r
+ /* Request Wait For Interrupt */\r
+ __WFI();\r
+ }\r
+ else\r
+ {\r
+ /* Request Wait For Event */\r
+ __WFE();\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enters STOP mode.\r
+ * @param PWR_Regulator: specifies the regulator state in STOP mode.\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_Regulator_ON: STOP mode with regulator ON\r
+ * @arg PWR_Regulator_LowPower: STOP mode with regulator in low power mode\r
+ * @param PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction.\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction\r
+ * @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction\r
+ * @retval None\r
+ */\r
+void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_PWR_REGULATOR(PWR_Regulator));\r
+ assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry));\r
+ \r
+ /* Select the regulator state in STOP mode ---------------------------------*/\r
+ tmpreg = PWR->CR;\r
+ /* Clear PDDS and LPDSR bits */\r
+ tmpreg &= CR_DS_MASK;\r
+ \r
+ /* Set LPDSR bit according to PWR_Regulator value */\r
+ tmpreg |= PWR_Regulator;\r
+ \r
+ /* Store the new value */\r
+ PWR->CR = tmpreg;\r
+ \r
+ /* Set SLEEPDEEP bit of Cortex System Control Register */\r
+ SCB->SCR |= SCB_SCR_SLEEPDEEP;\r
+ \r
+ /* Select STOP mode entry --------------------------------------------------*/\r
+ if(PWR_STOPEntry == PWR_STOPEntry_WFI)\r
+ { \r
+ /* Request Wait For Interrupt */\r
+ __WFI();\r
+ }\r
+ else\r
+ {\r
+ /* Request Wait For Event */\r
+ __WFE();\r
+ }\r
+ /* Reset SLEEPDEEP bit of Cortex System Control Register */\r
+ SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP); \r
+}\r
+\r
+/**\r
+ * @brief Enters STANDBY mode.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void PWR_EnterSTANDBYMode(void)\r
+{\r
+ /* Clear Wake-up flag */\r
+ PWR->CR |= PWR_CR_CWUF;\r
+ \r
+ /* Select STANDBY mode */\r
+ PWR->CR |= PWR_CR_PDDS;\r
+ \r
+ /* Set SLEEPDEEP bit of Cortex System Control Register */\r
+ SCB->SCR |= SCB_SCR_SLEEPDEEP;\r
+ \r
+/* This option is used to ensure that store operations are completed */\r
+#if defined ( __CC_ARM )\r
+ __force_stores();\r
+#endif\r
+ /* Request Wait For Interrupt */\r
+ __WFI();\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified PWR flag is set or not.\r
+ * @param PWR_FLAG: specifies the flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_FLAG_WU: Wake Up flag\r
+ * @arg PWR_FLAG_SB: StandBy flag\r
+ * @arg PWR_FLAG_PVDO: PVD Output\r
+ * @arg PWR_FLAG_VREFINTRDY: Internal Voltage Reference Ready flag\r
+ * @arg PWR_FLAG_VOS: Voltage Scaling select flag\r
+ * @arg PWR_FLAG_REGLP: Regulator LP flag \r
+ * @retval The new state of PWR_FLAG (SET or RESET).\r
+ */\r
+FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+ /* Check the parameters */\r
+ assert_param(IS_PWR_GET_FLAG(PWR_FLAG));\r
+ \r
+ if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the flag status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the PWR's pending flags.\r
+ * @param PWR_FLAG: specifies the flag to clear.\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_FLAG_WU: Wake Up flag\r
+ * @arg PWR_FLAG_SB: StandBy flag\r
+ * @retval None\r
+ */\r
+void PWR_ClearFlag(uint32_t PWR_FLAG)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG));\r
+ \r
+ PWR->CR |= PWR_FLAG << 2;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
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