]> git.sur5r.net Git - openocd/commitdiff
cleanup trailing whitespaces
authorRodrigo L. Rosa <rodrigorosa.lg@gmail.com>
Fri, 10 Jun 2011 19:23:34 +0000 (12:23 -0700)
committerØyvind Harboe <oyvind.harboe@zylin.com>
Sun, 12 Jun 2011 09:18:27 +0000 (11:18 +0200)
src/flash/nor/dsp5680xx_flash.c
src/jtag/drivers/ft2232.c
src/target/dsp5680xx.c
src/target/dsp5680xx.h

index 4e7a0b61023810741f2bf8c57cf940461ca8afb8..9fa7b06fe35c6789bbc5aed3de2867dec0a9f7fb 100644 (file)
@@ -3,7 +3,7 @@
  *   rodrigorosa.LG@gmail.com                                              *
  *                                                                         *
  *   Based on a file written by:                                           *
- *   Kevin McGuire                                                         * 
+ *   Kevin McGuire                                                         *
  *   Marcel Wijlaars                                                       *
  *   Michael Ashton                                                        *
  *                                                                         *
@@ -102,7 +102,7 @@ static int dsp5680xx_flash_protect(struct flash_bank *bank, int set, int first,
       for(int i = first;i<last;i++)
        bank->sectors[i].is_protected = 1;
     }
-  }else{    
+  }else{
     retval = dsp5680xx_f_unlock(bank->target);
     if(retval == ERROR_OK)
       for(int i = first;i<last;i++)
index 7c283278fdd063a9ef6a7006823ae98a8438d5eb..bde170050d15bbea93c38011a48e094c0624925b 100644 (file)
@@ -2935,7 +2935,7 @@ static int minimodule_init(void)
                LOG_ERROR("couldn't initialize FT2232 with 'minimodule' layout");
                return ERROR_JTAG_INIT_FAILED;
        }
-       
+
 
        nSRST    = 0x20;
 
index 3db31d30e6e7b2e63b555ca91cfbcf66a13ecaff..f3f25a17b75686af8580a8b5f0709f47bd8252ac 100644 (file)
@@ -726,11 +726,11 @@ static int dsp5680xx_read(struct target * target, uint32_t address, unsigned siz
        err_check_propagate(retval);
     context.flush = 0;
   }
-  
+
   context.flush = 1;
   retval = dsp5680xx_execute_queue();
   err_check_propagate(retval);
-  
+
   return retval;
 }
 
@@ -913,7 +913,7 @@ static int dsp5680xx_read_buffer(struct target * target, uint32_t address, uint3
     return ERROR_OK;
   }
   // read_buffer is called when the verify_image command is executed.
-  // The "/2" solves the byte/word addressing issue. 
+  // The "/2" solves the byte/word addressing issue.
   return dsp5680xx_read(target,address,2,size/2,buffer);
 }
 
@@ -1120,14 +1120,14 @@ int dsp5680xx_f_erase_check(struct target * target, uint8_t * erased,uint32_t se
     *erased = (uint8_t)(hfm_ustat&HFM_USTAT_MASK_BLANK);
   return retval;
 }
-  
+
 static int erase_sector(struct target * target, int sector, uint16_t * hfm_ustat){
   int retval;
   retval = dsp5680xx_f_execute_command(target,HFM_PAGE_ERASE,HFM_FLASH_BASE_ADDR+sector*HFM_SECTOR_SIZE/2,0,hfm_ustat,1);
   err_check_propagate(retval);
   return retval;
 }
+
 static int mass_erase(struct target * target, uint16_t * hfm_ustat){
   int retval;
   retval = dsp5680xx_f_execute_command(target,HFM_MASS_ERASE,0,0,hfm_ustat,1);
index da494c9afebfde0bd5a603c7fb8adb5ae32f9453..50ab990777faefe30d2203f5af8bf9d5e6862822 100644 (file)
 #define DSP5680XX_ONCE_OPDBR    0x08 /* EOnCE Program Data Bus Register (OPDBR) */
 #define DSP5680XX_ONCE_OTX1     0x09 /* EOnCE Upper Transmit register (OTX1) */
 #define DSP5680XX_ONCE_OPABFR   0x0A /* OnCE Program Address Register—Fetch cycle */
-#define DSP5680XX_ONCE_ORX      0x0B /* EOnCE Receive register (ORX) */ 
+#define DSP5680XX_ONCE_ORX      0x0B /* EOnCE Receive register (ORX) */
 #define DSP5680XX_ONCE_OCNTR_C  0x0C /* Clear OCNTR */
 #define DSP5680XX_ONCE_ORX1     0x0D /* EOnCE Upper Receive register (ORX1) */
 #define DSP5680XX_ONCE_OTBCR    0x0E /* EOnCE Trace Buffer Control Reg (OTBCR) */
 #define DSP5680XX_ONCE_OPABER   0x10 /* OnCE Program Address Register—Execute cycle */
 #define DSP5680XX_ONCE_OPFIFO   0x11 /* OnCE Program address FIFO */
-#define DSP5680XX_ONCE_OBAR1    0x12 /* EOnCE Breakpoint 1 Unit 0 Address Reg.(OBAR1) */ 
+#define DSP5680XX_ONCE_OBAR1    0x12 /* EOnCE Breakpoint 1 Unit 0 Address Reg.(OBAR1) */
 #define DSP5680XX_ONCE_OPABDR   0x13 /* OnCE Program Address Register—Decode cycle (OPABDR) */
 //----------------------------------------------------------------
 
 //----------------------------------------------------------------
 #define MC568013_EONCE_OBASE_ADDR 0xFF
 // The following are relative to EONCE_OBASE_ADDR (EONCE_OBASE_ADDR<<16 + ...)
-#define MC568013_EONCE_TX_RX_ADDR    0xFFFE // 
+#define MC568013_EONCE_TX_RX_ADDR    0xFFFE //
 #define MC568013_EONCE_TX1_RX1_HIGH_ADDR  0xFFFF // Relative to EONCE_OBASE_ADDR
 #define MC568013_EONCE_OCR 0xFFA0 // Relative to EONCE_OBASE_ADDR
 //----------------------------------------------------------------