--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.0.0\r
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software. If you wish to use our Amazon\r
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+/*-----------------------------------------------------------\r
+ * Implementation of functions defined in portable.h for the ARM CM4F port.\r
+ *----------------------------------------------------------*/\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/*\r
+ * Start first task is a separate function so it can be tested in isolation.\r
+ */\r
+void vPortStartFirstTask( void ) __attribute__ (( naked ));\r
+\r
+/*\r
+ * Exception handlers.\r
+ */\r
+void vPortSVCHandler( void ) __attribute__ (( naked ));\r
+void xPortPendSVHandler( void ) __attribute__ (( naked ));\r
+\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortStartFirstTask( void )\r
+{\r
+ __asm volatile(\r
+#if defined(__SES_ARM)\r
+ " ldr r0, =_vectors \n" /* Locate the stack using _vectors table. */\r
+#else\r
+ " ldr r0, =__isr_vector \n" /* Locate the stack using __isr_vector table. */\r
+#endif\r
+ " ldr r0, [r0] \n"\r
+ " msr msp, r0 \n" /* Set the msp back to the start of the stack. */\r
+ " cpsie i \n" /* Globally enable interrupts. */\r
+ " cpsie f \n"\r
+ " dsb \n"\r
+ " isb \n"\r
+#ifdef SOFTDEVICE_PRESENT\r
+ /* Block kernel interrupts only (PendSV) before calling SVC */\r
+ " mov r0, %0 \n"\r
+ " msr basepri, r0 \n"\r
+#endif\r
+ " svc 0 \n" /* System call to start first task. */\r
+ " \n"\r
+ " .align 2 \n"\r
+#ifdef SOFTDEVICE_PRESENT\r
+ ::"i"(configKERNEL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS))\r
+#endif\r
+ );\r
+}\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortSVCHandler( void )\r
+{\r
+ __asm volatile (\r
+ " ldr r3, =pxCurrentTCB \n" /* Restore the context. */\r
+ " ldr r1, [r3] \n" /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */\r
+ " ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. */\r
+ " ldmia r0!, {r4-r11, r14} \n" /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */\r
+ " msr psp, r0 \n" /* Restore the task stack pointer. */\r
+ " isb \n"\r
+ " mov r0, #0 \n"\r
+ " msr basepri, r0 \n"\r
+ " bx r14 \n"\r
+ " \n"\r
+ " .align 2 \n"\r
+ );\r
+}\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void xPortPendSVHandler( void )\r
+{\r
+ /* This is a naked function. */\r
+\r
+ __asm volatile\r
+ (\r
+ " mrs r0, psp \n"\r
+ " isb \n"\r
+ " \n"\r
+ " ldr r3, =pxCurrentTCB \n" /* Get the location of the current TCB. */\r
+ " ldr r2, [r3] \n"\r
+ " \n"\r
+ " tst r14, #0x10 \n" /* Is the task using the FPU context? If so, push high vfp registers. */\r
+ " it eq \n"\r
+ " vstmdbeq r0!, {s16-s31} \n"\r
+ " \n"\r
+ " stmdb r0!, {r4-r11, r14} \n" /* Save the core registers. */\r
+ " \n"\r
+ " str r0, [r2] \n" /* Save the new top of stack into the first member of the TCB. */\r
+ " \n"\r
+ " stmdb sp!, {r3} \n"\r
+ " mov r0, %0 \n"\r
+ " msr basepri, r0 \n"\r
+ " dsb \n"\r
+ " isb \n"\r
+ " bl vTaskSwitchContext \n"\r
+ " mov r0, #0 \n"\r
+ " msr basepri, r0 \n"\r
+ " ldmia sp!, {r3} \n"\r
+ " \n"\r
+ " ldr r1, [r3] \n" /* The first item in pxCurrentTCB is the task top of stack. */\r
+ " ldr r0, [r1] \n"\r
+ " \n"\r
+ " ldmia r0!, {r4-r11, r14} \n" /* Pop the core registers. */\r
+ " \n"\r
+ " tst r14, #0x10 \n" /* Is the task using the FPU context? If so, pop the high vfp registers too. */\r
+ " it eq \n"\r
+ " vldmiaeq r0!, {s16-s31} \n"\r
+ " \n"\r
+ " msr psp, r0 \n"\r
+ " isb \n"\r
+ " \n"\r
+ " \n"\r
+ " bx r14 \n"\r
+ " \n"\r
+ " .align 2 \n"\r
+ ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS))\r
+ );\r
+}\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.0.0\r
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software. If you wish to use our Amazon\r
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+/*-----------------------------------------------------------\r
+ * Implementation of functions defined in portable.h for the ARM CM4F port.\r
+ *----------------------------------------------------------*/\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#ifdef SOFTDEVICE_PRESENT\r
+#include "nrf_soc.h"\r
+#include "app_util.h"\r
+#include "app_util_platform.h"\r
+#endif\r
+\r
+#if !(__FPU_USED) && !(__LINT__)\r
+ #error This port can only be used when the project options are configured to enable hardware floating point support.\r
+#endif\r
+\r
+#if configMAX_SYSCALL_INTERRUPT_PRIORITY == 0\r
+ #error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html\r
+#endif\r
+\r
+/* Constants used to detect a Cortex-M7 r0p1 core, which should use the ARM_CM7\r
+r0p1 port. */\r
+#define portCORTEX_M4_r0p1_ID ( 0x410FC241UL )\r
+\r
+/* Constants required to check the validity of an interrupt priority. */\r
+#define portFIRST_USER_INTERRUPT_NUMBER ( 16 )\r
+#define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff )\r
+#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 )\r
+\r
+/* Constants required to set up the initial stack. */\r
+#define portINITIAL_XPSR (((xPSR_Type){.b.T = 1}).w)\r
+#define portINITIAL_EXEC_RETURN ( 0xfffffffd )\r
+\r
+/* Let the user override the pre-loading of the initial LR with the address of\r
+prvTaskExitError() in case is messes up unwinding of the stack in the\r
+debugger. */\r
+#ifdef configTASK_RETURN_ADDRESS\r
+ #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS\r
+#else\r
+ #define portTASK_RETURN_ADDRESS prvTaskExitError\r
+#endif\r
+\r
+/* Each task maintains its own interrupt status in the critical nesting\r
+variable. */\r
+static UBaseType_t uxCriticalNesting = 0;\r
+\r
+/*\r
+ * Setup the timer to generate the tick interrupts. The implementation in this\r
+ * file is weak to allow application writers to change the timer used to\r
+ * generate the tick interrupt.\r
+ */\r
+extern void vPortSetupTimerInterrupt( void );\r
+\r
+/*\r
+ * Exception handlers.\r
+ */\r
+void xPortSysTickHandler( void );\r
+\r
+/*\r
+ * Start first task is a separate function so it can be tested in isolation.\r
+ */\r
+extern void vPortStartFirstTask( void );\r
+\r
+/*\r
+ * Function to enable the VFP.\r
+ */\r
+static void vPortEnableVFP( void );\r
+\r
+/*\r
+ * Used to catch tasks that attempt to return from their implementing function.\r
+ */\r
+static void prvTaskExitError( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure\r
+ * FreeRTOS API functions are not called from interrupts that have been assigned\r
+ * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.\r
+ */\r
+#if ( configASSERT_DEFINED == 1 )\r
+ static uint8_t ucMaxSysCallPriority = 0;\r
+ static uint32_t ulMaxPRIGROUPValue = 0;\r
+#endif /* configASSERT_DEFINED */\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * See header file for description.\r
+ */\r
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )\r
+{\r
+ /* Simulate the stack frame as it would be created by a context switch\r
+ interrupt. */\r
+\r
+ /* Offset added to account for the way the MCU uses the stack on entry/exit\r
+ of interrupts, and to ensure alignment. */\r
+ pxTopOfStack--;\r
+\r
+ *pxTopOfStack = portINITIAL_XPSR; /* xPSR */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) pxCode; /* PC */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */\r
+\r
+ /* Save code space by skipping register initialisation. */\r
+ pxTopOfStack -= 5; /* R12, R3, R2 and R1. */\r
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */\r
+\r
+ /* A save method is being used that requires each task to maintain its\r
+ own exec return value. */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = portINITIAL_EXEC_RETURN;\r
+\r
+ pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */\r
+\r
+ return pxTopOfStack;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvTaskExitError( void )\r
+{\r
+ /* A function that implements a task must not exit or attempt to return to\r
+ its caller as there is nothing to return to. If a task wants to exit it\r
+ should instead call vTaskDelete( NULL ).\r
+\r
+ Artificially force an assert() to be triggered if configASSERT() is\r
+ defined, then stop here so application writers can catch the error. */\r
+ configASSERT( uxCriticalNesting == ~0UL );\r
+ portDISABLE_INTERRUPTS();\r
+ for ( ;; );\r
+}\r
+\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * See header file for description.\r
+ */\r
+BaseType_t xPortStartScheduler( void )\r
+{\r
+ /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.\r
+ See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */\r
+ configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );\r
+\r
+ /* This port is designed for nRF52, this is Cortex-M4 r0p1. */\r
+ configASSERT( SCB->CPUID == portCORTEX_M4_r0p1_ID );\r
+\r
+ #if ( configASSERT_DEFINED == 1 )\r
+ {\r
+ volatile uint32_t ulOriginalPriority;\r
+ volatile uint8_t * const pucFirstUserPriorityRegister = &NVIC->IP[0];\r
+ volatile uint8_t ucMaxPriorityValue;\r
+\r
+ /* Determine the maximum priority from which ISR safe FreeRTOS API\r
+ functions can be called. ISR safe functions are those that end in\r
+ "FromISR". FreeRTOS maintains separate thread and ISR API functions to\r
+ ensure interrupt entry is as fast and simple as possible.\r
+\r
+ Save the interrupt priority value that is about to be clobbered. */\r
+ ulOriginalPriority = *pucFirstUserPriorityRegister;\r
+\r
+ /* Determine the number of priority bits available. First write to all\r
+ possible bits. */\r
+ *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;\r
+\r
+ /* Read the value back to see how many bits stuck. */\r
+ ucMaxPriorityValue = *pucFirstUserPriorityRegister;\r
+\r
+ /* Use the same mask on the maximum system call priority. */\r
+ ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;\r
+\r
+ /* Calculate the maximum acceptable priority group value for the number\r
+ of bits read back. */\r
+ ulMaxPRIGROUPValue = SCB_AIRCR_PRIGROUP_Msk >> SCB_AIRCR_PRIGROUP_Pos;\r
+ while ( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )\r
+ {\r
+ ulMaxPRIGROUPValue--;\r
+ ucMaxPriorityValue <<= ( uint8_t ) 0x01;\r
+ }\r
+\r
+ /* Remove any bits that are more than actually existing. */\r
+ ulMaxPRIGROUPValue &= SCB_AIRCR_PRIGROUP_Msk >> SCB_AIRCR_PRIGROUP_Pos;\r
+\r
+ /* Restore the clobbered interrupt priority register to its original\r
+ value. */\r
+ *pucFirstUserPriorityRegister = ulOriginalPriority;\r
+ }\r
+ #endif /* conifgASSERT_DEFINED */\r
+\r
+ /* Make PendSV the lowest priority interrupts. */\r
+ NVIC_SetPriority(PendSV_IRQn, configKERNEL_INTERRUPT_PRIORITY);\r
+\r
+ /* Start the timer that generates the tick ISR. Interrupts are disabled\r
+ here already. */\r
+ vPortSetupTimerInterrupt();\r
+\r
+ /* Initialise the critical nesting count ready for the first task. */\r
+ uxCriticalNesting = 0;\r
+\r
+ /* Ensure the VFP is enabled - it should be anyway. */\r
+ vPortEnableVFP();\r
+\r
+ /* Lazy save always. */\r
+ FPU->FPCCR |= FPU_FPCCR_ASPEN_Msk | FPU_FPCCR_LSPEN_Msk;\r
+\r
+ /* Finally this port requires SEVONPEND to be active */\r
+ SCB->SCR |= SCB_SCR_SEVONPEND_Msk;\r
+\r
+ /* Start the first task. */\r
+ vPortStartFirstTask();\r
+\r
+ /* Should never get here as the tasks will now be executing! Call the task\r
+ exit error function to prevent compiler warnings about a static function\r
+ not being called in the case that the application writer overrides this\r
+ functionality by defining configTASK_RETURN_ADDRESS. */\r
+ prvTaskExitError();\r
+\r
+ /* Should not get here! */\r
+ return 0;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortEndScheduler( void )\r
+{\r
+ /* Not implemented in ports where there is nothing to return to.\r
+ Artificially force an assert. */\r
+ configASSERT( uxCriticalNesting == 1000UL );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortEnterCritical( void )\r
+{\r
+ portDISABLE_INTERRUPTS();\r
+ uxCriticalNesting++;\r
+\r
+ /* This is not the interrupt safe version of the enter critical function so\r
+ assert() if it is being called from an interrupt context. Only API\r
+ functions that end in "FromISR" can be used in an interrupt. Only assert if\r
+ the critical nesting count is 1 to protect against recursive calls if the\r
+ assert function also uses a critical section. */\r
+ if ( uxCriticalNesting == 1 )\r
+ {\r
+ configASSERT( ( SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk ) == 0 );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortExitCritical( void )\r
+{\r
+ configASSERT( uxCriticalNesting );\r
+ uxCriticalNesting--;\r
+ if ( uxCriticalNesting == 0 )\r
+ {\r
+ portENABLE_INTERRUPTS();\r
+ }\r
+}\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* This is a naked function. */\r
+static void vPortEnableVFP( void )\r
+{\r
+ SCB->CPACR |= 0xf << 20;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#if ( configASSERT_DEFINED == 1 )\r
+\r
+ void vPortValidateInterruptPriority( void )\r
+ {\r
+ uint32_t ulCurrentInterrupt;\r
+ uint8_t ucCurrentPriority;\r
+ IPSR_Type ipsr;\r
+\r
+ /* Obtain the number of the currently executing interrupt. */\r
+ ipsr.w = __get_IPSR();\r
+ ulCurrentInterrupt = ipsr.b.ISR;\r
+\r
+ /* Is the interrupt number a user defined interrupt? */\r
+ if ( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )\r
+ {\r
+ /* Look up the interrupt's priority. */\r
+ ucCurrentPriority = NVIC->IP[ ulCurrentInterrupt - portFIRST_USER_INTERRUPT_NUMBER ];\r
+\r
+ /* The following assertion will fail if a service routine (ISR) for\r
+ an interrupt that has been assigned a priority above\r
+ configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API\r
+ function. ISR safe FreeRTOS API functions must *only* be called\r
+ from interrupts that have been assigned a priority at or below\r
+ configMAX_SYSCALL_INTERRUPT_PRIORITY.\r
+\r
+ Numerically low interrupt priority numbers represent logically high\r
+ interrupt priorities, therefore the priority of the interrupt must\r
+ be set to a value equal to or numerically *higher* than\r
+ configMAX_SYSCALL_INTERRUPT_PRIORITY.\r
+\r
+ Interrupts that use the FreeRTOS API must not be left at their\r
+ default priority of zero as that is the highest possible priority,\r
+ which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,\r
+ and therefore also guaranteed to be invalid.\r
+\r
+ FreeRTOS maintains separate thread and ISR API functions to ensure\r
+ interrupt entry is as fast and simple as possible.\r
+\r
+ The following links provide detailed information:\r
+ http://www.freertos.org/RTOS-Cortex-M3-M4.html\r
+ http://www.freertos.org/FAQHelp.html */\r
+ configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );\r
+ }\r
+\r
+ /* Priority grouping: The interrupt controller (NVIC) allows the bits\r
+ that define each interrupt's priority to be split between bits that\r
+ define the interrupt's pre-emption priority bits and bits that define\r
+ the interrupt's sub-priority. For simplicity all bits must be defined\r
+ to be pre-emption priority bits. The following assertion will fail if\r
+ this is not the case (if some bits represent a sub-priority).\r
+\r
+ If the application only uses CMSIS libraries for interrupt\r
+ configuration then the correct setting can be achieved on all Cortex-M\r
+ devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the\r
+ scheduler. Note however that some vendor specific peripheral libraries\r
+ assume a non-zero priority group setting, in which cases using a value\r
+ of zero will result in unpredicable behaviour. */\r
+ configASSERT( NVIC_GetPriorityGrouping() <= ulMaxPRIGROUPValue );\r
+ }\r
+\r
+#endif /* configASSERT_DEFINED */\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.0.0\r
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software. If you wish to use our Amazon\r
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "app_util.h"\r
+\r
+#ifdef SOFTDEVICE_PRESENT\r
+#include "nrf_soc.h"\r
+#include "nrf_sdh.h"\r
+#include "app_error.h"\r
+#include "app_util_platform.h"\r
+#endif\r
+\r
+/*-----------------------------------------------------------\r
+ * Implementation of functions defined in portable.h for the ARM CM4F port.\r
+ * CMSIS compatible layer to menage SysTick ticking source.\r
+ *----------------------------------------------------------*/\r
+\r
+#if configTICK_SOURCE == FREERTOS_USE_SYSTICK\r
+\r
+\r
+#ifndef configSYSTICK_CLOCK_HZ\r
+ #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ\r
+ /* Ensure the SysTick is clocked at the same frequency as the core. */\r
+ #define portNVIC_SYSTICK_CLK_BIT ( SysTick_CTRL_CLKSOURCE_Msk )\r
+#else\r
+ /* The way the SysTick is clocked is not modified in case it is not the same\r
+ as the core. */\r
+ #define portNVIC_SYSTICK_CLK_BIT ( 0 )\r
+#endif\r
+\r
+\r
+#if configUSE_TICKLESS_IDLE == 1\r
+ #error SysTick port for RF52 does not support tickless idle. Use RTC mode instead.\r
+#endif /* configUSE_TICKLESS_IDLE */\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void xPortSysTickHandler( void )\r
+{\r
+ /* The SysTick runs at the lowest interrupt priority, so when this interrupt\r
+ executes all interrupts must be unmasked. There is therefore no need to\r
+ save and then restore the interrupt mask value as its value is already\r
+ known. */\r
+ ( void ) portSET_INTERRUPT_MASK_FROM_ISR();\r
+ {\r
+ /* Increment the RTOS tick. */\r
+ if ( xTaskIncrementTick() != pdFALSE )\r
+ {\r
+ /* A context switch is required. Context switching is performed in\r
+ the PendSV interrupt. Pend the PendSV interrupt. */\r
+ SCB->ICSR = SCB_ICSR_PENDSVSET_Msk;\r
+ __SEV();\r
+ }\r
+ }\r
+ portCLEAR_INTERRUPT_MASK_FROM_ISR( 0 );\r
+}\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Setup the systick timer to generate the tick interrupts at the required\r
+ * frequency.\r
+ */\r
+void vPortSetupTimerInterrupt( void )\r
+{\r
+ /* Set interrupt priority */\r
+ NVIC_SetPriority(SysTick_IRQn, configKERNEL_INTERRUPT_PRIORITY);\r
+ /* Configure SysTick to interrupt at the requested rate. */\r
+ SysTick->LOAD = ROUNDED_DIV(configSYSTICK_CLOCK_HZ, configTICK_RATE_HZ) - 1UL;\r
+ SysTick->CTRL = ( portNVIC_SYSTICK_CLK_BIT | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk );\r
+}\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+#elif configTICK_SOURCE == FREERTOS_USE_RTC\r
+\r
+#if configUSE_16_BIT_TICKS == 1\r
+#error This port does not support 16 bit ticks.\r
+#endif\r
+\r
+#include "nrf_rtc.h"\r
+#include "nrf_drv_clock.h"\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void xPortSysTickHandler( void )\r
+{\r
+#if configUSE_TICKLESS_IDLE == 1\r
+ nrf_rtc_event_clear(portNRF_RTC_REG, NRF_RTC_EVENT_COMPARE_0);\r
+#endif\r
+\r
+ BaseType_t switch_req = pdFALSE;\r
+ uint32_t isrstate = portSET_INTERRUPT_MASK_FROM_ISR();\r
+\r
+ uint32_t systick_counter = nrf_rtc_counter_get(portNRF_RTC_REG);\r
+ nrf_rtc_event_clear(portNRF_RTC_REG, NRF_RTC_EVENT_TICK);\r
+\r
+ if (configUSE_DISABLE_TICK_AUTO_CORRECTION_DEBUG == 0)\r
+ {\r
+ /* check FreeRTOSConfig.h file for more details on configUSE_DISABLE_TICK_AUTO_CORRECTION_DEBUG */\r
+ TickType_t diff;\r
+ diff = (systick_counter - xTaskGetTickCount()) & portNRF_RTC_MAXTICKS;\r
+\r
+ /* At most 1 step if scheduler is suspended - the xTaskIncrementTick\r
+ * would return the tick state from the moment when suspend function was called. */\r
+ if ((diff > 1) && (xTaskGetSchedulerState() != taskSCHEDULER_RUNNING))\r
+ {\r
+ diff = 1;\r
+ }\r
+ while ((diff--) > 0)\r
+ {\r
+ switch_req |= xTaskIncrementTick();\r
+ }\r
+ }\r
+ else\r
+ {\r
+ switch_req = xTaskIncrementTick();\r
+ }\r
+\r
+ /* Increment the RTOS tick as usual which checks if there is a need for rescheduling */\r
+ if ( switch_req != pdFALSE )\r
+ {\r
+ /* A context switch is required. Context switching is performed in\r
+ the PendSV interrupt. Pend the PendSV interrupt. */\r
+ SCB->ICSR = SCB_ICSR_PENDSVSET_Msk;\r
+ __SEV();\r
+ }\r
+\r
+ portCLEAR_INTERRUPT_MASK_FROM_ISR( isrstate );\r
+}\r
+\r
+/*\r
+ * Setup the RTC time to generate the tick interrupts at the required\r
+ * frequency.\r
+ */\r
+void vPortSetupTimerInterrupt( void )\r
+{\r
+ /* Request LF clock */\r
+ nrf_drv_clock_lfclk_request(NULL);\r
+\r
+ /* Configure SysTick to interrupt at the requested rate. */\r
+ nrf_rtc_prescaler_set(portNRF_RTC_REG, portNRF_RTC_PRESCALER);\r
+ nrf_rtc_int_enable (portNRF_RTC_REG, RTC_INTENSET_TICK_Msk);\r
+ nrf_rtc_task_trigger (portNRF_RTC_REG, NRF_RTC_TASK_CLEAR);\r
+ nrf_rtc_task_trigger (portNRF_RTC_REG, NRF_RTC_TASK_START);\r
+ nrf_rtc_event_enable(portNRF_RTC_REG, RTC_EVTEN_OVRFLW_Msk);\r
+\r
+ NVIC_SetPriority(portNRF_RTC_IRQn, configKERNEL_INTERRUPT_PRIORITY);\r
+ NVIC_EnableIRQ(portNRF_RTC_IRQn);\r
+}\r
+\r
+#if configUSE_TICKLESS_IDLE == 1\r
+\r
+void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )\r
+{\r
+ /*\r
+ * Implementation note:\r
+ *\r
+ * To help debugging the option configUSE_TICKLESS_IDLE_SIMPLE_DEBUG was presented.\r
+ * This option would make sure that even if program execution was stopped inside\r
+ * this function no more than expected number of ticks would be skipped.\r
+ *\r
+ * Normally RTC works all the time even if firmware execution was stopped\r
+ * and that may lead to skipping too much of ticks.\r
+ */\r
+ TickType_t enterTime;\r
+\r
+ /* Make sure the SysTick reload value does not overflow the counter. */\r
+ if ( xExpectedIdleTime > portNRF_RTC_MAXTICKS - configEXPECTED_IDLE_TIME_BEFORE_SLEEP )\r
+ {\r
+ xExpectedIdleTime = portNRF_RTC_MAXTICKS - configEXPECTED_IDLE_TIME_BEFORE_SLEEP;\r
+ }\r
+ /* Block all the interrupts globally */\r
+#ifdef SOFTDEVICE_PRESENT\r
+ do{\r
+ uint8_t dummy = 0;\r
+ uint32_t err_code = sd_nvic_critical_region_enter(&dummy);\r
+ APP_ERROR_CHECK(err_code);\r
+ }while (0);\r
+#else\r
+ __disable_irq();\r
+#endif\r
+\r
+ enterTime = nrf_rtc_counter_get(portNRF_RTC_REG);\r
+\r
+ if ( eTaskConfirmSleepModeStatus() != eAbortSleep )\r
+ {\r
+ TickType_t xModifiableIdleTime;\r
+ TickType_t wakeupTime = (enterTime + xExpectedIdleTime) & portNRF_RTC_MAXTICKS;\r
+\r
+ /* Stop tick events */\r
+ nrf_rtc_int_disable(portNRF_RTC_REG, NRF_RTC_INT_TICK_MASK);\r
+\r
+ /* Configure CTC interrupt */\r
+ nrf_rtc_cc_set(portNRF_RTC_REG, 0, wakeupTime);\r
+ nrf_rtc_event_clear(portNRF_RTC_REG, NRF_RTC_EVENT_COMPARE_0);\r
+ nrf_rtc_int_enable(portNRF_RTC_REG, NRF_RTC_INT_COMPARE0_MASK);\r
+\r
+ __DSB();\r
+\r
+ /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can\r
+ * set its parameter to 0 to indicate that its implementation contains\r
+ * its own wait for interrupt or wait for event instruction, and so wfi\r
+ * should not be executed again. However, the original expected idle\r
+ * time variable must remain unmodified, so a copy is taken. */\r
+ xModifiableIdleTime = xExpectedIdleTime;\r
+ configPRE_SLEEP_PROCESSING( xModifiableIdleTime );\r
+ if ( xModifiableIdleTime > 0 )\r
+ {\r
+#if 0 // With FreeRTOS sd_app_evt_wait increases power consumption with FreeRTOS compared to _WFE (NRFFOSDK-11174)\r
+#ifdef SOFTDEVICE_PRESENT\r
+ if (nrf_sdh_is_enabled())\r
+ {\r
+ uint32_t err_code = sd_app_evt_wait();\r
+ APP_ERROR_CHECK(err_code);\r
+ }\r
+ else\r
+#endif\r
+#endif // (NRFFOSDK-11174)\r
+ {\r
+ /* No SD - we would just block interrupts globally.\r
+ * BASEPRI cannot be used for that because it would prevent WFE from wake up.\r
+ */\r
+ do{\r
+ __WFE();\r
+ } while (0 == (NVIC->ISPR[0] | NVIC->ISPR[1]));\r
+ }\r
+ }\r
+ configPOST_SLEEP_PROCESSING( xExpectedIdleTime );\r
+\r
+ nrf_rtc_int_disable(portNRF_RTC_REG, NRF_RTC_INT_COMPARE0_MASK);\r
+ nrf_rtc_event_clear(portNRF_RTC_REG, NRF_RTC_EVENT_COMPARE_0);\r
+\r
+ /* Correct the system ticks */\r
+ {\r
+ TickType_t diff;\r
+ TickType_t exitTime;\r
+\r
+ nrf_rtc_event_clear(portNRF_RTC_REG, NRF_RTC_EVENT_TICK);\r
+ nrf_rtc_int_enable (portNRF_RTC_REG, NRF_RTC_INT_TICK_MASK);\r
+\r
+ exitTime = nrf_rtc_counter_get(portNRF_RTC_REG);\r
+ diff = (exitTime - enterTime) & portNRF_RTC_MAXTICKS;\r
+\r
+ /* It is important that we clear pending here so that our corrections are latest and in sync with tick_interrupt handler */\r
+ NVIC_ClearPendingIRQ(portNRF_RTC_IRQn);\r
+\r
+ if ((configUSE_TICKLESS_IDLE_SIMPLE_DEBUG) && (diff > xExpectedIdleTime))\r
+ {\r
+ diff = xExpectedIdleTime;\r
+ }\r
+\r
+ if (diff > 0)\r
+ {\r
+ vTaskStepTick(diff);\r
+ }\r
+ }\r
+ }\r
+#ifdef SOFTDEVICE_PRESENT\r
+ uint32_t err_code = sd_nvic_critical_region_exit(0);\r
+ APP_ERROR_CHECK(err_code);\r
+#else\r
+ __enable_irq();\r
+#endif\r
+}\r
+\r
+#endif // configUSE_TICKLESS_IDLE\r
+\r
+#else // configTICK_SOURCE\r
+ #error Unsupported configTICK_SOURCE value\r
+#endif // configTICK_SOURCE == FREERTOS_USE_SYSTICK\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.0.0\r
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software. If you wish to use our Amazon\r
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+\r
+#ifndef PORTMACRO_H\r
+#define PORTMACRO_H\r
+\r
+#include "portmacro_cmsis.h"\r
+\r
+#endif /* PORTMACRO_H */\r
+\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.0.0\r
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software. If you wish to use our Amazon\r
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+#ifndef PORTMACRO_CMSIS_H\r
+#define PORTMACRO_CMSIS_H\r
+#include "app_util.h"\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/*-----------------------------------------------------------\r
+ * Port specific definitions.\r
+ *\r
+ * The settings in this file configure FreeRTOS correctly for the\r
+ * given hardware and compiler.\r
+ *\r
+ * These settings should not be altered.\r
+ *-----------------------------------------------------------\r
+ */\r
+\r
+/* Type definitions. */\r
+#define portCHAR char\r
+#define portFLOAT float\r
+#define portDOUBLE double\r
+#define portLONG long\r
+#define portSHORT short\r
+#define portSTACK_TYPE uint32_t\r
+#define portBASE_TYPE long\r
+\r
+typedef portSTACK_TYPE StackType_t;\r
+typedef long BaseType_t;\r
+typedef unsigned long UBaseType_t;\r
+\r
+#if ( configUSE_16_BIT_TICKS == 1 )\r
+ typedef uint16_t TickType_t;\r
+ #define portMAX_DELAY ( TickType_t ) 0xffff\r
+#else\r
+ typedef uint32_t TickType_t;\r
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL\r
+\r
+ /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do\r
+ not need to be guarded with a critical section. */\r
+ #define portTICK_TYPE_IS_ATOMIC 1\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Architecture specifics. */\r
+#define portSTACK_GROWTH ( -1 )\r
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )\r
+#define portBYTE_ALIGNMENT 8\r
+\r
+/* RTC register */\r
+#define portNRF_RTC_REG NRF_RTC1\r
+/* IRQn used by the selected RTC */\r
+#define portNRF_RTC_IRQn RTC1_IRQn\r
+/* Constants required to manipulate the NVIC. */\r
+#define portNRF_RTC_PRESCALER ( (uint32_t) (ROUNDED_DIV(configSYSTICK_CLOCK_HZ, configTICK_RATE_HZ) - 1) )\r
+/* Maximum RTC ticks */\r
+#define portNRF_RTC_MAXTICKS ((1U<<24)-1U)\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Scheduler utilities. */\r
+#define portYIELD() do \\r
+{ \\r
+ /* Set a PendSV to request a context switch. */ \\r
+ SCB->ICSR = SCB_ICSR_PENDSVSET_Msk; \\r
+ __SEV(); \\r
+ /* Barriers are normally not required but do ensure the code is completely \\r
+ within the specified behaviour for the architecture. */ \\r
+ __DSB(); \\r
+ __ISB(); \\r
+}while (0)\r
+\r
+#define portEND_SWITCHING_ISR( xSwitchRequired ) if ( (xSwitchRequired) != pdFALSE ) portYIELD()\r
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Critical section management. */\r
+extern void vPortEnterCritical( void );\r
+extern void vPortExitCritical( void );\r
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortRaiseBASEPRI()\r
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vPortSetBASEPRI(x)\r
+#define portDISABLE_INTERRUPTS() vPortRaiseBASEPRI()\r
+#define portENABLE_INTERRUPTS() vPortSetBASEPRI(0)\r
+#define portENTER_CRITICAL() vPortEnterCritical()\r
+#define portEXIT_CRITICAL() vPortExitCritical()\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Task function macros as described on the FreeRTOS.org WEB site. These are\r
+not necessary for to use this port. They are defined so the common demo files\r
+(which build with all the ports) will build. */\r
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Tickless idle/low power functionality. */\r
+#ifndef portSUPPRESS_TICKS_AND_SLEEP\r
+ extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );\r
+ #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Architecture specific optimisations. */\r
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION\r
+ #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1\r
+#endif\r
+\r
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1\r
+\r
+ /* Count leading zeros helper. */\r
+ #define ucPortCountLeadingZeros( bits ) __CLZ( bits )\r
+\r
+ /* Check the configuration. */\r
+ #if ( configMAX_PRIORITIES > 32 )\r
+ #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.\r
+ #endif\r
+\r
+ /* Store/clear the ready priorities in a bit map. */\r
+ #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )\r
+ #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )\r
+\r
+ /*-----------------------------------------------------------*/\r
+\r
+ #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )\r
+\r
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+#ifdef configASSERT\r
+ void vPortValidateInterruptPriority( void );\r
+ #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()\r
+#endif\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+#define vPortSetBASEPRI( ulNewMaskValue ) __set_BASEPRI(ulNewMaskValue)\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+#define vPortRaiseBASEPRI( ) vPortSetBASEPRI(configMAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS))\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+__STATIC_INLINE uint32_t ulPortRaiseBASEPRI( void )\r
+{\r
+ uint32_t ulOriginalBASEPRI = __get_BASEPRI();\r
+ vPortRaiseBASEPRI();\r
+ return ulOriginalBASEPRI;\r
+}\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* PORTMACRO_CMSIS_H */\r
+\r
projects / freertos / commitdiff