\r
/*-----------------------------------------------------------*/\r
\r
-/* \r
- * Enable all the required interrupts in the FEC and in the interrupt controller. \r
+/*\r
+ * Enable all the required interrupts in the FEC and in the interrupt controller.\r
*/\r
static void prvEnableFECInterrupts( void );\r
\r
\r
/*\r
* FUNCTION ADAPTED FROM FREESCALE SUPPLIED SOURCE\r
- * \r
+ *\r
* Write a value to a PHY's MII register.\r
*\r
* Parameters:\r
{\r
unsigned portSHORT usData;\r
struct uip_eth_addr xAddr;\r
+unsigned portBASE_TYPE ux;\r
\r
/* The MAC address is set at the foot of FreeRTOSConfig.h. */\r
const unsigned portCHAR ucMACAddress[6] =\r
/* Wait for auto negotiate to complete. */\r
do\r
{\r
+ ux++;\r
+ if( ux > 10 )\r
+ {\r
+ /* Hardware bug workaround! Force 100Mbps half duplex. */\r
+ while( !fec_mii_read( configPHY_ADDRESS, 0, &usData ) ){};\r
+ usData &= ~0x2000; /* 10Mbps */\r
+ usData &= ~0x0100; /* Half Duplex */\r
+ usData &= ~0x1000; /* Manual Mode */\r
+ while( !fec_mii_write( configPHY_ADDRESS, 0, usData ) ){};\r
+ while( !fec_mii_write( configPHY_ADDRESS, 0, (usData|0x0200) )){}; /* Force re-negotiate */\r
+ break;\r
+ }\r
vTaskDelay( fecLINK_DELAY );\r
fec_mii_read( configPHY_ADDRESS, PHY_BMSR, &usData );\r
\r