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Work-in-progress check in of MicroBlaze Kintex7 demo.
authorrtel <rtel@1d2547de-c912-0410-9cb9-b8ca96c0e9e2>
Tue, 10 Mar 2015 15:58:19 +0000 (15:58 +0000)
committerrtel <rtel@1d2547de-c912-0410-9cb9-b8ca96c0e9e2>
Tue, 10 Mar 2015 15:58:19 +0000 (15:58 +0000)
git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2332 1d2547de-c912-0410-9cb9-b8ca96c0e9e2

19 files changed:
FreeRTOS/Demo/Common/Minimal/IntSemTest.c patch | blob | history
FreeRTOS/Demo/Common/Minimal/TimerDemo.c patch | blob | history
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/.cproject [new file with mode: 0644] patch | blob
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/.project [new file with mode: 0644] patch | blob
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/.sdkproject [new file with mode: 0644] patch | blob
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/Makefile [new file with mode: 0644] patch | blob
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/system.mss [new file with mode: 0644] patch | blob
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/Hardware/.project [new file with mode: 0644] patch | blob
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/Hardware/base_microblaze_design.hwh [new file with mode: 0644] patch | blob
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/Hardware/base_microblaze_design_bd.tcl [new file with mode: 0644] patch | blob
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/Hardware/base_microblaze_design_wrapper.bit [new file with mode: 0644] patch | blob
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/Hardware/base_microblaze_design_wrapper.mmi [new file with mode: 0644] patch | blob
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/Hardware/sysdef.xml [new file with mode: 0644] patch | blob
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/Hardware/system.hdf [new file with mode: 0644] patch | blob
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/.project patch | blob | history
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/src/Full_Demo/main_full.c patch | blob | history
FreeRTOS/Source/include/projdefs.h patch | blob | history
FreeRTOS/Source/portable/RVDS/ARM_CM4F/port.c patch | blob | history
FreeRTOS/Source/queue.c patch | blob | history

diff --git a/FreeRTOS/Demo/Common/Minimal/IntSemTest.c b/FreeRTOS/Demo/Common/Minimal/IntSemTest.c
index 8f21e8296e7899f046769aa3da947d235611dc72..e9ecdacf6697b51e1ac037555e023c165c03cdca 100644 (file)
--- a/FreeRTOS/Demo/Common/Minimal/IntSemTest.c
+++ b/FreeRTOS/Demo/Common/Minimal/IntSemTest.c
@@ -512,7 +512,7 @@ TickType_t xTimeNow;
        /* No mutual exclusion on xOkToGiveMutex, but this is only test code (and\r
        only executed on a 32-bit architecture) so ignore that in this case. */\r
        xTimeNow = xTaskGetTickCountFromISR();\r
-       if( ( xTimeNow - xLastGiveTime ) >= pdMS_TO_TICKS( intsemINTERRUPT_MUTEX_GIVE_PERIOD_MS ) )\r
+       if( ( ( TickType_t ) ( xTimeNow - xLastGiveTime ) ) >= pdMS_TO_TICKS( intsemINTERRUPT_MUTEX_GIVE_PERIOD_MS ) )\r
        {\r
                configASSERT( xISRMutex );\r
                if( xOkToGiveMutex != pdFALSE )\r
diff --git a/FreeRTOS/Demo/Common/Minimal/TimerDemo.c b/FreeRTOS/Demo/Common/Minimal/TimerDemo.c
index e8f44fe888c4c0333eb6a248f2533c8c5cbffe23..61a5b71cd4aa76e09b7a48ef0b9fe40ebab21900 100644 (file)
--- a/FreeRTOS/Demo/Common/Minimal/TimerDemo.c
+++ b/FreeRTOS/Demo/Common/Minimal/TimerDemo.c
@@ -395,10 +395,14 @@ static void       prvTest3_CheckAutoReloadExpireRates( void )
 {\r
 uint8_t ucMaxAllowableValue, ucMinAllowableValue, ucTimer;\r
 TickType_t xBlockPeriod, xTimerPeriod, xExpectedNumber;\r
-\r
-       /* Check the auto reload timers expire at the expected rates. */\r
-\r
-\r
+UBaseType_t uxOriginalPriority;\r
+\r
+       /* Check the auto reload timers expire at the expected rates.  Do this at a\r
+       high priority for maximum accuracy.  This is ok as most of the time is spent\r
+       in the Blocked state. */\r
+       uxOriginalPriority = uxTaskPriorityGet( NULL );\r
+       vTaskPrioritySet( NULL, ( configMAX_PRIORITIES - 1 ) );\r
+       \r
        /* Delaying for configTIMER_QUEUE_LENGTH * xBasePeriod ticks should allow\r
        all the auto reload timers to expire at least once. */\r
        xBlockPeriod = ( ( TickType_t ) configTIMER_QUEUE_LENGTH ) * xBasePeriod;\r
@@ -425,6 +429,9 @@ TickType_t xBlockPeriod, xTimerPeriod, xExpectedNumber;
                }\r
        }\r
 \r
+       /* Return to the original priority. */\r
+       vTaskPrioritySet( NULL, uxOriginalPriority );\r
+\r
        if( xTestStatus == pdPASS )\r
        {\r
                /* No errors have been reported so increment the loop counter so the\r
diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/.cproject b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/.cproject
new file mode 100644 (file)
index 0000000..9e3529d
--- /dev/null
+++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/.cproject
@@ -0,0 +1,13 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>\r
+<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">\r
+       <storageModule moduleId="org.eclipse.cdt.core.settings">\r
+               <cconfiguration id="org.eclipse.cdt.core.default.config.1741365255">\r
+                       <storageModule buildSystemId="org.eclipse.cdt.core.defaultConfigDataProvider" id="org.eclipse.cdt.core.default.config.1741365255" moduleId="org.eclipse.cdt.core.settings" name="Configuration">\r
+                               <externalSettings/>\r
+                               <extensions/>\r
+                       </storageModule>\r
+                       <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>\r
+               </cconfiguration>\r
+       </storageModule>\r
+       <storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>\r
+</cproject>\r
diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/.project b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/.project
new file mode 100644 (file)
index 0000000..b58d878
--- /dev/null
+++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/.project
@@ -0,0 +1,76 @@
+<?xml version="1.0" encoding="UTF-8"?>\r
+<projectDescription>\r
+       <name>BSP</name>\r
+       <comment>Created by SDK v2014.4</comment>\r
+       <projects>\r
+               <project>Hardware</project>\r
+       </projects>\r
+       <buildSpec>\r
+               <buildCommand>\r
+                       <name>org.eclipse.cdt.make.core.makeBuilder</name>\r
+                       <arguments>\r
+                               <dictionary>\r
+                                       <key>org.eclipse.cdt.core.errorOutputParser</key>\r
+                                       <value>org.eclipse.cdt.core.GASErrorParser;org.eclipse.cdt.core.GLDErrorParser;org.eclipse.cdt.core.GCCErrorParser;org.eclipse.cdt.core.GmakeErrorParser;org.eclipse.cdt.core.VCErrorParser;org.eclipse.cdt.core.CWDLocator;org.eclipse.cdt.core.MakeErrorParser;</value>\r
+                               </dictionary>\r
+                               <dictionary>\r
+                                       <key>org.eclipse.cdt.make.core.append_environment</key>\r
+                                       <value>true</value>\r
+                               </dictionary>\r
+                               <dictionary>\r
+                                       <key>org.eclipse.cdt.make.core.build.arguments</key>\r
+                                       <value></value>\r
+                               </dictionary>\r
+                               <dictionary>\r
+                                       <key>org.eclipse.cdt.make.core.build.command</key>\r
+                                       <value>make</value>\r
+                               </dictionary>\r
+                               <dictionary>\r
+                                       <key>org.eclipse.cdt.make.core.build.target.auto</key>\r
+                                       <value>all</value>\r
+                               </dictionary>\r
+                               <dictionary>\r
+                                       <key>org.eclipse.cdt.make.core.build.target.clean</key>\r
+                                       <value>clean</value>\r
+                               </dictionary>\r
+                               <dictionary>\r
+                                       <key>org.eclipse.cdt.make.core.build.target.inc</key>\r
+                                       <value>all</value>\r
+                               </dictionary>\r
+                               <dictionary>\r
+                                       <key>org.eclipse.cdt.make.core.enableAutoBuild</key>\r
+                                       <value>true</value>\r
+                               </dictionary>\r
+                               <dictionary>\r
+                                       <key>org.eclipse.cdt.make.core.enableCleanBuild</key>\r
+                                       <value>true</value>\r
+                               </dictionary>\r
+                               <dictionary>\r
+                                       <key>org.eclipse.cdt.make.core.enableFullBuild</key>\r
+                                       <value>true</value>\r
+                               </dictionary>\r
+                               <dictionary>\r
+                                       <key>org.eclipse.cdt.make.core.enabledIncrementalBuild</key>\r
+                                       <value>true</value>\r
+                               </dictionary>\r
+                               <dictionary>\r
+                                       <key>org.eclipse.cdt.make.core.environment</key>\r
+                                       <value></value>\r
+                               </dictionary>\r
+                               <dictionary>\r
+                                       <key>org.eclipse.cdt.make.core.stopOnError</key>\r
+                                       <value>false</value>\r
+                               </dictionary>\r
+                               <dictionary>\r
+                                       <key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>\r
+                                       <value>true</value>\r
+                               </dictionary>\r
+                       </arguments>\r
+               </buildCommand>\r
+       </buildSpec>\r
+       <natures>\r
+               <nature>com.xilinx.sdk.sw.SwProjectNature</nature>\r
+               <nature>org.eclipse.cdt.core.cnature</nature>\r
+               <nature>org.eclipse.cdt.make.core.makeNature</nature>\r
+       </natures>\r
+</projectDescription>\r
diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/.sdkproject b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/.sdkproject
new file mode 100644 (file)
index 0000000..d75738c
--- /dev/null
+++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/.sdkproject
@@ -0,0 +1,3 @@
+THIRPARTY=false
+PROCESSOR=microblaze_0
+MSS_FILE=system.mss
diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/Makefile b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/Makefile
new file mode 100644 (file)
index 0000000..2c54e15
--- /dev/null
+++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/Makefile
@@ -0,0 +1,31 @@
+# Makefile generated by Xilinx.\r
+\r
+PROCESSOR = microblaze_0\r
+LIBRARIES = ${PROCESSOR}/lib/libxil.a\r
+BSP_MAKEFILES := $(wildcard $(PROCESSOR)/libsrc/*/src/Makefile)\r
+SUBDIRS := $(patsubst %/Makefile, %, $(BSP_MAKEFILES))\r
+\r
+ifneq (,$(findstring win,$(RDI_PLATFORM)))\r
+ SHELL = CMD\r
+endif\r
+\r
+all: libs\r
+       @echo 'Finished building libraries'\r
+\r
+include: $(addsuffix /make.include,$(SUBDIRS))\r
+\r
+libs: $(addsuffix /make.libs,$(SUBDIRS))\r
+\r
+$(PROCESSOR)/lib/libxil.a: $(PROCESSOR)/lib/libxil_init.a\r
+       cp -f $< $@\r
+\r
+%/make.include: $(if $(wildcard $(PROCESSOR)/lib/libxil_init.a),$(PROCESSOR)/lib/libxil.a,)\r
+       @echo "Running Make include in $(subst /make.include,,$@)"\r
+       $(MAKE) -C $(subst /make.include,,$@) -s include  "SHELL=$(SHELL)" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS= -O2 -c -mcpu=v9.4 -mhard-float -mlittle-endian -mno-xl-soft-div -mno-xl-soft-mul -mxl-barrel-shift -mxl-float-convert -mxl-float-sqrt -mxl-multiply-high -mxl-pattern-compare" "EXTRA_COMPILER_FLAGS=-g -ffunction-sections -fdata-sections"\r
+\r
+%/make.libs: include\r
+       @echo "Running Make libs in $(subst /make.libs,,$@)"\r
+       $(MAKE) -C $(subst /make.libs,,$@) -s libs  "SHELL=$(SHELL)" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS= -O2 -c -mcpu=v9.4 -mhard-float -mlittle-endian -mno-xl-soft-div -mno-xl-soft-mul -mxl-barrel-shift -mxl-float-convert -mxl-float-sqrt -mxl-multiply-high -mxl-pattern-compare" "EXTRA_COMPILER_FLAGS=-g -ffunction-sections -fdata-sections"\r
+\r
+clean:\r
+       rm -f ${PROCESSOR}/lib/libxil.a\r
diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/system.mss b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/system.mss
new file mode 100644 (file)
index 0000000..2873863
--- /dev/null
+++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/system.mss
@@ -0,0 +1,78 @@
+\r
+ PARAMETER NAME = C:\E\Dev\FreeRTOS\WorkingCopy\FreeRTOS\Demo\MicroBlaze_Kintex7_EthernetLite\BSP\system.mss\r
+\r
+ PARAMETER VERSION = 2.2.0\r
+\r
+\r
+BEGIN OS\r
+ PARAMETER OS_NAME = standalone\r
+ PARAMETER OS_VER = 4.2\r
+ PARAMETER PROC_INSTANCE = microblaze_0\r
+ PARAMETER stdin = axi_uartlite_0\r
+ PARAMETER stdout = axi_uartlite_0\r
+END\r
+\r
+\r
+BEGIN PROCESSOR\r
+ PARAMETER DRIVER_NAME = cpu\r
+ PARAMETER DRIVER_VER = 2.2\r
+ PARAMETER HW_INSTANCE = microblaze_0\r
+END\r
+\r
+\r
+BEGIN DRIVER\r
+ PARAMETER DRIVER_NAME = emaclite\r
+ PARAMETER DRIVER_VER = 4.0\r
+ PARAMETER HW_INSTANCE = axi_ethernetlite_0\r
+END\r
+\r
+BEGIN DRIVER\r
+ PARAMETER DRIVER_NAME = gpio\r
+ PARAMETER DRIVER_VER = 4.0\r
+ PARAMETER HW_INSTANCE = axi_gpio_0\r
+END\r
+\r
+BEGIN DRIVER\r
+ PARAMETER DRIVER_NAME = intc\r
+ PARAMETER DRIVER_VER = 3.2\r
+ PARAMETER HW_INSTANCE = axi_intc_0\r
+END\r
+\r
+BEGIN DRIVER\r
+ PARAMETER DRIVER_NAME = tmrctr\r
+ PARAMETER DRIVER_VER = 3.0\r
+ PARAMETER HW_INSTANCE = axi_timer_0\r
+END\r
+\r
+BEGIN DRIVER\r
+ PARAMETER DRIVER_NAME = uartlite\r
+ PARAMETER DRIVER_VER = 3.0\r
+ PARAMETER HW_INSTANCE = axi_uartlite_0\r
+END\r
+\r
+BEGIN DRIVER\r
+ PARAMETER DRIVER_NAME = bram\r
+ PARAMETER DRIVER_VER = 4.0\r
+ PARAMETER HW_INSTANCE = microblaze_0_local_memory_dlmb_bram_if_cntlr\r
+END\r
+\r
+BEGIN DRIVER\r
+ PARAMETER DRIVER_NAME = bram\r
+ PARAMETER DRIVER_VER = 4.0\r
+ PARAMETER HW_INSTANCE = microblaze_0_local_memory_ilmb_bram_if_cntlr\r
+END\r
+\r
+BEGIN DRIVER\r
+ PARAMETER DRIVER_NAME = mig_7series\r
+ PARAMETER DRIVER_VER = 2.0\r
+ PARAMETER HW_INSTANCE = mig_7series_0\r
+END\r
+\r
+\r
+BEGIN LIBRARY\r
+ PARAMETER LIBRARY_NAME = lwip140\r
+ PARAMETER LIBRARY_VER = 2.3\r
+ PARAMETER PROC_INSTANCE = microblaze_0\r
+END\r
+\r
+\r
diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/Hardware/.project b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/Hardware/.project
new file mode 100644 (file)
index 0000000..f860e24
--- /dev/null
+++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/Hardware/.project
@@ -0,0 +1,68 @@
+<?xml version="1.0" encoding="UTF-8"?>\r
+<projectDescription>\r
+       <name>Hardware</name>\r
+       <comment>Created by SDK v2014.4</comment>\r
+       <projects>\r
+       </projects>\r
+       <buildSpec>\r
+       </buildSpec>\r
+       <natures>\r
+               <nature>com.xilinx.sdk.hw.HwProject</nature>\r
+       </natures>\r
+       <filteredResources>\r
+               <filter>\r
+                       <id>1421760060412</id>\r
+                       <name></name>\r
+                       <type>6</type>\r
+                       <matcher>\r
+                               <id>org.eclipse.ui.ide.multiFilter</id>\r
+                               <arguments>1.0-name-matches-false-false-*.xml</arguments>\r
+                       </matcher>\r
+               </filter>\r
+               <filter>\r
+                       <id>1421760060422</id>\r
+                       <name></name>\r
+                       <type>6</type>\r
+                       <matcher>\r
+                               <id>org.eclipse.ui.ide.multiFilter</id>\r
+                               <arguments>1.0-name-matches-false-false-*.svd</arguments>\r
+                       </matcher>\r
+               </filter>\r
+               <filter>\r
+                       <id>1421760060432</id>\r
+                       <name></name>\r
+                       <type>6</type>\r
+                       <matcher>\r
+                               <id>org.eclipse.ui.ide.multiFilter</id>\r
+                               <arguments>1.0-name-matches-false-false-*.hwh</arguments>\r
+                       </matcher>\r
+               </filter>\r
+               <filter>\r
+                       <id>1421760060432</id>\r
+                       <name></name>\r
+                       <type>6</type>\r
+                       <matcher>\r
+                               <id>org.eclipse.ui.ide.multiFilter</id>\r
+                               <arguments>1.0-name-matches-false-false-*.bit</arguments>\r
+                       </matcher>\r
+               </filter>\r
+               <filter>\r
+                       <id>1421760060442</id>\r
+                       <name></name>\r
+                       <type>6</type>\r
+                       <matcher>\r
+                               <id>org.eclipse.ui.ide.multiFilter</id>\r
+                               <arguments>1.0-name-matches-false-false-*.bmm</arguments>\r
+                       </matcher>\r
+               </filter>\r
+               <filter>\r
+                       <id>1421760060442</id>\r
+                       <name></name>\r
+                       <type>6</type>\r
+                       <matcher>\r
+                               <id>org.eclipse.ui.ide.multiFilter</id>\r
+                               <arguments>1.0-name-matches-false-false-*.mmi</arguments>\r
+                       </matcher>\r
+               </filter>\r
+       </filteredResources>\r
+</projectDescription>\r
diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/Hardware/base_microblaze_design.hwh b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/Hardware/base_microblaze_design.hwh
new file mode 100644 (file)
index 0000000..bf43cd8
--- /dev/null
+++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/Hardware/base_microblaze_design.hwh
@@ -0,0 +1,6575 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<EDKSYSTEM EDWVERSION="1.2" TIMESTAMP="Tue Jan 20 12:53:16 2015" VIVADOVERSION="2014.4">
+
+  <SYSTEMINFO ARCH="kintex7" BOARD="xilinx.com:kc705:part0:1.1" DEVICE="7k325t" NAME="base_microblaze_design_imp" PACKAGE="ffg900" SPEEDGRADE="-2"/>
+
+  <EXTERNALPORTS>
+    <PORT DIR="I" NAME="rs232_uart_rxd" SIGIS="undef"/>
+    <PORT DIR="O" NAME="rs232_uart_txd" SIGIS="undef"/>
+    <PORT DIR="O" LEFT="7" NAME="led_8bits_tri_o" RIGHT="0" SIGIS="undef"/>
+    <PORT DIR="I" NAME="mii_col" SIGIS="undef"/>
+    <PORT DIR="I" NAME="mii_crs" SIGIS="undef"/>
+    <PORT DIR="O" NAME="mii_rst_n" SIGIS="undef"/>
+    <PORT DIR="I" NAME="mii_rx_clk" SIGIS="undef"/>
+    <PORT DIR="I" NAME="mii_rx_dv" SIGIS="undef"/>
+    <PORT DIR="I" NAME="mii_rx_er" SIGIS="undef"/>
+    <PORT DIR="I" LEFT="3" NAME="mii_rxd" RIGHT="0" SIGIS="undef"/>
+    <PORT DIR="I" NAME="mii_tx_clk" SIGIS="undef"/>
+    <PORT DIR="O" NAME="mii_tx_en" SIGIS="undef"/>
+    <PORT DIR="O" LEFT="3" NAME="mii_txd" RIGHT="0" SIGIS="undef"/>
+    <PORT DIR="O" NAME="mdio_mdc_mdc" SIGIS="undef"/>
+    <PORT DIR="I" NAME="mdio_mdc_mdio_i" SIGIS="undef"/>
+    <PORT DIR="O" NAME="mdio_mdc_mdio_o" SIGIS="undef"/>
+    <PORT DIR="O" NAME="mdio_mdc_mdio_t" SIGIS="undef"/>
+    <PORT DIR="IO" LEFT="63" NAME="ddr3_sdram_dq" RIGHT="0" SIGIS="undef"/>
+    <PORT DIR="IO" LEFT="7" NAME="ddr3_sdram_dqs_p" RIGHT="0" SIGIS="undef"/>
+    <PORT DIR="IO" LEFT="7" NAME="ddr3_sdram_dqs_n" RIGHT="0" SIGIS="undef"/>
+    <PORT DIR="O" LEFT="13" NAME="ddr3_sdram_addr" RIGHT="0" SIGIS="undef"/>
+    <PORT DIR="O" LEFT="2" NAME="ddr3_sdram_ba" RIGHT="0" SIGIS="undef"/>
+    <PORT DIR="O" NAME="ddr3_sdram_ras_n" SIGIS="undef"/>
+    <PORT DIR="O" NAME="ddr3_sdram_cas_n" SIGIS="undef"/>
+    <PORT DIR="O" NAME="ddr3_sdram_we_n" SIGIS="undef"/>
+    <PORT DIR="O" NAME="ddr3_sdram_reset_n" SIGIS="undef"/>
+    <PORT DIR="O" LEFT="0" NAME="ddr3_sdram_ck_p" RIGHT="0" SIGIS="undef"/>
+    <PORT DIR="O" LEFT="0" NAME="ddr3_sdram_ck_n" RIGHT="0" SIGIS="undef"/>
+    <PORT DIR="O" LEFT="0" NAME="ddr3_sdram_cke" RIGHT="0" SIGIS="undef"/>
+    <PORT DIR="O" LEFT="0" NAME="ddr3_sdram_cs_n" RIGHT="0" SIGIS="undef"/>
+    <PORT DIR="O" LEFT="7" NAME="ddr3_sdram_dm" RIGHT="0" SIGIS="undef"/>
+    <PORT DIR="O" LEFT="0" NAME="ddr3_sdram_odt" RIGHT="0" SIGIS="undef"/>
+    <PORT DIR="I" NAME="sys_diff_clock_clk_p" SIGIS="undef"/>
+    <PORT DIR="I" NAME="sys_diff_clock_clk_n" SIGIS="undef"/>
+    <PORT DIR="I" NAME="reset" SIGIS="rst" SIGNAME="External_Ports_reset">
+      <CONNECTIONS>
+        <CONNECTION INSTANCE="mig_7series_0" PORT="sys_rst"/>
+      </CONNECTIONS>
+    </PORT>
+  </EXTERNALPORTS>
+
+  <MODULES>
+    <MODULE FULLNAME="/axi_ethernetlite_0" HWVERSION="3.0" INSTANCE="axi_ethernetlite_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="axi_ethernetlite" VLNV="xilinx.com:ip:axi_ethernetlite:3.0">
+      <DOCUMENTS>
+        <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_ethernetlite;v=v3_0;d=pg135-axi-ethernetlite.pdf"/>
+      </DOCUMENTS>
+      <PARAMETERS>
+        <PARAMETER NAME="C_FAMILY" VALUE="kintex7"/>
+        <PARAMETER NAME="C_INSTANCE" VALUE="axi_ethernetlite_inst"/>
+        <PARAMETER NAME="C_S_AXI_ACLK_PERIOD_PS" VALUE="10000"/>
+        <PARAMETER NAME="C_S_AXI_ADDR_WIDTH" VALUE="13"/>
+        <PARAMETER NAME="C_S_AXI_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_S_AXI_ID_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C_S_AXI_PROTOCOL" VALUE="AXI4LITE"/>
+        <PARAMETER NAME="C_INCLUDE_MDIO" VALUE="1"/>
+        <PARAMETER NAME="C_INCLUDE_INTERNAL_LOOPBACK" VALUE="0"/>
+        <PARAMETER NAME="C_INCLUDE_GLOBAL_BUFFERS" VALUE="1"/>
+        <PARAMETER NAME="C_DUPLEX" VALUE="1"/>
+        <PARAMETER NAME="C_TX_PING_PONG" VALUE="1"/>
+        <PARAMETER NAME="C_RX_PING_PONG" VALUE="1"/>
+        <PARAMETER NAME="Component_Name" VALUE="base_microblaze_design_axi_ethernetlite_0_0"/>
+        <PARAMETER NAME="AXI_ACLK_FREQ_MHZ" VALUE="100"/>
+        <PARAMETER NAME="Enable_Constraints" VALUE="1"/>
+        <PARAMETER NAME="USE_BOARD_FLOW" VALUE="true"/>
+        <PARAMETER NAME="MII_BOARD_INTERFACE" VALUE="mii"/>
+        <PARAMETER NAME="MDIO_BOARD_INTERFACE" VALUE="mdio_mdc"/>
+        <PARAMETER NAME="C_USE_INTERNAL" VALUE="0"/>
+        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
+        <PARAMETER NAME="C_BASEADDR" VALUE="0x40E00000"/>
+        <PARAMETER NAME="C_HIGHADDR" VALUE="0x40E0FFFF"/>
+      </PARAMETERS>
+      <PORTS>
+        <PORT CLKFREQUENCY="100000000" DIR="I" NAME="s_axi_aclk" SIGIS="clk" SIGNAME="mig_7series_0_ui_clk">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="mig_7series_0" PORT="ui_clk"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="s_axi_aresetn" SIGIS="rst" SIGNAME="rst_clk_wiz_1_100M_peripheral_aresetn">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="rst_clk_wiz_1_100M" PORT="peripheral_aresetn"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="ip2intc_irpt" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="axi_ethernetlite_0_ip2intc_irpt">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_intc_0" PORT="intr"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="12" NAME="s_axi_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_ethernetlite_0_s_axi_awaddr">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M04_AXI_awaddr"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="s_axi_awvalid" SIGIS="undef" SIGNAME="axi_ethernetlite_0_s_axi_awvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M04_AXI_awvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="s_axi_awready" SIGIS="undef" SIGNAME="axi_ethernetlite_0_s_axi_awready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M04_AXI_awready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="31" NAME="s_axi_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_ethernetlite_0_s_axi_wdata">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M04_AXI_wdata"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="3" NAME="s_axi_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axi_ethernetlite_0_s_axi_wstrb">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M04_AXI_wstrb"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="s_axi_wvalid" SIGIS="undef" SIGNAME="axi_ethernetlite_0_s_axi_wvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M04_AXI_wvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="s_axi_wready" SIGIS="undef" SIGNAME="axi_ethernetlite_0_s_axi_wready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M04_AXI_wready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="1" NAME="s_axi_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_ethernetlite_0_s_axi_bresp">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M04_AXI_bresp"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="s_axi_bvalid" SIGIS="undef" SIGNAME="axi_ethernetlite_0_s_axi_bvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M04_AXI_bvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="s_axi_bready" SIGIS="undef" SIGNAME="axi_ethernetlite_0_s_axi_bready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M04_AXI_bready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="12" NAME="s_axi_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_ethernetlite_0_s_axi_araddr">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M04_AXI_araddr"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="s_axi_arvalid" SIGIS="undef" SIGNAME="axi_ethernetlite_0_s_axi_arvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M04_AXI_arvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="s_axi_arready" SIGIS="undef" SIGNAME="axi_ethernetlite_0_s_axi_arready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M04_AXI_arready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="31" NAME="s_axi_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_ethernetlite_0_s_axi_rdata">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M04_AXI_rdata"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="1" NAME="s_axi_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_ethernetlite_0_s_axi_rresp">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M04_AXI_rresp"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="s_axi_rvalid" SIGIS="undef" SIGNAME="axi_ethernetlite_0_s_axi_rvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M04_AXI_rvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="s_axi_rready" SIGIS="undef" SIGNAME="axi_ethernetlite_0_s_axi_rready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M04_AXI_rready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="phy_tx_clk" SIGIS="undef"/>
+        <PORT DIR="I" NAME="phy_rx_clk" SIGIS="undef"/>
+        <PORT DIR="I" NAME="phy_crs" SIGIS="undef"/>
+        <PORT DIR="I" NAME="phy_dv" SIGIS="undef"/>
+        <PORT DIR="I" LEFT="3" NAME="phy_rx_data" RIGHT="0" SIGIS="undef"/>
+        <PORT DIR="I" NAME="phy_col" SIGIS="undef"/>
+        <PORT DIR="I" NAME="phy_rx_er" SIGIS="undef"/>
+        <PORT DIR="O" NAME="phy_rst_n" SIGIS="undef"/>
+        <PORT DIR="O" NAME="phy_tx_en" SIGIS="undef"/>
+        <PORT DIR="O" LEFT="3" NAME="phy_tx_data" RIGHT="0" SIGIS="undef"/>
+        <PORT DIR="I" NAME="phy_mdio_i" SIGIS="undef"/>
+        <PORT DIR="O" NAME="phy_mdio_o" SIGIS="undef"/>
+        <PORT DIR="O" NAME="phy_mdio_t" SIGIS="undef"/>
+        <PORT DIR="O" NAME="phy_mdc" SIGIS="undef"/>
+      </PORTS>
+      <BUSINTERFACES>
+        <BUSINTERFACE BUSNAME="microblaze_0_axi_periph_M04_AXI" NAME="S_AXI" TYPE="SLAVE">
+          <PORTMAPS>
+            <PORTMAP PHYSICAL="s_axi_araddr"/>
+            <PORTMAP PHYSICAL="s_axi_arready"/>
+            <PORTMAP PHYSICAL="s_axi_arvalid"/>
+            <PORTMAP PHYSICAL="s_axi_awaddr"/>
+            <PORTMAP PHYSICAL="s_axi_awready"/>
+            <PORTMAP PHYSICAL="s_axi_awvalid"/>
+            <PORTMAP PHYSICAL="s_axi_bready"/>
+            <PORTMAP PHYSICAL="s_axi_bresp"/>
+            <PORTMAP PHYSICAL="s_axi_bvalid"/>
+            <PORTMAP PHYSICAL="s_axi_rdata"/>
+            <PORTMAP PHYSICAL="s_axi_rready"/>
+            <PORTMAP PHYSICAL="s_axi_rresp"/>
+            <PORTMAP PHYSICAL="s_axi_rvalid"/>
+            <PORTMAP PHYSICAL="s_axi_wdata"/>
+            <PORTMAP PHYSICAL="s_axi_wready"/>
+            <PORTMAP PHYSICAL="s_axi_wstrb"/>
+            <PORTMAP PHYSICAL="s_axi_wvalid"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="axi_ethernetlite_0_MII" NAME="MII" TYPE="INITIATOR">
+          <PORTMAPS>
+            <PORTMAP PHYSICAL="phy_col"/>
+            <PORTMAP PHYSICAL="phy_crs"/>
+            <PORTMAP PHYSICAL="phy_rst_n"/>
+            <PORTMAP PHYSICAL="phy_rx_clk"/>
+            <PORTMAP PHYSICAL="phy_dv"/>
+            <PORTMAP PHYSICAL="phy_rx_er"/>
+            <PORTMAP PHYSICAL="phy_rx_data"/>
+            <PORTMAP PHYSICAL="phy_tx_clk"/>
+            <PORTMAP PHYSICAL="phy_tx_en"/>
+            <PORTMAP PHYSICAL="phy_tx_data"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="axi_ethernetlite_0_MDIO" NAME="MDIO" TYPE="INITIATOR">
+          <PORTMAPS>
+            <PORTMAP PHYSICAL="phy_mdc"/>
+            <PORTMAP PHYSICAL="phy_mdio_i"/>
+            <PORTMAP PHYSICAL="phy_mdio_o"/>
+            <PORTMAP PHYSICAL="phy_mdio_t"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+      </BUSINTERFACES>
+      <INTERRUPTINFO TYPE="SOURCE">
+        <TARGET INSTANCE="axi_intc_0" INTC_INDEX="0" PRIORITY="2"/>
+      </INTERRUPTINFO>
+    </MODULE>
+    <MODULE FULLNAME="/axi_gpio_0" HWVERSION="2.0" INSTANCE="axi_gpio_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="axi_gpio" VLNV="xilinx.com:ip:axi_gpio:2.0">
+      <DOCUMENTS>
+        <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_gpio;v=v2_0;d=pg144-axi-gpio.pdf"/>
+      </DOCUMENTS>
+      <PARAMETERS>
+        <PARAMETER NAME="C_FAMILY" VALUE="kintex7"/>
+        <PARAMETER NAME="C_S_AXI_ADDR_WIDTH" VALUE="9"/>
+        <PARAMETER NAME="C_S_AXI_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_GPIO_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="C_GPIO2_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_ALL_INPUTS" VALUE="0"/>
+        <PARAMETER NAME="C_ALL_INPUTS_2" VALUE="0"/>
+        <PARAMETER NAME="C_ALL_OUTPUTS" VALUE="1"/>
+        <PARAMETER NAME="C_ALL_OUTPUTS_2" VALUE="0"/>
+        <PARAMETER NAME="C_INTERRUPT_PRESENT" VALUE="0"/>
+        <PARAMETER NAME="C_DOUT_DEFAULT" VALUE="0x00000000"/>
+        <PARAMETER NAME="C_TRI_DEFAULT" VALUE="0xFFFFFFFF"/>
+        <PARAMETER NAME="C_IS_DUAL" VALUE="0"/>
+        <PARAMETER NAME="C_DOUT_DEFAULT_2" VALUE="0x00000000"/>
+        <PARAMETER NAME="C_TRI_DEFAULT_2" VALUE="0xFFFFFFFF"/>
+        <PARAMETER NAME="Component_Name" VALUE="base_microblaze_design_axi_gpio_0_0"/>
+        <PARAMETER NAME="USE_BOARD_FLOW" VALUE="true"/>
+        <PARAMETER NAME="GPIO_BOARD_INTERFACE" VALUE="led_8bits"/>
+        <PARAMETER NAME="GPIO2_BOARD_INTERFACE" VALUE="Custom"/>
+        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
+        <PARAMETER NAME="C_BASEADDR" VALUE="0x40000000"/>
+        <PARAMETER NAME="C_HIGHADDR" VALUE="0x4000FFFF"/>
+      </PARAMETERS>
+      <PORTS>
+        <PORT CLKFREQUENCY="100000000" DIR="I" NAME="s_axi_aclk" SIGIS="clk" SIGNAME="mig_7series_0_ui_clk">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="mig_7series_0" PORT="ui_clk"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="s_axi_aresetn" SIGIS="rst" SIGNAME="rst_clk_wiz_1_100M_peripheral_aresetn">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="rst_clk_wiz_1_100M" PORT="peripheral_aresetn"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="8" NAME="s_axi_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_awaddr">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M01_AXI_awaddr"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="s_axi_awvalid" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_awvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M01_AXI_awvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="s_axi_awready" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_awready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M01_AXI_awready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="31" NAME="s_axi_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_wdata">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M01_AXI_wdata"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="3" NAME="s_axi_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_wstrb">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M01_AXI_wstrb"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="s_axi_wvalid" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_wvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M01_AXI_wvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="s_axi_wready" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_wready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M01_AXI_wready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="1" NAME="s_axi_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_bresp">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M01_AXI_bresp"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="s_axi_bvalid" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_bvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M01_AXI_bvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="s_axi_bready" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_bready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M01_AXI_bready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="8" NAME="s_axi_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_araddr">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M01_AXI_araddr"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="s_axi_arvalid" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_arvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M01_AXI_arvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="s_axi_arready" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_arready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M01_AXI_arready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="31" NAME="s_axi_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_rdata">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M01_AXI_rdata"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="1" NAME="s_axi_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_rresp">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M01_AXI_rresp"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="s_axi_rvalid" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_rvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M01_AXI_rvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="s_axi_rready" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_rready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M01_AXI_rready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="7" NAME="gpio_io_o" RIGHT="0" SIGIS="undef"/>
+      </PORTS>
+      <BUSINTERFACES>
+        <BUSINTERFACE BUSNAME="microblaze_0_axi_periph_M01_AXI" NAME="S_AXI" TYPE="SLAVE">
+          <PORTMAPS>
+            <PORTMAP PHYSICAL="s_axi_araddr"/>
+            <PORTMAP PHYSICAL="s_axi_arready"/>
+            <PORTMAP PHYSICAL="s_axi_arvalid"/>
+            <PORTMAP PHYSICAL="s_axi_awaddr"/>
+            <PORTMAP PHYSICAL="s_axi_awready"/>
+            <PORTMAP PHYSICAL="s_axi_awvalid"/>
+            <PORTMAP PHYSICAL="s_axi_bready"/>
+            <PORTMAP PHYSICAL="s_axi_bresp"/>
+            <PORTMAP PHYSICAL="s_axi_bvalid"/>
+            <PORTMAP PHYSICAL="s_axi_rdata"/>
+            <PORTMAP PHYSICAL="s_axi_rready"/>
+            <PORTMAP PHYSICAL="s_axi_rresp"/>
+            <PORTMAP PHYSICAL="s_axi_rvalid"/>
+            <PORTMAP PHYSICAL="s_axi_wdata"/>
+            <PORTMAP PHYSICAL="s_axi_wready"/>
+            <PORTMAP PHYSICAL="s_axi_wstrb"/>
+            <PORTMAP PHYSICAL="s_axi_wvalid"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="axi_gpio_0_GPIO" NAME="GPIO" TYPE="INITIATOR">
+          <PORTMAPS>
+            <PORTMAP PHYSICAL="gpio_io_o"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+      </BUSINTERFACES>
+    </MODULE>
+    <MODULE FULLNAME="/axi_intc_0" HWVERSION="4.1" INSTANCE="axi_intc_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="INTERRUPT_CNTLR" MODTYPE="axi_intc" VLNV="xilinx.com:ip:axi_intc:4.1">
+      <DOCUMENTS>
+        <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_intc;v=v4_1;d=pg099-axi-intc.pdf"/>
+      </DOCUMENTS>
+      <PARAMETERS>
+        <PARAMETER NAME="C_FAMILY" VALUE="kintex7"/>
+        <PARAMETER NAME="C_INSTANCE" VALUE="axi_intc_inst"/>
+        <PARAMETER NAME="C_S_AXI_ADDR_WIDTH" VALUE="9"/>
+        <PARAMETER NAME="C_S_AXI_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_NUM_INTR_INPUTS" VALUE="3"/>
+        <PARAMETER NAME="C_NUM_SW_INTR" VALUE="0"/>
+        <PARAMETER NAME="C_KIND_OF_INTR" VALUE="0xfffffffe"/>
+        <PARAMETER NAME="C_KIND_OF_EDGE" VALUE="0xffffffff"/>
+        <PARAMETER NAME="C_KIND_OF_LVL" VALUE="0xffffffff"/>
+        <PARAMETER NAME="C_ASYNC_INTR" VALUE="0xFFFFFFF8"/>
+        <PARAMETER NAME="C_NUM_SYNC_FF" VALUE="2"/>
+        <PARAMETER NAME="C_IVAR_RESET_VALUE" VALUE="0x00000010"/>
+        <PARAMETER NAME="C_ENABLE_ASYNC" VALUE="0"/>
+        <PARAMETER NAME="C_HAS_IPR" VALUE="1"/>
+        <PARAMETER NAME="C_HAS_SIE" VALUE="1"/>
+        <PARAMETER NAME="C_HAS_CIE" VALUE="1"/>
+        <PARAMETER NAME="C_HAS_IVR" VALUE="1"/>
+        <PARAMETER NAME="C_HAS_ILR" VALUE="0"/>
+        <PARAMETER NAME="C_IRQ_IS_LEVEL" VALUE="1"/>
+        <PARAMETER NAME="C_IRQ_ACTIVE" VALUE="0x1"/>
+        <PARAMETER NAME="C_DISABLE_SYNCHRONIZERS" VALUE="1"/>
+        <PARAMETER NAME="C_MB_CLK_NOT_CONNECTED" VALUE="1"/>
+        <PARAMETER NAME="C_HAS_FAST" VALUE="0"/>
+        <PARAMETER NAME="C_EN_CASCADE_MODE" VALUE="0"/>
+        <PARAMETER NAME="C_CASCADE_MASTER" VALUE="0"/>
+        <PARAMETER NAME="Component_Name" VALUE="base_microblaze_design_axi_intc_0_0"/>
+        <PARAMETER NAME="Sense_of_IRQ_Level_Type" VALUE="Active_High"/>
+        <PARAMETER NAME="Sense_of_IRQ_Edge_Type" VALUE="Rising"/>
+        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
+        <PARAMETER NAME="EDK_SPECIAL" VALUE="INTR_CTRL"/>
+        <PARAMETER NAME="C_BASEADDR" VALUE="0x41200000"/>
+        <PARAMETER NAME="C_HIGHADDR" VALUE="0x4120FFFF"/>
+      </PARAMETERS>
+      <PORTS>
+        <PORT CLKFREQUENCY="100000000" DIR="I" NAME="s_axi_aclk" SIGIS="clk" SIGNAME="mig_7series_0_ui_clk">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="mig_7series_0" PORT="ui_clk"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="s_axi_aresetn" SIGIS="rst" SIGNAME="rst_clk_wiz_1_100M_peripheral_aresetn">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="rst_clk_wiz_1_100M" PORT="peripheral_aresetn"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="8" NAME="s_axi_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_awaddr">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M03_AXI_awaddr"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="s_axi_awvalid" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_awvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M03_AXI_awvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="s_axi_awready" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_awready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M03_AXI_awready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="31" NAME="s_axi_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_wdata">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M03_AXI_wdata"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="3" NAME="s_axi_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_wstrb">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M03_AXI_wstrb"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="s_axi_wvalid" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_wvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M03_AXI_wvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="s_axi_wready" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_wready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M03_AXI_wready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="1" NAME="s_axi_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_bresp">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M03_AXI_bresp"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="s_axi_bvalid" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_bvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M03_AXI_bvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="s_axi_bready" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_bready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M03_AXI_bready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="8" NAME="s_axi_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_araddr">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M03_AXI_araddr"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="s_axi_arvalid" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_arvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M03_AXI_arvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="s_axi_arready" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_arready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M03_AXI_arready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="31" NAME="s_axi_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_rdata">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M03_AXI_rdata"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="1" NAME="s_axi_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_rresp">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M03_AXI_rresp"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="s_axi_rvalid" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_rvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M03_AXI_rvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="s_axi_rready" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_rready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M03_AXI_rready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="2" NAME="intr" RIGHT="0" SENSITIVITY="EDGE_RISING:EDGE_RISING:LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="axi_ethernetlite_0_ip2intc_irpt &amp; axi_uartlite_0_interrupt &amp; axi_timer_0_interrupt">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_ethernetlite_0" PORT="ip2intc_irpt"/>
+            <CONNECTION INSTANCE="axi_uartlite_0" PORT="interrupt"/>
+            <CONNECTION INSTANCE="axi_timer_0" PORT="interrupt"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="irq" SIGIS="undef" SIGNAME="axi_intc_0_irq">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="Interrupt"/>
+          </CONNECTIONS>
+        </PORT>
+      </PORTS>
+      <BUSINTERFACES>
+        <BUSINTERFACE BUSNAME="microblaze_0_axi_periph_M03_AXI" NAME="s_axi" TYPE="SLAVE">
+          <PORTMAPS>
+            <PORTMAP PHYSICAL="s_axi_araddr"/>
+            <PORTMAP PHYSICAL="s_axi_arready"/>
+            <PORTMAP PHYSICAL="s_axi_arvalid"/>
+            <PORTMAP PHYSICAL="s_axi_awaddr"/>
+            <PORTMAP PHYSICAL="s_axi_awready"/>
+            <PORTMAP PHYSICAL="s_axi_awvalid"/>
+            <PORTMAP PHYSICAL="s_axi_bready"/>
+            <PORTMAP PHYSICAL="s_axi_bresp"/>
+            <PORTMAP PHYSICAL="s_axi_bvalid"/>
+            <PORTMAP PHYSICAL="s_axi_rdata"/>
+            <PORTMAP PHYSICAL="s_axi_rready"/>
+            <PORTMAP PHYSICAL="s_axi_rresp"/>
+            <PORTMAP PHYSICAL="s_axi_rvalid"/>
+            <PORTMAP PHYSICAL="s_axi_wdata"/>
+            <PORTMAP PHYSICAL="s_axi_wready"/>
+            <PORTMAP PHYSICAL="s_axi_wstrb"/>
+            <PORTMAP PHYSICAL="s_axi_wvalid"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="axi_intc_0_interrupt" NAME="interrupt" TYPE="INITIATOR">
+          <PORTMAPS>
+            <PORTMAP PHYSICAL="irq"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+      </BUSINTERFACES>
+      <INTERRUPTINFO INTC_INDEX="0" TYPE="CONTROLLER">
+        <SOURCE INSTANCE="axi_timer_0" PRIORITY="0" SIGNAME="axi_timer_0_interrupt"/>
+        <SOURCE INSTANCE="axi_uartlite_0" PRIORITY="1" SIGNAME="axi_uartlite_0_interrupt"/>
+        <SOURCE INSTANCE="axi_ethernetlite_0" PRIORITY="2" SIGNAME="axi_ethernetlite_0_ip2intc_irpt"/>
+      </INTERRUPTINFO>
+    </MODULE>
+    <MODULE FULLNAME="/axi_mem_intercon" HWVERSION="2.1" INSTANCE="axi_mem_intercon" IPTYPE="BUS" IS_ENABLE="1" MODCLASS="BUS" MODTYPE="axi_interconnect" VLNV="xilinx.com:ip:axi_interconnect:2.1">
+      <DOCUMENTS>
+        <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_interconnect;v=v2_1;d=pg059-axi-interconnect.pdf"/>
+      </DOCUMENTS>
+      <PARAMETERS>
+        <PARAMETER NAME="NUM_SI" VALUE="2"/>
+        <PARAMETER NAME="NUM_MI" VALUE="1"/>
+        <PARAMETER NAME="STRATEGY" VALUE="0"/>
+        <PARAMETER NAME="ENABLE_ADVANCED_OPTIONS" VALUE="0"/>
+        <PARAMETER NAME="ENABLE_PROTOCOL_CHECKERS" VALUE="0"/>
+        <PARAMETER NAME="XBAR_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="PCHK_WAITS" VALUE="0"/>
+        <PARAMETER NAME="PCHK_MAX_RD_BURSTS" VALUE="2"/>
+        <PARAMETER NAME="PCHK_MAX_WR_BURSTS" VALUE="2"/>
+        <PARAMETER NAME="SYNCHRONIZATION_STAGES" VALUE="2"/>
+        <PARAMETER NAME="M00_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M01_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M02_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M03_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M04_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M05_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M06_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M07_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M08_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M09_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M10_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M11_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M12_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M13_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M14_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M15_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M16_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M17_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M18_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M19_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M20_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M21_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M22_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M23_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M24_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M25_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M26_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M27_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M28_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M29_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M30_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M31_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M32_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M33_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M34_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M35_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M36_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M37_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M38_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M39_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M40_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M41_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M42_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M43_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M44_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M45_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M46_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M47_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M48_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M49_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M50_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M51_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M52_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M53_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M54_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M55_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M56_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M57_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M58_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M59_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M60_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M61_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M62_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M63_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M00_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M01_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M02_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M03_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M04_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M05_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M06_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M07_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M08_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M09_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M10_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M11_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M12_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M13_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M14_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M15_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M16_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M17_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M18_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M19_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M20_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M21_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M22_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M23_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M24_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M25_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M26_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M27_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M28_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M29_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M30_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M31_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M32_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M33_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M34_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M35_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M36_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M37_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M38_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M39_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M40_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M41_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M42_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M43_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M44_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M45_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M46_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M47_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M48_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M49_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M50_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M51_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M52_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M53_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M54_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M55_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M56_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M57_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M58_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M59_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M60_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M61_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M62_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M63_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="S00_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="S01_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="S02_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="S03_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="S04_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="S05_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="S06_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="S07_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="S08_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="S09_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="S10_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="S11_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="S12_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="S13_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="S14_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="S15_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="S00_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="S01_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="S02_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="S03_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="S04_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="S05_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="S06_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="S07_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="S08_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="S09_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="S10_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="S11_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="S12_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="S13_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="S14_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="S15_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M00_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M01_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M02_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M03_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M04_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M05_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M06_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M07_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M08_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M09_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M10_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M11_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M12_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M13_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M14_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M15_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M16_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M17_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M18_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M19_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M20_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M21_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M22_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M23_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M24_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M25_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M26_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M27_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M28_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M29_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M30_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M31_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M32_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M33_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M34_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M35_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M36_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M37_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M38_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M39_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M40_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M41_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M42_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M43_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M44_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M45_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M46_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M47_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M48_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M49_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M50_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M51_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M52_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M53_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M54_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M55_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M56_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M57_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M58_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M59_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M60_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M61_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M62_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M63_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M00_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M01_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M02_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M03_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M04_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M05_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M06_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M07_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M08_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M09_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M10_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M11_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M12_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M13_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M14_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M15_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M16_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M17_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M18_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M19_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M20_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M21_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M22_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M23_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M24_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M25_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M26_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M27_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M28_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M29_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M30_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M31_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M32_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M33_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M34_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M35_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M36_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M37_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M38_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M39_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M40_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M41_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M42_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M43_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M44_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M45_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M46_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M47_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M48_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M49_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M50_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M51_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M52_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M53_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M54_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M55_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M56_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M57_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M58_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M59_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M60_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M61_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M62_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M63_SECURE" VALUE="0"/>
+        <PARAMETER NAME="Component_Name" VALUE="base_microblaze_design_axi_mem_intercon_0"/>
+        <PARAMETER NAME="EDK_IPTYPE" VALUE="BUS"/>
+      </PARAMETERS>
+      <PORTS>
+        <PORT DIR="I" NAME="ACLK" SIGIS="clk" SIGNAME="mig_7series_0_ui_clk">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="mig_7series_0" PORT="ui_clk"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="0" NAME="ARESETN" RIGHT="0" SIGIS="rst" SIGNAME="rst_clk_wiz_1_100M_interconnect_aresetn">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="rst_clk_wiz_1_100M" PORT="interconnect_aresetn"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="S00_ACLK" SIGIS="clk" SIGNAME="mig_7series_0_ui_clk">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="mig_7series_0" PORT="ui_clk"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="0" NAME="S00_ARESETN" RIGHT="0" SIGIS="rst" SIGNAME="rst_clk_wiz_1_100M_peripheral_aresetn">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="rst_clk_wiz_1_100M" PORT="peripheral_aresetn"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M00_ACLK" SIGIS="clk" SIGNAME="mig_7series_0_ui_clk">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="mig_7series_0" PORT="ui_clk"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="0" NAME="M00_ARESETN" RIGHT="0" SIGIS="rst" SIGNAME="rst_clk_wiz_1_100M_peripheral_aresetn">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="rst_clk_wiz_1_100M" PORT="peripheral_aresetn"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="S01_ACLK" SIGIS="clk" SIGNAME="mig_7series_0_ui_clk">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="mig_7series_0" PORT="ui_clk"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="0" NAME="S01_ARESETN" RIGHT="0" SIGIS="rst" SIGNAME="rst_clk_wiz_1_100M_peripheral_aresetn">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="rst_clk_wiz_1_100M" PORT="peripheral_aresetn"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="31" NAME="S00_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_araddr">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DC_ARADDR"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="1" NAME="S00_AXI_arburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_arburst">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DC_ARBURST"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="3" NAME="S00_AXI_arcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_arcache">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DC_ARCACHE"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="0" NAME="S00_AXI_arid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_arid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DC_ARID"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="7" NAME="S00_AXI_arlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_arlen">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DC_ARLEN"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="0" NAME="S00_AXI_arlock" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_arlock">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DC_ARLOCK"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="2" NAME="S00_AXI_arprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_arprot">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DC_ARPROT"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="3" NAME="S00_AXI_arqos" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_arqos">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DC_ARQOS"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="0" NAME="S00_AXI_arready" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_arready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DC_ARREADY"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="2" NAME="S00_AXI_arsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_arsize">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DC_ARSIZE"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="0" NAME="S00_AXI_arvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_arvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DC_ARVALID"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="31" NAME="S00_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_awaddr">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DC_AWADDR"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="1" NAME="S00_AXI_awburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_awburst">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DC_AWBURST"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="3" NAME="S00_AXI_awcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_awcache">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DC_AWCACHE"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="0" NAME="S00_AXI_awid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_awid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DC_AWID"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="7" NAME="S00_AXI_awlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_awlen">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DC_AWLEN"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="0" NAME="S00_AXI_awlock" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_awlock">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DC_AWLOCK"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="2" NAME="S00_AXI_awprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_awprot">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DC_AWPROT"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="3" NAME="S00_AXI_awqos" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_awqos">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DC_AWQOS"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="0" NAME="S00_AXI_awready" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_awready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DC_AWREADY"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="2" NAME="S00_AXI_awsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_awsize">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DC_AWSIZE"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="0" NAME="S00_AXI_awvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_awvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DC_AWVALID"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="0" NAME="S00_AXI_bid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_bid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DC_BID"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="0" NAME="S00_AXI_bready" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_bready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DC_BREADY"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="1" NAME="S00_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_bresp">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DC_BRESP"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="0" NAME="S00_AXI_bvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_bvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DC_BVALID"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="31" NAME="S00_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_rdata">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DC_RDATA"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="0" NAME="S00_AXI_rid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_rid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DC_RID"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="0" NAME="S00_AXI_rlast" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_rlast">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DC_RLAST"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="0" NAME="S00_AXI_rready" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_rready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DC_RREADY"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="1" NAME="S00_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_rresp">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DC_RRESP"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="0" NAME="S00_AXI_rvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_rvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DC_RVALID"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="31" NAME="S00_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_wdata">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DC_WDATA"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="0" NAME="S00_AXI_wlast" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_wlast">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DC_WLAST"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="0" NAME="S00_AXI_wready" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_wready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DC_WREADY"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="3" NAME="S00_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_wstrb">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DC_WSTRB"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="0" NAME="S00_AXI_wvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_wvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DC_WVALID"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="0" NAME="M00_AXI_awid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="mig_7series_0" PORT="s_axi_awid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="31" NAME="M00_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awaddr">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="mig_7series_0" PORT="s_axi_awaddr"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="7" NAME="M00_AXI_awlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awlen">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="mig_7series_0" PORT="s_axi_awlen"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="2" NAME="M00_AXI_awsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awsize">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="mig_7series_0" PORT="s_axi_awsize"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="1" NAME="M00_AXI_awburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awburst">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="mig_7series_0" PORT="s_axi_awburst"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="0" NAME="M00_AXI_awlock" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awlock">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="mig_7series_0" PORT="s_axi_awlock"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="3" NAME="M00_AXI_awcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awcache">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="mig_7series_0" PORT="s_axi_awcache"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="2" NAME="M00_AXI_awprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awprot">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="mig_7series_0" PORT="s_axi_awprot"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="3" NAME="M00_AXI_awqos" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awqos">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="mig_7series_0" PORT="s_axi_awqos"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="0" NAME="M00_AXI_awvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="mig_7series_0" PORT="s_axi_awvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="0" NAME="M00_AXI_awready" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="mig_7series_0" PORT="s_axi_awready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="31" NAME="M00_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_wdata">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="mig_7series_0" PORT="s_axi_wdata"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="3" NAME="M00_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_wstrb">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="mig_7series_0" PORT="s_axi_wstrb"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="0" NAME="M00_AXI_wlast" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_wlast">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="mig_7series_0" PORT="s_axi_wlast"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="0" NAME="M00_AXI_wvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_wvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="mig_7series_0" PORT="s_axi_wvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="0" NAME="M00_AXI_wready" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_wready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="mig_7series_0" PORT="s_axi_wready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="0" NAME="M00_AXI_bready" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_bready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="mig_7series_0" PORT="s_axi_bready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="0" NAME="M00_AXI_bid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_bid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="mig_7series_0" PORT="s_axi_bid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="1" NAME="M00_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_bresp">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="mig_7series_0" PORT="s_axi_bresp"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="0" NAME="M00_AXI_bvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_bvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="mig_7series_0" PORT="s_axi_bvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="0" NAME="M00_AXI_arid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="mig_7series_0" PORT="s_axi_arid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="31" NAME="M00_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_araddr">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="mig_7series_0" PORT="s_axi_araddr"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="7" NAME="M00_AXI_arlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arlen">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="mig_7series_0" PORT="s_axi_arlen"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="2" NAME="M00_AXI_arsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arsize">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="mig_7series_0" PORT="s_axi_arsize"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="1" NAME="M00_AXI_arburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arburst">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="mig_7series_0" PORT="s_axi_arburst"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="0" NAME="M00_AXI_arlock" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arlock">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="mig_7series_0" PORT="s_axi_arlock"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="3" NAME="M00_AXI_arcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arcache">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="mig_7series_0" PORT="s_axi_arcache"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="2" NAME="M00_AXI_arprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arprot">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="mig_7series_0" PORT="s_axi_arprot"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="3" NAME="M00_AXI_arqos" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arqos">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="mig_7series_0" PORT="s_axi_arqos"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="0" NAME="M00_AXI_arvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="mig_7series_0" PORT="s_axi_arvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="0" NAME="M00_AXI_arready" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="mig_7series_0" PORT="s_axi_arready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="0" NAME="M00_AXI_rready" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_rready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="mig_7series_0" PORT="s_axi_rready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="0" NAME="M00_AXI_rid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_rid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="mig_7series_0" PORT="s_axi_rid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="31" NAME="M00_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_rdata">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="mig_7series_0" PORT="s_axi_rdata"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="1" NAME="M00_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_rresp">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="mig_7series_0" PORT="s_axi_rresp"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="0" NAME="M00_AXI_rlast" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_rlast">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="mig_7series_0" PORT="s_axi_rlast"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="0" NAME="M00_AXI_rvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_rvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="mig_7series_0" PORT="s_axi_rvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="31" NAME="S01_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_araddr">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_IC_ARADDR"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="1" NAME="S01_AXI_arburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_arburst">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_IC_ARBURST"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="3" NAME="S01_AXI_arcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_arcache">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_IC_ARCACHE"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="0" NAME="S01_AXI_arid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_arid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_IC_ARID"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="7" NAME="S01_AXI_arlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_arlen">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_IC_ARLEN"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="0" NAME="S01_AXI_arlock" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_arlock">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_IC_ARLOCK"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="2" NAME="S01_AXI_arprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_arprot">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_IC_ARPROT"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="3" NAME="S01_AXI_arqos" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_arqos">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_IC_ARQOS"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="0" NAME="S01_AXI_arready" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_arready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_IC_ARREADY"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="2" NAME="S01_AXI_arsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_arsize">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_IC_ARSIZE"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="0" NAME="S01_AXI_arvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_arvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_IC_ARVALID"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="31" NAME="S01_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_awaddr">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_IC_AWADDR"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="1" NAME="S01_AXI_awburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_awburst">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_IC_AWBURST"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="3" NAME="S01_AXI_awcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_awcache">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_IC_AWCACHE"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="0" NAME="S01_AXI_awid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_awid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_IC_AWID"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="7" NAME="S01_AXI_awlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_awlen">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_IC_AWLEN"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="0" NAME="S01_AXI_awlock" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_awlock">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_IC_AWLOCK"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="2" NAME="S01_AXI_awprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_awprot">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_IC_AWPROT"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="3" NAME="S01_AXI_awqos" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_awqos">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_IC_AWQOS"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="0" NAME="S01_AXI_awready" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_awready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_IC_AWREADY"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="2" NAME="S01_AXI_awsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_awsize">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_IC_AWSIZE"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="0" NAME="S01_AXI_awvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_awvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_IC_AWVALID"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="0" NAME="S01_AXI_bid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_bid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_IC_BID"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="0" NAME="S01_AXI_bready" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_bready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_IC_BREADY"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="1" NAME="S01_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_bresp">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_IC_BRESP"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="0" NAME="S01_AXI_bvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_bvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_IC_BVALID"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="31" NAME="S01_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_rdata">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_IC_RDATA"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="0" NAME="S01_AXI_rid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_rid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_IC_RID"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="0" NAME="S01_AXI_rlast" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_rlast">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_IC_RLAST"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="0" NAME="S01_AXI_rready" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_rready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_IC_RREADY"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="1" NAME="S01_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_rresp">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_IC_RRESP"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="0" NAME="S01_AXI_rvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_rvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_IC_RVALID"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="31" NAME="S01_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_wdata">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_IC_WDATA"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="0" NAME="S01_AXI_wlast" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_wlast">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_IC_WLAST"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="0" NAME="S01_AXI_wready" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_wready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_IC_WREADY"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="3" NAME="S01_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_wstrb">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_IC_WSTRB"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="0" NAME="S01_AXI_wvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_wvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_IC_WVALID"/>
+          </CONNECTIONS>
+        </PORT>
+      </PORTS>
+      <BUSINTERFACES>
+        <BUSINTERFACE BUSNAME="microblaze_0_M_AXI_DC" NAME="S00_AXI" TYPE="SLAVE">
+          <PORTMAPS>
+            <PORTMAP PHYSICAL="S00_AXI_araddr"/>
+            <PORTMAP PHYSICAL="S00_AXI_arburst"/>
+            <PORTMAP PHYSICAL="S00_AXI_arcache"/>
+            <PORTMAP PHYSICAL="S00_AXI_arid"/>
+            <PORTMAP PHYSICAL="S00_AXI_arlen"/>
+            <PORTMAP PHYSICAL="S00_AXI_arlock"/>
+            <PORTMAP PHYSICAL="S00_AXI_arprot"/>
+            <PORTMAP PHYSICAL="S00_AXI_arqos"/>
+            <PORTMAP PHYSICAL="S00_AXI_arready"/>
+            <PORTMAP PHYSICAL="S00_AXI_arsize"/>
+            <PORTMAP PHYSICAL="S00_AXI_arvalid"/>
+            <PORTMAP PHYSICAL="S00_AXI_awaddr"/>
+            <PORTMAP PHYSICAL="S00_AXI_awburst"/>
+            <PORTMAP PHYSICAL="S00_AXI_awcache"/>
+            <PORTMAP PHYSICAL="S00_AXI_awid"/>
+            <PORTMAP PHYSICAL="S00_AXI_awlen"/>
+            <PORTMAP PHYSICAL="S00_AXI_awlock"/>
+            <PORTMAP PHYSICAL="S00_AXI_awprot"/>
+            <PORTMAP PHYSICAL="S00_AXI_awqos"/>
+            <PORTMAP PHYSICAL="S00_AXI_awready"/>
+            <PORTMAP PHYSICAL="S00_AXI_awsize"/>
+            <PORTMAP PHYSICAL="S00_AXI_awvalid"/>
+            <PORTMAP PHYSICAL="S00_AXI_bid"/>
+            <PORTMAP PHYSICAL="S00_AXI_bready"/>
+            <PORTMAP PHYSICAL="S00_AXI_bresp"/>
+            <PORTMAP PHYSICAL="S00_AXI_bvalid"/>
+            <PORTMAP PHYSICAL="S00_AXI_rdata"/>
+            <PORTMAP PHYSICAL="S00_AXI_rid"/>
+            <PORTMAP PHYSICAL="S00_AXI_rlast"/>
+            <PORTMAP PHYSICAL="S00_AXI_rready"/>
+            <PORTMAP PHYSICAL="S00_AXI_rresp"/>
+            <PORTMAP PHYSICAL="S00_AXI_rvalid"/>
+            <PORTMAP PHYSICAL="S00_AXI_wdata"/>
+            <PORTMAP PHYSICAL="S00_AXI_wlast"/>
+            <PORTMAP PHYSICAL="S00_AXI_wready"/>
+            <PORTMAP PHYSICAL="S00_AXI_wstrb"/>
+            <PORTMAP PHYSICAL="S00_AXI_wvalid"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="axi_mem_intercon_M00_AXI" NAME="M00_AXI" TYPE="MASTER">
+          <PORTMAPS>
+            <PORTMAP PHYSICAL="M00_AXI_awid"/>
+            <PORTMAP PHYSICAL="M00_AXI_awaddr"/>
+            <PORTMAP PHYSICAL="M00_AXI_awlen"/>
+            <PORTMAP PHYSICAL="M00_AXI_awsize"/>
+            <PORTMAP PHYSICAL="M00_AXI_awburst"/>
+            <PORTMAP PHYSICAL="M00_AXI_awlock"/>
+            <PORTMAP PHYSICAL="M00_AXI_awcache"/>
+            <PORTMAP PHYSICAL="M00_AXI_awprot"/>
+            <PORTMAP PHYSICAL="M00_AXI_awqos"/>
+            <PORTMAP PHYSICAL="M00_AXI_awvalid"/>
+            <PORTMAP PHYSICAL="M00_AXI_awready"/>
+            <PORTMAP PHYSICAL="M00_AXI_wdata"/>
+            <PORTMAP PHYSICAL="M00_AXI_wstrb"/>
+            <PORTMAP PHYSICAL="M00_AXI_wlast"/>
+            <PORTMAP PHYSICAL="M00_AXI_wvalid"/>
+            <PORTMAP PHYSICAL="M00_AXI_wready"/>
+            <PORTMAP PHYSICAL="M00_AXI_bready"/>
+            <PORTMAP PHYSICAL="M00_AXI_bid"/>
+            <PORTMAP PHYSICAL="M00_AXI_bresp"/>
+            <PORTMAP PHYSICAL="M00_AXI_bvalid"/>
+            <PORTMAP PHYSICAL="M00_AXI_arid"/>
+            <PORTMAP PHYSICAL="M00_AXI_araddr"/>
+            <PORTMAP PHYSICAL="M00_AXI_arlen"/>
+            <PORTMAP PHYSICAL="M00_AXI_arsize"/>
+            <PORTMAP PHYSICAL="M00_AXI_arburst"/>
+            <PORTMAP PHYSICAL="M00_AXI_arlock"/>
+            <PORTMAP PHYSICAL="M00_AXI_arcache"/>
+            <PORTMAP PHYSICAL="M00_AXI_arprot"/>
+            <PORTMAP PHYSICAL="M00_AXI_arqos"/>
+            <PORTMAP PHYSICAL="M00_AXI_arvalid"/>
+            <PORTMAP PHYSICAL="M00_AXI_arready"/>
+            <PORTMAP PHYSICAL="M00_AXI_rready"/>
+            <PORTMAP PHYSICAL="M00_AXI_rid"/>
+            <PORTMAP PHYSICAL="M00_AXI_rdata"/>
+            <PORTMAP PHYSICAL="M00_AXI_rresp"/>
+            <PORTMAP PHYSICAL="M00_AXI_rlast"/>
+            <PORTMAP PHYSICAL="M00_AXI_rvalid"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="microblaze_0_M_AXI_IC" NAME="S01_AXI" TYPE="SLAVE">
+          <PORTMAPS>
+            <PORTMAP PHYSICAL="S01_AXI_araddr"/>
+            <PORTMAP PHYSICAL="S01_AXI_arburst"/>
+            <PORTMAP PHYSICAL="S01_AXI_arcache"/>
+            <PORTMAP PHYSICAL="S01_AXI_arid"/>
+            <PORTMAP PHYSICAL="S01_AXI_arlen"/>
+            <PORTMAP PHYSICAL="S01_AXI_arlock"/>
+            <PORTMAP PHYSICAL="S01_AXI_arprot"/>
+            <PORTMAP PHYSICAL="S01_AXI_arqos"/>
+            <PORTMAP PHYSICAL="S01_AXI_arready"/>
+            <PORTMAP PHYSICAL="S01_AXI_arsize"/>
+            <PORTMAP PHYSICAL="S01_AXI_arvalid"/>
+            <PORTMAP PHYSICAL="S01_AXI_awaddr"/>
+            <PORTMAP PHYSICAL="S01_AXI_awburst"/>
+            <PORTMAP PHYSICAL="S01_AXI_awcache"/>
+            <PORTMAP PHYSICAL="S01_AXI_awid"/>
+            <PORTMAP PHYSICAL="S01_AXI_awlen"/>
+            <PORTMAP PHYSICAL="S01_AXI_awlock"/>
+            <PORTMAP PHYSICAL="S01_AXI_awprot"/>
+            <PORTMAP PHYSICAL="S01_AXI_awqos"/>
+            <PORTMAP PHYSICAL="S01_AXI_awready"/>
+            <PORTMAP PHYSICAL="S01_AXI_awsize"/>
+            <PORTMAP PHYSICAL="S01_AXI_awvalid"/>
+            <PORTMAP PHYSICAL="S01_AXI_bid"/>
+            <PORTMAP PHYSICAL="S01_AXI_bready"/>
+            <PORTMAP PHYSICAL="S01_AXI_bresp"/>
+            <PORTMAP PHYSICAL="S01_AXI_bvalid"/>
+            <PORTMAP PHYSICAL="S01_AXI_rdata"/>
+            <PORTMAP PHYSICAL="S01_AXI_rid"/>
+            <PORTMAP PHYSICAL="S01_AXI_rlast"/>
+            <PORTMAP PHYSICAL="S01_AXI_rready"/>
+            <PORTMAP PHYSICAL="S01_AXI_rresp"/>
+            <PORTMAP PHYSICAL="S01_AXI_rvalid"/>
+            <PORTMAP PHYSICAL="S01_AXI_wdata"/>
+            <PORTMAP PHYSICAL="S01_AXI_wlast"/>
+            <PORTMAP PHYSICAL="S01_AXI_wready"/>
+            <PORTMAP PHYSICAL="S01_AXI_wstrb"/>
+            <PORTMAP PHYSICAL="S01_AXI_wvalid"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+      </BUSINTERFACES>
+    </MODULE>
+    <MODULE FULLNAME="/axi_timer_0" HWVERSION="2.0" INSTANCE="axi_timer_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="axi_timer" VLNV="xilinx.com:ip:axi_timer:2.0">
+      <DOCUMENTS>
+        <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_timer;v=v2_0;d=pg079-axi-timer.pdf"/>
+      </DOCUMENTS>
+      <PARAMETERS>
+        <PARAMETER NAME="C_FAMILY" VALUE="kintex7"/>
+        <PARAMETER NAME="C_COUNT_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_ONE_TIMER_ONLY" VALUE="0"/>
+        <PARAMETER NAME="C_TRIG0_ASSERT" VALUE="&quot;1&quot;"/>
+        <PARAMETER NAME="C_TRIG1_ASSERT" VALUE="&quot;1&quot;"/>
+        <PARAMETER NAME="C_GEN0_ASSERT" VALUE="&quot;1&quot;"/>
+        <PARAMETER NAME="C_GEN1_ASSERT" VALUE="&quot;1&quot;"/>
+        <PARAMETER NAME="C_S_AXI_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_S_AXI_ADDR_WIDTH" VALUE="5"/>
+        <PARAMETER NAME="Component_Name" VALUE="base_microblaze_design_axi_timer_0_0"/>
+        <PARAMETER NAME="TRIG0_ASSERT" VALUE="Active_High"/>
+        <PARAMETER NAME="TRIG1_ASSERT" VALUE="Active_High"/>
+        <PARAMETER NAME="GEN0_ASSERT" VALUE="Active_High"/>
+        <PARAMETER NAME="GEN1_ASSERT" VALUE="Active_High"/>
+        <PARAMETER NAME="COUNT_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="mode_64bit" VALUE="0"/>
+        <PARAMETER NAME="enable_timer2" VALUE="1"/>
+        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
+        <PARAMETER NAME="C_BASEADDR" VALUE="0x41C00000"/>
+        <PARAMETER NAME="C_HIGHADDR" VALUE="0x41C0FFFF"/>
+      </PARAMETERS>
+      <PORTS>
+        <PORT DIR="I" NAME="capturetrig0" SIGIS="undef"/>
+        <PORT DIR="I" NAME="capturetrig1" SIGIS="undef"/>
+        <PORT DIR="O" NAME="generateout0" SIGIS="undef"/>
+        <PORT DIR="O" NAME="generateout1" SIGIS="undef"/>
+        <PORT DIR="O" NAME="pwm0" SIGIS="undef"/>
+        <PORT DIR="O" NAME="interrupt" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="axi_timer_0_interrupt">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_intc_0" PORT="intr"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="freeze" SIGIS="undef"/>
+        <PORT CLKFREQUENCY="100000000" DIR="I" NAME="s_axi_aclk" SIGIS="clk" SIGNAME="mig_7series_0_ui_clk">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="mig_7series_0" PORT="ui_clk"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="s_axi_aresetn" SIGIS="rst" SIGNAME="rst_clk_wiz_1_100M_peripheral_aresetn">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="rst_clk_wiz_1_100M" PORT="peripheral_aresetn"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="4" NAME="s_axi_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_timer_0_s_axi_awaddr">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M02_AXI_awaddr"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="s_axi_awvalid" SIGIS="undef" SIGNAME="axi_timer_0_s_axi_awvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M02_AXI_awvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="s_axi_awready" SIGIS="undef" SIGNAME="axi_timer_0_s_axi_awready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M02_AXI_awready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="31" NAME="s_axi_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_timer_0_s_axi_wdata">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M02_AXI_wdata"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="3" NAME="s_axi_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axi_timer_0_s_axi_wstrb">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M02_AXI_wstrb"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="s_axi_wvalid" SIGIS="undef" SIGNAME="axi_timer_0_s_axi_wvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M02_AXI_wvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="s_axi_wready" SIGIS="undef" SIGNAME="axi_timer_0_s_axi_wready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M02_AXI_wready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="1" NAME="s_axi_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_timer_0_s_axi_bresp">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M02_AXI_bresp"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="s_axi_bvalid" SIGIS="undef" SIGNAME="axi_timer_0_s_axi_bvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M02_AXI_bvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="s_axi_bready" SIGIS="undef" SIGNAME="axi_timer_0_s_axi_bready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M02_AXI_bready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="4" NAME="s_axi_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_timer_0_s_axi_araddr">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M02_AXI_araddr"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="s_axi_arvalid" SIGIS="undef" SIGNAME="axi_timer_0_s_axi_arvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M02_AXI_arvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="s_axi_arready" SIGIS="undef" SIGNAME="axi_timer_0_s_axi_arready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M02_AXI_arready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="31" NAME="s_axi_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_timer_0_s_axi_rdata">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M02_AXI_rdata"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="1" NAME="s_axi_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_timer_0_s_axi_rresp">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M02_AXI_rresp"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="s_axi_rvalid" SIGIS="undef" SIGNAME="axi_timer_0_s_axi_rvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M02_AXI_rvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="s_axi_rready" SIGIS="undef" SIGNAME="axi_timer_0_s_axi_rready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M02_AXI_rready"/>
+          </CONNECTIONS>
+        </PORT>
+      </PORTS>
+      <BUSINTERFACES>
+        <BUSINTERFACE BUSNAME="microblaze_0_axi_periph_M02_AXI" NAME="S_AXI" TYPE="SLAVE">
+          <PORTMAPS>
+            <PORTMAP PHYSICAL="s_axi_araddr"/>
+            <PORTMAP PHYSICAL="s_axi_arready"/>
+            <PORTMAP PHYSICAL="s_axi_arvalid"/>
+            <PORTMAP PHYSICAL="s_axi_awaddr"/>
+            <PORTMAP PHYSICAL="s_axi_awready"/>
+            <PORTMAP PHYSICAL="s_axi_awvalid"/>
+            <PORTMAP PHYSICAL="s_axi_bready"/>
+            <PORTMAP PHYSICAL="s_axi_bresp"/>
+            <PORTMAP PHYSICAL="s_axi_bvalid"/>
+            <PORTMAP PHYSICAL="s_axi_rdata"/>
+            <PORTMAP PHYSICAL="s_axi_rready"/>
+            <PORTMAP PHYSICAL="s_axi_rresp"/>
+            <PORTMAP PHYSICAL="s_axi_rvalid"/>
+            <PORTMAP PHYSICAL="s_axi_wdata"/>
+            <PORTMAP PHYSICAL="s_axi_wready"/>
+            <PORTMAP PHYSICAL="s_axi_wstrb"/>
+            <PORTMAP PHYSICAL="s_axi_wvalid"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+      </BUSINTERFACES>
+      <INTERRUPTINFO TYPE="SOURCE">
+        <TARGET INSTANCE="axi_intc_0" INTC_INDEX="0" PRIORITY="0"/>
+      </INTERRUPTINFO>
+    </MODULE>
+    <MODULE FULLNAME="/axi_uartlite_0" HWVERSION="2.0" INSTANCE="axi_uartlite_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="axi_uartlite" VLNV="xilinx.com:ip:axi_uartlite:2.0">
+      <DOCUMENTS>
+        <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_uartlite;v=v2_0;d=pg142-axi-uartlite.pdf"/>
+      </DOCUMENTS>
+      <PARAMETERS>
+        <PARAMETER NAME="C_FAMILY" VALUE="kintex7"/>
+        <PARAMETER NAME="C_S_AXI_ACLK_FREQ_HZ" VALUE="100000000"/>
+        <PARAMETER NAME="C_S_AXI_ADDR_WIDTH" VALUE="4"/>
+        <PARAMETER NAME="C_S_AXI_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_BAUDRATE" VALUE="115200"/>
+        <PARAMETER NAME="C_DATA_BITS" VALUE="8"/>
+        <PARAMETER NAME="C_USE_PARITY" VALUE="0"/>
+        <PARAMETER NAME="C_ODD_PARITY" VALUE="0"/>
+        <PARAMETER NAME="C_S_AXI_ACLK_FREQ_HZ_d" VALUE="100"/>
+        <PARAMETER NAME="Component_Name" VALUE="base_microblaze_design_axi_uartlite_0_0"/>
+        <PARAMETER NAME="PARITY" VALUE="No_Parity"/>
+        <PARAMETER NAME="USE_BOARD_FLOW" VALUE="true"/>
+        <PARAMETER NAME="UARTLITE_BOARD_INTERFACE" VALUE="rs232_uart"/>
+        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
+        <PARAMETER NAME="C_BASEADDR" VALUE="0x40600000"/>
+        <PARAMETER NAME="C_HIGHADDR" VALUE="0x4060FFFF"/>
+      </PARAMETERS>
+      <PORTS>
+        <PORT CLKFREQUENCY="100000000" DIR="I" NAME="s_axi_aclk" SIGIS="clk" SIGNAME="mig_7series_0_ui_clk">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="mig_7series_0" PORT="ui_clk"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="s_axi_aresetn" SIGIS="rst" SIGNAME="rst_clk_wiz_1_100M_peripheral_aresetn">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="rst_clk_wiz_1_100M" PORT="peripheral_aresetn"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="interrupt" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="axi_uartlite_0_interrupt">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_intc_0" PORT="intr"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="3" NAME="s_axi_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_uartlite_0_s_axi_awaddr">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M00_AXI_awaddr"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="s_axi_awvalid" SIGIS="undef" SIGNAME="axi_uartlite_0_s_axi_awvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M00_AXI_awvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="s_axi_awready" SIGIS="undef" SIGNAME="axi_uartlite_0_s_axi_awready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M00_AXI_awready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="31" NAME="s_axi_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_uartlite_0_s_axi_wdata">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M00_AXI_wdata"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="3" NAME="s_axi_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axi_uartlite_0_s_axi_wstrb">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M00_AXI_wstrb"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="s_axi_wvalid" SIGIS="undef" SIGNAME="axi_uartlite_0_s_axi_wvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M00_AXI_wvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="s_axi_wready" SIGIS="undef" SIGNAME="axi_uartlite_0_s_axi_wready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M00_AXI_wready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="1" NAME="s_axi_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_uartlite_0_s_axi_bresp">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M00_AXI_bresp"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="s_axi_bvalid" SIGIS="undef" SIGNAME="axi_uartlite_0_s_axi_bvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M00_AXI_bvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="s_axi_bready" SIGIS="undef" SIGNAME="axi_uartlite_0_s_axi_bready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M00_AXI_bready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="3" NAME="s_axi_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_uartlite_0_s_axi_araddr">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M00_AXI_araddr"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="s_axi_arvalid" SIGIS="undef" SIGNAME="axi_uartlite_0_s_axi_arvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M00_AXI_arvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="s_axi_arready" SIGIS="undef" SIGNAME="axi_uartlite_0_s_axi_arready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M00_AXI_arready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="31" NAME="s_axi_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_uartlite_0_s_axi_rdata">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M00_AXI_rdata"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="1" NAME="s_axi_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_uartlite_0_s_axi_rresp">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M00_AXI_rresp"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="s_axi_rvalid" SIGIS="undef" SIGNAME="axi_uartlite_0_s_axi_rvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M00_AXI_rvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="s_axi_rready" SIGIS="undef" SIGNAME="axi_uartlite_0_s_axi_rready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M00_AXI_rready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="rx" SIGIS="undef"/>
+        <PORT DIR="O" NAME="tx" SIGIS="undef"/>
+      </PORTS>
+      <BUSINTERFACES>
+        <BUSINTERFACE BUSNAME="microblaze_0_axi_periph_M00_AXI" NAME="S_AXI" TYPE="SLAVE">
+          <PORTMAPS>
+            <PORTMAP PHYSICAL="s_axi_araddr"/>
+            <PORTMAP PHYSICAL="s_axi_arready"/>
+            <PORTMAP PHYSICAL="s_axi_arvalid"/>
+            <PORTMAP PHYSICAL="s_axi_awaddr"/>
+            <PORTMAP PHYSICAL="s_axi_awready"/>
+            <PORTMAP PHYSICAL="s_axi_awvalid"/>
+            <PORTMAP PHYSICAL="s_axi_bready"/>
+            <PORTMAP PHYSICAL="s_axi_bresp"/>
+            <PORTMAP PHYSICAL="s_axi_bvalid"/>
+            <PORTMAP PHYSICAL="s_axi_rdata"/>
+            <PORTMAP PHYSICAL="s_axi_rready"/>
+            <PORTMAP PHYSICAL="s_axi_rresp"/>
+            <PORTMAP PHYSICAL="s_axi_rvalid"/>
+            <PORTMAP PHYSICAL="s_axi_wdata"/>
+            <PORTMAP PHYSICAL="s_axi_wready"/>
+            <PORTMAP PHYSICAL="s_axi_wstrb"/>
+            <PORTMAP PHYSICAL="s_axi_wvalid"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="axi_uartlite_0_UART" NAME="UART" TYPE="INITIATOR">
+          <PORTMAPS>
+            <PORTMAP PHYSICAL="rx"/>
+            <PORTMAP PHYSICAL="tx"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+      </BUSINTERFACES>
+      <INTERRUPTINFO TYPE="SOURCE">
+        <TARGET INSTANCE="axi_intc_0" INTC_INDEX="0" PRIORITY="1"/>
+      </INTERRUPTINFO>
+    </MODULE>
+    <MODULE FULLNAME="/mdm_1" HWVERSION="3.2" INSTANCE="mdm_1" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="DEBUG" MODTYPE="mdm" VLNV="xilinx.com:ip:mdm:3.2">
+      <DOCUMENTS>
+        <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=mdm;v=v3_2;d=pg115-mdm.pdf"/>
+      </DOCUMENTS>
+      <PARAMETERS>
+        <PARAMETER NAME="C_FAMILY" VALUE="kintex7"/>
+        <PARAMETER NAME="C_JTAG_CHAIN" VALUE="2"/>
+        <PARAMETER NAME="C_USE_BSCAN" VALUE="0"/>
+        <PARAMETER NAME="C_USE_CONFIG_RESET" VALUE="0"/>
+        <PARAMETER NAME="C_INTERCONNECT" VALUE="2"/>
+        <PARAMETER NAME="C_MB_DBG_PORTS" VALUE="1"/>
+        <PARAMETER NAME="C_USE_UART" VALUE="0"/>
+        <PARAMETER NAME="C_DBG_REG_ACCESS" VALUE="0"/>
+        <PARAMETER NAME="C_DBG_MEM_ACCESS" VALUE="0"/>
+        <PARAMETER NAME="C_USE_CROSS_TRIGGER" VALUE="0"/>
+        <PARAMETER NAME="C_TRACE_OUTPUT" VALUE="0"/>
+        <PARAMETER NAME="C_TRACE_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_TRACE_CLK_FREQ_HZ" VALUE="200000000"/>
+        <PARAMETER NAME="C_TRACE_CLK_OUT_PHASE" VALUE="90"/>
+        <PARAMETER NAME="C_S_AXI_ADDR_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_S_AXI_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_S_AXI_ACLK_FREQ_HZ" VALUE="100000000"/>
+        <PARAMETER NAME="C_M_AXI_ADDR_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_M_AXI_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_M_AXI_THREAD_ID_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C_DATA_SIZE" VALUE="32"/>
+        <PARAMETER NAME="C_M_AXIS_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_M_AXIS_ID_WIDTH" VALUE="7"/>
+        <PARAMETER NAME="C_XMTC" VALUE="0"/>
+        <PARAMETER NAME="C_BRK" VALUE="0"/>
+        <PARAMETER NAME="C_TRIG_IN_PORTS" VALUE="1"/>
+        <PARAMETER NAME="C_TRIG_OUT_PORTS" VALUE="1"/>
+        <PARAMETER NAME="Component_Name" VALUE="base_microblaze_design_mdm_1_0"/>
+        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
+      </PARAMETERS>
+      <PORTS>
+        <PORT DIR="O" NAME="Debug_SYS_Rst" SIGIS="rst" SIGNAME="mdm_1_Debug_SYS_Rst">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="rst_clk_wiz_1_100M" PORT="mb_debug_sys_rst"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="Dbg_Clk_0" SIGIS="undef" SIGNAME="mdm_1_Dbg_Clk_0">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="Dbg_Clk"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="Dbg_TDI_0" SIGIS="undef" SIGNAME="mdm_1_Dbg_TDI_0">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="Dbg_TDI"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="Dbg_TDO_0" SIGIS="undef" SIGNAME="mdm_1_Dbg_TDO_0">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="Dbg_TDO"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="0" NAME="Dbg_Reg_En_0" RIGHT="7" SIGIS="undef" SIGNAME="mdm_1_Dbg_Reg_En_0">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="Dbg_Reg_En"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="Dbg_Capture_0" SIGIS="undef" SIGNAME="mdm_1_Dbg_Capture_0">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="Dbg_Capture"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="Dbg_Shift_0" SIGIS="undef" SIGNAME="mdm_1_Dbg_Shift_0">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="Dbg_Shift"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="Dbg_Update_0" SIGIS="undef" SIGNAME="mdm_1_Dbg_Update_0">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="Dbg_Update"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="Dbg_Rst_0" SIGIS="undef" SIGNAME="mdm_1_Dbg_Rst_0">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="Debug_Rst"/>
+          </CONNECTIONS>
+        </PORT>
+      </PORTS>
+      <BUSINTERFACES>
+        <BUSINTERFACE BUSNAME="mdm_1_MBDEBUG_0" NAME="MBDEBUG_0" TYPE="INITIATOR">
+          <PORTMAPS>
+            <PORTMAP PHYSICAL="Dbg_Capture_0"/>
+            <PORTMAP PHYSICAL="Dbg_Clk_0"/>
+            <PORTMAP PHYSICAL="Dbg_Reg_En_0"/>
+            <PORTMAP PHYSICAL="Dbg_Rst_0"/>
+            <PORTMAP PHYSICAL="Dbg_Shift_0"/>
+            <PORTMAP PHYSICAL="Dbg_TDI_0"/>
+            <PORTMAP PHYSICAL="Dbg_TDO_0"/>
+            <PORTMAP PHYSICAL="Dbg_Update_0"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+      </BUSINTERFACES>
+      <MEMORYMAP/>
+      <PERIPHERALS>
+        <PERIPHERAL INSTANCE="microblaze_0"/>
+      </PERIPHERALS>
+    </MODULE>
+    <MODULE FULLNAME="/microblaze_0" HWVERSION="9.4" INSTANCE="microblaze_0" IPTYPE="PROCESSOR" IS_ENABLE="1" MODCLASS="PROCESSOR" MODTYPE="microblaze" PROCTYPE="microblaze" VLNV="xilinx.com:ip:microblaze:9.4">
+      <DOCUMENTS>
+        <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/rdoc?v=2014.3;d=ug984-vivado-microblaze-ref.pdf"/>
+      </DOCUMENTS>
+      <PARAMETERS>
+        <PARAMETER NAME="C_SCO" VALUE="0"/>
+        <PARAMETER NAME="C_FREQ" VALUE="100000000"/>
+        <PARAMETER NAME="C_USE_CONFIG_RESET" VALUE="0"/>
+        <PARAMETER NAME="C_NUM_SYNC_FF_CLK" VALUE="2"/>
+        <PARAMETER NAME="C_NUM_SYNC_FF_CLK_IRQ" VALUE="1"/>
+        <PARAMETER NAME="C_NUM_SYNC_FF_CLK_DEBUG" VALUE="2"/>
+        <PARAMETER NAME="C_NUM_SYNC_FF_DBG_CLK" VALUE="1"/>
+        <PARAMETER NAME="C_FAULT_TOLERANT" VALUE="0"/>
+        <PARAMETER NAME="C_ECC_USE_CE_EXCEPTION" VALUE="0"/>
+        <PARAMETER NAME="C_LOCKSTEP_SLAVE" VALUE="0"/>
+        <PARAMETER NAME="C_FAMILY" VALUE="kintex7"/>
+        <PARAMETER NAME="C_DATA_SIZE" VALUE="32"/>
+        <PARAMETER NAME="C_INSTANCE" VALUE="base_microblaze_design_microblaze_0_0"/>
+        <PARAMETER NAME="C_AVOID_PRIMITIVES" VALUE="0"/>
+        <PARAMETER NAME="C_AREA_OPTIMIZED" VALUE="0"/>
+        <PARAMETER NAME="C_OPTIMIZATION" VALUE="0"/>
+        <PARAMETER NAME="C_INTERCONNECT" VALUE="2"/>
+        <PARAMETER NAME="C_BASE_VECTORS" VALUE="0x00000000"/>
+        <PARAMETER NAME="C_M_AXI_DP_THREAD_ID_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C_M_AXI_DP_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_M_AXI_DP_ADDR_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_M_AXI_DP_EXCLUSIVE_ACCESS" VALUE="0"/>
+        <PARAMETER NAME="C_M_AXI_D_BUS_EXCEPTION" VALUE="1"/>
+        <PARAMETER NAME="C_M_AXI_IP_THREAD_ID_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C_M_AXI_IP_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_M_AXI_IP_ADDR_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_M_AXI_I_BUS_EXCEPTION" VALUE="1"/>
+        <PARAMETER NAME="C_D_LMB" VALUE="1"/>
+        <PARAMETER NAME="C_D_AXI" VALUE="1"/>
+        <PARAMETER NAME="C_I_LMB" VALUE="1"/>
+        <PARAMETER NAME="C_I_AXI" VALUE="0"/>
+        <PARAMETER NAME="C_USE_MSR_INSTR" VALUE="1"/>
+        <PARAMETER NAME="C_USE_PCMP_INSTR" VALUE="1"/>
+        <PARAMETER NAME="C_USE_BARREL" VALUE="1"/>
+        <PARAMETER NAME="C_USE_DIV" VALUE="1"/>
+        <PARAMETER NAME="C_USE_HW_MUL" VALUE="2"/>
+        <PARAMETER NAME="C_USE_FPU" VALUE="2"/>
+        <PARAMETER NAME="C_USE_REORDER_INSTR" VALUE="1"/>
+        <PARAMETER NAME="C_UNALIGNED_EXCEPTIONS" VALUE="1"/>
+        <PARAMETER NAME="C_ILL_OPCODE_EXCEPTION" VALUE="1"/>
+        <PARAMETER NAME="C_DIV_ZERO_EXCEPTION" VALUE="1"/>
+        <PARAMETER NAME="C_FPU_EXCEPTION" VALUE="1"/>
+        <PARAMETER NAME="C_FSL_LINKS" VALUE="0"/>
+        <PARAMETER NAME="C_USE_EXTENDED_FSL_INSTR" VALUE="0"/>
+        <PARAMETER NAME="C_FSL_EXCEPTION" VALUE="0"/>
+        <PARAMETER NAME="C_USE_STACK_PROTECTION" VALUE="1"/>
+        <PARAMETER NAME="C_USE_INTERRUPT" VALUE="1"/>
+        <PARAMETER NAME="C_USE_EXT_BRK" VALUE="0"/>
+        <PARAMETER NAME="C_USE_EXT_NM_BRK" VALUE="0"/>
+        <PARAMETER NAME="C_USE_MMU" VALUE="0"/>
+        <PARAMETER NAME="C_MMU_DTLB_SIZE" VALUE="4"/>
+        <PARAMETER NAME="C_MMU_ITLB_SIZE" VALUE="2"/>
+        <PARAMETER NAME="C_MMU_TLB_ACCESS" VALUE="3"/>
+        <PARAMETER NAME="C_MMU_ZONES" VALUE="2"/>
+        <PARAMETER NAME="C_MMU_PRIVILEGED_INSTR" VALUE="0"/>
+        <PARAMETER NAME="C_USE_BRANCH_TARGET_CACHE" VALUE="1"/>
+        <PARAMETER NAME="C_BRANCH_TARGET_CACHE_SIZE" VALUE="0"/>
+        <PARAMETER NAME="C_PC_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_PVR" VALUE="0"/>
+        <PARAMETER NAME="C_PVR_USER1" VALUE="0x00"/>
+        <PARAMETER NAME="C_PVR_USER2" VALUE="0x00000000"/>
+        <PARAMETER NAME="C_DYNAMIC_BUS_SIZING" VALUE="0"/>
+        <PARAMETER NAME="C_RESET_MSR" VALUE="0x00000000"/>
+        <PARAMETER NAME="C_OPCODE_0x0_ILLEGAL" VALUE="1"/>
+        <PARAMETER NAME="C_DEBUG_ENABLED" VALUE="1"/>
+        <PARAMETER NAME="C_NUMBER_OF_PC_BRK" VALUE="8"/>
+        <PARAMETER NAME="C_NUMBER_OF_RD_ADDR_BRK" VALUE="2"/>
+        <PARAMETER NAME="C_NUMBER_OF_WR_ADDR_BRK" VALUE="2"/>
+        <PARAMETER NAME="C_DEBUG_EVENT_COUNTERS" VALUE="5"/>
+        <PARAMETER NAME="C_DEBUG_LATENCY_COUNTERS" VALUE="1"/>
+        <PARAMETER NAME="C_DEBUG_COUNTER_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_DEBUG_TRACE_SIZE" VALUE="8192"/>
+        <PARAMETER NAME="C_DEBUG_EXTERNAL_TRACE" VALUE="0"/>
+        <PARAMETER NAME="C_DEBUG_PROFILE_SIZE" VALUE="0"/>
+        <PARAMETER NAME="C_INTERRUPT_IS_EDGE" VALUE="0"/>
+        <PARAMETER NAME="C_EDGE_IS_POSITIVE" VALUE="1"/>
+        <PARAMETER NAME="C_ASYNC_INTERRUPT" VALUE="1"/>
+        <PARAMETER NAME="C_M0_AXIS_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_S0_AXIS_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_M1_AXIS_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_S1_AXIS_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_M2_AXIS_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_S2_AXIS_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_M3_AXIS_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_S3_AXIS_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_M4_AXIS_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_S4_AXIS_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_M5_AXIS_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_S5_AXIS_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_M6_AXIS_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_S6_AXIS_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_M7_AXIS_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_S7_AXIS_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_M8_AXIS_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_S8_AXIS_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_M9_AXIS_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_S9_AXIS_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_M10_AXIS_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_S10_AXIS_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_M11_AXIS_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_S11_AXIS_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_M12_AXIS_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_S12_AXIS_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_M13_AXIS_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_S13_AXIS_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_M14_AXIS_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_S14_AXIS_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_M15_AXIS_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_S15_AXIS_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_ICACHE_BASEADDR" VALUE="0x80000000"/>
+        <PARAMETER NAME="C_ICACHE_HIGHADDR" VALUE="0xbfffffff"/>
+        <PARAMETER NAME="C_USE_ICACHE" VALUE="1"/>
+        <PARAMETER NAME="C_ALLOW_ICACHE_WR" VALUE="1"/>
+        <PARAMETER NAME="C_ADDR_TAG_BITS" VALUE="15"/>
+        <PARAMETER NAME="C_CACHE_BYTE_SIZE" VALUE="32768"/>
+        <PARAMETER NAME="C_ICACHE_LINE_LEN" VALUE="8"/>
+        <PARAMETER NAME="C_ICACHE_ALWAYS_USED" VALUE="1"/>
+        <PARAMETER NAME="C_ICACHE_STREAMS" VALUE="1"/>
+        <PARAMETER NAME="C_ICACHE_VICTIMS" VALUE="8"/>
+        <PARAMETER NAME="C_ICACHE_FORCE_TAG_LUTRAM" VALUE="0"/>
+        <PARAMETER NAME="C_ICACHE_DATA_WIDTH" VALUE="0"/>
+        <PARAMETER NAME="C_M_AXI_IC_THREAD_ID_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C_M_AXI_IC_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_M_AXI_IC_ADDR_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_M_AXI_IC_USER_VALUE" VALUE="31"/>
+        <PARAMETER NAME="C_M_AXI_IC_AWUSER_WIDTH" VALUE="5"/>
+        <PARAMETER NAME="C_M_AXI_IC_ARUSER_WIDTH" VALUE="5"/>
+        <PARAMETER NAME="C_M_AXI_IC_WUSER_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C_M_AXI_IC_RUSER_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C_M_AXI_IC_BUSER_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C_DCACHE_BASEADDR" VALUE="0x80000000"/>
+        <PARAMETER NAME="C_DCACHE_HIGHADDR" VALUE="0xbfffffff"/>
+        <PARAMETER NAME="C_USE_DCACHE" VALUE="1"/>
+        <PARAMETER NAME="C_ALLOW_DCACHE_WR" VALUE="1"/>
+        <PARAMETER NAME="C_DCACHE_ADDR_TAG" VALUE="15"/>
+        <PARAMETER NAME="C_DCACHE_BYTE_SIZE" VALUE="32768"/>
+        <PARAMETER NAME="C_DCACHE_LINE_LEN" VALUE="8"/>
+        <PARAMETER NAME="C_DCACHE_ALWAYS_USED" VALUE="1"/>
+        <PARAMETER NAME="C_DCACHE_USE_WRITEBACK" VALUE="1"/>
+        <PARAMETER NAME="C_DCACHE_VICTIMS" VALUE="8"/>
+        <PARAMETER NAME="C_DCACHE_FORCE_TAG_LUTRAM" VALUE="0"/>
+        <PARAMETER NAME="C_DCACHE_DATA_WIDTH" VALUE="0"/>
+        <PARAMETER NAME="C_M_AXI_DC_THREAD_ID_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C_M_AXI_DC_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_M_AXI_DC_ADDR_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_M_AXI_DC_EXCLUSIVE_ACCESS" VALUE="0"/>
+        <PARAMETER NAME="C_M_AXI_DC_USER_VALUE" VALUE="31"/>
+        <PARAMETER NAME="C_M_AXI_DC_AWUSER_WIDTH" VALUE="5"/>
+        <PARAMETER NAME="C_M_AXI_DC_ARUSER_WIDTH" VALUE="5"/>
+        <PARAMETER NAME="C_M_AXI_DC_WUSER_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C_M_AXI_DC_RUSER_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C_M_AXI_DC_BUSER_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C_TRACE" VALUE="1"/>
+        <PARAMETER NAME="C_LOCKSTEP_SELECT" VALUE="0"/>
+        <PARAMETER NAME="C_ENABLE_DISCRETE_PORTS" VALUE="0"/>
+        <PARAMETER NAME="C_M_AXI_DC_USER_SIGNALS" VALUE="0"/>
+        <PARAMETER NAME="C_M_AXI_IC_USER_SIGNALS" VALUE="0"/>
+        <PARAMETER NAME="G_TEMPLATE_LIST" VALUE="2"/>
+        <PARAMETER NAME="G_USE_EXCEPTIONS" VALUE="1"/>
+        <PARAMETER NAME="C_M0_AXIS_PROTOCOL" VALUE="GENERIC"/>
+        <PARAMETER NAME="C_S0_AXIS_PROTOCOL" VALUE="GENERIC"/>
+        <PARAMETER NAME="C_M1_AXIS_PROTOCOL" VALUE="GENERIC"/>
+        <PARAMETER NAME="C_S1_AXIS_PROTOCOL" VALUE="GENERIC"/>
+        <PARAMETER NAME="C_M2_AXIS_PROTOCOL" VALUE="GENERIC"/>
+        <PARAMETER NAME="C_S2_AXIS_PROTOCOL" VALUE="GENERIC"/>
+        <PARAMETER NAME="C_M3_AXIS_PROTOCOL" VALUE="GENERIC"/>
+        <PARAMETER NAME="C_S3_AXIS_PROTOCOL" VALUE="GENERIC"/>
+        <PARAMETER NAME="C_M4_AXIS_PROTOCOL" VALUE="GENERIC"/>
+        <PARAMETER NAME="C_S4_AXIS_PROTOCOL" VALUE="GENERIC"/>
+        <PARAMETER NAME="C_M5_AXIS_PROTOCOL" VALUE="GENERIC"/>
+        <PARAMETER NAME="C_S5_AXIS_PROTOCOL" VALUE="GENERIC"/>
+        <PARAMETER NAME="C_M6_AXIS_PROTOCOL" VALUE="GENERIC"/>
+        <PARAMETER NAME="C_S6_AXIS_PROTOCOL" VALUE="GENERIC"/>
+        <PARAMETER NAME="C_M7_AXIS_PROTOCOL" VALUE="GENERIC"/>
+        <PARAMETER NAME="C_S7_AXIS_PROTOCOL" VALUE="GENERIC"/>
+        <PARAMETER NAME="C_M8_AXIS_PROTOCOL" VALUE="GENERIC"/>
+        <PARAMETER NAME="C_S8_AXIS_PROTOCOL" VALUE="GENERIC"/>
+        <PARAMETER NAME="C_M9_AXIS_PROTOCOL" VALUE="GENERIC"/>
+        <PARAMETER NAME="C_S9_AXIS_PROTOCOL" VALUE="GENERIC"/>
+        <PARAMETER NAME="C_M10_AXIS_PROTOCOL" VALUE="GENERIC"/>
+        <PARAMETER NAME="C_S10_AXIS_PROTOCOL" VALUE="GENERIC"/>
+        <PARAMETER NAME="C_M11_AXIS_PROTOCOL" VALUE="GENERIC"/>
+        <PARAMETER NAME="C_S11_AXIS_PROTOCOL" VALUE="GENERIC"/>
+        <PARAMETER NAME="C_M12_AXIS_PROTOCOL" VALUE="GENERIC"/>
+        <PARAMETER NAME="C_S12_AXIS_PROTOCOL" VALUE="GENERIC"/>
+        <PARAMETER NAME="C_M13_AXIS_PROTOCOL" VALUE="GENERIC"/>
+        <PARAMETER NAME="C_S13_AXIS_PROTOCOL" VALUE="GENERIC"/>
+        <PARAMETER NAME="C_M14_AXIS_PROTOCOL" VALUE="GENERIC"/>
+        <PARAMETER NAME="C_S14_AXIS_PROTOCOL" VALUE="GENERIC"/>
+        <PARAMETER NAME="C_M15_AXIS_PROTOCOL" VALUE="GENERIC"/>
+        <PARAMETER NAME="C_S15_AXIS_PROTOCOL" VALUE="GENERIC"/>
+        <PARAMETER NAME="Component_Name" VALUE="base_microblaze_design_microblaze_0_0"/>
+        <PARAMETER NAME="C_ENDIANNESS" VALUE="1"/>
+        <PARAMETER NAME="EDK_IPTYPE" VALUE="PROCESSOR"/>
+        <PARAMETER NAME="EDK_SPECIAL" VALUE="microblaze"/>
+      </PARAMETERS>
+      <PORTS>
+        <PORT CLKFREQUENCY="100000000" DIR="I" NAME="Clk" SIGIS="clk" SIGNAME="mig_7series_0_ui_clk">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="mig_7series_0" PORT="ui_clk"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="Reset" SIGIS="rst" SIGNAME="rst_clk_wiz_1_100M_mb_reset">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="rst_clk_wiz_1_100M" PORT="mb_reset"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="Interrupt" SIGIS="INTERRUPT" SIGNAME="axi_intc_0_irq">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_intc_0" PORT="irq"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="0" NAME="Interrupt_Address" RIGHT="31" SIGIS="undef"/>
+        <PORT DIR="O" LEFT="0" NAME="Interrupt_Ack" RIGHT="1" SIGIS="undef"/>
+        <PORT DIR="O" LEFT="0" NAME="Instr_Addr" RIGHT="31" SIGIS="undef" SIGNAME="microblaze_0_Instr_Addr">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_v10" PORT="M_ABus"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="0" NAME="Instr" RIGHT="31" SIGIS="undef" SIGNAME="microblaze_0_Instr">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_v10" PORT="LMB_ReadDBus"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="IFetch" SIGIS="undef" SIGNAME="microblaze_0_IFetch">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_v10" PORT="M_ReadStrobe"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="I_AS" SIGIS="undef" SIGNAME="microblaze_0_I_AS">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_v10" PORT="M_AddrStrobe"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="IReady" SIGIS="undef" SIGNAME="microblaze_0_IReady">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_v10" PORT="LMB_Ready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="IWAIT" SIGIS="undef" SIGNAME="microblaze_0_IWAIT">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_v10" PORT="LMB_Wait"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="ICE" SIGIS="undef" SIGNAME="microblaze_0_ICE">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_v10" PORT="LMB_CE"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="IUE" SIGIS="undef" SIGNAME="microblaze_0_IUE">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_v10" PORT="LMB_UE"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="0" NAME="Data_Addr" RIGHT="31" SIGIS="undef" SIGNAME="microblaze_0_Data_Addr">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_v10" PORT="M_ABus"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="0" NAME="Data_Read" RIGHT="31" SIGIS="undef" SIGNAME="microblaze_0_Data_Read">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_v10" PORT="LMB_ReadDBus"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="0" NAME="Data_Write" RIGHT="31" SIGIS="undef" SIGNAME="microblaze_0_Data_Write">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_v10" PORT="M_DBus"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="D_AS" SIGIS="undef" SIGNAME="microblaze_0_D_AS">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_v10" PORT="M_AddrStrobe"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="Read_Strobe" SIGIS="undef" SIGNAME="microblaze_0_Read_Strobe">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_v10" PORT="M_ReadStrobe"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="Write_Strobe" SIGIS="undef" SIGNAME="microblaze_0_Write_Strobe">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_v10" PORT="M_WriteStrobe"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="DReady" SIGIS="undef" SIGNAME="microblaze_0_DReady">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_v10" PORT="LMB_Ready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="DWait" SIGIS="undef" SIGNAME="microblaze_0_DWait">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_v10" PORT="LMB_Wait"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="DCE" SIGIS="undef" SIGNAME="microblaze_0_DCE">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_v10" PORT="LMB_CE"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="DUE" SIGIS="undef" SIGNAME="microblaze_0_DUE">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_v10" PORT="LMB_UE"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="0" NAME="Byte_Enable" RIGHT="3" SIGIS="undef" SIGNAME="microblaze_0_Byte_Enable">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_v10" PORT="M_BE"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="31" NAME="M_AXI_DP_AWADDR" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_M_AXI_DP_AWADDR">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="S00_AXI_awaddr"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="2" NAME="M_AXI_DP_AWPROT" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_M_AXI_DP_AWPROT">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="S00_AXI_awprot"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="M_AXI_DP_AWVALID" SIGIS="undef" SIGNAME="microblaze_0_M_AXI_DP_AWVALID">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="S00_AXI_awvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M_AXI_DP_AWREADY" SIGIS="undef" SIGNAME="microblaze_0_M_AXI_DP_AWREADY">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="S00_AXI_awready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="31" NAME="M_AXI_DP_WDATA" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_M_AXI_DP_WDATA">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="S00_AXI_wdata"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="3" NAME="M_AXI_DP_WSTRB" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_M_AXI_DP_WSTRB">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="S00_AXI_wstrb"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="M_AXI_DP_WVALID" SIGIS="undef" SIGNAME="microblaze_0_M_AXI_DP_WVALID">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="S00_AXI_wvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M_AXI_DP_WREADY" SIGIS="undef" SIGNAME="microblaze_0_M_AXI_DP_WREADY">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="S00_AXI_wready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="1" NAME="M_AXI_DP_BRESP" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_M_AXI_DP_BRESP">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="S00_AXI_bresp"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M_AXI_DP_BVALID" SIGIS="undef" SIGNAME="microblaze_0_M_AXI_DP_BVALID">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="S00_AXI_bvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="M_AXI_DP_BREADY" SIGIS="undef" SIGNAME="microblaze_0_M_AXI_DP_BREADY">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="S00_AXI_bready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="31" NAME="M_AXI_DP_ARADDR" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_M_AXI_DP_ARADDR">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="S00_AXI_araddr"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="2" NAME="M_AXI_DP_ARPROT" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_M_AXI_DP_ARPROT">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="S00_AXI_arprot"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="M_AXI_DP_ARVALID" SIGIS="undef" SIGNAME="microblaze_0_M_AXI_DP_ARVALID">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="S00_AXI_arvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M_AXI_DP_ARREADY" SIGIS="undef" SIGNAME="microblaze_0_M_AXI_DP_ARREADY">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="S00_AXI_arready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="31" NAME="M_AXI_DP_RDATA" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_M_AXI_DP_RDATA">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="S00_AXI_rdata"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="1" NAME="M_AXI_DP_RRESP" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_M_AXI_DP_RRESP">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="S00_AXI_rresp"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M_AXI_DP_RVALID" SIGIS="undef" SIGNAME="microblaze_0_M_AXI_DP_RVALID">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="S00_AXI_rvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="M_AXI_DP_RREADY" SIGIS="undef" SIGNAME="microblaze_0_M_AXI_DP_RREADY">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="S00_AXI_rready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="Dbg_Clk" SIGIS="undef" SIGNAME="mdm_1_Dbg_Clk_0">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="mdm_1" PORT="Dbg_Clk_0"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="Dbg_TDI" SIGIS="undef" SIGNAME="mdm_1_Dbg_TDI_0">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="mdm_1" PORT="Dbg_TDI_0"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="Dbg_TDO" SIGIS="undef" SIGNAME="mdm_1_Dbg_TDO_0">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="mdm_1" PORT="Dbg_TDO_0"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="0" NAME="Dbg_Reg_En" RIGHT="7" SIGIS="undef" SIGNAME="mdm_1_Dbg_Reg_En_0">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="mdm_1" PORT="Dbg_Reg_En_0"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="Dbg_Shift" SIGIS="undef" SIGNAME="mdm_1_Dbg_Shift_0">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="mdm_1" PORT="Dbg_Shift_0"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="Dbg_Capture" SIGIS="undef" SIGNAME="mdm_1_Dbg_Capture_0">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="mdm_1" PORT="Dbg_Capture_0"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="Dbg_Update" SIGIS="undef" SIGNAME="mdm_1_Dbg_Update_0">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="mdm_1" PORT="Dbg_Update_0"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="Debug_Rst" SIGIS="undef" SIGNAME="mdm_1_Dbg_Rst_0">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="mdm_1" PORT="Dbg_Rst_0"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="0" NAME="Trace_Instruction" RIGHT="31" SIGIS="undef"/>
+        <PORT DIR="O" NAME="Trace_Valid_Instr" SIGIS="undef"/>
+        <PORT DIR="O" LEFT="0" NAME="Trace_PC" RIGHT="31" SIGIS="undef"/>
+        <PORT DIR="O" NAME="Trace_Reg_Write" SIGIS="undef"/>
+        <PORT DIR="O" LEFT="0" NAME="Trace_Reg_Addr" RIGHT="4" SIGIS="undef"/>
+        <PORT DIR="O" LEFT="0" NAME="Trace_MSR_Reg" RIGHT="14" SIGIS="undef"/>
+        <PORT DIR="O" LEFT="0" NAME="Trace_PID_Reg" RIGHT="7" SIGIS="undef"/>
+        <PORT DIR="O" LEFT="0" NAME="Trace_New_Reg_Value" RIGHT="31" SIGIS="undef"/>
+        <PORT DIR="O" NAME="Trace_Exception_Taken" SIGIS="undef"/>
+        <PORT DIR="O" LEFT="0" NAME="Trace_Exception_Kind" RIGHT="4" SIGIS="undef"/>
+        <PORT DIR="O" NAME="Trace_Jump_Taken" SIGIS="undef"/>
+        <PORT DIR="O" NAME="Trace_Delay_Slot" SIGIS="undef"/>
+        <PORT DIR="O" LEFT="0" NAME="Trace_Data_Address" RIGHT="31" SIGIS="undef"/>
+        <PORT DIR="O" LEFT="0" NAME="Trace_Data_Write_Value" RIGHT="31" SIGIS="undef"/>
+        <PORT DIR="O" LEFT="0" NAME="Trace_Data_Byte_Enable" RIGHT="3" SIGIS="undef"/>
+        <PORT DIR="O" NAME="Trace_Data_Access" SIGIS="undef"/>
+        <PORT DIR="O" NAME="Trace_Data_Read" SIGIS="undef"/>
+        <PORT DIR="O" NAME="Trace_Data_Write" SIGIS="undef"/>
+        <PORT DIR="O" NAME="Trace_DCache_Req" SIGIS="undef"/>
+        <PORT DIR="O" NAME="Trace_DCache_Hit" SIGIS="undef"/>
+        <PORT DIR="O" NAME="Trace_DCache_Rdy" SIGIS="undef"/>
+        <PORT DIR="O" NAME="Trace_DCache_Read" SIGIS="undef"/>
+        <PORT DIR="O" NAME="Trace_ICache_Req" SIGIS="undef"/>
+        <PORT DIR="O" NAME="Trace_ICache_Hit" SIGIS="undef"/>
+        <PORT DIR="O" NAME="Trace_ICache_Rdy" SIGIS="undef"/>
+        <PORT DIR="O" NAME="Trace_OF_PipeRun" SIGIS="undef"/>
+        <PORT DIR="O" NAME="Trace_EX_PipeRun" SIGIS="undef"/>
+        <PORT DIR="O" NAME="Trace_MEM_PipeRun" SIGIS="undef"/>
+        <PORT DIR="O" NAME="Trace_MB_Halted" SIGIS="undef"/>
+        <PORT DIR="O" NAME="Trace_Jump_Hit" SIGIS="undef"/>
+        <PORT DIR="O" LEFT="0" NAME="M_AXI_IC_AWID" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_awid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_awid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="31" NAME="M_AXI_IC_AWADDR" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_awaddr">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_awaddr"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="7" NAME="M_AXI_IC_AWLEN" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_awlen">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_awlen"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="2" NAME="M_AXI_IC_AWSIZE" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_awsize">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_awsize"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="1" NAME="M_AXI_IC_AWBURST" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_awburst">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_awburst"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="M_AXI_IC_AWLOCK" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_awlock">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_awlock"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="3" NAME="M_AXI_IC_AWCACHE" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_awcache">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_awcache"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="2" NAME="M_AXI_IC_AWPROT" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_awprot">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_awprot"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="3" NAME="M_AXI_IC_AWQOS" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_awqos">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_awqos"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="M_AXI_IC_AWVALID" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_awvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_awvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M_AXI_IC_AWREADY" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_awready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_awready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="31" NAME="M_AXI_IC_WDATA" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_wdata">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_wdata"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="3" NAME="M_AXI_IC_WSTRB" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_wstrb">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_wstrb"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="M_AXI_IC_WLAST" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_wlast">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_wlast"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="M_AXI_IC_WVALID" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_wvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_wvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M_AXI_IC_WREADY" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_wready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_wready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="0" NAME="M_AXI_IC_BID" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_bid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_bid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="1" NAME="M_AXI_IC_BRESP" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_bresp">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_bresp"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M_AXI_IC_BVALID" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_bvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_bvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="M_AXI_IC_BREADY" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_bready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_bready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="0" NAME="M_AXI_IC_ARID" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_arid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_arid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="31" NAME="M_AXI_IC_ARADDR" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_araddr">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_araddr"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="7" NAME="M_AXI_IC_ARLEN" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_arlen">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_arlen"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="2" NAME="M_AXI_IC_ARSIZE" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_arsize">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_arsize"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="1" NAME="M_AXI_IC_ARBURST" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_arburst">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_arburst"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="M_AXI_IC_ARLOCK" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_arlock">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_arlock"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="3" NAME="M_AXI_IC_ARCACHE" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_arcache">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_arcache"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="2" NAME="M_AXI_IC_ARPROT" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_arprot">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_arprot"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="3" NAME="M_AXI_IC_ARQOS" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_arqos">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_arqos"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="M_AXI_IC_ARVALID" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_arvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_arvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M_AXI_IC_ARREADY" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_arready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_arready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="0" NAME="M_AXI_IC_RID" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_rid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_rid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="31" NAME="M_AXI_IC_RDATA" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_rdata">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_rdata"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="1" NAME="M_AXI_IC_RRESP" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_rresp">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_rresp"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M_AXI_IC_RLAST" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_rlast">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_rlast"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M_AXI_IC_RVALID" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_rvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_rvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="M_AXI_IC_RREADY" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_rready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_rready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="0" NAME="M_AXI_DC_AWID" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_awid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_awid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="31" NAME="M_AXI_DC_AWADDR" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_awaddr">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_awaddr"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="7" NAME="M_AXI_DC_AWLEN" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_awlen">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_awlen"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="2" NAME="M_AXI_DC_AWSIZE" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_awsize">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_awsize"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="1" NAME="M_AXI_DC_AWBURST" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_awburst">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_awburst"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="M_AXI_DC_AWLOCK" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_awlock">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_awlock"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="3" NAME="M_AXI_DC_AWCACHE" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_awcache">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_awcache"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="2" NAME="M_AXI_DC_AWPROT" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_awprot">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_awprot"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="3" NAME="M_AXI_DC_AWQOS" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_awqos">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_awqos"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="M_AXI_DC_AWVALID" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_awvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_awvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M_AXI_DC_AWREADY" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_awready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_awready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="31" NAME="M_AXI_DC_WDATA" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_wdata">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_wdata"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="3" NAME="M_AXI_DC_WSTRB" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_wstrb">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_wstrb"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="M_AXI_DC_WLAST" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_wlast">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_wlast"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="M_AXI_DC_WVALID" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_wvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_wvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M_AXI_DC_WREADY" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_wready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_wready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="1" NAME="M_AXI_DC_BRESP" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_bresp">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_bresp"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="0" NAME="M_AXI_DC_BID" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_bid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_bid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M_AXI_DC_BVALID" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_bvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_bvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="M_AXI_DC_BREADY" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_bready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_bready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="0" NAME="M_AXI_DC_ARID" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_arid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_arid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="31" NAME="M_AXI_DC_ARADDR" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_araddr">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_araddr"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="7" NAME="M_AXI_DC_ARLEN" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_arlen">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_arlen"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="2" NAME="M_AXI_DC_ARSIZE" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_arsize">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_arsize"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="1" NAME="M_AXI_DC_ARBURST" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_arburst">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_arburst"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="M_AXI_DC_ARLOCK" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_arlock">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_arlock"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="3" NAME="M_AXI_DC_ARCACHE" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_arcache">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_arcache"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="2" NAME="M_AXI_DC_ARPROT" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_arprot">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_arprot"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="3" NAME="M_AXI_DC_ARQOS" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_arqos">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_arqos"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="M_AXI_DC_ARVALID" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_arvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_arvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M_AXI_DC_ARREADY" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_arready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_arready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="0" NAME="M_AXI_DC_RID" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_rid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_rid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="31" NAME="M_AXI_DC_RDATA" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_rdata">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_rdata"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="1" NAME="M_AXI_DC_RRESP" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_rresp">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_rresp"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M_AXI_DC_RLAST" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_rlast">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_rlast"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M_AXI_DC_RVALID" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_rvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_rvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="M_AXI_DC_RREADY" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_rready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_rready"/>
+          </CONNECTIONS>
+        </PORT>
+      </PORTS>
+      <BUSINTERFACES>
+        <BUSINTERFACE BUSNAME="axi_intc_0_interrupt" NAME="INTERRUPT" TYPE="TARGET">
+          <PORTMAPS>
+            <PORTMAP PHYSICAL="Interrupt_Ack"/>
+            <PORTMAP PHYSICAL="Interrupt_Address"/>
+            <PORTMAP PHYSICAL="Interrupt"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="microblaze_0_DLMB" NAME="DLMB" TYPE="MASTER">
+          <PORTMAPS>
+            <PORTMAP PHYSICAL="Data_Addr"/>
+            <PORTMAP PHYSICAL="D_AS"/>
+            <PORTMAP PHYSICAL="Byte_Enable"/>
+            <PORTMAP PHYSICAL="DCE"/>
+            <PORTMAP PHYSICAL="Data_Read"/>
+            <PORTMAP PHYSICAL="Read_Strobe"/>
+            <PORTMAP PHYSICAL="DReady"/>
+            <PORTMAP PHYSICAL="DUE"/>
+            <PORTMAP PHYSICAL="DWait"/>
+            <PORTMAP PHYSICAL="Data_Write"/>
+            <PORTMAP PHYSICAL="Write_Strobe"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="microblaze_0_ILMB" NAME="ILMB" TYPE="MASTER">
+          <PORTMAPS>
+            <PORTMAP PHYSICAL="Instr_Addr"/>
+            <PORTMAP PHYSICAL="I_AS"/>
+            <PORTMAP PHYSICAL="ICE"/>
+            <PORTMAP PHYSICAL="Instr"/>
+            <PORTMAP PHYSICAL="IFetch"/>
+            <PORTMAP PHYSICAL="IReady"/>
+            <PORTMAP PHYSICAL="IUE"/>
+            <PORTMAP PHYSICAL="IWAIT"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="microblaze_0_M_AXI_DP" NAME="M_AXI_DP" TYPE="MASTER">
+          <PORTMAPS>
+            <PORTMAP PHYSICAL="M_AXI_DP_ARADDR"/>
+            <PORTMAP PHYSICAL="M_AXI_DP_ARPROT"/>
+            <PORTMAP PHYSICAL="M_AXI_DP_ARREADY"/>
+            <PORTMAP PHYSICAL="M_AXI_DP_ARVALID"/>
+            <PORTMAP PHYSICAL="M_AXI_DP_AWADDR"/>
+            <PORTMAP PHYSICAL="M_AXI_DP_AWPROT"/>
+            <PORTMAP PHYSICAL="M_AXI_DP_AWREADY"/>
+            <PORTMAP PHYSICAL="M_AXI_DP_AWVALID"/>
+            <PORTMAP PHYSICAL="M_AXI_DP_BREADY"/>
+            <PORTMAP PHYSICAL="M_AXI_DP_BRESP"/>
+            <PORTMAP PHYSICAL="M_AXI_DP_BVALID"/>
+            <PORTMAP PHYSICAL="M_AXI_DP_RDATA"/>
+            <PORTMAP PHYSICAL="M_AXI_DP_RREADY"/>
+            <PORTMAP PHYSICAL="M_AXI_DP_RRESP"/>
+            <PORTMAP PHYSICAL="M_AXI_DP_RVALID"/>
+            <PORTMAP PHYSICAL="M_AXI_DP_WDATA"/>
+            <PORTMAP PHYSICAL="M_AXI_DP_WREADY"/>
+            <PORTMAP PHYSICAL="M_AXI_DP_WSTRB"/>
+            <PORTMAP PHYSICAL="M_AXI_DP_WVALID"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="microblaze_0_M_AXI_DC" NAME="M_AXI_DC" TYPE="MASTER">
+          <PORTMAPS>
+            <PORTMAP PHYSICAL="M_AXI_DC_ARADDR"/>
+            <PORTMAP PHYSICAL="M_AXI_DC_ARBURST"/>
+            <PORTMAP PHYSICAL="M_AXI_DC_ARCACHE"/>
+            <PORTMAP PHYSICAL="M_AXI_DC_ARID"/>
+            <PORTMAP PHYSICAL="M_AXI_DC_ARLEN"/>
+            <PORTMAP PHYSICAL="M_AXI_DC_ARLOCK"/>
+            <PORTMAP PHYSICAL="M_AXI_DC_ARPROT"/>
+            <PORTMAP PHYSICAL="M_AXI_DC_ARQOS"/>
+            <PORTMAP PHYSICAL="M_AXI_DC_ARREADY"/>
+            <PORTMAP PHYSICAL="M_AXI_DC_ARSIZE"/>
+            <PORTMAP PHYSICAL="M_AXI_DC_ARVALID"/>
+            <PORTMAP PHYSICAL="M_AXI_DC_AWADDR"/>
+            <PORTMAP PHYSICAL="M_AXI_DC_AWBURST"/>
+            <PORTMAP PHYSICAL="M_AXI_DC_AWCACHE"/>
+            <PORTMAP PHYSICAL="M_AXI_DC_AWID"/>
+            <PORTMAP PHYSICAL="M_AXI_DC_AWLEN"/>
+            <PORTMAP PHYSICAL="M_AXI_DC_AWLOCK"/>
+            <PORTMAP PHYSICAL="M_AXI_DC_AWPROT"/>
+            <PORTMAP PHYSICAL="M_AXI_DC_AWQOS"/>
+            <PORTMAP PHYSICAL="M_AXI_DC_AWREADY"/>
+            <PORTMAP PHYSICAL="M_AXI_DC_AWSIZE"/>
+            <PORTMAP PHYSICAL="M_AXI_DC_AWVALID"/>
+            <PORTMAP PHYSICAL="M_AXI_DC_BID"/>
+            <PORTMAP PHYSICAL="M_AXI_DC_BREADY"/>
+            <PORTMAP PHYSICAL="M_AXI_DC_BRESP"/>
+            <PORTMAP PHYSICAL="M_AXI_DC_BVALID"/>
+            <PORTMAP PHYSICAL="M_AXI_DC_RDATA"/>
+            <PORTMAP PHYSICAL="M_AXI_DC_RID"/>
+            <PORTMAP PHYSICAL="M_AXI_DC_RLAST"/>
+            <PORTMAP PHYSICAL="M_AXI_DC_RREADY"/>
+            <PORTMAP PHYSICAL="M_AXI_DC_RRESP"/>
+            <PORTMAP PHYSICAL="M_AXI_DC_RVALID"/>
+            <PORTMAP PHYSICAL="M_AXI_DC_WDATA"/>
+            <PORTMAP PHYSICAL="M_AXI_DC_WLAST"/>
+            <PORTMAP PHYSICAL="M_AXI_DC_WREADY"/>
+            <PORTMAP PHYSICAL="M_AXI_DC_WSTRB"/>
+            <PORTMAP PHYSICAL="M_AXI_DC_WVALID"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="microblaze_0_M_AXI_IC" NAME="M_AXI_IC" TYPE="MASTER">
+          <PORTMAPS>
+            <PORTMAP PHYSICAL="M_AXI_IC_ARADDR"/>
+            <PORTMAP PHYSICAL="M_AXI_IC_ARBURST"/>
+            <PORTMAP PHYSICAL="M_AXI_IC_ARCACHE"/>
+            <PORTMAP PHYSICAL="M_AXI_IC_ARID"/>
+            <PORTMAP PHYSICAL="M_AXI_IC_ARLEN"/>
+            <PORTMAP PHYSICAL="M_AXI_IC_ARLOCK"/>
+            <PORTMAP PHYSICAL="M_AXI_IC_ARPROT"/>
+            <PORTMAP PHYSICAL="M_AXI_IC_ARQOS"/>
+            <PORTMAP PHYSICAL="M_AXI_IC_ARREADY"/>
+            <PORTMAP PHYSICAL="M_AXI_IC_ARSIZE"/>
+            <PORTMAP PHYSICAL="M_AXI_IC_ARVALID"/>
+            <PORTMAP PHYSICAL="M_AXI_IC_AWADDR"/>
+            <PORTMAP PHYSICAL="M_AXI_IC_AWBURST"/>
+            <PORTMAP PHYSICAL="M_AXI_IC_AWCACHE"/>
+            <PORTMAP PHYSICAL="M_AXI_IC_AWID"/>
+            <PORTMAP PHYSICAL="M_AXI_IC_AWLEN"/>
+            <PORTMAP PHYSICAL="M_AXI_IC_AWLOCK"/>
+            <PORTMAP PHYSICAL="M_AXI_IC_AWPROT"/>
+            <PORTMAP PHYSICAL="M_AXI_IC_AWQOS"/>
+            <PORTMAP PHYSICAL="M_AXI_IC_AWREADY"/>
+            <PORTMAP PHYSICAL="M_AXI_IC_AWSIZE"/>
+            <PORTMAP PHYSICAL="M_AXI_IC_AWVALID"/>
+            <PORTMAP PHYSICAL="M_AXI_IC_BID"/>
+            <PORTMAP PHYSICAL="M_AXI_IC_BREADY"/>
+            <PORTMAP PHYSICAL="M_AXI_IC_BRESP"/>
+            <PORTMAP PHYSICAL="M_AXI_IC_BVALID"/>
+            <PORTMAP PHYSICAL="M_AXI_IC_RDATA"/>
+            <PORTMAP PHYSICAL="M_AXI_IC_RID"/>
+            <PORTMAP PHYSICAL="M_AXI_IC_RLAST"/>
+            <PORTMAP PHYSICAL="M_AXI_IC_RREADY"/>
+            <PORTMAP PHYSICAL="M_AXI_IC_RRESP"/>
+            <PORTMAP PHYSICAL="M_AXI_IC_RVALID"/>
+            <PORTMAP PHYSICAL="M_AXI_IC_WDATA"/>
+            <PORTMAP PHYSICAL="M_AXI_IC_WLAST"/>
+            <PORTMAP PHYSICAL="M_AXI_IC_WREADY"/>
+            <PORTMAP PHYSICAL="M_AXI_IC_WSTRB"/>
+            <PORTMAP PHYSICAL="M_AXI_IC_WVALID"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="mdm_1_MBDEBUG_0" NAME="DEBUG" TYPE="TARGET">
+          <PORTMAPS>
+            <PORTMAP PHYSICAL="Dbg_Capture"/>
+            <PORTMAP PHYSICAL="Dbg_Clk"/>
+            <PORTMAP PHYSICAL="Dbg_Reg_En"/>
+            <PORTMAP PHYSICAL="Debug_Rst"/>
+            <PORTMAP PHYSICAL="Dbg_Shift"/>
+            <PORTMAP PHYSICAL="Dbg_TDI"/>
+            <PORTMAP PHYSICAL="Dbg_TDO"/>
+            <PORTMAP PHYSICAL="Dbg_Update"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" NAME="TRACE" TYPE="INITIATOR">
+          <PORTMAPS>
+            <PORTMAP PHYSICAL="Trace_Data_Access"/>
+            <PORTMAP PHYSICAL="Trace_Data_Address"/>
+            <PORTMAP PHYSICAL="Trace_Data_Byte_Enable"/>
+            <PORTMAP PHYSICAL="Trace_Data_Read"/>
+            <PORTMAP PHYSICAL="Trace_Data_Write"/>
+            <PORTMAP PHYSICAL="Trace_Data_Write_Value"/>
+            <PORTMAP PHYSICAL="Trace_DCache_Hit"/>
+            <PORTMAP PHYSICAL="Trace_DCache_Rdy"/>
+            <PORTMAP PHYSICAL="Trace_DCache_Read"/>
+            <PORTMAP PHYSICAL="Trace_DCache_Req"/>
+            <PORTMAP PHYSICAL="Trace_Delay_Slot"/>
+            <PORTMAP PHYSICAL="Trace_EX_PipeRun"/>
+            <PORTMAP PHYSICAL="Trace_Exception_Kind"/>
+            <PORTMAP PHYSICAL="Trace_Exception_Taken"/>
+            <PORTMAP PHYSICAL="Trace_ICache_Hit"/>
+            <PORTMAP PHYSICAL="Trace_ICache_Rdy"/>
+            <PORTMAP PHYSICAL="Trace_ICache_Req"/>
+            <PORTMAP PHYSICAL="Trace_Instruction"/>
+            <PORTMAP PHYSICAL="Trace_Jump_Hit"/>
+            <PORTMAP PHYSICAL="Trace_Jump_Taken"/>
+            <PORTMAP PHYSICAL="Trace_MB_Halted"/>
+            <PORTMAP PHYSICAL="Trace_MEM_PipeRun"/>
+            <PORTMAP PHYSICAL="Trace_MSR_Reg"/>
+            <PORTMAP PHYSICAL="Trace_New_Reg_Value"/>
+            <PORTMAP PHYSICAL="Trace_OF_PipeRun"/>
+            <PORTMAP PHYSICAL="Trace_PC"/>
+            <PORTMAP PHYSICAL="Trace_PID_Reg"/>
+            <PORTMAP PHYSICAL="Trace_Reg_Addr"/>
+            <PORTMAP PHYSICAL="Trace_Reg_Write"/>
+            <PORTMAP PHYSICAL="Trace_Valid_Instr"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+      </BUSINTERFACES>
+      <MEMORYMAP>
+        <MEMRANGE ADDRESSBLOCK="Mem" BASENAME="C_BASEADDR" BASEVALUE="0x00000000" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x0003FFFF" INSTANCE="microblaze_0_local_memory_dlmb_bram_if_cntlr" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" MEMTYPE="MEMORY"/>
+        <MEMRANGE ADDRESSBLOCK="Mem" BASENAME="C_BASEADDR" BASEVALUE="0x00000000" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x0003FFFF" INSTANCE="microblaze_0_local_memory_ilmb_bram_if_cntlr" IS_DATA="FALSE" IS_INSTRUCTION="TRUE" MEMTYPE="MEMORY"/>
+        <MEMRANGE ADDRESSBLOCK="Reg" BASENAME="C_BASEADDR" BASEVALUE="0x40000000" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4000FFFF" INSTANCE="axi_gpio_0" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" MEMTYPE="REGISTER"/>
+        <MEMRANGE ADDRESSBLOCK="Reg" BASENAME="C_BASEADDR" BASEVALUE="0x40600000" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4060FFFF" INSTANCE="axi_uartlite_0" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" MEMTYPE="REGISTER"/>
+        <MEMRANGE ADDRESSBLOCK="Reg" BASENAME="C_BASEADDR" BASEVALUE="0x40E00000" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x40E0FFFF" INSTANCE="axi_ethernetlite_0" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" MEMTYPE="REGISTER"/>
+        <MEMRANGE ADDRESSBLOCK="Reg" BASENAME="C_BASEADDR" BASEVALUE="0x41200000" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4120FFFF" INSTANCE="axi_intc_0" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" MEMTYPE="REGISTER"/>
+        <MEMRANGE ADDRESSBLOCK="Reg" BASENAME="C_BASEADDR" BASEVALUE="0x41C00000" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x41C0FFFF" INSTANCE="axi_timer_0" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" MEMTYPE="REGISTER"/>
+        <MEMRANGE ADDRESSBLOCK="memaddr" BASENAME="C_BASEADDR" BASEVALUE="0x80000000" HIGHNAME="C_HIGHADDR" HIGHVALUE="0xBFFFFFFF" INSTANCE="mig_7series_0" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" MEMTYPE="MEMORY"/>
+        <MEMRANGE ADDRESSBLOCK="memaddr" BASENAME="C_BASEADDR" BASEVALUE="0x80000000" HIGHNAME="C_HIGHADDR" HIGHVALUE="0xBFFFFFFF" INSTANCE="mig_7series_0" IS_DATA="FALSE" IS_INSTRUCTION="TRUE" MEMTYPE="MEMORY"/>
+      </MEMORYMAP>
+      <PERIPHERALS>
+        <PERIPHERAL INSTANCE="microblaze_0_local_memory_dlmb_bram_if_cntlr"/>
+        <PERIPHERAL INSTANCE="microblaze_0_local_memory_ilmb_bram_if_cntlr"/>
+        <PERIPHERAL INSTANCE="axi_gpio_0"/>
+        <PERIPHERAL INSTANCE="axi_uartlite_0"/>
+        <PERIPHERAL INSTANCE="axi_ethernetlite_0"/>
+        <PERIPHERAL INSTANCE="axi_intc_0"/>
+        <PERIPHERAL INSTANCE="axi_timer_0"/>
+        <PERIPHERAL INSTANCE="mig_7series_0"/>
+      </PERIPHERALS>
+    </MODULE>
+    <MODULE FULLNAME="/microblaze_0_axi_periph" HWVERSION="2.1" INSTANCE="microblaze_0_axi_periph" IPTYPE="BUS" IS_ENABLE="1" MODCLASS="BUS" MODTYPE="axi_interconnect" VLNV="xilinx.com:ip:axi_interconnect:2.1">
+      <DOCUMENTS>
+        <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_interconnect;v=v2_1;d=pg059-axi-interconnect.pdf"/>
+      </DOCUMENTS>
+      <PARAMETERS>
+        <PARAMETER NAME="NUM_SI" VALUE="1"/>
+        <PARAMETER NAME="NUM_MI" VALUE="5"/>
+        <PARAMETER NAME="STRATEGY" VALUE="0"/>
+        <PARAMETER NAME="ENABLE_ADVANCED_OPTIONS" VALUE="0"/>
+        <PARAMETER NAME="ENABLE_PROTOCOL_CHECKERS" VALUE="0"/>
+        <PARAMETER NAME="XBAR_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="PCHK_WAITS" VALUE="0"/>
+        <PARAMETER NAME="PCHK_MAX_RD_BURSTS" VALUE="2"/>
+        <PARAMETER NAME="PCHK_MAX_WR_BURSTS" VALUE="2"/>
+        <PARAMETER NAME="SYNCHRONIZATION_STAGES" VALUE="2"/>
+        <PARAMETER NAME="M00_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M01_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M02_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M03_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M04_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M05_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M06_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M07_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M08_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M09_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M10_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M11_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M12_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M13_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M14_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M15_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M16_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M17_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M18_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M19_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M20_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M21_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M22_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M23_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M24_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M25_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M26_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M27_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M28_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M29_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M30_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M31_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M32_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M33_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M34_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M35_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M36_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M37_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M38_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M39_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M40_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M41_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M42_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M43_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M44_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M45_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M46_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M47_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M48_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M49_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M50_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M51_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M52_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M53_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M54_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M55_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M56_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M57_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M58_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M59_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M60_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M61_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M62_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M63_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M00_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M01_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M02_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M03_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M04_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M05_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M06_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M07_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M08_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M09_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M10_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M11_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M12_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M13_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M14_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M15_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M16_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M17_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M18_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M19_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M20_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M21_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M22_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M23_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M24_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M25_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M26_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M27_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M28_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M29_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M30_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M31_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M32_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M33_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M34_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M35_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M36_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M37_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M38_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M39_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M40_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M41_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M42_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M43_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M44_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M45_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M46_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M47_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M48_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M49_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M50_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M51_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M52_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M53_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M54_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M55_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M56_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M57_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M58_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M59_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M60_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M61_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M62_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M63_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="S00_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="S01_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="S02_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="S03_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="S04_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="S05_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="S06_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="S07_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="S08_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="S09_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="S10_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="S11_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="S12_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="S13_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="S14_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="S15_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="S00_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="S01_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="S02_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="S03_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="S04_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="S05_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="S06_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="S07_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="S08_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="S09_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="S10_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="S11_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="S12_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="S13_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="S14_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="S15_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M00_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M01_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M02_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M03_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M04_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M05_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M06_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M07_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M08_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M09_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M10_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M11_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M12_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M13_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M14_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M15_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M16_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M17_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M18_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M19_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M20_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M21_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M22_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M23_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M24_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M25_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M26_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M27_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M28_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M29_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M30_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M31_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M32_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M33_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M34_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M35_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M36_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M37_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M38_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M39_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M40_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M41_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M42_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M43_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M44_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M45_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M46_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M47_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M48_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M49_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M50_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M51_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M52_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M53_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M54_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M55_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M56_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M57_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M58_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M59_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M60_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M61_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M62_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M63_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M00_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M01_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M02_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M03_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M04_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M05_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M06_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M07_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M08_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M09_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M10_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M11_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M12_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M13_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M14_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M15_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M16_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M17_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M18_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M19_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M20_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M21_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M22_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M23_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M24_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M25_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M26_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M27_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M28_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M29_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M30_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M31_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M32_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M33_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M34_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M35_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M36_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M37_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M38_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M39_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M40_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M41_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M42_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M43_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M44_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M45_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M46_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M47_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M48_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M49_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M50_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M51_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M52_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M53_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M54_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M55_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M56_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M57_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M58_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M59_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M60_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M61_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M62_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M63_SECURE" VALUE="0"/>
+        <PARAMETER NAME="Component_Name" VALUE="base_microblaze_design_microblaze_0_axi_periph_0"/>
+        <PARAMETER NAME="EDK_IPTYPE" VALUE="BUS"/>
+      </PARAMETERS>
+      <PORTS>
+        <PORT DIR="I" NAME="ACLK" SIGIS="clk" SIGNAME="mig_7series_0_ui_clk">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="mig_7series_0" PORT="ui_clk"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="0" NAME="ARESETN" RIGHT="0" SIGIS="rst" SIGNAME="rst_clk_wiz_1_100M_interconnect_aresetn">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="rst_clk_wiz_1_100M" PORT="interconnect_aresetn"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="S00_ACLK" SIGIS="clk" SIGNAME="mig_7series_0_ui_clk">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="mig_7series_0" PORT="ui_clk"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="0" NAME="S00_ARESETN" RIGHT="0" SIGIS="rst" SIGNAME="rst_clk_wiz_1_100M_peripheral_aresetn">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="rst_clk_wiz_1_100M" PORT="peripheral_aresetn"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M00_ACLK" SIGIS="clk" SIGNAME="mig_7series_0_ui_clk">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="mig_7series_0" PORT="ui_clk"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="0" NAME="M00_ARESETN" RIGHT="0" SIGIS="rst" SIGNAME="rst_clk_wiz_1_100M_peripheral_aresetn">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="rst_clk_wiz_1_100M" PORT="peripheral_aresetn"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M01_ACLK" SIGIS="clk" SIGNAME="mig_7series_0_ui_clk">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="mig_7series_0" PORT="ui_clk"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="0" NAME="M01_ARESETN" RIGHT="0" SIGIS="rst" SIGNAME="rst_clk_wiz_1_100M_peripheral_aresetn">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="rst_clk_wiz_1_100M" PORT="peripheral_aresetn"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M02_ACLK" SIGIS="clk" SIGNAME="mig_7series_0_ui_clk">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="mig_7series_0" PORT="ui_clk"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="0" NAME="M02_ARESETN" RIGHT="0" SIGIS="rst" SIGNAME="rst_clk_wiz_1_100M_peripheral_aresetn">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="rst_clk_wiz_1_100M" PORT="peripheral_aresetn"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M03_ACLK" SIGIS="clk" SIGNAME="mig_7series_0_ui_clk">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="mig_7series_0" PORT="ui_clk"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="0" NAME="M03_ARESETN" RIGHT="0" SIGIS="rst" SIGNAME="rst_clk_wiz_1_100M_peripheral_aresetn">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="rst_clk_wiz_1_100M" PORT="peripheral_aresetn"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M04_ACLK" SIGIS="clk" SIGNAME="mig_7series_0_ui_clk">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="mig_7series_0" PORT="ui_clk"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="0" NAME="M04_ARESETN" RIGHT="0" SIGIS="rst" SIGNAME="rst_clk_wiz_1_100M_peripheral_aresetn">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="rst_clk_wiz_1_100M" PORT="peripheral_aresetn"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="31" NAME="S00_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_M_AXI_DP_ARADDR">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DP_ARADDR"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="2" NAME="S00_AXI_arprot" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_M_AXI_DP_ARPROT">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DP_ARPROT"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="0" NAME="S00_AXI_arready" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_M_AXI_DP_ARREADY">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DP_ARREADY"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="0" NAME="S00_AXI_arvalid" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_M_AXI_DP_ARVALID">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DP_ARVALID"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="31" NAME="S00_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_M_AXI_DP_AWADDR">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DP_AWADDR"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="2" NAME="S00_AXI_awprot" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_M_AXI_DP_AWPROT">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DP_AWPROT"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="0" NAME="S00_AXI_awready" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_M_AXI_DP_AWREADY">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DP_AWREADY"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="0" NAME="S00_AXI_awvalid" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_M_AXI_DP_AWVALID">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DP_AWVALID"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="0" NAME="S00_AXI_bready" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_M_AXI_DP_BREADY">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DP_BREADY"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="1" NAME="S00_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_M_AXI_DP_BRESP">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DP_BRESP"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="0" NAME="S00_AXI_bvalid" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_M_AXI_DP_BVALID">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DP_BVALID"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="31" NAME="S00_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_M_AXI_DP_RDATA">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DP_RDATA"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="0" NAME="S00_AXI_rready" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_M_AXI_DP_RREADY">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DP_RREADY"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="1" NAME="S00_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_M_AXI_DP_RRESP">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DP_RRESP"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="0" NAME="S00_AXI_rvalid" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_M_AXI_DP_RVALID">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DP_RVALID"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="31" NAME="S00_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_M_AXI_DP_WDATA">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DP_WDATA"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="0" NAME="S00_AXI_wready" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_M_AXI_DP_WREADY">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DP_WREADY"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="3" NAME="S00_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_M_AXI_DP_WSTRB">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DP_WSTRB"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="0" NAME="S00_AXI_wvalid" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_M_AXI_DP_WVALID">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DP_WVALID"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="3" NAME="M00_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_uartlite_0_s_axi_araddr">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_uartlite_0" PORT="s_axi_araddr"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="0" NAME="M00_AXI_arready" RIGHT="0" SIGIS="undef" SIGNAME="axi_uartlite_0_s_axi_arready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_uartlite_0" PORT="s_axi_arready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="0" NAME="M00_AXI_arvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_uartlite_0_s_axi_arvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_uartlite_0" PORT="s_axi_arvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="3" NAME="M00_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_uartlite_0_s_axi_awaddr">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_uartlite_0" PORT="s_axi_awaddr"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="0" NAME="M00_AXI_awready" RIGHT="0" SIGIS="undef" SIGNAME="axi_uartlite_0_s_axi_awready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_uartlite_0" PORT="s_axi_awready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="0" NAME="M00_AXI_awvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_uartlite_0_s_axi_awvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_uartlite_0" PORT="s_axi_awvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="0" NAME="M00_AXI_bready" RIGHT="0" SIGIS="undef" SIGNAME="axi_uartlite_0_s_axi_bready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_uartlite_0" PORT="s_axi_bready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="1" NAME="M00_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_uartlite_0_s_axi_bresp">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_uartlite_0" PORT="s_axi_bresp"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="0" NAME="M00_AXI_bvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_uartlite_0_s_axi_bvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_uartlite_0" PORT="s_axi_bvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="31" NAME="M00_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_uartlite_0_s_axi_rdata">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_uartlite_0" PORT="s_axi_rdata"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="0" NAME="M00_AXI_rready" RIGHT="0" SIGIS="undef" SIGNAME="axi_uartlite_0_s_axi_rready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_uartlite_0" PORT="s_axi_rready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="1" NAME="M00_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_uartlite_0_s_axi_rresp">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_uartlite_0" PORT="s_axi_rresp"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="0" NAME="M00_AXI_rvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_uartlite_0_s_axi_rvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_uartlite_0" PORT="s_axi_rvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="31" NAME="M00_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_uartlite_0_s_axi_wdata">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_uartlite_0" PORT="s_axi_wdata"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="0" NAME="M00_AXI_wready" RIGHT="0" SIGIS="undef" SIGNAME="axi_uartlite_0_s_axi_wready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_uartlite_0" PORT="s_axi_wready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="3" NAME="M00_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axi_uartlite_0_s_axi_wstrb">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_uartlite_0" PORT="s_axi_wstrb"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="0" NAME="M00_AXI_wvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_uartlite_0_s_axi_wvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_uartlite_0" PORT="s_axi_wvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="8" NAME="M01_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_araddr">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_gpio_0" PORT="s_axi_araddr"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="0" NAME="M01_AXI_arready" RIGHT="0" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_arready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_gpio_0" PORT="s_axi_arready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="0" NAME="M01_AXI_arvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_arvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_gpio_0" PORT="s_axi_arvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="8" NAME="M01_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_awaddr">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_gpio_0" PORT="s_axi_awaddr"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="0" NAME="M01_AXI_awready" RIGHT="0" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_awready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_gpio_0" PORT="s_axi_awready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="0" NAME="M01_AXI_awvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_awvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_gpio_0" PORT="s_axi_awvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="0" NAME="M01_AXI_bready" RIGHT="0" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_bready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_gpio_0" PORT="s_axi_bready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="1" NAME="M01_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_bresp">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_gpio_0" PORT="s_axi_bresp"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="0" NAME="M01_AXI_bvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_bvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_gpio_0" PORT="s_axi_bvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="31" NAME="M01_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_rdata">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_gpio_0" PORT="s_axi_rdata"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="0" NAME="M01_AXI_rready" RIGHT="0" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_rready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_gpio_0" PORT="s_axi_rready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="1" NAME="M01_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_rresp">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_gpio_0" PORT="s_axi_rresp"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="0" NAME="M01_AXI_rvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_rvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_gpio_0" PORT="s_axi_rvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="31" NAME="M01_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_wdata">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_gpio_0" PORT="s_axi_wdata"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="0" NAME="M01_AXI_wready" RIGHT="0" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_wready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_gpio_0" PORT="s_axi_wready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="3" NAME="M01_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_wstrb">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_gpio_0" PORT="s_axi_wstrb"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="0" NAME="M01_AXI_wvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_wvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_gpio_0" PORT="s_axi_wvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="4" NAME="M02_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_timer_0_s_axi_araddr">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_timer_0" PORT="s_axi_araddr"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M02_AXI_arready" SIGIS="undef" SIGNAME="axi_timer_0_s_axi_arready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_timer_0" PORT="s_axi_arready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="M02_AXI_arvalid" SIGIS="undef" SIGNAME="axi_timer_0_s_axi_arvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_timer_0" PORT="s_axi_arvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="4" NAME="M02_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_timer_0_s_axi_awaddr">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_timer_0" PORT="s_axi_awaddr"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M02_AXI_awready" SIGIS="undef" SIGNAME="axi_timer_0_s_axi_awready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_timer_0" PORT="s_axi_awready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="M02_AXI_awvalid" SIGIS="undef" SIGNAME="axi_timer_0_s_axi_awvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_timer_0" PORT="s_axi_awvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="M02_AXI_bready" SIGIS="undef" SIGNAME="axi_timer_0_s_axi_bready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_timer_0" PORT="s_axi_bready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="1" NAME="M02_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_timer_0_s_axi_bresp">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_timer_0" PORT="s_axi_bresp"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M02_AXI_bvalid" SIGIS="undef" SIGNAME="axi_timer_0_s_axi_bvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_timer_0" PORT="s_axi_bvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="31" NAME="M02_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_timer_0_s_axi_rdata">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_timer_0" PORT="s_axi_rdata"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="M02_AXI_rready" SIGIS="undef" SIGNAME="axi_timer_0_s_axi_rready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_timer_0" PORT="s_axi_rready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="1" NAME="M02_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_timer_0_s_axi_rresp">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_timer_0" PORT="s_axi_rresp"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M02_AXI_rvalid" SIGIS="undef" SIGNAME="axi_timer_0_s_axi_rvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_timer_0" PORT="s_axi_rvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="31" NAME="M02_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_timer_0_s_axi_wdata">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_timer_0" PORT="s_axi_wdata"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M02_AXI_wready" SIGIS="undef" SIGNAME="axi_timer_0_s_axi_wready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_timer_0" PORT="s_axi_wready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="3" NAME="M02_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axi_timer_0_s_axi_wstrb">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_timer_0" PORT="s_axi_wstrb"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="M02_AXI_wvalid" SIGIS="undef" SIGNAME="axi_timer_0_s_axi_wvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_timer_0" PORT="s_axi_wvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="8" NAME="M03_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_araddr">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_araddr"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M03_AXI_arready" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_arready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_arready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="M03_AXI_arvalid" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_arvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_arvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="8" NAME="M03_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_awaddr">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_awaddr"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M03_AXI_awready" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_awready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_awready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="M03_AXI_awvalid" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_awvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_awvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="M03_AXI_bready" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_bready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_bready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="1" NAME="M03_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_bresp">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_bresp"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M03_AXI_bvalid" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_bvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_bvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="31" NAME="M03_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_rdata">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_rdata"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="M03_AXI_rready" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_rready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_rready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="1" NAME="M03_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_rresp">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_rresp"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M03_AXI_rvalid" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_rvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_rvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="31" NAME="M03_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_wdata">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_wdata"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M03_AXI_wready" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_wready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_wready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="3" NAME="M03_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_wstrb">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_wstrb"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="M03_AXI_wvalid" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_wvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_wvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="12" NAME="M04_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_ethernetlite_0_s_axi_araddr">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_ethernetlite_0" PORT="s_axi_araddr"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M04_AXI_arready" SIGIS="undef" SIGNAME="axi_ethernetlite_0_s_axi_arready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_ethernetlite_0" PORT="s_axi_arready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="M04_AXI_arvalid" SIGIS="undef" SIGNAME="axi_ethernetlite_0_s_axi_arvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_ethernetlite_0" PORT="s_axi_arvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="12" NAME="M04_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_ethernetlite_0_s_axi_awaddr">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_ethernetlite_0" PORT="s_axi_awaddr"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M04_AXI_awready" SIGIS="undef" SIGNAME="axi_ethernetlite_0_s_axi_awready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_ethernetlite_0" PORT="s_axi_awready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="M04_AXI_awvalid" SIGIS="undef" SIGNAME="axi_ethernetlite_0_s_axi_awvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_ethernetlite_0" PORT="s_axi_awvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="M04_AXI_bready" SIGIS="undef" SIGNAME="axi_ethernetlite_0_s_axi_bready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_ethernetlite_0" PORT="s_axi_bready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="1" NAME="M04_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_ethernetlite_0_s_axi_bresp">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_ethernetlite_0" PORT="s_axi_bresp"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M04_AXI_bvalid" SIGIS="undef" SIGNAME="axi_ethernetlite_0_s_axi_bvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_ethernetlite_0" PORT="s_axi_bvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="31" NAME="M04_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_ethernetlite_0_s_axi_rdata">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_ethernetlite_0" PORT="s_axi_rdata"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="M04_AXI_rready" SIGIS="undef" SIGNAME="axi_ethernetlite_0_s_axi_rready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_ethernetlite_0" PORT="s_axi_rready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="1" NAME="M04_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_ethernetlite_0_s_axi_rresp">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_ethernetlite_0" PORT="s_axi_rresp"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M04_AXI_rvalid" SIGIS="undef" SIGNAME="axi_ethernetlite_0_s_axi_rvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_ethernetlite_0" PORT="s_axi_rvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="31" NAME="M04_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_ethernetlite_0_s_axi_wdata">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_ethernetlite_0" PORT="s_axi_wdata"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M04_AXI_wready" SIGIS="undef" SIGNAME="axi_ethernetlite_0_s_axi_wready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_ethernetlite_0" PORT="s_axi_wready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="3" NAME="M04_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axi_ethernetlite_0_s_axi_wstrb">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_ethernetlite_0" PORT="s_axi_wstrb"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="M04_AXI_wvalid" SIGIS="undef" SIGNAME="axi_ethernetlite_0_s_axi_wvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_ethernetlite_0" PORT="s_axi_wvalid"/>
+          </CONNECTIONS>
+        </PORT>
+      </PORTS>
+      <BUSINTERFACES>
+        <BUSINTERFACE BUSNAME="microblaze_0_M_AXI_DP" NAME="S00_AXI" TYPE="SLAVE">
+          <PORTMAPS>
+            <PORTMAP PHYSICAL="S00_AXI_araddr"/>
+            <PORTMAP PHYSICAL="S00_AXI_arprot"/>
+            <PORTMAP PHYSICAL="S00_AXI_arready"/>
+            <PORTMAP PHYSICAL="S00_AXI_arvalid"/>
+            <PORTMAP PHYSICAL="S00_AXI_awaddr"/>
+            <PORTMAP PHYSICAL="S00_AXI_awprot"/>
+            <PORTMAP PHYSICAL="S00_AXI_awready"/>
+            <PORTMAP PHYSICAL="S00_AXI_awvalid"/>
+            <PORTMAP PHYSICAL="S00_AXI_bready"/>
+            <PORTMAP PHYSICAL="S00_AXI_bresp"/>
+            <PORTMAP PHYSICAL="S00_AXI_bvalid"/>
+            <PORTMAP PHYSICAL="S00_AXI_rdata"/>
+            <PORTMAP PHYSICAL="S00_AXI_rready"/>
+            <PORTMAP PHYSICAL="S00_AXI_rresp"/>
+            <PORTMAP PHYSICAL="S00_AXI_rvalid"/>
+            <PORTMAP PHYSICAL="S00_AXI_wdata"/>
+            <PORTMAP PHYSICAL="S00_AXI_wready"/>
+            <PORTMAP PHYSICAL="S00_AXI_wstrb"/>
+            <PORTMAP PHYSICAL="S00_AXI_wvalid"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="microblaze_0_axi_periph_M00_AXI" NAME="M00_AXI" TYPE="MASTER">
+          <PORTMAPS>
+            <PORTMAP PHYSICAL="M00_AXI_araddr"/>
+            <PORTMAP PHYSICAL="M00_AXI_arready"/>
+            <PORTMAP PHYSICAL="M00_AXI_arvalid"/>
+            <PORTMAP PHYSICAL="M00_AXI_awaddr"/>
+            <PORTMAP PHYSICAL="M00_AXI_awready"/>
+            <PORTMAP PHYSICAL="M00_AXI_awvalid"/>
+            <PORTMAP PHYSICAL="M00_AXI_bready"/>
+            <PORTMAP PHYSICAL="M00_AXI_bresp"/>
+            <PORTMAP PHYSICAL="M00_AXI_bvalid"/>
+            <PORTMAP PHYSICAL="M00_AXI_rdata"/>
+            <PORTMAP PHYSICAL="M00_AXI_rready"/>
+            <PORTMAP PHYSICAL="M00_AXI_rresp"/>
+            <PORTMAP PHYSICAL="M00_AXI_rvalid"/>
+            <PORTMAP PHYSICAL="M00_AXI_wdata"/>
+            <PORTMAP PHYSICAL="M00_AXI_wready"/>
+            <PORTMAP PHYSICAL="M00_AXI_wstrb"/>
+            <PORTMAP PHYSICAL="M00_AXI_wvalid"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="microblaze_0_axi_periph_M01_AXI" NAME="M01_AXI" TYPE="MASTER">
+          <PORTMAPS>
+            <PORTMAP PHYSICAL="M01_AXI_araddr"/>
+            <PORTMAP PHYSICAL="M01_AXI_arready"/>
+            <PORTMAP PHYSICAL="M01_AXI_arvalid"/>
+            <PORTMAP PHYSICAL="M01_AXI_awaddr"/>
+            <PORTMAP PHYSICAL="M01_AXI_awready"/>
+            <PORTMAP PHYSICAL="M01_AXI_awvalid"/>
+            <PORTMAP PHYSICAL="M01_AXI_bready"/>
+            <PORTMAP PHYSICAL="M01_AXI_bresp"/>
+            <PORTMAP PHYSICAL="M01_AXI_bvalid"/>
+            <PORTMAP PHYSICAL="M01_AXI_rdata"/>
+            <PORTMAP PHYSICAL="M01_AXI_rready"/>
+            <PORTMAP PHYSICAL="M01_AXI_rresp"/>
+            <PORTMAP PHYSICAL="M01_AXI_rvalid"/>
+            <PORTMAP PHYSICAL="M01_AXI_wdata"/>
+            <PORTMAP PHYSICAL="M01_AXI_wready"/>
+            <PORTMAP PHYSICAL="M01_AXI_wstrb"/>
+            <PORTMAP PHYSICAL="M01_AXI_wvalid"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="microblaze_0_axi_periph_M02_AXI" NAME="M02_AXI" TYPE="MASTER">
+          <PORTMAPS>
+            <PORTMAP PHYSICAL="M02_AXI_araddr"/>
+            <PORTMAP PHYSICAL="M02_AXI_arready"/>
+            <PORTMAP PHYSICAL="M02_AXI_arvalid"/>
+            <PORTMAP PHYSICAL="M02_AXI_awaddr"/>
+            <PORTMAP PHYSICAL="M02_AXI_awready"/>
+            <PORTMAP PHYSICAL="M02_AXI_awvalid"/>
+            <PORTMAP PHYSICAL="M02_AXI_bready"/>
+            <PORTMAP PHYSICAL="M02_AXI_bresp"/>
+            <PORTMAP PHYSICAL="M02_AXI_bvalid"/>
+            <PORTMAP PHYSICAL="M02_AXI_rdata"/>
+            <PORTMAP PHYSICAL="M02_AXI_rready"/>
+            <PORTMAP PHYSICAL="M02_AXI_rresp"/>
+            <PORTMAP PHYSICAL="M02_AXI_rvalid"/>
+            <PORTMAP PHYSICAL="M02_AXI_wdata"/>
+            <PORTMAP PHYSICAL="M02_AXI_wready"/>
+            <PORTMAP PHYSICAL="M02_AXI_wstrb"/>
+            <PORTMAP PHYSICAL="M02_AXI_wvalid"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="microblaze_0_axi_periph_M03_AXI" NAME="M03_AXI" TYPE="MASTER">
+          <PORTMAPS>
+            <PORTMAP PHYSICAL="M03_AXI_araddr"/>
+            <PORTMAP PHYSICAL="M03_AXI_arready"/>
+            <PORTMAP PHYSICAL="M03_AXI_arvalid"/>
+            <PORTMAP PHYSICAL="M03_AXI_awaddr"/>
+            <PORTMAP PHYSICAL="M03_AXI_awready"/>
+            <PORTMAP PHYSICAL="M03_AXI_awvalid"/>
+            <PORTMAP PHYSICAL="M03_AXI_bready"/>
+            <PORTMAP PHYSICAL="M03_AXI_bresp"/>
+            <PORTMAP PHYSICAL="M03_AXI_bvalid"/>
+            <PORTMAP PHYSICAL="M03_AXI_rdata"/>
+            <PORTMAP PHYSICAL="M03_AXI_rready"/>
+            <PORTMAP PHYSICAL="M03_AXI_rresp"/>
+            <PORTMAP PHYSICAL="M03_AXI_rvalid"/>
+            <PORTMAP PHYSICAL="M03_AXI_wdata"/>
+            <PORTMAP PHYSICAL="M03_AXI_wready"/>
+            <PORTMAP PHYSICAL="M03_AXI_wstrb"/>
+            <PORTMAP PHYSICAL="M03_AXI_wvalid"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="microblaze_0_axi_periph_M04_AXI" NAME="M04_AXI" TYPE="MASTER">
+          <PORTMAPS>
+            <PORTMAP PHYSICAL="M04_AXI_araddr"/>
+            <PORTMAP PHYSICAL="M04_AXI_arready"/>
+            <PORTMAP PHYSICAL="M04_AXI_arvalid"/>
+            <PORTMAP PHYSICAL="M04_AXI_awaddr"/>
+            <PORTMAP PHYSICAL="M04_AXI_awready"/>
+            <PORTMAP PHYSICAL="M04_AXI_awvalid"/>
+            <PORTMAP PHYSICAL="M04_AXI_bready"/>
+            <PORTMAP PHYSICAL="M04_AXI_bresp"/>
+            <PORTMAP PHYSICAL="M04_AXI_bvalid"/>
+            <PORTMAP PHYSICAL="M04_AXI_rdata"/>
+            <PORTMAP PHYSICAL="M04_AXI_rready"/>
+            <PORTMAP PHYSICAL="M04_AXI_rresp"/>
+            <PORTMAP PHYSICAL="M04_AXI_rvalid"/>
+            <PORTMAP PHYSICAL="M04_AXI_wdata"/>
+            <PORTMAP PHYSICAL="M04_AXI_wready"/>
+            <PORTMAP PHYSICAL="M04_AXI_wstrb"/>
+            <PORTMAP PHYSICAL="M04_AXI_wvalid"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+      </BUSINTERFACES>
+    </MODULE>
+    <MODULE FULLNAME="/microblaze_0_local_memory/dlmb_bram_if_cntlr" HWVERSION="4.0" INSTANCE="microblaze_0_local_memory_dlmb_bram_if_cntlr" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="MEMORY_CNTLR" MODTYPE="lmb_bram_if_cntlr" VLNV="xilinx.com:ip:lmb_bram_if_cntlr:4.0">
+      <DOCUMENTS>
+        <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=lmb_bram_if_cntlr;v=v4_0;d=pg112-lmb-bram-if-cntlr.pdf"/>
+      </DOCUMENTS>
+      <PARAMETERS>
+        <PARAMETER NAME="C_FAMILY" VALUE="kintex7"/>
+        <PARAMETER NAME="C_NUM_LMB" VALUE="1"/>
+        <PARAMETER NAME="C_MASK" VALUE="0xc0000000"/>
+        <PARAMETER NAME="C_MASK1" VALUE="0x00800000"/>
+        <PARAMETER NAME="C_MASK2" VALUE="0x00800000"/>
+        <PARAMETER NAME="C_MASK3" VALUE="0x00800000"/>
+        <PARAMETER NAME="C_LMB_AWIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_LMB_DWIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_ECC" VALUE="0"/>
+        <PARAMETER NAME="C_INTERCONNECT" VALUE="0"/>
+        <PARAMETER NAME="C_FAULT_INJECT" VALUE="0"/>
+        <PARAMETER NAME="C_CE_FAILING_REGISTERS" VALUE="0"/>
+        <PARAMETER NAME="C_UE_FAILING_REGISTERS" VALUE="0"/>
+        <PARAMETER NAME="C_ECC_STATUS_REGISTERS" VALUE="0"/>
+        <PARAMETER NAME="C_ECC_ONOFF_REGISTER" VALUE="0"/>
+        <PARAMETER NAME="C_ECC_ONOFF_RESET_VALUE" VALUE="1"/>
+        <PARAMETER NAME="C_CE_COUNTER_WIDTH" VALUE="0"/>
+        <PARAMETER NAME="C_WRITE_ACCESS" VALUE="2"/>
+        <PARAMETER NAME="C_S_AXI_CTRL_ADDR_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_S_AXI_CTRL_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_S_AXI_CTRL_ACLK_FREQ_HZ" VALUE="100000000"/>
+        <PARAMETER NAME="C_S_AXI_CTRL_PROTOCOL" VALUE="AXI4LITE"/>
+        <PARAMETER NAME="Component_Name" VALUE="base_microblaze_design_dlmb_bram_if_cntlr_0"/>
+        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
+        <PARAMETER NAME="EDK_SPECIAL" VALUE="BRAM_CTRL"/>
+        <PARAMETER NAME="C_BASEADDR" VALUE="0x00000000"/>
+        <PARAMETER NAME="C_HIGHADDR" VALUE="0x0003FFFF"/>
+      </PARAMETERS>
+      <PORTS>
+        <PORT CLKFREQUENCY="100000000" DIR="I" NAME="LMB_Clk" SIGIS="clk" SIGNAME="mig_7series_0_ui_clk">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="mig_7series_0" PORT="ui_clk"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="LMB_Rst" SIGIS="rst" SIGNAME="rst_clk_wiz_1_100M_bus_struct_reset">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="rst_clk_wiz_1_100M" PORT="bus_struct_reset"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="0" NAME="LMB_ABus" RIGHT="31" SIGIS="undef" SIGNAME="microblaze_0_local_memory_dlmb_bram_if_cntlr_LMB_ABus">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_v10" PORT="LMB_ABus"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="0" NAME="LMB_WriteDBus" RIGHT="31" SIGIS="undef" SIGNAME="microblaze_0_local_memory_dlmb_bram_if_cntlr_LMB_WriteDBus">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_v10" PORT="LMB_WriteDBus"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="LMB_AddrStrobe" SIGIS="undef" SIGNAME="microblaze_0_local_memory_dlmb_bram_if_cntlr_LMB_AddrStrobe">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_v10" PORT="LMB_AddrStrobe"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="LMB_ReadStrobe" SIGIS="undef" SIGNAME="microblaze_0_local_memory_dlmb_bram_if_cntlr_LMB_ReadStrobe">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_v10" PORT="LMB_ReadStrobe"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="LMB_WriteStrobe" SIGIS="undef" SIGNAME="microblaze_0_local_memory_dlmb_bram_if_cntlr_LMB_WriteStrobe">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_v10" PORT="LMB_WriteStrobe"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="0" NAME="LMB_BE" RIGHT="3" SIGIS="undef" SIGNAME="microblaze_0_local_memory_dlmb_bram_if_cntlr_LMB_BE">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_v10" PORT="LMB_BE"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="0" NAME="Sl_DBus" RIGHT="31" SIGIS="undef" SIGNAME="microblaze_0_local_memory_dlmb_bram_if_cntlr_Sl_DBus">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_v10" PORT="Sl_DBus"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="Sl_Ready" SIGIS="undef" SIGNAME="microblaze_0_local_memory_dlmb_bram_if_cntlr_Sl_Ready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_v10" PORT="Sl_Ready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="Sl_Wait" SIGIS="undef" SIGNAME="microblaze_0_local_memory_dlmb_bram_if_cntlr_Sl_Wait">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_v10" PORT="Sl_Wait"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="Sl_UE" SIGIS="undef" SIGNAME="microblaze_0_local_memory_dlmb_bram_if_cntlr_Sl_UE">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_v10" PORT="Sl_UE"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="Sl_CE" SIGIS="undef" SIGNAME="microblaze_0_local_memory_dlmb_bram_if_cntlr_Sl_CE">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_v10" PORT="Sl_CE"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="BRAM_Rst_A" SIGIS="undef" SIGNAME="microblaze_0_local_memory_dlmb_bram_if_cntlr_BRAM_Rst_A">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_local_memory_lmb_bram" PORT="rsta"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="BRAM_Clk_A" SIGIS="undef" SIGNAME="microblaze_0_local_memory_dlmb_bram_if_cntlr_BRAM_Clk_A">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_local_memory_lmb_bram" PORT="clka"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="0" NAME="BRAM_Addr_A" RIGHT="31" SIGIS="undef" SIGNAME="microblaze_0_local_memory_dlmb_bram_if_cntlr_BRAM_Addr_A">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_local_memory_lmb_bram" PORT="addra"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="BRAM_EN_A" SIGIS="undef" SIGNAME="microblaze_0_local_memory_dlmb_bram_if_cntlr_BRAM_EN_A">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_local_memory_lmb_bram" PORT="ena"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="0" NAME="BRAM_WEN_A" RIGHT="3" SIGIS="undef" SIGNAME="microblaze_0_local_memory_dlmb_bram_if_cntlr_BRAM_WEN_A">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_local_memory_lmb_bram" PORT="wea"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="0" NAME="BRAM_Dout_A" RIGHT="31" SIGIS="undef" SIGNAME="microblaze_0_local_memory_dlmb_bram_if_cntlr_BRAM_Dout_A">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_local_memory_lmb_bram" PORT="dina"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="0" NAME="BRAM_Din_A" RIGHT="31" SIGIS="undef" SIGNAME="microblaze_0_local_memory_dlmb_bram_if_cntlr_BRAM_Din_A">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_local_memory_lmb_bram" PORT="douta"/>
+          </CONNECTIONS>
+        </PORT>
+      </PORTS>
+      <BUSINTERFACES>
+        <BUSINTERFACE BUSNAME="microblaze_0_local_memory_dlmb_v10_LMB_Sl_0" NAME="SLMB" TYPE="SLAVE">
+          <PORTMAPS>
+            <PORTMAP PHYSICAL="LMB_ABus"/>
+            <PORTMAP PHYSICAL="LMB_AddrStrobe"/>
+            <PORTMAP PHYSICAL="LMB_BE"/>
+            <PORTMAP PHYSICAL="Sl_CE"/>
+            <PORTMAP PHYSICAL="Sl_DBus"/>
+            <PORTMAP PHYSICAL="LMB_ReadStrobe"/>
+            <PORTMAP PHYSICAL="Sl_Ready"/>
+            <PORTMAP PHYSICAL="Sl_UE"/>
+            <PORTMAP PHYSICAL="Sl_Wait"/>
+            <PORTMAP PHYSICAL="LMB_WriteDBus"/>
+            <PORTMAP PHYSICAL="LMB_WriteStrobe"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="microblaze_0_local_memory_dlmb_bram_if_cntlr_BRAM_PORT" NAME="BRAM_PORT" TYPE="INITIATOR">
+          <PORTMAPS>
+            <PORTMAP PHYSICAL="BRAM_Addr_A"/>
+            <PORTMAP PHYSICAL="BRAM_Clk_A"/>
+            <PORTMAP PHYSICAL="BRAM_Dout_A"/>
+            <PORTMAP PHYSICAL="BRAM_Din_A"/>
+            <PORTMAP PHYSICAL="BRAM_EN_A"/>
+            <PORTMAP PHYSICAL="BRAM_Rst_A"/>
+            <PORTMAP PHYSICAL="BRAM_WEN_A"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+      </BUSINTERFACES>
+    </MODULE>
+    <MODULE FULLNAME="/microblaze_0_local_memory/dlmb_v10" HWVERSION="3.0" INSTANCE="microblaze_0_local_memory_dlmb_v10" IPTYPE="BUS" IS_ENABLE="1" MODCLASS="BUS" MODTYPE="lmb_v10" VLNV="xilinx.com:ip:lmb_v10:3.0">
+      <DOCUMENTS>
+        <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=lmb_v10;v=v3_0;d=pg113-lmb-v10.pdf"/>
+      </DOCUMENTS>
+      <PARAMETERS>
+        <PARAMETER NAME="C_LMB_NUM_SLAVES" VALUE="1"/>
+        <PARAMETER NAME="C_LMB_DWIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_LMB_AWIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_EXT_RESET_HIGH" VALUE="1"/>
+        <PARAMETER NAME="Component_Name" VALUE="base_microblaze_design_dlmb_v10_0"/>
+        <PARAMETER NAME="EDK_IPTYPE" VALUE="BUS"/>
+      </PARAMETERS>
+      <PORTS>
+        <PORT CLKFREQUENCY="100000000" DIR="I" NAME="LMB_Clk" SIGIS="clk" SIGNAME="mig_7series_0_ui_clk">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="mig_7series_0" PORT="ui_clk"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="SYS_Rst" SIGIS="rst" SIGNAME="rst_clk_wiz_1_100M_bus_struct_reset">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="rst_clk_wiz_1_100M" PORT="bus_struct_reset"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="LMB_Rst" SIGIS="undef"/>
+        <PORT DIR="I" LEFT="0" NAME="M_ABus" RIGHT="31" SIGIS="undef" SIGNAME="microblaze_0_Data_Addr">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="Data_Addr"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M_ReadStrobe" SIGIS="undef" SIGNAME="microblaze_0_Read_Strobe">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="Read_Strobe"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M_WriteStrobe" SIGIS="undef" SIGNAME="microblaze_0_Write_Strobe">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="Write_Strobe"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M_AddrStrobe" SIGIS="undef" SIGNAME="microblaze_0_D_AS">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="D_AS"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="0" NAME="M_DBus" RIGHT="31" SIGIS="undef" SIGNAME="microblaze_0_Data_Write">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="Data_Write"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="0" NAME="M_BE" RIGHT="3" SIGIS="undef" SIGNAME="microblaze_0_Byte_Enable">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="Byte_Enable"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="0" NAME="Sl_DBus" RIGHT="31" SIGIS="undef" SIGNAME="microblaze_0_local_memory_dlmb_bram_if_cntlr_Sl_DBus">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_bram_if_cntlr" PORT="Sl_DBus"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="0" NAME="Sl_Ready" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_local_memory_dlmb_bram_if_cntlr_Sl_Ready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_bram_if_cntlr" PORT="Sl_Ready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="0" NAME="Sl_Wait" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_local_memory_dlmb_bram_if_cntlr_Sl_Wait">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_bram_if_cntlr" PORT="Sl_Wait"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="0" NAME="Sl_UE" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_local_memory_dlmb_bram_if_cntlr_Sl_UE">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_bram_if_cntlr" PORT="Sl_UE"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="0" NAME="Sl_CE" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_local_memory_dlmb_bram_if_cntlr_Sl_CE">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_bram_if_cntlr" PORT="Sl_CE"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="0" NAME="LMB_ABus" RIGHT="31" SIGIS="undef" SIGNAME="microblaze_0_local_memory_dlmb_bram_if_cntlr_LMB_ABus">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_bram_if_cntlr" PORT="LMB_ABus"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="LMB_ReadStrobe" SIGIS="undef" SIGNAME="microblaze_0_local_memory_dlmb_bram_if_cntlr_LMB_ReadStrobe">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_bram_if_cntlr" PORT="LMB_ReadStrobe"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="LMB_WriteStrobe" SIGIS="undef" SIGNAME="microblaze_0_local_memory_dlmb_bram_if_cntlr_LMB_WriteStrobe">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_bram_if_cntlr" PORT="LMB_WriteStrobe"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="LMB_AddrStrobe" SIGIS="undef" SIGNAME="microblaze_0_local_memory_dlmb_bram_if_cntlr_LMB_AddrStrobe">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_bram_if_cntlr" PORT="LMB_AddrStrobe"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="0" NAME="LMB_ReadDBus" RIGHT="31" SIGIS="undef" SIGNAME="microblaze_0_Data_Read">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="Data_Read"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="0" NAME="LMB_WriteDBus" RIGHT="31" SIGIS="undef" SIGNAME="microblaze_0_local_memory_dlmb_bram_if_cntlr_LMB_WriteDBus">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_bram_if_cntlr" PORT="LMB_WriteDBus"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="LMB_Ready" SIGIS="undef" SIGNAME="microblaze_0_DReady">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="DReady"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="LMB_Wait" SIGIS="undef" SIGNAME="microblaze_0_DWait">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="DWait"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="LMB_UE" SIGIS="undef" SIGNAME="microblaze_0_DUE">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="DUE"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="LMB_CE" SIGIS="undef" SIGNAME="microblaze_0_DCE">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="DCE"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="0" NAME="LMB_BE" RIGHT="3" SIGIS="undef" SIGNAME="microblaze_0_local_memory_dlmb_bram_if_cntlr_LMB_BE">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_bram_if_cntlr" PORT="LMB_BE"/>
+          </CONNECTIONS>
+        </PORT>
+      </PORTS>
+      <BUSINTERFACES>
+        <BUSINTERFACE BUSNAME="microblaze_0_local_memory_dlmb_v10_LMB_Sl_0" NAME="LMB_Sl_0" TYPE="SLAVE">
+          <PORTMAPS>
+            <PORTMAP PHYSICAL="LMB_ABus"/>
+            <PORTMAP PHYSICAL="LMB_AddrStrobe"/>
+            <PORTMAP PHYSICAL="LMB_BE"/>
+            <PORTMAP PHYSICAL="Sl_CE"/>
+            <PORTMAP PHYSICAL="Sl_DBus"/>
+            <PORTMAP PHYSICAL="LMB_ReadStrobe"/>
+            <PORTMAP PHYSICAL="Sl_Ready"/>
+            <PORTMAP PHYSICAL="LMB_Rst"/>
+            <PORTMAP PHYSICAL="Sl_UE"/>
+            <PORTMAP PHYSICAL="Sl_Wait"/>
+            <PORTMAP PHYSICAL="LMB_WriteDBus"/>
+            <PORTMAP PHYSICAL="LMB_WriteStrobe"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="microblaze_0_DLMB" NAME="LMB_M" TYPE="SLAVE">
+          <PORTMAPS>
+            <PORTMAP PHYSICAL="M_ABus"/>
+            <PORTMAP PHYSICAL="M_AddrStrobe"/>
+            <PORTMAP PHYSICAL="M_BE"/>
+            <PORTMAP PHYSICAL="LMB_CE"/>
+            <PORTMAP PHYSICAL="LMB_ReadDBus"/>
+            <PORTMAP PHYSICAL="M_ReadStrobe"/>
+            <PORTMAP PHYSICAL="LMB_Ready"/>
+            <PORTMAP PHYSICAL="LMB_Rst"/>
+            <PORTMAP PHYSICAL="LMB_UE"/>
+            <PORTMAP PHYSICAL="LMB_Wait"/>
+            <PORTMAP PHYSICAL="M_DBus"/>
+            <PORTMAP PHYSICAL="M_WriteStrobe"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+      </BUSINTERFACES>
+    </MODULE>
+    <MODULE FULLNAME="/microblaze_0_local_memory/ilmb_bram_if_cntlr" HWVERSION="4.0" INSTANCE="microblaze_0_local_memory_ilmb_bram_if_cntlr" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="MEMORY_CNTLR" MODTYPE="lmb_bram_if_cntlr" VLNV="xilinx.com:ip:lmb_bram_if_cntlr:4.0">
+      <DOCUMENTS>
+        <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=lmb_bram_if_cntlr;v=v4_0;d=pg112-lmb-bram-if-cntlr.pdf"/>
+      </DOCUMENTS>
+      <PARAMETERS>
+        <PARAMETER NAME="C_FAMILY" VALUE="kintex7"/>
+        <PARAMETER NAME="C_NUM_LMB" VALUE="1"/>
+        <PARAMETER NAME="C_MASK" VALUE="0x80000000"/>
+        <PARAMETER NAME="C_MASK1" VALUE="0x00800000"/>
+        <PARAMETER NAME="C_MASK2" VALUE="0x00800000"/>
+        <PARAMETER NAME="C_MASK3" VALUE="0x00800000"/>
+        <PARAMETER NAME="C_LMB_AWIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_LMB_DWIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_ECC" VALUE="0"/>
+        <PARAMETER NAME="C_INTERCONNECT" VALUE="0"/>
+        <PARAMETER NAME="C_FAULT_INJECT" VALUE="0"/>
+        <PARAMETER NAME="C_CE_FAILING_REGISTERS" VALUE="0"/>
+        <PARAMETER NAME="C_UE_FAILING_REGISTERS" VALUE="0"/>
+        <PARAMETER NAME="C_ECC_STATUS_REGISTERS" VALUE="0"/>
+        <PARAMETER NAME="C_ECC_ONOFF_REGISTER" VALUE="0"/>
+        <PARAMETER NAME="C_ECC_ONOFF_RESET_VALUE" VALUE="1"/>
+        <PARAMETER NAME="C_CE_COUNTER_WIDTH" VALUE="0"/>
+        <PARAMETER NAME="C_WRITE_ACCESS" VALUE="2"/>
+        <PARAMETER NAME="C_S_AXI_CTRL_ADDR_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_S_AXI_CTRL_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_S_AXI_CTRL_ACLK_FREQ_HZ" VALUE="100000000"/>
+        <PARAMETER NAME="C_S_AXI_CTRL_PROTOCOL" VALUE="AXI4LITE"/>
+        <PARAMETER NAME="Component_Name" VALUE="base_microblaze_design_ilmb_bram_if_cntlr_0"/>
+        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
+        <PARAMETER NAME="EDK_SPECIAL" VALUE="BRAM_CTRL"/>
+        <PARAMETER NAME="C_BASEADDR" VALUE="0x00000000"/>
+        <PARAMETER NAME="C_HIGHADDR" VALUE="0x0003FFFF"/>
+      </PARAMETERS>
+      <PORTS>
+        <PORT CLKFREQUENCY="100000000" DIR="I" NAME="LMB_Clk" SIGIS="clk" SIGNAME="mig_7series_0_ui_clk">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="mig_7series_0" PORT="ui_clk"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="LMB_Rst" SIGIS="rst" SIGNAME="rst_clk_wiz_1_100M_bus_struct_reset">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="rst_clk_wiz_1_100M" PORT="bus_struct_reset"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="0" NAME="LMB_ABus" RIGHT="31" SIGIS="undef" SIGNAME="microblaze_0_local_memory_ilmb_bram_if_cntlr_LMB_ABus">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_v10" PORT="LMB_ABus"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="0" NAME="LMB_WriteDBus" RIGHT="31" SIGIS="undef" SIGNAME="microblaze_0_local_memory_ilmb_bram_if_cntlr_LMB_WriteDBus">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_v10" PORT="LMB_WriteDBus"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="LMB_AddrStrobe" SIGIS="undef" SIGNAME="microblaze_0_local_memory_ilmb_bram_if_cntlr_LMB_AddrStrobe">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_v10" PORT="LMB_AddrStrobe"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="LMB_ReadStrobe" SIGIS="undef" SIGNAME="microblaze_0_local_memory_ilmb_bram_if_cntlr_LMB_ReadStrobe">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_v10" PORT="LMB_ReadStrobe"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="LMB_WriteStrobe" SIGIS="undef" SIGNAME="microblaze_0_local_memory_ilmb_bram_if_cntlr_LMB_WriteStrobe">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_v10" PORT="LMB_WriteStrobe"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="0" NAME="LMB_BE" RIGHT="3" SIGIS="undef" SIGNAME="microblaze_0_local_memory_ilmb_bram_if_cntlr_LMB_BE">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_v10" PORT="LMB_BE"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="0" NAME="Sl_DBus" RIGHT="31" SIGIS="undef" SIGNAME="microblaze_0_local_memory_ilmb_bram_if_cntlr_Sl_DBus">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_v10" PORT="Sl_DBus"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="Sl_Ready" SIGIS="undef" SIGNAME="microblaze_0_local_memory_ilmb_bram_if_cntlr_Sl_Ready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_v10" PORT="Sl_Ready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="Sl_Wait" SIGIS="undef" SIGNAME="microblaze_0_local_memory_ilmb_bram_if_cntlr_Sl_Wait">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_v10" PORT="Sl_Wait"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="Sl_UE" SIGIS="undef" SIGNAME="microblaze_0_local_memory_ilmb_bram_if_cntlr_Sl_UE">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_v10" PORT="Sl_UE"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="Sl_CE" SIGIS="undef" SIGNAME="microblaze_0_local_memory_ilmb_bram_if_cntlr_Sl_CE">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_v10" PORT="Sl_CE"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="BRAM_Rst_A" SIGIS="undef" SIGNAME="microblaze_0_local_memory_ilmb_bram_if_cntlr_BRAM_Rst_A">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_local_memory_lmb_bram" PORT="rstb"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="BRAM_Clk_A" SIGIS="undef" SIGNAME="microblaze_0_local_memory_ilmb_bram_if_cntlr_BRAM_Clk_A">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_local_memory_lmb_bram" PORT="clkb"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="0" NAME="BRAM_Addr_A" RIGHT="31" SIGIS="undef" SIGNAME="microblaze_0_local_memory_ilmb_bram_if_cntlr_BRAM_Addr_A">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_local_memory_lmb_bram" PORT="addrb"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="BRAM_EN_A" SIGIS="undef" SIGNAME="microblaze_0_local_memory_ilmb_bram_if_cntlr_BRAM_EN_A">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_local_memory_lmb_bram" PORT="enb"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="0" NAME="BRAM_WEN_A" RIGHT="3" SIGIS="undef" SIGNAME="microblaze_0_local_memory_ilmb_bram_if_cntlr_BRAM_WEN_A">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_local_memory_lmb_bram" PORT="web"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="0" NAME="BRAM_Dout_A" RIGHT="31" SIGIS="undef" SIGNAME="microblaze_0_local_memory_ilmb_bram_if_cntlr_BRAM_Dout_A">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_local_memory_lmb_bram" PORT="dinb"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="0" NAME="BRAM_Din_A" RIGHT="31" SIGIS="undef" SIGNAME="microblaze_0_local_memory_ilmb_bram_if_cntlr_BRAM_Din_A">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_local_memory_lmb_bram" PORT="doutb"/>
+          </CONNECTIONS>
+        </PORT>
+      </PORTS>
+      <BUSINTERFACES>
+        <BUSINTERFACE BUSNAME="microblaze_0_local_memory_ilmb_v10_LMB_Sl_0" NAME="SLMB" TYPE="SLAVE">
+          <PORTMAPS>
+            <PORTMAP PHYSICAL="LMB_ABus"/>
+            <PORTMAP PHYSICAL="LMB_AddrStrobe"/>
+            <PORTMAP PHYSICAL="LMB_BE"/>
+            <PORTMAP PHYSICAL="Sl_CE"/>
+            <PORTMAP PHYSICAL="Sl_DBus"/>
+            <PORTMAP PHYSICAL="LMB_ReadStrobe"/>
+            <PORTMAP PHYSICAL="Sl_Ready"/>
+            <PORTMAP PHYSICAL="Sl_UE"/>
+            <PORTMAP PHYSICAL="Sl_Wait"/>
+            <PORTMAP PHYSICAL="LMB_WriteDBus"/>
+            <PORTMAP PHYSICAL="LMB_WriteStrobe"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="microblaze_0_local_memory_ilmb_bram_if_cntlr_BRAM_PORT" NAME="BRAM_PORT" TYPE="INITIATOR">
+          <PORTMAPS>
+            <PORTMAP PHYSICAL="BRAM_Addr_A"/>
+            <PORTMAP PHYSICAL="BRAM_Clk_A"/>
+            <PORTMAP PHYSICAL="BRAM_Dout_A"/>
+            <PORTMAP PHYSICAL="BRAM_Din_A"/>
+            <PORTMAP PHYSICAL="BRAM_EN_A"/>
+            <PORTMAP PHYSICAL="BRAM_Rst_A"/>
+            <PORTMAP PHYSICAL="BRAM_WEN_A"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+      </BUSINTERFACES>
+    </MODULE>
+    <MODULE FULLNAME="/microblaze_0_local_memory/ilmb_v10" HWVERSION="3.0" INSTANCE="microblaze_0_local_memory_ilmb_v10" IPTYPE="BUS" IS_ENABLE="1" MODCLASS="BUS" MODTYPE="lmb_v10" VLNV="xilinx.com:ip:lmb_v10:3.0">
+      <DOCUMENTS>
+        <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=lmb_v10;v=v3_0;d=pg113-lmb-v10.pdf"/>
+      </DOCUMENTS>
+      <PARAMETERS>
+        <PARAMETER NAME="C_LMB_NUM_SLAVES" VALUE="1"/>
+        <PARAMETER NAME="C_LMB_DWIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_LMB_AWIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_EXT_RESET_HIGH" VALUE="1"/>
+        <PARAMETER NAME="Component_Name" VALUE="base_microblaze_design_ilmb_v10_0"/>
+        <PARAMETER NAME="EDK_IPTYPE" VALUE="BUS"/>
+      </PARAMETERS>
+      <PORTS>
+        <PORT CLKFREQUENCY="100000000" DIR="I" NAME="LMB_Clk" SIGIS="clk" SIGNAME="mig_7series_0_ui_clk">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="mig_7series_0" PORT="ui_clk"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="SYS_Rst" SIGIS="rst" SIGNAME="rst_clk_wiz_1_100M_bus_struct_reset">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="rst_clk_wiz_1_100M" PORT="bus_struct_reset"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="LMB_Rst" SIGIS="undef"/>
+        <PORT DIR="I" LEFT="0" NAME="M_ABus" RIGHT="31" SIGIS="undef" SIGNAME="microblaze_0_Instr_Addr">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="Instr_Addr"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M_ReadStrobe" SIGIS="undef" SIGNAME="microblaze_0_IFetch">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="IFetch"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M_WriteStrobe" SIGIS="undef"/>
+        <PORT DIR="I" NAME="M_AddrStrobe" SIGIS="undef" SIGNAME="microblaze_0_I_AS">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="I_AS"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="0" NAME="M_DBus" RIGHT="31" SIGIS="undef"/>
+        <PORT DIR="I" LEFT="0" NAME="M_BE" RIGHT="3" SIGIS="undef"/>
+        <PORT DIR="I" LEFT="0" NAME="Sl_DBus" RIGHT="31" SIGIS="undef" SIGNAME="microblaze_0_local_memory_ilmb_bram_if_cntlr_Sl_DBus">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_bram_if_cntlr" PORT="Sl_DBus"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="0" NAME="Sl_Ready" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_local_memory_ilmb_bram_if_cntlr_Sl_Ready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_bram_if_cntlr" PORT="Sl_Ready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="0" NAME="Sl_Wait" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_local_memory_ilmb_bram_if_cntlr_Sl_Wait">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_bram_if_cntlr" PORT="Sl_Wait"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="0" NAME="Sl_UE" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_local_memory_ilmb_bram_if_cntlr_Sl_UE">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_bram_if_cntlr" PORT="Sl_UE"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="0" NAME="Sl_CE" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_local_memory_ilmb_bram_if_cntlr_Sl_CE">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_bram_if_cntlr" PORT="Sl_CE"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="0" NAME="LMB_ABus" RIGHT="31" SIGIS="undef" SIGNAME="microblaze_0_local_memory_ilmb_bram_if_cntlr_LMB_ABus">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_bram_if_cntlr" PORT="LMB_ABus"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="LMB_ReadStrobe" SIGIS="undef" SIGNAME="microblaze_0_local_memory_ilmb_bram_if_cntlr_LMB_ReadStrobe">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_bram_if_cntlr" PORT="LMB_ReadStrobe"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="LMB_WriteStrobe" SIGIS="undef" SIGNAME="microblaze_0_local_memory_ilmb_bram_if_cntlr_LMB_WriteStrobe">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_bram_if_cntlr" PORT="LMB_WriteStrobe"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="LMB_AddrStrobe" SIGIS="undef" SIGNAME="microblaze_0_local_memory_ilmb_bram_if_cntlr_LMB_AddrStrobe">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_bram_if_cntlr" PORT="LMB_AddrStrobe"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="0" NAME="LMB_ReadDBus" RIGHT="31" SIGIS="undef" SIGNAME="microblaze_0_Instr">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="Instr"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="0" NAME="LMB_WriteDBus" RIGHT="31" SIGIS="undef" SIGNAME="microblaze_0_local_memory_ilmb_bram_if_cntlr_LMB_WriteDBus">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_bram_if_cntlr" PORT="LMB_WriteDBus"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="LMB_Ready" SIGIS="undef" SIGNAME="microblaze_0_IReady">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="IReady"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="LMB_Wait" SIGIS="undef" SIGNAME="microblaze_0_IWAIT">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="IWAIT"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="LMB_UE" SIGIS="undef" SIGNAME="microblaze_0_IUE">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="IUE"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="LMB_CE" SIGIS="undef" SIGNAME="microblaze_0_ICE">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="ICE"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="0" NAME="LMB_BE" RIGHT="3" SIGIS="undef" SIGNAME="microblaze_0_local_memory_ilmb_bram_if_cntlr_LMB_BE">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_bram_if_cntlr" PORT="LMB_BE"/>
+          </CONNECTIONS>
+        </PORT>
+      </PORTS>
+      <BUSINTERFACES>
+        <BUSINTERFACE BUSNAME="microblaze_0_local_memory_ilmb_v10_LMB_Sl_0" NAME="LMB_Sl_0" TYPE="SLAVE">
+          <PORTMAPS>
+            <PORTMAP PHYSICAL="LMB_ABus"/>
+            <PORTMAP PHYSICAL="LMB_AddrStrobe"/>
+            <PORTMAP PHYSICAL="LMB_BE"/>
+            <PORTMAP PHYSICAL="Sl_CE"/>
+            <PORTMAP PHYSICAL="Sl_DBus"/>
+            <PORTMAP PHYSICAL="LMB_ReadStrobe"/>
+            <PORTMAP PHYSICAL="Sl_Ready"/>
+            <PORTMAP PHYSICAL="LMB_Rst"/>
+            <PORTMAP PHYSICAL="Sl_UE"/>
+            <PORTMAP PHYSICAL="Sl_Wait"/>
+            <PORTMAP PHYSICAL="LMB_WriteDBus"/>
+            <PORTMAP PHYSICAL="LMB_WriteStrobe"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="microblaze_0_ILMB" NAME="LMB_M" TYPE="SLAVE">
+          <PORTMAPS>
+            <PORTMAP PHYSICAL="M_ABus"/>
+            <PORTMAP PHYSICAL="M_AddrStrobe"/>
+            <PORTMAP PHYSICAL="M_BE"/>
+            <PORTMAP PHYSICAL="LMB_CE"/>
+            <PORTMAP PHYSICAL="LMB_ReadDBus"/>
+            <PORTMAP PHYSICAL="M_ReadStrobe"/>
+            <PORTMAP PHYSICAL="LMB_Ready"/>
+            <PORTMAP PHYSICAL="LMB_Rst"/>
+            <PORTMAP PHYSICAL="LMB_UE"/>
+            <PORTMAP PHYSICAL="LMB_Wait"/>
+            <PORTMAP PHYSICAL="M_DBus"/>
+            <PORTMAP PHYSICAL="M_WriteStrobe"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+      </BUSINTERFACES>
+    </MODULE>
+    <MODULE FULLNAME="/microblaze_0_local_memory/lmb_bram" HWVERSION="8.2" INSTANCE="microblaze_0_local_memory_lmb_bram" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="MEMORY" MODTYPE="blk_mem_gen" VLNV="xilinx.com:ip:blk_mem_gen:8.2">
+      <DOCUMENTS>
+        <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=blk_mem_gen;v=v8_2;d=pg058-blk-mem-gen.pdf"/>
+      </DOCUMENTS>
+      <PARAMETERS>
+        <PARAMETER NAME="C_FAMILY" VALUE="kintex7"/>
+        <PARAMETER NAME="C_XDEVICEFAMILY" VALUE="kintex7"/>
+        <PARAMETER NAME="C_ELABORATION_DIR" VALUE="./"/>
+        <PARAMETER NAME="C_INTERFACE_TYPE" VALUE="0"/>
+        <PARAMETER NAME="C_AXI_TYPE" VALUE="1"/>
+        <PARAMETER NAME="C_AXI_SLAVE_TYPE" VALUE="0"/>
+        <PARAMETER NAME="C_USE_BRAM_BLOCK" VALUE="1"/>
+        <PARAMETER NAME="C_ENABLE_32BIT_ADDRESS" VALUE="1"/>
+        <PARAMETER NAME="C_CTRL_ECC_ALGO" VALUE="NONE"/>
+        <PARAMETER NAME="C_HAS_AXI_ID" VALUE="0"/>
+        <PARAMETER NAME="C_AXI_ID_WIDTH" VALUE="4"/>
+        <PARAMETER NAME="C_MEM_TYPE" VALUE="2"/>
+        <PARAMETER NAME="C_BYTE_SIZE" VALUE="8"/>
+        <PARAMETER NAME="C_ALGORITHM" VALUE="1"/>
+        <PARAMETER NAME="C_PRIM_TYPE" VALUE="1"/>
+        <PARAMETER NAME="C_LOAD_INIT_FILE" VALUE="0"/>
+        <PARAMETER NAME="C_INIT_FILE_NAME" VALUE="no_coe_file_loaded"/>
+        <PARAMETER NAME="C_INIT_FILE" VALUE="base_microblaze_design_lmb_bram_0.mem"/>
+        <PARAMETER NAME="C_USE_DEFAULT_DATA" VALUE="0"/>
+        <PARAMETER NAME="C_DEFAULT_DATA" VALUE="0"/>
+        <PARAMETER NAME="C_HAS_RSTA" VALUE="1"/>
+        <PARAMETER NAME="C_RST_PRIORITY_A" VALUE="CE"/>
+        <PARAMETER NAME="C_RSTRAM_A" VALUE="0"/>
+        <PARAMETER NAME="C_INITA_VAL" VALUE="0"/>
+        <PARAMETER NAME="C_HAS_ENA" VALUE="1"/>
+        <PARAMETER NAME="C_HAS_REGCEA" VALUE="0"/>
+        <PARAMETER NAME="C_USE_BYTE_WEA" VALUE="1"/>
+        <PARAMETER NAME="C_WEA_WIDTH" VALUE="4"/>
+        <PARAMETER NAME="C_WRITE_MODE_A" VALUE="WRITE_FIRST"/>
+        <PARAMETER NAME="C_WRITE_WIDTH_A" VALUE="32"/>
+        <PARAMETER NAME="C_READ_WIDTH_A" VALUE="32"/>
+        <PARAMETER NAME="C_WRITE_DEPTH_A" VALUE="65536"/>
+        <PARAMETER NAME="C_READ_DEPTH_A" VALUE="65536"/>
+        <PARAMETER NAME="C_ADDRA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_HAS_RSTB" VALUE="1"/>
+        <PARAMETER NAME="C_RST_PRIORITY_B" VALUE="CE"/>
+        <PARAMETER NAME="C_RSTRAM_B" VALUE="0"/>
+        <PARAMETER NAME="C_INITB_VAL" VALUE="0"/>
+        <PARAMETER NAME="C_HAS_ENB" VALUE="1"/>
+        <PARAMETER NAME="C_HAS_REGCEB" VALUE="0"/>
+        <PARAMETER NAME="C_USE_BYTE_WEB" VALUE="1"/>
+        <PARAMETER NAME="C_WEB_WIDTH" VALUE="4"/>
+        <PARAMETER NAME="C_WRITE_MODE_B" VALUE="WRITE_FIRST"/>
+        <PARAMETER NAME="C_WRITE_WIDTH_B" VALUE="32"/>
+        <PARAMETER NAME="C_READ_WIDTH_B" VALUE="32"/>
+        <PARAMETER NAME="C_WRITE_DEPTH_B" VALUE="65536"/>
+        <PARAMETER NAME="C_READ_DEPTH_B" VALUE="65536"/>
+        <PARAMETER NAME="C_ADDRB_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_HAS_MEM_OUTPUT_REGS_A" VALUE="0"/>
+        <PARAMETER NAME="C_HAS_MEM_OUTPUT_REGS_B" VALUE="0"/>
+        <PARAMETER NAME="C_HAS_MUX_OUTPUT_REGS_A" VALUE="0"/>
+        <PARAMETER NAME="C_HAS_MUX_OUTPUT_REGS_B" VALUE="0"/>
+        <PARAMETER NAME="C_MUX_PIPELINE_STAGES" VALUE="0"/>
+        <PARAMETER NAME="C_HAS_SOFTECC_INPUT_REGS_A" VALUE="0"/>
+        <PARAMETER NAME="C_HAS_SOFTECC_OUTPUT_REGS_B" VALUE="0"/>
+        <PARAMETER NAME="C_USE_SOFTECC" VALUE="0"/>
+        <PARAMETER NAME="C_USE_ECC" VALUE="0"/>
+        <PARAMETER NAME="C_EN_ECC_PIPE" VALUE="0"/>
+        <PARAMETER NAME="C_HAS_INJECTERR" VALUE="0"/>
+        <PARAMETER NAME="C_SIM_COLLISION_CHECK" VALUE="ALL"/>
+        <PARAMETER NAME="C_COMMON_CLK" VALUE="0"/>
+        <PARAMETER NAME="C_DISABLE_WARN_BHV_COLL" VALUE="0"/>
+        <PARAMETER NAME="C_EN_SLEEP_PIN" VALUE="0"/>
+        <PARAMETER NAME="C_DISABLE_WARN_BHV_RANGE" VALUE="0"/>
+        <PARAMETER NAME="C_COUNT_36K_BRAM" VALUE="64"/>
+        <PARAMETER NAME="C_COUNT_18K_BRAM" VALUE="0"/>
+        <PARAMETER NAME="C_EST_POWER_SUMMARY" VALUE="Estimated Power for IP     :     20.388004 mW"/>
+        <PARAMETER NAME="Component_Name" VALUE="base_microblaze_design_lmb_bram_0"/>
+        <PARAMETER NAME="Interface_Type" VALUE="Native"/>
+        <PARAMETER NAME="AXI_Type" VALUE="AXI4_Full"/>
+        <PARAMETER NAME="AXI_Slave_Type" VALUE="Memory_Slave"/>
+        <PARAMETER NAME="Use_AXI_ID" VALUE="false"/>
+        <PARAMETER NAME="AXI_ID_Width" VALUE="4"/>
+        <PARAMETER NAME="Memory_Type" VALUE="True_Dual_Port_RAM"/>
+        <PARAMETER NAME="Enable_32bit_Address" VALUE="true"/>
+        <PARAMETER NAME="ecctype" VALUE="No_ECC"/>
+        <PARAMETER NAME="ECC" VALUE="false"/>
+        <PARAMETER NAME="softecc" VALUE="false"/>
+        <PARAMETER NAME="EN_SLEEP_PIN" VALUE="false"/>
+        <PARAMETER NAME="EN_ECC_PIPE" VALUE="false"/>
+        <PARAMETER NAME="Use_Error_Injection_Pins" VALUE="false"/>
+        <PARAMETER NAME="Error_Injection_Type" VALUE="Single_Bit_Error_Injection"/>
+        <PARAMETER NAME="Use_Byte_Write_Enable" VALUE="true"/>
+        <PARAMETER NAME="Byte_Size" VALUE="8"/>
+        <PARAMETER NAME="Algorithm" VALUE="Minimum_Area"/>
+        <PARAMETER NAME="Primitive" VALUE="8kx2"/>
+        <PARAMETER NAME="Assume_Synchronous_Clk" VALUE="false"/>
+        <PARAMETER NAME="Write_Width_A" VALUE="32"/>
+        <PARAMETER NAME="Write_Depth_A" VALUE="65536"/>
+        <PARAMETER NAME="Read_Width_A" VALUE="32"/>
+        <PARAMETER NAME="Operating_Mode_A" VALUE="WRITE_FIRST"/>
+        <PARAMETER NAME="Enable_A" VALUE="Use_ENA_Pin"/>
+        <PARAMETER NAME="Write_Width_B" VALUE="32"/>
+        <PARAMETER NAME="Read_Width_B" VALUE="32"/>
+        <PARAMETER NAME="Operating_Mode_B" VALUE="WRITE_FIRST"/>
+        <PARAMETER NAME="Enable_B" VALUE="Use_ENB_Pin"/>
+        <PARAMETER NAME="Register_PortA_Output_of_Memory_Primitives" VALUE="false"/>
+        <PARAMETER NAME="Register_PortA_Output_of_Memory_Core" VALUE="false"/>
+        <PARAMETER NAME="Use_REGCEA_Pin" VALUE="false"/>
+        <PARAMETER NAME="Register_PortB_Output_of_Memory_Primitives" VALUE="false"/>
+        <PARAMETER NAME="Register_PortB_Output_of_Memory_Core" VALUE="false"/>
+        <PARAMETER NAME="Use_REGCEB_Pin" VALUE="false"/>
+        <PARAMETER NAME="register_porta_input_of_softecc" VALUE="false"/>
+        <PARAMETER NAME="register_portb_output_of_softecc" VALUE="false"/>
+        <PARAMETER NAME="Pipeline_Stages" VALUE="0"/>
+        <PARAMETER NAME="Load_Init_File" VALUE="false"/>
+        <PARAMETER NAME="Coe_File" VALUE="no_coe_file_loaded"/>
+        <PARAMETER NAME="Fill_Remaining_Memory_Locations" VALUE="false"/>
+        <PARAMETER NAME="Remaining_Memory_Locations" VALUE="0"/>
+        <PARAMETER NAME="Use_RSTA_Pin" VALUE="true"/>
+        <PARAMETER NAME="Reset_Memory_Latch_A" VALUE="false"/>
+        <PARAMETER NAME="Reset_Priority_A" VALUE="CE"/>
+        <PARAMETER NAME="Output_Reset_Value_A" VALUE="0"/>
+        <PARAMETER NAME="Use_RSTB_Pin" VALUE="true"/>
+        <PARAMETER NAME="Reset_Memory_Latch_B" VALUE="false"/>
+        <PARAMETER NAME="Reset_Priority_B" VALUE="CE"/>
+        <PARAMETER NAME="Output_Reset_Value_B" VALUE="0"/>
+        <PARAMETER NAME="Reset_Type" VALUE="SYNC"/>
+        <PARAMETER NAME="Additional_Inputs_for_Power_Estimation" VALUE="false"/>
+        <PARAMETER NAME="Port_A_Clock" VALUE="100"/>
+        <PARAMETER NAME="Port_A_Write_Rate" VALUE="50"/>
+        <PARAMETER NAME="Port_B_Clock" VALUE="100"/>
+        <PARAMETER NAME="Port_B_Write_Rate" VALUE="50"/>
+        <PARAMETER NAME="Port_A_Enable_Rate" VALUE="100"/>
+        <PARAMETER NAME="Port_B_Enable_Rate" VALUE="100"/>
+        <PARAMETER NAME="Collision_Warnings" VALUE="ALL"/>
+        <PARAMETER NAME="Disable_Collision_Warnings" VALUE="false"/>
+        <PARAMETER NAME="Disable_Out_of_Range_Warnings" VALUE="false"/>
+        <PARAMETER NAME="use_bram_block" VALUE="BRAM_Controller"/>
+        <PARAMETER NAME="MEM_FILE" VALUE="base_microblaze_design_lmb_bram_0.mem"/>
+        <PARAMETER NAME="CTRL_ECC_ALGO" VALUE="NONE"/>
+        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
+      </PARAMETERS>
+      <PORTS>
+        <PORT DIR="I" NAME="clka" SIGIS="undef" SIGNAME="microblaze_0_local_memory_dlmb_bram_if_cntlr_BRAM_Clk_A">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_bram_if_cntlr" PORT="BRAM_Clk_A"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="rsta" SIGIS="undef" SIGNAME="microblaze_0_local_memory_dlmb_bram_if_cntlr_BRAM_Rst_A">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_bram_if_cntlr" PORT="BRAM_Rst_A"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="ena" SIGIS="undef" SIGNAME="microblaze_0_local_memory_dlmb_bram_if_cntlr_BRAM_EN_A">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_bram_if_cntlr" PORT="BRAM_EN_A"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="3" NAME="wea" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_local_memory_dlmb_bram_if_cntlr_BRAM_WEN_A">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_bram_if_cntlr" PORT="BRAM_WEN_A"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="31" NAME="addra" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_local_memory_dlmb_bram_if_cntlr_BRAM_Addr_A">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_bram_if_cntlr" PORT="BRAM_Addr_A"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="31" NAME="dina" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_local_memory_dlmb_bram_if_cntlr_BRAM_Dout_A">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_bram_if_cntlr" PORT="BRAM_Dout_A"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="31" NAME="douta" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_local_memory_dlmb_bram_if_cntlr_BRAM_Din_A">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_bram_if_cntlr" PORT="BRAM_Din_A"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="clkb" SIGIS="undef" SIGNAME="microblaze_0_local_memory_ilmb_bram_if_cntlr_BRAM_Clk_A">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_bram_if_cntlr" PORT="BRAM_Clk_A"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="rstb" SIGIS="undef" SIGNAME="microblaze_0_local_memory_ilmb_bram_if_cntlr_BRAM_Rst_A">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_bram_if_cntlr" PORT="BRAM_Rst_A"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="enb" SIGIS="undef" SIGNAME="microblaze_0_local_memory_ilmb_bram_if_cntlr_BRAM_EN_A">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_bram_if_cntlr" PORT="BRAM_EN_A"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="3" NAME="web" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_local_memory_ilmb_bram_if_cntlr_BRAM_WEN_A">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_bram_if_cntlr" PORT="BRAM_WEN_A"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="31" NAME="addrb" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_local_memory_ilmb_bram_if_cntlr_BRAM_Addr_A">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_bram_if_cntlr" PORT="BRAM_Addr_A"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="31" NAME="dinb" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_local_memory_ilmb_bram_if_cntlr_BRAM_Dout_A">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_bram_if_cntlr" PORT="BRAM_Dout_A"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="31" NAME="doutb" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_local_memory_ilmb_bram_if_cntlr_BRAM_Din_A">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_bram_if_cntlr" PORT="BRAM_Din_A"/>
+          </CONNECTIONS>
+        </PORT>
+      </PORTS>
+      <BUSINTERFACES>
+        <BUSINTERFACE BUSNAME="microblaze_0_local_memory_dlmb_bram_if_cntlr_BRAM_PORT" NAME="BRAM_PORTA" TYPE="TARGET">
+          <PORTMAPS>
+            <PORTMAP PHYSICAL="addra"/>
+            <PORTMAP PHYSICAL="clka"/>
+            <PORTMAP PHYSICAL="dina"/>
+            <PORTMAP PHYSICAL="douta"/>
+            <PORTMAP PHYSICAL="ena"/>
+            <PORTMAP PHYSICAL="rsta"/>
+            <PORTMAP PHYSICAL="wea"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="microblaze_0_local_memory_ilmb_bram_if_cntlr_BRAM_PORT" NAME="BRAM_PORTB" TYPE="TARGET">
+          <PORTMAPS>
+            <PORTMAP PHYSICAL="addrb"/>
+            <PORTMAP PHYSICAL="clkb"/>
+            <PORTMAP PHYSICAL="dinb"/>
+            <PORTMAP PHYSICAL="doutb"/>
+            <PORTMAP PHYSICAL="enb"/>
+            <PORTMAP PHYSICAL="rstb"/>
+            <PORTMAP PHYSICAL="web"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+      </BUSINTERFACES>
+    </MODULE>
+    <MODULE FULLNAME="/mig_7series_0" HWVERSION="2.3" INSTANCE="mig_7series_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="MEMORY_CNTLR" MODTYPE="mig_7series" VLNV="xilinx.com:ip:mig_7series:2.3">
+      <DOCUMENTS/>
+      <PARAMETERS>
+        <PARAMETER NAME="NoOfControllers" VALUE="1"/>
+        <PARAMETER NAME="COMBINED_INTERFACE" VALUE="0"/>
+        <PARAMETER NAME="REFCLK_TYPE" VALUE="NONE"/>
+        <PARAMETER NAME="MEM_TYPE" VALUE="DDR3"/>
+        <PARAMETER NAME="TEMP_MON_CONTROL" VALUE="INTERNAL"/>
+        <PARAMETER NAME="POLARITY" VALUE="ACTIVE_HIGH"/>
+        <PARAMETER NAME="IS_CLK_SHARED" VALUE="FALSE"/>
+        <PARAMETER NAME="SYSCLK_TYPE" VALUE="DIFF"/>
+        <PARAMETER NAME="USE_AXI" VALUE="1"/>
+        <PARAMETER NAME="ECC" VALUE="OFF"/>
+        <PARAMETER NAME="DDR3_DQ_WIDTH" VALUE="64"/>
+        <PARAMETER NAME="DDR3_DQS_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="DDR3_ROW_WIDTH" VALUE="14"/>
+        <PARAMETER NAME="DDR3_BANK_WIDTH" VALUE="3"/>
+        <PARAMETER NAME="DDR3_CK_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="DDR3_CKE_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="DDR3_CS_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="DDR3_nCS_PER_RANK" VALUE="1"/>
+        <PARAMETER NAME="DDR3_DM_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="DDR3_ODT_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="DDR3_USE_CS_PORT" VALUE="1"/>
+        <PARAMETER NAME="DDR3_USE_DM_PORT" VALUE="1"/>
+        <PARAMETER NAME="DDR3_USE_ODT_PORT" VALUE="1"/>
+        <PARAMETER NAME="DDR3_REG_CTRL" VALUE="OFF"/>
+        <PARAMETER NAME="DDR3_DQS_CNT_WIDTH" VALUE="3"/>
+        <PARAMETER NAME="DDR3_DEBUG_PORT" VALUE="OFF"/>
+        <PARAMETER NAME="DDR2_DQ_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="DDR2_DQS_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="DDR2_ROW_WIDTH" VALUE="14"/>
+        <PARAMETER NAME="DDR2_BANK_WIDTH" VALUE="3"/>
+        <PARAMETER NAME="DDR2_CK_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="DDR2_CKE_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="DDR2_CS_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="DDR2_nCS_PER_RANK" VALUE="1"/>
+        <PARAMETER NAME="DDR2_DM_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="DDR2_ODT_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="DDR2_USE_CS_PORT" VALUE="1"/>
+        <PARAMETER NAME="DDR2_USE_DM_PORT" VALUE="1"/>
+        <PARAMETER NAME="DDR2_USE_ODT_PORT" VALUE="1"/>
+        <PARAMETER NAME="DDR2_REG_CTRL" VALUE="OFF"/>
+        <PARAMETER NAME="DDR2_DQS_CNT_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="DDR2_DEBUG_PORT" VALUE="OFF"/>
+        <PARAMETER NAME="LPDDR2_DQ_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="LPDDR2_DQS_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="LPDDR2_ROW_WIDTH" VALUE="14"/>
+        <PARAMETER NAME="LPDDR2_BANK_WIDTH" VALUE="3"/>
+        <PARAMETER NAME="LPDDR2_CK_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="LPDDR2_CKE_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="LPDDR2_CS_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="LPDDR2_nCS_PER_RANK" VALUE="1"/>
+        <PARAMETER NAME="LPDDR2_DM_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="LPDDR2_USE_CS_PORT" VALUE="1"/>
+        <PARAMETER NAME="LPDDR2_USE_DM_PORT" VALUE="1"/>
+        <PARAMETER NAME="LPDDR2_USE_ODT_PORT" VALUE="1"/>
+        <PARAMETER NAME="LPDDR2_REG_CTRL" VALUE="OFF"/>
+        <PARAMETER NAME="LPDDR2_DQS_CNT_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="LPDDR2_DEBUG_PORT" VALUE="OFF"/>
+        <PARAMETER NAME="DQS_CNT_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="DEBUG_PORT" VALUE="OFF"/>
+        <PARAMETER NAME="DDRX_ADDR_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="DDRX_nCK_PER_CLK" VALUE="2"/>
+        <PARAMETER NAME="DDRX_DATA_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="DDR3_ADDR_WIDTH" VALUE="28"/>
+        <PARAMETER NAME="DDR3_nCK_PER_CLK" VALUE="4"/>
+        <PARAMETER NAME="DDR3_DATA_WIDTH" VALUE="64"/>
+        <PARAMETER NAME="DDR2_ADDR_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="DDR2_nCK_PER_CLK" VALUE="2"/>
+        <PARAMETER NAME="DDR2_DATA_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="LPDDR2_ADDR_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="LPDDR2_nCK_PER_CLK" VALUE="2"/>
+        <PARAMETER NAME="LPDDR2_DATA_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="FREQ_HZ" VALUE="100000000"/>
+        <PARAMETER NAME="PHASE" VALUE="0.000"/>
+        <PARAMETER NAME="UI_EXTRA_CLOCKS" VALUE="FALSE"/>
+        <PARAMETER NAME="MMCM_VCO" VALUE="800"/>
+        <PARAMETER NAME="MMCM_CLKOUT0_FREQ" VALUE="10.0"/>
+        <PARAMETER NAME="MMCM_CLKOUT1_FREQ" VALUE="10"/>
+        <PARAMETER NAME="MMCM_CLKOUT2_FREQ" VALUE="10"/>
+        <PARAMETER NAME="MMCM_CLKOUT3_FREQ" VALUE="10"/>
+        <PARAMETER NAME="MMCM_CLKOUT4_FREQ" VALUE="10"/>
+        <PARAMETER NAME="MMCM_CLKOUT0_EN" VALUE="FALSE"/>
+        <PARAMETER NAME="MMCM_CLKOUT2_EN" VALUE="FALSE"/>
+        <PARAMETER NAME="MMCM_CLKOUT1_EN" VALUE="FALSE"/>
+        <PARAMETER NAME="MMCM_CLKOUT3_EN" VALUE="FALSE"/>
+        <PARAMETER NAME="MMCM_CLKOUT4_EN" VALUE="FALSE"/>
+        <PARAMETER NAME="C_S_AXI_CTRL_ID_WIDTH" VALUE="4"/>
+        <PARAMETER NAME="C_S_AXI_CTRL_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_S_AXI_CTRL_ADDR_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_S_AXI_CTRL_MEM_SIZE" VALUE="1048576"/>
+        <PARAMETER NAME="C_S_AXI_ID_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C_S_AXI_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_S_AXI_ADDR_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_S_AXI_MEM_SIZE" VALUE="1073741824"/>
+        <PARAMETER NAME="QDRIIP_NUM_DEVICES" VALUE="1"/>
+        <PARAMETER NAME="QDRIIP_DATA_WIDTH" VALUE="18"/>
+        <PARAMETER NAME="QDRIIP_ADDR_WIDTH" VALUE="29"/>
+        <PARAMETER NAME="QDRIIP_BW_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="QDRIIP_DEBUG_PORT" VALUE="OFF"/>
+        <PARAMETER NAME="QDRIIP_BURST_LEN" VALUE="1"/>
+        <PARAMETER NAME="RLDII_NUM_DEVICES" VALUE="1"/>
+        <PARAMETER NAME="RLDII_DATA_WIDTH" VALUE="18"/>
+        <PARAMETER NAME="RLDII_RLD_ADDR_WIDTH" VALUE="29"/>
+        <PARAMETER NAME="RLDII_QK_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="RLDII_CK_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="RLDII_DK_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="RLDII_DM_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="RLDII_BANK_WIDTH" VALUE="2"/>
+        <PARAMETER NAME="RLDII_QVLD_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="RLDII_DEBUG_PORT" VALUE="OFF"/>
+        <PARAMETER NAME="RLDIII_NUM_DEVICES" VALUE="1"/>
+        <PARAMETER NAME="RLDIII_DATA_WIDTH" VALUE="18"/>
+        <PARAMETER NAME="RLDIII_RLD_ADDR_WIDTH" VALUE="29"/>
+        <PARAMETER NAME="RLDIII_QK_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="RLDIII_CK_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="RLDIII_DK_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="RLDIII_DM_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="RLDIII_BANK_WIDTH" VALUE="2"/>
+        <PARAMETER NAME="RLDIII_QVLD_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="RLDIII_DEBUG_PORT" VALUE="OFF"/>
+        <PARAMETER NAME="RLDX_CMD_PER_CLK" VALUE="1"/>
+        <PARAMETER NAME="RLDX_DATA_WIDTH" VALUE="18"/>
+        <PARAMETER NAME="RLDX_ADDR_WIDTH" VALUE="29"/>
+        <PARAMETER NAME="RLDX_BANK_WIDTH" VALUE="2"/>
+        <PARAMETER NAME="RLDX_nCK_PER_CLK" VALUE="1"/>
+        <PARAMETER NAME="RLDX_DM_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="RLDII_CMD_PER_CLK" VALUE="1"/>
+        <PARAMETER NAME="RLDII_ADDR_WIDTH" VALUE="29"/>
+        <PARAMETER NAME="RLDII_nCK_PER_CLK" VALUE="1"/>
+        <PARAMETER NAME="RLDIII_CMD_PER_CLK" VALUE="1"/>
+        <PARAMETER NAME="RLDIII_ADDR_WIDTH" VALUE="29"/>
+        <PARAMETER NAME="RLDIII_nCK_PER_CLK" VALUE="1"/>
+        <PARAMETER NAME="C0_MEM_TYPE" VALUE="DDR3"/>
+        <PARAMETER NAME="C0_IS_CLK_SHARED" VALUE="FALSE"/>
+        <PARAMETER NAME="C0_SYSCLK_TYPE" VALUE="DIFF"/>
+        <PARAMETER NAME="C0_USE_AXI" VALUE="0"/>
+        <PARAMETER NAME="C0_ECC" VALUE="OFF"/>
+        <PARAMETER NAME="C0_DDR3_DQ_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="C0_DDR3_DQS_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C0_DDR3_ROW_WIDTH" VALUE="14"/>
+        <PARAMETER NAME="C0_DDR3_BANK_WIDTH" VALUE="3"/>
+        <PARAMETER NAME="C0_DDR3_CK_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C0_DDR3_CKE_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C0_DDR3_CS_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C0_DDR3_nCS_PER_RANK" VALUE="1"/>
+        <PARAMETER NAME="C0_DDR3_DM_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C0_DDR3_ODT_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C0_DDR3_USE_CS_PORT" VALUE="1"/>
+        <PARAMETER NAME="C0_DDR3_USE_DM_PORT" VALUE="1"/>
+        <PARAMETER NAME="C0_DDR3_USE_ODT_PORT" VALUE="1"/>
+        <PARAMETER NAME="C0_DDR3_REG_CTRL" VALUE="OFF"/>
+        <PARAMETER NAME="C0_DDR3_DQS_CNT_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C0_DDR3_DEBUG_PORT" VALUE="OFF"/>
+        <PARAMETER NAME="C0_DDR2_DQ_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="C0_DDR2_DQS_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C0_DDR2_ROW_WIDTH" VALUE="14"/>
+        <PARAMETER NAME="C0_DDR2_BANK_WIDTH" VALUE="3"/>
+        <PARAMETER NAME="C0_DDR2_CK_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C0_DDR2_CKE_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C0_DDR2_CS_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C0_DDR2_nCS_PER_RANK" VALUE="1"/>
+        <PARAMETER NAME="C0_DDR2_DM_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C0_DDR2_ODT_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C0_DDR2_USE_CS_PORT" VALUE="1"/>
+        <PARAMETER NAME="C0_DDR2_USE_DM_PORT" VALUE="1"/>
+        <PARAMETER NAME="C0_DDR2_USE_ODT_PORT" VALUE="1"/>
+        <PARAMETER NAME="C0_DDR2_REG_CTRL" VALUE="OFF"/>
+        <PARAMETER NAME="C0_DDR2_DQS_CNT_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C0_DDR2_DEBUG_PORT" VALUE="OFF"/>
+        <PARAMETER NAME="C0_LPDDR2_DQ_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="C0_LPDDR2_DQS_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C0_LPDDR2_ROW_WIDTH" VALUE="14"/>
+        <PARAMETER NAME="C0_LPDDR2_BANK_WIDTH" VALUE="3"/>
+        <PARAMETER NAME="C0_LPDDR2_CK_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C0_LPDDR2_CKE_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C0_LPDDR2_CS_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C0_LPDDR2_nCS_PER_RANK" VALUE="1"/>
+        <PARAMETER NAME="C0_LPDDR2_DM_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C0_LPDDR2_USE_CS_PORT" VALUE="1"/>
+        <PARAMETER NAME="C0_LPDDR2_USE_DM_PORT" VALUE="1"/>
+        <PARAMETER NAME="C0_LPDDR2_USE_ODT_PORT" VALUE="1"/>
+        <PARAMETER NAME="C0_LPDDR2_REG_CTRL" VALUE="OFF"/>
+        <PARAMETER NAME="C0_LPDDR2_DQS_CNT_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C0_LPDDR2_DEBUG_PORT" VALUE="OFF"/>
+        <PARAMETER NAME="C0_DQS_CNT_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C0_DEBUG_PORT" VALUE="OFF"/>
+        <PARAMETER NAME="C0_DDRX_ADDR_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="C0_DDRX_nCK_PER_CLK" VALUE="2"/>
+        <PARAMETER NAME="C0_DDRX_DATA_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="C0_DDR3_ADDR_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="C0_DDR3_nCK_PER_CLK" VALUE="2"/>
+        <PARAMETER NAME="C0_DDR3_DATA_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="C0_DDR2_ADDR_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="C0_DDR2_nCK_PER_CLK" VALUE="2"/>
+        <PARAMETER NAME="C0_DDR2_DATA_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="C0_LPDDR2_ADDR_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="C0_LPDDR2_nCK_PER_CLK" VALUE="2"/>
+        <PARAMETER NAME="C0_LPDDR2_DATA_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="C0_FREQ_HZ" VALUE="100.0"/>
+        <PARAMETER NAME="C0_PHASE" VALUE="0.000"/>
+        <PARAMETER NAME="C0_UI_EXTRA_CLOCKS" VALUE="FALSE"/>
+        <PARAMETER NAME="C0_MMCM_VCO" VALUE="1200.0"/>
+        <PARAMETER NAME="C0_MMCM_CLKOUT0_FREQ" VALUE="10.0"/>
+        <PARAMETER NAME="C0_MMCM_CLKOUT1_FREQ" VALUE="10"/>
+        <PARAMETER NAME="C0_MMCM_CLKOUT2_FREQ" VALUE="10"/>
+        <PARAMETER NAME="C0_MMCM_CLKOUT3_FREQ" VALUE="10"/>
+        <PARAMETER NAME="C0_MMCM_CLKOUT4_FREQ" VALUE="10"/>
+        <PARAMETER NAME="C0_MMCM_CLKOUT0_EN" VALUE="FALSE"/>
+        <PARAMETER NAME="C0_MMCM_CLKOUT2_EN" VALUE="FALSE"/>
+        <PARAMETER NAME="C0_MMCM_CLKOUT1_EN" VALUE="FALSE"/>
+        <PARAMETER NAME="C0_MMCM_CLKOUT3_EN" VALUE="FALSE"/>
+        <PARAMETER NAME="C0_MMCM_CLKOUT4_EN" VALUE="FALSE"/>
+        <PARAMETER NAME="C0_C_S_AXI_CTRL_ID_WIDTH" VALUE="4"/>
+        <PARAMETER NAME="C0_C_S_AXI_CTRL_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C0_C_S_AXI_CTRL_ADDR_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C0_C_S_AXI_CTRL_MEM_SIZE" VALUE="1048576"/>
+        <PARAMETER NAME="C0_C_S_AXI_ID_WIDTH" VALUE="4"/>
+        <PARAMETER NAME="C0_C_S_AXI_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C0_C_S_AXI_ADDR_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C0_C_S_AXI_MEM_SIZE" VALUE="1048576"/>
+        <PARAMETER NAME="C0_QDRIIP_NUM_DEVICES" VALUE="1"/>
+        <PARAMETER NAME="C0_QDRIIP_DATA_WIDTH" VALUE="18"/>
+        <PARAMETER NAME="C0_QDRIIP_ADDR_WIDTH" VALUE="29"/>
+        <PARAMETER NAME="C0_QDRIIP_BW_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="C0_QDRIIP_DEBUG_PORT" VALUE="OFF"/>
+        <PARAMETER NAME="C0_QDRIIP_BURST_LEN" VALUE="1"/>
+        <PARAMETER NAME="C0_RLDII_NUM_DEVICES" VALUE="1"/>
+        <PARAMETER NAME="C0_RLDII_DATA_WIDTH" VALUE="18"/>
+        <PARAMETER NAME="C0_RLDII_RLD_ADDR_WIDTH" VALUE="29"/>
+        <PARAMETER NAME="C0_RLDII_QK_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="C0_RLDII_CK_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C0_RLDII_DK_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C0_RLDII_DM_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C0_RLDII_BANK_WIDTH" VALUE="2"/>
+        <PARAMETER NAME="C0_RLDII_QVLD_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C0_RLDII_DEBUG_PORT" VALUE="OFF"/>
+        <PARAMETER NAME="C0_RLDIII_NUM_DEVICES" VALUE="1"/>
+        <PARAMETER NAME="C0_RLDIII_DATA_WIDTH" VALUE="18"/>
+        <PARAMETER NAME="C0_RLDIII_RLD_ADDR_WIDTH" VALUE="29"/>
+        <PARAMETER NAME="C0_RLDIII_QK_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="C0_RLDIII_CK_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C0_RLDIII_DK_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C0_RLDIII_DM_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C0_RLDIII_BANK_WIDTH" VALUE="2"/>
+        <PARAMETER NAME="C0_RLDIII_QVLD_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C0_RLDIII_DEBUG_PORT" VALUE="OFF"/>
+        <PARAMETER NAME="C0_RLDX_CMD_PER_CLK" VALUE="1"/>
+        <PARAMETER NAME="C0_RLDX_DATA_WIDTH" VALUE="18"/>
+        <PARAMETER NAME="C0_RLDX_ADDR_WIDTH" VALUE="29"/>
+        <PARAMETER NAME="C0_RLDX_BANK_WIDTH" VALUE="2"/>
+        <PARAMETER NAME="C0_RLDX_nCK_PER_CLK" VALUE="1"/>
+        <PARAMETER NAME="C0_RLDX_DM_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C0_RLDII_CMD_PER_CLK" VALUE="1"/>
+        <PARAMETER NAME="C0_RLDII_ADDR_WIDTH" VALUE="29"/>
+        <PARAMETER NAME="C0_RLDII_nCK_PER_CLK" VALUE="1"/>
+        <PARAMETER NAME="C0_RLDIII_CMD_PER_CLK" VALUE="1"/>
+        <PARAMETER NAME="C0_RLDIII_ADDR_WIDTH" VALUE="29"/>
+        <PARAMETER NAME="C0_RLDIII_nCK_PER_CLK" VALUE="1"/>
+        <PARAMETER NAME="C0_POLARITY" VALUE="ACTIVE_LOW"/>
+        <PARAMETER NAME="C1_MEM_TYPE" VALUE="DDR3"/>
+        <PARAMETER NAME="C1_IS_CLK_SHARED" VALUE="FALSE"/>
+        <PARAMETER NAME="C1_SYSCLK_TYPE" VALUE="DIFF"/>
+        <PARAMETER NAME="C1_USE_AXI" VALUE="0"/>
+        <PARAMETER NAME="C1_ECC" VALUE="OFF"/>
+        <PARAMETER NAME="C1_DDR3_DQ_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="C1_DDR3_DQS_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C1_DDR3_ROW_WIDTH" VALUE="14"/>
+        <PARAMETER NAME="C1_DDR3_BANK_WIDTH" VALUE="3"/>
+        <PARAMETER NAME="C1_DDR3_CK_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C1_DDR3_CKE_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C1_DDR3_CS_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C1_DDR3_nCS_PER_RANK" VALUE="1"/>
+        <PARAMETER NAME="C1_DDR3_DM_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C1_DDR3_ODT_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C1_DDR3_USE_CS_PORT" VALUE="1"/>
+        <PARAMETER NAME="C1_DDR3_USE_DM_PORT" VALUE="1"/>
+        <PARAMETER NAME="C1_DDR3_USE_ODT_PORT" VALUE="1"/>
+        <PARAMETER NAME="C1_DDR3_REG_CTRL" VALUE="OFF"/>
+        <PARAMETER NAME="C1_DDR3_DQS_CNT_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C1_DDR3_DEBUG_PORT" VALUE="OFF"/>
+        <PARAMETER NAME="C1_DDR2_DQ_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="C1_DDR2_DQS_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C1_DDR2_ROW_WIDTH" VALUE="14"/>
+        <PARAMETER NAME="C1_DDR2_BANK_WIDTH" VALUE="3"/>
+        <PARAMETER NAME="C1_DDR2_CK_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C1_DDR2_CKE_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C1_DDR2_CS_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C1_DDR2_nCS_PER_RANK" VALUE="1"/>
+        <PARAMETER NAME="C1_DDR2_DM_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C1_DDR2_ODT_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C1_DDR2_USE_CS_PORT" VALUE="1"/>
+        <PARAMETER NAME="C1_DDR2_USE_DM_PORT" VALUE="1"/>
+        <PARAMETER NAME="C1_DDR2_USE_ODT_PORT" VALUE="1"/>
+        <PARAMETER NAME="C1_DDR2_REG_CTRL" VALUE="OFF"/>
+        <PARAMETER NAME="C1_DDR2_DQS_CNT_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C1_DDR2_DEBUG_PORT" VALUE="OFF"/>
+        <PARAMETER NAME="C1_LPDDR2_DQ_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="C1_LPDDR2_DQS_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C1_LPDDR2_ROW_WIDTH" VALUE="14"/>
+        <PARAMETER NAME="C1_LPDDR2_BANK_WIDTH" VALUE="3"/>
+        <PARAMETER NAME="C1_LPDDR2_CK_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C1_LPDDR2_CKE_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C1_LPDDR2_CS_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C1_LPDDR2_nCS_PER_RANK" VALUE="1"/>
+        <PARAMETER NAME="C1_LPDDR2_DM_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C1_LPDDR2_USE_CS_PORT" VALUE="1"/>
+        <PARAMETER NAME="C1_LPDDR2_USE_DM_PORT" VALUE="1"/>
+        <PARAMETER NAME="C1_LPDDR2_USE_ODT_PORT" VALUE="1"/>
+        <PARAMETER NAME="C1_LPDDR2_REG_CTRL" VALUE="OFF"/>
+        <PARAMETER NAME="C1_LPDDR2_DQS_CNT_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C1_LPDDR2_DEBUG_PORT" VALUE="OFF"/>
+        <PARAMETER NAME="C1_DQS_CNT_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C1_DEBUG_PORT" VALUE="OFF"/>
+        <PARAMETER NAME="C1_DDRX_ADDR_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="C1_DDRX_nCK_PER_CLK" VALUE="2"/>
+        <PARAMETER NAME="C1_DDRX_DATA_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="C1_DDR3_ADDR_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="C1_DDR3_nCK_PER_CLK" VALUE="2"/>
+        <PARAMETER NAME="C1_DDR3_DATA_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="C1_DDR2_ADDR_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="C1_DDR2_nCK_PER_CLK" VALUE="2"/>
+        <PARAMETER NAME="C1_DDR2_DATA_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="C1_LPDDR2_ADDR_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="C1_LPDDR2_nCK_PER_CLK" VALUE="2"/>
+        <PARAMETER NAME="C1_LPDDR2_DATA_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="C1_FREQ_HZ" VALUE="100.0"/>
+        <PARAMETER NAME="C1_PHASE" VALUE="0.000"/>
+        <PARAMETER NAME="C1_UI_EXTRA_CLOCKS" VALUE="FALSE"/>
+        <PARAMETER NAME="C1_MMCM_VCO" VALUE="1200.0"/>
+        <PARAMETER NAME="C1_MMCM_CLKOUT0_FREQ" VALUE="10.0"/>
+        <PARAMETER NAME="C1_MMCM_CLKOUT1_FREQ" VALUE="10"/>
+        <PARAMETER NAME="C1_MMCM_CLKOUT2_FREQ" VALUE="10"/>
+        <PARAMETER NAME="C1_MMCM_CLKOUT3_FREQ" VALUE="10"/>
+        <PARAMETER NAME="C1_MMCM_CLKOUT4_FREQ" VALUE="10"/>
+        <PARAMETER NAME="C1_MMCM_CLKOUT0_EN" VALUE="FALSE"/>
+        <PARAMETER NAME="C1_MMCM_CLKOUT2_EN" VALUE="FALSE"/>
+        <PARAMETER NAME="C1_MMCM_CLKOUT1_EN" VALUE="FALSE"/>
+        <PARAMETER NAME="C1_MMCM_CLKOUT3_EN" VALUE="FALSE"/>
+        <PARAMETER NAME="C1_MMCM_CLKOUT4_EN" VALUE="FALSE"/>
+        <PARAMETER NAME="C1_C_S_AXI_CTRL_ID_WIDTH" VALUE="4"/>
+        <PARAMETER NAME="C1_C_S_AXI_CTRL_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C1_C_S_AXI_CTRL_ADDR_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C1_C_S_AXI_CTRL_MEM_SIZE" VALUE="1048576"/>
+        <PARAMETER NAME="C1_C_S_AXI_ID_WIDTH" VALUE="4"/>
+        <PARAMETER NAME="C1_C_S_AXI_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C1_C_S_AXI_ADDR_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C1_C_S_AXI_MEM_SIZE" VALUE="1048576"/>
+        <PARAMETER NAME="C1_QDRIIP_NUM_DEVICES" VALUE="1"/>
+        <PARAMETER NAME="C1_QDRIIP_DATA_WIDTH" VALUE="18"/>
+        <PARAMETER NAME="C1_QDRIIP_ADDR_WIDTH" VALUE="29"/>
+        <PARAMETER NAME="C1_QDRIIP_BW_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="C1_QDRIIP_DEBUG_PORT" VALUE="OFF"/>
+        <PARAMETER NAME="C1_QDRIIP_BURST_LEN" VALUE="1"/>
+        <PARAMETER NAME="C1_RLDII_NUM_DEVICES" VALUE="1"/>
+        <PARAMETER NAME="C1_RLDII_DATA_WIDTH" VALUE="18"/>
+        <PARAMETER NAME="C1_RLDII_RLD_ADDR_WIDTH" VALUE="29"/>
+        <PARAMETER NAME="C1_RLDII_QK_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="C1_RLDII_CK_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C1_RLDII_DK_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C1_RLDII_DM_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C1_RLDII_BANK_WIDTH" VALUE="2"/>
+        <PARAMETER NAME="C1_RLDII_QVLD_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C1_RLDII_DEBUG_PORT" VALUE="OFF"/>
+        <PARAMETER NAME="C1_RLDIII_NUM_DEVICES" VALUE="1"/>
+        <PARAMETER NAME="C1_RLDIII_DATA_WIDTH" VALUE="18"/>
+        <PARAMETER NAME="C1_RLDIII_RLD_ADDR_WIDTH" VALUE="29"/>
+        <PARAMETER NAME="C1_RLDIII_QK_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="C1_RLDIII_CK_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C1_RLDIII_DK_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C1_RLDIII_DM_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C1_RLDIII_BANK_WIDTH" VALUE="2"/>
+        <PARAMETER NAME="C1_RLDIII_QVLD_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C1_RLDIII_DEBUG_PORT" VALUE="OFF"/>
+        <PARAMETER NAME="C1_RLDX_CMD_PER_CLK" VALUE="1"/>
+        <PARAMETER NAME="C1_RLDX_DATA_WIDTH" VALUE="18"/>
+        <PARAMETER NAME="C1_RLDX_ADDR_WIDTH" VALUE="29"/>
+        <PARAMETER NAME="C1_RLDX_BANK_WIDTH" VALUE="2"/>
+        <PARAMETER NAME="C1_RLDX_nCK_PER_CLK" VALUE="1"/>
+        <PARAMETER NAME="C1_RLDX_DM_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C1_RLDII_CMD_PER_CLK" VALUE="1"/>
+        <PARAMETER NAME="C1_RLDII_ADDR_WIDTH" VALUE="29"/>
+        <PARAMETER NAME="C1_RLDII_nCK_PER_CLK" VALUE="1"/>
+        <PARAMETER NAME="C1_RLDIII_CMD_PER_CLK" VALUE="1"/>
+        <PARAMETER NAME="C1_RLDIII_ADDR_WIDTH" VALUE="29"/>
+        <PARAMETER NAME="C1_RLDIII_nCK_PER_CLK" VALUE="1"/>
+        <PARAMETER NAME="C1_POLARITY" VALUE="ACTIVE_LOW"/>
+        <PARAMETER NAME="C2_MEM_TYPE" VALUE="DDR3"/>
+        <PARAMETER NAME="C2_IS_CLK_SHARED" VALUE="FALSE"/>
+        <PARAMETER NAME="C2_SYSCLK_TYPE" VALUE="DIFF"/>
+        <PARAMETER NAME="C2_USE_AXI" VALUE="0"/>
+        <PARAMETER NAME="C2_ECC" VALUE="OFF"/>
+        <PARAMETER NAME="C2_DDR3_DQ_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="C2_DDR3_DQS_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C2_DDR3_ROW_WIDTH" VALUE="14"/>
+        <PARAMETER NAME="C2_DDR3_BANK_WIDTH" VALUE="3"/>
+        <PARAMETER NAME="C2_DDR3_CK_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C2_DDR3_CKE_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C2_DDR3_CS_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C2_DDR3_nCS_PER_RANK" VALUE="1"/>
+        <PARAMETER NAME="C2_DDR3_DM_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C2_DDR3_ODT_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C2_DDR3_USE_CS_PORT" VALUE="1"/>
+        <PARAMETER NAME="C2_DDR3_USE_DM_PORT" VALUE="1"/>
+        <PARAMETER NAME="C2_DDR3_USE_ODT_PORT" VALUE="1"/>
+        <PARAMETER NAME="C2_DDR3_REG_CTRL" VALUE="OFF"/>
+        <PARAMETER NAME="C2_DDR3_DQS_CNT_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C2_DDR3_DEBUG_PORT" VALUE="OFF"/>
+        <PARAMETER NAME="C2_DDR2_DQ_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="C2_DDR2_DQS_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C2_DDR2_ROW_WIDTH" VALUE="14"/>
+        <PARAMETER NAME="C2_DDR2_BANK_WIDTH" VALUE="3"/>
+        <PARAMETER NAME="C2_DDR2_CK_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C2_DDR2_CKE_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C2_DDR2_CS_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C2_DDR2_nCS_PER_RANK" VALUE="1"/>
+        <PARAMETER NAME="C2_DDR2_DM_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C2_DDR2_ODT_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C2_DDR2_USE_CS_PORT" VALUE="1"/>
+        <PARAMETER NAME="C2_DDR2_USE_DM_PORT" VALUE="1"/>
+        <PARAMETER NAME="C2_DDR2_USE_ODT_PORT" VALUE="1"/>
+        <PARAMETER NAME="C2_DDR2_REG_CTRL" VALUE="OFF"/>
+        <PARAMETER NAME="C2_DDR2_DQS_CNT_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C2_DDR2_DEBUG_PORT" VALUE="OFF"/>
+        <PARAMETER NAME="C2_LPDDR2_DQ_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="C2_LPDDR2_DQS_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C2_LPDDR2_ROW_WIDTH" VALUE="14"/>
+        <PARAMETER NAME="C2_LPDDR2_BANK_WIDTH" VALUE="3"/>
+        <PARAMETER NAME="C2_LPDDR2_CK_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C2_LPDDR2_CKE_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C2_LPDDR2_CS_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C2_LPDDR2_nCS_PER_RANK" VALUE="1"/>
+        <PARAMETER NAME="C2_LPDDR2_DM_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C2_LPDDR2_USE_CS_PORT" VALUE="1"/>
+        <PARAMETER NAME="C2_LPDDR2_USE_DM_PORT" VALUE="1"/>
+        <PARAMETER NAME="C2_LPDDR2_USE_ODT_PORT" VALUE="1"/>
+        <PARAMETER NAME="C2_LPDDR2_REG_CTRL" VALUE="OFF"/>
+        <PARAMETER NAME="C2_LPDDR2_DQS_CNT_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C2_LPDDR2_DEBUG_PORT" VALUE="OFF"/>
+        <PARAMETER NAME="C2_DQS_CNT_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C2_DEBUG_PORT" VALUE="OFF"/>
+        <PARAMETER NAME="C2_DDRX_ADDR_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="C2_DDRX_nCK_PER_CLK" VALUE="2"/>
+        <PARAMETER NAME="C2_DDRX_DATA_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="C2_DDR3_ADDR_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="C2_DDR3_nCK_PER_CLK" VALUE="2"/>
+        <PARAMETER NAME="C2_DDR3_DATA_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="C2_DDR2_ADDR_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="C2_DDR2_nCK_PER_CLK" VALUE="2"/>
+        <PARAMETER NAME="C2_DDR2_DATA_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="C2_LPDDR2_ADDR_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="C2_LPDDR2_nCK_PER_CLK" VALUE="2"/>
+        <PARAMETER NAME="C2_LPDDR2_DATA_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="C2_FREQ_HZ" VALUE="100.0"/>
+        <PARAMETER NAME="C2_PHASE" VALUE="0.000"/>
+        <PARAMETER NAME="C2_UI_EXTRA_CLOCKS" VALUE="FALSE"/>
+        <PARAMETER NAME="C2_MMCM_VCO" VALUE="1200.0"/>
+        <PARAMETER NAME="C2_MMCM_CLKOUT0_FREQ" VALUE="10.0"/>
+        <PARAMETER NAME="C2_MMCM_CLKOUT1_FREQ" VALUE="10"/>
+        <PARAMETER NAME="C2_MMCM_CLKOUT2_FREQ" VALUE="10"/>
+        <PARAMETER NAME="C2_MMCM_CLKOUT3_FREQ" VALUE="10"/>
+        <PARAMETER NAME="C2_MMCM_CLKOUT4_FREQ" VALUE="10"/>
+        <PARAMETER NAME="C2_MMCM_CLKOUT0_EN" VALUE="FALSE"/>
+        <PARAMETER NAME="C2_MMCM_CLKOUT2_EN" VALUE="FALSE"/>
+        <PARAMETER NAME="C2_MMCM_CLKOUT1_EN" VALUE="FALSE"/>
+        <PARAMETER NAME="C2_MMCM_CLKOUT3_EN" VALUE="FALSE"/>
+        <PARAMETER NAME="C2_MMCM_CLKOUT4_EN" VALUE="FALSE"/>
+        <PARAMETER NAME="C2_C_S_AXI_CTRL_ID_WIDTH" VALUE="4"/>
+        <PARAMETER NAME="C2_C_S_AXI_CTRL_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C2_C_S_AXI_CTRL_ADDR_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C2_C_S_AXI_CTRL_MEM_SIZE" VALUE="1048576"/>
+        <PARAMETER NAME="C2_C_S_AXI_ID_WIDTH" VALUE="4"/>
+        <PARAMETER NAME="C2_C_S_AXI_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C2_C_S_AXI_ADDR_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C2_C_S_AXI_MEM_SIZE" VALUE="1048576"/>
+        <PARAMETER NAME="C2_QDRIIP_NUM_DEVICES" VALUE="1"/>
+        <PARAMETER NAME="C2_QDRIIP_DATA_WIDTH" VALUE="18"/>
+        <PARAMETER NAME="C2_QDRIIP_ADDR_WIDTH" VALUE="29"/>
+        <PARAMETER NAME="C2_QDRIIP_BW_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="C2_QDRIIP_DEBUG_PORT" VALUE="OFF"/>
+        <PARAMETER NAME="C2_QDRIIP_BURST_LEN" VALUE="1"/>
+        <PARAMETER NAME="C2_RLDII_NUM_DEVICES" VALUE="1"/>
+        <PARAMETER NAME="C2_RLDII_DATA_WIDTH" VALUE="18"/>
+        <PARAMETER NAME="C2_RLDII_RLD_ADDR_WIDTH" VALUE="29"/>
+        <PARAMETER NAME="C2_RLDII_QK_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="C2_RLDII_CK_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C2_RLDII_DK_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C2_RLDII_DM_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C2_RLDII_BANK_WIDTH" VALUE="2"/>
+        <PARAMETER NAME="C2_RLDII_QVLD_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C2_RLDII_DEBUG_PORT" VALUE="OFF"/>
+        <PARAMETER NAME="C2_RLDIII_NUM_DEVICES" VALUE="1"/>
+        <PARAMETER NAME="C2_RLDIII_DATA_WIDTH" VALUE="18"/>
+        <PARAMETER NAME="C2_RLDIII_RLD_ADDR_WIDTH" VALUE="29"/>
+        <PARAMETER NAME="C2_RLDIII_QK_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="C2_RLDIII_CK_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C2_RLDIII_DK_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C2_RLDIII_DM_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C2_RLDIII_BANK_WIDTH" VALUE="2"/>
+        <PARAMETER NAME="C2_RLDIII_QVLD_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C2_RLDIII_DEBUG_PORT" VALUE="OFF"/>
+        <PARAMETER NAME="C2_RLDX_CMD_PER_CLK" VALUE="1"/>
+        <PARAMETER NAME="C2_RLDX_DATA_WIDTH" VALUE="18"/>
+        <PARAMETER NAME="C2_RLDX_ADDR_WIDTH" VALUE="29"/>
+        <PARAMETER NAME="C2_RLDX_BANK_WIDTH" VALUE="2"/>
+        <PARAMETER NAME="C2_RLDX_nCK_PER_CLK" VALUE="1"/>
+        <PARAMETER NAME="C2_RLDX_DM_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C2_RLDII_CMD_PER_CLK" VALUE="1"/>
+        <PARAMETER NAME="C2_RLDII_ADDR_WIDTH" VALUE="29"/>
+        <PARAMETER NAME="C2_RLDII_nCK_PER_CLK" VALUE="1"/>
+        <PARAMETER NAME="C2_RLDIII_CMD_PER_CLK" VALUE="1"/>
+        <PARAMETER NAME="C2_RLDIII_ADDR_WIDTH" VALUE="29"/>
+        <PARAMETER NAME="C2_RLDIII_nCK_PER_CLK" VALUE="1"/>
+        <PARAMETER NAME="C2_POLARITY" VALUE="ACTIVE_LOW"/>
+        <PARAMETER NAME="C3_MEM_TYPE" VALUE="DDR3"/>
+        <PARAMETER NAME="C3_IS_CLK_SHARED" VALUE="FALSE"/>
+        <PARAMETER NAME="C3_SYSCLK_TYPE" VALUE="DIFF"/>
+        <PARAMETER NAME="C3_USE_AXI" VALUE="0"/>
+        <PARAMETER NAME="C3_ECC" VALUE="OFF"/>
+        <PARAMETER NAME="C3_DDR3_DQ_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="C3_DDR3_DQS_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C3_DDR3_ROW_WIDTH" VALUE="14"/>
+        <PARAMETER NAME="C3_DDR3_BANK_WIDTH" VALUE="3"/>
+        <PARAMETER NAME="C3_DDR3_CK_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C3_DDR3_CKE_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C3_DDR3_CS_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C3_DDR3_nCS_PER_RANK" VALUE="1"/>
+        <PARAMETER NAME="C3_DDR3_DM_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C3_DDR3_ODT_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C3_DDR3_USE_CS_PORT" VALUE="1"/>
+        <PARAMETER NAME="C3_DDR3_USE_DM_PORT" VALUE="1"/>
+        <PARAMETER NAME="C3_DDR3_USE_ODT_PORT" VALUE="1"/>
+        <PARAMETER NAME="C3_DDR3_REG_CTRL" VALUE="OFF"/>
+        <PARAMETER NAME="C3_DDR3_DQS_CNT_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C3_DDR3_DEBUG_PORT" VALUE="OFF"/>
+        <PARAMETER NAME="C3_DDR2_DQ_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="C3_DDR2_DQS_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C3_DDR2_ROW_WIDTH" VALUE="14"/>
+        <PARAMETER NAME="C3_DDR2_BANK_WIDTH" VALUE="3"/>
+        <PARAMETER NAME="C3_DDR2_CK_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C3_DDR2_CKE_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C3_DDR2_CS_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C3_DDR2_nCS_PER_RANK" VALUE="1"/>
+        <PARAMETER NAME="C3_DDR2_DM_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C3_DDR2_ODT_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C3_DDR2_USE_CS_PORT" VALUE="1"/>
+        <PARAMETER NAME="C3_DDR2_USE_DM_PORT" VALUE="1"/>
+        <PARAMETER NAME="C3_DDR2_USE_ODT_PORT" VALUE="1"/>
+        <PARAMETER NAME="C3_DDR2_REG_CTRL" VALUE="OFF"/>
+        <PARAMETER NAME="C3_DDR2_DQS_CNT_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C3_DDR2_DEBUG_PORT" VALUE="OFF"/>
+        <PARAMETER NAME="C3_LPDDR2_DQ_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="C3_LPDDR2_DQS_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C3_LPDDR2_ROW_WIDTH" VALUE="14"/>
+        <PARAMETER NAME="C3_LPDDR2_BANK_WIDTH" VALUE="3"/>
+        <PARAMETER NAME="C3_LPDDR2_CK_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C3_LPDDR2_CKE_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C3_LPDDR2_CS_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C3_LPDDR2_nCS_PER_RANK" VALUE="1"/>
+        <PARAMETER NAME="C3_LPDDR2_DM_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C3_LPDDR2_USE_CS_PORT" VALUE="1"/>
+        <PARAMETER NAME="C3_LPDDR2_USE_DM_PORT" VALUE="1"/>
+        <PARAMETER NAME="C3_LPDDR2_USE_ODT_PORT" VALUE="1"/>
+        <PARAMETER NAME="C3_LPDDR2_REG_CTRL" VALUE="OFF"/>
+        <PARAMETER NAME="C3_LPDDR2_DQS_CNT_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C3_LPDDR2_DEBUG_PORT" VALUE="OFF"/>
+        <PARAMETER NAME="C3_DQS_CNT_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C3_DEBUG_PORT" VALUE="OFF"/>
+        <PARAMETER NAME="C3_DDRX_ADDR_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="C3_DDRX_nCK_PER_CLK" VALUE="2"/>
+        <PARAMETER NAME="C3_DDRX_DATA_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="C3_DDR3_ADDR_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="C3_DDR3_nCK_PER_CLK" VALUE="2"/>
+        <PARAMETER NAME="C3_DDR3_DATA_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="C3_DDR2_ADDR_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="C3_DDR2_nCK_PER_CLK" VALUE="2"/>
+        <PARAMETER NAME="C3_DDR2_DATA_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="C3_LPDDR2_ADDR_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="C3_LPDDR2_nCK_PER_CLK" VALUE="2"/>
+        <PARAMETER NAME="C3_LPDDR2_DATA_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="C3_FREQ_HZ" VALUE="100.0"/>
+        <PARAMETER NAME="C3_PHASE" VALUE="0.000"/>
+        <PARAMETER NAME="C3_UI_EXTRA_CLOCKS" VALUE="FALSE"/>
+        <PARAMETER NAME="C3_MMCM_VCO" VALUE="1200.0"/>
+        <PARAMETER NAME="C3_MMCM_CLKOUT0_FREQ" VALUE="10.0"/>
+        <PARAMETER NAME="C3_MMCM_CLKOUT1_FREQ" VALUE="10"/>
+        <PARAMETER NAME="C3_MMCM_CLKOUT2_FREQ" VALUE="10"/>
+        <PARAMETER NAME="C3_MMCM_CLKOUT3_FREQ" VALUE="10"/>
+        <PARAMETER NAME="C3_MMCM_CLKOUT4_FREQ" VALUE="10"/>
+        <PARAMETER NAME="C3_MMCM_CLKOUT0_EN" VALUE="FALSE"/>
+        <PARAMETER NAME="C3_MMCM_CLKOUT2_EN" VALUE="FALSE"/>
+        <PARAMETER NAME="C3_MMCM_CLKOUT1_EN" VALUE="FALSE"/>
+        <PARAMETER NAME="C3_MMCM_CLKOUT3_EN" VALUE="FALSE"/>
+        <PARAMETER NAME="C3_MMCM_CLKOUT4_EN" VALUE="FALSE"/>
+        <PARAMETER NAME="C3_C_S_AXI_CTRL_ID_WIDTH" VALUE="4"/>
+        <PARAMETER NAME="C3_C_S_AXI_CTRL_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C3_C_S_AXI_CTRL_ADDR_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C3_C_S_AXI_CTRL_MEM_SIZE" VALUE="1048576"/>
+        <PARAMETER NAME="C3_C_S_AXI_ID_WIDTH" VALUE="4"/>
+        <PARAMETER NAME="C3_C_S_AXI_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C3_C_S_AXI_ADDR_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C3_C_S_AXI_MEM_SIZE" VALUE="1048576"/>
+        <PARAMETER NAME="C3_QDRIIP_NUM_DEVICES" VALUE="1"/>
+        <PARAMETER NAME="C3_QDRIIP_DATA_WIDTH" VALUE="18"/>
+        <PARAMETER NAME="C3_QDRIIP_ADDR_WIDTH" VALUE="29"/>
+        <PARAMETER NAME="C3_QDRIIP_BW_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="C3_QDRIIP_DEBUG_PORT" VALUE="OFF"/>
+        <PARAMETER NAME="C3_QDRIIP_BURST_LEN" VALUE="1"/>
+        <PARAMETER NAME="C3_RLDII_NUM_DEVICES" VALUE="1"/>
+        <PARAMETER NAME="C3_RLDII_DATA_WIDTH" VALUE="18"/>
+        <PARAMETER NAME="C3_RLDII_RLD_ADDR_WIDTH" VALUE="29"/>
+        <PARAMETER NAME="C3_RLDII_QK_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="C3_RLDII_CK_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C3_RLDII_DK_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C3_RLDII_DM_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C3_RLDII_BANK_WIDTH" VALUE="2"/>
+        <PARAMETER NAME="C3_RLDII_QVLD_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C3_RLDII_DEBUG_PORT" VALUE="OFF"/>
+        <PARAMETER NAME="C3_RLDIII_NUM_DEVICES" VALUE="1"/>
+        <PARAMETER NAME="C3_RLDIII_DATA_WIDTH" VALUE="18"/>
+        <PARAMETER NAME="C3_RLDIII_RLD_ADDR_WIDTH" VALUE="29"/>
+        <PARAMETER NAME="C3_RLDIII_QK_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="C3_RLDIII_CK_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C3_RLDIII_DK_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C3_RLDIII_DM_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C3_RLDIII_BANK_WIDTH" VALUE="2"/>
+        <PARAMETER NAME="C3_RLDIII_QVLD_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C3_RLDIII_DEBUG_PORT" VALUE="OFF"/>
+        <PARAMETER NAME="C3_RLDX_CMD_PER_CLK" VALUE="1"/>
+        <PARAMETER NAME="C3_RLDX_DATA_WIDTH" VALUE="18"/>
+        <PARAMETER NAME="C3_RLDX_ADDR_WIDTH" VALUE="29"/>
+        <PARAMETER NAME="C3_RLDX_BANK_WIDTH" VALUE="2"/>
+        <PARAMETER NAME="C3_RLDX_nCK_PER_CLK" VALUE="1"/>
+        <PARAMETER NAME="C3_RLDX_DM_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C3_RLDII_CMD_PER_CLK" VALUE="1"/>
+        <PARAMETER NAME="C3_RLDII_ADDR_WIDTH" VALUE="29"/>
+        <PARAMETER NAME="C3_RLDII_nCK_PER_CLK" VALUE="1"/>
+        <PARAMETER NAME="C3_RLDIII_CMD_PER_CLK" VALUE="1"/>
+        <PARAMETER NAME="C3_RLDIII_ADDR_WIDTH" VALUE="29"/>
+        <PARAMETER NAME="C3_RLDIII_nCK_PER_CLK" VALUE="1"/>
+        <PARAMETER NAME="C3_POLARITY" VALUE="ACTIVE_LOW"/>
+        <PARAMETER NAME="C4_MEM_TYPE" VALUE="DDR3"/>
+        <PARAMETER NAME="C4_IS_CLK_SHARED" VALUE="FALSE"/>
+        <PARAMETER NAME="C4_SYSCLK_TYPE" VALUE="DIFF"/>
+        <PARAMETER NAME="C4_USE_AXI" VALUE="0"/>
+        <PARAMETER NAME="C4_ECC" VALUE="OFF"/>
+        <PARAMETER NAME="C4_DDR3_DQ_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="C4_DDR3_DQS_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C4_DDR3_ROW_WIDTH" VALUE="14"/>
+        <PARAMETER NAME="C4_DDR3_BANK_WIDTH" VALUE="3"/>
+        <PARAMETER NAME="C4_DDR3_CK_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C4_DDR3_CKE_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C4_DDR3_CS_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C4_DDR3_nCS_PER_RANK" VALUE="1"/>
+        <PARAMETER NAME="C4_DDR3_DM_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C4_DDR3_ODT_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C4_DDR3_USE_CS_PORT" VALUE="1"/>
+        <PARAMETER NAME="C4_DDR3_USE_DM_PORT" VALUE="1"/>
+        <PARAMETER NAME="C4_DDR3_USE_ODT_PORT" VALUE="1"/>
+        <PARAMETER NAME="C4_DDR3_REG_CTRL" VALUE="OFF"/>
+        <PARAMETER NAME="C4_DDR3_DQS_CNT_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C4_DDR3_DEBUG_PORT" VALUE="OFF"/>
+        <PARAMETER NAME="C4_DDR2_DQ_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="C4_DDR2_DQS_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C4_DDR2_ROW_WIDTH" VALUE="14"/>
+        <PARAMETER NAME="C4_DDR2_BANK_WIDTH" VALUE="3"/>
+        <PARAMETER NAME="C4_DDR2_CK_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C4_DDR2_CKE_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C4_DDR2_CS_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C4_DDR2_nCS_PER_RANK" VALUE="1"/>
+        <PARAMETER NAME="C4_DDR2_DM_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C4_DDR2_ODT_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C4_DDR2_USE_CS_PORT" VALUE="1"/>
+        <PARAMETER NAME="C4_DDR2_USE_DM_PORT" VALUE="1"/>
+        <PARAMETER NAME="C4_DDR2_USE_ODT_PORT" VALUE="1"/>
+        <PARAMETER NAME="C4_DDR2_REG_CTRL" VALUE="OFF"/>
+        <PARAMETER NAME="C4_DDR2_DQS_CNT_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C4_DDR2_DEBUG_PORT" VALUE="OFF"/>
+        <PARAMETER NAME="C4_LPDDR2_DQ_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="C4_LPDDR2_DQS_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C4_LPDDR2_ROW_WIDTH" VALUE="14"/>
+        <PARAMETER NAME="C4_LPDDR2_BANK_WIDTH" VALUE="3"/>
+        <PARAMETER NAME="C4_LPDDR2_CK_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C4_LPDDR2_CKE_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C4_LPDDR2_CS_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C4_LPDDR2_nCS_PER_RANK" VALUE="1"/>
+        <PARAMETER NAME="C4_LPDDR2_DM_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C4_LPDDR2_USE_CS_PORT" VALUE="1"/>
+        <PARAMETER NAME="C4_LPDDR2_USE_DM_PORT" VALUE="1"/>
+        <PARAMETER NAME="C4_LPDDR2_USE_ODT_PORT" VALUE="1"/>
+        <PARAMETER NAME="C4_LPDDR2_REG_CTRL" VALUE="OFF"/>
+        <PARAMETER NAME="C4_LPDDR2_DQS_CNT_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C4_LPDDR2_DEBUG_PORT" VALUE="OFF"/>
+        <PARAMETER NAME="C4_DQS_CNT_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C4_DEBUG_PORT" VALUE="OFF"/>
+        <PARAMETER NAME="C4_DDRX_ADDR_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="C4_DDRX_nCK_PER_CLK" VALUE="2"/>
+        <PARAMETER NAME="C4_DDRX_DATA_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="C4_DDR3_ADDR_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="C4_DDR3_nCK_PER_CLK" VALUE="2"/>
+        <PARAMETER NAME="C4_DDR3_DATA_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="C4_DDR2_ADDR_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="C4_DDR2_nCK_PER_CLK" VALUE="2"/>
+        <PARAMETER NAME="C4_DDR2_DATA_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="C4_LPDDR2_ADDR_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="C4_LPDDR2_nCK_PER_CLK" VALUE="2"/>
+        <PARAMETER NAME="C4_LPDDR2_DATA_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="C4_FREQ_HZ" VALUE="100.0"/>
+        <PARAMETER NAME="C4_PHASE" VALUE="0.000"/>
+        <PARAMETER NAME="C4_UI_EXTRA_CLOCKS" VALUE="FALSE"/>
+        <PARAMETER NAME="C4_MMCM_VCO" VALUE="1200.0"/>
+        <PARAMETER NAME="C4_MMCM_CLKOUT0_FREQ" VALUE="10.0"/>
+        <PARAMETER NAME="C4_MMCM_CLKOUT1_FREQ" VALUE="10"/>
+        <PARAMETER NAME="C4_MMCM_CLKOUT2_FREQ" VALUE="10"/>
+        <PARAMETER NAME="C4_MMCM_CLKOUT3_FREQ" VALUE="10"/>
+        <PARAMETER NAME="C4_MMCM_CLKOUT4_FREQ" VALUE="10"/>
+        <PARAMETER NAME="C4_MMCM_CLKOUT0_EN" VALUE="FALSE"/>
+        <PARAMETER NAME="C4_MMCM_CLKOUT2_EN" VALUE="FALSE"/>
+        <PARAMETER NAME="C4_MMCM_CLKOUT1_EN" VALUE="FALSE"/>
+        <PARAMETER NAME="C4_MMCM_CLKOUT3_EN" VALUE="FALSE"/>
+        <PARAMETER NAME="C4_MMCM_CLKOUT4_EN" VALUE="FALSE"/>
+        <PARAMETER NAME="C4_C_S_AXI_CTRL_ID_WIDTH" VALUE="4"/>
+        <PARAMETER NAME="C4_C_S_AXI_CTRL_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C4_C_S_AXI_CTRL_ADDR_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C4_C_S_AXI_CTRL_MEM_SIZE" VALUE="1048576"/>
+        <PARAMETER NAME="C4_C_S_AXI_ID_WIDTH" VALUE="4"/>
+        <PARAMETER NAME="C4_C_S_AXI_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C4_C_S_AXI_ADDR_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C4_C_S_AXI_MEM_SIZE" VALUE="1048576"/>
+        <PARAMETER NAME="C4_QDRIIP_NUM_DEVICES" VALUE="1"/>
+        <PARAMETER NAME="C4_QDRIIP_DATA_WIDTH" VALUE="18"/>
+        <PARAMETER NAME="C4_QDRIIP_ADDR_WIDTH" VALUE="29"/>
+        <PARAMETER NAME="C4_QDRIIP_BW_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="C4_QDRIIP_DEBUG_PORT" VALUE="OFF"/>
+        <PARAMETER NAME="C4_QDRIIP_BURST_LEN" VALUE="1"/>
+        <PARAMETER NAME="C4_RLDII_NUM_DEVICES" VALUE="1"/>
+        <PARAMETER NAME="C4_RLDII_DATA_WIDTH" VALUE="18"/>
+        <PARAMETER NAME="C4_RLDII_RLD_ADDR_WIDTH" VALUE="29"/>
+        <PARAMETER NAME="C4_RLDII_QK_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="C4_RLDII_CK_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C4_RLDII_DK_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C4_RLDII_DM_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C4_RLDII_BANK_WIDTH" VALUE="2"/>
+        <PARAMETER NAME="C4_RLDII_QVLD_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C4_RLDII_DEBUG_PORT" VALUE="OFF"/>
+        <PARAMETER NAME="C4_RLDIII_NUM_DEVICES" VALUE="1"/>
+        <PARAMETER NAME="C4_RLDIII_DATA_WIDTH" VALUE="18"/>
+        <PARAMETER NAME="C4_RLDIII_RLD_ADDR_WIDTH" VALUE="29"/>
+        <PARAMETER NAME="C4_RLDIII_QK_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="C4_RLDIII_CK_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C4_RLDIII_DK_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C4_RLDIII_DM_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C4_RLDIII_BANK_WIDTH" VALUE="2"/>
+        <PARAMETER NAME="C4_RLDIII_QVLD_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C4_RLDIII_DEBUG_PORT" VALUE="OFF"/>
+        <PARAMETER NAME="C4_RLDX_CMD_PER_CLK" VALUE="1"/>
+        <PARAMETER NAME="C4_RLDX_DATA_WIDTH" VALUE="18"/>
+        <PARAMETER NAME="C4_RLDX_ADDR_WIDTH" VALUE="29"/>
+        <PARAMETER NAME="C4_RLDX_BANK_WIDTH" VALUE="2"/>
+        <PARAMETER NAME="C4_RLDX_nCK_PER_CLK" VALUE="1"/>
+        <PARAMETER NAME="C4_RLDX_DM_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C4_RLDII_CMD_PER_CLK" VALUE="1"/>
+        <PARAMETER NAME="C4_RLDII_ADDR_WIDTH" VALUE="29"/>
+        <PARAMETER NAME="C4_RLDII_nCK_PER_CLK" VALUE="1"/>
+        <PARAMETER NAME="C4_RLDIII_CMD_PER_CLK" VALUE="1"/>
+        <PARAMETER NAME="C4_RLDIII_ADDR_WIDTH" VALUE="29"/>
+        <PARAMETER NAME="C4_RLDIII_nCK_PER_CLK" VALUE="1"/>
+        <PARAMETER NAME="C4_POLARITY" VALUE="ACTIVE_LOW"/>
+        <PARAMETER NAME="C5_MEM_TYPE" VALUE="DDR3"/>
+        <PARAMETER NAME="C5_IS_CLK_SHARED" VALUE="FALSE"/>
+        <PARAMETER NAME="C5_SYSCLK_TYPE" VALUE="DIFF"/>
+        <PARAMETER NAME="C5_USE_AXI" VALUE="0"/>
+        <PARAMETER NAME="C5_ECC" VALUE="OFF"/>
+        <PARAMETER NAME="C5_DDR3_DQ_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="C5_DDR3_DQS_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C5_DDR3_ROW_WIDTH" VALUE="14"/>
+        <PARAMETER NAME="C5_DDR3_BANK_WIDTH" VALUE="3"/>
+        <PARAMETER NAME="C5_DDR3_CK_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C5_DDR3_CKE_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C5_DDR3_CS_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C5_DDR3_nCS_PER_RANK" VALUE="1"/>
+        <PARAMETER NAME="C5_DDR3_DM_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C5_DDR3_ODT_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C5_DDR3_USE_CS_PORT" VALUE="1"/>
+        <PARAMETER NAME="C5_DDR3_USE_DM_PORT" VALUE="1"/>
+        <PARAMETER NAME="C5_DDR3_USE_ODT_PORT" VALUE="1"/>
+        <PARAMETER NAME="C5_DDR3_REG_CTRL" VALUE="OFF"/>
+        <PARAMETER NAME="C5_DDR3_DQS_CNT_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C5_DDR3_DEBUG_PORT" VALUE="OFF"/>
+        <PARAMETER NAME="C5_DDR2_DQ_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="C5_DDR2_DQS_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C5_DDR2_ROW_WIDTH" VALUE="14"/>
+        <PARAMETER NAME="C5_DDR2_BANK_WIDTH" VALUE="3"/>
+        <PARAMETER NAME="C5_DDR2_CK_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C5_DDR2_CKE_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C5_DDR2_CS_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C5_DDR2_nCS_PER_RANK" VALUE="1"/>
+        <PARAMETER NAME="C5_DDR2_DM_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C5_DDR2_ODT_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C5_DDR2_USE_CS_PORT" VALUE="1"/>
+        <PARAMETER NAME="C5_DDR2_USE_DM_PORT" VALUE="1"/>
+        <PARAMETER NAME="C5_DDR2_USE_ODT_PORT" VALUE="1"/>
+        <PARAMETER NAME="C5_DDR2_REG_CTRL" VALUE="OFF"/>
+        <PARAMETER NAME="C5_DDR2_DQS_CNT_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C5_DDR2_DEBUG_PORT" VALUE="OFF"/>
+        <PARAMETER NAME="C5_LPDDR2_DQ_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="C5_LPDDR2_DQS_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C5_LPDDR2_ROW_WIDTH" VALUE="14"/>
+        <PARAMETER NAME="C5_LPDDR2_BANK_WIDTH" VALUE="3"/>
+        <PARAMETER NAME="C5_LPDDR2_CK_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C5_LPDDR2_CKE_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C5_LPDDR2_CS_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C5_LPDDR2_nCS_PER_RANK" VALUE="1"/>
+        <PARAMETER NAME="C5_LPDDR2_DM_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C5_LPDDR2_USE_CS_PORT" VALUE="1"/>
+        <PARAMETER NAME="C5_LPDDR2_USE_DM_PORT" VALUE="1"/>
+        <PARAMETER NAME="C5_LPDDR2_USE_ODT_PORT" VALUE="1"/>
+        <PARAMETER NAME="C5_LPDDR2_REG_CTRL" VALUE="OFF"/>
+        <PARAMETER NAME="C5_LPDDR2_DQS_CNT_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C5_LPDDR2_DEBUG_PORT" VALUE="OFF"/>
+        <PARAMETER NAME="C5_DQS_CNT_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C5_DEBUG_PORT" VALUE="OFF"/>
+        <PARAMETER NAME="C5_DDRX_ADDR_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="C5_DDRX_nCK_PER_CLK" VALUE="2"/>
+        <PARAMETER NAME="C5_DDRX_DATA_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="C5_DDR3_ADDR_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="C5_DDR3_nCK_PER_CLK" VALUE="2"/>
+        <PARAMETER NAME="C5_DDR3_DATA_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="C5_DDR2_ADDR_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="C5_DDR2_nCK_PER_CLK" VALUE="2"/>
+        <PARAMETER NAME="C5_DDR2_DATA_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="C5_LPDDR2_ADDR_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="C5_LPDDR2_nCK_PER_CLK" VALUE="2"/>
+        <PARAMETER NAME="C5_LPDDR2_DATA_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="C5_FREQ_HZ" VALUE="100.0"/>
+        <PARAMETER NAME="C5_PHASE" VALUE="0.000"/>
+        <PARAMETER NAME="C5_UI_EXTRA_CLOCKS" VALUE="FALSE"/>
+        <PARAMETER NAME="C5_MMCM_VCO" VALUE="1200.0"/>
+        <PARAMETER NAME="C5_MMCM_CLKOUT0_FREQ" VALUE="10.0"/>
+        <PARAMETER NAME="C5_MMCM_CLKOUT1_FREQ" VALUE="10"/>
+        <PARAMETER NAME="C5_MMCM_CLKOUT2_FREQ" VALUE="10"/>
+        <PARAMETER NAME="C5_MMCM_CLKOUT3_FREQ" VALUE="10"/>
+        <PARAMETER NAME="C5_MMCM_CLKOUT4_FREQ" VALUE="10"/>
+        <PARAMETER NAME="C5_MMCM_CLKOUT0_EN" VALUE="FALSE"/>
+        <PARAMETER NAME="C5_MMCM_CLKOUT2_EN" VALUE="FALSE"/>
+        <PARAMETER NAME="C5_MMCM_CLKOUT1_EN" VALUE="FALSE"/>
+        <PARAMETER NAME="C5_MMCM_CLKOUT3_EN" VALUE="FALSE"/>
+        <PARAMETER NAME="C5_MMCM_CLKOUT4_EN" VALUE="FALSE"/>
+        <PARAMETER NAME="C5_C_S_AXI_CTRL_ID_WIDTH" VALUE="4"/>
+        <PARAMETER NAME="C5_C_S_AXI_CTRL_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C5_C_S_AXI_CTRL_ADDR_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C5_C_S_AXI_CTRL_MEM_SIZE" VALUE="1048576"/>
+        <PARAMETER NAME="C5_C_S_AXI_ID_WIDTH" VALUE="4"/>
+        <PARAMETER NAME="C5_C_S_AXI_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C5_C_S_AXI_ADDR_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C5_C_S_AXI_MEM_SIZE" VALUE="1048576"/>
+        <PARAMETER NAME="C5_QDRIIP_NUM_DEVICES" VALUE="1"/>
+        <PARAMETER NAME="C5_QDRIIP_DATA_WIDTH" VALUE="18"/>
+        <PARAMETER NAME="C5_QDRIIP_ADDR_WIDTH" VALUE="29"/>
+        <PARAMETER NAME="C5_QDRIIP_BW_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="C5_QDRIIP_DEBUG_PORT" VALUE="OFF"/>
+        <PARAMETER NAME="C5_QDRIIP_BURST_LEN" VALUE="1"/>
+        <PARAMETER NAME="C5_RLDII_NUM_DEVICES" VALUE="1"/>
+        <PARAMETER NAME="C5_RLDII_DATA_WIDTH" VALUE="18"/>
+        <PARAMETER NAME="C5_RLDII_RLD_ADDR_WIDTH" VALUE="29"/>
+        <PARAMETER NAME="C5_RLDII_QK_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="C5_RLDII_CK_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C5_RLDII_DK_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C5_RLDII_DM_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C5_RLDII_BANK_WIDTH" VALUE="2"/>
+        <PARAMETER NAME="C5_RLDII_QVLD_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C5_RLDII_DEBUG_PORT" VALUE="OFF"/>
+        <PARAMETER NAME="C5_RLDIII_NUM_DEVICES" VALUE="1"/>
+        <PARAMETER NAME="C5_RLDIII_DATA_WIDTH" VALUE="18"/>
+        <PARAMETER NAME="C5_RLDIII_RLD_ADDR_WIDTH" VALUE="29"/>
+        <PARAMETER NAME="C5_RLDIII_QK_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="C5_RLDIII_CK_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C5_RLDIII_DK_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C5_RLDIII_DM_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C5_RLDIII_BANK_WIDTH" VALUE="2"/>
+        <PARAMETER NAME="C5_RLDIII_QVLD_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C5_RLDIII_DEBUG_PORT" VALUE="OFF"/>
+        <PARAMETER NAME="C5_RLDX_CMD_PER_CLK" VALUE="1"/>
+        <PARAMETER NAME="C5_RLDX_DATA_WIDTH" VALUE="18"/>
+        <PARAMETER NAME="C5_RLDX_ADDR_WIDTH" VALUE="29"/>
+        <PARAMETER NAME="C5_RLDX_BANK_WIDTH" VALUE="2"/>
+        <PARAMETER NAME="C5_RLDX_nCK_PER_CLK" VALUE="1"/>
+        <PARAMETER NAME="C5_RLDX_DM_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C5_RLDII_CMD_PER_CLK" VALUE="1"/>
+        <PARAMETER NAME="C5_RLDII_ADDR_WIDTH" VALUE="29"/>
+        <PARAMETER NAME="C5_RLDII_nCK_PER_CLK" VALUE="1"/>
+        <PARAMETER NAME="C5_RLDIII_CMD_PER_CLK" VALUE="1"/>
+        <PARAMETER NAME="C5_RLDIII_ADDR_WIDTH" VALUE="29"/>
+        <PARAMETER NAME="C5_RLDIII_nCK_PER_CLK" VALUE="1"/>
+        <PARAMETER NAME="C5_POLARITY" VALUE="ACTIVE_LOW"/>
+        <PARAMETER NAME="C6_MEM_TYPE" VALUE="DDR3"/>
+        <PARAMETER NAME="C6_IS_CLK_SHARED" VALUE="FALSE"/>
+        <PARAMETER NAME="C6_SYSCLK_TYPE" VALUE="DIFF"/>
+        <PARAMETER NAME="C6_USE_AXI" VALUE="0"/>
+        <PARAMETER NAME="C6_ECC" VALUE="OFF"/>
+        <PARAMETER NAME="C6_DDR3_DQ_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="C6_DDR3_DQS_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C6_DDR3_ROW_WIDTH" VALUE="14"/>
+        <PARAMETER NAME="C6_DDR3_BANK_WIDTH" VALUE="3"/>
+        <PARAMETER NAME="C6_DDR3_CK_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C6_DDR3_CKE_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C6_DDR3_CS_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C6_DDR3_nCS_PER_RANK" VALUE="1"/>
+        <PARAMETER NAME="C6_DDR3_DM_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C6_DDR3_ODT_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C6_DDR3_USE_CS_PORT" VALUE="1"/>
+        <PARAMETER NAME="C6_DDR3_USE_DM_PORT" VALUE="1"/>
+        <PARAMETER NAME="C6_DDR3_USE_ODT_PORT" VALUE="1"/>
+        <PARAMETER NAME="C6_DDR3_REG_CTRL" VALUE="OFF"/>
+        <PARAMETER NAME="C6_DDR3_DQS_CNT_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C6_DDR3_DEBUG_PORT" VALUE="OFF"/>
+        <PARAMETER NAME="C6_DDR2_DQ_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="C6_DDR2_DQS_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C6_DDR2_ROW_WIDTH" VALUE="14"/>
+        <PARAMETER NAME="C6_DDR2_BANK_WIDTH" VALUE="3"/>
+        <PARAMETER NAME="C6_DDR2_CK_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C6_DDR2_CKE_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C6_DDR2_CS_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C6_DDR2_nCS_PER_RANK" VALUE="1"/>
+        <PARAMETER NAME="C6_DDR2_DM_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C6_DDR2_ODT_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C6_DDR2_USE_CS_PORT" VALUE="1"/>
+        <PARAMETER NAME="C6_DDR2_USE_DM_PORT" VALUE="1"/>
+        <PARAMETER NAME="C6_DDR2_USE_ODT_PORT" VALUE="1"/>
+        <PARAMETER NAME="C6_DDR2_REG_CTRL" VALUE="OFF"/>
+        <PARAMETER NAME="C6_DDR2_DQS_CNT_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C6_DDR2_DEBUG_PORT" VALUE="OFF"/>
+        <PARAMETER NAME="C6_LPDDR2_DQ_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="C6_LPDDR2_DQS_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C6_LPDDR2_ROW_WIDTH" VALUE="14"/>
+        <PARAMETER NAME="C6_LPDDR2_BANK_WIDTH" VALUE="3"/>
+        <PARAMETER NAME="C6_LPDDR2_CK_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C6_LPDDR2_CKE_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C6_LPDDR2_CS_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C6_LPDDR2_nCS_PER_RANK" VALUE="1"/>
+        <PARAMETER NAME="C6_LPDDR2_DM_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C6_LPDDR2_USE_CS_PORT" VALUE="1"/>
+        <PARAMETER NAME="C6_LPDDR2_USE_DM_PORT" VALUE="1"/>
+        <PARAMETER NAME="C6_LPDDR2_USE_ODT_PORT" VALUE="1"/>
+        <PARAMETER NAME="C6_LPDDR2_REG_CTRL" VALUE="OFF"/>
+        <PARAMETER NAME="C6_LPDDR2_DQS_CNT_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C6_LPDDR2_DEBUG_PORT" VALUE="OFF"/>
+        <PARAMETER NAME="C6_DQS_CNT_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C6_DEBUG_PORT" VALUE="OFF"/>
+        <PARAMETER NAME="C6_DDRX_ADDR_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="C6_DDRX_nCK_PER_CLK" VALUE="2"/>
+        <PARAMETER NAME="C6_DDRX_DATA_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="C6_DDR3_ADDR_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="C6_DDR3_nCK_PER_CLK" VALUE="2"/>
+        <PARAMETER NAME="C6_DDR3_DATA_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="C6_DDR2_ADDR_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="C6_DDR2_nCK_PER_CLK" VALUE="2"/>
+        <PARAMETER NAME="C6_DDR2_DATA_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="C6_LPDDR2_ADDR_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="C6_LPDDR2_nCK_PER_CLK" VALUE="2"/>
+        <PARAMETER NAME="C6_LPDDR2_DATA_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="C6_FREQ_HZ" VALUE="100.0"/>
+        <PARAMETER NAME="C6_PHASE" VALUE="0.000"/>
+        <PARAMETER NAME="C6_UI_EXTRA_CLOCKS" VALUE="FALSE"/>
+        <PARAMETER NAME="C6_MMCM_VCO" VALUE="1200.0"/>
+        <PARAMETER NAME="C6_MMCM_CLKOUT0_FREQ" VALUE="10.0"/>
+        <PARAMETER NAME="C6_MMCM_CLKOUT1_FREQ" VALUE="10"/>
+        <PARAMETER NAME="C6_MMCM_CLKOUT2_FREQ" VALUE="10"/>
+        <PARAMETER NAME="C6_MMCM_CLKOUT3_FREQ" VALUE="10"/>
+        <PARAMETER NAME="C6_MMCM_CLKOUT4_FREQ" VALUE="10"/>
+        <PARAMETER NAME="C6_MMCM_CLKOUT0_EN" VALUE="FALSE"/>
+        <PARAMETER NAME="C6_MMCM_CLKOUT2_EN" VALUE="FALSE"/>
+        <PARAMETER NAME="C6_MMCM_CLKOUT1_EN" VALUE="FALSE"/>
+        <PARAMETER NAME="C6_MMCM_CLKOUT3_EN" VALUE="FALSE"/>
+        <PARAMETER NAME="C6_MMCM_CLKOUT4_EN" VALUE="FALSE"/>
+        <PARAMETER NAME="C6_C_S_AXI_CTRL_ID_WIDTH" VALUE="4"/>
+        <PARAMETER NAME="C6_C_S_AXI_CTRL_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C6_C_S_AXI_CTRL_ADDR_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C6_C_S_AXI_CTRL_MEM_SIZE" VALUE="1048576"/>
+        <PARAMETER NAME="C6_C_S_AXI_ID_WIDTH" VALUE="4"/>
+        <PARAMETER NAME="C6_C_S_AXI_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C6_C_S_AXI_ADDR_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C6_C_S_AXI_MEM_SIZE" VALUE="1048576"/>
+        <PARAMETER NAME="C6_QDRIIP_NUM_DEVICES" VALUE="1"/>
+        <PARAMETER NAME="C6_QDRIIP_DATA_WIDTH" VALUE="18"/>
+        <PARAMETER NAME="C6_QDRIIP_ADDR_WIDTH" VALUE="29"/>
+        <PARAMETER NAME="C6_QDRIIP_BW_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="C6_QDRIIP_DEBUG_PORT" VALUE="OFF"/>
+        <PARAMETER NAME="C6_QDRIIP_BURST_LEN" VALUE="1"/>
+        <PARAMETER NAME="C6_RLDII_NUM_DEVICES" VALUE="1"/>
+        <PARAMETER NAME="C6_RLDII_DATA_WIDTH" VALUE="18"/>
+        <PARAMETER NAME="C6_RLDII_RLD_ADDR_WIDTH" VALUE="29"/>
+        <PARAMETER NAME="C6_RLDII_QK_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="C6_RLDII_CK_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C6_RLDII_DK_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C6_RLDII_DM_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C6_RLDII_BANK_WIDTH" VALUE="2"/>
+        <PARAMETER NAME="C6_RLDII_QVLD_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C6_RLDII_DEBUG_PORT" VALUE="OFF"/>
+        <PARAMETER NAME="C6_RLDIII_NUM_DEVICES" VALUE="1"/>
+        <PARAMETER NAME="C6_RLDIII_DATA_WIDTH" VALUE="18"/>
+        <PARAMETER NAME="C6_RLDIII_RLD_ADDR_WIDTH" VALUE="29"/>
+        <PARAMETER NAME="C6_RLDIII_QK_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="C6_RLDIII_CK_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C6_RLDIII_DK_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C6_RLDIII_DM_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C6_RLDIII_BANK_WIDTH" VALUE="2"/>
+        <PARAMETER NAME="C6_RLDIII_QVLD_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C6_RLDIII_DEBUG_PORT" VALUE="OFF"/>
+        <PARAMETER NAME="C6_RLDX_CMD_PER_CLK" VALUE="1"/>
+        <PARAMETER NAME="C6_RLDX_DATA_WIDTH" VALUE="18"/>
+        <PARAMETER NAME="C6_RLDX_ADDR_WIDTH" VALUE="29"/>
+        <PARAMETER NAME="C6_RLDX_BANK_WIDTH" VALUE="2"/>
+        <PARAMETER NAME="C6_RLDX_nCK_PER_CLK" VALUE="1"/>
+        <PARAMETER NAME="C6_RLDX_DM_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C6_RLDII_CMD_PER_CLK" VALUE="1"/>
+        <PARAMETER NAME="C6_RLDII_ADDR_WIDTH" VALUE="29"/>
+        <PARAMETER NAME="C6_RLDII_nCK_PER_CLK" VALUE="1"/>
+        <PARAMETER NAME="C6_RLDIII_CMD_PER_CLK" VALUE="1"/>
+        <PARAMETER NAME="C6_RLDIII_ADDR_WIDTH" VALUE="29"/>
+        <PARAMETER NAME="C6_RLDIII_nCK_PER_CLK" VALUE="1"/>
+        <PARAMETER NAME="C6_POLARITY" VALUE="ACTIVE_LOW"/>
+        <PARAMETER NAME="C7_MEM_TYPE" VALUE="DDR3"/>
+        <PARAMETER NAME="C7_IS_CLK_SHARED" VALUE="FALSE"/>
+        <PARAMETER NAME="C7_SYSCLK_TYPE" VALUE="DIFF"/>
+        <PARAMETER NAME="C7_USE_AXI" VALUE="0"/>
+        <PARAMETER NAME="C7_ECC" VALUE="OFF"/>
+        <PARAMETER NAME="C7_DDR3_DQ_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="C7_DDR3_DQS_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C7_DDR3_ROW_WIDTH" VALUE="14"/>
+        <PARAMETER NAME="C7_DDR3_BANK_WIDTH" VALUE="3"/>
+        <PARAMETER NAME="C7_DDR3_CK_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C7_DDR3_CKE_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C7_DDR3_CS_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C7_DDR3_nCS_PER_RANK" VALUE="1"/>
+        <PARAMETER NAME="C7_DDR3_DM_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C7_DDR3_ODT_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C7_DDR3_USE_CS_PORT" VALUE="1"/>
+        <PARAMETER NAME="C7_DDR3_USE_DM_PORT" VALUE="1"/>
+        <PARAMETER NAME="C7_DDR3_USE_ODT_PORT" VALUE="1"/>
+        <PARAMETER NAME="C7_DDR3_REG_CTRL" VALUE="OFF"/>
+        <PARAMETER NAME="C7_DDR3_DQS_CNT_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C7_DDR3_DEBUG_PORT" VALUE="OFF"/>
+        <PARAMETER NAME="C7_DDR2_DQ_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="C7_DDR2_DQS_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C7_DDR2_ROW_WIDTH" VALUE="14"/>
+        <PARAMETER NAME="C7_DDR2_BANK_WIDTH" VALUE="3"/>
+        <PARAMETER NAME="C7_DDR2_CK_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C7_DDR2_CKE_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C7_DDR2_CS_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C7_DDR2_nCS_PER_RANK" VALUE="1"/>
+        <PARAMETER NAME="C7_DDR2_DM_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C7_DDR2_ODT_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C7_DDR2_USE_CS_PORT" VALUE="1"/>
+        <PARAMETER NAME="C7_DDR2_USE_DM_PORT" VALUE="1"/>
+        <PARAMETER NAME="C7_DDR2_USE_ODT_PORT" VALUE="1"/>
+        <PARAMETER NAME="C7_DDR2_REG_CTRL" VALUE="OFF"/>
+        <PARAMETER NAME="C7_DDR2_DQS_CNT_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C7_DDR2_DEBUG_PORT" VALUE="OFF"/>
+        <PARAMETER NAME="C7_LPDDR2_DQ_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="C7_LPDDR2_DQS_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C7_LPDDR2_ROW_WIDTH" VALUE="14"/>
+        <PARAMETER NAME="C7_LPDDR2_BANK_WIDTH" VALUE="3"/>
+        <PARAMETER NAME="C7_LPDDR2_CK_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C7_LPDDR2_CKE_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C7_LPDDR2_CS_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C7_LPDDR2_nCS_PER_RANK" VALUE="1"/>
+        <PARAMETER NAME="C7_LPDDR2_DM_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C7_LPDDR2_USE_CS_PORT" VALUE="1"/>
+        <PARAMETER NAME="C7_LPDDR2_USE_DM_PORT" VALUE="1"/>
+        <PARAMETER NAME="C7_LPDDR2_USE_ODT_PORT" VALUE="1"/>
+        <PARAMETER NAME="C7_LPDDR2_REG_CTRL" VALUE="OFF"/>
+        <PARAMETER NAME="C7_LPDDR2_DQS_CNT_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C7_LPDDR2_DEBUG_PORT" VALUE="OFF"/>
+        <PARAMETER NAME="C7_DQS_CNT_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C7_DEBUG_PORT" VALUE="OFF"/>
+        <PARAMETER NAME="C7_DDRX_ADDR_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="C7_DDRX_nCK_PER_CLK" VALUE="2"/>
+        <PARAMETER NAME="C7_DDRX_DATA_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="C7_DDR3_ADDR_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="C7_DDR3_nCK_PER_CLK" VALUE="2"/>
+        <PARAMETER NAME="C7_DDR3_DATA_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="C7_DDR2_ADDR_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="C7_DDR2_nCK_PER_CLK" VALUE="2"/>
+        <PARAMETER NAME="C7_DDR2_DATA_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="C7_LPDDR2_ADDR_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="C7_LPDDR2_nCK_PER_CLK" VALUE="2"/>
+        <PARAMETER NAME="C7_LPDDR2_DATA_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="C7_FREQ_HZ" VALUE="100.0"/>
+        <PARAMETER NAME="C7_PHASE" VALUE="0.000"/>
+        <PARAMETER NAME="C7_UI_EXTRA_CLOCKS" VALUE="FALSE"/>
+        <PARAMETER NAME="C7_MMCM_VCO" VALUE="1200.0"/>
+        <PARAMETER NAME="C7_MMCM_CLKOUT0_FREQ" VALUE="10.0"/>
+        <PARAMETER NAME="C7_MMCM_CLKOUT1_FREQ" VALUE="10"/>
+        <PARAMETER NAME="C7_MMCM_CLKOUT2_FREQ" VALUE="10"/>
+        <PARAMETER NAME="C7_MMCM_CLKOUT3_FREQ" VALUE="10"/>
+        <PARAMETER NAME="C7_MMCM_CLKOUT4_FREQ" VALUE="10"/>
+        <PARAMETER NAME="C7_MMCM_CLKOUT0_EN" VALUE="FALSE"/>
+        <PARAMETER NAME="C7_MMCM_CLKOUT2_EN" VALUE="FALSE"/>
+        <PARAMETER NAME="C7_MMCM_CLKOUT1_EN" VALUE="FALSE"/>
+        <PARAMETER NAME="C7_MMCM_CLKOUT3_EN" VALUE="FALSE"/>
+        <PARAMETER NAME="C7_MMCM_CLKOUT4_EN" VALUE="FALSE"/>
+        <PARAMETER NAME="C7_C_S_AXI_CTRL_ID_WIDTH" VALUE="4"/>
+        <PARAMETER NAME="C7_C_S_AXI_CTRL_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C7_C_S_AXI_CTRL_ADDR_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C7_C_S_AXI_CTRL_MEM_SIZE" VALUE="1048576"/>
+        <PARAMETER NAME="C7_C_S_AXI_ID_WIDTH" VALUE="4"/>
+        <PARAMETER NAME="C7_C_S_AXI_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C7_C_S_AXI_ADDR_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C7_C_S_AXI_MEM_SIZE" VALUE="1048576"/>
+        <PARAMETER NAME="C7_QDRIIP_NUM_DEVICES" VALUE="1"/>
+        <PARAMETER NAME="C7_QDRIIP_DATA_WIDTH" VALUE="18"/>
+        <PARAMETER NAME="C7_QDRIIP_ADDR_WIDTH" VALUE="29"/>
+        <PARAMETER NAME="C7_QDRIIP_BW_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="C7_QDRIIP_DEBUG_PORT" VALUE="OFF"/>
+        <PARAMETER NAME="C7_QDRIIP_BURST_LEN" VALUE="1"/>
+        <PARAMETER NAME="C7_RLDII_NUM_DEVICES" VALUE="1"/>
+        <PARAMETER NAME="C7_RLDII_DATA_WIDTH" VALUE="18"/>
+        <PARAMETER NAME="C7_RLDII_RLD_ADDR_WIDTH" VALUE="29"/>
+        <PARAMETER NAME="C7_RLDII_QK_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="C7_RLDII_CK_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C7_RLDII_DK_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C7_RLDII_DM_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C7_RLDII_BANK_WIDTH" VALUE="2"/>
+        <PARAMETER NAME="C7_RLDII_QVLD_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C7_RLDII_DEBUG_PORT" VALUE="OFF"/>
+        <PARAMETER NAME="C7_RLDIII_NUM_DEVICES" VALUE="1"/>
+        <PARAMETER NAME="C7_RLDIII_DATA_WIDTH" VALUE="18"/>
+        <PARAMETER NAME="C7_RLDIII_RLD_ADDR_WIDTH" VALUE="29"/>
+        <PARAMETER NAME="C7_RLDIII_QK_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="C7_RLDIII_CK_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C7_RLDIII_DK_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C7_RLDIII_DM_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C7_RLDIII_BANK_WIDTH" VALUE="2"/>
+        <PARAMETER NAME="C7_RLDIII_QVLD_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C7_RLDIII_DEBUG_PORT" VALUE="OFF"/>
+        <PARAMETER NAME="C7_RLDX_CMD_PER_CLK" VALUE="1"/>
+        <PARAMETER NAME="C7_RLDX_DATA_WIDTH" VALUE="18"/>
+        <PARAMETER NAME="C7_RLDX_ADDR_WIDTH" VALUE="29"/>
+        <PARAMETER NAME="C7_RLDX_BANK_WIDTH" VALUE="2"/>
+        <PARAMETER NAME="C7_RLDX_nCK_PER_CLK" VALUE="1"/>
+        <PARAMETER NAME="C7_RLDX_DM_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C7_RLDII_CMD_PER_CLK" VALUE="1"/>
+        <PARAMETER NAME="C7_RLDII_ADDR_WIDTH" VALUE="29"/>
+        <PARAMETER NAME="C7_RLDII_nCK_PER_CLK" VALUE="1"/>
+        <PARAMETER NAME="C7_RLDIII_CMD_PER_CLK" VALUE="1"/>
+        <PARAMETER NAME="C7_RLDIII_ADDR_WIDTH" VALUE="29"/>
+        <PARAMETER NAME="C7_RLDIII_nCK_PER_CLK" VALUE="1"/>
+        <PARAMETER NAME="C7_POLARITY" VALUE="ACTIVE_LOW"/>
+        <PARAMETER NAME="XML_INPUT_FILE" VALUE="board.prj"/>
+        <PARAMETER NAME="RESET_BOARD_INTERFACE" VALUE="reset"/>
+        <PARAMETER NAME="MIG_DONT_TOUCH_PARAM" VALUE="Custom"/>
+        <PARAMETER NAME="BOARD_MIG_PARAM" VALUE="ddr3_sdram"/>
+        <PARAMETER NAME="Component_Name" VALUE="base_microblaze_design_mig_7series_0_0"/>
+        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
+        <PARAMETER NAME="EDK_SPECIAL" VALUE="MEMORY_CTRL"/>
+        <PARAMETER NAME="C_BASEADDR" VALUE="0x80000000"/>
+        <PARAMETER NAME="C_HIGHADDR" VALUE="0xBFFFFFFF"/>
+      </PARAMETERS>
+      <PORTS>
+        <PORT DIR="I" NAME="sys_rst" SIGIS="rst" SIGNAME="External_Ports_reset">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="External_Ports" PORT="reset"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="IO" LEFT="63" NAME="ddr3_dq" RIGHT="0" SIGIS="undef"/>
+        <PORT DIR="IO" LEFT="7" NAME="ddr3_dqs_p" RIGHT="0" SIGIS="undef"/>
+        <PORT DIR="IO" LEFT="7" NAME="ddr3_dqs_n" RIGHT="0" SIGIS="undef"/>
+        <PORT DIR="O" LEFT="13" NAME="ddr3_addr" RIGHT="0" SIGIS="undef"/>
+        <PORT DIR="O" LEFT="2" NAME="ddr3_ba" RIGHT="0" SIGIS="undef"/>
+        <PORT DIR="O" NAME="ddr3_ras_n" SIGIS="undef"/>
+        <PORT DIR="O" NAME="ddr3_cas_n" SIGIS="undef"/>
+        <PORT DIR="O" NAME="ddr3_we_n" SIGIS="undef"/>
+        <PORT DIR="O" NAME="ddr3_reset_n" SIGIS="undef"/>
+        <PORT DIR="O" LEFT="0" NAME="ddr3_ck_p" RIGHT="0" SIGIS="undef"/>
+        <PORT DIR="O" LEFT="0" NAME="ddr3_ck_n" RIGHT="0" SIGIS="undef"/>
+        <PORT DIR="O" LEFT="0" NAME="ddr3_cke" RIGHT="0" SIGIS="undef"/>
+        <PORT DIR="O" LEFT="0" NAME="ddr3_cs_n" RIGHT="0" SIGIS="undef"/>
+        <PORT DIR="O" LEFT="7" NAME="ddr3_dm" RIGHT="0" SIGIS="undef"/>
+        <PORT DIR="O" LEFT="0" NAME="ddr3_odt" RIGHT="0" SIGIS="undef"/>
+        <PORT DIR="O" NAME="ui_clk_sync_rst" SIGIS="rst" SIGNAME="mig_7series_0_ui_clk_sync_rst">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="rst_clk_wiz_1_100M" PORT="ext_reset_in"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT CLKFREQUENCY="100000000" DIR="O" NAME="ui_clk" SIGIS="clk" SIGNAME="mig_7series_0_ui_clk">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="Clk"/>
+            <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_v10" PORT="LMB_Clk"/>
+            <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_bram_if_cntlr" PORT="LMB_Clk"/>
+            <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_v10" PORT="LMB_Clk"/>
+            <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_bram_if_cntlr" PORT="LMB_Clk"/>
+            <CONNECTION INSTANCE="rst_clk_wiz_1_100M" PORT="slowest_sync_clk"/>
+            <CONNECTION INSTANCE="axi_uartlite_0" PORT="s_axi_aclk"/>
+            <CONNECTION INSTANCE="axi_gpio_0" PORT="s_axi_aclk"/>
+            <CONNECTION INSTANCE="axi_timer_0" PORT="s_axi_aclk"/>
+            <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_aclk"/>
+            <CONNECTION INSTANCE="axi_ethernetlite_0" PORT="s_axi_aclk"/>
+            <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="S00_ACLK"/>
+            <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="ACLK"/>
+            <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M00_ACLK"/>
+            <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M01_ACLK"/>
+            <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M02_ACLK"/>
+            <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M03_ACLK"/>
+            <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M04_ACLK"/>
+            <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_ACLK"/>
+            <CONNECTION INSTANCE="axi_mem_intercon" PORT="ACLK"/>
+            <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_ACLK"/>
+            <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_ACLK"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="0" NAME="s_axi_awid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_awid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="31" NAME="s_axi_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awaddr">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_awaddr"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="7" NAME="s_axi_awlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awlen">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_awlen"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="2" NAME="s_axi_awsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awsize">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_awsize"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="1" NAME="s_axi_awburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awburst">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_awburst"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="s_axi_awlock" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awlock">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_awlock"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="3" NAME="s_axi_awcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awcache">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_awcache"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="2" NAME="s_axi_awprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awprot">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_awprot"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="3" NAME="s_axi_awqos" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awqos">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_awqos"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="s_axi_awvalid" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_awvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="s_axi_awready" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_awready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="31" NAME="s_axi_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_wdata">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_wdata"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="3" NAME="s_axi_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_wstrb">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_wstrb"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="s_axi_wlast" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_wlast">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_wlast"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="s_axi_wvalid" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_wvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_wvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="s_axi_wready" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_wready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_wready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="s_axi_bready" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_bready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_bready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="0" NAME="s_axi_bid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_bid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_bid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="1" NAME="s_axi_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_bresp">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_bresp"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="s_axi_bvalid" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_bvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_bvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="0" NAME="s_axi_arid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_arid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="31" NAME="s_axi_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_araddr">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_araddr"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="7" NAME="s_axi_arlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arlen">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_arlen"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="2" NAME="s_axi_arsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arsize">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_arsize"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="1" NAME="s_axi_arburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arburst">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_arburst"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="s_axi_arlock" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arlock">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_arlock"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="3" NAME="s_axi_arcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arcache">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_arcache"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="2" NAME="s_axi_arprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arprot">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_arprot"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="3" NAME="s_axi_arqos" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arqos">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_arqos"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="s_axi_arvalid" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_arvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="s_axi_arready" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_arready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="s_axi_rready" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_rready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_rready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="0" NAME="s_axi_rid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_rid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_rid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="31" NAME="s_axi_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_rdata">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_rdata"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="1" NAME="s_axi_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_rresp">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_rresp"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="s_axi_rlast" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_rlast">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_rlast"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="s_axi_rvalid" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_rvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_rvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="mmcm_locked" SIGIS="undef" SIGNAME="mig_7series_0_mmcm_locked">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="rst_clk_wiz_1_100M" PORT="dcm_locked"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="sys_clk_p" SIGIS="undef"/>
+        <PORT DIR="I" NAME="sys_clk_n" SIGIS="undef"/>
+        <PORT DIR="O" NAME="init_calib_complete" SIGIS="undef"/>
+        <PORT DIR="I" NAME="aresetn" SIGIS="rst" SIGNAME="rst_clk_wiz_1_100M_peripheral_aresetn">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="rst_clk_wiz_1_100M" PORT="peripheral_aresetn"/>
+          </CONNECTIONS>
+        </PORT>
+      </PORTS>
+      <BUSINTERFACES>
+        <BUSINTERFACE BUSNAME="mig_7series_0_DDR3" NAME="DDR3" TYPE="INITIATOR">
+          <PORTMAPS>
+            <PORTMAP PHYSICAL="ddr3_dq"/>
+            <PORTMAP PHYSICAL="ddr3_dqs_p"/>
+            <PORTMAP PHYSICAL="ddr3_dqs_n"/>
+            <PORTMAP PHYSICAL="ddr3_addr"/>
+            <PORTMAP PHYSICAL="ddr3_ba"/>
+            <PORTMAP PHYSICAL="ddr3_ras_n"/>
+            <PORTMAP PHYSICAL="ddr3_cas_n"/>
+            <PORTMAP PHYSICAL="ddr3_we_n"/>
+            <PORTMAP PHYSICAL="ddr3_reset_n"/>
+            <PORTMAP PHYSICAL="ddr3_ck_p"/>
+            <PORTMAP PHYSICAL="ddr3_ck_n"/>
+            <PORTMAP PHYSICAL="ddr3_cke"/>
+            <PORTMAP PHYSICAL="ddr3_cs_n"/>
+            <PORTMAP PHYSICAL="ddr3_dm"/>
+            <PORTMAP PHYSICAL="ddr3_odt"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="axi_mem_intercon_M00_AXI" NAME="S_AXI" TYPE="SLAVE">
+          <PORTMAPS>
+            <PORTMAP PHYSICAL="s_axi_awid"/>
+            <PORTMAP PHYSICAL="s_axi_awaddr"/>
+            <PORTMAP PHYSICAL="s_axi_awlen"/>
+            <PORTMAP PHYSICAL="s_axi_awsize"/>
+            <PORTMAP PHYSICAL="s_axi_awburst"/>
+            <PORTMAP PHYSICAL="s_axi_awlock"/>
+            <PORTMAP PHYSICAL="s_axi_awcache"/>
+            <PORTMAP PHYSICAL="s_axi_awprot"/>
+            <PORTMAP PHYSICAL="s_axi_awqos"/>
+            <PORTMAP PHYSICAL="s_axi_awvalid"/>
+            <PORTMAP PHYSICAL="s_axi_awready"/>
+            <PORTMAP PHYSICAL="s_axi_wdata"/>
+            <PORTMAP PHYSICAL="s_axi_wstrb"/>
+            <PORTMAP PHYSICAL="s_axi_wlast"/>
+            <PORTMAP PHYSICAL="s_axi_wvalid"/>
+            <PORTMAP PHYSICAL="s_axi_wready"/>
+            <PORTMAP PHYSICAL="s_axi_bready"/>
+            <PORTMAP PHYSICAL="s_axi_bid"/>
+            <PORTMAP PHYSICAL="s_axi_bresp"/>
+            <PORTMAP PHYSICAL="s_axi_bvalid"/>
+            <PORTMAP PHYSICAL="s_axi_arid"/>
+            <PORTMAP PHYSICAL="s_axi_araddr"/>
+            <PORTMAP PHYSICAL="s_axi_arlen"/>
+            <PORTMAP PHYSICAL="s_axi_arsize"/>
+            <PORTMAP PHYSICAL="s_axi_arburst"/>
+            <PORTMAP PHYSICAL="s_axi_arlock"/>
+            <PORTMAP PHYSICAL="s_axi_arcache"/>
+            <PORTMAP PHYSICAL="s_axi_arprot"/>
+            <PORTMAP PHYSICAL="s_axi_arqos"/>
+            <PORTMAP PHYSICAL="s_axi_arvalid"/>
+            <PORTMAP PHYSICAL="s_axi_arready"/>
+            <PORTMAP PHYSICAL="s_axi_rready"/>
+            <PORTMAP PHYSICAL="s_axi_rid"/>
+            <PORTMAP PHYSICAL="s_axi_rdata"/>
+            <PORTMAP PHYSICAL="s_axi_rresp"/>
+            <PORTMAP PHYSICAL="s_axi_rlast"/>
+            <PORTMAP PHYSICAL="s_axi_rvalid"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="External_Interface_sys_diff_clock" NAME="SYS_CLK" TYPE="TARGET">
+          <PORTMAPS>
+            <PORTMAP PHYSICAL="sys_clk_p"/>
+            <PORTMAP PHYSICAL="sys_clk_n"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+      </BUSINTERFACES>
+    </MODULE>
+    <MODULE FULLNAME="/rst_clk_wiz_1_100M" HWVERSION="5.0" INSTANCE="rst_clk_wiz_1_100M" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="proc_sys_reset" VLNV="xilinx.com:ip:proc_sys_reset:5.0">
+      <DOCUMENTS>
+        <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=proc_sys_reset;v=v5_0;d=pg164-proc-sys-reset.pdf"/>
+      </DOCUMENTS>
+      <PARAMETERS>
+        <PARAMETER NAME="C_FAMILY" VALUE="kintex7"/>
+        <PARAMETER NAME="C_EXT_RST_WIDTH" VALUE="4"/>
+        <PARAMETER NAME="C_AUX_RST_WIDTH" VALUE="4"/>
+        <PARAMETER NAME="C_EXT_RESET_HIGH" VALUE="1"/>
+        <PARAMETER NAME="C_AUX_RESET_HIGH" VALUE="0"/>
+        <PARAMETER NAME="C_NUM_BUS_RST" VALUE="1"/>
+        <PARAMETER NAME="C_NUM_PERP_RST" VALUE="1"/>
+        <PARAMETER NAME="C_NUM_INTERCONNECT_ARESETN" VALUE="1"/>
+        <PARAMETER NAME="C_NUM_PERP_ARESETN" VALUE="1"/>
+        <PARAMETER NAME="Component_Name" VALUE="base_microblaze_design_rst_clk_wiz_1_100M_0"/>
+        <PARAMETER NAME="USE_BOARD_FLOW" VALUE="true"/>
+        <PARAMETER NAME="RESET_BOARD_INTERFACE" VALUE="Custom"/>
+        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
+      </PARAMETERS>
+      <PORTS>
+        <PORT CLKFREQUENCY="100000000" DIR="I" NAME="slowest_sync_clk" SIGIS="clk" SIGNAME="mig_7series_0_ui_clk">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="mig_7series_0" PORT="ui_clk"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="ext_reset_in" SIGIS="rst" SIGNAME="mig_7series_0_ui_clk_sync_rst">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="mig_7series_0" PORT="ui_clk_sync_rst"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="aux_reset_in" SIGIS="rst"/>
+        <PORT DIR="I" NAME="mb_debug_sys_rst" SIGIS="rst" SIGNAME="mdm_1_Debug_SYS_Rst">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="mdm_1" PORT="Debug_SYS_Rst"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="dcm_locked" SIGIS="undef" SIGNAME="mig_7series_0_mmcm_locked">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="mig_7series_0" PORT="mmcm_locked"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="mb_reset" SIGIS="rst" SIGNAME="rst_clk_wiz_1_100M_mb_reset">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="Reset"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="0" NAME="bus_struct_reset" RIGHT="0" SIGIS="rst" SIGNAME="rst_clk_wiz_1_100M_bus_struct_reset">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_v10" PORT="SYS_Rst"/>
+            <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_bram_if_cntlr" PORT="LMB_Rst"/>
+            <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_v10" PORT="SYS_Rst"/>
+            <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_bram_if_cntlr" PORT="LMB_Rst"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="0" NAME="peripheral_reset" RIGHT="0" SIGIS="rst"/>
+        <PORT DIR="O" LEFT="0" NAME="interconnect_aresetn" RIGHT="0" SIGIS="rst" SIGNAME="rst_clk_wiz_1_100M_interconnect_aresetn">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="ARESETN"/>
+            <CONNECTION INSTANCE="axi_mem_intercon" PORT="ARESETN"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="0" NAME="peripheral_aresetn" RIGHT="0" SIGIS="rst" SIGNAME="rst_clk_wiz_1_100M_peripheral_aresetn">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_uartlite_0" PORT="s_axi_aresetn"/>
+            <CONNECTION INSTANCE="axi_gpio_0" PORT="s_axi_aresetn"/>
+            <CONNECTION INSTANCE="axi_timer_0" PORT="s_axi_aresetn"/>
+            <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_aresetn"/>
+            <CONNECTION INSTANCE="axi_ethernetlite_0" PORT="s_axi_aresetn"/>
+            <CONNECTION INSTANCE="mig_7series_0" PORT="aresetn"/>
+            <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="S00_ARESETN"/>
+            <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M00_ARESETN"/>
+            <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M01_ARESETN"/>
+            <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M02_ARESETN"/>
+            <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M03_ARESETN"/>
+            <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M04_ARESETN"/>
+            <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_ARESETN"/>
+            <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_ARESETN"/>
+            <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_ARESETN"/>
+          </CONNECTIONS>
+        </PORT>
+      </PORTS>
+      <BUSINTERFACES/>
+    </MODULE>
+  </MODULES>
+
+  <REPOSITORIES/>
+
+</EDKSYSTEM>
diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/Hardware/base_microblaze_design_bd.tcl b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/Hardware/base_microblaze_design_bd.tcl
new file mode 100644 (file)
index 0000000..ef538a0
--- /dev/null
+++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/Hardware/base_microblaze_design_bd.tcl
@@ -0,0 +1,360 @@
+\r
+################################################################\r
+# This is a generated script based on design: base_microblaze_design\r
+#\r
+# Though there are limitations about the generated script,\r
+# the main purpose of this utility is to make learning\r
+# IP Integrator Tcl commands easier.\r
+################################################################\r
+\r
+################################################################\r
+# Check if script is running in correct Vivado version.\r
+################################################################\r
+set scripts_vivado_version 2014.4\r
+set current_vivado_version [version -short]\r
+\r
+if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {\r
+   puts ""\r
+   puts "ERROR: This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."\r
+\r
+   return 1\r
+}\r
+\r
+################################################################\r
+# START\r
+################################################################\r
+\r
+# To test this script, run the following commands from Vivado Tcl console:\r
+# source base_microblaze_design_script.tcl\r
+\r
+# If you do not already have a project created,\r
+# you can create a project using the following command:\r
+#    create_project project_1 myproj -part xc7k325tffg900-2\r
+#    set_property BOARD_PART xilinx.com:kc705:part0:1.1 [current_project]\r
+\r
+\r
+# CHANGE DESIGN NAME HERE\r
+set design_name base_microblaze_design\r
+\r
+# If you do not already have an existing IP Integrator design open,\r
+# you can create a design using the following command:\r
+#    create_bd_design $design_name\r
+\r
+# CHECKING IF PROJECT EXISTS\r
+if { [get_projects -quiet] eq "" } {\r
+   puts "ERROR: Please open or create a project!"\r
+   return 1\r
+}\r
+\r
+\r
+# Creating design if needed\r
+set errMsg ""\r
+set nRet 0\r
+\r
+set cur_design [current_bd_design -quiet]\r
+set list_cells [get_bd_cells -quiet]\r
+\r
+if { ${design_name} eq "" } {\r
+   # USE CASES:\r
+   #    1) Design_name not set\r
+\r
+   set errMsg "ERROR: Please set the variable <design_name> to a non-empty value."\r
+   set nRet 1\r
+\r
+} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {\r
+   # USE CASES:\r
+   #    2): Current design opened AND is empty AND names same.\r
+   #    3): Current design opened AND is empty AND names diff; design_name NOT in project.\r
+   #    4): Current design opened AND is empty AND names diff; design_name exists in project.\r
+\r
+   if { $cur_design ne $design_name } {\r
+      puts "INFO: Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."\r
+      set design_name [get_property NAME $cur_design]\r
+   }\r
+   puts "INFO: Constructing design in IPI design <$cur_design>..."\r
+\r
+} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {\r
+   # USE CASES:\r
+   #    5) Current design opened AND has components AND same names.\r
+\r
+   set errMsg "ERROR: Design <$design_name> already exists in your project, please set the variable <design_name> to another value."\r
+   set nRet 1\r
+} elseif { [get_files -quiet ${design_name}.bd] ne "" } {\r
+   # USE CASES: \r
+   #    6) Current opened design, has components, but diff names, design_name exists in project.\r
+   #    7) No opened design, design_name exists in project.\r
+\r
+   set errMsg "ERROR: Design <$design_name> already exists in your project, please set the variable <design_name> to another value."\r
+   set nRet 2\r
+\r
+} else {\r
+   # USE CASES:\r
+   #    8) No opened design, design_name not in project.\r
+   #    9) Current opened design, has components, but diff names, design_name not in project.\r
+\r
+   puts "INFO: Currently there is no design <$design_name> in project, so creating one..."\r
+\r
+   create_bd_design $design_name\r
+\r
+   puts "INFO: Making design <$design_name> as current_bd_design."\r
+   current_bd_design $design_name\r
+\r
+}\r
+\r
+puts "INFO: Currently the variable <design_name> is equal to \"$design_name\"."\r
+\r
+if { $nRet != 0 } {\r
+   puts $errMsg\r
+   return $nRet\r
+}\r
+\r
+##################################################################\r
+# DESIGN PROCs\r
+##################################################################\r
+\r
+\r
+# Hierarchical cell: microblaze_0_local_memory\r
+proc create_hier_cell_microblaze_0_local_memory { parentCell nameHier } {\r
+\r
+  if { $parentCell eq "" || $nameHier eq "" } {\r
+     puts "ERROR: create_hier_cell_microblaze_0_local_memory() - Empty argument(s)!"\r
+     return\r
+  }\r
+\r
+  # Get object for parentCell\r
+  set parentObj [get_bd_cells $parentCell]\r
+  if { $parentObj == "" } {\r
+     puts "ERROR: Unable to find parent cell <$parentCell>!"\r
+     return\r
+  }\r
+\r
+  # Make sure parentObj is hier blk\r
+  set parentType [get_property TYPE $parentObj]\r
+  if { $parentType ne "hier" } {\r
+     puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."\r
+     return\r
+  }\r
+\r
+  # Save current instance; Restore later\r
+  set oldCurInst [current_bd_instance .]\r
+\r
+  # Set parent object as current\r
+  current_bd_instance $parentObj\r
+\r
+  # Create cell and set as current instance\r
+  set hier_obj [create_bd_cell -type hier $nameHier]\r
+  current_bd_instance $hier_obj\r
+\r
+  # Create interface pins\r
+  create_bd_intf_pin -mode MirroredMaster -vlnv xilinx.com:interface:lmb_rtl:1.0 DLMB\r
+  create_bd_intf_pin -mode MirroredMaster -vlnv xilinx.com:interface:lmb_rtl:1.0 ILMB\r
+\r
+  # Create pins\r
+  create_bd_pin -dir I -type clk LMB_Clk\r
+  create_bd_pin -dir I -from 0 -to 0 -type rst LMB_Rst\r
+\r
+  # Create instance: dlmb_bram_if_cntlr, and set properties\r
+  set dlmb_bram_if_cntlr [ create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_bram_if_cntlr:4.0 dlmb_bram_if_cntlr ]\r
+  set_property -dict [ list CONFIG.C_ECC {0}  ] $dlmb_bram_if_cntlr\r
+\r
+  # Create instance: dlmb_v10, and set properties\r
+  set dlmb_v10 [ create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_v10:3.0 dlmb_v10 ]\r
+\r
+  # Create instance: ilmb_bram_if_cntlr, and set properties\r
+  set ilmb_bram_if_cntlr [ create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_bram_if_cntlr:4.0 ilmb_bram_if_cntlr ]\r
+  set_property -dict [ list CONFIG.C_ECC {0}  ] $ilmb_bram_if_cntlr\r
+\r
+  # Create instance: ilmb_v10, and set properties\r
+  set ilmb_v10 [ create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_v10:3.0 ilmb_v10 ]\r
+\r
+  # Create instance: lmb_bram, and set properties\r
+  set lmb_bram [ create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.2 lmb_bram ]\r
+  set_property -dict [ list CONFIG.Memory_Type {True_Dual_Port_RAM} CONFIG.use_bram_block {BRAM_Controller}  ] $lmb_bram\r
+\r
+  # Create interface connections\r
+  connect_bd_intf_net -intf_net microblaze_0_dlmb [get_bd_intf_pins DLMB] [get_bd_intf_pins dlmb_v10/LMB_M]\r
+  connect_bd_intf_net -intf_net microblaze_0_dlmb_bus [get_bd_intf_pins dlmb_bram_if_cntlr/SLMB] [get_bd_intf_pins dlmb_v10/LMB_Sl_0]\r
+  connect_bd_intf_net -intf_net microblaze_0_dlmb_cntlr [get_bd_intf_pins dlmb_bram_if_cntlr/BRAM_PORT] [get_bd_intf_pins lmb_bram/BRAM_PORTA]\r
+  connect_bd_intf_net -intf_net microblaze_0_ilmb [get_bd_intf_pins ILMB] [get_bd_intf_pins ilmb_v10/LMB_M]\r
+  connect_bd_intf_net -intf_net microblaze_0_ilmb_bus [get_bd_intf_pins ilmb_bram_if_cntlr/SLMB] [get_bd_intf_pins ilmb_v10/LMB_Sl_0]\r
+  connect_bd_intf_net -intf_net microblaze_0_ilmb_cntlr [get_bd_intf_pins ilmb_bram_if_cntlr/BRAM_PORT] [get_bd_intf_pins lmb_bram/BRAM_PORTB]\r
+\r
+  # Create port connections\r
+  connect_bd_net -net microblaze_0_Clk [get_bd_pins LMB_Clk] [get_bd_pins dlmb_bram_if_cntlr/LMB_Clk] [get_bd_pins dlmb_v10/LMB_Clk] [get_bd_pins ilmb_bram_if_cntlr/LMB_Clk] [get_bd_pins ilmb_v10/LMB_Clk]\r
+  connect_bd_net -net microblaze_0_LMB_Rst [get_bd_pins LMB_Rst] [get_bd_pins dlmb_bram_if_cntlr/LMB_Rst] [get_bd_pins dlmb_v10/SYS_Rst] [get_bd_pins ilmb_bram_if_cntlr/LMB_Rst] [get_bd_pins ilmb_v10/SYS_Rst]\r
+  \r
+  # Restore current instance\r
+  current_bd_instance $oldCurInst\r
+}\r
+\r
+\r
+# Procedure to create entire design; Provide argument to make\r
+# procedure reusable. If parentCell is "", will use root.\r
+proc create_root_design { parentCell } {\r
+\r
+  if { $parentCell eq "" } {\r
+     set parentCell [get_bd_cells /]\r
+  }\r
+\r
+  # Get object for parentCell\r
+  set parentObj [get_bd_cells $parentCell]\r
+  if { $parentObj == "" } {\r
+     puts "ERROR: Unable to find parent cell <$parentCell>!"\r
+     return\r
+  }\r
+\r
+  # Make sure parentObj is hier blk\r
+  set parentType [get_property TYPE $parentObj]\r
+  if { $parentType ne "hier" } {\r
+     puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."\r
+     return\r
+  }\r
+\r
+  # Save current instance; Restore later\r
+  set oldCurInst [current_bd_instance .]\r
+\r
+  # Set parent object as current\r
+  current_bd_instance $parentObj\r
+\r
+\r
+  # Create interface ports\r
+  set ddr3_sdram [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr3_sdram ]\r
+  set led_8bits [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 led_8bits ]\r
+  set mdio_mdc [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:mdio_rtl:1.0 mdio_mdc ]\r
+  set mii [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:mii_rtl:1.0 mii ]\r
+  set rs232_uart [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:uart_rtl:1.0 rs232_uart ]\r
+  set sys_diff_clock [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sys_diff_clock ]\r
+\r
+  # Create ports\r
+  set reset [ create_bd_port -dir I -type rst reset ]\r
+  set_property -dict [ list CONFIG.POLARITY {ACTIVE_HIGH}  ] $reset\r
+\r
+  # Create instance: axi_ethernetlite_0, and set properties\r
+  set axi_ethernetlite_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_ethernetlite:3.0 axi_ethernetlite_0 ]\r
+  set_property -dict [ list CONFIG.MDIO_BOARD_INTERFACE {mdio_mdc} CONFIG.MII_BOARD_INTERFACE {mii} CONFIG.USE_BOARD_FLOW {true}  ] $axi_ethernetlite_0\r
+\r
+  # Create instance: axi_gpio_0, and set properties\r
+  set axi_gpio_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_0 ]\r
+  set_property -dict [ list CONFIG.GPIO_BOARD_INTERFACE {led_8bits} CONFIG.USE_BOARD_FLOW {true}  ] $axi_gpio_0\r
+\r
+  # Create instance: axi_intc_0, and set properties\r
+  set axi_intc_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_intc:4.1 axi_intc_0 ]\r
+\r
+  # Create instance: axi_mem_intercon, and set properties\r
+  set axi_mem_intercon [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_mem_intercon ]\r
+  set_property -dict [ list CONFIG.NUM_MI {1} CONFIG.NUM_SI {2}  ] $axi_mem_intercon\r
+\r
+  # Create instance: axi_timer_0, and set properties\r
+  set axi_timer_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_timer:2.0 axi_timer_0 ]\r
+\r
+  # Create instance: axi_uartlite_0, and set properties\r
+  set axi_uartlite_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_uartlite:2.0 axi_uartlite_0 ]\r
+  set_property -dict [ list CONFIG.C_BAUDRATE {115200} CONFIG.UARTLITE_BOARD_INTERFACE {rs232_uart} CONFIG.USE_BOARD_FLOW {true}  ] $axi_uartlite_0\r
+\r
+  # Create instance: mdm_1, and set properties\r
+  set mdm_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:mdm:3.2 mdm_1 ]\r
+\r
+  # Create instance: microblaze_0, and set properties\r
+  set microblaze_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:microblaze:9.4 microblaze_0 ]\r
+  set_property -dict [ list CONFIG.C_CACHE_BYTE_SIZE {32768} \\r
+CONFIG.C_DCACHE_BYTE_SIZE {32768} CONFIG.C_DCACHE_LINE_LEN {8} \\r
+CONFIG.C_DCACHE_USE_WRITEBACK {1} CONFIG.C_DCACHE_VICTIMS {8} \\r
+CONFIG.C_DEBUG_ENABLED {1} CONFIG.C_DIV_ZERO_EXCEPTION {1} \\r
+CONFIG.C_D_AXI {1} CONFIG.C_D_LMB {1} \\r
+CONFIG.C_FPU_EXCEPTION {1} CONFIG.C_ICACHE_LINE_LEN {8} \\r
+CONFIG.C_ICACHE_STREAMS {1} CONFIG.C_ICACHE_VICTIMS {8} \\r
+CONFIG.C_ILL_OPCODE_EXCEPTION {1} CONFIG.C_I_LMB {1} \\r
+CONFIG.C_M_AXI_D_BUS_EXCEPTION {1} CONFIG.C_M_AXI_I_BUS_EXCEPTION {1} \\r
+CONFIG.C_NUMBER_OF_PC_BRK {8} CONFIG.C_NUMBER_OF_RD_ADDR_BRK {2} \\r
+CONFIG.C_NUMBER_OF_WR_ADDR_BRK {2} CONFIG.C_OPCODE_0x0_ILLEGAL {1} \\r
+CONFIG.C_TRACE {1} CONFIG.C_UNALIGNED_EXCEPTIONS {1} \\r
+CONFIG.C_USE_BARREL {1} CONFIG.C_USE_BRANCH_TARGET_CACHE {1} \\r
+CONFIG.C_USE_DCACHE {1} CONFIG.C_USE_DIV {1} \\r
+CONFIG.C_USE_FPU {2} CONFIG.C_USE_HW_MUL {2} \\r
+CONFIG.C_USE_ICACHE {1} CONFIG.C_USE_MSR_INSTR {1} \\r
+CONFIG.C_USE_PCMP_INSTR {1} CONFIG.C_USE_REORDER_INSTR {1} \\r
+CONFIG.C_USE_STACK_PROTECTION {1} CONFIG.G_TEMPLATE_LIST {2} \\r
+CONFIG.G_USE_EXCEPTIONS {1}  ] $microblaze_0\r
+\r
+  # Create instance: microblaze_0_axi_periph, and set properties\r
+  set microblaze_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 microblaze_0_axi_periph ]\r
+  set_property -dict [ list CONFIG.NUM_MI {5} CONFIG.NUM_SI {1}  ] $microblaze_0_axi_periph\r
+\r
+  # Create instance: microblaze_0_local_memory\r
+  create_hier_cell_microblaze_0_local_memory [current_bd_instance .] microblaze_0_local_memory\r
+\r
+  # Create instance: mig_7series_0, and set properties\r
+  set mig_7series_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:mig_7series:2.3 mig_7series_0 ]\r
+  set_property -dict [ list CONFIG.BOARD_MIG_PARAM {ddr3_sdram} CONFIG.RESET_BOARD_INTERFACE {reset}  ] $mig_7series_0\r
+\r
+  # Create instance: rst_clk_wiz_1_100M, and set properties\r
+  set rst_clk_wiz_1_100M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_clk_wiz_1_100M ]\r
+  set_property -dict [ list CONFIG.RESET_BOARD_INTERFACE {Custom} CONFIG.USE_BOARD_FLOW {true}  ] $rst_clk_wiz_1_100M\r
+\r
+  # Create instance: xlconcat_0, and set properties\r
+  set xlconcat_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_0 ]\r
+  set_property -dict [ list CONFIG.NUM_PORTS {3}  ] $xlconcat_0\r
+\r
+  # Create interface connections\r
+  connect_bd_intf_net -intf_net SYS_CLK_1 [get_bd_intf_ports sys_diff_clock] [get_bd_intf_pins mig_7series_0/SYS_CLK]\r
+  connect_bd_intf_net -intf_net axi_ethernetlite_0_MDIO [get_bd_intf_ports mdio_mdc] [get_bd_intf_pins axi_ethernetlite_0/MDIO]\r
+  connect_bd_intf_net -intf_net axi_ethernetlite_0_MII [get_bd_intf_ports mii] [get_bd_intf_pins axi_ethernetlite_0/MII]\r
+  connect_bd_intf_net -intf_net axi_gpio_0_GPIO [get_bd_intf_ports led_8bits] [get_bd_intf_pins axi_gpio_0/GPIO]\r
+  connect_bd_intf_net -intf_net axi_intc_0_interrupt [get_bd_intf_pins axi_intc_0/interrupt] [get_bd_intf_pins microblaze_0/INTERRUPT]\r
+  connect_bd_intf_net -intf_net axi_mem_intercon_M00_AXI [get_bd_intf_pins axi_mem_intercon/M00_AXI] [get_bd_intf_pins mig_7series_0/S_AXI]\r
+  connect_bd_intf_net -intf_net axi_uartlite_0_UART [get_bd_intf_ports rs232_uart] [get_bd_intf_pins axi_uartlite_0/UART]\r
+  connect_bd_intf_net -intf_net microblaze_0_M_AXI_DC [get_bd_intf_pins axi_mem_intercon/S00_AXI] [get_bd_intf_pins microblaze_0/M_AXI_DC]\r
+  connect_bd_intf_net -intf_net microblaze_0_M_AXI_DP [get_bd_intf_pins microblaze_0/M_AXI_DP] [get_bd_intf_pins microblaze_0_axi_periph/S00_AXI]\r
+  connect_bd_intf_net -intf_net microblaze_0_M_AXI_IC [get_bd_intf_pins axi_mem_intercon/S01_AXI] [get_bd_intf_pins microblaze_0/M_AXI_IC]\r
+  connect_bd_intf_net -intf_net microblaze_0_axi_periph_M00_AXI [get_bd_intf_pins axi_uartlite_0/S_AXI] [get_bd_intf_pins microblaze_0_axi_periph/M00_AXI]\r
+  connect_bd_intf_net -intf_net microblaze_0_axi_periph_M01_AXI [get_bd_intf_pins axi_gpio_0/S_AXI] [get_bd_intf_pins microblaze_0_axi_periph/M01_AXI]\r
+  connect_bd_intf_net -intf_net microblaze_0_axi_periph_M02_AXI [get_bd_intf_pins axi_timer_0/S_AXI] [get_bd_intf_pins microblaze_0_axi_periph/M02_AXI]\r
+  connect_bd_intf_net -intf_net microblaze_0_axi_periph_M03_AXI [get_bd_intf_pins axi_intc_0/s_axi] [get_bd_intf_pins microblaze_0_axi_periph/M03_AXI]\r
+  connect_bd_intf_net -intf_net microblaze_0_axi_periph_M04_AXI [get_bd_intf_pins axi_ethernetlite_0/S_AXI] [get_bd_intf_pins microblaze_0_axi_periph/M04_AXI]\r
+  connect_bd_intf_net -intf_net microblaze_0_debug [get_bd_intf_pins mdm_1/MBDEBUG_0] [get_bd_intf_pins microblaze_0/DEBUG]\r
+  connect_bd_intf_net -intf_net microblaze_0_dlmb_1 [get_bd_intf_pins microblaze_0/DLMB] [get_bd_intf_pins microblaze_0_local_memory/DLMB]\r
+  connect_bd_intf_net -intf_net microblaze_0_ilmb_1 [get_bd_intf_pins microblaze_0/ILMB] [get_bd_intf_pins microblaze_0_local_memory/ILMB]\r
+  connect_bd_intf_net -intf_net mig_7series_0_DDR3 [get_bd_intf_ports ddr3_sdram] [get_bd_intf_pins mig_7series_0/DDR3]\r
+\r
+  # Create port connections\r
+  connect_bd_net -net axi_ethernetlite_0_ip2intc_irpt [get_bd_pins axi_ethernetlite_0/ip2intc_irpt] [get_bd_pins xlconcat_0/In2]\r
+  connect_bd_net -net axi_timer_0_interrupt [get_bd_pins axi_timer_0/interrupt] [get_bd_pins xlconcat_0/In0]\r
+  connect_bd_net -net axi_uartlite_0_interrupt [get_bd_pins axi_uartlite_0/interrupt] [get_bd_pins xlconcat_0/In1]\r
+  connect_bd_net -net mdm_1_debug_sys_rst [get_bd_pins mdm_1/Debug_SYS_Rst] [get_bd_pins rst_clk_wiz_1_100M/mb_debug_sys_rst]\r
+  connect_bd_net -net microblaze_0_Clk [get_bd_pins axi_ethernetlite_0/s_axi_aclk] [get_bd_pins axi_gpio_0/s_axi_aclk] [get_bd_pins axi_intc_0/s_axi_aclk] [get_bd_pins axi_mem_intercon/ACLK] [get_bd_pins axi_mem_intercon/M00_ACLK] [get_bd_pins axi_mem_intercon/S00_ACLK] [get_bd_pins axi_mem_intercon/S01_ACLK] [get_bd_pins axi_timer_0/s_axi_aclk] [get_bd_pins axi_uartlite_0/s_axi_aclk] [get_bd_pins microblaze_0/Clk] [get_bd_pins microblaze_0_axi_periph/ACLK] [get_bd_pins microblaze_0_axi_periph/M00_ACLK] [get_bd_pins microblaze_0_axi_periph/M01_ACLK] [get_bd_pins microblaze_0_axi_periph/M02_ACLK] [get_bd_pins microblaze_0_axi_periph/M03_ACLK] [get_bd_pins microblaze_0_axi_periph/M04_ACLK] [get_bd_pins microblaze_0_axi_periph/S00_ACLK] [get_bd_pins microblaze_0_local_memory/LMB_Clk] [get_bd_pins mig_7series_0/ui_clk] [get_bd_pins rst_clk_wiz_1_100M/slowest_sync_clk]\r
+  connect_bd_net -net mig_7series_0_mmcm_locked [get_bd_pins mig_7series_0/mmcm_locked] [get_bd_pins rst_clk_wiz_1_100M/dcm_locked]\r
+  connect_bd_net -net mig_7series_0_ui_clk_sync_rst [get_bd_pins mig_7series_0/ui_clk_sync_rst] [get_bd_pins rst_clk_wiz_1_100M/ext_reset_in]\r
+  connect_bd_net -net reset_1 [get_bd_ports reset] [get_bd_pins mig_7series_0/sys_rst]\r
+  connect_bd_net -net rst_clk_wiz_1_100M_bus_struct_reset [get_bd_pins microblaze_0_local_memory/LMB_Rst] [get_bd_pins rst_clk_wiz_1_100M/bus_struct_reset]\r
+  connect_bd_net -net rst_clk_wiz_1_100M_interconnect_aresetn [get_bd_pins axi_mem_intercon/ARESETN] [get_bd_pins microblaze_0_axi_periph/ARESETN] [get_bd_pins rst_clk_wiz_1_100M/interconnect_aresetn]\r
+  connect_bd_net -net rst_clk_wiz_1_100M_mb_reset [get_bd_pins microblaze_0/Reset] [get_bd_pins rst_clk_wiz_1_100M/mb_reset]\r
+  connect_bd_net -net rst_clk_wiz_1_100M_peripheral_aresetn [get_bd_pins axi_ethernetlite_0/s_axi_aresetn] [get_bd_pins axi_gpio_0/s_axi_aresetn] [get_bd_pins axi_intc_0/s_axi_aresetn] [get_bd_pins axi_mem_intercon/M00_ARESETN] [get_bd_pins axi_mem_intercon/S00_ARESETN] [get_bd_pins axi_mem_intercon/S01_ARESETN] [get_bd_pins axi_timer_0/s_axi_aresetn] [get_bd_pins axi_uartlite_0/s_axi_aresetn] [get_bd_pins microblaze_0_axi_periph/M00_ARESETN] [get_bd_pins microblaze_0_axi_periph/M01_ARESETN] [get_bd_pins microblaze_0_axi_periph/M02_ARESETN] [get_bd_pins microblaze_0_axi_periph/M03_ARESETN] [get_bd_pins microblaze_0_axi_periph/M04_ARESETN] [get_bd_pins microblaze_0_axi_periph/S00_ARESETN] [get_bd_pins mig_7series_0/aresetn] [get_bd_pins rst_clk_wiz_1_100M/peripheral_aresetn]\r
+  connect_bd_net -net xlconcat_0_dout [get_bd_pins axi_intc_0/intr] [get_bd_pins xlconcat_0/dout]\r
+\r
+  # Create address segments\r
+  create_bd_addr_seg -range 0x10000 -offset 0x40E00000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs axi_ethernetlite_0/S_AXI/Reg] SEG_axi_ethernetlite_0_Reg\r
+  create_bd_addr_seg -range 0x10000 -offset 0x40000000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs axi_gpio_0/S_AXI/Reg] SEG_axi_gpio_0_Reg\r
+  create_bd_addr_seg -range 0x10000 -offset 0x41200000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs axi_intc_0/s_axi/Reg] SEG_axi_intc_0_Reg\r
+  create_bd_addr_seg -range 0x10000 -offset 0x41C00000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs axi_timer_0/S_AXI/Reg] SEG_axi_timer_0_Reg\r
+  create_bd_addr_seg -range 0x10000 -offset 0x40600000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs axi_uartlite_0/S_AXI/Reg] SEG_axi_uartlite_0_Reg\r
+  create_bd_addr_seg -range 0x40000 -offset 0x0 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs microblaze_0_local_memory/dlmb_bram_if_cntlr/SLMB/Mem] SEG_dlmb_bram_if_cntlr_Mem\r
+  create_bd_addr_seg -range 0x40000 -offset 0x0 [get_bd_addr_spaces microblaze_0/Instruction] [get_bd_addr_segs microblaze_0_local_memory/ilmb_bram_if_cntlr/SLMB/Mem] SEG_ilmb_bram_if_cntlr_Mem\r
+  create_bd_addr_seg -range 0x40000000 -offset 0x80000000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs mig_7series_0/memmap/memaddr] SEG_mig_7series_0_memaddr\r
+  create_bd_addr_seg -range 0x40000000 -offset 0x80000000 [get_bd_addr_spaces microblaze_0/Instruction] [get_bd_addr_segs mig_7series_0/memmap/memaddr] SEG_mig_7series_0_memaddr\r
+  \r
+\r
+  # Restore current instance\r
+  current_bd_instance $oldCurInst\r
+\r
+  save_bd_design\r
+}\r
+# End of create_root_design()\r
+\r
+\r
+##################################################################\r
+# MAIN FLOW\r
+##################################################################\r
+\r
+create_root_design ""\r
+\r
+\r
diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/Hardware/base_microblaze_design_wrapper.bit b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/Hardware/base_microblaze_design_wrapper.bit
new file mode 100644 (file)
index 0000000..6fdb600
Binary files /dev/null and b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/Hardware/base_microblaze_design_wrapper.bit differ
diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/Hardware/base_microblaze_design_wrapper.mmi b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/Hardware/base_microblaze_design_wrapper.mmi
new file mode 100644 (file)
index 0000000..40c93ef
--- /dev/null
+++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/Hardware/base_microblaze_design_wrapper.mmi
@@ -0,0 +1,334 @@
+<?xml version="1.0" encoding="UTF-8"?>\r
+<MemInfo Version="1" Minor="0">\r
+  <Processor Endianness="Little" InstPath="base_microblaze_design_i/microblaze_0">\r
+    <AddressSpace Name="base_microblaze_design_i_microblaze_0.base_microblaze_design_i_microblaze_0_local_memory_dlmb_bram_if_cntlr" Begin="0" End="262143">\r
+      <BusBlock>\r
+        <BitLane MemType="RAMB32" Placement="X1Y4">\r
+          <DataWidth MSB="7" LSB="7"/>\r
+          <AddressRange Begin="0" End="32767"/>\r
+          <Parity ON="false" NumBits="0"/>\r
+        </BitLane>\r
+        <BitLane MemType="RAMB32" Placement="X1Y8">\r
+          <DataWidth MSB="6" LSB="6"/>\r
+          <AddressRange Begin="0" End="32767"/>\r
+          <Parity ON="false" NumBits="0"/>\r
+        </BitLane>\r
+        <BitLane MemType="RAMB32" Placement="X0Y8">\r
+          <DataWidth MSB="5" LSB="5"/>\r
+          <AddressRange Begin="0" End="32767"/>\r
+          <Parity ON="false" NumBits="0"/>\r
+        </BitLane>\r
+        <BitLane MemType="RAMB32" Placement="X4Y0">\r
+          <DataWidth MSB="4" LSB="4"/>\r
+          <AddressRange Begin="0" End="32767"/>\r
+          <Parity ON="false" NumBits="0"/>\r
+        </BitLane>\r
+        <BitLane MemType="RAMB32" Placement="X1Y12">\r
+          <DataWidth MSB="3" LSB="3"/>\r
+          <AddressRange Begin="0" End="32767"/>\r
+          <Parity ON="false" NumBits="0"/>\r
+        </BitLane>\r
+        <BitLane MemType="RAMB32" Placement="X2Y5">\r
+          <DataWidth MSB="2" LSB="2"/>\r
+          <AddressRange Begin="0" End="32767"/>\r
+          <Parity ON="false" NumBits="0"/>\r
+        </BitLane>\r
+        <BitLane MemType="RAMB32" Placement="X3Y17">\r
+          <DataWidth MSB="1" LSB="1"/>\r
+          <AddressRange Begin="0" End="32767"/>\r
+          <Parity ON="false" NumBits="0"/>\r
+        </BitLane>\r
+        <BitLane MemType="RAMB32" Placement="X3Y6">\r
+          <DataWidth MSB="0" LSB="0"/>\r
+          <AddressRange Begin="0" End="32767"/>\r
+          <Parity ON="false" NumBits="0"/>\r
+        </BitLane>\r
+        <BitLane MemType="RAMB32" Placement="X2Y1">\r
+          <DataWidth MSB="15" LSB="15"/>\r
+          <AddressRange Begin="0" End="32767"/>\r
+          <Parity ON="false" NumBits="0"/>\r
+        </BitLane>\r
+        <BitLane MemType="RAMB32" Placement="X2Y3">\r
+          <DataWidth MSB="14" LSB="14"/>\r
+          <AddressRange Begin="0" End="32767"/>\r
+          <Parity ON="false" NumBits="0"/>\r
+        </BitLane>\r
+        <BitLane MemType="RAMB32" Placement="X6Y7">\r
+          <DataWidth MSB="13" LSB="13"/>\r
+          <AddressRange Begin="0" End="32767"/>\r
+          <Parity ON="false" NumBits="0"/>\r
+        </BitLane>\r
+        <BitLane MemType="RAMB32" Placement="X5Y2">\r
+          <DataWidth MSB="12" LSB="12"/>\r
+          <AddressRange Begin="0" End="32767"/>\r
+          <Parity ON="false" NumBits="0"/>\r
+        </BitLane>\r
+        <BitLane MemType="RAMB32" Placement="X2Y13">\r
+          <DataWidth MSB="11" LSB="11"/>\r
+          <AddressRange Begin="0" End="32767"/>\r
+          <Parity ON="false" NumBits="0"/>\r
+        </BitLane>\r
+        <BitLane MemType="RAMB32" Placement="X4Y13">\r
+          <DataWidth MSB="10" LSB="10"/>\r
+          <AddressRange Begin="0" End="32767"/>\r
+          <Parity ON="false" NumBits="0"/>\r
+        </BitLane>\r
+        <BitLane MemType="RAMB32" Placement="X5Y0">\r
+          <DataWidth MSB="9" LSB="9"/>\r
+          <AddressRange Begin="0" End="32767"/>\r
+          <Parity ON="false" NumBits="0"/>\r
+        </BitLane>\r
+        <BitLane MemType="RAMB32" Placement="X4Y2">\r
+          <DataWidth MSB="8" LSB="8"/>\r
+          <AddressRange Begin="0" End="32767"/>\r
+          <Parity ON="false" NumBits="0"/>\r
+        </BitLane>\r
+        <BitLane MemType="RAMB32" Placement="X5Y8">\r
+          <DataWidth MSB="23" LSB="23"/>\r
+          <AddressRange Begin="0" End="32767"/>\r
+          <Parity ON="false" NumBits="0"/>\r
+        </BitLane>\r
+        <BitLane MemType="RAMB32" Placement="X2Y7">\r
+          <DataWidth MSB="22" LSB="22"/>\r
+          <AddressRange Begin="0" End="32767"/>\r
+          <Parity ON="false" NumBits="0"/>\r
+        </BitLane>\r
+        <BitLane MemType="RAMB32" Placement="X1Y10">\r
+          <DataWidth MSB="21" LSB="21"/>\r
+          <AddressRange Begin="0" End="32767"/>\r
+          <Parity ON="false" NumBits="0"/>\r
+        </BitLane>\r
+        <BitLane MemType="RAMB32" Placement="X4Y7">\r
+          <DataWidth MSB="20" LSB="20"/>\r
+          <AddressRange Begin="0" End="32767"/>\r
+          <Parity ON="false" NumBits="0"/>\r
+        </BitLane>\r
+        <BitLane MemType="RAMB32" Placement="X2Y11">\r
+          <DataWidth MSB="19" LSB="19"/>\r
+          <AddressRange Begin="0" End="32767"/>\r
+          <Parity ON="false" NumBits="0"/>\r
+        </BitLane>\r
+        <BitLane MemType="RAMB32" Placement="X3Y0">\r
+          <DataWidth MSB="18" LSB="18"/>\r
+          <AddressRange Begin="0" End="32767"/>\r
+          <Parity ON="false" NumBits="0"/>\r
+        </BitLane>\r
+        <BitLane MemType="RAMB32" Placement="X6Y11">\r
+          <DataWidth MSB="17" LSB="17"/>\r
+          <AddressRange Begin="0" End="32767"/>\r
+          <Parity ON="false" NumBits="0"/>\r
+        </BitLane>\r
+        <BitLane MemType="RAMB32" Placement="X3Y2">\r
+          <DataWidth MSB="16" LSB="16"/>\r
+          <AddressRange Begin="0" End="32767"/>\r
+          <Parity ON="false" NumBits="0"/>\r
+        </BitLane>\r
+        <BitLane MemType="RAMB32" Placement="X1Y6">\r
+          <DataWidth MSB="31" LSB="31"/>\r
+          <AddressRange Begin="0" End="32767"/>\r
+          <Parity ON="false" NumBits="0"/>\r
+        </BitLane>\r
+        <BitLane MemType="RAMB32" Placement="X2Y9">\r
+          <DataWidth MSB="30" LSB="30"/>\r
+          <AddressRange Begin="0" End="32767"/>\r
+          <Parity ON="false" NumBits="0"/>\r
+        </BitLane>\r
+        <BitLane MemType="RAMB32" Placement="X4Y15">\r
+          <DataWidth MSB="29" LSB="29"/>\r
+          <AddressRange Begin="0" End="32767"/>\r
+          <Parity ON="false" NumBits="0"/>\r
+        </BitLane>\r
+        <BitLane MemType="RAMB32" Placement="X6Y3">\r
+          <DataWidth MSB="28" LSB="28"/>\r
+          <AddressRange Begin="0" End="32767"/>\r
+          <Parity ON="false" NumBits="0"/>\r
+        </BitLane>\r
+        <BitLane MemType="RAMB32" Placement="X3Y15">\r
+          <DataWidth MSB="27" LSB="27"/>\r
+          <AddressRange Begin="0" End="32767"/>\r
+          <Parity ON="false" NumBits="0"/>\r
+        </BitLane>\r
+        <BitLane MemType="RAMB32" Placement="X5Y13">\r
+          <DataWidth MSB="26" LSB="26"/>\r
+          <AddressRange Begin="0" End="32767"/>\r
+          <Parity ON="false" NumBits="0"/>\r
+        </BitLane>\r
+        <BitLane MemType="RAMB32" Placement="X6Y9">\r
+          <DataWidth MSB="25" LSB="25"/>\r
+          <AddressRange Begin="0" End="32767"/>\r
+          <Parity ON="false" NumBits="0"/>\r
+        </BitLane>\r
+        <BitLane MemType="RAMB32" Placement="X6Y5">\r
+          <DataWidth MSB="24" LSB="24"/>\r
+          <AddressRange Begin="0" End="32767"/>\r
+          <Parity ON="false" NumBits="0"/>\r
+        </BitLane>\r
+      </BusBlock>\r
+      <BusBlock>\r
+        <BitLane MemType="RAMB32" Placement="X1Y5">\r
+          <DataWidth MSB="7" LSB="7"/>\r
+          <AddressRange Begin="32768" End="65535"/>\r
+          <Parity ON="false" NumBits="0"/>\r
+        </BitLane>\r
+        <BitLane MemType="RAMB32" Placement="X1Y9">\r
+          <DataWidth MSB="6" LSB="6"/>\r
+          <AddressRange Begin="32768" End="65535"/>\r
+          <Parity ON="false" NumBits="0"/>\r
+        </BitLane>\r
+        <BitLane MemType="RAMB32" Placement="X0Y9">\r
+          <DataWidth MSB="5" LSB="5"/>\r
+          <AddressRange Begin="32768" End="65535"/>\r
+          <Parity ON="false" NumBits="0"/>\r
+        </BitLane>\r
+        <BitLane MemType="RAMB32" Placement="X4Y1">\r
+          <DataWidth MSB="4" LSB="4"/>\r
+          <AddressRange Begin="32768" End="65535"/>\r
+          <Parity ON="false" NumBits="0"/>\r
+        </BitLane>\r
+        <BitLane MemType="RAMB32" Placement="X1Y13">\r
+          <DataWidth MSB="3" LSB="3"/>\r
+          <AddressRange Begin="32768" End="65535"/>\r
+          <Parity ON="false" NumBits="0"/>\r
+        </BitLane>\r
+        <BitLane MemType="RAMB32" Placement="X2Y6">\r
+          <DataWidth MSB="2" LSB="2"/>\r
+          <AddressRange Begin="32768" End="65535"/>\r
+          <Parity ON="false" NumBits="0"/>\r
+        </BitLane>\r
+        <BitLane MemType="RAMB32" Placement="X3Y18">\r
+          <DataWidth MSB="1" LSB="1"/>\r
+          <AddressRange Begin="32768" End="65535"/>\r
+          <Parity ON="false" NumBits="0"/>\r
+        </BitLane>\r
+        <BitLane MemType="RAMB32" Placement="X3Y7">\r
+          <DataWidth MSB="0" LSB="0"/>\r
+          <AddressRange Begin="32768" End="65535"/>\r
+          <Parity ON="false" NumBits="0"/>\r
+        </BitLane>\r
+        <BitLane MemType="RAMB32" Placement="X2Y2">\r
+          <DataWidth MSB="15" LSB="15"/>\r
+          <AddressRange Begin="32768" End="65535"/>\r
+          <Parity ON="false" NumBits="0"/>\r
+        </BitLane>\r
+        <BitLane MemType="RAMB32" Placement="X2Y4">\r
+          <DataWidth MSB="14" LSB="14"/>\r
+          <AddressRange Begin="32768" End="65535"/>\r
+          <Parity ON="false" NumBits="0"/>\r
+        </BitLane>\r
+        <BitLane MemType="RAMB32" Placement="X6Y8">\r
+          <DataWidth MSB="13" LSB="13"/>\r
+          <AddressRange Begin="32768" End="65535"/>\r
+          <Parity ON="false" NumBits="0"/>\r
+        </BitLane>\r
+        <BitLane MemType="RAMB32" Placement="X5Y3">\r
+          <DataWidth MSB="12" LSB="12"/>\r
+          <AddressRange Begin="32768" End="65535"/>\r
+          <Parity ON="false" NumBits="0"/>\r
+        </BitLane>\r
+        <BitLane MemType="RAMB32" Placement="X2Y14">\r
+          <DataWidth MSB="11" LSB="11"/>\r
+          <AddressRange Begin="32768" End="65535"/>\r
+          <Parity ON="false" NumBits="0"/>\r
+        </BitLane>\r
+        <BitLane MemType="RAMB32" Placement="X4Y14">\r
+          <DataWidth MSB="10" LSB="10"/>\r
+          <AddressRange Begin="32768" End="65535"/>\r
+          <Parity ON="false" NumBits="0"/>\r
+        </BitLane>\r
+        <BitLane MemType="RAMB32" Placement="X5Y1">\r
+          <DataWidth MSB="9" LSB="9"/>\r
+          <AddressRange Begin="32768" End="65535"/>\r
+          <Parity ON="false" NumBits="0"/>\r
+        </BitLane>\r
+        <BitLane MemType="RAMB32" Placement="X4Y3">\r
+          <DataWidth MSB="8" LSB="8"/>\r
+          <AddressRange Begin="32768" End="65535"/>\r
+          <Parity ON="false" NumBits="0"/>\r
+        </BitLane>\r
+        <BitLane MemType="RAMB32" Placement="X5Y9">\r
+          <DataWidth MSB="23" LSB="23"/>\r
+          <AddressRange Begin="32768" End="65535"/>\r
+          <Parity ON="false" NumBits="0"/>\r
+        </BitLane>\r
+        <BitLane MemType="RAMB32" Placement="X2Y8">\r
+          <DataWidth MSB="22" LSB="22"/>\r
+          <AddressRange Begin="32768" End="65535"/>\r
+          <Parity ON="false" NumBits="0"/>\r
+        </BitLane>\r
+        <BitLane MemType="RAMB32" Placement="X1Y11">\r
+          <DataWidth MSB="21" LSB="21"/>\r
+          <AddressRange Begin="32768" End="65535"/>\r
+          <Parity ON="false" NumBits="0"/>\r
+        </BitLane>\r
+        <BitLane MemType="RAMB32" Placement="X4Y8">\r
+          <DataWidth MSB="20" LSB="20"/>\r
+          <AddressRange Begin="32768" End="65535"/>\r
+          <Parity ON="false" NumBits="0"/>\r
+        </BitLane>\r
+        <BitLane MemType="RAMB32" Placement="X2Y12">\r
+          <DataWidth MSB="19" LSB="19"/>\r
+          <AddressRange Begin="32768" End="65535"/>\r
+          <Parity ON="false" NumBits="0"/>\r
+        </BitLane>\r
+        <BitLane MemType="RAMB32" Placement="X3Y1">\r
+          <DataWidth MSB="18" LSB="18"/>\r
+          <AddressRange Begin="32768" End="65535"/>\r
+          <Parity ON="false" NumBits="0"/>\r
+        </BitLane>\r
+        <BitLane MemType="RAMB32" Placement="X6Y12">\r
+          <DataWidth MSB="17" LSB="17"/>\r
+          <AddressRange Begin="32768" End="65535"/>\r
+          <Parity ON="false" NumBits="0"/>\r
+        </BitLane>\r
+        <BitLane MemType="RAMB32" Placement="X3Y3">\r
+          <DataWidth MSB="16" LSB="16"/>\r
+          <AddressRange Begin="32768" End="65535"/>\r
+          <Parity ON="false" NumBits="0"/>\r
+        </BitLane>\r
+        <BitLane MemType="RAMB32" Placement="X1Y7">\r
+          <DataWidth MSB="31" LSB="31"/>\r
+          <AddressRange Begin="32768" End="65535"/>\r
+          <Parity ON="false" NumBits="0"/>\r
+        </BitLane>\r
+        <BitLane MemType="RAMB32" Placement="X2Y10">\r
+          <DataWidth MSB="30" LSB="30"/>\r
+          <AddressRange Begin="32768" End="65535"/>\r
+          <Parity ON="false" NumBits="0"/>\r
+        </BitLane>\r
+        <BitLane MemType="RAMB32" Placement="X4Y16">\r
+          <DataWidth MSB="29" LSB="29"/>\r
+          <AddressRange Begin="32768" End="65535"/>\r
+          <Parity ON="false" NumBits="0"/>\r
+        </BitLane>\r
+        <BitLane MemType="RAMB32" Placement="X6Y4">\r
+          <DataWidth MSB="28" LSB="28"/>\r
+          <AddressRange Begin="32768" End="65535"/>\r
+          <Parity ON="false" NumBits="0"/>\r
+        </BitLane>\r
+        <BitLane MemType="RAMB32" Placement="X3Y16">\r
+          <DataWidth MSB="27" LSB="27"/>\r
+          <AddressRange Begin="32768" End="65535"/>\r
+          <Parity ON="false" NumBits="0"/>\r
+        </BitLane>\r
+        <BitLane MemType="RAMB32" Placement="X5Y14">\r
+          <DataWidth MSB="26" LSB="26"/>\r
+          <AddressRange Begin="32768" End="65535"/>\r
+          <Parity ON="false" NumBits="0"/>\r
+        </BitLane>\r
+        <BitLane MemType="RAMB32" Placement="X6Y10">\r
+          <DataWidth MSB="25" LSB="25"/>\r
+          <AddressRange Begin="32768" End="65535"/>\r
+          <Parity ON="false" NumBits="0"/>\r
+        </BitLane>\r
+        <BitLane MemType="RAMB32" Placement="X6Y6">\r
+          <DataWidth MSB="24" LSB="24"/>\r
+          <AddressRange Begin="32768" End="65535"/>\r
+          <Parity ON="false" NumBits="0"/>\r
+        </BitLane>\r
+      </BusBlock>\r
+    </AddressSpace>\r
+  </Processor>\r
+  <Config>\r
+    <Option Name="Part" Val="xc7k325tffg900-2"/>\r
+  </Config>\r
+</MemInfo>\r
diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/Hardware/sysdef.xml b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/Hardware/sysdef.xml
new file mode 100644 (file)
index 0000000..6e97db5
--- /dev/null
+++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/Hardware/sysdef.xml
@@ -0,0 +1,14 @@
+<?xml version="1.0"?>\r
+<Project Version="1" Minor="0">\r
+       <BUILD_NUMBER Name="1071353"/>\r
+       <FULL_BUILD Name="SW Build 1071353 on Tue Nov 18 18:29:27 MST 2014"/>\r
+       <MODE Name="Post-Bitstream"/>\r
+       <SYSTEMINFO BOARD="xilinx.com:kc705:part0:1.1" ARCH="kintex7" PACKAGE="ffg900" DEVICE="7k325t" SPEED="-2" LUT="" FF="" BRAM="" DSP=""/>\r
+       <HIERARCHY Name="base_microblaze_design_i"/>\r
+       <File Type="HW_HANDOFF" Name="base_microblaze_design.hwh" ModTime="1421754940"/>\r
+       <File Type="BIT" Name="base_microblaze_design_wrapper.bit" ModTime="1421759776"/>\r
+       <File Type="BMM" Name="base_microblaze_design_wrapper.mmi" ModTime="1421759676"/>\r
+       <File Type="BD_TCL" Name="base_microblaze_design_bd.tcl" ModTime="1421754940"/>\r
+       <USEDRESOURCES LUT="" FF="" BRAM="" DSP=""/>\r
+</Project>\r
+\r
diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/Hardware/system.hdf b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/Hardware/system.hdf
new file mode 100644 (file)
index 0000000..d508b5e
Binary files /dev/null and b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/Hardware/system.hdf differ
diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/.project b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/.project
index 3dbb5fb213948c1334712a37b205f682a1d5b9a0..75b22006973a68325e886e5b7495cbb72a9fa9f2 100644 (file)
--- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/.project
+++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/.project
@@ -115,7 +115,7 @@
                        </matcher>\r
                </filter>\r
                <filter>\r
-                       <id>1421425118832</id>\r
+                       <id>1426001044021</id>\r
                        <name>src/Full_Demo/Common_Demo_Source/Minimal</name>\r
                        <type>5</type>\r
                        <matcher>\r
@@ -124,7 +124,7 @@
                        </matcher>\r
                </filter>\r
                <filter>\r
-                       <id>1421425118842</id>\r
+                       <id>1426001044028</id>\r
                        <name>src/Full_Demo/Common_Demo_Source/Minimal</name>\r
                        <type>5</type>\r
                        <matcher>\r
@@ -133,7 +133,7 @@
                        </matcher>\r
                </filter>\r
                <filter>\r
-                       <id>1421425118842</id>\r
+                       <id>1426001044037</id>\r
                        <name>src/Full_Demo/Common_Demo_Source/Minimal</name>\r
                        <type>5</type>\r
                        <matcher>\r
@@ -142,7 +142,7 @@
                        </matcher>\r
                </filter>\r
                <filter>\r
-                       <id>1421425118852</id>\r
+                       <id>1426001044046</id>\r
                        <name>src/Full_Demo/Common_Demo_Source/Minimal</name>\r
                        <type>5</type>\r
                        <matcher>\r
@@ -151,7 +151,7 @@
                        </matcher>\r
                </filter>\r
                <filter>\r
-                       <id>1421425118852</id>\r
+                       <id>1426001044057</id>\r
                        <name>src/Full_Demo/Common_Demo_Source/Minimal</name>\r
                        <type>5</type>\r
                        <matcher>\r
@@ -160,7 +160,7 @@
                        </matcher>\r
                </filter>\r
                <filter>\r
-                       <id>1421425118852</id>\r
+                       <id>1426001044063</id>\r
                        <name>src/Full_Demo/Common_Demo_Source/Minimal</name>\r
                        <type>5</type>\r
                        <matcher>\r
@@ -169,7 +169,7 @@
                        </matcher>\r
                </filter>\r
                <filter>\r
-                       <id>1421425118862</id>\r
+                       <id>1426001044071</id>\r
                        <name>src/Full_Demo/Common_Demo_Source/Minimal</name>\r
                        <type>5</type>\r
                        <matcher>\r
@@ -178,7 +178,7 @@
                        </matcher>\r
                </filter>\r
                <filter>\r
-                       <id>1421425118872</id>\r
+                       <id>1426001044076</id>\r
                        <name>src/Full_Demo/Common_Demo_Source/Minimal</name>\r
                        <type>5</type>\r
                        <matcher>\r
@@ -187,7 +187,7 @@
                        </matcher>\r
                </filter>\r
                <filter>\r
-                       <id>1421425118872</id>\r
+                       <id>1426001044081</id>\r
                        <name>src/Full_Demo/Common_Demo_Source/Minimal</name>\r
                        <type>5</type>\r
                        <matcher>\r
@@ -196,7 +196,7 @@
                        </matcher>\r
                </filter>\r
                <filter>\r
-                       <id>1421425118872</id>\r
+                       <id>1426001044088</id>\r
                        <name>src/Full_Demo/Common_Demo_Source/Minimal</name>\r
                        <type>5</type>\r
                        <matcher>\r
@@ -205,7 +205,7 @@
                        </matcher>\r
                </filter>\r
                <filter>\r
-                       <id>1421425118882</id>\r
+                       <id>1426001044094</id>\r
                        <name>src/Full_Demo/Common_Demo_Source/Minimal</name>\r
                        <type>5</type>\r
                        <matcher>\r
@@ -214,7 +214,7 @@
                        </matcher>\r
                </filter>\r
                <filter>\r
-                       <id>1421425118882</id>\r
+                       <id>1426001044098</id>\r
                        <name>src/Full_Demo/Common_Demo_Source/Minimal</name>\r
                        <type>5</type>\r
                        <matcher>\r
@@ -223,7 +223,7 @@
                        </matcher>\r
                </filter>\r
                <filter>\r
-                       <id>1421425118892</id>\r
+                       <id>1426001044103</id>\r
                        <name>src/Full_Demo/Common_Demo_Source/Minimal</name>\r
                        <type>5</type>\r
                        <matcher>\r
@@ -232,7 +232,7 @@
                        </matcher>\r
                </filter>\r
                <filter>\r
-                       <id>1421425118892</id>\r
+                       <id>1426001044107</id>\r
                        <name>src/Full_Demo/Common_Demo_Source/Minimal</name>\r
                        <type>5</type>\r
                        <matcher>\r
diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/src/Full_Demo/main_full.c b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/src/Full_Demo/main_full.c
index e1b15a5d021efb380c8575301c1d7113e5d77650..af5550ac99ab5e7dce7ad88077317f4d84987b1b 100644 (file)
--- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/src/Full_Demo/main_full.c
+++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/src/Full_Demo/main_full.c
@@ -137,7 +137,6 @@
 #include "partest.h"\r
 #include "serial.h"\r
 #include "TimerDemo.h"\r
-#include "IntQueue.h"\r
 #include "EventGroupsDemo.h"\r
 #include "TaskNotify.h"\r
 #include "IntSemTest.h"\r
@@ -242,8 +241,6 @@ void main_full( void )
        /* Start all the other standard demo/test tasks.  They have not particular\r
        functionality, but do demonstrate how to use the FreeRTOS API and test the\r
        kernel port. */\r
-//     vStartInterruptQueueTasks();\r
-\r
        vStartDynamicPriorityTasks();\r
        vCreateBlockTimeTasks();\r
        vStartCountingSemaphoreTasks();\r
@@ -321,11 +318,6 @@ unsigned long ulErrorFound = pdFALSE;
 \r
                /* Check all the demo tasks (other than the flash tasks) to ensure\r
                that they are all still running, and that none have detected an error. */\r
-if( 0 )//              if( xAreIntQueueTasksStillRunning() != pdTRUE )\r
-               {\r
-                       ulErrorFound |= 1UL << 0UL;\r
-               }\r
-\r
                if( xAreMathsTaskStillRunning() != pdTRUE )\r
                {\r
                        ulErrorFound |= 1UL << 1UL;\r
@@ -356,6 +348,11 @@ if( 0 )//          if( xAreIntQueueTasksStillRunning() != pdTRUE )
                        ulErrorFound |= 1UL << 8UL;\r
                }\r
 \r
+               if( xAreTimerDemoTasksStillRunning( ( TickType_t ) mainNO_ERROR_CHECK_TASK_PERIOD ) != pdPASS )\r
+               {\r
+                       ulErrorFound |= 1UL << 9UL;\r
+               }\r
+\r
                if( xAreCountingSemaphoreTasksStillRunning() != pdTRUE )\r
                {\r
                        ulErrorFound |= 1UL << 10UL;\r
@@ -366,11 +363,6 @@ if( 0 )//          if( xAreIntQueueTasksStillRunning() != pdTRUE )
                        ulErrorFound |= 1UL << 14UL;\r
                }\r
 \r
-               if( xAreTimerDemoTasksStillRunning( ( TickType_t ) mainNO_ERROR_CHECK_TASK_PERIOD ) != pdPASS )\r
-               {\r
-                       ulErrorFound |= 1UL << 9UL;\r
-               }\r
-\r
                if( xAreEventGroupTasksStillRunning() != pdPASS )\r
                {\r
                        ulErrorFound |= 1UL << 12UL;\r
diff --git a/FreeRTOS/Source/include/projdefs.h b/FreeRTOS/Source/include/projdefs.h
index e8198b354af80d520c375049761cb7d0f2618b49..db30b34be4dd6e9ff508c275a4468324bbe16e64 100644 (file)
--- a/FreeRTOS/Source/include/projdefs.h
+++ b/FreeRTOS/Source/include/projdefs.h
@@ -77,7 +77,7 @@
 typedef void (*TaskFunction_t)( void * );\r
 \r
 /* Converts a time in milliseconds to a time in ticks. */\r
-#define pdMS_TO_TICKS( xTimeInMs ) ( ( ( TickType_t ) ( xTimeInMs ) * configTICK_RATE_HZ ) / ( TickType_t ) 1000 )\r
+#define pdMS_TO_TICKS( xTimeInMs ) ( ( TickType_t ) ( ( ( TickType_t ) ( xTimeInMs ) * ( TickType_t ) configTICK_RATE_HZ ) / ( TickType_t ) 1000 ) )\r
 \r
 #define pdFALSE                        ( ( BaseType_t ) 0 )\r
 #define pdTRUE                 ( ( BaseType_t ) 1 )\r
diff --git a/FreeRTOS/Source/portable/RVDS/ARM_CM4F/port.c b/FreeRTOS/Source/portable/RVDS/ARM_CM4F/port.c
index 543aa00dda43d7dfd6058e0e95800934078426ec..f47e9ca26f00ff39a8aa4aff4953d193d6118350 100644 (file)
--- a/FreeRTOS/Source/portable/RVDS/ARM_CM4F/port.c
+++ b/FreeRTOS/Source/portable/RVDS/ARM_CM4F/port.c
@@ -489,7 +489,6 @@ __asm void xPortPendSVHandler( void )
        #endif\r
 \r
        bx r14\r
-       nop\r
 }\r
 /*-----------------------------------------------------------*/\r
 \r
diff --git a/FreeRTOS/Source/queue.c b/FreeRTOS/Source/queue.c
index b26f6dac7638c49a1f2069457fb3a4222a545783..c552e660502a2f2b3dd833ce01ef51efe170a18c 100644 (file)
--- a/FreeRTOS/Source/queue.c
+++ b/FreeRTOS/Source/queue.c
@@ -340,7 +340,7 @@ int8_t *pcAllocatedBuffer;
 \r
        if( pcAllocatedBuffer != NULL )\r
        {\r
-               pxNewQueue = ( Queue_t * ) pcAllocatedBuffer; /*lint !e826 MISRA The buffer cannot be to small because it was dimensioned by sizeof( Queue_t ) + xQueueSizeInBytes. */\r
+               pxNewQueue = ( Queue_t * ) pcAllocatedBuffer; /*lint !e826 MISRA The buffer cannot be too small because it was dimensioned by sizeof( Queue_t ) + xQueueSizeInBytes. */\r
 \r
                if( uxItemSize == ( UBaseType_t ) 0 )\r
                {\r
FreeRTOS imported from SF.net SVN