Microblaze port: Place critical section around XIntc_Enable() to protect read/modify...

git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2528 1d2547de-c912-0410-9cb9-b8ca96c0e9e2

diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/src/serial.c b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/src/serial.c
index 3d96be5a5f28d99f479a41722e6a0fe5ec2e617f..90ffe0fe961bd96ec9e10a064e84de7223474c57 100644 (file)
--- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/src/serial.c
+++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/src/serial.c
@@ -210,7 +210,7 @@ portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE;
 \r
 static void prvTxHandler( void *pvUnused, unsigned portBASE_TYPE uxUnused )\r
 {\r
-BaseType_t xHigherPriorityTaskWoken = NULL;\r
+BaseType_t xHigherPriorityTaskWoken = ( BaseType_t ) NULL;\r
 \r
        ( void ) pvUnused;\r
        ( void ) uxUnused;\r

diff --git a/FreeRTOS/Source/portable/GCC/MicroBlazeV9/port.c b/FreeRTOS/Source/portable/GCC/MicroBlazeV9/port.c
index 0460e46d297304cbc18e295680ee388a8d3c8f5d..f30b9e45748816f56d8c326674496580d7aa0df0 100644 (file)
--- a/FreeRTOS/Source/portable/GCC/MicroBlazeV9/port.c
+++ b/FreeRTOS/Source/portable/GCC/MicroBlazeV9/port.c
@@ -47,7 +47,7 @@ the scheduler being commenced interrupts should not be enabled, so the critical
 nesting variable is initialised to a non-zero value. */\r
 #define portINITIAL_NESTING_VALUE      ( 0xff )\r
 \r
-/* The bit within the MSR register that enabled/disables interrupts and \r
+/* The bit within the MSR register that enabled/disables interrupts and\r
 exceptions respectively. */\r
 #define portMSR_IE                                     ( 0x02U )\r
 #define portMSR_EE                                     ( 0x100U )\r
@@ -131,7 +131,7 @@ extern void _start1( void );
        disabled.  Each task will enable interrupts automatically when it enters\r
        the running state for the first time. */\r
        *pxTopOfStack = mfmsr() & ~portMSR_IE;\r
-       \r
+\r
        #if( MICROBLAZE_EXCEPTIONS_ENABLED == 1 )\r
        {\r
                /* Ensure exceptions are enabled for the task. */\r
@@ -305,7 +305,13 @@ int32_t lReturn;
        lReturn = prvEnsureInterruptControllerIsInitialised();\r
        if( lReturn == pdPASS )\r
        {\r
-               XIntc_Enable( &xInterruptControllerInstance, ucInterruptID );\r
+               /* Critical section protects read/modify/writer operation inside\r
+               XIntc_Enable(). */\r
+               portENTER_CRITICAL();\r
+               {\r
+                       XIntc_Enable( &xInterruptControllerInstance, ucInterruptID );\r
+               }\r
+               portEXIT_CRITICAL();\r
        }\r
 \r
        configASSERT( lReturn );\r