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Work in progress.
authorrichardbarry <richardbarry@1d2547de-c912-0410-9cb9-b8ca96c0e9e2>
Thu, 14 Jan 2010 12:24:29 +0000 (12:24 +0000)
committerrichardbarry <richardbarry@1d2547de-c912-0410-9cb9-b8ca96c0e9e2>
Thu, 14 Jan 2010 12:24:29 +0000 (12:24 +0000)
git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@955 1d2547de-c912-0410-9cb9-b8ca96c0e9e2

Demo/SuperH_SH7216_Renesas/RTOSDemo.tws patch | blob | history
Demo/SuperH_SH7216_Renesas/RTOSDemo/RTOSDemo.hwp patch | blob | history
Demo/SuperH_SH7216_Renesas/RTOSDemo/RTOSDemo.nav patch | blob | history
Demo/SuperH_SH7216_Renesas/RTOSDemo/RTOSDemo.tps patch | blob | history
Demo/SuperH_SH7216_Renesas/RTOSDemo/SessionSH7216_E10A-USB_SYSTEM__SH.hsf patch | blob | history
Demo/SuperH_SH7216_Renesas/RTOSDemo/intprg.c patch | blob | history
Demo/SuperH_SH7216_Renesas/RTOSDemo/main.c patch | blob | history
Demo/SuperH_SH7216_Renesas/RTOSDemo/regtest.src [new file with mode: 0644] patch | blob
Demo/SuperH_SH7216_Renesas/RTOSDemo/vecttbl.c patch | blob | history

diff --git a/Demo/SuperH_SH7216_Renesas/RTOSDemo.tws b/Demo/SuperH_SH7216_Renesas/RTOSDemo.tws
index c9d1887c1862f8c1a5399530c35339e405360232..2303b819be2b11f4c6cc9061aea21c29d707f4c8 100644 (file)
--- a/Demo/SuperH_SH7216_Renesas/RTOSDemo.tws
+++ b/Demo/SuperH_SH7216_Renesas/RTOSDemo.tws
@@ -7,23 +7,17 @@
 [GENERAL_DATA]\r
 [BREAKPOINTS]\r
 [OPEN_WORKSPACE_FILES]\r
-"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\SuperH_SH7216_Renesas\RTOSDemo\FreeRTOSConfig.h" \r
-"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\SuperH_SH7216_Renesas\RTOSDemo\intprg.c" \r
 "C:\E\Dev\FreeRTOS\WorkingCopy\Demo\SuperH_SH7216_Renesas\RTOSDemo\main.c" \r
-"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\SuperH_SH7216_Renesas\RTOSDemo\resetprg.c" \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\SuperH_SH7216_Renesas\RTOSDemo\regtest.src" \r
 "C:\E\Dev\FreeRTOS\WorkingCopy\Demo\SuperH_SH7216_Renesas\RTOSDemo\vecttbl.c" \r
-"C:\E\Dev\FreeRTOS\WorkingCopy\Source\include\list.h" \r
 "C:\E\Dev\FreeRTOS\WorkingCopy\Source\portable\Renesas\SH2A_FPU\port.c" \r
-"C:\E\Dev\FreeRTOS\WorkingCopy\Source\portable\Renesas\SH2A_FPU\portmacro.h" \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Source\portable\Renesas\SH2A_FPU\portasm.src" \r
 [WORKSPACE_FILE_STATES]\r
-"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\SuperH_SH7216_Renesas\RTOSDemo\FreeRTOSConfig.h" 88 88 1216 383 0 2 \r
-"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\SuperH_SH7216_Renesas\RTOSDemo\intprg.c" 0 0 1132 383 0 7 \r
-"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\SuperH_SH7216_Renesas\RTOSDemo\main.c" -4 -23 1316 445 1 0 \r
-"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\SuperH_SH7216_Renesas\RTOSDemo\resetprg.c" 110 110 1216 383 0 5 \r
-"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\SuperH_SH7216_Renesas\RTOSDemo\vecttbl.c" 154 154 1132 383 0 6 \r
-"C:\E\Dev\FreeRTOS\WorkingCopy\Source\include\list.h" 66 66 1216 383 0 1 \r
-"C:\E\Dev\FreeRTOS\WorkingCopy\Source\portable\Renesas\SH2A_FPU\port.c" 0 0 1400 586 0 3 \r
-"C:\E\Dev\FreeRTOS\WorkingCopy\Source\portable\Renesas\SH2A_FPU\portmacro.h" 132 132 1216 383 0 4 \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\SuperH_SH7216_Renesas\RTOSDemo\main.c" 0 0 918 659 0 0 \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\SuperH_SH7216_Renesas\RTOSDemo\regtest.src" -4 -23 1016 659 1 4 \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\SuperH_SH7216_Renesas\RTOSDemo\vecttbl.c" 0 0 712 434 0 3 \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Source\portable\Renesas\SH2A_FPU\port.c" 0 0 1400 586 0 1 \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Source\portable\Renesas\SH2A_FPU\portasm.src" 0 0 805 659 0 2 \r
 [LOADED_PROJECTS]\r
 "RTOSDemo" \r
 [END]\r
diff --git a/Demo/SuperH_SH7216_Renesas/RTOSDemo/RTOSDemo.hwp b/Demo/SuperH_SH7216_Renesas/RTOSDemo/RTOSDemo.hwp
index 1e77fc7f74f9137f41daa16328aeb9290f7452a2..d3ddb2e16966280a6b96f46e269cd7308b5da066 100644 (file)
--- a/Demo/SuperH_SH7216_Renesas/RTOSDemo/RTOSDemo.hwp
+++ b/Demo/SuperH_SH7216_Renesas/RTOSDemo/RTOSDemo.hwp
@@ -121,14 +121,17 @@
 "C:\E\Dev\FreeRTOS\WorkingCopy\Demo\SuperH_SH7216_Renesas\RTOSDemo\dbsct.c" "User" "C source file" 2 \r
 "C:\E\Dev\FreeRTOS\WorkingCopy\Demo\SuperH_SH7216_Renesas\RTOSDemo\intprg.c" "User" "C source file" 2 \r
 "C:\E\Dev\FreeRTOS\WorkingCopy\Demo\SuperH_SH7216_Renesas\RTOSDemo\main.c" "User" "C source file" 2 \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\SuperH_SH7216_Renesas\RTOSDemo\regtest.src" "User" "Assembly source file" 2 \r
 "C:\E\Dev\FreeRTOS\WorkingCopy\Demo\SuperH_SH7216_Renesas\RTOSDemo\resetprg.c" "User" "C source file" 2 \r
 "C:\E\Dev\FreeRTOS\WorkingCopy\Demo\SuperH_SH7216_Renesas\RTOSDemo\vecttbl.c" "User" "C source file" 2 \r
 "C:\E\Dev\FreeRTOS\WorkingCopy\Source\list.c" "User" "C source file|FreeRTOS" 2 \r
 "C:\E\Dev\FreeRTOS\WorkingCopy\Source\portable\MemMang\heap_2.c" "User" "C source file|FreeRTOS" 2 \r
 "C:\E\Dev\FreeRTOS\WorkingCopy\Source\portable\Renesas\SH2A_FPU\port.c" "User" "C source file|FreeRTOS" 2 \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Source\portable\Renesas\SH2A_FPU\portasm.src" "User" "Assembly source file" 2 \r
 "C:\E\Dev\FreeRTOS\WorkingCopy\Source\queue.c" "User" "C source file|FreeRTOS" 2 \r
 "C:\E\Dev\FreeRTOS\WorkingCopy\Source\tasks.c" "User" "C source file|FreeRTOS" 2 \r
 [FOLDER]\r
+"Assembly source file" "Assembly source file" \r
 "C source file" "C source file" \r
 "C source file|FreeRTOS" "" \r
 [GENERAL_DATA_PROJECT]\r
@@ -139,24 +142,26 @@
 "SessionSH7216_E10A-USB_SYSTEM__SH" "C:\E\Dev\FreeRTOS\WorkingCopy\Demo\SuperH_SH7216_Renesas\RTOSDemo\SessionSH7216_E10A-USB_SYSTEM__SH.hsf" 0 \r
 [GENERAL_DATA_SESSION_SessionSH7216_E10A-USB_SYSTEM__SH]\r
 [OPTIONS_Debug_SH7216_E10A-USB_SYSTEM__SH_Renesas OptLinker]\r
-"Single Shot" "03711fb24378ac10" 4 \r
+"Single Shot" "0d47a4b27059ac10" 4 \r
 [OPTIONS_Debug_SH7216_E10A-USB_SYSTEM__SH_Renesas SH Assembler]\r
 "Assembly source file" "05db08d6f178ac10" 3 \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\SuperH_SH7216_Renesas\RTOSDemo\regtest.src" "0fd8e3b27059ac10" 3 \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Source\portable\Renesas\SH2A_FPU\portasm.src" "0cc802940e29ac10" 3 \r
 "Linkage symbol file" "05db08d6f178ac10" 3 \r
 [OPTIONS_Debug_SH7216_E10A-USB_SYSTEM__SH_Renesas SH C/C++ Compiler]\r
-"C source file" "0a3b1de34378ac10" 2 \r
-"C++ source file" "0a3b1de34378ac10" 2 \r
-"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\SuperH_SH7216_Renesas\RTOSDemo\ParTest\ParTest.c" "0a3b1de34378ac10" 2 \r
-"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\SuperH_SH7216_Renesas\RTOSDemo\dbsct.c" "0a3b1de34378ac10" 2 \r
-"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\SuperH_SH7216_Renesas\RTOSDemo\intprg.c" "0a3b1de34378ac10" 2 \r
-"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\SuperH_SH7216_Renesas\RTOSDemo\main.c" "0a3b1de34378ac10" 2 \r
-"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\SuperH_SH7216_Renesas\RTOSDemo\resetprg.c" "0a3b1de34378ac10" 2 \r
-"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\SuperH_SH7216_Renesas\RTOSDemo\vecttbl.c" "0a3b1de34378ac10" 2 \r
-"C:\E\Dev\FreeRTOS\WorkingCopy\Source\list.c" "0a3b1de34378ac10" 2 \r
-"C:\E\Dev\FreeRTOS\WorkingCopy\Source\portable\MemMang\heap_2.c" "0a3b1de34378ac10" 2 \r
-"C:\E\Dev\FreeRTOS\WorkingCopy\Source\portable\Renesas\SH2A_FPU\port.c" "0a3b1de34378ac10" 2 \r
-"C:\E\Dev\FreeRTOS\WorkingCopy\Source\queue.c" "0a3b1de34378ac10" 2 \r
-"C:\E\Dev\FreeRTOS\WorkingCopy\Source\tasks.c" "0a3b1de34378ac10" 2 \r
+"C source file" "0deaf32ba059ac10" 2 \r
+"C++ source file" "0deaf32ba059ac10" 2 \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\SuperH_SH7216_Renesas\RTOSDemo\ParTest\ParTest.c" "0deaf32ba059ac10" 2 \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\SuperH_SH7216_Renesas\RTOSDemo\dbsct.c" "0deaf32ba059ac10" 2 \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\SuperH_SH7216_Renesas\RTOSDemo\intprg.c" "0deaf32ba059ac10" 2 \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\SuperH_SH7216_Renesas\RTOSDemo\main.c" "0deaf32ba059ac10" 2 \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\SuperH_SH7216_Renesas\RTOSDemo\resetprg.c" "0deaf32ba059ac10" 2 \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\SuperH_SH7216_Renesas\RTOSDemo\vecttbl.c" "0deaf32ba059ac10" 2 \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Source\list.c" "0deaf32ba059ac10" 2 \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Source\portable\MemMang\heap_2.c" "0deaf32ba059ac10" 2 \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Source\portable\Renesas\SH2A_FPU\port.c" "0deaf32ba059ac10" 2 \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Source\queue.c" "0deaf32ba059ac10" 2 \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Source\tasks.c" "0deaf32ba059ac10" 2 \r
 [OPTIONS_Debug_SH7216_E10A-USB_SYSTEM__SH_Renesas SH C/C++ Library Generator]\r
 "Single Shot" "05db08d6f178ac10" 1 \r
 [OPTIONS_Debug_SH7216_E10A-USB_SYSTEM__SH]\r
@@ -165,7 +170,7 @@
 " 3 \r
 "[V|VERSION|6] [S|FORM|STYPE] [S|BYTE_COUNT_VALUE|FF] [B|DEBUG|1] [S|ROM|(D,R)] [S|CRC|NONE|00000000] [B|LIST|1] [S|LIST|^"$(CONFIGDIR)\$(PROJECTNAME).map^"] [S|SHOW|METHODCUSTOM|] [S|OUTPUT|^"$(CONFIGDIR)\$(PROJECTNAME).mot^"] [I|SPACE|^"FF^"] [B|OPTIMIZE|0] [I|CACHESIZE|000000008] [I|CACHELINE|000000020] [S|START|DVECTTBL,DINTTBL(00)|PResetPRG,PIntPRG(0800)|P,C,C$BSEC,C$DSEC,D(01000)|B,R(0FFF80000)|S(0FFFBFC00)] [B|SKIPDEPENDENCY|1]\r
 " 4 \r
-"[V|VERSION|7] [S|INCLUDE|^"$(PROJDIR)\..\..\..\Source\portable\Renesas\SH2A_FPU^"|^"$(PROJDIR)\..\..\..\Source\include^"|^"$(PROJDIR)\.^"|^"$(PROJDIR)\..\..\Common\include^"] [S|OUTPUTPATH|^"$(CONFIGDIR)\$(FILELEAF).obj^"] [B|DEBUG|1] [S|ALIGN4|ALL] [B|TBR|0] [B|STUFF|0] [S|BSS_ORDER|DECLARATION] [S|MXGEN_MEM0|00000000] [S|MXGEN_MEM1|00000000] [B|LIST|0] [S|GBR|AUTO] [S|INLINE|DEFAULT] [I|INLINE|20] [S|MISRA2004_CHECK_RULE|ALL] [S|MISRA2004_RULE|1.1|3.4|4.1|5.2|5.3|5.4|5.5|5.6|5.7|6.1|6.2|6.3|6.4|6.5|7.1|8.1|8.2|8.3|8.5|8.6|8.7|8.8|8.11|8.12|9.2|9.3|10.1|10.2|10.3|10.4|10.5|10.6|11.1|11.2|11.3|11.4|11.5|12.1|12.2|12.3|12.4|12.5|12.6|12.7|12.8|12.9|12.10|12.11|12.12|12.13|13.1|13.2|13.3|13.4|13.7|14.1|14.2|14.3|14.4|14.5|14.6|14.7|14.8|14.9|14.10|15.1|15.2|15.3|15.4|15.5|16.1|16.2|16.3|16.4|16.5|16.6|16.8|16.9|17.3|17.4|17.5|17.6|18.1|18.2|18.4|19.1|20.2|20.4|20.5|20.7|20.8|20.9|20.10|20.11|20.12] [S|MISRA1998_CHECK_RULE|ALL] [S|MISRA1998_RULE|1|5|8|12|13|14|17|18|19|20|21|22|24|28|29|31|32|33|34|35|36|37|38|39|40|42|43|44|45|46|48|49|50|51|53|54|55|56|57|58|59|60|61|62|63|64|65|68|69|70|71|72|73|74|75|76|77|78|79|80|82|83|84|85|99|101|102|103|104|105|106|108|110|111|112|113|115|118|119|121|122|123|124|125|126|127] [S|MISRA_GROUP_FILE_PATH|^"$(PROJDIR)\$(PROJECTNAME).rde^"] [S|OPT_RANGE|ALL] [I|MAX_UNROLL|1] [S|CPU|SH2AFPU] [S|ROUND|NEAREST] [B|CHGINCPATH|1] [B|SKIPDEPENDENCY|1] [N|DEPENDSCAN|1]\r
+"[V|VERSION|7] [S|INCLUDE|^"$(PROJDIR)\..\..\..\Source\portable\Renesas\SH2A_FPU^"|^"$(PROJDIR)\..\..\..\Source\include^"|^"$(PROJDIR)\.^"|^"$(PROJDIR)\..\..\Common\include^"] [S|OUTPUTPATH|^"$(CONFIGDIR)\$(FILELEAF).obj^"] [B|DEBUG|1] [S|ALIGN4|ALL] [S|ASSEMBLY|^"[V|VERSION|1]] [S|OUTPUTPATH|^"^"$(CONFIGDIR)\$(FILELEAF).obj^"^"]] [S|LITERAL|POOL|BRANCH|JUMP|RETURN]] [S|DISPSIZE|12]] [I|TAB|8]] [B|CHGINCPATH|1]] [S|CPU|SH2AFPU]] [S|ENDIAN|BIG]] [S|ROUND|NEAREST]] [B|DENORMALIZE|0]]^"] [B|TBR|0] [B|STUFF|0] [S|BSS_ORDER|DECLARATION] [S|MXGEN_MEM0|00000000] [S|MXGEN_MEM1|00000000] [B|LIST|0] [B|OPTIMIZE|0] [S|GBR|AUTO] [S|INLINE|DEFAULT] [I|INLINE|20] [S|MISRA2004_CHECK_RULE|ALL] [S|MISRA2004_RULE|1.1|3.4|4.1|5.2|5.3|5.4|5.5|5.6|5.7|6.1|6.2|6.3|6.4|6.5|7.1|8.1|8.2|8.3|8.5|8.6|8.7|8.8|8.11|8.12|9.2|9.3|10.1|10.2|10.3|10.4|10.5|10.6|11.1|11.2|11.3|11.4|11.5|12.1|12.2|12.3|12.4|12.5|12.6|12.7|12.8|12.9|12.10|12.11|12.12|12.13|13.1|13.2|13.3|13.4|13.7|14.1|14.2|14.3|14.4|14.5|14.6|14.7|14.8|14.9|14.10|15.1|15.2|15.3|15.4|15.5|16.1|16.2|16.3|16.4|16.5|16.6|16.8|16.9|17.3|17.4|17.5|17.6|18.1|18.2|18.4|19.1|20.2|20.4|20.5|20.7|20.8|20.9|20.10|20.11|20.12] [S|MISRA1998_CHECK_RULE|ALL] [S|MISRA1998_RULE|1|5|8|12|13|14|17|18|19|20|21|22|24|28|29|31|32|33|34|35|36|37|38|39|40|42|43|44|45|46|48|49|50|51|53|54|55|56|57|58|59|60|61|62|63|64|65|68|69|70|71|72|73|74|75|76|77|78|79|80|82|83|84|85|99|101|102|103|104|105|106|108|110|111|112|113|115|118|119|121|122|123|124|125|126|127] [S|MISRA_GROUP_FILE_PATH|^"$(PROJDIR)\$(PROJECTNAME).rde^"] [S|OPT_RANGE|ALL] [I|MAX_UNROLL|1] [S|CPU|SH2AFPU] [S|ROUND|NEAREST] [B|CHGINCPATH|1] [B|SKIPDEPENDENCY|1] [N|DEPENDSCAN|1]\r
 " 2 \r
 "[V|VERSION|7] [S|MODE|BUILD/CHANGED] [S|EXISTOUTPUTPATH|^"$(CONFIGDIR)\$(PROJECTNAME).lib^"] [B|RUNTIME|1] [B|STDLIB|1] [B|STRING|1] [S|OUTPUTPATH|^"$(CONFIGDIR)\$(PROJECTNAME).lib^"] [S|ALIGN4|ALL] [B|STUFF|0] [S|BSS_ORDER|DECLARATION] [S|GBR|AUTO] [S|INLINE|DEFAULT] [I|INLINE|20] [S|OPT_RANGE|ALL] [I|MAX_UNROLL|1] [B|SAVE_CONT_REG|1] [S|CPU|SH2AFPU] [S|ROUND|NEAREST] [B|SKIPDEPENDENCY|1]\r
 " 1 \r
diff --git a/Demo/SuperH_SH7216_Renesas/RTOSDemo/RTOSDemo.nav b/Demo/SuperH_SH7216_Renesas/RTOSDemo/RTOSDemo.nav
index 823c549d190b605ffd49442bf0b6fbac5f927c46..ac41d6529f2532a9ac4155c1e18868731d7b3a51 100644 (file)
Binary files a/Demo/SuperH_SH7216_Renesas/RTOSDemo/RTOSDemo.nav and b/Demo/SuperH_SH7216_Renesas/RTOSDemo/RTOSDemo.nav differ
diff --git a/Demo/SuperH_SH7216_Renesas/RTOSDemo/RTOSDemo.tps b/Demo/SuperH_SH7216_Renesas/RTOSDemo/RTOSDemo.tps
index 750d5a6592a39b9366c9f363caceb8248bbc7049..804f6fa5088b480c793000047ef2ed3ab5fb8646 100644 (file)
--- a/Demo/SuperH_SH7216_Renesas/RTOSDemo/RTOSDemo.tps
+++ b/Demo/SuperH_SH7216_Renesas/RTOSDemo/RTOSDemo.tps
@@ -12,7 +12,7 @@
 "SessionSH7216_E10A-USB_SYSTEM__SH" \r
 [GENERAL_DATA_PROJECT]\r
 [GENERAL_DATA_CONFIGURATION_Debug_SH7216_E10A-USB_SYSTEM__SH]\r
-"PROJECT_FILES_MODIFIED_DATA_TAG" "TRUE" \r
+"PROJECT_FILES_MODIFIED_DATA_TAG" "FALSE" \r
 [SESSIONS_Debug_SH7216_E10A-USB_SYSTEM__SH]\r
 "SessionSH7216_E10A-USB_SYSTEM__SH" \r
 [GENERAL_DATA_SESSION_SessionSH7216_E10A-USB_SYSTEM__SH]\r
diff --git a/Demo/SuperH_SH7216_Renesas/RTOSDemo/SessionSH7216_E10A-USB_SYSTEM__SH.hsf b/Demo/SuperH_SH7216_Renesas/RTOSDemo/SessionSH7216_E10A-USB_SYSTEM__SH.hsf
index e4912a8f81e7d5a4273b0456eab72f1eee151ca9..8138c036286e2fe86f04f98a62a36982052acf55 100644 (file)
--- a/Demo/SuperH_SH7216_Renesas/RTOSDemo/SessionSH7216_E10A-USB_SYSTEM__SH.hsf
+++ b/Demo/SuperH_SH7216_Renesas/RTOSDemo/SessionSH7216_E10A-USB_SYSTEM__SH.hsf
@@ -79,7 +79,23 @@
 "{8A898260-6F1D-11D5-8EB6-00004CC34E9D}ECX_WAVE_COMB_BUFFER" ",,,," \r
 "{8A898260-6F1D-11D5-8EB6-00004CC34E9D}ECX_WAVE_SAMPLING_RATE" "1000" \r
 "{8A898260-6F1D-11D5-8EB6-00004CC34E9D}WaveformCtrlViews" "0" \r
-"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersCtrlViews" "0" \r
+"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersCtrlViews" "1" \r
+"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersWnd0ColumnWidth" "50,307,118" \r
+"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersWnd0ECX_REGISTER_COUNT" "82" \r
+"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersWnd0ECX_REGISTER_DISPLAYED" "1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1" \r
+"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersWnd0HideFLAGs" "1" \r
+"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersWnd0HideRadix" "0" \r
+"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersWnd0LastFileName" "" \r
+"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersWnd0RadixList" "16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,2,16,16,16,16,16,16,16,2,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16," \r
+"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersWndInstanceKey0" "{WK_00000001_REGISTERS}RTOSDemoSessionSH7216_E10A-USB_SYSTEM__SH" \r
+"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersWndViewB0ColumnWidth" "50,456,35" \r
+"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersWndViewB0ECX_REGISTER_COUNT" "82" \r
+"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersWndViewB0ECX_REGISTER_DISPLAYED" "1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1" \r
+"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersWndViewB0HideFLAGs" "1" \r
+"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersWndViewB0HideRadix" "0" \r
+"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersWndViewB0LastFileName" "" \r
+"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersWndViewB0RadixList" "16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,2,16,16,16,16,16,16,16,2,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16," \r
+"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersWndViewBInstanceKey0" "{WK_00000001_REGISTERS}RTOSDemoSessionSH7216_E10A-USB_SYSTEM__SHViewB" \r
 "{AC411480-6F0A-11D5-8EB6-00004CC34E9D}ECX_IMAGE_ADDRESS_NAME" "" \r
 "{AC411480-6F0A-11D5-8EB6-00004CC34E9D}ECX_IMAGE_BUFFER" "00000000,00000000,0,0" \r
 "{AC411480-6F0A-11D5-8EB6-00004CC34E9D}ECX_IMAGE_COLOR" "0,0,0,0" \r
@@ -90,8 +106,43 @@
 "{AC411480-6F0A-11D5-8EB6-00004CC34E9D}ECX_IMAGE_SAMPLEING_RATE" "1000" \r
 "{AC411480-6F0A-11D5-8EB6-00004CC34E9D}ECX_IMAGE_VIEW" "0,0,0,0,0,0" \r
 "{AC411480-6F0A-11D5-8EB6-00004CC34E9D}ImageCtrlViews" "0" \r
-"{B266D880-6FA1-11D5-8613-00A024591A38}WatchCtrlViews" "0" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchCtrlViews" "4" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ColWidth0" "198" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ColWidth1" "150" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ColWidth12" "150" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ColWidth2" "120" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ColWidth3" "200" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ECX_WATCH_ITEM0000" "pxCurrentTCB, 4, 0, P, Col, Hex, MN" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ECX_WATCH_ITEM0000_SCOPE" "Current Scope," \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ECX_WATCH_ITEM0001" "*, 11, 0, C0000, Exp, Hex, N" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ECX_WATCH_ITEM0002" "pxTopOfStack, 4, 0, C0001, Col, Hex, N" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ECX_WATCH_ITEM0003" "xGenericListItem, 11, 0, C0001, Col, Hex, N" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ECX_WATCH_ITEM0004" "xEventListItem, 11, 0, C0001, Col, Hex, N" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ECX_WATCH_ITEM0005" "uxPriority, 2, 0, C0001, Col, Hex, N" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ECX_WATCH_ITEM0006" "pxStack, 4, 0, C0001, Col, Hex, N" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ECX_WATCH_ITEM0007" "pcTaskName, 6, 0, C0001, Col, Hex, N" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ECX_WATCH_ITEM0008" "uxCriticalNesting, 2, 0, C0001, Col, Hex, N" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ECX_WATCH_ITEMCnt" "1" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd1ColWidth0" "120" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd1ColWidth1" "150" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd1ColWidth12" "150" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd1ColWidth2" "120" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd1ColWidth3" "200" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd1ECX_WATCH_ITEMCnt" "0" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd2ColWidth0" "120" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd2ColWidth1" "150" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd2ColWidth12" "150" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd2ColWidth2" "120" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd2ColWidth3" "200" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd2ECX_WATCH_ITEMCnt" "0" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd3ColWidth0" "120" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd3ColWidth1" "150" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd3ColWidth12" "150" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd3ColWidth2" "120" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd3ColWidth3" "200" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd3ECX_WATCH_ITEMCnt" "0" \r
 "{B266D880-6FA1-11D5-8613-00A024591A38}WatchWndInitial_Radix" "0" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWndInstanceKey0" "{WK_00000001_WATCH}RTOSDemoSessionSH7216_E10A-USB_SYSTEM__SH" \r
 "{B266D880-6FA1-11D5-8613-00A024591A38}WatchWndRecentFile_WatchRecord" "" \r
 "{B266D880-6FA1-11D5-8613-00A024591A38}WatchWndRecentFile_WatchSave" "" \r
 "{B266D880-6FA1-11D5-8613-00A024591A38}WatchWndUpdate_Interval" "100" \r
@@ -188,30 +239,30 @@
 "{D293FA15-461F-4D9F-B9C9-64724B3409F9}T_TRACE_TRACE_ACQUISITION2" "1,0,1,1,1,1,1,0,0,0,0,0,0" \r
 "{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_EVAL_DENORMAL_MODE" "16777216" \r
 "{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_EVAL_ROUND_MODE" "768" \r
-"{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_0" "00000000FFFF8000" \r
-"{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_1" "00000000FFFE3A00" \r
-"{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_10" "0000000000000000" \r
-"{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_11" "0000000000000000" \r
-"{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_12" "0000000000000000" \r
-"{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_13" "0000000000000000" \r
-"{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_14" "0000000000000000" \r
-"{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_15" "00000000FFFC0000" \r
-"{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_16" "00000000000011EC" \r
+"{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_0" "00000000FFF80AD4" \r
+"{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_1" "0000000000000001" \r
+"{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_10" "000000000000000B" \r
+"{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_11" "000000000000000C" \r
+"{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_12" "000000000000000D" \r
+"{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_13" "000000000000000E" \r
+"{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_14" "0000000000000022" \r
+"{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_15" "00000000FFF801E0" \r
+"{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_16" "0000000000001EF0" \r
 "{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_17" "0000000000000001" \r
-"{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_18" "0000000000000000" \r
+"{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_18" "0000000000000011" \r
 "{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_19" "0000000000000000" \r
-"{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_2" "00000000FFFFFA00" \r
+"{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_2" "0000000000000003" \r
 "{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_20" "0000000000000000" \r
-"{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_21" "0000000000000000" \r
-"{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_22" "0000000000000000" \r
-"{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_23" "00000000000011E2" \r
+"{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_21" "0000000000000010" \r
+"{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_22" "000000000000000F" \r
+"{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_23" "0000000000000011" \r
 "{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_24" "0000000000000000" \r
 "{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_25" "0000000000040001" \r
 "{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_26" "0000000000000000" \r
 "{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_27" "0000000000000000" \r
 "{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_28" "0000000000000000" \r
 "{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_29" "0000000000000000" \r
-"{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_3" "00000000FFFE3A06" \r
+"{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_3" "0000000000000004" \r
 "{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_30" "0000000000000000" \r
 "{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_31" "0000000000000000" \r
 "{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_32" "0000000000000000" \r
@@ -222,7 +273,7 @@
 "{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_37" "0000000000000000" \r
 "{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_38" "0000000000000000" \r
 "{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_39" "0000000000000000" \r
-"{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_4" "0000000000000001" \r
+"{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_4" "0000000000000005" \r
 "{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_40" "0000000000000000" \r
 "{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_41" "0000000000000000" \r
 "{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_42" "0000000000000000" \r
@@ -233,11 +284,11 @@
 "{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_47" "0000000000000000" \r
 "{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_48" "0000000000000000" \r
 "{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_49" "0000000000000000" \r
-"{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_5" "00000000FFFFFA00" \r
-"{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_6" "00000000FFFFFA00" \r
-"{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_7" "00000000FFFFFF0F" \r
-"{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_8" "0000000000000000" \r
-"{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_9" "0000000000000000" \r
+"{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_5" "0000000000000006" \r
+"{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_6" "0000000000000007" \r
+"{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_7" "0000000000000008" \r
+"{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_8" "0000000000000009" \r
+"{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_9" "000000000000000A" \r
 "{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_COUNT" "50" \r
 "{D595F9C0-EF22-11D5-B7DB-0000E10B3DA9}EventCtrlViews" "0" \r
 "{EEDC9300-6FBE-11D5-8613-00A024591A38}LocalsCtrlViews" "0" \r
@@ -270,7 +321,7 @@
 "{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp23" "0" \r
 "{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp24" "0" \r
 "{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp25" "0" \r
-"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp26" "1" \r
+"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp26" "0" \r
 "{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp27" "0" \r
 "{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp28" "0" \r
 "{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp29" "0" \r
@@ -325,7 +376,7 @@
 "{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp8" "0" \r
 "{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp9" "0" \r
 "{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0ScrollHorz" "0" \r
-"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0ScrollVert" "24" \r
+"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0ScrollVert" "0" \r
 "{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd1ColWidth0" "200" \r
 "{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd1ColWidth1" "100" \r
 "{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd1ColWidth2" "100" \r
@@ -349,13 +400,14 @@
 0 \r
 [WINDOW_POSITION_STATE_DATA_VD1]\r
 "Help" "TOOLBAR 0" 59419 1 5 "0.00" 0 0 0 0 0 17 0 "" "0.0" \r
-"{WK_00000001_CmdLine}RTOSDemoSessionSH7216_E10A-USB_SYSTEM__SH" "WINDOW" 59422 0 0 "0.02" 433 0 0 350 200 18 0 "32771|32772|32778|<<separator>>|32773|32774|<<separator>>|32820|<<separator>>|32801|32824" "0.0" \r
+"{WK_00000001_CmdLine}RTOSDemoSessionSH7216_E10A-USB_SYSTEM__SH" "WINDOW" 59422 0 1 "0.08" 219 0 0 350 200 18 0 "32771|32772|32778|<<separator>>|32773|32774|<<separator>>|32820|<<separator>>|32801|32824" "0.0" \r
 "{WK_00000001_DISASSEMBLY}" "WINDOW" 0 0 0 "0.00" 0 -4 -23 1400 586 9 0 "" "0.0" \r
 "{WK_00000001_EVENT}RTOSDemoSessionSH7216_E10A-USB_SYSTEM__SH" "WINDOW" 59422 0 0 "0.50" 292 0 0 350 200 2065 0 "32774|32775|32777|<<separator>>|32780|<<separator>>" "0.0" \r
-"{WK_00000001_IO}RTOSDemoSessionSH7216_E10A-USB_SYSTEM__SH" "WINDOW" 59422 0 1 "0.46" 433 0 0 350 200 18 0 "32817|32826|32819|32820|32821" "0.0" \r
-"{WK_00000001_OUTPUT}" "WINDOW" 59422 0 1 "0.98" 433 560 340 350 200 18 0 "36756|36757|36758|36759|<<separator>>|36746|36747|<<separator>>|39531|<<separator>>|39500|39534|<<separator>>|36687" "0.0" \r
-"{WK_00000001_REGISTERS}RTOSDemoSessionSH7216_E10A-USB_SYSTEM__SH" "WINDOW" 59421 0 0 "1.00" 666 0 0 350 200 2065 0 "" "0.0" \r
-"{WK_00000001_STATUS}RTOSDemoSessionSH7216_E10A-USB_SYSTEM__SH" "WINDOW" 59422 0 0 "0.50" 433 0 0 350 200 17 0 "" "0.0" \r
+"{WK_00000001_IO}RTOSDemoSessionSH7216_E10A-USB_SYSTEM__SH" "WINDOW" 59422 0 3 "0.31" 219 0 0 350 200 17 0 "32817|32826|32819|32820|32821" "0.0" \r
+"{WK_00000001_OUTPUT}" "WINDOW" 59422 0 2 "0.92" 219 560 340 350 200 18 0 "36756|36757|36758|36759|<<separator>>|36746|36747|<<separator>>|39531|<<separator>>|39500|39534|<<separator>>|36687" "0.0" \r
+"{WK_00000001_REGISTERS}RTOSDemoSessionSH7216_E10A-USB_SYSTEM__SH" "WINDOW" 59421 0 0 "1.00" 293 0 0 350 200 18 0 "" "0.0" \r
+"{WK_00000001_STATUS}RTOSDemoSessionSH7216_E10A-USB_SYSTEM__SH" "WINDOW" 59422 0 4 "0.50" 219 0 0 350 200 17 0 "" "0.0" \r
+"{WK_00000001_WATCH}RTOSDemoSessionSH7216_E10A-USB_SYSTEM__SH" "WINDOW" 59422 0 0 "0.50" 219 0 0 350 200 17 0 "32781|32783|<<separator>>|32771|32829|32772|32827|32773|<<separator>>|32786|<<separator>>|32810|32811|32831" "0.0" \r
 "{WK_00000002_WORKSPACE}" "WINDOW" 59420 0 0 "1.00" 340 560 340 350 200 18 0 "" "0.0" \r
 "{WK_TB00000001_STANDARD}" "TOOLBAR 0" 59419 0 2 "0.00" 0 0 0 0 0 18 0 "" "0.0" \r
 "{WK_TB00000002_EDITOR}" "TOOLBAR 0" 59419 0 0 "0.00" 0 0 0 0 0 18 0 "" "0.0" \r
@@ -367,7 +419,7 @@
 "{WK_TB00000009_VERSIONCONTROL}" "TOOLBAR 0" 59419 1 3 "0.00" 0 0 0 0 0 17 0 "" "0.0" \r
 "{WK_TB00000011_CPU}" "TOOLBAR 0" 59419 2 3 "0.00" 0 0 0 0 0 18 0 "" "0.0" \r
 "{WK_TB00000012_MAP}" "TOOLBAR 0" 59419 1 4 "0.00" 0 0 0 0 0 17 0 "" "0.0" \r
-"{WK_TB00000013_SYMBOL}" "TOOLBAR 0" 59419 2 4 "0.00" 0 0 0 0 0 18 0 "" "0.0" \r
+"{WK_TB00000013_SYMBOL}" "TOOLBAR 0" 59419 2 5 "0.00" 0 0 0 0 0 18 0 "" "0.0" \r
 "{WK_TB00000014_CODE}" "TOOLBAR 0" 59419 2 8 "0.00" 0 0 0 0 0 17 0 "" "0.0" \r
 "{WK_TB00000015_PERFORMANCE}" "TOOLBAR 0" 59419 2 7 "0.00" 0 0 0 0 0 17 0 "" "0.0" \r
 "{WK_TB00000016_GRAPHIC}" "TOOLBAR 0" 59419 2 6 "0.00" 0 0 0 0 0 17 0 "" "0.0" \r
@@ -375,19 +427,16 @@
 "{WK_TB00000023_RTOS}" "TOOLBAR 0" 59419 2 9 "0.00" 0 0 0 0 0 17 0 "" "0.0" \r
 "{WK_TB00000026_MACRO}" "TOOLBAR 0" 59419 1 6 "0.00" 0 0 0 0 0 17 0 "" "0.0" \r
 "{WK_TB00000028_RTOSDEBUG}" "TOOLBAR 0" 59419 2 2 "0.00" 0 0 0 0 0 17 0 "" "0.0" \r
-"{WK_TB00000029_SYSTEMTOOL}" "TOOLBAR 0" 59419 2 3 "0.00" 0 0 0 0 0 17 0 "" "0.0" \r
+"{WK_TB00000029_SYSTEMTOOL}" "TOOLBAR 0" 59419 2 4 "0.00" 0 0 0 0 0 17 0 "" "0.0" \r
 [WINDOW_POSITION_STATE_DATA_VD2]\r
 [WINDOW_POSITION_STATE_DATA_VD3]\r
 [WINDOW_POSITION_STATE_DATA_VD4]\r
 [WINDOW_Z_ORDER]\r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\SuperH_SH7216_Renesas\RTOSDemo\regtest.src" \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Source\portable\Renesas\SH2A_FPU\portasm.src" \r
 "C:\E\Dev\FreeRTOS\WorkingCopy\Demo\SuperH_SH7216_Renesas\RTOSDemo\main.c" \r
 "C:\E\Dev\FreeRTOS\WorkingCopy\Source\portable\Renesas\SH2A_FPU\port.c" \r
-"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\SuperH_SH7216_Renesas\RTOSDemo\intprg.c" \r
-"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\SuperH_SH7216_Renesas\RTOSDemo\resetprg.c" \r
-"C:\E\Dev\FreeRTOS\WorkingCopy\Source\portable\Renesas\SH2A_FPU\portmacro.h" \r
 "C:\E\Dev\FreeRTOS\WorkingCopy\Demo\SuperH_SH7216_Renesas\RTOSDemo\vecttbl.c" \r
-"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\SuperH_SH7216_Renesas\RTOSDemo\FreeRTOSConfig.h" \r
-"C:\E\Dev\FreeRTOS\WorkingCopy\Source\include\list.h" \r
 [TARGET_NAME]\r
 "SH7216 E10A-USB SYSTEM (SH2A-FPU)" "" 0 \r
 [STATUSBAR_STATEINFO_VD1]\r
@@ -434,9 +483,5 @@
 [FLASH_DETAILS]\r
 "" 0 0 "" 0 "" 0 0 "" 0 0 0 0 0 0 0 "" "" "" "" "" \r
 [BREAKPOINTS]\r
-"c:\e\dev\freertos\workingcopy\demo\superh_sh7216_renesas\rtosdemo\intprg.c" 291 2518 1 "{00000000-0000-0000-C000-000000000046}" "" \r
-"c:\e\dev\freertos\workingcopy\demo\superh_sh7216_renesas\rtosdemo\intprg.c" 299 2524 1 "{00000000-0000-0000-C000-000000000046}" "" \r
-"c:\e\dev\freertos\workingcopy\demo\superh_sh7216_renesas\rtosdemo\intprg.c" 307 2530 1 "{00000000-0000-0000-C000-000000000046}" "" \r
-"c:\e\dev\freertos\workingcopy\demo\superh_sh7216_renesas\rtosdemo\main.c" 139 4690 1 "{00000000-0000-0000-C000-000000000046}" "" \r
-"c:\e\dev\freertos\workingcopy\demo\superh_sh7216_renesas\rtosdemo\main.c" 154 4710 1 "{00000000-0000-0000-C000-000000000046}" "" \r
+"c:\e\dev\freertos\workingcopy\demo\superh_sh7216_renesas\rtosdemo\regtest.src" 89 7808 1 "{00000000-0000-0000-C000-000000000046}" "" \r
 [END]\r
diff --git a/Demo/SuperH_SH7216_Renesas/RTOSDemo/intprg.c b/Demo/SuperH_SH7216_Renesas/RTOSDemo/intprg.c
index 5afaa787aeb1f44e22e75b2809815dc9f600670f..e5fee0dce90cbdbbad2705d2db755c006e97f11e 100644 (file)
--- a/Demo/SuperH_SH7216_Renesas/RTOSDemo/intprg.c
+++ b/Demo/SuperH_SH7216_Renesas/RTOSDemo/intprg.c
@@ -16,35 +16,35 @@
 #pragma section IntPRG\r
 \r
 // 4 Illegal code\r
-void INT_Illegal_code(void){/* sleep(); */}\r
+void INT_Illegal_code(void){for( ;; ); /* sleep(); */}\r
 // 5 Reserved\r
 \r
 // 6 Illegal slot\r
-void INT_Illegal_slot(void){/* sleep(); */}\r
+void INT_Illegal_slot(void){for( ;; ); /* sleep(); */}\r
 // 7 Reserved\r
 \r
 // 8 Reserved\r
 \r
 // 9 CPU Address error\r
-void INT_CPU_Address(void){/* sleep(); */}\r
+void INT_CPU_Address(void){for( ;; ); /* sleep(); */}\r
 // 10 DMAC Address error\r
-void INT_DMAC_Address(void){/* sleep(); */}\r
+void INT_DMAC_Address(void){for( ;; ); /* sleep(); */}\r
 // 11 NMI\r
-void INT_NMI(void){/* sleep(); */}\r
+void INT_NMI(void){for( ;; ); /* sleep(); */}\r
 // 12 User breakpoint trap\r
-void INT_User_Break(void){/* sleep(); */}\r
+void INT_User_Break(void){for( ;; ); /* sleep(); */}\r
 // 13 Reserved\r
 \r
 // 14 H-UDI\r
-void INT_HUDI(void){/* sleep(); */}\r
+void INT_HUDI(void){for( ;; ); /* sleep(); */}\r
 // 15 Register bank over\r
-void INT_Bank_Overflow(void){/* sleep(); */}\r
+void INT_Bank_Overflow(void){for( ;; ); /* sleep(); */}\r
 // 16 Register bank under\r
-void INT_Bank_Underflow(void){/* sleep(); */}\r
+void INT_Bank_Underflow(void){for( ;; ); /* sleep(); */}\r
 // 17 ZERO DIV\r
-void INT_Divide_by_Zero(void){/* sleep(); */}\r
+void INT_Divide_by_Zero(void){for( ;; ); /* sleep(); */}\r
 // 18 OVER DIV\r
-void INT_Divide_Overflow(void){/* sleep(); */}\r
+void INT_Divide_Overflow(void){for( ;; ); /* sleep(); */}\r
 // 19 Reserved\r
 \r
 // 20 Reserved\r
@@ -72,85 +72,85 @@ void INT_Divide_Overflow(void){/* sleep(); */}
 // 31 Reserved\r
 \r
 // 32 TRAPA (User Vecter)\r
-void INT_TRAPA32(void){/* sleep(); */}\r
+void INT_TRAPA32(void){ for( ;; ); /* sleep(); */ }\r
 // 33 TRAPA (User Vecter)\r
-void INT_TRAPA33(void){/* sleep(); */}\r
+void INT_TRAPA33(void){for( ;; ); /* sleep(); */}\r
 // 34 TRAPA (User Vecter)\r
-void INT_TRAPA34(void){/* sleep(); */}\r
+void INT_TRAPA34(void){for( ;; ); /* sleep(); */}\r
 // 35 TRAPA (User Vecter)\r
-void INT_TRAPA35(void){/* sleep(); */}\r
+void INT_TRAPA35(void){for( ;; ); /* sleep(); */}\r
 // 36 TRAPA (User Vecter)\r
-void INT_TRAPA36(void){/* sleep(); */}\r
+void INT_TRAPA36(void){for( ;; ); /* sleep(); */}\r
 // 37 TRAPA (User Vecter)\r
-void INT_TRAPA37(void){/* sleep(); */}\r
+void INT_TRAPA37(void){for( ;; ); /* sleep(); */}\r
 // 38 TRAPA (User Vecter)\r
-void INT_TRAPA38(void){/* sleep(); */}\r
+void INT_TRAPA38(void){for( ;; ); /* sleep(); */}\r
 // 39 TRAPA (User Vecter)\r
-void INT_TRAPA39(void){/* sleep(); */}\r
+void INT_TRAPA39(void){for( ;; ); /* sleep(); */}\r
 // 40 TRAPA (User Vecter)\r
-void INT_TRAPA40(void){/* sleep(); */}\r
+void INT_TRAPA40(void){for( ;; ); /* sleep(); */}\r
 // 41 TRAPA (User Vecter)\r
-void INT_TRAPA41(void){/* sleep(); */}\r
+void INT_TRAPA41(void){for( ;; ); /* sleep(); */}\r
 // 42 TRAPA (User Vecter)\r
-void INT_TRAPA42(void){/* sleep(); */}\r
+void INT_TRAPA42(void){for( ;; ); /* sleep(); */}\r
 // 43 TRAPA (User Vecter)\r
-void INT_TRAPA43(void){/* sleep(); */}\r
+void INT_TRAPA43(void){for( ;; ); /* sleep(); */}\r
 // 44 TRAPA (User Vecter)\r
-void INT_TRAPA44(void){/* sleep(); */}\r
+void INT_TRAPA44(void){for( ;; ); /* sleep(); */}\r
 // 45 TRAPA (User Vecter)\r
-void INT_TRAPA45(void){/* sleep(); */}\r
+void INT_TRAPA45(void){for( ;; ); /* sleep(); */}\r
 // 46 TRAPA (User Vecter)\r
-void INT_TRAPA46(void){/* sleep(); */}\r
+void INT_TRAPA46(void){for( ;; ); /* sleep(); */}\r
 // 47 TRAPA (User Vecter)\r
-void INT_TRAPA47(void){/* sleep(); */}\r
+void INT_TRAPA47(void){for( ;; ); /* sleep(); */}\r
 // 48 TRAPA (User Vecter)\r
-void INT_TRAPA48(void){/* sleep(); */}\r
+void INT_TRAPA48(void){for( ;; ); /* sleep(); */}\r
 // 49 TRAPA (User Vecter)\r
-void INT_TRAPA49(void){/* sleep(); */}\r
+void INT_TRAPA49(void){for( ;; ); /* sleep(); */}\r
 // 50 TRAPA (User Vecter)\r
-void INT_TRAPA50(void){/* sleep(); */}\r
+void INT_TRAPA50(void){for( ;; ); /* sleep(); */}\r
 // 51 TRAPA (User Vecter)\r
-void INT_TRAPA51(void){/* sleep(); */}\r
+void INT_TRAPA51(void){for( ;; ); /* sleep(); */}\r
 // 52 TRAPA (User Vecter)\r
-void INT_TRAPA52(void){/* sleep(); */}\r
+void INT_TRAPA52(void){for( ;; ); /* sleep(); */}\r
 // 53 TRAPA (User Vecter)\r
-void INT_TRAPA53(void){/* sleep(); */}\r
+void INT_TRAPA53(void){for( ;; ); /* sleep(); */}\r
 // 54 TRAPA (User Vecter)\r
-void INT_TRAPA54(void){/* sleep(); */}\r
+void INT_TRAPA54(void){for( ;; ); /* sleep(); */}\r
 // 55 TRAPA (User Vecter)\r
-void INT_TRAPA55(void){/* sleep(); */}\r
+void INT_TRAPA55(void){for( ;; ); /* sleep(); */}\r
 // 56 TRAPA (User Vecter)\r
-void INT_TRAPA56(void){/* sleep(); */}\r
+void INT_TRAPA56(void){for( ;; ); /* sleep(); */}\r
 // 57 TRAPA (User Vecter)\r
-void INT_TRAPA57(void){/* sleep(); */}\r
+void INT_TRAPA57(void){for( ;; ); /* sleep(); */}\r
 // 58 TRAPA (User Vecter)\r
-void INT_TRAPA58(void){/* sleep(); */}\r
+void INT_TRAPA58(void){for( ;; ); /* sleep(); */}\r
 // 59 TRAPA (User Vecter)\r
-void INT_TRAPA59(void){/* sleep(); */}\r
+void INT_TRAPA59(void){for( ;; ); /* sleep(); */}\r
 // 60 TRAPA (User Vecter)\r
-void INT_TRAPA60(void){/* sleep(); */}\r
+void INT_TRAPA60(void){for( ;; ); /* sleep(); */}\r
 // 61 TRAPA (User Vecter)\r
-void INT_TRAPA61(void){/* sleep(); */}\r
+void INT_TRAPA61(void){for( ;; ); /* sleep(); */}\r
 // 62 TRAPA (User Vecter)\r
-void INT_TRAPA62(void){/* sleep(); */}\r
+void INT_TRAPA62(void){for( ;; ); /* sleep(); */}\r
 // 63 TRAPA (User Vecter)\r
-void INT_TRAPA63(void){/* sleep(); */}\r
+void INT_TRAPA63(void){for( ;; ); /* sleep(); */}\r
 // 64 Interrupt IRQ0\r
-void INT_IRQ0(void){/* sleep(); */}\r
+void INT_IRQ0(void){for( ;; ); /* sleep(); */}\r
 // 65 Interrupt IRQ1\r
-void INT_IRQ1(void){/* sleep(); */}\r
+void INT_IRQ1(void){for( ;; ); /* sleep(); */}\r
 // 66 Interrupt IRQ2\r
-void INT_IRQ2(void){/* sleep(); */}\r
+void INT_IRQ2(void){for( ;; ); /* sleep(); */}\r
 // 67 Interrupt IRQ3\r
-void INT_IRQ3(void){/* sleep(); */}\r
+void INT_IRQ3(void){for( ;; ); /* sleep(); */}\r
 // 68 Interrupt IRQ4\r
-void INT_IRQ4(void){/* sleep(); */}\r
+void INT_IRQ4(void){for( ;; ); /* sleep(); */}\r
 // 69 Interrupt IRQ5\r
-void INT_IRQ5(void){/* sleep(); */}\r
+void INT_IRQ5(void){for( ;; ); /* sleep(); */}\r
 // 70 Interrupt IRQ6\r
-void INT_IRQ6(void){/* sleep(); */}\r
+void INT_IRQ6(void){for( ;; ); /* sleep(); */}\r
 // 71 Interrupt IRQ7\r
-void INT_IRQ7(void){/* sleep(); */}\r
+void INT_IRQ7(void){for( ;; ); /* sleep(); */}\r
 // 72 Reserved\r
 \r
 // 73 Reserved\r
@@ -168,21 +168,21 @@ void INT_IRQ7(void){/* sleep(); */}
 // 79 Reserved\r
 \r
 // 80 Interrupt PINT0\r
-void INT_PINT0(void){/* sleep(); */}\r
+void INT_PINT0(void){for( ;; ); /* sleep(); */}\r
 // 81 Interrupt PINT1\r
-void INT_PINT1(void){/* sleep(); */}\r
+void INT_PINT1(void){for( ;; ); /* sleep(); */}\r
 // 82 Interrupt PINT2\r
-void INT_PINT2(void){/* sleep(); */}\r
+void INT_PINT2(void){for( ;; ); /* sleep(); */}\r
 // 83 Interrupt PINT3\r
-void INT_PINT3(void){/* sleep(); */}\r
+void INT_PINT3(void){for( ;; ); /* sleep(); */}\r
 // 84 Interrupt PINT4\r
-void INT_PINT4(void){/* sleep(); */}\r
+void INT_PINT4(void){for( ;; ); /* sleep(); */}\r
 // 85 Interrupt PINT5\r
-void INT_PINT5(void){/* sleep(); */}\r
+void INT_PINT5(void){for( ;; ); /* sleep(); */}\r
 // 86 Interrupt PINT6\r
-void INT_PINT6(void){/* sleep(); */}\r
+void INT_PINT6(void){for( ;; ); /* sleep(); */}\r
 // 87 Interrupt PINT7\r
-void INT_PINT7(void){/* sleep(); */}\r
+void INT_PINT7(void){for( ;; ); /* sleep(); */}\r
 // 88 Reserved\r
 \r
 // 89 Reserved\r
@@ -190,9 +190,9 @@ void INT_PINT7(void){/* sleep(); */}
 // 90 Reserved\r
 \r
 // 91 ROM FIFE\r
-void INT_ROM_FIFE(void){/* sleep(); */}\r
+void INT_ROM_FIFE(void){for( ;; ); /* sleep(); */}\r
 // 92 A/D ADI0\r
-void INT_AD_ADI0(void){/* sleep(); */}\r
+void INT_AD_ADI0(void){for( ;; ); /* sleep(); */}\r
 // 93 Reserved\r
 \r
 // 94 Reserved\r
@@ -200,7 +200,7 @@ void INT_AD_ADI0(void){/* sleep(); */}
 // 95 Reserved\r
 \r
 // 96 A/D ADI1\r
-void INT_AD_ADI1(void){/* sleep(); */}\r
+void INT_AD_ADI1(void){for( ;; ); /* sleep(); */}\r
 // 97 Reserved\r
 \r
 // 98 Reserved\r
@@ -216,79 +216,79 @@ void INT_AD_ADI1(void){/* sleep(); */}
 // 103 Reserved\r
 \r
 // 104 RCANET0 ERS_0\r
-void INT_RCANET0_ERS_0(void){/* sleep(); */}\r
+void INT_RCANET0_ERS_0(void){for( ;; ); /* sleep(); */}\r
 // 105 RCANET0 OVR_0\r
-void INT_RCANET0_OVR_0(void){/* sleep(); */}\r
+void INT_RCANET0_OVR_0(void){for( ;; ); /* sleep(); */}\r
 // 106 RCANET0 RM01_0\r
-void INT_RCANET0_RM01_0(void){/* sleep(); */}\r
+void INT_RCANET0_RM01_0(void){for( ;; ); /* sleep(); */}\r
 // 107 RCANET0 SLE_0\r
-void INT_RCANET0_SLE_0(void){/* sleep(); */}\r
+void INT_RCANET0_SLE_0(void){for( ;; ); /* sleep(); */}\r
 // 108 DMAC0 DEI0\r
-void INT_DMAC0_DEI0(void){/* sleep(); */}\r
+void INT_DMAC0_DEI0(void){for( ;; ); /* sleep(); */}\r
 // 109 DMAC0 HEI0\r
-void INT_DMAC0_HEI0(void){/* sleep(); */}\r
+void INT_DMAC0_HEI0(void){for( ;; ); /* sleep(); */}\r
 // 110 Reserved\r
 \r
 // 111 Reserved\r
 \r
 // 112 DMAC1 DEI1\r
-void INT_DMAC1_DEI1(void){/* sleep(); */}\r
+void INT_DMAC1_DEI1(void){for( ;; ); /* sleep(); */}\r
 // 113 DMAC1 HEI1\r
-void INT_DMAC1_HEI1(void){/* sleep(); */}\r
+void INT_DMAC1_HEI1(void){for( ;; ); /* sleep(); */}\r
 // 114 Reserved\r
 \r
 // 115 Reserved\r
 \r
 // 116 DMAC2 DEI2\r
-void INT_DMAC2_DEI2(void){/* sleep(); */}\r
+void INT_DMAC2_DEI2(void){for( ;; ); /* sleep(); */}\r
 // 117 DMAC2 HEI2\r
-void INT_DMAC2_HEI2(void){/* sleep(); */}\r
+void INT_DMAC2_HEI2(void){for( ;; ); /* sleep(); */}\r
 // 118 Reserved\r
 \r
 // 119 Reserved\r
 \r
 // 120 DMAC3 DEI3\r
-void INT_DMAC3_DEI3(void){/* sleep(); */}\r
+void INT_DMAC3_DEI3(void){for( ;; ); /* sleep(); */}\r
 // 121 DMAC3 HEI3\r
-void INT_DMAC3_HEI3(void){/* sleep(); */}\r
+void INT_DMAC3_HEI3(void){for( ;; ); /* sleep(); */}\r
 // 122 Reserved\r
 \r
 // 123 Reserved\r
 \r
 // 124 DMAC4 DEI4\r
-void INT_DMAC4_DEI4(void){/* sleep(); */}\r
+void INT_DMAC4_DEI4(void){for( ;; ); /* sleep(); */}\r
 // 125 DMAC4 HEI4\r
-void INT_DMAC4_HEI4(void){/* sleep(); */}\r
+void INT_DMAC4_HEI4(void){for( ;; ); /* sleep(); */}\r
 // 126 Reserved\r
 \r
 // 127 Reserved\r
 \r
 // 128 DMAC5 DEI5\r
-void INT_DMAC5_DEI5(void){/* sleep(); */}\r
+void INT_DMAC5_DEI5(void){for( ;; ); /* sleep(); */}\r
 // 129 DMAC5 HEI5\r
-void INT_DMAC5_HEI5(void){/* sleep(); */}\r
+void INT_DMAC5_HEI5(void){for( ;; ); /* sleep(); */}\r
 // 130 Reserved\r
 \r
 // 131 Reserved\r
 \r
 // 132 DMAC6 DEI6\r
-void INT_DMAC6_DEI6(void){/* sleep(); */}\r
+void INT_DMAC6_DEI6(void){for( ;; ); /* sleep(); */}\r
 // 133 DMAC6 HEI6\r
-void INT_DMAC6_HEI6(void){/* sleep(); */}\r
+void INT_DMAC6_HEI6(void){for( ;; ); /* sleep(); */}\r
 // 134 Reserved\r
 \r
 // 135 Reserved\r
 \r
 // 136 DMAC7 DEI7\r
-void INT_DMAC7_DEI7(void){/* sleep(); */}\r
+void INT_DMAC7_DEI7(void){for( ;; ); /* sleep(); */}\r
 // 137 DMAC7 HEI7\r
-void INT_DMAC7_HEI7(void){/* sleep(); */}\r
+void INT_DMAC7_HEI7(void){for( ;; ); /* sleep(); */}\r
 // 138 Reserved\r
 \r
 // 139 Reserved\r
 \r
 // 140 CMT CMI0\r
-void INT_CMT_CMI0(void){/* sleep(); */}\r
+//void INT_CMT_CMI0(void){for( ;; ); /* sleep(); */}\r
 // 141 Reserved\r
 \r
 // 142 Reserved\r
@@ -296,7 +296,7 @@ void INT_CMT_CMI0(void){/* sleep(); */}
 // 143 Reserved\r
 \r
 // 144 CMT CMI1\r
-void INT_CMT_CMI1(void){/* sleep(); */}\r
+void INT_CMT_CMI1(void){for( ;; ); /* sleep(); */}\r
 // 145 Reserved\r
 \r
 // 146 Reserved\r
@@ -304,79 +304,79 @@ void INT_CMT_CMI1(void){/* sleep(); */}
 // 147 Reserved\r
 \r
 // 148 BSC CMTI\r
-void INT_BSC_CMTI(void){/* sleep(); */}\r
+void INT_BSC_CMTI(void){for( ;; ); /* sleep(); */}\r
 // 149 Reserved\r
 \r
 // 150 USB EP4FULL\r
-void INT_USB_EP4FULL(void){/* sleep(); */}\r
+void INT_USB_EP4FULL(void){for( ;; ); /* sleep(); */}\r
 // 151 USB EP5EMPTY\r
-void INT_USB_EP5EMPTY(void){/* sleep(); */}\r
+void INT_USB_EP5EMPTY(void){for( ;; ); /* sleep(); */}\r
 // 152 WDT ITI\r
-void INT_WDT_ITI(void){/* sleep(); */}\r
+void INT_WDT_ITI(void){for( ;; ); /* sleep(); */}\r
 // 153 E-DMAC EINT0\r
-void INT_EDMAC_EINT0(void){/* sleep(); */}\r
+void INT_EDMAC_EINT0(void){for( ;; ); /* sleep(); */}\r
 // 154 USB EP1FULL\r
-void INT_USB_EP1FULL(void){/* sleep(); */}\r
+void INT_USB_EP1FULL(void){for( ;; ); /* sleep(); */}\r
 // 155 USB EP2EMPTY\r
-void INT_USB_EP2EMPTY(void){/* sleep(); */}\r
+void INT_USB_EP2EMPTY(void){for( ;; ); /* sleep(); */}\r
 // 156 MTU2 MTU0 TGI0A\r
-void INT_MTU2_MTU0_TGI0A(void){/* sleep(); */}\r
+void INT_MTU2_MTU0_TGI0A(void){for( ;; ); /* sleep(); */}\r
 // 157 MTU2 MTU0 TGI0B\r
-void INT_MTU2_MTU0_TGI0B(void){/* sleep(); */}\r
+void INT_MTU2_MTU0_TGI0B(void){for( ;; ); /* sleep(); */}\r
 // 158 MTU2 MTU0 TGI0C\r
-void INT_MTU2_MTU0_TGI0C(void){/* sleep(); */}\r
+void INT_MTU2_MTU0_TGI0C(void){for( ;; ); /* sleep(); */}\r
 // 159 MTU2 MTU0 TGI0D\r
-void INT_MTU2_MTU0_TGI0D(void){/* sleep(); */}\r
+void INT_MTU2_MTU0_TGI0D(void){for( ;; ); /* sleep(); */}\r
 // 160 MTU2 MTU0 TGI0V\r
-void INT_MTU2_MTU0_TGI0V(void){/* sleep(); */}\r
+void INT_MTU2_MTU0_TGI0V(void){for( ;; ); /* sleep(); */}\r
 // 161 MTU2 MTU0 TGI0E\r
-void INT_MTU2_MTU0_TGI0E(void){/* sleep(); */}\r
+void INT_MTU2_MTU0_TGI0E(void){for( ;; ); /* sleep(); */}\r
 // 162 MTU2 MTU0 TGI0F\r
-void INT_MTU2_MTU0_TGI0F(void){/* sleep(); */}\r
+void INT_MTU2_MTU0_TGI0F(void){for( ;; ); /* sleep(); */}\r
 // 163 Reserved\r
 \r
 // 164 MTU2 MTU1 TGI1A\r
-void INT_MTU2_MTU1_TGI1A(void){/* sleep(); */}\r
+void INT_MTU2_MTU1_TGI1A(void){for( ;; ); /* sleep(); */}\r
 // 165 MTU2 MTU1 TGI1B\r
-void INT_MTU2_MTU1_TGI1B(void){/* sleep(); */}\r
+void INT_MTU2_MTU1_TGI1B(void){for( ;; ); /* sleep(); */}\r
 // 166 Reserved \r
 \r
 // 167 Reserved\r
 \r
 // 168 MTU2 MTU1 TGI1V\r
-void INT_MTU2_MTU1_TGI1V(void){/* sleep(); */}\r
+void INT_MTU2_MTU1_TGI1V(void){for( ;; ); /* sleep(); */}\r
 // 169 MTU2 MTU1 TGI1U\r
-void INT_MTU2_MTU1_TGI1U(void){/* sleep(); */}\r
+void INT_MTU2_MTU1_TGI1U(void){for( ;; ); /* sleep(); */}\r
 // 170 Reserved \r
 \r
 // 171 Reserved\r
 \r
 // 172 MTU2 MTU2 TGI2A\r
-void INT_MTU2_MTU2_TGI2A(void){/* sleep(); */}\r
+void INT_MTU2_MTU2_TGI2A(void){for( ;; ); /* sleep(); */}\r
 // 173 MTU2 MTU2 TGI2B\r
-void INT_MTU2_MTU2_TGI2B(void){/* sleep(); */}\r
+void INT_MTU2_MTU2_TGI2B(void){for( ;; ); /* sleep(); */}\r
 // 174 Reserved \r
 \r
 // 175 Reserved\r
 \r
 // 176 MTU2 MTU2 TGI2V\r
-void INT_MTU2_MTU2_TGI2V(void){/* sleep(); */}\r
+void INT_MTU2_MTU2_TGI2V(void){for( ;; ); /* sleep(); */}\r
 // 177 MTU2 MTU2 TGI2U\r
-void INT_MTU2_MTU2_TGI2U(void){/* sleep(); */}\r
+void INT_MTU2_MTU2_TGI2U(void){for( ;; ); /* sleep(); */}\r
 // 178 Reserved \r
 \r
 // 179 Reserved\r
 \r
 // 180 MTU2 MTU3 TGI3A\r
-void INT_MTU2_MTU3_TGI3A(void){/* sleep(); */}\r
+void INT_MTU2_MTU3_TGI3A(void){for( ;; ); /* sleep(); */}\r
 // 181 MTU2 MTU3 TGI3B\r
-void INT_MTU2_MTU3_TGI3B(void){/* sleep(); */}\r
+void INT_MTU2_MTU3_TGI3B(void){for( ;; ); /* sleep(); */}\r
 // 182 MTU2 MTU3 TGI3C\r
-void INT_MTU2_MTU3_TGI3C(void){/* sleep(); */}\r
+void INT_MTU2_MTU3_TGI3C(void){for( ;; ); /* sleep(); */}\r
 // 183 MTU2 MTU3 TGI3D\r
-void INT_MTU2_MTU3_TGI3D(void){/* sleep(); */}\r
+void INT_MTU2_MTU3_TGI3D(void){for( ;; ); /* sleep(); */}\r
 // 184 MTU2 MTU3 TGI3V\r
-void INT_MTU2_MTU3_TGI3V(void){/* sleep(); */}\r
+void INT_MTU2_MTU3_TGI3V(void){for( ;; ); /* sleep(); */}\r
 // 185 Reserved \r
 \r
 // 186 Reserved\r
@@ -384,15 +384,15 @@ void INT_MTU2_MTU3_TGI3V(void){/* sleep(); */}
 // 187 Reserved \r
 \r
 // 188 MTU2 MTU4 TGI4A\r
-void INT_MTU2_MTU4_TGI4A(void){/* sleep(); */}\r
+void INT_MTU2_MTU4_TGI4A(void){for( ;; ); /* sleep(); */}\r
 // 189 MTU2 MTU4 TGI4B\r
-void INT_MTU2_MTU4_TGI4B(void){/* sleep(); */}\r
+void INT_MTU2_MTU4_TGI4B(void){for( ;; ); /* sleep(); */}\r
 // 190 MTU2 MTU4 TGI4C\r
-void INT_MTU2_MTU4_TGI4C(void){/* sleep(); */}\r
+void INT_MTU2_MTU4_TGI4C(void){for( ;; ); /* sleep(); */}\r
 // 191 MTU2 MTU4 TGI4D\r
-void INT_MTU2_MTU4_TGI4D(void){/* sleep(); */}\r
+void INT_MTU2_MTU4_TGI4D(void){for( ;; ); /* sleep(); */}\r
 // 192 MTU2 MTU4 TGI4V\r
-void INT_MTU2_MTU4_TGI4V(void){/* sleep(); */}\r
+void INT_MTU2_MTU4_TGI4V(void){for( ;; ); /* sleep(); */}\r
 // 193 Reserved \r
 \r
 // 194 Reserved\r
@@ -400,31 +400,31 @@ void INT_MTU2_MTU4_TGI4V(void){/* sleep(); */}
 // 195 Reserved \r
 \r
 // 196 MTU2 MTU5 TGI5U\r
-void INT_MTU2_MTU5_TGI5U(void){/* sleep(); */}\r
+void INT_MTU2_MTU5_TGI5U(void){for( ;; ); /* sleep(); */}\r
 // 197 MTU2 MTU5 TGI5V\r
-void INT_MTU2_MTU5_TGI5V(void){/* sleep(); */}\r
+void INT_MTU2_MTU5_TGI5V(void){for( ;; ); /* sleep(); */}\r
 // 198 MTU2 MTU5 TGI5W\r
-void INT_MTU2_MTU5_TGI5W(void){/* sleep(); */}\r
+void INT_MTU2_MTU5_TGI5W(void){for( ;; ); /* sleep(); */}\r
 // 199 Reserved \r
 \r
 // 200 POE2 OEI1\r
-void INT_POE2_OEI1(void){/* sleep(); */}\r
+void INT_POE2_OEI1(void){for( ;; ); /* sleep(); */}\r
 // 201 POE2 OEI2 \r
-void INT_POE2_OEI2(void){/* sleep(); */}\r
+void INT_POE2_OEI2(void){for( ;; ); /* sleep(); */}\r
 // 202 Reserved \r
 \r
 // 203 Reserved\r
 \r
 // 204 MTU2S MTU3S TGI3A \r
-void INT_MTU2S_MTU3S_TGI3A(void){/* sleep(); */}\r
+void INT_MTU2S_MTU3S_TGI3A(void){for( ;; ); /* sleep(); */}\r
 // 205 MTU2S MTU3S TGI3B\r
-void INT_MTU2S_MTU3S_TGI3B(void){/* sleep(); */}\r
+void INT_MTU2S_MTU3S_TGI3B(void){for( ;; ); /* sleep(); */}\r
 // 206 MTU2S MTU3S TGI3C\r
-void INT_MTU2S_MTU3S_TGI3C(void){/* sleep(); */}\r
+void INT_MTU2S_MTU3S_TGI3C(void){for( ;; ); /* sleep(); */}\r
 // 207 MTU2S MTU3S TGI3D \r
-void INT_MTU2S_MTU3S_TGI3D(void){/* sleep(); */}\r
+void INT_MTU2S_MTU3S_TGI3D(void){for( ;; ); /* sleep(); */}\r
 // 208 MTU2S MTU3S TGI3V\r
-void INT_MTU2S_MTU3S_TGI3V(void){/* sleep(); */}\r
+void INT_MTU2S_MTU3S_TGI3V(void){for( ;; ); /* sleep(); */}\r
 // 209 Reserved \r
 \r
 // 210 Reserved \r
@@ -432,15 +432,15 @@ void INT_MTU2S_MTU3S_TGI3V(void){/* sleep(); */}
 // 211 Reserved\r
 \r
 // 212 MTU2S MTU4S TGI4A \r
-void INT_MTU2S_MTU4S_TGI4A(void){/* sleep(); */}\r
+void INT_MTU2S_MTU4S_TGI4A(void){for( ;; ); /* sleep(); */}\r
 // 213 MTU2S MTU4S TGI4B \r
-void INT_MTU2S_MTU4S_TGI4B(void){/* sleep(); */}\r
+void INT_MTU2S_MTU4S_TGI4B(void){for( ;; ); /* sleep(); */}\r
 // 214 MTU2S MTU4S TGI4C \r
-void INT_MTU2S_MTU4S_TGI4C(void){/* sleep(); */}\r
+void INT_MTU2S_MTU4S_TGI4C(void){for( ;; ); /* sleep(); */}\r
 // 215 MTU2S MTU4S TGI4D \r
-void INT_MTU2S_MTU4S_TGI4D(void){/* sleep(); */}\r
+void INT_MTU2S_MTU4S_TGI4D(void){for( ;; ); /* sleep(); */}\r
 // 216 MTU2S MTU4S TGI4V \r
-void INT_MTU2S_MTU4S_TGI4V(void){/* sleep(); */}\r
+void INT_MTU2S_MTU4S_TGI4V(void){for( ;; ); /* sleep(); */}\r
 // 217 Reserved \r
 \r
 // 218 Reserved\r
@@ -448,78 +448,78 @@ void INT_MTU2S_MTU4S_TGI4V(void){/* sleep(); */}
 // 219 Reserved \r
 \r
 // 220 MTU2S MTU5S TGI5U \r
-void INT_MTU2S_MTU5S_TGI5U(void){/* sleep(); */}\r
+void INT_MTU2S_MTU5S_TGI5U(void){for( ;; ); /* sleep(); */}\r
 // 221 MTU2S MTU5S TGI5V\r
-void INT_MTU2S_MTU5S_TGI5V(void){/* sleep(); */}\r
+void INT_MTU2S_MTU5S_TGI5V(void){for( ;; ); /* sleep(); */}\r
 // 222 MTU2S MTU5S TGI5W \r
-void INT_MTU2S_MTU5S_TGI5W(void){/* sleep(); */}\r
+void INT_MTU2S_MTU5S_TGI5W(void){for( ;; ); /* sleep(); */}\r
 // 223 Reserved\r
 \r
 // 224 POE2 OEI3\r
-void INT_POE2_OEI3(void){/* sleep(); */}\r
+void INT_POE2_OEI3(void){for( ;; ); /* sleep(); */}\r
 // 225 Reserved\r
 \r
 // 226 USB USI0\r
-void INT_USB_USI0(void){/* sleep(); */}\r
+void INT_USB_USI0(void){for( ;; ); /* sleep(); */}\r
 // 227 USB USI1\r
-void INT_USB_USI1(void){/* sleep(); */}\r
+void INT_USB_USI1(void){for( ;; ); /* sleep(); */}\r
 // 228 IIC3 STPI\r
-void INT_IIC3_STPI(void){/* sleep(); */}\r
+void INT_IIC3_STPI(void){for( ;; ); /* sleep(); */}\r
 // 229 IIC3 NAKI \r
-void INT_IIC3_NAKI(void){/* sleep(); */}\r
+void INT_IIC3_NAKI(void){for( ;; ); /* sleep(); */}\r
 // 230 IIC3 RXI \r
-void INT_IIC3_RXI(void){/* sleep(); */}\r
+void INT_IIC3_RXI(void){for( ;; ); /* sleep(); */}\r
 // 231 IIC3 TXI\r
-void INT_IIC3_TXI(void){/* sleep(); */}\r
+void INT_IIC3_TXI(void){for( ;; ); /* sleep(); */}\r
 // 232 IIC3 TEI \r
-void INT_IIC3_TEI(void){/* sleep(); */}\r
+void INT_IIC3_TEI(void){for( ;; ); /* sleep(); */}\r
 // 233 RSPI SPERI\r
-void INT_RSPI_SPERI(void){/* sleep(); */}\r
+void INT_RSPI_SPERI(void){for( ;; ); /* sleep(); */}\r
 // 234 RSPI SPRXI\r
-void INT_RSPI_SPRXI(void){/* sleep(); */}\r
+void INT_RSPI_SPRXI(void){for( ;; ); /* sleep(); */}\r
 // 235 RSPI SPTXI\r
-void INT_RSPI_SPTXI(void){/* sleep(); */}\r
+void INT_RSPI_SPTXI(void){for( ;; ); /* sleep(); */}\r
 // 236 SCI SCI4 ERI4\r
-void INT_SCI_SCI4_ERI4(void){/* sleep(); */}\r
+void INT_SCI_SCI4_ERI4(void){for( ;; ); /* sleep(); */}\r
 // 237 SCI SCI4 RXI4\r
-void INT_SCI_SCI4_RXI4(void){/* sleep(); */}\r
+void INT_SCI_SCI4_RXI4(void){for( ;; ); /* sleep(); */}\r
 // 238 SCI SCI4 TXI4\r
-void INT_SCI_SCI4_TXI4(void){/* sleep(); */}\r
+void INT_SCI_SCI4_TXI4(void){for( ;; ); /* sleep(); */}\r
 // 239 SCI SCI4 TEI4\r
-void INT_SCI_SCI4_TEI4(void){/* sleep(); */}\r
+void INT_SCI_SCI4_TEI4(void){for( ;; ); /* sleep(); */}\r
 // 240 SCI SCI0 ERI0\r
-void INT_SCI_SCI0_ERI0(void){/* sleep(); */}\r
+void INT_SCI_SCI0_ERI0(void){for( ;; ); /* sleep(); */}\r
 // 241 SCI SCI0 RXI0\r
-void INT_SCI_SCI0_RXI0(void){/* sleep(); */}\r
+void INT_SCI_SCI0_RXI0(void){for( ;; ); /* sleep(); */}\r
 // 242 SCI SCI0 TXI0\r
-void INT_SCI_SCI0_TXI0(void){/* sleep(); */}\r
+void INT_SCI_SCI0_TXI0(void){for( ;; ); /* sleep(); */}\r
 // 243 SCI SCI0 TEI0\r
-void INT_SCI_SCI0_TEI0(void){/* sleep(); */}\r
+void INT_SCI_SCI0_TEI0(void){for( ;; ); /* sleep(); */}\r
 // 244 SCI SCI1 ERI1\r
-void INT_SCI_SCI1_ERI1(void){/* sleep(); */}\r
+void INT_SCI_SCI1_ERI1(void){for( ;; ); /* sleep(); */}\r
 // 245 SCI SCI1 RXI1\r
-void INT_SCI_SCI1_RXI1(void){/* sleep(); */}\r
+void INT_SCI_SCI1_RXI1(void){for( ;; ); /* sleep(); */}\r
 // 246 SCI SCI1 TXI1\r
-void INT_SCI_SCI1_TXI1(void){/* sleep(); */}\r
+void INT_SCI_SCI1_TXI1(void){for( ;; ); /* sleep(); */}\r
 // 247 SCI SCI1 TEI1\r
-void INT_SCI_SCI1_TEI1(void){/* sleep(); */}\r
+void INT_SCI_SCI1_TEI1(void){for( ;; ); /* sleep(); */}\r
 // 248 SCI SCI2 ERI2\r
-void INT_SCI_SCI2_ERI2(void){/* sleep(); */}\r
+void INT_SCI_SCI2_ERI2(void){for( ;; ); /* sleep(); */}\r
 // 249 SCI SCI2 RXI2\r
-void INT_SCI_SCI2_RXI2(void){/* sleep(); */}\r
+void INT_SCI_SCI2_RXI2(void){for( ;; ); /* sleep(); */}\r
 // 250 SCI SCI2 TXI2\r
-void INT_SCI_SCI2_TXI2(void){/* sleep(); */}\r
+void INT_SCI_SCI2_TXI2(void){for( ;; ); /* sleep(); */}\r
 // 251 SCI SCI2 TEI2\r
-void INT_SCI_SCI2_TEI2(void){/* sleep(); */}\r
+void INT_SCI_SCI2_TEI2(void){for( ;; ); /* sleep(); */}\r
 // 252 SCIF SCIF3 BRI3\r
-void INT_SCIF_SCIF3_BRI3(void){/* sleep(); */}\r
+void INT_SCIF_SCIF3_BRI3(void){for( ;; ); /* sleep(); */}\r
 // 253 SCIF SCIF3 ERI3\r
-void INT_SCIF_SCIF3_ERI3(void){/* sleep(); */}\r
+void INT_SCIF_SCIF3_ERI3(void){for( ;; ); /* sleep(); */}\r
 // 254 SCIF SCIF3 RXI3\r
-void INT_SCIF_SCIF3_RXI3(void){/* sleep(); */}\r
+void INT_SCIF_SCIF3_RXI3(void){for( ;; ); /* sleep(); */}\r
 // 255 SCIF SCIF3 TXI3\r
-void INT_SCIF_SCIF3_TXI3(void){/* sleep(); */}\r
+void INT_SCIF_SCIF3_TXI3(void){for( ;; ); /* sleep(); */}\r
 // Dummy\r
-void Dummy(void){/* sleep(); */}\r
+void Dummy(void){ for( ;; ); sleep(); }\r
 \r
 /* End of File */\r
diff --git a/Demo/SuperH_SH7216_Renesas/RTOSDemo/main.c b/Demo/SuperH_SH7216_Renesas/RTOSDemo/main.c
index bc5e76c36f74398f0285b06109252ee5c5b973c3..758a85cacca0db6b3ecc0378f855a4790c7e6cab 100644 (file)
--- a/Demo/SuperH_SH7216_Renesas/RTOSDemo/main.c
+++ b/Demo/SuperH_SH7216_Renesas/RTOSDemo/main.c
@@ -62,14 +62,22 @@ void vApplicationMallocFailedHook( void );
 void vApplicationIdleHook( void );\r
 static void prvSetupHardware( void );\r
 \r
+extern void vRegTest1Task( void *pvParameters );\r
+extern void vRegTest2Task( void *pvParameters );\r
+\r
+unsigned long ulRegTest1CycleCount = 0UL, ulRegTest2CycleCount = 0UL;\r
+\r
 /*-----------------------------------------------------------*/\r
 \r
 void main(void)\r
 {\r
        prvSetupHardware();\r
-       \r
+\r
+       xTaskCreate( vRegTest1Task, "RegTest1", configMINIMAL_STACK_SIZE, ( void * ) 0x12345678UL, 1, NULL );\r
+       xTaskCreate( vRegTest2Task, "RegTest2", configMINIMAL_STACK_SIZE, ( void * ) 0x11223344UL, 1, NULL );\r
+        \r
        vTaskStartScheduler();\r
-       taskENABLE_INTERRUPTS();\r
+\r
        for( ;; );\r
 }\r
 /*-----------------------------------------------------------*/\r
@@ -146,15 +154,26 @@ unsigned long ulCompareMatch = ( configPERIPHERAL_CLOCK_HZ / ( configTICK_RATE_H
 }\r
 /*-----------------------------------------------------------*/\r
 \r
-//#pragma interrupt (vTempISR)\r
-//void vTempISR( void );\r
-\r
-void xINT_CMT_CMI0( void )\r
+void INT_CMT_CMI0( void )\r
 {\r
-       CMT0.CMCSR.BIT.CMF = 0;\r
-}\r
-\r
-\r
+static unsigned long ul = 0;\r
 \r
+       ul++;\r
+       if( ul >= 1000 )\r
+       {\r
+               if( PE.DR.WORD & ( 0x01 << 9 ) )\r
+               {\r
+                       PE.DR.WORD &= ~( 0x01 << 9 );\r
+               }\r
+               else\r
+               {\r
+                       PE.DR.WORD |= ( 0x01 << 9 );\r
+               }\r
+               \r
+               ul = 0;\r
+       }\r
 \r
+       CMT0.CMCSR.BIT.CMF = 0;\r
+}\r
+/*-----------------------------------------------------------*/\r
 \r
diff --git a/Demo/SuperH_SH7216_Renesas/RTOSDemo/regtest.src b/Demo/SuperH_SH7216_Renesas/RTOSDemo/regtest.src
new file mode 100644 (file)
index 0000000..0cf566d
--- /dev/null
+++ b/Demo/SuperH_SH7216_Renesas/RTOSDemo/regtest.src
@@ -0,0 +1,176 @@
+;/*\r
+;    FreeRTOS V6.0.1 - Copyright (C) 2009 Real Time Engineers Ltd.\r
+;\r
+;    ***************************************************************************\r
+;    *                                                                         *\r
+;    * If you are:                                                             *\r
+;    *                                                                         *\r
+;    *    + New to FreeRTOS,                                                   *\r
+;    *    + Wanting to learn FreeRTOS or multitasking in general quickly       *\r
+;    *    + Looking for basic training,                                        *\r
+;    *    + Wanting to improve your FreeRTOS skills and productivity           *\r
+;    *                                                                         *\r
+;    * then take a look at the FreeRTOS eBook                                  *\r
+;    *                                                                         *\r
+;    *        "Using the FreeRTOS Real Time Kernel - a Practical Guide"        *\r
+;    *                  http://www.FreeRTOS.org/Documentation                  *\r
+;    *                                                                         *\r
+;    * A pdf reference manual is also available.  Both are usually delivered   *\r
+;    * to your inbox within 20 minutes to two hours when purchased between 8am *\r
+;    * and 8pm GMT (although please allow up to 24 hours in case of            *\r
+;    * exceptional circumstances).  Thank you for your support!                *\r
+;    *                                                                         *\r
+;    ***************************************************************************\r
+;\r
+;    This file is part of the FreeRTOS distribution.\r
+;\r
+;    FreeRTOS is free software; you can redistribute it and/or modify it under\r
+;    the terms of the GNU General Public License (version 2) as published by the\r
+;    Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+;    ***NOTE*** The exception to the GPL is included to allow you to distribute\r
+;    a combined work that includes FreeRTOS without being obliged to provide the\r
+;    source code for proprietary components outside of the FreeRTOS kernel.\r
+;    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT\r
+;    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\r
+;    FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\r
+;    more details. You should have received a copy of the GNU General Public \r
+;    License and the FreeRTOS license exception along with FreeRTOS; if not it \r
+;    can be viewed here: http://www.freertos.org/a00114.html and also obtained \r
+;    by writing to Richard Barry, contact details for whom are available on the\r
+;    FreeRTOS WEB site.\r
+;\r
+;    1 tab == 4 spaces!\r
+;\r
+;    http://www.FreeRTOS.org - Documentation, latest information, license and\r
+;    contact details.\r
+;\r
+;    http://www.SafeRTOS.com - A version that is certified for use in safety\r
+;    critical systems.\r
+;\r
+;    http://www.OpenRTOS.com - Commercial support, development, porting,\r
+;    licensing and training services.\r
+;*/\r
+\r
+       .import _pxCurrentTCB\r
+       .import _vTaskSwitchContext\r
+       .import _ulRegTest1CycleCount\r
+       .import _ulRegTest2CycleCount\r
+\r
+       .export _vRegTest1Task\r
+       .export _vRegTest2Task\r
+\r
+    .section    P\r
+       \r
+_vRegTest1Task:\r
+\r
+       mov             #3, r2\r
+       mov             #4, r3\r
+       mov             #5, r4\r
+       mov             #6, r5\r
+       mov             #7, r6\r
+       mov             #8, r7\r
+       mov             #9, r8\r
+       mov             #10, r9\r
+       mov             #11, r10\r
+       mov             #12, r11\r
+       mov             #13, r12\r
+       mov             #14, r13\r
+\r
+       mov             #15, r0\r
+       lds             r0, macl\r
+       mov             #16, r0\r
+       lds             r0, mach\r
+       mov             #17, r0\r
+       ldc             r0, gbr\r
+       \r
+_vRegTest1Loop:\r
+\r
+       ; Reset r1 which was used in the tests.\r
+       mov             #2, r1\r
+       \r
+       mov             #2, r0\r
+       cmp/eq  r0, r1\r
+       bf              _vRegTestError\r
+       \r
+       mov             #3, r0\r
+       cmp/eq  r0, r2\r
+       bf              _vRegTestError\r
+\r
+       mov             #4, r0\r
+       cmp/eq  r0, r3\r
+       bf              _vRegTestError\r
+\r
+       mov             #5, r0\r
+       cmp/eq  r0, r4\r
+       bf              _vRegTestError\r
+\r
+       mov             #6, r0\r
+       cmp/eq  r0, r5\r
+       bf              _vRegTestError\r
+\r
+       mov             #7, r0\r
+       cmp/eq  r0, r6\r
+       bf              _vRegTestError\r
+\r
+       mov             #8, r0\r
+       cmp/eq  r0, r7\r
+       bf              _vRegTestError\r
+\r
+       mov             #9, r0\r
+       cmp/eq  r0, r8\r
+       bf              _vRegTestError\r
+\r
+       mov             #10, r0\r
+       cmp/eq  r0, r9\r
+       bf              _vRegTestError\r
+\r
+       mov             #11, r0\r
+       cmp/eq  r0, r10\r
+       bf              _vRegTestError\r
+\r
+       mov             #12, r0\r
+       cmp/eq  r0, r11\r
+       bf              _vRegTestError\r
+\r
+       mov             #13, r0\r
+       cmp/eq  r0, r12\r
+       bf              _vRegTestError\r
+\r
+       mov             #14, r0\r
+       cmp/eq  r0, r13\r
+       bf              _vRegTestError\r
+\r
+       sts             macl, r0\r
+       mov             #15, r1\r
+       cmp/eq  r0, r1\r
+       bf              _vRegTestError\r
+\r
+       sts             mach, r0\r
+       mov             #16, r1\r
+       cmp/eq  r0, r1\r
+       bf              _vRegTestError\r
+\r
+       stc             gbr, r0\r
+       mov             #17, r1\r
+       cmp/eq  r0, r1\r
+       bf              _vRegTestError\r
+\r
+       mov.l   #_ulRegTest1CycleCount, r0\r
+       mov.l   @r0, r1\r
+       add             #1, r1\r
+       mov.l   r1, @r0\r
+\r
+       bra             _vRegTest1Task\r
+       nop\r
+\r
+_vRegTest2Task:\r
+\r
+       trapa   #33\r
+       bra             _vRegTest2Task\r
+       nop\r
+       \r
+_vRegTestError:\r
+       bra             _vRegTestError\r
+\r
+       .end\r
+               \r
diff --git a/Demo/SuperH_SH7216_Renesas/RTOSDemo/vecttbl.c b/Demo/SuperH_SH7216_Renesas/RTOSDemo/vecttbl.c
index 5fb4e35e686598b192febf33bb1ee446facd7821..a0f18d465e80222055d557f9b626362b03b8ad87 100644 (file)
--- a/Demo/SuperH_SH7216_Renesas/RTOSDemo/vecttbl.c
+++ b/Demo/SuperH_SH7216_Renesas/RTOSDemo/vecttbl.c
@@ -13,6 +13,9 @@
 \r
 #include "vect.h"\r
 \r
+extern void vPortStartFirstTask( void );\r
+extern void vPortYield( void );\r
+\r
 #pragma section VECTTBL\r
 \r
 void *RESET_Vectors[] = {\r
@@ -89,9 +92,11 @@ void *INT_Vectors[] = {
 // 31 Reserved\r
     (void*) Dummy,\r
 // 32 TRAPA (User Vecter)\r
-    (void*) INT_TRAPA32,\r
+//   (void*) INT_TRAPA32,\r
+       (void*) vPortStartFirstTask,\r
 // 33 TRAPA (User Vecter)\r
-    (void*) INT_TRAPA33,\r
+//    (void*) INT_TRAPA33,\r
+       (void*) vPortYield,\r
 // 34 TRAPA (User Vecter)\r
     (void*) INT_TRAPA34,\r
 // 35 TRAPA (User Vecter)\r
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