# STM32f0x stlink pseudo target
#
-set CHIPNAME stm32f0x
-set CPUTAPID 0x0BB11477
-set WORKAREASIZE 0x400
+if { [info exists CHIPNAME] == 0 } {
+ set CHIPNAME stm32f0x
+}
+
+if { [info exists CPUTAPID] == 0 } {
+ set CPUTAPID 0x0bb11477
+}
+
+if { [info exists WORKAREASIZE] == 0 } {
+ set WORKAREASIZE 0x400
+}
source [find target/stm32_stlink.cfg]
# STM32f1x stlink pseudo target
#
-set CHIPNAME stm32f1x
-set CPUTAPID 0x1ba01477
-set WORKAREASIZE 0x4000
+if { [info exists CHIPNAME] == 0 } {
+ set CHIPNAME stm32f1x
+}
+
+if { [info exists CPUTAPID] == 0 } {
+ set CPUTAPID 0x1ba01477
+}
+
+if { [info exists WORKAREASIZE] == 0 } {
+ set WORKAREASIZE 0x4000
+}
source [find target/stm32_stlink.cfg]
# STM32f2x stlink pseudo target
#
-set CHIPNAME stm32f2x
-set CPUTAPID 0x2ba01477
-set WORKAREASIZE 0x10000
+if { [info exists CHIPNAME] == 0 } {
+ set CHIPNAME stm32f2x
+}
+
+if { [info exists CPUTAPID] == 0 } {
+ set CPUTAPID 0x2ba01477
+}
+
+if { [info exists WORKAREASIZE] == 0 } {
+ set WORKAREASIZE 0x10000
+}
source [find target/stm32_stlink.cfg]
# STM32f4x stlink pseudo target
#
-set CHIPNAME stm32f4x
-set CPUTAPID 0x2ba01477
-set WORKAREASIZE 0x10000
+if { [info exists CHIPNAME] == 0 } {
+ set CHIPNAME stm32f4x
+}
+
+if { [info exists CPUTAPID] == 0 } {
+ set CPUTAPID 0x2ba01477
+}
+
+if { [info exists WORKAREASIZE] == 0 } {
+ set WORKAREASIZE 0x10000
+}
source [find target/stm32_stlink.cfg]
# STM32lx stlink pseudo target
#
-set CHIPNAME stm32lx
-set CPUTAPID 0x2ba01477
-set WORKAREASIZE 0x3800
+if { [info exists CHIPNAME] == 0 } {
+ set CHIPNAME stm32lx
+}
+
+if { [info exists CPUTAPID] == 0 } {
+ set CPUTAPID 0x2ba01477
+}
+
+if { [info exists WORKAREASIZE] == 0 } {
+ set WORKAREASIZE 0x3800
+}
source [find target/stm32_stlink.cfg]