--- /dev/null
+/*\r
+ FreeRTOS.org V5.1.0 - Copyright (C) 2003-2008 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS.org distribution.\r
+\r
+ FreeRTOS.org is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS.org is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS.org; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS.org, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section\r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ ***************************************************************************\r
+ * *\r
+ * SAVE TIME AND MONEY! We can port FreeRTOS.org to your own hardware, *\r
+ * and even write all or part of your application on your behalf. *\r
+ * See http://www.OpenRTOS.com for details of the services we provide to *\r
+ * expedite your project. *\r
+ * *\r
+ ***************************************************************************\r
+ ***************************************************************************\r
+\r
+ Please ensure to read the configuration and relevant port sections of the\r
+ online documentation.\r
+\r
+ http://www.FreeRTOS.org - Documentation, latest information, license and\r
+ contact details.\r
+\r
+ http://www.SafeRTOS.com - A version that is certified for use in safety\r
+ critical systems.\r
+\r
+ http://www.OpenRTOS.com - Commercial support, development, porting,\r
+ licensing and training services.\r
+*/\r
+\r
+#ifndef FREERTOS_CONFIG_H\r
+#define FREERTOS_CONFIG_H\r
+\r
+/* Library includes. */\r
+#include "common.h"\r
+\r
+/*-----------------------------------------------------------\r
+ * Application specific definitions.\r
+ *\r
+ * These definitions should be adjusted for your particular hardware and\r
+ * application requirements.\r
+ *\r
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\r
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. \r
+ *\r
+ * See http://www.freertos.org/a00110.html.\r
+ *----------------------------------------------------------*/\r
+\r
+#define configUSE_PREEMPTION 1\r
+#define configUSE_IDLE_HOOK 0\r
+#define configUSE_TICK_HOOK 0\r
+#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 80000000 )\r
+#define configTICK_RATE_HZ ( ( portTickType ) 100 )\r
+#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 160 )\r
+#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 30 * 1024 ) )\r
+#define configMAX_TASK_NAME_LEN ( 12 )\r
+#define configUSE_TRACE_FACILITY 1\r
+#define configUSE_16_BIT_TICKS 0\r
+#define configIDLE_SHOULD_YIELD 0\r
+#define configUSE_CO_ROUTINES 0\r
+#define configUSE_MUTEXES 1\r
+#define configCHECK_FOR_STACK_OVERFLOW 2\r
+#define configUSE_RECURSIVE_MUTEXES 1\r
+#define configQUEUE_REGISTRY_SIZE 0\r
+#define configUSE_COUNTING_SEMAPHORES 0\r
+\r
+#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 6 )\r
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )\r
+\r
+/* Set the following definitions to 1 to include the API function, or zero\r
+to exclude the API function. */\r
+\r
+#define INCLUDE_vTaskPrioritySet 1\r
+#define INCLUDE_uxTaskPriorityGet 1\r
+#define INCLUDE_vTaskDelete 1\r
+#define INCLUDE_vTaskCleanUpResources 0\r
+#define INCLUDE_vTaskSuspend 1\r
+#define INCLUDE_vTaskDelayUntil 1\r
+#define INCLUDE_vTaskDelay 1\r
+#define INCLUDE_uxTaskGetStackHighWaterMark 1\r
+\r
+#define configYIELD_INTERRUPT_VECTOR 16UL\r
+#define configKERNEL_INTERRUPT_PRIORITY 1\r
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY 4\r
+\r
+void vApplicationSetupInterrupts( void );\r
+\r
+/* Ethernet configuration. */\r
+#define configMAC_0 0x00\r
+#define configMAC_1 0x04\r
+#define configMAC_2 0x9F\r
+#define configMAC_3 0x00\r
+#define configMAC_4 0xAB\r
+#define configMAC_5 0x2B\r
+\r
+#define configIP_ADDR0 192\r
+#define configIP_ADDR1 168\r
+#define configIP_ADDR2 0\r
+#define configIP_ADDR3 11\r
+\r
+#define configGW_ADDR0 172\r
+#define configGW_ADDR1 25\r
+#define configGW_ADDR2 218\r
+#define configGW_ADDR3 3\r
+\r
+#define configNET_MASK0 255\r
+#define configNET_MASK1 255\r
+#define configNET_MASK2 255\r
+#define configNET_MASK3 0\r
+\r
+#define configNUM_FEC_TX_BUFFERS 2\r
+#define configNUM_FEC_RX_BUFFERS 4\r
+#define configFEC_BUFFER_SIZE 1520\r
+#define configUSE_PROMISCUOUS_MODE 0\r
+#define configETHERNET_INPUT_TASK_STACK_SIZE ( 320 )\r
+#define configETHERNET_INPUT_TASK_PRIORITY ( configMAX_PRIORITIES - 1 )\r
+\r
+#define configPHY_ADDRESS 1\r
+\r
+#if ( configFEC_BUFFER_SIZE & 0x0F ) != 0\r
+ #error configFEC_BUFFER_SIZE must be a multiple of 16.\r
+#endif\r
+\r
+#endif /* FREERTOS_CONFIG_H */\r
--- /dev/null
+/*\r
+ FreeRTOS.org V5.1.0 - Copyright (C) 2003-2008 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS.org distribution.\r
+\r
+ FreeRTOS.org is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS.org is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS.org; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS.org, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section\r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ ***************************************************************************\r
+ * *\r
+ * SAVE TIME AND MONEY! We can port FreeRTOS.org to your own hardware, *\r
+ * and even write all or part of your application on your behalf. *\r
+ * See http://www.OpenRTOS.com for details of the services we provide to *\r
+ * expedite your project. *\r
+ * *\r
+ ***************************************************************************\r
+ ***************************************************************************\r
+\r
+ Please ensure to read the configuration and relevant port sections of the\r
+ online documentation.\r
+\r
+ http://www.FreeRTOS.org - Documentation, latest information, license and\r
+ contact details.\r
+\r
+ http://www.SafeRTOS.com - A version that is certified for use in safety\r
+ critical systems.\r
+\r
+ http://www.OpenRTOS.com - Commercial support, development, porting,\r
+ licensing and training services.\r
+*/\r
+\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+__declspec(interrupt:0) void vPIT0InterruptHandler( void );\r
+\r
+/* Constants used to configure the interrupts. */\r
+#define portPRESCALE_VALUE 64\r
+#define portPRESCALE_REG_SETTING ( 5 << 8 )\r
+#define portPIT_INTERRUPT_ENABLED ( 0x08 )\r
+#define configPIT0_INTERRUPT_VECTOR ( 55 )\r
+\r
+/*\r
+ * FreeRTOS.org requires two interrupts - a tick interrupt generated from a\r
+ * timer source, and a spare interrupt vector used for context switching.\r
+ * The configuration below uses PIT0 for the former, and vector 16 for the\r
+ * latter. **IF YOUR APPLICATION HAS BOTH OF THESE INTERRUPTS FREE THEN YOU DO\r
+ * NOT NEED TO CHANGE ANY OF THIS CODE** - otherwise instructions are provided\r
+ * here for using alternative interrupt sources.\r
+ *\r
+ * To change the tick interrupt source:\r
+ *\r
+ * 1) Modify vApplicationSetupInterrupts() below to be correct for whichever\r
+ * peripheral is to be used to generate the tick interrupt. The name of the\r
+ * handler function (currently vPIT0InterruptHandler()) should also be updated\r
+ * to indicate which peripheral is generating the interrupt.\r
+ *\r
+ * 2) Make sure the interrupt source is cleared within the interrupt handler function.\r
+ * Currently vPIT0InterruptHandler() clears the PIT0 interrupt.\r
+ *\r
+ * 3) Update the vector table within mcf5225x_vectors.s to install the tick\r
+ * interrupt handler in the correct vector position.\r
+ *\r
+ * To change the spare interrupt source:\r
+ *\r
+ * 1) Modify vApplicationSetupInterrupts() below to be correct for whichever\r
+ * interrupt vector is to be used. Make sure you use a spare interrupt on interrupt\r
+ * controller 0, otherwise the register used to request context switches will also\r
+ * require modification.\r
+ *\r
+ * 2) Change the definition of configYIELD_INTERRUPT_VECTOR within FreeRTOSConfig.h\r
+ * to be correct for your chosen interrupt vector.\r
+ *\r
+ * 3) Update the vector table within mcf5225x_vectors.s to install the handler\r
+ * _vPortYieldISR() in the correct vector position (by default vector number 16 is\r
+ * used).\r
+ */\r
+void vApplicationSetupInterrupts( void )\r
+{\r
+const unsigned portSHORT usCompareMatchValue = ( ( configCPU_CLOCK_HZ / portPRESCALE_VALUE ) / configTICK_RATE_HZ );\r
+\r
+ /* Configure interrupt priority and level and unmask interrupt for PIT0. */\r
+ MCF_INTC0_ICR55 = ( 1 | ( configKERNEL_INTERRUPT_PRIORITY << 3 ) );\r
+ MCF_INTC0_IMRH &= ~( MCF_INTC_IMRH_INT_MASK55 );\r
+\r
+ /* Do the same for vector 63 (interrupt controller 0. I don't think the\r
+ write to MCF_INTC0_IMRH is actually required here but is included for\r
+ completeness. */\r
+ MCF_INTC0_ICR16 = ( 0 | configKERNEL_INTERRUPT_PRIORITY << 3 );\r
+ MCF_INTC0_IMRL &= ~( MCF_INTC_IMRL_INT_MASK16 | 0x01 );\r
+\r
+ /* Configure PIT0 to generate the RTOS tick. */\r
+ MCF_PIT0_PCSR |= MCF_PIT_PCSR_PIF;\r
+ MCF_PIT0_PCSR = ( portPRESCALE_REG_SETTING | MCF_PIT_PCSR_PIE | MCF_PIT_PCSR_RLD | MCF_PIT_PCSR_EN );\r
+ MCF_PIT0_PMR = usCompareMatchValue;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+__declspec(interrupt:0) void vPIT0InterruptHandler( void )\r
+{\r
+unsigned portLONG ulSavedInterruptMask;\r
+\r
+ /* Clear the PIT0 interrupt. */\r
+ MCF_PIT0_PCSR |= MCF_PIT_PCSR_PIF;\r
+\r
+ /* Increment the RTOS tick. */\r
+ ulSavedInterruptMask = portSET_INTERRUPT_MASK_FROM_ISR();\r
+ vTaskIncrementTick();\r
+ portCLEAR_INTERRUPT_MASK_FROM_ISR( ulSavedInterruptMask );\r
+\r
+ /* If we are using the pre-emptive scheduler then also request a\r
+ context switch as incrementing the tick could have unblocked a task. */\r
+ #if configUSE_PREEMPTION == 1\r
+ {\r
+ taskYIELD();\r
+ }\r
+ #endif\r
+}\r
--- /dev/null
+/* Coldfire C Header File\r
+ * Copyright Freescale Semiconductor Inc\r
+ * All rights reserved.\r
+ *\r
+ * 2008/04/17 Revision: 0.2\r
+ *\r
+ * (c) Copyright UNIS, spol. s r.o. 1997-2008\r
+ * UNIS, spol. s r.o.\r
+ * Jundrovska 33\r
+ * 624 00 Brno\r
+ * Czech Republic\r
+ * http : www.processorexpert.com\r
+ * mail : info@processorexpert.com\r
+ */\r
+\r
+#ifndef __MCF52259_H__\r
+#define __MCF52259_H__\r
+\r
+\r
+/********************************************************************/\r
+/*\r
+ * The basic data types\r
+ */\r
+\r
+typedef unsigned char uint8; /* 8 bits */\r
+typedef unsigned short int uint16; /* 16 bits */\r
+typedef unsigned long int uint32; /* 32 bits */\r
+\r
+typedef signed char int8; /* 8 bits */\r
+typedef signed short int int16; /* 16 bits */\r
+typedef signed long int int32; /* 32 bits */\r
+\r
+typedef volatile uint8 vuint8; /* 8 bits */\r
+typedef volatile uint16 vuint16; /* 16 bits */\r
+typedef volatile uint32 vuint32; /* 32 bits */\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+#pragma define_section system ".system" far_absolute RW\r
+\r
+/***\r
+ * MCF52259 Derivative Memory map definitions from linker command files:\r
+ * __IPSBAR, __RAMBAR, __RAMBAR_SIZE, __FLASHBAR, __FLASHBAR_SIZE linker\r
+ * symbols must be defined in the linker command file.\r
+ */\r
+\r
+extern __declspec(system) uint8 __IPSBAR[];\r
+extern __declspec(system) uint8 __RAMBAR[];\r
+extern __declspec(system) uint8 __RAMBAR_SIZE[];\r
+extern __declspec(system) uint8 __FLASHBAR[];\r
+extern __declspec(system) uint8 __FLASHBAR_SIZE[];\r
+\r
+#define IPSBAR_ADDRESS (uint32)__IPSBAR\r
+#define RAMBAR_ADDRESS (uint32)__RAMBAR\r
+#define RAMBAR_SIZE (uint32)__RAMBAR_SIZE\r
+#define FLASHBAR_ADDRESS (uint32)__FLASHBAR\r
+#define FLASHBAR_SIZE (uint32)__FLASHBAR_SIZE\r
+\r
+\r
+#include "MCF52259_SCM.h"\r
+#include "MCF52259_FBCS.h"\r
+#include "MCF52259_DMA.h"\r
+#include "MCF52259_UART.h"\r
+#include "MCF52259_I2C.h"\r
+#include "MCF52259_QSPI.h"\r
+#include "MCF52259_DTIM.h"\r
+#include "MCF52259_INTC.h"\r
+#include "MCF52259_FEC.h"\r
+#include "MCF52259_GPIO.h"\r
+#include "MCF52259_PAD.h"\r
+#include "MCF52259_RCM.h"\r
+#include "MCF52259_CCM.h"\r
+#include "MCF52259_PMM.h"\r
+#include "MCF52259_CLOCK.h"\r
+#include "MCF52259_EPORT.h"\r
+#include "MCF52259_BWT.h"\r
+#include "MCF52259_PIT.h"\r
+#include "MCF52259_FlexCAN.h"\r
+#include "MCF52259_CANMB.h"\r
+#include "MCF52259_RTC.h"\r
+#include "MCF52259_ADC.h"\r
+#include "MCF52259_GPT.h"\r
+#include "MCF52259_PWM.h"\r
+#include "MCF52259_USB_OTG.h"\r
+#include "MCF52259_CFM.h"\r
+#include "MCF52259_RNGA.h"\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+\r
+#endif /* __MCF52259_H__ */\r
--- /dev/null
+/* Coldfire C Header File\r
+ * Copyright Freescale Semiconductor Inc\r
+ * All rights reserved.\r
+ *\r
+ * 2008/04/17 Revision: 0.2\r
+ *\r
+ * (c) Copyright UNIS, spol. s r.o. 1997-2008\r
+ * UNIS, spol. s r.o.\r
+ * Jundrovska 33\r
+ * 624 00 Brno\r
+ * Czech Republic\r
+ * http : www.processorexpert.com\r
+ * mail : info@processorexpert.com\r
+ */\r
+\r
+#ifndef __MCF52259_ADC_H__\r
+#define __MCF52259_ADC_H__\r
+\r
+\r
+/*********************************************************************\r
+*\r
+* Analog-to-Digital Converter (ADC)\r
+*\r
+*********************************************************************/\r
+\r
+/* Register read/write macros */\r
+#define MCF_ADC_CTRL1 (*(vuint16*)(0x40190000))\r
+#define MCF_ADC_CTRL2 (*(vuint16*)(0x40190002))\r
+#define MCF_ADC_ADZCC (*(vuint16*)(0x40190004))\r
+#define MCF_ADC_ADLST1 (*(vuint16*)(0x40190006))\r
+#define MCF_ADC_ADLST2 (*(vuint16*)(0x40190008))\r
+#define MCF_ADC_ADSDIS (*(vuint16*)(0x4019000A))\r
+#define MCF_ADC_ADSTAT (*(vuint16*)(0x4019000C))\r
+#define MCF_ADC_ADLSTAT (*(vuint16*)(0x4019000E))\r
+#define MCF_ADC_ADZCSTAT (*(vuint16*)(0x40190010))\r
+#define MCF_ADC_ADRSLT0 (*(vuint16*)(0x40190012))\r
+#define MCF_ADC_ADRSLT1 (*(vuint16*)(0x40190014))\r
+#define MCF_ADC_ADRSLT2 (*(vuint16*)(0x40190016))\r
+#define MCF_ADC_ADRSLT3 (*(vuint16*)(0x40190018))\r
+#define MCF_ADC_ADRSLT4 (*(vuint16*)(0x4019001A))\r
+#define MCF_ADC_ADRSLT5 (*(vuint16*)(0x4019001C))\r
+#define MCF_ADC_ADRSLT6 (*(vuint16*)(0x4019001E))\r
+#define MCF_ADC_ADRSLT7 (*(vuint16*)(0x40190020))\r
+#define MCF_ADC_ADLLMT0 (*(vuint16*)(0x40190022))\r
+#define MCF_ADC_ADLLMT1 (*(vuint16*)(0x40190024))\r
+#define MCF_ADC_ADLLMT2 (*(vuint16*)(0x40190026))\r
+#define MCF_ADC_ADLLMT3 (*(vuint16*)(0x40190028))\r
+#define MCF_ADC_ADLLMT4 (*(vuint16*)(0x4019002A))\r
+#define MCF_ADC_ADLLMT5 (*(vuint16*)(0x4019002C))\r
+#define MCF_ADC_ADLLMT6 (*(vuint16*)(0x4019002E))\r
+#define MCF_ADC_ADLLMT7 (*(vuint16*)(0x40190030))\r
+#define MCF_ADC_ADHLMT0 (*(vuint16*)(0x40190032))\r
+#define MCF_ADC_ADHLMT1 (*(vuint16*)(0x40190034))\r
+#define MCF_ADC_ADHLMT2 (*(vuint16*)(0x40190036))\r
+#define MCF_ADC_ADHLMT3 (*(vuint16*)(0x40190038))\r
+#define MCF_ADC_ADHLMT4 (*(vuint16*)(0x4019003A))\r
+#define MCF_ADC_ADHLMT5 (*(vuint16*)(0x4019003C))\r
+#define MCF_ADC_ADHLMT6 (*(vuint16*)(0x4019003E))\r
+#define MCF_ADC_ADHLMT7 (*(vuint16*)(0x40190040))\r
+#define MCF_ADC_ADOFS0 (*(vuint16*)(0x40190042))\r
+#define MCF_ADC_ADOFS1 (*(vuint16*)(0x40190044))\r
+#define MCF_ADC_ADOFS2 (*(vuint16*)(0x40190046))\r
+#define MCF_ADC_ADOFS3 (*(vuint16*)(0x40190048))\r
+#define MCF_ADC_ADOFS4 (*(vuint16*)(0x4019004A))\r
+#define MCF_ADC_ADOFS5 (*(vuint16*)(0x4019004C))\r
+#define MCF_ADC_ADOFS6 (*(vuint16*)(0x4019004E))\r
+#define MCF_ADC_ADOFS7 (*(vuint16*)(0x40190050))\r
+#define MCF_ADC_POWER (*(vuint16*)(0x40190052))\r
+#define MCF_ADC_CAL (*(vuint16*)(0x40190054))\r
+#define MCF_ADC_ADRSLT(x) (*(vuint16*)(0x40190012 + ((x)*0x2)))\r
+#define MCF_ADC_ADLLMT(x) (*(vuint16*)(0x40190022 + ((x)*0x2)))\r
+#define MCF_ADC_ADHLMT(x) (*(vuint16*)(0x40190032 + ((x)*0x2)))\r
+#define MCF_ADC_ADOFS(x) (*(vuint16*)(0x40190042 + ((x)*0x2)))\r
+\r
+\r
+/* Bit definitions and macros for MCF_ADC_CTRL1 */\r
+#define MCF_ADC_CTRL1_SMODE(x) (((x)&0x7)<<0)\r
+#define MCF_ADC_CTRL1_CHNCFG(x) (((x)&0xF)<<0x4)\r
+#define MCF_ADC_CTRL1_HLMTIE (0x100)\r
+#define MCF_ADC_CTRL1_LLMTIE (0x200)\r
+#define MCF_ADC_CTRL1_ZCIE (0x400)\r
+#define MCF_ADC_CTRL1_EOSIE0 (0x800)\r
+#define MCF_ADC_CTRL1_SYNC0 (0x1000)\r
+#define MCF_ADC_CTRL1_START0 (0x2000)\r
+#define MCF_ADC_CTRL1_STOP0 (0x4000)\r
+\r
+/* Bit definitions and macros for MCF_ADC_CTRL2 */\r
+#define MCF_ADC_CTRL2_DIV(x) (((x)&0x1F)<<0)\r
+#define MCF_ADC_CTRL2_SIMULT (0x20)\r
+#define MCF_ADC_CTRL2_EOSIE1 (0x800)\r
+#define MCF_ADC_CTRL2_SYNC1 (0x1000)\r
+#define MCF_ADC_CTRL2_START1 (0x2000)\r
+#define MCF_ADC_CTRL2_STOP1 (0x4000)\r
+\r
+/* Bit definitions and macros for MCF_ADC_ADZCC */\r
+#define MCF_ADC_ADZCC_ZCE0(x) (((x)&0x3)<<0)\r
+#define MCF_ADC_ADZCC_ZCE1(x) (((x)&0x3)<<0x2)\r
+#define MCF_ADC_ADZCC_ZCE2(x) (((x)&0x3)<<0x4)\r
+#define MCF_ADC_ADZCC_ZCE3(x) (((x)&0x3)<<0x6)\r
+#define MCF_ADC_ADZCC_ZCE4(x) (((x)&0x3)<<0x8)\r
+#define MCF_ADC_ADZCC_ZCE5(x) (((x)&0x3)<<0xA)\r
+#define MCF_ADC_ADZCC_ZCE6(x) (((x)&0x3)<<0xC)\r
+#define MCF_ADC_ADZCC_ZCE7(x) (((x)&0x3)<<0xE)\r
+\r
+/* Bit definitions and macros for MCF_ADC_ADLST1 */\r
+#define MCF_ADC_ADLST1_SAMPLE0(x) (((x)&0x7)<<0)\r
+#define MCF_ADC_ADLST1_SAMPLE1(x) (((x)&0x7)<<0x4)\r
+#define MCF_ADC_ADLST1_SAMPLE2(x) (((x)&0x7)<<0x8)\r
+#define MCF_ADC_ADLST1_SAMPLE3(x) (((x)&0x7)<<0xC)\r
+\r
+/* Bit definitions and macros for MCF_ADC_ADLST2 */\r
+#define MCF_ADC_ADLST2_SAMPLE4(x) (((x)&0x7)<<0)\r
+#define MCF_ADC_ADLST2_SAMPLE5(x) (((x)&0x7)<<0x4)\r
+#define MCF_ADC_ADLST2_SAMPLE6(x) (((x)&0x7)<<0x8)\r
+#define MCF_ADC_ADLST2_SAMPLE7(x) (((x)&0x7)<<0xC)\r
+\r
+/* Bit definitions and macros for MCF_ADC_ADSDIS */\r
+#define MCF_ADC_ADSDIS_DS0 (0x1)\r
+#define MCF_ADC_ADSDIS_DS1 (0x2)\r
+#define MCF_ADC_ADSDIS_DS2 (0x4)\r
+#define MCF_ADC_ADSDIS_DS3 (0x8)\r
+#define MCF_ADC_ADSDIS_DS4 (0x10)\r
+#define MCF_ADC_ADSDIS_DS5 (0x20)\r
+#define MCF_ADC_ADSDIS_DS6 (0x40)\r
+#define MCF_ADC_ADSDIS_DS7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_ADC_ADSTAT */\r
+#define MCF_ADC_ADSTAT_RDY0 (0x1)\r
+#define MCF_ADC_ADSTAT_RDY1 (0x2)\r
+#define MCF_ADC_ADSTAT_RDY2 (0x4)\r
+#define MCF_ADC_ADSTAT_RDY3 (0x8)\r
+#define MCF_ADC_ADSTAT_RDY4 (0x10)\r
+#define MCF_ADC_ADSTAT_RDY5 (0x20)\r
+#define MCF_ADC_ADSTAT_RDY6 (0x40)\r
+#define MCF_ADC_ADSTAT_RDY7 (0x80)\r
+#define MCF_ADC_ADSTAT_HLMTI (0x100)\r
+#define MCF_ADC_ADSTAT_LLMTI (0x200)\r
+#define MCF_ADC_ADSTAT_ZCI (0x400)\r
+#define MCF_ADC_ADSTAT_EOSI0 (0x800)\r
+#define MCF_ADC_ADSTAT_EOSI1 (0x1000)\r
+#define MCF_ADC_ADSTAT_CIP1 (0x4000)\r
+#define MCF_ADC_ADSTAT_CIP0 (0x8000)\r
+\r
+/* Bit definitions and macros for MCF_ADC_ADLSTAT */\r
+#define MCF_ADC_ADLSTAT_LLS0 (0x1)\r
+#define MCF_ADC_ADLSTAT_LLS1 (0x2)\r
+#define MCF_ADC_ADLSTAT_LLS2 (0x4)\r
+#define MCF_ADC_ADLSTAT_LLS3 (0x8)\r
+#define MCF_ADC_ADLSTAT_LLS4 (0x10)\r
+#define MCF_ADC_ADLSTAT_LLS5 (0x20)\r
+#define MCF_ADC_ADLSTAT_LLS6 (0x40)\r
+#define MCF_ADC_ADLSTAT_LLS7 (0x80)\r
+#define MCF_ADC_ADLSTAT_HLS0 (0x100)\r
+#define MCF_ADC_ADLSTAT_HLS1 (0x200)\r
+#define MCF_ADC_ADLSTAT_HLS2 (0x400)\r
+#define MCF_ADC_ADLSTAT_HLS3 (0x800)\r
+#define MCF_ADC_ADLSTAT_HLS4 (0x1000)\r
+#define MCF_ADC_ADLSTAT_HLS5 (0x2000)\r
+#define MCF_ADC_ADLSTAT_HLS6 (0x4000)\r
+#define MCF_ADC_ADLSTAT_HLS7 (0x8000)\r
+\r
+/* Bit definitions and macros for MCF_ADC_ADZCSTAT */\r
+#define MCF_ADC_ADZCSTAT_ZCS0 (0x1)\r
+#define MCF_ADC_ADZCSTAT_ZCS1 (0x2)\r
+#define MCF_ADC_ADZCSTAT_ZCS2 (0x4)\r
+#define MCF_ADC_ADZCSTAT_ZCS3 (0x8)\r
+#define MCF_ADC_ADZCSTAT_ZCS4 (0x10)\r
+#define MCF_ADC_ADZCSTAT_ZCS5 (0x20)\r
+#define MCF_ADC_ADZCSTAT_ZCS6 (0x40)\r
+#define MCF_ADC_ADZCSTAT_ZCS7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_ADC_ADRSLT */\r
+#define MCF_ADC_ADRSLT_RSLT(x) (((x)&0xFFF)<<0x3)\r
+#define MCF_ADC_ADRSLT_SEXT (0x8000)\r
+\r
+/* Bit definitions and macros for MCF_ADC_ADLLMT */\r
+#define MCF_ADC_ADLLMT_LLMT(x) (((x)&0xFFF)<<0x3)\r
+\r
+/* Bit definitions and macros for MCF_ADC_ADHLMT */\r
+#define MCF_ADC_ADHLMT_HLMT(x) (((x)&0xFFF)<<0x3)\r
+\r
+/* Bit definitions and macros for MCF_ADC_ADOFS */\r
+#define MCF_ADC_ADOFS_OFFSET(x) (((x)&0xFFF)<<0x3)\r
+\r
+/* Bit definitions and macros for MCF_ADC_POWER */\r
+#define MCF_ADC_POWER_PD0 (0x1)\r
+#define MCF_ADC_POWER_PD1 (0x2)\r
+#define MCF_ADC_POWER_PD2 (0x4)\r
+#define MCF_ADC_POWER_APD (0x8)\r
+#define MCF_ADC_POWER_PUDELAY(x) (((x)&0x3F)<<0x4)\r
+#define MCF_ADC_POWER_PSTS0 (0x400)\r
+#define MCF_ADC_POWER_PSTS1 (0x800)\r
+#define MCF_ADC_POWER_PSTS2 (0x1000)\r
+#define MCF_ADC_POWER_ASB (0x8000)\r
+\r
+/* Bit definitions and macros for MCF_ADC_CAL */\r
+#define MCF_ADC_CAL_SEL_VREFL (0x4000)\r
+#define MCF_ADC_CAL_SEL_VREFH (0x8000)\r
+\r
+\r
+#endif /* __MCF52259_ADC_H__ */\r
--- /dev/null
+/* Coldfire C Header File\r
+ * Copyright Freescale Semiconductor Inc\r
+ * All rights reserved.\r
+ *\r
+ * 2008/04/17 Revision: 0.2\r
+ *\r
+ * (c) Copyright UNIS, spol. s r.o. 1997-2008\r
+ * UNIS, spol. s r.o.\r
+ * Jundrovska 33\r
+ * 624 00 Brno\r
+ * Czech Republic\r
+ * http : www.processorexpert.com\r
+ * mail : info@processorexpert.com\r
+ */\r
+\r
+#ifndef __MCF52259_BWT_H__\r
+#define __MCF52259_BWT_H__\r
+\r
+\r
+/*********************************************************************\r
+*\r
+* Backup Watchdog Timer Module (BWT)\r
+*\r
+*********************************************************************/\r
+\r
+/* Register read/write macros */\r
+#define MCF_BWT_WCR (*(vuint16*)(0x40140000))\r
+#define MCF_BWT_WMR (*(vuint16*)(0x40140002))\r
+#define MCF_BWT_WCNTR (*(vuint16*)(0x40140004))\r
+#define MCF_BWT_WSR (*(vuint16*)(0x40140006))\r
+\r
+\r
+/* Bit definitions and macros for MCF_BWT_WCR */\r
+#define MCF_BWT_WCR_EN (0x1)\r
+#define MCF_BWT_WCR_DBG (0x2)\r
+#define MCF_BWT_WCR_DOZE (0x4)\r
+#define MCF_BWT_WCR_WAIT (0x8)\r
+#define MCF_BWT_WCR_STOP (0x10)\r
+\r
+/* Bit definitions and macros for MCF_BWT_WMR */\r
+#define MCF_BWT_WMR_WM(x) (((x)&0xFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_BWT_WCNTR */\r
+#define MCF_BWT_WCNTR_WC(x) (((x)&0xFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_BWT_WSR */\r
+#define MCF_BWT_WSR_WS(x) (((x)&0xFFFF)<<0)\r
+\r
+\r
+#endif /* __MCF52259_BWT_H__ */\r
--- /dev/null
+/* Coldfire C Header File\r
+ * Copyright Freescale Semiconductor Inc\r
+ * All rights reserved.\r
+ *\r
+ * 2008/04/17 Revision: 0.2\r
+ *\r
+ * (c) Copyright UNIS, spol. s r.o. 1997-2008\r
+ * UNIS, spol. s r.o.\r
+ * Jundrovska 33\r
+ * 624 00 Brno\r
+ * Czech Republic\r
+ * http : www.processorexpert.com\r
+ * mail : info@processorexpert.com\r
+ */\r
+\r
+#ifndef __MCF52259_CANMB_H__\r
+#define __MCF52259_CANMB_H__\r
+\r
+\r
+/*********************************************************************\r
+*\r
+* Flex Controller Area Network Module (FlexCAN) message buffers\r
+*\r
+*********************************************************************/\r
+\r
+/* Register read/write macros */\r
+#define MCF_CANMB_CODE0 (*(vuint8 *)(&__IPSBAR[0x170080]))\r
+#define MCF_CANMB_CTRL0 (*(vuint8 *)(&__IPSBAR[0x170081]))\r
+#define MCF_CANMB_TIME0 (*(vuint16*)(&__IPSBAR[0x170082]))\r
+#define MCF_CANMB_ID0 (*(vuint32*)(&__IPSBAR[0x170084]))\r
+#define MCF_CANMB_DATA_WORD_1_0 (*(vuint16*)(&__IPSBAR[0x170088]))\r
+#define MCF_CANMB_DATA_WORD_2_0 (*(vuint16*)(&__IPSBAR[0x17008A]))\r
+#define MCF_CANMB_DATA_WORD_3_0 (*(vuint16*)(&__IPSBAR[0x17008C]))\r
+#define MCF_CANMB_DATA_WORD_4_0 (*(vuint16*)(&__IPSBAR[0x17008E]))\r
+#define MCF_CANMB_CODE1 (*(vuint8 *)(&__IPSBAR[0x170090]))\r
+#define MCF_CANMB_CTRL1 (*(vuint8 *)(&__IPSBAR[0x170091]))\r
+#define MCF_CANMB_TIME1 (*(vuint16*)(&__IPSBAR[0x170092]))\r
+#define MCF_CANMB_ID1 (*(vuint32*)(&__IPSBAR[0x170094]))\r
+#define MCF_CANMB_DATA_WORD_1_1 (*(vuint16*)(&__IPSBAR[0x170098]))\r
+#define MCF_CANMB_DATA_WORD_2_1 (*(vuint16*)(&__IPSBAR[0x17009A]))\r
+#define MCF_CANMB_DATA_WORD_3_1 (*(vuint16*)(&__IPSBAR[0x17009C]))\r
+#define MCF_CANMB_DATA_WORD_4_1 (*(vuint16*)(&__IPSBAR[0x17009E]))\r
+#define MCF_CANMB_CODE2 (*(vuint8 *)(&__IPSBAR[0x1700A0]))\r
+#define MCF_CANMB_CTRL2 (*(vuint8 *)(&__IPSBAR[0x1700A1]))\r
+#define MCF_CANMB_TIME2 (*(vuint16*)(&__IPSBAR[0x1700A2]))\r
+#define MCF_CANMB_ID2 (*(vuint32*)(&__IPSBAR[0x1700A4]))\r
+#define MCF_CANMB_DATA_WORD_1_2 (*(vuint16*)(&__IPSBAR[0x1700A8]))\r
+#define MCF_CANMB_DATA_WORD_2_2 (*(vuint16*)(&__IPSBAR[0x1700AA]))\r
+#define MCF_CANMB_DATA_WORD_3_2 (*(vuint16*)(&__IPSBAR[0x1700AC]))\r
+#define MCF_CANMB_DATA_WORD_4_2 (*(vuint16*)(&__IPSBAR[0x1700AE]))\r
+#define MCF_CANMB_CODE3 (*(vuint8 *)(&__IPSBAR[0x1700B0]))\r
+#define MCF_CANMB_CTRL3 (*(vuint8 *)(&__IPSBAR[0x1700B1]))\r
+#define MCF_CANMB_TIME3 (*(vuint16*)(&__IPSBAR[0x1700B2]))\r
+#define MCF_CANMB_ID3 (*(vuint32*)(&__IPSBAR[0x1700B4]))\r
+#define MCF_CANMB_DATA_WORD_1_3 (*(vuint16*)(&__IPSBAR[0x1700B8]))\r
+#define MCF_CANMB_DATA_WORD_2_3 (*(vuint16*)(&__IPSBAR[0x1700BA]))\r
+#define MCF_CANMB_DATA_WORD_3_3 (*(vuint16*)(&__IPSBAR[0x1700BC]))\r
+#define MCF_CANMB_DATA_WORD_4_3 (*(vuint16*)(&__IPSBAR[0x1700BE]))\r
+#define MCF_CANMB_CODE4 (*(vuint8 *)(&__IPSBAR[0x1700C0]))\r
+#define MCF_CANMB_CTRL4 (*(vuint8 *)(&__IPSBAR[0x1700C1]))\r
+#define MCF_CANMB_TIME4 (*(vuint16*)(&__IPSBAR[0x1700C2]))\r
+#define MCF_CANMB_ID4 (*(vuint32*)(&__IPSBAR[0x1700C4]))\r
+#define MCF_CANMB_DATA_WORD_1_4 (*(vuint16*)(&__IPSBAR[0x1700C8]))\r
+#define MCF_CANMB_DATA_WORD_2_4 (*(vuint16*)(&__IPSBAR[0x1700CA]))\r
+#define MCF_CANMB_DATA_WORD_3_4 (*(vuint16*)(&__IPSBAR[0x1700CC]))\r
+#define MCF_CANMB_DATA_WORD_4_4 (*(vuint16*)(&__IPSBAR[0x1700CE]))\r
+#define MCF_CANMB_CODE5 (*(vuint8 *)(&__IPSBAR[0x1700D0]))\r
+#define MCF_CANMB_CTRL5 (*(vuint8 *)(&__IPSBAR[0x1700D1]))\r
+#define MCF_CANMB_TIME5 (*(vuint16*)(&__IPSBAR[0x1700D2]))\r
+#define MCF_CANMB_ID5 (*(vuint32*)(&__IPSBAR[0x1700D4]))\r
+#define MCF_CANMB_DATA_WORD_1_5 (*(vuint16*)(&__IPSBAR[0x1700D8]))\r
+#define MCF_CANMB_DATA_WORD_2_5 (*(vuint16*)(&__IPSBAR[0x1700DA]))\r
+#define MCF_CANMB_DATA_WORD_3_5 (*(vuint16*)(&__IPSBAR[0x1700DC]))\r
+#define MCF_CANMB_DATA_WORD_4_5 (*(vuint16*)(&__IPSBAR[0x1700DE]))\r
+#define MCF_CANMB_CODE6 (*(vuint8 *)(&__IPSBAR[0x1700E0]))\r
+#define MCF_CANMB_CTRL6 (*(vuint8 *)(&__IPSBAR[0x1700E1]))\r
+#define MCF_CANMB_TIME6 (*(vuint16*)(&__IPSBAR[0x1700E2]))\r
+#define MCF_CANMB_ID6 (*(vuint32*)(&__IPSBAR[0x1700E4]))\r
+#define MCF_CANMB_DATA_WORD_1_6 (*(vuint16*)(&__IPSBAR[0x1700E8]))\r
+#define MCF_CANMB_DATA_WORD_2_6 (*(vuint16*)(&__IPSBAR[0x1700EA]))\r
+#define MCF_CANMB_DATA_WORD_3_6 (*(vuint16*)(&__IPSBAR[0x1700EC]))\r
+#define MCF_CANMB_DATA_WORD_4_6 (*(vuint16*)(&__IPSBAR[0x1700EE]))\r
+#define MCF_CANMB_CODE7 (*(vuint8 *)(&__IPSBAR[0x1700F0]))\r
+#define MCF_CANMB_CTRL7 (*(vuint8 *)(&__IPSBAR[0x1700F1]))\r
+#define MCF_CANMB_TIME7 (*(vuint16*)(&__IPSBAR[0x1700F2]))\r
+#define MCF_CANMB_ID7 (*(vuint32*)(&__IPSBAR[0x1700F4]))\r
+#define MCF_CANMB_DATA_WORD_1_7 (*(vuint16*)(&__IPSBAR[0x1700F8]))\r
+#define MCF_CANMB_DATA_WORD_2_7 (*(vuint16*)(&__IPSBAR[0x1700FA]))\r
+#define MCF_CANMB_DATA_WORD_3_7 (*(vuint16*)(&__IPSBAR[0x1700FC]))\r
+#define MCF_CANMB_DATA_WORD_4_7 (*(vuint16*)(&__IPSBAR[0x1700FE]))\r
+#define MCF_CANMB_CODE8 (*(vuint8 *)(&__IPSBAR[0x170100]))\r
+#define MCF_CANMB_CTRL8 (*(vuint8 *)(&__IPSBAR[0x170101]))\r
+#define MCF_CANMB_TIME8 (*(vuint16*)(&__IPSBAR[0x170102]))\r
+#define MCF_CANMB_ID8 (*(vuint32*)(&__IPSBAR[0x170104]))\r
+#define MCF_CANMB_DATA_WORD_1_8 (*(vuint16*)(&__IPSBAR[0x170108]))\r
+#define MCF_CANMB_DATA_WORD_2_8 (*(vuint16*)(&__IPSBAR[0x17010A]))\r
+#define MCF_CANMB_DATA_WORD_3_8 (*(vuint16*)(&__IPSBAR[0x17010C]))\r
+#define MCF_CANMB_DATA_WORD_4_8 (*(vuint16*)(&__IPSBAR[0x17010E]))\r
+#define MCF_CANMB_CODE9 (*(vuint8 *)(&__IPSBAR[0x170110]))\r
+#define MCF_CANMB_CTRL9 (*(vuint8 *)(&__IPSBAR[0x170111]))\r
+#define MCF_CANMB_TIME9 (*(vuint16*)(&__IPSBAR[0x170112]))\r
+#define MCF_CANMB_ID9 (*(vuint32*)(&__IPSBAR[0x170114]))\r
+#define MCF_CANMB_DATA_WORD_1_9 (*(vuint16*)(&__IPSBAR[0x170118]))\r
+#define MCF_CANMB_DATA_WORD_2_9 (*(vuint16*)(&__IPSBAR[0x17011A]))\r
+#define MCF_CANMB_DATA_WORD_3_9 (*(vuint16*)(&__IPSBAR[0x17011C]))\r
+#define MCF_CANMB_DATA_WORD_4_9 (*(vuint16*)(&__IPSBAR[0x17011E]))\r
+#define MCF_CANMB_CODE10 (*(vuint8 *)(&__IPSBAR[0x170120]))\r
+#define MCF_CANMB_CTRL10 (*(vuint8 *)(&__IPSBAR[0x170121]))\r
+#define MCF_CANMB_TIME10 (*(vuint16*)(&__IPSBAR[0x170122]))\r
+#define MCF_CANMB_ID10 (*(vuint32*)(&__IPSBAR[0x170124]))\r
+#define MCF_CANMB_DATA_WORD_1_10 (*(vuint16*)(&__IPSBAR[0x170128]))\r
+#define MCF_CANMB_DATA_WORD_2_10 (*(vuint16*)(&__IPSBAR[0x17012A]))\r
+#define MCF_CANMB_DATA_WORD_3_10 (*(vuint16*)(&__IPSBAR[0x17012C]))\r
+#define MCF_CANMB_DATA_WORD_4_10 (*(vuint16*)(&__IPSBAR[0x17012E]))\r
+#define MCF_CANMB_CODE11 (*(vuint8 *)(&__IPSBAR[0x170130]))\r
+#define MCF_CANMB_CTRL11 (*(vuint8 *)(&__IPSBAR[0x170131]))\r
+#define MCF_CANMB_TIME11 (*(vuint16*)(&__IPSBAR[0x170132]))\r
+#define MCF_CANMB_ID11 (*(vuint32*)(&__IPSBAR[0x170134]))\r
+#define MCF_CANMB_DATA_WORD_1_11 (*(vuint16*)(&__IPSBAR[0x170138]))\r
+#define MCF_CANMB_DATA_WORD_2_11 (*(vuint16*)(&__IPSBAR[0x17013A]))\r
+#define MCF_CANMB_DATA_WORD_3_11 (*(vuint16*)(&__IPSBAR[0x17013C]))\r
+#define MCF_CANMB_DATA_WORD_4_11 (*(vuint16*)(&__IPSBAR[0x17013E]))\r
+#define MCF_CANMB_CODE12 (*(vuint8 *)(&__IPSBAR[0x170140]))\r
+#define MCF_CANMB_CTRL12 (*(vuint8 *)(&__IPSBAR[0x170141]))\r
+#define MCF_CANMB_TIME12 (*(vuint16*)(&__IPSBAR[0x170142]))\r
+#define MCF_CANMB_ID12 (*(vuint32*)(&__IPSBAR[0x170144]))\r
+#define MCF_CANMB_DATA_WORD_1_ (*(vuint16*)(&__IPSBAR[0x170148]))\r
+#define MCF_CANMB_DATA_WORD_2_12 (*(vuint16*)(&__IPSBAR[0x17014A]))\r
+#define MCF_CANMB_DATA_WORD_3_12 (*(vuint16*)(&__IPSBAR[0x17014C]))\r
+#define MCF_CANMB_DATA_WORD_4_12 (*(vuint16*)(&__IPSBAR[0x17014E]))\r
+#define MCF_CANMB_CODE13 (*(vuint8 *)(&__IPSBAR[0x170150]))\r
+#define MCF_CANMB_CTRL13 (*(vuint8 *)(&__IPSBAR[0x170151]))\r
+#define MCF_CANMB_TIME13 (*(vuint16*)(&__IPSBAR[0x170152]))\r
+#define MCF_CANMB_ID13 (*(vuint32*)(&__IPSBAR[0x170154]))\r
+#define MCF_CANMB_DATA_WORD_1_13 (*(vuint16*)(&__IPSBAR[0x170158]))\r
+#define MCF_CANMB_DATA_WORD_2_13 (*(vuint16*)(&__IPSBAR[0x17015A]))\r
+#define MCF_CANMB_DATA_WORD_3_13 (*(vuint16*)(&__IPSBAR[0x17015C]))\r
+#define MCF_CANMB_DATA_WORD_4_13 (*(vuint16*)(&__IPSBAR[0x17015E]))\r
+#define MCF_CANMB_CODE14 (*(vuint8 *)(&__IPSBAR[0x170160]))\r
+#define MCF_CANMB_CTRL14 (*(vuint8 *)(&__IPSBAR[0x170161]))\r
+#define MCF_CANMB_TIME14 (*(vuint16*)(&__IPSBAR[0x170162]))\r
+#define MCF_CANMB_ID14 (*(vuint32*)(&__IPSBAR[0x170164]))\r
+#define MCF_CANMB_DATA_WORD_1_14 (*(vuint16*)(&__IPSBAR[0x170168]))\r
+#define MCF_CANMB_DATA_WORD_2_14 (*(vuint16*)(&__IPSBAR[0x17016A]))\r
+#define MCF_CANMB_DATA_WORD_3_14 (*(vuint16*)(&__IPSBAR[0x17016C]))\r
+#define MCF_CANMB_DATA_WORD_4_14 (*(vuint16*)(&__IPSBAR[0x17016E]))\r
+#define MCF_CANMB_CODE15 (*(vuint8 *)(&__IPSBAR[0x170170]))\r
+#define MCF_CANMB_CTRL15 (*(vuint8 *)(&__IPSBAR[0x170171]))\r
+#define MCF_CANMB_TIME15 (*(vuint16*)(&__IPSBAR[0x170172]))\r
+#define MCF_CANMB_ID15 (*(vuint32*)(&__IPSBAR[0x170174]))\r
+#define MCF_CANMB_DATA_WORD_1_15 (*(vuint16*)(&__IPSBAR[0x170178]))\r
+#define MCF_CANMB_DATA_WORD_2_15 (*(vuint16*)(&__IPSBAR[0x17017A]))\r
+#define MCF_CANMB_DATA_WORD_3_15 (*(vuint16*)(&__IPSBAR[0x17017C]))\r
+#define MCF_CANMB_DATA_WORD_4_15 (*(vuint16*)(&__IPSBAR[0x17017E]))\r
+#define MCF_CANMB_CODE(x) (*(vuint8 *)(&__IPSBAR[0x170080 + ((x)*0x10)]))\r
+#define MCF_CANMB_CTRL(x) (*(vuint8 *)(&__IPSBAR[0x170081 + ((x)*0x10)]))\r
+#define MCF_CANMB_TIME(x) (*(vuint16*)(&__IPSBAR[0x170082 + ((x)*0x10)]))\r
+#define MCF_CANMB_ID(x) (*(vuint32*)(&__IPSBAR[0x170084 + ((x)*0x10)]))\r
+#define MCF_CANMB_DATA_WORD_1(x) (*(vuint16*)(&__IPSBAR[0x170088 + ((x)*0x10)]))\r
+#define MCF_CANMB_DATA_WORD_2(x) (*(vuint16*)(&__IPSBAR[0x17008A + ((x)*0x10)]))\r
+#define MCF_CANMB_DATA_WORD_3(x) (*(vuint16*)(&__IPSBAR[0x17008C + ((x)*0x10)]))\r
+#define MCF_CANMB_DATA_WORD_4(x) (*(vuint16*)(&__IPSBAR[0x17008E + ((x)*0x10)]))\r
+\r
+\r
+/* Other macros */\r
+#define MCF_CANMB_BYTE(x,y) (*(vuint8 *)(&__IPSBAR[((0x170088 + ((x)*0x10)+y))]))\r
+\r
+\r
+/* Bit definitions and macros for MCF_CANMB_CODE */\r
+#define MCF_CANMB_CODE_CODE(x) (((x)&0xF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_CANMB_CTRL */\r
+#define MCF_CANMB_CTRL_LENGTH(x) (((x)&0xF)<<0)\r
+#define MCF_CANMB_CTRL_RTR (0x10)\r
+#define MCF_CANMB_CTRL_IDE (0x20)\r
+#define MCF_CANMB_CTRL_SRR (0x40)\r
+\r
+/* Bit definitions and macros for MCF_CANMB_TIME */\r
+#define MCF_CANMB_TIME_TIME_STAMP(x) (((x)&0xFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_CANMB_ID */\r
+#define MCF_CANMB_ID_EXT(x) (((x)&0x3FFFF)<<0)\r
+#define MCF_CANMB_ID_STD(x) (((x)&0x7FF)<<0x12)\r
+\r
+/* Bit definitions and macros for MCF_CANMB_DATA_WORD_1 */\r
+#define MCF_CANMB_DATA_WORD_1_DATA_BYTE_1(x) (((x)&0xFF)<<0)\r
+#define MCF_CANMB_DATA_WORD_1_DATA_BYTE_0(x) (((x)&0xFF)<<0x8)\r
+\r
+/* Bit definitions and macros for MCF_CANMB_DATA_WORD_2 */\r
+#define MCF_CANMB_DATA_WORD_2_DATA_BYTE_3(x) (((x)&0xFF)<<0)\r
+#define MCF_CANMB_DATA_WORD_2_DATA_BYTE_2(x) (((x)&0xFF)<<0x8)\r
+\r
+/* Bit definitions and macros for MCF_CANMB_DATA_WORD_3 */\r
+#define MCF_CANMB_DATA_WORD_3_DATA_BYTE_5(x) (((x)&0xFF)<<0)\r
+#define MCF_CANMB_DATA_WORD_3_DATA_BYTE_4(x) (((x)&0xFF)<<0x8)\r
+\r
+/* Bit definitions and macros for MCF_CANMB_DATA_WORD_4 */\r
+#define MCF_CANMB_DATA_WORD_4_DATA_BYTE_7(x) (((x)&0xFF)<<0)\r
+#define MCF_CANMB_DATA_WORD_4_DATA_BYTE_6(x) (((x)&0xFF)<<0x8)\r
+\r
+\r
+#endif /* __MCF52259_CANMB_H__ */\r
--- /dev/null
+/* Coldfire C Header File\r
+ * Copyright Freescale Semiconductor Inc\r
+ * All rights reserved.\r
+ *\r
+ * 2008/04/17 Revision: 0.2\r
+ *\r
+ * (c) Copyright UNIS, spol. s r.o. 1997-2008\r
+ * UNIS, spol. s r.o.\r
+ * Jundrovska 33\r
+ * 624 00 Brno\r
+ * Czech Republic\r
+ * http : www.processorexpert.com\r
+ * mail : info@processorexpert.com\r
+ */\r
+\r
+#ifndef __MCF52259_CCM_H__\r
+#define __MCF52259_CCM_H__\r
+\r
+\r
+/*********************************************************************\r
+*\r
+* Chip Configuration Module (CCM)\r
+*\r
+*********************************************************************/\r
+\r
+/* Register read/write macros */\r
+#define MCF_CCM_CCR (*(vuint16*)(0x40110004))\r
+#define MCF_CCM_RCON (*(vuint16*)(0x40110008))\r
+#define MCF_CCM_CIR (*(vuint16*)(0x4011000A))\r
+#define MCF_CCM_CCE (*(vuint16*)(0x40110010))\r
+\r
+\r
+/* Bit definitions and macros for MCF_CCM_CCR */\r
+#define MCF_CCM_CCR_Mode(x) (((x)&0x7)<<0x8)\r
+#define MCF_CCM_CCR_MODE_SINGLECHIP (0x600)\r
+#define MCF_CCM_CCR_MODE_EZPORT (0x500)\r
+#define MCF_CCM_CCR_LOAD (0x8000)\r
+\r
+/* Bit definitions and macros for MCF_CCM_RCON */\r
+#define MCF_CCM_RCON_RLOAD (0x20)\r
+\r
+/* Bit definitions and macros for MCF_CCM_CIR */\r
+#define MCF_CCM_CIR_PRN(x) (((x)&0x3F)<<0)\r
+#define MCF_CCM_CIR_PIN(x) (((x)&0x3FF)<<0x6)\r
+\r
+/* Bit definitions and macros for MCF_CCM_CCE */\r
+#define MCF_CCM_CCE_USBEND (0x4000)\r
+#define MCF_CCM_CCE_MBMOD (0x8000)\r
+\r
+\r
+#endif /* __MCF52259_CCM_H__ */\r
--- /dev/null
+/* Coldfire C Header File\r
+ * Copyright Freescale Semiconductor Inc\r
+ * All rights reserved.\r
+ *\r
+ * 2008/04/17 Revision: 0.2\r
+ *\r
+ * (c) Copyright UNIS, spol. s r.o. 1997-2008\r
+ * UNIS, spol. s r.o.\r
+ * Jundrovska 33\r
+ * 624 00 Brno\r
+ * Czech Republic\r
+ * http : www.processorexpert.com\r
+ * mail : info@processorexpert.com\r
+ */\r
+\r
+#ifndef __MCF52259_CFM_H__\r
+#define __MCF52259_CFM_H__\r
+\r
+\r
+/*********************************************************************\r
+*\r
+* ColdFire Flash Module (CFM)\r
+*\r
+*********************************************************************/\r
+\r
+/* Register read/write macros */\r
+#define MCF_CFM_CFMMCR (*(vuint16*)(0x401D0000))\r
+#define MCF_CFM_CFMCLKD (*(vuint8 *)(0x401D0002))\r
+#define MCF_CFM_CFMSEC (*(vuint32*)(0x401D0008))\r
+#define MCF_CFM_CFMPROT (*(vuint32*)(0x401D0010))\r
+#define MCF_CFM_CFMSACC (*(vuint32*)(0x401D0014))\r
+#define MCF_CFM_CFMDACC (*(vuint32*)(0x401D0018))\r
+#define MCF_CFM_CFMUSTAT (*(vuint8 *)(0x401D0020))\r
+#define MCF_CFM_CFMCMD (*(vuint8 *)(0x401D0024))\r
+#define MCF_CFM_CFMCLKSEL (*(vuint16*)(0x401D004A))\r
+\r
+\r
+/* Bit definitions and macros for MCF_CFM_CFMMCR */\r
+#define MCF_CFM_CFMMCR_KEYACC (0x20)\r
+#define MCF_CFM_CFMMCR_CCIE (0x40)\r
+#define MCF_CFM_CFMMCR_CBEIE (0x80)\r
+#define MCF_CFM_CFMMCR_AEIE (0x100)\r
+#define MCF_CFM_CFMMCR_PVIE (0x200)\r
+#define MCF_CFM_CFMMCR_LOCK (0x400)\r
+\r
+/* Bit definitions and macros for MCF_CFM_CFMCLKD */\r
+#define MCF_CFM_CFMCLKD_DIV(x) (((x)&0x3F)<<0)\r
+#define MCF_CFM_CFMCLKD_PRDIV8 (0x40)\r
+#define MCF_CFM_CFMCLKD_DIVLD (0x80)\r
+\r
+/* Bit definitions and macros for MCF_CFM_CFMSEC */\r
+#define MCF_CFM_CFMSEC_SEC(x) (((x)&0xFFFF)<<0)\r
+#define MCF_CFM_CFMSEC_SECSTAT (0x40000000)\r
+#define MCF_CFM_CFMSEC_KEYEN (0x80000000)\r
+\r
+/* Bit definitions and macros for MCF_CFM_CFMPROT */\r
+#define MCF_CFM_CFMPROT_PROTECT(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_CFM_CFMSACC */\r
+#define MCF_CFM_CFMSACC_SUPV(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_CFM_CFMDACC */\r
+#define MCF_CFM_CFMDACC_DACC(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_CFM_CFMUSTAT */\r
+#define MCF_CFM_CFMUSTAT_BLANK (0x4)\r
+#define MCF_CFM_CFMUSTAT_ACCERR (0x10)\r
+#define MCF_CFM_CFMUSTAT_PVIOL (0x20)\r
+#define MCF_CFM_CFMUSTAT_CCIF (0x40)\r
+#define MCF_CFM_CFMUSTAT_CBEIF (0x80)\r
+\r
+/* Bit definitions and macros for MCF_CFM_CFMCMD */\r
+#define MCF_CFM_CFMCMD_CMD(x) (((x)&0x7F)<<0)\r
+#define MCF_CFM_CFMCMD_BLANK_CHECK (0x5)\r
+#define MCF_CFM_CFMCMD_PAGE_ERASE_VERIFY (0x6)\r
+#define MCF_CFM_CFMCMD_WORD_PROGRAM (0x20)\r
+#define MCF_CFM_CFMCMD_PAGE_ERASE (0x40)\r
+#define MCF_CFM_CFMCMD_MASS_ERASE (0x41)\r
+\r
+/* Bit definitions and macros for MCF_CFM_CFMCLKSEL */\r
+#define MCF_CFM_CFMCLKSEL_CLKSEL(x) (((x)&0x3)<<0)\r
+\r
+\r
+#endif /* __MCF52259_CFM_H__ */\r
--- /dev/null
+/* Coldfire C Header File\r
+ * Copyright Freescale Semiconductor Inc\r
+ * All rights reserved.\r
+ *\r
+ * 2008/04/17 Revision: 0.2\r
+ *\r
+ * (c) Copyright UNIS, spol. s r.o. 1997-2008\r
+ * UNIS, spol. s r.o.\r
+ * Jundrovska 33\r
+ * 624 00 Brno\r
+ * Czech Republic\r
+ * http : www.processorexpert.com\r
+ * mail : info@processorexpert.com\r
+ */\r
+\r
+#ifndef __MCF52259_CLOCK_H__\r
+#define __MCF52259_CLOCK_H__\r
+\r
+\r
+/*********************************************************************\r
+*\r
+* Clock Module (CLOCK)\r
+*\r
+*********************************************************************/\r
+\r
+/* Register read/write macros */\r
+#define MCF_CLOCK_SYNCR (*(vuint16*)(0x40120000))\r
+#define MCF_CLOCK_SYNSR (*(vuint8 *)(0x40120002))\r
+#define MCF_CLOCK_ROCR (*(vuint16*)(0x40120004))\r
+#define MCF_CLOCK_LPDR (*(vuint8 *)(0x40120007))\r
+#define MCF_CLOCK_CCHR (*(vuint8 *)(0x40120008))\r
+#define MCF_CLOCK_CCLR (*(vuint8 *)(0x40120009))\r
+#define MCF_CLOCK_OCHR (*(vuint8 *)(0x4012000A))\r
+#define MCF_CLOCK_OCLR (*(vuint8 *)(0x4012000B))\r
+#define MCF_CLOCK_RTCCR (*(vuint8 *)(0x40120012))\r
+#define MCF_CLOCK_BWCR (*(vuint8 *)(0x40120013))\r
+\r
+\r
+/* Bit definitions and macros for MCF_CLOCK_SYNCR */\r
+#define MCF_CLOCK_SYNCR_PLLEN (0x1)\r
+#define MCF_CLOCK_SYNCR_PLLMODE (0x2)\r
+#define MCF_CLOCK_SYNCR_CLKSRC (0x4)\r
+#define MCF_CLOCK_SYNCR_FWKUP (0x20)\r
+#define MCF_CLOCK_SYNCR_DISCLK (0x40)\r
+#define MCF_CLOCK_SYNCR_LOCEN (0x80)\r
+#define MCF_CLOCK_SYNCR_RFD(x) (((x)&0x7)<<0x8)\r
+#define MCF_CLOCK_SYNCR_LOCRE (0x800)\r
+#define MCF_CLOCK_SYNCR_MFD(x) (((x)&0x7)<<0xC)\r
+#define MCF_CLOCK_SYNCR_LOLRE (0x8000)\r
+\r
+/* Bit definitions and macros for MCF_CLOCK_SYNSR */\r
+#define MCF_CLOCK_SYNSR_LOCS (0x4)\r
+#define MCF_CLOCK_SYNSR_LOCK (0x8)\r
+#define MCF_CLOCK_SYNSR_LOCKS (0x10)\r
+#define MCF_CLOCK_SYNSR_CRYOSC (0x20)\r
+#define MCF_CLOCK_SYNSR_OCOSC (0x40)\r
+#define MCF_CLOCK_SYNSR_EXTOSC (0x80)\r
+\r
+/* Bit definitions and macros for MCF_CLOCK_ROCR */\r
+#define MCF_CLOCK_ROCR_TRIM(x) (((x)&0x3FF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_CLOCK_LPDR */\r
+#define MCF_CLOCK_LPDR_LPD(x) (((x)&0xF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_CLOCK_CCHR */\r
+#define MCF_CLOCK_CCHR_CCHR(x) (((x)&0x7)<<0)\r
+\r
+/* Bit definitions and macros for MCF_CLOCK_CCLR */\r
+#define MCF_CLOCK_CCLR_OSCSEL0 (0x1)\r
+#define MCF_CLOCK_CCLR_OSCSEL1 (0x2)\r
+\r
+/* Bit definitions and macros for MCF_CLOCK_OCHR */\r
+#define MCF_CLOCK_OCHR_STBY (0x40)\r
+#define MCF_CLOCK_OCHR_OCOEN (0x80)\r
+\r
+/* Bit definitions and macros for MCF_CLOCK_OCLR */\r
+#define MCF_CLOCK_OCLR_RANGE (0x10)\r
+#define MCF_CLOCK_OCLR_LPEN (0x20)\r
+#define MCF_CLOCK_OCLR_REFS (0x40)\r
+#define MCF_CLOCK_OCLR_OSCEN (0x80)\r
+\r
+/* Bit definitions and macros for MCF_CLOCK_RTCCR */\r
+#define MCF_CLOCK_RTCCR_RTCSEL (0x1)\r
+#define MCF_CLOCK_RTCCR_LPEN (0x2)\r
+#define MCF_CLOCK_RTCCR_REFS (0x4)\r
+#define MCF_CLOCK_RTCCR_KHZEN (0x8)\r
+#define MCF_CLOCK_RTCCR_OSCEN (0x10)\r
+#define MCF_CLOCK_RTCCR_EXTALEN (0x40)\r
+\r
+/* Bit definitions and macros for MCF_CLOCK_BWCR */\r
+#define MCF_CLOCK_BWCR_BWDSEL (0x1)\r
+#define MCF_CLOCK_BWCR_BWDSTOP (0x2)\r
+\r
+\r
+#endif /* __MCF52259_CLOCK_H__ */\r
--- /dev/null
+/* Coldfire C Header File\r
+ * Copyright Freescale Semiconductor Inc\r
+ * All rights reserved.\r
+ *\r
+ * 2008/04/17 Revision: 0.2\r
+ *\r
+ * (c) Copyright UNIS, spol. s r.o. 1997-2008\r
+ * UNIS, spol. s r.o.\r
+ * Jundrovska 33\r
+ * 624 00 Brno\r
+ * Czech Republic\r
+ * http : www.processorexpert.com\r
+ * mail : info@processorexpert.com\r
+ */\r
+\r
+#ifndef __MCF52259_DMA_H__\r
+#define __MCF52259_DMA_H__\r
+\r
+\r
+/*********************************************************************\r
+*\r
+* DMA Controller (DMA)\r
+*\r
+*********************************************************************/\r
+\r
+/* Register read/write macros */\r
+#define MCF_DMA0_SAR (*(vuint32*)(0x40000100))\r
+#define MCF_DMA0_DAR (*(vuint32*)(0x40000104))\r
+#define MCF_DMA0_DSR (*(vuint8 *)(0x40000108))\r
+#define MCF_DMA0_BCR (*(vuint32*)(0x40000108))\r
+#define MCF_DMA0_DCR (*(vuint32*)(0x4000010C))\r
+\r
+#define MCF_DMA1_SAR (*(vuint32*)(0x40000110))\r
+#define MCF_DMA1_DAR (*(vuint32*)(0x40000114))\r
+#define MCF_DMA1_DSR (*(vuint8 *)(0x40000118))\r
+#define MCF_DMA1_BCR (*(vuint32*)(0x40000118))\r
+#define MCF_DMA1_DCR (*(vuint32*)(0x4000011C))\r
+\r
+#define MCF_DMA2_SAR (*(vuint32*)(0x40000120))\r
+#define MCF_DMA2_DAR (*(vuint32*)(0x40000124))\r
+#define MCF_DMA2_DSR (*(vuint8 *)(0x40000128))\r
+#define MCF_DMA2_BCR (*(vuint32*)(0x40000128))\r
+#define MCF_DMA2_DCR (*(vuint32*)(0x4000012C))\r
+\r
+#define MCF_DMA3_SAR (*(vuint32*)(0x40000130))\r
+#define MCF_DMA3_DAR (*(vuint32*)(0x40000134))\r
+#define MCF_DMA3_DSR (*(vuint8 *)(0x40000138))\r
+#define MCF_DMA3_BCR (*(vuint32*)(0x40000138))\r
+#define MCF_DMA3_DCR (*(vuint32*)(0x4000013C))\r
+\r
+#define MCF_DMA_SAR(x) (*(vuint32*)(0x40000100 + ((x)*0x10)))\r
+#define MCF_DMA_DAR(x) (*(vuint32*)(0x40000104 + ((x)*0x10)))\r
+#define MCF_DMA_DSR(x) (*(vuint8 *)(0x40000108 + ((x)*0x10)))\r
+#define MCF_DMA_BCR(x) (*(vuint32*)(0x40000108 + ((x)*0x10)))\r
+#define MCF_DMA_DCR(x) (*(vuint32*)(0x4000010C + ((x)*0x10)))\r
+\r
+\r
+/* Bit definitions and macros for MCF_DMA_SAR */\r
+#define MCF_DMA_SAR_SAR(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_DMA_DAR */\r
+#define MCF_DMA_DAR_DAR(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_DMA_DSR */\r
+#define MCF_DMA_DSR_DONE (0x1)\r
+#define MCF_DMA_DSR_BSY (0x2)\r
+#define MCF_DMA_DSR_REQ (0x4)\r
+#define MCF_DMA_DSR_BED (0x10)\r
+#define MCF_DMA_DSR_BES (0x20)\r
+#define MCF_DMA_DSR_CE (0x40)\r
+\r
+/* Bit definitions and macros for MCF_DMA_BCR */\r
+#define MCF_DMA_BCR_BCR(x) (((x)&0xFFFFFF)<<0)\r
+#define MCF_DMA_BCR_DSR(x) (((x)&0xFF)<<0x18)\r
+\r
+/* Bit definitions and macros for MCF_DMA_DCR */\r
+#define MCF_DMA_DCR_LCH2(x) (((x)&0x3)<<0)\r
+#define MCF_DMA_DCR_LCH2_CH0 (0)\r
+#define MCF_DMA_DCR_LCH2_CH1 (0x1)\r
+#define MCF_DMA_DCR_LCH2_CH2 (0x2)\r
+#define MCF_DMA_DCR_LCH2_CH3 (0x3)\r
+#define MCF_DMA_DCR_LCH1(x) (((x)&0x3)<<0x2)\r
+#define MCF_DMA_DCR_LCH1_CH0 (0)\r
+#define MCF_DMA_DCR_LCH1_CH1 (0x1)\r
+#define MCF_DMA_DCR_LCH1_CH2 (0x2)\r
+#define MCF_DMA_DCR_LCH1_CH3 (0x3)\r
+#define MCF_DMA_DCR_LINKCC(x) (((x)&0x3)<<0x4)\r
+#define MCF_DMA_DCR_D_REQ (0x80)\r
+#define MCF_DMA_DCR_DMOD(x) (((x)&0xF)<<0x8)\r
+#define MCF_DMA_DCR_DMOD_DIS (0)\r
+#define MCF_DMA_DCR_DMOD_16 (0x1)\r
+#define MCF_DMA_DCR_DMOD_32 (0x2)\r
+#define MCF_DMA_DCR_DMOD_64 (0x3)\r
+#define MCF_DMA_DCR_DMOD_128 (0x4)\r
+#define MCF_DMA_DCR_DMOD_256 (0x5)\r
+#define MCF_DMA_DCR_DMOD_512 (0x6)\r
+#define MCF_DMA_DCR_DMOD_1K (0x7)\r
+#define MCF_DMA_DCR_DMOD_2K (0x8)\r
+#define MCF_DMA_DCR_DMOD_4K (0x9)\r
+#define MCF_DMA_DCR_DMOD_8K (0xA)\r
+#define MCF_DMA_DCR_DMOD_16K (0xB)\r
+#define MCF_DMA_DCR_DMOD_32K (0xC)\r
+#define MCF_DMA_DCR_DMOD_64K (0xD)\r
+#define MCF_DMA_DCR_DMOD_128K (0xE)\r
+#define MCF_DMA_DCR_DMOD_256K (0xF)\r
+#define MCF_DMA_DCR_SMOD(x) (((x)&0xF)<<0xC)\r
+#define MCF_DMA_DCR_SMOD_DIS (0)\r
+#define MCF_DMA_DCR_SMOD_16 (0x1)\r
+#define MCF_DMA_DCR_SMOD_32 (0x2)\r
+#define MCF_DMA_DCR_SMOD_64 (0x3)\r
+#define MCF_DMA_DCR_SMOD_128 (0x4)\r
+#define MCF_DMA_DCR_SMOD_256 (0x5)\r
+#define MCF_DMA_DCR_SMOD_512 (0x6)\r
+#define MCF_DMA_DCR_SMOD_1K (0x7)\r
+#define MCF_DMA_DCR_SMOD_2K (0x8)\r
+#define MCF_DMA_DCR_SMOD_4K (0x9)\r
+#define MCF_DMA_DCR_SMOD_8K (0xA)\r
+#define MCF_DMA_DCR_SMOD_16K (0xB)\r
+#define MCF_DMA_DCR_SMOD_32K (0xC)\r
+#define MCF_DMA_DCR_SMOD_64K (0xD)\r
+#define MCF_DMA_DCR_SMOD_128K (0xE)\r
+#define MCF_DMA_DCR_SMOD_256K (0xF)\r
+#define MCF_DMA_DCR_START (0x10000)\r
+#define MCF_DMA_DCR_DSIZE(x) (((x)&0x3)<<0x11)\r
+#define MCF_DMA_DCR_DSIZE_LONG (0)\r
+#define MCF_DMA_DCR_DSIZE_BYTE (0x1)\r
+#define MCF_DMA_DCR_DSIZE_WORD (0x2)\r
+#define MCF_DMA_DCR_DSIZE_LINE (0x3)\r
+#define MCF_DMA_DCR_DINC (0x80000)\r
+#define MCF_DMA_DCR_SSIZE(x) (((x)&0x3)<<0x14)\r
+#define MCF_DMA_DCR_SSIZE_LONG (0)\r
+#define MCF_DMA_DCR_SSIZE_BYTE (0x1)\r
+#define MCF_DMA_DCR_SSIZE_WORD (0x2)\r
+#define MCF_DMA_DCR_SSIZE_LINE (0x3)\r
+#define MCF_DMA_DCR_SINC (0x400000)\r
+#define MCF_DMA_DCR_BWC(x) (((x)&0x7)<<0x19)\r
+#define MCF_DMA_DCR_BWC_16K (0x1)\r
+#define MCF_DMA_DCR_BWC_32K (0x2)\r
+#define MCF_DMA_DCR_BWC_64K (0x3)\r
+#define MCF_DMA_DCR_BWC_128K (0x4)\r
+#define MCF_DMA_DCR_BWC_256K (0x5)\r
+#define MCF_DMA_DCR_BWC_512K (0x6)\r
+#define MCF_DMA_DCR_BWC_1024K (0x7)\r
+#define MCF_DMA_DCR_AA (0x10000000)\r
+#define MCF_DMA_DCR_CS (0x20000000)\r
+#define MCF_DMA_DCR_EEXT (0x40000000)\r
+#define MCF_DMA_DCR_INT (0x80000000)\r
+\r
+\r
+#endif /* __MCF52259_DMA_H__ */\r
--- /dev/null
+/* Coldfire C Header File\r
+ * Copyright Freescale Semiconductor Inc\r
+ * All rights reserved.\r
+ *\r
+ * 2008/04/17 Revision: 0.2\r
+ *\r
+ * (c) Copyright UNIS, spol. s r.o. 1997-2008\r
+ * UNIS, spol. s r.o.\r
+ * Jundrovska 33\r
+ * 624 00 Brno\r
+ * Czech Republic\r
+ * http : www.processorexpert.com\r
+ * mail : info@processorexpert.com\r
+ */\r
+\r
+#ifndef __MCF52259_DTIM_H__\r
+#define __MCF52259_DTIM_H__\r
+\r
+\r
+/*********************************************************************\r
+*\r
+* DMA Timers (DTIM)\r
+*\r
+*********************************************************************/\r
+\r
+/* Register read/write macros */\r
+#define MCF_DTIM0_DTMR (*(vuint16*)(0x40000400))\r
+#define MCF_DTIM0_DTXMR (*(vuint8 *)(0x40000402))\r
+#define MCF_DTIM0_DTER (*(vuint8 *)(0x40000403))\r
+#define MCF_DTIM0_DTRR (*(vuint32*)(0x40000404))\r
+#define MCF_DTIM0_DTCR (*(vuint32*)(0x40000408))\r
+#define MCF_DTIM0_DTCN (*(vuint32*)(0x4000040C))\r
+\r
+#define MCF_DTIM1_DTMR (*(vuint16*)(0x40000440))\r
+#define MCF_DTIM1_DTXMR (*(vuint8 *)(0x40000442))\r
+#define MCF_DTIM1_DTER (*(vuint8 *)(0x40000443))\r
+#define MCF_DTIM1_DTRR (*(vuint32*)(0x40000444))\r
+#define MCF_DTIM1_DTCR (*(vuint32*)(0x40000448))\r
+#define MCF_DTIM1_DTCN (*(vuint32*)(0x4000044C))\r
+\r
+#define MCF_DTIM2_DTMR (*(vuint16*)(0x40000480))\r
+#define MCF_DTIM2_DTXMR (*(vuint8 *)(0x40000482))\r
+#define MCF_DTIM2_DTER (*(vuint8 *)(0x40000483))\r
+#define MCF_DTIM2_DTRR (*(vuint32*)(0x40000484))\r
+#define MCF_DTIM2_DTCR (*(vuint32*)(0x40000488))\r
+#define MCF_DTIM2_DTCN (*(vuint32*)(0x4000048C))\r
+\r
+#define MCF_DTIM3_DTMR (*(vuint16*)(0x400004C0))\r
+#define MCF_DTIM3_DTXMR (*(vuint8 *)(0x400004C2))\r
+#define MCF_DTIM3_DTER (*(vuint8 *)(0x400004C3))\r
+#define MCF_DTIM3_DTRR (*(vuint32*)(0x400004C4))\r
+#define MCF_DTIM3_DTCR (*(vuint32*)(0x400004C8))\r
+#define MCF_DTIM3_DTCN (*(vuint32*)(0x400004CC))\r
+\r
+#define MCF_DTIM_DTMR(x) (*(vuint16*)(0x40000400 + ((x)*0x40)))\r
+#define MCF_DTIM_DTXMR(x) (*(vuint8 *)(0x40000402 + ((x)*0x40)))\r
+#define MCF_DTIM_DTER(x) (*(vuint8 *)(0x40000403 + ((x)*0x40)))\r
+#define MCF_DTIM_DTRR(x) (*(vuint32*)(0x40000404 + ((x)*0x40)))\r
+#define MCF_DTIM_DTCR(x) (*(vuint32*)(0x40000408 + ((x)*0x40)))\r
+#define MCF_DTIM_DTCN(x) (*(vuint32*)(0x4000040C + ((x)*0x40)))\r
+\r
+\r
+/* Bit definitions and macros for MCF_DTIM_DTMR */\r
+#define MCF_DTIM_DTMR_RST (0x1)\r
+#define MCF_DTIM_DTMR_CLK(x) (((x)&0x3)<<0x1)\r
+#define MCF_DTIM_DTMR_CLK_STOP (0)\r
+#define MCF_DTIM_DTMR_CLK_DIV1 (0x2)\r
+#define MCF_DTIM_DTMR_CLK_DIV16 (0x4)\r
+#define MCF_DTIM_DTMR_CLK_DTIN (0x6)\r
+#define MCF_DTIM_DTMR_FRR (0x8)\r
+#define MCF_DTIM_DTMR_ORRI (0x10)\r
+#define MCF_DTIM_DTMR_OM (0x20)\r
+#define MCF_DTIM_DTMR_CE(x) (((x)&0x3)<<0x6)\r
+#define MCF_DTIM_DTMR_CE_NONE (0)\r
+#define MCF_DTIM_DTMR_CE_RISE (0x40)\r
+#define MCF_DTIM_DTMR_CE_FALL (0x80)\r
+#define MCF_DTIM_DTMR_CE_ANY (0xC0)\r
+#define MCF_DTIM_DTMR_PS(x) (((x)&0xFF)<<0x8)\r
+\r
+/* Bit definitions and macros for MCF_DTIM_DTXMR */\r
+#define MCF_DTIM_DTXMR_MODE16 (0x1)\r
+#define MCF_DTIM_DTXMR_HALTED (0x40)\r
+#define MCF_DTIM_DTXMR_DMAEN (0x80)\r
+\r
+/* Bit definitions and macros for MCF_DTIM_DTER */\r
+#define MCF_DTIM_DTER_CAP (0x1)\r
+#define MCF_DTIM_DTER_REF (0x2)\r
+\r
+/* Bit definitions and macros for MCF_DTIM_DTRR */\r
+#define MCF_DTIM_DTRR_REF(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_DTIM_DTCR */\r
+#define MCF_DTIM_DTCR_CAP(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_DTIM_DTCN */\r
+#define MCF_DTIM_DTCN_CNT(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+\r
+#endif /* __MCF52259_DTIM_H__ */\r
--- /dev/null
+/* Coldfire C Header File\r
+ * Copyright Freescale Semiconductor Inc\r
+ * All rights reserved.\r
+ *\r
+ * 2008/04/17 Revision: 0.2\r
+ *\r
+ * (c) Copyright UNIS, spol. s r.o. 1997-2008\r
+ * UNIS, spol. s r.o.\r
+ * Jundrovska 33\r
+ * 624 00 Brno\r
+ * Czech Republic\r
+ * http : www.processorexpert.com\r
+ * mail : info@processorexpert.com\r
+ */\r
+\r
+#ifndef __MCF52259_EPORT_H__\r
+#define __MCF52259_EPORT_H__\r
+\r
+\r
+/*********************************************************************\r
+*\r
+* Edge Port Module (EPORT)\r
+*\r
+*********************************************************************/\r
+\r
+/* Register read/write macros */\r
+#define MCF_EPORT_EPPAR (*(vuint16*)(0x40130000))\r
+#define MCF_EPORT_EPDDR (*(vuint8 *)(0x40130002))\r
+#define MCF_EPORT_EPIER (*(vuint8 *)(0x40130003))\r
+#define MCF_EPORT_EPDR (*(vuint8 *)(0x40130004))\r
+#define MCF_EPORT_EPPDR (*(vuint8 *)(0x40130005))\r
+#define MCF_EPORT_EPFR (*(vuint8 *)(0x40130006))\r
+\r
+\r
+\r
+/* Bit definitions and macros for MCF_EPORT_EPPAR */\r
+#define MCF_EPORT_EPPAR_EPPA1(x) (((x)&0x3)<<0x2)\r
+#define MCF_EPORT_EPPAR_EPPA1_LEVEL (0)\r
+#define MCF_EPORT_EPPAR_EPPA1_RISING (0x4)\r
+#define MCF_EPORT_EPPAR_EPPA1_FALLING (0x8)\r
+#define MCF_EPORT_EPPAR_EPPA1_BOTH (0xC)\r
+#define MCF_EPORT_EPPAR_EPPA2(x) (((x)&0x3)<<0x4)\r
+#define MCF_EPORT_EPPAR_EPPA2_LEVEL (0)\r
+#define MCF_EPORT_EPPAR_EPPA2_RISING (0x10)\r
+#define MCF_EPORT_EPPAR_EPPA2_FALLING (0x20)\r
+#define MCF_EPORT_EPPAR_EPPA2_BOTH (0x30)\r
+#define MCF_EPORT_EPPAR_EPPA3(x) (((x)&0x3)<<0x6)\r
+#define MCF_EPORT_EPPAR_EPPA3_LEVEL (0)\r
+#define MCF_EPORT_EPPAR_EPPA3_RISING (0x40)\r
+#define MCF_EPORT_EPPAR_EPPA3_FALLING (0x80)\r
+#define MCF_EPORT_EPPAR_EPPA3_BOTH (0xC0)\r
+#define MCF_EPORT_EPPAR_EPPA4(x) (((x)&0x3)<<0x8)\r
+#define MCF_EPORT_EPPAR_EPPA4_LEVEL (0)\r
+#define MCF_EPORT_EPPAR_EPPA4_RISING (0x100)\r
+#define MCF_EPORT_EPPAR_EPPA4_FALLING (0x200)\r
+#define MCF_EPORT_EPPAR_EPPA4_BOTH (0x300)\r
+#define MCF_EPORT_EPPAR_EPPA5(x) (((x)&0x3)<<0xA)\r
+#define MCF_EPORT_EPPAR_EPPA5_LEVEL (0)\r
+#define MCF_EPORT_EPPAR_EPPA5_RISING (0x400)\r
+#define MCF_EPORT_EPPAR_EPPA5_FALLING (0x800)\r
+#define MCF_EPORT_EPPAR_EPPA5_BOTH (0xC00)\r
+#define MCF_EPORT_EPPAR_EPPA6(x) (((x)&0x3)<<0xC)\r
+#define MCF_EPORT_EPPAR_EPPA6_LEVEL (0)\r
+#define MCF_EPORT_EPPAR_EPPA6_RISING (0x1000)\r
+#define MCF_EPORT_EPPAR_EPPA6_FALLING (0x2000)\r
+#define MCF_EPORT_EPPAR_EPPA6_BOTH (0x3000)\r
+#define MCF_EPORT_EPPAR_EPPA7(x) (((x)&0x3)<<0xE)\r
+#define MCF_EPORT_EPPAR_EPPA7_LEVEL (0)\r
+#define MCF_EPORT_EPPAR_EPPA7_RISING (0x4000)\r
+#define MCF_EPORT_EPPAR_EPPA7_FALLING (0x8000)\r
+#define MCF_EPORT_EPPAR_EPPA7_BOTH (0xC000)\r
+#define MCF_EPORT_EPPAR_LEVEL (0)\r
+#define MCF_EPORT_EPPAR_RISING (0x1)\r
+#define MCF_EPORT_EPPAR_FALLING (0x2)\r
+#define MCF_EPORT_EPPAR_BOTH (0x3)\r
+\r
+/* Bit definitions and macros for MCF_EPORT_EPDDR */\r
+#define MCF_EPORT_EPDDR_EPDD1 (0x2)\r
+#define MCF_EPORT_EPDDR_EPDD2 (0x4)\r
+#define MCF_EPORT_EPDDR_EPDD3 (0x8)\r
+#define MCF_EPORT_EPDDR_EPDD4 (0x10)\r
+#define MCF_EPORT_EPDDR_EPDD5 (0x20)\r
+#define MCF_EPORT_EPDDR_EPDD6 (0x40)\r
+#define MCF_EPORT_EPDDR_EPDD7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_EPORT_EPIER */\r
+#define MCF_EPORT_EPIER_EPIE1 (0x2)\r
+#define MCF_EPORT_EPIER_EPIE2 (0x4)\r
+#define MCF_EPORT_EPIER_EPIE3 (0x8)\r
+#define MCF_EPORT_EPIER_EPIE4 (0x10)\r
+#define MCF_EPORT_EPIER_EPIE5 (0x20)\r
+#define MCF_EPORT_EPIER_EPIE6 (0x40)\r
+#define MCF_EPORT_EPIER_EPIE7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_EPORT_EPDR */\r
+#define MCF_EPORT_EPDR_EPD1 (0x2)\r
+#define MCF_EPORT_EPDR_EPD2 (0x4)\r
+#define MCF_EPORT_EPDR_EPD3 (0x8)\r
+#define MCF_EPORT_EPDR_EPD4 (0x10)\r
+#define MCF_EPORT_EPDR_EPD5 (0x20)\r
+#define MCF_EPORT_EPDR_EPD6 (0x40)\r
+#define MCF_EPORT_EPDR_EPD7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_EPORT_EPPDR */\r
+#define MCF_EPORT_EPPDR_EPPD1 (0x2)\r
+#define MCF_EPORT_EPPDR_EPPD2 (0x4)\r
+#define MCF_EPORT_EPPDR_EPPD3 (0x8)\r
+#define MCF_EPORT_EPPDR_EPPD4 (0x10)\r
+#define MCF_EPORT_EPPDR_EPPD5 (0x20)\r
+#define MCF_EPORT_EPPDR_EPPD6 (0x40)\r
+#define MCF_EPORT_EPPDR_EPPD7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_EPORT_EPFR */\r
+#define MCF_EPORT_EPFR_EPF1 (0x2)\r
+#define MCF_EPORT_EPFR_EPF2 (0x4)\r
+#define MCF_EPORT_EPFR_EPF3 (0x8)\r
+#define MCF_EPORT_EPFR_EPF4 (0x10)\r
+#define MCF_EPORT_EPFR_EPF5 (0x20)\r
+#define MCF_EPORT_EPFR_EPF6 (0x40)\r
+#define MCF_EPORT_EPFR_EPF7 (0x80)\r
+\r
+\r
+#endif /* __MCF52259_EPORT_H__ */\r
--- /dev/null
+/* Coldfire C Header File\r
+ * Copyright Freescale Semiconductor Inc\r
+ * All rights reserved.\r
+ *\r
+ * 2008/04/17 Revision: 0.2\r
+ *\r
+ * (c) Copyright UNIS, spol. s r.o. 1997-2008\r
+ * UNIS, spol. s r.o.\r
+ * Jundrovska 33\r
+ * 624 00 Brno\r
+ * Czech Republic\r
+ * http : www.processorexpert.com\r
+ * mail : info@processorexpert.com\r
+ */\r
+\r
+#ifndef __MCF52259_FBCS_H__\r
+#define __MCF52259_FBCS_H__\r
+\r
+\r
+/*********************************************************************\r
+*\r
+* Mini-FlexBus Chip Select Module (FBCS)\r
+*\r
+*********************************************************************/\r
+\r
+/* Register read/write macros */\r
+#define MCF_FBCS0_CSAR (*(vuint32*)(0x40000080))\r
+#define MCF_FBCS0_CSMR (*(vuint32*)(0x40000084))\r
+#define MCF_FBCS0_CSCR (*(vuint32*)(0x40000088))\r
+\r
+#define MCF_FBCS1_CSAR (*(vuint32*)(0x4000008C))\r
+#define MCF_FBCS1_CSMR (*(vuint32*)(0x40000090))\r
+#define MCF_FBCS1_CSCR (*(vuint32*)(0x40000094))\r
+\r
+#define MCF_FBCS_CSAR(x) (*(vuint32*)(0x40000080 + ((x)*0xC)))\r
+#define MCF_FBCS_CSMR(x) (*(vuint32*)(0x40000084 + ((x)*0xC)))\r
+#define MCF_FBCS_CSCR(x) (*(vuint32*)(0x40000088 + ((x)*0xC)))\r
+\r
+\r
+/* Bit definitions and macros for MCF_FBCS_CSAR */\r
+#define MCF_FBCS_CSAR_BA(x) ((x)&0xFFFF0000)\r
+\r
+/* Bit definitions and macros for MCF_FBCS_CSMR */\r
+#define MCF_FBCS_CSMR_V (0x1)\r
+#define MCF_FBCS_CSMR_WP (0x100)\r
+#define MCF_FBCS_CSMR_BAM(x) (((x)&0xFFFF)<<0x10)\r
+#define MCF_FBCS_CSMR_BAM_4G (0xFFFF0000)\r
+#define MCF_FBCS_CSMR_BAM_2G (0x7FFF0000)\r
+#define MCF_FBCS_CSMR_BAM_1G (0x3FFF0000)\r
+#define MCF_FBCS_CSMR_BAM_1024M (0x3FFF0000)\r
+#define MCF_FBCS_CSMR_BAM_512M (0x1FFF0000)\r
+#define MCF_FBCS_CSMR_BAM_256M (0xFFF0000)\r
+#define MCF_FBCS_CSMR_BAM_128M (0x7FF0000)\r
+#define MCF_FBCS_CSMR_BAM_64M (0x3FF0000)\r
+#define MCF_FBCS_CSMR_BAM_32M (0x1FF0000)\r
+#define MCF_FBCS_CSMR_BAM_16M (0xFF0000)\r
+#define MCF_FBCS_CSMR_BAM_8M (0x7F0000)\r
+#define MCF_FBCS_CSMR_BAM_4M (0x3F0000)\r
+#define MCF_FBCS_CSMR_BAM_2M (0x1F0000)\r
+#define MCF_FBCS_CSMR_BAM_1M (0xF0000)\r
+#define MCF_FBCS_CSMR_BAM_1024K (0xF0000)\r
+#define MCF_FBCS_CSMR_BAM_512K (0x70000)\r
+#define MCF_FBCS_CSMR_BAM_256K (0x30000)\r
+#define MCF_FBCS_CSMR_BAM_128K (0x10000)\r
+#define MCF_FBCS_CSMR_BAM_64K (0)\r
+\r
+/* Bit definitions and macros for MCF_FBCS_CSCR */\r
+#define MCF_FBCS_CSCR_BSTW (0x8)\r
+#define MCF_FBCS_CSCR_BSTR (0x10)\r
+#define MCF_FBCS_CSCR_PS(x) (((x)&0x3)<<0x6)\r
+#define MCF_FBCS_CSCR_PS_8 (0x40)\r
+#define MCF_FBCS_CSCR_PS_16 (0x80)\r
+#define MCF_FBCS_CSCR_AA (0x100)\r
+#define MCF_FBCS_CSCR_MUX (0x200)\r
+#define MCF_FBCS_CSCR_WS(x) (((x)&0x3F)<<0xA)\r
+#define MCF_FBCS_CSCR_WRAH(x) (((x)&0x3)<<0x10)\r
+#define MCF_FBCS_CSCR_RDAH(x) (((x)&0x3)<<0x12)\r
+#define MCF_FBCS_CSCR_ASET(x) (((x)&0x3)<<0x14)\r
+#define MCF_FBCS_CSCR_SWSEN (0x800000)\r
+#define MCF_FBCS_CSCR_SWS(x) (((x)&0x3F)<<0x1A)\r
+\r
+\r
+#endif /* __MCF52259_FBCS_H__ */\r
--- /dev/null
+/* Coldfire C Header File\r
+ * Copyright Freescale Semiconductor Inc\r
+ * All rights reserved.\r
+ *\r
+ * 2008/04/17 Revision: 0.2\r
+ *\r
+ * (c) Copyright UNIS, spol. s r.o. 1997-2008\r
+ * UNIS, spol. s r.o.\r
+ * Jundrovska 33\r
+ * 624 00 Brno\r
+ * Czech Republic\r
+ * http : www.processorexpert.com\r
+ * mail : info@processorexpert.com\r
+ */\r
+\r
+#ifndef __MCF52259_FEC_H__\r
+#define __MCF52259_FEC_H__\r
+\r
+\r
+/*********************************************************************\r
+*\r
+* Fast Ethernet Controller(FEC)\r
+*\r
+*********************************************************************/\r
+\r
+/* Register read/write macros */\r
+#define MCF_FEC_EIR (*(vuint32*)(0x40001004))\r
+#define MCF_FEC_EIMR (*(vuint32*)(0x40001008))\r
+#define MCF_FEC_RDAR (*(vuint32*)(0x40001010))\r
+#define MCF_FEC_TDAR (*(vuint32*)(0x40001014))\r
+#define MCF_FEC_ECR (*(vuint32*)(0x40001024))\r
+#define MCF_FEC_MMFR (*(vuint32*)(0x40001040))\r
+#define MCF_FEC_MSCR (*(vuint32*)(0x40001044))\r
+#define MCF_FEC_MIBC (*(vuint32*)(0x40001064))\r
+#define MCF_FEC_RCR (*(vuint32*)(0x40001084))\r
+#define MCF_FEC_TCR (*(vuint32*)(0x400010C4))\r
+#define MCF_FEC_PALR (*(vuint32*)(0x400010E4))\r
+#define MCF_FEC_PAUR (*(vuint32*)(0x400010E8))\r
+#define MCF_FEC_OPD (*(vuint32*)(0x400010EC))\r
+#define MCF_FEC_IAUR (*(vuint32*)(0x40001118))\r
+#define MCF_FEC_IALR (*(vuint32*)(0x4000111C))\r
+#define MCF_FEC_GAUR (*(vuint32*)(0x40001120))\r
+#define MCF_FEC_GALR (*(vuint32*)(0x40001124))\r
+#define MCF_FEC_TFWR (*(vuint32*)(0x40001144))\r
+#define MCF_FEC_FRBR (*(vuint32*)(0x4000114C))\r
+#define MCF_FEC_FRSR (*(vuint32*)(0x40001150))\r
+#define MCF_FEC_ERDSR (*(vuint32*)(0x40001180))\r
+#define MCF_FEC_ETSDR (*(vuint32*)(0x40001184))\r
+#define MCF_FEC_EMRBR (*(vuint32*)(0x40001188))\r
+#define MCF_FEC_RMON_T_DROP (*(vuint32*)(0x40001200))\r
+#define MCF_FEC_RMON_T_PACKETS (*(vuint32*)(0x40001204))\r
+#define MCF_FEC_RMON_T_BC_PKT (*(vuint32*)(0x40001208))\r
+#define MCF_FEC_RMON_T_MC_PKT (*(vuint32*)(0x4000120C))\r
+#define MCF_FEC_RMON_T_CRC_ALIGN (*(vuint32*)(0x40001210))\r
+#define MCF_FEC_RMON_T_UNDERSIZE (*(vuint32*)(0x40001214))\r
+#define MCF_FEC_RMON_T_OVERSIZE (*(vuint32*)(0x40001218))\r
+#define MCF_FEC_RMON_T_FRAG (*(vuint32*)(0x4000121C))\r
+#define MCF_FEC_RMON_T_JAB (*(vuint32*)(0x40001220))\r
+#define MCF_FEC_RMON_T_COL (*(vuint32*)(0x40001224))\r
+#define MCF_FEC_RMON_T_P64 (*(vuint32*)(0x40001228))\r
+#define MCF_FEC_RMON_T_P65TO127 (*(vuint32*)(0x4000122C))\r
+#define MCF_FEC_RMON_T_P128TO255 (*(vuint32*)(0x40001230))\r
+#define MCF_FEC_RMON_T_P256TO511 (*(vuint32*)(0x40001234))\r
+#define MCF_FEC_RMON_T_P512TO1023 (*(vuint32*)(0x40001238))\r
+#define MCF_FEC_RMON_T_P1024TO2047 (*(vuint32*)(0x4000123C))\r
+#define MCF_FEC_RMON_T_P_GTE2048 (*(vuint32*)(0x40001240))\r
+#define MCF_FEC_RMON_T_OCTETS (*(vuint32*)(0x40001244))\r
+#define MCF_FEC_IEEE_T_DROP (*(vuint32*)(0x40001248))\r
+#define MCF_FEC_IEEE_T_FRAME_OK (*(vuint32*)(0x4000124C))\r
+#define MCF_FEC_IEEE_T_1COL (*(vuint32*)(0x40001250))\r
+#define MCF_FEC_IEEE_T_MCOL (*(vuint32*)(0x40001254))\r
+#define MCF_FEC_IEEE_T_DEF (*(vuint32*)(0x40001258))\r
+#define MCF_FEC_IEEE_T_LCOL (*(vuint32*)(0x4000125C))\r
+#define MCF_FEC_IEEE_T_EXCOL (*(vuint32*)(0x40001260))\r
+#define MCF_FEC_IEEE_T_MACERR (*(vuint32*)(0x40001264))\r
+#define MCF_FEC_IEEE_T_CSERR (*(vuint32*)(0x40001268))\r
+#define MCF_FEC_IEEE_T_SQE (*(vuint32*)(0x4000126C))\r
+#define MCF_FEC_IEEE_T_FDXFC (*(vuint32*)(0x40001270))\r
+#define MCF_FEC_IEEE_T_OCTETS_OK (*(vuint32*)(0x40001274))\r
+#define MCF_FEC_RMON_R_PACKETS (*(vuint32*)(0x40001284))\r
+#define MCF_FEC_RMON_R_BC_PKT (*(vuint32*)(0x40001288))\r
+#define MCF_FEC_RMON_R_MC_PKT (*(vuint32*)(0x4000128C))\r
+#define MCF_FEC_RMON_R_CRC_ALIGN (*(vuint32*)(0x40001290))\r
+#define MCF_FEC_RMON_R_UNDERSIZE (*(vuint32*)(0x40001294))\r
+#define MCF_FEC_RMON_R_OVERSIZE (*(vuint32*)(0x40001298))\r
+#define MCF_FEC_RMON_R_FRAG (*(vuint32*)(0x4000129C))\r
+#define MCF_FEC_RMON_R_JAB (*(vuint32*)(0x400012A0))\r
+#define MCF_FEC_RMON_R_RESVD_0 (*(vuint32*)(0x400012A4))\r
+#define MCF_FEC_RMON_R_P64 (*(vuint32*)(0x400012A8))\r
+#define MCF_FEC_RMON_R_P65TO127 (*(vuint32*)(0x400012AC))\r
+#define MCF_FEC_RMON_R_P128TO255 (*(vuint32*)(0x400012B0))\r
+#define MCF_FEC_RMON_R_P256TO511 (*(vuint32*)(0x400012B4))\r
+#define MCF_FEC_RMON_R_P512TO1023 (*(vuint32*)(0x400012B8))\r
+#define MCF_FEC_RMON_R_P1024TO2047 (*(vuint32*)(0x400012BC))\r
+#define MCF_FEC_RMON_R_P_GTE2048 (*(vuint32*)(0x400012C0))\r
+#define MCF_FEC_RMON_R_OCTETS (*(vuint32*)(0x400012C4))\r
+#define MCF_FEC_IEEE_R_DROP (*(vuint32*)(0x400012C8))\r
+#define MCF_FEC_IEEE_R_FRAME_OK (*(vuint32*)(0x400012CC))\r
+#define MCF_FEC_IEEE_R_CRC (*(vuint32*)(0x400012D0))\r
+#define MCF_FEC_IEEE_R_ALIGN (*(vuint32*)(0x400012D4))\r
+#define MCF_FEC_IEEE_R_MACERR (*(vuint32*)(0x400012D8))\r
+#define MCF_FEC_IEEE_R_FDXFC (*(vuint32*)(0x400012DC))\r
+#define MCF_FEC_IEEE_R_OCTETS_OK (*(vuint32*)(0x400012E0))\r
+\r
+\r
+\r
+/* Bit definitions and macros for MCF_FEC_EIR */\r
+#define MCF_FEC_EIR_UN (0x80000)\r
+#define MCF_FEC_EIR_RL (0x100000)\r
+#define MCF_FEC_EIR_LC (0x200000)\r
+#define MCF_FEC_EIR_EBERR (0x400000)\r
+#define MCF_FEC_EIR_MII (0x800000)\r
+#define MCF_FEC_EIR_RXB (0x1000000)\r
+#define MCF_FEC_EIR_RXF (0x2000000)\r
+#define MCF_FEC_EIR_TXB (0x4000000)\r
+#define MCF_FEC_EIR_TXF (0x8000000)\r
+#define MCF_FEC_EIR_GRA (0x10000000)\r
+#define MCF_FEC_EIR_BABT (0x20000000)\r
+#define MCF_FEC_EIR_BABR (0x40000000)\r
+#define MCF_FEC_EIR_HBERR (0x80000000)\r
+#define MCF_FEC_EIR_CLEAR_ALL (0xFFFFFFFF)\r
+\r
+/* Bit definitions and macros for MCF_FEC_EIMR */\r
+#define MCF_FEC_EIMR_UN (0x80000)\r
+#define MCF_FEC_EIMR_RL (0x100000)\r
+#define MCF_FEC_EIMR_LC (0x200000)\r
+#define MCF_FEC_EIMR_EBERR (0x400000)\r
+#define MCF_FEC_EIMR_MII (0x800000)\r
+#define MCF_FEC_EIMR_RXB (0x1000000)\r
+#define MCF_FEC_EIMR_RXF (0x2000000)\r
+#define MCF_FEC_EIMR_TXB (0x4000000)\r
+#define MCF_FEC_EIMR_TXF (0x8000000)\r
+#define MCF_FEC_EIMR_GRA (0x10000000)\r
+#define MCF_FEC_EIMR_BABT (0x20000000)\r
+#define MCF_FEC_EIMR_BABR (0x40000000)\r
+#define MCF_FEC_EIMR_HBERR (0x80000000)\r
+#define MCF_FEC_EIMR_MASK_ALL (0)\r
+#define MCF_FEC_EIMR_UNMASK_ALL (0xFFFFFFFF)\r
+\r
+/* Bit definitions and macros for MCF_FEC_RDAR */\r
+#define MCF_FEC_RDAR_R_DES_ACTIVE (0x1000000)\r
+\r
+/* Bit definitions and macros for MCF_FEC_TDAR */\r
+#define MCF_FEC_TDAR_X_DES_ACTIVE (0x1000000)\r
+\r
+/* Bit definitions and macros for MCF_FEC_ECR */\r
+#define MCF_FEC_ECR_RESET (0x1)\r
+#define MCF_FEC_ECR_ETHER_EN (0x2)\r
+\r
+/* Bit definitions and macros for MCF_FEC_MMFR */\r
+#define MCF_FEC_MMFR_DATA(x) (((x)&0xFFFF)<<0)\r
+#define MCF_FEC_MMFR_TA(x) (((x)&0x3)<<0x10)\r
+#define MCF_FEC_MMFR_TA_10 (0x20000)\r
+#define MCF_FEC_MMFR_RA(x) (((x)&0x1F)<<0x12)\r
+#define MCF_FEC_MMFR_PA(x) (((x)&0x1F)<<0x17)\r
+#define MCF_FEC_MMFR_OP(x) (((x)&0x3)<<0x1C)\r
+#define MCF_FEC_MMFR_OP_READ (0x20000000)\r
+#define MCF_FEC_MMFR_OP_WRITE (0x10000000)\r
+#define MCF_FEC_MMFR_ST(x) (((x)&0x3)<<0x1E)\r
+#define MCF_FEC_MMFR_ST_01 (0x40000000)\r
+\r
+/* Bit definitions and macros for MCF_FEC_MSCR */\r
+#define MCF_FEC_MSCR_MII_SPEED(x) (((x)&0x3F)<<0x1)\r
+#define MCF_FEC_MSCR_DIS_PREAMBLE (0x80)\r
+\r
+/* Bit definitions and macros for MCF_FEC_MIBC */\r
+#define MCF_FEC_MIBC_MIB_IDLE (0x40000000)\r
+#define MCF_FEC_MIBC_MIB_DISABLE (0x80000000)\r
+\r
+/* Bit definitions and macros for MCF_FEC_RCR */\r
+#define MCF_FEC_RCR_LOOP (0x1)\r
+#define MCF_FEC_RCR_DRT (0x2)\r
+#define MCF_FEC_RCR_MII_MODE (0x4)\r
+#define MCF_FEC_RCR_PROM (0x8)\r
+#define MCF_FEC_RCR_BC_REJ (0x10)\r
+#define MCF_FEC_RCR_FCE (0x20)\r
+#define MCF_FEC_RCR_MAX_FL(x) (((x)&0x7FF)<<0x10)\r
+\r
+/* Bit definitions and macros for MCF_FEC_TCR */\r
+#define MCF_FEC_TCR_GTS (0x1)\r
+#define MCF_FEC_TCR_HBC (0x2)\r
+#define MCF_FEC_TCR_FDEN (0x4)\r
+#define MCF_FEC_TCR_TFC_PAUSE (0x8)\r
+#define MCF_FEC_TCR_RFC_PAUSE (0x10)\r
+\r
+/* Bit definitions and macros for MCF_FEC_PALR */\r
+#define MCF_FEC_PALR_PADDR1(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_PAUR */\r
+#define MCF_FEC_PAUR_TYPE(x) (((x)&0xFFFF)<<0)\r
+#define MCF_FEC_PAUR_PADDR2(x) (((x)&0xFFFF)<<0x10)\r
+\r
+/* Bit definitions and macros for MCF_FEC_OPD */\r
+#define MCF_FEC_OPD_PAUSE_DUR(x) (((x)&0xFFFF)<<0)\r
+#define MCF_FEC_OPD_OPCODE(x) (((x)&0xFFFF)<<0x10)\r
+\r
+/* Bit definitions and macros for MCF_FEC_IAUR */\r
+#define MCF_FEC_IAUR_IADDR1(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_IALR */\r
+#define MCF_FEC_IALR_IADDR2(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_GAUR */\r
+#define MCF_FEC_GAUR_GADDR1(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_GALR */\r
+#define MCF_FEC_GALR_GADDR2(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_TFWR */\r
+#define MCF_FEC_TFWR_X_WMRK(x) (((x)&0x3)<<0)\r
+#define MCF_FEC_TFWR_X_WMRK_64 (0)\r
+#define MCF_FEC_TFWR_X_WMRK_128 (0x2)\r
+#define MCF_FEC_TFWR_X_WMRK_192 (0x3)\r
+\r
+/* Bit definitions and macros for MCF_FEC_FRBR */\r
+#define MCF_FEC_FRBR_R_BOUND(x) (((x)&0xFF)<<0x2)\r
+\r
+/* Bit definitions and macros for MCF_FEC_FRSR */\r
+#define MCF_FEC_FRSR_R_FSTART(x) (((x)&0xFF)<<0x2)\r
+\r
+/* Bit definitions and macros for MCF_FEC_ERDSR */\r
+#define MCF_FEC_ERDSR_R_DES_START(x) (((x)&0x3FFFFFFF)<<0x2)\r
+\r
+/* Bit definitions and macros for MCF_FEC_ETSDR */\r
+#define MCF_FEC_ETSDR_X_DES_START(x) (((x)&0x3FFFFFFF)<<0x2)\r
+\r
+/* Bit definitions and macros for MCF_FEC_EMRBR */\r
+#define MCF_FEC_EMRBR_R_BUF_SIZE(x) (((x)&0x7F)<<0x4)\r
+\r
+/* Bit definitions and macros for MCF_FEC_RMON_T_DROP */\r
+#define MCF_FEC_RMON_T_DROP_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_RMON_T_PACKETS */\r
+#define MCF_FEC_RMON_T_PACKETS_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_RMON_T_BC_PKT */\r
+#define MCF_FEC_RMON_T_BC_PKT_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_RMON_T_MC_PKT */\r
+#define MCF_FEC_RMON_T_MC_PKT_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_RMON_T_CRC_ALIGN */\r
+#define MCF_FEC_RMON_T_CRC_ALIGN_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_RMON_T_UNDERSIZE */\r
+#define MCF_FEC_RMON_T_UNDERSIZE_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_RMON_T_OVERSIZE */\r
+#define MCF_FEC_RMON_T_OVERSIZE_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_RMON_T_FRAG */\r
+#define MCF_FEC_RMON_T_FRAG_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_RMON_T_JAB */\r
+#define MCF_FEC_RMON_T_JAB_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_RMON_T_COL */\r
+#define MCF_FEC_RMON_T_COL_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_RMON_T_P64 */\r
+#define MCF_FEC_RMON_T_P64_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_RMON_T_P65TO127 */\r
+#define MCF_FEC_RMON_T_P65TO127_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_RMON_T_P128TO255 */\r
+#define MCF_FEC_RMON_T_P128TO255_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_RMON_T_P256TO511 */\r
+#define MCF_FEC_RMON_T_P256TO511_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_RMON_T_P512TO1023 */\r
+#define MCF_FEC_RMON_T_P512TO1023_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_RMON_T_P1024TO2047 */\r
+#define MCF_FEC_RMON_T_P1024TO2047_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_RMON_T_P_GTE2048 */\r
+#define MCF_FEC_RMON_T_P_GTE2048_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_RMON_T_OCTETS */\r
+#define MCF_FEC_RMON_T_OCTETS_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_IEEE_T_DROP */\r
+#define MCF_FEC_IEEE_T_DROP_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_IEEE_T_FRAME_OK */\r
+#define MCF_FEC_IEEE_T_FRAME_OK_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_IEEE_T_1COL */\r
+#define MCF_FEC_IEEE_T_1COL_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_IEEE_T_MCOL */\r
+#define MCF_FEC_IEEE_T_MCOL_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_IEEE_T_DEF */\r
+#define MCF_FEC_IEEE_T_DEF_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_IEEE_T_LCOL */\r
+#define MCF_FEC_IEEE_T_LCOL_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_IEEE_T_EXCOL */\r
+#define MCF_FEC_IEEE_T_EXCOL_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_IEEE_T_MACERR */\r
+#define MCF_FEC_IEEE_T_MACERR_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_IEEE_T_CSERR */\r
+#define MCF_FEC_IEEE_T_CSERR_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_IEEE_T_SQE */\r
+#define MCF_FEC_IEEE_T_SQE_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_IEEE_T_FDXFC */\r
+#define MCF_FEC_IEEE_T_FDXFC_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_IEEE_T_OCTETS_OK */\r
+#define MCF_FEC_IEEE_T_OCTETS_OK_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_RMON_R_PACKETS */\r
+#define MCF_FEC_RMON_R_PACKETS_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_RMON_R_BC_PKT */\r
+#define MCF_FEC_RMON_R_BC_PKT_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_RMON_R_MC_PKT */\r
+#define MCF_FEC_RMON_R_MC_PKT_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_RMON_R_CRC_ALIGN */\r
+#define MCF_FEC_RMON_R_CRC_ALIGN_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_RMON_R_UNDERSIZE */\r
+#define MCF_FEC_RMON_R_UNDERSIZE_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_RMON_R_OVERSIZE */\r
+#define MCF_FEC_RMON_R_OVERSIZE_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_RMON_R_FRAG */\r
+#define MCF_FEC_RMON_R_FRAG_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_RMON_R_JAB */\r
+#define MCF_FEC_RMON_R_JAB_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_RMON_R_RESVD_0 */\r
+#define MCF_FEC_RMON_R_RESVD_0_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_RMON_R_P64 */\r
+#define MCF_FEC_RMON_R_P64_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_RMON_R_P65TO127 */\r
+#define MCF_FEC_RMON_R_P65TO127_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_RMON_R_P128TO255 */\r
+#define MCF_FEC_RMON_R_P128TO255_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_RMON_R_P256TO511 */\r
+#define MCF_FEC_RMON_R_P256TO511_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_RMON_R_P512TO1023 */\r
+#define MCF_FEC_RMON_R_P512TO1023_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_RMON_R_P1024TO2047 */\r
+#define MCF_FEC_RMON_R_P1024TO2047_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_RMON_R_P_GTE2048 */\r
+#define MCF_FEC_RMON_R_P_GTE2048_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_RMON_R_OCTETS */\r
+#define MCF_FEC_RMON_R_OCTETS_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_IEEE_R_DROP */\r
+#define MCF_FEC_IEEE_R_DROP_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_IEEE_R_FRAME_OK */\r
+#define MCF_FEC_IEEE_R_FRAME_OK_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_IEEE_R_CRC */\r
+#define MCF_FEC_IEEE_R_CRC_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_IEEE_R_ALIGN */\r
+#define MCF_FEC_IEEE_R_ALIGN_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_IEEE_R_MACERR */\r
+#define MCF_FEC_IEEE_R_MACERR_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_IEEE_R_FDXFC */\r
+#define MCF_FEC_IEEE_R_FDXFC_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_IEEE_R_OCTETS_OK */\r
+#define MCF_FEC_IEEE_R_OCTETS_OK_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+\r
+#endif /* __MCF52259_FEC_H__ */\r
--- /dev/null
+/* Coldfire C Header File\r
+ * Copyright Freescale Semiconductor Inc\r
+ * All rights reserved.\r
+ *\r
+ * 2008/04/17 Revision: 0.2\r
+ *\r
+ * (c) Copyright UNIS, spol. s r.o. 1997-2008\r
+ * UNIS, spol. s r.o.\r
+ * Jundrovska 33\r
+ * 624 00 Brno\r
+ * Czech Republic\r
+ * http : www.processorexpert.com\r
+ * mail : info@processorexpert.com\r
+ */\r
+\r
+#ifndef __MCF52259_FlexCAN_H__\r
+#define __MCF52259_FlexCAN_H__\r
+\r
+\r
+/*********************************************************************\r
+*\r
+* Flex Controller Area Network (FlexCAN)\r
+*\r
+*********************************************************************/\r
+\r
+/* Register read/write macros */\r
+#define MCF_FlexCAN_CANMCR (*(vuint32*)(0x40170000))\r
+#define MCF_FlexCAN_CANCTRL (*(vuint32*)(0x40170004))\r
+#define MCF_FlexCAN_TIMER (*(vuint32*)(0x40170008))\r
+#define MCF_FlexCAN_RXGMASK (*(vuint32*)(0x40170010))\r
+#define MCF_FlexCAN_RX14MASK (*(vuint32*)(0x40170014))\r
+#define MCF_FlexCAN_RX15MASK (*(vuint32*)(0x40170018))\r
+#define MCF_FlexCAN_ERRCNT (*(vuint32*)(0x4017001C))\r
+#define MCF_FlexCAN_ERRSTAT (*(vuint32*)(0x40170020))\r
+#define MCF_FlexCAN_IMASK (*(vuint32*)(0x40170028))\r
+#define MCF_FlexCAN_IFLAG (*(vuint32*)(0x40170030))\r
+\r
+\r
+\r
+/* Bit definitions and macros for MCF_FlexCAN_CANMCR */\r
+#define MCF_FlexCAN_CANMCR_MAXMB(x) (((x)&0xF)<<0)\r
+#define MCF_FlexCAN_CANMCR_LPMACK (0x100000)\r
+#define MCF_FlexCAN_CANMCR_SUPV (0x800000)\r
+#define MCF_FlexCAN_CANMCR_FRZACK (0x1000000)\r
+#define MCF_FlexCAN_CANMCR_SOFTRST (0x2000000)\r
+#define MCF_FlexCAN_CANMCR_NOTRDY (0x8000000)\r
+#define MCF_FlexCAN_CANMCR_HALT (0x10000000)\r
+#define MCF_FlexCAN_CANMCR_FRZ (0x40000000)\r
+#define MCF_FlexCAN_CANMCR_MDIS (0x80000000)\r
+\r
+/* Bit definitions and macros for MCF_FlexCAN_CANCTRL */\r
+#define MCF_FlexCAN_CANCTRL_PROPSEG(x) (((x)&0x7)<<0)\r
+#define MCF_FlexCAN_CANCTRL_LOM (0x8)\r
+#define MCF_FlexCAN_CANCTRL_LBUF (0x10)\r
+#define MCF_FlexCAN_CANCTRL_TSYNC (0x20)\r
+#define MCF_FlexCAN_CANCTRL_BOFFREC (0x40)\r
+#define MCF_FlexCAN_CANCTRL_SAMP (0x80)\r
+#define MCF_FlexCAN_CANCTRL_LPB (0x1000)\r
+#define MCF_FlexCAN_CANCTRL_CLK_SRC (0x2000)\r
+#define MCF_FlexCAN_CANCTRL_ERRMSK (0x4000)\r
+#define MCF_FlexCAN_CANCTRL_BOFFMSK (0x8000)\r
+#define MCF_FlexCAN_CANCTRL_PSEG2(x) (((x)&0x7)<<0x10)\r
+#define MCF_FlexCAN_CANCTRL_PSEG1(x) (((x)&0x7)<<0x13)\r
+#define MCF_FlexCAN_CANCTRL_RJW(x) (((x)&0x3)<<0x16)\r
+#define MCF_FlexCAN_CANCTRL_PRESDIV(x) (((x)&0xFF)<<0x18)\r
+\r
+/* Bit definitions and macros for MCF_FlexCAN_TIMER */\r
+#define MCF_FlexCAN_TIMER_TIMER(x) (((x)&0xFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FlexCAN_RXGMASK */\r
+#define MCF_FlexCAN_RXGMASK_MI(x) (((x)&0x1FFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FlexCAN_RX14MASK */\r
+#define MCF_FlexCAN_RX14MASK_MI(x) (((x)&0x1FFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FlexCAN_RX15MASK */\r
+#define MCF_FlexCAN_RX15MASK_MI(x) (((x)&0x1FFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FlexCAN_ERRCNT */\r
+#define MCF_FlexCAN_ERRCNT_TXECTR(x) (((x)&0xFF)<<0)\r
+#define MCF_FlexCAN_ERRCNT_RXECTR(x) (((x)&0xFF)<<0x8)\r
+\r
+/* Bit definitions and macros for MCF_FlexCAN_ERRSTAT */\r
+#define MCF_FlexCAN_ERRSTAT_ERRINT (0x2)\r
+#define MCF_FlexCAN_ERRSTAT_BOFFINT (0x4)\r
+#define MCF_FlexCAN_ERRSTAT_FLTCONF(x) (((x)&0x3)<<0x4)\r
+#define MCF_FlexCAN_ERRSTAT_FLTCONF_ACTIVE (0)\r
+#define MCF_FlexCAN_ERRSTAT_FLTCONF_PASSIVE (0x10)\r
+#define MCF_FlexCAN_ERRSTAT_FLTCONF_BUSOFF (0x20)\r
+#define MCF_FlexCAN_ERRSTAT_TXRX (0x40)\r
+#define MCF_FlexCAN_ERRSTAT_IDLE (0x80)\r
+#define MCF_FlexCAN_ERRSTAT_RXWRN (0x100)\r
+#define MCF_FlexCAN_ERRSTAT_TXWRN (0x200)\r
+#define MCF_FlexCAN_ERRSTAT_STFERR (0x400)\r
+#define MCF_FlexCAN_ERRSTAT_FRMERR (0x800)\r
+#define MCF_FlexCAN_ERRSTAT_CRCERR (0x1000)\r
+#define MCF_FlexCAN_ERRSTAT_ACKERR (0x2000)\r
+#define MCF_FlexCAN_ERRSTAT_BIT0ERR (0x4000)\r
+#define MCF_FlexCAN_ERRSTAT_BIT1ERR (0x8000)\r
+\r
+/* Bit definitions and macros for MCF_FlexCAN_IMASK */\r
+#define MCF_FlexCAN_IMASK_BUF0M (0x1)\r
+#define MCF_FlexCAN_IMASK_BUF1M (0x2)\r
+#define MCF_FlexCAN_IMASK_BUF2M (0x4)\r
+#define MCF_FlexCAN_IMASK_BUF3M (0x8)\r
+#define MCF_FlexCAN_IMASK_BUF4M (0x10)\r
+#define MCF_FlexCAN_IMASK_BUF5M (0x20)\r
+#define MCF_FlexCAN_IMASK_BUF6M (0x40)\r
+#define MCF_FlexCAN_IMASK_BUF7M (0x80)\r
+#define MCF_FlexCAN_IMASK_BUF8M (0x100)\r
+#define MCF_FlexCAN_IMASK_BUF9M (0x200)\r
+#define MCF_FlexCAN_IMASK_BUF10M (0x400)\r
+#define MCF_FlexCAN_IMASK_BUF11M (0x800)\r
+#define MCF_FlexCAN_IMASK_BUF12M (0x1000)\r
+#define MCF_FlexCAN_IMASK_BUF13M (0x2000)\r
+#define MCF_FlexCAN_IMASK_BUF14M (0x4000)\r
+#define MCF_FlexCAN_IMASK_BUF15M (0x8000)\r
+#define MCF_FlexCAN_IMASK_BUF(x) (0x1<<(x))\r
+\r
+/* Bit definitions and macros for MCF_FlexCAN_IFLAG */\r
+#define MCF_FlexCAN_IFLAG_BUF0I (0x1)\r
+#define MCF_FlexCAN_IFLAG_BUF1I (0x2)\r
+#define MCF_FlexCAN_IFLAG_BUF2I (0x4)\r
+#define MCF_FlexCAN_IFLAG_BUF3I (0x8)\r
+#define MCF_FlexCAN_IFLAG_BUF4I (0x10)\r
+#define MCF_FlexCAN_IFLAG_BUF5I (0x20)\r
+#define MCF_FlexCAN_IFLAG_BUF6I (0x40)\r
+#define MCF_FlexCAN_IFLAG_BUF7I (0x80)\r
+#define MCF_FlexCAN_IFLAG_BUF8I (0x100)\r
+#define MCF_FlexCAN_IFLAG_BUF9I (0x200)\r
+#define MCF_FlexCAN_IFLAG_BUF10I (0x400)\r
+#define MCF_FlexCAN_IFLAG_BUF11I (0x800)\r
+#define MCF_FlexCAN_IFLAG_BUF12I (0x1000)\r
+#define MCF_FlexCAN_IFLAG_BUF13I (0x2000)\r
+#define MCF_FlexCAN_IFLAG_BUF14I (0x4000)\r
+#define MCF_FlexCAN_IFLAG_BUF15I (0x8000)\r
+#define MCF_FlexCAN_IFLAG_BUF(x) (0x1<<(x))\r
+\r
+\r
+#endif /* __MCF52259_FlexCAN_H__ */\r
--- /dev/null
+/* Coldfire C Header File\r
+ * Copyright Freescale Semiconductor Inc\r
+ * All rights reserved.\r
+ *\r
+ * 2008/04/17 Revision: 0.2\r
+ *\r
+ * (c) Copyright UNIS, spol. s r.o. 1997-2008\r
+ * UNIS, spol. s r.o.\r
+ * Jundrovska 33\r
+ * 624 00 Brno\r
+ * Czech Republic\r
+ * http : www.processorexpert.com\r
+ * mail : info@processorexpert.com\r
+ */\r
+\r
+#ifndef __MCF52259_GPIO_H__\r
+#define __MCF52259_GPIO_H__\r
+\r
+\r
+/*********************************************************************\r
+*\r
+* General Purpose I/O (GPIO)\r
+*\r
+*********************************************************************/\r
+\r
+/* Register read/write macros */\r
+#define MCF_GPIO_PORTTE (*(vuint8 *)(0x40100000))\r
+#define MCF_GPIO_DDRTE (*(vuint8 *)(0x40100018))\r
+#define MCF_GPIO_SETTE (*(vuint8 *)(0x40100030))\r
+#define MCF_GPIO_CLRTE (*(vuint8 *)(0x40100048))\r
+#define MCF_GPIO_PTEPAR (*(vuint8 *)(0x40100060))\r
+\r
+#define MCF_GPIO_PORTTF (*(vuint8 *)(0x40100001))\r
+#define MCF_GPIO_DDRTF (*(vuint8 *)(0x40100019))\r
+#define MCF_GPIO_SETTF (*(vuint8 *)(0x40100031))\r
+#define MCF_GPIO_CLRTF (*(vuint8 *)(0x40100049))\r
+#define MCF_GPIO_PTFPAR (*(vuint8 *)(0x40100061))\r
+\r
+#define MCF_GPIO_PORTTG (*(vuint8 *)(0x40100002))\r
+#define MCF_GPIO_DDRTG (*(vuint8 *)(0x4010001A))\r
+#define MCF_GPIO_SETTG (*(vuint8 *)(0x40100032))\r
+#define MCF_GPIO_CLRTG (*(vuint8 *)(0x4010004A))\r
+#define MCF_GPIO_PTGPAR (*(vuint8 *)(0x40100062))\r
+\r
+#define MCF_GPIO_PORTTH (*(vuint8 *)(0x40100003))\r
+#define MCF_GPIO_DDRTH (*(vuint8 *)(0x4010001B))\r
+#define MCF_GPIO_SETTH (*(vuint8 *)(0x40100033))\r
+#define MCF_GPIO_CLRTH (*(vuint8 *)(0x4010004B))\r
+#define MCF_GPIO_PTHPAR (*(vuint16*)(0x40100090))\r
+\r
+#define MCF_GPIO_PORTTI (*(vuint8 *)(0x40100004))\r
+#define MCF_GPIO_DDRTI (*(vuint8 *)(0x4010001C))\r
+#define MCF_GPIO_SETTI (*(vuint8 *)(0x40100034))\r
+#define MCF_GPIO_CLRTI (*(vuint8 *)(0x4010004C))\r
+#define MCF_GPIO_PTIPAR (*(vuint8 *)(0x40100064))\r
+\r
+#define MCF_GPIO_PORTTJ (*(vuint8 *)(0x40100006))\r
+#define MCF_GPIO_DDRTJ (*(vuint8 *)(0x4010001E))\r
+#define MCF_GPIO_SETTJ (*(vuint8 *)(0x40100036))\r
+#define MCF_GPIO_CLRTJ (*(vuint8 *)(0x4010004E))\r
+#define MCF_GPIO_PTJPAR (*(vuint8 *)(0x40100066))\r
+\r
+#define MCF_GPIO_PORTNQ (*(vuint8 *)(0x40100008))\r
+#define MCF_GPIO_DDRNQ (*(vuint8 *)(0x40100020))\r
+#define MCF_GPIO_SETNQ (*(vuint8 *)(0x40100038))\r
+#define MCF_GPIO_CLRNQ (*(vuint8 *)(0x40100050))\r
+#define MCF_GPIO_PNQPAR (*(vuint16*)(0x40100068))\r
+\r
+#define MCF_GPIO_PORTAN (*(vuint8 *)(0x4010000A))\r
+#define MCF_GPIO_DDRAN (*(vuint8 *)(0x40100022))\r
+#define MCF_GPIO_SETAN (*(vuint8 *)(0x4010003A))\r
+#define MCF_GPIO_CLRAN (*(vuint8 *)(0x40100052))\r
+#define MCF_GPIO_PANPAR (*(vuint8 *)(0x4010006A))\r
+\r
+#define MCF_GPIO_PORTAS (*(vuint8 *)(0x4010000B))\r
+#define MCF_GPIO_DDRAS (*(vuint8 *)(0x40100023))\r
+#define MCF_GPIO_SETAS (*(vuint8 *)(0x4010003B))\r
+#define MCF_GPIO_CLRAS (*(vuint8 *)(0x40100053))\r
+#define MCF_GPIO_PASPAR (*(vuint8 *)(0x4010006B))\r
+\r
+#define MCF_GPIO_PORTQS (*(vuint8 *)(0x4010000C))\r
+#define MCF_GPIO_DDRQS (*(vuint8 *)(0x40100024))\r
+#define MCF_GPIO_SETQS (*(vuint8 *)(0x4010003C))\r
+#define MCF_GPIO_CLRQS (*(vuint8 *)(0x40100054))\r
+#define MCF_GPIO_PQSPAR (*(vuint16*)(0x4010006C))\r
+\r
+#define MCF_GPIO_PORTTA (*(vuint8 *)(0x4010000E))\r
+#define MCF_GPIO_DDRTA (*(vuint8 *)(0x40100026))\r
+#define MCF_GPIO_SETTA (*(vuint8 *)(0x4010003E))\r
+#define MCF_GPIO_CLRTA (*(vuint8 *)(0x40100056))\r
+#define MCF_GPIO_PTAPAR (*(vuint8 *)(0x4010006E))\r
+\r
+#define MCF_GPIO_PORTTC (*(vuint8 *)(0x4010000F))\r
+#define MCF_GPIO_DDRTC (*(vuint8 *)(0x40100027))\r
+#define MCF_GPIO_SETTC (*(vuint8 *)(0x4010003F))\r
+#define MCF_GPIO_CLRTC (*(vuint8 *)(0x40100057))\r
+#define MCF_GPIO_PTCPAR (*(vuint8 *)(0x4010006F))\r
+\r
+#define MCF_GPIO_PORTUA (*(vuint8 *)(0x40100011))\r
+#define MCF_GPIO_DDRUA (*(vuint8 *)(0x40100029))\r
+#define MCF_GPIO_SETUA (*(vuint8 *)(0x40100041))\r
+#define MCF_GPIO_CLRUA (*(vuint8 *)(0x40100059))\r
+#define MCF_GPIO_PUAPAR (*(vuint8 *)(0x40100071))\r
+\r
+#define MCF_GPIO_PORTUB (*(vuint8 *)(0x40100012))\r
+#define MCF_GPIO_DDRUB (*(vuint8 *)(0x4010002A))\r
+#define MCF_GPIO_SETUB (*(vuint8 *)(0x40100042))\r
+#define MCF_GPIO_CLRUB (*(vuint8 *)(0x4010005A))\r
+#define MCF_GPIO_PUBPAR (*(vuint8 *)(0x40100072))\r
+\r
+#define MCF_GPIO_PORTUC (*(vuint8 *)(0x40100013))\r
+#define MCF_GPIO_DDRUC (*(vuint8 *)(0x4010002B))\r
+#define MCF_GPIO_SETUC (*(vuint8 *)(0x40100043))\r
+#define MCF_GPIO_CLRUC (*(vuint8 *)(0x4010005B))\r
+#define MCF_GPIO_PUCPAR (*(vuint8 *)(0x40100073))\r
+\r
+#define MCF_GPIO_PORTDD (*(vuint8 *)(0x40100014))\r
+#define MCF_GPIO_DDRDD (*(vuint8 *)(0x4010002C))\r
+#define MCF_GPIO_SETDD (*(vuint8 *)(0x40100044))\r
+#define MCF_GPIO_CLRDD (*(vuint8 *)(0x4010005C))\r
+#define MCF_GPIO_PDDPAR (*(vuint8 *)(0x40100074))\r
+\r
+\r
+\r
+/* Bit definitions and macros for MCF_GPIO_PORTTE */\r
+#define MCF_GPIO_PORTTE_PORTTE0 (0x1)\r
+#define MCF_GPIO_PORTTE_PORTTE1 (0x2)\r
+#define MCF_GPIO_PORTTE_PORTTE2 (0x4)\r
+#define MCF_GPIO_PORTTE_PORTTE3 (0x8)\r
+#define MCF_GPIO_PORTTE_PORTTE4 (0x10)\r
+#define MCF_GPIO_PORTTE_PORTTE5 (0x20)\r
+#define MCF_GPIO_PORTTE_PORTTE6 (0x40)\r
+#define MCF_GPIO_PORTTE_PORTTE7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_DDRTE */\r
+#define MCF_GPIO_DDRTE_DDRTE0 (0x1)\r
+#define MCF_GPIO_DDRTE_DDRTE1 (0x2)\r
+#define MCF_GPIO_DDRTE_DDRTE2 (0x4)\r
+#define MCF_GPIO_DDRTE_DDRTE3 (0x8)\r
+#define MCF_GPIO_DDRTE_DDRTE4 (0x10)\r
+#define MCF_GPIO_DDRTE_DDRTE5 (0x20)\r
+#define MCF_GPIO_DDRTE_DDRTE6 (0x40)\r
+#define MCF_GPIO_DDRTE_DDRTE7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_SETTE */\r
+#define MCF_GPIO_SETTE_SETTE0 (0x1)\r
+#define MCF_GPIO_SETTE_SETTE1 (0x2)\r
+#define MCF_GPIO_SETTE_SETTE2 (0x4)\r
+#define MCF_GPIO_SETTE_SETTE3 (0x8)\r
+#define MCF_GPIO_SETTE_SETTE4 (0x10)\r
+#define MCF_GPIO_SETTE_SETTE5 (0x20)\r
+#define MCF_GPIO_SETTE_SETTE6 (0x40)\r
+#define MCF_GPIO_SETTE_SETTE7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_CLRTE */\r
+#define MCF_GPIO_CLRTE_CLRTE0 (0x1)\r
+#define MCF_GPIO_CLRTE_CLRTE1 (0x2)\r
+#define MCF_GPIO_CLRTE_CLRTE2 (0x4)\r
+#define MCF_GPIO_CLRTE_CLRTE3 (0x8)\r
+#define MCF_GPIO_CLRTE_CLRTE4 (0x10)\r
+#define MCF_GPIO_CLRTE_CLRTE5 (0x20)\r
+#define MCF_GPIO_CLRTE_CLRTE6 (0x40)\r
+#define MCF_GPIO_CLRTE_CLRTE7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_PTEPAR */\r
+#define MCF_GPIO_PTEPAR_PTEPAR0 (0x1)\r
+#define MCF_GPIO_PTEPAR_MB_A0_GPIO (0)\r
+#define MCF_GPIO_PTEPAR_MB_A0_MB_A0 (0x1)\r
+#define MCF_GPIO_PTEPAR_PTEPAR1 (0x2)\r
+#define MCF_GPIO_PTEPAR_MB_A1_GPIO (0)\r
+#define MCF_GPIO_PTEPAR_MB_A1_MB_A1 (0x2)\r
+#define MCF_GPIO_PTEPAR_PTEPAR2 (0x4)\r
+#define MCF_GPIO_PTEPAR_MB_A2_GPIO (0)\r
+#define MCF_GPIO_PTEPAR_MB_A2_MB_A2 (0x4)\r
+#define MCF_GPIO_PTEPAR_PTEPAR3 (0x8)\r
+#define MCF_GPIO_PTEPAR_MB_A3_GPIO (0)\r
+#define MCF_GPIO_PTEPAR_MB_A3_MB_A3 (0x8)\r
+#define MCF_GPIO_PTEPAR_PTEPAR4 (0x10)\r
+#define MCF_GPIO_PTEPAR_MB_A4_GPIO (0)\r
+#define MCF_GPIO_PTEPAR_MB_A4_MB_A4 (0x10)\r
+#define MCF_GPIO_PTEPAR_PTEPAR5 (0x20)\r
+#define MCF_GPIO_PTEPAR_MB_A5_GPIO (0)\r
+#define MCF_GPIO_PTEPAR_MB_A5_MB_A5 (0x20)\r
+#define MCF_GPIO_PTEPAR_PTEPAR6 (0x40)\r
+#define MCF_GPIO_PTEPAR_MB_A6_GPIO (0)\r
+#define MCF_GPIO_PTEPAR_MB_A6_MB_A6 (0x40)\r
+#define MCF_GPIO_PTEPAR_PTEPAR7 (0x80)\r
+#define MCF_GPIO_PTEPAR_MB_A7_GPIO (0)\r
+#define MCF_GPIO_PTEPAR_MB_A7_MB_A7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_PORTTF */\r
+#define MCF_GPIO_PORTTF_PORTTF0 (0x1)\r
+#define MCF_GPIO_PORTTF_PORTTF1 (0x2)\r
+#define MCF_GPIO_PORTTF_PORTTF2 (0x4)\r
+#define MCF_GPIO_PORTTF_PORTTF3 (0x8)\r
+#define MCF_GPIO_PORTTF_PORTTF4 (0x10)\r
+#define MCF_GPIO_PORTTF_PORTTF5 (0x20)\r
+#define MCF_GPIO_PORTTF_PORTTF6 (0x40)\r
+#define MCF_GPIO_PORTTF_PORTTF7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_DDRTF */\r
+#define MCF_GPIO_DDRTF_DDRTF0 (0x1)\r
+#define MCF_GPIO_DDRTF_DDRTF1 (0x2)\r
+#define MCF_GPIO_DDRTF_DDRTF2 (0x4)\r
+#define MCF_GPIO_DDRTF_DDRTF3 (0x8)\r
+#define MCF_GPIO_DDRTF_DDRTF4 (0x10)\r
+#define MCF_GPIO_DDRTF_DDRTF5 (0x20)\r
+#define MCF_GPIO_DDRTF_DDRTF6 (0x40)\r
+#define MCF_GPIO_DDRTF_DDRTF7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_SETTF */\r
+#define MCF_GPIO_SETTF_SETTF0 (0x1)\r
+#define MCF_GPIO_SETTF_SETTF1 (0x2)\r
+#define MCF_GPIO_SETTF_SETTF2 (0x4)\r
+#define MCF_GPIO_SETTF_SETTF3 (0x8)\r
+#define MCF_GPIO_SETTF_SETTF4 (0x10)\r
+#define MCF_GPIO_SETTF_SETTF5 (0x20)\r
+#define MCF_GPIO_SETTF_SETTF6 (0x40)\r
+#define MCF_GPIO_SETTF_SETTF7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_CLRTF */\r
+#define MCF_GPIO_CLRTF_CLRTF0 (0x1)\r
+#define MCF_GPIO_CLRTF_CLRTF1 (0x2)\r
+#define MCF_GPIO_CLRTF_CLRTF2 (0x4)\r
+#define MCF_GPIO_CLRTF_CLRTF3 (0x8)\r
+#define MCF_GPIO_CLRTF_CLRTF4 (0x10)\r
+#define MCF_GPIO_CLRTF_CLRTF5 (0x20)\r
+#define MCF_GPIO_CLRTF_CLRTF6 (0x40)\r
+#define MCF_GPIO_CLRTF_CLRTF7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_PTFPAR */\r
+#define MCF_GPIO_PTFPAR_PTFPAR0 (0x1)\r
+#define MCF_GPIO_PTFPAR_MB_A8_GPIO (0)\r
+#define MCF_GPIO_PTFPAR_MB_A8_MB_A8 (0x1)\r
+#define MCF_GPIO_PTFPAR_PTFPAR1 (0x2)\r
+#define MCF_GPIO_PTFPAR_MB_A9_GPIO (0)\r
+#define MCF_GPIO_PTFPAR_MB_A9_MB_A9 (0x2)\r
+#define MCF_GPIO_PTFPAR_PTFPAR2 (0x4)\r
+#define MCF_GPIO_PTFPAR_MB_A10_GPIO (0)\r
+#define MCF_GPIO_PTFPAR_MB_A10_MB_A10 (0x4)\r
+#define MCF_GPIO_PTFPAR_PTFPAR3 (0x8)\r
+#define MCF_GPIO_PTFPAR_MB_A11_GPIO (0)\r
+#define MCF_GPIO_PTFPAR_MB_A11_MB_A11 (0x8)\r
+#define MCF_GPIO_PTFPAR_PTFPAR4 (0x10)\r
+#define MCF_GPIO_PTFPAR_MB_A12_GPIO (0)\r
+#define MCF_GPIO_PTFPAR_MB_A12_MB_A12 (0x10)\r
+#define MCF_GPIO_PTFPAR_PTFPAR5 (0x20)\r
+#define MCF_GPIO_PTFPAR_MB_A13_GPIO (0)\r
+#define MCF_GPIO_PTFPAR_MB_A13_MB_A13 (0x20)\r
+#define MCF_GPIO_PTFPAR_PTFPAR6 (0x40)\r
+#define MCF_GPIO_PTFPAR_MB_A14_GPIO (0)\r
+#define MCF_GPIO_PTFPAR_MB_A14_MB_A14 (0x40)\r
+#define MCF_GPIO_PTFPAR_PTFPAR7 (0x80)\r
+#define MCF_GPIO_PTFPAR_MB_A15_GPIO (0)\r
+#define MCF_GPIO_PTFPAR_MB_A15_MB_A15 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_PORTTG */\r
+#define MCF_GPIO_PORTTG_PORTTG0 (0x1)\r
+#define MCF_GPIO_PORTTG_PORTTG1 (0x2)\r
+#define MCF_GPIO_PORTTG_PORTTG2 (0x4)\r
+#define MCF_GPIO_PORTTG_PORTTG3 (0x8)\r
+#define MCF_GPIO_PORTTG_PORTTG4 (0x10)\r
+#define MCF_GPIO_PORTTG_PORTTG5 (0x20)\r
+#define MCF_GPIO_PORTTG_PORTTG6 (0x40)\r
+#define MCF_GPIO_PORTTG_PORTTG7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_DDRTG */\r
+#define MCF_GPIO_DDRTG_DDRTG0 (0x1)\r
+#define MCF_GPIO_DDRTG_DDRTG1 (0x2)\r
+#define MCF_GPIO_DDRTG_DDRTG2 (0x4)\r
+#define MCF_GPIO_DDRTG_DDRTG3 (0x8)\r
+#define MCF_GPIO_DDRTG_DDRTG4 (0x10)\r
+#define MCF_GPIO_DDRTG_DDRTG5 (0x20)\r
+#define MCF_GPIO_DDRTG_DDRTG6 (0x40)\r
+#define MCF_GPIO_DDRTG_DDRTG7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_SETTG */\r
+#define MCF_GPIO_SETTG_SETTG0 (0x1)\r
+#define MCF_GPIO_SETTG_SETTG1 (0x2)\r
+#define MCF_GPIO_SETTG_SETTG2 (0x4)\r
+#define MCF_GPIO_SETTG_SETTG3 (0x8)\r
+#define MCF_GPIO_SETTG_SETTG4 (0x10)\r
+#define MCF_GPIO_SETTG_SETTG5 (0x20)\r
+#define MCF_GPIO_SETTG_SETTG6 (0x40)\r
+#define MCF_GPIO_SETTG_SETTG7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_CLRTG */\r
+#define MCF_GPIO_CLRTG_CLRTG0 (0x1)\r
+#define MCF_GPIO_CLRTG_CLRTG1 (0x2)\r
+#define MCF_GPIO_CLRTG_CLRTG2 (0x4)\r
+#define MCF_GPIO_CLRTG_CLRTG3 (0x8)\r
+#define MCF_GPIO_CLRTG_CLRTG4 (0x10)\r
+#define MCF_GPIO_CLRTG_CLRTG5 (0x20)\r
+#define MCF_GPIO_CLRTG_CLRTG6 (0x40)\r
+#define MCF_GPIO_CLRTG_CLRTG7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_PTGPAR */\r
+#define MCF_GPIO_PTGPAR_PTGPAR0 (0x1)\r
+#define MCF_GPIO_PTGPAR_MB_A16_GPIO (0)\r
+#define MCF_GPIO_PTGPAR_MB_A16_MB_A16 (0x1)\r
+#define MCF_GPIO_PTGPAR_PTGPAR1 (0x2)\r
+#define MCF_GPIO_PTGPAR_MB_A17_GPIO (0)\r
+#define MCF_GPIO_PTGPAR_MB_A17_MB_A17 (0x2)\r
+#define MCF_GPIO_PTGPAR_PTGPAR2 (0x4)\r
+#define MCF_GPIO_PTGPAR_MB_A18_GPIO (0)\r
+#define MCF_GPIO_PTGPAR_MB_A18_MB_A18 (0x4)\r
+#define MCF_GPIO_PTGPAR_PTGPAR3 (0x8)\r
+#define MCF_GPIO_PTGPAR_MB_A19_GPIO (0)\r
+#define MCF_GPIO_PTGPAR_MB_A19_MB_A19 (0x8)\r
+#define MCF_GPIO_PTGPAR_PTGPAR4 (0x10)\r
+#define MCF_GPIO_PTGPAR_PTGPAR5 (0x20)\r
+#define MCF_GPIO_PTGPAR_MB_CS1_GPIO (0)\r
+#define MCF_GPIO_PTGPAR_MB_CS0_MB_CS0 (0x20)\r
+#define MCF_GPIO_PTGPAR_PTGPAR6 (0x40)\r
+#define MCF_GPIO_PTGPAR_MB_OE_GPIO (0)\r
+#define MCF_GPIO_PTGPAR_MB_OE_MB_OE (0x40)\r
+#define MCF_GPIO_PTGPAR_PTGPAR7 (0x80)\r
+#define MCF_GPIO_PTGPAR_MB_RW_GPIO (0)\r
+#define MCF_GPIO_PTGPAR_MB_RW_MB_RW (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_PORTTH */\r
+#define MCF_GPIO_PORTTH_PORTTH0 (0x1)\r
+#define MCF_GPIO_PORTTH_PORTTH1 (0x2)\r
+#define MCF_GPIO_PORTTH_PORTTH2 (0x4)\r
+#define MCF_GPIO_PORTTH_PORTTH3 (0x8)\r
+#define MCF_GPIO_PORTTH_PORTTH4 (0x10)\r
+#define MCF_GPIO_PORTTH_PORTTH5 (0x20)\r
+#define MCF_GPIO_PORTTH_PORTTH6 (0x40)\r
+#define MCF_GPIO_PORTTH_PORTTH7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_DDRTH */\r
+#define MCF_GPIO_DDRTH_DDRTH0 (0x1)\r
+#define MCF_GPIO_DDRTH_DDRTH1 (0x2)\r
+#define MCF_GPIO_DDRTH_DDRTH2 (0x4)\r
+#define MCF_GPIO_DDRTH_DDRTH3 (0x8)\r
+#define MCF_GPIO_DDRTH_DDRTH4 (0x10)\r
+#define MCF_GPIO_DDRTH_DDRTH5 (0x20)\r
+#define MCF_GPIO_DDRTH_DDRTH6 (0x40)\r
+#define MCF_GPIO_DDRTH_DDRTH7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_SETTH */\r
+#define MCF_GPIO_SETTH_SETTH0 (0x1)\r
+#define MCF_GPIO_SETTH_SETTH1 (0x2)\r
+#define MCF_GPIO_SETTH_SETTH2 (0x4)\r
+#define MCF_GPIO_SETTH_SETTH3 (0x8)\r
+#define MCF_GPIO_SETTH_SETTH4 (0x10)\r
+#define MCF_GPIO_SETTH_SETTH5 (0x20)\r
+#define MCF_GPIO_SETTH_SETTH6 (0x40)\r
+#define MCF_GPIO_SETTH_SETTH7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_CLRTH */\r
+#define MCF_GPIO_CLRTH_CLRTH0 (0x1)\r
+#define MCF_GPIO_CLRTH_CLRTH1 (0x2)\r
+#define MCF_GPIO_CLRTH_CLRTH2 (0x4)\r
+#define MCF_GPIO_CLRTH_CLRTH3 (0x8)\r
+#define MCF_GPIO_CLRTH_CLRTH4 (0x10)\r
+#define MCF_GPIO_CLRTH_CLRTH5 (0x20)\r
+#define MCF_GPIO_CLRTH_CLRTH6 (0x40)\r
+#define MCF_GPIO_CLRTH_CLRTH7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_PTHPAR */\r
+#define MCF_GPIO_PTHPAR_PTHPAR0(x) (((x)&0x3)<<0)\r
+#define MCF_GPIO_PTHPAR_MB_D0_GPIO (0)\r
+#define MCF_GPIO_PTHPAR_MB_D0_MB_D0 (0x1)\r
+#define MCF_GPIO_PTHPAR_MB_D0_SYNCB (0x2)\r
+#define MCF_GPIO_PTHPAR_PTHPAR1(x) (((x)&0x3)<<0x2)\r
+#define MCF_GPIO_PTHPAR_MB_D1_GPIO (0)\r
+#define MCF_GPIO_PTHPAR_MB_D1_MB_D1 (0x4)\r
+#define MCF_GPIO_PTHPAR_MB_D1_SYNCA (0x8)\r
+#define MCF_GPIO_PTHPAR_PTHPAR2(x) (((x)&0x3)<<0x4)\r
+#define MCF_GPIO_PTHPAR_MB_D2_GPIO (0)\r
+#define MCF_GPIO_PTHPAR_MB_D2_MB_D2 (0x10)\r
+#define MCF_GPIO_PTHPAR_MB_D2_USB_VBUSE (0x20)\r
+#define MCF_GPIO_PTHPAR_PTHPAR3(x) (((x)&0x3)<<0x6)\r
+#define MCF_GPIO_PTHPAR_MB_D3_GPIO (0)\r
+#define MCF_GPIO_PTHPAR_MB_D3_MB_D3 (0x40)\r
+#define MCF_GPIO_PTHPAR_MB_D3_USB_VBUSD (0x80)\r
+#define MCF_GPIO_PTHPAR_PTHPAR4(x) (((x)&0x3)<<0x8)\r
+#define MCF_GPIO_PTHPAR_MB_D4_GPIO (0)\r
+#define MCF_GPIO_PTHPAR_MB_D4_MB_D4 (0x100)\r
+#define MCF_GPIO_PTHPAR_MB_D4_SDA1 (0x200)\r
+#define MCF_GPIO_PTHPAR_PTHPAR5(x) (((x)&0x3)<<0xA)\r
+#define MCF_GPIO_PTHPAR_MB_D5_GPIO (0)\r
+#define MCF_GPIO_PTHPAR_MB_D5_MB_D5 (0x400)\r
+#define MCF_GPIO_PTHPAR_MB_D5_SCL1 (0x800)\r
+#define MCF_GPIO_PTHPAR_PTHPAR6(x) (((x)&0x3)<<0xC)\r
+#define MCF_GPIO_PTHPAR_MB_D6_GPIO (0)\r
+#define MCF_GPIO_PTHPAR_MB_D6_MB_D6 (0x1000)\r
+#define MCF_GPIO_PTHPAR_MB_D6_CANTX (0x2000)\r
+#define MCF_GPIO_PTHPAR_PTHPAR7(x) (((x)&0x3)<<0xE)\r
+#define MCF_GPIO_PTHPAR_MB_D7_GPIO (0)\r
+#define MCF_GPIO_PTHPAR_MB_D7_MB_D7 (0x4000)\r
+#define MCF_GPIO_PTHPAR_MB_D7_CANRX (0x8000)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_PORTTI */\r
+#define MCF_GPIO_PORTTI_PORTTI0 (0x1)\r
+#define MCF_GPIO_PORTTI_PORTTI1 (0x2)\r
+#define MCF_GPIO_PORTTI_PORTTI2 (0x4)\r
+#define MCF_GPIO_PORTTI_PORTTI3 (0x8)\r
+#define MCF_GPIO_PORTTI_PORTTI4 (0x10)\r
+#define MCF_GPIO_PORTTI_PORTTI5 (0x20)\r
+#define MCF_GPIO_PORTTI_PORTTI6 (0x40)\r
+#define MCF_GPIO_PORTTI_PORTTI7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_DDRTI */\r
+#define MCF_GPIO_DDRTI_DDRTI0 (0x1)\r
+#define MCF_GPIO_DDRTI_DDRTI1 (0x2)\r
+#define MCF_GPIO_DDRTI_DDRTI2 (0x4)\r
+#define MCF_GPIO_DDRTI_DDRTI3 (0x8)\r
+#define MCF_GPIO_DDRTI_DDRTI4 (0x10)\r
+#define MCF_GPIO_DDRTI_DDRTI5 (0x20)\r
+#define MCF_GPIO_DDRTI_DDRTI6 (0x40)\r
+#define MCF_GPIO_DDRTI_DDRTI7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_SETTI */\r
+#define MCF_GPIO_SETTI_SETTI0 (0x1)\r
+#define MCF_GPIO_SETTI_SETTI1 (0x2)\r
+#define MCF_GPIO_SETTI_SETTI2 (0x4)\r
+#define MCF_GPIO_SETTI_SETTI3 (0x8)\r
+#define MCF_GPIO_SETTI_SETTI4 (0x10)\r
+#define MCF_GPIO_SETTI_SETTI5 (0x20)\r
+#define MCF_GPIO_SETTI_SETTI6 (0x40)\r
+#define MCF_GPIO_SETTI_SETTI7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_CLRTI */\r
+#define MCF_GPIO_CLRTI_CLRTI0 (0x1)\r
+#define MCF_GPIO_CLRTI_CLRTI1 (0x2)\r
+#define MCF_GPIO_CLRTI_CLRTI2 (0x4)\r
+#define MCF_GPIO_CLRTI_CLRTI3 (0x8)\r
+#define MCF_GPIO_CLRTI_CLRTI4 (0x10)\r
+#define MCF_GPIO_CLRTI_CLRTI5 (0x20)\r
+#define MCF_GPIO_CLRTI_CLRTI6 (0x40)\r
+#define MCF_GPIO_CLRTI_CLRTI7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_PTIPAR */\r
+#define MCF_GPIO_PTIPAR_PTIPAR0 (0x1)\r
+#define MCF_GPIO_PTIPAR_FEC_COL_GPIO (0)\r
+#define MCF_GPIO_PTIPAR_FEC_COL_FEC_COL (0x1)\r
+#define MCF_GPIO_PTIPAR_PTIPAR1 (0x2)\r
+#define MCF_GPIO_PTIPAR_FEC_CRS_GPIO (0)\r
+#define MCF_GPIO_PTIPAR_FEC_CRS_FEC_CRS (0x2)\r
+#define MCF_GPIO_PTIPAR_PTIPAR2 (0x4)\r
+#define MCF_GPIO_PTIPAR_FEC_RXCLK_GPIO (0)\r
+#define MCF_GPIO_PTIPAR_FEC_RXCLK_FEC_RXCLK (0x4)\r
+#define MCF_GPIO_PTIPAR_PTIPAR3 (0x8)\r
+#define MCF_GPIO_PTIPAR_FEC_RXD0_GPIO (0)\r
+#define MCF_GPIO_PTIPAR_FEC_RXD0_FEC_RXD0 (0x8)\r
+#define MCF_GPIO_PTIPAR_PTIPAR4 (0x10)\r
+#define MCF_GPIO_PTIPAR_FEC_RXD1_GPIO (0)\r
+#define MCF_GPIO_PTIPAR_FEC_RXD1_FEC_RXD1 (0x10)\r
+#define MCF_GPIO_PTIPAR_PTIPAR5 (0x20)\r
+#define MCF_GPIO_PTIPAR_FEC_RXD2_GPIO (0)\r
+#define MCF_GPIO_PTIPAR_FEC_RXD2_FEC_RXD2 (0x20)\r
+#define MCF_GPIO_PTIPAR_PTIPAR6 (0x40)\r
+#define MCF_GPIO_PTIPAR_FEC_RXD3_GPIO (0)\r
+#define MCF_GPIO_PTIPAR_FEC_RXD3_FEC_RXD3 (0x40)\r
+#define MCF_GPIO_PTIPAR_PTIPAR7 (0x80)\r
+#define MCF_GPIO_PTIPAR_FEC_RXDV_GPIO (0)\r
+#define MCF_GPIO_PTIPAR_FEC_RXDV_FEC_RXDV (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_PORTTJ */\r
+#define MCF_GPIO_PORTTJ_PORTTJ0 (0x1)\r
+#define MCF_GPIO_PORTTJ_PORTTJ1 (0x2)\r
+#define MCF_GPIO_PORTTJ_PORTTJ2 (0x4)\r
+#define MCF_GPIO_PORTTJ_PORTTJ3 (0x8)\r
+#define MCF_GPIO_PORTTJ_PORTTJ4 (0x10)\r
+#define MCF_GPIO_PORTTJ_PORTTJ5 (0x20)\r
+#define MCF_GPIO_PORTTJ_PORTTJ6 (0x40)\r
+#define MCF_GPIO_PORTTJ_PORTTJ7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_DDRTJ */\r
+#define MCF_GPIO_DDRTJ_DDRTJ0 (0x1)\r
+#define MCF_GPIO_DDRTJ_DDRTJ1 (0x2)\r
+#define MCF_GPIO_DDRTJ_DDRTJ2 (0x4)\r
+#define MCF_GPIO_DDRTJ_DDRTJ3 (0x8)\r
+#define MCF_GPIO_DDRTJ_DDRTJ4 (0x10)\r
+#define MCF_GPIO_DDRTJ_DDRTJ5 (0x20)\r
+#define MCF_GPIO_DDRTJ_DDRTJ6 (0x40)\r
+#define MCF_GPIO_DDRTJ_DDRTJ7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_SETTJ */\r
+#define MCF_GPIO_SETTJ_SETTJ0 (0x1)\r
+#define MCF_GPIO_SETTJ_SETTJ1 (0x2)\r
+#define MCF_GPIO_SETTJ_SETTJ2 (0x4)\r
+#define MCF_GPIO_SETTJ_SETTJ3 (0x8)\r
+#define MCF_GPIO_SETTJ_SETTJ4 (0x10)\r
+#define MCF_GPIO_SETTJ_SETTJ5 (0x20)\r
+#define MCF_GPIO_SETTJ_SETTJ6 (0x40)\r
+#define MCF_GPIO_SETTJ_SETTJ7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_CLRTJ */\r
+#define MCF_GPIO_CLRTJ_CLRTJ0 (0x1)\r
+#define MCF_GPIO_CLRTJ_CLRTJ1 (0x2)\r
+#define MCF_GPIO_CLRTJ_CLRTJ2 (0x4)\r
+#define MCF_GPIO_CLRTJ_CLRTJ3 (0x8)\r
+#define MCF_GPIO_CLRTJ_CLRTJ4 (0x10)\r
+#define MCF_GPIO_CLRTJ_CLRTJ5 (0x20)\r
+#define MCF_GPIO_CLRTJ_CLRTJ6 (0x40)\r
+#define MCF_GPIO_CLRTJ_CLRTJ7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_PTJPAR */\r
+#define MCF_GPIO_PTJPAR_PTJPAR0 (0x1)\r
+#define MCF_GPIO_PTJPAR_FEC_RXER_GPIO (0)\r
+#define MCF_GPIO_PTJPAR_FEC_RXER_FEC_RXER (0x1)\r
+#define MCF_GPIO_PTJPAR_PTJPAR1 (0x2)\r
+#define MCF_GPIO_PTJPAR_FEC_TXCLK_GPIO (0)\r
+#define MCF_GPIO_PTJPAR_FEC_TXCLK_FEC_TXCLK (0x2)\r
+#define MCF_GPIO_PTJPAR_PTJPAR2 (0x4)\r
+#define MCF_GPIO_PTJPAR_FEC_TXD0_GPIO (0)\r
+#define MCF_GPIO_PTJPAR_FEC_TXD0_FEC_TXD0 (0x4)\r
+#define MCF_GPIO_PTJPAR_PTJPAR3 (0x8)\r
+#define MCF_GPIO_PTJPAR_FEC_TXD1_GPIO (0)\r
+#define MCF_GPIO_PTJPAR_FEC_TXD1_FEC_TXD1 (0x8)\r
+#define MCF_GPIO_PTJPAR_PTJPAR4 (0x10)\r
+#define MCF_GPIO_PTJPAR_FEC_TXD2_GPIO (0)\r
+#define MCF_GPIO_PTJPAR_FEC_TXD2_FEC_TXD2 (0x10)\r
+#define MCF_GPIO_PTJPAR_PTJPAR5 (0x20)\r
+#define MCF_GPIO_PTJPAR_FEC_TXD3_GPIO (0)\r
+#define MCF_GPIO_PTJPAR_FEC_TXD3_FEC_TXD3 (0x20)\r
+#define MCF_GPIO_PTJPAR_PTJPAR6 (0x40)\r
+#define MCF_GPIO_PTJPAR_FEC_TXEN_GPIO (0)\r
+#define MCF_GPIO_PTJPAR_FEC_TXEN_FEC_TXEN (0x40)\r
+#define MCF_GPIO_PTJPAR_PTJPAR7 (0x80)\r
+#define MCF_GPIO_PTJPAR_FEC_TXER_GPIO (0)\r
+#define MCF_GPIO_PTJPAR_FEC_TXER_FEC_TXER (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_PORTNQ */\r
+#define MCF_GPIO_PORTNQ_PORTNQ1 (0x2)\r
+#define MCF_GPIO_PORTNQ_PORTNQ2 (0x4)\r
+#define MCF_GPIO_PORTNQ_PORTNQ3 (0x8)\r
+#define MCF_GPIO_PORTNQ_PORTNQ4 (0x10)\r
+#define MCF_GPIO_PORTNQ_PORTNQ5 (0x20)\r
+#define MCF_GPIO_PORTNQ_PORTNQ6 (0x40)\r
+#define MCF_GPIO_PORTNQ_PORTNQ7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_DDRNQ */\r
+#define MCF_GPIO_DDRNQ_DDRNQ1 (0x2)\r
+#define MCF_GPIO_DDRNQ_DDRNQ2 (0x4)\r
+#define MCF_GPIO_DDRNQ_DDRNQ3 (0x8)\r
+#define MCF_GPIO_DDRNQ_DDRNQ4 (0x10)\r
+#define MCF_GPIO_DDRNQ_DDRNQ5 (0x20)\r
+#define MCF_GPIO_DDRNQ_DDRNQ6 (0x40)\r
+#define MCF_GPIO_DDRNQ_DDRNQ7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_SETNQ */\r
+#define MCF_GPIO_SETNQ_SETNQ1 (0x2)\r
+#define MCF_GPIO_SETNQ_SETNQ2 (0x4)\r
+#define MCF_GPIO_SETNQ_SETNQ3 (0x8)\r
+#define MCF_GPIO_SETNQ_SETNQ4 (0x10)\r
+#define MCF_GPIO_SETNQ_SETNQ5 (0x20)\r
+#define MCF_GPIO_SETNQ_SETNQ6 (0x40)\r
+#define MCF_GPIO_SETNQ_SETNQ7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_CLRNQ */\r
+#define MCF_GPIO_CLRNQ_CLRNQ1 (0x2)\r
+#define MCF_GPIO_CLRNQ_CLRNQ2 (0x4)\r
+#define MCF_GPIO_CLRNQ_CLRNQ3 (0x8)\r
+#define MCF_GPIO_CLRNQ_CLRNQ4 (0x10)\r
+#define MCF_GPIO_CLRNQ_CLRNQ5 (0x20)\r
+#define MCF_GPIO_CLRNQ_CLRNQ6 (0x40)\r
+#define MCF_GPIO_CLRNQ_CLRNQ7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_PNQPAR */\r
+#define MCF_GPIO_PNQPAR_PNQPAR1(x) (((x)&0x3)<<0x2)\r
+#define MCF_GPIO_PNQPAR_IRQ1_GPIO (0)\r
+#define MCF_GPIO_PNQPAR_IRQ1_IRQ1 (0x4)\r
+#define MCF_GPIO_PNQPAR_IRQ1_USB_ALT_CLK (0xC)\r
+#define MCF_GPIO_PNQPAR_PNQPAR2(x) (((x)&0x3)<<0x4)\r
+#define MCF_GPIO_PNQPAR_PNQPAR3(x) (((x)&0x3)<<0x6)\r
+#define MCF_GPIO_PNQPAR_IRQ3_GPIO (0)\r
+#define MCF_GPIO_PNQPAR_IRQ3_IRQ3 (0x40)\r
+#define MCF_GPIO_PNQPAR_IRQ3_FEC_MDIO (0x80)\r
+#define MCF_GPIO_PNQPAR_PNQPAR4(x) (((x)&0x3)<<0x8)\r
+#define MCF_GPIO_PNQPAR_PNQPAR5(x) (((x)&0x3)<<0xA)\r
+#define MCF_GPIO_PNQPAR_IRQ5_GPIO (0)\r
+#define MCF_GPIO_PNQPAR_IRQ5_IRQ5 (0x400)\r
+#define MCF_GPIO_PNQPAR_IRQ5_FEC_MDC (0x800)\r
+#define MCF_GPIO_PNQPAR_PNQPAR6(x) (((x)&0x3)<<0xC)\r
+#define MCF_GPIO_PNQPAR_PNQPAR7(x) (((x)&0x3)<<0xE)\r
+#define MCF_GPIO_PNQPAR_IRQ7_GPIO (0)\r
+#define MCF_GPIO_PNQPAR_IRQ7_IRQ7 (0x4000)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_PORTAN */\r
+#define MCF_GPIO_PORTAN_PORTAN0 (0x1)\r
+#define MCF_GPIO_PORTAN_PORTAN1 (0x2)\r
+#define MCF_GPIO_PORTAN_PORTAN2 (0x4)\r
+#define MCF_GPIO_PORTAN_PORTAN3 (0x8)\r
+#define MCF_GPIO_PORTAN_PORTAN4 (0x10)\r
+#define MCF_GPIO_PORTAN_PORTAN5 (0x20)\r
+#define MCF_GPIO_PORTAN_PORTAN6 (0x40)\r
+#define MCF_GPIO_PORTAN_PORTAN7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_DDRAN */\r
+#define MCF_GPIO_DDRAN_DDRAN0 (0x1)\r
+#define MCF_GPIO_DDRAN_DDRAN1 (0x2)\r
+#define MCF_GPIO_DDRAN_DDRAN2 (0x4)\r
+#define MCF_GPIO_DDRAN_DDRAN3 (0x8)\r
+#define MCF_GPIO_DDRAN_DDRAN4 (0x10)\r
+#define MCF_GPIO_DDRAN_DDRAN5 (0x20)\r
+#define MCF_GPIO_DDRAN_DDRAN6 (0x40)\r
+#define MCF_GPIO_DDRAN_DDRAN7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_SETAN */\r
+#define MCF_GPIO_SETAN_SETAN0 (0x1)\r
+#define MCF_GPIO_SETAN_SETAN1 (0x2)\r
+#define MCF_GPIO_SETAN_SETAN2 (0x4)\r
+#define MCF_GPIO_SETAN_SETAN3 (0x8)\r
+#define MCF_GPIO_SETAN_SETAN4 (0x10)\r
+#define MCF_GPIO_SETAN_SETAN5 (0x20)\r
+#define MCF_GPIO_SETAN_SETAN6 (0x40)\r
+#define MCF_GPIO_SETAN_SETAN7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_CLRAN */\r
+#define MCF_GPIO_CLRAN_CLRAN0 (0x1)\r
+#define MCF_GPIO_CLRAN_CLRAN1 (0x2)\r
+#define MCF_GPIO_CLRAN_CLRAN2 (0x4)\r
+#define MCF_GPIO_CLRAN_CLRAN3 (0x8)\r
+#define MCF_GPIO_CLRAN_CLRAN4 (0x10)\r
+#define MCF_GPIO_CLRAN_CLRAN5 (0x20)\r
+#define MCF_GPIO_CLRAN_CLRAN6 (0x40)\r
+#define MCF_GPIO_CLRAN_CLRAN7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_PANPAR */\r
+#define MCF_GPIO_PANPAR_PANPAR0 (0x1)\r
+#define MCF_GPIO_PANPAR_AN0_GPIO (0)\r
+#define MCF_GPIO_PANPAR_AN0_AN0 (0x1)\r
+#define MCF_GPIO_PANPAR_PANPAR1 (0x2)\r
+#define MCF_GPIO_PANPAR_AN1_GPIO (0)\r
+#define MCF_GPIO_PANPAR_AN1_AN1 (0x2)\r
+#define MCF_GPIO_PANPAR_PANPAR2 (0x4)\r
+#define MCF_GPIO_PANPAR_AN2_GPIO (0)\r
+#define MCF_GPIO_PANPAR_AN2_AN2 (0x4)\r
+#define MCF_GPIO_PANPAR_PANPAR3 (0x8)\r
+#define MCF_GPIO_PANPAR_AN3_GPIO (0)\r
+#define MCF_GPIO_PANPAR_AN3_AN3 (0x8)\r
+#define MCF_GPIO_PANPAR_PANPAR4 (0x10)\r
+#define MCF_GPIO_PANPAR_AN4_GPIO (0)\r
+#define MCF_GPIO_PANPAR_AN4_AN4 (0x10)\r
+#define MCF_GPIO_PANPAR_PANPAR5 (0x20)\r
+#define MCF_GPIO_PANPAR_AN5_GPIO (0)\r
+#define MCF_GPIO_PANPAR_AN5_AN5 (0x20)\r
+#define MCF_GPIO_PANPAR_PANPAR6 (0x40)\r
+#define MCF_GPIO_PANPAR_AN6_GPIO (0)\r
+#define MCF_GPIO_PANPAR_AN6_AN6 (0x40)\r
+#define MCF_GPIO_PANPAR_PANPAR7 (0x80)\r
+#define MCF_GPIO_PANPAR_AN7_GPIO (0)\r
+#define MCF_GPIO_PANPAR_AN7_AN7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_PORTAS */\r
+#define MCF_GPIO_PORTAS_PORTAS0 (0x1)\r
+#define MCF_GPIO_PORTAS_PORTAS1 (0x2)\r
+#define MCF_GPIO_PORTAS_PORTAS2 (0x4)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_DDRAS */\r
+#define MCF_GPIO_DDRAS_DDRAS0 (0x1)\r
+#define MCF_GPIO_DDRAS_DDRAS1 (0x2)\r
+#define MCF_GPIO_DDRAS_DDRAS2 (0x4)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_SETAS */\r
+#define MCF_GPIO_SETAS_SETAS0 (0x1)\r
+#define MCF_GPIO_SETAS_SETAS1 (0x2)\r
+#define MCF_GPIO_SETAS_SETAS2 (0x4)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_CLRAS */\r
+#define MCF_GPIO_CLRAS_CLRAS0 (0x1)\r
+#define MCF_GPIO_CLRAS_CLRAS1 (0x2)\r
+#define MCF_GPIO_CLRAS_CLRAS2 (0x4)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_PASPAR */\r
+#define MCF_GPIO_PASPAR_PASPAR0(x) (((x)&0x3)<<0)\r
+#define MCF_GPIO_PASPAR_SCL0_GPIO (0)\r
+#define MCF_GPIO_PASPAR_SCL0_SCL0 (0x1)\r
+#define MCF_GPIO_PASPAR_SCL0_UTXD2 (0x3)\r
+#define MCF_GPIO_PASPAR_PASPAR1(x) (((x)&0x3)<<0x2)\r
+#define MCF_GPIO_PASPAR_SDA0_GPIO (0)\r
+#define MCF_GPIO_PASPAR_SDA0_SDA0 (0x4)\r
+#define MCF_GPIO_PASPAR_SDA0_URXD2 (0xC)\r
+#define MCF_GPIO_PASPAR_PASPAR2(x) (((x)&0x3)<<0x4)\r
+#define MCF_GPIO_PASPAR_MB_ALE_GPIO (0)\r
+#define MCF_GPIO_PASPAR_MB_ALE_MB_ALE (0x10)\r
+#define MCF_GPIO_PASPAR_MB_ALE_MB_CS1 (0x20)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_PORTQS */\r
+#define MCF_GPIO_PORTQS_PORTQS0 (0x1)\r
+#define MCF_GPIO_PORTQS_PORTQS1 (0x2)\r
+#define MCF_GPIO_PORTQS_PORTQS2 (0x4)\r
+#define MCF_GPIO_PORTQS_PORTQS3 (0x8)\r
+#define MCF_GPIO_PORTQS_PORTQS4 (0x10)\r
+#define MCF_GPIO_PORTQS_PORTQS5 (0x20)\r
+#define MCF_GPIO_PORTQS_PORTQS6 (0x40)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_DDRQS */\r
+#define MCF_GPIO_DDRQS_DDRQS0 (0x1)\r
+#define MCF_GPIO_DDRQS_DDRQS1 (0x2)\r
+#define MCF_GPIO_DDRQS_DDRQS2 (0x4)\r
+#define MCF_GPIO_DDRQS_DDRQS3 (0x8)\r
+#define MCF_GPIO_DDRQS_DDRQS4 (0x10)\r
+#define MCF_GPIO_DDRQS_DDRQS5 (0x20)\r
+#define MCF_GPIO_DDRQS_DDRQS6 (0x40)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_SETQS */\r
+#define MCF_GPIO_SETQS_SETQS0 (0x1)\r
+#define MCF_GPIO_SETQS_SETQS1 (0x2)\r
+#define MCF_GPIO_SETQS_SETQS2 (0x4)\r
+#define MCF_GPIO_SETQS_SETQS3 (0x8)\r
+#define MCF_GPIO_SETQS_SETQS4 (0x10)\r
+#define MCF_GPIO_SETQS_SETQS5 (0x20)\r
+#define MCF_GPIO_SETQS_SETQS6 (0x40)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_CLRQS */\r
+#define MCF_GPIO_CLRQS_CLRQS0 (0x1)\r
+#define MCF_GPIO_CLRQS_CLRQS1 (0x2)\r
+#define MCF_GPIO_CLRQS_CLRQS2 (0x4)\r
+#define MCF_GPIO_CLRQS_CLRQS3 (0x8)\r
+#define MCF_GPIO_CLRQS_CLRQS4 (0x10)\r
+#define MCF_GPIO_CLRQS_CLRQS5 (0x20)\r
+#define MCF_GPIO_CLRQS_CLRQS6 (0x40)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_PQSPAR */\r
+#define MCF_GPIO_PQSPAR_PQSPAR0(x) (((x)&0x3)<<0)\r
+#define MCF_GPIO_PQSPAR_QSPI_DOUT_GPIO (0)\r
+#define MCF_GPIO_PQSPAR_QSPI_DOUT_DOUT (0x1)\r
+#define MCF_GPIO_PQSPAR_QSPI_DOUT_SCL1 (0x2)\r
+#define MCF_GPIO_PQSPAR_QSPI_DOUT_UTXD1 (0x3)\r
+#define MCF_GPIO_PQSPAR_PQSPAR1(x) (((x)&0x3)<<0x2)\r
+#define MCF_GPIO_PQSPAR_QSPI_DIN_GPIO (0)\r
+#define MCF_GPIO_PQSPAR_QSPI_DIN_DIN (0x4)\r
+#define MCF_GPIO_PQSPAR_QSPI_DIN_SDA1 (0x8)\r
+#define MCF_GPIO_PQSPAR_QSPI_DIN_URXD1 (0xC)\r
+#define MCF_GPIO_PQSPAR_PQSPAR2(x) (((x)&0x3)<<0x4)\r
+#define MCF_GPIO_PQSPAR_QSPI_CLK_GPIO (0)\r
+#define MCF_GPIO_PQSPAR_QSPI_CLK_CLK (0x10)\r
+#define MCF_GPIO_PQSPAR_QSPI_CLK_SCL0 (0x20)\r
+#define MCF_GPIO_PQSPAR_QSPI_CLK_URTS1 (0x30)\r
+#define MCF_GPIO_PQSPAR_PQSPAR3(x) (((x)&0x3)<<0x6)\r
+#define MCF_GPIO_PQSPAR_QSPI_CS0_GPIO (0)\r
+#define MCF_GPIO_PQSPAR_QSPI_CS0_CS0 (0x40)\r
+#define MCF_GPIO_PQSPAR_QSPI_CS0_SDA0 (0x80)\r
+#define MCF_GPIO_PQSPAR_QSPI_CS0_UCTS1 (0xC0)\r
+#define MCF_GPIO_PQSPAR_PQSPAR4(x) (((x)&0x3)<<0x8)\r
+#define MCF_GPIO_PQSPAR_PQSPAR5(x) (((x)&0x3)<<0xA)\r
+#define MCF_GPIO_PQSPAR_QSPI_CS2_GPIO (0)\r
+#define MCF_GPIO_PQSPAR_QSPI_CS2_CS2 (0x400)\r
+#define MCF_GPIO_PQSPAR_QSPI_CS2_SYNCB (0x800)\r
+#define MCF_GPIO_PQSPAR_QSPI_CS2_USB_DM_PDOWN (0xC00)\r
+#define MCF_GPIO_PQSPAR_PQSPAR6(x) (((x)&0x3)<<0xC)\r
+#define MCF_GPIO_PQSPAR_QSPI_CS3_GPIO (0)\r
+#define MCF_GPIO_PQSPAR_QSPI_CS3_CS3 (0x1000)\r
+#define MCF_GPIO_PQSPAR_QSPI_CS3_SYNCA (0x2000)\r
+#define MCF_GPIO_PQSPAR_QSPI_CS3_USB_DP_PDOWN (0x3000)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_PORTTA */\r
+#define MCF_GPIO_PORTTA_PORTTA0 (0x1)\r
+#define MCF_GPIO_PORTTA_PORTTA1 (0x2)\r
+#define MCF_GPIO_PORTTA_PORTTA2 (0x4)\r
+#define MCF_GPIO_PORTTA_PORTTA3 (0x8)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_DDRTA */\r
+#define MCF_GPIO_DDRTA_DDRTA0 (0x1)\r
+#define MCF_GPIO_DDRTA_DDRTA1 (0x2)\r
+#define MCF_GPIO_DDRTA_DDRTA2 (0x4)\r
+#define MCF_GPIO_DDRTA_DDRTA3 (0x8)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_SETTA */\r
+#define MCF_GPIO_SETTA_SETTA0 (0x1)\r
+#define MCF_GPIO_SETTA_SETTA1 (0x2)\r
+#define MCF_GPIO_SETTA_SETTA2 (0x4)\r
+#define MCF_GPIO_SETTA_SETTA3 (0x8)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_CLRTA */\r
+#define MCF_GPIO_CLRTA_CLRTA0 (0x1)\r
+#define MCF_GPIO_CLRTA_CLRTA1 (0x2)\r
+#define MCF_GPIO_CLRTA_CLRTA2 (0x4)\r
+#define MCF_GPIO_CLRTA_CLRTA3 (0x8)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_PTAPAR */\r
+#define MCF_GPIO_PTAPAR_PTAPAR0(x) (((x)&0x3)<<0)\r
+#define MCF_GPIO_PTAPAR_ICOC0_GPIO (0)\r
+#define MCF_GPIO_PTAPAR_ICOC0_ICOC0 (0x1)\r
+#define MCF_GPIO_PTAPAR_ICOC0_PWM1 (0x3)\r
+#define MCF_GPIO_PTAPAR_PTAPAR1(x) (((x)&0x3)<<0x2)\r
+#define MCF_GPIO_PTAPAR_ICOC1_GPIO (0)\r
+#define MCF_GPIO_PTAPAR_ICOC1_ICOC1 (0x4)\r
+#define MCF_GPIO_PTAPAR_ICOC1_PWM3 (0xC)\r
+#define MCF_GPIO_PTAPAR_PTAPAR2(x) (((x)&0x3)<<0x4)\r
+#define MCF_GPIO_PTAPAR_ICOC2_GPIO (0)\r
+#define MCF_GPIO_PTAPAR_ICOC2_ICOC2 (0x10)\r
+#define MCF_GPIO_PTAPAR_ICOC2_PWM5 (0x30)\r
+#define MCF_GPIO_PTAPAR_PTAPAR3(x) (((x)&0x3)<<0x6)\r
+#define MCF_GPIO_PTAPAR_ICOC3_GPIO (0)\r
+#define MCF_GPIO_PTAPAR_ICOC3_ICOC3 (0x40)\r
+#define MCF_GPIO_PTAPAR_ICOC3_PWM7 (0xC0)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_PORTTC */\r
+#define MCF_GPIO_PORTTC_PORTTC0 (0x1)\r
+#define MCF_GPIO_PORTTC_PORTTC1 (0x2)\r
+#define MCF_GPIO_PORTTC_PORTTC2 (0x4)\r
+#define MCF_GPIO_PORTTC_PORTTC3 (0x8)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_DDRTC */\r
+#define MCF_GPIO_DDRTC_DDRTC0 (0x1)\r
+#define MCF_GPIO_DDRTC_DDRTC1 (0x2)\r
+#define MCF_GPIO_DDRTC_DDRTC2 (0x4)\r
+#define MCF_GPIO_DDRTC_DDRTC3 (0x8)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_SETTC */\r
+#define MCF_GPIO_SETTC_SETTC0 (0x1)\r
+#define MCF_GPIO_SETTC_SETTC1 (0x2)\r
+#define MCF_GPIO_SETTC_SETTC2 (0x4)\r
+#define MCF_GPIO_SETTC_SETTC3 (0x8)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_CLRTC */\r
+#define MCF_GPIO_CLRTC_CLRTC0 (0x1)\r
+#define MCF_GPIO_CLRTC_CLRTC1 (0x2)\r
+#define MCF_GPIO_CLRTC_CLRTC2 (0x4)\r
+#define MCF_GPIO_CLRTC_CLRTC3 (0x8)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_PTCPAR */\r
+#define MCF_GPIO_PTCPAR_PTCPAR0(x) (((x)&0x3)<<0)\r
+#define MCF_GPIO_PTCPAR_DTIN0_GPIO (0)\r
+#define MCF_GPIO_PTCPAR_DTIN0_DTIN0 (0x1)\r
+#define MCF_GPIO_PTCPAR_DTIN0_DTOUT0 (0x2)\r
+#define MCF_GPIO_PTCPAR_DTIN0_PWM0 (0x3)\r
+#define MCF_GPIO_PTCPAR_PTCPAR1(x) (((x)&0x3)<<0x2)\r
+#define MCF_GPIO_PTCPAR_DTIN1_GPIO (0)\r
+#define MCF_GPIO_PTCPAR_DTIN1_DTIN1 (0x4)\r
+#define MCF_GPIO_PTCPAR_DTIN1_DTOUT1 (0x8)\r
+#define MCF_GPIO_PTCPAR_DTIN1_PWM2 (0xC)\r
+#define MCF_GPIO_PTCPAR_PTCPAR2(x) (((x)&0x3)<<0x4)\r
+#define MCF_GPIO_PTCPAR_DTIN2_GPIO (0)\r
+#define MCF_GPIO_PTCPAR_DTIN2_DTIN2 (0x10)\r
+#define MCF_GPIO_PTCPAR_DTIN2_DTOUT2 (0x20)\r
+#define MCF_GPIO_PTCPAR_DTIN2_PWM4 (0x30)\r
+#define MCF_GPIO_PTCPAR_PTCPAR3(x) (((x)&0x3)<<0x6)\r
+#define MCF_GPIO_PTCPAR_DTIN3_GPIO (0)\r
+#define MCF_GPIO_PTCPAR_DTIN3_DTIN3 (0x40)\r
+#define MCF_GPIO_PTCPAR_DTIN3_DTOUT3 (0x80)\r
+#define MCF_GPIO_PTCPAR_DTIN3_PWM6 (0xC0)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_PORTUA */\r
+#define MCF_GPIO_PORTUA_PORTUA0 (0x1)\r
+#define MCF_GPIO_PORTUA_PORTUA1 (0x2)\r
+#define MCF_GPIO_PORTUA_PORTUA2 (0x4)\r
+#define MCF_GPIO_PORTUA_PORTUA3 (0x8)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_DDRUA */\r
+#define MCF_GPIO_DDRUA_DDRUA0 (0x1)\r
+#define MCF_GPIO_DDRUA_DDRUA1 (0x2)\r
+#define MCF_GPIO_DDRUA_DDRUA2 (0x4)\r
+#define MCF_GPIO_DDRUA_DDRUA3 (0x8)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_SETUA */\r
+#define MCF_GPIO_SETUA_SETUA0 (0x1)\r
+#define MCF_GPIO_SETUA_SETUA1 (0x2)\r
+#define MCF_GPIO_SETUA_SETUA2 (0x4)\r
+#define MCF_GPIO_SETUA_SETUA3 (0x8)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_CLRUA */\r
+#define MCF_GPIO_CLRUA_CLRUA0 (0x1)\r
+#define MCF_GPIO_CLRUA_CLRUA1 (0x2)\r
+#define MCF_GPIO_CLRUA_CLRUA2 (0x4)\r
+#define MCF_GPIO_CLRUA_CLRUA3 (0x8)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_PUAPAR */\r
+#define MCF_GPIO_PUAPAR_PUAPAR0(x) (((x)&0x3)<<0)\r
+#define MCF_GPIO_PUAPAR_UTXD0_GPIO (0)\r
+#define MCF_GPIO_PUAPAR_UTXD0_UTXD0 (0x1)\r
+#define MCF_GPIO_PUAPAR_PUAPAR1(x) (((x)&0x3)<<0x2)\r
+#define MCF_GPIO_PUAPAR_URXD0_GPIO (0)\r
+#define MCF_GPIO_PUAPAR_URXD0_URXD0 (0x4)\r
+#define MCF_GPIO_PUAPAR_PUAPAR2(x) (((x)&0x3)<<0x4)\r
+#define MCF_GPIO_PUAPAR_URTS0_GPIO (0)\r
+#define MCF_GPIO_PUAPAR_URTS0_URTS0 (0x10)\r
+#define MCF_GPIO_PUAPAR_URTS0_USB_VBUSD (0x30)\r
+#define MCF_GPIO_PUAPAR_PUAPAR3(x) (((x)&0x3)<<0x6)\r
+#define MCF_GPIO_PUAPAR_UCTS0_GPIO (0)\r
+#define MCF_GPIO_PUAPAR_UCTS0_UCTS0 (0x40)\r
+#define MCF_GPIO_PUAPAR_UCTS0_USB_VBUSE (0xC0)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_PORTUB */\r
+#define MCF_GPIO_PORTUB_PORTUB0 (0x1)\r
+#define MCF_GPIO_PORTUB_PORTUB1 (0x2)\r
+#define MCF_GPIO_PORTUB_PORTUB2 (0x4)\r
+#define MCF_GPIO_PORTUB_PORTUB3 (0x8)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_DDRUB */\r
+#define MCF_GPIO_DDRUB_DDRUB0 (0x1)\r
+#define MCF_GPIO_DDRUB_DDRUB1 (0x2)\r
+#define MCF_GPIO_DDRUB_DDRUB2 (0x4)\r
+#define MCF_GPIO_DDRUB_DDRUB3 (0x8)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_SETUB */\r
+#define MCF_GPIO_SETUB_SETUB0 (0x1)\r
+#define MCF_GPIO_SETUB_SETUB1 (0x2)\r
+#define MCF_GPIO_SETUB_SETUB2 (0x4)\r
+#define MCF_GPIO_SETUB_SETUB3 (0x8)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_CLRUB */\r
+#define MCF_GPIO_CLRUB_CLRUB0 (0x1)\r
+#define MCF_GPIO_CLRUB_CLRUB1 (0x2)\r
+#define MCF_GPIO_CLRUB_CLRUB2 (0x4)\r
+#define MCF_GPIO_CLRUB_CLRUB3 (0x8)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_PUBPAR */\r
+#define MCF_GPIO_PUBPAR_PUBPAR0(x) (((x)&0x3)<<0)\r
+#define MCF_GPIO_PUBPAR_UTXD1_GPIO (0)\r
+#define MCF_GPIO_PUBPAR_UTXD1_UTXD1 (0x1)\r
+#define MCF_GPIO_PUBPAR_UTXD1_SCL1 (0x2)\r
+#define MCF_GPIO_PUBPAR_PUBPAR1(x) (((x)&0x3)<<0x2)\r
+#define MCF_GPIO_PUBPAR_URXD1_GPIO (0)\r
+#define MCF_GPIO_PUBPAR_URXD1_URXD1 (0x4)\r
+#define MCF_GPIO_PUBPAR_URXD1_SDA1 (0x8)\r
+#define MCF_GPIO_PUBPAR_PUBPAR2(x) (((x)&0x3)<<0x4)\r
+#define MCF_GPIO_PUBPAR_URTS1_GPIO (0)\r
+#define MCF_GPIO_PUBPAR_URTS1_URTS1 (0x10)\r
+#define MCF_GPIO_PUBPAR_URTS1_SYNCB (0x20)\r
+#define MCF_GPIO_PUBPAR_URTS1_UTXD2 (0x30)\r
+#define MCF_GPIO_PUBPAR_PUBPAR3(x) (((x)&0x3)<<0x6)\r
+#define MCF_GPIO_PUBPAR_UCTS1_GPIO (0)\r
+#define MCF_GPIO_PUBPAR_UCTS1_UCTS1 (0x40)\r
+#define MCF_GPIO_PUBPAR_UCTS1_SYNCA (0x80)\r
+#define MCF_GPIO_PUBPAR_UCTS1_URXD2 (0xC0)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_PORTUC */\r
+#define MCF_GPIO_PORTUC_PORTUC0 (0x1)\r
+#define MCF_GPIO_PORTUC_PORTUC1 (0x2)\r
+#define MCF_GPIO_PORTUC_PORTUC2 (0x4)\r
+#define MCF_GPIO_PORTUC_PORTUC3 (0x8)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_DDRUC */\r
+#define MCF_GPIO_DDRUC_DDRUC0 (0x1)\r
+#define MCF_GPIO_DDRUC_DDRUC1 (0x2)\r
+#define MCF_GPIO_DDRUC_DDRUC2 (0x4)\r
+#define MCF_GPIO_DDRUC_DDRUC3 (0x8)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_SETUC */\r
+#define MCF_GPIO_SETUC_SETUC0 (0x1)\r
+#define MCF_GPIO_SETUC_SETUC1 (0x2)\r
+#define MCF_GPIO_SETUC_SETUC2 (0x4)\r
+#define MCF_GPIO_SETUC_SETUC3 (0x8)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_CLRUC */\r
+#define MCF_GPIO_CLRUC_CLRUC0 (0x1)\r
+#define MCF_GPIO_CLRUC_CLRUC1 (0x2)\r
+#define MCF_GPIO_CLRUC_CLRUC2 (0x4)\r
+#define MCF_GPIO_CLRUC_CLRUC3 (0x8)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_PUCPAR */\r
+#define MCF_GPIO_PUCPAR_PUCPAR0(x) (((x)&0x3)<<0)\r
+#define MCF_GPIO_PUCPAR_UTXD2_GPIO (0)\r
+#define MCF_GPIO_PUCPAR_UTXD2_UTXD2 (0x1)\r
+#define MCF_GPIO_PUCPAR_UTXD2_CANTX (0x2)\r
+#define MCF_GPIO_PUCPAR_PUCPAR1(x) (((x)&0x3)<<0x2)\r
+#define MCF_GPIO_PUCPAR_URXD2_GPIO (0)\r
+#define MCF_GPIO_PUCPAR_URXD2_URXD2 (0x4)\r
+#define MCF_GPIO_PUCPAR_URXD2_CANRX (0x8)\r
+#define MCF_GPIO_PUCPAR_PUCPAR2(x) (((x)&0x3)<<0x4)\r
+#define MCF_GPIO_PUCPAR_URTS2_GPIO (0)\r
+#define MCF_GPIO_PUCPAR_URTS2_URTS2 (0x10)\r
+#define MCF_GPIO_PUCPAR_URTS2_SDA1 (0x20)\r
+#define MCF_GPIO_PUCPAR_URTS2_USB_VBUSDIS (0x30)\r
+#define MCF_GPIO_PUCPAR_PUCPAR3(x) (((x)&0x3)<<0x6)\r
+#define MCF_GPIO_PUCPAR_UCTS2_GPIO (0)\r
+#define MCF_GPIO_PUCPAR_UCTS2_UCTS2 (0x40)\r
+#define MCF_GPIO_PUCPAR_UCTS2_SCL1 (0x80)\r
+#define MCF_GPIO_PUCPAR_UCTS2_USB_VBUSCHG (0xC0)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_PORTDD */\r
+#define MCF_GPIO_PORTDD_PORTDD0 (0x1)\r
+#define MCF_GPIO_PORTDD_PORTDD1 (0x2)\r
+#define MCF_GPIO_PORTDD_PORTDD2 (0x4)\r
+#define MCF_GPIO_PORTDD_PORTDD3 (0x8)\r
+#define MCF_GPIO_PORTDD_PORTDD4 (0x10)\r
+#define MCF_GPIO_PORTDD_PORTDD5 (0x20)\r
+#define MCF_GPIO_PORTDD_PORTDD6 (0x40)\r
+#define MCF_GPIO_PORTDD_PORTDD7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_DDRDD */\r
+#define MCF_GPIO_DDRDD_DDRDD0 (0x1)\r
+#define MCF_GPIO_DDRDD_DDRDD1 (0x2)\r
+#define MCF_GPIO_DDRDD_DDRDD2 (0x4)\r
+#define MCF_GPIO_DDRDD_DDRDD3 (0x8)\r
+#define MCF_GPIO_DDRDD_DDRDD4 (0x10)\r
+#define MCF_GPIO_DDRDD_DDRDD5 (0x20)\r
+#define MCF_GPIO_DDRDD_DDRDD6 (0x40)\r
+#define MCF_GPIO_DDRDD_DDRDD7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_SETDD */\r
+#define MCF_GPIO_SETDD_SETDD0 (0x1)\r
+#define MCF_GPIO_SETDD_SETDD1 (0x2)\r
+#define MCF_GPIO_SETDD_SETDD2 (0x4)\r
+#define MCF_GPIO_SETDD_SETDD3 (0x8)\r
+#define MCF_GPIO_SETDD_SETDD4 (0x10)\r
+#define MCF_GPIO_SETDD_SETDD5 (0x20)\r
+#define MCF_GPIO_SETDD_SETDD6 (0x40)\r
+#define MCF_GPIO_SETDD_SETDD7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_CLRDD */\r
+#define MCF_GPIO_CLRDD_CLRDD0 (0x1)\r
+#define MCF_GPIO_CLRDD_CLRDD1 (0x2)\r
+#define MCF_GPIO_CLRDD_CLRDD2 (0x4)\r
+#define MCF_GPIO_CLRDD_CLRDD3 (0x8)\r
+#define MCF_GPIO_CLRDD_CLRDD4 (0x10)\r
+#define MCF_GPIO_CLRDD_CLRDD5 (0x20)\r
+#define MCF_GPIO_CLRDD_CLRDD6 (0x40)\r
+#define MCF_GPIO_CLRDD_CLRDD7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_PDDPAR */\r
+#define MCF_GPIO_PDDPAR_PDDPAR0 (0x1)\r
+#define MCF_GPIO_PDDPAR_PST0_GPIO (0)\r
+#define MCF_GPIO_PDDPAR_PST0_PST0 (0x1)\r
+#define MCF_GPIO_PDDPAR_PDDPAR1 (0x2)\r
+#define MCF_GPIO_PDDPAR_PST1_GPIO (0)\r
+#define MCF_GPIO_PDDPAR_PST1_PST1 (0x2)\r
+#define MCF_GPIO_PDDPAR_PDDPAR2 (0x4)\r
+#define MCF_GPIO_PDDPAR_PST2_GPIO (0)\r
+#define MCF_GPIO_PDDPAR_PST2_PST2 (0x4)\r
+#define MCF_GPIO_PDDPAR_PDDPAR3 (0x8)\r
+#define MCF_GPIO_PDDPAR_PST3_GPIO (0)\r
+#define MCF_GPIO_PDDPAR_PST3_PST3 (0x8)\r
+#define MCF_GPIO_PDDPAR_PDDPAR4 (0x10)\r
+#define MCF_GPIO_PDDPAR_DDATA0_GPIO (0)\r
+#define MCF_GPIO_PDDPAR_DDATA0_DDATA0 (0x10)\r
+#define MCF_GPIO_PDDPAR_PDDPAR5 (0x20)\r
+#define MCF_GPIO_PDDPAR_DDATA1_GPIO (0)\r
+#define MCF_GPIO_PDDPAR_DDATA1_DDATA1 (0x20)\r
+#define MCF_GPIO_PDDPAR_PDDPAR6 (0x40)\r
+#define MCF_GPIO_PDDPAR_DDATA2_GPIO (0)\r
+#define MCF_GPIO_PDDPAR_DDATA2_DDATA2 (0x40)\r
+#define MCF_GPIO_PDDPAR_PDDPAR7 (0x80)\r
+#define MCF_GPIO_PDDPAR_DDATA3_GPIO (0)\r
+#define MCF_GPIO_PDDPAR_DDATA3_DDATA3 (0x80)\r
+\r
+\r
+#endif /* __MCF52259_GPIO_H__ */\r
--- /dev/null
+/* Coldfire C Header File\r
+ * Copyright Freescale Semiconductor Inc\r
+ * All rights reserved.\r
+ *\r
+ * 2008/04/17 Revision: 0.2\r
+ *\r
+ * (c) Copyright UNIS, spol. s r.o. 1997-2008\r
+ * UNIS, spol. s r.o.\r
+ * Jundrovska 33\r
+ * 624 00 Brno\r
+ * Czech Republic\r
+ * http : www.processorexpert.com\r
+ * mail : info@processorexpert.com\r
+ */\r
+\r
+#ifndef __MCF52259_GPT_H__\r
+#define __MCF52259_GPT_H__\r
+\r
+\r
+/*********************************************************************\r
+*\r
+* General Purpose Timer Module (GPT)\r
+*\r
+*********************************************************************/\r
+\r
+/* Register read/write macros */\r
+#define MCF_GPT_GPTIOS (*(vuint8 *)(0x401A0000))\r
+#define MCF_GPT_GPTCFORC (*(vuint8 *)(0x401A0001))\r
+#define MCF_GPT_GPTOC3M (*(vuint8 *)(0x401A0002))\r
+#define MCF_GPT_GPTOC3D (*(vuint8 *)(0x401A0003))\r
+#define MCF_GPT_GPTCNT (*(vuint16*)(0x401A0004))\r
+#define MCF_GPT_GPTSCR1 (*(vuint8 *)(0x401A0006))\r
+#define MCF_GPT_GPTTOV (*(vuint8 *)(0x401A0008))\r
+#define MCF_GPT_GPTCTL1 (*(vuint8 *)(0x401A0009))\r
+#define MCF_GPT_GPTCTL2 (*(vuint8 *)(0x401A000B))\r
+#define MCF_GPT_GPTIE (*(vuint8 *)(0x401A000C))\r
+#define MCF_GPT_GPTSCR2 (*(vuint8 *)(0x401A000D))\r
+#define MCF_GPT_GPTFLG1 (*(vuint8 *)(0x401A000E))\r
+#define MCF_GPT_GPTFLG2 (*(vuint8 *)(0x401A000F))\r
+#define MCF_GPT_GPTC0 (*(vuint16*)(0x401A0010))\r
+#define MCF_GPT_GPTC1 (*(vuint16*)(0x401A0012))\r
+#define MCF_GPT_GPTC2 (*(vuint16*)(0x401A0014))\r
+#define MCF_GPT_GPTC3 (*(vuint16*)(0x401A0016))\r
+#define MCF_GPT_GPTPACTL (*(vuint8 *)(0x401A0018))\r
+#define MCF_GPT_GPTPAFLG (*(vuint8 *)(0x401A0019))\r
+#define MCF_GPT_GPTPACNT (*(vuint16*)(0x401A001A))\r
+#define MCF_GPT_GPTPORT (*(vuint8 *)(0x401A001D))\r
+#define MCF_GPT_GPTDDR (*(vuint8 *)(0x401A001E))\r
+#define MCF_GPT_GPTC(x) (*(vuint16*)(0x401A0010 + ((x)*0x2)))\r
+\r
+\r
+/* Bit definitions and macros for MCF_GPT_GPTIOS */\r
+#define MCF_GPT_GPTIOS_IOS0 (0x1)\r
+#define MCF_GPT_GPTIOS_IOS1 (0x2)\r
+#define MCF_GPT_GPTIOS_IOS2 (0x4)\r
+#define MCF_GPT_GPTIOS_IOS3 (0x8)\r
+\r
+/* Bit definitions and macros for MCF_GPT_GPTCFORC */\r
+#define MCF_GPT_GPTCFORC_FOC0 (0x1)\r
+#define MCF_GPT_GPTCFORC_FOC1 (0x2)\r
+#define MCF_GPT_GPTCFORC_FOC2 (0x4)\r
+#define MCF_GPT_GPTCFORC_FOC3 (0x8)\r
+\r
+/* Bit definitions and macros for MCF_GPT_GPTOC3M */\r
+#define MCF_GPT_GPTOC3M_OC3M0 (0x1)\r
+#define MCF_GPT_GPTOC3M_OC3M1 (0x2)\r
+#define MCF_GPT_GPTOC3M_OC3M2 (0x4)\r
+#define MCF_GPT_GPTOC3M_OC3M3 (0x8)\r
+\r
+/* Bit definitions and macros for MCF_GPT_GPTOC3D */\r
+#define MCF_GPT_GPTOC3D_OC3D0 (0x1)\r
+#define MCF_GPT_GPTOC3D_OC3D1 (0x2)\r
+#define MCF_GPT_GPTOC3D_OC3D2 (0x4)\r
+#define MCF_GPT_GPTOC3D_OC3D3 (0x8)\r
+\r
+/* Bit definitions and macros for MCF_GPT_GPTCNT */\r
+#define MCF_GPT_GPTCNT_CNTR(x) (((x)&0xFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_GPT_GPTSCR1 */\r
+#define MCF_GPT_GPTSCR1_TFFCA (0x10)\r
+#define MCF_GPT_GPTSCR1_GPTEN (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPT_GPTTOV */\r
+#define MCF_GPT_GPTTOV_TOV0 (0x1)\r
+#define MCF_GPT_GPTTOV_TOV1 (0x2)\r
+#define MCF_GPT_GPTTOV_TOV2 (0x4)\r
+#define MCF_GPT_GPTTOV_TOV3 (0x8)\r
+\r
+/* Bit definitions and macros for MCF_GPT_GPTCTL1 */\r
+#define MCF_GPT_GPTCTL1_OL0 (0x1)\r
+#define MCF_GPT_GPTCTL1_OM0 (0x2)\r
+#define MCF_GPT_GPTCTL1_OL1 (0x4)\r
+#define MCF_GPT_GPTCTL1_OM1 (0x8)\r
+#define MCF_GPT_GPTCTL1_OL2 (0x10)\r
+#define MCF_GPT_GPTCTL1_OM2 (0x20)\r
+#define MCF_GPT_GPTCTL1_OL3 (0x40)\r
+#define MCF_GPT_GPTCTL1_OM3 (0x80)\r
+#define MCF_GPT_GPTCTL1_OUTPUT0_NOTHING (0)\r
+#define MCF_GPT_GPTCTL1_OUTPUT0_TOGGLE (0x1)\r
+#define MCF_GPT_GPTCTL1_OUTPUT0_CLEAR (0x2)\r
+#define MCF_GPT_GPTCTL1_OUTPUT0_SET (0x3)\r
+#define MCF_GPT_GPTCTL1_OUTPUT1_NOTHING (0)\r
+#define MCF_GPT_GPTCTL1_OUTPUT1_TOGGLE (0x4)\r
+#define MCF_GPT_GPTCTL1_OUTPUT1_CLEAR (0x8)\r
+#define MCF_GPT_GPTCTL1_OUTPUT1_SET (0xC)\r
+#define MCF_GPT_GPTCTL1_OUTPUT2_NOTHING (0)\r
+#define MCF_GPT_GPTCTL1_OUTPUT2_TOGGLE (0x10)\r
+#define MCF_GPT_GPTCTL1_OUTPUT2_CLEAR (0x20)\r
+#define MCF_GPT_GPTCTL1_OUTPUT2_SET (0x30)\r
+#define MCF_GPT_GPTCTL1_OUTPUT3_NOTHING (0)\r
+#define MCF_GPT_GPTCTL1_OUTPUT3_TOGGLE (0x40)\r
+#define MCF_GPT_GPTCTL1_OUTPUT3_CLEAR (0x80)\r
+#define MCF_GPT_GPTCTL1_OUTPUT3_SET (0xC0)\r
+\r
+/* Bit definitions and macros for MCF_GPT_GPTCTL2 */\r
+#define MCF_GPT_GPTCTL2_EDG0A (0x1)\r
+#define MCF_GPT_GPTCTL2_EDG0B (0x2)\r
+#define MCF_GPT_GPTCTL2_EDG1A (0x4)\r
+#define MCF_GPT_GPTCTL2_EDG1B (0x8)\r
+#define MCF_GPT_GPTCTL2_EDG2A (0x10)\r
+#define MCF_GPT_GPTCTL2_EDG2B (0x20)\r
+#define MCF_GPT_GPTCTL2_EDG3A (0x40)\r
+#define MCF_GPT_GPTCTL2_EDG3B (0x80)\r
+#define MCF_GPT_GPTCTL2_INPUT0_DISABLED (0)\r
+#define MCF_GPT_GPTCTL2_INPUT0_RISING (0x1)\r
+#define MCF_GPT_GPTCTL2_INPUT0_FALLING (0x2)\r
+#define MCF_GPT_GPTCTL2_INPUT0_ANY (0x3)\r
+#define MCF_GPT_GPTCTL2_INPUT1_DISABLED (0)\r
+#define MCF_GPT_GPTCTL2_INPUT1_RISING (0x4)\r
+#define MCF_GPT_GPTCTL2_INPUT1_FALLING (0x8)\r
+#define MCF_GPT_GPTCTL2_INPUT1_ANY (0xC)\r
+#define MCF_GPT_GPTCTL2_INPUT2_DISABLED (0)\r
+#define MCF_GPT_GPTCTL2_INPUT2_RISING (0x10)\r
+#define MCF_GPT_GPTCTL2_INPUT2_FALLING (0x20)\r
+#define MCF_GPT_GPTCTL2_INPUT2_ANY (0x30)\r
+#define MCF_GPT_GPTCTL2_INPUT3_DISABLED (0)\r
+#define MCF_GPT_GPTCTL2_INPUT3_RISING (0x40)\r
+#define MCF_GPT_GPTCTL2_INPUT3_FALLING (0x80)\r
+#define MCF_GPT_GPTCTL2_INPUT3_ANY (0xC0)\r
+\r
+/* Bit definitions and macros for MCF_GPT_GPTIE */\r
+#define MCF_GPT_GPTIE_CI0 (0x1)\r
+#define MCF_GPT_GPTIE_CI1 (0x2)\r
+#define MCF_GPT_GPTIE_CI2 (0x4)\r
+#define MCF_GPT_GPTIE_CI3 (0x8)\r
+\r
+/* Bit definitions and macros for MCF_GPT_GPTSCR2 */\r
+#define MCF_GPT_GPTSCR2_PR(x) (((x)&0x7)<<0)\r
+#define MCF_GPT_GPTSCR2_PR_1 (0)\r
+#define MCF_GPT_GPTSCR2_PR_2 (0x1)\r
+#define MCF_GPT_GPTSCR2_PR_4 (0x2)\r
+#define MCF_GPT_GPTSCR2_PR_8 (0x3)\r
+#define MCF_GPT_GPTSCR2_PR_16 (0x4)\r
+#define MCF_GPT_GPTSCR2_PR_32 (0x5)\r
+#define MCF_GPT_GPTSCR2_PR_64 (0x6)\r
+#define MCF_GPT_GPTSCR2_PR_128 (0x7)\r
+#define MCF_GPT_GPTSCR2_TCRE (0x8)\r
+#define MCF_GPT_GPTSCR2_RDPT (0x10)\r
+#define MCF_GPT_GPTSCR2_PUPT (0x20)\r
+#define MCF_GPT_GPTSCR2_TOI (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPT_GPTFLG1 */\r
+#define MCF_GPT_GPTFLG1_CF0 (0x1)\r
+#define MCF_GPT_GPTFLG1_CF1 (0x2)\r
+#define MCF_GPT_GPTFLG1_CF2 (0x4)\r
+#define MCF_GPT_GPTFLG1_CF3 (0x8)\r
+\r
+/* Bit definitions and macros for MCF_GPT_GPTFLG2 */\r
+#define MCF_GPT_GPTFLG2_TOF (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPT_GPTC */\r
+#define MCF_GPT_GPTC_CCNT(x) (((x)&0xFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_GPT_GPTPACTL */\r
+#define MCF_GPT_GPTPACTL_PAI (0x1)\r
+#define MCF_GPT_GPTPACTL_PAOVI (0x2)\r
+#define MCF_GPT_GPTPACTL_CLK(x) (((x)&0x3)<<0x2)\r
+#define MCF_GPT_GPTPACTL_CLK_GPTPR (0)\r
+#define MCF_GPT_GPTPACTL_CLK_PACLK (0x1)\r
+#define MCF_GPT_GPTPACTL_CLK_PACLK_256 (0x2)\r
+#define MCF_GPT_GPTPACTL_CLK_PACLK_65536 (0x3)\r
+#define MCF_GPT_GPTPACTL_PEDGE (0x10)\r
+#define MCF_GPT_GPTPACTL_PAMOD (0x20)\r
+#define MCF_GPT_GPTPACTL_PAE (0x40)\r
+\r
+/* Bit definitions and macros for MCF_GPT_GPTPAFLG */\r
+#define MCF_GPT_GPTPAFLG_PAIF (0x1)\r
+#define MCF_GPT_GPTPAFLG_PAOVF (0x2)\r
+\r
+/* Bit definitions and macros for MCF_GPT_GPTPACNT */\r
+#define MCF_GPT_GPTPACNT_PACNT(x) (((x)&0xFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_GPT_GPTPORT */\r
+#define MCF_GPT_GPTPORT_PORTT0 (0x1)\r
+#define MCF_GPT_GPTPORT_PORTT1 (0x2)\r
+#define MCF_GPT_GPTPORT_PORTT2 (0x4)\r
+#define MCF_GPT_GPTPORT_PORTT3 (0x8)\r
+\r
+/* Bit definitions and macros for MCF_GPT_GPTDDR */\r
+#define MCF_GPT_GPTDDR_DDRT0 (0x1)\r
+#define MCF_GPT_GPTDDR_DDRT1 (0x2)\r
+#define MCF_GPT_GPTDDR_DDRT2 (0x4)\r
+#define MCF_GPT_GPTDDR_DDRT3 (0x8)\r
+\r
+\r
+#endif /* __MCF52259_GPT_H__ */\r
--- /dev/null
+/* Coldfire C Header File\r
+ * Copyright Freescale Semiconductor Inc\r
+ * All rights reserved.\r
+ *\r
+ * 2008/04/17 Revision: 0.2\r
+ *\r
+ * (c) Copyright UNIS, spol. s r.o. 1997-2008\r
+ * UNIS, spol. s r.o.\r
+ * Jundrovska 33\r
+ * 624 00 Brno\r
+ * Czech Republic\r
+ * http : www.processorexpert.com\r
+ * mail : info@processorexpert.com\r
+ */\r
+\r
+#ifndef __MCF52259_I2C_H__\r
+#define __MCF52259_I2C_H__\r
+\r
+\r
+/*********************************************************************\r
+*\r
+* I2C Module (I2C)\r
+*\r
+*********************************************************************/\r
+\r
+/* Register read/write macros */\r
+#define MCF_I2C0_I2ADR (*(vuint8 *)(0x40000300))\r
+#define MCF_I2C0_I2FDR (*(vuint8 *)(0x40000304))\r
+#define MCF_I2C0_I2CR (*(vuint8 *)(0x40000308))\r
+#define MCF_I2C0_I2SR (*(vuint8 *)(0x4000030C))\r
+#define MCF_I2C0_I2DR (*(vuint8 *)(0x40000310))\r
+\r
+#define MCF_I2C1_I2ADR (*(vuint8 *)(0x40000380))\r
+#define MCF_I2C1_I2FDR (*(vuint8 *)(0x40000384))\r
+#define MCF_I2C1_I2CR (*(vuint8 *)(0x40000388))\r
+#define MCF_I2C1_I2SR (*(vuint8 *)(0x4000038C))\r
+#define MCF_I2C1_I2DR (*(vuint8 *)(0x40000390))\r
+\r
+#define MCF_I2C_I2ADR(x) (*(vuint8 *)(0x40000300 + ((x)*0x80)))\r
+#define MCF_I2C_I2FDR(x) (*(vuint8 *)(0x40000304 + ((x)*0x80)))\r
+#define MCF_I2C_I2CR(x) (*(vuint8 *)(0x40000308 + ((x)*0x80)))\r
+#define MCF_I2C_I2SR(x) (*(vuint8 *)(0x4000030C + ((x)*0x80)))\r
+#define MCF_I2C_I2DR(x) (*(vuint8 *)(0x40000310 + ((x)*0x80)))\r
+\r
+\r
+/* Bit definitions and macros for MCF_I2C_I2ADR */\r
+#define MCF_I2C_I2ADR_ADR(x) (((x)&0x7F)<<0x1)\r
+\r
+/* Bit definitions and macros for MCF_I2C_I2FDR */\r
+#define MCF_I2C_I2FDR_IC(x) (((x)&0x3F)<<0)\r
+\r
+/* Bit definitions and macros for MCF_I2C_I2CR */\r
+#define MCF_I2C_I2CR_RSTA (0x4)\r
+#define MCF_I2C_I2CR_TXAK (0x8)\r
+#define MCF_I2C_I2CR_MTX (0x10)\r
+#define MCF_I2C_I2CR_MSTA (0x20)\r
+#define MCF_I2C_I2CR_IIEN (0x40)\r
+#define MCF_I2C_I2CR_IEN (0x80)\r
+\r
+/* Bit definitions and macros for MCF_I2C_I2SR */\r
+#define MCF_I2C_I2SR_RXAK (0x1)\r
+#define MCF_I2C_I2SR_IIF (0x2)\r
+#define MCF_I2C_I2SR_SRW (0x4)\r
+#define MCF_I2C_I2SR_IAL (0x10)\r
+#define MCF_I2C_I2SR_IBB (0x20)\r
+#define MCF_I2C_I2SR_IAAS (0x40)\r
+#define MCF_I2C_I2SR_ICF (0x80)\r
+\r
+/* Bit definitions and macros for MCF_I2C_I2DR */\r
+#define MCF_I2C_I2DR_DATA(x) (((x)&0xFF)<<0)\r
+\r
+\r
+#endif /* __MCF52259_I2C_H__ */\r
--- /dev/null
+/* Coldfire C Header File\r
+ * Copyright Freescale Semiconductor Inc\r
+ * All rights reserved.\r
+ *\r
+ * 2008/04/17 Revision: 0.2\r
+ *\r
+ * (c) Copyright UNIS, spol. s r.o. 1997-2008\r
+ * UNIS, spol. s r.o.\r
+ * Jundrovska 33\r
+ * 624 00 Brno\r
+ * Czech Republic\r
+ * http : www.processorexpert.com\r
+ * mail : info@processorexpert.com\r
+ */\r
+\r
+#ifndef __MCF52259_INTC_H__\r
+#define __MCF52259_INTC_H__\r
+\r
+\r
+/*********************************************************************\r
+*\r
+* Interrupt Controller (INTC)\r
+*\r
+*********************************************************************/\r
+\r
+/* Register read/write macros */\r
+#define MCF_INTC0_IPRH (*(vuint32*)(0x40000C00))\r
+#define MCF_INTC0_IPRL (*(vuint32*)(0x40000C04))\r
+#define MCF_INTC0_IMRH (*(vuint32*)(0x40000C08))\r
+#define MCF_INTC0_IMRL (*(vuint32*)(0x40000C0C))\r
+#define MCF_INTC0_INTFRCH (*(vuint32*)(0x40000C10))\r
+#define MCF_INTC0_INTFRCL (*(vuint32*)(0x40000C14))\r
+#define MCF_INTC0_IRLR (*(vuint8 *)(0x40000C18))\r
+#define MCF_INTC0_IACKLPR (*(vuint8 *)(0x40000C19))\r
+#define MCF_INTC0_ICR01 (*(vuint8 *)(0x40000C41))\r
+#define MCF_INTC0_ICR02 (*(vuint8 *)(0x40000C42))\r
+#define MCF_INTC0_ICR03 (*(vuint8 *)(0x40000C43))\r
+#define MCF_INTC0_ICR04 (*(vuint8 *)(0x40000C44))\r
+#define MCF_INTC0_ICR05 (*(vuint8 *)(0x40000C45))\r
+#define MCF_INTC0_ICR06 (*(vuint8 *)(0x40000C46))\r
+#define MCF_INTC0_ICR07 (*(vuint8 *)(0x40000C47))\r
+#define MCF_INTC0_ICR08 (*(vuint8 *)(0x40000C48))\r
+#define MCF_INTC0_ICR09 (*(vuint8 *)(0x40000C49))\r
+#define MCF_INTC0_ICR10 (*(vuint8 *)(0x40000C4A))\r
+#define MCF_INTC0_ICR11 (*(vuint8 *)(0x40000C4B))\r
+#define MCF_INTC0_ICR12 (*(vuint8 *)(0x40000C4C))\r
+#define MCF_INTC0_ICR13 (*(vuint8 *)(0x40000C4D))\r
+#define MCF_INTC0_ICR14 (*(vuint8 *)(0x40000C4E))\r
+#define MCF_INTC0_ICR15 (*(vuint8 *)(0x40000C4F))\r
+#define MCF_INTC0_ICR16 (*(vuint8 *)(0x40000C50))\r
+#define MCF_INTC0_ICR17 (*(vuint8 *)(0x40000C51))\r
+#define MCF_INTC0_ICR18 (*(vuint8 *)(0x40000C52))\r
+#define MCF_INTC0_ICR19 (*(vuint8 *)(0x40000C53))\r
+#define MCF_INTC0_ICR20 (*(vuint8 *)(0x40000C54))\r
+#define MCF_INTC0_ICR21 (*(vuint8 *)(0x40000C55))\r
+#define MCF_INTC0_ICR22 (*(vuint8 *)(0x40000C56))\r
+#define MCF_INTC0_ICR23 (*(vuint8 *)(0x40000C57))\r
+#define MCF_INTC0_ICR24 (*(vuint8 *)(0x40000C58))\r
+#define MCF_INTC0_ICR25 (*(vuint8 *)(0x40000C59))\r
+#define MCF_INTC0_ICR26 (*(vuint8 *)(0x40000C5A))\r
+#define MCF_INTC0_ICR27 (*(vuint8 *)(0x40000C5B))\r
+#define MCF_INTC0_ICR28 (*(vuint8 *)(0x40000C5C))\r
+#define MCF_INTC0_ICR29 (*(vuint8 *)(0x40000C5D))\r
+#define MCF_INTC0_ICR30 (*(vuint8 *)(0x40000C5E))\r
+#define MCF_INTC0_ICR31 (*(vuint8 *)(0x40000C5F))\r
+#define MCF_INTC0_ICR32 (*(vuint8 *)(0x40000C60))\r
+#define MCF_INTC0_ICR33 (*(vuint8 *)(0x40000C61))\r
+#define MCF_INTC0_ICR34 (*(vuint8 *)(0x40000C62))\r
+#define MCF_INTC0_ICR35 (*(vuint8 *)(0x40000C63))\r
+#define MCF_INTC0_ICR36 (*(vuint8 *)(0x40000C64))\r
+#define MCF_INTC0_ICR37 (*(vuint8 *)(0x40000C65))\r
+#define MCF_INTC0_ICR38 (*(vuint8 *)(0x40000C66))\r
+#define MCF_INTC0_ICR39 (*(vuint8 *)(0x40000C67))\r
+#define MCF_INTC0_ICR40 (*(vuint8 *)(0x40000C68))\r
+#define MCF_INTC0_ICR41 (*(vuint8 *)(0x40000C69))\r
+#define MCF_INTC0_ICR42 (*(vuint8 *)(0x40000C6A))\r
+#define MCF_INTC0_ICR43 (*(vuint8 *)(0x40000C6B))\r
+#define MCF_INTC0_ICR44 (*(vuint8 *)(0x40000C6C))\r
+#define MCF_INTC0_ICR45 (*(vuint8 *)(0x40000C6D))\r
+#define MCF_INTC0_ICR46 (*(vuint8 *)(0x40000C6E))\r
+#define MCF_INTC0_ICR47 (*(vuint8 *)(0x40000C6F))\r
+#define MCF_INTC0_ICR48 (*(vuint8 *)(0x40000C70))\r
+#define MCF_INTC0_ICR49 (*(vuint8 *)(0x40000C71))\r
+#define MCF_INTC0_ICR50 (*(vuint8 *)(0x40000C72))\r
+#define MCF_INTC0_ICR51 (*(vuint8 *)(0x40000C73))\r
+#define MCF_INTC0_ICR52 (*(vuint8 *)(0x40000C74))\r
+#define MCF_INTC0_ICR53 (*(vuint8 *)(0x40000C75))\r
+#define MCF_INTC0_ICR54 (*(vuint8 *)(0x40000C76))\r
+#define MCF_INTC0_ICR55 (*(vuint8 *)(0x40000C77))\r
+#define MCF_INTC0_ICR56 (*(vuint8 *)(0x40000C78))\r
+#define MCF_INTC0_ICR57 (*(vuint8 *)(0x40000C79))\r
+#define MCF_INTC0_ICR58 (*(vuint8 *)(0x40000C7A))\r
+#define MCF_INTC0_ICR59 (*(vuint8 *)(0x40000C7B))\r
+#define MCF_INTC0_ICR60 (*(vuint8 *)(0x40000C7C))\r
+#define MCF_INTC0_ICR61 (*(vuint8 *)(0x40000C7D))\r
+#define MCF_INTC0_ICR62 (*(vuint8 *)(0x40000C7E))\r
+#define MCF_INTC0_ICR63 (*(vuint8 *)(0x40000C7F))\r
+#define MCF_INTC0_SWIACK (*(vuint8 *)(0x40000CE0))\r
+#define MCF_INTC0_L1IACK (*(vuint8 *)(0x40000CE4))\r
+#define MCF_INTC0_L2IACK (*(vuint8 *)(0x40000CE8))\r
+#define MCF_INTC0_L3IACK (*(vuint8 *)(0x40000CEC))\r
+#define MCF_INTC0_L4IACK (*(vuint8 *)(0x40000CF0))\r
+#define MCF_INTC0_L5IACK (*(vuint8 *)(0x40000CF4))\r
+#define MCF_INTC0_L6IACK (*(vuint8 *)(0x40000CF8))\r
+#define MCF_INTC0_L7IACK (*(vuint8 *)(0x40000CFC))\r
+#define MCF_INTC0_ICR(x) (*(vuint8 *)(0x40000C41 + ((x-1)*0x1)))\r
+#define MCF_INTC0_LIACK(x) (*(vuint8 *)(0x40000CE4 + ((x-1)*0x4)))\r
+\r
+#define MCF_INTC1_IPRH (*(vuint32*)(0x40000D00))\r
+#define MCF_INTC1_IPRL (*(vuint32*)(0x40000D04))\r
+#define MCF_INTC1_IMRH (*(vuint32*)(0x40000D08))\r
+#define MCF_INTC1_IMRL (*(vuint32*)(0x40000D0C))\r
+#define MCF_INTC1_INTFRCH (*(vuint32*)(0x40000D10))\r
+#define MCF_INTC1_INTFRCL (*(vuint32*)(0x40000D14))\r
+#define MCF_INTC1_IRLR (*(vuint8 *)(0x40000D18))\r
+#define MCF_INTC1_IACKLPR (*(vuint8 *)(0x40000D19))\r
+#define MCF_INTC1_ICR01 (*(vuint8 *)(0x40000D41))\r
+#define MCF_INTC1_ICR02 (*(vuint8 *)(0x40000D42))\r
+#define MCF_INTC1_ICR03 (*(vuint8 *)(0x40000D43))\r
+#define MCF_INTC1_ICR04 (*(vuint8 *)(0x40000D44))\r
+#define MCF_INTC1_ICR05 (*(vuint8 *)(0x40000D45))\r
+#define MCF_INTC1_ICR06 (*(vuint8 *)(0x40000D46))\r
+#define MCF_INTC1_ICR07 (*(vuint8 *)(0x40000D47))\r
+#define MCF_INTC1_ICR08 (*(vuint8 *)(0x40000D48))\r
+#define MCF_INTC1_ICR09 (*(vuint8 *)(0x40000D49))\r
+#define MCF_INTC1_ICR10 (*(vuint8 *)(0x40000D4A))\r
+#define MCF_INTC1_ICR11 (*(vuint8 *)(0x40000D4B))\r
+#define MCF_INTC1_ICR12 (*(vuint8 *)(0x40000D4C))\r
+#define MCF_INTC1_ICR13 (*(vuint8 *)(0x40000D4D))\r
+#define MCF_INTC1_ICR14 (*(vuint8 *)(0x40000D4E))\r
+#define MCF_INTC1_ICR15 (*(vuint8 *)(0x40000D4F))\r
+#define MCF_INTC1_ICR16 (*(vuint8 *)(0x40000D50))\r
+#define MCF_INTC1_ICR17 (*(vuint8 *)(0x40000D51))\r
+#define MCF_INTC1_ICR18 (*(vuint8 *)(0x40000D52))\r
+#define MCF_INTC1_ICR19 (*(vuint8 *)(0x40000D53))\r
+#define MCF_INTC1_ICR20 (*(vuint8 *)(0x40000D54))\r
+#define MCF_INTC1_ICR21 (*(vuint8 *)(0x40000D55))\r
+#define MCF_INTC1_ICR22 (*(vuint8 *)(0x40000D56))\r
+#define MCF_INTC1_ICR23 (*(vuint8 *)(0x40000D57))\r
+#define MCF_INTC1_ICR24 (*(vuint8 *)(0x40000D58))\r
+#define MCF_INTC1_ICR25 (*(vuint8 *)(0x40000D59))\r
+#define MCF_INTC1_ICR26 (*(vuint8 *)(0x40000D5A))\r
+#define MCF_INTC1_ICR27 (*(vuint8 *)(0x40000D5B))\r
+#define MCF_INTC1_ICR28 (*(vuint8 *)(0x40000D5C))\r
+#define MCF_INTC1_ICR29 (*(vuint8 *)(0x40000D5D))\r
+#define MCF_INTC1_ICR30 (*(vuint8 *)(0x40000D5E))\r
+#define MCF_INTC1_ICR31 (*(vuint8 *)(0x40000D5F))\r
+#define MCF_INTC1_ICR32 (*(vuint8 *)(0x40000D60))\r
+#define MCF_INTC1_ICR33 (*(vuint8 *)(0x40000D61))\r
+#define MCF_INTC1_ICR34 (*(vuint8 *)(0x40000D62))\r
+#define MCF_INTC1_ICR35 (*(vuint8 *)(0x40000D63))\r
+#define MCF_INTC1_ICR36 (*(vuint8 *)(0x40000D64))\r
+#define MCF_INTC1_ICR37 (*(vuint8 *)(0x40000D65))\r
+#define MCF_INTC1_ICR38 (*(vuint8 *)(0x40000D66))\r
+#define MCF_INTC1_ICR39 (*(vuint8 *)(0x40000D67))\r
+#define MCF_INTC1_ICR40 (*(vuint8 *)(0x40000D68))\r
+#define MCF_INTC1_ICR41 (*(vuint8 *)(0x40000D69))\r
+#define MCF_INTC1_ICR42 (*(vuint8 *)(0x40000D6A))\r
+#define MCF_INTC1_ICR43 (*(vuint8 *)(0x40000D6B))\r
+#define MCF_INTC1_ICR44 (*(vuint8 *)(0x40000D6C))\r
+#define MCF_INTC1_ICR45 (*(vuint8 *)(0x40000D6D))\r
+#define MCF_INTC1_ICR46 (*(vuint8 *)(0x40000D6E))\r
+#define MCF_INTC1_ICR47 (*(vuint8 *)(0x40000D6F))\r
+#define MCF_INTC1_ICR48 (*(vuint8 *)(0x40000D70))\r
+#define MCF_INTC1_ICR49 (*(vuint8 *)(0x40000D71))\r
+#define MCF_INTC1_ICR50 (*(vuint8 *)(0x40000D72))\r
+#define MCF_INTC1_ICR51 (*(vuint8 *)(0x40000D73))\r
+#define MCF_INTC1_ICR52 (*(vuint8 *)(0x40000D74))\r
+#define MCF_INTC1_ICR53 (*(vuint8 *)(0x40000D75))\r
+#define MCF_INTC1_ICR54 (*(vuint8 *)(0x40000D76))\r
+#define MCF_INTC1_ICR55 (*(vuint8 *)(0x40000D77))\r
+#define MCF_INTC1_ICR56 (*(vuint8 *)(0x40000D78))\r
+#define MCF_INTC1_ICR57 (*(vuint8 *)(0x40000D79))\r
+#define MCF_INTC1_ICR58 (*(vuint8 *)(0x40000D7A))\r
+#define MCF_INTC1_ICR59 (*(vuint8 *)(0x40000D7B))\r
+#define MCF_INTC1_ICR60 (*(vuint8 *)(0x40000D7C))\r
+#define MCF_INTC1_ICR61 (*(vuint8 *)(0x40000D7D))\r
+#define MCF_INTC1_ICR62 (*(vuint8 *)(0x40000D7E))\r
+#define MCF_INTC1_ICR63 (*(vuint8 *)(0x40000D7F))\r
+#define MCF_INTC1_SWIACK (*(vuint8 *)(0x40000DE0))\r
+#define MCF_INTC1_L1IACK (*(vuint8 *)(0x40000DE4))\r
+#define MCF_INTC1_L2IACK (*(vuint8 *)(0x40000DE8))\r
+#define MCF_INTC1_L3IACK (*(vuint8 *)(0x40000DEC))\r
+#define MCF_INTC1_L4IACK (*(vuint8 *)(0x40000DF0))\r
+#define MCF_INTC1_L5IACK (*(vuint8 *)(0x40000DF4))\r
+#define MCF_INTC1_L6IACK (*(vuint8 *)(0x40000DF8))\r
+#define MCF_INTC1_L7IACK (*(vuint8 *)(0x40000DFC))\r
+#define MCF_INTC1_ICR(x) (*(vuint8 *)(0x40000D41 + ((x-1)*0x1)))\r
+#define MCF_INTC1_LIACK(x) (*(vuint8 *)(0x40000DE4 + ((x-1)*0x4)))\r
+\r
+#define MCF_INTC_IPRH(x) (*(vuint32*)(0x40000C00 + ((x)*0x100)))\r
+#define MCF_INTC_IPRL(x) (*(vuint32*)(0x40000C04 + ((x)*0x100)))\r
+#define MCF_INTC_IMRH(x) (*(vuint32*)(0x40000C08 + ((x)*0x100)))\r
+#define MCF_INTC_IMRL(x) (*(vuint32*)(0x40000C0C + ((x)*0x100)))\r
+#define MCF_INTC_INTFRCH(x) (*(vuint32*)(0x40000C10 + ((x)*0x100)))\r
+#define MCF_INTC_INTFRCL(x) (*(vuint32*)(0x40000C14 + ((x)*0x100)))\r
+#define MCF_INTC_IRLR(x) (*(vuint8 *)(0x40000C18 + ((x)*0x100)))\r
+#define MCF_INTC_IACKLPR(x) (*(vuint8 *)(0x40000C19 + ((x)*0x100)))\r
+#define MCF_INTC_ICR01(x) (*(vuint8 *)(0x40000C41 + ((x)*0x100)))\r
+#define MCF_INTC_ICR02(x) (*(vuint8 *)(0x40000C42 + ((x)*0x100)))\r
+#define MCF_INTC_ICR03(x) (*(vuint8 *)(0x40000C43 + ((x)*0x100)))\r
+#define MCF_INTC_ICR04(x) (*(vuint8 *)(0x40000C44 + ((x)*0x100)))\r
+#define MCF_INTC_ICR05(x) (*(vuint8 *)(0x40000C45 + ((x)*0x100)))\r
+#define MCF_INTC_ICR06(x) (*(vuint8 *)(0x40000C46 + ((x)*0x100)))\r
+#define MCF_INTC_ICR07(x) (*(vuint8 *)(0x40000C47 + ((x)*0x100)))\r
+#define MCF_INTC_ICR08(x) (*(vuint8 *)(0x40000C48 + ((x)*0x100)))\r
+#define MCF_INTC_ICR09(x) (*(vuint8 *)(0x40000C49 + ((x)*0x100)))\r
+#define MCF_INTC_ICR10(x) (*(vuint8 *)(0x40000C4A + ((x)*0x100)))\r
+#define MCF_INTC_ICR11(x) (*(vuint8 *)(0x40000C4B + ((x)*0x100)))\r
+#define MCF_INTC_ICR12(x) (*(vuint8 *)(0x40000C4C + ((x)*0x100)))\r
+#define MCF_INTC_ICR13(x) (*(vuint8 *)(0x40000C4D + ((x)*0x100)))\r
+#define MCF_INTC_ICR14(x) (*(vuint8 *)(0x40000C4E + ((x)*0x100)))\r
+#define MCF_INTC_ICR15(x) (*(vuint8 *)(0x40000C4F + ((x)*0x100)))\r
+#define MCF_INTC_ICR16(x) (*(vuint8 *)(0x40000C50 + ((x)*0x100)))\r
+#define MCF_INTC_ICR17(x) (*(vuint8 *)(0x40000C51 + ((x)*0x100)))\r
+#define MCF_INTC_ICR18(x) (*(vuint8 *)(0x40000C52 + ((x)*0x100)))\r
+#define MCF_INTC_ICR19(x) (*(vuint8 *)(0x40000C53 + ((x)*0x100)))\r
+#define MCF_INTC_ICR20(x) (*(vuint8 *)(0x40000C54 + ((x)*0x100)))\r
+#define MCF_INTC_ICR21(x) (*(vuint8 *)(0x40000C55 + ((x)*0x100)))\r
+#define MCF_INTC_ICR22(x) (*(vuint8 *)(0x40000C56 + ((x)*0x100)))\r
+#define MCF_INTC_ICR23(x) (*(vuint8 *)(0x40000C57 + ((x)*0x100)))\r
+#define MCF_INTC_ICR24(x) (*(vuint8 *)(0x40000C58 + ((x)*0x100)))\r
+#define MCF_INTC_ICR25(x) (*(vuint8 *)(0x40000C59 + ((x)*0x100)))\r
+#define MCF_INTC_ICR26(x) (*(vuint8 *)(0x40000C5A + ((x)*0x100)))\r
+#define MCF_INTC_ICR27(x) (*(vuint8 *)(0x40000C5B + ((x)*0x100)))\r
+#define MCF_INTC_ICR28(x) (*(vuint8 *)(0x40000C5C + ((x)*0x100)))\r
+#define MCF_INTC_ICR29(x) (*(vuint8 *)(0x40000C5D + ((x)*0x100)))\r
+#define MCF_INTC_ICR30(x) (*(vuint8 *)(0x40000C5E + ((x)*0x100)))\r
+#define MCF_INTC_ICR31(x) (*(vuint8 *)(0x40000C5F + ((x)*0x100)))\r
+#define MCF_INTC_ICR32(x) (*(vuint8 *)(0x40000C60 + ((x)*0x100)))\r
+#define MCF_INTC_ICR33(x) (*(vuint8 *)(0x40000C61 + ((x)*0x100)))\r
+#define MCF_INTC_ICR34(x) (*(vuint8 *)(0x40000C62 + ((x)*0x100)))\r
+#define MCF_INTC_ICR35(x) (*(vuint8 *)(0x40000C63 + ((x)*0x100)))\r
+#define MCF_INTC_ICR36(x) (*(vuint8 *)(0x40000C64 + ((x)*0x100)))\r
+#define MCF_INTC_ICR37(x) (*(vuint8 *)(0x40000C65 + ((x)*0x100)))\r
+#define MCF_INTC_ICR38(x) (*(vuint8 *)(0x40000C66 + ((x)*0x100)))\r
+#define MCF_INTC_ICR39(x) (*(vuint8 *)(0x40000C67 + ((x)*0x100)))\r
+#define MCF_INTC_ICR40(x) (*(vuint8 *)(0x40000C68 + ((x)*0x100)))\r
+#define MCF_INTC_ICR41(x) (*(vuint8 *)(0x40000C69 + ((x)*0x100)))\r
+#define MCF_INTC_ICR42(x) (*(vuint8 *)(0x40000C6A + ((x)*0x100)))\r
+#define MCF_INTC_ICR43(x) (*(vuint8 *)(0x40000C6B + ((x)*0x100)))\r
+#define MCF_INTC_ICR44(x) (*(vuint8 *)(0x40000C6C + ((x)*0x100)))\r
+#define MCF_INTC_ICR45(x) (*(vuint8 *)(0x40000C6D + ((x)*0x100)))\r
+#define MCF_INTC_ICR46(x) (*(vuint8 *)(0x40000C6E + ((x)*0x100)))\r
+#define MCF_INTC_ICR47(x) (*(vuint8 *)(0x40000C6F + ((x)*0x100)))\r
+#define MCF_INTC_ICR48(x) (*(vuint8 *)(0x40000C70 + ((x)*0x100)))\r
+#define MCF_INTC_ICR49(x) (*(vuint8 *)(0x40000C71 + ((x)*0x100)))\r
+#define MCF_INTC_ICR50(x) (*(vuint8 *)(0x40000C72 + ((x)*0x100)))\r
+#define MCF_INTC_ICR51(x) (*(vuint8 *)(0x40000C73 + ((x)*0x100)))\r
+#define MCF_INTC_ICR52(x) (*(vuint8 *)(0x40000C74 + ((x)*0x100)))\r
+#define MCF_INTC_ICR53(x) (*(vuint8 *)(0x40000C75 + ((x)*0x100)))\r
+#define MCF_INTC_ICR54(x) (*(vuint8 *)(0x40000C76 + ((x)*0x100)))\r
+#define MCF_INTC_ICR55(x) (*(vuint8 *)(0x40000C77 + ((x)*0x100)))\r
+#define MCF_INTC_ICR56(x) (*(vuint8 *)(0x40000C78 + ((x)*0x100)))\r
+#define MCF_INTC_ICR57(x) (*(vuint8 *)(0x40000C79 + ((x)*0x100)))\r
+#define MCF_INTC_ICR58(x) (*(vuint8 *)(0x40000C7A + ((x)*0x100)))\r
+#define MCF_INTC_ICR59(x) (*(vuint8 *)(0x40000C7B + ((x)*0x100)))\r
+#define MCF_INTC_ICR60(x) (*(vuint8 *)(0x40000C7C + ((x)*0x100)))\r
+#define MCF_INTC_ICR61(x) (*(vuint8 *)(0x40000C7D + ((x)*0x100)))\r
+#define MCF_INTC_ICR62(x) (*(vuint8 *)(0x40000C7E + ((x)*0x100)))\r
+#define MCF_INTC_ICR63(x) (*(vuint8 *)(0x40000C7F + ((x)*0x100)))\r
+#define MCF_INTC_SWIACK(x) (*(vuint8 *)(0x40000CE0 + ((x)*0x100)))\r
+#define MCF_INTC_L1IACK(x) (*(vuint8 *)(0x40000CE4 + ((x)*0x100)))\r
+#define MCF_INTC_L2IACK(x) (*(vuint8 *)(0x40000CE8 + ((x)*0x100)))\r
+#define MCF_INTC_L3IACK(x) (*(vuint8 *)(0x40000CEC + ((x)*0x100)))\r
+#define MCF_INTC_L4IACK(x) (*(vuint8 *)(0x40000CF0 + ((x)*0x100)))\r
+#define MCF_INTC_L5IACK(x) (*(vuint8 *)(0x40000CF4 + ((x)*0x100)))\r
+#define MCF_INTC_L6IACK(x) (*(vuint8 *)(0x40000CF8 + ((x)*0x100)))\r
+#define MCF_INTC_L7IACK(x) (*(vuint8 *)(0x40000CFC + ((x)*0x100)))\r
+\r
+\r
+/* Bit definitions and macros for MCF_INTC_IPRH */\r
+#define MCF_INTC_IPRH_INT32 (0x1)\r
+#define MCF_INTC_IPRH_INT33 (0x2)\r
+#define MCF_INTC_IPRH_INT34 (0x4)\r
+#define MCF_INTC_IPRH_INT35 (0x8)\r
+#define MCF_INTC_IPRH_INT36 (0x10)\r
+#define MCF_INTC_IPRH_INT37 (0x20)\r
+#define MCF_INTC_IPRH_INT38 (0x40)\r
+#define MCF_INTC_IPRH_INT39 (0x80)\r
+#define MCF_INTC_IPRH_INT40 (0x100)\r
+#define MCF_INTC_IPRH_INT41 (0x200)\r
+#define MCF_INTC_IPRH_INT42 (0x400)\r
+#define MCF_INTC_IPRH_INT43 (0x800)\r
+#define MCF_INTC_IPRH_INT44 (0x1000)\r
+#define MCF_INTC_IPRH_INT45 (0x2000)\r
+#define MCF_INTC_IPRH_INT46 (0x4000)\r
+#define MCF_INTC_IPRH_INT47 (0x8000)\r
+#define MCF_INTC_IPRH_INT48 (0x10000)\r
+#define MCF_INTC_IPRH_INT49 (0x20000)\r
+#define MCF_INTC_IPRH_INT50 (0x40000)\r
+#define MCF_INTC_IPRH_INT51 (0x80000)\r
+#define MCF_INTC_IPRH_INT52 (0x100000)\r
+#define MCF_INTC_IPRH_INT53 (0x200000)\r
+#define MCF_INTC_IPRH_INT54 (0x400000)\r
+#define MCF_INTC_IPRH_INT55 (0x800000)\r
+#define MCF_INTC_IPRH_INT56 (0x1000000)\r
+#define MCF_INTC_IPRH_INT57 (0x2000000)\r
+#define MCF_INTC_IPRH_INT58 (0x4000000)\r
+#define MCF_INTC_IPRH_INT59 (0x8000000)\r
+#define MCF_INTC_IPRH_INT60 (0x10000000)\r
+#define MCF_INTC_IPRH_INT61 (0x20000000)\r
+#define MCF_INTC_IPRH_INT62 (0x40000000)\r
+#define MCF_INTC_IPRH_INT63 (0x80000000)\r
+\r
+/* Bit definitions and macros for MCF_INTC_IPRL */\r
+#define MCF_INTC_IPRL_INT1 (0x2)\r
+#define MCF_INTC_IPRL_INT2 (0x4)\r
+#define MCF_INTC_IPRL_INT3 (0x8)\r
+#define MCF_INTC_IPRL_INT4 (0x10)\r
+#define MCF_INTC_IPRL_INT5 (0x20)\r
+#define MCF_INTC_IPRL_INT6 (0x40)\r
+#define MCF_INTC_IPRL_INT7 (0x80)\r
+#define MCF_INTC_IPRL_INT8 (0x100)\r
+#define MCF_INTC_IPRL_INT9 (0x200)\r
+#define MCF_INTC_IPRL_INT10 (0x400)\r
+#define MCF_INTC_IPRL_INT11 (0x800)\r
+#define MCF_INTC_IPRL_INT12 (0x1000)\r
+#define MCF_INTC_IPRL_INT13 (0x2000)\r
+#define MCF_INTC_IPRL_INT14 (0x4000)\r
+#define MCF_INTC_IPRL_INT15 (0x8000)\r
+#define MCF_INTC_IPRL_INT16 (0x10000)\r
+#define MCF_INTC_IPRL_INT17 (0x20000)\r
+#define MCF_INTC_IPRL_INT18 (0x40000)\r
+#define MCF_INTC_IPRL_INT19 (0x80000)\r
+#define MCF_INTC_IPRL_INT20 (0x100000)\r
+#define MCF_INTC_IPRL_INT21 (0x200000)\r
+#define MCF_INTC_IPRL_INT22 (0x400000)\r
+#define MCF_INTC_IPRL_INT23 (0x800000)\r
+#define MCF_INTC_IPRL_INT24 (0x1000000)\r
+#define MCF_INTC_IPRL_INT25 (0x2000000)\r
+#define MCF_INTC_IPRL_INT26 (0x4000000)\r
+#define MCF_INTC_IPRL_INT27 (0x8000000)\r
+#define MCF_INTC_IPRL_INT28 (0x10000000)\r
+#define MCF_INTC_IPRL_INT29 (0x20000000)\r
+#define MCF_INTC_IPRL_INT30 (0x40000000)\r
+#define MCF_INTC_IPRL_INT31 (0x80000000)\r
+\r
+/* Bit definitions and macros for MCF_INTC_IMRH */\r
+#define MCF_INTC_IMRH_INT_MASK32 (0x1)\r
+#define MCF_INTC_IMRH_INT_MASK33 (0x2)\r
+#define MCF_INTC_IMRH_INT_MASK34 (0x4)\r
+#define MCF_INTC_IMRH_INT_MASK35 (0x8)\r
+#define MCF_INTC_IMRH_INT_MASK36 (0x10)\r
+#define MCF_INTC_IMRH_INT_MASK37 (0x20)\r
+#define MCF_INTC_IMRH_INT_MASK38 (0x40)\r
+#define MCF_INTC_IMRH_INT_MASK39 (0x80)\r
+#define MCF_INTC_IMRH_INT_MASK40 (0x100)\r
+#define MCF_INTC_IMRH_INT_MASK41 (0x200)\r
+#define MCF_INTC_IMRH_INT_MASK42 (0x400)\r
+#define MCF_INTC_IMRH_INT_MASK43 (0x800)\r
+#define MCF_INTC_IMRH_INT_MASK44 (0x1000)\r
+#define MCF_INTC_IMRH_INT_MASK45 (0x2000)\r
+#define MCF_INTC_IMRH_INT_MASK46 (0x4000)\r
+#define MCF_INTC_IMRH_INT_MASK47 (0x8000)\r
+#define MCF_INTC_IMRH_INT_MASK48 (0x10000)\r
+#define MCF_INTC_IMRH_INT_MASK49 (0x20000)\r
+#define MCF_INTC_IMRH_INT_MASK50 (0x40000)\r
+#define MCF_INTC_IMRH_INT_MASK51 (0x80000)\r
+#define MCF_INTC_IMRH_INT_MASK52 (0x100000)\r
+#define MCF_INTC_IMRH_INT_MASK53 (0x200000)\r
+#define MCF_INTC_IMRH_INT_MASK54 (0x400000)\r
+#define MCF_INTC_IMRH_INT_MASK55 (0x800000)\r
+#define MCF_INTC_IMRH_INT_MASK56 (0x1000000)\r
+#define MCF_INTC_IMRH_INT_MASK57 (0x2000000)\r
+#define MCF_INTC_IMRH_INT_MASK58 (0x4000000)\r
+#define MCF_INTC_IMRH_INT_MASK59 (0x8000000)\r
+#define MCF_INTC_IMRH_INT_MASK60 (0x10000000)\r
+#define MCF_INTC_IMRH_INT_MASK61 (0x20000000)\r
+#define MCF_INTC_IMRH_INT_MASK62 (0x40000000)\r
+#define MCF_INTC_IMRH_INT_MASK63 (0x80000000)\r
+\r
+/* Bit definitions and macros for MCF_INTC_IMRL */\r
+#define MCF_INTC_IMRL_MASKALL (0x1)\r
+#define MCF_INTC_IMRL_INT_MASK1 (0x2)\r
+#define MCF_INTC_IMRL_INT_MASK2 (0x4)\r
+#define MCF_INTC_IMRL_INT_MASK3 (0x8)\r
+#define MCF_INTC_IMRL_INT_MASK4 (0x10)\r
+#define MCF_INTC_IMRL_INT_MASK5 (0x20)\r
+#define MCF_INTC_IMRL_INT_MASK6 (0x40)\r
+#define MCF_INTC_IMRL_INT_MASK7 (0x80)\r
+#define MCF_INTC_IMRL_INT_MASK8 (0x100)\r
+#define MCF_INTC_IMRL_INT_MASK9 (0x200)\r
+#define MCF_INTC_IMRL_INT_MASK10 (0x400)\r
+#define MCF_INTC_IMRL_INT_MASK11 (0x800)\r
+#define MCF_INTC_IMRL_INT_MASK12 (0x1000)\r
+#define MCF_INTC_IMRL_INT_MASK13 (0x2000)\r
+#define MCF_INTC_IMRL_INT_MASK14 (0x4000)\r
+#define MCF_INTC_IMRL_INT_MASK15 (0x8000)\r
+#define MCF_INTC_IMRL_INT_MASK16 (0x10000)\r
+#define MCF_INTC_IMRL_INT_MASK17 (0x20000)\r
+#define MCF_INTC_IMRL_INT_MASK18 (0x40000)\r
+#define MCF_INTC_IMRL_INT_MASK19 (0x80000)\r
+#define MCF_INTC_IMRL_INT_MASK20 (0x100000)\r
+#define MCF_INTC_IMRL_INT_MASK21 (0x200000)\r
+#define MCF_INTC_IMRL_INT_MASK22 (0x400000)\r
+#define MCF_INTC_IMRL_INT_MASK23 (0x800000)\r
+#define MCF_INTC_IMRL_INT_MASK24 (0x1000000)\r
+#define MCF_INTC_IMRL_INT_MASK25 (0x2000000)\r
+#define MCF_INTC_IMRL_INT_MASK26 (0x4000000)\r
+#define MCF_INTC_IMRL_INT_MASK27 (0x8000000)\r
+#define MCF_INTC_IMRL_INT_MASK28 (0x10000000)\r
+#define MCF_INTC_IMRL_INT_MASK29 (0x20000000)\r
+#define MCF_INTC_IMRL_INT_MASK30 (0x40000000)\r
+#define MCF_INTC_IMRL_INT_MASK31 (0x80000000)\r
+\r
+/* Bit definitions and macros for MCF_INTC_INTFRCH */\r
+#define MCF_INTC_INTFRCH_INTFRC32 (0x1)\r
+#define MCF_INTC_INTFRCH_INTFRC33 (0x2)\r
+#define MCF_INTC_INTFRCH_INTFRC34 (0x4)\r
+#define MCF_INTC_INTFRCH_INTFRC35 (0x8)\r
+#define MCF_INTC_INTFRCH_INTFRC36 (0x10)\r
+#define MCF_INTC_INTFRCH_INTFRC37 (0x20)\r
+#define MCF_INTC_INTFRCH_INTFRC38 (0x40)\r
+#define MCF_INTC_INTFRCH_INTFRC39 (0x80)\r
+#define MCF_INTC_INTFRCH_INTFRC40 (0x100)\r
+#define MCF_INTC_INTFRCH_INTFRC41 (0x200)\r
+#define MCF_INTC_INTFRCH_INTFRC42 (0x400)\r
+#define MCF_INTC_INTFRCH_INTFRC43 (0x800)\r
+#define MCF_INTC_INTFRCH_INTFRC44 (0x1000)\r
+#define MCF_INTC_INTFRCH_INTFRC45 (0x2000)\r
+#define MCF_INTC_INTFRCH_INTFRC46 (0x4000)\r
+#define MCF_INTC_INTFRCH_INTFRC47 (0x8000)\r
+#define MCF_INTC_INTFRCH_INTFRC48 (0x10000)\r
+#define MCF_INTC_INTFRCH_INTFRC49 (0x20000)\r
+#define MCF_INTC_INTFRCH_INTFRC50 (0x40000)\r
+#define MCF_INTC_INTFRCH_INTFRC51 (0x80000)\r
+#define MCF_INTC_INTFRCH_INTFRC52 (0x100000)\r
+#define MCF_INTC_INTFRCH_INTFRC53 (0x200000)\r
+#define MCF_INTC_INTFRCH_INTFRC54 (0x400000)\r
+#define MCF_INTC_INTFRCH_INTFRC55 (0x800000)\r
+#define MCF_INTC_INTFRCH_INTFRC56 (0x1000000)\r
+#define MCF_INTC_INTFRCH_INTFRC57 (0x2000000)\r
+#define MCF_INTC_INTFRCH_INTFRC58 (0x4000000)\r
+#define MCF_INTC_INTFRCH_INTFRC59 (0x8000000)\r
+#define MCF_INTC_INTFRCH_INTFRC60 (0x10000000)\r
+#define MCF_INTC_INTFRCH_INTFRC61 (0x20000000)\r
+#define MCF_INTC_INTFRCH_INTFRC62 (0x40000000)\r
+#define MCF_INTC_INTFRCH_INTFRC63 (0x80000000)\r
+\r
+/* Bit definitions and macros for MCF_INTC_INTFRCL */\r
+#define MCF_INTC_INTFRCL_INTFRC1 (0x2)\r
+#define MCF_INTC_INTFRCL_INTFRC2 (0x4)\r
+#define MCF_INTC_INTFRCL_INTFRC3 (0x8)\r
+#define MCF_INTC_INTFRCL_INTFRC4 (0x10)\r
+#define MCF_INTC_INTFRCL_INTFRC5 (0x20)\r
+#define MCF_INTC_INTFRCL_INTFRC6 (0x40)\r
+#define MCF_INTC_INTFRCL_INTFRC7 (0x80)\r
+#define MCF_INTC_INTFRCL_INTFRC8 (0x100)\r
+#define MCF_INTC_INTFRCL_INTFRC9 (0x200)\r
+#define MCF_INTC_INTFRCL_INTFRC10 (0x400)\r
+#define MCF_INTC_INTFRCL_INTFRC11 (0x800)\r
+#define MCF_INTC_INTFRCL_INTFRC12 (0x1000)\r
+#define MCF_INTC_INTFRCL_INTFRC13 (0x2000)\r
+#define MCF_INTC_INTFRCL_INTFRC14 (0x4000)\r
+#define MCF_INTC_INTFRCL_INTFRC15 (0x8000)\r
+#define MCF_INTC_INTFRCL_INTFRC16 (0x10000)\r
+#define MCF_INTC_INTFRCL_INTFRC17 (0x20000)\r
+#define MCF_INTC_INTFRCL_INTFRC18 (0x40000)\r
+#define MCF_INTC_INTFRCL_INTFRC19 (0x80000)\r
+#define MCF_INTC_INTFRCL_INTFRC20 (0x100000)\r
+#define MCF_INTC_INTFRCL_INTFRC21 (0x200000)\r
+#define MCF_INTC_INTFRCL_INTFRC22 (0x400000)\r
+#define MCF_INTC_INTFRCL_INTFRC23 (0x800000)\r
+#define MCF_INTC_INTFRCL_INTFRC24 (0x1000000)\r
+#define MCF_INTC_INTFRCL_INTFRC25 (0x2000000)\r
+#define MCF_INTC_INTFRCL_INTFRC26 (0x4000000)\r
+#define MCF_INTC_INTFRCL_INTFRC27 (0x8000000)\r
+#define MCF_INTC_INTFRCL_INTFRC28 (0x10000000)\r
+#define MCF_INTC_INTFRCL_INTFRC29 (0x20000000)\r
+#define MCF_INTC_INTFRCL_INTFRC30 (0x40000000)\r
+#define MCF_INTC_INTFRCL_INTFRC31 (0x80000000)\r
+\r
+/* Bit definitions and macros for MCF_INTC_IRLR */\r
+#define MCF_INTC_IRLR_IRQ(x) (((x)&0x7F)<<0x1)\r
+\r
+/* Bit definitions and macros for MCF_INTC_IACKLPR */\r
+#define MCF_INTC_IACKLPR_PRI(x) (((x)&0xF)<<0)\r
+#define MCF_INTC_IACKLPR_LEVEL(x) (((x)&0x7)<<0x4)\r
+\r
+/* Bit definitions and macros for MCF_INTC_ICR */\r
+#define MCF_INTC_ICR_IP(x) (((x)&0x7)<<0)\r
+#define MCF_INTC_ICR_IL(x) (((x)&0x7)<<0x3)\r
+\r
+/* Bit definitions and macros for MCF_INTC_SWIACK */\r
+#define MCF_INTC_SWIACK_VECTOR(x) (((x)&0xFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_INTC_LIACK */\r
+#define MCF_INTC_LIACK_VECTOR(x) (((x)&0xFF)<<0)\r
+\r
+\r
+#endif /* __MCF52259_INTC_H__ */\r
--- /dev/null
+/* Coldfire C Header File\r
+ * Copyright Freescale Semiconductor Inc\r
+ * All rights reserved.\r
+ *\r
+ * 2008/04/17 Revision: 0.2\r
+ *\r
+ * (c) Copyright UNIS, spol. s r.o. 1997-2008\r
+ * UNIS, spol. s r.o.\r
+ * Jundrovska 33\r
+ * 624 00 Brno\r
+ * Czech Republic\r
+ * http : www.processorexpert.com\r
+ * mail : info@processorexpert.com\r
+ */\r
+\r
+#ifndef __MCF52259_PAD_H__\r
+#define __MCF52259_PAD_H__\r
+\r
+\r
+/*********************************************************************\r
+*\r
+* Common GPIO\r
+*\r
+*********************************************************************/\r
+\r
+/* Register read/write macros */\r
+#define MCF_PAD_PSRR0 (*(vuint32*)(0x40100078))\r
+#define MCF_PAD_PDSR0 (*(vuint32*)(0x4010007C))\r
+#define MCF_PAD_PSRR1 (*(vuint32*)(0x40100080))\r
+#define MCF_PAD_PSRR2 (*(vuint16*)(0x40100086))\r
+#define MCF_PAD_PDSR1 (*(vuint32*)(0x40100088))\r
+#define MCF_PAD_PDSR2 (*(vuint16*)(0x4010008E))\r
+\r
+\r
+/* Bit definitions and macros for MCF_PAD_PSRR0 */\r
+#define MCF_PAD_PSRR0_PSRR0 (0x1)\r
+#define MCF_PAD_PSRR0_PSRR1 (0x2)\r
+#define MCF_PAD_PSRR0_PSRR2 (0x4)\r
+#define MCF_PAD_PSRR0_PSRR3 (0x8)\r
+#define MCF_PAD_PSRR0_PSRR4 (0x10)\r
+#define MCF_PAD_PSRR0_PSRR5 (0x20)\r
+#define MCF_PAD_PSRR0_PSRR6 (0x40)\r
+#define MCF_PAD_PSRR0_PSRR7 (0x80)\r
+#define MCF_PAD_PSRR0_PSRR8 (0x100)\r
+#define MCF_PAD_PSRR0_PSRR9 (0x200)\r
+#define MCF_PAD_PSRR0_PSRR10 (0x400)\r
+#define MCF_PAD_PSRR0_PSRR11 (0x800)\r
+#define MCF_PAD_PSRR0_PSRR12 (0x1000)\r
+#define MCF_PAD_PSRR0_PSRR13 (0x2000)\r
+#define MCF_PAD_PSRR0_PSRR14 (0x4000)\r
+#define MCF_PAD_PSRR0_PSRR15 (0x8000)\r
+#define MCF_PAD_PSRR0_PSRR16 (0x10000)\r
+#define MCF_PAD_PSRR0_PSRR17 (0x20000)\r
+#define MCF_PAD_PSRR0_PSRR18 (0x40000)\r
+#define MCF_PAD_PSRR0_PSRR19 (0x80000)\r
+#define MCF_PAD_PSRR0_PSRR20 (0x100000)\r
+#define MCF_PAD_PSRR0_PSRR21 (0x200000)\r
+#define MCF_PAD_PSRR0_PSRR22 (0x400000)\r
+#define MCF_PAD_PSRR0_PSRR23 (0x800000)\r
+#define MCF_PAD_PSRR0_PSRR24 (0x1000000)\r
+#define MCF_PAD_PSRR0_PSRR25 (0x2000000)\r
+#define MCF_PAD_PSRR0_PSRR26 (0x4000000)\r
+#define MCF_PAD_PSRR0_PSRR27 (0x8000000)\r
+#define MCF_PAD_PSRR0_PSRR28 (0x10000000)\r
+#define MCF_PAD_PSRR0_PSRR29 (0x20000000)\r
+#define MCF_PAD_PSRR0_PSRR30 (0x40000000)\r
+#define MCF_PAD_PSRR0_PSRR31 (0x80000000)\r
+\r
+/* Bit definitions and macros for MCF_PAD_PDSR0 */\r
+#define MCF_PAD_PDSR0_PDSR0 (0x1)\r
+#define MCF_PAD_PDSR0_PDSR1 (0x2)\r
+#define MCF_PAD_PDSR0_PDSR2 (0x4)\r
+#define MCF_PAD_PDSR0_PDSR3 (0x8)\r
+#define MCF_PAD_PDSR0_PDSR4 (0x10)\r
+#define MCF_PAD_PDSR0_PDSR5 (0x20)\r
+#define MCF_PAD_PDSR0_PDSR6 (0x40)\r
+#define MCF_PAD_PDSR0_PDSR7 (0x80)\r
+#define MCF_PAD_PDSR0_PDSR8 (0x100)\r
+#define MCF_PAD_PDSR0_PDSR9 (0x200)\r
+#define MCF_PAD_PDSR0_PDSR10 (0x400)\r
+#define MCF_PAD_PDSR0_PDSR11 (0x800)\r
+#define MCF_PAD_PDSR0_PDSR12 (0x1000)\r
+#define MCF_PAD_PDSR0_PDSR13 (0x2000)\r
+#define MCF_PAD_PDSR0_PDSR14 (0x4000)\r
+#define MCF_PAD_PDSR0_PDSR15 (0x8000)\r
+#define MCF_PAD_PDSR0_PDSR16 (0x10000)\r
+#define MCF_PAD_PDSR0_PDSR17 (0x20000)\r
+#define MCF_PAD_PDSR0_PDSR18 (0x40000)\r
+#define MCF_PAD_PDSR0_PDSR19 (0x80000)\r
+#define MCF_PAD_PDSR0_PDSR20 (0x100000)\r
+#define MCF_PAD_PDSR0_PDSR21 (0x200000)\r
+#define MCF_PAD_PDSR0_PDSR22 (0x400000)\r
+#define MCF_PAD_PDSR0_PDSR23 (0x800000)\r
+#define MCF_PAD_PDSR0_PDSR24 (0x1000000)\r
+#define MCF_PAD_PDSR0_PDSR25 (0x2000000)\r
+#define MCF_PAD_PDSR0_PDSR26 (0x4000000)\r
+#define MCF_PAD_PDSR0_PDSR27 (0x8000000)\r
+#define MCF_PAD_PDSR0_PDSR28 (0x10000000)\r
+#define MCF_PAD_PDSR0_PDSR29 (0x20000000)\r
+#define MCF_PAD_PDSR0_PDSR30 (0x40000000)\r
+#define MCF_PAD_PDSR0_PDSR31 (0x80000000)\r
+\r
+/* Bit definitions and macros for MCF_PAD_PSRR1 */\r
+#define MCF_PAD_PSRR1_PSRR32 (0x1)\r
+#define MCF_PAD_PSRR1_PSRR33 (0x2)\r
+#define MCF_PAD_PSRR1_PSRR34 (0x4)\r
+#define MCF_PAD_PSRR1_PSRR35 (0x8)\r
+#define MCF_PAD_PSRR1_PSRR36 (0x10)\r
+#define MCF_PAD_PSRR1_PSRR37 (0x20)\r
+#define MCF_PAD_PSRR1_PSRR38 (0x40)\r
+#define MCF_PAD_PSRR1_PSRR39 (0x80)\r
+#define MCF_PAD_PSRR1_PSRR40 (0x100)\r
+#define MCF_PAD_PSRR1_PSRR41 (0x200)\r
+#define MCF_PAD_PSRR1_PSRR42 (0x400)\r
+#define MCF_PAD_PSRR1_PSRR43 (0x800)\r
+#define MCF_PAD_PSRR1_PSRR44 (0x1000)\r
+#define MCF_PAD_PSRR1_PSRR45 (0x2000)\r
+#define MCF_PAD_PSRR1_PSRR46 (0x4000)\r
+#define MCF_PAD_PSRR1_PSRR47 (0x8000)\r
+#define MCF_PAD_PSRR1_PSRR48 (0x10000)\r
+#define MCF_PAD_PSRR1_PSRR49 (0x20000)\r
+#define MCF_PAD_PSRR1_PSRR50 (0x40000)\r
+#define MCF_PAD_PSRR1_PSRR51 (0x80000)\r
+#define MCF_PAD_PSRR1_PSRR52 (0x100000)\r
+#define MCF_PAD_PSRR1_PSRR53 (0x200000)\r
+#define MCF_PAD_PSRR1_PSRR54 (0x400000)\r
+#define MCF_PAD_PSRR1_PSRR55 (0x800000)\r
+#define MCF_PAD_PSRR1_PSRR56 (0x1000000)\r
+#define MCF_PAD_PSRR1_PSRR57 (0x2000000)\r
+#define MCF_PAD_PSRR1_PSRR58 (0x4000000)\r
+#define MCF_PAD_PSRR1_PSRR59 (0x8000000)\r
+#define MCF_PAD_PSRR1_PSRR60 (0x10000000)\r
+#define MCF_PAD_PSRR1_PSRR61 (0x20000000)\r
+#define MCF_PAD_PSRR1_PSRR62 (0x40000000)\r
+#define MCF_PAD_PSRR1_PSRR63 (0x80000000)\r
+\r
+/* Bit definitions and macros for MCF_PAD_PSRR2 */\r
+#define MCF_PAD_PSRR2_PSRR64 (0x1)\r
+#define MCF_PAD_PSRR2_PSRR65 (0x2)\r
+#define MCF_PAD_PSRR2_PSRR66 (0x4)\r
+#define MCF_PAD_PSRR2_PSRR67 (0x8)\r
+#define MCF_PAD_PSRR2_PSRR68 (0x10)\r
+#define MCF_PAD_PSRR2_PSRR69 (0x20)\r
+#define MCF_PAD_PSRR2_PSRR70 (0x40)\r
+#define MCF_PAD_PSRR2_PSRR71 (0x80)\r
+#define MCF_PAD_PSRR2_PSRR72 (0x100)\r
+#define MCF_PAD_PSRR2_PSRR73 (0x200)\r
+#define MCF_PAD_PSRR2_PSRR74 (0x400)\r
+#define MCF_PAD_PSRR2_PSRR75 (0x800)\r
+#define MCF_PAD_PSRR2_PSRR76 (0x1000)\r
+#define MCF_PAD_PSRR2_PSRR77 (0x2000)\r
+#define MCF_PAD_PSRR2_PSRR78 (0x4000)\r
+#define MCF_PAD_PSRR2_PSRR79 (0x8000)\r
+\r
+/* Bit definitions and macros for MCF_PAD_PDSR1 */\r
+#define MCF_PAD_PDSR1_PDSR32 (0x1)\r
+#define MCF_PAD_PDSR1_PDSR33 (0x2)\r
+#define MCF_PAD_PDSR1_PDSR34 (0x4)\r
+#define MCF_PAD_PDSR1_PDSR35 (0x8)\r
+#define MCF_PAD_PDSR1_PDSR36 (0x10)\r
+#define MCF_PAD_PDSR1_PDSR37 (0x20)\r
+#define MCF_PAD_PDSR1_PDSR38 (0x40)\r
+#define MCF_PAD_PDSR1_PDSR39 (0x80)\r
+#define MCF_PAD_PDSR1_PDSR40 (0x100)\r
+#define MCF_PAD_PDSR1_PDSR41 (0x200)\r
+#define MCF_PAD_PDSR1_PDSR42 (0x400)\r
+#define MCF_PAD_PDSR1_PDSR43 (0x800)\r
+#define MCF_PAD_PDSR1_PDSR44 (0x1000)\r
+#define MCF_PAD_PDSR1_PDSR45 (0x2000)\r
+#define MCF_PAD_PDSR1_PDSR46 (0x4000)\r
+#define MCF_PAD_PDSR1_PDSR47 (0x8000)\r
+#define MCF_PAD_PDSR1_PDSR48 (0x10000)\r
+#define MCF_PAD_PDSR1_PDSR49 (0x20000)\r
+#define MCF_PAD_PDSR1_PDSR50 (0x40000)\r
+#define MCF_PAD_PDSR1_PDSR51 (0x80000)\r
+#define MCF_PAD_PDSR1_PDSR52 (0x100000)\r
+#define MCF_PAD_PDSR1_PDSR53 (0x200000)\r
+#define MCF_PAD_PDSR1_PDSR54 (0x400000)\r
+#define MCF_PAD_PDSR1_PDSR55 (0x800000)\r
+#define MCF_PAD_PDSR1_PDSR56 (0x1000000)\r
+#define MCF_PAD_PDSR1_PDSR57 (0x2000000)\r
+#define MCF_PAD_PDSR1_PDSR58 (0x4000000)\r
+#define MCF_PAD_PDSR1_PDSR59 (0x8000000)\r
+#define MCF_PAD_PDSR1_PDSR60 (0x10000000)\r
+#define MCF_PAD_PDSR1_PDSR61 (0x20000000)\r
+#define MCF_PAD_PDSR1_PDSR62 (0x40000000)\r
+#define MCF_PAD_PDSR1_PDSR63 (0x80000000)\r
+\r
+/* Bit definitions and macros for MCF_PAD_PDSR2 */\r
+#define MCF_PAD_PDSR2_PDSR64 (0x1)\r
+#define MCF_PAD_PDSR2_PDSR65 (0x2)\r
+#define MCF_PAD_PDSR2_PDSR66 (0x4)\r
+#define MCF_PAD_PDSR2_PDSR67 (0x8)\r
+#define MCF_PAD_PDSR2_PDSR68 (0x10)\r
+#define MCF_PAD_PDSR2_PDSR69 (0x20)\r
+#define MCF_PAD_PDSR2_PDSR70 (0x40)\r
+#define MCF_PAD_PDSR2_PDSR71 (0x80)\r
+#define MCF_PAD_PDSR2_PDSR72 (0x100)\r
+#define MCF_PAD_PDSR2_PDSR73 (0x200)\r
+#define MCF_PAD_PDSR2_PDSR74 (0x400)\r
+#define MCF_PAD_PDSR2_PDSR75 (0x800)\r
+#define MCF_PAD_PDSR2_PDSR76 (0x1000)\r
+#define MCF_PAD_PDSR2_PDSR77 (0x2000)\r
+#define MCF_PAD_PDSR2_PDSR78 (0x4000)\r
+#define MCF_PAD_PDSR2_PDSR79 (0x8000)\r
+\r
+\r
+#endif /* __MCF52259_PAD_H__ */\r
--- /dev/null
+/* Coldfire C Header File\r
+ * Copyright Freescale Semiconductor Inc\r
+ * All rights reserved.\r
+ *\r
+ * 2008/04/17 Revision: 0.2\r
+ *\r
+ * (c) Copyright UNIS, spol. s r.o. 1997-2008\r
+ * UNIS, spol. s r.o.\r
+ * Jundrovska 33\r
+ * 624 00 Brno\r
+ * Czech Republic\r
+ * http : www.processorexpert.com\r
+ * mail : info@processorexpert.com\r
+ */\r
+\r
+#ifndef __MCF52259_PIT_H__\r
+#define __MCF52259_PIT_H__\r
+\r
+\r
+/*********************************************************************\r
+*\r
+* Programmable Interrupt Timer (PIT)\r
+*\r
+*********************************************************************/\r
+\r
+/* Register read/write macros */\r
+#define MCF_PIT0_PCSR (*(vuint16*)(0x40150000))\r
+#define MCF_PIT0_PMR (*(vuint16*)(0x40150002))\r
+#define MCF_PIT0_PCNTR (*(vuint16*)(0x40150004))\r
+\r
+#define MCF_PIT1_PCSR (*(vuint16*)(0x40160000))\r
+#define MCF_PIT1_PMR (*(vuint16*)(0x40160002))\r
+#define MCF_PIT1_PCNTR (*(vuint16*)(0x40160004))\r
+\r
+#define MCF_PIT_PCSR(x) (*(vuint16*)(0x40150000 + ((x)*0x10000)))\r
+#define MCF_PIT_PMR(x) (*(vuint16*)(0x40150002 + ((x)*0x10000)))\r
+#define MCF_PIT_PCNTR(x) (*(vuint16*)(0x40150004 + ((x)*0x10000)))\r
+\r
+\r
+/* Bit definitions and macros for MCF_PIT_PCSR */\r
+#define MCF_PIT_PCSR_EN (0x1)\r
+#define MCF_PIT_PCSR_RLD (0x2)\r
+#define MCF_PIT_PCSR_PIF (0x4)\r
+#define MCF_PIT_PCSR_PIE (0x8)\r
+#define MCF_PIT_PCSR_OVW (0x10)\r
+#define MCF_PIT_PCSR_DBG (0x20)\r
+#define MCF_PIT_PCSR_DOZE (0x40)\r
+#define MCF_PIT_PCSR_PRE(x) (((x)&0xF)<<0x8)\r
+\r
+/* Bit definitions and macros for MCF_PIT_PMR */\r
+#define MCF_PIT_PMR_PM(x) (((x)&0xFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_PIT_PCNTR */\r
+#define MCF_PIT_PCNTR_PC(x) (((x)&0xFFFF)<<0)\r
+\r
+\r
+#endif /* __MCF52259_PIT_H__ */\r
--- /dev/null
+/* Coldfire C Header File\r
+ * Copyright Freescale Semiconductor Inc\r
+ * All rights reserved.\r
+ *\r
+ * 2008/04/17 Revision: 0.2\r
+ *\r
+ * (c) Copyright UNIS, spol. s r.o. 1997-2008\r
+ * UNIS, spol. s r.o.\r
+ * Jundrovska 33\r
+ * 624 00 Brno\r
+ * Czech Republic\r
+ * http : www.processorexpert.com\r
+ * mail : info@processorexpert.com\r
+ */\r
+\r
+#ifndef __MCF52259_PMM_H__\r
+#define __MCF52259_PMM_H__\r
+\r
+\r
+/*********************************************************************\r
+*\r
+* Power Management (PMM)\r
+*\r
+*********************************************************************/\r
+\r
+/* Register read/write macros */\r
+#define MCF_PMM_LPICR (*(vuint8 *)(0x40000012))\r
+#define MCF_PMM_LPCR (*(vuint8 *)(0x40110007))\r
+\r
+\r
+/* Bit definitions and macros for MCF_PMM_LPICR */\r
+#define MCF_PMM_LPICR_XLPM_IPL(x) (((x)&0x7)<<0x4)\r
+#define MCF_PMM_LPICR_ENBSTOP (0x80)\r
+\r
+/* Bit definitions and macros for MCF_PMM_LPCR */\r
+#define MCF_PMM_LPCR_LVDSE (0x2)\r
+#define MCF_PMM_LPCR_STPMD(x) (((x)&0x3)<<0x3)\r
+#define MCF_PMM_LPCR_STPMD_SYS_DISABLED (0)\r
+#define MCF_PMM_LPCR_STPMD_SYS_CLKOUT_DISABLED (0x8)\r
+#define MCF_PMM_LPCR_STPMD_ONLY_OSC_ENABLED (0x10)\r
+#define MCF_PMM_LPCR_STPMD_ALL_DISABLED (0x18)\r
+#define MCF_PMM_LPCR_LPMD(x) (((x)&0x3)<<0x6)\r
+#define MCF_PMM_LPCR_LPMD_RUN (0)\r
+#define MCF_PMM_LPCR_LPMD_DOZE (0x40)\r
+#define MCF_PMM_LPCR_LPMD_WAIT (0x80)\r
+#define MCF_PMM_LPCR_LPMD_STOP (0xC0)\r
+\r
+\r
+#endif /* __MCF52259_PMM_H__ */\r
--- /dev/null
+/* Coldfire C Header File\r
+ * Copyright Freescale Semiconductor Inc\r
+ * All rights reserved.\r
+ *\r
+ * 2008/04/17 Revision: 0.2\r
+ *\r
+ * (c) Copyright UNIS, spol. s r.o. 1997-2008\r
+ * UNIS, spol. s r.o.\r
+ * Jundrovska 33\r
+ * 624 00 Brno\r
+ * Czech Republic\r
+ * http : www.processorexpert.com\r
+ * mail : info@processorexpert.com\r
+ */\r
+\r
+#ifndef __MCF52259_PWM_H__\r
+#define __MCF52259_PWM_H__\r
+\r
+\r
+/*********************************************************************\r
+*\r
+* Pulse Width Modulation (PWM)\r
+*\r
+*********************************************************************/\r
+\r
+/* Register read/write macros */\r
+#define MCF_PWM_PWME (*(vuint8 *)(0x401B0000))\r
+#define MCF_PWM_PWMPOL (*(vuint8 *)(0x401B0001))\r
+#define MCF_PWM_PWMCLK (*(vuint8 *)(0x401B0002))\r
+#define MCF_PWM_PWMPRCLK (*(vuint8 *)(0x401B0003))\r
+#define MCF_PWM_PWMCAE (*(vuint8 *)(0x401B0004))\r
+#define MCF_PWM_PWMCTL (*(vuint8 *)(0x401B0005))\r
+#define MCF_PWM_PWMSCLA (*(vuint8 *)(0x401B0008))\r
+#define MCF_PWM_PWMSCLB (*(vuint8 *)(0x401B0009))\r
+#define MCF_PWM_PWMCNT0 (*(vuint8 *)(0x401B000C))\r
+#define MCF_PWM_PWMCNT1 (*(vuint8 *)(0x401B000D))\r
+#define MCF_PWM_PWMCNT2 (*(vuint8 *)(0x401B000E))\r
+#define MCF_PWM_PWMCNT3 (*(vuint8 *)(0x401B000F))\r
+#define MCF_PWM_PWMCNT4 (*(vuint8 *)(0x401B0010))\r
+#define MCF_PWM_PWMCNT5 (*(vuint8 *)(0x401B0011))\r
+#define MCF_PWM_PWMCNT6 (*(vuint8 *)(0x401B0012))\r
+#define MCF_PWM_PWMCNT7 (*(vuint8 *)(0x401B0013))\r
+#define MCF_PWM_PWMPER0 (*(vuint8 *)(0x401B0014))\r
+#define MCF_PWM_PWMPER1 (*(vuint8 *)(0x401B0015))\r
+#define MCF_PWM_PWMPER2 (*(vuint8 *)(0x401B0016))\r
+#define MCF_PWM_PWMPER3 (*(vuint8 *)(0x401B0017))\r
+#define MCF_PWM_PWMPER4 (*(vuint8 *)(0x401B0018))\r
+#define MCF_PWM_PWMPER5 (*(vuint8 *)(0x401B0019))\r
+#define MCF_PWM_PWMPER6 (*(vuint8 *)(0x401B001A))\r
+#define MCF_PWM_PWMPER7 (*(vuint8 *)(0x401B001B))\r
+#define MCF_PWM_PWMDTY0 (*(vuint8 *)(0x401B001C))\r
+#define MCF_PWM_PWMDTY1 (*(vuint8 *)(0x401B001D))\r
+#define MCF_PWM_PWMDTY2 (*(vuint8 *)(0x401B001E))\r
+#define MCF_PWM_PWMDTY3 (*(vuint8 *)(0x401B001F))\r
+#define MCF_PWM_PWMDTY4 (*(vuint8 *)(0x401B0020))\r
+#define MCF_PWM_PWMDTY5 (*(vuint8 *)(0x401B0021))\r
+#define MCF_PWM_PWMDTY6 (*(vuint8 *)(0x401B0022))\r
+#define MCF_PWM_PWMDTY7 (*(vuint8 *)(0x401B0023))\r
+#define MCF_PWM_PWMSDN (*(vuint8 *)(0x401B0024))\r
+#define MCF_PWM_PWMCNT(x) (*(vuint8 *)(0x401B000C + ((x)*0x1)))\r
+#define MCF_PWM_PWMPER(x) (*(vuint8 *)(0x401B0014 + ((x)*0x1)))\r
+#define MCF_PWM_PWMDTY(x) (*(vuint8 *)(0x401B001C + ((x)*0x1)))\r
+\r
+\r
+/* Bit definitions and macros for MCF_PWM_PWME */\r
+#define MCF_PWM_PWME_PWME0 (0x1)\r
+#define MCF_PWM_PWME_PWME1 (0x2)\r
+#define MCF_PWM_PWME_PWME2 (0x4)\r
+#define MCF_PWM_PWME_PWME3 (0x8)\r
+#define MCF_PWM_PWME_PWME4 (0x10)\r
+#define MCF_PWM_PWME_PWME5 (0x20)\r
+#define MCF_PWM_PWME_PWME6 (0x40)\r
+#define MCF_PWM_PWME_PWME7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_PWM_PWMPOL */\r
+#define MCF_PWM_PWMPOL_PPOL0 (0x1)\r
+#define MCF_PWM_PWMPOL_PPOL1 (0x2)\r
+#define MCF_PWM_PWMPOL_PPOL2 (0x4)\r
+#define MCF_PWM_PWMPOL_PPOL3 (0x8)\r
+#define MCF_PWM_PWMPOL_PPOL4 (0x10)\r
+#define MCF_PWM_PWMPOL_PPOL5 (0x20)\r
+#define MCF_PWM_PWMPOL_PPOL6 (0x40)\r
+#define MCF_PWM_PWMPOL_PPOL7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_PWM_PWMCLK */\r
+#define MCF_PWM_PWMCLK_PCLK0 (0x1)\r
+#define MCF_PWM_PWMCLK_PCLK1 (0x2)\r
+#define MCF_PWM_PWMCLK_PCLK2 (0x4)\r
+#define MCF_PWM_PWMCLK_PCLK3 (0x8)\r
+#define MCF_PWM_PWMCLK_PCLK4 (0x10)\r
+#define MCF_PWM_PWMCLK_PCLK5 (0x20)\r
+#define MCF_PWM_PWMCLK_PCLK6 (0x40)\r
+#define MCF_PWM_PWMCLK_PCLK7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_PWM_PWMPRCLK */\r
+#define MCF_PWM_PWMPRCLK_PCKA(x) (((x)&0x7)<<0)\r
+#define MCF_PWM_PWMPRCLK_PCKB(x) (((x)&0x7)<<0x4)\r
+\r
+/* Bit definitions and macros for MCF_PWM_PWMCAE */\r
+#define MCF_PWM_PWMCAE_CAE0 (0x1)\r
+#define MCF_PWM_PWMCAE_CAE1 (0x2)\r
+#define MCF_PWM_PWMCAE_CAE2 (0x4)\r
+#define MCF_PWM_PWMCAE_CAE3 (0x8)\r
+#define MCF_PWM_PWMCAE_CAE4 (0x10)\r
+#define MCF_PWM_PWMCAE_CAE5 (0x20)\r
+#define MCF_PWM_PWMCAE_CAE6 (0x40)\r
+#define MCF_PWM_PWMCAE_CAE7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_PWM_PWMCTL */\r
+#define MCF_PWM_PWMCTL_PFRZ (0x4)\r
+#define MCF_PWM_PWMCTL_PSWAI (0x8)\r
+#define MCF_PWM_PWMCTL_CON01 (0x10)\r
+#define MCF_PWM_PWMCTL_CON23 (0x20)\r
+#define MCF_PWM_PWMCTL_CON45 (0x40)\r
+#define MCF_PWM_PWMCTL_CON67 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_PWM_PWMSCLA */\r
+#define MCF_PWM_PWMSCLA_SCALEA(x) (((x)&0xFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_PWM_PWMSCLB */\r
+#define MCF_PWM_PWMSCLB_SCALEB(x) (((x)&0xFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_PWM_PWMCNT */\r
+#define MCF_PWM_PWMCNT_COUNT(x) (((x)&0xFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_PWM_PWMPER */\r
+#define MCF_PWM_PWMPER_PERIOD(x) (((x)&0xFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_PWM_PWMDTY */\r
+#define MCF_PWM_PWMDTY_DUTY(x) (((x)&0xFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_PWM_PWMSDN */\r
+#define MCF_PWM_PWMSDN_SDNEN (0x1)\r
+#define MCF_PWM_PWMSDN_PWM7IL (0x2)\r
+#define MCF_PWM_PWMSDN_PWM7IN (0x4)\r
+#define MCF_PWM_PWMSDN_LVL (0x10)\r
+#define MCF_PWM_PWMSDN_RESTART (0x20)\r
+#define MCF_PWM_PWMSDN_IE (0x40)\r
+#define MCF_PWM_PWMSDN_IF (0x80)\r
+\r
+\r
+#endif /* __MCF52259_PWM_H__ */\r
--- /dev/null
+/* Coldfire C Header File\r
+ * Copyright Freescale Semiconductor Inc\r
+ * All rights reserved.\r
+ *\r
+ * 2008/04/17 Revision: 0.2\r
+ *\r
+ * (c) Copyright UNIS, spol. s r.o. 1997-2008\r
+ * UNIS, spol. s r.o.\r
+ * Jundrovska 33\r
+ * 624 00 Brno\r
+ * Czech Republic\r
+ * http : www.processorexpert.com\r
+ * mail : info@processorexpert.com\r
+ */\r
+\r
+#ifndef __MCF52259_QSPI_H__\r
+#define __MCF52259_QSPI_H__\r
+\r
+\r
+/*********************************************************************\r
+*\r
+* Queued Serial Peripheral Interface (QSPI)\r
+*\r
+*********************************************************************/\r
+\r
+/* Register read/write macros */\r
+#define MCF_QSPI_QMR (*(vuint16*)(0x40000340))\r
+#define MCF_QSPI_QDLYR (*(vuint16*)(0x40000344))\r
+#define MCF_QSPI_QWR (*(vuint16*)(0x40000348))\r
+#define MCF_QSPI_QIR (*(vuint16*)(0x4000034C))\r
+#define MCF_QSPI_QAR (*(vuint16*)(0x40000350))\r
+#define MCF_QSPI_QDR (*(vuint16*)(0x40000354))\r
+\r
+\r
+/* Bit definitions and macros for MCF_QSPI_QMR */\r
+#define MCF_QSPI_QMR_BAUD(x) (((x)&0xFF)<<0)\r
+#define MCF_QSPI_QMR_CPHA (0x100)\r
+#define MCF_QSPI_QMR_CPOL (0x200)\r
+#define MCF_QSPI_QMR_BITS(x) (((x)&0xF)<<0xA)\r
+#define MCF_QSPI_QMR_DOHIE (0x4000)\r
+#define MCF_QSPI_QMR_MSTR (0x8000)\r
+\r
+/* Bit definitions and macros for MCF_QSPI_QDLYR */\r
+#define MCF_QSPI_QDLYR_DTL(x) (((x)&0xFF)<<0)\r
+#define MCF_QSPI_QDLYR_QCD(x) (((x)&0x7F)<<0x8)\r
+#define MCF_QSPI_QDLYR_SPE (0x8000)\r
+\r
+/* Bit definitions and macros for MCF_QSPI_QWR */\r
+#define MCF_QSPI_QWR_NEWQP(x) (((x)&0xF)<<0)\r
+#define MCF_QSPI_QWR_CPTQP(x) (((x)&0xF)<<0x4)\r
+#define MCF_QSPI_QWR_ENDQP(x) (((x)&0xF)<<0x8)\r
+#define MCF_QSPI_QWR_CSIV (0x1000)\r
+#define MCF_QSPI_QWR_WRTO (0x2000)\r
+#define MCF_QSPI_QWR_WREN (0x4000)\r
+#define MCF_QSPI_QWR_HALT (0x8000)\r
+\r
+/* Bit definitions and macros for MCF_QSPI_QIR */\r
+#define MCF_QSPI_QIR_SPIF (0x1)\r
+#define MCF_QSPI_QIR_ABRT (0x4)\r
+#define MCF_QSPI_QIR_WCEF (0x8)\r
+#define MCF_QSPI_QIR_SPIFE (0x100)\r
+#define MCF_QSPI_QIR_ABRTE (0x400)\r
+#define MCF_QSPI_QIR_WCEFE (0x800)\r
+#define MCF_QSPI_QIR_ABRTL (0x1000)\r
+#define MCF_QSPI_QIR_ABRTB (0x4000)\r
+#define MCF_QSPI_QIR_WCEFB (0x8000)\r
+\r
+/* Bit definitions and macros for MCF_QSPI_QAR */\r
+#define MCF_QSPI_QAR_ADDR(x) (((x)&0x3F)<<0)\r
+#define MCF_QSPI_QAR_TRANS (0)\r
+#define MCF_QSPI_QAR_RECV (0x10)\r
+#define MCF_QSPI_QAR_CMD (0x20)\r
+\r
+/* Bit definitions and macros for MCF_QSPI_QDR */\r
+#define MCF_QSPI_QDR_DATA(x) (((x)&0xFFFF)<<0)\r
+#define MCF_QSPI_QDR_CONT (0x8000)\r
+#define MCF_QSPI_QDR_BITSE (0x4000)\r
+#define MCF_QSPI_QDR_DT (0x2000)\r
+#define MCF_QSPI_QDR_DSCK (0x1000)\r
+#define MCF_QSPI_QDR_QSPI_CS3 (0x800)\r
+#define MCF_QSPI_QDR_QSPI_CS2 (0x400)\r
+#define MCF_QSPI_QDR_QSPI_CS1 (0x200)\r
+#define MCF_QSPI_QDR_QSPI_CS0 (0x100)\r
+\r
+\r
+#endif /* __MCF52259_QSPI_H__ */\r
--- /dev/null
+/* Coldfire C Header File\r
+ * Copyright Freescale Semiconductor Inc\r
+ * All rights reserved.\r
+ *\r
+ * 2008/04/17 Revision: 0.2\r
+ *\r
+ * (c) Copyright UNIS, spol. s r.o. 1997-2008\r
+ * UNIS, spol. s r.o.\r
+ * Jundrovska 33\r
+ * 624 00 Brno\r
+ * Czech Republic\r
+ * http : www.processorexpert.com\r
+ * mail : info@processorexpert.com\r
+ */\r
+\r
+#ifndef __MCF52259_RCM_H__\r
+#define __MCF52259_RCM_H__\r
+\r
+\r
+/*********************************************************************\r
+*\r
+* Reset Controller Module (RCM)\r
+*\r
+*********************************************************************/\r
+\r
+/* Register read/write macros */\r
+#define MCF_RCM_RCR (*(vuint8 *)(0x40110000))\r
+#define MCF_RCM_RSR (*(vuint8 *)(0x40110001))\r
+\r
+\r
+/* Bit definitions and macros for MCF_RCM_RCR */\r
+#define MCF_RCM_RCR_LVDE (0x1)\r
+#define MCF_RCM_RCR_LVDRE (0x4)\r
+#define MCF_RCM_RCR_LVDIE (0x8)\r
+#define MCF_RCM_RCR_LVDF (0x10)\r
+#define MCF_RCM_RCR_FRCRSTOUT (0x40)\r
+#define MCF_RCM_RCR_SOFTRST (0x80)\r
+\r
+/* Bit definitions and macros for MCF_RCM_RSR */\r
+#define MCF_RCM_RSR_LOL (0x1)\r
+#define MCF_RCM_RSR_LOC (0x2)\r
+#define MCF_RCM_RSR_EXT (0x4)\r
+#define MCF_RCM_RSR_POR (0x8)\r
+#define MCF_RCM_RSR_WDR (0x10)\r
+#define MCF_RCM_RSR_SOFT (0x20)\r
+#define MCF_RCM_RSR_LVD (0x40)\r
+\r
+\r
+#endif /* __MCF52259_RCM_H__ */\r
--- /dev/null
+/* Coldfire C Header File\r
+ * Copyright Freescale Semiconductor Inc\r
+ * All rights reserved.\r
+ *\r
+ * 2008/04/17 Revision: 0.2\r
+ *\r
+ * (c) Copyright UNIS, spol. s r.o. 1997-2008\r
+ * UNIS, spol. s r.o.\r
+ * Jundrovska 33\r
+ * 624 00 Brno\r
+ * Czech Republic\r
+ * http : www.processorexpert.com\r
+ * mail : info@processorexpert.com\r
+ */\r
+\r
+#ifndef __MCF52259_RNGA_H__\r
+#define __MCF52259_RNGA_H__\r
+\r
+\r
+/*********************************************************************\r
+*\r
+* Random Number Generator (RNG)\r
+*\r
+*********************************************************************/\r
+\r
+/* Register read/write macros */\r
+#define MCF_RNGA_RNGCR (*(vuint32*)(0x401F0000))\r
+#define MCF_RNGA_RNGSR (*(vuint32*)(0x401F0004))\r
+#define MCF_RNGA_RNGER (*(vuint32*)(0x401F0008))\r
+#define MCF_RNGA_RNGOUT (*(vuint32*)(0x401F000C))\r
+\r
+\r
+/* Bit definitions and macros for MCF_RNGA_RNGCR */\r
+#define MCF_RNGA_RNGCR_GO (0x1)\r
+#define MCF_RNGA_RNGCR_HA (0x2)\r
+#define MCF_RNGA_RNGCR_IM (0x4)\r
+#define MCF_RNGA_RNGCR_CI (0x8)\r
+#define MCF_RNGA_RNGCR_SLM (0x10)\r
+\r
+/* Bit definitions and macros for MCF_RNGA_RNGSR */\r
+#define MCF_RNGA_RNGSR_SV (0x1)\r
+#define MCF_RNGA_RNGSR_LRS (0x2)\r
+#define MCF_RNGA_RNGSR_FUF (0x4)\r
+#define MCF_RNGA_RNGSR_EI (0x8)\r
+#define MCF_RNGA_RNGSR_SLP (0x10)\r
+#define MCF_RNGA_RNGSR_OFL(x) (((x)&0xFF)<<0x8)\r
+#define MCF_RNGA_RNGSR_OFS(x) (((x)&0xFF)<<0x10)\r
+\r
+/* Bit definitions and macros for MCF_RNGA_RNGER */\r
+#define MCF_RNGA_RNGER_ENT(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_RNGA_RNGOUT */\r
+#define MCF_RNGA_RNGOUT_RANDOM_OUTPUT(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+\r
+#endif /* __MCF52259_RNGA_H__ */\r
--- /dev/null
+/* Coldfire C Header File\r
+ * Copyright Freescale Semiconductor Inc\r
+ * All rights reserved.\r
+ *\r
+ * 2008/04/17 Revision: 0.2\r
+ *\r
+ * (c) Copyright UNIS, spol. s r.o. 1997-2008\r
+ * UNIS, spol. s r.o.\r
+ * Jundrovska 33\r
+ * 624 00 Brno\r
+ * Czech Republic\r
+ * http : www.processorexpert.com\r
+ * mail : info@processorexpert.com\r
+ */\r
+\r
+#ifndef __MCF52259_RTC_H__\r
+#define __MCF52259_RTC_H__\r
+\r
+\r
+/*********************************************************************\r
+*\r
+* Real-Time Clock (RTC)\r
+*\r
+*********************************************************************/\r
+\r
+/* Register read/write macros */\r
+#define MCF_RTC_HOURMIN (*(vuint32*)(0x40180000))\r
+#define MCF_RTC_SECONDS (*(vuint32*)(0x40180004))\r
+#define MCF_RTC_ALRM_HM (*(vuint32*)(0x40180008))\r
+#define MCF_RTC_ALRM_SEC (*(vuint32*)(0x4018000C))\r
+#define MCF_RTC_RTCCTL (*(vuint32*)(0x40180010))\r
+#define MCF_RTC_RTCISR (*(vuint32*)(0x40180014))\r
+#define MCF_RTC_RTCIENR (*(vuint32*)(0x40180018))\r
+#define MCF_RTC_STPWCH (*(vuint32*)(0x4018001C))\r
+#define MCF_RTC_DAYS (*(vuint32*)(0x40180020))\r
+#define MCF_RTC_ALRM_DAY (*(vuint32*)(0x40180024))\r
+#define MCF_RTC_RTCGOCU (*(vuint32*)(0x40180034))\r
+#define MCF_RTC_RTCGOCL (*(vuint32*)(0x40180038))\r
+\r
+\r
+/* Bit definitions and macros for MCF_RTC_HOURMIN */\r
+#define MCF_RTC_HOURMIN_MINUTES(x) (((x)&0x3F)<<0)\r
+#define MCF_RTC_HOURMIN_HOURS(x) (((x)&0x1F)<<0x8)\r
+\r
+/* Bit definitions and macros for MCF_RTC_SECONDS */\r
+#define MCF_RTC_SECONDS_SECONDS(x) (((x)&0x3F)<<0)\r
+\r
+/* Bit definitions and macros for MCF_RTC_ALRM_HM */\r
+#define MCF_RTC_ALRM_HM_MINUTES(x) (((x)&0x3F)<<0)\r
+#define MCF_RTC_ALRM_HM_HOURS(x) (((x)&0x1F)<<0x8)\r
+\r
+/* Bit definitions and macros for MCF_RTC_ALRM_SEC */\r
+#define MCF_RTC_ALRM_SEC_SECONDS(x) (((x)&0x3F)<<0)\r
+\r
+/* Bit definitions and macros for MCF_RTC_RTCCTL */\r
+#define MCF_RTC_RTCCTL_SWR (0x1)\r
+#define MCF_RTC_RTCCTL_EN (0x80)\r
+\r
+/* Bit definitions and macros for MCF_RTC_RTCISR */\r
+#define MCF_RTC_RTCISR_SW (0x1)\r
+#define MCF_RTC_RTCISR_MIN (0x2)\r
+#define MCF_RTC_RTCISR_ALM (0x4)\r
+#define MCF_RTC_RTCISR_DAY (0x8)\r
+#define MCF_RTC_RTCISR_1HZ (0x10)\r
+#define MCF_RTC_RTCISR_HR (0x20)\r
+\r
+/* Bit definitions and macros for MCF_RTC_RTCIENR */\r
+#define MCF_RTC_RTCIENR_SW (0x1)\r
+#define MCF_RTC_RTCIENR_MIN (0x2)\r
+#define MCF_RTC_RTCIENR_ALM (0x4)\r
+#define MCF_RTC_RTCIENR_DAY (0x8)\r
+#define MCF_RTC_RTCIENR_1HZ (0x10)\r
+#define MCF_RTC_RTCIENR_HR (0x20)\r
+\r
+/* Bit definitions and macros for MCF_RTC_STPWCH */\r
+#define MCF_RTC_STPWCH_CNT(x) (((x)&0x3F)<<0)\r
+\r
+/* Bit definitions and macros for MCF_RTC_DAYS */\r
+#define MCF_RTC_DAYS_DAYS(x) (((x)&0xFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_RTC_ALRM_DAY */\r
+#define MCF_RTC_ALRM_DAY_DAYSAL(x) (((x)&0xFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_RTC_RTCGOCU */\r
+#define MCF_RTC_RTCGOCU_RTCGOCNT(x) (((x)&0xFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_RTC_RTCGOCL */\r
+#define MCF_RTC_RTCGOCL_RTCGOCNT(x) (((x)&0xFFFF)<<0)\r
+\r
+\r
+#endif /* __MCF52259_RTC_H__ */\r
--- /dev/null
+/* Coldfire C Header File\r
+ * Copyright Freescale Semiconductor Inc\r
+ * All rights reserved.\r
+ *\r
+ * 2008/04/17 Revision: 0.2\r
+ *\r
+ * (c) Copyright UNIS, spol. s r.o. 1997-2008\r
+ * UNIS, spol. s r.o.\r
+ * Jundrovska 33\r
+ * 624 00 Brno\r
+ * Czech Republic\r
+ * http : www.processorexpert.com\r
+ * mail : info@processorexpert.com\r
+ */\r
+\r
+#ifndef __MCF52259_SCM_H__\r
+#define __MCF52259_SCM_H__\r
+\r
+\r
+/*********************************************************************\r
+*\r
+* System Control Module (SCM)\r
+*\r
+*********************************************************************/\r
+\r
+/* Register read/write macros */\r
+#define MCF_SCM_RAMBAR (*(vuint32*)(&__IPSBAR[0x8]))\r
+#define MCF_SCM_PPMRH (*(vuint32*)(&__IPSBAR[0xC]))\r
+#define MCF_SCM_CRSR (*(vuint8 *)(&__IPSBAR[0x10]))\r
+#define MCF_SCM_CWCR (*(vuint8 *)(&__IPSBAR[0x11]))\r
+#define MCF_SCM_CWSR (*(vuint8 *)(&__IPSBAR[0x13]))\r
+#define MCF_SCM_DMAREQC (*(vuint32*)(&__IPSBAR[0x14]))\r
+#define MCF_SCM_PPMRL (*(vuint32*)(&__IPSBAR[0x18]))\r
+#define MCF_SCM_MPARK (*(vuint32*)(&__IPSBAR[0x1C]))\r
+#define MCF_SCM_MPR (*(vuint8 *)(&__IPSBAR[0x20]))\r
+#define MCF_SCM_PPMRS (*(vuint8 *)(&__IPSBAR[0x21]))\r
+#define MCF_SCM_PPMRC (*(vuint8 *)(&__IPSBAR[0x22]))\r
+#define MCF_SCM_IPSBMT (*(vuint8 *)(&__IPSBAR[0x23]))\r
+#define MCF_SCM_PACR0 (*(vuint8 *)(&__IPSBAR[0x24]))\r
+#define MCF_SCM_PACR1 (*(vuint8 *)(&__IPSBAR[0x25]))\r
+#define MCF_SCM_PACR2 (*(vuint8 *)(&__IPSBAR[0x26]))\r
+#define MCF_SCM_PACR3 (*(vuint8 *)(&__IPSBAR[0x27]))\r
+#define MCF_SCM_PACR4 (*(vuint8 *)(&__IPSBAR[0x28]))\r
+#define MCF_SCM_PACR5 (*(vuint8 *)(&__IPSBAR[0x29]))\r
+#define MCF_SCM_PACR6 (*(vuint8 *)(&__IPSBAR[0x2A]))\r
+#define MCF_SCM_PACR7 (*(vuint8 *)(&__IPSBAR[0x2B]))\r
+#define MCF_SCM_PACR8 (*(vuint8 *)(&__IPSBAR[0x2C]))\r
+#define MCF_SCM_PACR10 (*(vuint8 *)(&__IPSBAR[0x2E]))\r
+#define MCF_SCM_GPACR0 (*(vuint8 *)(&__IPSBAR[0x30]))\r
+#define MCF_SCM_GPACR1 (*(vuint8 *)(&__IPSBAR[0x31]))\r
+#define MCF_SCM_PACR(x) (*(vuint8 *)(&__IPSBAR[0x24 + ((x)*0x1)]))\r
+#define MCF_SCM_GPACR(x) (*(vuint8 *)(&__IPSBAR[0x30 + ((x)*0x1)]))\r
+\r
+/* Other macros */\r
+#define MCF_SCM_IPSBAR (*(vuint32*)(&__IPSBAR[0x0]))\r
+#define MCF_SCM_IPSBAR_V (0x1)\r
+#define MCF_SCM_IPSBAR_BA(x) ((x)&0xC0000000)\r
+\r
+\r
+/* Bit definitions and macros for MCF_SCM_RAMBAR */\r
+#define MCF_SCM_RAMBAR_BDE (0x200)\r
+#define MCF_SCM_RAMBAR_BA(x) ((x)&0xFFFF0000)\r
+\r
+/* Bit definitions and macros for MCF_SCM_PPMRH */\r
+#define MCF_SCM_PPMRH_CDGPIO (0x1)\r
+#define MCF_SCM_PPMRH_CDEPORT (0x2)\r
+#define MCF_SCM_PPMRH_CDPIT0 (0x8)\r
+#define MCF_SCM_PPMRH_CDPIT1 (0x10)\r
+#define MCF_SCM_PPMRH_CDADC (0x80)\r
+#define MCF_SCM_PPMRH_CDGPT (0x100)\r
+#define MCF_SCM_PPMRH_CDPWM (0x200)\r
+#define MCF_SCM_PPMRH_CDCFM (0x800)\r
+#define MCF_SCM_PPMRH_CDUSB (0x1000)\r
+\r
+/* Bit definitions and macros for MCF_SCM_CRSR */\r
+#define MCF_SCM_CRSR_EXT (0x80)\r
+\r
+/* Bit definitions and macros for MCF_SCM_CWCR */\r
+#define MCF_SCM_CWCR_CWTIF (0x1)\r
+#define MCF_SCM_CWCR_CWTAVAL (0x2)\r
+#define MCF_SCM_CWCR_CWTA (0x4)\r
+#define MCF_SCM_CWCR_CWT(x) (((x)&0x7)<<0x3)\r
+#define MCF_SCM_CWCR_CWT_2_9 (0)\r
+#define MCF_SCM_CWCR_CWT_2_11 (0x8)\r
+#define MCF_SCM_CWCR_CWT_2_13 (0x10)\r
+#define MCF_SCM_CWCR_CWT_2_15 (0x18)\r
+#define MCF_SCM_CWCR_CWT_2_19 (0x20)\r
+#define MCF_SCM_CWCR_CWT_2_23 (0x28)\r
+#define MCF_SCM_CWCR_CWT_2_27 (0x30)\r
+#define MCF_SCM_CWCR_CWT_2_31 (0x38)\r
+#define MCF_SCM_CWCR_CWRI (0x40)\r
+#define MCF_SCM_CWCR_CWE (0x80)\r
+\r
+/* Bit definitions and macros for MCF_SCM_CWSR */\r
+#define MCF_SCM_CWSR_CWSR(x) (((x)&0xFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_SCM_DMAREQC */\r
+#define MCF_SCM_DMAREQC_DMAC0(x) (((x)&0xF)<<0)\r
+#define MCF_SCM_DMAREQC_DMAC1(x) (((x)&0xF)<<0x4)\r
+#define MCF_SCM_DMAREQC_DMAC2(x) (((x)&0xF)<<0x8)\r
+#define MCF_SCM_DMAREQC_DMAC3(x) (((x)&0xF)<<0xC)\r
+\r
+/* Bit definitions and macros for MCF_SCM_PPMRL */\r
+#define MCF_SCM_PPMRL_CDG (0x2)\r
+#define MCF_SCM_PPMRL_CDMINIBUS (0x8)\r
+#define MCF_SCM_PPMRL_CDDMA (0x10)\r
+#define MCF_SCM_PPMRL_CDUART0 (0x20)\r
+#define MCF_SCM_PPMRL_CDUART1 (0x40)\r
+#define MCF_SCM_PPMRL_CDUART2 (0x80)\r
+#define MCF_SCM_PPMRL_CDI2C0 (0x200)\r
+#define MCF_SCM_PPMRL_CDQSPI (0x400)\r
+#define MCF_SCM_PPMRL_CDI2C1 (0x800)\r
+#define MCF_SCM_PPMRL_CDDTIM0 (0x2000)\r
+#define MCF_SCM_PPMRL_CDDTIM1 (0x4000)\r
+#define MCF_SCM_PPMRL_CDDTIM2 (0x8000)\r
+#define MCF_SCM_PPMRL_CDDTIM3 (0x10000)\r
+#define MCF_SCM_PPMRL_CDINTC0 (0x20000)\r
+#define MCF_SCM_PPMRL_CDINTC1 (0x40000)\r
+#define MCF_SCM_PPMRL_CDFEC (0x200000)\r
+\r
+/* Bit definitions and macros for MCF_SCM_MPARK */\r
+#define MCF_SCM_MPARK_LCKOUT_TIME(x) (((x)&0xF)<<0x8)\r
+#define MCF_SCM_MPARK_PRKLAST (0x1000)\r
+#define MCF_SCM_MPARK_TIMEOUT (0x2000)\r
+#define MCF_SCM_MPARK_FIXED (0x4000)\r
+#define MCF_SCM_MPARK_M1_PRTY(x) (((x)&0x3)<<0x10)\r
+#define MCF_SCM_MPARK_M0_PRTY(x) (((x)&0x3)<<0x12)\r
+#define MCF_SCM_MPARK_M2_PRTY(x) (((x)&0x3)<<0x14)\r
+#define MCF_SCM_MPARK_M3_PRTY(x) (((x)&0x3)<<0x16)\r
+#define MCF_SCM_MPARK_BCR24BIT (0x1000000)\r
+#define MCF_SCM_MPARK_M2_P_EN (0x2000000)\r
+\r
+/* Bit definitions and macros for MCF_SCM_MPR */\r
+#define MCF_SCM_MPR_MPR(x) (((x)&0xF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_SCM_PPMRS */\r
+#define MCF_SCM_PPMRS_PPMRS(x) (((x)&0x7F)<<0)\r
+#define MCF_SCM_PPMRS_DISABLE_ALL (0x40)\r
+#define MCF_SCM_PPMRS_DISABLE_CFM (0x2B)\r
+#define MCF_SCM_PPMRS_DISABLE_CAN (0x2A)\r
+#define MCF_SCM_PPMRS_DISABLE_PWM (0x29)\r
+#define MCF_SCM_PPMRS_DISABLE_GPT (0x28)\r
+#define MCF_SCM_PPMRS_DISABLE_ADC (0x27)\r
+#define MCF_SCM_PPMRS_DISABLE_PIT1 (0x24)\r
+#define MCF_SCM_PPMRS_DISABLE_PIT0 (0x23)\r
+#define MCF_SCM_PPMRS_DISABLE_EPORT (0x21)\r
+#define MCF_SCM_PPMRS_DISABLE_PORTS (0x20)\r
+#define MCF_SCM_PPMRS_DISABLE_INTC (0x11)\r
+#define MCF_SCM_PPMRS_DISABLE_DTIM3 (0x10)\r
+#define MCF_SCM_PPMRS_DISABLE_DTIM2 (0xF)\r
+#define MCF_SCM_PPMRS_DISABLE_DTIM1 (0xE)\r
+#define MCF_SCM_PPMRS_DISABLE_DTIM0 (0xD)\r
+#define MCF_SCM_PPMRS_DISABLE_QSPI (0xA)\r
+#define MCF_SCM_PPMRS_DISABLE_I2C (0x9)\r
+#define MCF_SCM_PPMRS_DISABLE_UART2 (0x7)\r
+#define MCF_SCM_PPMRS_DISABLE_UART1 (0x6)\r
+#define MCF_SCM_PPMRS_DISABLE_UART0 (0x5)\r
+#define MCF_SCM_PPMRS_DISABLE_DMA (0x4)\r
+#define MCF_SCM_PPMRS_SET_CDG (0x1)\r
+\r
+/* Bit definitions and macros for MCF_SCM_PPMRC */\r
+#define MCF_SCM_PPMRC_PPMRC(x) (((x)&0x7F)<<0)\r
+#define MCF_SCM_PPMRC_ENABLE_ALL (0x40)\r
+#define MCF_SCM_PPMRC_ENABLE_CFM (0x2B)\r
+#define MCF_SCM_PPMRC_ENABLE_CAN (0x2A)\r
+#define MCF_SCM_PPMRC_ENABLE_PWM (0x29)\r
+#define MCF_SCM_PPMRC_ENABLE_GPT (0x28)\r
+#define MCF_SCM_PPMRC_ENABLE_ADC (0x27)\r
+#define MCF_SCM_PPMRC_ENABLE_PIT1 (0x24)\r
+#define MCF_SCM_PPMRC_ENABLE_PIT0 (0x23)\r
+#define MCF_SCM_PPMRC_ENABLE_EPORT (0x21)\r
+#define MCF_SCM_PPMRC_ENABLE_PORTS (0x20)\r
+#define MCF_SCM_PPMRC_ENABLE_INTC (0x11)\r
+#define MCF_SCM_PPMRC_ENABLE_DTIM3 (0x10)\r
+#define MCF_SCM_PPMRC_ENABLE_DTIM2 (0xF)\r
+#define MCF_SCM_PPMRC_ENABLE_DTIM1 (0xE)\r
+#define MCF_SCM_PPMRC_ENABLE_DTIM0 (0xD)\r
+#define MCF_SCM_PPMRC_ENABLE_QSPI (0xA)\r
+#define MCF_SCM_PPMRC_ENABLE_I2C (0x9)\r
+#define MCF_SCM_PPMRC_ENABLE_UART2 (0x7)\r
+#define MCF_SCM_PPMRC_ENABLE_UART1 (0x6)\r
+#define MCF_SCM_PPMRC_ENABLE_UART0 (0x5)\r
+#define MCF_SCM_PPMRC_ENABLE_DMA (0x4)\r
+#define MCF_SCM_PPMRC_CLEAR_CDG (0x1)\r
+\r
+/* Bit definitions and macros for MCF_SCM_IPSBMT */\r
+#define MCF_SCM_IPSBMT_BMT(x) (((x)&0x7)<<0)\r
+#define MCF_SCM_IPSBMT_BMT_CYCLES_1024 (0)\r
+#define MCF_SCM_IPSBMT_BMT_CYCLES_512 (0x1)\r
+#define MCF_SCM_IPSBMT_BMT_CYCLES_256 (0x2)\r
+#define MCF_SCM_IPSBMT_BMT_CYCLES_128 (0x3)\r
+#define MCF_SCM_IPSBMT_BMT_CYCLES_64 (0x4)\r
+#define MCF_SCM_IPSBMT_BMT_CYCLES_32 (0x5)\r
+#define MCF_SCM_IPSBMT_BMT_CYCLES_16 (0x6)\r
+#define MCF_SCM_IPSBMT_BMT_CYCLES_8 (0x7)\r
+#define MCF_SCM_IPSBMT_BME (0x8)\r
+\r
+/* Bit definitions and macros for MCF_SCM_PACR */\r
+#define MCF_SCM_PACR_ACCESS_CTRL0(x) (((x)&0x7)<<0)\r
+#define MCF_SCM_PACR_LOCK0 (0x8)\r
+#define MCF_SCM_PACR_ACCESS_CTRL1(x) (((x)&0x7)<<0x4)\r
+#define MCF_SCM_PACR_LOCK1 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_SCM_PACR10 */\r
+#define MCF_SCM_PACR10_ACCESS_CTRL0(x) (((x)&0x7)<<0)\r
+#define MCF_SCM_PACR10_LOCK0 (0x8)\r
+#define MCF_SCM_PACR10_ACCESS_CTRL1(x) (((x)&0x7)<<0x4)\r
+#define MCF_SCM_PACR10_LOCK1 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_SCM_GPACR */\r
+#define MCF_SCM_GPACR_ACCESS_CTRL(x) (((x)&0xF)<<0)\r
+#define MCF_SCM_GPACR_LOCK (0x80)\r
+\r
+\r
+#endif /* __MCF52259_SCM_H__ */\r
--- /dev/null
+/* Coldfire C Header File\r
+ * Copyright Freescale Semiconductor Inc\r
+ * All rights reserved.\r
+ *\r
+ * 2008/02/26 Revision: 0.1\r
+ *\r
+ * (c) Copyright UNIS, spol. s r.o. 1997-2008\r
+ * UNIS, spol. s r.o.\r
+ * Jundrovska 33\r
+ * 624 00 Brno\r
+ * Czech Republic\r
+ * http : www.processorexpert.com\r
+ * mail : info@processorexpert.com\r
+ */\r
+\r
+#ifndef __MCF52259_TMR_H__\r
+#define __MCF52259_TMR_H__\r
+\r
+\r
+/*********************************************************************\r
+*\r
+* Timer Module (TMR)\r
+*\r
+*********************************************************************/\r
+\r
+/* Register read/write macros */\r
+#define MCF_TMR0_TMR (*(vuint16*)(0x40000400))\r
+#define MCF_TMR0_TRR (*(vuint16*)(0x40000404))\r
+#define MCF_TMR0_TCR (*(vuint16*)(0x40000408))\r
+#define MCF_TMR0_TCN (*(vuint16*)(0x4000040C))\r
+#define MCF_TMR0_TER (*(vuint8 *)(0x40000411))\r
+\r
+#define MCF_TMR1_TMR (*(vuint16*)(0x40000440))\r
+#define MCF_TMR1_TRR (*(vuint16*)(0x40000444))\r
+#define MCF_TMR1_TCR (*(vuint16*)(0x40000448))\r
+#define MCF_TMR1_TCN (*(vuint16*)(0x4000044C))\r
+#define MCF_TMR1_TER (*(vuint8 *)(0x40000451))\r
+\r
+#define MCF_TMR2_TMR (*(vuint16*)(0x40000480))\r
+#define MCF_TMR2_TRR (*(vuint16*)(0x40000484))\r
+#define MCF_TMR2_TCR (*(vuint16*)(0x40000488))\r
+#define MCF_TMR2_TCN (*(vuint16*)(0x4000048C))\r
+#define MCF_TMR2_TER (*(vuint8 *)(0x40000491))\r
+\r
+#define MCF_TMR3_TMR (*(vuint16*)(0x400004C0))\r
+#define MCF_TMR3_TRR (*(vuint16*)(0x400004C4))\r
+#define MCF_TMR3_TCR (*(vuint16*)(0x400004C8))\r
+#define MCF_TMR3_TCN (*(vuint16*)(0x400004CC))\r
+#define MCF_TMR3_TER (*(vuint8 *)(0x400004D1))\r
+\r
+#define MCF_TMR_TMR(x) (*(vuint16*)(0x40000400 + ((x)*0x40)))\r
+#define MCF_TMR_TRR(x) (*(vuint16*)(0x40000404 + ((x)*0x40)))\r
+#define MCF_TMR_TCR(x) (*(vuint16*)(0x40000408 + ((x)*0x40)))\r
+#define MCF_TMR_TCN(x) (*(vuint16*)(0x4000040C + ((x)*0x40)))\r
+#define MCF_TMR_TER(x) (*(vuint8 *)(0x40000411 + ((x)*0x40)))\r
+\r
+\r
+/* Bit definitions and macros for MCF_TMR_TMR */\r
+#define MCF_TMR_TMR_RST (0x1)\r
+#define MCF_TMR_TMR_CLK(x) (((x)&0x3)<<0x1)\r
+#define MCF_TMR_TMR_CLK_STOP (0)\r
+#define MCF_TMR_TMR_CLK_SYSCLK (0x2)\r
+#define MCF_TMR_TMR_CLK_DIV16 (0x4)\r
+#define MCF_TMR_TMR_CLK_TIN (0x6)\r
+#define MCF_TMR_TMR_FRR (0x8)\r
+#define MCF_TMR_TMR_ORI (0x10)\r
+#define MCF_TMR_TMR_OM (0x20)\r
+#define MCF_TMR_TMR_CE(x) (((x)&0x3)<<0x6)\r
+#define MCF_TMR_TMR_CE_NONE (0)\r
+#define MCF_TMR_TMR_CE_RISE (0x40)\r
+#define MCF_TMR_TMR_CE_FALL (0x80)\r
+#define MCF_TMR_TMR_CE_ANY (0xC0)\r
+#define MCF_TMR_TMR_PS(x) (((x)&0xFF)<<0x8)\r
+\r
+/* Bit definitions and macros for MCF_TMR_TRR */\r
+#define MCF_TMR_TRR_REF(x) (((x)&0xFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_TMR_TCR */\r
+#define MCF_TMR_TCR_CAP(x) (((x)&0xFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_TMR_TCN */\r
+#define MCF_TMR_TCN_COUNT(x) (((x)&0xFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_TMR_TER */\r
+#define MCF_TMR_TER_CAP (0x1)\r
+#define MCF_TMR_TER_REF (0x2)\r
+\r
+\r
+#endif /* __MCF52259_TMR_H__ */\r
--- /dev/null
+/* Coldfire C Header File\r
+ * Copyright Freescale Semiconductor Inc\r
+ * All rights reserved.\r
+ *\r
+ * 2008/04/17 Revision: 0.2\r
+ *\r
+ * (c) Copyright UNIS, spol. s r.o. 1997-2008\r
+ * UNIS, spol. s r.o.\r
+ * Jundrovska 33\r
+ * 624 00 Brno\r
+ * Czech Republic\r
+ * http : www.processorexpert.com\r
+ * mail : info@processorexpert.com\r
+ */\r
+\r
+#ifndef __MCF52259_UART_H__\r
+#define __MCF52259_UART_H__\r
+\r
+\r
+/*********************************************************************\r
+*\r
+* Universal Asynchronous Receiver Transmitter (UART)\r
+*\r
+*********************************************************************/\r
+\r
+/* Register read/write macros */\r
+#define MCF_UART0_UMR1 (*(vuint8 *)(0x40000200))\r
+#define MCF_UART0_UMR2 (*(vuint8 *)(0x40000200))\r
+#define MCF_UART0_USR (*(vuint8 *)(0x40000204))\r
+#define MCF_UART0_UCSR (*(vuint8 *)(0x40000204))\r
+#define MCF_UART0_UCR (*(vuint8 *)(0x40000208))\r
+#define MCF_UART0_URB (*(vuint8 *)(0x4000020C))\r
+#define MCF_UART0_UTB (*(vuint8 *)(0x4000020C))\r
+#define MCF_UART0_UIPCR (*(vuint8 *)(0x40000210))\r
+#define MCF_UART0_UACR (*(vuint8 *)(0x40000210))\r
+#define MCF_UART0_UIMR (*(vuint8 *)(0x40000214))\r
+#define MCF_UART0_UISR (*(vuint8 *)(0x40000214))\r
+#define MCF_UART0_UBG1 (*(vuint8 *)(0x40000218))\r
+#define MCF_UART0_UBG2 (*(vuint8 *)(0x4000021C))\r
+#define MCF_UART0_UIP (*(vuint8 *)(0x40000234))\r
+#define MCF_UART0_UOP1 (*(vuint8 *)(0x40000238))\r
+#define MCF_UART0_UOP0 (*(vuint8 *)(0x4000023C))\r
+\r
+#define MCF_UART1_UMR1 (*(vuint8 *)(0x40000240))\r
+#define MCF_UART1_UMR2 (*(vuint8 *)(0x40000240))\r
+#define MCF_UART1_USR (*(vuint8 *)(0x40000244))\r
+#define MCF_UART1_UCSR (*(vuint8 *)(0x40000244))\r
+#define MCF_UART1_UCR (*(vuint8 *)(0x40000248))\r
+#define MCF_UART1_URB (*(vuint8 *)(0x4000024C))\r
+#define MCF_UART1_UTB (*(vuint8 *)(0x4000024C))\r
+#define MCF_UART1_UIPCR (*(vuint8 *)(0x40000250))\r
+#define MCF_UART1_UACR (*(vuint8 *)(0x40000250))\r
+#define MCF_UART1_UIMR (*(vuint8 *)(0x40000254))\r
+#define MCF_UART1_UISR (*(vuint8 *)(0x40000254))\r
+#define MCF_UART1_UBG1 (*(vuint8 *)(0x40000258))\r
+#define MCF_UART1_UBG2 (*(vuint8 *)(0x4000025C))\r
+#define MCF_UART1_UIP (*(vuint8 *)(0x40000274))\r
+#define MCF_UART1_UOP1 (*(vuint8 *)(0x40000278))\r
+#define MCF_UART1_UOP0 (*(vuint8 *)(0x4000027C))\r
+\r
+#define MCF_UART2_UMR1 (*(vuint8 *)(0x40000280))\r
+#define MCF_UART2_UMR2 (*(vuint8 *)(0x40000280))\r
+#define MCF_UART2_USR (*(vuint8 *)(0x40000284))\r
+#define MCF_UART2_UCSR (*(vuint8 *)(0x40000284))\r
+#define MCF_UART2_UCR (*(vuint8 *)(0x40000288))\r
+#define MCF_UART2_URB (*(vuint8 *)(0x4000028C))\r
+#define MCF_UART2_UTB (*(vuint8 *)(0x4000028C))\r
+#define MCF_UART2_UIPCR (*(vuint8 *)(0x40000290))\r
+#define MCF_UART2_UACR (*(vuint8 *)(0x40000290))\r
+#define MCF_UART2_UIMR (*(vuint8 *)(0x40000294))\r
+#define MCF_UART2_UISR (*(vuint8 *)(0x40000294))\r
+#define MCF_UART2_UBG1 (*(vuint8 *)(0x40000298))\r
+#define MCF_UART2_UBG2 (*(vuint8 *)(0x4000029C))\r
+#define MCF_UART2_UIP (*(vuint8 *)(0x400002B4))\r
+#define MCF_UART2_UOP1 (*(vuint8 *)(0x400002B8))\r
+#define MCF_UART2_UOP0 (*(vuint8 *)(0x400002BC))\r
+\r
+#define MCF_UART_UMR(x) (*(vuint8 *)(0x40000200 + ((x)*0x40)))\r
+#define MCF_UART_USR(x) (*(vuint8 *)(0x40000204 + ((x)*0x40)))\r
+#define MCF_UART_UCSR(x) (*(vuint8 *)(0x40000204 + ((x)*0x40)))\r
+#define MCF_UART_UCR(x) (*(vuint8 *)(0x40000208 + ((x)*0x40)))\r
+#define MCF_UART_URB(x) (*(vuint8 *)(0x4000020C + ((x)*0x40)))\r
+#define MCF_UART_UTB(x) (*(vuint8 *)(0x4000020C + ((x)*0x40)))\r
+#define MCF_UART_UIPCR(x) (*(vuint8 *)(0x40000210 + ((x)*0x40)))\r
+#define MCF_UART_UACR(x) (*(vuint8 *)(0x40000210 + ((x)*0x40)))\r
+#define MCF_UART_UIMR(x) (*(vuint8 *)(0x40000214 + ((x)*0x40)))\r
+#define MCF_UART_UISR(x) (*(vuint8 *)(0x40000214 + ((x)*0x40)))\r
+#define MCF_UART_UBG1(x) (*(vuint8 *)(0x40000218 + ((x)*0x40)))\r
+#define MCF_UART_UBG2(x) (*(vuint8 *)(0x4000021C + ((x)*0x40)))\r
+#define MCF_UART_UIP(x) (*(vuint8 *)(0x40000234 + ((x)*0x40)))\r
+#define MCF_UART_UOP1(x) (*(vuint8 *)(0x40000238 + ((x)*0x40)))\r
+#define MCF_UART_UOP0(x) (*(vuint8 *)(0x4000023C + ((x)*0x40)))\r
+\r
+/* Bit definitions and macros for MCF_UART_UMR */\r
+#define MCF_UART_UMR_BC(x) (((x)&0x3)<<0)\r
+#define MCF_UART_UMR_BC_5 (0)\r
+#define MCF_UART_UMR_BC_6 (0x1)\r
+#define MCF_UART_UMR_BC_7 (0x2)\r
+#define MCF_UART_UMR_BC_8 (0x3)\r
+#define MCF_UART_UMR_PT (0x4)\r
+#define MCF_UART_UMR_PM(x) (((x)&0x3)<<0x3)\r
+#define MCF_UART_UMR_ERR (0x20)\r
+#define MCF_UART_UMR_RXIRQ (0x40)\r
+#define MCF_UART_UMR_RXRTS (0x80)\r
+#define MCF_UART_UMR_PM_MULTI_ADDR (0x1C)\r
+#define MCF_UART_UMR_PM_MULTI_DATA (0x18)\r
+#define MCF_UART_UMR_PM_NONE (0x10)\r
+#define MCF_UART_UMR_PM_FORCE_HI (0xC)\r
+#define MCF_UART_UMR_PM_FORCE_LO (0x8)\r
+#define MCF_UART_UMR_PM_ODD (0x4)\r
+#define MCF_UART_UMR_PM_EVEN (0)\r
+#define MCF_UART_UMR_SB(x) (((x)&0xF)<<0)\r
+#define MCF_UART_UMR_SB_STOP_BITS_1 (0x7)\r
+#define MCF_UART_UMR_SB_STOP_BITS_15 (0x8)\r
+#define MCF_UART_UMR_SB_STOP_BITS_2 (0xF)\r
+#define MCF_UART_UMR_TXCTS (0x10)\r
+#define MCF_UART_UMR_TXRTS (0x20)\r
+#define MCF_UART_UMR_CM(x) (((x)&0x3)<<0x6)\r
+#define MCF_UART_UMR_CM_NORMAL (0)\r
+#define MCF_UART_UMR_CM_ECHO (0x40)\r
+#define MCF_UART_UMR_CM_LOCAL_LOOP (0x80)\r
+#define MCF_UART_UMR_CM_REMOTE_LOOP (0xC0)\r
+\r
+/* Bit definitions and macros for MCF_UART_USR */\r
+#define MCF_UART_USR_RXRDY (0x1)\r
+#define MCF_UART_USR_FFULL (0x2)\r
+#define MCF_UART_USR_TXRDY (0x4)\r
+#define MCF_UART_USR_TXEMP (0x8)\r
+#define MCF_UART_USR_OE (0x10)\r
+#define MCF_UART_USR_PE (0x20)\r
+#define MCF_UART_USR_FE (0x40)\r
+#define MCF_UART_USR_RB (0x80)\r
+\r
+/* Bit definitions and macros for MCF_UART_UCSR */\r
+#define MCF_UART_UCSR_TCS(x) (((x)&0xF)<<0)\r
+#define MCF_UART_UCSR_TCS_SYS_CLK (0xD)\r
+#define MCF_UART_UCSR_TCS_CTM16 (0xE)\r
+#define MCF_UART_UCSR_TCS_CTM (0xF)\r
+#define MCF_UART_UCSR_RCS(x) (((x)&0xF)<<0x4)\r
+#define MCF_UART_UCSR_RCS_SYS_CLK (0xD0)\r
+#define MCF_UART_UCSR_RCS_CTM16 (0xE0)\r
+#define MCF_UART_UCSR_RCS_CTM (0xF0)\r
+\r
+/* Bit definitions and macros for MCF_UART_UCR */\r
+#define MCF_UART_UCR_RC(x) (((x)&0x3)<<0)\r
+#define MCF_UART_UCR_RX_ENABLED (0x1)\r
+#define MCF_UART_UCR_RX_DISABLED (0x2)\r
+#define MCF_UART_UCR_TC(x) (((x)&0x3)<<0x2)\r
+#define MCF_UART_UCR_TX_ENABLED (0x4)\r
+#define MCF_UART_UCR_TX_DISABLED (0x8)\r
+#define MCF_UART_UCR_MISC(x) (((x)&0x7)<<0x4)\r
+#define MCF_UART_UCR_NONE (0)\r
+#define MCF_UART_UCR_RESET_MR (0x10)\r
+#define MCF_UART_UCR_RESET_RX (0x20)\r
+#define MCF_UART_UCR_RESET_TX (0x30)\r
+#define MCF_UART_UCR_RESET_ERROR (0x40)\r
+#define MCF_UART_UCR_RESET_BKCHGINT (0x50)\r
+#define MCF_UART_UCR_START_BREAK (0x60)\r
+#define MCF_UART_UCR_STOP_BREAK (0x70)\r
+\r
+/* Bit definitions and macros for MCF_UART_URB */\r
+#define MCF_UART_URB_RB(x) (((x)&0xFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_UART_UTB */\r
+#define MCF_UART_UTB_TB(x) (((x)&0xFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_UART_UIPCR */\r
+#define MCF_UART_UIPCR_CTS (0x1)\r
+#define MCF_UART_UIPCR_COS (0x10)\r
+\r
+/* Bit definitions and macros for MCF_UART_UACR */\r
+#define MCF_UART_UACR_IEC (0x1)\r
+\r
+/* Bit definitions and macros for MCF_UART_UIMR */\r
+#define MCF_UART_UIMR_TXRDY (0x1)\r
+#define MCF_UART_UIMR_FFULL_RXRDY (0x2)\r
+#define MCF_UART_UIMR_DB (0x4)\r
+#define MCF_UART_UIMR_COS (0x80)\r
+\r
+/* Bit definitions and macros for MCF_UART_UISR */\r
+#define MCF_UART_UISR_TXRDY (0x1)\r
+#define MCF_UART_UISR_FFULL_RXRDY (0x2)\r
+#define MCF_UART_UISR_DB (0x4)\r
+#define MCF_UART_UISR_COS (0x80)\r
+\r
+/* Bit definitions and macros for MCF_UART_UBG1 */\r
+#define MCF_UART_UBG1_Divider_MSB(x) (((x)&0xFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_UART_UBG2 */\r
+#define MCF_UART_UBG2_Divider_LSB(x) (((x)&0xFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_UART_UIP */\r
+#define MCF_UART_UIP_CTS (0x1)\r
+\r
+/* Bit definitions and macros for MCF_UART_UOP1 */\r
+#define MCF_UART_UOP1_RTS (0x1)\r
+\r
+/* Bit definitions and macros for MCF_UART_UOP0 */\r
+#define MCF_UART_UOP0_RTS (0x1)\r
+\r
+\r
+#endif /* __MCF52259_UART_H__ */\r
--- /dev/null
+/* Coldfire C Header File\r
+ * Copyright Freescale Semiconductor Inc\r
+ * All rights reserved.\r
+ *\r
+ * 2008/04/17 Revision: 0.2\r
+ *\r
+ * (c) Copyright UNIS, spol. s r.o. 1997-2008\r
+ * UNIS, spol. s r.o.\r
+ * Jundrovska 33\r
+ * 624 00 Brno\r
+ * Czech Republic\r
+ * http : www.processorexpert.com\r
+ * mail : info@processorexpert.com\r
+ */\r
+\r
+#ifndef __MCF52259_USB_OTG_H__\r
+#define __MCF52259_USB_OTG_H__\r
+\r
+\r
+/*********************************************************************\r
+*\r
+* Universal Serial Bus - OTG Controller (USB_OTG)\r
+*\r
+*********************************************************************/\r
+\r
+/* Register read/write macros */\r
+#define MCF_USB_OTG_PER_ID (*(vuint8 *)(&__IPSBAR[0x1C0000]))\r
+#define MCF_USB_OTG_ID_COMP (*(vuint8 *)(&__IPSBAR[0x1C0004]))\r
+#define MCF_USB_OTG_REV (*(vuint8 *)(&__IPSBAR[0x1C0008]))\r
+#define MCF_USB_OTG_ADD_INFO (*(vuint8 *)(&__IPSBAR[0x1C000C]))\r
+#define MCF_USB_OTG_OTG_INT_STAT (*(vuint8 *)(&__IPSBAR[0x1C0010]))\r
+#define MCF_USB_OTG_OTG_INT_EN (*(vuint8 *)(&__IPSBAR[0x1C0014]))\r
+#define MCF_USB_OTG_OTG_STAT (*(vuint8 *)(&__IPSBAR[0x1C0018]))\r
+#define MCF_USB_OTG_OTG_CTRL (*(vuint8 *)(&__IPSBAR[0x1C001C]))\r
+#define MCF_USB_OTG_INT_STAT (*(vuint8 *)(&__IPSBAR[0x1C0080]))\r
+#define MCF_USB_OTG_INT_ENB (*(vuint8 *)(&__IPSBAR[0x1C0084]))\r
+#define MCF_USB_OTG_ERR_STAT (*(vuint8 *)(&__IPSBAR[0x1C0088]))\r
+#define MCF_USB_OTG_ERR_ENB (*(vuint8 *)(&__IPSBAR[0x1C008C]))\r
+#define MCF_USB_OTG_STAT (*(vuint8 *)(&__IPSBAR[0x1C0090]))\r
+#define MCF_USB_OTG_CTL (*(vuint8 *)(&__IPSBAR[0x1C0094]))\r
+#define MCF_USB_OTG_ADDR (*(vuint8 *)(&__IPSBAR[0x1C0098]))\r
+#define MCF_USB_OTG_BDT_PAGE_01 (*(vuint8 *)(&__IPSBAR[0x1C009C]))\r
+#define MCF_USB_OTG_FRM_NUML (*(vuint8 *)(&__IPSBAR[0x1C00A0]))\r
+#define MCF_USB_OTG_FRM_NUMH (*(vuint8 *)(&__IPSBAR[0x1C00A4]))\r
+#define MCF_USB_OTG_TOKEN (*(vuint8 *)(&__IPSBAR[0x1C00A8]))\r
+#define MCF_USB_OTG_SOF_THLD (*(vuint8 *)(&__IPSBAR[0x1C00AC]))\r
+#define MCF_USB_OTG_BDT_PAGE_02 (*(vuint8 *)(&__IPSBAR[0x1C00B0]))\r
+#define MCF_USB_OTG_BDT_PAGE_03 (*(vuint8 *)(&__IPSBAR[0x1C00B4]))\r
+#define MCF_USB_OTG_ENDPT0 (*(vuint8 *)(&__IPSBAR[0x1C00C0]))\r
+#define MCF_USB_OTG_ENDPT1 (*(vuint8 *)(&__IPSBAR[0x1C00C4]))\r
+#define MCF_USB_OTG_ENDPT2 (*(vuint8 *)(&__IPSBAR[0x1C00C8]))\r
+#define MCF_USB_OTG_ENDPT3 (*(vuint8 *)(&__IPSBAR[0x1C00CC]))\r
+#define MCF_USB_OTG_ENDPT4 (*(vuint8 *)(&__IPSBAR[0x1C00D0]))\r
+#define MCF_USB_OTG_ENDPT5 (*(vuint8 *)(&__IPSBAR[0x1C00D4]))\r
+#define MCF_USB_OTG_ENDPT6 (*(vuint8 *)(&__IPSBAR[0x1C00D8]))\r
+#define MCF_USB_OTG_ENDPT7 (*(vuint8 *)(&__IPSBAR[0x1C00DC]))\r
+#define MCF_USB_OTG_ENDPT8 (*(vuint8 *)(&__IPSBAR[0x1C00E0]))\r
+#define MCF_USB_OTG_ENDPT9 (*(vuint8 *)(&__IPSBAR[0x1C00E4]))\r
+#define MCF_USB_OTG_ENDPT10 (*(vuint8 *)(&__IPSBAR[0x1C00E8]))\r
+#define MCF_USB_OTG_ENDPT11 (*(vuint8 *)(&__IPSBAR[0x1C00EC]))\r
+#define MCF_USB_OTG_ENDPT12 (*(vuint8 *)(&__IPSBAR[0x1C00F0]))\r
+#define MCF_USB_OTG_ENDPT13 (*(vuint8 *)(&__IPSBAR[0x1C00F4]))\r
+#define MCF_USB_OTG_ENDPT14 (*(vuint8 *)(&__IPSBAR[0x1C00F8]))\r
+#define MCF_USB_OTG_ENDPT15 (*(vuint8 *)(&__IPSBAR[0x1C00FC]))\r
+#define MCF_USB_OTG_USB_CTRL (*(vuint8 *)(&__IPSBAR[0x1C0100]))\r
+#define MCF_USB_OTG_USB_OTG_OBSERVE (*(vuint8 *)(&__IPSBAR[0x1C0104]))\r
+#define MCF_USB_OTG_USB_OTG_CONTROL (*(vuint8 *)(&__IPSBAR[0x1C0108]))\r
+#define MCF_USB_OTG_ENDPT(x) (*(vuint8 *)(&__IPSBAR[0x1C00C0 + ((x)*0x4)]))\r
+\r
+/* Other macros */\r
+#define MCF_USB_OTG_FRM_NUM (MCF_USB_OTG_INT_STAT=MCF_USB_OTG_INT_STAT_SOF_TOK ,MCF_USB_OTG_FRM_NUML | (((vuint16)MCF_USB_OTG_FRM_NUMH)<<8))\r
+\r
+\r
+/* Bit definitions and macros for MCF_USB_OTG_PER_ID */\r
+#define MCF_USB_OTG_PER_ID_ID(x) (((x)&0x3F)<<0)\r
+\r
+/* Bit definitions and macros for MCF_USB_OTG_ID_COMP */\r
+#define MCF_USB_OTG_ID_COMP_NID(x) (((x)&0x3F)<<0)\r
+\r
+/* Bit definitions and macros for MCF_USB_OTG_REV */\r
+#define MCF_USB_OTG_REV_REV(x) (((x)&0xFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_USB_OTG_ADD_INFO */\r
+#define MCF_USB_OTG_ADD_INFO_IEHOST (0x1)\r
+#define MCF_USB_OTG_ADD_INFO_IRQ_NUM(x) (((x)&0x1F)<<0x3)\r
+\r
+/* Bit definitions and macros for MCF_USB_OTG_OTG_INT_STAT */\r
+#define MCF_USB_OTG_OTG_INT_STAT_A_VBUS_CHG (0x1)\r
+#define MCF_USB_OTG_OTG_INT_STAT_B_SESS_CHG (0x4)\r
+#define MCF_USB_OTG_OTG_INT_STAT_SESS_VLD_CHG (0x8)\r
+#define MCF_USB_OTG_OTG_INT_STAT_LINE_STATE_CHG (0x20)\r
+#define MCF_USB_OTG_OTG_INT_STAT_1_MSEC (0x40)\r
+#define MCF_USB_OTG_OTG_INT_STAT_ID_CHG (0x80)\r
+\r
+/* Bit definitions and macros for MCF_USB_OTG_OTG_INT_EN */\r
+#define MCF_USB_OTG_OTG_INT_EN_A_VBUS_EN (0x1)\r
+#define MCF_USB_OTG_OTG_INT_EN_B_SESS_EN (0x4)\r
+#define MCF_USB_OTG_OTG_INT_EN_SESS_VLD_EN (0x8)\r
+#define MCF_USB_OTG_OTG_INT_EN_LINE_STATE_EN (0x20)\r
+#define MCF_USB_OTG_OTG_INT_EN_1_MSEC_EN (0x40)\r
+#define MCF_USB_OTG_OTG_INT_EN_ID_EN (0x80)\r
+\r
+/* Bit definitions and macros for MCF_USB_OTG_OTG_STAT */\r
+#define MCF_USB_OTG_OTG_STAT_A_VBUS_VLD (0x1)\r
+#define MCF_USB_OTG_OTG_STAT_B_SESS_END (0x4)\r
+#define MCF_USB_OTG_OTG_STAT_SESS_VLD (0x8)\r
+#define MCF_USB_OTG_OTG_STAT_LINE_STATE_STABLE (0x20)\r
+#define MCF_USB_OTG_OTG_STAT_1_MSEC_EN (0x40)\r
+#define MCF_USB_OTG_OTG_STAT_ID (0x80)\r
+\r
+/* Bit definitions and macros for MCF_USB_OTG_OTG_CTRL */\r
+#define MCF_USB_OTG_OTG_CTRL_VBUS_DSCHG (0x1)\r
+#define MCF_USB_OTG_OTG_CTRL_VBUS_CHG (0x2)\r
+#define MCF_USB_OTG_OTG_CTRL_OTG_EN (0x4)\r
+#define MCF_USB_OTG_OTG_CTRL_VBUS_ON (0x8)\r
+#define MCF_USB_OTG_OTG_CTRL_DM_LOW (0x10)\r
+#define MCF_USB_OTG_OTG_CTRL_DP_LOW (0x20)\r
+#define MCF_USB_OTG_OTG_CTRL_DP_HIGH (0x80)\r
+\r
+/* Bit definitions and macros for MCF_USB_OTG_INT_STAT */\r
+#define MCF_USB_OTG_INT_STAT_USB_RST (0x1)\r
+#define MCF_USB_OTG_INT_STAT_ERROR (0x2)\r
+#define MCF_USB_OTG_INT_STAT_SOF_TOK (0x4)\r
+#define MCF_USB_OTG_INT_STAT_TOK_DNE (0x8)\r
+#define MCF_USB_OTG_INT_STAT_SLEEP (0x10)\r
+#define MCF_USB_OTG_INT_STAT_RESUME (0x20)\r
+#define MCF_USB_OTG_INT_STAT_ATTACH (0x40)\r
+#define MCF_USB_OTG_INT_STAT_STALL (0x80)\r
+\r
+/* Bit definitions and macros for MCF_USB_OTG_INT_ENB */\r
+#define MCF_USB_OTG_INT_ENB_USB_RST_EN (0x1)\r
+#define MCF_USB_OTG_INT_ENB_ERROR_EN (0x2)\r
+#define MCF_USB_OTG_INT_ENB_SOF_TOK_EN (0x4)\r
+#define MCF_USB_OTG_INT_ENB_TOK_DNE_EN (0x8)\r
+#define MCF_USB_OTG_INT_ENB_SLEEP_EN (0x10)\r
+#define MCF_USB_OTG_INT_ENB_RESUME_EN (0x20)\r
+#define MCF_USB_OTG_INT_ENB_ATTACH_EN (0x40)\r
+#define MCF_USB_OTG_INT_ENB_STALL_EN (0x80)\r
+\r
+/* Bit definitions and macros for MCF_USB_OTG_ERR_STAT */\r
+#define MCF_USB_OTG_ERR_STAT_PID_ERR (0x1)\r
+#define MCF_USB_OTG_ERR_STAT_CRC5_EOF (0x2)\r
+#define MCF_USB_OTG_ERR_STAT_CRC16 (0x4)\r
+#define MCF_USB_OTG_ERR_STAT_DFN8 (0x8)\r
+#define MCF_USB_OTG_ERR_STAT_BTO_ERR (0x10)\r
+#define MCF_USB_OTG_ERR_STAT_DMA_ERR (0x20)\r
+#define MCF_USB_OTG_ERR_STAT_BTS_ERR (0x80)\r
+\r
+/* Bit definitions and macros for MCF_USB_OTG_ERR_ENB */\r
+#define MCF_USB_OTG_ERR_ENB_PID_ERR_EN (0x1)\r
+#define MCF_USB_OTG_ERR_ENB_CRC5_EOF_EN (0x2)\r
+#define MCF_USB_OTG_ERR_ENB_CRC16_EN (0x4)\r
+#define MCF_USB_OTG_ERR_ENB_DFN8_EN (0x8)\r
+#define MCF_USB_OTG_ERR_ENB_BTO_ERR_EN (0x10)\r
+#define MCF_USB_OTG_ERR_ENB_DMA_ERR_EN (0x20)\r
+#define MCF_USB_OTG_ERR_ENB_BTS_ERR_EN (0x80)\r
+\r
+/* Bit definitions and macros for MCF_USB_OTG_STAT */\r
+#define MCF_USB_OTG_STAT_ODD (0x4)\r
+#define MCF_USB_OTG_STAT_TX (0x8)\r
+#define MCF_USB_OTG_STAT_ENDP(x) (((x)&0xF)<<0x4)\r
+\r
+/* Bit definitions and macros for MCF_USB_OTG_CTL */\r
+#define MCF_USB_OTG_CTL_USB_EN_SOF_EN (0x1)\r
+#define MCF_USB_OTG_CTL_ODD_RST (0x2)\r
+#define MCF_USB_OTG_CTL_RESUME (0x4)\r
+#define MCF_USB_OTG_CTL_HOST_MODE_EN (0x8)\r
+#define MCF_USB_OTG_CTL_RESET (0x10)\r
+#define MCF_USB_OTG_CTL_TXSUSPEND_TOKENBUSY (0x20)\r
+#define MCF_USB_OTG_CTL_SE0 (0x40)\r
+#define MCF_USB_OTG_CTL_JSTATE (0x80)\r
+\r
+/* Bit definitions and macros for MCF_USB_OTG_ADDR */\r
+#define MCF_USB_OTG_ADDR_ADDR(x) (((x)&0x7F)<<0)\r
+#define MCF_USB_OTG_ADDR_LS_EN (0x80)\r
+\r
+/* Bit definitions and macros for MCF_USB_OTG_BDT_PAGE_01 */\r
+#define MCF_USB_OTG_BDT_PAGE_01_BDT_BA9 (0x2)\r
+#define MCF_USB_OTG_BDT_PAGE_01_BDT_BA10 (0x4)\r
+#define MCF_USB_OTG_BDT_PAGE_01_BDT_BA11 (0x8)\r
+#define MCF_USB_OTG_BDT_PAGE_01_BDT_BA12 (0x10)\r
+#define MCF_USB_OTG_BDT_PAGE_01_BDT_BA13 (0x20)\r
+#define MCF_USB_OTG_BDT_PAGE_01_BDT_BA14 (0x40)\r
+#define MCF_USB_OTG_BDT_PAGE_01_BDT_BA15 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_USB_OTG_FRM_NUML */\r
+#define MCF_USB_OTG_FRM_NUML_FRM0 (0x1)\r
+#define MCF_USB_OTG_FRM_NUML_FRM1 (0x2)\r
+#define MCF_USB_OTG_FRM_NUML_FRM2 (0x4)\r
+#define MCF_USB_OTG_FRM_NUML_FRM3 (0x8)\r
+#define MCF_USB_OTG_FRM_NUML_FRM4 (0x10)\r
+#define MCF_USB_OTG_FRM_NUML_FRM5 (0x20)\r
+#define MCF_USB_OTG_FRM_NUML_FRM6 (0x40)\r
+#define MCF_USB_OTG_FRM_NUML_FRM7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_USB_OTG_FRM_NUMH */\r
+#define MCF_USB_OTG_FRM_NUMH_FRM8 (0x1)\r
+#define MCF_USB_OTG_FRM_NUMH_FRM9 (0x2)\r
+#define MCF_USB_OTG_FRM_NUMH_FRM10 (0x4)\r
+\r
+/* Bit definitions and macros for MCF_USB_OTG_TOKEN */\r
+#define MCF_USB_OTG_TOKEN_TOKEN_ENDPT(x) (((x)&0xF)<<0)\r
+#define MCF_USB_OTG_TOKEN_TOKEN_PID(x) (((x)&0xF)<<0x4)\r
+#define MCF_USB_OTG_TOKEN_TOKEN_PID_OUT (0x10)\r
+#define MCF_USB_OTG_TOKEN_TOKEN_PID_IN (0x90)\r
+#define MCF_USB_OTG_TOKEN_TOKEN_PID_SETUP (0xD0)\r
+\r
+/* Bit definitions and macros for MCF_USB_OTG_SOF_THLD */\r
+#define MCF_USB_OTG_SOF_THLD_CNT0 (0x1)\r
+#define MCF_USB_OTG_SOF_THLD_CNT1 (0x2)\r
+#define MCF_USB_OTG_SOF_THLD_CNT2 (0x4)\r
+#define MCF_USB_OTG_SOF_THLD_CNT3 (0x8)\r
+#define MCF_USB_OTG_SOF_THLD_CNT4 (0x10)\r
+#define MCF_USB_OTG_SOF_THLD_CNT5 (0x20)\r
+#define MCF_USB_OTG_SOF_THLD_CNT6 (0x40)\r
+#define MCF_USB_OTG_SOF_THLD_CNT7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_USB_OTG_BDT_PAGE_02 */\r
+#define MCF_USB_OTG_BDT_PAGE_02_BDT_BA16 (0x1)\r
+#define MCF_USB_OTG_BDT_PAGE_02_BDT_BA17 (0x2)\r
+#define MCF_USB_OTG_BDT_PAGE_02_BDT_BA18 (0x4)\r
+#define MCF_USB_OTG_BDT_PAGE_02_BDT_BA19 (0x8)\r
+#define MCF_USB_OTG_BDT_PAGE_02_BDT_BA20 (0x10)\r
+#define MCF_USB_OTG_BDT_PAGE_02_BDT_BA21 (0x20)\r
+#define MCF_USB_OTG_BDT_PAGE_02_BDT_BA22 (0x40)\r
+#define MCF_USB_OTG_BDT_PAGE_02_BDT_BA23 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_USB_OTG_BDT_PAGE_03 */\r
+#define MCF_USB_OTG_BDT_PAGE_03_BDT_BA24 (0x1)\r
+#define MCF_USB_OTG_BDT_PAGE_03_BDT_BA25 (0x2)\r
+#define MCF_USB_OTG_BDT_PAGE_03_BDT_BA26 (0x4)\r
+#define MCF_USB_OTG_BDT_PAGE_03_BDT_BA27 (0x8)\r
+#define MCF_USB_OTG_BDT_PAGE_03_BDT_BA28 (0x10)\r
+#define MCF_USB_OTG_BDT_PAGE_03_BDT_BA29 (0x20)\r
+#define MCF_USB_OTG_BDT_PAGE_03_BDT_BA30 (0x40)\r
+#define MCF_USB_OTG_BDT_PAGE_03_BDT_BA31 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_USB_OTG_ENDPT */\r
+#define MCF_USB_OTG_ENDPT_EP_HSHK (0x1)\r
+#define MCF_USB_OTG_ENDPT_EP_STALL (0x2)\r
+#define MCF_USB_OTG_ENDPT_EP_TX_EN (0x4)\r
+#define MCF_USB_OTG_ENDPT_EP_RX_EN (0x8)\r
+#define MCF_USB_OTG_ENDPT_EP_CTL_DIS (0x10)\r
+#define MCF_USB_OTG_ENDPT_RETRY_DIS (0x40)\r
+#define MCF_USB_OTG_ENDPT_HOST_WO_HUB (0x80)\r
+\r
+/* Bit definitions and macros for MCF_USB_OTG_USB_CTRL */\r
+#define MCF_USB_OTG_USB_CTRL_CLK_SRC(x) (((x)&0x3)<<0)\r
+#define MCF_USB_OTG_USB_CTRL_CLK_SRC_ALTCLK (0)\r
+#define MCF_USB_OTG_USB_CTRL_CLK_SRC_OSCCLK (0x1)\r
+#define MCF_USB_OTG_USB_CTRL_CLK_SRC_SYSCLK (0x3)\r
+#define MCF_USB_OTG_USB_CTRL_PDE (0x40)\r
+#define MCF_USB_OTG_USB_CTRL_SUSP (0x80)\r
+\r
+/* Bit definitions and macros for MCF_USB_OTG_USB_OTG_OBSERVE */\r
+#define MCF_USB_OTG_USB_OTG_OBSERVE_DM_PD (0x10)\r
+#define MCF_USB_OTG_USB_OTG_OBSERVE_DP_PD (0x40)\r
+#define MCF_USB_OTG_USB_OTG_OBSERVE_DP_PU (0x80)\r
+\r
+/* Bit definitions and macros for MCF_USB_OTG_USB_OTG_CONTROL */\r
+#define MCF_USB_OTG_USB_OTG_CONTROL_SESSEND (0x1)\r
+#define MCF_USB_OTG_USB_OTG_CONTROL_SESSVLD (0x2)\r
+#define MCF_USB_OTG_USB_OTG_CONTROL_VBUSVLD (0x4)\r
+#define MCF_USB_OTG_USB_OTG_CONTROL_ID (0x8)\r
+#define MCF_USB_OTG_USB_OTG_CONTROL_DPPULLUP_NONOTG (0x10)\r
+\r
+\r
+#endif /* __MCF52259_USB_OTG_H__ */\r
--- /dev/null
+/*\r
+ * File: common.h\r
+ * Purpose: File to be included by all project files\r
+ *\r
+ * Notes:\r
+ * \r
+ * License: All software covered by license agreement in -\r
+ * docs/Freescale_Software_License.pdf\r
+ */\r
+\r
+#ifndef _COMMON_H_\r
+#define _COMMON_H_\r
+\r
+/********************************************************************/\r
+\r
+/*\r
+ * Debug prints ON (#define) or OFF (#undef)\r
+ */\r
+#undef DEBUG_PRINT \r
+#undef DEBUG_PRINT_D0D1 \r
+\r
+/* \r
+ * Include the generic CPU header file \r
+ */\r
+#include "mcf5xxx.h"\r
+\r
+/* \r
+ * Include the specific CPU header file \r
+ */\r
+#include "mcf5225x.h"\r
+\r
+#include "mcf5225x_evb.h"\r
+\r
+/* \r
+ * MetroWerks looks for an underscore prepended to C function names \r
+ */\r
+#define _UNDERSCORE_\r
+\r
+/* \r
+ * The source uses __interrupt__ to identify a function as\r
+ * an interrupt or exception handler. Codewarrior uses \r
+ * __declspec(interrupt), so we are appeasing it like this.\r
+ */\r
+#define __interrupt__ __declspec(interrupt)\r
+\r
+/* \r
+ * Force functions to return values in D0 \r
+ */\r
+#pragma pointers_in_D0\r
+\r
+/* \r
+ * Provide a few assembly instructions for C level routines\r
+ */\r
+#define halt() asm( halt)\r
+#define nop() asm( nop)\r
+#define tpf() asm( tpf)\r
+#define stop_2700() asm( stop #0x2700)\r
+#define stop_2600() asm( stop #0x2600)\r
+#define stop_2500() asm( stop #0x2500)\r
+#define stop_2400() asm( stop #0x2400)\r
+#define stop_2300() asm( stop #0x2300)\r
+#define stop_2200() asm( stop #0x2200)\r
+#define stop_2100() asm( stop #0x2100)\r
+#define stop_2000() asm( stop #0x2000)\r
+\r
+/* \r
+ * Define custom sections for relocating code, data, and constants \r
+ */\r
+#pragma define_section relocate_code ".relocate_code" far_absolute RX\r
+#pragma define_section relocate_data ".relocate_data" far_absolute RW\r
+#pragma define_section relocate_const ".relocate_const" far_absolute R\r
+#define __relocate_code__ __declspec(relocate_code)\r
+#define __relocate_data__ __declspec(relocate_data)\r
+#define __relocate_const__ __declspec(relocate_const)\r
+ \r
+/* \r
+ * Include common utilities\r
+ */\r
+void assert_failed(char *, int);\r
+\r
+#ifdef DEBUG_PRINT\r
+#define ASSERT(expr) \\r
+ if (!(expr)) \\r
+ assert_failed(__FILE__, __LINE__)\r
+#else\r
+#define ASSERT(expr)\r
+#endif\r
+ \r
+//#include "assert.h"\r
+//#include "io.h"\r
+//#include "stdlib.h"\r
+\r
+\r
+/********************************************************************/\r
+\r
+#endif /* _COMMON_H_ */\r
--- /dev/null
+/*\r
+ * File: mcf5225x.h\r
+ * Purpose: Register and bit definitions\r
+ *\r
+ * License: All software covered by license agreement in -\r
+ * docs/Freescale_Software_License.pdf\r
+ */\r
+\r
+#ifndef __MCF5225x_H__\r
+#define __MCF5225x_H__\r
+\r
+/********************************************************************/\r
+/*\r
+ * 5225x includes\r
+ */\r
+\r
+#include "MCF52259_SCM.h"\r
+#include "MCF52259_FBCS.h"\r
+#include "MCF52259_DMA.h"\r
+#include "MCF52259_UART.h"\r
+#include "MCF52259_I2C.h"\r
+#include "MCF52259_QSPI.h"\r
+#include "MCF52259_DTIM.h"\r
+#include "MCF52259_INTC.h"\r
+#include "MCF52259_FEC.h"\r
+#include "MCF52259_GPIO.h"\r
+#include "MCF52259_PAD.h"\r
+#include "MCF52259_RCM.h"\r
+#include "MCF52259_CCM.h"\r
+#include "MCF52259_PMM.h"\r
+#include "MCF52259_CLOCK.h"\r
+#include "MCF52259_EPORT.h"\r
+#include "MCF52259_BWT.h"\r
+#include "MCF52259_PIT.h"\r
+#include "MCF52259_FlexCAN.h"\r
+#include "MCF52259_CANMB.h"\r
+#include "MCF52259_RTC.h"\r
+#include "MCF52259_ADC.h"\r
+#include "MCF52259_GPT.h"\r
+#include "MCF52259_PWM.h"\r
+#include "MCF52259_USB_OTG.h"\r
+#include "MCF52259_CFM.h"\r
+#include "MCF52259_RNGA.h"\r
+\r
+\r
+/********************************************************************/\r
+\r
+#endif /* __MCF5225x_H__ */\r
--- /dev/null
+/*\r
+ * File: m5225x_evb.h\r
+ * Purpose: Evaluation board definitions and memory map information\r
+ *\r
+ * Notes:\r
+ * \r
+ * License: All software covered by license agreement in -\r
+ * docs/Freescale_Software_License.pdf\r
+ */\r
+\r
+#ifndef _M5225xEVB_H\r
+#define _M5225xEVB_H\r
+\r
+#define COLDFIRE_MAC_ADDRESS {0x00, 0x04, 0x9f, 0x00, 0xab, 0x2b}\r
+\r
+/********************************************************************/\r
+\r
+//#include "mcf5xxx.h"\r
+\r
+/********************************************************************/\r
+#define LED0_TOGGLE MCF_GPIO_PORTTC = (uint8)(MCF_GPIO_PORTTC ^ MCF_GPIO_PORTTC_PORTTC0)\r
+\r
+/*\r
+ * Debug prints ON (#undef) or OFF (#define)\r
+ */\r
+#undef DEBUG\r
+\r
+/* \r
+ * System Bus Clock Info \r
+ */\r
+ \r
+ \r
+#define SYSTEM_CLOCK 80 /* system bus frequency in MHz */\r
+//#define PERIOD 12.5 /* system bus period in ns */\r
+#define TERMINAL_BAUD 19200\r
+#define UART_BAUD TERMINAL_BAUD /* 19200*/\r
+\r
+#define TERMINAL_PORT 0\r
+#define REF_CLK_MHZ 48\r
+#define SYS_CLK_MHZ SYSTEM_CLOCK\r
+#define REF_CLK_KHZ (REF_CLK_MHZ * 1000)\r
+#define SYS_CLK_KHZ (SYS_CLK_MHZ * 1000)\r
+\r
+/* \r
+ * Memory map definitions from linker command files \r
+ */\r
+\r
+extern uint8 __IPSBAR[];\r
+extern uint8 __SRAM[];\r
+extern uint8 __FLASH[]; \r
+extern uint8 __SRAM_SIZE[];\r
+extern uint8 __FLASH_SIZE[];\r
+extern uint8 __DATA_ROM[];\r
+extern uint8 __DATA_RAM[];\r
+extern uint8 __DATA_END[];\r
+extern uint8 __BSS_START[];\r
+extern uint8 __BSS_END[];\r
+extern uint32 VECTOR_TABLE[];\r
+extern uint32 __VECTOR_RAM[];\r
+\r
+\r
+/* \r
+ * Memory Map Info \r
+ */\r
+#define IPSBAR_ADDRESS (uint32)__IPSBAR\r
+\r
+#define SRAM_ADDRESS (uint32)__SRAM\r
+#define SRAM_SIZE (uint32)__SRAM_SIZE\r
+\r
+#define FLASH_ADDRESS (uint32)__FLASH\r
+#define FLASH_SIZE (uint32)__FLASH_SIZE\r
+\r
+/*\r
+ * Interrupt Controller Definitions\r
+ */\r
+#define TIMER_NETWORK_LEVEL 3\r
+#define USB_NETWORK_LEVEL 1\r
+\r
+/*\r
+ * Timer period info\r
+ */\r
+ \r
+ /* 1 sec / max timeout */\r
+#define TIMER_NETWORK_PERIOD 1000000000/0x10000 \r
+\r
+/*\r
+ * Board specific function prototypes\r
+ */\r
+\r
+void leds_init();\r
+void board_led_display(uint8 number);\r
+\r
+/********************************************************************/\r
+\r
+#endif /* _M5225xEVB_H */\r
--- /dev/null
+/*\r
+ * File: mcf5xxx.h\r
+ * Purpose: Definitions common to all ColdFire processors\r
+ *\r
+ * Notes:\r
+ * \r
+ * License: All software covered by license agreement in -\r
+ * docs/Freescale_Software_License.pdf\r
+ */\r
+\r
+#ifndef _CPU_MCF5XXX_H\r
+#define _CPU_MCF5XXX_H\r
+\r
+/***********************************************************************/\r
+/*\r
+ * Misc. Defines\r
+ */\r
+#ifdef FALSE\r
+#undef FALSE\r
+#endif\r
+#define FALSE (0)\r
+\r
+#ifdef TRUE\r
+#undef TRUE\r
+#endif\r
+#define TRUE (1)\r
+\r
+#ifdef NULL\r
+#undef NULL\r
+#endif\r
+#define NULL (0)\r
+\r
+#ifdef ON\r
+#undef ON\r
+#endif\r
+#define ON (1)\r
+\r
+#ifdef OFF\r
+#undef OFF\r
+#endif\r
+#define OFF (0)\r
+\r
+/***********************************************************************/\r
+/*\r
+ * The basic data types\r
+ */\r
+typedef unsigned char uint8; /* 8 bits */\r
+typedef unsigned short int uint16; /* 16 bits */\r
+typedef unsigned long int uint32; /* 32 bits */\r
+\r
+typedef char int8; /* 8 bits */\r
+typedef short int int16; /* 16 bits */\r
+typedef int int32; /* 32 bits */\r
+\r
+typedef volatile int8 vint8; /* 8 bits */\r
+typedef volatile int16 vint16; /* 16 bits */\r
+typedef volatile int32 vint32; /* 32 bits */\r
+\r
+typedef volatile uint8 vuint8; /* 8 bits */\r
+typedef volatile uint16 vuint16; /* 16 bits */\r
+typedef volatile uint32 vuint32; /* 32 bits */\r
+\r
+/***********************************************************************/\r
+/*\r
+ * Common M68K & ColdFire definitions\r
+ */\r
+#define ADDRESS uint32\r
+#define INSTRUCTION uint16\r
+#define ILLEGAL 0x4AFC\r
+#define CPU_WORD_SIZE 16\r
+\r
+/* Status Register */\r
+#define MCF5XXX_SR_T (0x8000)\r
+#define MCF5XXX_SR_S (0x2000)\r
+#define MCF5XXX_SR_M (0x1000)\r
+#define MCF5XXX_SR_IPL (0x0700)\r
+#define MCF5XXX_SR_IPL_0 (0x0000)\r
+#define MCF5XXX_SR_IPL_1 (0x0100)\r
+#define MCF5XXX_SR_IPL_2 (0x0200)\r
+#define MCF5XXX_SR_IPL_3 (0x0300)\r
+#define MCF5XXX_SR_IPL_4 (0x0400)\r
+#define MCF5XXX_SR_IPL_5 (0x0500)\r
+#define MCF5XXX_SR_IPL_6 (0x0600)\r
+#define MCF5XXX_SR_IPL_7 (0x0700)\r
+#define MCF5XXX_SR_X (0x0010)\r
+#define MCF5XXX_SR_N (0x0008)\r
+#define MCF5XXX_SR_Z (0x0004)\r
+#define MCF5XXX_SR_V (0x0002)\r
+#define MCF5XXX_SR_C (0x0001)\r
+\r
+/* Cache Control Register */\r
+#define MCF5XXX_CACR_CENB (0x80000000)\r
+#define MCF5XXX_CACR_DEC (0x80000000)\r
+#define MCF5XXX_CACR_DW (0x40000000)\r
+#define MCF5XXX_CACR_DESB (0x20000000)\r
+#define MCF5XXX_CACR_CPDI (0x10000000)\r
+#define MCF5XXX_CACR_DDPI (0x10000000)\r
+#define MCF5XXX_CACR_CPD (0x10000000)\r
+#define MCF5XXX_CACR_CFRZ (0x08000000)\r
+#define MCF5XXX_CACR_DHLCK (0x08000000)\r
+#define MCF5XXX_CACR_DDCM_WT (0x00000000)\r
+#define MCF5XXX_CACR_DDCM_CB (0x02000000)\r
+#define MCF5XXX_CACR_DDCM_IP (0x04000000)\r
+#define MCF5XXX_CACR_DDCM_II (0x06000000)\r
+#define MCF5XXX_CACR_CINV (0x01000000)\r
+#define MCF5XXX_CACR_DCINVA (0x01000000)\r
+#define MCF5XXX_CACR_DIDI (0x00800000)\r
+#define MCF5XXX_CACR_DDSP (0x00800000)\r
+#define MCF5XXX_CACR_DISD (0x00400000)\r
+#define MCF5XXX_CACR_INVI (0x00200000)\r
+#define MCF5XXX_CACR_INVD (0x00100000)\r
+#define MCF5XXX_CACR_BEC (0x00080000)\r
+#define MCF5XXX_CACR_BCINVA (0x00040000)\r
+#define MCF5XXX_CACR_IEC (0x00008000)\r
+#define MCF5XXX_CACR_DNFB (0x00002000)\r
+#define MCF5XXX_CACR_IDPI (0x00001000)\r
+#define MCF5XXX_CACR_IHLCK (0x00000800)\r
+#define MCF5XXX_CACR_CEIB (0x00000400)\r
+#define MCF5XXX_CACR_IDCM (0x00000400)\r
+#define MCF5XXX_CACR_DCM_WR (0x00000000)\r
+#define MCF5XXX_CACR_DCM_CB (0x00000100)\r
+#define MCF5XXX_CACR_DCM_IP (0x00000200)\r
+#define MCF5XXX_CACR_DCM (0x00000200)\r
+#define MCF5XXX_CACR_DCM_II (0x00000300)\r
+#define MCF5XXX_CACR_DBWE (0x00000100)\r
+#define MCF5XXX_CACR_ICINVA (0x00000100)\r
+#define MCF5XXX_CACR_IDSP (0x00000080)\r
+#define MCF5XXX_CACR_DWP (0x00000020)\r
+#define MCF5XXX_CACR_EUSP (0x00000020)\r
+#define MCF5XXX_CACR_EUST (0x00000020)\r
+#define MCF5XXX_CACR_DF (0x00000010)\r
+#define MCF5XXX_CACR_CLNF_00 (0x00000000)\r
+#define MCF5XXX_CACR_CLNF_01 (0x00000002)\r
+#define MCF5XXX_CACR_CLNF_10 (0x00000004)\r
+#define MCF5XXX_CACR_CLNF_11 (0x00000006)\r
+\r
+/* Access Control Register */\r
+#define MCF5XXX_ACR_AB(a) ((a)&0xFF000000)\r
+#define MCF5XXX_ACR_AM(a) (((a)&0xFF000000) >> 8)\r
+#define MCF5XXX_ACR_AM_4G (0x00FF0000)\r
+#define MCF5XXX_ACR_AM_2G (0x007F0000)\r
+#define MCF5XXX_ACR_AM_1G (0x003F0000)\r
+#define MCF5XXX_ACR_AM_1024M (0x003F0000)\r
+#define MCF5XXX_ACR_AM_512M (0x001F0000)\r
+#define MCF5XXX_ACR_AM_256M (0x000F0000)\r
+#define MCF5XXX_ACR_AM_128M (0x00070000)\r
+#define MCF5XXX_ACR_AM_64M (0x00030000)\r
+#define MCF5XXX_ACR_AM_32M (0x00010000)\r
+#define MCF5XXX_ACR_AM_16M (0x00000000)\r
+#define MCF5XXX_ACR_EN (0x00008000)\r
+#define MCF5XXX_ACR_SM_USER (0x00000000)\r
+#define MCF5XXX_ACR_SM_SUPER (0x00002000)\r
+#define MCF5XXX_ACR_SM_IGNORE (0x00006000)\r
+#define MCF5XXX_ACR_ENIB (0x00000080)\r
+#define MCF5XXX_ACR_CM (0x00000040)\r
+#define MCF5XXX_ACR_DCM_WR (0x00000000)\r
+#define MCF5XXX_ACR_DCM_CB (0x00000020)\r
+#define MCF5XXX_ACR_DCM_IP (0x00000040)\r
+#define MCF5XXX_ACR_DCM_II (0x00000060)\r
+#define MCF5XXX_ACR_CM (0x00000040)\r
+#define MCF5XXX_ACR_BWE (0x00000020)\r
+#define MCF5XXX_ACR_WP (0x00000004)\r
+\r
+/* RAM Base Address Register */\r
+#define MCF5XXX_RAMBAR_BA(a) ((a)&0xFFFFC000)\r
+#define MCF5XXX_RAMBAR_PRI_00 (0x00000000)\r
+#define MCF5XXX_RAMBAR_PRI_01 (0x00004000)\r
+#define MCF5XXX_RAMBAR_PRI_10 (0x00008000)\r
+#define MCF5XXX_RAMBAR_PRI_11 (0x0000C000)\r
+#define MCF5XXX_RAMBAR_WP (0x00000100)\r
+#define MCF5XXX_RAMBAR_CI (0x00000020)\r
+#define MCF5XXX_RAMBAR_SC (0x00000010)\r
+#define MCF5XXX_RAMBAR_SD (0x00000008)\r
+#define MCF5XXX_RAMBAR_UC (0x00000004)\r
+#define MCF5XXX_RAMBAR_UD (0x00000002)\r
+#define MCF5XXX_RAMBAR_V (0x00000001)\r
+\r
+/* Read macros for D0/D1 reset values */\r
+#define MCF5XXX_D0_PF(x) (((x)&0xFF000000)>>24)\r
+#define MCF5XXX_D0_VER(x) (((x)&0x00F00000)>>20)\r
+#define MCF5XXX_D0_REV(x) (((x)&0x000F0000)>>16)\r
+#define MCF5XXX_D0_MAC(x) ((x)&0x00008000)\r
+#define MCF5XXX_D0_DIV(x) ((x)&0x00004000)\r
+#define MCF5XXX_D0_EMAC(x) ((x)&0x00002000)\r
+#define MCF5XXX_D0_FPU(x) ((x)&0x00001000)\r
+#define MCF5XXX_D0_MMU(x) ((x)&0x00000800)\r
+#define MCF5XXX_D0_ISA(x) (((x)&0x000000F0)>>4)\r
+#define MCF5XXX_D0_DEBUG(x) (((x)&0x0000000F)>>0)\r
+#define MCF5XXX_D1_CL(x) (((x)&0xC0000000)>>30)\r
+#define MCF5XXX_D1_ICA(x) (((x)&0x30000000)>>28)\r
+#define MCF5XXX_D1_ICSIZ(x) (((x)&0x0F000000)>>24)\r
+#define MCF5XXX_D1_RAM0SIZ(x) (((x)&0x00F00000)>>20)\r
+#define MCF5XXX_D1_ROM0SIZ(x) (((x)&0x000F0000)>>16)\r
+#define MCF5XXX_D1_BUSW(x) (((x)&0x0000C000)>>14)\r
+#define MCF5XXX_D1_DCA(x) (((x)&0x00003000)>>12)\r
+#define MCF5XXX_D1_DCSIZ(x) (((x)&0x00000F00)>>8)\r
+#define MCF5XXX_D1_RAM1SIZ(x) (((x)&0x000000F0)>>4)\r
+#define MCF5XXX_D1_ROM1SIZ(x) (((x)&0x0000000F)>>0)\r
+\r
+/***********************************************************************/\r
+/*\r
+ * The ColdFire family of processors has a simplified exception stack\r
+ * frame that looks like the following:\r
+ *\r
+ * 3322222222221111 111111\r
+ * 1098765432109876 5432109876543210\r
+ * 8 +----------------+----------------+\r
+ * | Program Counter |\r
+ * 4 +----------------+----------------+\r
+ * |FS/Fmt/Vector/FS| SR |\r
+ * SP --> 0 +----------------+----------------+\r
+ *\r
+ * The stack self-aligns to a 4-byte boundary at an exception, with\r
+ * the FS/Fmt/Vector/FS field indicating the size of the adjustment\r
+ * (SP += 0,1,2,3 bytes).\r
+ */\r
+#define MCF5XXX_RD_SF_FORMAT(PTR) \\r
+ ((*((uint16 *)(PTR)) >> 12) & 0x00FF)\r
+\r
+#define MCF5XXX_RD_SF_VECTOR(PTR) \\r
+ ((*((uint16 *)(PTR)) >> 2) & 0x00FF)\r
+\r
+#define MCF5XXX_RD_SF_FS(PTR) \\r
+ ( ((*((uint16 *)(PTR)) & 0x0C00) >> 8) | (*((uint16 *)(PTR)) & 0x0003) )\r
+\r
+#define MCF5XXX_SF_SR(PTR) *((uint16 *)(PTR)+1)\r
+#define MCF5XXX_SF_PC(PTR) *((uint32 *)(PTR)+1)\r
+\r
+/********************************************************************/\r
+/*\r
+ * Functions provided in mcf5xxx.s\r
+ */\r
+int asm_set_ipl (uint32);\r
+void mcf5xxx_exe_wdebug (void *);\r
+void mcf5xxx_wr_sr (uint32);\r
+void mcf5xxx_wr_cacr (uint32);\r
+void mcf5xxx_wr_asid (uint32);\r
+void mcf5xxx_wr_acr0 (uint32);\r
+void mcf5xxx_wr_acr1 (uint32);\r
+void mcf5xxx_wr_acr2 (uint32);\r
+void mcf5xxx_wr_acr3 (uint32);\r
+void mcf5xxx_wr_mmubar (uint32);\r
+void mcf5xxx_wr_other_a7 (uint32);\r
+void mcf5xxx_wr_other_sp (uint32);\r
+void mcf5xxx_wr_vbr (uint32);\r
+void mcf5xxx_wr_macsr (uint32);\r
+void mcf5xxx_wr_mask (uint32);\r
+void mcf5xxx_wr_acc0 (uint32);\r
+void mcf5xxx_wr_accext01 (uint32);\r
+void mcf5xxx_wr_accext23 (uint32);\r
+void mcf5xxx_wr_acc1 (uint32);\r
+void mcf5xxx_wr_acc2 (uint32);\r
+void mcf5xxx_wr_acc3 (uint32);\r
+void mcf5xxx_wr_pc (uint32);\r
+void mcf5xxx_wr_rombar0 (uint32);\r
+void mcf5xxx_wr_rombar1 (uint32);\r
+void mcf5xxx_wr_rambar0 (uint32);\r
+void mcf5xxx_wr_rambar1 (uint32);\r
+void mcf5xxx_wr_mpcr (uint32);\r
+void mcf5xxx_wr_secmbar (uint32);\r
+void mcf5xxx_wr_mbar1 (uint32);\r
+void mcf5xxx_wr_mbar (uint32);\r
+void mcf5xxx_wr_mbar0 (uint32);\r
+\r
+/*\r
+ * Functions provided in mcf5xxx.c\r
+ */\r
+void mcf5xxx_exception_handler (void *);\r
+void mcf5xxx_interpret_d0d1 (int, int);\r
+void mcf5xxx_irq_enable (void);\r
+void mcf5xxx_irq_disable (void);\r
+ADDRESS mcf5xxx_set_handler (int, ADDRESS);\r
+\r
+/*\r
+ * Functions provided by processor specific C file\r
+ */\r
+void cpu_handle_interrupt (int);\r
+\r
+/********************************************************************/\r
+\r
+#endif /* _CPU_MCF5XXX_H */\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS.org V5.0.3 - copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section\r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ ***************************************************************************\r
+ * *\r
+ * SAVE TIME AND MONEY! We can port FreeRTOS.org to your own hardware, *\r
+ * and even write all or part of your application on your behalf. *\r
+ * See http://www.OpenRTOS.com for details of the services we provide to *\r
+ * expedite your project. *\r
+ * *\r
+ ***************************************************************************\r
+ ***************************************************************************\r
+\r
+ Please ensure to read the configuration and relevant port sections of the\r
+ online documentation.\r
+\r
+ http://www.FreeRTOS.org - Documentation, latest information, license and \r
+ contact details.\r
+\r
+ http://www.SafeRTOS.com - A version that is certified for use in safety \r
+ critical systems.\r
+\r
+ http://www.OpenRTOS.com - Commercial support, development, porting, \r
+ licensing and training services.\r
+*/\r
+\r
+/*\r
+ Implements a simplistic WEB server. Every time a connection is made and\r
+ data is received a dynamic page that shows the current TCP/IP statistics\r
+ is generated and returned. The connection is then closed.\r
+\r
+ This file was adapted from a FreeRTOS lwIP slip demo supplied by a third\r
+ party.\r
+*/\r
+\r
+/* ------------------------ System includes ------------------------------- */\r
+\r
+\r
+/* ------------------------ FreeRTOS includes ----------------------------- */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "semphr.h"\r
+\r
+/* ------------------------ lwIP includes --------------------------------- */\r
+#include "lwip/api.h"\r
+#include "lwip/tcpip.h"\r
+#include "lwip/ip.h"\r
+#include "lwip/memp.h"\r
+#include "lwip/stats.h"\r
+#include "netif/loopif.h"\r
+\r
+/* ------------------------ Project includes ------------------------------ */\r
+#include "common.h"\r
+\r
+#include "HTTPDemo.h"\r
+\r
+/* ------------------------ Defines --------------------------------------- */\r
+/* The size of the buffer in which the dynamic WEB page is created. */\r
+#define webMAX_PAGE_SIZE ( 1024 ) /*FSL: buffer containing array*/\r
+\r
+/* Standard GET response. */\r
+#define webHTTP_OK "HTTP/1.0 200 OK\r\nContent-type: text/html\r\n\r\n"\r
+\r
+/* The port on which we listen. */\r
+#define webHTTP_PORT ( 80 )\r
+\r
+/* Delay on close error. */\r
+#define webSHORT_DELAY ( 10 )\r
+\r
+/* Format of the dynamic page that is returned on each connection. */\r
+#define webHTML_START \\r
+"<html>\\r
+<head>\\r
+</head>\\r
+<BODY onLoad=\"window.setTimeout("location.href='index.html'",1000)\"bgcolor=\"#CCCCff\">\\r
+\r\n\r\nPage Hits = "\r
+\r
+#define webHTML_END \\r
+"\r\n" \\r
+"</pre>\r\n" \\r
+"</BODY>\r\n" \\r
+"</html>"\r
+\r
+#if INCLUDE_uxTaskGetStackHighWaterMark\r
+ static volatile unsigned portBASE_TYPE uxHighWaterMark_web = 0;\r
+#endif\r
+\r
+/* ------------------------ Prototypes ------------------------------------ */\r
+static void vProcessConnection( struct netconn *pxNetCon );\r
+\r
+/*------------------------------------------------------------*/\r
+\r
+/*\r
+ * Process an incoming connection on port 80.\r
+ *\r
+ * This simply checks to see if the incoming data contains a GET request, and\r
+ * if so sends back a single dynamically created page. The connection is then\r
+ * closed. A more complete implementation could create a task for each\r
+ * connection.\r
+ */\r
+static void vProcessConnection( struct netconn *pxNetCon )\r
+{\r
+ static portCHAR cDynamicPage[webMAX_PAGE_SIZE], cPageHits[11];\r
+ struct netbuf *pxRxBuffer;\r
+ portCHAR *pcRxString;\r
+ unsigned portSHORT usLength;\r
+ static unsigned portLONG ulPageHits = 0;\r
+\r
+ /* We expect to immediately get data. */\r
+ pxRxBuffer = netconn_recv( pxNetCon );\r
+\r
+ if( pxRxBuffer != NULL )\r
+ {\r
+ /* Where is the data? */\r
+ netbuf_data( pxRxBuffer, ( void * )&pcRxString, &usLength );\r
+\r
+ /* Is this a GET? We don't handle anything else. */\r
+ if( !strncmp( pcRxString, "GET", 3 ) )\r
+ {\r
+ pcRxString = cDynamicPage;\r
+\r
+ /* Update the hit count. */\r
+ ulPageHits++;\r
+ sprintf( cPageHits, "%d", (int)ulPageHits );\r
+\r
+ /* Write out the HTTP OK header. */ \r
+ netconn_write( pxNetCon, webHTTP_OK, ( u16_t ) strlen( webHTTP_OK ), NETCONN_COPY );\r
+\r
+ /* Generate the dynamic page...\r
+ \r
+ ... First the page header. */\r
+ strcpy( cDynamicPage, webHTML_START );\r
+ /* ... Then the hit count... */\r
+ strcat( cDynamicPage, cPageHits );\r
+ \r
+ strcat( cDynamicPage,\r
+ "<p><pre>Task State Priority Stack #<br>************************************************<br>" );\r
+ /* ... Then the list of tasks and their status... */\r
+ vTaskList( ( signed portCHAR * )cDynamicPage + strlen( cDynamicPage ) ); \r
+ \r
+ /* ... Finally the page footer. */\r
+ strcat( cDynamicPage, webHTML_END );\r
+\r
+ /* Write out the dynamically generated page. */\r
+ netconn_write( pxNetCon, cDynamicPage, ( u16_t ) strlen( cDynamicPage ), NETCONN_COPY );\r
+ }\r
+ netbuf_delete( pxRxBuffer );\r
+ }\r
+ netconn_close( pxNetCon );\r
+}\r
+\r
+/*------------------------------------------------------------*/\r
+\r
+void vlwIPInit( void )\r
+{\r
+ /* Initialize lwIP and its interface layer. */\r
+ tcpip_init( NULL, NULL );\r
+}\r
+\r
+/*------------------------------------------------------------*/\r
+\r
+void vBasicWEBServer( void *pvParameters )\r
+{\r
+ struct netconn *pxHTTPListener, *pxNewConnection;\r
+ struct ip_addr xIpAddr, xNetMast, xGateway;\r
+ static struct netif fec523x_if;\r
+ extern err_t ethernetif_init(struct netif *netif);\r
+\r
+ /* Parameters are not used - suppress compiler error. */\r
+ ( void )pvParameters;\r
+\r
+ vlwIPInit();\r
+\r
+ /* Create and configure the FEC interface. */\r
+ IP4_ADDR( &xIpAddr, configIP_ADDR0, configIP_ADDR1, configIP_ADDR2, configIP_ADDR3 );\r
+ IP4_ADDR( &xNetMast, configNET_MASK0, configNET_MASK1, configNET_MASK2, configNET_MASK3 );\r
+ IP4_ADDR( &xGateway, configGW_ADDR0, configGW_ADDR1, configGW_ADDR2, configGW_ADDR3 );\r
+ netif_add( &fec523x_if, &xIpAddr, &xNetMast, &xGateway, NULL, ethernetif_init, tcpip_input );\r
+\r
+ /* make it the default interface */\r
+ netif_set_default( &fec523x_if );\r
+\r
+ /* bring it up */\r
+ netif_set_up( &fec523x_if );\r
+\r
+ /* Create a new tcp connection handle */\r
+ pxHTTPListener = netconn_new( NETCONN_TCP );\r
+ netconn_bind( pxHTTPListener, NULL, webHTTP_PORT );\r
+ netconn_listen( pxHTTPListener );\r
+\r
+ /* Loop forever */\r
+ for( ;; )\r
+ { \r
+ /* Wait for connection. */\r
+ pxNewConnection = netconn_accept( pxHTTPListener );\r
+\r
+ if( pxNewConnection != NULL )\r
+ {\r
+ /* Service connection. */\r
+ vProcessConnection( pxNewConnection );\r
+ while( netconn_delete( pxNewConnection ) != ERR_OK )\r
+ {\r
+ vTaskDelay( webSHORT_DELAY );\r
+ }\r
+ }\r
+ }\r
+}\r
--- /dev/null
+/*\r
+ FreeRTOS.org V5.0.3 - copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section\r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ ***************************************************************************\r
+ * *\r
+ * SAVE TIME AND MONEY! We can port FreeRTOS.org to your own hardware, *\r
+ * and even write all or part of your application on your behalf. *\r
+ * See http://www.OpenRTOS.com for details of the services we provide to *\r
+ * expedite your project. *\r
+ * *\r
+ ***************************************************************************\r
+ ***************************************************************************\r
+\r
+ Please ensure to read the configuration and relevant port sections of the\r
+ online documentation.\r
+\r
+ http://www.FreeRTOS.org - Documentation, latest information, license and \r
+ contact details.\r
+\r
+ http://www.SafeRTOS.com - A version that is certified for use in safety \r
+ critical systems.\r
+\r
+ http://www.OpenRTOS.com - Commercial support, development, porting, \r
+ licensing and training services.\r
+*/\r
+\r
+#ifndef BASIC_WEB_SERVER_H\r
+#define BASIC_WEB_SERVER_H\r
+\r
+/* The function that implements the WEB server task. */\r
+void vBasicWEBServer( void *pvParameters );\r
+\r
+ \r
+/* Initialisation required by lwIP. */\r
+void vlwIPInit( void );\r
+\r
+ \r
+#endif /* \r
+ */\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS.org V5.1.0 - Copyright (C) 2003-2008 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS.org distribution.\r
+\r
+ FreeRTOS.org is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS.org is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS.org; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS.org, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section\r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ ***************************************************************************\r
+ * *\r
+ * SAVE TIME AND MONEY! We can port FreeRTOS.org to your own hardware, *\r
+ * and even write all or part of your application on your behalf. *\r
+ * See http://www.OpenRTOS.com for details of the services we provide to *\r
+ * expedite your project. *\r
+ * *\r
+ ***************************************************************************\r
+ ***************************************************************************\r
+\r
+ Please ensure to read the configuration and relevant port sections of the\r
+ online documentation.\r
+\r
+ http://www.FreeRTOS.org - Documentation, latest information, license and\r
+ contact details.\r
+\r
+ http://www.SafeRTOS.com - A version that is certified for use in safety\r
+ critical systems.\r
+\r
+ http://www.OpenRTOS.com - Commercial support, development, porting,\r
+ licensing and training services.\r
+*/\r
+\r
+/*\r
+ Changes from V2.5.2\r
+\r
+ + All LED's are turned off to start.\r
+*/\r
+\r
+\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "partest.h"\r
+\r
+#define partstNUM_LEDs 4\r
+\r
+/*-----------------------------------------------------------\r
+ * Simple parallel port IO routines.\r
+ *-----------------------------------------------------------*/\r
+\r
+void vParTestInitialise( void )\r
+{\r
+ /* Enable signals as GPIO */\r
+ MCF_GPIO_PTCPAR = 0\r
+ | MCF_GPIO_PTCPAR_DTIN3_GPIO\r
+ | MCF_GPIO_PTCPAR_DTIN2_GPIO\r
+ | MCF_GPIO_PTCPAR_DTIN1_GPIO\r
+ | MCF_GPIO_PTCPAR_DTIN0_GPIO;\r
+ \r
+ /* Enable signals as digital outputs */\r
+ MCF_GPIO_DDRTC = 0\r
+ | MCF_GPIO_DDRTC_DDRTC3\r
+ | MCF_GPIO_DDRTC_DDRTC2\r
+ | MCF_GPIO_DDRTC_DDRTC1\r
+ | MCF_GPIO_DDRTC_DDRTC0;\r
+\r
+ MCF_GPIO_PORTTC = 0x00; // TURN LEDS OFF\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue )\r
+{\r
+unsigned portBASE_TYPE uxLEDMask;\r
+\r
+ if( uxLED < partstNUM_LEDs )\r
+ {\r
+ uxLEDMask = 1UL << uxLED;\r
+ \r
+ taskENTER_CRITICAL();\r
+ {\r
+ if( xValue )\r
+ {\r
+ MCF_GPIO_PORTTC |= uxLEDMask;\r
+ }\r
+ else\r
+ {\r
+ MCF_GPIO_PORTTC &= ~uxLEDMask;\r
+ }\r
+ }\r
+ taskEXIT_CRITICAL();\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestToggleLED( unsigned portBASE_TYPE uxLED )\r
+{\r
+unsigned portBASE_TYPE uxLEDMask;\r
+\r
+ if( uxLED < partstNUM_LEDs )\r
+ {\r
+ uxLEDMask = 1UL << uxLED;\r
+ \r
+ taskENTER_CRITICAL();\r
+ {\r
+ if( MCF_GPIO_PORTTC & uxLEDMask )\r
+ {\r
+ MCF_GPIO_PORTTC &= ~uxLEDMask;\r
+ }\r
+ else\r
+ {\r
+ MCF_GPIO_PORTTC |= uxLEDMask;\r
+ }\r
+ }\r
+ taskEXIT_CRITICAL();\r
+ }\r
+}\r
+\r
--- /dev/null
+ResetHalt\r
+\r
+; Set VBR to the beginning of what will be SRAM\r
+; VBR is an absolute CPU register\r
+writecontrolreg 0x0801 0x20000000\r
+\r
+; Set RAMBAR1 (SRAM)\r
+writecontrolreg 0x0C05 0x20000021\r
+\r
+; Set FLASHBAR (Flash)\r
+writecontrolreg 0x0C04 0x00000061\r
+\r
+; Enable PST[3:0] signals\r
+writemem.b 0x40100074 0x0F\r
--- /dev/null
+// Memory Configuration File\r
+//\r
+// Description:\r
+// A memory configuration file contains commands that define the legally accessible\r
+// areas of memory for your specific board. Useful for example when the debugger\r
+// tries to display the content of a "char *" variable, that has not yet been initialized.\r
+// In this case the debugger may try to read from a bogus address, which could cause a\r
+// bus error.\r
+//\r
+// Board:\r
+// Freescale MCF52259\r
+//\r
+// Reference:\r
+// \r
+\r
+\r
+// All reserved ranges read back 0xBABA...\r
+reservedchar 0xBA\r
+\r
+address IPSBAR_BASE 0x40000000\r
+\r
+usederivative "MCF52259"\r
+\r
+// Memory Map:\r
+// ----------------------------------------------------------------------\r
+range 0x00000000 0x0007FFFF 4 Read // 512 KByte Internal Flash Memory\r
+reserved 0x00080000 0x1FFFFFFF\r
+range 0x20000000 0x2000FFFF 4 ReadWrite // 64 Kbytes Internal SRAM\r
+reserved 0x20010000 0x3FFFFFFF \r
+// $IPSBAR_BASE $IPSBAR_BASE + 0x1FFFFF // Memory Mapped Registers\r
+reserved $IPSBAR_BASE + 0x200000 0xFFFFFFFF\r
--- /dev/null
+<?xml version="1.0" encoding="iso-8859-1" standalone="no" ?>\r
+\r
+<fpconfig xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="fp_config.xsd">\r
+\r
+ <targetconfwindow>\r
+ <usecustomsettings>false</usecustomsettings>\r
+ <targetprocessor>52259</targetprocessor>\r
+ <connection></connection>\r
+ <usetargetinit>true</usetargetinit>\r
+ <targetinitfile>{CodeWarrior}\ColdFire_Support\Initialization_Files\MCF52259.cfg</targetinitfile>\r
+ <targetmembuffaddr>0x20000000</targetmembuffaddr>\r
+ <targetmembuffsize>0x00008000</targetmembuffsize>\r
+ <enablelogging>true</enablelogging>\r
+ <verifywrites>false</verifywrites>\r
+ </targetconfwindow>\r
+\r
+ <flashconfwindow>\r
+ <membaseaddr>0x00000000</membaseaddr>\r
+ <device>CFM_MCF5225X_512</device>\r
+ <organization>32Kx16x1</organization>\r
+ <flashstart>0x00000000</flashstart>\r
+ <flashend>0x0007FFFF</flashend>\r
+ </flashconfwindow>\r
+\r
+ <programverifywindow>\r
+ <useselectedfile>false</useselectedfile>\r
+ <projbuildtargetfile>nofile</projbuildtargetfile>\r
+ <fileiotype>Auto Detect</fileiotype>\r
+ <restrictaddrrange>false</restrictaddrrange>\r
+ <restrictaddrrangestart>0x00000000</restrictaddrrangestart>\r
+ <restrictaddrrangeend>0x0007FFFF</restrictaddrrangeend>\r
+ <applyaddroffset>false</applyaddroffset>\r
+ <addroffset>0x00000000</addroffset>\r
+ </programverifywindow>\r
+\r
+ <eraseblankcheckwindow>\r
+ <eraseallsectors>true</eraseallsectors>\r
+ <sector/>\r
+ <processsectorsindividually>false</processsectorsindividually>\r
+ </eraseblankcheckwindow>\r
+\r
+ <checksumwindow>\r
+ <computechecksumover>FileOnTarg</computechecksumover>\r
+ <addrstart>0x00000000</addrstart>\r
+ <addrsize>0x0000FFFF</addrsize>\r
+ </checksumwindow>\r
+\r
+</fpconfig>\r
--- /dev/null
+ResetHalt\r
+\r
+; Set VBR to the beginning of what will be SRAM\r
+; VBR is an absolute CPU register\r
+writecontrolreg 0x0801 0x20000000\r
+\r
+; Set RAMBAR1 (SRAM)\r
+writecontrolreg 0x0C05 0x20000021\r
+\r
+; Set FLASHBAR (Flash)\r
+writecontrolreg 0x0C04 0x00000061\r
+\r
+; Enable PST[3:0] signals\r
+writemem.b 0x40100074 0x0F\r
--- /dev/null
+/*\r
+ * File: mcf52xx.c\r
+ * Purpose: Source to select CF derivative\r
+ *\r
+ * Notes:\r
+ * \r
+ * License: All software covered by license agreement in -\r
+ * docs/Freescale_Software_License.pdf\r
+ */\r
+/********************************************************************/\r
+\r
+#include "common.h"\r
+\r
+/********************************************************************/\r
+/*\r
+ * Pause for the specified number of micro-seconds.\r
+ * Uses DTIM3 as a timer\r
+ */\r
+void\r
+cpu_pause(int usecs)\r
+{\r
+ /* Enable the DMA Timer 3 */\r
+ MCF_DTIM3_DTRR = (vuint32)(usecs - 1);\r
+ MCF_DTIM3_DTER = MCF_DTIM_DTER_REF;\r
+ MCF_DTIM3_DTMR = 0\r
+ | MCF_DTIM_DTMR_PS(SYSTEM_CLOCK)\r
+ | MCF_DTIM_DTMR_FRR\r
+ | MCF_DTIM_DTMR_CLK_DIV1\r
+ | MCF_DTIM_DTMR_RST;\r
+\r
+ while ((MCF_DTIM3_DTER & MCF_DTIM_DTER_REF) == 0) \r
+ {};\r
+ \r
+ /* Disable the timer */\r
+ MCF_DTIM3_DTMR = 0;\r
+}\r
+\r
+/********************************************************************/\r
+void\r
+board_handle_interrupt (int vector)\r
+{\r
+ switch (vector)\r
+ {\r
+ case 65: /* Eport Interrupt 1 */\r
+ printf("SW2\n");\r
+ MCF_EPORT_EPFR = MCF_EPORT_EPFR_EPF1;\r
+ break;\r
+ case 69: /* Eport Interrupt 5 */\r
+ printf("SW1\n");\r
+ MCF_EPORT_EPFR = MCF_EPORT_EPFR_EPF5;\r
+ break;\r
+ case 71: /* Eport Interrupt 7 */\r
+ printf("ABORT\n");\r
+ MCF_EPORT_EPFR = MCF_EPORT_EPFR_EPF7;\r
+ break;\r
+ case 66: /* Eport Interrupt 2 */\r
+ case 67: /* Eport Interrupt 3 */\r
+ case 68: /* Eport Interrupt 4 */\r
+ case 70: /* Eport Interrupt 6 */\r
+ default:\r
+ MCF_EPORT_EPFR = (uint8)(0x01 << (vector - 64));\r
+ printf("Edge Port Interrupt #%d\n",vector - 64);\r
+ break;\r
+ }\r
+}\r
+/********************************************************************/\r
+\r
+/********************************************************************/\r
+void\r
+cpu_handle_interrupt (int vector)\r
+{\r
+ if (vector < 64 || vector > 192)\r
+ return;\r
+ \r
+ if (vector >= 64 && vector <= 71)\r
+ board_handle_interrupt(vector);\r
+ else\r
+ printf("User Defined Vector #%d\n",vector);\r
+}\r
+/********************************************************************/\r
+\r
--- /dev/null
+/*\r
+ * File: mcf5225x.h\r
+ * Purpose: Register and bit definitions\r
+ * \r
+ * License: All software covered by license agreement in -\r
+ * docs/Freescale_Software_License.pdf\r
+ */\r
+\r
+#ifndef __MCF5225x_H__\r
+#define __MCF5225x_H__\r
+\r
+/********************************************************************/\r
+/*\r
+ * 5225x includes\r
+ */\r
+\r
+#include "MCF52259_SCM.h"\r
+#include "MCF52259_DMA.h"\r
+#include "MCF52259_UART.h"\r
+#include "MCF52259_I2C.h"\r
+#include "MCF52259_QSPI.h"\r
+#include "MCF52259_TMR.h"\r
+#include "MCF52259_INTC.h"\r
+#include "MCF52259_FEC.h"\r
+#include "MCF52259_GPIO.h"\r
+#include "MCF52259_PAD.h"\r
+#include "MCF52259_RCM.h"\r
+#include "MCF52259_CCM.h"\r
+#include "MCF52259_PMM.h"\r
+#include "MCF52259_CLOCK.h"\r
+#include "MCF52259_EPORT.h"\r
+#include "MCF52259_BWT.h"\r
+#include "MCF52259_PIT.h"\r
+#include "MCF52259_FlexCAN.h"\r
+#include "MCF52259_RTC.h"\r
+#include "MCF52259_ADC.h"\r
+#include "MCF52259_GPT.h"\r
+#include "MCF52259_PWM.h"\r
+#include "MCF52259_USB_OTG.h"\r
+#include "MCF52259_CFM.h"\r
+#include "MCF52259_RNGA.h"\r
+#include "MCF52259_fbcs.h"\r
+#include "mcf52259_dtim.h"\r
+\r
+\r
+/********************************************************************/\r
+\r
+#endif /* __MCF5225x_H__ */\r
--- /dev/null
+/*\r
+ * File: mcf5225x_lo.s\r
+ * Purpose: Low-level routines for the MCF5225x.\r
+ *\r
+ * Notes: \r
+ * \r
+ * License: All software covered by license agreement in -\r
+ * docs/Freescale_Software_License.pdf\r
+ */\r
+\r
+#define mcf5225x_init _mcf5225x_init\r
+#define common_startup _common_startup\r
+#define cpu_startup _cpu_startup\r
+#define main _main\r
+#define __IPSBAR ___IPSBAR \r
+#define __SRAM ___SRAM \r
+#define __FLASH ___FLASH \r
+#define __SP_INIT ___SP_INIT \r
+ \r
+ .extern __IPSBAR\r
+ .extern __SRAM\r
+ .extern __FLASH\r
+ .extern __SP_INIT\r
+ .extern mcf5225x_init\r
+ .extern common_startup\r
+ .extern cpu_startup\r
+ .extern main\r
+\r
+ .global asm_startmeup\r
+ .global _asm_startmeup\r
+ .global d0_reset\r
+ .global _d0_reset\r
+ .global d1_reset\r
+ .global _d1_reset\r
+\r
+ .data\r
+ \r
+d0_reset:\r
+_d0_reset: .long 0\r
+d1_reset:\r
+_d1_reset: .long 0\r
+\r
+ .text\r
+\r
+/********************************************************************\r
+ * \r
+ * This is the main entry point upon hard reset. The memory map is\r
+ * setup based on linker file definitions, then the higher level\r
+ * system initialization routine is called. Finally, we jump to the\r
+ * "main" process. \r
+ */\r
+asm_startmeup:\r
+_asm_startmeup:\r
+\r
+ move.w #0x2700,sr\r
+\r
+ /* Save off reset values of D0 and D1 */\r
+ move.l d0,d6\r
+ move.l d1,d7\r
+ \r
+ /* Initialize RAMBAR1: locate SRAM and validate it */\r
+ move.l #__SRAM,d0\r
+ andi.l #0xFFFF0000,d0\r
+ add.l #0x21,d0\r
+ movec d0,RAMBAR1\r
+\r
+ /* Locate Stack Pointer */ \r
+ move.l #__SP_INIT,sp\r
+\r
+ /* Initialize IPSBAR */\r
+ move.l #__IPSBAR,d0\r
+ add.l #0x1,d0\r
+ move.l d0,0x40000000\r
+ \r
+ /* Initialize FLASHBAR */\r
+ move.l #__FLASH,d0\r
+ cmp.l #0x00000000,d0\r
+ bne change_flashbar\r
+ add.l #0x61,d0\r
+ movec d0,RAMBAR0\r
+\r
+_continue_startup:\r
+\r
+ /* Locate Stack Pointer */ \r
+ move.l #__SP_INIT,sp\r
+\r
+ /* Initialize the system */\r
+ jsr mcf5225x_init\r
+\r
+ /* Common startup code */\r
+ //jsr common_startup\r
+\r
+ /* Save off intial D0 and D1 to RAM */\r
+ move.l d6,d0_reset\r
+ move.l d7,d1_reset\r
+ \r
+ /* CPU specific startup code */\r
+ //jsr cpu_startup\r
+\r
+ /* Jump to the main process */\r
+ jsr main\r
+ \r
+ bra .\r
+ nop\r
+ nop\r
+ halt\r
+\r
+change_flashbar:\r
+ /* \r
+ * The following sequence is used to set FLASHBAR. Since we may \r
+ * be executing from Flash, we must put the routine into SRAM for\r
+ * execution and then jump back to Flash using the new address.\r
+ *\r
+ * The following instructions are coded into the SRAM:\r
+ *\r
+ * move.l #(__FLASH + 0x21),d0\r
+ * movec d0, RAMBAR0\r
+ * jmp _continue_startup\r
+ *\r
+ * An arbitrary SRAM address is chosen until the real address\r
+ * can be loaded.\r
+ *\r
+ * This routine is not necessary if the default Flash address\r
+ * (0x00000000) is used.\r
+ *\r
+ * If running in SRAM, change_flashbar should not be executed \r
+ */\r
+\r
+ move.l #__SRAM,a0\r
+\r
+ /* Code "move.l #(__FLASH + 0x21),d0" into SRAM */\r
+ move.w #0x203C,d0\r
+ move.w d0,(a0)+\r
+ move.l #__FLASH,d0\r
+ add.l #0x21,d0\r
+ move.l d0,(a0)+\r
+ \r
+ /* Code "movec d0,FLASHBAR" into SRAM */\r
+ move.l #0x4e7b0C04,d0\r
+ move.l d0,(a0)+\r
+ \r
+ /* Code "jmp _continue_startup" into SRAM */\r
+ move.w #0x4EF9,d0\r
+ move.w d0,(a0)+\r
+ move.l #_continue_startup,d0\r
+ move.l d0,(a0)+\r
+\r
+ /* Jump to code segment in internal SRAM */\r
+ jmp __SRAM\r
+\r
+/********************************************************************/\r
+\r
+ .end\r
--- /dev/null
+/*\r
+ * File: sysinit.c\r
+ * Purpose: Reset configuration of the M52259EVB\r
+ * \r
+ * License: All software covered by license agreement in -\r
+ * docs/Freescale_Software_License.pdf\r
+ */\r
+\r
+#include "common.h"\r
+\r
+/********************************************************************/\r
+\r
+void mcf5225x_init(void);\r
+void mcf5225x_wtm_init(void);\r
+void mcf5225x_pll_init(void);\r
+void mcf5225x_uart_init(void);\r
+void mcf5225x_scm_init(void);\r
+void mcf5225x_gpio_init(void);\r
+\r
+/********************************************************************/\r
+void\r
+mcf5225x_init(void)\r
+{\r
+ register uint32 n;\r
+ register uint8 *dp, *sp;\r
+\r
+\r
+ /* \r
+ * Allow interrupts from ABORT, SW1, SW2 (IRQ[1,5,7]) \r
+ * and USB (IRQ[2,6])\r
+ */\r
+ \r
+ \r
+ /* Enable IRQ signals on the port */\r
+ MCF_GPIO_PNQPAR = 0\r
+ | MCF_GPIO_PNQPAR_IRQ1_IRQ1 \r
+ | MCF_GPIO_PNQPAR_IRQ5_IRQ5\r
+ | MCF_GPIO_PNQPAR_IRQ7_IRQ7;\r
+ \r
+ /* Set EPORT to look for falling edges */\r
+ MCF_EPORT_EPPAR = 0\r
+ | MCF_EPORT_EPPAR_EPPA1_FALLING \r
+ | MCF_EPORT_EPPAR_EPPA2_FALLING \r
+ | MCF_EPORT_EPPAR_EPPA5_FALLING\r
+ | MCF_EPORT_EPPAR_EPPA6_FALLING \r
+ | MCF_EPORT_EPPAR_EPPA7_FALLING;\r
+ \r
+ /* Clear any currently triggered events on the EPORT */\r
+ MCF_EPORT_EPIER = 0\r
+ | MCF_EPORT_EPIER_EPIE1\r
+ | MCF_EPORT_EPIER_EPIE2 \r
+ | MCF_EPORT_EPIER_EPIE5\r
+ | MCF_EPORT_EPIER_EPIE6 \r
+ | MCF_EPORT_EPIER_EPIE7;\r
+ \r
+ /* Enable interrupts in the interrupt controller */\r
+ MCF_INTC0_IMRL &= ~(0\r
+ | MCF_INTC_IMRL_INT_MASK1 \r
+ | MCF_INTC_IMRL_INT_MASK2 \r
+ | MCF_INTC_IMRL_INT_MASK5 \r
+ | MCF_INTC_IMRL_INT_MASK6 \r
+ | MCF_INTC_IMRL_INT_MASK7 \r
+ | MCF_INTC_IMRL_MASKALL);\r
+\r
+ \r
+ /* Enable debug */\r
+ MCF_GPIO_PDDPAR = 0x0F;\r
+ \r
+ /* Set real time clock freq */\r
+\r
+ MCF_CLOCK_RTCCR = 48000000;\r
+\r
+ /* Copy the vector table to RAM */\r
+ if (__VECTOR_RAM != VECTOR_TABLE)\r
+ {\r
+ for (n = 0; n < 256; n++)\r
+ __VECTOR_RAM[n] = VECTOR_TABLE[n];\r
+ \r
+ mcf5xxx_wr_vbr((uint32)__VECTOR_RAM);\r
+ }\r
+\r
+ /*\r
+ * Move initialized data from ROM to RAM.\r
+ */\r
+ if (__DATA_ROM != __DATA_RAM)\r
+ {\r
+ dp = (uint8 *)__DATA_RAM;\r
+ sp = (uint8 *)__DATA_ROM;\r
+ n = (uint32)(__DATA_END - __DATA_RAM);\r
+ while (n--)\r
+ *dp++ = *sp++;\r
+ }\r
+\r
+ /*\r
+ * Zero uninitialized data\r
+ */\r
+ if (__BSS_START != __BSS_END)\r
+ {\r
+ sp = (uint8 *)__BSS_START;\r
+ n = (uint32)(__BSS_END - __BSS_START);\r
+ while (n--)\r
+ *sp++ = 0;\r
+ }\r
+ mcf5225x_wtm_init();\r
+\r
+ mcf5225x_pll_init();\r
+ mcf5225x_scm_init();\r
+ mcf5225x_uart_init();\r
+}\r
+/********************************************************************/\r
+void\r
+mcf5225x_wtm_init(void)\r
+{\r
+ /*\r
+ * Disable Software Watchdog Timer\r
+ */\r
+ MCF_SCM_CWCR = 0;\r
+}\r
+/********************************************************************/\r
+void\r
+mcf5225x_pll_init(void)\r
+{\r
+ /*Required if booting with internal relaxation oscillator & pll off, clkmod[1:0]=00 & xtal=1 */\r
+#ifndef OMIT_OCLR_CONFIGURATION\r
+ MCF_CLOCK_OCLR = 0xC0; //turn on crystal\r
+ MCF_CLOCK_CCLR = 0x00; //switch to crystal \r
+ MCF_CLOCK_OCHR = 0x00; //turn off relaxation osc\r
+#endif\r
+\r
+ /* The PLL pre divider - 48MHz / 6 = 8MHz */\r
+ MCF_CLOCK_CCHR =0x05;\r
+ \r
+ \r
+ /* The PLL pre-divider affects this!!! \r
+ * Multiply 48Mhz reference crystal /CCHR by 10 to acheive system clock of 80Mhz\r
+ */\r
+\r
+ MCF_CLOCK_SYNCR &= ~(MCF_CLOCK_SYNCR_PLLEN);\r
+\r
+ MCF_CLOCK_SYNCR |= MCF_CLOCK_SYNCR_CLKSRC | MCF_CLOCK_SYNCR_PLLMODE;\r
+ \r
+ //80\r
+ MCF_CLOCK_SYNCR |= MCF_CLOCK_SYNCR_MFD(3) | MCF_CLOCK_SYNCR_RFD(0);\r
+ //64\r
+ //MCF_CLOCK_SYNCR = MCF_CLOCK_SYNCR_MFD(2) | MCF_CLOCK_SYNCR_RFD(0);\r
+ //16\r
+ //MCF_CLOCK_SYNCR = MCF_CLOCK_SYNCR_MFD(2) | MCF_CLOCK_SYNCR_RFD(2);\r
+ //8\r
+ //MCF_CLOCK_SYNCR = MCF_CLOCK_SYNCR_MFD(2) | MCF_CLOCK_SYNCR_RFD(3);\r
+ //1\r
+ //MCF_CLOCK_SYNCR = MCF_CLOCK_SYNCR_MFD(2) | MCF_CLOCK_SYNCR_RFD(6);\r
+ \r
+ MCF_CLOCK_SYNCR |= MCF_CLOCK_SYNCR_PLLEN;\r
+\r
+ \r
+ while (!(MCF_CLOCK_SYNSR & MCF_CLOCK_SYNSR_LOCK))\r
+ {\r
+ }\r
+}\r
+/********************************************************************/\r
+void\r
+mcf5225x_scm_init(void)\r
+{\r
+ /*\r
+ * Enable on-chip modules to access internal SRAM\r
+ */\r
+ MCF_SCM_RAMBAR = (0\r
+ | MCF_SCM_RAMBAR_BA(SRAM_ADDRESS)\r
+ | MCF_SCM_RAMBAR_BDE);\r
+}\r
+/********************************************************************/\r
+void\r
+mcf5225x_gpio_init(void)\r
+{\r
+ /*\r
+ * Initialize Port TA to enable Axcel control\r
+ */\r
+ MCF_GPIO_PTAPAR = 0x00; \r
+ MCF_GPIO_DDRTA = 0x0F;\r
+ MCF_GPIO_PORTTA = 0x04;\r
+ \r
+}\r
+/********************************************************************/\r
+void\r
+mcf5225x_uart_init(void)\r
+{\r
+ /*\r
+ * Initialize all three UARTs for serial communications\r
+ */\r
+\r
+ register uint16 ubgs;\r
+\r
+ /*\r
+ * Set Port UA to initialize URXD0/UTXD0\r
+ */\r
+ MCF_GPIO_PUAPAR = 0\r
+ | MCF_GPIO_PUAPAR_URXD0_URXD0\r
+ | MCF_GPIO_PUAPAR_UTXD0_UTXD0;\r
+\r
+ MCF_GPIO_PUBPAR = 0\r
+ | MCF_GPIO_PUBPAR_URXD1_URXD1\r
+ | MCF_GPIO_PUBPAR_UTXD1_UTXD1;\r
+\r
+ MCF_GPIO_PUCPAR = 0\r
+ | MCF_GPIO_PUCPAR_URXD2_URXD2\r
+ | MCF_GPIO_PUCPAR_UTXD2_UTXD2;\r
+\r
+ /*\r
+ * Reset Transmitter\r
+ */\r
+ MCF_UART0_UCR = MCF_UART_UCR_RESET_TX;\r
+ MCF_UART1_UCR = MCF_UART_UCR_RESET_TX;\r
+ MCF_UART2_UCR = MCF_UART_UCR_RESET_TX;\r
+\r
+ /*\r
+ * Reset Receiver\r
+ */\r
+ MCF_UART0_UCR = MCF_UART_UCR_RESET_RX;\r
+ MCF_UART1_UCR = MCF_UART_UCR_RESET_RX;\r
+ MCF_UART2_UCR = MCF_UART_UCR_RESET_RX;\r
+\r
+ /*\r
+ * Reset Mode Register\r
+ */\r
+ MCF_UART0_UCR = MCF_UART_UCR_RESET_MR;\r
+ MCF_UART1_UCR = MCF_UART_UCR_RESET_MR;\r
+ MCF_UART2_UCR = MCF_UART_UCR_RESET_MR;\r
+\r
+ /*\r
+ * No parity, 8-bits per character\r
+ */\r
+ MCF_UART0_UMR1 = (0\r
+ | MCF_UART_UMR_PM_NONE\r
+ | MCF_UART_UMR_BC_8 );\r
+ MCF_UART1_UMR1 = (0\r
+ | MCF_UART_UMR_PM_NONE\r
+ | MCF_UART_UMR_BC_8 );\r
+ MCF_UART2_UMR1 = (0\r
+ | MCF_UART_UMR_PM_NONE\r
+ | MCF_UART_UMR_BC_8 );\r
+\r
+ /*\r
+ * No echo or loopback, 1 stop bit\r
+ */\r
+ MCF_UART0_UMR2 = (0\r
+ | MCF_UART_UMR_CM_NORMAL\r
+ | MCF_UART_UMR_SB_STOP_BITS_1);\r
+ MCF_UART1_UMR2 = (0\r
+ | MCF_UART_UMR_CM_NORMAL\r
+ | MCF_UART_UMR_SB_STOP_BITS_1);\r
+ MCF_UART2_UMR2 = (0\r
+ | MCF_UART_UMR_CM_NORMAL\r
+ | MCF_UART_UMR_SB_STOP_BITS_1);\r
+\r
+ /*\r
+ * Set Rx and Tx baud by SYSTEM CLOCK\r
+ */\r
+ MCF_UART0_UCSR = (0\r
+ | MCF_UART_UCSR_RCS_SYS_CLK\r
+ | MCF_UART_UCSR_TCS_SYS_CLK);\r
+ MCF_UART1_UCSR = (0\r
+ | MCF_UART_UCSR_RCS_SYS_CLK\r
+ | MCF_UART_UCSR_TCS_SYS_CLK);\r
+ MCF_UART2_UCSR = (0\r
+ | MCF_UART_UCSR_RCS_SYS_CLK\r
+ | MCF_UART_UCSR_TCS_SYS_CLK);\r
+\r
+ /*\r
+ * Mask all UART interrupts\r
+ */\r
+ MCF_UART0_UIMR = 0;\r
+ MCF_UART1_UIMR = 0;\r
+ MCF_UART2_UIMR = 0;\r
+\r
+ /*\r
+ * Calculate baud settings\r
+ */\r
+ ubgs = (uint16)((SYSTEM_CLOCK*1000000)/(UART_BAUD * 32));\r
+\r
+ MCF_UART0_UBG1 = (uint8)((ubgs & 0xFF00) >> 8);\r
+ MCF_UART0_UBG2 = (uint8)(ubgs & 0x00FF);\r
+ MCF_UART1_UBG1 = (uint8)((ubgs & 0xFF00) >> 8);\r
+ MCF_UART1_UBG2 = (uint8)(ubgs & 0x00FF);\r
+ MCF_UART2_UBG1 = (uint8)((ubgs & 0xFF00) >> 8);\r
+ MCF_UART2_UBG2 = (uint8)(ubgs & 0x00FF);\r
+\r
+ /*\r
+ * Enable receiver and transmitter\r
+ */\r
+ MCF_UART0_UCR = (0\r
+ | MCF_UART_UCR_TX_ENABLED\r
+ | MCF_UART_UCR_RX_ENABLED);\r
+ MCF_UART1_UCR = (0\r
+ | MCF_UART_UCR_TX_ENABLED\r
+ | MCF_UART_UCR_RX_ENABLED);\r
+ MCF_UART2_UCR = (0\r
+ | MCF_UART_UCR_TX_ENABLED\r
+ | MCF_UART_UCR_RX_ENABLED);\r
+\r
+}\r
+/********************************************************************/\r
--- /dev/null
+/*\r
+ * File: vectors.s\r
+ * Purpose: MCF5225x vector table\r
+ * \r
+ * License: All software covered by license agreement in -\r
+ * docs/Freescale_Software_License.pdf\r
+ */\r
+\r
+#ifdef __GNUC__ /* { */\r
+#define sr %sr\r
+#define _asm_exception_handler irq_handler\r
+#define _timer_handler timer_handler\r
+#endif /* } __GNUC__ */\r
+\r
+ .global VECTOR_TABLE\r
+ .global _VECTOR_TABLE\r
+ .global start\r
+\r
+ .extern ___SP_INIT\r
+ .extern _asm_startmeup\r
+ .extern _asm_exception_handler\r
+ .extern _vPIT0InterruptHandler\r
+ .extern vPortYieldISR\r
+ .extern _vFECISRHandler \r
+ .text\r
+\r
+/*\r
+ * Exception Vector Table\r
+ */\r
+VECTOR_TABLE:\r
+_VECTOR_TABLE:\r
+INITSP: .long ___SP_INIT /* Initial SP */\r
+INITPC: .long _asm_startmeup /* Initial PC */\r
+vector02: .long _asm_exception_handler /* Access Error */\r
+vector03: .long _asm_exception_handler /* Address Error */\r
+vector04: .long _asm_exception_handler /* Illegal Instruction */\r
+vector05: .long _asm_exception_handler /* Reserved */\r
+vector06: .long _asm_exception_handler /* Reserved */\r
+vector07: .long _asm_exception_handler /* Reserved */\r
+vector08: .long _asm_exception_handler /* Privilege Violation */\r
+vector09: .long _asm_exception_handler /* Trace */\r
+vector0A: .long _asm_exception_handler /* Unimplemented A-Line */\r
+vector0B: .long _asm_exception_handler /* Unimplemented F-Line */\r
+vector0C: .long _asm_exception_handler /* Debug Interrupt */\r
+vector0D: .long _asm_exception_handler /* Reserved */\r
+vector0E: .long _asm_exception_handler /* Format Error */\r
+vector0F: .long _asm_exception_handler /* Unitialized Int. */\r
+vector10: .long _asm_exception_handler /* Reserved */\r
+vector11: .long _asm_exception_handler /* Reserved */\r
+vector12: .long _asm_exception_handler /* Reserved */\r
+vector13: .long _asm_exception_handler /* Reserved */\r
+vector14: .long _asm_exception_handler /* Reserved */\r
+vector15: .long _asm_exception_handler /* Reserved */\r
+vector16: .long _asm_exception_handler /* Reserved */\r
+vector17: .long _asm_exception_handler /* Reserved */\r
+vector18: .long _asm_exception_handler /* Spurious Interrupt */\r
+vector19: .long _asm_exception_handler /* Autovector Level 1 */\r
+vector1A: .long _asm_exception_handler /* Autovector Level 2 */\r
+vector1B: .long _asm_exception_handler /* Autovector Level 3 */\r
+vector1C: .long _asm_exception_handler /* Autovector Level 4 */\r
+vector1D: .long _asm_exception_handler /* Autovector Level 5 */\r
+vector1E: .long _asm_exception_handler /* Autovector Level 6 */\r
+vector1F: .long _asm_exception_handler /* Autovector Level 7 */\r
+vector20: .long _asm_exception_handler /* TRAP #0 */\r
+vector21: .long _asm_exception_handler /* TRAP #1 */\r
+vector22: .long _asm_exception_handler /* TRAP #2 */\r
+vector23: .long _asm_exception_handler /* TRAP #3 */\r
+vector24: .long _asm_exception_handler /* TRAP #4 */\r
+vector25: .long _asm_exception_handler /* TRAP #5 */\r
+vector26: .long _asm_exception_handler /* TRAP #6 */\r
+vector27: .long _asm_exception_handler /* TRAP #7 */\r
+vector28: .long _asm_exception_handler /* TRAP #8 */\r
+vector29: .long _asm_exception_handler /* TRAP #9 */\r
+vector2A: .long _asm_exception_handler /* TRAP #10 */\r
+vector2B: .long _asm_exception_handler /* TRAP #11 */\r
+vector2C: .long _asm_exception_handler /* TRAP #12 */\r
+vector2D: .long _asm_exception_handler /* TRAP #13 */\r
+vector2E: .long _asm_exception_handler /* TRAP #14 */\r
+vector2F: .long _asm_exception_handler /* TRAP #15 */\r
+vector30: .long _asm_exception_handler /* Reserved */\r
+vector31: .long _asm_exception_handler /* Reserved */\r
+vector32: .long _asm_exception_handler /* Reserved */\r
+vector33: .long _asm_exception_handler /* Reserved */\r
+vector34: .long _asm_exception_handler /* Reserved */\r
+vector35: .long _asm_exception_handler /* Reserved */\r
+vector36: .long _asm_exception_handler /* Reserved */\r
+vector37: .long _asm_exception_handler /* Reserved */\r
+vector38: .long _asm_exception_handler /* Reserved */\r
+vector39: .long _asm_exception_handler /* Reserved */\r
+vector3A: .long _asm_exception_handler /* Reserved */\r
+vector3B: .long _asm_exception_handler /* Reserved */\r
+vector3C: .long _asm_exception_handler /* Reserved */\r
+vector3D: .long _asm_exception_handler /* Reserved */\r
+vector3E: .long _asm_exception_handler /* Reserved */\r
+vector3F: .long _asm_exception_handler /* Reserved */\r
+vector40: .long _asm_exception_handler\r
+vector41: .long _asm_exception_handler\r
+vector42: .long _asm_exception_handler\r
+vector43: .long _asm_exception_handler\r
+vector44: .long _asm_exception_handler\r
+vector45: .long _asm_exception_handler\r
+vector46: .long _asm_exception_handler\r
+vector47: .long _asm_exception_handler\r
+vector48: .long _asm_exception_handler\r
+vector49: .long _asm_exception_handler\r
+vector4A: .long _asm_exception_handler\r
+vector4B: .long _asm_exception_handler\r
+vector4C: .long _asm_exception_handler\r
+vector4D: .long _asm_exception_handler\r
+vector4E: .long _asm_exception_handler\r
+vector4F: .long _asm_exception_handler\r
+vector50: .long vPortYieldISR\r
+vector51: .long _asm_exception_handler\r
+vector52: .long _asm_exception_handler\r
+vector53: .long _asm_exception_handler\r
+vector54: .long _asm_exception_handler\r
+vector55: .long _asm_exception_handler\r
+vector56: .long _asm_exception_handler\r
+vector57: .long _asm_exception_handler\r
+vector58: .long _asm_exception_handler\r
+vector59: .long _vFECISRHandler\r
+vector5A: .long _vFECISRHandler\r
+vector5B: .long _vFECISRHandler\r
+vector5C: .long _vFECISRHandler\r
+vector5D: .long _vFECISRHandler\r
+vector5E: .long _vFECISRHandler\r
+vector5F: .long _vFECISRHandler\r
+vector60: .long _asm_exception_handler\r
+vector61: .long _vFECISRHandler\r
+vector62: .long _vFECISRHandler\r
+vector63: .long _vFECISRHandler\r
+vector64: .long _asm_exception_handler\r
+vector65: .long _asm_exception_handler\r
+vector66: .long _asm_exception_handler\r
+vector67: .long _asm_exception_handler\r
+vector68: .long _asm_exception_handler\r
+vector69: .long _asm_exception_handler\r
+vector6A: .long _asm_exception_handler\r
+vector6B: .long _asm_exception_handler\r
+vector6C: .long _asm_exception_handler\r
+vector6D: .long _asm_exception_handler\r
+vector6E: .long _asm_exception_handler\r
+vector6F: .long _asm_exception_handler\r
+vector70: .long _asm_exception_handler\r
+vector71: .long _asm_exception_handler\r
+vector72: .long _asm_exception_handler\r
+vector73: .long _asm_exception_handler\r
+vector74: .long _asm_exception_handler\r
+vector75: .long _asm_exception_handler\r
+vector76: .long _asm_exception_handler\r
+vector77: .long _vPIT0InterruptHandler\r
+vector78: .long _asm_exception_handler\r
+vector79: .long _asm_exception_handler\r
+vector7A: .long _asm_exception_handler\r
+vector7B: .long _asm_exception_handler\r
+vector7C: .long _asm_exception_handler\r
+vector7D: .long _asm_exception_handler\r
+vector7E: .long _asm_exception_handler\r
+vector7F: .long _asm_exception_handler \r
+vector80: .long _asm_exception_handler\r
+vector81: .long _asm_exception_handler\r
+vector82: .long _asm_exception_handler\r
+vector83: .long _asm_exception_handler\r
+vector84: .long _asm_exception_handler\r
+vector85: .long _asm_exception_handler\r
+vector86: .long _asm_exception_handler\r
+vector87: .long _asm_exception_handler\r
+vector88: .long _asm_exception_handler\r
+vector89: .long _asm_exception_handler\r
+vector8A: .long _asm_exception_handler\r
+vector8B: .long _asm_exception_handler\r
+vector8C: .long _asm_exception_handler\r
+vector8D: .long _asm_exception_handler\r
+vector8E: .long _asm_exception_handler\r
+vector8F: .long _asm_exception_handler\r
+vector90: .long _asm_exception_handler\r
+vector91: .long _asm_exception_handler\r
+vector92: .long _asm_exception_handler\r
+vector93: .long _asm_exception_handler\r
+vector94: .long _asm_exception_handler\r
+vector95: .long _asm_exception_handler\r
+vector96: .long _asm_exception_handler\r
+vector97: .long _asm_exception_handler\r
+vector98: .long _asm_exception_handler\r
+vector99: .long _asm_exception_handler\r
+vector9A: .long _asm_exception_handler\r
+vector9B: .long _asm_exception_handler\r
+vector9C: .long _asm_exception_handler\r
+vector9D: .long _asm_exception_handler\r
+vector9E: .long _asm_exception_handler\r
+vector9F: .long _asm_exception_handler\r
+vectorA0: .long _asm_exception_handler\r
+vectorA1: .long _asm_exception_handler\r
+vectorA2: .long _asm_exception_handler\r
+vectorA3: .long _asm_exception_handler\r
+vectorA4: .long _asm_exception_handler\r
+vectorA5: .long _asm_exception_handler\r
+vectorA6: .long _asm_exception_handler\r
+vectorA7: .long _asm_exception_handler\r
+vectorA8: .long _asm_exception_handler\r
+vectorA9: .long _asm_exception_handler\r
+vectorAA: .long _asm_exception_handler\r
+vectorAB: .long _asm_exception_handler\r
+vectorAC: .long _asm_exception_handler\r
+vectorAD: .long _asm_exception_handler\r
+vectorAE: .long _asm_exception_handler\r
+vectorAF: .long _asm_exception_handler\r
+vectorB0: .long _asm_exception_handler\r
+vectorB1: .long _asm_exception_handler\r
+vectorB2: .long _asm_exception_handler\r
+vectorB3: .long _asm_exception_handler\r
+vectorB4: .long _asm_exception_handler\r
+vectorB5: .long _asm_exception_handler\r
+vectorB6: .long _asm_exception_handler\r
+vectorB7: .long _asm_exception_handler\r
+vectorB8: .long _asm_exception_handler\r
+vectorB9: .long _asm_exception_handler\r
+vectorBA: .long _asm_exception_handler\r
+vectorBB: .long _asm_exception_handler\r
+vectorBC: .long _asm_exception_handler\r
+vectorBD: .long _asm_exception_handler\r
+vectorBE: .long _asm_exception_handler\r
+vectorBF: .long _asm_exception_handler\r
+\r
+ .org 0x400\r
+\r
+/* \r
+ * CFM Flash Configuration Field \r
+ */\r
+KEY_UPPER: .long 0x00000000\r
+KEY_LOWER: .long 0x00000000\r
+CFMPROT: .long 0x00000000\r
+CFMSACC: .long 0x00000000\r
+CFMDACC: .long 0x00000000\r
+CFMSEC: .long 0x00000000\r
+\r
+\r
+/********************************************************************/\r
+\r
+\r
+\r
+ .end\r
--- /dev/null
+/*\r
+ * File: mcf5xxx.c\r
+ * Purpose: Generic high-level routines for generic ColdFire processors\r
+ *\r
+ * Notes: \r
+ * \r
+ * License: All software covered by license agreement in -\r
+ * docs/Freescale_Software_License.pdf\r
+ */\r
+\r
+#include "common.h"\r
+\r
+/********************************************************************/\r
+\r
+#define EXCEPTFMT "%s -- PC = %#08X\n"\r
+\r
+/********************************************************************/\r
+/*\r
+ * This is the exception handler for all defined exceptions. Most\r
+ * exceptions do nothing, but some of the more important ones are\r
+ * handled to some extent.\r
+ *\r
+ * Called by asm_exception_handler \r
+ */\r
+void \r
+mcf5xxx_exception_handler (void *framep) \r
+{\r
+ switch (MCF5XXX_RD_SF_FORMAT(framep))\r
+ {\r
+ case 4:\r
+ case 5:\r
+ case 6:\r
+ case 7:\r
+ break;\r
+ default:\r
+ printf(EXCEPTFMT,"Illegal stack type", MCF5XXX_SF_PC(framep));\r
+ break;\r
+ }\r
+\r
+ switch (MCF5XXX_RD_SF_VECTOR(framep))\r
+ {\r
+ case 2:\r
+ printf(EXCEPTFMT, "Access Error", MCF5XXX_SF_PC(framep));\r
+ switch (MCF5XXX_RD_SF_FS(framep))\r
+ {\r
+ case 4:\r
+ printf("Error on instruction fetch\n");\r
+ break;\r
+ case 8:\r
+ printf("Error on operand write\n");\r
+ break;\r
+ case 9:\r
+ printf("Attempted write to write-protected space\n");\r
+ break;\r
+ case 12:\r
+ printf("Error on operand read\n");\r
+ break;\r
+ default:\r
+ printf("Reserved Fault Status Encoding\n");\r
+ break;\r
+ }\r
+ break;\r
+ case 3:\r
+ printf(EXCEPTFMT, "Address Error", MCF5XXX_SF_PC(framep));\r
+ switch (MCF5XXX_RD_SF_FS(framep))\r
+ {\r
+ case 4:\r
+ printf("Error on instruction fetch\n");\r
+ break;\r
+ case 8:\r
+ printf("Error on operand write\n");\r
+ break;\r
+ case 9:\r
+ printf("Attempted write to write-protected space\n");\r
+ break;\r
+ case 12:\r
+ printf("Error on operand read\n");\r
+ break;\r
+ default:\r
+ printf("Reserved Fault Status Encoding\n");\r
+ break;\r
+ }\r
+ break;\r
+ case 4:\r
+ printf(EXCEPTFMT, "Illegal instruction", MCF5XXX_SF_PC(framep));\r
+ break;\r
+ case 8:\r
+ printf(EXCEPTFMT, "Privilege violation", MCF5XXX_SF_PC(framep));\r
+ break;\r
+ case 9:\r
+ printf(EXCEPTFMT, "Trace Exception", MCF5XXX_SF_PC(framep));\r
+ break;\r
+ case 10:\r
+ printf(EXCEPTFMT, "Unimplemented A-Line Instruction", \\r
+ MCF5XXX_SF_PC(framep));\r
+ break;\r
+ case 11:\r
+ printf(EXCEPTFMT, "Unimplemented F-Line Instruction", \\r
+ MCF5XXX_SF_PC(framep));\r
+ break;\r
+ case 12:\r
+ printf(EXCEPTFMT, "Debug Interrupt", MCF5XXX_SF_PC(framep));\r
+ break;\r
+ case 14:\r
+ printf(EXCEPTFMT, "Format Error", MCF5XXX_SF_PC(framep));\r
+ break;\r
+ case 15:\r
+ printf(EXCEPTFMT, "Unitialized Interrupt", MCF5XXX_SF_PC(framep));\r
+ break;\r
+ case 24:\r
+ printf(EXCEPTFMT, "Spurious Interrupt", MCF5XXX_SF_PC(framep));\r
+ break;\r
+ case 25:\r
+ case 26:\r
+ case 27:\r
+ case 28:\r
+ case 29:\r
+ case 30:\r
+ case 31:\r
+ printf("Autovector interrupt level %d\n",\r
+ MCF5XXX_RD_SF_VECTOR(framep) - 24);\r
+ break;\r
+ case 32:\r
+ case 33:\r
+ case 34:\r
+ case 35:\r
+ case 36:\r
+ case 37:\r
+ case 38:\r
+ case 39:\r
+ case 40:\r
+ case 41:\r
+ case 42:\r
+ case 43:\r
+ case 44:\r
+ case 45:\r
+ case 46:\r
+ case 47:\r
+ printf("TRAP #%d\n", MCF5XXX_RD_SF_VECTOR(framep) - 32);\r
+ break;\r
+ case 5:\r
+ case 6:\r
+ case 7:\r
+ case 13:\r
+ case 16:\r
+ case 17:\r
+ case 18:\r
+ case 19:\r
+ case 20:\r
+ case 21:\r
+ case 22:\r
+ case 23:\r
+ case 48:\r
+ case 49:\r
+ case 50:\r
+ case 51:\r
+ case 52:\r
+ case 53:\r
+ case 54:\r
+ case 55:\r
+ case 56:\r
+ case 57:\r
+ case 58:\r
+ case 59:\r
+ case 60:\r
+ case 61:\r
+ case 62:\r
+ case 63:\r
+ printf("Reserved: #%d\n", MCF5XXX_RD_SF_VECTOR(framep));\r
+ break;\r
+ default:\r
+ cpu_handle_interrupt(MCF5XXX_RD_SF_VECTOR(framep));\r
+ break;\r
+ }\r
+}\r
+\r
+/********************************************************************/\r
+/*\r
+ * Interpret the reset values of D0 and D1\r
+ *\r
+ * Parameters:\r
+ * d0 - the reset value of data register zero\r
+ * d1 - the reset value of data register one\r
+ */\r
+void\r
+mcf5xxx_interpret_d0d1(int d0, int d1)\r
+{\r
+#ifdef DEBUG_PRINT\r
+ printf("\nColdFire Core Configuration:\n");\r
+ printf("----------------------------\n");\r
+ printf("Processor Family %#02x\n",MCF5XXX_D0_PF(d0));\r
+ printf("ColdFire Core Version: %d\n",MCF5XXX_D0_VER(d0));\r
+ printf("Processor Revision: %d\n",MCF5XXX_D0_REV(d1));\r
+ printf("Bus Width: ");\r
+ switch (MCF5XXX_D1_BUSW(d1))\r
+ {\r
+ case 0:\r
+ printf("32-bit\n");\r
+ break;\r
+ default:\r
+ printf("Reserved\n");\r
+ }\r
+ printf("ISA Version: ");\r
+ switch (MCF5XXX_D0_ISA(d0))\r
+ {\r
+ case 0:\r
+ printf("A\n");\r
+ break;\r
+ case 1:\r
+ printf("B\n");\r
+ break;\r
+ case 2:\r
+ printf("C\n");\r
+ break;\r
+ case 8:\r
+ printf("A+\n");\r
+ break;\r
+ default:\r
+ printf("Reserved\n");\r
+ }\r
+ printf("Debug Version: ");\r
+ switch (MCF5XXX_D0_DEBUG(d0))\r
+ {\r
+ case 0:\r
+ printf("A\n");\r
+ break;\r
+ case 1:\r
+ printf("B\n");\r
+ break;\r
+ case 2:\r
+ printf("C\n");\r
+ break;\r
+ case 3:\r
+ printf("D\n");\r
+ break;\r
+ case 4:\r
+ printf("E\n");\r
+ break;\r
+ case 9:\r
+ printf("B+\n");\r
+ break;\r
+ default :\r
+ printf("Reserved\n");\r
+ }\r
+ printf("MAC: %s\n", MCF5XXX_D0_MAC(d0) ? "Yes" : "No");\r
+ printf("DIV: %s\n", MCF5XXX_D0_DIV(d0) ? "Yes" : "No");\r
+ printf("EMAC: %s\n", MCF5XXX_D0_EMAC(d0) ? "Yes" : "No");\r
+ printf("FPU: %s\n", MCF5XXX_D0_FPU(d0) ? "Yes" : "No");\r
+ printf("MMU: %s\n", MCF5XXX_D0_MMU(d0) ? "Yes" : "No");\r
+ printf("RAM Bank 0 Size: ");\r
+ switch (MCF5XXX_D1_RAM0SIZ(d1))\r
+ {\r
+ case 0:\r
+ case 1:\r
+ case 2:\r
+ case 3:\r
+ printf("None\n");\r
+ break;\r
+ case 4:\r
+ printf("4KB\n");\r
+ break;\r
+ case 5:\r
+ printf("8KB\n");\r
+ break;\r
+ case 6:\r
+ printf("16KB\n");\r
+ break;\r
+ case 7:\r
+ printf("32KB\n");\r
+ break;\r
+ case 8:\r
+ printf("64KB\n");\r
+ break;\r
+ case 9:\r
+ printf("128KB\n");\r
+ break;\r
+ case 10:\r
+ printf("256KB\n");\r
+ break;\r
+ case 11:\r
+ printf("512KB\n");\r
+ break;\r
+ default:\r
+ printf("Reserved\n");\r
+ }\r
+ printf("RAM Bank 1 Size: ");\r
+ switch (MCF5XXX_D1_RAM1SIZ(d1))\r
+ {\r
+ case 0:\r
+ case 1:\r
+ case 2:\r
+ case 3:\r
+ printf("None\n");\r
+ break;\r
+ case 4:\r
+ printf("4KB\n");\r
+ break;\r
+ case 5:\r
+ printf("8KB\n");\r
+ break;\r
+ case 6:\r
+ printf("16KB\n");\r
+ break;\r
+ case 7:\r
+ printf("32KB\n");\r
+ break;\r
+ case 8:\r
+ printf("64KB\n");\r
+ break;\r
+ case 9:\r
+ printf("128KB\n");\r
+ break;\r
+ case 10:\r
+ printf("256KB\n");\r
+ break;\r
+ case 11:\r
+ printf("512KB\n");\r
+ break;\r
+ default:\r
+ printf("Reserved\n");\r
+ }\r
+ printf("ROM Bank 0 Size: ");\r
+ switch (MCF5XXX_D1_ROM0SIZ(d1))\r
+ {\r
+ case 0:\r
+ case 1:\r
+ case 2:\r
+ case 3:\r
+ printf("None\n");\r
+ break;\r
+ case 4:\r
+ printf("4KB\n");\r
+ break;\r
+ case 5:\r
+ printf("8KB\n");\r
+ break;\r
+ case 6:\r
+ printf("16KB\n");\r
+ break;\r
+ case 7:\r
+ printf("32KB\n");\r
+ break;\r
+ case 8:\r
+ printf("64KB\n");\r
+ break;\r
+ case 9:\r
+ printf("128KB\n");\r
+ default:\r
+ printf("Reserved\n");\r
+ }\r
+ printf("ROM Bank 1 Size: ");\r
+ switch (MCF5XXX_D1_ROM1SIZ(d1))\r
+ {\r
+ case 0:\r
+ case 1:\r
+ case 2:\r
+ case 3:\r
+ printf("None\n");\r
+ break;\r
+ case 4:\r
+ printf("4KB\n");\r
+ break;\r
+ case 5:\r
+ printf("8KB\n");\r
+ break;\r
+ case 6:\r
+ printf("16KB\n");\r
+ break;\r
+ case 7:\r
+ printf("32KB\n");\r
+ break;\r
+ case 8:\r
+ printf("64KB\n");\r
+ break;\r
+ case 9:\r
+ printf("128KB\n");\r
+ default:\r
+ printf("Reserved\n");\r
+ }\r
+ printf("Cache Line Size: ");\r
+ switch (MCF5XXX_D1_CL(d1))\r
+ {\r
+ case 0:\r
+ printf("16-byte\n");\r
+ break;\r
+ default:\r
+ printf("Reserved\n");\r
+ }\r
+ printf("I-Cache Associativity: ");\r
+ switch (MCF5XXX_D1_ICA(d1))\r
+ {\r
+ case 0:\r
+ printf("Four-way\n");\r
+ break;\r
+ case 1:\r
+ printf("Direct mapped\n");\r
+ break;\r
+ default:\r
+ printf("Reserved\n");\r
+ }\r
+ printf("D-Cache Associativity: ");\r
+ switch (MCF5XXX_D1_DCA(d1))\r
+ {\r
+ case 0:\r
+ printf("Four-way\n");\r
+ break;\r
+ case 1:\r
+ printf("Direct mapped\n");\r
+ break;\r
+ default:\r
+ printf("Reserved\n");\r
+ }\r
+ printf("I-Cache Size: ");\r
+ switch (MCF5XXX_D1_ICSIZ(d1))\r
+ {\r
+ case 0:\r
+ printf("None\n");\r
+ break;\r
+ case 1:\r
+ printf("512B\n");\r
+ break;\r
+ case 2:\r
+ printf("1KB\n"); \r
+ break;\r
+ case 3:\r
+ printf("2KB\n");\r
+ break;\r
+ case 4:\r
+ printf("4KB\n");\r
+ break;\r
+ case 5:\r
+ printf("8KB\n");\r
+ break;\r
+ case 6:\r
+ printf("16KB\n");\r
+ break;\r
+ case 7:\r
+ printf("32KB\n");\r
+ break;\r
+ case 8:\r
+ printf("64KB\n");\r
+ break;\r
+ default:\r
+ printf("Reserved\n");\r
+ }\r
+ printf("D-Cache Size: ");\r
+ switch (MCF5XXX_D1_DCSIZ(d1))\r
+ {\r
+ case 0:\r
+ printf("None\n");\r
+ break;\r
+ case 1:\r
+ printf("512B\n");\r
+ break;\r
+ case 2:\r
+ printf("1KB\n");\r
+ break;\r
+ case 3:\r
+ printf("2KB\n");\r
+ break;\r
+ case 4:\r
+ printf("4KB\n");\r
+ break;\r
+ case 5:\r
+ printf("8KB\n");\r
+ break;\r
+ case 6:\r
+ printf("16KB\n");\r
+ break;\r
+ case 7:\r
+ printf("32KB\n");\r
+ break;\r
+ case 8:\r
+ printf("64KB\n");\r
+ break;\r
+ default:\r
+ printf("Reserved\n");\r
+ }\r
+ printf("\n");\r
+#else\r
+ /* Remove compiler warnings. */\r
+ ( void ) d0;\r
+ ( void ) d1;\r
+#endif\r
+}\r
+\r
+/********************************************************************/\r
+void\r
+mcf5xxx_irq_enable (void)\r
+{\r
+ asm_set_ipl(0);\r
+}\r
+/********************************************************************/\r
+void\r
+mcf5xxx_irq_disable (void)\r
+{\r
+ asm_set_ipl(7);\r
+}\r
+/********************************************************************/\r
+/*\r
+ * Write new interrupt vector handler into the vector table\r
+ * Return previous handler address\r
+ */ \r
+\r
+ADDRESS\r
+mcf5xxx_set_handler (int vector, ADDRESS new_handler)\r
+{\r
+ ADDRESS old_handler;\r
+ extern uint32 __VECTOR_RAM[];\r
+\r
+ old_handler = (ADDRESS) __VECTOR_RAM[vector];\r
+ __VECTOR_RAM[vector] = (uint32)new_handler;\r
+ return old_handler;\r
+}\r
+\r
+/********************************************************************/\r
--- /dev/null
+/*\r
+ * File: mcf5xxx.h\r
+ * Purpose: Definitions common to all ColdFire processors\r
+ *\r
+ * Notes:\r
+ * \r
+ * License: All software covered by license agreement in -\r
+ * docs/Freescale_Software_License.pdf\r
+ */\r
+\r
+#ifndef _CPU_MCF5XXX_H\r
+#define _CPU_MCF5XXX_H\r
+\r
+/***********************************************************************/\r
+/*\r
+ * Misc. Defines\r
+ */\r
+#ifdef FALSE\r
+#undef FALSE\r
+#endif\r
+#define FALSE (0)\r
+\r
+#ifdef TRUE\r
+#undef TRUE\r
+#endif\r
+#define TRUE (1)\r
+\r
+#ifdef NULL\r
+#undef NULL\r
+#endif\r
+#define NULL (0)\r
+\r
+#ifdef ON\r
+#undef ON\r
+#endif\r
+#define ON (1)\r
+\r
+#ifdef OFF\r
+#undef OFF\r
+#endif\r
+#define OFF (0)\r
+\r
+/***********************************************************************/\r
+/*\r
+ * The basic data types\r
+ */\r
+typedef unsigned char uint8; /* 8 bits */\r
+typedef unsigned short int uint16; /* 16 bits */\r
+typedef unsigned long int uint32; /* 32 bits */\r
+\r
+typedef char int8; /* 8 bits */\r
+typedef short int int16; /* 16 bits */\r
+typedef int int32; /* 32 bits */\r
+\r
+typedef volatile int8 vint8; /* 8 bits */\r
+typedef volatile int16 vint16; /* 16 bits */\r
+typedef volatile int32 vint32; /* 32 bits */\r
+\r
+typedef volatile uint8 vuint8; /* 8 bits */\r
+typedef volatile uint16 vuint16; /* 16 bits */\r
+typedef volatile uint32 vuint32; /* 32 bits */\r
+\r
+/***********************************************************************/\r
+/*\r
+ * Common M68K & ColdFire definitions\r
+ */\r
+#define ADDRESS uint32\r
+#define INSTRUCTION uint16\r
+#define ILLEGAL 0x4AFC\r
+#define CPU_WORD_SIZE 16\r
+\r
+/* Status Register */\r
+#define MCF5XXX_SR_T (0x8000)\r
+#define MCF5XXX_SR_S (0x2000)\r
+#define MCF5XXX_SR_M (0x1000)\r
+#define MCF5XXX_SR_IPL (0x0700)\r
+#define MCF5XXX_SR_IPL_0 (0x0000)\r
+#define MCF5XXX_SR_IPL_1 (0x0100)\r
+#define MCF5XXX_SR_IPL_2 (0x0200)\r
+#define MCF5XXX_SR_IPL_3 (0x0300)\r
+#define MCF5XXX_SR_IPL_4 (0x0400)\r
+#define MCF5XXX_SR_IPL_5 (0x0500)\r
+#define MCF5XXX_SR_IPL_6 (0x0600)\r
+#define MCF5XXX_SR_IPL_7 (0x0700)\r
+#define MCF5XXX_SR_X (0x0010)\r
+#define MCF5XXX_SR_N (0x0008)\r
+#define MCF5XXX_SR_Z (0x0004)\r
+#define MCF5XXX_SR_V (0x0002)\r
+#define MCF5XXX_SR_C (0x0001)\r
+\r
+/* Cache Control Register */\r
+#define MCF5XXX_CACR_CENB (0x80000000)\r
+#define MCF5XXX_CACR_DEC (0x80000000)\r
+#define MCF5XXX_CACR_DW (0x40000000)\r
+#define MCF5XXX_CACR_DESB (0x20000000)\r
+#define MCF5XXX_CACR_CPDI (0x10000000)\r
+#define MCF5XXX_CACR_DDPI (0x10000000)\r
+#define MCF5XXX_CACR_CPD (0x10000000)\r
+#define MCF5XXX_CACR_CFRZ (0x08000000)\r
+#define MCF5XXX_CACR_DHLCK (0x08000000)\r
+#define MCF5XXX_CACR_DDCM_WT (0x00000000)\r
+#define MCF5XXX_CACR_DDCM_CB (0x02000000)\r
+#define MCF5XXX_CACR_DDCM_IP (0x04000000)\r
+#define MCF5XXX_CACR_DDCM_II (0x06000000)\r
+#define MCF5XXX_CACR_CINV (0x01000000)\r
+#define MCF5XXX_CACR_DCINVA (0x01000000)\r
+#define MCF5XXX_CACR_DIDI (0x00800000)\r
+#define MCF5XXX_CACR_DDSP (0x00800000)\r
+#define MCF5XXX_CACR_DISD (0x00400000)\r
+#define MCF5XXX_CACR_INVI (0x00200000)\r
+#define MCF5XXX_CACR_INVD (0x00100000)\r
+#define MCF5XXX_CACR_BEC (0x00080000)\r
+#define MCF5XXX_CACR_BCINVA (0x00040000)\r
+#define MCF5XXX_CACR_IEC (0x00008000)\r
+#define MCF5XXX_CACR_DNFB (0x00002000)\r
+#define MCF5XXX_CACR_IDPI (0x00001000)\r
+#define MCF5XXX_CACR_IHLCK (0x00000800)\r
+#define MCF5XXX_CACR_CEIB (0x00000400)\r
+#define MCF5XXX_CACR_IDCM (0x00000400)\r
+#define MCF5XXX_CACR_DCM_WR (0x00000000)\r
+#define MCF5XXX_CACR_DCM_CB (0x00000100)\r
+#define MCF5XXX_CACR_DCM_IP (0x00000200)\r
+#define MCF5XXX_CACR_DCM (0x00000200)\r
+#define MCF5XXX_CACR_DCM_II (0x00000300)\r
+#define MCF5XXX_CACR_DBWE (0x00000100)\r
+#define MCF5XXX_CACR_ICINVA (0x00000100)\r
+#define MCF5XXX_CACR_IDSP (0x00000080)\r
+#define MCF5XXX_CACR_DWP (0x00000020)\r
+#define MCF5XXX_CACR_EUSP (0x00000020)\r
+#define MCF5XXX_CACR_EUST (0x00000020)\r
+#define MCF5XXX_CACR_DF (0x00000010)\r
+#define MCF5XXX_CACR_CLNF_00 (0x00000000)\r
+#define MCF5XXX_CACR_CLNF_01 (0x00000002)\r
+#define MCF5XXX_CACR_CLNF_10 (0x00000004)\r
+#define MCF5XXX_CACR_CLNF_11 (0x00000006)\r
+\r
+/* Access Control Register */\r
+#define MCF5XXX_ACR_AB(a) ((a)&0xFF000000)\r
+#define MCF5XXX_ACR_AM(a) (((a)&0xFF000000) >> 8)\r
+#define MCF5XXX_ACR_AM_4G (0x00FF0000)\r
+#define MCF5XXX_ACR_AM_2G (0x007F0000)\r
+#define MCF5XXX_ACR_AM_1G (0x003F0000)\r
+#define MCF5XXX_ACR_AM_1024M (0x003F0000)\r
+#define MCF5XXX_ACR_AM_512M (0x001F0000)\r
+#define MCF5XXX_ACR_AM_256M (0x000F0000)\r
+#define MCF5XXX_ACR_AM_128M (0x00070000)\r
+#define MCF5XXX_ACR_AM_64M (0x00030000)\r
+#define MCF5XXX_ACR_AM_32M (0x00010000)\r
+#define MCF5XXX_ACR_AM_16M (0x00000000)\r
+#define MCF5XXX_ACR_EN (0x00008000)\r
+#define MCF5XXX_ACR_SM_USER (0x00000000)\r
+#define MCF5XXX_ACR_SM_SUPER (0x00002000)\r
+#define MCF5XXX_ACR_SM_IGNORE (0x00006000)\r
+#define MCF5XXX_ACR_ENIB (0x00000080)\r
+#define MCF5XXX_ACR_CM (0x00000040)\r
+#define MCF5XXX_ACR_DCM_WR (0x00000000)\r
+#define MCF5XXX_ACR_DCM_CB (0x00000020)\r
+#define MCF5XXX_ACR_DCM_IP (0x00000040)\r
+#define MCF5XXX_ACR_DCM_II (0x00000060)\r
+#define MCF5XXX_ACR_CM (0x00000040)\r
+#define MCF5XXX_ACR_BWE (0x00000020)\r
+#define MCF5XXX_ACR_WP (0x00000004)\r
+\r
+/* RAM Base Address Register */\r
+#define MCF5XXX_RAMBAR_BA(a) ((a)&0xFFFFC000)\r
+#define MCF5XXX_RAMBAR_PRI_00 (0x00000000)\r
+#define MCF5XXX_RAMBAR_PRI_01 (0x00004000)\r
+#define MCF5XXX_RAMBAR_PRI_10 (0x00008000)\r
+#define MCF5XXX_RAMBAR_PRI_11 (0x0000C000)\r
+#define MCF5XXX_RAMBAR_WP (0x00000100)\r
+#define MCF5XXX_RAMBAR_CI (0x00000020)\r
+#define MCF5XXX_RAMBAR_SC (0x00000010)\r
+#define MCF5XXX_RAMBAR_SD (0x00000008)\r
+#define MCF5XXX_RAMBAR_UC (0x00000004)\r
+#define MCF5XXX_RAMBAR_UD (0x00000002)\r
+#define MCF5XXX_RAMBAR_V (0x00000001)\r
+\r
+/* Read macros for D0/D1 reset values */\r
+#define MCF5XXX_D0_PF(x) (((x)&0xFF000000)>>24)\r
+#define MCF5XXX_D0_VER(x) (((x)&0x00F00000)>>20)\r
+#define MCF5XXX_D0_REV(x) (((x)&0x000F0000)>>16)\r
+#define MCF5XXX_D0_MAC(x) ((x)&0x00008000)\r
+#define MCF5XXX_D0_DIV(x) ((x)&0x00004000)\r
+#define MCF5XXX_D0_EMAC(x) ((x)&0x00002000)\r
+#define MCF5XXX_D0_FPU(x) ((x)&0x00001000)\r
+#define MCF5XXX_D0_MMU(x) ((x)&0x00000800)\r
+#define MCF5XXX_D0_ISA(x) (((x)&0x000000F0)>>4)\r
+#define MCF5XXX_D0_DEBUG(x) (((x)&0x0000000F)>>0)\r
+#define MCF5XXX_D1_CL(x) (((x)&0xC0000000)>>30)\r
+#define MCF5XXX_D1_ICA(x) (((x)&0x30000000)>>28)\r
+#define MCF5XXX_D1_ICSIZ(x) (((x)&0x0F000000)>>24)\r
+#define MCF5XXX_D1_RAM0SIZ(x) (((x)&0x00F00000)>>20)\r
+#define MCF5XXX_D1_ROM0SIZ(x) (((x)&0x000F0000)>>16)\r
+#define MCF5XXX_D1_BUSW(x) (((x)&0x0000C000)>>14)\r
+#define MCF5XXX_D1_DCA(x) (((x)&0x00003000)>>12)\r
+#define MCF5XXX_D1_DCSIZ(x) (((x)&0x00000F00)>>8)\r
+#define MCF5XXX_D1_RAM1SIZ(x) (((x)&0x000000F0)>>4)\r
+#define MCF5XXX_D1_ROM1SIZ(x) (((x)&0x0000000F)>>0)\r
+\r
+/***********************************************************************/\r
+/*\r
+ * The ColdFire family of processors has a simplified exception stack\r
+ * frame that looks like the following:\r
+ *\r
+ * 3322222222221111 111111\r
+ * 1098765432109876 5432109876543210\r
+ * 8 +----------------+----------------+\r
+ * | Program Counter |\r
+ * 4 +----------------+----------------+\r
+ * |FS/Fmt/Vector/FS| SR |\r
+ * SP --> 0 +----------------+----------------+\r
+ *\r
+ * The stack self-aligns to a 4-byte boundary at an exception, with\r
+ * the FS/Fmt/Vector/FS field indicating the size of the adjustment\r
+ * (SP += 0,1,2,3 bytes).\r
+ */\r
+#define MCF5XXX_RD_SF_FORMAT(PTR) \\r
+ ((*((uint16 *)(PTR)) >> 12) & 0x00FF)\r
+\r
+#define MCF5XXX_RD_SF_VECTOR(PTR) \\r
+ ((*((uint16 *)(PTR)) >> 2) & 0x00FF)\r
+\r
+#define MCF5XXX_RD_SF_FS(PTR) \\r
+ ( ((*((uint16 *)(PTR)) & 0x0C00) >> 8) | (*((uint16 *)(PTR)) & 0x0003) )\r
+\r
+#define MCF5XXX_SF_SR(PTR) *((uint16 *)(PTR)+1)\r
+#define MCF5XXX_SF_PC(PTR) *((uint32 *)(PTR)+1)\r
+\r
+/********************************************************************/\r
+/*\r
+ * Functions provided in mcf5xxx.s\r
+ */\r
+int asm_set_ipl (uint32);\r
+void mcf5xxx_exe_wdebug (void *);\r
+void mcf5xxx_wr_sr (uint32);\r
+void mcf5xxx_wr_cacr (uint32);\r
+void mcf5xxx_wr_asid (uint32);\r
+void mcf5xxx_wr_acr0 (uint32);\r
+void mcf5xxx_wr_acr1 (uint32);\r
+void mcf5xxx_wr_acr2 (uint32);\r
+void mcf5xxx_wr_acr3 (uint32);\r
+void mcf5xxx_wr_mmubar (uint32);\r
+void mcf5xxx_wr_other_a7 (uint32);\r
+void mcf5xxx_wr_other_sp (uint32);\r
+void mcf5xxx_wr_vbr (uint32);\r
+void mcf5xxx_wr_macsr (uint32);\r
+void mcf5xxx_wr_mask (uint32);\r
+void mcf5xxx_wr_acc0 (uint32);\r
+void mcf5xxx_wr_accext01 (uint32);\r
+void mcf5xxx_wr_accext23 (uint32);\r
+void mcf5xxx_wr_acc1 (uint32);\r
+void mcf5xxx_wr_acc2 (uint32);\r
+void mcf5xxx_wr_acc3 (uint32);\r
+void mcf5xxx_wr_pc (uint32);\r
+void mcf5xxx_wr_rombar0 (uint32);\r
+void mcf5xxx_wr_rombar1 (uint32);\r
+void mcf5xxx_wr_rambar0 (uint32);\r
+void mcf5xxx_wr_rambar1 (uint32);\r
+void mcf5xxx_wr_mpcr (uint32);\r
+void mcf5xxx_wr_secmbar (uint32);\r
+void mcf5xxx_wr_mbar1 (uint32);\r
+void mcf5xxx_wr_mbar (uint32);\r
+void mcf5xxx_wr_mbar0 (uint32);\r
+void mcf5xxx_move_line (ADDRESS, ADDRESS);\r
+\r
+/*\r
+ * Functions provided in mcf5xxx.c\r
+ */\r
+void mcf5xxx_exception_handler (void *);\r
+void mcf5xxx_interpret_d0d1 (int, int);\r
+void mcf5xxx_irq_enable (void);\r
+void mcf5xxx_irq_disable (void);\r
+ADDRESS mcf5xxx_set_handler (int, ADDRESS);\r
+\r
+/*\r
+ * Functions provided by processor specific C file\r
+ */\r
+void cpu_handle_interrupt (int);\r
+\r
+/********************************************************************/\r
+\r
+#endif /* _CPU_MCF5XXX_H */\r
+\r
--- /dev/null
+/*\r
+ * File: mcf5xxx.s\r
+ * Purpose: Lowest level routines for all ColdFire processors.\r
+ *\r
+ * Notes: \r
+ *\r
+ * License: All software covered by license agreement in -\r
+ * docs/Freescale_Software_License.pdf\r
+ */\r
+\r
+#define mcf5xxx_exception_handler _mcf5xxx_exception_handler\r
+\r
+ .extern mcf5xxx_exception_handler\r
+\r
+ .global asm_exception_handler\r
+ .global _asm_exception_handler\r
+ .global asm_set_ipl\r
+ .global _asm_set_ipl\r
+ .global mcf5xxx_exe_wdebug\r
+ .global _mcf5xxx_exe_wdebug\r
+ .global mcf5xxx_move_line //added by Mac\r
+ .global _mcf5xxx_move_line //added by Mac\r
+ .global mcf5xxx_wr_cacr\r
+ .global _mcf5xxx_wr_cacr\r
+ .global mcf5xxx_wr_asid\r
+ .global _mcf5xxx_wr_asid\r
+ .global mcf5xxx_wr_acr0\r
+ .global _mcf5xxx_wr_acr0\r
+ .global mcf5xxx_wr_acr1\r
+ .global _mcf5xxx_wr_acr1\r
+ .global mcf5xxx_wr_acr2\r
+ .global _mcf5xxx_wr_acr2\r
+ .global mcf5xxx_wr_acr3\r
+ .global _mcf5xxx_wr_acr3\r
+ .global mcf5xxx_wr_mmubar\r
+ .global _mcf5xxx_wr_mmubar\r
+ .global mcf5xxx_wr_other_a7\r
+ .global _mcf5xxx_wr_other_a7\r
+ .global mcf5xxx_wr_vbr\r
+ .global _mcf5xxx_wr_vbr\r
+ .global mcf5xxx_wr_macsr\r
+ .global _mcf5xxx_wr_macsr\r
+ .global mcf5xxx_wr_mask\r
+ .global _mcf5xxx_wr_mask\r
+ .global mcf5xxx_wr_acc0\r
+ .global _mcf5xxx_wr_acc0\r
+ .global mcf5xxx_wr_accext01\r
+ .global _mcf5xxx_wr_accext01\r
+ .global mcf5xxx_wr_accext23\r
+ .global _mcf5xxx_wr_accext23\r
+ .global mcf5xxx_wr_acc1\r
+ .global _mcf5xxx_wr_acc1\r
+ .global mcf5xxx_wr_acc2\r
+ .global _mcf5xxx_wr_acc2\r
+ .global mcf5xxx_wr_acc3\r
+ .global _mcf5xxx_wr_acc3\r
+ .global mcf5xxx_wr_sr\r
+ .global _mcf5xxx_wr_sr\r
+ .global mcf5xxx_wr_pc\r
+ .global _mcf5xxx_wr_pc\r
+ .global mcf5xxx_wr_rombar0\r
+ .global _mcf5xxx_wr_rombar0\r
+ .global mcf5xxx_wr_rombar1\r
+ .global _mcf5xxx_wr_rombar1\r
+ .global mcf5xxx_wr_rambar0\r
+ .global _mcf5xxx_wr_rambar0\r
+ .global mcf5xxx_wr_rambar1\r
+ .global _mcf5xxx_wr_rambar1\r
+ .global mcf5xxx_wr_mpcr\r
+ .global _mcf5xxx_wr_mpcr\r
+ .global mcf5xxx_wr_secmbar\r
+ .global _mcf5xxx_wr_secmbar\r
+ .global mcf5xxx_wr_mbar\r
+ .global _mcf5xxx_wr_mbar\r
+\r
+ .text\r
+\r
+/********************************************************************\r
+ * This routine is the lowest-level exception handler.\r
+ */\r
+ \r
+asm_exception_handler:\r
+_asm_exception_handler:\r
+ lea -16(SP),SP\r
+ movem.l D0-D1/A0-A1,(SP)\r
+ lea 16(SP),A1\r
+ move.l A1,-(SP)\r
+ jsr mcf5xxx_exception_handler\r
+ lea 4(SP),SP\r
+ movem.l (SP),D0-D1/A0-A1\r
+ lea 16(SP),SP\r
+ rte\r
+\r
+/********************************************************************/\r
+/*\r
+ * This routines changes the IPL to the value passed into the routine.\r
+ * It also returns the old IPL value back.\r
+ * Calling convention from C:\r
+ * old_ipl = asm_set_ipl(new_ipl);\r
+ * For the Diab Data C compiler, it passes return value thru D0.\r
+ * Note that only the least significant three bits of the passed\r
+ * value are used.\r
+ */\r
+\r
+asm_set_ipl:\r
+_asm_set_ipl:\r
+ link A6,#-8\r
+ movem.l D6-D7,(SP)\r
+\r
+ move.w SR,D7 /* current sr */\r
+\r
+ move.l D7,D0 /* prepare return value */\r
+ andi.l #0x0700,D0 /* mask out IPL */\r
+ lsr.l #8,D0 /* IPL */\r
+\r
+ move.l 8(A6),D6 /* get argument */\r
+ andi.l #0x07,D6 /* least significant three bits */\r
+ lsl.l #8,D6 /* move over to make mask */\r
+\r
+ andi.l #0x0000F8FF,D7 /* zero out current IPL */\r
+ or.l D6,D7 /* place new IPL in sr */\r
+ move.w D7,SR\r
+\r
+ movem.l (SP),D6-D7\r
+ lea 8(SP),SP\r
+ unlk A6\r
+ rts\r
+\r
+/********************************************************************/\r
+/*\r
+ * These routines execute special ColdFire instructions\r
+ */\r
+\r
+mcf5xxx_exe_wdebug:\r
+_mcf5xxx_exe_wdebug:\r
+ move.l 4(sp),a0\r
+ wdebug.l (a0)\r
+ rts \r
+ \r
+ mcf5xxx_move_line:\r
+_mcf5xxx_move_line:\r
+ lea.l -24(sp),sp\r
+ movem.l d0-d3/a0-a1,(sp) \r
+ movea.l 28(sp),a0 /* source in a0 */\r
+ movea.l 32(sp),a1 /* destination in a1 */\r
+ movem.l (a0),d0-d3 /* move line from source */\r
+ movem.l d0-d3,(a1) /* move line to destination */\r
+ movem.l (sp),d0-d3/a0-a1\r
+ lea.l 24(sp),sp\r
+ rts\r
+ \r
+ \r
+/********************************************************************/\r
+/*\r
+ * These routines write to the special purpose registers in the ColdFire\r
+ * core. Since these registers are write-only in the supervisor model,\r
+ * no corresponding read routines exist.\r
+ */\r
+ \r
+mcf5xxx_wr_sr:\r
+_mcf5xxx_wr_sr:\r
+ move.l 4(SP),D0\r
+ move.w D0,SR\r
+ rts\r
+ \r
+mcf5xxx_wr_cacr:\r
+_mcf5xxx_wr_cacr:\r
+ move.l 4(SP),D0\r
+ .long 0x4e7b0002 /* movec d0,cacr */\r
+ nop\r
+ rts\r
+\r
+mcf5xxx_wr_asid:\r
+_mcf5xxx_wr_asid:\r
+ move.l 4(SP),D0\r
+ .long 0x4e7b0003 /* movec d0,asid */\r
+ nop\r
+ rts\r
+\r
+mcf5xxx_wr_acr0:\r
+_mcf5xxx_wr_acr0:\r
+ move.l 4(SP),D0\r
+ .long 0x4e7b0004 /* movec d0,ACR0 */\r
+ nop\r
+ rts\r
+\r
+mcf5xxx_wr_acr1:\r
+_mcf5xxx_wr_acr1:\r
+ move.l 4(SP),D0\r
+ .long 0x4e7b0005 /* movec d0,ACR1 */\r
+ nop\r
+ rts\r
+\r
+mcf5xxx_wr_acr2:\r
+_mcf5xxx_wr_acr2:\r
+ move.l 4(SP),D0\r
+ .long 0x4e7b0006 /* movec d0,ACR2 */\r
+ nop\r
+ rts\r
+\r
+mcf5xxx_wr_acr3:\r
+_mcf5xxx_wr_acr3:\r
+ move.l 4(SP),D0\r
+ .long 0x4e7b0007 /* movec d0,ACR3 */\r
+ nop\r
+ rts\r
+\r
+mcf5xxx_wr_mmubar:\r
+_mcf5xxx_wr_mmubar:\r
+ move.l 4(SP),D0\r
+ .long 0x4e7b0008 /* movec d0,MBAR */\r
+ nop\r
+ rts\r
+\r
+mcf5xxx_wr_other_a7:\r
+_mcf5xxx_wr_other_a7:\r
+ move.l 4(SP),D0\r
+ .long 0x4e7b0800 /* movec d0,OTHER_A7 */\r
+ nop\r
+ rts\r
+ \r
+mcf5xxx_wr_vbr:\r
+_mcf5xxx_wr_vbr:\r
+ move.l 4(SP),D0\r
+ .long 0x4e7b0801 /* movec d0,VBR */\r
+ nop\r
+ rts\r
+\r
+mcf5xxx_wr_macsr:\r
+_mcf5xxx_wr_macsr:\r
+ move.l 4(SP),D0\r
+ .long 0x4e7b0804 /* movec d0,MACSR */\r
+ nop\r
+ rts\r
+\r
+mcf5xxx_wr_mask:\r
+_mcf5xxx_wr_mask:\r
+ move.l 4(SP),D0\r
+ .long 0x4e7b0805 /* movec d0,MASK */\r
+ nop\r
+ rts\r
+\r
+mcf5xxx_wr_acc0:\r
+_mcf5xxx_wr_acc0:\r
+ move.l 4(SP),D0\r
+ .long 0x4e7b0806 /* movec d0,ACC0 */\r
+ nop\r
+ rts\r
+\r
+mcf5xxx_wr_accext01:\r
+_mcf5xxx_wr_accext01:\r
+ move.l 4(SP),D0\r
+ .long 0x4e7b0807 /* movec d0,ACCEXT01 */\r
+ nop\r
+ rts\r
+\r
+mcf5xxx_wr_accext23:\r
+_mcf5xxx_wr_accext23:\r
+ move.l 4(SP),D0\r
+ .long 0x4e7b0808 /* movec d0,ACCEXT23 */\r
+ nop\r
+ rts\r
+\r
+mcf5xxx_wr_acc1:\r
+_mcf5xxx_wr_acc1:\r
+ move.l 4(SP),D0\r
+ .long 0x4e7b0809 /* movec d0,ACC1 */\r
+ nop\r
+ rts\r
+\r
+mcf5xxx_wr_acc2:\r
+_mcf5xxx_wr_acc2:\r
+ move.l 4(SP),D0\r
+ .long 0x4e7b080A /* movec d0,ACC2 */\r
+ nop\r
+ rts\r
+\r
+mcf5xxx_wr_acc3:\r
+_mcf5xxx_wr_acc3:\r
+ move.l 4(SP),D0\r
+ .long 0x4e7b080B /* movec d0,ACC3 */\r
+ nop\r
+ rts\r
+\r
+mcf5xxx_wr_pc:\r
+_mcf5xxx_wr_pc:\r
+ move.l 4(SP),D0\r
+ .long 0x4e7b080F /* movec d0,PC */\r
+ nop\r
+ rts\r
+\r
+mcf5xxx_wr_rombar0:\r
+_mcf5xxx_wr_rombar0:\r
+ move.l 4(SP),D0\r
+ .long 0x4e7b0C00 /* movec d0,ROMBAR0 */\r
+ nop\r
+ rts\r
+\r
+mcf5xxx_wr_rombar1:\r
+_mcf5xxx_wr_rombar1:\r
+ move.l 4(SP),D0\r
+ .long 0x4e7b0C01 /* movec d0,ROMBAR1 */\r
+ nop\r
+ rts\r
+\r
+mcf5xxx_wr_rambar0:\r
+_mcf5xxx_wr_rambar0:\r
+ move.l 4(SP),D0\r
+ .long 0x4e7b0C04 /* movec d0,RAMBAR0 */\r
+ nop\r
+ rts\r
+\r
+mcf5xxx_wr_rambar1:\r
+_mcf5xxx_wr_rambar1:\r
+ move.l 4(SP),D0\r
+ .long 0x4e7b0C05 /* movec d0,RAMBAR1 */\r
+ nop\r
+ rts\r
+\r
+mcf5xxx_wr_mpcr:\r
+_mcf5xxx_wr_mpcr:\r
+ move.l 4(SP),D0\r
+ .long 0x4e7b0C0C /* movec d0,MPCR */\r
+ nop\r
+ rts\r
+\r
+mcf5xxx_wr_secmbar:\r
+_mcf5xxx_wr_secmbar:\r
+ move.l 4(SP),D0\r
+ .long 0x4e7b0C0E /* movec d0,MBAR1 */\r
+ nop\r
+ rts\r
+\r
+mcf5xxx_wr_mbar:\r
+_mcf5xxx_wr_mbar:\r
+ move.l 4(SP),D0\r
+ .long 0x4e7b0C0F /* movec d0,MBAR0 */\r
+ nop\r
+ rts\r
+\r
+/********************************************************************/\r
+ .end\r
--- /dev/null
+# NOTE: The debugger uses the Illegal Instruction Vector to stop.\r
+# A small subroutine is written at the location VBR+0x408-VBR+0x40B\r
+# to handle the exception. The Illegal Instruction Vector in\r
+# the the vector table at VBR+0x10 is then pointed to it. When the\r
+# debugger encounters an illegal instruction, it jumps to this \r
+# subroutine, which ends with an RTE, then exits.\r
+# Do not overwrite this area of memory otherwise the debugger may not \r
+# exit properly.\r
+# */\r
+\r
+MEMORY\r
+{\r
+ vectorflash(RX) : ORIGIN = 0x00000000, LENGTH = 0x00000418\r
+\r
+ flash (RX) : ORIGIN = 0x00000420, LENGTH = 0x0007FC00\r
+ vectorram(RWX) : ORIGIN = 0x20000000, LENGTH = 0x00000400\r
+ sram (RWX) : ORIGIN = 0x20000400, LENGTH = 0x0000FA00\r
+ ipsbar (RWX) : ORIGIN = 0x40000000, LENGTH = 0x0\r
+}\r
+\r
+SECTIONS \r
+{\r
+ .ipsbar : {} > ipsbar\r
+ \r
+ .vectorflash :\r
+ {\r
+ mcf5225x_vectors.s (.text)\r
+ } > vectorflash\r
+ \r
+ .flash :\r
+ {\r
+ *(.text)\r
+ . = ALIGN(0x10);\r
+ *(.rodata)\r
+\r
+ ___DATA_ROM = .;\r
+ } > flash\r
+ \r
+ .data : AT(___DATA_ROM) \r
+ {\r
+ ___DATA_RAM = . ;\r
+\r
+ *(.exception) \r
+ . = ALIGN(0x10); \r
+ __exception_table_start__ = .;\r
+ EXCEPTION\r
+ __exception_table_end__ = .;\r
+\r
+ ___sinit__ = .;\r
+ STATICINIT\r
+\r
+ *(.data)\r
+ *(.relocate_code)\r
+ . = ALIGN (0x10);\r
+ ___DATA_END = .;\r
+\r
+ __START_SDATA = .;\r
+ *(.sdata)\r
+\r
+ . = ALIGN (0x10);\r
+ __END_SDATA = .;\r
+\r
+ __SDA_BASE = .;\r
+ . = ALIGN(0x10);\r
+ } > sram\r
+\r
+ .bss :\r
+ {\r
+ . = ALIGN(0x10);\r
+ __START_SBSS = .;\r
+ *(.sbss)\r
+ *(SCOMMON)\r
+ __END_SBSS = .;\r
+\r
+ . = ALIGN(0x10);\r
+ __START_BSS = .;\r
+ *(.bss)\r
+ *(COMMON)\r
+ __END_BSS = .; \r
+ ___BSS_START = __START_SBSS;\r
+ ___BSS_END = __END_BSS;\r
+ . = ALIGN(0x10);\r
+\r
+ } >> sram\r
+\r
+ ___FLASH = ADDR(.vectorflash);\r
+ ___FLASH_SIZE = 0x00080000;\r
+ ___SRAM = 0x20000400;\r
+ ___SRAM_SIZE = 0x0000FC00;\r
+\r
+ ___VECTOR_RAM = 0x20000000;\r
+ ___IPSBAR = ADDR(.ipsbar);\r
+\r
+ ___SP_SIZE = 0x200;\r
+ ___HEAP_START = .;\r
+ ___HEAP_END = ___SRAM + ___SRAM_SIZE - ___SP_SIZE;\r
+ ___SP_END = ___HEAP_END;\r
+ ___SP_INIT = ___SP_END + ___SP_SIZE;\r
+ \r
+ ___heap_addr = ___HEAP_START;\r
+ ___heap_size = ___HEAP_END - ___HEAP_START ;\r
+ __SP_INIT = ___SP_INIT;\r
+}\r
--- /dev/null
+/*\r
+ * Copyright (c) 2001-2003 Swedish Institute of Computer Science.\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. The name of the author may not be used to endorse or promote products\r
+ * derived from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT\r
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\r
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT\r
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING\r
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY\r
+ * OF SUCH DAMAGE.\r
+ *\r
+ * This file is part of the lwIP TCP/IP stack.\r
+ *\r
+ * Author: Adam Dunkels <adam@sics.se>\r
+ *\r
+ */\r
+#ifndef __LWIPOPTS_H__\r
+#define __LWIPOPTS_H__\r
+\r
+#define TCPIP_THREAD_NAME "tcp/ip"\r
+#define TCPIP_THREAD_STACKSIZE 350\r
+#define TCPIP_THREAD_PRIO 2\r
+\r
+#define DEFAULT_THREAD_STACKSIZE 200\r
+#define DEFAULT_THREAD_PRIO 1\r
+\r
+#define ETH_PAD_SIZE 2\r
+\r
+#define NOT_LWIP_DEBUG 0\r
+#define DBG_TYPES_ON 0x00\r
+#define LWIP_DBG_TYPES_ON LWIP_DBG_OFF\r
+\r
+#define ETHARP_DEBUG LWIP_DBG_OFF\r
+#define NETIF_DEBUG LWIP_DBG_OFF\r
+#define PBUF_DEBUG LWIP_DBG_OFF\r
+#define API_LIB_DEBUG LWIP_DBG_OFF\r
+#define API_MSG_DEBUG LWIP_DBG_OFF\r
+#define SOCKETS_DEBUG LWIP_DBG_OFF\r
+#define ICMP_DEBUG LWIP_DBG_OFF\r
+#define IGMP_DEBUG LWIP_DBG_OFF\r
+#define INET_DEBUG LWIP_DBG_OFF\r
+#define IP_DEBUG LWIP_DBG_OFF\r
+#define IP_REASS_DEBUG LWIP_DBG_OFF\r
+#define RAW_DEBUG LWIP_DBG_OFF\r
+#define MEM_DEBUG LWIP_DBG_OFF\r
+#define MEMP_DEBUG LWIP_DBG_OFF\r
+#define SYS_DEBUG LWIP_DBG_OFF\r
+#define TCP_DEBUG LWIP_DBG_OFF\r
+#define TCP_INPUT_DEBUG LWIP_DBG_OFF\r
+#define TCP_FR_DEBUG LWIP_DBG_OFF\r
+#define TCP_RTO_DEBUG LWIP_DBG_OFF\r
+#define TCP_CWND_DEBUG LWIP_DBG_OFF\r
+#define TCP_WND_DEBUG LWIP_DBG_OFF\r
+#define TCP_OUTPUT_DEBUG LWIP_DBG_OFF\r
+#define TCP_RST_DEBUG LWIP_DBG_OFF\r
+#define TCP_QLEN_DEBUG LWIP_DBG_OFF\r
+#define UDP_DEBUG LWIP_DBG_OFF\r
+#define TCPIP_DEBUG LWIP_DBG_OFF\r
+#define PPP_DEBUG LWIP_DBG_OFF\r
+#define SLIP_DEBUG LWIP_DBG_OFF\r
+#define DHCP_DEBUG LWIP_DBG_OFF\r
+#define AUTOIP_DEBUG LWIP_DBG_OFF\r
+#define SNMP_MSG_DEBUG LWIP_DBG_OFF\r
+#define SNMP_MIB_DEBUG LWIP_DBG_OFF\r
+#define DNS_DEBUG LWIP_DBG_OFF\r
+#define LWIP_NOASSERT 0\r
+\r
+#define ETHARP_TRUST_IP_MAC 0\r
+#define LWIP_UDP 0\r
+\r
+/**\r
+ * SYS_LIGHTWEIGHT_PROT==1: if you want inter-task protection for certain\r
+ * critical regions during buffer allocation, deallocation and memory\r
+ * allocation and deallocation.\r
+ */\r
+#define SYS_LIGHTWEIGHT_PROT 1\r
+\r
+/*\r
+ ------------------------------------\r
+ ---------- Memory options ----------\r
+ ------------------------------------\r
+*/\r
+\r
+/**\r
+ * MEM_ALIGNMENT: should be set to the alignment of the CPU\r
+ * 4 byte alignment -> #define MEM_ALIGNMENT 4\r
+ * 2 byte alignment -> #define MEM_ALIGNMENT 2\r
+ */\r
+#define MEM_ALIGNMENT 4\r
+\r
+/**\r
+ * MEM_SIZE: the size of the heap memory. If the application will send\r
+ * a lot of data that needs to be copied, this should be set high.\r
+ */\r
+#define MEM_SIZE (8*1024)\r
+\r
+/*\r
+ ------------------------------------------------\r
+ ---------- Internal Memory Pool Sizes ----------\r
+ ------------------------------------------------\r
+*/\r
+/**\r
+ * MEMP_NUM_PBUF: the number of memp struct pbufs (used for PBUF_ROM and PBUF_REF).\r
+ * If the application sends a lot of data out of ROM (or other static memory),\r
+ * this should be set high.\r
+ */\r
+#define MEMP_NUM_PBUF 20\r
+\r
+/**\r
+ * MEMP_NUM_TCP_PCB: the number of simulatenously active TCP connections.\r
+ * (requires the LWIP_TCP option)\r
+ */\r
+#define MEMP_NUM_TCP_PCB 10\r
+\r
+/**\r
+ * MEMP_NUM_TCP_SEG: the number of simultaneously queued TCP segments.\r
+ * (requires the LWIP_TCP option)\r
+ */\r
+#define MEMP_NUM_TCP_SEG 8\r
+\r
+/**\r
+ * MEMP_NUM_SYS_TIMEOUT: the number of simulateously active timeouts.\r
+ * (requires NO_SYS==0)\r
+ */\r
+#define MEMP_NUM_SYS_TIMEOUT 5\r
+\r
+/**\r
+ * MEMP_NUM_NETBUF: the number of struct netbufs.\r
+ * (only needed if you use the sequential API, like api_lib.c)\r
+ */\r
+#define MEMP_NUM_NETBUF 4\r
+\r
+/**\r
+ * PBUF_POOL_SIZE: the number of buffers in the pbuf pool.\r
+ */\r
+#define PBUF_POOL_SIZE 4\r
+\r
+\r
+/*\r
+ ----------------------------------\r
+ ---------- Pbuf options ----------\r
+ ----------------------------------\r
+*/\r
+\r
+/**\r
+ * PBUF_POOL_BUFSIZE: the size of each pbuf in the pbuf pool. The default is\r
+ * designed to accomodate single full size TCP frame in one pbuf, including\r
+ * TCP_MSS, IP header, and link header.\r
+ */\r
+#define PBUF_POOL_BUFSIZE 1500\r
+\r
+/*\r
+ ---------------------------------\r
+ ---------- TCP options ----------\r
+ ---------------------------------\r
+*/\r
+/**\r
+ * LWIP_TCP==1: Turn on TCP.\r
+ */\r
+#define LWIP_TCP 1\r
+\r
+/* TCP Maximum segment size. */\r
+#define TCP_MSS 1500\r
+\r
+/* TCP sender buffer space (bytes). */\r
+#define TCP_SND_BUF 1500\r
+\r
+/**\r
+ * TCP_WND: The size of a TCP window.\r
+ */\r
+#define TCP_WND 1500\r
+\r
+/**\r
+ * TCP_SYNMAXRTX: Maximum number of retransmissions of SYN segments.\r
+ */\r
+#define TCP_SYNMAXRTX 4\r
+\r
+/*\r
+ ---------------------------------\r
+ ---------- RAW options ----------\r
+ ---------------------------------\r
+*/\r
+/**\r
+ * LWIP_RAW==1: Enable application layer to hook into the IP layer itself.\r
+ */\r
+#define LWIP_RAW 0\r
+\r
+\r
+/*\r
+ ------------------------------------\r
+ ---------- Socket options ----------\r
+ ------------------------------------\r
+*/\r
+/**\r
+ * LWIP_SOCKET==1: Enable Socket API (require to use sockets.c)\r
+ */\r
+#define LWIP_SOCKET 0\r
+\r
+\r
+/*\r
+ ----------------------------------------\r
+ ---------- Statistics options ----------\r
+ ----------------------------------------\r
+*/\r
+/**\r
+ * LWIP_STATS==1: Enable statistics collection in lwip_stats.\r
+ */\r
+#define LWIP_STATS 0\r
+\r
+/*\r
+ ----------------------------------\r
+ ---------- DHCP options ----------\r
+ ----------------------------------\r
+*/\r
+/**\r
+ * LWIP_DHCP==1: Enable DHCP module.\r
+ */\r
+#define LWIP_DHCP 0\r
+\r
+\r
+#define LWIP_PROVIDE_ERRNO 0\r
+\r
+#endif /* __LWIPOPTS_H__ */\r
--- /dev/null
+/*\r
+ FreeRTOS.org V5.1.0 - Copyright (C) 2003-2008 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS.org distribution.\r
+\r
+ FreeRTOS.org is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS.org is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS.org; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS.org, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section\r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ ***************************************************************************\r
+ * *\r
+ * SAVE TIME AND MONEY! We can port FreeRTOS.org to your own hardware, *\r
+ * and even write all or part of your application on your behalf. *\r
+ * See http://www.OpenRTOS.com for details of the services we provide to *\r
+ * expedite your project. *\r
+ * *\r
+ ***************************************************************************\r
+ ***************************************************************************\r
+\r
+ Please ensure to read the configuration and relevant port sections of the\r
+ online documentation.\r
+\r
+ http://www.FreeRTOS.org - Documentation, latest information, license and\r
+ contact details.\r
+\r
+ http://www.SafeRTOS.com - A version that is certified for use in safety\r
+ critical systems.\r
+\r
+ http://www.OpenRTOS.com - Commercial support, development, porting,\r
+ licensing and training services.\r
+*/\r
+\r
+\r
+/*\r
+ * Creates all the demo application tasks, then starts the scheduler. The WEB\r
+ * documentation provides more details of the standard demo application tasks.\r
+ * In addition to the standard demo tasks, the following tasks and tests are\r
+ * defined and/or created within this file:\r
+ *\r
+ * "Web server" - Very basic demonstration of the lwIP stack. The WEB server\r
+ * simply generates a page that shows the current state of all the tasks within\r
+ * the system, including the high water mark of each task stack. The high water\r
+ * mark is displayed as the amount of stack that has never been used, so the\r
+ * closer the value is to zero the closer the task has come to overflowing its\r
+ * stack. The IP address and net mask are set within FreeRTOSConfig.h.\r
+ *\r
+ * "Check" task - This only executes every five seconds but has a high priority\r
+ * to ensure it gets processor time. Its main function is to check that all the\r
+ * standard demo tasks are still operational. While no errors have been\r
+ * discovered the check task will toggle an LED every 5 seconds - the toggle\r
+ * rate increasing to 500ms being a visual indication that at least one task has\r
+ * reported unexpected behaviour.\r
+ *\r
+ * "Reg test" tasks - These fill the registers with known values, then check\r
+ * that each register still contains its expected value. Each task uses\r
+ * different values. The tasks run with very low priority so get preempted very\r
+ * frequently. A register containing an unexpected value is indicative of an\r
+ * error in the context switching mechanism.\r
+ *\r
+ */\r
+\r
+/* Standard includes. */\r
+#include <stdio.h>\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "queue.h"\r
+#include "semphr.h"\r
+\r
+/* Demo app includes. */\r
+#include "BlockQ.h"\r
+#include "death.h"\r
+#include "flash.h"\r
+#include "partest.h"\r
+#include "semtest.h"\r
+#include "PollQ.h"\r
+#include "GenQTest.h"\r
+#include "QPeek.h"\r
+#include "recmutex.h"\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The time between cycles of the 'check' functionality - as described at the\r
+top of this file. */\r
+#define mainNO_ERROR_PERIOD ( ( portTickType ) 5000 / portTICK_RATE_MS )\r
+\r
+/* The rate at which the LED controlled by the 'check' task will flash should an\r
+error have been detected. */\r
+#define mainERROR_PERIOD ( ( portTickType ) 500 / portTICK_RATE_MS )\r
+\r
+/* The LED controlled by the 'check' task. */\r
+#define mainCHECK_LED ( 3 )\r
+\r
+/* ComTest constants - there is no free LED for the comtest tasks. */\r
+#define mainCOM_TEST_BAUD_RATE ( ( unsigned portLONG ) 19200 )\r
+#define mainCOM_TEST_LED ( 5 )\r
+\r
+/* Task priorities. */\r
+#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 )\r
+#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 )\r
+#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+#define mainINTEGER_TASK_PRIORITY ( tskIDLE_PRIORITY )\r
+#define mainGEN_QUEUE_TASK_PRIORITY ( tskIDLE_PRIORITY )\r
+#define mainWEB_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+\r
+/*\r
+ * Configure the hardware for the demo.\r
+ */\r
+static void prvSetupHardware( void );\r
+\r
+/*\r
+ * Implements the 'check' task functionality as described at the top of this\r
+ * file.\r
+ */\r
+static void prvCheckTask( void *pvParameters );\r
+\r
+/*\r
+ * Implement the 'Reg test' functionality as described at the top of this file.\r
+ */\r
+static void vRegTest1Task( void *pvParameters );\r
+static void vRegTest2Task( void *pvParameters );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Counters used to detect errors within the reg test tasks. */\r
+static volatile unsigned portLONG ulRegTest1Counter = 0x11111111, ulRegTest2Counter = 0x22222222;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+int main( void )\r
+{\r
+extern void vBasicWEBServer( void *pv );\r
+\r
+ /* Setup the hardware ready for this demo. */\r
+ prvSetupHardware();\r
+ ( void )sys_thread_new("HTTPD", vBasicWEBServer, NULL, 320, mainWEB_TASK_PRIORITY );\r
+\r
+ /* Start the standard demo tasks. */\r
+ vStartLEDFlashTasks( tskIDLE_PRIORITY );\r
+ vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );\r
+ vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );\r
+ vStartGenericQueueTasks( mainGEN_QUEUE_TASK_PRIORITY );\r
+ vStartQueuePeekTasks();\r
+ vStartRecursiveMutexTasks();\r
+ vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );\r
+\r
+ /* Start the reg test tasks - defined in this file. */\r
+ xTaskCreate( vRegTest1Task, ( signed portCHAR * ) "Reg1", configMINIMAL_STACK_SIZE, ( void * ) &ulRegTest1Counter, tskIDLE_PRIORITY, NULL );\r
+ xTaskCreate( vRegTest2Task, ( signed portCHAR * ) "Reg2", configMINIMAL_STACK_SIZE, ( void * ) &ulRegTest2Counter, tskIDLE_PRIORITY, NULL );\r
+\r
+ /* Create the check task. */\r
+ xTaskCreate( prvCheckTask, ( signed portCHAR * ) "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );\r
+\r
+ /* The suicide tasks must be created last as they need to know how many\r
+ tasks were running prior to their creation in order to ascertain whether\r
+ or not the correct/expected number of tasks are running at any given time. */\r
+ vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY );\r
+\r
+ /* Start the scheduler. */\r
+ vTaskStartScheduler();\r
+\r
+ /* Will only get here if there was insufficient memory to create the idle\r
+ task. */\r
+ for( ;; )\r
+ {\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvCheckTask( void *pvParameters )\r
+{\r
+unsigned ulTicksToWait = mainNO_ERROR_PERIOD, ulError = 0, ulLastRegTest1Count = 0, ulLastRegTest2Count = 0;\r
+portTickType xLastExecutionTime;\r
+\r
+ ( void ) pvParameters;\r
+\r
+ /* Initialise the variable used to control our iteration rate prior to\r
+ its first use. */\r
+ xLastExecutionTime = xTaskGetTickCount();\r
+\r
+ for( ;; )\r
+ {\r
+ /* Wait until it is time to run the tests again. */\r
+ vTaskDelayUntil( &xLastExecutionTime, ulTicksToWait );\r
+\r
+ /* Has an error been found in any task? */\r
+ if( xAreGenericQueueTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulError |= 0x01UL;\r
+ }\r
+\r
+ if( xAreQueuePeekTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulError |= 0x02UL;\r
+ }\r
+\r
+ if( xAreBlockingQueuesStillRunning() != pdTRUE )\r
+ {\r
+ ulError |= 0x04UL;\r
+ }\r
+\r
+ if( xAreSemaphoreTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulError |= 0x20UL;\r
+ }\r
+\r
+ if( xArePollingQueuesStillRunning() != pdTRUE )\r
+ {\r
+ ulError |= 0x40UL;\r
+ }\r
+\r
+ if( xIsCreateTaskStillRunning() != pdTRUE )\r
+ {\r
+ ulError |= 0x80UL;\r
+ }\r
+\r
+ if( xAreRecursiveMutexTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulError |= 0x200UL;\r
+ }\r
+\r
+ if( ulLastRegTest1Count == ulRegTest1Counter )\r
+ {\r
+ ulError |= 0x1000UL;\r
+ }\r
+\r
+ if( ulLastRegTest2Count == ulRegTest2Counter )\r
+ {\r
+ ulError |= 0x1000UL;\r
+ }\r
+\r
+ ulLastRegTest1Count = ulRegTest1Counter;\r
+ ulLastRegTest2Count = ulRegTest2Counter;\r
+\r
+ /* If an error has been found then increase our cycle rate, and in so\r
+ going increase the rate at which the check task LED toggles. */\r
+ if( ulError != 0 )\r
+ {\r
+ ulTicksToWait = mainERROR_PERIOD;\r
+ }\r
+\r
+ /* Toggle the LED each itteration. */\r
+ vParTestToggleLED( mainCHECK_LED );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void prvSetupHardware( void )\r
+{\r
+ portDISABLE_INTERRUPTS();\r
+\r
+ /* Setup the port used to toggle LEDs. */\r
+ vParTestInitialise();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationStackOverflowHook( xTaskHandle *pxTask, signed portCHAR *pcTaskName )\r
+{\r
+ /* This will get called if a stack overflow is detected during the context\r
+ switch. Set configCHECK_FOR_STACK_OVERFLOWS to 2 to also check for stack\r
+ problems within nested interrupts, but only do this for debug purposes as\r
+ it will increase the context switch time. */\r
+\r
+ ( void ) pxTask;\r
+ ( void ) pcTaskName;\r
+\r
+ for( ;; )\r
+ {\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void vRegTest1Task( void *pvParameters )\r
+{\r
+ /* Sanity check - did we receive the parameter expected? */\r
+ if( pvParameters != &ulRegTest1Counter )\r
+ {\r
+ /* Change here so the check task can detect that an error occurred. */\r
+ for( ;; )\r
+ {\r
+ }\r
+ }\r
+\r
+ /* Set all the registers to known values, then check that each retains its\r
+ expected value - as described at the top of this file. If an error is\r
+ found then the loop counter will no longer be incremented allowing the check\r
+ task to recognise the error. */\r
+ asm volatile ( "reg_test_1_start: \n\t"\r
+ " moveq #1, d0 \n\t"\r
+ " moveq #2, d1 \n\t"\r
+ " moveq #3, d2 \n\t"\r
+ " moveq #4, d3 \n\t"\r
+ " moveq #5, d4 \n\t"\r
+ " moveq #6, d5 \n\t"\r
+ " moveq #7, d6 \n\t"\r
+ " moveq #8, d7 \n\t"\r
+ " move #9, a0 \n\t"\r
+ " move #10, a1 \n\t"\r
+ " move #11, a2 \n\t"\r
+ " move #12, a3 \n\t"\r
+ " move #13, a4 \n\t"\r
+ " move #14, a5 \n\t"\r
+ " move #15, a6 \n\t"\r
+ " \n\t"\r
+ " cmpi.l #1, d0 \n\t"\r
+ " bne reg_test_1_error \n\t"\r
+ " cmpi.l #2, d1 \n\t"\r
+ " bne reg_test_1_error \n\t"\r
+ " cmpi.l #3, d2 \n\t"\r
+ " bne reg_test_1_error \n\t"\r
+ " cmpi.l #4, d3 \n\t"\r
+ " bne reg_test_1_error \n\t"\r
+ " cmpi.l #5, d4 \n\t"\r
+ " bne reg_test_1_error \n\t"\r
+ " cmpi.l #6, d5 \n\t"\r
+ " bne reg_test_1_error \n\t"\r
+ " cmpi.l #7, d6 \n\t"\r
+ " bne reg_test_1_error \n\t"\r
+ " cmpi.l #8, d7 \n\t"\r
+ " bne reg_test_1_error \n\t"\r
+ " move a0, d0 \n\t"\r
+ " cmpi.l #9, d0 \n\t"\r
+ " bne reg_test_1_error \n\t"\r
+ " move a1, d0 \n\t"\r
+ " cmpi.l #10, d0 \n\t"\r
+ " bne reg_test_1_error \n\t"\r
+ " move a2, d0 \n\t"\r
+ " cmpi.l #11, d0 \n\t"\r
+ " bne reg_test_1_error \n\t"\r
+ " move a3, d0 \n\t"\r
+ " cmpi.l #12, d0 \n\t"\r
+ " bne reg_test_1_error \n\t"\r
+ " move a4, d0 \n\t"\r
+ " cmpi.l #13, d0 \n\t"\r
+ " bne reg_test_1_error \n\t"\r
+ " move a5, d0 \n\t"\r
+ " cmpi.l #14, d0 \n\t"\r
+ " bne reg_test_1_error \n\t"\r
+ " move a6, d0 \n\t"\r
+ " cmpi.l #15, d0 \n\t"\r
+ " bne reg_test_1_error \n\t"\r
+ " move ulRegTest1Counter, d0 \n\t"\r
+ " addq #1, d0 \n\t"\r
+ " move d0, ulRegTest1Counter \n\t"\r
+ " bra reg_test_1_start \n\t"\r
+ "reg_test_1_error: \n\t"\r
+ " bra reg_test_1_error \n\t"\r
+ );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void vRegTest2Task( void *pvParameters )\r
+{\r
+ /* Sanity check - did we receive the parameter expected? */\r
+ if( pvParameters != &ulRegTest2Counter )\r
+ {\r
+ /* Change here so the check task can detect that an error occurred. */\r
+ for( ;; )\r
+ {\r
+ }\r
+ }\r
+\r
+ /* Set all the registers to known values, then check that each retains its\r
+ expected value - as described at the top of this file. If an error is\r
+ found then the loop counter will no longer be incremented allowing the check\r
+ task to recognise the error. */\r
+ asm volatile ( "reg_test_2_start: \n\t"\r
+ " moveq #10, d0 \n\t"\r
+ " moveq #20, d1 \n\t"\r
+ " moveq #30, d2 \n\t"\r
+ " moveq #40, d3 \n\t"\r
+ " moveq #50, d4 \n\t"\r
+ " moveq #60, d5 \n\t"\r
+ " moveq #70, d6 \n\t"\r
+ " moveq #80, d7 \n\t"\r
+ " move #90, a0 \n\t"\r
+ " move #100, a1 \n\t"\r
+ " move #110, a2 \n\t"\r
+ " move #120, a3 \n\t"\r
+ " move #130, a4 \n\t"\r
+ " move #140, a5 \n\t"\r
+ " move #150, a6 \n\t"\r
+ " \n\t"\r
+ " cmpi.l #10, d0 \n\t"\r
+ " bne reg_test_2_error \n\t"\r
+ " cmpi.l #20, d1 \n\t"\r
+ " bne reg_test_2_error \n\t"\r
+ " cmpi.l #30, d2 \n\t"\r
+ " bne reg_test_2_error \n\t"\r
+ " cmpi.l #40, d3 \n\t"\r
+ " bne reg_test_2_error \n\t"\r
+ " cmpi.l #50, d4 \n\t"\r
+ " bne reg_test_2_error \n\t"\r
+ " cmpi.l #60, d5 \n\t"\r
+ " bne reg_test_2_error \n\t"\r
+ " cmpi.l #70, d6 \n\t"\r
+ " bne reg_test_2_error \n\t"\r
+ " cmpi.l #80, d7 \n\t"\r
+ " bne reg_test_2_error \n\t"\r
+ " move a0, d0 \n\t"\r
+ " cmpi.l #90, d0 \n\t"\r
+ " bne reg_test_2_error \n\t"\r
+ " move a1, d0 \n\t"\r
+ " cmpi.l #100, d0 \n\t"\r
+ " bne reg_test_2_error \n\t"\r
+ " move a2, d0 \n\t"\r
+ " cmpi.l #110, d0 \n\t"\r
+ " bne reg_test_2_error \n\t"\r
+ " move a3, d0 \n\t"\r
+ " cmpi.l #120, d0 \n\t"\r
+ " bne reg_test_2_error \n\t"\r
+ " move a4, d0 \n\t"\r
+ " cmpi.l #130, d0 \n\t"\r
+ " bne reg_test_2_error \n\t"\r
+ " move a5, d0 \n\t"\r
+ " cmpi.l #140, d0 \n\t"\r
+ " bne reg_test_2_error \n\t"\r
+ " move a6, d0 \n\t"\r
+ " cmpi.l #150, d0 \n\t"\r
+ " bne reg_test_2_error \n\t"\r
+ " move ulRegTest1Counter, d0 \n\t"\r
+ " addq #1, d0 \n\t"\r
+ " move d0, ulRegTest2Counter \n\t"\r
+ " bra reg_test_2_start \n\t"\r
+ "reg_test_2_error: \n\t"\r
+ " bra reg_test_2_error \n\t"\r
+ );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+\r
+\r
--- /dev/null
+/*\r
+ Copyright 2001, 2002 Georges Menie (www.menie.org)\r
+ stdarg version contributed by Christian Ettinger\r
+\r
+ This program is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU Lesser General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ This program is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU Lesser General Public License for more details.\r
+\r
+ You should have received a copy of the GNU Lesser General Public License\r
+ along with this program; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+*/\r
+\r
+/*\r
+ putchar is the only external dependency for this file,\r
+ if you have a working putchar, leave it commented out.\r
+ If not, uncomment the define below and\r
+ replace outbyte(c) by your own function call.\r
+\r
+*/\r
+\r
+#define putchar(c) c\r
+\r
+#include <stdarg.h>\r
+\r
+static void printchar(char **str, int c)\r
+{\r
+ //extern int putchar(int c);\r
+ \r
+ if (str) {\r
+ **str = (char)c;\r
+ ++(*str);\r
+ }\r
+ else\r
+ { \r
+ (void)putchar(c);\r
+ }\r
+}\r
+\r
+#define PAD_RIGHT 1\r
+#define PAD_ZERO 2\r
+\r
+static int prints(char **out, const char *string, int width, int pad)\r
+{\r
+ register int pc = 0, padchar = ' ';\r
+\r
+ if (width > 0) {\r
+ register int len = 0;\r
+ register const char *ptr;\r
+ for (ptr = string; *ptr; ++ptr) ++len;\r
+ if (len >= width) width = 0;\r
+ else width -= len;\r
+ if (pad & PAD_ZERO) padchar = '0';\r
+ }\r
+ if (!(pad & PAD_RIGHT)) {\r
+ for ( ; width > 0; --width) {\r
+ printchar (out, padchar);\r
+ ++pc;\r
+ }\r
+ }\r
+ for ( ; *string ; ++string) {\r
+ printchar (out, *string);\r
+ ++pc;\r
+ }\r
+ for ( ; width > 0; --width) {\r
+ printchar (out, padchar);\r
+ ++pc;\r
+ }\r
+\r
+ return pc;\r
+}\r
+\r
+/* the following should be enough for 32 bit int */\r
+#define PRINT_BUF_LEN 12\r
+\r
+static int printi(char **out, int i, int b, int sg, int width, int pad, int letbase)\r
+{\r
+ char print_buf[PRINT_BUF_LEN];\r
+ register char *s;\r
+ register int t, neg = 0, pc = 0;\r
+ register unsigned int u = (unsigned int)i;\r
+\r
+ if (i == 0) {\r
+ print_buf[0] = '0';\r
+ print_buf[1] = '\0';\r
+ return prints (out, print_buf, width, pad);\r
+ }\r
+\r
+ if (sg && b == 10 && i < 0) {\r
+ neg = 1;\r
+ u = (unsigned int)-i;\r
+ }\r
+\r
+ s = print_buf + PRINT_BUF_LEN-1;\r
+ *s = '\0';\r
+\r
+ while (u) {\r
+ t = (int)u % b;\r
+ if( t >= 10 )\r
+ t += letbase - '0' - 10;\r
+ *--s = (char)(t + '0');\r
+ u /= b;\r
+ }\r
+\r
+ if (neg) {\r
+ if( width && (pad & PAD_ZERO) ) {\r
+ printchar (out, '-');\r
+ ++pc;\r
+ --width;\r
+ }\r
+ else {\r
+ *--s = '-';\r
+ }\r
+ }\r
+\r
+ return pc + prints (out, s, width, pad);\r
+}\r
+\r
+static int print( char **out, const char *format, va_list args )\r
+{\r
+ register int width, pad;\r
+ register int pc = 0;\r
+ char scr[2];\r
+\r
+ for (; *format != 0; ++format) {\r
+ if (*format == '%') {\r
+ ++format;\r
+ width = pad = 0;\r
+ if (*format == '\0') break;\r
+ if (*format == '%') goto out;\r
+ if (*format == '-') {\r
+ ++format;\r
+ pad = PAD_RIGHT;\r
+ }\r
+ while (*format == '0') {\r
+ ++format;\r
+ pad |= PAD_ZERO;\r
+ }\r
+ for ( ; *format >= '0' && *format <= '9'; ++format) {\r
+ width *= 10;\r
+ width += *format - '0';\r
+ }\r
+ if( *format == 's' ) {\r
+ register char *s = (char *)va_arg( args, int );\r
+ pc += prints (out, s?s:"(null)", width, pad);\r
+ continue;\r
+ }\r
+ if( *format == 'd' ) {\r
+ pc += printi (out, va_arg( args, int ), 10, 1, width, pad, 'a');\r
+ continue;\r
+ }\r
+ if( *format == 'x' ) {\r
+ pc += printi (out, va_arg( args, int ), 16, 0, width, pad, 'a');\r
+ continue;\r
+ }\r
+ if( *format == 'X' ) {\r
+ pc += printi (out, va_arg( args, int ), 16, 0, width, pad, 'A');\r
+ continue;\r
+ }\r
+ if( *format == 'u' ) {\r
+ pc += printi (out, va_arg( args, int ), 10, 0, width, pad, 'a');\r
+ continue;\r
+ }\r
+ if( *format == 'c' ) {\r
+ /* char are converted to int then pushed on the stack */\r
+ scr[0] = (char)va_arg( args, int );\r
+ scr[1] = '\0';\r
+ pc += prints (out, scr, width, pad);\r
+ continue;\r
+ }\r
+ }\r
+ else {\r
+ out:\r
+ printchar (out, *format);\r
+ ++pc;\r
+ }\r
+ }\r
+ if (out) **out = '\0';\r
+ va_end( args );\r
+ return pc;\r
+}\r
+\r
+int printf(const char *format, ...)\r
+{\r
+ va_list args;\r
+ \r
+ va_start( args, format );\r
+ return print( 0, format, args );\r
+}\r
+\r
+int sprintf(char *out, const char *format, ...)\r
+{\r
+ va_list args;\r
+ \r
+ va_start( args, format );\r
+ return print( &out, format, args );\r
+}\r
+\r
+\r
+int snprintf( char *buf, unsigned int count, const char *format, ... )\r
+{\r
+ va_list args;\r
+ \r
+ ( void ) count;\r
+ \r
+ va_start( args, format );\r
+ return print( &buf, format, args );\r
+}\r
+\r
+\r
+#ifdef TEST_PRINTF\r
+int main(void)\r
+{\r
+ char *ptr = "Hello world!";\r
+ char *np = 0;\r
+ int i = 5;\r
+ unsigned int bs = sizeof(int)*8;\r
+ int mi;\r
+ char buf[80];\r
+\r
+ mi = (1 << (bs-1)) + 1;\r
+ printf("%s\n", ptr);\r
+ printf("printf test\n");\r
+ printf("%s is null pointer\n", np);\r
+ printf("%d = 5\n", i);\r
+ printf("%d = - max int\n", mi);\r
+ printf("char %c = 'a'\n", 'a');\r
+ printf("hex %x = ff\n", 0xff);\r
+ printf("hex %02x = 00\n", 0);\r
+ printf("signed %d = unsigned %u = hex %x\n", -3, -3, -3);\r
+ printf("%d %s(s)%", 0, "message");\r
+ printf("\n");\r
+ printf("%d %s(s) with %%\n", 0, "message");\r
+ sprintf(buf, "justif: \"%-10s\"\n", "left"); printf("%s", buf);\r
+ sprintf(buf, "justif: \"%10s\"\n", "right"); printf("%s", buf);\r
+ sprintf(buf, " 3: %04d zero padded\n", 3); printf("%s", buf);\r
+ sprintf(buf, " 3: %-4d left justif.\n", 3); printf("%s", buf);\r
+ sprintf(buf, " 3: %4d right justif.\n", 3); printf("%s", buf);\r
+ sprintf(buf, "-3: %04d zero padded\n", -3); printf("%s", buf);\r
+ sprintf(buf, "-3: %-4d left justif.\n", -3); printf("%s", buf);\r
+ sprintf(buf, "-3: %4d right justif.\n", -3); printf("%s", buf);\r
+\r
+ return 0;\r
+}\r
+\r
+/*\r
+ * if you compile this file with\r
+ * gcc -Wall $(YOUR_C_OPTIONS) -DTEST_PRINTF -c printf.c\r
+ * you will get a normal warning:\r
+ * printf.c:214: warning: spurious trailing `%' in format\r
+ * this line is testing an invalid % at the end of the format string.\r
+ *\r
+ * this should display (on 32bit int machine) :\r
+ *\r
+ * Hello world!\r
+ * printf test\r
+ * (null) is null pointer\r
+ * 5 = 5\r
+ * -2147483647 = - max int\r
+ * char a = 'a'\r
+ * hex ff = ff\r
+ * hex 00 = 00\r
+ * signed -3 = unsigned 4294967293 = hex fffffffd\r
+ * 0 message(s)\r
+ * 0 message(s) with %\r
+ * justif: "left "\r
+ * justif: " right"\r
+ * 3: 0003 zero padded\r
+ * 3: 3 left justif.\r
+ * 3: 3 right justif.\r
+ * -3: -003 zero padded\r
+ * -3: -3 left justif.\r
+ * -3: -3 right justif.\r
+ */\r
+\r
+#endif\r
+\r
+\r
+/* To keep linker happy. */\r
+int write( int i, char* c, int n)\r
+{\r
+ (void)i;\r
+ (void)n;\r
+ (void)c;\r
+ return 0;\r
+}\r
+\r
--- /dev/null
+//------------------------------------------------------------------------\r
+// Readme.txt\r
+//------------------------------------------------------------------------\r
+This project is configure to get you up and running quickly using \r
+CodeWarrior with the Freescale MCF52259 board.\r
+\r
+This project provides full support for the selected board.\r
+The created project provides Standard IO Support through console and terminal window.\r
+\r
+Sample code for the following language:\r
+- C\r
+\r
+\r
+//------------------------------------------------------------------------\r
+// Memory Maps\r
+//------------------------------------------------------------------------\r
+The Hardware has the following memory map:\r
+\r
+# MCF52259 Derivative Memory map definitions from linker command files:\r
+# __IPSBAR, __RAMBAR, __RAMBAR_SIZE, __FLASHBAR, __FLASHBAR_SIZE linker\r
+# symbols must be defined in the linker command file.\r
+\r
+# Memory Mapped Registers (IPSBAR= 0x40000000)\r
+ ___IPSBAR = 0x40000000;\r
+\r
+# 32 Kbytes Internal SRAM\r
+ ___RAMBAR = 0x20000000;\r
+ ___RAMBAR_SIZE = 0x00008000;\r
+\r
+# 512 KByte Internal Flash Memory\r
+ ___FLASHBAR = 0x00000000;\r
+ ___FLASHBAR_SIZE = 0x00080000;\r
+\r
+\r
+\r
+//------------------------------------------------------------------------\r
+// Project Structure\r
+//------------------------------------------------------------------------\r
+The project generated contains various files/groups:\r
+- readme.txt: information for this project\r
+- Sources: application source codes, user customizable startup \r
+ code, uart library, exception table\r
+- Includes: derivative and board header files, ... \r
+- Libs: runtime and libs \r
+- Project Settings: linker command files for the different build \r
+ targets, the initialization and memory configuration files for \r
+ the hardware debugging, the common startup code, etc...\r
+ \r
+//------------------------------------------------------------------------\r
+// Build Targets\r
+//------------------------------------------------------------------------\r
+- CONSOLE_INTERNAL_RAM:\r
+This project target is setup to load and debug code from internal RAM.\r
+It should be used during your application development.\r
+The application outputs to the CodeWarrior's console window.\r
+\r
+- INTERNAL_RAM:\r
+This project target is setup to load and debug code from internal RAM.\r
+It should be used during your application development.\r
+This is the very basic project that outputs to the UART.\r
+You needs to connect a Terminal Program to see the output.\r
+\r
+- INTERNAL_FLASH:\r
+This project target is setup to load and debug code in Internal FLASH.\r
+This is the very basic project that outputs to the UART. User needs\r
+to connect the terminal to see the output.\r
+\r
+\r
+\r
+===================================================================\r
+WARNING regarding debugging new project wizard code with CCS-SIM\r
+===================================================================\r
+The CCS-SIM is an instruction set simulator, it does not implement\r
+any peripherals.\r
+The new project generated by the wizard are using startup code \r
+performing some hardware peripheral initializations.\r
+When debugging with the CCS-SIM it might happen that the simulation\r
+stuck on loop using non implemented peripheral register flag as \r
+condition (PLL initialization as example). \r
+In this case, you should either:\r
+- move the PC to next statement\r
+- use a skip point\r
+- define a simulator specific macro which used when define allos you \r
+to comment out the unwanted code in order to debug with CCS-SIM\r
+ \r
+\r
+===================================================================\r
+WARNING regarding code located in RAM\r
+===================================================================\r
+Many possible ColdFire target processors have an external bus, so \r
+you can use large external RAM devices for debugging applications \r
+during development. But some processors do not have an external \r
+bus, so you must accommodate applications in on-chip memory. \r
+Although this on-chip RAM accommodates this CodeWarrior project, \r
+it probably is too small for full development of your application. \r
+Accordingly, for a processor without external bus, you should locate \r
+your applications in flash memory. \r
+\r
+//------------------------------------------------------------------------\r
+// Flashing the code\r
+//------------------------------------------------------------------------\r
+1. Select the appropriate project target and build it\r
+2. Make sure the correct remote connection is selected in the Remote \r
+ Connection debugger panel\r
+3. In the CodeWarrior IDE menu, select Project > Set Default Project \r
+ and select your project\r
+4. In the CodeWarrior IDE menu, select Project > Set Default Target \r
+ and select the project target that has the code you want to flash\r
+5. In the CodeWarrior IDE menu, select Tools > Flash Programmer\r
+6. Go to the flash programmer Target Configuration panel, click Load \r
+ Settings \r
+7. Browse to the <your project location>\cfg sub folder and\r
+ select the flash settings xml file matching your build target \r
+8. Check that Use Custom Settings checkbox is not selected\r
+9. Go to the Erase/Blank Check panel, select the All Sectors option and \r
+ click Erase\r
+10. Go to Program/Verify panel, click Program\r
+11. Your code should now be flashed\r
+\r
+//------------------------------------------------------------------------\r
+// Terminal Settings\r
+//------------------------------------------------------------------------\r
+In case the UART is supported, the terminal should be setup with:\r
+- 19200 bauds,\r
+- 8 data bits,\r
+- no parity,\r
+- 1 stop bit,\r
+- no flow control.\r
+\r
+Please check this file in the project.\r
+\r
+//------------------------------------------------------------------------\r
+// Getting Started\r
+//------------------------------------------------------------------------\r
+To build/debug your project, use the CodeWarrior IDE menu Project > Debug \r
+or press F5. This will launch the debugger. Press again F5 in the \r
+debugger (or the CodeWarrior IDE menu Project > Run) to start the \r
+application. The CodeWarrior IDE menu Project > Break stops the \r
+application.\r
+\r
+//------------------------------------------------------------------------\r
+// Adding your own code\r
+//------------------------------------------------------------------------\r
+Once everything is working as expected, you can begin adding your own code\r
+to the project. Keep in mind that we provide this as an example of how to\r
+get up and running quickly with CodeWarrior. There are certainly other\r
+ways to handle interrupts and set up your linker command file. Feel free\r
+to modify any of the source files provided.\r
+\r
+//------------------------------------------------------------------------\r
+// Additional documentation\r
+//------------------------------------------------------------------------\r
+Read the online documentation provided. In CodeWarrior IDE menu, select\r
+Help > CodeWarrior Help.\r
+\r
+//------------------------------------------------------------------------\r
+// Contacting Freescale\r
+//------------------------------------------------------------------------\r
+For bug reports, technical questions, and suggestions, please use the\r
+forms installed in the Release_Notes folder.\r
--- /dev/null
+/* FILENAME: stdlib.c\r
+ *\r
+ * Functions normally found in a standard C lib.\r
+ *\r
+ * 12/28/2005 - added memcmp and memmove\r
+ *\r
+ * Notes: These functions support ASCII only!!!\r
+ */\r
+\r
+#include "common.h"\r
+#include "stdlib.h"\r
+\r
+/****************************************************************/\r
+int\r
+isspace (int ch)\r
+{\r
+ if ((ch == ' ') || (ch == '\t')) /* \n ??? */\r
+ return TRUE;\r
+ else\r
+ return FALSE;\r
+}\r
+\r
+/****************************************************************/\r
+int\r
+isalnum (int ch)\r
+{\r
+ /* ASCII only */\r
+ if (((ch >= '0') && (ch <= '9')) ||\r
+ ((ch >= 'A') && (ch <= 'Z')) ||\r
+ ((ch >= 'a') && (ch <= 'z')))\r
+ return TRUE;\r
+ else\r
+ return FALSE;\r
+}\r
+\r
+/****************************************************************/\r
+int\r
+isdigit (int ch)\r
+{\r
+ /* ASCII only */\r
+ if ((ch >= '0') && (ch <= '9'))\r
+ return TRUE;\r
+ else\r
+ return FALSE;\r
+}\r
+\r
+/****************************************************************/\r
+int\r
+isupper (int ch)\r
+{\r
+ /* ASCII only */\r
+ if ((ch >= 'A') && (ch <= 'Z'))\r
+ return TRUE;\r
+ else\r
+ return FALSE;\r
+}\r
+\r
+/****************************************************************/\r
+int\r
+strcasecmp (const char *s1, const char *s2)\r
+{\r
+ char c1, c2;\r
+ int result = 0;\r
+\r
+ while (result == 0)\r
+ {\r
+ c1 = *s1++;\r
+ c2 = *s2++;\r
+ if ((c1 >= 'a') && (c1 <= 'z'))\r
+ c1 = (char)(c1 - ' ');\r
+ if ((c2 >= 'a') && (c2 <= 'z'))\r
+ c2 = (char)(c2 - ' ');\r
+ if ((result = (c1 - c2)) != 0)\r
+ break;\r
+ if ((c1 == 0) || (c2 == 0))\r
+ break;\r
+ }\r
+ return result;\r
+}\r
+\r
+\r
+/****************************************************************/\r
+int\r
+stricmp (const char *s1, const char *s2)\r
+{\r
+ return (strcasecmp(s1, s2));\r
+}\r
+\r
+/****************************************************************/\r
+int\r
+strncasecmp (const char *s1, const char *s2, int n)\r
+{\r
+ char c1, c2;\r
+ int k = 0;\r
+ int result = 0;\r
+\r
+ while ( k++ < n )\r
+ {\r
+ c1 = *s1++;\r
+ c2 = *s2++;\r
+ if ((c1 >= 'a') && (c1 <= 'z'))\r
+ c1 = (char)(c1 - ' ');\r
+ if ((c2 >= 'a') && (c2 <= 'z'))\r
+ c2 = (char)(c2 - ' ');\r
+ if ((result = (c1 - c2)) != 0)\r
+ break;\r
+ if ((c1 == 0) || (c2 == 0))\r
+ break;\r
+ }\r
+ return result;\r
+}\r
+\r
+/****************************************************************/\r
+int\r
+strnicmp (const char *s1, const char *s2, int n)\r
+{\r
+ return (strncasecmp(s1, s2, n));\r
+}\r
+\r
+/****************************************************************/\r
+uint32\r
+strtoul (char *str, char **ptr, int base)\r
+{\r
+ unsigned long rvalue = 0;\r
+ int neg = 0;\r
+ int c;\r
+\r
+ /* Validate parameters */\r
+ if ((str != NULL) && (base >= 0) && (base <= 36))\r
+ {\r
+ /* Skip leading white spaces */\r
+ while (isspace(*str))\r
+ {\r
+ ++str;\r
+ }\r
+\r
+ /* Check for notations */\r
+ switch (str[0])\r
+ {\r
+ case '0':\r
+ if (base == 0)\r
+ {\r
+ if ((str[1] == 'x') || (str[1] == 'X'))\r
+ {\r
+ base = 16;\r
+ str += 2;\r
+ }\r
+ else\r
+ {\r
+ base = 8;\r
+ str++;\r
+ }\r
+ }\r
+ break;\r
+ \r
+ case '-':\r
+ neg = 1;\r
+ str++;\r
+ break;\r
+\r
+ case '+':\r
+ str++;\r
+ break;\r
+\r
+ default:\r
+ break;\r
+ }\r
+\r
+ if (base == 0)\r
+ base = 10;\r
+\r
+ /* Valid "digits" are 0..9, A..Z, a..z */\r
+ while (isalnum(c = *str))\r
+ {\r
+ /* Convert char to num in 0..36 */\r
+ if ((c -= ('a' - 10)) < 10) /* 'a'..'z' */\r
+ {\r
+ if ((c += ('a' - 'A')) < 10) /* 'A'..'Z' */\r
+ {\r
+ c += ('A' - '0' - 10); /* '0'..'9' */\r
+ }\r
+ }\r
+\r
+ /* check c against base */\r
+ if (c >= base)\r
+ {\r
+ break;\r
+ }\r
+\r
+ if (neg)\r
+ {\r
+ rvalue = (rvalue * base) - c;\r
+ }\r
+ else\r
+ {\r
+ rvalue = (rvalue * base) + c;\r
+ }\r
+\r
+ ++str;\r
+ }\r
+ }\r
+\r
+ /* Upon exit, 'str' points to the character at which valid info */\r
+ /* STOPS. No chars including and beyond 'str' are used. */\r
+\r
+ if (ptr != NULL)\r
+ *ptr = str;\r
+ \r
+ return rvalue;\r
+ }\r
+\r
+/****************************************************************/\r
+int\r
+atoi (const char *str)\r
+{\r
+ char *s = (char *)str;\r
+ \r
+ return ((int)strtoul(s, NULL, 10));\r
+}\r
+\r
+/****************************************************************/\r
+int\r
+strlen (const char *str)\r
+{\r
+ char *s = (char *)str;\r
+ int len = 0;\r
+\r
+ if (s == NULL)\r
+ return 0;\r
+\r
+ while (*s++ != '\0')\r
+ ++len;\r
+\r
+ return len;\r
+}\r
+\r
+/****************************************************************/\r
+char *\r
+strcat (char *dest, const char *src)\r
+{\r
+ char *dp;\r
+ char *sp = (char *)src;\r
+\r
+ if ((dest != NULL) && (src != NULL))\r
+ {\r
+ dp = &dest[strlen(dest)];\r
+\r
+ while (*sp != '\0')\r
+ {\r
+ *dp++ = *sp++;\r
+ }\r
+ *dp = '\0';\r
+ }\r
+ return dest;\r
+}\r
+\r
+/****************************************************************/\r
+char *\r
+strncat (char *dest, const char *src, int n)\r
+{\r
+ char *dp;\r
+ char *sp = (char *)src;\r
+\r
+ if ((dest != NULL) && (src != NULL) && (n > 0))\r
+ {\r
+ dp = &dest[strlen(dest)];\r
+\r
+ while ((*sp != '\0') && (n-- > 0))\r
+ {\r
+ *dp++ = *sp++;\r
+ }\r
+ *dp = '\0';\r
+ }\r
+ return dest;\r
+}\r
+\r
+/****************************************************************/\r
+char *\r
+strcpy (char *dest, const char *src)\r
+{\r
+ char *dp = (char *)dest;\r
+ char *sp = (char *)src;\r
+\r
+ if ((dest != NULL) && (src != NULL))\r
+ {\r
+ while (*sp != '\0')\r
+ {\r
+ *dp++ = *sp++;\r
+ }\r
+ *dp = '\0';\r
+ }\r
+ return dest;\r
+}\r
+\r
+/****************************************************************/\r
+char *\r
+strncpy (char *dest, const char *src, int n)\r
+{\r
+ char *dp = (char *)dest;\r
+ char *sp = (char *)src;\r
+\r
+ if ((dest != NULL) && (src != NULL) && (n > 0))\r
+ {\r
+ while ((*sp != '\0') && (n-- > 0))\r
+ {\r
+ *dp++ = *sp++;\r
+ }\r
+ *dp = '\0';\r
+ }\r
+ return dest;\r
+}\r
+\r
+/****************************************************************/\r
+int\r
+strcmp (const char *s1, const char *s2)\r
+{\r
+ /* No checks for NULL */\r
+ char *s1p = (char *)s1;\r
+ char *s2p = (char *)s2;\r
+\r
+ while (*s2p != '\0')\r
+ {\r
+ if (*s1p != *s2p)\r
+ break;\r
+\r
+ ++s1p;\r
+ ++s2p;\r
+ }\r
+ return (*s1p - *s2p);\r
+}\r
+\r
+/****************************************************************/\r
+int\r
+strncmp (const char *s1, const char *s2, int n)\r
+{\r
+ /* No checks for NULL */\r
+ char *s1p = (char *)s1;\r
+ char *s2p = (char *)s2;\r
+\r
+ if (n <= 0)\r
+ return 0;\r
+\r
+ while (*s2p != '\0')\r
+ {\r
+ if (*s1p != *s2p)\r
+ break;\r
+\r
+ if (--n == 0)\r
+ break;\r
+\r
+ ++s1p;\r
+ ++s2p;\r
+ }\r
+ return (*s1p - *s2p);\r
+}\r
+\r
+/****************************************************************/\r
+char *\r
+strstr(const char *s1, const char *s2)\r
+{\r
+ char *sp = (char *)s1;\r
+ int len1 = strlen(s1);\r
+ int len2 = strlen(s2);\r
+\r
+ while (len1 >= len2) \r
+ {\r
+ if (strncmp(sp, s2, len2) == 0)\r
+ {\r
+ return (sp);\r
+ }\r
+ ++sp;\r
+ --len1;\r
+ }\r
+\r
+ return (NULL);\r
+}\r
+\r
+/****************************************************************/\r
+char *\r
+strchr(const char *str, int c)\r
+{\r
+ char *sp = (char *)str;\r
+ char ch = (char)(c & 0xff);\r
+\r
+ while (*sp != '\0')\r
+ {\r
+ if (*sp == ch)\r
+ {\r
+ return (sp);\r
+ }\r
+ ++sp;\r
+ }\r
+\r
+ return (NULL);\r
+}\r
+\r
+/****************************************************************/\r
+void *\r
+memcpy (void *dest, const void *src, unsigned n)\r
+{\r
+ unsigned char *dbp = (unsigned char *)dest;\r
+ unsigned char *sbp = (unsigned char *)src;\r
+\r
+ if ((dest != NULL) && (src != NULL) && (n > 0))\r
+ {\r
+ while (n--)\r
+ *dbp++ = *sbp++;\r
+ }\r
+ return dest;\r
+}\r
+\r
+/****************************************************************/\r
+void *\r
+memset (void *s, int c, unsigned n)\r
+{\r
+ /* Not optimized, but very portable */\r
+ unsigned char *sp = (unsigned char *)s;\r
+\r
+ if ((s != NULL) && (n > 0))\r
+ {\r
+ while (n--)\r
+ {\r
+ *sp++ = (unsigned char)c;\r
+ }\r
+ }\r
+ return s;\r
+}\r
+\r
+/****************************************************************/\r
+int\r
+memcmp (const void *s1, const void *s2, unsigned n)\r
+{\r
+ unsigned char *s1p, *s2p;\r
+\r
+ if (s1 && s2 && (n > 0))\r
+ {\r
+ s1p = (unsigned char *)s1;\r
+ s2p = (unsigned char *)s2;\r
+\r
+ while ((--n >= 0) && (*s1p == *s2p))\r
+ {\r
+ if (*s1p != *s2p)\r
+ return (*s1p - *s2p);\r
+ ++s1p;\r
+ ++s2p;\r
+ }\r
+ }\r
+\r
+ return (0);\r
+}\r
+\r
+/****************************************************************/\r
+void *\r
+memmove (void *dest, const void *src, unsigned n)\r
+{\r
+ unsigned char *dbp = (unsigned char *)dest;\r
+ unsigned char *sbp = (unsigned char *)src;\r
+ unsigned char *dend = dbp + n;\r
+ unsigned char *send = sbp + n;\r
+\r
+ if ((dest != NULL) && (src != NULL) && (n > 0))\r
+ {\r
+ /* see if a memcpy would overwrite source buffer */\r
+ if ((sbp < dbp) && (dbp < send))\r
+ {\r
+ while (n--)\r
+ *(--dend) = *(--send);\r
+ }\r
+ else\r
+ {\r
+ while (n--)\r
+ *dbp++ = *sbp++;\r
+ }\r
+ }\r
+\r
+ return dest;\r
+}\r
+\r
+/****************************************************************/\r
--- /dev/null
+/*\r
+ * File: stdlib.h\r
+ * Purpose: Function prototypes for standard library functions\r
+ *\r
+ * Notes:\r
+ */\r
+\r
+#ifndef _STDLIB_H\r
+#define _STDLIB_H\r
+\r
+/********************************************************************\r
+ * Standard library functions\r
+ ********************************************************************/\r
+\r
+int\r
+isspace (int);\r
+\r
+int\r
+isalnum (int);\r
+\r
+int\r
+isdigit (int);\r
+\r
+int\r
+isupper (int);\r
+\r
+int\r
+strcasecmp (const char *, const char *);\r
+\r
+int\r
+strncasecmp (const char *, const char *, int);\r
+\r
+unsigned long\r
+strtoul (char *, char **, int);\r
+\r
+int\r
+strlen (const char *);\r
+\r
+char *\r
+strcat (char *, const char *);\r
+\r
+char *\r
+strncat (char *, const char *, int);\r
+\r
+char *\r
+strcpy (char *, const char *);\r
+\r
+char *\r
+strncpy (char *, const char *, int);\r
+\r
+int\r
+strcmp (const char *, const char *);\r
+\r
+int\r
+strncmp (const char *, const char *, int);\r
+\r
+void *\r
+memcpy (void *, const void *, unsigned);\r
+\r
+void *\r
+memset (void *, int, unsigned);\r
+\r
+void\r
+free (void *);\r
+ \r
+void *\r
+malloc (unsigned);\r
+\r
+#define RAND_MAX 32767\r
+\r
+int\r
+rand (void);\r
+\r
+void\r
+srand (int);\r
+\r
+/********************************************************************/\r
+\r
+#endif\r
projects / freertos / commitdiff