--- /dev/null
+\r
+Microsoft Visual Studio Solution File, Format Version 11.00\r
+# Atmel Studio Solution File, Format Version 11.00\r
+Project("{54F91283-7BC4-4236-8FF9-10F437C3AD48}") = "RTOSDemo", "RTOSDemo.cproj", "{257FE152-8D54-41CA-AFE7-777DE72FE329}"\r
+EndProject\r
+Global\r
+ GlobalSection(SolutionConfigurationPlatforms) = preSolution\r
+ Debug|ARM = Debug|ARM\r
+ Release|ARM = Release|ARM\r
+ EndGlobalSection\r
+ GlobalSection(ProjectConfigurationPlatforms) = postSolution\r
+ {257FE152-8D54-41CA-AFE7-777DE72FE329}.Debug|ARM.ActiveCfg = Debug|ARM\r
+ {257FE152-8D54-41CA-AFE7-777DE72FE329}.Debug|ARM.Build.0 = Debug|ARM\r
+ {257FE152-8D54-41CA-AFE7-777DE72FE329}.Release|ARM.ActiveCfg = Release|ARM\r
+ {257FE152-8D54-41CA-AFE7-777DE72FE329}.Release|ARM.Build.0 = Release|ARM\r
+ EndGlobalSection\r
+ GlobalSection(SolutionProperties) = preSolution\r
+ HideSolutionNode = FALSE\r
+ EndGlobalSection\r
+EndGlobal\r
--- /dev/null
+<?xml version="1.0" encoding="utf-8"?>\r
+<Project xmlns="http://schemas.microsoft.com/developer/msbuild/2003" DefaultTargets="Build">\r
+ <PropertyGroup>\r
+ <SchemaVersion>2.0</SchemaVersion>\r
+ <ProjectVersion>6.1</ProjectVersion>\r
+ <ProjectGuid>{257fe152-8d54-41ca-afe7-777de72fe329}</ProjectGuid>\r
+ <Name>$(MSBuildProjectName)</Name>\r
+ <AssemblyName>$(MSBuildProjectName)</AssemblyName>\r
+ <RootNamespace>$(MSBuildProjectName)</RootNamespace>\r
+ <AsfFrameworkConfig>\r
+ <framework-data>\r
+ <options>\r
+ <option id="common.boards" value="Add" config="" content-id="Atmel.ASF" />\r
+ <option id="common.services.ioport" value="Add" config="" content-id="Atmel.ASF" />\r
+ <option id="sam.components.ethernet_phy.ksz8051mnl" value="Add" config="" content-id="Atmel.ASF" />\r
+ <option id="sam.drivers.gmac" value="Add" config="" content-id="Atmel.ASF" />\r
+ <option id="common.applications.user_application" value="Add" config="" content-id="Atmel.ASF" />\r
+ <option id="sam.utils.cmsis.sam4e.source.template" value="Add" config="" content-id="Atmel.ASF" />\r
+ </options>\r
+ <configurations>\r
+ <configuration key="config.compiler.armgcc.fpu_used" value="yes" default="yes" content-id="Atmel.ASF" />\r
+ <configuration key="config.compiler.armgcc.printf" value="iprintf" default="iprintf" content-id="Atmel.ASF" />\r
+ </configurations>\r
+ <files>\r
+ <file path="src/main.c" framework="" version="" source="common/applications/user_application/main.c" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/config/conf_board.h" framework="" version="" source="common/applications/user_application/sam4e16e_sam4e_ek/config/conf_board.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/config/conf_clock.h" framework="" version="" source="common/applications/user_application/sam4e16e_sam4e_ek/config/conf_clock.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/common/boards/board.h" framework="" version="" source="common/boards/board.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/common/services/clock/genclk.h" framework="" version="" source="common/services/clock/genclk.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/common/services/clock/osc.h" framework="" version="" source="common/services/clock/osc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/common/services/clock/pll.h" framework="" version="" source="common/services/clock/pll.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/common/services/clock/sam4e/genclk.h" framework="" version="" source="common/services/clock/sam4e/genclk.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/common/services/clock/sam4e/osc.h" framework="" version="" source="common/services/clock/sam4e/osc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/common/services/clock/sam4e/pll.h" framework="" version="" source="common/services/clock/sam4e/pll.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/common/services/clock/sam4e/sysclk.c" framework="" version="" source="common/services/clock/sam4e/sysclk.c" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/common/services/clock/sam4e/sysclk.h" framework="" version="" source="common/services/clock/sam4e/sysclk.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/common/services/clock/sysclk.h" framework="" version="" source="common/services/clock/sysclk.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/common/services/ioport/ioport.h" framework="" version="" source="common/services/ioport/ioport.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/common/services/ioport/sam/ioport_pio.h" framework="" version="" source="common/services/ioport/sam/ioport_pio.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/common/utils/interrupt.h" framework="" version="" source="common/utils/interrupt.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/common/utils/interrupt/interrupt_sam_nvic.c" framework="" version="" source="common/utils/interrupt/interrupt_sam_nvic.c" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/common/utils/interrupt/interrupt_sam_nvic.h" framework="" version="" source="common/utils/interrupt/interrupt_sam_nvic.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/common/utils/parts.h" framework="" version="" source="common/utils/parts.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam/boards/sam4e_ek/init.c" framework="" version="" source="sam/boards/sam4e_ek/init.c" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam/boards/sam4e_ek/led.h" framework="" version="" source="sam/boards/sam4e_ek/led.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam/boards/sam4e_ek/sam4e_ek.h" framework="" version="" source="sam/boards/sam4e_ek/sam4e_ek.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam/drivers/pmc/pmc.c" framework="" version="" source="sam/drivers/pmc/pmc.c" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam/drivers/pmc/pmc.h" framework="" version="" source="sam/drivers/pmc/pmc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam/drivers/pmc/sleep.c" framework="" version="" source="sam/drivers/pmc/sleep.c" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam/drivers/pmc/sleep.h" framework="" version="" source="sam/drivers/pmc/sleep.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam/utils/cmsis/sam4e/include/component/acc.h" framework="" version="" source="sam/utils/cmsis/sam4e/include/component/acc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam/utils/cmsis/sam4e/include/component/aes.h" framework="" version="" source="sam/utils/cmsis/sam4e/include/component/aes.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam/utils/cmsis/sam4e/include/component/afec.h" framework="" version="" source="sam/utils/cmsis/sam4e/include/component/afec.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam/utils/cmsis/sam4e/include/component/can.h" framework="" version="" source="sam/utils/cmsis/sam4e/include/component/can.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam/utils/cmsis/sam4e/include/component/chipid.h" framework="" version="" source="sam/utils/cmsis/sam4e/include/component/chipid.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam/utils/cmsis/sam4e/include/component/cmcc.h" framework="" version="" source="sam/utils/cmsis/sam4e/include/component/cmcc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam/utils/cmsis/sam4e/include/component/crccu.h" framework="" version="" source="sam/utils/cmsis/sam4e/include/component/crccu.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam/utils/cmsis/sam4e/include/component/dacc.h" framework="" version="" source="sam/utils/cmsis/sam4e/include/component/dacc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam/utils/cmsis/sam4e/include/component/dmac.h" framework="" version="" source="sam/utils/cmsis/sam4e/include/component/dmac.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam/utils/cmsis/sam4e/include/component/efc.h" framework="" version="" source="sam/utils/cmsis/sam4e/include/component/efc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam/utils/cmsis/sam4e/include/component/gmac.h" framework="" version="" source="sam/utils/cmsis/sam4e/include/component/gmac.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam/utils/cmsis/sam4e/include/component/gpbr.h" framework="" version="" source="sam/utils/cmsis/sam4e/include/component/gpbr.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam/utils/cmsis/sam4e/include/component/hsmci.h" framework="" version="" source="sam/utils/cmsis/sam4e/include/component/hsmci.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam/utils/cmsis/sam4e/include/component/matrix.h" framework="" version="" source="sam/utils/cmsis/sam4e/include/component/matrix.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam/utils/cmsis/sam4e/include/component/pdc.h" framework="" version="" source="sam/utils/cmsis/sam4e/include/component/pdc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam/utils/cmsis/sam4e/include/component/pio.h" framework="" version="" source="sam/utils/cmsis/sam4e/include/component/pio.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam/utils/cmsis/sam4e/include/component/pmc.h" framework="" version="" source="sam/utils/cmsis/sam4e/include/component/pmc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam/utils/cmsis/sam4e/include/component/pwm.h" framework="" version="" source="sam/utils/cmsis/sam4e/include/component/pwm.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam/utils/cmsis/sam4e/include/component/rstc.h" framework="" version="" source="sam/utils/cmsis/sam4e/include/component/rstc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam/utils/cmsis/sam4e/include/component/rswdt.h" framework="" version="" source="sam/utils/cmsis/sam4e/include/component/rswdt.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam/utils/cmsis/sam4e/include/component/rtc.h" framework="" version="" source="sam/utils/cmsis/sam4e/include/component/rtc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam/utils/cmsis/sam4e/include/component/rtt.h" framework="" version="" source="sam/utils/cmsis/sam4e/include/component/rtt.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam/utils/cmsis/sam4e/include/component/smc.h" framework="" version="" source="sam/utils/cmsis/sam4e/include/component/smc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam/utils/cmsis/sam4e/include/component/spi.h" framework="" version="" source="sam/utils/cmsis/sam4e/include/component/spi.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam/utils/cmsis/sam4e/include/component/supc.h" framework="" version="" source="sam/utils/cmsis/sam4e/include/component/supc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam/utils/cmsis/sam4e/include/component/tc.h" framework="" version="" source="sam/utils/cmsis/sam4e/include/component/tc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam/utils/cmsis/sam4e/include/component/twi.h" framework="" version="" source="sam/utils/cmsis/sam4e/include/component/twi.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam/utils/cmsis/sam4e/include/component/uart.h" framework="" version="" source="sam/utils/cmsis/sam4e/include/component/uart.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam/utils/cmsis/sam4e/include/component/udp.h" framework="" version="" source="sam/utils/cmsis/sam4e/include/component/udp.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam/utils/cmsis/sam4e/include/component/usart.h" framework="" version="" source="sam/utils/cmsis/sam4e/include/component/usart.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam/utils/cmsis/sam4e/include/component/wdt.h" framework="" version="" source="sam/utils/cmsis/sam4e/include/component/wdt.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam/utils/cmsis/sam4e/include/instance/acc.h" framework="" version="" source="sam/utils/cmsis/sam4e/include/instance/acc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam/utils/cmsis/sam4e/include/instance/aes.h" framework="" version="" source="sam/utils/cmsis/sam4e/include/instance/aes.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam/utils/cmsis/sam4e/include/instance/afec0.h" framework="" version="" source="sam/utils/cmsis/sam4e/include/instance/afec0.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam/utils/cmsis/sam4e/include/instance/afec1.h" framework="" version="" source="sam/utils/cmsis/sam4e/include/instance/afec1.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam/utils/cmsis/sam4e/include/instance/can0.h" framework="" version="" source="sam/utils/cmsis/sam4e/include/instance/can0.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam/utils/cmsis/sam4e/include/instance/can1.h" framework="" version="" source="sam/utils/cmsis/sam4e/include/instance/can1.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam/utils/cmsis/sam4e/include/instance/chipid.h" framework="" version="" source="sam/utils/cmsis/sam4e/include/instance/chipid.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam/utils/cmsis/sam4e/include/instance/cmcc.h" framework="" version="" source="sam/utils/cmsis/sam4e/include/instance/cmcc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam/utils/cmsis/sam4e/include/instance/crccu.h" framework="" version="" source="sam/utils/cmsis/sam4e/include/instance/crccu.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam/utils/cmsis/sam4e/include/instance/dacc.h" framework="" version="" source="sam/utils/cmsis/sam4e/include/instance/dacc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam/utils/cmsis/sam4e/include/instance/dmac.h" framework="" version="" source="sam/utils/cmsis/sam4e/include/instance/dmac.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam/utils/cmsis/sam4e/include/instance/efc.h" framework="" version="" source="sam/utils/cmsis/sam4e/include/instance/efc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam/utils/cmsis/sam4e/include/instance/gmac.h" framework="" version="" source="sam/utils/cmsis/sam4e/include/instance/gmac.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam/utils/cmsis/sam4e/include/instance/gpbr.h" framework="" version="" source="sam/utils/cmsis/sam4e/include/instance/gpbr.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam/utils/cmsis/sam4e/include/instance/hsmci.h" framework="" version="" source="sam/utils/cmsis/sam4e/include/instance/hsmci.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam/utils/cmsis/sam4e/include/instance/matrix.h" framework="" version="" source="sam/utils/cmsis/sam4e/include/instance/matrix.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam/utils/cmsis/sam4e/include/instance/pioa.h" framework="" version="" source="sam/utils/cmsis/sam4e/include/instance/pioa.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam/utils/cmsis/sam4e/include/instance/piob.h" framework="" version="" source="sam/utils/cmsis/sam4e/include/instance/piob.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam/utils/cmsis/sam4e/include/instance/pioc.h" framework="" version="" source="sam/utils/cmsis/sam4e/include/instance/pioc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam/utils/cmsis/sam4e/include/instance/piod.h" framework="" version="" source="sam/utils/cmsis/sam4e/include/instance/piod.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam/utils/cmsis/sam4e/include/instance/pioe.h" framework="" version="" source="sam/utils/cmsis/sam4e/include/instance/pioe.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam/utils/cmsis/sam4e/include/instance/pmc.h" framework="" version="" source="sam/utils/cmsis/sam4e/include/instance/pmc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam/utils/cmsis/sam4e/include/instance/pwm.h" framework="" version="" source="sam/utils/cmsis/sam4e/include/instance/pwm.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam/utils/cmsis/sam4e/include/instance/rstc.h" framework="" version="" source="sam/utils/cmsis/sam4e/include/instance/rstc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam/utils/cmsis/sam4e/include/instance/rswdt.h" framework="" version="" source="sam/utils/cmsis/sam4e/include/instance/rswdt.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam/utils/cmsis/sam4e/include/instance/rtc.h" framework="" version="" source="sam/utils/cmsis/sam4e/include/instance/rtc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam/utils/cmsis/sam4e/include/instance/rtt.h" framework="" version="" source="sam/utils/cmsis/sam4e/include/instance/rtt.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam/utils/cmsis/sam4e/include/instance/smc.h" framework="" version="" source="sam/utils/cmsis/sam4e/include/instance/smc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam/utils/cmsis/sam4e/include/instance/spi.h" framework="" version="" source="sam/utils/cmsis/sam4e/include/instance/spi.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam/utils/cmsis/sam4e/include/instance/supc.h" framework="" version="" source="sam/utils/cmsis/sam4e/include/instance/supc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam/utils/cmsis/sam4e/include/instance/tc0.h" framework="" version="" source="sam/utils/cmsis/sam4e/include/instance/tc0.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam/utils/cmsis/sam4e/include/instance/tc1.h" framework="" version="" source="sam/utils/cmsis/sam4e/include/instance/tc1.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam/utils/cmsis/sam4e/include/instance/tc2.h" framework="" version="" source="sam/utils/cmsis/sam4e/include/instance/tc2.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam/utils/cmsis/sam4e/include/instance/twi0.h" framework="" version="" source="sam/utils/cmsis/sam4e/include/instance/twi0.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam/utils/cmsis/sam4e/include/instance/twi1.h" framework="" version="" source="sam/utils/cmsis/sam4e/include/instance/twi1.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam/utils/cmsis/sam4e/include/instance/uart0.h" framework="" version="" source="sam/utils/cmsis/sam4e/include/instance/uart0.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam/utils/cmsis/sam4e/include/instance/uart1.h" framework="" version="" source="sam/utils/cmsis/sam4e/include/instance/uart1.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam/utils/cmsis/sam4e/include/instance/udp.h" framework="" version="" source="sam/utils/cmsis/sam4e/include/instance/udp.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam/utils/cmsis/sam4e/include/instance/usart0.h" framework="" version="" source="sam/utils/cmsis/sam4e/include/instance/usart0.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam/utils/cmsis/sam4e/include/instance/usart1.h" framework="" version="" source="sam/utils/cmsis/sam4e/include/instance/usart1.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam/utils/cmsis/sam4e/include/instance/wdt.h" framework="" version="" source="sam/utils/cmsis/sam4e/include/instance/wdt.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/ASF/sam/utils/cmsis/sam4e/include/pio/sam4e16c.h" framework="" version="" source="sam/utils/cmsis/sam4e/include/pio/sam4e16c.h" changed="False" content-id="Atmel.ASF" />\r
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+ <None Include="src\ASF\sam\utils\cmsis\sam4e\include\instance\hsmci.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\sam\utils\cmsis\sam4e\include\instance\matrix.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\sam\utils\cmsis\sam4e\include\instance\pioa.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\sam\utils\cmsis\sam4e\include\instance\piob.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\sam\utils\cmsis\sam4e\include\instance\pioc.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\sam\utils\cmsis\sam4e\include\instance\piod.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\sam\utils\cmsis\sam4e\include\instance\pioe.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\sam\utils\cmsis\sam4e\include\instance\pmc.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\sam\utils\cmsis\sam4e\include\instance\pwm.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\sam\utils\cmsis\sam4e\include\instance\rstc.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\sam\utils\cmsis\sam4e\include\instance\rswdt.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\sam\utils\cmsis\sam4e\include\instance\rtc.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\sam\utils\cmsis\sam4e\include\instance\rtt.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\sam\utils\cmsis\sam4e\include\instance\smc.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\sam\utils\cmsis\sam4e\include\instance\spi.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\sam\utils\cmsis\sam4e\include\instance\supc.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\sam\utils\cmsis\sam4e\include\instance\tc0.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\sam\utils\cmsis\sam4e\include\instance\tc1.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\sam\utils\cmsis\sam4e\include\instance\tc2.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\sam\utils\cmsis\sam4e\include\instance\twi0.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\sam\utils\cmsis\sam4e\include\instance\twi1.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\sam\utils\cmsis\sam4e\include\instance\uart0.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\sam\utils\cmsis\sam4e\include\instance\uart1.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\sam\utils\cmsis\sam4e\include\instance\udp.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\sam\utils\cmsis\sam4e\include\instance\usart0.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\sam\utils\cmsis\sam4e\include\instance\usart1.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\sam\utils\cmsis\sam4e\include\instance\wdt.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\sam\utils\cmsis\sam4e\include\pio\sam4e16c.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\sam\utils\cmsis\sam4e\include\pio\sam4e16e.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\sam\utils\cmsis\sam4e\include\pio\sam4e8c.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\sam\utils\cmsis\sam4e\include\pio\sam4e8e.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\sam\utils\cmsis\sam4e\include\sam4e.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\sam\utils\cmsis\sam4e\include\sam4e16c.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\sam\utils\cmsis\sam4e\include\sam4e16e.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\sam\utils\cmsis\sam4e\include\sam4e8c.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\sam\utils\cmsis\sam4e\include\sam4e8e.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\sam\utils\cmsis\sam4e\source\templates\exceptions.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\sam\utils\cmsis\sam4e\source\templates\system_sam4e.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\sam\utils\compiler.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\sam\utils\fpu\fpu.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\sam\utils\header_files\io.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\sam\utils\linker_scripts\sam4e\sam4e16e\gcc\flash.ld">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\sam\utils\make\Makefile.sam.in">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\sam\utils\preprocessor\mrepeat.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\sam\utils\preprocessor\preprocessor.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\sam\utils\preprocessor\stringz.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\sam\utils\preprocessor\tpaste.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\sam\utils\status_codes.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\thirdparty\CMSIS\CMSIS END USER LICENCE AGREEMENT.pdf">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\thirdparty\CMSIS\Include\arm_math.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\thirdparty\CMSIS\Include\core_cm4.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\thirdparty\CMSIS\Include\core_cm4_simd.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\thirdparty\CMSIS\Include\core_cmFunc.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\thirdparty\CMSIS\Include\core_cmInstr.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\thirdparty\CMSIS\Lib\GCC\libarm_cortexM4lf_math.a">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\thirdparty\CMSIS\README.txt">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\ASF\thirdparty\CMSIS\license.txt">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ </ItemGroup>\r
+ <ItemGroup>\r
+ <Folder Include="src\" />\r
+ <Folder Include="src\ASF\" />\r
+ <Folder Include="src\ASF\common\" />\r
+ <Folder Include="src\ASF\common\boards\" />\r
+ <Folder Include="src\ASF\common\services\" />\r
+ <Folder Include="src\ASF\common\services\clock\" />\r
+ <Folder Include="src\ASF\common\services\clock\sam4e\" />\r
+ <Folder Include="src\ASF\common\services\ioport\" />\r
+ <Folder Include="src\ASF\common\services\ioport\sam\" />\r
+ <Folder Include="src\ASF\common\utils\" />\r
+ <Folder Include="src\ASF\common\utils\interrupt\" />\r
+ <Folder Include="src\ASF\sam\" />\r
+ <Folder Include="src\ASF\sam\boards\" />\r
+ <Folder Include="src\ASF\sam\boards\sam4e_ek\" />\r
+ <Folder Include="src\ASF\sam\components\" />\r
+ <Folder Include="src\ASF\sam\components\ethernet_phy\" />\r
+ <Folder Include="src\ASF\sam\components\ethernet_phy\ksz8051mnl\" />\r
+ <Folder Include="src\ASF\sam\drivers\" />\r
+ <Folder Include="src\ASF\sam\drivers\gmac\" />\r
+ <Folder Include="src\ASF\sam\drivers\pmc\" />\r
+ <Folder Include="src\ASF\sam\utils\" />\r
+ <Folder Include="src\ASF\sam\utils\cmsis\" />\r
+ <Folder Include="src\ASF\sam\utils\cmsis\sam4e\" />\r
+ <Folder Include="src\ASF\sam\utils\cmsis\sam4e\include\" />\r
+ <Folder Include="src\ASF\sam\utils\cmsis\sam4e\include\component\" />\r
+ <Folder Include="src\ASF\sam\utils\cmsis\sam4e\include\instance\" />\r
+ <Folder Include="src\ASF\sam\utils\cmsis\sam4e\include\pio\" />\r
+ <Folder Include="src\ASF\sam\utils\cmsis\sam4e\source\" />\r
+ <Folder Include="src\ASF\sam\utils\cmsis\sam4e\source\templates\" />\r
+ <Folder Include="src\ASF\sam\utils\cmsis\sam4e\source\templates\gcc\" />\r
+ <Folder Include="src\ASF\sam\utils\fpu\" />\r
+ <Folder Include="src\ASF\sam\utils\header_files\" />\r
+ <Folder Include="src\ASF\sam\utils\linker_scripts\" />\r
+ <Folder Include="src\ASF\sam\utils\linker_scripts\sam4e\" />\r
+ <Folder Include="src\ASF\sam\utils\linker_scripts\sam4e\sam4e16e\" />\r
+ <Folder Include="src\ASF\sam\utils\linker_scripts\sam4e\sam4e16e\gcc\" />\r
+ <Folder Include="src\ASF\sam\utils\make\" />\r
+ <Folder Include="src\ASF\sam\utils\preprocessor\" />\r
+ <Folder Include="src\ASF\sam\utils\syscalls\" />\r
+ <Folder Include="src\ASF\sam\utils\syscalls\gcc\" />\r
+ <Folder Include="src\ASF\thirdparty\" />\r
+ <Folder Include="src\ASF\thirdparty\CMSIS\" />\r
+ <Folder Include="src\ASF\thirdparty\CMSIS\Include\" />\r
+ <Folder Include="src\ASF\thirdparty\CMSIS\Lib\" />\r
+ <Folder Include="src\ASF\thirdparty\CMSIS\Lib\GCC\" />\r
+ <Folder Include="src\config\" />\r
+ <Folder Include="src\FreeRTOS" />\r
+ <Folder Include="src\FreeRTOS+" />\r
+ <Folder Include="src\FreeRTOS+\FreeRTOS+FAT SL\API" />\r
+ <Folder Include="src\FreeRTOS+\FreeRTOS+FAT SL\Media Driver" />\r
+ <Folder Include="src\FreeRTOS+\FreeRTOS+FAT SL\PSP" />\r
+ <Folder Include="src\FreeRTOS+\FreeRTOS+FAT SL\PSP\Target" />\r
+ <Folder Include="src\FreeRTOS+\FreeRTOS+FAT SL\PSP\Target\RTC" />\r
+ <Folder Include="src\FreeRTOS+\FreeRTOS+UDP" />\r
+ <Folder Include="src\FreeRTOS+\FreeRTOS+UDP\portable" />\r
+ <Folder Include="src\FreeRTOS+\FreeRTOS+UDP\portable\NetWorkInterface" />\r
+ <Folder Include="src\FreeRTOS+\FreeRTOS+UDP\portable\NetworkBuffers" />\r
+ <Folder Include="src\FreeRTOS+\FreeRTOS+CLI" />\r
+ <Folder Include="src\FreeRTOS+\FreeRTOS+FAT SL" />\r
+ <Folder Include="src\FreeRTOS\portable" />\r
+ </ItemGroup>\r
+ <Import Project="$(AVRSTUDIO_EXE_PATH)\\Vs\\Compiler.targets" />\r
+</Project>
\ No newline at end of file
--- /dev/null
+[BREAKPOINTS]\r
+ShowInfoWin = 1\r
+EnableFlashBP = 2\r
+BPDuringExecution = 0\r
+[CFI]\r
+CFISize = 0x00\r
+CFIAddr = 0x00\r
+[CPU]\r
+OverrideMemMap = 0\r
+AllowSimulation = 1\r
+ScriptFile=""\r
+[FLASH]\r
+CacheExcludeSize = 0x00\r
+CacheExcludeAddr = 0x00\r
+MinNumBytesFlashDL = 0\r
+SkipProgOnCRCMatch = 1\r
+VerifyDownload = 1\r
+AllowCaching = 1\r
+EnableFlashDL = 2\r
+Override = 0\r
+Device="UNSPECIFIED"\r
+[GENERAL]\r
+WorkRAMSize = 0x00\r
+WorkRAMAddr = 0x00\r
+RAMUsageLimit = 0x00\r
+[SWO]\r
+SWOLogFile=""\r
+[MEM]\r
+RdOverrideOrMask = 0x00\r
+RdOverrideAndMask = 0xFFFFFFFF\r
+RdOverrideAddr = 0xFFFFFFFF\r
+WrOverrideOrMask = 0x00\r
+WrOverrideAndMask = 0xFFFFFFFF\r
+WrOverrideAddr = 0xFFFFFFFF\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Standard board header file.\r
+ *\r
+ * This file includes the appropriate board header file according to the\r
+ * defined board (parameter BOARD).\r
+ *\r
+ * Copyright (c) 2009-2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _BOARD_H_\r
+#define _BOARD_H_\r
+\r
+/**\r
+ * \defgroup group_common_boards Generic board support\r
+ *\r
+ * The generic board support module includes board-specific definitions\r
+ * and function prototypes, such as the board initialization function.\r
+ *\r
+ * \{\r
+ */\r
+\r
+#include "compiler.h"\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+\r
+/*! \name Base Boards\r
+ */\r
+//! @{\r
+#define EVK1100 1 //!< AT32UC3A EVK1100 board.\r
+#define EVK1101 2 //!< AT32UC3B EVK1101 board.\r
+#define UC3C_EK 3 //!< AT32UC3C UC3C_EK board.\r
+#define EVK1104 4 //!< AT32UC3A3 EVK1104 board.\r
+#define EVK1105 5 //!< AT32UC3A EVK1105 board.\r
+#define STK600_RCUC3L0 6 //!< STK600 RCUC3L0 board.\r
+#define UC3L_EK 7 //!< AT32UC3L-EK board.\r
+#define XPLAIN 8 //!< ATxmega128A1 Xplain board.\r
+#define STK600_RC064X 10 //!< ATxmega256A3 STK600 board.\r
+#define STK600_RC100X 11 //!< ATxmega128A1 STK600 board.\r
+#define UC3_A3_XPLAINED 13 //!< ATUC3A3 UC3-A3 Xplained board.\r
+#define UC3_L0_XPLAINED 15 //!< ATUC3L0 UC3-L0 Xplained board.\r
+#define STK600_RCUC3D 16 //!< STK600 RCUC3D board.\r
+#define STK600_RCUC3C0 17 //!< STK600 RCUC3C board.\r
+#define XMEGA_B1_XPLAINED 18 //!< ATxmega128B1 Xplained board.\r
+#define XMEGA_A1_XPLAINED 19 //!< ATxmega128A1 Xplain-A1 board.\r
+#define STK600_RCUC3L4 21 //!< ATUCL4 STK600 board\r
+#define UC3_L0_XPLAINED_BC 22 //!< ATUC3L0 UC3-L0 Xplained board controller board\r
+#define MEGA1284P_XPLAINED_BC 23 //!< ATmega1284P-Xplained board controller board\r
+#define STK600_RC044X 24 //!< STK600 with RC044X routing card board.\r
+#define STK600_RCUC3B0 25 //!< STK600 RCUC3B0 board.\r
+#define UC3_L0_QT600 26 //!< QT600 UC3L0 MCU board.\r
+#define XMEGA_A3BU_XPLAINED 27 //!< ATxmega256A3BU Xplained board.\r
+#define STK600_RC064X_LCDX 28 //!< XMEGAB3 STK600 RC064X LCDX board.\r
+#define STK600_RC100X_LCDX 29 //!< XMEGAB1 STK600 RC100X LCDX board.\r
+#define UC3B_BOARD_CONTROLLER 30 //!< AT32UC3B1 board controller for Atmel boards\r
+#define RZ600 31 //!< AT32UC3A RZ600 MCU board\r
+#define SAM3S_EK 32 //!< SAM3S-EK board.\r
+#define SAM3U_EK 33 //!< SAM3U-EK board.\r
+#define SAM3X_EK 34 //!< SAM3X-EK board.\r
+#define SAM3N_EK 35 //!< SAM3N-EK board.\r
+#define SAM3S_EK2 36 //!< SAM3S-EK2 board.\r
+#define SAM4S_EK 37 //!< SAM4S-EK board.\r
+#define STK600_RCUC3A0 38 //!< STK600 RCUC3A0 board.\r
+#define STK600_MEGA 39 //!< STK600 MEGA board.\r
+#define MEGA_1284P_XPLAINED 40 //!< ATmega1284P Xplained board.\r
+#define SAM4S_XPLAINED 41 //!< SAM4S Xplained board.\r
+#define ATXMEGA128A1_QT600 42 //!< QT600 ATXMEGA128A1 MCU board.\r
+#define ARDUINO_DUE_X 43 //!< Arduino Due/X board.\r
+#define STK600_RCUC3L3 44 //!< ATUCL3 STK600 board\r
+#define SAM4L_EK 45 //!< SAM4L-EK board.\r
+#define STK600_MEGA_RF 46 //!< STK600 MEGA RF EVK board.\r
+#define XMEGA_C3_XPLAINED 47 //!< ATxmega384C3 Xplained board.\r
+#define STK600_RC032X 48 //!< STK600 with RC032X routing card board.\r
+#define SAM4S_EK2 49 //!< SAM4S-EK2 board.\r
+#define XMEGA_E5_XPLAINED 50 //!< ATxmega32E5 Xplained board.\r
+#define SAM4E_EK 51 //!< SAM4E-EK board.\r
+#define ATMEGA256RFR2_XPLAINED_PRO 52 //!< ATmega256RFR2 Xplained Pro board.\r
+#define SAM4S_XPLAINED_PRO 53 //!< SAM4S Xplained Pro board.\r
+#define SAM4L_XPLAINED_PRO 54 //!< SAM4L Xplained Pro board.\r
+#define ATMEGA256RFR2_ZIGBIT 55 //!< ATmega256RFR2 zigbit\r
+#define XMEGA_RF233_ZIGBIT 56 //!< ATxmega256A3U with AT86RF233 zigbit\r
+#define XMEGA_RF212B_ZIGBIT 57 //!< ATxmega256A3U with AT86RF212B zigbit\r
+#define SAM4S_WPIR_RD 58 //!< SAM4S-WPIR-RD board.\r
+#define SAMD20_XPLAINED_PRO 59 //!< SAMD20 Xplained PRO board\r
+#define SAM4L8_XPLAINED_PRO 60 //!< SAM4L8 Xplained Pro board.\r
+#define SAM4N_XPLAINED_PRO 61 //!< SAM4N-XPLAINED-PRO board.\r
+#define XMEGA_A3_REB_CBB 62 //!< SAM4L8 Xplained Pro board.\r
+#define ATMEGARFX_RCB 63 //!< RFR2 & RFA1 RCB\r
+#define SIMULATOR_XMEGA_A1 97 //!< Simulator for XMEGA A1 devices\r
+#define AVR_SIMULATOR_UC3 98 //!< AVR SIMULATOR for AVR UC3 device family.\r
+#define USER_BOARD 99 //!< User-reserved board (if any).\r
+#define DUMMY_BOARD 100 //!< Dummy board to support board-independent applications (e.g. bootloader)\r
+//! @}\r
+\r
+/*! \name Extension Boards\r
+ */\r
+//! @{\r
+#define EXT1102 1 //!< AT32UC3B EXT1102 board\r
+#define MC300 2 //!< AT32UC3 MC300 board\r
+#define SENSORS_XPLAINED_INERTIAL_1 3 //!< Xplained inertial sensor board 1\r
+#define SENSORS_XPLAINED_INERTIAL_2 4 //!< Xplained inertial sensor board 2\r
+#define SENSORS_XPLAINED_PRESSURE_1 5 //!< Xplained pressure sensor board\r
+#define SENSORS_XPLAINED_LIGHTPROX_1 6 //!< Xplained light & proximity sensor board\r
+#define SENSORS_XPLAINED_INERTIAL_A1 7 //!< Xplained inertial sensor board "A"\r
+#define RZ600_AT86RF231 8 //!< AT86RF231 RF board in RZ600\r
+#define RZ600_AT86RF230B 9 //!< AT86RF230B RF board in RZ600\r
+#define RZ600_AT86RF212 10 //!< AT86RF212 RF board in RZ600\r
+#define SENSORS_XPLAINED_BREADBOARD 11 //!< Xplained sensor development breadboard\r
+#define SECURITY_XPLAINED 12 //!< Xplained ATSHA204 board\r
+#define USER_EXT_BOARD 99 //!< User-reserved extension board (if any).\r
+//! @}\r
+\r
+#if BOARD == EVK1100\r
+# include "evk1100/evk1100.h"\r
+#elif BOARD == EVK1101\r
+# include "evk1101/evk1101.h"\r
+#elif BOARD == UC3C_EK\r
+# include "uc3c_ek/uc3c_ek.h"\r
+#elif BOARD == EVK1104\r
+# include "evk1104/evk1104.h"\r
+#elif BOARD == EVK1105\r
+# include "evk1105/evk1105.h"\r
+#elif BOARD == STK600_RCUC3L0\r
+# include "stk600/rcuc3l0/stk600_rcuc3l0.h"\r
+#elif BOARD == UC3L_EK\r
+# include "uc3l_ek/uc3l_ek.h"\r
+#elif BOARD == STK600_RCUC3L4\r
+# include "stk600/rcuc3l4/stk600_rcuc3l4.h"\r
+#elif BOARD == XPLAIN\r
+# include "xplain/xplain.h"\r
+#elif BOARD == STK600_MEGA\r
+ /*No header-file to include*/\r
+#elif BOARD == STK600_MEGA_RF\r
+# include "stk600.h"\r
+#elif BOARD == ATMEGA256RFR2_XPLAINED_PRO\r
+# include "atmega256rfr2_xplained_pro/atmega256rfr2_xplained_pro.h"\r
+#elif BOARD == ATMEGA256RFR2_ZIGBIT\r
+# include "atmega256rfr2_zigbit/atmega256rfr2_zigbit.h"\r
+#elif BOARD == STK600_RC032X\r
+# include "stk600/rc032x/stk600_rc032x.h"\r
+#elif BOARD == STK600_RC044X\r
+# include "stk600/rc044x/stk600_rc044x.h"\r
+#elif BOARD == STK600_RC064X\r
+# include "stk600/rc064x/stk600_rc064x.h"\r
+#elif BOARD == STK600_RC100X\r
+# include "stk600/rc100x/stk600_rc100x.h"\r
+#elif BOARD == UC3_A3_XPLAINED\r
+# include "uc3_a3_xplained/uc3_a3_xplained.h"\r
+#elif BOARD == UC3_L0_XPLAINED\r
+# include "uc3_l0_xplained/uc3_l0_xplained.h"\r
+#elif BOARD == STK600_RCUC3B0\r
+# include "stk600/rcuc3b0/stk600_rcuc3b0.h"\r
+#elif BOARD == STK600_RCUC3D\r
+# include "stk600/rcuc3d/stk600_rcuc3d.h"\r
+#elif BOARD == STK600_RCUC3C0\r
+# include "stk600/rcuc3c0/stk600_rcuc3c0.h"\r
+#elif BOARD == XMEGA_B1_XPLAINED\r
+# include "xmega_b1_xplained/xmega_b1_xplained.h"\r
+#elif BOARD == STK600_RC064X_LCDX\r
+# include "stk600/rc064x_lcdx/stk600_rc064x_lcdx.h"\r
+#elif BOARD == STK600_RC100X_LCDX\r
+# include "stk600/rc100x_lcdx/stk600_rc100x_lcdx.h"\r
+#elif BOARD == XMEGA_A1_XPLAINED\r
+# include "xmega_a1_xplained/xmega_a1_xplained.h"\r
+#elif BOARD == UC3_L0_XPLAINED_BC\r
+# include "uc3_l0_xplained_bc/uc3_l0_xplained_bc.h"\r
+#elif BOARD == SAM3S_EK\r
+# include "sam3s_ek/sam3s_ek.h"\r
+# include "system_sam3s.h"\r
+#elif BOARD == SAM3S_EK2\r
+# include "sam3s_ek2/sam3s_ek2.h"\r
+# include "system_sam3sd8.h"\r
+#elif BOARD == SAM3U_EK\r
+# include "sam3u_ek/sam3u_ek.h"\r
+# include "system_sam3u.h"\r
+#elif BOARD == SAM3X_EK\r
+# include "sam3x_ek/sam3x_ek.h"\r
+# include "system_sam3x.h"\r
+#elif BOARD == SAM3N_EK\r
+# include "sam3n_ek/sam3n_ek.h"\r
+# include "system_sam3n.h"\r
+#elif BOARD == SAM4S_EK\r
+# include "sam4s_ek/sam4s_ek.h"\r
+# include "system_sam4s.h"\r
+#elif BOARD == SAM4S_WPIR_RD\r
+# include "sam4s_wpir_rd/sam4s_wpir_rd.h"\r
+# include "system_sam4s.h"\r
+#elif BOARD == SAM4S_XPLAINED\r
+# include "sam4s_xplained/sam4s_xplained.h"\r
+# include "system_sam4s.h"\r
+#elif BOARD == SAM4S_EK2\r
+# include "sam4s_ek2/sam4s_ek2.h"\r
+# include "system_sam4s.h"\r
+#elif BOARD == MEGA_1284P_XPLAINED\r
+ /*No header-file to include*/\r
+#elif BOARD == ARDUINO_DUE_X\r
+# include "arduino_due_x/arduino_due_x.h"\r
+# include "system_sam3x.h"\r
+#elif BOARD == SAM4L_EK\r
+# include "sam4l_ek/sam4l_ek.h"\r
+#elif BOARD == SAM4E_EK\r
+# include "sam4e_ek/sam4e_ek.h"\r
+#elif BOARD == SAMD20_XPLAINED_PRO\r
+# include "samd20_xplained_pro/samd20_xplained_pro.h"\r
+#elif BOARD == SAM4N_XPLAINED_PRO\r
+# include "sam4n_xplained_pro/sam4n_xplained_pro.h"\r
+#elif BOARD == MEGA1284P_XPLAINED_BC\r
+# include "mega1284p_xplained_bc/mega1284p_xplained_bc.h"\r
+#elif BOARD == UC3_L0_QT600\r
+# include "uc3_l0_qt600/uc3_l0_qt600.h"\r
+#elif BOARD == XMEGA_A3BU_XPLAINED\r
+# include "xmega_a3bu_xplained/xmega_a3bu_xplained.h"\r
+#elif BOARD == XMEGA_E5_XPLAINED\r
+# include "xmega_e5_xplained/xmega_e5_xplained.h"\r
+#elif BOARD == UC3B_BOARD_CONTROLLER\r
+# include "uc3b_board_controller/uc3b_board_controller.h"\r
+#elif BOARD == RZ600\r
+# include "rz600/rz600.h"\r
+#elif BOARD == STK600_RCUC3A0\r
+# include "stk600/rcuc3a0/stk600_rcuc3a0.h"\r
+#elif BOARD == ATXMEGA128A1_QT600\r
+# include "atxmega128a1_qt600/atxmega128a1_qt600.h"\r
+#elif BOARD == STK600_RCUC3L3\r
+# include "stk600/rcuc3l3/stk600_rcuc3l3.h"\r
+#elif BOARD == SAM4S_XPLAINED_PRO\r
+# include "sam4s_xplained_pro/sam4s_xplained_pro.h"\r
+#elif BOARD == SAM4L_XPLAINED_PRO\r
+# include "sam4l_xplained_pro/sam4l_xplained_pro.h"\r
+#elif BOARD == SAM4L8_XPLAINED_PRO\r
+# include "sam4l8_xplained_pro/sam4l8_xplained_pro.h"\r
+#elif BOARD == SIMULATOR_XMEGA_A1\r
+# include "simulator/xmega_a1/simulator_xmega_a1.h"\r
+#elif BOARD == XMEGA_C3_XPLAINED\r
+# include "xmega_c3_xplained/xmega_c3_xplained.h"\r
+#elif BOARD == XMEGA_RF233_ZIGBIT\r
+# include "xmega_rf233_zigbit/xmega_rf233_zigbit.h"\r
+#elif BOARD == XMEGA_A3_REB_CBB\r
+# include "xmega_a3_reb_cbb/xmega_a3_reb_cbb.h"\r
+#elif BOARD == ATMEGARFX_RCB\r
+# include "atmegarfx_rcb/atmegarfx_rcb.h"\r
+#elif BOARD == XMEGA_RF212B_ZIGBIT\r
+# include "xmega_rf212b_zigbit/xmega_rf212b_zigbit.h"\r
+#elif BOARD == AVR_SIMULATOR_UC3\r
+# include "avr_simulator_uc3/avr_simulator_uc3.h"\r
+#elif BOARD == USER_BOARD\r
+ // User-reserved area: #include the header file of your board here (if any).\r
+# include "user_board.h"\r
+#elif BOARD == DUMMY_BOARD\r
+# include "dummy/dummy_board.h"\r
+#else\r
+# error No known Atmel board defined\r
+#endif\r
+\r
+#if (defined EXT_BOARD)\r
+# if EXT_BOARD == MC300\r
+# include "mc300/mc300.h"\r
+# elif (EXT_BOARD == SENSORS_XPLAINED_INERTIAL_1) || \\r
+ (EXT_BOARD == SENSORS_XPLAINED_INERTIAL_2) || \\r
+ (EXT_BOARD == SENSORS_XPLAINED_INERTIAL_A1) || \\r
+ (EXT_BOARD == SENSORS_XPLAINED_PRESSURE_1) || \\r
+ (EXT_BOARD == SENSORS_XPLAINED_LIGHTPROX_1) || \\r
+ (EXT_BOARD == SENSORS_XPLAINED_BREADBOARD)\r
+# include "sensors_xplained/sensors_xplained.h"\r
+# elif EXT_BOARD == RZ600_AT86RF231\r
+# include "at86rf231/at86rf231.h"\r
+# elif EXT_BOARD == RZ600_AT86RF230B\r
+# include "at86rf230b/at86rf230b.h"\r
+# elif EXT_BOARD == RZ600_AT86RF212\r
+# include "at86rf212/at86rf212.h"\r
+# elif EXT_BOARD == SECURITY_XPLAINED\r
+# include "security_xplained.h"\r
+# elif EXT_BOARD == USER_EXT_BOARD\r
+ // User-reserved area: #include the header file of your extension board here\r
+ // (if any).\r
+# endif\r
+#endif\r
+\r
+\r
+#if (defined(__GNUC__) && defined(__AVR32__)) || (defined(__ICCAVR32__) || defined(__AAVR32__))\r
+#ifdef __AVR32_ABI_COMPILER__ // Automatically defined when compiling for AVR32, not when assembling.\r
+\r
+/*! \brief This function initializes the board target resources\r
+ *\r
+ * This function should be called to ensure proper initialization of the target\r
+ * board hardware connected to the part.\r
+ */\r
+extern void board_init(void);\r
+\r
+#endif // #ifdef __AVR32_ABI_COMPILER__\r
+#else\r
+/*! \brief This function initializes the board target resources\r
+ *\r
+ * This function should be called to ensure proper initialization of the target\r
+ * board hardware connected to the part.\r
+ */\r
+extern void board_init(void);\r
+#endif\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+/**\r
+ * \}\r
+ */\r
+\r
+#endif // _BOARD_H_\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Generic clock management\r
+ *\r
+ * Copyright (c) 2010-2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+#ifndef CLK_GENCLK_H_INCLUDED\r
+#define CLK_GENCLK_H_INCLUDED\r
+\r
+#include "parts.h"\r
+\r
+#if SAM3S\r
+# include "sam3s/genclk.h"\r
+#elif SAM3U\r
+# include "sam3u/genclk.h"\r
+#elif SAM3N\r
+# include "sam3n/genclk.h"\r
+#elif SAM3XA\r
+# include "sam3x/genclk.h"\r
+#elif SAM4S\r
+# include "sam4s/genclk.h"\r
+#elif SAM4L\r
+# include "sam4l/genclk.h"\r
+#elif SAM4E\r
+# include "sam4e/genclk.h"\r
+#elif SAM4N\r
+# include "sam4n/genclk.h"\r
+#elif (UC3A0 || UC3A1)\r
+# include "uc3a0_a1/genclk.h"\r
+#elif UC3A3\r
+# include "uc3a3_a4/genclk.h"\r
+#elif UC3B\r
+# include "uc3b0_b1/genclk.h"\r
+#elif UC3C\r
+# include "uc3c/genclk.h"\r
+#elif UC3D\r
+# include "uc3d/genclk.h"\r
+#elif UC3L\r
+# include "uc3l/genclk.h"\r
+#else\r
+# error Unsupported chip type\r
+#endif\r
+\r
+/**\r
+ * \ingroup clk_group\r
+ * \defgroup genclk_group Generic Clock Management\r
+ *\r
+ * Generic clocks are configurable clocks which run outside the system\r
+ * clock domain. They are often connected to peripherals which have an\r
+ * asynchronous component running independently of the bus clock, e.g.\r
+ * USB controllers, low-power timers and RTCs, etc.\r
+ *\r
+ * Note that not all platforms have support for generic clocks; on such\r
+ * platforms, this API will not be available.\r
+ *\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \def GENCLK_DIV_MAX\r
+ * \brief Maximum divider supported by the generic clock implementation\r
+ */\r
+/**\r
+ * \enum genclk_source\r
+ * \brief Generic clock source ID\r
+ *\r
+ * Each generic clock may be generated from a different clock source.\r
+ * These are the available alternatives provided by the chip.\r
+ */\r
+\r
+//! \name Generic clock configuration\r
+//@{\r
+/**\r
+ * \struct genclk_config\r
+ * \brief Hardware representation of a set of generic clock parameters\r
+ */\r
+/**\r
+ * \fn void genclk_config_defaults(struct genclk_config *cfg,\r
+ * unsigned int id)\r
+ * \brief Initialize \a cfg to the default configuration for the clock\r
+ * identified by \a id.\r
+ */\r
+/**\r
+ * \fn void genclk_config_read(struct genclk_config *cfg, unsigned int id)\r
+ * \brief Read the currently active configuration of the clock\r
+ * identified by \a id into \a cfg.\r
+ */\r
+/**\r
+ * \fn void genclk_config_write(const struct genclk_config *cfg,\r
+ * unsigned int id)\r
+ * \brief Activate the configuration \a cfg on the clock identified by\r
+ * \a id.\r
+ */\r
+/**\r
+ * \fn void genclk_config_set_source(struct genclk_config *cfg,\r
+ * enum genclk_source src)\r
+ * \brief Select a new source clock \a src in configuration \a cfg.\r
+ */\r
+/**\r
+ * \fn void genclk_config_set_divider(struct genclk_config *cfg,\r
+ * unsigned int divider)\r
+ * \brief Set a new \a divider in configuration \a cfg.\r
+ */\r
+/**\r
+ * \fn void genclk_enable_source(enum genclk_source src)\r
+ * \brief Enable the source clock \a src used by a generic clock.\r
+ */\r
+ //@}\r
+\r
+//! \name Enabling and disabling Generic Clocks\r
+//@{\r
+/**\r
+ * \fn void genclk_enable(const struct genclk_config *cfg, unsigned int id)\r
+ * \brief Activate the configuration \a cfg on the clock identified by\r
+ * \a id and enable it.\r
+ */\r
+/**\r
+ * \fn void genclk_disable(unsigned int id)\r
+ * \brief Disable the generic clock identified by \a id.\r
+ */\r
+//@}\r
+\r
+/**\r
+ * \brief Enable the configuration defined by \a src and \a divider\r
+ * for the generic clock identified by \a id.\r
+ *\r
+ * \param id The ID of the generic clock.\r
+ * \param src The source clock of the generic clock.\r
+ * \param divider The divider used to generate the generic clock.\r
+ */\r
+static inline void genclk_enable_config(unsigned int id, enum genclk_source src, unsigned int divider)\r
+{\r
+ struct genclk_config gcfg;\r
+\r
+ genclk_config_defaults(&gcfg, id);\r
+ genclk_enable_source(src);\r
+ genclk_config_set_source(&gcfg, src);\r
+ genclk_config_set_divider(&gcfg, divider);\r
+ genclk_enable(&gcfg, id);\r
+}\r
+\r
+//! @}\r
+\r
+#endif /* CLK_GENCLK_H_INCLUDED */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Oscillator management\r
+ *\r
+ * Copyright (c) 2010-2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+#ifndef OSC_H_INCLUDED\r
+#define OSC_H_INCLUDED\r
+\r
+#include "parts.h"\r
+#include "conf_clock.h"\r
+\r
+#if SAM3S\r
+# include "sam3s/osc.h"\r
+#elif SAM3XA\r
+# include "sam3x/osc.h"\r
+#elif SAM3U\r
+# include "sam3u/osc.h"\r
+#elif SAM3N\r
+# include "sam3n/osc.h"\r
+#elif SAM4S\r
+# include "sam4s/osc.h"\r
+#elif SAM4E\r
+# include "sam4e/osc.h"\r
+#elif SAM4L\r
+# include "sam4l/osc.h"\r
+#elif SAM4N\r
+# include "sam4n/osc.h"\r
+#elif (UC3A0 || UC3A1)\r
+# include "uc3a0_a1/osc.h"\r
+#elif UC3A3\r
+# include "uc3a3_a4/osc.h"\r
+#elif UC3B\r
+# include "uc3b0_b1/osc.h"\r
+#elif UC3C\r
+# include "uc3c/osc.h"\r
+#elif UC3D\r
+# include "uc3d/osc.h"\r
+#elif UC3L\r
+# include "uc3l/osc.h"\r
+#elif XMEGA\r
+# include "xmega/osc.h"\r
+#else\r
+# error Unsupported chip type\r
+#endif\r
+\r
+/**\r
+ * \ingroup clk_group\r
+ * \defgroup osc_group Oscillator Management\r
+ *\r
+ * This group contains functions and definitions related to configuring\r
+ * and enabling/disabling on-chip oscillators. Internal RC-oscillators,\r
+ * external crystal oscillators and external clock generators are\r
+ * supported by this module. What all of these have in common is that\r
+ * they swing at a fixed, nominal frequency which is normally not\r
+ * adjustable.\r
+ *\r
+ * \par Example: Enabling an oscillator\r
+ *\r
+ * The following example demonstrates how to enable the external\r
+ * oscillator on XMEGA A and wait for it to be ready to use. The\r
+ * oscillator identifiers are platform-specific, so while the same\r
+ * procedure is used on all platforms, the parameter to osc_enable()\r
+ * will be different from device to device.\r
+ * \code\r
+ osc_enable(OSC_ID_XOSC);\r
+ osc_wait_ready(OSC_ID_XOSC); \endcode\r
+ *\r
+ * \section osc_group_board Board-specific Definitions\r
+ * If external oscillators are used, the board code must provide the\r
+ * following definitions for each of those:\r
+ * - \b BOARD_<osc name>_HZ: The nominal frequency of the oscillator.\r
+ * - \b BOARD_<osc name>_STARTUP_US: The startup time of the\r
+ * oscillator in microseconds.\r
+ * - \b BOARD_<osc name>_TYPE: The type of oscillator connected, i.e.\r
+ * whether it's a crystal or external clock, and sometimes what kind\r
+ * of crystal it is. The meaning of this value is platform-specific.\r
+ *\r
+ * @{\r
+ */\r
+\r
+//! \name Oscillator Management\r
+//@{\r
+/**\r
+ * \fn void osc_enable(uint8_t id)\r
+ * \brief Enable oscillator \a id\r
+ *\r
+ * The startup time and mode value is automatically determined based on\r
+ * definitions in the board code.\r
+ */\r
+/**\r
+ * \fn void osc_disable(uint8_t id)\r
+ * \brief Disable oscillator \a id\r
+ */\r
+/**\r
+ * \fn osc_is_ready(uint8_t id)\r
+ * \brief Determine whether oscillator \a id is ready.\r
+ * \retval true Oscillator \a id is running and ready to use as a clock\r
+ * source.\r
+ * \retval false Oscillator \a id is not running.\r
+ */\r
+/**\r
+ * \fn uint32_t osc_get_rate(uint8_t id)\r
+ * \brief Return the frequency of oscillator \a id in Hz\r
+ */\r
+\r
+#ifndef __ASSEMBLY__\r
+\r
+/**\r
+ * \brief Wait until the oscillator identified by \a id is ready\r
+ *\r
+ * This function will busy-wait for the oscillator identified by \a id\r
+ * to become stable and ready to use as a clock source.\r
+ *\r
+ * \param id A number identifying the oscillator to wait for.\r
+ */\r
+static inline void osc_wait_ready(uint8_t id)\r
+{\r
+ while (!osc_is_ready(id)) {\r
+ /* Do nothing */\r
+ }\r
+}\r
+\r
+#endif /* __ASSEMBLY__ */\r
+\r
+//@}\r
+\r
+//! @}\r
+\r
+#endif /* OSC_H_INCLUDED */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief PLL management\r
+ *\r
+ * Copyright (c) 2010-2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+#ifndef CLK_PLL_H_INCLUDED\r
+#define CLK_PLL_H_INCLUDED\r
+\r
+#include "parts.h"\r
+#include "conf_clock.h"\r
+\r
+#if SAM3S\r
+# include "sam3s/pll.h"\r
+#elif SAM3XA\r
+# include "sam3x/pll.h"\r
+#elif SAM3U\r
+# include "sam3u/pll.h"\r
+#elif SAM3N\r
+# include "sam3n/pll.h"\r
+#elif SAM4S\r
+# include "sam4s/pll.h"\r
+#elif SAM4E\r
+# include "sam4e/pll.h"\r
+#elif SAM4L\r
+# include "sam4l/pll.h"\r
+#elif SAM4N\r
+# include "sam4n/pll.h"\r
+#elif (UC3A0 || UC3A1)\r
+# include "uc3a0_a1/pll.h"\r
+#elif UC3A3\r
+# include "uc3a3_a4/pll.h"\r
+#elif UC3B\r
+# include "uc3b0_b1/pll.h"\r
+#elif UC3C\r
+# include "uc3c/pll.h"\r
+#elif UC3D\r
+# include "uc3d/pll.h"\r
+#elif (UC3L0128 || UC3L0256 || UC3L3_L4)\r
+# include "uc3l/pll.h"\r
+#elif XMEGA\r
+# include "xmega/pll.h"\r
+#else\r
+# error Unsupported chip type\r
+#endif\r
+\r
+/**\r
+ * \ingroup clk_group\r
+ * \defgroup pll_group PLL Management\r
+ *\r
+ * This group contains functions and definitions related to configuring\r
+ * and enabling/disabling on-chip PLLs. A PLL will take an input signal\r
+ * (the \em source), optionally divide the frequency by a configurable\r
+ * \em divider, and then multiply the frequency by a configurable \em\r
+ * multiplier.\r
+ *\r
+ * Some devices don't support input dividers; specifying any other\r
+ * divisor than 1 on these devices will result in an assertion failure.\r
+ * Other devices may have various restrictions to the frequency range of\r
+ * the input and output signals.\r
+ *\r
+ * \par Example: Setting up PLL0 with default parameters\r
+ *\r
+ * The following example shows how to configure and enable PLL0 using\r
+ * the default parameters specified using the configuration symbols\r
+ * listed above.\r
+ * \code\r
+ pll_enable_config_defaults(0); \endcode\r
+ *\r
+ * To configure, enable PLL0 using the default parameters and to disable\r
+ * a specific feature like Wide Bandwidth Mode (a UC3A3-specific\r
+ * PLL option.), you can use this initialization process.\r
+ * \code\r
+ struct pll_config pllcfg;\r
+ if (pll_is_locked(pll_id)) {\r
+ return; // Pll already running\r
+ }\r
+ pll_enable_source(CONFIG_PLL0_SOURCE);\r
+ pll_config_defaults(&pllcfg, 0);\r
+ pll_config_set_option(&pllcfg, PLL_OPT_WBM_DISABLE);\r
+ pll_enable(&pllcfg, 0);\r
+ pll_wait_for_lock(0); \endcode\r
+ *\r
+ * When the last function call returns, PLL0 is ready to be used as the\r
+ * main system clock source.\r
+ *\r
+ * \section pll_group_config Configuration Symbols\r
+ *\r
+ * Each PLL has a set of default parameters determined by the following\r
+ * configuration symbols in the application's configuration file:\r
+ * - \b CONFIG_PLLn_SOURCE: The default clock source connected to the\r
+ * input of PLL \a n. Must be one of the values defined by the\r
+ * #pll_source enum.\r
+ * - \b CONFIG_PLLn_MUL: The default multiplier (loop divider) of PLL\r
+ * \a n.\r
+ * - \b CONFIG_PLLn_DIV: The default input divider of PLL \a n.\r
+ *\r
+ * These configuration symbols determine the result of calling\r
+ * pll_config_defaults() and pll_get_default_rate().\r
+ *\r
+ * @{\r
+ */\r
+\r
+//! \name Chip-specific PLL characteristics\r
+//@{\r
+/**\r
+ * \def PLL_MAX_STARTUP_CYCLES\r
+ * \brief Maximum PLL startup time in number of slow clock cycles\r
+ */\r
+/**\r
+ * \def NR_PLLS\r
+ * \brief Number of on-chip PLLs\r
+ */\r
+\r
+/**\r
+ * \def PLL_MIN_HZ\r
+ * \brief Minimum frequency that the PLL can generate\r
+ */\r
+/**\r
+ * \def PLL_MAX_HZ\r
+ * \brief Maximum frequency that the PLL can generate\r
+ */\r
+/**\r
+ * \def PLL_NR_OPTIONS\r
+ * \brief Number of PLL option bits\r
+ */\r
+//@}\r
+\r
+/**\r
+ * \enum pll_source\r
+ * \brief PLL clock source\r
+ */\r
+\r
+//! \name PLL configuration\r
+//@{\r
+\r
+/**\r
+ * \struct pll_config\r
+ * \brief Hardware-specific representation of PLL configuration.\r
+ *\r
+ * This structure contains one or more device-specific values\r
+ * representing the current PLL configuration. The contents of this\r
+ * structure is typically different from platform to platform, and the\r
+ * user should not access any fields except through the PLL\r
+ * configuration API.\r
+ */\r
+\r
+/**\r
+ * \fn void pll_config_init(struct pll_config *cfg,\r
+ * enum pll_source src, unsigned int div, unsigned int mul)\r
+ * \brief Initialize PLL configuration from standard parameters.\r
+ *\r
+ * \note This function may be defined inline because it is assumed to be\r
+ * called very few times, and usually with constant parameters. Inlining\r
+ * it will in such cases reduce the code size significantly.\r
+ *\r
+ * \param cfg The PLL configuration to be initialized.\r
+ * \param src The oscillator to be used as input to the PLL.\r
+ * \param div PLL input divider.\r
+ * \param mul PLL loop divider (i.e. multiplier).\r
+ *\r
+ * \return A configuration which will make the PLL run at\r
+ * (\a mul / \a div) times the frequency of \a src\r
+ */\r
+/**\r
+ * \def pll_config_defaults(cfg, pll_id)\r
+ * \brief Initialize PLL configuration using default parameters.\r
+ *\r
+ * After this function returns, \a cfg will contain a configuration\r
+ * which will make the PLL run at (CONFIG_PLLx_MUL / CONFIG_PLLx_DIV)\r
+ * times the frequency of CONFIG_PLLx_SOURCE.\r
+ *\r
+ * \param cfg The PLL configuration to be initialized.\r
+ * \param pll_id Use defaults for this PLL.\r
+ */\r
+/**\r
+ * \def pll_get_default_rate(pll_id)\r
+ * \brief Get the default rate in Hz of \a pll_id\r
+ */\r
+/**\r
+ * \fn void pll_config_set_option(struct pll_config *cfg,\r
+ * unsigned int option)\r
+ * \brief Set the PLL option bit \a option in the configuration \a cfg.\r
+ *\r
+ * \param cfg The PLL configuration to be changed.\r
+ * \param option The PLL option bit to be set.\r
+ */\r
+/**\r
+ * \fn void pll_config_clear_option(struct pll_config *cfg,\r
+ * unsigned int option)\r
+ * \brief Clear the PLL option bit \a option in the configuration \a cfg.\r
+ *\r
+ * \param cfg The PLL configuration to be changed.\r
+ * \param option The PLL option bit to be cleared.\r
+ */\r
+/**\r
+ * \fn void pll_config_read(struct pll_config *cfg, unsigned int pll_id)\r
+ * \brief Read the currently active configuration of \a pll_id.\r
+ *\r
+ * \param cfg The configuration object into which to store the currently\r
+ * active configuration.\r
+ * \param pll_id The ID of the PLL to be accessed.\r
+ */\r
+/**\r
+ * \fn void pll_config_write(const struct pll_config *cfg,\r
+ * unsigned int pll_id)\r
+ * \brief Activate the configuration \a cfg on \a pll_id\r
+ *\r
+ * \param cfg The configuration object representing the PLL\r
+ * configuration to be activated.\r
+ * \param pll_id The ID of the PLL to be updated.\r
+ */\r
+\r
+//@}\r
+\r
+//! \name Interaction with the PLL hardware\r
+//@{\r
+/**\r
+ * \fn void pll_enable(const struct pll_config *cfg,\r
+ * unsigned int pll_id)\r
+ * \brief Activate the configuration \a cfg and enable PLL \a pll_id.\r
+ *\r
+ * \param cfg The PLL configuration to be activated.\r
+ * \param pll_id The ID of the PLL to be enabled.\r
+ */\r
+/**\r
+ * \fn void pll_disable(unsigned int pll_id)\r
+ * \brief Disable the PLL identified by \a pll_id.\r
+ *\r
+ * After this function is called, the PLL identified by \a pll_id will\r
+ * be disabled. The PLL configuration stored in hardware may be affected\r
+ * by this, so if the caller needs to restore the same configuration\r
+ * later, it should either do a pll_config_read() before disabling the\r
+ * PLL, or remember the last configuration written to the PLL.\r
+ *\r
+ * \param pll_id The ID of the PLL to be disabled.\r
+ */\r
+/**\r
+ * \fn bool pll_is_locked(unsigned int pll_id)\r
+ * \brief Determine whether the PLL is locked or not.\r
+ *\r
+ * \param pll_id The ID of the PLL to check.\r
+ *\r
+ * \retval true The PLL is locked and ready to use as a clock source\r
+ * \retval false The PLL is not yet locked, or has not been enabled.\r
+ */\r
+/**\r
+ * \fn void pll_enable_source(enum pll_source src)\r
+ * \brief Enable the source of the pll.\r
+ * The source is enabled, if the source is not already running.\r
+ *\r
+ * \param src The ID of the PLL source to enable.\r
+ */\r
+/**\r
+ * \fn void pll_enable_config_defaults(unsigned int pll_id)\r
+ * \brief Enable the pll with the default configuration.\r
+ * PLL is enabled, if the PLL is not already locked.\r
+ *\r
+ * \param pll_id The ID of the PLL to enable.\r
+ */\r
+\r
+/**\r
+ * \brief Wait for PLL \a pll_id to become locked\r
+ *\r
+ * \todo Use a timeout to avoid waiting forever and hanging the system\r
+ *\r
+ * \param pll_id The ID of the PLL to wait for.\r
+ *\r
+ * \retval STATUS_OK The PLL is now locked.\r
+ * \retval ERR_TIMEOUT Timed out waiting for PLL to become locked.\r
+ */\r
+static inline int pll_wait_for_lock(unsigned int pll_id)\r
+{\r
+ Assert(pll_id < NR_PLLS);\r
+\r
+ while (!pll_is_locked(pll_id)) {\r
+ /* Do nothing */\r
+ }\r
+\r
+ return 0;\r
+}\r
+\r
+//@}\r
+//! @}\r
+\r
+#endif /* CLK_PLL_H_INCLUDED */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Chip-specific generic clock management.\r
+ *\r
+ * Copyright (c) 2012 - 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef CHIP_GENCLK_H_INCLUDED\r
+#define CHIP_GENCLK_H_INCLUDED\r
+\r
+#include <osc.h>\r
+#include <pll.h>\r
+\r
+/// @cond 0\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+/**INDENT-ON**/\r
+/// @endcond\r
+\r
+/**\r
+ * \weakgroup genclk_group\r
+ * @{\r
+ */\r
+\r
+//! \name Programmable Clock Identifiers (PCK)\r
+//@{\r
+#define GENCLK_PCK_0 0 //!< PCK0 ID\r
+#define GENCLK_PCK_1 1 //!< PCK1 ID\r
+#define GENCLK_PCK_2 2 //!< PCK2 ID\r
+//@}\r
+\r
+//! \name Programmable Clock Sources (PCK)\r
+//@{\r
+\r
+enum genclk_source {\r
+ GENCLK_PCK_SRC_SLCK_RC = 0,//!< Internal 32kHz RC oscillator as PCK source clock\r
+ GENCLK_PCK_SRC_SLCK_XTAL = 1,//!< External 32kHz crystal oscillator as PCK source clock\r
+ GENCLK_PCK_SRC_SLCK_BYPASS = 2,//!< External 32kHz bypass oscillator as PCK source clock\r
+ GENCLK_PCK_SRC_MAINCK_4M_RC = 3,//!< Internal 4MHz RC oscillator as PCK source clock\r
+ GENCLK_PCK_SRC_MAINCK_8M_RC = 4,//!< Internal 8MHz RC oscillator as PCK source clock\r
+ GENCLK_PCK_SRC_MAINCK_12M_RC = 5,//!< Internal 12MHz RC oscillator as PCK source clock\r
+ GENCLK_PCK_SRC_MAINCK_XTAL = 6,//!< External crystal oscillator as PCK source clock\r
+ GENCLK_PCK_SRC_MAINCK_BYPASS = 7,//!< External bypass oscillator as PCK source clock\r
+ GENCLK_PCK_SRC_PLLACK = 8,//!< Use PLLACK as PCK source clock\r
+ GENCLK_PCK_SRC_MCK = 9,//!< Use Master Clk as PCK source clock\r
+};\r
+\r
+//@}\r
+\r
+//! \name Programmable Clock Prescalers (PCK)\r
+//@{\r
+\r
+enum genclk_divider {\r
+ GENCLK_PCK_PRES_1 = PMC_PCK_PRES_CLK_1, //!< Set PCK clock prescaler to 1\r
+ GENCLK_PCK_PRES_2 = PMC_PCK_PRES_CLK_2, //!< Set PCK clock prescaler to 2\r
+ GENCLK_PCK_PRES_4 = PMC_PCK_PRES_CLK_4, //!< Set PCK clock prescaler to 4\r
+ GENCLK_PCK_PRES_8 = PMC_PCK_PRES_CLK_8, //!< Set PCK clock prescaler to 8\r
+ GENCLK_PCK_PRES_16 = PMC_PCK_PRES_CLK_16, //!< Set PCK clock prescaler to 16\r
+ GENCLK_PCK_PRES_32 = PMC_PCK_PRES_CLK_32, //!< Set PCK clock prescaler to 32\r
+ GENCLK_PCK_PRES_64 = PMC_PCK_PRES_CLK_64, //!< Set PCK clock prescaler to 64\r
+};\r
+\r
+//@}\r
+\r
+struct genclk_config {\r
+ uint32_t ctrl;\r
+};\r
+\r
+static inline void genclk_config_defaults(struct genclk_config *p_cfg,\r
+ uint32_t ul_id)\r
+{\r
+ ul_id = ul_id;\r
+ p_cfg->ctrl = 0;\r
+}\r
+\r
+static inline void genclk_config_read(struct genclk_config *p_cfg,\r
+ uint32_t ul_id)\r
+{\r
+ p_cfg->ctrl = PMC->PMC_PCK[ul_id];\r
+}\r
+\r
+static inline void genclk_config_write(const struct genclk_config *p_cfg,\r
+ uint32_t ul_id)\r
+{\r
+ PMC->PMC_PCK[ul_id] = p_cfg->ctrl;\r
+}\r
+\r
+//! \name Programmable Clock Source and Prescaler configuration\r
+//@{\r
+\r
+static inline void genclk_config_set_source(struct genclk_config *p_cfg,\r
+ enum genclk_source e_src)\r
+{\r
+ p_cfg->ctrl &= (~PMC_PCK_CSS_Msk);\r
+\r
+ switch (e_src) {\r
+ case GENCLK_PCK_SRC_SLCK_RC:\r
+ case GENCLK_PCK_SRC_SLCK_XTAL:\r
+ case GENCLK_PCK_SRC_SLCK_BYPASS:\r
+ p_cfg->ctrl |= (PMC_PCK_CSS_SLOW_CLK);\r
+ break;\r
+\r
+ case GENCLK_PCK_SRC_MAINCK_4M_RC:\r
+ case GENCLK_PCK_SRC_MAINCK_8M_RC:\r
+ case GENCLK_PCK_SRC_MAINCK_12M_RC:\r
+ case GENCLK_PCK_SRC_MAINCK_XTAL:\r
+ case GENCLK_PCK_SRC_MAINCK_BYPASS:\r
+ p_cfg->ctrl |= (PMC_PCK_CSS_MAIN_CLK);\r
+ break;\r
+\r
+ case GENCLK_PCK_SRC_PLLACK:\r
+ p_cfg->ctrl |= (PMC_PCK_CSS_PLLA_CLK);\r
+ break;\r
+\r
+ case GENCLK_PCK_SRC_MCK:\r
+ p_cfg->ctrl |= (PMC_PCK_CSS_MCK);\r
+ break;\r
+\r
+ default:\r
+ break;\r
+ }\r
+}\r
+\r
+static inline void genclk_config_set_divider(struct genclk_config *p_cfg,\r
+ uint32_t e_divider)\r
+{\r
+ p_cfg->ctrl &= ~PMC_PCK_PRES_Msk;\r
+ p_cfg->ctrl |= e_divider;\r
+}\r
+\r
+//@}\r
+\r
+static inline void genclk_enable(const struct genclk_config *p_cfg, uint32_t ul_id)\r
+{\r
+ PMC->PMC_PCK[ul_id] = p_cfg->ctrl;\r
+ pmc_enable_pck(ul_id);\r
+}\r
+\r
+static inline void genclk_disable(uint32_t ul_id)\r
+{\r
+ pmc_disable_pck(ul_id);\r
+}\r
+\r
+static inline void genclk_enable_source(enum genclk_source e_src)\r
+{\r
+ switch (e_src) {\r
+ case GENCLK_PCK_SRC_SLCK_RC:\r
+ if (!osc_is_ready(OSC_SLCK_32K_RC)) {\r
+ osc_enable(OSC_SLCK_32K_RC);\r
+ osc_wait_ready(OSC_SLCK_32K_RC);\r
+ }\r
+ break;\r
+\r
+ case GENCLK_PCK_SRC_SLCK_XTAL:\r
+ if (!osc_is_ready(OSC_SLCK_32K_XTAL)) {\r
+ osc_enable(OSC_SLCK_32K_XTAL);\r
+ osc_wait_ready(OSC_SLCK_32K_XTAL);\r
+ }\r
+ break;\r
+\r
+ case GENCLK_PCK_SRC_SLCK_BYPASS:\r
+ if (!osc_is_ready(OSC_SLCK_32K_BYPASS)) {\r
+ osc_enable(OSC_SLCK_32K_BYPASS);\r
+ osc_wait_ready(OSC_SLCK_32K_BYPASS);\r
+ }\r
+ break;\r
+\r
+ case GENCLK_PCK_SRC_MAINCK_4M_RC:\r
+ if (!osc_is_ready(OSC_MAINCK_4M_RC)) {\r
+ osc_enable(OSC_MAINCK_4M_RC);\r
+ osc_wait_ready(OSC_MAINCK_4M_RC);\r
+ }\r
+ break;\r
+\r
+ case GENCLK_PCK_SRC_MAINCK_8M_RC:\r
+ if (!osc_is_ready(OSC_MAINCK_8M_RC)) {\r
+ osc_enable(OSC_MAINCK_8M_RC);\r
+ osc_wait_ready(OSC_MAINCK_8M_RC);\r
+ }\r
+ break;\r
+\r
+ case GENCLK_PCK_SRC_MAINCK_12M_RC:\r
+ if (!osc_is_ready(OSC_MAINCK_12M_RC)) {\r
+ osc_enable(OSC_MAINCK_12M_RC);\r
+ osc_wait_ready(OSC_MAINCK_12M_RC);\r
+ }\r
+ break;\r
+\r
+ case GENCLK_PCK_SRC_MAINCK_XTAL:\r
+ if (!osc_is_ready(OSC_MAINCK_XTAL)) {\r
+ osc_enable(OSC_MAINCK_XTAL);\r
+ osc_wait_ready(OSC_MAINCK_XTAL);\r
+ }\r
+ break;\r
+\r
+ case GENCLK_PCK_SRC_MAINCK_BYPASS:\r
+ if (!osc_is_ready(OSC_MAINCK_BYPASS)) {\r
+ osc_enable(OSC_MAINCK_BYPASS);\r
+ osc_wait_ready(OSC_MAINCK_BYPASS);\r
+ }\r
+ break;\r
+\r
+#ifdef CONFIG_PLL0_SOURCE\r
+ case GENCLK_PCK_SRC_PLLACK:\r
+ pll_enable_config_defaults(0);\r
+ break;\r
+#endif\r
+\r
+ case GENCLK_PCK_SRC_MCK:\r
+ break;\r
+\r
+ default:\r
+ Assert(false);\r
+ break;\r
+ }\r
+}\r
+\r
+//! @}\r
+\r
+/// @cond 0\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+/**INDENT-ON**/\r
+/// @endcond\r
+\r
+#endif /* CHIP_GENCLK_H_INCLUDED */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Chip-specific oscillator management functions.\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef CHIP_OSC_H_INCLUDED\r
+#define CHIP_OSC_H_INCLUDED\r
+\r
+#include "board.h"\r
+#include "pmc.h"\r
+\r
+/// @cond 0\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+/**INDENT-ON**/\r
+/// @endcond\r
+\r
+/**\r
+ * \weakgroup osc_group\r
+ * @{\r
+ */\r
+\r
+//! \name Oscillator identifiers\r
+//@{\r
+#define OSC_SLCK_32K_RC 0 //!< Internal 32kHz RC oscillator.\r
+#define OSC_SLCK_32K_XTAL 1 //!< External 32kHz crystal oscillator.\r
+#define OSC_SLCK_32K_BYPASS 2 //!< External 32kHz bypass oscillator.\r
+#define OSC_MAINCK_4M_RC 3 //!< Internal 4MHz RC oscillator.\r
+#define OSC_MAINCK_8M_RC 4 //!< Internal 8MHz RC oscillator.\r
+#define OSC_MAINCK_12M_RC 5 //!< Internal 12MHz RC oscillator.\r
+#define OSC_MAINCK_XTAL 6 //!< External crystal oscillator.\r
+#define OSC_MAINCK_BYPASS 7 //!< External bypass oscillator.\r
+//@}\r
+\r
+//! \name Oscillator clock speed in hertz\r
+//@{\r
+#define OSC_SLCK_32K_RC_HZ CHIP_FREQ_SLCK_RC //!< Internal 32kHz RC oscillator.\r
+#define OSC_SLCK_32K_XTAL_HZ BOARD_FREQ_SLCK_XTAL //!< External 32kHz crystal oscillator.\r
+#define OSC_SLCK_32K_BYPASS_HZ BOARD_FREQ_SLCK_BYPASS //!< External 32kHz bypass oscillator.\r
+#define OSC_MAINCK_4M_RC_HZ CHIP_FREQ_MAINCK_RC_4MHZ //!< Internal 4MHz RC oscillator.\r
+#define OSC_MAINCK_8M_RC_HZ CHIP_FREQ_MAINCK_RC_8MHZ //!< Internal 8MHz RC oscillator.\r
+#define OSC_MAINCK_12M_RC_HZ CHIP_FREQ_MAINCK_RC_12MHZ //!< Internal 12MHz RC oscillator.\r
+#define OSC_MAINCK_XTAL_HZ BOARD_FREQ_MAINCK_XTAL //!< External crystal oscillator.\r
+#define OSC_MAINCK_BYPASS_HZ BOARD_FREQ_MAINCK_BYPASS //!< External bypass oscillator.\r
+//@}\r
+\r
+static inline void osc_enable(uint32_t ul_id)\r
+{\r
+ switch (ul_id) {\r
+ case OSC_SLCK_32K_RC:\r
+ break;\r
+\r
+ case OSC_SLCK_32K_XTAL:\r
+ pmc_switch_sclk_to_32kxtal(PMC_OSC_XTAL);\r
+ break;\r
+\r
+ case OSC_SLCK_32K_BYPASS:\r
+ pmc_switch_sclk_to_32kxtal(PMC_OSC_BYPASS);\r
+ break;\r
+\r
+\r
+ case OSC_MAINCK_4M_RC:\r
+ pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_4_MHz);\r
+ break;\r
+\r
+ case OSC_MAINCK_8M_RC:\r
+ pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_8_MHz);\r
+ break;\r
+\r
+ case OSC_MAINCK_12M_RC:\r
+ pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_12_MHz);\r
+ break;\r
+\r
+\r
+ case OSC_MAINCK_XTAL:\r
+ pmc_switch_mainck_to_xtal(PMC_OSC_XTAL,\r
+ pmc_us_to_moscxtst(BOARD_OSC_STARTUP_US,\r
+ OSC_SLCK_32K_RC_HZ));\r
+ break;\r
+\r
+ case OSC_MAINCK_BYPASS:\r
+ pmc_switch_mainck_to_xtal(PMC_OSC_BYPASS,\r
+ pmc_us_to_moscxtst(BOARD_OSC_STARTUP_US,\r
+ OSC_SLCK_32K_RC_HZ));\r
+ break;\r
+ }\r
+}\r
+\r
+static inline void osc_disable(uint32_t ul_id)\r
+{\r
+ switch (ul_id) {\r
+ case OSC_SLCK_32K_RC:\r
+ case OSC_SLCK_32K_XTAL:\r
+ case OSC_SLCK_32K_BYPASS:\r
+ break;\r
+\r
+ case OSC_MAINCK_4M_RC:\r
+ case OSC_MAINCK_8M_RC:\r
+ case OSC_MAINCK_12M_RC:\r
+ pmc_osc_disable_fastrc();\r
+ break;\r
+\r
+ case OSC_MAINCK_XTAL:\r
+ pmc_osc_disable_xtal(PMC_OSC_XTAL);\r
+ break;\r
+\r
+ case OSC_MAINCK_BYPASS:\r
+ pmc_osc_disable_xtal(PMC_OSC_BYPASS);\r
+ break;\r
+ }\r
+}\r
+\r
+static inline bool osc_is_ready(uint32_t ul_id)\r
+{\r
+ switch (ul_id) {\r
+ case OSC_SLCK_32K_RC:\r
+ return 1;\r
+\r
+ case OSC_SLCK_32K_XTAL:\r
+ case OSC_SLCK_32K_BYPASS:\r
+ return pmc_osc_is_ready_32kxtal();\r
+\r
+ case OSC_MAINCK_4M_RC:\r
+ case OSC_MAINCK_8M_RC:\r
+ case OSC_MAINCK_12M_RC:\r
+ case OSC_MAINCK_XTAL:\r
+ case OSC_MAINCK_BYPASS:\r
+ return pmc_osc_is_ready_mainck();\r
+ }\r
+\r
+ return 0;\r
+}\r
+\r
+static inline uint32_t osc_get_rate(uint32_t ul_id)\r
+{\r
+ switch (ul_id) {\r
+ case OSC_SLCK_32K_RC:\r
+ return OSC_SLCK_32K_RC_HZ;\r
+\r
+#ifdef BOARD_FREQ_SLCK_XTAL\r
+ case OSC_SLCK_32K_XTAL:\r
+ return BOARD_FREQ_SLCK_XTAL;\r
+#endif\r
+\r
+#ifdef BOARD_FREQ_SLCK_BYPASS\r
+ case OSC_SLCK_32K_BYPASS:\r
+ return BOARD_FREQ_SLCK_BYPASS;\r
+#endif\r
+\r
+ case OSC_MAINCK_4M_RC:\r
+ return OSC_MAINCK_4M_RC_HZ;\r
+\r
+ case OSC_MAINCK_8M_RC:\r
+ return OSC_MAINCK_8M_RC_HZ;\r
+\r
+ case OSC_MAINCK_12M_RC:\r
+ return OSC_MAINCK_12M_RC_HZ;\r
+\r
+#ifdef BOARD_FREQ_MAINCK_XTAL\r
+ case OSC_MAINCK_XTAL:\r
+ return BOARD_FREQ_MAINCK_XTAL;\r
+#endif\r
+\r
+#ifdef BOARD_FREQ_MAINCK_BYPASS\r
+ case OSC_MAINCK_BYPASS:\r
+ return BOARD_FREQ_MAINCK_BYPASS;\r
+#endif\r
+ }\r
+\r
+ return 0;\r
+}\r
+\r
+//! @}\r
+\r
+/// @cond 0\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+/**INDENT-ON**/\r
+/// @endcond\r
+\r
+#endif /* CHIP_OSC_H_INCLUDED */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Chip-specific PLL definitions.\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef CHIP_PLL_H_INCLUDED\r
+#define CHIP_PLL_H_INCLUDED\r
+\r
+#include <osc.h>\r
+\r
+/// @cond 0\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+/**INDENT-ON**/\r
+/// @endcond\r
+\r
+/**\r
+ * \weakgroup pll_group\r
+ * @{\r
+ */\r
+\r
+#define PLL_OUTPUT_MIN_HZ 80000000\r
+#define PLL_OUTPUT_MAX_HZ 240000000\r
+\r
+#define PLL_INPUT_MIN_HZ 3000000\r
+#define PLL_INPUT_MAX_HZ 32000000\r
+\r
+#define NR_PLLS 1\r
+#define PLLA_ID 0\r
+\r
+#define PLL_COUNT 0x3fU\r
+\r
+enum pll_source {\r
+ PLL_SRC_MAINCK_4M_RC = OSC_MAINCK_4M_RC, //!< Internal 4MHz RC oscillator.\r
+ PLL_SRC_MAINCK_8M_RC = OSC_MAINCK_8M_RC, //!< Internal 8MHz RC oscillator.\r
+ PLL_SRC_MAINCK_12M_RC = OSC_MAINCK_12M_RC, //!< Internal 12MHz RC oscillator.\r
+ PLL_SRC_MAINCK_XTAL = OSC_MAINCK_XTAL, //!< External crystal oscillator.\r
+ PLL_SRC_MAINCK_BYPASS = OSC_MAINCK_BYPASS, //!< External bypass oscillator.\r
+ PLL_NR_SOURCES, //!< Number of PLL sources.\r
+};\r
+\r
+struct pll_config {\r
+ uint32_t ctrl;\r
+};\r
+\r
+#define pll_get_default_rate(pll_id) \\r
+ ((osc_get_rate(CONFIG_PLL##pll_id##_SOURCE) \\r
+ * CONFIG_PLL##pll_id##_MUL) \\r
+ / CONFIG_PLL##pll_id##_DIV)\r
+\r
+/**\r
+ * \note The SAM4E PLL hardware interprets mul as mul+1. For readability the\r
+ * hardware mul+1 is hidden in this implementation. Use mul as mul effective\r
+ * value.\r
+ */\r
+static inline void pll_config_init(struct pll_config *p_cfg,\r
+ enum pll_source e_src, uint32_t ul_div, uint32_t ul_mul)\r
+{\r
+ uint32_t vco_hz;\r
+\r
+ Assert(e_src < PLL_NR_SOURCES);\r
+\r
+ /* Calculate internal VCO frequency */\r
+ vco_hz = osc_get_rate(e_src) / ul_div;\r
+ Assert(vco_hz >= PLL_INPUT_MIN_HZ);\r
+ Assert(vco_hz <= PLL_INPUT_MAX_HZ);\r
+\r
+ vco_hz *= ul_mul;\r
+ Assert(vco_hz >= PLL_OUTPUT_MIN_HZ);\r
+ Assert(vco_hz <= PLL_OUTPUT_MAX_HZ);\r
+\r
+ /* PMC hardware will automatically make it mul+1 */\r
+ p_cfg->ctrl = CKGR_PLLAR_MULA(ul_mul - 1) | CKGR_PLLAR_DIVA(ul_div) | \\r
+ CKGR_PLLAR_PLLACOUNT(PLL_COUNT);\r
+}\r
+\r
+#define pll_config_defaults(cfg, pll_id) \\r
+ pll_config_init(cfg, \\r
+ CONFIG_PLL##pll_id##_SOURCE, \\r
+ CONFIG_PLL##pll_id##_DIV, \\r
+ CONFIG_PLL##pll_id##_MUL)\r
+\r
+static inline void pll_config_read(struct pll_config *p_cfg, uint32_t ul_pll_id)\r
+{\r
+ Assert(ul_pll_id < NR_PLLS);\r
+\r
+ if (ul_pll_id == PLLA_ID) {\r
+ p_cfg->ctrl = PMC->CKGR_PLLAR;\r
+ }\r
+}\r
+\r
+static inline void pll_config_write(const struct pll_config *p_cfg, uint32_t ul_pll_id)\r
+{\r
+ Assert(ul_pll_id < NR_PLLS);\r
+\r
+ if (ul_pll_id == PLLA_ID) {\r
+ pmc_disable_pllack(); // Always stop PLL first!\r
+ PMC->CKGR_PLLAR = CKGR_PLLAR_ONE | p_cfg->ctrl;\r
+ }\r
+}\r
+\r
+static inline void pll_enable(const struct pll_config *p_cfg, uint32_t ul_pll_id)\r
+{\r
+ Assert(ul_pll_id < NR_PLLS);\r
+\r
+ if (ul_pll_id == PLLA_ID) {\r
+ pmc_disable_pllack(); // Always stop PLL first!\r
+ PMC->CKGR_PLLAR = CKGR_PLLAR_ONE | p_cfg->ctrl;\r
+ }\r
+}\r
+\r
+/**\r
+ * \note This will only disable the selected PLL, not the underlying oscillator (mainck).\r
+ */\r
+static inline void pll_disable(uint32_t ul_pll_id)\r
+{\r
+ Assert(ul_pll_id < NR_PLLS);\r
+\r
+ if (ul_pll_id == PLLA_ID) {\r
+ pmc_disable_pllack();\r
+ }\r
+}\r
+\r
+static inline uint32_t pll_is_locked(uint32_t ul_pll_id)\r
+{\r
+ Assert(ul_pll_id < NR_PLLS);\r
+\r
+ UNUSED(ul_pll_id);\r
+ return pmc_is_locked_pllack();\r
+}\r
+\r
+static inline void pll_enable_source(enum pll_source e_src)\r
+{\r
+ switch (e_src) {\r
+ case PLL_SRC_MAINCK_4M_RC:\r
+ case PLL_SRC_MAINCK_8M_RC:\r
+ case PLL_SRC_MAINCK_12M_RC:\r
+ case PLL_SRC_MAINCK_XTAL:\r
+ case PLL_SRC_MAINCK_BYPASS:\r
+ osc_enable(e_src);\r
+ osc_wait_ready(e_src);\r
+ break;\r
+\r
+ default:\r
+ Assert(false);\r
+ break;\r
+ }\r
+}\r
+\r
+static inline void pll_enable_config_defaults(unsigned int ul_pll_id)\r
+{\r
+ struct pll_config pllcfg;\r
+\r
+ if (pll_is_locked(ul_pll_id)) {\r
+ return; // Pll already running\r
+ }\r
+ switch (ul_pll_id) {\r
+#ifdef CONFIG_PLL0_SOURCE\r
+ case 0:\r
+ pll_enable_source(CONFIG_PLL0_SOURCE);\r
+ pll_config_init(&pllcfg,\r
+ CONFIG_PLL0_SOURCE,\r
+ CONFIG_PLL0_DIV,\r
+ CONFIG_PLL0_MUL);\r
+ break;\r
+#endif\r
+ default:\r
+ Assert(false);\r
+ break;\r
+ }\r
+ pll_enable(&pllcfg, ul_pll_id);\r
+ while (!pll_is_locked(ul_pll_id));\r
+}\r
+\r
+//! @}\r
+\r
+/// @cond 0\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+/**INDENT-ON**/\r
+/// @endcond\r
+\r
+#endif /* CHIP_PLL_H_INCLUDED */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Chip-specific system clock management functions.\r
+ *\r
+ * Copyright (c) 2012 - 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#include <sysclk.h>\r
+\r
+/// @cond 0\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+/**INDENT-ON**/\r
+/// @endcond\r
+\r
+/**\r
+ * \weakgroup sysclk_group\r
+ * @{\r
+ */\r
+\r
+#if defined(CONFIG_SYSCLK_DEFAULT_RETURNS_SLOW_OSC)\r
+/**\r
+ * \brief boolean signalling that the sysclk_init is done.\r
+ */\r
+uint32_t sysclk_initialized = 0;\r
+#endif\r
+\r
+/**\r
+ * \brief Set system clock prescaler configuration\r
+ *\r
+ * This function will change the system clock prescaler configuration to\r
+ * match the parameters.\r
+ *\r
+ * \note The parameters to this function are device-specific.\r
+ *\r
+ * \param ul_pres The CPU clock will be divided by \f$2^{mck\_pres}\f$\r
+ */\r
+void sysclk_set_prescalers(uint32_t ul_pres)\r
+{\r
+ pmc_mck_set_prescaler(ul_pres);\r
+ SystemCoreClockUpdate();\r
+}\r
+\r
+/**\r
+ * \brief Change the source of the main system clock.\r
+ *\r
+ * \param ul_src The new system clock source. Must be one of the constants\r
+ * from the <em>System Clock Sources</em> section.\r
+ */\r
+void sysclk_set_source(uint32_t ul_src)\r
+{\r
+ switch (ul_src) {\r
+ case SYSCLK_SRC_SLCK_RC:\r
+ case SYSCLK_SRC_SLCK_XTAL:\r
+ case SYSCLK_SRC_SLCK_BYPASS:\r
+ pmc_mck_set_source(PMC_MCKR_CSS_SLOW_CLK);\r
+ break;\r
+\r
+ case SYSCLK_SRC_MAINCK_4M_RC:\r
+ case SYSCLK_SRC_MAINCK_8M_RC:\r
+ case SYSCLK_SRC_MAINCK_12M_RC:\r
+ case SYSCLK_SRC_MAINCK_XTAL:\r
+ case SYSCLK_SRC_MAINCK_BYPASS:\r
+ pmc_mck_set_source(PMC_MCKR_CSS_MAIN_CLK);\r
+ break;\r
+\r
+ case SYSCLK_SRC_PLLACK:\r
+ pmc_mck_set_source(PMC_MCKR_CSS_PLLA_CLK);\r
+ break;\r
+ }\r
+\r
+ SystemCoreClockUpdate();\r
+}\r
+\r
+#if defined(CONFIG_USBCLK_SOURCE) || defined(__DOXYGEN__)\r
+/**\r
+ * \brief Enable USB clock.\r
+ *\r
+ * \note The SAM3S UDP hardware interprets div as div+1. For readability the hardware div+1\r
+ * is hidden in this implementation. Use div as div effective value.\r
+ *\r
+ * \param pll_id Source of the USB clock.\r
+ * \param div Actual clock divisor. Must be superior to 0.\r
+ */\r
+void sysclk_enable_usb(void)\r
+{\r
+ Assert(CONFIG_USBCLK_DIV > 0);\r
+\r
+#ifdef CONFIG_PLL0_SOURCE\r
+ if (CONFIG_USBCLK_SOURCE == USBCLK_SRC_PLL0) {\r
+ struct pll_config pllcfg;\r
+\r
+ pll_enable_source(CONFIG_PLL0_SOURCE);\r
+ pll_config_defaults(&pllcfg, 0);\r
+ pll_enable(&pllcfg, 0);\r
+ pll_wait_for_lock(0);\r
+ pmc_switch_udpck_to_pllack(CONFIG_USBCLK_DIV - 1);\r
+ pmc_enable_udpck();\r
+ return;\r
+ }\r
+#endif\r
+}\r
+\r
+/**\r
+ * \brief Disable the USB clock.\r
+ *\r
+ * \note This implementation does not switch off the PLL, it just turns off the USB clock.\r
+ */\r
+void sysclk_disable_usb(void)\r
+{\r
+ pmc_disable_udpck();\r
+}\r
+#endif // CONFIG_USBCLK_SOURCE\r
+\r
+void sysclk_init(void)\r
+{\r
+ /* Set a flash wait state depending on the new cpu frequency */\r
+ system_init_flash(sysclk_get_cpu_hz());\r
+\r
+ /* Config system clock setting */\r
+ if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_SLCK_RC) {\r
+ osc_enable(OSC_SLCK_32K_RC);\r
+ osc_wait_ready(OSC_SLCK_32K_RC);\r
+ pmc_switch_mck_to_sclk(CONFIG_SYSCLK_PRES);\r
+ }\r
+\r
+ else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_SLCK_XTAL) {\r
+ osc_enable(OSC_SLCK_32K_XTAL);\r
+ osc_wait_ready(OSC_SLCK_32K_XTAL);\r
+ pmc_switch_mck_to_sclk(CONFIG_SYSCLK_PRES);\r
+ }\r
+\r
+ else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_SLCK_BYPASS) {\r
+ osc_enable(OSC_SLCK_32K_BYPASS);\r
+ osc_wait_ready(OSC_SLCK_32K_BYPASS);\r
+ pmc_switch_mck_to_sclk(CONFIG_SYSCLK_PRES);\r
+ }\r
+\r
+ else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_4M_RC) {\r
+ /* Already running from SYSCLK_SRC_MAINCK_4M_RC */\r
+ }\r
+\r
+ else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_8M_RC) {\r
+ osc_enable(OSC_MAINCK_8M_RC);\r
+ osc_wait_ready(OSC_MAINCK_8M_RC);\r
+ pmc_switch_mck_to_mainck(CONFIG_SYSCLK_PRES);\r
+ }\r
+\r
+ else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_12M_RC) {\r
+ osc_enable(OSC_MAINCK_12M_RC);\r
+ osc_wait_ready(OSC_MAINCK_12M_RC);\r
+ pmc_switch_mck_to_mainck(CONFIG_SYSCLK_PRES);\r
+ }\r
+\r
+ else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_XTAL) {\r
+ osc_enable(OSC_MAINCK_XTAL);\r
+ osc_wait_ready(OSC_MAINCK_XTAL);\r
+ pmc_switch_mck_to_mainck(CONFIG_SYSCLK_PRES);\r
+ }\r
+\r
+ else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_BYPASS) {\r
+ osc_enable(OSC_MAINCK_BYPASS);\r
+ osc_wait_ready(OSC_MAINCK_BYPASS);\r
+ pmc_switch_mck_to_mainck(CONFIG_SYSCLK_PRES);\r
+ }\r
+\r
+#ifdef CONFIG_PLL0_SOURCE\r
+ else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_PLLACK) {\r
+ struct pll_config pllcfg;\r
+\r
+ pll_enable_source(CONFIG_PLL0_SOURCE);\r
+ pll_config_defaults(&pllcfg, 0);\r
+ pll_enable(&pllcfg, 0);\r
+ pll_wait_for_lock(0);\r
+ pmc_switch_mck_to_pllack(CONFIG_SYSCLK_PRES);\r
+ }\r
+#endif\r
+\r
+ /* Update the SystemFrequency variable */\r
+ SystemCoreClockUpdate();\r
+\r
+#if (defined CONFIG_SYSCLK_DEFAULT_RETURNS_SLOW_OSC)\r
+ /* Signal that the internal frequencies are setup */\r
+ sysclk_initialized = 1;\r
+#endif\r
+}\r
+\r
+//! @}\r
+\r
+/// @cond 0\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+/**INDENT-ON**/\r
+/// @endcond\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Chip-specific system clock management functions.\r
+ *\r
+ * Copyright (c) 2012 - 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef CHIP_SYSCLK_H_INCLUDED\r
+#define CHIP_SYSCLK_H_INCLUDED\r
+\r
+#include <osc.h>\r
+#include <pll.h>\r
+\r
+/**\r
+ * \page sysclk_quickstart Quick Start Guide for the System Clock Management\r
+ * service (SAM4E)\r
+ *\r
+ * This is the quick start guide for the \ref sysclk_group "System Clock\r
+ * Management" service, with step-by-step instructions on how to configure and\r
+ * use the service for specific use cases.\r
+ *\r
+ * \section sysclk_quickstart_usecases System Clock Management use cases\r
+ * - \ref sysclk_quickstart_basic\r
+ * - \ref sysclk_quickstart_use_case_2\r
+ *\r
+ * \section sysclk_quickstart_basic Basic usage of the System Clock Management\r
+ * service\r
+ * This section will present a basic use case for the System Clock Management\r
+ * service. This use case will configure the main system clock to 120MHz,\r
+ * using an internal PLL module to multiply the frequency of a crystal attached\r
+ * to the microcontroller.\r
+ *\r
+ * \subsection sysclk_quickstart_use_case_1_prereq Prerequisites\r
+ * - None\r
+ *\r
+ * \subsection sysclk_quickstart_use_case_1_setup_steps Initialization code\r
+ * Add to the application initialization code:\r
+ * \code\r
+ * sysclk_init();\r
+ * \endcode\r
+ *\r
+ * \subsection sysclk_quickstart_use_case_1_setup_steps_workflow Workflow\r
+ * -# Configure the system clocks according to the settings in conf_clock.h:\r
+ * \code sysclk_init(); \endcode\r
+ *\r
+ * \subsection sysclk_quickstart_use_case_1_example_code Example code\r
+ * Add or uncomment the following in your conf_clock.h header file,\r
+ * commenting out all other definitions of the same symbol(s):\r
+ * \code\r
+ * #define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_PLLACK\r
+ *\r
+ * // Fpll0 = (Fclk * PLL_mul) / PLL_div\r
+ * #define CONFIG_PLL0_SOURCE PLL_SRC_MAINCK_XTAL\r
+ * #define CONFIG_PLL0_MUL (120000000UL / BOARD_FREQ_MAINCK_XTAL)\r
+ * #define CONFIG_PLL0_DIV 1\r
+ *\r
+ * // Fbus = Fsys / BUS_div\r
+ * #define CONFIG_SYSCLK_PRES SYSCLK_PRES_1\r
+ * \endcode\r
+ *\r
+ * \subsection sysclk_quickstart_use_case_1_example_workflow Workflow\r
+ * -# Configure the main system clock to use the output of the PLL module as\r
+ * its source:\r
+ * \code #define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_PLLACK \endcode\r
+ * -# Configure the PLL module to use the fast external fast crystal\r
+ * oscillator as its source:\r
+ * \code #define CONFIG_PLL0_SOURCE PLL_SRC_MAINCK_XTAL \endcode\r
+ * -# Configure the PLL module to multiply the external fast crystal\r
+ * oscillator frequency up to 120MHz:\r
+ * \code\r
+ * #define CONFIG_PLL0_MUL (120000000UL / BOARD_FREQ_MAINCK_XTAL)\r
+ * #define CONFIG_PLL0_DIV 1\r
+ * \endcode\r
+ * \note For user boards, \c BOARD_FREQ_MAINCK_XTAL should be defined in the\r
+ * board \c conf_board.h configuration\r
+ * file as the frequency of the fast crystal attached to the microcontroller.\r
+ * -# Configure the main clock to run at the full 120MHz, disable scaling of\r
+ * the main system clock speed:\r
+ * \code\r
+ * #define CONFIG_SYSCLK_PRES SYSCLK_PRES_1\r
+ * \endcode\r
+ * \note Some dividers are powers of two, while others are integer division\r
+ * factors. Refer to the formulas in the conf_clock.h template commented\r
+ * above each division define.\r
+ */\r
+\r
+/**\r
+ * \page sysclk_quickstart_use_case_2 Advanced use case - Peripheral Bus Clock\r
+ * Management (SAM4E)\r
+ *\r
+ * \section sysclk_quickstart_use_case_2 Advanced use case - Peripheral Bus\r
+ * Clock Management\r
+ * This section will present a more advanced use case for the System Clock\r
+ * Management service. This use case will configure the main system clock to\r
+ * 96MHz, using an internal PLL module to multiply the frequency of a crystal\r
+ * attached to the microcontroller. The USB clock will be configured via the\r
+ * same PLL module.\r
+ *\r
+ * \subsection sysclk_quickstart_use_case_2_prereq Prerequisites\r
+ * - None\r
+ *\r
+ * \subsection sysclk_quickstart_use_case_2_setup_steps Initialization code\r
+ * Add to the application initialization code:\r
+ * \code\r
+ * sysclk_init();\r
+ * \endcode\r
+ *\r
+ * \subsection sysclk_quickstart_use_case_2_setup_steps_workflow Workflow\r
+ * -# Configure the system clocks according to the settings in conf_clock.h:\r
+ * \code sysclk_init(); \endcode\r
+ *\r
+ * \subsection sysclk_quickstart_use_case_2_example_code Example code\r
+ * Add or uncomment the following in your conf_clock.h header file,\r
+ * commenting out all other definitions of the same symbol(s):\r
+ * \code\r
+ * #define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_PLLACK\r
+ *\r
+ * // Fpll0 = (Fclk * PLL_mul) / PLL_div\r
+ * #define CONFIG_PLL0_SOURCE PLL_SRC_MAINCK_XTAL\r
+ * #define CONFIG_PLL0_MUL (96000000UL / BOARD_FREQ_MAINCK_XTAL)\r
+ * #define CONFIG_PLL0_DIV 1\r
+ *\r
+ * // Fbus = Fsys / BUS_div\r
+ * #define CONFIG_SYSCLK_PRES SYSCLK_PRES_1\r
+ *\r
+ * // Fusb = Fsys / USB_div\r
+ * #define CONFIG_USBCLK_SOURCE USBCLK_SRC_PLL0\r
+ * #define CONFIG_USBCLK_DIV 2\r
+ * \endcode\r
+ *\r
+ * \subsection sysclk_quickstart_use_case_2_example_workflow Workflow\r
+ * -# Configure the main system clock to use the output of the PLL0 module as\r
+ * its source:\r
+ * \code #define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_PLLACK \endcode\r
+ * -# Configure the PLL0 module to use the fast external fast crystal\r
+ * oscillator as its source:\r
+ * \code #define CONFIG_PLL0_SOURCE PLL_SRC_MAINCK_XTAL \endcode\r
+ * -# Configure the PLL0 module to multiply the external fast crystal\r
+ * oscillator frequency up to 96MHz:\r
+ * \code\r
+ * #define CONFIG_PLL0_MUL (96000000UL / BOARD_FREQ_MAINCK_XTAL)\r
+ * #define CONFIG_PLL0_DIV 1\r
+ * \endcode\r
+ * \note For user boards, \c BOARD_FREQ_MAINCK_XTAL should be defined in the\r
+ * board \c conf_board.h configuration file as the frequency of the fast\r
+ * crystal attached to the microcontroller.\r
+ * -# Configure the main clock to run at the full 96MHz, disable scaling of\r
+ * the main system clock speed:\r
+ * \code\r
+ * #define CONFIG_SYSCLK_PRES SYSCLK_PRES_1\r
+ * \endcode\r
+ * \note Some dividers are powers of two, while others are integer division\r
+ * factors. Refer to the formulas in the conf_clock.h template commented\r
+ * above each division define.\r
+ * -# Configure the USB module clock to use the output of the PLL0 module as\r
+ * its source with division 2:\r
+ * \code\r
+ * #define CONFIG_USBCLK_SOURCE USBCLK_SRC_PLL0\r
+ * #define CONFIG_USBCLK_DIV 2\r
+ * \endcode\r
+ */\r
+\r
+/// @cond 0\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+/**INDENT-ON**/\r
+/// @endcond\r
+\r
+/**\r
+ * \weakgroup sysclk_group\r
+ * @{\r
+ */\r
+\r
+//! \name Configuration Symbols\r
+//@{\r
+/**\r
+ * \def CONFIG_SYSCLK_SOURCE\r
+ * \brief Initial/static main system clock source\r
+ *\r
+ * The main system clock will be configured to use this clock during\r
+ * initialization.\r
+ */\r
+#ifndef CONFIG_SYSCLK_SOURCE\r
+# define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_4M_RC\r
+#endif\r
+/**\r
+ * \def CONFIG_SYSCLK_PRES\r
+ * \brief Initial CPU clock divider (mck)\r
+ *\r
+ * The MCK will run at\r
+ * \f[\r
+ * f_{MCK} = \frac{f_{sys}}{\mathrm{CONFIG\_SYSCLK\_PRES}}\,\mbox{Hz}\r
+ * \f]\r
+ * after initialization.\r
+ */\r
+#ifndef CONFIG_SYSCLK_PRES\r
+# define CONFIG_SYSCLK_PRES 0\r
+#endif\r
+\r
+//@}\r
+\r
+//! \name Master Clock Sources (MCK)\r
+//@{\r
+#define SYSCLK_SRC_SLCK_RC 0 //!< Internal 32kHz RC oscillator as master source clock\r
+#define SYSCLK_SRC_SLCK_XTAL 1 //!< External 32kHz crystal oscillator as master source clock\r
+#define SYSCLK_SRC_SLCK_BYPASS 2 //!< External 32kHz bypass oscillator as master source clock\r
+#define SYSCLK_SRC_MAINCK_4M_RC 3 //!< Internal 4MHz RC oscillator as master source clock\r
+#define SYSCLK_SRC_MAINCK_8M_RC 4 //!< Internal 8MHz RC oscillator as master source clock\r
+#define SYSCLK_SRC_MAINCK_12M_RC 5 //!< Internal 12MHz RC oscillator as master source clock\r
+#define SYSCLK_SRC_MAINCK_XTAL 6 //!< External crystal oscillator as master source clock\r
+#define SYSCLK_SRC_MAINCK_BYPASS 7 //!< External bypass oscillator as master source clock\r
+#define SYSCLK_SRC_PLLACK 8 //!< Use PLLACK as master source clock\r
+//@}\r
+\r
+//! \name Master Clock Prescalers (MCK)\r
+//@{\r
+#define SYSCLK_PRES_1 PMC_MCKR_PRES_CLK_1 //!< Set master clock prescaler to 1\r
+#define SYSCLK_PRES_2 PMC_MCKR_PRES_CLK_2 //!< Set master clock prescaler to 2\r
+#define SYSCLK_PRES_4 PMC_MCKR_PRES_CLK_4 //!< Set master clock prescaler to 4\r
+#define SYSCLK_PRES_8 PMC_MCKR_PRES_CLK_8 //!< Set master clock prescaler to 8\r
+#define SYSCLK_PRES_16 PMC_MCKR_PRES_CLK_16 //!< Set master clock prescaler to 16\r
+#define SYSCLK_PRES_32 PMC_MCKR_PRES_CLK_32 //!< Set master clock prescaler to 32\r
+#define SYSCLK_PRES_64 PMC_MCKR_PRES_CLK_64 //!< Set master clock prescaler to 64\r
+#define SYSCLK_PRES_3 PMC_MCKR_PRES_CLK_3 //!< Set master clock prescaler to 3\r
+//@}\r
+\r
+//! \name USB Clock Sources\r
+//@{\r
+#define USBCLK_SRC_PLL0 0 //!< Use PLLA\r
+//@}\r
+\r
+/**\r
+ * \def CONFIG_USBCLK_SOURCE\r
+ * \brief Configuration symbol for the USB generic clock source\r
+ *\r
+ * Sets the clock source to use for the USB. The source must also be properly\r
+ * configured.\r
+ *\r
+ * Define this to one of the \c USBCLK_SRC_xxx settings. Leave it undefined if\r
+ * USB is not required.\r
+ */\r
+#ifdef __DOXYGEN__\r
+# define CONFIG_USBCLK_SOURCE\r
+#endif\r
+\r
+/**\r
+ * \def CONFIG_USBCLK_DIV\r
+ * \brief Configuration symbol for the USB generic clock divider setting\r
+ *\r
+ * Sets the clock division for the USB generic clock. If a USB clock source is\r
+ * selected with CONFIG_USBCLK_SOURCE, this configuration symbol must also be\r
+ * defined.\r
+ */\r
+#ifdef __DOXYGEN__\r
+# define CONFIG_USBCLK_DIV\r
+#endif\r
+\r
+/**\r
+ * \name Querying the system clock\r
+ *\r
+ * The following functions may be used to query the current frequency of\r
+ * the system clock and the CPU and bus clocks derived from it.\r
+ * sysclk_get_main_hz() and sysclk_get_cpu_hz() can be assumed to be\r
+ * available on all platforms, although some platforms may define\r
+ * additional accessors for various chip-internal bus clocks. These are\r
+ * usually not intended to be queried directly by generic code.\r
+ */\r
+//@{\r
+\r
+/**\r
+ * \brief Return the current rate in Hz of the main system clock\r
+ *\r
+ * \todo This function assumes that the main clock source never changes\r
+ * once it's been set up, and that PLL0 always runs at the compile-time\r
+ * configured default rate. While this is probably the most common\r
+ * configuration, which we want to support as a special case for\r
+ * performance reasons, we will at some point need to support more\r
+ * dynamic setups as well.\r
+ */\r
+#if (defined CONFIG_SYSCLK_DEFAULT_RETURNS_SLOW_OSC)\r
+extern uint32_t sysclk_initialized;\r
+#endif\r
+static inline uint32_t sysclk_get_main_hz(void)\r
+{\r
+#if (defined CONFIG_SYSCLK_DEFAULT_RETURNS_SLOW_OSC)\r
+ if (!sysclk_initialized ) {\r
+ return OSC_MAINCK_4M_RC_HZ;\r
+ }\r
+#endif\r
+\r
+ /* Config system clock setting */\r
+ if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_SLCK_RC) {\r
+ return OSC_SLCK_32K_RC_HZ;\r
+ } else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_SLCK_XTAL) {\r
+ return OSC_SLCK_32K_XTAL_HZ;\r
+ } else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_SLCK_BYPASS) {\r
+ return OSC_SLCK_32K_BYPASS_HZ;\r
+ } else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_4M_RC) {\r
+ return OSC_MAINCK_4M_RC_HZ;\r
+ } else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_8M_RC) {\r
+ return OSC_MAINCK_8M_RC_HZ;\r
+ } else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_12M_RC) {\r
+ return OSC_MAINCK_12M_RC_HZ;\r
+ } else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_XTAL) {\r
+ return OSC_MAINCK_XTAL_HZ;\r
+ } else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_BYPASS) {\r
+ return OSC_MAINCK_BYPASS_HZ;\r
+ }\r
+#ifdef CONFIG_PLL0_SOURCE\r
+ else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_PLLACK) {\r
+ return pll_get_default_rate(0);\r
+ }\r
+#endif\r
+\r
+ else {\r
+ /* unhandled_case(CONFIG_SYSCLK_SOURCE); */\r
+ return 0;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Return the current rate in Hz of the CPU clock\r
+ *\r
+ * \todo This function assumes that the CPU always runs at the system\r
+ * clock frequency. We want to support at least two more scenarios:\r
+ * Fixed CPU/bus clock dividers (config symbols) and dynamic CPU/bus\r
+ * clock dividers (which may change at run time). Ditto for all the bus\r
+ * clocks.\r
+ *\r
+ * \return Frequency of the CPU clock, in Hz.\r
+ */\r
+static inline uint32_t sysclk_get_cpu_hz(void)\r
+{\r
+ /* CONFIG_SYSCLK_PRES is the register value for setting the expected */\r
+ /* prescaler, not an immediate value. */\r
+ return sysclk_get_main_hz() /\r
+ ((CONFIG_SYSCLK_PRES == SYSCLK_PRES_3) ? 3 :\r
+ (1 << (CONFIG_SYSCLK_PRES >> PMC_MCKR_PRES_Pos)));\r
+}\r
+\r
+/**\r
+ * \brief Retrieves the current rate in Hz of the peripheral clocks.\r
+ *\r
+ * \return Frequency of the peripheral clocks, in Hz.\r
+ */\r
+static inline uint32_t sysclk_get_peripheral_hz(void)\r
+{\r
+ /* CONFIG_SYSCLK_PRES is the register value for setting the expected */\r
+ /* prescaler, not an immediate value. */\r
+ return sysclk_get_main_hz() /\r
+ ((CONFIG_SYSCLK_PRES == SYSCLK_PRES_3) ? 3 :\r
+ (1 << (CONFIG_SYSCLK_PRES >> PMC_MCKR_PRES_Pos)));\r
+}\r
+\r
+/**\r
+ * \brief Retrieves the current rate in Hz of the Peripheral Bus clock attached\r
+ * to the specified peripheral.\r
+ *\r
+ * \param module Pointer to the module's base address.\r
+ *\r
+ * \return Frequency of the bus attached to the specified peripheral, in Hz.\r
+ */\r
+static inline uint32_t sysclk_get_peripheral_bus_hz(const volatile void *module)\r
+{\r
+ UNUSED(module);\r
+ return sysclk_get_peripheral_hz();\r
+}\r
+//@}\r
+\r
+//! \name Enabling and disabling synchronous clocks\r
+//@{\r
+\r
+/**\r
+ * \brief Enable a peripheral's clock.\r
+ *\r
+ * \param ul_id Id (number) of the peripheral clock.\r
+ */\r
+static inline void sysclk_enable_peripheral_clock(uint32_t ul_id)\r
+{\r
+ pmc_enable_periph_clk(ul_id);\r
+}\r
+\r
+/**\r
+ * \brief Disable a peripheral's clock.\r
+ *\r
+ * \param ul_id Id (number) of the peripheral clock.\r
+ */\r
+static inline void sysclk_disable_peripheral_clock(uint32_t ul_id)\r
+{\r
+ pmc_disable_periph_clk(ul_id);\r
+}\r
+\r
+//@}\r
+\r
+//! \name System Clock Source and Prescaler configuration\r
+//@{\r
+\r
+extern void sysclk_set_prescalers(uint32_t ul_pres);\r
+extern void sysclk_set_source(uint32_t ul_src);\r
+\r
+//@}\r
+\r
+extern void sysclk_enable_usb(void);\r
+extern void sysclk_disable_usb(void);\r
+\r
+extern void sysclk_init(void);\r
+\r
+//! @}\r
+\r
+/// @cond 0\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+/**INDENT-ON**/\r
+/// @endcond\r
+\r
+#endif /* CHIP_SYSCLK_H_INCLUDED */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief System clock management\r
+ *\r
+ * Copyright (c) 2010-2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+#ifndef SYSCLK_H_INCLUDED\r
+#define SYSCLK_H_INCLUDED\r
+\r
+#include "parts.h"\r
+#include "conf_clock.h"\r
+\r
+#if SAM3S\r
+# include "sam3s/sysclk.h"\r
+#elif SAM3U\r
+# include "sam3u/sysclk.h"\r
+#elif SAM3N\r
+# include "sam3n/sysclk.h"\r
+#elif SAM3XA\r
+# include "sam3x/sysclk.h"\r
+#elif SAM4S\r
+# include "sam4s/sysclk.h"\r
+#elif SAM4E\r
+# include "sam4e/sysclk.h"\r
+#elif SAM4L\r
+# include "sam4l/sysclk.h"\r
+#elif SAM4N\r
+# include "sam4n/sysclk.h"\r
+#elif (UC3A0 || UC3A1)\r
+# include "uc3a0_a1/sysclk.h"\r
+#elif UC3A3\r
+# include "uc3a3_a4/sysclk.h"\r
+#elif UC3B\r
+# include "uc3b0_b1/sysclk.h"\r
+#elif UC3C\r
+# include "uc3c/sysclk.h"\r
+#elif UC3D\r
+# include "uc3d/sysclk.h"\r
+#elif UC3L\r
+# include "uc3l/sysclk.h"\r
+#elif XMEGA\r
+# include "xmega/sysclk.h"\r
+#elif MEGA\r
+# include "mega/sysclk.h"\r
+#else\r
+# error Unsupported chip type\r
+#endif\r
+\r
+/**\r
+ * \defgroup clk_group Clock Management\r
+ */\r
+\r
+/**\r
+ * \ingroup clk_group\r
+ * \defgroup sysclk_group System Clock Management\r
+ *\r
+ * See \ref sysclk_quickstart.\r
+ *\r
+ * The <em>sysclk</em> API covers the <em>system clock</em> and all\r
+ * clocks derived from it. The system clock is a chip-internal clock on\r
+ * which all <em>synchronous clocks</em>, i.e. CPU and bus/peripheral\r
+ * clocks, are based. The system clock is typically generated from one\r
+ * of a variety of sources, which may include crystal and RC oscillators\r
+ * as well as PLLs. The clocks derived from the system clock are\r
+ * sometimes also known as <em>synchronous clocks</em>, since they\r
+ * always run synchronously with respect to each other, as opposed to\r
+ * <em>generic clocks</em> which may run from different oscillators or\r
+ * PLLs.\r
+ *\r
+ * Most applications should simply call sysclk_init() to initialize\r
+ * everything related to the system clock and its source (oscillator,\r
+ * PLL or DFLL), and leave it at that. More advanced applications, and\r
+ * platform-specific drivers, may require additional services from the\r
+ * clock system, some of which may be platform-specific.\r
+ *\r
+ * \section sysclk_group_platform Platform Dependencies\r
+ *\r
+ * The sysclk API is partially chip- or platform-specific. While all\r
+ * platforms provide mostly the same functionality, there are some\r
+ * variations around how different bus types and clock tree structures\r
+ * are handled.\r
+ *\r
+ * The following functions are available on all platforms with the same\r
+ * parameters and functionality. These functions may be called freely by\r
+ * portable applications, drivers and services:\r
+ * - sysclk_init()\r
+ * - sysclk_set_source()\r
+ * - sysclk_get_main_hz()\r
+ * - sysclk_get_cpu_hz()\r
+ * - sysclk_get_peripheral_bus_hz()\r
+ *\r
+ * The following functions are available on all platforms, but there may\r
+ * be variations in the function signature (i.e. parameters) and\r
+ * behavior. These functions are typically called by platform-specific\r
+ * parts of drivers, and applications that aren't intended to be\r
+ * portable:\r
+ * - sysclk_enable_peripheral_clock()\r
+ * - sysclk_disable_peripheral_clock()\r
+ * - sysclk_enable_module()\r
+ * - sysclk_disable_module()\r
+ * - sysclk_module_is_enabled()\r
+ * - sysclk_set_prescalers()\r
+ *\r
+ * All other functions should be considered platform-specific.\r
+ * Enabling/disabling clocks to specific peripherals as well as\r
+ * determining the speed of these clocks should be done by calling\r
+ * functions provided by the driver for that peripheral.\r
+ *\r
+ * @{\r
+ */\r
+\r
+//! \name System Clock Initialization\r
+//@{\r
+/**\r
+ * \fn void sysclk_init(void)\r
+ * \brief Initialize the synchronous clock system.\r
+ *\r
+ * This function will initialize the system clock and its source. This\r
+ * includes:\r
+ * - Mask all synchronous clocks except for any clocks which are\r
+ * essential for normal operation (for example internal memory\r
+ * clocks).\r
+ * - Set up the system clock prescalers as specified by the\r
+ * application's configuration file.\r
+ * - Enable the clock source specified by the application's\r
+ * configuration file (oscillator or PLL) and wait for it to become\r
+ * stable.\r
+ * - Set the main system clock source to the clock specified by the\r
+ * application's configuration file.\r
+ *\r
+ * Since all non-essential peripheral clocks are initially disabled, it\r
+ * is the responsibility of the peripheral driver to re-enable any\r
+ * clocks that are needed for normal operation.\r
+ */\r
+//@}\r
+\r
+//! @}\r
+\r
+#endif /* SYSCLK_H_INCLUDED */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Common IOPORT service main header file for AVR, UC3 and ARM\r
+ * architectures.\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+#ifndef IOPORT_H\r
+#define IOPORT_H\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+#include <parts.h>\r
+#include <compiler.h>\r
+\r
+/**\r
+ * \defgroup ioport_group Common IOPORT API\r
+ *\r
+ * See \ref ioport_quickstart.\r
+ *\r
+ * This is common IOPORT service for GPIO pin configuration and control in a\r
+ * standardized manner across the MEGA, MEGA_RF, XMEGA, UC3 and ARM devices.\r
+ *\r
+ * Port pin control code is optimized for each platform, and should produce\r
+ * both compact and fast execution times when used with constant values.\r
+ *\r
+ * \section dependencies Dependencies\r
+ * This driver depends on the following modules:\r
+ * - \ref sysclk_group for clock speed and functions.\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \def IOPORT_CREATE_PIN(port, pin)\r
+ * \brief Create IOPORT pin number\r
+ *\r
+ * Create a IOPORT pin number for use with the IOPORT functions.\r
+ *\r
+ * \param port IOPORT port (e.g. PORTA, PA or PIOA depending on chosen\r
+ * architecture)\r
+ * \param pin IOPORT zero-based index of the I/O pin\r
+ */\r
+\r
+/** \brief IOPORT pin directions */\r
+enum ioport_direction {\r
+ IOPORT_DIR_INPUT, /*!< IOPORT input direction */\r
+ IOPORT_DIR_OUTPUT, /*!< IOPORT output direction */\r
+};\r
+\r
+/** \brief IOPORT levels */\r
+enum ioport_value {\r
+ IOPORT_PIN_LEVEL_LOW, /*!< IOPORT pin value low */\r
+ IOPORT_PIN_LEVEL_HIGH, /*!< IOPORT pin value high */\r
+};\r
+\r
+#if MEGA_RF\r
+/** \brief IOPORT edge sense modes */\r
+enum ioport_sense {\r
+ IOPORT_SENSE_LEVEL, /*!< IOPORT sense low level */\r
+ IOPORT_SENSE_BOTHEDGES, /*!< IOPORT sense both rising and falling edges */\r
+ IOPORT_SENSE_FALLING, /*!< IOPORT sense falling edges */\r
+ IOPORT_SENSE_RISING, /*!< IOPORT sense rising edges */\r
+};\r
+#elif SAM && !SAM4L\r
+/** \brief IOPORT edge sense modes */\r
+enum ioport_sense {\r
+ IOPORT_SENSE_BOTHEDGES, /*!< IOPORT sense both rising and falling edges */\r
+ IOPORT_SENSE_FALLING, /*!< IOPORT sense falling edges */\r
+ IOPORT_SENSE_RISING, /*!< IOPORT sense rising edges */\r
+ IOPORT_SENSE_LEVEL_LOW, /*!< IOPORT sense low level */\r
+ IOPORT_SENSE_LEVEL_HIGH,/*!< IOPORT sense High level */\r
+};\r
+#else\r
+enum ioport_sense {\r
+ IOPORT_SENSE_BOTHEDGES, /*!< IOPORT sense both rising and falling edges */\r
+ IOPORT_SENSE_RISING, /*!< IOPORT sense rising edges */\r
+ IOPORT_SENSE_FALLING, /*!< IOPORT sense falling edges */\r
+};\r
+#endif\r
+\r
+\r
+#if XMEGA\r
+# include "xmega/ioport.h"\r
+# if defined(IOPORT_XMEGA_COMPAT)\r
+# include "xmega/ioport_compat.h"\r
+# endif\r
+#elif MEGA\r
+# include "mega/ioport.h"\r
+#elif UC3\r
+# include "uc3/ioport.h"\r
+#elif SAM\r
+# if SAM4L\r
+# include "sam/ioport_gpio.h"\r
+# elif SAMD20\r
+# include "sam0/ioport.h"\r
+# else\r
+# include "sam/ioport_pio.h"\r
+# endif\r
+#endif\r
+\r
+/**\r
+ * \brief Initializes the IOPORT service, ready for use.\r
+ *\r
+ * This function must be called before using any other functions in the IOPORT\r
+ * service.\r
+ */\r
+static inline void ioport_init(void)\r
+{\r
+ arch_ioport_init();\r
+}\r
+\r
+/**\r
+ * \brief Enable an IOPORT pin, based on a pin created with \ref\r
+ * IOPORT_CREATE_PIN().\r
+ *\r
+ * \param pin IOPORT pin to enable\r
+ */\r
+static inline void ioport_enable_pin(ioport_pin_t pin)\r
+{\r
+ arch_ioport_enable_pin(pin);\r
+}\r
+\r
+/**\r
+ * \brief Enable multiple pins in a single IOPORT port.\r
+ *\r
+ * \param port IOPORT port to enable\r
+ * \param mask Mask of pins within the port to enable\r
+ */\r
+static inline void ioport_enable_port(ioport_port_t port,\r
+ ioport_port_mask_t mask)\r
+{\r
+ arch_ioport_enable_port(port, mask);\r
+}\r
+\r
+/**\r
+ * \brief Disable IOPORT pin, based on a pin created with \ref\r
+ * IOPORT_CREATE_PIN().\r
+ *\r
+ * \param pin IOPORT pin to disable\r
+ */\r
+static inline void ioport_disable_pin(ioport_pin_t pin)\r
+{\r
+ arch_ioport_disable_pin(pin);\r
+}\r
+\r
+/**\r
+ * \brief Disable multiple pins in a single IOPORT port.\r
+ *\r
+ * \param port IOPORT port to disable\r
+ * \param mask Pin mask of pins to disable\r
+ */\r
+static inline void ioport_disable_port(ioport_port_t port,\r
+ ioport_port_mask_t mask)\r
+{\r
+ arch_ioport_disable_port(port, mask);\r
+}\r
+\r
+/**\r
+ * \brief Set multiple pin modes in a single IOPORT port, such as pull-up,\r
+ * pull-down, etc. configuration.\r
+ *\r
+ * \param port IOPORT port to configure\r
+ * \param mask Pin mask of pins to configure\r
+ * \param mode Mode masks to configure for the specified pins (\ref\r
+ * ioport_modes)\r
+ */\r
+static inline void ioport_set_port_mode(ioport_port_t port,\r
+ ioport_port_mask_t mask, ioport_mode_t mode)\r
+{\r
+ arch_ioport_set_port_mode(port, mask, mode);\r
+}\r
+\r
+/**\r
+ * \brief Set pin mode for one single IOPORT pin.\r
+ *\r
+ * \param pin IOPORT pin to configure\r
+ * \param mode Mode masks to configure for the specified pin (\ref ioport_modes)\r
+ */\r
+static inline void ioport_set_pin_mode(ioport_pin_t pin, ioport_mode_t mode)\r
+{\r
+ arch_ioport_set_pin_mode(pin, mode);\r
+}\r
+\r
+/**\r
+ * \brief Reset multiple pin modes in a specified IOPORT port to defaults.\r
+ *\r
+ * \param port IOPORT port to configure\r
+ * \param mask Mask of pins whose mode configuration is to be reset\r
+ */\r
+static inline void ioport_reset_port_mode(ioport_port_t port,\r
+ ioport_port_mask_t mask)\r
+{\r
+ arch_ioport_set_port_mode(port, mask, 0);\r
+}\r
+\r
+/**\r
+ * \brief Reset pin mode configuration for a single IOPORT pin\r
+ *\r
+ * \param pin IOPORT pin to configure\r
+ */\r
+static inline void ioport_reset_pin_mode(ioport_pin_t pin)\r
+{\r
+ arch_ioport_set_pin_mode(pin, 0);\r
+}\r
+\r
+/**\r
+ * \brief Set I/O direction for a group of pins in a single IOPORT.\r
+ *\r
+ * \param port IOPORT port to configure\r
+ * \param mask Pin mask of pins to configure\r
+ * \param dir Direction to set for the specified pins (\ref ioport_direction)\r
+ */\r
+static inline void ioport_set_port_dir(ioport_port_t port,\r
+ ioport_port_mask_t mask, enum ioport_direction dir)\r
+{\r
+ arch_ioport_set_port_dir(port, mask, dir);\r
+}\r
+\r
+/**\r
+ * \brief Set direction for a single IOPORT pin.\r
+ *\r
+ * \param pin IOPORT pin to configure\r
+ * \param dir Direction to set for the specified pin (\ref ioport_direction)\r
+ */\r
+static inline void ioport_set_pin_dir(ioport_pin_t pin,\r
+ enum ioport_direction dir)\r
+{\r
+ arch_ioport_set_pin_dir(pin, dir);\r
+}\r
+\r
+/**\r
+ * \brief Set an IOPORT pin to a specified logical value.\r
+ *\r
+ * \param pin IOPORT pin to configure\r
+ * \param level Logical value of the pin\r
+ */\r
+static inline void ioport_set_pin_level(ioport_pin_t pin, bool level)\r
+{\r
+ arch_ioport_set_pin_level(pin, level);\r
+}\r
+\r
+/**\r
+ * \brief Set a group of IOPORT pins in a single port to a specified logical\r
+ * value.\r
+ *\r
+ * \param port IOPORT port to write to\r
+ * \param mask Pin mask of pins to modify\r
+ * \param level Level of the pins to be modified\r
+ */\r
+static inline void ioport_set_port_level(ioport_port_t port,\r
+ ioport_port_mask_t mask, ioport_port_mask_t level)\r
+{\r
+ arch_ioport_set_port_level(port, mask, level);\r
+}\r
+\r
+/**\r
+ * \brief Get current value of an IOPORT pin, which has been configured as an\r
+ * input.\r
+ *\r
+ * \param pin IOPORT pin to read\r
+ * \return Current logical value of the specified pin\r
+ */\r
+static inline bool ioport_get_pin_level(ioport_pin_t pin)\r
+{\r
+ return arch_ioport_get_pin_level(pin);\r
+}\r
+\r
+/**\r
+ * \brief Get current value of several IOPORT pins in a single port, which have\r
+ * been configured as an inputs.\r
+ *\r
+ * \param port IOPORT port to read\r
+ * \param mask Pin mask of pins to read\r
+ * \return Logical levels of the specified pins from the read port, returned as\r
+ * a mask.\r
+ */\r
+static inline ioport_port_mask_t ioport_get_port_level(ioport_pin_t port,\r
+ ioport_port_mask_t mask)\r
+{\r
+ return arch_ioport_get_port_level(port, mask);\r
+}\r
+\r
+/**\r
+ * \brief Toggle the value of an IOPORT pin, which has previously configured as\r
+ * an output.\r
+ *\r
+ * \param pin IOPORT pin to toggle\r
+ */\r
+static inline void ioport_toggle_pin_level(ioport_pin_t pin)\r
+{\r
+ arch_ioport_toggle_pin_level(pin);\r
+}\r
+\r
+/**\r
+ * \brief Toggle the values of several IOPORT pins located in a single port.\r
+ *\r
+ * \param port IOPORT port to modify\r
+ * \param mask Pin mask of pins to toggle\r
+ */\r
+static inline void ioport_toggle_port_level(ioport_port_t port,\r
+ ioport_port_mask_t mask)\r
+{\r
+ arch_ioport_toggle_port_level(port, mask);\r
+}\r
+\r
+/**\r
+ * \brief Set the pin sense mode of a single IOPORT pin.\r
+ *\r
+ * \param pin IOPORT pin to configure\r
+ * \param pin_sense Edge to sense for the pin (\ref ioport_sense)\r
+ */\r
+static inline void ioport_set_pin_sense_mode(ioport_pin_t pin,\r
+ enum ioport_sense pin_sense)\r
+{\r
+ arch_ioport_set_pin_sense_mode(pin, pin_sense);\r
+}\r
+\r
+/**\r
+ * \brief Set the pin sense mode of a multiple IOPORT pins on a single port.\r
+ *\r
+ * \param port IOPORT port to configure\r
+ * \param mask Bitmask if pins whose edge sense is to be configured\r
+ * \param pin_sense Edge to sense for the pins (\ref ioport_sense)\r
+ */\r
+static inline void ioport_set_port_sense_mode(ioport_port_t port,\r
+ ioport_port_mask_t mask,\r
+ enum ioport_sense pin_sense)\r
+{\r
+ arch_ioport_set_port_sense_mode(port, mask, pin_sense);\r
+}\r
+\r
+/**\r
+ * \brief Convert a pin ID into a its port ID.\r
+ *\r
+ * \param pin IOPORT pin ID to convert\r
+ * \retval Port ID for the given pin ID\r
+ */\r
+static inline ioport_port_t ioport_pin_to_port_id(ioport_pin_t pin)\r
+{\r
+ return arch_ioport_pin_to_port_id(pin);\r
+}\r
+\r
+/**\r
+ * \brief Convert a pin ID into a bitmask mask for the given pin on its port.\r
+ *\r
+ * \param pin IOPORT pin ID to convert\r
+ * \retval Bitmask with a bit set that corresponds to the given pin ID in its port\r
+ */\r
+static inline ioport_port_mask_t ioport_pin_to_mask(ioport_pin_t pin)\r
+{\r
+ return arch_ioport_pin_to_mask(pin);\r
+}\r
+\r
+/** @} */\r
+\r
+/**\r
+ * \page ioport_quickstart Quick start guide for the common IOPORT service\r
+ *\r
+ * This is the quick start guide for the \ref ioport_group, with\r
+ * step-by-step instructions on how to configure and use the service in a\r
+ * selection of use cases.\r
+ *\r
+ * The use cases contain several code fragments. The code fragments in the\r
+ * steps for setup can be copied into a custom initialization function, while\r
+ * the steps for usage can be copied into, e.g., the main application function.\r
+ *\r
+ * \section ioport_quickstart_basic Basic use case\r
+ * In this use case we will configure one IO pin for button input and one for\r
+ * LED control. Then it will read the button state and output it on the LED.\r
+ *\r
+ * \section ioport_quickstart_basic_setup Setup steps\r
+ *\r
+ * \subsection ioport_quickstart_basic_setup_code Example code\r
+ * \code\r
+ * #define MY_LED IOPORT_CREATE_PIN(PORTA, 5)\r
+ * #define MY_BUTTON IOPORT_CREATE_PIN(PORTA, 6)\r
+ *\r
+ * ioport_init();\r
+ *\r
+ * ioport_set_pin_dir(MY_LED, IOPORT_DIR_OUTPUT);\r
+ * ioport_set_pin_dir(MY_BUTTON, IOPORT_DIR_INPUT);\r
+ * ioport_set_pin_mode(MY_BUTTON, IOPORT_MODE_PULLUP);\r
+ * \endcode\r
+ *\r
+ * \subsection ioport_quickstart_basic_setup_flow Workflow\r
+ * -# It's useful to give the GPIOs symbolic names and this can be done with\r
+ * the \ref IOPORT_CREATE_PIN macro. We define one for a LED and one for a\r
+ * button.\r
+ * - \code\r
+ * #define MY_LED IOPORT_CREATE_PIN(PORTA, 5)\r
+ * #define MY_BUTTON IOPORT_CREATE_PIN(PORTA, 6)\r
+ * \endcode\r
+ * - \note The usefulness of the \ref IOPORT_CREATE_PIN macro and port names\r
+ * differ between architectures:\r
+ * - MEGA, MEGA_RF and XMEGA: Use \ref IOPORT_CREATE_PIN macro with port definitions\r
+ * PORTA, PORTB ...\r
+ * - UC3: Most convenient to pick up the device header file pin definition\r
+ * and us it directly. E.g.: AVR32_PIN_PB06\r
+ * - SAM: Most convenient to pick up the device header file pin definition\r
+ * and us it directly. E.g.: PIO_PA5_IDX<br>\r
+ * \ref IOPORT_CREATE_PIN can also be used with port definitions\r
+ * PIOA, PIOB ...\r
+ * -# Initialize the ioport service. This typically enables the IO module if\r
+ * needed.\r
+ * - \code ioport_init(); \endcode\r
+ * -# Set the LED GPIO as output:\r
+ * - \code ioport_set_pin_dir(MY_LED, IOPORT_DIR_OUTPUT); \endcode\r
+ * -# Set the button GPIO as input:\r
+ * - \code ioport_set_pin_dir(MY_BUTTON, IOPORT_DIR_INPUT); \endcode\r
+ * -# Enable pull-up for the button GPIO:\r
+ * - \code ioport_set_pin_mode(MY_BUTTON, IOPORT_MODE_PULLUP); \endcode\r
+ *\r
+ * \section ioport_quickstart_basic_usage Usage steps\r
+ *\r
+ * \subsection ioport_quickstart_basic_usage_code Example code\r
+ * \code\r
+ * bool value;\r
+ *\r
+ * value = ioport_get_pin_level(MY_BUTTON);\r
+ * ioport_set_pin_level(MY_LED, value);\r
+ * \endcode\r
+ *\r
+ * \subsection ioport_quickstart_basic_usage_flow Workflow\r
+ * -# Define a boolean variable for state storage:\r
+ * - \code bool value; \endcode\r
+ * -# Read out the button level into variable value:\r
+ * - \code value = ioport_get_pin_level(MY_BUTTON); \endcode\r
+ * -# Set the LED to read out value from the button:\r
+ * - \code ioport_set_pin_level(MY_LED, value); \endcode\r
+ *\r
+ * \section ioport_quickstart_advanced Advanced use cases\r
+ * - \subpage ioport_quickstart_use_case_1 : Port access\r
+ */\r
+\r
+/**\r
+ * \page ioport_quickstart_use_case_1 Advanced use case doing port access\r
+ *\r
+ * In this case we will read out the pins from one whole port and write the\r
+ * read value to another port.\r
+ *\r
+ * \section ioport_quickstart_use_case_1_setup Setup steps\r
+ *\r
+ * \subsection ioport_quickstart_use_case_1_setup_code Example code\r
+ * \code\r
+ * #define IN_PORT IOPORT_PORTA\r
+ * #define OUT_PORT IOPORT_PORTB\r
+ * #define MASK 0x00000060\r
+ *\r
+ * ioport_init();\r
+ *\r
+ * ioport_set_port_dir(IN_PORT, MASK, IOPORT_DIR_INPUT);\r
+ * ioport_set_port_dir(OUT_PORT, MASK, IOPORT_DIR_OUTPUT);\r
+ * \endcode\r
+ *\r
+ * \subsection ioport_quickstart_basic_setup_flow Workflow\r
+ * -# It's useful to give the ports symbolic names:\r
+ * - \code\r
+ * #define IN_PORT IOPORT_PORTA\r
+ * #define OUT_PORT IOPORT_PORTB\r
+ * \endcode\r
+ * - \note The port names differ between architectures:\r
+ * - MEGA_RF, MEGA and XMEGA: There are predefined names for ports: IOPORT_PORTA,\r
+ * IOPORT_PORTB ...\r
+ * - UC3: Use the index value of the different IO blocks: 0, 1 ...\r
+ * - SAM: There are predefined names for ports: IOPORT_PIOA, IOPORT_PIOB\r
+ * ...\r
+ * -# Also useful to define a mask for the bits to work with:\r
+ * - \code #define MASK 0x00000060 \endcode\r
+ * -# Initialize the ioport service. This typically enables the IO module if\r
+ * needed.\r
+ * - \code ioport_init(); \endcode\r
+ * -# Set one of the ports as input:\r
+ * - \code ioport_set_pin_dir(IN_PORT, MASK, IOPORT_DIR_INPUT); \endcode\r
+ * -# Set the other port as output:\r
+ * - \code ioport_set_pin_dir(OUT_PORT, MASK, IOPORT_DIR_OUTPUT); \endcode\r
+ *\r
+ * \section ioport_quickstart_basic_usage Usage steps\r
+ *\r
+ * \subsection ioport_quickstart_basic_usage_code Example code\r
+ * \code\r
+ * ioport_port_mask_t value;\r
+ *\r
+ * value = ioport_get_port_level(IN_PORT, MASK);\r
+ * ioport_set_port_level(OUT_PORT, MASK, value);\r
+ * \endcode\r
+ *\r
+ * \subsection ioport_quickstart_basic_usage_flow Workflow\r
+ * -# Define a variable for port date storage:\r
+ * - \code ioport_port_mask_t value; \endcode\r
+ * -# Read out from one port:\r
+ * - \code value = ioport_get_port_level(IN_PORT, MASK); \endcode\r
+ * -# Put the read data out on the other port:\r
+ * - \code ioport_set_port_level(OUT_PORT, MASK, value); \endcode\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* IOPORT_H */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief SAM architecture specific IOPORT service implementation header file.\r
+ *\r
+ * Copyright (c) 2012 - 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+#ifndef IOPORT_SAM_H\r
+#define IOPORT_SAM_H\r
+\r
+#include <sysclk.h>\r
+\r
+#define IOPORT_CREATE_PIN(port, pin) ((IOPORT_ ## port) * 32 + (pin))\r
+#define IOPORT_BASE_ADDRESS (uintptr_t)PIOA\r
+#define IOPORT_PIO_OFFSET ((uintptr_t)PIOB - (uintptr_t)PIOA)\r
+\r
+#define IOPORT_PIOA 0\r
+#define IOPORT_PIOB 1\r
+#define IOPORT_PIOC 2\r
+#define IOPORT_PIOD 3\r
+#define IOPORT_PIOE 4\r
+#define IOPORT_PIOF 5\r
+\r
+/**\r
+ * \weakgroup ioport_group\r
+ * \section ioport_modes IOPORT Modes\r
+ *\r
+ * For details on these please see the SAM Manual.\r
+ *\r
+ * @{\r
+ */\r
+\r
+/** \name IOPORT Mode bit definitions */\r
+/** @{ */\r
+#define IOPORT_MODE_MUX_MASK (0x7 << 0) /*!< MUX bits mask */\r
+#define IOPORT_MODE_MUX_BIT0 ( 1 << 0) /*!< MUX BIT0 mask */\r
+\r
+#if SAM3N || SAM3S || SAM4S || SAM4E || SAM4N\r
+#define IOPORT_MODE_MUX_BIT1 ( 1 << 1) /*!< MUX BIT1 mask */\r
+#endif\r
+\r
+#define IOPORT_MODE_MUX_A ( 0 << 0) /*!< MUX function A */\r
+#define IOPORT_MODE_MUX_B ( 1 << 0) /*!< MUX function B */\r
+\r
+#if SAM3N || SAM3S || SAM4S || SAM4E || SAM4N\r
+#define IOPORT_MODE_MUX_C ( 2 << 0) /*!< MUX function C */\r
+#define IOPORT_MODE_MUX_D ( 3 << 0) /*!< MUX function D */\r
+#endif\r
+\r
+#define IOPORT_MODE_PULLUP ( 1 << 3) /*!< Pull-up */\r
+\r
+#if SAM3N || SAM3S || SAM4S || SAM4E || SAM4N\r
+#define IOPORT_MODE_PULLDOWN ( 1 << 4) /*!< Pull-down */\r
+#endif\r
+\r
+#define IOPORT_MODE_OPEN_DRAIN ( 1 << 5) /*!< Open drain */\r
+\r
+#define IOPORT_MODE_GLITCH_FILTER ( 1 << 6) /*!< Glitch filter */\r
+#define IOPORT_MODE_DEBOUNCE ( 1 << 7) /*!< Input debounce */\r
+/** @} */\r
+\r
+/** @} */\r
+\r
+typedef uint32_t ioport_mode_t;\r
+typedef uint32_t ioport_pin_t;\r
+typedef uint32_t ioport_port_t;\r
+typedef uint32_t ioport_port_mask_t;\r
+\r
+__always_inline static ioport_port_t arch_ioport_pin_to_port_id(ioport_pin_t pin)\r
+{\r
+ return pin >> 5;\r
+}\r
+\r
+__always_inline static Pio *arch_ioport_port_to_base(ioport_port_t port)\r
+{\r
+ return (Pio *)((uintptr_t)IOPORT_BASE_ADDRESS +\r
+ (IOPORT_PIO_OFFSET * port));\r
+}\r
+\r
+__always_inline static Pio *arch_ioport_pin_to_base(ioport_pin_t pin)\r
+{\r
+ return arch_ioport_port_to_base(arch_ioport_pin_to_port_id(pin));\r
+}\r
+\r
+__always_inline static ioport_port_mask_t arch_ioport_pin_to_mask(ioport_pin_t pin)\r
+{\r
+ return 1U << (pin & 0x1F);\r
+}\r
+\r
+__always_inline static void arch_ioport_init(void)\r
+{\r
+#ifdef ID_PIOA\r
+ sysclk_enable_peripheral_clock(ID_PIOA);\r
+#endif\r
+#ifdef ID_PIOB\r
+ sysclk_enable_peripheral_clock(ID_PIOB);\r
+#endif\r
+#ifdef ID_PIOC\r
+ sysclk_enable_peripheral_clock(ID_PIOC);\r
+#endif\r
+#ifdef ID_PIOD\r
+ sysclk_enable_peripheral_clock(ID_PIOD);\r
+#endif\r
+#ifdef ID_PIOE\r
+ sysclk_enable_peripheral_clock(ID_PIOE);\r
+#endif\r
+#ifdef ID_PIOF\r
+ sysclk_enable_peripheral_clock(ID_PIOF);\r
+#endif\r
+}\r
+\r
+__always_inline static void arch_ioport_enable_port(ioport_port_t port,\r
+ ioport_port_mask_t mask)\r
+{\r
+ arch_ioport_port_to_base(port)->PIO_PER = mask;\r
+}\r
+\r
+__always_inline static void arch_ioport_disable_port(ioport_port_t port,\r
+ ioport_port_mask_t mask)\r
+{\r
+ arch_ioport_port_to_base(port)->PIO_PDR = mask;\r
+}\r
+\r
+__always_inline static void arch_ioport_enable_pin(ioport_pin_t pin)\r
+{\r
+ arch_ioport_enable_port(arch_ioport_pin_to_port_id(pin),\r
+ arch_ioport_pin_to_mask(pin));\r
+}\r
+\r
+__always_inline static void arch_ioport_disable_pin(ioport_pin_t pin)\r
+{\r
+ arch_ioport_disable_port(arch_ioport_pin_to_port_id(pin),\r
+ arch_ioport_pin_to_mask(pin));\r
+}\r
+\r
+__always_inline static void arch_ioport_set_port_mode(ioport_port_t port,\r
+ ioport_port_mask_t mask, ioport_mode_t mode)\r
+{\r
+ Pio *base = arch_ioport_port_to_base(port);\r
+\r
+ if (mode & IOPORT_MODE_PULLUP) {\r
+ base->PIO_PUER = mask;\r
+ } else {\r
+ base->PIO_PUDR = mask;\r
+ }\r
+\r
+#if defined(IOPORT_MODE_PULLDOWN)\r
+ if (mode & IOPORT_MODE_PULLDOWN) {\r
+ base->PIO_PPDER = mask;\r
+ } else {\r
+ base->PIO_PPDDR = mask;\r
+ }\r
+#endif\r
+\r
+ if (mode & IOPORT_MODE_OPEN_DRAIN) {\r
+ base->PIO_MDER = mask;\r
+ } else {\r
+ base->PIO_MDDR = mask;\r
+ }\r
+\r
+ if (mode & (IOPORT_MODE_GLITCH_FILTER | IOPORT_MODE_DEBOUNCE)) {\r
+ base->PIO_IFER = mask;\r
+ } else {\r
+ base->PIO_IFDR = mask;\r
+ }\r
+\r
+ if (mode & IOPORT_MODE_DEBOUNCE) {\r
+#if SAM3U || SAM3XA\r
+ base->PIO_DIFSR = mask;\r
+#else\r
+ base->PIO_IFSCER = mask;\r
+#endif\r
+ } else {\r
+#if SAM3U || SAM3XA\r
+ base->PIO_SCIFSR = mask;\r
+#else\r
+ base->PIO_IFSCDR = mask;\r
+#endif\r
+ }\r
+\r
+#if !defined(IOPORT_MODE_MUX_BIT1)\r
+ if (mode & IOPORT_MODE_MUX_BIT0) {\r
+ base->PIO_ABSR |= mask;\r
+ } else {\r
+ base->PIO_ABSR &= ~mask;\r
+ }\r
+#else\r
+ if (mode & IOPORT_MODE_MUX_BIT0) {\r
+ base->PIO_ABCDSR[0] |= mask;\r
+ } else {\r
+ base->PIO_ABCDSR[0] &= ~mask;\r
+ }\r
+\r
+ if (mode & IOPORT_MODE_MUX_BIT1) {\r
+ base->PIO_ABCDSR[1] |= mask;\r
+ } else {\r
+ base->PIO_ABCDSR[1] &= ~mask;\r
+ }\r
+#endif\r
+}\r
+\r
+__always_inline static void arch_ioport_set_pin_mode(ioport_pin_t pin,\r
+ ioport_mode_t mode)\r
+{\r
+ arch_ioport_set_port_mode(arch_ioport_pin_to_port_id(pin),\r
+ arch_ioport_pin_to_mask(pin), mode);\r
+}\r
+\r
+__always_inline static void arch_ioport_set_port_dir(ioport_port_t port,\r
+ ioport_port_mask_t mask, enum ioport_direction group_direction)\r
+{\r
+ Pio *base = arch_ioport_port_to_base(port);\r
+\r
+ if (group_direction == IOPORT_DIR_OUTPUT) {\r
+ base->PIO_OER = mask;\r
+ } else if (group_direction == IOPORT_DIR_INPUT) {\r
+ base->PIO_ODR = mask;\r
+ }\r
+\r
+ base->PIO_OWER = mask;\r
+}\r
+\r
+__always_inline static void arch_ioport_set_pin_dir(ioport_pin_t pin,\r
+ enum ioport_direction dir)\r
+{\r
+ Pio *base = arch_ioport_pin_to_base(pin);\r
+\r
+ if (dir == IOPORT_DIR_OUTPUT) {\r
+ base->PIO_OER = arch_ioport_pin_to_mask(pin);\r
+ } else if (dir == IOPORT_DIR_INPUT) {\r
+ base->PIO_ODR = arch_ioport_pin_to_mask(pin);\r
+ }\r
+\r
+ base->PIO_OWER = arch_ioport_pin_to_mask(pin);\r
+}\r
+\r
+__always_inline static void arch_ioport_set_pin_level(ioport_pin_t pin,\r
+ bool level)\r
+{\r
+ Pio *base = arch_ioport_pin_to_base(pin);\r
+\r
+ if (level) {\r
+ base->PIO_SODR = arch_ioport_pin_to_mask(pin);\r
+ } else {\r
+ base->PIO_CODR = arch_ioport_pin_to_mask(pin);\r
+ }\r
+}\r
+\r
+__always_inline static void arch_ioport_set_port_level(ioport_port_t port,\r
+ ioport_port_mask_t mask, ioport_port_mask_t level)\r
+{\r
+ Pio *base = arch_ioport_port_to_base(port);\r
+\r
+ base->PIO_SODR = mask & level;\r
+ base->PIO_CODR = mask & ~level;\r
+}\r
+\r
+__always_inline static bool arch_ioport_get_pin_level(ioport_pin_t pin)\r
+{\r
+ return arch_ioport_pin_to_base(pin)->PIO_PDSR & arch_ioport_pin_to_mask(pin);\r
+}\r
+\r
+__always_inline static ioport_port_mask_t arch_ioport_get_port_level(\r
+ ioport_port_t port, ioport_port_mask_t mask)\r
+{\r
+ return arch_ioport_port_to_base(port)->PIO_PDSR & mask;\r
+}\r
+\r
+__always_inline static void arch_ioport_toggle_pin_level(ioport_pin_t pin)\r
+{\r
+ Pio *port = arch_ioport_pin_to_base(pin);\r
+ ioport_port_mask_t mask = arch_ioport_pin_to_mask(pin);\r
+\r
+ if (port->PIO_PDSR & arch_ioport_pin_to_mask(pin)) {\r
+ port->PIO_CODR = mask;\r
+ } else {\r
+ port->PIO_SODR = mask;\r
+ }\r
+}\r
+\r
+__always_inline static void arch_ioport_toggle_port_level(ioport_port_t port,\r
+ ioport_port_mask_t mask)\r
+{\r
+ arch_ioport_port_to_base(port)->PIO_ODSR ^= mask;\r
+}\r
+\r
+__always_inline static void arch_ioport_set_port_sense_mode(ioport_port_t port,\r
+ ioport_port_mask_t mask, enum ioport_sense pin_sense)\r
+{\r
+ Pio *base = arch_ioport_port_to_base(port);\r
+ /* AIMMR ELSR FRLHSR\r
+ * 0 X X IOPORT_SENSE_BOTHEDGES (Default)\r
+ * 1 0 0 IOPORT_SENSE_FALLING\r
+ * 1 0 1 IOPORT_SENSE_RISING\r
+ * 1 1 0 IOPORT_SENSE_LEVEL_LOW\r
+ * 1 1 1 IOPORT_SENSE_LEVEL_HIGH\r
+ */\r
+ switch(pin_sense) {\r
+ case IOPORT_SENSE_LEVEL_LOW:\r
+ base->PIO_LSR = mask;\r
+ base->PIO_FELLSR = mask;\r
+ break;\r
+ case IOPORT_SENSE_LEVEL_HIGH:\r
+ base->PIO_LSR = mask;\r
+ base->PIO_REHLSR = mask;\r
+ break;\r
+ case IOPORT_SENSE_FALLING:\r
+ base->PIO_ESR = mask;\r
+ base->PIO_FELLSR = mask;\r
+ break;\r
+ case IOPORT_SENSE_RISING:\r
+ base->PIO_ESR = mask;\r
+ base->PIO_REHLSR = mask;\r
+ break;\r
+ default:\r
+ base->PIO_AIMDR = mask;\r
+ return;\r
+ }\r
+ base->PIO_AIMER = mask;\r
+}\r
+\r
+__always_inline static void arch_ioport_set_pin_sense_mode(ioport_pin_t pin,\r
+ enum ioport_sense pin_sense)\r
+{\r
+ arch_ioport_set_port_sense_mode(arch_ioport_pin_to_port_id(pin),\r
+ arch_ioport_pin_to_mask(pin), pin_sense);\r
+}\r
+\r
+#endif /* IOPORT_SAM_H */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Global interrupt management for 8- and 32-bit AVR\r
+ *\r
+ * Copyright (c) 2010-2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+#ifndef UTILS_INTERRUPT_H\r
+#define UTILS_INTERRUPT_H\r
+\r
+#include <parts.h>\r
+\r
+#if XMEGA || MEGA || TINY\r
+# include "interrupt/interrupt_avr8.h"\r
+#elif UC3\r
+# include "interrupt/interrupt_avr32.h"\r
+#elif SAM3S || SAM3N || SAM3XA || SAM3U || SAM4S || SAM4L || SAM4E || SAMD20 || SAM\r
+# include "interrupt/interrupt_sam_nvic.h"\r
+#else\r
+# error Unsupported device.\r
+#endif\r
+\r
+/**\r
+ * \defgroup interrupt_group Global interrupt management\r
+ *\r
+ * This is a driver for global enabling and disabling of interrupts.\r
+ *\r
+ * @{\r
+ */\r
+\r
+#if defined(__DOXYGEN__)\r
+/**\r
+ * \def CONFIG_INTERRUPT_FORCE_INTC\r
+ * \brief Force usage of the ASF INTC driver\r
+ *\r
+ * Predefine this symbol when preprocessing to force the use of the ASF INTC driver.\r
+ * This is useful to ensure compatibility across compilers and shall be used only when required\r
+ * by the application needs.\r
+ */\r
+# define CONFIG_INTERRUPT_FORCE_INTC\r
+#endif\r
+\r
+//! \name Global interrupt flags\r
+//@{\r
+/**\r
+ * \typedef irqflags_t\r
+ * \brief Type used for holding state of interrupt flag\r
+ */\r
+\r
+/**\r
+ * \def cpu_irq_enable\r
+ * \brief Enable interrupts globally\r
+ */\r
+\r
+/**\r
+ * \def cpu_irq_disable\r
+ * \brief Disable interrupts globally\r
+ */\r
+\r
+/**\r
+ * \fn irqflags_t cpu_irq_save(void)\r
+ * \brief Get and clear the global interrupt flags\r
+ *\r
+ * Use in conjunction with \ref cpu_irq_restore.\r
+ *\r
+ * \return Current state of interrupt flags.\r
+ *\r
+ * \note This function leaves interrupts disabled.\r
+ */\r
+\r
+/**\r
+ * \fn void cpu_irq_restore(irqflags_t flags)\r
+ * \brief Restore global interrupt flags\r
+ *\r
+ * Use in conjunction with \ref cpu_irq_save.\r
+ *\r
+ * \param flags State to set interrupt flag to.\r
+ */\r
+\r
+/**\r
+ * \fn bool cpu_irq_is_enabled_flags(irqflags_t flags)\r
+ * \brief Check if interrupts are globally enabled in supplied flags\r
+ *\r
+ * \param flags Currents state of interrupt flags.\r
+ *\r
+ * \return True if interrupts are enabled.\r
+ */\r
+\r
+/**\r
+ * \def cpu_irq_is_enabled\r
+ * \brief Check if interrupts are globally enabled\r
+ *\r
+ * \return True if interrupts are enabled.\r
+ */\r
+//@}\r
+\r
+//! @}\r
+\r
+/**\r
+ * \ingroup interrupt_group\r
+ * \defgroup interrupt_deprecated_group Deprecated interrupt definitions\r
+ */\r
+\r
+#endif /* UTILS_INTERRUPT_H */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Global interrupt management for SAM D20, SAM3 and SAM4 (NVIC based)\r
+ *\r
+ * Copyright (c) 2012-2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#include "interrupt_sam_nvic.h"\r
+\r
+#if !defined(__DOXYGEN__)\r
+/* Deprecated - global flag to determine the global interrupt state. Required by\r
+ * QTouch library, however new applications should use cpu_irq_is_enabled()\r
+ * which probes the true global interrupt state from the CPU special registers.\r
+ */\r
+volatile bool g_interrupt_enabled = true;\r
+#endif\r
+\r
+void cpu_irq_enter_critical(void)\r
+{\r
+ if (cpu_irq_critical_section_counter == 0) {\r
+ if (cpu_irq_is_enabled()) {\r
+ cpu_irq_disable();\r
+ cpu_irq_prev_interrupt_state = true;\r
+ } else {\r
+ /* Make sure the to save the prev state as false */\r
+ cpu_irq_prev_interrupt_state = false;\r
+ }\r
+\r
+ }\r
+\r
+ cpu_irq_critical_section_counter++;\r
+}\r
+\r
+void cpu_irq_leave_critical(void)\r
+{\r
+ /* Check if the user is trying to leave a critical section when not in a critical section */\r
+ Assert(cpu_irq_critical_section_counter > 0);\r
+\r
+ cpu_irq_critical_section_counter--;\r
+\r
+ /* Only enable global interrupts when the counter reaches 0 and the state of the global interrupt flag\r
+ was enabled when entering critical state */\r
+ if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) {\r
+ cpu_irq_enable();\r
+ }\r
+}\r
+\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Global interrupt management for SAM D20, SAM3 and SAM4 (NVIC based)\r
+ *\r
+ * Copyright (c) 2012-2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef UTILS_INTERRUPT_INTERRUPT_H\r
+#define UTILS_INTERRUPT_INTERRUPT_H\r
+\r
+#include <compiler.h>\r
+#include <parts.h>\r
+\r
+/**\r
+ * \weakgroup interrupt_group\r
+ *\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \name Interrupt Service Routine definition\r
+ *\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \brief Define service routine\r
+ *\r
+ * \note For NVIC devices the interrupt service routines are predefined to\r
+ * add to vector table in binary generation, so there is no service\r
+ * register at run time. The routine collections are in exceptions.h.\r
+ *\r
+ * Usage:\r
+ * \code\r
+ * ISR(foo_irq_handler)\r
+ * {\r
+ * // Function definition\r
+ * ...\r
+ * }\r
+ * \endcode\r
+ *\r
+ * \param func Name for the function.\r
+ */\r
+# define ISR(func) \\r
+ void func (void)\r
+\r
+/**\r
+ * \brief Initialize interrupt vectors\r
+ *\r
+ * For NVIC the interrupt vectors are put in vector table. So nothing\r
+ * to do to initialize them, except defined the vector function with\r
+ * right name.\r
+ *\r
+ * This must be called prior to \ref irq_register_handler.\r
+ */\r
+# define irq_initialize_vectors() \\r
+ do { \\r
+ } while(0)\r
+\r
+/**\r
+ * \brief Register handler for interrupt\r
+ *\r
+ * For NVIC the interrupt vectors are put in vector table. So nothing\r
+ * to do to register them, except defined the vector function with\r
+ * right name.\r
+ *\r
+ * Usage:\r
+ * \code\r
+ * irq_initialize_vectors();\r
+ * irq_register_handler(foo_irq_handler);\r
+ * \endcode\r
+ *\r
+ * \note The function \a func must be defined with the \ref ISR macro.\r
+ * \note The functions prototypes can be found in the device exception header\r
+ * files (exceptions.h).\r
+ */\r
+# define irq_register_handler(int_num, int_prio) \\r
+ NVIC_ClearPendingIRQ( (IRQn_Type)int_num); \\r
+ NVIC_SetPriority( (IRQn_Type)int_num, int_prio); \\r
+ NVIC_EnableIRQ( (IRQn_Type)int_num); \\r
+\r
+//@}\r
+\r
+# define cpu_irq_enable() \\r
+ do { \\r
+ g_interrupt_enabled = true; \\r
+ __DMB(); \\r
+ __enable_irq(); \\r
+ } while (0)\r
+# define cpu_irq_disable() \\r
+ do { \\r
+ __disable_irq(); \\r
+ __DMB(); \\r
+ g_interrupt_enabled = false; \\r
+ } while (0)\r
+\r
+typedef uint32_t irqflags_t;\r
+\r
+#if !defined(__DOXYGEN__)\r
+extern volatile bool g_interrupt_enabled;\r
+#endif\r
+\r
+#define cpu_irq_is_enabled() (__get_PRIMASK() == 0)\r
+\r
+static volatile uint32_t cpu_irq_critical_section_counter;\r
+static volatile bool cpu_irq_prev_interrupt_state;\r
+\r
+static inline irqflags_t cpu_irq_save(void)\r
+{\r
+ irqflags_t flags = cpu_irq_is_enabled();\r
+ cpu_irq_disable();\r
+ return flags;\r
+}\r
+\r
+static inline bool cpu_irq_is_enabled_flags(irqflags_t flags)\r
+{\r
+ return (flags);\r
+}\r
+\r
+static inline void cpu_irq_restore(irqflags_t flags)\r
+{\r
+ if (cpu_irq_is_enabled_flags(flags))\r
+ cpu_irq_enable();\r
+}\r
+\r
+void cpu_irq_enter_critical(void);\r
+void cpu_irq_leave_critical(void);\r
+\r
+/**\r
+ * \weakgroup interrupt_deprecated_group\r
+ * @{\r
+ */\r
+\r
+#define Enable_global_interrupt() cpu_irq_enable()\r
+#define Disable_global_interrupt() cpu_irq_disable()\r
+#define Is_global_interrupt_enabled() cpu_irq_is_enabled()\r
+\r
+//@}\r
+\r
+//@}\r
+\r
+#endif /* UTILS_INTERRUPT_INTERRUPT_H */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Atmel part identification macros\r
+ *\r
+ * Copyright (C) 2012-2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef ATMEL_PARTS_H\r
+#define ATMEL_PARTS_H\r
+\r
+/**\r
+ * \defgroup part_macros_group Atmel part identification macros\r
+ *\r
+ * This collection of macros identify which series and families that the various\r
+ * Atmel parts belong to. These can be used to select part-dependent sections of\r
+ * code at compile time.\r
+ *\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \name Convenience macros for part checking\r
+ * @{\r
+ */\r
+/* ! Check GCC and IAR part definition for 8-bit AVR */\r
+#define AVR8_PART_IS_DEFINED(part) \\r
+ (defined(__ ## part ## __) || defined(__AVR_ ## part ## __))\r
+\r
+/* ! Check GCC and IAR part definition for 32-bit AVR */\r
+#define AVR32_PART_IS_DEFINED(part) \\r
+ (defined(__AT32 ## part ## __) || defined(__AVR32_ ## part ## __))\r
+\r
+/* ! Check GCC and IAR part definition for SAM */\r
+#define SAM_PART_IS_DEFINED(part) (defined(__ ## part ## __))\r
+/** @} */\r
+\r
+/**\r
+ * \defgroup uc3_part_macros_group AVR UC3 parts\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \name AVR UC3 A series\r
+ * @{\r
+ */\r
+#define UC3A0 ( \\r
+ AVR32_PART_IS_DEFINED(UC3A0128) || \\r
+ AVR32_PART_IS_DEFINED(UC3A0256) || \\r
+ AVR32_PART_IS_DEFINED(UC3A0512) \\r
+ )\r
+\r
+#define UC3A1 ( \\r
+ AVR32_PART_IS_DEFINED(UC3A1128) || \\r
+ AVR32_PART_IS_DEFINED(UC3A1256) || \\r
+ AVR32_PART_IS_DEFINED(UC3A1512) \\r
+ )\r
+\r
+#define UC3A3 ( \\r
+ AVR32_PART_IS_DEFINED(UC3A364) || \\r
+ AVR32_PART_IS_DEFINED(UC3A364S) || \\r
+ AVR32_PART_IS_DEFINED(UC3A3128) || \\r
+ AVR32_PART_IS_DEFINED(UC3A3128S) || \\r
+ AVR32_PART_IS_DEFINED(UC3A3256) || \\r
+ AVR32_PART_IS_DEFINED(UC3A3256S) \\r
+ )\r
+\r
+#define UC3A4 ( \\r
+ AVR32_PART_IS_DEFINED(UC3A464) || \\r
+ AVR32_PART_IS_DEFINED(UC3A464S) || \\r
+ AVR32_PART_IS_DEFINED(UC3A4128) || \\r
+ AVR32_PART_IS_DEFINED(UC3A4128S) || \\r
+ AVR32_PART_IS_DEFINED(UC3A4256) || \\r
+ AVR32_PART_IS_DEFINED(UC3A4256S) \\r
+ )\r
+/** @} */\r
+\r
+/**\r
+ * \name AVR UC3 B series\r
+ * @{\r
+ */\r
+#define UC3B0 ( \\r
+ AVR32_PART_IS_DEFINED(UC3B064) || \\r
+ AVR32_PART_IS_DEFINED(UC3B0128) || \\r
+ AVR32_PART_IS_DEFINED(UC3B0256) || \\r
+ AVR32_PART_IS_DEFINED(UC3B0512) \\r
+ )\r
+\r
+#define UC3B1 ( \\r
+ AVR32_PART_IS_DEFINED(UC3B164) || \\r
+ AVR32_PART_IS_DEFINED(UC3B1128) || \\r
+ AVR32_PART_IS_DEFINED(UC3B1256) || \\r
+ AVR32_PART_IS_DEFINED(UC3B1512) \\r
+ )\r
+/** @} */\r
+\r
+/**\r
+ * \name AVR UC3 C series\r
+ * @{\r
+ */\r
+#define UC3C0 ( \\r
+ AVR32_PART_IS_DEFINED(UC3C064C) || \\r
+ AVR32_PART_IS_DEFINED(UC3C0128C) || \\r
+ AVR32_PART_IS_DEFINED(UC3C0256C) || \\r
+ AVR32_PART_IS_DEFINED(UC3C0512C) \\r
+ )\r
+\r
+#define UC3C1 ( \\r
+ AVR32_PART_IS_DEFINED(UC3C164C) || \\r
+ AVR32_PART_IS_DEFINED(UC3C1128C) || \\r
+ AVR32_PART_IS_DEFINED(UC3C1256C) || \\r
+ AVR32_PART_IS_DEFINED(UC3C1512C) \\r
+ )\r
+\r
+#define UC3C2 ( \\r
+ AVR32_PART_IS_DEFINED(UC3C264C) || \\r
+ AVR32_PART_IS_DEFINED(UC3C2128C) || \\r
+ AVR32_PART_IS_DEFINED(UC3C2256C) || \\r
+ AVR32_PART_IS_DEFINED(UC3C2512C) \\r
+ )\r
+/** @} */\r
+\r
+/**\r
+ * \name AVR UC3 D series\r
+ * @{\r
+ */\r
+#define UC3D3 ( \\r
+ AVR32_PART_IS_DEFINED(UC64D3) || \\r
+ AVR32_PART_IS_DEFINED(UC128D3) \\r
+ )\r
+\r
+#define UC3D4 ( \\r
+ AVR32_PART_IS_DEFINED(UC64D4) || \\r
+ AVR32_PART_IS_DEFINED(UC128D4) \\r
+ )\r
+/** @} */\r
+\r
+/**\r
+ * \name AVR UC3 L series\r
+ * @{\r
+ */\r
+#define UC3L0 ( \\r
+ AVR32_PART_IS_DEFINED(UC3L016) || \\r
+ AVR32_PART_IS_DEFINED(UC3L032) || \\r
+ AVR32_PART_IS_DEFINED(UC3L064) \\r
+ )\r
+\r
+#define UC3L0128 ( \\r
+ AVR32_PART_IS_DEFINED(UC3L0128) \\r
+ )\r
+\r
+#define UC3L0256 ( \\r
+ AVR32_PART_IS_DEFINED(UC3L0256) \\r
+ )\r
+\r
+#define UC3L3 ( \\r
+ AVR32_PART_IS_DEFINED(UC64L3U) || \\r
+ AVR32_PART_IS_DEFINED(UC128L3U) || \\r
+ AVR32_PART_IS_DEFINED(UC256L3U) \\r
+ )\r
+\r
+#define UC3L4 ( \\r
+ AVR32_PART_IS_DEFINED(UC64L4U) || \\r
+ AVR32_PART_IS_DEFINED(UC128L4U) || \\r
+ AVR32_PART_IS_DEFINED(UC256L4U) \\r
+ )\r
+\r
+#define UC3L3_L4 (UC3L3 || UC3L4)\r
+/** @} */\r
+\r
+/**\r
+ * \name AVR UC3 families\r
+ * @{\r
+ */\r
+/** AVR UC3 A family */\r
+#define UC3A (UC3A0 || UC3A1 || UC3A3 || UC3A4)\r
+\r
+/** AVR UC3 B family */\r
+#define UC3B (UC3B0 || UC3B1)\r
+\r
+/** AVR UC3 C family */\r
+#define UC3C (UC3C0 || UC3C1 || UC3C2)\r
+\r
+/** AVR UC3 D family */\r
+#define UC3D (UC3D3 || UC3D4)\r
+\r
+/** AVR UC3 L family */\r
+#define UC3L (UC3L0 || UC3L0128 || UC3L0256 || UC3L3_L4)\r
+/** @} */\r
+\r
+/** AVR UC3 product line */\r
+#define UC3 (UC3A || UC3B || UC3C || UC3D || UC3L)\r
+\r
+/** @} */\r
+\r
+/**\r
+ * \defgroup xmega_part_macros_group AVR XMEGA parts\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \name AVR XMEGA A series\r
+ * @{\r
+ */\r
+#define XMEGA_A1 ( \\r
+ AVR8_PART_IS_DEFINED(ATxmega64A1) || \\r
+ AVR8_PART_IS_DEFINED(ATxmega128A1) \\r
+ )\r
+\r
+#define XMEGA_A3 ( \\r
+ AVR8_PART_IS_DEFINED(ATxmega64A3) || \\r
+ AVR8_PART_IS_DEFINED(ATxmega128A3) || \\r
+ AVR8_PART_IS_DEFINED(ATxmega192A3) || \\r
+ AVR8_PART_IS_DEFINED(ATxmega256A3) \\r
+ )\r
+\r
+#define XMEGA_A3B ( \\r
+ AVR8_PART_IS_DEFINED(ATxmega256A3B) \\r
+ )\r
+\r
+#define XMEGA_A4 ( \\r
+ AVR8_PART_IS_DEFINED(ATxmega16A4) || \\r
+ AVR8_PART_IS_DEFINED(ATxmega32A4) \\r
+ )\r
+/** @} */\r
+\r
+/**\r
+ * \name AVR XMEGA AU series\r
+ * @{\r
+ */\r
+#define XMEGA_A1U ( \\r
+ AVR8_PART_IS_DEFINED(ATxmega64A1U) || \\r
+ AVR8_PART_IS_DEFINED(ATxmega128A1U) \\r
+ )\r
+\r
+#define XMEGA_A3U ( \\r
+ AVR8_PART_IS_DEFINED(ATxmega64A3U) || \\r
+ AVR8_PART_IS_DEFINED(ATxmega128A3U) || \\r
+ AVR8_PART_IS_DEFINED(ATxmega192A3U) || \\r
+ AVR8_PART_IS_DEFINED(ATxmega256A3U) \\r
+ )\r
+\r
+#define XMEGA_A3BU ( \\r
+ AVR8_PART_IS_DEFINED(ATxmega256A3BU) \\r
+ )\r
+\r
+#define XMEGA_A4U ( \\r
+ AVR8_PART_IS_DEFINED(ATxmega16A4U) || \\r
+ AVR8_PART_IS_DEFINED(ATxmega32A4U) || \\r
+ AVR8_PART_IS_DEFINED(ATxmega64A4U) || \\r
+ AVR8_PART_IS_DEFINED(ATxmega128A4U) \\r
+ )\r
+/** @} */\r
+\r
+/**\r
+ * \name AVR XMEGA B series\r
+ * @{\r
+ */\r
+#define XMEGA_B1 ( \\r
+ AVR8_PART_IS_DEFINED(ATxmega64B1) || \\r
+ AVR8_PART_IS_DEFINED(ATxmega128B1) \\r
+ )\r
+\r
+#define XMEGA_B3 ( \\r
+ AVR8_PART_IS_DEFINED(ATxmega64B3) || \\r
+ AVR8_PART_IS_DEFINED(ATxmega128B3) \\r
+ )\r
+/** @} */\r
+\r
+/**\r
+ * \name AVR XMEGA C series\r
+ * @{\r
+ */\r
+#define XMEGA_C3 ( \\r
+ AVR8_PART_IS_DEFINED(ATxmega384C3) || \\r
+ AVR8_PART_IS_DEFINED(ATxmega256C3) || \\r
+ AVR8_PART_IS_DEFINED(ATxmega192C3) || \\r
+ AVR8_PART_IS_DEFINED(ATxmega128C3) || \\r
+ AVR8_PART_IS_DEFINED(ATxmega64C3) \\r
+ )\r
+\r
+#define XMEGA_C4 ( \\r
+ AVR8_PART_IS_DEFINED(ATxmega32C4) || \\r
+ AVR8_PART_IS_DEFINED(ATxmega16C4) \\r
+ )\r
+/** @} */\r
+\r
+/**\r
+ * \name AVR XMEGA D series\r
+ * @{\r
+ */\r
+#define XMEGA_D3 ( \\r
+ AVR8_PART_IS_DEFINED(ATxmega64D3) || \\r
+ AVR8_PART_IS_DEFINED(ATxmega128D3) || \\r
+ AVR8_PART_IS_DEFINED(ATxmega192D3) || \\r
+ AVR8_PART_IS_DEFINED(ATxmega256D3) || \\r
+ AVR8_PART_IS_DEFINED(ATxmega384D3) \\r
+ )\r
+\r
+#define XMEGA_D4 ( \\r
+ AVR8_PART_IS_DEFINED(ATxmega16D4) || \\r
+ AVR8_PART_IS_DEFINED(ATxmega32D4) || \\r
+ AVR8_PART_IS_DEFINED(ATxmega64D4) || \\r
+ AVR8_PART_IS_DEFINED(ATxmega128D4) \\r
+ )\r
+/** @} */\r
+\r
+/**\r
+ * \name AVR XMEGA E series\r
+ * @{\r
+ */\r
+#define XMEGA_E5 ( \\r
+ AVR8_PART_IS_DEFINED(ATxmega8E5) || \\r
+ AVR8_PART_IS_DEFINED(ATxmega16E5) || \\r
+ AVR8_PART_IS_DEFINED(ATxmega32E5) \\r
+ )\r
+/** @} */\r
+\r
+\r
+/**\r
+ * \name AVR XMEGA families\r
+ * @{\r
+ */\r
+/** AVR XMEGA A family */\r
+#define XMEGA_A (XMEGA_A1 || XMEGA_A3 || XMEGA_A3B || XMEGA_A4)\r
+\r
+/** AVR XMEGA AU family */\r
+#define XMEGA_AU (XMEGA_A1U || XMEGA_A3U || XMEGA_A3BU || XMEGA_A4U)\r
+\r
+/** AVR XMEGA B family */\r
+#define XMEGA_B (XMEGA_B1 || XMEGA_B3)\r
+\r
+/** AVR XMEGA C family */\r
+#define XMEGA_C (XMEGA_C3 || XMEGA_C4)\r
+\r
+/** AVR XMEGA D family */\r
+#define XMEGA_D (XMEGA_D3 || XMEGA_D4)\r
+\r
+/** AVR XMEGA E family */\r
+#define XMEGA_E (XMEGA_E5)\r
+/** @} */\r
+\r
+\r
+/** AVR XMEGA product line */\r
+#define XMEGA (XMEGA_A || XMEGA_AU || XMEGA_B || XMEGA_C || XMEGA_D || XMEGA_E)\r
+\r
+/** @} */\r
+\r
+/**\r
+ * \defgroup mega_part_macros_group megaAVR parts\r
+ *\r
+ * \note These megaAVR groupings are based on the groups in AVR Libc for the\r
+ * part header files. They are not names of official megaAVR device series or\r
+ * families.\r
+ *\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \name ATmegaxx0/xx1 subgroups\r
+ * @{\r
+ */\r
+#define MEGA_XX0 ( \\r
+ AVR8_PART_IS_DEFINED(ATmega640) || \\r
+ AVR8_PART_IS_DEFINED(ATmega1280) || \\r
+ AVR8_PART_IS_DEFINED(ATmega2560) \\r
+ )\r
+\r
+#define MEGA_XX1 ( \\r
+ AVR8_PART_IS_DEFINED(ATmega1281) || \\r
+ AVR8_PART_IS_DEFINED(ATmega2561) \\r
+ )\r
+/** @} */\r
+\r
+/**\r
+ * \name megaAVR groups\r
+ * @{\r
+ */\r
+/** ATmegaxx0/xx1 group */\r
+#define MEGA_XX0_1 (MEGA_XX0 || MEGA_XX1)\r
+\r
+/** ATmegaxx4 group */\r
+#define MEGA_XX4 ( \\r
+ AVR8_PART_IS_DEFINED(ATmega164A) || \\r
+ AVR8_PART_IS_DEFINED(ATmega164PA) || \\r
+ AVR8_PART_IS_DEFINED(ATmega324A) || \\r
+ AVR8_PART_IS_DEFINED(ATmega324PA) || \\r
+ AVR8_PART_IS_DEFINED(ATmega644) || \\r
+ AVR8_PART_IS_DEFINED(ATmega644A) || \\r
+ AVR8_PART_IS_DEFINED(ATmega644PA) || \\r
+ AVR8_PART_IS_DEFINED(ATmega1284P) || \\r
+ AVR8_PART_IS_DEFINED(ATmega128RFA1) \\r
+ )\r
+\r
+/** ATmegaxx4 group */\r
+#define MEGA_XX4_A ( \\r
+ AVR8_PART_IS_DEFINED(ATmega164A) || \\r
+ AVR8_PART_IS_DEFINED(ATmega164PA) || \\r
+ AVR8_PART_IS_DEFINED(ATmega324A) || \\r
+ AVR8_PART_IS_DEFINED(ATmega324PA) || \\r
+ AVR8_PART_IS_DEFINED(ATmega644A) || \\r
+ AVR8_PART_IS_DEFINED(ATmega644PA) || \\r
+ AVR8_PART_IS_DEFINED(ATmega1284P) \\r
+ )\r
+\r
+/** ATmegaxx8 group */\r
+#define MEGA_XX8 ( \\r
+ AVR8_PART_IS_DEFINED(ATmega48) || \\r
+ AVR8_PART_IS_DEFINED(ATmega48A) || \\r
+ AVR8_PART_IS_DEFINED(ATmega48PA) || \\r
+ AVR8_PART_IS_DEFINED(ATmega88) || \\r
+ AVR8_PART_IS_DEFINED(ATmega88A) || \\r
+ AVR8_PART_IS_DEFINED(ATmega88PA) || \\r
+ AVR8_PART_IS_DEFINED(ATmega168) || \\r
+ AVR8_PART_IS_DEFINED(ATmega168A) || \\r
+ AVR8_PART_IS_DEFINED(ATmega168PA) || \\r
+ AVR8_PART_IS_DEFINED(ATmega328) || \\r
+ AVR8_PART_IS_DEFINED(ATmega328P) \\r
+ )\r
+\r
+/** ATmegaxx8A/P/PA group */\r
+#define MEGA_XX8_A ( \\r
+ AVR8_PART_IS_DEFINED(ATmega48A) || \\r
+ AVR8_PART_IS_DEFINED(ATmega48PA) || \\r
+ AVR8_PART_IS_DEFINED(ATmega88A) || \\r
+ AVR8_PART_IS_DEFINED(ATmega88PA) || \\r
+ AVR8_PART_IS_DEFINED(ATmega168A) || \\r
+ AVR8_PART_IS_DEFINED(ATmega168PA) || \\r
+ AVR8_PART_IS_DEFINED(ATmega328P) \\r
+ )\r
+\r
+/** ATmegaxx group */\r
+#define MEGA_XX ( \\r
+ AVR8_PART_IS_DEFINED(ATmega16) || \\r
+ AVR8_PART_IS_DEFINED(ATmega16A) || \\r
+ AVR8_PART_IS_DEFINED(ATmega32) || \\r
+ AVR8_PART_IS_DEFINED(ATmega32A) || \\r
+ AVR8_PART_IS_DEFINED(ATmega64) || \\r
+ AVR8_PART_IS_DEFINED(ATmega64A) || \\r
+ AVR8_PART_IS_DEFINED(ATmega128) || \\r
+ AVR8_PART_IS_DEFINED(ATmega128A) \\r
+ )\r
+\r
+/** ATmegaxxA/P/PA group */\r
+#define MEGA_XX_A ( \\r
+ AVR8_PART_IS_DEFINED(ATmega16A) || \\r
+ AVR8_PART_IS_DEFINED(ATmega32A) || \\r
+ AVR8_PART_IS_DEFINED(ATmega64A) || \\r
+ AVR8_PART_IS_DEFINED(ATmega128A) \\r
+ )\r
+/** ATmegaxxRFA1 group */\r
+#define MEGA_RFA1 ( \\r
+ AVR8_PART_IS_DEFINED(ATmega128RFA1) \\r
+ )\r
+\r
+/** ATmegaxxRFR2 group */\r
+#define MEGA_RFR2 ( \\r
+ AVR8_PART_IS_DEFINED(ATmega64RFR2) || \\r
+ AVR8_PART_IS_DEFINED(ATmega128RFR2) || \\r
+ AVR8_PART_IS_DEFINED(ATmega256RFR2) \\r
+ )\r
+\r
+\r
+/** ATmegaxxRFxx group */\r
+#define MEGA_RF (MEGA_RFA1 || MEGA_RFR2)\r
+\r
+/**\r
+ * \name ATmegaxx_un0/un1/un2 subgroups\r
+ * @{\r
+ */\r
+#define MEGA_XX_UN0 ( \\r
+ AVR8_PART_IS_DEFINED(ATmega16) || \\r
+ AVR8_PART_IS_DEFINED(ATmega16A) || \\r
+ AVR8_PART_IS_DEFINED(ATmega32) || \\r
+ AVR8_PART_IS_DEFINED(ATmega32A) \\r
+ )\r
+\r
+/** ATmegaxx group without power reduction and\r
+ * And interrupt sense register.\r
+ */\r
+#define MEGA_XX_UN1 ( \\r
+ AVR8_PART_IS_DEFINED(ATmega64) || \\r
+ AVR8_PART_IS_DEFINED(ATmega64A) || \\r
+ AVR8_PART_IS_DEFINED(ATmega128) || \\r
+ AVR8_PART_IS_DEFINED(ATmega128A) \\r
+ )\r
+\r
+/** ATmegaxx group without power reduction and\r
+ * And interrupt sense register.\r
+ */\r
+#define MEGA_XX_UN2 ( \\r
+ AVR8_PART_IS_DEFINED(ATmega169P) || \\r
+ AVR8_PART_IS_DEFINED(ATmega169PA) || \\r
+ AVR8_PART_IS_DEFINED(ATmega329P) || \\r
+ AVR8_PART_IS_DEFINED(ATmega329PA) \\r
+ )\r
+\r
+/** Devices added to complete megaAVR offering.\r
+ * Please do not use this group symbol as it is not intended\r
+ * to be permanent: the devices should be regrouped.\r
+ */\r
+#define MEGA_UNCATEGORIZED ( \\r
+ AVR8_PART_IS_DEFINED(AT90CAN128) || \\r
+ AVR8_PART_IS_DEFINED(AT90CAN32) || \\r
+ AVR8_PART_IS_DEFINED(AT90CAN64) || \\r
+ AVR8_PART_IS_DEFINED(AT90PWM1) || \\r
+ AVR8_PART_IS_DEFINED(AT90PWM216) || \\r
+ AVR8_PART_IS_DEFINED(AT90PWM2B) || \\r
+ AVR8_PART_IS_DEFINED(AT90PWM316) || \\r
+ AVR8_PART_IS_DEFINED(AT90PWM3B) || \\r
+ AVR8_PART_IS_DEFINED(AT90PWM81) || \\r
+ AVR8_PART_IS_DEFINED(AT90USB1286) || \\r
+ AVR8_PART_IS_DEFINED(AT90USB1287) || \\r
+ AVR8_PART_IS_DEFINED(AT90USB162) || \\r
+ AVR8_PART_IS_DEFINED(AT90USB646) || \\r
+ AVR8_PART_IS_DEFINED(AT90USB647) || \\r
+ AVR8_PART_IS_DEFINED(AT90USB82) || \\r
+ AVR8_PART_IS_DEFINED(ATmega1284) || \\r
+ AVR8_PART_IS_DEFINED(ATmega162) || \\r
+ AVR8_PART_IS_DEFINED(ATmega164P) || \\r
+ AVR8_PART_IS_DEFINED(ATmega165A) || \\r
+ AVR8_PART_IS_DEFINED(ATmega165P) || \\r
+ AVR8_PART_IS_DEFINED(ATmega165PA) || \\r
+ AVR8_PART_IS_DEFINED(ATmega168P) || \\r
+ AVR8_PART_IS_DEFINED(ATmega169A) || \\r
+ AVR8_PART_IS_DEFINED(ATmega16M1) || \\r
+ AVR8_PART_IS_DEFINED(ATmega16U2) || \\r
+ AVR8_PART_IS_DEFINED(ATmega16U4) || \\r
+ AVR8_PART_IS_DEFINED(ATmega2564RFR2) || \\r
+ AVR8_PART_IS_DEFINED(ATmega256RFA2) || \\r
+ AVR8_PART_IS_DEFINED(ATmega324P) || \\r
+ AVR8_PART_IS_DEFINED(ATmega325) || \\r
+ AVR8_PART_IS_DEFINED(ATmega3250) || \\r
+ AVR8_PART_IS_DEFINED(ATmega3250A) || \\r
+ AVR8_PART_IS_DEFINED(ATmega3250P) || \\r
+ AVR8_PART_IS_DEFINED(ATmega3250PA) || \\r
+ AVR8_PART_IS_DEFINED(ATmega325A) || \\r
+ AVR8_PART_IS_DEFINED(ATmega325P) || \\r
+ AVR8_PART_IS_DEFINED(ATmega325PA) || \\r
+ AVR8_PART_IS_DEFINED(ATmega329) || \\r
+ AVR8_PART_IS_DEFINED(ATmega3290) || \\r
+ AVR8_PART_IS_DEFINED(ATmega3290A) || \\r
+ AVR8_PART_IS_DEFINED(ATmega3290P) || \\r
+ AVR8_PART_IS_DEFINED(ATmega3290PA) || \\r
+ AVR8_PART_IS_DEFINED(ATmega329A) || \\r
+ AVR8_PART_IS_DEFINED(ATmega32M1) || \\r
+ AVR8_PART_IS_DEFINED(ATmega32U2) || \\r
+ AVR8_PART_IS_DEFINED(ATmega32U4) || \\r
+ AVR8_PART_IS_DEFINED(ATmega48P) || \\r
+ AVR8_PART_IS_DEFINED(ATmega644P) || \\r
+ AVR8_PART_IS_DEFINED(ATmega645) || \\r
+ AVR8_PART_IS_DEFINED(ATmega6450) || \\r
+ AVR8_PART_IS_DEFINED(ATmega6450A) || \\r
+ AVR8_PART_IS_DEFINED(ATmega6450P) || \\r
+ AVR8_PART_IS_DEFINED(ATmega645A) || \\r
+ AVR8_PART_IS_DEFINED(ATmega645P) || \\r
+ AVR8_PART_IS_DEFINED(ATmega649) || \\r
+ AVR8_PART_IS_DEFINED(ATmega6490) || \\r
+ AVR8_PART_IS_DEFINED(ATmega6490A) || \\r
+ AVR8_PART_IS_DEFINED(ATmega6490P) || \\r
+ AVR8_PART_IS_DEFINED(ATmega649A) || \\r
+ AVR8_PART_IS_DEFINED(ATmega649P) || \\r
+ AVR8_PART_IS_DEFINED(ATmega64M1) || \\r
+ AVR8_PART_IS_DEFINED(ATmega64RFA2) || \\r
+ AVR8_PART_IS_DEFINED(ATmega8) || \\r
+ AVR8_PART_IS_DEFINED(ATmega8515) || \\r
+ AVR8_PART_IS_DEFINED(ATmega8535) || \\r
+ AVR8_PART_IS_DEFINED(ATmega88P) || \\r
+ AVR8_PART_IS_DEFINED(ATmega8A) || \\r
+ AVR8_PART_IS_DEFINED(ATmega8U2) \\r
+ )\r
+\r
+/** Unspecified group */\r
+#define MEGA_UNSPECIFIED (MEGA_XX_UN0 || MEGA_XX_UN1 || MEGA_XX_UN2 || \\r
+ MEGA_UNCATEGORIZED)\r
+\r
+/** @} */\r
+\r
+/** megaAVR product line */\r
+#define MEGA (MEGA_XX0_1 || MEGA_XX4 || MEGA_XX8 || MEGA_XX || MEGA_RF || \\r
+ MEGA_UNSPECIFIED)\r
+\r
+/** @} */\r
+\r
+/**\r
+ * \defgroup tiny_part_macros_group tinyAVR parts\r
+ *\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \name tinyAVR groups\r
+ * @{\r
+ */\r
+\r
+/** Devices added to complete tinyAVR offering.\r
+ * Please do not use this group symbol as it is not intended\r
+ * to be permanent: the devices should be regrouped.\r
+ */\r
+#define TINY_UNCATEGORIZED ( \\r
+ AVR8_PART_IS_DEFINED(ATtiny10) || \\r
+ AVR8_PART_IS_DEFINED(ATtiny13) || \\r
+ AVR8_PART_IS_DEFINED(ATtiny13A) || \\r
+ AVR8_PART_IS_DEFINED(ATtiny1634) || \\r
+ AVR8_PART_IS_DEFINED(ATtiny167) || \\r
+ AVR8_PART_IS_DEFINED(ATtiny20) || \\r
+ AVR8_PART_IS_DEFINED(ATtiny2313) || \\r
+ AVR8_PART_IS_DEFINED(ATtiny2313A) || \\r
+ AVR8_PART_IS_DEFINED(ATtiny24) || \\r
+ AVR8_PART_IS_DEFINED(ATtiny24A) || \\r
+ AVR8_PART_IS_DEFINED(ATtiny25) || \\r
+ AVR8_PART_IS_DEFINED(ATtiny26) || \\r
+ AVR8_PART_IS_DEFINED(ATtiny261) || \\r
+ AVR8_PART_IS_DEFINED(ATtiny261A) || \\r
+ AVR8_PART_IS_DEFINED(ATtiny4) || \\r
+ AVR8_PART_IS_DEFINED(ATtiny40) || \\r
+ AVR8_PART_IS_DEFINED(ATtiny4313) || \\r
+ AVR8_PART_IS_DEFINED(ATtiny43U) || \\r
+ AVR8_PART_IS_DEFINED(ATtiny44) || \\r
+ AVR8_PART_IS_DEFINED(ATtiny44A) || \\r
+ AVR8_PART_IS_DEFINED(ATtiny45) || \\r
+ AVR8_PART_IS_DEFINED(ATtiny461) || \\r
+ AVR8_PART_IS_DEFINED(ATtiny461A) || \\r
+ AVR8_PART_IS_DEFINED(ATtiny48) || \\r
+ AVR8_PART_IS_DEFINED(ATtiny5) || \\r
+ AVR8_PART_IS_DEFINED(ATtiny828) || \\r
+ AVR8_PART_IS_DEFINED(ATtiny84) || \\r
+ AVR8_PART_IS_DEFINED(ATtiny84A) || \\r
+ AVR8_PART_IS_DEFINED(ATtiny85) || \\r
+ AVR8_PART_IS_DEFINED(ATtiny861) || \\r
+ AVR8_PART_IS_DEFINED(ATtiny861A) || \\r
+ AVR8_PART_IS_DEFINED(ATtiny87) || \\r
+ AVR8_PART_IS_DEFINED(ATtiny88) || \\r
+ AVR8_PART_IS_DEFINED(ATtiny9) \\r
+ )\r
+\r
+/** @} */\r
+\r
+/** tinyAVR product line */\r
+#define TINY (TINY_UNCATEGORIZED)\r
+\r
+/** @} */\r
+\r
+/**\r
+ * \defgroup sam_part_macros_group SAM parts\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \name SAM3S series\r
+ * @{\r
+ */\r
+#define SAM3S1 ( \\r
+ SAM_PART_IS_DEFINED(SAM3S1A) || \\r
+ SAM_PART_IS_DEFINED(SAM3S1B) || \\r
+ SAM_PART_IS_DEFINED(SAM3S1C) \\r
+ )\r
+\r
+#define SAM3S2 ( \\r
+ SAM_PART_IS_DEFINED(SAM3S2A) || \\r
+ SAM_PART_IS_DEFINED(SAM3S2B) || \\r
+ SAM_PART_IS_DEFINED(SAM3S2C) \\r
+ )\r
+\r
+#define SAM3S4 ( \\r
+ SAM_PART_IS_DEFINED(SAM3S4A) || \\r
+ SAM_PART_IS_DEFINED(SAM3S4B) || \\r
+ SAM_PART_IS_DEFINED(SAM3S4C) \\r
+ )\r
+\r
+#define SAM3S8 ( \\r
+ SAM_PART_IS_DEFINED(SAM3S8B) || \\r
+ SAM_PART_IS_DEFINED(SAM3S8C) \\r
+ )\r
+\r
+#define SAM3SD8 ( \\r
+ SAM_PART_IS_DEFINED(SAM3SD8B) || \\r
+ SAM_PART_IS_DEFINED(SAM3SD8C) \\r
+ )\r
+/** @} */\r
+\r
+/**\r
+ * \name SAM3U series\r
+ * @{\r
+ */\r
+#define SAM3U1 ( \\r
+ SAM_PART_IS_DEFINED(SAM3U1C) || \\r
+ SAM_PART_IS_DEFINED(SAM3U1E) \\r
+ )\r
+\r
+#define SAM3U2 ( \\r
+ SAM_PART_IS_DEFINED(SAM3U2C) || \\r
+ SAM_PART_IS_DEFINED(SAM3U2E) \\r
+ )\r
+\r
+#define SAM3U4 ( \\r
+ SAM_PART_IS_DEFINED(SAM3U4C) || \\r
+ SAM_PART_IS_DEFINED(SAM3U4E) \\r
+ )\r
+/** @} */\r
+\r
+/**\r
+ * \name SAM3N series\r
+ * @{\r
+ */\r
+#define SAM3N1 ( \\r
+ SAM_PART_IS_DEFINED(SAM3N1A) || \\r
+ SAM_PART_IS_DEFINED(SAM3N1B) || \\r
+ SAM_PART_IS_DEFINED(SAM3N1C) \\r
+ )\r
+\r
+#define SAM3N2 ( \\r
+ SAM_PART_IS_DEFINED(SAM3N2A) || \\r
+ SAM_PART_IS_DEFINED(SAM3N2B) || \\r
+ SAM_PART_IS_DEFINED(SAM3N2C) \\r
+ )\r
+\r
+#define SAM3N4 ( \\r
+ SAM_PART_IS_DEFINED(SAM3N4A) || \\r
+ SAM_PART_IS_DEFINED(SAM3N4B) || \\r
+ SAM_PART_IS_DEFINED(SAM3N4C) \\r
+ )\r
+/** @} */\r
+\r
+/**\r
+ * \name SAM3X series\r
+ * @{\r
+ */\r
+#define SAM3X4 ( \\r
+ SAM_PART_IS_DEFINED(SAM3X4C) || \\r
+ SAM_PART_IS_DEFINED(SAM3X4E) \\r
+ )\r
+\r
+#define SAM3X8 ( \\r
+ SAM_PART_IS_DEFINED(SAM3X8C) || \\r
+ SAM_PART_IS_DEFINED(SAM3X8E) || \\r
+ SAM_PART_IS_DEFINED(SAM3X8H) \\r
+ )\r
+/** @} */\r
+\r
+/**\r
+ * \name SAM3A series\r
+ * @{\r
+ */\r
+#define SAM3A4 ( \\r
+ SAM_PART_IS_DEFINED(SAM3A4C) \\r
+ )\r
+\r
+#define SAM3A8 ( \\r
+ SAM_PART_IS_DEFINED(SAM3A8C) \\r
+ )\r
+/** @} */\r
+\r
+/**\r
+ * \name SAM4S series\r
+ * @{\r
+ */\r
+#define SAM4S8 ( \\r
+ SAM_PART_IS_DEFINED(SAM4S8B) || \\r
+ SAM_PART_IS_DEFINED(SAM4S8C) \\r
+ )\r
+\r
+#define SAM4S16 ( \\r
+ SAM_PART_IS_DEFINED(SAM4S16B) || \\r
+ SAM_PART_IS_DEFINED(SAM4S16C) \\r
+ )\r
+\r
+#define SAM4SA16 ( \\r
+ SAM_PART_IS_DEFINED(SAM4SA16B) || \\r
+ SAM_PART_IS_DEFINED(SAM4SA16C) \\r
+ )\r
+\r
+#define SAM4SD16 ( \\r
+ SAM_PART_IS_DEFINED(SAM4SD16B) || \\r
+ SAM_PART_IS_DEFINED(SAM4SD16C) \\r
+ )\r
+\r
+#define SAM4SD32 ( \\r
+ SAM_PART_IS_DEFINED(SAM4SD32B) || \\r
+ SAM_PART_IS_DEFINED(SAM4SD32C) \\r
+ )\r
+/** @} */\r
+\r
+/**\r
+ * \name SAM4L series\r
+ * @{\r
+ */\r
+#define SAM4LS ( \\r
+ SAM_PART_IS_DEFINED(SAM4LS2A) || \\r
+ SAM_PART_IS_DEFINED(SAM4LS2B) || \\r
+ SAM_PART_IS_DEFINED(SAM4LS2C) || \\r
+ SAM_PART_IS_DEFINED(SAM4LS4A) || \\r
+ SAM_PART_IS_DEFINED(SAM4LS4B) || \\r
+ SAM_PART_IS_DEFINED(SAM4LS4C) || \\r
+ SAM_PART_IS_DEFINED(SAM4LS8A) || \\r
+ SAM_PART_IS_DEFINED(SAM4LS8B) || \\r
+ SAM_PART_IS_DEFINED(SAM4LS8C) \\r
+ )\r
+\r
+#define SAM4LC ( \\r
+ SAM_PART_IS_DEFINED(SAM4LC2A) || \\r
+ SAM_PART_IS_DEFINED(SAM4LC2B) || \\r
+ SAM_PART_IS_DEFINED(SAM4LC2C) || \\r
+ SAM_PART_IS_DEFINED(SAM4LC4A) || \\r
+ SAM_PART_IS_DEFINED(SAM4LC4B) || \\r
+ SAM_PART_IS_DEFINED(SAM4LC4C) || \\r
+ SAM_PART_IS_DEFINED(SAM4LC8A) || \\r
+ SAM_PART_IS_DEFINED(SAM4LC8B) || \\r
+ SAM_PART_IS_DEFINED(SAM4LC8C) \\r
+ )\r
+/** @} */\r
+\r
+/**\r
+ * \name SAMD20 series\r
+ * @{\r
+ */\r
+#define SAMD20J ( \\r
+ SAM_PART_IS_DEFINED(SAMD20J14) || \\r
+ SAM_PART_IS_DEFINED(SAMD20J15) || \\r
+ SAM_PART_IS_DEFINED(SAMD20J16) || \\r
+ SAM_PART_IS_DEFINED(SAMD20J17) || \\r
+ SAM_PART_IS_DEFINED(SAMD20J18) \\r
+ )\r
+\r
+#define SAMD20G ( \\r
+ SAM_PART_IS_DEFINED(SAMD20G14) || \\r
+ SAM_PART_IS_DEFINED(SAMD20G15) || \\r
+ SAM_PART_IS_DEFINED(SAMD20G16) || \\r
+ SAM_PART_IS_DEFINED(SAMD20G17) || \\r
+ SAM_PART_IS_DEFINED(SAMD20G18) \\r
+ )\r
+\r
+#define SAMD20E ( \\r
+ SAM_PART_IS_DEFINED(SAMD20E14) || \\r
+ SAM_PART_IS_DEFINED(SAMD20E15) || \\r
+ SAM_PART_IS_DEFINED(SAMD20E16) || \\r
+ SAM_PART_IS_DEFINED(SAMD20E17) || \\r
+ SAM_PART_IS_DEFINED(SAMD20E18) \\r
+ )\r
+/** @} */\r
+\r
+/**\r
+ * \name SAM4E series\r
+ * @{\r
+ */\r
+#define SAM4E8 ( \\r
+ SAM_PART_IS_DEFINED(SAM4E8E) \\r
+ )\r
+\r
+#define SAM4E16 ( \\r
+ SAM_PART_IS_DEFINED(SAM4E16E) \\r
+ )\r
+/** @} */\r
+\r
+/**\r
+ * \name SAM4N series\r
+ * @{\r
+ */\r
+#define SAM4N8 ( \\r
+ SAM_PART_IS_DEFINED(SAM4N8A) || \\r
+ SAM_PART_IS_DEFINED(SAM4N8B) || \\r
+ SAM_PART_IS_DEFINED(SAM4N8C) \\r
+ )\r
+\r
+#define SAM4N16 ( \\r
+ SAM_PART_IS_DEFINED(SAM4N16B) || \\r
+ SAM_PART_IS_DEFINED(SAM4N16C) \\r
+ )\r
+/** @} */\r
+\r
+/**\r
+ * \name SAM families\r
+ * @{\r
+ */\r
+/** SAM3S Family */\r
+#define SAM3S (SAM3S1 || SAM3S2 || SAM3S4 || SAM3S8 || SAM3SD8)\r
+\r
+/** SAM3U Family */\r
+#define SAM3U (SAM3U1 || SAM3U2 || SAM3U4)\r
+\r
+/** SAM3N Family */\r
+#define SAM3N (SAM3N1 || SAM3N2 || SAM3N4)\r
+\r
+/** SAM3XA Family */\r
+#define SAM3XA (SAM3X4 || SAM3X8 || SAM3A4 || SAM3A8)\r
+\r
+/** SAM4S Family */\r
+#define SAM4S (SAM4S8 || SAM4S16 || SAM4SA16 || SAM4SD16 || SAM4SD32)\r
+\r
+/** SAM4L Family */\r
+#define SAM4L (SAM4LS || SAM4LC)\r
+\r
+/** SAMD20 Family */\r
+#define SAMD20 (SAMD20J || SAMD20G || SAMD20E)\r
+/** @} */\r
+\r
+/** SAM4E Family */\r
+#define SAM4E (SAM4E8 || SAM4E16)\r
+\r
+/** SAM4N Family */\r
+#define SAM4N (SAM4N8 || SAM4N16)\r
+\r
+/** @} */\r
+\r
+/** SAM product line */\r
+#define SAM (SAM3S || SAM3U || SAM3N || SAM3XA || SAM4S || SAM4L || SAM4E || SAMD20 || SAM4N)\r
+\r
+/** @} */\r
+\r
+/** @} */\r
+\r
+/** @} */\r
+\r
+#endif /* ATMEL_PARTS_H */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief SAM4E-EK board init.\r
+ *\r
+ * Copyright (c) 2012 - 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#include "compiler.h"\r
+#include "board.h"\r
+#include "conf_board.h"\r
+#include "ioport.h"\r
+\r
+/**\r
+ * \brief Set peripheral mode for IOPORT pins.\r
+ * It will configure port mode and disable pin mode (but enable peripheral).\r
+ * \param port IOPORT port to configure\r
+ * \param masks IOPORT pin masks to configure\r
+ * \param mode Mode masks to configure for the specified pin (\ref ioport_modes)\r
+ */\r
+#define ioport_set_port_peripheral_mode(port, masks, mode) \\r
+ do {\\r
+ ioport_set_port_mode(port, masks, mode);\\r
+ ioport_disable_port(port, masks);\\r
+ } while (0)\r
+\r
+/**\r
+ * \brief Set peripheral mode for one single IOPORT pin.\r
+ * It will configure port mode and disable pin mode (but enable peripheral).\r
+ * \param pin IOPORT pin to configure\r
+ * \param mode Mode masks to configure for the specified pin (\ref ioport_modes)\r
+ */\r
+#define ioport_set_pin_peripheral_mode(pin, mode) \\r
+ do {\\r
+ ioport_set_pin_mode(pin, mode);\\r
+ ioport_disable_pin(pin);\\r
+ } while (0)\r
+\r
+/**\r
+ * \brief Set input mode for one single IOPORT pin.\r
+ * It will configure port mode and disable pin mode (but enable peripheral).\r
+ * \param pin IOPORT pin to configure\r
+ * \param mode Mode masks to configure for the specified pin (\ref ioport_modes)\r
+ * \param sense Sense for interrupt detection (\ref ioport_sense)\r
+ */\r
+#define ioport_set_pin_input_mode(pin, mode, sense) \\r
+ do {\\r
+ ioport_set_pin_dir(pin, IOPORT_DIR_INPUT);\\r
+ ioport_set_pin_mode(pin, mode);\\r
+ ioport_set_pin_sense_mode(pin, sense);\\r
+ } while (0)\r
+\r
+void board_init(void)\r
+{\r
+#ifndef CONF_BOARD_KEEP_WATCHDOG_AT_INIT\r
+ /* Disable the watchdog */\r
+ WDT->WDT_MR = WDT_MR_WDDIS;\r
+#endif\r
+\r
+ /* Initialize IOPORTs */\r
+ ioport_init();\r
+\r
+ /* Configure the pins connected to LEDs as output and set their\r
+ * default initial state to high (LEDs off).\r
+ */\r
+ ioport_set_pin_dir(LED0_GPIO, IOPORT_DIR_OUTPUT);\r
+ ioport_set_pin_level(LED0_GPIO, LED0_INACTIVE_LEVEL);\r
+ ioport_set_pin_dir(LED1_GPIO, IOPORT_DIR_OUTPUT);\r
+ ioport_set_pin_level(LED1_GPIO, LED0_INACTIVE_LEVEL);\r
+ ioport_set_pin_dir(LED2_GPIO, IOPORT_DIR_OUTPUT);\r
+ ioport_set_pin_level(LED2_GPIO, LED0_INACTIVE_LEVEL);\r
+\r
+ /* Configure Push Button pins */\r
+ ioport_set_pin_input_mode(GPIO_PUSH_BUTTON_1, GPIO_PUSH_BUTTON_1_FLAGS,\r
+ GPIO_PUSH_BUTTON_1_SENSE);\r
+ ioport_set_pin_input_mode(GPIO_PUSH_BUTTON_2, GPIO_PUSH_BUTTON_2_FLAGS,\r
+ GPIO_PUSH_BUTTON_2_SENSE);\r
+ ioport_set_pin_input_mode(GPIO_PUSH_BUTTON_3, GPIO_PUSH_BUTTON_3_FLAGS,\r
+ GPIO_PUSH_BUTTON_3_SENSE);\r
+ ioport_set_pin_input_mode(GPIO_PUSH_BUTTON_4, GPIO_PUSH_BUTTON_4_FLAGS,\r
+ GPIO_PUSH_BUTTON_4_SENSE);\r
+\r
+#ifdef CONF_BOARD_UART_CONSOLE\r
+ /* Configure UART pins */\r
+ ioport_set_port_peripheral_mode(PINS_UART0_PORT, PINS_UART0,\r
+ PINS_UART0_MASK);\r
+#endif\r
+\r
+#ifdef CONF_BOARD_PWM_LED0\r
+ /* Configure PWM LED0 pin */\r
+ ioport_set_pin_peripheral_mode(PIN_PWM_LED0_GPIO, PIN_PWM_LED0_FLAGS);\r
+#endif\r
+\r
+#ifdef CONF_BOARD_PWM_LED1\r
+ /* Configure PWM LED1 pin */\r
+ ioport_set_pin_peripheral_mode(PIN_PWM_LED1_GPIO, PIN_PWM_LED1_FLAGS);\r
+#endif\r
+\r
+#ifdef CONF_BOARD_PWM_LED2\r
+ /* Configure PWM LED2 pin */\r
+ ioport_set_pin_peripheral_mode(PIN_PWM_LED2_GPIO, PIN_PWM_LED2_FLAGS);\r
+#endif\r
+\r
+#ifdef CONF_BOARD_PWM_LED3\r
+ /* Configure PWM LED3 pin */\r
+ ioport_set_pin_peripheral_mode(PIN_PWM_LED3_GPIO, PIN_PWM_LED3_FLAGS);\r
+#endif\r
+\r
+#ifdef CONF_BOARD_USART_RXD\r
+ /* Configure USART RXD pin */\r
+ ioport_set_pin_peripheral_mode(PIN_USART1_RXD_IDX,\r
+ PIN_USART1_RXD_FLAGS);\r
+#endif\r
+\r
+#ifdef CONF_BOARD_USART_TXD\r
+ /* Configure USART TXD pin */\r
+ ioport_set_pin_peripheral_mode(PIN_USART1_TXD_IDX,\r
+ PIN_USART1_TXD_FLAGS);\r
+#endif\r
+\r
+#ifdef CONF_BOARD_USART_CTS\r
+ /* Configure USART CTS pin */\r
+ ioport_set_pin_peripheral_mode(PIN_USART1_CTS_IDX,\r
+ PIN_USART1_CTS_FLAGS);\r
+#endif\r
+\r
+#ifdef CONF_BOARD_USART_RTS\r
+ /* Configure USART RTS pin */\r
+ ioport_set_pin_peripheral_mode(PIN_USART1_RTS_IDX,\r
+ PIN_USART1_RTS_FLAGS);\r
+#endif\r
+\r
+#ifdef CONF_BOARD_USART_SCK\r
+ /* Configure USART synchronous communication SCK pin */\r
+ ioport_set_pin_peripheral_mode(PIN_USART1_SCK_IDX,\r
+ PIN_USART1_SCK_FLAGS);\r
+#endif\r
+\r
+#ifdef CONF_BOARD_ADM3312_EN\r
+ /* Configure ADM3312 enable pin */\r
+ ioport_set_pin_dir(PIN_USART1_EN_IDX, IOPORT_DIR_OUTPUT);\r
+#ifdef CONF_BOARD_ADM3312_EN_DISABLE_AT_INIT\r
+ ioport_set_pin_level(PIN_USART1_EN_IDX, PIN_USART1_EN_INACTIVE_LEVEL);\r
+#else\r
+ ioport_set_pin_level(PIN_USART1_EN_IDX, PIN_USART1_EN_ACTIVE_LEVEL);\r
+#endif\r
+#endif\r
+\r
+#ifdef CONF_BOARD_ADS7843\r
+ /* Configure Touchscreen SPI pins */\r
+ ioport_set_pin_dir(BOARD_ADS7843_IRQ_GPIO, IOPORT_DIR_INPUT);\r
+ ioport_set_pin_mode(BOARD_ADS7843_IRQ_GPIO, BOARD_ADS7843_IRQ_FLAGS);\r
+ ioport_set_pin_dir(BOARD_ADS7843_BUSY_GPIO, IOPORT_DIR_INPUT);\r
+ ioport_set_pin_mode(BOARD_ADS7843_BUSY_GPIO, BOARD_ADS7843_BUSY_FLAGS);\r
+ ioport_set_pin_peripheral_mode(SPI_MISO_GPIO, SPI_MISO_FLAGS);\r
+ ioport_set_pin_peripheral_mode(SPI_MOSI_GPIO, SPI_MOSI_FLAGS);\r
+ ioport_set_pin_peripheral_mode(SPI_SPCK_GPIO, SPI_SPCK_FLAGS);\r
+ ioport_set_pin_peripheral_mode(SPI_NPCS0_GPIO, SPI_NPCS0_FLAGS);\r
+#endif\r
+\r
+#ifdef CONF_BOARD_CAN0\r
+ /* Configure the CAN0 TX and RX pins. */\r
+ ioport_set_pin_peripheral_mode(PIN_CAN0_RX_IDX, PIN_CAN0_RX_FLAGS);\r
+ ioport_set_pin_peripheral_mode(PIN_CAN0_TX_IDX, PIN_CAN0_TX_FLAGS);\r
+ /* Configure the transiver0 RS & EN pins. */\r
+ ioport_set_pin_dir(PIN_CAN0_TR_RS_IDX, IOPORT_DIR_OUTPUT);\r
+ ioport_set_pin_dir(PIN_CAN0_TR_EN_IDX, IOPORT_DIR_OUTPUT);\r
+#endif\r
+\r
+#ifdef CONF_BOARD_CAN1\r
+ /* Configure the CAN1 TX and RX pin. */\r
+ ioport_set_pin_peripheral_mode(PIN_CAN1_RX_IDX, PIN_CAN1_RX_FLAGS);\r
+ ioport_set_pin_peripheral_mode(PIN_CAN1_TX_IDX, PIN_CAN1_TX_FLAGS);\r
+ /* Configure the transiver1 RS & EN pins. */\r
+ ioport_set_pin_dir(PIN_CAN1_TR_RS_IDX, IOPORT_DIR_OUTPUT);\r
+ ioport_set_pin_dir(PIN_CAN1_TR_EN_IDX, IOPORT_DIR_OUTPUT);\r
+#endif\r
+\r
+#if defined(CONF_BOARD_USB_PORT)\r
+# if defined(CONF_BOARD_USB_VBUS_DETECT)\r
+ gpio_configure_pin(USB_VBUS_PIN, USB_VBUS_FLAGS);\r
+# endif\r
+#endif\r
+\r
+#ifdef CONF_BOARD_ILI93XX\r
+ /* Configure LCD EBI pins */\r
+ ioport_set_pin_peripheral_mode(PIN_EBI_DATA_BUS_D0,PIN_EBI_DATA_BUS_FLAGS);\r
+ ioport_set_pin_peripheral_mode(PIN_EBI_DATA_BUS_D1,PIN_EBI_DATA_BUS_FLAGS);\r
+ ioport_set_pin_peripheral_mode(PIN_EBI_DATA_BUS_D2,PIN_EBI_DATA_BUS_FLAGS);\r
+ ioport_set_pin_peripheral_mode(PIN_EBI_DATA_BUS_D3,PIN_EBI_DATA_BUS_FLAGS);\r
+ ioport_set_pin_peripheral_mode(PIN_EBI_DATA_BUS_D4,PIN_EBI_DATA_BUS_FLAGS);\r
+ ioport_set_pin_peripheral_mode(PIN_EBI_DATA_BUS_D5,PIN_EBI_DATA_BUS_FLAGS);\r
+ ioport_set_pin_peripheral_mode(PIN_EBI_DATA_BUS_D6,PIN_EBI_DATA_BUS_FLAGS);\r
+ ioport_set_pin_peripheral_mode(PIN_EBI_DATA_BUS_D7,PIN_EBI_DATA_BUS_FLAGS);\r
+ \r
+ ioport_set_pin_peripheral_mode(PIN_EBI_NRD,PIN_EBI_NRD_FLAGS);\r
+ ioport_set_pin_peripheral_mode(PIN_EBI_NWE,PIN_EBI_NWE_FLAGS);\r
+ ioport_set_pin_peripheral_mode(PIN_EBI_NCS1,PIN_EBI_NCS1_FLAGS);\r
+ ioport_set_pin_peripheral_mode(PIN_EBI_LCD_RS,PIN_EBI_LCD_RS_FLAGS);\r
+#endif\r
+\r
+#ifdef CONF_BOARD_AAT3155\r
+ /* Configure Backlight control pin */\r
+ ioport_set_pin_dir(BOARD_AAT31XX_SET_GPIO, IOPORT_DIR_OUTPUT);\r
+#endif\r
+\r
+#ifdef CONF_BOARD_SPI\r
+ ioport_set_pin_peripheral_mode(SPI_MISO_GPIO, SPI_MISO_FLAGS);\r
+ ioport_set_pin_peripheral_mode(SPI_MOSI_GPIO, SPI_MOSI_FLAGS);\r
+ ioport_set_pin_peripheral_mode(SPI_SPCK_GPIO, SPI_SPCK_FLAGS);\r
+\r
+#ifdef CONF_BOARD_SPI_NPCS0\r
+ ioport_set_pin_peripheral_mode(SPI_NPCS0_GPIO, SPI_NPCS0_FLAGS);\r
+#endif\r
+\r
+#ifdef CONF_BOARD_SPI_NPCS3\r
+#if defined(CONF_BOARD_SPI_NPCS3_GPIO) && defined(CONF_BOARD_SPI_NPCS3_FLAGS)\r
+ ioport_set_pin_peripheral_mode(CONF_BOARD_SPI_NPCS3_GPIO,\r
+ CONF_BOARD_SPI_NPCS3_FLAGS);\r
+#else\r
+ ioport_set_pin_peripheral_mode(SPI_NPCS3_PA5_GPIO, SPI_NPCS3_PA5_FLAGS);\r
+#endif\r
+#endif\r
+#endif\r
+\r
+#if (defined(CONF_BOARD_TWI0) || defined(CONF_BOARD_QTOUCH))\r
+ ioport_set_pin_peripheral_mode(TWI0_DATA_GPIO, TWI0_DATA_FLAGS);\r
+ ioport_set_pin_peripheral_mode(TWI0_CLK_GPIO, TWI0_CLK_FLAGS);\r
+#endif\r
+\r
+#if defined (CONF_BOARD_SD_MMC_HSMCI)\r
+ /* Configure HSMCI pins */\r
+ ioport_set_pin_peripheral_mode(PIN_HSMCI_MCCDA_GPIO, PIN_HSMCI_MCCDA_FLAGS);\r
+ ioport_set_pin_peripheral_mode(PIN_HSMCI_MCCK_GPIO, PIN_HSMCI_MCCK_FLAGS);\r
+ ioport_set_pin_peripheral_mode(PIN_HSMCI_MCDA0_GPIO, PIN_HSMCI_MCDA0_FLAGS);\r
+ ioport_set_pin_peripheral_mode(PIN_HSMCI_MCDA1_GPIO, PIN_HSMCI_MCDA1_FLAGS);\r
+ ioport_set_pin_peripheral_mode(PIN_HSMCI_MCDA2_GPIO, PIN_HSMCI_MCDA2_FLAGS);\r
+ ioport_set_pin_peripheral_mode(PIN_HSMCI_MCDA3_GPIO, PIN_HSMCI_MCDA3_FLAGS);\r
+\r
+ /* Configure SD/MMC card detect pin */\r
+ ioport_set_pin_peripheral_mode(SD_MMC_0_CD_GPIO, SD_MMC_0_CD_FLAGS);\r
+#endif\r
+\r
+#ifdef CONF_BOARD_TWI1\r
+ ioport_set_pin_peripheral_mode(TWI1_DATA_GPIO, TWI1_DATA_FLAGS);\r
+ ioport_set_pin_peripheral_mode(TWI1_CLK_GPIO, TWI1_CLK_FLAGS);\r
+#endif\r
+\r
+#ifdef CONF_BOARD_KSZ8051MNL\r
+ ioport_set_pin_peripheral_mode(PIN_KSZ8051MNL_RXC_IDX,\r
+ PIN_KSZ8051MNL_RXC_FLAGS);\r
+ ioport_set_pin_peripheral_mode(PIN_KSZ8051MNL_TXC_IDX,\r
+ PIN_KSZ8051MNL_TXC_FLAGS);\r
+ ioport_set_pin_peripheral_mode(PIN_KSZ8051MNL_TXEN_IDX,\r
+ PIN_KSZ8051MNL_TXEN_FLAGS);\r
+ ioport_set_pin_peripheral_mode(PIN_KSZ8051MNL_TXD3_IDX,\r
+ PIN_KSZ8051MNL_TXD3_FLAGS);\r
+ ioport_set_pin_peripheral_mode(PIN_KSZ8051MNL_TXD2_IDX,\r
+ PIN_KSZ8051MNL_TXD2_FLAGS);\r
+ ioport_set_pin_peripheral_mode(PIN_KSZ8051MNL_TXD1_IDX,\r
+ PIN_KSZ8051MNL_TXD1_FLAGS);\r
+ ioport_set_pin_peripheral_mode(PIN_KSZ8051MNL_TXD0_IDX,\r
+ PIN_KSZ8051MNL_TXD0_FLAGS);\r
+ ioport_set_pin_peripheral_mode(PIN_KSZ8051MNL_RXD3_IDX,\r
+ PIN_KSZ8051MNL_RXD3_FLAGS);\r
+ ioport_set_pin_peripheral_mode(PIN_KSZ8051MNL_RXD2_IDX,\r
+ PIN_KSZ8051MNL_RXD2_FLAGS);\r
+ ioport_set_pin_peripheral_mode(PIN_KSZ8051MNL_RXD1_IDX,\r
+ PIN_KSZ8051MNL_RXD1_FLAGS);\r
+ ioport_set_pin_peripheral_mode(PIN_KSZ8051MNL_RXD0_IDX,\r
+ PIN_KSZ8051MNL_RXD0_FLAGS);\r
+ ioport_set_pin_peripheral_mode(PIN_KSZ8051MNL_RXER_IDX,\r
+ PIN_KSZ8051MNL_RXER_FLAGS);\r
+ ioport_set_pin_peripheral_mode(PIN_KSZ8051MNL_RXDV_IDX,\r
+ PIN_KSZ8051MNL_RXDV_FLAGS);\r
+ ioport_set_pin_peripheral_mode(PIN_KSZ8051MNL_CRS_IDX,\r
+ PIN_KSZ8051MNL_CRS_FLAGS);\r
+ ioport_set_pin_peripheral_mode(PIN_KSZ8051MNL_COL_IDX,\r
+ PIN_KSZ8051MNL_COL_FLAGS);\r
+ ioport_set_pin_peripheral_mode(PIN_KSZ8051MNL_MDC_IDX,\r
+ PIN_KSZ8051MNL_MDC_FLAGS);\r
+ ioport_set_pin_peripheral_mode(PIN_KSZ8051MNL_MDIO_IDX,\r
+ PIN_KSZ8051MNL_MDIO_FLAGS);\r
+ ioport_set_pin_dir(PIN_KSZ8051MNL_INTRP_IDX, IOPORT_DIR_INPUT);\r
+#endif\r
+\r
+#ifdef CONF_BOARD_TFDU4300_SD\r
+ /* Configure IrDA transceiver shutdown pin */\r
+ ioport_set_pin_dir(PIN_IRDA_SD_IDX, IOPORT_DIR_OUTPUT);\r
+ ioport_set_pin_level(PIN_IRDA_SD_IDX, IOPORT_PIN_LEVEL_HIGH);\r
+#endif\r
+\r
+#ifdef CONF_BOARD_ADM3485_RE\r
+ /* Configure RS485 transceiver RE pin */\r
+ ioport_set_pin_dir(PIN_RE_IDX, IOPORT_DIR_OUTPUT);\r
+ ioport_set_pin_level(PIN_RE_IDX, IOPORT_PIN_LEVEL_LOW);\r
+#endif\r
+\r
+#ifdef CONF_BOARD_ISO7816_RST\r
+ /* Configure ISO7816 card reset pin */\r
+ ioport_set_pin_dir(PIN_ISO7816_RST_IDX, IOPORT_DIR_OUTPUT);\r
+ ioport_set_pin_level(PIN_ISO7816_RST_IDX, IOPORT_PIN_LEVEL_LOW);\r
+#endif\r
+\r
+#ifdef CONF_BOARD_ISO7816\r
+ /* Configure ISO7816 interface TXD & SCK pin */\r
+ ioport_set_pin_peripheral_mode(PIN_USART1_TXD_IDX, PIN_USART1_TXD_FLAGS);\r
+ ioport_set_pin_peripheral_mode(PIN_USART1_SCK_IDX, PIN_USART1_SCK_FLAGS);\r
+#endif\r
+\r
+#ifdef CONF_BOARD_NAND\r
+ ioport_set_pin_peripheral_mode(PIN_EBI_NANDOE, PIN_EBI_NANDOE_FLAGS);\r
+ ioport_set_pin_peripheral_mode(PIN_EBI_NANDWE, PIN_EBI_NANDWE_FLAGS);\r
+ ioport_set_pin_peripheral_mode(PIN_EBI_NANDCLE, PIN_EBI_NANDCLE_FLAGS);\r
+ ioport_set_pin_peripheral_mode(PIN_EBI_NANDALE, PIN_EBI_NANDALE_FLAGS);\r
+ ioport_set_pin_peripheral_mode(PIN_EBI_NANDIO_0, PIN_EBI_NANDIO_0_FLAGS);\r
+ ioport_set_pin_peripheral_mode(PIN_EBI_NANDIO_1, PIN_EBI_NANDIO_1_FLAGS);\r
+ ioport_set_pin_peripheral_mode(PIN_EBI_NANDIO_2, PIN_EBI_NANDIO_2_FLAGS);\r
+ ioport_set_pin_peripheral_mode(PIN_EBI_NANDIO_3, PIN_EBI_NANDIO_3_FLAGS);\r
+ ioport_set_pin_peripheral_mode(PIN_EBI_NANDIO_4, PIN_EBI_NANDIO_4_FLAGS);\r
+ ioport_set_pin_peripheral_mode(PIN_EBI_NANDIO_5, PIN_EBI_NANDIO_5_FLAGS);\r
+ ioport_set_pin_peripheral_mode(PIN_EBI_NANDIO_6, PIN_EBI_NANDIO_6_FLAGS);\r
+ ioport_set_pin_peripheral_mode(PIN_EBI_NANDIO_7, PIN_EBI_NANDIO_7_FLAGS);\r
+ ioport_set_pin_dir(PIN_NF_CE_IDX, IOPORT_DIR_OUTPUT);\r
+ ioport_set_pin_dir(PIN_NF_RB_IDX, IOPORT_DIR_INPUT);\r
+ ioport_set_pin_mode(PIN_NF_RB_IDX, IOPORT_MODE_PULLUP);\r
+#endif\r
+\r
+\r
+#ifdef CONF_BOARD_QTOUCH\r
+ /* Configure CHANGE pin for QTouch device */\r
+ ioport_set_pin_input_mode(BOARD_QT_CHANGE_PIN_IDX, BOARD_QT_CHANGE_PIN_FLAGS,\r
+ BOARD_QT_CHANGE_PIN_SENSE);\r
+#endif\r
+}\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief SAM4E-EK LEDs support package.\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef LED_H_INCLUDED\r
+#define LED_H_INCLUDED\r
+\r
+#include "compiler.h"\r
+#include "ioport.h"\r
+\r
+/**\r
+ * \brief Turns off the specified LEDs.\r
+ *\r
+ * \param led LED to turn off (LEDx_GPIO).\r
+ *\r
+ * \note The pins of the specified LEDs are set to GPIO output mode.\r
+ */\r
+#define LED_Off(led) ioport_set_pin_level(led##_GPIO, led##_INACTIVE_LEVEL)\r
+\r
+/**\r
+ * \brief Turns on the specified LEDs.\r
+ *\r
+ * \param led LED to turn on (LEDx_GPIO).\r
+ *\r
+ * \note The pins of the specified LEDs are set to GPIO output mode.\r
+ */\r
+#define LED_On(led) ioport_set_pin_level(led##_GPIO, led##_ACTIVE_LEVEL)\r
+\r
+/**\r
+ * \brief Toggles the specified LEDs.\r
+ *\r
+ * \param led LED to toggle (LEDx_GPIO).\r
+ *\r
+ * \note The pins of the specified LEDs are set to GPIO output mode.\r
+ */\r
+#define LED_Toggle(led) ioport_toggle_pin_level(led##_GPIO)\r
+\r
+\r
+#endif // LED_H_INCLUDED\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief SAM4E-EK Board Definition.\r
+ *\r
+ * Copyright (c) 2012 - 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4E_EK_H_\r
+#define _SAM4E_EK_H_\r
+\r
+#include "compiler.h"\r
+#include "system_sam4e.h"\r
+#include "exceptions.h"\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/**\r
+ * \page sam4e_ek_opfreq "SAM4E-EK - Operating frequencies"\r
+ * This page lists several definition related to the board operating frequency\r
+ *\r
+ * \section Definitions\r
+ * - \ref BOARD_FREQ_*\r
+ * - \ref BOARD_MCK\r
+ */\r
+\r
+/** Board oscillator settings */\r
+#define BOARD_FREQ_SLCK_XTAL (32768U)\r
+#define BOARD_FREQ_SLCK_BYPASS (32768U)\r
+#define BOARD_FREQ_MAINCK_XTAL (12000000U)\r
+#define BOARD_FREQ_MAINCK_BYPASS (12000000U)\r
+\r
+/** Master clock frequency */\r
+#define BOARD_MCK CHIP_FREQ_CPU_MAX\r
+\r
+/** board main clock xtal statup time */\r
+#define BOARD_OSC_STARTUP_US 15625\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/**\r
+ * \page sam4e_ek_board_info "SAM4E-EK - Board informations"\r
+ * This page lists several definition related to the board description.\r
+ *\r
+ * \section Definitions\r
+ * - \ref BOARD_NAME\r
+ */\r
+\r
+/** Name of the board */\r
+#define BOARD_NAME "SAM4E-EK"\r
+/** Board definition */\r
+#define sam4eek\r
+/** Family definition (already defined) */\r
+#define sam4e\r
+/** Core definition */\r
+#define cortexm4\r
+\r
+/*----------------------------------------------------------------------------*/\r
+\r
+/** UART0 pins (UTXD0 and URXD0) definitions, PA10,9. */\r
+#define PINS_UART0 (PIO_PA9A_URXD0 | PIO_PA10A_UTXD0)\r
+#define PINS_UART0_FLAGS (IOPORT_MODE_MUX_A)\r
+\r
+#define PINS_UART0_PORT IOPORT_PIOA\r
+#define PINS_UART0_MASK (PIO_PA9A_URXD0 | PIO_PA10A_UTXD0)\r
+#define PINS_UART0_PIO PIOA\r
+#define PINS_UART0_ID ID_PIOA\r
+#define PINS_UART0_TYPE PIO_PERIPH_A\r
+#define PINS_UART0_ATTR PIO_DEFAULT\r
+\r
+/** UART1 pins (UTXD1 and URXD1) definitions, PA6,5. */\r
+#define PINS_UART1 (PIO_PA6C_URXD1 | PIO_PA5C_UTXD1)\r
+#define PINS_UART1_FLAGS (IOPORT_MODE_MUX_C)\r
+\r
+#define PINS_UART1_PORT IOPORT_PIOA\r
+#define PINS_UART1_MASK (PIO_PA6C_URXD1 | PIO_PA5C_UTXD1)\r
+#define PINS_UART1_PIO PIOA\r
+#define PINS_UART1_ID ID_PIOA\r
+#define PINS_UART1_TYPE PIO_PERIPH_C\r
+#define PINS_UART1_ATTR PIO_DEFAULT\r
+\r
+/** LED #0 pin definition (Blue). */\r
+#define LED_0_NAME "Blue LED D2"\r
+#define PIN_LED_0 {PIO_PA0, PIOA, ID_PIOA, PIO_OUTPUT_1, PIO_DEFAULT}\r
+#define PIN_LED_0_MASK PIO_PA0\r
+#define PIN_LED_0_PIO PIOA\r
+#define PIN_LED_0_ID ID_PIOA\r
+#define PIN_LED_0_TYPE PIO_OUTPUT_1\r
+#define PIN_LED_0_ATTR PIO_DEFAULT\r
+\r
+#define LED0_GPIO (PIO_PA0_IDX)\r
+#define LED0_FLAGS (0)\r
+#define LED0_ACTIVE_LEVEL IOPORT_PIN_LEVEL_LOW\r
+#define LED0_INACTIVE_LEVEL IOPORT_PIN_LEVEL_HIGH\r
+\r
+/** LED #1 pin definition (Amber). */\r
+#define LED_1_NAME "Amber LED D3"\r
+#define PIN_LED_1 {PIO_PD20, PIOD, ID_PIOD, PIO_OUTPUT_1, PIO_DEFAULT}\r
+#define PIN_LED_1_MASK PIO_PD20\r
+#define PIN_LED_1_PIO PIOD\r
+#define PIN_LED_1_ID ID_PIOD\r
+#define PIN_LED_1_TYPE PIO_OUTPUT_1\r
+#define PIN_LED_1_ATTR PIO_DEFAULT\r
+\r
+#define LED1_GPIO (PIO_PD20_IDX)\r
+#define LED1_FLAGS (0)\r
+#define LED1_ACTIVE_LEVEL IOPORT_PIN_LEVEL_LOW\r
+#define LED1_INACTIVE_LEVEL IOPORT_PIN_LEVEL_HIGH\r
+\r
+/** LED #2 pin definition (Green). */\r
+#define LED_2_NAME "Green LED D4"\r
+#define PIN_LED_2_MASK PIO_PD21\r
+#define PIN_LED_2_PIO PIOD\r
+#define PIN_LED_2_ID ID_PIOD\r
+#define PIN_LED_2_TYPE PIO_OUTPUT_1\r
+#define PIN_LED_2_ATTR PIO_DEFAULT\r
+\r
+#define LED2_GPIO (PIO_PD21_IDX)\r
+#define LED2_FLAGS (0)\r
+#define LED2_ACTIVE_LEVEL IOPORT_PIN_LEVEL_LOW\r
+#define LED2_INACTIVE_LEVEL IOPORT_PIN_LEVEL_HIGH\r
+\r
+/** LED #3 pin definition (Red). */\r
+#define LED_3_NAME "Red LED D5"\r
+#define PIN_LED_3_MASK PIO_PD22\r
+#define PIN_LED_3_PIO PIOD\r
+#define PIN_LED_3_ID ID_PIOD\r
+#define PIN_LED_3_TYPE PIO_OUTPUT_0\r
+#define PIN_LED_3_ATTR PIO_DEFAULT\r
+\r
+#define LED3_GPIO (PIO_PD22_IDX)\r
+#define LED3_FLAGS (0)\r
+#define LED3_ACTIVE_LEVEL IOPORT_PIN_LEVEL_HIGH\r
+#define LED3_INACTIVE_LEVEL IOPORT_PIN_LEVEL_LOW\r
+\r
+#define BOARD_NUM_OF_LED 4\r
+\r
+/** HSMCI pins definition. */\r
+/*! Number of slot connected on HSMCI interface */\r
+#define SD_MMC_HSMCI_MEM_CNT 1\r
+#define SD_MMC_HSMCI_SLOT_0_SIZE 4\r
+#define PINS_HSMCI {0x3fUL << 26, PIOA, ID_PIOA, PIO_PERIPH_C, PIO_PULLUP}\r
+/** HSMCI MCCDA pin definition. */\r
+#define PIN_HSMCI_MCCDA_GPIO (PIO_PA28_IDX)\r
+#define PIN_HSMCI_MCCDA_FLAGS (IOPORT_MODE_MUX_C)\r
+/** HSMCI MCCK pin definition. */\r
+#define PIN_HSMCI_MCCK_GPIO (PIO_PA29_IDX)\r
+#define PIN_HSMCI_MCCK_FLAGS (IOPORT_MODE_MUX_C)\r
+/** HSMCI MCDA0 pin definition. */\r
+#define PIN_HSMCI_MCDA0_GPIO (PIO_PA30_IDX)\r
+#define PIN_HSMCI_MCDA0_FLAGS (IOPORT_MODE_MUX_C)\r
+/** HSMCI MCDA1 pin definition. */\r
+#define PIN_HSMCI_MCDA1_GPIO (PIO_PA31_IDX)\r
+#define PIN_HSMCI_MCDA1_FLAGS (IOPORT_MODE_MUX_C)\r
+/** HSMCI MCDA2 pin definition. */\r
+#define PIN_HSMCI_MCDA2_GPIO (PIO_PA26_IDX)\r
+#define PIN_HSMCI_MCDA2_FLAGS (IOPORT_MODE_MUX_C)\r
+/** HSMCI MCDA3 pin definition. */\r
+#define PIN_HSMCI_MCDA3_GPIO (PIO_PA27_IDX)\r
+#define PIN_HSMCI_MCDA3_FLAGS (IOPORT_MODE_MUX_C)\r
+\r
+/** SD/MMC card detect pin definition. */\r
+#define PIN_HSMCI_CD {PIO_PA6, PIOA, ID_PIOA, PIO_INPUT, PIO_PULLUP}\r
+#define SD_MMC_0_CD_GPIO (PIO_PA6_IDX)\r
+#define SD_MMC_0_CD_PIO_ID ID_PIOA\r
+#define SD_MMC_0_CD_FLAGS (IOPORT_MODE_PULLUP)\r
+#define SD_MMC_0_CD_DETECT_VALUE 0\r
+\r
+/**\r
+ * Push button #0 definition. Attributes = pull-up + debounce + interrupt on\r
+ * rising edge.\r
+ */\r
+#define PUSHBUTTON_1_NAME "BP2 WAKU"\r
+#define PUSHBUTTON_1_WKUP_LINE (9)\r
+#define PUSHBUTTON_1_WKUP_FSTT (PMC_FSMR_FSTT9)\r
+#define GPIO_PUSH_BUTTON_1 (PIO_PA19_IDX)\r
+#define GPIO_PUSH_BUTTON_1_FLAGS (IOPORT_MODE_PULLUP | IOPORT_MODE_DEBOUNCE)\r
+#define GPIO_PUSH_BUTTON_1_SENSE (IOPORT_SENSE_RISING)\r
+\r
+#define PIN_PUSHBUTTON_1 {PIO_PA19, PIOA, ID_PIOA, PIO_INPUT, \\r
+ PIO_PULLUP | PIO_DEBOUNCE | PIO_IT_RISE_EDGE}\r
+#define PIN_PUSHBUTTON_1_MASK PIO_PA19\r
+#define PIN_PUSHBUTTON_1_PIO PIOA\r
+#define PIN_PUSHBUTTON_1_ID ID_PIOA\r
+#define PIN_PUSHBUTTON_1_TYPE PIO_INPUT\r
+#define PIN_PUSHBUTTON_1_ATTR (PIO_PULLUP | PIO_DEBOUNCE | PIO_IT_RISE_EDGE)\r
+#define PIN_PUSHBUTTON_1_IRQn PIOA_IRQn\r
+\r
+/**\r
+ * Push button #1 definition. Attributes = pull-up + debounce + interrupt on\r
+ * falling edge.\r
+ */\r
+#define PUSHBUTTON_2_NAME "BP3 TAMP"\r
+#define PUSHBUTTON_2_WKUP_LINE (10)\r
+#define PUSHBUTTON_2_WKUP_FSTT (PMC_FSMR_FSTT10)\r
+#define GPIO_PUSH_BUTTON_2 (PIO_PA20_IDX)\r
+#define GPIO_PUSH_BUTTON_2_FLAGS (IOPORT_MODE_PULLUP | IOPORT_MODE_DEBOUNCE)\r
+#define GPIO_PUSH_BUTTON_2_SENSE (IOPORT_SENSE_FALLING)\r
+\r
+#define PIN_PUSHBUTTON_2 {PIO_PA20, PIOA, ID_PIOA, PIO_INPUT, \\r
+ PIO_PULLUP | PIO_DEBOUNCE | PIO_IT_FALL_EDGE}\r
+#define PIN_PUSHBUTTON_2_MASK PIO_PA20\r
+#define PIN_PUSHBUTTON_2_PIO PIOA\r
+#define PIN_PUSHBUTTON_2_ID ID_PIOA\r
+#define PIN_PUSHBUTTON_2_TYPE PIO_INPUT\r
+#define PIN_PUSHBUTTON_2_ATTR (PIO_PULLUP | PIO_DEBOUNCE | PIO_IT_FALL_EDGE)\r
+#define PIN_PUSHBUTTON_2_IRQn PIOA_IRQn\r
+\r
+/**\r
+ * Push button #2 definition. Attributes = pull-up + debounce + interrupt on\r
+ * both edges.\r
+ */\r
+#define PUSHBUTTON_3_NAME "BP4 SCROLL-UP"\r
+#define PUSHBUTTON_3_WKUP_LINE (1)\r
+#define PUSHBUTTON_3_WKUP_FSTT (PMC_FSMR_FSTT1)\r
+#define GPIO_PUSH_BUTTON_3 (PIO_PA1_IDX)\r
+#define GPIO_PUSH_BUTTON_3_FLAGS (IOPORT_MODE_PULLUP | IOPORT_MODE_DEBOUNCE)\r
+#define GPIO_PUSH_BUTTON_3_SENSE (IOPORT_SENSE_BOTHEDGES)\r
+\r
+#define PIN_PUSHBUTTON_3 {PIO_PA1, PIOA, ID_PIOA, PIO_INPUT, \\r
+ PIO_PULLUP | PIO_DEBOUNCE | PIO_IT_RISE_EDGE}\r
+#define PIN_PUSHBUTTON_3_MASK PIO_PA1\r
+#define PIN_PUSHBUTTON_3_PIO PIOA\r
+#define PIN_PUSHBUTTON_3_ID ID_PIOA\r
+#define PIN_PUSHBUTTON_3_TYPE PIO_INPUT\r
+#define PIN_PUSHBUTTON_3_ATTR (PIO_PULLUP | PIO_DEBOUNCE | PIO_IT_RISE_EDGE)\r
+#define PIN_PUSHBUTTON_3_IRQn PIOA_IRQn\r
+\r
+/**\r
+ * Push button #3 definition. Attributes = pull-up + debounce + interrupt on\r
+ * rising edge.\r
+ */\r
+#define PUSHBUTTON_4_NAME "BP5 SCROLL-DOWN"\r
+#define PUSHBUTTON_4_WKUP_LINE (2)\r
+#define PUSHBUTTON_4_WKUP_FSTT (PMC_FSMR_FSTT2)\r
+#define GPIO_PUSH_BUTTON_4 (PIO_PA2_IDX)\r
+#define GPIO_PUSH_BUTTON_4_FLAGS (IOPORT_MODE_PULLUP | IOPORT_MODE_DEBOUNCE)\r
+#define GPIO_PUSH_BUTTON_4_SENSE (IOPORT_SENSE_RISING)\r
+\r
+#define PIN_PUSHBUTTON_4 {PIO_PA2, PIOA, ID_PIOA, PIO_INPUT, \\r
+ PIO_PULLUP | PIO_DEBOUNCE | PIO_IT_RISE_EDGE}\r
+#define PIN_PUSHBUTTON_4_MASK PIO_PA2\r
+#define PIN_PUSHBUTTON_4_PIO PIOA\r
+#define PIN_PUSHBUTTON_4_ID ID_PIOA\r
+#define PIN_PUSHBUTTON_4_TYPE PIO_INPUT\r
+#define PIN_PUSHBUTTON_4_ATTR (PIO_PULLUP | PIO_DEBOUNCE | PIO_IT_RISE_EDGE)\r
+#define PIN_PUSHBUTTON_4_IRQn PIOA_IRQn\r
+\r
+/** List of all push button definitions. */\r
+#define PINS_PUSHBUTTONS {PIN_PUSHBUTTON_1, PIN_PUSHBUTTON_2,\\r
+ PIN_PUSHBUTTON_3, PIN_PUSHBUTTON_4}\r
+\r
+#define PIN_TC0_TIOA0 (PIO_PA0_IDX)\r
+#define PIN_TC0_TIOA0_MUX (IOPORT_MODE_MUX_B)\r
+#define PIN_TC0_TIOA0_FLAGS (IOPORT_MODE_MUX_B)\r
+\r
+#define PIN_TC0_TIOA1 (PIO_PA15_IDX)\r
+#define PIN_TC0_TIOA1_MUX (IOPORT_MODE_MUX_B)\r
+#define PIN_TC0_TIOA1_FLAGS (IOPORT_MODE_MUX_B)\r
+\r
+#define PIN_TC0_TIOA1_PIO PIOA\r
+#define PIN_TC0_TIOA1_MASK PIO_PA15\r
+#define PIN_TC0_TIOA1_ID ID_PIOA\r
+#define PIN_TC0_TIOA1_TYPE PIO_PERIPH_B\r
+#define PIN_TC0_TIOA1_ATTR PIO_DEFAULT\r
+\r
+#define PIN_TC0_TIOA2 (PIO_PA26_IDX)\r
+#define PIN_TC0_TIOA2_MUX (IOPORT_MODE_MUX_B)\r
+#define PIN_TC0_TIOA2_FLAGS (IOPORT_MODE_MUX_B)\r
+\r
+#define PIN_TC0_TIOA2_PIO PIOA\r
+#define PIN_TC0_TIOA2_MASK PIO_PA26\r
+#define PIN_TC0_TIOA2_ID ID_PIOA\r
+#define PIN_TC0_TIOA2_TYPE PIO_PERIPH_B\r
+#define PIN_TC0_TIOA2_ATTR PIO_DEFAULT\r
+\r
+/** PWM LED0 pin definitions. */\r
+#define PIN_PWM_LED0_GPIO PIO_PD20_IDX\r
+#define PIN_PWM_LED0_FLAGS (IOPORT_MODE_MUX_A)\r
+#define PIN_PWM_LED0_CHANNEL PWM_CHANNEL_0\r
+\r
+/** PWM LED1 pin definitions. */\r
+#define PIN_PWM_LED1_GPIO PIO_PD21_IDX\r
+#define PIN_PWM_LED1_FLAGS (IOPORT_MODE_MUX_A)\r
+#define PIN_PWM_LED1_CHANNEL PWM_CHANNEL_1\r
+\r
+/** PWM LED2 pin definitions. */\r
+#define PIN_PWM_LED2_GPIO PIO_PD22_IDX\r
+#define PIN_PWM_LED2_FLAGS (IOPORT_MODE_MUX_A)\r
+#define PIN_PWM_LED2_CHANNEL PWM_CHANNEL_2\r
+\r
+/** PWM LED3 pin definitions. */\r
+#define PIN_PWM_LED3_GPIO PIO_PA0_IDX\r
+#define PIN_PWM_LED3_FLAGS (IOPORT_MODE_MUX_A)\r
+#define PIN_PWM_LED3_CHANNEL PWM_CHANNEL_0\r
+\r
+\r
+/** SPI MISO pin definition. */\r
+#define SPI_MISO_GPIO (PIO_PA12_IDX)\r
+#define SPI_MISO_FLAGS (IOPORT_MODE_MUX_A)\r
+/** SPI MOSI pin definition. */\r
+#define SPI_MOSI_GPIO (PIO_PA13_IDX)\r
+#define SPI_MOSI_FLAGS (IOPORT_MODE_MUX_A)\r
+/** SPI SPCK pin definition. */\r
+#define SPI_SPCK_GPIO (PIO_PA14_IDX)\r
+#define SPI_SPCK_FLAGS (IOPORT_MODE_MUX_A)\r
+\r
+/** SPI chip select 0 pin definition. (Only one configuration is possible) */\r
+#define SPI_NPCS0_GPIO (PIO_PA11_IDX)\r
+#define SPI_NPCS0_FLAGS (IOPORT_MODE_MUX_A)\r
+/** SPI chip select 1 pin definition. (multiple configurations are possible) */\r
+#define SPI_NPCS1_PA9_GPIO (PIO_PA9_IDX)\r
+#define SPI_NPCS1_PA9_FLAGS (IOPORT_MODE_MUX_B)\r
+#define SPI_NPCS1_PA31_GPIO (PIO_PA31_IDX)\r
+#define SPI_NPCS1_PA31_FLAGS (IOPORT_MODE_MUX_A)\r
+#define SPI_NPCS1_PB14_GPIO (PIO_PB14_IDX)\r
+#define SPI_NPCS1_PB14_FLAGS (IOPORT_MODE_MUX_A)\r
+#define SPI_NPCS1_PC4_GPIO (PIO_PC4_IDX)\r
+#define SPI_NPCS1_PC4_FLAGS (IOPORT_MODE_MUX_B)\r
+/** SPI chip select 2 pin definition. (multiple configurations are possible) */\r
+#define SPI_NPCS2_PA10_GPIO (PIO_PA10_IDX)\r
+#define SPI_NPCS2_PA10_FLAGS (IOPORT_MODE_MUX_B)\r
+#define SPI_NPCS2_PA30_GPIO (PIO_PA30_IDX)\r
+#define SPI_NPCS2_PA30_FLAGS (IOPORT_MODE_MUX_B)\r
+#define SPI_NPCS2_PB2_GPIO (PIO_PB2_IDX)\r
+#define SPI_NPCS2_PB2_FLAGS (IOPORT_MODE_MUX_B)\r
+/** SPI chip select 3 pin definition. (multiple configurations are possible) */\r
+#define SPI_NPCS3_PA3_GPIO (PIO_PA3_IDX)\r
+#define SPI_NPCS3_PA3_FLAGS (IOPORT_MODE_MUX_B)\r
+#define SPI_NPCS3_PA5_GPIO (PIO_PA5_IDX)\r
+#define SPI_NPCS3_PA5_FLAGS (IOPORT_MODE_MUX_B)\r
+#define SPI_NPCS3_PA22_GPIO (PIO_PA22_IDX)\r
+#define SPI_NPCS3_PA22_FLAGS (IOPORT_MODE_MUX_B)\r
+\r
+/* Select the SPI module that AT25DFx is connected to */\r
+#define AT25DFX_SPI_MODULE SPI\r
+\r
+/* Chip select used by AT25DFx components on the SPI module instance */\r
+#define AT25DFX_CS 3\r
+\r
+/* Touch screen IRQ & Busy pin definition */\r
+#define BOARD_ADS7843_IRQ_GPIO (PIO_PA16_IDX)\r
+#define BOARD_ADS7843_IRQ_FLAGS IOPORT_MODE_PULLUP\r
+#define BOARD_ADS7843_BUSY_GPIO (PIO_PA17_IDX)\r
+#define BOARD_ADS7843_BUSY_FLAGS IOPORT_MODE_PULLUP\r
+/**\r
+* SPI instance, which can be SPI, SPI0 or SPI1, depends on which SPI\r
+* channel is used.\r
+*/\r
+#define BOARD_ADS7843_SPI_BASE SPI\r
+/* SPI chip select NO., depends on which SPI CS pin is used by ADS7843. */\r
+#define BOARD_ADS7843_SPI_NPCS 0\r
+\r
+/** TWI0 pins definition */\r
+#define TWI0_DATA_GPIO PIO_PA3_IDX\r
+#define TWI0_DATA_FLAGS (IOPORT_MODE_MUX_A)\r
+#define TWI0_CLK_GPIO PIO_PA4_IDX\r
+#define TWI0_CLK_FLAGS (IOPORT_MODE_MUX_A)\r
+\r
+/** TWI1 pins definition */\r
+#define TWI1_DATA_GPIO PIO_PB4_IDX\r
+#define TWI1_DATA_FLAGS (IOPORT_MODE_MUX_A)\r
+#define TWI1_CLK_GPIO PIO_PB5_IDX\r
+#define TWI1_CLK_FLAGS (IOPORT_MODE_MUX_A)\r
+\r
+/** PCK0 pin definition (PA6) */\r
+#define PIN_PCK0 (PIO_PA6_IDX)\r
+#define PIN_PCK0_MUX (IOPORT_MODE_MUX_B)\r
+#define PIN_PCK0_FLAGS (IOPORT_MODE_MUX_B)\r
+#define PIN_PCK0_PORT IOPORT_PIOA\r
+#define PIN_PCK0_MASK PIO_PA6B_PCK0\r
+#define PIN_PCK0_PIO PIOA\r
+#define PIN_PCK0_ID ID_PIOA\r
+#define PIN_PCK0_TYPE PIO_PERIPH_B\r
+#define PIN_PCK0_ATTR PIO_DEFAULT\r
+\r
+/** USART0 pin RX */\r
+#define PIN_USART0_RXD {PIO_PB0C_RXD0, PIOB, ID_PIOB, PIO_PERIPH_C, \\r
+ PIO_DEFAULT}\r
+#define PIN_USART0_RXD_IDX (PIO_PB0_IDX)\r
+#define PIN_USART0_RXD_FLAGS (IOPORT_MODE_MUX_C)\r
+/** USART0 pin TX */\r
+#define PIN_USART0_TXD {PIO_PB1C_TXD0, PIOB, ID_PIOB, PIO_PERIPH_C, \\r
+ PIO_DEFAULT}\r
+#define PIN_USART0_TXD_IDX (PIO_PB1_IDX)\r
+#define PIN_USART0_TXD_FLAGS (IOPORT_MODE_MUX_C)\r
+/** USART0 pin CTS */\r
+#define PIN_USART0_CTS {PIO_PB2C_CTS0, PIOB, ID_PIOB, PIO_PERIPH_C, \\r
+ PIO_DEFAULT}\r
+#define PIN_USART0_CTS_IDX (PIO_PB2_IDX)\r
+#define PIN_USART0_CTS_FLAGS (IOPORT_MODE_MUX_C)\r
+/** USART0 pin RTS */\r
+#define PIN_USART0_RTS {PIO_PB3C_RTS0, PIOB, ID_PIOB, PIO_PERIPH_C, \\r
+ PIO_DEFAULT}\r
+#define PIN_USART0_RTS_IDX (PIO_PB3_IDX)\r
+#define PIN_USART0_RTS_FLAGS (IOPORT_MODE_MUX_C)\r
+/** USART0 pin SCK */\r
+#define PIN_USART0_SCK {PIO_PB13C_SCK0, PIOB, ID_PIOB, PIO_PERIPH_C, \\r
+ PIO_DEFAULT}\r
+#define PIN_USART0_SCK_IDX (PIO_PB13_IDX)\r
+#define PIN_USART0_SCK_FLAGS (IOPORT_MODE_MUX_C)\r
+\r
+/** USART1 pin RX */\r
+#define PIN_USART1_RXD {PIO_PA21A_RXD1, PIOA, ID_PIOA, PIO_PERIPH_A, \\r
+ PIO_DEFAULT}\r
+#define PIN_USART1_RXD_IDX (PIO_PA21_IDX)\r
+#define PIN_USART1_RXD_FLAGS (IOPORT_MODE_MUX_A)\r
+/** USART1 pin TX */\r
+#define PIN_USART1_TXD {PIO_PA22A_TXD1, PIOA, ID_PIOA, PIO_PERIPH_A, \\r
+ PIO_DEFAULT}\r
+#define PIN_USART1_TXD_IDX (PIO_PA22_IDX)\r
+#define PIN_USART1_TXD_FLAGS (IOPORT_MODE_MUX_A)\r
+/** USART1 pin CTS */\r
+#define PIN_USART1_CTS {PIO_PA25A_CTS1, PIOA, ID_PIOA, PIO_PERIPH_A, \\r
+ PIO_DEFAULT}\r
+#define PIN_USART1_CTS_IDX (PIO_PA25_IDX)\r
+#define PIN_USART1_CTS_FLAGS (IOPORT_MODE_MUX_A)\r
+/** USART1 pin RTS */\r
+#define PIN_USART1_RTS {PIO_PA24A_RTS1, PIOA, ID_PIOA, PIO_PERIPH_A, \\r
+ PIO_DEFAULT}\r
+#define PIN_USART1_RTS_IDX (PIO_PA24_IDX)\r
+#define PIN_USART1_RTS_FLAGS (IOPORT_MODE_MUX_A)\r
+/** USART1 pin SCK */\r
+#define PIN_USART1_SCK {PIO_PA23A_SCK1, PIOA, ID_PIOA, PIO_PERIPH_A, \\r
+ PIO_DEFAULT}\r
+#define PIN_USART1_SCK_IDX (PIO_PA23_IDX)\r
+#define PIN_USART1_SCK_FLAGS (IOPORT_MODE_MUX_A)\r
+/** USART1 pin ENABLE */\r
+#define PIN_USART1_EN {PIO_PA23, PIOA, ID_PIOA, PIO_OUTPUT_0, \\r
+ PIO_DEFAULT}\r
+#define PIN_USART1_EN_IDX (PIO_PA23_IDX)\r
+#define PIN_USART1_EN_FLAGS (0)\r
+#define PIN_USART1_EN_ACTIVE_LEVEL IOPORT_PIN_LEVEL_LOW\r
+#define PIN_USART1_EN_INACTIVE_LEVEL IOPORT_PIN_LEVEL_HIGH\r
+\r
+/** USB VBus monitoring pin definition. */\r
+#define PIN_USB_VBUS {PIO_PC21, PIOC, ID_PIOC, PIO_INPUT, PIO_PULLUP}\r
+#define USB_VBUS_FLAGS (PIO_INPUT | PIO_DEBOUNCE | PIO_IT_EDGE)\r
+#define USB_VBUS_PIN_IRQn (PIOC_IRQn)\r
+#define USB_VBUS_PIN (PIO_PC21_IDX)\r
+#define USB_VBUS_PIO_ID (ID_PIOC)\r
+#define USB_VBUS_PIO_MASK (PIO_PC21)\r
+/* This pin can not be used as fast wakeup source such as\r
+ * USB_VBUS_WKUP PMC_FSMR_FSTT7 */\r
+\r
+/** USB D- pin (System function) */\r
+#define PIN_USB_DM {PIO_PB10}\r
+/** USB D+ pin (System function) */\r
+#define PIN_USB_DP {PIO_PB11}\r
+\r
+/** EBI Data Bus pins */\r
+#define PIN_EBI_DATA_BUS_D0 PIO_PC0_IDX\r
+#define PIN_EBI_DATA_BUS_D1 PIO_PC1_IDX\r
+#define PIN_EBI_DATA_BUS_D2 PIO_PC2_IDX\r
+#define PIN_EBI_DATA_BUS_D3 PIO_PC3_IDX\r
+#define PIN_EBI_DATA_BUS_D4 PIO_PC4_IDX\r
+#define PIN_EBI_DATA_BUS_D5 PIO_PC5_IDX\r
+#define PIN_EBI_DATA_BUS_D6 PIO_PC6_IDX\r
+#define PIN_EBI_DATA_BUS_D7 PIO_PC7_IDX\r
+#define PIN_EBI_DATA_BUS_FLAGS (IOPORT_MODE_MUX_A | IOPORT_MODE_PULLUP)\r
+\r
+#define PIN_EBI_NRD PIO_PC11_IDX\r
+#define PIN_EBI_NRD_FLAGS (IOPORT_MODE_MUX_A | IOPORT_MODE_PULLUP)\r
+#define PIN_EBI_NWE PIO_PC8_IDX\r
+#define PIN_EBI_NWE_FLAGS (IOPORT_MODE_MUX_A | IOPORT_MODE_PULLUP)\r
+\r
+/** EBI pin for LCD CS and RS **/\r
+#define PIN_EBI_NCS1 PIO_PD18_IDX\r
+#define PIN_EBI_NCS1_FLAGS (IOPORT_MODE_MUX_A | IOPORT_MODE_PULLUP)\r
+#define PIN_EBI_LCD_RS PIO_PC19_IDX\r
+#define PIN_EBI_LCD_RS_FLAGS (IOPORT_MODE_MUX_A | IOPORT_MODE_PULLUP)\r
+\r
+/** Indicates board has an ILI9325 external component to manage LCD. */\r
+#define BOARD_LCD_ILI93XX\r
+\r
+/** Backlight pin definition. */\r
+#define BOARD_AAT31XX_SET_GPIO PIO_PC13_IDX\r
+/** Define ILI93xx base address. */\r
+#define BOARD_ILI93XX_ADDR 0x61000000\r
+/** Define ILI9325 register select signal. */\r
+#define BOARD_ILI93XX_RS (1 << 1)\r
+/** Display width in pixels. */\r
+#define BOARD_LCD_WIDTH 240\r
+/** Display height in pixels. */\r
+#define BOARD_LCD_HEIGHT 320\r
+\r
+/* KSZ8051MNL relate PIN definition */\r
+#define PIN_KSZ8051MNL_RXC_IDX PIO_PD14_IDX\r
+#define PIN_KSZ8051MNL_RXC_FLAGS (IOPORT_MODE_MUX_A)\r
+#define PIN_KSZ8051MNL_TXC_IDX PIO_PD0_IDX\r
+#define PIN_KSZ8051MNL_TXC_FLAGS (IOPORT_MODE_MUX_A)\r
+#define PIN_KSZ8051MNL_TXEN_IDX PIO_PD1_IDX\r
+#define PIN_KSZ8051MNL_TXEN_FLAGS (IOPORT_MODE_MUX_A)\r
+#define PIN_KSZ8051MNL_TXD3_IDX PIO_PD16_IDX\r
+#define PIN_KSZ8051MNL_TXD3_FLAGS (IOPORT_MODE_MUX_A)\r
+#define PIN_KSZ8051MNL_TXD2_IDX PIO_PD15_IDX\r
+#define PIN_KSZ8051MNL_TXD2_FLAGS (IOPORT_MODE_MUX_A)\r
+#define PIN_KSZ8051MNL_TXD1_IDX PIO_PD3_IDX\r
+#define PIN_KSZ8051MNL_TXD1_FLAGS (IOPORT_MODE_MUX_A)\r
+#define PIN_KSZ8051MNL_TXD0_IDX PIO_PD2_IDX\r
+#define PIN_KSZ8051MNL_TXD0_FLAGS (IOPORT_MODE_MUX_A)\r
+#define PIN_KSZ8051MNL_RXD3_IDX PIO_PD12_IDX\r
+#define PIN_KSZ8051MNL_RXD3_FLAGS (IOPORT_MODE_MUX_A)\r
+#define PIN_KSZ8051MNL_RXD2_IDX PIO_PD11_IDX\r
+#define PIN_KSZ8051MNL_RXD2_FLAGS (IOPORT_MODE_MUX_A)\r
+#define PIN_KSZ8051MNL_RXD1_IDX PIO_PD6_IDX\r
+#define PIN_KSZ8051MNL_RXD1_FLAGS (IOPORT_MODE_MUX_A)\r
+#define PIN_KSZ8051MNL_RXD0_IDX PIO_PD5_IDX\r
+#define PIN_KSZ8051MNL_RXD0_FLAGS (IOPORT_MODE_MUX_A)\r
+#define PIN_KSZ8051MNL_RXER_IDX PIO_PD7_IDX\r
+#define PIN_KSZ8051MNL_RXER_FLAGS (IOPORT_MODE_MUX_A)\r
+#define PIN_KSZ8051MNL_RXDV_IDX PIO_PD4_IDX\r
+#define PIN_KSZ8051MNL_RXDV_FLAGS (IOPORT_MODE_MUX_A)\r
+#define PIN_KSZ8051MNL_CRS_IDX PIO_PD10_IDX\r
+#define PIN_KSZ8051MNL_CRS_FLAGS (IOPORT_MODE_MUX_A)\r
+#define PIN_KSZ8051MNL_COL_IDX PIO_PD13_IDX\r
+#define PIN_KSZ8051MNL_COL_FLAGS (IOPORT_MODE_MUX_A)\r
+#define PIN_KSZ8051MNL_MDC_IDX PIO_PD8_IDX\r
+#define PIN_KSZ8051MNL_MDC_FLAGS (IOPORT_MODE_MUX_A)\r
+#define PIN_KSZ8051MNL_MDIO_IDX PIO_PD9_IDX\r
+#define PIN_KSZ8051MNL_MDIO_FLAGS (IOPORT_MODE_MUX_A)\r
+#define PIN_KSZ8051MNL_INTRP_IDX PIO_PD28_IDX\r
+\r
+/** NandFlash pins definition: OE. */\r
+#define PIN_EBI_NANDOE (PIO_PC9_IDX)\r
+#define PIN_EBI_NANDOE_FLAGS (IOPORT_MODE_MUX_A)\r
+\r
+/** NandFlash pins definition: WE. */\r
+#define PIN_EBI_NANDWE (PIO_PC10_IDX)\r
+#define PIN_EBI_NANDWE_FLAGS (IOPORT_MODE_MUX_A)\r
+\r
+/** NandFlash pins definition: CLE. */\r
+#define PIN_EBI_NANDCLE (PIO_PC17_IDX)\r
+#define PIN_EBI_NANDCLE_FLAGS (IOPORT_MODE_MUX_A)\r
+\r
+/** NandFlash pins definition: ALE. */\r
+#define PIN_EBI_NANDALE (PIO_PC16_IDX)\r
+#define PIN_EBI_NANDALE_FLAGS (IOPORT_MODE_MUX_A)\r
+\r
+/** NandFlash pins definition: DATA. */\r
+#define PIN_EBI_NANDIO_0 (PIO_PC0_IDX)\r
+#define PIN_EBI_NANDIO_0_FLAGS (IOPORT_MODE_MUX_A)\r
+\r
+#define PIN_EBI_NANDIO_1 (PIO_PC1_IDX)\r
+#define PIN_EBI_NANDIO_1_FLAGS (IOPORT_MODE_MUX_A)\r
+\r
+#define PIN_EBI_NANDIO_2 (PIO_PC2_IDX)\r
+#define PIN_EBI_NANDIO_2_FLAGS (IOPORT_MODE_MUX_A)\r
+\r
+#define PIN_EBI_NANDIO_3 (PIO_PC3_IDX)\r
+#define PIN_EBI_NANDIO_3_FLAGS (IOPORT_MODE_MUX_A)\r
+\r
+#define PIN_EBI_NANDIO_4 (PIO_PC4_IDX)\r
+#define PIN_EBI_NANDIO_4_FLAGS (IOPORT_MODE_MUX_A)\r
+\r
+#define PIN_EBI_NANDIO_5 (PIO_PC5_IDX)\r
+#define PIN_EBI_NANDIO_5_FLAGS (IOPORT_MODE_MUX_A)\r
+\r
+#define PIN_EBI_NANDIO_6 (PIO_PC6_IDX)\r
+#define PIN_EBI_NANDIO_6_FLAGS (IOPORT_MODE_MUX_A)\r
+\r
+#define PIN_EBI_NANDIO_7 (PIO_PC7_IDX)\r
+#define PIN_EBI_NANDIO_7_FLAGS (IOPORT_MODE_MUX_A)\r
+\r
+/** Nandflash chip enable pin definition. */\r
+#define PIN_NF_CE_IDX (PIO_PC14_IDX)\r
+\r
+/** Nandflash ready/busy pin definition. */\r
+#define PIN_NF_RB_IDX (PIO_PC18_IDX)\r
+\r
+/* Chip select number for nand */\r
+#define BOARD_NAND_CS 0\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/**\r
+ * \page sam4e_ek_usb "SAM4E-EK - USB device"\r
+ *\r
+ * \section Definitions\r
+ * - \ref BOARD_USB_BMATTRIBUTES\r
+ * - \ref CHIP_USB_UDP\r
+ * - \ref CHIP_USB_PULLUP_INTERNAL\r
+ * - \ref CHIP_USB_NUMENDPOINTS\r
+ * - \ref CHIP_USB_ENDPOINTS_MAXPACKETSIZE\r
+ * - \ref CHIP_USB_ENDPOINTS_BANKS\r
+ */\r
+\r
+/**\r
+ * USB attributes configuration descriptor (bus or self powered,\r
+ * remote wakeup)\r
+ */\r
+#define BOARD_USB_BMATTRIBUTES USBConfigurationDescriptor_SELFPOWERED_RWAKEUP\r
+\r
+/** Indicates chip has an UDP Full Speed. */\r
+#define CHIP_USB_UDP\r
+\r
+/** Indicates chip has an internal pull-up. */\r
+#define CHIP_USB_PULLUP_INTERNAL\r
+\r
+/** Number of USB endpoints */\r
+#define CHIP_USB_NUMENDPOINTS 8\r
+\r
+/** Endpoints max packet size */\r
+#define CHIP_USB_ENDPOINTS_MAXPACKETSIZE(i) \\r
+ ((i == 0) ? 64 : \\r
+ ((i == 1) ? 64 : \\r
+ ((i == 2) ? 64 : \\r
+ ((i == 3) ? 64 : \\r
+ ((i == 4) ? 512 : \\r
+ ((i == 5) ? 512 : \\r
+ ((i == 6) ? 64 : \\r
+ ((i == 7) ? 64 : 0 ))))))))\r
+\r
+/** Endpoints Number of Bank */\r
+#define CHIP_USB_ENDPOINTS_BANKS(i) \\r
+ ((i == 0) ? 1 : \\r
+ ((i == 1) ? 2 : \\r
+ ((i == 2) ? 2 : \\r
+ ((i == 3) ? 1 : \\r
+ ((i == 4) ? 2 : \\r
+ ((i == 5) ? 2 : \\r
+ ((i == 6) ? 2 : \\r
+ ((i == 7) ? 2 : 0 ))))))))\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/**\r
+ * \page sam4e_ek_extcomp "SAM4E-EK - External components"\r
+ * This page lists the definitions related to external on-board components\r
+ * located in the board.h file for the SAM4E-EK.\r
+ *\r
+ * SD Card\r
+ * - \ref BOARD_SD_PINS\r
+ * - \ref BOARD_SD_PIN_CD\r
+ *\r
+ * QTouch component (QT2160)\r
+ * - \ref BOARD_QT_TWI_INSTANCE\r
+ * - \ref BOARD_QT_DEVICE_ADDRESS\r
+ * - \ref BOARD_QT_CHANGE_PIN_IDX\r
+ * - \ref BOARD_QT_CHANGE_PIN_FLAGS\r
+ * - \ref BOARD_QT_CHANGE_PIN_SENSE\r
+ */\r
+\r
+/** HSMCI pins that shall be configured to access the SD card. */\r
+#define BOARD_SD_PINS PINS_HSMCI\r
+/** HSMCI Card Detect pin. */\r
+#define BOARD_SD_PIN_CD PIN_HSMCI_CD\r
+\r
+/** TWI instance for QTouch device */\r
+#define BOARD_QT_TWI_INSTANCE TWI0\r
+/* QTouch device address (I2CA1 = I2CA0 = 0) */\r
+#define BOARD_QT_DEVICE_ADDRESS 0x0D\r
+/** QTouch component pin definition */\r
+#define BOARD_QT_CHANGE_PIN_IDX (PIO_PE4_IDX)\r
+#define BOARD_QT_CHANGE_PIN_FLAGS (IOPORT_MODE_PULLUP | IOPORT_MODE_DEBOUNCE)\r
+#define BOARD_QT_CHANGE_PIN_SENSE (IOPORT_SENSE_FALLING)\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/**\r
+ * \page sam4e_ek_mem "SAM4E-EK - Memories"\r
+ * This page lists definitions related to internal & external on-board memories.\r
+ *\r
+ * \section NandFlash\r
+ * - \ref BOARD_NF_COMMAND_ADDR\r
+ * - \ref BOARD_NF_ADDRESS_ADDR\r
+ * - \ref BOARD_NF_DATA_ADDR\r
+ *\r
+ * \section NorFlash\r
+ * - \ref BOARD_NORFLASH_ADDR\r
+ * - \ref BOARD_NORFLASH_DFT_BUS_SIZE\r
+ */\r
+\r
+/** Address for transferring command bytes to the nandflash. */\r
+#define BOARD_NF_COMMAND_ADDR 0x60400000\r
+/** Address for transferring address bytes to the nandflash. */\r
+#define BOARD_NF_ADDRESS_ADDR 0x60200000\r
+/** Address for transferring data bytes to the nandflash. */\r
+#define BOARD_NF_DATA_ADDR 0x60000000\r
+/* Bus width for NAND */\r
+#define CONF_NF_BUSWIDTH 8\r
+/* Access timing for NAND */\r
+#define CONF_NF_SETUP_TIMING (SMC_SETUP_NWE_SETUP(0) \\r
+ | SMC_SETUP_NCS_WR_SETUP(1) \\r
+ | SMC_SETUP_NRD_SETUP(0) \\r
+ | SMC_SETUP_NCS_RD_SETUP(1))\r
+#define CONF_NF_PULSE_TIMING (SMC_PULSE_NWE_PULSE(2) \\r
+ | SMC_PULSE_NCS_WR_PULSE(3) \\r
+ | SMC_PULSE_NRD_PULSE(4) \\r
+ | SMC_PULSE_NCS_RD_PULSE(4))\r
+#define CONF_NF_CYCLE_TIMING (SMC_CYCLE_NWE_CYCLE(4) \\r
+ | SMC_CYCLE_NRD_CYCLE(7))\r
+\r
+/** Address for transferring command bytes to the norflash. */\r
+#define BOARD_NORFLASH_ADDR 0x63000000\r
+/** Default NOR bus size after power up reset */\r
+#define BOARD_NORFLASH_DFT_BUS_SIZE 8\r
+\r
+/*----------------------------------------------------------------------------*/\r
+\r
+#define CONSOLE_UART UART0\r
+#define CONSOLE_UART_ID ID_UART0\r
+\r
+/* RE pin. */\r
+#define PIN_RE_IDX PIN_USART1_CTS_IDX\r
+#define PIN_RE_FLAGS (0)\r
+\r
+/* IRDA SD pin. */\r
+#define PIN_IRDA_SD_IDX PIN_USART1_CTS_IDX\r
+#define PIN_IRDA_SD_FLAGS (0)\r
+\r
+/* TXD pin configuration. */\r
+#define PIN_USART_TXD_IDX PIN_USART1_TXD_IDX\r
+#define PIN_USART_TXD_FLAGS (IOPORT_MODE_MUX_A)\r
+#define PIN_USART_TXD_IO_FLAGS (0)\r
+\r
+/* ISO7816 example relate PIN definition. */\r
+#define ISO7816_USART_ID ID_USART1\r
+#define ISO7816_USART USART1\r
+#define PIN_ISO7816_RST_IDX PIO_PA15_IDX\r
+#define PIN_ISO7816_RST_FLAG (0)\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/* GMAC HW configurations */\r
+#define BOARD_GMAC_PHY_ADDR 0\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/**\r
+ * \page sam4e_ek_CAN "SAM4E-EK - CAN"\r
+ * This page lists definitions related to CAN0 and CAN1.\r
+ *\r
+ * CAN\r
+ * - \ref PIN_CAN0_TRANSCEIVER_RXEN\r
+ * - \ref PIN_CAN0_TRANSCEIVER_RS\r
+ * - \ref PIN_CAN0_TXD\r
+ * - \ref PIN_CAN0_RXD\r
+ * - \ref PINS_CAN0\r
+ *\r
+ * - \ref PIN_CAN1_TRANSCEIVER_RXEN\r
+ * - \ref PIN_CAN1_TRANSCEIVER_RS\r
+ * - \ref PIN_CAN1_TXD\r
+ * - \ref PIN_CAN1_RXD\r
+ * - \ref PINS_CAN1\r
+ */\r
+/** CAN0 transceiver PIN RS. */\r
+#define PIN_CAN0_TR_RS_IDX PIO_PE0_IDX\r
+#define PIN_CAN0_TR_RS_FLAGS IOPORT_DIR_OUTPUT\r
+\r
+/** CAN0 transceiver PIN EN. */\r
+#define PIN_CAN0_TR_EN_IDX PIO_PE1_IDX\r
+#define PIN_CAN0_TR_EN_FLAGS IOPORT_DIR_OUTPUT\r
+\r
+/** CAN0 PIN RX. */\r
+#define PIN_CAN0_RX_IDX PIO_PB3_IDX\r
+#define PIN_CAN0_RX_FLAGS IOPORT_MODE_MUX_A\r
+\r
+/** CAN0 PIN TX. */\r
+#define PIN_CAN0_TX_IDX PIO_PB2_IDX\r
+#define PIN_CAN0_TX_FLAGS IOPORT_MODE_MUX_A\r
+\r
+/** CAN1 transceiver PIN RS. */\r
+#define PIN_CAN1_TR_RS_IDX PIO_PE2_IDX\r
+#define PIN_CAN1_TR_RS_FLAGS IOPORT_DIR_OUTPUT\r
+\r
+/** CAN1 transceiver PIN EN. */\r
+#define PIN_CAN1_TR_EN_IDX PIO_PE3_IDX\r
+#define PIN_CAN1_TR_EN_FLAGS IOPORT_DIR_OUTPUT\r
+\r
+/** CAN1 PIN RX. */\r
+#define PIN_CAN1_RX_IDX PIO_PC12_IDX\r
+#define PIN_CAN1_RX_FLAGS IOPORT_MODE_MUX_C\r
+\r
+/** CAN1 PIN TX. */\r
+#define PIN_CAN1_TX_IDX PIO_PC15_IDX\r
+#define PIN_CAN1_TX_FLAGS IOPORT_MODE_MUX_C\r
+\r
+/** AFEC channel for potentiometer */\r
+#define AFEC_CHANNEL_POTENTIOMETER AFEC_CHANNEL_5\r
+\r
+/*----------------------------------------------------------------------------*/\r
+#endif /* _SAM4E_EK_H_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Ethernet Phy management\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+/**\r
+ *\r
+ * \defgroup ethernet_phy_group Ethernet Phy\r
+ *\r
+ * This is the common API for Ethernet Phy on ARMs. Additional features are available\r
+ * in the documentation of the specific modules.\r
+ *\r
+ * \section ethernet_phy_group_platform Platform Dependencies\r
+ *\r
+ * The ethernet_phy API is partially chip- or platform-specific. While all\r
+ * platforms provide mostly the same functionality, there are some\r
+ * variations around how different bus types and clock tree structures\r
+ * are handled.\r
+ *\r
+ * The following functions are available on all platforms, but there may\r
+ * be variations in the function signature (i.e. parameters) and\r
+ * behaviour. These functions are typically called by platform-specific\r
+ * parts of drivers, and applications that aren't intended to be\r
+ * portable:\r
+ * - ethernet_phy_init()\r
+ * - ethernet_phy_set_link()\r
+ * - ethernet_phy_auto_negotiate()\r
+ * - ethernet_phy_reset()\r
+ *\r
+ * @{\r
+ */\r
+\r
+//! @}\r
+\r
--- /dev/null
+ /**\r
+ * \file\r
+ *\r
+ * \brief API driver for KSZ8051MNL PHY component.\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#include "ethernet_phy.h"\r
+#include "gmac.h"\r
+#include "conf_eth.h"\r
+\r
+/// @cond 0\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+/**INDENT-ON**/\r
+/// @endcond\r
+\r
+/**\r
+ * \defgroup ksz8051mnl_ethernet_phy_group PHY component (KSZ8051MNL)\r
+ *\r
+ * Driver for the ksz8051mnl component. This driver provides access to the main\r
+ * features of the PHY.\r
+ *\r
+ * \section dependencies Dependencies\r
+ * This driver depends on the following modules:\r
+ * - \ref gmac_group Ethernet Media Access Controller (GMAC) module.\r
+ *\r
+ * @{\r
+ */\r
+\r
+/* Max PHY number */\r
+#define ETH_PHY_MAX_ADDR 31\r
+\r
+/* Ethernet PHY operation max retry count */\r
+#define ETH_PHY_RETRY_MAX 1000000\r
+\r
+/* Ethernet PHY operation timeout */\r
+#define ETH_PHY_TIMEOUT 10\r
+\r
+/**\r
+ * \brief Find a valid PHY Address ( from addrStart to 31 ).\r
+ *\r
+ * \param p_gmac Pointer to the GMAC instance.\r
+ * \param uc_phy_addr PHY address.\r
+ * \param uc_start_addr Start address of the PHY to be searched.\r
+ *\r
+ * \return 0xFF when no valid PHY address is found.\r
+ */\r
+static uint8_t ethernet_phy_find_valid(Gmac *p_gmac, uint8_t uc_phy_addr,\r
+ uint8_t uc_start_addr)\r
+{\r
+ uint32_t ul_value = 0;\r
+ uint8_t uc_rc = 0;\r
+ uint8_t uc_cnt;\r
+ uint8_t uc_phy_address = uc_phy_addr;\r
+\r
+ gmac_enable_management(p_gmac, true);\r
+\r
+ /* Check the current PHY address */\r
+ gmac_phy_read(p_gmac, uc_phy_addr, GMII_PHYID1, &ul_value);\r
+\r
+ /* Find another one */\r
+ if (ul_value != GMII_OUI_LSB) {\r
+ uc_rc = 0xFF;\r
+ for (uc_cnt = uc_start_addr; uc_cnt <= ETH_PHY_MAX_ADDR; uc_cnt++) {\r
+ uc_phy_address = (uc_phy_address + 1) & 0x1F;\r
+ gmac_phy_read(p_gmac, uc_phy_address, GMII_PHYID1, &ul_value);\r
+ if (ul_value == GMII_OUI_MSB) {\r
+ uc_rc = uc_phy_address;\r
+ break;\r
+ }\r
+ }\r
+ }\r
+\r
+ gmac_enable_management(p_gmac, false);\r
+\r
+ if (uc_rc != 0xFF) {\r
+ gmac_phy_read(p_gmac, uc_phy_address, GMII_BMSR, &ul_value);\r
+ }\r
+ return uc_rc;\r
+}\r
+\r
+\r
+/**\r
+ * \brief Perform a HW initialization to the PHY and set up clocks.\r
+ *\r
+ * This should be called only once to initialize the PHY pre-settings.\r
+ * The PHY address is the reset status of CRS, RXD[3:0] (the emacPins' pullups).\r
+ * The COL pin is used to select MII mode on reset (pulled up for Reduced MII).\r
+ * The RXDV pin is used to select test mode on reset (pulled up for test mode).\r
+ * The above pins should be predefined for corresponding settings in resetPins.\r
+ * The GMAC peripheral pins are configured after the reset is done.\r
+ *\r
+ * \param p_gmac Pointer to the GMAC instance.\r
+ * \param uc_phy_addr PHY address.\r
+ * \param ul_mck GMAC MCK.\r
+ *\r
+ * Return GMAC_OK if successfully, GMAC_TIMEOUT if timeout.\r
+ */\r
+uint8_t ethernet_phy_init(Gmac *p_gmac, uint8_t uc_phy_addr, uint32_t mck)\r
+{\r
+ uint8_t uc_rc = GMAC_TIMEOUT;\r
+ uint8_t uc_phy;\r
+\r
+ ethernet_phy_reset(GMAC,uc_phy_addr);\r
+\r
+ /* Configure GMAC runtime clock */\r
+ uc_rc = gmac_set_mdc_clock(p_gmac, mck);\r
+ if (uc_rc != GMAC_OK) {\r
+ return 0;\r
+ }\r
+\r
+ /* Check PHY Address */\r
+ uc_phy = ethernet_phy_find_valid(p_gmac, uc_phy_addr, 0);\r
+ if (uc_phy == 0xFF) {\r
+ return 0;\r
+ }\r
+ if (uc_phy != uc_phy_addr) {\r
+ ethernet_phy_reset(p_gmac, uc_phy_addr);\r
+ }\r
+\r
+ return uc_rc;\r
+}\r
+\r
+\r
+/**\r
+ * \brief Get the Link & speed settings, and automatically set up the GMAC with the\r
+ * settings.\r
+ *\r
+ * \param p_gmac Pointer to the GMAC instance.\r
+ * \param uc_phy_addr PHY address.\r
+ * \param uc_apply_setting_flag Set to 0 to not apply the PHY configurations, else to apply.\r
+ *\r
+ * Return GMAC_OK if successfully, GMAC_TIMEOUT if timeout.\r
+ */\r
+uint8_t ethernet_phy_set_link(Gmac *p_gmac, uint8_t uc_phy_addr,\r
+ uint8_t uc_apply_setting_flag)\r
+{\r
+ uint32_t ul_stat1;\r
+ uint32_t ul_stat2;\r
+ uint8_t uc_phy_address, uc_speed, uc_fd;\r
+ uint8_t uc_rc = GMAC_TIMEOUT;\r
+\r
+ gmac_enable_management(p_gmac, true);\r
+\r
+ uc_phy_address = uc_phy_addr;\r
+\r
+ uc_rc = gmac_phy_read(p_gmac, uc_phy_address, GMII_BMSR, &ul_stat1);\r
+ if (uc_rc != GMAC_OK) {\r
+ /* Disable PHY management and start the GMAC transfer */\r
+ gmac_enable_management(p_gmac, false);\r
+\r
+ return uc_rc;\r
+ }\r
+\r
+ if ((ul_stat1 & GMII_LINK_STATUS) == 0) {\r
+ /* Disable PHY management and start the GMAC transfer */\r
+ gmac_enable_management(p_gmac, false);\r
+\r
+ return GMAC_INVALID;\r
+ }\r
+\r
+ if (uc_apply_setting_flag == 0) {\r
+ /* Disable PHY management and start the GMAC transfer */\r
+ gmac_enable_management(p_gmac, false);\r
+\r
+ return uc_rc;\r
+ }\r
+\r
+ /* Read advertisement */\r
+ uc_rc = gmac_phy_read(p_gmac, uc_phy_address, GMII_ANAR, &ul_stat2);\r
+ if (uc_rc != GMAC_OK) {\r
+ /* Disable PHY management and start the GMAC transfer */\r
+ gmac_enable_management(p_gmac, false);\r
+\r
+ return uc_rc;\r
+ }\r
+\r
+ if ((ul_stat1 & GMII_100BASE_TX_FD) && (ul_stat2 & GMII_100TX_FDX)) {\r
+ /* Set GMAC for 100BaseTX and Full Duplex */\r
+ uc_speed = true;\r
+ uc_fd = true;\r
+ }\r
+\r
+ if ((ul_stat1 & GMII_10BASE_T_FD) && (ul_stat2 & GMII_10_FDX)) {\r
+ /* Set MII for 10BaseT and Full Duplex */\r
+ uc_speed = false;\r
+ uc_fd = true;\r
+ }\r
+\r
+ if ((ul_stat1 & GMII_100BASE_T4_HD) && (ul_stat2 & GMII_100TX_HDX)) {\r
+ /* Set MII for 100BaseTX and Half Duplex */\r
+ uc_speed = true;\r
+ uc_fd = false;\r
+ }\r
+\r
+ if ((ul_stat1 & GMII_10BASE_T_HD) && (ul_stat2 & GMII_10_HDX)) {\r
+ /* Set MII for 10BaseT and Half Duplex */\r
+ uc_speed = false;\r
+ uc_fd = false;\r
+ }\r
+\r
+ gmac_set_speed(p_gmac, uc_speed);\r
+ gmac_enable_full_duplex(p_gmac, uc_fd);\r
+\r
+ /* Start the GMAC transfers */\r
+ gmac_enable_management(p_gmac, false);\r
+ return uc_rc;\r
+}\r
+\r
+\r
+/**\r
+ * \brief Issue an auto negotiation of the PHY.\r
+ *\r
+ * \param p_gmac Pointer to the GMAC instance.\r
+ * \param uc_phy_addr PHY address.\r
+ *\r
+ * Return GMAC_OK if successfully, GMAC_TIMEOUT if timeout.\r
+ */\r
+uint8_t ethernet_phy_auto_negotiate(Gmac *p_gmac, uint8_t uc_phy_addr)\r
+{\r
+ uint32_t ul_retry_max = ETH_PHY_RETRY_MAX;\r
+ uint32_t ul_value;\r
+ uint32_t ul_phy_anar;\r
+ uint32_t ul_phy_analpar;\r
+ uint32_t ul_retry_count = 0;\r
+ uint8_t uc_speed = 0;\r
+ uint8_t uc_fd=0;\r
+ uint8_t uc_rc = GMAC_TIMEOUT;\r
+\r
+ gmac_enable_management(p_gmac, true);\r
+\r
+ /* Set up control register */\r
+ uc_rc = gmac_phy_read(p_gmac, uc_phy_addr, GMII_BMCR, &ul_value);\r
+ if (uc_rc != GMAC_OK) {\r
+ gmac_enable_management(p_gmac, false);\r
+ return uc_rc;\r
+ }\r
+\r
+ ul_value &= ~(uint32_t)GMII_AUTONEG; /* Remove auto-negotiation enable */\r
+ ul_value &= ~(uint32_t)(GMII_LOOPBACK | GMII_POWER_DOWN);\r
+ ul_value |= (uint32_t)GMII_ISOLATE; /* Electrically isolate PHY */\r
+ uc_rc = gmac_phy_write(p_gmac, uc_phy_addr, GMII_BMCR, ul_value);\r
+ if (uc_rc != GMAC_OK) {\r
+ gmac_enable_management(p_gmac, false);\r
+ return uc_rc;\r
+ }\r
+\r
+ /* \r
+ * Set the Auto_negotiation Advertisement Register.\r
+ * MII advertising for Next page.\r
+ * 100BaseTxFD and HD, 10BaseTFD and HD, IEEE 802.3.\r
+ */\r
+ ul_phy_anar = GMII_100TX_FDX | GMII_100TX_HDX | GMII_10_FDX | GMII_10_HDX | \r
+ GMII_AN_IEEE_802_3;\r
+ uc_rc = gmac_phy_write(p_gmac, uc_phy_addr, GMII_ANAR, ul_phy_anar);\r
+ if (uc_rc != GMAC_OK) {\r
+ gmac_enable_management(p_gmac, false);\r
+ return uc_rc;\r
+ }\r
+\r
+ /* Read & modify control register */\r
+ uc_rc = gmac_phy_read(p_gmac, uc_phy_addr, GMII_BMCR, &ul_value);\r
+ if (uc_rc != GMAC_OK) {\r
+ gmac_enable_management(p_gmac, false);\r
+ return uc_rc;\r
+ }\r
+\r
+ ul_value |= GMII_SPEED_SELECT | GMII_AUTONEG | GMII_DUPLEX_MODE;\r
+ uc_rc = gmac_phy_write(p_gmac, uc_phy_addr, GMII_BMCR, ul_value);\r
+ if (uc_rc != GMAC_OK) {\r
+ gmac_enable_management(p_gmac, false);\r
+ return uc_rc;\r
+ }\r
+\r
+ /* Restart auto negotiation */\r
+ ul_value |= (uint32_t)GMII_RESTART_AUTONEG;\r
+ ul_value &= ~(uint32_t)GMII_ISOLATE;\r
+ uc_rc = gmac_phy_write(p_gmac, uc_phy_addr, GMII_BMCR, ul_value);\r
+ if (uc_rc != GMAC_OK) {\r
+ gmac_enable_management(p_gmac, false);\r
+ return uc_rc;\r
+ }\r
+\r
+ /* Check if auto negotiation is completed */\r
+ while (1) {\r
+ uc_rc = gmac_phy_read(p_gmac, uc_phy_addr, GMII_BMSR, &ul_value);\r
+ if (uc_rc != GMAC_OK) {\r
+ gmac_enable_management(p_gmac, false);\r
+ return uc_rc;\r
+ }\r
+ /* Done successfully */\r
+ if (ul_value & GMII_AUTONEG_COMP) {\r
+ break;\r
+ }\r
+\r
+ /* Timeout check */\r
+ if (ul_retry_max) {\r
+ if (++ul_retry_count >= ul_retry_max) {\r
+ gmac_enable_management(p_gmac, false);\r
+ return GMAC_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+\r
+ /* Get the auto negotiate link partner base page */\r
+ uc_rc = gmac_phy_read(p_gmac, uc_phy_addr, GMII_PCR1, &ul_phy_analpar);\r
+ if (uc_rc != GMAC_OK) {\r
+ gmac_enable_management(p_gmac, false);\r
+ return uc_rc;\r
+ }\r
+\r
+\r
+ /* Set up the GMAC link speed */\r
+ if ((ul_phy_anar & ul_phy_analpar) & GMII_100TX_FDX) {\r
+ /* Set MII for 100BaseTX and Full Duplex */\r
+ uc_speed = true;\r
+ uc_fd = true;\r
+ } else if ((ul_phy_anar & ul_phy_analpar) & GMII_10_FDX) {\r
+ /* Set MII for 10BaseT and Full Duplex */\r
+ uc_speed = false;\r
+ uc_fd = true;\r
+ } else if ((ul_phy_anar & ul_phy_analpar) & GMII_100TX_HDX) {\r
+ /* Set MII for 100BaseTX and half Duplex */\r
+ uc_speed = true;\r
+ uc_fd = false;\r
+ } else if ((ul_phy_anar & ul_phy_analpar) & GMII_10_HDX) {\r
+ /* Set MII for 10BaseT and half Duplex */\r
+ uc_speed = false;\r
+ uc_fd = false;\r
+ }\r
+\r
+ gmac_set_speed(p_gmac, uc_speed);\r
+ gmac_enable_full_duplex(p_gmac, uc_fd);\r
+\r
+ /* Select Media Independent Interface type */\r
+ gmac_select_mii_mode(p_gmac, ETH_PHY_MODE);\r
+\r
+ gmac_enable_transmit(GMAC, true);\r
+ gmac_enable_receive(GMAC, true);\r
+\r
+ gmac_enable_management(p_gmac, false);\r
+ return uc_rc;\r
+}\r
+\r
+/**\r
+ * \brief Issue a SW reset to reset all registers of the PHY.\r
+ *\r
+ * \param p_gmac Pointer to the GMAC instance.\r
+ * \param uc_phy_addr PHY address.\r
+ *\r
+ * \Return GMAC_OK if successfully, GMAC_TIMEOUT if timeout.\r
+ */\r
+uint8_t ethernet_phy_reset(Gmac *p_gmac, uint8_t uc_phy_addr)\r
+{\r
+ uint32_t ul_bmcr = GMII_RESET;\r
+ uint8_t uc_phy_address = uc_phy_addr;\r
+ uint32_t ul_timeout = ETH_PHY_TIMEOUT;\r
+ uint8_t uc_rc = GMAC_TIMEOUT;\r
+\r
+ gmac_enable_management(p_gmac, true);\r
+\r
+ ul_bmcr = GMII_RESET;\r
+ gmac_phy_write(p_gmac, uc_phy_address, GMII_BMCR, ul_bmcr);\r
+\r
+ do {\r
+ gmac_phy_read(p_gmac, uc_phy_address, GMII_BMCR, &ul_bmcr);\r
+ ul_timeout--;\r
+ } while ((ul_bmcr & GMII_RESET) && ul_timeout);\r
+\r
+ gmac_enable_management(p_gmac, false);\r
+\r
+ if (!ul_timeout) {\r
+ uc_rc = GMAC_OK;\r
+ }\r
+\r
+ return (uc_rc);\r
+}\r
+\r
+/// @cond 0\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+/**INDENT-ON**/\r
+/// @endcond\r
+\r
+/**\r
+ * \}\r
+ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief KSZ8051MNL (Ethernet PHY) driver for SAM.\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef ETHERNET_PHY_H_INCLUDED\r
+#define ETHERNET_PHY_H_INCLUDED\r
+\r
+#include "compiler.h"\r
+\r
+// IEEE defined Registers\r
+#define GMII_BMCR 0x00 // Basic Control\r
+#define GMII_BMSR 0x01 // Basic Status\r
+#define GMII_PHYID1 0x02 // PHY Idendifier 1\r
+#define GMII_PHYID2 0x03 // PHY Idendifier 2\r
+#define GMII_ANAR 0x04 // Auto_Negotiation Advertisement\r
+#define GMII_ANLPAR 0x05 // Auto_negotiation Link Partner Ability\r
+#define GMII_ANER 0x06 // Auto-negotiation Expansion\r
+#define GMII_ANNPR 0x07 // Auto-negotiation Next Page\r
+#define GMII_ANLPNPAR 0x08 // Link Partner Next Page Ability\r
+//#define GMII_1000BTCR 9 // 1000Base-T Control // Reserved\r
+//#define GMII_1000BTSR 10 // 1000Base-T Status // Reserved\r
+#define GMII_AFECR1 0x11 // AFE Control 1\r
+//#define GMII_ERDWR 12 // Extend Register - Data Write Register\r
+//#define GMII_ERDRR 13 // Extend Register - Data Read Register\r
+//14 reserved\r
+#define GMII_RXERCR 0x15 // RXER Counter\r
+\r
+#define GMII_OMSOR 0x16 // Operation Mode Strap Override\r
+#define GMII_OMSSR 0x17 // Operation Mode Strap Status\r
+#define GMII_ECR 0x18 // Expanded Control\r
+//#define GMII_DPPSR 19 // Digital PMA/PCS Status\r
+//20 reserved\r
+//#define GMII_RXERCR 21 // RXER Counter Register\r
+//22-26 reserved\r
+#define GMII_ICSR 0x1B // Interrupt Control/Status\r
+//#define GMII_DDC1R 28 // Digital Debug Control 1 Register\r
+#define GMII_LCSR 0x1D // LinkMD Control/Status\r
+\r
+//29-30 reserved\r
+#define GMII_PCR1 0x1E // PHY Control 1\r
+#define GMII_PCR2 0x1F // PHY Control 2\r
+\r
+/*\r
+//Extend Registers\r
+#define GMII_CCR 256 // Common Control Register\r
+#define GMII_SSR 257 // Strap Status Register\r
+#define GMII_OMSOR 258 // Operation Mode Strap Override Register\r
+#define GMII_OMSSR 259 // Operation Mode Strap Status Register\r
+#define GMII_RCCPSR 260 // RGMII Clock and Control Pad Skew Register\r
+#define GMII_RRDPSR 261 // RGMII RX Data Pad Skew Register\r
+#define GMII_ATR 263 // Analog Test Register\r
+*/\r
+\r
+\r
+// Bit definitions: GMII_BMCR 0x00 Basic Control\r
+#define GMII_RESET (1 << 15) // 1= Software Reset; 0=Normal Operation\r
+#define GMII_LOOPBACK (1 << 14) // 1=loopback Enabled; 0=Normal Operation\r
+#define GMII_SPEED_SELECT (1 << 13) // 1=100Mbps; 0=10Mbps\r
+#define GMII_AUTONEG (1 << 12) // Auto-negotiation Enable\r
+#define GMII_POWER_DOWN (1 << 11) // 1=Power down 0=Normal operation\r
+#define GMII_ISOLATE (1 << 10) // 1 = Isolates 0 = Normal operation\r
+#define GMII_RESTART_AUTONEG (1 << 9) // 1 = Restart auto-negotiation 0 = Normal operation\r
+#define GMII_DUPLEX_MODE (1 << 8) // 1 = Full duplex operation 0 = Normal operation\r
+#define GMII_COLLISION_TEST (1 << 7) // 1 = Enable COL test; 0 = Disable COL test\r
+//#define GMII_SPEED_SELECT_MSB (1 << 6) // Reserved\r
+// Reserved 6 to 0 // Read as 0, ignore on write\r
+\r
+// Bit definitions: GMII_BMSR 0x01 Basic Status\r
+#define GMII_100BASE_T4 (1 << 15) // 100BASE-T4 Capable\r
+#define GMII_100BASE_TX_FD (1 << 14) // 100BASE-TX Full Duplex Capable\r
+#define GMII_100BASE_T4_HD (1 << 13) // 100BASE-TX Half Duplex Capable\r
+#define GMII_10BASE_T_FD (1 << 12) // 10BASE-T Full Duplex Capable\r
+#define GMII_10BASE_T_HD (1 << 11) // 10BASE-T Half Duplex Capable\r
+// Reserved 10 to79 // Read as 0, ignore on write\r
+//#define GMII_EXTEND_STATUS (1 << 8) // 1 = Extend Status Information In Reg 15\r
+// Reserved 7\r
+#define GMII_MF_PREAMB_SUPPR (1 << 6) // MII Frame Preamble Suppression\r
+#define GMII_AUTONEG_COMP (1 << 5) // Auto-negotiation Complete\r
+#define GMII_REMOTE_FAULT (1 << 4) // Remote Fault\r
+#define GMII_AUTONEG_ABILITY (1 << 3) // Auto Configuration Ability\r
+#define GMII_LINK_STATUS (1 << 2) // Link Status\r
+#define GMII_JABBER_DETECT (1 << 1) // Jabber Detect\r
+#define GMII_EXTEND_CAPAB (1 << 0) // Extended Capability\r
+\r
+\r
+// Bit definitions: GMII_PHYID1 0x02 PHY Idendifier 1\r
+// Bit definitions: GMII_PHYID2 0x03 PHY Idendifier 2\r
+#define GMII_LSB_MASK 0x3F\r
+#define GMII_OUI_MSB 0x0022\r
+#define GMII_OUI_LSB 0x05\r
+\r
+\r
+// Bit definitions: GMII_ANAR 0x04 Auto_Negotiation Advertisement\r
+// Bit definitions: GMII_ANLPAR 0x05 Auto_negotiation Link Partner Ability\r
+#define GMII_NP (1 << 15) // Next page Indication\r
+// Reserved 7\r
+#define GMII_RF (1 << 13) // Remote Fault\r
+// Reserved 12 // Write as 0, ignore on read\r
+#define GMII_PAUSE_MASK (3 << 11) // 0,0 = No Pause 1,0 = Asymmetric Pause(link partner)\r
+ // 0,1 = Symmetric Pause 1,1 = Symmetric&Asymmetric Pause(local device) \r
+#define GMII_100T4 (1 << 9) // 100BASE-T4 Support\r
+#define GMII_100TX_FDX (1 << 8) // 100BASE-TX Full Duplex Support\r
+#define GMII_100TX_HDX (1 << 7) // 100BASE-TX Support\r
+#define GMII_10_FDX (1 << 6) // 10BASE-T Full Duplex Support\r
+#define GMII_10_HDX (1 << 5) // 10BASE-T Support\r
+// Selector 4 to 0 // Protocol Selection Bits\r
+#define GMII_AN_IEEE_802_3 0x0001 // [00001] = IEEE 802.3\r
+\r
+\r
+// Bit definitions: GMII_ANER 0x06 Auto-negotiation Expansion\r
+// Reserved 15 to 5 // Read as 0, ignore on write\r
+#define GMII_PDF (1 << 4) // Local Device Parallel Detection Fault\r
+#define GMII_LP_NP_ABLE (1 << 3) // Link Partner Next Page Able\r
+#define GMII_NP_ABLE (1 << 2) // Local Device Next Page Able\r
+#define GMII_PAGE_RX (1 << 1) // New Page Received\r
+#define GMII_LP_AN_ABLE (1 << 0) // Link Partner Auto-negotiation Able\r
+\r
+/**\r
+ * \brief Perform a HW initialization to the PHY and set up clocks.\r
+ *\r
+ * This should be called only once to initialize the PHY pre-settings.\r
+ * The PHY address is the reset status of CRS, RXD[3:0] (the GmacPins' pullups).\r
+ * The COL pin is used to select MII mode on reset (pulled up for Reduced MII).\r
+ * The RXDV pin is used to select test mode on reset (pulled up for test mode).\r
+ * The above pins should be predefined for corresponding settings in resetPins.\r
+ * The GMAC peripheral pins are configured after the reset is done.\r
+ *\r
+ * \param p_gmac Pointer to the GMAC instance.\r
+ * \param uc_phy_addr PHY address.\r
+ * \param ul_mck GMAC MCK.\r
+ *\r
+ * Return GMAC_OK if successfully, GMAC_TIMEOUT if timeout.\r
+ */\r
+uint8_t ethernet_phy_init(Gmac *p_gmac, uint8_t uc_phy_addr, uint32_t ul_mck);\r
+\r
+\r
+/**\r
+ * \brief Get the Link & speed settings, and automatically set up the GMAC with the\r
+ * settings.\r
+ *\r
+ * \param p_gmac Pointer to the GMAC instance.\r
+ * \param uc_phy_addr PHY address.\r
+ * \param uc_apply_setting_flag Set to 0 to not apply the PHY configurations, else to apply.\r
+ *\r
+ * Return GMAC_OK if successfully, GMAC_TIMEOUT if timeout.\r
+ */\r
+uint8_t ethernet_phy_set_link(Gmac *p_gmac, uint8_t uc_phy_addr,\r
+ uint8_t uc_apply_setting_flag);\r
+\r
+\r
+/**\r
+ * \brief Issue an auto negotiation of the PHY.\r
+ *\r
+ * \param p_gmac Pointer to the GMAC instance.\r
+ * \param uc_phy_addr PHY address.\r
+ *\r
+ * Return GMAC_OK if successfully, GMAC_TIMEOUT if timeout.\r
+ */\r
+uint8_t ethernet_phy_auto_negotiate(Gmac *p_gmac, uint8_t uc_phy_addr);\r
+\r
+/**\r
+ * \brief Issue a SW reset to reset all registers of the PHY.\r
+ *\r
+ * \param p_gmac Pointer to the GMAC instance.\r
+ * \param uc_phy_addr PHY address.\r
+ *\r
+ * \Return GMAC_OK if successfully, GMAC_TIMEOUT if timeout.\r
+ */\r
+uint8_t ethernet_phy_reset(Gmac *p_gmac, uint8_t uc_phy_addr);\r
+\r
+#endif /* #ifndef ETHERNET_PHY_H_INCLUDED */\r
+\r
--- /dev/null
+ /**\r
+ * \file\r
+ *\r
+ * \brief GMAC (Ethernet MAC) driver for SAM.\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+ \r
+#include "compiler.h"\r
+#include "gmac.h"\r
+#include <string.h>\r
+#include "conf_eth.h"\r
+\r
+/// @cond 0\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+/**INDENT-ON**/\r
+/// @endcond\r
+\r
+/**\r
+ * \defgroup gmac_group Ethernet Media Access Controller\r
+ *\r
+ * See \ref gmac_quickstart.\r
+ *\r
+ * Driver for the GMAC (Ethernet Media Access Controller).\r
+ * This file contains basic functions for the GMAC, with support for all modes, settings\r
+ * and clock speeds.\r
+ *\r
+ * \section dependencies Dependencies\r
+ * This driver does not depend on other modules.\r
+ *\r
+ * @{\r
+ */\r
+\r
+/** TX descriptor lists */\r
+COMPILER_ALIGNED(8)\r
+static gmac_tx_descriptor_t gs_tx_desc[GMAC_TX_BUFFERS];\r
+/** TX callback lists */\r
+static gmac_dev_tx_cb_t gs_tx_callback[GMAC_TX_BUFFERS];\r
+/** RX descriptors lists */\r
+COMPILER_ALIGNED(8)\r
+static gmac_rx_descriptor_t gs_rx_desc[GMAC_RX_BUFFERS];\r
+/** Send Buffer. Section 3.6 of AMBA 2.0 spec states that burst should not cross the\r
+ * 1K Boundaries. Receive buffer manager write operations are burst of 2 words => 3 lsb bits\r
+ * of the address shall be set to 0.\r
+ */\r
+COMPILER_ALIGNED(8)\r
+static uint8_t gs_uc_tx_buffer[GMAC_TX_BUFFERS * GMAC_TX_UNITSIZE];\r
+\r
+/** Receive Buffer */\r
+COMPILER_ALIGNED(8)\r
+static uint8_t gs_uc_rx_buffer[GMAC_RX_BUFFERS * GMAC_RX_UNITSIZE];\r
+\r
+/**\r
+ * GMAC device memory management struct.\r
+ */\r
+typedef struct gmac_dev_mem {\r
+ /* Pointer to allocated buffer for RX. The address should be 8-byte aligned\r
+ and the size should be GMAC_RX_UNITSIZE * wRxSize. */\r
+ uint8_t *p_rx_buffer;\r
+ /* Pointer to allocated RX descriptor list. */\r
+ gmac_rx_descriptor_t *p_rx_dscr;\r
+ /* RX size, in number of registered units (RX descriptors). */\r
+ uint16_t us_rx_size;\r
+ /* Pointer to allocated buffer for TX. The address should be 8-byte aligned\r
+ and the size should be GMAC_TX_UNITSIZE * wTxSize. */\r
+ uint8_t *p_tx_buffer;\r
+ /* Pointer to allocated TX descriptor list. */\r
+ gmac_tx_descriptor_t *p_tx_dscr;\r
+ /* TX size, in number of registered units (TX descriptors). */\r
+ uint16_t us_tx_size;\r
+} gmac_dev_mem_t;\r
+\r
+/** Return count in buffer */\r
+#define CIRC_CNT(head,tail,size) (((head) - (tail)) % (size))\r
+\r
+/*\r
+ * Return space available, from 0 to size-1.\r
+ * Always leave one free char as a completely full buffer that has (head == tail), \r
+ * which is the same as empty.\r
+ */\r
+#define CIRC_SPACE(head,tail,size) CIRC_CNT((tail),((head)+1),(size))\r
+\r
+/** Circular buffer is empty ? */\r
+#define CIRC_EMPTY(head, tail) (head == tail)\r
+/** Clear circular buffer */\r
+#define CIRC_CLEAR(head, tail) (head = tail = 0)\r
+\r
+/** Increment head or tail */\r
+static void circ_inc(uint16_t *headortail, uint32_t size)\r
+{\r
+ (*headortail)++;\r
+ if((*headortail) >= size) {\r
+ (*headortail) = 0;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Wait PHY operation to be completed.\r
+ *\r
+ * \param p_gmac HW controller address.\r
+ * \param ul_retry The retry times, 0 to wait forever until completeness.\r
+ *\r
+ * Return GMAC_OK if the operation is completed successfully.\r
+ */\r
+static uint8_t gmac_wait_phy(Gmac* p_gmac, const uint32_t ul_retry)\r
+{\r
+ volatile uint32_t ul_retry_count = 0;\r
+\r
+ while (!gmac_is_phy_idle(p_gmac)) {\r
+ if (ul_retry == 0) {\r
+ continue;\r
+ }\r
+\r
+ ul_retry_count++;\r
+\r
+ if (ul_retry_count >= ul_retry) {\r
+ return GMAC_TIMEOUT;\r
+ }\r
+ }\r
+ return GMAC_OK;\r
+}\r
+\r
+/**\r
+ * \brief Disable transfer, reset registers and descriptor lists.\r
+ *\r
+ * \param p_dev Pointer to GMAC driver instance.\r
+ *\r
+ */\r
+static void gmac_reset_tx_mem(gmac_device_t* p_dev)\r
+{\r
+ Gmac *p_hw = p_dev->p_hw;\r
+ uint8_t *p_tx_buff = p_dev->p_tx_buffer;\r
+ gmac_tx_descriptor_t *p_td = p_dev->p_tx_dscr;\r
+\r
+ uint32_t ul_index;\r
+ uint32_t ul_address;\r
+\r
+ /* Disable TX */\r
+ gmac_enable_transmit(p_hw, 0);\r
+\r
+ /* Set up the TX descriptors */\r
+ CIRC_CLEAR(p_dev->us_tx_head, p_dev->us_tx_tail);\r
+ for (ul_index = 0; ul_index < p_dev->us_tx_list_size; ul_index++) {\r
+ ul_address = (uint32_t) (&(p_tx_buff[ul_index * GMAC_TX_UNITSIZE]));\r
+ p_td[ul_index].addr = ul_address;\r
+ p_td[ul_index].status.val = GMAC_TXD_USED;\r
+ }\r
+ p_td[p_dev->us_tx_list_size - 1].status.val =\r
+ GMAC_TXD_USED | GMAC_TXD_WRAP;\r
+\r
+ /* Set transmit buffer queue */\r
+ gmac_set_tx_queue(p_hw, (uint32_t) p_td);\r
+}\r
+\r
+/**\r
+ * \brief Disable receiver, reset registers and descriptor list.\r
+ *\r
+ * \param p_drv Pointer to GMAC Driver instance.\r
+ */\r
+static void gmac_reset_rx_mem(gmac_device_t* p_dev)\r
+{\r
+ Gmac *p_hw = p_dev->p_hw;\r
+ uint8_t *p_rx_buff = p_dev->p_rx_buffer;\r
+ gmac_rx_descriptor_t *pRd = p_dev->p_rx_dscr;\r
+\r
+ uint32_t ul_index;\r
+ uint32_t ul_address;\r
+\r
+ /* Disable RX */\r
+ gmac_enable_receive(p_hw, 0);\r
+\r
+ /* Set up the RX descriptors */\r
+ p_dev->us_rx_idx = 0;\r
+ for (ul_index = 0; ul_index < p_dev->us_rx_list_size; ul_index++) {\r
+ ul_address = (uint32_t) (&(p_rx_buff[ul_index * GMAC_RX_UNITSIZE]));\r
+ pRd[ul_index].addr.val = ul_address & GMAC_RXD_ADDR_MASK;\r
+ pRd[ul_index].status.val = 0;\r
+ }\r
+ pRd[p_dev->us_rx_list_size - 1].addr.val |= GMAC_RXD_WRAP;\r
+\r
+ /* Set receive buffer queue */\r
+ gmac_set_rx_queue(p_hw, (uint32_t) pRd);\r
+}\r
+\r
+\r
+/**\r
+ * \brief Initialize the allocated buffer lists for GMAC driver to transfer data.\r
+ * Must be invoked after gmac_dev_init() but before RX/TX starts.\r
+ *\r
+ * \note If input address is not 8-byte aligned, the address is automatically\r
+ * adjusted and the list size is reduced by one.\r
+ *\r
+ * \param p_gmac Pointer to GMAC instance. \r
+ * \param p_gmac_dev Pointer to GMAC device instance.\r
+ * \param p_dev_mm Pointer to the GMAC memory management control block.\r
+ * \param p_tx_cb Pointer to allocated TX callback list.\r
+ *\r
+ * \return GMAC_OK or GMAC_PARAM.\r
+ */\r
+static uint8_t gmac_init_mem(Gmac* p_gmac, gmac_device_t* p_gmac_dev,\r
+ gmac_dev_mem_t* p_dev_mm,\r
+ gmac_dev_tx_cb_t* p_tx_cb)\r
+{\r
+ if (p_dev_mm->us_rx_size <= 1 || p_dev_mm->us_tx_size <= 1 || p_tx_cb == NULL) {\r
+ return GMAC_PARAM;\r
+ }\r
+\r
+ /* Assign RX buffers */\r
+ if (((uint32_t) p_dev_mm->p_rx_buffer & 0x7)\r
+ || ((uint32_t) p_dev_mm->p_rx_dscr & 0x7)) {\r
+ p_dev_mm->us_rx_size--;\r
+ }\r
+ p_gmac_dev->p_rx_buffer =\r
+ (uint8_t *) ((uint32_t) p_dev_mm->p_rx_buffer & 0xFFFFFFF8);\r
+ p_gmac_dev->p_rx_dscr =\r
+ (gmac_rx_descriptor_t *) ((uint32_t) p_dev_mm->p_rx_dscr \r
+ & 0xFFFFFFF8);\r
+ p_gmac_dev->us_rx_list_size = p_dev_mm->us_rx_size;\r
+\r
+ /* Assign TX buffers */\r
+ if (((uint32_t) p_dev_mm->p_tx_buffer & 0x7)\r
+ || ((uint32_t) p_dev_mm->p_tx_dscr & 0x7)) {\r
+ p_dev_mm->us_tx_size--;\r
+ }\r
+ p_gmac_dev->p_tx_buffer =\r
+ (uint8_t *) ((uint32_t) p_dev_mm->p_tx_buffer & 0xFFFFFFF8);\r
+ p_gmac_dev->p_tx_dscr =\r
+ (gmac_tx_descriptor_t *) ((uint32_t) p_dev_mm->p_tx_dscr \r
+ & 0xFFFFFFF8);\r
+ p_gmac_dev->us_tx_list_size = p_dev_mm->us_tx_size;\r
+ p_gmac_dev->func_tx_cb_list = p_tx_cb;\r
+\r
+ /* Reset TX & RX */\r
+ gmac_reset_rx_mem(p_gmac_dev);\r
+ gmac_reset_tx_mem(p_gmac_dev);\r
+\r
+ /* Enable Rx and Tx, plus the statistics register */\r
+ gmac_enable_transmit(p_gmac, true);\r
+ gmac_enable_receive(p_gmac, true);\r
+ gmac_enable_statistics_write(p_gmac, true);\r
+\r
+ /* Set up the interrupts for transmission and errors */\r
+ gmac_enable_interrupt(p_gmac, \r
+ GMAC_IER_RXUBR | /* Enable receive used bit read interrupt. */\r
+ GMAC_IER_TUR | /* Enable transmit underrun interrupt. */\r
+ GMAC_IER_RLEX | /* Enable retry limit exceeded interrupt. */\r
+ GMAC_IER_TFC | /* Enable transmit buffers exhausted in mid-frame interrupt. */\r
+ GMAC_IER_TCOMP | /* Enable transmit complete interrupt. */\r
+ GMAC_IER_ROVR | /* Enable receive overrun interrupt. */\r
+ GMAC_IER_HRESP | /* Enable Hresp not OK interrupt. */\r
+ GMAC_IER_PFNZ | /* Enable pause frame received interrupt. */\r
+ GMAC_IER_PTZ); /* Enable pause time zero interrupt. */\r
+\r
+ return GMAC_OK;\r
+}\r
+\r
+/**\r
+ * \brief Read the PHY register.\r
+ *\r
+ * \param p_gmac Pointer to the GMAC instance. \r
+ * \param uc_phy_address PHY address.\r
+ * \param uc_address Register address.\r
+ * \param p_value Pointer to a 32-bit location to store read data.\r
+ *\r
+ * \Return GMAC_OK if successfully, GMAC_TIMEOUT if timeout.\r
+ */\r
+uint8_t gmac_phy_read(Gmac* p_gmac, uint8_t uc_phy_address, uint8_t uc_address,\r
+ uint32_t* p_value)\r
+{\r
+ gmac_maintain_phy(p_gmac, uc_phy_address, uc_address, 1, 0);\r
+\r
+ if (gmac_wait_phy(p_gmac, MAC_PHY_RETRY_MAX) == GMAC_TIMEOUT) {\r
+ return GMAC_TIMEOUT;\r
+ }\r
+ *p_value = gmac_get_phy_data(p_gmac);\r
+ return GMAC_OK;\r
+}\r
+\r
+/**\r
+ * \brief Write the PHY register.\r
+ *\r
+ * \param p_gmac Pointer to the GMAC instance. \r
+ * \param uc_phy_address PHY Address.\r
+ * \param uc_address Register Address.\r
+ * \param ul_value Data to write, actually 16-bit data.\r
+ *\r
+ * \Return GMAC_OK if successfully, GMAC_TIMEOUT if timeout.\r
+ */\r
+uint8_t gmac_phy_write(Gmac* p_gmac, uint8_t uc_phy_address,\r
+ uint8_t uc_address, uint32_t ul_value)\r
+{\r
+ gmac_maintain_phy(p_gmac, uc_phy_address, uc_address, 0, ul_value);\r
+\r
+ if (gmac_wait_phy(p_gmac, MAC_PHY_RETRY_MAX) == GMAC_TIMEOUT) {\r
+ return GMAC_TIMEOUT;\r
+ }\r
+ return GMAC_OK;\r
+}\r
+\r
+/**\r
+ * \brief Initialize the GMAC driver.\r
+ *\r
+ * \param p_gmac Pointer to the GMAC instance. \r
+ * \param p_gmac_dev Pointer to the GMAC device instance. \r
+ * \param p_opt GMAC configure options.\r
+ */\r
+void gmac_dev_init(Gmac* p_gmac, gmac_device_t* p_gmac_dev,\r
+ gmac_options_t* p_opt)\r
+{\r
+ gmac_dev_mem_t gmac_dev_mm;\r
+\r
+ /* Disable TX & RX and more */\r
+ gmac_network_control(p_gmac, 0);\r
+ gmac_disable_interrupt(p_gmac, ~0u);\r
+\r
+\r
+ gmac_clear_statistics(p_gmac);\r
+\r
+ /* Clear all status bits in the receive status register. */\r
+ gmac_clear_rx_status(p_gmac, GMAC_RSR_RXOVR | GMAC_RSR_REC | GMAC_RSR_BNA);\r
+\r
+ /* Clear all status bits in the transmit status register */\r
+ gmac_clear_tx_status(p_gmac, GMAC_TSR_UBR | GMAC_TSR_COL | GMAC_TSR_RLE\r
+ | GMAC_TSR_TFC | GMAC_TSR_TXCOMP | GMAC_TSR_UND);\r
+\r
+ /* Clear interrupts */\r
+ gmac_get_interrupt_status(p_gmac);\r
+\r
+ /* Enable the copy of data into the buffers\r
+ ignore broadcasts, and not copy FCS. */\r
+ gmac_set_configure(p_gmac,\r
+ gmac_get_configure(p_gmac) | GMAC_NCFGR_IRXFCS| GMAC_NCFGR_PEN);\r
+\r
+ gmac_enable_copy_all(p_gmac, p_opt->uc_copy_all_frame);\r
+ gmac_disable_broadcast(p_gmac, p_opt->uc_no_boardcast);\r
+\r
+ /* Fill in GMAC device memory management */\r
+ gmac_dev_mm.p_rx_buffer = gs_uc_rx_buffer;\r
+ gmac_dev_mm.p_rx_dscr = gs_rx_desc;\r
+ gmac_dev_mm.us_rx_size = GMAC_RX_BUFFERS;\r
+\r
+ gmac_dev_mm.p_tx_buffer = gs_uc_tx_buffer;\r
+ gmac_dev_mm.p_tx_dscr = gs_tx_desc;\r
+ gmac_dev_mm.us_tx_size = GMAC_TX_BUFFERS;\r
+\r
+ gmac_init_mem(p_gmac, p_gmac_dev, &gmac_dev_mm, gs_tx_callback);\r
+\r
+ gmac_set_address(p_gmac, 0, p_opt->uc_mac_addr);\r
+\r
+}\r
+\r
+/**\r
+ * \brief Frames can be read from the GMAC in multiple sections.\r
+ * Read ul_frame_size bytes from the GMAC receive buffers to pcTo.\r
+ * p_rcv_size is the size of the entire frame. Generally gmac_read\r
+ * will be repeatedly called until the sum of all the ul_frame_size equals\r
+ * the value of p_rcv_size.\r
+ *\r
+ * \param p_gmac_dev Pointer to the GMAC device instance. \r
+ * \param p_frame Address of the frame buffer.\r
+ * \param ul_frame_size Length of the frame.\r
+ * \param p_rcv_size Received frame size.\r
+ *\r
+ * \return GMAC_OK if receiving frame successfully, otherwise failed.\r
+ */\r
+uint32_t gmac_dev_read(gmac_device_t* p_gmac_dev, uint8_t* p_frame,\r
+ uint32_t ul_frame_size, uint32_t* p_rcv_size)\r
+{\r
+ uint16_t us_buffer_length;\r
+ uint32_t tmp_ul_frame_size = 0;\r
+ uint8_t *p_tmp_frame = 0;\r
+ uint16_t us_tmp_idx = p_gmac_dev->us_rx_idx;\r
+ gmac_rx_descriptor_t *p_rx_td =\r
+ &p_gmac_dev->p_rx_dscr[p_gmac_dev->us_rx_idx];\r
+ int8_t c_is_frame = 0;\r
+\r
+ if (p_frame == NULL)\r
+ return GMAC_PARAM;\r
+\r
+ /* Set the default return value */\r
+ *p_rcv_size = 0;\r
+\r
+ /* Process received RX descriptor */\r
+ while ((p_rx_td->addr.val & GMAC_RXD_OWNERSHIP) == GMAC_RXD_OWNERSHIP) {\r
+ /* A start of frame has been received, discard previous fragments */\r
+ if ((p_rx_td->status.val & GMAC_RXD_SOF) == GMAC_RXD_SOF) {\r
+ /* Skip previous fragment */\r
+ while (us_tmp_idx != p_gmac_dev->us_rx_idx) {\r
+ p_rx_td = &p_gmac_dev->p_rx_dscr[p_gmac_dev->us_rx_idx];\r
+ p_rx_td->addr.val &= ~(GMAC_RXD_OWNERSHIP);\r
+\r
+ circ_inc(&p_gmac_dev->us_rx_idx, p_gmac_dev->us_rx_list_size);\r
+ }\r
+ /* Reset the temporary frame pointer */\r
+ p_tmp_frame = p_frame;\r
+ tmp_ul_frame_size = 0;\r
+ /* Start to gather buffers in a frame */\r
+ c_is_frame = 1;\r
+ }\r
+\r
+ /* Increment the pointer */\r
+ circ_inc(&us_tmp_idx, p_gmac_dev->us_rx_list_size);\r
+\r
+ /* Copy data in the frame buffer */\r
+ if (c_is_frame) {\r
+ if (us_tmp_idx == p_gmac_dev->us_rx_idx) {\r
+ do {\r
+ p_rx_td = &p_gmac_dev->p_rx_dscr[p_gmac_dev->us_rx_idx];\r
+ p_rx_td->addr.val &= ~(GMAC_RXD_OWNERSHIP);\r
+ circ_inc(&p_gmac_dev->us_rx_idx, p_gmac_dev->us_rx_list_size);\r
+ \r
+ } while (us_tmp_idx != p_gmac_dev->us_rx_idx);\r
+\r
+ return GMAC_RX_NULL;\r
+ }\r
+ /* Copy the buffer into the application frame */\r
+ us_buffer_length = GMAC_RX_UNITSIZE;\r
+ if ((tmp_ul_frame_size + us_buffer_length) > ul_frame_size) {\r
+ us_buffer_length = ul_frame_size - tmp_ul_frame_size;\r
+ }\r
+\r
+ memcpy(p_tmp_frame,\r
+ (void *)(p_rx_td->addr.val & GMAC_RXD_ADDR_MASK),\r
+ us_buffer_length);\r
+ p_tmp_frame += us_buffer_length;\r
+ tmp_ul_frame_size += us_buffer_length;\r
+\r
+ /* An end of frame has been received, return the data */\r
+ if ((p_rx_td->status.val & GMAC_RXD_EOF) == GMAC_RXD_EOF) {\r
+ /* Frame size from the GMAC */\r
+ *p_rcv_size = (p_rx_td->status.val & GMAC_RXD_LEN_MASK);\r
+\r
+ /* All data have been copied in the application frame buffer => release TD */\r
+ while (p_gmac_dev->us_rx_idx != us_tmp_idx) {\r
+ p_rx_td = &p_gmac_dev->p_rx_dscr[p_gmac_dev->us_rx_idx];\r
+ p_rx_td->addr.val &= ~(GMAC_RXD_OWNERSHIP);\r
+ circ_inc(&p_gmac_dev->us_rx_idx, p_gmac_dev->us_rx_list_size);\r
+ }\r
+\r
+ /* Application frame buffer is too small so that all data have not been copied */\r
+ if (tmp_ul_frame_size < *p_rcv_size) {\r
+ return GMAC_SIZE_TOO_SMALL;\r
+ }\r
+\r
+ return GMAC_OK;\r
+ }\r
+ }\r
+ /* SOF has not been detected, skip the fragment */\r
+ else {\r
+ p_rx_td->addr.val &= ~(GMAC_RXD_OWNERSHIP);\r
+ p_gmac_dev->us_rx_idx = us_tmp_idx;\r
+ }\r
+\r
+ /* Process the next buffer */\r
+ p_rx_td = &p_gmac_dev->p_rx_dscr[us_tmp_idx];\r
+ }\r
+\r
+ return GMAC_RX_NULL;\r
+}\r
+\r
+/**\r
+ * \brief Send ulLength bytes from pcFrom. This copies the buffer to one of the\r
+ * GMAC Tx buffers, and then indicates to the GMAC that the buffer is ready.\r
+ * If lEndOfFrame is true then the data being copied is the end of the frame\r
+ * and the frame can be transmitted.\r
+ *\r
+ * \param p_gmac_dev Pointer to the GMAC device instance.\r
+ * \param p_buffer Pointer to the data buffer.\r
+ * \param ul_size Length of the frame.\r
+ * \param func_tx_cb Transmit callback function.\r
+ *\r
+ * \return Length sent.\r
+ */\r
+uint32_t gmac_dev_write(gmac_device_t* p_gmac_dev, void *p_buffer,\r
+ uint32_t ul_size, gmac_dev_tx_cb_t func_tx_cb)\r
+{\r
+\r
+ volatile gmac_tx_descriptor_t *p_tx_td;\r
+ volatile gmac_dev_tx_cb_t *p_func_tx_cb;\r
+\r
+ Gmac *p_hw = p_gmac_dev->p_hw;\r
+\r
+\r
+ /* Check parameter */\r
+ if (ul_size > GMAC_TX_UNITSIZE) {\r
+ return GMAC_PARAM;\r
+ }\r
+\r
+ /* Pointers to the current transmit descriptor */\r
+ p_tx_td = &p_gmac_dev->p_tx_dscr[p_gmac_dev->us_tx_head];\r
+\r
+ /* If no free TxTd, buffer can't be sent, schedule the wakeup callback */\r
+ if (CIRC_SPACE(p_gmac_dev->us_tx_head, p_gmac_dev->us_tx_tail,\r
+ p_gmac_dev->us_tx_list_size) == 0) {\r
+ if (p_tx_td[p_gmac_dev->us_tx_head].status.val & GMAC_TXD_USED)\r
+ return GMAC_TX_BUSY;\r
+ }\r
+\r
+ /* Pointers to the current Tx callback */\r
+ p_func_tx_cb = &p_gmac_dev->func_tx_cb_list[p_gmac_dev->us_tx_head];\r
+\r
+ /* Set up/copy data to transmission buffer */\r
+ if (p_buffer && ul_size) {\r
+ /* Driver manages the ring buffer */\r
+ memcpy((void *)p_tx_td->addr, p_buffer, ul_size);\r
+ }\r
+\r
+ /* Tx callback */\r
+ *p_func_tx_cb = func_tx_cb;\r
+\r
+ /* Update transmit descriptor status */\r
+\r
+ /* The buffer size defined is the length of ethernet frame,\r
+ so it's always the last buffer of the frame. */\r
+ if (p_gmac_dev->us_tx_head == p_gmac_dev->us_tx_list_size - 1) {\r
+ p_tx_td->status.val =\r
+ (ul_size & GMAC_TXD_LEN_MASK) | GMAC_TXD_LAST\r
+ | GMAC_TXD_WRAP;\r
+ } else {\r
+ p_tx_td->status.val =\r
+ (ul_size & GMAC_TXD_LEN_MASK) | GMAC_TXD_LAST;\r
+ }\r
+\r
+ circ_inc(&p_gmac_dev->us_tx_head, p_gmac_dev->us_tx_list_size);\r
+\r
+ /* Now start to transmit if it is still not done */\r
+ gmac_start_transmission(p_hw);\r
+\r
+ return GMAC_OK;\r
+}\r
+\r
+/**\r
+ * \brief Get current load of transmit.\r
+ *\r
+ * \param p_gmac_dev Pointer to the GMAC device instance.\r
+ *\r
+ * \return Current load of transmit. \r
+ */\r
+uint32_t gmac_dev_get_tx_load(gmac_device_t* p_gmac_dev)\r
+{\r
+ uint16_t us_head = p_gmac_dev->us_tx_head;\r
+ uint16_t us_tail = p_gmac_dev->us_tx_tail;\r
+ return CIRC_CNT(us_head, us_tail, p_gmac_dev->us_tx_list_size);\r
+}\r
+\r
+/**\r
+ * \brief Register/Clear RX callback. Callback will be invoked after the next received\r
+ * frame.\r
+ *\r
+ * When gmac_dev_read() returns GMAC_RX_NULL, the application task calls\r
+ * gmac_dev_set_rx_callback() to register func_rx_cb() callback and enters suspend state.\r
+ * The callback is in charge to resume the task once a new frame has been\r
+ * received. The next time gmac_dev_read() is called, it will be successful.\r
+ *\r
+ * This function is usually invoked from the RX callback itself with NULL\r
+ * callback, to unregister. Once the callback has resumed the application task,\r
+ * there is no need to invoke the callback again.\r
+ *\r
+ * \param p_gmac_dev Pointer to the GMAC device instance.\r
+ * \param func_tx_cb Receive callback function.\r
+ */\r
+void gmac_dev_set_rx_callback(gmac_device_t* p_gmac_dev,\r
+ gmac_dev_tx_cb_t func_rx_cb)\r
+{\r
+ Gmac *p_hw = p_gmac_dev->p_hw;\r
+\r
+ if (func_rx_cb == NULL) {\r
+ gmac_disable_interrupt(p_hw, GMAC_IDR_RCOMP);\r
+ p_gmac_dev->func_rx_cb = NULL;\r
+ } else {\r
+ p_gmac_dev->func_rx_cb = func_rx_cb;\r
+ gmac_enable_interrupt(p_hw, GMAC_IER_RCOMP);\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Register/Clear TX wakeup callback.\r
+ *\r
+ * When gmac_dev_write() returns GMAC_TX_BUSY (all transmit descriptor busy), the application\r
+ * task calls gmac_dev_set_tx_wakeup_callback() to register func_wakeup() callback and\r
+ * enters suspend state. The callback is in charge to resume the task once\r
+ * several transmit descriptors have been released. The next time gmac_dev_write() will be called,\r
+ * it shall be successful.\r
+ *\r
+ * This function is usually invoked with NULL callback from the TX wakeup\r
+ * callback itself, to unregister. Once the callback has resumed the\r
+ * application task, there is no need to invoke the callback again.\r
+ *\r
+ * \param p_gmac_dev Pointer to GMAC device instance.\r
+ * \param func_wakeup Pointer to wakeup callback function.\r
+ * \param uc_threshold Number of free transmit descriptor before wakeup callback invoked.\r
+ *\r
+ * \return GMAC_OK, GMAC_PARAM on parameter error.\r
+ */\r
+uint8_t gmac_dev_set_tx_wakeup_callback(gmac_device_t* p_gmac_dev,\r
+ gmac_dev_wakeup_cb_t func_wakeup_cb, uint8_t uc_threshold)\r
+{\r
+ if (func_wakeup_cb == NULL) {\r
+ p_gmac_dev->func_wakeup_cb = NULL;\r
+ } else {\r
+ if (uc_threshold <= p_gmac_dev->us_tx_list_size) {\r
+ p_gmac_dev->func_wakeup_cb = func_wakeup_cb;\r
+ p_gmac_dev->uc_wakeup_threshold = uc_threshold;\r
+ } else {\r
+ return GMAC_PARAM;\r
+ }\r
+ }\r
+\r
+ return GMAC_OK;\r
+}\r
+\r
+\r
+/**\r
+ * \brief Reset TX & RX queue & statistics.\r
+ *\r
+ * \param p_gmac_dev Pointer to GMAC device instance.\r
+ */\r
+void gmac_dev_reset(gmac_device_t* p_gmac_dev)\r
+{\r
+ Gmac *p_hw = p_gmac_dev->p_hw;\r
+\r
+ gmac_reset_rx_mem(p_gmac_dev);\r
+ gmac_reset_tx_mem(p_gmac_dev);\r
+ gmac_network_control(p_hw, GMAC_NCR_TXEN | GMAC_NCR_RXEN\r
+ | GMAC_NCR_WESTAT | GMAC_NCR_CLRSTAT);\r
+}\r
+\r
+\r
+/**\r
+ * \brief GMAC Interrupt handler.\r
+ *\r
+ * \param p_gmac_dev Pointer to GMAC device instance.\r
+ */\r
+void gmac_handler(gmac_device_t* p_gmac_dev)\r
+{\r
+ Gmac *p_hw = p_gmac_dev->p_hw;\r
+\r
+ gmac_tx_descriptor_t *p_tx_td;\r
+ gmac_dev_tx_cb_t *p_tx_cb;\r
+ volatile uint32_t ul_isr;\r
+ volatile uint32_t ul_rsr;\r
+ volatile uint32_t ul_tsr;\r
+ uint32_t ul_rx_status_flag;\r
+ uint32_t ul_tx_status_flag;\r
+\r
+ ul_isr = gmac_get_interrupt_status(p_hw);\r
+ ul_rsr = gmac_get_rx_status(p_hw);\r
+ ul_tsr = gmac_get_tx_status(p_hw);\r
+\r
+ ul_isr &= ~(gmac_get_interrupt_mask(p_hw) | 0xF8030300);\r
+\r
+ /* RX packet */\r
+ if ((ul_isr & GMAC_ISR_RCOMP) || (ul_rsr & GMAC_RSR_REC)) {\r
+ ul_rx_status_flag = GMAC_RSR_REC;\r
+\r
+ /* Check OVR */\r
+ if (ul_rsr & GMAC_RSR_RXOVR) {\r
+ ul_rx_status_flag |= GMAC_RSR_RXOVR;\r
+ }\r
+ /* Check BNA */\r
+ if (ul_rsr & GMAC_RSR_BNA) {\r
+ ul_rx_status_flag |= GMAC_RSR_BNA;\r
+ }\r
+ /* Clear status */\r
+ gmac_clear_rx_status(p_hw, ul_rx_status_flag);\r
+\r
+ /* Invoke callbacks */\r
+ if (p_gmac_dev->func_rx_cb) {\r
+ p_gmac_dev->func_rx_cb(ul_rx_status_flag);\r
+ }\r
+ }\r
+\r
+ /* TX packet */\r
+ if ((ul_isr & GMAC_ISR_TCOMP) || (ul_tsr & GMAC_TSR_TXCOMP)) {\r
+\r
+ ul_tx_status_flag = GMAC_TSR_TXCOMP;\r
+\r
+ /* A frame transmitted */\r
+\r
+ /* Check RLE */\r
+ if (ul_tsr & GMAC_TSR_RLE) {\r
+ /* Status RLE & Number of discarded buffers */\r
+ ul_tx_status_flag = GMAC_TSR_RLE | CIRC_CNT(p_gmac_dev->us_tx_head,\r
+ p_gmac_dev->us_tx_tail, p_gmac_dev->us_tx_list_size);\r
+ p_tx_cb = &p_gmac_dev->func_tx_cb_list[p_gmac_dev->us_tx_tail];\r
+ gmac_reset_tx_mem(p_gmac_dev);\r
+ gmac_enable_transmit(p_hw, 1);\r
+ }\r
+ /* Check COL */\r
+ if (ul_tsr & GMAC_TSR_COL) {\r
+ ul_tx_status_flag |= GMAC_TSR_COL;\r
+ }\r
+ /* Check UND */\r
+ if (ul_tsr & GMAC_TSR_UND) {\r
+ ul_tx_status_flag |= GMAC_TSR_UND;\r
+ }\r
+ /* Clear status */\r
+ gmac_clear_tx_status(p_hw, ul_tx_status_flag);\r
+\r
+ if (!CIRC_EMPTY(p_gmac_dev->us_tx_head, p_gmac_dev->us_tx_tail)) {\r
+ /* Check the buffers */\r
+ do {\r
+ p_tx_td = &p_gmac_dev->p_tx_dscr[p_gmac_dev->us_tx_tail];\r
+ p_tx_cb = &p_gmac_dev->func_tx_cb_list[p_gmac_dev->us_tx_tail];\r
+ /* Any error? Exit if buffer has not been sent yet */\r
+ if ((p_tx_td->status.val & GMAC_TXD_USED) == 0) {\r
+ break;\r
+ }\r
+\r
+ /* Notify upper layer that a packet has been sent */\r
+ if (*p_tx_cb) {\r
+ (*p_tx_cb) (ul_tx_status_flag);\r
+ }\r
+\r
+ circ_inc(&p_gmac_dev->us_tx_tail, p_gmac_dev->us_tx_list_size);\r
+ } while (CIRC_CNT(p_gmac_dev->us_tx_head, p_gmac_dev->us_tx_tail,\r
+ p_gmac_dev->us_tx_list_size));\r
+ }\r
+\r
+ if (ul_tsr & GMAC_TSR_RLE) {\r
+ /* Notify upper layer RLE */\r
+ if (*p_tx_cb) {\r
+ (*p_tx_cb) (ul_tx_status_flag);\r
+ }\r
+ }\r
+\r
+ /* If a wakeup has been scheduled, notify upper layer that it can\r
+ send other packets, and the sending will be successful. */\r
+ if ((CIRC_SPACE(p_gmac_dev->us_tx_head, p_gmac_dev->us_tx_tail,\r
+ p_gmac_dev->us_tx_list_size) >= p_gmac_dev->uc_wakeup_threshold)\r
+ && p_gmac_dev->func_wakeup_cb) {\r
+ p_gmac_dev->func_wakeup_cb();\r
+ }\r
+ }\r
+}\r
+\r
+//@}\r
+\r
+/// @cond 0\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+/**INDENT-ON**/\r
+/// @endcond\r
--- /dev/null
+ /**\r
+ * \file\r
+ *\r
+ * \brief GMAC (Ethernet MAC) driver for SAM.\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef GMAC_H_INCLUDED\r
+#define GMAC_H_INCLUDED\r
+\r
+#include "compiler.h"\r
+\r
+/// @cond 0\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+/**INDENT-ON**/\r
+/// @endcond\r
+\r
+/** The buffer addresses written into the descriptors must be aligned, so the\r
+ last few bits are zero. These bits have special meaning for the GMAC\r
+ peripheral and cannot be used as part of the address. */\r
+#define GMAC_RXD_ADDR_MASK 0xFFFFFFFC\r
+#define GMAC_RXD_WRAP (1ul << 1) /**< Wrap bit */\r
+#define GMAC_RXD_OWNERSHIP (1ul << 0) /**< Ownership bit */\r
+\r
+#define GMAC_RXD_BROADCAST (1ul << 31) /**< Broadcast detected */\r
+#define GMAC_RXD_MULTIHASH (1ul << 30) /**< Multicast hash match */\r
+#define GMAC_RXD_UNIHASH (1ul << 29) /**< Unicast hash match */\r
+#define GMAC_RXD_ADDR_FOUND (1ul << 27) /**< Specific address match found */\r
+#define GMAC_RXD_ADDR (3ul << 25) /**< Address match */\r
+#define GMAC_RXD_RXCOEN (1ul << 24) /**< RXCOEN related function */\r
+#define GMAC_RXD_TYPE (3ul << 22) /**< Type ID match */\r
+#define GMAC_RXD_VLAN (1ul << 21) /**< VLAN tag detected */\r
+#define GMAC_RXD_PRIORITY (1ul << 20) /**< Priority tag detected */\r
+#define GMAC_RXD_PRIORITY_MASK (3ul << 17) /**< VLAN priority */\r
+#define GMAC_RXD_CFI (1ul << 16) /**< Concatenation Format Indicator only if bit 21 is set */\r
+#define GMAC_RXD_EOF (1ul << 15) /**< End of frame */\r
+#define GMAC_RXD_SOF (1ul << 14) /**< Start of frame */\r
+#define GMAC_RXD_FCS (1ul << 13) /**< Frame check sequence */\r
+#define GMAC_RXD_OFFSET_MASK /**< Receive buffer offset */\r
+#define GMAC_RXD_LEN_MASK (0xFFF) /**< Length of frame including FCS (if selected) */\r
+#define GMAC_RXD_LENJUMBO_MASK (0x3FFF) /**< Jumbo frame length */\r
+\r
+#define GMAC_TXD_USED (1ul << 31) /**< Frame is transmitted */\r
+#define GMAC_TXD_WRAP (1ul << 30) /**< Last descriptor */\r
+#define GMAC_TXD_ERROR (1ul << 29) /**< Retry limit exceeded, error */\r
+#define GMAC_TXD_UNDERRUN (1ul << 28) /**< Transmit underrun */\r
+#define GMAC_TXD_EXHAUSTED (1ul << 27) /**< Buffer exhausted */\r
+#define GMAC_TXD_LATE (1ul << 26) /**< Late collision,transmit error */\r
+#define GMAC_TXD_CHECKSUM_ERROR (7ul << 20) /**< Checksum error */\r
+#define GMAC_TXD_NOCRC (1ul << 16) /**< No CRC */\r
+#define GMAC_TXD_LAST (1ul << 15) /**< Last buffer in frame */\r
+#define GMAC_TXD_LEN_MASK (0x1FFF) /**< Length of buffer */\r
+\r
+/** The MAC can support frame lengths up to 1536 bytes */\r
+#define GMAC_FRAME_LENTGH_MAX 1536\r
+\r
+#define GMAC_RX_UNITSIZE 128 /**< Fixed size for RX buffer */\r
+#define GMAC_TX_UNITSIZE 1518 /**< Size for ETH frame length */\r
+\r
+/** GMAC clock speed */\r
+#define GMAC_MCK_SPEED_240MHZ (240*1000*1000)\r
+#define GMAC_MCK_SPEED_160MHZ (160*1000*1000)\r
+#define GMAC_MCK_SPEED_120MHZ (120*1000*1000)\r
+#define GMAC_MCK_SPEED_80MHZ (80*1000*1000)\r
+#define GMAC_MCK_SPEED_40MHZ (40*1000*1000)\r
+#define GMAC_MCK_SPEED_20MHZ (20*1000*1000)\r
+\r
+/** GMAC maintain code default value*/\r
+#define GMAC_MAN_CODE_VALUE (10)\r
+\r
+/** GMAC maintain start of frame default value*/\r
+#define GMAC_MAN_SOF_VALUE (1)\r
+\r
+/** GMAC maintain read/write*/\r
+#define GMAC_MAN_RW_TYPE (2)\r
+\r
+/** GMAC maintain read only*/\r
+#define GMAC_MAN_READ_ONLY (1)\r
+\r
+/** GMAC address length */\r
+#define GMAC_ADDR_LENGTH (6)\r
+\r
+\r
+#define GMAC_DUPLEX_HALF 0\r
+#define GMAC_DUPLEX_FULL 1\r
+\r
+#define GMAC_SPEED_10M 0\r
+#define GMAC_SPEED_100M 1\r
+\r
+/**\r
+ * \brief Return codes for GMAC APIs.\r
+ */\r
+typedef enum {\r
+ GMAC_OK = 0, /** Operation OK */\r
+ GMAC_TIMEOUT = 1, /** GMAC operation timeout */\r
+ GMAC_TX_BUSY, /** TX in progress */\r
+ GMAC_RX_NULL, /** No data received */\r
+ GMAC_SIZE_TOO_SMALL, /** Buffer size not enough */\r
+ GMAC_PARAM, /** Parameter error, TX packet invalid or RX size too small */\r
+ GMAC_INVALID = 0xFF, /* Invalid */\r
+} gmac_status_t;\r
+\r
+/**\r
+ * \brief Media Independent Interface (MII) type.\r
+ */\r
+typedef enum {\r
+ GMAC_PHY_MII = 0, /** MII mode */\r
+ GMAC_PHY_RMII = 1, /** Reduced MII mode */\r
+ GMAC_PHY_INVALID = 0xFF, /* Invalid mode*/\r
+} gmac_mii_mode_t;\r
+\r
+/** Receive buffer descriptor struct */\r
+COMPILER_PACK_SET(8)\r
+typedef struct gmac_rx_descriptor {\r
+ union gmac_rx_addr {\r
+ uint32_t val;\r
+ struct gmac_rx_addr_bm {\r
+ uint32_t b_ownership:1, /**< User clear, GMAC sets this to 1 once it has successfully written a frame to memory */\r
+ b_wrap:1, /**< Marks last descriptor in receive buffer */\r
+ addr_dw:30; /**< Address in number of DW */\r
+ } bm;\r
+ } addr; /**< Address, Wrap & Ownership */\r
+ union gmac_rx_status {\r
+ uint32_t val;\r
+ struct gmac_rx_status_bm {\r
+ uint32_t len:13, /** Length of frame including FCS */\r
+ b_fcs:1, /** Receive buffer offset, bits 13:12 of frame length for jumbo frame */\r
+ b_sof:1, /** Start of frame */\r
+ b_eof:1, /** End of frame */\r
+ b_cfi:1, /** Concatenation Format Indicator */\r
+ vlan_priority:3, /** VLAN priority (if VLAN detected) */\r
+ b_priority_detected:1, /** Priority tag detected */\r
+ b_vlan_detected:1, /**< VLAN tag detected */\r
+ b_type_id_match:2, /**< Type ID match */\r
+ b_checksumoffload:1, /**< Checksum offload specific function */\r
+ b_addrmatch:2, /**< Address register match */\r
+ b_ext_addr_match:1, /**< External address match found */\r
+ reserved:1,\r
+ b_uni_hash_match:1, /**< Unicast hash match */\r
+ b_multi_hash_match:1, /**< Multicast hash match */\r
+ b_boardcast_detect:1; /**< Global broadcast address detected */\r
+ } bm;\r
+ } status;\r
+} gmac_rx_descriptor_t;\r
+\r
+/** Transmit buffer descriptor struct */\r
+COMPILER_PACK_SET(8)\r
+typedef struct gmac_tx_descriptor {\r
+ uint32_t addr;\r
+ union gmac_tx_status {\r
+ uint32_t val;\r
+ struct gmac_tx_status_bm {\r
+ uint32_t len:14, /**< Length of buffer */\r
+ reserved:1,\r
+ b_last_buffer:1, /**< Last buffer (in the current frame) */\r
+ b_no_crc:1, /**< No CRC */\r
+ reserved1:3,\r
+ b_checksumoffload:3, /**< Transmit checksum generation offload errors */\r
+ reserved2:3,\r
+ b_lco:1, /**< Late collision, transmit error detected */\r
+ b_exhausted:1, /**< Buffer exhausted in mid frame */\r
+ b_underrun:1, /**< Transmit underrun */\r
+ b_error:1, /**< Retry limit exceeded, error detected */\r
+ b_wrap:1, /**< Marks last descriptor in TD list */\r
+ b_used:1; /**< User clear, GMAC sets this to 1 once a frame has been successfully transmitted */\r
+ } bm;\r
+ } status;\r
+} gmac_tx_descriptor_t;\r
+\r
+COMPILER_PACK_RESET()\r
+\r
+/**\r
+ * \brief Input parameters when initializing the gmac module mode.\r
+ */\r
+typedef struct gmac_options {\r
+ /* Enable/Disable CopyAllFrame */\r
+ uint8_t uc_copy_all_frame;\r
+ /* Enable/Disable NoBroadCast */\r
+ uint8_t uc_no_boardcast;\r
+ /* MAC address */\r
+ uint8_t uc_mac_addr[GMAC_ADDR_LENGTH];\r
+} gmac_options_t;\r
+\r
+/** RX callback */\r
+typedef void (*gmac_dev_tx_cb_t) (uint32_t ul_status);\r
+/** Wakeup callback */\r
+typedef void (*gmac_dev_wakeup_cb_t) (void);\r
+\r
+/**\r
+ * GMAC driver structure.\r
+ */\r
+typedef struct gmac_device {\r
+\r
+ /** Pointer to HW register base */\r
+ Gmac *p_hw;\r
+ /**\r
+ * Pointer to allocated TX buffer.\r
+ * Section 3.6 of AMBA 2.0 spec states that burst should not cross\r
+ * 1K Boundaries.\r
+ * Receive buffer manager writes are burst of 2 words => 3 lsb bits\r
+ * of the address shall be set to 0.\r
+ */\r
+ uint8_t *p_tx_buffer;\r
+ /** Pointer to allocated RX buffer */\r
+ uint8_t *p_rx_buffer;\r
+ /** Pointer to Rx TDs (must be 8-byte aligned) */\r
+ gmac_rx_descriptor_t *p_rx_dscr;\r
+ /** Pointer to Tx TDs (must be 8-byte aligned) */\r
+ gmac_tx_descriptor_t *p_tx_dscr;\r
+ /** Optional callback to be invoked once a frame has been received */\r
+ gmac_dev_tx_cb_t func_rx_cb;\r
+ /** Optional callback to be invoked once several TDs have been released */\r
+ gmac_dev_wakeup_cb_t func_wakeup_cb;\r
+ /** Optional callback list to be invoked once TD has been processed */\r
+ gmac_dev_tx_cb_t *func_tx_cb_list;\r
+ /** RX TD list size */\r
+ uint16_t us_rx_list_size;\r
+ /** RX index for current processing TD */\r
+ uint16_t us_rx_idx;\r
+ /** TX TD list size */\r
+ uint16_t us_tx_list_size;\r
+ /** Circular buffer head pointer by upper layer (buffer to be sent) */\r
+ uint16_t us_tx_head;\r
+ /** Circular buffer tail pointer incremented by handlers (buffer sent) */\r
+ uint16_t us_tx_tail;\r
+\r
+ /** Number of free TD before wakeup callback is invoked */\r
+ uint8_t uc_wakeup_threshold;\r
+} gmac_device_t;\r
+\r
+/**\r
+ * \brief Write network control value.\r
+ *\r
+ * \param p_gmac Pointer to the GMAC instance.\r
+ * \param ul_ncr Network control value.\r
+ */\r
+static inline void gmac_network_control(Gmac* p_gmac, uint32_t ul_ncr)\r
+{\r
+ p_gmac->GMAC_NCR = ul_ncr;\r
+}\r
+\r
+/**\r
+ * \brief Get network control value.\r
+ *\r
+ * \param p_gmac Pointer to the GMAC instance.\r
+ */\r
+\r
+static inline uint32_t gmac_get_network_control(Gmac* p_gmac)\r
+{\r
+ return p_gmac->GMAC_NCR;\r
+}\r
+\r
+/**\r
+ * \brief Enable/Disable GMAC receive.\r
+ *\r
+ * \param p_gmac Pointer to the GMAC instance.\r
+ * \param uc_enable 0 to disable GMAC receiver, else to enable it.\r
+ */\r
+static inline void gmac_enable_receive(Gmac* p_gmac, uint8_t uc_enable)\r
+{\r
+ if (uc_enable) {\r
+ p_gmac->GMAC_NCR |= GMAC_NCR_RXEN;\r
+ } else {\r
+ p_gmac->GMAC_NCR &= ~GMAC_NCR_RXEN;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Enable/Disable GMAC transmit.\r
+ *\r
+ * \param p_gmac Pointer to the GMAC instance.\r
+ * \param uc_enable 0 to disable GMAC transmit, else to enable it.\r
+ */\r
+static inline void gmac_enable_transmit(Gmac* p_gmac, uint8_t uc_enable)\r
+{\r
+ if (uc_enable) {\r
+ p_gmac->GMAC_NCR |= GMAC_NCR_TXEN;\r
+ } else {\r
+ p_gmac->GMAC_NCR &= ~GMAC_NCR_TXEN;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Enable/Disable GMAC management.\r
+ *\r
+ * \param p_gmac Pointer to the GMAC instance.\r
+ * \param uc_enable 0 to disable GMAC management, else to enable it.\r
+ */\r
+static inline void gmac_enable_management(Gmac* p_gmac, uint8_t uc_enable)\r
+{\r
+ if (uc_enable) {\r
+ p_gmac->GMAC_NCR |= GMAC_NCR_MPE;\r
+ } else {\r
+ p_gmac->GMAC_NCR &= ~GMAC_NCR_MPE;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Clear all statistics registers.\r
+ *\r
+ * \param p_gmac Pointer to the GMAC instance.\r
+ */\r
+static inline void gmac_clear_statistics(Gmac* p_gmac)\r
+{\r
+ p_gmac->GMAC_NCR |= GMAC_NCR_CLRSTAT;\r
+}\r
+\r
+/**\r
+ * \brief Increase all statistics registers.\r
+ *\r
+ * \param p_gmac Pointer to the GMAC instance.\r
+ */\r
+static inline void gmac_increase_statistics(Gmac* p_gmac)\r
+{\r
+ p_gmac->GMAC_NCR |= GMAC_NCR_INCSTAT;\r
+}\r
+\r
+/**\r
+ * \brief Enable/Disable statistics registers writing.\r
+ *\r
+ * \param p_gmac Pointer to the GMAC instance.\r
+ * \param uc_enable 0 to disable the statistics registers writing, else to enable it.\r
+ */\r
+static inline void gmac_enable_statistics_write(Gmac* p_gmac,\r
+ uint8_t uc_enable)\r
+{\r
+ if (uc_enable) {\r
+ p_gmac->GMAC_NCR |= GMAC_NCR_WESTAT;\r
+ } else {\r
+ p_gmac->GMAC_NCR &= ~GMAC_NCR_WESTAT;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief In half-duplex mode, forces collisions on all received frames.\r
+ *\r
+ * \param p_gmac Pointer to the GMAC instance.\r
+ * \param uc_enable 0 to disable the back pressure, else to enable it.\r
+ */\r
+static inline void gmac_enable_back_pressure(Gmac* p_gmac, uint8_t uc_enable)\r
+{\r
+ if (uc_enable) {\r
+ p_gmac->GMAC_NCR |= GMAC_NCR_BP;\r
+ } else {\r
+ p_gmac->GMAC_NCR &= ~GMAC_NCR_BP;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Start transmission.\r
+ *\r
+ * \param p_gmac Pointer to the GMAC instance.\r
+ */\r
+static inline void gmac_start_transmission(Gmac* p_gmac)\r
+{\r
+ p_gmac->GMAC_NCR |= GMAC_NCR_TSTART;\r
+}\r
+\r
+/**\r
+ * \brief Halt transmission.\r
+ *\r
+ * \param p_gmac Pointer to the GMAC instance.\r
+ */\r
+static inline void gmac_halt_transmission(Gmac* p_gmac)\r
+{\r
+ p_gmac->GMAC_NCR |= GMAC_NCR_THALT;\r
+}\r
+\r
+/**\r
+ * \brief Transmit pause frame.\r
+ *\r
+ * \param p_gmac Pointer to the GMAC instance.\r
+ */\r
+static inline void gmac_tx_pause_frame(Gmac* p_gmac)\r
+{\r
+ p_gmac->GMAC_NCR |= GMAC_NCR_TXPF;\r
+}\r
+\r
+/**\r
+ * \brief Transmit zero quantum pause frame.\r
+ *\r
+ * \param p_gmac Pointer to the GMAC instance.\r
+ */\r
+static inline void gmac_tx_pause_zero_quantum_frame(Gmac* p_gmac)\r
+{\r
+ p_gmac->GMAC_NCR |= GMAC_NCR_TXZQPF;\r
+}\r
+\r
+/**\r
+ * \brief Read snapshot.\r
+ *\r
+ * \param p_gmac Pointer to the GMAC instance.\r
+ */\r
+static inline void gmac_read_snapshot(Gmac* p_gmac)\r
+{\r
+ p_gmac->GMAC_NCR |= GMAC_NCR_RDS;\r
+}\r
+\r
+/**\r
+ * \brief Store receivetime stamp to memory.\r
+ *\r
+ * \param p_gmac Pointer to the GMAC instance.\r
+ * \param uc_enable 0 to normal operation, else to enable the store.\r
+ */\r
+static inline void gmac_store_rx_time_stamp(Gmac* p_gmac, uint8_t uc_enable)\r
+{\r
+ if (uc_enable) {\r
+ p_gmac->GMAC_NCR |= GMAC_NCR_SRTSM;\r
+ } else {\r
+ p_gmac->GMAC_NCR &= ~GMAC_NCR_SRTSM;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Enable PFC priority-based pause reception.\r
+ *\r
+ * \param p_gmac Pointer to the GMAC instance.\r
+ * \param uc_enable 1 to set the reception, 0 to disable.\r
+ */\r
+static inline void gmac_enable_pfc_pause_frame(Gmac* p_gmac, uint8_t uc_enable)\r
+{\r
+ if (uc_enable) {\r
+ p_gmac->GMAC_NCR |= GMAC_NCR_ENPBPR;\r
+ } else {\r
+ p_gmac->GMAC_NCR &= ~GMAC_NCR_ENPBPR;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Transmit PFC priority-based pause reception.\r
+ *\r
+ * \param p_gmac Pointer to the GMAC instance.\r
+ */\r
+static inline void gmac_transmit_pfc_pause_frame(Gmac* p_gmac)\r
+{\r
+ p_gmac->GMAC_NCR |= GMAC_NCR_TXPBPF;\r
+}\r
+\r
+/**\r
+ * \brief Flush next packet.\r
+ *\r
+ * \param p_gmac Pointer to the GMAC instance.\r
+ */\r
+static inline void gmac_flush_next_packet(Gmac* p_gmac)\r
+{\r
+ p_gmac->GMAC_NCR |= GMAC_NCR_FNP;\r
+}\r
+\r
+/**\r
+ * \brief Set up network configuration register.\r
+ *\r
+ * \param p_gmac Pointer to the GMAC instance.\r
+ * \param ul_cfg Network configuration value.\r
+ */\r
+static inline void gmac_set_configure(Gmac* p_gmac, uint32_t ul_cfg)\r
+{\r
+ p_gmac->GMAC_NCFGR = ul_cfg;\r
+}\r
+\r
+/**\r
+ * \brief Get network configuration.\r
+ *\r
+ * \param p_gmac Pointer to the GMAC instance.\r
+ *\r
+ * \return Network configuration.\r
+ */\r
+static inline uint32_t gmac_get_configure(Gmac* p_gmac)\r
+{\r
+ return p_gmac->GMAC_NCFGR;\r
+}\r
+\r
+/**\r
+ * \brief Set speed.\r
+ *\r
+ * \param p_gmac Pointer to the GMAC instance.\r
+ * \param uc_speed 1 to indicate 100Mbps, 0 to 10Mbps.\r
+ */\r
+static inline void gmac_set_speed(Gmac* p_gmac, uint8_t uc_speed)\r
+{\r
+ if (uc_speed) {\r
+ p_gmac->GMAC_NCFGR |= GMAC_NCFGR_SPD;\r
+ } else {\r
+ p_gmac->GMAC_NCFGR &= ~GMAC_NCFGR_SPD;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Enable/Disable Full-Duplex mode.\r
+ *\r
+ * \param p_gmac Pointer to the GMAC instance.\r
+ * \param uc_enable 0 to disable the Full-Duplex mode, else to enable it.\r
+ */\r
+static inline void gmac_enable_full_duplex(Gmac* p_gmac, uint8_t uc_enable)\r
+{\r
+ if (uc_enable) {\r
+ p_gmac->GMAC_NCFGR |= GMAC_NCFGR_FD;\r
+ } else {\r
+ p_gmac->GMAC_NCFGR &= ~GMAC_NCFGR_FD;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Enable/Disable Copy(Receive) All Valid Frames.\r
+ *\r
+ * \param p_gmac Pointer to the GMAC instance.\r
+ * \param uc_enable 0 to disable copying all valid frames, else to enable it.\r
+ */\r
+static inline void gmac_enable_copy_all(Gmac* p_gmac, uint8_t uc_enable)\r
+{\r
+ if (uc_enable) {\r
+ p_gmac->GMAC_NCFGR |= GMAC_NCFGR_CAF;\r
+ } else {\r
+ p_gmac->GMAC_NCFGR &= ~GMAC_NCFGR_CAF;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Enable/Disable jumbo frames (up to 10240 bytes).\r
+ *\r
+ * \param p_gmac Pointer to the GMAC instance.\r
+ * \param uc_enable 0 to disable the jumbo frames, else to enable it.\r
+ */\r
+static inline void gmac_enable_jumbo_frames(Gmac* p_gmac, uint8_t uc_enable)\r
+{\r
+ if (uc_enable) {\r
+ p_gmac->GMAC_NCFGR |= GMAC_NCFGR_JFRAME;\r
+ } else {\r
+ p_gmac->GMAC_NCFGR &= ~GMAC_NCFGR_JFRAME;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Disable/Enable broadcast receiving.\r
+ *\r
+ * \param p_gmac Pointer to the GMAC instance.\r
+ * \param uc_enable 1 to disable the broadcast, else to enable it.\r
+ */\r
+static inline void gmac_disable_broadcast(Gmac* p_gmac, uint8_t uc_enable)\r
+{\r
+ if (uc_enable) {\r
+ p_gmac->GMAC_NCFGR |= GMAC_NCFGR_NBC;\r
+ } else {\r
+ p_gmac->GMAC_NCFGR &= ~GMAC_NCFGR_NBC;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Enable/Disable multicast hash.\r
+ *\r
+ * \param p_gmac Pointer to the GMAC instance.\r
+ * \param uc_enable 0 to disable the multicast hash, else to enable it.\r
+ */\r
+static inline void gmac_enable_multicast_hash(Gmac* p_gmac, uint8_t uc_enable)\r
+{\r
+ if (uc_enable) {\r
+ p_gmac->GMAC_NCFGR |= GMAC_NCFGR_UNIHEN;\r
+ } else {\r
+ p_gmac->GMAC_NCFGR &= ~GMAC_NCFGR_UNIHEN;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Enable/Disable big frames (over 1518, up to 1536).\r
+ *\r
+ * \param p_gmac Pointer to the GMAC instance.\r
+ * \param uc_enable 0 to disable big frames else to enable it.\r
+ */\r
+static inline void gmac_enable_big_frame(Gmac* p_gmac, uint8_t uc_enable)\r
+{\r
+ if (uc_enable) {\r
+ p_gmac->GMAC_NCFGR |= GMAC_NCFGR_MAXFS;\r
+ } else {\r
+ p_gmac->GMAC_NCFGR &= ~GMAC_NCFGR_MAXFS;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Set MDC clock divider.\r
+ *\r
+ * \param p_gmac Pointer to the GMAC instance.\r
+ * \param ul_mck GMAC MCK.\r
+ *\r
+ * \return GMAC_OK if successfully.\r
+ */\r
+static inline uint8_t gmac_set_mdc_clock(Gmac* p_gmac, uint32_t ul_mck)\r
+{\r
+ uint32_t ul_clk;\r
+ \r
+ if (ul_mck > GMAC_MCK_SPEED_240MHZ) {\r
+ return GMAC_INVALID;\r
+ } else if (ul_mck > GMAC_MCK_SPEED_160MHZ) {\r
+ ul_clk = GMAC_NCFGR_CLK_MCK_96;\r
+ } else if (ul_mck > GMAC_MCK_SPEED_120MHZ) {\r
+ ul_clk = GMAC_NCFGR_CLK_MCK_64;\r
+ } else if (ul_mck > GMAC_MCK_SPEED_80MHZ) {\r
+ ul_clk = GMAC_NCFGR_CLK_MCK_48;\r
+ } else if (ul_mck > GMAC_MCK_SPEED_40MHZ) {\r
+ ul_clk = GMAC_NCFGR_CLK_MCK_32;\r
+ } else if (ul_mck > GMAC_MCK_SPEED_20MHZ) {\r
+ ul_clk = GMAC_NCFGR_CLK_MCK_16;\r
+ } else {\r
+ ul_clk = GMAC_NCFGR_CLK_MCK_8;\r
+ }\r
+ p_gmac->GMAC_NCFGR &= ~GMAC_NCFGR_CLK_Msk;\r
+ p_gmac->GMAC_NCFGR |= ul_clk;\r
+ return GMAC_OK;\r
+}\r
+\r
+/**\r
+ * \brief Enable/Disable retry test.\r
+ *\r
+ * \param p_gmac Pointer to the GMAC instance.\r
+ * \param uc_enable 0 to disable the GMAC receiver, else to enable it.\r
+ */\r
+static inline void gmac_enable_retry_test(Gmac* p_gmac, uint8_t uc_enable)\r
+{\r
+ if (uc_enable) {\r
+ p_gmac->GMAC_NCFGR |= GMAC_NCFGR_RTY;\r
+ } else {\r
+ p_gmac->GMAC_NCFGR &= ~GMAC_NCFGR_RTY;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Enable/Disable pause (when a valid pause frame is received).\r
+ *\r
+ * \param p_gmac Pointer to the GMAC instance.\r
+ * \param uc_enable 0 to disable pause frame, else to enable it.\r
+ */\r
+static inline void gmac_enable_pause_frame(Gmac* p_gmac, uint8_t uc_enable)\r
+{\r
+ if (uc_enable) {\r
+ p_gmac->GMAC_NCFGR |= GMAC_NCFGR_PEN;\r
+ } else {\r
+ p_gmac->GMAC_NCFGR &= ~GMAC_NCFGR_PEN;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Set receive buffer offset to 0 ~ 3.\r
+ *\r
+ * \param p_gmac Pointer to the GMAC instance.\r
+ */\r
+static inline void gmac_set_rx_buffer_offset(Gmac* p_gmac, uint8_t uc_offset)\r
+{\r
+ p_gmac->GMAC_NCFGR &= ~GMAC_NCFGR_RXBUFO_Msk;\r
+ p_gmac->GMAC_NCFGR |= GMAC_NCFGR_RXBUFO(uc_offset);\r
+}\r
+\r
+/**\r
+ * \brief Enable/Disable receive length field checking.\r
+ *\r
+ * \param p_gmac Pointer to the GMAC instance.\r
+ * \param uc_enable 0 to disable receive length field checking, else to enable it.\r
+ */\r
+static inline void gmac_enable_rx_length_check(Gmac* p_gmac, uint8_t uc_enable)\r
+{\r
+ if (uc_enable) {\r
+ p_gmac->GMAC_NCFGR |= GMAC_NCFGR_LFERD;\r
+ } else {\r
+ p_gmac->GMAC_NCFGR &= ~GMAC_NCFGR_LFERD;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Enable/Disable discarding FCS field of received frames.\r
+ *\r
+ * \param p_gmac Pointer to the GMAC instance.\r
+ * \param uc_enable 0 to disable discarding FCS field of received frames, else to enable it.\r
+ */\r
+static inline void gmac_enable_discard_fcs(Gmac* p_gmac, uint8_t uc_enable)\r
+{\r
+ if (uc_enable) {\r
+ p_gmac->GMAC_NCFGR |= GMAC_NCFGR_RFCS;\r
+ } else {\r
+ p_gmac->GMAC_NCFGR &= ~GMAC_NCFGR_RFCS;\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ * \brief Enable/Disable frames to be received in half-duplex mode\r
+ * while transmitting.\r
+ *\r
+ * \param p_gmac Pointer to the GMAC instance.\r
+ * \param uc_enable 0 to disable the received in half-duplex mode, else to enable it.\r
+ */\r
+static inline void gmac_enable_efrhd(Gmac* p_gmac, uint8_t uc_enable)\r
+{\r
+ if (uc_enable) {\r
+ p_gmac->GMAC_NCFGR |= GMAC_NCFGR_EFRHD;\r
+ } else {\r
+ p_gmac->GMAC_NCFGR &= ~GMAC_NCFGR_EFRHD;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Enable/Disable ignore RX FCS.\r
+ *\r
+ * \param p_gmac Pointer to the GMAC instance.\r
+ * \param uc_enable 0 to disable ignore RX FCS, else to enable it.\r
+ */\r
+static inline void gmac_enable_ignore_rx_fcs(Gmac* p_gmac, uint8_t uc_enable)\r
+{\r
+ if (uc_enable) {\r
+ p_gmac->GMAC_NCFGR |= GMAC_NCFGR_IRXFCS;\r
+ } else {\r
+ p_gmac->GMAC_NCFGR &= ~GMAC_NCFGR_IRXFCS;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Get Network Status.\r
+ *\r
+ * \param p_gmac Pointer to the GMAC instance.\r
+ *\r
+ * \return Network status.\r
+ */\r
+static inline uint32_t gmac_get_status(Gmac* p_gmac)\r
+{\r
+ return p_gmac->GMAC_NSR;\r
+}\r
+\r
+/**\r
+ * \brief Get MDIO IN pin status.\r
+ *\r
+ * \param p_gmac Pointer to the GMAC instance.\r
+ *\r
+ * \return MDIO IN pin status.\r
+ */\r
+static inline uint8_t gmac_get_MDIO(Gmac* p_gmac)\r
+{\r
+ return ((p_gmac->GMAC_NSR & GMAC_NSR_MDIO) > 0);\r
+}\r
+\r
+/**\r
+ * \brief Check if PHY is idle.\r
+ *\r
+ * \param p_gmac Pointer to the GMAC instance.\r
+ *\r
+ * \return 1 if PHY is idle.\r
+ */\r
+static inline uint8_t gmac_is_phy_idle(Gmac* p_gmac)\r
+{\r
+ return ((p_gmac->GMAC_NSR & GMAC_NSR_IDLE) > 0);\r
+}\r
+\r
+/**\r
+ * \brief Return transmit status.\r
+ *\r
+ * \param p_gmac Pointer to the GMAC instance.\r
+ *\r
+ * \return Transmit status.\r
+ */\r
+static inline uint32_t gmac_get_tx_status(Gmac* p_gmac)\r
+{\r
+ return p_gmac->GMAC_TSR;\r
+}\r
+\r
+/**\r
+ * \brief Clear transmit status.\r
+ *\r
+ * \param p_gmac Pointer to the GMAC instance.\r
+ * \param ul_status Transmit status.\r
+ */\r
+static inline void gmac_clear_tx_status(Gmac* p_gmac, uint32_t ul_status)\r
+{\r
+ p_gmac->GMAC_TSR = ul_status;\r
+}\r
+\r
+/**\r
+ * \brief Return receive status.\r
+ *\r
+ * \param p_gmac Pointer to the GMAC instance.\r
+ */\r
+static inline uint32_t gmac_get_rx_status(Gmac* p_gmac)\r
+{\r
+ return p_gmac->GMAC_RSR;\r
+}\r
+\r
+/**\r
+ * \brief Clear receive status.\r
+ *\r
+ * \param p_gmac Pointer to the GMAC instance.\r
+ * \param ul_status Receive status.\r
+ */\r
+static inline void gmac_clear_rx_status(Gmac* p_gmac, uint32_t ul_status)\r
+{\r
+ p_gmac->GMAC_RSR = ul_status;\r
+}\r
+\r
+/**\r
+ * \brief Set Rx Queue.\r
+ *\r
+ * \param p_gmac Pointer to the GMAC instance.\r
+ * \param ul_addr Rx queue address.\r
+ */\r
+static inline void gmac_set_rx_queue(Gmac* p_gmac, uint32_t ul_addr)\r
+{\r
+ p_gmac->GMAC_RBQB = GMAC_RBQB_ADDR_Msk & ul_addr;\r
+}\r
+\r
+/**\r
+ * \brief Get Rx Queue Address.\r
+ *\r
+ * \param p_gmac Pointer to the GMAC instance.\r
+ *\r
+ * \return Rx queue address.\r
+ */\r
+static inline uint32_t gmac_get_rx_queue(Gmac* p_gmac)\r
+{\r
+ return p_gmac->GMAC_RBQB;\r
+}\r
+\r
+/**\r
+ * \brief Set Tx Queue.\r
+ *\r
+ * \param p_gmac Pointer to the GMAC instance.\r
+ * \param ul_addr Tx queue address.\r
+ */\r
+static inline void gmac_set_tx_queue(Gmac* p_gmac, uint32_t ul_addr)\r
+{\r
+ p_gmac->GMAC_TBQB = GMAC_TBQB_ADDR_Msk & ul_addr;\r
+}\r
+\r
+/**\r
+ * \brief Get Tx Queue.\r
+ *\r
+ * \param p_gmac Pointer to the GMAC instance.\r
+ *\r
+ * \return Rx queue address.\r
+ */\r
+static inline uint32_t gmac_get_tx_queue(Gmac* p_gmac)\r
+{\r
+ return p_gmac->GMAC_TBQB;\r
+}\r
+\r
+/**\r
+ * \brief Enable interrupt(s).\r
+ *\r
+ * \param p_gmac Pointer to the GMAC instance.\r
+ * \param ul_source Interrupt source(s) to be enabled.\r
+ */\r
+static inline void gmac_enable_interrupt(Gmac* p_gmac, uint32_t ul_source)\r
+{\r
+ p_gmac->GMAC_IER = ul_source;\r
+}\r
+\r
+/**\r
+ * \brief Disable interrupt(s).\r
+ *\r
+ * \param p_gmac Pointer to the GMAC instance.\r
+ * \param ul_source Interrupt source(s) to be disabled.\r
+ */\r
+static inline void gmac_disable_interrupt(Gmac* p_gmac, uint32_t ul_source)\r
+{\r
+ p_gmac->GMAC_IDR = ul_source;\r
+}\r
+\r
+/**\r
+ * \brief Return interrupt status.\r
+ *\r
+ * \param p_gmac Pointer to the GMAC instance.\r
+ *\r
+ * \return Interrupt status.\r
+ */\r
+static inline uint32_t gmac_get_interrupt_status(Gmac* p_gmac)\r
+{\r
+ return p_gmac->GMAC_ISR;\r
+}\r
+\r
+/**\r
+ * \brief Return interrupt mask.\r
+ *\r
+ * \param p_gmac Pointer to the GMAC instance.\r
+ *\r
+ * \return Interrupt mask.\r
+ */\r
+static inline uint32_t gmac_get_interrupt_mask(Gmac* p_gmac)\r
+{\r
+ return p_gmac->GMAC_IMR;\r
+}\r
+\r
+/**\r
+ * \brief Execute PHY maintenance command.\r
+ *\r
+ * \param p_gmac Pointer to the GMAC instance.\r
+ * \param uc_phy_addr PHY address.\r
+ * \param uc_reg_addr Register address.\r
+ * \param uc_rw 1 to Read, 0 to write.\r
+ * \param us_data Data to be performed, write only.\r
+ */\r
+static inline void gmac_maintain_phy(Gmac* p_gmac,\r
+ uint8_t uc_phy_addr, uint8_t uc_reg_addr, uint8_t uc_rw,\r
+ uint16_t us_data)\r
+{\r
+ /* Wait until bus idle */\r
+ while ((p_gmac->GMAC_NSR & GMAC_NSR_IDLE) == 0);\r
+ /* Write maintain register */\r
+ p_gmac->GMAC_MAN = GMAC_MAN_WTN(GMAC_MAN_CODE_VALUE)\r
+ | GMAC_MAN_CLTTO \r
+ | GMAC_MAN_PHYA(uc_phy_addr)\r
+ | GMAC_MAN_REGA(uc_reg_addr)\r
+ | GMAC_MAN_OP((uc_rw ? GMAC_MAN_RW_TYPE : GMAC_MAN_READ_ONLY))\r
+ | GMAC_MAN_DATA(us_data);\r
+}\r
+\r
+/**\r
+ * \brief Get PHY maintenance data returned.\r
+ *\r
+ * \param p_gmac Pointer to the GMAC instance.\r
+ *\r
+ * \return Get PHY data.\r
+ */\r
+static inline uint16_t gmac_get_phy_data(Gmac* p_gmac)\r
+{\r
+ /* Wait until bus idle */\r
+ while ((p_gmac->GMAC_NSR & GMAC_NSR_IDLE) == 0);\r
+ /* Return data */\r
+ return (uint16_t) (p_gmac->GMAC_MAN & GMAC_MAN_DATA_Msk);\r
+}\r
+\r
+/**\r
+ * \brief Set Hash.\r
+ *\r
+ * \param p_gmac Pointer to the GMAC instance.\r
+ * \param ul_hash_top Hash top.\r
+ * \param ul_hash_bottom Hash bottom.\r
+ */\r
+static inline void gmac_set_hash(Gmac* p_gmac, uint32_t ul_hash_top,\r
+ uint32_t ul_hash_bottom)\r
+{\r
+ p_gmac->GMAC_HRB = ul_hash_bottom;\r
+ p_gmac->GMAC_HRT = ul_hash_top;\r
+}\r
+\r
+/**\r
+ * \brief Set 64 bits Hash.\r
+ *\r
+ * \param p_gmac Pointer to the GMAC instance.\r
+ * \param ull_hash 64 bits hash value.\r
+ */\r
+static inline void gmac_set_hash64(Gmac* p_gmac, uint64_t ull_hash)\r
+{\r
+ p_gmac->GMAC_HRB = (uint32_t) ull_hash;\r
+ p_gmac->GMAC_HRT = (uint32_t) (ull_hash >> 32);\r
+}\r
+\r
+/**\r
+ * \brief Set MAC Address.\r
+ *\r
+ * \param p_gmac Pointer to the GMAC instance.\r
+ * \param uc_index GMAC specific address register index.\r
+ * \param p_mac_addr GMAC address.\r
+ */\r
+static inline void gmac_set_address(Gmac* p_gmac, uint8_t uc_index,\r
+ uint8_t* p_mac_addr)\r
+{\r
+ p_gmac->GMAC_SA[uc_index].GMAC_SAB = (p_mac_addr[3] << 24)\r
+ | (p_mac_addr[2] << 16)\r
+ | (p_mac_addr[1] << 8)\r
+ | (p_mac_addr[0]);\r
+ p_gmac->GMAC_SA[uc_index].GMAC_SAT = (p_mac_addr[5] << 8)\r
+ | (p_mac_addr[4]);\r
+}\r
+\r
+/**\r
+ * \brief Set MAC Address via 2 dword.\r
+ *\r
+ * \param p_gmac Pointer to the GMAC instance.\r
+ * \param uc_index GMAC specific address register index.\r
+ * \param ul_mac_top GMAC top address.\r
+ * \param ul_mac_bottom GMAC bottom address.\r
+ */\r
+static inline void gmac_set_address32(Gmac* p_gmac, uint8_t uc_index,\r
+ uint32_t ul_mac_top, uint32_t ul_mac_bottom)\r
+{\r
+ p_gmac->GMAC_SA[uc_index].GMAC_SAB = ul_mac_bottom;\r
+ p_gmac->GMAC_SA[uc_index].GMAC_SAT = ul_mac_top;\r
+}\r
+\r
+/**\r
+ * \brief Set MAC Address via int64.\r
+ *\r
+ * \param p_gmac Pointer to the GMAC instance.\r
+ * \param uc_index GMAC specific address register index.\r
+ * \param ull_mac 64-bit GMAC address.\r
+ */\r
+static inline void gmac_set_address64(Gmac* p_gmac, uint8_t uc_index,\r
+ uint64_t ull_mac)\r
+{\r
+ p_gmac->GMAC_SA[uc_index].GMAC_SAB = (uint32_t) ull_mac;\r
+ p_gmac->GMAC_SA[uc_index].GMAC_SAT = (uint32_t) (ull_mac >> 32);\r
+}\r
+\r
+/**\r
+ * \brief Select media independent interface mode.\r
+ *\r
+ * \param p_gmac Pointer to the GMAC instance.\r
+ * \param mode Media independent interface mode.\r
+ */\r
+static inline void gmac_select_mii_mode(Gmac* p_gmac, gmac_mii_mode_t mode)\r
+{\r
+ switch (mode) {\r
+ case GMAC_PHY_MII:\r
+ case GMAC_PHY_RMII:\r
+ p_gmac->GMAC_UR |= GMAC_UR_RMIIMII;\r
+ break;\r
+\r
+ default:\r
+ p_gmac->GMAC_UR &= ~GMAC_UR_RMIIMII;\r
+ break;\r
+ }\r
+}\r
+\r
+uint8_t gmac_phy_read(Gmac* p_gmac, uint8_t uc_phy_address, uint8_t uc_address,\r
+ uint32_t* p_value);\r
+uint8_t gmac_phy_write(Gmac* p_gmac, uint8_t uc_phy_address,\r
+ uint8_t uc_address, uint32_t ul_value);\r
+void gmac_dev_init(Gmac* p_gmac, gmac_device_t* p_gmac_dev,\r
+ gmac_options_t* p_opt);\r
+uint32_t gmac_dev_read(gmac_device_t* p_gmac_dev, uint8_t* p_frame,\r
+ uint32_t ul_frame_size, uint32_t* p_rcv_size);\r
+uint32_t gmac_dev_write(gmac_device_t* p_gmac_dev, void *p_buffer,\r
+ uint32_t ul_size, gmac_dev_tx_cb_t func_tx_cb);\r
+uint32_t gmac_dev_get_tx_load(gmac_device_t* p_gmac_dev);\r
+void gmac_dev_set_rx_callback(gmac_device_t* p_gmac_dev,\r
+ gmac_dev_tx_cb_t func_rx_cb);\r
+uint8_t gmac_dev_set_tx_wakeup_callback(gmac_device_t* p_gmac_dev,\r
+ gmac_dev_wakeup_cb_t func_wakeup, uint8_t uc_threshold);\r
+void gmac_dev_reset(gmac_device_t* p_gmac_dev);\r
+void gmac_handler(gmac_device_t* p_gmac_dev);\r
+\r
+/// @cond 0\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+/**INDENT-ON**/\r
+/// @endcond\r
+\r
+/**\r
+ * \page gmac_quickstart Quickstart guide for GMAC driver.\r
+ *\r
+ * This is the quickstart guide for the \ref gmac_group "Ethernet MAC",\r
+ * with step-by-step instructions on how to configure and use the driver in a\r
+ * selection of use cases.\r
+ *\r
+ * The use cases contain several code fragments. The code fragments in the\r
+ * steps for setup can be copied into a custom initialization function, while\r
+ * the steps for usage can be copied into, e.g., the main application function.\r
+ *\r
+ * \section gmac_basic_use_case Basic use case\r
+ * In the basic use case, the GMAC driver are configured for:\r
+ * - PHY component KSZ8051MNL is used\r
+ * - GMAC uses MII mode\r
+ * - The number of receive buffer is 16\r
+ * - The number of transfer buffer is 8\r
+ * - MAC address is set to 00-04-25-1c-a0-02\r
+ * - IP address is set to 192.168.0.2\r
+ * - IP address is set to 192.168.0.2\r
+ * - Gateway is set to 192.168.0.1\r
+ * - Network mask is 255.255.255.0\r
+ * - PHY operation max retry count is 1000000\r
+ * - GMAC is configured to not support copy all frame and support broadcast\r
+ * - The data will be read from the ethernet\r
+ *\r
+ * \section gmac_basic_use_case_setup Setup steps\r
+ *\r
+ * \subsection gmac_basic_use_case_setup_prereq Prerequisites\r
+ * -# \ref sysclk_group "System Clock Management (sysclock)"\r
+ * -# \ref pmc_group "Power Management Controller (pmc)"\r
+ * -# \ref ksz8051mnl_ethernet_phy_group "PHY component (KSZ8051MNL)"\r
+ *\r
+ * \subsection gmac_basic_use_case_setup_code Example code\r
+ * Content of conf_eth.h\r
+ * \code\r
+ * #define GMAC_RX_BUFFERS 16\r
+ * #define GMAC_TX_BUFFERS 8\r
+ * #define MAC_PHY_RETRY_MAX 1000000\r
+ * #define ETHERNET_CONF_ETHADDR0 0x00\r
+ * #define ETHERNET_CONF_ETHADDR0 0x00\r
+ * #define ETHERNET_CONF_ETHADDR1 0x04\r
+ * #define ETHERNET_CONF_ETHADDR2 0x25\r
+ * #define ETHERNET_CONF_ETHADDR3 0x1C\r
+ * #define ETHERNET_CONF_ETHADDR4 0xA0\r
+ * #define ETHERNET_CONF_ETHADDR5 0x02\r
+ * #define ETHERNET_CONF_IPADDR0 192\r
+ * #define ETHERNET_CONF_IPADDR1 168\r
+ * #define ETHERNET_CONF_IPADDR2 0\r
+ * #define ETHERNET_CONF_IPADDR3 2\r
+ * #define ETHERNET_CONF_GATEWAY_ADDR0 192\r
+ * #define ETHERNET_CONF_GATEWAY_ADDR1 168\r
+ * #define ETHERNET_CONF_GATEWAY_ADDR2 0\r
+ * #define ETHERNET_CONF_GATEWAY_ADDR3 1\r
+ * #define ETHERNET_CONF_NET_MASK0 255\r
+ * #define ETHERNET_CONF_NET_MASK1 255\r
+ * #define ETHERNET_CONF_NET_MASK2 255\r
+ * #define ETHERNET_CONF_NET_MASK3 0\r
+ * #define ETH_PHY_MODE ETH_PHY_MODE\r
+ * \endcode\r
+ *\r
+ * A specific gmac device and the receive data buffer must be defined; another ul_frm_size should be defined\r
+ * to trace the actual size of the data received.\r
+ * \code\r
+ * static gmac_device_t gs_gmac_dev;\r
+ * static volatile uint8_t gs_uc_eth_buffer[GMAC_FRAME_LENTGH_MAX];\r
+ *\r
+ * uint32_t ul_frm_size;\r
+ * \endcode\r
+ *\r
+ * Add to application C-file:\r
+ * \code\r
+ * void gmac_init(void)\r
+ * {\r
+ * sysclk_init();\r
+ *\r
+ * board_init();\r
+ *\r
+ * pmc_enable_periph_clk(ID_GMAC);\r
+ *\r
+ * gmac_option.uc_copy_all_frame = 0;\r
+ * gmac_option.uc_no_boardcast = 0;\r
+ * memcpy(gmac_option.uc_mac_addr, gs_uc_mac_address, sizeof(gs_uc_mac_address));\r
+ * gs_gmac_dev.p_hw = GMAC;\r
+ *\r
+ * gmac_dev_init(GMAC, &gs_gmac_dev, &gmac_option);\r
+ *\r
+ * NVIC_EnableIRQ(GMAC_IRQn);\r
+ *\r
+ * ethernet_phy_init(GMAC, BOARD_GMAC_PHY_ADDR, sysclk_get_cpu_hz());\r
+ * \r
+ * ethernet_phy_auto_negotiate(GMAC, BOARD_GMAC_PHY_ADDR);\r
+ *\r
+ * ethernet_phy_set_link(GMAC, BOARD_GMAC_PHY_ADDR, 1);\r
+ * \endcode\r
+ *\r
+ * \subsection gmac_basic_use_case_setup_flow Workflow\r
+ * -# Ensure that conf_eth.h is present and contains the\r
+ * following configuration symbol. This configuration file is used\r
+ * by the driver and should not be included by the user.\r
+ * - \code\r
+ * #define GMAC_RX_BUFFERS 16\r
+ * #define GMAC_TX_BUFFERS 8\r
+ * #define MAC_PHY_RETRY_MAX 1000000\r
+ * #define ETHERNET_CONF_ETHADDR0 0x00\r
+ * #define ETHERNET_CONF_ETHADDR0 0x00\r
+ * #define ETHERNET_CONF_ETHADDR1 0x04\r
+ * #define ETHERNET_CONF_ETHADDR2 0x25\r
+ * #define ETHERNET_CONF_ETHADDR3 0x1C\r
+ * #define ETHERNET_CONF_ETHADDR4 0xA0\r
+ * #define ETHERNET_CONF_ETHADDR5 0x02\r
+ * #define ETHERNET_CONF_IPADDR0 192\r
+ * #define ETHERNET_CONF_IPADDR1 168\r
+ * #define ETHERNET_CONF_IPADDR2 0\r
+ * #define ETHERNET_CONF_IPADDR3 2\r
+ * #define ETHERNET_CONF_GATEWAY_ADDR0 192\r
+ * #define ETHERNET_CONF_GATEWAY_ADDR1 168\r
+ * #define ETHERNET_CONF_GATEWAY_ADDR2 0\r
+ * #define ETHERNET_CONF_GATEWAY_ADDR3 1\r
+ * #define ETHERNET_CONF_NET_MASK0 255\r
+ * #define ETHERNET_CONF_NET_MASK1 255\r
+ * #define ETHERNET_CONF_NET_MASK2 255\r
+ * #define ETHERNET_CONF_NET_MASK3 0\r
+ * #define ETH_PHY_MODE GMAC_PHY_MII\r
+ * \endcode\r
+ * -# Enable the system clock:\r
+ * - \code sysclk_init(); \endcode\r
+ * -# Enable PIO configurations for GMAC:\r
+ * - \code board_init(); \endcode\r
+ * -# Enable PMC clock for GMAC:\r
+ * - \code pmc_enable_periph_clk(ID_GMAC); \endcode\r
+ * -# Set the GMAC options; it's set to copy all frame and support broadcast:\r
+ * - \code\r
+ * gmac_option.uc_copy_all_frame = 0;\r
+ * gmac_option.uc_no_boardcast = 0;\r
+ * memcpy(gmac_option.uc_mac_addr, gs_uc_mac_address, sizeof(gs_uc_mac_address));\r
+ * gs_gmac_dev.p_hw = GMAC;\r
+ * \endcode\r
+ * -# Initialize GMAC device with the filled option:\r
+ * - \code\r
+ * gmac_dev_init(GMAC, &gs_gmac_dev, &gmac_option);\r
+ * \endcode\r
+ * -# Enable the interrupt service for GMAC:\r
+ * - \code\r
+ * NVIC_EnableIRQ(GMAC_IRQn);\r
+ * \endcode\r
+ * -# Initialize the PHY component:\r
+ * - \code\r
+ * ethernet_phy_init(GMAC, BOARD_GMAC_PHY_ADDR, sysclk_get_cpu_hz());\r
+ * \endcode\r
+ * -# The link will be established based on auto negotiation.\r
+ * - \code\r
+ * ethernet_phy_auto_negotiate(GMAC, BOARD_GMAC_PHY_ADDR);\r
+ * \endcode\r
+ * -# Establish the ethernet link; the network can be worked from now on:\r
+ * - \code\r
+ * ethernet_phy_set_link(GMAC, BOARD_GMAC_PHY_ADDR, 1);\r
+ * \endcode\r
+ *\r
+ * \section gmac_basic_use_case_usage Usage steps\r
+ * \subsection gmac_basic_use_case_usage_code Example code\r
+ * Add to, e.g., main loop in application C-file:\r
+ * \code\r
+ * gmac_dev_read(&gs_gmac_dev, (uint8_t *) gs_uc_eth_buffer, sizeof(gs_uc_eth_buffer), &ul_frm_size));\r
+ * \endcode\r
+ *\r
+ * \subsection gmac_basic_use_case_usage_flow Workflow\r
+ * -# Start reading the data from the ethernet:\r
+ * - \code gmac_dev_read(&gs_gmac_dev, (uint8_t *) gs_uc_eth_buffer, sizeof(gs_uc_eth_buffer), &ul_frm_size)); \endcode\r
+ */\r
+\r
+#endif /* GMAC_H_INCLUDED */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Power Management Controller (PMC) driver for SAM.\r
+ *\r
+ * Copyright (c) 2011 - 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#include "pmc.h"\r
+\r
+#if (SAM3N)\r
+# define MAX_PERIPH_ID 31\r
+#elif (SAM3XA)\r
+# define MAX_PERIPH_ID 44\r
+#elif (SAM3U)\r
+# define MAX_PERIPH_ID 29\r
+#elif (SAM3S || SAM4S)\r
+# define MAX_PERIPH_ID 34\r
+#elif (SAM4E)\r
+# define MAX_PERIPH_ID 47\r
+#elif (SAM4N)\r
+# define MAX_PERIPH_ID 31\r
+#endif\r
+\r
+/// @cond 0\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+/**INDENT-ON**/\r
+/// @endcond\r
+\r
+/**\r
+ * \defgroup sam_drivers_pmc_group Power Management Controller (PMC)\r
+ *\r
+ * \par Purpose\r
+ *\r
+ * The Power Management Controller (PMC) optimizes power consumption by\r
+ * controlling all system and user peripheral clocks. The PMC enables/disables\r
+ * the clock inputs to many of the peripherals and the Cortex-M Processor.\r
+ *\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \brief Set the prescaler of the MCK.\r
+ *\r
+ * \param ul_pres Prescaler value.\r
+ */\r
+void pmc_mck_set_prescaler(uint32_t ul_pres)\r
+{\r
+ PMC->PMC_MCKR =\r
+ (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | ul_pres;\r
+ while (!(PMC->PMC_SR & PMC_SR_MCKRDY));\r
+}\r
+\r
+/**\r
+ * \brief Set the source of the MCK.\r
+ *\r
+ * \param ul_source Source selection value.\r
+ */\r
+void pmc_mck_set_source(uint32_t ul_source)\r
+{\r
+ PMC->PMC_MCKR =\r
+ (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) | ul_source;\r
+ while (!(PMC->PMC_SR & PMC_SR_MCKRDY));\r
+}\r
+\r
+/**\r
+ * \brief Switch master clock source selection to slow clock.\r
+ *\r
+ * \param ul_pres Processor clock prescaler.\r
+ *\r
+ * \retval 0 Success.\r
+ * \retval 1 Timeout error.\r
+ */\r
+uint32_t pmc_switch_mck_to_sclk(uint32_t ul_pres)\r
+{\r
+ uint32_t ul_timeout;\r
+\r
+ PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) |\r
+ PMC_MCKR_CSS_SLOW_CLK;\r
+ for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY);\r
+ --ul_timeout) {\r
+ if (ul_timeout == 0) {\r
+ return 1;\r
+ }\r
+ }\r
+\r
+ PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | ul_pres;\r
+ for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY);\r
+ --ul_timeout) {\r
+ if (ul_timeout == 0) {\r
+ return 1;\r
+ }\r
+ }\r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * \brief Switch master clock source selection to main clock.\r
+ *\r
+ * \param ul_pres Processor clock prescaler.\r
+ *\r
+ * \retval 0 Success.\r
+ * \retval 1 Timeout error.\r
+ */\r
+uint32_t pmc_switch_mck_to_mainck(uint32_t ul_pres)\r
+{\r
+ uint32_t ul_timeout;\r
+\r
+ PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) |\r
+ PMC_MCKR_CSS_MAIN_CLK;\r
+ for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY);\r
+ --ul_timeout) {\r
+ if (ul_timeout == 0) {\r
+ return 1;\r
+ }\r
+ }\r
+\r
+ PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | ul_pres;\r
+ for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY);\r
+ --ul_timeout) {\r
+ if (ul_timeout == 0) {\r
+ return 1;\r
+ }\r
+ }\r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * \brief Switch master clock source selection to PLLA clock.\r
+ *\r
+ * \param ul_pres Processor clock prescaler.\r
+ *\r
+ * \retval 0 Success.\r
+ * \retval 1 Timeout error.\r
+ */\r
+uint32_t pmc_switch_mck_to_pllack(uint32_t ul_pres)\r
+{\r
+ uint32_t ul_timeout;\r
+\r
+ PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | ul_pres;\r
+ for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY);\r
+ --ul_timeout) {\r
+ if (ul_timeout == 0) {\r
+ return 1;\r
+ }\r
+ }\r
+\r
+ PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) |\r
+ PMC_MCKR_CSS_PLLA_CLK;\r
+\r
+ for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY);\r
+ --ul_timeout) {\r
+ if (ul_timeout == 0) {\r
+ return 1;\r
+ }\r
+ }\r
+\r
+ return 0;\r
+}\r
+\r
+#if (SAM3S || SAM4S)\r
+/**\r
+ * \brief Switch master clock source selection to PLLB clock.\r
+ *\r
+ * \param ul_pres Processor clock prescaler.\r
+ *\r
+ * \retval 0 Success.\r
+ * \retval 1 Timeout error.\r
+ */\r
+uint32_t pmc_switch_mck_to_pllbck(uint32_t ul_pres)\r
+{\r
+ uint32_t ul_timeout;\r
+\r
+ PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | ul_pres;\r
+ for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY);\r
+ --ul_timeout) {\r
+ if (ul_timeout == 0) {\r
+ return 1;\r
+ }\r
+ }\r
+\r
+ PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) |\r
+ PMC_MCKR_CSS_PLLB_CLK;\r
+ for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY);\r
+ --ul_timeout) {\r
+ if (ul_timeout == 0) {\r
+ return 1;\r
+ }\r
+ }\r
+\r
+ return 0;\r
+}\r
+#endif\r
+\r
+#if (SAM3XA || SAM3U)\r
+/**\r
+ * \brief Switch master clock source selection to UPLL clock.\r
+ *\r
+ * \param ul_pres Processor clock prescaler.\r
+ *\r
+ * \retval 0 Success.\r
+ * \retval 1 Timeout error.\r
+ */\r
+uint32_t pmc_switch_mck_to_upllck(uint32_t ul_pres)\r
+{\r
+ uint32_t ul_timeout;\r
+\r
+ PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | ul_pres;\r
+ for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY);\r
+ --ul_timeout) {\r
+ if (ul_timeout == 0) {\r
+ return 1;\r
+ }\r
+ }\r
+\r
+ PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) |\r
+ PMC_MCKR_CSS_UPLL_CLK;\r
+ for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY);\r
+ --ul_timeout) {\r
+ if (ul_timeout == 0) {\r
+ return 1;\r
+ }\r
+ }\r
+\r
+ return 0;\r
+}\r
+#endif\r
+\r
+/**\r
+ * \brief Switch slow clock source selection to external 32k (Xtal or Bypass).\r
+ *\r
+ * \note This function disables the PLLs.\r
+ *\r
+ * \note Switching SCLK back to 32krc is only possible by shutting down the\r
+ * VDDIO power supply.\r
+ *\r
+ * \param ul_bypass 0 for Xtal, 1 for bypass.\r
+ */\r
+void pmc_switch_sclk_to_32kxtal(uint32_t ul_bypass)\r
+{\r
+ /* Set Bypass mode if required */\r
+ if (ul_bypass == 1) {\r
+ SUPC->SUPC_MR |= SUPC_MR_KEY(SUPC_KEY_VALUE) |\r
+ SUPC_MR_OSCBYPASS;\r
+ }\r
+\r
+ SUPC->SUPC_CR = SUPC_CR_KEY(SUPC_KEY_VALUE) | SUPC_CR_XTALSEL;\r
+}\r
+\r
+/**\r
+ * \brief Check if the external 32k Xtal is ready.\r
+ *\r
+ * \retval 1 External 32k Xtal is ready.\r
+ * \retval 0 External 32k Xtal is not ready.\r
+ */\r
+uint32_t pmc_osc_is_ready_32kxtal(void)\r
+{\r
+ return ((SUPC->SUPC_SR & SUPC_SR_OSCSEL)\r
+ && (PMC->PMC_SR & PMC_SR_OSCSELS));\r
+}\r
+\r
+/**\r
+ * \brief Switch main clock source selection to internal fast RC.\r
+ *\r
+ * \param ul_moscrcf Fast RC oscillator(4/8/12Mhz).\r
+ *\r
+ * \retval 0 Success.\r
+ * \retval 1 Timeout error.\r
+ * \retval 2 Invalid frequency.\r
+ */\r
+void pmc_switch_mainck_to_fastrc(uint32_t ul_moscrcf)\r
+{\r
+ uint32_t ul_needXTEN = 0;\r
+\r
+ /* Enable Fast RC oscillator but DO NOT switch to RC now */\r
+ if (PMC->CKGR_MOR & CKGR_MOR_MOSCXTEN) {\r
+ PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCRCF_Msk) |\r
+ PMC_CKGR_MOR_KEY_VALUE | CKGR_MOR_MOSCRCEN |\r
+ ul_moscrcf;\r
+ } else {\r
+ ul_needXTEN = 1;\r
+ PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCRCF_Msk) |\r
+ PMC_CKGR_MOR_KEY_VALUE | CKGR_MOR_MOSCRCEN |\r
+ CKGR_MOR_MOSCXTEN | CKGR_MOR_MOSCXTST_Msk |\r
+ ul_moscrcf;\r
+ }\r
+\r
+ /* Wait the Fast RC to stabilize */\r
+ while (!(PMC->PMC_SR & PMC_SR_MOSCRCS));\r
+\r
+ /* Switch to Fast RC */\r
+ PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCSEL) |\r
+ PMC_CKGR_MOR_KEY_VALUE;\r
+\r
+ /* Disable xtal oscillator */\r
+ if (ul_needXTEN) {\r
+ PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTEN) |\r
+ PMC_CKGR_MOR_KEY_VALUE;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Enable fast RC oscillator.\r
+ *\r
+ * \param ul_rc Fast RC oscillator(4/8/12Mhz).\r
+ */\r
+void pmc_osc_enable_fastrc(uint32_t ul_rc)\r
+{\r
+ /* Enable Fast RC oscillator but DO NOT switch to RC now.\r
+ * Keep MOSCSEL to 1 */\r
+ PMC->CKGR_MOR = PMC_CKGR_MOR_KEY_VALUE | CKGR_MOR_MOSCSEL |\r
+ CKGR_MOR_MOSCXTEN | CKGR_MOR_MOSCRCEN | ul_rc;\r
+ /* Wait the Fast RC to stabilize */\r
+ while (!(PMC->PMC_SR & PMC_SR_MOSCRCS));\r
+}\r
+\r
+/**\r
+ * \brief Disable the internal fast RC.\r
+ */\r
+void pmc_osc_disable_fastrc(void)\r
+{\r
+ /* Disable Fast RC oscillator */\r
+ PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCRCEN &\r
+ ~CKGR_MOR_MOSCRCF_Msk)\r
+ | PMC_CKGR_MOR_KEY_VALUE;\r
+}\r
+\r
+/**\r
+ * \brief Check if the main fastrc is ready.\r
+ *\r
+ * \retval 0 Xtal is not ready, otherwise ready.\r
+ */\r
+uint32_t pmc_osc_is_ready_fastrc(void)\r
+{\r
+ return (PMC->PMC_SR & PMC_SR_MOSCRCS);\r
+}\r
+\r
+/**\r
+ * \brief Enable main XTAL oscillator.\r
+ *\r
+ * \param ul_xtal_startup_time Xtal start-up time, in number of slow clocks.\r
+ */\r
+void pmc_osc_enable_main_xtal(uint32_t ul_xtal_startup_time)\r
+{\r
+ uint32_t mor = PMC->CKGR_MOR;\r
+ mor &= ~(CKGR_MOR_MOSCXTBY|CKGR_MOR_MOSCXTEN);\r
+ mor |= PMC_CKGR_MOR_KEY_VALUE | CKGR_MOR_MOSCXTEN |\r
+ CKGR_MOR_MOSCXTST(ul_xtal_startup_time);\r
+ PMC->CKGR_MOR = mor;\r
+ /* Wait the main Xtal to stabilize */\r
+ while (!(PMC->PMC_SR & PMC_SR_MOSCXTS));\r
+}\r
+\r
+/**\r
+ * \brief Bypass main XTAL.\r
+ */\r
+void pmc_osc_bypass_main_xtal(void)\r
+{\r
+ uint32_t mor = PMC->CKGR_MOR;\r
+ mor &= ~(CKGR_MOR_MOSCXTBY|CKGR_MOR_MOSCXTEN);\r
+ mor |= PMC_CKGR_MOR_KEY_VALUE | CKGR_MOR_MOSCXTBY;\r
+ /* Enable Crystal oscillator but DO NOT switch now. Keep MOSCSEL to 0 */\r
+ PMC->CKGR_MOR = mor;\r
+ /* The MOSCXTS in PMC_SR is automatically set */\r
+}\r
+\r
+/**\r
+ * \brief Disable the main Xtal.\r
+ */\r
+void pmc_osc_disable_main_xtal(void)\r
+{\r
+ uint32_t mor = PMC->CKGR_MOR;\r
+ mor &= ~(CKGR_MOR_MOSCXTBY|CKGR_MOR_MOSCXTEN);\r
+ PMC->CKGR_MOR = PMC_CKGR_MOR_KEY_VALUE | mor;\r
+}\r
+\r
+/**\r
+ * \brief Check if the main crystal is bypassed.\r
+ *\r
+ * \retval 0 Xtal is bypassed, otherwise not.\r
+ */\r
+uint32_t pmc_osc_is_bypassed_main_xtal(void)\r
+{\r
+ return (PMC->CKGR_MOR & CKGR_MOR_MOSCXTBY);\r
+}\r
+\r
+/**\r
+ * \brief Check if the main crystal is ready.\r
+ *\r
+ * \note If main crystal is bypassed, it's always ready.\r
+ *\r
+ * \retval 0 main crystal is not ready, otherwise ready.\r
+ */\r
+uint32_t pmc_osc_is_ready_main_xtal(void)\r
+{\r
+ return (PMC->PMC_SR & PMC_SR_MOSCXTS);\r
+}\r
+\r
+/**\r
+ * \brief Switch main clock source selection to external Xtal/Bypass.\r
+ *\r
+ * \note The function may switch MCK to SCLK if MCK source is MAINCK to avoid\r
+ * any system crash.\r
+ *\r
+ * \note If used in Xtal mode, the Xtal is automatically enabled.\r
+ *\r
+ * \param ul_bypass 0 for Xtal, 1 for bypass.\r
+ *\r
+ * \retval 0 Success.\r
+ * \retval 1 Timeout error.\r
+ */\r
+void pmc_switch_mainck_to_xtal(uint32_t ul_bypass,\r
+ uint32_t ul_xtal_startup_time)\r
+{\r
+ /* Enable Main Xtal oscillator */\r
+ if (ul_bypass) {\r
+ PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTEN) |\r
+ PMC_CKGR_MOR_KEY_VALUE | CKGR_MOR_MOSCXTBY |\r
+ CKGR_MOR_MOSCSEL;\r
+ } else {\r
+ PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTBY) |\r
+ PMC_CKGR_MOR_KEY_VALUE | CKGR_MOR_MOSCXTEN |\r
+ CKGR_MOR_MOSCXTST(ul_xtal_startup_time);\r
+ /* Wait the Xtal to stabilize */\r
+ while (!(PMC->PMC_SR & PMC_SR_MOSCXTS));\r
+\r
+ PMC->CKGR_MOR |= PMC_CKGR_MOR_KEY_VALUE | CKGR_MOR_MOSCSEL;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Disable the external Xtal.\r
+ *\r
+ * \param ul_bypass 0 for Xtal, 1 for bypass.\r
+ */\r
+void pmc_osc_disable_xtal(uint32_t ul_bypass)\r
+{\r
+ /* Disable xtal oscillator */\r
+ if (ul_bypass) {\r
+ PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTBY) |\r
+ PMC_CKGR_MOR_KEY_VALUE;\r
+ } else {\r
+ PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTEN) |\r
+ PMC_CKGR_MOR_KEY_VALUE;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Check if the MAINCK is ready. Depending on MOSCEL, MAINCK can be one\r
+ * of Xtal, bypass or internal RC.\r
+ *\r
+ * \retval 1 Xtal is ready.\r
+ * \retval 0 Xtal is not ready.\r
+ */\r
+uint32_t pmc_osc_is_ready_mainck(void)\r
+{\r
+ return PMC->PMC_SR & PMC_SR_MOSCSELS;\r
+}\r
+\r
+/**\r
+ * \brief Select Main Crystal or internal RC as main clock source.\r
+ *\r
+ * \note This function will not enable/disable RC or Main Crystal.\r
+ *\r
+ * \param ul_xtal_rc 0 internal RC is selected, otherwise Main Crystal.\r
+ */\r
+void pmc_mainck_osc_select(uint32_t ul_xtal_rc)\r
+{\r
+ uint32_t mor = PMC->CKGR_MOR;\r
+ if (ul_xtal_rc) {\r
+ mor |= CKGR_MOR_MOSCSEL;\r
+ } else {\r
+ mor &= ~CKGR_MOR_MOSCSEL;\r
+ }\r
+ PMC->CKGR_MOR = PMC_CKGR_MOR_KEY_VALUE | mor;\r
+}\r
+\r
+/**\r
+ * \brief Enable PLLA clock.\r
+ *\r
+ * \param mula PLLA multiplier.\r
+ * \param pllacount PLLA counter.\r
+ * \param diva Divider.\r
+ */\r
+void pmc_enable_pllack(uint32_t mula, uint32_t pllacount, uint32_t diva)\r
+{\r
+ /* first disable the PLL to unlock the lock */\r
+ pmc_disable_pllack();\r
+\r
+ PMC->CKGR_PLLAR = CKGR_PLLAR_ONE | CKGR_PLLAR_DIVA(diva) |\r
+ CKGR_PLLAR_PLLACOUNT(pllacount) | CKGR_PLLAR_MULA(mula);\r
+ while ((PMC->PMC_SR & PMC_SR_LOCKA) == 0);\r
+}\r
+\r
+/**\r
+ * \brief Disable PLLA clock.\r
+ */\r
+void pmc_disable_pllack(void)\r
+{\r
+ PMC->CKGR_PLLAR = CKGR_PLLAR_ONE | CKGR_PLLAR_MULA(0);\r
+}\r
+\r
+/**\r
+ * \brief Is PLLA locked?\r
+ *\r
+ * \retval 0 Not locked.\r
+ * \retval 1 Locked.\r
+ */\r
+uint32_t pmc_is_locked_pllack(void)\r
+{\r
+ return (PMC->PMC_SR & PMC_SR_LOCKA);\r
+}\r
+\r
+#if (SAM3S || SAM4S)\r
+/**\r
+ * \brief Enable PLLB clock.\r
+ *\r
+ * \param mulb PLLB multiplier.\r
+ * \param pllbcount PLLB counter.\r
+ * \param divb Divider.\r
+ */\r
+void pmc_enable_pllbck(uint32_t mulb, uint32_t pllbcount, uint32_t divb)\r
+{\r
+ /* first disable the PLL to unlock the lock */\r
+ pmc_disable_pllbck();\r
+\r
+ PMC->CKGR_PLLBR =\r
+ CKGR_PLLBR_DIVB(divb) | CKGR_PLLBR_PLLBCOUNT(pllbcount)\r
+ | CKGR_PLLBR_MULB(mulb);\r
+ while ((PMC->PMC_SR & PMC_SR_LOCKB) == 0);\r
+}\r
+\r
+/**\r
+ * \brief Disable PLLB clock.\r
+ */\r
+void pmc_disable_pllbck(void)\r
+{\r
+ PMC->CKGR_PLLBR = CKGR_PLLBR_MULB(0);\r
+}\r
+\r
+/**\r
+ * \brief Is PLLB locked?\r
+ *\r
+ * \retval 0 Not locked.\r
+ * \retval 1 Locked.\r
+ */\r
+uint32_t pmc_is_locked_pllbck(void)\r
+{\r
+ return (PMC->PMC_SR & PMC_SR_LOCKB);\r
+}\r
+#endif\r
+\r
+#if (SAM3XA || SAM3U)\r
+/**\r
+ * \brief Enable UPLL clock.\r
+ */\r
+void pmc_enable_upll_clock(void)\r
+{\r
+ PMC->CKGR_UCKR = CKGR_UCKR_UPLLCOUNT(3) | CKGR_UCKR_UPLLEN;\r
+\r
+ /* Wait UTMI PLL Lock Status */\r
+ while (!(PMC->PMC_SR & PMC_SR_LOCKU));\r
+}\r
+\r
+/**\r
+ * \brief Disable UPLL clock.\r
+ */\r
+void pmc_disable_upll_clock(void)\r
+{\r
+ PMC->CKGR_UCKR &= ~CKGR_UCKR_UPLLEN;\r
+}\r
+\r
+/**\r
+ * \brief Is UPLL locked?\r
+ *\r
+ * \retval 0 Not locked.\r
+ * \retval 1 Locked.\r
+ */\r
+uint32_t pmc_is_locked_upll(void)\r
+{\r
+ return (PMC->PMC_SR & PMC_SR_LOCKU);\r
+}\r
+#endif\r
+\r
+/**\r
+ * \brief Enable the specified peripheral clock.\r
+ *\r
+ * \note The ID must NOT be shifted (i.e., 1 << ID_xxx).\r
+ *\r
+ * \param ul_id Peripheral ID (ID_xxx).\r
+ *\r
+ * \retval 0 Success.\r
+ * \retval 1 Invalid parameter.\r
+ */\r
+uint32_t pmc_enable_periph_clk(uint32_t ul_id)\r
+{\r
+ if (ul_id > MAX_PERIPH_ID) {\r
+ return 1;\r
+ }\r
+\r
+ if (ul_id < 32) {\r
+ if ((PMC->PMC_PCSR0 & (1u << ul_id)) != (1u << ul_id)) {\r
+ PMC->PMC_PCER0 = 1 << ul_id;\r
+ }\r
+#if (SAM3S || SAM3XA || SAM4S || SAM4E)\r
+ } else {\r
+ ul_id -= 32;\r
+ if ((PMC->PMC_PCSR1 & (1u << ul_id)) != (1u << ul_id)) {\r
+ PMC->PMC_PCER1 = 1 << ul_id;\r
+ }\r
+#endif\r
+ }\r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * \brief Disable the specified peripheral clock.\r
+ *\r
+ * \note The ID must NOT be shifted (i.e., 1 << ID_xxx).\r
+ *\r
+ * \param ul_id Peripheral ID (ID_xxx).\r
+ *\r
+ * \retval 0 Success.\r
+ * \retval 1 Invalid parameter.\r
+ */\r
+uint32_t pmc_disable_periph_clk(uint32_t ul_id)\r
+{\r
+ if (ul_id > MAX_PERIPH_ID) {\r
+ return 1;\r
+ }\r
+\r
+ if (ul_id < 32) {\r
+ if ((PMC->PMC_PCSR0 & (1u << ul_id)) == (1u << ul_id)) {\r
+ PMC->PMC_PCDR0 = 1 << ul_id;\r
+ }\r
+#if (SAM3S || SAM3XA || SAM4S || SAM4E)\r
+ } else {\r
+ ul_id -= 32;\r
+ if ((PMC->PMC_PCSR1 & (1u << ul_id)) == (1u << ul_id)) {\r
+ PMC->PMC_PCDR1 = 1 << ul_id;\r
+ }\r
+#endif\r
+ }\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * \brief Enable all peripheral clocks.\r
+ */\r
+void pmc_enable_all_periph_clk(void)\r
+{\r
+ PMC->PMC_PCER0 = PMC_MASK_STATUS0;\r
+ while ((PMC->PMC_PCSR0 & PMC_MASK_STATUS0) != PMC_MASK_STATUS0);\r
+\r
+#if (SAM3S || SAM3XA || SAM4S || SAM4E)\r
+ PMC->PMC_PCER1 = PMC_MASK_STATUS1;\r
+ while ((PMC->PMC_PCSR1 & PMC_MASK_STATUS1) != PMC_MASK_STATUS1);\r
+#endif\r
+}\r
+\r
+/**\r
+ * \brief Disable all peripheral clocks.\r
+ */\r
+void pmc_disable_all_periph_clk(void)\r
+{\r
+ PMC->PMC_PCDR0 = PMC_MASK_STATUS0;\r
+ while ((PMC->PMC_PCSR0 & PMC_MASK_STATUS0) != 0);\r
+\r
+#if (SAM3S || SAM3XA || SAM4S || SAM4E)\r
+ PMC->PMC_PCDR1 = PMC_MASK_STATUS1;\r
+ while ((PMC->PMC_PCSR1 & PMC_MASK_STATUS1) != 0);\r
+#endif\r
+}\r
+\r
+/**\r
+ * \brief Check if the specified peripheral clock is enabled.\r
+ *\r
+ * \note The ID must NOT be shifted (i.e., 1 << ID_xxx).\r
+ *\r
+ * \param ul_id Peripheral ID (ID_xxx).\r
+ *\r
+ * \retval 0 Peripheral clock is disabled or unknown.\r
+ * \retval 1 Peripheral clock is enabled.\r
+ */\r
+uint32_t pmc_is_periph_clk_enabled(uint32_t ul_id)\r
+{\r
+ if (ul_id > MAX_PERIPH_ID) {\r
+ return 0;\r
+ }\r
+\r
+#if (SAM3S || SAM3XA || SAM4S || SAM4E)\r
+ if (ul_id < 32) {\r
+#endif\r
+ if ((PMC->PMC_PCSR0 & (1u << ul_id))) {\r
+ return 1;\r
+ } else {\r
+ return 0;\r
+ }\r
+#if (SAM3S || SAM3XA || SAM4S || SAM4E)\r
+ } else {\r
+ ul_id -= 32;\r
+ if ((PMC->PMC_PCSR1 & (1u << ul_id))) {\r
+ return 1;\r
+ } else {\r
+ return 0;\r
+ }\r
+ }\r
+#endif\r
+}\r
+\r
+/**\r
+ * \brief Set the prescaler for the specified programmable clock.\r
+ *\r
+ * \param ul_id Peripheral ID.\r
+ * \param ul_pres Prescaler value.\r
+ */\r
+void pmc_pck_set_prescaler(uint32_t ul_id, uint32_t ul_pres)\r
+{\r
+ PMC->PMC_PCK[ul_id] =\r
+ (PMC->PMC_PCK[ul_id] & ~PMC_PCK_PRES_Msk) | ul_pres;\r
+ while ((PMC->PMC_SCER & (PMC_SCER_PCK0 << ul_id))\r
+ && !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id)));\r
+}\r
+\r
+/**\r
+ * \brief Set the source oscillator for the specified programmable clock.\r
+ *\r
+ * \param ul_id Peripheral ID.\r
+ * \param ul_source Source selection value.\r
+ */\r
+void pmc_pck_set_source(uint32_t ul_id, uint32_t ul_source)\r
+{\r
+ PMC->PMC_PCK[ul_id] =\r
+ (PMC->PMC_PCK[ul_id] & ~PMC_PCK_CSS_Msk) | ul_source;\r
+ while ((PMC->PMC_SCER & (PMC_SCER_PCK0 << ul_id))\r
+ && !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id)));\r
+}\r
+\r
+/**\r
+ * \brief Switch programmable clock source selection to slow clock.\r
+ *\r
+ * \param ul_id Id of the programmable clock.\r
+ * \param ul_pres Programmable clock prescaler.\r
+ *\r
+ * \retval 0 Success.\r
+ * \retval 1 Timeout error.\r
+ */\r
+uint32_t pmc_switch_pck_to_sclk(uint32_t ul_id, uint32_t ul_pres)\r
+{\r
+ uint32_t ul_timeout;\r
+\r
+ PMC->PMC_PCK[ul_id] = PMC_PCK_CSS_SLOW_CLK | ul_pres;\r
+ for (ul_timeout = PMC_TIMEOUT;\r
+ !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id)); --ul_timeout) {\r
+ if (ul_timeout == 0) {\r
+ return 1;\r
+ }\r
+ }\r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * \brief Switch programmable clock source selection to main clock.\r
+ *\r
+ * \param ul_id Id of the programmable clock.\r
+ * \param ul_pres Programmable clock prescaler.\r
+ *\r
+ * \retval 0 Success.\r
+ * \retval 1 Timeout error.\r
+ */\r
+uint32_t pmc_switch_pck_to_mainck(uint32_t ul_id, uint32_t ul_pres)\r
+{\r
+ uint32_t ul_timeout;\r
+\r
+ PMC->PMC_PCK[ul_id] = PMC_PCK_CSS_MAIN_CLK | ul_pres;\r
+ for (ul_timeout = PMC_TIMEOUT;\r
+ !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id)); --ul_timeout) {\r
+ if (ul_timeout == 0) {\r
+ return 1;\r
+ }\r
+ }\r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * \brief Switch programmable clock source selection to PLLA clock.\r
+ *\r
+ * \param ul_id Id of the programmable clock.\r
+ * \param ul_pres Programmable clock prescaler.\r
+ *\r
+ * \retval 0 Success.\r
+ * \retval 1 Timeout error.\r
+ */\r
+uint32_t pmc_switch_pck_to_pllack(uint32_t ul_id, uint32_t ul_pres)\r
+{\r
+ uint32_t ul_timeout;\r
+\r
+ PMC->PMC_PCK[ul_id] = PMC_PCK_CSS_PLLA_CLK | ul_pres;\r
+ for (ul_timeout = PMC_TIMEOUT;\r
+ !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id)); --ul_timeout) {\r
+ if (ul_timeout == 0) {\r
+ return 1;\r
+ }\r
+ }\r
+\r
+ return 0;\r
+}\r
+\r
+#if (SAM3S || SAM4S)\r
+/**\r
+ * \brief Switch programmable clock source selection to PLLB clock.\r
+ *\r
+ * \param ul_id Id of the programmable clock.\r
+ * \param ul_pres Programmable clock prescaler.\r
+ *\r
+ * \retval 0 Success.\r
+ * \retval 1 Timeout error.\r
+ */\r
+uint32_t pmc_switch_pck_to_pllbck(uint32_t ul_id, uint32_t ul_pres)\r
+{\r
+ uint32_t ul_timeout;\r
+\r
+ PMC->PMC_PCK[ul_id] = PMC_PCK_CSS_PLLB_CLK | ul_pres;\r
+ for (ul_timeout = PMC_TIMEOUT;\r
+ !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id));\r
+ --ul_timeout) {\r
+ if (ul_timeout == 0) {\r
+ return 1;\r
+ }\r
+ }\r
+\r
+ return 0;\r
+}\r
+#endif\r
+\r
+#if (SAM3XA || SAM3U)\r
+/**\r
+ * \brief Switch programmable clock source selection to UPLL clock.\r
+ *\r
+ * \param ul_id Id of the programmable clock.\r
+ * \param ul_pres Programmable clock prescaler.\r
+ *\r
+ * \retval 0 Success.\r
+ * \retval 1 Timeout error.\r
+ */\r
+uint32_t pmc_switch_pck_to_upllck(uint32_t ul_id, uint32_t ul_pres)\r
+{\r
+ uint32_t ul_timeout;\r
+\r
+ PMC->PMC_PCK[ul_id] = PMC_PCK_CSS_UPLL_CLK | ul_pres;\r
+ for (ul_timeout = PMC_TIMEOUT;\r
+ !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id));\r
+ --ul_timeout) {\r
+ if (ul_timeout == 0) {\r
+ return 1;\r
+ }\r
+ }\r
+\r
+ return 0;\r
+}\r
+#endif\r
+\r
+/**\r
+ * \brief Enable the specified programmable clock.\r
+ *\r
+ * \param ul_id Id of the programmable clock.\r
+ */\r
+void pmc_enable_pck(uint32_t ul_id)\r
+{\r
+ PMC->PMC_SCER = PMC_SCER_PCK0 << ul_id;\r
+}\r
+\r
+/**\r
+ * \brief Disable the specified programmable clock.\r
+ *\r
+ * \param ul_id Id of the programmable clock.\r
+ */\r
+void pmc_disable_pck(uint32_t ul_id)\r
+{\r
+ PMC->PMC_SCDR = PMC_SCER_PCK0 << ul_id;\r
+}\r
+\r
+/**\r
+ * \brief Enable all programmable clocks.\r
+ */\r
+void pmc_enable_all_pck(void)\r
+{\r
+ PMC->PMC_SCER = PMC_SCER_PCK0 | PMC_SCER_PCK1 | PMC_SCER_PCK2;\r
+}\r
+\r
+/**\r
+ * \brief Disable all programmable clocks.\r
+ */\r
+void pmc_disable_all_pck(void)\r
+{\r
+ PMC->PMC_SCDR = PMC_SCDR_PCK0 | PMC_SCDR_PCK1 | PMC_SCDR_PCK2;\r
+}\r
+\r
+/**\r
+ * \brief Check if the specified programmable clock is enabled.\r
+ *\r
+ * \param ul_id Id of the programmable clock.\r
+ *\r
+ * \retval 0 Programmable clock is disabled or unknown.\r
+ * \retval 1 Programmable clock is enabled.\r
+ */\r
+uint32_t pmc_is_pck_enabled(uint32_t ul_id)\r
+{\r
+ if (ul_id > 2) {\r
+ return 0;\r
+ }\r
+\r
+ return (PMC->PMC_SCSR & (PMC_SCSR_PCK0 << ul_id));\r
+}\r
+\r
+#if (SAM3S || SAM3XA || SAM4S || SAM4E)\r
+/**\r
+ * \brief Switch UDP (USB) clock source selection to PLLA clock.\r
+ *\r
+ * \param ul_usbdiv Clock divisor.\r
+ */\r
+void pmc_switch_udpck_to_pllack(uint32_t ul_usbdiv)\r
+{\r
+ PMC->PMC_USB = PMC_USB_USBDIV(ul_usbdiv);\r
+}\r
+#endif\r
+\r
+#if (SAM3S || SAM4S)\r
+/**\r
+ * \brief Switch UDP (USB) clock source selection to PLLB clock.\r
+ *\r
+ * \param ul_usbdiv Clock divisor.\r
+ */\r
+void pmc_switch_udpck_to_pllbck(uint32_t ul_usbdiv)\r
+{\r
+ PMC->PMC_USB = PMC_USB_USBDIV(ul_usbdiv) | PMC_USB_USBS;\r
+}\r
+#endif\r
+\r
+#if (SAM3XA)\r
+/**\r
+ * \brief Switch UDP (USB) clock source selection to UPLL clock.\r
+ *\r
+ * \param dw_usbdiv Clock divisor.\r
+ */\r
+void pmc_switch_udpck_to_upllck(uint32_t ul_usbdiv)\r
+{\r
+ PMC->PMC_USB = PMC_USB_USBS | PMC_USB_USBDIV(ul_usbdiv);\r
+}\r
+#endif\r
+\r
+#if (SAM3S || SAM3XA || SAM4S || SAM4E)\r
+/**\r
+ * \brief Enable UDP (USB) clock.\r
+ */\r
+void pmc_enable_udpck(void)\r
+{\r
+# if (SAM3S || SAM4S || SAM4E)\r
+ PMC->PMC_SCER = PMC_SCER_UDP;\r
+# else\r
+ PMC->PMC_SCER = PMC_SCER_UOTGCLK;\r
+# endif\r
+}\r
+\r
+/**\r
+ * \brief Disable UDP (USB) clock.\r
+ */\r
+void pmc_disable_udpck(void)\r
+{\r
+# if (SAM3S || SAM4S || SAM4E)\r
+ PMC->PMC_SCDR = PMC_SCDR_UDP;\r
+# else\r
+ PMC->PMC_SCDR = PMC_SCDR_UOTGCLK;\r
+# endif\r
+}\r
+#endif\r
+\r
+/**\r
+ * \brief Enable PMC interrupts.\r
+ *\r
+ * \param ul_sources Interrupt sources bit map.\r
+ */\r
+void pmc_enable_interrupt(uint32_t ul_sources)\r
+{\r
+ PMC->PMC_IER = ul_sources;\r
+}\r
+\r
+/**\r
+ * \brief Disable PMC interrupts.\r
+ *\r
+ * \param ul_sources Interrupt sources bit map.\r
+ */\r
+void pmc_disable_interrupt(uint32_t ul_sources)\r
+{\r
+ PMC->PMC_IDR = ul_sources;\r
+}\r
+\r
+/**\r
+ * \brief Get PMC interrupt mask.\r
+ *\r
+ * \return The interrupt mask value.\r
+ */\r
+uint32_t pmc_get_interrupt_mask(void)\r
+{\r
+ return PMC->PMC_IMR;\r
+}\r
+\r
+/**\r
+ * \brief Get current status.\r
+ *\r
+ * \return The current PMC status.\r
+ */\r
+uint32_t pmc_get_status(void)\r
+{\r
+ return PMC->PMC_SR;\r
+}\r
+\r
+/**\r
+ * \brief Set the wake-up inputs for fast startup mode registers\r
+ * (event generation).\r
+ *\r
+ * \param ul_inputs Wake up inputs to enable.\r
+ */\r
+void pmc_set_fast_startup_input(uint32_t ul_inputs)\r
+{\r
+ ul_inputs &= PMC_FAST_STARTUP_Msk;\r
+ PMC->PMC_FSMR |= ul_inputs;\r
+}\r
+\r
+/**\r
+ * \brief Clear the wake-up inputs for fast startup mode registers\r
+ * (remove event generation).\r
+ *\r
+ * \param ul_inputs Wake up inputs to disable.\r
+ */\r
+void pmc_clr_fast_startup_input(uint32_t ul_inputs)\r
+{\r
+ ul_inputs &= PMC_FAST_STARTUP_Msk;\r
+ PMC->PMC_FSMR &= ~ul_inputs;\r
+}\r
+\r
+/**\r
+ * \brief Enable Sleep Mode.\r
+ * Enter condition: (WFE or WFI) + (SLEEPDEEP bit = 0) + (LPM bit = 0)\r
+ *\r
+ * \param uc_type 0 for wait for interrupt, 1 for wait for event.\r
+ * \note For SAM4S and SAM4E series, since only WFI is effective, uc_type = 1\r
+ * will be treated as uc_type = 0.\r
+ */\r
+void pmc_enable_sleepmode(uint8_t uc_type)\r
+{\r
+#if !defined(SAM4S) || !defined(SAM4E) || !defined(SAM4N)\r
+ PMC->PMC_FSMR &= (uint32_t) ~ PMC_FSMR_LPM; // Enter Sleep mode\r
+#endif\r
+ SCB->SCR &= (uint32_t) ~ SCB_SCR_SLEEPDEEP_Msk; // Deep sleep\r
+\r
+#if (SAM4S || SAM4E || SAM4N)\r
+ UNUSED(uc_type);\r
+ __WFI();\r
+#else\r
+ if (uc_type == 0) {\r
+ __WFI();\r
+ } else {\r
+ __WFE();\r
+ }\r
+#endif\r
+}\r
+\r
+#if (SAM4S || SAM4E || SAM4N)\r
+static uint32_t ul_flash_in_wait_mode = PMC_WAIT_MODE_FLASH_DEEP_POWERDOWN;\r
+/**\r
+ * \brief Set the embedded flash state in wait mode\r
+ *\r
+ * \param ul_flash_state PMC_WAIT_MODE_FLASH_STANDBY flash in standby mode,\r
+ * PMC_WAIT_MODE_FLASH_DEEP_POWERDOWN flash in deep power down mode.\r
+ */\r
+void pmc_set_flash_in_wait_mode(uint32_t ul_flash_state)\r
+{\r
+ ul_flash_in_wait_mode = ul_flash_state;\r
+}\r
+\r
+/**\r
+ * \brief Enable Wait Mode. Enter condition: (WAITMODE bit = 1) +\r
+ * (SLEEPDEEP bit = 0) + FLPM\r
+ */\r
+void pmc_enable_waitmode(void)\r
+{\r
+ uint32_t i;\r
+\r
+ /* Flash in Deep Power Down mode */\r
+ i = PMC->PMC_FSMR;\r
+ i &= ~PMC_FSMR_FLPM_Msk;\r
+ i |= ul_flash_in_wait_mode;\r
+ PMC->PMC_FSMR = i;\r
+\r
+ /* Clear SLEEPDEEP bit */\r
+ SCB->SCR &= (uint32_t) ~ SCB_SCR_SLEEPDEEP_Msk;\r
+\r
+ /* Backup FWS setting and set Flash Wait State at 0 */\r
+#if defined(ID_EFC)\r
+ uint32_t fmr_backup;\r
+ fmr_backup = EFC->EEFC_FMR;\r
+ EFC->EEFC_FMR &= (uint32_t) ~ EEFC_FMR_FWS_Msk;\r
+#endif\r
+#if defined(ID_EFC0)\r
+ uint32_t fmr0_backup;\r
+ fmr0_backup = EFC0->EEFC_FMR;\r
+ EFC0->EEFC_FMR &= (uint32_t) ~ EEFC_FMR_FWS_Msk;\r
+#endif\r
+#if defined(ID_EFC1)\r
+ uint32_t fmr1_backup;\r
+ fmr1_backup = EFC1->EEFC_FMR;\r
+ EFC1->EEFC_FMR &= (uint32_t) ~ EEFC_FMR_FWS_Msk;\r
+#endif\r
+\r
+ /* Set the WAITMODE bit = 1 */\r
+ PMC->CKGR_MOR |= CKGR_MOR_KEY(0x37u) | CKGR_MOR_WAITMODE;\r
+\r
+ /* Waiting for Master Clock Ready MCKRDY = 1 */\r
+ while (!(PMC->PMC_SR & PMC_SR_MCKRDY));\r
+\r
+ /* Waiting for MOSCRCEN bit cleared is strongly recommended\r
+ * to ensure that the core will not execute undesired instructions\r
+ */\r
+ for (i = 0; i < 500; i++) {\r
+ __NOP();\r
+ }\r
+ while (!(PMC->CKGR_MOR & CKGR_MOR_MOSCRCEN));\r
+\r
+ /* Restore EFC FMR setting */\r
+#if defined(ID_EFC)\r
+ EFC->EEFC_FMR = fmr_backup;\r
+#endif\r
+#if defined(ID_EFC0)\r
+ EFC0->EEFC_FMR = fmr0_backup;\r
+#endif\r
+#if defined(ID_EFC1)\r
+ EFC1->EEFC_FMR = fmr1_backup;\r
+#endif\r
+}\r
+#else\r
+/**\r
+ * \brief Enable Wait Mode. Enter condition: WFE + (SLEEPDEEP bit = 0) +\r
+ * (LPM bit = 1)\r
+ */\r
+void pmc_enable_waitmode(void)\r
+{\r
+ uint32_t i;\r
+\r
+ PMC->PMC_FSMR |= PMC_FSMR_LPM; /* Enter Wait mode */\r
+ SCB->SCR &= (uint32_t) ~ SCB_SCR_SLEEPDEEP_Msk; /* Deep sleep */\r
+ __WFE();\r
+\r
+ /* Waiting for MOSCRCEN bit cleared is strongly recommended\r
+ * to ensure that the core will not execute undesired instructions\r
+ */\r
+ for (i = 0; i < 500; i++) {\r
+ __NOP();\r
+ }\r
+ while (!(PMC->CKGR_MOR & CKGR_MOR_MOSCRCEN));\r
+}\r
+#endif\r
+\r
+/**\r
+ * \brief Enable Backup Mode. Enter condition: WFE/(VROFF bit = 1) +\r
+ * (SLEEPDEEP bit = 1)\r
+ */\r
+void pmc_enable_backupmode(void)\r
+{\r
+ SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;\r
+#if (SAM4S || SAM4E || SAM4N)\r
+ SUPC->SUPC_CR = SUPC_CR_KEY(SUPC_KEY_VALUE) | SUPC_CR_VROFF_STOP_VREG;\r
+#else\r
+ __WFE();\r
+#endif\r
+}\r
+\r
+/**\r
+ * \brief Enable Clock Failure Detector.\r
+ */\r
+void pmc_enable_clock_failure_detector(void)\r
+{\r
+ uint32_t ul_reg = PMC->CKGR_MOR;\r
+\r
+ PMC->CKGR_MOR = PMC_CKGR_MOR_KEY_VALUE | CKGR_MOR_CFDEN | ul_reg;\r
+}\r
+\r
+/**\r
+ * \brief Disable Clock Failure Detector.\r
+ */\r
+void pmc_disable_clock_failure_detector(void)\r
+{\r
+ uint32_t ul_reg = PMC->CKGR_MOR & (~CKGR_MOR_CFDEN);\r
+\r
+ PMC->CKGR_MOR = PMC_CKGR_MOR_KEY_VALUE | ul_reg;\r
+}\r
+\r
+#if SAM4N\r
+/**\r
+ * \brief Enable Slow Crystal Oscillator Frequency Monitoring.\r
+ */\r
+void pmc_enable_sclk_osc_freq_monitor(void)\r
+{\r
+ uint32_t ul_reg = PMC->CKGR_MOR;\r
+\r
+ PMC->CKGR_MOR = PMC_CKGR_MOR_KEY_VALUE | CKGR_MOR_XT32KFME | ul_reg;\r
+}\r
+\r
+/**\r
+ * \brief Disable Slow Crystal Oscillator Frequency Monitoring.\r
+ */\r
+void pmc_disable_sclk_osc_freq_monitor(void)\r
+{\r
+ uint32_t ul_reg = PMC->CKGR_MOR & (~CKGR_MOR_XT32KFME);\r
+\r
+ PMC->CKGR_MOR = PMC_CKGR_MOR_KEY_VALUE | ul_reg;\r
+}\r
+#endif\r
+\r
+/**\r
+ * \brief Enable or disable write protect of PMC registers.\r
+ *\r
+ * \param ul_enable 1 to enable, 0 to disable.\r
+ */\r
+void pmc_set_writeprotect(uint32_t ul_enable)\r
+{\r
+ if (ul_enable) {\r
+ PMC->PMC_WPMR = PMC_WPMR_WPKEY_VALUE | PMC_WPMR_WPEN;\r
+ } else {\r
+ PMC->PMC_WPMR = PMC_WPMR_WPKEY_VALUE;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Return write protect status.\r
+ *\r
+ * \retval 0 Protection disabled.\r
+ * \retval 1 Protection enabled.\r
+ */\r
+uint32_t pmc_get_writeprotect_status(void)\r
+{\r
+ return PMC->PMC_WPMR & PMC_WPMR_WPEN;\r
+}\r
+\r
+/// @cond 0\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+/**INDENT-ON**/\r
+/// @endcond\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Power Management Controller (PMC) driver for SAM.\r
+ *\r
+ * Copyright (c) 2011 - 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef PMC_H_INCLUDED\r
+#define PMC_H_INCLUDED\r
+\r
+#include "compiler.h"\r
+\r
+/// @cond 0\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+/**INDENT-ON**/\r
+/// @endcond\r
+\r
+/** Bit mask for peripheral clocks (PCER0) */\r
+#define PMC_MASK_STATUS0 (0xFFFFFFFC)\r
+\r
+/** Bit mask for peripheral clocks (PCER1) */\r
+#define PMC_MASK_STATUS1 (0xFFFFFFFF)\r
+\r
+/** Loop counter timeout value */\r
+#define PMC_TIMEOUT (2048)\r
+\r
+/** Key to unlock CKGR_MOR register */\r
+#define PMC_CKGR_MOR_KEY_VALUE CKGR_MOR_KEY(0x37)\r
+\r
+/** Key used to write SUPC registers */\r
+#define SUPC_KEY_VALUE ((uint32_t) 0xA5)\r
+\r
+/** Mask to access fast startup input */\r
+#define PMC_FAST_STARTUP_Msk (0x7FFFFu)\r
+\r
+/** PMC_WPMR Write Protect KEY, unlock it */\r
+#define PMC_WPMR_WPKEY_VALUE PMC_WPMR_WPKEY((uint32_t) 0x504D43)\r
+\r
+/** Using external oscillator */\r
+#define PMC_OSC_XTAL 0\r
+\r
+/** Oscillator in bypass mode */\r
+#define PMC_OSC_BYPASS 1\r
+\r
+#define PMC_PCK_0 0 /* PCK0 ID */\r
+#define PMC_PCK_1 1 /* PCK1 ID */\r
+#define PMC_PCK_2 2 /* PCK2 ID */\r
+\r
+#if SAM4S || SAM4E || SAM4N\r
+/** Flash state in Wait Mode */\r
+#define PMC_WAIT_MODE_FLASH_STANDBY PMC_FSMR_FLPM_FLASH_STANDBY\r
+#define PMC_WAIT_MODE_FLASH_DEEP_POWERDOWN PMC_FSMR_FLPM_FLASH_DEEP_POWERDOWN\r
+#define PMC_WAIT_MODE_FLASH_IDLE PMC_FSMR_FLPM_FLASH_IDLE\r
+#endif\r
+\r
+/** Convert startup time from us to MOSCXTST */\r
+#define pmc_us_to_moscxtst(startup_us, slowck_freq) \\r
+ ((startup_us * slowck_freq / 8 / 1000000) < 0x100 ? \\r
+ (startup_us * slowck_freq / 8 / 1000000) : 0xFF)\r
+\r
+/**\r
+ * \name Master clock (MCK) Source and Prescaler configuration\r
+ *\r
+ * \note The following functions may be used to select the clock source and\r
+ * prescaler for the master clock.\r
+ */\r
+//@{\r
+\r
+void pmc_mck_set_prescaler(uint32_t ul_pres);\r
+void pmc_mck_set_source(uint32_t ul_source);\r
+uint32_t pmc_switch_mck_to_sclk(uint32_t ul_pres);\r
+uint32_t pmc_switch_mck_to_mainck(uint32_t ul_pres);\r
+uint32_t pmc_switch_mck_to_pllack(uint32_t ul_pres);\r
+#if (SAM3S || SAM4S)\r
+uint32_t pmc_switch_mck_to_pllbck(uint32_t ul_pres);\r
+#endif\r
+#if (SAM3XA || SAM3U)\r
+uint32_t pmc_switch_mck_to_upllck(uint32_t ul_pres);\r
+#endif\r
+#if (SAM4S || SAM4E || SAM4N)\r
+void pmc_set_flash_in_wait_mode(uint32_t ul_flash_state);\r
+#endif\r
+\r
+\r
+//@}\r
+\r
+/**\r
+ * \name Slow clock (SLCK) oscillator and configuration\r
+ *\r
+ */\r
+//@{\r
+\r
+void pmc_switch_sclk_to_32kxtal(uint32_t ul_bypass);\r
+uint32_t pmc_osc_is_ready_32kxtal(void);\r
+\r
+//@}\r
+\r
+/**\r
+ * \name Main Clock (MAINCK) oscillator and configuration\r
+ *\r
+ */\r
+//@{\r
+\r
+void pmc_switch_mainck_to_fastrc(uint32_t ul_moscrcf);\r
+void pmc_osc_enable_fastrc(uint32_t ul_rc);\r
+void pmc_osc_disable_fastrc(void);\r
+uint32_t pmc_osc_is_ready_fastrc(void);\r
+void pmc_osc_enable_main_xtal(uint32_t ul_xtal_startup_time);\r
+void pmc_osc_bypass_main_xtal(void);\r
+void pmc_osc_disable_main_xtal(void);\r
+uint32_t pmc_osc_is_bypassed_main_xtal(void);\r
+uint32_t pmc_osc_is_ready_main_xtal(void);\r
+void pmc_switch_mainck_to_xtal(uint32_t ul_bypass,\r
+ uint32_t ul_xtal_startup_time);\r
+void pmc_osc_disable_xtal(uint32_t ul_bypass);\r
+uint32_t pmc_osc_is_ready_mainck(void);\r
+void pmc_mainck_osc_select(uint32_t ul_xtal_rc);\r
+\r
+//@}\r
+\r
+/**\r
+ * \name PLL oscillator and configuration\r
+ *\r
+ */\r
+//@{\r
+\r
+void pmc_enable_pllack(uint32_t mula, uint32_t pllacount, uint32_t diva);\r
+void pmc_disable_pllack(void);\r
+uint32_t pmc_is_locked_pllack(void);\r
+\r
+#if (SAM3S || SAM4S)\r
+void pmc_enable_pllbck(uint32_t mulb, uint32_t pllbcount, uint32_t divb);\r
+void pmc_disable_pllbck(void);\r
+uint32_t pmc_is_locked_pllbck(void);\r
+#endif\r
+\r
+#if (SAM3XA || SAM3U)\r
+void pmc_enable_upll_clock(void);\r
+void pmc_disable_upll_clock(void);\r
+uint32_t pmc_is_locked_upll(void);\r
+#endif\r
+\r
+//@}\r
+\r
+/**\r
+ * \name Peripherals clock configuration\r
+ *\r
+ */\r
+//@{\r
+\r
+uint32_t pmc_enable_periph_clk(uint32_t ul_id);\r
+uint32_t pmc_disable_periph_clk(uint32_t ul_id);\r
+void pmc_enable_all_periph_clk(void);\r
+void pmc_disable_all_periph_clk(void);\r
+uint32_t pmc_is_periph_clk_enabled(uint32_t ul_id);\r
+\r
+//@}\r
+\r
+/**\r
+ * \name Programmable clock Source and Prescaler configuration\r
+ *\r
+ * The following functions may be used to select the clock source and\r
+ * prescaler for the specified programmable clock.\r
+ */\r
+//@{\r
+\r
+void pmc_pck_set_prescaler(uint32_t ul_id, uint32_t ul_pres);\r
+void pmc_pck_set_source(uint32_t ul_id, uint32_t ul_source);\r
+uint32_t pmc_switch_pck_to_sclk(uint32_t ul_id, uint32_t ul_pres);\r
+uint32_t pmc_switch_pck_to_mainck(uint32_t ul_id, uint32_t ul_pres);\r
+uint32_t pmc_switch_pck_to_pllack(uint32_t ul_id, uint32_t ul_pres);\r
+#if (SAM3S || SAM4S)\r
+uint32_t pmc_switch_pck_to_pllbck(uint32_t ul_id, uint32_t ul_pres);\r
+#endif\r
+#if (SAM3XA || SAM3U)\r
+uint32_t pmc_switch_pck_to_upllck(uint32_t ul_id, uint32_t ul_pres);\r
+#endif\r
+void pmc_enable_pck(uint32_t ul_id);\r
+void pmc_disable_pck(uint32_t ul_id);\r
+void pmc_enable_all_pck(void);\r
+void pmc_disable_all_pck(void);\r
+uint32_t pmc_is_pck_enabled(uint32_t ul_id);\r
+\r
+//@}\r
+\r
+/**\r
+ * \name USB clock configuration\r
+ *\r
+ */\r
+//@{\r
+\r
+#if (SAM3S || SAM3XA || SAM4S || SAM4E)\r
+void pmc_switch_udpck_to_pllack(uint32_t ul_usbdiv);\r
+#endif\r
+#if (SAM3S || SAM4S)\r
+void pmc_switch_udpck_to_pllbck(uint32_t ul_usbdiv);\r
+#endif\r
+#if (SAM3XA)\r
+void pmc_switch_udpck_to_upllck(uint32_t ul_usbdiv);\r
+#endif\r
+#if (SAM3S || SAM3XA || SAM4S || SAM4E)\r
+void pmc_enable_udpck(void);\r
+void pmc_disable_udpck(void);\r
+#endif\r
+\r
+//@}\r
+\r
+/**\r
+ * \name Interrupt and status management\r
+ *\r
+ */\r
+//@{\r
+\r
+void pmc_enable_interrupt(uint32_t ul_sources);\r
+void pmc_disable_interrupt(uint32_t ul_sources);\r
+uint32_t pmc_get_interrupt_mask(void);\r
+uint32_t pmc_get_status(void);\r
+\r
+//@}\r
+\r
+/**\r
+ * \name Power management\r
+ *\r
+ * The following functions are used to configure sleep mode and additional\r
+ * wake up inputs.\r
+ */\r
+//@{\r
+\r
+void pmc_set_fast_startup_input(uint32_t ul_inputs);\r
+void pmc_clr_fast_startup_input(uint32_t ul_inputs);\r
+void pmc_enable_sleepmode(uint8_t uc_type);\r
+void pmc_enable_waitmode(void);\r
+void pmc_enable_backupmode(void);\r
+\r
+//@}\r
+\r
+/**\r
+ * \name Failure detector\r
+ *\r
+ */\r
+//@{\r
+\r
+void pmc_enable_clock_failure_detector(void);\r
+void pmc_disable_clock_failure_detector(void);\r
+\r
+//@}\r
+\r
+#if SAM4N\r
+/**\r
+ * \name Slow Crystal Oscillator Frequency Monitoring\r
+ *\r
+ */\r
+//@{\r
+\r
+void pmc_enable_sclk_osc_freq_monitor(void);\r
+void pmc_disable_sclk_osc_freq_monitor(void);\r
+\r
+//@}\r
+#endif\r
+\r
+/**\r
+ * \name Write protection\r
+ *\r
+ */\r
+//@{\r
+\r
+void pmc_set_writeprotect(uint32_t ul_enable);\r
+uint32_t pmc_get_writeprotect_status(void);\r
+\r
+//@}\r
+\r
+/// @cond 0\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+/**INDENT-ON**/\r
+/// @endcond\r
+\r
+//! @}\r
+\r
+/**\r
+ * \page sam_pmc_quickstart Quick start guide for the SAM PMC module\r
+ *\r
+ * This is the quick start guide for the \ref pmc_group "PMC module", with\r
+ * step-by-step instructions on how to configure and use the driver in a\r
+ * selection of use cases.\r
+ *\r
+ * The use cases contain several code fragments. The code fragments in the\r
+ * steps for setup can be copied into a custom initialization function, while\r
+ * the steps for usage can be copied into, e.g., the main application function.\r
+ *\r
+ * \section pmc_use_cases PMC use cases\r
+ * - \ref pmc_basic_use_case Basic use case - Switch Main Clock sources\r
+ * - \ref pmc_use_case_2 Advanced use case - Configure Programmable Clocks\r
+ *\r
+ * \section pmc_basic_use_case Basic use case - Switch Main Clock sources\r
+ * In this use case, the PMC module is configured for a variety of system clock\r
+ * sources and speeds. A LED is used to visually indicate the current clock\r
+ * speed as the source is switched.\r
+ *\r
+ * \section pmc_basic_use_case_setup Setup\r
+ *\r
+ * \subsection pmc_basic_use_case_setup_prereq Prerequisites\r
+ * -# \ref gpio_group "General Purpose I/O Management (gpio)"\r
+ *\r
+ * \subsection pmc_basic_use_case_setup_code Code\r
+ * The following function needs to be added to the user application, to flash a\r
+ * board LED a variable number of times at a rate given in CPU ticks.\r
+ *\r
+ * \code\r
+ * #define FLASH_TICK_COUNT 0x00012345\r
+ *\r
+ * void flash_led(uint32_t tick_count, uint8_t flash_count)\r
+ * {\r
+ * SysTick->CTRL = SysTick_CTRL_ENABLE_Msk;\r
+ * SysTick->LOAD = tick_count;\r
+ *\r
+ * while (flash_count--)\r
+ * {\r
+ * gpio_toggle_pin(LED0_GPIO);\r
+ * while (!(SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk));\r
+ * gpio_toggle_pin(LED0_GPIO);\r
+ * while (!(SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk));\r
+ * }\r
+ * }\r
+ * \endcode\r
+ *\r
+ * \section pmc_basic_use_case_usage Use case\r
+ *\r
+ * \subsection pmc_basic_use_case_usage_code Example code\r
+ * Add to application C-file:\r
+ * \code\r
+ * for (;;)\r
+ * {\r
+ * pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_12_MHz);\r
+ * flash_led(FLASH_TICK_COUNT, 5);\r
+ * pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_8_MHz);\r
+ * flash_led(FLASH_TICK_COUNT, 5);\r
+ * pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_4_MHz);\r
+ * flash_led(FLASH_TICK_COUNT, 5);\r
+ * pmc_switch_mainck_to_xtal(0);\r
+ * flash_led(FLASH_TICK_COUNT, 5);\r
+ * }\r
+ * \endcode\r
+ *\r
+ * \subsection pmc_basic_use_case_usage_flow Workflow\r
+ * -# Wrap the code in an infinite loop:\r
+ * \code\r
+ * for (;;)\r
+ * \endcode\r
+ * -# Switch the Master CPU frequency to the internal 12MHz RC oscillator, flash\r
+ * a LED on the board several times:\r
+ * \code\r
+ * pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_12_MHz);\r
+ * flash_led(FLASH_TICK_COUNT, 5);\r
+ * \endcode\r
+ * -# Switch the Master CPU frequency to the internal 8MHz RC oscillator, flash\r
+ * a LED on the board several times:\r
+ * \code\r
+ * pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_8_MHz);\r
+ * flash_led(FLASH_TICK_COUNT, 5);\r
+ * \endcode\r
+ * -# Switch the Master CPU frequency to the internal 4MHz RC oscillator, flash\r
+ * a LED on the board several times:\r
+ * \code\r
+ * pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_4_MHz);\r
+ * flash_led(FLASH_TICK_COUNT, 5);\r
+ * \endcode\r
+ * -# Switch the Master CPU frequency to the external crystal oscillator, flash\r
+ * a LED on the board several times:\r
+ * \code\r
+ * pmc_switch_mainck_to_xtal(0, BOARD_OSC_STARTUP_US);\r
+ * flash_led(FLASH_TICK_COUNT, 5);\r
+ * \endcode\r
+ */\r
+\r
+/**\r
+ * \page pmc_use_case_2 Use case #2 - Configure Programmable Clocks\r
+ * In this use case, the PMC module is configured to start the Slow Clock from\r
+ * an attached 32KHz crystal, and start one of the Programmable Clock modules\r
+ * sourced from the Slow Clock divided down with a prescale factor of 64.\r
+ *\r
+ * \section pmc_use_case_2_setup Setup\r
+ *\r
+ * \subsection pmc_use_case_2_setup_prereq Prerequisites\r
+ * -# \ref pio_group "Parallel Input/Output Controller (pio)"\r
+ *\r
+ * \subsection pmc_use_case_2_setup_code Code\r
+ * The following code must be added to the user application:\r
+ * \code\r
+ * pio_set_peripheral(PIOA, PIO_PERIPH_B, PIO_PA17);\r
+ * \endcode\r
+ *\r
+ * \subsection pmc_use_case_2_setup_code_workflow Workflow\r
+ * -# Configure the PCK1 pin to output on a specific port pin (in this case,\r
+ * PIOA pin 17) of the microcontroller.\r
+ * \code\r
+ * pio_set_peripheral(PIOA, PIO_PERIPH_B, PIO_PA17);\r
+ * \endcode\r
+ * \note The peripheral selection and pin will vary according to your selected\r
+ * SAM device model. Refer to the "Peripheral Signal Multiplexing on I/O\r
+ * Lines" of your device's datasheet.\r
+ *\r
+ * \section pmc_use_case_2_usage Use case\r
+ * The generated PCK1 clock output can be viewed on an oscilloscope attached to\r
+ * the correct pin of the microcontroller.\r
+ *\r
+ * \subsection pmc_use_case_2_usage_code Example code\r
+ * Add to application C-file:\r
+ * \code\r
+ * pmc_switch_sclk_to_32kxtal(PMC_OSC_XTAL);\r
+ * pmc_switch_pck_to_sclk(PMC_PCK_1, PMC_PCK_PRES_CLK_64);\r
+ * pmc_enable_pck(PMC_PCK_1);\r
+ *\r
+ * for (;;)\r
+ * {\r
+ * // Do Nothing\r
+ * }\r
+ * \endcode\r
+ *\r
+ * \subsection pmc_use_case_2_usage_flow Workflow\r
+ * -# Switch the Slow Clock source input to an external 32KHz crystal:\r
+ * \code\r
+ * pmc_switch_sclk_to_32kxtal(PMC_OSC_XTAL);\r
+ * \endcode\r
+ * -# Switch the Programmable Clock module PCK1 source clock to the Slow Clock,\r
+ * with a prescaler of 64:\r
+ * \code\r
+ * pmc_switch_pck_to_sclk(PMC_PCK_1, PMC_PCK_PRES_CLK_64);\r
+ * \endcode\r
+ * -# Enable Programmable Clock module PCK1:\r
+ * \code\r
+ * pmc_enable_pck(PMC_PCK_1);\r
+ * \endcode\r
+ * -# Enter an infinite loop:\r
+ * \code\r
+ * for (;;)\r
+ * {\r
+ * // Do Nothing\r
+ * }\r
+ * \endcode\r
+ */\r
+\r
+#endif /* PMC_H_INCLUDED */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Sleep mode access\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#include <compiler.h>\r
+#include "sleep.h"\r
+\r
+/* SAM3 and SAM4 series */\r
+#if (SAM3S || SAM3N || SAM3XA || SAM3U || SAM4S || SAM4E || SAM4N)\r
+# include "pmc.h"\r
+# include "board.h"\r
+\r
+/* Checking board configuration of main clock xtal statup time */\r
+#if !defined(BOARD_OSC_STARTUP_US)\r
+# warning The board main clock xtal statup time has not been defined. Using default settings.\r
+# define BOARD_OSC_STARTUP_US (15625UL)\r
+#endif\r
+\r
+/**\r
+ * Save clock settings and shutdown PLLs\r
+ */\r
+__always_inline static void pmc_save_clock_settings(\r
+ uint32_t *p_osc_setting,\r
+ uint32_t *p_pll0_setting,\r
+ uint32_t *p_pll1_setting,\r
+ uint32_t *p_mck_setting)\r
+{\r
+ if (p_osc_setting) {\r
+ *p_osc_setting = PMC->CKGR_MOR;\r
+ }\r
+ if (p_pll0_setting) {\r
+ *p_pll0_setting = PMC->CKGR_PLLAR;\r
+ }\r
+ if (p_pll1_setting) {\r
+#if (SAM3S || SAM4S)\r
+ *p_pll1_setting = PMC->CKGR_PLLBR;\r
+#elif (SAM3U || SAM3XA)\r
+ *p_pll1_setting = PMC->CKGR_UCKR;\r
+#else\r
+ *p_pll1_setting = 0;\r
+#endif\r
+ }\r
+ if (p_mck_setting) {\r
+ *p_mck_setting = PMC->PMC_MCKR;\r
+ }\r
+\r
+ /* Switch MCK to internal 4/8/12M RC for fast wakeup\r
+ and disable unused clock for power saving. */\r
+ pmc_switch_mck_to_sclk(PMC_MCKR_PRES_CLK_1);\r
+ pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_4_MHz);\r
+ pmc_osc_disable_xtal(0);\r
+ pmc_disable_pllack();\r
+#if (SAM3S || SAM4S)\r
+ pmc_disable_pllbck();\r
+#elif (SAM3U || SAM3XA)\r
+ pmc_disable_upll_clock();\r
+#endif\r
+ pmc_switch_mck_to_mainck(PMC_MCKR_PRES_CLK_1);\r
+}\r
+\r
+/**\r
+ * Restore clock settings\r
+ */\r
+__always_inline static void pmc_restore_clock_setting(\r
+ uint32_t osc_setting,\r
+ uint32_t pll0_setting,\r
+ uint32_t pll1_setting,\r
+ uint32_t mck_setting)\r
+{\r
+ uint32_t mckr;\r
+ uint32_t pll_sr = 0;\r
+\r
+ /* Switch MCK to slow clock */\r
+ pmc_switch_mck_to_sclk(PMC_MCKR_PRES_CLK_1);\r
+ /* Switch mainck to external xtal */\r
+ if (CKGR_MOR_MOSCXTBY == (osc_setting & CKGR_MOR_MOSCXTBY)) {\r
+ /* Bypass mode */\r
+ pmc_switch_mainck_to_xtal(PMC_OSC_BYPASS,\r
+ pmc_us_to_moscxtst(BOARD_OSC_STARTUP_US,\r
+ CHIP_FREQ_SLCK_RC));\r
+ pmc_osc_disable_fastrc();\r
+ } else if (CKGR_MOR_MOSCXTEN == (osc_setting & CKGR_MOR_MOSCXTEN)) {\r
+ /* External XTAL */\r
+ pmc_switch_mainck_to_xtal(PMC_OSC_XTAL,\r
+ pmc_us_to_moscxtst(BOARD_OSC_STARTUP_US,\r
+ CHIP_FREQ_SLCK_RC));\r
+ pmc_osc_disable_fastrc();\r
+ }\r
+\r
+ if (pll0_setting & CKGR_PLLAR_MULA_Msk) {\r
+ PMC->CKGR_PLLAR = CKGR_PLLAR_ONE | pll0_setting;\r
+ pll_sr |= PMC_SR_LOCKA;\r
+ }\r
+#if (SAM3S || SAM4S)\r
+ if (pll1_setting & CKGR_PLLBR_MULB_Msk) {\r
+ PMC->CKGR_PLLBR = pll1_setting;\r
+ pll_sr |= PMC_SR_LOCKB;\r
+ }\r
+#elif (SAM3U || SAM3XA)\r
+ if (pll1_setting & CKGR_UCKR_UPLLEN) {\r
+ PMC->CKGR_UCKR = pll1_setting;\r
+ pll_sr |= PMC_SR_LOCKU;\r
+ }\r
+#else\r
+ UNUSED(pll1_setting);\r
+#endif\r
+ /* Wait MCK source ready */\r
+ switch(mck_setting & PMC_MCKR_CSS_Msk) {\r
+ case PMC_MCKR_CSS_PLLA_CLK:\r
+ while (!(PMC->PMC_SR & PMC_SR_LOCKA));\r
+ break;\r
+#if (SAM3S || SAM4S)\r
+ case PMC_MCKR_CSS_PLLB_CLK:\r
+ while (!(PMC->PMC_SR & PMC_SR_LOCKB));\r
+ break;\r
+#elif (SAM3U || SAM3XA)\r
+ case PMC_MCKR_CSS_UPLL_CLK:\r
+ while (!(PMC->PMC_SR & PMC_SR_LOCKU));\r
+ break;\r
+#endif\r
+ }\r
+\r
+ /* Switch to faster clock */\r
+ mckr = PMC->PMC_MCKR;\r
+ /* Set PRES */\r
+ PMC->PMC_MCKR = (mckr & ~PMC_MCKR_PRES_Msk)\r
+ | (mck_setting & PMC_MCKR_PRES_Msk);\r
+ while (!(PMC->PMC_SR & PMC_SR_MCKRDY));\r
+ /* Set CSS and others */\r
+ PMC->PMC_MCKR = mck_setting;\r
+ while (!(PMC->PMC_SR & PMC_SR_MCKRDY));\r
+ /* Waiting all restored PLLs ready */\r
+ while (!(PMC->PMC_SR & pll_sr));\r
+}\r
+\r
+/** If clocks are switched to FASTRC for WAIT mode */\r
+static volatile bool b_is_fastrc_used = false;\r
+/** Callback invoked once when clocks are restored */\r
+static pmc_callback_wakeup_clocks_restored_t callback_clocks_restored = NULL;\r
+\r
+void pmc_sleep(int sleep_mode)\r
+{\r
+ switch (sleep_mode) {\r
+ case SAM_PM_SMODE_SLEEP_WFI:\r
+ case SAM_PM_SMODE_SLEEP_WFE:\r
+#if (SAM4S || SAM4E || SAM4N)\r
+ SCB->SCR &= (uint32_t)~SCR_SLEEPDEEP;\r
+ cpu_irq_enable();\r
+ __WFI();\r
+ break;\r
+#else\r
+ PMC->PMC_FSMR &= (uint32_t)~PMC_FSMR_LPM;\r
+ SCB->SCR &= (uint32_t)~SCR_SLEEPDEEP;\r
+ cpu_irq_enable();\r
+ if (sleep_mode == SAM_PM_SMODE_SLEEP_WFI)\r
+ __WFI();\r
+ else\r
+ __WFE();\r
+ break;\r
+#endif\r
+ case SAM_PM_SMODE_WAIT: {\r
+ uint32_t mor, pllr0, pllr1, mckr;\r
+ cpu_irq_disable();\r
+ b_is_fastrc_used = true;\r
+ pmc_save_clock_settings(&mor, &pllr0, &pllr1, &mckr);\r
+\r
+ /* Enter wait mode */\r
+ cpu_irq_enable();\r
+ pmc_enable_waitmode();\r
+\r
+ cpu_irq_disable();\r
+ pmc_restore_clock_setting(mor, pllr0, pllr1, mckr);\r
+ b_is_fastrc_used = false;\r
+ if (callback_clocks_restored) {\r
+ callback_clocks_restored();\r
+ callback_clocks_restored = NULL;\r
+ }\r
+ cpu_irq_enable();\r
+ break;\r
+ }\r
+\r
+ case SAM_PM_SMODE_BACKUP:\r
+ SCB->SCR |= SCR_SLEEPDEEP;\r
+#if (SAM4S || SAM4E || SAM4N)\r
+ SUPC->SUPC_CR = SUPC_CR_KEY(0xA5u) | SUPC_CR_VROFF_STOP_VREG;\r
+ cpu_irq_enable();\r
+ __WFI() ;\r
+#else\r
+ cpu_irq_enable();\r
+ __WFE() ;\r
+#endif\r
+ break;\r
+ }\r
+}\r
+\r
+bool pmc_is_wakeup_clocks_restored(void)\r
+{\r
+ return !b_is_fastrc_used;\r
+}\r
+\r
+void pmc_wait_wakeup_clocks_restore(\r
+ pmc_callback_wakeup_clocks_restored_t callback)\r
+{\r
+ if (b_is_fastrc_used) {\r
+ cpu_irq_disable();\r
+ callback_clocks_restored = callback;\r
+ } else if (callback) {\r
+ callback();\r
+ }\r
+}\r
+\r
+#endif /* #if (SAM3S || SAM3N || SAM3XA || SAM3U || SAM4S || SAM4E || SAM4N) */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Sleep mode access\r
+ *\r
+ * Copyright (c) 2012 - 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef SLEEP_H\r
+#define SLEEP_H\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+#include <compiler.h>\r
+\r
+/**\r
+ * \defgroup sleep_group Power Manager (PM)\r
+ *\r
+ * This is a stub on the SAM Power Manager Control (PMC) for the sleepmgr\r
+ * service.\r
+ *\r
+ * \note To minimize the code overhead, these functions do not feature\r
+ * interrupt-protected access since they are likely to be called inside\r
+ * interrupt handlers or in applications where such protection is not\r
+ * necessary. If such protection is needed, it must be ensured by the calling\r
+ * code.\r
+ *\r
+ * @{\r
+ */\r
+\r
+#if defined(__DOXYGEN__)\r
+/**\r
+ * \brief Sets the MCU in the specified sleep mode\r
+ * \param sleep_mode Sleep mode to set.\r
+ */\r
+#endif\r
+/* SAM3 and SAM4 series */\r
+#if (SAM3S || SAM3N || SAM3XA || SAM3U || SAM4S || SAM4E || SAM4N)\r
+\r
+# define SAM_PM_SMODE_ACTIVE 0 /**< Active */\r
+# define SAM_PM_SMODE_SLEEP_WFE 1 /**< Wait for Events */\r
+# define SAM_PM_SMODE_SLEEP_WFI 2 /**< Wait for Interrupts */\r
+# define SAM_PM_SMODE_WAIT 3 /**< Wait Mode */\r
+# define SAM_PM_SMODE_BACKUP 4 /**< Backup Mode */\r
+\r
+/** (SCR) Sleep deep bit */\r
+#define SCR_SLEEPDEEP (0x1 << 2)\r
+\r
+/**\r
+ * Clocks restored callback function type.\r
+ * Registered by routine pmc_wait_wakeup_clocks_restore()\r
+ * Callback called when all clocks are restored.\r
+ */\r
+typedef void (*pmc_callback_wakeup_clocks_restored_t) (void);\r
+\r
+/**\r
+ * Enter sleep mode\r
+ * \param sleep_mode Sleep mode to enter\r
+ */\r
+void pmc_sleep(int sleep_mode);\r
+\r
+/**\r
+ * Check if clocks are restored after wakeup\r
+ * (For WAIT mode. In WAIT mode, clocks are switched to FASTRC.\r
+ * After wakeup clocks should be restored, before that some of the\r
+ * ISR should not be served, otherwise there may be timing or clock issue.)\r
+ */\r
+bool pmc_is_wakeup_clocks_restored(void);\r
+\r
+/**\r
+ * \r
+ * \return true if start waiting\r
+ */\r
+void pmc_wait_wakeup_clocks_restore(\r
+ pmc_callback_wakeup_clocks_restored_t callback);\r
+\r
+#endif\r
+\r
+//! @}\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* SLEEP_H */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4E_ACC_COMPONENT_\r
+#define _SAM4E_ACC_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Analog Comparator Controller */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM4E_ACC Analog Comparator Controller */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Acc hardware registers */\r
+typedef struct {\r
+ WoReg ACC_CR; /**< \brief (Acc Offset: 0x00) Control Register */\r
+ RwReg ACC_MR; /**< \brief (Acc Offset: 0x04) Mode Register */\r
+ RoReg Reserved1[7];\r
+ WoReg ACC_IER; /**< \brief (Acc Offset: 0x24) Interrupt Enable Register */\r
+ WoReg ACC_IDR; /**< \brief (Acc Offset: 0x28) Interrupt Disable Register */\r
+ RoReg ACC_IMR; /**< \brief (Acc Offset: 0x2C) Interrupt Mask Register */\r
+ RoReg ACC_ISR; /**< \brief (Acc Offset: 0x30) Interrupt Status Register */\r
+ RoReg Reserved2[24];\r
+ RwReg ACC_ACR; /**< \brief (Acc Offset: 0x94) Analog Control Register */\r
+ RoReg Reserved3[19];\r
+ RwReg ACC_WPMR; /**< \brief (Acc Offset: 0xE4) Write Protect Mode Register */\r
+ RoReg ACC_WPSR; /**< \brief (Acc Offset: 0xE8) Write Protect Status Register */\r
+} Acc;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- ACC_CR : (ACC Offset: 0x00) Control Register -------- */\r
+#define ACC_CR_SWRST (0x1u << 0) /**< \brief (ACC_CR) SoftWare ReSeT */\r
+/* -------- ACC_MR : (ACC Offset: 0x04) Mode Register -------- */\r
+#define ACC_MR_SELMINUS_Pos 0\r
+#define ACC_MR_SELMINUS_Msk (0x7u << ACC_MR_SELMINUS_Pos) /**< \brief (ACC_MR) SELection for MINUS comparator input */\r
+#define ACC_MR_SELMINUS_TS (0x0u << 0) /**< \brief (ACC_MR) SelectTS */\r
+#define ACC_MR_SELMINUS_ADVREF (0x1u << 0) /**< \brief (ACC_MR) Select ADVREF */\r
+#define ACC_MR_SELMINUS_DAC0 (0x2u << 0) /**< \brief (ACC_MR) Select DAC0 */\r
+#define ACC_MR_SELMINUS_DAC1 (0x3u << 0) /**< \brief (ACC_MR) Select DAC1 */\r
+#define ACC_MR_SELMINUS_AD0 (0x4u << 0) /**< \brief (ACC_MR) Select AD0 */\r
+#define ACC_MR_SELMINUS_AD1 (0x5u << 0) /**< \brief (ACC_MR) Select AD1 */\r
+#define ACC_MR_SELMINUS_AD2 (0x6u << 0) /**< \brief (ACC_MR) Select AD2 */\r
+#define ACC_MR_SELMINUS_AD3 (0x7u << 0) /**< \brief (ACC_MR) Select AD3 */\r
+#define ACC_MR_SELPLUS_Pos 4\r
+#define ACC_MR_SELPLUS_Msk (0x7u << ACC_MR_SELPLUS_Pos) /**< \brief (ACC_MR) SELection for PLUS comparator input */\r
+#define ACC_MR_SELPLUS_AD0 (0x0u << 4) /**< \brief (ACC_MR) Select AD0 */\r
+#define ACC_MR_SELPLUS_AD1 (0x1u << 4) /**< \brief (ACC_MR) Select AD1 */\r
+#define ACC_MR_SELPLUS_AD2 (0x2u << 4) /**< \brief (ACC_MR) Select AD2 */\r
+#define ACC_MR_SELPLUS_AD3 (0x3u << 4) /**< \brief (ACC_MR) Select AD3 */\r
+#define ACC_MR_SELPLUS_AD4 (0x4u << 4) /**< \brief (ACC_MR) Select AD4 */\r
+#define ACC_MR_SELPLUS_AD5 (0x5u << 4) /**< \brief (ACC_MR) Select AD5 */\r
+#define ACC_MR_SELPLUS_AD6 (0x6u << 4) /**< \brief (ACC_MR) Select AD6 */\r
+#define ACC_MR_SELPLUS_AD7 (0x7u << 4) /**< \brief (ACC_MR) Select AD7 */\r
+#define ACC_MR_ACEN (0x1u << 8) /**< \brief (ACC_MR) Analog Comparator ENable */\r
+#define ACC_MR_ACEN_DIS (0x0u << 8) /**< \brief (ACC_MR) Analog Comparator Disabled. */\r
+#define ACC_MR_ACEN_EN (0x1u << 8) /**< \brief (ACC_MR) Analog Comparator Enabled. */\r
+#define ACC_MR_EDGETYP_Pos 9\r
+#define ACC_MR_EDGETYP_Msk (0x3u << ACC_MR_EDGETYP_Pos) /**< \brief (ACC_MR) EDGE TYPe */\r
+#define ACC_MR_EDGETYP_RISING (0x0u << 9) /**< \brief (ACC_MR) only rising edge of comparator output */\r
+#define ACC_MR_EDGETYP_FALLING (0x1u << 9) /**< \brief (ACC_MR) falling edge of comparator output */\r
+#define ACC_MR_EDGETYP_ANY (0x2u << 9) /**< \brief (ACC_MR) any edge of comparator output */\r
+#define ACC_MR_INV (0x1u << 12) /**< \brief (ACC_MR) INVert comparator output */\r
+#define ACC_MR_INV_DIS (0x0u << 12) /**< \brief (ACC_MR) Analog Comparator output is directly processed. */\r
+#define ACC_MR_INV_EN (0x1u << 12) /**< \brief (ACC_MR) Analog Comparator output is inverted prior to being processed. */\r
+#define ACC_MR_SELFS (0x1u << 13) /**< \brief (ACC_MR) SELection of Fault Source */\r
+#define ACC_MR_SELFS_CF (0x0u << 13) /**< \brief (ACC_MR) the CF flag is used to drive the FAULT output. */\r
+#define ACC_MR_SELFS_OUTPUT (0x1u << 13) /**< \brief (ACC_MR) the output of the Analog Comparator flag is used to drive the FAULT output. */\r
+#define ACC_MR_FE (0x1u << 14) /**< \brief (ACC_MR) Fault Enable */\r
+#define ACC_MR_FE_DIS (0x0u << 14) /**< \brief (ACC_MR) the FAULT output is tied to 0. */\r
+#define ACC_MR_FE_EN (0x1u << 14) /**< \brief (ACC_MR) the FAULT output is driven by the signal defined by SELFS. */\r
+/* -------- ACC_IER : (ACC Offset: 0x24) Interrupt Enable Register -------- */\r
+#define ACC_IER_CE (0x1u << 0) /**< \brief (ACC_IER) Comparison Edge */\r
+/* -------- ACC_IDR : (ACC Offset: 0x28) Interrupt Disable Register -------- */\r
+#define ACC_IDR_CE (0x1u << 0) /**< \brief (ACC_IDR) Comparison Edge */\r
+/* -------- ACC_IMR : (ACC Offset: 0x2C) Interrupt Mask Register -------- */\r
+#define ACC_IMR_CE (0x1u << 0) /**< \brief (ACC_IMR) Comparison Edge */\r
+/* -------- ACC_ISR : (ACC Offset: 0x30) Interrupt Status Register -------- */\r
+#define ACC_ISR_CE (0x1u << 0) /**< \brief (ACC_ISR) Comparison Edge */\r
+#define ACC_ISR_SCO (0x1u << 1) /**< \brief (ACC_ISR) Synchronized Comparator Output */\r
+#define ACC_ISR_MASK (0x1u << 31) /**< \brief (ACC_ISR) */\r
+/* -------- ACC_ACR : (ACC Offset: 0x94) Analog Control Register -------- */\r
+#define ACC_ACR_ISEL (0x1u << 0) /**< \brief (ACC_ACR) Current SELection */\r
+#define ACC_ACR_ISEL_LOPW (0x0u << 0) /**< \brief (ACC_ACR) low power option. */\r
+#define ACC_ACR_ISEL_HISP (0x1u << 0) /**< \brief (ACC_ACR) high speed option. */\r
+#define ACC_ACR_HYST_Pos 1\r
+#define ACC_ACR_HYST_Msk (0x3u << ACC_ACR_HYST_Pos) /**< \brief (ACC_ACR) HYSTeresis selection */\r
+#define ACC_ACR_HYST(value) ((ACC_ACR_HYST_Msk & ((value) << ACC_ACR_HYST_Pos)))\r
+/* -------- ACC_WPMR : (ACC Offset: 0xE4) Write Protect Mode Register -------- */\r
+#define ACC_WPMR_WPEN (0x1u << 0) /**< \brief (ACC_WPMR) Write Protect Enable */\r
+#define ACC_WPMR_WPKEY_Pos 8\r
+#define ACC_WPMR_WPKEY_Msk (0xffffffu << ACC_WPMR_WPKEY_Pos) /**< \brief (ACC_WPMR) Write Protect KEY */\r
+#define ACC_WPMR_WPKEY(value) ((ACC_WPMR_WPKEY_Msk & ((value) << ACC_WPMR_WPKEY_Pos)))\r
+/* -------- ACC_WPSR : (ACC Offset: 0xE8) Write Protect Status Register -------- */\r
+#define ACC_WPSR_WPROTERR (0x1u << 0) /**< \brief (ACC_WPSR) Write PROTection ERRor */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM4E_ACC_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4E_AES_COMPONENT_\r
+#define _SAM4E_AES_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Advanced Encryption Standard */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM4E_AES Advanced Encryption Standard */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Aes hardware registers */\r
+typedef struct {\r
+ WoReg AES_CR; /**< \brief (Aes Offset: 0x00) Control Register */\r
+ RwReg AES_MR; /**< \brief (Aes Offset: 0x04) Mode Register */\r
+ RoReg Reserved1[2];\r
+ WoReg AES_IER; /**< \brief (Aes Offset: 0x10) Interrupt Enable Register */\r
+ WoReg AES_IDR; /**< \brief (Aes Offset: 0x14) Interrupt Disable Register */\r
+ RoReg AES_IMR; /**< \brief (Aes Offset: 0x18) Interrupt Mask Register */\r
+ RoReg AES_ISR; /**< \brief (Aes Offset: 0x1C) Interrupt Status Register */\r
+ WoReg AES_KEYWR[8]; /**< \brief (Aes Offset: 0x20) Key Word Register */\r
+ WoReg AES_IDATAR[4]; /**< \brief (Aes Offset: 0x40) Input Data Register */\r
+ RoReg AES_ODATAR[4]; /**< \brief (Aes Offset: 0x50) Output Data Register */\r
+ WoReg AES_IVR[4]; /**< \brief (Aes Offset: 0x60) Initialization Vector Register */\r
+} Aes;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- AES_CR : (AES Offset: 0x00) Control Register -------- */\r
+#define AES_CR_START (0x1u << 0) /**< \brief (AES_CR) Start Processing */\r
+#define AES_CR_SWRST (0x1u << 8) /**< \brief (AES_CR) Software Reset */\r
+/* -------- AES_MR : (AES Offset: 0x04) Mode Register -------- */\r
+#define AES_MR_CIPHER (0x1u << 0) /**< \brief (AES_MR) Processing Mode */\r
+#define AES_MR_DUALBUFF (0x1u << 3) /**< \brief (AES_MR) Dual Input BUFFer */\r
+#define AES_MR_DUALBUFF_INACTIVE (0x0u << 3) /**< \brief (AES_MR) AES_IDATARx cannot be written during processing of previous block. */\r
+#define AES_MR_DUALBUFF_ACTIVE (0x1u << 3) /**< \brief (AES_MR) AES_IDATARx can be written during processing of previous block when SMOD = 0x2. It speeds up the overall runtime of large files. */\r
+#define AES_MR_PROCDLY_Pos 4\r
+#define AES_MR_PROCDLY_Msk (0xfu << AES_MR_PROCDLY_Pos) /**< \brief (AES_MR) Processing Delay */\r
+#define AES_MR_PROCDLY(value) ((AES_MR_PROCDLY_Msk & ((value) << AES_MR_PROCDLY_Pos)))\r
+#define AES_MR_SMOD_Pos 8\r
+#define AES_MR_SMOD_Msk (0x3u << AES_MR_SMOD_Pos) /**< \brief (AES_MR) Start Mode */\r
+#define AES_MR_SMOD_MANUAL_START (0x0u << 8) /**< \brief (AES_MR) Manual Mode */\r
+#define AES_MR_SMOD_AUTO_START (0x1u << 8) /**< \brief (AES_MR) Auto Mode */\r
+#define AES_MR_SMOD_IDATAR0_START (0x2u << 8) /**< \brief (AES_MR) AES_IDATAR0 access only Auto Mode */\r
+#define AES_MR_KEYSIZE_Pos 10\r
+#define AES_MR_KEYSIZE_Msk (0x3u << AES_MR_KEYSIZE_Pos) /**< \brief (AES_MR) Key Size */\r
+#define AES_MR_KEYSIZE_AES128 (0x0u << 10) /**< \brief (AES_MR) AES Key Size is 128 bits */\r
+#define AES_MR_KEYSIZE_AES192 (0x1u << 10) /**< \brief (AES_MR) AES Key Size is 192 bits */\r
+#define AES_MR_KEYSIZE_AES256 (0x2u << 10) /**< \brief (AES_MR) AES Key Size is 256 bits */\r
+#define AES_MR_OPMOD_Pos 12\r
+#define AES_MR_OPMOD_Msk (0x7u << AES_MR_OPMOD_Pos) /**< \brief (AES_MR) Operation Mode */\r
+#define AES_MR_OPMOD_ECB (0x0u << 12) /**< \brief (AES_MR) ECB: Electronic Code Book mode */\r
+#define AES_MR_OPMOD_CBC (0x1u << 12) /**< \brief (AES_MR) CBC: Cipher Block Chaining mode */\r
+#define AES_MR_OPMOD_OFB (0x2u << 12) /**< \brief (AES_MR) OFB: Output Feedback mode */\r
+#define AES_MR_OPMOD_CFB (0x3u << 12) /**< \brief (AES_MR) CFB: Cipher Feedback mode */\r
+#define AES_MR_OPMOD_CTR (0x4u << 12) /**< \brief (AES_MR) CTR: Counter mode (16-bit internal counter) */\r
+#define AES_MR_LOD (0x1u << 15) /**< \brief (AES_MR) Last Output Data Mode */\r
+#define AES_MR_CFBS_Pos 16\r
+#define AES_MR_CFBS_Msk (0x7u << AES_MR_CFBS_Pos) /**< \brief (AES_MR) Cipher Feedback Data Size */\r
+#define AES_MR_CFBS_SIZE_128BIT (0x0u << 16) /**< \brief (AES_MR) 128-bit */\r
+#define AES_MR_CFBS_SIZE_64BIT (0x1u << 16) /**< \brief (AES_MR) 64-bit */\r
+#define AES_MR_CFBS_SIZE_32BIT (0x2u << 16) /**< \brief (AES_MR) 32-bit */\r
+#define AES_MR_CFBS_SIZE_16BIT (0x3u << 16) /**< \brief (AES_MR) 16-bit */\r
+#define AES_MR_CFBS_SIZE_8BIT (0x4u << 16) /**< \brief (AES_MR) 8-bit */\r
+#define AES_MR_CKEY_Pos 20\r
+#define AES_MR_CKEY_Msk (0xfu << AES_MR_CKEY_Pos) /**< \brief (AES_MR) Key */\r
+#define AES_MR_CKEY(value) ((AES_MR_CKEY_Msk & ((value) << AES_MR_CKEY_Pos)))\r
+/* -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- */\r
+#define AES_IER_DATRDY (0x1u << 0) /**< \brief (AES_IER) Data Ready Interrupt Enable */\r
+#define AES_IER_ENDRX (0x1u << 1) /**< \brief (AES_IER) End of Receive Buffer Interrupt Enable */\r
+#define AES_IER_ENDTX (0x1u << 2) /**< \brief (AES_IER) End of Transmit Buffer Interrupt Enable */\r
+#define AES_IER_RXBUFF (0x1u << 3) /**< \brief (AES_IER) Receive Buffer Full Interrupt Enable */\r
+#define AES_IER_TXBUFE (0x1u << 4) /**< \brief (AES_IER) Transmit Buffer Empty Interrupt Enable */\r
+#define AES_IER_URAD (0x1u << 8) /**< \brief (AES_IER) Unspecified Register Access Detection Interrupt Enable */\r
+/* -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- */\r
+#define AES_IDR_DATRDY (0x1u << 0) /**< \brief (AES_IDR) Data Ready Interrupt Disable */\r
+#define AES_IDR_ENDRX (0x1u << 1) /**< \brief (AES_IDR) End of Receive Buffer Interrupt Disable */\r
+#define AES_IDR_ENDTX (0x1u << 2) /**< \brief (AES_IDR) End of Transmit Buffer Interrupt Disable */\r
+#define AES_IDR_RXBUFF (0x1u << 3) /**< \brief (AES_IDR) Receive Buffer Full Interrupt Disable */\r
+#define AES_IDR_TXBUFE (0x1u << 4) /**< \brief (AES_IDR) Transmit Buffer Empty Interrupt Disable */\r
+#define AES_IDR_URAD (0x1u << 8) /**< \brief (AES_IDR) Unspecified Register Access Detection Interrupt Disable */\r
+/* -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- */\r
+#define AES_IMR_DATRDY (0x1u << 0) /**< \brief (AES_IMR) Data Ready Interrupt Mask */\r
+#define AES_IMR_ENDRX (0x1u << 1) /**< \brief (AES_IMR) End of Receive Buffer Interrupt Mask */\r
+#define AES_IMR_ENDTX (0x1u << 2) /**< \brief (AES_IMR) End of Transmit Buffer Interrupt Mask */\r
+#define AES_IMR_RXBUFF (0x1u << 3) /**< \brief (AES_IMR) Receive Buffer Full Interrupt Mask */\r
+#define AES_IMR_TXBUFE (0x1u << 4) /**< \brief (AES_IMR) Transmit Buffer Empty Interrupt Mask */\r
+#define AES_IMR_URAD (0x1u << 8) /**< \brief (AES_IMR) Unspecified Register Access Detection Interrupt Mask */\r
+/* -------- AES_ISR : (AES Offset: 0x1C) Interrupt Status Register -------- */\r
+#define AES_ISR_DATRDY (0x1u << 0) /**< \brief (AES_ISR) Data Ready */\r
+#define AES_ISR_ENDRX (0x1u << 1) /**< \brief (AES_ISR) End of RX Buffer */\r
+#define AES_ISR_ENDTX (0x1u << 2) /**< \brief (AES_ISR) End of TX Buffer */\r
+#define AES_ISR_RXBUFF (0x1u << 3) /**< \brief (AES_ISR) RX Buffer Full */\r
+#define AES_ISR_TXBUFE (0x1u << 4) /**< \brief (AES_ISR) TX Buffer Empty */\r
+#define AES_ISR_URAD (0x1u << 8) /**< \brief (AES_ISR) Unspecified Register Access Detection Status */\r
+#define AES_ISR_URAT_Pos 12\r
+#define AES_ISR_URAT_Msk (0xfu << AES_ISR_URAT_Pos) /**< \brief (AES_ISR) Unspecified Register Access: */\r
+#define AES_ISR_URAT_IDR_WR_PROCESSING (0x0u << 12) /**< \brief (AES_ISR) Input Data Register written during the data processing when SMOD=0x2 mode. */\r
+#define AES_ISR_URAT_ODR_RD_PROCESSING (0x1u << 12) /**< \brief (AES_ISR) Output Data Register read during the data processing. */\r
+#define AES_ISR_URAT_MR_WR_PROCESSING (0x2u << 12) /**< \brief (AES_ISR) Mode Register written during the data processing. */\r
+#define AES_ISR_URAT_ODR_RD_SUBKGEN (0x3u << 12) /**< \brief (AES_ISR) Output Data Register read during the sub-keys generation. */\r
+#define AES_ISR_URAT_MR_WR_SUBKGEN (0x4u << 12) /**< \brief (AES_ISR) Mode Register written during the sub-keys generation. */\r
+#define AES_ISR_URAT_WOR_RD_ACCESS (0x5u << 12) /**< \brief (AES_ISR) Write-only register read access. */\r
+/* -------- AES_KEYWR[8] : (AES Offset: 0x20) Key Word Register -------- */\r
+#define AES_KEYWR_KEYW_Pos 0\r
+#define AES_KEYWR_KEYW_Msk (0xffffffffu << AES_KEYWR_KEYW_Pos) /**< \brief (AES_KEYWR[8]) Key Word */\r
+#define AES_KEYWR_KEYW(value) ((AES_KEYWR_KEYW_Msk & ((value) << AES_KEYWR_KEYW_Pos)))\r
+/* -------- AES_IDATAR[4] : (AES Offset: 0x40) Input Data Register -------- */\r
+#define AES_IDATAR_IDATA_Pos 0\r
+#define AES_IDATAR_IDATA_Msk (0xffffffffu << AES_IDATAR_IDATA_Pos) /**< \brief (AES_IDATAR[4]) Input Data Word */\r
+#define AES_IDATAR_IDATA(value) ((AES_IDATAR_IDATA_Msk & ((value) << AES_IDATAR_IDATA_Pos)))\r
+/* -------- AES_ODATAR[4] : (AES Offset: 0x50) Output Data Register -------- */\r
+#define AES_ODATAR_ODATA_Pos 0\r
+#define AES_ODATAR_ODATA_Msk (0xffffffffu << AES_ODATAR_ODATA_Pos) /**< \brief (AES_ODATAR[4]) Output Data */\r
+/* -------- AES_IVR[4] : (AES Offset: 0x60) Initialization Vector Register -------- */\r
+#define AES_IVR_IV_Pos 0\r
+#define AES_IVR_IV_Msk (0xffffffffu << AES_IVR_IV_Pos) /**< \brief (AES_IVR[4]) Initialization Vector */\r
+#define AES_IVR_IV(value) ((AES_IVR_IV_Msk & ((value) << AES_IVR_IV_Pos)))\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM4E_AES_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4E_AFEC_COMPONENT_\r
+#define _SAM4E_AFEC_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Analog-Front-End Controller */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM4E_AFEC Analog-Front-End Controller */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Afec hardware registers */\r
+typedef struct {\r
+ WoReg AFEC_CR; /**< \brief (Afec Offset: 0x00) Control Register */\r
+ RwReg AFEC_MR; /**< \brief (Afec Offset: 0x04) Mode Register */\r
+ RwReg AFEC_EMR; /**< \brief (Afec Offset: 0x08) Extended Mode Register */\r
+ RwReg AFEC_SEQ1R; /**< \brief (Afec Offset: 0x0C) Channel Sequence 1 Register */\r
+ RwReg AFEC_SEQ2R; /**< \brief (Afec Offset: 0x10) Channel Sequence 2 Register */\r
+ WoReg AFEC_CHER; /**< \brief (Afec Offset: 0x14) Channel Enable Register */\r
+ WoReg AFEC_CHDR; /**< \brief (Afec Offset: 0x18) Channel Disable Register */\r
+ RoReg AFEC_CHSR; /**< \brief (Afec Offset: 0x1C) Channel Status Register */\r
+ RoReg AFEC_LCDR; /**< \brief (Afec Offset: 0x20) Last Converted Data Register */\r
+ WoReg AFEC_IER; /**< \brief (Afec Offset: 0x24) Interrupt Enable Register */\r
+ WoReg AFEC_IDR; /**< \brief (Afec Offset: 0x28) Interrupt Disable Register */\r
+ RoReg AFEC_IMR; /**< \brief (Afec Offset: 0x2C) Interrupt Mask Register */\r
+ RoReg AFEC_ISR; /**< \brief (Afec Offset: 0x30) Interrupt Status Register */\r
+ RoReg Reserved1[6];\r
+ RoReg AFEC_OVER; /**< \brief (Afec Offset: 0x4C) Overrun Status Register */\r
+ RwReg AFEC_CWR; /**< \brief (Afec Offset: 0x50) Compare Window Register */\r
+ RwReg AFEC_CGR; /**< \brief (Afec Offset: 0x54) Channel Gain Register */\r
+ RoReg Reserved2[1];\r
+ RwReg AFEC_CDOR; /**< \brief (Afec Offset: 0x5C) Channel Calibration DC Offset Register */\r
+ RwReg AFEC_DIFFR; /**< \brief (Afec Offset: 0x60) Channel Differential Register */\r
+ RwReg AFEC_CSELR; /**< \brief (Afec Offset: 0x64) Channel Register Selection */\r
+ RoReg AFEC_CDR; /**< \brief (Afec Offset: 0x68) Channel Data Register */\r
+ RwReg AFEC_COCR; /**< \brief (Afec Offset: 0x6C) Channel Offset Compensation Register */\r
+ RwReg AFEC_TEMPMR; /**< \brief (Afec Offset: 0x70) Temperature Sensor Mode Register */\r
+ RwReg AFEC_TEMPCWR; /**< \brief (Afec Offset: 0x74) Temperature Compare Window Register */\r
+ RoReg Reserved3[7];\r
+ RwReg AFEC_ACR; /**< \brief (Afec Offset: 0x94) Analog Control Register */\r
+ RoReg Reserved4[19];\r
+ RwReg AFEC_WPMR; /**< \brief (Afec Offset: 0xE4) Write Protect Mode Register */\r
+ RoReg AFEC_WPSR; /**< \brief (Afec Offset: 0xE8) Write Protect Status Register */\r
+ RoReg Reserved5[5];\r
+ RwReg AFEC_RPR; /**< \brief (Afec Offset: 0x100) Receive Pointer Register */\r
+ RwReg AFEC_RCR; /**< \brief (Afec Offset: 0x104) Receive Counter Register */\r
+ RoReg Reserved6[2];\r
+ RwReg AFEC_RNPR; /**< \brief (Afec Offset: 0x110) Receive Next Pointer Register */\r
+ RwReg AFEC_RNCR; /**< \brief (Afec Offset: 0x114) Receive Next Counter Register */\r
+ RoReg Reserved7[2];\r
+ WoReg AFEC_PTCR; /**< \brief (Afec Offset: 0x120) Transfer Control Register */\r
+ RoReg AFEC_PTSR; /**< \brief (Afec Offset: 0x124) Transfer Status Register */\r
+} Afec;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- AFEC_CR : (AFEC Offset: 0x00) Control Register -------- */\r
+#define AFEC_CR_SWRST (0x1u << 0) /**< \brief (AFEC_CR) Software Reset */\r
+#define AFEC_CR_START (0x1u << 1) /**< \brief (AFEC_CR) Start Conversion */\r
+#define AFEC_CR_AUTOCAL (0x1u << 3) /**< \brief (AFEC_CR) Automatic Calibration of AFEC */\r
+/* -------- AFEC_MR : (AFEC Offset: 0x04) Mode Register -------- */\r
+#define AFEC_MR_TRGEN (0x1u << 0) /**< \brief (AFEC_MR) Trigger Enable */\r
+#define AFEC_MR_TRGEN_DIS (0x0u << 0) /**< \brief (AFEC_MR) Hardware triggers are disabled. Starting a conversion is only possible by software. */\r
+#define AFEC_MR_TRGEN_EN (0x1u << 0) /**< \brief (AFEC_MR) Hardware trigger selected by TRGSEL field is enabled. */\r
+#define AFEC_MR_TRGSEL_Pos 1\r
+#define AFEC_MR_TRGSEL_Msk (0x7u << AFEC_MR_TRGSEL_Pos) /**< \brief (AFEC_MR) Trigger Selection */\r
+#define AFEC_MR_TRGSEL_AFEC_TRIG0 (0x0u << 1) /**< \brief (AFEC_MR) ADTRG pin */\r
+#define AFEC_MR_TRGSEL_AFEC_TRIG1 (0x1u << 1) /**< \brief (AFEC_MR) TIO Output of the Timer Counter Channel 0 */\r
+#define AFEC_MR_TRGSEL_AFEC_TRIG2 (0x2u << 1) /**< \brief (AFEC_MR) TIO Output of the Timer Counter Channel 1 */\r
+#define AFEC_MR_TRGSEL_AFEC_TRIG3 (0x3u << 1) /**< \brief (AFEC_MR) TIO Output of the Timer Counter Channel 2 */\r
+#define AFEC_MR_TRGSEL_AFEC_TRIG4 (0x4u << 1) /**< \brief (AFEC_MR) PWM Event Line 0 */\r
+#define AFEC_MR_TRGSEL_AFEC_TRIG5 (0x5u << 1) /**< \brief (AFEC_MR) PWM Event Line 1 */\r
+#define AFEC_MR_SLEEP (0x1u << 5) /**< \brief (AFEC_MR) Sleep Mode */\r
+#define AFEC_MR_SLEEP_NORMAL (0x0u << 5) /**< \brief (AFEC_MR) Normal Mode: The AFEC Core and reference voltage circuitry are kept ON between conversions */\r
+#define AFEC_MR_SLEEP_SLEEP (0x1u << 5) /**< \brief (AFEC_MR) Sleep Mode: The AFEC Core and reference voltage circuitry are OFF between conversions */\r
+#define AFEC_MR_FWUP (0x1u << 6) /**< \brief (AFEC_MR) Fast Wake Up */\r
+#define AFEC_MR_FWUP_OFF (0x0u << 6) /**< \brief (AFEC_MR) Normal Sleep Mode: The sleep mode is defined by the SLEEP bit */\r
+#define AFEC_MR_FWUP_ON (0x1u << 6) /**< \brief (AFEC_MR) Fast Wake Up Sleep Mode: The Voltage reference is ON between conversions and AFEC Core is OFF */\r
+#define AFEC_MR_FREERUN (0x1u << 7) /**< \brief (AFEC_MR) Free Run Mode */\r
+#define AFEC_MR_FREERUN_OFF (0x0u << 7) /**< \brief (AFEC_MR) Normal Mode */\r
+#define AFEC_MR_FREERUN_ON (0x1u << 7) /**< \brief (AFEC_MR) Free Run Mode: Never wait for any trigger. */\r
+#define AFEC_MR_PRESCAL_Pos 8\r
+#define AFEC_MR_PRESCAL_Msk (0xffu << AFEC_MR_PRESCAL_Pos) /**< \brief (AFEC_MR) Prescaler Rate Selection */\r
+#define AFEC_MR_PRESCAL(value) ((AFEC_MR_PRESCAL_Msk & ((value) << AFEC_MR_PRESCAL_Pos)))\r
+#define AFEC_MR_STARTUP_Pos 16\r
+#define AFEC_MR_STARTUP_Msk (0xfu << AFEC_MR_STARTUP_Pos) /**< \brief (AFEC_MR) Start Up Time */\r
+#define AFEC_MR_STARTUP_SUT0 (0x0u << 16) /**< \brief (AFEC_MR) 0 periods of AFEClock */\r
+#define AFEC_MR_STARTUP_SUT8 (0x1u << 16) /**< \brief (AFEC_MR) 8 periods of AFEClock */\r
+#define AFEC_MR_STARTUP_SUT16 (0x2u << 16) /**< \brief (AFEC_MR) 16 periods of AFEClock */\r
+#define AFEC_MR_STARTUP_SUT24 (0x3u << 16) /**< \brief (AFEC_MR) 24 periods of AFEClock */\r
+#define AFEC_MR_STARTUP_SUT64 (0x4u << 16) /**< \brief (AFEC_MR) 64 periods of AFEClock */\r
+#define AFEC_MR_STARTUP_SUT80 (0x5u << 16) /**< \brief (AFEC_MR) 80 periods of AFEClock */\r
+#define AFEC_MR_STARTUP_SUT96 (0x6u << 16) /**< \brief (AFEC_MR) 96 periods of AFEClock */\r
+#define AFEC_MR_STARTUP_SUT112 (0x7u << 16) /**< \brief (AFEC_MR) 112 periods of AFEClock */\r
+#define AFEC_MR_STARTUP_SUT512 (0x8u << 16) /**< \brief (AFEC_MR) 512 periods of AFEClock */\r
+#define AFEC_MR_STARTUP_SUT576 (0x9u << 16) /**< \brief (AFEC_MR) 576 periods of AFEClock */\r
+#define AFEC_MR_STARTUP_SUT640 (0xAu << 16) /**< \brief (AFEC_MR) 640 periods of AFEClock */\r
+#define AFEC_MR_STARTUP_SUT704 (0xBu << 16) /**< \brief (AFEC_MR) 704 periods of AFEClock */\r
+#define AFEC_MR_STARTUP_SUT768 (0xCu << 16) /**< \brief (AFEC_MR) 768 periods of AFEClock */\r
+#define AFEC_MR_STARTUP_SUT832 (0xDu << 16) /**< \brief (AFEC_MR) 832 periods of AFEClock */\r
+#define AFEC_MR_STARTUP_SUT896 (0xEu << 16) /**< \brief (AFEC_MR) 896 periods of AFEClock */\r
+#define AFEC_MR_STARTUP_SUT960 (0xFu << 16) /**< \brief (AFEC_MR) 960 periods of AFEClock */\r
+#define AFEC_MR_SETTLING_Pos 20\r
+#define AFEC_MR_SETTLING_Msk (0x3u << AFEC_MR_SETTLING_Pos) /**< \brief (AFEC_MR) Analog Settling Time */\r
+#define AFEC_MR_SETTLING_AST3 (0x0u << 20) /**< \brief (AFEC_MR) 3 periods of AFEClock */\r
+#define AFEC_MR_SETTLING_AST5 (0x1u << 20) /**< \brief (AFEC_MR) 5 periods of AFEClock */\r
+#define AFEC_MR_SETTLING_AST9 (0x2u << 20) /**< \brief (AFEC_MR) 9 periods of AFEClock */\r
+#define AFEC_MR_SETTLING_AST17 (0x3u << 20) /**< \brief (AFEC_MR) 17 periods of AFEClock */\r
+#define AFEC_MR_ANACH (0x1u << 23) /**< \brief (AFEC_MR) Analog Change */\r
+#define AFEC_MR_ANACH_NONE (0x0u << 23) /**< \brief (AFEC_MR) No analog change on channel switching: DIFF0, GAIN0 are used for all channels */\r
+#define AFEC_MR_ANACH_ALLOWED (0x1u << 23) /**< \brief (AFEC_MR) Allows different analog settings for each channel. See AFEC_CGR Register. */\r
+#define AFEC_MR_TRACKTIM_Pos 24\r
+#define AFEC_MR_TRACKTIM_Msk (0xfu << AFEC_MR_TRACKTIM_Pos) /**< \brief (AFEC_MR) Tracking Time */\r
+#define AFEC_MR_TRACKTIM(value) ((AFEC_MR_TRACKTIM_Msk & ((value) << AFEC_MR_TRACKTIM_Pos)))\r
+#define AFEC_MR_TRANSFER_Pos 28\r
+#define AFEC_MR_TRANSFER_Msk (0x3u << AFEC_MR_TRANSFER_Pos) /**< \brief (AFEC_MR) Transfer Period */\r
+#define AFEC_MR_TRANSFER(value) ((AFEC_MR_TRANSFER_Msk & ((value) << AFEC_MR_TRANSFER_Pos)))\r
+#define AFEC_MR_USEQ (0x1u << 31) /**< \brief (AFEC_MR) Use Sequence Enable */\r
+#define AFEC_MR_USEQ_NUM_ORDER (0x0u << 31) /**< \brief (AFEC_MR) Normal Mode: The controller converts channels in a simple numeric order. */\r
+#define AFEC_MR_USEQ_REG_ORDER (0x1u << 31) /**< \brief (AFEC_MR) User Sequence Mode: The sequence respects what is defined in AFEC_SEQR1 and AFEC_SEQR2 registers. */\r
+/* -------- AFEC_EMR : (AFEC Offset: 0x08) Extended Mode Register -------- */\r
+#define AFEC_EMR_CMPMODE_Pos 0\r
+#define AFEC_EMR_CMPMODE_Msk (0x3u << AFEC_EMR_CMPMODE_Pos) /**< \brief (AFEC_EMR) Comparison Mode */\r
+#define AFEC_EMR_CMPMODE_LOW (0x0u << 0) /**< \brief (AFEC_EMR) Generates an event when the converted data is lower than the low threshold of the window. */\r
+#define AFEC_EMR_CMPMODE_HIGH (0x1u << 0) /**< \brief (AFEC_EMR) Generates an event when the converted data is higher than the high threshold of the window. */\r
+#define AFEC_EMR_CMPMODE_IN (0x2u << 0) /**< \brief (AFEC_EMR) Generates an event when the converted data is in the comparison window. */\r
+#define AFEC_EMR_CMPMODE_OUT (0x3u << 0) /**< \brief (AFEC_EMR) Generates an event when the converted data is out of the comparison window. */\r
+#define AFEC_EMR_CMPSEL_Pos 3\r
+#define AFEC_EMR_CMPSEL_Msk (0x1fu << AFEC_EMR_CMPSEL_Pos) /**< \brief (AFEC_EMR) Comparison Selected Channel */\r
+#define AFEC_EMR_CMPSEL(value) ((AFEC_EMR_CMPSEL_Msk & ((value) << AFEC_EMR_CMPSEL_Pos)))\r
+#define AFEC_EMR_CMPALL (0x1u << 9) /**< \brief (AFEC_EMR) Compare All Channels */\r
+#define AFEC_EMR_CMPFILTER_Pos 12\r
+#define AFEC_EMR_CMPFILTER_Msk (0x3u << AFEC_EMR_CMPFILTER_Pos) /**< \brief (AFEC_EMR) Compare Event Filtering */\r
+#define AFEC_EMR_CMPFILTER(value) ((AFEC_EMR_CMPFILTER_Msk & ((value) << AFEC_EMR_CMPFILTER_Pos)))\r
+#define AFEC_EMR_RES_Pos 16\r
+#define AFEC_EMR_RES_Msk (0x7u << AFEC_EMR_RES_Pos) /**< \brief (AFEC_EMR) Resolution */\r
+#define AFEC_EMR_RES_NO_AVERAGE (0x0u << 16) /**< \brief (AFEC_EMR) 12-bit resolution, AFEC sample rate is maximum (no averaging). */\r
+#define AFEC_EMR_RES_LOW_RES (0x1u << 16) /**< \brief (AFEC_EMR) 10-bit resolution, AFEC sample rate is maximum (no averaging). */\r
+#define AFEC_EMR_RES_OSR4 (0x2u << 16) /**< \brief (AFEC_EMR) 13-bit resolution, AFEC sample rate divided by 4 (averaging). */\r
+#define AFEC_EMR_RES_OSR16 (0x3u << 16) /**< \brief (AFEC_EMR) 14-bit resolution, AFEC sample rate divided by 16 (averaging). */\r
+#define AFEC_EMR_RES_OSR64 (0x4u << 16) /**< \brief (AFEC_EMR) 15-bit resolution, AFEC sample rate divided by 64 (averaging). */\r
+#define AFEC_EMR_RES_OSR256 (0x5u << 16) /**< \brief (AFEC_EMR) 16-bit resolution, AFEC sample rate divided by 256 (averaging). */\r
+#define AFEC_EMR_TAG (0x1u << 24) /**< \brief (AFEC_EMR) TAG of AFEC_LDCR register */\r
+#define AFEC_EMR_STM (0x1u << 25) /**< \brief (AFEC_EMR) Single Trigger Mode */\r
+/* -------- AFEC_SEQ1R : (AFEC Offset: 0x0C) Channel Sequence 1 Register -------- */\r
+#define AFEC_SEQ1R_USCH0_Pos 0\r
+#define AFEC_SEQ1R_USCH0_Msk (0xfu << AFEC_SEQ1R_USCH0_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 0 */\r
+#define AFEC_SEQ1R_USCH0(value) ((AFEC_SEQ1R_USCH0_Msk & ((value) << AFEC_SEQ1R_USCH0_Pos)))\r
+#define AFEC_SEQ1R_USCH1_Pos 4\r
+#define AFEC_SEQ1R_USCH1_Msk (0xfu << AFEC_SEQ1R_USCH1_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 1 */\r
+#define AFEC_SEQ1R_USCH1(value) ((AFEC_SEQ1R_USCH1_Msk & ((value) << AFEC_SEQ1R_USCH1_Pos)))\r
+#define AFEC_SEQ1R_USCH2_Pos 8\r
+#define AFEC_SEQ1R_USCH2_Msk (0xfu << AFEC_SEQ1R_USCH2_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 2 */\r
+#define AFEC_SEQ1R_USCH2(value) ((AFEC_SEQ1R_USCH2_Msk & ((value) << AFEC_SEQ1R_USCH2_Pos)))\r
+#define AFEC_SEQ1R_USCH3_Pos 12\r
+#define AFEC_SEQ1R_USCH3_Msk (0xfu << AFEC_SEQ1R_USCH3_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 3 */\r
+#define AFEC_SEQ1R_USCH3(value) ((AFEC_SEQ1R_USCH3_Msk & ((value) << AFEC_SEQ1R_USCH3_Pos)))\r
+#define AFEC_SEQ1R_USCH4_Pos 16\r
+#define AFEC_SEQ1R_USCH4_Msk (0xfu << AFEC_SEQ1R_USCH4_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 4 */\r
+#define AFEC_SEQ1R_USCH4(value) ((AFEC_SEQ1R_USCH4_Msk & ((value) << AFEC_SEQ1R_USCH4_Pos)))\r
+#define AFEC_SEQ1R_USCH5_Pos 20\r
+#define AFEC_SEQ1R_USCH5_Msk (0xfu << AFEC_SEQ1R_USCH5_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 5 */\r
+#define AFEC_SEQ1R_USCH5(value) ((AFEC_SEQ1R_USCH5_Msk & ((value) << AFEC_SEQ1R_USCH5_Pos)))\r
+#define AFEC_SEQ1R_USCH6_Pos 24\r
+#define AFEC_SEQ1R_USCH6_Msk (0xfu << AFEC_SEQ1R_USCH6_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 6 */\r
+#define AFEC_SEQ1R_USCH6(value) ((AFEC_SEQ1R_USCH6_Msk & ((value) << AFEC_SEQ1R_USCH6_Pos)))\r
+#define AFEC_SEQ1R_USCH7_Pos 28\r
+#define AFEC_SEQ1R_USCH7_Msk (0xfu << AFEC_SEQ1R_USCH7_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 7 */\r
+#define AFEC_SEQ1R_USCH7(value) ((AFEC_SEQ1R_USCH7_Msk & ((value) << AFEC_SEQ1R_USCH7_Pos)))\r
+/* -------- AFEC_SEQ2R : (AFEC Offset: 0x10) Channel Sequence 2 Register -------- */\r
+#define AFEC_SEQ2R_USCH8_Pos 0\r
+#define AFEC_SEQ2R_USCH8_Msk (0xfu << AFEC_SEQ2R_USCH8_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 8 */\r
+#define AFEC_SEQ2R_USCH8(value) ((AFEC_SEQ2R_USCH8_Msk & ((value) << AFEC_SEQ2R_USCH8_Pos)))\r
+#define AFEC_SEQ2R_USCH9_Pos 4\r
+#define AFEC_SEQ2R_USCH9_Msk (0xfu << AFEC_SEQ2R_USCH9_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 9 */\r
+#define AFEC_SEQ2R_USCH9(value) ((AFEC_SEQ2R_USCH9_Msk & ((value) << AFEC_SEQ2R_USCH9_Pos)))\r
+#define AFEC_SEQ2R_USCH10_Pos 8\r
+#define AFEC_SEQ2R_USCH10_Msk (0xfu << AFEC_SEQ2R_USCH10_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 10 */\r
+#define AFEC_SEQ2R_USCH10(value) ((AFEC_SEQ2R_USCH10_Msk & ((value) << AFEC_SEQ2R_USCH10_Pos)))\r
+#define AFEC_SEQ2R_USCH11_Pos 12\r
+#define AFEC_SEQ2R_USCH11_Msk (0xfu << AFEC_SEQ2R_USCH11_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 11 */\r
+#define AFEC_SEQ2R_USCH11(value) ((AFEC_SEQ2R_USCH11_Msk & ((value) << AFEC_SEQ2R_USCH11_Pos)))\r
+#define AFEC_SEQ2R_USCH12_Pos 16\r
+#define AFEC_SEQ2R_USCH12_Msk (0xfu << AFEC_SEQ2R_USCH12_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 12 */\r
+#define AFEC_SEQ2R_USCH12(value) ((AFEC_SEQ2R_USCH12_Msk & ((value) << AFEC_SEQ2R_USCH12_Pos)))\r
+#define AFEC_SEQ2R_USCH13_Pos 20\r
+#define AFEC_SEQ2R_USCH13_Msk (0xfu << AFEC_SEQ2R_USCH13_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 13 */\r
+#define AFEC_SEQ2R_USCH13(value) ((AFEC_SEQ2R_USCH13_Msk & ((value) << AFEC_SEQ2R_USCH13_Pos)))\r
+#define AFEC_SEQ2R_USCH14_Pos 24\r
+#define AFEC_SEQ2R_USCH14_Msk (0xfu << AFEC_SEQ2R_USCH14_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 14 */\r
+#define AFEC_SEQ2R_USCH14(value) ((AFEC_SEQ2R_USCH14_Msk & ((value) << AFEC_SEQ2R_USCH14_Pos)))\r
+#define AFEC_SEQ2R_USCH15_Pos 28\r
+#define AFEC_SEQ2R_USCH15_Msk (0xfu << AFEC_SEQ2R_USCH15_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 15 */\r
+#define AFEC_SEQ2R_USCH15(value) ((AFEC_SEQ2R_USCH15_Msk & ((value) << AFEC_SEQ2R_USCH15_Pos)))\r
+/* -------- AFEC_CHER : (AFEC Offset: 0x14) Channel Enable Register -------- */\r
+#define AFEC_CHER_CH0 (0x1u << 0) /**< \brief (AFEC_CHER) Channel 0 Enable */\r
+#define AFEC_CHER_CH1 (0x1u << 1) /**< \brief (AFEC_CHER) Channel 1 Enable */\r
+#define AFEC_CHER_CH2 (0x1u << 2) /**< \brief (AFEC_CHER) Channel 2 Enable */\r
+#define AFEC_CHER_CH3 (0x1u << 3) /**< \brief (AFEC_CHER) Channel 3 Enable */\r
+#define AFEC_CHER_CH4 (0x1u << 4) /**< \brief (AFEC_CHER) Channel 4 Enable */\r
+#define AFEC_CHER_CH5 (0x1u << 5) /**< \brief (AFEC_CHER) Channel 5 Enable */\r
+#define AFEC_CHER_CH6 (0x1u << 6) /**< \brief (AFEC_CHER) Channel 6 Enable */\r
+#define AFEC_CHER_CH7 (0x1u << 7) /**< \brief (AFEC_CHER) Channel 7 Enable */\r
+#define AFEC_CHER_CH8 (0x1u << 8) /**< \brief (AFEC_CHER) Channel 8 Enable */\r
+#define AFEC_CHER_CH9 (0x1u << 9) /**< \brief (AFEC_CHER) Channel 9 Enable */\r
+#define AFEC_CHER_CH10 (0x1u << 10) /**< \brief (AFEC_CHER) Channel 10 Enable */\r
+#define AFEC_CHER_CH11 (0x1u << 11) /**< \brief (AFEC_CHER) Channel 11 Enable */\r
+#define AFEC_CHER_CH12 (0x1u << 12) /**< \brief (AFEC_CHER) Channel 12 Enable */\r
+#define AFEC_CHER_CH13 (0x1u << 13) /**< \brief (AFEC_CHER) Channel 13 Enable */\r
+#define AFEC_CHER_CH14 (0x1u << 14) /**< \brief (AFEC_CHER) Channel 14 Enable */\r
+#define AFEC_CHER_CH15 (0x1u << 15) /**< \brief (AFEC_CHER) Channel 15 Enable */\r
+/* -------- AFEC_CHDR : (AFEC Offset: 0x18) Channel Disable Register -------- */\r
+#define AFEC_CHDR_CH0 (0x1u << 0) /**< \brief (AFEC_CHDR) Channel 0 Disable */\r
+#define AFEC_CHDR_CH1 (0x1u << 1) /**< \brief (AFEC_CHDR) Channel 1 Disable */\r
+#define AFEC_CHDR_CH2 (0x1u << 2) /**< \brief (AFEC_CHDR) Channel 2 Disable */\r
+#define AFEC_CHDR_CH3 (0x1u << 3) /**< \brief (AFEC_CHDR) Channel 3 Disable */\r
+#define AFEC_CHDR_CH4 (0x1u << 4) /**< \brief (AFEC_CHDR) Channel 4 Disable */\r
+#define AFEC_CHDR_CH5 (0x1u << 5) /**< \brief (AFEC_CHDR) Channel 5 Disable */\r
+#define AFEC_CHDR_CH6 (0x1u << 6) /**< \brief (AFEC_CHDR) Channel 6 Disable */\r
+#define AFEC_CHDR_CH7 (0x1u << 7) /**< \brief (AFEC_CHDR) Channel 7 Disable */\r
+#define AFEC_CHDR_CH8 (0x1u << 8) /**< \brief (AFEC_CHDR) Channel 8 Disable */\r
+#define AFEC_CHDR_CH9 (0x1u << 9) /**< \brief (AFEC_CHDR) Channel 9 Disable */\r
+#define AFEC_CHDR_CH10 (0x1u << 10) /**< \brief (AFEC_CHDR) Channel 10 Disable */\r
+#define AFEC_CHDR_CH11 (0x1u << 11) /**< \brief (AFEC_CHDR) Channel 11 Disable */\r
+#define AFEC_CHDR_CH12 (0x1u << 12) /**< \brief (AFEC_CHDR) Channel 12 Disable */\r
+#define AFEC_CHDR_CH13 (0x1u << 13) /**< \brief (AFEC_CHDR) Channel 13 Disable */\r
+#define AFEC_CHDR_CH14 (0x1u << 14) /**< \brief (AFEC_CHDR) Channel 14 Disable */\r
+#define AFEC_CHDR_CH15 (0x1u << 15) /**< \brief (AFEC_CHDR) Channel 15 Disable */\r
+/* -------- AFEC_CHSR : (AFEC Offset: 0x1C) Channel Status Register -------- */\r
+#define AFEC_CHSR_CH0 (0x1u << 0) /**< \brief (AFEC_CHSR) Channel 0 Status */\r
+#define AFEC_CHSR_CH1 (0x1u << 1) /**< \brief (AFEC_CHSR) Channel 1 Status */\r
+#define AFEC_CHSR_CH2 (0x1u << 2) /**< \brief (AFEC_CHSR) Channel 2 Status */\r
+#define AFEC_CHSR_CH3 (0x1u << 3) /**< \brief (AFEC_CHSR) Channel 3 Status */\r
+#define AFEC_CHSR_CH4 (0x1u << 4) /**< \brief (AFEC_CHSR) Channel 4 Status */\r
+#define AFEC_CHSR_CH5 (0x1u << 5) /**< \brief (AFEC_CHSR) Channel 5 Status */\r
+#define AFEC_CHSR_CH6 (0x1u << 6) /**< \brief (AFEC_CHSR) Channel 6 Status */\r
+#define AFEC_CHSR_CH7 (0x1u << 7) /**< \brief (AFEC_CHSR) Channel 7 Status */\r
+#define AFEC_CHSR_CH8 (0x1u << 8) /**< \brief (AFEC_CHSR) Channel 8 Status */\r
+#define AFEC_CHSR_CH9 (0x1u << 9) /**< \brief (AFEC_CHSR) Channel 9 Status */\r
+#define AFEC_CHSR_CH10 (0x1u << 10) /**< \brief (AFEC_CHSR) Channel 10 Status */\r
+#define AFEC_CHSR_CH11 (0x1u << 11) /**< \brief (AFEC_CHSR) Channel 11 Status */\r
+#define AFEC_CHSR_CH12 (0x1u << 12) /**< \brief (AFEC_CHSR) Channel 12 Status */\r
+#define AFEC_CHSR_CH13 (0x1u << 13) /**< \brief (AFEC_CHSR) Channel 13 Status */\r
+#define AFEC_CHSR_CH14 (0x1u << 14) /**< \brief (AFEC_CHSR) Channel 14 Status */\r
+#define AFEC_CHSR_CH15 (0x1u << 15) /**< \brief (AFEC_CHSR) Channel 15 Status */\r
+/* -------- AFEC_LCDR : (AFEC Offset: 0x20) Last Converted Data Register -------- */\r
+#define AFEC_LCDR_LDATA_Pos 0\r
+#define AFEC_LCDR_LDATA_Msk (0xffffu << AFEC_LCDR_LDATA_Pos) /**< \brief (AFEC_LCDR) Last Data Converted */\r
+#define AFEC_LCDR_CHNB_Pos 24\r
+#define AFEC_LCDR_CHNB_Msk (0xfu << AFEC_LCDR_CHNB_Pos) /**< \brief (AFEC_LCDR) Channel Number */\r
+/* -------- AFEC_IER : (AFEC Offset: 0x24) Interrupt Enable Register -------- */\r
+#define AFEC_IER_EOC0 (0x1u << 0) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 0 */\r
+#define AFEC_IER_EOC1 (0x1u << 1) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 1 */\r
+#define AFEC_IER_EOC2 (0x1u << 2) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 2 */\r
+#define AFEC_IER_EOC3 (0x1u << 3) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 3 */\r
+#define AFEC_IER_EOC4 (0x1u << 4) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 4 */\r
+#define AFEC_IER_EOC5 (0x1u << 5) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 5 */\r
+#define AFEC_IER_EOC6 (0x1u << 6) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 6 */\r
+#define AFEC_IER_EOC7 (0x1u << 7) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 7 */\r
+#define AFEC_IER_EOC8 (0x1u << 8) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 8 */\r
+#define AFEC_IER_EOC9 (0x1u << 9) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 9 */\r
+#define AFEC_IER_EOC10 (0x1u << 10) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 10 */\r
+#define AFEC_IER_EOC11 (0x1u << 11) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 11 */\r
+#define AFEC_IER_EOC12 (0x1u << 12) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 12 */\r
+#define AFEC_IER_EOC13 (0x1u << 13) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 13 */\r
+#define AFEC_IER_EOC14 (0x1u << 14) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 14 */\r
+#define AFEC_IER_EOC15 (0x1u << 15) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 15 */\r
+#define AFEC_IER_DRDY (0x1u << 24) /**< \brief (AFEC_IER) Data Ready Interrupt Enable */\r
+#define AFEC_IER_GOVRE (0x1u << 25) /**< \brief (AFEC_IER) General Overrun Error Interrupt Enable */\r
+#define AFEC_IER_COMPE (0x1u << 26) /**< \brief (AFEC_IER) Comparison Event Interrupt Enable+ */\r
+#define AFEC_IER_ENDRX (0x1u << 27) /**< \brief (AFEC_IER) End of Receive Buffer Interrupt Enable */\r
+#define AFEC_IER_RXBUFF (0x1u << 28) /**< \brief (AFEC_IER) Receive Buffer Full Interrupt Enable */\r
+#define AFEC_IER_TEMPCHG (0x1u << 30) /**< \brief (AFEC_IER) Temperature Change Interrupt Enable */\r
+#define AFEC_IER_EOCAL (0x1u << 31) /**< \brief (AFEC_IER) End of Calibration Sequence Interrupt Enable */\r
+/* -------- AFEC_IDR : (AFEC Offset: 0x28) Interrupt Disable Register -------- */\r
+#define AFEC_IDR_EOC0 (0x1u << 0) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 0 */\r
+#define AFEC_IDR_EOC1 (0x1u << 1) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 1 */\r
+#define AFEC_IDR_EOC2 (0x1u << 2) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 2 */\r
+#define AFEC_IDR_EOC3 (0x1u << 3) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 3 */\r
+#define AFEC_IDR_EOC4 (0x1u << 4) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 4 */\r
+#define AFEC_IDR_EOC5 (0x1u << 5) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 5 */\r
+#define AFEC_IDR_EOC6 (0x1u << 6) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 6 */\r
+#define AFEC_IDR_EOC7 (0x1u << 7) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 7 */\r
+#define AFEC_IDR_EOC8 (0x1u << 8) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 8 */\r
+#define AFEC_IDR_EOC9 (0x1u << 9) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 9 */\r
+#define AFEC_IDR_EOC10 (0x1u << 10) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 10 */\r
+#define AFEC_IDR_EOC11 (0x1u << 11) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 11 */\r
+#define AFEC_IDR_EOC12 (0x1u << 12) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 12 */\r
+#define AFEC_IDR_EOC13 (0x1u << 13) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 13 */\r
+#define AFEC_IDR_EOC14 (0x1u << 14) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 14 */\r
+#define AFEC_IDR_EOC15 (0x1u << 15) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 15 */\r
+#define AFEC_IDR_DRDY (0x1u << 24) /**< \brief (AFEC_IDR) Data Ready Interrupt Disable */\r
+#define AFEC_IDR_GOVRE (0x1u << 25) /**< \brief (AFEC_IDR) General Overrun Error Interrupt Disable */\r
+#define AFEC_IDR_COMPE (0x1u << 26) /**< \brief (AFEC_IDR) Comparison Event Interrupt Disable */\r
+#define AFEC_IDR_ENDRX (0x1u << 27) /**< \brief (AFEC_IDR) End of Receive Buffer Interrupt Disable */\r
+#define AFEC_IDR_RXBUFF (0x1u << 28) /**< \brief (AFEC_IDR) Receive Buffer Full Interrupt Disable */\r
+#define AFEC_IDR_TEMPCHG (0x1u << 30) /**< \brief (AFEC_IDR) Temperature Change Interrupt Disable */\r
+#define AFEC_IDR_EOCAL (0x1u << 31) /**< \brief (AFEC_IDR) End of Calibration Sequence Interrupt Disable */\r
+/* -------- AFEC_IMR : (AFEC Offset: 0x2C) Interrupt Mask Register -------- */\r
+#define AFEC_IMR_EOC0 (0x1u << 0) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 0 */\r
+#define AFEC_IMR_EOC1 (0x1u << 1) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 1 */\r
+#define AFEC_IMR_EOC2 (0x1u << 2) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 2 */\r
+#define AFEC_IMR_EOC3 (0x1u << 3) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 3 */\r
+#define AFEC_IMR_EOC4 (0x1u << 4) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 4 */\r
+#define AFEC_IMR_EOC5 (0x1u << 5) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 5 */\r
+#define AFEC_IMR_EOC6 (0x1u << 6) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 6 */\r
+#define AFEC_IMR_EOC7 (0x1u << 7) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 7 */\r
+#define AFEC_IMR_EOC8 (0x1u << 8) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 8 */\r
+#define AFEC_IMR_EOC9 (0x1u << 9) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 9 */\r
+#define AFEC_IMR_EOC10 (0x1u << 10) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 10 */\r
+#define AFEC_IMR_EOC11 (0x1u << 11) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 11 */\r
+#define AFEC_IMR_EOC12 (0x1u << 12) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 12 */\r
+#define AFEC_IMR_EOC13 (0x1u << 13) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 13 */\r
+#define AFEC_IMR_EOC14 (0x1u << 14) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 14 */\r
+#define AFEC_IMR_EOC15 (0x1u << 15) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 15 */\r
+#define AFEC_IMR_DRDY (0x1u << 24) /**< \brief (AFEC_IMR) Data Ready Interrupt Mask */\r
+#define AFEC_IMR_GOVRE (0x1u << 25) /**< \brief (AFEC_IMR) General Overrun Error Interrupt Mask */\r
+#define AFEC_IMR_COMPE (0x1u << 26) /**< \brief (AFEC_IMR) Comparison Event Interrupt Mask */\r
+#define AFEC_IMR_ENDRX (0x1u << 27) /**< \brief (AFEC_IMR) End of Receive Buffer Interrupt Mask */\r
+#define AFEC_IMR_RXBUFF (0x1u << 28) /**< \brief (AFEC_IMR) Receive Buffer Full Interrupt Mask */\r
+#define AFEC_IMR_TEMPCHG (0x1u << 30) /**< \brief (AFEC_IMR) Temperature Change Interrupt Mask */\r
+#define AFEC_IMR_EOCAL (0x1u << 31) /**< \brief (AFEC_IMR) End of Calibration Sequence Interrupt Mask */\r
+/* -------- AFEC_ISR : (AFEC Offset: 0x30) Interrupt Status Register -------- */\r
+#define AFEC_ISR_EOC0 (0x1u << 0) /**< \brief (AFEC_ISR) End of Conversion 0 */\r
+#define AFEC_ISR_EOC1 (0x1u << 1) /**< \brief (AFEC_ISR) End of Conversion 1 */\r
+#define AFEC_ISR_EOC2 (0x1u << 2) /**< \brief (AFEC_ISR) End of Conversion 2 */\r
+#define AFEC_ISR_EOC3 (0x1u << 3) /**< \brief (AFEC_ISR) End of Conversion 3 */\r
+#define AFEC_ISR_EOC4 (0x1u << 4) /**< \brief (AFEC_ISR) End of Conversion 4 */\r
+#define AFEC_ISR_EOC5 (0x1u << 5) /**< \brief (AFEC_ISR) End of Conversion 5 */\r
+#define AFEC_ISR_EOC6 (0x1u << 6) /**< \brief (AFEC_ISR) End of Conversion 6 */\r
+#define AFEC_ISR_EOC7 (0x1u << 7) /**< \brief (AFEC_ISR) End of Conversion 7 */\r
+#define AFEC_ISR_EOC8 (0x1u << 8) /**< \brief (AFEC_ISR) End of Conversion 8 */\r
+#define AFEC_ISR_EOC9 (0x1u << 9) /**< \brief (AFEC_ISR) End of Conversion 9 */\r
+#define AFEC_ISR_EOC10 (0x1u << 10) /**< \brief (AFEC_ISR) End of Conversion 10 */\r
+#define AFEC_ISR_EOC11 (0x1u << 11) /**< \brief (AFEC_ISR) End of Conversion 11 */\r
+#define AFEC_ISR_EOC12 (0x1u << 12) /**< \brief (AFEC_ISR) End of Conversion 12 */\r
+#define AFEC_ISR_EOC13 (0x1u << 13) /**< \brief (AFEC_ISR) End of Conversion 13 */\r
+#define AFEC_ISR_EOC14 (0x1u << 14) /**< \brief (AFEC_ISR) End of Conversion 14 */\r
+#define AFEC_ISR_EOC15 (0x1u << 15) /**< \brief (AFEC_ISR) End of Conversion 15 */\r
+#define AFEC_ISR_DRDY (0x1u << 24) /**< \brief (AFEC_ISR) Data Ready */\r
+#define AFEC_ISR_GOVRE (0x1u << 25) /**< \brief (AFEC_ISR) General Overrun Error */\r
+#define AFEC_ISR_COMPE (0x1u << 26) /**< \brief (AFEC_ISR) Comparison Error */\r
+#define AFEC_ISR_ENDRX (0x1u << 27) /**< \brief (AFEC_ISR) End of RX Buffer */\r
+#define AFEC_ISR_RXBUFF (0x1u << 28) /**< \brief (AFEC_ISR) RX Buffer Full */\r
+#define AFEC_ISR_TEMPCHG (0x1u << 30) /**< \brief (AFEC_ISR) Temperature Change */\r
+#define AFEC_ISR_EOCAL (0x1u << 31) /**< \brief (AFEC_ISR) End of Calibration Sequence */\r
+/* -------- AFEC_OVER : (AFEC Offset: 0x4C) Overrun Status Register -------- */\r
+#define AFEC_OVER_OVRE0 (0x1u << 0) /**< \brief (AFEC_OVER) Overrun Error 0 */\r
+#define AFEC_OVER_OVRE1 (0x1u << 1) /**< \brief (AFEC_OVER) Overrun Error 1 */\r
+#define AFEC_OVER_OVRE2 (0x1u << 2) /**< \brief (AFEC_OVER) Overrun Error 2 */\r
+#define AFEC_OVER_OVRE3 (0x1u << 3) /**< \brief (AFEC_OVER) Overrun Error 3 */\r
+#define AFEC_OVER_OVRE4 (0x1u << 4) /**< \brief (AFEC_OVER) Overrun Error 4 */\r
+#define AFEC_OVER_OVRE5 (0x1u << 5) /**< \brief (AFEC_OVER) Overrun Error 5 */\r
+#define AFEC_OVER_OVRE6 (0x1u << 6) /**< \brief (AFEC_OVER) Overrun Error 6 */\r
+#define AFEC_OVER_OVRE7 (0x1u << 7) /**< \brief (AFEC_OVER) Overrun Error 7 */\r
+#define AFEC_OVER_OVRE8 (0x1u << 8) /**< \brief (AFEC_OVER) Overrun Error 8 */\r
+#define AFEC_OVER_OVRE9 (0x1u << 9) /**< \brief (AFEC_OVER) Overrun Error 9 */\r
+#define AFEC_OVER_OVRE10 (0x1u << 10) /**< \brief (AFEC_OVER) Overrun Error 10 */\r
+#define AFEC_OVER_OVRE11 (0x1u << 11) /**< \brief (AFEC_OVER) Overrun Error 11 */\r
+#define AFEC_OVER_OVRE12 (0x1u << 12) /**< \brief (AFEC_OVER) Overrun Error 12 */\r
+#define AFEC_OVER_OVRE13 (0x1u << 13) /**< \brief (AFEC_OVER) Overrun Error 13 */\r
+#define AFEC_OVER_OVRE14 (0x1u << 14) /**< \brief (AFEC_OVER) Overrun Error 14 */\r
+#define AFEC_OVER_OVRE15 (0x1u << 15) /**< \brief (AFEC_OVER) Overrun Error 15 */\r
+/* -------- AFEC_CWR : (AFEC Offset: 0x50) Compare Window Register -------- */\r
+#define AFEC_CWR_LOWTHRES_Pos 0\r
+#define AFEC_CWR_LOWTHRES_Msk (0xfffu << AFEC_CWR_LOWTHRES_Pos) /**< \brief (AFEC_CWR) Low Threshold */\r
+#define AFEC_CWR_LOWTHRES(value) ((AFEC_CWR_LOWTHRES_Msk & ((value) << AFEC_CWR_LOWTHRES_Pos)))\r
+#define AFEC_CWR_HIGHTHRES_Pos 16\r
+#define AFEC_CWR_HIGHTHRES_Msk (0xfffu << AFEC_CWR_HIGHTHRES_Pos) /**< \brief (AFEC_CWR) High Threshold */\r
+#define AFEC_CWR_HIGHTHRES(value) ((AFEC_CWR_HIGHTHRES_Msk & ((value) << AFEC_CWR_HIGHTHRES_Pos)))\r
+/* -------- AFEC_CGR : (AFEC Offset: 0x54) Channel Gain Register -------- */\r
+#define AFEC_CGR_GAIN0_Pos 0\r
+#define AFEC_CGR_GAIN0_Msk (0x3u << AFEC_CGR_GAIN0_Pos) /**< \brief (AFEC_CGR) Gain for channel 0 */\r
+#define AFEC_CGR_GAIN0(value) ((AFEC_CGR_GAIN0_Msk & ((value) << AFEC_CGR_GAIN0_Pos)))\r
+#define AFEC_CGR_GAIN1_Pos 2\r
+#define AFEC_CGR_GAIN1_Msk (0x3u << AFEC_CGR_GAIN1_Pos) /**< \brief (AFEC_CGR) Gain for channel 1 */\r
+#define AFEC_CGR_GAIN1(value) ((AFEC_CGR_GAIN1_Msk & ((value) << AFEC_CGR_GAIN1_Pos)))\r
+#define AFEC_CGR_GAIN2_Pos 4\r
+#define AFEC_CGR_GAIN2_Msk (0x3u << AFEC_CGR_GAIN2_Pos) /**< \brief (AFEC_CGR) Gain for channel 2 */\r
+#define AFEC_CGR_GAIN2(value) ((AFEC_CGR_GAIN2_Msk & ((value) << AFEC_CGR_GAIN2_Pos)))\r
+#define AFEC_CGR_GAIN3_Pos 6\r
+#define AFEC_CGR_GAIN3_Msk (0x3u << AFEC_CGR_GAIN3_Pos) /**< \brief (AFEC_CGR) Gain for channel 3 */\r
+#define AFEC_CGR_GAIN3(value) ((AFEC_CGR_GAIN3_Msk & ((value) << AFEC_CGR_GAIN3_Pos)))\r
+#define AFEC_CGR_GAIN4_Pos 8\r
+#define AFEC_CGR_GAIN4_Msk (0x3u << AFEC_CGR_GAIN4_Pos) /**< \brief (AFEC_CGR) Gain for channel 4 */\r
+#define AFEC_CGR_GAIN4(value) ((AFEC_CGR_GAIN4_Msk & ((value) << AFEC_CGR_GAIN4_Pos)))\r
+#define AFEC_CGR_GAIN5_Pos 10\r
+#define AFEC_CGR_GAIN5_Msk (0x3u << AFEC_CGR_GAIN5_Pos) /**< \brief (AFEC_CGR) Gain for channel 5 */\r
+#define AFEC_CGR_GAIN5(value) ((AFEC_CGR_GAIN5_Msk & ((value) << AFEC_CGR_GAIN5_Pos)))\r
+#define AFEC_CGR_GAIN6_Pos 12\r
+#define AFEC_CGR_GAIN6_Msk (0x3u << AFEC_CGR_GAIN6_Pos) /**< \brief (AFEC_CGR) Gain for channel 6 */\r
+#define AFEC_CGR_GAIN6(value) ((AFEC_CGR_GAIN6_Msk & ((value) << AFEC_CGR_GAIN6_Pos)))\r
+#define AFEC_CGR_GAIN7_Pos 14\r
+#define AFEC_CGR_GAIN7_Msk (0x3u << AFEC_CGR_GAIN7_Pos) /**< \brief (AFEC_CGR) Gain for channel 7 */\r
+#define AFEC_CGR_GAIN7(value) ((AFEC_CGR_GAIN7_Msk & ((value) << AFEC_CGR_GAIN7_Pos)))\r
+#define AFEC_CGR_GAIN8_Pos 16\r
+#define AFEC_CGR_GAIN8_Msk (0x3u << AFEC_CGR_GAIN8_Pos) /**< \brief (AFEC_CGR) Gain for channel 8 */\r
+#define AFEC_CGR_GAIN8(value) ((AFEC_CGR_GAIN8_Msk & ((value) << AFEC_CGR_GAIN8_Pos)))\r
+#define AFEC_CGR_GAIN9_Pos 18\r
+#define AFEC_CGR_GAIN9_Msk (0x3u << AFEC_CGR_GAIN9_Pos) /**< \brief (AFEC_CGR) Gain for channel 9 */\r
+#define AFEC_CGR_GAIN9(value) ((AFEC_CGR_GAIN9_Msk & ((value) << AFEC_CGR_GAIN9_Pos)))\r
+#define AFEC_CGR_GAIN10_Pos 20\r
+#define AFEC_CGR_GAIN10_Msk (0x3u << AFEC_CGR_GAIN10_Pos) /**< \brief (AFEC_CGR) Gain for channel 10 */\r
+#define AFEC_CGR_GAIN10(value) ((AFEC_CGR_GAIN10_Msk & ((value) << AFEC_CGR_GAIN10_Pos)))\r
+#define AFEC_CGR_GAIN11_Pos 22\r
+#define AFEC_CGR_GAIN11_Msk (0x3u << AFEC_CGR_GAIN11_Pos) /**< \brief (AFEC_CGR) Gain for channel 11 */\r
+#define AFEC_CGR_GAIN11(value) ((AFEC_CGR_GAIN11_Msk & ((value) << AFEC_CGR_GAIN11_Pos)))\r
+#define AFEC_CGR_GAIN12_Pos 24\r
+#define AFEC_CGR_GAIN12_Msk (0x3u << AFEC_CGR_GAIN12_Pos) /**< \brief (AFEC_CGR) Gain for channel 12 */\r
+#define AFEC_CGR_GAIN12(value) ((AFEC_CGR_GAIN12_Msk & ((value) << AFEC_CGR_GAIN12_Pos)))\r
+#define AFEC_CGR_GAIN13_Pos 26\r
+#define AFEC_CGR_GAIN13_Msk (0x3u << AFEC_CGR_GAIN13_Pos) /**< \brief (AFEC_CGR) Gain for channel 13 */\r
+#define AFEC_CGR_GAIN13(value) ((AFEC_CGR_GAIN13_Msk & ((value) << AFEC_CGR_GAIN13_Pos)))\r
+#define AFEC_CGR_GAIN14_Pos 28\r
+#define AFEC_CGR_GAIN14_Msk (0x3u << AFEC_CGR_GAIN14_Pos) /**< \brief (AFEC_CGR) Gain for channel 14 */\r
+#define AFEC_CGR_GAIN14(value) ((AFEC_CGR_GAIN14_Msk & ((value) << AFEC_CGR_GAIN14_Pos)))\r
+#define AFEC_CGR_GAIN15_Pos 30\r
+#define AFEC_CGR_GAIN15_Msk (0x3u << AFEC_CGR_GAIN15_Pos) /**< \brief (AFEC_CGR) Gain for channel 15 */\r
+#define AFEC_CGR_GAIN15(value) ((AFEC_CGR_GAIN15_Msk & ((value) << AFEC_CGR_GAIN15_Pos)))\r
+/* -------- AFEC_CDOR : (AFEC Offset: 0x5C) Channel Calibration DC Offset Register -------- */\r
+#define AFEC_CDOR_OFF0 (0x1u << 0) /**< \brief (AFEC_CDOR) Offset for channel 0, used in automatic calibration procedure */\r
+#define AFEC_CDOR_OFF1 (0x1u << 1) /**< \brief (AFEC_CDOR) Offset for channel 1, used in automatic calibration procedure */\r
+#define AFEC_CDOR_OFF2 (0x1u << 2) /**< \brief (AFEC_CDOR) Offset for channel 2, used in automatic calibration procedure */\r
+#define AFEC_CDOR_OFF3 (0x1u << 3) /**< \brief (AFEC_CDOR) Offset for channel 3, used in automatic calibration procedure */\r
+#define AFEC_CDOR_OFF4 (0x1u << 4) /**< \brief (AFEC_CDOR) Offset for channel 4, used in automatic calibration procedure */\r
+#define AFEC_CDOR_OFF5 (0x1u << 5) /**< \brief (AFEC_CDOR) Offset for channel 5, used in automatic calibration procedure */\r
+#define AFEC_CDOR_OFF6 (0x1u << 6) /**< \brief (AFEC_CDOR) Offset for channel 6, used in automatic calibration procedure */\r
+#define AFEC_CDOR_OFF7 (0x1u << 7) /**< \brief (AFEC_CDOR) Offset for channel 7, used in automatic calibration procedure */\r
+#define AFEC_CDOR_OFF8 (0x1u << 8) /**< \brief (AFEC_CDOR) Offset for channel 8, used in automatic calibration procedure */\r
+#define AFEC_CDOR_OFF9 (0x1u << 9) /**< \brief (AFEC_CDOR) Offset for channel 9, used in automatic calibration procedure */\r
+#define AFEC_CDOR_OFF10 (0x1u << 10) /**< \brief (AFEC_CDOR) Offset for channel 10, used in automatic calibration procedure */\r
+#define AFEC_CDOR_OFF11 (0x1u << 11) /**< \brief (AFEC_CDOR) Offset for channel 11, used in automatic calibration procedure */\r
+#define AFEC_CDOR_OFF12 (0x1u << 12) /**< \brief (AFEC_CDOR) Offset for channel 12, used in automatic calibration procedure */\r
+#define AFEC_CDOR_OFF13 (0x1u << 13) /**< \brief (AFEC_CDOR) Offset for channel 13, used in automatic calibration procedure */\r
+#define AFEC_CDOR_OFF14 (0x1u << 14) /**< \brief (AFEC_CDOR) Offset for channel 14, used in automatic calibration procedure */\r
+#define AFEC_CDOR_OFF15 (0x1u << 15) /**< \brief (AFEC_CDOR) Offset for channel 15, used in automatic calibration procedure */\r
+/* -------- AFEC_DIFFR : (AFEC Offset: 0x60) Channel Differential Register -------- */\r
+#define AFEC_DIFFR_DIFF0 (0x1u << 0) /**< \brief (AFEC_DIFFR) Differential inputs for channel 0 */\r
+#define AFEC_DIFFR_DIFF1 (0x1u << 1) /**< \brief (AFEC_DIFFR) Differential inputs for channel 1 */\r
+#define AFEC_DIFFR_DIFF2 (0x1u << 2) /**< \brief (AFEC_DIFFR) Differential inputs for channel 2 */\r
+#define AFEC_DIFFR_DIFF3 (0x1u << 3) /**< \brief (AFEC_DIFFR) Differential inputs for channel 3 */\r
+#define AFEC_DIFFR_DIFF4 (0x1u << 4) /**< \brief (AFEC_DIFFR) Differential inputs for channel 4 */\r
+#define AFEC_DIFFR_DIFF5 (0x1u << 5) /**< \brief (AFEC_DIFFR) Differential inputs for channel 5 */\r
+#define AFEC_DIFFR_DIFF6 (0x1u << 6) /**< \brief (AFEC_DIFFR) Differential inputs for channel 6 */\r
+#define AFEC_DIFFR_DIFF7 (0x1u << 7) /**< \brief (AFEC_DIFFR) Differential inputs for channel 7 */\r
+#define AFEC_DIFFR_DIFF8 (0x1u << 8) /**< \brief (AFEC_DIFFR) Differential inputs for channel 8 */\r
+#define AFEC_DIFFR_DIFF9 (0x1u << 9) /**< \brief (AFEC_DIFFR) Differential inputs for channel 9 */\r
+#define AFEC_DIFFR_DIFF10 (0x1u << 10) /**< \brief (AFEC_DIFFR) Differential inputs for channel 10 */\r
+#define AFEC_DIFFR_DIFF11 (0x1u << 11) /**< \brief (AFEC_DIFFR) Differential inputs for channel 11 */\r
+#define AFEC_DIFFR_DIFF12 (0x1u << 12) /**< \brief (AFEC_DIFFR) Differential inputs for channel 12 */\r
+#define AFEC_DIFFR_DIFF13 (0x1u << 13) /**< \brief (AFEC_DIFFR) Differential inputs for channel 13 */\r
+#define AFEC_DIFFR_DIFF14 (0x1u << 14) /**< \brief (AFEC_DIFFR) Differential inputs for channel 14 */\r
+#define AFEC_DIFFR_DIFF15 (0x1u << 15) /**< \brief (AFEC_DIFFR) Differential inputs for channel 15 */\r
+/* -------- AFEC_CSELR : (AFEC Offset: 0x64) Channel Register Selection -------- */\r
+#define AFEC_CSELR_CSEL_Pos 0\r
+#define AFEC_CSELR_CSEL_Msk (0xfu << AFEC_CSELR_CSEL_Pos) /**< \brief (AFEC_CSELR) Channel Selection */\r
+#define AFEC_CSELR_CSEL(value) ((AFEC_CSELR_CSEL_Msk & ((value) << AFEC_CSELR_CSEL_Pos)))\r
+/* -------- AFEC_CDR : (AFEC Offset: 0x68) Channel Data Register -------- */\r
+#define AFEC_CDR_DATA_Pos 0\r
+#define AFEC_CDR_DATA_Msk (0xfffu << AFEC_CDR_DATA_Pos) /**< \brief (AFEC_CDR) Converted Data */\r
+/* -------- AFEC_COCR : (AFEC Offset: 0x6C) Channel Offset Compensation Register -------- */\r
+#define AFEC_COCR_AOFF_Pos 0\r
+#define AFEC_COCR_AOFF_Msk (0xfffu << AFEC_COCR_AOFF_Pos) /**< \brief (AFEC_COCR) Analog Offset */\r
+#define AFEC_COCR_AOFF(value) ((AFEC_COCR_AOFF_Msk & ((value) << AFEC_COCR_AOFF_Pos)))\r
+/* -------- AFEC_TEMPMR : (AFEC Offset: 0x70) Temperature Sensor Mode Register -------- */\r
+#define AFEC_TEMPMR_RTCT (0x1u << 0) /**< \brief (AFEC_TEMPMR) Temperature Sensor RTC Trigger mode */\r
+#define AFEC_TEMPMR_TEMPCMPMOD_Pos 4\r
+#define AFEC_TEMPMR_TEMPCMPMOD_Msk (0x3u << AFEC_TEMPMR_TEMPCMPMOD_Pos) /**< \brief (AFEC_TEMPMR) Temperature Comparison Mode */\r
+#define AFEC_TEMPMR_TEMPCMPMOD_LOW (0x0u << 4) /**< \brief (AFEC_TEMPMR) Generates an event when the converted data is lower than the low threshold of the window. */\r
+#define AFEC_TEMPMR_TEMPCMPMOD_HIGH (0x1u << 4) /**< \brief (AFEC_TEMPMR) Generates an event when the converted data is higher than the high threshold of the window. */\r
+#define AFEC_TEMPMR_TEMPCMPMOD_IN (0x2u << 4) /**< \brief (AFEC_TEMPMR) Generates an event when the converted data is in the comparison window. */\r
+#define AFEC_TEMPMR_TEMPCMPMOD_OUT (0x3u << 4) /**< \brief (AFEC_TEMPMR) Generates an event when the converted data is out of the comparison window. */\r
+/* -------- AFEC_TEMPCWR : (AFEC Offset: 0x74) Temperature Compare Window Register -------- */\r
+#define AFEC_TEMPCWR_TLOWTHRES_Pos 0\r
+#define AFEC_TEMPCWR_TLOWTHRES_Msk (0xffffu << AFEC_TEMPCWR_TLOWTHRES_Pos) /**< \brief (AFEC_TEMPCWR) Temperature Low Threshold */\r
+#define AFEC_TEMPCWR_TLOWTHRES(value) ((AFEC_TEMPCWR_TLOWTHRES_Msk & ((value) << AFEC_TEMPCWR_TLOWTHRES_Pos)))\r
+#define AFEC_TEMPCWR_THIGHTHRES_Pos 16\r
+#define AFEC_TEMPCWR_THIGHTHRES_Msk (0xffffu << AFEC_TEMPCWR_THIGHTHRES_Pos) /**< \brief (AFEC_TEMPCWR) Temperature High Threshold */\r
+#define AFEC_TEMPCWR_THIGHTHRES(value) ((AFEC_TEMPCWR_THIGHTHRES_Msk & ((value) << AFEC_TEMPCWR_THIGHTHRES_Pos)))\r
+/* -------- AFEC_ACR : (AFEC Offset: 0x94) Analog Control Register -------- */\r
+#define AFEC_ACR_IBCTL_Pos 8\r
+#define AFEC_ACR_IBCTL_Msk (0x3u << AFEC_ACR_IBCTL_Pos) /**< \brief (AFEC_ACR) AFEC Bias Current Control */\r
+#define AFEC_ACR_IBCTL(value) ((AFEC_ACR_IBCTL_Msk & ((value) << AFEC_ACR_IBCTL_Pos)))\r
+/* -------- AFEC_WPMR : (AFEC Offset: 0xE4) Write Protect Mode Register -------- */\r
+#define AFEC_WPMR_WPEN (0x1u << 0) /**< \brief (AFEC_WPMR) Write Protect Enable */\r
+#define AFEC_WPMR_WPKEY_Pos 8\r
+#define AFEC_WPMR_WPKEY_Msk (0xffffffu << AFEC_WPMR_WPKEY_Pos) /**< \brief (AFEC_WPMR) Write Protect KEY */\r
+#define AFEC_WPMR_WPKEY_ADC (0x414443u << 8) /**< \brief (AFEC_WPMR) Should be written at value 0x414443 ("ADC" in ASCII). Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */\r
+/* -------- AFEC_WPSR : (AFEC Offset: 0xE8) Write Protect Status Register -------- */\r
+#define AFEC_WPSR_WPVS (0x1u << 0) /**< \brief (AFEC_WPSR) Write Protect Violation Status */\r
+#define AFEC_WPSR_WPVSRC_Pos 8\r
+#define AFEC_WPSR_WPVSRC_Msk (0xffffu << AFEC_WPSR_WPVSRC_Pos) /**< \brief (AFEC_WPSR) Write Protect Violation Source */\r
+/* -------- AFEC_RPR : (AFEC Offset: 0x100) Receive Pointer Register -------- */\r
+#define AFEC_RPR_RXPTR_Pos 0\r
+#define AFEC_RPR_RXPTR_Msk (0xffffffffu << AFEC_RPR_RXPTR_Pos) /**< \brief (AFEC_RPR) Receive Pointer Register */\r
+#define AFEC_RPR_RXPTR(value) ((AFEC_RPR_RXPTR_Msk & ((value) << AFEC_RPR_RXPTR_Pos)))\r
+/* -------- AFEC_RCR : (AFEC Offset: 0x104) Receive Counter Register -------- */\r
+#define AFEC_RCR_RXCTR_Pos 0\r
+#define AFEC_RCR_RXCTR_Msk (0xffffu << AFEC_RCR_RXCTR_Pos) /**< \brief (AFEC_RCR) Receive Counter Register */\r
+#define AFEC_RCR_RXCTR(value) ((AFEC_RCR_RXCTR_Msk & ((value) << AFEC_RCR_RXCTR_Pos)))\r
+/* -------- AFEC_RNPR : (AFEC Offset: 0x110) Receive Next Pointer Register -------- */\r
+#define AFEC_RNPR_RXNPTR_Pos 0\r
+#define AFEC_RNPR_RXNPTR_Msk (0xffffffffu << AFEC_RNPR_RXNPTR_Pos) /**< \brief (AFEC_RNPR) Receive Next Pointer */\r
+#define AFEC_RNPR_RXNPTR(value) ((AFEC_RNPR_RXNPTR_Msk & ((value) << AFEC_RNPR_RXNPTR_Pos)))\r
+/* -------- AFEC_RNCR : (AFEC Offset: 0x114) Receive Next Counter Register -------- */\r
+#define AFEC_RNCR_RXNCTR_Pos 0\r
+#define AFEC_RNCR_RXNCTR_Msk (0xffffu << AFEC_RNCR_RXNCTR_Pos) /**< \brief (AFEC_RNCR) Receive Next Counter */\r
+#define AFEC_RNCR_RXNCTR(value) ((AFEC_RNCR_RXNCTR_Msk & ((value) << AFEC_RNCR_RXNCTR_Pos)))\r
+/* -------- AFEC_PTCR : (AFEC Offset: 0x120) Transfer Control Register -------- */\r
+#define AFEC_PTCR_RXTEN (0x1u << 0) /**< \brief (AFEC_PTCR) Receiver Transfer Enable */\r
+#define AFEC_PTCR_RXTDIS (0x1u << 1) /**< \brief (AFEC_PTCR) Receiver Transfer Disable */\r
+#define AFEC_PTCR_TXTEN (0x1u << 8) /**< \brief (AFEC_PTCR) Transmitter Transfer Enable */\r
+#define AFEC_PTCR_TXTDIS (0x1u << 9) /**< \brief (AFEC_PTCR) Transmitter Transfer Disable */\r
+/* -------- AFEC_PTSR : (AFEC Offset: 0x124) Transfer Status Register -------- */\r
+#define AFEC_PTSR_RXTEN (0x1u << 0) /**< \brief (AFEC_PTSR) Receiver Transfer Enable */\r
+#define AFEC_PTSR_TXTEN (0x1u << 8) /**< \brief (AFEC_PTSR) Transmitter Transfer Enable */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM4E_AFEC_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4E_CAN_COMPONENT_\r
+#define _SAM4E_CAN_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Controller Area Network */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM4E_CAN Controller Area Network */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief CanMb hardware registers */\r
+typedef struct {\r
+ RwReg CAN_MMR; /**< \brief (CanMb Offset: 0x0) Mailbox Mode Register */\r
+ RwReg CAN_MAM; /**< \brief (CanMb Offset: 0x4) Mailbox Acceptance Mask Register */\r
+ RwReg CAN_MID; /**< \brief (CanMb Offset: 0x8) Mailbox ID Register */\r
+ RwReg CAN_MFID; /**< \brief (CanMb Offset: 0xC) Mailbox Family ID Register */\r
+ RwReg CAN_MSR; /**< \brief (CanMb Offset: 0x10) Mailbox Status Register */\r
+ RwReg CAN_MDL; /**< \brief (CanMb Offset: 0x14) Mailbox Data Low Register */\r
+ RwReg CAN_MDH; /**< \brief (CanMb Offset: 0x18) Mailbox Data High Register */\r
+ RwReg CAN_MCR; /**< \brief (CanMb Offset: 0x1C) Mailbox Control Register */\r
+} CanMb;\r
+/** \brief Can hardware registers */\r
+#define CANMB_NUMBER 8\r
+typedef struct {\r
+ RwReg CAN_MR; /**< \brief (Can Offset: 0x0000) Mode Register */\r
+ WoReg CAN_IER; /**< \brief (Can Offset: 0x0004) Interrupt Enable Register */\r
+ WoReg CAN_IDR; /**< \brief (Can Offset: 0x0008) Interrupt Disable Register */\r
+ RoReg CAN_IMR; /**< \brief (Can Offset: 0x000C) Interrupt Mask Register */\r
+ RoReg CAN_SR; /**< \brief (Can Offset: 0x0010) Status Register */\r
+ RwReg CAN_BR; /**< \brief (Can Offset: 0x0014) Baudrate Register */\r
+ RoReg CAN_TIM; /**< \brief (Can Offset: 0x0018) Timer Register */\r
+ RoReg CAN_TIMESTP; /**< \brief (Can Offset: 0x001C) Timestamp Register */\r
+ RoReg CAN_ECR; /**< \brief (Can Offset: 0x0020) Error Counter Register */\r
+ WoReg CAN_TCR; /**< \brief (Can Offset: 0x0024) Transfer Command Register */\r
+ WoReg CAN_ACR; /**< \brief (Can Offset: 0x0028) Abort Command Register */\r
+ RoReg Reserved1[46];\r
+ RwReg CAN_WPMR; /**< \brief (Can Offset: 0x00E4) Write Protect Mode Register */\r
+ RoReg CAN_WPSR; /**< \brief (Can Offset: 0x00E8) Write Protect Status Register */\r
+ RoReg Reserved2[69];\r
+ CanMb CAN_MB[CANMB_NUMBER]; /**< \brief (Can Offset: 0x200) MB = 0 .. 7 */\r
+} Can;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- CAN_MR : (CAN Offset: 0x0000) Mode Register -------- */\r
+#define CAN_MR_CANEN (0x1u << 0) /**< \brief (CAN_MR) CAN Controller Enable */\r
+#define CAN_MR_LPM (0x1u << 1) /**< \brief (CAN_MR) Disable/Enable Low Power Mode */\r
+#define CAN_MR_ABM (0x1u << 2) /**< \brief (CAN_MR) Disable/Enable Autobaud/Listen mode */\r
+#define CAN_MR_OVL (0x1u << 3) /**< \brief (CAN_MR) Disable/Enable Overload Frame */\r
+#define CAN_MR_TEOF (0x1u << 4) /**< \brief (CAN_MR) Timestamp messages at each end of Frame */\r
+#define CAN_MR_TTM (0x1u << 5) /**< \brief (CAN_MR) Disable/Enable Time Triggered Mode */\r
+#define CAN_MR_TIMFRZ (0x1u << 6) /**< \brief (CAN_MR) Enable Timer Freeze */\r
+#define CAN_MR_DRPT (0x1u << 7) /**< \brief (CAN_MR) Disable Repeat */\r
+/* -------- CAN_IER : (CAN Offset: 0x0004) Interrupt Enable Register -------- */\r
+#define CAN_IER_MB0 (0x1u << 0) /**< \brief (CAN_IER) Mailbox 0 Interrupt Enable */\r
+#define CAN_IER_MB1 (0x1u << 1) /**< \brief (CAN_IER) Mailbox 1 Interrupt Enable */\r
+#define CAN_IER_MB2 (0x1u << 2) /**< \brief (CAN_IER) Mailbox 2 Interrupt Enable */\r
+#define CAN_IER_MB3 (0x1u << 3) /**< \brief (CAN_IER) Mailbox 3 Interrupt Enable */\r
+#define CAN_IER_MB4 (0x1u << 4) /**< \brief (CAN_IER) Mailbox 4 Interrupt Enable */\r
+#define CAN_IER_MB5 (0x1u << 5) /**< \brief (CAN_IER) Mailbox 5 Interrupt Enable */\r
+#define CAN_IER_MB6 (0x1u << 6) /**< \brief (CAN_IER) Mailbox 6 Interrupt Enable */\r
+#define CAN_IER_MB7 (0x1u << 7) /**< \brief (CAN_IER) Mailbox 7 Interrupt Enable */\r
+#define CAN_IER_ERRA (0x1u << 16) /**< \brief (CAN_IER) Error Active Mode Interrupt Enable */\r
+#define CAN_IER_WARN (0x1u << 17) /**< \brief (CAN_IER) Warning Limit Interrupt Enable */\r
+#define CAN_IER_ERRP (0x1u << 18) /**< \brief (CAN_IER) Error Passive Mode Interrupt Enable */\r
+#define CAN_IER_BOFF (0x1u << 19) /**< \brief (CAN_IER) Bus Off Mode Interrupt Enable */\r
+#define CAN_IER_SLEEP (0x1u << 20) /**< \brief (CAN_IER) Sleep Interrupt Enable */\r
+#define CAN_IER_WAKEUP (0x1u << 21) /**< \brief (CAN_IER) Wakeup Interrupt Enable */\r
+#define CAN_IER_TOVF (0x1u << 22) /**< \brief (CAN_IER) Timer Overflow Interrupt Enable */\r
+#define CAN_IER_TSTP (0x1u << 23) /**< \brief (CAN_IER) TimeStamp Interrupt Enable */\r
+#define CAN_IER_CERR (0x1u << 24) /**< \brief (CAN_IER) CRC Error Interrupt Enable */\r
+#define CAN_IER_SERR (0x1u << 25) /**< \brief (CAN_IER) Stuffing Error Interrupt Enable */\r
+#define CAN_IER_AERR (0x1u << 26) /**< \brief (CAN_IER) Acknowledgment Error Interrupt Enable */\r
+#define CAN_IER_FERR (0x1u << 27) /**< \brief (CAN_IER) Form Error Interrupt Enable */\r
+#define CAN_IER_BERR (0x1u << 28) /**< \brief (CAN_IER) Bit Error Interrupt Enable */\r
+/* -------- CAN_IDR : (CAN Offset: 0x0008) Interrupt Disable Register -------- */\r
+#define CAN_IDR_MB0 (0x1u << 0) /**< \brief (CAN_IDR) Mailbox 0 Interrupt Disable */\r
+#define CAN_IDR_MB1 (0x1u << 1) /**< \brief (CAN_IDR) Mailbox 1 Interrupt Disable */\r
+#define CAN_IDR_MB2 (0x1u << 2) /**< \brief (CAN_IDR) Mailbox 2 Interrupt Disable */\r
+#define CAN_IDR_MB3 (0x1u << 3) /**< \brief (CAN_IDR) Mailbox 3 Interrupt Disable */\r
+#define CAN_IDR_MB4 (0x1u << 4) /**< \brief (CAN_IDR) Mailbox 4 Interrupt Disable */\r
+#define CAN_IDR_MB5 (0x1u << 5) /**< \brief (CAN_IDR) Mailbox 5 Interrupt Disable */\r
+#define CAN_IDR_MB6 (0x1u << 6) /**< \brief (CAN_IDR) Mailbox 6 Interrupt Disable */\r
+#define CAN_IDR_MB7 (0x1u << 7) /**< \brief (CAN_IDR) Mailbox 7 Interrupt Disable */\r
+#define CAN_IDR_ERRA (0x1u << 16) /**< \brief (CAN_IDR) Error Active Mode Interrupt Disable */\r
+#define CAN_IDR_WARN (0x1u << 17) /**< \brief (CAN_IDR) Warning Limit Interrupt Disable */\r
+#define CAN_IDR_ERRP (0x1u << 18) /**< \brief (CAN_IDR) Error Passive Mode Interrupt Disable */\r
+#define CAN_IDR_BOFF (0x1u << 19) /**< \brief (CAN_IDR) Bus Off Mode Interrupt Disable */\r
+#define CAN_IDR_SLEEP (0x1u << 20) /**< \brief (CAN_IDR) Sleep Interrupt Disable */\r
+#define CAN_IDR_WAKEUP (0x1u << 21) /**< \brief (CAN_IDR) Wakeup Interrupt Disable */\r
+#define CAN_IDR_TOVF (0x1u << 22) /**< \brief (CAN_IDR) Timer Overflow Interrupt */\r
+#define CAN_IDR_TSTP (0x1u << 23) /**< \brief (CAN_IDR) TimeStamp Interrupt Disable */\r
+#define CAN_IDR_CERR (0x1u << 24) /**< \brief (CAN_IDR) CRC Error Interrupt Disable */\r
+#define CAN_IDR_SERR (0x1u << 25) /**< \brief (CAN_IDR) Stuffing Error Interrupt Disable */\r
+#define CAN_IDR_AERR (0x1u << 26) /**< \brief (CAN_IDR) Acknowledgment Error Interrupt Disable */\r
+#define CAN_IDR_FERR (0x1u << 27) /**< \brief (CAN_IDR) Form Error Interrupt Disable */\r
+#define CAN_IDR_BERR (0x1u << 28) /**< \brief (CAN_IDR) Bit Error Interrupt Disable */\r
+/* -------- CAN_IMR : (CAN Offset: 0x000C) Interrupt Mask Register -------- */\r
+#define CAN_IMR_MB0 (0x1u << 0) /**< \brief (CAN_IMR) Mailbox 0 Interrupt Mask */\r
+#define CAN_IMR_MB1 (0x1u << 1) /**< \brief (CAN_IMR) Mailbox 1 Interrupt Mask */\r
+#define CAN_IMR_MB2 (0x1u << 2) /**< \brief (CAN_IMR) Mailbox 2 Interrupt Mask */\r
+#define CAN_IMR_MB3 (0x1u << 3) /**< \brief (CAN_IMR) Mailbox 3 Interrupt Mask */\r
+#define CAN_IMR_MB4 (0x1u << 4) /**< \brief (CAN_IMR) Mailbox 4 Interrupt Mask */\r
+#define CAN_IMR_MB5 (0x1u << 5) /**< \brief (CAN_IMR) Mailbox 5 Interrupt Mask */\r
+#define CAN_IMR_MB6 (0x1u << 6) /**< \brief (CAN_IMR) Mailbox 6 Interrupt Mask */\r
+#define CAN_IMR_MB7 (0x1u << 7) /**< \brief (CAN_IMR) Mailbox 7 Interrupt Mask */\r
+#define CAN_IMR_ERRA (0x1u << 16) /**< \brief (CAN_IMR) Error Active Mode Interrupt Mask */\r
+#define CAN_IMR_WARN (0x1u << 17) /**< \brief (CAN_IMR) Warning Limit Interrupt Mask */\r
+#define CAN_IMR_ERRP (0x1u << 18) /**< \brief (CAN_IMR) Error Passive Mode Interrupt Mask */\r
+#define CAN_IMR_BOFF (0x1u << 19) /**< \brief (CAN_IMR) Bus Off Mode Interrupt Mask */\r
+#define CAN_IMR_SLEEP (0x1u << 20) /**< \brief (CAN_IMR) Sleep Interrupt Mask */\r
+#define CAN_IMR_WAKEUP (0x1u << 21) /**< \brief (CAN_IMR) Wakeup Interrupt Mask */\r
+#define CAN_IMR_TOVF (0x1u << 22) /**< \brief (CAN_IMR) Timer Overflow Interrupt Mask */\r
+#define CAN_IMR_TSTP (0x1u << 23) /**< \brief (CAN_IMR) Timestamp Interrupt Mask */\r
+#define CAN_IMR_CERR (0x1u << 24) /**< \brief (CAN_IMR) CRC Error Interrupt Mask */\r
+#define CAN_IMR_SERR (0x1u << 25) /**< \brief (CAN_IMR) Stuffing Error Interrupt Mask */\r
+#define CAN_IMR_AERR (0x1u << 26) /**< \brief (CAN_IMR) Acknowledgment Error Interrupt Mask */\r
+#define CAN_IMR_FERR (0x1u << 27) /**< \brief (CAN_IMR) Form Error Interrupt Mask */\r
+#define CAN_IMR_BERR (0x1u << 28) /**< \brief (CAN_IMR) Bit Error Interrupt Mask */\r
+/* -------- CAN_SR : (CAN Offset: 0x0010) Status Register -------- */\r
+#define CAN_SR_MB0 (0x1u << 0) /**< \brief (CAN_SR) Mailbox 0 Event */\r
+#define CAN_SR_MB1 (0x1u << 1) /**< \brief (CAN_SR) Mailbox 1 Event */\r
+#define CAN_SR_MB2 (0x1u << 2) /**< \brief (CAN_SR) Mailbox 2 Event */\r
+#define CAN_SR_MB3 (0x1u << 3) /**< \brief (CAN_SR) Mailbox 3 Event */\r
+#define CAN_SR_MB4 (0x1u << 4) /**< \brief (CAN_SR) Mailbox 4 Event */\r
+#define CAN_SR_MB5 (0x1u << 5) /**< \brief (CAN_SR) Mailbox 5 Event */\r
+#define CAN_SR_MB6 (0x1u << 6) /**< \brief (CAN_SR) Mailbox 6 Event */\r
+#define CAN_SR_MB7 (0x1u << 7) /**< \brief (CAN_SR) Mailbox 7 Event */\r
+#define CAN_SR_ERRA (0x1u << 16) /**< \brief (CAN_SR) Error Active Mode */\r
+#define CAN_SR_WARN (0x1u << 17) /**< \brief (CAN_SR) Warning Limit */\r
+#define CAN_SR_ERRP (0x1u << 18) /**< \brief (CAN_SR) Error Passive Mode */\r
+#define CAN_SR_BOFF (0x1u << 19) /**< \brief (CAN_SR) Bus Off Mode */\r
+#define CAN_SR_SLEEP (0x1u << 20) /**< \brief (CAN_SR) CAN controller in Low power Mode */\r
+#define CAN_SR_WAKEUP (0x1u << 21) /**< \brief (CAN_SR) CAN controller is not in Low power Mode */\r
+#define CAN_SR_TOVF (0x1u << 22) /**< \brief (CAN_SR) Timer Overflow */\r
+#define CAN_SR_TSTP (0x1u << 23) /**< \brief (CAN_SR) */\r
+#define CAN_SR_CERR (0x1u << 24) /**< \brief (CAN_SR) Mailbox CRC Error */\r
+#define CAN_SR_SERR (0x1u << 25) /**< \brief (CAN_SR) Mailbox Stuffing Error */\r
+#define CAN_SR_AERR (0x1u << 26) /**< \brief (CAN_SR) Acknowledgment Error */\r
+#define CAN_SR_FERR (0x1u << 27) /**< \brief (CAN_SR) Form Error */\r
+#define CAN_SR_BERR (0x1u << 28) /**< \brief (CAN_SR) Bit Error */\r
+#define CAN_SR_RBSY (0x1u << 29) /**< \brief (CAN_SR) Receiver busy */\r
+#define CAN_SR_TBSY (0x1u << 30) /**< \brief (CAN_SR) Transmitter busy */\r
+#define CAN_SR_OVLSY (0x1u << 31) /**< \brief (CAN_SR) Overload busy */\r
+/* -------- CAN_BR : (CAN Offset: 0x0014) Baudrate Register -------- */\r
+#define CAN_BR_PHASE2_Pos 0\r
+#define CAN_BR_PHASE2_Msk (0x7u << CAN_BR_PHASE2_Pos) /**< \brief (CAN_BR) Phase 2 segment */\r
+#define CAN_BR_PHASE2(value) ((CAN_BR_PHASE2_Msk & ((value) << CAN_BR_PHASE2_Pos)))\r
+#define CAN_BR_PHASE1_Pos 4\r
+#define CAN_BR_PHASE1_Msk (0x7u << CAN_BR_PHASE1_Pos) /**< \brief (CAN_BR) Phase 1 segment */\r
+#define CAN_BR_PHASE1(value) ((CAN_BR_PHASE1_Msk & ((value) << CAN_BR_PHASE1_Pos)))\r
+#define CAN_BR_PROPAG_Pos 8\r
+#define CAN_BR_PROPAG_Msk (0x7u << CAN_BR_PROPAG_Pos) /**< \brief (CAN_BR) Programming time segment */\r
+#define CAN_BR_PROPAG(value) ((CAN_BR_PROPAG_Msk & ((value) << CAN_BR_PROPAG_Pos)))\r
+#define CAN_BR_SJW_Pos 12\r
+#define CAN_BR_SJW_Msk (0x3u << CAN_BR_SJW_Pos) /**< \brief (CAN_BR) Re-synchronization jump width */\r
+#define CAN_BR_SJW(value) ((CAN_BR_SJW_Msk & ((value) << CAN_BR_SJW_Pos)))\r
+#define CAN_BR_BRP_Pos 16\r
+#define CAN_BR_BRP_Msk (0x7fu << CAN_BR_BRP_Pos) /**< \brief (CAN_BR) Baudrate Prescaler. */\r
+#define CAN_BR_BRP(value) ((CAN_BR_BRP_Msk & ((value) << CAN_BR_BRP_Pos)))\r
+#define CAN_BR_SMP (0x1u << 24) /**< \brief (CAN_BR) Sampling Mode */\r
+#define CAN_BR_SMP_ONCE (0x0u << 24) /**< \brief (CAN_BR) The incoming bit stream is sampled once at sample point. */\r
+#define CAN_BR_SMP_THREE (0x1u << 24) /**< \brief (CAN_BR) The incoming bit stream is sampled three times with a period of a MCK clock period, centered on sample point. */\r
+/* -------- CAN_TIM : (CAN Offset: 0x0018) Timer Register -------- */\r
+#define CAN_TIM_TIMER_Pos 0\r
+#define CAN_TIM_TIMER_Msk (0xffffu << CAN_TIM_TIMER_Pos) /**< \brief (CAN_TIM) Timer */\r
+/* -------- CAN_TIMESTP : (CAN Offset: 0x001C) Timestamp Register -------- */\r
+#define CAN_TIMESTP_MTIMESTAMP_Pos 0\r
+#define CAN_TIMESTP_MTIMESTAMP_Msk (0xffffu << CAN_TIMESTP_MTIMESTAMP_Pos) /**< \brief (CAN_TIMESTP) Timestamp */\r
+/* -------- CAN_ECR : (CAN Offset: 0x0020) Error Counter Register -------- */\r
+#define CAN_ECR_REC_Pos 0\r
+#define CAN_ECR_REC_Msk (0xffu << CAN_ECR_REC_Pos) /**< \brief (CAN_ECR) Receive Error Counter */\r
+#define CAN_ECR_TEC_Pos 16\r
+#define CAN_ECR_TEC_Msk (0x1ffu << CAN_ECR_TEC_Pos) /**< \brief (CAN_ECR) Transmit Error Counter */\r
+/* -------- CAN_TCR : (CAN Offset: 0x0024) Transfer Command Register -------- */\r
+#define CAN_TCR_MB0 (0x1u << 0) /**< \brief (CAN_TCR) Transfer Request for Mailbox 0 */\r
+#define CAN_TCR_MB1 (0x1u << 1) /**< \brief (CAN_TCR) Transfer Request for Mailbox 1 */\r
+#define CAN_TCR_MB2 (0x1u << 2) /**< \brief (CAN_TCR) Transfer Request for Mailbox 2 */\r
+#define CAN_TCR_MB3 (0x1u << 3) /**< \brief (CAN_TCR) Transfer Request for Mailbox 3 */\r
+#define CAN_TCR_MB4 (0x1u << 4) /**< \brief (CAN_TCR) Transfer Request for Mailbox 4 */\r
+#define CAN_TCR_MB5 (0x1u << 5) /**< \brief (CAN_TCR) Transfer Request for Mailbox 5 */\r
+#define CAN_TCR_MB6 (0x1u << 6) /**< \brief (CAN_TCR) Transfer Request for Mailbox 6 */\r
+#define CAN_TCR_MB7 (0x1u << 7) /**< \brief (CAN_TCR) Transfer Request for Mailbox 7 */\r
+#define CAN_TCR_TIMRST (0x1u << 31) /**< \brief (CAN_TCR) Timer Reset */\r
+/* -------- CAN_ACR : (CAN Offset: 0x0028) Abort Command Register -------- */\r
+#define CAN_ACR_MB0 (0x1u << 0) /**< \brief (CAN_ACR) Abort Request for Mailbox 0 */\r
+#define CAN_ACR_MB1 (0x1u << 1) /**< \brief (CAN_ACR) Abort Request for Mailbox 1 */\r
+#define CAN_ACR_MB2 (0x1u << 2) /**< \brief (CAN_ACR) Abort Request for Mailbox 2 */\r
+#define CAN_ACR_MB3 (0x1u << 3) /**< \brief (CAN_ACR) Abort Request for Mailbox 3 */\r
+#define CAN_ACR_MB4 (0x1u << 4) /**< \brief (CAN_ACR) Abort Request for Mailbox 4 */\r
+#define CAN_ACR_MB5 (0x1u << 5) /**< \brief (CAN_ACR) Abort Request for Mailbox 5 */\r
+#define CAN_ACR_MB6 (0x1u << 6) /**< \brief (CAN_ACR) Abort Request for Mailbox 6 */\r
+#define CAN_ACR_MB7 (0x1u << 7) /**< \brief (CAN_ACR) Abort Request for Mailbox 7 */\r
+/* -------- CAN_WPMR : (CAN Offset: 0x00E4) Write Protect Mode Register -------- */\r
+#define CAN_WPMR_WPEN (0x1u << 0) /**< \brief (CAN_WPMR) Write Protection Enable */\r
+#define CAN_WPMR_WPKEY_Pos 8\r
+#define CAN_WPMR_WPKEY_Msk (0xffffffu << CAN_WPMR_WPKEY_Pos) /**< \brief (CAN_WPMR) SPI Write Protection Key Password */\r
+#define CAN_WPMR_WPKEY(value) ((CAN_WPMR_WPKEY_Msk & ((value) << CAN_WPMR_WPKEY_Pos)))\r
+/* -------- CAN_WPSR : (CAN Offset: 0x00E8) Write Protect Status Register -------- */\r
+#define CAN_WPSR_WPVS (0x1u << 0) /**< \brief (CAN_WPSR) Write Protection Violation Status */\r
+#define CAN_WPSR_WPVSRC_Pos 8\r
+#define CAN_WPSR_WPVSRC_Msk (0xffu << CAN_WPSR_WPVSRC_Pos) /**< \brief (CAN_WPSR) Write Protection Violation Source */\r
+/* -------- CAN_MMR : (CAN Offset: N/A) Mailbox Mode Register -------- */\r
+#define CAN_MMR_MTIMEMARK_Pos 0\r
+#define CAN_MMR_MTIMEMARK_Msk (0xffffu << CAN_MMR_MTIMEMARK_Pos) /**< \brief (CAN_MMR) Mailbox Timemark */\r
+#define CAN_MMR_MTIMEMARK(value) ((CAN_MMR_MTIMEMARK_Msk & ((value) << CAN_MMR_MTIMEMARK_Pos)))\r
+#define CAN_MMR_PRIOR_Pos 16\r
+#define CAN_MMR_PRIOR_Msk (0xfu << CAN_MMR_PRIOR_Pos) /**< \brief (CAN_MMR) Mailbox Priority */\r
+#define CAN_MMR_PRIOR(value) ((CAN_MMR_PRIOR_Msk & ((value) << CAN_MMR_PRIOR_Pos)))\r
+#define CAN_MMR_MOT_Pos 24\r
+#define CAN_MMR_MOT_Msk (0x7u << CAN_MMR_MOT_Pos) /**< \brief (CAN_MMR) Mailbox Object Type */\r
+#define CAN_MMR_MOT_MB_DISABLED (0x0u << 24) /**< \brief (CAN_MMR) Mailbox is disabled. This prevents receiving or transmitting any messages with this mailbox. */\r
+#define CAN_MMR_MOT_MB_RX (0x1u << 24) /**< \brief (CAN_MMR) Reception Mailbox. Mailbox is configured for reception. If a message is received while the mailbox data register is full, it is discarded. */\r
+#define CAN_MMR_MOT_MB_RX_OVERWRITE (0x2u << 24) /**< \brief (CAN_MMR) Reception mailbox with overwrite. Mailbox is configured for reception. If a message is received while the mailbox is full, it overwrites the previous message. */\r
+#define CAN_MMR_MOT_MB_TX (0x3u << 24) /**< \brief (CAN_MMR) Transmit mailbox. Mailbox is configured for transmission. */\r
+#define CAN_MMR_MOT_MB_CONSUMER (0x4u << 24) /**< \brief (CAN_MMR) Consumer Mailbox. Mailbox is configured in reception but behaves as a Transmit Mailbox, i.e., it sends a remote frame and waits for an answer. */\r
+#define CAN_MMR_MOT_MB_PRODUCER (0x5u << 24) /**< \brief (CAN_MMR) Producer Mailbox. Mailbox is configured in transmission but also behaves like a reception mailbox, i.e., it waits to receive a Remote Frame before sending its contents. */\r
+/* -------- CAN_MAM : (CAN Offset: N/A) Mailbox Acceptance Mask Register -------- */\r
+#define CAN_MAM_MIDvB_Pos 0\r
+#define CAN_MAM_MIDvB_Msk (0x3ffffu << CAN_MAM_MIDvB_Pos) /**< \brief (CAN_MAM) Complementary bits for identifier in extended frame mode */\r
+#define CAN_MAM_MIDvB(value) ((CAN_MAM_MIDvB_Msk & ((value) << CAN_MAM_MIDvB_Pos)))\r
+#define CAN_MAM_MIDvA_Pos 18\r
+#define CAN_MAM_MIDvA_Msk (0x7ffu << CAN_MAM_MIDvA_Pos) /**< \brief (CAN_MAM) Identifier for standard frame mode */\r
+#define CAN_MAM_MIDvA(value) ((CAN_MAM_MIDvA_Msk & ((value) << CAN_MAM_MIDvA_Pos)))\r
+#define CAN_MAM_MIDE (0x1u << 29) /**< \brief (CAN_MAM) Identifier Version */\r
+/* -------- CAN_MID : (CAN Offset: N/A) Mailbox ID Register -------- */\r
+#define CAN_MID_MIDvB_Pos 0\r
+#define CAN_MID_MIDvB_Msk (0x3ffffu << CAN_MID_MIDvB_Pos) /**< \brief (CAN_MID) Complementary bits for identifier in extended frame mode */\r
+#define CAN_MID_MIDvB(value) ((CAN_MID_MIDvB_Msk & ((value) << CAN_MID_MIDvB_Pos)))\r
+#define CAN_MID_MIDvA_Pos 18\r
+#define CAN_MID_MIDvA_Msk (0x7ffu << CAN_MID_MIDvA_Pos) /**< \brief (CAN_MID) Identifier for standard frame mode */\r
+#define CAN_MID_MIDvA(value) ((CAN_MID_MIDvA_Msk & ((value) << CAN_MID_MIDvA_Pos)))\r
+#define CAN_MID_MIDE (0x1u << 29) /**< \brief (CAN_MID) Identifier Version */\r
+/* -------- CAN_MFID : (CAN Offset: N/A) Mailbox Family ID Register -------- */\r
+#define CAN_MFID_MFID_Pos 0\r
+#define CAN_MFID_MFID_Msk (0x1fffffffu << CAN_MFID_MFID_Pos) /**< \brief (CAN_MFID) Family ID */\r
+/* -------- CAN_MSR : (CAN Offset: N/A) Mailbox Status Register -------- */\r
+#define CAN_MSR_MTIMESTAMP_Pos 0\r
+#define CAN_MSR_MTIMESTAMP_Msk (0xffffu << CAN_MSR_MTIMESTAMP_Pos) /**< \brief (CAN_MSR) Timer value */\r
+#define CAN_MSR_MDLC_Pos 16\r
+#define CAN_MSR_MDLC_Msk (0xfu << CAN_MSR_MDLC_Pos) /**< \brief (CAN_MSR) Mailbox Data Length Code */\r
+#define CAN_MSR_MRTR (0x1u << 20) /**< \brief (CAN_MSR) Mailbox Remote Transmission Request */\r
+#define CAN_MSR_MABT (0x1u << 22) /**< \brief (CAN_MSR) Mailbox Message Abort */\r
+#define CAN_MSR_MRDY (0x1u << 23) /**< \brief (CAN_MSR) Mailbox Ready */\r
+#define CAN_MSR_MMI (0x1u << 24) /**< \brief (CAN_MSR) Mailbox Message Ignored */\r
+/* -------- CAN_MDL : (CAN Offset: N/A) Mailbox Data Low Register -------- */\r
+#define CAN_MDL_MDL_Pos 0\r
+#define CAN_MDL_MDL_Msk (0xffffffffu << CAN_MDL_MDL_Pos) /**< \brief (CAN_MDL) Message Data Low Value */\r
+#define CAN_MDL_MDL(value) ((CAN_MDL_MDL_Msk & ((value) << CAN_MDL_MDL_Pos)))\r
+/* -------- CAN_MDH : (CAN Offset: N/A) Mailbox Data High Register -------- */\r
+#define CAN_MDH_MDH_Pos 0\r
+#define CAN_MDH_MDH_Msk (0xffffffffu << CAN_MDH_MDH_Pos) /**< \brief (CAN_MDH) Message Data High Value */\r
+#define CAN_MDH_MDH(value) ((CAN_MDH_MDH_Msk & ((value) << CAN_MDH_MDH_Pos)))\r
+/* -------- CAN_MCR : (CAN Offset: N/A) Mailbox Control Register -------- */\r
+#define CAN_MCR_MDLC_Pos 16\r
+#define CAN_MCR_MDLC_Msk (0xfu << CAN_MCR_MDLC_Pos) /**< \brief (CAN_MCR) Mailbox Data Length Code */\r
+#define CAN_MCR_MDLC(value) ((CAN_MCR_MDLC_Msk & ((value) << CAN_MCR_MDLC_Pos)))\r
+#define CAN_MCR_MRTR (0x1u << 20) /**< \brief (CAN_MCR) Mailbox Remote Transmission Request */\r
+#define CAN_MCR_MACR (0x1u << 22) /**< \brief (CAN_MCR) Abort Request for Mailbox x */\r
+#define CAN_MCR_MTCR (0x1u << 23) /**< \brief (CAN_MCR) Mailbox Transfer Command */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM4E_CAN_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4E_CHIPID_COMPONENT_\r
+#define _SAM4E_CHIPID_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Chip Identifier */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM4E_CHIPID Chip Identifier */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Chipid hardware registers */\r
+typedef struct {\r
+ RoReg CHIPID_CIDR; /**< \brief (Chipid Offset: 0x0) Chip ID Register */\r
+ RoReg CHIPID_EXID; /**< \brief (Chipid Offset: 0x4) Chip ID Extension Register */\r
+} Chipid;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- CHIPID_CIDR : (CHIPID Offset: 0x0) Chip ID Register -------- */\r
+#define CHIPID_CIDR_VERSION_Pos 0\r
+#define CHIPID_CIDR_VERSION_Msk (0x1fu << CHIPID_CIDR_VERSION_Pos) /**< \brief (CHIPID_CIDR) Version of the Device */\r
+#define CHIPID_CIDR_EPROC_Pos 5\r
+#define CHIPID_CIDR_EPROC_Msk (0x7u << CHIPID_CIDR_EPROC_Pos) /**< \brief (CHIPID_CIDR) Embedded Processor */\r
+#define CHIPID_CIDR_EPROC_ARM946ES (0x1u << 5) /**< \brief (CHIPID_CIDR) ARM946ES */\r
+#define CHIPID_CIDR_EPROC_ARM7TDMI (0x2u << 5) /**< \brief (CHIPID_CIDR) ARM7TDMI */\r
+#define CHIPID_CIDR_EPROC_CM3 (0x3u << 5) /**< \brief (CHIPID_CIDR) Cortex-M3 */\r
+#define CHIPID_CIDR_EPROC_ARM920T (0x4u << 5) /**< \brief (CHIPID_CIDR) ARM920T */\r
+#define CHIPID_CIDR_EPROC_ARM926EJS (0x5u << 5) /**< \brief (CHIPID_CIDR) ARM926EJS */\r
+#define CHIPID_CIDR_EPROC_CA5 (0x6u << 5) /**< \brief (CHIPID_CIDR) Cortex-A5 */\r
+#define CHIPID_CIDR_EPROC_CM4 (0x7u << 5) /**< \brief (CHIPID_CIDR) Cortex-M4 */\r
+#define CHIPID_CIDR_NVPSIZ_Pos 8\r
+#define CHIPID_CIDR_NVPSIZ_Msk (0xfu << CHIPID_CIDR_NVPSIZ_Pos) /**< \brief (CHIPID_CIDR) Nonvolatile Program Memory Size */\r
+#define CHIPID_CIDR_NVPSIZ_NONE (0x0u << 8) /**< \brief (CHIPID_CIDR) None */\r
+#define CHIPID_CIDR_NVPSIZ_8K (0x1u << 8) /**< \brief (CHIPID_CIDR) 8 Kbytes */\r
+#define CHIPID_CIDR_NVPSIZ_16K (0x2u << 8) /**< \brief (CHIPID_CIDR) 16 Kbytes */\r
+#define CHIPID_CIDR_NVPSIZ_32K (0x3u << 8) /**< \brief (CHIPID_CIDR) 32 Kbytes */\r
+#define CHIPID_CIDR_NVPSIZ_64K (0x5u << 8) /**< \brief (CHIPID_CIDR) 64 Kbytes */\r
+#define CHIPID_CIDR_NVPSIZ_128K (0x7u << 8) /**< \brief (CHIPID_CIDR) 128 Kbytes */\r
+#define CHIPID_CIDR_NVPSIZ_256K (0x9u << 8) /**< \brief (CHIPID_CIDR) 256 Kbytes */\r
+#define CHIPID_CIDR_NVPSIZ_512K (0xAu << 8) /**< \brief (CHIPID_CIDR) 512 Kbytes */\r
+#define CHIPID_CIDR_NVPSIZ_1024K (0xCu << 8) /**< \brief (CHIPID_CIDR) 1024 Kbytes */\r
+#define CHIPID_CIDR_NVPSIZ_2048K (0xEu << 8) /**< \brief (CHIPID_CIDR) 2048 Kbytes */\r
+#define CHIPID_CIDR_NVPSIZ2_Pos 12\r
+#define CHIPID_CIDR_NVPSIZ2_Msk (0xfu << CHIPID_CIDR_NVPSIZ2_Pos) /**< \brief (CHIPID_CIDR) Second Nonvolatile Program Memory Size */\r
+#define CHIPID_CIDR_NVPSIZ2_NONE (0x0u << 12) /**< \brief (CHIPID_CIDR) None */\r
+#define CHIPID_CIDR_NVPSIZ2_8K (0x1u << 12) /**< \brief (CHIPID_CIDR) 8 Kbytes */\r
+#define CHIPID_CIDR_NVPSIZ2_16K (0x2u << 12) /**< \brief (CHIPID_CIDR) 16 Kbytes */\r
+#define CHIPID_CIDR_NVPSIZ2_32K (0x3u << 12) /**< \brief (CHIPID_CIDR) 32 Kbytes */\r
+#define CHIPID_CIDR_NVPSIZ2_64K (0x5u << 12) /**< \brief (CHIPID_CIDR) 64 Kbytes */\r
+#define CHIPID_CIDR_NVPSIZ2_128K (0x7u << 12) /**< \brief (CHIPID_CIDR) 128 Kbytes */\r
+#define CHIPID_CIDR_NVPSIZ2_256K (0x9u << 12) /**< \brief (CHIPID_CIDR) 256 Kbytes */\r
+#define CHIPID_CIDR_NVPSIZ2_512K (0xAu << 12) /**< \brief (CHIPID_CIDR) 512 Kbytes */\r
+#define CHIPID_CIDR_NVPSIZ2_1024K (0xCu << 12) /**< \brief (CHIPID_CIDR) 1024 Kbytes */\r
+#define CHIPID_CIDR_NVPSIZ2_2048K (0xEu << 12) /**< \brief (CHIPID_CIDR) 2048 Kbytes */\r
+#define CHIPID_CIDR_SRAMSIZ_Pos 16\r
+#define CHIPID_CIDR_SRAMSIZ_Msk (0xfu << CHIPID_CIDR_SRAMSIZ_Pos) /**< \brief (CHIPID_CIDR) Internal SRAM Size */\r
+#define CHIPID_CIDR_SRAMSIZ_48K (0x0u << 16) /**< \brief (CHIPID_CIDR) 48 Kbytes */\r
+#define CHIPID_CIDR_SRAMSIZ_192K (0x1u << 16) /**< \brief (CHIPID_CIDR) 192 Kbytes */\r
+#define CHIPID_CIDR_SRAMSIZ_2K (0x2u << 16) /**< \brief (CHIPID_CIDR) 2 Kbytes */\r
+#define CHIPID_CIDR_SRAMSIZ_6K (0x3u << 16) /**< \brief (CHIPID_CIDR) 6 Kbytes */\r
+#define CHIPID_CIDR_SRAMSIZ_24K (0x4u << 16) /**< \brief (CHIPID_CIDR) 24 Kbytes */\r
+#define CHIPID_CIDR_SRAMSIZ_4K (0x5u << 16) /**< \brief (CHIPID_CIDR) 4 Kbytes */\r
+#define CHIPID_CIDR_SRAMSIZ_80K (0x6u << 16) /**< \brief (CHIPID_CIDR) 80 Kbytes */\r
+#define CHIPID_CIDR_SRAMSIZ_160K (0x7u << 16) /**< \brief (CHIPID_CIDR) 160 Kbytes */\r
+#define CHIPID_CIDR_SRAMSIZ_8K (0x8u << 16) /**< \brief (CHIPID_CIDR) 8 Kbytes */\r
+#define CHIPID_CIDR_SRAMSIZ_16K (0x9u << 16) /**< \brief (CHIPID_CIDR) 16 Kbytes */\r
+#define CHIPID_CIDR_SRAMSIZ_32K (0xAu << 16) /**< \brief (CHIPID_CIDR) 32 Kbytes */\r
+#define CHIPID_CIDR_SRAMSIZ_64K (0xBu << 16) /**< \brief (CHIPID_CIDR) 64 Kbytes */\r
+#define CHIPID_CIDR_SRAMSIZ_128K (0xCu << 16) /**< \brief (CHIPID_CIDR) 128 Kbytes */\r
+#define CHIPID_CIDR_SRAMSIZ_256K (0xDu << 16) /**< \brief (CHIPID_CIDR) 256 Kbytes */\r
+#define CHIPID_CIDR_SRAMSIZ_96K (0xEu << 16) /**< \brief (CHIPID_CIDR) 96 Kbytes */\r
+#define CHIPID_CIDR_SRAMSIZ_512K (0xFu << 16) /**< \brief (CHIPID_CIDR) 512 Kbytes */\r
+#define CHIPID_CIDR_ARCH_Pos 20\r
+#define CHIPID_CIDR_ARCH_Msk (0xffu << CHIPID_CIDR_ARCH_Pos) /**< \brief (CHIPID_CIDR) Architecture Identifier */\r
+#define CHIPID_CIDR_ARCH_AT91SAM9xx (0x19u << 20) /**< \brief (CHIPID_CIDR) AT91SAM9xx Series */\r
+#define CHIPID_CIDR_ARCH_AT91SAM9XExx (0x29u << 20) /**< \brief (CHIPID_CIDR) AT91SAM9XExx Series */\r
+#define CHIPID_CIDR_ARCH_AT91x34 (0x34u << 20) /**< \brief (CHIPID_CIDR) AT91x34 Series */\r
+#define CHIPID_CIDR_ARCH_CAP7 (0x37u << 20) /**< \brief (CHIPID_CIDR) CAP7 Series */\r
+#define CHIPID_CIDR_ARCH_CAP9 (0x39u << 20) /**< \brief (CHIPID_CIDR) CAP9 Series */\r
+#define CHIPID_CIDR_ARCH_CAP11 (0x3Bu << 20) /**< \brief (CHIPID_CIDR) CAP11 Series */\r
+#define CHIPID_CIDR_ARCH_SAM4E (0x3Cu << 20) /**< \brief (CHIPID_CIDR) SAM4E Series */\r
+#define CHIPID_CIDR_ARCH_AT91x40 (0x40u << 20) /**< \brief (CHIPID_CIDR) AT91x40 Series */\r
+#define CHIPID_CIDR_ARCH_AT91x42 (0x42u << 20) /**< \brief (CHIPID_CIDR) AT91x42 Series */\r
+#define CHIPID_CIDR_ARCH_AT91x55 (0x55u << 20) /**< \brief (CHIPID_CIDR) AT91x55 Series */\r
+#define CHIPID_CIDR_ARCH_AT91SAM7Axx (0x60u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7Axx Series */\r
+#define CHIPID_CIDR_ARCH_AT91SAM7AQxx (0x61u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7AQxx Series */\r
+#define CHIPID_CIDR_ARCH_AT91x63 (0x63u << 20) /**< \brief (CHIPID_CIDR) AT91x63 Series */\r
+#define CHIPID_CIDR_ARCH_AT91SAM7Sxx (0x70u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7Sxx Series */\r
+#define CHIPID_CIDR_ARCH_AT91SAM7XCxx (0x71u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7XCxx Series */\r
+#define CHIPID_CIDR_ARCH_AT91SAM7SExx (0x72u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7SExx Series */\r
+#define CHIPID_CIDR_ARCH_AT91SAM7Lxx (0x73u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7Lxx Series */\r
+#define CHIPID_CIDR_ARCH_AT91SAM7Xxx (0x75u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7Xxx Series */\r
+#define CHIPID_CIDR_ARCH_AT91SAM7SLxx (0x76u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7SLxx Series */\r
+#define CHIPID_CIDR_ARCH_SAM3UxC (0x80u << 20) /**< \brief (CHIPID_CIDR) SAM3UxC Series (100-pin version) */\r
+#define CHIPID_CIDR_ARCH_SAM3UxE (0x81u << 20) /**< \brief (CHIPID_CIDR) SAM3UxE Series (144-pin version) */\r
+#define CHIPID_CIDR_ARCH_SAM3AxC (0x83u << 20) /**< \brief (CHIPID_CIDR) SAM3AxC Series (100-pin version) */\r
+#define CHIPID_CIDR_ARCH_SAM3XxC (0x84u << 20) /**< \brief (CHIPID_CIDR) SAM3XxC Series (100-pin version) */\r
+#define CHIPID_CIDR_ARCH_SAM3XxE (0x85u << 20) /**< \brief (CHIPID_CIDR) SAM3XxE Series (144-pin version) */\r
+#define CHIPID_CIDR_ARCH_SAM3XxG (0x86u << 20) /**< \brief (CHIPID_CIDR) SAM3XxG Series (208/217-pin version) */\r
+#define CHIPID_CIDR_ARCH_AT91x92 (0x92u << 20) /**< \brief (CHIPID_CIDR) AT91x92 Series */\r
+#define CHIPID_CIDR_ARCH_SAM3SDxB (0x99u << 20) /**< \brief (CHIPID_CIDR) SAM3SDxB Series (64-pin version) */\r
+#define CHIPID_CIDR_ARCH_SAM3SDxC (0x9Au << 20) /**< \brief (CHIPID_CIDR) SAM3SDxC Series (100-pin version) */\r
+#define CHIPID_CIDR_ARCH_SAM5A (0xA5u << 20) /**< \brief (CHIPID_CIDR) SAM5A */\r
+#define CHIPID_CIDR_ARCH_SAM4LxA (0xB0u << 20) /**< \brief (CHIPID_CIDR) SAM4LxA Series (48-pin version) */\r
+#define CHIPID_CIDR_ARCH_SAM4LxB (0xB1u << 20) /**< \brief (CHIPID_CIDR) SAM4LxB Series (64-pin version) */\r
+#define CHIPID_CIDR_ARCH_SAM4LxC (0xB2u << 20) /**< \brief (CHIPID_CIDR) SAM4LxC Series (100-pin version) */\r
+#define CHIPID_CIDR_ARCH_AT75Cxx (0xF0u << 20) /**< \brief (CHIPID_CIDR) AT75Cxx Series */\r
+#define CHIPID_CIDR_NVPTYP_Pos 28\r
+#define CHIPID_CIDR_NVPTYP_Msk (0x7u << CHIPID_CIDR_NVPTYP_Pos) /**< \brief (CHIPID_CIDR) Nonvolatile Program Memory Type */\r
+#define CHIPID_CIDR_NVPTYP_ROM (0x0u << 28) /**< \brief (CHIPID_CIDR) ROM */\r
+#define CHIPID_CIDR_NVPTYP_ROMLESS (0x1u << 28) /**< \brief (CHIPID_CIDR) ROMless or on-chip Flash */\r
+#define CHIPID_CIDR_NVPTYP_FLASH (0x2u << 28) /**< \brief (CHIPID_CIDR) Embedded Flash Memory */\r
+#define CHIPID_CIDR_NVPTYP_ROM_FLASH (0x3u << 28) /**< \brief (CHIPID_CIDR) ROM and Embedded Flash MemoryNVPSIZ is ROM size NVPSIZ2 is Flash size */\r
+#define CHIPID_CIDR_NVPTYP_SRAM (0x4u << 28) /**< \brief (CHIPID_CIDR) SRAM emulating ROM */\r
+#define CHIPID_CIDR_EXT (0x1u << 31) /**< \brief (CHIPID_CIDR) Extension Flag */\r
+/* -------- CHIPID_EXID : (CHIPID Offset: 0x4) Chip ID Extension Register -------- */\r
+#define CHIPID_EXID_EXID_Pos 0\r
+#define CHIPID_EXID_EXID_Msk (0xffffffffu << CHIPID_EXID_EXID_Pos) /**< \brief (CHIPID_EXID) Chip ID Extension */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM4E_CHIPID_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4E_CMCC_COMPONENT_\r
+#define _SAM4E_CMCC_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Cortex M Cache Controller */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM4E_CMCC Cortex M Cache Controller */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Cmcc hardware registers */\r
+typedef struct {\r
+ RoReg CMCC_TYPE; /**< \brief (Cmcc Offset: 0x00) Cache Type Register */\r
+ RwReg CMCC_CFG; /**< \brief (Cmcc Offset: 0x04) Cache Configuration Register */\r
+ WoReg CMCC_CTRL; /**< \brief (Cmcc Offset: 0x08) Cache Control Register */\r
+ RoReg CMCC_SR; /**< \brief (Cmcc Offset: 0x0C) Cache Status Register */\r
+ RoReg Reserved1[4];\r
+ WoReg CMCC_MAINT0; /**< \brief (Cmcc Offset: 0x20) Cache Maintenance Register 0 */\r
+ WoReg CMCC_MAINT1; /**< \brief (Cmcc Offset: 0x24) Cache Maintenance Register 1 */\r
+ RwReg CMCC_MCFG; /**< \brief (Cmcc Offset: 0x28) Cache Monitor Configuration Register */\r
+ RwReg CMCC_MEN; /**< \brief (Cmcc Offset: 0x2C) Cache Monitor Enable Register */\r
+ WoReg CMCC_MCTRL; /**< \brief (Cmcc Offset: 0x30) Cache Monitor Control Register */\r
+ RoReg CMCC_MSR; /**< \brief (Cmcc Offset: 0x34) Cache Monitor Status Register */\r
+} Cmcc;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- CMCC_TYPE : (CMCC Offset: 0x00) Cache Type Register -------- */\r
+#define CMCC_TYPE_AP (0x1u << 0) /**< \brief (CMCC_TYPE) Access Port Access Allowed */\r
+#define CMCC_TYPE_GCLK (0x1u << 1) /**< \brief (CMCC_TYPE) Dynamic Clock Gating Supported */\r
+#define CMCC_TYPE_RANDP (0x1u << 2) /**< \brief (CMCC_TYPE) Random Selection Policy Supported */\r
+#define CMCC_TYPE_LRUP (0x1u << 3) /**< \brief (CMCC_TYPE) Least Recently Used Policy Supported */\r
+#define CMCC_TYPE_RRP (0x1u << 4) /**< \brief (CMCC_TYPE) Random Selection Policy Supported */\r
+#define CMCC_TYPE_WAYNUM_Pos 5\r
+#define CMCC_TYPE_WAYNUM_Msk (0x3u << CMCC_TYPE_WAYNUM_Pos) /**< \brief (CMCC_TYPE) Number of Way */\r
+#define CMCC_TYPE_WAYNUM_DMAPPED (0x0u << 5) /**< \brief (CMCC_TYPE) Direct Mapped Cache */\r
+#define CMCC_TYPE_WAYNUM_ARCH2WAY (0x1u << 5) /**< \brief (CMCC_TYPE) 2-WAY set associative */\r
+#define CMCC_TYPE_WAYNUM_ARCH4WAY (0x2u << 5) /**< \brief (CMCC_TYPE) 4-WAY set associative */\r
+#define CMCC_TYPE_WAYNUM_ARCH8WAY (0x3u << 5) /**< \brief (CMCC_TYPE) 8-WAY set associative */\r
+#define CMCC_TYPE_LCKDOWN (0x1u << 7) /**< \brief (CMCC_TYPE) Lock Down Supported */\r
+#define CMCC_TYPE_CSIZE_Pos 8\r
+#define CMCC_TYPE_CSIZE_Msk (0x7u << CMCC_TYPE_CSIZE_Pos) /**< \brief (CMCC_TYPE) Cache Size */\r
+#define CMCC_TYPE_CSIZE_CSIZE_1KB (0x0u << 8) /**< \brief (CMCC_TYPE) Cache Size 1 Kbytes */\r
+#define CMCC_TYPE_CSIZE_CSIZE_2KB (0x1u << 8) /**< \brief (CMCC_TYPE) Cache Size 2 Kbytes */\r
+#define CMCC_TYPE_CSIZE_CSIZE_4KB (0x2u << 8) /**< \brief (CMCC_TYPE) Cache Size 4 Kbytes */\r
+#define CMCC_TYPE_CSIZE_CSIZE_8KB (0x3u << 8) /**< \brief (CMCC_TYPE) Cache Size 8 Kbytes */\r
+#define CMCC_TYPE_CLSIZE_Pos 11\r
+#define CMCC_TYPE_CLSIZE_Msk (0x7u << CMCC_TYPE_CLSIZE_Pos) /**< \brief (CMCC_TYPE) Cache Size */\r
+#define CMCC_TYPE_CLSIZE_CLSIZE_1KB (0x0u << 11) /**< \brief (CMCC_TYPE) 4 bytes */\r
+#define CMCC_TYPE_CLSIZE_CLSIZE_2KB (0x1u << 11) /**< \brief (CMCC_TYPE) 8 bytes */\r
+#define CMCC_TYPE_CLSIZE_CLSIZE_4KB (0x2u << 11) /**< \brief (CMCC_TYPE) 16 bytes */\r
+#define CMCC_TYPE_CLSIZE_CLSIZE_8KB (0x3u << 11) /**< \brief (CMCC_TYPE) 32 bytes */\r
+/* -------- CMCC_CFG : (CMCC Offset: 0x04) Cache Configuration Register -------- */\r
+#define CMCC_CFG_GCLKDIS (0x1u << 0) /**< \brief (CMCC_CFG) Disable Clock Gating */\r
+/* -------- CMCC_CTRL : (CMCC Offset: 0x08) Cache Control Register -------- */\r
+#define CMCC_CTRL_CEN (0x1u << 0) /**< \brief (CMCC_CTRL) Cache Controller Enable */\r
+/* -------- CMCC_SR : (CMCC Offset: 0x0C) Cache Status Register -------- */\r
+#define CMCC_SR_CSTS (0x1u << 0) /**< \brief (CMCC_SR) Cache Controller Status */\r
+/* -------- CMCC_MAINT0 : (CMCC Offset: 0x20) Cache Maintenance Register 0 -------- */\r
+#define CMCC_MAINT0_INVALL (0x1u << 0) /**< \brief (CMCC_MAINT0) Cache Controller Invalidate All */\r
+/* -------- CMCC_MAINT1 : (CMCC Offset: 0x24) Cache Maintenance Register 1 -------- */\r
+#define CMCC_MAINT1_INDEX_Pos 4\r
+#define CMCC_MAINT1_INDEX_Msk (0x1fu << CMCC_MAINT1_INDEX_Pos) /**< \brief (CMCC_MAINT1) Invalidate Index */\r
+#define CMCC_MAINT1_INDEX(value) ((CMCC_MAINT1_INDEX_Msk & ((value) << CMCC_MAINT1_INDEX_Pos)))\r
+#define CMCC_MAINT1_WAY_Pos 30\r
+#define CMCC_MAINT1_WAY_Msk (0x3u << CMCC_MAINT1_WAY_Pos) /**< \brief (CMCC_MAINT1) Invalidate Way */\r
+#define CMCC_MAINT1_WAY_WAY0 (0x0u << 30) /**< \brief (CMCC_MAINT1) Way 0 is selection for index invalidation */\r
+#define CMCC_MAINT1_WAY_WAY1 (0x1u << 30) /**< \brief (CMCC_MAINT1) Way 1 is selection for index invalidation */\r
+#define CMCC_MAINT1_WAY_WAY2 (0x2u << 30) /**< \brief (CMCC_MAINT1) Way 2 is selection for index invalidation */\r
+#define CMCC_MAINT1_WAY_WAY3 (0x3u << 30) /**< \brief (CMCC_MAINT1) Way 3 is selection for index invalidation */\r
+/* -------- CMCC_MCFG : (CMCC Offset: 0x28) Cache Monitor Configuration Register -------- */\r
+#define CMCC_MCFG_MODE_Pos 0\r
+#define CMCC_MCFG_MODE_Msk (0x3u << CMCC_MCFG_MODE_Pos) /**< \brief (CMCC_MCFG) Cache Controller Monitor Counter Mode */\r
+#define CMCC_MCFG_MODE_CYCLE_COUNT (0x0u << 0) /**< \brief (CMCC_MCFG) Cycle counter */\r
+#define CMCC_MCFG_MODE_IHIT_COUNT (0x1u << 0) /**< \brief (CMCC_MCFG) Instruction hit counter */\r
+#define CMCC_MCFG_MODE_DHIT_COUNT (0x2u << 0) /**< \brief (CMCC_MCFG) Data hit counter */\r
+/* -------- CMCC_MEN : (CMCC Offset: 0x2C) Cache Monitor Enable Register -------- */\r
+#define CMCC_MEN_MENABLE (0x1u << 0) /**< \brief (CMCC_MEN) Cache Controller Monitor Enable */\r
+/* -------- CMCC_MCTRL : (CMCC Offset: 0x30) Cache Monitor Control Register -------- */\r
+#define CMCC_MCTRL_SWRST (0x1u << 0) /**< \brief (CMCC_MCTRL) Monitor */\r
+/* -------- CMCC_MSR : (CMCC Offset: 0x34) Cache Monitor Status Register -------- */\r
+#define CMCC_MSR_EVENT_CNT_Pos 0\r
+#define CMCC_MSR_EVENT_CNT_Msk (0xffffffffu << CMCC_MSR_EVENT_CNT_Pos) /**< \brief (CMCC_MSR) Monitor Event Counter */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM4E_CMCC_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4E_CRCCU_COMPONENT_\r
+#define _SAM4E_CRCCU_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Cyclic Redundancy Check Calculation Unit */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM4E_CRCCU Cyclic Redundancy Check Calculation Unit */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Crccu hardware registers */\r
+typedef struct {\r
+ RwReg CRCCU_DSCR; /**< \brief (Crccu Offset: 0x00000000) CRCCU Descriptor Base Register */\r
+ RoReg Reserved1[1];\r
+ WoReg CRCCU_DMA_EN; /**< \brief (Crccu Offset: 0x00000008) CRCCU DMA Enable Register */\r
+ WoReg CRCCU_DMA_DIS; /**< \brief (Crccu Offset: 0x0000000C) CRCCU DMA Disable Register */\r
+ RoReg CRCCU_DMA_SR; /**< \brief (Crccu Offset: 0x00000010) CRCCU DMA Status Register */\r
+ WoReg CRCCU_DMA_IER; /**< \brief (Crccu Offset: 0x00000014) CRCCU DMA Interrupt Enable Register */\r
+ WoReg CRCCU_DMA_IDR; /**< \brief (Crccu Offset: 0x00000018) CRCCU DMA Interrupt Disable Register */\r
+ RoReg CRCCU_DMA_IMR; /**< \brief (Crccu Offset: 0x0000001C) CRCCU DMA Interrupt Mask Register */\r
+ RoReg CRCCU_DMA_ISR; /**< \brief (Crccu Offset: 0x00000020) CRCCU DMA Interrupt Status Register */\r
+ RoReg Reserved2[4];\r
+ WoReg CRCCU_CR; /**< \brief (Crccu Offset: 0x00000034) CRCCU Control Register */\r
+ RwReg CRCCU_MR; /**< \brief (Crccu Offset: 0x00000038) CRCCU Mode Register */\r
+ RoReg CRCCU_SR; /**< \brief (Crccu Offset: 0x0000003C) CRCCU Status Register */\r
+ WoReg CRCCU_IER; /**< \brief (Crccu Offset: 0x00000040) CRCCU Interrupt Enable Register */\r
+ WoReg CRCCU_IDR; /**< \brief (Crccu Offset: 0x00000044) CRCCU Interrupt Disable Register */\r
+ RoReg CRCCU_IMR; /**< \brief (Crccu Offset: 0x00000048) CRCCU Interrupt Mask Register */\r
+ RoReg CRCCU_ISR; /**< \brief (Crccu Offset: 0x0000004C) CRCCU Interrupt Status Register */\r
+} Crccu;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- CRCCU_DSCR : (CRCCU Offset: 0x00000000) CRCCU Descriptor Base Register -------- */\r
+#define CRCCU_DSCR_DSCR_Pos 9\r
+#define CRCCU_DSCR_DSCR_Msk (0x7fffffu << CRCCU_DSCR_DSCR_Pos) /**< \brief (CRCCU_DSCR) Descriptor Base Address */\r
+#define CRCCU_DSCR_DSCR(value) ((CRCCU_DSCR_DSCR_Msk & ((value) << CRCCU_DSCR_DSCR_Pos)))\r
+/* -------- CRCCU_DMA_EN : (CRCCU Offset: 0x00000008) CRCCU DMA Enable Register -------- */\r
+#define CRCCU_DMA_EN_DMAEN (0x1u << 0) /**< \brief (CRCCU_DMA_EN) DMA Enable Register */\r
+/* -------- CRCCU_DMA_DIS : (CRCCU Offset: 0x0000000C) CRCCU DMA Disable Register -------- */\r
+#define CRCCU_DMA_DIS_DMADIS (0x1u << 0) /**< \brief (CRCCU_DMA_DIS) DMA Disable Register */\r
+/* -------- CRCCU_DMA_SR : (CRCCU Offset: 0x00000010) CRCCU DMA Status Register -------- */\r
+#define CRCCU_DMA_SR_DMASR (0x1u << 0) /**< \brief (CRCCU_DMA_SR) DMA Status Register */\r
+/* -------- CRCCU_DMA_IER : (CRCCU Offset: 0x00000014) CRCCU DMA Interrupt Enable Register -------- */\r
+#define CRCCU_DMA_IER_DMAIER (0x1u << 0) /**< \brief (CRCCU_DMA_IER) Interrupt Enable register */\r
+/* -------- CRCCU_DMA_IDR : (CRCCU Offset: 0x00000018) CRCCU DMA Interrupt Disable Register -------- */\r
+#define CRCCU_DMA_IDR_DMAIDR (0x1u << 0) /**< \brief (CRCCU_DMA_IDR) Interrupt Disable register */\r
+/* -------- CRCCU_DMA_IMR : (CRCCU Offset: 0x0000001C) CRCCU DMA Interrupt Mask Register -------- */\r
+#define CRCCU_DMA_IMR_DMAIMR (0x1u << 0) /**< \brief (CRCCU_DMA_IMR) Interrupt Mask Register */\r
+/* -------- CRCCU_DMA_ISR : (CRCCU Offset: 0x00000020) CRCCU DMA Interrupt Status Register -------- */\r
+#define CRCCU_DMA_ISR_DMAISR (0x1u << 0) /**< \brief (CRCCU_DMA_ISR) Interrupt Status register */\r
+/* -------- CRCCU_CR : (CRCCU Offset: 0x00000034) CRCCU Control Register -------- */\r
+#define CRCCU_CR_RESET (0x1u << 0) /**< \brief (CRCCU_CR) CRC Computation Reset */\r
+/* -------- CRCCU_MR : (CRCCU Offset: 0x00000038) CRCCU Mode Register -------- */\r
+#define CRCCU_MR_ENABLE (0x1u << 0) /**< \brief (CRCCU_MR) CRC Enable */\r
+#define CRCCU_MR_COMPARE (0x1u << 1) /**< \brief (CRCCU_MR) CRC Compare */\r
+#define CRCCU_MR_PTYPE_Pos 2\r
+#define CRCCU_MR_PTYPE_Msk (0x3u << CRCCU_MR_PTYPE_Pos) /**< \brief (CRCCU_MR) Primitive Polynomial */\r
+#define CRCCU_MR_PTYPE_CCITT8023 (0x0u << 2) /**< \brief (CRCCU_MR) Polynom 0x04C11DB7 */\r
+#define CRCCU_MR_PTYPE_CASTAGNOLI (0x1u << 2) /**< \brief (CRCCU_MR) Polynom 0x1EDC6F41 */\r
+#define CRCCU_MR_PTYPE_CCITT16 (0x2u << 2) /**< \brief (CRCCU_MR) Polynom 0x1021 */\r
+#define CRCCU_MR_DIVIDER_Pos 4\r
+#define CRCCU_MR_DIVIDER_Msk (0xfu << CRCCU_MR_DIVIDER_Pos) /**< \brief (CRCCU_MR) Request Divider */\r
+#define CRCCU_MR_DIVIDER(value) ((CRCCU_MR_DIVIDER_Msk & ((value) << CRCCU_MR_DIVIDER_Pos)))\r
+/* -------- CRCCU_SR : (CRCCU Offset: 0x0000003C) CRCCU Status Register -------- */\r
+#define CRCCU_SR_CRC_Pos 0\r
+#define CRCCU_SR_CRC_Msk (0xffffffffu << CRCCU_SR_CRC_Pos) /**< \brief (CRCCU_SR) Cyclic Redundancy Check Value */\r
+/* -------- CRCCU_IER : (CRCCU Offset: 0x00000040) CRCCU Interrupt Enable Register -------- */\r
+#define CRCCU_IER_ERRIER (0x1u << 0) /**< \brief (CRCCU_IER) CRC Error Interrupt Enable */\r
+/* -------- CRCCU_IDR : (CRCCU Offset: 0x00000044) CRCCU Interrupt Disable Register -------- */\r
+#define CRCCU_IDR_ERRIDR (0x1u << 0) /**< \brief (CRCCU_IDR) CRC Error Interrupt Disable */\r
+/* -------- CRCCU_IMR : (CRCCU Offset: 0x00000048) CRCCU Interrupt Mask Register -------- */\r
+#define CRCCU_IMR_ERRIMR (0x1u << 0) /**< \brief (CRCCU_IMR) CRC Error Interrupt Mask */\r
+/* -------- CRCCU_ISR : (CRCCU Offset: 0x0000004C) CRCCU Interrupt Status Register -------- */\r
+#define CRCCU_ISR_ERRISR (0x1u << 0) /**< \brief (CRCCU_ISR) CRC Error Interrupt Status */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM4E_CRCCU_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4E_DACC_COMPONENT_\r
+#define _SAM4E_DACC_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Digital-to-Analog Converter Controller */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM4E_DACC Digital-to-Analog Converter Controller */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Dacc hardware registers */\r
+typedef struct {\r
+ WoReg DACC_CR; /**< \brief (Dacc Offset: 0x00) Control Register */\r
+ RwReg DACC_MR; /**< \brief (Dacc Offset: 0x04) Mode Register */\r
+ RoReg Reserved1[2];\r
+ WoReg DACC_CHER; /**< \brief (Dacc Offset: 0x10) Channel Enable Register */\r
+ WoReg DACC_CHDR; /**< \brief (Dacc Offset: 0x14) Channel Disable Register */\r
+ RoReg DACC_CHSR; /**< \brief (Dacc Offset: 0x18) Channel Status Register */\r
+ RoReg Reserved2[1];\r
+ WoReg DACC_CDR; /**< \brief (Dacc Offset: 0x20) Conversion Data Register */\r
+ WoReg DACC_IER; /**< \brief (Dacc Offset: 0x24) Interrupt Enable Register */\r
+ WoReg DACC_IDR; /**< \brief (Dacc Offset: 0x28) Interrupt Disable Register */\r
+ RoReg DACC_IMR; /**< \brief (Dacc Offset: 0x2C) Interrupt Mask Register */\r
+ RoReg DACC_ISR; /**< \brief (Dacc Offset: 0x30) Interrupt Status Register */\r
+ RoReg Reserved3[24];\r
+ RwReg DACC_ACR; /**< \brief (Dacc Offset: 0x94) Analog Current Register */\r
+ RoReg Reserved4[19];\r
+ RwReg DACC_WPMR; /**< \brief (Dacc Offset: 0xE4) Write Protect Mode register */\r
+ RoReg DACC_WPSR; /**< \brief (Dacc Offset: 0xE8) Write Protect Status register */\r
+ RoReg Reserved5[7];\r
+ RwReg DACC_TPR; /**< \brief (Dacc Offset: 0x108) Transmit Pointer Register */\r
+ RwReg DACC_TCR; /**< \brief (Dacc Offset: 0x10C) Transmit Counter Register */\r
+ RoReg Reserved6[2];\r
+ RwReg DACC_TNPR; /**< \brief (Dacc Offset: 0x118) Transmit Next Pointer Register */\r
+ RwReg DACC_TNCR; /**< \brief (Dacc Offset: 0x11C) Transmit Next Counter Register */\r
+ WoReg DACC_PTCR; /**< \brief (Dacc Offset: 0x120) Transfer Control Register */\r
+ RoReg DACC_PTSR; /**< \brief (Dacc Offset: 0x124) Transfer Status Register */\r
+} Dacc;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- DACC_CR : (DACC Offset: 0x00) Control Register -------- */\r
+#define DACC_CR_SWRST (0x1u << 0) /**< \brief (DACC_CR) Software Reset */\r
+/* -------- DACC_MR : (DACC Offset: 0x04) Mode Register -------- */\r
+#define DACC_MR_TRGEN (0x1u << 0) /**< \brief (DACC_MR) Trigger Enable */\r
+#define DACC_MR_TRGEN_DIS (0x0u << 0) /**< \brief (DACC_MR) External trigger mode disabled. DACC in free running mode. */\r
+#define DACC_MR_TRGEN_EN (0x1u << 0) /**< \brief (DACC_MR) External trigger mode enabled. */\r
+#define DACC_MR_TRGSEL_Pos 1\r
+#define DACC_MR_TRGSEL_Msk (0x7u << DACC_MR_TRGSEL_Pos) /**< \brief (DACC_MR) Trigger Selection */\r
+#define DACC_MR_TRGSEL(value) ((DACC_MR_TRGSEL_Msk & ((value) << DACC_MR_TRGSEL_Pos)))\r
+#define DACC_MR_WORD (0x1u << 4) /**< \brief (DACC_MR) Word Transfer */\r
+#define DACC_MR_WORD_HALF (0x0u << 4) /**< \brief (DACC_MR) Half-Word transfer */\r
+#define DACC_MR_WORD_WORD (0x1u << 4) /**< \brief (DACC_MR) Word Transfer */\r
+#define DACC_MR_SLEEP (0x1u << 5) /**< \brief (DACC_MR) Sleep Mode */\r
+#define DACC_MR_FASTWKUP (0x1u << 6) /**< \brief (DACC_MR) Fast Wake up Mode */\r
+#define DACC_MR_REFRESH_Pos 8\r
+#define DACC_MR_REFRESH_Msk (0xffu << DACC_MR_REFRESH_Pos) /**< \brief (DACC_MR) Refresh Period */\r
+#define DACC_MR_REFRESH(value) ((DACC_MR_REFRESH_Msk & ((value) << DACC_MR_REFRESH_Pos)))\r
+#define DACC_MR_USER_SEL_Pos 16\r
+#define DACC_MR_USER_SEL_Msk (0x3u << DACC_MR_USER_SEL_Pos) /**< \brief (DACC_MR) User Channel Selection */\r
+#define DACC_MR_USER_SEL_CHANNEL0 (0x0u << 16) /**< \brief (DACC_MR) Channel 0 */\r
+#define DACC_MR_USER_SEL_CHANNEL1 (0x1u << 16) /**< \brief (DACC_MR) Channel 1 */\r
+#define DACC_MR_TAG (0x1u << 20) /**< \brief (DACC_MR) Tag Selection Mode */\r
+#define DACC_MR_TAG_DIS (0x0u << 20) /**< \brief (DACC_MR) Tag selection mode disabled. Using USER_SEL to select the channel for the conversion. */\r
+#define DACC_MR_TAG_EN (0x1u << 20) /**< \brief (DACC_MR) Tag selection mode enabled */\r
+#define DACC_MR_MAXS (0x1u << 21) /**< \brief (DACC_MR) Max Speed Mode */\r
+#define DACC_MR_MAXS_NORMAL (0x0u << 21) /**< \brief (DACC_MR) Normal Mode */\r
+#define DACC_MR_MAXS_MAXIMUM (0x1u << 21) /**< \brief (DACC_MR) Max Speed Mode enabled */\r
+#define DACC_MR_CLKDIV (0x1u << 22) /**< \brief (DACC_MR) Clock Divider */\r
+#define DACC_MR_CLKDIV_DIV_2 (0x0u << 22) /**< \brief (DACC_MR) The DAC clock is MCK divided by 2 */\r
+#define DACC_MR_CLKDIV_DIV_4 (0x1u << 22) /**< \brief (DACC_MR) The DAC clock is MCK divided by 4 (to be used when MCK frequency is above 100MHz) */\r
+#define DACC_MR_STARTUP_Pos 24\r
+#define DACC_MR_STARTUP_Msk (0x3fu << DACC_MR_STARTUP_Pos) /**< \brief (DACC_MR) Startup Time Selection */\r
+#define DACC_MR_STARTUP_0 (0x0u << 24) /**< \brief (DACC_MR) 0 periods of DACClock */\r
+#define DACC_MR_STARTUP_8 (0x1u << 24) /**< \brief (DACC_MR) 8 periods of DACClock */\r
+#define DACC_MR_STARTUP_16 (0x2u << 24) /**< \brief (DACC_MR) 16 periods of DACClock */\r
+#define DACC_MR_STARTUP_24 (0x3u << 24) /**< \brief (DACC_MR) 24 periods of DACClock */\r
+#define DACC_MR_STARTUP_64 (0x4u << 24) /**< \brief (DACC_MR) 64 periods of DACClock */\r
+#define DACC_MR_STARTUP_80 (0x5u << 24) /**< \brief (DACC_MR) 80 periods of DACClock */\r
+#define DACC_MR_STARTUP_96 (0x6u << 24) /**< \brief (DACC_MR) 96 periods of DACClock */\r
+#define DACC_MR_STARTUP_112 (0x7u << 24) /**< \brief (DACC_MR) 112 periods of DACClock */\r
+#define DACC_MR_STARTUP_512 (0x8u << 24) /**< \brief (DACC_MR) 512 periods of DACClock */\r
+#define DACC_MR_STARTUP_576 (0x9u << 24) /**< \brief (DACC_MR) 576 periods of DACClock */\r
+#define DACC_MR_STARTUP_640 (0xAu << 24) /**< \brief (DACC_MR) 640 periods of DACClock */\r
+#define DACC_MR_STARTUP_704 (0xBu << 24) /**< \brief (DACC_MR) 704 periods of DACClock */\r
+#define DACC_MR_STARTUP_768 (0xCu << 24) /**< \brief (DACC_MR) 768 periods of DACClock */\r
+#define DACC_MR_STARTUP_832 (0xDu << 24) /**< \brief (DACC_MR) 832 periods of DACClock */\r
+#define DACC_MR_STARTUP_896 (0xEu << 24) /**< \brief (DACC_MR) 896 periods of DACClock */\r
+#define DACC_MR_STARTUP_960 (0xFu << 24) /**< \brief (DACC_MR) 960 periods of DACClock */\r
+#define DACC_MR_STARTUP_1024 (0x10u << 24) /**< \brief (DACC_MR) 1024 periods of DACClock */\r
+#define DACC_MR_STARTUP_1088 (0x11u << 24) /**< \brief (DACC_MR) 1088 periods of DACClock */\r
+#define DACC_MR_STARTUP_1152 (0x12u << 24) /**< \brief (DACC_MR) 1152 periods of DACClock */\r
+#define DACC_MR_STARTUP_1216 (0x13u << 24) /**< \brief (DACC_MR) 1216 periods of DACClock */\r
+#define DACC_MR_STARTUP_1280 (0x14u << 24) /**< \brief (DACC_MR) 1280 periods of DACClock */\r
+#define DACC_MR_STARTUP_1344 (0x15u << 24) /**< \brief (DACC_MR) 1344 periods of DACClock */\r
+#define DACC_MR_STARTUP_1408 (0x16u << 24) /**< \brief (DACC_MR) 1408 periods of DACClock */\r
+#define DACC_MR_STARTUP_1472 (0x17u << 24) /**< \brief (DACC_MR) 1472 periods of DACClock */\r
+#define DACC_MR_STARTUP_1536 (0x18u << 24) /**< \brief (DACC_MR) 1536 periods of DACClock */\r
+#define DACC_MR_STARTUP_1600 (0x19u << 24) /**< \brief (DACC_MR) 1600 periods of DACClock */\r
+#define DACC_MR_STARTUP_1664 (0x1Au << 24) /**< \brief (DACC_MR) 1664 periods of DACClock */\r
+#define DACC_MR_STARTUP_1728 (0x1Bu << 24) /**< \brief (DACC_MR) 1728 periods of DACClock */\r
+#define DACC_MR_STARTUP_1792 (0x1Cu << 24) /**< \brief (DACC_MR) 1792 periods of DACClock */\r
+#define DACC_MR_STARTUP_1856 (0x1Du << 24) /**< \brief (DACC_MR) 1856 periods of DACClock */\r
+#define DACC_MR_STARTUP_1920 (0x1Eu << 24) /**< \brief (DACC_MR) 1920 periods of DACClock */\r
+#define DACC_MR_STARTUP_1984 (0x1Fu << 24) /**< \brief (DACC_MR) 1984 periods of DACClock */\r
+/* -------- DACC_CHER : (DACC Offset: 0x10) Channel Enable Register -------- */\r
+#define DACC_CHER_CH0 (0x1u << 0) /**< \brief (DACC_CHER) Channel 0 Enable */\r
+#define DACC_CHER_CH1 (0x1u << 1) /**< \brief (DACC_CHER) Channel 1 Enable */\r
+/* -------- DACC_CHDR : (DACC Offset: 0x14) Channel Disable Register -------- */\r
+#define DACC_CHDR_CH0 (0x1u << 0) /**< \brief (DACC_CHDR) Channel 0 Disable */\r
+#define DACC_CHDR_CH1 (0x1u << 1) /**< \brief (DACC_CHDR) Channel 1 Disable */\r
+/* -------- DACC_CHSR : (DACC Offset: 0x18) Channel Status Register -------- */\r
+#define DACC_CHSR_CH0 (0x1u << 0) /**< \brief (DACC_CHSR) Channel 0 Status */\r
+#define DACC_CHSR_CH1 (0x1u << 1) /**< \brief (DACC_CHSR) Channel 1 Status */\r
+/* -------- DACC_CDR : (DACC Offset: 0x20) Conversion Data Register -------- */\r
+#define DACC_CDR_DATA_Pos 0\r
+#define DACC_CDR_DATA_Msk (0xffffffffu << DACC_CDR_DATA_Pos) /**< \brief (DACC_CDR) Data to Convert */\r
+#define DACC_CDR_DATA(value) ((DACC_CDR_DATA_Msk & ((value) << DACC_CDR_DATA_Pos)))\r
+/* -------- DACC_IER : (DACC Offset: 0x24) Interrupt Enable Register -------- */\r
+#define DACC_IER_TXRDY (0x1u << 0) /**< \brief (DACC_IER) Transmit Ready Interrupt Enable */\r
+#define DACC_IER_EOC (0x1u << 1) /**< \brief (DACC_IER) End of Conversion Interrupt Enable */\r
+#define DACC_IER_ENDTX (0x1u << 2) /**< \brief (DACC_IER) End of Transmit Buffer Interrupt Enable */\r
+#define DACC_IER_TXBUFE (0x1u << 3) /**< \brief (DACC_IER) Transmit Buffer Empty Interrupt Enable */\r
+/* -------- DACC_IDR : (DACC Offset: 0x28) Interrupt Disable Register -------- */\r
+#define DACC_IDR_TXRDY (0x1u << 0) /**< \brief (DACC_IDR) Transmit Ready Interrupt Disable. */\r
+#define DACC_IDR_EOC (0x1u << 1) /**< \brief (DACC_IDR) End of Conversion Interrupt Disable */\r
+#define DACC_IDR_ENDTX (0x1u << 2) /**< \brief (DACC_IDR) End of Transmit Buffer Interrupt Disable */\r
+#define DACC_IDR_TXBUFE (0x1u << 3) /**< \brief (DACC_IDR) Transmit Buffer Empty Interrupt Disable */\r
+/* -------- DACC_IMR : (DACC Offset: 0x2C) Interrupt Mask Register -------- */\r
+#define DACC_IMR_TXRDY (0x1u << 0) /**< \brief (DACC_IMR) Transmit Ready Interrupt Mask */\r
+#define DACC_IMR_EOC (0x1u << 1) /**< \brief (DACC_IMR) End of Conversion Interrupt Mask */\r
+#define DACC_IMR_ENDTX (0x1u << 2) /**< \brief (DACC_IMR) End of Transmit Buffer Interrupt Mask */\r
+#define DACC_IMR_TXBUFE (0x1u << 3) /**< \brief (DACC_IMR) Transmit Buffer Empty Interrupt Mask */\r
+/* -------- DACC_ISR : (DACC Offset: 0x30) Interrupt Status Register -------- */\r
+#define DACC_ISR_TXRDY (0x1u << 0) /**< \brief (DACC_ISR) Transmit Ready Interrupt Flag */\r
+#define DACC_ISR_EOC (0x1u << 1) /**< \brief (DACC_ISR) End of Conversion Interrupt Flag */\r
+#define DACC_ISR_ENDTX (0x1u << 2) /**< \brief (DACC_ISR) End of DMA Interrupt Flag */\r
+#define DACC_ISR_TXBUFE (0x1u << 3) /**< \brief (DACC_ISR) Transmit Buffer Empty */\r
+/* -------- DACC_ACR : (DACC Offset: 0x94) Analog Current Register -------- */\r
+#define DACC_ACR_IBCTLCH0_Pos 0\r
+#define DACC_ACR_IBCTLCH0_Msk (0x3u << DACC_ACR_IBCTLCH0_Pos) /**< \brief (DACC_ACR) Analog Output Current Control */\r
+#define DACC_ACR_IBCTLCH0(value) ((DACC_ACR_IBCTLCH0_Msk & ((value) << DACC_ACR_IBCTLCH0_Pos)))\r
+#define DACC_ACR_IBCTLCH1_Pos 2\r
+#define DACC_ACR_IBCTLCH1_Msk (0x3u << DACC_ACR_IBCTLCH1_Pos) /**< \brief (DACC_ACR) Analog Output Current Control */\r
+#define DACC_ACR_IBCTLCH1(value) ((DACC_ACR_IBCTLCH1_Msk & ((value) << DACC_ACR_IBCTLCH1_Pos)))\r
+#define DACC_ACR_IBCTLDACCORE_Pos 8\r
+#define DACC_ACR_IBCTLDACCORE_Msk (0x3u << DACC_ACR_IBCTLDACCORE_Pos) /**< \brief (DACC_ACR) Bias Current Control for DAC Core */\r
+#define DACC_ACR_IBCTLDACCORE(value) ((DACC_ACR_IBCTLDACCORE_Msk & ((value) << DACC_ACR_IBCTLDACCORE_Pos)))\r
+/* -------- DACC_WPMR : (DACC Offset: 0xE4) Write Protect Mode register -------- */\r
+#define DACC_WPMR_WPEN (0x1u << 0) /**< \brief (DACC_WPMR) Write Protect Enable */\r
+#define DACC_WPMR_WPKEY_Pos 8\r
+#define DACC_WPMR_WPKEY_Msk (0xffffffu << DACC_WPMR_WPKEY_Pos) /**< \brief (DACC_WPMR) Write Protect KEY */\r
+#define DACC_WPMR_WPKEY(value) ((DACC_WPMR_WPKEY_Msk & ((value) << DACC_WPMR_WPKEY_Pos)))\r
+/* -------- DACC_WPSR : (DACC Offset: 0xE8) Write Protect Status register -------- */\r
+#define DACC_WPSR_WPROTERR (0x1u << 0) /**< \brief (DACC_WPSR) Write protection error */\r
+#define DACC_WPSR_WPROTADDR_Pos 8\r
+#define DACC_WPSR_WPROTADDR_Msk (0xffu << DACC_WPSR_WPROTADDR_Pos) /**< \brief (DACC_WPSR) Write protection error address */\r
+/* -------- DACC_TPR : (DACC Offset: 0x108) Transmit Pointer Register -------- */\r
+#define DACC_TPR_TXPTR_Pos 0\r
+#define DACC_TPR_TXPTR_Msk (0xffffffffu << DACC_TPR_TXPTR_Pos) /**< \brief (DACC_TPR) Transmit Counter Register */\r
+#define DACC_TPR_TXPTR(value) ((DACC_TPR_TXPTR_Msk & ((value) << DACC_TPR_TXPTR_Pos)))\r
+/* -------- DACC_TCR : (DACC Offset: 0x10C) Transmit Counter Register -------- */\r
+#define DACC_TCR_TXCTR_Pos 0\r
+#define DACC_TCR_TXCTR_Msk (0xffffu << DACC_TCR_TXCTR_Pos) /**< \brief (DACC_TCR) Transmit Counter Register */\r
+#define DACC_TCR_TXCTR(value) ((DACC_TCR_TXCTR_Msk & ((value) << DACC_TCR_TXCTR_Pos)))\r
+/* -------- DACC_TNPR : (DACC Offset: 0x118) Transmit Next Pointer Register -------- */\r
+#define DACC_TNPR_TXNPTR_Pos 0\r
+#define DACC_TNPR_TXNPTR_Msk (0xffffffffu << DACC_TNPR_TXNPTR_Pos) /**< \brief (DACC_TNPR) Transmit Next Pointer */\r
+#define DACC_TNPR_TXNPTR(value) ((DACC_TNPR_TXNPTR_Msk & ((value) << DACC_TNPR_TXNPTR_Pos)))\r
+/* -------- DACC_TNCR : (DACC Offset: 0x11C) Transmit Next Counter Register -------- */\r
+#define DACC_TNCR_TXNCTR_Pos 0\r
+#define DACC_TNCR_TXNCTR_Msk (0xffffu << DACC_TNCR_TXNCTR_Pos) /**< \brief (DACC_TNCR) Transmit Counter Next */\r
+#define DACC_TNCR_TXNCTR(value) ((DACC_TNCR_TXNCTR_Msk & ((value) << DACC_TNCR_TXNCTR_Pos)))\r
+/* -------- DACC_PTCR : (DACC Offset: 0x120) Transfer Control Register -------- */\r
+#define DACC_PTCR_RXTEN (0x1u << 0) /**< \brief (DACC_PTCR) Receiver Transfer Enable */\r
+#define DACC_PTCR_RXTDIS (0x1u << 1) /**< \brief (DACC_PTCR) Receiver Transfer Disable */\r
+#define DACC_PTCR_TXTEN (0x1u << 8) /**< \brief (DACC_PTCR) Transmitter Transfer Enable */\r
+#define DACC_PTCR_TXTDIS (0x1u << 9) /**< \brief (DACC_PTCR) Transmitter Transfer Disable */\r
+/* -------- DACC_PTSR : (DACC Offset: 0x124) Transfer Status Register -------- */\r
+#define DACC_PTSR_RXTEN (0x1u << 0) /**< \brief (DACC_PTSR) Receiver Transfer Enable */\r
+#define DACC_PTSR_TXTEN (0x1u << 8) /**< \brief (DACC_PTSR) Transmitter Transfer Enable */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM4E_DACC_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4E_DMAC_COMPONENT_\r
+#define _SAM4E_DMAC_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR DMA Controller */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM4E_DMAC DMA Controller */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief DmacCh_num hardware registers */\r
+typedef struct {\r
+ RwReg DMAC_SADDR; /**< \brief (DmacCh_num Offset: 0x0) DMAC Channel Source Address Register */\r
+ RwReg DMAC_DADDR; /**< \brief (DmacCh_num Offset: 0x4) DMAC Channel Destination Address Register */\r
+ RwReg DMAC_DSCR; /**< \brief (DmacCh_num Offset: 0x8) DMAC Channel Descriptor Address Register */\r
+ RwReg DMAC_CTRLA; /**< \brief (DmacCh_num Offset: 0xC) DMAC Channel Control A Register */\r
+ RwReg DMAC_CTRLB; /**< \brief (DmacCh_num Offset: 0x10) DMAC Channel Control B Register */\r
+ RwReg DMAC_CFG; /**< \brief (DmacCh_num Offset: 0x14) DMAC Channel Configuration Register */\r
+ RoReg Reserved1[4];\r
+} DmacCh_num;\r
+/** \brief Dmac hardware registers */\r
+#define DMACCH_NUM_NUMBER 4\r
+typedef struct {\r
+ RwReg DMAC_GCFG; /**< \brief (Dmac Offset: 0x000) DMAC Global Configuration Register */\r
+ RwReg DMAC_EN; /**< \brief (Dmac Offset: 0x004) DMAC Enable Register */\r
+ RwReg DMAC_SREQ; /**< \brief (Dmac Offset: 0x008) DMAC Software Single Request Register */\r
+ RwReg DMAC_CREQ; /**< \brief (Dmac Offset: 0x00C) DMAC Software Chunk Transfer Request Register */\r
+ RwReg DMAC_LAST; /**< \brief (Dmac Offset: 0x010) DMAC Software Last Transfer Flag Register */\r
+ RoReg Reserved1[1];\r
+ WoReg DMAC_EBCIER; /**< \brief (Dmac Offset: 0x018) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Enable register. */\r
+ WoReg DMAC_EBCIDR; /**< \brief (Dmac Offset: 0x01C) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Disable register. */\r
+ RoReg DMAC_EBCIMR; /**< \brief (Dmac Offset: 0x020) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Mask Register. */\r
+ RoReg DMAC_EBCISR; /**< \brief (Dmac Offset: 0x024) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Status Register. */\r
+ WoReg DMAC_CHER; /**< \brief (Dmac Offset: 0x028) DMAC Channel Handler Enable Register */\r
+ WoReg DMAC_CHDR; /**< \brief (Dmac Offset: 0x02C) DMAC Channel Handler Disable Register */\r
+ RoReg DMAC_CHSR; /**< \brief (Dmac Offset: 0x030) DMAC Channel Handler Status Register */\r
+ RoReg Reserved2[2];\r
+ DmacCh_num DMAC_CH_NUM[DMACCH_NUM_NUMBER]; /**< \brief (Dmac Offset: 0x3C) ch_num = 0 .. 3 */\r
+ RoReg Reserved3[66];\r
+ RwReg DMAC_WPMR; /**< \brief (Dmac Offset: 0x1E4) DMAC Write Protect Mode Register */\r
+ RoReg DMAC_WPSR; /**< \brief (Dmac Offset: 0x1E8) DMAC Write Protect Status Register */\r
+} Dmac;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- DMAC_GCFG : (DMAC Offset: 0x000) DMAC Global Configuration Register -------- */\r
+#define DMAC_GCFG_ARB_CFG (0x1u << 4) /**< \brief (DMAC_GCFG) Arbiter Configuration */\r
+#define DMAC_GCFG_ARB_CFG_FIXED (0x0u << 4) /**< \brief (DMAC_GCFG) Fixed priority arbiter. */\r
+#define DMAC_GCFG_ARB_CFG_ROUND_ROBIN (0x1u << 4) /**< \brief (DMAC_GCFG) Modified round robin arbiter. */\r
+/* -------- DMAC_EN : (DMAC Offset: 0x004) DMAC Enable Register -------- */\r
+#define DMAC_EN_ENABLE (0x1u << 0) /**< \brief (DMAC_EN) General Enable of DMA */\r
+/* -------- DMAC_SREQ : (DMAC Offset: 0x008) DMAC Software Single Request Register -------- */\r
+#define DMAC_SREQ_SSREQ0 (0x1u << 0) /**< \brief (DMAC_SREQ) Source Request */\r
+#define DMAC_SREQ_DSREQ0 (0x1u << 1) /**< \brief (DMAC_SREQ) Destination Request */\r
+#define DMAC_SREQ_SSREQ1 (0x1u << 2) /**< \brief (DMAC_SREQ) Source Request */\r
+#define DMAC_SREQ_DSREQ1 (0x1u << 3) /**< \brief (DMAC_SREQ) Destination Request */\r
+#define DMAC_SREQ_SSREQ2 (0x1u << 4) /**< \brief (DMAC_SREQ) Source Request */\r
+#define DMAC_SREQ_DSREQ2 (0x1u << 5) /**< \brief (DMAC_SREQ) Destination Request */\r
+#define DMAC_SREQ_SSREQ3 (0x1u << 6) /**< \brief (DMAC_SREQ) Source Request */\r
+#define DMAC_SREQ_DSREQ3 (0x1u << 7) /**< \brief (DMAC_SREQ) Destination Request */\r
+/* -------- DMAC_CREQ : (DMAC Offset: 0x00C) DMAC Software Chunk Transfer Request Register -------- */\r
+#define DMAC_CREQ_SCREQ0 (0x1u << 0) /**< \brief (DMAC_CREQ) Source Chunk Request */\r
+#define DMAC_CREQ_DCREQ0 (0x1u << 1) /**< \brief (DMAC_CREQ) Destination Chunk Request */\r
+#define DMAC_CREQ_SCREQ1 (0x1u << 2) /**< \brief (DMAC_CREQ) Source Chunk Request */\r
+#define DMAC_CREQ_DCREQ1 (0x1u << 3) /**< \brief (DMAC_CREQ) Destination Chunk Request */\r
+#define DMAC_CREQ_SCREQ2 (0x1u << 4) /**< \brief (DMAC_CREQ) Source Chunk Request */\r
+#define DMAC_CREQ_DCREQ2 (0x1u << 5) /**< \brief (DMAC_CREQ) Destination Chunk Request */\r
+#define DMAC_CREQ_SCREQ3 (0x1u << 6) /**< \brief (DMAC_CREQ) Source Chunk Request */\r
+#define DMAC_CREQ_DCREQ3 (0x1u << 7) /**< \brief (DMAC_CREQ) Destination Chunk Request */\r
+/* -------- DMAC_LAST : (DMAC Offset: 0x010) DMAC Software Last Transfer Flag Register -------- */\r
+#define DMAC_LAST_SLAST0 (0x1u << 0) /**< \brief (DMAC_LAST) Source Last */\r
+#define DMAC_LAST_DLAST0 (0x1u << 1) /**< \brief (DMAC_LAST) Destination Last */\r
+#define DMAC_LAST_SLAST1 (0x1u << 2) /**< \brief (DMAC_LAST) Source Last */\r
+#define DMAC_LAST_DLAST1 (0x1u << 3) /**< \brief (DMAC_LAST) Destination Last */\r
+#define DMAC_LAST_SLAST2 (0x1u << 4) /**< \brief (DMAC_LAST) Source Last */\r
+#define DMAC_LAST_DLAST2 (0x1u << 5) /**< \brief (DMAC_LAST) Destination Last */\r
+#define DMAC_LAST_SLAST3 (0x1u << 6) /**< \brief (DMAC_LAST) Source Last */\r
+#define DMAC_LAST_DLAST3 (0x1u << 7) /**< \brief (DMAC_LAST) Destination Last */\r
+/* -------- DMAC_EBCIER : (DMAC Offset: 0x018) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Enable register. -------- */\r
+#define DMAC_EBCIER_BTC0 (0x1u << 0) /**< \brief (DMAC_EBCIER) Buffer Transfer Completed [3:0] */\r
+#define DMAC_EBCIER_BTC1 (0x1u << 1) /**< \brief (DMAC_EBCIER) Buffer Transfer Completed [3:0] */\r
+#define DMAC_EBCIER_BTC2 (0x1u << 2) /**< \brief (DMAC_EBCIER) Buffer Transfer Completed [3:0] */\r
+#define DMAC_EBCIER_BTC3 (0x1u << 3) /**< \brief (DMAC_EBCIER) Buffer Transfer Completed [3:0] */\r
+#define DMAC_EBCIER_CBTC0 (0x1u << 8) /**< \brief (DMAC_EBCIER) Chained Buffer Transfer Completed [3:0] */\r
+#define DMAC_EBCIER_CBTC1 (0x1u << 9) /**< \brief (DMAC_EBCIER) Chained Buffer Transfer Completed [3:0] */\r
+#define DMAC_EBCIER_CBTC2 (0x1u << 10) /**< \brief (DMAC_EBCIER) Chained Buffer Transfer Completed [3:0] */\r
+#define DMAC_EBCIER_CBTC3 (0x1u << 11) /**< \brief (DMAC_EBCIER) Chained Buffer Transfer Completed [3:0] */\r
+#define DMAC_EBCIER_ERR0 (0x1u << 16) /**< \brief (DMAC_EBCIER) Access Error [3:0] */\r
+#define DMAC_EBCIER_ERR1 (0x1u << 17) /**< \brief (DMAC_EBCIER) Access Error [3:0] */\r
+#define DMAC_EBCIER_ERR2 (0x1u << 18) /**< \brief (DMAC_EBCIER) Access Error [3:0] */\r
+#define DMAC_EBCIER_ERR3 (0x1u << 19) /**< \brief (DMAC_EBCIER) Access Error [3:0] */\r
+/* -------- DMAC_EBCIDR : (DMAC Offset: 0x01C) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Disable register. -------- */\r
+#define DMAC_EBCIDR_BTC0 (0x1u << 0) /**< \brief (DMAC_EBCIDR) Buffer Transfer Completed [3:0] */\r
+#define DMAC_EBCIDR_BTC1 (0x1u << 1) /**< \brief (DMAC_EBCIDR) Buffer Transfer Completed [3:0] */\r
+#define DMAC_EBCIDR_BTC2 (0x1u << 2) /**< \brief (DMAC_EBCIDR) Buffer Transfer Completed [3:0] */\r
+#define DMAC_EBCIDR_BTC3 (0x1u << 3) /**< \brief (DMAC_EBCIDR) Buffer Transfer Completed [3:0] */\r
+#define DMAC_EBCIDR_CBTC0 (0x1u << 8) /**< \brief (DMAC_EBCIDR) Chained Buffer Transfer Completed [3:0] */\r
+#define DMAC_EBCIDR_CBTC1 (0x1u << 9) /**< \brief (DMAC_EBCIDR) Chained Buffer Transfer Completed [3:0] */\r
+#define DMAC_EBCIDR_CBTC2 (0x1u << 10) /**< \brief (DMAC_EBCIDR) Chained Buffer Transfer Completed [3:0] */\r
+#define DMAC_EBCIDR_CBTC3 (0x1u << 11) /**< \brief (DMAC_EBCIDR) Chained Buffer Transfer Completed [3:0] */\r
+#define DMAC_EBCIDR_ERR0 (0x1u << 16) /**< \brief (DMAC_EBCIDR) Access Error [3:0] */\r
+#define DMAC_EBCIDR_ERR1 (0x1u << 17) /**< \brief (DMAC_EBCIDR) Access Error [3:0] */\r
+#define DMAC_EBCIDR_ERR2 (0x1u << 18) /**< \brief (DMAC_EBCIDR) Access Error [3:0] */\r
+#define DMAC_EBCIDR_ERR3 (0x1u << 19) /**< \brief (DMAC_EBCIDR) Access Error [3:0] */\r
+/* -------- DMAC_EBCIMR : (DMAC Offset: 0x020) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Mask Register. -------- */\r
+#define DMAC_EBCIMR_BTC0 (0x1u << 0) /**< \brief (DMAC_EBCIMR) Buffer Transfer Completed [3:0] */\r
+#define DMAC_EBCIMR_BTC1 (0x1u << 1) /**< \brief (DMAC_EBCIMR) Buffer Transfer Completed [3:0] */\r
+#define DMAC_EBCIMR_BTC2 (0x1u << 2) /**< \brief (DMAC_EBCIMR) Buffer Transfer Completed [3:0] */\r
+#define DMAC_EBCIMR_BTC3 (0x1u << 3) /**< \brief (DMAC_EBCIMR) Buffer Transfer Completed [3:0] */\r
+#define DMAC_EBCIMR_CBTC0 (0x1u << 8) /**< \brief (DMAC_EBCIMR) Chained Buffer Transfer Completed [3:0] */\r
+#define DMAC_EBCIMR_CBTC1 (0x1u << 9) /**< \brief (DMAC_EBCIMR) Chained Buffer Transfer Completed [3:0] */\r
+#define DMAC_EBCIMR_CBTC2 (0x1u << 10) /**< \brief (DMAC_EBCIMR) Chained Buffer Transfer Completed [3:0] */\r
+#define DMAC_EBCIMR_CBTC3 (0x1u << 11) /**< \brief (DMAC_EBCIMR) Chained Buffer Transfer Completed [3:0] */\r
+#define DMAC_EBCIMR_ERR0 (0x1u << 16) /**< \brief (DMAC_EBCIMR) Access Error [3:0] */\r
+#define DMAC_EBCIMR_ERR1 (0x1u << 17) /**< \brief (DMAC_EBCIMR) Access Error [3:0] */\r
+#define DMAC_EBCIMR_ERR2 (0x1u << 18) /**< \brief (DMAC_EBCIMR) Access Error [3:0] */\r
+#define DMAC_EBCIMR_ERR3 (0x1u << 19) /**< \brief (DMAC_EBCIMR) Access Error [3:0] */\r
+/* -------- DMAC_EBCISR : (DMAC Offset: 0x024) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Status Register. -------- */\r
+#define DMAC_EBCISR_BTC0 (0x1u << 0) /**< \brief (DMAC_EBCISR) Buffer Transfer Completed [3:0] */\r
+#define DMAC_EBCISR_BTC1 (0x1u << 1) /**< \brief (DMAC_EBCISR) Buffer Transfer Completed [3:0] */\r
+#define DMAC_EBCISR_BTC2 (0x1u << 2) /**< \brief (DMAC_EBCISR) Buffer Transfer Completed [3:0] */\r
+#define DMAC_EBCISR_BTC3 (0x1u << 3) /**< \brief (DMAC_EBCISR) Buffer Transfer Completed [3:0] */\r
+#define DMAC_EBCISR_CBTC0 (0x1u << 8) /**< \brief (DMAC_EBCISR) Chained Buffer Transfer Completed [3:0] */\r
+#define DMAC_EBCISR_CBTC1 (0x1u << 9) /**< \brief (DMAC_EBCISR) Chained Buffer Transfer Completed [3:0] */\r
+#define DMAC_EBCISR_CBTC2 (0x1u << 10) /**< \brief (DMAC_EBCISR) Chained Buffer Transfer Completed [3:0] */\r
+#define DMAC_EBCISR_CBTC3 (0x1u << 11) /**< \brief (DMAC_EBCISR) Chained Buffer Transfer Completed [3:0] */\r
+#define DMAC_EBCISR_ERR0 (0x1u << 16) /**< \brief (DMAC_EBCISR) Access Error [3:0] */\r
+#define DMAC_EBCISR_ERR1 (0x1u << 17) /**< \brief (DMAC_EBCISR) Access Error [3:0] */\r
+#define DMAC_EBCISR_ERR2 (0x1u << 18) /**< \brief (DMAC_EBCISR) Access Error [3:0] */\r
+#define DMAC_EBCISR_ERR3 (0x1u << 19) /**< \brief (DMAC_EBCISR) Access Error [3:0] */\r
+/* -------- DMAC_CHER : (DMAC Offset: 0x028) DMAC Channel Handler Enable Register -------- */\r
+#define DMAC_CHER_ENA0 (0x1u << 0) /**< \brief (DMAC_CHER) Enable [3:0] */\r
+#define DMAC_CHER_ENA1 (0x1u << 1) /**< \brief (DMAC_CHER) Enable [3:0] */\r
+#define DMAC_CHER_ENA2 (0x1u << 2) /**< \brief (DMAC_CHER) Enable [3:0] */\r
+#define DMAC_CHER_ENA3 (0x1u << 3) /**< \brief (DMAC_CHER) Enable [3:0] */\r
+#define DMAC_CHER_SUSP0 (0x1u << 8) /**< \brief (DMAC_CHER) Suspend [3:0] */\r
+#define DMAC_CHER_SUSP1 (0x1u << 9) /**< \brief (DMAC_CHER) Suspend [3:0] */\r
+#define DMAC_CHER_SUSP2 (0x1u << 10) /**< \brief (DMAC_CHER) Suspend [3:0] */\r
+#define DMAC_CHER_SUSP3 (0x1u << 11) /**< \brief (DMAC_CHER) Suspend [3:0] */\r
+#define DMAC_CHER_KEEP0 (0x1u << 24) /**< \brief (DMAC_CHER) Keep on [3:0] */\r
+#define DMAC_CHER_KEEP1 (0x1u << 25) /**< \brief (DMAC_CHER) Keep on [3:0] */\r
+#define DMAC_CHER_KEEP2 (0x1u << 26) /**< \brief (DMAC_CHER) Keep on [3:0] */\r
+#define DMAC_CHER_KEEP3 (0x1u << 27) /**< \brief (DMAC_CHER) Keep on [3:0] */\r
+/* -------- DMAC_CHDR : (DMAC Offset: 0x02C) DMAC Channel Handler Disable Register -------- */\r
+#define DMAC_CHDR_DIS0 (0x1u << 0) /**< \brief (DMAC_CHDR) Disable [3:0] */\r
+#define DMAC_CHDR_DIS1 (0x1u << 1) /**< \brief (DMAC_CHDR) Disable [3:0] */\r
+#define DMAC_CHDR_DIS2 (0x1u << 2) /**< \brief (DMAC_CHDR) Disable [3:0] */\r
+#define DMAC_CHDR_DIS3 (0x1u << 3) /**< \brief (DMAC_CHDR) Disable [3:0] */\r
+#define DMAC_CHDR_RES0 (0x1u << 8) /**< \brief (DMAC_CHDR) Resume [3:0] */\r
+#define DMAC_CHDR_RES1 (0x1u << 9) /**< \brief (DMAC_CHDR) Resume [3:0] */\r
+#define DMAC_CHDR_RES2 (0x1u << 10) /**< \brief (DMAC_CHDR) Resume [3:0] */\r
+#define DMAC_CHDR_RES3 (0x1u << 11) /**< \brief (DMAC_CHDR) Resume [3:0] */\r
+/* -------- DMAC_CHSR : (DMAC Offset: 0x030) DMAC Channel Handler Status Register -------- */\r
+#define DMAC_CHSR_ENA0 (0x1u << 0) /**< \brief (DMAC_CHSR) Enable [3:0] */\r
+#define DMAC_CHSR_ENA1 (0x1u << 1) /**< \brief (DMAC_CHSR) Enable [3:0] */\r
+#define DMAC_CHSR_ENA2 (0x1u << 2) /**< \brief (DMAC_CHSR) Enable [3:0] */\r
+#define DMAC_CHSR_ENA3 (0x1u << 3) /**< \brief (DMAC_CHSR) Enable [3:0] */\r
+#define DMAC_CHSR_SUSP0 (0x1u << 8) /**< \brief (DMAC_CHSR) Suspend [3:0] */\r
+#define DMAC_CHSR_SUSP1 (0x1u << 9) /**< \brief (DMAC_CHSR) Suspend [3:0] */\r
+#define DMAC_CHSR_SUSP2 (0x1u << 10) /**< \brief (DMAC_CHSR) Suspend [3:0] */\r
+#define DMAC_CHSR_SUSP3 (0x1u << 11) /**< \brief (DMAC_CHSR) Suspend [3:0] */\r
+#define DMAC_CHSR_EMPT0 (0x1u << 16) /**< \brief (DMAC_CHSR) Empty [3:0] */\r
+#define DMAC_CHSR_EMPT1 (0x1u << 17) /**< \brief (DMAC_CHSR) Empty [3:0] */\r
+#define DMAC_CHSR_EMPT2 (0x1u << 18) /**< \brief (DMAC_CHSR) Empty [3:0] */\r
+#define DMAC_CHSR_EMPT3 (0x1u << 19) /**< \brief (DMAC_CHSR) Empty [3:0] */\r
+#define DMAC_CHSR_STAL0 (0x1u << 24) /**< \brief (DMAC_CHSR) Stalled [3:0] */\r
+#define DMAC_CHSR_STAL1 (0x1u << 25) /**< \brief (DMAC_CHSR) Stalled [3:0] */\r
+#define DMAC_CHSR_STAL2 (0x1u << 26) /**< \brief (DMAC_CHSR) Stalled [3:0] */\r
+#define DMAC_CHSR_STAL3 (0x1u << 27) /**< \brief (DMAC_CHSR) Stalled [3:0] */\r
+/* -------- DMAC_SADDR : (DMAC Offset: N/A) DMAC Channel Source Address Register -------- */\r
+#define DMAC_SADDR_SADDR_Pos 0\r
+#define DMAC_SADDR_SADDR_Msk (0xffffffffu << DMAC_SADDR_SADDR_Pos) /**< \brief (DMAC_SADDR) Channel x Source Address */\r
+#define DMAC_SADDR_SADDR(value) ((DMAC_SADDR_SADDR_Msk & ((value) << DMAC_SADDR_SADDR_Pos)))\r
+/* -------- DMAC_DADDR : (DMAC Offset: N/A) DMAC Channel Destination Address Register -------- */\r
+#define DMAC_DADDR_DADDR_Pos 0\r
+#define DMAC_DADDR_DADDR_Msk (0xffffffffu << DMAC_DADDR_DADDR_Pos) /**< \brief (DMAC_DADDR) Channel x Destination Address */\r
+#define DMAC_DADDR_DADDR(value) ((DMAC_DADDR_DADDR_Msk & ((value) << DMAC_DADDR_DADDR_Pos)))\r
+/* -------- DMAC_DSCR : (DMAC Offset: N/A) DMAC Channel Descriptor Address Register -------- */\r
+#define DMAC_DSCR_DSCR_Pos 2\r
+#define DMAC_DSCR_DSCR_Msk (0x3fffffffu << DMAC_DSCR_DSCR_Pos) /**< \brief (DMAC_DSCR) Buffer Transfer Descriptor Address */\r
+#define DMAC_DSCR_DSCR(value) ((DMAC_DSCR_DSCR_Msk & ((value) << DMAC_DSCR_DSCR_Pos)))\r
+/* -------- DMAC_CTRLA : (DMAC Offset: N/A) DMAC Channel Control A Register -------- */\r
+#define DMAC_CTRLA_BTSIZE_Pos 0\r
+#define DMAC_CTRLA_BTSIZE_Msk (0xffffu << DMAC_CTRLA_BTSIZE_Pos) /**< \brief (DMAC_CTRLA) Buffer Transfer Size */\r
+#define DMAC_CTRLA_BTSIZE(value) ((DMAC_CTRLA_BTSIZE_Msk & ((value) << DMAC_CTRLA_BTSIZE_Pos)))\r
+#define DMAC_CTRLA_SRC_WIDTH_Pos 24\r
+#define DMAC_CTRLA_SRC_WIDTH_Msk (0x3u << DMAC_CTRLA_SRC_WIDTH_Pos) /**< \brief (DMAC_CTRLA) Transfer Width for the Source */\r
+#define DMAC_CTRLA_SRC_WIDTH_BYTE (0x0u << 24) /**< \brief (DMAC_CTRLA) the transfer size is set to 8-bit width */\r
+#define DMAC_CTRLA_SRC_WIDTH_HALF_WORD (0x1u << 24) /**< \brief (DMAC_CTRLA) the transfer size is set to 16-bit width */\r
+#define DMAC_CTRLA_SRC_WIDTH_WORD (0x2u << 24) /**< \brief (DMAC_CTRLA) the transfer size is set to 32-bit width */\r
+#define DMAC_CTRLA_DST_WIDTH_Pos 28\r
+#define DMAC_CTRLA_DST_WIDTH_Msk (0x3u << DMAC_CTRLA_DST_WIDTH_Pos) /**< \brief (DMAC_CTRLA) Transfer Width for the Destination */\r
+#define DMAC_CTRLA_DST_WIDTH_BYTE (0x0u << 28) /**< \brief (DMAC_CTRLA) the transfer size is set to 8-bit width */\r
+#define DMAC_CTRLA_DST_WIDTH_HALF_WORD (0x1u << 28) /**< \brief (DMAC_CTRLA) the transfer size is set to 16-bit width */\r
+#define DMAC_CTRLA_DST_WIDTH_WORD (0x2u << 28) /**< \brief (DMAC_CTRLA) the transfer size is set to 32-bit width */\r
+#define DMAC_CTRLA_DONE (0x1u << 31) /**< \brief (DMAC_CTRLA) Current Descriptor Stop Command and Transfer Completed Memory Indicator */\r
+/* -------- DMAC_CTRLB : (DMAC Offset: N/A) DMAC Channel Control B Register -------- */\r
+#define DMAC_CTRLB_SRC_DSCR (0x1u << 16) /**< \brief (DMAC_CTRLB) Source Address Descriptor */\r
+#define DMAC_CTRLB_SRC_DSCR_FETCH_FROM_MEM (0x0u << 16) /**< \brief (DMAC_CTRLB) Source address is updated when the descriptor is fetched from the memory. */\r
+#define DMAC_CTRLB_SRC_DSCR_FETCH_DISABLE (0x1u << 16) /**< \brief (DMAC_CTRLB) Buffer Descriptor Fetch operation is disabled for the source. */\r
+#define DMAC_CTRLB_DST_DSCR (0x1u << 20) /**< \brief (DMAC_CTRLB) Destination Address Descriptor */\r
+#define DMAC_CTRLB_DST_DSCR_FETCH_FROM_MEM (0x0u << 20) /**< \brief (DMAC_CTRLB) Destination address is updated when the descriptor is fetched from the memory. */\r
+#define DMAC_CTRLB_DST_DSCR_FETCH_DISABLE (0x1u << 20) /**< \brief (DMAC_CTRLB) Buffer Descriptor Fetch operation is disabled for the destination. */\r
+#define DMAC_CTRLB_FC_Pos 21\r
+#define DMAC_CTRLB_FC_Msk (0x3u << DMAC_CTRLB_FC_Pos) /**< \brief (DMAC_CTRLB) Flow Control */\r
+#define DMAC_CTRLB_FC_MEM2MEM_DMA_FC (0x0u << 21) /**< \brief (DMAC_CTRLB) Memory-to-Memory Transfer DMAC is flow controller */\r
+#define DMAC_CTRLB_FC_MEM2PER_DMA_FC (0x1u << 21) /**< \brief (DMAC_CTRLB) Memory-to-Peripheral Transfer DMAC is flow controller */\r
+#define DMAC_CTRLB_FC_PER2MEM_DMA_FC (0x2u << 21) /**< \brief (DMAC_CTRLB) Peripheral-to-Memory Transfer DMAC is flow controller */\r
+#define DMAC_CTRLB_FC_PER2PER_DMA_FC (0x3u << 21) /**< \brief (DMAC_CTRLB) Peripheral-to-Peripheral Transfer DMAC is flow controller */\r
+#define DMAC_CTRLB_SRC_INCR_Pos 24\r
+#define DMAC_CTRLB_SRC_INCR_Msk (0x3u << DMAC_CTRLB_SRC_INCR_Pos) /**< \brief (DMAC_CTRLB) Incrementing, Decrementing or Fixed Address for the Source */\r
+#define DMAC_CTRLB_SRC_INCR_INCREMENTING (0x0u << 24) /**< \brief (DMAC_CTRLB) The source address is incremented */\r
+#define DMAC_CTRLB_SRC_INCR_DECREMENTING (0x1u << 24) /**< \brief (DMAC_CTRLB) The source address is decremented */\r
+#define DMAC_CTRLB_SRC_INCR_FIXED (0x2u << 24) /**< \brief (DMAC_CTRLB) The source address remains unchanged */\r
+#define DMAC_CTRLB_DST_INCR_Pos 28\r
+#define DMAC_CTRLB_DST_INCR_Msk (0x3u << DMAC_CTRLB_DST_INCR_Pos) /**< \brief (DMAC_CTRLB) Incrementing, Decrementing or Fixed Address for the Destination */\r
+#define DMAC_CTRLB_DST_INCR_INCREMENTING (0x0u << 28) /**< \brief (DMAC_CTRLB) The destination address is incremented */\r
+#define DMAC_CTRLB_DST_INCR_DECREMENTING (0x1u << 28) /**< \brief (DMAC_CTRLB) The destination address is decremented */\r
+#define DMAC_CTRLB_DST_INCR_FIXED (0x2u << 28) /**< \brief (DMAC_CTRLB) The destination address remains unchanged */\r
+#define DMAC_CTRLB_IEN (0x1u << 30) /**< \brief (DMAC_CTRLB) Interrupt Enable Not */\r
+/* -------- DMAC_CFG : (DMAC Offset: N/A) DMAC Channel Configuration Register -------- */\r
+#define DMAC_CFG_SRC_PER_Pos 0\r
+#define DMAC_CFG_SRC_PER_Msk (0xfu << DMAC_CFG_SRC_PER_Pos) /**< \brief (DMAC_CFG) Source with Peripheral identifier */\r
+#define DMAC_CFG_SRC_PER(value) ((DMAC_CFG_SRC_PER_Msk & ((value) << DMAC_CFG_SRC_PER_Pos)))\r
+#define DMAC_CFG_DST_PER_Pos 4\r
+#define DMAC_CFG_DST_PER_Msk (0xfu << DMAC_CFG_DST_PER_Pos) /**< \brief (DMAC_CFG) Destination with Peripheral identifier */\r
+#define DMAC_CFG_DST_PER(value) ((DMAC_CFG_DST_PER_Msk & ((value) << DMAC_CFG_DST_PER_Pos)))\r
+#define DMAC_CFG_SRC_H2SEL (0x1u << 9) /**< \brief (DMAC_CFG) Software or Hardware Selection for the Source */\r
+#define DMAC_CFG_SRC_H2SEL_SW (0x0u << 9) /**< \brief (DMAC_CFG) Software handshaking interface is used to trigger a transfer request. */\r
+#define DMAC_CFG_SRC_H2SEL_HW (0x1u << 9) /**< \brief (DMAC_CFG) Hardware handshaking interface is used to trigger a transfer request. */\r
+#define DMAC_CFG_DST_H2SEL (0x1u << 13) /**< \brief (DMAC_CFG) Software or Hardware Selection for the Destination */\r
+#define DMAC_CFG_DST_H2SEL_SW (0x0u << 13) /**< \brief (DMAC_CFG) Software handshaking interface is used to trigger a transfer request. */\r
+#define DMAC_CFG_DST_H2SEL_HW (0x1u << 13) /**< \brief (DMAC_CFG) Hardware handshaking interface is used to trigger a transfer request. */\r
+#define DMAC_CFG_SOD (0x1u << 16) /**< \brief (DMAC_CFG) Stop On Done */\r
+#define DMAC_CFG_SOD_DISABLE (0x0u << 16) /**< \brief (DMAC_CFG) STOP ON DONE disabled, the descriptor fetch operation ignores DONE Field of CTRLA register. */\r
+#define DMAC_CFG_SOD_ENABLE (0x1u << 16) /**< \brief (DMAC_CFG) STOP ON DONE activated, the DMAC module is automatically disabled if DONE FIELD is set to 1. */\r
+#define DMAC_CFG_LOCK_IF (0x1u << 20) /**< \brief (DMAC_CFG) Interface Lock */\r
+#define DMAC_CFG_LOCK_IF_DISABLE (0x0u << 20) /**< \brief (DMAC_CFG) Interface Lock capability is disabled */\r
+#define DMAC_CFG_LOCK_IF_ENABLE (0x1u << 20) /**< \brief (DMAC_CFG) Interface Lock capability is enabled */\r
+#define DMAC_CFG_LOCK_B (0x1u << 21) /**< \brief (DMAC_CFG) Bus Lock */\r
+#define DMAC_CFG_LOCK_B_DISABLE (0x0u << 21) /**< \brief (DMAC_CFG) AHB Bus Locking capability is disabled. */\r
+#define DMAC_CFG_LOCK_IF_L (0x1u << 22) /**< \brief (DMAC_CFG) Master Interface Arbiter Lock */\r
+#define DMAC_CFG_LOCK_IF_L_CHUNK (0x0u << 22) /**< \brief (DMAC_CFG) The Master Interface Arbiter is locked by the channel x for a chunk transfer. */\r
+#define DMAC_CFG_LOCK_IF_L_BUFFER (0x1u << 22) /**< \brief (DMAC_CFG) The Master Interface Arbiter is locked by the channel x for a buffer transfer. */\r
+#define DMAC_CFG_AHB_PROT_Pos 24\r
+#define DMAC_CFG_AHB_PROT_Msk (0x7u << DMAC_CFG_AHB_PROT_Pos) /**< \brief (DMAC_CFG) AHB Protection */\r
+#define DMAC_CFG_AHB_PROT(value) ((DMAC_CFG_AHB_PROT_Msk & ((value) << DMAC_CFG_AHB_PROT_Pos)))\r
+#define DMAC_CFG_FIFOCFG_Pos 28\r
+#define DMAC_CFG_FIFOCFG_Msk (0x3u << DMAC_CFG_FIFOCFG_Pos) /**< \brief (DMAC_CFG) FIFO Configuration */\r
+#define DMAC_CFG_FIFOCFG_ALAP_CFG (0x0u << 28) /**< \brief (DMAC_CFG) The largest defined length AHB burst is performed on the destination AHB interface. */\r
+#define DMAC_CFG_FIFOCFG_HALF_CFG (0x1u << 28) /**< \brief (DMAC_CFG) When half FIFO size is available/filled, a source/destination request is serviced. */\r
+#define DMAC_CFG_FIFOCFG_ASAP_CFG (0x2u << 28) /**< \brief (DMAC_CFG) When there is enough space/data available to perform a single AHB access, then the request is serviced. */\r
+/* -------- DMAC_WPMR : (DMAC Offset: 0x1E4) DMAC Write Protect Mode Register -------- */\r
+#define DMAC_WPMR_WPEN (0x1u << 0) /**< \brief (DMAC_WPMR) Write Protect Enable */\r
+#define DMAC_WPMR_WPKEY_Pos 8\r
+#define DMAC_WPMR_WPKEY_Msk (0xffffffu << DMAC_WPMR_WPKEY_Pos) /**< \brief (DMAC_WPMR) Write Protect KEY */\r
+#define DMAC_WPMR_WPKEY(value) ((DMAC_WPMR_WPKEY_Msk & ((value) << DMAC_WPMR_WPKEY_Pos)))\r
+/* -------- DMAC_WPSR : (DMAC Offset: 0x1E8) DMAC Write Protect Status Register -------- */\r
+#define DMAC_WPSR_WPVS (0x1u << 0) /**< \brief (DMAC_WPSR) Write Protect Violation Status */\r
+#define DMAC_WPSR_WPVSRC_Pos 8\r
+#define DMAC_WPSR_WPVSRC_Msk (0xffffu << DMAC_WPSR_WPVSRC_Pos) /**< \brief (DMAC_WPSR) Write Protect Violation Source */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM4E_DMAC_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4E_EFC_COMPONENT_\r
+#define _SAM4E_EFC_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Embedded Flash Controller */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM4E_EFC Embedded Flash Controller */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Efc hardware registers */\r
+typedef struct {\r
+ RwReg EEFC_FMR; /**< \brief (Efc Offset: 0x00) EEFC Flash Mode Register */\r
+ WoReg EEFC_FCR; /**< \brief (Efc Offset: 0x04) EEFC Flash Command Register */\r
+ RoReg EEFC_FSR; /**< \brief (Efc Offset: 0x08) EEFC Flash Status Register */\r
+ RoReg EEFC_FRR; /**< \brief (Efc Offset: 0x0C) EEFC Flash Result Register */\r
+} Efc;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- EEFC_FMR : (EFC Offset: 0x00) EEFC Flash Mode Register -------- */\r
+#define EEFC_FMR_FRDY (0x1u << 0) /**< \brief (EEFC_FMR) Ready Interrupt Enable */\r
+#define EEFC_FMR_FWS_Pos 8\r
+#define EEFC_FMR_FWS_Msk (0xfu << EEFC_FMR_FWS_Pos) /**< \brief (EEFC_FMR) Flash Wait State */\r
+#define EEFC_FMR_FWS(value) ((EEFC_FMR_FWS_Msk & ((value) << EEFC_FMR_FWS_Pos)))\r
+#define EEFC_FMR_SCOD (0x1u << 16) /**< \brief (EEFC_FMR) Sequential Code Optimization Disable */\r
+#define EEFC_FMR_FAM (0x1u << 24) /**< \brief (EEFC_FMR) Flash Access Mode */\r
+#define EEFC_FMR_CLOE (0x1u << 26) /**< \brief (EEFC_FMR) Code Loops Optimization Enable */\r
+/* -------- EEFC_FCR : (EFC Offset: 0x04) EEFC Flash Command Register -------- */\r
+#define EEFC_FCR_FCMD_Pos 0\r
+#define EEFC_FCR_FCMD_Msk (0xffu << EEFC_FCR_FCMD_Pos) /**< \brief (EEFC_FCR) Flash Command */\r
+#define EEFC_FCR_FCMD_GETD (0x0u << 0) /**< \brief (EEFC_FCR) Get Flash Descriptor */\r
+#define EEFC_FCR_FCMD_WP (0x1u << 0) /**< \brief (EEFC_FCR) Write page */\r
+#define EEFC_FCR_FCMD_WPL (0x2u << 0) /**< \brief (EEFC_FCR) Write page and lock */\r
+#define EEFC_FCR_FCMD_EWP (0x3u << 0) /**< \brief (EEFC_FCR) Erase page and write page */\r
+#define EEFC_FCR_FCMD_EWPL (0x4u << 0) /**< \brief (EEFC_FCR) Erase page and write page then lock */\r
+#define EEFC_FCR_FCMD_EA (0x5u << 0) /**< \brief (EEFC_FCR) Erase all */\r
+#define EEFC_FCR_FCMD_EPA (0x7u << 0) /**< \brief (EEFC_FCR) Erase Pages */\r
+#define EEFC_FCR_FCMD_SLB (0x8u << 0) /**< \brief (EEFC_FCR) Set Lock Bit */\r
+#define EEFC_FCR_FCMD_CLB (0x9u << 0) /**< \brief (EEFC_FCR) Clear Lock Bit */\r
+#define EEFC_FCR_FCMD_GLB (0xAu << 0) /**< \brief (EEFC_FCR) Get Lock Bit */\r
+#define EEFC_FCR_FCMD_SGPB (0xBu << 0) /**< \brief (EEFC_FCR) Set GPNVM Bit */\r
+#define EEFC_FCR_FCMD_CGPB (0xCu << 0) /**< \brief (EEFC_FCR) Clear GPNVM Bit */\r
+#define EEFC_FCR_FCMD_GGPB (0xDu << 0) /**< \brief (EEFC_FCR) Get GPNVM Bit */\r
+#define EEFC_FCR_FCMD_STUI (0xEu << 0) /**< \brief (EEFC_FCR) Start Read Unique Identifier */\r
+#define EEFC_FCR_FCMD_SPUI (0xFu << 0) /**< \brief (EEFC_FCR) Stop Read Unique Identifier */\r
+#define EEFC_FCR_FCMD_GCALB (0x10u << 0) /**< \brief (EEFC_FCR) Get CALIB Bit */\r
+#define EEFC_FCR_FCMD_ES (0x11u << 0) /**< \brief (EEFC_FCR) Erase Sector */\r
+#define EEFC_FCR_FCMD_WUS (0x12u << 0) /**< \brief (EEFC_FCR) Write User Signature */\r
+#define EEFC_FCR_FCMD_EUS (0x13u << 0) /**< \brief (EEFC_FCR) Erase User Signature */\r
+#define EEFC_FCR_FCMD_STUS (0x14u << 0) /**< \brief (EEFC_FCR) Start Read User Signature */\r
+#define EEFC_FCR_FCMD_SPUS (0x15u << 0) /**< \brief (EEFC_FCR) Stop Read User Signature */\r
+#define EEFC_FCR_FARG_Pos 8\r
+#define EEFC_FCR_FARG_Msk (0xffffu << EEFC_FCR_FARG_Pos) /**< \brief (EEFC_FCR) Flash Command Argument */\r
+#define EEFC_FCR_FARG(value) ((EEFC_FCR_FARG_Msk & ((value) << EEFC_FCR_FARG_Pos)))\r
+#define EEFC_FCR_FKEY_Pos 24\r
+#define EEFC_FCR_FKEY_Msk (0xffu << EEFC_FCR_FKEY_Pos) /**< \brief (EEFC_FCR) Flash Writing Protection Key */\r
+#define EEFC_FCR_FKEY_PASSWD (0x5Au << 24) /**< \brief (EEFC_FCR) The 0x5A value enables the command defined by the bits of the register. If the field is written with a different value, the write is not performed and no action is started. */\r
+/* -------- EEFC_FSR : (EFC Offset: 0x08) EEFC Flash Status Register -------- */\r
+#define EEFC_FSR_FRDY (0x1u << 0) /**< \brief (EEFC_FSR) Flash Ready Status */\r
+#define EEFC_FSR_FCMDE (0x1u << 1) /**< \brief (EEFC_FSR) Flash Command Error Status */\r
+#define EEFC_FSR_FLOCKE (0x1u << 2) /**< \brief (EEFC_FSR) Flash Lock Error Status */\r
+#define EEFC_FSR_FLERR (0x1u << 3) /**< \brief (EEFC_FSR) Flash Error Status */\r
+/* -------- EEFC_FRR : (EFC Offset: 0x0C) EEFC Flash Result Register -------- */\r
+#define EEFC_FRR_FVALUE_Pos 0\r
+#define EEFC_FRR_FVALUE_Msk (0xffffffffu << EEFC_FRR_FVALUE_Pos) /**< \brief (EEFC_FRR) Flash Result Value */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM4E_EFC_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4E_GMAC_COMPONENT_\r
+#define _SAM4E_GMAC_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Gigabit Ethernet MAC */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM4E_GMAC Gigabit Ethernet MAC */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief GmacSa hardware registers */\r
+typedef struct {\r
+ RwReg GMAC_SAB; /**< \brief (GmacSa Offset: 0x0) Specific Address 1 Bottom [31:0] Register */\r
+ RwReg GMAC_SAT; /**< \brief (GmacSa Offset: 0x4) Specific Address 1 Top [47:32] Register */\r
+} GmacSa;\r
+/** \brief Gmac hardware registers */\r
+#define GMACSA_NUMBER 4\r
+typedef struct {\r
+ RwReg GMAC_NCR; /**< \brief (Gmac Offset: 0x000) Network Control Register */\r
+ RwReg GMAC_NCFGR; /**< \brief (Gmac Offset: 0x004) Network Configuration Register */\r
+ RoReg GMAC_NSR; /**< \brief (Gmac Offset: 0x008) Network Status Register */\r
+ RwReg GMAC_UR; /**< \brief (Gmac Offset: 0x00C) User Register */\r
+ RwReg GMAC_DCFGR; /**< \brief (Gmac Offset: 0x010) DMA Configuration Register */\r
+ RwReg GMAC_TSR; /**< \brief (Gmac Offset: 0x014) Transmit Status Register */\r
+ RwReg GMAC_RBQB; /**< \brief (Gmac Offset: 0x018) Receive Buffer Queue Base Address */\r
+ RwReg GMAC_TBQB; /**< \brief (Gmac Offset: 0x01C) Transmit Buffer Queue Base Address */\r
+ RwReg GMAC_RSR; /**< \brief (Gmac Offset: 0x020) Receive Status Register */\r
+ RoReg GMAC_ISR; /**< \brief (Gmac Offset: 0x024) Interrupt Status Register */\r
+ WoReg GMAC_IER; /**< \brief (Gmac Offset: 0x028) Interrupt Enable Register */\r
+ WoReg GMAC_IDR; /**< \brief (Gmac Offset: 0x02C) Interrupt Disable Register */\r
+ RoReg GMAC_IMR; /**< \brief (Gmac Offset: 0x030) Interrupt Mask Register */\r
+ RwReg GMAC_MAN; /**< \brief (Gmac Offset: 0x034) PHY Maintenance Register */\r
+ RoReg GMAC_RPQ; /**< \brief (Gmac Offset: 0x038) Received Pause Quantum Register */\r
+ RwReg GMAC_TPQ; /**< \brief (Gmac Offset: 0x03C) Transmit Pause Quantum Register */\r
+ RoReg Reserved1[16];\r
+ RwReg GMAC_HRB; /**< \brief (Gmac Offset: 0x080) Hash Register Bottom [31:0] */\r
+ RwReg GMAC_HRT; /**< \brief (Gmac Offset: 0x084) Hash Register Top [63:32] */\r
+ GmacSa GMAC_SA[GMACSA_NUMBER]; /**< \brief (Gmac Offset: 0x088) 1 .. 4 */\r
+ RwReg GMAC_TIDM[4]; /**< \brief (Gmac Offset: 0x0A8) Type ID Match 1 Register */\r
+ RoReg Reserved2[1];\r
+ RwReg GMAC_IPGS; /**< \brief (Gmac Offset: 0x0BC) IPG Stretch Register */\r
+ RwReg GMAC_SVLAN; /**< \brief (Gmac Offset: 0x0C0) Stacked VLAN Register */\r
+ RwReg GMAC_TPFCP; /**< \brief (Gmac Offset: 0x0C4) Transmit PFC Pause Register */\r
+ RwReg GMAC_SAMB1; /**< \brief (Gmac Offset: 0x0C8) Specific Address 1 Mask Bottom [31:0] Register */\r
+ RwReg GMAC_SAMT1; /**< \brief (Gmac Offset: 0x0CC) Specific Address 1 Mask Top [47:32] Register */\r
+ RoReg Reserved3[12];\r
+ RoReg GMAC_OTLO; /**< \brief (Gmac Offset: 0x100) Octets Transmitted [31:0] Register */\r
+ RoReg GMAC_OTHI; /**< \brief (Gmac Offset: 0x104) Octets Transmitted [47:32] Register */\r
+ RoReg GMAC_FT; /**< \brief (Gmac Offset: 0x108) Frames Transmitted Register */\r
+ RoReg GMAC_BCFT; /**< \brief (Gmac Offset: 0x10C) Broadcast Frames Transmitted Register */\r
+ RoReg GMAC_MFT; /**< \brief (Gmac Offset: 0x110) Multicast Frames Transmitted Register */\r
+ RoReg GMAC_PFT; /**< \brief (Gmac Offset: 0x114) Pause Frames Transmitted Register */\r
+ RoReg GMAC_BFT64; /**< \brief (Gmac Offset: 0x118) 64 Byte Frames Transmitted Register */\r
+ RoReg GMAC_TBFT127; /**< \brief (Gmac Offset: 0x11C) 65 to 127 Byte Frames Transmitted Register */\r
+ RoReg GMAC_TBFT255; /**< \brief (Gmac Offset: 0x120) 128 to 255 Byte Frames Transmitted Register */\r
+ RoReg GMAC_TBFT511; /**< \brief (Gmac Offset: 0x124) 256 to 511 Byte Frames Transmitted Register */\r
+ RoReg GMAC_TBFT1023; /**< \brief (Gmac Offset: 0x128) 512 to 1023 Byte Frames Transmitted Register */\r
+ RoReg GMAC_TBFT1518; /**< \brief (Gmac Offset: 0x12C) 1024 to 1518 Byte Frames Transmitted Register */\r
+ RoReg GMAC_GTBFT1518; /**< \brief (Gmac Offset: 0x130) Greater Than 1518 Byte Frames Transmitted Register */\r
+ RoReg GMAC_TUR; /**< \brief (Gmac Offset: 0x134) Transmit Under Runs Register */\r
+ RoReg GMAC_SCF; /**< \brief (Gmac Offset: 0x138) Single Collision Frames Register */\r
+ RoReg GMAC_MCF; /**< \brief (Gmac Offset: 0x13C) Multiple Collision Frames Register */\r
+ RoReg GMAC_EC; /**< \brief (Gmac Offset: 0x140) Excessive Collisions Register */\r
+ RoReg GMAC_LC; /**< \brief (Gmac Offset: 0x144) Late Collisions Register */\r
+ RoReg GMAC_DTF; /**< \brief (Gmac Offset: 0x148) Deferred Transmission Frames Register */\r
+ RoReg GMAC_CSE; /**< \brief (Gmac Offset: 0x14C) Carrier Sense Errors Register */\r
+ RoReg GMAC_ORLO; /**< \brief (Gmac Offset: 0x150) Octets Received [31:0] Received */\r
+ RoReg GMAC_ORHI; /**< \brief (Gmac Offset: 0x154) Octets Received [47:32] Received */\r
+ RoReg GMAC_FR; /**< \brief (Gmac Offset: 0x158) Frames Received Register */\r
+ RoReg GMAC_BCFR; /**< \brief (Gmac Offset: 0x15C) Broadcast Frames Received Register */\r
+ RoReg GMAC_MFR; /**< \brief (Gmac Offset: 0x160) Multicast Frames Received Register */\r
+ RoReg GMAC_PFR; /**< \brief (Gmac Offset: 0x164) Pause Frames Received Register */\r
+ RoReg GMAC_BFR64; /**< \brief (Gmac Offset: 0x168) 64 Byte Frames Received Register */\r
+ RoReg GMAC_TBFR127; /**< \brief (Gmac Offset: 0x16C) 65 to 127 Byte Frames Received Register */\r
+ RoReg GMAC_TBFR255; /**< \brief (Gmac Offset: 0x170) 128 to 255 Byte Frames Received Register */\r
+ RoReg GMAC_TBFR511; /**< \brief (Gmac Offset: 0x174) 256 to 511Byte Frames Received Register */\r
+ RoReg GMAC_TBFR1023; /**< \brief (Gmac Offset: 0x178) 512 to 1023 Byte Frames Received Register */\r
+ RoReg GMAC_TBFR1518; /**< \brief (Gmac Offset: 0x17C) 1024 to 1518 Byte Frames Received Register */\r
+ RoReg GMAC_TMXBFR; /**< \brief (Gmac Offset: 0x180) 1519 to Maximum Byte Frames Received Register */\r
+ RoReg GMAC_UFR; /**< \brief (Gmac Offset: 0x184) Undersize Frames Received Register */\r
+ RoReg GMAC_OFR; /**< \brief (Gmac Offset: 0x188) Oversize Frames Received Register */\r
+ RoReg GMAC_JR; /**< \brief (Gmac Offset: 0x18C) Jabbers Received Register */\r
+ RoReg GMAC_FCSE; /**< \brief (Gmac Offset: 0x190) Frame Check Sequence Errors Register */\r
+ RoReg GMAC_LFFE; /**< \brief (Gmac Offset: 0x194) Length Field Frame Errors Register */\r
+ RoReg GMAC_RSE; /**< \brief (Gmac Offset: 0x198) Receive Symbol Errors Register */\r
+ RoReg GMAC_AE; /**< \brief (Gmac Offset: 0x19C) Alignment Errors Register */\r
+ RoReg GMAC_RRE; /**< \brief (Gmac Offset: 0x1A0) Receive Resource Errors Register */\r
+ RoReg GMAC_ROE; /**< \brief (Gmac Offset: 0x1A4) Receive Overrun Register */\r
+ RoReg GMAC_IHCE; /**< \brief (Gmac Offset: 0x1A8) IP Header Checksum Errors Register */\r
+ RoReg GMAC_TCE; /**< \brief (Gmac Offset: 0x1AC) TCP Checksum Errors Register */\r
+ RoReg GMAC_UCE; /**< \brief (Gmac Offset: 0x1B0) UDP Checksum Errors Register */\r
+ RoReg Reserved4[5];\r
+ RwReg GMAC_TSSS; /**< \brief (Gmac Offset: 0x1C8) 1588 Timer Sync Strobe Seconds Register */\r
+ RwReg GMAC_TSSN; /**< \brief (Gmac Offset: 0x1CC) 1588 Timer Sync Strobe Nanoseconds Register */\r
+ RwReg GMAC_TS; /**< \brief (Gmac Offset: 0x1D0) 1588 Timer Seconds Register */\r
+ RwReg GMAC_TN; /**< \brief (Gmac Offset: 0x1D4) 1588 Timer Nanoseconds Register */\r
+ WoReg GMAC_TA; /**< \brief (Gmac Offset: 0x1D8) 1588 Timer Adjust Register */\r
+ RwReg GMAC_TI; /**< \brief (Gmac Offset: 0x1DC) 1588 Timer Increment Register */\r
+ RoReg GMAC_EFTS; /**< \brief (Gmac Offset: 0x1E0) PTP Event Frame Transmitted Seconds */\r
+ RoReg GMAC_EFTN; /**< \brief (Gmac Offset: 0x1E4) PTP Event Frame Transmitted Nanoseconds */\r
+ RoReg GMAC_EFRS; /**< \brief (Gmac Offset: 0x1E8) PTP Event Frame Received Seconds */\r
+ RoReg GMAC_EFRN; /**< \brief (Gmac Offset: 0x1EC) PTP Event Frame Received Nanoseconds */\r
+ RoReg GMAC_PEFTS; /**< \brief (Gmac Offset: 0x1F0) PTP Peer Event Frame Transmitted Seconds */\r
+ RoReg GMAC_PEFTN; /**< \brief (Gmac Offset: 0x1F4) PTP Peer Event Frame Transmitted Nanoseconds */\r
+ RoReg GMAC_PEFRS; /**< \brief (Gmac Offset: 0x1F8) PTP Peer Event Frame Received Seconds */\r
+ RoReg GMAC_PEFRN; /**< \brief (Gmac Offset: 0x1FC) PTP Peer Event Frame Received Nanoseconds */\r
+} Gmac;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- GMAC_NCR : (GMAC Offset: 0x000) Network Control Register -------- */\r
+#define GMAC_NCR_LBL (0x1u << 1) /**< \brief (GMAC_NCR) Loop Back Local */\r
+#define GMAC_NCR_RXEN (0x1u << 2) /**< \brief (GMAC_NCR) Receive Enable */\r
+#define GMAC_NCR_TXEN (0x1u << 3) /**< \brief (GMAC_NCR) Transmit Enable */\r
+#define GMAC_NCR_MPE (0x1u << 4) /**< \brief (GMAC_NCR) Management Port Enable */\r
+#define GMAC_NCR_CLRSTAT (0x1u << 5) /**< \brief (GMAC_NCR) Clear Statistics Registers */\r
+#define GMAC_NCR_INCSTAT (0x1u << 6) /**< \brief (GMAC_NCR) Increment Statistics Registers */\r
+#define GMAC_NCR_WESTAT (0x1u << 7) /**< \brief (GMAC_NCR) Write Enable for Statistics Registers */\r
+#define GMAC_NCR_BP (0x1u << 8) /**< \brief (GMAC_NCR) Back pressure */\r
+#define GMAC_NCR_TSTART (0x1u << 9) /**< \brief (GMAC_NCR) Start Transmission */\r
+#define GMAC_NCR_THALT (0x1u << 10) /**< \brief (GMAC_NCR) Transmit Halt */\r
+#define GMAC_NCR_TXPF (0x1u << 11) /**< \brief (GMAC_NCR) Transmit Pause Frame */\r
+#define GMAC_NCR_TXZQPF (0x1u << 12) /**< \brief (GMAC_NCR) Transmit Zero Quantum Pause Frame */\r
+#define GMAC_NCR_RDS (0x1u << 14) /**< \brief (GMAC_NCR) Read Snapshot */\r
+#define GMAC_NCR_SRTSM (0x1u << 15) /**< \brief (GMAC_NCR) Store Receive Time Stamp to Memory */\r
+#define GMAC_NCR_ENPBPR (0x1u << 16) /**< \brief (GMAC_NCR) Enable PFC Priority-based Pause Reception */\r
+#define GMAC_NCR_TXPBPF (0x1u << 17) /**< \brief (GMAC_NCR) Transmit PFC Priority-based Pause Frame */\r
+#define GMAC_NCR_FNP (0x1u << 18) /**< \brief (GMAC_NCR) Flush Next Packet */\r
+/* -------- GMAC_NCFGR : (GMAC Offset: 0x004) Network Configuration Register -------- */\r
+#define GMAC_NCFGR_SPD (0x1u << 0) /**< \brief (GMAC_NCFGR) Speed */\r
+#define GMAC_NCFGR_FD (0x1u << 1) /**< \brief (GMAC_NCFGR) Full Duplex */\r
+#define GMAC_NCFGR_DNVLAN (0x1u << 2) /**< \brief (GMAC_NCFGR) Discard Non-VLAN FRAMES */\r
+#define GMAC_NCFGR_JFRAME (0x1u << 3) /**< \brief (GMAC_NCFGR) Jumbo Frame Size */\r
+#define GMAC_NCFGR_CAF (0x1u << 4) /**< \brief (GMAC_NCFGR) Copy All Frames */\r
+#define GMAC_NCFGR_NBC (0x1u << 5) /**< \brief (GMAC_NCFGR) No Broadcast */\r
+#define GMAC_NCFGR_MTIHEN (0x1u << 6) /**< \brief (GMAC_NCFGR) Multicast Hash Enable */\r
+#define GMAC_NCFGR_UNIHEN (0x1u << 7) /**< \brief (GMAC_NCFGR) Unicast Hash Enable */\r
+#define GMAC_NCFGR_MAXFS (0x1u << 8) /**< \brief (GMAC_NCFGR) 1536 Maximum Frame Size */\r
+#define GMAC_NCFGR_RTY (0x1u << 12) /**< \brief (GMAC_NCFGR) Retry Test */\r
+#define GMAC_NCFGR_PEN (0x1u << 13) /**< \brief (GMAC_NCFGR) Pause Enable */\r
+#define GMAC_NCFGR_RXBUFO_Pos 14\r
+#define GMAC_NCFGR_RXBUFO_Msk (0x3u << GMAC_NCFGR_RXBUFO_Pos) /**< \brief (GMAC_NCFGR) Receive Buffer Offset */\r
+#define GMAC_NCFGR_RXBUFO(value) ((GMAC_NCFGR_RXBUFO_Msk & ((value) << GMAC_NCFGR_RXBUFO_Pos)))\r
+#define GMAC_NCFGR_LFERD (0x1u << 16) /**< \brief (GMAC_NCFGR) Length Field Error Frame Discard */\r
+#define GMAC_NCFGR_RFCS (0x1u << 17) /**< \brief (GMAC_NCFGR) Remove FCS */\r
+#define GMAC_NCFGR_CLK_Pos 18\r
+#define GMAC_NCFGR_CLK_Msk (0x7u << GMAC_NCFGR_CLK_Pos) /**< \brief (GMAC_NCFGR) MDC CLock Division */\r
+#define GMAC_NCFGR_CLK_MCK_8 (0x0u << 18) /**< \brief (GMAC_NCFGR) MCK divided by 8 (MCK up to 20 MHz) */\r
+#define GMAC_NCFGR_CLK_MCK_16 (0x1u << 18) /**< \brief (GMAC_NCFGR) MCK divided by 16 (MCK up to 40 MHz) */\r
+#define GMAC_NCFGR_CLK_MCK_32 (0x2u << 18) /**< \brief (GMAC_NCFGR) MCK divided by 32 (MCK up to 80 MHz) */\r
+#define GMAC_NCFGR_CLK_MCK_48 (0x3u << 18) /**< \brief (GMAC_NCFGR) MCK divided by 48 (MCK up to 120MHz) */\r
+#define GMAC_NCFGR_CLK_MCK_64 (0x4u << 18) /**< \brief (GMAC_NCFGR) MCK divided by 64 (MCK up to 160 MHz) */\r
+#define GMAC_NCFGR_CLK_MCK_96 (0x5u << 18) /**< \brief (GMAC_NCFGR) MCK divided by 96 (MCK up to 240 MHz) */\r
+#define GMAC_NCFGR_DBW_Pos 21\r
+#define GMAC_NCFGR_DBW_Msk (0x3u << GMAC_NCFGR_DBW_Pos) /**< \brief (GMAC_NCFGR) Data Bus Width */\r
+#define GMAC_NCFGR_DBW(value) ((GMAC_NCFGR_DBW_Msk & ((value) << GMAC_NCFGR_DBW_Pos)))\r
+#define GMAC_NCFGR_DCPF (0x1u << 23) /**< \brief (GMAC_NCFGR) Disable Copy of Pause Frames */\r
+#define GMAC_NCFGR_RXCOEN (0x1u << 24) /**< \brief (GMAC_NCFGR) Receive Checksum Offload Enable */\r
+#define GMAC_NCFGR_EFRHD (0x1u << 25) /**< \brief (GMAC_NCFGR) Enable Frames Received in Half Duplex */\r
+#define GMAC_NCFGR_IRXFCS (0x1u << 26) /**< \brief (GMAC_NCFGR) Ignore RX FCS */\r
+#define GMAC_NCFGR_IPGSEN (0x1u << 28) /**< \brief (GMAC_NCFGR) IP Stretch Enable */\r
+#define GMAC_NCFGR_RXBP (0x1u << 29) /**< \brief (GMAC_NCFGR) Receive Bad Preamble */\r
+#define GMAC_NCFGR_IRXER (0x1u << 30) /**< \brief (GMAC_NCFGR) Ignore IPG GRXER */\r
+/* -------- GMAC_NSR : (GMAC Offset: 0x008) Network Status Register -------- */\r
+#define GMAC_NSR_MDIO (0x1u << 1) /**< \brief (GMAC_NSR) MDIO Input Status */\r
+#define GMAC_NSR_IDLE (0x1u << 2) /**< \brief (GMAC_NSR) PHY Management Logic Idle */\r
+/* -------- GMAC_UR : (GMAC Offset: 0x00C) User Register -------- */\r
+#define GMAC_UR_RMIIMII (0x1u << 0) /**< \brief (GMAC_UR) */\r
+/* -------- GMAC_DCFGR : (GMAC Offset: 0x010) DMA Configuration Register -------- */\r
+#define GMAC_DCFGR_FBLDO_Pos 0\r
+#define GMAC_DCFGR_FBLDO_Msk (0x1fu << GMAC_DCFGR_FBLDO_Pos) /**< \brief (GMAC_DCFGR) Fixed Burst Length for DMA Data Operations: */\r
+#define GMAC_DCFGR_FBLDO_SINGLE (0x1u << 0) /**< \brief (GMAC_DCFGR) 00001: Always use SINGLE AHB bursts */\r
+#define GMAC_DCFGR_FBLDO_INCR4 (0x4u << 0) /**< \brief (GMAC_DCFGR) 001xx: Attempt to use INCR4 AHB bursts (Default) */\r
+#define GMAC_DCFGR_FBLDO_INCR8 (0x8u << 0) /**< \brief (GMAC_DCFGR) 01xxx: Attempt to use INCR8 AHB bursts */\r
+#define GMAC_DCFGR_FBLDO_INCR16 (0x10u << 0) /**< \brief (GMAC_DCFGR) 1xxxx: Attempt to use INCR16 AHB bursts */\r
+#define GMAC_DCFGR_ESMA (0x1u << 6) /**< \brief (GMAC_DCFGR) Endian Swap Mode Enable for Management Descriptor Accesses */\r
+#define GMAC_DCFGR_ESPA (0x1u << 7) /**< \brief (GMAC_DCFGR) Endian Swap Mode Enable for Packet Data Accesses */\r
+#define GMAC_DCFGR_TXCOEN (0x1u << 11) /**< \brief (GMAC_DCFGR) Transmitter Checksum Generation Offload Enable */\r
+#define GMAC_DCFGR_DRBS_Pos 16\r
+#define GMAC_DCFGR_DRBS_Msk (0xffu << GMAC_DCFGR_DRBS_Pos) /**< \brief (GMAC_DCFGR) DMA Receive Buffer Size */\r
+#define GMAC_DCFGR_DRBS(value) ((GMAC_DCFGR_DRBS_Msk & ((value) << GMAC_DCFGR_DRBS_Pos)))\r
+/* -------- GMAC_TSR : (GMAC Offset: 0x014) Transmit Status Register -------- */\r
+#define GMAC_TSR_UBR (0x1u << 0) /**< \brief (GMAC_TSR) Used Bit Read */\r
+#define GMAC_TSR_COL (0x1u << 1) /**< \brief (GMAC_TSR) Collision Occurred */\r
+#define GMAC_TSR_RLE (0x1u << 2) /**< \brief (GMAC_TSR) Retry Limit Exceeded */\r
+#define GMAC_TSR_TXGO (0x1u << 3) /**< \brief (GMAC_TSR) Transmit Go */\r
+#define GMAC_TSR_TFC (0x1u << 4) /**< \brief (GMAC_TSR) Transmit Frame Corruption due to AHB error */\r
+#define GMAC_TSR_TXCOMP (0x1u << 5) /**< \brief (GMAC_TSR) Transmit Complete */\r
+#define GMAC_TSR_UND (0x1u << 6) /**< \brief (GMAC_TSR) Transmit Under Run */\r
+#define GMAC_TSR_HRESP (0x1u << 8) /**< \brief (GMAC_TSR) HRESP Not OK */\r
+/* -------- GMAC_RBQB : (GMAC Offset: 0x018) Receive Buffer Queue Base Address -------- */\r
+#define GMAC_RBQB_ADDR_Pos 2\r
+#define GMAC_RBQB_ADDR_Msk (0x3fffffffu << GMAC_RBQB_ADDR_Pos) /**< \brief (GMAC_RBQB) Receive buffer queue base address */\r
+#define GMAC_RBQB_ADDR(value) ((GMAC_RBQB_ADDR_Msk & ((value) << GMAC_RBQB_ADDR_Pos)))\r
+/* -------- GMAC_TBQB : (GMAC Offset: 0x01C) Transmit Buffer Queue Base Address -------- */\r
+#define GMAC_TBQB_ADDR_Pos 2\r
+#define GMAC_TBQB_ADDR_Msk (0x3fffffffu << GMAC_TBQB_ADDR_Pos) /**< \brief (GMAC_TBQB) Transmit Buffer Queue Base Address */\r
+#define GMAC_TBQB_ADDR(value) ((GMAC_TBQB_ADDR_Msk & ((value) << GMAC_TBQB_ADDR_Pos)))\r
+/* -------- GMAC_RSR : (GMAC Offset: 0x020) Receive Status Register -------- */\r
+#define GMAC_RSR_BNA (0x1u << 0) /**< \brief (GMAC_RSR) Buffer Not Available */\r
+#define GMAC_RSR_REC (0x1u << 1) /**< \brief (GMAC_RSR) Frame Received */\r
+#define GMAC_RSR_RXOVR (0x1u << 2) /**< \brief (GMAC_RSR) Receive Overrun */\r
+#define GMAC_RSR_HNO (0x1u << 3) /**< \brief (GMAC_RSR) HRESP Not OK */\r
+/* -------- GMAC_ISR : (GMAC Offset: 0x024) Interrupt Status Register -------- */\r
+#define GMAC_ISR_MFS (0x1u << 0) /**< \brief (GMAC_ISR) Management Frame Sent */\r
+#define GMAC_ISR_RCOMP (0x1u << 1) /**< \brief (GMAC_ISR) Receive Complete */\r
+#define GMAC_ISR_RXUBR (0x1u << 2) /**< \brief (GMAC_ISR) RX Used Bit Read */\r
+#define GMAC_ISR_TXUBR (0x1u << 3) /**< \brief (GMAC_ISR) TX Used Bit Read */\r
+#define GMAC_ISR_TUR (0x1u << 4) /**< \brief (GMAC_ISR) Transmit Under Run */\r
+#define GMAC_ISR_RLEX (0x1u << 5) /**< \brief (GMAC_ISR) Retry Limit Exceeded */\r
+#define GMAC_ISR_TFC (0x1u << 6) /**< \brief (GMAC_ISR) Transmit Frame Corruption due to AHB error */\r
+#define GMAC_ISR_TCOMP (0x1u << 7) /**< \brief (GMAC_ISR) Transmit Complete */\r
+#define GMAC_ISR_ROVR (0x1u << 10) /**< \brief (GMAC_ISR) Receive Overrun */\r
+#define GMAC_ISR_HRESP (0x1u << 11) /**< \brief (GMAC_ISR) HRESP Not OK */\r
+#define GMAC_ISR_PFNZ (0x1u << 12) /**< \brief (GMAC_ISR) Pause Frame with Non-zero Pause Quantum Received */\r
+#define GMAC_ISR_PTZ (0x1u << 13) /**< \brief (GMAC_ISR) Pause Time Zero */\r
+#define GMAC_ISR_PFTR (0x1u << 14) /**< \brief (GMAC_ISR) Pause Frame Transmitted */\r
+#define GMAC_ISR_DRQFR (0x1u << 18) /**< \brief (GMAC_ISR) PTP Delay Request Frame Received */\r
+#define GMAC_ISR_SFR (0x1u << 19) /**< \brief (GMAC_ISR) PTP Sync Frame Received */\r
+#define GMAC_ISR_DRQFT (0x1u << 20) /**< \brief (GMAC_ISR) PTP Delay Request Frame Transmitted */\r
+#define GMAC_ISR_SFT (0x1u << 21) /**< \brief (GMAC_ISR) PTP Sync Frame Transmitted */\r
+#define GMAC_ISR_PDRQFR (0x1u << 22) /**< \brief (GMAC_ISR) PDelay Request Frame Received */\r
+#define GMAC_ISR_PDRSFR (0x1u << 23) /**< \brief (GMAC_ISR) PDelay Response Frame Received */\r
+#define GMAC_ISR_PDRQFT (0x1u << 24) /**< \brief (GMAC_ISR) PDelay Request Frame Transmitted */\r
+#define GMAC_ISR_PDRSFT (0x1u << 25) /**< \brief (GMAC_ISR) PDelay Response Frame Transmitted */\r
+#define GMAC_ISR_SRI (0x1u << 26) /**< \brief (GMAC_ISR) TSU Seconds Register Increment */\r
+#define GMAC_ISR_WOL (0x1u << 28) /**< \brief (GMAC_ISR) Wake On LAN */\r
+/* -------- GMAC_IER : (GMAC Offset: 0x028) Interrupt Enable Register -------- */\r
+#define GMAC_IER_MFS (0x1u << 0) /**< \brief (GMAC_IER) Management Frame Sent */\r
+#define GMAC_IER_RCOMP (0x1u << 1) /**< \brief (GMAC_IER) Receive Complete */\r
+#define GMAC_IER_RXUBR (0x1u << 2) /**< \brief (GMAC_IER) RX Used Bit Read */\r
+#define GMAC_IER_TXUBR (0x1u << 3) /**< \brief (GMAC_IER) TX Used Bit Read */\r
+#define GMAC_IER_TUR (0x1u << 4) /**< \brief (GMAC_IER) Transmit Under Run */\r
+#define GMAC_IER_RLEX (0x1u << 5) /**< \brief (GMAC_IER) Retry Limit Exceeded or Late Collision */\r
+#define GMAC_IER_TFC (0x1u << 6) /**< \brief (GMAC_IER) Transmit Frame Corruption due to AHB error */\r
+#define GMAC_IER_TCOMP (0x1u << 7) /**< \brief (GMAC_IER) Transmit Complete */\r
+#define GMAC_IER_ROVR (0x1u << 10) /**< \brief (GMAC_IER) Receive Overrun */\r
+#define GMAC_IER_HRESP (0x1u << 11) /**< \brief (GMAC_IER) HRESP Not OK */\r
+#define GMAC_IER_PFNZ (0x1u << 12) /**< \brief (GMAC_IER) Pause Frame with Non-zero Pause Quantum Received */\r
+#define GMAC_IER_PTZ (0x1u << 13) /**< \brief (GMAC_IER) Pause Time Zero */\r
+#define GMAC_IER_PFTR (0x1u << 14) /**< \brief (GMAC_IER) Pause Frame Transmitted */\r
+#define GMAC_IER_EXINT (0x1u << 15) /**< \brief (GMAC_IER) External Interrupt */\r
+#define GMAC_IER_DRQFR (0x1u << 18) /**< \brief (GMAC_IER) PTP Delay Request Frame Received */\r
+#define GMAC_IER_SFR (0x1u << 19) /**< \brief (GMAC_IER) PTP Sync Frame Received */\r
+#define GMAC_IER_DRQFT (0x1u << 20) /**< \brief (GMAC_IER) PTP Delay Request Frame Transmitted */\r
+#define GMAC_IER_SFT (0x1u << 21) /**< \brief (GMAC_IER) PTP Sync Frame Transmitted */\r
+#define GMAC_IER_PDRQFR (0x1u << 22) /**< \brief (GMAC_IER) PDelay Request Frame Received */\r
+#define GMAC_IER_PDRSFR (0x1u << 23) /**< \brief (GMAC_IER) PDelay Response Frame Received */\r
+#define GMAC_IER_PDRQFT (0x1u << 24) /**< \brief (GMAC_IER) PDelay Request Frame Transmitted */\r
+#define GMAC_IER_PDRSFT (0x1u << 25) /**< \brief (GMAC_IER) PDelay Response Frame Transmitted */\r
+#define GMAC_IER_SRI (0x1u << 26) /**< \brief (GMAC_IER) TSU Seconds Register Increment */\r
+#define GMAC_IER_WOL (0x1u << 28) /**< \brief (GMAC_IER) Wake On LAN */\r
+/* -------- GMAC_IDR : (GMAC Offset: 0x02C) Interrupt Disable Register -------- */\r
+#define GMAC_IDR_MFS (0x1u << 0) /**< \brief (GMAC_IDR) Management Frame Sent */\r
+#define GMAC_IDR_RCOMP (0x1u << 1) /**< \brief (GMAC_IDR) Receive Complete */\r
+#define GMAC_IDR_RXUBR (0x1u << 2) /**< \brief (GMAC_IDR) RX Used Bit Read */\r
+#define GMAC_IDR_TXUBR (0x1u << 3) /**< \brief (GMAC_IDR) TX Used Bit Read */\r
+#define GMAC_IDR_TUR (0x1u << 4) /**< \brief (GMAC_IDR) Transmit Under Run */\r
+#define GMAC_IDR_RLEX (0x1u << 5) /**< \brief (GMAC_IDR) Retry Limit Exceeded or Late Collision */\r
+#define GMAC_IDR_TFC (0x1u << 6) /**< \brief (GMAC_IDR) Transmit Frame Corruption due to AHB error */\r
+#define GMAC_IDR_TCOMP (0x1u << 7) /**< \brief (GMAC_IDR) Transmit Complete */\r
+#define GMAC_IDR_ROVR (0x1u << 10) /**< \brief (GMAC_IDR) Receive Overrun */\r
+#define GMAC_IDR_HRESP (0x1u << 11) /**< \brief (GMAC_IDR) HRESP Not OK */\r
+#define GMAC_IDR_PFNZ (0x1u << 12) /**< \brief (GMAC_IDR) Pause Frame with Non-zero Pause Quantum Received */\r
+#define GMAC_IDR_PTZ (0x1u << 13) /**< \brief (GMAC_IDR) Pause Time Zero */\r
+#define GMAC_IDR_PFTR (0x1u << 14) /**< \brief (GMAC_IDR) Pause Frame Transmitted */\r
+#define GMAC_IDR_EXINT (0x1u << 15) /**< \brief (GMAC_IDR) External Interrupt */\r
+#define GMAC_IDR_DRQFR (0x1u << 18) /**< \brief (GMAC_IDR) PTP Delay Request Frame Received */\r
+#define GMAC_IDR_SFR (0x1u << 19) /**< \brief (GMAC_IDR) PTP Sync Frame Received */\r
+#define GMAC_IDR_DRQFT (0x1u << 20) /**< \brief (GMAC_IDR) PTP Delay Request Frame Transmitted */\r
+#define GMAC_IDR_SFT (0x1u << 21) /**< \brief (GMAC_IDR) PTP Sync Frame Transmitted */\r
+#define GMAC_IDR_PDRQFR (0x1u << 22) /**< \brief (GMAC_IDR) PDelay Request Frame Received */\r
+#define GMAC_IDR_PDRSFR (0x1u << 23) /**< \brief (GMAC_IDR) PDelay Response Frame Received */\r
+#define GMAC_IDR_PDRQFT (0x1u << 24) /**< \brief (GMAC_IDR) PDelay Request Frame Transmitted */\r
+#define GMAC_IDR_PDRSFT (0x1u << 25) /**< \brief (GMAC_IDR) PDelay Response Frame Transmitted */\r
+#define GMAC_IDR_SRI (0x1u << 26) /**< \brief (GMAC_IDR) TSU Seconds Register Increment */\r
+#define GMAC_IDR_WOL (0x1u << 28) /**< \brief (GMAC_IDR) Wake On LAN */\r
+/* -------- GMAC_IMR : (GMAC Offset: 0x030) Interrupt Mask Register -------- */\r
+#define GMAC_IMR_MFS (0x1u << 0) /**< \brief (GMAC_IMR) Management Frame Sent */\r
+#define GMAC_IMR_RCOMP (0x1u << 1) /**< \brief (GMAC_IMR) Receive Complete */\r
+#define GMAC_IMR_RXUBR (0x1u << 2) /**< \brief (GMAC_IMR) RX Used Bit Read */\r
+#define GMAC_IMR_TXUBR (0x1u << 3) /**< \brief (GMAC_IMR) TX Used Bit Read */\r
+#define GMAC_IMR_TUR (0x1u << 4) /**< \brief (GMAC_IMR) Transmit Under Run */\r
+#define GMAC_IMR_RLEX (0x1u << 5) /**< \brief (GMAC_IMR) Retry Limit Exceeded */\r
+#define GMAC_IMR_TFC (0x1u << 6) /**< \brief (GMAC_IMR) Transmit Frame Corruption due to AHB error */\r
+#define GMAC_IMR_TCOMP (0x1u << 7) /**< \brief (GMAC_IMR) Transmit Complete */\r
+#define GMAC_IMR_ROVR (0x1u << 10) /**< \brief (GMAC_IMR) Receive Overrun */\r
+#define GMAC_IMR_HRESP (0x1u << 11) /**< \brief (GMAC_IMR) HRESP Not OK */\r
+#define GMAC_IMR_PFNZ (0x1u << 12) /**< \brief (GMAC_IMR) Pause Frame with Non-zero Pause Quantum Received */\r
+#define GMAC_IMR_PTZ (0x1u << 13) /**< \brief (GMAC_IMR) Pause Time Zero */\r
+#define GMAC_IMR_PFTR (0x1u << 14) /**< \brief (GMAC_IMR) Pause Frame Transmitted */\r
+#define GMAC_IMR_EXINT (0x1u << 15) /**< \brief (GMAC_IMR) External Interrupt */\r
+#define GMAC_IMR_DRQFR (0x1u << 18) /**< \brief (GMAC_IMR) PTP Delay Request Frame Received */\r
+#define GMAC_IMR_SFR (0x1u << 19) /**< \brief (GMAC_IMR) PTP Sync Frame Received */\r
+#define GMAC_IMR_DRQFT (0x1u << 20) /**< \brief (GMAC_IMR) PTP Delay Request Frame Transmitted */\r
+#define GMAC_IMR_SFT (0x1u << 21) /**< \brief (GMAC_IMR) PTP Sync Frame Transmitted */\r
+#define GMAC_IMR_PDRQFR (0x1u << 22) /**< \brief (GMAC_IMR) PDelay Request Frame Received */\r
+#define GMAC_IMR_PDRSFR (0x1u << 23) /**< \brief (GMAC_IMR) PDelay Response Frame Received */\r
+#define GMAC_IMR_PDRQFT (0x1u << 24) /**< \brief (GMAC_IMR) PDelay Request Frame Transmitted */\r
+#define GMAC_IMR_PDRSFT (0x1u << 25) /**< \brief (GMAC_IMR) PDelay Response Frame Transmitted */\r
+/* -------- GMAC_MAN : (GMAC Offset: 0x034) PHY Maintenance Register -------- */\r
+#define GMAC_MAN_DATA_Pos 0\r
+#define GMAC_MAN_DATA_Msk (0xffffu << GMAC_MAN_DATA_Pos) /**< \brief (GMAC_MAN) PHY Data */\r
+#define GMAC_MAN_DATA(value) ((GMAC_MAN_DATA_Msk & ((value) << GMAC_MAN_DATA_Pos)))\r
+#define GMAC_MAN_WTN_Pos 16\r
+#define GMAC_MAN_WTN_Msk (0x3u << GMAC_MAN_WTN_Pos) /**< \brief (GMAC_MAN) Write Ten */\r
+#define GMAC_MAN_WTN(value) ((GMAC_MAN_WTN_Msk & ((value) << GMAC_MAN_WTN_Pos)))\r
+#define GMAC_MAN_REGA_Pos 18\r
+#define GMAC_MAN_REGA_Msk (0x1fu << GMAC_MAN_REGA_Pos) /**< \brief (GMAC_MAN) Register Address */\r
+#define GMAC_MAN_REGA(value) ((GMAC_MAN_REGA_Msk & ((value) << GMAC_MAN_REGA_Pos)))\r
+#define GMAC_MAN_PHYA_Pos 23\r
+#define GMAC_MAN_PHYA_Msk (0x1fu << GMAC_MAN_PHYA_Pos) /**< \brief (GMAC_MAN) PHY Address */\r
+#define GMAC_MAN_PHYA(value) ((GMAC_MAN_PHYA_Msk & ((value) << GMAC_MAN_PHYA_Pos)))\r
+#define GMAC_MAN_OP_Pos 28\r
+#define GMAC_MAN_OP_Msk (0x3u << GMAC_MAN_OP_Pos) /**< \brief (GMAC_MAN) Operation */\r
+#define GMAC_MAN_OP(value) ((GMAC_MAN_OP_Msk & ((value) << GMAC_MAN_OP_Pos)))\r
+#define GMAC_MAN_CLTTO (0x1u << 30) /**< \brief (GMAC_MAN) Clause 22 Operation */\r
+#define GMAC_MAN_WZO (0x1u << 31) /**< \brief (GMAC_MAN) Write ZERO */\r
+/* -------- GMAC_RPQ : (GMAC Offset: 0x038) Received Pause Quantum Register -------- */\r
+#define GMAC_RPQ_RPQ_Pos 0\r
+#define GMAC_RPQ_RPQ_Msk (0xffffu << GMAC_RPQ_RPQ_Pos) /**< \brief (GMAC_RPQ) Received Pause Quantum */\r
+/* -------- GMAC_TPQ : (GMAC Offset: 0x03C) Transmit Pause Quantum Register -------- */\r
+#define GMAC_TPQ_TPQ_Pos 0\r
+#define GMAC_TPQ_TPQ_Msk (0xffffu << GMAC_TPQ_TPQ_Pos) /**< \brief (GMAC_TPQ) Transmit Pause Quantum */\r
+#define GMAC_TPQ_TPQ(value) ((GMAC_TPQ_TPQ_Msk & ((value) << GMAC_TPQ_TPQ_Pos)))\r
+/* -------- GMAC_HRB : (GMAC Offset: 0x080) Hash Register Bottom [31:0] -------- */\r
+#define GMAC_HRB_ADDR_Pos 0\r
+#define GMAC_HRB_ADDR_Msk (0xffffffffu << GMAC_HRB_ADDR_Pos) /**< \brief (GMAC_HRB) Hash Address */\r
+#define GMAC_HRB_ADDR(value) ((GMAC_HRB_ADDR_Msk & ((value) << GMAC_HRB_ADDR_Pos)))\r
+/* -------- GMAC_HRT : (GMAC Offset: 0x084) Hash Register Top [63:32] -------- */\r
+#define GMAC_HRT_ADDR_Pos 0\r
+#define GMAC_HRT_ADDR_Msk (0xffffffffu << GMAC_HRT_ADDR_Pos) /**< \brief (GMAC_HRT) Hash Address */\r
+#define GMAC_HRT_ADDR(value) ((GMAC_HRT_ADDR_Msk & ((value) << GMAC_HRT_ADDR_Pos)))\r
+/* -------- GMAC_SAB1 : (GMAC Offset: 0x088) Specific Address 1 Bottom [31:0] Register -------- */\r
+#define GMAC_SAB1_ADDR_Pos 0\r
+#define GMAC_SAB1_ADDR_Msk (0xffffffffu << GMAC_SAB1_ADDR_Pos) /**< \brief (GMAC_SAB1) Specific Address 1 */\r
+#define GMAC_SAB1_ADDR(value) ((GMAC_SAB1_ADDR_Msk & ((value) << GMAC_SAB1_ADDR_Pos)))\r
+/* -------- GMAC_SAT1 : (GMAC Offset: 0x08C) Specific Address 1 Top [47:32] Register -------- */\r
+#define GMAC_SAT1_ADDR_Pos 0\r
+#define GMAC_SAT1_ADDR_Msk (0xffffu << GMAC_SAT1_ADDR_Pos) /**< \brief (GMAC_SAT1) Specific Address 1 */\r
+#define GMAC_SAT1_ADDR(value) ((GMAC_SAT1_ADDR_Msk & ((value) << GMAC_SAT1_ADDR_Pos)))\r
+/* -------- GMAC_SAB2 : (GMAC Offset: 0x090) Specific Address 2 Bottom [31:0] Register -------- */\r
+#define GMAC_SAB2_ADDR_Pos 0\r
+#define GMAC_SAB2_ADDR_Msk (0xffffffffu << GMAC_SAB2_ADDR_Pos) /**< \brief (GMAC_SAB2) Specific Address 2 */\r
+#define GMAC_SAB2_ADDR(value) ((GMAC_SAB2_ADDR_Msk & ((value) << GMAC_SAB2_ADDR_Pos)))\r
+/* -------- GMAC_SAT2 : (GMAC Offset: 0x094) Specific Address 2 Top [47:32] Register -------- */\r
+#define GMAC_SAT2_ADDR_Pos 0\r
+#define GMAC_SAT2_ADDR_Msk (0xffffu << GMAC_SAT2_ADDR_Pos) /**< \brief (GMAC_SAT2) Specific Address 2 */\r
+#define GMAC_SAT2_ADDR(value) ((GMAC_SAT2_ADDR_Msk & ((value) << GMAC_SAT2_ADDR_Pos)))\r
+/* -------- GMAC_SAB3 : (GMAC Offset: 0x098) Specific Address 3 Bottom [31:0] Register -------- */\r
+#define GMAC_SAB3_ADDR_Pos 0\r
+#define GMAC_SAB3_ADDR_Msk (0xffffffffu << GMAC_SAB3_ADDR_Pos) /**< \brief (GMAC_SAB3) Specific Address 3 */\r
+#define GMAC_SAB3_ADDR(value) ((GMAC_SAB3_ADDR_Msk & ((value) << GMAC_SAB3_ADDR_Pos)))\r
+/* -------- GMAC_SAT3 : (GMAC Offset: 0x09C) Specific Address 3 Top [47:32] Register -------- */\r
+#define GMAC_SAT3_ADDR_Pos 0\r
+#define GMAC_SAT3_ADDR_Msk (0xffffu << GMAC_SAT3_ADDR_Pos) /**< \brief (GMAC_SAT3) Specific Address 3 */\r
+#define GMAC_SAT3_ADDR(value) ((GMAC_SAT3_ADDR_Msk & ((value) << GMAC_SAT3_ADDR_Pos)))\r
+/* -------- GMAC_SAB4 : (GMAC Offset: 0x0A0) Specific Address 4 Bottom [31:0] Register -------- */\r
+#define GMAC_SAB4_ADDR_Pos 0\r
+#define GMAC_SAB4_ADDR_Msk (0xffffffffu << GMAC_SAB4_ADDR_Pos) /**< \brief (GMAC_SAB4) Specific Address 4 */\r
+#define GMAC_SAB4_ADDR(value) ((GMAC_SAB4_ADDR_Msk & ((value) << GMAC_SAB4_ADDR_Pos)))\r
+/* -------- GMAC_SAT4 : (GMAC Offset: 0x0A4) Specific Address 4 Top [47:32] Register -------- */\r
+#define GMAC_SAT4_ADDR_Pos 0\r
+#define GMAC_SAT4_ADDR_Msk (0xffffu << GMAC_SAT4_ADDR_Pos) /**< \brief (GMAC_SAT4) Specific Address 4 */\r
+#define GMAC_SAT4_ADDR(value) ((GMAC_SAT4_ADDR_Msk & ((value) << GMAC_SAT4_ADDR_Pos)))\r
+/* -------- GMAC_TIDM[4] : (GMAC Offset: 0x0A8) Type ID Match 1 Register -------- */\r
+#define GMAC_TIDM_TID_Pos 0\r
+#define GMAC_TIDM_TID_Msk (0xffffu << GMAC_TIDM_TID_Pos) /**< \brief (GMAC_TIDM[4]) Type ID Match 1 */\r
+#define GMAC_TIDM_TID(value) ((GMAC_TIDM_TID_Msk & ((value) << GMAC_TIDM_TID_Pos)))\r
+/* -------- GMAC_IPGS : (GMAC Offset: 0x0BC) IPG Stretch Register -------- */\r
+#define GMAC_IPGS_FL_Pos 0\r
+#define GMAC_IPGS_FL_Msk (0xffffu << GMAC_IPGS_FL_Pos) /**< \brief (GMAC_IPGS) Frame Length */\r
+#define GMAC_IPGS_FL(value) ((GMAC_IPGS_FL_Msk & ((value) << GMAC_IPGS_FL_Pos)))\r
+/* -------- GMAC_SVLAN : (GMAC Offset: 0x0C0) Stacked VLAN Register -------- */\r
+#define GMAC_SVLAN_VLAN_TYPE_Pos 0\r
+#define GMAC_SVLAN_VLAN_TYPE_Msk (0xffffu << GMAC_SVLAN_VLAN_TYPE_Pos) /**< \brief (GMAC_SVLAN) User Defined VLAN_TYPE Field */\r
+#define GMAC_SVLAN_VLAN_TYPE(value) ((GMAC_SVLAN_VLAN_TYPE_Msk & ((value) << GMAC_SVLAN_VLAN_TYPE_Pos)))\r
+#define GMAC_SVLAN_ESVLAN (0x1u << 31) /**< \brief (GMAC_SVLAN) Enable Stacked VLAN Processing Mode */\r
+/* -------- GMAC_TPFCP : (GMAC Offset: 0x0C4) Transmit PFC Pause Register -------- */\r
+#define GMAC_TPFCP_PEV_Pos 0\r
+#define GMAC_TPFCP_PEV_Msk (0xffu << GMAC_TPFCP_PEV_Pos) /**< \brief (GMAC_TPFCP) Priority Enable Vector */\r
+#define GMAC_TPFCP_PEV(value) ((GMAC_TPFCP_PEV_Msk & ((value) << GMAC_TPFCP_PEV_Pos)))\r
+#define GMAC_TPFCP_PQ_Pos 8\r
+#define GMAC_TPFCP_PQ_Msk (0xffu << GMAC_TPFCP_PQ_Pos) /**< \brief (GMAC_TPFCP) Pause Quantum */\r
+#define GMAC_TPFCP_PQ(value) ((GMAC_TPFCP_PQ_Msk & ((value) << GMAC_TPFCP_PQ_Pos)))\r
+/* -------- GMAC_SAMB1 : (GMAC Offset: 0x0C8) Specific Address 1 Mask Bottom [31:0] Register -------- */\r
+#define GMAC_SAMB1_ADDR_Pos 0\r
+#define GMAC_SAMB1_ADDR_Msk (0xffffffffu << GMAC_SAMB1_ADDR_Pos) /**< \brief (GMAC_SAMB1) Specific Address 1 Mask */\r
+#define GMAC_SAMB1_ADDR(value) ((GMAC_SAMB1_ADDR_Msk & ((value) << GMAC_SAMB1_ADDR_Pos)))\r
+/* -------- GMAC_SAMT1 : (GMAC Offset: 0x0CC) Specific Address 1 Mask Top [47:32] Register -------- */\r
+#define GMAC_SAMT1_ADDR_Pos 0\r
+#define GMAC_SAMT1_ADDR_Msk (0xffffu << GMAC_SAMT1_ADDR_Pos) /**< \brief (GMAC_SAMT1) Specific Address 1 Mask */\r
+#define GMAC_SAMT1_ADDR(value) ((GMAC_SAMT1_ADDR_Msk & ((value) << GMAC_SAMT1_ADDR_Pos)))\r
+/* -------- GMAC_OTLO : (GMAC Offset: 0x100) Octets Transmitted [31:0] Register -------- */\r
+#define GMAC_OTLO_TXO_Pos 0\r
+#define GMAC_OTLO_TXO_Msk (0xffffffffu << GMAC_OTLO_TXO_Pos) /**< \brief (GMAC_OTLO) Transmitted Octets */\r
+/* -------- GMAC_OTHI : (GMAC Offset: 0x104) Octets Transmitted [47:32] Register -------- */\r
+#define GMAC_OTHI_TXO_Pos 0\r
+#define GMAC_OTHI_TXO_Msk (0xffffu << GMAC_OTHI_TXO_Pos) /**< \brief (GMAC_OTHI) Transmitted Octets */\r
+/* -------- GMAC_FT : (GMAC Offset: 0x108) Frames Transmitted Register -------- */\r
+#define GMAC_FT_FTX_Pos 0\r
+#define GMAC_FT_FTX_Msk (0xffffffffu << GMAC_FT_FTX_Pos) /**< \brief (GMAC_FT) Frames Transmitted without Error */\r
+/* -------- GMAC_BCFT : (GMAC Offset: 0x10C) Broadcast Frames Transmitted Register -------- */\r
+#define GMAC_BCFT_BFTX_Pos 0\r
+#define GMAC_BCFT_BFTX_Msk (0xffffffffu << GMAC_BCFT_BFTX_Pos) /**< \brief (GMAC_BCFT) Broadcast Frames Transmitted without Error */\r
+/* -------- GMAC_MFT : (GMAC Offset: 0x110) Multicast Frames Transmitted Register -------- */\r
+#define GMAC_MFT_MFTX_Pos 0\r
+#define GMAC_MFT_MFTX_Msk (0xffffffffu << GMAC_MFT_MFTX_Pos) /**< \brief (GMAC_MFT) Multicast Frames Transmitted without Error */\r
+/* -------- GMAC_PFT : (GMAC Offset: 0x114) Pause Frames Transmitted Register -------- */\r
+#define GMAC_PFT_PFTX_Pos 0\r
+#define GMAC_PFT_PFTX_Msk (0xffffu << GMAC_PFT_PFTX_Pos) /**< \brief (GMAC_PFT) Pause Frames Transmitted Register */\r
+/* -------- GMAC_BFT64 : (GMAC Offset: 0x118) 64 Byte Frames Transmitted Register -------- */\r
+#define GMAC_BFT64_NFTX_Pos 0\r
+#define GMAC_BFT64_NFTX_Msk (0xffffffffu << GMAC_BFT64_NFTX_Pos) /**< \brief (GMAC_BFT64) 64 Byte Frames Transmitted without Error */\r
+/* -------- GMAC_TBFT127 : (GMAC Offset: 0x11C) 65 to 127 Byte Frames Transmitted Register -------- */\r
+#define GMAC_TBFT127_NFTX_Pos 0\r
+#define GMAC_TBFT127_NFTX_Msk (0xffffffffu << GMAC_TBFT127_NFTX_Pos) /**< \brief (GMAC_TBFT127) 65 to 127 Byte Frames Transmitted without Error */\r
+/* -------- GMAC_TBFT255 : (GMAC Offset: 0x120) 128 to 255 Byte Frames Transmitted Register -------- */\r
+#define GMAC_TBFT255_NFTX_Pos 0\r
+#define GMAC_TBFT255_NFTX_Msk (0xffffffffu << GMAC_TBFT255_NFTX_Pos) /**< \brief (GMAC_TBFT255) 128 to 255 Byte Frames Transmitted without Error */\r
+/* -------- GMAC_TBFT511 : (GMAC Offset: 0x124) 256 to 511 Byte Frames Transmitted Register -------- */\r
+#define GMAC_TBFT511_NFTX_Pos 0\r
+#define GMAC_TBFT511_NFTX_Msk (0xffffffffu << GMAC_TBFT511_NFTX_Pos) /**< \brief (GMAC_TBFT511) 256 to 511 Byte Frames Transmitted without Error */\r
+/* -------- GMAC_TBFT1023 : (GMAC Offset: 0x128) 512 to 1023 Byte Frames Transmitted Register -------- */\r
+#define GMAC_TBFT1023_NFTX_Pos 0\r
+#define GMAC_TBFT1023_NFTX_Msk (0xffffffffu << GMAC_TBFT1023_NFTX_Pos) /**< \brief (GMAC_TBFT1023) 512 to 1023 Byte Frames Transmitted without Error */\r
+/* -------- GMAC_TBFT1518 : (GMAC Offset: 0x12C) 1024 to 1518 Byte Frames Transmitted Register -------- */\r
+#define GMAC_TBFT1518_NFTX_Pos 0\r
+#define GMAC_TBFT1518_NFTX_Msk (0xffffffffu << GMAC_TBFT1518_NFTX_Pos) /**< \brief (GMAC_TBFT1518) 1024 to 1518 Byte Frames Transmitted without Error */\r
+/* -------- GMAC_GTBFT1518 : (GMAC Offset: 0x130) Greater Than 1518 Byte Frames Transmitted Register -------- */\r
+#define GMAC_GTBFT1518_NFTX_Pos 0\r
+#define GMAC_GTBFT1518_NFTX_Msk (0xffffffffu << GMAC_GTBFT1518_NFTX_Pos) /**< \brief (GMAC_GTBFT1518) Greater than 1518 Byte Frames Transmitted without Error */\r
+/* -------- GMAC_TUR : (GMAC Offset: 0x134) Transmit Under Runs Register -------- */\r
+#define GMAC_TUR_TXUNR_Pos 0\r
+#define GMAC_TUR_TXUNR_Msk (0x3ffu << GMAC_TUR_TXUNR_Pos) /**< \brief (GMAC_TUR) Transmit Under Runs */\r
+/* -------- GMAC_SCF : (GMAC Offset: 0x138) Single Collision Frames Register -------- */\r
+#define GMAC_SCF_SCOL_Pos 0\r
+#define GMAC_SCF_SCOL_Msk (0x3ffffu << GMAC_SCF_SCOL_Pos) /**< \brief (GMAC_SCF) Single Collision */\r
+/* -------- GMAC_MCF : (GMAC Offset: 0x13C) Multiple Collision Frames Register -------- */\r
+#define GMAC_MCF_MCOL_Pos 0\r
+#define GMAC_MCF_MCOL_Msk (0x3ffffu << GMAC_MCF_MCOL_Pos) /**< \brief (GMAC_MCF) Multiple Collision */\r
+/* -------- GMAC_EC : (GMAC Offset: 0x140) Excessive Collisions Register -------- */\r
+#define GMAC_EC_XCOL_Pos 0\r
+#define GMAC_EC_XCOL_Msk (0x3ffu << GMAC_EC_XCOL_Pos) /**< \brief (GMAC_EC) Excessive Collisions */\r
+/* -------- GMAC_LC : (GMAC Offset: 0x144) Late Collisions Register -------- */\r
+#define GMAC_LC_LCOL_Pos 0\r
+#define GMAC_LC_LCOL_Msk (0x3ffu << GMAC_LC_LCOL_Pos) /**< \brief (GMAC_LC) Late Collisions */\r
+/* -------- GMAC_DTF : (GMAC Offset: 0x148) Deferred Transmission Frames Register -------- */\r
+#define GMAC_DTF_DEFT_Pos 0\r
+#define GMAC_DTF_DEFT_Msk (0x3ffffu << GMAC_DTF_DEFT_Pos) /**< \brief (GMAC_DTF) Deferred Transmission */\r
+/* -------- GMAC_CSE : (GMAC Offset: 0x14C) Carrier Sense Errors Register -------- */\r
+#define GMAC_CSE_CSR_Pos 0\r
+#define GMAC_CSE_CSR_Msk (0x3ffu << GMAC_CSE_CSR_Pos) /**< \brief (GMAC_CSE) Carrier Sense Error */\r
+/* -------- GMAC_ORLO : (GMAC Offset: 0x150) Octets Received [31:0] Received -------- */\r
+#define GMAC_ORLO_RXO_Pos 0\r
+#define GMAC_ORLO_RXO_Msk (0xffffffffu << GMAC_ORLO_RXO_Pos) /**< \brief (GMAC_ORLO) Received Octets */\r
+/* -------- GMAC_ORHI : (GMAC Offset: 0x154) Octets Received [47:32] Received -------- */\r
+#define GMAC_ORHI_RXO_Pos 0\r
+#define GMAC_ORHI_RXO_Msk (0xffffu << GMAC_ORHI_RXO_Pos) /**< \brief (GMAC_ORHI) Received Octets */\r
+/* -------- GMAC_FR : (GMAC Offset: 0x158) Frames Received Register -------- */\r
+#define GMAC_FR_FRX_Pos 0\r
+#define GMAC_FR_FRX_Msk (0xffffffffu << GMAC_FR_FRX_Pos) /**< \brief (GMAC_FR) Frames Received without Error */\r
+/* -------- GMAC_BCFR : (GMAC Offset: 0x15C) Broadcast Frames Received Register -------- */\r
+#define GMAC_BCFR_BFRX_Pos 0\r
+#define GMAC_BCFR_BFRX_Msk (0xffffffffu << GMAC_BCFR_BFRX_Pos) /**< \brief (GMAC_BCFR) Broadcast Frames Received without Error */\r
+/* -------- GMAC_MFR : (GMAC Offset: 0x160) Multicast Frames Received Register -------- */\r
+#define GMAC_MFR_MFRX_Pos 0\r
+#define GMAC_MFR_MFRX_Msk (0xffffffffu << GMAC_MFR_MFRX_Pos) /**< \brief (GMAC_MFR) Multicast Frames Received without Error */\r
+/* -------- GMAC_PFR : (GMAC Offset: 0x164) Pause Frames Received Register -------- */\r
+#define GMAC_PFR_PFRX_Pos 0\r
+#define GMAC_PFR_PFRX_Msk (0xffffu << GMAC_PFR_PFRX_Pos) /**< \brief (GMAC_PFR) Pause Frames Received Register */\r
+/* -------- GMAC_BFR64 : (GMAC Offset: 0x168) 64 Byte Frames Received Register -------- */\r
+#define GMAC_BFR64_NFRX_Pos 0\r
+#define GMAC_BFR64_NFRX_Msk (0xffffffffu << GMAC_BFR64_NFRX_Pos) /**< \brief (GMAC_BFR64) 64 Byte Frames Received without Error */\r
+/* -------- GMAC_TBFR127 : (GMAC Offset: 0x16C) 65 to 127 Byte Frames Received Register -------- */\r
+#define GMAC_TBFR127_NFRX_Pos 0\r
+#define GMAC_TBFR127_NFRX_Msk (0xffffffffu << GMAC_TBFR127_NFRX_Pos) /**< \brief (GMAC_TBFR127) 65 to 127 Byte Frames Received without Error */\r
+/* -------- GMAC_TBFR255 : (GMAC Offset: 0x170) 128 to 255 Byte Frames Received Register -------- */\r
+#define GMAC_TBFR255_NFRX_Pos 0\r
+#define GMAC_TBFR255_NFRX_Msk (0xffffffffu << GMAC_TBFR255_NFRX_Pos) /**< \brief (GMAC_TBFR255) 128 to 255 Byte Frames Received without Error */\r
+/* -------- GMAC_TBFR511 : (GMAC Offset: 0x174) 256 to 511Byte Frames Received Register -------- */\r
+#define GMAC_TBFR511_NFRX_Pos 0\r
+#define GMAC_TBFR511_NFRX_Msk (0xffffffffu << GMAC_TBFR511_NFRX_Pos) /**< \brief (GMAC_TBFR511) 256 to 511 Byte Frames Received without Error */\r
+/* -------- GMAC_TBFR1023 : (GMAC Offset: 0x178) 512 to 1023 Byte Frames Received Register -------- */\r
+#define GMAC_TBFR1023_NFRX_Pos 0\r
+#define GMAC_TBFR1023_NFRX_Msk (0xffffffffu << GMAC_TBFR1023_NFRX_Pos) /**< \brief (GMAC_TBFR1023) 512 to 1023 Byte Frames Received without Error */\r
+/* -------- GMAC_TBFR1518 : (GMAC Offset: 0x17C) 1024 to 1518 Byte Frames Received Register -------- */\r
+#define GMAC_TBFR1518_NFRX_Pos 0\r
+#define GMAC_TBFR1518_NFRX_Msk (0xffffffffu << GMAC_TBFR1518_NFRX_Pos) /**< \brief (GMAC_TBFR1518) 1024 to 1518 Byte Frames Received without Error */\r
+/* -------- GMAC_TMXBFR : (GMAC Offset: 0x180) 1519 to Maximum Byte Frames Received Register -------- */\r
+#define GMAC_TMXBFR_NFRX_Pos 0\r
+#define GMAC_TMXBFR_NFRX_Msk (0xffffffffu << GMAC_TMXBFR_NFRX_Pos) /**< \brief (GMAC_TMXBFR) 1519 to Maximum Byte Frames Received without Error */\r
+/* -------- GMAC_UFR : (GMAC Offset: 0x184) Undersize Frames Received Register -------- */\r
+#define GMAC_UFR_UFRX_Pos 0\r
+#define GMAC_UFR_UFRX_Msk (0x3ffu << GMAC_UFR_UFRX_Pos) /**< \brief (GMAC_UFR) Undersize Frames Received */\r
+/* -------- GMAC_OFR : (GMAC Offset: 0x188) Oversize Frames Received Register -------- */\r
+#define GMAC_OFR_OFRX_Pos 0\r
+#define GMAC_OFR_OFRX_Msk (0x3ffu << GMAC_OFR_OFRX_Pos) /**< \brief (GMAC_OFR) Oversized Frames Received */\r
+/* -------- GMAC_JR : (GMAC Offset: 0x18C) Jabbers Received Register -------- */\r
+#define GMAC_JR_JRX_Pos 0\r
+#define GMAC_JR_JRX_Msk (0x3ffu << GMAC_JR_JRX_Pos) /**< \brief (GMAC_JR) Jabbers Received */\r
+/* -------- GMAC_FCSE : (GMAC Offset: 0x190) Frame Check Sequence Errors Register -------- */\r
+#define GMAC_FCSE_FCKR_Pos 0\r
+#define GMAC_FCSE_FCKR_Msk (0x3ffu << GMAC_FCSE_FCKR_Pos) /**< \brief (GMAC_FCSE) Frame Check Sequence Errors */\r
+/* -------- GMAC_LFFE : (GMAC Offset: 0x194) Length Field Frame Errors Register -------- */\r
+#define GMAC_LFFE_LFER_Pos 0\r
+#define GMAC_LFFE_LFER_Msk (0x3ffu << GMAC_LFFE_LFER_Pos) /**< \brief (GMAC_LFFE) Length Field Frame Errors */\r
+/* -------- GMAC_RSE : (GMAC Offset: 0x198) Receive Symbol Errors Register -------- */\r
+#define GMAC_RSE_RXSE_Pos 0\r
+#define GMAC_RSE_RXSE_Msk (0x3ffu << GMAC_RSE_RXSE_Pos) /**< \brief (GMAC_RSE) Receive Symbol Errors */\r
+/* -------- GMAC_AE : (GMAC Offset: 0x19C) Alignment Errors Register -------- */\r
+#define GMAC_AE_AER_Pos 0\r
+#define GMAC_AE_AER_Msk (0x3ffu << GMAC_AE_AER_Pos) /**< \brief (GMAC_AE) Alignment Errors */\r
+/* -------- GMAC_RRE : (GMAC Offset: 0x1A0) Receive Resource Errors Register -------- */\r
+#define GMAC_RRE_RXRER_Pos 0\r
+#define GMAC_RRE_RXRER_Msk (0x3ffffu << GMAC_RRE_RXRER_Pos) /**< \brief (GMAC_RRE) Receive Resource Errors */\r
+/* -------- GMAC_ROE : (GMAC Offset: 0x1A4) Receive Overrun Register -------- */\r
+#define GMAC_ROE_RXOVR_Pos 0\r
+#define GMAC_ROE_RXOVR_Msk (0x3ffu << GMAC_ROE_RXOVR_Pos) /**< \brief (GMAC_ROE) Receive Overruns */\r
+/* -------- GMAC_IHCE : (GMAC Offset: 0x1A8) IP Header Checksum Errors Register -------- */\r
+#define GMAC_IHCE_HCKER_Pos 0\r
+#define GMAC_IHCE_HCKER_Msk (0xffu << GMAC_IHCE_HCKER_Pos) /**< \brief (GMAC_IHCE) IP Header Checksum Errors */\r
+/* -------- GMAC_TCE : (GMAC Offset: 0x1AC) TCP Checksum Errors Register -------- */\r
+#define GMAC_TCE_TCKER_Pos 0\r
+#define GMAC_TCE_TCKER_Msk (0xffu << GMAC_TCE_TCKER_Pos) /**< \brief (GMAC_TCE) TCP Checksum Errors */\r
+/* -------- GMAC_UCE : (GMAC Offset: 0x1B0) UDP Checksum Errors Register -------- */\r
+#define GMAC_UCE_UCKER_Pos 0\r
+#define GMAC_UCE_UCKER_Msk (0xffu << GMAC_UCE_UCKER_Pos) /**< \brief (GMAC_UCE) UDP Checksum Errors */\r
+/* -------- GMAC_TSSS : (GMAC Offset: 0x1C8) 1588 Timer Sync Strobe Seconds Register -------- */\r
+#define GMAC_TSSS_VTS_Pos 0\r
+#define GMAC_TSSS_VTS_Msk (0xffffffffu << GMAC_TSSS_VTS_Pos) /**< \brief (GMAC_TSSS) Value of Timer Seconds Register Capture */\r
+#define GMAC_TSSS_VTS(value) ((GMAC_TSSS_VTS_Msk & ((value) << GMAC_TSSS_VTS_Pos)))\r
+/* -------- GMAC_TSSN : (GMAC Offset: 0x1CC) 1588 Timer Sync Strobe Nanoseconds Register -------- */\r
+#define GMAC_TSSN_VTN_Pos 0\r
+#define GMAC_TSSN_VTN_Msk (0x3fffffffu << GMAC_TSSN_VTN_Pos) /**< \brief (GMAC_TSSN) Value Timer Nanoseconds Register Capture */\r
+#define GMAC_TSSN_VTN(value) ((GMAC_TSSN_VTN_Msk & ((value) << GMAC_TSSN_VTN_Pos)))\r
+/* -------- GMAC_TS : (GMAC Offset: 0x1D0) 1588 Timer Seconds Register -------- */\r
+#define GMAC_TS_TCS_Pos 0\r
+#define GMAC_TS_TCS_Msk (0xffffffffu << GMAC_TS_TCS_Pos) /**< \brief (GMAC_TS) Timer Count in Seconds */\r
+#define GMAC_TS_TCS(value) ((GMAC_TS_TCS_Msk & ((value) << GMAC_TS_TCS_Pos)))\r
+/* -------- GMAC_TN : (GMAC Offset: 0x1D4) 1588 Timer Nanoseconds Register -------- */\r
+#define GMAC_TN_TNS_Pos 0\r
+#define GMAC_TN_TNS_Msk (0x3fffffffu << GMAC_TN_TNS_Pos) /**< \brief (GMAC_TN) Timer Count in Nanoseconds */\r
+#define GMAC_TN_TNS(value) ((GMAC_TN_TNS_Msk & ((value) << GMAC_TN_TNS_Pos)))\r
+/* -------- GMAC_TA : (GMAC Offset: 0x1D8) 1588 Timer Adjust Register -------- */\r
+#define GMAC_TA_ITDT_Pos 0\r
+#define GMAC_TA_ITDT_Msk (0x3fffffffu << GMAC_TA_ITDT_Pos) /**< \brief (GMAC_TA) Increment/Decrement */\r
+#define GMAC_TA_ITDT(value) ((GMAC_TA_ITDT_Msk & ((value) << GMAC_TA_ITDT_Pos)))\r
+#define GMAC_TA_ADJ (0x1u << 31) /**< \brief (GMAC_TA) Adjust 1588 Timer */\r
+/* -------- GMAC_TI : (GMAC Offset: 0x1DC) 1588 Timer Increment Register -------- */\r
+#define GMAC_TI_CNS_Pos 0\r
+#define GMAC_TI_CNS_Msk (0xffu << GMAC_TI_CNS_Pos) /**< \brief (GMAC_TI) Count Nanoseconds */\r
+#define GMAC_TI_CNS(value) ((GMAC_TI_CNS_Msk & ((value) << GMAC_TI_CNS_Pos)))\r
+#define GMAC_TI_ACNS_Pos 8\r
+#define GMAC_TI_ACNS_Msk (0xffu << GMAC_TI_ACNS_Pos) /**< \brief (GMAC_TI) Alternative Count Nanoseconds */\r
+#define GMAC_TI_ACNS(value) ((GMAC_TI_ACNS_Msk & ((value) << GMAC_TI_ACNS_Pos)))\r
+#define GMAC_TI_NIT_Pos 16\r
+#define GMAC_TI_NIT_Msk (0xffu << GMAC_TI_NIT_Pos) /**< \brief (GMAC_TI) Number of Increments */\r
+#define GMAC_TI_NIT(value) ((GMAC_TI_NIT_Msk & ((value) << GMAC_TI_NIT_Pos)))\r
+/* -------- GMAC_EFTS : (GMAC Offset: 0x1E0) PTP Event Frame Transmitted Seconds -------- */\r
+#define GMAC_EFTS_RUD_Pos 0\r
+#define GMAC_EFTS_RUD_Msk (0xffffffffu << GMAC_EFTS_RUD_Pos) /**< \brief (GMAC_EFTS) Register Update */\r
+/* -------- GMAC_EFTN : (GMAC Offset: 0x1E4) PTP Event Frame Transmitted Nanoseconds -------- */\r
+#define GMAC_EFTN_RUD_Pos 0\r
+#define GMAC_EFTN_RUD_Msk (0x3fffffffu << GMAC_EFTN_RUD_Pos) /**< \brief (GMAC_EFTN) Register Update */\r
+/* -------- GMAC_EFRS : (GMAC Offset: 0x1E8) PTP Event Frame Received Seconds -------- */\r
+#define GMAC_EFRS_RUD_Pos 0\r
+#define GMAC_EFRS_RUD_Msk (0xffffffffu << GMAC_EFRS_RUD_Pos) /**< \brief (GMAC_EFRS) Register Update */\r
+/* -------- GMAC_EFRN : (GMAC Offset: 0x1EC) PTP Event Frame Received Nanoseconds -------- */\r
+#define GMAC_EFRN_RUD_Pos 0\r
+#define GMAC_EFRN_RUD_Msk (0x3fffffffu << GMAC_EFRN_RUD_Pos) /**< \brief (GMAC_EFRN) Register Update */\r
+/* -------- GMAC_PEFTS : (GMAC Offset: 0x1F0) PTP Peer Event Frame Transmitted Seconds -------- */\r
+#define GMAC_PEFTS_RUD_Pos 0\r
+#define GMAC_PEFTS_RUD_Msk (0xffffffffu << GMAC_PEFTS_RUD_Pos) /**< \brief (GMAC_PEFTS) Register Update */\r
+/* -------- GMAC_PEFTN : (GMAC Offset: 0x1F4) PTP Peer Event Frame Transmitted Nanoseconds -------- */\r
+#define GMAC_PEFTN_RUD_Pos 0\r
+#define GMAC_PEFTN_RUD_Msk (0x3fffffffu << GMAC_PEFTN_RUD_Pos) /**< \brief (GMAC_PEFTN) Register Update */\r
+/* -------- GMAC_PEFRS : (GMAC Offset: 0x1F8) PTP Peer Event Frame Received Seconds -------- */\r
+#define GMAC_PEFRS_RUD_Pos 0\r
+#define GMAC_PEFRS_RUD_Msk (0xffffffffu << GMAC_PEFRS_RUD_Pos) /**< \brief (GMAC_PEFRS) Register Update */\r
+/* -------- GMAC_PEFRN : (GMAC Offset: 0x1FC) PTP Peer Event Frame Received Nanoseconds -------- */\r
+#define GMAC_PEFRN_RUD_Pos 0\r
+#define GMAC_PEFRN_RUD_Msk (0x3fffffffu << GMAC_PEFRN_RUD_Pos) /**< \brief (GMAC_PEFRN) Register Update */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM4E_GMAC_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4E_GPBR_COMPONENT_\r
+#define _SAM4E_GPBR_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR General Purpose Backup Register */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM4E_GPBR General Purpose Backup Register */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Gpbr hardware registers */\r
+typedef struct {\r
+ RwReg SYS_GPBR[20]; /**< \brief (Gpbr Offset: 0x0) General Purpose Backup Register */\r
+} Gpbr;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- SYS_GPBR[20] : (GPBR Offset: 0x0) General Purpose Backup Register -------- */\r
+#define SYS_GPBR_GPBR_VALUE_Pos 0\r
+#define SYS_GPBR_GPBR_VALUE_Msk (0xffffffffu << SYS_GPBR_GPBR_VALUE_Pos) /**< \brief (SYS_GPBR[20]) Value of GPBR x */\r
+#define SYS_GPBR_GPBR_VALUE(value) ((SYS_GPBR_GPBR_VALUE_Msk & ((value) << SYS_GPBR_GPBR_VALUE_Pos)))\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM4E_GPBR_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4E_HSMCI_COMPONENT_\r
+#define _SAM4E_HSMCI_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR High Speed MultiMedia Card Interface */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM4E_HSMCI High Speed MultiMedia Card Interface */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Hsmci hardware registers */\r
+typedef struct {\r
+ WoReg HSMCI_CR; /**< \brief (Hsmci Offset: 0x00) Control Register */\r
+ RwReg HSMCI_MR; /**< \brief (Hsmci Offset: 0x04) Mode Register */\r
+ RwReg HSMCI_DTOR; /**< \brief (Hsmci Offset: 0x08) Data Timeout Register */\r
+ RwReg HSMCI_SDCR; /**< \brief (Hsmci Offset: 0x0C) SD/SDIO Card Register */\r
+ RwReg HSMCI_ARGR; /**< \brief (Hsmci Offset: 0x10) Argument Register */\r
+ WoReg HSMCI_CMDR; /**< \brief (Hsmci Offset: 0x14) Command Register */\r
+ RwReg HSMCI_BLKR; /**< \brief (Hsmci Offset: 0x18) Block Register */\r
+ RwReg HSMCI_CSTOR; /**< \brief (Hsmci Offset: 0x1C) Completion Signal Timeout Register */\r
+ RoReg HSMCI_RSPR[4]; /**< \brief (Hsmci Offset: 0x20) Response Register */\r
+ RoReg HSMCI_RDR; /**< \brief (Hsmci Offset: 0x30) Receive Data Register */\r
+ WoReg HSMCI_TDR; /**< \brief (Hsmci Offset: 0x34) Transmit Data Register */\r
+ RoReg Reserved1[2];\r
+ RoReg HSMCI_SR; /**< \brief (Hsmci Offset: 0x40) Status Register */\r
+ WoReg HSMCI_IER; /**< \brief (Hsmci Offset: 0x44) Interrupt Enable Register */\r
+ WoReg HSMCI_IDR; /**< \brief (Hsmci Offset: 0x48) Interrupt Disable Register */\r
+ RoReg HSMCI_IMR; /**< \brief (Hsmci Offset: 0x4C) Interrupt Mask Register */\r
+ RoReg Reserved2[1];\r
+ RwReg HSMCI_CFG; /**< \brief (Hsmci Offset: 0x54) Configuration Register */\r
+ RoReg Reserved3[35];\r
+ RwReg HSMCI_WPMR; /**< \brief (Hsmci Offset: 0xE4) Write Protection Mode Register */\r
+ RoReg HSMCI_WPSR; /**< \brief (Hsmci Offset: 0xE8) Write Protection Status Register */\r
+ RoReg Reserved4[5];\r
+ RwReg HSMCI_RPR; /**< \brief (Hsmci Offset: 0x100) Receive Pointer Register */\r
+ RwReg HSMCI_RCR; /**< \brief (Hsmci Offset: 0x104) Receive Counter Register */\r
+ RwReg HSMCI_TPR; /**< \brief (Hsmci Offset: 0x108) Transmit Pointer Register */\r
+ RwReg HSMCI_TCR; /**< \brief (Hsmci Offset: 0x10C) Transmit Counter Register */\r
+ RwReg HSMCI_RNPR; /**< \brief (Hsmci Offset: 0x110) Receive Next Pointer Register */\r
+ RwReg HSMCI_RNCR; /**< \brief (Hsmci Offset: 0x114) Receive Next Counter Register */\r
+ RwReg HSMCI_TNPR; /**< \brief (Hsmci Offset: 0x118) Transmit Next Pointer Register */\r
+ RwReg HSMCI_TNCR; /**< \brief (Hsmci Offset: 0x11C) Transmit Next Counter Register */\r
+ WoReg HSMCI_PTCR; /**< \brief (Hsmci Offset: 0x120) Transfer Control Register */\r
+ RoReg HSMCI_PTSR; /**< \brief (Hsmci Offset: 0x124) Transfer Status Register */\r
+ RoReg Reserved5[54];\r
+ RwReg HSMCI_FIFO[256]; /**< \brief (Hsmci Offset: 0x200) FIFO Memory Aperture0 */\r
+} Hsmci;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- HSMCI_CR : (HSMCI Offset: 0x00) Control Register -------- */\r
+#define HSMCI_CR_MCIEN (0x1u << 0) /**< \brief (HSMCI_CR) Multi-Media Interface Enable */\r
+#define HSMCI_CR_MCIDIS (0x1u << 1) /**< \brief (HSMCI_CR) Multi-Media Interface Disable */\r
+#define HSMCI_CR_PWSEN (0x1u << 2) /**< \brief (HSMCI_CR) Power Save Mode Enable */\r
+#define HSMCI_CR_PWSDIS (0x1u << 3) /**< \brief (HSMCI_CR) Power Save Mode Disable */\r
+#define HSMCI_CR_SWRST (0x1u << 7) /**< \brief (HSMCI_CR) Software Reset */\r
+/* -------- HSMCI_MR : (HSMCI Offset: 0x04) Mode Register -------- */\r
+#define HSMCI_MR_CLKDIV_Pos 0\r
+#define HSMCI_MR_CLKDIV_Msk (0xffu << HSMCI_MR_CLKDIV_Pos) /**< \brief (HSMCI_MR) Clock Divider */\r
+#define HSMCI_MR_CLKDIV(value) ((HSMCI_MR_CLKDIV_Msk & ((value) << HSMCI_MR_CLKDIV_Pos)))\r
+#define HSMCI_MR_PWSDIV_Pos 8\r
+#define HSMCI_MR_PWSDIV_Msk (0x7u << HSMCI_MR_PWSDIV_Pos) /**< \brief (HSMCI_MR) Power Saving Divider */\r
+#define HSMCI_MR_PWSDIV(value) ((HSMCI_MR_PWSDIV_Msk & ((value) << HSMCI_MR_PWSDIV_Pos)))\r
+#define HSMCI_MR_RDPROOF (0x1u << 11) /**< \brief (HSMCI_MR) Read Proof Enable */\r
+#define HSMCI_MR_WRPROOF (0x1u << 12) /**< \brief (HSMCI_MR) Write Proof Enable */\r
+#define HSMCI_MR_FBYTE (0x1u << 13) /**< \brief (HSMCI_MR) Force Byte Transfer */\r
+#define HSMCI_MR_PADV (0x1u << 14) /**< \brief (HSMCI_MR) Padding Value */\r
+#define HSMCI_MR_PDCMODE (0x1u << 15) /**< \brief (HSMCI_MR) PDC-oriented Mode */\r
+#define HSMCI_MR_CLKODD (0x1u << 16) /**< \brief (HSMCI_MR) Clock divider is odd */\r
+/* -------- HSMCI_DTOR : (HSMCI Offset: 0x08) Data Timeout Register -------- */\r
+#define HSMCI_DTOR_DTOCYC_Pos 0\r
+#define HSMCI_DTOR_DTOCYC_Msk (0xfu << HSMCI_DTOR_DTOCYC_Pos) /**< \brief (HSMCI_DTOR) Data Timeout Cycle Number */\r
+#define HSMCI_DTOR_DTOCYC(value) ((HSMCI_DTOR_DTOCYC_Msk & ((value) << HSMCI_DTOR_DTOCYC_Pos)))\r
+#define HSMCI_DTOR_DTOMUL_Pos 4\r
+#define HSMCI_DTOR_DTOMUL_Msk (0x7u << HSMCI_DTOR_DTOMUL_Pos) /**< \brief (HSMCI_DTOR) Data Timeout Multiplier */\r
+#define HSMCI_DTOR_DTOMUL_1 (0x0u << 4) /**< \brief (HSMCI_DTOR) DTOCYC */\r
+#define HSMCI_DTOR_DTOMUL_16 (0x1u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 16 */\r
+#define HSMCI_DTOR_DTOMUL_128 (0x2u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 128 */\r
+#define HSMCI_DTOR_DTOMUL_256 (0x3u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 256 */\r
+#define HSMCI_DTOR_DTOMUL_1024 (0x4u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 1024 */\r
+#define HSMCI_DTOR_DTOMUL_4096 (0x5u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 4096 */\r
+#define HSMCI_DTOR_DTOMUL_65536 (0x6u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 65536 */\r
+#define HSMCI_DTOR_DTOMUL_1048576 (0x7u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 1048576 */\r
+/* -------- HSMCI_SDCR : (HSMCI Offset: 0x0C) SD/SDIO Card Register -------- */\r
+#define HSMCI_SDCR_SDCSEL_Pos 0\r
+#define HSMCI_SDCR_SDCSEL_Msk (0x3u << HSMCI_SDCR_SDCSEL_Pos) /**< \brief (HSMCI_SDCR) SDCard/SDIO Slot */\r
+#define HSMCI_SDCR_SDCSEL_SLOTA (0x0u << 0) /**< \brief (HSMCI_SDCR) Slot A is selected. */\r
+#define HSMCI_SDCR_SDCSEL_SLOTB (0x1u << 0) /**< \brief (HSMCI_SDCR) - */\r
+#define HSMCI_SDCR_SDCSEL_SLOTC (0x2u << 0) /**< \brief (HSMCI_SDCR) - */\r
+#define HSMCI_SDCR_SDCSEL_SLOTD (0x3u << 0) /**< \brief (HSMCI_SDCR) - */\r
+#define HSMCI_SDCR_SDCBUS_Pos 6\r
+#define HSMCI_SDCR_SDCBUS_Msk (0x3u << HSMCI_SDCR_SDCBUS_Pos) /**< \brief (HSMCI_SDCR) SDCard/SDIO Bus Width */\r
+#define HSMCI_SDCR_SDCBUS_1 (0x0u << 6) /**< \brief (HSMCI_SDCR) 1 bit */\r
+#define HSMCI_SDCR_SDCBUS_4 (0x2u << 6) /**< \brief (HSMCI_SDCR) 4 bit */\r
+#define HSMCI_SDCR_SDCBUS_8 (0x3u << 6) /**< \brief (HSMCI_SDCR) 8 bit */\r
+/* -------- HSMCI_ARGR : (HSMCI Offset: 0x10) Argument Register -------- */\r
+#define HSMCI_ARGR_ARG_Pos 0\r
+#define HSMCI_ARGR_ARG_Msk (0xffffffffu << HSMCI_ARGR_ARG_Pos) /**< \brief (HSMCI_ARGR) Command Argument */\r
+#define HSMCI_ARGR_ARG(value) ((HSMCI_ARGR_ARG_Msk & ((value) << HSMCI_ARGR_ARG_Pos)))\r
+/* -------- HSMCI_CMDR : (HSMCI Offset: 0x14) Command Register -------- */\r
+#define HSMCI_CMDR_CMDNB_Pos 0\r
+#define HSMCI_CMDR_CMDNB_Msk (0x3fu << HSMCI_CMDR_CMDNB_Pos) /**< \brief (HSMCI_CMDR) Command Number */\r
+#define HSMCI_CMDR_CMDNB(value) ((HSMCI_CMDR_CMDNB_Msk & ((value) << HSMCI_CMDR_CMDNB_Pos)))\r
+#define HSMCI_CMDR_RSPTYP_Pos 6\r
+#define HSMCI_CMDR_RSPTYP_Msk (0x3u << HSMCI_CMDR_RSPTYP_Pos) /**< \brief (HSMCI_CMDR) Response Type */\r
+#define HSMCI_CMDR_RSPTYP_NORESP (0x0u << 6) /**< \brief (HSMCI_CMDR) No response. */\r
+#define HSMCI_CMDR_RSPTYP_48_BIT (0x1u << 6) /**< \brief (HSMCI_CMDR) 48-bit response. */\r
+#define HSMCI_CMDR_RSPTYP_136_BIT (0x2u << 6) /**< \brief (HSMCI_CMDR) 136-bit response. */\r
+#define HSMCI_CMDR_RSPTYP_R1B (0x3u << 6) /**< \brief (HSMCI_CMDR) R1b response type */\r
+#define HSMCI_CMDR_SPCMD_Pos 8\r
+#define HSMCI_CMDR_SPCMD_Msk (0x7u << HSMCI_CMDR_SPCMD_Pos) /**< \brief (HSMCI_CMDR) Special Command */\r
+#define HSMCI_CMDR_SPCMD_STD (0x0u << 8) /**< \brief (HSMCI_CMDR) Not a special CMD. */\r
+#define HSMCI_CMDR_SPCMD_INIT (0x1u << 8) /**< \brief (HSMCI_CMDR) Initialization CMD: 74 clock cycles for initialization sequence. */\r
+#define HSMCI_CMDR_SPCMD_SYNC (0x2u << 8) /**< \brief (HSMCI_CMDR) Synchronized CMD: Wait for the end of the current data block transfer before sending the pending command. */\r
+#define HSMCI_CMDR_SPCMD_CE_ATA (0x3u << 8) /**< \brief (HSMCI_CMDR) CE-ATA Completion Signal disable Command. The host cancels the ability for the device to return a command completion signal on the command line. */\r
+#define HSMCI_CMDR_SPCMD_IT_CMD (0x4u << 8) /**< \brief (HSMCI_CMDR) Interrupt command: Corresponds to the Interrupt Mode (CMD40). */\r
+#define HSMCI_CMDR_SPCMD_IT_RESP (0x5u << 8) /**< \brief (HSMCI_CMDR) Interrupt response: Corresponds to the Interrupt Mode (CMD40). */\r
+#define HSMCI_CMDR_SPCMD_BOR (0x6u << 8) /**< \brief (HSMCI_CMDR) Boot Operation Request. Start a boot operation mode, the host processor can read boot data from the MMC device directly. */\r
+#define HSMCI_CMDR_SPCMD_EBO (0x7u << 8) /**< \brief (HSMCI_CMDR) End Boot Operation. This command allows the host processor to terminate the boot operation mode. */\r
+#define HSMCI_CMDR_OPDCMD (0x1u << 11) /**< \brief (HSMCI_CMDR) Open Drain Command */\r
+#define HSMCI_CMDR_OPDCMD_PUSHPULL (0x0u << 11) /**< \brief (HSMCI_CMDR) Push pull command. */\r
+#define HSMCI_CMDR_OPDCMD_OPENDRAIN (0x1u << 11) /**< \brief (HSMCI_CMDR) Open drain command. */\r
+#define HSMCI_CMDR_MAXLAT (0x1u << 12) /**< \brief (HSMCI_CMDR) Max Latency for Command to Response */\r
+#define HSMCI_CMDR_MAXLAT_5 (0x0u << 12) /**< \brief (HSMCI_CMDR) 5-cycle max latency. */\r
+#define HSMCI_CMDR_MAXLAT_64 (0x1u << 12) /**< \brief (HSMCI_CMDR) 64-cycle max latency. */\r
+#define HSMCI_CMDR_TRCMD_Pos 16\r
+#define HSMCI_CMDR_TRCMD_Msk (0x3u << HSMCI_CMDR_TRCMD_Pos) /**< \brief (HSMCI_CMDR) Transfer Command */\r
+#define HSMCI_CMDR_TRCMD_NO_DATA (0x0u << 16) /**< \brief (HSMCI_CMDR) No data transfer */\r
+#define HSMCI_CMDR_TRCMD_START_DATA (0x1u << 16) /**< \brief (HSMCI_CMDR) Start data transfer */\r
+#define HSMCI_CMDR_TRCMD_STOP_DATA (0x2u << 16) /**< \brief (HSMCI_CMDR) Stop data transfer */\r
+#define HSMCI_CMDR_TRDIR (0x1u << 18) /**< \brief (HSMCI_CMDR) Transfer Direction */\r
+#define HSMCI_CMDR_TRDIR_WRITE (0x0u << 18) /**< \brief (HSMCI_CMDR) Write. */\r
+#define HSMCI_CMDR_TRDIR_READ (0x1u << 18) /**< \brief (HSMCI_CMDR) Read. */\r
+#define HSMCI_CMDR_TRTYP_Pos 19\r
+#define HSMCI_CMDR_TRTYP_Msk (0x7u << HSMCI_CMDR_TRTYP_Pos) /**< \brief (HSMCI_CMDR) Transfer Type */\r
+#define HSMCI_CMDR_TRTYP_SINGLE (0x0u << 19) /**< \brief (HSMCI_CMDR) MMC/SD Card Single Block */\r
+#define HSMCI_CMDR_TRTYP_MULTIPLE (0x1u << 19) /**< \brief (HSMCI_CMDR) MMC/SD Card Multiple Block */\r
+#define HSMCI_CMDR_TRTYP_STREAM (0x2u << 19) /**< \brief (HSMCI_CMDR) MMC Stream */\r
+#define HSMCI_CMDR_TRTYP_BYTE (0x4u << 19) /**< \brief (HSMCI_CMDR) SDIO Byte */\r
+#define HSMCI_CMDR_TRTYP_BLOCK (0x5u << 19) /**< \brief (HSMCI_CMDR) SDIO Block */\r
+#define HSMCI_CMDR_IOSPCMD_Pos 24\r
+#define HSMCI_CMDR_IOSPCMD_Msk (0x3u << HSMCI_CMDR_IOSPCMD_Pos) /**< \brief (HSMCI_CMDR) SDIO Special Command */\r
+#define HSMCI_CMDR_IOSPCMD_STD (0x0u << 24) /**< \brief (HSMCI_CMDR) Not an SDIO Special Command */\r
+#define HSMCI_CMDR_IOSPCMD_SUSPEND (0x1u << 24) /**< \brief (HSMCI_CMDR) SDIO Suspend Command */\r
+#define HSMCI_CMDR_IOSPCMD_RESUME (0x2u << 24) /**< \brief (HSMCI_CMDR) SDIO Resume Command */\r
+#define HSMCI_CMDR_ATACS (0x1u << 26) /**< \brief (HSMCI_CMDR) ATA with Command Completion Signal */\r
+#define HSMCI_CMDR_ATACS_NORMAL (0x0u << 26) /**< \brief (HSMCI_CMDR) Normal operation mode. */\r
+#define HSMCI_CMDR_ATACS_COMPLETION (0x1u << 26) /**< \brief (HSMCI_CMDR) This bit indicates that a completion signal is expected within a programmed amount of time (HSMCI_CSTOR). */\r
+#define HSMCI_CMDR_BOOT_ACK (0x1u << 27) /**< \brief (HSMCI_CMDR) Boot Operation Acknowledge. */\r
+/* -------- HSMCI_BLKR : (HSMCI Offset: 0x18) Block Register -------- */\r
+#define HSMCI_BLKR_BCNT_Pos 0\r
+#define HSMCI_BLKR_BCNT_Msk (0xffffu << HSMCI_BLKR_BCNT_Pos) /**< \brief (HSMCI_BLKR) MMC/SDIO Block Count - SDIO Byte Count */\r
+#define HSMCI_BLKR_BCNT(value) ((HSMCI_BLKR_BCNT_Msk & ((value) << HSMCI_BLKR_BCNT_Pos)))\r
+#define HSMCI_BLKR_BLKLEN_Pos 16\r
+#define HSMCI_BLKR_BLKLEN_Msk (0xffffu << HSMCI_BLKR_BLKLEN_Pos) /**< \brief (HSMCI_BLKR) Data Block Length */\r
+#define HSMCI_BLKR_BLKLEN(value) ((HSMCI_BLKR_BLKLEN_Msk & ((value) << HSMCI_BLKR_BLKLEN_Pos)))\r
+/* -------- HSMCI_CSTOR : (HSMCI Offset: 0x1C) Completion Signal Timeout Register -------- */\r
+#define HSMCI_CSTOR_CSTOCYC_Pos 0\r
+#define HSMCI_CSTOR_CSTOCYC_Msk (0xfu << HSMCI_CSTOR_CSTOCYC_Pos) /**< \brief (HSMCI_CSTOR) Completion Signal Timeout Cycle Number */\r
+#define HSMCI_CSTOR_CSTOCYC(value) ((HSMCI_CSTOR_CSTOCYC_Msk & ((value) << HSMCI_CSTOR_CSTOCYC_Pos)))\r
+#define HSMCI_CSTOR_CSTOMUL_Pos 4\r
+#define HSMCI_CSTOR_CSTOMUL_Msk (0x7u << HSMCI_CSTOR_CSTOMUL_Pos) /**< \brief (HSMCI_CSTOR) Completion Signal Timeout Multiplier */\r
+#define HSMCI_CSTOR_CSTOMUL_1 (0x0u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1 */\r
+#define HSMCI_CSTOR_CSTOMUL_16 (0x1u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 16 */\r
+#define HSMCI_CSTOR_CSTOMUL_128 (0x2u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 128 */\r
+#define HSMCI_CSTOR_CSTOMUL_256 (0x3u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 256 */\r
+#define HSMCI_CSTOR_CSTOMUL_1024 (0x4u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1024 */\r
+#define HSMCI_CSTOR_CSTOMUL_4096 (0x5u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 4096 */\r
+#define HSMCI_CSTOR_CSTOMUL_65536 (0x6u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 65536 */\r
+#define HSMCI_CSTOR_CSTOMUL_1048576 (0x7u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1048576 */\r
+/* -------- HSMCI_RSPR[4] : (HSMCI Offset: 0x20) Response Register -------- */\r
+#define HSMCI_RSPR_RSP_Pos 0\r
+#define HSMCI_RSPR_RSP_Msk (0xffffffffu << HSMCI_RSPR_RSP_Pos) /**< \brief (HSMCI_RSPR[4]) Response */\r
+/* -------- HSMCI_RDR : (HSMCI Offset: 0x30) Receive Data Register -------- */\r
+#define HSMCI_RDR_DATA_Pos 0\r
+#define HSMCI_RDR_DATA_Msk (0xffffffffu << HSMCI_RDR_DATA_Pos) /**< \brief (HSMCI_RDR) Data to Read */\r
+/* -------- HSMCI_TDR : (HSMCI Offset: 0x34) Transmit Data Register -------- */\r
+#define HSMCI_TDR_DATA_Pos 0\r
+#define HSMCI_TDR_DATA_Msk (0xffffffffu << HSMCI_TDR_DATA_Pos) /**< \brief (HSMCI_TDR) Data to Write */\r
+#define HSMCI_TDR_DATA(value) ((HSMCI_TDR_DATA_Msk & ((value) << HSMCI_TDR_DATA_Pos)))\r
+/* -------- HSMCI_SR : (HSMCI Offset: 0x40) Status Register -------- */\r
+#define HSMCI_SR_CMDRDY (0x1u << 0) /**< \brief (HSMCI_SR) Command Ready */\r
+#define HSMCI_SR_RXRDY (0x1u << 1) /**< \brief (HSMCI_SR) Receiver Ready */\r
+#define HSMCI_SR_TXRDY (0x1u << 2) /**< \brief (HSMCI_SR) Transmit Ready */\r
+#define HSMCI_SR_BLKE (0x1u << 3) /**< \brief (HSMCI_SR) Data Block Ended */\r
+#define HSMCI_SR_DTIP (0x1u << 4) /**< \brief (HSMCI_SR) Data Transfer in Progress */\r
+#define HSMCI_SR_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_SR) HSMCI Not Busy */\r
+#define HSMCI_SR_ENDRX (0x1u << 6) /**< \brief (HSMCI_SR) End of RX Buffer */\r
+#define HSMCI_SR_ENDTX (0x1u << 7) /**< \brief (HSMCI_SR) End of TX Buffer */\r
+#define HSMCI_SR_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_SR) SDIO Interrupt for Slot A */\r
+#define HSMCI_SR_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_SR) SDIO Read Wait Operation Status */\r
+#define HSMCI_SR_CSRCV (0x1u << 13) /**< \brief (HSMCI_SR) CE-ATA Completion Signal Received */\r
+#define HSMCI_SR_RXBUFF (0x1u << 14) /**< \brief (HSMCI_SR) RX Buffer Full */\r
+#define HSMCI_SR_TXBUFE (0x1u << 15) /**< \brief (HSMCI_SR) TX Buffer Empty */\r
+#define HSMCI_SR_RINDE (0x1u << 16) /**< \brief (HSMCI_SR) Response Index Error */\r
+#define HSMCI_SR_RDIRE (0x1u << 17) /**< \brief (HSMCI_SR) Response Direction Error */\r
+#define HSMCI_SR_RCRCE (0x1u << 18) /**< \brief (HSMCI_SR) Response CRC Error */\r
+#define HSMCI_SR_RENDE (0x1u << 19) /**< \brief (HSMCI_SR) Response End Bit Error */\r
+#define HSMCI_SR_RTOE (0x1u << 20) /**< \brief (HSMCI_SR) Response Time-out Error */\r
+#define HSMCI_SR_DCRCE (0x1u << 21) /**< \brief (HSMCI_SR) Data CRC Error */\r
+#define HSMCI_SR_DTOE (0x1u << 22) /**< \brief (HSMCI_SR) Data Time-out Error */\r
+#define HSMCI_SR_CSTOE (0x1u << 23) /**< \brief (HSMCI_SR) Completion Signal Time-out Error */\r
+#define HSMCI_SR_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_SR) FIFO empty flag */\r
+#define HSMCI_SR_XFRDONE (0x1u << 27) /**< \brief (HSMCI_SR) Transfer Done flag */\r
+#define HSMCI_SR_ACKRCV (0x1u << 28) /**< \brief (HSMCI_SR) Boot Operation Acknowledge Received */\r
+#define HSMCI_SR_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_SR) Boot Operation Acknowledge Error */\r
+#define HSMCI_SR_OVRE (0x1u << 30) /**< \brief (HSMCI_SR) Overrun */\r
+#define HSMCI_SR_UNRE (0x1u << 31) /**< \brief (HSMCI_SR) Underrun */\r
+/* -------- HSMCI_IER : (HSMCI Offset: 0x44) Interrupt Enable Register -------- */\r
+#define HSMCI_IER_CMDRDY (0x1u << 0) /**< \brief (HSMCI_IER) Command Ready Interrupt Enable */\r
+#define HSMCI_IER_RXRDY (0x1u << 1) /**< \brief (HSMCI_IER) Receiver Ready Interrupt Enable */\r
+#define HSMCI_IER_TXRDY (0x1u << 2) /**< \brief (HSMCI_IER) Transmit Ready Interrupt Enable */\r
+#define HSMCI_IER_BLKE (0x1u << 3) /**< \brief (HSMCI_IER) Data Block Ended Interrupt Enable */\r
+#define HSMCI_IER_DTIP (0x1u << 4) /**< \brief (HSMCI_IER) Data Transfer in Progress Interrupt Enable */\r
+#define HSMCI_IER_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_IER) Data Not Busy Interrupt Enable */\r
+#define HSMCI_IER_ENDRX (0x1u << 6) /**< \brief (HSMCI_IER) End of Receive Buffer Interrupt Enable */\r
+#define HSMCI_IER_ENDTX (0x1u << 7) /**< \brief (HSMCI_IER) End of Transmit Buffer Interrupt Enable */\r
+#define HSMCI_IER_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_IER) SDIO Interrupt for Slot A Interrupt Enable */\r
+#define HSMCI_IER_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_IER) SDIO Read Wait Operation Status Interrupt Enable */\r
+#define HSMCI_IER_CSRCV (0x1u << 13) /**< \brief (HSMCI_IER) Completion Signal Received Interrupt Enable */\r
+#define HSMCI_IER_RXBUFF (0x1u << 14) /**< \brief (HSMCI_IER) Receive Buffer Full Interrupt Enable */\r
+#define HSMCI_IER_TXBUFE (0x1u << 15) /**< \brief (HSMCI_IER) Transmit Buffer Empty Interrupt Enable */\r
+#define HSMCI_IER_RINDE (0x1u << 16) /**< \brief (HSMCI_IER) Response Index Error Interrupt Enable */\r
+#define HSMCI_IER_RDIRE (0x1u << 17) /**< \brief (HSMCI_IER) Response Direction Error Interrupt Enable */\r
+#define HSMCI_IER_RCRCE (0x1u << 18) /**< \brief (HSMCI_IER) Response CRC Error Interrupt Enable */\r
+#define HSMCI_IER_RENDE (0x1u << 19) /**< \brief (HSMCI_IER) Response End Bit Error Interrupt Enable */\r
+#define HSMCI_IER_RTOE (0x1u << 20) /**< \brief (HSMCI_IER) Response Time-out Error Interrupt Enable */\r
+#define HSMCI_IER_DCRCE (0x1u << 21) /**< \brief (HSMCI_IER) Data CRC Error Interrupt Enable */\r
+#define HSMCI_IER_DTOE (0x1u << 22) /**< \brief (HSMCI_IER) Data Time-out Error Interrupt Enable */\r
+#define HSMCI_IER_CSTOE (0x1u << 23) /**< \brief (HSMCI_IER) Completion Signal Timeout Error Interrupt Enable */\r
+#define HSMCI_IER_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_IER) FIFO empty Interrupt enable */\r
+#define HSMCI_IER_XFRDONE (0x1u << 27) /**< \brief (HSMCI_IER) Transfer Done Interrupt enable */\r
+#define HSMCI_IER_ACKRCV (0x1u << 28) /**< \brief (HSMCI_IER) Boot Acknowledge Interrupt Enable */\r
+#define HSMCI_IER_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_IER) Boot Acknowledge Error Interrupt Enable */\r
+#define HSMCI_IER_OVRE (0x1u << 30) /**< \brief (HSMCI_IER) Overrun Interrupt Enable */\r
+#define HSMCI_IER_UNRE (0x1u << 31) /**< \brief (HSMCI_IER) Underrun Interrupt Enable */\r
+/* -------- HSMCI_IDR : (HSMCI Offset: 0x48) Interrupt Disable Register -------- */\r
+#define HSMCI_IDR_CMDRDY (0x1u << 0) /**< \brief (HSMCI_IDR) Command Ready Interrupt Disable */\r
+#define HSMCI_IDR_RXRDY (0x1u << 1) /**< \brief (HSMCI_IDR) Receiver Ready Interrupt Disable */\r
+#define HSMCI_IDR_TXRDY (0x1u << 2) /**< \brief (HSMCI_IDR) Transmit Ready Interrupt Disable */\r
+#define HSMCI_IDR_BLKE (0x1u << 3) /**< \brief (HSMCI_IDR) Data Block Ended Interrupt Disable */\r
+#define HSMCI_IDR_DTIP (0x1u << 4) /**< \brief (HSMCI_IDR) Data Transfer in Progress Interrupt Disable */\r
+#define HSMCI_IDR_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_IDR) Data Not Busy Interrupt Disable */\r
+#define HSMCI_IDR_ENDRX (0x1u << 6) /**< \brief (HSMCI_IDR) End of Receive Buffer Interrupt Disable */\r
+#define HSMCI_IDR_ENDTX (0x1u << 7) /**< \brief (HSMCI_IDR) End of Transmit Buffer Interrupt Disable */\r
+#define HSMCI_IDR_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_IDR) SDIO Interrupt for Slot A Interrupt Disable */\r
+#define HSMCI_IDR_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_IDR) SDIO Read Wait Operation Status Interrupt Disable */\r
+#define HSMCI_IDR_CSRCV (0x1u << 13) /**< \brief (HSMCI_IDR) Completion Signal received interrupt Disable */\r
+#define HSMCI_IDR_RXBUFF (0x1u << 14) /**< \brief (HSMCI_IDR) Receive Buffer Full Interrupt Disable */\r
+#define HSMCI_IDR_TXBUFE (0x1u << 15) /**< \brief (HSMCI_IDR) Transmit Buffer Empty Interrupt Disable */\r
+#define HSMCI_IDR_RINDE (0x1u << 16) /**< \brief (HSMCI_IDR) Response Index Error Interrupt Disable */\r
+#define HSMCI_IDR_RDIRE (0x1u << 17) /**< \brief (HSMCI_IDR) Response Direction Error Interrupt Disable */\r
+#define HSMCI_IDR_RCRCE (0x1u << 18) /**< \brief (HSMCI_IDR) Response CRC Error Interrupt Disable */\r
+#define HSMCI_IDR_RENDE (0x1u << 19) /**< \brief (HSMCI_IDR) Response End Bit Error Interrupt Disable */\r
+#define HSMCI_IDR_RTOE (0x1u << 20) /**< \brief (HSMCI_IDR) Response Time-out Error Interrupt Disable */\r
+#define HSMCI_IDR_DCRCE (0x1u << 21) /**< \brief (HSMCI_IDR) Data CRC Error Interrupt Disable */\r
+#define HSMCI_IDR_DTOE (0x1u << 22) /**< \brief (HSMCI_IDR) Data Time-out Error Interrupt Disable */\r
+#define HSMCI_IDR_CSTOE (0x1u << 23) /**< \brief (HSMCI_IDR) Completion Signal Time out Error Interrupt Disable */\r
+#define HSMCI_IDR_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_IDR) FIFO empty Interrupt Disable */\r
+#define HSMCI_IDR_XFRDONE (0x1u << 27) /**< \brief (HSMCI_IDR) Transfer Done Interrupt Disable */\r
+#define HSMCI_IDR_ACKRCV (0x1u << 28) /**< \brief (HSMCI_IDR) Boot Acknowledge Interrupt Disable */\r
+#define HSMCI_IDR_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_IDR) Boot Acknowledge Error Interrupt Disable */\r
+#define HSMCI_IDR_OVRE (0x1u << 30) /**< \brief (HSMCI_IDR) Overrun Interrupt Disable */\r
+#define HSMCI_IDR_UNRE (0x1u << 31) /**< \brief (HSMCI_IDR) Underrun Interrupt Disable */\r
+/* -------- HSMCI_IMR : (HSMCI Offset: 0x4C) Interrupt Mask Register -------- */\r
+#define HSMCI_IMR_CMDRDY (0x1u << 0) /**< \brief (HSMCI_IMR) Command Ready Interrupt Mask */\r
+#define HSMCI_IMR_RXRDY (0x1u << 1) /**< \brief (HSMCI_IMR) Receiver Ready Interrupt Mask */\r
+#define HSMCI_IMR_TXRDY (0x1u << 2) /**< \brief (HSMCI_IMR) Transmit Ready Interrupt Mask */\r
+#define HSMCI_IMR_BLKE (0x1u << 3) /**< \brief (HSMCI_IMR) Data Block Ended Interrupt Mask */\r
+#define HSMCI_IMR_DTIP (0x1u << 4) /**< \brief (HSMCI_IMR) Data Transfer in Progress Interrupt Mask */\r
+#define HSMCI_IMR_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_IMR) Data Not Busy Interrupt Mask */\r
+#define HSMCI_IMR_ENDRX (0x1u << 6) /**< \brief (HSMCI_IMR) End of Receive Buffer Interrupt Mask */\r
+#define HSMCI_IMR_ENDTX (0x1u << 7) /**< \brief (HSMCI_IMR) End of Transmit Buffer Interrupt Mask */\r
+#define HSMCI_IMR_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_IMR) SDIO Interrupt for Slot A Interrupt Mask */\r
+#define HSMCI_IMR_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_IMR) SDIO Read Wait Operation Status Interrupt Mask */\r
+#define HSMCI_IMR_CSRCV (0x1u << 13) /**< \brief (HSMCI_IMR) Completion Signal Received Interrupt Mask */\r
+#define HSMCI_IMR_RXBUFF (0x1u << 14) /**< \brief (HSMCI_IMR) Receive Buffer Full Interrupt Mask */\r
+#define HSMCI_IMR_TXBUFE (0x1u << 15) /**< \brief (HSMCI_IMR) Transmit Buffer Empty Interrupt Mask */\r
+#define HSMCI_IMR_RINDE (0x1u << 16) /**< \brief (HSMCI_IMR) Response Index Error Interrupt Mask */\r
+#define HSMCI_IMR_RDIRE (0x1u << 17) /**< \brief (HSMCI_IMR) Response Direction Error Interrupt Mask */\r
+#define HSMCI_IMR_RCRCE (0x1u << 18) /**< \brief (HSMCI_IMR) Response CRC Error Interrupt Mask */\r
+#define HSMCI_IMR_RENDE (0x1u << 19) /**< \brief (HSMCI_IMR) Response End Bit Error Interrupt Mask */\r
+#define HSMCI_IMR_RTOE (0x1u << 20) /**< \brief (HSMCI_IMR) Response Time-out Error Interrupt Mask */\r
+#define HSMCI_IMR_DCRCE (0x1u << 21) /**< \brief (HSMCI_IMR) Data CRC Error Interrupt Mask */\r
+#define HSMCI_IMR_DTOE (0x1u << 22) /**< \brief (HSMCI_IMR) Data Time-out Error Interrupt Mask */\r
+#define HSMCI_IMR_CSTOE (0x1u << 23) /**< \brief (HSMCI_IMR) Completion Signal Time-out Error Interrupt Mask */\r
+#define HSMCI_IMR_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_IMR) FIFO Empty Interrupt Mask */\r
+#define HSMCI_IMR_XFRDONE (0x1u << 27) /**< \brief (HSMCI_IMR) Transfer Done Interrupt Mask */\r
+#define HSMCI_IMR_ACKRCV (0x1u << 28) /**< \brief (HSMCI_IMR) Boot Operation Acknowledge Received Interrupt Mask */\r
+#define HSMCI_IMR_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_IMR) Boot Operation Acknowledge Error Interrupt Mask */\r
+#define HSMCI_IMR_OVRE (0x1u << 30) /**< \brief (HSMCI_IMR) Overrun Interrupt Mask */\r
+#define HSMCI_IMR_UNRE (0x1u << 31) /**< \brief (HSMCI_IMR) Underrun Interrupt Mask */\r
+/* -------- HSMCI_CFG : (HSMCI Offset: 0x54) Configuration Register -------- */\r
+#define HSMCI_CFG_FIFOMODE (0x1u << 0) /**< \brief (HSMCI_CFG) HSMCI Internal FIFO control mode */\r
+#define HSMCI_CFG_FERRCTRL (0x1u << 4) /**< \brief (HSMCI_CFG) Flow Error flag reset control mode */\r
+#define HSMCI_CFG_HSMODE (0x1u << 8) /**< \brief (HSMCI_CFG) High Speed Mode */\r
+#define HSMCI_CFG_LSYNC (0x1u << 12) /**< \brief (HSMCI_CFG) Synchronize on the last block */\r
+/* -------- HSMCI_WPMR : (HSMCI Offset: 0xE4) Write Protection Mode Register -------- */\r
+#define HSMCI_WPMR_WP_EN (0x1u << 0) /**< \brief (HSMCI_WPMR) Write Protection Enable */\r
+#define HSMCI_WPMR_WP_KEY_Pos 8\r
+#define HSMCI_WPMR_WP_KEY_Msk (0xffffffu << HSMCI_WPMR_WP_KEY_Pos) /**< \brief (HSMCI_WPMR) Write Protection Key password */\r
+#define HSMCI_WPMR_WP_KEY(value) ((HSMCI_WPMR_WP_KEY_Msk & ((value) << HSMCI_WPMR_WP_KEY_Pos)))\r
+/* -------- HSMCI_WPSR : (HSMCI Offset: 0xE8) Write Protection Status Register -------- */\r
+#define HSMCI_WPSR_WP_VS_Pos 0\r
+#define HSMCI_WPSR_WP_VS_Msk (0xfu << HSMCI_WPSR_WP_VS_Pos) /**< \brief (HSMCI_WPSR) Write Protection Violation Status */\r
+#define HSMCI_WPSR_WP_VS_NONE (0x0u << 0) /**< \brief (HSMCI_WPSR) No Write Protection Violation occurred since the last read of this register (WP_SR) */\r
+#define HSMCI_WPSR_WP_VS_WRITE (0x1u << 0) /**< \brief (HSMCI_WPSR) Write Protection detected unauthorized attempt to write a control register had occurred (since the last read.) */\r
+#define HSMCI_WPSR_WP_VS_RESET (0x2u << 0) /**< \brief (HSMCI_WPSR) Software reset had been performed while Write Protection was enabled (since the last read). */\r
+#define HSMCI_WPSR_WP_VS_BOTH (0x3u << 0) /**< \brief (HSMCI_WPSR) Both Write Protection violation and software reset with Write Protection enabled have occurred since the last read. */\r
+#define HSMCI_WPSR_WP_VSRC_Pos 8\r
+#define HSMCI_WPSR_WP_VSRC_Msk (0xffffu << HSMCI_WPSR_WP_VSRC_Pos) /**< \brief (HSMCI_WPSR) Write Protection Violation SouRCe */\r
+/* -------- HSMCI_RPR : (HSMCI Offset: 0x100) Receive Pointer Register -------- */\r
+#define HSMCI_RPR_RXPTR_Pos 0\r
+#define HSMCI_RPR_RXPTR_Msk (0xffffffffu << HSMCI_RPR_RXPTR_Pos) /**< \brief (HSMCI_RPR) Receive Pointer Register */\r
+#define HSMCI_RPR_RXPTR(value) ((HSMCI_RPR_RXPTR_Msk & ((value) << HSMCI_RPR_RXPTR_Pos)))\r
+/* -------- HSMCI_RCR : (HSMCI Offset: 0x104) Receive Counter Register -------- */\r
+#define HSMCI_RCR_RXCTR_Pos 0\r
+#define HSMCI_RCR_RXCTR_Msk (0xffffu << HSMCI_RCR_RXCTR_Pos) /**< \brief (HSMCI_RCR) Receive Counter Register */\r
+#define HSMCI_RCR_RXCTR(value) ((HSMCI_RCR_RXCTR_Msk & ((value) << HSMCI_RCR_RXCTR_Pos)))\r
+/* -------- HSMCI_TPR : (HSMCI Offset: 0x108) Transmit Pointer Register -------- */\r
+#define HSMCI_TPR_TXPTR_Pos 0\r
+#define HSMCI_TPR_TXPTR_Msk (0xffffffffu << HSMCI_TPR_TXPTR_Pos) /**< \brief (HSMCI_TPR) Transmit Counter Register */\r
+#define HSMCI_TPR_TXPTR(value) ((HSMCI_TPR_TXPTR_Msk & ((value) << HSMCI_TPR_TXPTR_Pos)))\r
+/* -------- HSMCI_TCR : (HSMCI Offset: 0x10C) Transmit Counter Register -------- */\r
+#define HSMCI_TCR_TXCTR_Pos 0\r
+#define HSMCI_TCR_TXCTR_Msk (0xffffu << HSMCI_TCR_TXCTR_Pos) /**< \brief (HSMCI_TCR) Transmit Counter Register */\r
+#define HSMCI_TCR_TXCTR(value) ((HSMCI_TCR_TXCTR_Msk & ((value) << HSMCI_TCR_TXCTR_Pos)))\r
+/* -------- HSMCI_RNPR : (HSMCI Offset: 0x110) Receive Next Pointer Register -------- */\r
+#define HSMCI_RNPR_RXNPTR_Pos 0\r
+#define HSMCI_RNPR_RXNPTR_Msk (0xffffffffu << HSMCI_RNPR_RXNPTR_Pos) /**< \brief (HSMCI_RNPR) Receive Next Pointer */\r
+#define HSMCI_RNPR_RXNPTR(value) ((HSMCI_RNPR_RXNPTR_Msk & ((value) << HSMCI_RNPR_RXNPTR_Pos)))\r
+/* -------- HSMCI_RNCR : (HSMCI Offset: 0x114) Receive Next Counter Register -------- */\r
+#define HSMCI_RNCR_RXNCTR_Pos 0\r
+#define HSMCI_RNCR_RXNCTR_Msk (0xffffu << HSMCI_RNCR_RXNCTR_Pos) /**< \brief (HSMCI_RNCR) Receive Next Counter */\r
+#define HSMCI_RNCR_RXNCTR(value) ((HSMCI_RNCR_RXNCTR_Msk & ((value) << HSMCI_RNCR_RXNCTR_Pos)))\r
+/* -------- HSMCI_TNPR : (HSMCI Offset: 0x118) Transmit Next Pointer Register -------- */\r
+#define HSMCI_TNPR_TXNPTR_Pos 0\r
+#define HSMCI_TNPR_TXNPTR_Msk (0xffffffffu << HSMCI_TNPR_TXNPTR_Pos) /**< \brief (HSMCI_TNPR) Transmit Next Pointer */\r
+#define HSMCI_TNPR_TXNPTR(value) ((HSMCI_TNPR_TXNPTR_Msk & ((value) << HSMCI_TNPR_TXNPTR_Pos)))\r
+/* -------- HSMCI_TNCR : (HSMCI Offset: 0x11C) Transmit Next Counter Register -------- */\r
+#define HSMCI_TNCR_TXNCTR_Pos 0\r
+#define HSMCI_TNCR_TXNCTR_Msk (0xffffu << HSMCI_TNCR_TXNCTR_Pos) /**< \brief (HSMCI_TNCR) Transmit Counter Next */\r
+#define HSMCI_TNCR_TXNCTR(value) ((HSMCI_TNCR_TXNCTR_Msk & ((value) << HSMCI_TNCR_TXNCTR_Pos)))\r
+/* -------- HSMCI_PTCR : (HSMCI Offset: 0x120) Transfer Control Register -------- */\r
+#define HSMCI_PTCR_RXTEN (0x1u << 0) /**< \brief (HSMCI_PTCR) Receiver Transfer Enable */\r
+#define HSMCI_PTCR_RXTDIS (0x1u << 1) /**< \brief (HSMCI_PTCR) Receiver Transfer Disable */\r
+#define HSMCI_PTCR_TXTEN (0x1u << 8) /**< \brief (HSMCI_PTCR) Transmitter Transfer Enable */\r
+#define HSMCI_PTCR_TXTDIS (0x1u << 9) /**< \brief (HSMCI_PTCR) Transmitter Transfer Disable */\r
+/* -------- HSMCI_PTSR : (HSMCI Offset: 0x124) Transfer Status Register -------- */\r
+#define HSMCI_PTSR_RXTEN (0x1u << 0) /**< \brief (HSMCI_PTSR) Receiver Transfer Enable */\r
+#define HSMCI_PTSR_TXTEN (0x1u << 8) /**< \brief (HSMCI_PTSR) Transmitter Transfer Enable */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM4E_HSMCI_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4E_MATRIX_COMPONENT_\r
+#define _SAM4E_MATRIX_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Bus Matrix */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM4E_MATRIX Bus Matrix */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Matrix hardware registers */\r
+typedef struct {\r
+ RwReg MATRIX_MCFG[7]; /**< \brief (Matrix Offset: 0x0000) Master Configuration Register */\r
+ RoReg Reserved1[9];\r
+ RwReg MATRIX_SCFG[6]; /**< \brief (Matrix Offset: 0x0040) Slave Configuration Register */\r
+ RoReg Reserved2[10];\r
+ RwReg MATRIX_PRAS0; /**< \brief (Matrix Offset: 0x0080) Priority Register A for Slave 0 */\r
+ RoReg Reserved3[1];\r
+ RwReg MATRIX_PRAS1; /**< \brief (Matrix Offset: 0x0088) Priority Register A for Slave 1 */\r
+ RoReg Reserved4[1];\r
+ RwReg MATRIX_PRAS2; /**< \brief (Matrix Offset: 0x0090) Priority Register A for Slave 2 */\r
+ RoReg Reserved5[1];\r
+ RwReg MATRIX_PRAS3; /**< \brief (Matrix Offset: 0x0098) Priority Register A for Slave 3 */\r
+ RoReg Reserved6[1];\r
+ RwReg MATRIX_PRAS4; /**< \brief (Matrix Offset: 0x00A0) Priority Register A for Slave 4 */\r
+ RoReg Reserved7[1];\r
+ RwReg MATRIX_PRAS5; /**< \brief (Matrix Offset: 0x00A8) Priority Register A for Slave 5 */\r
+ RoReg Reserved8[1];\r
+ RoReg Reserved9[20];\r
+ RwReg MATRIX_MRCR; /**< \brief (Matrix Offset: 0x0100) Master Remap Control Register */\r
+ RoReg Reserved10[4];\r
+ RwReg CCFG_SYSIO; /**< \brief (Matrix Offset: 0x0114) System I/O Configuration Register */\r
+ RoReg Reserved11[3];\r
+ RwReg CCFG_SMCNFCS; /**< \brief (Matrix Offset: 0x0124) SMC NAND Flash Chip Select Configuration Register */\r
+ RoReg Reserved12[47];\r
+ RwReg MATRIX_WPMR; /**< \brief (Matrix Offset: 0x01E4) Write Protect Mode Register */\r
+ RoReg MATRIX_WPSR; /**< \brief (Matrix Offset: 0x01E8) Write Protect Status Register */\r
+} Matrix;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- MATRIX_MCFG[7] : (MATRIX Offset: 0x0000) Master Configuration Register -------- */\r
+#define MATRIX_MCFG_ULBT_Pos 0\r
+#define MATRIX_MCFG_ULBT_Msk (0x7u << MATRIX_MCFG_ULBT_Pos) /**< \brief (MATRIX_MCFG[7]) Undefined Length Burst Type */\r
+#define MATRIX_MCFG_ULBT(value) ((MATRIX_MCFG_ULBT_Msk & ((value) << MATRIX_MCFG_ULBT_Pos)))\r
+/* -------- MATRIX_SCFG[6] : (MATRIX Offset: 0x0040) Slave Configuration Register -------- */\r
+#define MATRIX_SCFG_SLOT_CYCLE_Pos 0\r
+#define MATRIX_SCFG_SLOT_CYCLE_Msk (0x1ffu << MATRIX_SCFG_SLOT_CYCLE_Pos) /**< \brief (MATRIX_SCFG[6]) Maximum Bus Grant Duration for Masters */\r
+#define MATRIX_SCFG_SLOT_CYCLE(value) ((MATRIX_SCFG_SLOT_CYCLE_Msk & ((value) << MATRIX_SCFG_SLOT_CYCLE_Pos)))\r
+#define MATRIX_SCFG_DEFMSTR_TYPE_Pos 16\r
+#define MATRIX_SCFG_DEFMSTR_TYPE_Msk (0x3u << MATRIX_SCFG_DEFMSTR_TYPE_Pos) /**< \brief (MATRIX_SCFG[6]) Default Master Type */\r
+#define MATRIX_SCFG_DEFMSTR_TYPE(value) ((MATRIX_SCFG_DEFMSTR_TYPE_Msk & ((value) << MATRIX_SCFG_DEFMSTR_TYPE_Pos)))\r
+#define MATRIX_SCFG_FIXED_DEFMSTR_Pos 18\r
+#define MATRIX_SCFG_FIXED_DEFMSTR_Msk (0xfu << MATRIX_SCFG_FIXED_DEFMSTR_Pos) /**< \brief (MATRIX_SCFG[6]) Fixed Default Master */\r
+#define MATRIX_SCFG_FIXED_DEFMSTR(value) ((MATRIX_SCFG_FIXED_DEFMSTR_Msk & ((value) << MATRIX_SCFG_FIXED_DEFMSTR_Pos)))\r
+/* -------- MATRIX_PRAS0 : (MATRIX Offset: 0x0080) Priority Register A for Slave 0 -------- */\r
+#define MATRIX_PRAS0_M0PR_Pos 0\r
+#define MATRIX_PRAS0_M0PR_Msk (0x3u << MATRIX_PRAS0_M0PR_Pos) /**< \brief (MATRIX_PRAS0) Master 0 Priority */\r
+#define MATRIX_PRAS0_M0PR(value) ((MATRIX_PRAS0_M0PR_Msk & ((value) << MATRIX_PRAS0_M0PR_Pos)))\r
+#define MATRIX_PRAS0_M1PR_Pos 4\r
+#define MATRIX_PRAS0_M1PR_Msk (0x3u << MATRIX_PRAS0_M1PR_Pos) /**< \brief (MATRIX_PRAS0) Master 1 Priority */\r
+#define MATRIX_PRAS0_M1PR(value) ((MATRIX_PRAS0_M1PR_Msk & ((value) << MATRIX_PRAS0_M1PR_Pos)))\r
+#define MATRIX_PRAS0_M2PR_Pos 8\r
+#define MATRIX_PRAS0_M2PR_Msk (0x3u << MATRIX_PRAS0_M2PR_Pos) /**< \brief (MATRIX_PRAS0) Master 2 Priority */\r
+#define MATRIX_PRAS0_M2PR(value) ((MATRIX_PRAS0_M2PR_Msk & ((value) << MATRIX_PRAS0_M2PR_Pos)))\r
+#define MATRIX_PRAS0_M3PR_Pos 12\r
+#define MATRIX_PRAS0_M3PR_Msk (0x3u << MATRIX_PRAS0_M3PR_Pos) /**< \brief (MATRIX_PRAS0) Master 3 Priority */\r
+#define MATRIX_PRAS0_M3PR(value) ((MATRIX_PRAS0_M3PR_Msk & ((value) << MATRIX_PRAS0_M3PR_Pos)))\r
+#define MATRIX_PRAS0_M4PR_Pos 16\r
+#define MATRIX_PRAS0_M4PR_Msk (0x3u << MATRIX_PRAS0_M4PR_Pos) /**< \brief (MATRIX_PRAS0) Master 4 Priority */\r
+#define MATRIX_PRAS0_M4PR(value) ((MATRIX_PRAS0_M4PR_Msk & ((value) << MATRIX_PRAS0_M4PR_Pos)))\r
+#define MATRIX_PRAS0_M5PR_Pos 20\r
+#define MATRIX_PRAS0_M5PR_Msk (0x3u << MATRIX_PRAS0_M5PR_Pos) /**< \brief (MATRIX_PRAS0) Master 5 Priority */\r
+#define MATRIX_PRAS0_M5PR(value) ((MATRIX_PRAS0_M5PR_Msk & ((value) << MATRIX_PRAS0_M5PR_Pos)))\r
+#define MATRIX_PRAS0_M6PR_Pos 24\r
+#define MATRIX_PRAS0_M6PR_Msk (0x3u << MATRIX_PRAS0_M6PR_Pos) /**< \brief (MATRIX_PRAS0) Master 6 Priority */\r
+#define MATRIX_PRAS0_M6PR(value) ((MATRIX_PRAS0_M6PR_Msk & ((value) << MATRIX_PRAS0_M6PR_Pos)))\r
+/* -------- MATRIX_PRAS1 : (MATRIX Offset: 0x0088) Priority Register A for Slave 1 -------- */\r
+#define MATRIX_PRAS1_M0PR_Pos 0\r
+#define MATRIX_PRAS1_M0PR_Msk (0x3u << MATRIX_PRAS1_M0PR_Pos) /**< \brief (MATRIX_PRAS1) Master 0 Priority */\r
+#define MATRIX_PRAS1_M0PR(value) ((MATRIX_PRAS1_M0PR_Msk & ((value) << MATRIX_PRAS1_M0PR_Pos)))\r
+#define MATRIX_PRAS1_M1PR_Pos 4\r
+#define MATRIX_PRAS1_M1PR_Msk (0x3u << MATRIX_PRAS1_M1PR_Pos) /**< \brief (MATRIX_PRAS1) Master 1 Priority */\r
+#define MATRIX_PRAS1_M1PR(value) ((MATRIX_PRAS1_M1PR_Msk & ((value) << MATRIX_PRAS1_M1PR_Pos)))\r
+#define MATRIX_PRAS1_M2PR_Pos 8\r
+#define MATRIX_PRAS1_M2PR_Msk (0x3u << MATRIX_PRAS1_M2PR_Pos) /**< \brief (MATRIX_PRAS1) Master 2 Priority */\r
+#define MATRIX_PRAS1_M2PR(value) ((MATRIX_PRAS1_M2PR_Msk & ((value) << MATRIX_PRAS1_M2PR_Pos)))\r
+#define MATRIX_PRAS1_M3PR_Pos 12\r
+#define MATRIX_PRAS1_M3PR_Msk (0x3u << MATRIX_PRAS1_M3PR_Pos) /**< \brief (MATRIX_PRAS1) Master 3 Priority */\r
+#define MATRIX_PRAS1_M3PR(value) ((MATRIX_PRAS1_M3PR_Msk & ((value) << MATRIX_PRAS1_M3PR_Pos)))\r
+#define MATRIX_PRAS1_M4PR_Pos 16\r
+#define MATRIX_PRAS1_M4PR_Msk (0x3u << MATRIX_PRAS1_M4PR_Pos) /**< \brief (MATRIX_PRAS1) Master 4 Priority */\r
+#define MATRIX_PRAS1_M4PR(value) ((MATRIX_PRAS1_M4PR_Msk & ((value) << MATRIX_PRAS1_M4PR_Pos)))\r
+#define MATRIX_PRAS1_M5PR_Pos 20\r
+#define MATRIX_PRAS1_M5PR_Msk (0x3u << MATRIX_PRAS1_M5PR_Pos) /**< \brief (MATRIX_PRAS1) Master 5 Priority */\r
+#define MATRIX_PRAS1_M5PR(value) ((MATRIX_PRAS1_M5PR_Msk & ((value) << MATRIX_PRAS1_M5PR_Pos)))\r
+#define MATRIX_PRAS1_M6PR_Pos 24\r
+#define MATRIX_PRAS1_M6PR_Msk (0x3u << MATRIX_PRAS1_M6PR_Pos) /**< \brief (MATRIX_PRAS1) Master 6 Priority */\r
+#define MATRIX_PRAS1_M6PR(value) ((MATRIX_PRAS1_M6PR_Msk & ((value) << MATRIX_PRAS1_M6PR_Pos)))\r
+/* -------- MATRIX_PRAS2 : (MATRIX Offset: 0x0090) Priority Register A for Slave 2 -------- */\r
+#define MATRIX_PRAS2_M0PR_Pos 0\r
+#define MATRIX_PRAS2_M0PR_Msk (0x3u << MATRIX_PRAS2_M0PR_Pos) /**< \brief (MATRIX_PRAS2) Master 0 Priority */\r
+#define MATRIX_PRAS2_M0PR(value) ((MATRIX_PRAS2_M0PR_Msk & ((value) << MATRIX_PRAS2_M0PR_Pos)))\r
+#define MATRIX_PRAS2_M1PR_Pos 4\r
+#define MATRIX_PRAS2_M1PR_Msk (0x3u << MATRIX_PRAS2_M1PR_Pos) /**< \brief (MATRIX_PRAS2) Master 1 Priority */\r
+#define MATRIX_PRAS2_M1PR(value) ((MATRIX_PRAS2_M1PR_Msk & ((value) << MATRIX_PRAS2_M1PR_Pos)))\r
+#define MATRIX_PRAS2_M2PR_Pos 8\r
+#define MATRIX_PRAS2_M2PR_Msk (0x3u << MATRIX_PRAS2_M2PR_Pos) /**< \brief (MATRIX_PRAS2) Master 2 Priority */\r
+#define MATRIX_PRAS2_M2PR(value) ((MATRIX_PRAS2_M2PR_Msk & ((value) << MATRIX_PRAS2_M2PR_Pos)))\r
+#define MATRIX_PRAS2_M3PR_Pos 12\r
+#define MATRIX_PRAS2_M3PR_Msk (0x3u << MATRIX_PRAS2_M3PR_Pos) /**< \brief (MATRIX_PRAS2) Master 3 Priority */\r
+#define MATRIX_PRAS2_M3PR(value) ((MATRIX_PRAS2_M3PR_Msk & ((value) << MATRIX_PRAS2_M3PR_Pos)))\r
+#define MATRIX_PRAS2_M4PR_Pos 16\r
+#define MATRIX_PRAS2_M4PR_Msk (0x3u << MATRIX_PRAS2_M4PR_Pos) /**< \brief (MATRIX_PRAS2) Master 4 Priority */\r
+#define MATRIX_PRAS2_M4PR(value) ((MATRIX_PRAS2_M4PR_Msk & ((value) << MATRIX_PRAS2_M4PR_Pos)))\r
+#define MATRIX_PRAS2_M5PR_Pos 20\r
+#define MATRIX_PRAS2_M5PR_Msk (0x3u << MATRIX_PRAS2_M5PR_Pos) /**< \brief (MATRIX_PRAS2) Master 5 Priority */\r
+#define MATRIX_PRAS2_M5PR(value) ((MATRIX_PRAS2_M5PR_Msk & ((value) << MATRIX_PRAS2_M5PR_Pos)))\r
+#define MATRIX_PRAS2_M6PR_Pos 24\r
+#define MATRIX_PRAS2_M6PR_Msk (0x3u << MATRIX_PRAS2_M6PR_Pos) /**< \brief (MATRIX_PRAS2) Master 6 Priority */\r
+#define MATRIX_PRAS2_M6PR(value) ((MATRIX_PRAS2_M6PR_Msk & ((value) << MATRIX_PRAS2_M6PR_Pos)))\r
+/* -------- MATRIX_PRAS3 : (MATRIX Offset: 0x0098) Priority Register A for Slave 3 -------- */\r
+#define MATRIX_PRAS3_M0PR_Pos 0\r
+#define MATRIX_PRAS3_M0PR_Msk (0x3u << MATRIX_PRAS3_M0PR_Pos) /**< \brief (MATRIX_PRAS3) Master 0 Priority */\r
+#define MATRIX_PRAS3_M0PR(value) ((MATRIX_PRAS3_M0PR_Msk & ((value) << MATRIX_PRAS3_M0PR_Pos)))\r
+#define MATRIX_PRAS3_M1PR_Pos 4\r
+#define MATRIX_PRAS3_M1PR_Msk (0x3u << MATRIX_PRAS3_M1PR_Pos) /**< \brief (MATRIX_PRAS3) Master 1 Priority */\r
+#define MATRIX_PRAS3_M1PR(value) ((MATRIX_PRAS3_M1PR_Msk & ((value) << MATRIX_PRAS3_M1PR_Pos)))\r
+#define MATRIX_PRAS3_M2PR_Pos 8\r
+#define MATRIX_PRAS3_M2PR_Msk (0x3u << MATRIX_PRAS3_M2PR_Pos) /**< \brief (MATRIX_PRAS3) Master 2 Priority */\r
+#define MATRIX_PRAS3_M2PR(value) ((MATRIX_PRAS3_M2PR_Msk & ((value) << MATRIX_PRAS3_M2PR_Pos)))\r
+#define MATRIX_PRAS3_M3PR_Pos 12\r
+#define MATRIX_PRAS3_M3PR_Msk (0x3u << MATRIX_PRAS3_M3PR_Pos) /**< \brief (MATRIX_PRAS3) Master 3 Priority */\r
+#define MATRIX_PRAS3_M3PR(value) ((MATRIX_PRAS3_M3PR_Msk & ((value) << MATRIX_PRAS3_M3PR_Pos)))\r
+#define MATRIX_PRAS3_M4PR_Pos 16\r
+#define MATRIX_PRAS3_M4PR_Msk (0x3u << MATRIX_PRAS3_M4PR_Pos) /**< \brief (MATRIX_PRAS3) Master 4 Priority */\r
+#define MATRIX_PRAS3_M4PR(value) ((MATRIX_PRAS3_M4PR_Msk & ((value) << MATRIX_PRAS3_M4PR_Pos)))\r
+#define MATRIX_PRAS3_M5PR_Pos 20\r
+#define MATRIX_PRAS3_M5PR_Msk (0x3u << MATRIX_PRAS3_M5PR_Pos) /**< \brief (MATRIX_PRAS3) Master 5 Priority */\r
+#define MATRIX_PRAS3_M5PR(value) ((MATRIX_PRAS3_M5PR_Msk & ((value) << MATRIX_PRAS3_M5PR_Pos)))\r
+#define MATRIX_PRAS3_M6PR_Pos 24\r
+#define MATRIX_PRAS3_M6PR_Msk (0x3u << MATRIX_PRAS3_M6PR_Pos) /**< \brief (MATRIX_PRAS3) Master 6 Priority */\r
+#define MATRIX_PRAS3_M6PR(value) ((MATRIX_PRAS3_M6PR_Msk & ((value) << MATRIX_PRAS3_M6PR_Pos)))\r
+/* -------- MATRIX_PRAS4 : (MATRIX Offset: 0x00A0) Priority Register A for Slave 4 -------- */\r
+#define MATRIX_PRAS4_M0PR_Pos 0\r
+#define MATRIX_PRAS4_M0PR_Msk (0x3u << MATRIX_PRAS4_M0PR_Pos) /**< \brief (MATRIX_PRAS4) Master 0 Priority */\r
+#define MATRIX_PRAS4_M0PR(value) ((MATRIX_PRAS4_M0PR_Msk & ((value) << MATRIX_PRAS4_M0PR_Pos)))\r
+#define MATRIX_PRAS4_M1PR_Pos 4\r
+#define MATRIX_PRAS4_M1PR_Msk (0x3u << MATRIX_PRAS4_M1PR_Pos) /**< \brief (MATRIX_PRAS4) Master 1 Priority */\r
+#define MATRIX_PRAS4_M1PR(value) ((MATRIX_PRAS4_M1PR_Msk & ((value) << MATRIX_PRAS4_M1PR_Pos)))\r
+#define MATRIX_PRAS4_M2PR_Pos 8\r
+#define MATRIX_PRAS4_M2PR_Msk (0x3u << MATRIX_PRAS4_M2PR_Pos) /**< \brief (MATRIX_PRAS4) Master 2 Priority */\r
+#define MATRIX_PRAS4_M2PR(value) ((MATRIX_PRAS4_M2PR_Msk & ((value) << MATRIX_PRAS4_M2PR_Pos)))\r
+#define MATRIX_PRAS4_M3PR_Pos 12\r
+#define MATRIX_PRAS4_M3PR_Msk (0x3u << MATRIX_PRAS4_M3PR_Pos) /**< \brief (MATRIX_PRAS4) Master 3 Priority */\r
+#define MATRIX_PRAS4_M3PR(value) ((MATRIX_PRAS4_M3PR_Msk & ((value) << MATRIX_PRAS4_M3PR_Pos)))\r
+#define MATRIX_PRAS4_M4PR_Pos 16\r
+#define MATRIX_PRAS4_M4PR_Msk (0x3u << MATRIX_PRAS4_M4PR_Pos) /**< \brief (MATRIX_PRAS4) Master 4 Priority */\r
+#define MATRIX_PRAS4_M4PR(value) ((MATRIX_PRAS4_M4PR_Msk & ((value) << MATRIX_PRAS4_M4PR_Pos)))\r
+#define MATRIX_PRAS4_M5PR_Pos 20\r
+#define MATRIX_PRAS4_M5PR_Msk (0x3u << MATRIX_PRAS4_M5PR_Pos) /**< \brief (MATRIX_PRAS4) Master 5 Priority */\r
+#define MATRIX_PRAS4_M5PR(value) ((MATRIX_PRAS4_M5PR_Msk & ((value) << MATRIX_PRAS4_M5PR_Pos)))\r
+#define MATRIX_PRAS4_M6PR_Pos 24\r
+#define MATRIX_PRAS4_M6PR_Msk (0x3u << MATRIX_PRAS4_M6PR_Pos) /**< \brief (MATRIX_PRAS4) Master 6 Priority */\r
+#define MATRIX_PRAS4_M6PR(value) ((MATRIX_PRAS4_M6PR_Msk & ((value) << MATRIX_PRAS4_M6PR_Pos)))\r
+/* -------- MATRIX_PRAS5 : (MATRIX Offset: 0x00A8) Priority Register A for Slave 5 -------- */\r
+#define MATRIX_PRAS5_M0PR_Pos 0\r
+#define MATRIX_PRAS5_M0PR_Msk (0x3u << MATRIX_PRAS5_M0PR_Pos) /**< \brief (MATRIX_PRAS5) Master 0 Priority */\r
+#define MATRIX_PRAS5_M0PR(value) ((MATRIX_PRAS5_M0PR_Msk & ((value) << MATRIX_PRAS5_M0PR_Pos)))\r
+#define MATRIX_PRAS5_M1PR_Pos 4\r
+#define MATRIX_PRAS5_M1PR_Msk (0x3u << MATRIX_PRAS5_M1PR_Pos) /**< \brief (MATRIX_PRAS5) Master 1 Priority */\r
+#define MATRIX_PRAS5_M1PR(value) ((MATRIX_PRAS5_M1PR_Msk & ((value) << MATRIX_PRAS5_M1PR_Pos)))\r
+#define MATRIX_PRAS5_M2PR_Pos 8\r
+#define MATRIX_PRAS5_M2PR_Msk (0x3u << MATRIX_PRAS5_M2PR_Pos) /**< \brief (MATRIX_PRAS5) Master 2 Priority */\r
+#define MATRIX_PRAS5_M2PR(value) ((MATRIX_PRAS5_M2PR_Msk & ((value) << MATRIX_PRAS5_M2PR_Pos)))\r
+#define MATRIX_PRAS5_M3PR_Pos 12\r
+#define MATRIX_PRAS5_M3PR_Msk (0x3u << MATRIX_PRAS5_M3PR_Pos) /**< \brief (MATRIX_PRAS5) Master 3 Priority */\r
+#define MATRIX_PRAS5_M3PR(value) ((MATRIX_PRAS5_M3PR_Msk & ((value) << MATRIX_PRAS5_M3PR_Pos)))\r
+#define MATRIX_PRAS5_M4PR_Pos 16\r
+#define MATRIX_PRAS5_M4PR_Msk (0x3u << MATRIX_PRAS5_M4PR_Pos) /**< \brief (MATRIX_PRAS5) Master 4 Priority */\r
+#define MATRIX_PRAS5_M4PR(value) ((MATRIX_PRAS5_M4PR_Msk & ((value) << MATRIX_PRAS5_M4PR_Pos)))\r
+#define MATRIX_PRAS5_M5PR_Pos 20\r
+#define MATRIX_PRAS5_M5PR_Msk (0x3u << MATRIX_PRAS5_M5PR_Pos) /**< \brief (MATRIX_PRAS5) Master 5 Priority */\r
+#define MATRIX_PRAS5_M5PR(value) ((MATRIX_PRAS5_M5PR_Msk & ((value) << MATRIX_PRAS5_M5PR_Pos)))\r
+#define MATRIX_PRAS5_M6PR_Pos 24\r
+#define MATRIX_PRAS5_M6PR_Msk (0x3u << MATRIX_PRAS5_M6PR_Pos) /**< \brief (MATRIX_PRAS5) Master 6 Priority */\r
+#define MATRIX_PRAS5_M6PR(value) ((MATRIX_PRAS5_M6PR_Msk & ((value) << MATRIX_PRAS5_M6PR_Pos)))\r
+/* -------- MATRIX_MRCR : (MATRIX Offset: 0x0100) Master Remap Control Register -------- */\r
+#define MATRIX_MRCR_RCB0 (0x1u << 0) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 0 */\r
+#define MATRIX_MRCR_RCB1 (0x1u << 1) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 1 */\r
+#define MATRIX_MRCR_RCB2 (0x1u << 2) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 2 */\r
+#define MATRIX_MRCR_RCB3 (0x1u << 3) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 3 */\r
+#define MATRIX_MRCR_RCB4 (0x1u << 4) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 4 */\r
+#define MATRIX_MRCR_RCB5 (0x1u << 5) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 5 */\r
+#define MATRIX_MRCR_RCB6 (0x1u << 6) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 6 */\r
+/* -------- CCFG_SYSIO : (MATRIX Offset: 0x0114) System I/O Configuration Register -------- */\r
+#define CCFG_SYSIO_SYSIO4 (0x1u << 4) /**< \brief (CCFG_SYSIO) PB4 or TDI Assignment */\r
+#define CCFG_SYSIO_SYSIO5 (0x1u << 5) /**< \brief (CCFG_SYSIO) PB5 or TDO/TRACESWO Assignment */\r
+#define CCFG_SYSIO_SYSIO6 (0x1u << 6) /**< \brief (CCFG_SYSIO) PB6 or TMS/SWDIO Assignment */\r
+#define CCFG_SYSIO_SYSIO7 (0x1u << 7) /**< \brief (CCFG_SYSIO) PB7 or TCK/SWCLK Assignment */\r
+#define CCFG_SYSIO_SYSIO10 (0x1u << 10) /**< \brief (CCFG_SYSIO) PB10 or DDM Assignment */\r
+#define CCFG_SYSIO_SYSIO11 (0x1u << 11) /**< \brief (CCFG_SYSIO) PB11 or DDP Assignment */\r
+#define CCFG_SYSIO_SYSIO12 (0x1u << 12) /**< \brief (CCFG_SYSIO) PB12 or ERASE Assignment */\r
+/* -------- CCFG_SMCNFCS : (MATRIX Offset: 0x0124) SMC NAND Flash Chip Select Configuration Register -------- */\r
+#define CCFG_SMCNFCS_SMC_NFCS0 (0x1u << 0) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 0 Assignment */\r
+#define CCFG_SMCNFCS_SMC_NFCS1 (0x1u << 1) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 1 Assignment */\r
+#define CCFG_SMCNFCS_SMC_NFCS2 (0x1u << 2) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 2 Assignment */\r
+#define CCFG_SMCNFCS_SMC_NFCS3 (0x1u << 3) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 3 Assignment */\r
+/* -------- MATRIX_WPMR : (MATRIX Offset: 0x01E4) Write Protect Mode Register -------- */\r
+#define MATRIX_WPMR_WPEN (0x1u << 0) /**< \brief (MATRIX_WPMR) Write Protect Enable */\r
+#define MATRIX_WPMR_WPKEY_Pos 8\r
+#define MATRIX_WPMR_WPKEY_Msk (0xffffffu << MATRIX_WPMR_WPKEY_Pos) /**< \brief (MATRIX_WPMR) Write Protect KEY (Write-only) */\r
+#define MATRIX_WPMR_WPKEY(value) ((MATRIX_WPMR_WPKEY_Msk & ((value) << MATRIX_WPMR_WPKEY_Pos)))\r
+/* -------- MATRIX_WPSR : (MATRIX Offset: 0x01E8) Write Protect Status Register -------- */\r
+#define MATRIX_WPSR_WPVS (0x1u << 0) /**< \brief (MATRIX_WPSR) Write Protect Violation Status */\r
+#define MATRIX_WPSR_WPVSRC_Pos 8\r
+#define MATRIX_WPSR_WPVSRC_Msk (0xffffu << MATRIX_WPSR_WPVSRC_Pos) /**< \brief (MATRIX_WPSR) Write Protect Violation Source */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM4E_MATRIX_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4E_PDC_COMPONENT_\r
+#define _SAM4E_PDC_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Peripheral DMA Controller */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM4E_PDC Peripheral DMA Controller */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Pdc hardware registers */\r
+typedef struct {\r
+ RwReg PERIPH_RPR; /**< \brief (Pdc Offset: 0x00) Receive Pointer Register */\r
+ RwReg PERIPH_RCR; /**< \brief (Pdc Offset: 0x04) Receive Counter Register */\r
+ RwReg PERIPH_TPR; /**< \brief (Pdc Offset: 0x08) Transmit Pointer Register */\r
+ RwReg PERIPH_TCR; /**< \brief (Pdc Offset: 0x0C) Transmit Counter Register */\r
+ RwReg PERIPH_RNPR; /**< \brief (Pdc Offset: 0x10) Receive Next Pointer Register */\r
+ RwReg PERIPH_RNCR; /**< \brief (Pdc Offset: 0x14) Receive Next Counter Register */\r
+ RwReg PERIPH_TNPR; /**< \brief (Pdc Offset: 0x18) Transmit Next Pointer Register */\r
+ RwReg PERIPH_TNCR; /**< \brief (Pdc Offset: 0x1C) Transmit Next Counter Register */\r
+ WoReg PERIPH_PTCR; /**< \brief (Pdc Offset: 0x20) Transfer Control Register */\r
+ RoReg PERIPH_PTSR; /**< \brief (Pdc Offset: 0x24) Transfer Status Register */\r
+} Pdc;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- PERIPH_RPR : (PDC Offset: 0x00) Receive Pointer Register -------- */\r
+#define PERIPH_RPR_RXPTR_Pos 0\r
+#define PERIPH_RPR_RXPTR_Msk (0xffffffffu << PERIPH_RPR_RXPTR_Pos) /**< \brief (PERIPH_RPR) Receive Pointer Register */\r
+#define PERIPH_RPR_RXPTR(value) ((PERIPH_RPR_RXPTR_Msk & ((value) << PERIPH_RPR_RXPTR_Pos)))\r
+/* -------- PERIPH_RCR : (PDC Offset: 0x04) Receive Counter Register -------- */\r
+#define PERIPH_RCR_RXCTR_Pos 0\r
+#define PERIPH_RCR_RXCTR_Msk (0xffffu << PERIPH_RCR_RXCTR_Pos) /**< \brief (PERIPH_RCR) Receive Counter Register */\r
+#define PERIPH_RCR_RXCTR(value) ((PERIPH_RCR_RXCTR_Msk & ((value) << PERIPH_RCR_RXCTR_Pos)))\r
+/* -------- PERIPH_TPR : (PDC Offset: 0x08) Transmit Pointer Register -------- */\r
+#define PERIPH_TPR_TXPTR_Pos 0\r
+#define PERIPH_TPR_TXPTR_Msk (0xffffffffu << PERIPH_TPR_TXPTR_Pos) /**< \brief (PERIPH_TPR) Transmit Counter Register */\r
+#define PERIPH_TPR_TXPTR(value) ((PERIPH_TPR_TXPTR_Msk & ((value) << PERIPH_TPR_TXPTR_Pos)))\r
+/* -------- PERIPH_TCR : (PDC Offset: 0x0C) Transmit Counter Register -------- */\r
+#define PERIPH_TCR_TXCTR_Pos 0\r
+#define PERIPH_TCR_TXCTR_Msk (0xffffu << PERIPH_TCR_TXCTR_Pos) /**< \brief (PERIPH_TCR) Transmit Counter Register */\r
+#define PERIPH_TCR_TXCTR(value) ((PERIPH_TCR_TXCTR_Msk & ((value) << PERIPH_TCR_TXCTR_Pos)))\r
+/* -------- PERIPH_RNPR : (PDC Offset: 0x10) Receive Next Pointer Register -------- */\r
+#define PERIPH_RNPR_RXNPTR_Pos 0\r
+#define PERIPH_RNPR_RXNPTR_Msk (0xffffffffu << PERIPH_RNPR_RXNPTR_Pos) /**< \brief (PERIPH_RNPR) Receive Next Pointer */\r
+#define PERIPH_RNPR_RXNPTR(value) ((PERIPH_RNPR_RXNPTR_Msk & ((value) << PERIPH_RNPR_RXNPTR_Pos)))\r
+/* -------- PERIPH_RNCR : (PDC Offset: 0x14) Receive Next Counter Register -------- */\r
+#define PERIPH_RNCR_RXNCTR_Pos 0\r
+#define PERIPH_RNCR_RXNCTR_Msk (0xffffu << PERIPH_RNCR_RXNCTR_Pos) /**< \brief (PERIPH_RNCR) Receive Next Counter */\r
+#define PERIPH_RNCR_RXNCTR(value) ((PERIPH_RNCR_RXNCTR_Msk & ((value) << PERIPH_RNCR_RXNCTR_Pos)))\r
+/* -------- PERIPH_TNPR : (PDC Offset: 0x18) Transmit Next Pointer Register -------- */\r
+#define PERIPH_TNPR_TXNPTR_Pos 0\r
+#define PERIPH_TNPR_TXNPTR_Msk (0xffffffffu << PERIPH_TNPR_TXNPTR_Pos) /**< \brief (PERIPH_TNPR) Transmit Next Pointer */\r
+#define PERIPH_TNPR_TXNPTR(value) ((PERIPH_TNPR_TXNPTR_Msk & ((value) << PERIPH_TNPR_TXNPTR_Pos)))\r
+/* -------- PERIPH_TNCR : (PDC Offset: 0x1C) Transmit Next Counter Register -------- */\r
+#define PERIPH_TNCR_TXNCTR_Pos 0\r
+#define PERIPH_TNCR_TXNCTR_Msk (0xffffu << PERIPH_TNCR_TXNCTR_Pos) /**< \brief (PERIPH_TNCR) Transmit Counter Next */\r
+#define PERIPH_TNCR_TXNCTR(value) ((PERIPH_TNCR_TXNCTR_Msk & ((value) << PERIPH_TNCR_TXNCTR_Pos)))\r
+/* -------- PERIPH_PTCR : (PDC Offset: 0x20) Transfer Control Register -------- */\r
+#define PERIPH_PTCR_RXTEN (0x1u << 0) /**< \brief (PERIPH_PTCR) Receiver Transfer Enable */\r
+#define PERIPH_PTCR_RXTDIS (0x1u << 1) /**< \brief (PERIPH_PTCR) Receiver Transfer Disable */\r
+#define PERIPH_PTCR_TXTEN (0x1u << 8) /**< \brief (PERIPH_PTCR) Transmitter Transfer Enable */\r
+#define PERIPH_PTCR_TXTDIS (0x1u << 9) /**< \brief (PERIPH_PTCR) Transmitter Transfer Disable */\r
+/* -------- PERIPH_PTSR : (PDC Offset: 0x24) Transfer Status Register -------- */\r
+#define PERIPH_PTSR_RXTEN (0x1u << 0) /**< \brief (PERIPH_PTSR) Receiver Transfer Enable */\r
+#define PERIPH_PTSR_TXTEN (0x1u << 8) /**< \brief (PERIPH_PTSR) Transmitter Transfer Enable */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM4E_PDC_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4E_PIO_COMPONENT_\r
+#define _SAM4E_PIO_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Parallel Input/Output Controller */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM4E_PIO Parallel Input/Output Controller */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Pio hardware registers */\r
+typedef struct {\r
+ WoReg PIO_PER; /**< \brief (Pio Offset: 0x0000) PIO Enable Register */\r
+ WoReg PIO_PDR; /**< \brief (Pio Offset: 0x0004) PIO Disable Register */\r
+ RoReg PIO_PSR; /**< \brief (Pio Offset: 0x0008) PIO Status Register */\r
+ RoReg Reserved1[1];\r
+ WoReg PIO_OER; /**< \brief (Pio Offset: 0x0010) Output Enable Register */\r
+ WoReg PIO_ODR; /**< \brief (Pio Offset: 0x0014) Output Disable Register */\r
+ RoReg PIO_OSR; /**< \brief (Pio Offset: 0x0018) Output Status Register */\r
+ RoReg Reserved2[1];\r
+ WoReg PIO_IFER; /**< \brief (Pio Offset: 0x0020) Glitch Input Filter Enable Register */\r
+ WoReg PIO_IFDR; /**< \brief (Pio Offset: 0x0024) Glitch Input Filter Disable Register */\r
+ RoReg PIO_IFSR; /**< \brief (Pio Offset: 0x0028) Glitch Input Filter Status Register */\r
+ RoReg Reserved3[1];\r
+ WoReg PIO_SODR; /**< \brief (Pio Offset: 0x0030) Set Output Data Register */\r
+ WoReg PIO_CODR; /**< \brief (Pio Offset: 0x0034) Clear Output Data Register */\r
+ RwReg PIO_ODSR; /**< \brief (Pio Offset: 0x0038) Output Data Status Register */\r
+ RoReg PIO_PDSR; /**< \brief (Pio Offset: 0x003C) Pin Data Status Register */\r
+ WoReg PIO_IER; /**< \brief (Pio Offset: 0x0040) Interrupt Enable Register */\r
+ WoReg PIO_IDR; /**< \brief (Pio Offset: 0x0044) Interrupt Disable Register */\r
+ RoReg PIO_IMR; /**< \brief (Pio Offset: 0x0048) Interrupt Mask Register */\r
+ RoReg PIO_ISR; /**< \brief (Pio Offset: 0x004C) Interrupt Status Register */\r
+ WoReg PIO_MDER; /**< \brief (Pio Offset: 0x0050) Multi-driver Enable Register */\r
+ WoReg PIO_MDDR; /**< \brief (Pio Offset: 0x0054) Multi-driver Disable Register */\r
+ RoReg PIO_MDSR; /**< \brief (Pio Offset: 0x0058) Multi-driver Status Register */\r
+ RoReg Reserved4[1];\r
+ WoReg PIO_PUDR; /**< \brief (Pio Offset: 0x0060) Pull-up Disable Register */\r
+ WoReg PIO_PUER; /**< \brief (Pio Offset: 0x0064) Pull-up Enable Register */\r
+ RoReg PIO_PUSR; /**< \brief (Pio Offset: 0x0068) Pad Pull-up Status Register */\r
+ RoReg Reserved5[1];\r
+ RwReg PIO_ABCDSR[2]; /**< \brief (Pio Offset: 0x0070) Peripheral Select Register */\r
+ RoReg Reserved6[2];\r
+ WoReg PIO_IFSCDR; /**< \brief (Pio Offset: 0x0080) Input Filter Slow Clock Disable Register */\r
+ WoReg PIO_IFSCER; /**< \brief (Pio Offset: 0x0084) Input Filter Slow Clock Enable Register */\r
+ RoReg PIO_IFSCSR; /**< \brief (Pio Offset: 0x0088) Input Filter Slow Clock Status Register */\r
+ RwReg PIO_SCDR; /**< \brief (Pio Offset: 0x008C) Slow Clock Divider Debouncing Register */\r
+ WoReg PIO_PPDDR; /**< \brief (Pio Offset: 0x0090) Pad Pull-down Disable Register */\r
+ WoReg PIO_PPDER; /**< \brief (Pio Offset: 0x0094) Pad Pull-down Enable Register */\r
+ RoReg PIO_PPDSR; /**< \brief (Pio Offset: 0x0098) Pad Pull-down Status Register */\r
+ RoReg Reserved7[1];\r
+ WoReg PIO_OWER; /**< \brief (Pio Offset: 0x00A0) Output Write Enable */\r
+ WoReg PIO_OWDR; /**< \brief (Pio Offset: 0x00A4) Output Write Disable */\r
+ RoReg PIO_OWSR; /**< \brief (Pio Offset: 0x00A8) Output Write Status Register */\r
+ RoReg Reserved8[1];\r
+ WoReg PIO_AIMER; /**< \brief (Pio Offset: 0x00B0) Additional Interrupt Modes Enable Register */\r
+ WoReg PIO_AIMDR; /**< \brief (Pio Offset: 0x00B4) Additional Interrupt Modes Disables Register */\r
+ RoReg PIO_AIMMR; /**< \brief (Pio Offset: 0x00B8) Additional Interrupt Modes Mask Register */\r
+ RoReg Reserved9[1];\r
+ WoReg PIO_ESR; /**< \brief (Pio Offset: 0x00C0) Edge Select Register */\r
+ WoReg PIO_LSR; /**< \brief (Pio Offset: 0x00C4) Level Select Register */\r
+ RoReg PIO_ELSR; /**< \brief (Pio Offset: 0x00C8) Edge/Level Status Register */\r
+ RoReg Reserved10[1];\r
+ WoReg PIO_FELLSR; /**< \brief (Pio Offset: 0x00D0) Falling Edge/Low Level Select Register */\r
+ WoReg PIO_REHLSR; /**< \brief (Pio Offset: 0x00D4) Rising Edge/ High Level Select Register */\r
+ RoReg PIO_FRLHSR; /**< \brief (Pio Offset: 0x00D8) Fall/Rise - Low/High Status Register */\r
+ RoReg Reserved11[1];\r
+ RoReg PIO_LOCKSR; /**< \brief (Pio Offset: 0x00E0) Lock Status */\r
+ RwReg PIO_WPMR; /**< \brief (Pio Offset: 0x00E4) Write Protect Mode Register */\r
+ RoReg PIO_WPSR; /**< \brief (Pio Offset: 0x00E8) Write Protect Status Register */\r
+ RoReg Reserved12[5];\r
+ RwReg PIO_SCHMITT; /**< \brief (Pio Offset: 0x0100) Schmitt Trigger Register */\r
+ RoReg Reserved13[3];\r
+ RwReg PIO_DELAYR; /**< \brief (Pio Offset: 0x0110) IO Delay Register */\r
+ RoReg Reserved14[15];\r
+ RwReg PIO_PCMR; /**< \brief (Pio Offset: 0x150) Parallel Capture Mode Register */\r
+ WoReg PIO_PCIER; /**< \brief (Pio Offset: 0x154) Parallel Capture Interrupt Enable Register */\r
+ WoReg PIO_PCIDR; /**< \brief (Pio Offset: 0x158) Parallel Capture Interrupt Disable Register */\r
+ RoReg PIO_PCIMR; /**< \brief (Pio Offset: 0x15C) Parallel Capture Interrupt Mask Register */\r
+ RoReg PIO_PCISR; /**< \brief (Pio Offset: 0x160) Parallel Capture Interrupt Status Register */\r
+ RoReg PIO_PCRHR; /**< \brief (Pio Offset: 0x164) Parallel Capture Reception Holding Register */\r
+ RwReg PIO_RPR; /**< \brief (Pio Offset: 0x168) Receive Pointer Register */\r
+ RwReg PIO_RCR; /**< \brief (Pio Offset: 0x16C) Receive Counter Register */\r
+ RoReg Reserved15[2];\r
+ RwReg PIO_RNPR; /**< \brief (Pio Offset: 0x178) Receive Next Pointer Register */\r
+ RwReg PIO_RNCR; /**< \brief (Pio Offset: 0x17C) Receive Next Counter Register */\r
+ RoReg Reserved16[2];\r
+ WoReg PIO_PTCR; /**< \brief (Pio Offset: 0x188) Transfer Control Register */\r
+ RoReg PIO_PTSR; /**< \brief (Pio Offset: 0x18C) Transfer Status Register */\r
+} Pio;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- PIO_PER : (PIO Offset: 0x0000) PIO Enable Register -------- */\r
+#define PIO_PER_P0 (0x1u << 0) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P1 (0x1u << 1) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P2 (0x1u << 2) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P3 (0x1u << 3) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P4 (0x1u << 4) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P5 (0x1u << 5) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P6 (0x1u << 6) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P7 (0x1u << 7) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P8 (0x1u << 8) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P9 (0x1u << 9) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P10 (0x1u << 10) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P11 (0x1u << 11) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P12 (0x1u << 12) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P13 (0x1u << 13) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P14 (0x1u << 14) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P15 (0x1u << 15) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P16 (0x1u << 16) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P17 (0x1u << 17) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P18 (0x1u << 18) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P19 (0x1u << 19) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P20 (0x1u << 20) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P21 (0x1u << 21) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P22 (0x1u << 22) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P23 (0x1u << 23) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P24 (0x1u << 24) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P25 (0x1u << 25) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P26 (0x1u << 26) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P27 (0x1u << 27) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P28 (0x1u << 28) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P29 (0x1u << 29) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P30 (0x1u << 30) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P31 (0x1u << 31) /**< \brief (PIO_PER) PIO Enable */\r
+/* -------- PIO_PDR : (PIO Offset: 0x0004) PIO Disable Register -------- */\r
+#define PIO_PDR_P0 (0x1u << 0) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P1 (0x1u << 1) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P2 (0x1u << 2) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P3 (0x1u << 3) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P4 (0x1u << 4) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P5 (0x1u << 5) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P6 (0x1u << 6) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P7 (0x1u << 7) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P8 (0x1u << 8) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P9 (0x1u << 9) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P10 (0x1u << 10) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P11 (0x1u << 11) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P12 (0x1u << 12) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P13 (0x1u << 13) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P14 (0x1u << 14) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P15 (0x1u << 15) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P16 (0x1u << 16) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P17 (0x1u << 17) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P18 (0x1u << 18) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P19 (0x1u << 19) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P20 (0x1u << 20) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P21 (0x1u << 21) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P22 (0x1u << 22) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P23 (0x1u << 23) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P24 (0x1u << 24) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P25 (0x1u << 25) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P26 (0x1u << 26) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P27 (0x1u << 27) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P28 (0x1u << 28) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P29 (0x1u << 29) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P30 (0x1u << 30) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P31 (0x1u << 31) /**< \brief (PIO_PDR) PIO Disable */\r
+/* -------- PIO_PSR : (PIO Offset: 0x0008) PIO Status Register -------- */\r
+#define PIO_PSR_P0 (0x1u << 0) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P1 (0x1u << 1) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P2 (0x1u << 2) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P3 (0x1u << 3) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P4 (0x1u << 4) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P5 (0x1u << 5) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P6 (0x1u << 6) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P7 (0x1u << 7) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P8 (0x1u << 8) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P9 (0x1u << 9) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P10 (0x1u << 10) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P11 (0x1u << 11) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P12 (0x1u << 12) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P13 (0x1u << 13) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P14 (0x1u << 14) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P15 (0x1u << 15) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P16 (0x1u << 16) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P17 (0x1u << 17) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P18 (0x1u << 18) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P19 (0x1u << 19) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P20 (0x1u << 20) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P21 (0x1u << 21) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P22 (0x1u << 22) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P23 (0x1u << 23) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P24 (0x1u << 24) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P25 (0x1u << 25) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P26 (0x1u << 26) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P27 (0x1u << 27) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P28 (0x1u << 28) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P29 (0x1u << 29) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P30 (0x1u << 30) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P31 (0x1u << 31) /**< \brief (PIO_PSR) PIO Status */\r
+/* -------- PIO_OER : (PIO Offset: 0x0010) Output Enable Register -------- */\r
+#define PIO_OER_P0 (0x1u << 0) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P1 (0x1u << 1) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P2 (0x1u << 2) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P3 (0x1u << 3) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P4 (0x1u << 4) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P5 (0x1u << 5) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P6 (0x1u << 6) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P7 (0x1u << 7) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P8 (0x1u << 8) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P9 (0x1u << 9) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P10 (0x1u << 10) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P11 (0x1u << 11) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P12 (0x1u << 12) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P13 (0x1u << 13) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P14 (0x1u << 14) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P15 (0x1u << 15) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P16 (0x1u << 16) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P17 (0x1u << 17) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P18 (0x1u << 18) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P19 (0x1u << 19) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P20 (0x1u << 20) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P21 (0x1u << 21) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P22 (0x1u << 22) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P23 (0x1u << 23) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P24 (0x1u << 24) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P25 (0x1u << 25) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P26 (0x1u << 26) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P27 (0x1u << 27) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P28 (0x1u << 28) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P29 (0x1u << 29) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P30 (0x1u << 30) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P31 (0x1u << 31) /**< \brief (PIO_OER) Output Enable */\r
+/* -------- PIO_ODR : (PIO Offset: 0x0014) Output Disable Register -------- */\r
+#define PIO_ODR_P0 (0x1u << 0) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P1 (0x1u << 1) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P2 (0x1u << 2) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P3 (0x1u << 3) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P4 (0x1u << 4) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P5 (0x1u << 5) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P6 (0x1u << 6) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P7 (0x1u << 7) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P8 (0x1u << 8) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P9 (0x1u << 9) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P10 (0x1u << 10) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P11 (0x1u << 11) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P12 (0x1u << 12) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P13 (0x1u << 13) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P14 (0x1u << 14) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P15 (0x1u << 15) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P16 (0x1u << 16) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P17 (0x1u << 17) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P18 (0x1u << 18) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P19 (0x1u << 19) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P20 (0x1u << 20) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P21 (0x1u << 21) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P22 (0x1u << 22) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P23 (0x1u << 23) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P24 (0x1u << 24) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P25 (0x1u << 25) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P26 (0x1u << 26) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P27 (0x1u << 27) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P28 (0x1u << 28) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P29 (0x1u << 29) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P30 (0x1u << 30) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P31 (0x1u << 31) /**< \brief (PIO_ODR) Output Disable */\r
+/* -------- PIO_OSR : (PIO Offset: 0x0018) Output Status Register -------- */\r
+#define PIO_OSR_P0 (0x1u << 0) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P1 (0x1u << 1) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P2 (0x1u << 2) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P3 (0x1u << 3) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P4 (0x1u << 4) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P5 (0x1u << 5) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P6 (0x1u << 6) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P7 (0x1u << 7) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P8 (0x1u << 8) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P9 (0x1u << 9) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P10 (0x1u << 10) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P11 (0x1u << 11) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P12 (0x1u << 12) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P13 (0x1u << 13) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P14 (0x1u << 14) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P15 (0x1u << 15) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P16 (0x1u << 16) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P17 (0x1u << 17) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P18 (0x1u << 18) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P19 (0x1u << 19) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P20 (0x1u << 20) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P21 (0x1u << 21) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P22 (0x1u << 22) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P23 (0x1u << 23) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P24 (0x1u << 24) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P25 (0x1u << 25) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P26 (0x1u << 26) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P27 (0x1u << 27) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P28 (0x1u << 28) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P29 (0x1u << 29) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P30 (0x1u << 30) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P31 (0x1u << 31) /**< \brief (PIO_OSR) Output Status */\r
+/* -------- PIO_IFER : (PIO Offset: 0x0020) Glitch Input Filter Enable Register -------- */\r
+#define PIO_IFER_P0 (0x1u << 0) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P1 (0x1u << 1) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P2 (0x1u << 2) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P3 (0x1u << 3) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P4 (0x1u << 4) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P5 (0x1u << 5) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P6 (0x1u << 6) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P7 (0x1u << 7) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P8 (0x1u << 8) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P9 (0x1u << 9) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P10 (0x1u << 10) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P11 (0x1u << 11) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P12 (0x1u << 12) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P13 (0x1u << 13) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P14 (0x1u << 14) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P15 (0x1u << 15) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P16 (0x1u << 16) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P17 (0x1u << 17) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P18 (0x1u << 18) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P19 (0x1u << 19) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P20 (0x1u << 20) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P21 (0x1u << 21) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P22 (0x1u << 22) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P23 (0x1u << 23) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P24 (0x1u << 24) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P25 (0x1u << 25) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P26 (0x1u << 26) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P27 (0x1u << 27) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P28 (0x1u << 28) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P29 (0x1u << 29) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P30 (0x1u << 30) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P31 (0x1u << 31) /**< \brief (PIO_IFER) Input Filter Enable */\r
+/* -------- PIO_IFDR : (PIO Offset: 0x0024) Glitch Input Filter Disable Register -------- */\r
+#define PIO_IFDR_P0 (0x1u << 0) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P1 (0x1u << 1) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P2 (0x1u << 2) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P3 (0x1u << 3) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P4 (0x1u << 4) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P5 (0x1u << 5) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P6 (0x1u << 6) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P7 (0x1u << 7) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P8 (0x1u << 8) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P9 (0x1u << 9) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P10 (0x1u << 10) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P11 (0x1u << 11) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P12 (0x1u << 12) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P13 (0x1u << 13) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P14 (0x1u << 14) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P15 (0x1u << 15) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P16 (0x1u << 16) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P17 (0x1u << 17) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P18 (0x1u << 18) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P19 (0x1u << 19) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P20 (0x1u << 20) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P21 (0x1u << 21) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P22 (0x1u << 22) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P23 (0x1u << 23) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P24 (0x1u << 24) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P25 (0x1u << 25) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P26 (0x1u << 26) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P27 (0x1u << 27) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P28 (0x1u << 28) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P29 (0x1u << 29) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P30 (0x1u << 30) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P31 (0x1u << 31) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+/* -------- PIO_IFSR : (PIO Offset: 0x0028) Glitch Input Filter Status Register -------- */\r
+#define PIO_IFSR_P0 (0x1u << 0) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P1 (0x1u << 1) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P2 (0x1u << 2) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P3 (0x1u << 3) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P4 (0x1u << 4) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P5 (0x1u << 5) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P6 (0x1u << 6) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P7 (0x1u << 7) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P8 (0x1u << 8) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P9 (0x1u << 9) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P10 (0x1u << 10) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P11 (0x1u << 11) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P12 (0x1u << 12) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P13 (0x1u << 13) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P14 (0x1u << 14) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P15 (0x1u << 15) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P16 (0x1u << 16) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P17 (0x1u << 17) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P18 (0x1u << 18) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P19 (0x1u << 19) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P20 (0x1u << 20) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P21 (0x1u << 21) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P22 (0x1u << 22) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P23 (0x1u << 23) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P24 (0x1u << 24) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P25 (0x1u << 25) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P26 (0x1u << 26) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P27 (0x1u << 27) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P28 (0x1u << 28) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P29 (0x1u << 29) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P30 (0x1u << 30) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P31 (0x1u << 31) /**< \brief (PIO_IFSR) Input Filer Status */\r
+/* -------- PIO_SODR : (PIO Offset: 0x0030) Set Output Data Register -------- */\r
+#define PIO_SODR_P0 (0x1u << 0) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P1 (0x1u << 1) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P2 (0x1u << 2) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P3 (0x1u << 3) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P4 (0x1u << 4) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P5 (0x1u << 5) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P6 (0x1u << 6) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P7 (0x1u << 7) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P8 (0x1u << 8) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P9 (0x1u << 9) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P10 (0x1u << 10) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P11 (0x1u << 11) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P12 (0x1u << 12) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P13 (0x1u << 13) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P14 (0x1u << 14) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P15 (0x1u << 15) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P16 (0x1u << 16) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P17 (0x1u << 17) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P18 (0x1u << 18) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P19 (0x1u << 19) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P20 (0x1u << 20) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P21 (0x1u << 21) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P22 (0x1u << 22) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P23 (0x1u << 23) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P24 (0x1u << 24) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P25 (0x1u << 25) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P26 (0x1u << 26) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P27 (0x1u << 27) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P28 (0x1u << 28) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P29 (0x1u << 29) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P30 (0x1u << 30) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P31 (0x1u << 31) /**< \brief (PIO_SODR) Set Output Data */\r
+/* -------- PIO_CODR : (PIO Offset: 0x0034) Clear Output Data Register -------- */\r
+#define PIO_CODR_P0 (0x1u << 0) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P1 (0x1u << 1) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P2 (0x1u << 2) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P3 (0x1u << 3) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P4 (0x1u << 4) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P5 (0x1u << 5) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P6 (0x1u << 6) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P7 (0x1u << 7) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P8 (0x1u << 8) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P9 (0x1u << 9) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P10 (0x1u << 10) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P11 (0x1u << 11) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P12 (0x1u << 12) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P13 (0x1u << 13) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P14 (0x1u << 14) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P15 (0x1u << 15) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P16 (0x1u << 16) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P17 (0x1u << 17) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P18 (0x1u << 18) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P19 (0x1u << 19) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P20 (0x1u << 20) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P21 (0x1u << 21) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P22 (0x1u << 22) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P23 (0x1u << 23) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P24 (0x1u << 24) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P25 (0x1u << 25) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P26 (0x1u << 26) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P27 (0x1u << 27) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P28 (0x1u << 28) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P29 (0x1u << 29) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P30 (0x1u << 30) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P31 (0x1u << 31) /**< \brief (PIO_CODR) Clear Output Data */\r
+/* -------- PIO_ODSR : (PIO Offset: 0x0038) Output Data Status Register -------- */\r
+#define PIO_ODSR_P0 (0x1u << 0) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P1 (0x1u << 1) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P2 (0x1u << 2) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P3 (0x1u << 3) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P4 (0x1u << 4) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P5 (0x1u << 5) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P6 (0x1u << 6) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P7 (0x1u << 7) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P8 (0x1u << 8) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P9 (0x1u << 9) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P10 (0x1u << 10) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P11 (0x1u << 11) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P12 (0x1u << 12) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P13 (0x1u << 13) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P14 (0x1u << 14) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P15 (0x1u << 15) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P16 (0x1u << 16) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P17 (0x1u << 17) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P18 (0x1u << 18) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P19 (0x1u << 19) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P20 (0x1u << 20) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P21 (0x1u << 21) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P22 (0x1u << 22) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P23 (0x1u << 23) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P24 (0x1u << 24) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P25 (0x1u << 25) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P26 (0x1u << 26) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P27 (0x1u << 27) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P28 (0x1u << 28) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P29 (0x1u << 29) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P30 (0x1u << 30) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P31 (0x1u << 31) /**< \brief (PIO_ODSR) Output Data Status */\r
+/* -------- PIO_PDSR : (PIO Offset: 0x003C) Pin Data Status Register -------- */\r
+#define PIO_PDSR_P0 (0x1u << 0) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P1 (0x1u << 1) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P2 (0x1u << 2) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P3 (0x1u << 3) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P4 (0x1u << 4) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P5 (0x1u << 5) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P6 (0x1u << 6) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P7 (0x1u << 7) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P8 (0x1u << 8) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P9 (0x1u << 9) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P10 (0x1u << 10) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P11 (0x1u << 11) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P12 (0x1u << 12) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P13 (0x1u << 13) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P14 (0x1u << 14) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P15 (0x1u << 15) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P16 (0x1u << 16) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P17 (0x1u << 17) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P18 (0x1u << 18) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P19 (0x1u << 19) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P20 (0x1u << 20) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P21 (0x1u << 21) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P22 (0x1u << 22) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P23 (0x1u << 23) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P24 (0x1u << 24) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P25 (0x1u << 25) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P26 (0x1u << 26) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P27 (0x1u << 27) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P28 (0x1u << 28) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P29 (0x1u << 29) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P30 (0x1u << 30) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P31 (0x1u << 31) /**< \brief (PIO_PDSR) Output Data Status */\r
+/* -------- PIO_IER : (PIO Offset: 0x0040) Interrupt Enable Register -------- */\r
+#define PIO_IER_P0 (0x1u << 0) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P1 (0x1u << 1) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P2 (0x1u << 2) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P3 (0x1u << 3) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P4 (0x1u << 4) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P5 (0x1u << 5) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P6 (0x1u << 6) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P7 (0x1u << 7) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P8 (0x1u << 8) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P9 (0x1u << 9) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P10 (0x1u << 10) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P11 (0x1u << 11) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P12 (0x1u << 12) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P13 (0x1u << 13) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P14 (0x1u << 14) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P15 (0x1u << 15) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P16 (0x1u << 16) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P17 (0x1u << 17) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P18 (0x1u << 18) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P19 (0x1u << 19) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P20 (0x1u << 20) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P21 (0x1u << 21) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P22 (0x1u << 22) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P23 (0x1u << 23) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P24 (0x1u << 24) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P25 (0x1u << 25) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P26 (0x1u << 26) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P27 (0x1u << 27) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P28 (0x1u << 28) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P29 (0x1u << 29) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P30 (0x1u << 30) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P31 (0x1u << 31) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+/* -------- PIO_IDR : (PIO Offset: 0x0044) Interrupt Disable Register -------- */\r
+#define PIO_IDR_P0 (0x1u << 0) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P1 (0x1u << 1) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P2 (0x1u << 2) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P3 (0x1u << 3) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P4 (0x1u << 4) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P5 (0x1u << 5) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P6 (0x1u << 6) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P7 (0x1u << 7) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P8 (0x1u << 8) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P9 (0x1u << 9) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P10 (0x1u << 10) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P11 (0x1u << 11) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P12 (0x1u << 12) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P13 (0x1u << 13) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P14 (0x1u << 14) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P15 (0x1u << 15) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P16 (0x1u << 16) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P17 (0x1u << 17) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P18 (0x1u << 18) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P19 (0x1u << 19) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P20 (0x1u << 20) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P21 (0x1u << 21) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P22 (0x1u << 22) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P23 (0x1u << 23) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P24 (0x1u << 24) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P25 (0x1u << 25) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P26 (0x1u << 26) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P27 (0x1u << 27) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P28 (0x1u << 28) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P29 (0x1u << 29) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P30 (0x1u << 30) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P31 (0x1u << 31) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+/* -------- PIO_IMR : (PIO Offset: 0x0048) Interrupt Mask Register -------- */\r
+#define PIO_IMR_P0 (0x1u << 0) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P1 (0x1u << 1) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P2 (0x1u << 2) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P3 (0x1u << 3) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P4 (0x1u << 4) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P5 (0x1u << 5) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P6 (0x1u << 6) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P7 (0x1u << 7) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P8 (0x1u << 8) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P9 (0x1u << 9) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P10 (0x1u << 10) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P11 (0x1u << 11) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P12 (0x1u << 12) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P13 (0x1u << 13) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P14 (0x1u << 14) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P15 (0x1u << 15) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P16 (0x1u << 16) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P17 (0x1u << 17) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P18 (0x1u << 18) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P19 (0x1u << 19) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P20 (0x1u << 20) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P21 (0x1u << 21) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P22 (0x1u << 22) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P23 (0x1u << 23) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P24 (0x1u << 24) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P25 (0x1u << 25) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P26 (0x1u << 26) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P27 (0x1u << 27) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P28 (0x1u << 28) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P29 (0x1u << 29) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P30 (0x1u << 30) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P31 (0x1u << 31) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+/* -------- PIO_ISR : (PIO Offset: 0x004C) Interrupt Status Register -------- */\r
+#define PIO_ISR_P0 (0x1u << 0) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P1 (0x1u << 1) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P2 (0x1u << 2) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P3 (0x1u << 3) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P4 (0x1u << 4) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P5 (0x1u << 5) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P6 (0x1u << 6) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P7 (0x1u << 7) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P8 (0x1u << 8) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P9 (0x1u << 9) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P10 (0x1u << 10) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P11 (0x1u << 11) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P12 (0x1u << 12) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P13 (0x1u << 13) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P14 (0x1u << 14) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P15 (0x1u << 15) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P16 (0x1u << 16) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P17 (0x1u << 17) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P18 (0x1u << 18) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P19 (0x1u << 19) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P20 (0x1u << 20) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P21 (0x1u << 21) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P22 (0x1u << 22) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P23 (0x1u << 23) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P24 (0x1u << 24) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P25 (0x1u << 25) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P26 (0x1u << 26) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P27 (0x1u << 27) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P28 (0x1u << 28) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P29 (0x1u << 29) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P30 (0x1u << 30) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P31 (0x1u << 31) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+/* -------- PIO_MDER : (PIO Offset: 0x0050) Multi-driver Enable Register -------- */\r
+#define PIO_MDER_P0 (0x1u << 0) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P1 (0x1u << 1) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P2 (0x1u << 2) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P3 (0x1u << 3) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P4 (0x1u << 4) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P5 (0x1u << 5) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P6 (0x1u << 6) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P7 (0x1u << 7) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P8 (0x1u << 8) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P9 (0x1u << 9) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P10 (0x1u << 10) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P11 (0x1u << 11) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P12 (0x1u << 12) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P13 (0x1u << 13) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P14 (0x1u << 14) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P15 (0x1u << 15) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P16 (0x1u << 16) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P17 (0x1u << 17) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P18 (0x1u << 18) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P19 (0x1u << 19) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P20 (0x1u << 20) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P21 (0x1u << 21) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P22 (0x1u << 22) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P23 (0x1u << 23) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P24 (0x1u << 24) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P25 (0x1u << 25) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P26 (0x1u << 26) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P27 (0x1u << 27) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P28 (0x1u << 28) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P29 (0x1u << 29) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P30 (0x1u << 30) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P31 (0x1u << 31) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+/* -------- PIO_MDDR : (PIO Offset: 0x0054) Multi-driver Disable Register -------- */\r
+#define PIO_MDDR_P0 (0x1u << 0) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P1 (0x1u << 1) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P2 (0x1u << 2) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P3 (0x1u << 3) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P4 (0x1u << 4) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P5 (0x1u << 5) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P6 (0x1u << 6) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P7 (0x1u << 7) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P8 (0x1u << 8) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P9 (0x1u << 9) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P10 (0x1u << 10) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P11 (0x1u << 11) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P12 (0x1u << 12) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P13 (0x1u << 13) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P14 (0x1u << 14) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P15 (0x1u << 15) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P16 (0x1u << 16) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P17 (0x1u << 17) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P18 (0x1u << 18) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P19 (0x1u << 19) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P20 (0x1u << 20) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P21 (0x1u << 21) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P22 (0x1u << 22) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P23 (0x1u << 23) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P24 (0x1u << 24) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P25 (0x1u << 25) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P26 (0x1u << 26) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P27 (0x1u << 27) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P28 (0x1u << 28) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P29 (0x1u << 29) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P30 (0x1u << 30) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P31 (0x1u << 31) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+/* -------- PIO_MDSR : (PIO Offset: 0x0058) Multi-driver Status Register -------- */\r
+#define PIO_MDSR_P0 (0x1u << 0) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P1 (0x1u << 1) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P2 (0x1u << 2) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P3 (0x1u << 3) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P4 (0x1u << 4) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P5 (0x1u << 5) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P6 (0x1u << 6) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P7 (0x1u << 7) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P8 (0x1u << 8) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P9 (0x1u << 9) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P10 (0x1u << 10) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P11 (0x1u << 11) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P12 (0x1u << 12) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P13 (0x1u << 13) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P14 (0x1u << 14) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P15 (0x1u << 15) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P16 (0x1u << 16) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P17 (0x1u << 17) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P18 (0x1u << 18) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P19 (0x1u << 19) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P20 (0x1u << 20) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P21 (0x1u << 21) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P22 (0x1u << 22) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P23 (0x1u << 23) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P24 (0x1u << 24) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P25 (0x1u << 25) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P26 (0x1u << 26) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P27 (0x1u << 27) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P28 (0x1u << 28) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P29 (0x1u << 29) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P30 (0x1u << 30) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P31 (0x1u << 31) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+/* -------- PIO_PUDR : (PIO Offset: 0x0060) Pull-up Disable Register -------- */\r
+#define PIO_PUDR_P0 (0x1u << 0) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P1 (0x1u << 1) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P2 (0x1u << 2) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P3 (0x1u << 3) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P4 (0x1u << 4) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P5 (0x1u << 5) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P6 (0x1u << 6) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P7 (0x1u << 7) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P8 (0x1u << 8) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P9 (0x1u << 9) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P10 (0x1u << 10) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P11 (0x1u << 11) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P12 (0x1u << 12) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P13 (0x1u << 13) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P14 (0x1u << 14) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P15 (0x1u << 15) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P16 (0x1u << 16) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P17 (0x1u << 17) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P18 (0x1u << 18) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P19 (0x1u << 19) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P20 (0x1u << 20) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P21 (0x1u << 21) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P22 (0x1u << 22) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P23 (0x1u << 23) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P24 (0x1u << 24) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P25 (0x1u << 25) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P26 (0x1u << 26) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P27 (0x1u << 27) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P28 (0x1u << 28) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P29 (0x1u << 29) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P30 (0x1u << 30) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P31 (0x1u << 31) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+/* -------- PIO_PUER : (PIO Offset: 0x0064) Pull-up Enable Register -------- */\r
+#define PIO_PUER_P0 (0x1u << 0) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P1 (0x1u << 1) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P2 (0x1u << 2) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P3 (0x1u << 3) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P4 (0x1u << 4) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P5 (0x1u << 5) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P6 (0x1u << 6) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P7 (0x1u << 7) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P8 (0x1u << 8) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P9 (0x1u << 9) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P10 (0x1u << 10) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P11 (0x1u << 11) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P12 (0x1u << 12) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P13 (0x1u << 13) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P14 (0x1u << 14) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P15 (0x1u << 15) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P16 (0x1u << 16) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P17 (0x1u << 17) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P18 (0x1u << 18) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P19 (0x1u << 19) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P20 (0x1u << 20) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P21 (0x1u << 21) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P22 (0x1u << 22) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P23 (0x1u << 23) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P24 (0x1u << 24) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P25 (0x1u << 25) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P26 (0x1u << 26) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P27 (0x1u << 27) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P28 (0x1u << 28) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P29 (0x1u << 29) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P30 (0x1u << 30) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P31 (0x1u << 31) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+/* -------- PIO_PUSR : (PIO Offset: 0x0068) Pad Pull-up Status Register -------- */\r
+#define PIO_PUSR_P0 (0x1u << 0) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P1 (0x1u << 1) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P2 (0x1u << 2) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P3 (0x1u << 3) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P4 (0x1u << 4) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P5 (0x1u << 5) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P6 (0x1u << 6) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P7 (0x1u << 7) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P8 (0x1u << 8) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P9 (0x1u << 9) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P10 (0x1u << 10) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P11 (0x1u << 11) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P12 (0x1u << 12) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P13 (0x1u << 13) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P14 (0x1u << 14) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P15 (0x1u << 15) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P16 (0x1u << 16) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P17 (0x1u << 17) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P18 (0x1u << 18) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P19 (0x1u << 19) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P20 (0x1u << 20) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P21 (0x1u << 21) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P22 (0x1u << 22) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P23 (0x1u << 23) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P24 (0x1u << 24) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P25 (0x1u << 25) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P26 (0x1u << 26) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P27 (0x1u << 27) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P28 (0x1u << 28) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P29 (0x1u << 29) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P30 (0x1u << 30) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P31 (0x1u << 31) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+/* -------- PIO_ABCDSR[2] : (PIO Offset: 0x0070) Peripheral Select Register -------- */\r
+#define PIO_ABCDSR_P0 (0x1u << 0) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */\r
+#define PIO_ABCDSR_P1 (0x1u << 1) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */\r
+#define PIO_ABCDSR_P2 (0x1u << 2) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */\r
+#define PIO_ABCDSR_P3 (0x1u << 3) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */\r
+#define PIO_ABCDSR_P4 (0x1u << 4) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */\r
+#define PIO_ABCDSR_P5 (0x1u << 5) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */\r
+#define PIO_ABCDSR_P6 (0x1u << 6) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */\r
+#define PIO_ABCDSR_P7 (0x1u << 7) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */\r
+#define PIO_ABCDSR_P8 (0x1u << 8) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */\r
+#define PIO_ABCDSR_P9 (0x1u << 9) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */\r
+#define PIO_ABCDSR_P10 (0x1u << 10) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */\r
+#define PIO_ABCDSR_P11 (0x1u << 11) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */\r
+#define PIO_ABCDSR_P12 (0x1u << 12) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */\r
+#define PIO_ABCDSR_P13 (0x1u << 13) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */\r
+#define PIO_ABCDSR_P14 (0x1u << 14) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */\r
+#define PIO_ABCDSR_P15 (0x1u << 15) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */\r
+#define PIO_ABCDSR_P16 (0x1u << 16) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */\r
+#define PIO_ABCDSR_P17 (0x1u << 17) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */\r
+#define PIO_ABCDSR_P18 (0x1u << 18) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */\r
+#define PIO_ABCDSR_P19 (0x1u << 19) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */\r
+#define PIO_ABCDSR_P20 (0x1u << 20) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */\r
+#define PIO_ABCDSR_P21 (0x1u << 21) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */\r
+#define PIO_ABCDSR_P22 (0x1u << 22) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */\r
+#define PIO_ABCDSR_P23 (0x1u << 23) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */\r
+#define PIO_ABCDSR_P24 (0x1u << 24) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */\r
+#define PIO_ABCDSR_P25 (0x1u << 25) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */\r
+#define PIO_ABCDSR_P26 (0x1u << 26) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */\r
+#define PIO_ABCDSR_P27 (0x1u << 27) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */\r
+#define PIO_ABCDSR_P28 (0x1u << 28) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */\r
+#define PIO_ABCDSR_P29 (0x1u << 29) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */\r
+#define PIO_ABCDSR_P30 (0x1u << 30) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */\r
+#define PIO_ABCDSR_P31 (0x1u << 31) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */\r
+/* -------- PIO_IFSCDR : (PIO Offset: 0x0080) Input Filter Slow Clock Disable Register -------- */\r
+#define PIO_IFSCDR_P0 (0x1u << 0) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */\r
+#define PIO_IFSCDR_P1 (0x1u << 1) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */\r
+#define PIO_IFSCDR_P2 (0x1u << 2) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */\r
+#define PIO_IFSCDR_P3 (0x1u << 3) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */\r
+#define PIO_IFSCDR_P4 (0x1u << 4) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */\r
+#define PIO_IFSCDR_P5 (0x1u << 5) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */\r
+#define PIO_IFSCDR_P6 (0x1u << 6) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */\r
+#define PIO_IFSCDR_P7 (0x1u << 7) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */\r
+#define PIO_IFSCDR_P8 (0x1u << 8) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */\r
+#define PIO_IFSCDR_P9 (0x1u << 9) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */\r
+#define PIO_IFSCDR_P10 (0x1u << 10) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */\r
+#define PIO_IFSCDR_P11 (0x1u << 11) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */\r
+#define PIO_IFSCDR_P12 (0x1u << 12) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */\r
+#define PIO_IFSCDR_P13 (0x1u << 13) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */\r
+#define PIO_IFSCDR_P14 (0x1u << 14) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */\r
+#define PIO_IFSCDR_P15 (0x1u << 15) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */\r
+#define PIO_IFSCDR_P16 (0x1u << 16) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */\r
+#define PIO_IFSCDR_P17 (0x1u << 17) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */\r
+#define PIO_IFSCDR_P18 (0x1u << 18) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */\r
+#define PIO_IFSCDR_P19 (0x1u << 19) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */\r
+#define PIO_IFSCDR_P20 (0x1u << 20) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */\r
+#define PIO_IFSCDR_P21 (0x1u << 21) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */\r
+#define PIO_IFSCDR_P22 (0x1u << 22) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */\r
+#define PIO_IFSCDR_P23 (0x1u << 23) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */\r
+#define PIO_IFSCDR_P24 (0x1u << 24) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */\r
+#define PIO_IFSCDR_P25 (0x1u << 25) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */\r
+#define PIO_IFSCDR_P26 (0x1u << 26) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */\r
+#define PIO_IFSCDR_P27 (0x1u << 27) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */\r
+#define PIO_IFSCDR_P28 (0x1u << 28) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */\r
+#define PIO_IFSCDR_P29 (0x1u << 29) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */\r
+#define PIO_IFSCDR_P30 (0x1u << 30) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */\r
+#define PIO_IFSCDR_P31 (0x1u << 31) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */\r
+/* -------- PIO_IFSCER : (PIO Offset: 0x0084) Input Filter Slow Clock Enable Register -------- */\r
+#define PIO_IFSCER_P0 (0x1u << 0) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */\r
+#define PIO_IFSCER_P1 (0x1u << 1) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */\r
+#define PIO_IFSCER_P2 (0x1u << 2) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */\r
+#define PIO_IFSCER_P3 (0x1u << 3) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */\r
+#define PIO_IFSCER_P4 (0x1u << 4) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */\r
+#define PIO_IFSCER_P5 (0x1u << 5) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */\r
+#define PIO_IFSCER_P6 (0x1u << 6) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */\r
+#define PIO_IFSCER_P7 (0x1u << 7) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */\r
+#define PIO_IFSCER_P8 (0x1u << 8) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */\r
+#define PIO_IFSCER_P9 (0x1u << 9) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */\r
+#define PIO_IFSCER_P10 (0x1u << 10) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */\r
+#define PIO_IFSCER_P11 (0x1u << 11) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */\r
+#define PIO_IFSCER_P12 (0x1u << 12) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */\r
+#define PIO_IFSCER_P13 (0x1u << 13) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */\r
+#define PIO_IFSCER_P14 (0x1u << 14) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */\r
+#define PIO_IFSCER_P15 (0x1u << 15) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */\r
+#define PIO_IFSCER_P16 (0x1u << 16) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */\r
+#define PIO_IFSCER_P17 (0x1u << 17) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */\r
+#define PIO_IFSCER_P18 (0x1u << 18) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */\r
+#define PIO_IFSCER_P19 (0x1u << 19) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */\r
+#define PIO_IFSCER_P20 (0x1u << 20) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */\r
+#define PIO_IFSCER_P21 (0x1u << 21) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */\r
+#define PIO_IFSCER_P22 (0x1u << 22) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */\r
+#define PIO_IFSCER_P23 (0x1u << 23) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */\r
+#define PIO_IFSCER_P24 (0x1u << 24) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */\r
+#define PIO_IFSCER_P25 (0x1u << 25) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */\r
+#define PIO_IFSCER_P26 (0x1u << 26) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */\r
+#define PIO_IFSCER_P27 (0x1u << 27) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */\r
+#define PIO_IFSCER_P28 (0x1u << 28) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */\r
+#define PIO_IFSCER_P29 (0x1u << 29) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */\r
+#define PIO_IFSCER_P30 (0x1u << 30) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */\r
+#define PIO_IFSCER_P31 (0x1u << 31) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */\r
+/* -------- PIO_IFSCSR : (PIO Offset: 0x0088) Input Filter Slow Clock Status Register -------- */\r
+#define PIO_IFSCSR_P0 (0x1u << 0) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P1 (0x1u << 1) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P2 (0x1u << 2) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P3 (0x1u << 3) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P4 (0x1u << 4) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P5 (0x1u << 5) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P6 (0x1u << 6) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P7 (0x1u << 7) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P8 (0x1u << 8) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P9 (0x1u << 9) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P10 (0x1u << 10) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P11 (0x1u << 11) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P12 (0x1u << 12) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P13 (0x1u << 13) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P14 (0x1u << 14) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P15 (0x1u << 15) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P16 (0x1u << 16) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P17 (0x1u << 17) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P18 (0x1u << 18) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P19 (0x1u << 19) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P20 (0x1u << 20) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P21 (0x1u << 21) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P22 (0x1u << 22) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P23 (0x1u << 23) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P24 (0x1u << 24) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P25 (0x1u << 25) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P26 (0x1u << 26) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P27 (0x1u << 27) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P28 (0x1u << 28) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P29 (0x1u << 29) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P30 (0x1u << 30) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P31 (0x1u << 31) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+/* -------- PIO_SCDR : (PIO Offset: 0x008C) Slow Clock Divider Debouncing Register -------- */\r
+#define PIO_SCDR_DIV_Pos 0\r
+#define PIO_SCDR_DIV_Msk (0x3fffu << PIO_SCDR_DIV_Pos) /**< \brief (PIO_SCDR) */\r
+#define PIO_SCDR_DIV(value) ((PIO_SCDR_DIV_Msk & ((value) << PIO_SCDR_DIV_Pos)))\r
+/* -------- PIO_PPDDR : (PIO Offset: 0x0090) Pad Pull-down Disable Register -------- */\r
+#define PIO_PPDDR_P0 (0x1u << 0) /**< \brief (PIO_PPDDR) Pull Down Disable. */\r
+#define PIO_PPDDR_P1 (0x1u << 1) /**< \brief (PIO_PPDDR) Pull Down Disable. */\r
+#define PIO_PPDDR_P2 (0x1u << 2) /**< \brief (PIO_PPDDR) Pull Down Disable. */\r
+#define PIO_PPDDR_P3 (0x1u << 3) /**< \brief (PIO_PPDDR) Pull Down Disable. */\r
+#define PIO_PPDDR_P4 (0x1u << 4) /**< \brief (PIO_PPDDR) Pull Down Disable. */\r
+#define PIO_PPDDR_P5 (0x1u << 5) /**< \brief (PIO_PPDDR) Pull Down Disable. */\r
+#define PIO_PPDDR_P6 (0x1u << 6) /**< \brief (PIO_PPDDR) Pull Down Disable. */\r
+#define PIO_PPDDR_P7 (0x1u << 7) /**< \brief (PIO_PPDDR) Pull Down Disable. */\r
+#define PIO_PPDDR_P8 (0x1u << 8) /**< \brief (PIO_PPDDR) Pull Down Disable. */\r
+#define PIO_PPDDR_P9 (0x1u << 9) /**< \brief (PIO_PPDDR) Pull Down Disable. */\r
+#define PIO_PPDDR_P10 (0x1u << 10) /**< \brief (PIO_PPDDR) Pull Down Disable. */\r
+#define PIO_PPDDR_P11 (0x1u << 11) /**< \brief (PIO_PPDDR) Pull Down Disable. */\r
+#define PIO_PPDDR_P12 (0x1u << 12) /**< \brief (PIO_PPDDR) Pull Down Disable. */\r
+#define PIO_PPDDR_P13 (0x1u << 13) /**< \brief (PIO_PPDDR) Pull Down Disable. */\r
+#define PIO_PPDDR_P14 (0x1u << 14) /**< \brief (PIO_PPDDR) Pull Down Disable. */\r
+#define PIO_PPDDR_P15 (0x1u << 15) /**< \brief (PIO_PPDDR) Pull Down Disable. */\r
+#define PIO_PPDDR_P16 (0x1u << 16) /**< \brief (PIO_PPDDR) Pull Down Disable. */\r
+#define PIO_PPDDR_P17 (0x1u << 17) /**< \brief (PIO_PPDDR) Pull Down Disable. */\r
+#define PIO_PPDDR_P18 (0x1u << 18) /**< \brief (PIO_PPDDR) Pull Down Disable. */\r
+#define PIO_PPDDR_P19 (0x1u << 19) /**< \brief (PIO_PPDDR) Pull Down Disable. */\r
+#define PIO_PPDDR_P20 (0x1u << 20) /**< \brief (PIO_PPDDR) Pull Down Disable. */\r
+#define PIO_PPDDR_P21 (0x1u << 21) /**< \brief (PIO_PPDDR) Pull Down Disable. */\r
+#define PIO_PPDDR_P22 (0x1u << 22) /**< \brief (PIO_PPDDR) Pull Down Disable. */\r
+#define PIO_PPDDR_P23 (0x1u << 23) /**< \brief (PIO_PPDDR) Pull Down Disable. */\r
+#define PIO_PPDDR_P24 (0x1u << 24) /**< \brief (PIO_PPDDR) Pull Down Disable. */\r
+#define PIO_PPDDR_P25 (0x1u << 25) /**< \brief (PIO_PPDDR) Pull Down Disable. */\r
+#define PIO_PPDDR_P26 (0x1u << 26) /**< \brief (PIO_PPDDR) Pull Down Disable. */\r
+#define PIO_PPDDR_P27 (0x1u << 27) /**< \brief (PIO_PPDDR) Pull Down Disable. */\r
+#define PIO_PPDDR_P28 (0x1u << 28) /**< \brief (PIO_PPDDR) Pull Down Disable. */\r
+#define PIO_PPDDR_P29 (0x1u << 29) /**< \brief (PIO_PPDDR) Pull Down Disable. */\r
+#define PIO_PPDDR_P30 (0x1u << 30) /**< \brief (PIO_PPDDR) Pull Down Disable. */\r
+#define PIO_PPDDR_P31 (0x1u << 31) /**< \brief (PIO_PPDDR) Pull Down Disable. */\r
+/* -------- PIO_PPDER : (PIO Offset: 0x0094) Pad Pull-down Enable Register -------- */\r
+#define PIO_PPDER_P0 (0x1u << 0) /**< \brief (PIO_PPDER) Pull Down Enable. */\r
+#define PIO_PPDER_P1 (0x1u << 1) /**< \brief (PIO_PPDER) Pull Down Enable. */\r
+#define PIO_PPDER_P2 (0x1u << 2) /**< \brief (PIO_PPDER) Pull Down Enable. */\r
+#define PIO_PPDER_P3 (0x1u << 3) /**< \brief (PIO_PPDER) Pull Down Enable. */\r
+#define PIO_PPDER_P4 (0x1u << 4) /**< \brief (PIO_PPDER) Pull Down Enable. */\r
+#define PIO_PPDER_P5 (0x1u << 5) /**< \brief (PIO_PPDER) Pull Down Enable. */\r
+#define PIO_PPDER_P6 (0x1u << 6) /**< \brief (PIO_PPDER) Pull Down Enable. */\r
+#define PIO_PPDER_P7 (0x1u << 7) /**< \brief (PIO_PPDER) Pull Down Enable. */\r
+#define PIO_PPDER_P8 (0x1u << 8) /**< \brief (PIO_PPDER) Pull Down Enable. */\r
+#define PIO_PPDER_P9 (0x1u << 9) /**< \brief (PIO_PPDER) Pull Down Enable. */\r
+#define PIO_PPDER_P10 (0x1u << 10) /**< \brief (PIO_PPDER) Pull Down Enable. */\r
+#define PIO_PPDER_P11 (0x1u << 11) /**< \brief (PIO_PPDER) Pull Down Enable. */\r
+#define PIO_PPDER_P12 (0x1u << 12) /**< \brief (PIO_PPDER) Pull Down Enable. */\r
+#define PIO_PPDER_P13 (0x1u << 13) /**< \brief (PIO_PPDER) Pull Down Enable. */\r
+#define PIO_PPDER_P14 (0x1u << 14) /**< \brief (PIO_PPDER) Pull Down Enable. */\r
+#define PIO_PPDER_P15 (0x1u << 15) /**< \brief (PIO_PPDER) Pull Down Enable. */\r
+#define PIO_PPDER_P16 (0x1u << 16) /**< \brief (PIO_PPDER) Pull Down Enable. */\r
+#define PIO_PPDER_P17 (0x1u << 17) /**< \brief (PIO_PPDER) Pull Down Enable. */\r
+#define PIO_PPDER_P18 (0x1u << 18) /**< \brief (PIO_PPDER) Pull Down Enable. */\r
+#define PIO_PPDER_P19 (0x1u << 19) /**< \brief (PIO_PPDER) Pull Down Enable. */\r
+#define PIO_PPDER_P20 (0x1u << 20) /**< \brief (PIO_PPDER) Pull Down Enable. */\r
+#define PIO_PPDER_P21 (0x1u << 21) /**< \brief (PIO_PPDER) Pull Down Enable. */\r
+#define PIO_PPDER_P22 (0x1u << 22) /**< \brief (PIO_PPDER) Pull Down Enable. */\r
+#define PIO_PPDER_P23 (0x1u << 23) /**< \brief (PIO_PPDER) Pull Down Enable. */\r
+#define PIO_PPDER_P24 (0x1u << 24) /**< \brief (PIO_PPDER) Pull Down Enable. */\r
+#define PIO_PPDER_P25 (0x1u << 25) /**< \brief (PIO_PPDER) Pull Down Enable. */\r
+#define PIO_PPDER_P26 (0x1u << 26) /**< \brief (PIO_PPDER) Pull Down Enable. */\r
+#define PIO_PPDER_P27 (0x1u << 27) /**< \brief (PIO_PPDER) Pull Down Enable. */\r
+#define PIO_PPDER_P28 (0x1u << 28) /**< \brief (PIO_PPDER) Pull Down Enable. */\r
+#define PIO_PPDER_P29 (0x1u << 29) /**< \brief (PIO_PPDER) Pull Down Enable. */\r
+#define PIO_PPDER_P30 (0x1u << 30) /**< \brief (PIO_PPDER) Pull Down Enable. */\r
+#define PIO_PPDER_P31 (0x1u << 31) /**< \brief (PIO_PPDER) Pull Down Enable. */\r
+/* -------- PIO_PPDSR : (PIO Offset: 0x0098) Pad Pull-down Status Register -------- */\r
+#define PIO_PPDSR_P0 (0x1u << 0) /**< \brief (PIO_PPDSR) Pull Down Status. */\r
+#define PIO_PPDSR_P1 (0x1u << 1) /**< \brief (PIO_PPDSR) Pull Down Status. */\r
+#define PIO_PPDSR_P2 (0x1u << 2) /**< \brief (PIO_PPDSR) Pull Down Status. */\r
+#define PIO_PPDSR_P3 (0x1u << 3) /**< \brief (PIO_PPDSR) Pull Down Status. */\r
+#define PIO_PPDSR_P4 (0x1u << 4) /**< \brief (PIO_PPDSR) Pull Down Status. */\r
+#define PIO_PPDSR_P5 (0x1u << 5) /**< \brief (PIO_PPDSR) Pull Down Status. */\r
+#define PIO_PPDSR_P6 (0x1u << 6) /**< \brief (PIO_PPDSR) Pull Down Status. */\r
+#define PIO_PPDSR_P7 (0x1u << 7) /**< \brief (PIO_PPDSR) Pull Down Status. */\r
+#define PIO_PPDSR_P8 (0x1u << 8) /**< \brief (PIO_PPDSR) Pull Down Status. */\r
+#define PIO_PPDSR_P9 (0x1u << 9) /**< \brief (PIO_PPDSR) Pull Down Status. */\r
+#define PIO_PPDSR_P10 (0x1u << 10) /**< \brief (PIO_PPDSR) Pull Down Status. */\r
+#define PIO_PPDSR_P11 (0x1u << 11) /**< \brief (PIO_PPDSR) Pull Down Status. */\r
+#define PIO_PPDSR_P12 (0x1u << 12) /**< \brief (PIO_PPDSR) Pull Down Status. */\r
+#define PIO_PPDSR_P13 (0x1u << 13) /**< \brief (PIO_PPDSR) Pull Down Status. */\r
+#define PIO_PPDSR_P14 (0x1u << 14) /**< \brief (PIO_PPDSR) Pull Down Status. */\r
+#define PIO_PPDSR_P15 (0x1u << 15) /**< \brief (PIO_PPDSR) Pull Down Status. */\r
+#define PIO_PPDSR_P16 (0x1u << 16) /**< \brief (PIO_PPDSR) Pull Down Status. */\r
+#define PIO_PPDSR_P17 (0x1u << 17) /**< \brief (PIO_PPDSR) Pull Down Status. */\r
+#define PIO_PPDSR_P18 (0x1u << 18) /**< \brief (PIO_PPDSR) Pull Down Status. */\r
+#define PIO_PPDSR_P19 (0x1u << 19) /**< \brief (PIO_PPDSR) Pull Down Status. */\r
+#define PIO_PPDSR_P20 (0x1u << 20) /**< \brief (PIO_PPDSR) Pull Down Status. */\r
+#define PIO_PPDSR_P21 (0x1u << 21) /**< \brief (PIO_PPDSR) Pull Down Status. */\r
+#define PIO_PPDSR_P22 (0x1u << 22) /**< \brief (PIO_PPDSR) Pull Down Status. */\r
+#define PIO_PPDSR_P23 (0x1u << 23) /**< \brief (PIO_PPDSR) Pull Down Status. */\r
+#define PIO_PPDSR_P24 (0x1u << 24) /**< \brief (PIO_PPDSR) Pull Down Status. */\r
+#define PIO_PPDSR_P25 (0x1u << 25) /**< \brief (PIO_PPDSR) Pull Down Status. */\r
+#define PIO_PPDSR_P26 (0x1u << 26) /**< \brief (PIO_PPDSR) Pull Down Status. */\r
+#define PIO_PPDSR_P27 (0x1u << 27) /**< \brief (PIO_PPDSR) Pull Down Status. */\r
+#define PIO_PPDSR_P28 (0x1u << 28) /**< \brief (PIO_PPDSR) Pull Down Status. */\r
+#define PIO_PPDSR_P29 (0x1u << 29) /**< \brief (PIO_PPDSR) Pull Down Status. */\r
+#define PIO_PPDSR_P30 (0x1u << 30) /**< \brief (PIO_PPDSR) Pull Down Status. */\r
+#define PIO_PPDSR_P31 (0x1u << 31) /**< \brief (PIO_PPDSR) Pull Down Status. */\r
+/* -------- PIO_OWER : (PIO Offset: 0x00A0) Output Write Enable -------- */\r
+#define PIO_OWER_P0 (0x1u << 0) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P1 (0x1u << 1) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P2 (0x1u << 2) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P3 (0x1u << 3) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P4 (0x1u << 4) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P5 (0x1u << 5) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P6 (0x1u << 6) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P7 (0x1u << 7) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P8 (0x1u << 8) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P9 (0x1u << 9) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P10 (0x1u << 10) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P11 (0x1u << 11) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P12 (0x1u << 12) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P13 (0x1u << 13) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P14 (0x1u << 14) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P15 (0x1u << 15) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P16 (0x1u << 16) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P17 (0x1u << 17) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P18 (0x1u << 18) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P19 (0x1u << 19) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P20 (0x1u << 20) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P21 (0x1u << 21) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P22 (0x1u << 22) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P23 (0x1u << 23) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P24 (0x1u << 24) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P25 (0x1u << 25) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P26 (0x1u << 26) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P27 (0x1u << 27) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P28 (0x1u << 28) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P29 (0x1u << 29) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P30 (0x1u << 30) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P31 (0x1u << 31) /**< \brief (PIO_OWER) Output Write Enable. */\r
+/* -------- PIO_OWDR : (PIO Offset: 0x00A4) Output Write Disable -------- */\r
+#define PIO_OWDR_P0 (0x1u << 0) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P1 (0x1u << 1) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P2 (0x1u << 2) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P3 (0x1u << 3) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P4 (0x1u << 4) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P5 (0x1u << 5) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P6 (0x1u << 6) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P7 (0x1u << 7) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P8 (0x1u << 8) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P9 (0x1u << 9) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P10 (0x1u << 10) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P11 (0x1u << 11) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P12 (0x1u << 12) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P13 (0x1u << 13) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P14 (0x1u << 14) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P15 (0x1u << 15) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P16 (0x1u << 16) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P17 (0x1u << 17) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P18 (0x1u << 18) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P19 (0x1u << 19) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P20 (0x1u << 20) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P21 (0x1u << 21) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P22 (0x1u << 22) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P23 (0x1u << 23) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P24 (0x1u << 24) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P25 (0x1u << 25) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P26 (0x1u << 26) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P27 (0x1u << 27) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P28 (0x1u << 28) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P29 (0x1u << 29) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P30 (0x1u << 30) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P31 (0x1u << 31) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+/* -------- PIO_OWSR : (PIO Offset: 0x00A8) Output Write Status Register -------- */\r
+#define PIO_OWSR_P0 (0x1u << 0) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P1 (0x1u << 1) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P2 (0x1u << 2) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P3 (0x1u << 3) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P4 (0x1u << 4) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P5 (0x1u << 5) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P6 (0x1u << 6) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P7 (0x1u << 7) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P8 (0x1u << 8) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P9 (0x1u << 9) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P10 (0x1u << 10) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P11 (0x1u << 11) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P12 (0x1u << 12) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P13 (0x1u << 13) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P14 (0x1u << 14) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P15 (0x1u << 15) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P16 (0x1u << 16) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P17 (0x1u << 17) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P18 (0x1u << 18) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P19 (0x1u << 19) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P20 (0x1u << 20) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P21 (0x1u << 21) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P22 (0x1u << 22) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P23 (0x1u << 23) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P24 (0x1u << 24) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P25 (0x1u << 25) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P26 (0x1u << 26) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P27 (0x1u << 27) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P28 (0x1u << 28) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P29 (0x1u << 29) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P30 (0x1u << 30) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P31 (0x1u << 31) /**< \brief (PIO_OWSR) Output Write Status. */\r
+/* -------- PIO_AIMER : (PIO Offset: 0x00B0) Additional Interrupt Modes Enable Register -------- */\r
+#define PIO_AIMER_P0 (0x1u << 0) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P1 (0x1u << 1) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P2 (0x1u << 2) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P3 (0x1u << 3) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P4 (0x1u << 4) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P5 (0x1u << 5) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P6 (0x1u << 6) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P7 (0x1u << 7) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P8 (0x1u << 8) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P9 (0x1u << 9) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P10 (0x1u << 10) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P11 (0x1u << 11) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P12 (0x1u << 12) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P13 (0x1u << 13) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P14 (0x1u << 14) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P15 (0x1u << 15) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P16 (0x1u << 16) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P17 (0x1u << 17) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P18 (0x1u << 18) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P19 (0x1u << 19) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P20 (0x1u << 20) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P21 (0x1u << 21) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P22 (0x1u << 22) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P23 (0x1u << 23) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P24 (0x1u << 24) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P25 (0x1u << 25) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P26 (0x1u << 26) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P27 (0x1u << 27) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P28 (0x1u << 28) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P29 (0x1u << 29) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P30 (0x1u << 30) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P31 (0x1u << 31) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+/* -------- PIO_AIMDR : (PIO Offset: 0x00B4) Additional Interrupt Modes Disables Register -------- */\r
+#define PIO_AIMDR_P0 (0x1u << 0) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P1 (0x1u << 1) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P2 (0x1u << 2) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P3 (0x1u << 3) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P4 (0x1u << 4) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P5 (0x1u << 5) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P6 (0x1u << 6) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P7 (0x1u << 7) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P8 (0x1u << 8) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P9 (0x1u << 9) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P10 (0x1u << 10) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P11 (0x1u << 11) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P12 (0x1u << 12) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P13 (0x1u << 13) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P14 (0x1u << 14) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P15 (0x1u << 15) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P16 (0x1u << 16) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P17 (0x1u << 17) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P18 (0x1u << 18) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P19 (0x1u << 19) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P20 (0x1u << 20) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P21 (0x1u << 21) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P22 (0x1u << 22) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P23 (0x1u << 23) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P24 (0x1u << 24) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P25 (0x1u << 25) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P26 (0x1u << 26) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P27 (0x1u << 27) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P28 (0x1u << 28) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P29 (0x1u << 29) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P30 (0x1u << 30) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P31 (0x1u << 31) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+/* -------- PIO_AIMMR : (PIO Offset: 0x00B8) Additional Interrupt Modes Mask Register -------- */\r
+#define PIO_AIMMR_P0 (0x1u << 0) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P1 (0x1u << 1) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P2 (0x1u << 2) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P3 (0x1u << 3) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P4 (0x1u << 4) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P5 (0x1u << 5) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P6 (0x1u << 6) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P7 (0x1u << 7) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P8 (0x1u << 8) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P9 (0x1u << 9) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P10 (0x1u << 10) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P11 (0x1u << 11) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P12 (0x1u << 12) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P13 (0x1u << 13) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P14 (0x1u << 14) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P15 (0x1u << 15) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P16 (0x1u << 16) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P17 (0x1u << 17) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P18 (0x1u << 18) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P19 (0x1u << 19) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P20 (0x1u << 20) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P21 (0x1u << 21) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P22 (0x1u << 22) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P23 (0x1u << 23) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P24 (0x1u << 24) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P25 (0x1u << 25) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P26 (0x1u << 26) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P27 (0x1u << 27) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P28 (0x1u << 28) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P29 (0x1u << 29) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P30 (0x1u << 30) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P31 (0x1u << 31) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+/* -------- PIO_ESR : (PIO Offset: 0x00C0) Edge Select Register -------- */\r
+#define PIO_ESR_P0 (0x1u << 0) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P1 (0x1u << 1) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P2 (0x1u << 2) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P3 (0x1u << 3) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P4 (0x1u << 4) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P5 (0x1u << 5) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P6 (0x1u << 6) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P7 (0x1u << 7) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P8 (0x1u << 8) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P9 (0x1u << 9) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P10 (0x1u << 10) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P11 (0x1u << 11) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P12 (0x1u << 12) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P13 (0x1u << 13) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P14 (0x1u << 14) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P15 (0x1u << 15) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P16 (0x1u << 16) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P17 (0x1u << 17) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P18 (0x1u << 18) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P19 (0x1u << 19) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P20 (0x1u << 20) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P21 (0x1u << 21) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P22 (0x1u << 22) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P23 (0x1u << 23) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P24 (0x1u << 24) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P25 (0x1u << 25) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P26 (0x1u << 26) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P27 (0x1u << 27) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P28 (0x1u << 28) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P29 (0x1u << 29) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P30 (0x1u << 30) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P31 (0x1u << 31) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+/* -------- PIO_LSR : (PIO Offset: 0x00C4) Level Select Register -------- */\r
+#define PIO_LSR_P0 (0x1u << 0) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P1 (0x1u << 1) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P2 (0x1u << 2) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P3 (0x1u << 3) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P4 (0x1u << 4) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P5 (0x1u << 5) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P6 (0x1u << 6) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P7 (0x1u << 7) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P8 (0x1u << 8) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P9 (0x1u << 9) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P10 (0x1u << 10) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P11 (0x1u << 11) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P12 (0x1u << 12) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P13 (0x1u << 13) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P14 (0x1u << 14) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P15 (0x1u << 15) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P16 (0x1u << 16) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P17 (0x1u << 17) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P18 (0x1u << 18) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P19 (0x1u << 19) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P20 (0x1u << 20) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P21 (0x1u << 21) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P22 (0x1u << 22) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P23 (0x1u << 23) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P24 (0x1u << 24) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P25 (0x1u << 25) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P26 (0x1u << 26) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P27 (0x1u << 27) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P28 (0x1u << 28) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P29 (0x1u << 29) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P30 (0x1u << 30) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P31 (0x1u << 31) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+/* -------- PIO_ELSR : (PIO Offset: 0x00C8) Edge/Level Status Register -------- */\r
+#define PIO_ELSR_P0 (0x1u << 0) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P1 (0x1u << 1) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P2 (0x1u << 2) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P3 (0x1u << 3) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P4 (0x1u << 4) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P5 (0x1u << 5) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P6 (0x1u << 6) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P7 (0x1u << 7) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P8 (0x1u << 8) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P9 (0x1u << 9) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P10 (0x1u << 10) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P11 (0x1u << 11) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P12 (0x1u << 12) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P13 (0x1u << 13) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P14 (0x1u << 14) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P15 (0x1u << 15) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P16 (0x1u << 16) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P17 (0x1u << 17) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P18 (0x1u << 18) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P19 (0x1u << 19) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P20 (0x1u << 20) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P21 (0x1u << 21) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P22 (0x1u << 22) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P23 (0x1u << 23) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P24 (0x1u << 24) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P25 (0x1u << 25) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P26 (0x1u << 26) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P27 (0x1u << 27) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P28 (0x1u << 28) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P29 (0x1u << 29) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P30 (0x1u << 30) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P31 (0x1u << 31) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+/* -------- PIO_FELLSR : (PIO Offset: 0x00D0) Falling Edge/Low Level Select Register -------- */\r
+#define PIO_FELLSR_P0 (0x1u << 0) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P1 (0x1u << 1) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P2 (0x1u << 2) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P3 (0x1u << 3) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P4 (0x1u << 4) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P5 (0x1u << 5) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P6 (0x1u << 6) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P7 (0x1u << 7) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P8 (0x1u << 8) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P9 (0x1u << 9) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P10 (0x1u << 10) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P11 (0x1u << 11) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P12 (0x1u << 12) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P13 (0x1u << 13) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P14 (0x1u << 14) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P15 (0x1u << 15) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P16 (0x1u << 16) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P17 (0x1u << 17) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P18 (0x1u << 18) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P19 (0x1u << 19) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P20 (0x1u << 20) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P21 (0x1u << 21) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P22 (0x1u << 22) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P23 (0x1u << 23) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P24 (0x1u << 24) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P25 (0x1u << 25) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P26 (0x1u << 26) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P27 (0x1u << 27) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P28 (0x1u << 28) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P29 (0x1u << 29) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P30 (0x1u << 30) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P31 (0x1u << 31) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+/* -------- PIO_REHLSR : (PIO Offset: 0x00D4) Rising Edge/ High Level Select Register -------- */\r
+#define PIO_REHLSR_P0 (0x1u << 0) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P1 (0x1u << 1) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P2 (0x1u << 2) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P3 (0x1u << 3) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P4 (0x1u << 4) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P5 (0x1u << 5) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P6 (0x1u << 6) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P7 (0x1u << 7) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P8 (0x1u << 8) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P9 (0x1u << 9) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P10 (0x1u << 10) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P11 (0x1u << 11) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P12 (0x1u << 12) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P13 (0x1u << 13) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P14 (0x1u << 14) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P15 (0x1u << 15) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P16 (0x1u << 16) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P17 (0x1u << 17) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P18 (0x1u << 18) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P19 (0x1u << 19) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P20 (0x1u << 20) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P21 (0x1u << 21) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P22 (0x1u << 22) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P23 (0x1u << 23) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P24 (0x1u << 24) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P25 (0x1u << 25) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P26 (0x1u << 26) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P27 (0x1u << 27) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P28 (0x1u << 28) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P29 (0x1u << 29) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P30 (0x1u << 30) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P31 (0x1u << 31) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+/* -------- PIO_FRLHSR : (PIO Offset: 0x00D8) Fall/Rise - Low/High Status Register -------- */\r
+#define PIO_FRLHSR_P0 (0x1u << 0) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P1 (0x1u << 1) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P2 (0x1u << 2) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P3 (0x1u << 3) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P4 (0x1u << 4) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P5 (0x1u << 5) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P6 (0x1u << 6) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P7 (0x1u << 7) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P8 (0x1u << 8) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P9 (0x1u << 9) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P10 (0x1u << 10) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P11 (0x1u << 11) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P12 (0x1u << 12) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P13 (0x1u << 13) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P14 (0x1u << 14) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P15 (0x1u << 15) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P16 (0x1u << 16) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P17 (0x1u << 17) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P18 (0x1u << 18) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P19 (0x1u << 19) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P20 (0x1u << 20) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P21 (0x1u << 21) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P22 (0x1u << 22) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P23 (0x1u << 23) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P24 (0x1u << 24) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P25 (0x1u << 25) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P26 (0x1u << 26) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P27 (0x1u << 27) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P28 (0x1u << 28) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P29 (0x1u << 29) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P30 (0x1u << 30) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P31 (0x1u << 31) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+/* -------- PIO_LOCKSR : (PIO Offset: 0x00E0) Lock Status -------- */\r
+#define PIO_LOCKSR_P0 (0x1u << 0) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P1 (0x1u << 1) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P2 (0x1u << 2) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P3 (0x1u << 3) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P4 (0x1u << 4) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P5 (0x1u << 5) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P6 (0x1u << 6) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P7 (0x1u << 7) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P8 (0x1u << 8) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P9 (0x1u << 9) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P10 (0x1u << 10) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P11 (0x1u << 11) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P12 (0x1u << 12) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P13 (0x1u << 13) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P14 (0x1u << 14) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P15 (0x1u << 15) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P16 (0x1u << 16) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P17 (0x1u << 17) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P18 (0x1u << 18) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P19 (0x1u << 19) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P20 (0x1u << 20) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P21 (0x1u << 21) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P22 (0x1u << 22) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P23 (0x1u << 23) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P24 (0x1u << 24) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P25 (0x1u << 25) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P26 (0x1u << 26) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P27 (0x1u << 27) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P28 (0x1u << 28) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P29 (0x1u << 29) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P30 (0x1u << 30) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P31 (0x1u << 31) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+/* -------- PIO_WPMR : (PIO Offset: 0x00E4) Write Protect Mode Register -------- */\r
+#define PIO_WPMR_WPEN (0x1u << 0) /**< \brief (PIO_WPMR) Write Protect Enable */\r
+#define PIO_WPMR_WPKEY_Pos 8\r
+#define PIO_WPMR_WPKEY_Msk (0xffffffu << PIO_WPMR_WPKEY_Pos) /**< \brief (PIO_WPMR) Write Protect KEY */\r
+#define PIO_WPMR_WPKEY(value) ((PIO_WPMR_WPKEY_Msk & ((value) << PIO_WPMR_WPKEY_Pos)))\r
+/* -------- PIO_WPSR : (PIO Offset: 0x00E8) Write Protect Status Register -------- */\r
+#define PIO_WPSR_WPVS (0x1u << 0) /**< \brief (PIO_WPSR) Write Protect Violation Status */\r
+#define PIO_WPSR_WPVSRC_Pos 8\r
+#define PIO_WPSR_WPVSRC_Msk (0xffffu << PIO_WPSR_WPVSRC_Pos) /**< \brief (PIO_WPSR) Write Protect Violation Source */\r
+/* -------- PIO_SCHMITT : (PIO Offset: 0x0100) Schmitt Trigger Register -------- */\r
+#define PIO_SCHMITT_SCHMITT0 (0x1u << 0) /**< \brief (PIO_SCHMITT) */\r
+#define PIO_SCHMITT_SCHMITT1 (0x1u << 1) /**< \brief (PIO_SCHMITT) */\r
+#define PIO_SCHMITT_SCHMITT2 (0x1u << 2) /**< \brief (PIO_SCHMITT) */\r
+#define PIO_SCHMITT_SCHMITT3 (0x1u << 3) /**< \brief (PIO_SCHMITT) */\r
+#define PIO_SCHMITT_SCHMITT4 (0x1u << 4) /**< \brief (PIO_SCHMITT) */\r
+#define PIO_SCHMITT_SCHMITT5 (0x1u << 5) /**< \brief (PIO_SCHMITT) */\r
+#define PIO_SCHMITT_SCHMITT6 (0x1u << 6) /**< \brief (PIO_SCHMITT) */\r
+#define PIO_SCHMITT_SCHMITT7 (0x1u << 7) /**< \brief (PIO_SCHMITT) */\r
+#define PIO_SCHMITT_SCHMITT8 (0x1u << 8) /**< \brief (PIO_SCHMITT) */\r
+#define PIO_SCHMITT_SCHMITT9 (0x1u << 9) /**< \brief (PIO_SCHMITT) */\r
+#define PIO_SCHMITT_SCHMITT10 (0x1u << 10) /**< \brief (PIO_SCHMITT) */\r
+#define PIO_SCHMITT_SCHMITT11 (0x1u << 11) /**< \brief (PIO_SCHMITT) */\r
+#define PIO_SCHMITT_SCHMITT12 (0x1u << 12) /**< \brief (PIO_SCHMITT) */\r
+#define PIO_SCHMITT_SCHMITT13 (0x1u << 13) /**< \brief (PIO_SCHMITT) */\r
+#define PIO_SCHMITT_SCHMITT14 (0x1u << 14) /**< \brief (PIO_SCHMITT) */\r
+#define PIO_SCHMITT_SCHMITT15 (0x1u << 15) /**< \brief (PIO_SCHMITT) */\r
+#define PIO_SCHMITT_SCHMITT16 (0x1u << 16) /**< \brief (PIO_SCHMITT) */\r
+#define PIO_SCHMITT_SCHMITT17 (0x1u << 17) /**< \brief (PIO_SCHMITT) */\r
+#define PIO_SCHMITT_SCHMITT18 (0x1u << 18) /**< \brief (PIO_SCHMITT) */\r
+#define PIO_SCHMITT_SCHMITT19 (0x1u << 19) /**< \brief (PIO_SCHMITT) */\r
+#define PIO_SCHMITT_SCHMITT20 (0x1u << 20) /**< \brief (PIO_SCHMITT) */\r
+#define PIO_SCHMITT_SCHMITT21 (0x1u << 21) /**< \brief (PIO_SCHMITT) */\r
+#define PIO_SCHMITT_SCHMITT22 (0x1u << 22) /**< \brief (PIO_SCHMITT) */\r
+#define PIO_SCHMITT_SCHMITT23 (0x1u << 23) /**< \brief (PIO_SCHMITT) */\r
+#define PIO_SCHMITT_SCHMITT24 (0x1u << 24) /**< \brief (PIO_SCHMITT) */\r
+#define PIO_SCHMITT_SCHMITT25 (0x1u << 25) /**< \brief (PIO_SCHMITT) */\r
+#define PIO_SCHMITT_SCHMITT26 (0x1u << 26) /**< \brief (PIO_SCHMITT) */\r
+#define PIO_SCHMITT_SCHMITT27 (0x1u << 27) /**< \brief (PIO_SCHMITT) */\r
+#define PIO_SCHMITT_SCHMITT28 (0x1u << 28) /**< \brief (PIO_SCHMITT) */\r
+#define PIO_SCHMITT_SCHMITT29 (0x1u << 29) /**< \brief (PIO_SCHMITT) */\r
+#define PIO_SCHMITT_SCHMITT30 (0x1u << 30) /**< \brief (PIO_SCHMITT) */\r
+#define PIO_SCHMITT_SCHMITT31 (0x1u << 31) /**< \brief (PIO_SCHMITT) */\r
+/* -------- PIO_DELAYR : (PIO Offset: 0x0110) IO Delay Register -------- */\r
+#define PIO_DELAYR_Delay0_Pos 0\r
+#define PIO_DELAYR_Delay0_Msk (0xfu << PIO_DELAYR_Delay0_Pos) /**< \brief (PIO_DELAYR) */\r
+#define PIO_DELAYR_Delay0(value) ((PIO_DELAYR_Delay0_Msk & ((value) << PIO_DELAYR_Delay0_Pos)))\r
+#define PIO_DELAYR_Delay1_Pos 4\r
+#define PIO_DELAYR_Delay1_Msk (0xfu << PIO_DELAYR_Delay1_Pos) /**< \brief (PIO_DELAYR) */\r
+#define PIO_DELAYR_Delay1(value) ((PIO_DELAYR_Delay1_Msk & ((value) << PIO_DELAYR_Delay1_Pos)))\r
+#define PIO_DELAYR_Delay2_Pos 8\r
+#define PIO_DELAYR_Delay2_Msk (0xfu << PIO_DELAYR_Delay2_Pos) /**< \brief (PIO_DELAYR) */\r
+#define PIO_DELAYR_Delay2(value) ((PIO_DELAYR_Delay2_Msk & ((value) << PIO_DELAYR_Delay2_Pos)))\r
+#define PIO_DELAYR_Delay3_Pos 12\r
+#define PIO_DELAYR_Delay3_Msk (0xfu << PIO_DELAYR_Delay3_Pos) /**< \brief (PIO_DELAYR) */\r
+#define PIO_DELAYR_Delay3(value) ((PIO_DELAYR_Delay3_Msk & ((value) << PIO_DELAYR_Delay3_Pos)))\r
+#define PIO_DELAYR_Delay4_Pos 16\r
+#define PIO_DELAYR_Delay4_Msk (0xfu << PIO_DELAYR_Delay4_Pos) /**< \brief (PIO_DELAYR) */\r
+#define PIO_DELAYR_Delay4(value) ((PIO_DELAYR_Delay4_Msk & ((value) << PIO_DELAYR_Delay4_Pos)))\r
+#define PIO_DELAYR_Delay5_Pos 20\r
+#define PIO_DELAYR_Delay5_Msk (0xfu << PIO_DELAYR_Delay5_Pos) /**< \brief (PIO_DELAYR) */\r
+#define PIO_DELAYR_Delay5(value) ((PIO_DELAYR_Delay5_Msk & ((value) << PIO_DELAYR_Delay5_Pos)))\r
+#define PIO_DELAYR_Delay6_Pos 24\r
+#define PIO_DELAYR_Delay6_Msk (0xfu << PIO_DELAYR_Delay6_Pos) /**< \brief (PIO_DELAYR) */\r
+#define PIO_DELAYR_Delay6(value) ((PIO_DELAYR_Delay6_Msk & ((value) << PIO_DELAYR_Delay6_Pos)))\r
+#define PIO_DELAYR_Delay7_Pos 28\r
+#define PIO_DELAYR_Delay7_Msk (0xfu << PIO_DELAYR_Delay7_Pos) /**< \brief (PIO_DELAYR) */\r
+#define PIO_DELAYR_Delay7(value) ((PIO_DELAYR_Delay7_Msk & ((value) << PIO_DELAYR_Delay7_Pos)))\r
+/* -------- PIO_PCMR : (PIO Offset: 0x150) Parallel Capture Mode Register -------- */\r
+#define PIO_PCMR_PCEN (0x1u << 0) /**< \brief (PIO_PCMR) Parallel Capture Mode Enable */\r
+#define PIO_PCMR_DSIZE_Pos 4\r
+#define PIO_PCMR_DSIZE_Msk (0x3u << PIO_PCMR_DSIZE_Pos) /**< \brief (PIO_PCMR) Parallel Capture Mode Data Size */\r
+#define PIO_PCMR_DSIZE_BYTE (0x0u << 4) /**< \brief (PIO_PCMR) The reception data in the PIO_PCRHR register is a BYTE (8-bit) */\r
+#define PIO_PCMR_DSIZE_HALFWORD (0x1u << 4) /**< \brief (PIO_PCMR) The reception data in the PIO_PCRHR register is a HALF-WORD (16-bit) */\r
+#define PIO_PCMR_DSIZE_WORD (0x2u << 4) /**< \brief (PIO_PCMR) The reception data in the PIO_PCRHR register is a WORD (32-bit) */\r
+#define PIO_PCMR_ALWYS (0x1u << 9) /**< \brief (PIO_PCMR) Parallel Capture Mode Always Sampling */\r
+#define PIO_PCMR_HALFS (0x1u << 10) /**< \brief (PIO_PCMR) Parallel Capture Mode Half Sampling */\r
+#define PIO_PCMR_FRSTS (0x1u << 11) /**< \brief (PIO_PCMR) Parallel Capture Mode First Sample */\r
+/* -------- PIO_PCIER : (PIO Offset: 0x154) Parallel Capture Interrupt Enable Register -------- */\r
+#define PIO_PCIER_DRDY (0x1u << 0) /**< \brief (PIO_PCIER) Parallel Capture Mode Data Ready Interrupt Enable */\r
+#define PIO_PCIER_OVRE (0x1u << 1) /**< \brief (PIO_PCIER) Parallel Capture Mode Overrun Error Interrupt Enable */\r
+#define PIO_PCIER_ENDRX (0x1u << 2) /**< \brief (PIO_PCIER) End of Reception Transfer Interrupt Enable */\r
+#define PIO_PCIER_RXBUFF (0x1u << 3) /**< \brief (PIO_PCIER) Reception Buffer Full Interrupt Enable */\r
+/* -------- PIO_PCIDR : (PIO Offset: 0x158) Parallel Capture Interrupt Disable Register -------- */\r
+#define PIO_PCIDR_DRDY (0x1u << 0) /**< \brief (PIO_PCIDR) Parallel Capture Mode Data Ready Interrupt Disable */\r
+#define PIO_PCIDR_OVRE (0x1u << 1) /**< \brief (PIO_PCIDR) Parallel Capture Mode Overrun Error Interrupt Disable */\r
+#define PIO_PCIDR_ENDRX (0x1u << 2) /**< \brief (PIO_PCIDR) End of Reception Transfer Interrupt Disable */\r
+#define PIO_PCIDR_RXBUFF (0x1u << 3) /**< \brief (PIO_PCIDR) Reception Buffer Full Interrupt Disable */\r
+/* -------- PIO_PCIMR : (PIO Offset: 0x15C) Parallel Capture Interrupt Mask Register -------- */\r
+#define PIO_PCIMR_DRDY (0x1u << 0) /**< \brief (PIO_PCIMR) Parallel Capture Mode Data Ready Interrupt Mask */\r
+#define PIO_PCIMR_OVRE (0x1u << 1) /**< \brief (PIO_PCIMR) Parallel Capture Mode Overrun Error Interrupt Mask */\r
+#define PIO_PCIMR_ENDRX (0x1u << 2) /**< \brief (PIO_PCIMR) End of Reception Transfer Interrupt Mask */\r
+#define PIO_PCIMR_RXBUFF (0x1u << 3) /**< \brief (PIO_PCIMR) Reception Buffer Full Interrupt Mask */\r
+/* -------- PIO_PCISR : (PIO Offset: 0x160) Parallel Capture Interrupt Status Register -------- */\r
+#define PIO_PCISR_DRDY (0x1u << 0) /**< \brief (PIO_PCISR) Parallel Capture Mode Data Ready */\r
+#define PIO_PCISR_OVRE (0x1u << 1) /**< \brief (PIO_PCISR) Parallel Capture Mode Overrun Error. */\r
+#define PIO_PCISR_ENDRX (0x1u << 2) /**< \brief (PIO_PCISR) End of Reception Transfer. */\r
+#define PIO_PCISR_RXBUFF (0x1u << 3) /**< \brief (PIO_PCISR) Reception Buffer Full */\r
+/* -------- PIO_PCRHR : (PIO Offset: 0x164) Parallel Capture Reception Holding Register -------- */\r
+#define PIO_PCRHR_RDATA_Pos 0\r
+#define PIO_PCRHR_RDATA_Msk (0xffffffffu << PIO_PCRHR_RDATA_Pos) /**< \brief (PIO_PCRHR) Parallel Capture Mode Reception Data. */\r
+/* -------- PIO_RPR : (PIO Offset: 0x168) Receive Pointer Register -------- */\r
+#define PIO_RPR_RXPTR_Pos 0\r
+#define PIO_RPR_RXPTR_Msk (0xffffffffu << PIO_RPR_RXPTR_Pos) /**< \brief (PIO_RPR) Receive Pointer Register */\r
+#define PIO_RPR_RXPTR(value) ((PIO_RPR_RXPTR_Msk & ((value) << PIO_RPR_RXPTR_Pos)))\r
+/* -------- PIO_RCR : (PIO Offset: 0x16C) Receive Counter Register -------- */\r
+#define PIO_RCR_RXCTR_Pos 0\r
+#define PIO_RCR_RXCTR_Msk (0xffffu << PIO_RCR_RXCTR_Pos) /**< \brief (PIO_RCR) Receive Counter Register */\r
+#define PIO_RCR_RXCTR(value) ((PIO_RCR_RXCTR_Msk & ((value) << PIO_RCR_RXCTR_Pos)))\r
+/* -------- PIO_RNPR : (PIO Offset: 0x178) Receive Next Pointer Register -------- */\r
+#define PIO_RNPR_RXNPTR_Pos 0\r
+#define PIO_RNPR_RXNPTR_Msk (0xffffffffu << PIO_RNPR_RXNPTR_Pos) /**< \brief (PIO_RNPR) Receive Next Pointer */\r
+#define PIO_RNPR_RXNPTR(value) ((PIO_RNPR_RXNPTR_Msk & ((value) << PIO_RNPR_RXNPTR_Pos)))\r
+/* -------- PIO_RNCR : (PIO Offset: 0x17C) Receive Next Counter Register -------- */\r
+#define PIO_RNCR_RXNCTR_Pos 0\r
+#define PIO_RNCR_RXNCTR_Msk (0xffffu << PIO_RNCR_RXNCTR_Pos) /**< \brief (PIO_RNCR) Receive Next Counter */\r
+#define PIO_RNCR_RXNCTR(value) ((PIO_RNCR_RXNCTR_Msk & ((value) << PIO_RNCR_RXNCTR_Pos)))\r
+/* -------- PIO_PTCR : (PIO Offset: 0x188) Transfer Control Register -------- */\r
+#define PIO_PTCR_RXTEN (0x1u << 0) /**< \brief (PIO_PTCR) Receiver Transfer Enable */\r
+#define PIO_PTCR_RXTDIS (0x1u << 1) /**< \brief (PIO_PTCR) Receiver Transfer Disable */\r
+#define PIO_PTCR_TXTEN (0x1u << 8) /**< \brief (PIO_PTCR) Transmitter Transfer Enable */\r
+#define PIO_PTCR_TXTDIS (0x1u << 9) /**< \brief (PIO_PTCR) Transmitter Transfer Disable */\r
+/* -------- PIO_PTSR : (PIO Offset: 0x18C) Transfer Status Register -------- */\r
+#define PIO_PTSR_RXTEN (0x1u << 0) /**< \brief (PIO_PTSR) Receiver Transfer Enable */\r
+#define PIO_PTSR_TXTEN (0x1u << 8) /**< \brief (PIO_PTSR) Transmitter Transfer Enable */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM4E_PIO_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4E_PMC_COMPONENT_\r
+#define _SAM4E_PMC_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Power Management Controller */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM4E_PMC Power Management Controller */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Pmc hardware registers */\r
+typedef struct {\r
+ WoReg PMC_SCER; /**< \brief (Pmc Offset: 0x0000) System Clock Enable Register */\r
+ WoReg PMC_SCDR; /**< \brief (Pmc Offset: 0x0004) System Clock Disable Register */\r
+ RoReg PMC_SCSR; /**< \brief (Pmc Offset: 0x0008) System Clock Status Register */\r
+ RoReg Reserved1[1];\r
+ WoReg PMC_PCER0; /**< \brief (Pmc Offset: 0x0010) Peripheral Clock Enable Register 0 */\r
+ WoReg PMC_PCDR0; /**< \brief (Pmc Offset: 0x0014) Peripheral Clock Disable Register 0 */\r
+ RoReg PMC_PCSR0; /**< \brief (Pmc Offset: 0x0018) Peripheral Clock Status Register 0 */\r
+ RoReg Reserved2[1];\r
+ RwReg CKGR_MOR; /**< \brief (Pmc Offset: 0x0020) Main Oscillator Register */\r
+ RwReg CKGR_MCFR; /**< \brief (Pmc Offset: 0x0024) Main Clock Frequency Register */\r
+ RwReg CKGR_PLLAR; /**< \brief (Pmc Offset: 0x0028) PLLA Register */\r
+ RoReg Reserved3[1];\r
+ RwReg PMC_MCKR; /**< \brief (Pmc Offset: 0x0030) Master Clock Register */\r
+ RoReg Reserved4[1];\r
+ RwReg PMC_USB; /**< \brief (Pmc Offset: 0x0038) USB Clock Register */\r
+ RoReg Reserved5[1];\r
+ RwReg PMC_PCK[3]; /**< \brief (Pmc Offset: 0x0040) Programmable Clock 0 Register */\r
+ RoReg Reserved6[5];\r
+ WoReg PMC_IER; /**< \brief (Pmc Offset: 0x0060) Interrupt Enable Register */\r
+ WoReg PMC_IDR; /**< \brief (Pmc Offset: 0x0064) Interrupt Disable Register */\r
+ RoReg PMC_SR; /**< \brief (Pmc Offset: 0x0068) Status Register */\r
+ RoReg PMC_IMR; /**< \brief (Pmc Offset: 0x006C) Interrupt Mask Register */\r
+ RwReg PMC_FSMR; /**< \brief (Pmc Offset: 0x0070) Fast Start-up Mode Register */\r
+ RwReg PMC_FSPR; /**< \brief (Pmc Offset: 0x0074) Fast Start-up Polarity Register */\r
+ WoReg PMC_FOCR; /**< \brief (Pmc Offset: 0x0078) Fault Output Clear Register */\r
+ RoReg Reserved7[26];\r
+ RwReg PMC_WPMR; /**< \brief (Pmc Offset: 0x00E4) Write Protect Mode Register */\r
+ RoReg PMC_WPSR; /**< \brief (Pmc Offset: 0x00E8) Write Protect Status Register */\r
+ RoReg Reserved8[5];\r
+ WoReg PMC_PCER1; /**< \brief (Pmc Offset: 0x0100) Peripheral Clock Enable Register 1 */\r
+ WoReg PMC_PCDR1; /**< \brief (Pmc Offset: 0x0104) Peripheral Clock Disable Register 1 */\r
+ RoReg PMC_PCSR1; /**< \brief (Pmc Offset: 0x0108) Peripheral Clock Status Register 1 */\r
+ RoReg Reserved9[1];\r
+ RwReg PMC_OCR; /**< \brief (Pmc Offset: 0x0110) Oscillator Calibration Register */\r
+} Pmc;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- PMC_SCER : (PMC Offset: 0x0000) System Clock Enable Register -------- */\r
+#define PMC_SCER_UDP (0x1u << 7) /**< \brief (PMC_SCER) USB Device Port Clock Enable */\r
+#define PMC_SCER_PCK0 (0x1u << 8) /**< \brief (PMC_SCER) Programmable Clock 0 Output Enable */\r
+#define PMC_SCER_PCK1 (0x1u << 9) /**< \brief (PMC_SCER) Programmable Clock 1 Output Enable */\r
+#define PMC_SCER_PCK2 (0x1u << 10) /**< \brief (PMC_SCER) Programmable Clock 2 Output Enable */\r
+/* -------- PMC_SCDR : (PMC Offset: 0x0004) System Clock Disable Register -------- */\r
+#define PMC_SCDR_UDP (0x1u << 7) /**< \brief (PMC_SCDR) USB Device Port Clock Disable */\r
+#define PMC_SCDR_PCK0 (0x1u << 8) /**< \brief (PMC_SCDR) Programmable Clock 0 Output Disable */\r
+#define PMC_SCDR_PCK1 (0x1u << 9) /**< \brief (PMC_SCDR) Programmable Clock 1 Output Disable */\r
+#define PMC_SCDR_PCK2 (0x1u << 10) /**< \brief (PMC_SCDR) Programmable Clock 2 Output Disable */\r
+/* -------- PMC_SCSR : (PMC Offset: 0x0008) System Clock Status Register -------- */\r
+#define PMC_SCSR_UDP (0x1u << 7) /**< \brief (PMC_SCSR) USB Device Port Clock Status */\r
+#define PMC_SCSR_PCK0 (0x1u << 8) /**< \brief (PMC_SCSR) Programmable Clock 0 Output Status */\r
+#define PMC_SCSR_PCK1 (0x1u << 9) /**< \brief (PMC_SCSR) Programmable Clock 1 Output Status */\r
+#define PMC_SCSR_PCK2 (0x1u << 10) /**< \brief (PMC_SCSR) Programmable Clock 2 Output Status */\r
+/* -------- PMC_PCER0 : (PMC Offset: 0x0010) Peripheral Clock Enable Register 0 -------- */\r
+#define PMC_PCER0_PID9 (0x1u << 9) /**< \brief (PMC_PCER0) Peripheral Clock 9 Enable */\r
+#define PMC_PCER0_PID10 (0x1u << 10) /**< \brief (PMC_PCER0) Peripheral Clock 10 Enable */\r
+#define PMC_PCER0_PID11 (0x1u << 11) /**< \brief (PMC_PCER0) Peripheral Clock 11 Enable */\r
+#define PMC_PCER0_PID12 (0x1u << 12) /**< \brief (PMC_PCER0) Peripheral Clock 12 Enable */\r
+#define PMC_PCER0_PID13 (0x1u << 13) /**< \brief (PMC_PCER0) Peripheral Clock 13 Enable */\r
+#define PMC_PCER0_PID14 (0x1u << 14) /**< \brief (PMC_PCER0) Peripheral Clock 14 Enable */\r
+#define PMC_PCER0_PID15 (0x1u << 15) /**< \brief (PMC_PCER0) Peripheral Clock 15 Enable */\r
+#define PMC_PCER0_PID16 (0x1u << 16) /**< \brief (PMC_PCER0) Peripheral Clock 16 Enable */\r
+#define PMC_PCER0_PID17 (0x1u << 17) /**< \brief (PMC_PCER0) Peripheral Clock 17 Enable */\r
+#define PMC_PCER0_PID18 (0x1u << 18) /**< \brief (PMC_PCER0) Peripheral Clock 18 Enable */\r
+#define PMC_PCER0_PID19 (0x1u << 19) /**< \brief (PMC_PCER0) Peripheral Clock 19 Enable */\r
+#define PMC_PCER0_PID20 (0x1u << 20) /**< \brief (PMC_PCER0) Peripheral Clock 20 Enable */\r
+#define PMC_PCER0_PID21 (0x1u << 21) /**< \brief (PMC_PCER0) Peripheral Clock 21 Enable */\r
+#define PMC_PCER0_PID22 (0x1u << 22) /**< \brief (PMC_PCER0) Peripheral Clock 22 Enable */\r
+#define PMC_PCER0_PID23 (0x1u << 23) /**< \brief (PMC_PCER0) Peripheral Clock 23 Enable */\r
+#define PMC_PCER0_PID24 (0x1u << 24) /**< \brief (PMC_PCER0) Peripheral Clock 24 Enable */\r
+#define PMC_PCER0_PID25 (0x1u << 25) /**< \brief (PMC_PCER0) Peripheral Clock 25 Enable */\r
+#define PMC_PCER0_PID26 (0x1u << 26) /**< \brief (PMC_PCER0) Peripheral Clock 26 Enable */\r
+#define PMC_PCER0_PID27 (0x1u << 27) /**< \brief (PMC_PCER0) Peripheral Clock 27 Enable */\r
+#define PMC_PCER0_PID28 (0x1u << 28) /**< \brief (PMC_PCER0) Peripheral Clock 28 Enable */\r
+#define PMC_PCER0_PID29 (0x1u << 29) /**< \brief (PMC_PCER0) Peripheral Clock 29 Enable */\r
+#define PMC_PCER0_PID30 (0x1u << 30) /**< \brief (PMC_PCER0) Peripheral Clock 30 Enable */\r
+#define PMC_PCER0_PID31 (0x1u << 31) /**< \brief (PMC_PCER0) Peripheral Clock 31 Enable */\r
+/* -------- PMC_PCDR0 : (PMC Offset: 0x0014) Peripheral Clock Disable Register 0 -------- */\r
+#define PMC_PCDR0_PID9 (0x1u << 9) /**< \brief (PMC_PCDR0) Peripheral Clock 9 Disable */\r
+#define PMC_PCDR0_PID10 (0x1u << 10) /**< \brief (PMC_PCDR0) Peripheral Clock 10 Disable */\r
+#define PMC_PCDR0_PID11 (0x1u << 11) /**< \brief (PMC_PCDR0) Peripheral Clock 11 Disable */\r
+#define PMC_PCDR0_PID12 (0x1u << 12) /**< \brief (PMC_PCDR0) Peripheral Clock 12 Disable */\r
+#define PMC_PCDR0_PID13 (0x1u << 13) /**< \brief (PMC_PCDR0) Peripheral Clock 13 Disable */\r
+#define PMC_PCDR0_PID14 (0x1u << 14) /**< \brief (PMC_PCDR0) Peripheral Clock 14 Disable */\r
+#define PMC_PCDR0_PID15 (0x1u << 15) /**< \brief (PMC_PCDR0) Peripheral Clock 15 Disable */\r
+#define PMC_PCDR0_PID16 (0x1u << 16) /**< \brief (PMC_PCDR0) Peripheral Clock 16 Disable */\r
+#define PMC_PCDR0_PID17 (0x1u << 17) /**< \brief (PMC_PCDR0) Peripheral Clock 17 Disable */\r
+#define PMC_PCDR0_PID18 (0x1u << 18) /**< \brief (PMC_PCDR0) Peripheral Clock 18 Disable */\r
+#define PMC_PCDR0_PID19 (0x1u << 19) /**< \brief (PMC_PCDR0) Peripheral Clock 19 Disable */\r
+#define PMC_PCDR0_PID20 (0x1u << 20) /**< \brief (PMC_PCDR0) Peripheral Clock 20 Disable */\r
+#define PMC_PCDR0_PID21 (0x1u << 21) /**< \brief (PMC_PCDR0) Peripheral Clock 21 Disable */\r
+#define PMC_PCDR0_PID22 (0x1u << 22) /**< \brief (PMC_PCDR0) Peripheral Clock 22 Disable */\r
+#define PMC_PCDR0_PID23 (0x1u << 23) /**< \brief (PMC_PCDR0) Peripheral Clock 23 Disable */\r
+#define PMC_PCDR0_PID24 (0x1u << 24) /**< \brief (PMC_PCDR0) Peripheral Clock 24 Disable */\r
+#define PMC_PCDR0_PID25 (0x1u << 25) /**< \brief (PMC_PCDR0) Peripheral Clock 25 Disable */\r
+#define PMC_PCDR0_PID26 (0x1u << 26) /**< \brief (PMC_PCDR0) Peripheral Clock 26 Disable */\r
+#define PMC_PCDR0_PID27 (0x1u << 27) /**< \brief (PMC_PCDR0) Peripheral Clock 27 Disable */\r
+#define PMC_PCDR0_PID28 (0x1u << 28) /**< \brief (PMC_PCDR0) Peripheral Clock 28 Disable */\r
+#define PMC_PCDR0_PID29 (0x1u << 29) /**< \brief (PMC_PCDR0) Peripheral Clock 29 Disable */\r
+#define PMC_PCDR0_PID30 (0x1u << 30) /**< \brief (PMC_PCDR0) Peripheral Clock 30 Disable */\r
+#define PMC_PCDR0_PID31 (0x1u << 31) /**< \brief (PMC_PCDR0) Peripheral Clock 31 Disable */\r
+/* -------- PMC_PCSR0 : (PMC Offset: 0x0018) Peripheral Clock Status Register 0 -------- */\r
+#define PMC_PCSR0_PID9 (0x1u << 9) /**< \brief (PMC_PCSR0) Peripheral Clock 9 Status */\r
+#define PMC_PCSR0_PID10 (0x1u << 10) /**< \brief (PMC_PCSR0) Peripheral Clock 10 Status */\r
+#define PMC_PCSR0_PID11 (0x1u << 11) /**< \brief (PMC_PCSR0) Peripheral Clock 11 Status */\r
+#define PMC_PCSR0_PID12 (0x1u << 12) /**< \brief (PMC_PCSR0) Peripheral Clock 12 Status */\r
+#define PMC_PCSR0_PID13 (0x1u << 13) /**< \brief (PMC_PCSR0) Peripheral Clock 13 Status */\r
+#define PMC_PCSR0_PID14 (0x1u << 14) /**< \brief (PMC_PCSR0) Peripheral Clock 14 Status */\r
+#define PMC_PCSR0_PID15 (0x1u << 15) /**< \brief (PMC_PCSR0) Peripheral Clock 15 Status */\r
+#define PMC_PCSR0_PID16 (0x1u << 16) /**< \brief (PMC_PCSR0) Peripheral Clock 16 Status */\r
+#define PMC_PCSR0_PID17 (0x1u << 17) /**< \brief (PMC_PCSR0) Peripheral Clock 17 Status */\r
+#define PMC_PCSR0_PID18 (0x1u << 18) /**< \brief (PMC_PCSR0) Peripheral Clock 18 Status */\r
+#define PMC_PCSR0_PID19 (0x1u << 19) /**< \brief (PMC_PCSR0) Peripheral Clock 19 Status */\r
+#define PMC_PCSR0_PID20 (0x1u << 20) /**< \brief (PMC_PCSR0) Peripheral Clock 20 Status */\r
+#define PMC_PCSR0_PID21 (0x1u << 21) /**< \brief (PMC_PCSR0) Peripheral Clock 21 Status */\r
+#define PMC_PCSR0_PID22 (0x1u << 22) /**< \brief (PMC_PCSR0) Peripheral Clock 22 Status */\r
+#define PMC_PCSR0_PID23 (0x1u << 23) /**< \brief (PMC_PCSR0) Peripheral Clock 23 Status */\r
+#define PMC_PCSR0_PID24 (0x1u << 24) /**< \brief (PMC_PCSR0) Peripheral Clock 24 Status */\r
+#define PMC_PCSR0_PID25 (0x1u << 25) /**< \brief (PMC_PCSR0) Peripheral Clock 25 Status */\r
+#define PMC_PCSR0_PID26 (0x1u << 26) /**< \brief (PMC_PCSR0) Peripheral Clock 26 Status */\r
+#define PMC_PCSR0_PID27 (0x1u << 27) /**< \brief (PMC_PCSR0) Peripheral Clock 27 Status */\r
+#define PMC_PCSR0_PID28 (0x1u << 28) /**< \brief (PMC_PCSR0) Peripheral Clock 28 Status */\r
+#define PMC_PCSR0_PID29 (0x1u << 29) /**< \brief (PMC_PCSR0) Peripheral Clock 29 Status */\r
+#define PMC_PCSR0_PID30 (0x1u << 30) /**< \brief (PMC_PCSR0) Peripheral Clock 30 Status */\r
+#define PMC_PCSR0_PID31 (0x1u << 31) /**< \brief (PMC_PCSR0) Peripheral Clock 31 Status */\r
+/* -------- CKGR_MOR : (PMC Offset: 0x0020) Main Oscillator Register -------- */\r
+#define CKGR_MOR_MOSCXTEN (0x1u << 0) /**< \brief (CKGR_MOR) Main Crystal Oscillator Enable */\r
+#define CKGR_MOR_MOSCXTBY (0x1u << 1) /**< \brief (CKGR_MOR) Main Crystal Oscillator Bypass */\r
+#define CKGR_MOR_WAITMODE (0x1u << 2) /**< \brief (CKGR_MOR) Wait Mode Command */\r
+#define CKGR_MOR_MOSCRCEN (0x1u << 3) /**< \brief (CKGR_MOR) Main On-Chip RC Oscillator Enable */\r
+#define CKGR_MOR_MOSCRCF_Pos 4\r
+#define CKGR_MOR_MOSCRCF_Msk (0x7u << CKGR_MOR_MOSCRCF_Pos) /**< \brief (CKGR_MOR) Main On-Chip RC Oscillator Frequency Selection */\r
+#define CKGR_MOR_MOSCRCF_4_MHz (0x0u << 4) /**< \brief (CKGR_MOR) The Fast RC Oscillator Frequency is at 4 MHz (default) */\r
+#define CKGR_MOR_MOSCRCF_8_MHz (0x1u << 4) /**< \brief (CKGR_MOR) The Fast RC Oscillator Frequency is at 8 MHz */\r
+#define CKGR_MOR_MOSCRCF_12_MHz (0x2u << 4) /**< \brief (CKGR_MOR) The Fast RC Oscillator Frequency is at 12 MHz */\r
+#define CKGR_MOR_MOSCXTST_Pos 8\r
+#define CKGR_MOR_MOSCXTST_Msk (0xffu << CKGR_MOR_MOSCXTST_Pos) /**< \brief (CKGR_MOR) Main Crystal Oscillator Start-up Time */\r
+#define CKGR_MOR_MOSCXTST(value) ((CKGR_MOR_MOSCXTST_Msk & ((value) << CKGR_MOR_MOSCXTST_Pos)))\r
+#define CKGR_MOR_KEY_Pos 16\r
+#define CKGR_MOR_KEY_Msk (0xffu << CKGR_MOR_KEY_Pos) /**< \brief (CKGR_MOR) Password */\r
+#define CKGR_MOR_KEY(value) ((CKGR_MOR_KEY_Msk & ((value) << CKGR_MOR_KEY_Pos)))\r
+#define CKGR_MOR_MOSCSEL (0x1u << 24) /**< \brief (CKGR_MOR) Main Oscillator Selection */\r
+#define CKGR_MOR_CFDEN (0x1u << 25) /**< \brief (CKGR_MOR) Clock Failure Detector Enable */\r
+/* -------- CKGR_MCFR : (PMC Offset: 0x0024) Main Clock Frequency Register -------- */\r
+#define CKGR_MCFR_MAINF_Pos 0\r
+#define CKGR_MCFR_MAINF_Msk (0xffffu << CKGR_MCFR_MAINF_Pos) /**< \brief (CKGR_MCFR) Main Clock Frequency */\r
+#define CKGR_MCFR_MAINF(value) ((CKGR_MCFR_MAINF_Msk & ((value) << CKGR_MCFR_MAINF_Pos)))\r
+#define CKGR_MCFR_MAINFRDY (0x1u << 16) /**< \brief (CKGR_MCFR) Main Clock Ready */\r
+#define CKGR_MCFR_RCMEAS (0x1u << 20) /**< \brief (CKGR_MCFR) RC Oscillator Frequency Measure (write-only) */\r
+/* -------- CKGR_PLLAR : (PMC Offset: 0x0028) PLLA Register -------- */\r
+#define CKGR_PLLAR_DIVA_Pos 0\r
+#define CKGR_PLLAR_DIVA_Msk (0xffu << CKGR_PLLAR_DIVA_Pos) /**< \brief (CKGR_PLLAR) Divider */\r
+#define CKGR_PLLAR_DIVA(value) ((CKGR_PLLAR_DIVA_Msk & ((value) << CKGR_PLLAR_DIVA_Pos)))\r
+#define CKGR_PLLAR_PLLACOUNT_Pos 8\r
+#define CKGR_PLLAR_PLLACOUNT_Msk (0x3fu << CKGR_PLLAR_PLLACOUNT_Pos) /**< \brief (CKGR_PLLAR) PLLA Counter */\r
+#define CKGR_PLLAR_PLLACOUNT(value) ((CKGR_PLLAR_PLLACOUNT_Msk & ((value) << CKGR_PLLAR_PLLACOUNT_Pos)))\r
+#define CKGR_PLLAR_MULA_Pos 16\r
+#define CKGR_PLLAR_MULA_Msk (0x7ffu << CKGR_PLLAR_MULA_Pos) /**< \brief (CKGR_PLLAR) PLLA Multiplier */\r
+#define CKGR_PLLAR_MULA(value) ((CKGR_PLLAR_MULA_Msk & ((value) << CKGR_PLLAR_MULA_Pos)))\r
+#define CKGR_PLLAR_ONE (0x1u << 29) /**< \brief (CKGR_PLLAR) Must Be Set to 1 */\r
+/* -------- PMC_MCKR : (PMC Offset: 0x0030) Master Clock Register -------- */\r
+#define PMC_MCKR_CSS_Pos 0\r
+#define PMC_MCKR_CSS_Msk (0x3u << PMC_MCKR_CSS_Pos) /**< \brief (PMC_MCKR) Master Clock Source Selection */\r
+#define PMC_MCKR_CSS_SLOW_CLK (0x0u << 0) /**< \brief (PMC_MCKR) Slow Clock is selected */\r
+#define PMC_MCKR_CSS_MAIN_CLK (0x1u << 0) /**< \brief (PMC_MCKR) Main Clock is selected */\r
+#define PMC_MCKR_CSS_PLLA_CLK (0x2u << 0) /**< \brief (PMC_MCKR) PLLA Clock is selected */\r
+#define PMC_MCKR_PRES_Pos 4\r
+#define PMC_MCKR_PRES_Msk (0x7u << PMC_MCKR_PRES_Pos) /**< \brief (PMC_MCKR) Processor Clock Prescaler */\r
+#define PMC_MCKR_PRES_CLK_1 (0x0u << 4) /**< \brief (PMC_MCKR) Selected clock */\r
+#define PMC_MCKR_PRES_CLK_2 (0x1u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 2 */\r
+#define PMC_MCKR_PRES_CLK_4 (0x2u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 4 */\r
+#define PMC_MCKR_PRES_CLK_8 (0x3u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 8 */\r
+#define PMC_MCKR_PRES_CLK_16 (0x4u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 16 */\r
+#define PMC_MCKR_PRES_CLK_32 (0x5u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 32 */\r
+#define PMC_MCKR_PRES_CLK_64 (0x6u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 64 */\r
+#define PMC_MCKR_PRES_CLK_3 (0x7u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 3 */\r
+#define PMC_MCKR_PLLADIV2 (0x1u << 12) /**< \brief (PMC_MCKR) PLLA Divisor by 2 */\r
+/* -------- PMC_USB : (PMC Offset: 0x0038) USB Clock Register -------- */\r
+#define PMC_USB_USBDIV_Pos 8\r
+#define PMC_USB_USBDIV_Msk (0xfu << PMC_USB_USBDIV_Pos) /**< \brief (PMC_USB) Divider for USB Clock. */\r
+#define PMC_USB_USBDIV(value) ((PMC_USB_USBDIV_Msk & ((value) << PMC_USB_USBDIV_Pos)))\r
+/* -------- PMC_PCK[3] : (PMC Offset: 0x0040) Programmable Clock 0 Register -------- */\r
+#define PMC_PCK_CSS_Pos 0\r
+#define PMC_PCK_CSS_Msk (0x7u << PMC_PCK_CSS_Pos) /**< \brief (PMC_PCK[3]) Master Clock Source Selection */\r
+#define PMC_PCK_CSS_SLOW_CLK (0x0u << 0) /**< \brief (PMC_PCK[3]) Slow Clock is selected */\r
+#define PMC_PCK_CSS_MAIN_CLK (0x1u << 0) /**< \brief (PMC_PCK[3]) Main Clock is selected */\r
+#define PMC_PCK_CSS_PLLA_CLK (0x2u << 0) /**< \brief (PMC_PCK[3]) PLLA Clock is selected */\r
+#define PMC_PCK_CSS_MCK (0x4u << 0) /**< \brief (PMC_PCK[3]) Master Clock is selected */\r
+#define PMC_PCK_PRES_Pos 4\r
+#define PMC_PCK_PRES_Msk (0x7u << PMC_PCK_PRES_Pos) /**< \brief (PMC_PCK[3]) Programmable Clock Prescaler */\r
+#define PMC_PCK_PRES_CLK_1 (0x0u << 4) /**< \brief (PMC_PCK[3]) Selected clock */\r
+#define PMC_PCK_PRES_CLK_2 (0x1u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 2 */\r
+#define PMC_PCK_PRES_CLK_4 (0x2u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 4 */\r
+#define PMC_PCK_PRES_CLK_8 (0x3u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 8 */\r
+#define PMC_PCK_PRES_CLK_16 (0x4u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 16 */\r
+#define PMC_PCK_PRES_CLK_32 (0x5u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 32 */\r
+#define PMC_PCK_PRES_CLK_64 (0x6u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 64 */\r
+/* -------- PMC_IER : (PMC Offset: 0x0060) Interrupt Enable Register -------- */\r
+#define PMC_IER_MOSCXTS (0x1u << 0) /**< \brief (PMC_IER) Main Crystal Oscillator Status Interrupt Enable */\r
+#define PMC_IER_LOCKA (0x1u << 1) /**< \brief (PMC_IER) PLLA Lock Interrupt Enable */\r
+#define PMC_IER_MCKRDY (0x1u << 3) /**< \brief (PMC_IER) Master Clock Ready Interrupt Enable */\r
+#define PMC_IER_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IER) Programmable Clock Ready 0 Interrupt Enable */\r
+#define PMC_IER_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IER) Programmable Clock Ready 1 Interrupt Enable */\r
+#define PMC_IER_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IER) Programmable Clock Ready 2 Interrupt Enable */\r
+#define PMC_IER_MOSCSELS (0x1u << 16) /**< \brief (PMC_IER) Main Oscillator Selection Status Interrupt Enable */\r
+#define PMC_IER_MOSCRCS (0x1u << 17) /**< \brief (PMC_IER) Main On-Chip RC Status Interrupt Enable */\r
+#define PMC_IER_CFDEV (0x1u << 18) /**< \brief (PMC_IER) Clock Failure Detector Event Interrupt Enable */\r
+/* -------- PMC_IDR : (PMC Offset: 0x0064) Interrupt Disable Register -------- */\r
+#define PMC_IDR_MOSCXTS (0x1u << 0) /**< \brief (PMC_IDR) Main Crystal Oscillator Status Interrupt Disable */\r
+#define PMC_IDR_LOCKA (0x1u << 1) /**< \brief (PMC_IDR) PLLA Lock Interrupt Disable */\r
+#define PMC_IDR_MCKRDY (0x1u << 3) /**< \brief (PMC_IDR) Master Clock Ready Interrupt Disable */\r
+#define PMC_IDR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IDR) Programmable Clock Ready 0 Interrupt Disable */\r
+#define PMC_IDR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IDR) Programmable Clock Ready 1 Interrupt Disable */\r
+#define PMC_IDR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IDR) Programmable Clock Ready 2 Interrupt Disable */\r
+#define PMC_IDR_MOSCSELS (0x1u << 16) /**< \brief (PMC_IDR) Main Oscillator Selection Status Interrupt Disable */\r
+#define PMC_IDR_MOSCRCS (0x1u << 17) /**< \brief (PMC_IDR) Main On-Chip RC Status Interrupt Disable */\r
+#define PMC_IDR_CFDEV (0x1u << 18) /**< \brief (PMC_IDR) Clock Failure Detector Event Interrupt Disable */\r
+/* -------- PMC_SR : (PMC Offset: 0x0068) Status Register -------- */\r
+#define PMC_SR_MOSCXTS (0x1u << 0) /**< \brief (PMC_SR) Main XTAL Oscillator Status */\r
+#define PMC_SR_LOCKA (0x1u << 1) /**< \brief (PMC_SR) PLLA Lock Status */\r
+#define PMC_SR_MCKRDY (0x1u << 3) /**< \brief (PMC_SR) Master Clock Status */\r
+#define PMC_SR_OSCSELS (0x1u << 7) /**< \brief (PMC_SR) Slow Clock Oscillator Selection */\r
+#define PMC_SR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_SR) Programmable Clock Ready Status */\r
+#define PMC_SR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_SR) Programmable Clock Ready Status */\r
+#define PMC_SR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_SR) Programmable Clock Ready Status */\r
+#define PMC_SR_MOSCSELS (0x1u << 16) /**< \brief (PMC_SR) Main Oscillator Selection Status */\r
+#define PMC_SR_MOSCRCS (0x1u << 17) /**< \brief (PMC_SR) Main On-Chip RC Oscillator Status */\r
+#define PMC_SR_CFDEV (0x1u << 18) /**< \brief (PMC_SR) Clock Failure Detector Event */\r
+#define PMC_SR_CFDS (0x1u << 19) /**< \brief (PMC_SR) Clock Failure Detector Status */\r
+#define PMC_SR_FOS (0x1u << 20) /**< \brief (PMC_SR) Clock Failure Detector Fault Output Status */\r
+/* -------- PMC_IMR : (PMC Offset: 0x006C) Interrupt Mask Register -------- */\r
+#define PMC_IMR_MOSCXTS (0x1u << 0) /**< \brief (PMC_IMR) Main Crystal Oscillator Status Interrupt Mask */\r
+#define PMC_IMR_LOCKA (0x1u << 1) /**< \brief (PMC_IMR) PLLA Lock Interrupt Mask */\r
+#define PMC_IMR_MCKRDY (0x1u << 3) /**< \brief (PMC_IMR) Master Clock Ready Interrupt Mask */\r
+#define PMC_IMR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IMR) Programmable Clock Ready 0 Interrupt Mask */\r
+#define PMC_IMR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IMR) Programmable Clock Ready 1 Interrupt Mask */\r
+#define PMC_IMR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IMR) Programmable Clock Ready 2 Interrupt Mask */\r
+#define PMC_IMR_MOSCSELS (0x1u << 16) /**< \brief (PMC_IMR) Main Oscillator Selection Status Interrupt Mask */\r
+#define PMC_IMR_MOSCRCS (0x1u << 17) /**< \brief (PMC_IMR) Main On-Chip RC Status Interrupt Mask */\r
+#define PMC_IMR_CFDEV (0x1u << 18) /**< \brief (PMC_IMR) Clock Failure Detector Event Interrupt Mask */\r
+/* -------- PMC_FSMR : (PMC Offset: 0x0070) Fast Start-up Mode Register -------- */\r
+#define PMC_FSMR_FSTT0 (0x1u << 0) /**< \brief (PMC_FSMR) Fast Start-up Input Enable 0 */\r
+#define PMC_FSMR_FSTT1 (0x1u << 1) /**< \brief (PMC_FSMR) Fast Start-up Input Enable 1 */\r
+#define PMC_FSMR_FSTT2 (0x1u << 2) /**< \brief (PMC_FSMR) Fast Start-up Input Enable 2 */\r
+#define PMC_FSMR_FSTT3 (0x1u << 3) /**< \brief (PMC_FSMR) Fast Start-up Input Enable 3 */\r
+#define PMC_FSMR_FSTT4 (0x1u << 4) /**< \brief (PMC_FSMR) Fast Start-up Input Enable 4 */\r
+#define PMC_FSMR_FSTT5 (0x1u << 5) /**< \brief (PMC_FSMR) Fast Start-up Input Enable 5 */\r
+#define PMC_FSMR_FSTT6 (0x1u << 6) /**< \brief (PMC_FSMR) Fast Start-up Input Enable 6 */\r
+#define PMC_FSMR_FSTT7 (0x1u << 7) /**< \brief (PMC_FSMR) Fast Start-up Input Enable 7 */\r
+#define PMC_FSMR_FSTT8 (0x1u << 8) /**< \brief (PMC_FSMR) Fast Start-up Input Enable 8 */\r
+#define PMC_FSMR_FSTT9 (0x1u << 9) /**< \brief (PMC_FSMR) Fast Start-up Input Enable 9 */\r
+#define PMC_FSMR_FSTT10 (0x1u << 10) /**< \brief (PMC_FSMR) Fast Start-up Input Enable 10 */\r
+#define PMC_FSMR_FSTT11 (0x1u << 11) /**< \brief (PMC_FSMR) Fast Start-up Input Enable 11 */\r
+#define PMC_FSMR_FSTT12 (0x1u << 12) /**< \brief (PMC_FSMR) Fast Start-up Input Enable 12 */\r
+#define PMC_FSMR_FSTT13 (0x1u << 13) /**< \brief (PMC_FSMR) Fast Start-up Input Enable 13 */\r
+#define PMC_FSMR_FSTT14 (0x1u << 14) /**< \brief (PMC_FSMR) Fast Start-up Input Enable 14 */\r
+#define PMC_FSMR_FSTT15 (0x1u << 15) /**< \brief (PMC_FSMR) Fast Start-up Input Enable 15 */\r
+#define PMC_FSMR_RTTAL (0x1u << 16) /**< \brief (PMC_FSMR) RTT Alarm Enable */\r
+#define PMC_FSMR_RTCAL (0x1u << 17) /**< \brief (PMC_FSMR) RTC Alarm Enable */\r
+#define PMC_FSMR_USBAL (0x1u << 18) /**< \brief (PMC_FSMR) USB Alarm Enable */\r
+#define PMC_FSMR_FLPM_Pos 21\r
+#define PMC_FSMR_FLPM_Msk (0x3u << PMC_FSMR_FLPM_Pos) /**< \brief (PMC_FSMR) Flash Low Power Mode */\r
+#define PMC_FSMR_FLPM_FLASH_STANDBY (0x0u << 21) /**< \brief (PMC_FSMR) Flash is in Standby Mode when system enters Wait Mode */\r
+#define PMC_FSMR_FLPM_FLASH_DEEP_POWERDOWN (0x1u << 21) /**< \brief (PMC_FSMR) Flash is in deep power down mode when system enters Wait Mode */\r
+#define PMC_FSMR_FLPM_FLASH_IDLE (0x2u << 21) /**< \brief (PMC_FSMR) idle mode */\r
+/* -------- PMC_FSPR : (PMC Offset: 0x0074) Fast Start-up Polarity Register -------- */\r
+#define PMC_FSPR_FSTP0 (0x1u << 0) /**< \brief (PMC_FSPR) Fast Start-up Input Polarityx */\r
+#define PMC_FSPR_FSTP1 (0x1u << 1) /**< \brief (PMC_FSPR) Fast Start-up Input Polarityx */\r
+#define PMC_FSPR_FSTP2 (0x1u << 2) /**< \brief (PMC_FSPR) Fast Start-up Input Polarityx */\r
+#define PMC_FSPR_FSTP3 (0x1u << 3) /**< \brief (PMC_FSPR) Fast Start-up Input Polarityx */\r
+#define PMC_FSPR_FSTP4 (0x1u << 4) /**< \brief (PMC_FSPR) Fast Start-up Input Polarityx */\r
+#define PMC_FSPR_FSTP5 (0x1u << 5) /**< \brief (PMC_FSPR) Fast Start-up Input Polarityx */\r
+#define PMC_FSPR_FSTP6 (0x1u << 6) /**< \brief (PMC_FSPR) Fast Start-up Input Polarityx */\r
+#define PMC_FSPR_FSTP7 (0x1u << 7) /**< \brief (PMC_FSPR) Fast Start-up Input Polarityx */\r
+#define PMC_FSPR_FSTP8 (0x1u << 8) /**< \brief (PMC_FSPR) Fast Start-up Input Polarityx */\r
+#define PMC_FSPR_FSTP9 (0x1u << 9) /**< \brief (PMC_FSPR) Fast Start-up Input Polarityx */\r
+#define PMC_FSPR_FSTP10 (0x1u << 10) /**< \brief (PMC_FSPR) Fast Start-up Input Polarityx */\r
+#define PMC_FSPR_FSTP11 (0x1u << 11) /**< \brief (PMC_FSPR) Fast Start-up Input Polarityx */\r
+#define PMC_FSPR_FSTP12 (0x1u << 12) /**< \brief (PMC_FSPR) Fast Start-up Input Polarityx */\r
+#define PMC_FSPR_FSTP13 (0x1u << 13) /**< \brief (PMC_FSPR) Fast Start-up Input Polarityx */\r
+#define PMC_FSPR_FSTP14 (0x1u << 14) /**< \brief (PMC_FSPR) Fast Start-up Input Polarityx */\r
+#define PMC_FSPR_FSTP15 (0x1u << 15) /**< \brief (PMC_FSPR) Fast Start-up Input Polarityx */\r
+/* -------- PMC_FOCR : (PMC Offset: 0x0078) Fault Output Clear Register -------- */\r
+#define PMC_FOCR_FOCLR (0x1u << 0) /**< \brief (PMC_FOCR) Fault Output Clear */\r
+/* -------- PMC_WPMR : (PMC Offset: 0x00E4) Write Protect Mode Register -------- */\r
+#define PMC_WPMR_WPEN (0x1u << 0) /**< \brief (PMC_WPMR) Write Protect Enable */\r
+#define PMC_WPMR_WPKEY_Pos 8\r
+#define PMC_WPMR_WPKEY_Msk (0xffffffu << PMC_WPMR_WPKEY_Pos) /**< \brief (PMC_WPMR) Write Protect KEY */\r
+#define PMC_WPMR_WPKEY(value) ((PMC_WPMR_WPKEY_Msk & ((value) << PMC_WPMR_WPKEY_Pos)))\r
+/* -------- PMC_WPSR : (PMC Offset: 0x00E8) Write Protect Status Register -------- */\r
+#define PMC_WPSR_WPVS (0x1u << 0) /**< \brief (PMC_WPSR) Write Protect Violation Status */\r
+#define PMC_WPSR_WPVSRC_Pos 8\r
+#define PMC_WPSR_WPVSRC_Msk (0xffffu << PMC_WPSR_WPVSRC_Pos) /**< \brief (PMC_WPSR) Write Protect Violation Source */\r
+/* -------- PMC_PCER1 : (PMC Offset: 0x0100) Peripheral Clock Enable Register 1 -------- */\r
+#define PMC_PCER1_PID32 (0x1u << 0) /**< \brief (PMC_PCER1) Peripheral Clock 32 Enable */\r
+#define PMC_PCER1_PID33 (0x1u << 1) /**< \brief (PMC_PCER1) Peripheral Clock 33 Enable */\r
+#define PMC_PCER1_PID34 (0x1u << 2) /**< \brief (PMC_PCER1) Peripheral Clock 34 Enable */\r
+#define PMC_PCER1_PID35 (0x1u << 3) /**< \brief (PMC_PCER1) Peripheral Clock 35 Enable */\r
+#define PMC_PCER1_PID36 (0x1u << 4) /**< \brief (PMC_PCER1) Peripheral Clock 36 Enable */\r
+#define PMC_PCER1_PID37 (0x1u << 5) /**< \brief (PMC_PCER1) Peripheral Clock 37 Enable */\r
+#define PMC_PCER1_PID38 (0x1u << 6) /**< \brief (PMC_PCER1) Peripheral Clock 38 Enable */\r
+#define PMC_PCER1_PID39 (0x1u << 7) /**< \brief (PMC_PCER1) Peripheral Clock 39 Enable */\r
+#define PMC_PCER1_PID40 (0x1u << 8) /**< \brief (PMC_PCER1) Peripheral Clock 40 Enable */\r
+#define PMC_PCER1_PID41 (0x1u << 9) /**< \brief (PMC_PCER1) Peripheral Clock 41 Enable */\r
+#define PMC_PCER1_PID42 (0x1u << 10) /**< \brief (PMC_PCER1) Peripheral Clock 42 Enable */\r
+#define PMC_PCER1_PID43 (0x1u << 11) /**< \brief (PMC_PCER1) Peripheral Clock 43 Enable */\r
+#define PMC_PCER1_PID44 (0x1u << 12) /**< \brief (PMC_PCER1) Peripheral Clock 44 Enable */\r
+#define PMC_PCER1_PID45 (0x1u << 13) /**< \brief (PMC_PCER1) Peripheral Clock 45 Enable */\r
+#define PMC_PCER1_PID46 (0x1u << 14) /**< \brief (PMC_PCER1) Peripheral Clock 46 Enable */\r
+#define PMC_PCER1_PID47 (0x1u << 15) /**< \brief (PMC_PCER1) Peripheral Clock 47 Enable */\r
+/* -------- PMC_PCDR1 : (PMC Offset: 0x0104) Peripheral Clock Disable Register 1 -------- */\r
+#define PMC_PCDR1_PID32 (0x1u << 0) /**< \brief (PMC_PCDR1) Peripheral Clock 32 Disable */\r
+#define PMC_PCDR1_PID33 (0x1u << 1) /**< \brief (PMC_PCDR1) Peripheral Clock 33 Disable */\r
+#define PMC_PCDR1_PID34 (0x1u << 2) /**< \brief (PMC_PCDR1) Peripheral Clock 34 Disable */\r
+#define PMC_PCDR1_PID35 (0x1u << 3) /**< \brief (PMC_PCDR1) Peripheral Clock 35 Disable */\r
+#define PMC_PCDR1_PID36 (0x1u << 4) /**< \brief (PMC_PCDR1) Peripheral Clock 36 Disable */\r
+#define PMC_PCDR1_PID37 (0x1u << 5) /**< \brief (PMC_PCDR1) Peripheral Clock 37 Disable */\r
+#define PMC_PCDR1_PID38 (0x1u << 6) /**< \brief (PMC_PCDR1) Peripheral Clock 38 Disable */\r
+#define PMC_PCDR1_PID39 (0x1u << 7) /**< \brief (PMC_PCDR1) Peripheral Clock 39 Disable */\r
+#define PMC_PCDR1_PID40 (0x1u << 8) /**< \brief (PMC_PCDR1) Peripheral Clock 40 Disable */\r
+#define PMC_PCDR1_PID41 (0x1u << 9) /**< \brief (PMC_PCDR1) Peripheral Clock 41 Disable */\r
+#define PMC_PCDR1_PID42 (0x1u << 10) /**< \brief (PMC_PCDR1) Peripheral Clock 42 Disable */\r
+#define PMC_PCDR1_PID43 (0x1u << 11) /**< \brief (PMC_PCDR1) Peripheral Clock 43 Disable */\r
+#define PMC_PCDR1_PID44 (0x1u << 12) /**< \brief (PMC_PCDR1) Peripheral Clock 44 Disable */\r
+#define PMC_PCDR1_PID45 (0x1u << 13) /**< \brief (PMC_PCDR1) Peripheral Clock 45 Disable */\r
+#define PMC_PCDR1_PID46 (0x1u << 14) /**< \brief (PMC_PCDR1) Peripheral Clock 46 Disable */\r
+#define PMC_PCDR1_PID47 (0x1u << 15) /**< \brief (PMC_PCDR1) Peripheral Clock 47 Disable */\r
+/* -------- PMC_PCSR1 : (PMC Offset: 0x0108) Peripheral Clock Status Register 1 -------- */\r
+#define PMC_PCSR1_PID32 (0x1u << 0) /**< \brief (PMC_PCSR1) Peripheral Clock 32 Status */\r
+#define PMC_PCSR1_PID33 (0x1u << 1) /**< \brief (PMC_PCSR1) Peripheral Clock 33 Status */\r
+#define PMC_PCSR1_PID34 (0x1u << 2) /**< \brief (PMC_PCSR1) Peripheral Clock 34 Status */\r
+#define PMC_PCSR1_PID35 (0x1u << 3) /**< \brief (PMC_PCSR1) Peripheral Clock 35 Status */\r
+#define PMC_PCSR1_PID36 (0x1u << 4) /**< \brief (PMC_PCSR1) Peripheral Clock 36 Status */\r
+#define PMC_PCSR1_PID37 (0x1u << 5) /**< \brief (PMC_PCSR1) Peripheral Clock 37 Status */\r
+#define PMC_PCSR1_PID38 (0x1u << 6) /**< \brief (PMC_PCSR1) Peripheral Clock 38 Status */\r
+#define PMC_PCSR1_PID39 (0x1u << 7) /**< \brief (PMC_PCSR1) Peripheral Clock 39 Status */\r
+#define PMC_PCSR1_PID40 (0x1u << 8) /**< \brief (PMC_PCSR1) Peripheral Clock 40 Status */\r
+#define PMC_PCSR1_PID41 (0x1u << 9) /**< \brief (PMC_PCSR1) Peripheral Clock 41 Status */\r
+#define PMC_PCSR1_PID42 (0x1u << 10) /**< \brief (PMC_PCSR1) Peripheral Clock 42 Status */\r
+#define PMC_PCSR1_PID43 (0x1u << 11) /**< \brief (PMC_PCSR1) Peripheral Clock 43 Status */\r
+#define PMC_PCSR1_PID44 (0x1u << 12) /**< \brief (PMC_PCSR1) Peripheral Clock 44 Status */\r
+#define PMC_PCSR1_PID45 (0x1u << 13) /**< \brief (PMC_PCSR1) Peripheral Clock 45 Status */\r
+#define PMC_PCSR1_PID46 (0x1u << 14) /**< \brief (PMC_PCSR1) Peripheral Clock 46 Status */\r
+#define PMC_PCSR1_PID47 (0x1u << 15) /**< \brief (PMC_PCSR1) Peripheral Clock 47 Status */\r
+/* -------- PMC_OCR : (PMC Offset: 0x0110) Oscillator Calibration Register -------- */\r
+#define PMC_OCR_CAL4_Pos 0\r
+#define PMC_OCR_CAL4_Msk (0x7fu << PMC_OCR_CAL4_Pos) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 4 MHz */\r
+#define PMC_OCR_CAL4(value) ((PMC_OCR_CAL4_Msk & ((value) << PMC_OCR_CAL4_Pos)))\r
+#define PMC_OCR_SEL4 (0x1u << 7) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 4 MHz */\r
+#define PMC_OCR_CAL8_Pos 8\r
+#define PMC_OCR_CAL8_Msk (0x7fu << PMC_OCR_CAL8_Pos) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 8 MHz */\r
+#define PMC_OCR_CAL8(value) ((PMC_OCR_CAL8_Msk & ((value) << PMC_OCR_CAL8_Pos)))\r
+#define PMC_OCR_SEL8 (0x1u << 15) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 8 MHz */\r
+#define PMC_OCR_CAL12_Pos 16\r
+#define PMC_OCR_CAL12_Msk (0x7fu << PMC_OCR_CAL12_Pos) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 12 MHz */\r
+#define PMC_OCR_CAL12(value) ((PMC_OCR_CAL12_Msk & ((value) << PMC_OCR_CAL12_Pos)))\r
+#define PMC_OCR_SEL12 (0x1u << 23) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 12 MHz */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM4E_PMC_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4E_PWM_COMPONENT_\r
+#define _SAM4E_PWM_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM4E_PWM Pulse Width Modulation Controller */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief PwmCh_num hardware registers */\r
+typedef struct {\r
+ RwReg PWM_CMR; /**< \brief (PwmCh_num Offset: 0x0) PWM Channel Mode Register */\r
+ RwReg PWM_CDTY; /**< \brief (PwmCh_num Offset: 0x4) PWM Channel Duty Cycle Register */\r
+ RwReg PWM_CDTYUPD; /**< \brief (PwmCh_num Offset: 0x8) PWM Channel Duty Cycle Update Register */\r
+ RwReg PWM_CPRD; /**< \brief (PwmCh_num Offset: 0xC) PWM Channel Period Register */\r
+ RwReg PWM_CPRDUPD; /**< \brief (PwmCh_num Offset: 0x10) PWM Channel Period Update Register */\r
+ RwReg PWM_CCNT; /**< \brief (PwmCh_num Offset: 0x14) PWM Channel Counter Register */\r
+ RwReg PWM_DT; /**< \brief (PwmCh_num Offset: 0x18) PWM Channel Dead Time Register */\r
+ RwReg PWM_DTUPD; /**< \brief (PwmCh_num Offset: 0x1C) PWM Channel Dead Time Update Register */\r
+} PwmCh_num;\r
+/** \brief PwmCh_num_0x400 hardware registers */\r
+typedef struct {\r
+ RwReg PWM_CMUPD; /**< \brief (PwmCh_num_0x400 Offset: 0x0) PWM Channel Mode Update Register */\r
+ RwReg PWM_CAE; /**< \brief (PwmCh_num_0x400 Offset: 0x4) PWM Channel Additional Edge Register */\r
+ RwReg PWM_CAEUPD; /**< \brief (PwmCh_num_0x400 Offset: 0x8) PWM Channel Additional Edge Update Register */\r
+ RoReg Reserved1[5];\r
+} PwmCh_num_0x400;\r
+/** \brief PwmCmp hardware registers */\r
+typedef struct {\r
+ RwReg PWM_CMPV; /**< \brief (PwmCmp Offset: 0x0) PWM Comparison 0 Value Register */\r
+ RwReg PWM_CMPVUPD; /**< \brief (PwmCmp Offset: 0x4) PWM Comparison 0 Value Update Register */\r
+ RwReg PWM_CMPM; /**< \brief (PwmCmp Offset: 0x8) PWM Comparison 0 Mode Register */\r
+ RwReg PWM_CMPMUPD; /**< \brief (PwmCmp Offset: 0xC) PWM Comparison 0 Mode Update Register */\r
+} PwmCmp;\r
+/** \brief Pwm hardware registers */\r
+#define PWMCMP_NUMBER 8\r
+#define PWMCH_NUM_NUMBER 4\r
+#define PWMCH_NUM_0X400_NUMBER 4\r
+typedef struct {\r
+ RwReg PWM_CLK; /**< \brief (Pwm Offset: 0x00) PWM Clock Register */\r
+ WoReg PWM_ENA; /**< \brief (Pwm Offset: 0x04) PWM Enable Register */\r
+ WoReg PWM_DIS; /**< \brief (Pwm Offset: 0x08) PWM Disable Register */\r
+ RoReg PWM_SR; /**< \brief (Pwm Offset: 0x0C) PWM Status Register */\r
+ WoReg PWM_IER1; /**< \brief (Pwm Offset: 0x10) PWM Interrupt Enable Register 1 */\r
+ WoReg PWM_IDR1; /**< \brief (Pwm Offset: 0x14) PWM Interrupt Disable Register 1 */\r
+ RoReg PWM_IMR1; /**< \brief (Pwm Offset: 0x18) PWM Interrupt Mask Register 1 */\r
+ RoReg PWM_ISR1; /**< \brief (Pwm Offset: 0x1C) PWM Interrupt Status Register 1 */\r
+ RwReg PWM_SCM; /**< \brief (Pwm Offset: 0x20) PWM Sync Channels Mode Register */\r
+ RoReg Reserved1[1];\r
+ RwReg PWM_SCUC; /**< \brief (Pwm Offset: 0x28) PWM Sync Channels Update Control Register */\r
+ RwReg PWM_SCUP; /**< \brief (Pwm Offset: 0x2C) PWM Sync Channels Update Period Register */\r
+ WoReg PWM_SCUPUPD; /**< \brief (Pwm Offset: 0x30) PWM Sync Channels Update Period Update Register */\r
+ WoReg PWM_IER2; /**< \brief (Pwm Offset: 0x34) PWM Interrupt Enable Register 2 */\r
+ WoReg PWM_IDR2; /**< \brief (Pwm Offset: 0x38) PWM Interrupt Disable Register 2 */\r
+ RoReg PWM_IMR2; /**< \brief (Pwm Offset: 0x3C) PWM Interrupt Mask Register 2 */\r
+ RoReg PWM_ISR2; /**< \brief (Pwm Offset: 0x40) PWM Interrupt Status Register 2 */\r
+ RwReg PWM_OOV; /**< \brief (Pwm Offset: 0x44) PWM Output Override Value Register */\r
+ RwReg PWM_OS; /**< \brief (Pwm Offset: 0x48) PWM Output Selection Register */\r
+ WoReg PWM_OSS; /**< \brief (Pwm Offset: 0x4C) PWM Output Selection Set Register */\r
+ WoReg PWM_OSC; /**< \brief (Pwm Offset: 0x50) PWM Output Selection Clear Register */\r
+ WoReg PWM_OSSUPD; /**< \brief (Pwm Offset: 0x54) PWM Output Selection Set Update Register */\r
+ WoReg PWM_OSCUPD; /**< \brief (Pwm Offset: 0x58) PWM Output Selection Clear Update Register */\r
+ RwReg PWM_FMR; /**< \brief (Pwm Offset: 0x5C) PWM Fault Mode Register */\r
+ RoReg PWM_FSR; /**< \brief (Pwm Offset: 0x60) PWM Fault Status Register */\r
+ WoReg PWM_FCR; /**< \brief (Pwm Offset: 0x64) PWM Fault Clear Register */\r
+ RwReg PWM_FPV1; /**< \brief (Pwm Offset: 0x68) PWM Fault Protection Value Register 1 */\r
+ RwReg PWM_FPE; /**< \brief (Pwm Offset: 0x6C) PWM Fault Protection Enable Register */\r
+ RoReg Reserved2[3];\r
+ RwReg PWM_ELMR[2]; /**< \brief (Pwm Offset: 0x7C) PWM Event Line 0 Mode Register */\r
+ RoReg Reserved3[7];\r
+ RwReg PWM_SSPR; /**< \brief (Pwm Offset: 0xA0) PWM Spread Spectrum Register */\r
+ WoReg PWM_SSPUP; /**< \brief (Pwm Offset: 0xA4) PWM Spread Spectrum Update Register */\r
+ RoReg Reserved4[2];\r
+ RwReg PWM_SMMR; /**< \brief (Pwm Offset: 0xB0) PWM Stepper Motor Mode Register */\r
+ RoReg Reserved5[3];\r
+ RwReg PWM_FPV2; /**< \brief (Pwm Offset: 0xC0) PWM Fault Protection Value 2 Register */\r
+ RoReg Reserved6[8];\r
+ WoReg PWM_WPCR; /**< \brief (Pwm Offset: 0xE4) PWM Write Protect Control Register */\r
+ RoReg PWM_WPSR; /**< \brief (Pwm Offset: 0xE8) PWM Write Protect Status Register */\r
+ RoReg Reserved7[7];\r
+ RwReg PWM_TPR; /**< \brief (Pwm Offset: 0x108) Transmit Pointer Register */\r
+ RwReg PWM_TCR; /**< \brief (Pwm Offset: 0x10C) Transmit Counter Register */\r
+ RoReg Reserved8[2];\r
+ RwReg PWM_TNPR; /**< \brief (Pwm Offset: 0x118) Transmit Next Pointer Register */\r
+ RwReg PWM_TNCR; /**< \brief (Pwm Offset: 0x11C) Transmit Next Counter Register */\r
+ WoReg PWM_PTCR; /**< \brief (Pwm Offset: 0x120) Transfer Control Register */\r
+ RoReg PWM_PTSR; /**< \brief (Pwm Offset: 0x124) Transfer Status Register */\r
+ RoReg Reserved9[2];\r
+ PwmCmp PWM_CMP[PWMCMP_NUMBER]; /**< \brief (Pwm Offset: 0x130) 0 .. 7 */\r
+ RoReg Reserved10[20];\r
+ PwmCh_num PWM_CH_NUM[PWMCH_NUM_NUMBER]; /**< \brief (Pwm Offset: 0x200) ch_num = 0 .. 3 */\r
+ RoReg Reserved11[96];\r
+ PwmCh_num_0x400 PWM_CH_NUM_0X400[PWMCH_NUM_0X400_NUMBER]; /**< \brief (Pwm Offset: 0x400) ch_num = 0 .. 3 */\r
+} Pwm;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- PWM_CLK : (PWM Offset: 0x00) PWM Clock Register -------- */\r
+#define PWM_CLK_DIVA_Pos 0\r
+#define PWM_CLK_DIVA_Msk (0xffu << PWM_CLK_DIVA_Pos) /**< \brief (PWM_CLK) CLKA, CLKB Divide Factor */\r
+#define PWM_CLK_DIVA(value) ((PWM_CLK_DIVA_Msk & ((value) << PWM_CLK_DIVA_Pos)))\r
+#define PWM_CLK_PREA_Pos 8\r
+#define PWM_CLK_PREA_Msk (0xfu << PWM_CLK_PREA_Pos) /**< \brief (PWM_CLK) CLKA, CLKB Source Clock Selection */\r
+#define PWM_CLK_PREA(value) ((PWM_CLK_PREA_Msk & ((value) << PWM_CLK_PREA_Pos)))\r
+#define PWM_CLK_DIVB_Pos 16\r
+#define PWM_CLK_DIVB_Msk (0xffu << PWM_CLK_DIVB_Pos) /**< \brief (PWM_CLK) CLKA, CLKB Divide Factor */\r
+#define PWM_CLK_DIVB(value) ((PWM_CLK_DIVB_Msk & ((value) << PWM_CLK_DIVB_Pos)))\r
+#define PWM_CLK_PREB_Pos 24\r
+#define PWM_CLK_PREB_Msk (0xfu << PWM_CLK_PREB_Pos) /**< \brief (PWM_CLK) CLKA, CLKB Source Clock Selection */\r
+#define PWM_CLK_PREB(value) ((PWM_CLK_PREB_Msk & ((value) << PWM_CLK_PREB_Pos)))\r
+/* -------- PWM_ENA : (PWM Offset: 0x04) PWM Enable Register -------- */\r
+#define PWM_ENA_CHID0 (0x1u << 0) /**< \brief (PWM_ENA) Channel ID */\r
+#define PWM_ENA_CHID1 (0x1u << 1) /**< \brief (PWM_ENA) Channel ID */\r
+#define PWM_ENA_CHID2 (0x1u << 2) /**< \brief (PWM_ENA) Channel ID */\r
+#define PWM_ENA_CHID3 (0x1u << 3) /**< \brief (PWM_ENA) Channel ID */\r
+/* -------- PWM_DIS : (PWM Offset: 0x08) PWM Disable Register -------- */\r
+#define PWM_DIS_CHID0 (0x1u << 0) /**< \brief (PWM_DIS) Channel ID */\r
+#define PWM_DIS_CHID1 (0x1u << 1) /**< \brief (PWM_DIS) Channel ID */\r
+#define PWM_DIS_CHID2 (0x1u << 2) /**< \brief (PWM_DIS) Channel ID */\r
+#define PWM_DIS_CHID3 (0x1u << 3) /**< \brief (PWM_DIS) Channel ID */\r
+/* -------- PWM_SR : (PWM Offset: 0x0C) PWM Status Register -------- */\r
+#define PWM_SR_CHID0 (0x1u << 0) /**< \brief (PWM_SR) Channel ID */\r
+#define PWM_SR_CHID1 (0x1u << 1) /**< \brief (PWM_SR) Channel ID */\r
+#define PWM_SR_CHID2 (0x1u << 2) /**< \brief (PWM_SR) Channel ID */\r
+#define PWM_SR_CHID3 (0x1u << 3) /**< \brief (PWM_SR) Channel ID */\r
+/* -------- PWM_IER1 : (PWM Offset: 0x10) PWM Interrupt Enable Register 1 -------- */\r
+#define PWM_IER1_CHID0 (0x1u << 0) /**< \brief (PWM_IER1) Counter Event on Channel 0 Interrupt Enable */\r
+#define PWM_IER1_CHID1 (0x1u << 1) /**< \brief (PWM_IER1) Counter Event on Channel 1 Interrupt Enable */\r
+#define PWM_IER1_CHID2 (0x1u << 2) /**< \brief (PWM_IER1) Counter Event on Channel 2 Interrupt Enable */\r
+#define PWM_IER1_CHID3 (0x1u << 3) /**< \brief (PWM_IER1) Counter Event on Channel 3 Interrupt Enable */\r
+#define PWM_IER1_FCHID0 (0x1u << 16) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 0 Interrupt Enable */\r
+#define PWM_IER1_FCHID1 (0x1u << 17) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 1 Interrupt Enable */\r
+#define PWM_IER1_FCHID2 (0x1u << 18) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 2 Interrupt Enable */\r
+#define PWM_IER1_FCHID3 (0x1u << 19) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 3 Interrupt Enable */\r
+/* -------- PWM_IDR1 : (PWM Offset: 0x14) PWM Interrupt Disable Register 1 -------- */\r
+#define PWM_IDR1_CHID0 (0x1u << 0) /**< \brief (PWM_IDR1) Counter Event on Channel 0 Interrupt Disable */\r
+#define PWM_IDR1_CHID1 (0x1u << 1) /**< \brief (PWM_IDR1) Counter Event on Channel 1 Interrupt Disable */\r
+#define PWM_IDR1_CHID2 (0x1u << 2) /**< \brief (PWM_IDR1) Counter Event on Channel 2 Interrupt Disable */\r
+#define PWM_IDR1_CHID3 (0x1u << 3) /**< \brief (PWM_IDR1) Counter Event on Channel 3 Interrupt Disable */\r
+#define PWM_IDR1_FCHID0 (0x1u << 16) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 0 Interrupt Disable */\r
+#define PWM_IDR1_FCHID1 (0x1u << 17) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 1 Interrupt Disable */\r
+#define PWM_IDR1_FCHID2 (0x1u << 18) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 2 Interrupt Disable */\r
+#define PWM_IDR1_FCHID3 (0x1u << 19) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 3 Interrupt Disable */\r
+/* -------- PWM_IMR1 : (PWM Offset: 0x18) PWM Interrupt Mask Register 1 -------- */\r
+#define PWM_IMR1_CHID0 (0x1u << 0) /**< \brief (PWM_IMR1) Counter Event on Channel 0 Interrupt Mask */\r
+#define PWM_IMR1_CHID1 (0x1u << 1) /**< \brief (PWM_IMR1) Counter Event on Channel 1 Interrupt Mask */\r
+#define PWM_IMR1_CHID2 (0x1u << 2) /**< \brief (PWM_IMR1) Counter Event on Channel 2 Interrupt Mask */\r
+#define PWM_IMR1_CHID3 (0x1u << 3) /**< \brief (PWM_IMR1) Counter Event on Channel 3 Interrupt Mask */\r
+#define PWM_IMR1_FCHID0 (0x1u << 16) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 0 Interrupt Mask */\r
+#define PWM_IMR1_FCHID1 (0x1u << 17) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 1 Interrupt Mask */\r
+#define PWM_IMR1_FCHID2 (0x1u << 18) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 2 Interrupt Mask */\r
+#define PWM_IMR1_FCHID3 (0x1u << 19) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 3 Interrupt Mask */\r
+/* -------- PWM_ISR1 : (PWM Offset: 0x1C) PWM Interrupt Status Register 1 -------- */\r
+#define PWM_ISR1_CHID0 (0x1u << 0) /**< \brief (PWM_ISR1) Counter Event on Channel 0 */\r
+#define PWM_ISR1_CHID1 (0x1u << 1) /**< \brief (PWM_ISR1) Counter Event on Channel 1 */\r
+#define PWM_ISR1_CHID2 (0x1u << 2) /**< \brief (PWM_ISR1) Counter Event on Channel 2 */\r
+#define PWM_ISR1_CHID3 (0x1u << 3) /**< \brief (PWM_ISR1) Counter Event on Channel 3 */\r
+#define PWM_ISR1_FCHID0 (0x1u << 16) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 0 */\r
+#define PWM_ISR1_FCHID1 (0x1u << 17) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 1 */\r
+#define PWM_ISR1_FCHID2 (0x1u << 18) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 2 */\r
+#define PWM_ISR1_FCHID3 (0x1u << 19) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 3 */\r
+/* -------- PWM_SCM : (PWM Offset: 0x20) PWM Sync Channels Mode Register -------- */\r
+#define PWM_SCM_SYNC0 (0x1u << 0) /**< \brief (PWM_SCM) Synchronous Channel 0 */\r
+#define PWM_SCM_SYNC1 (0x1u << 1) /**< \brief (PWM_SCM) Synchronous Channel 1 */\r
+#define PWM_SCM_SYNC2 (0x1u << 2) /**< \brief (PWM_SCM) Synchronous Channel 2 */\r
+#define PWM_SCM_SYNC3 (0x1u << 3) /**< \brief (PWM_SCM) Synchronous Channel 3 */\r
+#define PWM_SCM_UPDM_Pos 16\r
+#define PWM_SCM_UPDM_Msk (0x3u << PWM_SCM_UPDM_Pos) /**< \brief (PWM_SCM) Synchronous Channels Update Mode */\r
+#define PWM_SCM_UPDM_MODE0 (0x0u << 16) /**< \brief (PWM_SCM) Manual write of double buffer registers and manual update of synchronous channels */\r
+#define PWM_SCM_UPDM_MODE1 (0x1u << 16) /**< \brief (PWM_SCM) Manual write of double buffer registers and automatic update of synchronous channels */\r
+#define PWM_SCM_UPDM_MODE2 (0x2u << 16) /**< \brief (PWM_SCM) Automatic write of duty-cycle update registers by the PDC and automatic update of synchronous channels */\r
+#define PWM_SCM_PTRM (0x1u << 20) /**< \brief (PWM_SCM) PDC Transfer Request Mode */\r
+#define PWM_SCM_PTRCS_Pos 21\r
+#define PWM_SCM_PTRCS_Msk (0x7u << PWM_SCM_PTRCS_Pos) /**< \brief (PWM_SCM) PDC Transfer Request Comparison Selection */\r
+#define PWM_SCM_PTRCS(value) ((PWM_SCM_PTRCS_Msk & ((value) << PWM_SCM_PTRCS_Pos)))\r
+/* -------- PWM_SCUC : (PWM Offset: 0x28) PWM Sync Channels Update Control Register -------- */\r
+#define PWM_SCUC_UPDULOCK (0x1u << 0) /**< \brief (PWM_SCUC) Synchronous Channels Update Unlock */\r
+/* -------- PWM_SCUP : (PWM Offset: 0x2C) PWM Sync Channels Update Period Register -------- */\r
+#define PWM_SCUP_UPR_Pos 0\r
+#define PWM_SCUP_UPR_Msk (0xfu << PWM_SCUP_UPR_Pos) /**< \brief (PWM_SCUP) Update Period */\r
+#define PWM_SCUP_UPR(value) ((PWM_SCUP_UPR_Msk & ((value) << PWM_SCUP_UPR_Pos)))\r
+#define PWM_SCUP_UPRCNT_Pos 4\r
+#define PWM_SCUP_UPRCNT_Msk (0xfu << PWM_SCUP_UPRCNT_Pos) /**< \brief (PWM_SCUP) Update Period Counter */\r
+#define PWM_SCUP_UPRCNT(value) ((PWM_SCUP_UPRCNT_Msk & ((value) << PWM_SCUP_UPRCNT_Pos)))\r
+/* -------- PWM_SCUPUPD : (PWM Offset: 0x30) PWM Sync Channels Update Period Update Register -------- */\r
+#define PWM_SCUPUPD_UPRUPD_Pos 0\r
+#define PWM_SCUPUPD_UPRUPD_Msk (0xfu << PWM_SCUPUPD_UPRUPD_Pos) /**< \brief (PWM_SCUPUPD) Update Period Update */\r
+#define PWM_SCUPUPD_UPRUPD(value) ((PWM_SCUPUPD_UPRUPD_Msk & ((value) << PWM_SCUPUPD_UPRUPD_Pos)))\r
+/* -------- PWM_IER2 : (PWM Offset: 0x34) PWM Interrupt Enable Register 2 -------- */\r
+#define PWM_IER2_WRDY (0x1u << 0) /**< \brief (PWM_IER2) Write Ready for Synchronous Channels Update Interrupt Enable */\r
+#define PWM_IER2_ENDTX (0x1u << 1) /**< \brief (PWM_IER2) PDC End of TX Buffer Interrupt Enable */\r
+#define PWM_IER2_TXBUFE (0x1u << 2) /**< \brief (PWM_IER2) PDC TX Buffer Empty Interrupt Enable */\r
+#define PWM_IER2_UNRE (0x1u << 3) /**< \brief (PWM_IER2) Synchronous Channels Update Underrun Error Interrupt Enable */\r
+#define PWM_IER2_CMPM0 (0x1u << 8) /**< \brief (PWM_IER2) Comparison 0 Match Interrupt Enable */\r
+#define PWM_IER2_CMPM1 (0x1u << 9) /**< \brief (PWM_IER2) Comparison 1 Match Interrupt Enable */\r
+#define PWM_IER2_CMPM2 (0x1u << 10) /**< \brief (PWM_IER2) Comparison 2 Match Interrupt Enable */\r
+#define PWM_IER2_CMPM3 (0x1u << 11) /**< \brief (PWM_IER2) Comparison 3 Match Interrupt Enable */\r
+#define PWM_IER2_CMPM4 (0x1u << 12) /**< \brief (PWM_IER2) Comparison 4 Match Interrupt Enable */\r
+#define PWM_IER2_CMPM5 (0x1u << 13) /**< \brief (PWM_IER2) Comparison 5 Match Interrupt Enable */\r
+#define PWM_IER2_CMPM6 (0x1u << 14) /**< \brief (PWM_IER2) Comparison 6 Match Interrupt Enable */\r
+#define PWM_IER2_CMPM7 (0x1u << 15) /**< \brief (PWM_IER2) Comparison 7 Match Interrupt Enable */\r
+#define PWM_IER2_CMPU0 (0x1u << 16) /**< \brief (PWM_IER2) Comparison 0 Update Interrupt Enable */\r
+#define PWM_IER2_CMPU1 (0x1u << 17) /**< \brief (PWM_IER2) Comparison 1 Update Interrupt Enable */\r
+#define PWM_IER2_CMPU2 (0x1u << 18) /**< \brief (PWM_IER2) Comparison 2 Update Interrupt Enable */\r
+#define PWM_IER2_CMPU3 (0x1u << 19) /**< \brief (PWM_IER2) Comparison 3 Update Interrupt Enable */\r
+#define PWM_IER2_CMPU4 (0x1u << 20) /**< \brief (PWM_IER2) Comparison 4 Update Interrupt Enable */\r
+#define PWM_IER2_CMPU5 (0x1u << 21) /**< \brief (PWM_IER2) Comparison 5 Update Interrupt Enable */\r
+#define PWM_IER2_CMPU6 (0x1u << 22) /**< \brief (PWM_IER2) Comparison 6 Update Interrupt Enable */\r
+#define PWM_IER2_CMPU7 (0x1u << 23) /**< \brief (PWM_IER2) Comparison 7 Update Interrupt Enable */\r
+/* -------- PWM_IDR2 : (PWM Offset: 0x38) PWM Interrupt Disable Register 2 -------- */\r
+#define PWM_IDR2_WRDY (0x1u << 0) /**< \brief (PWM_IDR2) Write Ready for Synchronous Channels Update Interrupt Disable */\r
+#define PWM_IDR2_ENDTX (0x1u << 1) /**< \brief (PWM_IDR2) PDC End of TX Buffer Interrupt Disable */\r
+#define PWM_IDR2_TXBUFE (0x1u << 2) /**< \brief (PWM_IDR2) PDC TX Buffer Empty Interrupt Disable */\r
+#define PWM_IDR2_UNRE (0x1u << 3) /**< \brief (PWM_IDR2) Synchronous Channels Update Underrun Error Interrupt Disable */\r
+#define PWM_IDR2_CMPM0 (0x1u << 8) /**< \brief (PWM_IDR2) Comparison 0 Match Interrupt Disable */\r
+#define PWM_IDR2_CMPM1 (0x1u << 9) /**< \brief (PWM_IDR2) Comparison 1 Match Interrupt Disable */\r
+#define PWM_IDR2_CMPM2 (0x1u << 10) /**< \brief (PWM_IDR2) Comparison 2 Match Interrupt Disable */\r
+#define PWM_IDR2_CMPM3 (0x1u << 11) /**< \brief (PWM_IDR2) Comparison 3 Match Interrupt Disable */\r
+#define PWM_IDR2_CMPM4 (0x1u << 12) /**< \brief (PWM_IDR2) Comparison 4 Match Interrupt Disable */\r
+#define PWM_IDR2_CMPM5 (0x1u << 13) /**< \brief (PWM_IDR2) Comparison 5 Match Interrupt Disable */\r
+#define PWM_IDR2_CMPM6 (0x1u << 14) /**< \brief (PWM_IDR2) Comparison 6 Match Interrupt Disable */\r
+#define PWM_IDR2_CMPM7 (0x1u << 15) /**< \brief (PWM_IDR2) Comparison 7 Match Interrupt Disable */\r
+#define PWM_IDR2_CMPU0 (0x1u << 16) /**< \brief (PWM_IDR2) Comparison 0 Update Interrupt Disable */\r
+#define PWM_IDR2_CMPU1 (0x1u << 17) /**< \brief (PWM_IDR2) Comparison 1 Update Interrupt Disable */\r
+#define PWM_IDR2_CMPU2 (0x1u << 18) /**< \brief (PWM_IDR2) Comparison 2 Update Interrupt Disable */\r
+#define PWM_IDR2_CMPU3 (0x1u << 19) /**< \brief (PWM_IDR2) Comparison 3 Update Interrupt Disable */\r
+#define PWM_IDR2_CMPU4 (0x1u << 20) /**< \brief (PWM_IDR2) Comparison 4 Update Interrupt Disable */\r
+#define PWM_IDR2_CMPU5 (0x1u << 21) /**< \brief (PWM_IDR2) Comparison 5 Update Interrupt Disable */\r
+#define PWM_IDR2_CMPU6 (0x1u << 22) /**< \brief (PWM_IDR2) Comparison 6 Update Interrupt Disable */\r
+#define PWM_IDR2_CMPU7 (0x1u << 23) /**< \brief (PWM_IDR2) Comparison 7 Update Interrupt Disable */\r
+/* -------- PWM_IMR2 : (PWM Offset: 0x3C) PWM Interrupt Mask Register 2 -------- */\r
+#define PWM_IMR2_WRDY (0x1u << 0) /**< \brief (PWM_IMR2) Write Ready for Synchronous Channels Update Interrupt Mask */\r
+#define PWM_IMR2_ENDTX (0x1u << 1) /**< \brief (PWM_IMR2) PDC End of TX Buffer Interrupt Mask */\r
+#define PWM_IMR2_TXBUFE (0x1u << 2) /**< \brief (PWM_IMR2) PDC TX Buffer Empty Interrupt Mask */\r
+#define PWM_IMR2_UNRE (0x1u << 3) /**< \brief (PWM_IMR2) Synchronous Channels Update Underrun Error Interrupt Mask */\r
+#define PWM_IMR2_CMPM0 (0x1u << 8) /**< \brief (PWM_IMR2) Comparison 0 Match Interrupt Mask */\r
+#define PWM_IMR2_CMPM1 (0x1u << 9) /**< \brief (PWM_IMR2) Comparison 1 Match Interrupt Mask */\r
+#define PWM_IMR2_CMPM2 (0x1u << 10) /**< \brief (PWM_IMR2) Comparison 2 Match Interrupt Mask */\r
+#define PWM_IMR2_CMPM3 (0x1u << 11) /**< \brief (PWM_IMR2) Comparison 3 Match Interrupt Mask */\r
+#define PWM_IMR2_CMPM4 (0x1u << 12) /**< \brief (PWM_IMR2) Comparison 4 Match Interrupt Mask */\r
+#define PWM_IMR2_CMPM5 (0x1u << 13) /**< \brief (PWM_IMR2) Comparison 5 Match Interrupt Mask */\r
+#define PWM_IMR2_CMPM6 (0x1u << 14) /**< \brief (PWM_IMR2) Comparison 6 Match Interrupt Mask */\r
+#define PWM_IMR2_CMPM7 (0x1u << 15) /**< \brief (PWM_IMR2) Comparison 7 Match Interrupt Mask */\r
+#define PWM_IMR2_CMPU0 (0x1u << 16) /**< \brief (PWM_IMR2) Comparison 0 Update Interrupt Mask */\r
+#define PWM_IMR2_CMPU1 (0x1u << 17) /**< \brief (PWM_IMR2) Comparison 1 Update Interrupt Mask */\r
+#define PWM_IMR2_CMPU2 (0x1u << 18) /**< \brief (PWM_IMR2) Comparison 2 Update Interrupt Mask */\r
+#define PWM_IMR2_CMPU3 (0x1u << 19) /**< \brief (PWM_IMR2) Comparison 3 Update Interrupt Mask */\r
+#define PWM_IMR2_CMPU4 (0x1u << 20) /**< \brief (PWM_IMR2) Comparison 4 Update Interrupt Mask */\r
+#define PWM_IMR2_CMPU5 (0x1u << 21) /**< \brief (PWM_IMR2) Comparison 5 Update Interrupt Mask */\r
+#define PWM_IMR2_CMPU6 (0x1u << 22) /**< \brief (PWM_IMR2) Comparison 6 Update Interrupt Mask */\r
+#define PWM_IMR2_CMPU7 (0x1u << 23) /**< \brief (PWM_IMR2) Comparison 7 Update Interrupt Mask */\r
+/* -------- PWM_ISR2 : (PWM Offset: 0x40) PWM Interrupt Status Register 2 -------- */\r
+#define PWM_ISR2_WRDY (0x1u << 0) /**< \brief (PWM_ISR2) Write Ready for Synchronous Channels Update */\r
+#define PWM_ISR2_ENDTX (0x1u << 1) /**< \brief (PWM_ISR2) PDC End of TX Buffer */\r
+#define PWM_ISR2_TXBUFE (0x1u << 2) /**< \brief (PWM_ISR2) PDC TX Buffer Empty */\r
+#define PWM_ISR2_UNRE (0x1u << 3) /**< \brief (PWM_ISR2) Synchronous Channels Update Underrun Error */\r
+#define PWM_ISR2_CMPM0 (0x1u << 8) /**< \brief (PWM_ISR2) Comparison 0 Match */\r
+#define PWM_ISR2_CMPM1 (0x1u << 9) /**< \brief (PWM_ISR2) Comparison 1 Match */\r
+#define PWM_ISR2_CMPM2 (0x1u << 10) /**< \brief (PWM_ISR2) Comparison 2 Match */\r
+#define PWM_ISR2_CMPM3 (0x1u << 11) /**< \brief (PWM_ISR2) Comparison 3 Match */\r
+#define PWM_ISR2_CMPM4 (0x1u << 12) /**< \brief (PWM_ISR2) Comparison 4 Match */\r
+#define PWM_ISR2_CMPM5 (0x1u << 13) /**< \brief (PWM_ISR2) Comparison 5 Match */\r
+#define PWM_ISR2_CMPM6 (0x1u << 14) /**< \brief (PWM_ISR2) Comparison 6 Match */\r
+#define PWM_ISR2_CMPM7 (0x1u << 15) /**< \brief (PWM_ISR2) Comparison 7 Match */\r
+#define PWM_ISR2_CMPU0 (0x1u << 16) /**< \brief (PWM_ISR2) Comparison 0 Update */\r
+#define PWM_ISR2_CMPU1 (0x1u << 17) /**< \brief (PWM_ISR2) Comparison 1 Update */\r
+#define PWM_ISR2_CMPU2 (0x1u << 18) /**< \brief (PWM_ISR2) Comparison 2 Update */\r
+#define PWM_ISR2_CMPU3 (0x1u << 19) /**< \brief (PWM_ISR2) Comparison 3 Update */\r
+#define PWM_ISR2_CMPU4 (0x1u << 20) /**< \brief (PWM_ISR2) Comparison 4 Update */\r
+#define PWM_ISR2_CMPU5 (0x1u << 21) /**< \brief (PWM_ISR2) Comparison 5 Update */\r
+#define PWM_ISR2_CMPU6 (0x1u << 22) /**< \brief (PWM_ISR2) Comparison 6 Update */\r
+#define PWM_ISR2_CMPU7 (0x1u << 23) /**< \brief (PWM_ISR2) Comparison 7 Update */\r
+/* -------- PWM_OOV : (PWM Offset: 0x44) PWM Output Override Value Register -------- */\r
+#define PWM_OOV_OOVH0 (0x1u << 0) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 0 */\r
+#define PWM_OOV_OOVH1 (0x1u << 1) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 1 */\r
+#define PWM_OOV_OOVH2 (0x1u << 2) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 2 */\r
+#define PWM_OOV_OOVH3 (0x1u << 3) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 3 */\r
+#define PWM_OOV_OOVL0 (0x1u << 16) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 0 */\r
+#define PWM_OOV_OOVL1 (0x1u << 17) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 1 */\r
+#define PWM_OOV_OOVL2 (0x1u << 18) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 2 */\r
+#define PWM_OOV_OOVL3 (0x1u << 19) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 3 */\r
+/* -------- PWM_OS : (PWM Offset: 0x48) PWM Output Selection Register -------- */\r
+#define PWM_OS_OSH0 (0x1u << 0) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 0 */\r
+#define PWM_OS_OSH1 (0x1u << 1) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 1 */\r
+#define PWM_OS_OSH2 (0x1u << 2) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 2 */\r
+#define PWM_OS_OSH3 (0x1u << 3) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 3 */\r
+#define PWM_OS_OSL0 (0x1u << 16) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 0 */\r
+#define PWM_OS_OSL1 (0x1u << 17) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 1 */\r
+#define PWM_OS_OSL2 (0x1u << 18) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 2 */\r
+#define PWM_OS_OSL3 (0x1u << 19) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 3 */\r
+/* -------- PWM_OSS : (PWM Offset: 0x4C) PWM Output Selection Set Register -------- */\r
+#define PWM_OSS_OSSH0 (0x1u << 0) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 0 */\r
+#define PWM_OSS_OSSH1 (0x1u << 1) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 1 */\r
+#define PWM_OSS_OSSH2 (0x1u << 2) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 2 */\r
+#define PWM_OSS_OSSH3 (0x1u << 3) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 3 */\r
+#define PWM_OSS_OSSL0 (0x1u << 16) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 0 */\r
+#define PWM_OSS_OSSL1 (0x1u << 17) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 1 */\r
+#define PWM_OSS_OSSL2 (0x1u << 18) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 2 */\r
+#define PWM_OSS_OSSL3 (0x1u << 19) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 3 */\r
+/* -------- PWM_OSC : (PWM Offset: 0x50) PWM Output Selection Clear Register -------- */\r
+#define PWM_OSC_OSCH0 (0x1u << 0) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 0 */\r
+#define PWM_OSC_OSCH1 (0x1u << 1) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 1 */\r
+#define PWM_OSC_OSCH2 (0x1u << 2) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 2 */\r
+#define PWM_OSC_OSCH3 (0x1u << 3) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 3 */\r
+#define PWM_OSC_OSCL0 (0x1u << 16) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 0 */\r
+#define PWM_OSC_OSCL1 (0x1u << 17) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 1 */\r
+#define PWM_OSC_OSCL2 (0x1u << 18) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 2 */\r
+#define PWM_OSC_OSCL3 (0x1u << 19) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 3 */\r
+/* -------- PWM_OSSUPD : (PWM Offset: 0x54) PWM Output Selection Set Update Register -------- */\r
+#define PWM_OSSUPD_OSSUPH0 (0x1u << 0) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 0 */\r
+#define PWM_OSSUPD_OSSUPH1 (0x1u << 1) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 1 */\r
+#define PWM_OSSUPD_OSSUPH2 (0x1u << 2) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 2 */\r
+#define PWM_OSSUPD_OSSUPH3 (0x1u << 3) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 3 */\r
+#define PWM_OSSUPD_OSSUPL0 (0x1u << 16) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 0 */\r
+#define PWM_OSSUPD_OSSUPL1 (0x1u << 17) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 1 */\r
+#define PWM_OSSUPD_OSSUPL2 (0x1u << 18) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 2 */\r
+#define PWM_OSSUPD_OSSUPL3 (0x1u << 19) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 3 */\r
+/* -------- PWM_OSCUPD : (PWM Offset: 0x58) PWM Output Selection Clear Update Register -------- */\r
+#define PWM_OSCUPD_OSCUPH0 (0x1u << 0) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 0 */\r
+#define PWM_OSCUPD_OSCUPH1 (0x1u << 1) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 1 */\r
+#define PWM_OSCUPD_OSCUPH2 (0x1u << 2) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 2 */\r
+#define PWM_OSCUPD_OSCUPH3 (0x1u << 3) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 3 */\r
+#define PWM_OSCUPD_OSCUPL0 (0x1u << 16) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 0 */\r
+#define PWM_OSCUPD_OSCUPL1 (0x1u << 17) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 1 */\r
+#define PWM_OSCUPD_OSCUPL2 (0x1u << 18) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 2 */\r
+#define PWM_OSCUPD_OSCUPL3 (0x1u << 19) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 3 */\r
+/* -------- PWM_FMR : (PWM Offset: 0x5C) PWM Fault Mode Register -------- */\r
+#define PWM_FMR_FPOL_Pos 0\r
+#define PWM_FMR_FPOL_Msk (0xffu << PWM_FMR_FPOL_Pos) /**< \brief (PWM_FMR) Fault Polarity (fault input bit varies from 0 to 7) */\r
+#define PWM_FMR_FPOL(value) ((PWM_FMR_FPOL_Msk & ((value) << PWM_FMR_FPOL_Pos)))\r
+#define PWM_FMR_FMOD_Pos 8\r
+#define PWM_FMR_FMOD_Msk (0xffu << PWM_FMR_FMOD_Pos) /**< \brief (PWM_FMR) Fault Activation Mode (fault input bit varies from 0 to 7) */\r
+#define PWM_FMR_FMOD(value) ((PWM_FMR_FMOD_Msk & ((value) << PWM_FMR_FMOD_Pos)))\r
+#define PWM_FMR_FFIL_Pos 16\r
+#define PWM_FMR_FFIL_Msk (0xffu << PWM_FMR_FFIL_Pos) /**< \brief (PWM_FMR) Fault Filtering (fault input bit varies from 0 to 7) */\r
+#define PWM_FMR_FFIL(value) ((PWM_FMR_FFIL_Msk & ((value) << PWM_FMR_FFIL_Pos)))\r
+/* -------- PWM_FSR : (PWM Offset: 0x60) PWM Fault Status Register -------- */\r
+#define PWM_FSR_FIV_Pos 0\r
+#define PWM_FSR_FIV_Msk (0xffu << PWM_FSR_FIV_Pos) /**< \brief (PWM_FSR) Fault Input Value (fault input bit varies from 0 to 7) */\r
+#define PWM_FSR_FS_Pos 8\r
+#define PWM_FSR_FS_Msk (0xffu << PWM_FSR_FS_Pos) /**< \brief (PWM_FSR) Fault Status (fault input bit varies from 0 to 7) */\r
+/* -------- PWM_FCR : (PWM Offset: 0x64) PWM Fault Clear Register -------- */\r
+#define PWM_FCR_FCLR_Pos 0\r
+#define PWM_FCR_FCLR_Msk (0xffu << PWM_FCR_FCLR_Pos) /**< \brief (PWM_FCR) Fault Clear (fault input bit varies from 0 to 7) */\r
+#define PWM_FCR_FCLR(value) ((PWM_FCR_FCLR_Msk & ((value) << PWM_FCR_FCLR_Pos)))\r
+/* -------- PWM_FPV1 : (PWM Offset: 0x68) PWM Fault Protection Value Register 1 -------- */\r
+#define PWM_FPV1_FPVH0 (0x1u << 0) /**< \brief (PWM_FPV1) Fault Protection Value for PWMH output on channel 0 */\r
+#define PWM_FPV1_FPVH1 (0x1u << 1) /**< \brief (PWM_FPV1) Fault Protection Value for PWMH output on channel 1 */\r
+#define PWM_FPV1_FPVH2 (0x1u << 2) /**< \brief (PWM_FPV1) Fault Protection Value for PWMH output on channel 2 */\r
+#define PWM_FPV1_FPVH3 (0x1u << 3) /**< \brief (PWM_FPV1) Fault Protection Value for PWMH output on channel 3 */\r
+#define PWM_FPV1_FPVL0 (0x1u << 16) /**< \brief (PWM_FPV1) Fault Protection Value for PWML output on channel 0 */\r
+#define PWM_FPV1_FPVL1 (0x1u << 17) /**< \brief (PWM_FPV1) Fault Protection Value for PWML output on channel 1 */\r
+#define PWM_FPV1_FPVL2 (0x1u << 18) /**< \brief (PWM_FPV1) Fault Protection Value for PWML output on channel 2 */\r
+#define PWM_FPV1_FPVL3 (0x1u << 19) /**< \brief (PWM_FPV1) Fault Protection Value for PWML output on channel 3 */\r
+/* -------- PWM_FPE : (PWM Offset: 0x6C) PWM Fault Protection Enable Register -------- */\r
+#define PWM_FPE_FPE0_Pos 0\r
+#define PWM_FPE_FPE0_Msk (0xffu << PWM_FPE_FPE0_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 0 (fault input bit varies from 0 to 7) */\r
+#define PWM_FPE_FPE0(value) ((PWM_FPE_FPE0_Msk & ((value) << PWM_FPE_FPE0_Pos)))\r
+#define PWM_FPE_FPE1_Pos 8\r
+#define PWM_FPE_FPE1_Msk (0xffu << PWM_FPE_FPE1_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 1 (fault input bit varies from 0 to 7) */\r
+#define PWM_FPE_FPE1(value) ((PWM_FPE_FPE1_Msk & ((value) << PWM_FPE_FPE1_Pos)))\r
+#define PWM_FPE_FPE2_Pos 16\r
+#define PWM_FPE_FPE2_Msk (0xffu << PWM_FPE_FPE2_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 2 (fault input bit varies from 0 to 7) */\r
+#define PWM_FPE_FPE2(value) ((PWM_FPE_FPE2_Msk & ((value) << PWM_FPE_FPE2_Pos)))\r
+#define PWM_FPE_FPE3_Pos 24\r
+#define PWM_FPE_FPE3_Msk (0xffu << PWM_FPE_FPE3_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 3 (fault input bit varies from 0 to 7) */\r
+#define PWM_FPE_FPE3(value) ((PWM_FPE_FPE3_Msk & ((value) << PWM_FPE_FPE3_Pos)))\r
+/* -------- PWM_ELMR[2] : (PWM Offset: 0x7C) PWM Event Line 0 Mode Register -------- */\r
+#define PWM_ELMR_CSEL0 (0x1u << 0) /**< \brief (PWM_ELMR[2]) Comparison 0 Selection */\r
+#define PWM_ELMR_CSEL1 (0x1u << 1) /**< \brief (PWM_ELMR[2]) Comparison 1 Selection */\r
+#define PWM_ELMR_CSEL2 (0x1u << 2) /**< \brief (PWM_ELMR[2]) Comparison 2 Selection */\r
+#define PWM_ELMR_CSEL3 (0x1u << 3) /**< \brief (PWM_ELMR[2]) Comparison 3 Selection */\r
+#define PWM_ELMR_CSEL4 (0x1u << 4) /**< \brief (PWM_ELMR[2]) Comparison 4 Selection */\r
+#define PWM_ELMR_CSEL5 (0x1u << 5) /**< \brief (PWM_ELMR[2]) Comparison 5 Selection */\r
+#define PWM_ELMR_CSEL6 (0x1u << 6) /**< \brief (PWM_ELMR[2]) Comparison 6 Selection */\r
+#define PWM_ELMR_CSEL7 (0x1u << 7) /**< \brief (PWM_ELMR[2]) Comparison 7 Selection */\r
+/* -------- PWM_SSPR : (PWM Offset: 0xA0) PWM Spread Spectrum Register -------- */\r
+#define PWM_SSPR_SPRD_Pos 0\r
+#define PWM_SSPR_SPRD_Msk (0xffffffu << PWM_SSPR_SPRD_Pos) /**< \brief (PWM_SSPR) Spread Spectrum Limit Value */\r
+#define PWM_SSPR_SPRD(value) ((PWM_SSPR_SPRD_Msk & ((value) << PWM_SSPR_SPRD_Pos)))\r
+#define PWM_SSPR_SPRDM (0x1u << 24) /**< \brief (PWM_SSPR) Spread Spectrum Counter Mode */\r
+/* -------- PWM_SSPUP : (PWM Offset: 0xA4) PWM Spread Spectrum Update Register -------- */\r
+#define PWM_SSPUP_SPRDUP_Pos 0\r
+#define PWM_SSPUP_SPRDUP_Msk (0xffffffu << PWM_SSPUP_SPRDUP_Pos) /**< \brief (PWM_SSPUP) Spread Spectrum Limit Value Update */\r
+#define PWM_SSPUP_SPRDUP(value) ((PWM_SSPUP_SPRDUP_Msk & ((value) << PWM_SSPUP_SPRDUP_Pos)))\r
+/* -------- PWM_SMMR : (PWM Offset: 0xB0) PWM Stepper Motor Mode Register -------- */\r
+#define PWM_SMMR_GCEN0 (0x1u << 0) /**< \brief (PWM_SMMR) Gray Count ENable */\r
+#define PWM_SMMR_GCEN1 (0x1u << 1) /**< \brief (PWM_SMMR) Gray Count ENable */\r
+#define PWM_SMMR_DOWN0 (0x1u << 16) /**< \brief (PWM_SMMR) DOWN Count */\r
+#define PWM_SMMR_DOWN1 (0x1u << 17) /**< \brief (PWM_SMMR) DOWN Count */\r
+/* -------- PWM_FPV2 : (PWM Offset: 0xC0) PWM Fault Protection Value 2 Register -------- */\r
+#define PWM_FPV2_FPZH0 (0x1u << 0) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWMH output on channel 0 */\r
+#define PWM_FPV2_FPZH1 (0x1u << 1) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWMH output on channel 1 */\r
+#define PWM_FPV2_FPZH2 (0x1u << 2) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWMH output on channel 2 */\r
+#define PWM_FPV2_FPZH3 (0x1u << 3) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWMH output on channel 3 */\r
+#define PWM_FPV2_FPZL0 (0x1u << 16) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWML output on channel 0 */\r
+#define PWM_FPV2_FPZL1 (0x1u << 17) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWML output on channel 1 */\r
+#define PWM_FPV2_FPZL2 (0x1u << 18) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWML output on channel 2 */\r
+#define PWM_FPV2_FPZL3 (0x1u << 19) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWML output on channel 3 */\r
+/* -------- PWM_WPCR : (PWM Offset: 0xE4) PWM Write Protect Control Register -------- */\r
+#define PWM_WPCR_WPCMD_Pos 0\r
+#define PWM_WPCR_WPCMD_Msk (0x3u << PWM_WPCR_WPCMD_Pos) /**< \brief (PWM_WPCR) Write Protect Command */\r
+#define PWM_WPCR_WPCMD(value) ((PWM_WPCR_WPCMD_Msk & ((value) << PWM_WPCR_WPCMD_Pos)))\r
+#define PWM_WPCR_WPRG0 (0x1u << 2) /**< \brief (PWM_WPCR) Write Protect Register Group 0 */\r
+#define PWM_WPCR_WPRG1 (0x1u << 3) /**< \brief (PWM_WPCR) Write Protect Register Group 1 */\r
+#define PWM_WPCR_WPRG2 (0x1u << 4) /**< \brief (PWM_WPCR) Write Protect Register Group 2 */\r
+#define PWM_WPCR_WPRG3 (0x1u << 5) /**< \brief (PWM_WPCR) Write Protect Register Group 3 */\r
+#define PWM_WPCR_WPRG4 (0x1u << 6) /**< \brief (PWM_WPCR) Write Protect Register Group 4 */\r
+#define PWM_WPCR_WPRG5 (0x1u << 7) /**< \brief (PWM_WPCR) Write Protect Register Group 5 */\r
+#define PWM_WPCR_WPKEY_Pos 8\r
+#define PWM_WPCR_WPKEY_Msk (0xffffffu << PWM_WPCR_WPKEY_Pos) /**< \brief (PWM_WPCR) Write Protect Key */\r
+#define PWM_WPCR_WPKEY(value) ((PWM_WPCR_WPKEY_Msk & ((value) << PWM_WPCR_WPKEY_Pos)))\r
+/* -------- PWM_WPSR : (PWM Offset: 0xE8) PWM Write Protect Status Register -------- */\r
+#define PWM_WPSR_WPSWS0 (0x1u << 0) /**< \brief (PWM_WPSR) Write Protect SW Status */\r
+#define PWM_WPSR_WPSWS1 (0x1u << 1) /**< \brief (PWM_WPSR) Write Protect SW Status */\r
+#define PWM_WPSR_WPSWS2 (0x1u << 2) /**< \brief (PWM_WPSR) Write Protect SW Status */\r
+#define PWM_WPSR_WPSWS3 (0x1u << 3) /**< \brief (PWM_WPSR) Write Protect SW Status */\r
+#define PWM_WPSR_WPSWS4 (0x1u << 4) /**< \brief (PWM_WPSR) Write Protect SW Status */\r
+#define PWM_WPSR_WPSWS5 (0x1u << 5) /**< \brief (PWM_WPSR) Write Protect SW Status */\r
+#define PWM_WPSR_WPVS (0x1u << 7) /**< \brief (PWM_WPSR) Write Protect Violation Status */\r
+#define PWM_WPSR_WPHWS0 (0x1u << 8) /**< \brief (PWM_WPSR) Write Protect HW Status */\r
+#define PWM_WPSR_WPHWS1 (0x1u << 9) /**< \brief (PWM_WPSR) Write Protect HW Status */\r
+#define PWM_WPSR_WPHWS2 (0x1u << 10) /**< \brief (PWM_WPSR) Write Protect HW Status */\r
+#define PWM_WPSR_WPHWS3 (0x1u << 11) /**< \brief (PWM_WPSR) Write Protect HW Status */\r
+#define PWM_WPSR_WPHWS4 (0x1u << 12) /**< \brief (PWM_WPSR) Write Protect HW Status */\r
+#define PWM_WPSR_WPHWS5 (0x1u << 13) /**< \brief (PWM_WPSR) Write Protect HW Status */\r
+#define PWM_WPSR_WPVSRC_Pos 16\r
+#define PWM_WPSR_WPVSRC_Msk (0xffffu << PWM_WPSR_WPVSRC_Pos) /**< \brief (PWM_WPSR) Write Protect Violation Source */\r
+/* -------- PWM_TPR : (PWM Offset: 0x108) Transmit Pointer Register -------- */\r
+#define PWM_TPR_TXPTR_Pos 0\r
+#define PWM_TPR_TXPTR_Msk (0xffffffffu << PWM_TPR_TXPTR_Pos) /**< \brief (PWM_TPR) Transmit Counter Register */\r
+#define PWM_TPR_TXPTR(value) ((PWM_TPR_TXPTR_Msk & ((value) << PWM_TPR_TXPTR_Pos)))\r
+/* -------- PWM_TCR : (PWM Offset: 0x10C) Transmit Counter Register -------- */\r
+#define PWM_TCR_TXCTR_Pos 0\r
+#define PWM_TCR_TXCTR_Msk (0xffffu << PWM_TCR_TXCTR_Pos) /**< \brief (PWM_TCR) Transmit Counter Register */\r
+#define PWM_TCR_TXCTR(value) ((PWM_TCR_TXCTR_Msk & ((value) << PWM_TCR_TXCTR_Pos)))\r
+/* -------- PWM_TNPR : (PWM Offset: 0x118) Transmit Next Pointer Register -------- */\r
+#define PWM_TNPR_TXNPTR_Pos 0\r
+#define PWM_TNPR_TXNPTR_Msk (0xffffffffu << PWM_TNPR_TXNPTR_Pos) /**< \brief (PWM_TNPR) Transmit Next Pointer */\r
+#define PWM_TNPR_TXNPTR(value) ((PWM_TNPR_TXNPTR_Msk & ((value) << PWM_TNPR_TXNPTR_Pos)))\r
+/* -------- PWM_TNCR : (PWM Offset: 0x11C) Transmit Next Counter Register -------- */\r
+#define PWM_TNCR_TXNCTR_Pos 0\r
+#define PWM_TNCR_TXNCTR_Msk (0xffffu << PWM_TNCR_TXNCTR_Pos) /**< \brief (PWM_TNCR) Transmit Counter Next */\r
+#define PWM_TNCR_TXNCTR(value) ((PWM_TNCR_TXNCTR_Msk & ((value) << PWM_TNCR_TXNCTR_Pos)))\r
+/* -------- PWM_PTCR : (PWM Offset: 0x120) Transfer Control Register -------- */\r
+#define PWM_PTCR_RXTEN (0x1u << 0) /**< \brief (PWM_PTCR) Receiver Transfer Enable */\r
+#define PWM_PTCR_RXTDIS (0x1u << 1) /**< \brief (PWM_PTCR) Receiver Transfer Disable */\r
+#define PWM_PTCR_TXTEN (0x1u << 8) /**< \brief (PWM_PTCR) Transmitter Transfer Enable */\r
+#define PWM_PTCR_TXTDIS (0x1u << 9) /**< \brief (PWM_PTCR) Transmitter Transfer Disable */\r
+/* -------- PWM_PTSR : (PWM Offset: 0x124) Transfer Status Register -------- */\r
+#define PWM_PTSR_RXTEN (0x1u << 0) /**< \brief (PWM_PTSR) Receiver Transfer Enable */\r
+#define PWM_PTSR_TXTEN (0x1u << 8) /**< \brief (PWM_PTSR) Transmitter Transfer Enable */\r
+/* -------- PWM_CMPV : (PWM Offset: N/A) PWM Comparison 0 Value Register -------- */\r
+#define PWM_CMPV_CV_Pos 0\r
+#define PWM_CMPV_CV_Msk (0xffffffu << PWM_CMPV_CV_Pos) /**< \brief (PWM_CMPV) Comparison x Value */\r
+#define PWM_CMPV_CV(value) ((PWM_CMPV_CV_Msk & ((value) << PWM_CMPV_CV_Pos)))\r
+#define PWM_CMPV_CVM (0x1u << 24) /**< \brief (PWM_CMPV) Comparison x Value Mode */\r
+/* -------- PWM_CMPVUPD : (PWM Offset: N/A) PWM Comparison 0 Value Update Register -------- */\r
+#define PWM_CMPVUPD_CVUPD_Pos 0\r
+#define PWM_CMPVUPD_CVUPD_Msk (0xffffffu << PWM_CMPVUPD_CVUPD_Pos) /**< \brief (PWM_CMPVUPD) Comparison x Value Update */\r
+#define PWM_CMPVUPD_CVUPD(value) ((PWM_CMPVUPD_CVUPD_Msk & ((value) << PWM_CMPVUPD_CVUPD_Pos)))\r
+#define PWM_CMPVUPD_CVMUPD (0x1u << 24) /**< \brief (PWM_CMPVUPD) Comparison x Value Mode Update */\r
+/* -------- PWM_CMPM : (PWM Offset: N/A) PWM Comparison 0 Mode Register -------- */\r
+#define PWM_CMPM_CEN (0x1u << 0) /**< \brief (PWM_CMPM) Comparison x Enable */\r
+#define PWM_CMPM_CTR_Pos 4\r
+#define PWM_CMPM_CTR_Msk (0xfu << PWM_CMPM_CTR_Pos) /**< \brief (PWM_CMPM) Comparison x Trigger */\r
+#define PWM_CMPM_CTR(value) ((PWM_CMPM_CTR_Msk & ((value) << PWM_CMPM_CTR_Pos)))\r
+#define PWM_CMPM_CPR_Pos 8\r
+#define PWM_CMPM_CPR_Msk (0xfu << PWM_CMPM_CPR_Pos) /**< \brief (PWM_CMPM) Comparison x Period */\r
+#define PWM_CMPM_CPR(value) ((PWM_CMPM_CPR_Msk & ((value) << PWM_CMPM_CPR_Pos)))\r
+#define PWM_CMPM_CPRCNT_Pos 12\r
+#define PWM_CMPM_CPRCNT_Msk (0xfu << PWM_CMPM_CPRCNT_Pos) /**< \brief (PWM_CMPM) Comparison x Period Counter */\r
+#define PWM_CMPM_CPRCNT(value) ((PWM_CMPM_CPRCNT_Msk & ((value) << PWM_CMPM_CPRCNT_Pos)))\r
+#define PWM_CMPM_CUPR_Pos 16\r
+#define PWM_CMPM_CUPR_Msk (0xfu << PWM_CMPM_CUPR_Pos) /**< \brief (PWM_CMPM) Comparison x Update Period */\r
+#define PWM_CMPM_CUPR(value) ((PWM_CMPM_CUPR_Msk & ((value) << PWM_CMPM_CUPR_Pos)))\r
+#define PWM_CMPM_CUPRCNT_Pos 20\r
+#define PWM_CMPM_CUPRCNT_Msk (0xfu << PWM_CMPM_CUPRCNT_Pos) /**< \brief (PWM_CMPM) Comparison x Update Period Counter */\r
+#define PWM_CMPM_CUPRCNT(value) ((PWM_CMPM_CUPRCNT_Msk & ((value) << PWM_CMPM_CUPRCNT_Pos)))\r
+/* -------- PWM_CMPMUPD : (PWM Offset: N/A) PWM Comparison 0 Mode Update Register -------- */\r
+#define PWM_CMPMUPD_CENUPD (0x1u << 0) /**< \brief (PWM_CMPMUPD) Comparison x Enable Update */\r
+#define PWM_CMPMUPD_CTRUPD_Pos 4\r
+#define PWM_CMPMUPD_CTRUPD_Msk (0xfu << PWM_CMPMUPD_CTRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Trigger Update */\r
+#define PWM_CMPMUPD_CTRUPD(value) ((PWM_CMPMUPD_CTRUPD_Msk & ((value) << PWM_CMPMUPD_CTRUPD_Pos)))\r
+#define PWM_CMPMUPD_CPRUPD_Pos 8\r
+#define PWM_CMPMUPD_CPRUPD_Msk (0xfu << PWM_CMPMUPD_CPRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Period Update */\r
+#define PWM_CMPMUPD_CPRUPD(value) ((PWM_CMPMUPD_CPRUPD_Msk & ((value) << PWM_CMPMUPD_CPRUPD_Pos)))\r
+#define PWM_CMPMUPD_CUPRUPD_Pos 16\r
+#define PWM_CMPMUPD_CUPRUPD_Msk (0xfu << PWM_CMPMUPD_CUPRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Update Period Update */\r
+#define PWM_CMPMUPD_CUPRUPD(value) ((PWM_CMPMUPD_CUPRUPD_Msk & ((value) << PWM_CMPMUPD_CUPRUPD_Pos)))\r
+/* -------- PWM_CMR : (PWM Offset: N/A) PWM Channel Mode Register -------- */\r
+#define PWM_CMR_CPRE_Pos 0\r
+#define PWM_CMR_CPRE_Msk (0xfu << PWM_CMR_CPRE_Pos) /**< \brief (PWM_CMR) Channel Pre-scaler */\r
+#define PWM_CMR_CPRE_MCK (0x0u << 0) /**< \brief (PWM_CMR) Master clock */\r
+#define PWM_CMR_CPRE_MCK_DIV_2 (0x1u << 0) /**< \brief (PWM_CMR) Master clock/2 */\r
+#define PWM_CMR_CPRE_MCK_DIV_4 (0x2u << 0) /**< \brief (PWM_CMR) Master clock/4 */\r
+#define PWM_CMR_CPRE_MCK_DIV_8 (0x3u << 0) /**< \brief (PWM_CMR) Master clock/8 */\r
+#define PWM_CMR_CPRE_MCK_DIV_16 (0x4u << 0) /**< \brief (PWM_CMR) Master clock/16 */\r
+#define PWM_CMR_CPRE_MCK_DIV_32 (0x5u << 0) /**< \brief (PWM_CMR) Master clock/32 */\r
+#define PWM_CMR_CPRE_MCK_DIV_64 (0x6u << 0) /**< \brief (PWM_CMR) Master clock/64 */\r
+#define PWM_CMR_CPRE_MCK_DIV_128 (0x7u << 0) /**< \brief (PWM_CMR) Master clock/128 */\r
+#define PWM_CMR_CPRE_MCK_DIV_256 (0x8u << 0) /**< \brief (PWM_CMR) Master clock/256 */\r
+#define PWM_CMR_CPRE_MCK_DIV_512 (0x9u << 0) /**< \brief (PWM_CMR) Master clock/512 */\r
+#define PWM_CMR_CPRE_MCK_DIV_1024 (0xAu << 0) /**< \brief (PWM_CMR) Master clock/1024 */\r
+#define PWM_CMR_CPRE_CLKA (0xBu << 0) /**< \brief (PWM_CMR) Clock A */\r
+#define PWM_CMR_CPRE_CLKB (0xCu << 0) /**< \brief (PWM_CMR) Clock B */\r
+#define PWM_CMR_CALG (0x1u << 8) /**< \brief (PWM_CMR) Channel Alignment */\r
+#define PWM_CMR_CPOL (0x1u << 9) /**< \brief (PWM_CMR) Channel Polarity */\r
+#define PWM_CMR_CES (0x1u << 10) /**< \brief (PWM_CMR) Counter Event Selection */\r
+#define PWM_CMR_UPDS (0x1u << 11) /**< \brief (PWM_CMR) Update Selection */\r
+#define PWM_CMR_DTE (0x1u << 16) /**< \brief (PWM_CMR) Dead-Time Generator Enable */\r
+#define PWM_CMR_DTHI (0x1u << 17) /**< \brief (PWM_CMR) Dead-Time PWMHx Output Inverted */\r
+#define PWM_CMR_DTLI (0x1u << 18) /**< \brief (PWM_CMR) Dead-Time PWMLx Output Inverted */\r
+/* -------- PWM_CDTY : (PWM Offset: N/A) PWM Channel Duty Cycle Register -------- */\r
+#define PWM_CDTY_CDTY_Pos 0\r
+#define PWM_CDTY_CDTY_Msk (0xffffffu << PWM_CDTY_CDTY_Pos) /**< \brief (PWM_CDTY) Channel Duty-Cycle */\r
+#define PWM_CDTY_CDTY(value) ((PWM_CDTY_CDTY_Msk & ((value) << PWM_CDTY_CDTY_Pos)))\r
+/* -------- PWM_CDTYUPD : (PWM Offset: N/A) PWM Channel Duty Cycle Update Register -------- */\r
+#define PWM_CDTYUPD_CDTYUPD_Pos 0\r
+#define PWM_CDTYUPD_CDTYUPD_Msk (0xffffffu << PWM_CDTYUPD_CDTYUPD_Pos) /**< \brief (PWM_CDTYUPD) Channel Duty-Cycle Update */\r
+#define PWM_CDTYUPD_CDTYUPD(value) ((PWM_CDTYUPD_CDTYUPD_Msk & ((value) << PWM_CDTYUPD_CDTYUPD_Pos)))\r
+/* -------- PWM_CPRD : (PWM Offset: N/A) PWM Channel Period Register -------- */\r
+#define PWM_CPRD_CPRD_Pos 0\r
+#define PWM_CPRD_CPRD_Msk (0xffffffu << PWM_CPRD_CPRD_Pos) /**< \brief (PWM_CPRD) Channel Period */\r
+#define PWM_CPRD_CPRD(value) ((PWM_CPRD_CPRD_Msk & ((value) << PWM_CPRD_CPRD_Pos)))\r
+/* -------- PWM_CPRDUPD : (PWM Offset: N/A) PWM Channel Period Update Register -------- */\r
+#define PWM_CPRDUPD_CPRDUPD_Pos 0\r
+#define PWM_CPRDUPD_CPRDUPD_Msk (0xffffffu << PWM_CPRDUPD_CPRDUPD_Pos) /**< \brief (PWM_CPRDUPD) Channel Period Update */\r
+#define PWM_CPRDUPD_CPRDUPD(value) ((PWM_CPRDUPD_CPRDUPD_Msk & ((value) << PWM_CPRDUPD_CPRDUPD_Pos)))\r
+/* -------- PWM_CCNT : (PWM Offset: N/A) PWM Channel Counter Register -------- */\r
+#define PWM_CCNT_CNT_Pos 0\r
+#define PWM_CCNT_CNT_Msk (0xffffffu << PWM_CCNT_CNT_Pos) /**< \brief (PWM_CCNT) Channel Counter Register */\r
+/* -------- PWM_DT : (PWM Offset: N/A) PWM Channel Dead Time Register -------- */\r
+#define PWM_DT_DTH_Pos 0\r
+#define PWM_DT_DTH_Msk (0xffffu << PWM_DT_DTH_Pos) /**< \brief (PWM_DT) Dead-Time Value for PWMHx Output */\r
+#define PWM_DT_DTH(value) ((PWM_DT_DTH_Msk & ((value) << PWM_DT_DTH_Pos)))\r
+#define PWM_DT_DTL_Pos 16\r
+#define PWM_DT_DTL_Msk (0xffffu << PWM_DT_DTL_Pos) /**< \brief (PWM_DT) Dead-Time Value for PWMLx Output */\r
+#define PWM_DT_DTL(value) ((PWM_DT_DTL_Msk & ((value) << PWM_DT_DTL_Pos)))\r
+/* -------- PWM_DTUPD : (PWM Offset: N/A) PWM Channel Dead Time Update Register -------- */\r
+#define PWM_DTUPD_DTHUPD_Pos 0\r
+#define PWM_DTUPD_DTHUPD_Msk (0xffffu << PWM_DTUPD_DTHUPD_Pos) /**< \brief (PWM_DTUPD) Dead-Time Value Update for PWMHx Output */\r
+#define PWM_DTUPD_DTHUPD(value) ((PWM_DTUPD_DTHUPD_Msk & ((value) << PWM_DTUPD_DTHUPD_Pos)))\r
+#define PWM_DTUPD_DTLUPD_Pos 16\r
+#define PWM_DTUPD_DTLUPD_Msk (0xffffu << PWM_DTUPD_DTLUPD_Pos) /**< \brief (PWM_DTUPD) Dead-Time Value Update for PWMLx Output */\r
+#define PWM_DTUPD_DTLUPD(value) ((PWM_DTUPD_DTLUPD_Msk & ((value) << PWM_DTUPD_DTLUPD_Pos)))\r
+/* -------- PWM_CMUPD : (PWM Offset: N/A) PWM Channel Mode Update Register -------- */\r
+#define PWM_CMUPD_CPOLUP (0x1u << 9) /**< \brief (PWM_CMUPD) Channel Polarity Update */\r
+#define PWM_CMUPD_CPOLINVUP (0x1u << 13) /**< \brief (PWM_CMUPD) Channel Polarity Inversion Update */\r
+/* -------- PWM_CAE : (PWM Offset: N/A) PWM Channel Additional Edge Register -------- */\r
+#define PWM_CAE_ADEDGV_Pos 0\r
+#define PWM_CAE_ADEDGV_Msk (0xffffffu << PWM_CAE_ADEDGV_Pos) /**< \brief (PWM_CAE) Channel Additional Edge Value */\r
+#define PWM_CAE_ADEDGV(value) ((PWM_CAE_ADEDGV_Msk & ((value) << PWM_CAE_ADEDGV_Pos)))\r
+#define PWM_CAE_ADEDGM_Pos 24\r
+#define PWM_CAE_ADEDGM_Msk (0x3u << PWM_CAE_ADEDGM_Pos) /**< \brief (PWM_CAE) Channel Additional Edge Mode */\r
+#define PWM_CAE_ADEDGM_INC (0x0u << 24) /**< \brief (PWM_CAE) The additional edge of the channel x output waveform occurs when CCNTx reaches ADEDGV and the counter of the channel x is incrementing. */\r
+#define PWM_CAE_ADEDGM_DEC (0x1u << 24) /**< \brief (PWM_CAE) The additional edge of the channel x output waveform occurs when CCNTx reaches ADEDGV and the counter of the channel x is incrementing. */\r
+#define PWM_CAE_ADEDGM_BOTH (0x2u << 24) /**< \brief (PWM_CAE) The additional edge of the channel x output waveform occurs when CCNTx reaches ADEDGV, whether the counter is incrementing or not. */\r
+/* -------- PWM_CAEUPD : (PWM Offset: N/A) PWM Channel Additional Edge Update Register -------- */\r
+#define PWM_CAEUPD_ADEDGVUP_Pos 0\r
+#define PWM_CAEUPD_ADEDGVUP_Msk (0xffffffu << PWM_CAEUPD_ADEDGVUP_Pos) /**< \brief (PWM_CAEUPD) Channel Additional Edge Value Update */\r
+#define PWM_CAEUPD_ADEDGVUP(value) ((PWM_CAEUPD_ADEDGVUP_Msk & ((value) << PWM_CAEUPD_ADEDGVUP_Pos)))\r
+#define PWM_CAEUPD_ADEDGMUP_Pos 24\r
+#define PWM_CAEUPD_ADEDGMUP_Msk (0x3u << PWM_CAEUPD_ADEDGMUP_Pos) /**< \brief (PWM_CAEUPD) Channel Additional Edge Mode Update */\r
+#define PWM_CAEUPD_ADEDGMUP_INC (0x0u << 24) /**< \brief (PWM_CAEUPD) The additional edge of the channel x output waveform occurs when CCNTx reaches ADEDGVUP and the counter of the channel x is incrementing. */\r
+#define PWM_CAEUPD_ADEDGMUP_DEC (0x1u << 24) /**< \brief (PWM_CAEUPD) The additional edge of the channel x output waveform occurs when CCNTx reaches ADEDGVUP and the counter of the channel x is incrementing. */\r
+#define PWM_CAEUPD_ADEDGMUP_BOTH (0x2u << 24) /**< \brief (PWM_CAEUPD) The additional edge of the channel x output waveform occurs when CCNTx reaches ADEDGVUP, whether the counter is incrementing or not. */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM4E_PWM_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4E_RSTC_COMPONENT_\r
+#define _SAM4E_RSTC_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Reset Controller */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM4E_RSTC Reset Controller */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Rstc hardware registers */\r
+typedef struct {\r
+ WoReg RSTC_CR; /**< \brief (Rstc Offset: 0x00) Control Register */\r
+ RoReg RSTC_SR; /**< \brief (Rstc Offset: 0x04) Status Register */\r
+ RwReg RSTC_MR; /**< \brief (Rstc Offset: 0x08) Mode Register */\r
+} Rstc;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- RSTC_CR : (RSTC Offset: 0x00) Control Register -------- */\r
+#define RSTC_CR_PROCRST (0x1u << 0) /**< \brief (RSTC_CR) Processor Reset */\r
+#define RSTC_CR_PERRST (0x1u << 2) /**< \brief (RSTC_CR) Peripheral Reset */\r
+#define RSTC_CR_EXTRST (0x1u << 3) /**< \brief (RSTC_CR) External Reset */\r
+#define RSTC_CR_KEY_Pos 24\r
+#define RSTC_CR_KEY_Msk (0xffu << RSTC_CR_KEY_Pos) /**< \brief (RSTC_CR) System Reset Key */\r
+#define RSTC_CR_KEY(value) ((RSTC_CR_KEY_Msk & ((value) << RSTC_CR_KEY_Pos)))\r
+/* -------- RSTC_SR : (RSTC Offset: 0x04) Status Register -------- */\r
+#define RSTC_SR_URSTS (0x1u << 0) /**< \brief (RSTC_SR) User Reset Status */\r
+#define RSTC_SR_RSTTYP_Pos 8\r
+#define RSTC_SR_RSTTYP_Msk (0x7u << RSTC_SR_RSTTYP_Pos) /**< \brief (RSTC_SR) Reset Type */\r
+#define RSTC_SR_NRSTL (0x1u << 16) /**< \brief (RSTC_SR) NRST Pin Level */\r
+#define RSTC_SR_SRCMP (0x1u << 17) /**< \brief (RSTC_SR) Software Reset Command in Progress */\r
+/* -------- RSTC_MR : (RSTC Offset: 0x08) Mode Register -------- */\r
+#define RSTC_MR_URSTEN (0x1u << 0) /**< \brief (RSTC_MR) User Reset Enable */\r
+#define RSTC_MR_URSTIEN (0x1u << 4) /**< \brief (RSTC_MR) User Reset Interrupt Enable */\r
+#define RSTC_MR_ERSTL_Pos 8\r
+#define RSTC_MR_ERSTL_Msk (0xfu << RSTC_MR_ERSTL_Pos) /**< \brief (RSTC_MR) External Reset Length */\r
+#define RSTC_MR_ERSTL(value) ((RSTC_MR_ERSTL_Msk & ((value) << RSTC_MR_ERSTL_Pos)))\r
+#define RSTC_MR_KEY_Pos 24\r
+#define RSTC_MR_KEY_Msk (0xffu << RSTC_MR_KEY_Pos) /**< \brief (RSTC_MR) Password */\r
+#define RSTC_MR_KEY(value) ((RSTC_MR_KEY_Msk & ((value) << RSTC_MR_KEY_Pos)))\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM4E_RSTC_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4E_RSWDT_COMPONENT_\r
+#define _SAM4E_RSWDT_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Reinforced Safety Watchdog Timer */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM4E_RSWDT Reinforced Safety Watchdog Timer */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Rswdt hardware registers */\r
+typedef struct {\r
+ WoReg RSWDT_CR; /**< \brief (Rswdt Offset: 0x00) Control Register */\r
+ RwReg RSWDT_MR; /**< \brief (Rswdt Offset: 0x04) Mode Register */\r
+ RoReg RSWDT_SR; /**< \brief (Rswdt Offset: 0x08) Status Register */\r
+} Rswdt;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- RSWDT_CR : (RSWDT Offset: 0x00) Control Register -------- */\r
+#define RSWDT_CR_WDRSTT (0x1u << 0) /**< \brief (RSWDT_CR) Watchdog Restart */\r
+#define RSWDT_CR_KEY_Pos 24\r
+#define RSWDT_CR_KEY_Msk (0xffu << RSWDT_CR_KEY_Pos) /**< \brief (RSWDT_CR) Password */\r
+#define RSWDT_CR_KEY(value) ((RSWDT_CR_KEY_Msk & ((value) << RSWDT_CR_KEY_Pos)))\r
+/* -------- RSWDT_MR : (RSWDT Offset: 0x04) Mode Register -------- */\r
+#define RSWDT_MR_WDV_Pos 0\r
+#define RSWDT_MR_WDV_Msk (0xfffu << RSWDT_MR_WDV_Pos) /**< \brief (RSWDT_MR) Watchdog Counter Value */\r
+#define RSWDT_MR_WDV(value) ((RSWDT_MR_WDV_Msk & ((value) << RSWDT_MR_WDV_Pos)))\r
+#define RSWDT_MR_WDFIEN (0x1u << 12) /**< \brief (RSWDT_MR) Watchdog Fault Interrupt Enable */\r
+#define RSWDT_MR_WDRSTEN (0x1u << 13) /**< \brief (RSWDT_MR) Watchdog Reset Enable */\r
+#define RSWDT_MR_WDRPROC (0x1u << 14) /**< \brief (RSWDT_MR) Watchdog Reset Processor */\r
+#define RSWDT_MR_WDDIS (0x1u << 15) /**< \brief (RSWDT_MR) Watchdog Disable */\r
+#define RSWDT_MR_WDD_Pos 16\r
+#define RSWDT_MR_WDD_Msk (0xfffu << RSWDT_MR_WDD_Pos) /**< \brief (RSWDT_MR) Watchdog Delta Value */\r
+#define RSWDT_MR_WDD(value) ((RSWDT_MR_WDD_Msk & ((value) << RSWDT_MR_WDD_Pos)))\r
+#define RSWDT_MR_WDDBGHLT (0x1u << 28) /**< \brief (RSWDT_MR) Watchdog Debug Halt */\r
+#define RSWDT_MR_WDIDLEHLT (0x1u << 29) /**< \brief (RSWDT_MR) Watchdog Idle Halt */\r
+/* -------- RSWDT_SR : (RSWDT Offset: 0x08) Status Register -------- */\r
+#define RSWDT_SR_WDUNF (0x1u << 0) /**< \brief (RSWDT_SR) Watchdog Underflow */\r
+#define RSWDT_SR_WDERR (0x1u << 1) /**< \brief (RSWDT_SR) Watchdog Error */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM4E_RSWDT_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4E_RTC_COMPONENT_\r
+#define _SAM4E_RTC_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Real-time Clock */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM4E_RTC Real-time Clock */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Rtc hardware registers */\r
+typedef struct {\r
+ RwReg RTC_CR; /**< \brief (Rtc Offset: 0x00) Control Register */\r
+ RwReg RTC_MR; /**< \brief (Rtc Offset: 0x04) Mode Register */\r
+ RwReg RTC_TIMR; /**< \brief (Rtc Offset: 0x08) Time Register */\r
+ RwReg RTC_CALR; /**< \brief (Rtc Offset: 0x0C) Calendar Register */\r
+ RwReg RTC_TIMALR; /**< \brief (Rtc Offset: 0x10) Time Alarm Register */\r
+ RwReg RTC_CALALR; /**< \brief (Rtc Offset: 0x14) Calendar Alarm Register */\r
+ RoReg RTC_SR; /**< \brief (Rtc Offset: 0x18) Status Register */\r
+ WoReg RTC_SCCR; /**< \brief (Rtc Offset: 0x1C) Status Clear Command Register */\r
+ WoReg RTC_IER; /**< \brief (Rtc Offset: 0x20) Interrupt Enable Register */\r
+ WoReg RTC_IDR; /**< \brief (Rtc Offset: 0x24) Interrupt Disable Register */\r
+ RoReg RTC_IMR; /**< \brief (Rtc Offset: 0x28) Interrupt Mask Register */\r
+ RoReg RTC_VER; /**< \brief (Rtc Offset: 0x2C) Valid Entry Register */\r
+} Rtc;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- RTC_CR : (RTC Offset: 0x00) Control Register -------- */\r
+#define RTC_CR_UPDTIM (0x1u << 0) /**< \brief (RTC_CR) Update Request Time Register */\r
+#define RTC_CR_UPDCAL (0x1u << 1) /**< \brief (RTC_CR) Update Request Calendar Register */\r
+#define RTC_CR_TIMEVSEL_Pos 8\r
+#define RTC_CR_TIMEVSEL_Msk (0x3u << RTC_CR_TIMEVSEL_Pos) /**< \brief (RTC_CR) Time Event Selection */\r
+#define RTC_CR_TIMEVSEL_MINUTE (0x0u << 8) /**< \brief (RTC_CR) Minute change */\r
+#define RTC_CR_TIMEVSEL_HOUR (0x1u << 8) /**< \brief (RTC_CR) Hour change */\r
+#define RTC_CR_TIMEVSEL_MIDNIGHT (0x2u << 8) /**< \brief (RTC_CR) Every day at midnight */\r
+#define RTC_CR_TIMEVSEL_NOON (0x3u << 8) /**< \brief (RTC_CR) Every day at noon */\r
+#define RTC_CR_CALEVSEL_Pos 16\r
+#define RTC_CR_CALEVSEL_Msk (0x3u << RTC_CR_CALEVSEL_Pos) /**< \brief (RTC_CR) Calendar Event Selection */\r
+#define RTC_CR_CALEVSEL_WEEK (0x0u << 16) /**< \brief (RTC_CR) Week change (every Monday at time 00:00:00) */\r
+#define RTC_CR_CALEVSEL_MONTH (0x1u << 16) /**< \brief (RTC_CR) Month change (every 01 of each month at time 00:00:00) */\r
+#define RTC_CR_CALEVSEL_YEAR (0x2u << 16) /**< \brief (RTC_CR) Year change (every January 1 at time 00:00:00) */\r
+/* -------- RTC_MR : (RTC Offset: 0x04) Mode Register -------- */\r
+#define RTC_MR_HRMOD (0x1u << 0) /**< \brief (RTC_MR) 12-/24-hour Mode */\r
+#define RTC_MR_PERSIAN (0x1u << 1) /**< \brief (RTC_MR) PERSIAN Calendar */\r
+#define RTC_MR_NEGPPM (0x1u << 4) /**< \brief (RTC_MR) NEGative PPM Correction */\r
+#define RTC_MR_CORRECTION_Pos 8\r
+#define RTC_MR_CORRECTION_Msk (0x7fu << RTC_MR_CORRECTION_Pos) /**< \brief (RTC_MR) Slow Clock Correction */\r
+#define RTC_MR_CORRECTION(value) ((RTC_MR_CORRECTION_Msk & ((value) << RTC_MR_CORRECTION_Pos)))\r
+#define RTC_MR_HIGHPPM (0x1u << 15) /**< \brief (RTC_MR) HIGH PPM Correction */\r
+#define RTC_MR_OUT0_Pos 16\r
+#define RTC_MR_OUT0_Msk (0x7u << RTC_MR_OUT0_Pos) /**< \brief (RTC_MR) RTCOUT0 OutputSource Selection */\r
+#define RTC_MR_OUT0_NO_WAVE (0x0u << 16) /**< \brief (RTC_MR) no waveform, stuck at '0' */\r
+#define RTC_MR_OUT0_FREQ1HZ (0x1u << 16) /**< \brief (RTC_MR) 1 Hz square wave */\r
+#define RTC_MR_OUT0_FREQ32HZ (0x2u << 16) /**< \brief (RTC_MR) 32 Hz square wave */\r
+#define RTC_MR_OUT0_FREQ64HZ (0x3u << 16) /**< \brief (RTC_MR) 64 Hz square wave */\r
+#define RTC_MR_OUT0_FREQ512HZ (0x4u << 16) /**< \brief (RTC_MR) 512 Hz square wave */\r
+#define RTC_MR_OUT0_ALARM_TOGGLE (0x5u << 16) /**< \brief (RTC_MR) output toggles when alarm flag rises */\r
+#define RTC_MR_OUT0_ALARM_FLAG (0x6u << 16) /**< \brief (RTC_MR) output is a copy of the alarm flag */\r
+#define RTC_MR_OUT0_PROG_PULSE (0x7u << 16) /**< \brief (RTC_MR) duty cycle programmable pulse */\r
+#define RTC_MR_OUT1_Pos 20\r
+#define RTC_MR_OUT1_Msk (0x7u << RTC_MR_OUT1_Pos) /**< \brief (RTC_MR) RTCOUT1 Output Source Selection */\r
+#define RTC_MR_OUT1_NO_WAVE (0x0u << 20) /**< \brief (RTC_MR) no waveform, stuck at '0' */\r
+#define RTC_MR_OUT1_FREQ1HZ (0x1u << 20) /**< \brief (RTC_MR) 1 Hz square wave */\r
+#define RTC_MR_OUT1_FREQ32HZ (0x2u << 20) /**< \brief (RTC_MR) 32 Hz square wave */\r
+#define RTC_MR_OUT1_FREQ64HZ (0x3u << 20) /**< \brief (RTC_MR) 64 Hz square wave */\r
+#define RTC_MR_OUT1_FREQ512HZ (0x4u << 20) /**< \brief (RTC_MR) 512 Hz square wave */\r
+#define RTC_MR_OUT1_ALARM_TOGGLE (0x5u << 20) /**< \brief (RTC_MR) output toggles when alarm flag rises */\r
+#define RTC_MR_OUT1_ALARM_FLAG (0x6u << 20) /**< \brief (RTC_MR) output is a copy of the alarm flag */\r
+#define RTC_MR_OUT1_PROG_PULSE (0x7u << 20) /**< \brief (RTC_MR) duty cycle programmable pulse */\r
+#define RTC_MR_THIGH_Pos 24\r
+#define RTC_MR_THIGH_Msk (0x7u << RTC_MR_THIGH_Pos) /**< \brief (RTC_MR) High Duration of the Output Pulse */\r
+#define RTC_MR_THIGH_H_31MS (0x0u << 24) /**< \brief (RTC_MR) 31.2 ms */\r
+#define RTC_MR_THIGH_H_16MS (0x1u << 24) /**< \brief (RTC_MR) 15.6 ms */\r
+#define RTC_MR_THIGH_H_4MS (0x2u << 24) /**< \brief (RTC_MR) 3.91 Mms */\r
+#define RTC_MR_THIGH_H_976US (0x3u << 24) /**< \brief (RTC_MR) 976 us */\r
+#define RTC_MR_THIGH_H_488US (0x4u << 24) /**< \brief (RTC_MR) 488 us */\r
+#define RTC_MR_THIGH_H_122US (0x5u << 24) /**< \brief (RTC_MR) 122 us */\r
+#define RTC_MR_THIGH_H_30US (0x6u << 24) /**< \brief (RTC_MR) 30.5 us */\r
+#define RTC_MR_THIGH_H_15US (0x7u << 24) /**< \brief (RTC_MR) 15.2 us */\r
+#define RTC_MR_TPERIOD_Pos 28\r
+#define RTC_MR_TPERIOD_Msk (0x3u << RTC_MR_TPERIOD_Pos) /**< \brief (RTC_MR) Period of the Output Pulse */\r
+#define RTC_MR_TPERIOD_P_1S (0x0u << 28) /**< \brief (RTC_MR) 1 second */\r
+#define RTC_MR_TPERIOD_P_500MS (0x1u << 28) /**< \brief (RTC_MR) 500 ms */\r
+#define RTC_MR_TPERIOD_P_250MS (0x2u << 28) /**< \brief (RTC_MR) 250 ms */\r
+#define RTC_MR_TPERIOD_P_125MS (0x3u << 28) /**< \brief (RTC_MR) 125 ms */\r
+/* -------- RTC_TIMR : (RTC Offset: 0x08) Time Register -------- */\r
+#define RTC_TIMR_SEC_Pos 0\r
+#define RTC_TIMR_SEC_Msk (0x7fu << RTC_TIMR_SEC_Pos) /**< \brief (RTC_TIMR) Current Second */\r
+#define RTC_TIMR_SEC(value) ((RTC_TIMR_SEC_Msk & ((value) << RTC_TIMR_SEC_Pos)))\r
+#define RTC_TIMR_MIN_Pos 8\r
+#define RTC_TIMR_MIN_Msk (0x7fu << RTC_TIMR_MIN_Pos) /**< \brief (RTC_TIMR) Current Minute */\r
+#define RTC_TIMR_MIN(value) ((RTC_TIMR_MIN_Msk & ((value) << RTC_TIMR_MIN_Pos)))\r
+#define RTC_TIMR_HOUR_Pos 16\r
+#define RTC_TIMR_HOUR_Msk (0x3fu << RTC_TIMR_HOUR_Pos) /**< \brief (RTC_TIMR) Current Hour */\r
+#define RTC_TIMR_HOUR(value) ((RTC_TIMR_HOUR_Msk & ((value) << RTC_TIMR_HOUR_Pos)))\r
+#define RTC_TIMR_AMPM (0x1u << 22) /**< \brief (RTC_TIMR) Ante Meridiem Post Meridiem Indicator */\r
+/* -------- RTC_CALR : (RTC Offset: 0x0C) Calendar Register -------- */\r
+#define RTC_CALR_CENT_Pos 0\r
+#define RTC_CALR_CENT_Msk (0x7fu << RTC_CALR_CENT_Pos) /**< \brief (RTC_CALR) Current Century */\r
+#define RTC_CALR_CENT(value) ((RTC_CALR_CENT_Msk & ((value) << RTC_CALR_CENT_Pos)))\r
+#define RTC_CALR_YEAR_Pos 8\r
+#define RTC_CALR_YEAR_Msk (0xffu << RTC_CALR_YEAR_Pos) /**< \brief (RTC_CALR) Current Year */\r
+#define RTC_CALR_YEAR(value) ((RTC_CALR_YEAR_Msk & ((value) << RTC_CALR_YEAR_Pos)))\r
+#define RTC_CALR_MONTH_Pos 16\r
+#define RTC_CALR_MONTH_Msk (0x1fu << RTC_CALR_MONTH_Pos) /**< \brief (RTC_CALR) Current Month */\r
+#define RTC_CALR_MONTH(value) ((RTC_CALR_MONTH_Msk & ((value) << RTC_CALR_MONTH_Pos)))\r
+#define RTC_CALR_DAY_Pos 21\r
+#define RTC_CALR_DAY_Msk (0x7u << RTC_CALR_DAY_Pos) /**< \brief (RTC_CALR) Current Day in Current Week */\r
+#define RTC_CALR_DAY(value) ((RTC_CALR_DAY_Msk & ((value) << RTC_CALR_DAY_Pos)))\r
+#define RTC_CALR_DATE_Pos 24\r
+#define RTC_CALR_DATE_Msk (0x3fu << RTC_CALR_DATE_Pos) /**< \brief (RTC_CALR) Current Day in Current Month */\r
+#define RTC_CALR_DATE(value) ((RTC_CALR_DATE_Msk & ((value) << RTC_CALR_DATE_Pos)))\r
+/* -------- RTC_TIMALR : (RTC Offset: 0x10) Time Alarm Register -------- */\r
+#define RTC_TIMALR_SEC_Pos 0\r
+#define RTC_TIMALR_SEC_Msk (0x7fu << RTC_TIMALR_SEC_Pos) /**< \brief (RTC_TIMALR) Second Alarm */\r
+#define RTC_TIMALR_SEC(value) ((RTC_TIMALR_SEC_Msk & ((value) << RTC_TIMALR_SEC_Pos)))\r
+#define RTC_TIMALR_SECEN (0x1u << 7) /**< \brief (RTC_TIMALR) Second Alarm Enable */\r
+#define RTC_TIMALR_MIN_Pos 8\r
+#define RTC_TIMALR_MIN_Msk (0x7fu << RTC_TIMALR_MIN_Pos) /**< \brief (RTC_TIMALR) Minute Alarm */\r
+#define RTC_TIMALR_MIN(value) ((RTC_TIMALR_MIN_Msk & ((value) << RTC_TIMALR_MIN_Pos)))\r
+#define RTC_TIMALR_MINEN (0x1u << 15) /**< \brief (RTC_TIMALR) Minute Alarm Enable */\r
+#define RTC_TIMALR_HOUR_Pos 16\r
+#define RTC_TIMALR_HOUR_Msk (0x3fu << RTC_TIMALR_HOUR_Pos) /**< \brief (RTC_TIMALR) Hour Alarm */\r
+#define RTC_TIMALR_HOUR(value) ((RTC_TIMALR_HOUR_Msk & ((value) << RTC_TIMALR_HOUR_Pos)))\r
+#define RTC_TIMALR_AMPM (0x1u << 22) /**< \brief (RTC_TIMALR) AM/PM Indicator */\r
+#define RTC_TIMALR_HOUREN (0x1u << 23) /**< \brief (RTC_TIMALR) Hour Alarm Enable */\r
+/* -------- RTC_CALALR : (RTC Offset: 0x14) Calendar Alarm Register -------- */\r
+#define RTC_CALALR_MONTH_Pos 16\r
+#define RTC_CALALR_MONTH_Msk (0x1fu << RTC_CALALR_MONTH_Pos) /**< \brief (RTC_CALALR) Month Alarm */\r
+#define RTC_CALALR_MONTH(value) ((RTC_CALALR_MONTH_Msk & ((value) << RTC_CALALR_MONTH_Pos)))\r
+#define RTC_CALALR_MTHEN (0x1u << 23) /**< \brief (RTC_CALALR) Month Alarm Enable */\r
+#define RTC_CALALR_DATE_Pos 24\r
+#define RTC_CALALR_DATE_Msk (0x3fu << RTC_CALALR_DATE_Pos) /**< \brief (RTC_CALALR) Date Alarm */\r
+#define RTC_CALALR_DATE(value) ((RTC_CALALR_DATE_Msk & ((value) << RTC_CALALR_DATE_Pos)))\r
+#define RTC_CALALR_DATEEN (0x1u << 31) /**< \brief (RTC_CALALR) Date Alarm Enable */\r
+/* -------- RTC_SR : (RTC Offset: 0x18) Status Register -------- */\r
+#define RTC_SR_ACKUPD (0x1u << 0) /**< \brief (RTC_SR) Acknowledge for Update */\r
+#define RTC_SR_ACKUPD_FREERUN (0x0u << 0) /**< \brief (RTC_SR) Time and calendar registers cannot be updated. */\r
+#define RTC_SR_ACKUPD_UPDATE (0x1u << 0) /**< \brief (RTC_SR) Time and calendar registers can be updated. */\r
+#define RTC_SR_ALARM (0x1u << 1) /**< \brief (RTC_SR) Alarm Flag */\r
+#define RTC_SR_ALARM_NO_ALARMEVENT (0x0u << 1) /**< \brief (RTC_SR) No alarm matching condition occurred. */\r
+#define RTC_SR_ALARM_ALARMEVENT (0x1u << 1) /**< \brief (RTC_SR) An alarm matching condition has occurred. */\r
+#define RTC_SR_SEC (0x1u << 2) /**< \brief (RTC_SR) Second Event */\r
+#define RTC_SR_SEC_NO_SECEVENT (0x0u << 2) /**< \brief (RTC_SR) No second event has occurred since the last clear. */\r
+#define RTC_SR_SEC_SECEVENT (0x1u << 2) /**< \brief (RTC_SR) At least one second event has occurred since the last clear. */\r
+#define RTC_SR_TIMEV (0x1u << 3) /**< \brief (RTC_SR) Time Event */\r
+#define RTC_SR_TIMEV_NO_TIMEVENT (0x0u << 3) /**< \brief (RTC_SR) No time event has occurred since the last clear. */\r
+#define RTC_SR_TIMEV_TIMEVENT (0x1u << 3) /**< \brief (RTC_SR) At least one time event has occurred since the last clear. */\r
+#define RTC_SR_CALEV (0x1u << 4) /**< \brief (RTC_SR) Calendar Event */\r
+#define RTC_SR_CALEV_NO_CALEVENT (0x0u << 4) /**< \brief (RTC_SR) No calendar event has occurred since the last clear. */\r
+#define RTC_SR_CALEV_CALEVENT (0x1u << 4) /**< \brief (RTC_SR) At least one calendar event has occurred since the last clear. */\r
+#define RTC_SR_TDERR (0x1u << 5) /**< \brief (RTC_SR) Time and/or Date Free Running Error */\r
+#define RTC_SR_TDERR_CORRECT (0x0u << 5) /**< \brief (RTC_SR) The internal free running counters are carrying valid values since the last read of RTC_SR. */\r
+#define RTC_SR_TDERR_ERR_TIMEDATE (0x1u << 5) /**< \brief (RTC_SR) The internal free running counters have been corrupted (invalid date or time, non-BCD values) since the last read and/or they are still invalid. */\r
+/* -------- RTC_SCCR : (RTC Offset: 0x1C) Status Clear Command Register -------- */\r
+#define RTC_SCCR_ACKCLR (0x1u << 0) /**< \brief (RTC_SCCR) Acknowledge Clear */\r
+#define RTC_SCCR_ALRCLR (0x1u << 1) /**< \brief (RTC_SCCR) Alarm Clear */\r
+#define RTC_SCCR_SECCLR (0x1u << 2) /**< \brief (RTC_SCCR) Second Clear */\r
+#define RTC_SCCR_TIMCLR (0x1u << 3) /**< \brief (RTC_SCCR) Time Clear */\r
+#define RTC_SCCR_CALCLR (0x1u << 4) /**< \brief (RTC_SCCR) Calendar Clear */\r
+#define RTC_SCCR_TDERRCLR (0x1u << 5) /**< \brief (RTC_SCCR) Time and/or Date Free Running Error Clear */\r
+/* -------- RTC_IER : (RTC Offset: 0x20) Interrupt Enable Register -------- */\r
+#define RTC_IER_ACKEN (0x1u << 0) /**< \brief (RTC_IER) Acknowledge Update Interrupt Enable */\r
+#define RTC_IER_ALREN (0x1u << 1) /**< \brief (RTC_IER) Alarm Interrupt Enable */\r
+#define RTC_IER_SECEN (0x1u << 2) /**< \brief (RTC_IER) Second Event Interrupt Enable */\r
+#define RTC_IER_TIMEN (0x1u << 3) /**< \brief (RTC_IER) Time Event Interrupt Enable */\r
+#define RTC_IER_CALEN (0x1u << 4) /**< \brief (RTC_IER) Calendar Event Interrupt Enable */\r
+#define RTC_IER_TDERREN (0x1u << 5) /**< \brief (RTC_IER) Time and/or Date Error Interrupt Enable */\r
+/* -------- RTC_IDR : (RTC Offset: 0x24) Interrupt Disable Register -------- */\r
+#define RTC_IDR_ACKDIS (0x1u << 0) /**< \brief (RTC_IDR) Acknowledge Update Interrupt Disable */\r
+#define RTC_IDR_ALRDIS (0x1u << 1) /**< \brief (RTC_IDR) Alarm Interrupt Disable */\r
+#define RTC_IDR_SECDIS (0x1u << 2) /**< \brief (RTC_IDR) Second Event Interrupt Disable */\r
+#define RTC_IDR_TIMDIS (0x1u << 3) /**< \brief (RTC_IDR) Time Event Interrupt Disable */\r
+#define RTC_IDR_CALDIS (0x1u << 4) /**< \brief (RTC_IDR) Calendar Event Interrupt Disable */\r
+#define RTC_IDR_TDERRDIS (0x1u << 5) /**< \brief (RTC_IDR) Time and/or Date Error Interrupt Disable */\r
+/* -------- RTC_IMR : (RTC Offset: 0x28) Interrupt Mask Register -------- */\r
+#define RTC_IMR_ACK (0x1u << 0) /**< \brief (RTC_IMR) Acknowledge Update Interrupt Mask */\r
+#define RTC_IMR_ALR (0x1u << 1) /**< \brief (RTC_IMR) Alarm Interrupt Mask */\r
+#define RTC_IMR_SEC (0x1u << 2) /**< \brief (RTC_IMR) Second Event Interrupt Mask */\r
+#define RTC_IMR_TIM (0x1u << 3) /**< \brief (RTC_IMR) Time Event Interrupt Mask */\r
+#define RTC_IMR_CAL (0x1u << 4) /**< \brief (RTC_IMR) Calendar Event Interrupt Mask */\r
+/* -------- RTC_VER : (RTC Offset: 0x2C) Valid Entry Register -------- */\r
+#define RTC_VER_NVTIM (0x1u << 0) /**< \brief (RTC_VER) Non-valid Time */\r
+#define RTC_VER_NVCAL (0x1u << 1) /**< \brief (RTC_VER) Non-valid Calendar */\r
+#define RTC_VER_NVTIMALR (0x1u << 2) /**< \brief (RTC_VER) Non-valid Time Alarm */\r
+#define RTC_VER_NVCALALR (0x1u << 3) /**< \brief (RTC_VER) Non-valid Calendar Alarm */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM4E_RTC_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4E_RTT_COMPONENT_\r
+#define _SAM4E_RTT_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Real-time Timer */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM4E_RTT Real-time Timer */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Rtt hardware registers */\r
+typedef struct {\r
+ RwReg RTT_MR; /**< \brief (Rtt Offset: 0x00) Mode Register */\r
+ RwReg RTT_AR; /**< \brief (Rtt Offset: 0x04) Alarm Register */\r
+ RoReg RTT_VR; /**< \brief (Rtt Offset: 0x08) Value Register */\r
+ RoReg RTT_SR; /**< \brief (Rtt Offset: 0x0C) Status Register */\r
+} Rtt;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- RTT_MR : (RTT Offset: 0x00) Mode Register -------- */\r
+#define RTT_MR_RTPRES_Pos 0\r
+#define RTT_MR_RTPRES_Msk (0xffffu << RTT_MR_RTPRES_Pos) /**< \brief (RTT_MR) Real-time Timer Prescaler Value */\r
+#define RTT_MR_RTPRES(value) ((RTT_MR_RTPRES_Msk & ((value) << RTT_MR_RTPRES_Pos)))\r
+#define RTT_MR_ALMIEN (0x1u << 16) /**< \brief (RTT_MR) Alarm Interrupt Enable */\r
+#define RTT_MR_RTTINCIEN (0x1u << 17) /**< \brief (RTT_MR) Real-time Timer Increment Interrupt Enable */\r
+#define RTT_MR_RTTRST (0x1u << 18) /**< \brief (RTT_MR) Real-time Timer Restart */\r
+#define RTT_MR_RTTDIS (0x1u << 20) /**< \brief (RTT_MR) Real-time Timer Disable */\r
+#define RTT_MR_RTC1HZ (0x1u << 24) /**< \brief (RTT_MR) Real-Time Clock 1Hz Clock Selection */\r
+/* -------- RTT_AR : (RTT Offset: 0x04) Alarm Register -------- */\r
+#define RTT_AR_ALMV_Pos 0\r
+#define RTT_AR_ALMV_Msk (0xffffffffu << RTT_AR_ALMV_Pos) /**< \brief (RTT_AR) Alarm Value */\r
+#define RTT_AR_ALMV(value) ((RTT_AR_ALMV_Msk & ((value) << RTT_AR_ALMV_Pos)))\r
+/* -------- RTT_VR : (RTT Offset: 0x08) Value Register -------- */\r
+#define RTT_VR_CRTV_Pos 0\r
+#define RTT_VR_CRTV_Msk (0xffffffffu << RTT_VR_CRTV_Pos) /**< \brief (RTT_VR) Current Real-time Value */\r
+/* -------- RTT_SR : (RTT Offset: 0x0C) Status Register -------- */\r
+#define RTT_SR_ALMS (0x1u << 0) /**< \brief (RTT_SR) Real-time Alarm Status */\r
+#define RTT_SR_RTTINC (0x1u << 1) /**< \brief (RTT_SR) Real-time Timer Increment */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM4E_RTT_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4E_SMC_COMPONENT_\r
+#define _SAM4E_SMC_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Static Memory Controller */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM4E_SMC Static Memory Controller */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief SmcCs_number hardware registers */\r
+typedef struct {\r
+ RwReg SMC_SETUP; /**< \brief (SmcCs_number Offset: 0x0) SMC Setup Register */\r
+ RwReg SMC_PULSE; /**< \brief (SmcCs_number Offset: 0x4) SMC Pulse Register */\r
+ RwReg SMC_CYCLE; /**< \brief (SmcCs_number Offset: 0x8) SMC Cycle Register */\r
+ RwReg SMC_MODE; /**< \brief (SmcCs_number Offset: 0xC) SMC Mode Register */\r
+} SmcCs_number;\r
+/** \brief Smc hardware registers */\r
+#define SMCCS_NUMBER_NUMBER 4\r
+typedef struct {\r
+ SmcCs_number SMC_CS_NUMBER[SMCCS_NUMBER_NUMBER]; /**< \brief (Smc Offset: 0x0) CS_number = 0 .. 3 */\r
+ RoReg Reserved1[16];\r
+ RwReg SMC_OCMS; /**< \brief (Smc Offset: 0x80) SMC OCMS MODE Register */\r
+ WoReg SMC_KEY1; /**< \brief (Smc Offset: 0x84) SMC OCMS KEY1 Register */\r
+ WoReg SMC_KEY2; /**< \brief (Smc Offset: 0x88) SMC OCMS KEY2 Register */\r
+ RoReg Reserved2[22];\r
+ RwReg SMC_WPMR; /**< \brief (Smc Offset: 0xE4) SMC Write Protect Mode Register */\r
+ RoReg SMC_WPSR; /**< \brief (Smc Offset: 0xE8) SMC Write Protect Status Register */\r
+} Smc;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- SMC_SETUP : (SMC Offset: N/A) SMC Setup Register -------- */\r
+#define SMC_SETUP_NWE_SETUP_Pos 0\r
+#define SMC_SETUP_NWE_SETUP_Msk (0x3fu << SMC_SETUP_NWE_SETUP_Pos) /**< \brief (SMC_SETUP) NWE Setup Length */\r
+#define SMC_SETUP_NWE_SETUP(value) ((SMC_SETUP_NWE_SETUP_Msk & ((value) << SMC_SETUP_NWE_SETUP_Pos)))\r
+#define SMC_SETUP_NCS_WR_SETUP_Pos 8\r
+#define SMC_SETUP_NCS_WR_SETUP_Msk (0x3fu << SMC_SETUP_NCS_WR_SETUP_Pos) /**< \brief (SMC_SETUP) NCS Setup Length in WRITE Access */\r
+#define SMC_SETUP_NCS_WR_SETUP(value) ((SMC_SETUP_NCS_WR_SETUP_Msk & ((value) << SMC_SETUP_NCS_WR_SETUP_Pos)))\r
+#define SMC_SETUP_NRD_SETUP_Pos 16\r
+#define SMC_SETUP_NRD_SETUP_Msk (0x3fu << SMC_SETUP_NRD_SETUP_Pos) /**< \brief (SMC_SETUP) NRD Setup Length */\r
+#define SMC_SETUP_NRD_SETUP(value) ((SMC_SETUP_NRD_SETUP_Msk & ((value) << SMC_SETUP_NRD_SETUP_Pos)))\r
+#define SMC_SETUP_NCS_RD_SETUP_Pos 24\r
+#define SMC_SETUP_NCS_RD_SETUP_Msk (0x3fu << SMC_SETUP_NCS_RD_SETUP_Pos) /**< \brief (SMC_SETUP) NCS Setup Length in READ Access */\r
+#define SMC_SETUP_NCS_RD_SETUP(value) ((SMC_SETUP_NCS_RD_SETUP_Msk & ((value) << SMC_SETUP_NCS_RD_SETUP_Pos)))\r
+/* -------- SMC_PULSE : (SMC Offset: N/A) SMC Pulse Register -------- */\r
+#define SMC_PULSE_NWE_PULSE_Pos 0\r
+#define SMC_PULSE_NWE_PULSE_Msk (0x7fu << SMC_PULSE_NWE_PULSE_Pos) /**< \brief (SMC_PULSE) NWE Pulse Length */\r
+#define SMC_PULSE_NWE_PULSE(value) ((SMC_PULSE_NWE_PULSE_Msk & ((value) << SMC_PULSE_NWE_PULSE_Pos)))\r
+#define SMC_PULSE_NCS_WR_PULSE_Pos 8\r
+#define SMC_PULSE_NCS_WR_PULSE_Msk (0x7fu << SMC_PULSE_NCS_WR_PULSE_Pos) /**< \brief (SMC_PULSE) NCS Pulse Length in WRITE Access */\r
+#define SMC_PULSE_NCS_WR_PULSE(value) ((SMC_PULSE_NCS_WR_PULSE_Msk & ((value) << SMC_PULSE_NCS_WR_PULSE_Pos)))\r
+#define SMC_PULSE_NRD_PULSE_Pos 16\r
+#define SMC_PULSE_NRD_PULSE_Msk (0x7fu << SMC_PULSE_NRD_PULSE_Pos) /**< \brief (SMC_PULSE) NRD Pulse Length */\r
+#define SMC_PULSE_NRD_PULSE(value) ((SMC_PULSE_NRD_PULSE_Msk & ((value) << SMC_PULSE_NRD_PULSE_Pos)))\r
+#define SMC_PULSE_NCS_RD_PULSE_Pos 24\r
+#define SMC_PULSE_NCS_RD_PULSE_Msk (0x7fu << SMC_PULSE_NCS_RD_PULSE_Pos) /**< \brief (SMC_PULSE) NCS Pulse Length in READ Access */\r
+#define SMC_PULSE_NCS_RD_PULSE(value) ((SMC_PULSE_NCS_RD_PULSE_Msk & ((value) << SMC_PULSE_NCS_RD_PULSE_Pos)))\r
+/* -------- SMC_CYCLE : (SMC Offset: N/A) SMC Cycle Register -------- */\r
+#define SMC_CYCLE_NWE_CYCLE_Pos 0\r
+#define SMC_CYCLE_NWE_CYCLE_Msk (0x1ffu << SMC_CYCLE_NWE_CYCLE_Pos) /**< \brief (SMC_CYCLE) Total Write Cycle Length */\r
+#define SMC_CYCLE_NWE_CYCLE(value) ((SMC_CYCLE_NWE_CYCLE_Msk & ((value) << SMC_CYCLE_NWE_CYCLE_Pos)))\r
+#define SMC_CYCLE_NRD_CYCLE_Pos 16\r
+#define SMC_CYCLE_NRD_CYCLE_Msk (0x1ffu << SMC_CYCLE_NRD_CYCLE_Pos) /**< \brief (SMC_CYCLE) Total Read Cycle Length */\r
+#define SMC_CYCLE_NRD_CYCLE(value) ((SMC_CYCLE_NRD_CYCLE_Msk & ((value) << SMC_CYCLE_NRD_CYCLE_Pos)))\r
+/* -------- SMC_MODE : (SMC Offset: N/A) SMC Mode Register -------- */\r
+#define SMC_MODE_READ_MODE (0x1u << 0) /**< \brief (SMC_MODE) */\r
+#define SMC_MODE_WRITE_MODE (0x1u << 1) /**< \brief (SMC_MODE) */\r
+#define SMC_MODE_EXNW_MODE_Pos 4\r
+#define SMC_MODE_EXNW_MODE_Msk (0x3u << SMC_MODE_EXNW_MODE_Pos) /**< \brief (SMC_MODE) NWAIT Mode */\r
+#define SMC_MODE_EXNW_MODE_DISABLED (0x0u << 4) /**< \brief (SMC_MODE) Disabled */\r
+#define SMC_MODE_EXNW_MODE_FROZEN (0x2u << 4) /**< \brief (SMC_MODE) Frozen Mode */\r
+#define SMC_MODE_EXNW_MODE_READY (0x3u << 4) /**< \brief (SMC_MODE) Ready Mode */\r
+#define SMC_MODE_TDF_CYCLES_Pos 16\r
+#define SMC_MODE_TDF_CYCLES_Msk (0xfu << SMC_MODE_TDF_CYCLES_Pos) /**< \brief (SMC_MODE) Data Float Time */\r
+#define SMC_MODE_TDF_CYCLES(value) ((SMC_MODE_TDF_CYCLES_Msk & ((value) << SMC_MODE_TDF_CYCLES_Pos)))\r
+#define SMC_MODE_TDF_MODE (0x1u << 20) /**< \brief (SMC_MODE) TDF Optimization */\r
+#define SMC_MODE_PMEN (0x1u << 24) /**< \brief (SMC_MODE) Page Mode Enabled */\r
+#define SMC_MODE_PS_Pos 28\r
+#define SMC_MODE_PS_Msk (0x3u << SMC_MODE_PS_Pos) /**< \brief (SMC_MODE) Page Size */\r
+#define SMC_MODE_PS_4_BYTE (0x0u << 28) /**< \brief (SMC_MODE) 4-byte page */\r
+#define SMC_MODE_PS_8_BYTE (0x1u << 28) /**< \brief (SMC_MODE) 8-byte page */\r
+#define SMC_MODE_PS_16_BYTE (0x2u << 28) /**< \brief (SMC_MODE) 16-byte page */\r
+#define SMC_MODE_PS_32_BYTE (0x3u << 28) /**< \brief (SMC_MODE) 32-byte page */\r
+/* -------- SMC_OCMS : (SMC Offset: 0x80) SMC OCMS MODE Register -------- */\r
+#define SMC_OCMS_SMSE (0x1u << 0) /**< \brief (SMC_OCMS) Static Memory Controller Scrambling Enable */\r
+#define SMC_OCMS_CS0SE (0x1u << 16) /**< \brief (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable */\r
+#define SMC_OCMS_CS1SE (0x1u << 17) /**< \brief (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable */\r
+#define SMC_OCMS_CS2SE (0x1u << 18) /**< \brief (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable */\r
+#define SMC_OCMS_CS3SE (0x1u << 19) /**< \brief (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable */\r
+/* -------- SMC_KEY1 : (SMC Offset: 0x84) SMC OCMS KEY1 Register -------- */\r
+#define SMC_KEY1_KEY1_Pos 0\r
+#define SMC_KEY1_KEY1_Msk (0xffffffffu << SMC_KEY1_KEY1_Pos) /**< \brief (SMC_KEY1) Off Chip Memory Scrambling (OCMS) Key Part 1 */\r
+#define SMC_KEY1_KEY1(value) ((SMC_KEY1_KEY1_Msk & ((value) << SMC_KEY1_KEY1_Pos)))\r
+/* -------- SMC_KEY2 : (SMC Offset: 0x88) SMC OCMS KEY2 Register -------- */\r
+#define SMC_KEY2_KEY2_Pos 0\r
+#define SMC_KEY2_KEY2_Msk (0xffffffffu << SMC_KEY2_KEY2_Pos) /**< \brief (SMC_KEY2) Off Chip Memory Scrambling (OCMS) Key Part 2 */\r
+#define SMC_KEY2_KEY2(value) ((SMC_KEY2_KEY2_Msk & ((value) << SMC_KEY2_KEY2_Pos)))\r
+/* -------- SMC_WPMR : (SMC Offset: 0xE4) SMC Write Protect Mode Register -------- */\r
+#define SMC_WPMR_WPEN (0x1u << 0) /**< \brief (SMC_WPMR) Write Protect Enable */\r
+#define SMC_WPMR_WPKEY_Pos 8\r
+#define SMC_WPMR_WPKEY_Msk (0xffffffu << SMC_WPMR_WPKEY_Pos) /**< \brief (SMC_WPMR) Write Protect KEY */\r
+#define SMC_WPMR_WPKEY(value) ((SMC_WPMR_WPKEY_Msk & ((value) << SMC_WPMR_WPKEY_Pos)))\r
+/* -------- SMC_WPSR : (SMC Offset: 0xE8) SMC Write Protect Status Register -------- */\r
+#define SMC_WPSR_WPVS (0x1u << 0) /**< \brief (SMC_WPSR) Write Protect Enable */\r
+#define SMC_WPSR_WPVSRC_Pos 8\r
+#define SMC_WPSR_WPVSRC_Msk (0xffffu << SMC_WPSR_WPVSRC_Pos) /**< \brief (SMC_WPSR) Write Protect Violation Source */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM4E_SMC_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4E_SPI_COMPONENT_\r
+#define _SAM4E_SPI_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Serial Peripheral Interface */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM4E_SPI Serial Peripheral Interface */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Spi hardware registers */\r
+typedef struct {\r
+ WoReg SPI_CR; /**< \brief (Spi Offset: 0x00) Control Register */\r
+ RwReg SPI_MR; /**< \brief (Spi Offset: 0x04) Mode Register */\r
+ RoReg SPI_RDR; /**< \brief (Spi Offset: 0x08) Receive Data Register */\r
+ WoReg SPI_TDR; /**< \brief (Spi Offset: 0x0C) Transmit Data Register */\r
+ RoReg SPI_SR; /**< \brief (Spi Offset: 0x10) Status Register */\r
+ WoReg SPI_IER; /**< \brief (Spi Offset: 0x14) Interrupt Enable Register */\r
+ WoReg SPI_IDR; /**< \brief (Spi Offset: 0x18) Interrupt Disable Register */\r
+ RoReg SPI_IMR; /**< \brief (Spi Offset: 0x1C) Interrupt Mask Register */\r
+ RoReg Reserved1[4];\r
+ RwReg SPI_CSR[4]; /**< \brief (Spi Offset: 0x30) Chip Select Register */\r
+ RoReg Reserved2[41];\r
+ RwReg SPI_WPMR; /**< \brief (Spi Offset: 0xE4) Write Protection Control Register */\r
+ RoReg SPI_WPSR; /**< \brief (Spi Offset: 0xE8) Write Protection Status Register */\r
+ RoReg Reserved3[5];\r
+ RwReg SPI_RPR; /**< \brief (Spi Offset: 0x100) Receive Pointer Register */\r
+ RwReg SPI_RCR; /**< \brief (Spi Offset: 0x104) Receive Counter Register */\r
+ RwReg SPI_TPR; /**< \brief (Spi Offset: 0x108) Transmit Pointer Register */\r
+ RwReg SPI_TCR; /**< \brief (Spi Offset: 0x10C) Transmit Counter Register */\r
+ RwReg SPI_RNPR; /**< \brief (Spi Offset: 0x110) Receive Next Pointer Register */\r
+ RwReg SPI_RNCR; /**< \brief (Spi Offset: 0x114) Receive Next Counter Register */\r
+ RwReg SPI_TNPR; /**< \brief (Spi Offset: 0x118) Transmit Next Pointer Register */\r
+ RwReg SPI_TNCR; /**< \brief (Spi Offset: 0x11C) Transmit Next Counter Register */\r
+ WoReg SPI_PTCR; /**< \brief (Spi Offset: 0x120) Transfer Control Register */\r
+ RoReg SPI_PTSR; /**< \brief (Spi Offset: 0x124) Transfer Status Register */\r
+} Spi;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- SPI_CR : (SPI Offset: 0x00) Control Register -------- */\r
+#define SPI_CR_SPIEN (0x1u << 0) /**< \brief (SPI_CR) SPI Enable */\r
+#define SPI_CR_SPIDIS (0x1u << 1) /**< \brief (SPI_CR) SPI Disable */\r
+#define SPI_CR_SWRST (0x1u << 7) /**< \brief (SPI_CR) SPI Software Reset */\r
+#define SPI_CR_LASTXFER (0x1u << 24) /**< \brief (SPI_CR) Last Transfer */\r
+/* -------- SPI_MR : (SPI Offset: 0x04) Mode Register -------- */\r
+#define SPI_MR_MSTR (0x1u << 0) /**< \brief (SPI_MR) Master/Slave Mode */\r
+#define SPI_MR_PS (0x1u << 1) /**< \brief (SPI_MR) Peripheral Select */\r
+#define SPI_MR_PCSDEC (0x1u << 2) /**< \brief (SPI_MR) Chip Select Decode */\r
+#define SPI_MR_MODFDIS (0x1u << 4) /**< \brief (SPI_MR) Mode Fault Detection */\r
+#define SPI_MR_WDRBT (0x1u << 5) /**< \brief (SPI_MR) Wait Data Read Before Transfer */\r
+#define SPI_MR_LLB (0x1u << 7) /**< \brief (SPI_MR) Local Loopback Enable */\r
+#define SPI_MR_PCS_Pos 16\r
+#define SPI_MR_PCS_Msk (0xfu << SPI_MR_PCS_Pos) /**< \brief (SPI_MR) Peripheral Chip Select */\r
+#define SPI_MR_PCS(value) ((SPI_MR_PCS_Msk & ((value) << SPI_MR_PCS_Pos)))\r
+#define SPI_MR_DLYBCS_Pos 24\r
+#define SPI_MR_DLYBCS_Msk (0xffu << SPI_MR_DLYBCS_Pos) /**< \brief (SPI_MR) Delay Between Chip Selects */\r
+#define SPI_MR_DLYBCS(value) ((SPI_MR_DLYBCS_Msk & ((value) << SPI_MR_DLYBCS_Pos)))\r
+/* -------- SPI_RDR : (SPI Offset: 0x08) Receive Data Register -------- */\r
+#define SPI_RDR_RD_Pos 0\r
+#define SPI_RDR_RD_Msk (0xffffu << SPI_RDR_RD_Pos) /**< \brief (SPI_RDR) Receive Data */\r
+#define SPI_RDR_PCS_Pos 16\r
+#define SPI_RDR_PCS_Msk (0xfu << SPI_RDR_PCS_Pos) /**< \brief (SPI_RDR) Peripheral Chip Select */\r
+/* -------- SPI_TDR : (SPI Offset: 0x0C) Transmit Data Register -------- */\r
+#define SPI_TDR_TD_Pos 0\r
+#define SPI_TDR_TD_Msk (0xffffu << SPI_TDR_TD_Pos) /**< \brief (SPI_TDR) Transmit Data */\r
+#define SPI_TDR_TD(value) ((SPI_TDR_TD_Msk & ((value) << SPI_TDR_TD_Pos)))\r
+#define SPI_TDR_PCS_Pos 16\r
+#define SPI_TDR_PCS_Msk (0xfu << SPI_TDR_PCS_Pos) /**< \brief (SPI_TDR) Peripheral Chip Select */\r
+#define SPI_TDR_PCS(value) ((SPI_TDR_PCS_Msk & ((value) << SPI_TDR_PCS_Pos)))\r
+#define SPI_TDR_LASTXFER (0x1u << 24) /**< \brief (SPI_TDR) Last Transfer */\r
+/* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */\r
+#define SPI_SR_RDRF (0x1u << 0) /**< \brief (SPI_SR) Receive Data Register Full */\r
+#define SPI_SR_TDRE (0x1u << 1) /**< \brief (SPI_SR) Transmit Data Register Empty */\r
+#define SPI_SR_MODF (0x1u << 2) /**< \brief (SPI_SR) Mode Fault Error */\r
+#define SPI_SR_OVRES (0x1u << 3) /**< \brief (SPI_SR) Overrun Error Status */\r
+#define SPI_SR_ENDRX (0x1u << 4) /**< \brief (SPI_SR) End of RX buffer */\r
+#define SPI_SR_ENDTX (0x1u << 5) /**< \brief (SPI_SR) End of TX buffer */\r
+#define SPI_SR_RXBUFF (0x1u << 6) /**< \brief (SPI_SR) RX Buffer Full */\r
+#define SPI_SR_TXBUFE (0x1u << 7) /**< \brief (SPI_SR) TX Buffer Empty */\r
+#define SPI_SR_NSSR (0x1u << 8) /**< \brief (SPI_SR) NSS Rising */\r
+#define SPI_SR_TXEMPTY (0x1u << 9) /**< \brief (SPI_SR) Transmission Registers Empty */\r
+#define SPI_SR_UNDES (0x1u << 10) /**< \brief (SPI_SR) Underrun Error Status (Slave Mode Only) */\r
+#define SPI_SR_SPIENS (0x1u << 16) /**< \brief (SPI_SR) SPI Enable Status */\r
+/* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */\r
+#define SPI_IER_RDRF (0x1u << 0) /**< \brief (SPI_IER) Receive Data Register Full Interrupt Enable */\r
+#define SPI_IER_TDRE (0x1u << 1) /**< \brief (SPI_IER) SPI Transmit Data Register Empty Interrupt Enable */\r
+#define SPI_IER_MODF (0x1u << 2) /**< \brief (SPI_IER) Mode Fault Error Interrupt Enable */\r
+#define SPI_IER_OVRES (0x1u << 3) /**< \brief (SPI_IER) Overrun Error Interrupt Enable */\r
+#define SPI_IER_ENDRX (0x1u << 4) /**< \brief (SPI_IER) End of Receive Buffer Interrupt Enable */\r
+#define SPI_IER_ENDTX (0x1u << 5) /**< \brief (SPI_IER) End of Transmit Buffer Interrupt Enable */\r
+#define SPI_IER_RXBUFF (0x1u << 6) /**< \brief (SPI_IER) Receive Buffer Full Interrupt Enable */\r
+#define SPI_IER_TXBUFE (0x1u << 7) /**< \brief (SPI_IER) Transmit Buffer Empty Interrupt Enable */\r
+#define SPI_IER_NSSR (0x1u << 8) /**< \brief (SPI_IER) NSS Rising Interrupt Enable */\r
+#define SPI_IER_TXEMPTY (0x1u << 9) /**< \brief (SPI_IER) Transmission Registers Empty Enable */\r
+#define SPI_IER_UNDES (0x1u << 10) /**< \brief (SPI_IER) Underrun Error Interrupt Enable */\r
+/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */\r
+#define SPI_IDR_RDRF (0x1u << 0) /**< \brief (SPI_IDR) Receive Data Register Full Interrupt Disable */\r
+#define SPI_IDR_TDRE (0x1u << 1) /**< \brief (SPI_IDR) SPI Transmit Data Register Empty Interrupt Disable */\r
+#define SPI_IDR_MODF (0x1u << 2) /**< \brief (SPI_IDR) Mode Fault Error Interrupt Disable */\r
+#define SPI_IDR_OVRES (0x1u << 3) /**< \brief (SPI_IDR) Overrun Error Interrupt Disable */\r
+#define SPI_IDR_ENDRX (0x1u << 4) /**< \brief (SPI_IDR) End of Receive Buffer Interrupt Disable */\r
+#define SPI_IDR_ENDTX (0x1u << 5) /**< \brief (SPI_IDR) End of Transmit Buffer Interrupt Disable */\r
+#define SPI_IDR_RXBUFF (0x1u << 6) /**< \brief (SPI_IDR) Receive Buffer Full Interrupt Disable */\r
+#define SPI_IDR_TXBUFE (0x1u << 7) /**< \brief (SPI_IDR) Transmit Buffer Empty Interrupt Disable */\r
+#define SPI_IDR_NSSR (0x1u << 8) /**< \brief (SPI_IDR) NSS Rising Interrupt Disable */\r
+#define SPI_IDR_TXEMPTY (0x1u << 9) /**< \brief (SPI_IDR) Transmission Registers Empty Disable */\r
+#define SPI_IDR_UNDES (0x1u << 10) /**< \brief (SPI_IDR) Underrun Error Interrupt Disable */\r
+/* -------- SPI_IMR : (SPI Offset: 0x1C) Interrupt Mask Register -------- */\r
+#define SPI_IMR_RDRF (0x1u << 0) /**< \brief (SPI_IMR) Receive Data Register Full Interrupt Mask */\r
+#define SPI_IMR_TDRE (0x1u << 1) /**< \brief (SPI_IMR) SPI Transmit Data Register Empty Interrupt Mask */\r
+#define SPI_IMR_MODF (0x1u << 2) /**< \brief (SPI_IMR) Mode Fault Error Interrupt Mask */\r
+#define SPI_IMR_OVRES (0x1u << 3) /**< \brief (SPI_IMR) Overrun Error Interrupt Mask */\r
+#define SPI_IMR_ENDRX (0x1u << 4) /**< \brief (SPI_IMR) End of Receive Buffer Interrupt Mask */\r
+#define SPI_IMR_ENDTX (0x1u << 5) /**< \brief (SPI_IMR) End of Transmit Buffer Interrupt Mask */\r
+#define SPI_IMR_RXBUFF (0x1u << 6) /**< \brief (SPI_IMR) Receive Buffer Full Interrupt Mask */\r
+#define SPI_IMR_TXBUFE (0x1u << 7) /**< \brief (SPI_IMR) Transmit Buffer Empty Interrupt Mask */\r
+#define SPI_IMR_NSSR (0x1u << 8) /**< \brief (SPI_IMR) NSS Rising Interrupt Mask */\r
+#define SPI_IMR_TXEMPTY (0x1u << 9) /**< \brief (SPI_IMR) Transmission Registers Empty Mask */\r
+#define SPI_IMR_UNDES (0x1u << 10) /**< \brief (SPI_IMR) Underrun Error Interrupt Mask */\r
+/* -------- SPI_CSR[4] : (SPI Offset: 0x30) Chip Select Register -------- */\r
+#define SPI_CSR_CPOL (0x1u << 0) /**< \brief (SPI_CSR[4]) Clock Polarity */\r
+#define SPI_CSR_NCPHA (0x1u << 1) /**< \brief (SPI_CSR[4]) Clock Phase */\r
+#define SPI_CSR_CSNAAT (0x1u << 2) /**< \brief (SPI_CSR[4]) Chip Select Not Active After Transfer (Ignored if CSAAT = 1) */\r
+#define SPI_CSR_CSAAT (0x1u << 3) /**< \brief (SPI_CSR[4]) Chip Select Active After Transfer */\r
+#define SPI_CSR_BITS_Pos 4\r
+#define SPI_CSR_BITS_Msk (0xfu << SPI_CSR_BITS_Pos) /**< \brief (SPI_CSR[4]) Bits Per Transfer */\r
+#define SPI_CSR_BITS_8_BIT (0x0u << 4) /**< \brief (SPI_CSR[4]) 8 bits for transfer */\r
+#define SPI_CSR_BITS_9_BIT (0x1u << 4) /**< \brief (SPI_CSR[4]) 9 bits for transfer */\r
+#define SPI_CSR_BITS_10_BIT (0x2u << 4) /**< \brief (SPI_CSR[4]) 10 bits for transfer */\r
+#define SPI_CSR_BITS_11_BIT (0x3u << 4) /**< \brief (SPI_CSR[4]) 11 bits for transfer */\r
+#define SPI_CSR_BITS_12_BIT (0x4u << 4) /**< \brief (SPI_CSR[4]) 12 bits for transfer */\r
+#define SPI_CSR_BITS_13_BIT (0x5u << 4) /**< \brief (SPI_CSR[4]) 13 bits for transfer */\r
+#define SPI_CSR_BITS_14_BIT (0x6u << 4) /**< \brief (SPI_CSR[4]) 14 bits for transfer */\r
+#define SPI_CSR_BITS_15_BIT (0x7u << 4) /**< \brief (SPI_CSR[4]) 15 bits for transfer */\r
+#define SPI_CSR_BITS_16_BIT (0x8u << 4) /**< \brief (SPI_CSR[4]) 16 bits for transfer */\r
+#define SPI_CSR_SCBR_Pos 8\r
+#define SPI_CSR_SCBR_Msk (0xffu << SPI_CSR_SCBR_Pos) /**< \brief (SPI_CSR[4]) Serial Clock Baud Rate */\r
+#define SPI_CSR_SCBR(value) ((SPI_CSR_SCBR_Msk & ((value) << SPI_CSR_SCBR_Pos)))\r
+#define SPI_CSR_DLYBS_Pos 16\r
+#define SPI_CSR_DLYBS_Msk (0xffu << SPI_CSR_DLYBS_Pos) /**< \brief (SPI_CSR[4]) Delay Before SPCK */\r
+#define SPI_CSR_DLYBS(value) ((SPI_CSR_DLYBS_Msk & ((value) << SPI_CSR_DLYBS_Pos)))\r
+#define SPI_CSR_DLYBCT_Pos 24\r
+#define SPI_CSR_DLYBCT_Msk (0xffu << SPI_CSR_DLYBCT_Pos) /**< \brief (SPI_CSR[4]) Delay Between Consecutive Transfers */\r
+#define SPI_CSR_DLYBCT(value) ((SPI_CSR_DLYBCT_Msk & ((value) << SPI_CSR_DLYBCT_Pos)))\r
+/* -------- SPI_WPMR : (SPI Offset: 0xE4) Write Protection Control Register -------- */\r
+#define SPI_WPMR_WPEN (0x1u << 0) /**< \brief (SPI_WPMR) Write Protection Enable */\r
+#define SPI_WPMR_WPKEY_Pos 8\r
+#define SPI_WPMR_WPKEY_Msk (0xffffffu << SPI_WPMR_WPKEY_Pos) /**< \brief (SPI_WPMR) Write Protection Key Password */\r
+#define SPI_WPMR_WPKEY(value) ((SPI_WPMR_WPKEY_Msk & ((value) << SPI_WPMR_WPKEY_Pos)))\r
+/* -------- SPI_WPSR : (SPI Offset: 0xE8) Write Protection Status Register -------- */\r
+#define SPI_WPSR_WPVS (0x1u << 0) /**< \brief (SPI_WPSR) Write Protection Violation Status */\r
+#define SPI_WPSR_WPVSRC_Pos 8\r
+#define SPI_WPSR_WPVSRC_Msk (0xffu << SPI_WPSR_WPVSRC_Pos) /**< \brief (SPI_WPSR) Write Protection Violation Source */\r
+/* -------- SPI_RPR : (SPI Offset: 0x100) Receive Pointer Register -------- */\r
+#define SPI_RPR_RXPTR_Pos 0\r
+#define SPI_RPR_RXPTR_Msk (0xffffffffu << SPI_RPR_RXPTR_Pos) /**< \brief (SPI_RPR) Receive Pointer Register */\r
+#define SPI_RPR_RXPTR(value) ((SPI_RPR_RXPTR_Msk & ((value) << SPI_RPR_RXPTR_Pos)))\r
+/* -------- SPI_RCR : (SPI Offset: 0x104) Receive Counter Register -------- */\r
+#define SPI_RCR_RXCTR_Pos 0\r
+#define SPI_RCR_RXCTR_Msk (0xffffu << SPI_RCR_RXCTR_Pos) /**< \brief (SPI_RCR) Receive Counter Register */\r
+#define SPI_RCR_RXCTR(value) ((SPI_RCR_RXCTR_Msk & ((value) << SPI_RCR_RXCTR_Pos)))\r
+/* -------- SPI_TPR : (SPI Offset: 0x108) Transmit Pointer Register -------- */\r
+#define SPI_TPR_TXPTR_Pos 0\r
+#define SPI_TPR_TXPTR_Msk (0xffffffffu << SPI_TPR_TXPTR_Pos) /**< \brief (SPI_TPR) Transmit Counter Register */\r
+#define SPI_TPR_TXPTR(value) ((SPI_TPR_TXPTR_Msk & ((value) << SPI_TPR_TXPTR_Pos)))\r
+/* -------- SPI_TCR : (SPI Offset: 0x10C) Transmit Counter Register -------- */\r
+#define SPI_TCR_TXCTR_Pos 0\r
+#define SPI_TCR_TXCTR_Msk (0xffffu << SPI_TCR_TXCTR_Pos) /**< \brief (SPI_TCR) Transmit Counter Register */\r
+#define SPI_TCR_TXCTR(value) ((SPI_TCR_TXCTR_Msk & ((value) << SPI_TCR_TXCTR_Pos)))\r
+/* -------- SPI_RNPR : (SPI Offset: 0x110) Receive Next Pointer Register -------- */\r
+#define SPI_RNPR_RXNPTR_Pos 0\r
+#define SPI_RNPR_RXNPTR_Msk (0xffffffffu << SPI_RNPR_RXNPTR_Pos) /**< \brief (SPI_RNPR) Receive Next Pointer */\r
+#define SPI_RNPR_RXNPTR(value) ((SPI_RNPR_RXNPTR_Msk & ((value) << SPI_RNPR_RXNPTR_Pos)))\r
+/* -------- SPI_RNCR : (SPI Offset: 0x114) Receive Next Counter Register -------- */\r
+#define SPI_RNCR_RXNCTR_Pos 0\r
+#define SPI_RNCR_RXNCTR_Msk (0xffffu << SPI_RNCR_RXNCTR_Pos) /**< \brief (SPI_RNCR) Receive Next Counter */\r
+#define SPI_RNCR_RXNCTR(value) ((SPI_RNCR_RXNCTR_Msk & ((value) << SPI_RNCR_RXNCTR_Pos)))\r
+/* -------- SPI_TNPR : (SPI Offset: 0x118) Transmit Next Pointer Register -------- */\r
+#define SPI_TNPR_TXNPTR_Pos 0\r
+#define SPI_TNPR_TXNPTR_Msk (0xffffffffu << SPI_TNPR_TXNPTR_Pos) /**< \brief (SPI_TNPR) Transmit Next Pointer */\r
+#define SPI_TNPR_TXNPTR(value) ((SPI_TNPR_TXNPTR_Msk & ((value) << SPI_TNPR_TXNPTR_Pos)))\r
+/* -------- SPI_TNCR : (SPI Offset: 0x11C) Transmit Next Counter Register -------- */\r
+#define SPI_TNCR_TXNCTR_Pos 0\r
+#define SPI_TNCR_TXNCTR_Msk (0xffffu << SPI_TNCR_TXNCTR_Pos) /**< \brief (SPI_TNCR) Transmit Counter Next */\r
+#define SPI_TNCR_TXNCTR(value) ((SPI_TNCR_TXNCTR_Msk & ((value) << SPI_TNCR_TXNCTR_Pos)))\r
+/* -------- SPI_PTCR : (SPI Offset: 0x120) Transfer Control Register -------- */\r
+#define SPI_PTCR_RXTEN (0x1u << 0) /**< \brief (SPI_PTCR) Receiver Transfer Enable */\r
+#define SPI_PTCR_RXTDIS (0x1u << 1) /**< \brief (SPI_PTCR) Receiver Transfer Disable */\r
+#define SPI_PTCR_TXTEN (0x1u << 8) /**< \brief (SPI_PTCR) Transmitter Transfer Enable */\r
+#define SPI_PTCR_TXTDIS (0x1u << 9) /**< \brief (SPI_PTCR) Transmitter Transfer Disable */\r
+/* -------- SPI_PTSR : (SPI Offset: 0x124) Transfer Status Register -------- */\r
+#define SPI_PTSR_RXTEN (0x1u << 0) /**< \brief (SPI_PTSR) Receiver Transfer Enable */\r
+#define SPI_PTSR_TXTEN (0x1u << 8) /**< \brief (SPI_PTSR) Transmitter Transfer Enable */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM4E_SPI_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4E_SUPC_COMPONENT_\r
+#define _SAM4E_SUPC_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Supply Controller */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM4E_SUPC Supply Controller */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Supc hardware registers */\r
+typedef struct {\r
+ WoReg SUPC_CR; /**< \brief (Supc Offset: 0x00) Supply Controller Control Register */\r
+ RwReg SUPC_SMMR; /**< \brief (Supc Offset: 0x04) Supply Controller Supply Monitor Mode Register */\r
+ RwReg SUPC_MR; /**< \brief (Supc Offset: 0x08) Supply Controller Mode Register */\r
+ RwReg SUPC_WUMR; /**< \brief (Supc Offset: 0x0C) Supply Controller Wake-up Mode Register */\r
+ RwReg SUPC_WUIR; /**< \brief (Supc Offset: 0x10) Supply Controller Wake-up Inputs Register */\r
+ RoReg SUPC_SR; /**< \brief (Supc Offset: 0x14) Supply Controller Status Register */\r
+} Supc;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- SUPC_CR : (SUPC Offset: 0x00) Supply Controller Control Register -------- */\r
+#define SUPC_CR_VROFF (0x1u << 2) /**< \brief (SUPC_CR) Voltage Regulator Off */\r
+#define SUPC_CR_VROFF_NO_EFFECT (0x0u << 2) /**< \brief (SUPC_CR) no effect. */\r
+#define SUPC_CR_VROFF_STOP_VREG (0x1u << 2) /**< \brief (SUPC_CR) if KEY is correct, asserts the vddcore_nreset and stops the voltage regulator. */\r
+#define SUPC_CR_XTALSEL (0x1u << 3) /**< \brief (SUPC_CR) Crystal Oscillator Select */\r
+#define SUPC_CR_XTALSEL_NO_EFFECT (0x0u << 3) /**< \brief (SUPC_CR) no effect. */\r
+#define SUPC_CR_XTALSEL_CRYSTAL_SEL (0x1u << 3) /**< \brief (SUPC_CR) if KEY is correct, switches the slow clock on the crystal oscillator output. */\r
+#define SUPC_CR_KEY_Pos 24\r
+#define SUPC_CR_KEY_Msk (0xffu << SUPC_CR_KEY_Pos) /**< \brief (SUPC_CR) Password */\r
+#define SUPC_CR_KEY(value) ((SUPC_CR_KEY_Msk & ((value) << SUPC_CR_KEY_Pos)))\r
+/* -------- SUPC_SMMR : (SUPC Offset: 0x04) Supply Controller Supply Monitor Mode Register -------- */\r
+#define SUPC_SMMR_SMTH_Pos 0\r
+#define SUPC_SMMR_SMTH_Msk (0xfu << SUPC_SMMR_SMTH_Pos) /**< \brief (SUPC_SMMR) Supply Monitor Threshold */\r
+#define SUPC_SMMR_SMTH(value) ((SUPC_SMMR_SMTH_Msk & ((value) << SUPC_SMMR_SMTH_Pos)))\r
+#define SUPC_SMMR_SMSMPL_Pos 8\r
+#define SUPC_SMMR_SMSMPL_Msk (0x7u << SUPC_SMMR_SMSMPL_Pos) /**< \brief (SUPC_SMMR) Supply Monitor Sampling Period */\r
+#define SUPC_SMMR_SMSMPL_SMD (0x0u << 8) /**< \brief (SUPC_SMMR) Supply Monitor disabled */\r
+#define SUPC_SMMR_SMSMPL_CSM (0x1u << 8) /**< \brief (SUPC_SMMR) Continuous Supply Monitor */\r
+#define SUPC_SMMR_SMSMPL_32SLCK (0x2u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 32 SLCK periods */\r
+#define SUPC_SMMR_SMSMPL_256SLCK (0x3u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 256 SLCK periods */\r
+#define SUPC_SMMR_SMSMPL_2048SLCK (0x4u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 2,048 SLCK periods */\r
+#define SUPC_SMMR_SMRSTEN (0x1u << 12) /**< \brief (SUPC_SMMR) Supply Monitor Reset Enable */\r
+#define SUPC_SMMR_SMRSTEN_NOT_ENABLE (0x0u << 12) /**< \brief (SUPC_SMMR) the core reset signal "vddcore_nreset" is not affected when a supply monitor detection occurs. */\r
+#define SUPC_SMMR_SMRSTEN_ENABLE (0x1u << 12) /**< \brief (SUPC_SMMR) the core reset signal, vddcore_nreset is asserted when a supply monitor detection occurs. */\r
+#define SUPC_SMMR_SMIEN (0x1u << 13) /**< \brief (SUPC_SMMR) Supply Monitor Interrupt Enable */\r
+#define SUPC_SMMR_SMIEN_NOT_ENABLE (0x0u << 13) /**< \brief (SUPC_SMMR) the SUPC interrupt signal is not affected when a supply monitor detection occurs. */\r
+#define SUPC_SMMR_SMIEN_ENABLE (0x1u << 13) /**< \brief (SUPC_SMMR) the SUPC interrupt signal is asserted when a supply monitor detection occurs. */\r
+/* -------- SUPC_MR : (SUPC Offset: 0x08) Supply Controller Mode Register -------- */\r
+#define SUPC_MR_BODRSTEN (0x1u << 12) /**< \brief (SUPC_MR) Brownout Detector Reset Enable */\r
+#define SUPC_MR_BODRSTEN_NOT_ENABLE (0x0u << 12) /**< \brief (SUPC_MR) the core reset signal "vddcore_nreset" is not affected when a brownout detection occurs. */\r
+#define SUPC_MR_BODRSTEN_ENABLE (0x1u << 12) /**< \brief (SUPC_MR) the core reset signal, vddcore_nreset is asserted when a brownout detection occurs. */\r
+#define SUPC_MR_BODDIS (0x1u << 13) /**< \brief (SUPC_MR) Brownout Detector Disable */\r
+#define SUPC_MR_BODDIS_ENABLE (0x0u << 13) /**< \brief (SUPC_MR) the core brownout detector is enabled. */\r
+#define SUPC_MR_BODDIS_DISABLE (0x1u << 13) /**< \brief (SUPC_MR) the core brownout detector is disabled. */\r
+#define SUPC_MR_ONREG (0x1u << 14) /**< \brief (SUPC_MR) Voltage Regulator enable */\r
+#define SUPC_MR_ONREG_ONREG_UNUSED (0x0u << 14) /**< \brief (SUPC_MR) Internal voltage regulator is not used (external power supply is used) */\r
+#define SUPC_MR_ONREG_ONREG_USED (0x1u << 14) /**< \brief (SUPC_MR) internal voltage regulator is used */\r
+#define SUPC_MR_OSCBYPASS (0x1u << 20) /**< \brief (SUPC_MR) Oscillator Bypass */\r
+#define SUPC_MR_OSCBYPASS_NO_EFFECT (0x0u << 20) /**< \brief (SUPC_MR) no effect. Clock selection depends on XTALSEL value. */\r
+#define SUPC_MR_OSCBYPASS_BYPASS (0x1u << 20) /**< \brief (SUPC_MR) the 32-KHz XTAL oscillator is selected and is put in bypass mode. */\r
+#define SUPC_MR_KEY_Pos 24\r
+#define SUPC_MR_KEY_Msk (0xffu << SUPC_MR_KEY_Pos) /**< \brief (SUPC_MR) Password Key */\r
+#define SUPC_MR_KEY(value) ((SUPC_MR_KEY_Msk & ((value) << SUPC_MR_KEY_Pos)))\r
+/* -------- SUPC_WUMR : (SUPC Offset: 0x0C) Supply Controller Wake-up Mode Register -------- */\r
+#define SUPC_WUMR_FWUPEN (0x1u << 0) /**< \brief (SUPC_WUMR) Force Wake-up Enable */\r
+#define SUPC_WUMR_FWUPEN_NOT_ENABLE (0x0u << 0) /**< \brief (SUPC_WUMR) the Force Wake-up pin has no wake-up effect. */\r
+#define SUPC_WUMR_FWUPEN_ENABLE (0x1u << 0) /**< \brief (SUPC_WUMR) the Force Wake-up pin low forces the wake-up of the core power supply. */\r
+#define SUPC_WUMR_SMEN (0x1u << 1) /**< \brief (SUPC_WUMR) Supply Monitor Wake-up Enable */\r
+#define SUPC_WUMR_SMEN_NOT_ENABLE (0x0u << 1) /**< \brief (SUPC_WUMR) the supply monitor detection has no wake-up effect. */\r
+#define SUPC_WUMR_SMEN_ENABLE (0x1u << 1) /**< \brief (SUPC_WUMR) the supply monitor detection forces the wake-up of the core power supply. */\r
+#define SUPC_WUMR_RTTEN (0x1u << 2) /**< \brief (SUPC_WUMR) Real Time Timer Wake-up Enable */\r
+#define SUPC_WUMR_RTTEN_NOT_ENABLE (0x0u << 2) /**< \brief (SUPC_WUMR) the RTT alarm signal has no wake-up effect. */\r
+#define SUPC_WUMR_RTTEN_ENABLE (0x1u << 2) /**< \brief (SUPC_WUMR) the RTT alarm signal forces the wake-up of the core power supply. */\r
+#define SUPC_WUMR_RTCEN (0x1u << 3) /**< \brief (SUPC_WUMR) Real Time Clock Wake-up Enable */\r
+#define SUPC_WUMR_RTCEN_NOT_ENABLE (0x0u << 3) /**< \brief (SUPC_WUMR) the RTC alarm signal has no wake-up effect. */\r
+#define SUPC_WUMR_RTCEN_ENABLE (0x1u << 3) /**< \brief (SUPC_WUMR) the RTC alarm signal forces the wake-up of the core power supply. */\r
+#define SUPC_WUMR_LPDBCEN0 (0x1u << 5) /**< \brief (SUPC_WUMR) Low power Debouncer ENable WKUP0 */\r
+#define SUPC_WUMR_LPDBCEN0_NOT_ENABLE (0x0u << 5) /**< \brief (SUPC_WUMR) the WKUP0 input pin is not connected with low power debouncer. */\r
+#define SUPC_WUMR_LPDBCEN0_ENABLE (0x1u << 5) /**< \brief (SUPC_WUMR) the WKUP0 input pin is connected with low power debouncer and can force a core wake-up. */\r
+#define SUPC_WUMR_LPDBCEN1 (0x1u << 6) /**< \brief (SUPC_WUMR) Low power Debouncer ENable WKUP1 */\r
+#define SUPC_WUMR_LPDBCEN1_NOT_ENABLE (0x0u << 6) /**< \brief (SUPC_WUMR) the WKUP1input pin is not connected with low power debouncer. */\r
+#define SUPC_WUMR_LPDBCEN1_ENABLE (0x1u << 6) /**< \brief (SUPC_WUMR) the WKUP1 input pin is connected with low power debouncer and can force a core wake-up. */\r
+#define SUPC_WUMR_LPDBCCLR (0x1u << 7) /**< \brief (SUPC_WUMR) Low power Debouncer Clear */\r
+#define SUPC_WUMR_LPDBCCLR_NOT_ENABLE (0x0u << 7) /**< \brief (SUPC_WUMR) a low power debounce event does not create an immediate clear on first half GPBR registers. */\r
+#define SUPC_WUMR_LPDBCCLR_ENABLE (0x1u << 7) /**< \brief (SUPC_WUMR) a low power debounce event on WKUP0 or WKUP1 generates an immediate clear on first half GPBR registers. */\r
+#define SUPC_WUMR_FWUPDBC_Pos 8\r
+#define SUPC_WUMR_FWUPDBC_Msk (0x7u << SUPC_WUMR_FWUPDBC_Pos) /**< \brief (SUPC_WUMR) Force Wake-up Debouncer Period */\r
+#define SUPC_WUMR_FWUPDBC_IMMEDIATE (0x0u << 8) /**< \brief (SUPC_WUMR) Immediate, no debouncing, detected active at least on one Slow Clock edge. */\r
+#define SUPC_WUMR_FWUPDBC_3_SCLK (0x1u << 8) /**< \brief (SUPC_WUMR) FWUP shall be low for at least 3 SLCK periods */\r
+#define SUPC_WUMR_FWUPDBC_32_SCLK (0x2u << 8) /**< \brief (SUPC_WUMR) FWUP shall be low for at least 32 SLCK periods */\r
+#define SUPC_WUMR_FWUPDBC_512_SCLK (0x3u << 8) /**< \brief (SUPC_WUMR) FWUP shall be low for at least 512 SLCK periods */\r
+#define SUPC_WUMR_FWUPDBC_4096_SCLK (0x4u << 8) /**< \brief (SUPC_WUMR) FWUP shall be low for at least 4,096 SLCK periods */\r
+#define SUPC_WUMR_FWUPDBC_32768_SCLK (0x5u << 8) /**< \brief (SUPC_WUMR) FWUP shall be low for at least 32,768 SLCK periods */\r
+#define SUPC_WUMR_WKUPDBC_Pos 12\r
+#define SUPC_WUMR_WKUPDBC_Msk (0x7u << SUPC_WUMR_WKUPDBC_Pos) /**< \brief (SUPC_WUMR) Wake-up Inputs Debouncer Period */\r
+#define SUPC_WUMR_WKUPDBC_IMMEDIATE (0x0u << 12) /**< \brief (SUPC_WUMR) Immediate, no debouncing, detected active at least on one Slow Clock edge. */\r
+#define SUPC_WUMR_WKUPDBC_3_SCLK (0x1u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 3 SLCK periods */\r
+#define SUPC_WUMR_WKUPDBC_32_SCLK (0x2u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 32 SLCK periods */\r
+#define SUPC_WUMR_WKUPDBC_512_SCLK (0x3u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 512 SLCK periods */\r
+#define SUPC_WUMR_WKUPDBC_4096_SCLK (0x4u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 4,096 SLCK periods */\r
+#define SUPC_WUMR_WKUPDBC_32768_SCLK (0x5u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 32,768 SLCK periods */\r
+#define SUPC_WUMR_LPDBC_Pos 16\r
+#define SUPC_WUMR_LPDBC_Msk (0x7u << SUPC_WUMR_LPDBC_Pos) /**< \brief (SUPC_WUMR) Low Power DeBounCer Period */\r
+#define SUPC_WUMR_LPDBC_DISABLE (0x0u << 16) /**< \brief (SUPC_WUMR) Disable the low power debouncer. */\r
+#define SUPC_WUMR_LPDBC_2_RTCOUT0 (0x1u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in its active state for at least 2 RTCOUT0 periods */\r
+#define SUPC_WUMR_LPDBC_3_RTCOUT0 (0x2u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in its active state for at least 3 RTCOUT0 periods */\r
+#define SUPC_WUMR_LPDBC_4_RTCOUT0 (0x3u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in its active state for at least 4 RTCOUT0 periods */\r
+#define SUPC_WUMR_LPDBC_5_RTCOUT0 (0x4u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in its active state for at least 5 RTCOUT0 periods */\r
+#define SUPC_WUMR_LPDBC_6_RTCOUT0 (0x5u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in its active state for at least 6 RTCOUT0 periods */\r
+#define SUPC_WUMR_LPDBC_7_RTCOUT0 (0x6u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in its active state for at least 7 RTCOUT0 periods */\r
+#define SUPC_WUMR_LPDBC_8_RTCOUT0 (0x7u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in its active state for at least 8 RTCOUT0 periods */\r
+/* -------- SUPC_WUIR : (SUPC Offset: 0x10) Supply Controller Wake-up Inputs Register -------- */\r
+#define SUPC_WUIR_WKUPEN0 (0x1u << 0) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 */\r
+#define SUPC_WUIR_WKUPEN0_DISABLE (0x0u << 0) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake-up effect. */\r
+#define SUPC_WUIR_WKUPEN0_ENABLE (0x1u << 0) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake-up of the core power supply. */\r
+#define SUPC_WUIR_WKUPEN1 (0x1u << 1) /**< \brief (SUPC_WUIR) Wake-up Input Enable 1 */\r
+#define SUPC_WUIR_WKUPEN1_DISABLE (0x0u << 1) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake-up effect. */\r
+#define SUPC_WUIR_WKUPEN1_ENABLE (0x1u << 1) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake-up of the core power supply. */\r
+#define SUPC_WUIR_WKUPEN2 (0x1u << 2) /**< \brief (SUPC_WUIR) Wake-up Input Enable 2 */\r
+#define SUPC_WUIR_WKUPEN2_DISABLE (0x0u << 2) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake-up effect. */\r
+#define SUPC_WUIR_WKUPEN2_ENABLE (0x1u << 2) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake-up of the core power supply. */\r
+#define SUPC_WUIR_WKUPEN3 (0x1u << 3) /**< \brief (SUPC_WUIR) Wake-up Input Enable 3 */\r
+#define SUPC_WUIR_WKUPEN3_DISABLE (0x0u << 3) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake-up effect. */\r
+#define SUPC_WUIR_WKUPEN3_ENABLE (0x1u << 3) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake-up of the core power supply. */\r
+#define SUPC_WUIR_WKUPEN4 (0x1u << 4) /**< \brief (SUPC_WUIR) Wake-up Input Enable 4 */\r
+#define SUPC_WUIR_WKUPEN4_DISABLE (0x0u << 4) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake-up effect. */\r
+#define SUPC_WUIR_WKUPEN4_ENABLE (0x1u << 4) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake-up of the core power supply. */\r
+#define SUPC_WUIR_WKUPEN5 (0x1u << 5) /**< \brief (SUPC_WUIR) Wake-up Input Enable 5 */\r
+#define SUPC_WUIR_WKUPEN5_DISABLE (0x0u << 5) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake-up effect. */\r
+#define SUPC_WUIR_WKUPEN5_ENABLE (0x1u << 5) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake-up of the core power supply. */\r
+#define SUPC_WUIR_WKUPEN6 (0x1u << 6) /**< \brief (SUPC_WUIR) Wake-up Input Enable 6 */\r
+#define SUPC_WUIR_WKUPEN6_DISABLE (0x0u << 6) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake-up effect. */\r
+#define SUPC_WUIR_WKUPEN6_ENABLE (0x1u << 6) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake-up of the core power supply. */\r
+#define SUPC_WUIR_WKUPEN7 (0x1u << 7) /**< \brief (SUPC_WUIR) Wake-up Input Enable 7 */\r
+#define SUPC_WUIR_WKUPEN7_DISABLE (0x0u << 7) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake-up effect. */\r
+#define SUPC_WUIR_WKUPEN7_ENABLE (0x1u << 7) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake-up of the core power supply. */\r
+#define SUPC_WUIR_WKUPEN8 (0x1u << 8) /**< \brief (SUPC_WUIR) Wake-up Input Enable 8 */\r
+#define SUPC_WUIR_WKUPEN8_DISABLE (0x0u << 8) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake-up effect. */\r
+#define SUPC_WUIR_WKUPEN8_ENABLE (0x1u << 8) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake-up of the core power supply. */\r
+#define SUPC_WUIR_WKUPEN9 (0x1u << 9) /**< \brief (SUPC_WUIR) Wake-up Input Enable 9 */\r
+#define SUPC_WUIR_WKUPEN9_DISABLE (0x0u << 9) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake-up effect. */\r
+#define SUPC_WUIR_WKUPEN9_ENABLE (0x1u << 9) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake-up of the core power supply. */\r
+#define SUPC_WUIR_WKUPEN10 (0x1u << 10) /**< \brief (SUPC_WUIR) Wake-up Input Enable 10 */\r
+#define SUPC_WUIR_WKUPEN10_DISABLE (0x0u << 10) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake-up effect. */\r
+#define SUPC_WUIR_WKUPEN10_ENABLE (0x1u << 10) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake-up of the core power supply. */\r
+#define SUPC_WUIR_WKUPEN11 (0x1u << 11) /**< \brief (SUPC_WUIR) Wake-up Input Enable 11 */\r
+#define SUPC_WUIR_WKUPEN11_DISABLE (0x0u << 11) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake-up effect. */\r
+#define SUPC_WUIR_WKUPEN11_ENABLE (0x1u << 11) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake-up of the core power supply. */\r
+#define SUPC_WUIR_WKUPEN12 (0x1u << 12) /**< \brief (SUPC_WUIR) Wake-up Input Enable 12 */\r
+#define SUPC_WUIR_WKUPEN12_DISABLE (0x0u << 12) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake-up effect. */\r
+#define SUPC_WUIR_WKUPEN12_ENABLE (0x1u << 12) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake-up of the core power supply. */\r
+#define SUPC_WUIR_WKUPEN13 (0x1u << 13) /**< \brief (SUPC_WUIR) Wake-up Input Enable 13 */\r
+#define SUPC_WUIR_WKUPEN13_DISABLE (0x0u << 13) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake-up effect. */\r
+#define SUPC_WUIR_WKUPEN13_ENABLE (0x1u << 13) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake-up of the core power supply. */\r
+#define SUPC_WUIR_WKUPEN14 (0x1u << 14) /**< \brief (SUPC_WUIR) Wake-up Input Enable 14 */\r
+#define SUPC_WUIR_WKUPEN14_DISABLE (0x0u << 14) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake-up effect. */\r
+#define SUPC_WUIR_WKUPEN14_ENABLE (0x1u << 14) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake-up of the core power supply. */\r
+#define SUPC_WUIR_WKUPEN15 (0x1u << 15) /**< \brief (SUPC_WUIR) Wake-up Input Enable 15 */\r
+#define SUPC_WUIR_WKUPEN15_DISABLE (0x0u << 15) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake-up effect. */\r
+#define SUPC_WUIR_WKUPEN15_ENABLE (0x1u << 15) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake-up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT0 (0x1u << 16) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 */\r
+#define SUPC_WUIR_WKUPT0_LOW (0x0u << 16) /**< \brief (SUPC_WUIR) a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT0_HIGH (0x1u << 16) /**< \brief (SUPC_WUIR) a high level for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT1 (0x1u << 17) /**< \brief (SUPC_WUIR) Wake-up Input Type 1 */\r
+#define SUPC_WUIR_WKUPT1_LOW (0x0u << 17) /**< \brief (SUPC_WUIR) a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT1_HIGH (0x1u << 17) /**< \brief (SUPC_WUIR) a high level for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT2 (0x1u << 18) /**< \brief (SUPC_WUIR) Wake-up Input Type 2 */\r
+#define SUPC_WUIR_WKUPT2_LOW (0x0u << 18) /**< \brief (SUPC_WUIR) a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT2_HIGH (0x1u << 18) /**< \brief (SUPC_WUIR) a high level for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT3 (0x1u << 19) /**< \brief (SUPC_WUIR) Wake-up Input Type 3 */\r
+#define SUPC_WUIR_WKUPT3_LOW (0x0u << 19) /**< \brief (SUPC_WUIR) a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT3_HIGH (0x1u << 19) /**< \brief (SUPC_WUIR) a high level for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT4 (0x1u << 20) /**< \brief (SUPC_WUIR) Wake-up Input Type 4 */\r
+#define SUPC_WUIR_WKUPT4_LOW (0x0u << 20) /**< \brief (SUPC_WUIR) a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT4_HIGH (0x1u << 20) /**< \brief (SUPC_WUIR) a high level for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT5 (0x1u << 21) /**< \brief (SUPC_WUIR) Wake-up Input Type 5 */\r
+#define SUPC_WUIR_WKUPT5_LOW (0x0u << 21) /**< \brief (SUPC_WUIR) a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT5_HIGH (0x1u << 21) /**< \brief (SUPC_WUIR) a high level for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT6 (0x1u << 22) /**< \brief (SUPC_WUIR) Wake-up Input Type 6 */\r
+#define SUPC_WUIR_WKUPT6_LOW (0x0u << 22) /**< \brief (SUPC_WUIR) a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT6_HIGH (0x1u << 22) /**< \brief (SUPC_WUIR) a high level for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT7 (0x1u << 23) /**< \brief (SUPC_WUIR) Wake-up Input Type 7 */\r
+#define SUPC_WUIR_WKUPT7_LOW (0x0u << 23) /**< \brief (SUPC_WUIR) a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT7_HIGH (0x1u << 23) /**< \brief (SUPC_WUIR) a high level for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT8 (0x1u << 24) /**< \brief (SUPC_WUIR) Wake-up Input Type 8 */\r
+#define SUPC_WUIR_WKUPT8_LOW (0x0u << 24) /**< \brief (SUPC_WUIR) a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT8_HIGH (0x1u << 24) /**< \brief (SUPC_WUIR) a high level for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT9 (0x1u << 25) /**< \brief (SUPC_WUIR) Wake-up Input Type 9 */\r
+#define SUPC_WUIR_WKUPT9_LOW (0x0u << 25) /**< \brief (SUPC_WUIR) a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT9_HIGH (0x1u << 25) /**< \brief (SUPC_WUIR) a high level for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT10 (0x1u << 26) /**< \brief (SUPC_WUIR) Wake-up Input Type 10 */\r
+#define SUPC_WUIR_WKUPT10_LOW (0x0u << 26) /**< \brief (SUPC_WUIR) a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT10_HIGH (0x1u << 26) /**< \brief (SUPC_WUIR) a high level for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT11 (0x1u << 27) /**< \brief (SUPC_WUIR) Wake-up Input Type 11 */\r
+#define SUPC_WUIR_WKUPT11_LOW (0x0u << 27) /**< \brief (SUPC_WUIR) a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT11_HIGH (0x1u << 27) /**< \brief (SUPC_WUIR) a high level for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT12 (0x1u << 28) /**< \brief (SUPC_WUIR) Wake-up Input Type 12 */\r
+#define SUPC_WUIR_WKUPT12_LOW (0x0u << 28) /**< \brief (SUPC_WUIR) a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT12_HIGH (0x1u << 28) /**< \brief (SUPC_WUIR) a high level for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT13 (0x1u << 29) /**< \brief (SUPC_WUIR) Wake-up Input Type 13 */\r
+#define SUPC_WUIR_WKUPT13_LOW (0x0u << 29) /**< \brief (SUPC_WUIR) a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT13_HIGH (0x1u << 29) /**< \brief (SUPC_WUIR) a high level for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT14 (0x1u << 30) /**< \brief (SUPC_WUIR) Wake-up Input Type 14 */\r
+#define SUPC_WUIR_WKUPT14_LOW (0x0u << 30) /**< \brief (SUPC_WUIR) a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT14_HIGH (0x1u << 30) /**< \brief (SUPC_WUIR) a high level for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT15 (0x1u << 31) /**< \brief (SUPC_WUIR) Wake-up Input Type 15 */\r
+#define SUPC_WUIR_WKUPT15_LOW (0x0u << 31) /**< \brief (SUPC_WUIR) a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT15_HIGH (0x1u << 31) /**< \brief (SUPC_WUIR) a high level for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. */\r
+/* -------- SUPC_SR : (SUPC Offset: 0x14) Supply Controller Status Register -------- */\r
+#define SUPC_SR_FWUPS (0x1u << 0) /**< \brief (SUPC_SR) FWUP Wake-up Status */\r
+#define SUPC_SR_FWUPS_NO (0x0u << 0) /**< \brief (SUPC_SR) no wake-up due to the assertion of the FWUP pin has occurred since the last read of SUPC_SR. */\r
+#define SUPC_SR_FWUPS_PRESENT (0x1u << 0) /**< \brief (SUPC_SR) at least one wake-up due to the assertion of the FWUP pin has occurred since the last read of SUPC_SR. */\r
+#define SUPC_SR_WKUPS (0x1u << 1) /**< \brief (SUPC_SR) WKUP Wake-up Status */\r
+#define SUPC_SR_WKUPS_NO (0x0u << 1) /**< \brief (SUPC_SR) no wake-up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */\r
+#define SUPC_SR_WKUPS_PRESENT (0x1u << 1) /**< \brief (SUPC_SR) at least one wake-up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */\r
+#define SUPC_SR_SMWS (0x1u << 2) /**< \brief (SUPC_SR) Supply Monitor Detection Wake-up Status */\r
+#define SUPC_SR_SMWS_NO (0x0u << 2) /**< \brief (SUPC_SR) no wake-up due to a supply monitor detection has occurred since the last read of SUPC_SR. */\r
+#define SUPC_SR_SMWS_PRESENT (0x1u << 2) /**< \brief (SUPC_SR) at least one wake-up due to a supply monitor detection has occurred since the last read of SUPC_SR. */\r
+#define SUPC_SR_BODRSTS (0x1u << 3) /**< \brief (SUPC_SR) Brownout Detector Reset Status */\r
+#define SUPC_SR_BODRSTS_NO (0x0u << 3) /**< \brief (SUPC_SR) no core brownout rising edge event has been detected since the last read of the SUPC_SR. */\r
+#define SUPC_SR_BODRSTS_PRESENT (0x1u << 3) /**< \brief (SUPC_SR) at least one brownout output rising edge event has been detected since the last read of the SUPC_SR. */\r
+#define SUPC_SR_SMRSTS (0x1u << 4) /**< \brief (SUPC_SR) Supply Monitor Reset Status */\r
+#define SUPC_SR_SMRSTS_NO (0x0u << 4) /**< \brief (SUPC_SR) no supply monitor detection has generated a core reset since the last read of the SUPC_SR. */\r
+#define SUPC_SR_SMRSTS_PRESENT (0x1u << 4) /**< \brief (SUPC_SR) at least one supply monitor detection has generated a core reset since the last read of the SUPC_SR. */\r
+#define SUPC_SR_SMS (0x1u << 5) /**< \brief (SUPC_SR) Supply Monitor Status */\r
+#define SUPC_SR_SMS_NO (0x0u << 5) /**< \brief (SUPC_SR) no supply monitor detection since the last read of SUPC_SR. */\r
+#define SUPC_SR_SMS_PRESENT (0x1u << 5) /**< \brief (SUPC_SR) at least one supply monitor detection since the last read of SUPC_SR. */\r
+#define SUPC_SR_SMOS (0x1u << 6) /**< \brief (SUPC_SR) Supply Monitor Output Status */\r
+#define SUPC_SR_SMOS_HIGH (0x0u << 6) /**< \brief (SUPC_SR) the supply monitor detected VDDIO higher than its threshold at its last measurement. */\r
+#define SUPC_SR_SMOS_LOW (0x1u << 6) /**< \brief (SUPC_SR) the supply monitor detected VDDIO lower than its threshold at its last measurement. */\r
+#define SUPC_SR_OSCSEL (0x1u << 7) /**< \brief (SUPC_SR) 32-kHz Oscillator Selection Status */\r
+#define SUPC_SR_OSCSEL_RC (0x0u << 7) /**< \brief (SUPC_SR) the slow clock, SLCK is generated by the embedded 32-kHz RC oscillator. */\r
+#define SUPC_SR_OSCSEL_CRYST (0x1u << 7) /**< \brief (SUPC_SR) the slow clock, SLCK is generated by the 32-kHz crystal oscillator. */\r
+#define SUPC_SR_FWUPIS (0x1u << 12) /**< \brief (SUPC_SR) FWUP Input Status */\r
+#define SUPC_SR_FWUPIS_LOW (0x0u << 12) /**< \brief (SUPC_SR) FWUP input is tied low. */\r
+#define SUPC_SR_FWUPIS_HIGH (0x1u << 12) /**< \brief (SUPC_SR) FWUP input is tied high. */\r
+#define SUPC_SR_LPDBCS0 (0x1u << 13) /**< \brief (SUPC_SR) Low Power Debouncer Wake-up Status on WKUP0 */\r
+#define SUPC_SR_LPDBCS0_NO (0x0u << 13) /**< \brief (SUPC_SR) no wake-up due to the assertion of the WKUP0 pin has occurred since the last read of SUPC_SR. */\r
+#define SUPC_SR_LPDBCS0_PRESENT (0x1u << 13) /**< \brief (SUPC_SR) at least one wake-up due to the assertion of the WKUP0 pin has occurred since the last read of SUPC_SR. */\r
+#define SUPC_SR_LPDBCS1 (0x1u << 14) /**< \brief (SUPC_SR) Low Power Debouncer Wake-up Status on WKUP1 */\r
+#define SUPC_SR_LPDBCS1_NO (0x0u << 14) /**< \brief (SUPC_SR) no wake-up due to the assertion of the WKUP1 pin has occurred since the last read of SUPC_SR. */\r
+#define SUPC_SR_LPDBCS1_PRESENT (0x1u << 14) /**< \brief (SUPC_SR) at least one wake-up due to the assertion of the WKUP1 pin has occurred since the last read of SUPC_SR. */\r
+#define SUPC_SR_WKUPIS0 (0x1u << 16) /**< \brief (SUPC_SR) WKUP Input Status 0 */\r
+#define SUPC_SR_WKUPIS0_DIS (0x0u << 16) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */\r
+#define SUPC_SR_WKUPIS0_EN (0x1u << 16) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. */\r
+#define SUPC_SR_WKUPIS1 (0x1u << 17) /**< \brief (SUPC_SR) WKUP Input Status 1 */\r
+#define SUPC_SR_WKUPIS1_DIS (0x0u << 17) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */\r
+#define SUPC_SR_WKUPIS1_EN (0x1u << 17) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. */\r
+#define SUPC_SR_WKUPIS2 (0x1u << 18) /**< \brief (SUPC_SR) WKUP Input Status 2 */\r
+#define SUPC_SR_WKUPIS2_DIS (0x0u << 18) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */\r
+#define SUPC_SR_WKUPIS2_EN (0x1u << 18) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. */\r
+#define SUPC_SR_WKUPIS3 (0x1u << 19) /**< \brief (SUPC_SR) WKUP Input Status 3 */\r
+#define SUPC_SR_WKUPIS3_DIS (0x0u << 19) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */\r
+#define SUPC_SR_WKUPIS3_EN (0x1u << 19) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. */\r
+#define SUPC_SR_WKUPIS4 (0x1u << 20) /**< \brief (SUPC_SR) WKUP Input Status 4 */\r
+#define SUPC_SR_WKUPIS4_DIS (0x0u << 20) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */\r
+#define SUPC_SR_WKUPIS4_EN (0x1u << 20) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. */\r
+#define SUPC_SR_WKUPIS5 (0x1u << 21) /**< \brief (SUPC_SR) WKUP Input Status 5 */\r
+#define SUPC_SR_WKUPIS5_DIS (0x0u << 21) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */\r
+#define SUPC_SR_WKUPIS5_EN (0x1u << 21) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. */\r
+#define SUPC_SR_WKUPIS6 (0x1u << 22) /**< \brief (SUPC_SR) WKUP Input Status 6 */\r
+#define SUPC_SR_WKUPIS6_DIS (0x0u << 22) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */\r
+#define SUPC_SR_WKUPIS6_EN (0x1u << 22) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. */\r
+#define SUPC_SR_WKUPIS7 (0x1u << 23) /**< \brief (SUPC_SR) WKUP Input Status 7 */\r
+#define SUPC_SR_WKUPIS7_DIS (0x0u << 23) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */\r
+#define SUPC_SR_WKUPIS7_EN (0x1u << 23) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. */\r
+#define SUPC_SR_WKUPIS8 (0x1u << 24) /**< \brief (SUPC_SR) WKUP Input Status 8 */\r
+#define SUPC_SR_WKUPIS8_DIS (0x0u << 24) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */\r
+#define SUPC_SR_WKUPIS8_EN (0x1u << 24) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. */\r
+#define SUPC_SR_WKUPIS9 (0x1u << 25) /**< \brief (SUPC_SR) WKUP Input Status 9 */\r
+#define SUPC_SR_WKUPIS9_DIS (0x0u << 25) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */\r
+#define SUPC_SR_WKUPIS9_EN (0x1u << 25) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. */\r
+#define SUPC_SR_WKUPIS10 (0x1u << 26) /**< \brief (SUPC_SR) WKUP Input Status 10 */\r
+#define SUPC_SR_WKUPIS10_DIS (0x0u << 26) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */\r
+#define SUPC_SR_WKUPIS10_EN (0x1u << 26) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. */\r
+#define SUPC_SR_WKUPIS11 (0x1u << 27) /**< \brief (SUPC_SR) WKUP Input Status 11 */\r
+#define SUPC_SR_WKUPIS11_DIS (0x0u << 27) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */\r
+#define SUPC_SR_WKUPIS11_EN (0x1u << 27) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. */\r
+#define SUPC_SR_WKUPIS12 (0x1u << 28) /**< \brief (SUPC_SR) WKUP Input Status 12 */\r
+#define SUPC_SR_WKUPIS12_DIS (0x0u << 28) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */\r
+#define SUPC_SR_WKUPIS12_EN (0x1u << 28) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. */\r
+#define SUPC_SR_WKUPIS13 (0x1u << 29) /**< \brief (SUPC_SR) WKUP Input Status 13 */\r
+#define SUPC_SR_WKUPIS13_DIS (0x0u << 29) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */\r
+#define SUPC_SR_WKUPIS13_EN (0x1u << 29) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. */\r
+#define SUPC_SR_WKUPIS14 (0x1u << 30) /**< \brief (SUPC_SR) WKUP Input Status 14 */\r
+#define SUPC_SR_WKUPIS14_DIS (0x0u << 30) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */\r
+#define SUPC_SR_WKUPIS14_EN (0x1u << 30) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. */\r
+#define SUPC_SR_WKUPIS15 (0x1u << 31) /**< \brief (SUPC_SR) WKUP Input Status 15 */\r
+#define SUPC_SR_WKUPIS15_DIS (0x0u << 31) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */\r
+#define SUPC_SR_WKUPIS15_EN (0x1u << 31) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM4E_SUPC_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4E_TC_COMPONENT_\r
+#define _SAM4E_TC_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Timer Counter */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM4E_TC Timer Counter */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief TcChannel hardware registers */\r
+typedef struct {\r
+ RwReg TC_CCR; /**< \brief (TcChannel Offset: 0x0) Channel Control Register */\r
+ RwReg TC_CMR; /**< \brief (TcChannel Offset: 0x4) Channel Mode Register */\r
+ RwReg TC_SMMR; /**< \brief (TcChannel Offset: 0x8) Stepper Motor Mode Register */\r
+ RwReg TC_RAB; /**< \brief (TcChannel Offset: 0xC) Register AB */\r
+ RwReg TC_CV; /**< \brief (TcChannel Offset: 0x10) Counter Value */\r
+ RwReg TC_RA; /**< \brief (TcChannel Offset: 0x14) Register A */\r
+ RwReg TC_RB; /**< \brief (TcChannel Offset: 0x18) Register B */\r
+ RwReg TC_RC; /**< \brief (TcChannel Offset: 0x1C) Register C */\r
+ RwReg TC_SR; /**< \brief (TcChannel Offset: 0x20) Status Register */\r
+ RwReg TC_IER; /**< \brief (TcChannel Offset: 0x24) Interrupt Enable Register */\r
+ RwReg TC_IDR; /**< \brief (TcChannel Offset: 0x28) Interrupt Disable Register */\r
+ RwReg TC_IMR; /**< \brief (TcChannel Offset: 0x2C) Interrupt Mask Register */\r
+ RwReg TC_EMR; /**< \brief (TcChannel Offset: 0x30) Extended Mode Register */\r
+ RoReg Reserved1[3];\r
+} TcChannel;\r
+/** \brief TcPdc hardware registers */\r
+typedef struct {\r
+ RwReg TC_RPR; /**< \brief (TcPdc Offset: 0x0) Receive Pointer Register */\r
+ RwReg TC_RCR; /**< \brief (TcPdc Offset: 0x4) Receive Counter Register */\r
+ RoReg Reserved2[2];\r
+ RwReg TC_RNPR; /**< \brief (TcPdc Offset: 0x10) Receive Next Pointer Register */\r
+ RwReg TC_RNCR; /**< \brief (TcPdc Offset: 0x14) Receive Next Counter Register */\r
+ RoReg Reserved3[2];\r
+ RwReg TC_PTCR; /**< \brief (TcPdc Offset: 0x20) Transfer Control Register */\r
+ RwReg TC_PTSR; /**< \brief (TcPdc Offset: 0x24) Transfer Status Register */\r
+ RoReg Reserved4[6];\r
+} TcPdc;\r
+/** \brief Tc hardware registers */\r
+#define TCCHANNEL_NUMBER 3\r
+#define TCPDC_NUMBER 3\r
+typedef struct {\r
+ TcChannel TC_CHANNEL[TCCHANNEL_NUMBER]; /**< \brief (Tc Offset: 0x0) channel = 0 .. 2 */\r
+ WoReg TC_BCR; /**< \brief (Tc Offset: 0xC0) Block Control Register */\r
+ RwReg TC_BMR; /**< \brief (Tc Offset: 0xC4) Block Mode Register */\r
+ WoReg TC_QIER; /**< \brief (Tc Offset: 0xC8) QDEC Interrupt Enable Register */\r
+ WoReg TC_QIDR; /**< \brief (Tc Offset: 0xCC) QDEC Interrupt Disable Register */\r
+ RoReg TC_QIMR; /**< \brief (Tc Offset: 0xD0) QDEC Interrupt Mask Register */\r
+ RoReg TC_QISR; /**< \brief (Tc Offset: 0xD4) QDEC Interrupt Status Register */\r
+ RwReg TC_FMR; /**< \brief (Tc Offset: 0xD8) Fault Mode Register */\r
+ RoReg Reserved1[2];\r
+ RwReg TC_WPMR; /**< \brief (Tc Offset: 0xE4) Write Protect Mode Register */\r
+ RoReg Reserved2[6];\r
+ TcPdc TC_PDC[TCPDC_NUMBER]; /**< \brief (Tc Offset: 0x100) pdc = 0 .. 2 */\r
+} Tc;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- TC_CCR : (TC Offset: N/A) Channel Control Register -------- */\r
+#define TC_CCR_CLKEN (0x1u << 0) /**< \brief (TC_CCR) Counter Clock Enable Command */\r
+#define TC_CCR_CLKDIS (0x1u << 1) /**< \brief (TC_CCR) Counter Clock Disable Command */\r
+#define TC_CCR_SWTRG (0x1u << 2) /**< \brief (TC_CCR) Software Trigger Command */\r
+/* -------- TC_CMR : (TC Offset: N/A) Channel Mode Register -------- */\r
+#define TC_CMR_TCCLKS_Pos 0\r
+#define TC_CMR_TCCLKS_Msk (0x7u << TC_CMR_TCCLKS_Pos) /**< \brief (TC_CMR) Clock Selection */\r
+#define TC_CMR_TCCLKS_TIMER_CLOCK1 (0x0u << 0) /**< \brief (TC_CMR) Clock selected: TCLK1 */\r
+#define TC_CMR_TCCLKS_TIMER_CLOCK2 (0x1u << 0) /**< \brief (TC_CMR) Clock selected: TCLK2 */\r
+#define TC_CMR_TCCLKS_TIMER_CLOCK3 (0x2u << 0) /**< \brief (TC_CMR) Clock selected: TCLK3 */\r
+#define TC_CMR_TCCLKS_TIMER_CLOCK4 (0x3u << 0) /**< \brief (TC_CMR) Clock selected: TCLK4 */\r
+#define TC_CMR_TCCLKS_TIMER_CLOCK5 (0x4u << 0) /**< \brief (TC_CMR) Clock selected: TCLK5 */\r
+#define TC_CMR_TCCLKS_XC0 (0x5u << 0) /**< \brief (TC_CMR) Clock selected: XC0 */\r
+#define TC_CMR_TCCLKS_XC1 (0x6u << 0) /**< \brief (TC_CMR) Clock selected: XC1 */\r
+#define TC_CMR_TCCLKS_XC2 (0x7u << 0) /**< \brief (TC_CMR) Clock selected: XC2 */\r
+#define TC_CMR_CLKI (0x1u << 3) /**< \brief (TC_CMR) Clock Invert */\r
+#define TC_CMR_BURST_Pos 4\r
+#define TC_CMR_BURST_Msk (0x3u << TC_CMR_BURST_Pos) /**< \brief (TC_CMR) Burst Signal Selection */\r
+#define TC_CMR_BURST_NONE (0x0u << 4) /**< \brief (TC_CMR) The clock is not gated by an external signal. */\r
+#define TC_CMR_BURST_XC0 (0x1u << 4) /**< \brief (TC_CMR) XC0 is ANDed with the selected clock. */\r
+#define TC_CMR_BURST_XC1 (0x2u << 4) /**< \brief (TC_CMR) XC1 is ANDed with the selected clock. */\r
+#define TC_CMR_BURST_XC2 (0x3u << 4) /**< \brief (TC_CMR) XC2 is ANDed with the selected clock. */\r
+#define TC_CMR_LDBSTOP (0x1u << 6) /**< \brief (TC_CMR) Counter Clock Stopped with RB Loading */\r
+#define TC_CMR_LDBDIS (0x1u << 7) /**< \brief (TC_CMR) Counter Clock Disable with RB Loading */\r
+#define TC_CMR_ETRGEDG_Pos 8\r
+#define TC_CMR_ETRGEDG_Msk (0x3u << TC_CMR_ETRGEDG_Pos) /**< \brief (TC_CMR) External Trigger Edge Selection */\r
+#define TC_CMR_ETRGEDG_NONE (0x0u << 8) /**< \brief (TC_CMR) The clock is not gated by an external signal. */\r
+#define TC_CMR_ETRGEDG_RISING (0x1u << 8) /**< \brief (TC_CMR) Rising edge */\r
+#define TC_CMR_ETRGEDG_FALLING (0x2u << 8) /**< \brief (TC_CMR) Falling edge */\r
+#define TC_CMR_ETRGEDG_EDGE (0x3u << 8) /**< \brief (TC_CMR) Each edge */\r
+#define TC_CMR_ABETRG (0x1u << 10) /**< \brief (TC_CMR) TIOA or TIOB External Trigger Selection */\r
+#define TC_CMR_CPCTRG (0x1u << 14) /**< \brief (TC_CMR) RC Compare Trigger Enable */\r
+#define TC_CMR_WAVE (0x1u << 15) /**< \brief (TC_CMR) Waveform Mode */\r
+#define TC_CMR_LDRA_Pos 16\r
+#define TC_CMR_LDRA_Msk (0x3u << TC_CMR_LDRA_Pos) /**< \brief (TC_CMR) RA Loading Edge Selection */\r
+#define TC_CMR_LDRA_NONE (0x0u << 16) /**< \brief (TC_CMR) None */\r
+#define TC_CMR_LDRA_RISING (0x1u << 16) /**< \brief (TC_CMR) Rising edge of TIOA */\r
+#define TC_CMR_LDRA_FALLING (0x2u << 16) /**< \brief (TC_CMR) Falling edge of TIOA */\r
+#define TC_CMR_LDRA_EDGE (0x3u << 16) /**< \brief (TC_CMR) Each edge of TIOA */\r
+#define TC_CMR_LDRB_Pos 18\r
+#define TC_CMR_LDRB_Msk (0x3u << TC_CMR_LDRB_Pos) /**< \brief (TC_CMR) RB Loading Edge Selection */\r
+#define TC_CMR_LDRB_NONE (0x0u << 18) /**< \brief (TC_CMR) None */\r
+#define TC_CMR_LDRB_RISING (0x1u << 18) /**< \brief (TC_CMR) Rising edge of TIOA */\r
+#define TC_CMR_LDRB_FALLING (0x2u << 18) /**< \brief (TC_CMR) Falling edge of TIOA */\r
+#define TC_CMR_LDRB_EDGE (0x3u << 18) /**< \brief (TC_CMR) Each edge of TIOA */\r
+#define TC_CMR_SBSMPLR_Pos 20\r
+#define TC_CMR_SBSMPLR_Msk (0x7u << TC_CMR_SBSMPLR_Pos) /**< \brief (TC_CMR) Loading Edge Subsampling Ratio */\r
+#define TC_CMR_SBSMPLR_ONE (0x0u << 20) /**< \brief (TC_CMR) Load a Capture Register each selected edge */\r
+#define TC_CMR_SBSMPLR_HALF (0x1u << 20) /**< \brief (TC_CMR) Load a Capture Register every 2 selected edges */\r
+#define TC_CMR_SBSMPLR_FOURTH (0x2u << 20) /**< \brief (TC_CMR) Load a Capture Register every 4 selected edges */\r
+#define TC_CMR_SBSMPLR_EIGHTH (0x3u << 20) /**< \brief (TC_CMR) Load a Capture Register every 8 selected edges */\r
+#define TC_CMR_SBSMPLR_SIXTEENTH (0x4u << 20) /**< \brief (TC_CMR) Load a Capture Register every 16 selected edges */\r
+#define TC_CMR_CPCSTOP (0x1u << 6) /**< \brief (TC_CMR) Counter Clock Stopped with RC Compare */\r
+#define TC_CMR_CPCDIS (0x1u << 7) /**< \brief (TC_CMR) Counter Clock Disable with RC Compare */\r
+#define TC_CMR_EEVTEDG_Pos 8\r
+#define TC_CMR_EEVTEDG_Msk (0x3u << TC_CMR_EEVTEDG_Pos) /**< \brief (TC_CMR) External Event Edge Selection */\r
+#define TC_CMR_EEVTEDG_NONE (0x0u << 8) /**< \brief (TC_CMR) None */\r
+#define TC_CMR_EEVTEDG_RISING (0x1u << 8) /**< \brief (TC_CMR) Rising edge */\r
+#define TC_CMR_EEVTEDG_FALLING (0x2u << 8) /**< \brief (TC_CMR) Falling edge */\r
+#define TC_CMR_EEVTEDG_EDGE (0x3u << 8) /**< \brief (TC_CMR) Each edge */\r
+#define TC_CMR_EEVT_Pos 10\r
+#define TC_CMR_EEVT_Msk (0x3u << TC_CMR_EEVT_Pos) /**< \brief (TC_CMR) External Event Selection */\r
+#define TC_CMR_EEVT_TIOB (0x0u << 10) /**< \brief (TC_CMR) TIOB */\r
+#define TC_CMR_EEVT_XC0 (0x1u << 10) /**< \brief (TC_CMR) XC0 */\r
+#define TC_CMR_EEVT_XC1 (0x2u << 10) /**< \brief (TC_CMR) XC1 */\r
+#define TC_CMR_EEVT_XC2 (0x3u << 10) /**< \brief (TC_CMR) XC2 */\r
+#define TC_CMR_ENETRG (0x1u << 12) /**< \brief (TC_CMR) External Event Trigger Enable */\r
+#define TC_CMR_WAVSEL_Pos 13\r
+#define TC_CMR_WAVSEL_Msk (0x3u << TC_CMR_WAVSEL_Pos) /**< \brief (TC_CMR) Waveform Selection */\r
+#define TC_CMR_WAVSEL_UP (0x0u << 13) /**< \brief (TC_CMR) UP mode without automatic trigger on RC Compare */\r
+#define TC_CMR_WAVSEL_UPDOWN (0x1u << 13) /**< \brief (TC_CMR) UPDOWN mode without automatic trigger on RC Compare */\r
+#define TC_CMR_WAVSEL_UP_RC (0x2u << 13) /**< \brief (TC_CMR) UP mode with automatic trigger on RC Compare */\r
+#define TC_CMR_WAVSEL_UPDOWN_RC (0x3u << 13) /**< \brief (TC_CMR) UPDOWN mode with automatic trigger on RC Compare */\r
+#define TC_CMR_ACPA_Pos 16\r
+#define TC_CMR_ACPA_Msk (0x3u << TC_CMR_ACPA_Pos) /**< \brief (TC_CMR) RA Compare Effect on TIOA */\r
+#define TC_CMR_ACPA_NONE (0x0u << 16) /**< \brief (TC_CMR) None */\r
+#define TC_CMR_ACPA_SET (0x1u << 16) /**< \brief (TC_CMR) Set */\r
+#define TC_CMR_ACPA_CLEAR (0x2u << 16) /**< \brief (TC_CMR) Clear */\r
+#define TC_CMR_ACPA_TOGGLE (0x3u << 16) /**< \brief (TC_CMR) Toggle */\r
+#define TC_CMR_ACPC_Pos 18\r
+#define TC_CMR_ACPC_Msk (0x3u << TC_CMR_ACPC_Pos) /**< \brief (TC_CMR) RC Compare Effect on TIOA */\r
+#define TC_CMR_ACPC_NONE (0x0u << 18) /**< \brief (TC_CMR) None */\r
+#define TC_CMR_ACPC_SET (0x1u << 18) /**< \brief (TC_CMR) Set */\r
+#define TC_CMR_ACPC_CLEAR (0x2u << 18) /**< \brief (TC_CMR) Clear */\r
+#define TC_CMR_ACPC_TOGGLE (0x3u << 18) /**< \brief (TC_CMR) Toggle */\r
+#define TC_CMR_AEEVT_Pos 20\r
+#define TC_CMR_AEEVT_Msk (0x3u << TC_CMR_AEEVT_Pos) /**< \brief (TC_CMR) External Event Effect on TIOA */\r
+#define TC_CMR_AEEVT_NONE (0x0u << 20) /**< \brief (TC_CMR) None */\r
+#define TC_CMR_AEEVT_SET (0x1u << 20) /**< \brief (TC_CMR) Set */\r
+#define TC_CMR_AEEVT_CLEAR (0x2u << 20) /**< \brief (TC_CMR) Clear */\r
+#define TC_CMR_AEEVT_TOGGLE (0x3u << 20) /**< \brief (TC_CMR) Toggle */\r
+#define TC_CMR_ASWTRG_Pos 22\r
+#define TC_CMR_ASWTRG_Msk (0x3u << TC_CMR_ASWTRG_Pos) /**< \brief (TC_CMR) Software Trigger Effect on TIOA */\r
+#define TC_CMR_ASWTRG_NONE (0x0u << 22) /**< \brief (TC_CMR) None */\r
+#define TC_CMR_ASWTRG_SET (0x1u << 22) /**< \brief (TC_CMR) Set */\r
+#define TC_CMR_ASWTRG_CLEAR (0x2u << 22) /**< \brief (TC_CMR) Clear */\r
+#define TC_CMR_ASWTRG_TOGGLE (0x3u << 22) /**< \brief (TC_CMR) Toggle */\r
+#define TC_CMR_BCPB_Pos 24\r
+#define TC_CMR_BCPB_Msk (0x3u << TC_CMR_BCPB_Pos) /**< \brief (TC_CMR) RB Compare Effect on TIOB */\r
+#define TC_CMR_BCPB_NONE (0x0u << 24) /**< \brief (TC_CMR) None */\r
+#define TC_CMR_BCPB_SET (0x1u << 24) /**< \brief (TC_CMR) Set */\r
+#define TC_CMR_BCPB_CLEAR (0x2u << 24) /**< \brief (TC_CMR) Clear */\r
+#define TC_CMR_BCPB_TOGGLE (0x3u << 24) /**< \brief (TC_CMR) Toggle */\r
+#define TC_CMR_BCPC_Pos 26\r
+#define TC_CMR_BCPC_Msk (0x3u << TC_CMR_BCPC_Pos) /**< \brief (TC_CMR) RC Compare Effect on TIOB */\r
+#define TC_CMR_BCPC_NONE (0x0u << 26) /**< \brief (TC_CMR) None */\r
+#define TC_CMR_BCPC_SET (0x1u << 26) /**< \brief (TC_CMR) Set */\r
+#define TC_CMR_BCPC_CLEAR (0x2u << 26) /**< \brief (TC_CMR) Clear */\r
+#define TC_CMR_BCPC_TOGGLE (0x3u << 26) /**< \brief (TC_CMR) Toggle */\r
+#define TC_CMR_BEEVT_Pos 28\r
+#define TC_CMR_BEEVT_Msk (0x3u << TC_CMR_BEEVT_Pos) /**< \brief (TC_CMR) External Event Effect on TIOB */\r
+#define TC_CMR_BEEVT_NONE (0x0u << 28) /**< \brief (TC_CMR) None */\r
+#define TC_CMR_BEEVT_SET (0x1u << 28) /**< \brief (TC_CMR) Set */\r
+#define TC_CMR_BEEVT_CLEAR (0x2u << 28) /**< \brief (TC_CMR) Clear */\r
+#define TC_CMR_BEEVT_TOGGLE (0x3u << 28) /**< \brief (TC_CMR) Toggle */\r
+#define TC_CMR_BSWTRG_Pos 30\r
+#define TC_CMR_BSWTRG_Msk (0x3u << TC_CMR_BSWTRG_Pos) /**< \brief (TC_CMR) Software Trigger Effect on TIOB */\r
+#define TC_CMR_BSWTRG_NONE (0x0u << 30) /**< \brief (TC_CMR) None */\r
+#define TC_CMR_BSWTRG_SET (0x1u << 30) /**< \brief (TC_CMR) Set */\r
+#define TC_CMR_BSWTRG_CLEAR (0x2u << 30) /**< \brief (TC_CMR) Clear */\r
+#define TC_CMR_BSWTRG_TOGGLE (0x3u << 30) /**< \brief (TC_CMR) Toggle */\r
+/* -------- TC_SMMR : (TC Offset: N/A) Stepper Motor Mode Register -------- */\r
+#define TC_SMMR_GCEN (0x1u << 0) /**< \brief (TC_SMMR) Gray Count Enable */\r
+#define TC_SMMR_DOWN (0x1u << 1) /**< \brief (TC_SMMR) DOWN Count */\r
+/* -------- TC_RAB : (TC Offset: N/A) Register AB -------- */\r
+#define TC_RAB_RAB_Pos 0\r
+#define TC_RAB_RAB_Msk (0xffffffffu << TC_RAB_RAB_Pos) /**< \brief (TC_RAB) Register A or Register B */\r
+/* -------- TC_CV : (TC Offset: N/A) Counter Value -------- */\r
+#define TC_CV_CV_Pos 0\r
+#define TC_CV_CV_Msk (0xffffffffu << TC_CV_CV_Pos) /**< \brief (TC_CV) Counter Value */\r
+/* -------- TC_RA : (TC Offset: N/A) Register A -------- */\r
+#define TC_RA_RA_Pos 0\r
+#define TC_RA_RA_Msk (0xffffffffu << TC_RA_RA_Pos) /**< \brief (TC_RA) Register A */\r
+#define TC_RA_RA(value) ((TC_RA_RA_Msk & ((value) << TC_RA_RA_Pos)))\r
+/* -------- TC_RB : (TC Offset: N/A) Register B -------- */\r
+#define TC_RB_RB_Pos 0\r
+#define TC_RB_RB_Msk (0xffffffffu << TC_RB_RB_Pos) /**< \brief (TC_RB) Register B */\r
+#define TC_RB_RB(value) ((TC_RB_RB_Msk & ((value) << TC_RB_RB_Pos)))\r
+/* -------- TC_RC : (TC Offset: N/A) Register C -------- */\r
+#define TC_RC_RC_Pos 0\r
+#define TC_RC_RC_Msk (0xffffffffu << TC_RC_RC_Pos) /**< \brief (TC_RC) Register C */\r
+#define TC_RC_RC(value) ((TC_RC_RC_Msk & ((value) << TC_RC_RC_Pos)))\r
+/* -------- TC_SR : (TC Offset: N/A) Status Register -------- */\r
+#define TC_SR_COVFS (0x1u << 0) /**< \brief (TC_SR) Counter Overflow Status */\r
+#define TC_SR_LOVRS (0x1u << 1) /**< \brief (TC_SR) Load Overrun Status */\r
+#define TC_SR_CPAS (0x1u << 2) /**< \brief (TC_SR) RA Compare Status */\r
+#define TC_SR_CPBS (0x1u << 3) /**< \brief (TC_SR) RB Compare Status */\r
+#define TC_SR_CPCS (0x1u << 4) /**< \brief (TC_SR) RC Compare Status */\r
+#define TC_SR_LDRAS (0x1u << 5) /**< \brief (TC_SR) RA Loading Status */\r
+#define TC_SR_LDRBS (0x1u << 6) /**< \brief (TC_SR) RB Loading Status */\r
+#define TC_SR_ETRGS (0x1u << 7) /**< \brief (TC_SR) External Trigger Status */\r
+#define TC_SR_ENDRX (0x1u << 8) /**< \brief (TC_SR) End of Receiver Transfer */\r
+#define TC_SR_RXBUFF (0x1u << 9) /**< \brief (TC_SR) Reception Buffer Full */\r
+#define TC_SR_CLKSTA (0x1u << 16) /**< \brief (TC_SR) Clock Enabling Status */\r
+#define TC_SR_MTIOA (0x1u << 17) /**< \brief (TC_SR) TIOA Mirror */\r
+#define TC_SR_MTIOB (0x1u << 18) /**< \brief (TC_SR) TIOB Mirror */\r
+/* -------- TC_IER : (TC Offset: N/A) Interrupt Enable Register -------- */\r
+#define TC_IER_COVFS (0x1u << 0) /**< \brief (TC_IER) Counter Overflow */\r
+#define TC_IER_LOVRS (0x1u << 1) /**< \brief (TC_IER) Load Overrun */\r
+#define TC_IER_CPAS (0x1u << 2) /**< \brief (TC_IER) RA Compare */\r
+#define TC_IER_CPBS (0x1u << 3) /**< \brief (TC_IER) RB Compare */\r
+#define TC_IER_CPCS (0x1u << 4) /**< \brief (TC_IER) RC Compare */\r
+#define TC_IER_LDRAS (0x1u << 5) /**< \brief (TC_IER) RA Loading */\r
+#define TC_IER_LDRBS (0x1u << 6) /**< \brief (TC_IER) RB Loading */\r
+#define TC_IER_ETRGS (0x1u << 7) /**< \brief (TC_IER) External Trigger */\r
+#define TC_IER_ENDRX (0x1u << 8) /**< \brief (TC_IER) End of Receiver Transfer */\r
+#define TC_IER_RXBUFF (0x1u << 9) /**< \brief (TC_IER) Reception Buffer Full */\r
+/* -------- TC_IDR : (TC Offset: N/A) Interrupt Disable Register -------- */\r
+#define TC_IDR_COVFS (0x1u << 0) /**< \brief (TC_IDR) Counter Overflow */\r
+#define TC_IDR_LOVRS (0x1u << 1) /**< \brief (TC_IDR) Load Overrun */\r
+#define TC_IDR_CPAS (0x1u << 2) /**< \brief (TC_IDR) RA Compare */\r
+#define TC_IDR_CPBS (0x1u << 3) /**< \brief (TC_IDR) RB Compare */\r
+#define TC_IDR_CPCS (0x1u << 4) /**< \brief (TC_IDR) RC Compare */\r
+#define TC_IDR_LDRAS (0x1u << 5) /**< \brief (TC_IDR) RA Loading */\r
+#define TC_IDR_LDRBS (0x1u << 6) /**< \brief (TC_IDR) RB Loading */\r
+#define TC_IDR_ETRGS (0x1u << 7) /**< \brief (TC_IDR) External Trigger */\r
+#define TC_IDR_ENDRX (0x1u << 8) /**< \brief (TC_IDR) End of Receiver Transfer */\r
+#define TC_IDR_RXBUFF (0x1u << 9) /**< \brief (TC_IDR) Reception Buffer Full */\r
+/* -------- TC_IMR : (TC Offset: N/A) Interrupt Mask Register -------- */\r
+#define TC_IMR_COVFS (0x1u << 0) /**< \brief (TC_IMR) Counter Overflow */\r
+#define TC_IMR_LOVRS (0x1u << 1) /**< \brief (TC_IMR) Load Overrun */\r
+#define TC_IMR_CPAS (0x1u << 2) /**< \brief (TC_IMR) RA Compare */\r
+#define TC_IMR_CPBS (0x1u << 3) /**< \brief (TC_IMR) RB Compare */\r
+#define TC_IMR_CPCS (0x1u << 4) /**< \brief (TC_IMR) RC Compare */\r
+#define TC_IMR_LDRAS (0x1u << 5) /**< \brief (TC_IMR) RA Loading */\r
+#define TC_IMR_LDRBS (0x1u << 6) /**< \brief (TC_IMR) RB Loading */\r
+#define TC_IMR_ETRGS (0x1u << 7) /**< \brief (TC_IMR) External Trigger */\r
+#define TC_IMR_ENDRX (0x1u << 8) /**< \brief (TC_IMR) End of Receiver Transfer */\r
+#define TC_IMR_RXBUFF (0x1u << 9) /**< \brief (TC_IMR) Reception Buffer Full */\r
+/* -------- TC_EMR : (TC Offset: N/A) Extended Mode Register -------- */\r
+#define TC_EMR_TRIGSRCA_Pos 0\r
+#define TC_EMR_TRIGSRCA_Msk (0x3u << TC_EMR_TRIGSRCA_Pos) /**< \brief (TC_EMR) TRIGger SouRCe for input A */\r
+#define TC_EMR_TRIGSRCA_EXTERNAL_TIOAx (0x0u << 0) /**< \brief (TC_EMR) the trigger/capture input A is driven by external pin TIOAx */\r
+#define TC_EMR_TRIGSRCA_PWMx (0x1u << 0) /**< \brief (TC_EMR) the trigger/capture input A is driven internally by PWMx */\r
+#define TC_EMR_TRIGSRCB_Pos 4\r
+#define TC_EMR_TRIGSRCB_Msk (0x3u << TC_EMR_TRIGSRCB_Pos) /**< \brief (TC_EMR) TRIGger SouRCe for input B */\r
+#define TC_EMR_TRIGSRCB_EXTERNAL_TIOBx (0x0u << 4) /**< \brief (TC_EMR) the trigger/capture input B is driven by external pin TIOBx */\r
+#define TC_EMR_TRIGSRCB_PWMx (0x1u << 4) /**< \brief (TC_EMR) the trigger/capture input B is driven internally by PWMx */\r
+#define TC_EMR_NODIVCLK (0x1u << 8) /**< \brief (TC_EMR) NO DIVided CLocK */\r
+/* -------- TC_BCR : (TC Offset: 0xC0) Block Control Register -------- */\r
+#define TC_BCR_SYNC (0x1u << 0) /**< \brief (TC_BCR) Synchro Command */\r
+/* -------- TC_BMR : (TC Offset: 0xC4) Block Mode Register -------- */\r
+#define TC_BMR_TC0XC0S_Pos 0\r
+#define TC_BMR_TC0XC0S_Msk (0x3u << TC_BMR_TC0XC0S_Pos) /**< \brief (TC_BMR) External Clock Signal 0 Selection */\r
+#define TC_BMR_TC0XC0S_TCLK0 (0x0u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TCLK0 */\r
+#define TC_BMR_TC0XC0S_TIOA1 (0x2u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TIOA1 */\r
+#define TC_BMR_TC0XC0S_TIOA2 (0x3u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TIOA2 */\r
+#define TC_BMR_TC1XC1S_Pos 2\r
+#define TC_BMR_TC1XC1S_Msk (0x3u << TC_BMR_TC1XC1S_Pos) /**< \brief (TC_BMR) External Clock Signal 1 Selection */\r
+#define TC_BMR_TC1XC1S_TCLK1 (0x0u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TCLK1 */\r
+#define TC_BMR_TC1XC1S_TIOA0 (0x2u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TIOA0 */\r
+#define TC_BMR_TC1XC1S_TIOA2 (0x3u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TIOA2 */\r
+#define TC_BMR_TC2XC2S_Pos 4\r
+#define TC_BMR_TC2XC2S_Msk (0x3u << TC_BMR_TC2XC2S_Pos) /**< \brief (TC_BMR) External Clock Signal 2 Selection */\r
+#define TC_BMR_TC2XC2S_TCLK2 (0x0u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TCLK2 */\r
+#define TC_BMR_TC2XC2S_TIOA1 (0x2u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TIOA1 */\r
+#define TC_BMR_TC2XC2S_TIOA2 (0x3u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TIOA2 */\r
+#define TC_BMR_QDEN (0x1u << 8) /**< \brief (TC_BMR) Quadrature Decoder ENabled */\r
+#define TC_BMR_POSEN (0x1u << 9) /**< \brief (TC_BMR) POSition ENabled */\r
+#define TC_BMR_SPEEDEN (0x1u << 10) /**< \brief (TC_BMR) SPEED ENabled */\r
+#define TC_BMR_QDTRANS (0x1u << 11) /**< \brief (TC_BMR) Quadrature Decoding TRANSparent */\r
+#define TC_BMR_EDGPHA (0x1u << 12) /**< \brief (TC_BMR) EDGe on PHA count mode */\r
+#define TC_BMR_INVA (0x1u << 13) /**< \brief (TC_BMR) INVerted phA */\r
+#define TC_BMR_INVB (0x1u << 14) /**< \brief (TC_BMR) INVerted phB */\r
+#define TC_BMR_INVIDX (0x1u << 15) /**< \brief (TC_BMR) INVerted InDeX */\r
+#define TC_BMR_SWAP (0x1u << 16) /**< \brief (TC_BMR) SWAP PHA and PHB */\r
+#define TC_BMR_IDXPHB (0x1u << 17) /**< \brief (TC_BMR) InDeX pin is PHB pin */\r
+#define TC_BMR_FILTER (0x1u << 19) /**< \brief (TC_BMR) */\r
+#define TC_BMR_MAXFILT_Pos 20\r
+#define TC_BMR_MAXFILT_Msk (0x3fu << TC_BMR_MAXFILT_Pos) /**< \brief (TC_BMR) MAXimum FILTer */\r
+#define TC_BMR_MAXFILT(value) ((TC_BMR_MAXFILT_Msk & ((value) << TC_BMR_MAXFILT_Pos)))\r
+/* -------- TC_QIER : (TC Offset: 0xC8) QDEC Interrupt Enable Register -------- */\r
+#define TC_QIER_IDX (0x1u << 0) /**< \brief (TC_QIER) InDeX */\r
+#define TC_QIER_DIRCHG (0x1u << 1) /**< \brief (TC_QIER) DIRection CHanGe */\r
+#define TC_QIER_QERR (0x1u << 2) /**< \brief (TC_QIER) Quadrature ERRor */\r
+/* -------- TC_QIDR : (TC Offset: 0xCC) QDEC Interrupt Disable Register -------- */\r
+#define TC_QIDR_IDX (0x1u << 0) /**< \brief (TC_QIDR) InDeX */\r
+#define TC_QIDR_DIRCHG (0x1u << 1) /**< \brief (TC_QIDR) DIRection CHanGe */\r
+#define TC_QIDR_QERR (0x1u << 2) /**< \brief (TC_QIDR) Quadrature ERRor */\r
+/* -------- TC_QIMR : (TC Offset: 0xD0) QDEC Interrupt Mask Register -------- */\r
+#define TC_QIMR_IDX (0x1u << 0) /**< \brief (TC_QIMR) InDeX */\r
+#define TC_QIMR_DIRCHG (0x1u << 1) /**< \brief (TC_QIMR) DIRection CHanGe */\r
+#define TC_QIMR_QERR (0x1u << 2) /**< \brief (TC_QIMR) Quadrature ERRor */\r
+/* -------- TC_QISR : (TC Offset: 0xD4) QDEC Interrupt Status Register -------- */\r
+#define TC_QISR_IDX (0x1u << 0) /**< \brief (TC_QISR) InDeX */\r
+#define TC_QISR_DIRCHG (0x1u << 1) /**< \brief (TC_QISR) DIRection CHanGe */\r
+#define TC_QISR_QERR (0x1u << 2) /**< \brief (TC_QISR) Quadrature ERRor */\r
+#define TC_QISR_DIR (0x1u << 8) /**< \brief (TC_QISR) DIRection */\r
+/* -------- TC_FMR : (TC Offset: 0xD8) Fault Mode Register -------- */\r
+#define TC_FMR_ENCF0 (0x1u << 0) /**< \brief (TC_FMR) ENable Compare Fault Channel 0 */\r
+#define TC_FMR_ENCF1 (0x1u << 1) /**< \brief (TC_FMR) ENable Compare Fault Channel 1 */\r
+/* -------- TC_WPMR : (TC Offset: 0xE4) Write Protect Mode Register -------- */\r
+#define TC_WPMR_WPEN (0x1u << 0) /**< \brief (TC_WPMR) Write Protect Enable */\r
+#define TC_WPMR_WPKEY_Pos 8\r
+#define TC_WPMR_WPKEY_Msk (0xffffffu << TC_WPMR_WPKEY_Pos) /**< \brief (TC_WPMR) Write Protect KEY */\r
+#define TC_WPMR_WPKEY(value) ((TC_WPMR_WPKEY_Msk & ((value) << TC_WPMR_WPKEY_Pos)))\r
+/* -------- TC_RPR : (TC Offset: N/A) Receive Pointer Register -------- */\r
+#define TC_RPR_RXPTR_Pos 0\r
+#define TC_RPR_RXPTR_Msk (0xffffffffu << TC_RPR_RXPTR_Pos) /**< \brief (TC_RPR) Receive Pointer Register */\r
+#define TC_RPR_RXPTR(value) ((TC_RPR_RXPTR_Msk & ((value) << TC_RPR_RXPTR_Pos)))\r
+/* -------- TC_RCR : (TC Offset: N/A) Receive Counter Register -------- */\r
+#define TC_RCR_RXCTR_Pos 0\r
+#define TC_RCR_RXCTR_Msk (0xffffu << TC_RCR_RXCTR_Pos) /**< \brief (TC_RCR) Receive Counter Register */\r
+#define TC_RCR_RXCTR(value) ((TC_RCR_RXCTR_Msk & ((value) << TC_RCR_RXCTR_Pos)))\r
+/* -------- TC_RNPR : (TC Offset: N/A) Receive Next Pointer Register -------- */\r
+#define TC_RNPR_RXNPTR_Pos 0\r
+#define TC_RNPR_RXNPTR_Msk (0xffffffffu << TC_RNPR_RXNPTR_Pos) /**< \brief (TC_RNPR) Receive Next Pointer */\r
+#define TC_RNPR_RXNPTR(value) ((TC_RNPR_RXNPTR_Msk & ((value) << TC_RNPR_RXNPTR_Pos)))\r
+/* -------- TC_RNCR : (TC Offset: N/A) Receive Next Counter Register -------- */\r
+#define TC_RNCR_RXNCTR_Pos 0\r
+#define TC_RNCR_RXNCTR_Msk (0xffffu << TC_RNCR_RXNCTR_Pos) /**< \brief (TC_RNCR) Receive Next Counter */\r
+#define TC_RNCR_RXNCTR(value) ((TC_RNCR_RXNCTR_Msk & ((value) << TC_RNCR_RXNCTR_Pos)))\r
+/* -------- TC_PTCR : (TC Offset: N/A) Transfer Control Register -------- */\r
+#define TC_PTCR_RXTEN (0x1u << 0) /**< \brief (TC_PTCR) Receiver Transfer Enable */\r
+#define TC_PTCR_RXTDIS (0x1u << 1) /**< \brief (TC_PTCR) Receiver Transfer Disable */\r
+#define TC_PTCR_TXTEN (0x1u << 8) /**< \brief (TC_PTCR) Transmitter Transfer Enable */\r
+#define TC_PTCR_TXTDIS (0x1u << 9) /**< \brief (TC_PTCR) Transmitter Transfer Disable */\r
+/* -------- TC_PTSR : (TC Offset: N/A) Transfer Status Register -------- */\r
+#define TC_PTSR_RXTEN (0x1u << 0) /**< \brief (TC_PTSR) Receiver Transfer Enable */\r
+#define TC_PTSR_TXTEN (0x1u << 8) /**< \brief (TC_PTSR) Transmitter Transfer Enable */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM4E_TC_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4E_TWI_COMPONENT_\r
+#define _SAM4E_TWI_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Two-wire Interface */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM4E_TWI Two-wire Interface */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Twi hardware registers */\r
+typedef struct {\r
+ WoReg TWI_CR; /**< \brief (Twi Offset: 0x00) Control Register */\r
+ RwReg TWI_MMR; /**< \brief (Twi Offset: 0x04) Master Mode Register */\r
+ RwReg TWI_SMR; /**< \brief (Twi Offset: 0x08) Slave Mode Register */\r
+ RwReg TWI_IADR; /**< \brief (Twi Offset: 0x0C) Internal Address Register */\r
+ RwReg TWI_CWGR; /**< \brief (Twi Offset: 0x10) Clock Waveform Generator Register */\r
+ RoReg Reserved1[3];\r
+ RoReg TWI_SR; /**< \brief (Twi Offset: 0x20) Status Register */\r
+ WoReg TWI_IER; /**< \brief (Twi Offset: 0x24) Interrupt Enable Register */\r
+ WoReg TWI_IDR; /**< \brief (Twi Offset: 0x28) Interrupt Disable Register */\r
+ RoReg TWI_IMR; /**< \brief (Twi Offset: 0x2C) Interrupt Mask Register */\r
+ RoReg TWI_RHR; /**< \brief (Twi Offset: 0x30) Receive Holding Register */\r
+ WoReg TWI_THR; /**< \brief (Twi Offset: 0x34) Transmit Holding Register */\r
+ RoReg Reserved2[43];\r
+ RwReg TWI_WPROT_MODE; /**< \brief (Twi Offset: 0xE4) Protection Mode Register */\r
+ RoReg TWI_WPROT_STATUS; /**< \brief (Twi Offset: 0xE8) Protection Status Register */\r
+ RoReg Reserved3[5];\r
+ RwReg TWI_RPR; /**< \brief (Twi Offset: 0x100) Receive Pointer Register */\r
+ RwReg TWI_RCR; /**< \brief (Twi Offset: 0x104) Receive Counter Register */\r
+ RwReg TWI_TPR; /**< \brief (Twi Offset: 0x108) Transmit Pointer Register */\r
+ RwReg TWI_TCR; /**< \brief (Twi Offset: 0x10C) Transmit Counter Register */\r
+ RwReg TWI_RNPR; /**< \brief (Twi Offset: 0x110) Receive Next Pointer Register */\r
+ RwReg TWI_RNCR; /**< \brief (Twi Offset: 0x114) Receive Next Counter Register */\r
+ RwReg TWI_TNPR; /**< \brief (Twi Offset: 0x118) Transmit Next Pointer Register */\r
+ RwReg TWI_TNCR; /**< \brief (Twi Offset: 0x11C) Transmit Next Counter Register */\r
+ WoReg TWI_PTCR; /**< \brief (Twi Offset: 0x120) Transfer Control Register */\r
+ RoReg TWI_PTSR; /**< \brief (Twi Offset: 0x124) Transfer Status Register */\r
+} Twi;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- TWI_CR : (TWI Offset: 0x00) Control Register -------- */\r
+#define TWI_CR_START (0x1u << 0) /**< \brief (TWI_CR) Send a START Condition */\r
+#define TWI_CR_STOP (0x1u << 1) /**< \brief (TWI_CR) Send a STOP Condition */\r
+#define TWI_CR_MSEN (0x1u << 2) /**< \brief (TWI_CR) TWI Master Mode Enabled */\r
+#define TWI_CR_MSDIS (0x1u << 3) /**< \brief (TWI_CR) TWI Master Mode Disabled */\r
+#define TWI_CR_SVEN (0x1u << 4) /**< \brief (TWI_CR) TWI Slave Mode Enabled */\r
+#define TWI_CR_SVDIS (0x1u << 5) /**< \brief (TWI_CR) TWI Slave Mode Disabled */\r
+#define TWI_CR_QUICK (0x1u << 6) /**< \brief (TWI_CR) SMBUS Quick Command */\r
+#define TWI_CR_SWRST (0x1u << 7) /**< \brief (TWI_CR) Software Reset */\r
+/* -------- TWI_MMR : (TWI Offset: 0x04) Master Mode Register -------- */\r
+#define TWI_MMR_IADRSZ_Pos 8\r
+#define TWI_MMR_IADRSZ_Msk (0x3u << TWI_MMR_IADRSZ_Pos) /**< \brief (TWI_MMR) Internal Device Address Size */\r
+#define TWI_MMR_IADRSZ_NONE (0x0u << 8) /**< \brief (TWI_MMR) No internal device address */\r
+#define TWI_MMR_IADRSZ_1_BYTE (0x1u << 8) /**< \brief (TWI_MMR) One-byte internal device address */\r
+#define TWI_MMR_IADRSZ_2_BYTE (0x2u << 8) /**< \brief (TWI_MMR) Two-byte internal device address */\r
+#define TWI_MMR_IADRSZ_3_BYTE (0x3u << 8) /**< \brief (TWI_MMR) Three-byte internal device address */\r
+#define TWI_MMR_MREAD (0x1u << 12) /**< \brief (TWI_MMR) Master Read Direction */\r
+#define TWI_MMR_DADR_Pos 16\r
+#define TWI_MMR_DADR_Msk (0x7fu << TWI_MMR_DADR_Pos) /**< \brief (TWI_MMR) Device Address */\r
+#define TWI_MMR_DADR(value) ((TWI_MMR_DADR_Msk & ((value) << TWI_MMR_DADR_Pos)))\r
+/* -------- TWI_SMR : (TWI Offset: 0x08) Slave Mode Register -------- */\r
+#define TWI_SMR_SADR_Pos 16\r
+#define TWI_SMR_SADR_Msk (0x7fu << TWI_SMR_SADR_Pos) /**< \brief (TWI_SMR) Slave Address */\r
+#define TWI_SMR_SADR(value) ((TWI_SMR_SADR_Msk & ((value) << TWI_SMR_SADR_Pos)))\r
+/* -------- TWI_IADR : (TWI Offset: 0x0C) Internal Address Register -------- */\r
+#define TWI_IADR_IADR_Pos 0\r
+#define TWI_IADR_IADR_Msk (0xffffffu << TWI_IADR_IADR_Pos) /**< \brief (TWI_IADR) Internal Address */\r
+#define TWI_IADR_IADR(value) ((TWI_IADR_IADR_Msk & ((value) << TWI_IADR_IADR_Pos)))\r
+/* -------- TWI_CWGR : (TWI Offset: 0x10) Clock Waveform Generator Register -------- */\r
+#define TWI_CWGR_CLDIV_Pos 0\r
+#define TWI_CWGR_CLDIV_Msk (0xffu << TWI_CWGR_CLDIV_Pos) /**< \brief (TWI_CWGR) Clock Low Divider */\r
+#define TWI_CWGR_CLDIV(value) ((TWI_CWGR_CLDIV_Msk & ((value) << TWI_CWGR_CLDIV_Pos)))\r
+#define TWI_CWGR_CHDIV_Pos 8\r
+#define TWI_CWGR_CHDIV_Msk (0xffu << TWI_CWGR_CHDIV_Pos) /**< \brief (TWI_CWGR) Clock High Divider */\r
+#define TWI_CWGR_CHDIV(value) ((TWI_CWGR_CHDIV_Msk & ((value) << TWI_CWGR_CHDIV_Pos)))\r
+#define TWI_CWGR_CKDIV_Pos 16\r
+#define TWI_CWGR_CKDIV_Msk (0x7u << TWI_CWGR_CKDIV_Pos) /**< \brief (TWI_CWGR) Clock Divider */\r
+#define TWI_CWGR_CKDIV(value) ((TWI_CWGR_CKDIV_Msk & ((value) << TWI_CWGR_CKDIV_Pos)))\r
+/* -------- TWI_SR : (TWI Offset: 0x20) Status Register -------- */\r
+#define TWI_SR_TXCOMP (0x1u << 0) /**< \brief (TWI_SR) Transmission Completed (automatically set / reset) */\r
+#define TWI_SR_RXRDY (0x1u << 1) /**< \brief (TWI_SR) Receive Holding Register Ready (automatically set / reset) */\r
+#define TWI_SR_TXRDY (0x1u << 2) /**< \brief (TWI_SR) Transmit Holding Register Ready (automatically set / reset) */\r
+#define TWI_SR_SVREAD (0x1u << 3) /**< \brief (TWI_SR) Slave Read (automatically set / reset) */\r
+#define TWI_SR_SVACC (0x1u << 4) /**< \brief (TWI_SR) Slave Access (automatically set / reset) */\r
+#define TWI_SR_GACC (0x1u << 5) /**< \brief (TWI_SR) General Call Access (clear on read) */\r
+#define TWI_SR_OVRE (0x1u << 6) /**< \brief (TWI_SR) Overrun Error (clear on read) */\r
+#define TWI_SR_NACK (0x1u << 8) /**< \brief (TWI_SR) Not Acknowledged (clear on read) */\r
+#define TWI_SR_ARBLST (0x1u << 9) /**< \brief (TWI_SR) Arbitration Lost (clear on read) */\r
+#define TWI_SR_SCLWS (0x1u << 10) /**< \brief (TWI_SR) Clock Wait State (automatically set / reset) */\r
+#define TWI_SR_EOSACC (0x1u << 11) /**< \brief (TWI_SR) End Of Slave Access (clear on read) */\r
+#define TWI_SR_ENDRX (0x1u << 12) /**< \brief (TWI_SR) End of RX buffer */\r
+#define TWI_SR_ENDTX (0x1u << 13) /**< \brief (TWI_SR) End of TX buffer */\r
+#define TWI_SR_RXBUFF (0x1u << 14) /**< \brief (TWI_SR) RX Buffer Full */\r
+#define TWI_SR_TXBUFE (0x1u << 15) /**< \brief (TWI_SR) TX Buffer Empty */\r
+/* -------- TWI_IER : (TWI Offset: 0x24) Interrupt Enable Register -------- */\r
+#define TWI_IER_TXCOMP (0x1u << 0) /**< \brief (TWI_IER) Transmission Completed Interrupt Enable */\r
+#define TWI_IER_RXRDY (0x1u << 1) /**< \brief (TWI_IER) Receive Holding Register Ready Interrupt Enable */\r
+#define TWI_IER_TXRDY (0x1u << 2) /**< \brief (TWI_IER) Transmit Holding Register Ready Interrupt Enable */\r
+#define TWI_IER_SVACC (0x1u << 4) /**< \brief (TWI_IER) Slave Access Interrupt Enable */\r
+#define TWI_IER_GACC (0x1u << 5) /**< \brief (TWI_IER) General Call Access Interrupt Enable */\r
+#define TWI_IER_OVRE (0x1u << 6) /**< \brief (TWI_IER) Overrun Error Interrupt Enable */\r
+#define TWI_IER_NACK (0x1u << 8) /**< \brief (TWI_IER) Not Acknowledge Interrupt Enable */\r
+#define TWI_IER_ARBLST (0x1u << 9) /**< \brief (TWI_IER) Arbitration Lost Interrupt Enable */\r
+#define TWI_IER_SCL_WS (0x1u << 10) /**< \brief (TWI_IER) Clock Wait State Interrupt Enable */\r
+#define TWI_IER_EOSACC (0x1u << 11) /**< \brief (TWI_IER) End Of Slave Access Interrupt Enable */\r
+#define TWI_IER_ENDRX (0x1u << 12) /**< \brief (TWI_IER) End of Receive Buffer Interrupt Enable */\r
+#define TWI_IER_ENDTX (0x1u << 13) /**< \brief (TWI_IER) End of Transmit Buffer Interrupt Enable */\r
+#define TWI_IER_RXBUFF (0x1u << 14) /**< \brief (TWI_IER) Receive Buffer Full Interrupt Enable */\r
+#define TWI_IER_TXBUFE (0x1u << 15) /**< \brief (TWI_IER) Transmit Buffer Empty Interrupt Enable */\r
+/* -------- TWI_IDR : (TWI Offset: 0x28) Interrupt Disable Register -------- */\r
+#define TWI_IDR_TXCOMP (0x1u << 0) /**< \brief (TWI_IDR) Transmission Completed Interrupt Disable */\r
+#define TWI_IDR_RXRDY (0x1u << 1) /**< \brief (TWI_IDR) Receive Holding Register Ready Interrupt Disable */\r
+#define TWI_IDR_TXRDY (0x1u << 2) /**< \brief (TWI_IDR) Transmit Holding Register Ready Interrupt Disable */\r
+#define TWI_IDR_SVACC (0x1u << 4) /**< \brief (TWI_IDR) Slave Access Interrupt Disable */\r
+#define TWI_IDR_GACC (0x1u << 5) /**< \brief (TWI_IDR) General Call Access Interrupt Disable */\r
+#define TWI_IDR_OVRE (0x1u << 6) /**< \brief (TWI_IDR) Overrun Error Interrupt Disable */\r
+#define TWI_IDR_NACK (0x1u << 8) /**< \brief (TWI_IDR) Not Acknowledge Interrupt Disable */\r
+#define TWI_IDR_ARBLST (0x1u << 9) /**< \brief (TWI_IDR) Arbitration Lost Interrupt Disable */\r
+#define TWI_IDR_SCL_WS (0x1u << 10) /**< \brief (TWI_IDR) Clock Wait State Interrupt Disable */\r
+#define TWI_IDR_EOSACC (0x1u << 11) /**< \brief (TWI_IDR) End Of Slave Access Interrupt Disable */\r
+#define TWI_IDR_ENDRX (0x1u << 12) /**< \brief (TWI_IDR) End of Receive Buffer Interrupt Disable */\r
+#define TWI_IDR_ENDTX (0x1u << 13) /**< \brief (TWI_IDR) End of Transmit Buffer Interrupt Disable */\r
+#define TWI_IDR_RXBUFF (0x1u << 14) /**< \brief (TWI_IDR) Receive Buffer Full Interrupt Disable */\r
+#define TWI_IDR_TXBUFE (0x1u << 15) /**< \brief (TWI_IDR) Transmit Buffer Empty Interrupt Disable */\r
+/* -------- TWI_IMR : (TWI Offset: 0x2C) Interrupt Mask Register -------- */\r
+#define TWI_IMR_TXCOMP (0x1u << 0) /**< \brief (TWI_IMR) Transmission Completed Interrupt Mask */\r
+#define TWI_IMR_RXRDY (0x1u << 1) /**< \brief (TWI_IMR) Receive Holding Register Ready Interrupt Mask */\r
+#define TWI_IMR_TXRDY (0x1u << 2) /**< \brief (TWI_IMR) Transmit Holding Register Ready Interrupt Mask */\r
+#define TWI_IMR_SVACC (0x1u << 4) /**< \brief (TWI_IMR) Slave Access Interrupt Mask */\r
+#define TWI_IMR_GACC (0x1u << 5) /**< \brief (TWI_IMR) General Call Access Interrupt Mask */\r
+#define TWI_IMR_OVRE (0x1u << 6) /**< \brief (TWI_IMR) Overrun Error Interrupt Mask */\r
+#define TWI_IMR_NACK (0x1u << 8) /**< \brief (TWI_IMR) Not Acknowledge Interrupt Mask */\r
+#define TWI_IMR_ARBLST (0x1u << 9) /**< \brief (TWI_IMR) Arbitration Lost Interrupt Mask */\r
+#define TWI_IMR_SCL_WS (0x1u << 10) /**< \brief (TWI_IMR) Clock Wait State Interrupt Mask */\r
+#define TWI_IMR_EOSACC (0x1u << 11) /**< \brief (TWI_IMR) End Of Slave Access Interrupt Mask */\r
+#define TWI_IMR_ENDRX (0x1u << 12) /**< \brief (TWI_IMR) End of Receive Buffer Interrupt Mask */\r
+#define TWI_IMR_ENDTX (0x1u << 13) /**< \brief (TWI_IMR) End of Transmit Buffer Interrupt Mask */\r
+#define TWI_IMR_RXBUFF (0x1u << 14) /**< \brief (TWI_IMR) Receive Buffer Full Interrupt Mask */\r
+#define TWI_IMR_TXBUFE (0x1u << 15) /**< \brief (TWI_IMR) Transmit Buffer Empty Interrupt Mask */\r
+/* -------- TWI_RHR : (TWI Offset: 0x30) Receive Holding Register -------- */\r
+#define TWI_RHR_RXDATA_Pos 0\r
+#define TWI_RHR_RXDATA_Msk (0xffu << TWI_RHR_RXDATA_Pos) /**< \brief (TWI_RHR) Master or Slave Receive Holding Data */\r
+/* -------- TWI_THR : (TWI Offset: 0x34) Transmit Holding Register -------- */\r
+#define TWI_THR_TXDATA_Pos 0\r
+#define TWI_THR_TXDATA_Msk (0xffu << TWI_THR_TXDATA_Pos) /**< \brief (TWI_THR) Master or Slave Transmit Holding Data */\r
+#define TWI_THR_TXDATA(value) ((TWI_THR_TXDATA_Msk & ((value) << TWI_THR_TXDATA_Pos)))\r
+/* -------- TWI_WPROT_MODE : (TWI Offset: 0xE4) Protection Mode Register -------- */\r
+#define TWI_WPROT_MODE_WPROT (0x1u << 0) /**< \brief (TWI_WPROT_MODE) Write protection bit */\r
+#define TWI_WPROT_MODE_SECURITY_CODE_Pos 8\r
+#define TWI_WPROT_MODE_SECURITY_CODE_Msk (0xffffffu << TWI_WPROT_MODE_SECURITY_CODE_Pos) /**< \brief (TWI_WPROT_MODE) Write protection mode security code */\r
+#define TWI_WPROT_MODE_SECURITY_CODE(value) ((TWI_WPROT_MODE_SECURITY_CODE_Msk & ((value) << TWI_WPROT_MODE_SECURITY_CODE_Pos)))\r
+/* -------- TWI_WPROT_STATUS : (TWI Offset: 0xE8) Protection Status Register -------- */\r
+#define TWI_WPROT_STATUS_WPROTERR (0x1u << 0) /**< \brief (TWI_WPROT_STATUS) Write Protection Error */\r
+#define TWI_WPROT_STATUS_WPROTADDR_Pos 8\r
+#define TWI_WPROT_STATUS_WPROTADDR_Msk (0xffffffu << TWI_WPROT_STATUS_WPROTADDR_Pos) /**< \brief (TWI_WPROT_STATUS) Write Protection Error Address */\r
+/* -------- TWI_RPR : (TWI Offset: 0x100) Receive Pointer Register -------- */\r
+#define TWI_RPR_RXPTR_Pos 0\r
+#define TWI_RPR_RXPTR_Msk (0xffffffffu << TWI_RPR_RXPTR_Pos) /**< \brief (TWI_RPR) Receive Pointer Register */\r
+#define TWI_RPR_RXPTR(value) ((TWI_RPR_RXPTR_Msk & ((value) << TWI_RPR_RXPTR_Pos)))\r
+/* -------- TWI_RCR : (TWI Offset: 0x104) Receive Counter Register -------- */\r
+#define TWI_RCR_RXCTR_Pos 0\r
+#define TWI_RCR_RXCTR_Msk (0xffffu << TWI_RCR_RXCTR_Pos) /**< \brief (TWI_RCR) Receive Counter Register */\r
+#define TWI_RCR_RXCTR(value) ((TWI_RCR_RXCTR_Msk & ((value) << TWI_RCR_RXCTR_Pos)))\r
+/* -------- TWI_TPR : (TWI Offset: 0x108) Transmit Pointer Register -------- */\r
+#define TWI_TPR_TXPTR_Pos 0\r
+#define TWI_TPR_TXPTR_Msk (0xffffffffu << TWI_TPR_TXPTR_Pos) /**< \brief (TWI_TPR) Transmit Counter Register */\r
+#define TWI_TPR_TXPTR(value) ((TWI_TPR_TXPTR_Msk & ((value) << TWI_TPR_TXPTR_Pos)))\r
+/* -------- TWI_TCR : (TWI Offset: 0x10C) Transmit Counter Register -------- */\r
+#define TWI_TCR_TXCTR_Pos 0\r
+#define TWI_TCR_TXCTR_Msk (0xffffu << TWI_TCR_TXCTR_Pos) /**< \brief (TWI_TCR) Transmit Counter Register */\r
+#define TWI_TCR_TXCTR(value) ((TWI_TCR_TXCTR_Msk & ((value) << TWI_TCR_TXCTR_Pos)))\r
+/* -------- TWI_RNPR : (TWI Offset: 0x110) Receive Next Pointer Register -------- */\r
+#define TWI_RNPR_RXNPTR_Pos 0\r
+#define TWI_RNPR_RXNPTR_Msk (0xffffffffu << TWI_RNPR_RXNPTR_Pos) /**< \brief (TWI_RNPR) Receive Next Pointer */\r
+#define TWI_RNPR_RXNPTR(value) ((TWI_RNPR_RXNPTR_Msk & ((value) << TWI_RNPR_RXNPTR_Pos)))\r
+/* -------- TWI_RNCR : (TWI Offset: 0x114) Receive Next Counter Register -------- */\r
+#define TWI_RNCR_RXNCTR_Pos 0\r
+#define TWI_RNCR_RXNCTR_Msk (0xffffu << TWI_RNCR_RXNCTR_Pos) /**< \brief (TWI_RNCR) Receive Next Counter */\r
+#define TWI_RNCR_RXNCTR(value) ((TWI_RNCR_RXNCTR_Msk & ((value) << TWI_RNCR_RXNCTR_Pos)))\r
+/* -------- TWI_TNPR : (TWI Offset: 0x118) Transmit Next Pointer Register -------- */\r
+#define TWI_TNPR_TXNPTR_Pos 0\r
+#define TWI_TNPR_TXNPTR_Msk (0xffffffffu << TWI_TNPR_TXNPTR_Pos) /**< \brief (TWI_TNPR) Transmit Next Pointer */\r
+#define TWI_TNPR_TXNPTR(value) ((TWI_TNPR_TXNPTR_Msk & ((value) << TWI_TNPR_TXNPTR_Pos)))\r
+/* -------- TWI_TNCR : (TWI Offset: 0x11C) Transmit Next Counter Register -------- */\r
+#define TWI_TNCR_TXNCTR_Pos 0\r
+#define TWI_TNCR_TXNCTR_Msk (0xffffu << TWI_TNCR_TXNCTR_Pos) /**< \brief (TWI_TNCR) Transmit Counter Next */\r
+#define TWI_TNCR_TXNCTR(value) ((TWI_TNCR_TXNCTR_Msk & ((value) << TWI_TNCR_TXNCTR_Pos)))\r
+/* -------- TWI_PTCR : (TWI Offset: 0x120) Transfer Control Register -------- */\r
+#define TWI_PTCR_RXTEN (0x1u << 0) /**< \brief (TWI_PTCR) Receiver Transfer Enable */\r
+#define TWI_PTCR_RXTDIS (0x1u << 1) /**< \brief (TWI_PTCR) Receiver Transfer Disable */\r
+#define TWI_PTCR_TXTEN (0x1u << 8) /**< \brief (TWI_PTCR) Transmitter Transfer Enable */\r
+#define TWI_PTCR_TXTDIS (0x1u << 9) /**< \brief (TWI_PTCR) Transmitter Transfer Disable */\r
+/* -------- TWI_PTSR : (TWI Offset: 0x124) Transfer Status Register -------- */\r
+#define TWI_PTSR_RXTEN (0x1u << 0) /**< \brief (TWI_PTSR) Receiver Transfer Enable */\r
+#define TWI_PTSR_TXTEN (0x1u << 8) /**< \brief (TWI_PTSR) Transmitter Transfer Enable */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM4E_TWI_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4E_UART_COMPONENT_\r
+#define _SAM4E_UART_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Universal Asynchronous Receiver Transmitter */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM4E_UART Universal Asynchronous Receiver Transmitter */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Uart hardware registers */\r
+typedef struct {\r
+ WoReg UART_CR; /**< \brief (Uart Offset: 0x0000) Control Register */\r
+ RwReg UART_MR; /**< \brief (Uart Offset: 0x0004) Mode Register */\r
+ WoReg UART_IER; /**< \brief (Uart Offset: 0x0008) Interrupt Enable Register */\r
+ WoReg UART_IDR; /**< \brief (Uart Offset: 0x000C) Interrupt Disable Register */\r
+ RoReg UART_IMR; /**< \brief (Uart Offset: 0x0010) Interrupt Mask Register */\r
+ RoReg UART_SR; /**< \brief (Uart Offset: 0x0014) Status Register */\r
+ RoReg UART_RHR; /**< \brief (Uart Offset: 0x0018) Receive Holding Register */\r
+ WoReg UART_THR; /**< \brief (Uart Offset: 0x001C) Transmit Holding Register */\r
+ RwReg UART_BRGR; /**< \brief (Uart Offset: 0x0020) Baud Rate Generator Register */\r
+ RoReg Reserved1[55];\r
+ RwReg UART_RPR; /**< \brief (Uart Offset: 0x100) Receive Pointer Register */\r
+ RwReg UART_RCR; /**< \brief (Uart Offset: 0x104) Receive Counter Register */\r
+ RwReg UART_TPR; /**< \brief (Uart Offset: 0x108) Transmit Pointer Register */\r
+ RwReg UART_TCR; /**< \brief (Uart Offset: 0x10C) Transmit Counter Register */\r
+ RwReg UART_RNPR; /**< \brief (Uart Offset: 0x110) Receive Next Pointer Register */\r
+ RwReg UART_RNCR; /**< \brief (Uart Offset: 0x114) Receive Next Counter Register */\r
+ RwReg UART_TNPR; /**< \brief (Uart Offset: 0x118) Transmit Next Pointer Register */\r
+ RwReg UART_TNCR; /**< \brief (Uart Offset: 0x11C) Transmit Next Counter Register */\r
+ WoReg UART_PTCR; /**< \brief (Uart Offset: 0x120) Transfer Control Register */\r
+ RoReg UART_PTSR; /**< \brief (Uart Offset: 0x124) Transfer Status Register */\r
+} Uart;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- UART_CR : (UART Offset: 0x0000) Control Register -------- */\r
+#define UART_CR_RSTRX (0x1u << 2) /**< \brief (UART_CR) Reset Receiver */\r
+#define UART_CR_RSTTX (0x1u << 3) /**< \brief (UART_CR) Reset Transmitter */\r
+#define UART_CR_RXEN (0x1u << 4) /**< \brief (UART_CR) Receiver Enable */\r
+#define UART_CR_RXDIS (0x1u << 5) /**< \brief (UART_CR) Receiver Disable */\r
+#define UART_CR_TXEN (0x1u << 6) /**< \brief (UART_CR) Transmitter Enable */\r
+#define UART_CR_TXDIS (0x1u << 7) /**< \brief (UART_CR) Transmitter Disable */\r
+#define UART_CR_RSTSTA (0x1u << 8) /**< \brief (UART_CR) Reset Status Bits */\r
+/* -------- UART_MR : (UART Offset: 0x0004) Mode Register -------- */\r
+#define UART_MR_PAR_Pos 9\r
+#define UART_MR_PAR_Msk (0x7u << UART_MR_PAR_Pos) /**< \brief (UART_MR) Parity Type */\r
+#define UART_MR_PAR_EVEN (0x0u << 9) /**< \brief (UART_MR) Even Parity */\r
+#define UART_MR_PAR_ODD (0x1u << 9) /**< \brief (UART_MR) Odd Parity */\r
+#define UART_MR_PAR_SPACE (0x2u << 9) /**< \brief (UART_MR) Space: parity forced to 0 */\r
+#define UART_MR_PAR_MARK (0x3u << 9) /**< \brief (UART_MR) Mark: parity forced to 1 */\r
+#define UART_MR_PAR_NO (0x4u << 9) /**< \brief (UART_MR) No Parity */\r
+#define UART_MR_CHMODE_Pos 14\r
+#define UART_MR_CHMODE_Msk (0x3u << UART_MR_CHMODE_Pos) /**< \brief (UART_MR) Channel Mode */\r
+#define UART_MR_CHMODE_NORMAL (0x0u << 14) /**< \brief (UART_MR) Normal Mode */\r
+#define UART_MR_CHMODE_AUTOMATIC (0x1u << 14) /**< \brief (UART_MR) Automatic Echo */\r
+#define UART_MR_CHMODE_LOCAL_LOOPBACK (0x2u << 14) /**< \brief (UART_MR) Local Loopback */\r
+#define UART_MR_CHMODE_REMOTE_LOOPBACK (0x3u << 14) /**< \brief (UART_MR) Remote Loopback */\r
+/* -------- UART_IER : (UART Offset: 0x0008) Interrupt Enable Register -------- */\r
+#define UART_IER_RXRDY (0x1u << 0) /**< \brief (UART_IER) Enable RXRDY Interrupt */\r
+#define UART_IER_TXRDY (0x1u << 1) /**< \brief (UART_IER) Enable TXRDY Interrupt */\r
+#define UART_IER_ENDRX (0x1u << 3) /**< \brief (UART_IER) Enable End of Receive Transfer Interrupt */\r
+#define UART_IER_ENDTX (0x1u << 4) /**< \brief (UART_IER) Enable End of Transmit Interrupt */\r
+#define UART_IER_OVRE (0x1u << 5) /**< \brief (UART_IER) Enable Overrun Error Interrupt */\r
+#define UART_IER_FRAME (0x1u << 6) /**< \brief (UART_IER) Enable Framing Error Interrupt */\r
+#define UART_IER_PARE (0x1u << 7) /**< \brief (UART_IER) Enable Parity Error Interrupt */\r
+#define UART_IER_TXEMPTY (0x1u << 9) /**< \brief (UART_IER) Enable TXEMPTY Interrupt */\r
+#define UART_IER_TXBUFE (0x1u << 11) /**< \brief (UART_IER) Enable Buffer Empty Interrupt */\r
+#define UART_IER_RXBUFF (0x1u << 12) /**< \brief (UART_IER) Enable Buffer Full Interrupt */\r
+/* -------- UART_IDR : (UART Offset: 0x000C) Interrupt Disable Register -------- */\r
+#define UART_IDR_RXRDY (0x1u << 0) /**< \brief (UART_IDR) Disable RXRDY Interrupt */\r
+#define UART_IDR_TXRDY (0x1u << 1) /**< \brief (UART_IDR) Disable TXRDY Interrupt */\r
+#define UART_IDR_ENDRX (0x1u << 3) /**< \brief (UART_IDR) Disable End of Receive Transfer Interrupt */\r
+#define UART_IDR_ENDTX (0x1u << 4) /**< \brief (UART_IDR) Disable End of Transmit Interrupt */\r
+#define UART_IDR_OVRE (0x1u << 5) /**< \brief (UART_IDR) Disable Overrun Error Interrupt */\r
+#define UART_IDR_FRAME (0x1u << 6) /**< \brief (UART_IDR) Disable Framing Error Interrupt */\r
+#define UART_IDR_PARE (0x1u << 7) /**< \brief (UART_IDR) Disable Parity Error Interrupt */\r
+#define UART_IDR_TXEMPTY (0x1u << 9) /**< \brief (UART_IDR) Disable TXEMPTY Interrupt */\r
+#define UART_IDR_TXBUFE (0x1u << 11) /**< \brief (UART_IDR) Disable Buffer Empty Interrupt */\r
+#define UART_IDR_RXBUFF (0x1u << 12) /**< \brief (UART_IDR) Disable Buffer Full Interrupt */\r
+/* -------- UART_IMR : (UART Offset: 0x0010) Interrupt Mask Register -------- */\r
+#define UART_IMR_RXRDY (0x1u << 0) /**< \brief (UART_IMR) Mask RXRDY Interrupt */\r
+#define UART_IMR_TXRDY (0x1u << 1) /**< \brief (UART_IMR) Disable TXRDY Interrupt */\r
+#define UART_IMR_ENDRX (0x1u << 3) /**< \brief (UART_IMR) Mask End of Receive Transfer Interrupt */\r
+#define UART_IMR_ENDTX (0x1u << 4) /**< \brief (UART_IMR) Mask End of Transmit Interrupt */\r
+#define UART_IMR_OVRE (0x1u << 5) /**< \brief (UART_IMR) Mask Overrun Error Interrupt */\r
+#define UART_IMR_FRAME (0x1u << 6) /**< \brief (UART_IMR) Mask Framing Error Interrupt */\r
+#define UART_IMR_PARE (0x1u << 7) /**< \brief (UART_IMR) Mask Parity Error Interrupt */\r
+#define UART_IMR_TXEMPTY (0x1u << 9) /**< \brief (UART_IMR) Mask TXEMPTY Interrupt */\r
+#define UART_IMR_TXBUFE (0x1u << 11) /**< \brief (UART_IMR) Mask TXBUFE Interrupt */\r
+#define UART_IMR_RXBUFF (0x1u << 12) /**< \brief (UART_IMR) Mask RXBUFF Interrupt */\r
+/* -------- UART_SR : (UART Offset: 0x0014) Status Register -------- */\r
+#define UART_SR_RXRDY (0x1u << 0) /**< \brief (UART_SR) Receiver Ready */\r
+#define UART_SR_TXRDY (0x1u << 1) /**< \brief (UART_SR) Transmitter Ready */\r
+#define UART_SR_ENDRX (0x1u << 3) /**< \brief (UART_SR) End of Receiver Transfer */\r
+#define UART_SR_ENDTX (0x1u << 4) /**< \brief (UART_SR) End of Transmitter Transfer */\r
+#define UART_SR_OVRE (0x1u << 5) /**< \brief (UART_SR) Overrun Error */\r
+#define UART_SR_FRAME (0x1u << 6) /**< \brief (UART_SR) Framing Error */\r
+#define UART_SR_PARE (0x1u << 7) /**< \brief (UART_SR) Parity Error */\r
+#define UART_SR_TXEMPTY (0x1u << 9) /**< \brief (UART_SR) Transmitter Empty */\r
+#define UART_SR_TXBUFE (0x1u << 11) /**< \brief (UART_SR) Transmission Buffer Empty */\r
+#define UART_SR_RXBUFF (0x1u << 12) /**< \brief (UART_SR) Receive Buffer Full */\r
+/* -------- UART_RHR : (UART Offset: 0x0018) Receive Holding Register -------- */\r
+#define UART_RHR_RXCHR_Pos 0\r
+#define UART_RHR_RXCHR_Msk (0xffu << UART_RHR_RXCHR_Pos) /**< \brief (UART_RHR) Received Character */\r
+/* -------- UART_THR : (UART Offset: 0x001C) Transmit Holding Register -------- */\r
+#define UART_THR_TXCHR_Pos 0\r
+#define UART_THR_TXCHR_Msk (0xffu << UART_THR_TXCHR_Pos) /**< \brief (UART_THR) Character to be Transmitted */\r
+#define UART_THR_TXCHR(value) ((UART_THR_TXCHR_Msk & ((value) << UART_THR_TXCHR_Pos)))\r
+/* -------- UART_BRGR : (UART Offset: 0x0020) Baud Rate Generator Register -------- */\r
+#define UART_BRGR_CD_Pos 0\r
+#define UART_BRGR_CD_Msk (0xffffu << UART_BRGR_CD_Pos) /**< \brief (UART_BRGR) Clock Divisor */\r
+#define UART_BRGR_CD(value) ((UART_BRGR_CD_Msk & ((value) << UART_BRGR_CD_Pos)))\r
+/* -------- UART_RPR : (UART Offset: 0x100) Receive Pointer Register -------- */\r
+#define UART_RPR_RXPTR_Pos 0\r
+#define UART_RPR_RXPTR_Msk (0xffffffffu << UART_RPR_RXPTR_Pos) /**< \brief (UART_RPR) Receive Pointer Register */\r
+#define UART_RPR_RXPTR(value) ((UART_RPR_RXPTR_Msk & ((value) << UART_RPR_RXPTR_Pos)))\r
+/* -------- UART_RCR : (UART Offset: 0x104) Receive Counter Register -------- */\r
+#define UART_RCR_RXCTR_Pos 0\r
+#define UART_RCR_RXCTR_Msk (0xffffu << UART_RCR_RXCTR_Pos) /**< \brief (UART_RCR) Receive Counter Register */\r
+#define UART_RCR_RXCTR(value) ((UART_RCR_RXCTR_Msk & ((value) << UART_RCR_RXCTR_Pos)))\r
+/* -------- UART_TPR : (UART Offset: 0x108) Transmit Pointer Register -------- */\r
+#define UART_TPR_TXPTR_Pos 0\r
+#define UART_TPR_TXPTR_Msk (0xffffffffu << UART_TPR_TXPTR_Pos) /**< \brief (UART_TPR) Transmit Counter Register */\r
+#define UART_TPR_TXPTR(value) ((UART_TPR_TXPTR_Msk & ((value) << UART_TPR_TXPTR_Pos)))\r
+/* -------- UART_TCR : (UART Offset: 0x10C) Transmit Counter Register -------- */\r
+#define UART_TCR_TXCTR_Pos 0\r
+#define UART_TCR_TXCTR_Msk (0xffffu << UART_TCR_TXCTR_Pos) /**< \brief (UART_TCR) Transmit Counter Register */\r
+#define UART_TCR_TXCTR(value) ((UART_TCR_TXCTR_Msk & ((value) << UART_TCR_TXCTR_Pos)))\r
+/* -------- UART_RNPR : (UART Offset: 0x110) Receive Next Pointer Register -------- */\r
+#define UART_RNPR_RXNPTR_Pos 0\r
+#define UART_RNPR_RXNPTR_Msk (0xffffffffu << UART_RNPR_RXNPTR_Pos) /**< \brief (UART_RNPR) Receive Next Pointer */\r
+#define UART_RNPR_RXNPTR(value) ((UART_RNPR_RXNPTR_Msk & ((value) << UART_RNPR_RXNPTR_Pos)))\r
+/* -------- UART_RNCR : (UART Offset: 0x114) Receive Next Counter Register -------- */\r
+#define UART_RNCR_RXNCTR_Pos 0\r
+#define UART_RNCR_RXNCTR_Msk (0xffffu << UART_RNCR_RXNCTR_Pos) /**< \brief (UART_RNCR) Receive Next Counter */\r
+#define UART_RNCR_RXNCTR(value) ((UART_RNCR_RXNCTR_Msk & ((value) << UART_RNCR_RXNCTR_Pos)))\r
+/* -------- UART_TNPR : (UART Offset: 0x118) Transmit Next Pointer Register -------- */\r
+#define UART_TNPR_TXNPTR_Pos 0\r
+#define UART_TNPR_TXNPTR_Msk (0xffffffffu << UART_TNPR_TXNPTR_Pos) /**< \brief (UART_TNPR) Transmit Next Pointer */\r
+#define UART_TNPR_TXNPTR(value) ((UART_TNPR_TXNPTR_Msk & ((value) << UART_TNPR_TXNPTR_Pos)))\r
+/* -------- UART_TNCR : (UART Offset: 0x11C) Transmit Next Counter Register -------- */\r
+#define UART_TNCR_TXNCTR_Pos 0\r
+#define UART_TNCR_TXNCTR_Msk (0xffffu << UART_TNCR_TXNCTR_Pos) /**< \brief (UART_TNCR) Transmit Counter Next */\r
+#define UART_TNCR_TXNCTR(value) ((UART_TNCR_TXNCTR_Msk & ((value) << UART_TNCR_TXNCTR_Pos)))\r
+/* -------- UART_PTCR : (UART Offset: 0x120) Transfer Control Register -------- */\r
+#define UART_PTCR_RXTEN (0x1u << 0) /**< \brief (UART_PTCR) Receiver Transfer Enable */\r
+#define UART_PTCR_RXTDIS (0x1u << 1) /**< \brief (UART_PTCR) Receiver Transfer Disable */\r
+#define UART_PTCR_TXTEN (0x1u << 8) /**< \brief (UART_PTCR) Transmitter Transfer Enable */\r
+#define UART_PTCR_TXTDIS (0x1u << 9) /**< \brief (UART_PTCR) Transmitter Transfer Disable */\r
+/* -------- UART_PTSR : (UART Offset: 0x124) Transfer Status Register -------- */\r
+#define UART_PTSR_RXTEN (0x1u << 0) /**< \brief (UART_PTSR) Receiver Transfer Enable */\r
+#define UART_PTSR_TXTEN (0x1u << 8) /**< \brief (UART_PTSR) Transmitter Transfer Enable */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM4E_UART_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4E_UDP_COMPONENT_\r
+#define _SAM4E_UDP_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR USB Device Port */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM4E_UDP USB Device Port */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Udp hardware registers */\r
+typedef struct {\r
+ RoReg UDP_FRM_NUM; /**< \brief (Udp Offset: 0x000) Frame Number Register */\r
+ RwReg UDP_GLB_STAT; /**< \brief (Udp Offset: 0x004) Global State Register */\r
+ RwReg UDP_FADDR; /**< \brief (Udp Offset: 0x008) Function Address Register */\r
+ RoReg Reserved1[1];\r
+ WoReg UDP_IER; /**< \brief (Udp Offset: 0x010) Interrupt Enable Register */\r
+ WoReg UDP_IDR; /**< \brief (Udp Offset: 0x014) Interrupt Disable Register */\r
+ RoReg UDP_IMR; /**< \brief (Udp Offset: 0x018) Interrupt Mask Register */\r
+ RoReg UDP_ISR; /**< \brief (Udp Offset: 0x01C) Interrupt Status Register */\r
+ WoReg UDP_ICR; /**< \brief (Udp Offset: 0x020) Interrupt Clear Register */\r
+ RoReg Reserved2[1];\r
+ RwReg UDP_RST_EP; /**< \brief (Udp Offset: 0x028) Reset Endpoint Register */\r
+ RoReg Reserved3[1];\r
+ RwReg UDP_CSR[8]; /**< \brief (Udp Offset: 0x030) Endpoint Control and Status Register */\r
+ RwReg UDP_FDR[8]; /**< \brief (Udp Offset: 0x050) Endpoint FIFO Data Register */\r
+ RoReg Reserved4[1];\r
+ RwReg UDP_TXVC; /**< \brief (Udp Offset: 0x074) Transceiver Control Register */\r
+} Udp;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- UDP_FRM_NUM : (UDP Offset: 0x000) Frame Number Register -------- */\r
+#define UDP_FRM_NUM_FRM_NUM_Pos 0\r
+#define UDP_FRM_NUM_FRM_NUM_Msk (0x7ffu << UDP_FRM_NUM_FRM_NUM_Pos) /**< \brief (UDP_FRM_NUM) Frame Number as Defined in the Packet Field Formats */\r
+#define UDP_FRM_NUM_FRM_ERR (0x1u << 16) /**< \brief (UDP_FRM_NUM) Frame Error */\r
+#define UDP_FRM_NUM_FRM_OK (0x1u << 17) /**< \brief (UDP_FRM_NUM) Frame OK */\r
+/* -------- UDP_GLB_STAT : (UDP Offset: 0x004) Global State Register -------- */\r
+#define UDP_GLB_STAT_FADDEN (0x1u << 0) /**< \brief (UDP_GLB_STAT) Function Address Enable */\r
+#define UDP_GLB_STAT_CONFG (0x1u << 1) /**< \brief (UDP_GLB_STAT) Configured */\r
+#define UDP_GLB_STAT_ESR (0x1u << 2) /**< \brief (UDP_GLB_STAT) Enable Send Resume */\r
+#define UDP_GLB_STAT_RSMINPR (0x1u << 3) /**< \brief (UDP_GLB_STAT) */\r
+#define UDP_GLB_STAT_RMWUPE (0x1u << 4) /**< \brief (UDP_GLB_STAT) Remote Wake Up Enable */\r
+/* -------- UDP_FADDR : (UDP Offset: 0x008) Function Address Register -------- */\r
+#define UDP_FADDR_FADD_Pos 0\r
+#define UDP_FADDR_FADD_Msk (0x7fu << UDP_FADDR_FADD_Pos) /**< \brief (UDP_FADDR) Function Address Value */\r
+#define UDP_FADDR_FADD(value) ((UDP_FADDR_FADD_Msk & ((value) << UDP_FADDR_FADD_Pos)))\r
+#define UDP_FADDR_FEN (0x1u << 8) /**< \brief (UDP_FADDR) Function Enable */\r
+/* -------- UDP_IER : (UDP Offset: 0x010) Interrupt Enable Register -------- */\r
+#define UDP_IER_EP0INT (0x1u << 0) /**< \brief (UDP_IER) Enable Endpoint 0 Interrupt */\r
+#define UDP_IER_EP1INT (0x1u << 1) /**< \brief (UDP_IER) Enable Endpoint 1 Interrupt */\r
+#define UDP_IER_EP2INT (0x1u << 2) /**< \brief (UDP_IER) Enable Endpoint 2Interrupt */\r
+#define UDP_IER_EP3INT (0x1u << 3) /**< \brief (UDP_IER) Enable Endpoint 3 Interrupt */\r
+#define UDP_IER_EP4INT (0x1u << 4) /**< \brief (UDP_IER) Enable Endpoint 4 Interrupt */\r
+#define UDP_IER_EP5INT (0x1u << 5) /**< \brief (UDP_IER) Enable Endpoint 5 Interrupt */\r
+#define UDP_IER_EP6INT (0x1u << 6) /**< \brief (UDP_IER) Enable Endpoint 6 Interrupt */\r
+#define UDP_IER_EP7INT (0x1u << 7) /**< \brief (UDP_IER) Enable Endpoint 7 Interrupt */\r
+#define UDP_IER_RXSUSP (0x1u << 8) /**< \brief (UDP_IER) Enable UDP Suspend Interrupt */\r
+#define UDP_IER_RXRSM (0x1u << 9) /**< \brief (UDP_IER) Enable UDP Resume Interrupt */\r
+#define UDP_IER_EXTRSM (0x1u << 10) /**< \brief (UDP_IER) */\r
+#define UDP_IER_SOFINT (0x1u << 11) /**< \brief (UDP_IER) Enable Start Of Frame Interrupt */\r
+#define UDP_IER_WAKEUP (0x1u << 13) /**< \brief (UDP_IER) Enable UDP bus Wakeup Interrupt */\r
+/* -------- UDP_IDR : (UDP Offset: 0x014) Interrupt Disable Register -------- */\r
+#define UDP_IDR_EP0INT (0x1u << 0) /**< \brief (UDP_IDR) Disable Endpoint 0 Interrupt */\r
+#define UDP_IDR_EP1INT (0x1u << 1) /**< \brief (UDP_IDR) Disable Endpoint 1 Interrupt */\r
+#define UDP_IDR_EP2INT (0x1u << 2) /**< \brief (UDP_IDR) Disable Endpoint 2 Interrupt */\r
+#define UDP_IDR_EP3INT (0x1u << 3) /**< \brief (UDP_IDR) Disable Endpoint 3 Interrupt */\r
+#define UDP_IDR_EP4INT (0x1u << 4) /**< \brief (UDP_IDR) Disable Endpoint 4 Interrupt */\r
+#define UDP_IDR_EP5INT (0x1u << 5) /**< \brief (UDP_IDR) Disable Endpoint 5 Interrupt */\r
+#define UDP_IDR_EP6INT (0x1u << 6) /**< \brief (UDP_IDR) Disable Endpoint 6 Interrupt */\r
+#define UDP_IDR_EP7INT (0x1u << 7) /**< \brief (UDP_IDR) Disable Endpoint 7 Interrupt */\r
+#define UDP_IDR_RXSUSP (0x1u << 8) /**< \brief (UDP_IDR) Disable UDP Suspend Interrupt */\r
+#define UDP_IDR_RXRSM (0x1u << 9) /**< \brief (UDP_IDR) Disable UDP Resume Interrupt */\r
+#define UDP_IDR_EXTRSM (0x1u << 10) /**< \brief (UDP_IDR) */\r
+#define UDP_IDR_SOFINT (0x1u << 11) /**< \brief (UDP_IDR) Disable Start Of Frame Interrupt */\r
+#define UDP_IDR_WAKEUP (0x1u << 13) /**< \brief (UDP_IDR) Disable USB Bus Interrupt */\r
+/* -------- UDP_IMR : (UDP Offset: 0x018) Interrupt Mask Register -------- */\r
+#define UDP_IMR_EP0INT (0x1u << 0) /**< \brief (UDP_IMR) Mask Endpoint 0 Interrupt */\r
+#define UDP_IMR_EP1INT (0x1u << 1) /**< \brief (UDP_IMR) Mask Endpoint 1 Interrupt */\r
+#define UDP_IMR_EP2INT (0x1u << 2) /**< \brief (UDP_IMR) Mask Endpoint 2 Interrupt */\r
+#define UDP_IMR_EP3INT (0x1u << 3) /**< \brief (UDP_IMR) Mask Endpoint 3 Interrupt */\r
+#define UDP_IMR_EP4INT (0x1u << 4) /**< \brief (UDP_IMR) Mask Endpoint 4 Interrupt */\r
+#define UDP_IMR_EP5INT (0x1u << 5) /**< \brief (UDP_IMR) Mask Endpoint 5 Interrupt */\r
+#define UDP_IMR_EP6INT (0x1u << 6) /**< \brief (UDP_IMR) Mask Endpoint 6 Interrupt */\r
+#define UDP_IMR_EP7INT (0x1u << 7) /**< \brief (UDP_IMR) Mask Endpoint 7 Interrupt */\r
+#define UDP_IMR_RXSUSP (0x1u << 8) /**< \brief (UDP_IMR) Mask UDP Suspend Interrupt */\r
+#define UDP_IMR_RXRSM (0x1u << 9) /**< \brief (UDP_IMR) Mask UDP Resume Interrupt. */\r
+#define UDP_IMR_EXTRSM (0x1u << 10) /**< \brief (UDP_IMR) */\r
+#define UDP_IMR_SOFINT (0x1u << 11) /**< \brief (UDP_IMR) Mask Start Of Frame Interrupt */\r
+#define UDP_IMR_BIT12 (0x1u << 12) /**< \brief (UDP_IMR) UDP_IMR Bit 12 */\r
+#define UDP_IMR_WAKEUP (0x1u << 13) /**< \brief (UDP_IMR) USB Bus WAKEUP Interrupt */\r
+/* -------- UDP_ISR : (UDP Offset: 0x01C) Interrupt Status Register -------- */\r
+#define UDP_ISR_EP0INT (0x1u << 0) /**< \brief (UDP_ISR) Endpoint 0 Interrupt Status */\r
+#define UDP_ISR_EP1INT (0x1u << 1) /**< \brief (UDP_ISR) Endpoint 1 Interrupt Status */\r
+#define UDP_ISR_EP2INT (0x1u << 2) /**< \brief (UDP_ISR) Endpoint 2 Interrupt Status */\r
+#define UDP_ISR_EP3INT (0x1u << 3) /**< \brief (UDP_ISR) Endpoint 3 Interrupt Status */\r
+#define UDP_ISR_EP4INT (0x1u << 4) /**< \brief (UDP_ISR) Endpoint 4 Interrupt Status */\r
+#define UDP_ISR_EP5INT (0x1u << 5) /**< \brief (UDP_ISR) Endpoint 5 Interrupt Status */\r
+#define UDP_ISR_EP6INT (0x1u << 6) /**< \brief (UDP_ISR) Endpoint 6 Interrupt Status */\r
+#define UDP_ISR_EP7INT (0x1u << 7) /**< \brief (UDP_ISR) Endpoint 7Interrupt Status */\r
+#define UDP_ISR_RXSUSP (0x1u << 8) /**< \brief (UDP_ISR) UDP Suspend Interrupt Status */\r
+#define UDP_ISR_RXRSM (0x1u << 9) /**< \brief (UDP_ISR) UDP Resume Interrupt Status */\r
+#define UDP_ISR_EXTRSM (0x1u << 10) /**< \brief (UDP_ISR) */\r
+#define UDP_ISR_SOFINT (0x1u << 11) /**< \brief (UDP_ISR) Start of Frame Interrupt Status */\r
+#define UDP_ISR_ENDBUSRES (0x1u << 12) /**< \brief (UDP_ISR) End of BUS Reset Interrupt Status */\r
+#define UDP_ISR_WAKEUP (0x1u << 13) /**< \brief (UDP_ISR) UDP Resume Interrupt Status */\r
+/* -------- UDP_ICR : (UDP Offset: 0x020) Interrupt Clear Register -------- */\r
+#define UDP_ICR_RXSUSP (0x1u << 8) /**< \brief (UDP_ICR) Clear UDP Suspend Interrupt */\r
+#define UDP_ICR_RXRSM (0x1u << 9) /**< \brief (UDP_ICR) Clear UDP Resume Interrupt */\r
+#define UDP_ICR_EXTRSM (0x1u << 10) /**< \brief (UDP_ICR) */\r
+#define UDP_ICR_SOFINT (0x1u << 11) /**< \brief (UDP_ICR) Clear Start Of Frame Interrupt */\r
+#define UDP_ICR_ENDBUSRES (0x1u << 12) /**< \brief (UDP_ICR) Clear End of Bus Reset Interrupt */\r
+#define UDP_ICR_WAKEUP (0x1u << 13) /**< \brief (UDP_ICR) Clear Wakeup Interrupt */\r
+/* -------- UDP_RST_EP : (UDP Offset: 0x028) Reset Endpoint Register -------- */\r
+#define UDP_RST_EP_EP0 (0x1u << 0) /**< \brief (UDP_RST_EP) Reset Endpoint 0 */\r
+#define UDP_RST_EP_EP1 (0x1u << 1) /**< \brief (UDP_RST_EP) Reset Endpoint 1 */\r
+#define UDP_RST_EP_EP2 (0x1u << 2) /**< \brief (UDP_RST_EP) Reset Endpoint 2 */\r
+#define UDP_RST_EP_EP3 (0x1u << 3) /**< \brief (UDP_RST_EP) Reset Endpoint 3 */\r
+#define UDP_RST_EP_EP4 (0x1u << 4) /**< \brief (UDP_RST_EP) Reset Endpoint 4 */\r
+#define UDP_RST_EP_EP5 (0x1u << 5) /**< \brief (UDP_RST_EP) Reset Endpoint 5 */\r
+#define UDP_RST_EP_EP6 (0x1u << 6) /**< \brief (UDP_RST_EP) Reset Endpoint 6 */\r
+#define UDP_RST_EP_EP7 (0x1u << 7) /**< \brief (UDP_RST_EP) Reset Endpoint 7 */\r
+/* -------- UDP_CSR[8] : (UDP Offset: 0x030) Endpoint Control and Status Register -------- */\r
+#define UDP_CSR_TXCOMP (0x1u << 0) /**< \brief (UDP_CSR[8]) Generates an IN Packet with Data Previously Written in the DPR */\r
+#define UDP_CSR_RX_DATA_BK0 (0x1u << 1) /**< \brief (UDP_CSR[8]) Receive Data Bank 0 */\r
+#define UDP_CSR_RXSETUP (0x1u << 2) /**< \brief (UDP_CSR[8]) Received Setup */\r
+#define UDP_CSR_STALLSENT (0x1u << 3) /**< \brief (UDP_CSR[8]) Stall Sent */\r
+#define UDP_CSR_TXPKTRDY (0x1u << 4) /**< \brief (UDP_CSR[8]) Transmit Packet Ready */\r
+#define UDP_CSR_FORCESTALL (0x1u << 5) /**< \brief (UDP_CSR[8]) Force Stall (used by Control, Bulk and Isochronous Endpoints) */\r
+#define UDP_CSR_RX_DATA_BK1 (0x1u << 6) /**< \brief (UDP_CSR[8]) Receive Data Bank 1 (only used by endpoints with ping-pong attributes) */\r
+#define UDP_CSR_DIR (0x1u << 7) /**< \brief (UDP_CSR[8]) Transfer Direction (only available for control endpoints) */\r
+#define UDP_CSR_EPTYPE_Pos 8\r
+#define UDP_CSR_EPTYPE_Msk (0x7u << UDP_CSR_EPTYPE_Pos) /**< \brief (UDP_CSR[8]) Endpoint Type */\r
+#define UDP_CSR_EPTYPE_CTRL (0x0u << 8) /**< \brief (UDP_CSR[8]) Control */\r
+#define UDP_CSR_EPTYPE_ISO_OUT (0x1u << 8) /**< \brief (UDP_CSR[8]) Isochronous OUT */\r
+#define UDP_CSR_EPTYPE_BULK_OUT (0x2u << 8) /**< \brief (UDP_CSR[8]) Bulk OUT */\r
+#define UDP_CSR_EPTYPE_INT_OUT (0x3u << 8) /**< \brief (UDP_CSR[8]) Interrupt OUT */\r
+#define UDP_CSR_EPTYPE_ISO_IN (0x5u << 8) /**< \brief (UDP_CSR[8]) Isochronous IN */\r
+#define UDP_CSR_EPTYPE_BULK_IN (0x6u << 8) /**< \brief (UDP_CSR[8]) Bulk IN */\r
+#define UDP_CSR_EPTYPE_INT_IN (0x7u << 8) /**< \brief (UDP_CSR[8]) Interrupt IN */\r
+#define UDP_CSR_DTGLE (0x1u << 11) /**< \brief (UDP_CSR[8]) Data Toggle */\r
+#define UDP_CSR_EPEDS (0x1u << 15) /**< \brief (UDP_CSR[8]) Endpoint Enable Disable */\r
+#define UDP_CSR_RXBYTECNT_Pos 16\r
+#define UDP_CSR_RXBYTECNT_Msk (0x7ffu << UDP_CSR_RXBYTECNT_Pos) /**< \brief (UDP_CSR[8]) Number of Bytes Available in the FIFO */\r
+#define UDP_CSR_RXBYTECNT(value) ((UDP_CSR_RXBYTECNT_Msk & ((value) << UDP_CSR_RXBYTECNT_Pos)))\r
+#define UDP_CSR_ISOERROR (0x1u << 3) /**< \brief (UDP_CSR[8]) A CRC error has been detected in an isochronous transfer */\r
+/* -------- UDP_FDR[8] : (UDP Offset: 0x050) Endpoint FIFO Data Register -------- */\r
+#define UDP_FDR_FIFO_DATA_Pos 0\r
+#define UDP_FDR_FIFO_DATA_Msk (0xffu << UDP_FDR_FIFO_DATA_Pos) /**< \brief (UDP_FDR[8]) FIFO Data Value */\r
+#define UDP_FDR_FIFO_DATA(value) ((UDP_FDR_FIFO_DATA_Msk & ((value) << UDP_FDR_FIFO_DATA_Pos)))\r
+/* -------- UDP_TXVC : (UDP Offset: 0x074) Transceiver Control Register -------- */\r
+#define UDP_TXVC_TXVDIS (0x1u << 8) /**< \brief (UDP_TXVC) Transceiver Disable */\r
+#define UDP_TXVC_PUON (0x1u << 9) /**< \brief (UDP_TXVC) Pull-up On */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM4E_UDP_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4E_USART_COMPONENT_\r
+#define _SAM4E_USART_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Universal Synchronous Asynchronous Receiver Transmitter */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM4E_USART Universal Synchronous Asynchronous Receiver Transmitter */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Usart hardware registers */\r
+typedef struct {\r
+ WoReg US_CR; /**< \brief (Usart Offset: 0x0000) Control Register */\r
+ RwReg US_MR; /**< \brief (Usart Offset: 0x0004) Mode Register */\r
+ WoReg US_IER; /**< \brief (Usart Offset: 0x0008) Interrupt Enable Register */\r
+ WoReg US_IDR; /**< \brief (Usart Offset: 0x000C) Interrupt Disable Register */\r
+ RoReg US_IMR; /**< \brief (Usart Offset: 0x0010) Interrupt Mask Register */\r
+ RoReg US_CSR; /**< \brief (Usart Offset: 0x0014) Channel Status Register */\r
+ RoReg US_RHR; /**< \brief (Usart Offset: 0x0018) Receiver Holding Register */\r
+ WoReg US_THR; /**< \brief (Usart Offset: 0x001C) Transmitter Holding Register */\r
+ RwReg US_BRGR; /**< \brief (Usart Offset: 0x0020) Baud Rate Generator Register */\r
+ RwReg US_RTOR; /**< \brief (Usart Offset: 0x0024) Receiver Time-out Register */\r
+ RwReg US_TTGR; /**< \brief (Usart Offset: 0x0028) Transmitter Timeguard Register */\r
+ RoReg Reserved1[5];\r
+ RwReg US_FIDI; /**< \brief (Usart Offset: 0x0040) FI DI Ratio Register */\r
+ RoReg US_NER; /**< \brief (Usart Offset: 0x0044) Number of Errors Register */\r
+ RoReg Reserved2[1];\r
+ RwReg US_IF; /**< \brief (Usart Offset: 0x004C) IrDA Filter Register */\r
+ RwReg US_MAN; /**< \brief (Usart Offset: 0x0050) Manchester Encoder Decoder Register */\r
+ RoReg Reserved3[36];\r
+ RwReg US_WPMR; /**< \brief (Usart Offset: 0xE4) Write Protect Mode Register */\r
+ RoReg US_WPSR; /**< \brief (Usart Offset: 0xE8) Write Protect Status Register */\r
+ RoReg Reserved4[5];\r
+ RwReg US_RPR; /**< \brief (Usart Offset: 0x100) Receive Pointer Register */\r
+ RwReg US_RCR; /**< \brief (Usart Offset: 0x104) Receive Counter Register */\r
+ RwReg US_TPR; /**< \brief (Usart Offset: 0x108) Transmit Pointer Register */\r
+ RwReg US_TCR; /**< \brief (Usart Offset: 0x10C) Transmit Counter Register */\r
+ RwReg US_RNPR; /**< \brief (Usart Offset: 0x110) Receive Next Pointer Register */\r
+ RwReg US_RNCR; /**< \brief (Usart Offset: 0x114) Receive Next Counter Register */\r
+ RwReg US_TNPR; /**< \brief (Usart Offset: 0x118) Transmit Next Pointer Register */\r
+ RwReg US_TNCR; /**< \brief (Usart Offset: 0x11C) Transmit Next Counter Register */\r
+ WoReg US_PTCR; /**< \brief (Usart Offset: 0x120) Transfer Control Register */\r
+ RoReg US_PTSR; /**< \brief (Usart Offset: 0x124) Transfer Status Register */\r
+} Usart;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- US_CR : (USART Offset: 0x0000) Control Register -------- */\r
+#define US_CR_RSTRX (0x1u << 2) /**< \brief (US_CR) Reset Receiver */\r
+#define US_CR_RSTTX (0x1u << 3) /**< \brief (US_CR) Reset Transmitter */\r
+#define US_CR_RXEN (0x1u << 4) /**< \brief (US_CR) Receiver Enable */\r
+#define US_CR_RXDIS (0x1u << 5) /**< \brief (US_CR) Receiver Disable */\r
+#define US_CR_TXEN (0x1u << 6) /**< \brief (US_CR) Transmitter Enable */\r
+#define US_CR_TXDIS (0x1u << 7) /**< \brief (US_CR) Transmitter Disable */\r
+#define US_CR_RSTSTA (0x1u << 8) /**< \brief (US_CR) Reset Status Bits */\r
+#define US_CR_STTBRK (0x1u << 9) /**< \brief (US_CR) Start Break */\r
+#define US_CR_STPBRK (0x1u << 10) /**< \brief (US_CR) Stop Break */\r
+#define US_CR_STTTO (0x1u << 11) /**< \brief (US_CR) Start Time-out */\r
+#define US_CR_SENDA (0x1u << 12) /**< \brief (US_CR) Send Address */\r
+#define US_CR_RSTIT (0x1u << 13) /**< \brief (US_CR) Reset Iterations */\r
+#define US_CR_RSTNACK (0x1u << 14) /**< \brief (US_CR) Reset Non Acknowledge */\r
+#define US_CR_RETTO (0x1u << 15) /**< \brief (US_CR) Rearm Time-out */\r
+#define US_CR_DTREN (0x1u << 16) /**< \brief (US_CR) Data Terminal Ready Enable */\r
+#define US_CR_DTRDIS (0x1u << 17) /**< \brief (US_CR) Data Terminal Ready Disable */\r
+#define US_CR_RTSEN (0x1u << 18) /**< \brief (US_CR) Request to Send Enable */\r
+#define US_CR_RTSDIS (0x1u << 19) /**< \brief (US_CR) Request to Send Disable */\r
+#define US_CR_FCS (0x1u << 18) /**< \brief (US_CR) Force SPI Chip Select */\r
+#define US_CR_RCS (0x1u << 19) /**< \brief (US_CR) Release SPI Chip Select */\r
+/* -------- US_MR : (USART Offset: 0x0004) Mode Register -------- */\r
+#define US_MR_USART_MODE_Pos 0\r
+#define US_MR_USART_MODE_Msk (0xfu << US_MR_USART_MODE_Pos) /**< \brief (US_MR) USART Mode of Operation */\r
+#define US_MR_USART_MODE_NORMAL (0x0u << 0) /**< \brief (US_MR) Normal mode */\r
+#define US_MR_USART_MODE_RS485 (0x1u << 0) /**< \brief (US_MR) RS485 */\r
+#define US_MR_USART_MODE_HW_HANDSHAKING (0x2u << 0) /**< \brief (US_MR) Hardware Handshaking */\r
+#define US_MR_USART_MODE_MODEM (0x3u << 0) /**< \brief (US_MR) Modem */\r
+#define US_MR_USART_MODE_IS07816_T_0 (0x4u << 0) /**< \brief (US_MR) IS07816 Protocol: T = 0 */\r
+#define US_MR_USART_MODE_IS07816_T_1 (0x6u << 0) /**< \brief (US_MR) IS07816 Protocol: T = 1 */\r
+#define US_MR_USART_MODE_IRDA (0x8u << 0) /**< \brief (US_MR) IrDA */\r
+#define US_MR_USART_MODE_SPI_MASTER (0xEu << 0) /**< \brief (US_MR) SPI Master */\r
+#define US_MR_USART_MODE_SPI_SLAVE (0xFu << 0) /**< \brief (US_MR) SPI Slave */\r
+#define US_MR_USCLKS_Pos 4\r
+#define US_MR_USCLKS_Msk (0x3u << US_MR_USCLKS_Pos) /**< \brief (US_MR) Clock Selection */\r
+#define US_MR_USCLKS_MCK (0x0u << 4) /**< \brief (US_MR) Master Clock MCK is selected */\r
+#define US_MR_USCLKS_DIV (0x1u << 4) /**< \brief (US_MR) Internal Clock Divided MCK/DIV (DIV=8) is selected */\r
+#define US_MR_USCLKS_SCK (0x3u << 4) /**< \brief (US_MR) Serial Clock SLK is selected */\r
+#define US_MR_CHRL_Pos 6\r
+#define US_MR_CHRL_Msk (0x3u << US_MR_CHRL_Pos) /**< \brief (US_MR) Character Length. */\r
+#define US_MR_CHRL_5_BIT (0x0u << 6) /**< \brief (US_MR) Character length is 5 bits */\r
+#define US_MR_CHRL_6_BIT (0x1u << 6) /**< \brief (US_MR) Character length is 6 bits */\r
+#define US_MR_CHRL_7_BIT (0x2u << 6) /**< \brief (US_MR) Character length is 7 bits */\r
+#define US_MR_CHRL_8_BIT (0x3u << 6) /**< \brief (US_MR) Character length is 8 bits */\r
+#define US_MR_SYNC (0x1u << 8) /**< \brief (US_MR) Synchronous Mode Select */\r
+#define US_MR_PAR_Pos 9\r
+#define US_MR_PAR_Msk (0x7u << US_MR_PAR_Pos) /**< \brief (US_MR) Parity Type */\r
+#define US_MR_PAR_EVEN (0x0u << 9) /**< \brief (US_MR) Even parity */\r
+#define US_MR_PAR_ODD (0x1u << 9) /**< \brief (US_MR) Odd parity */\r
+#define US_MR_PAR_SPACE (0x2u << 9) /**< \brief (US_MR) Parity forced to 0 (Space) */\r
+#define US_MR_PAR_MARK (0x3u << 9) /**< \brief (US_MR) Parity forced to 1 (Mark) */\r
+#define US_MR_PAR_NO (0x4u << 9) /**< \brief (US_MR) No parity */\r
+#define US_MR_PAR_MULTIDROP (0x6u << 9) /**< \brief (US_MR) Multidrop mode */\r
+#define US_MR_NBSTOP_Pos 12\r
+#define US_MR_NBSTOP_Msk (0x3u << US_MR_NBSTOP_Pos) /**< \brief (US_MR) Number of Stop Bits */\r
+#define US_MR_NBSTOP_1_BIT (0x0u << 12) /**< \brief (US_MR) 1 stop bit */\r
+#define US_MR_NBSTOP_1_5_BIT (0x1u << 12) /**< \brief (US_MR) 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1) */\r
+#define US_MR_NBSTOP_2_BIT (0x2u << 12) /**< \brief (US_MR) 2 stop bits */\r
+#define US_MR_CHMODE_Pos 14\r
+#define US_MR_CHMODE_Msk (0x3u << US_MR_CHMODE_Pos) /**< \brief (US_MR) Channel Mode */\r
+#define US_MR_CHMODE_NORMAL (0x0u << 14) /**< \brief (US_MR) Normal Mode */\r
+#define US_MR_CHMODE_AUTOMATIC (0x1u << 14) /**< \brief (US_MR) Automatic Echo. Receiver input is connected to the TXD pin. */\r
+#define US_MR_CHMODE_LOCAL_LOOPBACK (0x2u << 14) /**< \brief (US_MR) Local Loopback. Transmitter output is connected to the Receiver Input. */\r
+#define US_MR_CHMODE_REMOTE_LOOPBACK (0x3u << 14) /**< \brief (US_MR) Remote Loopback. RXD pin is internally connected to the TXD pin. */\r
+#define US_MR_MSBF (0x1u << 16) /**< \brief (US_MR) Bit Order */\r
+#define US_MR_MODE9 (0x1u << 17) /**< \brief (US_MR) 9-bit Character Length */\r
+#define US_MR_CLKO (0x1u << 18) /**< \brief (US_MR) Clock Output Select */\r
+#define US_MR_OVER (0x1u << 19) /**< \brief (US_MR) Oversampling Mode */\r
+#define US_MR_INACK (0x1u << 20) /**< \brief (US_MR) Inhibit Non Acknowledge */\r
+#define US_MR_DSNACK (0x1u << 21) /**< \brief (US_MR) Disable Successive NACK */\r
+#define US_MR_VAR_SYNC (0x1u << 22) /**< \brief (US_MR) Variable Synchronization of Command/Data Sync Start Frame Delimiter */\r
+#define US_MR_INVDATA (0x1u << 23) /**< \brief (US_MR) Inverted Data */\r
+#define US_MR_MAX_ITERATION_Pos 24\r
+#define US_MR_MAX_ITERATION_Msk (0x7u << US_MR_MAX_ITERATION_Pos) /**< \brief (US_MR) Maximum Number of Automatic Iteration */\r
+#define US_MR_MAX_ITERATION(value) ((US_MR_MAX_ITERATION_Msk & ((value) << US_MR_MAX_ITERATION_Pos)))\r
+#define US_MR_FILTER (0x1u << 28) /**< \brief (US_MR) Infrared Receive Line Filter */\r
+#define US_MR_MAN (0x1u << 29) /**< \brief (US_MR) Manchester Encoder/Decoder Enable */\r
+#define US_MR_MODSYNC (0x1u << 30) /**< \brief (US_MR) Manchester Synchronization Mode */\r
+#define US_MR_ONEBIT (0x1u << 31) /**< \brief (US_MR) Start Frame Delimiter Selector */\r
+#define US_MR_CPHA (0x1u << 8) /**< \brief (US_MR) SPI Clock Phase */\r
+#define US_MR_CPOL (0x1u << 16) /**< \brief (US_MR) SPI Clock Polarity */\r
+#define US_MR_WRDBT (0x1u << 20) /**< \brief (US_MR) Wait Read Data Before Transfer */\r
+/* -------- US_IER : (USART Offset: 0x0008) Interrupt Enable Register -------- */\r
+#define US_IER_RXRDY (0x1u << 0) /**< \brief (US_IER) RXRDY Interrupt Enable */\r
+#define US_IER_TXRDY (0x1u << 1) /**< \brief (US_IER) TXRDY Interrupt Enable */\r
+#define US_IER_RXBRK (0x1u << 2) /**< \brief (US_IER) Receiver Break Interrupt Enable */\r
+#define US_IER_ENDRX (0x1u << 3) /**< \brief (US_IER) End of Receive Transfer Interrupt Enable (available in all USART modes of operation) */\r
+#define US_IER_ENDTX (0x1u << 4) /**< \brief (US_IER) End of Transmit Interrupt Enable (available in all USART modes of operation) */\r
+#define US_IER_OVRE (0x1u << 5) /**< \brief (US_IER) Overrun Error Interrupt Enable */\r
+#define US_IER_FRAME (0x1u << 6) /**< \brief (US_IER) Framing Error Interrupt Enable */\r
+#define US_IER_PARE (0x1u << 7) /**< \brief (US_IER) Parity Error Interrupt Enable */\r
+#define US_IER_TIMEOUT (0x1u << 8) /**< \brief (US_IER) Time-out Interrupt Enable */\r
+#define US_IER_TXEMPTY (0x1u << 9) /**< \brief (US_IER) TXEMPTY Interrupt Enable */\r
+#define US_IER_ITER (0x1u << 10) /**< \brief (US_IER) Max number of Repetitions Reached Interrupt Enable */\r
+#define US_IER_TXBUFE (0x1u << 11) /**< \brief (US_IER) Buffer Empty Interrupt Enable (available in all USART modes of operation) */\r
+#define US_IER_RXBUFF (0x1u << 12) /**< \brief (US_IER) Buffer Full Interrupt Enable (available in all USART modes of operation) */\r
+#define US_IER_NACK (0x1u << 13) /**< \brief (US_IER) Non AcknowledgeInterrupt Enable */\r
+#define US_IER_RIIC (0x1u << 16) /**< \brief (US_IER) Ring Indicator Input Change Enable */\r
+#define US_IER_DSRIC (0x1u << 17) /**< \brief (US_IER) Data Set Ready Input Change Enable */\r
+#define US_IER_DCDIC (0x1u << 18) /**< \brief (US_IER) Data Carrier Detect Input Change Interrupt Enable */\r
+#define US_IER_CTSIC (0x1u << 19) /**< \brief (US_IER) Clear to Send Input Change Interrupt Enable */\r
+#define US_IER_MANE (0x1u << 24) /**< \brief (US_IER) Manchester Error Interrupt Enable */\r
+#define US_IER_UNRE (0x1u << 10) /**< \brief (US_IER) SPI Underrun Error Interrupt Enable */\r
+/* -------- US_IDR : (USART Offset: 0x000C) Interrupt Disable Register -------- */\r
+#define US_IDR_RXRDY (0x1u << 0) /**< \brief (US_IDR) RXRDY Interrupt Disable */\r
+#define US_IDR_TXRDY (0x1u << 1) /**< \brief (US_IDR) TXRDY Interrupt Disable */\r
+#define US_IDR_RXBRK (0x1u << 2) /**< \brief (US_IDR) Receiver Break Interrupt Disable */\r
+#define US_IDR_ENDRX (0x1u << 3) /**< \brief (US_IDR) End of Receive Transfer Interrupt Disable (available in all USART modes of operation) */\r
+#define US_IDR_ENDTX (0x1u << 4) /**< \brief (US_IDR) End of Transmit Interrupt Disable (available in all USART modes of operation) */\r
+#define US_IDR_OVRE (0x1u << 5) /**< \brief (US_IDR) Overrun Error Interrupt Enable */\r
+#define US_IDR_FRAME (0x1u << 6) /**< \brief (US_IDR) Framing Error Interrupt Disable */\r
+#define US_IDR_PARE (0x1u << 7) /**< \brief (US_IDR) Parity Error Interrupt Disable */\r
+#define US_IDR_TIMEOUT (0x1u << 8) /**< \brief (US_IDR) Time-out Interrupt Disable */\r
+#define US_IDR_TXEMPTY (0x1u << 9) /**< \brief (US_IDR) TXEMPTY Interrupt Disable */\r
+#define US_IDR_ITER (0x1u << 10) /**< \brief (US_IDR) Max Number of Repetitions Reached Interrupt Disable */\r
+#define US_IDR_TXBUFE (0x1u << 11) /**< \brief (US_IDR) Buffer Empty Interrupt Disable (available in all USART modes of operation) */\r
+#define US_IDR_RXBUFF (0x1u << 12) /**< \brief (US_IDR) Buffer Full Interrupt Disable (available in all USART modes of operation) */\r
+#define US_IDR_NACK (0x1u << 13) /**< \brief (US_IDR) Non AcknowledgeInterrupt Disable */\r
+#define US_IDR_RIIC (0x1u << 16) /**< \brief (US_IDR) Ring Indicator Input Change Disable */\r
+#define US_IDR_DSRIC (0x1u << 17) /**< \brief (US_IDR) Data Set Ready Input Change Disable */\r
+#define US_IDR_DCDIC (0x1u << 18) /**< \brief (US_IDR) Data Carrier Detect Input Change Interrupt Disable */\r
+#define US_IDR_CTSIC (0x1u << 19) /**< \brief (US_IDR) Clear to Send Input Change Interrupt Disable */\r
+#define US_IDR_MANE (0x1u << 24) /**< \brief (US_IDR) Manchester Error Interrupt Disable */\r
+#define US_IDR_UNRE (0x1u << 10) /**< \brief (US_IDR) SPI Underrun Error Interrupt Disable */\r
+/* -------- US_IMR : (USART Offset: 0x0010) Interrupt Mask Register -------- */\r
+#define US_IMR_RXRDY (0x1u << 0) /**< \brief (US_IMR) RXRDY Interrupt Mask */\r
+#define US_IMR_TXRDY (0x1u << 1) /**< \brief (US_IMR) TXRDY Interrupt Mask */\r
+#define US_IMR_RXBRK (0x1u << 2) /**< \brief (US_IMR) Receiver Break Interrupt Mask */\r
+#define US_IMR_ENDRX (0x1u << 3) /**< \brief (US_IMR) End of Receive Transfer Interrupt Mask (available in all USART modes of operation) */\r
+#define US_IMR_ENDTX (0x1u << 4) /**< \brief (US_IMR) End of Transmit Interrupt Mask (available in all USART modes of operation) */\r
+#define US_IMR_OVRE (0x1u << 5) /**< \brief (US_IMR) Overrun Error Interrupt Mask */\r
+#define US_IMR_FRAME (0x1u << 6) /**< \brief (US_IMR) Framing Error Interrupt Mask */\r
+#define US_IMR_PARE (0x1u << 7) /**< \brief (US_IMR) Parity Error Interrupt Mask */\r
+#define US_IMR_TIMEOUT (0x1u << 8) /**< \brief (US_IMR) Time-out Interrupt Mask */\r
+#define US_IMR_TXEMPTY (0x1u << 9) /**< \brief (US_IMR) TXEMPTY Interrupt Mask */\r
+#define US_IMR_ITER (0x1u << 10) /**< \brief (US_IMR) Max Number of Repetitions Reached Interrupt Mask */\r
+#define US_IMR_TXBUFE (0x1u << 11) /**< \brief (US_IMR) Buffer Empty Interrupt Mask (available in all USART modes of operation) */\r
+#define US_IMR_RXBUFF (0x1u << 12) /**< \brief (US_IMR) Buffer Full Interrupt Mask (available in all USART modes of operation) */\r
+#define US_IMR_NACK (0x1u << 13) /**< \brief (US_IMR) Non AcknowledgeInterrupt Mask */\r
+#define US_IMR_RIIC (0x1u << 16) /**< \brief (US_IMR) Ring Indicator Input Change Mask */\r
+#define US_IMR_DSRIC (0x1u << 17) /**< \brief (US_IMR) Data Set Ready Input Change Mask */\r
+#define US_IMR_DCDIC (0x1u << 18) /**< \brief (US_IMR) Data Carrier Detect Input Change Interrupt Mask */\r
+#define US_IMR_CTSIC (0x1u << 19) /**< \brief (US_IMR) Clear to Send Input Change Interrupt Mask */\r
+#define US_IMR_MANE (0x1u << 24) /**< \brief (US_IMR) Manchester Error Interrupt Mask */\r
+#define US_IMR_UNRE (0x1u << 10) /**< \brief (US_IMR) SPI Underrun Error Interrupt Mask */\r
+/* -------- US_CSR : (USART Offset: 0x0014) Channel Status Register -------- */\r
+#define US_CSR_RXRDY (0x1u << 0) /**< \brief (US_CSR) Receiver Ready */\r
+#define US_CSR_TXRDY (0x1u << 1) /**< \brief (US_CSR) Transmitter Ready */\r
+#define US_CSR_RXBRK (0x1u << 2) /**< \brief (US_CSR) Break Received/End of Break */\r
+#define US_CSR_ENDRX (0x1u << 3) /**< \brief (US_CSR) End of Receiver Transfer */\r
+#define US_CSR_ENDTX (0x1u << 4) /**< \brief (US_CSR) End of Transmitter Transfer */\r
+#define US_CSR_OVRE (0x1u << 5) /**< \brief (US_CSR) Overrun Error */\r
+#define US_CSR_FRAME (0x1u << 6) /**< \brief (US_CSR) Framing Error */\r
+#define US_CSR_PARE (0x1u << 7) /**< \brief (US_CSR) Parity Error */\r
+#define US_CSR_TIMEOUT (0x1u << 8) /**< \brief (US_CSR) Receiver Time-out */\r
+#define US_CSR_TXEMPTY (0x1u << 9) /**< \brief (US_CSR) Transmitter Empty */\r
+#define US_CSR_ITER (0x1u << 10) /**< \brief (US_CSR) MaxNumber of Repetitions Reached */\r
+#define US_CSR_TXBUFE (0x1u << 11) /**< \brief (US_CSR) Transmission Buffer Empty */\r
+#define US_CSR_RXBUFF (0x1u << 12) /**< \brief (US_CSR) Reception Buffer Full */\r
+#define US_CSR_NACK (0x1u << 13) /**< \brief (US_CSR) Non AcknowledgeInterrupt */\r
+#define US_CSR_RIIC (0x1u << 16) /**< \brief (US_CSR) Ring Indicator Input Change Flag */\r
+#define US_CSR_DSRIC (0x1u << 17) /**< \brief (US_CSR) Data Set Ready Input Change Flag */\r
+#define US_CSR_DCDIC (0x1u << 18) /**< \brief (US_CSR) Data Carrier Detect Input Change Flag */\r
+#define US_CSR_CTSIC (0x1u << 19) /**< \brief (US_CSR) Clear to Send Input Change Flag */\r
+#define US_CSR_RI (0x1u << 20) /**< \brief (US_CSR) Image of RI Input */\r
+#define US_CSR_DSR (0x1u << 21) /**< \brief (US_CSR) Image of DSR Input */\r
+#define US_CSR_DCD (0x1u << 22) /**< \brief (US_CSR) Image of DCD Input */\r
+#define US_CSR_CTS (0x1u << 23) /**< \brief (US_CSR) Image of CTS Input */\r
+#define US_CSR_MANERR (0x1u << 24) /**< \brief (US_CSR) Manchester Error */\r
+#define US_CSR_UNRE (0x1u << 10) /**< \brief (US_CSR) Underrun Error */\r
+/* -------- US_RHR : (USART Offset: 0x0018) Receiver Holding Register -------- */\r
+#define US_RHR_RXCHR_Pos 0\r
+#define US_RHR_RXCHR_Msk (0x1ffu << US_RHR_RXCHR_Pos) /**< \brief (US_RHR) Received Character */\r
+#define US_RHR_RXSYNH (0x1u << 15) /**< \brief (US_RHR) Received Sync */\r
+/* -------- US_THR : (USART Offset: 0x001C) Transmitter Holding Register -------- */\r
+#define US_THR_TXCHR_Pos 0\r
+#define US_THR_TXCHR_Msk (0x1ffu << US_THR_TXCHR_Pos) /**< \brief (US_THR) Character to be Transmitted */\r
+#define US_THR_TXCHR(value) ((US_THR_TXCHR_Msk & ((value) << US_THR_TXCHR_Pos)))\r
+#define US_THR_TXSYNH (0x1u << 15) /**< \brief (US_THR) Sync Field to be Transmitted */\r
+/* -------- US_BRGR : (USART Offset: 0x0020) Baud Rate Generator Register -------- */\r
+#define US_BRGR_CD_Pos 0\r
+#define US_BRGR_CD_Msk (0xffffu << US_BRGR_CD_Pos) /**< \brief (US_BRGR) Clock Divider */\r
+#define US_BRGR_CD(value) ((US_BRGR_CD_Msk & ((value) << US_BRGR_CD_Pos)))\r
+#define US_BRGR_FP_Pos 16\r
+#define US_BRGR_FP_Msk (0x7u << US_BRGR_FP_Pos) /**< \brief (US_BRGR) Fractional Part */\r
+#define US_BRGR_FP(value) ((US_BRGR_FP_Msk & ((value) << US_BRGR_FP_Pos)))\r
+/* -------- US_RTOR : (USART Offset: 0x0024) Receiver Time-out Register -------- */\r
+#define US_RTOR_TO_Pos 0\r
+#define US_RTOR_TO_Msk (0xffffu << US_RTOR_TO_Pos) /**< \brief (US_RTOR) Time-out Value */\r
+#define US_RTOR_TO(value) ((US_RTOR_TO_Msk & ((value) << US_RTOR_TO_Pos)))\r
+/* -------- US_TTGR : (USART Offset: 0x0028) Transmitter Timeguard Register -------- */\r
+#define US_TTGR_TG_Pos 0\r
+#define US_TTGR_TG_Msk (0xffu << US_TTGR_TG_Pos) /**< \brief (US_TTGR) Timeguard Value */\r
+#define US_TTGR_TG(value) ((US_TTGR_TG_Msk & ((value) << US_TTGR_TG_Pos)))\r
+/* -------- US_FIDI : (USART Offset: 0x0040) FI DI Ratio Register -------- */\r
+#define US_FIDI_FI_DI_RATIO_Pos 0\r
+#define US_FIDI_FI_DI_RATIO_Msk (0x7ffu << US_FIDI_FI_DI_RATIO_Pos) /**< \brief (US_FIDI) FI Over DI Ratio Value */\r
+#define US_FIDI_FI_DI_RATIO(value) ((US_FIDI_FI_DI_RATIO_Msk & ((value) << US_FIDI_FI_DI_RATIO_Pos)))\r
+/* -------- US_NER : (USART Offset: 0x0044) Number of Errors Register -------- */\r
+#define US_NER_NB_ERRORS_Pos 0\r
+#define US_NER_NB_ERRORS_Msk (0xffu << US_NER_NB_ERRORS_Pos) /**< \brief (US_NER) Number of Errors */\r
+/* -------- US_IF : (USART Offset: 0x004C) IrDA Filter Register -------- */\r
+#define US_IF_IRDA_FILTER_Pos 0\r
+#define US_IF_IRDA_FILTER_Msk (0xffu << US_IF_IRDA_FILTER_Pos) /**< \brief (US_IF) IrDA Filter */\r
+#define US_IF_IRDA_FILTER(value) ((US_IF_IRDA_FILTER_Msk & ((value) << US_IF_IRDA_FILTER_Pos)))\r
+/* -------- US_MAN : (USART Offset: 0x0050) Manchester Encoder Decoder Register -------- */\r
+#define US_MAN_TX_PL_Pos 0\r
+#define US_MAN_TX_PL_Msk (0xfu << US_MAN_TX_PL_Pos) /**< \brief (US_MAN) Transmitter Preamble Length */\r
+#define US_MAN_TX_PL(value) ((US_MAN_TX_PL_Msk & ((value) << US_MAN_TX_PL_Pos)))\r
+#define US_MAN_TX_PP_Pos 8\r
+#define US_MAN_TX_PP_Msk (0x3u << US_MAN_TX_PP_Pos) /**< \brief (US_MAN) Transmitter Preamble Pattern */\r
+#define US_MAN_TX_PP_ALL_ONE (0x0u << 8) /**< \brief (US_MAN) The preamble is composed of '1's */\r
+#define US_MAN_TX_PP_ALL_ZERO (0x1u << 8) /**< \brief (US_MAN) The preamble is composed of '0's */\r
+#define US_MAN_TX_PP_ZERO_ONE (0x2u << 8) /**< \brief (US_MAN) The preamble is composed of '01's */\r
+#define US_MAN_TX_PP_ONE_ZERO (0x3u << 8) /**< \brief (US_MAN) The preamble is composed of '10's */\r
+#define US_MAN_TX_MPOL (0x1u << 12) /**< \brief (US_MAN) Transmitter Manchester Polarity */\r
+#define US_MAN_RX_PL_Pos 16\r
+#define US_MAN_RX_PL_Msk (0xfu << US_MAN_RX_PL_Pos) /**< \brief (US_MAN) Receiver Preamble Length */\r
+#define US_MAN_RX_PL(value) ((US_MAN_RX_PL_Msk & ((value) << US_MAN_RX_PL_Pos)))\r
+#define US_MAN_RX_PP_Pos 24\r
+#define US_MAN_RX_PP_Msk (0x3u << US_MAN_RX_PP_Pos) /**< \brief (US_MAN) Receiver Preamble Pattern detected */\r
+#define US_MAN_RX_PP_ALL_ONE (0x0u << 24) /**< \brief (US_MAN) The preamble is composed of '1's */\r
+#define US_MAN_RX_PP_ALL_ZERO (0x1u << 24) /**< \brief (US_MAN) The preamble is composed of '0's */\r
+#define US_MAN_RX_PP_ZERO_ONE (0x2u << 24) /**< \brief (US_MAN) The preamble is composed of '01's */\r
+#define US_MAN_RX_PP_ONE_ZERO (0x3u << 24) /**< \brief (US_MAN) The preamble is composed of '10's */\r
+#define US_MAN_RX_MPOL (0x1u << 28) /**< \brief (US_MAN) Receiver Manchester Polarity */\r
+#define US_MAN_ONE (0x1u << 29) /**< \brief (US_MAN) Must Be Set to 1 */\r
+#define US_MAN_DRIFT (0x1u << 30) /**< \brief (US_MAN) Drift Compensation */\r
+/* -------- US_WPMR : (USART Offset: 0xE4) Write Protect Mode Register -------- */\r
+#define US_WPMR_WPEN (0x1u << 0) /**< \brief (US_WPMR) Write Protect Enable */\r
+#define US_WPMR_WPKEY_Pos 8\r
+#define US_WPMR_WPKEY_Msk (0xffffffu << US_WPMR_WPKEY_Pos) /**< \brief (US_WPMR) Write Protect KEY */\r
+#define US_WPMR_WPKEY(value) ((US_WPMR_WPKEY_Msk & ((value) << US_WPMR_WPKEY_Pos)))\r
+/* -------- US_WPSR : (USART Offset: 0xE8) Write Protect Status Register -------- */\r
+#define US_WPSR_WPVS (0x1u << 0) /**< \brief (US_WPSR) Write Protect Violation Status */\r
+#define US_WPSR_WPVSRC_Pos 8\r
+#define US_WPSR_WPVSRC_Msk (0xffffu << US_WPSR_WPVSRC_Pos) /**< \brief (US_WPSR) Write Protect Violation Source */\r
+/* -------- US_RPR : (USART Offset: 0x100) Receive Pointer Register -------- */\r
+#define US_RPR_RXPTR_Pos 0\r
+#define US_RPR_RXPTR_Msk (0xffffffffu << US_RPR_RXPTR_Pos) /**< \brief (US_RPR) Receive Pointer Register */\r
+#define US_RPR_RXPTR(value) ((US_RPR_RXPTR_Msk & ((value) << US_RPR_RXPTR_Pos)))\r
+/* -------- US_RCR : (USART Offset: 0x104) Receive Counter Register -------- */\r
+#define US_RCR_RXCTR_Pos 0\r
+#define US_RCR_RXCTR_Msk (0xffffu << US_RCR_RXCTR_Pos) /**< \brief (US_RCR) Receive Counter Register */\r
+#define US_RCR_RXCTR(value) ((US_RCR_RXCTR_Msk & ((value) << US_RCR_RXCTR_Pos)))\r
+/* -------- US_TPR : (USART Offset: 0x108) Transmit Pointer Register -------- */\r
+#define US_TPR_TXPTR_Pos 0\r
+#define US_TPR_TXPTR_Msk (0xffffffffu << US_TPR_TXPTR_Pos) /**< \brief (US_TPR) Transmit Counter Register */\r
+#define US_TPR_TXPTR(value) ((US_TPR_TXPTR_Msk & ((value) << US_TPR_TXPTR_Pos)))\r
+/* -------- US_TCR : (USART Offset: 0x10C) Transmit Counter Register -------- */\r
+#define US_TCR_TXCTR_Pos 0\r
+#define US_TCR_TXCTR_Msk (0xffffu << US_TCR_TXCTR_Pos) /**< \brief (US_TCR) Transmit Counter Register */\r
+#define US_TCR_TXCTR(value) ((US_TCR_TXCTR_Msk & ((value) << US_TCR_TXCTR_Pos)))\r
+/* -------- US_RNPR : (USART Offset: 0x110) Receive Next Pointer Register -------- */\r
+#define US_RNPR_RXNPTR_Pos 0\r
+#define US_RNPR_RXNPTR_Msk (0xffffffffu << US_RNPR_RXNPTR_Pos) /**< \brief (US_RNPR) Receive Next Pointer */\r
+#define US_RNPR_RXNPTR(value) ((US_RNPR_RXNPTR_Msk & ((value) << US_RNPR_RXNPTR_Pos)))\r
+/* -------- US_RNCR : (USART Offset: 0x114) Receive Next Counter Register -------- */\r
+#define US_RNCR_RXNCTR_Pos 0\r
+#define US_RNCR_RXNCTR_Msk (0xffffu << US_RNCR_RXNCTR_Pos) /**< \brief (US_RNCR) Receive Next Counter */\r
+#define US_RNCR_RXNCTR(value) ((US_RNCR_RXNCTR_Msk & ((value) << US_RNCR_RXNCTR_Pos)))\r
+/* -------- US_TNPR : (USART Offset: 0x118) Transmit Next Pointer Register -------- */\r
+#define US_TNPR_TXNPTR_Pos 0\r
+#define US_TNPR_TXNPTR_Msk (0xffffffffu << US_TNPR_TXNPTR_Pos) /**< \brief (US_TNPR) Transmit Next Pointer */\r
+#define US_TNPR_TXNPTR(value) ((US_TNPR_TXNPTR_Msk & ((value) << US_TNPR_TXNPTR_Pos)))\r
+/* -------- US_TNCR : (USART Offset: 0x11C) Transmit Next Counter Register -------- */\r
+#define US_TNCR_TXNCTR_Pos 0\r
+#define US_TNCR_TXNCTR_Msk (0xffffu << US_TNCR_TXNCTR_Pos) /**< \brief (US_TNCR) Transmit Counter Next */\r
+#define US_TNCR_TXNCTR(value) ((US_TNCR_TXNCTR_Msk & ((value) << US_TNCR_TXNCTR_Pos)))\r
+/* -------- US_PTCR : (USART Offset: 0x120) Transfer Control Register -------- */\r
+#define US_PTCR_RXTEN (0x1u << 0) /**< \brief (US_PTCR) Receiver Transfer Enable */\r
+#define US_PTCR_RXTDIS (0x1u << 1) /**< \brief (US_PTCR) Receiver Transfer Disable */\r
+#define US_PTCR_TXTEN (0x1u << 8) /**< \brief (US_PTCR) Transmitter Transfer Enable */\r
+#define US_PTCR_TXTDIS (0x1u << 9) /**< \brief (US_PTCR) Transmitter Transfer Disable */\r
+/* -------- US_PTSR : (USART Offset: 0x124) Transfer Status Register -------- */\r
+#define US_PTSR_RXTEN (0x1u << 0) /**< \brief (US_PTSR) Receiver Transfer Enable */\r
+#define US_PTSR_TXTEN (0x1u << 8) /**< \brief (US_PTSR) Transmitter Transfer Enable */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM4E_USART_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4E_WDT_COMPONENT_\r
+#define _SAM4E_WDT_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Watchdog Timer */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM4E_WDT Watchdog Timer */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Wdt hardware registers */\r
+typedef struct {\r
+ WoReg WDT_CR; /**< \brief (Wdt Offset: 0x00) Control Register */\r
+ RwReg WDT_MR; /**< \brief (Wdt Offset: 0x04) Mode Register */\r
+ RoReg WDT_SR; /**< \brief (Wdt Offset: 0x08) Status Register */\r
+} Wdt;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- WDT_CR : (WDT Offset: 0x00) Control Register -------- */\r
+#define WDT_CR_WDRSTT (0x1u << 0) /**< \brief (WDT_CR) Watchdog Restart */\r
+#define WDT_CR_KEY_Pos 24\r
+#define WDT_CR_KEY_Msk (0xffu << WDT_CR_KEY_Pos) /**< \brief (WDT_CR) Password */\r
+#define WDT_CR_KEY(value) ((WDT_CR_KEY_Msk & ((value) << WDT_CR_KEY_Pos)))\r
+/* -------- WDT_MR : (WDT Offset: 0x04) Mode Register -------- */\r
+#define WDT_MR_WDV_Pos 0\r
+#define WDT_MR_WDV_Msk (0xfffu << WDT_MR_WDV_Pos) /**< \brief (WDT_MR) Watchdog Counter Value */\r
+#define WDT_MR_WDV(value) ((WDT_MR_WDV_Msk & ((value) << WDT_MR_WDV_Pos)))\r
+#define WDT_MR_WDFIEN (0x1u << 12) /**< \brief (WDT_MR) Watchdog Fault Interrupt Enable */\r
+#define WDT_MR_WDRSTEN (0x1u << 13) /**< \brief (WDT_MR) Watchdog Reset Enable */\r
+#define WDT_MR_WDRPROC (0x1u << 14) /**< \brief (WDT_MR) Watchdog Reset Processor */\r
+#define WDT_MR_WDDIS (0x1u << 15) /**< \brief (WDT_MR) Watchdog Disable */\r
+#define WDT_MR_WDD_Pos 16\r
+#define WDT_MR_WDD_Msk (0xfffu << WDT_MR_WDD_Pos) /**< \brief (WDT_MR) Watchdog Delta Value */\r
+#define WDT_MR_WDD(value) ((WDT_MR_WDD_Msk & ((value) << WDT_MR_WDD_Pos)))\r
+#define WDT_MR_WDDBGHLT (0x1u << 28) /**< \brief (WDT_MR) Watchdog Debug Halt */\r
+#define WDT_MR_WDIDLEHLT (0x1u << 29) /**< \brief (WDT_MR) Watchdog Idle Halt */\r
+/* -------- WDT_SR : (WDT Offset: 0x08) Status Register -------- */\r
+#define WDT_SR_WDUNF (0x1u << 0) /**< \brief (WDT_SR) Watchdog Underflow */\r
+#define WDT_SR_WDERR (0x1u << 1) /**< \brief (WDT_SR) Watchdog Error */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM4E_WDT_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4E_ACC_INSTANCE_\r
+#define _SAM4E_ACC_INSTANCE_\r
+\r
+/* ========== Register definition for ACC peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_ACC_CR (0x400BC000U) /**< \brief (ACC) Control Register */\r
+#define REG_ACC_MR (0x400BC004U) /**< \brief (ACC) Mode Register */\r
+#define REG_ACC_IER (0x400BC024U) /**< \brief (ACC) Interrupt Enable Register */\r
+#define REG_ACC_IDR (0x400BC028U) /**< \brief (ACC) Interrupt Disable Register */\r
+#define REG_ACC_IMR (0x400BC02CU) /**< \brief (ACC) Interrupt Mask Register */\r
+#define REG_ACC_ISR (0x400BC030U) /**< \brief (ACC) Interrupt Status Register */\r
+#define REG_ACC_ACR (0x400BC094U) /**< \brief (ACC) Analog Control Register */\r
+#define REG_ACC_WPMR (0x400BC0E4U) /**< \brief (ACC) Write Protect Mode Register */\r
+#define REG_ACC_WPSR (0x400BC0E8U) /**< \brief (ACC) Write Protect Status Register */\r
+#else\r
+#define REG_ACC_CR (*(WoReg*)0x400BC000U) /**< \brief (ACC) Control Register */\r
+#define REG_ACC_MR (*(RwReg*)0x400BC004U) /**< \brief (ACC) Mode Register */\r
+#define REG_ACC_IER (*(WoReg*)0x400BC024U) /**< \brief (ACC) Interrupt Enable Register */\r
+#define REG_ACC_IDR (*(WoReg*)0x400BC028U) /**< \brief (ACC) Interrupt Disable Register */\r
+#define REG_ACC_IMR (*(RoReg*)0x400BC02CU) /**< \brief (ACC) Interrupt Mask Register */\r
+#define REG_ACC_ISR (*(RoReg*)0x400BC030U) /**< \brief (ACC) Interrupt Status Register */\r
+#define REG_ACC_ACR (*(RwReg*)0x400BC094U) /**< \brief (ACC) Analog Control Register */\r
+#define REG_ACC_WPMR (*(RwReg*)0x400BC0E4U) /**< \brief (ACC) Write Protect Mode Register */\r
+#define REG_ACC_WPSR (*(RoReg*)0x400BC0E8U) /**< \brief (ACC) Write Protect Status Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM4E_ACC_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4E_AES_INSTANCE_\r
+#define _SAM4E_AES_INSTANCE_\r
+\r
+/* ========== Register definition for AES peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_AES_CR (0x40004000U) /**< \brief (AES) Control Register */\r
+#define REG_AES_MR (0x40004004U) /**< \brief (AES) Mode Register */\r
+#define REG_AES_IER (0x40004010U) /**< \brief (AES) Interrupt Enable Register */\r
+#define REG_AES_IDR (0x40004014U) /**< \brief (AES) Interrupt Disable Register */\r
+#define REG_AES_IMR (0x40004018U) /**< \brief (AES) Interrupt Mask Register */\r
+#define REG_AES_ISR (0x4000401CU) /**< \brief (AES) Interrupt Status Register */\r
+#define REG_AES_KEYWR (0x40004020U) /**< \brief (AES) Key Word Register */\r
+#define REG_AES_IDATAR (0x40004040U) /**< \brief (AES) Input Data Register */\r
+#define REG_AES_ODATAR (0x40004050U) /**< \brief (AES) Output Data Register */\r
+#define REG_AES_IVR (0x40004060U) /**< \brief (AES) Initialization Vector Register */\r
+#else\r
+#define REG_AES_CR (*(WoReg*)0x40004000U) /**< \brief (AES) Control Register */\r
+#define REG_AES_MR (*(RwReg*)0x40004004U) /**< \brief (AES) Mode Register */\r
+#define REG_AES_IER (*(WoReg*)0x40004010U) /**< \brief (AES) Interrupt Enable Register */\r
+#define REG_AES_IDR (*(WoReg*)0x40004014U) /**< \brief (AES) Interrupt Disable Register */\r
+#define REG_AES_IMR (*(RoReg*)0x40004018U) /**< \brief (AES) Interrupt Mask Register */\r
+#define REG_AES_ISR (*(RoReg*)0x4000401CU) /**< \brief (AES) Interrupt Status Register */\r
+#define REG_AES_KEYWR (*(WoReg*)0x40004020U) /**< \brief (AES) Key Word Register */\r
+#define REG_AES_IDATAR (*(WoReg*)0x40004040U) /**< \brief (AES) Input Data Register */\r
+#define REG_AES_ODATAR (*(RoReg*)0x40004050U) /**< \brief (AES) Output Data Register */\r
+#define REG_AES_IVR (*(WoReg*)0x40004060U) /**< \brief (AES) Initialization Vector Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM4E_AES_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4E_AFEC0_INSTANCE_\r
+#define _SAM4E_AFEC0_INSTANCE_\r
+\r
+/* ========== Register definition for AFEC0 peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_AFEC0_CR (0x400B0000U) /**< \brief (AFEC0) Control Register */\r
+#define REG_AFEC0_MR (0x400B0004U) /**< \brief (AFEC0) Mode Register */\r
+#define REG_AFEC0_EMR (0x400B0008U) /**< \brief (AFEC0) Extended Mode Register */\r
+#define REG_AFEC0_SEQ1R (0x400B000CU) /**< \brief (AFEC0) Channel Sequence 1 Register */\r
+#define REG_AFEC0_SEQ2R (0x400B0010U) /**< \brief (AFEC0) Channel Sequence 2 Register */\r
+#define REG_AFEC0_CHER (0x400B0014U) /**< \brief (AFEC0) Channel Enable Register */\r
+#define REG_AFEC0_CHDR (0x400B0018U) /**< \brief (AFEC0) Channel Disable Register */\r
+#define REG_AFEC0_CHSR (0x400B001CU) /**< \brief (AFEC0) Channel Status Register */\r
+#define REG_AFEC0_LCDR (0x400B0020U) /**< \brief (AFEC0) Last Converted Data Register */\r
+#define REG_AFEC0_IER (0x400B0024U) /**< \brief (AFEC0) Interrupt Enable Register */\r
+#define REG_AFEC0_IDR (0x400B0028U) /**< \brief (AFEC0) Interrupt Disable Register */\r
+#define REG_AFEC0_IMR (0x400B002CU) /**< \brief (AFEC0) Interrupt Mask Register */\r
+#define REG_AFEC0_ISR (0x400B0030U) /**< \brief (AFEC0) Interrupt Status Register */\r
+#define REG_AFEC0_OVER (0x400B004CU) /**< \brief (AFEC0) Overrun Status Register */\r
+#define REG_AFEC0_CWR (0x400B0050U) /**< \brief (AFEC0) Compare Window Register */\r
+#define REG_AFEC0_CGR (0x400B0054U) /**< \brief (AFEC0) Channel Gain Register */\r
+#define REG_AFEC0_CDOR (0x400B005CU) /**< \brief (AFEC0) Channel Calibration DC Offset Register */\r
+#define REG_AFEC0_DIFFR (0x400B0060U) /**< \brief (AFEC0) Channel Differential Register */\r
+#define REG_AFEC0_CSELR (0x400B0064U) /**< \brief (AFEC0) Channel Register Selection */\r
+#define REG_AFEC0_CDR (0x400B0068U) /**< \brief (AFEC0) Channel Data Register */\r
+#define REG_AFEC0_COCR (0x400B006CU) /**< \brief (AFEC0) Channel Offset Compensation Register */\r
+#define REG_AFEC0_TEMPMR (0x400B0070U) /**< \brief (AFEC0) Temperature Sensor Mode Register */\r
+#define REG_AFEC0_TEMPCWR (0x400B0074U) /**< \brief (AFEC0) Temperature Compare Window Register */\r
+#define REG_AFEC0_ACR (0x400B0094U) /**< \brief (AFEC0) Analog Control Register */\r
+#define REG_AFEC0_WPMR (0x400B00E4U) /**< \brief (AFEC0) Write Protect Mode Register */\r
+#define REG_AFEC0_WPSR (0x400B00E8U) /**< \brief (AFEC0) Write Protect Status Register */\r
+#define REG_AFEC0_RPR (0x400B0100U) /**< \brief (AFEC0) Receive Pointer Register */\r
+#define REG_AFEC0_RCR (0x400B0104U) /**< \brief (AFEC0) Receive Counter Register */\r
+#define REG_AFEC0_RNPR (0x400B0110U) /**< \brief (AFEC0) Receive Next Pointer Register */\r
+#define REG_AFEC0_RNCR (0x400B0114U) /**< \brief (AFEC0) Receive Next Counter Register */\r
+#define REG_AFEC0_PTCR (0x400B0120U) /**< \brief (AFEC0) Transfer Control Register */\r
+#define REG_AFEC0_PTSR (0x400B0124U) /**< \brief (AFEC0) Transfer Status Register */\r
+#else\r
+#define REG_AFEC0_CR (*(WoReg*)0x400B0000U) /**< \brief (AFEC0) Control Register */\r
+#define REG_AFEC0_MR (*(RwReg*)0x400B0004U) /**< \brief (AFEC0) Mode Register */\r
+#define REG_AFEC0_EMR (*(RwReg*)0x400B0008U) /**< \brief (AFEC0) Extended Mode Register */\r
+#define REG_AFEC0_SEQ1R (*(RwReg*)0x400B000CU) /**< \brief (AFEC0) Channel Sequence 1 Register */\r
+#define REG_AFEC0_SEQ2R (*(RwReg*)0x400B0010U) /**< \brief (AFEC0) Channel Sequence 2 Register */\r
+#define REG_AFEC0_CHER (*(WoReg*)0x400B0014U) /**< \brief (AFEC0) Channel Enable Register */\r
+#define REG_AFEC0_CHDR (*(WoReg*)0x400B0018U) /**< \brief (AFEC0) Channel Disable Register */\r
+#define REG_AFEC0_CHSR (*(RoReg*)0x400B001CU) /**< \brief (AFEC0) Channel Status Register */\r
+#define REG_AFEC0_LCDR (*(RoReg*)0x400B0020U) /**< \brief (AFEC0) Last Converted Data Register */\r
+#define REG_AFEC0_IER (*(WoReg*)0x400B0024U) /**< \brief (AFEC0) Interrupt Enable Register */\r
+#define REG_AFEC0_IDR (*(WoReg*)0x400B0028U) /**< \brief (AFEC0) Interrupt Disable Register */\r
+#define REG_AFEC0_IMR (*(RoReg*)0x400B002CU) /**< \brief (AFEC0) Interrupt Mask Register */\r
+#define REG_AFEC0_ISR (*(RoReg*)0x400B0030U) /**< \brief (AFEC0) Interrupt Status Register */\r
+#define REG_AFEC0_OVER (*(RoReg*)0x400B004CU) /**< \brief (AFEC0) Overrun Status Register */\r
+#define REG_AFEC0_CWR (*(RwReg*)0x400B0050U) /**< \brief (AFEC0) Compare Window Register */\r
+#define REG_AFEC0_CGR (*(RwReg*)0x400B0054U) /**< \brief (AFEC0) Channel Gain Register */\r
+#define REG_AFEC0_CDOR (*(RwReg*)0x400B005CU) /**< \brief (AFEC0) Channel Calibration DC Offset Register */\r
+#define REG_AFEC0_DIFFR (*(RwReg*)0x400B0060U) /**< \brief (AFEC0) Channel Differential Register */\r
+#define REG_AFEC0_CSELR (*(RwReg*)0x400B0064U) /**< \brief (AFEC0) Channel Register Selection */\r
+#define REG_AFEC0_CDR (*(RoReg*)0x400B0068U) /**< \brief (AFEC0) Channel Data Register */\r
+#define REG_AFEC0_COCR (*(RwReg*)0x400B006CU) /**< \brief (AFEC0) Channel Offset Compensation Register */\r
+#define REG_AFEC0_TEMPMR (*(RwReg*)0x400B0070U) /**< \brief (AFEC0) Temperature Sensor Mode Register */\r
+#define REG_AFEC0_TEMPCWR (*(RwReg*)0x400B0074U) /**< \brief (AFEC0) Temperature Compare Window Register */\r
+#define REG_AFEC0_ACR (*(RwReg*)0x400B0094U) /**< \brief (AFEC0) Analog Control Register */\r
+#define REG_AFEC0_WPMR (*(RwReg*)0x400B00E4U) /**< \brief (AFEC0) Write Protect Mode Register */\r
+#define REG_AFEC0_WPSR (*(RoReg*)0x400B00E8U) /**< \brief (AFEC0) Write Protect Status Register */\r
+#define REG_AFEC0_RPR (*(RwReg*)0x400B0100U) /**< \brief (AFEC0) Receive Pointer Register */\r
+#define REG_AFEC0_RCR (*(RwReg*)0x400B0104U) /**< \brief (AFEC0) Receive Counter Register */\r
+#define REG_AFEC0_RNPR (*(RwReg*)0x400B0110U) /**< \brief (AFEC0) Receive Next Pointer Register */\r
+#define REG_AFEC0_RNCR (*(RwReg*)0x400B0114U) /**< \brief (AFEC0) Receive Next Counter Register */\r
+#define REG_AFEC0_PTCR (*(WoReg*)0x400B0120U) /**< \brief (AFEC0) Transfer Control Register */\r
+#define REG_AFEC0_PTSR (*(RoReg*)0x400B0124U) /**< \brief (AFEC0) Transfer Status Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM4E_AFEC0_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4E_AFEC1_INSTANCE_\r
+#define _SAM4E_AFEC1_INSTANCE_\r
+\r
+/* ========== Register definition for AFEC1 peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_AFEC1_CR (0x400B4000U) /**< \brief (AFEC1) Control Register */\r
+#define REG_AFEC1_MR (0x400B4004U) /**< \brief (AFEC1) Mode Register */\r
+#define REG_AFEC1_EMR (0x400B4008U) /**< \brief (AFEC1) Extended Mode Register */\r
+#define REG_AFEC1_SEQ1R (0x400B400CU) /**< \brief (AFEC1) Channel Sequence 1 Register */\r
+#define REG_AFEC1_SEQ2R (0x400B4010U) /**< \brief (AFEC1) Channel Sequence 2 Register */\r
+#define REG_AFEC1_CHER (0x400B4014U) /**< \brief (AFEC1) Channel Enable Register */\r
+#define REG_AFEC1_CHDR (0x400B4018U) /**< \brief (AFEC1) Channel Disable Register */\r
+#define REG_AFEC1_CHSR (0x400B401CU) /**< \brief (AFEC1) Channel Status Register */\r
+#define REG_AFEC1_LCDR (0x400B4020U) /**< \brief (AFEC1) Last Converted Data Register */\r
+#define REG_AFEC1_IER (0x400B4024U) /**< \brief (AFEC1) Interrupt Enable Register */\r
+#define REG_AFEC1_IDR (0x400B4028U) /**< \brief (AFEC1) Interrupt Disable Register */\r
+#define REG_AFEC1_IMR (0x400B402CU) /**< \brief (AFEC1) Interrupt Mask Register */\r
+#define REG_AFEC1_ISR (0x400B4030U) /**< \brief (AFEC1) Interrupt Status Register */\r
+#define REG_AFEC1_OVER (0x400B404CU) /**< \brief (AFEC1) Overrun Status Register */\r
+#define REG_AFEC1_CWR (0x400B4050U) /**< \brief (AFEC1) Compare Window Register */\r
+#define REG_AFEC1_CGR (0x400B4054U) /**< \brief (AFEC1) Channel Gain Register */\r
+#define REG_AFEC1_CDOR (0x400B405CU) /**< \brief (AFEC1) Channel Calibration DC Offset Register */\r
+#define REG_AFEC1_DIFFR (0x400B4060U) /**< \brief (AFEC1) Channel Differential Register */\r
+#define REG_AFEC1_CSELR (0x400B4064U) /**< \brief (AFEC1) Channel Register Selection */\r
+#define REG_AFEC1_CDR (0x400B4068U) /**< \brief (AFEC1) Channel Data Register */\r
+#define REG_AFEC1_COCR (0x400B406CU) /**< \brief (AFEC1) Channel Offset Compensation Register */\r
+#define REG_AFEC1_TEMPMR (0x400B4070U) /**< \brief (AFEC1) Temperature Sensor Mode Register */\r
+#define REG_AFEC1_TEMPCWR (0x400B4074U) /**< \brief (AFEC1) Temperature Compare Window Register */\r
+#define REG_AFEC1_ACR (0x400B4094U) /**< \brief (AFEC1) Analog Control Register */\r
+#define REG_AFEC1_WPMR (0x400B40E4U) /**< \brief (AFEC1) Write Protect Mode Register */\r
+#define REG_AFEC1_WPSR (0x400B40E8U) /**< \brief (AFEC1) Write Protect Status Register */\r
+#define REG_AFEC1_RPR (0x400B4100U) /**< \brief (AFEC1) Receive Pointer Register */\r
+#define REG_AFEC1_RCR (0x400B4104U) /**< \brief (AFEC1) Receive Counter Register */\r
+#define REG_AFEC1_RNPR (0x400B4110U) /**< \brief (AFEC1) Receive Next Pointer Register */\r
+#define REG_AFEC1_RNCR (0x400B4114U) /**< \brief (AFEC1) Receive Next Counter Register */\r
+#define REG_AFEC1_PTCR (0x400B4120U) /**< \brief (AFEC1) Transfer Control Register */\r
+#define REG_AFEC1_PTSR (0x400B4124U) /**< \brief (AFEC1) Transfer Status Register */\r
+#else\r
+#define REG_AFEC1_CR (*(WoReg*)0x400B4000U) /**< \brief (AFEC1) Control Register */\r
+#define REG_AFEC1_MR (*(RwReg*)0x400B4004U) /**< \brief (AFEC1) Mode Register */\r
+#define REG_AFEC1_EMR (*(RwReg*)0x400B4008U) /**< \brief (AFEC1) Extended Mode Register */\r
+#define REG_AFEC1_SEQ1R (*(RwReg*)0x400B400CU) /**< \brief (AFEC1) Channel Sequence 1 Register */\r
+#define REG_AFEC1_SEQ2R (*(RwReg*)0x400B4010U) /**< \brief (AFEC1) Channel Sequence 2 Register */\r
+#define REG_AFEC1_CHER (*(WoReg*)0x400B4014U) /**< \brief (AFEC1) Channel Enable Register */\r
+#define REG_AFEC1_CHDR (*(WoReg*)0x400B4018U) /**< \brief (AFEC1) Channel Disable Register */\r
+#define REG_AFEC1_CHSR (*(RoReg*)0x400B401CU) /**< \brief (AFEC1) Channel Status Register */\r
+#define REG_AFEC1_LCDR (*(RoReg*)0x400B4020U) /**< \brief (AFEC1) Last Converted Data Register */\r
+#define REG_AFEC1_IER (*(WoReg*)0x400B4024U) /**< \brief (AFEC1) Interrupt Enable Register */\r
+#define REG_AFEC1_IDR (*(WoReg*)0x400B4028U) /**< \brief (AFEC1) Interrupt Disable Register */\r
+#define REG_AFEC1_IMR (*(RoReg*)0x400B402CU) /**< \brief (AFEC1) Interrupt Mask Register */\r
+#define REG_AFEC1_ISR (*(RoReg*)0x400B4030U) /**< \brief (AFEC1) Interrupt Status Register */\r
+#define REG_AFEC1_OVER (*(RoReg*)0x400B404CU) /**< \brief (AFEC1) Overrun Status Register */\r
+#define REG_AFEC1_CWR (*(RwReg*)0x400B4050U) /**< \brief (AFEC1) Compare Window Register */\r
+#define REG_AFEC1_CGR (*(RwReg*)0x400B4054U) /**< \brief (AFEC1) Channel Gain Register */\r
+#define REG_AFEC1_CDOR (*(RwReg*)0x400B405CU) /**< \brief (AFEC1) Channel Calibration DC Offset Register */\r
+#define REG_AFEC1_DIFFR (*(RwReg*)0x400B4060U) /**< \brief (AFEC1) Channel Differential Register */\r
+#define REG_AFEC1_CSELR (*(RwReg*)0x400B4064U) /**< \brief (AFEC1) Channel Register Selection */\r
+#define REG_AFEC1_CDR (*(RoReg*)0x400B4068U) /**< \brief (AFEC1) Channel Data Register */\r
+#define REG_AFEC1_COCR (*(RwReg*)0x400B406CU) /**< \brief (AFEC1) Channel Offset Compensation Register */\r
+#define REG_AFEC1_TEMPMR (*(RwReg*)0x400B4070U) /**< \brief (AFEC1) Temperature Sensor Mode Register */\r
+#define REG_AFEC1_TEMPCWR (*(RwReg*)0x400B4074U) /**< \brief (AFEC1) Temperature Compare Window Register */\r
+#define REG_AFEC1_ACR (*(RwReg*)0x400B4094U) /**< \brief (AFEC1) Analog Control Register */\r
+#define REG_AFEC1_WPMR (*(RwReg*)0x400B40E4U) /**< \brief (AFEC1) Write Protect Mode Register */\r
+#define REG_AFEC1_WPSR (*(RoReg*)0x400B40E8U) /**< \brief (AFEC1) Write Protect Status Register */\r
+#define REG_AFEC1_RPR (*(RwReg*)0x400B4100U) /**< \brief (AFEC1) Receive Pointer Register */\r
+#define REG_AFEC1_RCR (*(RwReg*)0x400B4104U) /**< \brief (AFEC1) Receive Counter Register */\r
+#define REG_AFEC1_RNPR (*(RwReg*)0x400B4110U) /**< \brief (AFEC1) Receive Next Pointer Register */\r
+#define REG_AFEC1_RNCR (*(RwReg*)0x400B4114U) /**< \brief (AFEC1) Receive Next Counter Register */\r
+#define REG_AFEC1_PTCR (*(WoReg*)0x400B4120U) /**< \brief (AFEC1) Transfer Control Register */\r
+#define REG_AFEC1_PTSR (*(RoReg*)0x400B4124U) /**< \brief (AFEC1) Transfer Status Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM4E_AFEC1_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4E_CAN0_INSTANCE_\r
+#define _SAM4E_CAN0_INSTANCE_\r
+\r
+/* ========== Register definition for CAN0 peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_CAN0_MR (0x40010000U) /**< \brief (CAN0) Mode Register */\r
+#define REG_CAN0_IER (0x40010004U) /**< \brief (CAN0) Interrupt Enable Register */\r
+#define REG_CAN0_IDR (0x40010008U) /**< \brief (CAN0) Interrupt Disable Register */\r
+#define REG_CAN0_IMR (0x4001000CU) /**< \brief (CAN0) Interrupt Mask Register */\r
+#define REG_CAN0_SR (0x40010010U) /**< \brief (CAN0) Status Register */\r
+#define REG_CAN0_BR (0x40010014U) /**< \brief (CAN0) Baudrate Register */\r
+#define REG_CAN0_TIM (0x40010018U) /**< \brief (CAN0) Timer Register */\r
+#define REG_CAN0_TIMESTP (0x4001001CU) /**< \brief (CAN0) Timestamp Register */\r
+#define REG_CAN0_ECR (0x40010020U) /**< \brief (CAN0) Error Counter Register */\r
+#define REG_CAN0_TCR (0x40010024U) /**< \brief (CAN0) Transfer Command Register */\r
+#define REG_CAN0_ACR (0x40010028U) /**< \brief (CAN0) Abort Command Register */\r
+#define REG_CAN0_WPMR (0x400100E4U) /**< \brief (CAN0) Write Protect Mode Register */\r
+#define REG_CAN0_WPSR (0x400100E8U) /**< \brief (CAN0) Write Protect Status Register */\r
+#define REG_CAN0_MMR0 (0x40010200U) /**< \brief (CAN0) Mailbox Mode Register (MB = 0) */\r
+#define REG_CAN0_MAM0 (0x40010204U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 0) */\r
+#define REG_CAN0_MID0 (0x40010208U) /**< \brief (CAN0) Mailbox ID Register (MB = 0) */\r
+#define REG_CAN0_MFID0 (0x4001020CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 0) */\r
+#define REG_CAN0_MSR0 (0x40010210U) /**< \brief (CAN0) Mailbox Status Register (MB = 0) */\r
+#define REG_CAN0_MDL0 (0x40010214U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 0) */\r
+#define REG_CAN0_MDH0 (0x40010218U) /**< \brief (CAN0) Mailbox Data High Register (MB = 0) */\r
+#define REG_CAN0_MCR0 (0x4001021CU) /**< \brief (CAN0) Mailbox Control Register (MB = 0) */\r
+#define REG_CAN0_MMR1 (0x40010220U) /**< \brief (CAN0) Mailbox Mode Register (MB = 1) */\r
+#define REG_CAN0_MAM1 (0x40010224U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 1) */\r
+#define REG_CAN0_MID1 (0x40010228U) /**< \brief (CAN0) Mailbox ID Register (MB = 1) */\r
+#define REG_CAN0_MFID1 (0x4001022CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 1) */\r
+#define REG_CAN0_MSR1 (0x40010230U) /**< \brief (CAN0) Mailbox Status Register (MB = 1) */\r
+#define REG_CAN0_MDL1 (0x40010234U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 1) */\r
+#define REG_CAN0_MDH1 (0x40010238U) /**< \brief (CAN0) Mailbox Data High Register (MB = 1) */\r
+#define REG_CAN0_MCR1 (0x4001023CU) /**< \brief (CAN0) Mailbox Control Register (MB = 1) */\r
+#define REG_CAN0_MMR2 (0x40010240U) /**< \brief (CAN0) Mailbox Mode Register (MB = 2) */\r
+#define REG_CAN0_MAM2 (0x40010244U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 2) */\r
+#define REG_CAN0_MID2 (0x40010248U) /**< \brief (CAN0) Mailbox ID Register (MB = 2) */\r
+#define REG_CAN0_MFID2 (0x4001024CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 2) */\r
+#define REG_CAN0_MSR2 (0x40010250U) /**< \brief (CAN0) Mailbox Status Register (MB = 2) */\r
+#define REG_CAN0_MDL2 (0x40010254U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 2) */\r
+#define REG_CAN0_MDH2 (0x40010258U) /**< \brief (CAN0) Mailbox Data High Register (MB = 2) */\r
+#define REG_CAN0_MCR2 (0x4001025CU) /**< \brief (CAN0) Mailbox Control Register (MB = 2) */\r
+#define REG_CAN0_MMR3 (0x40010260U) /**< \brief (CAN0) Mailbox Mode Register (MB = 3) */\r
+#define REG_CAN0_MAM3 (0x40010264U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 3) */\r
+#define REG_CAN0_MID3 (0x40010268U) /**< \brief (CAN0) Mailbox ID Register (MB = 3) */\r
+#define REG_CAN0_MFID3 (0x4001026CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 3) */\r
+#define REG_CAN0_MSR3 (0x40010270U) /**< \brief (CAN0) Mailbox Status Register (MB = 3) */\r
+#define REG_CAN0_MDL3 (0x40010274U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 3) */\r
+#define REG_CAN0_MDH3 (0x40010278U) /**< \brief (CAN0) Mailbox Data High Register (MB = 3) */\r
+#define REG_CAN0_MCR3 (0x4001027CU) /**< \brief (CAN0) Mailbox Control Register (MB = 3) */\r
+#define REG_CAN0_MMR4 (0x40010280U) /**< \brief (CAN0) Mailbox Mode Register (MB = 4) */\r
+#define REG_CAN0_MAM4 (0x40010284U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 4) */\r
+#define REG_CAN0_MID4 (0x40010288U) /**< \brief (CAN0) Mailbox ID Register (MB = 4) */\r
+#define REG_CAN0_MFID4 (0x4001028CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 4) */\r
+#define REG_CAN0_MSR4 (0x40010290U) /**< \brief (CAN0) Mailbox Status Register (MB = 4) */\r
+#define REG_CAN0_MDL4 (0x40010294U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 4) */\r
+#define REG_CAN0_MDH4 (0x40010298U) /**< \brief (CAN0) Mailbox Data High Register (MB = 4) */\r
+#define REG_CAN0_MCR4 (0x4001029CU) /**< \brief (CAN0) Mailbox Control Register (MB = 4) */\r
+#define REG_CAN0_MMR5 (0x400102A0U) /**< \brief (CAN0) Mailbox Mode Register (MB = 5) */\r
+#define REG_CAN0_MAM5 (0x400102A4U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 5) */\r
+#define REG_CAN0_MID5 (0x400102A8U) /**< \brief (CAN0) Mailbox ID Register (MB = 5) */\r
+#define REG_CAN0_MFID5 (0x400102ACU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 5) */\r
+#define REG_CAN0_MSR5 (0x400102B0U) /**< \brief (CAN0) Mailbox Status Register (MB = 5) */\r
+#define REG_CAN0_MDL5 (0x400102B4U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 5) */\r
+#define REG_CAN0_MDH5 (0x400102B8U) /**< \brief (CAN0) Mailbox Data High Register (MB = 5) */\r
+#define REG_CAN0_MCR5 (0x400102BCU) /**< \brief (CAN0) Mailbox Control Register (MB = 5) */\r
+#define REG_CAN0_MMR6 (0x400102C0U) /**< \brief (CAN0) Mailbox Mode Register (MB = 6) */\r
+#define REG_CAN0_MAM6 (0x400102C4U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 6) */\r
+#define REG_CAN0_MID6 (0x400102C8U) /**< \brief (CAN0) Mailbox ID Register (MB = 6) */\r
+#define REG_CAN0_MFID6 (0x400102CCU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 6) */\r
+#define REG_CAN0_MSR6 (0x400102D0U) /**< \brief (CAN0) Mailbox Status Register (MB = 6) */\r
+#define REG_CAN0_MDL6 (0x400102D4U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 6) */\r
+#define REG_CAN0_MDH6 (0x400102D8U) /**< \brief (CAN0) Mailbox Data High Register (MB = 6) */\r
+#define REG_CAN0_MCR6 (0x400102DCU) /**< \brief (CAN0) Mailbox Control Register (MB = 6) */\r
+#define REG_CAN0_MMR7 (0x400102E0U) /**< \brief (CAN0) Mailbox Mode Register (MB = 7) */\r
+#define REG_CAN0_MAM7 (0x400102E4U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 7) */\r
+#define REG_CAN0_MID7 (0x400102E8U) /**< \brief (CAN0) Mailbox ID Register (MB = 7) */\r
+#define REG_CAN0_MFID7 (0x400102ECU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 7) */\r
+#define REG_CAN0_MSR7 (0x400102F0U) /**< \brief (CAN0) Mailbox Status Register (MB = 7) */\r
+#define REG_CAN0_MDL7 (0x400102F4U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 7) */\r
+#define REG_CAN0_MDH7 (0x400102F8U) /**< \brief (CAN0) Mailbox Data High Register (MB = 7) */\r
+#define REG_CAN0_MCR7 (0x400102FCU) /**< \brief (CAN0) Mailbox Control Register (MB = 7) */\r
+#else\r
+#define REG_CAN0_MR (*(RwReg*)0x40010000U) /**< \brief (CAN0) Mode Register */\r
+#define REG_CAN0_IER (*(WoReg*)0x40010004U) /**< \brief (CAN0) Interrupt Enable Register */\r
+#define REG_CAN0_IDR (*(WoReg*)0x40010008U) /**< \brief (CAN0) Interrupt Disable Register */\r
+#define REG_CAN0_IMR (*(RoReg*)0x4001000CU) /**< \brief (CAN0) Interrupt Mask Register */\r
+#define REG_CAN0_SR (*(RoReg*)0x40010010U) /**< \brief (CAN0) Status Register */\r
+#define REG_CAN0_BR (*(RwReg*)0x40010014U) /**< \brief (CAN0) Baudrate Register */\r
+#define REG_CAN0_TIM (*(RoReg*)0x40010018U) /**< \brief (CAN0) Timer Register */\r
+#define REG_CAN0_TIMESTP (*(RoReg*)0x4001001CU) /**< \brief (CAN0) Timestamp Register */\r
+#define REG_CAN0_ECR (*(RoReg*)0x40010020U) /**< \brief (CAN0) Error Counter Register */\r
+#define REG_CAN0_TCR (*(WoReg*)0x40010024U) /**< \brief (CAN0) Transfer Command Register */\r
+#define REG_CAN0_ACR (*(WoReg*)0x40010028U) /**< \brief (CAN0) Abort Command Register */\r
+#define REG_CAN0_WPMR (*(RwReg*)0x400100E4U) /**< \brief (CAN0) Write Protect Mode Register */\r
+#define REG_CAN0_WPSR (*(RoReg*)0x400100E8U) /**< \brief (CAN0) Write Protect Status Register */\r
+#define REG_CAN0_MMR0 (*(RwReg*)0x40010200U) /**< \brief (CAN0) Mailbox Mode Register (MB = 0) */\r
+#define REG_CAN0_MAM0 (*(RwReg*)0x40010204U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 0) */\r
+#define REG_CAN0_MID0 (*(RwReg*)0x40010208U) /**< \brief (CAN0) Mailbox ID Register (MB = 0) */\r
+#define REG_CAN0_MFID0 (*(RoReg*)0x4001020CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 0) */\r
+#define REG_CAN0_MSR0 (*(RoReg*)0x40010210U) /**< \brief (CAN0) Mailbox Status Register (MB = 0) */\r
+#define REG_CAN0_MDL0 (*(RwReg*)0x40010214U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 0) */\r
+#define REG_CAN0_MDH0 (*(RwReg*)0x40010218U) /**< \brief (CAN0) Mailbox Data High Register (MB = 0) */\r
+#define REG_CAN0_MCR0 (*(WoReg*)0x4001021CU) /**< \brief (CAN0) Mailbox Control Register (MB = 0) */\r
+#define REG_CAN0_MMR1 (*(RwReg*)0x40010220U) /**< \brief (CAN0) Mailbox Mode Register (MB = 1) */\r
+#define REG_CAN0_MAM1 (*(RwReg*)0x40010224U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 1) */\r
+#define REG_CAN0_MID1 (*(RwReg*)0x40010228U) /**< \brief (CAN0) Mailbox ID Register (MB = 1) */\r
+#define REG_CAN0_MFID1 (*(RoReg*)0x4001022CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 1) */\r
+#define REG_CAN0_MSR1 (*(RoReg*)0x40010230U) /**< \brief (CAN0) Mailbox Status Register (MB = 1) */\r
+#define REG_CAN0_MDL1 (*(RwReg*)0x40010234U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 1) */\r
+#define REG_CAN0_MDH1 (*(RwReg*)0x40010238U) /**< \brief (CAN0) Mailbox Data High Register (MB = 1) */\r
+#define REG_CAN0_MCR1 (*(WoReg*)0x4001023CU) /**< \brief (CAN0) Mailbox Control Register (MB = 1) */\r
+#define REG_CAN0_MMR2 (*(RwReg*)0x40010240U) /**< \brief (CAN0) Mailbox Mode Register (MB = 2) */\r
+#define REG_CAN0_MAM2 (*(RwReg*)0x40010244U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 2) */\r
+#define REG_CAN0_MID2 (*(RwReg*)0x40010248U) /**< \brief (CAN0) Mailbox ID Register (MB = 2) */\r
+#define REG_CAN0_MFID2 (*(RoReg*)0x4001024CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 2) */\r
+#define REG_CAN0_MSR2 (*(RoReg*)0x40010250U) /**< \brief (CAN0) Mailbox Status Register (MB = 2) */\r
+#define REG_CAN0_MDL2 (*(RwReg*)0x40010254U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 2) */\r
+#define REG_CAN0_MDH2 (*(RwReg*)0x40010258U) /**< \brief (CAN0) Mailbox Data High Register (MB = 2) */\r
+#define REG_CAN0_MCR2 (*(WoReg*)0x4001025CU) /**< \brief (CAN0) Mailbox Control Register (MB = 2) */\r
+#define REG_CAN0_MMR3 (*(RwReg*)0x40010260U) /**< \brief (CAN0) Mailbox Mode Register (MB = 3) */\r
+#define REG_CAN0_MAM3 (*(RwReg*)0x40010264U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 3) */\r
+#define REG_CAN0_MID3 (*(RwReg*)0x40010268U) /**< \brief (CAN0) Mailbox ID Register (MB = 3) */\r
+#define REG_CAN0_MFID3 (*(RoReg*)0x4001026CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 3) */\r
+#define REG_CAN0_MSR3 (*(RoReg*)0x40010270U) /**< \brief (CAN0) Mailbox Status Register (MB = 3) */\r
+#define REG_CAN0_MDL3 (*(RwReg*)0x40010274U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 3) */\r
+#define REG_CAN0_MDH3 (*(RwReg*)0x40010278U) /**< \brief (CAN0) Mailbox Data High Register (MB = 3) */\r
+#define REG_CAN0_MCR3 (*(WoReg*)0x4001027CU) /**< \brief (CAN0) Mailbox Control Register (MB = 3) */\r
+#define REG_CAN0_MMR4 (*(RwReg*)0x40010280U) /**< \brief (CAN0) Mailbox Mode Register (MB = 4) */\r
+#define REG_CAN0_MAM4 (*(RwReg*)0x40010284U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 4) */\r
+#define REG_CAN0_MID4 (*(RwReg*)0x40010288U) /**< \brief (CAN0) Mailbox ID Register (MB = 4) */\r
+#define REG_CAN0_MFID4 (*(RoReg*)0x4001028CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 4) */\r
+#define REG_CAN0_MSR4 (*(RoReg*)0x40010290U) /**< \brief (CAN0) Mailbox Status Register (MB = 4) */\r
+#define REG_CAN0_MDL4 (*(RwReg*)0x40010294U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 4) */\r
+#define REG_CAN0_MDH4 (*(RwReg*)0x40010298U) /**< \brief (CAN0) Mailbox Data High Register (MB = 4) */\r
+#define REG_CAN0_MCR4 (*(WoReg*)0x4001029CU) /**< \brief (CAN0) Mailbox Control Register (MB = 4) */\r
+#define REG_CAN0_MMR5 (*(RwReg*)0x400102A0U) /**< \brief (CAN0) Mailbox Mode Register (MB = 5) */\r
+#define REG_CAN0_MAM5 (*(RwReg*)0x400102A4U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 5) */\r
+#define REG_CAN0_MID5 (*(RwReg*)0x400102A8U) /**< \brief (CAN0) Mailbox ID Register (MB = 5) */\r
+#define REG_CAN0_MFID5 (*(RoReg*)0x400102ACU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 5) */\r
+#define REG_CAN0_MSR5 (*(RoReg*)0x400102B0U) /**< \brief (CAN0) Mailbox Status Register (MB = 5) */\r
+#define REG_CAN0_MDL5 (*(RwReg*)0x400102B4U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 5) */\r
+#define REG_CAN0_MDH5 (*(RwReg*)0x400102B8U) /**< \brief (CAN0) Mailbox Data High Register (MB = 5) */\r
+#define REG_CAN0_MCR5 (*(WoReg*)0x400102BCU) /**< \brief (CAN0) Mailbox Control Register (MB = 5) */\r
+#define REG_CAN0_MMR6 (*(RwReg*)0x400102C0U) /**< \brief (CAN0) Mailbox Mode Register (MB = 6) */\r
+#define REG_CAN0_MAM6 (*(RwReg*)0x400102C4U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 6) */\r
+#define REG_CAN0_MID6 (*(RwReg*)0x400102C8U) /**< \brief (CAN0) Mailbox ID Register (MB = 6) */\r
+#define REG_CAN0_MFID6 (*(RoReg*)0x400102CCU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 6) */\r
+#define REG_CAN0_MSR6 (*(RoReg*)0x400102D0U) /**< \brief (CAN0) Mailbox Status Register (MB = 6) */\r
+#define REG_CAN0_MDL6 (*(RwReg*)0x400102D4U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 6) */\r
+#define REG_CAN0_MDH6 (*(RwReg*)0x400102D8U) /**< \brief (CAN0) Mailbox Data High Register (MB = 6) */\r
+#define REG_CAN0_MCR6 (*(WoReg*)0x400102DCU) /**< \brief (CAN0) Mailbox Control Register (MB = 6) */\r
+#define REG_CAN0_MMR7 (*(RwReg*)0x400102E0U) /**< \brief (CAN0) Mailbox Mode Register (MB = 7) */\r
+#define REG_CAN0_MAM7 (*(RwReg*)0x400102E4U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 7) */\r
+#define REG_CAN0_MID7 (*(RwReg*)0x400102E8U) /**< \brief (CAN0) Mailbox ID Register (MB = 7) */\r
+#define REG_CAN0_MFID7 (*(RoReg*)0x400102ECU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 7) */\r
+#define REG_CAN0_MSR7 (*(RoReg*)0x400102F0U) /**< \brief (CAN0) Mailbox Status Register (MB = 7) */\r
+#define REG_CAN0_MDL7 (*(RwReg*)0x400102F4U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 7) */\r
+#define REG_CAN0_MDH7 (*(RwReg*)0x400102F8U) /**< \brief (CAN0) Mailbox Data High Register (MB = 7) */\r
+#define REG_CAN0_MCR7 (*(WoReg*)0x400102FCU) /**< \brief (CAN0) Mailbox Control Register (MB = 7) */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM4E_CAN0_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4E_CAN1_INSTANCE_\r
+#define _SAM4E_CAN1_INSTANCE_\r
+\r
+/* ========== Register definition for CAN1 peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_CAN1_MR (0x40014000U) /**< \brief (CAN1) Mode Register */\r
+#define REG_CAN1_IER (0x40014004U) /**< \brief (CAN1) Interrupt Enable Register */\r
+#define REG_CAN1_IDR (0x40014008U) /**< \brief (CAN1) Interrupt Disable Register */\r
+#define REG_CAN1_IMR (0x4001400CU) /**< \brief (CAN1) Interrupt Mask Register */\r
+#define REG_CAN1_SR (0x40014010U) /**< \brief (CAN1) Status Register */\r
+#define REG_CAN1_BR (0x40014014U) /**< \brief (CAN1) Baudrate Register */\r
+#define REG_CAN1_TIM (0x40014018U) /**< \brief (CAN1) Timer Register */\r
+#define REG_CAN1_TIMESTP (0x4001401CU) /**< \brief (CAN1) Timestamp Register */\r
+#define REG_CAN1_ECR (0x40014020U) /**< \brief (CAN1) Error Counter Register */\r
+#define REG_CAN1_TCR (0x40014024U) /**< \brief (CAN1) Transfer Command Register */\r
+#define REG_CAN1_ACR (0x40014028U) /**< \brief (CAN1) Abort Command Register */\r
+#define REG_CAN1_WPMR (0x400140E4U) /**< \brief (CAN1) Write Protect Mode Register */\r
+#define REG_CAN1_WPSR (0x400140E8U) /**< \brief (CAN1) Write Protect Status Register */\r
+#define REG_CAN1_MMR0 (0x40014200U) /**< \brief (CAN1) Mailbox Mode Register (MB = 0) */\r
+#define REG_CAN1_MAM0 (0x40014204U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 0) */\r
+#define REG_CAN1_MID0 (0x40014208U) /**< \brief (CAN1) Mailbox ID Register (MB = 0) */\r
+#define REG_CAN1_MFID0 (0x4001420CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 0) */\r
+#define REG_CAN1_MSR0 (0x40014210U) /**< \brief (CAN1) Mailbox Status Register (MB = 0) */\r
+#define REG_CAN1_MDL0 (0x40014214U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 0) */\r
+#define REG_CAN1_MDH0 (0x40014218U) /**< \brief (CAN1) Mailbox Data High Register (MB = 0) */\r
+#define REG_CAN1_MCR0 (0x4001421CU) /**< \brief (CAN1) Mailbox Control Register (MB = 0) */\r
+#define REG_CAN1_MMR1 (0x40014220U) /**< \brief (CAN1) Mailbox Mode Register (MB = 1) */\r
+#define REG_CAN1_MAM1 (0x40014224U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 1) */\r
+#define REG_CAN1_MID1 (0x40014228U) /**< \brief (CAN1) Mailbox ID Register (MB = 1) */\r
+#define REG_CAN1_MFID1 (0x4001422CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 1) */\r
+#define REG_CAN1_MSR1 (0x40014230U) /**< \brief (CAN1) Mailbox Status Register (MB = 1) */\r
+#define REG_CAN1_MDL1 (0x40014234U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 1) */\r
+#define REG_CAN1_MDH1 (0x40014238U) /**< \brief (CAN1) Mailbox Data High Register (MB = 1) */\r
+#define REG_CAN1_MCR1 (0x4001423CU) /**< \brief (CAN1) Mailbox Control Register (MB = 1) */\r
+#define REG_CAN1_MMR2 (0x40014240U) /**< \brief (CAN1) Mailbox Mode Register (MB = 2) */\r
+#define REG_CAN1_MAM2 (0x40014244U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 2) */\r
+#define REG_CAN1_MID2 (0x40014248U) /**< \brief (CAN1) Mailbox ID Register (MB = 2) */\r
+#define REG_CAN1_MFID2 (0x4001424CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 2) */\r
+#define REG_CAN1_MSR2 (0x40014250U) /**< \brief (CAN1) Mailbox Status Register (MB = 2) */\r
+#define REG_CAN1_MDL2 (0x40014254U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 2) */\r
+#define REG_CAN1_MDH2 (0x40014258U) /**< \brief (CAN1) Mailbox Data High Register (MB = 2) */\r
+#define REG_CAN1_MCR2 (0x4001425CU) /**< \brief (CAN1) Mailbox Control Register (MB = 2) */\r
+#define REG_CAN1_MMR3 (0x40014260U) /**< \brief (CAN1) Mailbox Mode Register (MB = 3) */\r
+#define REG_CAN1_MAM3 (0x40014264U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 3) */\r
+#define REG_CAN1_MID3 (0x40014268U) /**< \brief (CAN1) Mailbox ID Register (MB = 3) */\r
+#define REG_CAN1_MFID3 (0x4001426CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 3) */\r
+#define REG_CAN1_MSR3 (0x40014270U) /**< \brief (CAN1) Mailbox Status Register (MB = 3) */\r
+#define REG_CAN1_MDL3 (0x40014274U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 3) */\r
+#define REG_CAN1_MDH3 (0x40014278U) /**< \brief (CAN1) Mailbox Data High Register (MB = 3) */\r
+#define REG_CAN1_MCR3 (0x4001427CU) /**< \brief (CAN1) Mailbox Control Register (MB = 3) */\r
+#define REG_CAN1_MMR4 (0x40014280U) /**< \brief (CAN1) Mailbox Mode Register (MB = 4) */\r
+#define REG_CAN1_MAM4 (0x40014284U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 4) */\r
+#define REG_CAN1_MID4 (0x40014288U) /**< \brief (CAN1) Mailbox ID Register (MB = 4) */\r
+#define REG_CAN1_MFID4 (0x4001428CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 4) */\r
+#define REG_CAN1_MSR4 (0x40014290U) /**< \brief (CAN1) Mailbox Status Register (MB = 4) */\r
+#define REG_CAN1_MDL4 (0x40014294U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 4) */\r
+#define REG_CAN1_MDH4 (0x40014298U) /**< \brief (CAN1) Mailbox Data High Register (MB = 4) */\r
+#define REG_CAN1_MCR4 (0x4001429CU) /**< \brief (CAN1) Mailbox Control Register (MB = 4) */\r
+#define REG_CAN1_MMR5 (0x400142A0U) /**< \brief (CAN1) Mailbox Mode Register (MB = 5) */\r
+#define REG_CAN1_MAM5 (0x400142A4U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 5) */\r
+#define REG_CAN1_MID5 (0x400142A8U) /**< \brief (CAN1) Mailbox ID Register (MB = 5) */\r
+#define REG_CAN1_MFID5 (0x400142ACU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 5) */\r
+#define REG_CAN1_MSR5 (0x400142B0U) /**< \brief (CAN1) Mailbox Status Register (MB = 5) */\r
+#define REG_CAN1_MDL5 (0x400142B4U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 5) */\r
+#define REG_CAN1_MDH5 (0x400142B8U) /**< \brief (CAN1) Mailbox Data High Register (MB = 5) */\r
+#define REG_CAN1_MCR5 (0x400142BCU) /**< \brief (CAN1) Mailbox Control Register (MB = 5) */\r
+#define REG_CAN1_MMR6 (0x400142C0U) /**< \brief (CAN1) Mailbox Mode Register (MB = 6) */\r
+#define REG_CAN1_MAM6 (0x400142C4U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 6) */\r
+#define REG_CAN1_MID6 (0x400142C8U) /**< \brief (CAN1) Mailbox ID Register (MB = 6) */\r
+#define REG_CAN1_MFID6 (0x400142CCU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 6) */\r
+#define REG_CAN1_MSR6 (0x400142D0U) /**< \brief (CAN1) Mailbox Status Register (MB = 6) */\r
+#define REG_CAN1_MDL6 (0x400142D4U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 6) */\r
+#define REG_CAN1_MDH6 (0x400142D8U) /**< \brief (CAN1) Mailbox Data High Register (MB = 6) */\r
+#define REG_CAN1_MCR6 (0x400142DCU) /**< \brief (CAN1) Mailbox Control Register (MB = 6) */\r
+#define REG_CAN1_MMR7 (0x400142E0U) /**< \brief (CAN1) Mailbox Mode Register (MB = 7) */\r
+#define REG_CAN1_MAM7 (0x400142E4U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 7) */\r
+#define REG_CAN1_MID7 (0x400142E8U) /**< \brief (CAN1) Mailbox ID Register (MB = 7) */\r
+#define REG_CAN1_MFID7 (0x400142ECU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 7) */\r
+#define REG_CAN1_MSR7 (0x400142F0U) /**< \brief (CAN1) Mailbox Status Register (MB = 7) */\r
+#define REG_CAN1_MDL7 (0x400142F4U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 7) */\r
+#define REG_CAN1_MDH7 (0x400142F8U) /**< \brief (CAN1) Mailbox Data High Register (MB = 7) */\r
+#define REG_CAN1_MCR7 (0x400142FCU) /**< \brief (CAN1) Mailbox Control Register (MB = 7) */\r
+#else\r
+#define REG_CAN1_MR (*(RwReg*)0x40014000U) /**< \brief (CAN1) Mode Register */\r
+#define REG_CAN1_IER (*(WoReg*)0x40014004U) /**< \brief (CAN1) Interrupt Enable Register */\r
+#define REG_CAN1_IDR (*(WoReg*)0x40014008U) /**< \brief (CAN1) Interrupt Disable Register */\r
+#define REG_CAN1_IMR (*(RoReg*)0x4001400CU) /**< \brief (CAN1) Interrupt Mask Register */\r
+#define REG_CAN1_SR (*(RoReg*)0x40014010U) /**< \brief (CAN1) Status Register */\r
+#define REG_CAN1_BR (*(RwReg*)0x40014014U) /**< \brief (CAN1) Baudrate Register */\r
+#define REG_CAN1_TIM (*(RoReg*)0x40014018U) /**< \brief (CAN1) Timer Register */\r
+#define REG_CAN1_TIMESTP (*(RoReg*)0x4001401CU) /**< \brief (CAN1) Timestamp Register */\r
+#define REG_CAN1_ECR (*(RoReg*)0x40014020U) /**< \brief (CAN1) Error Counter Register */\r
+#define REG_CAN1_TCR (*(WoReg*)0x40014024U) /**< \brief (CAN1) Transfer Command Register */\r
+#define REG_CAN1_ACR (*(WoReg*)0x40014028U) /**< \brief (CAN1) Abort Command Register */\r
+#define REG_CAN1_WPMR (*(RwReg*)0x400140E4U) /**< \brief (CAN1) Write Protect Mode Register */\r
+#define REG_CAN1_WPSR (*(RoReg*)0x400140E8U) /**< \brief (CAN1) Write Protect Status Register */\r
+#define REG_CAN1_MMR0 (*(RwReg*)0x40014200U) /**< \brief (CAN1) Mailbox Mode Register (MB = 0) */\r
+#define REG_CAN1_MAM0 (*(RwReg*)0x40014204U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 0) */\r
+#define REG_CAN1_MID0 (*(RwReg*)0x40014208U) /**< \brief (CAN1) Mailbox ID Register (MB = 0) */\r
+#define REG_CAN1_MFID0 (*(RoReg*)0x4001420CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 0) */\r
+#define REG_CAN1_MSR0 (*(RoReg*)0x40014210U) /**< \brief (CAN1) Mailbox Status Register (MB = 0) */\r
+#define REG_CAN1_MDL0 (*(RwReg*)0x40014214U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 0) */\r
+#define REG_CAN1_MDH0 (*(RwReg*)0x40014218U) /**< \brief (CAN1) Mailbox Data High Register (MB = 0) */\r
+#define REG_CAN1_MCR0 (*(WoReg*)0x4001421CU) /**< \brief (CAN1) Mailbox Control Register (MB = 0) */\r
+#define REG_CAN1_MMR1 (*(RwReg*)0x40014220U) /**< \brief (CAN1) Mailbox Mode Register (MB = 1) */\r
+#define REG_CAN1_MAM1 (*(RwReg*)0x40014224U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 1) */\r
+#define REG_CAN1_MID1 (*(RwReg*)0x40014228U) /**< \brief (CAN1) Mailbox ID Register (MB = 1) */\r
+#define REG_CAN1_MFID1 (*(RoReg*)0x4001422CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 1) */\r
+#define REG_CAN1_MSR1 (*(RoReg*)0x40014230U) /**< \brief (CAN1) Mailbox Status Register (MB = 1) */\r
+#define REG_CAN1_MDL1 (*(RwReg*)0x40014234U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 1) */\r
+#define REG_CAN1_MDH1 (*(RwReg*)0x40014238U) /**< \brief (CAN1) Mailbox Data High Register (MB = 1) */\r
+#define REG_CAN1_MCR1 (*(WoReg*)0x4001423CU) /**< \brief (CAN1) Mailbox Control Register (MB = 1) */\r
+#define REG_CAN1_MMR2 (*(RwReg*)0x40014240U) /**< \brief (CAN1) Mailbox Mode Register (MB = 2) */\r
+#define REG_CAN1_MAM2 (*(RwReg*)0x40014244U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 2) */\r
+#define REG_CAN1_MID2 (*(RwReg*)0x40014248U) /**< \brief (CAN1) Mailbox ID Register (MB = 2) */\r
+#define REG_CAN1_MFID2 (*(RoReg*)0x4001424CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 2) */\r
+#define REG_CAN1_MSR2 (*(RoReg*)0x40014250U) /**< \brief (CAN1) Mailbox Status Register (MB = 2) */\r
+#define REG_CAN1_MDL2 (*(RwReg*)0x40014254U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 2) */\r
+#define REG_CAN1_MDH2 (*(RwReg*)0x40014258U) /**< \brief (CAN1) Mailbox Data High Register (MB = 2) */\r
+#define REG_CAN1_MCR2 (*(WoReg*)0x4001425CU) /**< \brief (CAN1) Mailbox Control Register (MB = 2) */\r
+#define REG_CAN1_MMR3 (*(RwReg*)0x40014260U) /**< \brief (CAN1) Mailbox Mode Register (MB = 3) */\r
+#define REG_CAN1_MAM3 (*(RwReg*)0x40014264U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 3) */\r
+#define REG_CAN1_MID3 (*(RwReg*)0x40014268U) /**< \brief (CAN1) Mailbox ID Register (MB = 3) */\r
+#define REG_CAN1_MFID3 (*(RoReg*)0x4001426CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 3) */\r
+#define REG_CAN1_MSR3 (*(RoReg*)0x40014270U) /**< \brief (CAN1) Mailbox Status Register (MB = 3) */\r
+#define REG_CAN1_MDL3 (*(RwReg*)0x40014274U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 3) */\r
+#define REG_CAN1_MDH3 (*(RwReg*)0x40014278U) /**< \brief (CAN1) Mailbox Data High Register (MB = 3) */\r
+#define REG_CAN1_MCR3 (*(WoReg*)0x4001427CU) /**< \brief (CAN1) Mailbox Control Register (MB = 3) */\r
+#define REG_CAN1_MMR4 (*(RwReg*)0x40014280U) /**< \brief (CAN1) Mailbox Mode Register (MB = 4) */\r
+#define REG_CAN1_MAM4 (*(RwReg*)0x40014284U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 4) */\r
+#define REG_CAN1_MID4 (*(RwReg*)0x40014288U) /**< \brief (CAN1) Mailbox ID Register (MB = 4) */\r
+#define REG_CAN1_MFID4 (*(RoReg*)0x4001428CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 4) */\r
+#define REG_CAN1_MSR4 (*(RoReg*)0x40014290U) /**< \brief (CAN1) Mailbox Status Register (MB = 4) */\r
+#define REG_CAN1_MDL4 (*(RwReg*)0x40014294U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 4) */\r
+#define REG_CAN1_MDH4 (*(RwReg*)0x40014298U) /**< \brief (CAN1) Mailbox Data High Register (MB = 4) */\r
+#define REG_CAN1_MCR4 (*(WoReg*)0x4001429CU) /**< \brief (CAN1) Mailbox Control Register (MB = 4) */\r
+#define REG_CAN1_MMR5 (*(RwReg*)0x400142A0U) /**< \brief (CAN1) Mailbox Mode Register (MB = 5) */\r
+#define REG_CAN1_MAM5 (*(RwReg*)0x400142A4U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 5) */\r
+#define REG_CAN1_MID5 (*(RwReg*)0x400142A8U) /**< \brief (CAN1) Mailbox ID Register (MB = 5) */\r
+#define REG_CAN1_MFID5 (*(RoReg*)0x400142ACU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 5) */\r
+#define REG_CAN1_MSR5 (*(RoReg*)0x400142B0U) /**< \brief (CAN1) Mailbox Status Register (MB = 5) */\r
+#define REG_CAN1_MDL5 (*(RwReg*)0x400142B4U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 5) */\r
+#define REG_CAN1_MDH5 (*(RwReg*)0x400142B8U) /**< \brief (CAN1) Mailbox Data High Register (MB = 5) */\r
+#define REG_CAN1_MCR5 (*(WoReg*)0x400142BCU) /**< \brief (CAN1) Mailbox Control Register (MB = 5) */\r
+#define REG_CAN1_MMR6 (*(RwReg*)0x400142C0U) /**< \brief (CAN1) Mailbox Mode Register (MB = 6) */\r
+#define REG_CAN1_MAM6 (*(RwReg*)0x400142C4U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 6) */\r
+#define REG_CAN1_MID6 (*(RwReg*)0x400142C8U) /**< \brief (CAN1) Mailbox ID Register (MB = 6) */\r
+#define REG_CAN1_MFID6 (*(RoReg*)0x400142CCU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 6) */\r
+#define REG_CAN1_MSR6 (*(RoReg*)0x400142D0U) /**< \brief (CAN1) Mailbox Status Register (MB = 6) */\r
+#define REG_CAN1_MDL6 (*(RwReg*)0x400142D4U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 6) */\r
+#define REG_CAN1_MDH6 (*(RwReg*)0x400142D8U) /**< \brief (CAN1) Mailbox Data High Register (MB = 6) */\r
+#define REG_CAN1_MCR6 (*(WoReg*)0x400142DCU) /**< \brief (CAN1) Mailbox Control Register (MB = 6) */\r
+#define REG_CAN1_MMR7 (*(RwReg*)0x400142E0U) /**< \brief (CAN1) Mailbox Mode Register (MB = 7) */\r
+#define REG_CAN1_MAM7 (*(RwReg*)0x400142E4U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 7) */\r
+#define REG_CAN1_MID7 (*(RwReg*)0x400142E8U) /**< \brief (CAN1) Mailbox ID Register (MB = 7) */\r
+#define REG_CAN1_MFID7 (*(RoReg*)0x400142ECU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 7) */\r
+#define REG_CAN1_MSR7 (*(RoReg*)0x400142F0U) /**< \brief (CAN1) Mailbox Status Register (MB = 7) */\r
+#define REG_CAN1_MDL7 (*(RwReg*)0x400142F4U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 7) */\r
+#define REG_CAN1_MDH7 (*(RwReg*)0x400142F8U) /**< \brief (CAN1) Mailbox Data High Register (MB = 7) */\r
+#define REG_CAN1_MCR7 (*(WoReg*)0x400142FCU) /**< \brief (CAN1) Mailbox Control Register (MB = 7) */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM4E_CAN1_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4E_CHIPID_INSTANCE_\r
+#define _SAM4E_CHIPID_INSTANCE_\r
+\r
+/* ========== Register definition for CHIPID peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_CHIPID_CIDR (0x400E0740U) /**< \brief (CHIPID) Chip ID Register */\r
+#define REG_CHIPID_EXID (0x400E0744U) /**< \brief (CHIPID) Chip ID Extension Register */\r
+#else\r
+#define REG_CHIPID_CIDR (*(RoReg*)0x400E0740U) /**< \brief (CHIPID) Chip ID Register */\r
+#define REG_CHIPID_EXID (*(RoReg*)0x400E0744U) /**< \brief (CHIPID) Chip ID Extension Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM4E_CHIPID_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4E_CMCC_INSTANCE_\r
+#define _SAM4E_CMCC_INSTANCE_\r
+\r
+/* ========== Register definition for CMCC peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_CMCC_TYPE (0x400C4000U) /**< \brief (CMCC) Cache Type Register */\r
+#define REG_CMCC_CFG (0x400C4004U) /**< \brief (CMCC) Cache Configuration Register */\r
+#define REG_CMCC_CTRL (0x400C4008U) /**< \brief (CMCC) Cache Control Register */\r
+#define REG_CMCC_SR (0x400C400CU) /**< \brief (CMCC) Cache Status Register */\r
+#define REG_CMCC_MAINT0 (0x400C4020U) /**< \brief (CMCC) Cache Maintenance Register 0 */\r
+#define REG_CMCC_MAINT1 (0x400C4024U) /**< \brief (CMCC) Cache Maintenance Register 1 */\r
+#define REG_CMCC_MCFG (0x400C4028U) /**< \brief (CMCC) Cache Monitor Configuration Register */\r
+#define REG_CMCC_MEN (0x400C402CU) /**< \brief (CMCC) Cache Monitor Enable Register */\r
+#define REG_CMCC_MCTRL (0x400C4030U) /**< \brief (CMCC) Cache Monitor Control Register */\r
+#define REG_CMCC_MSR (0x400C4034U) /**< \brief (CMCC) Cache Monitor Status Register */\r
+#else\r
+#define REG_CMCC_TYPE (*(RoReg*)0x400C4000U) /**< \brief (CMCC) Cache Type Register */\r
+#define REG_CMCC_CFG (*(RwReg*)0x400C4004U) /**< \brief (CMCC) Cache Configuration Register */\r
+#define REG_CMCC_CTRL (*(WoReg*)0x400C4008U) /**< \brief (CMCC) Cache Control Register */\r
+#define REG_CMCC_SR (*(RoReg*)0x400C400CU) /**< \brief (CMCC) Cache Status Register */\r
+#define REG_CMCC_MAINT0 (*(WoReg*)0x400C4020U) /**< \brief (CMCC) Cache Maintenance Register 0 */\r
+#define REG_CMCC_MAINT1 (*(WoReg*)0x400C4024U) /**< \brief (CMCC) Cache Maintenance Register 1 */\r
+#define REG_CMCC_MCFG (*(RwReg*)0x400C4028U) /**< \brief (CMCC) Cache Monitor Configuration Register */\r
+#define REG_CMCC_MEN (*(RwReg*)0x400C402CU) /**< \brief (CMCC) Cache Monitor Enable Register */\r
+#define REG_CMCC_MCTRL (*(WoReg*)0x400C4030U) /**< \brief (CMCC) Cache Monitor Control Register */\r
+#define REG_CMCC_MSR (*(RoReg*)0x400C4034U) /**< \brief (CMCC) Cache Monitor Status Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM4E_CMCC_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4E_CRCCU_INSTANCE_\r
+#define _SAM4E_CRCCU_INSTANCE_\r
+\r
+/* ========== Register definition for CRCCU peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_CRCCU_DSCR (0x40044000U) /**< \brief (CRCCU) CRCCU Descriptor Base Register */\r
+#define REG_CRCCU_DMA_EN (0x40044008U) /**< \brief (CRCCU) CRCCU DMA Enable Register */\r
+#define REG_CRCCU_DMA_DIS (0x4004400CU) /**< \brief (CRCCU) CRCCU DMA Disable Register */\r
+#define REG_CRCCU_DMA_SR (0x40044010U) /**< \brief (CRCCU) CRCCU DMA Status Register */\r
+#define REG_CRCCU_DMA_IER (0x40044014U) /**< \brief (CRCCU) CRCCU DMA Interrupt Enable Register */\r
+#define REG_CRCCU_DMA_IDR (0x40044018U) /**< \brief (CRCCU) CRCCU DMA Interrupt Disable Register */\r
+#define REG_CRCCU_DMA_IMR (0x4004401CU) /**< \brief (CRCCU) CRCCU DMA Interrupt Mask Register */\r
+#define REG_CRCCU_DMA_ISR (0x40044020U) /**< \brief (CRCCU) CRCCU DMA Interrupt Status Register */\r
+#define REG_CRCCU_CR (0x40044034U) /**< \brief (CRCCU) CRCCU Control Register */\r
+#define REG_CRCCU_MR (0x40044038U) /**< \brief (CRCCU) CRCCU Mode Register */\r
+#define REG_CRCCU_SR (0x4004403CU) /**< \brief (CRCCU) CRCCU Status Register */\r
+#define REG_CRCCU_IER (0x40044040U) /**< \brief (CRCCU) CRCCU Interrupt Enable Register */\r
+#define REG_CRCCU_IDR (0x40044044U) /**< \brief (CRCCU) CRCCU Interrupt Disable Register */\r
+#define REG_CRCCU_IMR (0x40044048U) /**< \brief (CRCCU) CRCCU Interrupt Mask Register */\r
+#define REG_CRCCU_ISR (0x4004404CU) /**< \brief (CRCCU) CRCCU Interrupt Status Register */\r
+#else\r
+#define REG_CRCCU_DSCR (*(RwReg*)0x40044000U) /**< \brief (CRCCU) CRCCU Descriptor Base Register */\r
+#define REG_CRCCU_DMA_EN (*(WoReg*)0x40044008U) /**< \brief (CRCCU) CRCCU DMA Enable Register */\r
+#define REG_CRCCU_DMA_DIS (*(WoReg*)0x4004400CU) /**< \brief (CRCCU) CRCCU DMA Disable Register */\r
+#define REG_CRCCU_DMA_SR (*(RoReg*)0x40044010U) /**< \brief (CRCCU) CRCCU DMA Status Register */\r
+#define REG_CRCCU_DMA_IER (*(WoReg*)0x40044014U) /**< \brief (CRCCU) CRCCU DMA Interrupt Enable Register */\r
+#define REG_CRCCU_DMA_IDR (*(WoReg*)0x40044018U) /**< \brief (CRCCU) CRCCU DMA Interrupt Disable Register */\r
+#define REG_CRCCU_DMA_IMR (*(RoReg*)0x4004401CU) /**< \brief (CRCCU) CRCCU DMA Interrupt Mask Register */\r
+#define REG_CRCCU_DMA_ISR (*(RoReg*)0x40044020U) /**< \brief (CRCCU) CRCCU DMA Interrupt Status Register */\r
+#define REG_CRCCU_CR (*(WoReg*)0x40044034U) /**< \brief (CRCCU) CRCCU Control Register */\r
+#define REG_CRCCU_MR (*(RwReg*)0x40044038U) /**< \brief (CRCCU) CRCCU Mode Register */\r
+#define REG_CRCCU_SR (*(RoReg*)0x4004403CU) /**< \brief (CRCCU) CRCCU Status Register */\r
+#define REG_CRCCU_IER (*(WoReg*)0x40044040U) /**< \brief (CRCCU) CRCCU Interrupt Enable Register */\r
+#define REG_CRCCU_IDR (*(WoReg*)0x40044044U) /**< \brief (CRCCU) CRCCU Interrupt Disable Register */\r
+#define REG_CRCCU_IMR (*(RoReg*)0x40044048U) /**< \brief (CRCCU) CRCCU Interrupt Mask Register */\r
+#define REG_CRCCU_ISR (*(RoReg*)0x4004404CU) /**< \brief (CRCCU) CRCCU Interrupt Status Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM4E_CRCCU_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4E_DACC_INSTANCE_\r
+#define _SAM4E_DACC_INSTANCE_\r
+\r
+/* ========== Register definition for DACC peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_DACC_CR (0x400B8000U) /**< \brief (DACC) Control Register */\r
+#define REG_DACC_MR (0x400B8004U) /**< \brief (DACC) Mode Register */\r
+#define REG_DACC_CHER (0x400B8010U) /**< \brief (DACC) Channel Enable Register */\r
+#define REG_DACC_CHDR (0x400B8014U) /**< \brief (DACC) Channel Disable Register */\r
+#define REG_DACC_CHSR (0x400B8018U) /**< \brief (DACC) Channel Status Register */\r
+#define REG_DACC_CDR (0x400B8020U) /**< \brief (DACC) Conversion Data Register */\r
+#define REG_DACC_IER (0x400B8024U) /**< \brief (DACC) Interrupt Enable Register */\r
+#define REG_DACC_IDR (0x400B8028U) /**< \brief (DACC) Interrupt Disable Register */\r
+#define REG_DACC_IMR (0x400B802CU) /**< \brief (DACC) Interrupt Mask Register */\r
+#define REG_DACC_ISR (0x400B8030U) /**< \brief (DACC) Interrupt Status Register */\r
+#define REG_DACC_ACR (0x400B8094U) /**< \brief (DACC) Analog Current Register */\r
+#define REG_DACC_WPMR (0x400B80E4U) /**< \brief (DACC) Write Protect Mode register */\r
+#define REG_DACC_WPSR (0x400B80E8U) /**< \brief (DACC) Write Protect Status register */\r
+#define REG_DACC_TPR (0x400B8108U) /**< \brief (DACC) Transmit Pointer Register */\r
+#define REG_DACC_TCR (0x400B810CU) /**< \brief (DACC) Transmit Counter Register */\r
+#define REG_DACC_TNPR (0x400B8118U) /**< \brief (DACC) Transmit Next Pointer Register */\r
+#define REG_DACC_TNCR (0x400B811CU) /**< \brief (DACC) Transmit Next Counter Register */\r
+#define REG_DACC_PTCR (0x400B8120U) /**< \brief (DACC) Transfer Control Register */\r
+#define REG_DACC_PTSR (0x400B8124U) /**< \brief (DACC) Transfer Status Register */\r
+#else\r
+#define REG_DACC_CR (*(WoReg*)0x400B8000U) /**< \brief (DACC) Control Register */\r
+#define REG_DACC_MR (*(RwReg*)0x400B8004U) /**< \brief (DACC) Mode Register */\r
+#define REG_DACC_CHER (*(WoReg*)0x400B8010U) /**< \brief (DACC) Channel Enable Register */\r
+#define REG_DACC_CHDR (*(WoReg*)0x400B8014U) /**< \brief (DACC) Channel Disable Register */\r
+#define REG_DACC_CHSR (*(RoReg*)0x400B8018U) /**< \brief (DACC) Channel Status Register */\r
+#define REG_DACC_CDR (*(WoReg*)0x400B8020U) /**< \brief (DACC) Conversion Data Register */\r
+#define REG_DACC_IER (*(WoReg*)0x400B8024U) /**< \brief (DACC) Interrupt Enable Register */\r
+#define REG_DACC_IDR (*(WoReg*)0x400B8028U) /**< \brief (DACC) Interrupt Disable Register */\r
+#define REG_DACC_IMR (*(RoReg*)0x400B802CU) /**< \brief (DACC) Interrupt Mask Register */\r
+#define REG_DACC_ISR (*(RoReg*)0x400B8030U) /**< \brief (DACC) Interrupt Status Register */\r
+#define REG_DACC_ACR (*(RwReg*)0x400B8094U) /**< \brief (DACC) Analog Current Register */\r
+#define REG_DACC_WPMR (*(RwReg*)0x400B80E4U) /**< \brief (DACC) Write Protect Mode register */\r
+#define REG_DACC_WPSR (*(RoReg*)0x400B80E8U) /**< \brief (DACC) Write Protect Status register */\r
+#define REG_DACC_TPR (*(RwReg*)0x400B8108U) /**< \brief (DACC) Transmit Pointer Register */\r
+#define REG_DACC_TCR (*(RwReg*)0x400B810CU) /**< \brief (DACC) Transmit Counter Register */\r
+#define REG_DACC_TNPR (*(RwReg*)0x400B8118U) /**< \brief (DACC) Transmit Next Pointer Register */\r
+#define REG_DACC_TNCR (*(RwReg*)0x400B811CU) /**< \brief (DACC) Transmit Next Counter Register */\r
+#define REG_DACC_PTCR (*(WoReg*)0x400B8120U) /**< \brief (DACC) Transfer Control Register */\r
+#define REG_DACC_PTSR (*(RoReg*)0x400B8124U) /**< \brief (DACC) Transfer Status Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM4E_DACC_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4E_DMAC_INSTANCE_\r
+#define _SAM4E_DMAC_INSTANCE_\r
+\r
+/* ========== Register definition for DMAC peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_DMAC_GCFG (0x400C0000U) /**< \brief (DMAC) DMAC Global Configuration Register */\r
+#define REG_DMAC_EN (0x400C0004U) /**< \brief (DMAC) DMAC Enable Register */\r
+#define REG_DMAC_SREQ (0x400C0008U) /**< \brief (DMAC) DMAC Software Single Request Register */\r
+#define REG_DMAC_CREQ (0x400C000CU) /**< \brief (DMAC) DMAC Software Chunk Transfer Request Register */\r
+#define REG_DMAC_LAST (0x400C0010U) /**< \brief (DMAC) DMAC Software Last Transfer Flag Register */\r
+#define REG_DMAC_EBCIER (0x400C0018U) /**< \brief (DMAC) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Enable register. */\r
+#define REG_DMAC_EBCIDR (0x400C001CU) /**< \brief (DMAC) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Disable register. */\r
+#define REG_DMAC_EBCIMR (0x400C0020U) /**< \brief (DMAC) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Mask Register. */\r
+#define REG_DMAC_EBCISR (0x400C0024U) /**< \brief (DMAC) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Status Register. */\r
+#define REG_DMAC_CHER (0x400C0028U) /**< \brief (DMAC) DMAC Channel Handler Enable Register */\r
+#define REG_DMAC_CHDR (0x400C002CU) /**< \brief (DMAC) DMAC Channel Handler Disable Register */\r
+#define REG_DMAC_CHSR (0x400C0030U) /**< \brief (DMAC) DMAC Channel Handler Status Register */\r
+#define REG_DMAC_SADDR0 (0x400C003CU) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 0) */\r
+#define REG_DMAC_DADDR0 (0x400C0040U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 0) */\r
+#define REG_DMAC_DSCR0 (0x400C0044U) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 0) */\r
+#define REG_DMAC_CTRLA0 (0x400C0048U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 0) */\r
+#define REG_DMAC_CTRLB0 (0x400C004CU) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 0) */\r
+#define REG_DMAC_CFG0 (0x400C0050U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 0) */\r
+#define REG_DMAC_SADDR1 (0x400C0064U) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 1) */\r
+#define REG_DMAC_DADDR1 (0x400C0068U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 1) */\r
+#define REG_DMAC_DSCR1 (0x400C006CU) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 1) */\r
+#define REG_DMAC_CTRLA1 (0x400C0070U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 1) */\r
+#define REG_DMAC_CTRLB1 (0x400C0074U) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 1) */\r
+#define REG_DMAC_CFG1 (0x400C0078U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 1) */\r
+#define REG_DMAC_SADDR2 (0x400C008CU) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 2) */\r
+#define REG_DMAC_DADDR2 (0x400C0090U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 2) */\r
+#define REG_DMAC_DSCR2 (0x400C0094U) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 2) */\r
+#define REG_DMAC_CTRLA2 (0x400C0098U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 2) */\r
+#define REG_DMAC_CTRLB2 (0x400C009CU) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 2) */\r
+#define REG_DMAC_CFG2 (0x400C00A0U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 2) */\r
+#define REG_DMAC_SADDR3 (0x400C00B4U) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 3) */\r
+#define REG_DMAC_DADDR3 (0x400C00B8U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 3) */\r
+#define REG_DMAC_DSCR3 (0x400C00BCU) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 3) */\r
+#define REG_DMAC_CTRLA3 (0x400C00C0U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 3) */\r
+#define REG_DMAC_CTRLB3 (0x400C00C4U) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 3) */\r
+#define REG_DMAC_CFG3 (0x400C00C8U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 3) */\r
+#define REG_DMAC_WPMR (0x400C01E4U) /**< \brief (DMAC) DMAC Write Protect Mode Register */\r
+#define REG_DMAC_WPSR (0x400C01E8U) /**< \brief (DMAC) DMAC Write Protect Status Register */\r
+#else\r
+#define REG_DMAC_GCFG (*(RwReg*)0x400C0000U) /**< \brief (DMAC) DMAC Global Configuration Register */\r
+#define REG_DMAC_EN (*(RwReg*)0x400C0004U) /**< \brief (DMAC) DMAC Enable Register */\r
+#define REG_DMAC_SREQ (*(RwReg*)0x400C0008U) /**< \brief (DMAC) DMAC Software Single Request Register */\r
+#define REG_DMAC_CREQ (*(RwReg*)0x400C000CU) /**< \brief (DMAC) DMAC Software Chunk Transfer Request Register */\r
+#define REG_DMAC_LAST (*(RwReg*)0x400C0010U) /**< \brief (DMAC) DMAC Software Last Transfer Flag Register */\r
+#define REG_DMAC_EBCIER (*(WoReg*)0x400C0018U) /**< \brief (DMAC) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Enable register. */\r
+#define REG_DMAC_EBCIDR (*(WoReg*)0x400C001CU) /**< \brief (DMAC) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Disable register. */\r
+#define REG_DMAC_EBCIMR (*(RoReg*)0x400C0020U) /**< \brief (DMAC) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Mask Register. */\r
+#define REG_DMAC_EBCISR (*(RoReg*)0x400C0024U) /**< \brief (DMAC) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Status Register. */\r
+#define REG_DMAC_CHER (*(WoReg*)0x400C0028U) /**< \brief (DMAC) DMAC Channel Handler Enable Register */\r
+#define REG_DMAC_CHDR (*(WoReg*)0x400C002CU) /**< \brief (DMAC) DMAC Channel Handler Disable Register */\r
+#define REG_DMAC_CHSR (*(RoReg*)0x400C0030U) /**< \brief (DMAC) DMAC Channel Handler Status Register */\r
+#define REG_DMAC_SADDR0 (*(RwReg*)0x400C003CU) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 0) */\r
+#define REG_DMAC_DADDR0 (*(RwReg*)0x400C0040U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 0) */\r
+#define REG_DMAC_DSCR0 (*(RwReg*)0x400C0044U) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 0) */\r
+#define REG_DMAC_CTRLA0 (*(RwReg*)0x400C0048U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 0) */\r
+#define REG_DMAC_CTRLB0 (*(RwReg*)0x400C004CU) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 0) */\r
+#define REG_DMAC_CFG0 (*(RwReg*)0x400C0050U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 0) */\r
+#define REG_DMAC_SADDR1 (*(RwReg*)0x400C0064U) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 1) */\r
+#define REG_DMAC_DADDR1 (*(RwReg*)0x400C0068U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 1) */\r
+#define REG_DMAC_DSCR1 (*(RwReg*)0x400C006CU) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 1) */\r
+#define REG_DMAC_CTRLA1 (*(RwReg*)0x400C0070U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 1) */\r
+#define REG_DMAC_CTRLB1 (*(RwReg*)0x400C0074U) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 1) */\r
+#define REG_DMAC_CFG1 (*(RwReg*)0x400C0078U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 1) */\r
+#define REG_DMAC_SADDR2 (*(RwReg*)0x400C008CU) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 2) */\r
+#define REG_DMAC_DADDR2 (*(RwReg*)0x400C0090U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 2) */\r
+#define REG_DMAC_DSCR2 (*(RwReg*)0x400C0094U) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 2) */\r
+#define REG_DMAC_CTRLA2 (*(RwReg*)0x400C0098U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 2) */\r
+#define REG_DMAC_CTRLB2 (*(RwReg*)0x400C009CU) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 2) */\r
+#define REG_DMAC_CFG2 (*(RwReg*)0x400C00A0U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 2) */\r
+#define REG_DMAC_SADDR3 (*(RwReg*)0x400C00B4U) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 3) */\r
+#define REG_DMAC_DADDR3 (*(RwReg*)0x400C00B8U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 3) */\r
+#define REG_DMAC_DSCR3 (*(RwReg*)0x400C00BCU) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 3) */\r
+#define REG_DMAC_CTRLA3 (*(RwReg*)0x400C00C0U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 3) */\r
+#define REG_DMAC_CTRLB3 (*(RwReg*)0x400C00C4U) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 3) */\r
+#define REG_DMAC_CFG3 (*(RwReg*)0x400C00C8U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 3) */\r
+#define REG_DMAC_WPMR (*(RwReg*)0x400C01E4U) /**< \brief (DMAC) DMAC Write Protect Mode Register */\r
+#define REG_DMAC_WPSR (*(RoReg*)0x400C01E8U) /**< \brief (DMAC) DMAC Write Protect Status Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM4E_DMAC_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4E_EFC_INSTANCE_\r
+#define _SAM4E_EFC_INSTANCE_\r
+\r
+/* ========== Register definition for EFC peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_EFC_FMR (0x400E0A00U) /**< \brief (EFC) EEFC Flash Mode Register */\r
+#define REG_EFC_FCR (0x400E0A04U) /**< \brief (EFC) EEFC Flash Command Register */\r
+#define REG_EFC_FSR (0x400E0A08U) /**< \brief (EFC) EEFC Flash Status Register */\r
+#define REG_EFC_FRR (0x400E0A0CU) /**< \brief (EFC) EEFC Flash Result Register */\r
+#else\r
+#define REG_EFC_FMR (*(RwReg*)0x400E0A00U) /**< \brief (EFC) EEFC Flash Mode Register */\r
+#define REG_EFC_FCR (*(WoReg*)0x400E0A04U) /**< \brief (EFC) EEFC Flash Command Register */\r
+#define REG_EFC_FSR (*(RoReg*)0x400E0A08U) /**< \brief (EFC) EEFC Flash Status Register */\r
+#define REG_EFC_FRR (*(RoReg*)0x400E0A0CU) /**< \brief (EFC) EEFC Flash Result Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM4E_EFC_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4E_GMAC_INSTANCE_\r
+#define _SAM4E_GMAC_INSTANCE_\r
+\r
+/* ========== Register definition for GMAC peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_GMAC_NCR (0x40034000U) /**< \brief (GMAC) Network Control Register */\r
+#define REG_GMAC_NCFGR (0x40034004U) /**< \brief (GMAC) Network Configuration Register */\r
+#define REG_GMAC_NSR (0x40034008U) /**< \brief (GMAC) Network Status Register */\r
+#define REG_GMAC_UR (0x4003400CU) /**< \brief (GMAC) User Register */\r
+#define REG_GMAC_DCFGR (0x40034010U) /**< \brief (GMAC) DMA Configuration Register */\r
+#define REG_GMAC_TSR (0x40034014U) /**< \brief (GMAC) Transmit Status Register */\r
+#define REG_GMAC_RBQB (0x40034018U) /**< \brief (GMAC) Receive Buffer Queue Base Address */\r
+#define REG_GMAC_TBQB (0x4003401CU) /**< \brief (GMAC) Transmit Buffer Queue Base Address */\r
+#define REG_GMAC_RSR (0x40034020U) /**< \brief (GMAC) Receive Status Register */\r
+#define REG_GMAC_ISR (0x40034024U) /**< \brief (GMAC) Interrupt Status Register */\r
+#define REG_GMAC_IER (0x40034028U) /**< \brief (GMAC) Interrupt Enable Register */\r
+#define REG_GMAC_IDR (0x4003402CU) /**< \brief (GMAC) Interrupt Disable Register */\r
+#define REG_GMAC_IMR (0x40034030U) /**< \brief (GMAC) Interrupt Mask Register */\r
+#define REG_GMAC_MAN (0x40034034U) /**< \brief (GMAC) PHY Maintenance Register */\r
+#define REG_GMAC_RPQ (0x40034038U) /**< \brief (GMAC) Received Pause Quantum Register */\r
+#define REG_GMAC_TPQ (0x4003403CU) /**< \brief (GMAC) Transmit Pause Quantum Register */\r
+#define REG_GMAC_HRB (0x40034080U) /**< \brief (GMAC) Hash Register Bottom [31:0] */\r
+#define REG_GMAC_HRT (0x40034084U) /**< \brief (GMAC) Hash Register Top [63:32] */\r
+#define REG_GMAC_SAB1 (0x40034088U) /**< \brief (GMAC) Specific Address 1 Bottom [31:0] Register */\r
+#define REG_GMAC_SAT1 (0x4003408CU) /**< \brief (GMAC) Specific Address 1 Top [47:32] Register */\r
+#define REG_GMAC_SAB2 (0x40034090U) /**< \brief (GMAC) Specific Address 2 Bottom [31:0] Register */\r
+#define REG_GMAC_SAT2 (0x40034094U) /**< \brief (GMAC) Specific Address 2 Top [47:32] Register */\r
+#define REG_GMAC_SAB3 (0x40034098U) /**< \brief (GMAC) Specific Address 3 Bottom [31:0] Register */\r
+#define REG_GMAC_SAT3 (0x4003409CU) /**< \brief (GMAC) Specific Address 3 Top [47:32] Register */\r
+#define REG_GMAC_SAB4 (0x400340A0U) /**< \brief (GMAC) Specific Address 4 Bottom [31:0] Register */\r
+#define REG_GMAC_SAT4 (0x400340A4U) /**< \brief (GMAC) Specific Address 4 Top [47:32] Register */\r
+#define REG_GMAC_TIDM (0x400340A8U) /**< \brief (GMAC) Type ID Match 1 Register */\r
+#define REG_GMAC_IPGS (0x400340BCU) /**< \brief (GMAC) IPG Stretch Register */\r
+#define REG_GMAC_SVLAN (0x400340C0U) /**< \brief (GMAC) Stacked VLAN Register */\r
+#define REG_GMAC_TPFCP (0x400340C4U) /**< \brief (GMAC) Transmit PFC Pause Register */\r
+#define REG_GMAC_SAMB1 (0x400340C8U) /**< \brief (GMAC) Specific Address 1 Mask Bottom [31:0] Register */\r
+#define REG_GMAC_SAMT1 (0x400340CCU) /**< \brief (GMAC) Specific Address 1 Mask Top [47:32] Register */\r
+#define REG_GMAC_OTLO (0x40034100U) /**< \brief (GMAC) Octets Transmitted [31:0] Register */\r
+#define REG_GMAC_OTHI (0x40034104U) /**< \brief (GMAC) Octets Transmitted [47:32] Register */\r
+#define REG_GMAC_FT (0x40034108U) /**< \brief (GMAC) Frames Transmitted Register */\r
+#define REG_GMAC_BCFT (0x4003410CU) /**< \brief (GMAC) Broadcast Frames Transmitted Register */\r
+#define REG_GMAC_MFT (0x40034110U) /**< \brief (GMAC) Multicast Frames Transmitted Register */\r
+#define REG_GMAC_PFT (0x40034114U) /**< \brief (GMAC) Pause Frames Transmitted Register */\r
+#define REG_GMAC_BFT64 (0x40034118U) /**< \brief (GMAC) 64 Byte Frames Transmitted Register */\r
+#define REG_GMAC_TBFT127 (0x4003411CU) /**< \brief (GMAC) 65 to 127 Byte Frames Transmitted Register */\r
+#define REG_GMAC_TBFT255 (0x40034120U) /**< \brief (GMAC) 128 to 255 Byte Frames Transmitted Register */\r
+#define REG_GMAC_TBFT511 (0x40034124U) /**< \brief (GMAC) 256 to 511 Byte Frames Transmitted Register */\r
+#define REG_GMAC_TBFT1023 (0x40034128U) /**< \brief (GMAC) 512 to 1023 Byte Frames Transmitted Register */\r
+#define REG_GMAC_TBFT1518 (0x4003412CU) /**< \brief (GMAC) 1024 to 1518 Byte Frames Transmitted Register */\r
+#define REG_GMAC_GTBFT1518 (0x40034130U) /**< \brief (GMAC) Greater Than 1518 Byte Frames Transmitted Register */\r
+#define REG_GMAC_TUR (0x40034134U) /**< \brief (GMAC) Transmit Under Runs Register */\r
+#define REG_GMAC_SCF (0x40034138U) /**< \brief (GMAC) Single Collision Frames Register */\r
+#define REG_GMAC_MCF (0x4003413CU) /**< \brief (GMAC) Multiple Collision Frames Register */\r
+#define REG_GMAC_EC (0x40034140U) /**< \brief (GMAC) Excessive Collisions Register */\r
+#define REG_GMAC_LC (0x40034144U) /**< \brief (GMAC) Late Collisions Register */\r
+#define REG_GMAC_DTF (0x40034148U) /**< \brief (GMAC) Deferred Transmission Frames Register */\r
+#define REG_GMAC_CSE (0x4003414CU) /**< \brief (GMAC) Carrier Sense Errors Register */\r
+#define REG_GMAC_ORLO (0x40034150U) /**< \brief (GMAC) Octets Received [31:0] Received */\r
+#define REG_GMAC_ORHI (0x40034154U) /**< \brief (GMAC) Octets Received [47:32] Received */\r
+#define REG_GMAC_FR (0x40034158U) /**< \brief (GMAC) Frames Received Register */\r
+#define REG_GMAC_BCFR (0x4003415CU) /**< \brief (GMAC) Broadcast Frames Received Register */\r
+#define REG_GMAC_MFR (0x40034160U) /**< \brief (GMAC) Multicast Frames Received Register */\r
+#define REG_GMAC_PFR (0x40034164U) /**< \brief (GMAC) Pause Frames Received Register */\r
+#define REG_GMAC_BFR64 (0x40034168U) /**< \brief (GMAC) 64 Byte Frames Received Register */\r
+#define REG_GMAC_TBFR127 (0x4003416CU) /**< \brief (GMAC) 65 to 127 Byte Frames Received Register */\r
+#define REG_GMAC_TBFR255 (0x40034170U) /**< \brief (GMAC) 128 to 255 Byte Frames Received Register */\r
+#define REG_GMAC_TBFR511 (0x40034174U) /**< \brief (GMAC) 256 to 511Byte Frames Received Register */\r
+#define REG_GMAC_TBFR1023 (0x40034178U) /**< \brief (GMAC) 512 to 1023 Byte Frames Received Register */\r
+#define REG_GMAC_TBFR1518 (0x4003417CU) /**< \brief (GMAC) 1024 to 1518 Byte Frames Received Register */\r
+#define REG_GMAC_TMXBFR (0x40034180U) /**< \brief (GMAC) 1519 to Maximum Byte Frames Received Register */\r
+#define REG_GMAC_UFR (0x40034184U) /**< \brief (GMAC) Undersize Frames Received Register */\r
+#define REG_GMAC_OFR (0x40034188U) /**< \brief (GMAC) Oversize Frames Received Register */\r
+#define REG_GMAC_JR (0x4003418CU) /**< \brief (GMAC) Jabbers Received Register */\r
+#define REG_GMAC_FCSE (0x40034190U) /**< \brief (GMAC) Frame Check Sequence Errors Register */\r
+#define REG_GMAC_LFFE (0x40034194U) /**< \brief (GMAC) Length Field Frame Errors Register */\r
+#define REG_GMAC_RSE (0x40034198U) /**< \brief (GMAC) Receive Symbol Errors Register */\r
+#define REG_GMAC_AE (0x4003419CU) /**< \brief (GMAC) Alignment Errors Register */\r
+#define REG_GMAC_RRE (0x400341A0U) /**< \brief (GMAC) Receive Resource Errors Register */\r
+#define REG_GMAC_ROE (0x400341A4U) /**< \brief (GMAC) Receive Overrun Register */\r
+#define REG_GMAC_IHCE (0x400341A8U) /**< \brief (GMAC) IP Header Checksum Errors Register */\r
+#define REG_GMAC_TCE (0x400341ACU) /**< \brief (GMAC) TCP Checksum Errors Register */\r
+#define REG_GMAC_UCE (0x400341B0U) /**< \brief (GMAC) UDP Checksum Errors Register */\r
+#define REG_GMAC_TSSS (0x400341C8U) /**< \brief (GMAC) 1588 Timer Sync Strobe Seconds Register */\r
+#define REG_GMAC_TSSN (0x400341CCU) /**< \brief (GMAC) 1588 Timer Sync Strobe Nanoseconds Register */\r
+#define REG_GMAC_TS (0x400341D0U) /**< \brief (GMAC) 1588 Timer Seconds Register */\r
+#define REG_GMAC_TN (0x400341D4U) /**< \brief (GMAC) 1588 Timer Nanoseconds Register */\r
+#define REG_GMAC_TA (0x400341D8U) /**< \brief (GMAC) 1588 Timer Adjust Register */\r
+#define REG_GMAC_TI (0x400341DCU) /**< \brief (GMAC) 1588 Timer Increment Register */\r
+#define REG_GMAC_EFTS (0x400341E0U) /**< \brief (GMAC) PTP Event Frame Transmitted Seconds */\r
+#define REG_GMAC_EFTN (0x400341E4U) /**< \brief (GMAC) PTP Event Frame Transmitted Nanoseconds */\r
+#define REG_GMAC_EFRS (0x400341E8U) /**< \brief (GMAC) PTP Event Frame Received Seconds */\r
+#define REG_GMAC_EFRN (0x400341ECU) /**< \brief (GMAC) PTP Event Frame Received Nanoseconds */\r
+#define REG_GMAC_PEFTS (0x400341F0U) /**< \brief (GMAC) PTP Peer Event Frame Transmitted Seconds */\r
+#define REG_GMAC_PEFTN (0x400341F4U) /**< \brief (GMAC) PTP Peer Event Frame Transmitted Nanoseconds */\r
+#define REG_GMAC_PEFRS (0x400341F8U) /**< \brief (GMAC) PTP Peer Event Frame Received Seconds */\r
+#define REG_GMAC_PEFRN (0x400341FCU) /**< \brief (GMAC) PTP Peer Event Frame Received Nanoseconds */\r
+#else\r
+#define REG_GMAC_NCR (*(RwReg*)0x40034000U) /**< \brief (GMAC) Network Control Register */\r
+#define REG_GMAC_NCFGR (*(RwReg*)0x40034004U) /**< \brief (GMAC) Network Configuration Register */\r
+#define REG_GMAC_NSR (*(RoReg*)0x40034008U) /**< \brief (GMAC) Network Status Register */\r
+#define REG_GMAC_UR (*(RwReg*)0x4003400CU) /**< \brief (GMAC) User Register */\r
+#define REG_GMAC_DCFGR (*(RwReg*)0x40034010U) /**< \brief (GMAC) DMA Configuration Register */\r
+#define REG_GMAC_TSR (*(RwReg*)0x40034014U) /**< \brief (GMAC) Transmit Status Register */\r
+#define REG_GMAC_RBQB (*(RwReg*)0x40034018U) /**< \brief (GMAC) Receive Buffer Queue Base Address */\r
+#define REG_GMAC_TBQB (*(RwReg*)0x4003401CU) /**< \brief (GMAC) Transmit Buffer Queue Base Address */\r
+#define REG_GMAC_RSR (*(RwReg*)0x40034020U) /**< \brief (GMAC) Receive Status Register */\r
+#define REG_GMAC_ISR (*(RoReg*)0x40034024U) /**< \brief (GMAC) Interrupt Status Register */\r
+#define REG_GMAC_IER (*(WoReg*)0x40034028U) /**< \brief (GMAC) Interrupt Enable Register */\r
+#define REG_GMAC_IDR (*(WoReg*)0x4003402CU) /**< \brief (GMAC) Interrupt Disable Register */\r
+#define REG_GMAC_IMR (*(RoReg*)0x40034030U) /**< \brief (GMAC) Interrupt Mask Register */\r
+#define REG_GMAC_MAN (*(RwReg*)0x40034034U) /**< \brief (GMAC) PHY Maintenance Register */\r
+#define REG_GMAC_RPQ (*(RoReg*)0x40034038U) /**< \brief (GMAC) Received Pause Quantum Register */\r
+#define REG_GMAC_TPQ (*(RwReg*)0x4003403CU) /**< \brief (GMAC) Transmit Pause Quantum Register */\r
+#define REG_GMAC_HRB (*(RwReg*)0x40034080U) /**< \brief (GMAC) Hash Register Bottom [31:0] */\r
+#define REG_GMAC_HRT (*(RwReg*)0x40034084U) /**< \brief (GMAC) Hash Register Top [63:32] */\r
+#define REG_GMAC_SAB1 (*(RwReg*)0x40034088U) /**< \brief (GMAC) Specific Address 1 Bottom [31:0] Register */\r
+#define REG_GMAC_SAT1 (*(RwReg*)0x4003408CU) /**< \brief (GMAC) Specific Address 1 Top [47:32] Register */\r
+#define REG_GMAC_SAB2 (*(RwReg*)0x40034090U) /**< \brief (GMAC) Specific Address 2 Bottom [31:0] Register */\r
+#define REG_GMAC_SAT2 (*(RwReg*)0x40034094U) /**< \brief (GMAC) Specific Address 2 Top [47:32] Register */\r
+#define REG_GMAC_SAB3 (*(RwReg*)0x40034098U) /**< \brief (GMAC) Specific Address 3 Bottom [31:0] Register */\r
+#define REG_GMAC_SAT3 (*(RwReg*)0x4003409CU) /**< \brief (GMAC) Specific Address 3 Top [47:32] Register */\r
+#define REG_GMAC_SAB4 (*(RwReg*)0x400340A0U) /**< \brief (GMAC) Specific Address 4 Bottom [31:0] Register */\r
+#define REG_GMAC_SAT4 (*(RwReg*)0x400340A4U) /**< \brief (GMAC) Specific Address 4 Top [47:32] Register */\r
+#define REG_GMAC_TIDM (*(RwReg*)0x400340A8U) /**< \brief (GMAC) Type ID Match 1 Register */\r
+#define REG_GMAC_IPGS (*(RwReg*)0x400340BCU) /**< \brief (GMAC) IPG Stretch Register */\r
+#define REG_GMAC_SVLAN (*(RwReg*)0x400340C0U) /**< \brief (GMAC) Stacked VLAN Register */\r
+#define REG_GMAC_TPFCP (*(RwReg*)0x400340C4U) /**< \brief (GMAC) Transmit PFC Pause Register */\r
+#define REG_GMAC_SAMB1 (*(RwReg*)0x400340C8U) /**< \brief (GMAC) Specific Address 1 Mask Bottom [31:0] Register */\r
+#define REG_GMAC_SAMT1 (*(RwReg*)0x400340CCU) /**< \brief (GMAC) Specific Address 1 Mask Top [47:32] Register */\r
+#define REG_GMAC_OTLO (*(RoReg*)0x40034100U) /**< \brief (GMAC) Octets Transmitted [31:0] Register */\r
+#define REG_GMAC_OTHI (*(RoReg*)0x40034104U) /**< \brief (GMAC) Octets Transmitted [47:32] Register */\r
+#define REG_GMAC_FT (*(RoReg*)0x40034108U) /**< \brief (GMAC) Frames Transmitted Register */\r
+#define REG_GMAC_BCFT (*(RoReg*)0x4003410CU) /**< \brief (GMAC) Broadcast Frames Transmitted Register */\r
+#define REG_GMAC_MFT (*(RoReg*)0x40034110U) /**< \brief (GMAC) Multicast Frames Transmitted Register */\r
+#define REG_GMAC_PFT (*(RoReg*)0x40034114U) /**< \brief (GMAC) Pause Frames Transmitted Register */\r
+#define REG_GMAC_BFT64 (*(RoReg*)0x40034118U) /**< \brief (GMAC) 64 Byte Frames Transmitted Register */\r
+#define REG_GMAC_TBFT127 (*(RoReg*)0x4003411CU) /**< \brief (GMAC) 65 to 127 Byte Frames Transmitted Register */\r
+#define REG_GMAC_TBFT255 (*(RoReg*)0x40034120U) /**< \brief (GMAC) 128 to 255 Byte Frames Transmitted Register */\r
+#define REG_GMAC_TBFT511 (*(RoReg*)0x40034124U) /**< \brief (GMAC) 256 to 511 Byte Frames Transmitted Register */\r
+#define REG_GMAC_TBFT1023 (*(RoReg*)0x40034128U) /**< \brief (GMAC) 512 to 1023 Byte Frames Transmitted Register */\r
+#define REG_GMAC_TBFT1518 (*(RoReg*)0x4003412CU) /**< \brief (GMAC) 1024 to 1518 Byte Frames Transmitted Register */\r
+#define REG_GMAC_GTBFT1518 (*(RoReg*)0x40034130U) /**< \brief (GMAC) Greater Than 1518 Byte Frames Transmitted Register */\r
+#define REG_GMAC_TUR (*(RoReg*)0x40034134U) /**< \brief (GMAC) Transmit Under Runs Register */\r
+#define REG_GMAC_SCF (*(RoReg*)0x40034138U) /**< \brief (GMAC) Single Collision Frames Register */\r
+#define REG_GMAC_MCF (*(RoReg*)0x4003413CU) /**< \brief (GMAC) Multiple Collision Frames Register */\r
+#define REG_GMAC_EC (*(RoReg*)0x40034140U) /**< \brief (GMAC) Excessive Collisions Register */\r
+#define REG_GMAC_LC (*(RoReg*)0x40034144U) /**< \brief (GMAC) Late Collisions Register */\r
+#define REG_GMAC_DTF (*(RoReg*)0x40034148U) /**< \brief (GMAC) Deferred Transmission Frames Register */\r
+#define REG_GMAC_CSE (*(RoReg*)0x4003414CU) /**< \brief (GMAC) Carrier Sense Errors Register */\r
+#define REG_GMAC_ORLO (*(RoReg*)0x40034150U) /**< \brief (GMAC) Octets Received [31:0] Received */\r
+#define REG_GMAC_ORHI (*(RoReg*)0x40034154U) /**< \brief (GMAC) Octets Received [47:32] Received */\r
+#define REG_GMAC_FR (*(RoReg*)0x40034158U) /**< \brief (GMAC) Frames Received Register */\r
+#define REG_GMAC_BCFR (*(RoReg*)0x4003415CU) /**< \brief (GMAC) Broadcast Frames Received Register */\r
+#define REG_GMAC_MFR (*(RoReg*)0x40034160U) /**< \brief (GMAC) Multicast Frames Received Register */\r
+#define REG_GMAC_PFR (*(RoReg*)0x40034164U) /**< \brief (GMAC) Pause Frames Received Register */\r
+#define REG_GMAC_BFR64 (*(RoReg*)0x40034168U) /**< \brief (GMAC) 64 Byte Frames Received Register */\r
+#define REG_GMAC_TBFR127 (*(RoReg*)0x4003416CU) /**< \brief (GMAC) 65 to 127 Byte Frames Received Register */\r
+#define REG_GMAC_TBFR255 (*(RoReg*)0x40034170U) /**< \brief (GMAC) 128 to 255 Byte Frames Received Register */\r
+#define REG_GMAC_TBFR511 (*(RoReg*)0x40034174U) /**< \brief (GMAC) 256 to 511Byte Frames Received Register */\r
+#define REG_GMAC_TBFR1023 (*(RoReg*)0x40034178U) /**< \brief (GMAC) 512 to 1023 Byte Frames Received Register */\r
+#define REG_GMAC_TBFR1518 (*(RoReg*)0x4003417CU) /**< \brief (GMAC) 1024 to 1518 Byte Frames Received Register */\r
+#define REG_GMAC_TMXBFR (*(RoReg*)0x40034180U) /**< \brief (GMAC) 1519 to Maximum Byte Frames Received Register */\r
+#define REG_GMAC_UFR (*(RoReg*)0x40034184U) /**< \brief (GMAC) Undersize Frames Received Register */\r
+#define REG_GMAC_OFR (*(RoReg*)0x40034188U) /**< \brief (GMAC) Oversize Frames Received Register */\r
+#define REG_GMAC_JR (*(RoReg*)0x4003418CU) /**< \brief (GMAC) Jabbers Received Register */\r
+#define REG_GMAC_FCSE (*(RoReg*)0x40034190U) /**< \brief (GMAC) Frame Check Sequence Errors Register */\r
+#define REG_GMAC_LFFE (*(RoReg*)0x40034194U) /**< \brief (GMAC) Length Field Frame Errors Register */\r
+#define REG_GMAC_RSE (*(RoReg*)0x40034198U) /**< \brief (GMAC) Receive Symbol Errors Register */\r
+#define REG_GMAC_AE (*(RoReg*)0x4003419CU) /**< \brief (GMAC) Alignment Errors Register */\r
+#define REG_GMAC_RRE (*(RoReg*)0x400341A0U) /**< \brief (GMAC) Receive Resource Errors Register */\r
+#define REG_GMAC_ROE (*(RoReg*)0x400341A4U) /**< \brief (GMAC) Receive Overrun Register */\r
+#define REG_GMAC_IHCE (*(RoReg*)0x400341A8U) /**< \brief (GMAC) IP Header Checksum Errors Register */\r
+#define REG_GMAC_TCE (*(RoReg*)0x400341ACU) /**< \brief (GMAC) TCP Checksum Errors Register */\r
+#define REG_GMAC_UCE (*(RoReg*)0x400341B0U) /**< \brief (GMAC) UDP Checksum Errors Register */\r
+#define REG_GMAC_TSSS (*(RwReg*)0x400341C8U) /**< \brief (GMAC) 1588 Timer Sync Strobe Seconds Register */\r
+#define REG_GMAC_TSSN (*(RwReg*)0x400341CCU) /**< \brief (GMAC) 1588 Timer Sync Strobe Nanoseconds Register */\r
+#define REG_GMAC_TS (*(RwReg*)0x400341D0U) /**< \brief (GMAC) 1588 Timer Seconds Register */\r
+#define REG_GMAC_TN (*(RwReg*)0x400341D4U) /**< \brief (GMAC) 1588 Timer Nanoseconds Register */\r
+#define REG_GMAC_TA (*(WoReg*)0x400341D8U) /**< \brief (GMAC) 1588 Timer Adjust Register */\r
+#define REG_GMAC_TI (*(RwReg*)0x400341DCU) /**< \brief (GMAC) 1588 Timer Increment Register */\r
+#define REG_GMAC_EFTS (*(RoReg*)0x400341E0U) /**< \brief (GMAC) PTP Event Frame Transmitted Seconds */\r
+#define REG_GMAC_EFTN (*(RoReg*)0x400341E4U) /**< \brief (GMAC) PTP Event Frame Transmitted Nanoseconds */\r
+#define REG_GMAC_EFRS (*(RoReg*)0x400341E8U) /**< \brief (GMAC) PTP Event Frame Received Seconds */\r
+#define REG_GMAC_EFRN (*(RoReg*)0x400341ECU) /**< \brief (GMAC) PTP Event Frame Received Nanoseconds */\r
+#define REG_GMAC_PEFTS (*(RoReg*)0x400341F0U) /**< \brief (GMAC) PTP Peer Event Frame Transmitted Seconds */\r
+#define REG_GMAC_PEFTN (*(RoReg*)0x400341F4U) /**< \brief (GMAC) PTP Peer Event Frame Transmitted Nanoseconds */\r
+#define REG_GMAC_PEFRS (*(RoReg*)0x400341F8U) /**< \brief (GMAC) PTP Peer Event Frame Received Seconds */\r
+#define REG_GMAC_PEFRN (*(RoReg*)0x400341FCU) /**< \brief (GMAC) PTP Peer Event Frame Received Nanoseconds */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM4E_GMAC_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4E_GPBR_INSTANCE_\r
+#define _SAM4E_GPBR_INSTANCE_\r
+\r
+/* ========== Register definition for GPBR peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_GPBR_GPBR (0x400E1890U) /**< \brief (GPBR) General Purpose Backup Register */\r
+#else\r
+#define REG_GPBR_GPBR (*(RwReg*)0x400E1890U) /**< \brief (GPBR) General Purpose Backup Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM4E_GPBR_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4E_HSMCI_INSTANCE_\r
+#define _SAM4E_HSMCI_INSTANCE_\r
+\r
+/* ========== Register definition for HSMCI peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_HSMCI_CR (0x40080000U) /**< \brief (HSMCI) Control Register */\r
+#define REG_HSMCI_MR (0x40080004U) /**< \brief (HSMCI) Mode Register */\r
+#define REG_HSMCI_DTOR (0x40080008U) /**< \brief (HSMCI) Data Timeout Register */\r
+#define REG_HSMCI_SDCR (0x4008000CU) /**< \brief (HSMCI) SD/SDIO Card Register */\r
+#define REG_HSMCI_ARGR (0x40080010U) /**< \brief (HSMCI) Argument Register */\r
+#define REG_HSMCI_CMDR (0x40080014U) /**< \brief (HSMCI) Command Register */\r
+#define REG_HSMCI_BLKR (0x40080018U) /**< \brief (HSMCI) Block Register */\r
+#define REG_HSMCI_CSTOR (0x4008001CU) /**< \brief (HSMCI) Completion Signal Timeout Register */\r
+#define REG_HSMCI_RSPR (0x40080020U) /**< \brief (HSMCI) Response Register */\r
+#define REG_HSMCI_RDR (0x40080030U) /**< \brief (HSMCI) Receive Data Register */\r
+#define REG_HSMCI_TDR (0x40080034U) /**< \brief (HSMCI) Transmit Data Register */\r
+#define REG_HSMCI_SR (0x40080040U) /**< \brief (HSMCI) Status Register */\r
+#define REG_HSMCI_IER (0x40080044U) /**< \brief (HSMCI) Interrupt Enable Register */\r
+#define REG_HSMCI_IDR (0x40080048U) /**< \brief (HSMCI) Interrupt Disable Register */\r
+#define REG_HSMCI_IMR (0x4008004CU) /**< \brief (HSMCI) Interrupt Mask Register */\r
+#define REG_HSMCI_CFG (0x40080054U) /**< \brief (HSMCI) Configuration Register */\r
+#define REG_HSMCI_WPMR (0x400800E4U) /**< \brief (HSMCI) Write Protection Mode Register */\r
+#define REG_HSMCI_WPSR (0x400800E8U) /**< \brief (HSMCI) Write Protection Status Register */\r
+#define REG_HSMCI_RPR (0x40080100U) /**< \brief (HSMCI) Receive Pointer Register */\r
+#define REG_HSMCI_RCR (0x40080104U) /**< \brief (HSMCI) Receive Counter Register */\r
+#define REG_HSMCI_TPR (0x40080108U) /**< \brief (HSMCI) Transmit Pointer Register */\r
+#define REG_HSMCI_TCR (0x4008010CU) /**< \brief (HSMCI) Transmit Counter Register */\r
+#define REG_HSMCI_RNPR (0x40080110U) /**< \brief (HSMCI) Receive Next Pointer Register */\r
+#define REG_HSMCI_RNCR (0x40080114U) /**< \brief (HSMCI) Receive Next Counter Register */\r
+#define REG_HSMCI_TNPR (0x40080118U) /**< \brief (HSMCI) Transmit Next Pointer Register */\r
+#define REG_HSMCI_TNCR (0x4008011CU) /**< \brief (HSMCI) Transmit Next Counter Register */\r
+#define REG_HSMCI_PTCR (0x40080120U) /**< \brief (HSMCI) Transfer Control Register */\r
+#define REG_HSMCI_PTSR (0x40080124U) /**< \brief (HSMCI) Transfer Status Register */\r
+#define REG_HSMCI_FIFO (0x40080200U) /**< \brief (HSMCI) FIFO Memory Aperture0 */\r
+#else\r
+#define REG_HSMCI_CR (*(WoReg*)0x40080000U) /**< \brief (HSMCI) Control Register */\r
+#define REG_HSMCI_MR (*(RwReg*)0x40080004U) /**< \brief (HSMCI) Mode Register */\r
+#define REG_HSMCI_DTOR (*(RwReg*)0x40080008U) /**< \brief (HSMCI) Data Timeout Register */\r
+#define REG_HSMCI_SDCR (*(RwReg*)0x4008000CU) /**< \brief (HSMCI) SD/SDIO Card Register */\r
+#define REG_HSMCI_ARGR (*(RwReg*)0x40080010U) /**< \brief (HSMCI) Argument Register */\r
+#define REG_HSMCI_CMDR (*(WoReg*)0x40080014U) /**< \brief (HSMCI) Command Register */\r
+#define REG_HSMCI_BLKR (*(RwReg*)0x40080018U) /**< \brief (HSMCI) Block Register */\r
+#define REG_HSMCI_CSTOR (*(RwReg*)0x4008001CU) /**< \brief (HSMCI) Completion Signal Timeout Register */\r
+#define REG_HSMCI_RSPR (*(RoReg*)0x40080020U) /**< \brief (HSMCI) Response Register */\r
+#define REG_HSMCI_RDR (*(RoReg*)0x40080030U) /**< \brief (HSMCI) Receive Data Register */\r
+#define REG_HSMCI_TDR (*(WoReg*)0x40080034U) /**< \brief (HSMCI) Transmit Data Register */\r
+#define REG_HSMCI_SR (*(RoReg*)0x40080040U) /**< \brief (HSMCI) Status Register */\r
+#define REG_HSMCI_IER (*(WoReg*)0x40080044U) /**< \brief (HSMCI) Interrupt Enable Register */\r
+#define REG_HSMCI_IDR (*(WoReg*)0x40080048U) /**< \brief (HSMCI) Interrupt Disable Register */\r
+#define REG_HSMCI_IMR (*(RoReg*)0x4008004CU) /**< \brief (HSMCI) Interrupt Mask Register */\r
+#define REG_HSMCI_CFG (*(RwReg*)0x40080054U) /**< \brief (HSMCI) Configuration Register */\r
+#define REG_HSMCI_WPMR (*(RwReg*)0x400800E4U) /**< \brief (HSMCI) Write Protection Mode Register */\r
+#define REG_HSMCI_WPSR (*(RoReg*)0x400800E8U) /**< \brief (HSMCI) Write Protection Status Register */\r
+#define REG_HSMCI_RPR (*(RwReg*)0x40080100U) /**< \brief (HSMCI) Receive Pointer Register */\r
+#define REG_HSMCI_RCR (*(RwReg*)0x40080104U) /**< \brief (HSMCI) Receive Counter Register */\r
+#define REG_HSMCI_TPR (*(RwReg*)0x40080108U) /**< \brief (HSMCI) Transmit Pointer Register */\r
+#define REG_HSMCI_TCR (*(RwReg*)0x4008010CU) /**< \brief (HSMCI) Transmit Counter Register */\r
+#define REG_HSMCI_RNPR (*(RwReg*)0x40080110U) /**< \brief (HSMCI) Receive Next Pointer Register */\r
+#define REG_HSMCI_RNCR (*(RwReg*)0x40080114U) /**< \brief (HSMCI) Receive Next Counter Register */\r
+#define REG_HSMCI_TNPR (*(RwReg*)0x40080118U) /**< \brief (HSMCI) Transmit Next Pointer Register */\r
+#define REG_HSMCI_TNCR (*(RwReg*)0x4008011CU) /**< \brief (HSMCI) Transmit Next Counter Register */\r
+#define REG_HSMCI_PTCR (*(WoReg*)0x40080120U) /**< \brief (HSMCI) Transfer Control Register */\r
+#define REG_HSMCI_PTSR (*(RoReg*)0x40080124U) /**< \brief (HSMCI) Transfer Status Register */\r
+#define REG_HSMCI_FIFO (*(RwReg*)0x40080200U) /**< \brief (HSMCI) FIFO Memory Aperture0 */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM4E_HSMCI_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4E_MATRIX_INSTANCE_\r
+#define _SAM4E_MATRIX_INSTANCE_\r
+\r
+/* ========== Register definition for MATRIX peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_MATRIX_MCFG (0x400E0200U) /**< \brief (MATRIX) Master Configuration Register */\r
+#define REG_MATRIX_SCFG (0x400E0240U) /**< \brief (MATRIX) Slave Configuration Register */\r
+#define REG_MATRIX_PRAS0 (0x400E0280U) /**< \brief (MATRIX) Priority Register A for Slave 0 */\r
+#define REG_MATRIX_PRAS1 (0x400E0288U) /**< \brief (MATRIX) Priority Register A for Slave 1 */\r
+#define REG_MATRIX_PRAS2 (0x400E0290U) /**< \brief (MATRIX) Priority Register A for Slave 2 */\r
+#define REG_MATRIX_PRAS3 (0x400E0298U) /**< \brief (MATRIX) Priority Register A for Slave 3 */\r
+#define REG_MATRIX_PRAS4 (0x400E02A0U) /**< \brief (MATRIX) Priority Register A for Slave 4 */\r
+#define REG_MATRIX_PRAS5 (0x400E02A8U) /**< \brief (MATRIX) Priority Register A for Slave 5 */\r
+#define REG_MATRIX_MRCR (0x400E0300U) /**< \brief (MATRIX) Master Remap Control Register */\r
+#define REG_CCFG_SYSIO (0x400E0314U) /**< \brief (MATRIX) System I/O Configuration Register */\r
+#define REG_CCFG_SMCNFCS (0x400E0324U) /**< \brief (MATRIX) SMC NAND Flash Chip Select Configuration Register */\r
+#define REG_MATRIX_WPMR (0x400E03E4U) /**< \brief (MATRIX) Write Protect Mode Register */\r
+#define REG_MATRIX_WPSR (0x400E03E8U) /**< \brief (MATRIX) Write Protect Status Register */\r
+#else\r
+#define REG_MATRIX_MCFG (*(RwReg*)0x400E0200U) /**< \brief (MATRIX) Master Configuration Register */\r
+#define REG_MATRIX_SCFG (*(RwReg*)0x400E0240U) /**< \brief (MATRIX) Slave Configuration Register */\r
+#define REG_MATRIX_PRAS0 (*(RwReg*)0x400E0280U) /**< \brief (MATRIX) Priority Register A for Slave 0 */\r
+#define REG_MATRIX_PRAS1 (*(RwReg*)0x400E0288U) /**< \brief (MATRIX) Priority Register A for Slave 1 */\r
+#define REG_MATRIX_PRAS2 (*(RwReg*)0x400E0290U) /**< \brief (MATRIX) Priority Register A for Slave 2 */\r
+#define REG_MATRIX_PRAS3 (*(RwReg*)0x400E0298U) /**< \brief (MATRIX) Priority Register A for Slave 3 */\r
+#define REG_MATRIX_PRAS4 (*(RwReg*)0x400E02A0U) /**< \brief (MATRIX) Priority Register A for Slave 4 */\r
+#define REG_MATRIX_PRAS5 (*(RwReg*)0x400E02A8U) /**< \brief (MATRIX) Priority Register A for Slave 5 */\r
+#define REG_MATRIX_MRCR (*(RwReg*)0x400E0300U) /**< \brief (MATRIX) Master Remap Control Register */\r
+#define REG_CCFG_SYSIO (*(RwReg*)0x400E0314U) /**< \brief (MATRIX) System I/O Configuration Register */\r
+#define REG_CCFG_SMCNFCS (*(RwReg*)0x400E0324U) /**< \brief (MATRIX) SMC NAND Flash Chip Select Configuration Register */\r
+#define REG_MATRIX_WPMR (*(RwReg*)0x400E03E4U) /**< \brief (MATRIX) Write Protect Mode Register */\r
+#define REG_MATRIX_WPSR (*(RoReg*)0x400E03E8U) /**< \brief (MATRIX) Write Protect Status Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM4E_MATRIX_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4E_PIOA_INSTANCE_\r
+#define _SAM4E_PIOA_INSTANCE_\r
+\r
+/* ========== Register definition for PIOA peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_PIOA_PER (0x400E0E00U) /**< \brief (PIOA) PIO Enable Register */\r
+#define REG_PIOA_PDR (0x400E0E04U) /**< \brief (PIOA) PIO Disable Register */\r
+#define REG_PIOA_PSR (0x400E0E08U) /**< \brief (PIOA) PIO Status Register */\r
+#define REG_PIOA_OER (0x400E0E10U) /**< \brief (PIOA) Output Enable Register */\r
+#define REG_PIOA_ODR (0x400E0E14U) /**< \brief (PIOA) Output Disable Register */\r
+#define REG_PIOA_OSR (0x400E0E18U) /**< \brief (PIOA) Output Status Register */\r
+#define REG_PIOA_IFER (0x400E0E20U) /**< \brief (PIOA) Glitch Input Filter Enable Register */\r
+#define REG_PIOA_IFDR (0x400E0E24U) /**< \brief (PIOA) Glitch Input Filter Disable Register */\r
+#define REG_PIOA_IFSR (0x400E0E28U) /**< \brief (PIOA) Glitch Input Filter Status Register */\r
+#define REG_PIOA_SODR (0x400E0E30U) /**< \brief (PIOA) Set Output Data Register */\r
+#define REG_PIOA_CODR (0x400E0E34U) /**< \brief (PIOA) Clear Output Data Register */\r
+#define REG_PIOA_ODSR (0x400E0E38U) /**< \brief (PIOA) Output Data Status Register */\r
+#define REG_PIOA_PDSR (0x400E0E3CU) /**< \brief (PIOA) Pin Data Status Register */\r
+#define REG_PIOA_IER (0x400E0E40U) /**< \brief (PIOA) Interrupt Enable Register */\r
+#define REG_PIOA_IDR (0x400E0E44U) /**< \brief (PIOA) Interrupt Disable Register */\r
+#define REG_PIOA_IMR (0x400E0E48U) /**< \brief (PIOA) Interrupt Mask Register */\r
+#define REG_PIOA_ISR (0x400E0E4CU) /**< \brief (PIOA) Interrupt Status Register */\r
+#define REG_PIOA_MDER (0x400E0E50U) /**< \brief (PIOA) Multi-driver Enable Register */\r
+#define REG_PIOA_MDDR (0x400E0E54U) /**< \brief (PIOA) Multi-driver Disable Register */\r
+#define REG_PIOA_MDSR (0x400E0E58U) /**< \brief (PIOA) Multi-driver Status Register */\r
+#define REG_PIOA_PUDR (0x400E0E60U) /**< \brief (PIOA) Pull-up Disable Register */\r
+#define REG_PIOA_PUER (0x400E0E64U) /**< \brief (PIOA) Pull-up Enable Register */\r
+#define REG_PIOA_PUSR (0x400E0E68U) /**< \brief (PIOA) Pad Pull-up Status Register */\r
+#define REG_PIOA_ABCDSR (0x400E0E70U) /**< \brief (PIOA) Peripheral Select Register */\r
+#define REG_PIOA_IFSCDR (0x400E0E80U) /**< \brief (PIOA) Input Filter Slow Clock Disable Register */\r
+#define REG_PIOA_IFSCER (0x400E0E84U) /**< \brief (PIOA) Input Filter Slow Clock Enable Register */\r
+#define REG_PIOA_IFSCSR (0x400E0E88U) /**< \brief (PIOA) Input Filter Slow Clock Status Register */\r
+#define REG_PIOA_SCDR (0x400E0E8CU) /**< \brief (PIOA) Slow Clock Divider Debouncing Register */\r
+#define REG_PIOA_PPDDR (0x400E0E90U) /**< \brief (PIOA) Pad Pull-down Disable Register */\r
+#define REG_PIOA_PPDER (0x400E0E94U) /**< \brief (PIOA) Pad Pull-down Enable Register */\r
+#define REG_PIOA_PPDSR (0x400E0E98U) /**< \brief (PIOA) Pad Pull-down Status Register */\r
+#define REG_PIOA_OWER (0x400E0EA0U) /**< \brief (PIOA) Output Write Enable */\r
+#define REG_PIOA_OWDR (0x400E0EA4U) /**< \brief (PIOA) Output Write Disable */\r
+#define REG_PIOA_OWSR (0x400E0EA8U) /**< \brief (PIOA) Output Write Status Register */\r
+#define REG_PIOA_AIMER (0x400E0EB0U) /**< \brief (PIOA) Additional Interrupt Modes Enable Register */\r
+#define REG_PIOA_AIMDR (0x400E0EB4U) /**< \brief (PIOA) Additional Interrupt Modes Disables Register */\r
+#define REG_PIOA_AIMMR (0x400E0EB8U) /**< \brief (PIOA) Additional Interrupt Modes Mask Register */\r
+#define REG_PIOA_ESR (0x400E0EC0U) /**< \brief (PIOA) Edge Select Register */\r
+#define REG_PIOA_LSR (0x400E0EC4U) /**< \brief (PIOA) Level Select Register */\r
+#define REG_PIOA_ELSR (0x400E0EC8U) /**< \brief (PIOA) Edge/Level Status Register */\r
+#define REG_PIOA_FELLSR (0x400E0ED0U) /**< \brief (PIOA) Falling Edge/Low Level Select Register */\r
+#define REG_PIOA_REHLSR (0x400E0ED4U) /**< \brief (PIOA) Rising Edge/ High Level Select Register */\r
+#define REG_PIOA_FRLHSR (0x400E0ED8U) /**< \brief (PIOA) Fall/Rise - Low/High Status Register */\r
+#define REG_PIOA_LOCKSR (0x400E0EE0U) /**< \brief (PIOA) Lock Status */\r
+#define REG_PIOA_WPMR (0x400E0EE4U) /**< \brief (PIOA) Write Protect Mode Register */\r
+#define REG_PIOA_WPSR (0x400E0EE8U) /**< \brief (PIOA) Write Protect Status Register */\r
+#define REG_PIOA_SCHMITT (0x400E0F00U) /**< \brief (PIOA) Schmitt Trigger Register */\r
+#define REG_PIOA_DELAYR (0x400E0F10U) /**< \brief (PIOA) IO Delay Register */\r
+#define REG_PIOA_PCMR (0x400E0F50U) /**< \brief (PIOA) Parallel Capture Mode Register */\r
+#define REG_PIOA_PCIER (0x400E0F54U) /**< \brief (PIOA) Parallel Capture Interrupt Enable Register */\r
+#define REG_PIOA_PCIDR (0x400E0F58U) /**< \brief (PIOA) Parallel Capture Interrupt Disable Register */\r
+#define REG_PIOA_PCIMR (0x400E0F5CU) /**< \brief (PIOA) Parallel Capture Interrupt Mask Register */\r
+#define REG_PIOA_PCISR (0x400E0F60U) /**< \brief (PIOA) Parallel Capture Interrupt Status Register */\r
+#define REG_PIOA_PCRHR (0x400E0F64U) /**< \brief (PIOA) Parallel Capture Reception Holding Register */\r
+#define REG_PIOA_RPR (0x400E0F68U) /**< \brief (PIOA) Receive Pointer Register */\r
+#define REG_PIOA_RCR (0x400E0F6CU) /**< \brief (PIOA) Receive Counter Register */\r
+#define REG_PIOA_RNPR (0x400E0F78U) /**< \brief (PIOA) Receive Next Pointer Register */\r
+#define REG_PIOA_RNCR (0x400E0F7CU) /**< \brief (PIOA) Receive Next Counter Register */\r
+#define REG_PIOA_PTCR (0x400E0F88U) /**< \brief (PIOA) Transfer Control Register */\r
+#define REG_PIOA_PTSR (0x400E0F8CU) /**< \brief (PIOA) Transfer Status Register */\r
+#else\r
+#define REG_PIOA_PER (*(WoReg*)0x400E0E00U) /**< \brief (PIOA) PIO Enable Register */\r
+#define REG_PIOA_PDR (*(WoReg*)0x400E0E04U) /**< \brief (PIOA) PIO Disable Register */\r
+#define REG_PIOA_PSR (*(RoReg*)0x400E0E08U) /**< \brief (PIOA) PIO Status Register */\r
+#define REG_PIOA_OER (*(WoReg*)0x400E0E10U) /**< \brief (PIOA) Output Enable Register */\r
+#define REG_PIOA_ODR (*(WoReg*)0x400E0E14U) /**< \brief (PIOA) Output Disable Register */\r
+#define REG_PIOA_OSR (*(RoReg*)0x400E0E18U) /**< \brief (PIOA) Output Status Register */\r
+#define REG_PIOA_IFER (*(WoReg*)0x400E0E20U) /**< \brief (PIOA) Glitch Input Filter Enable Register */\r
+#define REG_PIOA_IFDR (*(WoReg*)0x400E0E24U) /**< \brief (PIOA) Glitch Input Filter Disable Register */\r
+#define REG_PIOA_IFSR (*(RoReg*)0x400E0E28U) /**< \brief (PIOA) Glitch Input Filter Status Register */\r
+#define REG_PIOA_SODR (*(WoReg*)0x400E0E30U) /**< \brief (PIOA) Set Output Data Register */\r
+#define REG_PIOA_CODR (*(WoReg*)0x400E0E34U) /**< \brief (PIOA) Clear Output Data Register */\r
+#define REG_PIOA_ODSR (*(RwReg*)0x400E0E38U) /**< \brief (PIOA) Output Data Status Register */\r
+#define REG_PIOA_PDSR (*(RoReg*)0x400E0E3CU) /**< \brief (PIOA) Pin Data Status Register */\r
+#define REG_PIOA_IER (*(WoReg*)0x400E0E40U) /**< \brief (PIOA) Interrupt Enable Register */\r
+#define REG_PIOA_IDR (*(WoReg*)0x400E0E44U) /**< \brief (PIOA) Interrupt Disable Register */\r
+#define REG_PIOA_IMR (*(RoReg*)0x400E0E48U) /**< \brief (PIOA) Interrupt Mask Register */\r
+#define REG_PIOA_ISR (*(RoReg*)0x400E0E4CU) /**< \brief (PIOA) Interrupt Status Register */\r
+#define REG_PIOA_MDER (*(WoReg*)0x400E0E50U) /**< \brief (PIOA) Multi-driver Enable Register */\r
+#define REG_PIOA_MDDR (*(WoReg*)0x400E0E54U) /**< \brief (PIOA) Multi-driver Disable Register */\r
+#define REG_PIOA_MDSR (*(RoReg*)0x400E0E58U) /**< \brief (PIOA) Multi-driver Status Register */\r
+#define REG_PIOA_PUDR (*(WoReg*)0x400E0E60U) /**< \brief (PIOA) Pull-up Disable Register */\r
+#define REG_PIOA_PUER (*(WoReg*)0x400E0E64U) /**< \brief (PIOA) Pull-up Enable Register */\r
+#define REG_PIOA_PUSR (*(RoReg*)0x400E0E68U) /**< \brief (PIOA) Pad Pull-up Status Register */\r
+#define REG_PIOA_ABCDSR (*(RwReg*)0x400E0E70U) /**< \brief (PIOA) Peripheral Select Register */\r
+#define REG_PIOA_IFSCDR (*(WoReg*)0x400E0E80U) /**< \brief (PIOA) Input Filter Slow Clock Disable Register */\r
+#define REG_PIOA_IFSCER (*(WoReg*)0x400E0E84U) /**< \brief (PIOA) Input Filter Slow Clock Enable Register */\r
+#define REG_PIOA_IFSCSR (*(RoReg*)0x400E0E88U) /**< \brief (PIOA) Input Filter Slow Clock Status Register */\r
+#define REG_PIOA_SCDR (*(RwReg*)0x400E0E8CU) /**< \brief (PIOA) Slow Clock Divider Debouncing Register */\r
+#define REG_PIOA_PPDDR (*(WoReg*)0x400E0E90U) /**< \brief (PIOA) Pad Pull-down Disable Register */\r
+#define REG_PIOA_PPDER (*(WoReg*)0x400E0E94U) /**< \brief (PIOA) Pad Pull-down Enable Register */\r
+#define REG_PIOA_PPDSR (*(RoReg*)0x400E0E98U) /**< \brief (PIOA) Pad Pull-down Status Register */\r
+#define REG_PIOA_OWER (*(WoReg*)0x400E0EA0U) /**< \brief (PIOA) Output Write Enable */\r
+#define REG_PIOA_OWDR (*(WoReg*)0x400E0EA4U) /**< \brief (PIOA) Output Write Disable */\r
+#define REG_PIOA_OWSR (*(RoReg*)0x400E0EA8U) /**< \brief (PIOA) Output Write Status Register */\r
+#define REG_PIOA_AIMER (*(WoReg*)0x400E0EB0U) /**< \brief (PIOA) Additional Interrupt Modes Enable Register */\r
+#define REG_PIOA_AIMDR (*(WoReg*)0x400E0EB4U) /**< \brief (PIOA) Additional Interrupt Modes Disables Register */\r
+#define REG_PIOA_AIMMR (*(RoReg*)0x400E0EB8U) /**< \brief (PIOA) Additional Interrupt Modes Mask Register */\r
+#define REG_PIOA_ESR (*(WoReg*)0x400E0EC0U) /**< \brief (PIOA) Edge Select Register */\r
+#define REG_PIOA_LSR (*(WoReg*)0x400E0EC4U) /**< \brief (PIOA) Level Select Register */\r
+#define REG_PIOA_ELSR (*(RoReg*)0x400E0EC8U) /**< \brief (PIOA) Edge/Level Status Register */\r
+#define REG_PIOA_FELLSR (*(WoReg*)0x400E0ED0U) /**< \brief (PIOA) Falling Edge/Low Level Select Register */\r
+#define REG_PIOA_REHLSR (*(WoReg*)0x400E0ED4U) /**< \brief (PIOA) Rising Edge/ High Level Select Register */\r
+#define REG_PIOA_FRLHSR (*(RoReg*)0x400E0ED8U) /**< \brief (PIOA) Fall/Rise - Low/High Status Register */\r
+#define REG_PIOA_LOCKSR (*(RoReg*)0x400E0EE0U) /**< \brief (PIOA) Lock Status */\r
+#define REG_PIOA_WPMR (*(RwReg*)0x400E0EE4U) /**< \brief (PIOA) Write Protect Mode Register */\r
+#define REG_PIOA_WPSR (*(RoReg*)0x400E0EE8U) /**< \brief (PIOA) Write Protect Status Register */\r
+#define REG_PIOA_SCHMITT (*(RwReg*)0x400E0F00U) /**< \brief (PIOA) Schmitt Trigger Register */\r
+#define REG_PIOA_DELAYR (*(RwReg*)0x400E0F10U) /**< \brief (PIOA) IO Delay Register */\r
+#define REG_PIOA_PCMR (*(RwReg*)0x400E0F50U) /**< \brief (PIOA) Parallel Capture Mode Register */\r
+#define REG_PIOA_PCIER (*(WoReg*)0x400E0F54U) /**< \brief (PIOA) Parallel Capture Interrupt Enable Register */\r
+#define REG_PIOA_PCIDR (*(WoReg*)0x400E0F58U) /**< \brief (PIOA) Parallel Capture Interrupt Disable Register */\r
+#define REG_PIOA_PCIMR (*(RoReg*)0x400E0F5CU) /**< \brief (PIOA) Parallel Capture Interrupt Mask Register */\r
+#define REG_PIOA_PCISR (*(RoReg*)0x400E0F60U) /**< \brief (PIOA) Parallel Capture Interrupt Status Register */\r
+#define REG_PIOA_PCRHR (*(RoReg*)0x400E0F64U) /**< \brief (PIOA) Parallel Capture Reception Holding Register */\r
+#define REG_PIOA_RPR (*(RwReg*)0x400E0F68U) /**< \brief (PIOA) Receive Pointer Register */\r
+#define REG_PIOA_RCR (*(RwReg*)0x400E0F6CU) /**< \brief (PIOA) Receive Counter Register */\r
+#define REG_PIOA_RNPR (*(RwReg*)0x400E0F78U) /**< \brief (PIOA) Receive Next Pointer Register */\r
+#define REG_PIOA_RNCR (*(RwReg*)0x400E0F7CU) /**< \brief (PIOA) Receive Next Counter Register */\r
+#define REG_PIOA_PTCR (*(WoReg*)0x400E0F88U) /**< \brief (PIOA) Transfer Control Register */\r
+#define REG_PIOA_PTSR (*(RoReg*)0x400E0F8CU) /**< \brief (PIOA) Transfer Status Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM4E_PIOA_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4E_PIOB_INSTANCE_\r
+#define _SAM4E_PIOB_INSTANCE_\r
+\r
+/* ========== Register definition for PIOB peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_PIOB_PER (0x400E1000U) /**< \brief (PIOB) PIO Enable Register */\r
+#define REG_PIOB_PDR (0x400E1004U) /**< \brief (PIOB) PIO Disable Register */\r
+#define REG_PIOB_PSR (0x400E1008U) /**< \brief (PIOB) PIO Status Register */\r
+#define REG_PIOB_OER (0x400E1010U) /**< \brief (PIOB) Output Enable Register */\r
+#define REG_PIOB_ODR (0x400E1014U) /**< \brief (PIOB) Output Disable Register */\r
+#define REG_PIOB_OSR (0x400E1018U) /**< \brief (PIOB) Output Status Register */\r
+#define REG_PIOB_IFER (0x400E1020U) /**< \brief (PIOB) Glitch Input Filter Enable Register */\r
+#define REG_PIOB_IFDR (0x400E1024U) /**< \brief (PIOB) Glitch Input Filter Disable Register */\r
+#define REG_PIOB_IFSR (0x400E1028U) /**< \brief (PIOB) Glitch Input Filter Status Register */\r
+#define REG_PIOB_SODR (0x400E1030U) /**< \brief (PIOB) Set Output Data Register */\r
+#define REG_PIOB_CODR (0x400E1034U) /**< \brief (PIOB) Clear Output Data Register */\r
+#define REG_PIOB_ODSR (0x400E1038U) /**< \brief (PIOB) Output Data Status Register */\r
+#define REG_PIOB_PDSR (0x400E103CU) /**< \brief (PIOB) Pin Data Status Register */\r
+#define REG_PIOB_IER (0x400E1040U) /**< \brief (PIOB) Interrupt Enable Register */\r
+#define REG_PIOB_IDR (0x400E1044U) /**< \brief (PIOB) Interrupt Disable Register */\r
+#define REG_PIOB_IMR (0x400E1048U) /**< \brief (PIOB) Interrupt Mask Register */\r
+#define REG_PIOB_ISR (0x400E104CU) /**< \brief (PIOB) Interrupt Status Register */\r
+#define REG_PIOB_MDER (0x400E1050U) /**< \brief (PIOB) Multi-driver Enable Register */\r
+#define REG_PIOB_MDDR (0x400E1054U) /**< \brief (PIOB) Multi-driver Disable Register */\r
+#define REG_PIOB_MDSR (0x400E1058U) /**< \brief (PIOB) Multi-driver Status Register */\r
+#define REG_PIOB_PUDR (0x400E1060U) /**< \brief (PIOB) Pull-up Disable Register */\r
+#define REG_PIOB_PUER (0x400E1064U) /**< \brief (PIOB) Pull-up Enable Register */\r
+#define REG_PIOB_PUSR (0x400E1068U) /**< \brief (PIOB) Pad Pull-up Status Register */\r
+#define REG_PIOB_ABCDSR (0x400E1070U) /**< \brief (PIOB) Peripheral Select Register */\r
+#define REG_PIOB_IFSCDR (0x400E1080U) /**< \brief (PIOB) Input Filter Slow Clock Disable Register */\r
+#define REG_PIOB_IFSCER (0x400E1084U) /**< \brief (PIOB) Input Filter Slow Clock Enable Register */\r
+#define REG_PIOB_IFSCSR (0x400E1088U) /**< \brief (PIOB) Input Filter Slow Clock Status Register */\r
+#define REG_PIOB_SCDR (0x400E108CU) /**< \brief (PIOB) Slow Clock Divider Debouncing Register */\r
+#define REG_PIOB_PPDDR (0x400E1090U) /**< \brief (PIOB) Pad Pull-down Disable Register */\r
+#define REG_PIOB_PPDER (0x400E1094U) /**< \brief (PIOB) Pad Pull-down Enable Register */\r
+#define REG_PIOB_PPDSR (0x400E1098U) /**< \brief (PIOB) Pad Pull-down Status Register */\r
+#define REG_PIOB_OWER (0x400E10A0U) /**< \brief (PIOB) Output Write Enable */\r
+#define REG_PIOB_OWDR (0x400E10A4U) /**< \brief (PIOB) Output Write Disable */\r
+#define REG_PIOB_OWSR (0x400E10A8U) /**< \brief (PIOB) Output Write Status Register */\r
+#define REG_PIOB_AIMER (0x400E10B0U) /**< \brief (PIOB) Additional Interrupt Modes Enable Register */\r
+#define REG_PIOB_AIMDR (0x400E10B4U) /**< \brief (PIOB) Additional Interrupt Modes Disables Register */\r
+#define REG_PIOB_AIMMR (0x400E10B8U) /**< \brief (PIOB) Additional Interrupt Modes Mask Register */\r
+#define REG_PIOB_ESR (0x400E10C0U) /**< \brief (PIOB) Edge Select Register */\r
+#define REG_PIOB_LSR (0x400E10C4U) /**< \brief (PIOB) Level Select Register */\r
+#define REG_PIOB_ELSR (0x400E10C8U) /**< \brief (PIOB) Edge/Level Status Register */\r
+#define REG_PIOB_FELLSR (0x400E10D0U) /**< \brief (PIOB) Falling Edge/Low Level Select Register */\r
+#define REG_PIOB_REHLSR (0x400E10D4U) /**< \brief (PIOB) Rising Edge/ High Level Select Register */\r
+#define REG_PIOB_FRLHSR (0x400E10D8U) /**< \brief (PIOB) Fall/Rise - Low/High Status Register */\r
+#define REG_PIOB_LOCKSR (0x400E10E0U) /**< \brief (PIOB) Lock Status */\r
+#define REG_PIOB_WPMR (0x400E10E4U) /**< \brief (PIOB) Write Protect Mode Register */\r
+#define REG_PIOB_WPSR (0x400E10E8U) /**< \brief (PIOB) Write Protect Status Register */\r
+#define REG_PIOB_SCHMITT (0x400E1100U) /**< \brief (PIOB) Schmitt Trigger Register */\r
+#define REG_PIOB_DELAYR (0x400E1110U) /**< \brief (PIOB) IO Delay Register */\r
+#define REG_PIOB_PCMR (0x400E1150U) /**< \brief (PIOB) Parallel Capture Mode Register */\r
+#define REG_PIOB_PCIER (0x400E1154U) /**< \brief (PIOB) Parallel Capture Interrupt Enable Register */\r
+#define REG_PIOB_PCIDR (0x400E1158U) /**< \brief (PIOB) Parallel Capture Interrupt Disable Register */\r
+#define REG_PIOB_PCIMR (0x400E115CU) /**< \brief (PIOB) Parallel Capture Interrupt Mask Register */\r
+#define REG_PIOB_PCISR (0x400E1160U) /**< \brief (PIOB) Parallel Capture Interrupt Status Register */\r
+#define REG_PIOB_PCRHR (0x400E1164U) /**< \brief (PIOB) Parallel Capture Reception Holding Register */\r
+#else\r
+#define REG_PIOB_PER (*(WoReg*)0x400E1000U) /**< \brief (PIOB) PIO Enable Register */\r
+#define REG_PIOB_PDR (*(WoReg*)0x400E1004U) /**< \brief (PIOB) PIO Disable Register */\r
+#define REG_PIOB_PSR (*(RoReg*)0x400E1008U) /**< \brief (PIOB) PIO Status Register */\r
+#define REG_PIOB_OER (*(WoReg*)0x400E1010U) /**< \brief (PIOB) Output Enable Register */\r
+#define REG_PIOB_ODR (*(WoReg*)0x400E1014U) /**< \brief (PIOB) Output Disable Register */\r
+#define REG_PIOB_OSR (*(RoReg*)0x400E1018U) /**< \brief (PIOB) Output Status Register */\r
+#define REG_PIOB_IFER (*(WoReg*)0x400E1020U) /**< \brief (PIOB) Glitch Input Filter Enable Register */\r
+#define REG_PIOB_IFDR (*(WoReg*)0x400E1024U) /**< \brief (PIOB) Glitch Input Filter Disable Register */\r
+#define REG_PIOB_IFSR (*(RoReg*)0x400E1028U) /**< \brief (PIOB) Glitch Input Filter Status Register */\r
+#define REG_PIOB_SODR (*(WoReg*)0x400E1030U) /**< \brief (PIOB) Set Output Data Register */\r
+#define REG_PIOB_CODR (*(WoReg*)0x400E1034U) /**< \brief (PIOB) Clear Output Data Register */\r
+#define REG_PIOB_ODSR (*(RwReg*)0x400E1038U) /**< \brief (PIOB) Output Data Status Register */\r
+#define REG_PIOB_PDSR (*(RoReg*)0x400E103CU) /**< \brief (PIOB) Pin Data Status Register */\r
+#define REG_PIOB_IER (*(WoReg*)0x400E1040U) /**< \brief (PIOB) Interrupt Enable Register */\r
+#define REG_PIOB_IDR (*(WoReg*)0x400E1044U) /**< \brief (PIOB) Interrupt Disable Register */\r
+#define REG_PIOB_IMR (*(RoReg*)0x400E1048U) /**< \brief (PIOB) Interrupt Mask Register */\r
+#define REG_PIOB_ISR (*(RoReg*)0x400E104CU) /**< \brief (PIOB) Interrupt Status Register */\r
+#define REG_PIOB_MDER (*(WoReg*)0x400E1050U) /**< \brief (PIOB) Multi-driver Enable Register */\r
+#define REG_PIOB_MDDR (*(WoReg*)0x400E1054U) /**< \brief (PIOB) Multi-driver Disable Register */\r
+#define REG_PIOB_MDSR (*(RoReg*)0x400E1058U) /**< \brief (PIOB) Multi-driver Status Register */\r
+#define REG_PIOB_PUDR (*(WoReg*)0x400E1060U) /**< \brief (PIOB) Pull-up Disable Register */\r
+#define REG_PIOB_PUER (*(WoReg*)0x400E1064U) /**< \brief (PIOB) Pull-up Enable Register */\r
+#define REG_PIOB_PUSR (*(RoReg*)0x400E1068U) /**< \brief (PIOB) Pad Pull-up Status Register */\r
+#define REG_PIOB_ABCDSR (*(RwReg*)0x400E1070U) /**< \brief (PIOB) Peripheral Select Register */\r
+#define REG_PIOB_IFSCDR (*(WoReg*)0x400E1080U) /**< \brief (PIOB) Input Filter Slow Clock Disable Register */\r
+#define REG_PIOB_IFSCER (*(WoReg*)0x400E1084U) /**< \brief (PIOB) Input Filter Slow Clock Enable Register */\r
+#define REG_PIOB_IFSCSR (*(RoReg*)0x400E1088U) /**< \brief (PIOB) Input Filter Slow Clock Status Register */\r
+#define REG_PIOB_SCDR (*(RwReg*)0x400E108CU) /**< \brief (PIOB) Slow Clock Divider Debouncing Register */\r
+#define REG_PIOB_PPDDR (*(WoReg*)0x400E1090U) /**< \brief (PIOB) Pad Pull-down Disable Register */\r
+#define REG_PIOB_PPDER (*(WoReg*)0x400E1094U) /**< \brief (PIOB) Pad Pull-down Enable Register */\r
+#define REG_PIOB_PPDSR (*(RoReg*)0x400E1098U) /**< \brief (PIOB) Pad Pull-down Status Register */\r
+#define REG_PIOB_OWER (*(WoReg*)0x400E10A0U) /**< \brief (PIOB) Output Write Enable */\r
+#define REG_PIOB_OWDR (*(WoReg*)0x400E10A4U) /**< \brief (PIOB) Output Write Disable */\r
+#define REG_PIOB_OWSR (*(RoReg*)0x400E10A8U) /**< \brief (PIOB) Output Write Status Register */\r
+#define REG_PIOB_AIMER (*(WoReg*)0x400E10B0U) /**< \brief (PIOB) Additional Interrupt Modes Enable Register */\r
+#define REG_PIOB_AIMDR (*(WoReg*)0x400E10B4U) /**< \brief (PIOB) Additional Interrupt Modes Disables Register */\r
+#define REG_PIOB_AIMMR (*(RoReg*)0x400E10B8U) /**< \brief (PIOB) Additional Interrupt Modes Mask Register */\r
+#define REG_PIOB_ESR (*(WoReg*)0x400E10C0U) /**< \brief (PIOB) Edge Select Register */\r
+#define REG_PIOB_LSR (*(WoReg*)0x400E10C4U) /**< \brief (PIOB) Level Select Register */\r
+#define REG_PIOB_ELSR (*(RoReg*)0x400E10C8U) /**< \brief (PIOB) Edge/Level Status Register */\r
+#define REG_PIOB_FELLSR (*(WoReg*)0x400E10D0U) /**< \brief (PIOB) Falling Edge/Low Level Select Register */\r
+#define REG_PIOB_REHLSR (*(WoReg*)0x400E10D4U) /**< \brief (PIOB) Rising Edge/ High Level Select Register */\r
+#define REG_PIOB_FRLHSR (*(RoReg*)0x400E10D8U) /**< \brief (PIOB) Fall/Rise - Low/High Status Register */\r
+#define REG_PIOB_LOCKSR (*(RoReg*)0x400E10E0U) /**< \brief (PIOB) Lock Status */\r
+#define REG_PIOB_WPMR (*(RwReg*)0x400E10E4U) /**< \brief (PIOB) Write Protect Mode Register */\r
+#define REG_PIOB_WPSR (*(RoReg*)0x400E10E8U) /**< \brief (PIOB) Write Protect Status Register */\r
+#define REG_PIOB_SCHMITT (*(RwReg*)0x400E1100U) /**< \brief (PIOB) Schmitt Trigger Register */\r
+#define REG_PIOB_DELAYR (*(RwReg*)0x400E1110U) /**< \brief (PIOB) IO Delay Register */\r
+#define REG_PIOB_PCMR (*(RwReg*)0x400E1150U) /**< \brief (PIOB) Parallel Capture Mode Register */\r
+#define REG_PIOB_PCIER (*(WoReg*)0x400E1154U) /**< \brief (PIOB) Parallel Capture Interrupt Enable Register */\r
+#define REG_PIOB_PCIDR (*(WoReg*)0x400E1158U) /**< \brief (PIOB) Parallel Capture Interrupt Disable Register */\r
+#define REG_PIOB_PCIMR (*(RoReg*)0x400E115CU) /**< \brief (PIOB) Parallel Capture Interrupt Mask Register */\r
+#define REG_PIOB_PCISR (*(RoReg*)0x400E1160U) /**< \brief (PIOB) Parallel Capture Interrupt Status Register */\r
+#define REG_PIOB_PCRHR (*(RoReg*)0x400E1164U) /**< \brief (PIOB) Parallel Capture Reception Holding Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM4E_PIOB_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4E_PIOC_INSTANCE_\r
+#define _SAM4E_PIOC_INSTANCE_\r
+\r
+/* ========== Register definition for PIOC peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_PIOC_PER (0x400E1200U) /**< \brief (PIOC) PIO Enable Register */\r
+#define REG_PIOC_PDR (0x400E1204U) /**< \brief (PIOC) PIO Disable Register */\r
+#define REG_PIOC_PSR (0x400E1208U) /**< \brief (PIOC) PIO Status Register */\r
+#define REG_PIOC_OER (0x400E1210U) /**< \brief (PIOC) Output Enable Register */\r
+#define REG_PIOC_ODR (0x400E1214U) /**< \brief (PIOC) Output Disable Register */\r
+#define REG_PIOC_OSR (0x400E1218U) /**< \brief (PIOC) Output Status Register */\r
+#define REG_PIOC_IFER (0x400E1220U) /**< \brief (PIOC) Glitch Input Filter Enable Register */\r
+#define REG_PIOC_IFDR (0x400E1224U) /**< \brief (PIOC) Glitch Input Filter Disable Register */\r
+#define REG_PIOC_IFSR (0x400E1228U) /**< \brief (PIOC) Glitch Input Filter Status Register */\r
+#define REG_PIOC_SODR (0x400E1230U) /**< \brief (PIOC) Set Output Data Register */\r
+#define REG_PIOC_CODR (0x400E1234U) /**< \brief (PIOC) Clear Output Data Register */\r
+#define REG_PIOC_ODSR (0x400E1238U) /**< \brief (PIOC) Output Data Status Register */\r
+#define REG_PIOC_PDSR (0x400E123CU) /**< \brief (PIOC) Pin Data Status Register */\r
+#define REG_PIOC_IER (0x400E1240U) /**< \brief (PIOC) Interrupt Enable Register */\r
+#define REG_PIOC_IDR (0x400E1244U) /**< \brief (PIOC) Interrupt Disable Register */\r
+#define REG_PIOC_IMR (0x400E1248U) /**< \brief (PIOC) Interrupt Mask Register */\r
+#define REG_PIOC_ISR (0x400E124CU) /**< \brief (PIOC) Interrupt Status Register */\r
+#define REG_PIOC_MDER (0x400E1250U) /**< \brief (PIOC) Multi-driver Enable Register */\r
+#define REG_PIOC_MDDR (0x400E1254U) /**< \brief (PIOC) Multi-driver Disable Register */\r
+#define REG_PIOC_MDSR (0x400E1258U) /**< \brief (PIOC) Multi-driver Status Register */\r
+#define REG_PIOC_PUDR (0x400E1260U) /**< \brief (PIOC) Pull-up Disable Register */\r
+#define REG_PIOC_PUER (0x400E1264U) /**< \brief (PIOC) Pull-up Enable Register */\r
+#define REG_PIOC_PUSR (0x400E1268U) /**< \brief (PIOC) Pad Pull-up Status Register */\r
+#define REG_PIOC_ABCDSR (0x400E1270U) /**< \brief (PIOC) Peripheral Select Register */\r
+#define REG_PIOC_IFSCDR (0x400E1280U) /**< \brief (PIOC) Input Filter Slow Clock Disable Register */\r
+#define REG_PIOC_IFSCER (0x400E1284U) /**< \brief (PIOC) Input Filter Slow Clock Enable Register */\r
+#define REG_PIOC_IFSCSR (0x400E1288U) /**< \brief (PIOC) Input Filter Slow Clock Status Register */\r
+#define REG_PIOC_SCDR (0x400E128CU) /**< \brief (PIOC) Slow Clock Divider Debouncing Register */\r
+#define REG_PIOC_PPDDR (0x400E1290U) /**< \brief (PIOC) Pad Pull-down Disable Register */\r
+#define REG_PIOC_PPDER (0x400E1294U) /**< \brief (PIOC) Pad Pull-down Enable Register */\r
+#define REG_PIOC_PPDSR (0x400E1298U) /**< \brief (PIOC) Pad Pull-down Status Register */\r
+#define REG_PIOC_OWER (0x400E12A0U) /**< \brief (PIOC) Output Write Enable */\r
+#define REG_PIOC_OWDR (0x400E12A4U) /**< \brief (PIOC) Output Write Disable */\r
+#define REG_PIOC_OWSR (0x400E12A8U) /**< \brief (PIOC) Output Write Status Register */\r
+#define REG_PIOC_AIMER (0x400E12B0U) /**< \brief (PIOC) Additional Interrupt Modes Enable Register */\r
+#define REG_PIOC_AIMDR (0x400E12B4U) /**< \brief (PIOC) Additional Interrupt Modes Disables Register */\r
+#define REG_PIOC_AIMMR (0x400E12B8U) /**< \brief (PIOC) Additional Interrupt Modes Mask Register */\r
+#define REG_PIOC_ESR (0x400E12C0U) /**< \brief (PIOC) Edge Select Register */\r
+#define REG_PIOC_LSR (0x400E12C4U) /**< \brief (PIOC) Level Select Register */\r
+#define REG_PIOC_ELSR (0x400E12C8U) /**< \brief (PIOC) Edge/Level Status Register */\r
+#define REG_PIOC_FELLSR (0x400E12D0U) /**< \brief (PIOC) Falling Edge/Low Level Select Register */\r
+#define REG_PIOC_REHLSR (0x400E12D4U) /**< \brief (PIOC) Rising Edge/ High Level Select Register */\r
+#define REG_PIOC_FRLHSR (0x400E12D8U) /**< \brief (PIOC) Fall/Rise - Low/High Status Register */\r
+#define REG_PIOC_LOCKSR (0x400E12E0U) /**< \brief (PIOC) Lock Status */\r
+#define REG_PIOC_WPMR (0x400E12E4U) /**< \brief (PIOC) Write Protect Mode Register */\r
+#define REG_PIOC_WPSR (0x400E12E8U) /**< \brief (PIOC) Write Protect Status Register */\r
+#define REG_PIOC_SCHMITT (0x400E1300U) /**< \brief (PIOC) Schmitt Trigger Register */\r
+#define REG_PIOC_DELAYR (0x400E1310U) /**< \brief (PIOC) IO Delay Register */\r
+#define REG_PIOC_PCMR (0x400E1350U) /**< \brief (PIOC) Parallel Capture Mode Register */\r
+#define REG_PIOC_PCIER (0x400E1354U) /**< \brief (PIOC) Parallel Capture Interrupt Enable Register */\r
+#define REG_PIOC_PCIDR (0x400E1358U) /**< \brief (PIOC) Parallel Capture Interrupt Disable Register */\r
+#define REG_PIOC_PCIMR (0x400E135CU) /**< \brief (PIOC) Parallel Capture Interrupt Mask Register */\r
+#define REG_PIOC_PCISR (0x400E1360U) /**< \brief (PIOC) Parallel Capture Interrupt Status Register */\r
+#define REG_PIOC_PCRHR (0x400E1364U) /**< \brief (PIOC) Parallel Capture Reception Holding Register */\r
+#else\r
+#define REG_PIOC_PER (*(WoReg*)0x400E1200U) /**< \brief (PIOC) PIO Enable Register */\r
+#define REG_PIOC_PDR (*(WoReg*)0x400E1204U) /**< \brief (PIOC) PIO Disable Register */\r
+#define REG_PIOC_PSR (*(RoReg*)0x400E1208U) /**< \brief (PIOC) PIO Status Register */\r
+#define REG_PIOC_OER (*(WoReg*)0x400E1210U) /**< \brief (PIOC) Output Enable Register */\r
+#define REG_PIOC_ODR (*(WoReg*)0x400E1214U) /**< \brief (PIOC) Output Disable Register */\r
+#define REG_PIOC_OSR (*(RoReg*)0x400E1218U) /**< \brief (PIOC) Output Status Register */\r
+#define REG_PIOC_IFER (*(WoReg*)0x400E1220U) /**< \brief (PIOC) Glitch Input Filter Enable Register */\r
+#define REG_PIOC_IFDR (*(WoReg*)0x400E1224U) /**< \brief (PIOC) Glitch Input Filter Disable Register */\r
+#define REG_PIOC_IFSR (*(RoReg*)0x400E1228U) /**< \brief (PIOC) Glitch Input Filter Status Register */\r
+#define REG_PIOC_SODR (*(WoReg*)0x400E1230U) /**< \brief (PIOC) Set Output Data Register */\r
+#define REG_PIOC_CODR (*(WoReg*)0x400E1234U) /**< \brief (PIOC) Clear Output Data Register */\r
+#define REG_PIOC_ODSR (*(RwReg*)0x400E1238U) /**< \brief (PIOC) Output Data Status Register */\r
+#define REG_PIOC_PDSR (*(RoReg*)0x400E123CU) /**< \brief (PIOC) Pin Data Status Register */\r
+#define REG_PIOC_IER (*(WoReg*)0x400E1240U) /**< \brief (PIOC) Interrupt Enable Register */\r
+#define REG_PIOC_IDR (*(WoReg*)0x400E1244U) /**< \brief (PIOC) Interrupt Disable Register */\r
+#define REG_PIOC_IMR (*(RoReg*)0x400E1248U) /**< \brief (PIOC) Interrupt Mask Register */\r
+#define REG_PIOC_ISR (*(RoReg*)0x400E124CU) /**< \brief (PIOC) Interrupt Status Register */\r
+#define REG_PIOC_MDER (*(WoReg*)0x400E1250U) /**< \brief (PIOC) Multi-driver Enable Register */\r
+#define REG_PIOC_MDDR (*(WoReg*)0x400E1254U) /**< \brief (PIOC) Multi-driver Disable Register */\r
+#define REG_PIOC_MDSR (*(RoReg*)0x400E1258U) /**< \brief (PIOC) Multi-driver Status Register */\r
+#define REG_PIOC_PUDR (*(WoReg*)0x400E1260U) /**< \brief (PIOC) Pull-up Disable Register */\r
+#define REG_PIOC_PUER (*(WoReg*)0x400E1264U) /**< \brief (PIOC) Pull-up Enable Register */\r
+#define REG_PIOC_PUSR (*(RoReg*)0x400E1268U) /**< \brief (PIOC) Pad Pull-up Status Register */\r
+#define REG_PIOC_ABCDSR (*(RwReg*)0x400E1270U) /**< \brief (PIOC) Peripheral Select Register */\r
+#define REG_PIOC_IFSCDR (*(WoReg*)0x400E1280U) /**< \brief (PIOC) Input Filter Slow Clock Disable Register */\r
+#define REG_PIOC_IFSCER (*(WoReg*)0x400E1284U) /**< \brief (PIOC) Input Filter Slow Clock Enable Register */\r
+#define REG_PIOC_IFSCSR (*(RoReg*)0x400E1288U) /**< \brief (PIOC) Input Filter Slow Clock Status Register */\r
+#define REG_PIOC_SCDR (*(RwReg*)0x400E128CU) /**< \brief (PIOC) Slow Clock Divider Debouncing Register */\r
+#define REG_PIOC_PPDDR (*(WoReg*)0x400E1290U) /**< \brief (PIOC) Pad Pull-down Disable Register */\r
+#define REG_PIOC_PPDER (*(WoReg*)0x400E1294U) /**< \brief (PIOC) Pad Pull-down Enable Register */\r
+#define REG_PIOC_PPDSR (*(RoReg*)0x400E1298U) /**< \brief (PIOC) Pad Pull-down Status Register */\r
+#define REG_PIOC_OWER (*(WoReg*)0x400E12A0U) /**< \brief (PIOC) Output Write Enable */\r
+#define REG_PIOC_OWDR (*(WoReg*)0x400E12A4U) /**< \brief (PIOC) Output Write Disable */\r
+#define REG_PIOC_OWSR (*(RoReg*)0x400E12A8U) /**< \brief (PIOC) Output Write Status Register */\r
+#define REG_PIOC_AIMER (*(WoReg*)0x400E12B0U) /**< \brief (PIOC) Additional Interrupt Modes Enable Register */\r
+#define REG_PIOC_AIMDR (*(WoReg*)0x400E12B4U) /**< \brief (PIOC) Additional Interrupt Modes Disables Register */\r
+#define REG_PIOC_AIMMR (*(RoReg*)0x400E12B8U) /**< \brief (PIOC) Additional Interrupt Modes Mask Register */\r
+#define REG_PIOC_ESR (*(WoReg*)0x400E12C0U) /**< \brief (PIOC) Edge Select Register */\r
+#define REG_PIOC_LSR (*(WoReg*)0x400E12C4U) /**< \brief (PIOC) Level Select Register */\r
+#define REG_PIOC_ELSR (*(RoReg*)0x400E12C8U) /**< \brief (PIOC) Edge/Level Status Register */\r
+#define REG_PIOC_FELLSR (*(WoReg*)0x400E12D0U) /**< \brief (PIOC) Falling Edge/Low Level Select Register */\r
+#define REG_PIOC_REHLSR (*(WoReg*)0x400E12D4U) /**< \brief (PIOC) Rising Edge/ High Level Select Register */\r
+#define REG_PIOC_FRLHSR (*(RoReg*)0x400E12D8U) /**< \brief (PIOC) Fall/Rise - Low/High Status Register */\r
+#define REG_PIOC_LOCKSR (*(RoReg*)0x400E12E0U) /**< \brief (PIOC) Lock Status */\r
+#define REG_PIOC_WPMR (*(RwReg*)0x400E12E4U) /**< \brief (PIOC) Write Protect Mode Register */\r
+#define REG_PIOC_WPSR (*(RoReg*)0x400E12E8U) /**< \brief (PIOC) Write Protect Status Register */\r
+#define REG_PIOC_SCHMITT (*(RwReg*)0x400E1300U) /**< \brief (PIOC) Schmitt Trigger Register */\r
+#define REG_PIOC_DELAYR (*(RwReg*)0x400E1310U) /**< \brief (PIOC) IO Delay Register */\r
+#define REG_PIOC_PCMR (*(RwReg*)0x400E1350U) /**< \brief (PIOC) Parallel Capture Mode Register */\r
+#define REG_PIOC_PCIER (*(WoReg*)0x400E1354U) /**< \brief (PIOC) Parallel Capture Interrupt Enable Register */\r
+#define REG_PIOC_PCIDR (*(WoReg*)0x400E1358U) /**< \brief (PIOC) Parallel Capture Interrupt Disable Register */\r
+#define REG_PIOC_PCIMR (*(RoReg*)0x400E135CU) /**< \brief (PIOC) Parallel Capture Interrupt Mask Register */\r
+#define REG_PIOC_PCISR (*(RoReg*)0x400E1360U) /**< \brief (PIOC) Parallel Capture Interrupt Status Register */\r
+#define REG_PIOC_PCRHR (*(RoReg*)0x400E1364U) /**< \brief (PIOC) Parallel Capture Reception Holding Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM4E_PIOC_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4E_PIOD_INSTANCE_\r
+#define _SAM4E_PIOD_INSTANCE_\r
+\r
+/* ========== Register definition for PIOD peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_PIOD_PER (0x400E1400U) /**< \brief (PIOD) PIO Enable Register */\r
+#define REG_PIOD_PDR (0x400E1404U) /**< \brief (PIOD) PIO Disable Register */\r
+#define REG_PIOD_PSR (0x400E1408U) /**< \brief (PIOD) PIO Status Register */\r
+#define REG_PIOD_OER (0x400E1410U) /**< \brief (PIOD) Output Enable Register */\r
+#define REG_PIOD_ODR (0x400E1414U) /**< \brief (PIOD) Output Disable Register */\r
+#define REG_PIOD_OSR (0x400E1418U) /**< \brief (PIOD) Output Status Register */\r
+#define REG_PIOD_IFER (0x400E1420U) /**< \brief (PIOD) Glitch Input Filter Enable Register */\r
+#define REG_PIOD_IFDR (0x400E1424U) /**< \brief (PIOD) Glitch Input Filter Disable Register */\r
+#define REG_PIOD_IFSR (0x400E1428U) /**< \brief (PIOD) Glitch Input Filter Status Register */\r
+#define REG_PIOD_SODR (0x400E1430U) /**< \brief (PIOD) Set Output Data Register */\r
+#define REG_PIOD_CODR (0x400E1434U) /**< \brief (PIOD) Clear Output Data Register */\r
+#define REG_PIOD_ODSR (0x400E1438U) /**< \brief (PIOD) Output Data Status Register */\r
+#define REG_PIOD_PDSR (0x400E143CU) /**< \brief (PIOD) Pin Data Status Register */\r
+#define REG_PIOD_IER (0x400E1440U) /**< \brief (PIOD) Interrupt Enable Register */\r
+#define REG_PIOD_IDR (0x400E1444U) /**< \brief (PIOD) Interrupt Disable Register */\r
+#define REG_PIOD_IMR (0x400E1448U) /**< \brief (PIOD) Interrupt Mask Register */\r
+#define REG_PIOD_ISR (0x400E144CU) /**< \brief (PIOD) Interrupt Status Register */\r
+#define REG_PIOD_MDER (0x400E1450U) /**< \brief (PIOD) Multi-driver Enable Register */\r
+#define REG_PIOD_MDDR (0x400E1454U) /**< \brief (PIOD) Multi-driver Disable Register */\r
+#define REG_PIOD_MDSR (0x400E1458U) /**< \brief (PIOD) Multi-driver Status Register */\r
+#define REG_PIOD_PUDR (0x400E1460U) /**< \brief (PIOD) Pull-up Disable Register */\r
+#define REG_PIOD_PUER (0x400E1464U) /**< \brief (PIOD) Pull-up Enable Register */\r
+#define REG_PIOD_PUSR (0x400E1468U) /**< \brief (PIOD) Pad Pull-up Status Register */\r
+#define REG_PIOD_ABCDSR (0x400E1470U) /**< \brief (PIOD) Peripheral Select Register */\r
+#define REG_PIOD_IFSCDR (0x400E1480U) /**< \brief (PIOD) Input Filter Slow Clock Disable Register */\r
+#define REG_PIOD_IFSCER (0x400E1484U) /**< \brief (PIOD) Input Filter Slow Clock Enable Register */\r
+#define REG_PIOD_IFSCSR (0x400E1488U) /**< \brief (PIOD) Input Filter Slow Clock Status Register */\r
+#define REG_PIOD_SCDR (0x400E148CU) /**< \brief (PIOD) Slow Clock Divider Debouncing Register */\r
+#define REG_PIOD_PPDDR (0x400E1490U) /**< \brief (PIOD) Pad Pull-down Disable Register */\r
+#define REG_PIOD_PPDER (0x400E1494U) /**< \brief (PIOD) Pad Pull-down Enable Register */\r
+#define REG_PIOD_PPDSR (0x400E1498U) /**< \brief (PIOD) Pad Pull-down Status Register */\r
+#define REG_PIOD_OWER (0x400E14A0U) /**< \brief (PIOD) Output Write Enable */\r
+#define REG_PIOD_OWDR (0x400E14A4U) /**< \brief (PIOD) Output Write Disable */\r
+#define REG_PIOD_OWSR (0x400E14A8U) /**< \brief (PIOD) Output Write Status Register */\r
+#define REG_PIOD_AIMER (0x400E14B0U) /**< \brief (PIOD) Additional Interrupt Modes Enable Register */\r
+#define REG_PIOD_AIMDR (0x400E14B4U) /**< \brief (PIOD) Additional Interrupt Modes Disables Register */\r
+#define REG_PIOD_AIMMR (0x400E14B8U) /**< \brief (PIOD) Additional Interrupt Modes Mask Register */\r
+#define REG_PIOD_ESR (0x400E14C0U) /**< \brief (PIOD) Edge Select Register */\r
+#define REG_PIOD_LSR (0x400E14C4U) /**< \brief (PIOD) Level Select Register */\r
+#define REG_PIOD_ELSR (0x400E14C8U) /**< \brief (PIOD) Edge/Level Status Register */\r
+#define REG_PIOD_FELLSR (0x400E14D0U) /**< \brief (PIOD) Falling Edge/Low Level Select Register */\r
+#define REG_PIOD_REHLSR (0x400E14D4U) /**< \brief (PIOD) Rising Edge/ High Level Select Register */\r
+#define REG_PIOD_FRLHSR (0x400E14D8U) /**< \brief (PIOD) Fall/Rise - Low/High Status Register */\r
+#define REG_PIOD_LOCKSR (0x400E14E0U) /**< \brief (PIOD) Lock Status */\r
+#define REG_PIOD_WPMR (0x400E14E4U) /**< \brief (PIOD) Write Protect Mode Register */\r
+#define REG_PIOD_WPSR (0x400E14E8U) /**< \brief (PIOD) Write Protect Status Register */\r
+#define REG_PIOD_SCHMITT (0x400E1500U) /**< \brief (PIOD) Schmitt Trigger Register */\r
+#define REG_PIOD_DELAYR (0x400E1510U) /**< \brief (PIOD) IO Delay Register */\r
+#define REG_PIOD_PCMR (0x400E1550U) /**< \brief (PIOD) Parallel Capture Mode Register */\r
+#define REG_PIOD_PCIER (0x400E1554U) /**< \brief (PIOD) Parallel Capture Interrupt Enable Register */\r
+#define REG_PIOD_PCIDR (0x400E1558U) /**< \brief (PIOD) Parallel Capture Interrupt Disable Register */\r
+#define REG_PIOD_PCIMR (0x400E155CU) /**< \brief (PIOD) Parallel Capture Interrupt Mask Register */\r
+#define REG_PIOD_PCISR (0x400E1560U) /**< \brief (PIOD) Parallel Capture Interrupt Status Register */\r
+#define REG_PIOD_PCRHR (0x400E1564U) /**< \brief (PIOD) Parallel Capture Reception Holding Register */\r
+#else\r
+#define REG_PIOD_PER (*(WoReg*)0x400E1400U) /**< \brief (PIOD) PIO Enable Register */\r
+#define REG_PIOD_PDR (*(WoReg*)0x400E1404U) /**< \brief (PIOD) PIO Disable Register */\r
+#define REG_PIOD_PSR (*(RoReg*)0x400E1408U) /**< \brief (PIOD) PIO Status Register */\r
+#define REG_PIOD_OER (*(WoReg*)0x400E1410U) /**< \brief (PIOD) Output Enable Register */\r
+#define REG_PIOD_ODR (*(WoReg*)0x400E1414U) /**< \brief (PIOD) Output Disable Register */\r
+#define REG_PIOD_OSR (*(RoReg*)0x400E1418U) /**< \brief (PIOD) Output Status Register */\r
+#define REG_PIOD_IFER (*(WoReg*)0x400E1420U) /**< \brief (PIOD) Glitch Input Filter Enable Register */\r
+#define REG_PIOD_IFDR (*(WoReg*)0x400E1424U) /**< \brief (PIOD) Glitch Input Filter Disable Register */\r
+#define REG_PIOD_IFSR (*(RoReg*)0x400E1428U) /**< \brief (PIOD) Glitch Input Filter Status Register */\r
+#define REG_PIOD_SODR (*(WoReg*)0x400E1430U) /**< \brief (PIOD) Set Output Data Register */\r
+#define REG_PIOD_CODR (*(WoReg*)0x400E1434U) /**< \brief (PIOD) Clear Output Data Register */\r
+#define REG_PIOD_ODSR (*(RwReg*)0x400E1438U) /**< \brief (PIOD) Output Data Status Register */\r
+#define REG_PIOD_PDSR (*(RoReg*)0x400E143CU) /**< \brief (PIOD) Pin Data Status Register */\r
+#define REG_PIOD_IER (*(WoReg*)0x400E1440U) /**< \brief (PIOD) Interrupt Enable Register */\r
+#define REG_PIOD_IDR (*(WoReg*)0x400E1444U) /**< \brief (PIOD) Interrupt Disable Register */\r
+#define REG_PIOD_IMR (*(RoReg*)0x400E1448U) /**< \brief (PIOD) Interrupt Mask Register */\r
+#define REG_PIOD_ISR (*(RoReg*)0x400E144CU) /**< \brief (PIOD) Interrupt Status Register */\r
+#define REG_PIOD_MDER (*(WoReg*)0x400E1450U) /**< \brief (PIOD) Multi-driver Enable Register */\r
+#define REG_PIOD_MDDR (*(WoReg*)0x400E1454U) /**< \brief (PIOD) Multi-driver Disable Register */\r
+#define REG_PIOD_MDSR (*(RoReg*)0x400E1458U) /**< \brief (PIOD) Multi-driver Status Register */\r
+#define REG_PIOD_PUDR (*(WoReg*)0x400E1460U) /**< \brief (PIOD) Pull-up Disable Register */\r
+#define REG_PIOD_PUER (*(WoReg*)0x400E1464U) /**< \brief (PIOD) Pull-up Enable Register */\r
+#define REG_PIOD_PUSR (*(RoReg*)0x400E1468U) /**< \brief (PIOD) Pad Pull-up Status Register */\r
+#define REG_PIOD_ABCDSR (*(RwReg*)0x400E1470U) /**< \brief (PIOD) Peripheral Select Register */\r
+#define REG_PIOD_IFSCDR (*(WoReg*)0x400E1480U) /**< \brief (PIOD) Input Filter Slow Clock Disable Register */\r
+#define REG_PIOD_IFSCER (*(WoReg*)0x400E1484U) /**< \brief (PIOD) Input Filter Slow Clock Enable Register */\r
+#define REG_PIOD_IFSCSR (*(RoReg*)0x400E1488U) /**< \brief (PIOD) Input Filter Slow Clock Status Register */\r
+#define REG_PIOD_SCDR (*(RwReg*)0x400E148CU) /**< \brief (PIOD) Slow Clock Divider Debouncing Register */\r
+#define REG_PIOD_PPDDR (*(WoReg*)0x400E1490U) /**< \brief (PIOD) Pad Pull-down Disable Register */\r
+#define REG_PIOD_PPDER (*(WoReg*)0x400E1494U) /**< \brief (PIOD) Pad Pull-down Enable Register */\r
+#define REG_PIOD_PPDSR (*(RoReg*)0x400E1498U) /**< \brief (PIOD) Pad Pull-down Status Register */\r
+#define REG_PIOD_OWER (*(WoReg*)0x400E14A0U) /**< \brief (PIOD) Output Write Enable */\r
+#define REG_PIOD_OWDR (*(WoReg*)0x400E14A4U) /**< \brief (PIOD) Output Write Disable */\r
+#define REG_PIOD_OWSR (*(RoReg*)0x400E14A8U) /**< \brief (PIOD) Output Write Status Register */\r
+#define REG_PIOD_AIMER (*(WoReg*)0x400E14B0U) /**< \brief (PIOD) Additional Interrupt Modes Enable Register */\r
+#define REG_PIOD_AIMDR (*(WoReg*)0x400E14B4U) /**< \brief (PIOD) Additional Interrupt Modes Disables Register */\r
+#define REG_PIOD_AIMMR (*(RoReg*)0x400E14B8U) /**< \brief (PIOD) Additional Interrupt Modes Mask Register */\r
+#define REG_PIOD_ESR (*(WoReg*)0x400E14C0U) /**< \brief (PIOD) Edge Select Register */\r
+#define REG_PIOD_LSR (*(WoReg*)0x400E14C4U) /**< \brief (PIOD) Level Select Register */\r
+#define REG_PIOD_ELSR (*(RoReg*)0x400E14C8U) /**< \brief (PIOD) Edge/Level Status Register */\r
+#define REG_PIOD_FELLSR (*(WoReg*)0x400E14D0U) /**< \brief (PIOD) Falling Edge/Low Level Select Register */\r
+#define REG_PIOD_REHLSR (*(WoReg*)0x400E14D4U) /**< \brief (PIOD) Rising Edge/ High Level Select Register */\r
+#define REG_PIOD_FRLHSR (*(RoReg*)0x400E14D8U) /**< \brief (PIOD) Fall/Rise - Low/High Status Register */\r
+#define REG_PIOD_LOCKSR (*(RoReg*)0x400E14E0U) /**< \brief (PIOD) Lock Status */\r
+#define REG_PIOD_WPMR (*(RwReg*)0x400E14E4U) /**< \brief (PIOD) Write Protect Mode Register */\r
+#define REG_PIOD_WPSR (*(RoReg*)0x400E14E8U) /**< \brief (PIOD) Write Protect Status Register */\r
+#define REG_PIOD_SCHMITT (*(RwReg*)0x400E1500U) /**< \brief (PIOD) Schmitt Trigger Register */\r
+#define REG_PIOD_DELAYR (*(RwReg*)0x400E1510U) /**< \brief (PIOD) IO Delay Register */\r
+#define REG_PIOD_PCMR (*(RwReg*)0x400E1550U) /**< \brief (PIOD) Parallel Capture Mode Register */\r
+#define REG_PIOD_PCIER (*(WoReg*)0x400E1554U) /**< \brief (PIOD) Parallel Capture Interrupt Enable Register */\r
+#define REG_PIOD_PCIDR (*(WoReg*)0x400E1558U) /**< \brief (PIOD) Parallel Capture Interrupt Disable Register */\r
+#define REG_PIOD_PCIMR (*(RoReg*)0x400E155CU) /**< \brief (PIOD) Parallel Capture Interrupt Mask Register */\r
+#define REG_PIOD_PCISR (*(RoReg*)0x400E1560U) /**< \brief (PIOD) Parallel Capture Interrupt Status Register */\r
+#define REG_PIOD_PCRHR (*(RoReg*)0x400E1564U) /**< \brief (PIOD) Parallel Capture Reception Holding Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM4E_PIOD_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4E_PIOE_INSTANCE_\r
+#define _SAM4E_PIOE_INSTANCE_\r
+\r
+/* ========== Register definition for PIOE peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_PIOE_PER (0x400E1600U) /**< \brief (PIOE) PIO Enable Register */\r
+#define REG_PIOE_PDR (0x400E1604U) /**< \brief (PIOE) PIO Disable Register */\r
+#define REG_PIOE_PSR (0x400E1608U) /**< \brief (PIOE) PIO Status Register */\r
+#define REG_PIOE_OER (0x400E1610U) /**< \brief (PIOE) Output Enable Register */\r
+#define REG_PIOE_ODR (0x400E1614U) /**< \brief (PIOE) Output Disable Register */\r
+#define REG_PIOE_OSR (0x400E1618U) /**< \brief (PIOE) Output Status Register */\r
+#define REG_PIOE_IFER (0x400E1620U) /**< \brief (PIOE) Glitch Input Filter Enable Register */\r
+#define REG_PIOE_IFDR (0x400E1624U) /**< \brief (PIOE) Glitch Input Filter Disable Register */\r
+#define REG_PIOE_IFSR (0x400E1628U) /**< \brief (PIOE) Glitch Input Filter Status Register */\r
+#define REG_PIOE_SODR (0x400E1630U) /**< \brief (PIOE) Set Output Data Register */\r
+#define REG_PIOE_CODR (0x400E1634U) /**< \brief (PIOE) Clear Output Data Register */\r
+#define REG_PIOE_ODSR (0x400E1638U) /**< \brief (PIOE) Output Data Status Register */\r
+#define REG_PIOE_PDSR (0x400E163CU) /**< \brief (PIOE) Pin Data Status Register */\r
+#define REG_PIOE_IER (0x400E1640U) /**< \brief (PIOE) Interrupt Enable Register */\r
+#define REG_PIOE_IDR (0x400E1644U) /**< \brief (PIOE) Interrupt Disable Register */\r
+#define REG_PIOE_IMR (0x400E1648U) /**< \brief (PIOE) Interrupt Mask Register */\r
+#define REG_PIOE_ISR (0x400E164CU) /**< \brief (PIOE) Interrupt Status Register */\r
+#define REG_PIOE_MDER (0x400E1650U) /**< \brief (PIOE) Multi-driver Enable Register */\r
+#define REG_PIOE_MDDR (0x400E1654U) /**< \brief (PIOE) Multi-driver Disable Register */\r
+#define REG_PIOE_MDSR (0x400E1658U) /**< \brief (PIOE) Multi-driver Status Register */\r
+#define REG_PIOE_PUDR (0x400E1660U) /**< \brief (PIOE) Pull-up Disable Register */\r
+#define REG_PIOE_PUER (0x400E1664U) /**< \brief (PIOE) Pull-up Enable Register */\r
+#define REG_PIOE_PUSR (0x400E1668U) /**< \brief (PIOE) Pad Pull-up Status Register */\r
+#define REG_PIOE_ABCDSR (0x400E1670U) /**< \brief (PIOE) Peripheral Select Register */\r
+#define REG_PIOE_IFSCDR (0x400E1680U) /**< \brief (PIOE) Input Filter Slow Clock Disable Register */\r
+#define REG_PIOE_IFSCER (0x400E1684U) /**< \brief (PIOE) Input Filter Slow Clock Enable Register */\r
+#define REG_PIOE_IFSCSR (0x400E1688U) /**< \brief (PIOE) Input Filter Slow Clock Status Register */\r
+#define REG_PIOE_SCDR (0x400E168CU) /**< \brief (PIOE) Slow Clock Divider Debouncing Register */\r
+#define REG_PIOE_PPDDR (0x400E1690U) /**< \brief (PIOE) Pad Pull-down Disable Register */\r
+#define REG_PIOE_PPDER (0x400E1694U) /**< \brief (PIOE) Pad Pull-down Enable Register */\r
+#define REG_PIOE_PPDSR (0x400E1698U) /**< \brief (PIOE) Pad Pull-down Status Register */\r
+#define REG_PIOE_OWER (0x400E16A0U) /**< \brief (PIOE) Output Write Enable */\r
+#define REG_PIOE_OWDR (0x400E16A4U) /**< \brief (PIOE) Output Write Disable */\r
+#define REG_PIOE_OWSR (0x400E16A8U) /**< \brief (PIOE) Output Write Status Register */\r
+#define REG_PIOE_AIMER (0x400E16B0U) /**< \brief (PIOE) Additional Interrupt Modes Enable Register */\r
+#define REG_PIOE_AIMDR (0x400E16B4U) /**< \brief (PIOE) Additional Interrupt Modes Disables Register */\r
+#define REG_PIOE_AIMMR (0x400E16B8U) /**< \brief (PIOE) Additional Interrupt Modes Mask Register */\r
+#define REG_PIOE_ESR (0x400E16C0U) /**< \brief (PIOE) Edge Select Register */\r
+#define REG_PIOE_LSR (0x400E16C4U) /**< \brief (PIOE) Level Select Register */\r
+#define REG_PIOE_ELSR (0x400E16C8U) /**< \brief (PIOE) Edge/Level Status Register */\r
+#define REG_PIOE_FELLSR (0x400E16D0U) /**< \brief (PIOE) Falling Edge/Low Level Select Register */\r
+#define REG_PIOE_REHLSR (0x400E16D4U) /**< \brief (PIOE) Rising Edge/ High Level Select Register */\r
+#define REG_PIOE_FRLHSR (0x400E16D8U) /**< \brief (PIOE) Fall/Rise - Low/High Status Register */\r
+#define REG_PIOE_LOCKSR (0x400E16E0U) /**< \brief (PIOE) Lock Status */\r
+#define REG_PIOE_WPMR (0x400E16E4U) /**< \brief (PIOE) Write Protect Mode Register */\r
+#define REG_PIOE_WPSR (0x400E16E8U) /**< \brief (PIOE) Write Protect Status Register */\r
+#define REG_PIOE_SCHMITT (0x400E1700U) /**< \brief (PIOE) Schmitt Trigger Register */\r
+#define REG_PIOE_DELAYR (0x400E1710U) /**< \brief (PIOE) IO Delay Register */\r
+#define REG_PIOE_PCMR (0x400E1750U) /**< \brief (PIOE) Parallel Capture Mode Register */\r
+#define REG_PIOE_PCIER (0x400E1754U) /**< \brief (PIOE) Parallel Capture Interrupt Enable Register */\r
+#define REG_PIOE_PCIDR (0x400E1758U) /**< \brief (PIOE) Parallel Capture Interrupt Disable Register */\r
+#define REG_PIOE_PCIMR (0x400E175CU) /**< \brief (PIOE) Parallel Capture Interrupt Mask Register */\r
+#define REG_PIOE_PCISR (0x400E1760U) /**< \brief (PIOE) Parallel Capture Interrupt Status Register */\r
+#define REG_PIOE_PCRHR (0x400E1764U) /**< \brief (PIOE) Parallel Capture Reception Holding Register */\r
+#else\r
+#define REG_PIOE_PER (*(WoReg*)0x400E1600U) /**< \brief (PIOE) PIO Enable Register */\r
+#define REG_PIOE_PDR (*(WoReg*)0x400E1604U) /**< \brief (PIOE) PIO Disable Register */\r
+#define REG_PIOE_PSR (*(RoReg*)0x400E1608U) /**< \brief (PIOE) PIO Status Register */\r
+#define REG_PIOE_OER (*(WoReg*)0x400E1610U) /**< \brief (PIOE) Output Enable Register */\r
+#define REG_PIOE_ODR (*(WoReg*)0x400E1614U) /**< \brief (PIOE) Output Disable Register */\r
+#define REG_PIOE_OSR (*(RoReg*)0x400E1618U) /**< \brief (PIOE) Output Status Register */\r
+#define REG_PIOE_IFER (*(WoReg*)0x400E1620U) /**< \brief (PIOE) Glitch Input Filter Enable Register */\r
+#define REG_PIOE_IFDR (*(WoReg*)0x400E1624U) /**< \brief (PIOE) Glitch Input Filter Disable Register */\r
+#define REG_PIOE_IFSR (*(RoReg*)0x400E1628U) /**< \brief (PIOE) Glitch Input Filter Status Register */\r
+#define REG_PIOE_SODR (*(WoReg*)0x400E1630U) /**< \brief (PIOE) Set Output Data Register */\r
+#define REG_PIOE_CODR (*(WoReg*)0x400E1634U) /**< \brief (PIOE) Clear Output Data Register */\r
+#define REG_PIOE_ODSR (*(RwReg*)0x400E1638U) /**< \brief (PIOE) Output Data Status Register */\r
+#define REG_PIOE_PDSR (*(RoReg*)0x400E163CU) /**< \brief (PIOE) Pin Data Status Register */\r
+#define REG_PIOE_IER (*(WoReg*)0x400E1640U) /**< \brief (PIOE) Interrupt Enable Register */\r
+#define REG_PIOE_IDR (*(WoReg*)0x400E1644U) /**< \brief (PIOE) Interrupt Disable Register */\r
+#define REG_PIOE_IMR (*(RoReg*)0x400E1648U) /**< \brief (PIOE) Interrupt Mask Register */\r
+#define REG_PIOE_ISR (*(RoReg*)0x400E164CU) /**< \brief (PIOE) Interrupt Status Register */\r
+#define REG_PIOE_MDER (*(WoReg*)0x400E1650U) /**< \brief (PIOE) Multi-driver Enable Register */\r
+#define REG_PIOE_MDDR (*(WoReg*)0x400E1654U) /**< \brief (PIOE) Multi-driver Disable Register */\r
+#define REG_PIOE_MDSR (*(RoReg*)0x400E1658U) /**< \brief (PIOE) Multi-driver Status Register */\r
+#define REG_PIOE_PUDR (*(WoReg*)0x400E1660U) /**< \brief (PIOE) Pull-up Disable Register */\r
+#define REG_PIOE_PUER (*(WoReg*)0x400E1664U) /**< \brief (PIOE) Pull-up Enable Register */\r
+#define REG_PIOE_PUSR (*(RoReg*)0x400E1668U) /**< \brief (PIOE) Pad Pull-up Status Register */\r
+#define REG_PIOE_ABCDSR (*(RwReg*)0x400E1670U) /**< \brief (PIOE) Peripheral Select Register */\r
+#define REG_PIOE_IFSCDR (*(WoReg*)0x400E1680U) /**< \brief (PIOE) Input Filter Slow Clock Disable Register */\r
+#define REG_PIOE_IFSCER (*(WoReg*)0x400E1684U) /**< \brief (PIOE) Input Filter Slow Clock Enable Register */\r
+#define REG_PIOE_IFSCSR (*(RoReg*)0x400E1688U) /**< \brief (PIOE) Input Filter Slow Clock Status Register */\r
+#define REG_PIOE_SCDR (*(RwReg*)0x400E168CU) /**< \brief (PIOE) Slow Clock Divider Debouncing Register */\r
+#define REG_PIOE_PPDDR (*(WoReg*)0x400E1690U) /**< \brief (PIOE) Pad Pull-down Disable Register */\r
+#define REG_PIOE_PPDER (*(WoReg*)0x400E1694U) /**< \brief (PIOE) Pad Pull-down Enable Register */\r
+#define REG_PIOE_PPDSR (*(RoReg*)0x400E1698U) /**< \brief (PIOE) Pad Pull-down Status Register */\r
+#define REG_PIOE_OWER (*(WoReg*)0x400E16A0U) /**< \brief (PIOE) Output Write Enable */\r
+#define REG_PIOE_OWDR (*(WoReg*)0x400E16A4U) /**< \brief (PIOE) Output Write Disable */\r
+#define REG_PIOE_OWSR (*(RoReg*)0x400E16A8U) /**< \brief (PIOE) Output Write Status Register */\r
+#define REG_PIOE_AIMER (*(WoReg*)0x400E16B0U) /**< \brief (PIOE) Additional Interrupt Modes Enable Register */\r
+#define REG_PIOE_AIMDR (*(WoReg*)0x400E16B4U) /**< \brief (PIOE) Additional Interrupt Modes Disables Register */\r
+#define REG_PIOE_AIMMR (*(RoReg*)0x400E16B8U) /**< \brief (PIOE) Additional Interrupt Modes Mask Register */\r
+#define REG_PIOE_ESR (*(WoReg*)0x400E16C0U) /**< \brief (PIOE) Edge Select Register */\r
+#define REG_PIOE_LSR (*(WoReg*)0x400E16C4U) /**< \brief (PIOE) Level Select Register */\r
+#define REG_PIOE_ELSR (*(RoReg*)0x400E16C8U) /**< \brief (PIOE) Edge/Level Status Register */\r
+#define REG_PIOE_FELLSR (*(WoReg*)0x400E16D0U) /**< \brief (PIOE) Falling Edge/Low Level Select Register */\r
+#define REG_PIOE_REHLSR (*(WoReg*)0x400E16D4U) /**< \brief (PIOE) Rising Edge/ High Level Select Register */\r
+#define REG_PIOE_FRLHSR (*(RoReg*)0x400E16D8U) /**< \brief (PIOE) Fall/Rise - Low/High Status Register */\r
+#define REG_PIOE_LOCKSR (*(RoReg*)0x400E16E0U) /**< \brief (PIOE) Lock Status */\r
+#define REG_PIOE_WPMR (*(RwReg*)0x400E16E4U) /**< \brief (PIOE) Write Protect Mode Register */\r
+#define REG_PIOE_WPSR (*(RoReg*)0x400E16E8U) /**< \brief (PIOE) Write Protect Status Register */\r
+#define REG_PIOE_SCHMITT (*(RwReg*)0x400E1700U) /**< \brief (PIOE) Schmitt Trigger Register */\r
+#define REG_PIOE_DELAYR (*(RwReg*)0x400E1710U) /**< \brief (PIOE) IO Delay Register */\r
+#define REG_PIOE_PCMR (*(RwReg*)0x400E1750U) /**< \brief (PIOE) Parallel Capture Mode Register */\r
+#define REG_PIOE_PCIER (*(WoReg*)0x400E1754U) /**< \brief (PIOE) Parallel Capture Interrupt Enable Register */\r
+#define REG_PIOE_PCIDR (*(WoReg*)0x400E1758U) /**< \brief (PIOE) Parallel Capture Interrupt Disable Register */\r
+#define REG_PIOE_PCIMR (*(RoReg*)0x400E175CU) /**< \brief (PIOE) Parallel Capture Interrupt Mask Register */\r
+#define REG_PIOE_PCISR (*(RoReg*)0x400E1760U) /**< \brief (PIOE) Parallel Capture Interrupt Status Register */\r
+#define REG_PIOE_PCRHR (*(RoReg*)0x400E1764U) /**< \brief (PIOE) Parallel Capture Reception Holding Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM4E_PIOE_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4E_PMC_INSTANCE_\r
+#define _SAM4E_PMC_INSTANCE_\r
+\r
+/* ========== Register definition for PMC peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_PMC_SCER (0x400E0400U) /**< \brief (PMC) System Clock Enable Register */\r
+#define REG_PMC_SCDR (0x400E0404U) /**< \brief (PMC) System Clock Disable Register */\r
+#define REG_PMC_SCSR (0x400E0408U) /**< \brief (PMC) System Clock Status Register */\r
+#define REG_PMC_PCER0 (0x400E0410U) /**< \brief (PMC) Peripheral Clock Enable Register 0 */\r
+#define REG_PMC_PCDR0 (0x400E0414U) /**< \brief (PMC) Peripheral Clock Disable Register 0 */\r
+#define REG_PMC_PCSR0 (0x400E0418U) /**< \brief (PMC) Peripheral Clock Status Register 0 */\r
+#define REG_CKGR_MOR (0x400E0420U) /**< \brief (PMC) Main Oscillator Register */\r
+#define REG_CKGR_MCFR (0x400E0424U) /**< \brief (PMC) Main Clock Frequency Register */\r
+#define REG_CKGR_PLLAR (0x400E0428U) /**< \brief (PMC) PLLA Register */\r
+#define REG_PMC_MCKR (0x400E0430U) /**< \brief (PMC) Master Clock Register */\r
+#define REG_PMC_USB (0x400E0438U) /**< \brief (PMC) USB Clock Register */\r
+#define REG_PMC_PCK (0x400E0440U) /**< \brief (PMC) Programmable Clock 0 Register */\r
+#define REG_PMC_IER (0x400E0460U) /**< \brief (PMC) Interrupt Enable Register */\r
+#define REG_PMC_IDR (0x400E0464U) /**< \brief (PMC) Interrupt Disable Register */\r
+#define REG_PMC_SR (0x400E0468U) /**< \brief (PMC) Status Register */\r
+#define REG_PMC_IMR (0x400E046CU) /**< \brief (PMC) Interrupt Mask Register */\r
+#define REG_PMC_FSMR (0x400E0470U) /**< \brief (PMC) Fast Start-up Mode Register */\r
+#define REG_PMC_FSPR (0x400E0474U) /**< \brief (PMC) Fast Start-up Polarity Register */\r
+#define REG_PMC_FOCR (0x400E0478U) /**< \brief (PMC) Fault Output Clear Register */\r
+#define REG_PMC_WPMR (0x400E04E4U) /**< \brief (PMC) Write Protect Mode Register */\r
+#define REG_PMC_WPSR (0x400E04E8U) /**< \brief (PMC) Write Protect Status Register */\r
+#define REG_PMC_PCER1 (0x400E0500U) /**< \brief (PMC) Peripheral Clock Enable Register 1 */\r
+#define REG_PMC_PCDR1 (0x400E0504U) /**< \brief (PMC) Peripheral Clock Disable Register 1 */\r
+#define REG_PMC_PCSR1 (0x400E0508U) /**< \brief (PMC) Peripheral Clock Status Register 1 */\r
+#define REG_PMC_OCR (0x400E0510U) /**< \brief (PMC) Oscillator Calibration Register */\r
+#else\r
+#define REG_PMC_SCER (*(WoReg*)0x400E0400U) /**< \brief (PMC) System Clock Enable Register */\r
+#define REG_PMC_SCDR (*(WoReg*)0x400E0404U) /**< \brief (PMC) System Clock Disable Register */\r
+#define REG_PMC_SCSR (*(RoReg*)0x400E0408U) /**< \brief (PMC) System Clock Status Register */\r
+#define REG_PMC_PCER0 (*(WoReg*)0x400E0410U) /**< \brief (PMC) Peripheral Clock Enable Register 0 */\r
+#define REG_PMC_PCDR0 (*(WoReg*)0x400E0414U) /**< \brief (PMC) Peripheral Clock Disable Register 0 */\r
+#define REG_PMC_PCSR0 (*(RoReg*)0x400E0418U) /**< \brief (PMC) Peripheral Clock Status Register 0 */\r
+#define REG_CKGR_MOR (*(RwReg*)0x400E0420U) /**< \brief (PMC) Main Oscillator Register */\r
+#define REG_CKGR_MCFR (*(RwReg*)0x400E0424U) /**< \brief (PMC) Main Clock Frequency Register */\r
+#define REG_CKGR_PLLAR (*(RwReg*)0x400E0428U) /**< \brief (PMC) PLLA Register */\r
+#define REG_PMC_MCKR (*(RwReg*)0x400E0430U) /**< \brief (PMC) Master Clock Register */\r
+#define REG_PMC_USB (*(RwReg*)0x400E0438U) /**< \brief (PMC) USB Clock Register */\r
+#define REG_PMC_PCK (*(RwReg*)0x400E0440U) /**< \brief (PMC) Programmable Clock 0 Register */\r
+#define REG_PMC_IER (*(WoReg*)0x400E0460U) /**< \brief (PMC) Interrupt Enable Register */\r
+#define REG_PMC_IDR (*(WoReg*)0x400E0464U) /**< \brief (PMC) Interrupt Disable Register */\r
+#define REG_PMC_SR (*(RoReg*)0x400E0468U) /**< \brief (PMC) Status Register */\r
+#define REG_PMC_IMR (*(RoReg*)0x400E046CU) /**< \brief (PMC) Interrupt Mask Register */\r
+#define REG_PMC_FSMR (*(RwReg*)0x400E0470U) /**< \brief (PMC) Fast Start-up Mode Register */\r
+#define REG_PMC_FSPR (*(RwReg*)0x400E0474U) /**< \brief (PMC) Fast Start-up Polarity Register */\r
+#define REG_PMC_FOCR (*(WoReg*)0x400E0478U) /**< \brief (PMC) Fault Output Clear Register */\r
+#define REG_PMC_WPMR (*(RwReg*)0x400E04E4U) /**< \brief (PMC) Write Protect Mode Register */\r
+#define REG_PMC_WPSR (*(RoReg*)0x400E04E8U) /**< \brief (PMC) Write Protect Status Register */\r
+#define REG_PMC_PCER1 (*(WoReg*)0x400E0500U) /**< \brief (PMC) Peripheral Clock Enable Register 1 */\r
+#define REG_PMC_PCDR1 (*(WoReg*)0x400E0504U) /**< \brief (PMC) Peripheral Clock Disable Register 1 */\r
+#define REG_PMC_PCSR1 (*(RoReg*)0x400E0508U) /**< \brief (PMC) Peripheral Clock Status Register 1 */\r
+#define REG_PMC_OCR (*(RwReg*)0x400E0510U) /**< \brief (PMC) Oscillator Calibration Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM4E_PMC_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4E_PWM_INSTANCE_\r
+#define _SAM4E_PWM_INSTANCE_\r
+\r
+/* ========== Register definition for PWM peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_PWM_CLK (0x40000000U) /**< \brief (PWM) PWM Clock Register */\r
+#define REG_PWM_ENA (0x40000004U) /**< \brief (PWM) PWM Enable Register */\r
+#define REG_PWM_DIS (0x40000008U) /**< \brief (PWM) PWM Disable Register */\r
+#define REG_PWM_SR (0x4000000CU) /**< \brief (PWM) PWM Status Register */\r
+#define REG_PWM_IER1 (0x40000010U) /**< \brief (PWM) PWM Interrupt Enable Register 1 */\r
+#define REG_PWM_IDR1 (0x40000014U) /**< \brief (PWM) PWM Interrupt Disable Register 1 */\r
+#define REG_PWM_IMR1 (0x40000018U) /**< \brief (PWM) PWM Interrupt Mask Register 1 */\r
+#define REG_PWM_ISR1 (0x4000001CU) /**< \brief (PWM) PWM Interrupt Status Register 1 */\r
+#define REG_PWM_SCM (0x40000020U) /**< \brief (PWM) PWM Sync Channels Mode Register */\r
+#define REG_PWM_SCUC (0x40000028U) /**< \brief (PWM) PWM Sync Channels Update Control Register */\r
+#define REG_PWM_SCUP (0x4000002CU) /**< \brief (PWM) PWM Sync Channels Update Period Register */\r
+#define REG_PWM_SCUPUPD (0x40000030U) /**< \brief (PWM) PWM Sync Channels Update Period Update Register */\r
+#define REG_PWM_IER2 (0x40000034U) /**< \brief (PWM) PWM Interrupt Enable Register 2 */\r
+#define REG_PWM_IDR2 (0x40000038U) /**< \brief (PWM) PWM Interrupt Disable Register 2 */\r
+#define REG_PWM_IMR2 (0x4000003CU) /**< \brief (PWM) PWM Interrupt Mask Register 2 */\r
+#define REG_PWM_ISR2 (0x40000040U) /**< \brief (PWM) PWM Interrupt Status Register 2 */\r
+#define REG_PWM_OOV (0x40000044U) /**< \brief (PWM) PWM Output Override Value Register */\r
+#define REG_PWM_OS (0x40000048U) /**< \brief (PWM) PWM Output Selection Register */\r
+#define REG_PWM_OSS (0x4000004CU) /**< \brief (PWM) PWM Output Selection Set Register */\r
+#define REG_PWM_OSC (0x40000050U) /**< \brief (PWM) PWM Output Selection Clear Register */\r
+#define REG_PWM_OSSUPD (0x40000054U) /**< \brief (PWM) PWM Output Selection Set Update Register */\r
+#define REG_PWM_OSCUPD (0x40000058U) /**< \brief (PWM) PWM Output Selection Clear Update Register */\r
+#define REG_PWM_FMR (0x4000005CU) /**< \brief (PWM) PWM Fault Mode Register */\r
+#define REG_PWM_FSR (0x40000060U) /**< \brief (PWM) PWM Fault Status Register */\r
+#define REG_PWM_FCR (0x40000064U) /**< \brief (PWM) PWM Fault Clear Register */\r
+#define REG_PWM_FPV1 (0x40000068U) /**< \brief (PWM) PWM Fault Protection Value Register 1 */\r
+#define REG_PWM_FPE (0x4000006CU) /**< \brief (PWM) PWM Fault Protection Enable Register */\r
+#define REG_PWM_ELMR (0x4000007CU) /**< \brief (PWM) PWM Event Line 0 Mode Register */\r
+#define REG_PWM_SSPR (0x400000A0U) /**< \brief (PWM) PWM Spread Spectrum Register */\r
+#define REG_PWM_SSPUP (0x400000A4U) /**< \brief (PWM) PWM Spread Spectrum Update Register */\r
+#define REG_PWM_SMMR (0x400000B0U) /**< \brief (PWM) PWM Stepper Motor Mode Register */\r
+#define REG_PWM_FPV2 (0x400000C0U) /**< \brief (PWM) PWM Fault Protection Value 2 Register */\r
+#define REG_PWM_WPCR (0x400000E4U) /**< \brief (PWM) PWM Write Protect Control Register */\r
+#define REG_PWM_WPSR (0x400000E8U) /**< \brief (PWM) PWM Write Protect Status Register */\r
+#define REG_PWM_TPR (0x40000108U) /**< \brief (PWM) Transmit Pointer Register */\r
+#define REG_PWM_TCR (0x4000010CU) /**< \brief (PWM) Transmit Counter Register */\r
+#define REG_PWM_TNPR (0x40000118U) /**< \brief (PWM) Transmit Next Pointer Register */\r
+#define REG_PWM_TNCR (0x4000011CU) /**< \brief (PWM) Transmit Next Counter Register */\r
+#define REG_PWM_PTCR (0x40000120U) /**< \brief (PWM) Transfer Control Register */\r
+#define REG_PWM_PTSR (0x40000124U) /**< \brief (PWM) Transfer Status Register */\r
+#define REG_PWM_CMPV0 (0x40000130U) /**< \brief (PWM) PWM Comparison 0 Value Register */\r
+#define REG_PWM_CMPVUPD0 (0x40000134U) /**< \brief (PWM) PWM Comparison 0 Value Update Register */\r
+#define REG_PWM_CMPM0 (0x40000138U) /**< \brief (PWM) PWM Comparison 0 Mode Register */\r
+#define REG_PWM_CMPMUPD0 (0x4000013CU) /**< \brief (PWM) PWM Comparison 0 Mode Update Register */\r
+#define REG_PWM_CMPV1 (0x40000140U) /**< \brief (PWM) PWM Comparison 1 Value Register */\r
+#define REG_PWM_CMPVUPD1 (0x40000144U) /**< \brief (PWM) PWM Comparison 1 Value Update Register */\r
+#define REG_PWM_CMPM1 (0x40000148U) /**< \brief (PWM) PWM Comparison 1 Mode Register */\r
+#define REG_PWM_CMPMUPD1 (0x4000014CU) /**< \brief (PWM) PWM Comparison 1 Mode Update Register */\r
+#define REG_PWM_CMPV2 (0x40000150U) /**< \brief (PWM) PWM Comparison 2 Value Register */\r
+#define REG_PWM_CMPVUPD2 (0x40000154U) /**< \brief (PWM) PWM Comparison 2 Value Update Register */\r
+#define REG_PWM_CMPM2 (0x40000158U) /**< \brief (PWM) PWM Comparison 2 Mode Register */\r
+#define REG_PWM_CMPMUPD2 (0x4000015CU) /**< \brief (PWM) PWM Comparison 2 Mode Update Register */\r
+#define REG_PWM_CMPV3 (0x40000160U) /**< \brief (PWM) PWM Comparison 3 Value Register */\r
+#define REG_PWM_CMPVUPD3 (0x40000164U) /**< \brief (PWM) PWM Comparison 3 Value Update Register */\r
+#define REG_PWM_CMPM3 (0x40000168U) /**< \brief (PWM) PWM Comparison 3 Mode Register */\r
+#define REG_PWM_CMPMUPD3 (0x4000016CU) /**< \brief (PWM) PWM Comparison 3 Mode Update Register */\r
+#define REG_PWM_CMPV4 (0x40000170U) /**< \brief (PWM) PWM Comparison 4 Value Register */\r
+#define REG_PWM_CMPVUPD4 (0x40000174U) /**< \brief (PWM) PWM Comparison 4 Value Update Register */\r
+#define REG_PWM_CMPM4 (0x40000178U) /**< \brief (PWM) PWM Comparison 4 Mode Register */\r
+#define REG_PWM_CMPMUPD4 (0x4000017CU) /**< \brief (PWM) PWM Comparison 4 Mode Update Register */\r
+#define REG_PWM_CMPV5 (0x40000180U) /**< \brief (PWM) PWM Comparison 5 Value Register */\r
+#define REG_PWM_CMPVUPD5 (0x40000184U) /**< \brief (PWM) PWM Comparison 5 Value Update Register */\r
+#define REG_PWM_CMPM5 (0x40000188U) /**< \brief (PWM) PWM Comparison 5 Mode Register */\r
+#define REG_PWM_CMPMUPD5 (0x4000018CU) /**< \brief (PWM) PWM Comparison 5 Mode Update Register */\r
+#define REG_PWM_CMPV6 (0x40000190U) /**< \brief (PWM) PWM Comparison 6 Value Register */\r
+#define REG_PWM_CMPVUPD6 (0x40000194U) /**< \brief (PWM) PWM Comparison 6 Value Update Register */\r
+#define REG_PWM_CMPM6 (0x40000198U) /**< \brief (PWM) PWM Comparison 6 Mode Register */\r
+#define REG_PWM_CMPMUPD6 (0x4000019CU) /**< \brief (PWM) PWM Comparison 6 Mode Update Register */\r
+#define REG_PWM_CMPV7 (0x400001A0U) /**< \brief (PWM) PWM Comparison 7 Value Register */\r
+#define REG_PWM_CMPVUPD7 (0x400001A4U) /**< \brief (PWM) PWM Comparison 7 Value Update Register */\r
+#define REG_PWM_CMPM7 (0x400001A8U) /**< \brief (PWM) PWM Comparison 7 Mode Register */\r
+#define REG_PWM_CMPMUPD7 (0x400001ACU) /**< \brief (PWM) PWM Comparison 7 Mode Update Register */\r
+#define REG_PWM_CMR0 (0x40000200U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 0) */\r
+#define REG_PWM_CDTY0 (0x40000204U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 0) */\r
+#define REG_PWM_CDTYUPD0 (0x40000208U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 0) */\r
+#define REG_PWM_CPRD0 (0x4000020CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 0) */\r
+#define REG_PWM_CPRDUPD0 (0x40000210U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 0) */\r
+#define REG_PWM_CCNT0 (0x40000214U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 0) */\r
+#define REG_PWM_DT0 (0x40000218U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 0) */\r
+#define REG_PWM_DTUPD0 (0x4000021CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 0) */\r
+#define REG_PWM_CMR1 (0x40000220U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 1) */\r
+#define REG_PWM_CDTY1 (0x40000224U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 1) */\r
+#define REG_PWM_CDTYUPD1 (0x40000228U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 1) */\r
+#define REG_PWM_CPRD1 (0x4000022CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 1) */\r
+#define REG_PWM_CPRDUPD1 (0x40000230U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 1) */\r
+#define REG_PWM_CCNT1 (0x40000234U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 1) */\r
+#define REG_PWM_DT1 (0x40000238U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 1) */\r
+#define REG_PWM_DTUPD1 (0x4000023CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 1) */\r
+#define REG_PWM_CMR2 (0x40000240U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 2) */\r
+#define REG_PWM_CDTY2 (0x40000244U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 2) */\r
+#define REG_PWM_CDTYUPD2 (0x40000248U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 2) */\r
+#define REG_PWM_CPRD2 (0x4000024CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 2) */\r
+#define REG_PWM_CPRDUPD2 (0x40000250U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 2) */\r
+#define REG_PWM_CCNT2 (0x40000254U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 2) */\r
+#define REG_PWM_DT2 (0x40000258U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 2) */\r
+#define REG_PWM_DTUPD2 (0x4000025CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 2) */\r
+#define REG_PWM_CMR3 (0x40000260U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 3) */\r
+#define REG_PWM_CDTY3 (0x40000264U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 3) */\r
+#define REG_PWM_CDTYUPD3 (0x40000268U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 3) */\r
+#define REG_PWM_CPRD3 (0x4000026CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 3) */\r
+#define REG_PWM_CPRDUPD3 (0x40000270U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 3) */\r
+#define REG_PWM_CCNT3 (0x40000274U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 3) */\r
+#define REG_PWM_DT3 (0x40000278U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 3) */\r
+#define REG_PWM_DTUPD3 (0x4000027CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 3) */\r
+#define REG_PWM_CMUPD0 (0x40000400U) /**< \brief (PWM) PWM Channel Mode Update Register (ch_num = 0) */\r
+#define REG_PWM_CAE0 (0x40000404U) /**< \brief (PWM) PWM Channel Additional Edge Register (ch_num = 0) */\r
+#define REG_PWM_CAEUPD0 (0x40000408U) /**< \brief (PWM) PWM Channel Additional Edge Update Register (ch_num = 0) */\r
+#define REG_PWM_CMUPD1 (0x40000420U) /**< \brief (PWM) PWM Channel Mode Update Register (ch_num = 1) */\r
+#define REG_PWM_CAE1 (0x40000424U) /**< \brief (PWM) PWM Channel Additional Edge Register (ch_num = 1) */\r
+#define REG_PWM_CAEUPD1 (0x40000428U) /**< \brief (PWM) PWM Channel Additional Edge Update Register (ch_num = 1) */\r
+#define REG_PWM_CMUPD2 (0x40000440U) /**< \brief (PWM) PWM Channel Mode Update Register (ch_num = 2) */\r
+#define REG_PWM_CAE2 (0x40000444U) /**< \brief (PWM) PWM Channel Additional Edge Register (ch_num = 2) */\r
+#define REG_PWM_CAEUPD2 (0x40000448U) /**< \brief (PWM) PWM Channel Additional Edge Update Register (ch_num = 2) */\r
+#define REG_PWM_CMUPD3 (0x40000460U) /**< \brief (PWM) PWM Channel Mode Update Register (ch_num = 3) */\r
+#define REG_PWM_CAE3 (0x40000464U) /**< \brief (PWM) PWM Channel Additional Edge Register (ch_num = 3) */\r
+#define REG_PWM_CAEUPD3 (0x40000468U) /**< \brief (PWM) PWM Channel Additional Edge Update Register (ch_num = 3) */\r
+#else\r
+#define REG_PWM_CLK (*(RwReg*)0x40000000U) /**< \brief (PWM) PWM Clock Register */\r
+#define REG_PWM_ENA (*(WoReg*)0x40000004U) /**< \brief (PWM) PWM Enable Register */\r
+#define REG_PWM_DIS (*(WoReg*)0x40000008U) /**< \brief (PWM) PWM Disable Register */\r
+#define REG_PWM_SR (*(RoReg*)0x4000000CU) /**< \brief (PWM) PWM Status Register */\r
+#define REG_PWM_IER1 (*(WoReg*)0x40000010U) /**< \brief (PWM) PWM Interrupt Enable Register 1 */\r
+#define REG_PWM_IDR1 (*(WoReg*)0x40000014U) /**< \brief (PWM) PWM Interrupt Disable Register 1 */\r
+#define REG_PWM_IMR1 (*(RoReg*)0x40000018U) /**< \brief (PWM) PWM Interrupt Mask Register 1 */\r
+#define REG_PWM_ISR1 (*(RoReg*)0x4000001CU) /**< \brief (PWM) PWM Interrupt Status Register 1 */\r
+#define REG_PWM_SCM (*(RwReg*)0x40000020U) /**< \brief (PWM) PWM Sync Channels Mode Register */\r
+#define REG_PWM_SCUC (*(RwReg*)0x40000028U) /**< \brief (PWM) PWM Sync Channels Update Control Register */\r
+#define REG_PWM_SCUP (*(RwReg*)0x4000002CU) /**< \brief (PWM) PWM Sync Channels Update Period Register */\r
+#define REG_PWM_SCUPUPD (*(WoReg*)0x40000030U) /**< \brief (PWM) PWM Sync Channels Update Period Update Register */\r
+#define REG_PWM_IER2 (*(WoReg*)0x40000034U) /**< \brief (PWM) PWM Interrupt Enable Register 2 */\r
+#define REG_PWM_IDR2 (*(WoReg*)0x40000038U) /**< \brief (PWM) PWM Interrupt Disable Register 2 */\r
+#define REG_PWM_IMR2 (*(RoReg*)0x4000003CU) /**< \brief (PWM) PWM Interrupt Mask Register 2 */\r
+#define REG_PWM_ISR2 (*(RoReg*)0x40000040U) /**< \brief (PWM) PWM Interrupt Status Register 2 */\r
+#define REG_PWM_OOV (*(RwReg*)0x40000044U) /**< \brief (PWM) PWM Output Override Value Register */\r
+#define REG_PWM_OS (*(RwReg*)0x40000048U) /**< \brief (PWM) PWM Output Selection Register */\r
+#define REG_PWM_OSS (*(WoReg*)0x4000004CU) /**< \brief (PWM) PWM Output Selection Set Register */\r
+#define REG_PWM_OSC (*(WoReg*)0x40000050U) /**< \brief (PWM) PWM Output Selection Clear Register */\r
+#define REG_PWM_OSSUPD (*(WoReg*)0x40000054U) /**< \brief (PWM) PWM Output Selection Set Update Register */\r
+#define REG_PWM_OSCUPD (*(WoReg*)0x40000058U) /**< \brief (PWM) PWM Output Selection Clear Update Register */\r
+#define REG_PWM_FMR (*(RwReg*)0x4000005CU) /**< \brief (PWM) PWM Fault Mode Register */\r
+#define REG_PWM_FSR (*(RoReg*)0x40000060U) /**< \brief (PWM) PWM Fault Status Register */\r
+#define REG_PWM_FCR (*(WoReg*)0x40000064U) /**< \brief (PWM) PWM Fault Clear Register */\r
+#define REG_PWM_FPV1 (*(RwReg*)0x40000068U) /**< \brief (PWM) PWM Fault Protection Value Register 1 */\r
+#define REG_PWM_FPE (*(RwReg*)0x4000006CU) /**< \brief (PWM) PWM Fault Protection Enable Register */\r
+#define REG_PWM_ELMR (*(RwReg*)0x4000007CU) /**< \brief (PWM) PWM Event Line 0 Mode Register */\r
+#define REG_PWM_SSPR (*(RwReg*)0x400000A0U) /**< \brief (PWM) PWM Spread Spectrum Register */\r
+#define REG_PWM_SSPUP (*(WoReg*)0x400000A4U) /**< \brief (PWM) PWM Spread Spectrum Update Register */\r
+#define REG_PWM_SMMR (*(RwReg*)0x400000B0U) /**< \brief (PWM) PWM Stepper Motor Mode Register */\r
+#define REG_PWM_FPV2 (*(RwReg*)0x400000C0U) /**< \brief (PWM) PWM Fault Protection Value 2 Register */\r
+#define REG_PWM_WPCR (*(WoReg*)0x400000E4U) /**< \brief (PWM) PWM Write Protect Control Register */\r
+#define REG_PWM_WPSR (*(RoReg*)0x400000E8U) /**< \brief (PWM) PWM Write Protect Status Register */\r
+#define REG_PWM_TPR (*(RwReg*)0x40000108U) /**< \brief (PWM) Transmit Pointer Register */\r
+#define REG_PWM_TCR (*(RwReg*)0x4000010CU) /**< \brief (PWM) Transmit Counter Register */\r
+#define REG_PWM_TNPR (*(RwReg*)0x40000118U) /**< \brief (PWM) Transmit Next Pointer Register */\r
+#define REG_PWM_TNCR (*(RwReg*)0x4000011CU) /**< \brief (PWM) Transmit Next Counter Register */\r
+#define REG_PWM_PTCR (*(WoReg*)0x40000120U) /**< \brief (PWM) Transfer Control Register */\r
+#define REG_PWM_PTSR (*(RoReg*)0x40000124U) /**< \brief (PWM) Transfer Status Register */\r
+#define REG_PWM_CMPV0 (*(RwReg*)0x40000130U) /**< \brief (PWM) PWM Comparison 0 Value Register */\r
+#define REG_PWM_CMPVUPD0 (*(WoReg*)0x40000134U) /**< \brief (PWM) PWM Comparison 0 Value Update Register */\r
+#define REG_PWM_CMPM0 (*(RwReg*)0x40000138U) /**< \brief (PWM) PWM Comparison 0 Mode Register */\r
+#define REG_PWM_CMPMUPD0 (*(WoReg*)0x4000013CU) /**< \brief (PWM) PWM Comparison 0 Mode Update Register */\r
+#define REG_PWM_CMPV1 (*(RwReg*)0x40000140U) /**< \brief (PWM) PWM Comparison 1 Value Register */\r
+#define REG_PWM_CMPVUPD1 (*(WoReg*)0x40000144U) /**< \brief (PWM) PWM Comparison 1 Value Update Register */\r
+#define REG_PWM_CMPM1 (*(RwReg*)0x40000148U) /**< \brief (PWM) PWM Comparison 1 Mode Register */\r
+#define REG_PWM_CMPMUPD1 (*(WoReg*)0x4000014CU) /**< \brief (PWM) PWM Comparison 1 Mode Update Register */\r
+#define REG_PWM_CMPV2 (*(RwReg*)0x40000150U) /**< \brief (PWM) PWM Comparison 2 Value Register */\r
+#define REG_PWM_CMPVUPD2 (*(WoReg*)0x40000154U) /**< \brief (PWM) PWM Comparison 2 Value Update Register */\r
+#define REG_PWM_CMPM2 (*(RwReg*)0x40000158U) /**< \brief (PWM) PWM Comparison 2 Mode Register */\r
+#define REG_PWM_CMPMUPD2 (*(WoReg*)0x4000015CU) /**< \brief (PWM) PWM Comparison 2 Mode Update Register */\r
+#define REG_PWM_CMPV3 (*(RwReg*)0x40000160U) /**< \brief (PWM) PWM Comparison 3 Value Register */\r
+#define REG_PWM_CMPVUPD3 (*(WoReg*)0x40000164U) /**< \brief (PWM) PWM Comparison 3 Value Update Register */\r
+#define REG_PWM_CMPM3 (*(RwReg*)0x40000168U) /**< \brief (PWM) PWM Comparison 3 Mode Register */\r
+#define REG_PWM_CMPMUPD3 (*(WoReg*)0x4000016CU) /**< \brief (PWM) PWM Comparison 3 Mode Update Register */\r
+#define REG_PWM_CMPV4 (*(RwReg*)0x40000170U) /**< \brief (PWM) PWM Comparison 4 Value Register */\r
+#define REG_PWM_CMPVUPD4 (*(WoReg*)0x40000174U) /**< \brief (PWM) PWM Comparison 4 Value Update Register */\r
+#define REG_PWM_CMPM4 (*(RwReg*)0x40000178U) /**< \brief (PWM) PWM Comparison 4 Mode Register */\r
+#define REG_PWM_CMPMUPD4 (*(WoReg*)0x4000017CU) /**< \brief (PWM) PWM Comparison 4 Mode Update Register */\r
+#define REG_PWM_CMPV5 (*(RwReg*)0x40000180U) /**< \brief (PWM) PWM Comparison 5 Value Register */\r
+#define REG_PWM_CMPVUPD5 (*(WoReg*)0x40000184U) /**< \brief (PWM) PWM Comparison 5 Value Update Register */\r
+#define REG_PWM_CMPM5 (*(RwReg*)0x40000188U) /**< \brief (PWM) PWM Comparison 5 Mode Register */\r
+#define REG_PWM_CMPMUPD5 (*(WoReg*)0x4000018CU) /**< \brief (PWM) PWM Comparison 5 Mode Update Register */\r
+#define REG_PWM_CMPV6 (*(RwReg*)0x40000190U) /**< \brief (PWM) PWM Comparison 6 Value Register */\r
+#define REG_PWM_CMPVUPD6 (*(WoReg*)0x40000194U) /**< \brief (PWM) PWM Comparison 6 Value Update Register */\r
+#define REG_PWM_CMPM6 (*(RwReg*)0x40000198U) /**< \brief (PWM) PWM Comparison 6 Mode Register */\r
+#define REG_PWM_CMPMUPD6 (*(WoReg*)0x4000019CU) /**< \brief (PWM) PWM Comparison 6 Mode Update Register */\r
+#define REG_PWM_CMPV7 (*(RwReg*)0x400001A0U) /**< \brief (PWM) PWM Comparison 7 Value Register */\r
+#define REG_PWM_CMPVUPD7 (*(WoReg*)0x400001A4U) /**< \brief (PWM) PWM Comparison 7 Value Update Register */\r
+#define REG_PWM_CMPM7 (*(RwReg*)0x400001A8U) /**< \brief (PWM) PWM Comparison 7 Mode Register */\r
+#define REG_PWM_CMPMUPD7 (*(WoReg*)0x400001ACU) /**< \brief (PWM) PWM Comparison 7 Mode Update Register */\r
+#define REG_PWM_CMR0 (*(RwReg*)0x40000200U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 0) */\r
+#define REG_PWM_CDTY0 (*(RwReg*)0x40000204U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 0) */\r
+#define REG_PWM_CDTYUPD0 (*(WoReg*)0x40000208U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 0) */\r
+#define REG_PWM_CPRD0 (*(RwReg*)0x4000020CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 0) */\r
+#define REG_PWM_CPRDUPD0 (*(WoReg*)0x40000210U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 0) */\r
+#define REG_PWM_CCNT0 (*(RoReg*)0x40000214U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 0) */\r
+#define REG_PWM_DT0 (*(RwReg*)0x40000218U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 0) */\r
+#define REG_PWM_DTUPD0 (*(WoReg*)0x4000021CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 0) */\r
+#define REG_PWM_CMR1 (*(RwReg*)0x40000220U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 1) */\r
+#define REG_PWM_CDTY1 (*(RwReg*)0x40000224U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 1) */\r
+#define REG_PWM_CDTYUPD1 (*(WoReg*)0x40000228U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 1) */\r
+#define REG_PWM_CPRD1 (*(RwReg*)0x4000022CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 1) */\r
+#define REG_PWM_CPRDUPD1 (*(WoReg*)0x40000230U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 1) */\r
+#define REG_PWM_CCNT1 (*(RoReg*)0x40000234U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 1) */\r
+#define REG_PWM_DT1 (*(RwReg*)0x40000238U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 1) */\r
+#define REG_PWM_DTUPD1 (*(WoReg*)0x4000023CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 1) */\r
+#define REG_PWM_CMR2 (*(RwReg*)0x40000240U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 2) */\r
+#define REG_PWM_CDTY2 (*(RwReg*)0x40000244U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 2) */\r
+#define REG_PWM_CDTYUPD2 (*(WoReg*)0x40000248U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 2) */\r
+#define REG_PWM_CPRD2 (*(RwReg*)0x4000024CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 2) */\r
+#define REG_PWM_CPRDUPD2 (*(WoReg*)0x40000250U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 2) */\r
+#define REG_PWM_CCNT2 (*(RoReg*)0x40000254U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 2) */\r
+#define REG_PWM_DT2 (*(RwReg*)0x40000258U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 2) */\r
+#define REG_PWM_DTUPD2 (*(WoReg*)0x4000025CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 2) */\r
+#define REG_PWM_CMR3 (*(RwReg*)0x40000260U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 3) */\r
+#define REG_PWM_CDTY3 (*(RwReg*)0x40000264U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 3) */\r
+#define REG_PWM_CDTYUPD3 (*(WoReg*)0x40000268U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 3) */\r
+#define REG_PWM_CPRD3 (*(RwReg*)0x4000026CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 3) */\r
+#define REG_PWM_CPRDUPD3 (*(WoReg*)0x40000270U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 3) */\r
+#define REG_PWM_CCNT3 (*(RoReg*)0x40000274U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 3) */\r
+#define REG_PWM_DT3 (*(RwReg*)0x40000278U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 3) */\r
+#define REG_PWM_DTUPD3 (*(WoReg*)0x4000027CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 3) */\r
+#define REG_PWM_CMUPD0 (*(WoReg*)0x40000400U) /**< \brief (PWM) PWM Channel Mode Update Register (ch_num = 0) */\r
+#define REG_PWM_CAE0 (*(RwReg*)0x40000404U) /**< \brief (PWM) PWM Channel Additional Edge Register (ch_num = 0) */\r
+#define REG_PWM_CAEUPD0 (*(WoReg*)0x40000408U) /**< \brief (PWM) PWM Channel Additional Edge Update Register (ch_num = 0) */\r
+#define REG_PWM_CMUPD1 (*(WoReg*)0x40000420U) /**< \brief (PWM) PWM Channel Mode Update Register (ch_num = 1) */\r
+#define REG_PWM_CAE1 (*(RwReg*)0x40000424U) /**< \brief (PWM) PWM Channel Additional Edge Register (ch_num = 1) */\r
+#define REG_PWM_CAEUPD1 (*(WoReg*)0x40000428U) /**< \brief (PWM) PWM Channel Additional Edge Update Register (ch_num = 1) */\r
+#define REG_PWM_CMUPD2 (*(WoReg*)0x40000440U) /**< \brief (PWM) PWM Channel Mode Update Register (ch_num = 2) */\r
+#define REG_PWM_CAE2 (*(RwReg*)0x40000444U) /**< \brief (PWM) PWM Channel Additional Edge Register (ch_num = 2) */\r
+#define REG_PWM_CAEUPD2 (*(WoReg*)0x40000448U) /**< \brief (PWM) PWM Channel Additional Edge Update Register (ch_num = 2) */\r
+#define REG_PWM_CMUPD3 (*(WoReg*)0x40000460U) /**< \brief (PWM) PWM Channel Mode Update Register (ch_num = 3) */\r
+#define REG_PWM_CAE3 (*(RwReg*)0x40000464U) /**< \brief (PWM) PWM Channel Additional Edge Register (ch_num = 3) */\r
+#define REG_PWM_CAEUPD3 (*(WoReg*)0x40000468U) /**< \brief (PWM) PWM Channel Additional Edge Update Register (ch_num = 3) */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM4E_PWM_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4E_RSTC_INSTANCE_\r
+#define _SAM4E_RSTC_INSTANCE_\r
+\r
+/* ========== Register definition for RSTC peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_RSTC_CR (0x400E1800U) /**< \brief (RSTC) Control Register */\r
+#define REG_RSTC_SR (0x400E1804U) /**< \brief (RSTC) Status Register */\r
+#define REG_RSTC_MR (0x400E1808U) /**< \brief (RSTC) Mode Register */\r
+#else\r
+#define REG_RSTC_CR (*(WoReg*)0x400E1800U) /**< \brief (RSTC) Control Register */\r
+#define REG_RSTC_SR (*(RoReg*)0x400E1804U) /**< \brief (RSTC) Status Register */\r
+#define REG_RSTC_MR (*(RwReg*)0x400E1808U) /**< \brief (RSTC) Mode Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM4E_RSTC_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4E_RSWDT_INSTANCE_\r
+#define _SAM4E_RSWDT_INSTANCE_\r
+\r
+/* ========== Register definition for RSWDT peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_RSWDT_CR (0x400E1900U) /**< \brief (RSWDT) Control Register */\r
+#define REG_RSWDT_MR (0x400E1904U) /**< \brief (RSWDT) Mode Register */\r
+#define REG_RSWDT_SR (0x400E1908U) /**< \brief (RSWDT) Status Register */\r
+#else\r
+#define REG_RSWDT_CR (*(WoReg*)0x400E1900U) /**< \brief (RSWDT) Control Register */\r
+#define REG_RSWDT_MR (*(RwReg*)0x400E1904U) /**< \brief (RSWDT) Mode Register */\r
+#define REG_RSWDT_SR (*(RoReg*)0x400E1908U) /**< \brief (RSWDT) Status Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM4E_RSWDT_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4E_RTC_INSTANCE_\r
+#define _SAM4E_RTC_INSTANCE_\r
+\r
+/* ========== Register definition for RTC peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_RTC_CR (0x400E1860U) /**< \brief (RTC) Control Register */\r
+#define REG_RTC_MR (0x400E1864U) /**< \brief (RTC) Mode Register */\r
+#define REG_RTC_TIMR (0x400E1868U) /**< \brief (RTC) Time Register */\r
+#define REG_RTC_CALR (0x400E186CU) /**< \brief (RTC) Calendar Register */\r
+#define REG_RTC_TIMALR (0x400E1870U) /**< \brief (RTC) Time Alarm Register */\r
+#define REG_RTC_CALALR (0x400E1874U) /**< \brief (RTC) Calendar Alarm Register */\r
+#define REG_RTC_SR (0x400E1878U) /**< \brief (RTC) Status Register */\r
+#define REG_RTC_SCCR (0x400E187CU) /**< \brief (RTC) Status Clear Command Register */\r
+#define REG_RTC_IER (0x400E1880U) /**< \brief (RTC) Interrupt Enable Register */\r
+#define REG_RTC_IDR (0x400E1884U) /**< \brief (RTC) Interrupt Disable Register */\r
+#define REG_RTC_IMR (0x400E1888U) /**< \brief (RTC) Interrupt Mask Register */\r
+#define REG_RTC_VER (0x400E188CU) /**< \brief (RTC) Valid Entry Register */\r
+#else\r
+#define REG_RTC_CR (*(RwReg*)0x400E1860U) /**< \brief (RTC) Control Register */\r
+#define REG_RTC_MR (*(RwReg*)0x400E1864U) /**< \brief (RTC) Mode Register */\r
+#define REG_RTC_TIMR (*(RwReg*)0x400E1868U) /**< \brief (RTC) Time Register */\r
+#define REG_RTC_CALR (*(RwReg*)0x400E186CU) /**< \brief (RTC) Calendar Register */\r
+#define REG_RTC_TIMALR (*(RwReg*)0x400E1870U) /**< \brief (RTC) Time Alarm Register */\r
+#define REG_RTC_CALALR (*(RwReg*)0x400E1874U) /**< \brief (RTC) Calendar Alarm Register */\r
+#define REG_RTC_SR (*(RoReg*)0x400E1878U) /**< \brief (RTC) Status Register */\r
+#define REG_RTC_SCCR (*(WoReg*)0x400E187CU) /**< \brief (RTC) Status Clear Command Register */\r
+#define REG_RTC_IER (*(WoReg*)0x400E1880U) /**< \brief (RTC) Interrupt Enable Register */\r
+#define REG_RTC_IDR (*(WoReg*)0x400E1884U) /**< \brief (RTC) Interrupt Disable Register */\r
+#define REG_RTC_IMR (*(RoReg*)0x400E1888U) /**< \brief (RTC) Interrupt Mask Register */\r
+#define REG_RTC_VER (*(RoReg*)0x400E188CU) /**< \brief (RTC) Valid Entry Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM4E_RTC_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4E_RTT_INSTANCE_\r
+#define _SAM4E_RTT_INSTANCE_\r
+\r
+/* ========== Register definition for RTT peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_RTT_MR (0x400E1830U) /**< \brief (RTT) Mode Register */\r
+#define REG_RTT_AR (0x400E1834U) /**< \brief (RTT) Alarm Register */\r
+#define REG_RTT_VR (0x400E1838U) /**< \brief (RTT) Value Register */\r
+#define REG_RTT_SR (0x400E183CU) /**< \brief (RTT) Status Register */\r
+#else\r
+#define REG_RTT_MR (*(RwReg*)0x400E1830U) /**< \brief (RTT) Mode Register */\r
+#define REG_RTT_AR (*(RwReg*)0x400E1834U) /**< \brief (RTT) Alarm Register */\r
+#define REG_RTT_VR (*(RoReg*)0x400E1838U) /**< \brief (RTT) Value Register */\r
+#define REG_RTT_SR (*(RoReg*)0x400E183CU) /**< \brief (RTT) Status Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM4E_RTT_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4E_SMC_INSTANCE_\r
+#define _SAM4E_SMC_INSTANCE_\r
+\r
+/* ========== Register definition for SMC peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_SMC_SETUP0 (0x40060000U) /**< \brief (SMC) SMC Setup Register (CS_number = 0) */\r
+#define REG_SMC_PULSE0 (0x40060004U) /**< \brief (SMC) SMC Pulse Register (CS_number = 0) */\r
+#define REG_SMC_CYCLE0 (0x40060008U) /**< \brief (SMC) SMC Cycle Register (CS_number = 0) */\r
+#define REG_SMC_MODE0 (0x4006000CU) /**< \brief (SMC) SMC Mode Register (CS_number = 0) */\r
+#define REG_SMC_SETUP1 (0x40060010U) /**< \brief (SMC) SMC Setup Register (CS_number = 1) */\r
+#define REG_SMC_PULSE1 (0x40060014U) /**< \brief (SMC) SMC Pulse Register (CS_number = 1) */\r
+#define REG_SMC_CYCLE1 (0x40060018U) /**< \brief (SMC) SMC Cycle Register (CS_number = 1) */\r
+#define REG_SMC_MODE1 (0x4006001CU) /**< \brief (SMC) SMC Mode Register (CS_number = 1) */\r
+#define REG_SMC_SETUP2 (0x40060020U) /**< \brief (SMC) SMC Setup Register (CS_number = 2) */\r
+#define REG_SMC_PULSE2 (0x40060024U) /**< \brief (SMC) SMC Pulse Register (CS_number = 2) */\r
+#define REG_SMC_CYCLE2 (0x40060028U) /**< \brief (SMC) SMC Cycle Register (CS_number = 2) */\r
+#define REG_SMC_MODE2 (0x4006002CU) /**< \brief (SMC) SMC Mode Register (CS_number = 2) */\r
+#define REG_SMC_SETUP3 (0x40060030U) /**< \brief (SMC) SMC Setup Register (CS_number = 3) */\r
+#define REG_SMC_PULSE3 (0x40060034U) /**< \brief (SMC) SMC Pulse Register (CS_number = 3) */\r
+#define REG_SMC_CYCLE3 (0x40060038U) /**< \brief (SMC) SMC Cycle Register (CS_number = 3) */\r
+#define REG_SMC_MODE3 (0x4006003CU) /**< \brief (SMC) SMC Mode Register (CS_number = 3) */\r
+#define REG_SMC_OCMS (0x40060080U) /**< \brief (SMC) SMC OCMS MODE Register */\r
+#define REG_SMC_KEY1 (0x40060084U) /**< \brief (SMC) SMC OCMS KEY1 Register */\r
+#define REG_SMC_KEY2 (0x40060088U) /**< \brief (SMC) SMC OCMS KEY2 Register */\r
+#define REG_SMC_WPMR (0x400600E4U) /**< \brief (SMC) SMC Write Protect Mode Register */\r
+#define REG_SMC_WPSR (0x400600E8U) /**< \brief (SMC) SMC Write Protect Status Register */\r
+#else\r
+#define REG_SMC_SETUP0 (*(RwReg*)0x40060000U) /**< \brief (SMC) SMC Setup Register (CS_number = 0) */\r
+#define REG_SMC_PULSE0 (*(RwReg*)0x40060004U) /**< \brief (SMC) SMC Pulse Register (CS_number = 0) */\r
+#define REG_SMC_CYCLE0 (*(RwReg*)0x40060008U) /**< \brief (SMC) SMC Cycle Register (CS_number = 0) */\r
+#define REG_SMC_MODE0 (*(RwReg*)0x4006000CU) /**< \brief (SMC) SMC Mode Register (CS_number = 0) */\r
+#define REG_SMC_SETUP1 (*(RwReg*)0x40060010U) /**< \brief (SMC) SMC Setup Register (CS_number = 1) */\r
+#define REG_SMC_PULSE1 (*(RwReg*)0x40060014U) /**< \brief (SMC) SMC Pulse Register (CS_number = 1) */\r
+#define REG_SMC_CYCLE1 (*(RwReg*)0x40060018U) /**< \brief (SMC) SMC Cycle Register (CS_number = 1) */\r
+#define REG_SMC_MODE1 (*(RwReg*)0x4006001CU) /**< \brief (SMC) SMC Mode Register (CS_number = 1) */\r
+#define REG_SMC_SETUP2 (*(RwReg*)0x40060020U) /**< \brief (SMC) SMC Setup Register (CS_number = 2) */\r
+#define REG_SMC_PULSE2 (*(RwReg*)0x40060024U) /**< \brief (SMC) SMC Pulse Register (CS_number = 2) */\r
+#define REG_SMC_CYCLE2 (*(RwReg*)0x40060028U) /**< \brief (SMC) SMC Cycle Register (CS_number = 2) */\r
+#define REG_SMC_MODE2 (*(RwReg*)0x4006002CU) /**< \brief (SMC) SMC Mode Register (CS_number = 2) */\r
+#define REG_SMC_SETUP3 (*(RwReg*)0x40060030U) /**< \brief (SMC) SMC Setup Register (CS_number = 3) */\r
+#define REG_SMC_PULSE3 (*(RwReg*)0x40060034U) /**< \brief (SMC) SMC Pulse Register (CS_number = 3) */\r
+#define REG_SMC_CYCLE3 (*(RwReg*)0x40060038U) /**< \brief (SMC) SMC Cycle Register (CS_number = 3) */\r
+#define REG_SMC_MODE3 (*(RwReg*)0x4006003CU) /**< \brief (SMC) SMC Mode Register (CS_number = 3) */\r
+#define REG_SMC_OCMS (*(RwReg*)0x40060080U) /**< \brief (SMC) SMC OCMS MODE Register */\r
+#define REG_SMC_KEY1 (*(WoReg*)0x40060084U) /**< \brief (SMC) SMC OCMS KEY1 Register */\r
+#define REG_SMC_KEY2 (*(WoReg*)0x40060088U) /**< \brief (SMC) SMC OCMS KEY2 Register */\r
+#define REG_SMC_WPMR (*(RwReg*)0x400600E4U) /**< \brief (SMC) SMC Write Protect Mode Register */\r
+#define REG_SMC_WPSR (*(RoReg*)0x400600E8U) /**< \brief (SMC) SMC Write Protect Status Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM4E_SMC_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4E_SPI_INSTANCE_\r
+#define _SAM4E_SPI_INSTANCE_\r
+\r
+/* ========== Register definition for SPI peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_SPI_CR (0x40088000U) /**< \brief (SPI) Control Register */\r
+#define REG_SPI_MR (0x40088004U) /**< \brief (SPI) Mode Register */\r
+#define REG_SPI_RDR (0x40088008U) /**< \brief (SPI) Receive Data Register */\r
+#define REG_SPI_TDR (0x4008800CU) /**< \brief (SPI) Transmit Data Register */\r
+#define REG_SPI_SR (0x40088010U) /**< \brief (SPI) Status Register */\r
+#define REG_SPI_IER (0x40088014U) /**< \brief (SPI) Interrupt Enable Register */\r
+#define REG_SPI_IDR (0x40088018U) /**< \brief (SPI) Interrupt Disable Register */\r
+#define REG_SPI_IMR (0x4008801CU) /**< \brief (SPI) Interrupt Mask Register */\r
+#define REG_SPI_CSR (0x40088030U) /**< \brief (SPI) Chip Select Register */\r
+#define REG_SPI_WPMR (0x400880E4U) /**< \brief (SPI) Write Protection Control Register */\r
+#define REG_SPI_WPSR (0x400880E8U) /**< \brief (SPI) Write Protection Status Register */\r
+#define REG_SPI_RPR (0x40088100U) /**< \brief (SPI) Receive Pointer Register */\r
+#define REG_SPI_RCR (0x40088104U) /**< \brief (SPI) Receive Counter Register */\r
+#define REG_SPI_TPR (0x40088108U) /**< \brief (SPI) Transmit Pointer Register */\r
+#define REG_SPI_TCR (0x4008810CU) /**< \brief (SPI) Transmit Counter Register */\r
+#define REG_SPI_RNPR (0x40088110U) /**< \brief (SPI) Receive Next Pointer Register */\r
+#define REG_SPI_RNCR (0x40088114U) /**< \brief (SPI) Receive Next Counter Register */\r
+#define REG_SPI_TNPR (0x40088118U) /**< \brief (SPI) Transmit Next Pointer Register */\r
+#define REG_SPI_TNCR (0x4008811CU) /**< \brief (SPI) Transmit Next Counter Register */\r
+#define REG_SPI_PTCR (0x40088120U) /**< \brief (SPI) Transfer Control Register */\r
+#define REG_SPI_PTSR (0x40088124U) /**< \brief (SPI) Transfer Status Register */\r
+#else\r
+#define REG_SPI_CR (*(WoReg*)0x40088000U) /**< \brief (SPI) Control Register */\r
+#define REG_SPI_MR (*(RwReg*)0x40088004U) /**< \brief (SPI) Mode Register */\r
+#define REG_SPI_RDR (*(RoReg*)0x40088008U) /**< \brief (SPI) Receive Data Register */\r
+#define REG_SPI_TDR (*(WoReg*)0x4008800CU) /**< \brief (SPI) Transmit Data Register */\r
+#define REG_SPI_SR (*(RoReg*)0x40088010U) /**< \brief (SPI) Status Register */\r
+#define REG_SPI_IER (*(WoReg*)0x40088014U) /**< \brief (SPI) Interrupt Enable Register */\r
+#define REG_SPI_IDR (*(WoReg*)0x40088018U) /**< \brief (SPI) Interrupt Disable Register */\r
+#define REG_SPI_IMR (*(RoReg*)0x4008801CU) /**< \brief (SPI) Interrupt Mask Register */\r
+#define REG_SPI_CSR (*(RwReg*)0x40088030U) /**< \brief (SPI) Chip Select Register */\r
+#define REG_SPI_WPMR (*(RwReg*)0x400880E4U) /**< \brief (SPI) Write Protection Control Register */\r
+#define REG_SPI_WPSR (*(RoReg*)0x400880E8U) /**< \brief (SPI) Write Protection Status Register */\r
+#define REG_SPI_RPR (*(RwReg*)0x40088100U) /**< \brief (SPI) Receive Pointer Register */\r
+#define REG_SPI_RCR (*(RwReg*)0x40088104U) /**< \brief (SPI) Receive Counter Register */\r
+#define REG_SPI_TPR (*(RwReg*)0x40088108U) /**< \brief (SPI) Transmit Pointer Register */\r
+#define REG_SPI_TCR (*(RwReg*)0x4008810CU) /**< \brief (SPI) Transmit Counter Register */\r
+#define REG_SPI_RNPR (*(RwReg*)0x40088110U) /**< \brief (SPI) Receive Next Pointer Register */\r
+#define REG_SPI_RNCR (*(RwReg*)0x40088114U) /**< \brief (SPI) Receive Next Counter Register */\r
+#define REG_SPI_TNPR (*(RwReg*)0x40088118U) /**< \brief (SPI) Transmit Next Pointer Register */\r
+#define REG_SPI_TNCR (*(RwReg*)0x4008811CU) /**< \brief (SPI) Transmit Next Counter Register */\r
+#define REG_SPI_PTCR (*(WoReg*)0x40088120U) /**< \brief (SPI) Transfer Control Register */\r
+#define REG_SPI_PTSR (*(RoReg*)0x40088124U) /**< \brief (SPI) Transfer Status Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM4E_SPI_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4E_SUPC_INSTANCE_\r
+#define _SAM4E_SUPC_INSTANCE_\r
+\r
+/* ========== Register definition for SUPC peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_SUPC_CR (0x400E1810U) /**< \brief (SUPC) Supply Controller Control Register */\r
+#define REG_SUPC_SMMR (0x400E1814U) /**< \brief (SUPC) Supply Controller Supply Monitor Mode Register */\r
+#define REG_SUPC_MR (0x400E1818U) /**< \brief (SUPC) Supply Controller Mode Register */\r
+#define REG_SUPC_WUMR (0x400E181CU) /**< \brief (SUPC) Supply Controller Wake-up Mode Register */\r
+#define REG_SUPC_WUIR (0x400E1820U) /**< \brief (SUPC) Supply Controller Wake-up Inputs Register */\r
+#define REG_SUPC_SR (0x400E1824U) /**< \brief (SUPC) Supply Controller Status Register */\r
+#else\r
+#define REG_SUPC_CR (*(WoReg*)0x400E1810U) /**< \brief (SUPC) Supply Controller Control Register */\r
+#define REG_SUPC_SMMR (*(RwReg*)0x400E1814U) /**< \brief (SUPC) Supply Controller Supply Monitor Mode Register */\r
+#define REG_SUPC_MR (*(RwReg*)0x400E1818U) /**< \brief (SUPC) Supply Controller Mode Register */\r
+#define REG_SUPC_WUMR (*(RwReg*)0x400E181CU) /**< \brief (SUPC) Supply Controller Wake-up Mode Register */\r
+#define REG_SUPC_WUIR (*(RwReg*)0x400E1820U) /**< \brief (SUPC) Supply Controller Wake-up Inputs Register */\r
+#define REG_SUPC_SR (*(RoReg*)0x400E1824U) /**< \brief (SUPC) Supply Controller Status Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM4E_SUPC_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4E_TC0_INSTANCE_\r
+#define _SAM4E_TC0_INSTANCE_\r
+\r
+/* ========== Register definition for TC0 peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_TC0_CCR0 (0x40090000U) /**< \brief (TC0) Channel Control Register (channel = 0) */\r
+#define REG_TC0_CMR0 (0x40090004U) /**< \brief (TC0) Channel Mode Register (channel = 0) */\r
+#define REG_TC0_SMMR0 (0x40090008U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 0) */\r
+#define REG_TC0_RAB0 (0x4009000CU) /**< \brief (TC0) Register AB (channel = 0) */\r
+#define REG_TC0_CV0 (0x40090010U) /**< \brief (TC0) Counter Value (channel = 0) */\r
+#define REG_TC0_RA0 (0x40090014U) /**< \brief (TC0) Register A (channel = 0) */\r
+#define REG_TC0_RB0 (0x40090018U) /**< \brief (TC0) Register B (channel = 0) */\r
+#define REG_TC0_RC0 (0x4009001CU) /**< \brief (TC0) Register C (channel = 0) */\r
+#define REG_TC0_SR0 (0x40090020U) /**< \brief (TC0) Status Register (channel = 0) */\r
+#define REG_TC0_IER0 (0x40090024U) /**< \brief (TC0) Interrupt Enable Register (channel = 0) */\r
+#define REG_TC0_IDR0 (0x40090028U) /**< \brief (TC0) Interrupt Disable Register (channel = 0) */\r
+#define REG_TC0_IMR0 (0x4009002CU) /**< \brief (TC0) Interrupt Mask Register (channel = 0) */\r
+#define REG_TC0_EMR0 (0x40090030U) /**< \brief (TC0) Extended Mode Register (channel = 0) */\r
+#define REG_TC0_CCR1 (0x40090040U) /**< \brief (TC0) Channel Control Register (channel = 1) */\r
+#define REG_TC0_CMR1 (0x40090044U) /**< \brief (TC0) Channel Mode Register (channel = 1) */\r
+#define REG_TC0_SMMR1 (0x40090048U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 1) */\r
+#define REG_TC0_RAB1 (0x4009004CU) /**< \brief (TC0) Register AB (channel = 1) */\r
+#define REG_TC0_CV1 (0x40090050U) /**< \brief (TC0) Counter Value (channel = 1) */\r
+#define REG_TC0_RA1 (0x40090054U) /**< \brief (TC0) Register A (channel = 1) */\r
+#define REG_TC0_RB1 (0x40090058U) /**< \brief (TC0) Register B (channel = 1) */\r
+#define REG_TC0_RC1 (0x4009005CU) /**< \brief (TC0) Register C (channel = 1) */\r
+#define REG_TC0_SR1 (0x40090060U) /**< \brief (TC0) Status Register (channel = 1) */\r
+#define REG_TC0_IER1 (0x40090064U) /**< \brief (TC0) Interrupt Enable Register (channel = 1) */\r
+#define REG_TC0_IDR1 (0x40090068U) /**< \brief (TC0) Interrupt Disable Register (channel = 1) */\r
+#define REG_TC0_IMR1 (0x4009006CU) /**< \brief (TC0) Interrupt Mask Register (channel = 1) */\r
+#define REG_TC0_EMR1 (0x40090070U) /**< \brief (TC0) Extended Mode Register (channel = 1) */\r
+#define REG_TC0_CCR2 (0x40090080U) /**< \brief (TC0) Channel Control Register (channel = 2) */\r
+#define REG_TC0_CMR2 (0x40090084U) /**< \brief (TC0) Channel Mode Register (channel = 2) */\r
+#define REG_TC0_SMMR2 (0x40090088U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 2) */\r
+#define REG_TC0_RAB2 (0x4009008CU) /**< \brief (TC0) Register AB (channel = 2) */\r
+#define REG_TC0_CV2 (0x40090090U) /**< \brief (TC0) Counter Value (channel = 2) */\r
+#define REG_TC0_RA2 (0x40090094U) /**< \brief (TC0) Register A (channel = 2) */\r
+#define REG_TC0_RB2 (0x40090098U) /**< \brief (TC0) Register B (channel = 2) */\r
+#define REG_TC0_RC2 (0x4009009CU) /**< \brief (TC0) Register C (channel = 2) */\r
+#define REG_TC0_SR2 (0x400900A0U) /**< \brief (TC0) Status Register (channel = 2) */\r
+#define REG_TC0_IER2 (0x400900A4U) /**< \brief (TC0) Interrupt Enable Register (channel = 2) */\r
+#define REG_TC0_IDR2 (0x400900A8U) /**< \brief (TC0) Interrupt Disable Register (channel = 2) */\r
+#define REG_TC0_IMR2 (0x400900ACU) /**< \brief (TC0) Interrupt Mask Register (channel = 2) */\r
+#define REG_TC0_EMR2 (0x400900B0U) /**< \brief (TC0) Extended Mode Register (channel = 2) */\r
+#define REG_TC0_BCR (0x400900C0U) /**< \brief (TC0) Block Control Register */\r
+#define REG_TC0_BMR (0x400900C4U) /**< \brief (TC0) Block Mode Register */\r
+#define REG_TC0_QIER (0x400900C8U) /**< \brief (TC0) QDEC Interrupt Enable Register */\r
+#define REG_TC0_QIDR (0x400900CCU) /**< \brief (TC0) QDEC Interrupt Disable Register */\r
+#define REG_TC0_QIMR (0x400900D0U) /**< \brief (TC0) QDEC Interrupt Mask Register */\r
+#define REG_TC0_QISR (0x400900D4U) /**< \brief (TC0) QDEC Interrupt Status Register */\r
+#define REG_TC0_FMR (0x400900D8U) /**< \brief (TC0) Fault Mode Register */\r
+#define REG_TC0_WPMR (0x400900E4U) /**< \brief (TC0) Write Protect Mode Register */\r
+#define REG_TC0_RPR0 (0x40090100U) /**< \brief (TC0) Receive Pointer Register (pdc = 0) */\r
+#define REG_TC0_RCR0 (0x40090104U) /**< \brief (TC0) Receive Counter Register (pdc = 0) */\r
+#define REG_TC0_RNPR0 (0x40090110U) /**< \brief (TC0) Receive Next Pointer Register (pdc = 0) */\r
+#define REG_TC0_RNCR0 (0x40090114U) /**< \brief (TC0) Receive Next Counter Register (pdc = 0) */\r
+#define REG_TC0_PTCR0 (0x40090120U) /**< \brief (TC0) Transfer Control Register (pdc = 0) */\r
+#define REG_TC0_PTSR0 (0x40090124U) /**< \brief (TC0) Transfer Status Register (pdc = 0) */\r
+#define REG_TC0_RPR1 (0x40090140U) /**< \brief (TC0) Receive Pointer Register (pdc = 1) */\r
+#define REG_TC0_RCR1 (0x40090144U) /**< \brief (TC0) Receive Counter Register (pdc = 1) */\r
+#define REG_TC0_RNPR1 (0x40090150U) /**< \brief (TC0) Receive Next Pointer Register (pdc = 1) */\r
+#define REG_TC0_RNCR1 (0x40090154U) /**< \brief (TC0) Receive Next Counter Register (pdc = 1) */\r
+#define REG_TC0_PTCR1 (0x40090160U) /**< \brief (TC0) Transfer Control Register (pdc = 1) */\r
+#define REG_TC0_PTSR1 (0x40090164U) /**< \brief (TC0) Transfer Status Register (pdc = 1) */\r
+#define REG_TC0_RPR2 (0x40090180U) /**< \brief (TC0) Receive Pointer Register (pdc = 2) */\r
+#define REG_TC0_RCR2 (0x40090184U) /**< \brief (TC0) Receive Counter Register (pdc = 2) */\r
+#define REG_TC0_RNPR2 (0x40090190U) /**< \brief (TC0) Receive Next Pointer Register (pdc = 2) */\r
+#define REG_TC0_RNCR2 (0x40090194U) /**< \brief (TC0) Receive Next Counter Register (pdc = 2) */\r
+#define REG_TC0_PTCR2 (0x400901A0U) /**< \brief (TC0) Transfer Control Register (pdc = 2) */\r
+#define REG_TC0_PTSR2 (0x400901A4U) /**< \brief (TC0) Transfer Status Register (pdc = 2) */\r
+#else\r
+#define REG_TC0_CCR0 (*(WoReg*)0x40090000U) /**< \brief (TC0) Channel Control Register (channel = 0) */\r
+#define REG_TC0_CMR0 (*(RwReg*)0x40090004U) /**< \brief (TC0) Channel Mode Register (channel = 0) */\r
+#define REG_TC0_SMMR0 (*(RwReg*)0x40090008U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 0) */\r
+#define REG_TC0_RAB0 (*(RoReg*)0x4009000CU) /**< \brief (TC0) Register AB (channel = 0) */\r
+#define REG_TC0_CV0 (*(RoReg*)0x40090010U) /**< \brief (TC0) Counter Value (channel = 0) */\r
+#define REG_TC0_RA0 (*(RwReg*)0x40090014U) /**< \brief (TC0) Register A (channel = 0) */\r
+#define REG_TC0_RB0 (*(RwReg*)0x40090018U) /**< \brief (TC0) Register B (channel = 0) */\r
+#define REG_TC0_RC0 (*(RwReg*)0x4009001CU) /**< \brief (TC0) Register C (channel = 0) */\r
+#define REG_TC0_SR0 (*(RoReg*)0x40090020U) /**< \brief (TC0) Status Register (channel = 0) */\r
+#define REG_TC0_IER0 (*(WoReg*)0x40090024U) /**< \brief (TC0) Interrupt Enable Register (channel = 0) */\r
+#define REG_TC0_IDR0 (*(WoReg*)0x40090028U) /**< \brief (TC0) Interrupt Disable Register (channel = 0) */\r
+#define REG_TC0_IMR0 (*(RoReg*)0x4009002CU) /**< \brief (TC0) Interrupt Mask Register (channel = 0) */\r
+#define REG_TC0_EMR0 (*(RwReg*)0x40090030U) /**< \brief (TC0) Extended Mode Register (channel = 0) */\r
+#define REG_TC0_CCR1 (*(WoReg*)0x40090040U) /**< \brief (TC0) Channel Control Register (channel = 1) */\r
+#define REG_TC0_CMR1 (*(RwReg*)0x40090044U) /**< \brief (TC0) Channel Mode Register (channel = 1) */\r
+#define REG_TC0_SMMR1 (*(RwReg*)0x40090048U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 1) */\r
+#define REG_TC0_RAB1 (*(RoReg*)0x4009004CU) /**< \brief (TC0) Register AB (channel = 1) */\r
+#define REG_TC0_CV1 (*(RoReg*)0x40090050U) /**< \brief (TC0) Counter Value (channel = 1) */\r
+#define REG_TC0_RA1 (*(RwReg*)0x40090054U) /**< \brief (TC0) Register A (channel = 1) */\r
+#define REG_TC0_RB1 (*(RwReg*)0x40090058U) /**< \brief (TC0) Register B (channel = 1) */\r
+#define REG_TC0_RC1 (*(RwReg*)0x4009005CU) /**< \brief (TC0) Register C (channel = 1) */\r
+#define REG_TC0_SR1 (*(RoReg*)0x40090060U) /**< \brief (TC0) Status Register (channel = 1) */\r
+#define REG_TC0_IER1 (*(WoReg*)0x40090064U) /**< \brief (TC0) Interrupt Enable Register (channel = 1) */\r
+#define REG_TC0_IDR1 (*(WoReg*)0x40090068U) /**< \brief (TC0) Interrupt Disable Register (channel = 1) */\r
+#define REG_TC0_IMR1 (*(RoReg*)0x4009006CU) /**< \brief (TC0) Interrupt Mask Register (channel = 1) */\r
+#define REG_TC0_EMR1 (*(RwReg*)0x40090070U) /**< \brief (TC0) Extended Mode Register (channel = 1) */\r
+#define REG_TC0_CCR2 (*(WoReg*)0x40090080U) /**< \brief (TC0) Channel Control Register (channel = 2) */\r
+#define REG_TC0_CMR2 (*(RwReg*)0x40090084U) /**< \brief (TC0) Channel Mode Register (channel = 2) */\r
+#define REG_TC0_SMMR2 (*(RwReg*)0x40090088U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 2) */\r
+#define REG_TC0_RAB2 (*(RoReg*)0x4009008CU) /**< \brief (TC0) Register AB (channel = 2) */\r
+#define REG_TC0_CV2 (*(RoReg*)0x40090090U) /**< \brief (TC0) Counter Value (channel = 2) */\r
+#define REG_TC0_RA2 (*(RwReg*)0x40090094U) /**< \brief (TC0) Register A (channel = 2) */\r
+#define REG_TC0_RB2 (*(RwReg*)0x40090098U) /**< \brief (TC0) Register B (channel = 2) */\r
+#define REG_TC0_RC2 (*(RwReg*)0x4009009CU) /**< \brief (TC0) Register C (channel = 2) */\r
+#define REG_TC0_SR2 (*(RoReg*)0x400900A0U) /**< \brief (TC0) Status Register (channel = 2) */\r
+#define REG_TC0_IER2 (*(WoReg*)0x400900A4U) /**< \brief (TC0) Interrupt Enable Register (channel = 2) */\r
+#define REG_TC0_IDR2 (*(WoReg*)0x400900A8U) /**< \brief (TC0) Interrupt Disable Register (channel = 2) */\r
+#define REG_TC0_IMR2 (*(RoReg*)0x400900ACU) /**< \brief (TC0) Interrupt Mask Register (channel = 2) */\r
+#define REG_TC0_EMR2 (*(RwReg*)0x400900B0U) /**< \brief (TC0) Extended Mode Register (channel = 2) */\r
+#define REG_TC0_BCR (*(WoReg*)0x400900C0U) /**< \brief (TC0) Block Control Register */\r
+#define REG_TC0_BMR (*(RwReg*)0x400900C4U) /**< \brief (TC0) Block Mode Register */\r
+#define REG_TC0_QIER (*(WoReg*)0x400900C8U) /**< \brief (TC0) QDEC Interrupt Enable Register */\r
+#define REG_TC0_QIDR (*(WoReg*)0x400900CCU) /**< \brief (TC0) QDEC Interrupt Disable Register */\r
+#define REG_TC0_QIMR (*(RoReg*)0x400900D0U) /**< \brief (TC0) QDEC Interrupt Mask Register */\r
+#define REG_TC0_QISR (*(RoReg*)0x400900D4U) /**< \brief (TC0) QDEC Interrupt Status Register */\r
+#define REG_TC0_FMR (*(RwReg*)0x400900D8U) /**< \brief (TC0) Fault Mode Register */\r
+#define REG_TC0_WPMR (*(RwReg*)0x400900E4U) /**< \brief (TC0) Write Protect Mode Register */\r
+#define REG_TC0_RPR0 (*(RwReg*)0x40090100U) /**< \brief (TC0) Receive Pointer Register (pdc = 0) */\r
+#define REG_TC0_RCR0 (*(RwReg*)0x40090104U) /**< \brief (TC0) Receive Counter Register (pdc = 0) */\r
+#define REG_TC0_RNPR0 (*(RwReg*)0x40090110U) /**< \brief (TC0) Receive Next Pointer Register (pdc = 0) */\r
+#define REG_TC0_RNCR0 (*(RwReg*)0x40090114U) /**< \brief (TC0) Receive Next Counter Register (pdc = 0) */\r
+#define REG_TC0_PTCR0 (*(WoReg*)0x40090120U) /**< \brief (TC0) Transfer Control Register (pdc = 0) */\r
+#define REG_TC0_PTSR0 (*(RoReg*)0x40090124U) /**< \brief (TC0) Transfer Status Register (pdc = 0) */\r
+#define REG_TC0_RPR1 (*(RwReg*)0x40090140U) /**< \brief (TC0) Receive Pointer Register (pdc = 1) */\r
+#define REG_TC0_RCR1 (*(RwReg*)0x40090144U) /**< \brief (TC0) Receive Counter Register (pdc = 1) */\r
+#define REG_TC0_RNPR1 (*(RwReg*)0x40090150U) /**< \brief (TC0) Receive Next Pointer Register (pdc = 1) */\r
+#define REG_TC0_RNCR1 (*(RwReg*)0x40090154U) /**< \brief (TC0) Receive Next Counter Register (pdc = 1) */\r
+#define REG_TC0_PTCR1 (*(WoReg*)0x40090160U) /**< \brief (TC0) Transfer Control Register (pdc = 1) */\r
+#define REG_TC0_PTSR1 (*(RoReg*)0x40090164U) /**< \brief (TC0) Transfer Status Register (pdc = 1) */\r
+#define REG_TC0_RPR2 (*(RwReg*)0x40090180U) /**< \brief (TC0) Receive Pointer Register (pdc = 2) */\r
+#define REG_TC0_RCR2 (*(RwReg*)0x40090184U) /**< \brief (TC0) Receive Counter Register (pdc = 2) */\r
+#define REG_TC0_RNPR2 (*(RwReg*)0x40090190U) /**< \brief (TC0) Receive Next Pointer Register (pdc = 2) */\r
+#define REG_TC0_RNCR2 (*(RwReg*)0x40090194U) /**< \brief (TC0) Receive Next Counter Register (pdc = 2) */\r
+#define REG_TC0_PTCR2 (*(WoReg*)0x400901A0U) /**< \brief (TC0) Transfer Control Register (pdc = 2) */\r
+#define REG_TC0_PTSR2 (*(RoReg*)0x400901A4U) /**< \brief (TC0) Transfer Status Register (pdc = 2) */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM4E_TC0_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4E_TC1_INSTANCE_\r
+#define _SAM4E_TC1_INSTANCE_\r
+\r
+/* ========== Register definition for TC1 peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_TC1_CCR0 (0x40094000U) /**< \brief (TC1) Channel Control Register (channel = 0) */\r
+#define REG_TC1_CMR0 (0x40094004U) /**< \brief (TC1) Channel Mode Register (channel = 0) */\r
+#define REG_TC1_SMMR0 (0x40094008U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 0) */\r
+#define REG_TC1_RAB0 (0x4009400CU) /**< \brief (TC1) Register AB (channel = 0) */\r
+#define REG_TC1_CV0 (0x40094010U) /**< \brief (TC1) Counter Value (channel = 0) */\r
+#define REG_TC1_RA0 (0x40094014U) /**< \brief (TC1) Register A (channel = 0) */\r
+#define REG_TC1_RB0 (0x40094018U) /**< \brief (TC1) Register B (channel = 0) */\r
+#define REG_TC1_RC0 (0x4009401CU) /**< \brief (TC1) Register C (channel = 0) */\r
+#define REG_TC1_SR0 (0x40094020U) /**< \brief (TC1) Status Register (channel = 0) */\r
+#define REG_TC1_IER0 (0x40094024U) /**< \brief (TC1) Interrupt Enable Register (channel = 0) */\r
+#define REG_TC1_IDR0 (0x40094028U) /**< \brief (TC1) Interrupt Disable Register (channel = 0) */\r
+#define REG_TC1_IMR0 (0x4009402CU) /**< \brief (TC1) Interrupt Mask Register (channel = 0) */\r
+#define REG_TC1_EMR0 (0x40094030U) /**< \brief (TC1) Extended Mode Register (channel = 0) */\r
+#define REG_TC1_CCR1 (0x40094040U) /**< \brief (TC1) Channel Control Register (channel = 1) */\r
+#define REG_TC1_CMR1 (0x40094044U) /**< \brief (TC1) Channel Mode Register (channel = 1) */\r
+#define REG_TC1_SMMR1 (0x40094048U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 1) */\r
+#define REG_TC1_RAB1 (0x4009404CU) /**< \brief (TC1) Register AB (channel = 1) */\r
+#define REG_TC1_CV1 (0x40094050U) /**< \brief (TC1) Counter Value (channel = 1) */\r
+#define REG_TC1_RA1 (0x40094054U) /**< \brief (TC1) Register A (channel = 1) */\r
+#define REG_TC1_RB1 (0x40094058U) /**< \brief (TC1) Register B (channel = 1) */\r
+#define REG_TC1_RC1 (0x4009405CU) /**< \brief (TC1) Register C (channel = 1) */\r
+#define REG_TC1_SR1 (0x40094060U) /**< \brief (TC1) Status Register (channel = 1) */\r
+#define REG_TC1_IER1 (0x40094064U) /**< \brief (TC1) Interrupt Enable Register (channel = 1) */\r
+#define REG_TC1_IDR1 (0x40094068U) /**< \brief (TC1) Interrupt Disable Register (channel = 1) */\r
+#define REG_TC1_IMR1 (0x4009406CU) /**< \brief (TC1) Interrupt Mask Register (channel = 1) */\r
+#define REG_TC1_EMR1 (0x40094070U) /**< \brief (TC1) Extended Mode Register (channel = 1) */\r
+#define REG_TC1_CCR2 (0x40094080U) /**< \brief (TC1) Channel Control Register (channel = 2) */\r
+#define REG_TC1_CMR2 (0x40094084U) /**< \brief (TC1) Channel Mode Register (channel = 2) */\r
+#define REG_TC1_SMMR2 (0x40094088U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 2) */\r
+#define REG_TC1_RAB2 (0x4009408CU) /**< \brief (TC1) Register AB (channel = 2) */\r
+#define REG_TC1_CV2 (0x40094090U) /**< \brief (TC1) Counter Value (channel = 2) */\r
+#define REG_TC1_RA2 (0x40094094U) /**< \brief (TC1) Register A (channel = 2) */\r
+#define REG_TC1_RB2 (0x40094098U) /**< \brief (TC1) Register B (channel = 2) */\r
+#define REG_TC1_RC2 (0x4009409CU) /**< \brief (TC1) Register C (channel = 2) */\r
+#define REG_TC1_SR2 (0x400940A0U) /**< \brief (TC1) Status Register (channel = 2) */\r
+#define REG_TC1_IER2 (0x400940A4U) /**< \brief (TC1) Interrupt Enable Register (channel = 2) */\r
+#define REG_TC1_IDR2 (0x400940A8U) /**< \brief (TC1) Interrupt Disable Register (channel = 2) */\r
+#define REG_TC1_IMR2 (0x400940ACU) /**< \brief (TC1) Interrupt Mask Register (channel = 2) */\r
+#define REG_TC1_EMR2 (0x400940B0U) /**< \brief (TC1) Extended Mode Register (channel = 2) */\r
+#define REG_TC1_BCR (0x400940C0U) /**< \brief (TC1) Block Control Register */\r
+#define REG_TC1_BMR (0x400940C4U) /**< \brief (TC1) Block Mode Register */\r
+#define REG_TC1_QIER (0x400940C8U) /**< \brief (TC1) QDEC Interrupt Enable Register */\r
+#define REG_TC1_QIDR (0x400940CCU) /**< \brief (TC1) QDEC Interrupt Disable Register */\r
+#define REG_TC1_QIMR (0x400940D0U) /**< \brief (TC1) QDEC Interrupt Mask Register */\r
+#define REG_TC1_QISR (0x400940D4U) /**< \brief (TC1) QDEC Interrupt Status Register */\r
+#define REG_TC1_FMR (0x400940D8U) /**< \brief (TC1) Fault Mode Register */\r
+#define REG_TC1_WPMR (0x400940E4U) /**< \brief (TC1) Write Protect Mode Register */\r
+#define REG_TC1_RPR0 (0x40094100U) /**< \brief (TC1) Receive Pointer Register (pdc = 0) */\r
+#define REG_TC1_RCR0 (0x40094104U) /**< \brief (TC1) Receive Counter Register (pdc = 0) */\r
+#define REG_TC1_RNPR0 (0x40094110U) /**< \brief (TC1) Receive Next Pointer Register (pdc = 0) */\r
+#define REG_TC1_RNCR0 (0x40094114U) /**< \brief (TC1) Receive Next Counter Register (pdc = 0) */\r
+#define REG_TC1_PTCR0 (0x40094120U) /**< \brief (TC1) Transfer Control Register (pdc = 0) */\r
+#define REG_TC1_PTSR0 (0x40094124U) /**< \brief (TC1) Transfer Status Register (pdc = 0) */\r
+#define REG_TC1_RPR1 (0x40094140U) /**< \brief (TC1) Receive Pointer Register (pdc = 1) */\r
+#define REG_TC1_RCR1 (0x40094144U) /**< \brief (TC1) Receive Counter Register (pdc = 1) */\r
+#define REG_TC1_RNPR1 (0x40094150U) /**< \brief (TC1) Receive Next Pointer Register (pdc = 1) */\r
+#define REG_TC1_RNCR1 (0x40094154U) /**< \brief (TC1) Receive Next Counter Register (pdc = 1) */\r
+#define REG_TC1_PTCR1 (0x40094160U) /**< \brief (TC1) Transfer Control Register (pdc = 1) */\r
+#define REG_TC1_PTSR1 (0x40094164U) /**< \brief (TC1) Transfer Status Register (pdc = 1) */\r
+#define REG_TC1_RPR2 (0x40094180U) /**< \brief (TC1) Receive Pointer Register (pdc = 2) */\r
+#define REG_TC1_RCR2 (0x40094184U) /**< \brief (TC1) Receive Counter Register (pdc = 2) */\r
+#define REG_TC1_RNPR2 (0x40094190U) /**< \brief (TC1) Receive Next Pointer Register (pdc = 2) */\r
+#define REG_TC1_RNCR2 (0x40094194U) /**< \brief (TC1) Receive Next Counter Register (pdc = 2) */\r
+#define REG_TC1_PTCR2 (0x400941A0U) /**< \brief (TC1) Transfer Control Register (pdc = 2) */\r
+#define REG_TC1_PTSR2 (0x400941A4U) /**< \brief (TC1) Transfer Status Register (pdc = 2) */\r
+#else\r
+#define REG_TC1_CCR0 (*(WoReg*)0x40094000U) /**< \brief (TC1) Channel Control Register (channel = 0) */\r
+#define REG_TC1_CMR0 (*(RwReg*)0x40094004U) /**< \brief (TC1) Channel Mode Register (channel = 0) */\r
+#define REG_TC1_SMMR0 (*(RwReg*)0x40094008U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 0) */\r
+#define REG_TC1_RAB0 (*(RoReg*)0x4009400CU) /**< \brief (TC1) Register AB (channel = 0) */\r
+#define REG_TC1_CV0 (*(RoReg*)0x40094010U) /**< \brief (TC1) Counter Value (channel = 0) */\r
+#define REG_TC1_RA0 (*(RwReg*)0x40094014U) /**< \brief (TC1) Register A (channel = 0) */\r
+#define REG_TC1_RB0 (*(RwReg*)0x40094018U) /**< \brief (TC1) Register B (channel = 0) */\r
+#define REG_TC1_RC0 (*(RwReg*)0x4009401CU) /**< \brief (TC1) Register C (channel = 0) */\r
+#define REG_TC1_SR0 (*(RoReg*)0x40094020U) /**< \brief (TC1) Status Register (channel = 0) */\r
+#define REG_TC1_IER0 (*(WoReg*)0x40094024U) /**< \brief (TC1) Interrupt Enable Register (channel = 0) */\r
+#define REG_TC1_IDR0 (*(WoReg*)0x40094028U) /**< \brief (TC1) Interrupt Disable Register (channel = 0) */\r
+#define REG_TC1_IMR0 (*(RoReg*)0x4009402CU) /**< \brief (TC1) Interrupt Mask Register (channel = 0) */\r
+#define REG_TC1_EMR0 (*(RwReg*)0x40094030U) /**< \brief (TC1) Extended Mode Register (channel = 0) */\r
+#define REG_TC1_CCR1 (*(WoReg*)0x40094040U) /**< \brief (TC1) Channel Control Register (channel = 1) */\r
+#define REG_TC1_CMR1 (*(RwReg*)0x40094044U) /**< \brief (TC1) Channel Mode Register (channel = 1) */\r
+#define REG_TC1_SMMR1 (*(RwReg*)0x40094048U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 1) */\r
+#define REG_TC1_RAB1 (*(RoReg*)0x4009404CU) /**< \brief (TC1) Register AB (channel = 1) */\r
+#define REG_TC1_CV1 (*(RoReg*)0x40094050U) /**< \brief (TC1) Counter Value (channel = 1) */\r
+#define REG_TC1_RA1 (*(RwReg*)0x40094054U) /**< \brief (TC1) Register A (channel = 1) */\r
+#define REG_TC1_RB1 (*(RwReg*)0x40094058U) /**< \brief (TC1) Register B (channel = 1) */\r
+#define REG_TC1_RC1 (*(RwReg*)0x4009405CU) /**< \brief (TC1) Register C (channel = 1) */\r
+#define REG_TC1_SR1 (*(RoReg*)0x40094060U) /**< \brief (TC1) Status Register (channel = 1) */\r
+#define REG_TC1_IER1 (*(WoReg*)0x40094064U) /**< \brief (TC1) Interrupt Enable Register (channel = 1) */\r
+#define REG_TC1_IDR1 (*(WoReg*)0x40094068U) /**< \brief (TC1) Interrupt Disable Register (channel = 1) */\r
+#define REG_TC1_IMR1 (*(RoReg*)0x4009406CU) /**< \brief (TC1) Interrupt Mask Register (channel = 1) */\r
+#define REG_TC1_EMR1 (*(RwReg*)0x40094070U) /**< \brief (TC1) Extended Mode Register (channel = 1) */\r
+#define REG_TC1_CCR2 (*(WoReg*)0x40094080U) /**< \brief (TC1) Channel Control Register (channel = 2) */\r
+#define REG_TC1_CMR2 (*(RwReg*)0x40094084U) /**< \brief (TC1) Channel Mode Register (channel = 2) */\r
+#define REG_TC1_SMMR2 (*(RwReg*)0x40094088U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 2) */\r
+#define REG_TC1_RAB2 (*(RoReg*)0x4009408CU) /**< \brief (TC1) Register AB (channel = 2) */\r
+#define REG_TC1_CV2 (*(RoReg*)0x40094090U) /**< \brief (TC1) Counter Value (channel = 2) */\r
+#define REG_TC1_RA2 (*(RwReg*)0x40094094U) /**< \brief (TC1) Register A (channel = 2) */\r
+#define REG_TC1_RB2 (*(RwReg*)0x40094098U) /**< \brief (TC1) Register B (channel = 2) */\r
+#define REG_TC1_RC2 (*(RwReg*)0x4009409CU) /**< \brief (TC1) Register C (channel = 2) */\r
+#define REG_TC1_SR2 (*(RoReg*)0x400940A0U) /**< \brief (TC1) Status Register (channel = 2) */\r
+#define REG_TC1_IER2 (*(WoReg*)0x400940A4U) /**< \brief (TC1) Interrupt Enable Register (channel = 2) */\r
+#define REG_TC1_IDR2 (*(WoReg*)0x400940A8U) /**< \brief (TC1) Interrupt Disable Register (channel = 2) */\r
+#define REG_TC1_IMR2 (*(RoReg*)0x400940ACU) /**< \brief (TC1) Interrupt Mask Register (channel = 2) */\r
+#define REG_TC1_EMR2 (*(RwReg*)0x400940B0U) /**< \brief (TC1) Extended Mode Register (channel = 2) */\r
+#define REG_TC1_BCR (*(WoReg*)0x400940C0U) /**< \brief (TC1) Block Control Register */\r
+#define REG_TC1_BMR (*(RwReg*)0x400940C4U) /**< \brief (TC1) Block Mode Register */\r
+#define REG_TC1_QIER (*(WoReg*)0x400940C8U) /**< \brief (TC1) QDEC Interrupt Enable Register */\r
+#define REG_TC1_QIDR (*(WoReg*)0x400940CCU) /**< \brief (TC1) QDEC Interrupt Disable Register */\r
+#define REG_TC1_QIMR (*(RoReg*)0x400940D0U) /**< \brief (TC1) QDEC Interrupt Mask Register */\r
+#define REG_TC1_QISR (*(RoReg*)0x400940D4U) /**< \brief (TC1) QDEC Interrupt Status Register */\r
+#define REG_TC1_FMR (*(RwReg*)0x400940D8U) /**< \brief (TC1) Fault Mode Register */\r
+#define REG_TC1_WPMR (*(RwReg*)0x400940E4U) /**< \brief (TC1) Write Protect Mode Register */\r
+#define REG_TC1_RPR0 (*(RwReg*)0x40094100U) /**< \brief (TC1) Receive Pointer Register (pdc = 0) */\r
+#define REG_TC1_RCR0 (*(RwReg*)0x40094104U) /**< \brief (TC1) Receive Counter Register (pdc = 0) */\r
+#define REG_TC1_RNPR0 (*(RwReg*)0x40094110U) /**< \brief (TC1) Receive Next Pointer Register (pdc = 0) */\r
+#define REG_TC1_RNCR0 (*(RwReg*)0x40094114U) /**< \brief (TC1) Receive Next Counter Register (pdc = 0) */\r
+#define REG_TC1_PTCR0 (*(WoReg*)0x40094120U) /**< \brief (TC1) Transfer Control Register (pdc = 0) */\r
+#define REG_TC1_PTSR0 (*(RoReg*)0x40094124U) /**< \brief (TC1) Transfer Status Register (pdc = 0) */\r
+#define REG_TC1_RPR1 (*(RwReg*)0x40094140U) /**< \brief (TC1) Receive Pointer Register (pdc = 1) */\r
+#define REG_TC1_RCR1 (*(RwReg*)0x40094144U) /**< \brief (TC1) Receive Counter Register (pdc = 1) */\r
+#define REG_TC1_RNPR1 (*(RwReg*)0x40094150U) /**< \brief (TC1) Receive Next Pointer Register (pdc = 1) */\r
+#define REG_TC1_RNCR1 (*(RwReg*)0x40094154U) /**< \brief (TC1) Receive Next Counter Register (pdc = 1) */\r
+#define REG_TC1_PTCR1 (*(WoReg*)0x40094160U) /**< \brief (TC1) Transfer Control Register (pdc = 1) */\r
+#define REG_TC1_PTSR1 (*(RoReg*)0x40094164U) /**< \brief (TC1) Transfer Status Register (pdc = 1) */\r
+#define REG_TC1_RPR2 (*(RwReg*)0x40094180U) /**< \brief (TC1) Receive Pointer Register (pdc = 2) */\r
+#define REG_TC1_RCR2 (*(RwReg*)0x40094184U) /**< \brief (TC1) Receive Counter Register (pdc = 2) */\r
+#define REG_TC1_RNPR2 (*(RwReg*)0x40094190U) /**< \brief (TC1) Receive Next Pointer Register (pdc = 2) */\r
+#define REG_TC1_RNCR2 (*(RwReg*)0x40094194U) /**< \brief (TC1) Receive Next Counter Register (pdc = 2) */\r
+#define REG_TC1_PTCR2 (*(WoReg*)0x400941A0U) /**< \brief (TC1) Transfer Control Register (pdc = 2) */\r
+#define REG_TC1_PTSR2 (*(RoReg*)0x400941A4U) /**< \brief (TC1) Transfer Status Register (pdc = 2) */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM4E_TC1_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4E_TC2_INSTANCE_\r
+#define _SAM4E_TC2_INSTANCE_\r
+\r
+/* ========== Register definition for TC2 peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_TC2_CCR0 (0x40098000U) /**< \brief (TC2) Channel Control Register (channel = 0) */\r
+#define REG_TC2_CMR0 (0x40098004U) /**< \brief (TC2) Channel Mode Register (channel = 0) */\r
+#define REG_TC2_SMMR0 (0x40098008U) /**< \brief (TC2) Stepper Motor Mode Register (channel = 0) */\r
+#define REG_TC2_RAB0 (0x4009800CU) /**< \brief (TC2) Register AB (channel = 0) */\r
+#define REG_TC2_CV0 (0x40098010U) /**< \brief (TC2) Counter Value (channel = 0) */\r
+#define REG_TC2_RA0 (0x40098014U) /**< \brief (TC2) Register A (channel = 0) */\r
+#define REG_TC2_RB0 (0x40098018U) /**< \brief (TC2) Register B (channel = 0) */\r
+#define REG_TC2_RC0 (0x4009801CU) /**< \brief (TC2) Register C (channel = 0) */\r
+#define REG_TC2_SR0 (0x40098020U) /**< \brief (TC2) Status Register (channel = 0) */\r
+#define REG_TC2_IER0 (0x40098024U) /**< \brief (TC2) Interrupt Enable Register (channel = 0) */\r
+#define REG_TC2_IDR0 (0x40098028U) /**< \brief (TC2) Interrupt Disable Register (channel = 0) */\r
+#define REG_TC2_IMR0 (0x4009802CU) /**< \brief (TC2) Interrupt Mask Register (channel = 0) */\r
+#define REG_TC2_EMR0 (0x40098030U) /**< \brief (TC2) Extended Mode Register (channel = 0) */\r
+#define REG_TC2_CCR1 (0x40098040U) /**< \brief (TC2) Channel Control Register (channel = 1) */\r
+#define REG_TC2_CMR1 (0x40098044U) /**< \brief (TC2) Channel Mode Register (channel = 1) */\r
+#define REG_TC2_SMMR1 (0x40098048U) /**< \brief (TC2) Stepper Motor Mode Register (channel = 1) */\r
+#define REG_TC2_RAB1 (0x4009804CU) /**< \brief (TC2) Register AB (channel = 1) */\r
+#define REG_TC2_CV1 (0x40098050U) /**< \brief (TC2) Counter Value (channel = 1) */\r
+#define REG_TC2_RA1 (0x40098054U) /**< \brief (TC2) Register A (channel = 1) */\r
+#define REG_TC2_RB1 (0x40098058U) /**< \brief (TC2) Register B (channel = 1) */\r
+#define REG_TC2_RC1 (0x4009805CU) /**< \brief (TC2) Register C (channel = 1) */\r
+#define REG_TC2_SR1 (0x40098060U) /**< \brief (TC2) Status Register (channel = 1) */\r
+#define REG_TC2_IER1 (0x40098064U) /**< \brief (TC2) Interrupt Enable Register (channel = 1) */\r
+#define REG_TC2_IDR1 (0x40098068U) /**< \brief (TC2) Interrupt Disable Register (channel = 1) */\r
+#define REG_TC2_IMR1 (0x4009806CU) /**< \brief (TC2) Interrupt Mask Register (channel = 1) */\r
+#define REG_TC2_EMR1 (0x40098070U) /**< \brief (TC2) Extended Mode Register (channel = 1) */\r
+#define REG_TC2_CCR2 (0x40098080U) /**< \brief (TC2) Channel Control Register (channel = 2) */\r
+#define REG_TC2_CMR2 (0x40098084U) /**< \brief (TC2) Channel Mode Register (channel = 2) */\r
+#define REG_TC2_SMMR2 (0x40098088U) /**< \brief (TC2) Stepper Motor Mode Register (channel = 2) */\r
+#define REG_TC2_RAB2 (0x4009808CU) /**< \brief (TC2) Register AB (channel = 2) */\r
+#define REG_TC2_CV2 (0x40098090U) /**< \brief (TC2) Counter Value (channel = 2) */\r
+#define REG_TC2_RA2 (0x40098094U) /**< \brief (TC2) Register A (channel = 2) */\r
+#define REG_TC2_RB2 (0x40098098U) /**< \brief (TC2) Register B (channel = 2) */\r
+#define REG_TC2_RC2 (0x4009809CU) /**< \brief (TC2) Register C (channel = 2) */\r
+#define REG_TC2_SR2 (0x400980A0U) /**< \brief (TC2) Status Register (channel = 2) */\r
+#define REG_TC2_IER2 (0x400980A4U) /**< \brief (TC2) Interrupt Enable Register (channel = 2) */\r
+#define REG_TC2_IDR2 (0x400980A8U) /**< \brief (TC2) Interrupt Disable Register (channel = 2) */\r
+#define REG_TC2_IMR2 (0x400980ACU) /**< \brief (TC2) Interrupt Mask Register (channel = 2) */\r
+#define REG_TC2_EMR2 (0x400980B0U) /**< \brief (TC2) Extended Mode Register (channel = 2) */\r
+#define REG_TC2_BCR (0x400980C0U) /**< \brief (TC2) Block Control Register */\r
+#define REG_TC2_BMR (0x400980C4U) /**< \brief (TC2) Block Mode Register */\r
+#define REG_TC2_QIER (0x400980C8U) /**< \brief (TC2) QDEC Interrupt Enable Register */\r
+#define REG_TC2_QIDR (0x400980CCU) /**< \brief (TC2) QDEC Interrupt Disable Register */\r
+#define REG_TC2_QIMR (0x400980D0U) /**< \brief (TC2) QDEC Interrupt Mask Register */\r
+#define REG_TC2_QISR (0x400980D4U) /**< \brief (TC2) QDEC Interrupt Status Register */\r
+#define REG_TC2_FMR (0x400980D8U) /**< \brief (TC2) Fault Mode Register */\r
+#define REG_TC2_WPMR (0x400980E4U) /**< \brief (TC2) Write Protect Mode Register */\r
+#else\r
+#define REG_TC2_CCR0 (*(WoReg*)0x40098000U) /**< \brief (TC2) Channel Control Register (channel = 0) */\r
+#define REG_TC2_CMR0 (*(RwReg*)0x40098004U) /**< \brief (TC2) Channel Mode Register (channel = 0) */\r
+#define REG_TC2_SMMR0 (*(RwReg*)0x40098008U) /**< \brief (TC2) Stepper Motor Mode Register (channel = 0) */\r
+#define REG_TC2_RAB0 (*(RoReg*)0x4009800CU) /**< \brief (TC2) Register AB (channel = 0) */\r
+#define REG_TC2_CV0 (*(RoReg*)0x40098010U) /**< \brief (TC2) Counter Value (channel = 0) */\r
+#define REG_TC2_RA0 (*(RwReg*)0x40098014U) /**< \brief (TC2) Register A (channel = 0) */\r
+#define REG_TC2_RB0 (*(RwReg*)0x40098018U) /**< \brief (TC2) Register B (channel = 0) */\r
+#define REG_TC2_RC0 (*(RwReg*)0x4009801CU) /**< \brief (TC2) Register C (channel = 0) */\r
+#define REG_TC2_SR0 (*(RoReg*)0x40098020U) /**< \brief (TC2) Status Register (channel = 0) */\r
+#define REG_TC2_IER0 (*(WoReg*)0x40098024U) /**< \brief (TC2) Interrupt Enable Register (channel = 0) */\r
+#define REG_TC2_IDR0 (*(WoReg*)0x40098028U) /**< \brief (TC2) Interrupt Disable Register (channel = 0) */\r
+#define REG_TC2_IMR0 (*(RoReg*)0x4009802CU) /**< \brief (TC2) Interrupt Mask Register (channel = 0) */\r
+#define REG_TC2_EMR0 (*(RwReg*)0x40098030U) /**< \brief (TC2) Extended Mode Register (channel = 0) */\r
+#define REG_TC2_CCR1 (*(WoReg*)0x40098040U) /**< \brief (TC2) Channel Control Register (channel = 1) */\r
+#define REG_TC2_CMR1 (*(RwReg*)0x40098044U) /**< \brief (TC2) Channel Mode Register (channel = 1) */\r
+#define REG_TC2_SMMR1 (*(RwReg*)0x40098048U) /**< \brief (TC2) Stepper Motor Mode Register (channel = 1) */\r
+#define REG_TC2_RAB1 (*(RoReg*)0x4009804CU) /**< \brief (TC2) Register AB (channel = 1) */\r
+#define REG_TC2_CV1 (*(RoReg*)0x40098050U) /**< \brief (TC2) Counter Value (channel = 1) */\r
+#define REG_TC2_RA1 (*(RwReg*)0x40098054U) /**< \brief (TC2) Register A (channel = 1) */\r
+#define REG_TC2_RB1 (*(RwReg*)0x40098058U) /**< \brief (TC2) Register B (channel = 1) */\r
+#define REG_TC2_RC1 (*(RwReg*)0x4009805CU) /**< \brief (TC2) Register C (channel = 1) */\r
+#define REG_TC2_SR1 (*(RoReg*)0x40098060U) /**< \brief (TC2) Status Register (channel = 1) */\r
+#define REG_TC2_IER1 (*(WoReg*)0x40098064U) /**< \brief (TC2) Interrupt Enable Register (channel = 1) */\r
+#define REG_TC2_IDR1 (*(WoReg*)0x40098068U) /**< \brief (TC2) Interrupt Disable Register (channel = 1) */\r
+#define REG_TC2_IMR1 (*(RoReg*)0x4009806CU) /**< \brief (TC2) Interrupt Mask Register (channel = 1) */\r
+#define REG_TC2_EMR1 (*(RwReg*)0x40098070U) /**< \brief (TC2) Extended Mode Register (channel = 1) */\r
+#define REG_TC2_CCR2 (*(WoReg*)0x40098080U) /**< \brief (TC2) Channel Control Register (channel = 2) */\r
+#define REG_TC2_CMR2 (*(RwReg*)0x40098084U) /**< \brief (TC2) Channel Mode Register (channel = 2) */\r
+#define REG_TC2_SMMR2 (*(RwReg*)0x40098088U) /**< \brief (TC2) Stepper Motor Mode Register (channel = 2) */\r
+#define REG_TC2_RAB2 (*(RoReg*)0x4009808CU) /**< \brief (TC2) Register AB (channel = 2) */\r
+#define REG_TC2_CV2 (*(RoReg*)0x40098090U) /**< \brief (TC2) Counter Value (channel = 2) */\r
+#define REG_TC2_RA2 (*(RwReg*)0x40098094U) /**< \brief (TC2) Register A (channel = 2) */\r
+#define REG_TC2_RB2 (*(RwReg*)0x40098098U) /**< \brief (TC2) Register B (channel = 2) */\r
+#define REG_TC2_RC2 (*(RwReg*)0x4009809CU) /**< \brief (TC2) Register C (channel = 2) */\r
+#define REG_TC2_SR2 (*(RoReg*)0x400980A0U) /**< \brief (TC2) Status Register (channel = 2) */\r
+#define REG_TC2_IER2 (*(WoReg*)0x400980A4U) /**< \brief (TC2) Interrupt Enable Register (channel = 2) */\r
+#define REG_TC2_IDR2 (*(WoReg*)0x400980A8U) /**< \brief (TC2) Interrupt Disable Register (channel = 2) */\r
+#define REG_TC2_IMR2 (*(RoReg*)0x400980ACU) /**< \brief (TC2) Interrupt Mask Register (channel = 2) */\r
+#define REG_TC2_EMR2 (*(RwReg*)0x400980B0U) /**< \brief (TC2) Extended Mode Register (channel = 2) */\r
+#define REG_TC2_BCR (*(WoReg*)0x400980C0U) /**< \brief (TC2) Block Control Register */\r
+#define REG_TC2_BMR (*(RwReg*)0x400980C4U) /**< \brief (TC2) Block Mode Register */\r
+#define REG_TC2_QIER (*(WoReg*)0x400980C8U) /**< \brief (TC2) QDEC Interrupt Enable Register */\r
+#define REG_TC2_QIDR (*(WoReg*)0x400980CCU) /**< \brief (TC2) QDEC Interrupt Disable Register */\r
+#define REG_TC2_QIMR (*(RoReg*)0x400980D0U) /**< \brief (TC2) QDEC Interrupt Mask Register */\r
+#define REG_TC2_QISR (*(RoReg*)0x400980D4U) /**< \brief (TC2) QDEC Interrupt Status Register */\r
+#define REG_TC2_FMR (*(RwReg*)0x400980D8U) /**< \brief (TC2) Fault Mode Register */\r
+#define REG_TC2_WPMR (*(RwReg*)0x400980E4U) /**< \brief (TC2) Write Protect Mode Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM4E_TC2_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4E_TWI0_INSTANCE_\r
+#define _SAM4E_TWI0_INSTANCE_\r
+\r
+/* ========== Register definition for TWI0 peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_TWI0_CR (0x400A8000U) /**< \brief (TWI0) Control Register */\r
+#define REG_TWI0_MMR (0x400A8004U) /**< \brief (TWI0) Master Mode Register */\r
+#define REG_TWI0_SMR (0x400A8008U) /**< \brief (TWI0) Slave Mode Register */\r
+#define REG_TWI0_IADR (0x400A800CU) /**< \brief (TWI0) Internal Address Register */\r
+#define REG_TWI0_CWGR (0x400A8010U) /**< \brief (TWI0) Clock Waveform Generator Register */\r
+#define REG_TWI0_SR (0x400A8020U) /**< \brief (TWI0) Status Register */\r
+#define REG_TWI0_IER (0x400A8024U) /**< \brief (TWI0) Interrupt Enable Register */\r
+#define REG_TWI0_IDR (0x400A8028U) /**< \brief (TWI0) Interrupt Disable Register */\r
+#define REG_TWI0_IMR (0x400A802CU) /**< \brief (TWI0) Interrupt Mask Register */\r
+#define REG_TWI0_RHR (0x400A8030U) /**< \brief (TWI0) Receive Holding Register */\r
+#define REG_TWI0_THR (0x400A8034U) /**< \brief (TWI0) Transmit Holding Register */\r
+#define REG_TWI0_WPROT_MODE (0x400A80E4U) /**< \brief (TWI0) Protection Mode Register */\r
+#define REG_TWI0_WPROT_STATUS (0x400A80E8U) /**< \brief (TWI0) Protection Status Register */\r
+#define REG_TWI0_RPR (0x400A8100U) /**< \brief (TWI0) Receive Pointer Register */\r
+#define REG_TWI0_RCR (0x400A8104U) /**< \brief (TWI0) Receive Counter Register */\r
+#define REG_TWI0_TPR (0x400A8108U) /**< \brief (TWI0) Transmit Pointer Register */\r
+#define REG_TWI0_TCR (0x400A810CU) /**< \brief (TWI0) Transmit Counter Register */\r
+#define REG_TWI0_RNPR (0x400A8110U) /**< \brief (TWI0) Receive Next Pointer Register */\r
+#define REG_TWI0_RNCR (0x400A8114U) /**< \brief (TWI0) Receive Next Counter Register */\r
+#define REG_TWI0_TNPR (0x400A8118U) /**< \brief (TWI0) Transmit Next Pointer Register */\r
+#define REG_TWI0_TNCR (0x400A811CU) /**< \brief (TWI0) Transmit Next Counter Register */\r
+#define REG_TWI0_PTCR (0x400A8120U) /**< \brief (TWI0) Transfer Control Register */\r
+#define REG_TWI0_PTSR (0x400A8124U) /**< \brief (TWI0) Transfer Status Register */\r
+#else\r
+#define REG_TWI0_CR (*(WoReg*)0x400A8000U) /**< \brief (TWI0) Control Register */\r
+#define REG_TWI0_MMR (*(RwReg*)0x400A8004U) /**< \brief (TWI0) Master Mode Register */\r
+#define REG_TWI0_SMR (*(RwReg*)0x400A8008U) /**< \brief (TWI0) Slave Mode Register */\r
+#define REG_TWI0_IADR (*(RwReg*)0x400A800CU) /**< \brief (TWI0) Internal Address Register */\r
+#define REG_TWI0_CWGR (*(RwReg*)0x400A8010U) /**< \brief (TWI0) Clock Waveform Generator Register */\r
+#define REG_TWI0_SR (*(RoReg*)0x400A8020U) /**< \brief (TWI0) Status Register */\r
+#define REG_TWI0_IER (*(WoReg*)0x400A8024U) /**< \brief (TWI0) Interrupt Enable Register */\r
+#define REG_TWI0_IDR (*(WoReg*)0x400A8028U) /**< \brief (TWI0) Interrupt Disable Register */\r
+#define REG_TWI0_IMR (*(RoReg*)0x400A802CU) /**< \brief (TWI0) Interrupt Mask Register */\r
+#define REG_TWI0_RHR (*(RoReg*)0x400A8030U) /**< \brief (TWI0) Receive Holding Register */\r
+#define REG_TWI0_THR (*(WoReg*)0x400A8034U) /**< \brief (TWI0) Transmit Holding Register */\r
+#define REG_TWI0_WPROT_MODE (*(RwReg*)0x400A80E4U) /**< \brief (TWI0) Protection Mode Register */\r
+#define REG_TWI0_WPROT_STATUS (*(RoReg*)0x400A80E8U) /**< \brief (TWI0) Protection Status Register */\r
+#define REG_TWI0_RPR (*(RwReg*)0x400A8100U) /**< \brief (TWI0) Receive Pointer Register */\r
+#define REG_TWI0_RCR (*(RwReg*)0x400A8104U) /**< \brief (TWI0) Receive Counter Register */\r
+#define REG_TWI0_TPR (*(RwReg*)0x400A8108U) /**< \brief (TWI0) Transmit Pointer Register */\r
+#define REG_TWI0_TCR (*(RwReg*)0x400A810CU) /**< \brief (TWI0) Transmit Counter Register */\r
+#define REG_TWI0_RNPR (*(RwReg*)0x400A8110U) /**< \brief (TWI0) Receive Next Pointer Register */\r
+#define REG_TWI0_RNCR (*(RwReg*)0x400A8114U) /**< \brief (TWI0) Receive Next Counter Register */\r
+#define REG_TWI0_TNPR (*(RwReg*)0x400A8118U) /**< \brief (TWI0) Transmit Next Pointer Register */\r
+#define REG_TWI0_TNCR (*(RwReg*)0x400A811CU) /**< \brief (TWI0) Transmit Next Counter Register */\r
+#define REG_TWI0_PTCR (*(WoReg*)0x400A8120U) /**< \brief (TWI0) Transfer Control Register */\r
+#define REG_TWI0_PTSR (*(RoReg*)0x400A8124U) /**< \brief (TWI0) Transfer Status Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM4E_TWI0_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4E_TWI1_INSTANCE_\r
+#define _SAM4E_TWI1_INSTANCE_\r
+\r
+/* ========== Register definition for TWI1 peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_TWI1_CR (0x400AC000U) /**< \brief (TWI1) Control Register */\r
+#define REG_TWI1_MMR (0x400AC004U) /**< \brief (TWI1) Master Mode Register */\r
+#define REG_TWI1_SMR (0x400AC008U) /**< \brief (TWI1) Slave Mode Register */\r
+#define REG_TWI1_IADR (0x400AC00CU) /**< \brief (TWI1) Internal Address Register */\r
+#define REG_TWI1_CWGR (0x400AC010U) /**< \brief (TWI1) Clock Waveform Generator Register */\r
+#define REG_TWI1_SR (0x400AC020U) /**< \brief (TWI1) Status Register */\r
+#define REG_TWI1_IER (0x400AC024U) /**< \brief (TWI1) Interrupt Enable Register */\r
+#define REG_TWI1_IDR (0x400AC028U) /**< \brief (TWI1) Interrupt Disable Register */\r
+#define REG_TWI1_IMR (0x400AC02CU) /**< \brief (TWI1) Interrupt Mask Register */\r
+#define REG_TWI1_RHR (0x400AC030U) /**< \brief (TWI1) Receive Holding Register */\r
+#define REG_TWI1_THR (0x400AC034U) /**< \brief (TWI1) Transmit Holding Register */\r
+#define REG_TWI1_WPROT_MODE (0x400AC0E4U) /**< \brief (TWI1) Protection Mode Register */\r
+#define REG_TWI1_WPROT_STATUS (0x400AC0E8U) /**< \brief (TWI1) Protection Status Register */\r
+#define REG_TWI1_RPR (0x400AC100U) /**< \brief (TWI1) Receive Pointer Register */\r
+#define REG_TWI1_RCR (0x400AC104U) /**< \brief (TWI1) Receive Counter Register */\r
+#define REG_TWI1_TPR (0x400AC108U) /**< \brief (TWI1) Transmit Pointer Register */\r
+#define REG_TWI1_TCR (0x400AC10CU) /**< \brief (TWI1) Transmit Counter Register */\r
+#define REG_TWI1_RNPR (0x400AC110U) /**< \brief (TWI1) Receive Next Pointer Register */\r
+#define REG_TWI1_RNCR (0x400AC114U) /**< \brief (TWI1) Receive Next Counter Register */\r
+#define REG_TWI1_TNPR (0x400AC118U) /**< \brief (TWI1) Transmit Next Pointer Register */\r
+#define REG_TWI1_TNCR (0x400AC11CU) /**< \brief (TWI1) Transmit Next Counter Register */\r
+#define REG_TWI1_PTCR (0x400AC120U) /**< \brief (TWI1) Transfer Control Register */\r
+#define REG_TWI1_PTSR (0x400AC124U) /**< \brief (TWI1) Transfer Status Register */\r
+#else\r
+#define REG_TWI1_CR (*(WoReg*)0x400AC000U) /**< \brief (TWI1) Control Register */\r
+#define REG_TWI1_MMR (*(RwReg*)0x400AC004U) /**< \brief (TWI1) Master Mode Register */\r
+#define REG_TWI1_SMR (*(RwReg*)0x400AC008U) /**< \brief (TWI1) Slave Mode Register */\r
+#define REG_TWI1_IADR (*(RwReg*)0x400AC00CU) /**< \brief (TWI1) Internal Address Register */\r
+#define REG_TWI1_CWGR (*(RwReg*)0x400AC010U) /**< \brief (TWI1) Clock Waveform Generator Register */\r
+#define REG_TWI1_SR (*(RoReg*)0x400AC020U) /**< \brief (TWI1) Status Register */\r
+#define REG_TWI1_IER (*(WoReg*)0x400AC024U) /**< \brief (TWI1) Interrupt Enable Register */\r
+#define REG_TWI1_IDR (*(WoReg*)0x400AC028U) /**< \brief (TWI1) Interrupt Disable Register */\r
+#define REG_TWI1_IMR (*(RoReg*)0x400AC02CU) /**< \brief (TWI1) Interrupt Mask Register */\r
+#define REG_TWI1_RHR (*(RoReg*)0x400AC030U) /**< \brief (TWI1) Receive Holding Register */\r
+#define REG_TWI1_THR (*(WoReg*)0x400AC034U) /**< \brief (TWI1) Transmit Holding Register */\r
+#define REG_TWI1_WPROT_MODE (*(RwReg*)0x400AC0E4U) /**< \brief (TWI1) Protection Mode Register */\r
+#define REG_TWI1_WPROT_STATUS (*(RoReg*)0x400AC0E8U) /**< \brief (TWI1) Protection Status Register */\r
+#define REG_TWI1_RPR (*(RwReg*)0x400AC100U) /**< \brief (TWI1) Receive Pointer Register */\r
+#define REG_TWI1_RCR (*(RwReg*)0x400AC104U) /**< \brief (TWI1) Receive Counter Register */\r
+#define REG_TWI1_TPR (*(RwReg*)0x400AC108U) /**< \brief (TWI1) Transmit Pointer Register */\r
+#define REG_TWI1_TCR (*(RwReg*)0x400AC10CU) /**< \brief (TWI1) Transmit Counter Register */\r
+#define REG_TWI1_RNPR (*(RwReg*)0x400AC110U) /**< \brief (TWI1) Receive Next Pointer Register */\r
+#define REG_TWI1_RNCR (*(RwReg*)0x400AC114U) /**< \brief (TWI1) Receive Next Counter Register */\r
+#define REG_TWI1_TNPR (*(RwReg*)0x400AC118U) /**< \brief (TWI1) Transmit Next Pointer Register */\r
+#define REG_TWI1_TNCR (*(RwReg*)0x400AC11CU) /**< \brief (TWI1) Transmit Next Counter Register */\r
+#define REG_TWI1_PTCR (*(WoReg*)0x400AC120U) /**< \brief (TWI1) Transfer Control Register */\r
+#define REG_TWI1_PTSR (*(RoReg*)0x400AC124U) /**< \brief (TWI1) Transfer Status Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM4E_TWI1_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4E_UART0_INSTANCE_\r
+#define _SAM4E_UART0_INSTANCE_\r
+\r
+/* ========== Register definition for UART0 peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_UART0_CR (0x400E0600U) /**< \brief (UART0) Control Register */\r
+#define REG_UART0_MR (0x400E0604U) /**< \brief (UART0) Mode Register */\r
+#define REG_UART0_IER (0x400E0608U) /**< \brief (UART0) Interrupt Enable Register */\r
+#define REG_UART0_IDR (0x400E060CU) /**< \brief (UART0) Interrupt Disable Register */\r
+#define REG_UART0_IMR (0x400E0610U) /**< \brief (UART0) Interrupt Mask Register */\r
+#define REG_UART0_SR (0x400E0614U) /**< \brief (UART0) Status Register */\r
+#define REG_UART0_RHR (0x400E0618U) /**< \brief (UART0) Receive Holding Register */\r
+#define REG_UART0_THR (0x400E061CU) /**< \brief (UART0) Transmit Holding Register */\r
+#define REG_UART0_BRGR (0x400E0620U) /**< \brief (UART0) Baud Rate Generator Register */\r
+#define REG_UART0_RPR (0x400E0700U) /**< \brief (UART0) Receive Pointer Register */\r
+#define REG_UART0_RCR (0x400E0704U) /**< \brief (UART0) Receive Counter Register */\r
+#define REG_UART0_TPR (0x400E0708U) /**< \brief (UART0) Transmit Pointer Register */\r
+#define REG_UART0_TCR (0x400E070CU) /**< \brief (UART0) Transmit Counter Register */\r
+#define REG_UART0_RNPR (0x400E0710U) /**< \brief (UART0) Receive Next Pointer Register */\r
+#define REG_UART0_RNCR (0x400E0714U) /**< \brief (UART0) Receive Next Counter Register */\r
+#define REG_UART0_TNPR (0x400E0718U) /**< \brief (UART0) Transmit Next Pointer Register */\r
+#define REG_UART0_TNCR (0x400E071CU) /**< \brief (UART0) Transmit Next Counter Register */\r
+#define REG_UART0_PTCR (0x400E0720U) /**< \brief (UART0) Transfer Control Register */\r
+#define REG_UART0_PTSR (0x400E0724U) /**< \brief (UART0) Transfer Status Register */\r
+#else\r
+#define REG_UART0_CR (*(WoReg*)0x400E0600U) /**< \brief (UART0) Control Register */\r
+#define REG_UART0_MR (*(RwReg*)0x400E0604U) /**< \brief (UART0) Mode Register */\r
+#define REG_UART0_IER (*(WoReg*)0x400E0608U) /**< \brief (UART0) Interrupt Enable Register */\r
+#define REG_UART0_IDR (*(WoReg*)0x400E060CU) /**< \brief (UART0) Interrupt Disable Register */\r
+#define REG_UART0_IMR (*(RoReg*)0x400E0610U) /**< \brief (UART0) Interrupt Mask Register */\r
+#define REG_UART0_SR (*(RoReg*)0x400E0614U) /**< \brief (UART0) Status Register */\r
+#define REG_UART0_RHR (*(RoReg*)0x400E0618U) /**< \brief (UART0) Receive Holding Register */\r
+#define REG_UART0_THR (*(WoReg*)0x400E061CU) /**< \brief (UART0) Transmit Holding Register */\r
+#define REG_UART0_BRGR (*(RwReg*)0x400E0620U) /**< \brief (UART0) Baud Rate Generator Register */\r
+#define REG_UART0_RPR (*(RwReg*)0x400E0700U) /**< \brief (UART0) Receive Pointer Register */\r
+#define REG_UART0_RCR (*(RwReg*)0x400E0704U) /**< \brief (UART0) Receive Counter Register */\r
+#define REG_UART0_TPR (*(RwReg*)0x400E0708U) /**< \brief (UART0) Transmit Pointer Register */\r
+#define REG_UART0_TCR (*(RwReg*)0x400E070CU) /**< \brief (UART0) Transmit Counter Register */\r
+#define REG_UART0_RNPR (*(RwReg*)0x400E0710U) /**< \brief (UART0) Receive Next Pointer Register */\r
+#define REG_UART0_RNCR (*(RwReg*)0x400E0714U) /**< \brief (UART0) Receive Next Counter Register */\r
+#define REG_UART0_TNPR (*(RwReg*)0x400E0718U) /**< \brief (UART0) Transmit Next Pointer Register */\r
+#define REG_UART0_TNCR (*(RwReg*)0x400E071CU) /**< \brief (UART0) Transmit Next Counter Register */\r
+#define REG_UART0_PTCR (*(WoReg*)0x400E0720U) /**< \brief (UART0) Transfer Control Register */\r
+#define REG_UART0_PTSR (*(RoReg*)0x400E0724U) /**< \brief (UART0) Transfer Status Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM4E_UART0_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4E_UART1_INSTANCE_\r
+#define _SAM4E_UART1_INSTANCE_\r
+\r
+/* ========== Register definition for UART1 peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_UART1_CR (0x40060600U) /**< \brief (UART1) Control Register */\r
+#define REG_UART1_MR (0x40060604U) /**< \brief (UART1) Mode Register */\r
+#define REG_UART1_IER (0x40060608U) /**< \brief (UART1) Interrupt Enable Register */\r
+#define REG_UART1_IDR (0x4006060CU) /**< \brief (UART1) Interrupt Disable Register */\r
+#define REG_UART1_IMR (0x40060610U) /**< \brief (UART1) Interrupt Mask Register */\r
+#define REG_UART1_SR (0x40060614U) /**< \brief (UART1) Status Register */\r
+#define REG_UART1_RHR (0x40060618U) /**< \brief (UART1) Receive Holding Register */\r
+#define REG_UART1_THR (0x4006061CU) /**< \brief (UART1) Transmit Holding Register */\r
+#define REG_UART1_BRGR (0x40060620U) /**< \brief (UART1) Baud Rate Generator Register */\r
+#define REG_UART1_RPR (0x40060700U) /**< \brief (UART1) Receive Pointer Register */\r
+#define REG_UART1_RCR (0x40060704U) /**< \brief (UART1) Receive Counter Register */\r
+#define REG_UART1_TPR (0x40060708U) /**< \brief (UART1) Transmit Pointer Register */\r
+#define REG_UART1_TCR (0x4006070CU) /**< \brief (UART1) Transmit Counter Register */\r
+#define REG_UART1_RNPR (0x40060710U) /**< \brief (UART1) Receive Next Pointer Register */\r
+#define REG_UART1_RNCR (0x40060714U) /**< \brief (UART1) Receive Next Counter Register */\r
+#define REG_UART1_TNPR (0x40060718U) /**< \brief (UART1) Transmit Next Pointer Register */\r
+#define REG_UART1_TNCR (0x4006071CU) /**< \brief (UART1) Transmit Next Counter Register */\r
+#define REG_UART1_PTCR (0x40060720U) /**< \brief (UART1) Transfer Control Register */\r
+#define REG_UART1_PTSR (0x40060724U) /**< \brief (UART1) Transfer Status Register */\r
+#else\r
+#define REG_UART1_CR (*(WoReg*)0x40060600U) /**< \brief (UART1) Control Register */\r
+#define REG_UART1_MR (*(RwReg*)0x40060604U) /**< \brief (UART1) Mode Register */\r
+#define REG_UART1_IER (*(WoReg*)0x40060608U) /**< \brief (UART1) Interrupt Enable Register */\r
+#define REG_UART1_IDR (*(WoReg*)0x4006060CU) /**< \brief (UART1) Interrupt Disable Register */\r
+#define REG_UART1_IMR (*(RoReg*)0x40060610U) /**< \brief (UART1) Interrupt Mask Register */\r
+#define REG_UART1_SR (*(RoReg*)0x40060614U) /**< \brief (UART1) Status Register */\r
+#define REG_UART1_RHR (*(RoReg*)0x40060618U) /**< \brief (UART1) Receive Holding Register */\r
+#define REG_UART1_THR (*(WoReg*)0x4006061CU) /**< \brief (UART1) Transmit Holding Register */\r
+#define REG_UART1_BRGR (*(RwReg*)0x40060620U) /**< \brief (UART1) Baud Rate Generator Register */\r
+#define REG_UART1_RPR (*(RwReg*)0x40060700U) /**< \brief (UART1) Receive Pointer Register */\r
+#define REG_UART1_RCR (*(RwReg*)0x40060704U) /**< \brief (UART1) Receive Counter Register */\r
+#define REG_UART1_TPR (*(RwReg*)0x40060708U) /**< \brief (UART1) Transmit Pointer Register */\r
+#define REG_UART1_TCR (*(RwReg*)0x4006070CU) /**< \brief (UART1) Transmit Counter Register */\r
+#define REG_UART1_RNPR (*(RwReg*)0x40060710U) /**< \brief (UART1) Receive Next Pointer Register */\r
+#define REG_UART1_RNCR (*(RwReg*)0x40060714U) /**< \brief (UART1) Receive Next Counter Register */\r
+#define REG_UART1_TNPR (*(RwReg*)0x40060718U) /**< \brief (UART1) Transmit Next Pointer Register */\r
+#define REG_UART1_TNCR (*(RwReg*)0x4006071CU) /**< \brief (UART1) Transmit Next Counter Register */\r
+#define REG_UART1_PTCR (*(WoReg*)0x40060720U) /**< \brief (UART1) Transfer Control Register */\r
+#define REG_UART1_PTSR (*(RoReg*)0x40060724U) /**< \brief (UART1) Transfer Status Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM4E_UART1_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4E_UDP_INSTANCE_\r
+#define _SAM4E_UDP_INSTANCE_\r
+\r
+/* ========== Register definition for UDP peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_UDP_FRM_NUM (0x40084000U) /**< \brief (UDP) Frame Number Register */\r
+#define REG_UDP_GLB_STAT (0x40084004U) /**< \brief (UDP) Global State Register */\r
+#define REG_UDP_FADDR (0x40084008U) /**< \brief (UDP) Function Address Register */\r
+#define REG_UDP_IER (0x40084010U) /**< \brief (UDP) Interrupt Enable Register */\r
+#define REG_UDP_IDR (0x40084014U) /**< \brief (UDP) Interrupt Disable Register */\r
+#define REG_UDP_IMR (0x40084018U) /**< \brief (UDP) Interrupt Mask Register */\r
+#define REG_UDP_ISR (0x4008401CU) /**< \brief (UDP) Interrupt Status Register */\r
+#define REG_UDP_ICR (0x40084020U) /**< \brief (UDP) Interrupt Clear Register */\r
+#define REG_UDP_RST_EP (0x40084028U) /**< \brief (UDP) Reset Endpoint Register */\r
+#define REG_UDP_CSR (0x40084030U) /**< \brief (UDP) Endpoint Control and Status Register */\r
+#define REG_UDP_FDR (0x40084050U) /**< \brief (UDP) Endpoint FIFO Data Register */\r
+#define REG_UDP_TXVC (0x40084074U) /**< \brief (UDP) Transceiver Control Register */\r
+#else\r
+#define REG_UDP_FRM_NUM (*(RoReg*)0x40084000U) /**< \brief (UDP) Frame Number Register */\r
+#define REG_UDP_GLB_STAT (*(RwReg*)0x40084004U) /**< \brief (UDP) Global State Register */\r
+#define REG_UDP_FADDR (*(RwReg*)0x40084008U) /**< \brief (UDP) Function Address Register */\r
+#define REG_UDP_IER (*(WoReg*)0x40084010U) /**< \brief (UDP) Interrupt Enable Register */\r
+#define REG_UDP_IDR (*(WoReg*)0x40084014U) /**< \brief (UDP) Interrupt Disable Register */\r
+#define REG_UDP_IMR (*(RoReg*)0x40084018U) /**< \brief (UDP) Interrupt Mask Register */\r
+#define REG_UDP_ISR (*(RoReg*)0x4008401CU) /**< \brief (UDP) Interrupt Status Register */\r
+#define REG_UDP_ICR (*(WoReg*)0x40084020U) /**< \brief (UDP) Interrupt Clear Register */\r
+#define REG_UDP_RST_EP (*(RwReg*)0x40084028U) /**< \brief (UDP) Reset Endpoint Register */\r
+#define REG_UDP_CSR (*(RwReg*)0x40084030U) /**< \brief (UDP) Endpoint Control and Status Register */\r
+#define REG_UDP_FDR (*(RwReg*)0x40084050U) /**< \brief (UDP) Endpoint FIFO Data Register */\r
+#define REG_UDP_TXVC (*(RwReg*)0x40084074U) /**< \brief (UDP) Transceiver Control Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM4E_UDP_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4E_USART0_INSTANCE_\r
+#define _SAM4E_USART0_INSTANCE_\r
+\r
+/* ========== Register definition for USART0 peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_USART0_CR (0x400A0000U) /**< \brief (USART0) Control Register */\r
+#define REG_USART0_MR (0x400A0004U) /**< \brief (USART0) Mode Register */\r
+#define REG_USART0_IER (0x400A0008U) /**< \brief (USART0) Interrupt Enable Register */\r
+#define REG_USART0_IDR (0x400A000CU) /**< \brief (USART0) Interrupt Disable Register */\r
+#define REG_USART0_IMR (0x400A0010U) /**< \brief (USART0) Interrupt Mask Register */\r
+#define REG_USART0_CSR (0x400A0014U) /**< \brief (USART0) Channel Status Register */\r
+#define REG_USART0_RHR (0x400A0018U) /**< \brief (USART0) Receiver Holding Register */\r
+#define REG_USART0_THR (0x400A001CU) /**< \brief (USART0) Transmitter Holding Register */\r
+#define REG_USART0_BRGR (0x400A0020U) /**< \brief (USART0) Baud Rate Generator Register */\r
+#define REG_USART0_RTOR (0x400A0024U) /**< \brief (USART0) Receiver Time-out Register */\r
+#define REG_USART0_TTGR (0x400A0028U) /**< \brief (USART0) Transmitter Timeguard Register */\r
+#define REG_USART0_FIDI (0x400A0040U) /**< \brief (USART0) FI DI Ratio Register */\r
+#define REG_USART0_NER (0x400A0044U) /**< \brief (USART0) Number of Errors Register */\r
+#define REG_USART0_IF (0x400A004CU) /**< \brief (USART0) IrDA Filter Register */\r
+#define REG_USART0_MAN (0x400A0050U) /**< \brief (USART0) Manchester Encoder Decoder Register */\r
+#define REG_USART0_WPMR (0x400A00E4U) /**< \brief (USART0) Write Protect Mode Register */\r
+#define REG_USART0_WPSR (0x400A00E8U) /**< \brief (USART0) Write Protect Status Register */\r
+#define REG_USART0_RPR (0x400A0100U) /**< \brief (USART0) Receive Pointer Register */\r
+#define REG_USART0_RCR (0x400A0104U) /**< \brief (USART0) Receive Counter Register */\r
+#define REG_USART0_TPR (0x400A0108U) /**< \brief (USART0) Transmit Pointer Register */\r
+#define REG_USART0_TCR (0x400A010CU) /**< \brief (USART0) Transmit Counter Register */\r
+#define REG_USART0_RNPR (0x400A0110U) /**< \brief (USART0) Receive Next Pointer Register */\r
+#define REG_USART0_RNCR (0x400A0114U) /**< \brief (USART0) Receive Next Counter Register */\r
+#define REG_USART0_TNPR (0x400A0118U) /**< \brief (USART0) Transmit Next Pointer Register */\r
+#define REG_USART0_TNCR (0x400A011CU) /**< \brief (USART0) Transmit Next Counter Register */\r
+#define REG_USART0_PTCR (0x400A0120U) /**< \brief (USART0) Transfer Control Register */\r
+#define REG_USART0_PTSR (0x400A0124U) /**< \brief (USART0) Transfer Status Register */\r
+#else\r
+#define REG_USART0_CR (*(WoReg*)0x400A0000U) /**< \brief (USART0) Control Register */\r
+#define REG_USART0_MR (*(RwReg*)0x400A0004U) /**< \brief (USART0) Mode Register */\r
+#define REG_USART0_IER (*(WoReg*)0x400A0008U) /**< \brief (USART0) Interrupt Enable Register */\r
+#define REG_USART0_IDR (*(WoReg*)0x400A000CU) /**< \brief (USART0) Interrupt Disable Register */\r
+#define REG_USART0_IMR (*(RoReg*)0x400A0010U) /**< \brief (USART0) Interrupt Mask Register */\r
+#define REG_USART0_CSR (*(RoReg*)0x400A0014U) /**< \brief (USART0) Channel Status Register */\r
+#define REG_USART0_RHR (*(RoReg*)0x400A0018U) /**< \brief (USART0) Receiver Holding Register */\r
+#define REG_USART0_THR (*(WoReg*)0x400A001CU) /**< \brief (USART0) Transmitter Holding Register */\r
+#define REG_USART0_BRGR (*(RwReg*)0x400A0020U) /**< \brief (USART0) Baud Rate Generator Register */\r
+#define REG_USART0_RTOR (*(RwReg*)0x400A0024U) /**< \brief (USART0) Receiver Time-out Register */\r
+#define REG_USART0_TTGR (*(RwReg*)0x400A0028U) /**< \brief (USART0) Transmitter Timeguard Register */\r
+#define REG_USART0_FIDI (*(RwReg*)0x400A0040U) /**< \brief (USART0) FI DI Ratio Register */\r
+#define REG_USART0_NER (*(RoReg*)0x400A0044U) /**< \brief (USART0) Number of Errors Register */\r
+#define REG_USART0_IF (*(RwReg*)0x400A004CU) /**< \brief (USART0) IrDA Filter Register */\r
+#define REG_USART0_MAN (*(RwReg*)0x400A0050U) /**< \brief (USART0) Manchester Encoder Decoder Register */\r
+#define REG_USART0_WPMR (*(RwReg*)0x400A00E4U) /**< \brief (USART0) Write Protect Mode Register */\r
+#define REG_USART0_WPSR (*(RoReg*)0x400A00E8U) /**< \brief (USART0) Write Protect Status Register */\r
+#define REG_USART0_RPR (*(RwReg*)0x400A0100U) /**< \brief (USART0) Receive Pointer Register */\r
+#define REG_USART0_RCR (*(RwReg*)0x400A0104U) /**< \brief (USART0) Receive Counter Register */\r
+#define REG_USART0_TPR (*(RwReg*)0x400A0108U) /**< \brief (USART0) Transmit Pointer Register */\r
+#define REG_USART0_TCR (*(RwReg*)0x400A010CU) /**< \brief (USART0) Transmit Counter Register */\r
+#define REG_USART0_RNPR (*(RwReg*)0x400A0110U) /**< \brief (USART0) Receive Next Pointer Register */\r
+#define REG_USART0_RNCR (*(RwReg*)0x400A0114U) /**< \brief (USART0) Receive Next Counter Register */\r
+#define REG_USART0_TNPR (*(RwReg*)0x400A0118U) /**< \brief (USART0) Transmit Next Pointer Register */\r
+#define REG_USART0_TNCR (*(RwReg*)0x400A011CU) /**< \brief (USART0) Transmit Next Counter Register */\r
+#define REG_USART0_PTCR (*(WoReg*)0x400A0120U) /**< \brief (USART0) Transfer Control Register */\r
+#define REG_USART0_PTSR (*(RoReg*)0x400A0124U) /**< \brief (USART0) Transfer Status Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM4E_USART0_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4E_USART1_INSTANCE_\r
+#define _SAM4E_USART1_INSTANCE_\r
+\r
+/* ========== Register definition for USART1 peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_USART1_CR (0x400A4000U) /**< \brief (USART1) Control Register */\r
+#define REG_USART1_MR (0x400A4004U) /**< \brief (USART1) Mode Register */\r
+#define REG_USART1_IER (0x400A4008U) /**< \brief (USART1) Interrupt Enable Register */\r
+#define REG_USART1_IDR (0x400A400CU) /**< \brief (USART1) Interrupt Disable Register */\r
+#define REG_USART1_IMR (0x400A4010U) /**< \brief (USART1) Interrupt Mask Register */\r
+#define REG_USART1_CSR (0x400A4014U) /**< \brief (USART1) Channel Status Register */\r
+#define REG_USART1_RHR (0x400A4018U) /**< \brief (USART1) Receiver Holding Register */\r
+#define REG_USART1_THR (0x400A401CU) /**< \brief (USART1) Transmitter Holding Register */\r
+#define REG_USART1_BRGR (0x400A4020U) /**< \brief (USART1) Baud Rate Generator Register */\r
+#define REG_USART1_RTOR (0x400A4024U) /**< \brief (USART1) Receiver Time-out Register */\r
+#define REG_USART1_TTGR (0x400A4028U) /**< \brief (USART1) Transmitter Timeguard Register */\r
+#define REG_USART1_FIDI (0x400A4040U) /**< \brief (USART1) FI DI Ratio Register */\r
+#define REG_USART1_NER (0x400A4044U) /**< \brief (USART1) Number of Errors Register */\r
+#define REG_USART1_IF (0x400A404CU) /**< \brief (USART1) IrDA Filter Register */\r
+#define REG_USART1_MAN (0x400A4050U) /**< \brief (USART1) Manchester Encoder Decoder Register */\r
+#define REG_USART1_WPMR (0x400A40E4U) /**< \brief (USART1) Write Protect Mode Register */\r
+#define REG_USART1_WPSR (0x400A40E8U) /**< \brief (USART1) Write Protect Status Register */\r
+#define REG_USART1_RPR (0x400A4100U) /**< \brief (USART1) Receive Pointer Register */\r
+#define REG_USART1_RCR (0x400A4104U) /**< \brief (USART1) Receive Counter Register */\r
+#define REG_USART1_TPR (0x400A4108U) /**< \brief (USART1) Transmit Pointer Register */\r
+#define REG_USART1_TCR (0x400A410CU) /**< \brief (USART1) Transmit Counter Register */\r
+#define REG_USART1_RNPR (0x400A4110U) /**< \brief (USART1) Receive Next Pointer Register */\r
+#define REG_USART1_RNCR (0x400A4114U) /**< \brief (USART1) Receive Next Counter Register */\r
+#define REG_USART1_TNPR (0x400A4118U) /**< \brief (USART1) Transmit Next Pointer Register */\r
+#define REG_USART1_TNCR (0x400A411CU) /**< \brief (USART1) Transmit Next Counter Register */\r
+#define REG_USART1_PTCR (0x400A4120U) /**< \brief (USART1) Transfer Control Register */\r
+#define REG_USART1_PTSR (0x400A4124U) /**< \brief (USART1) Transfer Status Register */\r
+#else\r
+#define REG_USART1_CR (*(WoReg*)0x400A4000U) /**< \brief (USART1) Control Register */\r
+#define REG_USART1_MR (*(RwReg*)0x400A4004U) /**< \brief (USART1) Mode Register */\r
+#define REG_USART1_IER (*(WoReg*)0x400A4008U) /**< \brief (USART1) Interrupt Enable Register */\r
+#define REG_USART1_IDR (*(WoReg*)0x400A400CU) /**< \brief (USART1) Interrupt Disable Register */\r
+#define REG_USART1_IMR (*(RoReg*)0x400A4010U) /**< \brief (USART1) Interrupt Mask Register */\r
+#define REG_USART1_CSR (*(RoReg*)0x400A4014U) /**< \brief (USART1) Channel Status Register */\r
+#define REG_USART1_RHR (*(RoReg*)0x400A4018U) /**< \brief (USART1) Receiver Holding Register */\r
+#define REG_USART1_THR (*(WoReg*)0x400A401CU) /**< \brief (USART1) Transmitter Holding Register */\r
+#define REG_USART1_BRGR (*(RwReg*)0x400A4020U) /**< \brief (USART1) Baud Rate Generator Register */\r
+#define REG_USART1_RTOR (*(RwReg*)0x400A4024U) /**< \brief (USART1) Receiver Time-out Register */\r
+#define REG_USART1_TTGR (*(RwReg*)0x400A4028U) /**< \brief (USART1) Transmitter Timeguard Register */\r
+#define REG_USART1_FIDI (*(RwReg*)0x400A4040U) /**< \brief (USART1) FI DI Ratio Register */\r
+#define REG_USART1_NER (*(RoReg*)0x400A4044U) /**< \brief (USART1) Number of Errors Register */\r
+#define REG_USART1_IF (*(RwReg*)0x400A404CU) /**< \brief (USART1) IrDA Filter Register */\r
+#define REG_USART1_MAN (*(RwReg*)0x400A4050U) /**< \brief (USART1) Manchester Encoder Decoder Register */\r
+#define REG_USART1_WPMR (*(RwReg*)0x400A40E4U) /**< \brief (USART1) Write Protect Mode Register */\r
+#define REG_USART1_WPSR (*(RoReg*)0x400A40E8U) /**< \brief (USART1) Write Protect Status Register */\r
+#define REG_USART1_RPR (*(RwReg*)0x400A4100U) /**< \brief (USART1) Receive Pointer Register */\r
+#define REG_USART1_RCR (*(RwReg*)0x400A4104U) /**< \brief (USART1) Receive Counter Register */\r
+#define REG_USART1_TPR (*(RwReg*)0x400A4108U) /**< \brief (USART1) Transmit Pointer Register */\r
+#define REG_USART1_TCR (*(RwReg*)0x400A410CU) /**< \brief (USART1) Transmit Counter Register */\r
+#define REG_USART1_RNPR (*(RwReg*)0x400A4110U) /**< \brief (USART1) Receive Next Pointer Register */\r
+#define REG_USART1_RNCR (*(RwReg*)0x400A4114U) /**< \brief (USART1) Receive Next Counter Register */\r
+#define REG_USART1_TNPR (*(RwReg*)0x400A4118U) /**< \brief (USART1) Transmit Next Pointer Register */\r
+#define REG_USART1_TNCR (*(RwReg*)0x400A411CU) /**< \brief (USART1) Transmit Next Counter Register */\r
+#define REG_USART1_PTCR (*(WoReg*)0x400A4120U) /**< \brief (USART1) Transfer Control Register */\r
+#define REG_USART1_PTSR (*(RoReg*)0x400A4124U) /**< \brief (USART1) Transfer Status Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM4E_USART1_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4E_WDT_INSTANCE_\r
+#define _SAM4E_WDT_INSTANCE_\r
+\r
+/* ========== Register definition for WDT peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_WDT_CR (0x400E1850U) /**< \brief (WDT) Control Register */\r
+#define REG_WDT_MR (0x400E1854U) /**< \brief (WDT) Mode Register */\r
+#define REG_WDT_SR (0x400E1858U) /**< \brief (WDT) Status Register */\r
+#else\r
+#define REG_WDT_CR (*(WoReg*)0x400E1850U) /**< \brief (WDT) Control Register */\r
+#define REG_WDT_MR (*(RwReg*)0x400E1854U) /**< \brief (WDT) Mode Register */\r
+#define REG_WDT_SR (*(RoReg*)0x400E1858U) /**< \brief (WDT) Status Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM4E_WDT_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4E16C_PIO_\r
+#define _SAM4E16C_PIO_\r
+\r
+#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */\r
+#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */\r
+#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */\r
+#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */\r
+#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */\r
+#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */\r
+#define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */\r
+#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */\r
+#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */\r
+#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */\r
+#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */\r
+#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */\r
+#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */\r
+#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */\r
+#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */\r
+#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */\r
+#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */\r
+#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */\r
+#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */\r
+#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */\r
+#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */\r
+#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */\r
+#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */\r
+#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */\r
+#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */\r
+#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */\r
+#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */\r
+#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */\r
+#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */\r
+#define PIO_PA29 (1u << 29) /**< \brief Pin Controlled by PA29 */\r
+#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */\r
+#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */\r
+#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */\r
+#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */\r
+#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */\r
+#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */\r
+#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */\r
+#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */\r
+#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */\r
+#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */\r
+#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */\r
+#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */\r
+#define PIO_PB10 (1u << 10) /**< \brief Pin Controlled by PB10 */\r
+#define PIO_PB11 (1u << 11) /**< \brief Pin Controlled by PB11 */\r
+#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */\r
+#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */\r
+#define PIO_PB14 (1u << 14) /**< \brief Pin Controlled by PB14 */\r
+#define PIO_PC0 (1u << 0) /**< \brief Pin Controlled by PC0 */\r
+#define PIO_PC1 (1u << 1) /**< \brief Pin Controlled by PC1 */\r
+#define PIO_PC2 (1u << 2) /**< \brief Pin Controlled by PC2 */\r
+#define PIO_PC3 (1u << 3) /**< \brief Pin Controlled by PC3 */\r
+#define PIO_PC4 (1u << 4) /**< \brief Pin Controlled by PC4 */\r
+#define PIO_PC5 (1u << 5) /**< \brief Pin Controlled by PC5 */\r
+#define PIO_PC6 (1u << 6) /**< \brief Pin Controlled by PC6 */\r
+#define PIO_PC7 (1u << 7) /**< \brief Pin Controlled by PC7 */\r
+#define PIO_PC8 (1u << 8) /**< \brief Pin Controlled by PC8 */\r
+#define PIO_PC9 (1u << 9) /**< \brief Pin Controlled by PC9 */\r
+#define PIO_PC10 (1u << 10) /**< \brief Pin Controlled by PC10 */\r
+#define PIO_PC11 (1u << 11) /**< \brief Pin Controlled by PC11 */\r
+#define PIO_PC12 (1u << 12) /**< \brief Pin Controlled by PC12 */\r
+#define PIO_PC13 (1u << 13) /**< \brief Pin Controlled by PC13 */\r
+#define PIO_PC14 (1u << 14) /**< \brief Pin Controlled by PC14 */\r
+#define PIO_PC15 (1u << 15) /**< \brief Pin Controlled by PC15 */\r
+#define PIO_PC16 (1u << 16) /**< \brief Pin Controlled by PC16 */\r
+#define PIO_PC17 (1u << 17) /**< \brief Pin Controlled by PC17 */\r
+#define PIO_PC18 (1u << 18) /**< \brief Pin Controlled by PC18 */\r
+#define PIO_PC19 (1u << 19) /**< \brief Pin Controlled by PC19 */\r
+#define PIO_PC20 (1u << 20) /**< \brief Pin Controlled by PC20 */\r
+#define PIO_PC21 (1u << 21) /**< \brief Pin Controlled by PC21 */\r
+#define PIO_PC22 (1u << 22) /**< \brief Pin Controlled by PC22 */\r
+#define PIO_PC23 (1u << 23) /**< \brief Pin Controlled by PC23 */\r
+#define PIO_PC24 (1u << 24) /**< \brief Pin Controlled by PC24 */\r
+#define PIO_PC25 (1u << 25) /**< \brief Pin Controlled by PC25 */\r
+#define PIO_PC26 (1u << 26) /**< \brief Pin Controlled by PC26 */\r
+#define PIO_PC27 (1u << 27) /**< \brief Pin Controlled by PC27 */\r
+#define PIO_PC28 (1u << 28) /**< \brief Pin Controlled by PC28 */\r
+#define PIO_PC29 (1u << 29) /**< \brief Pin Controlled by PC29 */\r
+#define PIO_PC30 (1u << 30) /**< \brief Pin Controlled by PC30 */\r
+#define PIO_PC31 (1u << 31) /**< \brief Pin Controlled by PC31 */\r
+#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */\r
+#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */\r
+#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */\r
+#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */\r
+#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */\r
+#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */\r
+#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */\r
+#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */\r
+#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */\r
+#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */\r
+#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */\r
+#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */\r
+#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */\r
+#define PIO_PD13 (1u << 13) /**< \brief Pin Controlled by PD13 */\r
+#define PIO_PD14 (1u << 14) /**< \brief Pin Controlled by PD14 */\r
+#define PIO_PD15 (1u << 15) /**< \brief Pin Controlled by PD15 */\r
+#define PIO_PD16 (1u << 16) /**< \brief Pin Controlled by PD16 */\r
+#define PIO_PD17 (1u << 17) /**< \brief Pin Controlled by PD17 */\r
+#define PIO_PD18 (1u << 18) /**< \brief Pin Controlled by PD18 */\r
+#define PIO_PD19 (1u << 19) /**< \brief Pin Controlled by PD19 */\r
+#define PIO_PD20 (1u << 20) /**< \brief Pin Controlled by PD20 */\r
+#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */\r
+#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */\r
+#define PIO_PD23 (1u << 23) /**< \brief Pin Controlled by PD23 */\r
+#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */\r
+#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */\r
+#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */\r
+#define PIO_PD27 (1u << 27) /**< \brief Pin Controlled by PD27 */\r
+#define PIO_PD28 (1u << 28) /**< \brief Pin Controlled by PD28 */\r
+#define PIO_PD29 (1u << 29) /**< \brief Pin Controlled by PD29 */\r
+#define PIO_PD30 (1u << 30) /**< \brief Pin Controlled by PD30 */\r
+#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */\r
+#define PIO_PE0 (1u << 0) /**< \brief Pin Controlled by PE0 */\r
+#define PIO_PE1 (1u << 1) /**< \brief Pin Controlled by PE1 */\r
+#define PIO_PE2 (1u << 2) /**< \brief Pin Controlled by PE2 */\r
+#define PIO_PE3 (1u << 3) /**< \brief Pin Controlled by PE3 */\r
+#define PIO_PE4 (1u << 4) /**< \brief Pin Controlled by PE4 */\r
+#define PIO_PE5 (1u << 5) /**< \brief Pin Controlled by PE5 */\r
+/* ========== Pio definition for AFEC0 peripheral ========== */\r
+#define PIO_PA17X1_AFE0_AD0 (1u << 17) /**< \brief Afec0 signal: AFE0_AD0 */\r
+#define PIO_PA18X1_AFE0_AD1 (1u << 18) /**< \brief Afec0 signal: AFE0_AD1 */\r
+#define PIO_PC30X1_AFE0_AD10 (1u << 30) /**< \brief Afec0 signal: AFE0_AD10 */\r
+#define PIO_PC31X1_AFE0_AD11 (1u << 31) /**< \brief Afec0 signal: AFE0_AD11 */\r
+#define PIO_PC26X1_AFE0_AD12 (1u << 26) /**< \brief Afec0 signal: AFE0_AD12 */\r
+#define PIO_PC27X1_AFE0_AD13 (1u << 27) /**< \brief Afec0 signal: AFE0_AD13 */\r
+#define PIO_PC0X1_AFE0_AD14 (1u << 0) /**< \brief Afec0 signal: AFE0_AD14 */\r
+#define PIO_PA19X1_AFE0_AD2 (1u << 19) /**< \brief Afec0 signal: AFE0_AD2/WKUP9 */\r
+#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD2/WKUP9 */\r
+#define PIO_PA20X1_AFE0_AD3 (1u << 20) /**< \brief Afec0 signal: AFE0_AD3/WKUP10 */\r
+#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD3/WKUP10 */\r
+#define PIO_PB0X1_AFE0_AD4 (1u << 0) /**< \brief Afec0 signal: AFE0_AD4/RTCOUT0 */\r
+#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD4/RTCOUT0 */\r
+#define PIO_PB1X1_AFE0_AD5 (1u << 1) /**< \brief Afec0 signal: AFE0_AD5/RTCOUT1 */\r
+#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec0 signal: AFE0_AD5/RTCOUT1 */\r
+#define PIO_PC13X1_AFE0_AD6 (1u << 13) /**< \brief Afec0 signal: AFE0_AD6 */\r
+#define PIO_PC15X1_AFE0_AD7 (1u << 15) /**< \brief Afec0 signal: AFE0_AD7 */\r
+#define PIO_PC12X1_AFE0_AD8 (1u << 12) /**< \brief Afec0 signal: AFE0_AD8 */\r
+#define PIO_PC29X1_AFE0_AD9 (1u << 29) /**< \brief Afec0 signal: AFE0_AD9 */\r
+#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */\r
+/* ========== Pio definition for AFEC1 peripheral ========== */\r
+#define PIO_PB2X1_AFE1_AD0 (1u << 2) /**< \brief Afec1 signal: AFE1_AD0/WKUP12 */\r
+#define PIO_PB2X1_WKUP12 (1u << 2) /**< \brief Afec1 signal: AFE1_AD0/WKUP12 */\r
+#define PIO_PB3X1_AFE1_AD1 (1u << 3) /**< \brief Afec1 signal: AFE1_AD1 */\r
+#define PIO_PA21X1_AFE1_AD2 (1u << 21) /**< \brief Afec1 signal: AFE1_AD2 */\r
+#define PIO_PA22X1_AFE1_AD3 (1u << 22) /**< \brief Afec1 signal: AFE1_AD3 */\r
+#define PIO_PC1X1_AFE1_AD4 (1u << 1) /**< \brief Afec1 signal: AFE1_AD4 */\r
+#define PIO_PC2X1_AFE1_AD5 (1u << 2) /**< \brief Afec1 signal: AFE1_AD5 */\r
+#define PIO_PC3X1_AFE1_AD6 (1u << 3) /**< \brief Afec1 signal: AFE1_AD6 */\r
+#define PIO_PC4X1_AFE1_AD7 (1u << 4) /**< \brief Afec1 signal: AFE1_AD7 */\r
+/* ========== Pio definition for CAN0 peripheral ========== */\r
+#define PIO_PB3A_CANRX0 (1u << 3) /**< \brief Can0 signal: CANRX0 */\r
+#define PIO_PB2A_CANTX0 (1u << 2) /**< \brief Can0 signal: CANTX0 */\r
+/* ========== Pio definition for CAN1 peripheral ========== */\r
+#define PIO_PC12C_CANRX1 (1u << 12) /**< \brief Can1 signal: CANRX1 */\r
+#define PIO_PC15C_CANTX1 (1u << 15) /**< \brief Can1 signal: CANTX1 */\r
+/* ========== Pio definition for DACC peripheral ========== */\r
+#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */\r
+#define PIO_PB14X1_DAC1 (1u << 14) /**< \brief Dacc signal: DAC1 */\r
+#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */\r
+/* ========== Pio definition for GMAC peripheral ========== */\r
+#define PIO_PD13A_GCOL (1u << 13) /**< \brief Gmac signal: GCOL */\r
+#define PIO_PD10A_GCRS (1u << 10) /**< \brief Gmac signal: GCRS */\r
+#define PIO_PD4A_GCRSDV (1u << 4) /**< \brief Gmac signal: GCRSDV/GRXDV */\r
+#define PIO_PD4A_GRXDV (1u << 4) /**< \brief Gmac signal: GCRSDV/GRXDV */\r
+#define PIO_PD8A_GMDC (1u << 8) /**< \brief Gmac signal: GMDC */\r
+#define PIO_PD9A_GMDIO (1u << 9) /**< \brief Gmac signal: GMDIO */\r
+#define PIO_PD5A_GRX0 (1u << 5) /**< \brief Gmac signal: GRX0 */\r
+#define PIO_PD6A_GRX0 (1u << 6) /**< \brief Gmac signal: GRX0 */\r
+#define PIO_PD11A_GRX2 (1u << 11) /**< \brief Gmac signal: GRX2 */\r
+#define PIO_PD12A_GRX3 (1u << 12) /**< \brief Gmac signal: GRX3 */\r
+#define PIO_PD14A_GRXCK (1u << 14) /**< \brief Gmac signal: GRXCK */\r
+#define PIO_PD7A_GRXER (1u << 7) /**< \brief Gmac signal: GRXER */\r
+#define PIO_PD2A_GTX0 (1u << 2) /**< \brief Gmac signal: GTX0 */\r
+#define PIO_PD3A_GTX1 (1u << 3) /**< \brief Gmac signal: GTX1 */\r
+#define PIO_PD15A_GTX2 (1u << 15) /**< \brief Gmac signal: GTX2 */\r
+#define PIO_PD16A_GTX3 (1u << 16) /**< \brief Gmac signal: GTX3 */\r
+#define PIO_PD0A_GTXCK (1u << 0) /**< \brief Gmac signal: GTXCK/GREFCK */\r
+#define PIO_PD0A_GREFCK (1u << 0) /**< \brief Gmac signal: GTXCK/GREFCK */\r
+#define PIO_PD1A_GTXEN (1u << 1) /**< \brief Gmac signal: GTXEN */\r
+#define PIO_PD17A_GTXER (1u << 17) /**< \brief Gmac signal: GTXER */\r
+/* ========== Pio definition for HSMCI peripheral ========== */\r
+#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */\r
+#define PIO_PA29C_MCCK (1u << 29) /**< \brief Hsmci signal: MCCK */\r
+#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */\r
+#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */\r
+#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */\r
+#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */\r
+/* ========== Pio definition for PIOA peripheral ========== */\r
+#define PIO_PA24X1_PIODC0 (1u << 24) /**< \brief Pioa signal: PIODC0 */\r
+#define PIO_PA25X1_PIODC1 (1u << 25) /**< \brief Pioa signal: PIODC1 */\r
+#define PIO_PA26X1_PIODC2 (1u << 26) /**< \brief Pioa signal: PIODC2 */\r
+#define PIO_PA27X1_PIODC3 (1u << 27) /**< \brief Pioa signal: PIODC3 */\r
+#define PIO_PA28X1_PIODC4 (1u << 28) /**< \brief Pioa signal: PIODC4 */\r
+#define PIO_PA29X1_PIODC5 (1u << 29) /**< \brief Pioa signal: PIODC5 */\r
+#define PIO_PA31X1_PIODC7 (1u << 31) /**< \brief Pioa signal: PIODC7 */\r
+#define PIO_PA23X1_PIODCCLK (1u << 23) /**< \brief Pioa signal: PIODCCLK */\r
+#define PIO_PA30X1_WKUP11 (1u << 30) /**< \brief Pioa signal: WKUP11/PIODC6 */\r
+#define PIO_PA30X1_PIODC6 (1u << 30) /**< \brief Pioa signal: WKUP11/PIODC6 */\r
+#define PIO_PA15X1_WKUP14 (1u << 15) /**< \brief Pioa signal: WKUP14/PIODCEN1 */\r
+#define PIO_PA15X1_PIODCEN1 (1u << 15) /**< \brief Pioa signal: WKUP14/PIODCEN1 */\r
+#define PIO_PA16X1_WKUP15 (1u << 16) /**< \brief Pioa signal: WKUP15/PIODCEN2 */\r
+#define PIO_PA16X1_PIODCEN2 (1u << 16) /**< \brief Pioa signal: WKUP15/PIODCEN2 */\r
+/* ========== Pio definition for PMC peripheral ========== */\r
+#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */\r
+#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */\r
+#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */\r
+#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */\r
+#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */\r
+#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */\r
+#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */\r
+/* ========== Pio definition for PWM peripheral ========== */\r
+#define PIO_PA9C_PWMFI0 (1u << 9) /**< \brief Pwm signal: PWMFI0 */\r
+#define PIO_PA0A_PWMH0 (1u << 0) /**< \brief Pwm signal: PWMH0 */\r
+#define PIO_PA11B_PWMH0 (1u << 11) /**< \brief Pwm signal: PWMH0 */\r
+#define PIO_PA23B_PWMH0 (1u << 23) /**< \brief Pwm signal: PWMH0 */\r
+#define PIO_PB0A_PWMH0 (1u << 0) /**< \brief Pwm signal: PWMH0 */\r
+#define PIO_PC18B_PWMH0 (1u << 18) /**< \brief Pwm signal: PWMH0 */\r
+#define PIO_PD20A_PWMH0 (1u << 20) /**< \brief Pwm signal: PWMH0 */\r
+#define PIO_PA1A_PWMH1 (1u << 1) /**< \brief Pwm signal: PWMH1 */\r
+#define PIO_PA12B_PWMH1 (1u << 12) /**< \brief Pwm signal: PWMH1 */\r
+#define PIO_PA24B_PWMH1 (1u << 24) /**< \brief Pwm signal: PWMH1 */\r
+#define PIO_PB1A_PWMH1 (1u << 1) /**< \brief Pwm signal: PWMH1 */\r
+#define PIO_PC19B_PWMH1 (1u << 19) /**< \brief Pwm signal: PWMH1 */\r
+#define PIO_PD21A_PWMH1 (1u << 21) /**< \brief Pwm signal: PWMH1 */\r
+#define PIO_PA2A_PWMH2 (1u << 2) /**< \brief Pwm signal: PWMH2 */\r
+#define PIO_PA13B_PWMH2 (1u << 13) /**< \brief Pwm signal: PWMH2 */\r
+#define PIO_PA25B_PWMH2 (1u << 25) /**< \brief Pwm signal: PWMH2 */\r
+#define PIO_PB4B_PWMH2 (1u << 4) /**< \brief Pwm signal: PWMH2 */\r
+#define PIO_PC20B_PWMH2 (1u << 20) /**< \brief Pwm signal: PWMH2 */\r
+#define PIO_PD22A_PWMH2 (1u << 22) /**< \brief Pwm signal: PWMH2 */\r
+#define PIO_PA7B_PWMH3 (1u << 7) /**< \brief Pwm signal: PWMH3 */\r
+#define PIO_PA14B_PWMH3 (1u << 14) /**< \brief Pwm signal: PWMH3 */\r
+#define PIO_PA17C_PWMH3 (1u << 17) /**< \brief Pwm signal: PWMH3 */\r
+#define PIO_PB14B_PWMH3 (1u << 14) /**< \brief Pwm signal: PWMH3 */\r
+#define PIO_PC21B_PWMH3 (1u << 21) /**< \brief Pwm signal: PWMH3 */\r
+#define PIO_PD23A_PWMH3 (1u << 23) /**< \brief Pwm signal: PWMH3 */\r
+#define PIO_PA19B_PWML0 (1u << 19) /**< \brief Pwm signal: PWML0 */\r
+#define PIO_PB5B_PWML0 (1u << 5) /**< \brief Pwm signal: PWML0 */\r
+#define PIO_PC0B_PWML0 (1u << 0) /**< \brief Pwm signal: PWML0 */\r
+#define PIO_PC13B_PWML0 (1u << 13) /**< \brief Pwm signal: PWML0 */\r
+#define PIO_PD24A_PWML0 (1u << 24) /**< \brief Pwm signal: PWML0 */\r
+#define PIO_PA20B_PWML1 (1u << 20) /**< \brief Pwm signal: PWML1 */\r
+#define PIO_PB12A_PWML1 (1u << 12) /**< \brief Pwm signal: PWML1 */\r
+#define PIO_PC1B_PWML1 (1u << 1) /**< \brief Pwm signal: PWML1 */\r
+#define PIO_PC15B_PWML1 (1u << 15) /**< \brief Pwm signal: PWML1 */\r
+#define PIO_PD25A_PWML1 (1u << 25) /**< \brief Pwm signal: PWML1 */\r
+#define PIO_PA16C_PWML2 (1u << 16) /**< \brief Pwm signal: PWML2 */\r
+#define PIO_PA30A_PWML2 (1u << 30) /**< \brief Pwm signal: PWML2 */\r
+#define PIO_PB13A_PWML2 (1u << 13) /**< \brief Pwm signal: PWML2 */\r
+#define PIO_PC2B_PWML2 (1u << 2) /**< \brief Pwm signal: PWML2 */\r
+#define PIO_PD26A_PWML2 (1u << 26) /**< \brief Pwm signal: PWML2 */\r
+#define PIO_PA15C_PWML3 (1u << 15) /**< \brief Pwm signal: PWML3 */\r
+#define PIO_PC3B_PWML3 (1u << 3) /**< \brief Pwm signal: PWML3 */\r
+#define PIO_PC22B_PWML3 (1u << 22) /**< \brief Pwm signal: PWML3 */\r
+#define PIO_PD27A_PWML3 (1u << 27) /**< \brief Pwm signal: PWML3 */\r
+/* ========== Pio definition for SPI peripheral ========== */\r
+#define PIO_PA12A_MISO (1u << 12) /**< \brief Spi signal: MISO */\r
+#define PIO_PA13A_MOSI (1u << 13) /**< \brief Spi signal: MOSI */\r
+#define PIO_PA11A_NPCS0 (1u << 11) /**< \brief Spi signal: NPCS0 */\r
+#define PIO_PA9B_NPCS1 (1u << 9) /**< \brief Spi signal: NPCS1 */\r
+#define PIO_PA31A_NPCS1 (1u << 31) /**< \brief Spi signal: NPCS1 */\r
+#define PIO_PB14A_NPCS1 (1u << 14) /**< \brief Spi signal: NPCS1 */\r
+#define PIO_PC4B_NPCS1 (1u << 4) /**< \brief Spi signal: NPCS1 */\r
+#define PIO_PA10B_NPCS2 (1u << 10) /**< \brief Spi signal: NPCS2 */\r
+#define PIO_PA30B_NPCS2 (1u << 30) /**< \brief Spi signal: NPCS2 */\r
+#define PIO_PB2B_NPCS2 (1u << 2) /**< \brief Spi signal: NPCS2 */\r
+#define PIO_PA3B_NPCS3 (1u << 3) /**< \brief Spi signal: NPCS3 */\r
+#define PIO_PA5B_NPCS3 (1u << 5) /**< \brief Spi signal: NPCS3 */\r
+#define PIO_PA22B_NPCS3 (1u << 22) /**< \brief Spi signal: NPCS3 */\r
+#define PIO_PA14A_SPCK (1u << 14) /**< \brief Spi signal: SPCK */\r
+/* ========== Pio definition for TC0 peripheral ========== */\r
+#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */\r
+#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */\r
+#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */\r
+#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */\r
+#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */\r
+#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */\r
+#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */\r
+#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */\r
+#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */\r
+/* ========== Pio definition for TC1 peripheral ========== */\r
+#define PIO_PC25B_TCLK3 (1u << 25) /**< \brief Tc1 signal: TCLK3 */\r
+#define PIO_PC28B_TCLK4 (1u << 28) /**< \brief Tc1 signal: TCLK4 */\r
+#define PIO_PC31B_TCLK5 (1u << 31) /**< \brief Tc1 signal: TCLK5 */\r
+#define PIO_PC23B_TIOA3 (1u << 23) /**< \brief Tc1 signal: TIOA3 */\r
+#define PIO_PC26B_TIOA4 (1u << 26) /**< \brief Tc1 signal: TIOA4 */\r
+#define PIO_PC29B_TIOA5 (1u << 29) /**< \brief Tc1 signal: TIOA5 */\r
+#define PIO_PC24B_TIOB3 (1u << 24) /**< \brief Tc1 signal: TIOB3 */\r
+#define PIO_PC27B_TIOB4 (1u << 27) /**< \brief Tc1 signal: TIOB4 */\r
+#define PIO_PC30B_TIOB5 (1u << 30) /**< \brief Tc1 signal: TIOB5 */\r
+/* ========== Pio definition for TC2 peripheral ========== */\r
+#define PIO_PC7B_TCLK6 (1u << 7) /**< \brief Tc2 signal: TCLK6 */\r
+#define PIO_PC10B_TCLK7 (1u << 10) /**< \brief Tc2 signal: TCLK7 */\r
+#define PIO_PC14B_TCLK8 (1u << 14) /**< \brief Tc2 signal: TCLK8 */\r
+#define PIO_PC5B_TIOA6 (1u << 5) /**< \brief Tc2 signal: TIOA6 */\r
+#define PIO_PC8B_TIOA7 (1u << 8) /**< \brief Tc2 signal: TIOA7 */\r
+#define PIO_PC11B_TIOA8 (1u << 11) /**< \brief Tc2 signal: TIOA8 */\r
+#define PIO_PC6B_TIOB6 (1u << 6) /**< \brief Tc2 signal: TIOB6 */\r
+#define PIO_PC9B_TIOB7 (1u << 9) /**< \brief Tc2 signal: TIOB7 */\r
+#define PIO_PC12B_TIOB8 (1u << 12) /**< \brief Tc2 signal: TIOB8 */\r
+/* ========== Pio definition for TWI0 peripheral ========== */\r
+#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twi0 signal: TWCK0 */\r
+#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twi0 signal: TWD0 */\r
+/* ========== Pio definition for TWI1 peripheral ========== */\r
+#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twi1 signal: TWCK1 */\r
+#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twi1 signal: TWD1 */\r
+/* ========== Pio definition for UART0 peripheral ========== */\r
+#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */\r
+#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */\r
+/* ========== Pio definition for UART1 peripheral ========== */\r
+#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */\r
+#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */\r
+/* ========== Pio definition for USART0 peripheral ========== */\r
+#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */\r
+#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */\r
+#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */\r
+#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */\r
+#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */\r
+/* ========== Pio definition for USART1 peripheral ========== */\r
+#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */\r
+#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */\r
+#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */\r
+#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */\r
+#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */\r
+#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */\r
+#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */\r
+#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */\r
+#define PIO_PA22A_TXD1 (1u << 22) /**< \brief Usart1 signal: TXD1 */\r
+/* ========== Pio indexes ========== */\r
+#define PIO_PA0_IDX 0\r
+#define PIO_PA1_IDX 1\r
+#define PIO_PA2_IDX 2\r
+#define PIO_PA3_IDX 3\r
+#define PIO_PA4_IDX 4\r
+#define PIO_PA5_IDX 5\r
+#define PIO_PA6_IDX 6\r
+#define PIO_PA7_IDX 7\r
+#define PIO_PA8_IDX 8\r
+#define PIO_PA9_IDX 9\r
+#define PIO_PA10_IDX 10\r
+#define PIO_PA11_IDX 11\r
+#define PIO_PA12_IDX 12\r
+#define PIO_PA13_IDX 13\r
+#define PIO_PA14_IDX 14\r
+#define PIO_PA15_IDX 15\r
+#define PIO_PA16_IDX 16\r
+#define PIO_PA17_IDX 17\r
+#define PIO_PA18_IDX 18\r
+#define PIO_PA19_IDX 19\r
+#define PIO_PA20_IDX 20\r
+#define PIO_PA21_IDX 21\r
+#define PIO_PA22_IDX 22\r
+#define PIO_PA23_IDX 23\r
+#define PIO_PA24_IDX 24\r
+#define PIO_PA25_IDX 25\r
+#define PIO_PA26_IDX 26\r
+#define PIO_PA27_IDX 27\r
+#define PIO_PA28_IDX 28\r
+#define PIO_PA29_IDX 29\r
+#define PIO_PA30_IDX 30\r
+#define PIO_PA31_IDX 31\r
+#define PIO_PB0_IDX 32\r
+#define PIO_PB1_IDX 33\r
+#define PIO_PB2_IDX 34\r
+#define PIO_PB3_IDX 35\r
+#define PIO_PB4_IDX 36\r
+#define PIO_PB5_IDX 37\r
+#define PIO_PB6_IDX 38\r
+#define PIO_PB7_IDX 39\r
+#define PIO_PB8_IDX 40\r
+#define PIO_PB9_IDX 41\r
+#define PIO_PB10_IDX 42\r
+#define PIO_PB11_IDX 43\r
+#define PIO_PB12_IDX 44\r
+#define PIO_PB13_IDX 45\r
+#define PIO_PB14_IDX 46\r
+#define PIO_PC0_IDX 64\r
+#define PIO_PC1_IDX 65\r
+#define PIO_PC2_IDX 66\r
+#define PIO_PC3_IDX 67\r
+#define PIO_PC4_IDX 68\r
+#define PIO_PC5_IDX 69\r
+#define PIO_PC6_IDX 70\r
+#define PIO_PC7_IDX 71\r
+#define PIO_PC8_IDX 72\r
+#define PIO_PC9_IDX 73\r
+#define PIO_PC10_IDX 74\r
+#define PIO_PC11_IDX 75\r
+#define PIO_PC12_IDX 76\r
+#define PIO_PC13_IDX 77\r
+#define PIO_PC14_IDX 78\r
+#define PIO_PC15_IDX 79\r
+#define PIO_PC16_IDX 80\r
+#define PIO_PC17_IDX 81\r
+#define PIO_PC18_IDX 82\r
+#define PIO_PC19_IDX 83\r
+#define PIO_PC20_IDX 84\r
+#define PIO_PC21_IDX 85\r
+#define PIO_PC22_IDX 86\r
+#define PIO_PC23_IDX 87\r
+#define PIO_PC24_IDX 88\r
+#define PIO_PC25_IDX 89\r
+#define PIO_PC26_IDX 90\r
+#define PIO_PC27_IDX 91\r
+#define PIO_PC28_IDX 92\r
+#define PIO_PC29_IDX 93\r
+#define PIO_PC30_IDX 94\r
+#define PIO_PC31_IDX 95\r
+#define PIO_PD0_IDX 96\r
+#define PIO_PD1_IDX 97\r
+#define PIO_PD2_IDX 98\r
+#define PIO_PD3_IDX 99\r
+#define PIO_PD4_IDX 100\r
+#define PIO_PD5_IDX 101\r
+#define PIO_PD6_IDX 102\r
+#define PIO_PD7_IDX 103\r
+#define PIO_PD8_IDX 104\r
+#define PIO_PD9_IDX 105\r
+#define PIO_PD10_IDX 106\r
+#define PIO_PD11_IDX 107\r
+#define PIO_PD12_IDX 108\r
+#define PIO_PD13_IDX 109\r
+#define PIO_PD14_IDX 110\r
+#define PIO_PD15_IDX 111\r
+#define PIO_PD16_IDX 112\r
+#define PIO_PD17_IDX 113\r
+#define PIO_PD18_IDX 114\r
+#define PIO_PD19_IDX 115\r
+#define PIO_PD20_IDX 116\r
+#define PIO_PD21_IDX 117\r
+#define PIO_PD22_IDX 118\r
+#define PIO_PD23_IDX 119\r
+#define PIO_PD24_IDX 120\r
+#define PIO_PD25_IDX 121\r
+#define PIO_PD26_IDX 122\r
+#define PIO_PD27_IDX 123\r
+#define PIO_PD28_IDX 124\r
+#define PIO_PD29_IDX 125\r
+#define PIO_PD30_IDX 126\r
+#define PIO_PD31_IDX 127\r
+#define PIO_PE0_IDX 128\r
+#define PIO_PE1_IDX 129\r
+#define PIO_PE2_IDX 130\r
+#define PIO_PE3_IDX 131\r
+#define PIO_PE4_IDX 132\r
+#define PIO_PE5_IDX 133\r
+\r
+#endif /* _SAM4E16C_PIO_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4E16E_PIO_\r
+#define _SAM4E16E_PIO_\r
+\r
+#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */\r
+#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */\r
+#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */\r
+#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */\r
+#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */\r
+#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */\r
+#define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */\r
+#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */\r
+#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */\r
+#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */\r
+#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */\r
+#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */\r
+#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */\r
+#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */\r
+#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */\r
+#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */\r
+#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */\r
+#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */\r
+#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */\r
+#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */\r
+#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */\r
+#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */\r
+#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */\r
+#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */\r
+#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */\r
+#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */\r
+#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */\r
+#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */\r
+#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */\r
+#define PIO_PA29 (1u << 29) /**< \brief Pin Controlled by PA29 */\r
+#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */\r
+#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */\r
+#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */\r
+#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */\r
+#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */\r
+#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */\r
+#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */\r
+#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */\r
+#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */\r
+#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */\r
+#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */\r
+#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */\r
+#define PIO_PB10 (1u << 10) /**< \brief Pin Controlled by PB10 */\r
+#define PIO_PB11 (1u << 11) /**< \brief Pin Controlled by PB11 */\r
+#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */\r
+#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */\r
+#define PIO_PB14 (1u << 14) /**< \brief Pin Controlled by PB14 */\r
+#define PIO_PC0 (1u << 0) /**< \brief Pin Controlled by PC0 */\r
+#define PIO_PC1 (1u << 1) /**< \brief Pin Controlled by PC1 */\r
+#define PIO_PC2 (1u << 2) /**< \brief Pin Controlled by PC2 */\r
+#define PIO_PC3 (1u << 3) /**< \brief Pin Controlled by PC3 */\r
+#define PIO_PC4 (1u << 4) /**< \brief Pin Controlled by PC4 */\r
+#define PIO_PC5 (1u << 5) /**< \brief Pin Controlled by PC5 */\r
+#define PIO_PC6 (1u << 6) /**< \brief Pin Controlled by PC6 */\r
+#define PIO_PC7 (1u << 7) /**< \brief Pin Controlled by PC7 */\r
+#define PIO_PC8 (1u << 8) /**< \brief Pin Controlled by PC8 */\r
+#define PIO_PC9 (1u << 9) /**< \brief Pin Controlled by PC9 */\r
+#define PIO_PC10 (1u << 10) /**< \brief Pin Controlled by PC10 */\r
+#define PIO_PC11 (1u << 11) /**< \brief Pin Controlled by PC11 */\r
+#define PIO_PC12 (1u << 12) /**< \brief Pin Controlled by PC12 */\r
+#define PIO_PC13 (1u << 13) /**< \brief Pin Controlled by PC13 */\r
+#define PIO_PC14 (1u << 14) /**< \brief Pin Controlled by PC14 */\r
+#define PIO_PC15 (1u << 15) /**< \brief Pin Controlled by PC15 */\r
+#define PIO_PC16 (1u << 16) /**< \brief Pin Controlled by PC16 */\r
+#define PIO_PC17 (1u << 17) /**< \brief Pin Controlled by PC17 */\r
+#define PIO_PC18 (1u << 18) /**< \brief Pin Controlled by PC18 */\r
+#define PIO_PC19 (1u << 19) /**< \brief Pin Controlled by PC19 */\r
+#define PIO_PC20 (1u << 20) /**< \brief Pin Controlled by PC20 */\r
+#define PIO_PC21 (1u << 21) /**< \brief Pin Controlled by PC21 */\r
+#define PIO_PC22 (1u << 22) /**< \brief Pin Controlled by PC22 */\r
+#define PIO_PC23 (1u << 23) /**< \brief Pin Controlled by PC23 */\r
+#define PIO_PC24 (1u << 24) /**< \brief Pin Controlled by PC24 */\r
+#define PIO_PC25 (1u << 25) /**< \brief Pin Controlled by PC25 */\r
+#define PIO_PC26 (1u << 26) /**< \brief Pin Controlled by PC26 */\r
+#define PIO_PC27 (1u << 27) /**< \brief Pin Controlled by PC27 */\r
+#define PIO_PC28 (1u << 28) /**< \brief Pin Controlled by PC28 */\r
+#define PIO_PC29 (1u << 29) /**< \brief Pin Controlled by PC29 */\r
+#define PIO_PC30 (1u << 30) /**< \brief Pin Controlled by PC30 */\r
+#define PIO_PC31 (1u << 31) /**< \brief Pin Controlled by PC31 */\r
+#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */\r
+#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */\r
+#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */\r
+#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */\r
+#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */\r
+#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */\r
+#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */\r
+#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */\r
+#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */\r
+#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */\r
+#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */\r
+#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */\r
+#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */\r
+#define PIO_PD13 (1u << 13) /**< \brief Pin Controlled by PD13 */\r
+#define PIO_PD14 (1u << 14) /**< \brief Pin Controlled by PD14 */\r
+#define PIO_PD15 (1u << 15) /**< \brief Pin Controlled by PD15 */\r
+#define PIO_PD16 (1u << 16) /**< \brief Pin Controlled by PD16 */\r
+#define PIO_PD17 (1u << 17) /**< \brief Pin Controlled by PD17 */\r
+#define PIO_PD18 (1u << 18) /**< \brief Pin Controlled by PD18 */\r
+#define PIO_PD19 (1u << 19) /**< \brief Pin Controlled by PD19 */\r
+#define PIO_PD20 (1u << 20) /**< \brief Pin Controlled by PD20 */\r
+#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */\r
+#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */\r
+#define PIO_PD23 (1u << 23) /**< \brief Pin Controlled by PD23 */\r
+#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */\r
+#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */\r
+#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */\r
+#define PIO_PD27 (1u << 27) /**< \brief Pin Controlled by PD27 */\r
+#define PIO_PD28 (1u << 28) /**< \brief Pin Controlled by PD28 */\r
+#define PIO_PD29 (1u << 29) /**< \brief Pin Controlled by PD29 */\r
+#define PIO_PD30 (1u << 30) /**< \brief Pin Controlled by PD30 */\r
+#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */\r
+#define PIO_PE0 (1u << 0) /**< \brief Pin Controlled by PE0 */\r
+#define PIO_PE1 (1u << 1) /**< \brief Pin Controlled by PE1 */\r
+#define PIO_PE2 (1u << 2) /**< \brief Pin Controlled by PE2 */\r
+#define PIO_PE3 (1u << 3) /**< \brief Pin Controlled by PE3 */\r
+#define PIO_PE4 (1u << 4) /**< \brief Pin Controlled by PE4 */\r
+#define PIO_PE5 (1u << 5) /**< \brief Pin Controlled by PE5 */\r
+/* ========== Pio definition for AFEC0 peripheral ========== */\r
+#define PIO_PA17X1_AFE0_AD0 (1u << 17) /**< \brief Afec0 signal: AFE0_AD0 */\r
+#define PIO_PA18X1_AFE0_AD1 (1u << 18) /**< \brief Afec0 signal: AFE0_AD1 */\r
+#define PIO_PC30X1_AFE0_AD10 (1u << 30) /**< \brief Afec0 signal: AFE0_AD10 */\r
+#define PIO_PC31X1_AFE0_AD11 (1u << 31) /**< \brief Afec0 signal: AFE0_AD11 */\r
+#define PIO_PC26X1_AFE0_AD12 (1u << 26) /**< \brief Afec0 signal: AFE0_AD12 */\r
+#define PIO_PC27X1_AFE0_AD13 (1u << 27) /**< \brief Afec0 signal: AFE0_AD13 */\r
+#define PIO_PC0X1_AFE0_AD14 (1u << 0) /**< \brief Afec0 signal: AFE0_AD14 */\r
+#define PIO_PA19X1_AFE0_AD2 (1u << 19) /**< \brief Afec0 signal: AFE0_AD2/WKUP9 */\r
+#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD2/WKUP9 */\r
+#define PIO_PA20X1_AFE0_AD3 (1u << 20) /**< \brief Afec0 signal: AFE0_AD3/WKUP10 */\r
+#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD3/WKUP10 */\r
+#define PIO_PB0X1_AFE0_AD4 (1u << 0) /**< \brief Afec0 signal: AFE0_AD4/RTCOUT0 */\r
+#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD4/RTCOUT0 */\r
+#define PIO_PB1X1_AFE0_AD5 (1u << 1) /**< \brief Afec0 signal: AFE0_AD5/RTCOUT1 */\r
+#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec0 signal: AFE0_AD5/RTCOUT1 */\r
+#define PIO_PC13X1_AFE0_AD6 (1u << 13) /**< \brief Afec0 signal: AFE0_AD6 */\r
+#define PIO_PC15X1_AFE0_AD7 (1u << 15) /**< \brief Afec0 signal: AFE0_AD7 */\r
+#define PIO_PC12X1_AFE0_AD8 (1u << 12) /**< \brief Afec0 signal: AFE0_AD8 */\r
+#define PIO_PC29X1_AFE0_AD9 (1u << 29) /**< \brief Afec0 signal: AFE0_AD9 */\r
+#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */\r
+/* ========== Pio definition for AFEC1 peripheral ========== */\r
+#define PIO_PB2X1_AFE1_AD0 (1u << 2) /**< \brief Afec1 signal: AFE1_AD0/WKUP12 */\r
+#define PIO_PB2X1_WKUP12 (1u << 2) /**< \brief Afec1 signal: AFE1_AD0/WKUP12 */\r
+#define PIO_PB3X1_AFE1_AD1 (1u << 3) /**< \brief Afec1 signal: AFE1_AD1 */\r
+#define PIO_PA21X1_AFE1_AD2 (1u << 21) /**< \brief Afec1 signal: AFE1_AD2 */\r
+#define PIO_PA22X1_AFE1_AD3 (1u << 22) /**< \brief Afec1 signal: AFE1_AD3 */\r
+#define PIO_PC1X1_AFE1_AD4 (1u << 1) /**< \brief Afec1 signal: AFE1_AD4 */\r
+#define PIO_PC2X1_AFE1_AD5 (1u << 2) /**< \brief Afec1 signal: AFE1_AD5 */\r
+#define PIO_PC3X1_AFE1_AD6 (1u << 3) /**< \brief Afec1 signal: AFE1_AD6 */\r
+#define PIO_PC4X1_AFE1_AD7 (1u << 4) /**< \brief Afec1 signal: AFE1_AD7 */\r
+/* ========== Pio definition for CAN0 peripheral ========== */\r
+#define PIO_PB3A_CANRX0 (1u << 3) /**< \brief Can0 signal: CANRX0 */\r
+#define PIO_PB2A_CANTX0 (1u << 2) /**< \brief Can0 signal: CANTX0 */\r
+/* ========== Pio definition for CAN1 peripheral ========== */\r
+#define PIO_PC12C_CANRX1 (1u << 12) /**< \brief Can1 signal: CANRX1 */\r
+#define PIO_PC15C_CANTX1 (1u << 15) /**< \brief Can1 signal: CANTX1 */\r
+/* ========== Pio definition for DACC peripheral ========== */\r
+#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */\r
+#define PIO_PB14X1_DAC1 (1u << 14) /**< \brief Dacc signal: DAC1 */\r
+#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */\r
+/* ========== Pio definition for EBI peripheral ========== */\r
+#define PIO_PC18A_A0 (1u << 18) /**< \brief Ebi signal: A0 */\r
+#define PIO_PC19A_A1 (1u << 19) /**< \brief Ebi signal: A1 */\r
+#define PIO_PC28A_A10 (1u << 28) /**< \brief Ebi signal: A10 */\r
+#define PIO_PC29A_A11 (1u << 29) /**< \brief Ebi signal: A11 */\r
+#define PIO_PC30A_A12 (1u << 30) /**< \brief Ebi signal: A12 */\r
+#define PIO_PC31A_A13 (1u << 31) /**< \brief Ebi signal: A13 */\r
+#define PIO_PA18C_A14 (1u << 18) /**< \brief Ebi signal: A14 */\r
+#define PIO_PA19C_A15 (1u << 19) /**< \brief Ebi signal: A15 */\r
+#define PIO_PA20C_A16 (1u << 20) /**< \brief Ebi signal: A16 */\r
+#define PIO_PA0C_A17 (1u << 0) /**< \brief Ebi signal: A17 */\r
+#define PIO_PA1C_A18 (1u << 1) /**< \brief Ebi signal: A18 */\r
+#define PIO_PA23C_A19 (1u << 23) /**< \brief Ebi signal: A19 */\r
+#define PIO_PC20A_A2 (1u << 20) /**< \brief Ebi signal: A2 */\r
+#define PIO_PA24C_A20 (1u << 24) /**< \brief Ebi signal: A20 */\r
+#define PIO_PC16A_A21 (1u << 16) /**< \brief Ebi signal: A21/NANDALE */\r
+#define PIO_PC16A_NANDALE (1u << 16) /**< \brief Ebi signal: A21/NANDALE */\r
+#define PIO_PC17A_A22 (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */\r
+#define PIO_PC17A_NANDCLE (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */\r
+#define PIO_PA25C_A23 (1u << 25) /**< \brief Ebi signal: A23 */\r
+#define PIO_PC21A_A3 (1u << 21) /**< \brief Ebi signal: A3 */\r
+#define PIO_PC22A_A4 (1u << 22) /**< \brief Ebi signal: A4 */\r
+#define PIO_PC23A_A5 (1u << 23) /**< \brief Ebi signal: A5 */\r
+#define PIO_PC24A_A6 (1u << 24) /**< \brief Ebi signal: A6 */\r
+#define PIO_PC25A_A7 (1u << 25) /**< \brief Ebi signal: A7 */\r
+#define PIO_PC26A_A8 (1u << 26) /**< \brief Ebi signal: A8 */\r
+#define PIO_PC27A_A9 (1u << 27) /**< \brief Ebi signal: A9 */\r
+#define PIO_PC0A_D0 (1u << 0) /**< \brief Ebi signal: D0 */\r
+#define PIO_PC1A_D1 (1u << 1) /**< \brief Ebi signal: D1 */\r
+#define PIO_PC2A_D2 (1u << 2) /**< \brief Ebi signal: D2 */\r
+#define PIO_PC3A_D3 (1u << 3) /**< \brief Ebi signal: D3 */\r
+#define PIO_PC4A_D4 (1u << 4) /**< \brief Ebi signal: D4 */\r
+#define PIO_PC5A_D5 (1u << 5) /**< \brief Ebi signal: D5 */\r
+#define PIO_PC6A_D6 (1u << 6) /**< \brief Ebi signal: D6 */\r
+#define PIO_PC7A_D7 (1u << 7) /**< \brief Ebi signal: D7 */\r
+#define PIO_PC9A_NANDOE (1u << 9) /**< \brief Ebi signal: NANDOE */\r
+#define PIO_PC10A_NANDWE (1u << 10) /**< \brief Ebi signal: NANDWE */\r
+#define PIO_PC14A_NCS0 (1u << 14) /**< \brief Ebi signal: NCS0 */\r
+#define PIO_PC15A_NCS1 (1u << 15) /**< \brief Ebi signal: NCS1 */\r
+#define PIO_PD18A_NCS1 (1u << 18) /**< \brief Ebi signal: NCS1 */\r
+#define PIO_PA22C_NCS2 (1u << 22) /**< \brief Ebi signal: NCS2 */\r
+#define PIO_PC12A_NCS3 (1u << 12) /**< \brief Ebi signal: NCS3 */\r
+#define PIO_PD19A_NCS3 (1u << 19) /**< \brief Ebi signal: NCS3 */\r
+#define PIO_PC11A_NRD (1u << 11) /**< \brief Ebi signal: NRD */\r
+#define PIO_PC13A_NWAIT (1u << 13) /**< \brief Ebi signal: NWAIT */\r
+#define PIO_PC8A_NWE (1u << 8) /**< \brief Ebi signal: NWE */\r
+/* ========== Pio definition for GMAC peripheral ========== */\r
+#define PIO_PD13A_GCOL (1u << 13) /**< \brief Gmac signal: GCOL */\r
+#define PIO_PD10A_GCRS (1u << 10) /**< \brief Gmac signal: GCRS */\r
+#define PIO_PD4A_GCRSDV (1u << 4) /**< \brief Gmac signal: GCRSDV/GRXDV */\r
+#define PIO_PD4A_GRXDV (1u << 4) /**< \brief Gmac signal: GCRSDV/GRXDV */\r
+#define PIO_PD8A_GMDC (1u << 8) /**< \brief Gmac signal: GMDC */\r
+#define PIO_PD9A_GMDIO (1u << 9) /**< \brief Gmac signal: GMDIO */\r
+#define PIO_PD5A_GRX0 (1u << 5) /**< \brief Gmac signal: GRX0 */\r
+#define PIO_PD6A_GRX0 (1u << 6) /**< \brief Gmac signal: GRX0 */\r
+#define PIO_PD11A_GRX2 (1u << 11) /**< \brief Gmac signal: GRX2 */\r
+#define PIO_PD12A_GRX3 (1u << 12) /**< \brief Gmac signal: GRX3 */\r
+#define PIO_PD14A_GRXCK (1u << 14) /**< \brief Gmac signal: GRXCK */\r
+#define PIO_PD7A_GRXER (1u << 7) /**< \brief Gmac signal: GRXER */\r
+#define PIO_PD2A_GTX0 (1u << 2) /**< \brief Gmac signal: GTX0 */\r
+#define PIO_PD3A_GTX1 (1u << 3) /**< \brief Gmac signal: GTX1 */\r
+#define PIO_PD15A_GTX2 (1u << 15) /**< \brief Gmac signal: GTX2 */\r
+#define PIO_PD16A_GTX3 (1u << 16) /**< \brief Gmac signal: GTX3 */\r
+#define PIO_PD0A_GTXCK (1u << 0) /**< \brief Gmac signal: GTXCK/GREFCK */\r
+#define PIO_PD0A_GREFCK (1u << 0) /**< \brief Gmac signal: GTXCK/GREFCK */\r
+#define PIO_PD1A_GTXEN (1u << 1) /**< \brief Gmac signal: GTXEN */\r
+#define PIO_PD17A_GTXER (1u << 17) /**< \brief Gmac signal: GTXER */\r
+/* ========== Pio definition for HSMCI peripheral ========== */\r
+#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */\r
+#define PIO_PA29C_MCCK (1u << 29) /**< \brief Hsmci signal: MCCK */\r
+#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */\r
+#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */\r
+#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */\r
+#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */\r
+/* ========== Pio definition for PIOA peripheral ========== */\r
+#define PIO_PA24X1_PIODC0 (1u << 24) /**< \brief Pioa signal: PIODC0 */\r
+#define PIO_PA25X1_PIODC1 (1u << 25) /**< \brief Pioa signal: PIODC1 */\r
+#define PIO_PA26X1_PIODC2 (1u << 26) /**< \brief Pioa signal: PIODC2 */\r
+#define PIO_PA27X1_PIODC3 (1u << 27) /**< \brief Pioa signal: PIODC3 */\r
+#define PIO_PA28X1_PIODC4 (1u << 28) /**< \brief Pioa signal: PIODC4 */\r
+#define PIO_PA29X1_PIODC5 (1u << 29) /**< \brief Pioa signal: PIODC5 */\r
+#define PIO_PA31X1_PIODC7 (1u << 31) /**< \brief Pioa signal: PIODC7 */\r
+#define PIO_PA23X1_PIODCCLK (1u << 23) /**< \brief Pioa signal: PIODCCLK */\r
+#define PIO_PA30X1_WKUP11 (1u << 30) /**< \brief Pioa signal: WKUP11/PIODC6 */\r
+#define PIO_PA30X1_PIODC6 (1u << 30) /**< \brief Pioa signal: WKUP11/PIODC6 */\r
+#define PIO_PA15X1_WKUP14 (1u << 15) /**< \brief Pioa signal: WKUP14/PIODCEN1 */\r
+#define PIO_PA15X1_PIODCEN1 (1u << 15) /**< \brief Pioa signal: WKUP14/PIODCEN1 */\r
+#define PIO_PA16X1_WKUP15 (1u << 16) /**< \brief Pioa signal: WKUP15/PIODCEN2 */\r
+#define PIO_PA16X1_PIODCEN2 (1u << 16) /**< \brief Pioa signal: WKUP15/PIODCEN2 */\r
+/* ========== Pio definition for PMC peripheral ========== */\r
+#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */\r
+#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */\r
+#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */\r
+#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */\r
+#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */\r
+#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */\r
+#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */\r
+/* ========== Pio definition for PWM peripheral ========== */\r
+#define PIO_PA9C_PWMFI0 (1u << 9) /**< \brief Pwm signal: PWMFI0 */\r
+#define PIO_PA0A_PWMH0 (1u << 0) /**< \brief Pwm signal: PWMH0 */\r
+#define PIO_PA11B_PWMH0 (1u << 11) /**< \brief Pwm signal: PWMH0 */\r
+#define PIO_PA23B_PWMH0 (1u << 23) /**< \brief Pwm signal: PWMH0 */\r
+#define PIO_PB0A_PWMH0 (1u << 0) /**< \brief Pwm signal: PWMH0 */\r
+#define PIO_PC18B_PWMH0 (1u << 18) /**< \brief Pwm signal: PWMH0 */\r
+#define PIO_PD20A_PWMH0 (1u << 20) /**< \brief Pwm signal: PWMH0 */\r
+#define PIO_PA1A_PWMH1 (1u << 1) /**< \brief Pwm signal: PWMH1 */\r
+#define PIO_PA12B_PWMH1 (1u << 12) /**< \brief Pwm signal: PWMH1 */\r
+#define PIO_PA24B_PWMH1 (1u << 24) /**< \brief Pwm signal: PWMH1 */\r
+#define PIO_PB1A_PWMH1 (1u << 1) /**< \brief Pwm signal: PWMH1 */\r
+#define PIO_PC19B_PWMH1 (1u << 19) /**< \brief Pwm signal: PWMH1 */\r
+#define PIO_PD21A_PWMH1 (1u << 21) /**< \brief Pwm signal: PWMH1 */\r
+#define PIO_PA2A_PWMH2 (1u << 2) /**< \brief Pwm signal: PWMH2 */\r
+#define PIO_PA13B_PWMH2 (1u << 13) /**< \brief Pwm signal: PWMH2 */\r
+#define PIO_PA25B_PWMH2 (1u << 25) /**< \brief Pwm signal: PWMH2 */\r
+#define PIO_PB4B_PWMH2 (1u << 4) /**< \brief Pwm signal: PWMH2 */\r
+#define PIO_PC20B_PWMH2 (1u << 20) /**< \brief Pwm signal: PWMH2 */\r
+#define PIO_PD22A_PWMH2 (1u << 22) /**< \brief Pwm signal: PWMH2 */\r
+#define PIO_PA7B_PWMH3 (1u << 7) /**< \brief Pwm signal: PWMH3 */\r
+#define PIO_PA14B_PWMH3 (1u << 14) /**< \brief Pwm signal: PWMH3 */\r
+#define PIO_PA17C_PWMH3 (1u << 17) /**< \brief Pwm signal: PWMH3 */\r
+#define PIO_PB14B_PWMH3 (1u << 14) /**< \brief Pwm signal: PWMH3 */\r
+#define PIO_PC21B_PWMH3 (1u << 21) /**< \brief Pwm signal: PWMH3 */\r
+#define PIO_PD23A_PWMH3 (1u << 23) /**< \brief Pwm signal: PWMH3 */\r
+#define PIO_PA19B_PWML0 (1u << 19) /**< \brief Pwm signal: PWML0 */\r
+#define PIO_PB5B_PWML0 (1u << 5) /**< \brief Pwm signal: PWML0 */\r
+#define PIO_PC0B_PWML0 (1u << 0) /**< \brief Pwm signal: PWML0 */\r
+#define PIO_PC13B_PWML0 (1u << 13) /**< \brief Pwm signal: PWML0 */\r
+#define PIO_PD24A_PWML0 (1u << 24) /**< \brief Pwm signal: PWML0 */\r
+#define PIO_PA20B_PWML1 (1u << 20) /**< \brief Pwm signal: PWML1 */\r
+#define PIO_PB12A_PWML1 (1u << 12) /**< \brief Pwm signal: PWML1 */\r
+#define PIO_PC1B_PWML1 (1u << 1) /**< \brief Pwm signal: PWML1 */\r
+#define PIO_PC15B_PWML1 (1u << 15) /**< \brief Pwm signal: PWML1 */\r
+#define PIO_PD25A_PWML1 (1u << 25) /**< \brief Pwm signal: PWML1 */\r
+#define PIO_PA16C_PWML2 (1u << 16) /**< \brief Pwm signal: PWML2 */\r
+#define PIO_PA30A_PWML2 (1u << 30) /**< \brief Pwm signal: PWML2 */\r
+#define PIO_PB13A_PWML2 (1u << 13) /**< \brief Pwm signal: PWML2 */\r
+#define PIO_PC2B_PWML2 (1u << 2) /**< \brief Pwm signal: PWML2 */\r
+#define PIO_PD26A_PWML2 (1u << 26) /**< \brief Pwm signal: PWML2 */\r
+#define PIO_PA15C_PWML3 (1u << 15) /**< \brief Pwm signal: PWML3 */\r
+#define PIO_PC3B_PWML3 (1u << 3) /**< \brief Pwm signal: PWML3 */\r
+#define PIO_PC22B_PWML3 (1u << 22) /**< \brief Pwm signal: PWML3 */\r
+#define PIO_PD27A_PWML3 (1u << 27) /**< \brief Pwm signal: PWML3 */\r
+/* ========== Pio definition for SPI peripheral ========== */\r
+#define PIO_PA12A_MISO (1u << 12) /**< \brief Spi signal: MISO */\r
+#define PIO_PA13A_MOSI (1u << 13) /**< \brief Spi signal: MOSI */\r
+#define PIO_PA11A_NPCS0 (1u << 11) /**< \brief Spi signal: NPCS0 */\r
+#define PIO_PA9B_NPCS1 (1u << 9) /**< \brief Spi signal: NPCS1 */\r
+#define PIO_PA31A_NPCS1 (1u << 31) /**< \brief Spi signal: NPCS1 */\r
+#define PIO_PB14A_NPCS1 (1u << 14) /**< \brief Spi signal: NPCS1 */\r
+#define PIO_PC4B_NPCS1 (1u << 4) /**< \brief Spi signal: NPCS1 */\r
+#define PIO_PA10B_NPCS2 (1u << 10) /**< \brief Spi signal: NPCS2 */\r
+#define PIO_PA30B_NPCS2 (1u << 30) /**< \brief Spi signal: NPCS2 */\r
+#define PIO_PB2B_NPCS2 (1u << 2) /**< \brief Spi signal: NPCS2 */\r
+#define PIO_PA3B_NPCS3 (1u << 3) /**< \brief Spi signal: NPCS3 */\r
+#define PIO_PA5B_NPCS3 (1u << 5) /**< \brief Spi signal: NPCS3 */\r
+#define PIO_PA22B_NPCS3 (1u << 22) /**< \brief Spi signal: NPCS3 */\r
+#define PIO_PA14A_SPCK (1u << 14) /**< \brief Spi signal: SPCK */\r
+/* ========== Pio definition for TC0 peripheral ========== */\r
+#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */\r
+#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */\r
+#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */\r
+#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */\r
+#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */\r
+#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */\r
+#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */\r
+#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */\r
+#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */\r
+/* ========== Pio definition for TC1 peripheral ========== */\r
+#define PIO_PC25B_TCLK3 (1u << 25) /**< \brief Tc1 signal: TCLK3 */\r
+#define PIO_PC28B_TCLK4 (1u << 28) /**< \brief Tc1 signal: TCLK4 */\r
+#define PIO_PC31B_TCLK5 (1u << 31) /**< \brief Tc1 signal: TCLK5 */\r
+#define PIO_PC23B_TIOA3 (1u << 23) /**< \brief Tc1 signal: TIOA3 */\r
+#define PIO_PC26B_TIOA4 (1u << 26) /**< \brief Tc1 signal: TIOA4 */\r
+#define PIO_PC29B_TIOA5 (1u << 29) /**< \brief Tc1 signal: TIOA5 */\r
+#define PIO_PC24B_TIOB3 (1u << 24) /**< \brief Tc1 signal: TIOB3 */\r
+#define PIO_PC27B_TIOB4 (1u << 27) /**< \brief Tc1 signal: TIOB4 */\r
+#define PIO_PC30B_TIOB5 (1u << 30) /**< \brief Tc1 signal: TIOB5 */\r
+/* ========== Pio definition for TC2 peripheral ========== */\r
+#define PIO_PC7B_TCLK6 (1u << 7) /**< \brief Tc2 signal: TCLK6 */\r
+#define PIO_PC10B_TCLK7 (1u << 10) /**< \brief Tc2 signal: TCLK7 */\r
+#define PIO_PC14B_TCLK8 (1u << 14) /**< \brief Tc2 signal: TCLK8 */\r
+#define PIO_PC5B_TIOA6 (1u << 5) /**< \brief Tc2 signal: TIOA6 */\r
+#define PIO_PC8B_TIOA7 (1u << 8) /**< \brief Tc2 signal: TIOA7 */\r
+#define PIO_PC11B_TIOA8 (1u << 11) /**< \brief Tc2 signal: TIOA8 */\r
+#define PIO_PC6B_TIOB6 (1u << 6) /**< \brief Tc2 signal: TIOB6 */\r
+#define PIO_PC9B_TIOB7 (1u << 9) /**< \brief Tc2 signal: TIOB7 */\r
+#define PIO_PC12B_TIOB8 (1u << 12) /**< \brief Tc2 signal: TIOB8 */\r
+/* ========== Pio definition for TWI0 peripheral ========== */\r
+#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twi0 signal: TWCK0 */\r
+#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twi0 signal: TWD0 */\r
+/* ========== Pio definition for TWI1 peripheral ========== */\r
+#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twi1 signal: TWCK1 */\r
+#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twi1 signal: TWD1 */\r
+/* ========== Pio definition for UART0 peripheral ========== */\r
+#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */\r
+#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */\r
+/* ========== Pio definition for UART1 peripheral ========== */\r
+#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */\r
+#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */\r
+/* ========== Pio definition for USART0 peripheral ========== */\r
+#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */\r
+#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */\r
+#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */\r
+#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */\r
+#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */\r
+/* ========== Pio definition for USART1 peripheral ========== */\r
+#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */\r
+#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */\r
+#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */\r
+#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */\r
+#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */\r
+#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */\r
+#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */\r
+#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */\r
+#define PIO_PA22A_TXD1 (1u << 22) /**< \brief Usart1 signal: TXD1 */\r
+/* ========== Pio indexes ========== */\r
+#define PIO_PA0_IDX 0\r
+#define PIO_PA1_IDX 1\r
+#define PIO_PA2_IDX 2\r
+#define PIO_PA3_IDX 3\r
+#define PIO_PA4_IDX 4\r
+#define PIO_PA5_IDX 5\r
+#define PIO_PA6_IDX 6\r
+#define PIO_PA7_IDX 7\r
+#define PIO_PA8_IDX 8\r
+#define PIO_PA9_IDX 9\r
+#define PIO_PA10_IDX 10\r
+#define PIO_PA11_IDX 11\r
+#define PIO_PA12_IDX 12\r
+#define PIO_PA13_IDX 13\r
+#define PIO_PA14_IDX 14\r
+#define PIO_PA15_IDX 15\r
+#define PIO_PA16_IDX 16\r
+#define PIO_PA17_IDX 17\r
+#define PIO_PA18_IDX 18\r
+#define PIO_PA19_IDX 19\r
+#define PIO_PA20_IDX 20\r
+#define PIO_PA21_IDX 21\r
+#define PIO_PA22_IDX 22\r
+#define PIO_PA23_IDX 23\r
+#define PIO_PA24_IDX 24\r
+#define PIO_PA25_IDX 25\r
+#define PIO_PA26_IDX 26\r
+#define PIO_PA27_IDX 27\r
+#define PIO_PA28_IDX 28\r
+#define PIO_PA29_IDX 29\r
+#define PIO_PA30_IDX 30\r
+#define PIO_PA31_IDX 31\r
+#define PIO_PB0_IDX 32\r
+#define PIO_PB1_IDX 33\r
+#define PIO_PB2_IDX 34\r
+#define PIO_PB3_IDX 35\r
+#define PIO_PB4_IDX 36\r
+#define PIO_PB5_IDX 37\r
+#define PIO_PB6_IDX 38\r
+#define PIO_PB7_IDX 39\r
+#define PIO_PB8_IDX 40\r
+#define PIO_PB9_IDX 41\r
+#define PIO_PB10_IDX 42\r
+#define PIO_PB11_IDX 43\r
+#define PIO_PB12_IDX 44\r
+#define PIO_PB13_IDX 45\r
+#define PIO_PB14_IDX 46\r
+#define PIO_PC0_IDX 64\r
+#define PIO_PC1_IDX 65\r
+#define PIO_PC2_IDX 66\r
+#define PIO_PC3_IDX 67\r
+#define PIO_PC4_IDX 68\r
+#define PIO_PC5_IDX 69\r
+#define PIO_PC6_IDX 70\r
+#define PIO_PC7_IDX 71\r
+#define PIO_PC8_IDX 72\r
+#define PIO_PC9_IDX 73\r
+#define PIO_PC10_IDX 74\r
+#define PIO_PC11_IDX 75\r
+#define PIO_PC12_IDX 76\r
+#define PIO_PC13_IDX 77\r
+#define PIO_PC14_IDX 78\r
+#define PIO_PC15_IDX 79\r
+#define PIO_PC16_IDX 80\r
+#define PIO_PC17_IDX 81\r
+#define PIO_PC18_IDX 82\r
+#define PIO_PC19_IDX 83\r
+#define PIO_PC20_IDX 84\r
+#define PIO_PC21_IDX 85\r
+#define PIO_PC22_IDX 86\r
+#define PIO_PC23_IDX 87\r
+#define PIO_PC24_IDX 88\r
+#define PIO_PC25_IDX 89\r
+#define PIO_PC26_IDX 90\r
+#define PIO_PC27_IDX 91\r
+#define PIO_PC28_IDX 92\r
+#define PIO_PC29_IDX 93\r
+#define PIO_PC30_IDX 94\r
+#define PIO_PC31_IDX 95\r
+#define PIO_PD0_IDX 96\r
+#define PIO_PD1_IDX 97\r
+#define PIO_PD2_IDX 98\r
+#define PIO_PD3_IDX 99\r
+#define PIO_PD4_IDX 100\r
+#define PIO_PD5_IDX 101\r
+#define PIO_PD6_IDX 102\r
+#define PIO_PD7_IDX 103\r
+#define PIO_PD8_IDX 104\r
+#define PIO_PD9_IDX 105\r
+#define PIO_PD10_IDX 106\r
+#define PIO_PD11_IDX 107\r
+#define PIO_PD12_IDX 108\r
+#define PIO_PD13_IDX 109\r
+#define PIO_PD14_IDX 110\r
+#define PIO_PD15_IDX 111\r
+#define PIO_PD16_IDX 112\r
+#define PIO_PD17_IDX 113\r
+#define PIO_PD18_IDX 114\r
+#define PIO_PD19_IDX 115\r
+#define PIO_PD20_IDX 116\r
+#define PIO_PD21_IDX 117\r
+#define PIO_PD22_IDX 118\r
+#define PIO_PD23_IDX 119\r
+#define PIO_PD24_IDX 120\r
+#define PIO_PD25_IDX 121\r
+#define PIO_PD26_IDX 122\r
+#define PIO_PD27_IDX 123\r
+#define PIO_PD28_IDX 124\r
+#define PIO_PD29_IDX 125\r
+#define PIO_PD30_IDX 126\r
+#define PIO_PD31_IDX 127\r
+#define PIO_PE0_IDX 128\r
+#define PIO_PE1_IDX 129\r
+#define PIO_PE2_IDX 130\r
+#define PIO_PE3_IDX 131\r
+#define PIO_PE4_IDX 132\r
+#define PIO_PE5_IDX 133\r
+\r
+#endif /* _SAM4E16E_PIO_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4E8C_PIO_\r
+#define _SAM4E8C_PIO_\r
+\r
+#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */\r
+#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */\r
+#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */\r
+#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */\r
+#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */\r
+#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */\r
+#define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */\r
+#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */\r
+#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */\r
+#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */\r
+#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */\r
+#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */\r
+#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */\r
+#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */\r
+#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */\r
+#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */\r
+#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */\r
+#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */\r
+#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */\r
+#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */\r
+#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */\r
+#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */\r
+#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */\r
+#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */\r
+#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */\r
+#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */\r
+#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */\r
+#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */\r
+#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */\r
+#define PIO_PA29 (1u << 29) /**< \brief Pin Controlled by PA29 */\r
+#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */\r
+#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */\r
+#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */\r
+#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */\r
+#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */\r
+#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */\r
+#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */\r
+#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */\r
+#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */\r
+#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */\r
+#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */\r
+#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */\r
+#define PIO_PB10 (1u << 10) /**< \brief Pin Controlled by PB10 */\r
+#define PIO_PB11 (1u << 11) /**< \brief Pin Controlled by PB11 */\r
+#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */\r
+#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */\r
+#define PIO_PB14 (1u << 14) /**< \brief Pin Controlled by PB14 */\r
+#define PIO_PC0 (1u << 0) /**< \brief Pin Controlled by PC0 */\r
+#define PIO_PC1 (1u << 1) /**< \brief Pin Controlled by PC1 */\r
+#define PIO_PC2 (1u << 2) /**< \brief Pin Controlled by PC2 */\r
+#define PIO_PC3 (1u << 3) /**< \brief Pin Controlled by PC3 */\r
+#define PIO_PC4 (1u << 4) /**< \brief Pin Controlled by PC4 */\r
+#define PIO_PC5 (1u << 5) /**< \brief Pin Controlled by PC5 */\r
+#define PIO_PC6 (1u << 6) /**< \brief Pin Controlled by PC6 */\r
+#define PIO_PC7 (1u << 7) /**< \brief Pin Controlled by PC7 */\r
+#define PIO_PC8 (1u << 8) /**< \brief Pin Controlled by PC8 */\r
+#define PIO_PC9 (1u << 9) /**< \brief Pin Controlled by PC9 */\r
+#define PIO_PC10 (1u << 10) /**< \brief Pin Controlled by PC10 */\r
+#define PIO_PC11 (1u << 11) /**< \brief Pin Controlled by PC11 */\r
+#define PIO_PC12 (1u << 12) /**< \brief Pin Controlled by PC12 */\r
+#define PIO_PC13 (1u << 13) /**< \brief Pin Controlled by PC13 */\r
+#define PIO_PC14 (1u << 14) /**< \brief Pin Controlled by PC14 */\r
+#define PIO_PC15 (1u << 15) /**< \brief Pin Controlled by PC15 */\r
+#define PIO_PC16 (1u << 16) /**< \brief Pin Controlled by PC16 */\r
+#define PIO_PC17 (1u << 17) /**< \brief Pin Controlled by PC17 */\r
+#define PIO_PC18 (1u << 18) /**< \brief Pin Controlled by PC18 */\r
+#define PIO_PC19 (1u << 19) /**< \brief Pin Controlled by PC19 */\r
+#define PIO_PC20 (1u << 20) /**< \brief Pin Controlled by PC20 */\r
+#define PIO_PC21 (1u << 21) /**< \brief Pin Controlled by PC21 */\r
+#define PIO_PC22 (1u << 22) /**< \brief Pin Controlled by PC22 */\r
+#define PIO_PC23 (1u << 23) /**< \brief Pin Controlled by PC23 */\r
+#define PIO_PC24 (1u << 24) /**< \brief Pin Controlled by PC24 */\r
+#define PIO_PC25 (1u << 25) /**< \brief Pin Controlled by PC25 */\r
+#define PIO_PC26 (1u << 26) /**< \brief Pin Controlled by PC26 */\r
+#define PIO_PC27 (1u << 27) /**< \brief Pin Controlled by PC27 */\r
+#define PIO_PC28 (1u << 28) /**< \brief Pin Controlled by PC28 */\r
+#define PIO_PC29 (1u << 29) /**< \brief Pin Controlled by PC29 */\r
+#define PIO_PC30 (1u << 30) /**< \brief Pin Controlled by PC30 */\r
+#define PIO_PC31 (1u << 31) /**< \brief Pin Controlled by PC31 */\r
+#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */\r
+#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */\r
+#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */\r
+#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */\r
+#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */\r
+#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */\r
+#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */\r
+#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */\r
+#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */\r
+#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */\r
+#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */\r
+#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */\r
+#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */\r
+#define PIO_PD13 (1u << 13) /**< \brief Pin Controlled by PD13 */\r
+#define PIO_PD14 (1u << 14) /**< \brief Pin Controlled by PD14 */\r
+#define PIO_PD15 (1u << 15) /**< \brief Pin Controlled by PD15 */\r
+#define PIO_PD16 (1u << 16) /**< \brief Pin Controlled by PD16 */\r
+#define PIO_PD17 (1u << 17) /**< \brief Pin Controlled by PD17 */\r
+#define PIO_PD18 (1u << 18) /**< \brief Pin Controlled by PD18 */\r
+#define PIO_PD19 (1u << 19) /**< \brief Pin Controlled by PD19 */\r
+#define PIO_PD20 (1u << 20) /**< \brief Pin Controlled by PD20 */\r
+#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */\r
+#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */\r
+#define PIO_PD23 (1u << 23) /**< \brief Pin Controlled by PD23 */\r
+#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */\r
+#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */\r
+#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */\r
+#define PIO_PD27 (1u << 27) /**< \brief Pin Controlled by PD27 */\r
+#define PIO_PD28 (1u << 28) /**< \brief Pin Controlled by PD28 */\r
+#define PIO_PD29 (1u << 29) /**< \brief Pin Controlled by PD29 */\r
+#define PIO_PD30 (1u << 30) /**< \brief Pin Controlled by PD30 */\r
+#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */\r
+#define PIO_PE0 (1u << 0) /**< \brief Pin Controlled by PE0 */\r
+#define PIO_PE1 (1u << 1) /**< \brief Pin Controlled by PE1 */\r
+#define PIO_PE2 (1u << 2) /**< \brief Pin Controlled by PE2 */\r
+#define PIO_PE3 (1u << 3) /**< \brief Pin Controlled by PE3 */\r
+#define PIO_PE4 (1u << 4) /**< \brief Pin Controlled by PE4 */\r
+#define PIO_PE5 (1u << 5) /**< \brief Pin Controlled by PE5 */\r
+/* ========== Pio definition for AFEC0 peripheral ========== */\r
+#define PIO_PA17X1_AFE0_AD0 (1u << 17) /**< \brief Afec0 signal: AFE0_AD0 */\r
+#define PIO_PA18X1_AFE0_AD1 (1u << 18) /**< \brief Afec0 signal: AFE0_AD1 */\r
+#define PIO_PC30X1_AFE0_AD10 (1u << 30) /**< \brief Afec0 signal: AFE0_AD10 */\r
+#define PIO_PC31X1_AFE0_AD11 (1u << 31) /**< \brief Afec0 signal: AFE0_AD11 */\r
+#define PIO_PC26X1_AFE0_AD12 (1u << 26) /**< \brief Afec0 signal: AFE0_AD12 */\r
+#define PIO_PC27X1_AFE0_AD13 (1u << 27) /**< \brief Afec0 signal: AFE0_AD13 */\r
+#define PIO_PC0X1_AFE0_AD14 (1u << 0) /**< \brief Afec0 signal: AFE0_AD14 */\r
+#define PIO_PA19X1_AFE0_AD2 (1u << 19) /**< \brief Afec0 signal: AFE0_AD2/WKUP9 */\r
+#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD2/WKUP9 */\r
+#define PIO_PA20X1_AFE0_AD3 (1u << 20) /**< \brief Afec0 signal: AFE0_AD3/WKUP10 */\r
+#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD3/WKUP10 */\r
+#define PIO_PB0X1_AFE0_AD4 (1u << 0) /**< \brief Afec0 signal: AFE0_AD4/RTCOUT0 */\r
+#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD4/RTCOUT0 */\r
+#define PIO_PB1X1_AFE0_AD5 (1u << 1) /**< \brief Afec0 signal: AFE0_AD5/RTCOUT1 */\r
+#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec0 signal: AFE0_AD5/RTCOUT1 */\r
+#define PIO_PC13X1_AFE0_AD6 (1u << 13) /**< \brief Afec0 signal: AFE0_AD6 */\r
+#define PIO_PC15X1_AFE0_AD7 (1u << 15) /**< \brief Afec0 signal: AFE0_AD7 */\r
+#define PIO_PC12X1_AFE0_AD8 (1u << 12) /**< \brief Afec0 signal: AFE0_AD8 */\r
+#define PIO_PC29X1_AFE0_AD9 (1u << 29) /**< \brief Afec0 signal: AFE0_AD9 */\r
+#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */\r
+/* ========== Pio definition for AFEC1 peripheral ========== */\r
+#define PIO_PB2X1_AFE1_AD0 (1u << 2) /**< \brief Afec1 signal: AFE1_AD0/WKUP12 */\r
+#define PIO_PB2X1_WKUP12 (1u << 2) /**< \brief Afec1 signal: AFE1_AD0/WKUP12 */\r
+#define PIO_PB3X1_AFE1_AD1 (1u << 3) /**< \brief Afec1 signal: AFE1_AD1 */\r
+#define PIO_PA21X1_AFE1_AD2 (1u << 21) /**< \brief Afec1 signal: AFE1_AD2 */\r
+#define PIO_PA22X1_AFE1_AD3 (1u << 22) /**< \brief Afec1 signal: AFE1_AD3 */\r
+#define PIO_PC1X1_AFE1_AD4 (1u << 1) /**< \brief Afec1 signal: AFE1_AD4 */\r
+#define PIO_PC2X1_AFE1_AD5 (1u << 2) /**< \brief Afec1 signal: AFE1_AD5 */\r
+#define PIO_PC3X1_AFE1_AD6 (1u << 3) /**< \brief Afec1 signal: AFE1_AD6 */\r
+#define PIO_PC4X1_AFE1_AD7 (1u << 4) /**< \brief Afec1 signal: AFE1_AD7 */\r
+/* ========== Pio definition for CAN0 peripheral ========== */\r
+#define PIO_PB3A_CANRX0 (1u << 3) /**< \brief Can0 signal: CANRX0 */\r
+#define PIO_PB2A_CANTX0 (1u << 2) /**< \brief Can0 signal: CANTX0 */\r
+/* ========== Pio definition for CAN1 peripheral ========== */\r
+#define PIO_PC12C_CANRX1 (1u << 12) /**< \brief Can1 signal: CANRX1 */\r
+#define PIO_PC15C_CANTX1 (1u << 15) /**< \brief Can1 signal: CANTX1 */\r
+/* ========== Pio definition for DACC peripheral ========== */\r
+#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */\r
+#define PIO_PB14X1_DAC1 (1u << 14) /**< \brief Dacc signal: DAC1 */\r
+#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */\r
+/* ========== Pio definition for GMAC peripheral ========== */\r
+#define PIO_PD13A_GCOL (1u << 13) /**< \brief Gmac signal: GCOL */\r
+#define PIO_PD10A_GCRS (1u << 10) /**< \brief Gmac signal: GCRS */\r
+#define PIO_PD4A_GCRSDV (1u << 4) /**< \brief Gmac signal: GCRSDV/GRXDV */\r
+#define PIO_PD4A_GRXDV (1u << 4) /**< \brief Gmac signal: GCRSDV/GRXDV */\r
+#define PIO_PD8A_GMDC (1u << 8) /**< \brief Gmac signal: GMDC */\r
+#define PIO_PD9A_GMDIO (1u << 9) /**< \brief Gmac signal: GMDIO */\r
+#define PIO_PD5A_GRX0 (1u << 5) /**< \brief Gmac signal: GRX0 */\r
+#define PIO_PD6A_GRX0 (1u << 6) /**< \brief Gmac signal: GRX0 */\r
+#define PIO_PD11A_GRX2 (1u << 11) /**< \brief Gmac signal: GRX2 */\r
+#define PIO_PD12A_GRX3 (1u << 12) /**< \brief Gmac signal: GRX3 */\r
+#define PIO_PD14A_GRXCK (1u << 14) /**< \brief Gmac signal: GRXCK */\r
+#define PIO_PD7A_GRXER (1u << 7) /**< \brief Gmac signal: GRXER */\r
+#define PIO_PD2A_GTX0 (1u << 2) /**< \brief Gmac signal: GTX0 */\r
+#define PIO_PD3A_GTX1 (1u << 3) /**< \brief Gmac signal: GTX1 */\r
+#define PIO_PD15A_GTX2 (1u << 15) /**< \brief Gmac signal: GTX2 */\r
+#define PIO_PD16A_GTX3 (1u << 16) /**< \brief Gmac signal: GTX3 */\r
+#define PIO_PD0A_GTXCK (1u << 0) /**< \brief Gmac signal: GTXCK/GREFCK */\r
+#define PIO_PD0A_GREFCK (1u << 0) /**< \brief Gmac signal: GTXCK/GREFCK */\r
+#define PIO_PD1A_GTXEN (1u << 1) /**< \brief Gmac signal: GTXEN */\r
+#define PIO_PD17A_GTXER (1u << 17) /**< \brief Gmac signal: GTXER */\r
+/* ========== Pio definition for HSMCI peripheral ========== */\r
+#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */\r
+#define PIO_PA29C_MCCK (1u << 29) /**< \brief Hsmci signal: MCCK */\r
+#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */\r
+#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */\r
+#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */\r
+#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */\r
+/* ========== Pio definition for PIOA peripheral ========== */\r
+#define PIO_PA24X1_PIODC0 (1u << 24) /**< \brief Pioa signal: PIODC0 */\r
+#define PIO_PA25X1_PIODC1 (1u << 25) /**< \brief Pioa signal: PIODC1 */\r
+#define PIO_PA26X1_PIODC2 (1u << 26) /**< \brief Pioa signal: PIODC2 */\r
+#define PIO_PA27X1_PIODC3 (1u << 27) /**< \brief Pioa signal: PIODC3 */\r
+#define PIO_PA28X1_PIODC4 (1u << 28) /**< \brief Pioa signal: PIODC4 */\r
+#define PIO_PA29X1_PIODC5 (1u << 29) /**< \brief Pioa signal: PIODC5 */\r
+#define PIO_PA31X1_PIODC7 (1u << 31) /**< \brief Pioa signal: PIODC7 */\r
+#define PIO_PA23X1_PIODCCLK (1u << 23) /**< \brief Pioa signal: PIODCCLK */\r
+#define PIO_PA30X1_WKUP11 (1u << 30) /**< \brief Pioa signal: WKUP11/PIODC6 */\r
+#define PIO_PA30X1_PIODC6 (1u << 30) /**< \brief Pioa signal: WKUP11/PIODC6 */\r
+#define PIO_PA15X1_WKUP14 (1u << 15) /**< \brief Pioa signal: WKUP14/PIODCEN1 */\r
+#define PIO_PA15X1_PIODCEN1 (1u << 15) /**< \brief Pioa signal: WKUP14/PIODCEN1 */\r
+#define PIO_PA16X1_WKUP15 (1u << 16) /**< \brief Pioa signal: WKUP15/PIODCEN2 */\r
+#define PIO_PA16X1_PIODCEN2 (1u << 16) /**< \brief Pioa signal: WKUP15/PIODCEN2 */\r
+/* ========== Pio definition for PMC peripheral ========== */\r
+#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */\r
+#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */\r
+#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */\r
+#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */\r
+#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */\r
+#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */\r
+#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */\r
+/* ========== Pio definition for PWM peripheral ========== */\r
+#define PIO_PA9C_PWMFI0 (1u << 9) /**< \brief Pwm signal: PWMFI0 */\r
+#define PIO_PA0A_PWMH0 (1u << 0) /**< \brief Pwm signal: PWMH0 */\r
+#define PIO_PA11B_PWMH0 (1u << 11) /**< \brief Pwm signal: PWMH0 */\r
+#define PIO_PA23B_PWMH0 (1u << 23) /**< \brief Pwm signal: PWMH0 */\r
+#define PIO_PB0A_PWMH0 (1u << 0) /**< \brief Pwm signal: PWMH0 */\r
+#define PIO_PC18B_PWMH0 (1u << 18) /**< \brief Pwm signal: PWMH0 */\r
+#define PIO_PD20A_PWMH0 (1u << 20) /**< \brief Pwm signal: PWMH0 */\r
+#define PIO_PA1A_PWMH1 (1u << 1) /**< \brief Pwm signal: PWMH1 */\r
+#define PIO_PA12B_PWMH1 (1u << 12) /**< \brief Pwm signal: PWMH1 */\r
+#define PIO_PA24B_PWMH1 (1u << 24) /**< \brief Pwm signal: PWMH1 */\r
+#define PIO_PB1A_PWMH1 (1u << 1) /**< \brief Pwm signal: PWMH1 */\r
+#define PIO_PC19B_PWMH1 (1u << 19) /**< \brief Pwm signal: PWMH1 */\r
+#define PIO_PD21A_PWMH1 (1u << 21) /**< \brief Pwm signal: PWMH1 */\r
+#define PIO_PA2A_PWMH2 (1u << 2) /**< \brief Pwm signal: PWMH2 */\r
+#define PIO_PA13B_PWMH2 (1u << 13) /**< \brief Pwm signal: PWMH2 */\r
+#define PIO_PA25B_PWMH2 (1u << 25) /**< \brief Pwm signal: PWMH2 */\r
+#define PIO_PB4B_PWMH2 (1u << 4) /**< \brief Pwm signal: PWMH2 */\r
+#define PIO_PC20B_PWMH2 (1u << 20) /**< \brief Pwm signal: PWMH2 */\r
+#define PIO_PD22A_PWMH2 (1u << 22) /**< \brief Pwm signal: PWMH2 */\r
+#define PIO_PA7B_PWMH3 (1u << 7) /**< \brief Pwm signal: PWMH3 */\r
+#define PIO_PA14B_PWMH3 (1u << 14) /**< \brief Pwm signal: PWMH3 */\r
+#define PIO_PA17C_PWMH3 (1u << 17) /**< \brief Pwm signal: PWMH3 */\r
+#define PIO_PB14B_PWMH3 (1u << 14) /**< \brief Pwm signal: PWMH3 */\r
+#define PIO_PC21B_PWMH3 (1u << 21) /**< \brief Pwm signal: PWMH3 */\r
+#define PIO_PD23A_PWMH3 (1u << 23) /**< \brief Pwm signal: PWMH3 */\r
+#define PIO_PA19B_PWML0 (1u << 19) /**< \brief Pwm signal: PWML0 */\r
+#define PIO_PB5B_PWML0 (1u << 5) /**< \brief Pwm signal: PWML0 */\r
+#define PIO_PC0B_PWML0 (1u << 0) /**< \brief Pwm signal: PWML0 */\r
+#define PIO_PC13B_PWML0 (1u << 13) /**< \brief Pwm signal: PWML0 */\r
+#define PIO_PD24A_PWML0 (1u << 24) /**< \brief Pwm signal: PWML0 */\r
+#define PIO_PA20B_PWML1 (1u << 20) /**< \brief Pwm signal: PWML1 */\r
+#define PIO_PB12A_PWML1 (1u << 12) /**< \brief Pwm signal: PWML1 */\r
+#define PIO_PC1B_PWML1 (1u << 1) /**< \brief Pwm signal: PWML1 */\r
+#define PIO_PC15B_PWML1 (1u << 15) /**< \brief Pwm signal: PWML1 */\r
+#define PIO_PD25A_PWML1 (1u << 25) /**< \brief Pwm signal: PWML1 */\r
+#define PIO_PA16C_PWML2 (1u << 16) /**< \brief Pwm signal: PWML2 */\r
+#define PIO_PA30A_PWML2 (1u << 30) /**< \brief Pwm signal: PWML2 */\r
+#define PIO_PB13A_PWML2 (1u << 13) /**< \brief Pwm signal: PWML2 */\r
+#define PIO_PC2B_PWML2 (1u << 2) /**< \brief Pwm signal: PWML2 */\r
+#define PIO_PD26A_PWML2 (1u << 26) /**< \brief Pwm signal: PWML2 */\r
+#define PIO_PA15C_PWML3 (1u << 15) /**< \brief Pwm signal: PWML3 */\r
+#define PIO_PC3B_PWML3 (1u << 3) /**< \brief Pwm signal: PWML3 */\r
+#define PIO_PC22B_PWML3 (1u << 22) /**< \brief Pwm signal: PWML3 */\r
+#define PIO_PD27A_PWML3 (1u << 27) /**< \brief Pwm signal: PWML3 */\r
+/* ========== Pio definition for SPI peripheral ========== */\r
+#define PIO_PA12A_MISO (1u << 12) /**< \brief Spi signal: MISO */\r
+#define PIO_PA13A_MOSI (1u << 13) /**< \brief Spi signal: MOSI */\r
+#define PIO_PA11A_NPCS0 (1u << 11) /**< \brief Spi signal: NPCS0 */\r
+#define PIO_PA9B_NPCS1 (1u << 9) /**< \brief Spi signal: NPCS1 */\r
+#define PIO_PA31A_NPCS1 (1u << 31) /**< \brief Spi signal: NPCS1 */\r
+#define PIO_PB14A_NPCS1 (1u << 14) /**< \brief Spi signal: NPCS1 */\r
+#define PIO_PC4B_NPCS1 (1u << 4) /**< \brief Spi signal: NPCS1 */\r
+#define PIO_PA10B_NPCS2 (1u << 10) /**< \brief Spi signal: NPCS2 */\r
+#define PIO_PA30B_NPCS2 (1u << 30) /**< \brief Spi signal: NPCS2 */\r
+#define PIO_PB2B_NPCS2 (1u << 2) /**< \brief Spi signal: NPCS2 */\r
+#define PIO_PA3B_NPCS3 (1u << 3) /**< \brief Spi signal: NPCS3 */\r
+#define PIO_PA5B_NPCS3 (1u << 5) /**< \brief Spi signal: NPCS3 */\r
+#define PIO_PA22B_NPCS3 (1u << 22) /**< \brief Spi signal: NPCS3 */\r
+#define PIO_PA14A_SPCK (1u << 14) /**< \brief Spi signal: SPCK */\r
+/* ========== Pio definition for TC0 peripheral ========== */\r
+#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */\r
+#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */\r
+#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */\r
+#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */\r
+#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */\r
+#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */\r
+#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */\r
+#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */\r
+#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */\r
+/* ========== Pio definition for TC1 peripheral ========== */\r
+#define PIO_PC25B_TCLK3 (1u << 25) /**< \brief Tc1 signal: TCLK3 */\r
+#define PIO_PC28B_TCLK4 (1u << 28) /**< \brief Tc1 signal: TCLK4 */\r
+#define PIO_PC31B_TCLK5 (1u << 31) /**< \brief Tc1 signal: TCLK5 */\r
+#define PIO_PC23B_TIOA3 (1u << 23) /**< \brief Tc1 signal: TIOA3 */\r
+#define PIO_PC26B_TIOA4 (1u << 26) /**< \brief Tc1 signal: TIOA4 */\r
+#define PIO_PC29B_TIOA5 (1u << 29) /**< \brief Tc1 signal: TIOA5 */\r
+#define PIO_PC24B_TIOB3 (1u << 24) /**< \brief Tc1 signal: TIOB3 */\r
+#define PIO_PC27B_TIOB4 (1u << 27) /**< \brief Tc1 signal: TIOB4 */\r
+#define PIO_PC30B_TIOB5 (1u << 30) /**< \brief Tc1 signal: TIOB5 */\r
+/* ========== Pio definition for TC2 peripheral ========== */\r
+#define PIO_PC7B_TCLK6 (1u << 7) /**< \brief Tc2 signal: TCLK6 */\r
+#define PIO_PC10B_TCLK7 (1u << 10) /**< \brief Tc2 signal: TCLK7 */\r
+#define PIO_PC14B_TCLK8 (1u << 14) /**< \brief Tc2 signal: TCLK8 */\r
+#define PIO_PC5B_TIOA6 (1u << 5) /**< \brief Tc2 signal: TIOA6 */\r
+#define PIO_PC8B_TIOA7 (1u << 8) /**< \brief Tc2 signal: TIOA7 */\r
+#define PIO_PC11B_TIOA8 (1u << 11) /**< \brief Tc2 signal: TIOA8 */\r
+#define PIO_PC6B_TIOB6 (1u << 6) /**< \brief Tc2 signal: TIOB6 */\r
+#define PIO_PC9B_TIOB7 (1u << 9) /**< \brief Tc2 signal: TIOB7 */\r
+#define PIO_PC12B_TIOB8 (1u << 12) /**< \brief Tc2 signal: TIOB8 */\r
+/* ========== Pio definition for TWI0 peripheral ========== */\r
+#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twi0 signal: TWCK0 */\r
+#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twi0 signal: TWD0 */\r
+/* ========== Pio definition for TWI1 peripheral ========== */\r
+#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twi1 signal: TWCK1 */\r
+#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twi1 signal: TWD1 */\r
+/* ========== Pio definition for UART0 peripheral ========== */\r
+#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */\r
+#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */\r
+/* ========== Pio definition for UART1 peripheral ========== */\r
+#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */\r
+#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */\r
+/* ========== Pio definition for USART0 peripheral ========== */\r
+#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */\r
+#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */\r
+#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */\r
+#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */\r
+#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */\r
+/* ========== Pio definition for USART1 peripheral ========== */\r
+#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */\r
+#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */\r
+#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */\r
+#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */\r
+#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */\r
+#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */\r
+#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */\r
+#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */\r
+#define PIO_PA22A_TXD1 (1u << 22) /**< \brief Usart1 signal: TXD1 */\r
+/* ========== Pio indexes ========== */\r
+#define PIO_PA0_IDX 0\r
+#define PIO_PA1_IDX 1\r
+#define PIO_PA2_IDX 2\r
+#define PIO_PA3_IDX 3\r
+#define PIO_PA4_IDX 4\r
+#define PIO_PA5_IDX 5\r
+#define PIO_PA6_IDX 6\r
+#define PIO_PA7_IDX 7\r
+#define PIO_PA8_IDX 8\r
+#define PIO_PA9_IDX 9\r
+#define PIO_PA10_IDX 10\r
+#define PIO_PA11_IDX 11\r
+#define PIO_PA12_IDX 12\r
+#define PIO_PA13_IDX 13\r
+#define PIO_PA14_IDX 14\r
+#define PIO_PA15_IDX 15\r
+#define PIO_PA16_IDX 16\r
+#define PIO_PA17_IDX 17\r
+#define PIO_PA18_IDX 18\r
+#define PIO_PA19_IDX 19\r
+#define PIO_PA20_IDX 20\r
+#define PIO_PA21_IDX 21\r
+#define PIO_PA22_IDX 22\r
+#define PIO_PA23_IDX 23\r
+#define PIO_PA24_IDX 24\r
+#define PIO_PA25_IDX 25\r
+#define PIO_PA26_IDX 26\r
+#define PIO_PA27_IDX 27\r
+#define PIO_PA28_IDX 28\r
+#define PIO_PA29_IDX 29\r
+#define PIO_PA30_IDX 30\r
+#define PIO_PA31_IDX 31\r
+#define PIO_PB0_IDX 32\r
+#define PIO_PB1_IDX 33\r
+#define PIO_PB2_IDX 34\r
+#define PIO_PB3_IDX 35\r
+#define PIO_PB4_IDX 36\r
+#define PIO_PB5_IDX 37\r
+#define PIO_PB6_IDX 38\r
+#define PIO_PB7_IDX 39\r
+#define PIO_PB8_IDX 40\r
+#define PIO_PB9_IDX 41\r
+#define PIO_PB10_IDX 42\r
+#define PIO_PB11_IDX 43\r
+#define PIO_PB12_IDX 44\r
+#define PIO_PB13_IDX 45\r
+#define PIO_PB14_IDX 46\r
+#define PIO_PC0_IDX 64\r
+#define PIO_PC1_IDX 65\r
+#define PIO_PC2_IDX 66\r
+#define PIO_PC3_IDX 67\r
+#define PIO_PC4_IDX 68\r
+#define PIO_PC5_IDX 69\r
+#define PIO_PC6_IDX 70\r
+#define PIO_PC7_IDX 71\r
+#define PIO_PC8_IDX 72\r
+#define PIO_PC9_IDX 73\r
+#define PIO_PC10_IDX 74\r
+#define PIO_PC11_IDX 75\r
+#define PIO_PC12_IDX 76\r
+#define PIO_PC13_IDX 77\r
+#define PIO_PC14_IDX 78\r
+#define PIO_PC15_IDX 79\r
+#define PIO_PC16_IDX 80\r
+#define PIO_PC17_IDX 81\r
+#define PIO_PC18_IDX 82\r
+#define PIO_PC19_IDX 83\r
+#define PIO_PC20_IDX 84\r
+#define PIO_PC21_IDX 85\r
+#define PIO_PC22_IDX 86\r
+#define PIO_PC23_IDX 87\r
+#define PIO_PC24_IDX 88\r
+#define PIO_PC25_IDX 89\r
+#define PIO_PC26_IDX 90\r
+#define PIO_PC27_IDX 91\r
+#define PIO_PC28_IDX 92\r
+#define PIO_PC29_IDX 93\r
+#define PIO_PC30_IDX 94\r
+#define PIO_PC31_IDX 95\r
+#define PIO_PD0_IDX 96\r
+#define PIO_PD1_IDX 97\r
+#define PIO_PD2_IDX 98\r
+#define PIO_PD3_IDX 99\r
+#define PIO_PD4_IDX 100\r
+#define PIO_PD5_IDX 101\r
+#define PIO_PD6_IDX 102\r
+#define PIO_PD7_IDX 103\r
+#define PIO_PD8_IDX 104\r
+#define PIO_PD9_IDX 105\r
+#define PIO_PD10_IDX 106\r
+#define PIO_PD11_IDX 107\r
+#define PIO_PD12_IDX 108\r
+#define PIO_PD13_IDX 109\r
+#define PIO_PD14_IDX 110\r
+#define PIO_PD15_IDX 111\r
+#define PIO_PD16_IDX 112\r
+#define PIO_PD17_IDX 113\r
+#define PIO_PD18_IDX 114\r
+#define PIO_PD19_IDX 115\r
+#define PIO_PD20_IDX 116\r
+#define PIO_PD21_IDX 117\r
+#define PIO_PD22_IDX 118\r
+#define PIO_PD23_IDX 119\r
+#define PIO_PD24_IDX 120\r
+#define PIO_PD25_IDX 121\r
+#define PIO_PD26_IDX 122\r
+#define PIO_PD27_IDX 123\r
+#define PIO_PD28_IDX 124\r
+#define PIO_PD29_IDX 125\r
+#define PIO_PD30_IDX 126\r
+#define PIO_PD31_IDX 127\r
+#define PIO_PE0_IDX 128\r
+#define PIO_PE1_IDX 129\r
+#define PIO_PE2_IDX 130\r
+#define PIO_PE3_IDX 131\r
+#define PIO_PE4_IDX 132\r
+#define PIO_PE5_IDX 133\r
+\r
+#endif /* _SAM4E8C_PIO_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4E8E_PIO_\r
+#define _SAM4E8E_PIO_\r
+\r
+#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */\r
+#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */\r
+#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */\r
+#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */\r
+#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */\r
+#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */\r
+#define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */\r
+#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */\r
+#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */\r
+#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */\r
+#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */\r
+#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */\r
+#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */\r
+#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */\r
+#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */\r
+#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */\r
+#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */\r
+#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */\r
+#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */\r
+#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */\r
+#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */\r
+#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */\r
+#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */\r
+#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */\r
+#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */\r
+#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */\r
+#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */\r
+#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */\r
+#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */\r
+#define PIO_PA29 (1u << 29) /**< \brief Pin Controlled by PA29 */\r
+#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */\r
+#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */\r
+#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */\r
+#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */\r
+#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */\r
+#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */\r
+#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */\r
+#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */\r
+#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */\r
+#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */\r
+#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */\r
+#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */\r
+#define PIO_PB10 (1u << 10) /**< \brief Pin Controlled by PB10 */\r
+#define PIO_PB11 (1u << 11) /**< \brief Pin Controlled by PB11 */\r
+#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */\r
+#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */\r
+#define PIO_PB14 (1u << 14) /**< \brief Pin Controlled by PB14 */\r
+#define PIO_PC0 (1u << 0) /**< \brief Pin Controlled by PC0 */\r
+#define PIO_PC1 (1u << 1) /**< \brief Pin Controlled by PC1 */\r
+#define PIO_PC2 (1u << 2) /**< \brief Pin Controlled by PC2 */\r
+#define PIO_PC3 (1u << 3) /**< \brief Pin Controlled by PC3 */\r
+#define PIO_PC4 (1u << 4) /**< \brief Pin Controlled by PC4 */\r
+#define PIO_PC5 (1u << 5) /**< \brief Pin Controlled by PC5 */\r
+#define PIO_PC6 (1u << 6) /**< \brief Pin Controlled by PC6 */\r
+#define PIO_PC7 (1u << 7) /**< \brief Pin Controlled by PC7 */\r
+#define PIO_PC8 (1u << 8) /**< \brief Pin Controlled by PC8 */\r
+#define PIO_PC9 (1u << 9) /**< \brief Pin Controlled by PC9 */\r
+#define PIO_PC10 (1u << 10) /**< \brief Pin Controlled by PC10 */\r
+#define PIO_PC11 (1u << 11) /**< \brief Pin Controlled by PC11 */\r
+#define PIO_PC12 (1u << 12) /**< \brief Pin Controlled by PC12 */\r
+#define PIO_PC13 (1u << 13) /**< \brief Pin Controlled by PC13 */\r
+#define PIO_PC14 (1u << 14) /**< \brief Pin Controlled by PC14 */\r
+#define PIO_PC15 (1u << 15) /**< \brief Pin Controlled by PC15 */\r
+#define PIO_PC16 (1u << 16) /**< \brief Pin Controlled by PC16 */\r
+#define PIO_PC17 (1u << 17) /**< \brief Pin Controlled by PC17 */\r
+#define PIO_PC18 (1u << 18) /**< \brief Pin Controlled by PC18 */\r
+#define PIO_PC19 (1u << 19) /**< \brief Pin Controlled by PC19 */\r
+#define PIO_PC20 (1u << 20) /**< \brief Pin Controlled by PC20 */\r
+#define PIO_PC21 (1u << 21) /**< \brief Pin Controlled by PC21 */\r
+#define PIO_PC22 (1u << 22) /**< \brief Pin Controlled by PC22 */\r
+#define PIO_PC23 (1u << 23) /**< \brief Pin Controlled by PC23 */\r
+#define PIO_PC24 (1u << 24) /**< \brief Pin Controlled by PC24 */\r
+#define PIO_PC25 (1u << 25) /**< \brief Pin Controlled by PC25 */\r
+#define PIO_PC26 (1u << 26) /**< \brief Pin Controlled by PC26 */\r
+#define PIO_PC27 (1u << 27) /**< \brief Pin Controlled by PC27 */\r
+#define PIO_PC28 (1u << 28) /**< \brief Pin Controlled by PC28 */\r
+#define PIO_PC29 (1u << 29) /**< \brief Pin Controlled by PC29 */\r
+#define PIO_PC30 (1u << 30) /**< \brief Pin Controlled by PC30 */\r
+#define PIO_PC31 (1u << 31) /**< \brief Pin Controlled by PC31 */\r
+#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */\r
+#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */\r
+#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */\r
+#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */\r
+#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */\r
+#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */\r
+#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */\r
+#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */\r
+#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */\r
+#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */\r
+#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */\r
+#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */\r
+#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */\r
+#define PIO_PD13 (1u << 13) /**< \brief Pin Controlled by PD13 */\r
+#define PIO_PD14 (1u << 14) /**< \brief Pin Controlled by PD14 */\r
+#define PIO_PD15 (1u << 15) /**< \brief Pin Controlled by PD15 */\r
+#define PIO_PD16 (1u << 16) /**< \brief Pin Controlled by PD16 */\r
+#define PIO_PD17 (1u << 17) /**< \brief Pin Controlled by PD17 */\r
+#define PIO_PD18 (1u << 18) /**< \brief Pin Controlled by PD18 */\r
+#define PIO_PD19 (1u << 19) /**< \brief Pin Controlled by PD19 */\r
+#define PIO_PD20 (1u << 20) /**< \brief Pin Controlled by PD20 */\r
+#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */\r
+#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */\r
+#define PIO_PD23 (1u << 23) /**< \brief Pin Controlled by PD23 */\r
+#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */\r
+#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */\r
+#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */\r
+#define PIO_PD27 (1u << 27) /**< \brief Pin Controlled by PD27 */\r
+#define PIO_PD28 (1u << 28) /**< \brief Pin Controlled by PD28 */\r
+#define PIO_PD29 (1u << 29) /**< \brief Pin Controlled by PD29 */\r
+#define PIO_PD30 (1u << 30) /**< \brief Pin Controlled by PD30 */\r
+#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */\r
+#define PIO_PE0 (1u << 0) /**< \brief Pin Controlled by PE0 */\r
+#define PIO_PE1 (1u << 1) /**< \brief Pin Controlled by PE1 */\r
+#define PIO_PE2 (1u << 2) /**< \brief Pin Controlled by PE2 */\r
+#define PIO_PE3 (1u << 3) /**< \brief Pin Controlled by PE3 */\r
+#define PIO_PE4 (1u << 4) /**< \brief Pin Controlled by PE4 */\r
+#define PIO_PE5 (1u << 5) /**< \brief Pin Controlled by PE5 */\r
+/* ========== Pio definition for AFEC0 peripheral ========== */\r
+#define PIO_PA17X1_AFE0_AD0 (1u << 17) /**< \brief Afec0 signal: AFE0_AD0 */\r
+#define PIO_PA18X1_AFE0_AD1 (1u << 18) /**< \brief Afec0 signal: AFE0_AD1 */\r
+#define PIO_PC30X1_AFE0_AD10 (1u << 30) /**< \brief Afec0 signal: AFE0_AD10 */\r
+#define PIO_PC31X1_AFE0_AD11 (1u << 31) /**< \brief Afec0 signal: AFE0_AD11 */\r
+#define PIO_PC26X1_AFE0_AD12 (1u << 26) /**< \brief Afec0 signal: AFE0_AD12 */\r
+#define PIO_PC27X1_AFE0_AD13 (1u << 27) /**< \brief Afec0 signal: AFE0_AD13 */\r
+#define PIO_PC0X1_AFE0_AD14 (1u << 0) /**< \brief Afec0 signal: AFE0_AD14 */\r
+#define PIO_PA19X1_AFE0_AD2 (1u << 19) /**< \brief Afec0 signal: AFE0_AD2/WKUP9 */\r
+#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD2/WKUP9 */\r
+#define PIO_PA20X1_AFE0_AD3 (1u << 20) /**< \brief Afec0 signal: AFE0_AD3/WKUP10 */\r
+#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD3/WKUP10 */\r
+#define PIO_PB0X1_AFE0_AD4 (1u << 0) /**< \brief Afec0 signal: AFE0_AD4/RTCOUT0 */\r
+#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD4/RTCOUT0 */\r
+#define PIO_PB1X1_AFE0_AD5 (1u << 1) /**< \brief Afec0 signal: AFE0_AD5/RTCOUT1 */\r
+#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec0 signal: AFE0_AD5/RTCOUT1 */\r
+#define PIO_PC13X1_AFE0_AD6 (1u << 13) /**< \brief Afec0 signal: AFE0_AD6 */\r
+#define PIO_PC15X1_AFE0_AD7 (1u << 15) /**< \brief Afec0 signal: AFE0_AD7 */\r
+#define PIO_PC12X1_AFE0_AD8 (1u << 12) /**< \brief Afec0 signal: AFE0_AD8 */\r
+#define PIO_PC29X1_AFE0_AD9 (1u << 29) /**< \brief Afec0 signal: AFE0_AD9 */\r
+#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */\r
+/* ========== Pio definition for AFEC1 peripheral ========== */\r
+#define PIO_PB2X1_AFE1_AD0 (1u << 2) /**< \brief Afec1 signal: AFE1_AD0/WKUP12 */\r
+#define PIO_PB2X1_WKUP12 (1u << 2) /**< \brief Afec1 signal: AFE1_AD0/WKUP12 */\r
+#define PIO_PB3X1_AFE1_AD1 (1u << 3) /**< \brief Afec1 signal: AFE1_AD1 */\r
+#define PIO_PA21X1_AFE1_AD2 (1u << 21) /**< \brief Afec1 signal: AFE1_AD2 */\r
+#define PIO_PA22X1_AFE1_AD3 (1u << 22) /**< \brief Afec1 signal: AFE1_AD3 */\r
+#define PIO_PC1X1_AFE1_AD4 (1u << 1) /**< \brief Afec1 signal: AFE1_AD4 */\r
+#define PIO_PC2X1_AFE1_AD5 (1u << 2) /**< \brief Afec1 signal: AFE1_AD5 */\r
+#define PIO_PC3X1_AFE1_AD6 (1u << 3) /**< \brief Afec1 signal: AFE1_AD6 */\r
+#define PIO_PC4X1_AFE1_AD7 (1u << 4) /**< \brief Afec1 signal: AFE1_AD7 */\r
+/* ========== Pio definition for CAN0 peripheral ========== */\r
+#define PIO_PB3A_CANRX0 (1u << 3) /**< \brief Can0 signal: CANRX0 */\r
+#define PIO_PB2A_CANTX0 (1u << 2) /**< \brief Can0 signal: CANTX0 */\r
+/* ========== Pio definition for CAN1 peripheral ========== */\r
+#define PIO_PC12C_CANRX1 (1u << 12) /**< \brief Can1 signal: CANRX1 */\r
+#define PIO_PC15C_CANTX1 (1u << 15) /**< \brief Can1 signal: CANTX1 */\r
+/* ========== Pio definition for DACC peripheral ========== */\r
+#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */\r
+#define PIO_PB14X1_DAC1 (1u << 14) /**< \brief Dacc signal: DAC1 */\r
+#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */\r
+/* ========== Pio definition for EBI peripheral ========== */\r
+#define PIO_PC18A_A0 (1u << 18) /**< \brief Ebi signal: A0 */\r
+#define PIO_PC19A_A1 (1u << 19) /**< \brief Ebi signal: A1 */\r
+#define PIO_PC28A_A10 (1u << 28) /**< \brief Ebi signal: A10 */\r
+#define PIO_PC29A_A11 (1u << 29) /**< \brief Ebi signal: A11 */\r
+#define PIO_PC30A_A12 (1u << 30) /**< \brief Ebi signal: A12 */\r
+#define PIO_PC31A_A13 (1u << 31) /**< \brief Ebi signal: A13 */\r
+#define PIO_PA18C_A14 (1u << 18) /**< \brief Ebi signal: A14 */\r
+#define PIO_PA19C_A15 (1u << 19) /**< \brief Ebi signal: A15 */\r
+#define PIO_PA20C_A16 (1u << 20) /**< \brief Ebi signal: A16 */\r
+#define PIO_PA0C_A17 (1u << 0) /**< \brief Ebi signal: A17 */\r
+#define PIO_PA1C_A18 (1u << 1) /**< \brief Ebi signal: A18 */\r
+#define PIO_PA23C_A19 (1u << 23) /**< \brief Ebi signal: A19 */\r
+#define PIO_PC20A_A2 (1u << 20) /**< \brief Ebi signal: A2 */\r
+#define PIO_PA24C_A20 (1u << 24) /**< \brief Ebi signal: A20 */\r
+#define PIO_PC16A_A21 (1u << 16) /**< \brief Ebi signal: A21/NANDALE */\r
+#define PIO_PC16A_NANDALE (1u << 16) /**< \brief Ebi signal: A21/NANDALE */\r
+#define PIO_PC17A_A22 (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */\r
+#define PIO_PC17A_NANDCLE (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */\r
+#define PIO_PA25C_A23 (1u << 25) /**< \brief Ebi signal: A23 */\r
+#define PIO_PC21A_A3 (1u << 21) /**< \brief Ebi signal: A3 */\r
+#define PIO_PC22A_A4 (1u << 22) /**< \brief Ebi signal: A4 */\r
+#define PIO_PC23A_A5 (1u << 23) /**< \brief Ebi signal: A5 */\r
+#define PIO_PC24A_A6 (1u << 24) /**< \brief Ebi signal: A6 */\r
+#define PIO_PC25A_A7 (1u << 25) /**< \brief Ebi signal: A7 */\r
+#define PIO_PC26A_A8 (1u << 26) /**< \brief Ebi signal: A8 */\r
+#define PIO_PC27A_A9 (1u << 27) /**< \brief Ebi signal: A9 */\r
+#define PIO_PC0A_D0 (1u << 0) /**< \brief Ebi signal: D0 */\r
+#define PIO_PC1A_D1 (1u << 1) /**< \brief Ebi signal: D1 */\r
+#define PIO_PC2A_D2 (1u << 2) /**< \brief Ebi signal: D2 */\r
+#define PIO_PC3A_D3 (1u << 3) /**< \brief Ebi signal: D3 */\r
+#define PIO_PC4A_D4 (1u << 4) /**< \brief Ebi signal: D4 */\r
+#define PIO_PC5A_D5 (1u << 5) /**< \brief Ebi signal: D5 */\r
+#define PIO_PC6A_D6 (1u << 6) /**< \brief Ebi signal: D6 */\r
+#define PIO_PC7A_D7 (1u << 7) /**< \brief Ebi signal: D7 */\r
+#define PIO_PC9A_NANDOE (1u << 9) /**< \brief Ebi signal: NANDOE */\r
+#define PIO_PC10A_NANDWE (1u << 10) /**< \brief Ebi signal: NANDWE */\r
+#define PIO_PC14A_NCS0 (1u << 14) /**< \brief Ebi signal: NCS0 */\r
+#define PIO_PC15A_NCS1 (1u << 15) /**< \brief Ebi signal: NCS1 */\r
+#define PIO_PD18A_NCS1 (1u << 18) /**< \brief Ebi signal: NCS1 */\r
+#define PIO_PA22C_NCS2 (1u << 22) /**< \brief Ebi signal: NCS2 */\r
+#define PIO_PC12A_NCS3 (1u << 12) /**< \brief Ebi signal: NCS3 */\r
+#define PIO_PD19A_NCS3 (1u << 19) /**< \brief Ebi signal: NCS3 */\r
+#define PIO_PC11A_NRD (1u << 11) /**< \brief Ebi signal: NRD */\r
+#define PIO_PC13A_NWAIT (1u << 13) /**< \brief Ebi signal: NWAIT */\r
+#define PIO_PC8A_NWE (1u << 8) /**< \brief Ebi signal: NWE */\r
+/* ========== Pio definition for GMAC peripheral ========== */\r
+#define PIO_PD13A_GCOL (1u << 13) /**< \brief Gmac signal: GCOL */\r
+#define PIO_PD10A_GCRS (1u << 10) /**< \brief Gmac signal: GCRS */\r
+#define PIO_PD4A_GCRSDV (1u << 4) /**< \brief Gmac signal: GCRSDV/GRXDV */\r
+#define PIO_PD4A_GRXDV (1u << 4) /**< \brief Gmac signal: GCRSDV/GRXDV */\r
+#define PIO_PD8A_GMDC (1u << 8) /**< \brief Gmac signal: GMDC */\r
+#define PIO_PD9A_GMDIO (1u << 9) /**< \brief Gmac signal: GMDIO */\r
+#define PIO_PD5A_GRX0 (1u << 5) /**< \brief Gmac signal: GRX0 */\r
+#define PIO_PD6A_GRX0 (1u << 6) /**< \brief Gmac signal: GRX0 */\r
+#define PIO_PD11A_GRX2 (1u << 11) /**< \brief Gmac signal: GRX2 */\r
+#define PIO_PD12A_GRX3 (1u << 12) /**< \brief Gmac signal: GRX3 */\r
+#define PIO_PD14A_GRXCK (1u << 14) /**< \brief Gmac signal: GRXCK */\r
+#define PIO_PD7A_GRXER (1u << 7) /**< \brief Gmac signal: GRXER */\r
+#define PIO_PD2A_GTX0 (1u << 2) /**< \brief Gmac signal: GTX0 */\r
+#define PIO_PD3A_GTX1 (1u << 3) /**< \brief Gmac signal: GTX1 */\r
+#define PIO_PD15A_GTX2 (1u << 15) /**< \brief Gmac signal: GTX2 */\r
+#define PIO_PD16A_GTX3 (1u << 16) /**< \brief Gmac signal: GTX3 */\r
+#define PIO_PD0A_GTXCK (1u << 0) /**< \brief Gmac signal: GTXCK/GREFCK */\r
+#define PIO_PD0A_GREFCK (1u << 0) /**< \brief Gmac signal: GTXCK/GREFCK */\r
+#define PIO_PD1A_GTXEN (1u << 1) /**< \brief Gmac signal: GTXEN */\r
+#define PIO_PD17A_GTXER (1u << 17) /**< \brief Gmac signal: GTXER */\r
+/* ========== Pio definition for HSMCI peripheral ========== */\r
+#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */\r
+#define PIO_PA29C_MCCK (1u << 29) /**< \brief Hsmci signal: MCCK */\r
+#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */\r
+#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */\r
+#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */\r
+#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */\r
+/* ========== Pio definition for PIOA peripheral ========== */\r
+#define PIO_PA24X1_PIODC0 (1u << 24) /**< \brief Pioa signal: PIODC0 */\r
+#define PIO_PA25X1_PIODC1 (1u << 25) /**< \brief Pioa signal: PIODC1 */\r
+#define PIO_PA26X1_PIODC2 (1u << 26) /**< \brief Pioa signal: PIODC2 */\r
+#define PIO_PA27X1_PIODC3 (1u << 27) /**< \brief Pioa signal: PIODC3 */\r
+#define PIO_PA28X1_PIODC4 (1u << 28) /**< \brief Pioa signal: PIODC4 */\r
+#define PIO_PA29X1_PIODC5 (1u << 29) /**< \brief Pioa signal: PIODC5 */\r
+#define PIO_PA31X1_PIODC7 (1u << 31) /**< \brief Pioa signal: PIODC7 */\r
+#define PIO_PA23X1_PIODCCLK (1u << 23) /**< \brief Pioa signal: PIODCCLK */\r
+#define PIO_PA30X1_WKUP11 (1u << 30) /**< \brief Pioa signal: WKUP11/PIODC6 */\r
+#define PIO_PA30X1_PIODC6 (1u << 30) /**< \brief Pioa signal: WKUP11/PIODC6 */\r
+#define PIO_PA15X1_WKUP14 (1u << 15) /**< \brief Pioa signal: WKUP14/PIODCEN1 */\r
+#define PIO_PA15X1_PIODCEN1 (1u << 15) /**< \brief Pioa signal: WKUP14/PIODCEN1 */\r
+#define PIO_PA16X1_WKUP15 (1u << 16) /**< \brief Pioa signal: WKUP15/PIODCEN2 */\r
+#define PIO_PA16X1_PIODCEN2 (1u << 16) /**< \brief Pioa signal: WKUP15/PIODCEN2 */\r
+/* ========== Pio definition for PMC peripheral ========== */\r
+#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */\r
+#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */\r
+#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */\r
+#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */\r
+#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */\r
+#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */\r
+#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */\r
+/* ========== Pio definition for PWM peripheral ========== */\r
+#define PIO_PA9C_PWMFI0 (1u << 9) /**< \brief Pwm signal: PWMFI0 */\r
+#define PIO_PA0A_PWMH0 (1u << 0) /**< \brief Pwm signal: PWMH0 */\r
+#define PIO_PA11B_PWMH0 (1u << 11) /**< \brief Pwm signal: PWMH0 */\r
+#define PIO_PA23B_PWMH0 (1u << 23) /**< \brief Pwm signal: PWMH0 */\r
+#define PIO_PB0A_PWMH0 (1u << 0) /**< \brief Pwm signal: PWMH0 */\r
+#define PIO_PC18B_PWMH0 (1u << 18) /**< \brief Pwm signal: PWMH0 */\r
+#define PIO_PD20A_PWMH0 (1u << 20) /**< \brief Pwm signal: PWMH0 */\r
+#define PIO_PA1A_PWMH1 (1u << 1) /**< \brief Pwm signal: PWMH1 */\r
+#define PIO_PA12B_PWMH1 (1u << 12) /**< \brief Pwm signal: PWMH1 */\r
+#define PIO_PA24B_PWMH1 (1u << 24) /**< \brief Pwm signal: PWMH1 */\r
+#define PIO_PB1A_PWMH1 (1u << 1) /**< \brief Pwm signal: PWMH1 */\r
+#define PIO_PC19B_PWMH1 (1u << 19) /**< \brief Pwm signal: PWMH1 */\r
+#define PIO_PD21A_PWMH1 (1u << 21) /**< \brief Pwm signal: PWMH1 */\r
+#define PIO_PA2A_PWMH2 (1u << 2) /**< \brief Pwm signal: PWMH2 */\r
+#define PIO_PA13B_PWMH2 (1u << 13) /**< \brief Pwm signal: PWMH2 */\r
+#define PIO_PA25B_PWMH2 (1u << 25) /**< \brief Pwm signal: PWMH2 */\r
+#define PIO_PB4B_PWMH2 (1u << 4) /**< \brief Pwm signal: PWMH2 */\r
+#define PIO_PC20B_PWMH2 (1u << 20) /**< \brief Pwm signal: PWMH2 */\r
+#define PIO_PD22A_PWMH2 (1u << 22) /**< \brief Pwm signal: PWMH2 */\r
+#define PIO_PA7B_PWMH3 (1u << 7) /**< \brief Pwm signal: PWMH3 */\r
+#define PIO_PA14B_PWMH3 (1u << 14) /**< \brief Pwm signal: PWMH3 */\r
+#define PIO_PA17C_PWMH3 (1u << 17) /**< \brief Pwm signal: PWMH3 */\r
+#define PIO_PB14B_PWMH3 (1u << 14) /**< \brief Pwm signal: PWMH3 */\r
+#define PIO_PC21B_PWMH3 (1u << 21) /**< \brief Pwm signal: PWMH3 */\r
+#define PIO_PD23A_PWMH3 (1u << 23) /**< \brief Pwm signal: PWMH3 */\r
+#define PIO_PA19B_PWML0 (1u << 19) /**< \brief Pwm signal: PWML0 */\r
+#define PIO_PB5B_PWML0 (1u << 5) /**< \brief Pwm signal: PWML0 */\r
+#define PIO_PC0B_PWML0 (1u << 0) /**< \brief Pwm signal: PWML0 */\r
+#define PIO_PC13B_PWML0 (1u << 13) /**< \brief Pwm signal: PWML0 */\r
+#define PIO_PD24A_PWML0 (1u << 24) /**< \brief Pwm signal: PWML0 */\r
+#define PIO_PA20B_PWML1 (1u << 20) /**< \brief Pwm signal: PWML1 */\r
+#define PIO_PB12A_PWML1 (1u << 12) /**< \brief Pwm signal: PWML1 */\r
+#define PIO_PC1B_PWML1 (1u << 1) /**< \brief Pwm signal: PWML1 */\r
+#define PIO_PC15B_PWML1 (1u << 15) /**< \brief Pwm signal: PWML1 */\r
+#define PIO_PD25A_PWML1 (1u << 25) /**< \brief Pwm signal: PWML1 */\r
+#define PIO_PA16C_PWML2 (1u << 16) /**< \brief Pwm signal: PWML2 */\r
+#define PIO_PA30A_PWML2 (1u << 30) /**< \brief Pwm signal: PWML2 */\r
+#define PIO_PB13A_PWML2 (1u << 13) /**< \brief Pwm signal: PWML2 */\r
+#define PIO_PC2B_PWML2 (1u << 2) /**< \brief Pwm signal: PWML2 */\r
+#define PIO_PD26A_PWML2 (1u << 26) /**< \brief Pwm signal: PWML2 */\r
+#define PIO_PA15C_PWML3 (1u << 15) /**< \brief Pwm signal: PWML3 */\r
+#define PIO_PC3B_PWML3 (1u << 3) /**< \brief Pwm signal: PWML3 */\r
+#define PIO_PC22B_PWML3 (1u << 22) /**< \brief Pwm signal: PWML3 */\r
+#define PIO_PD27A_PWML3 (1u << 27) /**< \brief Pwm signal: PWML3 */\r
+/* ========== Pio definition for SPI peripheral ========== */\r
+#define PIO_PA12A_MISO (1u << 12) /**< \brief Spi signal: MISO */\r
+#define PIO_PA13A_MOSI (1u << 13) /**< \brief Spi signal: MOSI */\r
+#define PIO_PA11A_NPCS0 (1u << 11) /**< \brief Spi signal: NPCS0 */\r
+#define PIO_PA9B_NPCS1 (1u << 9) /**< \brief Spi signal: NPCS1 */\r
+#define PIO_PA31A_NPCS1 (1u << 31) /**< \brief Spi signal: NPCS1 */\r
+#define PIO_PB14A_NPCS1 (1u << 14) /**< \brief Spi signal: NPCS1 */\r
+#define PIO_PC4B_NPCS1 (1u << 4) /**< \brief Spi signal: NPCS1 */\r
+#define PIO_PA10B_NPCS2 (1u << 10) /**< \brief Spi signal: NPCS2 */\r
+#define PIO_PA30B_NPCS2 (1u << 30) /**< \brief Spi signal: NPCS2 */\r
+#define PIO_PB2B_NPCS2 (1u << 2) /**< \brief Spi signal: NPCS2 */\r
+#define PIO_PA3B_NPCS3 (1u << 3) /**< \brief Spi signal: NPCS3 */\r
+#define PIO_PA5B_NPCS3 (1u << 5) /**< \brief Spi signal: NPCS3 */\r
+#define PIO_PA22B_NPCS3 (1u << 22) /**< \brief Spi signal: NPCS3 */\r
+#define PIO_PA14A_SPCK (1u << 14) /**< \brief Spi signal: SPCK */\r
+/* ========== Pio definition for TC0 peripheral ========== */\r
+#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */\r
+#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */\r
+#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */\r
+#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */\r
+#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */\r
+#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */\r
+#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */\r
+#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */\r
+#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */\r
+/* ========== Pio definition for TC1 peripheral ========== */\r
+#define PIO_PC25B_TCLK3 (1u << 25) /**< \brief Tc1 signal: TCLK3 */\r
+#define PIO_PC28B_TCLK4 (1u << 28) /**< \brief Tc1 signal: TCLK4 */\r
+#define PIO_PC31B_TCLK5 (1u << 31) /**< \brief Tc1 signal: TCLK5 */\r
+#define PIO_PC23B_TIOA3 (1u << 23) /**< \brief Tc1 signal: TIOA3 */\r
+#define PIO_PC26B_TIOA4 (1u << 26) /**< \brief Tc1 signal: TIOA4 */\r
+#define PIO_PC29B_TIOA5 (1u << 29) /**< \brief Tc1 signal: TIOA5 */\r
+#define PIO_PC24B_TIOB3 (1u << 24) /**< \brief Tc1 signal: TIOB3 */\r
+#define PIO_PC27B_TIOB4 (1u << 27) /**< \brief Tc1 signal: TIOB4 */\r
+#define PIO_PC30B_TIOB5 (1u << 30) /**< \brief Tc1 signal: TIOB5 */\r
+/* ========== Pio definition for TC2 peripheral ========== */\r
+#define PIO_PC7B_TCLK6 (1u << 7) /**< \brief Tc2 signal: TCLK6 */\r
+#define PIO_PC10B_TCLK7 (1u << 10) /**< \brief Tc2 signal: TCLK7 */\r
+#define PIO_PC14B_TCLK8 (1u << 14) /**< \brief Tc2 signal: TCLK8 */\r
+#define PIO_PC5B_TIOA6 (1u << 5) /**< \brief Tc2 signal: TIOA6 */\r
+#define PIO_PC8B_TIOA7 (1u << 8) /**< \brief Tc2 signal: TIOA7 */\r
+#define PIO_PC11B_TIOA8 (1u << 11) /**< \brief Tc2 signal: TIOA8 */\r
+#define PIO_PC6B_TIOB6 (1u << 6) /**< \brief Tc2 signal: TIOB6 */\r
+#define PIO_PC9B_TIOB7 (1u << 9) /**< \brief Tc2 signal: TIOB7 */\r
+#define PIO_PC12B_TIOB8 (1u << 12) /**< \brief Tc2 signal: TIOB8 */\r
+/* ========== Pio definition for TWI0 peripheral ========== */\r
+#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twi0 signal: TWCK0 */\r
+#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twi0 signal: TWD0 */\r
+/* ========== Pio definition for TWI1 peripheral ========== */\r
+#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twi1 signal: TWCK1 */\r
+#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twi1 signal: TWD1 */\r
+/* ========== Pio definition for UART0 peripheral ========== */\r
+#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */\r
+#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */\r
+/* ========== Pio definition for UART1 peripheral ========== */\r
+#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */\r
+#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */\r
+/* ========== Pio definition for USART0 peripheral ========== */\r
+#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */\r
+#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */\r
+#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */\r
+#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */\r
+#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */\r
+/* ========== Pio definition for USART1 peripheral ========== */\r
+#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */\r
+#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */\r
+#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */\r
+#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */\r
+#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */\r
+#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */\r
+#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */\r
+#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */\r
+#define PIO_PA22A_TXD1 (1u << 22) /**< \brief Usart1 signal: TXD1 */\r
+/* ========== Pio indexes ========== */\r
+#define PIO_PA0_IDX 0\r
+#define PIO_PA1_IDX 1\r
+#define PIO_PA2_IDX 2\r
+#define PIO_PA3_IDX 3\r
+#define PIO_PA4_IDX 4\r
+#define PIO_PA5_IDX 5\r
+#define PIO_PA6_IDX 6\r
+#define PIO_PA7_IDX 7\r
+#define PIO_PA8_IDX 8\r
+#define PIO_PA9_IDX 9\r
+#define PIO_PA10_IDX 10\r
+#define PIO_PA11_IDX 11\r
+#define PIO_PA12_IDX 12\r
+#define PIO_PA13_IDX 13\r
+#define PIO_PA14_IDX 14\r
+#define PIO_PA15_IDX 15\r
+#define PIO_PA16_IDX 16\r
+#define PIO_PA17_IDX 17\r
+#define PIO_PA18_IDX 18\r
+#define PIO_PA19_IDX 19\r
+#define PIO_PA20_IDX 20\r
+#define PIO_PA21_IDX 21\r
+#define PIO_PA22_IDX 22\r
+#define PIO_PA23_IDX 23\r
+#define PIO_PA24_IDX 24\r
+#define PIO_PA25_IDX 25\r
+#define PIO_PA26_IDX 26\r
+#define PIO_PA27_IDX 27\r
+#define PIO_PA28_IDX 28\r
+#define PIO_PA29_IDX 29\r
+#define PIO_PA30_IDX 30\r
+#define PIO_PA31_IDX 31\r
+#define PIO_PB0_IDX 32\r
+#define PIO_PB1_IDX 33\r
+#define PIO_PB2_IDX 34\r
+#define PIO_PB3_IDX 35\r
+#define PIO_PB4_IDX 36\r
+#define PIO_PB5_IDX 37\r
+#define PIO_PB6_IDX 38\r
+#define PIO_PB7_IDX 39\r
+#define PIO_PB8_IDX 40\r
+#define PIO_PB9_IDX 41\r
+#define PIO_PB10_IDX 42\r
+#define PIO_PB11_IDX 43\r
+#define PIO_PB12_IDX 44\r
+#define PIO_PB13_IDX 45\r
+#define PIO_PB14_IDX 46\r
+#define PIO_PC0_IDX 64\r
+#define PIO_PC1_IDX 65\r
+#define PIO_PC2_IDX 66\r
+#define PIO_PC3_IDX 67\r
+#define PIO_PC4_IDX 68\r
+#define PIO_PC5_IDX 69\r
+#define PIO_PC6_IDX 70\r
+#define PIO_PC7_IDX 71\r
+#define PIO_PC8_IDX 72\r
+#define PIO_PC9_IDX 73\r
+#define PIO_PC10_IDX 74\r
+#define PIO_PC11_IDX 75\r
+#define PIO_PC12_IDX 76\r
+#define PIO_PC13_IDX 77\r
+#define PIO_PC14_IDX 78\r
+#define PIO_PC15_IDX 79\r
+#define PIO_PC16_IDX 80\r
+#define PIO_PC17_IDX 81\r
+#define PIO_PC18_IDX 82\r
+#define PIO_PC19_IDX 83\r
+#define PIO_PC20_IDX 84\r
+#define PIO_PC21_IDX 85\r
+#define PIO_PC22_IDX 86\r
+#define PIO_PC23_IDX 87\r
+#define PIO_PC24_IDX 88\r
+#define PIO_PC25_IDX 89\r
+#define PIO_PC26_IDX 90\r
+#define PIO_PC27_IDX 91\r
+#define PIO_PC28_IDX 92\r
+#define PIO_PC29_IDX 93\r
+#define PIO_PC30_IDX 94\r
+#define PIO_PC31_IDX 95\r
+#define PIO_PD0_IDX 96\r
+#define PIO_PD1_IDX 97\r
+#define PIO_PD2_IDX 98\r
+#define PIO_PD3_IDX 99\r
+#define PIO_PD4_IDX 100\r
+#define PIO_PD5_IDX 101\r
+#define PIO_PD6_IDX 102\r
+#define PIO_PD7_IDX 103\r
+#define PIO_PD8_IDX 104\r
+#define PIO_PD9_IDX 105\r
+#define PIO_PD10_IDX 106\r
+#define PIO_PD11_IDX 107\r
+#define PIO_PD12_IDX 108\r
+#define PIO_PD13_IDX 109\r
+#define PIO_PD14_IDX 110\r
+#define PIO_PD15_IDX 111\r
+#define PIO_PD16_IDX 112\r
+#define PIO_PD17_IDX 113\r
+#define PIO_PD18_IDX 114\r
+#define PIO_PD19_IDX 115\r
+#define PIO_PD20_IDX 116\r
+#define PIO_PD21_IDX 117\r
+#define PIO_PD22_IDX 118\r
+#define PIO_PD23_IDX 119\r
+#define PIO_PD24_IDX 120\r
+#define PIO_PD25_IDX 121\r
+#define PIO_PD26_IDX 122\r
+#define PIO_PD27_IDX 123\r
+#define PIO_PD28_IDX 124\r
+#define PIO_PD29_IDX 125\r
+#define PIO_PD30_IDX 126\r
+#define PIO_PD31_IDX 127\r
+#define PIO_PE0_IDX 128\r
+#define PIO_PE1_IDX 129\r
+#define PIO_PE2_IDX 130\r
+#define PIO_PE3_IDX 131\r
+#define PIO_PE4_IDX 132\r
+#define PIO_PE5_IDX 133\r
+\r
+#endif /* _SAM4E8E_PIO_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4E_\r
+#define _SAM4E_\r
+\r
+#if defined __SAM4E8C__\r
+ #include "sam4e8c.h"\r
+#elif defined __SAM4E8E__\r
+ #include "sam4e8e.h"\r
+#elif defined __SAM4E16C__\r
+ #include "sam4e16c.h"\r
+#elif defined __SAM4E16E__\r
+ #include "sam4e16e.h"\r
+#else\r
+ #error Library does not support the specified device.\r
+#endif\r
+\r
+#endif /* _SAM4E_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4E16C_\r
+#define _SAM4E16C_\r
+\r
+/** \addtogroup SAM4E16C_definitions SAM4E16C definitions\r
+ This file defines all structures and symbols for SAM4E16C:\r
+ - registers and bitfields\r
+ - peripheral base address\r
+ - peripheral ID\r
+ - PIO definitions\r
+*/\r
+/*@{*/\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#include <stdint.h>\r
+#ifndef __cplusplus\r
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */\r
+#else\r
+typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */\r
+#endif\r
+typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */\r
+typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */\r
+#endif\r
+\r
+/* ************************************************************************** */\r
+/* CMSIS DEFINITIONS FOR SAM4E16C */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAM4E16C_cmsis CMSIS Definitions */\r
+/*@{*/\r
+\r
+/**< Interrupt Number Definition */\r
+typedef enum IRQn\r
+{\r
+/****** Cortex-M4 Processor Exceptions Numbers ******************************/\r
+ NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */\r
+ MemoryManagement_IRQn = -12, /**< 4 Cortex-M4 Memory Management Interrupt */\r
+ BusFault_IRQn = -11, /**< 5 Cortex-M4 Bus Fault Interrupt */\r
+ UsageFault_IRQn = -10, /**< 6 Cortex-M4 Usage Fault Interrupt */\r
+ SVCall_IRQn = -5, /**< 11 Cortex-M4 SV Call Interrupt */\r
+ DebugMonitor_IRQn = -4, /**< 12 Cortex-M4 Debug Monitor Interrupt */\r
+ PendSV_IRQn = -2, /**< 14 Cortex-M4 Pend SV Interrupt */\r
+ SysTick_IRQn = -1, /**< 15 Cortex-M4 System Tick Interrupt */\r
+/****** SAM4E16C specific Interrupt Numbers *********************************/\r
+\r
+ SUPC_IRQn = 0, /**< 0 SAM4E16C Supply Controller (SUPC) */\r
+ RSTC_IRQn = 1, /**< 1 SAM4E16C Reset Controller (RSTC) */\r
+ RTC_IRQn = 2, /**< 2 SAM4E16C Real Time Clock (RTC) */\r
+ RTT_IRQn = 3, /**< 3 SAM4E16C Real Time Timer (RTT) */\r
+ WDT_IRQn = 4, /**< 4 SAM4E16C Watchdog/Dual Watchdog Timer (WDT) */\r
+ PMC_IRQn = 5, /**< 5 SAM4E16C Power Management Controller (PMC) */\r
+ EFC_IRQn = 6, /**< 6 SAM4E16C Enhanced Embedded Flash Controller (EFC) */\r
+ UART0_IRQn = 7, /**< 7 SAM4E16C UART 0 (UART0) */\r
+ PIOA_IRQn = 9, /**< 9 SAM4E16C Parallel I/O Controller A (PIOA) */\r
+ PIOB_IRQn = 10, /**< 10 SAM4E16C Parallel I/O Controller B (PIOB) */\r
+ PIOC_IRQn = 11, /**< 11 SAM4E16C Parallel I/O Controller C (PIOC) */\r
+ USART0_IRQn = 14, /**< 14 SAM4E16C USART 0 (USART0) */\r
+ USART1_IRQn = 15, /**< 15 SAM4E16C USART 1 (USART1) */\r
+ HSMCI_IRQn = 16, /**< 16 SAM4E16C Multimedia Card Interface (HSMCI) */\r
+ TWI0_IRQn = 17, /**< 17 SAM4E16C Two Wire Interface 0 (TWI0) */\r
+ TWI1_IRQn = 18, /**< 18 SAM4E16C Two Wire Interface 1 (TWI1) */\r
+ SPI_IRQn = 19, /**< 19 SAM4E16C Serial Peripheral Interface (SPI) */\r
+ DMAC_IRQn = 20, /**< 20 SAM4E16C DMAC (DMAC) */\r
+ TC0_IRQn = 21, /**< 21 SAM4E16C Timer/Counter 0 (TC0) */\r
+ TC1_IRQn = 22, /**< 22 SAM4E16C Timer/Counter 1 (TC1) */\r
+ TC2_IRQn = 23, /**< 23 SAM4E16C Timer/Counter 2 (TC2) */\r
+ TC3_IRQn = 24, /**< 24 SAM4E16C Timer/Counter 3 (TC3) */\r
+ TC4_IRQn = 25, /**< 25 SAM4E16C Timer/Counter 4 (TC4) */\r
+ TC5_IRQn = 26, /**< 26 SAM4E16C Timer/Counter 5 (TC5) */\r
+ TC6_IRQn = 27, /**< 27 SAM4E16C Timer/Counter 6 (TC6) */\r
+ TC7_IRQn = 28, /**< 28 SAM4E16C Timer/Counter 7 (TC7) */\r
+ TC8_IRQn = 29, /**< 29 SAM4E16C Timer/Counter 8 (TC8) */\r
+ AFEC0_IRQn = 30, /**< 30 SAM4E16C Analog Front End 0 (AFEC0) */\r
+ AFEC1_IRQn = 31, /**< 31 SAM4E16C Analog Front End 1 (AFEC1) */\r
+ DACC_IRQn = 32, /**< 32 SAM4E16C Digital To Analog Converter (DACC) */\r
+ ACC_IRQn = 33, /**< 33 SAM4E16C Analog Comparator (ACC) */\r
+ ARM_IRQn = 34, /**< 34 SAM4E16C FPU signals : FPIXC, FPOFC, FPUFC, FPIOC, FPDZC, FPIDC, FPIXC (ARM) */\r
+ UDP_IRQn = 35, /**< 35 SAM4E16C USB DEVICE (UDP) */\r
+ PWM_IRQn = 36, /**< 36 SAM4E16C PWM (PWM) */\r
+ CAN0_IRQn = 37, /**< 37 SAM4E16C CAN0 (CAN0) */\r
+ CAN1_IRQn = 38, /**< 38 SAM4E16C CAN1 (CAN1) */\r
+ AES_IRQn = 39, /**< 39 SAM4E16C AES (AES) */\r
+ UART1_IRQn = 45, /**< 45 SAM4E16C UART (UART1) */\r
+\r
+ PERIPH_COUNT_IRQn = 46 /**< Number of peripheral IDs */\r
+} IRQn_Type;\r
+\r
+typedef struct _DeviceVectors\r
+{\r
+ /* Stack pointer */\r
+ void* pvStack;\r
+\r
+ /* Cortex-M handlers */\r
+ void* pfnReset_Handler;\r
+ void* pfnNMI_Handler;\r
+ void* pfnHardFault_Handler;\r
+ void* pfnMemManage_Handler;\r
+ void* pfnBusFault_Handler;\r
+ void* pfnUsageFault_Handler;\r
+ void* pfnReserved1_Handler;\r
+ void* pfnReserved2_Handler;\r
+ void* pfnReserved3_Handler;\r
+ void* pfnReserved4_Handler;\r
+ void* pfnSVC_Handler;\r
+ void* pfnDebugMon_Handler;\r
+ void* pfnReserved5_Handler;\r
+ void* pfnPendSV_Handler;\r
+ void* pfnSysTick_Handler;\r
+\r
+ /* Peripheral handlers */\r
+ void* pfnSUPC_Handler; /* 0 Supply Controller */\r
+ void* pfnRSTC_Handler; /* 1 Reset Controller */\r
+ void* pfnRTC_Handler; /* 2 Real Time Clock */\r
+ void* pfnRTT_Handler; /* 3 Real Time Timer */\r
+ void* pfnWDT_Handler; /* 4 Watchdog/Dual Watchdog Timer */\r
+ void* pfnPMC_Handler; /* 5 Power Management Controller */\r
+ void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */\r
+ void* pfnUART0_Handler; /* 7 UART 0 */\r
+ void* pvReserved8;\r
+ void* pfnPIOA_Handler; /* 9 Parallel I/O Controller A */\r
+ void* pfnPIOB_Handler; /* 10 Parallel I/O Controller B */\r
+ void* pfnPIOC_Handler; /* 11 Parallel I/O Controller C */\r
+ void* pvReserved12;\r
+ void* pvReserved13;\r
+ void* pfnUSART0_Handler; /* 14 USART 0 */\r
+ void* pfnUSART1_Handler; /* 15 USART 1 */\r
+ void* pfnHSMCI_Handler; /* 16 Multimedia Card Interface */\r
+ void* pfnTWI0_Handler; /* 17 Two Wire Interface 0 */\r
+ void* pfnTWI1_Handler; /* 18 Two Wire Interface 1 */\r
+ void* pfnSPI_Handler; /* 19 Serial Peripheral Interface */\r
+ void* pfnDMAC_Handler; /* 20 DMAC */\r
+ void* pfnTC0_Handler; /* 21 Timer/Counter 0 */\r
+ void* pfnTC1_Handler; /* 22 Timer/Counter 1 */\r
+ void* pfnTC2_Handler; /* 23 Timer/Counter 2 */\r
+ void* pfnTC3_Handler; /* 24 Timer/Counter 3 */\r
+ void* pfnTC4_Handler; /* 25 Timer/Counter 4 */\r
+ void* pfnTC5_Handler; /* 26 Timer/Counter 5 */\r
+ void* pfnTC6_Handler; /* 27 Timer/Counter 6 */\r
+ void* pfnTC7_Handler; /* 28 Timer/Counter 7 */\r
+ void* pfnTC8_Handler; /* 29 Timer/Counter 8 */\r
+ void* pfnAFEC0_Handler; /* 30 Analog Front End 0 */\r
+ void* pfnAFEC1_Handler; /* 31 Analog Front End 1 */\r
+ void* pfnDACC_Handler; /* 32 Digital To Analog Converter */\r
+ void* pfnACC_Handler; /* 33 Analog Comparator */\r
+ void* pfnARM_Handler; /* 34 FPU signals : FPIXC, FPOFC, FPUFC, FPIOC, FPDZC, FPIDC, FPIXC */\r
+ void* pfnUDP_Handler; /* 35 USB DEVICE */\r
+ void* pfnPWM_Handler; /* 36 PWM */\r
+ void* pfnCAN0_Handler; /* 37 CAN0 */\r
+ void* pfnCAN1_Handler; /* 38 CAN1 */\r
+ void* pfnAES_Handler; /* 39 AES */\r
+ void* pvReserved40;\r
+ void* pvReserved41;\r
+ void* pvReserved42;\r
+ void* pvReserved43;\r
+ void* pvReserved44;\r
+ void* pfnUART1_Handler; /* 45 UART */\r
+} DeviceVectors;\r
+\r
+/* Cortex-M4 core handlers */\r
+void Reset_Handler ( void );\r
+void NMI_Handler ( void );\r
+void HardFault_Handler ( void );\r
+void MemManage_Handler ( void );\r
+void BusFault_Handler ( void );\r
+void UsageFault_Handler ( void );\r
+void SVC_Handler ( void );\r
+void DebugMon_Handler ( void );\r
+void PendSV_Handler ( void );\r
+void SysTick_Handler ( void );\r
+\r
+/* Peripherals handlers */\r
+void ACC_Handler ( void );\r
+void AES_Handler ( void );\r
+void AFEC0_Handler ( void );\r
+void AFEC1_Handler ( void );\r
+void ARM_Handler ( void );\r
+void CAN0_Handler ( void );\r
+void CAN1_Handler ( void );\r
+void DACC_Handler ( void );\r
+void DMAC_Handler ( void );\r
+void EFC_Handler ( void );\r
+void HSMCI_Handler ( void );\r
+void PIOA_Handler ( void );\r
+void PIOB_Handler ( void );\r
+void PIOC_Handler ( void );\r
+void PMC_Handler ( void );\r
+void PWM_Handler ( void );\r
+void RSTC_Handler ( void );\r
+void RTC_Handler ( void );\r
+void RTT_Handler ( void );\r
+void SPI_Handler ( void );\r
+void SUPC_Handler ( void );\r
+void TC0_Handler ( void );\r
+void TC1_Handler ( void );\r
+void TC2_Handler ( void );\r
+void TC3_Handler ( void );\r
+void TC4_Handler ( void );\r
+void TC5_Handler ( void );\r
+void TC6_Handler ( void );\r
+void TC7_Handler ( void );\r
+void TC8_Handler ( void );\r
+void TWI0_Handler ( void );\r
+void TWI1_Handler ( void );\r
+void UART0_Handler ( void );\r
+void UART1_Handler ( void );\r
+void UDP_Handler ( void );\r
+void USART0_Handler ( void );\r
+void USART1_Handler ( void );\r
+void WDT_Handler ( void );\r
+\r
+/**\r
+ * \brief Configuration of the Cortex-M4 Processor and Core Peripherals\r
+ */\r
+\r
+#define __CM4_REV 0x0000 /**< SAM4E16C core revision number ([15:8] revision number, [7:0] patch number) */\r
+#define __MPU_PRESENT 0 /**< SAM4E16C does not provide a MPU */\r
+#define __FPU_PRESENT 1 /**< SAM4E16C does provide a FPU */\r
+#define __NVIC_PRIO_BITS 4 /**< SAM4E16C uses 4 Bits for the Priority Levels */\r
+#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */\r
+\r
+/*\r
+ * \brief CMSIS includes\r
+ */\r
+\r
+#include <core_cm4.h>\r
+#if !defined DONT_USE_CMSIS_INIT\r
+#include "system_sam4e.h"\r
+#endif /* DONT_USE_CMSIS_INIT */\r
+\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** SOFTWARE PERIPHERAL API DEFINITION FOR SAM4E16C */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAM4E16C_api Peripheral Software API */\r
+/*@{*/\r
+\r
+#include "component/acc.h"\r
+#include "component/aes.h"\r
+#include "component/afec.h"\r
+#include "component/can.h"\r
+#include "component/chipid.h"\r
+#include "component/cmcc.h"\r
+#include "component/crccu.h"\r
+#include "component/dacc.h"\r
+#include "component/dmac.h"\r
+#include "component/efc.h"\r
+#include "component/gpbr.h"\r
+#include "component/hsmci.h"\r
+#include "component/matrix.h"\r
+#include "component/pdc.h"\r
+#include "component/pio.h"\r
+#include "component/pmc.h"\r
+#include "component/pwm.h"\r
+#include "component/rstc.h"\r
+#include "component/rswdt.h"\r
+#include "component/rtc.h"\r
+#include "component/rtt.h"\r
+#include "component/spi.h"\r
+#include "component/supc.h"\r
+#include "component/tc.h"\r
+#include "component/twi.h"\r
+#include "component/uart.h"\r
+#include "component/udp.h"\r
+#include "component/usart.h"\r
+#include "component/wdt.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* REGISTER ACCESS DEFINITIONS FOR SAM4E16C */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAM4E16C_reg Registers Access Definitions */\r
+/*@{*/\r
+\r
+#include "instance/pwm.h"\r
+#include "instance/aes.h"\r
+#include "instance/can0.h"\r
+#include "instance/can1.h"\r
+#include "instance/crccu.h"\r
+#include "instance/uart1.h"\r
+#include "instance/hsmci.h"\r
+#include "instance/udp.h"\r
+#include "instance/spi.h"\r
+#include "instance/tc0.h"\r
+#include "instance/tc1.h"\r
+#include "instance/tc2.h"\r
+#include "instance/usart0.h"\r
+#include "instance/usart1.h"\r
+#include "instance/twi0.h"\r
+#include "instance/twi1.h"\r
+#include "instance/afec0.h"\r
+#include "instance/afec1.h"\r
+#include "instance/dacc.h"\r
+#include "instance/acc.h"\r
+#include "instance/dmac.h"\r
+#include "instance/cmcc.h"\r
+#include "instance/matrix.h"\r
+#include "instance/pmc.h"\r
+#include "instance/uart0.h"\r
+#include "instance/chipid.h"\r
+#include "instance/efc.h"\r
+#include "instance/pioa.h"\r
+#include "instance/piob.h"\r
+#include "instance/pioc.h"\r
+#include "instance/rstc.h"\r
+#include "instance/supc.h"\r
+#include "instance/rtt.h"\r
+#include "instance/wdt.h"\r
+#include "instance/rtc.h"\r
+#include "instance/gpbr.h"\r
+#include "instance/rswdt.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* PERIPHERAL ID DEFINITIONS FOR SAM4E16C */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAM4E16C_id Peripheral Ids Definitions */\r
+/*@{*/\r
+\r
+#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */\r
+#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */\r
+#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */\r
+#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */\r
+#define ID_WDT ( 4) /**< \brief Watchdog/Dual Watchdog Timer (WDT) */\r
+#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */\r
+#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */\r
+#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */\r
+#define ID_PIOA ( 9) /**< \brief Parallel I/O Controller A (PIOA) */\r
+#define ID_PIOB (10) /**< \brief Parallel I/O Controller B (PIOB) */\r
+#define ID_PIOC (11) /**< \brief Parallel I/O Controller C (PIOC) */\r
+#define ID_USART0 (14) /**< \brief USART 0 (USART0) */\r
+#define ID_USART1 (15) /**< \brief USART 1 (USART1) */\r
+#define ID_HSMCI (16) /**< \brief Multimedia Card Interface (HSMCI) */\r
+#define ID_TWI0 (17) /**< \brief Two Wire Interface 0 (TWI0) */\r
+#define ID_TWI1 (18) /**< \brief Two Wire Interface 1 (TWI1) */\r
+#define ID_SPI (19) /**< \brief Serial Peripheral Interface (SPI) */\r
+#define ID_DMAC (20) /**< \brief DMAC (DMAC) */\r
+#define ID_TC0 (21) /**< \brief Timer/Counter 0 (TC0) */\r
+#define ID_TC1 (22) /**< \brief Timer/Counter 1 (TC1) */\r
+#define ID_TC2 (23) /**< \brief Timer/Counter 2 (TC2) */\r
+#define ID_TC3 (24) /**< \brief Timer/Counter 3 (TC3) */\r
+#define ID_TC4 (25) /**< \brief Timer/Counter 4 (TC4) */\r
+#define ID_TC5 (26) /**< \brief Timer/Counter 5 (TC5) */\r
+#define ID_TC6 (27) /**< \brief Timer/Counter 6 (TC6) */\r
+#define ID_TC7 (28) /**< \brief Timer/Counter 7 (TC7) */\r
+#define ID_TC8 (29) /**< \brief Timer/Counter 8 (TC8) */\r
+#define ID_AFEC0 (30) /**< \brief Analog Front End 0 (AFEC0) */\r
+#define ID_AFEC1 (31) /**< \brief Analog Front End 1 (AFEC1) */\r
+#define ID_DACC (32) /**< \brief Digital To Analog Converter (DACC) */\r
+#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */\r
+#define ID_ARM (34) /**< \brief FPU signals : FPIXC, FPOFC, FPUFC, FPIOC, FPDZC, FPIDC, FPIXC (ARM) */\r
+#define ID_UDP (35) /**< \brief USB DEVICE (UDP) */\r
+#define ID_PWM (36) /**< \brief PWM (PWM) */\r
+#define ID_CAN0 (37) /**< \brief CAN0 (CAN0) */\r
+#define ID_CAN1 (38) /**< \brief CAN1 (CAN1) */\r
+#define ID_AES (39) /**< \brief AES (AES) */\r
+#define ID_UART1 (45) /**< \brief UART (UART1) */\r
+\r
+#define ID_PERIPH_COUNT (46) /**< \brief Number of peripheral IDs */\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* BASE ADDRESS DEFINITIONS FOR SAM4E16C */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAM4E16C_base Peripheral Base Address Definitions */\r
+/*@{*/\r
+\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define PWM (0x40000000U) /**< \brief (PWM ) Base Address */\r
+#define PDC_PWM (0x40000100U) /**< \brief (PDC_PWM ) Base Address */\r
+#define AES (0x40004000U) /**< \brief (AES ) Base Address */\r
+#define CAN0 (0x40010000U) /**< \brief (CAN0 ) Base Address */\r
+#define CAN1 (0x40014000U) /**< \brief (CAN1 ) Base Address */\r
+#define CRCCU (0x40044000U) /**< \brief (CRCCU ) Base Address */\r
+#define UART1 (0x40060600U) /**< \brief (UART1 ) Base Address */\r
+#define PDC_UART1 (0x40060700U) /**< \brief (PDC_UART1 ) Base Address */\r
+#define HSMCI (0x40080000U) /**< \brief (HSMCI ) Base Address */\r
+#define PDC_HSMCI (0x40080100U) /**< \brief (PDC_HSMCI ) Base Address */\r
+#define UDP (0x40084000U) /**< \brief (UDP ) Base Address */\r
+#define SPI (0x40088000U) /**< \brief (SPI ) Base Address */\r
+#define PDC_SPI (0x40088100U) /**< \brief (PDC_SPI ) Base Address */\r
+#define TC0 (0x40090000U) /**< \brief (TC0 ) Base Address */\r
+#define PDC_TC0 (0x40090100U) /**< \brief (PDC_TC0 ) Base Address */\r
+#define TC1 (0x40094000U) /**< \brief (TC1 ) Base Address */\r
+#define PDC_TC1 (0x40094100U) /**< \brief (PDC_TC1 ) Base Address */\r
+#define TC2 (0x40098000U) /**< \brief (TC2 ) Base Address */\r
+#define USART0 (0x400A0000U) /**< \brief (USART0 ) Base Address */\r
+#define PDC_USART0 (0x400A0100U) /**< \brief (PDC_USART0) Base Address */\r
+#define USART1 (0x400A4000U) /**< \brief (USART1 ) Base Address */\r
+#define PDC_USART1 (0x400A4100U) /**< \brief (PDC_USART1) Base Address */\r
+#define TWI0 (0x400A8000U) /**< \brief (TWI0 ) Base Address */\r
+#define PDC_TWI0 (0x400A8100U) /**< \brief (PDC_TWI0 ) Base Address */\r
+#define TWI1 (0x400AC000U) /**< \brief (TWI1 ) Base Address */\r
+#define PDC_TWI1 (0x400AC100U) /**< \brief (PDC_TWI1 ) Base Address */\r
+#define AFEC0 (0x400B0000U) /**< \brief (AFEC0 ) Base Address */\r
+#define PDC_AFEC0 (0x400B0100U) /**< \brief (PDC_AFEC0 ) Base Address */\r
+#define AFEC1 (0x400B4000U) /**< \brief (AFEC1 ) Base Address */\r
+#define PDC_AFEC1 (0x400B4100U) /**< \brief (PDC_AFEC1 ) Base Address */\r
+#define DACC (0x400B8000U) /**< \brief (DACC ) Base Address */\r
+#define PDC_DACC (0x400B8100U) /**< \brief (PDC_DACC ) Base Address */\r
+#define ACC (0x400BC000U) /**< \brief (ACC ) Base Address */\r
+#define DMAC (0x400C0000U) /**< \brief (DMAC ) Base Address */\r
+#define CMCC (0x400C4000U) /**< \brief (CMCC ) Base Address */\r
+#define MATRIX (0x400E0200U) /**< \brief (MATRIX ) Base Address */\r
+#define PMC (0x400E0400U) /**< \brief (PMC ) Base Address */\r
+#define UART0 (0x400E0600U) /**< \brief (UART0 ) Base Address */\r
+#define PDC_UART0 (0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */\r
+#define CHIPID (0x400E0740U) /**< \brief (CHIPID ) Base Address */\r
+#define EFC (0x400E0A00U) /**< \brief (EFC ) Base Address */\r
+#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */\r
+#define PDC_PIOA (0x400E0F68U) /**< \brief (PDC_PIOA ) Base Address */\r
+#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */\r
+#define PIOC (0x400E1200U) /**< \brief (PIOC ) Base Address */\r
+#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */\r
+#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */\r
+#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */\r
+#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */\r
+#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */\r
+#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */\r
+#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */\r
+#else\r
+#define PWM ((Pwm *)0x40000000U) /**< \brief (PWM ) Base Address */\r
+#define PDC_PWM ((Pdc *)0x40000100U) /**< \brief (PDC_PWM ) Base Address */\r
+#define AES ((Aes *)0x40004000U) /**< \brief (AES ) Base Address */\r
+#define CAN0 ((Can *)0x40010000U) /**< \brief (CAN0 ) Base Address */\r
+#define CAN1 ((Can *)0x40014000U) /**< \brief (CAN1 ) Base Address */\r
+#define CRCCU ((Crccu *)0x40044000U) /**< \brief (CRCCU ) Base Address */\r
+#define UART1 ((Uart *)0x40060600U) /**< \brief (UART1 ) Base Address */\r
+#define PDC_UART1 ((Pdc *)0x40060700U) /**< \brief (PDC_UART1 ) Base Address */\r
+#define HSMCI ((Hsmci *)0x40080000U) /**< \brief (HSMCI ) Base Address */\r
+#define PDC_HSMCI ((Pdc *)0x40080100U) /**< \brief (PDC_HSMCI ) Base Address */\r
+#define UDP ((Udp *)0x40084000U) /**< \brief (UDP ) Base Address */\r
+#define SPI ((Spi *)0x40088000U) /**< \brief (SPI ) Base Address */\r
+#define PDC_SPI ((Pdc *)0x40088100U) /**< \brief (PDC_SPI ) Base Address */\r
+#define TC0 ((Tc *)0x40090000U) /**< \brief (TC0 ) Base Address */\r
+#define PDC_TC0 ((Pdc *)0x40090100U) /**< \brief (PDC_TC0 ) Base Address */\r
+#define TC1 ((Tc *)0x40094000U) /**< \brief (TC1 ) Base Address */\r
+#define PDC_TC1 ((Pdc *)0x40094100U) /**< \brief (PDC_TC1 ) Base Address */\r
+#define TC2 ((Tc *)0x40098000U) /**< \brief (TC2 ) Base Address */\r
+#define USART0 ((Usart *)0x400A0000U) /**< \brief (USART0 ) Base Address */\r
+#define PDC_USART0 ((Pdc *)0x400A0100U) /**< \brief (PDC_USART0) Base Address */\r
+#define USART1 ((Usart *)0x400A4000U) /**< \brief (USART1 ) Base Address */\r
+#define PDC_USART1 ((Pdc *)0x400A4100U) /**< \brief (PDC_USART1) Base Address */\r
+#define TWI0 ((Twi *)0x400A8000U) /**< \brief (TWI0 ) Base Address */\r
+#define PDC_TWI0 ((Pdc *)0x400A8100U) /**< \brief (PDC_TWI0 ) Base Address */\r
+#define TWI1 ((Twi *)0x400AC000U) /**< \brief (TWI1 ) Base Address */\r
+#define PDC_TWI1 ((Pdc *)0x400AC100U) /**< \brief (PDC_TWI1 ) Base Address */\r
+#define AFEC0 ((Afec *)0x400B0000U) /**< \brief (AFEC0 ) Base Address */\r
+#define PDC_AFEC0 ((Pdc *)0x400B0100U) /**< \brief (PDC_AFEC0 ) Base Address */\r
+#define AFEC1 ((Afec *)0x400B4000U) /**< \brief (AFEC1 ) Base Address */\r
+#define PDC_AFEC1 ((Pdc *)0x400B4100U) /**< \brief (PDC_AFEC1 ) Base Address */\r
+#define DACC ((Dacc *)0x400B8000U) /**< \brief (DACC ) Base Address */\r
+#define PDC_DACC ((Pdc *)0x400B8100U) /**< \brief (PDC_DACC ) Base Address */\r
+#define ACC ((Acc *)0x400BC000U) /**< \brief (ACC ) Base Address */\r
+#define DMAC ((Dmac *)0x400C0000U) /**< \brief (DMAC ) Base Address */\r
+#define CMCC ((Cmcc *)0x400C4000U) /**< \brief (CMCC ) Base Address */\r
+#define MATRIX ((Matrix *)0x400E0200U) /**< \brief (MATRIX ) Base Address */\r
+#define PMC ((Pmc *)0x400E0400U) /**< \brief (PMC ) Base Address */\r
+#define UART0 ((Uart *)0x400E0600U) /**< \brief (UART0 ) Base Address */\r
+#define PDC_UART0 ((Pdc *)0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */\r
+#define CHIPID ((Chipid *)0x400E0740U) /**< \brief (CHIPID ) Base Address */\r
+#define EFC ((Efc *)0x400E0A00U) /**< \brief (EFC ) Base Address */\r
+#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */\r
+#define PDC_PIOA ((Pdc *)0x400E0F68U) /**< \brief (PDC_PIOA ) Base Address */\r
+#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */\r
+#define PIOC ((Pio *)0x400E1200U) /**< \brief (PIOC ) Base Address */\r
+#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */\r
+#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */\r
+#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */\r
+#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */\r
+#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */\r
+#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */\r
+#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* PIO DEFINITIONS FOR SAM4E16C */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAM4E16C_pio Peripheral Pio Definitions */\r
+/*@{*/\r
+\r
+#include "pio/sam4e16c.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* MEMORY MAPPING DEFINITIONS FOR SAM4E16C */\r
+/* ************************************************************************** */\r
+\r
+#define IFLASH_SIZE (0x100000u)\r
+#define IFLASH_PAGE_SIZE (512u)\r
+#define IFLASH_LOCK_REGION_SIZE (8192u)\r
+#define IFLASH_NB_OF_PAGES (2048u)\r
+#define IFLASH_NB_OF_LOCK_BITS (128u)\r
+#define IRAM_SIZE (0x20000u)\r
+\r
+#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */\r
+#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */\r
+#define IRAM_ADDR (0x20000000u) /**< Internal RAM base address */\r
+#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */\r
+#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */\r
+#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */\r
+#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */\r
+\r
+/* ************************************************************************** */\r
+/* MISCELLANEOUS DEFINITIONS FOR SAM4E16C */\r
+/* ************************************************************************** */\r
+\r
+#define CHIP_JTAGID (0x05B3703FUL)\r
+#define CHIP_CIDR (0xA3CC0CE0UL)\r
+#define CHIP_EXID (0x00110201UL)\r
+#define NB_CH_AFE0 (6UL)\r
+#define NB_CH_AFE1 (4UL)\r
+\r
+/* ************************************************************************** */\r
+/* ELECTRICAL DEFINITIONS FOR SAM4E16C */\r
+/* ************************************************************************** */\r
+\r
+/* Device characteristics */\r
+#define CHIP_FREQ_SLCK_RC_MIN (20000UL)\r
+#define CHIP_FREQ_SLCK_RC (32000UL)\r
+#define CHIP_FREQ_SLCK_RC_MAX (44000UL)\r
+#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL)\r
+#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL)\r
+#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL)\r
+#define CHIP_FREQ_CPU_MAX (120000000UL)\r
+#define CHIP_FREQ_XTAL_32K (32768UL)\r
+#define CHIP_FREQ_XTAL_12M (12000000UL)\r
+\r
+/* Embedded Flash Write Wait State */\r
+#define CHIP_FLASH_WRITE_WAIT_STATE (6U)\r
+\r
+/* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */\r
+#define CHIP_FREQ_FWS_0 (20000000UL) /**< \brief Maximum operating frequency when FWS is 0 */\r
+#define CHIP_FREQ_FWS_1 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */\r
+#define CHIP_FREQ_FWS_2 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */\r
+#define CHIP_FREQ_FWS_3 (80000000UL) /**< \brief Maximum operating frequency when FWS is 3 */\r
+#define CHIP_FREQ_FWS_4 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */\r
+#define CHIP_FREQ_FWS_5 (123000000UL) /**< \brief Maximum operating frequency when FWS is 5 */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+/*@}*/\r
+\r
+#endif /* _SAM4E16C_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4E16E_\r
+#define _SAM4E16E_\r
+\r
+/** \addtogroup SAM4E16E_definitions SAM4E16E definitions\r
+ This file defines all structures and symbols for SAM4E16E:\r
+ - registers and bitfields\r
+ - peripheral base address\r
+ - peripheral ID\r
+ - PIO definitions\r
+*/\r
+/*@{*/\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#include <stdint.h>\r
+#ifndef __cplusplus\r
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */\r
+#else\r
+typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */\r
+#endif\r
+typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */\r
+typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */\r
+#endif\r
+\r
+/* ************************************************************************** */\r
+/* CMSIS DEFINITIONS FOR SAM4E16E */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAM4E16E_cmsis CMSIS Definitions */\r
+/*@{*/\r
+\r
+/**< Interrupt Number Definition */\r
+typedef enum IRQn\r
+{\r
+/****** Cortex-M4 Processor Exceptions Numbers ******************************/\r
+ NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */\r
+ MemoryManagement_IRQn = -12, /**< 4 Cortex-M4 Memory Management Interrupt */\r
+ BusFault_IRQn = -11, /**< 5 Cortex-M4 Bus Fault Interrupt */\r
+ UsageFault_IRQn = -10, /**< 6 Cortex-M4 Usage Fault Interrupt */\r
+ SVCall_IRQn = -5, /**< 11 Cortex-M4 SV Call Interrupt */\r
+ DebugMonitor_IRQn = -4, /**< 12 Cortex-M4 Debug Monitor Interrupt */\r
+ PendSV_IRQn = -2, /**< 14 Cortex-M4 Pend SV Interrupt */\r
+ SysTick_IRQn = -1, /**< 15 Cortex-M4 System Tick Interrupt */\r
+/****** SAM4E16E specific Interrupt Numbers *********************************/\r
+\r
+ SUPC_IRQn = 0, /**< 0 SAM4E16E Supply Controller (SUPC) */\r
+ RSTC_IRQn = 1, /**< 1 SAM4E16E Reset Controller (RSTC) */\r
+ RTC_IRQn = 2, /**< 2 SAM4E16E Real Time Clock (RTC) */\r
+ RTT_IRQn = 3, /**< 3 SAM4E16E Real Time Timer (RTT) */\r
+ WDT_IRQn = 4, /**< 4 SAM4E16E Watchdog/Dual Watchdog Timer (WDT) */\r
+ PMC_IRQn = 5, /**< 5 SAM4E16E Power Management Controller (PMC) */\r
+ EFC_IRQn = 6, /**< 6 SAM4E16E Enhanced Embedded Flash Controller (EFC) */\r
+ UART0_IRQn = 7, /**< 7 SAM4E16E UART 0 (UART0) */\r
+ PIOA_IRQn = 9, /**< 9 SAM4E16E Parallel I/O Controller A (PIOA) */\r
+ PIOB_IRQn = 10, /**< 10 SAM4E16E Parallel I/O Controller B (PIOB) */\r
+ PIOC_IRQn = 11, /**< 11 SAM4E16E Parallel I/O Controller C (PIOC) */\r
+ PIOD_IRQn = 12, /**< 12 SAM4E16E Parallel I/O Controller D (PIOD) */\r
+ PIOE_IRQn = 13, /**< 13 SAM4E16E Parallel I/O Controller E (PIOE) */\r
+ USART0_IRQn = 14, /**< 14 SAM4E16E USART 0 (USART0) */\r
+ USART1_IRQn = 15, /**< 15 SAM4E16E USART 1 (USART1) */\r
+ HSMCI_IRQn = 16, /**< 16 SAM4E16E Multimedia Card Interface (HSMCI) */\r
+ TWI0_IRQn = 17, /**< 17 SAM4E16E Two Wire Interface 0 (TWI0) */\r
+ TWI1_IRQn = 18, /**< 18 SAM4E16E Two Wire Interface 1 (TWI1) */\r
+ SPI_IRQn = 19, /**< 19 SAM4E16E Serial Peripheral Interface (SPI) */\r
+ DMAC_IRQn = 20, /**< 20 SAM4E16E DMAC (DMAC) */\r
+ TC0_IRQn = 21, /**< 21 SAM4E16E Timer/Counter 0 (TC0) */\r
+ TC1_IRQn = 22, /**< 22 SAM4E16E Timer/Counter 1 (TC1) */\r
+ TC2_IRQn = 23, /**< 23 SAM4E16E Timer/Counter 2 (TC2) */\r
+ TC3_IRQn = 24, /**< 24 SAM4E16E Timer/Counter 3 (TC3) */\r
+ TC4_IRQn = 25, /**< 25 SAM4E16E Timer/Counter 4 (TC4) */\r
+ TC5_IRQn = 26, /**< 26 SAM4E16E Timer/Counter 5 (TC5) */\r
+ TC6_IRQn = 27, /**< 27 SAM4E16E Timer/Counter 6 (TC6) */\r
+ TC7_IRQn = 28, /**< 28 SAM4E16E Timer/Counter 7 (TC7) */\r
+ TC8_IRQn = 29, /**< 29 SAM4E16E Timer/Counter 8 (TC8) */\r
+ AFEC0_IRQn = 30, /**< 30 SAM4E16E Analog Front End 0 (AFEC0) */\r
+ AFEC1_IRQn = 31, /**< 31 SAM4E16E Analog Front End 1 (AFEC1) */\r
+ DACC_IRQn = 32, /**< 32 SAM4E16E Digital To Analog Converter (DACC) */\r
+ ACC_IRQn = 33, /**< 33 SAM4E16E Analog Comparator (ACC) */\r
+ ARM_IRQn = 34, /**< 34 SAM4E16E FPU signals : FPIXC, FPOFC, FPUFC, FPIOC, FPDZC, FPIDC, FPIXC (ARM) */\r
+ UDP_IRQn = 35, /**< 35 SAM4E16E USB DEVICE (UDP) */\r
+ PWM_IRQn = 36, /**< 36 SAM4E16E PWM (PWM) */\r
+ CAN0_IRQn = 37, /**< 37 SAM4E16E CAN0 (CAN0) */\r
+ CAN1_IRQn = 38, /**< 38 SAM4E16E CAN1 (CAN1) */\r
+ AES_IRQn = 39, /**< 39 SAM4E16E AES (AES) */\r
+ GMAC_IRQn = 44, /**< 44 SAM4E16E EMAC (GMAC) */\r
+ UART1_IRQn = 45, /**< 45 SAM4E16E UART (UART1) */\r
+\r
+ PERIPH_COUNT_IRQn = 46 /**< Number of peripheral IDs */\r
+} IRQn_Type;\r
+\r
+typedef struct _DeviceVectors\r
+{\r
+ /* Stack pointer */\r
+ void* pvStack;\r
+\r
+ /* Cortex-M handlers */\r
+ void* pfnReset_Handler;\r
+ void* pfnNMI_Handler;\r
+ void* pfnHardFault_Handler;\r
+ void* pfnMemManage_Handler;\r
+ void* pfnBusFault_Handler;\r
+ void* pfnUsageFault_Handler;\r
+ void* pfnReserved1_Handler;\r
+ void* pfnReserved2_Handler;\r
+ void* pfnReserved3_Handler;\r
+ void* pfnReserved4_Handler;\r
+ void* pfnSVC_Handler;\r
+ void* pfnDebugMon_Handler;\r
+ void* pfnReserved5_Handler;\r
+ void* pfnPendSV_Handler;\r
+ void* pfnSysTick_Handler;\r
+\r
+ /* Peripheral handlers */\r
+ void* pfnSUPC_Handler; /* 0 Supply Controller */\r
+ void* pfnRSTC_Handler; /* 1 Reset Controller */\r
+ void* pfnRTC_Handler; /* 2 Real Time Clock */\r
+ void* pfnRTT_Handler; /* 3 Real Time Timer */\r
+ void* pfnWDT_Handler; /* 4 Watchdog/Dual Watchdog Timer */\r
+ void* pfnPMC_Handler; /* 5 Power Management Controller */\r
+ void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */\r
+ void* pfnUART0_Handler; /* 7 UART 0 */\r
+ void* pvReserved8;\r
+ void* pfnPIOA_Handler; /* 9 Parallel I/O Controller A */\r
+ void* pfnPIOB_Handler; /* 10 Parallel I/O Controller B */\r
+ void* pfnPIOC_Handler; /* 11 Parallel I/O Controller C */\r
+ void* pfnPIOD_Handler; /* 12 Parallel I/O Controller D */\r
+ void* pfnPIOE_Handler; /* 13 Parallel I/O Controller E */\r
+ void* pfnUSART0_Handler; /* 14 USART 0 */\r
+ void* pfnUSART1_Handler; /* 15 USART 1 */\r
+ void* pfnHSMCI_Handler; /* 16 Multimedia Card Interface */\r
+ void* pfnTWI0_Handler; /* 17 Two Wire Interface 0 */\r
+ void* pfnTWI1_Handler; /* 18 Two Wire Interface 1 */\r
+ void* pfnSPI_Handler; /* 19 Serial Peripheral Interface */\r
+ void* pfnDMAC_Handler; /* 20 DMAC */\r
+ void* pfnTC0_Handler; /* 21 Timer/Counter 0 */\r
+ void* pfnTC1_Handler; /* 22 Timer/Counter 1 */\r
+ void* pfnTC2_Handler; /* 23 Timer/Counter 2 */\r
+ void* pfnTC3_Handler; /* 24 Timer/Counter 3 */\r
+ void* pfnTC4_Handler; /* 25 Timer/Counter 4 */\r
+ void* pfnTC5_Handler; /* 26 Timer/Counter 5 */\r
+ void* pfnTC6_Handler; /* 27 Timer/Counter 6 */\r
+ void* pfnTC7_Handler; /* 28 Timer/Counter 7 */\r
+ void* pfnTC8_Handler; /* 29 Timer/Counter 8 */\r
+ void* pfnAFEC0_Handler; /* 30 Analog Front End 0 */\r
+ void* pfnAFEC1_Handler; /* 31 Analog Front End 1 */\r
+ void* pfnDACC_Handler; /* 32 Digital To Analog Converter */\r
+ void* pfnACC_Handler; /* 33 Analog Comparator */\r
+ void* pfnARM_Handler; /* 34 FPU signals : FPIXC, FPOFC, FPUFC, FPIOC, FPDZC, FPIDC, FPIXC */\r
+ void* pfnUDP_Handler; /* 35 USB DEVICE */\r
+ void* pfnPWM_Handler; /* 36 PWM */\r
+ void* pfnCAN0_Handler; /* 37 CAN0 */\r
+ void* pfnCAN1_Handler; /* 38 CAN1 */\r
+ void* pfnAES_Handler; /* 39 AES */\r
+ void* pvReserved40;\r
+ void* pvReserved41;\r
+ void* pvReserved42;\r
+ void* pvReserved43;\r
+ void* pfnGMAC_Handler; /* 44 EMAC */\r
+ void* pfnUART1_Handler; /* 45 UART */\r
+} DeviceVectors;\r
+\r
+/* Cortex-M4 core handlers */\r
+void Reset_Handler ( void );\r
+void NMI_Handler ( void );\r
+void HardFault_Handler ( void );\r
+void MemManage_Handler ( void );\r
+void BusFault_Handler ( void );\r
+void UsageFault_Handler ( void );\r
+void SVC_Handler ( void );\r
+void DebugMon_Handler ( void );\r
+void PendSV_Handler ( void );\r
+void SysTick_Handler ( void );\r
+\r
+/* Peripherals handlers */\r
+void ACC_Handler ( void );\r
+void AES_Handler ( void );\r
+void AFEC0_Handler ( void );\r
+void AFEC1_Handler ( void );\r
+void ARM_Handler ( void );\r
+void CAN0_Handler ( void );\r
+void CAN1_Handler ( void );\r
+void DACC_Handler ( void );\r
+void DMAC_Handler ( void );\r
+void EFC_Handler ( void );\r
+void GMAC_Handler ( void );\r
+void HSMCI_Handler ( void );\r
+void PIOA_Handler ( void );\r
+void PIOB_Handler ( void );\r
+void PIOC_Handler ( void );\r
+void PIOD_Handler ( void );\r
+void PIOE_Handler ( void );\r
+void PMC_Handler ( void );\r
+void PWM_Handler ( void );\r
+void RSTC_Handler ( void );\r
+void RTC_Handler ( void );\r
+void RTT_Handler ( void );\r
+void SPI_Handler ( void );\r
+void SUPC_Handler ( void );\r
+void TC0_Handler ( void );\r
+void TC1_Handler ( void );\r
+void TC2_Handler ( void );\r
+void TC3_Handler ( void );\r
+void TC4_Handler ( void );\r
+void TC5_Handler ( void );\r
+void TC6_Handler ( void );\r
+void TC7_Handler ( void );\r
+void TC8_Handler ( void );\r
+void TWI0_Handler ( void );\r
+void TWI1_Handler ( void );\r
+void UART0_Handler ( void );\r
+void UART1_Handler ( void );\r
+void UDP_Handler ( void );\r
+void USART0_Handler ( void );\r
+void USART1_Handler ( void );\r
+void WDT_Handler ( void );\r
+\r
+/**\r
+ * \brief Configuration of the Cortex-M4 Processor and Core Peripherals\r
+ */\r
+\r
+#define __CM4_REV 0x0000 /**< SAM4E16E core revision number ([15:8] revision number, [7:0] patch number) */\r
+#define __MPU_PRESENT 0 /**< SAM4E16E does not provide a MPU */\r
+#define __FPU_PRESENT 1 /**< SAM4E16E does provide a FPU */\r
+#define __NVIC_PRIO_BITS 4 /**< SAM4E16E uses 4 Bits for the Priority Levels */\r
+#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */\r
+\r
+/*\r
+ * \brief CMSIS includes\r
+ */\r
+\r
+#include <core_cm4.h>\r
+#if !defined DONT_USE_CMSIS_INIT\r
+#include "system_sam4e.h"\r
+#endif /* DONT_USE_CMSIS_INIT */\r
+\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** SOFTWARE PERIPHERAL API DEFINITION FOR SAM4E16E */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAM4E16E_api Peripheral Software API */\r
+/*@{*/\r
+\r
+#include "component/acc.h"\r
+#include "component/aes.h"\r
+#include "component/afec.h"\r
+#include "component/can.h"\r
+#include "component/chipid.h"\r
+#include "component/cmcc.h"\r
+#include "component/crccu.h"\r
+#include "component/dacc.h"\r
+#include "component/dmac.h"\r
+#include "component/efc.h"\r
+#include "component/gmac.h"\r
+#include "component/gpbr.h"\r
+#include "component/hsmci.h"\r
+#include "component/matrix.h"\r
+#include "component/pdc.h"\r
+#include "component/pio.h"\r
+#include "component/pmc.h"\r
+#include "component/pwm.h"\r
+#include "component/rstc.h"\r
+#include "component/rswdt.h"\r
+#include "component/rtc.h"\r
+#include "component/rtt.h"\r
+#include "component/smc.h"\r
+#include "component/spi.h"\r
+#include "component/supc.h"\r
+#include "component/tc.h"\r
+#include "component/twi.h"\r
+#include "component/uart.h"\r
+#include "component/udp.h"\r
+#include "component/usart.h"\r
+#include "component/wdt.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* REGISTER ACCESS DEFINITIONS FOR SAM4E16E */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAM4E16E_reg Registers Access Definitions */\r
+/*@{*/\r
+\r
+#include "instance/pwm.h"\r
+#include "instance/aes.h"\r
+#include "instance/can0.h"\r
+#include "instance/can1.h"\r
+#include "instance/gmac.h"\r
+#include "instance/crccu.h"\r
+#include "instance/smc.h"\r
+#include "instance/uart1.h"\r
+#include "instance/hsmci.h"\r
+#include "instance/udp.h"\r
+#include "instance/spi.h"\r
+#include "instance/tc0.h"\r
+#include "instance/tc1.h"\r
+#include "instance/tc2.h"\r
+#include "instance/usart0.h"\r
+#include "instance/usart1.h"\r
+#include "instance/twi0.h"\r
+#include "instance/twi1.h"\r
+#include "instance/afec0.h"\r
+#include "instance/afec1.h"\r
+#include "instance/dacc.h"\r
+#include "instance/acc.h"\r
+#include "instance/dmac.h"\r
+#include "instance/cmcc.h"\r
+#include "instance/matrix.h"\r
+#include "instance/pmc.h"\r
+#include "instance/uart0.h"\r
+#include "instance/chipid.h"\r
+#include "instance/efc.h"\r
+#include "instance/pioa.h"\r
+#include "instance/piob.h"\r
+#include "instance/pioc.h"\r
+#include "instance/piod.h"\r
+#include "instance/pioe.h"\r
+#include "instance/rstc.h"\r
+#include "instance/supc.h"\r
+#include "instance/rtt.h"\r
+#include "instance/wdt.h"\r
+#include "instance/rtc.h"\r
+#include "instance/gpbr.h"\r
+#include "instance/rswdt.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* PERIPHERAL ID DEFINITIONS FOR SAM4E16E */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAM4E16E_id Peripheral Ids Definitions */\r
+/*@{*/\r
+\r
+#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */\r
+#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */\r
+#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */\r
+#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */\r
+#define ID_WDT ( 4) /**< \brief Watchdog/Dual Watchdog Timer (WDT) */\r
+#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */\r
+#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */\r
+#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */\r
+#define ID_SMC ( 8) /**< \brief Static Memory Controller (SMC) */\r
+#define ID_PIOA ( 9) /**< \brief Parallel I/O Controller A (PIOA) */\r
+#define ID_PIOB (10) /**< \brief Parallel I/O Controller B (PIOB) */\r
+#define ID_PIOC (11) /**< \brief Parallel I/O Controller C (PIOC) */\r
+#define ID_PIOD (12) /**< \brief Parallel I/O Controller D (PIOD) */\r
+#define ID_PIOE (13) /**< \brief Parallel I/O Controller E (PIOE) */\r
+#define ID_USART0 (14) /**< \brief USART 0 (USART0) */\r
+#define ID_USART1 (15) /**< \brief USART 1 (USART1) */\r
+#define ID_HSMCI (16) /**< \brief Multimedia Card Interface (HSMCI) */\r
+#define ID_TWI0 (17) /**< \brief Two Wire Interface 0 (TWI0) */\r
+#define ID_TWI1 (18) /**< \brief Two Wire Interface 1 (TWI1) */\r
+#define ID_SPI (19) /**< \brief Serial Peripheral Interface (SPI) */\r
+#define ID_DMAC (20) /**< \brief DMAC (DMAC) */\r
+#define ID_TC0 (21) /**< \brief Timer/Counter 0 (TC0) */\r
+#define ID_TC1 (22) /**< \brief Timer/Counter 1 (TC1) */\r
+#define ID_TC2 (23) /**< \brief Timer/Counter 2 (TC2) */\r
+#define ID_TC3 (24) /**< \brief Timer/Counter 3 (TC3) */\r
+#define ID_TC4 (25) /**< \brief Timer/Counter 4 (TC4) */\r
+#define ID_TC5 (26) /**< \brief Timer/Counter 5 (TC5) */\r
+#define ID_TC6 (27) /**< \brief Timer/Counter 6 (TC6) */\r
+#define ID_TC7 (28) /**< \brief Timer/Counter 7 (TC7) */\r
+#define ID_TC8 (29) /**< \brief Timer/Counter 8 (TC8) */\r
+#define ID_AFEC0 (30) /**< \brief Analog Front End 0 (AFEC0) */\r
+#define ID_AFEC1 (31) /**< \brief Analog Front End 1 (AFEC1) */\r
+#define ID_DACC (32) /**< \brief Digital To Analog Converter (DACC) */\r
+#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */\r
+#define ID_ARM (34) /**< \brief FPU signals : FPIXC, FPOFC, FPUFC, FPIOC, FPDZC, FPIDC, FPIXC (ARM) */\r
+#define ID_UDP (35) /**< \brief USB DEVICE (UDP) */\r
+#define ID_PWM (36) /**< \brief PWM (PWM) */\r
+#define ID_CAN0 (37) /**< \brief CAN0 (CAN0) */\r
+#define ID_CAN1 (38) /**< \brief CAN1 (CAN1) */\r
+#define ID_AES (39) /**< \brief AES (AES) */\r
+#define ID_GMAC (44) /**< \brief EMAC (GMAC) */\r
+#define ID_UART1 (45) /**< \brief UART (UART1) */\r
+\r
+#define ID_PERIPH_COUNT (46) /**< \brief Number of peripheral IDs */\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* BASE ADDRESS DEFINITIONS FOR SAM4E16E */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAM4E16E_base Peripheral Base Address Definitions */\r
+/*@{*/\r
+\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define PWM (0x40000000U) /**< \brief (PWM ) Base Address */\r
+#define PDC_PWM (0x40000100U) /**< \brief (PDC_PWM ) Base Address */\r
+#define AES (0x40004000U) /**< \brief (AES ) Base Address */\r
+#define CAN0 (0x40010000U) /**< \brief (CAN0 ) Base Address */\r
+#define CAN1 (0x40014000U) /**< \brief (CAN1 ) Base Address */\r
+#define GMAC (0x40034000U) /**< \brief (GMAC ) Base Address */\r
+#define CRCCU (0x40044000U) /**< \brief (CRCCU ) Base Address */\r
+#define SMC (0x40060000U) /**< \brief (SMC ) Base Address */\r
+#define UART1 (0x40060600U) /**< \brief (UART1 ) Base Address */\r
+#define PDC_UART1 (0x40060700U) /**< \brief (PDC_UART1 ) Base Address */\r
+#define HSMCI (0x40080000U) /**< \brief (HSMCI ) Base Address */\r
+#define PDC_HSMCI (0x40080100U) /**< \brief (PDC_HSMCI ) Base Address */\r
+#define UDP (0x40084000U) /**< \brief (UDP ) Base Address */\r
+#define SPI (0x40088000U) /**< \brief (SPI ) Base Address */\r
+#define PDC_SPI (0x40088100U) /**< \brief (PDC_SPI ) Base Address */\r
+#define TC0 (0x40090000U) /**< \brief (TC0 ) Base Address */\r
+#define PDC_TC0 (0x40090100U) /**< \brief (PDC_TC0 ) Base Address */\r
+#define TC1 (0x40094000U) /**< \brief (TC1 ) Base Address */\r
+#define PDC_TC1 (0x40094100U) /**< \brief (PDC_TC1 ) Base Address */\r
+#define TC2 (0x40098000U) /**< \brief (TC2 ) Base Address */\r
+#define USART0 (0x400A0000U) /**< \brief (USART0 ) Base Address */\r
+#define PDC_USART0 (0x400A0100U) /**< \brief (PDC_USART0) Base Address */\r
+#define USART1 (0x400A4000U) /**< \brief (USART1 ) Base Address */\r
+#define PDC_USART1 (0x400A4100U) /**< \brief (PDC_USART1) Base Address */\r
+#define TWI0 (0x400A8000U) /**< \brief (TWI0 ) Base Address */\r
+#define PDC_TWI0 (0x400A8100U) /**< \brief (PDC_TWI0 ) Base Address */\r
+#define TWI1 (0x400AC000U) /**< \brief (TWI1 ) Base Address */\r
+#define PDC_TWI1 (0x400AC100U) /**< \brief (PDC_TWI1 ) Base Address */\r
+#define AFEC0 (0x400B0000U) /**< \brief (AFEC0 ) Base Address */\r
+#define PDC_AFEC0 (0x400B0100U) /**< \brief (PDC_AFEC0 ) Base Address */\r
+#define AFEC1 (0x400B4000U) /**< \brief (AFEC1 ) Base Address */\r
+#define PDC_AFEC1 (0x400B4100U) /**< \brief (PDC_AFEC1 ) Base Address */\r
+#define DACC (0x400B8000U) /**< \brief (DACC ) Base Address */\r
+#define PDC_DACC (0x400B8100U) /**< \brief (PDC_DACC ) Base Address */\r
+#define ACC (0x400BC000U) /**< \brief (ACC ) Base Address */\r
+#define DMAC (0x400C0000U) /**< \brief (DMAC ) Base Address */\r
+#define CMCC (0x400C4000U) /**< \brief (CMCC ) Base Address */\r
+#define MATRIX (0x400E0200U) /**< \brief (MATRIX ) Base Address */\r
+#define PMC (0x400E0400U) /**< \brief (PMC ) Base Address */\r
+#define UART0 (0x400E0600U) /**< \brief (UART0 ) Base Address */\r
+#define PDC_UART0 (0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */\r
+#define CHIPID (0x400E0740U) /**< \brief (CHIPID ) Base Address */\r
+#define EFC (0x400E0A00U) /**< \brief (EFC ) Base Address */\r
+#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */\r
+#define PDC_PIOA (0x400E0F68U) /**< \brief (PDC_PIOA ) Base Address */\r
+#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */\r
+#define PIOC (0x400E1200U) /**< \brief (PIOC ) Base Address */\r
+#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */\r
+#define PIOE (0x400E1600U) /**< \brief (PIOE ) Base Address */\r
+#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */\r
+#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */\r
+#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */\r
+#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */\r
+#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */\r
+#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */\r
+#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */\r
+#else\r
+#define PWM ((Pwm *)0x40000000U) /**< \brief (PWM ) Base Address */\r
+#define PDC_PWM ((Pdc *)0x40000100U) /**< \brief (PDC_PWM ) Base Address */\r
+#define AES ((Aes *)0x40004000U) /**< \brief (AES ) Base Address */\r
+#define CAN0 ((Can *)0x40010000U) /**< \brief (CAN0 ) Base Address */\r
+#define CAN1 ((Can *)0x40014000U) /**< \brief (CAN1 ) Base Address */\r
+#define GMAC ((Gmac *)0x40034000U) /**< \brief (GMAC ) Base Address */\r
+#define CRCCU ((Crccu *)0x40044000U) /**< \brief (CRCCU ) Base Address */\r
+#define SMC ((Smc *)0x40060000U) /**< \brief (SMC ) Base Address */\r
+#define UART1 ((Uart *)0x40060600U) /**< \brief (UART1 ) Base Address */\r
+#define PDC_UART1 ((Pdc *)0x40060700U) /**< \brief (PDC_UART1 ) Base Address */\r
+#define HSMCI ((Hsmci *)0x40080000U) /**< \brief (HSMCI ) Base Address */\r
+#define PDC_HSMCI ((Pdc *)0x40080100U) /**< \brief (PDC_HSMCI ) Base Address */\r
+#define UDP ((Udp *)0x40084000U) /**< \brief (UDP ) Base Address */\r
+#define SPI ((Spi *)0x40088000U) /**< \brief (SPI ) Base Address */\r
+#define PDC_SPI ((Pdc *)0x40088100U) /**< \brief (PDC_SPI ) Base Address */\r
+#define TC0 ((Tc *)0x40090000U) /**< \brief (TC0 ) Base Address */\r
+#define PDC_TC0 ((Pdc *)0x40090100U) /**< \brief (PDC_TC0 ) Base Address */\r
+#define TC1 ((Tc *)0x40094000U) /**< \brief (TC1 ) Base Address */\r
+#define PDC_TC1 ((Pdc *)0x40094100U) /**< \brief (PDC_TC1 ) Base Address */\r
+#define TC2 ((Tc *)0x40098000U) /**< \brief (TC2 ) Base Address */\r
+#define USART0 ((Usart *)0x400A0000U) /**< \brief (USART0 ) Base Address */\r
+#define PDC_USART0 ((Pdc *)0x400A0100U) /**< \brief (PDC_USART0) Base Address */\r
+#define USART1 ((Usart *)0x400A4000U) /**< \brief (USART1 ) Base Address */\r
+#define PDC_USART1 ((Pdc *)0x400A4100U) /**< \brief (PDC_USART1) Base Address */\r
+#define TWI0 ((Twi *)0x400A8000U) /**< \brief (TWI0 ) Base Address */\r
+#define PDC_TWI0 ((Pdc *)0x400A8100U) /**< \brief (PDC_TWI0 ) Base Address */\r
+#define TWI1 ((Twi *)0x400AC000U) /**< \brief (TWI1 ) Base Address */\r
+#define PDC_TWI1 ((Pdc *)0x400AC100U) /**< \brief (PDC_TWI1 ) Base Address */\r
+#define AFEC0 ((Afec *)0x400B0000U) /**< \brief (AFEC0 ) Base Address */\r
+#define PDC_AFEC0 ((Pdc *)0x400B0100U) /**< \brief (PDC_AFEC0 ) Base Address */\r
+#define AFEC1 ((Afec *)0x400B4000U) /**< \brief (AFEC1 ) Base Address */\r
+#define PDC_AFEC1 ((Pdc *)0x400B4100U) /**< \brief (PDC_AFEC1 ) Base Address */\r
+#define DACC ((Dacc *)0x400B8000U) /**< \brief (DACC ) Base Address */\r
+#define PDC_DACC ((Pdc *)0x400B8100U) /**< \brief (PDC_DACC ) Base Address */\r
+#define ACC ((Acc *)0x400BC000U) /**< \brief (ACC ) Base Address */\r
+#define DMAC ((Dmac *)0x400C0000U) /**< \brief (DMAC ) Base Address */\r
+#define CMCC ((Cmcc *)0x400C4000U) /**< \brief (CMCC ) Base Address */\r
+#define MATRIX ((Matrix *)0x400E0200U) /**< \brief (MATRIX ) Base Address */\r
+#define PMC ((Pmc *)0x400E0400U) /**< \brief (PMC ) Base Address */\r
+#define UART0 ((Uart *)0x400E0600U) /**< \brief (UART0 ) Base Address */\r
+#define PDC_UART0 ((Pdc *)0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */\r
+#define CHIPID ((Chipid *)0x400E0740U) /**< \brief (CHIPID ) Base Address */\r
+#define EFC ((Efc *)0x400E0A00U) /**< \brief (EFC ) Base Address */\r
+#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */\r
+#define PDC_PIOA ((Pdc *)0x400E0F68U) /**< \brief (PDC_PIOA ) Base Address */\r
+#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */\r
+#define PIOC ((Pio *)0x400E1200U) /**< \brief (PIOC ) Base Address */\r
+#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */\r
+#define PIOE ((Pio *)0x400E1600U) /**< \brief (PIOE ) Base Address */\r
+#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */\r
+#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */\r
+#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */\r
+#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */\r
+#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */\r
+#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */\r
+#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* PIO DEFINITIONS FOR SAM4E16E */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAM4E16E_pio Peripheral Pio Definitions */\r
+/*@{*/\r
+\r
+#include "pio/sam4e16e.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* MEMORY MAPPING DEFINITIONS FOR SAM4E16E */\r
+/* ************************************************************************** */\r
+\r
+#define IFLASH_SIZE (0x100000u)\r
+#define IFLASH_PAGE_SIZE (512u)\r
+#define IFLASH_LOCK_REGION_SIZE (8192u)\r
+#define IFLASH_NB_OF_PAGES (2048u)\r
+#define IFLASH_NB_OF_LOCK_BITS (128u)\r
+#define IRAM_SIZE (0x20000u)\r
+\r
+#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */\r
+#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */\r
+#define IRAM_ADDR (0x20000000u) /**< Internal RAM base address */\r
+#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */\r
+#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */\r
+#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */\r
+#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */\r
+\r
+/* ************************************************************************** */\r
+/* MISCELLANEOUS DEFINITIONS FOR SAM4E16E */\r
+/* ************************************************************************** */\r
+\r
+#define CHIP_JTAGID (0x05B3703FUL)\r
+#define CHIP_CIDR (0xA3CC0CE0UL)\r
+#define CHIP_EXID (0x00120200UL)\r
+#define NB_CH_AFE0 (16UL)\r
+#define NB_CH_AFE1 (8UL)\r
+\r
+/* ************************************************************************** */\r
+/* ELECTRICAL DEFINITIONS FOR SAM4E16E */\r
+/* ************************************************************************** */\r
+\r
+/* Device characteristics */\r
+#define CHIP_FREQ_SLCK_RC_MIN (20000UL)\r
+#define CHIP_FREQ_SLCK_RC (32000UL)\r
+#define CHIP_FREQ_SLCK_RC_MAX (44000UL)\r
+#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL)\r
+#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL)\r
+#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL)\r
+#define CHIP_FREQ_CPU_MAX (120000000UL)\r
+#define CHIP_FREQ_XTAL_32K (32768UL)\r
+#define CHIP_FREQ_XTAL_12M (12000000UL)\r
+\r
+/* Embedded Flash Write Wait State */\r
+#define CHIP_FLASH_WRITE_WAIT_STATE (6U)\r
+\r
+/* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */\r
+#define CHIP_FREQ_FWS_0 (20000000UL) /**< \brief Maximum operating frequency when FWS is 0 */\r
+#define CHIP_FREQ_FWS_1 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */\r
+#define CHIP_FREQ_FWS_2 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */\r
+#define CHIP_FREQ_FWS_3 (80000000UL) /**< \brief Maximum operating frequency when FWS is 3 */\r
+#define CHIP_FREQ_FWS_4 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */\r
+#define CHIP_FREQ_FWS_5 (123000000UL) /**< \brief Maximum operating frequency when FWS is 5 */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+/*@}*/\r
+\r
+#endif /* _SAM4E16E_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4E8C_\r
+#define _SAM4E8C_\r
+\r
+/** \addtogroup SAM4E8C_definitions SAM4E8C definitions\r
+ This file defines all structures and symbols for SAM4E8C:\r
+ - registers and bitfields\r
+ - peripheral base address\r
+ - peripheral ID\r
+ - PIO definitions\r
+*/\r
+/*@{*/\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#include <stdint.h>\r
+#ifndef __cplusplus\r
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */\r
+#else\r
+typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */\r
+#endif\r
+typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */\r
+typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */\r
+#endif\r
+\r
+/* ************************************************************************** */\r
+/* CMSIS DEFINITIONS FOR SAM4E8C */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAM4E8C_cmsis CMSIS Definitions */\r
+/*@{*/\r
+\r
+/**< Interrupt Number Definition */\r
+typedef enum IRQn\r
+{\r
+/****** Cortex-M4 Processor Exceptions Numbers ******************************/\r
+ NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */\r
+ MemoryManagement_IRQn = -12, /**< 4 Cortex-M4 Memory Management Interrupt */\r
+ BusFault_IRQn = -11, /**< 5 Cortex-M4 Bus Fault Interrupt */\r
+ UsageFault_IRQn = -10, /**< 6 Cortex-M4 Usage Fault Interrupt */\r
+ SVCall_IRQn = -5, /**< 11 Cortex-M4 SV Call Interrupt */\r
+ DebugMonitor_IRQn = -4, /**< 12 Cortex-M4 Debug Monitor Interrupt */\r
+ PendSV_IRQn = -2, /**< 14 Cortex-M4 Pend SV Interrupt */\r
+ SysTick_IRQn = -1, /**< 15 Cortex-M4 System Tick Interrupt */\r
+/****** SAM4E8C specific Interrupt Numbers *********************************/\r
+\r
+ SUPC_IRQn = 0, /**< 0 SAM4E8C Supply Controller (SUPC) */\r
+ RSTC_IRQn = 1, /**< 1 SAM4E8C Reset Controller (RSTC) */\r
+ RTC_IRQn = 2, /**< 2 SAM4E8C Real Time Clock (RTC) */\r
+ RTT_IRQn = 3, /**< 3 SAM4E8C Real Time Timer (RTT) */\r
+ WDT_IRQn = 4, /**< 4 SAM4E8C Watchdog/Dual Watchdog Timer (WDT) */\r
+ PMC_IRQn = 5, /**< 5 SAM4E8C Power Management Controller (PMC) */\r
+ EFC_IRQn = 6, /**< 6 SAM4E8C Enhanced Embedded Flash Controller (EFC) */\r
+ UART0_IRQn = 7, /**< 7 SAM4E8C UART 0 (UART0) */\r
+ PIOA_IRQn = 9, /**< 9 SAM4E8C Parallel I/O Controller A (PIOA) */\r
+ PIOB_IRQn = 10, /**< 10 SAM4E8C Parallel I/O Controller B (PIOB) */\r
+ PIOC_IRQn = 11, /**< 11 SAM4E8C Parallel I/O Controller C (PIOC) */\r
+ USART0_IRQn = 14, /**< 14 SAM4E8C USART 0 (USART0) */\r
+ USART1_IRQn = 15, /**< 15 SAM4E8C USART 1 (USART1) */\r
+ HSMCI_IRQn = 16, /**< 16 SAM4E8C Multimedia Card Interface (HSMCI) */\r
+ TWI0_IRQn = 17, /**< 17 SAM4E8C Two Wire Interface 0 (TWI0) */\r
+ TWI1_IRQn = 18, /**< 18 SAM4E8C Two Wire Interface 1 (TWI1) */\r
+ SPI_IRQn = 19, /**< 19 SAM4E8C Serial Peripheral Interface (SPI) */\r
+ DMAC_IRQn = 20, /**< 20 SAM4E8C DMAC (DMAC) */\r
+ TC0_IRQn = 21, /**< 21 SAM4E8C Timer/Counter 0 (TC0) */\r
+ TC1_IRQn = 22, /**< 22 SAM4E8C Timer/Counter 1 (TC1) */\r
+ TC2_IRQn = 23, /**< 23 SAM4E8C Timer/Counter 2 (TC2) */\r
+ TC3_IRQn = 24, /**< 24 SAM4E8C Timer/Counter 3 (TC3) */\r
+ TC4_IRQn = 25, /**< 25 SAM4E8C Timer/Counter 4 (TC4) */\r
+ TC5_IRQn = 26, /**< 26 SAM4E8C Timer/Counter 5 (TC5) */\r
+ TC6_IRQn = 27, /**< 27 SAM4E8C Timer/Counter 6 (TC6) */\r
+ TC7_IRQn = 28, /**< 28 SAM4E8C Timer/Counter 7 (TC7) */\r
+ TC8_IRQn = 29, /**< 29 SAM4E8C Timer/Counter 8 (TC8) */\r
+ AFEC0_IRQn = 30, /**< 30 SAM4E8C Analog Front End 0 (AFEC0) */\r
+ AFEC1_IRQn = 31, /**< 31 SAM4E8C Analog Front End 1 (AFEC1) */\r
+ DACC_IRQn = 32, /**< 32 SAM4E8C Digital To Analog Converter (DACC) */\r
+ ACC_IRQn = 33, /**< 33 SAM4E8C Analog Comparator (ACC) */\r
+ ARM_IRQn = 34, /**< 34 SAM4E8C FPU signals : FPIXC, FPOFC, FPUFC, FPIOC, FPDZC, FPIDC, FPIXC (ARM) */\r
+ UDP_IRQn = 35, /**< 35 SAM4E8C USB DEVICE (UDP) */\r
+ PWM_IRQn = 36, /**< 36 SAM4E8C PWM (PWM) */\r
+ CAN0_IRQn = 37, /**< 37 SAM4E8C CAN0 (CAN0) */\r
+ CAN1_IRQn = 38, /**< 38 SAM4E8C CAN1 (CAN1) */\r
+ AES_IRQn = 39, /**< 39 SAM4E8C AES (AES) */\r
+ UART1_IRQn = 45, /**< 45 SAM4E8C UART (UART1) */\r
+\r
+ PERIPH_COUNT_IRQn = 46 /**< Number of peripheral IDs */\r
+} IRQn_Type;\r
+\r
+typedef struct _DeviceVectors\r
+{\r
+ /* Stack pointer */\r
+ void* pvStack;\r
+\r
+ /* Cortex-M handlers */\r
+ void* pfnReset_Handler;\r
+ void* pfnNMI_Handler;\r
+ void* pfnHardFault_Handler;\r
+ void* pfnMemManage_Handler;\r
+ void* pfnBusFault_Handler;\r
+ void* pfnUsageFault_Handler;\r
+ void* pfnReserved1_Handler;\r
+ void* pfnReserved2_Handler;\r
+ void* pfnReserved3_Handler;\r
+ void* pfnReserved4_Handler;\r
+ void* pfnSVC_Handler;\r
+ void* pfnDebugMon_Handler;\r
+ void* pfnReserved5_Handler;\r
+ void* pfnPendSV_Handler;\r
+ void* pfnSysTick_Handler;\r
+\r
+ /* Peripheral handlers */\r
+ void* pfnSUPC_Handler; /* 0 Supply Controller */\r
+ void* pfnRSTC_Handler; /* 1 Reset Controller */\r
+ void* pfnRTC_Handler; /* 2 Real Time Clock */\r
+ void* pfnRTT_Handler; /* 3 Real Time Timer */\r
+ void* pfnWDT_Handler; /* 4 Watchdog/Dual Watchdog Timer */\r
+ void* pfnPMC_Handler; /* 5 Power Management Controller */\r
+ void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */\r
+ void* pfnUART0_Handler; /* 7 UART 0 */\r
+ void* pvReserved8;\r
+ void* pfnPIOA_Handler; /* 9 Parallel I/O Controller A */\r
+ void* pfnPIOB_Handler; /* 10 Parallel I/O Controller B */\r
+ void* pfnPIOC_Handler; /* 11 Parallel I/O Controller C */\r
+ void* pvReserved12;\r
+ void* pvReserved13;\r
+ void* pfnUSART0_Handler; /* 14 USART 0 */\r
+ void* pfnUSART1_Handler; /* 15 USART 1 */\r
+ void* pfnHSMCI_Handler; /* 16 Multimedia Card Interface */\r
+ void* pfnTWI0_Handler; /* 17 Two Wire Interface 0 */\r
+ void* pfnTWI1_Handler; /* 18 Two Wire Interface 1 */\r
+ void* pfnSPI_Handler; /* 19 Serial Peripheral Interface */\r
+ void* pfnDMAC_Handler; /* 20 DMAC */\r
+ void* pfnTC0_Handler; /* 21 Timer/Counter 0 */\r
+ void* pfnTC1_Handler; /* 22 Timer/Counter 1 */\r
+ void* pfnTC2_Handler; /* 23 Timer/Counter 2 */\r
+ void* pfnTC3_Handler; /* 24 Timer/Counter 3 */\r
+ void* pfnTC4_Handler; /* 25 Timer/Counter 4 */\r
+ void* pfnTC5_Handler; /* 26 Timer/Counter 5 */\r
+ void* pfnTC6_Handler; /* 27 Timer/Counter 6 */\r
+ void* pfnTC7_Handler; /* 28 Timer/Counter 7 */\r
+ void* pfnTC8_Handler; /* 29 Timer/Counter 8 */\r
+ void* pfnAFEC0_Handler; /* 30 Analog Front End 0 */\r
+ void* pfnAFEC1_Handler; /* 31 Analog Front End 1 */\r
+ void* pfnDACC_Handler; /* 32 Digital To Analog Converter */\r
+ void* pfnACC_Handler; /* 33 Analog Comparator */\r
+ void* pfnARM_Handler; /* 34 FPU signals : FPIXC, FPOFC, FPUFC, FPIOC, FPDZC, FPIDC, FPIXC */\r
+ void* pfnUDP_Handler; /* 35 USB DEVICE */\r
+ void* pfnPWM_Handler; /* 36 PWM */\r
+ void* pfnCAN0_Handler; /* 37 CAN0 */\r
+ void* pfnCAN1_Handler; /* 38 CAN1 */\r
+ void* pfnAES_Handler; /* 39 AES */\r
+ void* pvReserved40;\r
+ void* pvReserved41;\r
+ void* pvReserved42;\r
+ void* pvReserved43;\r
+ void* pvReserved44;\r
+ void* pfnUART1_Handler; /* 45 UART */\r
+} DeviceVectors;\r
+\r
+/* Cortex-M4 core handlers */\r
+void Reset_Handler ( void );\r
+void NMI_Handler ( void );\r
+void HardFault_Handler ( void );\r
+void MemManage_Handler ( void );\r
+void BusFault_Handler ( void );\r
+void UsageFault_Handler ( void );\r
+void SVC_Handler ( void );\r
+void DebugMon_Handler ( void );\r
+void PendSV_Handler ( void );\r
+void SysTick_Handler ( void );\r
+\r
+/* Peripherals handlers */\r
+void ACC_Handler ( void );\r
+void AES_Handler ( void );\r
+void AFEC0_Handler ( void );\r
+void AFEC1_Handler ( void );\r
+void ARM_Handler ( void );\r
+void CAN0_Handler ( void );\r
+void CAN1_Handler ( void );\r
+void DACC_Handler ( void );\r
+void DMAC_Handler ( void );\r
+void EFC_Handler ( void );\r
+void HSMCI_Handler ( void );\r
+void PIOA_Handler ( void );\r
+void PIOB_Handler ( void );\r
+void PIOC_Handler ( void );\r
+void PMC_Handler ( void );\r
+void PWM_Handler ( void );\r
+void RSTC_Handler ( void );\r
+void RTC_Handler ( void );\r
+void RTT_Handler ( void );\r
+void SPI_Handler ( void );\r
+void SUPC_Handler ( void );\r
+void TC0_Handler ( void );\r
+void TC1_Handler ( void );\r
+void TC2_Handler ( void );\r
+void TC3_Handler ( void );\r
+void TC4_Handler ( void );\r
+void TC5_Handler ( void );\r
+void TC6_Handler ( void );\r
+void TC7_Handler ( void );\r
+void TC8_Handler ( void );\r
+void TWI0_Handler ( void );\r
+void TWI1_Handler ( void );\r
+void UART0_Handler ( void );\r
+void UART1_Handler ( void );\r
+void UDP_Handler ( void );\r
+void USART0_Handler ( void );\r
+void USART1_Handler ( void );\r
+void WDT_Handler ( void );\r
+\r
+/**\r
+ * \brief Configuration of the Cortex-M4 Processor and Core Peripherals\r
+ */\r
+\r
+#define __CM4_REV 0x0000 /**< SAM4E8C core revision number ([15:8] revision number, [7:0] patch number) */\r
+#define __MPU_PRESENT 0 /**< SAM4E8C does not provide a MPU */\r
+#define __FPU_PRESENT 1 /**< SAM4E8C does provide a FPU */\r
+#define __NVIC_PRIO_BITS 4 /**< SAM4E8C uses 4 Bits for the Priority Levels */\r
+#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */\r
+\r
+/*\r
+ * \brief CMSIS includes\r
+ */\r
+\r
+#include <core_cm4.h>\r
+#if !defined DONT_USE_CMSIS_INIT\r
+#include "system_sam4e.h"\r
+#endif /* DONT_USE_CMSIS_INIT */\r
+\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** SOFTWARE PERIPHERAL API DEFINITION FOR SAM4E8C */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAM4E8C_api Peripheral Software API */\r
+/*@{*/\r
+\r
+#include "component/acc.h"\r
+#include "component/aes.h"\r
+#include "component/afec.h"\r
+#include "component/can.h"\r
+#include "component/chipid.h"\r
+#include "component/cmcc.h"\r
+#include "component/crccu.h"\r
+#include "component/dacc.h"\r
+#include "component/dmac.h"\r
+#include "component/efc.h"\r
+#include "component/gpbr.h"\r
+#include "component/hsmci.h"\r
+#include "component/matrix.h"\r
+#include "component/pdc.h"\r
+#include "component/pio.h"\r
+#include "component/pmc.h"\r
+#include "component/pwm.h"\r
+#include "component/rstc.h"\r
+#include "component/rswdt.h"\r
+#include "component/rtc.h"\r
+#include "component/rtt.h"\r
+#include "component/spi.h"\r
+#include "component/supc.h"\r
+#include "component/tc.h"\r
+#include "component/twi.h"\r
+#include "component/uart.h"\r
+#include "component/udp.h"\r
+#include "component/usart.h"\r
+#include "component/wdt.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* REGISTER ACCESS DEFINITIONS FOR SAM4E8C */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAM4E8C_reg Registers Access Definitions */\r
+/*@{*/\r
+\r
+#include "instance/pwm.h"\r
+#include "instance/aes.h"\r
+#include "instance/can0.h"\r
+#include "instance/can1.h"\r
+#include "instance/crccu.h"\r
+#include "instance/uart1.h"\r
+#include "instance/hsmci.h"\r
+#include "instance/udp.h"\r
+#include "instance/spi.h"\r
+#include "instance/tc0.h"\r
+#include "instance/tc1.h"\r
+#include "instance/tc2.h"\r
+#include "instance/usart0.h"\r
+#include "instance/usart1.h"\r
+#include "instance/twi0.h"\r
+#include "instance/twi1.h"\r
+#include "instance/afec0.h"\r
+#include "instance/afec1.h"\r
+#include "instance/dacc.h"\r
+#include "instance/acc.h"\r
+#include "instance/dmac.h"\r
+#include "instance/cmcc.h"\r
+#include "instance/matrix.h"\r
+#include "instance/pmc.h"\r
+#include "instance/uart0.h"\r
+#include "instance/chipid.h"\r
+#include "instance/efc.h"\r
+#include "instance/pioa.h"\r
+#include "instance/piob.h"\r
+#include "instance/pioc.h"\r
+#include "instance/rstc.h"\r
+#include "instance/supc.h"\r
+#include "instance/rtt.h"\r
+#include "instance/wdt.h"\r
+#include "instance/rtc.h"\r
+#include "instance/gpbr.h"\r
+#include "instance/rswdt.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* PERIPHERAL ID DEFINITIONS FOR SAM4E8C */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAM4E8C_id Peripheral Ids Definitions */\r
+/*@{*/\r
+\r
+#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */\r
+#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */\r
+#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */\r
+#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */\r
+#define ID_WDT ( 4) /**< \brief Watchdog/Dual Watchdog Timer (WDT) */\r
+#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */\r
+#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */\r
+#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */\r
+#define ID_PIOA ( 9) /**< \brief Parallel I/O Controller A (PIOA) */\r
+#define ID_PIOB (10) /**< \brief Parallel I/O Controller B (PIOB) */\r
+#define ID_PIOC (11) /**< \brief Parallel I/O Controller C (PIOC) */\r
+#define ID_USART0 (14) /**< \brief USART 0 (USART0) */\r
+#define ID_USART1 (15) /**< \brief USART 1 (USART1) */\r
+#define ID_HSMCI (16) /**< \brief Multimedia Card Interface (HSMCI) */\r
+#define ID_TWI0 (17) /**< \brief Two Wire Interface 0 (TWI0) */\r
+#define ID_TWI1 (18) /**< \brief Two Wire Interface 1 (TWI1) */\r
+#define ID_SPI (19) /**< \brief Serial Peripheral Interface (SPI) */\r
+#define ID_DMAC (20) /**< \brief DMAC (DMAC) */\r
+#define ID_TC0 (21) /**< \brief Timer/Counter 0 (TC0) */\r
+#define ID_TC1 (22) /**< \brief Timer/Counter 1 (TC1) */\r
+#define ID_TC2 (23) /**< \brief Timer/Counter 2 (TC2) */\r
+#define ID_TC3 (24) /**< \brief Timer/Counter 3 (TC3) */\r
+#define ID_TC4 (25) /**< \brief Timer/Counter 4 (TC4) */\r
+#define ID_TC5 (26) /**< \brief Timer/Counter 5 (TC5) */\r
+#define ID_TC6 (27) /**< \brief Timer/Counter 6 (TC6) */\r
+#define ID_TC7 (28) /**< \brief Timer/Counter 7 (TC7) */\r
+#define ID_TC8 (29) /**< \brief Timer/Counter 8 (TC8) */\r
+#define ID_AFEC0 (30) /**< \brief Analog Front End 0 (AFEC0) */\r
+#define ID_AFEC1 (31) /**< \brief Analog Front End 1 (AFEC1) */\r
+#define ID_DACC (32) /**< \brief Digital To Analog Converter (DACC) */\r
+#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */\r
+#define ID_ARM (34) /**< \brief FPU signals : FPIXC, FPOFC, FPUFC, FPIOC, FPDZC, FPIDC, FPIXC (ARM) */\r
+#define ID_UDP (35) /**< \brief USB DEVICE (UDP) */\r
+#define ID_PWM (36) /**< \brief PWM (PWM) */\r
+#define ID_CAN0 (37) /**< \brief CAN0 (CAN0) */\r
+#define ID_CAN1 (38) /**< \brief CAN1 (CAN1) */\r
+#define ID_AES (39) /**< \brief AES (AES) */\r
+#define ID_UART1 (45) /**< \brief UART (UART1) */\r
+\r
+#define ID_PERIPH_COUNT (46) /**< \brief Number of peripheral IDs */\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* BASE ADDRESS DEFINITIONS FOR SAM4E8C */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAM4E8C_base Peripheral Base Address Definitions */\r
+/*@{*/\r
+\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define PWM (0x40000000U) /**< \brief (PWM ) Base Address */\r
+#define PDC_PWM (0x40000100U) /**< \brief (PDC_PWM ) Base Address */\r
+#define AES (0x40004000U) /**< \brief (AES ) Base Address */\r
+#define CAN0 (0x40010000U) /**< \brief (CAN0 ) Base Address */\r
+#define CAN1 (0x40014000U) /**< \brief (CAN1 ) Base Address */\r
+#define CRCCU (0x40044000U) /**< \brief (CRCCU ) Base Address */\r
+#define UART1 (0x40060600U) /**< \brief (UART1 ) Base Address */\r
+#define PDC_UART1 (0x40060700U) /**< \brief (PDC_UART1 ) Base Address */\r
+#define HSMCI (0x40080000U) /**< \brief (HSMCI ) Base Address */\r
+#define PDC_HSMCI (0x40080100U) /**< \brief (PDC_HSMCI ) Base Address */\r
+#define UDP (0x40084000U) /**< \brief (UDP ) Base Address */\r
+#define SPI (0x40088000U) /**< \brief (SPI ) Base Address */\r
+#define PDC_SPI (0x40088100U) /**< \brief (PDC_SPI ) Base Address */\r
+#define TC0 (0x40090000U) /**< \brief (TC0 ) Base Address */\r
+#define PDC_TC0 (0x40090100U) /**< \brief (PDC_TC0 ) Base Address */\r
+#define TC1 (0x40094000U) /**< \brief (TC1 ) Base Address */\r
+#define PDC_TC1 (0x40094100U) /**< \brief (PDC_TC1 ) Base Address */\r
+#define TC2 (0x40098000U) /**< \brief (TC2 ) Base Address */\r
+#define USART0 (0x400A0000U) /**< \brief (USART0 ) Base Address */\r
+#define PDC_USART0 (0x400A0100U) /**< \brief (PDC_USART0) Base Address */\r
+#define USART1 (0x400A4000U) /**< \brief (USART1 ) Base Address */\r
+#define PDC_USART1 (0x400A4100U) /**< \brief (PDC_USART1) Base Address */\r
+#define TWI0 (0x400A8000U) /**< \brief (TWI0 ) Base Address */\r
+#define PDC_TWI0 (0x400A8100U) /**< \brief (PDC_TWI0 ) Base Address */\r
+#define TWI1 (0x400AC000U) /**< \brief (TWI1 ) Base Address */\r
+#define PDC_TWI1 (0x400AC100U) /**< \brief (PDC_TWI1 ) Base Address */\r
+#define AFEC0 (0x400B0000U) /**< \brief (AFEC0 ) Base Address */\r
+#define PDC_AFEC0 (0x400B0100U) /**< \brief (PDC_AFEC0 ) Base Address */\r
+#define AFEC1 (0x400B4000U) /**< \brief (AFEC1 ) Base Address */\r
+#define PDC_AFEC1 (0x400B4100U) /**< \brief (PDC_AFEC1 ) Base Address */\r
+#define DACC (0x400B8000U) /**< \brief (DACC ) Base Address */\r
+#define PDC_DACC (0x400B8100U) /**< \brief (PDC_DACC ) Base Address */\r
+#define ACC (0x400BC000U) /**< \brief (ACC ) Base Address */\r
+#define DMAC (0x400C0000U) /**< \brief (DMAC ) Base Address */\r
+#define CMCC (0x400C4000U) /**< \brief (CMCC ) Base Address */\r
+#define MATRIX (0x400E0200U) /**< \brief (MATRIX ) Base Address */\r
+#define PMC (0x400E0400U) /**< \brief (PMC ) Base Address */\r
+#define UART0 (0x400E0600U) /**< \brief (UART0 ) Base Address */\r
+#define PDC_UART0 (0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */\r
+#define CHIPID (0x400E0740U) /**< \brief (CHIPID ) Base Address */\r
+#define EFC (0x400E0A00U) /**< \brief (EFC ) Base Address */\r
+#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */\r
+#define PDC_PIOA (0x400E0F68U) /**< \brief (PDC_PIOA ) Base Address */\r
+#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */\r
+#define PIOC (0x400E1200U) /**< \brief (PIOC ) Base Address */\r
+#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */\r
+#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */\r
+#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */\r
+#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */\r
+#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */\r
+#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */\r
+#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */\r
+#else\r
+#define PWM ((Pwm *)0x40000000U) /**< \brief (PWM ) Base Address */\r
+#define PDC_PWM ((Pdc *)0x40000100U) /**< \brief (PDC_PWM ) Base Address */\r
+#define AES ((Aes *)0x40004000U) /**< \brief (AES ) Base Address */\r
+#define CAN0 ((Can *)0x40010000U) /**< \brief (CAN0 ) Base Address */\r
+#define CAN1 ((Can *)0x40014000U) /**< \brief (CAN1 ) Base Address */\r
+#define CRCCU ((Crccu *)0x40044000U) /**< \brief (CRCCU ) Base Address */\r
+#define UART1 ((Uart *)0x40060600U) /**< \brief (UART1 ) Base Address */\r
+#define PDC_UART1 ((Pdc *)0x40060700U) /**< \brief (PDC_UART1 ) Base Address */\r
+#define HSMCI ((Hsmci *)0x40080000U) /**< \brief (HSMCI ) Base Address */\r
+#define PDC_HSMCI ((Pdc *)0x40080100U) /**< \brief (PDC_HSMCI ) Base Address */\r
+#define UDP ((Udp *)0x40084000U) /**< \brief (UDP ) Base Address */\r
+#define SPI ((Spi *)0x40088000U) /**< \brief (SPI ) Base Address */\r
+#define PDC_SPI ((Pdc *)0x40088100U) /**< \brief (PDC_SPI ) Base Address */\r
+#define TC0 ((Tc *)0x40090000U) /**< \brief (TC0 ) Base Address */\r
+#define PDC_TC0 ((Pdc *)0x40090100U) /**< \brief (PDC_TC0 ) Base Address */\r
+#define TC1 ((Tc *)0x40094000U) /**< \brief (TC1 ) Base Address */\r
+#define PDC_TC1 ((Pdc *)0x40094100U) /**< \brief (PDC_TC1 ) Base Address */\r
+#define TC2 ((Tc *)0x40098000U) /**< \brief (TC2 ) Base Address */\r
+#define USART0 ((Usart *)0x400A0000U) /**< \brief (USART0 ) Base Address */\r
+#define PDC_USART0 ((Pdc *)0x400A0100U) /**< \brief (PDC_USART0) Base Address */\r
+#define USART1 ((Usart *)0x400A4000U) /**< \brief (USART1 ) Base Address */\r
+#define PDC_USART1 ((Pdc *)0x400A4100U) /**< \brief (PDC_USART1) Base Address */\r
+#define TWI0 ((Twi *)0x400A8000U) /**< \brief (TWI0 ) Base Address */\r
+#define PDC_TWI0 ((Pdc *)0x400A8100U) /**< \brief (PDC_TWI0 ) Base Address */\r
+#define TWI1 ((Twi *)0x400AC000U) /**< \brief (TWI1 ) Base Address */\r
+#define PDC_TWI1 ((Pdc *)0x400AC100U) /**< \brief (PDC_TWI1 ) Base Address */\r
+#define AFEC0 ((Afec *)0x400B0000U) /**< \brief (AFEC0 ) Base Address */\r
+#define PDC_AFEC0 ((Pdc *)0x400B0100U) /**< \brief (PDC_AFEC0 ) Base Address */\r
+#define AFEC1 ((Afec *)0x400B4000U) /**< \brief (AFEC1 ) Base Address */\r
+#define PDC_AFEC1 ((Pdc *)0x400B4100U) /**< \brief (PDC_AFEC1 ) Base Address */\r
+#define DACC ((Dacc *)0x400B8000U) /**< \brief (DACC ) Base Address */\r
+#define PDC_DACC ((Pdc *)0x400B8100U) /**< \brief (PDC_DACC ) Base Address */\r
+#define ACC ((Acc *)0x400BC000U) /**< \brief (ACC ) Base Address */\r
+#define DMAC ((Dmac *)0x400C0000U) /**< \brief (DMAC ) Base Address */\r
+#define CMCC ((Cmcc *)0x400C4000U) /**< \brief (CMCC ) Base Address */\r
+#define MATRIX ((Matrix *)0x400E0200U) /**< \brief (MATRIX ) Base Address */\r
+#define PMC ((Pmc *)0x400E0400U) /**< \brief (PMC ) Base Address */\r
+#define UART0 ((Uart *)0x400E0600U) /**< \brief (UART0 ) Base Address */\r
+#define PDC_UART0 ((Pdc *)0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */\r
+#define CHIPID ((Chipid *)0x400E0740U) /**< \brief (CHIPID ) Base Address */\r
+#define EFC ((Efc *)0x400E0A00U) /**< \brief (EFC ) Base Address */\r
+#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */\r
+#define PDC_PIOA ((Pdc *)0x400E0F68U) /**< \brief (PDC_PIOA ) Base Address */\r
+#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */\r
+#define PIOC ((Pio *)0x400E1200U) /**< \brief (PIOC ) Base Address */\r
+#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */\r
+#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */\r
+#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */\r
+#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */\r
+#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */\r
+#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */\r
+#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* PIO DEFINITIONS FOR SAM4E8C */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAM4E8C_pio Peripheral Pio Definitions */\r
+/*@{*/\r
+\r
+#include "pio/sam4e8c.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* MEMORY MAPPING DEFINITIONS FOR SAM4E8C */\r
+/* ************************************************************************** */\r
+\r
+#define IFLASH_SIZE (0x80000u)\r
+#define IFLASH_PAGE_SIZE (512u)\r
+#define IFLASH_LOCK_REGION_SIZE (8192u)\r
+#define IFLASH_NB_OF_PAGES (1024u)\r
+#define IFLASH_NB_OF_LOCK_BITS (128u)\r
+#define IRAM_SIZE (0x20000u)\r
+\r
+#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */\r
+#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */\r
+#define IRAM_ADDR (0x20000000u) /**< Internal RAM base address */\r
+#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */\r
+#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */\r
+#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */\r
+#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */\r
+\r
+/* ************************************************************************** */\r
+/* MISCELLANEOUS DEFINITIONS FOR SAM4E8C */\r
+/* ************************************************************************** */\r
+\r
+#define CHIP_JTAGID (0x05B3703FUL)\r
+#define CHIP_CIDR (0xA3CC0CE0UL)\r
+#define CHIP_EXID (0x00110209UL)\r
+#define NB_CH_AFE0 (6UL)\r
+#define NB_CH_AFE1 (4UL)\r
+\r
+/* ************************************************************************** */\r
+/* ELECTRICAL DEFINITIONS FOR SAM4E8C */\r
+/* ************************************************************************** */\r
+\r
+/* Device characteristics */\r
+#define CHIP_FREQ_SLCK_RC_MIN (20000UL)\r
+#define CHIP_FREQ_SLCK_RC (32000UL)\r
+#define CHIP_FREQ_SLCK_RC_MAX (44000UL)\r
+#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL)\r
+#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL)\r
+#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL)\r
+#define CHIP_FREQ_CPU_MAX (120000000UL)\r
+#define CHIP_FREQ_XTAL_32K (32768UL)\r
+#define CHIP_FREQ_XTAL_12M (12000000UL)\r
+\r
+/* Embedded Flash Write Wait State */\r
+#define CHIP_FLASH_WRITE_WAIT_STATE (6U)\r
+\r
+/* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */\r
+#define CHIP_FREQ_FWS_0 (20000000UL) /**< \brief Maximum operating frequency when FWS is 0 */\r
+#define CHIP_FREQ_FWS_1 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */\r
+#define CHIP_FREQ_FWS_2 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */\r
+#define CHIP_FREQ_FWS_3 (80000000UL) /**< \brief Maximum operating frequency when FWS is 3 */\r
+#define CHIP_FREQ_FWS_4 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */\r
+#define CHIP_FREQ_FWS_5 (123000000UL) /**< \brief Maximum operating frequency when FWS is 5 */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+/*@}*/\r
+\r
+#endif /* _SAM4E8C_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4E8E_\r
+#define _SAM4E8E_\r
+\r
+/** \addtogroup SAM4E8E_definitions SAM4E8E definitions\r
+ This file defines all structures and symbols for SAM4E8E:\r
+ - registers and bitfields\r
+ - peripheral base address\r
+ - peripheral ID\r
+ - PIO definitions\r
+*/\r
+/*@{*/\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#include <stdint.h>\r
+#ifndef __cplusplus\r
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */\r
+#else\r
+typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */\r
+#endif\r
+typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */\r
+typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */\r
+#endif\r
+\r
+/* ************************************************************************** */\r
+/* CMSIS DEFINITIONS FOR SAM4E8E */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAM4E8E_cmsis CMSIS Definitions */\r
+/*@{*/\r
+\r
+/**< Interrupt Number Definition */\r
+typedef enum IRQn\r
+{\r
+/****** Cortex-M4 Processor Exceptions Numbers ******************************/\r
+ NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */\r
+ MemoryManagement_IRQn = -12, /**< 4 Cortex-M4 Memory Management Interrupt */\r
+ BusFault_IRQn = -11, /**< 5 Cortex-M4 Bus Fault Interrupt */\r
+ UsageFault_IRQn = -10, /**< 6 Cortex-M4 Usage Fault Interrupt */\r
+ SVCall_IRQn = -5, /**< 11 Cortex-M4 SV Call Interrupt */\r
+ DebugMonitor_IRQn = -4, /**< 12 Cortex-M4 Debug Monitor Interrupt */\r
+ PendSV_IRQn = -2, /**< 14 Cortex-M4 Pend SV Interrupt */\r
+ SysTick_IRQn = -1, /**< 15 Cortex-M4 System Tick Interrupt */\r
+/****** SAM4E8E specific Interrupt Numbers *********************************/\r
+\r
+ SUPC_IRQn = 0, /**< 0 SAM4E8E Supply Controller (SUPC) */\r
+ RSTC_IRQn = 1, /**< 1 SAM4E8E Reset Controller (RSTC) */\r
+ RTC_IRQn = 2, /**< 2 SAM4E8E Real Time Clock (RTC) */\r
+ RTT_IRQn = 3, /**< 3 SAM4E8E Real Time Timer (RTT) */\r
+ WDT_IRQn = 4, /**< 4 SAM4E8E Watchdog/Dual Watchdog Timer (WDT) */\r
+ PMC_IRQn = 5, /**< 5 SAM4E8E Power Management Controller (PMC) */\r
+ EFC_IRQn = 6, /**< 6 SAM4E8E Enhanced Embedded Flash Controller (EFC) */\r
+ UART0_IRQn = 7, /**< 7 SAM4E8E UART 0 (UART0) */\r
+ PIOA_IRQn = 9, /**< 9 SAM4E8E Parallel I/O Controller A (PIOA) */\r
+ PIOB_IRQn = 10, /**< 10 SAM4E8E Parallel I/O Controller B (PIOB) */\r
+ PIOC_IRQn = 11, /**< 11 SAM4E8E Parallel I/O Controller C (PIOC) */\r
+ PIOD_IRQn = 12, /**< 12 SAM4E8E Parallel I/O Controller D (PIOD) */\r
+ PIOE_IRQn = 13, /**< 13 SAM4E8E Parallel I/O Controller E (PIOE) */\r
+ USART0_IRQn = 14, /**< 14 SAM4E8E USART 0 (USART0) */\r
+ USART1_IRQn = 15, /**< 15 SAM4E8E USART 1 (USART1) */\r
+ HSMCI_IRQn = 16, /**< 16 SAM4E8E Multimedia Card Interface (HSMCI) */\r
+ TWI0_IRQn = 17, /**< 17 SAM4E8E Two Wire Interface 0 (TWI0) */\r
+ TWI1_IRQn = 18, /**< 18 SAM4E8E Two Wire Interface 1 (TWI1) */\r
+ SPI_IRQn = 19, /**< 19 SAM4E8E Serial Peripheral Interface (SPI) */\r
+ DMAC_IRQn = 20, /**< 20 SAM4E8E DMAC (DMAC) */\r
+ TC0_IRQn = 21, /**< 21 SAM4E8E Timer/Counter 0 (TC0) */\r
+ TC1_IRQn = 22, /**< 22 SAM4E8E Timer/Counter 1 (TC1) */\r
+ TC2_IRQn = 23, /**< 23 SAM4E8E Timer/Counter 2 (TC2) */\r
+ TC3_IRQn = 24, /**< 24 SAM4E8E Timer/Counter 3 (TC3) */\r
+ TC4_IRQn = 25, /**< 25 SAM4E8E Timer/Counter 4 (TC4) */\r
+ TC5_IRQn = 26, /**< 26 SAM4E8E Timer/Counter 5 (TC5) */\r
+ TC6_IRQn = 27, /**< 27 SAM4E8E Timer/Counter 6 (TC6) */\r
+ TC7_IRQn = 28, /**< 28 SAM4E8E Timer/Counter 7 (TC7) */\r
+ TC8_IRQn = 29, /**< 29 SAM4E8E Timer/Counter 8 (TC8) */\r
+ AFEC0_IRQn = 30, /**< 30 SAM4E8E Analog Front End 0 (AFEC0) */\r
+ AFEC1_IRQn = 31, /**< 31 SAM4E8E Analog Front End 1 (AFEC1) */\r
+ DACC_IRQn = 32, /**< 32 SAM4E8E Digital To Analog Converter (DACC) */\r
+ ACC_IRQn = 33, /**< 33 SAM4E8E Analog Comparator (ACC) */\r
+ ARM_IRQn = 34, /**< 34 SAM4E8E FPU signals : FPIXC, FPOFC, FPUFC, FPIOC, FPDZC, FPIDC, FPIXC (ARM) */\r
+ UDP_IRQn = 35, /**< 35 SAM4E8E USB DEVICE (UDP) */\r
+ PWM_IRQn = 36, /**< 36 SAM4E8E PWM (PWM) */\r
+ CAN0_IRQn = 37, /**< 37 SAM4E8E CAN0 (CAN0) */\r
+ CAN1_IRQn = 38, /**< 38 SAM4E8E CAN1 (CAN1) */\r
+ AES_IRQn = 39, /**< 39 SAM4E8E AES (AES) */\r
+ GMAC_IRQn = 44, /**< 44 SAM4E8E EMAC (GMAC) */\r
+ UART1_IRQn = 45, /**< 45 SAM4E8E UART (UART1) */\r
+\r
+ PERIPH_COUNT_IRQn = 46 /**< Number of peripheral IDs */\r
+} IRQn_Type;\r
+\r
+typedef struct _DeviceVectors\r
+{\r
+ /* Stack pointer */\r
+ void* pvStack;\r
+\r
+ /* Cortex-M handlers */\r
+ void* pfnReset_Handler;\r
+ void* pfnNMI_Handler;\r
+ void* pfnHardFault_Handler;\r
+ void* pfnMemManage_Handler;\r
+ void* pfnBusFault_Handler;\r
+ void* pfnUsageFault_Handler;\r
+ void* pfnReserved1_Handler;\r
+ void* pfnReserved2_Handler;\r
+ void* pfnReserved3_Handler;\r
+ void* pfnReserved4_Handler;\r
+ void* pfnSVC_Handler;\r
+ void* pfnDebugMon_Handler;\r
+ void* pfnReserved5_Handler;\r
+ void* pfnPendSV_Handler;\r
+ void* pfnSysTick_Handler;\r
+\r
+ /* Peripheral handlers */\r
+ void* pfnSUPC_Handler; /* 0 Supply Controller */\r
+ void* pfnRSTC_Handler; /* 1 Reset Controller */\r
+ void* pfnRTC_Handler; /* 2 Real Time Clock */\r
+ void* pfnRTT_Handler; /* 3 Real Time Timer */\r
+ void* pfnWDT_Handler; /* 4 Watchdog/Dual Watchdog Timer */\r
+ void* pfnPMC_Handler; /* 5 Power Management Controller */\r
+ void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */\r
+ void* pfnUART0_Handler; /* 7 UART 0 */\r
+ void* pvReserved8;\r
+ void* pfnPIOA_Handler; /* 9 Parallel I/O Controller A */\r
+ void* pfnPIOB_Handler; /* 10 Parallel I/O Controller B */\r
+ void* pfnPIOC_Handler; /* 11 Parallel I/O Controller C */\r
+ void* pfnPIOD_Handler; /* 12 Parallel I/O Controller D */\r
+ void* pfnPIOE_Handler; /* 13 Parallel I/O Controller E */\r
+ void* pfnUSART0_Handler; /* 14 USART 0 */\r
+ void* pfnUSART1_Handler; /* 15 USART 1 */\r
+ void* pfnHSMCI_Handler; /* 16 Multimedia Card Interface */\r
+ void* pfnTWI0_Handler; /* 17 Two Wire Interface 0 */\r
+ void* pfnTWI1_Handler; /* 18 Two Wire Interface 1 */\r
+ void* pfnSPI_Handler; /* 19 Serial Peripheral Interface */\r
+ void* pfnDMAC_Handler; /* 20 DMAC */\r
+ void* pfnTC0_Handler; /* 21 Timer/Counter 0 */\r
+ void* pfnTC1_Handler; /* 22 Timer/Counter 1 */\r
+ void* pfnTC2_Handler; /* 23 Timer/Counter 2 */\r
+ void* pfnTC3_Handler; /* 24 Timer/Counter 3 */\r
+ void* pfnTC4_Handler; /* 25 Timer/Counter 4 */\r
+ void* pfnTC5_Handler; /* 26 Timer/Counter 5 */\r
+ void* pfnTC6_Handler; /* 27 Timer/Counter 6 */\r
+ void* pfnTC7_Handler; /* 28 Timer/Counter 7 */\r
+ void* pfnTC8_Handler; /* 29 Timer/Counter 8 */\r
+ void* pfnAFEC0_Handler; /* 30 Analog Front End 0 */\r
+ void* pfnAFEC1_Handler; /* 31 Analog Front End 1 */\r
+ void* pfnDACC_Handler; /* 32 Digital To Analog Converter */\r
+ void* pfnACC_Handler; /* 33 Analog Comparator */\r
+ void* pfnARM_Handler; /* 34 FPU signals : FPIXC, FPOFC, FPUFC, FPIOC, FPDZC, FPIDC, FPIXC */\r
+ void* pfnUDP_Handler; /* 35 USB DEVICE */\r
+ void* pfnPWM_Handler; /* 36 PWM */\r
+ void* pfnCAN0_Handler; /* 37 CAN0 */\r
+ void* pfnCAN1_Handler; /* 38 CAN1 */\r
+ void* pfnAES_Handler; /* 39 AES */\r
+ void* pvReserved40;\r
+ void* pvReserved41;\r
+ void* pvReserved42;\r
+ void* pvReserved43;\r
+ void* pfnGMAC_Handler; /* 44 EMAC */\r
+ void* pfnUART1_Handler; /* 45 UART */\r
+} DeviceVectors;\r
+\r
+/* Cortex-M4 core handlers */\r
+void Reset_Handler ( void );\r
+void NMI_Handler ( void );\r
+void HardFault_Handler ( void );\r
+void MemManage_Handler ( void );\r
+void BusFault_Handler ( void );\r
+void UsageFault_Handler ( void );\r
+void SVC_Handler ( void );\r
+void DebugMon_Handler ( void );\r
+void PendSV_Handler ( void );\r
+void SysTick_Handler ( void );\r
+\r
+/* Peripherals handlers */\r
+void ACC_Handler ( void );\r
+void AES_Handler ( void );\r
+void AFEC0_Handler ( void );\r
+void AFEC1_Handler ( void );\r
+void ARM_Handler ( void );\r
+void CAN0_Handler ( void );\r
+void CAN1_Handler ( void );\r
+void DACC_Handler ( void );\r
+void DMAC_Handler ( void );\r
+void EFC_Handler ( void );\r
+void GMAC_Handler ( void );\r
+void HSMCI_Handler ( void );\r
+void PIOA_Handler ( void );\r
+void PIOB_Handler ( void );\r
+void PIOC_Handler ( void );\r
+void PIOD_Handler ( void );\r
+void PIOE_Handler ( void );\r
+void PMC_Handler ( void );\r
+void PWM_Handler ( void );\r
+void RSTC_Handler ( void );\r
+void RTC_Handler ( void );\r
+void RTT_Handler ( void );\r
+void SPI_Handler ( void );\r
+void SUPC_Handler ( void );\r
+void TC0_Handler ( void );\r
+void TC1_Handler ( void );\r
+void TC2_Handler ( void );\r
+void TC3_Handler ( void );\r
+void TC4_Handler ( void );\r
+void TC5_Handler ( void );\r
+void TC6_Handler ( void );\r
+void TC7_Handler ( void );\r
+void TC8_Handler ( void );\r
+void TWI0_Handler ( void );\r
+void TWI1_Handler ( void );\r
+void UART0_Handler ( void );\r
+void UART1_Handler ( void );\r
+void UDP_Handler ( void );\r
+void USART0_Handler ( void );\r
+void USART1_Handler ( void );\r
+void WDT_Handler ( void );\r
+\r
+/**\r
+ * \brief Configuration of the Cortex-M4 Processor and Core Peripherals\r
+ */\r
+\r
+#define __CM4_REV 0x0000 /**< SAM4E8E core revision number ([15:8] revision number, [7:0] patch number) */\r
+#define __MPU_PRESENT 0 /**< SAM4E8E does not provide a MPU */\r
+#define __FPU_PRESENT 1 /**< SAM4E8E does provide a FPU */\r
+#define __NVIC_PRIO_BITS 4 /**< SAM4E8E uses 4 Bits for the Priority Levels */\r
+#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */\r
+\r
+/*\r
+ * \brief CMSIS includes\r
+ */\r
+\r
+#include <core_cm4.h>\r
+#if !defined DONT_USE_CMSIS_INIT\r
+#include "system_sam4e.h"\r
+#endif /* DONT_USE_CMSIS_INIT */\r
+\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** SOFTWARE PERIPHERAL API DEFINITION FOR SAM4E8E */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAM4E8E_api Peripheral Software API */\r
+/*@{*/\r
+\r
+#include "component/acc.h"\r
+#include "component/aes.h"\r
+#include "component/afec.h"\r
+#include "component/can.h"\r
+#include "component/chipid.h"\r
+#include "component/cmcc.h"\r
+#include "component/crccu.h"\r
+#include "component/dacc.h"\r
+#include "component/dmac.h"\r
+#include "component/efc.h"\r
+#include "component/gmac.h"\r
+#include "component/gpbr.h"\r
+#include "component/hsmci.h"\r
+#include "component/matrix.h"\r
+#include "component/pdc.h"\r
+#include "component/pio.h"\r
+#include "component/pmc.h"\r
+#include "component/pwm.h"\r
+#include "component/rstc.h"\r
+#include "component/rswdt.h"\r
+#include "component/rtc.h"\r
+#include "component/rtt.h"\r
+#include "component/smc.h"\r
+#include "component/spi.h"\r
+#include "component/supc.h"\r
+#include "component/tc.h"\r
+#include "component/twi.h"\r
+#include "component/uart.h"\r
+#include "component/udp.h"\r
+#include "component/usart.h"\r
+#include "component/wdt.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* REGISTER ACCESS DEFINITIONS FOR SAM4E8E */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAM4E8E_reg Registers Access Definitions */\r
+/*@{*/\r
+\r
+#include "instance/pwm.h"\r
+#include "instance/aes.h"\r
+#include "instance/can0.h"\r
+#include "instance/can1.h"\r
+#include "instance/gmac.h"\r
+#include "instance/crccu.h"\r
+#include "instance/smc.h"\r
+#include "instance/uart1.h"\r
+#include "instance/hsmci.h"\r
+#include "instance/udp.h"\r
+#include "instance/spi.h"\r
+#include "instance/tc0.h"\r
+#include "instance/tc1.h"\r
+#include "instance/tc2.h"\r
+#include "instance/usart0.h"\r
+#include "instance/usart1.h"\r
+#include "instance/twi0.h"\r
+#include "instance/twi1.h"\r
+#include "instance/afec0.h"\r
+#include "instance/afec1.h"\r
+#include "instance/dacc.h"\r
+#include "instance/acc.h"\r
+#include "instance/dmac.h"\r
+#include "instance/cmcc.h"\r
+#include "instance/matrix.h"\r
+#include "instance/pmc.h"\r
+#include "instance/uart0.h"\r
+#include "instance/chipid.h"\r
+#include "instance/efc.h"\r
+#include "instance/pioa.h"\r
+#include "instance/piob.h"\r
+#include "instance/pioc.h"\r
+#include "instance/piod.h"\r
+#include "instance/pioe.h"\r
+#include "instance/rstc.h"\r
+#include "instance/supc.h"\r
+#include "instance/rtt.h"\r
+#include "instance/wdt.h"\r
+#include "instance/rtc.h"\r
+#include "instance/gpbr.h"\r
+#include "instance/rswdt.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* PERIPHERAL ID DEFINITIONS FOR SAM4E8E */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAM4E8E_id Peripheral Ids Definitions */\r
+/*@{*/\r
+\r
+#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */\r
+#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */\r
+#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */\r
+#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */\r
+#define ID_WDT ( 4) /**< \brief Watchdog/Dual Watchdog Timer (WDT) */\r
+#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */\r
+#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */\r
+#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */\r
+#define ID_SMC ( 8) /**< \brief Static Memory Controller (SMC) */\r
+#define ID_PIOA ( 9) /**< \brief Parallel I/O Controller A (PIOA) */\r
+#define ID_PIOB (10) /**< \brief Parallel I/O Controller B (PIOB) */\r
+#define ID_PIOC (11) /**< \brief Parallel I/O Controller C (PIOC) */\r
+#define ID_PIOD (12) /**< \brief Parallel I/O Controller D (PIOD) */\r
+#define ID_PIOE (13) /**< \brief Parallel I/O Controller E (PIOE) */\r
+#define ID_USART0 (14) /**< \brief USART 0 (USART0) */\r
+#define ID_USART1 (15) /**< \brief USART 1 (USART1) */\r
+#define ID_HSMCI (16) /**< \brief Multimedia Card Interface (HSMCI) */\r
+#define ID_TWI0 (17) /**< \brief Two Wire Interface 0 (TWI0) */\r
+#define ID_TWI1 (18) /**< \brief Two Wire Interface 1 (TWI1) */\r
+#define ID_SPI (19) /**< \brief Serial Peripheral Interface (SPI) */\r
+#define ID_DMAC (20) /**< \brief DMAC (DMAC) */\r
+#define ID_TC0 (21) /**< \brief Timer/Counter 0 (TC0) */\r
+#define ID_TC1 (22) /**< \brief Timer/Counter 1 (TC1) */\r
+#define ID_TC2 (23) /**< \brief Timer/Counter 2 (TC2) */\r
+#define ID_TC3 (24) /**< \brief Timer/Counter 3 (TC3) */\r
+#define ID_TC4 (25) /**< \brief Timer/Counter 4 (TC4) */\r
+#define ID_TC5 (26) /**< \brief Timer/Counter 5 (TC5) */\r
+#define ID_TC6 (27) /**< \brief Timer/Counter 6 (TC6) */\r
+#define ID_TC7 (28) /**< \brief Timer/Counter 7 (TC7) */\r
+#define ID_TC8 (29) /**< \brief Timer/Counter 8 (TC8) */\r
+#define ID_AFEC0 (30) /**< \brief Analog Front End 0 (AFEC0) */\r
+#define ID_AFEC1 (31) /**< \brief Analog Front End 1 (AFEC1) */\r
+#define ID_DACC (32) /**< \brief Digital To Analog Converter (DACC) */\r
+#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */\r
+#define ID_ARM (34) /**< \brief FPU signals : FPIXC, FPOFC, FPUFC, FPIOC, FPDZC, FPIDC, FPIXC (ARM) */\r
+#define ID_UDP (35) /**< \brief USB DEVICE (UDP) */\r
+#define ID_PWM (36) /**< \brief PWM (PWM) */\r
+#define ID_CAN0 (37) /**< \brief CAN0 (CAN0) */\r
+#define ID_CAN1 (38) /**< \brief CAN1 (CAN1) */\r
+#define ID_AES (39) /**< \brief AES (AES) */\r
+#define ID_GMAC (44) /**< \brief EMAC (GMAC) */\r
+#define ID_UART1 (45) /**< \brief UART (UART1) */\r
+\r
+#define ID_PERIPH_COUNT (46) /**< \brief Number of peripheral IDs */\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* BASE ADDRESS DEFINITIONS FOR SAM4E8E */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAM4E8E_base Peripheral Base Address Definitions */\r
+/*@{*/\r
+\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define PWM (0x40000000U) /**< \brief (PWM ) Base Address */\r
+#define PDC_PWM (0x40000100U) /**< \brief (PDC_PWM ) Base Address */\r
+#define AES (0x40004000U) /**< \brief (AES ) Base Address */\r
+#define CAN0 (0x40010000U) /**< \brief (CAN0 ) Base Address */\r
+#define CAN1 (0x40014000U) /**< \brief (CAN1 ) Base Address */\r
+#define GMAC (0x40034000U) /**< \brief (GMAC ) Base Address */\r
+#define CRCCU (0x40044000U) /**< \brief (CRCCU ) Base Address */\r
+#define SMC (0x40060000U) /**< \brief (SMC ) Base Address */\r
+#define UART1 (0x40060600U) /**< \brief (UART1 ) Base Address */\r
+#define PDC_UART1 (0x40060700U) /**< \brief (PDC_UART1 ) Base Address */\r
+#define HSMCI (0x40080000U) /**< \brief (HSMCI ) Base Address */\r
+#define PDC_HSMCI (0x40080100U) /**< \brief (PDC_HSMCI ) Base Address */\r
+#define UDP (0x40084000U) /**< \brief (UDP ) Base Address */\r
+#define SPI (0x40088000U) /**< \brief (SPI ) Base Address */\r
+#define PDC_SPI (0x40088100U) /**< \brief (PDC_SPI ) Base Address */\r
+#define TC0 (0x40090000U) /**< \brief (TC0 ) Base Address */\r
+#define PDC_TC0 (0x40090100U) /**< \brief (PDC_TC0 ) Base Address */\r
+#define TC1 (0x40094000U) /**< \brief (TC1 ) Base Address */\r
+#define PDC_TC1 (0x40094100U) /**< \brief (PDC_TC1 ) Base Address */\r
+#define TC2 (0x40098000U) /**< \brief (TC2 ) Base Address */\r
+#define USART0 (0x400A0000U) /**< \brief (USART0 ) Base Address */\r
+#define PDC_USART0 (0x400A0100U) /**< \brief (PDC_USART0) Base Address */\r
+#define USART1 (0x400A4000U) /**< \brief (USART1 ) Base Address */\r
+#define PDC_USART1 (0x400A4100U) /**< \brief (PDC_USART1) Base Address */\r
+#define TWI0 (0x400A8000U) /**< \brief (TWI0 ) Base Address */\r
+#define PDC_TWI0 (0x400A8100U) /**< \brief (PDC_TWI0 ) Base Address */\r
+#define TWI1 (0x400AC000U) /**< \brief (TWI1 ) Base Address */\r
+#define PDC_TWI1 (0x400AC100U) /**< \brief (PDC_TWI1 ) Base Address */\r
+#define AFEC0 (0x400B0000U) /**< \brief (AFEC0 ) Base Address */\r
+#define PDC_AFEC0 (0x400B0100U) /**< \brief (PDC_AFEC0 ) Base Address */\r
+#define AFEC1 (0x400B4000U) /**< \brief (AFEC1 ) Base Address */\r
+#define PDC_AFEC1 (0x400B4100U) /**< \brief (PDC_AFEC1 ) Base Address */\r
+#define DACC (0x400B8000U) /**< \brief (DACC ) Base Address */\r
+#define PDC_DACC (0x400B8100U) /**< \brief (PDC_DACC ) Base Address */\r
+#define ACC (0x400BC000U) /**< \brief (ACC ) Base Address */\r
+#define DMAC (0x400C0000U) /**< \brief (DMAC ) Base Address */\r
+#define CMCC (0x400C4000U) /**< \brief (CMCC ) Base Address */\r
+#define MATRIX (0x400E0200U) /**< \brief (MATRIX ) Base Address */\r
+#define PMC (0x400E0400U) /**< \brief (PMC ) Base Address */\r
+#define UART0 (0x400E0600U) /**< \brief (UART0 ) Base Address */\r
+#define PDC_UART0 (0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */\r
+#define CHIPID (0x400E0740U) /**< \brief (CHIPID ) Base Address */\r
+#define EFC (0x400E0A00U) /**< \brief (EFC ) Base Address */\r
+#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */\r
+#define PDC_PIOA (0x400E0F68U) /**< \brief (PDC_PIOA ) Base Address */\r
+#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */\r
+#define PIOC (0x400E1200U) /**< \brief (PIOC ) Base Address */\r
+#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */\r
+#define PIOE (0x400E1600U) /**< \brief (PIOE ) Base Address */\r
+#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */\r
+#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */\r
+#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */\r
+#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */\r
+#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */\r
+#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */\r
+#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */\r
+#else\r
+#define PWM ((Pwm *)0x40000000U) /**< \brief (PWM ) Base Address */\r
+#define PDC_PWM ((Pdc *)0x40000100U) /**< \brief (PDC_PWM ) Base Address */\r
+#define AES ((Aes *)0x40004000U) /**< \brief (AES ) Base Address */\r
+#define CAN0 ((Can *)0x40010000U) /**< \brief (CAN0 ) Base Address */\r
+#define CAN1 ((Can *)0x40014000U) /**< \brief (CAN1 ) Base Address */\r
+#define GMAC ((Gmac *)0x40034000U) /**< \brief (GMAC ) Base Address */\r
+#define CRCCU ((Crccu *)0x40044000U) /**< \brief (CRCCU ) Base Address */\r
+#define SMC ((Smc *)0x40060000U) /**< \brief (SMC ) Base Address */\r
+#define UART1 ((Uart *)0x40060600U) /**< \brief (UART1 ) Base Address */\r
+#define PDC_UART1 ((Pdc *)0x40060700U) /**< \brief (PDC_UART1 ) Base Address */\r
+#define HSMCI ((Hsmci *)0x40080000U) /**< \brief (HSMCI ) Base Address */\r
+#define PDC_HSMCI ((Pdc *)0x40080100U) /**< \brief (PDC_HSMCI ) Base Address */\r
+#define UDP ((Udp *)0x40084000U) /**< \brief (UDP ) Base Address */\r
+#define SPI ((Spi *)0x40088000U) /**< \brief (SPI ) Base Address */\r
+#define PDC_SPI ((Pdc *)0x40088100U) /**< \brief (PDC_SPI ) Base Address */\r
+#define TC0 ((Tc *)0x40090000U) /**< \brief (TC0 ) Base Address */\r
+#define PDC_TC0 ((Pdc *)0x40090100U) /**< \brief (PDC_TC0 ) Base Address */\r
+#define TC1 ((Tc *)0x40094000U) /**< \brief (TC1 ) Base Address */\r
+#define PDC_TC1 ((Pdc *)0x40094100U) /**< \brief (PDC_TC1 ) Base Address */\r
+#define TC2 ((Tc *)0x40098000U) /**< \brief (TC2 ) Base Address */\r
+#define USART0 ((Usart *)0x400A0000U) /**< \brief (USART0 ) Base Address */\r
+#define PDC_USART0 ((Pdc *)0x400A0100U) /**< \brief (PDC_USART0) Base Address */\r
+#define USART1 ((Usart *)0x400A4000U) /**< \brief (USART1 ) Base Address */\r
+#define PDC_USART1 ((Pdc *)0x400A4100U) /**< \brief (PDC_USART1) Base Address */\r
+#define TWI0 ((Twi *)0x400A8000U) /**< \brief (TWI0 ) Base Address */\r
+#define PDC_TWI0 ((Pdc *)0x400A8100U) /**< \brief (PDC_TWI0 ) Base Address */\r
+#define TWI1 ((Twi *)0x400AC000U) /**< \brief (TWI1 ) Base Address */\r
+#define PDC_TWI1 ((Pdc *)0x400AC100U) /**< \brief (PDC_TWI1 ) Base Address */\r
+#define AFEC0 ((Afec *)0x400B0000U) /**< \brief (AFEC0 ) Base Address */\r
+#define PDC_AFEC0 ((Pdc *)0x400B0100U) /**< \brief (PDC_AFEC0 ) Base Address */\r
+#define AFEC1 ((Afec *)0x400B4000U) /**< \brief (AFEC1 ) Base Address */\r
+#define PDC_AFEC1 ((Pdc *)0x400B4100U) /**< \brief (PDC_AFEC1 ) Base Address */\r
+#define DACC ((Dacc *)0x400B8000U) /**< \brief (DACC ) Base Address */\r
+#define PDC_DACC ((Pdc *)0x400B8100U) /**< \brief (PDC_DACC ) Base Address */\r
+#define ACC ((Acc *)0x400BC000U) /**< \brief (ACC ) Base Address */\r
+#define DMAC ((Dmac *)0x400C0000U) /**< \brief (DMAC ) Base Address */\r
+#define CMCC ((Cmcc *)0x400C4000U) /**< \brief (CMCC ) Base Address */\r
+#define MATRIX ((Matrix *)0x400E0200U) /**< \brief (MATRIX ) Base Address */\r
+#define PMC ((Pmc *)0x400E0400U) /**< \brief (PMC ) Base Address */\r
+#define UART0 ((Uart *)0x400E0600U) /**< \brief (UART0 ) Base Address */\r
+#define PDC_UART0 ((Pdc *)0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */\r
+#define CHIPID ((Chipid *)0x400E0740U) /**< \brief (CHIPID ) Base Address */\r
+#define EFC ((Efc *)0x400E0A00U) /**< \brief (EFC ) Base Address */\r
+#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */\r
+#define PDC_PIOA ((Pdc *)0x400E0F68U) /**< \brief (PDC_PIOA ) Base Address */\r
+#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */\r
+#define PIOC ((Pio *)0x400E1200U) /**< \brief (PIOC ) Base Address */\r
+#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */\r
+#define PIOE ((Pio *)0x400E1600U) /**< \brief (PIOE ) Base Address */\r
+#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */\r
+#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */\r
+#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */\r
+#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */\r
+#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */\r
+#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */\r
+#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* PIO DEFINITIONS FOR SAM4E8E */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAM4E8E_pio Peripheral Pio Definitions */\r
+/*@{*/\r
+\r
+#include "pio/sam4e8e.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* MEMORY MAPPING DEFINITIONS FOR SAM4E8E */\r
+/* ************************************************************************** */\r
+\r
+#define IFLASH_SIZE (0x80000u)\r
+#define IFLASH_PAGE_SIZE (512u)\r
+#define IFLASH_LOCK_REGION_SIZE (8192u)\r
+#define IFLASH_NB_OF_PAGES (1024u)\r
+#define IFLASH_NB_OF_LOCK_BITS (128u)\r
+#define IRAM_SIZE (0x20000u)\r
+\r
+#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */\r
+#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */\r
+#define IRAM_ADDR (0x20000000u) /**< Internal RAM base address */\r
+#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */\r
+#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */\r
+#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */\r
+#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */\r
+\r
+/* ************************************************************************** */\r
+/* MISCELLANEOUS DEFINITIONS FOR SAM4E8E */\r
+/* ************************************************************************** */\r
+\r
+#define CHIP_JTAGID (0x05B3703FUL)\r
+#define CHIP_CIDR (0xA3CC0CE0UL)\r
+#define CHIP_EXID (0x00120208UL)\r
+#define NB_CH_AFE0 (16UL)\r
+#define NB_CH_AFE1 (8UL)\r
+\r
+/* ************************************************************************** */\r
+/* ELECTRICAL DEFINITIONS FOR SAM4E8E */\r
+/* ************************************************************************** */\r
+\r
+/* Device characteristics */\r
+#define CHIP_FREQ_SLCK_RC_MIN (20000UL)\r
+#define CHIP_FREQ_SLCK_RC (32000UL)\r
+#define CHIP_FREQ_SLCK_RC_MAX (44000UL)\r
+#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL)\r
+#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL)\r
+#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL)\r
+#define CHIP_FREQ_CPU_MAX (120000000UL)\r
+#define CHIP_FREQ_XTAL_32K (32768UL)\r
+#define CHIP_FREQ_XTAL_12M (12000000UL)\r
+\r
+/* Embedded Flash Write Wait State */\r
+#define CHIP_FLASH_WRITE_WAIT_STATE (6U)\r
+\r
+/* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */\r
+#define CHIP_FREQ_FWS_0 (20000000UL) /**< \brief Maximum operating frequency when FWS is 0 */\r
+#define CHIP_FREQ_FWS_1 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */\r
+#define CHIP_FREQ_FWS_2 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */\r
+#define CHIP_FREQ_FWS_3 (80000000UL) /**< \brief Maximum operating frequency when FWS is 3 */\r
+#define CHIP_FREQ_FWS_4 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */\r
+#define CHIP_FREQ_FWS_5 (123000000UL) /**< \brief Maximum operating frequency when FWS is 5 */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+/*@}*/\r
+\r
+#endif /* _SAM4E8E_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief This file contains the default exception handlers.\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ * \par Purpose\r
+ *\r
+ * This file provides basic support for Cortex-M processor based\r
+ * microcontrollers.\r
+ *\r
+ * \note\r
+ * The exception handler has weak aliases.\r
+ * As they are weak aliases, any function with the same name will override\r
+ * this definition.\r
+ *\r
+ */\r
+\r
+#include "exceptions.h"\r
+\r
+/* @cond 0 */\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+/**INDENT-ON**/\r
+/* @endcond */\r
+\r
+#ifdef __GNUC__\r
+/* Cortex-M4 core handlers */\r
+void Reset_Handler (void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void NMI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void HardFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void MemManage_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void BusFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void UsageFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void SVC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void DebugMon_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void PendSV_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void SysTick_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+\r
+/* Peripherals handlers */\r
+void SUPC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void RSTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void RTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void RTT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void WDT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void PMC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void EFC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void UART0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void SMC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void PIOA_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void PIOB_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void PIOC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void PIOD_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void PIOE_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void USART0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void USART1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void HSMCI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void TWI0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void TWI1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void SPI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void DMAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void TC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void TC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void TC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void TC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void TC4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void TC5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void TC6_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void TC7_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void TC8_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void AFEC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void AFEC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void DACC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void ACC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void ARM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void UDP_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void PWM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void CAN0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void CAN1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void AES_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void GMAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void UART1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+#endif /* __GNUC__ */\r
+\r
+#ifdef __ICCARM__\r
+/* Cortex-M4 core handlers */\r
+#pragma weak Reset_Handler=Dummy_Handler\r
+#pragma weak NMI_Handler=Dummy_Handler\r
+#pragma weak HardFault_Handler=Dummy_Handler\r
+#pragma weak MemManage_Handler=Dummy_Handler\r
+#pragma weak BusFault_Handler=Dummy_Handler\r
+#pragma weak UsageFault_Handler=Dummy_Handler\r
+#pragma weak SVC_Handler=Dummy_Handler\r
+#pragma weak DebugMon_Handler=Dummy_Handler\r
+#pragma weak PendSV_Handler=Dummy_Handler\r
+#pragma weak SysTick_Handler=Dummy_Handler\r
+\r
+/* Peripherals handlers */\r
+#pragma weak SUPC_Handler=Dummy_Handler\r
+#pragma weak RSTC_Handler=Dummy_Handler\r
+#pragma weak RTC_Handler=Dummy_Handler\r
+#pragma weak RTT_Handler=Dummy_Handler\r
+#pragma weak WDT_Handler=Dummy_Handler\r
+#pragma weak PMC_Handler=Dummy_Handler\r
+#pragma weak EFC_Handler=Dummy_Handler\r
+#pragma weak UART0_Handler=Dummy_Handler\r
+#pragma weak SMC_Handler=Dummy_Handler\r
+#pragma weak PIOA_Handler=Dummy_Handler\r
+#pragma weak PIOB_Handler=Dummy_Handler\r
+#pragma weak PIOC_Handler=Dummy_Handler\r
+#pragma weak PIOD_Handler=Dummy_Handler\r
+#pragma weak PIOE_Handler=Dummy_Handler\r
+#pragma weak USART0_Handler=Dummy_Handler\r
+#pragma weak USART1_Handler=Dummy_Handler\r
+#pragma weak HSMCI_Handler=Dummy_Handler\r
+#pragma weak TWI0_Handler=Dummy_Handler\r
+#pragma weak TWI1_Handler=Dummy_Handler\r
+#pragma weak SPI_Handler=Dummy_Handler\r
+#pragma weak DMAC_Handler=Dummy_Handler\r
+#pragma weak TC0_Handler=Dummy_Handler\r
+#pragma weak TC1_Handler=Dummy_Handler\r
+#pragma weak TC2_Handler=Dummy_Handler\r
+#pragma weak TC3_Handler=Dummy_Handler\r
+#pragma weak TC4_Handler=Dummy_Handler\r
+#pragma weak TC5_Handler=Dummy_Handler\r
+#pragma weak TC6_Handler=Dummy_Handler\r
+#pragma weak TC7_Handler=Dummy_Handler\r
+#pragma weak TC8_Handler=Dummy_Handler\r
+#pragma weak AFEC0_Handler=Dummy_Handler\r
+#pragma weak AFEC1_Handler=Dummy_Handler\r
+#pragma weak DACC_Handler=Dummy_Handler\r
+#pragma weak ACC_Handler=Dummy_Handler\r
+#pragma weak ARM_Handler=Dummy_Handler\r
+#pragma weak UDP_Handler=Dummy_Handler\r
+#pragma weak PWM_Handler=Dummy_Handler\r
+#pragma weak CAN0_Handler=Dummy_Handler\r
+#pragma weak CAN1_Handler=Dummy_Handler\r
+#pragma weak AES_Handler=Dummy_Handler\r
+#pragma weak GMAC_Handler=Dummy_Handler\r
+#pragma weak UART1_Handler=Dummy_Handler\r
+#endif /* __ICCARM__ */\r
+\r
+/**\r
+ * \brief Default interrupt handler for unused IRQs.\r
+ */\r
+void Dummy_Handler(void)\r
+{\r
+ while (1) {\r
+ }\r
+}\r
+\r
+/* @cond 0 */\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+/**INDENT-ON**/\r
+/* @endcond */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief This file contains the interface for default exception handlers.\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef EXCEPTIONS_H_INCLUDED\r
+#define EXCEPTIONS_H_INCLUDED\r
+\r
+#include "sam4e.h"\r
+\r
+/* @cond 0 */\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+/**INDENT-ON**/\r
+/* @endcond */\r
+\r
+/* Function prototype for exception table items (interrupt handler). */\r
+typedef void (*IntFunc) (void);\r
+\r
+/* Default empty handler */\r
+void Dummy_Handler(void);\r
+\r
+/* @cond 0 */\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+/**INDENT-ON**/\r
+/* @endcond */\r
+\r
+#endif /* EXCEPTIONS_H_INCLUDED */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Startup file for SAM4E.\r
+ *\r
+ * Copyright (c) 2012 - 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#include "sam4e.h"\r
+#include "exceptions.h"\r
+#include "system_sam4e.h"\r
+#if __FPU_USED /* CMSIS defined value to indicate usage of FPU */\r
+#include "fpu.h"\r
+#endif\r
+\r
+/* Initialize segments */\r
+extern uint32_t _sfixed;\r
+extern uint32_t _efixed;\r
+extern uint32_t _etext;\r
+extern uint32_t _srelocate;\r
+extern uint32_t _erelocate;\r
+extern uint32_t _szero;\r
+extern uint32_t _ezero;\r
+extern uint32_t _sstack;\r
+extern uint32_t _estack;\r
+\r
+/** \cond DOXYGEN_SHOULD_SKIP_THIS */\r
+int main(void);\r
+/** \endcond */\r
+\r
+void __libc_init_array(void);\r
+\r
+/* Exception Table */\r
+__attribute__ ((section(".vectors")))\r
+const DeviceVectors exception_table = {\r
+\r
+ /* Configure Initial Stack Pointer, using linker-generated symbols */\r
+ (void*) (&_estack),\r
+\r
+ (void*) Reset_Handler,\r
+ (void*) NMI_Handler,\r
+ (void*) HardFault_Handler,\r
+ (void*) MemManage_Handler,\r
+ (void*) BusFault_Handler,\r
+ (void*) UsageFault_Handler,\r
+ (void*) (0UL), /* Reserved */\r
+ (void*) (0UL), /* Reserved */\r
+ (void*) (0UL), /* Reserved */\r
+ (void*) (0UL), /* Reserved */\r
+ (void*) SVC_Handler,\r
+ (void*) DebugMon_Handler,\r
+ (void*) (0UL), /* Reserved */\r
+ (void*) PendSV_Handler,\r
+ (void*) SysTick_Handler,\r
+\r
+ /* Configurable interrupts */\r
+ (void*) SUPC_Handler, /* 0 Supply Controller */\r
+ (void*) RSTC_Handler, /* 1 Reset Controller */\r
+ (void*) RTC_Handler, /* 2 Real Time Clock */\r
+ (void*) RTT_Handler, /* 3 Real Time Timer */\r
+ (void*) WDT_Handler, /* 4 Watchdog/Dual Watchdog Timer */\r
+ (void*) PMC_Handler, /* 5 Power Management Controller */\r
+ (void*) EFC_Handler, /* 6 Enhanced Embedded Flash Controller */\r
+ (void*) UART0_Handler, /* 7 UART 0 */\r
+ (void*) Dummy_Handler,\r
+ (void*) PIOA_Handler, /* 9 Parallel I/O Controller A */\r
+ (void*) PIOB_Handler, /* 10 Parallel I/O Controller B */\r
+ (void*) PIOC_Handler, /* 11 Parallel I/O Controller C */\r
+#ifdef _SAM4E_PIOD_INSTANCE_\r
+ (void*) PIOD_Handler, /* 12 Parallel I/O Controller D */\r
+#else\r
+ (void*) Dummy_Handler,\r
+#endif\r
+#ifdef _SAM4E_PIOE_INSTANCE_\r
+ (void*) PIOE_Handler, /* 13 Parallel I/O Controller E */\r
+#else\r
+ (void*) Dummy_Handler,\r
+#endif\r
+ (void*) USART0_Handler, /* 14 USART 0 */\r
+ (void*) USART1_Handler, /* 15 USART 1 */\r
+ (void*) HSMCI_Handler, /* 16 Multimedia Card Interface */\r
+ (void*) TWI0_Handler, /* 17 Two Wire Interface 0 */\r
+ (void*) TWI1_Handler, /* 18 Two Wire Interface 1 */\r
+ (void*) SPI_Handler, /* 19 Serial Peripheral Interface */\r
+ (void*) DMAC_Handler, /* 20 DMAC */\r
+ (void*) TC0_Handler, /* 21 Timer/Counter 0 */\r
+ (void*) TC1_Handler, /* 22 Timer/Counter 1 */\r
+ (void*) TC2_Handler, /* 23 Timer/Counter 2 */\r
+ (void*) TC3_Handler, /* 24 Timer/Counter 3 */\r
+ (void*) TC4_Handler, /* 25 Timer/Counter 4 */\r
+ (void*) TC5_Handler, /* 26 Timer/Counter 5 */\r
+ (void*) TC6_Handler, /* 27 Timer/Counter 6 */\r
+ (void*) TC7_Handler, /* 28 Timer/Counter 7 */\r
+ (void*) TC8_Handler, /* 29 Timer/Counter 8 */\r
+ (void*) AFEC0_Handler, /* 30 Analog Front End 0 */\r
+ (void*) AFEC1_Handler, /* 31 Analog Front End 1 */\r
+ (void*) DACC_Handler, /* 32 Digital To Analog Converter */\r
+ (void*) ACC_Handler, /* 33 Analog Comparator */\r
+ (void*) ARM_Handler, /* 34 FPU signals : FPIXC, FPOFC, FPUFC, FPIOC, FPDZC, FPIDC, FPIXC */\r
+ (void*) UDP_Handler, /* 35 USB DEVICE */\r
+ (void*) PWM_Handler, /* 36 PWM */\r
+ (void*) CAN0_Handler, /* 37 CAN0 */\r
+ (void*) CAN1_Handler, /* 38 CAN1 */\r
+ (void*) AES_Handler, /* 39 AES */\r
+ (void*) Dummy_Handler,\r
+ (void*) Dummy_Handler,\r
+ (void*) Dummy_Handler,\r
+ (void*) Dummy_Handler,\r
+#ifdef _SAM4E_GMAC_INSTANCE_\r
+ (void*) GMAC_Handler, /* 44 EMAC */\r
+#else\r
+ (void*) Dummy_Handler,\r
+#endif\r
+ (void*) UART1_Handler /* 45 UART */\r
+};\r
+\r
+/**\r
+ * \brief This is the code that gets called on processor reset.\r
+ * To initialize the device, and call the main() routine.\r
+ */\r
+void Reset_Handler(void)\r
+{\r
+ uint32_t *pSrc, *pDest;\r
+\r
+ /* Initialize the relocate segment */\r
+ pSrc = &_etext;\r
+ pDest = &_srelocate;\r
+\r
+ if (pSrc != pDest) {\r
+ for (; pDest < &_erelocate;) {\r
+ *pDest++ = *pSrc++;\r
+ }\r
+ }\r
+\r
+ /* Clear the zero segment */\r
+ for (pDest = &_szero; pDest < &_ezero;) {\r
+ *pDest++ = 0;\r
+ }\r
+\r
+ /* Set the vector table base address */\r
+ pSrc = (uint32_t *) & _sfixed;\r
+ SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);\r
+\r
+#if __FPU_USED\r
+ fpu_enable();\r
+#endif\r
+\r
+ /* Initialize the C library */\r
+ __libc_init_array();\r
+\r
+ /* Branch to main function */\r
+ main();\r
+\r
+ /* Infinite loop */\r
+ while (1);\r
+}\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Provides the low-level initialization functions that called\r
+ * on chip startup.\r
+ *\r
+ * Copyright (c) 2011 - 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#include "sam4e.h"\r
+\r
+/* @cond 0 */\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+/**INDENT-ON**/\r
+/* @endcond */\r
+\r
+/* Clock Settings (120MHz) */\r
+#define SYS_BOARD_OSCOUNT (CKGR_MOR_MOSCXTST(0x8U))\r
+#define SYS_BOARD_PLLAR (CKGR_PLLAR_ONE \\r
+ | CKGR_PLLAR_MULA(0x13U) \\r
+ | CKGR_PLLAR_PLLACOUNT(0x3fU) \\r
+ | CKGR_PLLAR_DIVA(0x1U))\r
+#define SYS_BOARD_MCKR (PMC_MCKR_PRES_CLK_2 | PMC_MCKR_CSS_PLLA_CLK)\r
+\r
+#define SYS_CKGR_MOR_KEY_VALUE CKGR_MOR_KEY(0x37) /* Key to unlock MOR register */\r
+\r
+uint32_t SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ;\r
+\r
+/**\r
+ * \brief Setup the microcontroller system.\r
+ * Initialize the System and update the SystemFrequency variable.\r
+ */\r
+void SystemInit( void )\r
+{\r
+ /* Set FWS according to SYS_BOARD_MCKR configuration */\r
+ EFC->EEFC_FMR = EEFC_FMR_FWS(5);\r
+\r
+ /* Initialize main oscillator */\r
+ if ( !(PMC->CKGR_MOR & CKGR_MOR_MOSCSEL) ) {\r
+ PMC->CKGR_MOR = SYS_CKGR_MOR_KEY_VALUE | SYS_BOARD_OSCOUNT |\r
+ CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN;\r
+\r
+ while ( !(PMC->PMC_SR & PMC_SR_MOSCXTS) ) {\r
+ }\r
+ }\r
+\r
+ /* Switch to 3-20MHz Xtal oscillator */\r
+ PMC->CKGR_MOR = SYS_CKGR_MOR_KEY_VALUE | SYS_BOARD_OSCOUNT |\r
+ CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN |\r
+ CKGR_MOR_MOSCSEL;\r
+\r
+ while ( !(PMC->PMC_SR & PMC_SR_MOSCSELS) ) {\r
+ }\r
+\r
+ PMC->PMC_MCKR = (PMC->PMC_MCKR & ~(uint32_t)PMC_MCKR_CSS_Msk) |\r
+ PMC_MCKR_CSS_MAIN_CLK;\r
+\r
+ while ( !(PMC->PMC_SR & PMC_SR_MCKRDY) ) {\r
+ }\r
+\r
+ /* Initialize PLLA */\r
+ PMC->CKGR_PLLAR = SYS_BOARD_PLLAR;\r
+ while ( !(PMC->PMC_SR & PMC_SR_LOCKA) ) {\r
+ }\r
+\r
+ /* Switch to main clock */\r
+ PMC->PMC_MCKR = (SYS_BOARD_MCKR & ~PMC_MCKR_CSS_Msk) |\r
+ PMC_MCKR_CSS_MAIN_CLK;\r
+ while ( !(PMC->PMC_SR & PMC_SR_MCKRDY) ) {\r
+ }\r
+\r
+ /* Switch to PLLA */\r
+ PMC->PMC_MCKR = SYS_BOARD_MCKR;\r
+ while ( !(PMC->PMC_SR & PMC_SR_MCKRDY) ) {\r
+ }\r
+\r
+ SystemCoreClock = CHIP_FREQ_CPU_MAX;\r
+}\r
+\r
+void SystemCoreClockUpdate( void )\r
+{\r
+ /* Determine clock frequency according to clock register values */\r
+ switch (PMC->PMC_MCKR & (uint32_t) PMC_MCKR_CSS_Msk) {\r
+ case PMC_MCKR_CSS_SLOW_CLK: /* Slow clock */\r
+ if ( SUPC->SUPC_SR & SUPC_SR_OSCSEL ) {\r
+ SystemCoreClock = CHIP_FREQ_XTAL_32K;\r
+ } else {\r
+ SystemCoreClock = CHIP_FREQ_SLCK_RC;\r
+ }\r
+ break;\r
+\r
+ case PMC_MCKR_CSS_MAIN_CLK: /* Main clock */\r
+ if ( PMC->CKGR_MOR & CKGR_MOR_MOSCSEL ) {\r
+ SystemCoreClock = CHIP_FREQ_XTAL_12M;\r
+ } else {\r
+ SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ;\r
+\r
+ switch ( PMC->CKGR_MOR & CKGR_MOR_MOSCRCF_Msk ) {\r
+ case CKGR_MOR_MOSCRCF_4_MHz:\r
+ break;\r
+\r
+ case CKGR_MOR_MOSCRCF_8_MHz:\r
+ SystemCoreClock *= 2U;\r
+ break;\r
+\r
+ case CKGR_MOR_MOSCRCF_12_MHz:\r
+ SystemCoreClock *= 3U;\r
+ break;\r
+\r
+ default:\r
+ break;\r
+ }\r
+ }\r
+ break;\r
+\r
+ case PMC_MCKR_CSS_PLLA_CLK: /* PLLA clock */\r
+ if ( PMC->CKGR_MOR & CKGR_MOR_MOSCSEL ) {\r
+ SystemCoreClock = CHIP_FREQ_XTAL_12M ;\r
+ } else {\r
+ SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ;\r
+\r
+ switch ( PMC->CKGR_MOR & CKGR_MOR_MOSCRCF_Msk ) {\r
+ case CKGR_MOR_MOSCRCF_4_MHz:\r
+ break;\r
+\r
+ case CKGR_MOR_MOSCRCF_8_MHz:\r
+ SystemCoreClock *= 2U;\r
+ break;\r
+\r
+ case CKGR_MOR_MOSCRCF_12_MHz:\r
+ SystemCoreClock *= 3U;\r
+ break;\r
+\r
+ default:\r
+ break;\r
+ }\r
+ }\r
+\r
+ if ((uint32_t) (PMC->PMC_MCKR & (uint32_t) PMC_MCKR_CSS_Msk) == PMC_MCKR_CSS_PLLA_CLK)\r
+ {\r
+ SystemCoreClock *= ((((PMC->CKGR_PLLAR) & CKGR_PLLAR_MULA_Msk) >> CKGR_PLLAR_MULA_Pos) + 1U);\r
+ SystemCoreClock /= ((((PMC->CKGR_PLLAR) & CKGR_PLLAR_DIVA_Msk) >> CKGR_PLLAR_DIVA_Pos));\r
+ }\r
+ break;\r
+\r
+ default:\r
+ break;\r
+ }\r
+\r
+ if ((PMC->PMC_MCKR & PMC_MCKR_PRES_Msk) == PMC_MCKR_PRES_CLK_3) {\r
+ SystemCoreClock /= 3U;\r
+ } else {\r
+ SystemCoreClock >>= ((PMC->PMC_MCKR & PMC_MCKR_PRES_Msk) >>\r
+ PMC_MCKR_PRES_Pos);\r
+ }\r
+}\r
+\r
+/**\r
+ * Initialize flash.\r
+ */\r
+void system_init_flash( uint32_t ul_clk )\r
+{\r
+ /* Set FWS for embedded Flash access according to operating frequency */\r
+ if ( ul_clk < CHIP_FREQ_FWS_0 ) {\r
+ EFC->EEFC_FMR = EEFC_FMR_FWS(0);\r
+ } else {\r
+ if (ul_clk < CHIP_FREQ_FWS_1) {\r
+ EFC->EEFC_FMR = EEFC_FMR_FWS(1);\r
+ } else {\r
+ if (ul_clk < CHIP_FREQ_FWS_2) {\r
+ EFC->EEFC_FMR = EEFC_FMR_FWS(2);\r
+ } else {\r
+ if ( ul_clk < CHIP_FREQ_FWS_3 ) {\r
+ EFC->EEFC_FMR = EEFC_FMR_FWS(3);\r
+ } else {\r
+ if ( ul_clk < CHIP_FREQ_FWS_4 ) {\r
+ EFC->EEFC_FMR = EEFC_FMR_FWS(4);\r
+ } else {\r
+ EFC->EEFC_FMR = EEFC_FMR_FWS(5);\r
+ }\r
+ }\r
+ }\r
+ }\r
+ }\r
+}\r
+\r
+/* @cond 0 */\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+/**INDENT-ON**/\r
+/* @endcond */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Provides the low-level initialization functions that called\r
+ * on chip startup.\r
+ *\r
+ * Copyright (c) 2011 - 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef SYSTEM_SAM4E_H_INCLUDED\r
+#define SYSTEM_SAM4E_H_INCLUDED\r
+\r
+/* @cond 0 */\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+/**INDENT-ON**/\r
+/* @endcond */\r
+\r
+#include <stdint.h>\r
+\r
+extern uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock) */\r
+\r
+/**\r
+ * @brief Setup the microcontroller system.\r
+ * Initialize the System and update the SystemCoreClock variable.\r
+ */\r
+void SystemInit(void);\r
+\r
+/**\r
+ * @brief Updates the SystemCoreClock with current core Clock\r
+ * retrieved from cpu registers.\r
+ */\r
+void SystemCoreClockUpdate(void);\r
+\r
+/**\r
+ * Initialize flash.\r
+ */\r
+void system_init_flash(uint32_t dw_clk);\r
+\r
+/* @cond 0 */\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+/**INDENT-ON**/\r
+/* @endcond */\r
+\r
+#endif /* SYSTEM_SAM4E_H_INCLUDED */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Commonly used includes, types and macros.\r
+ *\r
+ * Copyright (c) 2010-2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef UTILS_COMPILER_H\r
+#define UTILS_COMPILER_H\r
+\r
+/**\r
+ * \defgroup group_sam_utils Compiler abstraction layer and code utilities\r
+ *\r
+ * Compiler abstraction layer and code utilities for AT91SAM.\r
+ * This module provides various abstraction layers and utilities to make code compatible between different compilers.\r
+ *\r
+ * \{\r
+ */\r
+#include <stddef.h>\r
+\r
+#if (defined __ICCARM__)\r
+# include <intrinsics.h>\r
+#endif\r
+\r
+#include <parts.h>\r
+#include "preprocessor.h"\r
+\r
+#include <io.h>\r
+\r
+//_____ D E C L A R A T I O N S ____________________________________________\r
+\r
+#ifndef __ASSEMBLY__ // Not defined for assembling.\r
+\r
+#include <stdio.h>\r
+#include <stdbool.h>\r
+#include <stdint.h>\r
+#include <stdlib.h>\r
+\r
+#ifdef __ICCARM__\r
+/*! \name Compiler Keywords\r
+ *\r
+ * Port of some keywords from GCC to IAR Embedded Workbench.\r
+ */\r
+//! @{\r
+#define __asm__ asm\r
+#define __inline__ inline\r
+#define __volatile__\r
+//! @}\r
+\r
+#endif\r
+\r
+#define FUNC_PTR void *\r
+/**\r
+ * \def UNUSED\r
+ * \brief Marking \a v as a unused parameter or value.\r
+ */\r
+#define UNUSED(v) (void)(v)\r
+\r
+/**\r
+ * \def unused\r
+ * \brief Marking \a v as a unused parameter or value.\r
+ */\r
+#define unused(v) do { (void)(v); } while(0)\r
+\r
+/**\r
+ * \def barrier\r
+ * \brief Memory barrier\r
+ */\r
+#define barrier() __DMB()\r
+\r
+/**\r
+ * \brief Emit the compiler pragma \a arg.\r
+ *\r
+ * \param arg The pragma directive as it would appear after \e \#pragma\r
+ * (i.e. not stringified).\r
+ */\r
+#define COMPILER_PRAGMA(arg) _Pragma(#arg)\r
+\r
+/**\r
+ * \def COMPILER_PACK_SET(alignment)\r
+ * \brief Set maximum alignment for subsequent struct and union\r
+ * definitions to \a alignment.\r
+ */\r
+#define COMPILER_PACK_SET(alignment) COMPILER_PRAGMA(pack(alignment))\r
+\r
+/**\r
+ * \def COMPILER_PACK_RESET()\r
+ * \brief Set default alignment for subsequent struct and union\r
+ * definitions.\r
+ */\r
+#define COMPILER_PACK_RESET() COMPILER_PRAGMA(pack())\r
+\r
+\r
+/**\r
+ * \brief Set aligned boundary.\r
+ */\r
+#if (defined __GNUC__) || (defined __CC_ARM)\r
+# define COMPILER_ALIGNED(a) __attribute__((__aligned__(a)))\r
+#elif (defined __ICCARM__)\r
+# define COMPILER_ALIGNED(a) COMPILER_PRAGMA(data_alignment = a)\r
+#endif\r
+\r
+/**\r
+ * \brief Set word-aligned boundary.\r
+ */\r
+#if (defined __GNUC__) || defined(__CC_ARM)\r
+#define COMPILER_WORD_ALIGNED __attribute__((__aligned__(4)))\r
+#elif (defined __ICCARM__)\r
+#define COMPILER_WORD_ALIGNED COMPILER_PRAGMA(data_alignment = 4)\r
+#endif\r
+\r
+/**\r
+ * \def __always_inline\r
+ * \brief The function should always be inlined.\r
+ *\r
+ * This annotation instructs the compiler to ignore its inlining\r
+ * heuristics and inline the function no matter how big it thinks it\r
+ * becomes.\r
+ */\r
+#if defined(__CC_ARM)\r
+# define __always_inline __forceinline\r
+#elif (defined __GNUC__)\r
+# define __always_inline inline __attribute__((__always_inline__))\r
+#elif (defined __ICCARM__)\r
+# define __always_inline _Pragma("inline=forced")\r
+#endif\r
+\r
+/*! \brief This macro is used to test fatal errors.\r
+ *\r
+ * The macro tests if the expression is false. If it is, a fatal error is\r
+ * detected and the application hangs up. If TEST_SUITE_DEFINE_ASSERT_MACRO\r
+ * is defined, a unit test version of the macro is used, to allow execution\r
+ * of further tests after a false expression.\r
+ *\r
+ * \param expr Expression to evaluate and supposed to be nonzero.\r
+ */\r
+#if defined(_ASSERT_ENABLE_)\r
+# if defined(TEST_SUITE_DEFINE_ASSERT_MACRO)\r
+ // Assert() is defined in unit_test/suite.h\r
+# include "unit_test/suite.h"\r
+# else\r
+#undef TEST_SUITE_DEFINE_ASSERT_MACRO\r
+# define Assert(expr) \\r
+ {\\r
+ if (!(expr)) while (true);\\r
+ }\r
+# endif\r
+#else\r
+# define Assert(expr) ((void) 0)\r
+#endif\r
+\r
+/* Define WEAK attribute */\r
+#if defined ( __CC_ARM ) /* Keil µVision 4 */\r
+# define WEAK __attribute__ ((weak))\r
+#elif defined ( __ICCARM__ ) /* IAR Ewarm 5.41+ */\r
+# define WEAK __weak\r
+#elif defined ( __GNUC__ ) /* GCC CS3 2009q3-68 */\r
+# define WEAK __attribute__ ((weak))\r
+#endif\r
+\r
+/* Define NO_INIT attribute */\r
+#if defined ( __CC_ARM )\r
+# define NO_INIT __attribute__((zero_init))\r
+#elif defined ( __ICCARM__ )\r
+# define NO_INIT __no_init\r
+#elif defined ( __GNUC__ )\r
+# define NO_INIT __attribute__((section(".no_init")))\r
+#endif\r
+\r
+/* Define RAMFUNC attribute */\r
+#if defined ( __CC_ARM ) /* Keil µVision 4 */\r
+# define RAMFUNC __attribute__ ((section(".ramfunc")))\r
+#elif defined ( __ICCARM__ ) /* IAR Ewarm 5.41+ */\r
+# define RAMFUNC __ramfunc\r
+#elif defined ( __GNUC__ ) /* GCC CS3 2009q3-68 */\r
+# define RAMFUNC __attribute__ ((section(".ramfunc")))\r
+#endif\r
+\r
+/* Define OPTIMIZE_HIGH attribute */\r
+#if defined ( __CC_ARM ) /* Keil µVision 4 */\r
+# define OPTIMIZE_HIGH _Pragma("O3") \r
+#elif defined ( __ICCARM__ ) /* IAR Ewarm 5.41+ */\r
+# define OPTIMIZE_HIGH _Pragma("optimize=high")\r
+#elif defined ( __GNUC__ ) /* GCC CS3 2009q3-68 */\r
+# define OPTIMIZE_HIGH __attribute__((optimize(s)))\r
+#endif\r
+\r
+#include "interrupt.h"\r
+\r
+/*! \name Usual Types\r
+ */\r
+//! @{\r
+typedef unsigned char Bool; //!< Boolean.\r
+#ifndef __cplusplus\r
+#if !defined(__bool_true_false_are_defined)\r
+typedef unsigned char bool; //!< Boolean.\r
+#endif\r
+#endif\r
+typedef int8_t S8 ; //!< 8-bit signed integer.\r
+typedef uint8_t U8 ; //!< 8-bit unsigned integer.\r
+typedef int16_t S16; //!< 16-bit signed integer.\r
+typedef uint16_t U16; //!< 16-bit unsigned integer.\r
+typedef uint16_t le16_t;\r
+typedef uint16_t be16_t;\r
+typedef int32_t S32; //!< 32-bit signed integer.\r
+typedef uint32_t U32; //!< 32-bit unsigned integer.\r
+typedef uint32_t le32_t;\r
+typedef uint32_t be32_t;\r
+typedef int64_t S64; //!< 64-bit signed integer.\r
+typedef uint64_t U64; //!< 64-bit unsigned integer.\r
+typedef float F32; //!< 32-bit floating-point number.\r
+typedef double F64; //!< 64-bit floating-point number.\r
+typedef uint32_t iram_size_t;\r
+//! @}\r
+\r
+\r
+/*! \name Status Types\r
+ */\r
+//! @{\r
+typedef bool Status_bool_t; //!< Boolean status.\r
+typedef U8 Status_t; //!< 8-bit-coded status.\r
+//! @}\r
+\r
+\r
+/*! \name Aliasing Aggregate Types\r
+ */\r
+//! @{\r
+\r
+//! 16-bit union.\r
+typedef union\r
+{\r
+ S16 s16 ;\r
+ U16 u16 ;\r
+ S8 s8 [2];\r
+ U8 u8 [2];\r
+} Union16;\r
+\r
+//! 32-bit union.\r
+typedef union\r
+{\r
+ S32 s32 ;\r
+ U32 u32 ;\r
+ S16 s16[2];\r
+ U16 u16[2];\r
+ S8 s8 [4];\r
+ U8 u8 [4];\r
+} Union32;\r
+\r
+//! 64-bit union.\r
+typedef union\r
+{\r
+ S64 s64 ;\r
+ U64 u64 ;\r
+ S32 s32[2];\r
+ U32 u32[2];\r
+ S16 s16[4];\r
+ U16 u16[4];\r
+ S8 s8 [8];\r
+ U8 u8 [8];\r
+} Union64;\r
+\r
+//! Union of pointers to 64-, 32-, 16- and 8-bit unsigned integers.\r
+typedef union\r
+{\r
+ S64 *s64ptr;\r
+ U64 *u64ptr;\r
+ S32 *s32ptr;\r
+ U32 *u32ptr;\r
+ S16 *s16ptr;\r
+ U16 *u16ptr;\r
+ S8 *s8ptr ;\r
+ U8 *u8ptr ;\r
+} UnionPtr;\r
+\r
+//! Union of pointers to volatile 64-, 32-, 16- and 8-bit unsigned integers.\r
+typedef union\r
+{\r
+ volatile S64 *s64ptr;\r
+ volatile U64 *u64ptr;\r
+ volatile S32 *s32ptr;\r
+ volatile U32 *u32ptr;\r
+ volatile S16 *s16ptr;\r
+ volatile U16 *u16ptr;\r
+ volatile S8 *s8ptr ;\r
+ volatile U8 *u8ptr ;\r
+} UnionVPtr;\r
+\r
+//! Union of pointers to constant 64-, 32-, 16- and 8-bit unsigned integers.\r
+typedef union\r
+{\r
+ const S64 *s64ptr;\r
+ const U64 *u64ptr;\r
+ const S32 *s32ptr;\r
+ const U32 *u32ptr;\r
+ const S16 *s16ptr;\r
+ const U16 *u16ptr;\r
+ const S8 *s8ptr ;\r
+ const U8 *u8ptr ;\r
+} UnionCPtr;\r
+\r
+//! Union of pointers to constant volatile 64-, 32-, 16- and 8-bit unsigned integers.\r
+typedef union\r
+{\r
+ const volatile S64 *s64ptr;\r
+ const volatile U64 *u64ptr;\r
+ const volatile S32 *s32ptr;\r
+ const volatile U32 *u32ptr;\r
+ const volatile S16 *s16ptr;\r
+ const volatile U16 *u16ptr;\r
+ const volatile S8 *s8ptr ;\r
+ const volatile U8 *u8ptr ;\r
+} UnionCVPtr;\r
+\r
+//! Structure of pointers to 64-, 32-, 16- and 8-bit unsigned integers.\r
+typedef struct\r
+{\r
+ S64 *s64ptr;\r
+ U64 *u64ptr;\r
+ S32 *s32ptr;\r
+ U32 *u32ptr;\r
+ S16 *s16ptr;\r
+ U16 *u16ptr;\r
+ S8 *s8ptr ;\r
+ U8 *u8ptr ;\r
+} StructPtr;\r
+\r
+//! Structure of pointers to volatile 64-, 32-, 16- and 8-bit unsigned integers.\r
+typedef struct\r
+{\r
+ volatile S64 *s64ptr;\r
+ volatile U64 *u64ptr;\r
+ volatile S32 *s32ptr;\r
+ volatile U32 *u32ptr;\r
+ volatile S16 *s16ptr;\r
+ volatile U16 *u16ptr;\r
+ volatile S8 *s8ptr ;\r
+ volatile U8 *u8ptr ;\r
+} StructVPtr;\r
+\r
+//! Structure of pointers to constant 64-, 32-, 16- and 8-bit unsigned integers.\r
+typedef struct\r
+{\r
+ const S64 *s64ptr;\r
+ const U64 *u64ptr;\r
+ const S32 *s32ptr;\r
+ const U32 *u32ptr;\r
+ const S16 *s16ptr;\r
+ const U16 *u16ptr;\r
+ const S8 *s8ptr ;\r
+ const U8 *u8ptr ;\r
+} StructCPtr;\r
+\r
+//! Structure of pointers to constant volatile 64-, 32-, 16- and 8-bit unsigned integers.\r
+typedef struct\r
+{\r
+ const volatile S64 *s64ptr;\r
+ const volatile U64 *u64ptr;\r
+ const volatile S32 *s32ptr;\r
+ const volatile U32 *u32ptr;\r
+ const volatile S16 *s16ptr;\r
+ const volatile U16 *u16ptr;\r
+ const volatile S8 *s8ptr ;\r
+ const volatile U8 *u8ptr ;\r
+} StructCVPtr;\r
+\r
+//! @}\r
+\r
+#endif // #ifndef __ASSEMBLY__\r
+\r
+/*! \name Usual Constants\r
+ */\r
+//! @{\r
+#define DISABLE 0\r
+#define ENABLE 1\r
+#ifndef __cplusplus\r
+#if !defined(__bool_true_false_are_defined)\r
+#define false 0\r
+#define true 1\r
+#endif\r
+#endif\r
+#define PASS 0\r
+#define FAIL 1\r
+#define LOW 0\r
+#define HIGH 1\r
+//! @}\r
+\r
+\r
+#ifndef __ASSEMBLY__ // not for assembling.\r
+\r
+//! \name Optimization Control\r
+//@{\r
+\r
+/**\r
+ * \def likely(exp)\r
+ * \brief The expression \a exp is likely to be true\r
+ */\r
+#ifndef likely\r
+# define likely(exp) (exp)\r
+#endif\r
+\r
+/**\r
+ * \def unlikely(exp)\r
+ * \brief The expression \a exp is unlikely to be true\r
+ */\r
+#ifndef unlikely\r
+# define unlikely(exp) (exp)\r
+#endif\r
+\r
+/**\r
+ * \def is_constant(exp)\r
+ * \brief Determine if an expression evaluates to a constant value.\r
+ *\r
+ * \param exp Any expression\r
+ *\r
+ * \return true if \a exp is constant, false otherwise.\r
+ */\r
+#if (defined __GNUC__) || (defined __CC_ARM)\r
+# define is_constant(exp) __builtin_constant_p(exp)\r
+#else\r
+# define is_constant(exp) (0)\r
+#endif\r
+\r
+//! @}\r
+\r
+/*! \name Bit-Field Handling\r
+ */\r
+//! @{\r
+\r
+/*! \brief Reads the bits of a value specified by a given bit-mask.\r
+ *\r
+ * \param value Value to read bits from.\r
+ * \param mask Bit-mask indicating bits to read.\r
+ *\r
+ * \return Read bits.\r
+ */\r
+#define Rd_bits( value, mask) ((value) & (mask))\r
+\r
+/*! \brief Writes the bits of a C lvalue specified by a given bit-mask.\r
+ *\r
+ * \param lvalue C lvalue to write bits to.\r
+ * \param mask Bit-mask indicating bits to write.\r
+ * \param bits Bits to write.\r
+ *\r
+ * \return Resulting value with written bits.\r
+ */\r
+#define Wr_bits(lvalue, mask, bits) ((lvalue) = ((lvalue) & ~(mask)) |\\r
+ ((bits ) & (mask)))\r
+\r
+/*! \brief Tests the bits of a value specified by a given bit-mask.\r
+ *\r
+ * \param value Value of which to test bits.\r
+ * \param mask Bit-mask indicating bits to test.\r
+ *\r
+ * \return \c 1 if at least one of the tested bits is set, else \c 0.\r
+ */\r
+#define Tst_bits( value, mask) (Rd_bits(value, mask) != 0)\r
+\r
+/*! \brief Clears the bits of a C lvalue specified by a given bit-mask.\r
+ *\r
+ * \param lvalue C lvalue of which to clear bits.\r
+ * \param mask Bit-mask indicating bits to clear.\r
+ *\r
+ * \return Resulting value with cleared bits.\r
+ */\r
+#define Clr_bits(lvalue, mask) ((lvalue) &= ~(mask))\r
+\r
+/*! \brief Sets the bits of a C lvalue specified by a given bit-mask.\r
+ *\r
+ * \param lvalue C lvalue of which to set bits.\r
+ * \param mask Bit-mask indicating bits to set.\r
+ *\r
+ * \return Resulting value with set bits.\r
+ */\r
+#define Set_bits(lvalue, mask) ((lvalue) |= (mask))\r
+\r
+/*! \brief Toggles the bits of a C lvalue specified by a given bit-mask.\r
+ *\r
+ * \param lvalue C lvalue of which to toggle bits.\r
+ * \param mask Bit-mask indicating bits to toggle.\r
+ *\r
+ * \return Resulting value with toggled bits.\r
+ */\r
+#define Tgl_bits(lvalue, mask) ((lvalue) ^= (mask))\r
+\r
+/*! \brief Reads the bit-field of a value specified by a given bit-mask.\r
+ *\r
+ * \param value Value to read a bit-field from.\r
+ * \param mask Bit-mask indicating the bit-field to read.\r
+ *\r
+ * \return Read bit-field.\r
+ */\r
+#define Rd_bitfield( value, mask) (Rd_bits( value, mask) >> ctz(mask))\r
+\r
+/*! \brief Writes the bit-field of a C lvalue specified by a given bit-mask.\r
+ *\r
+ * \param lvalue C lvalue to write a bit-field to.\r
+ * \param mask Bit-mask indicating the bit-field to write.\r
+ * \param bitfield Bit-field to write.\r
+ *\r
+ * \return Resulting value with written bit-field.\r
+ */\r
+#define Wr_bitfield(lvalue, mask, bitfield) (Wr_bits(lvalue, mask, (U32)(bitfield) << ctz(mask)))\r
+\r
+//! @}\r
+\r
+\r
+/*! \name Zero-Bit Counting\r
+ *\r
+ * Under GCC, __builtin_clz and __builtin_ctz behave like macros when\r
+ * applied to constant expressions (values known at compile time), so they are\r
+ * more optimized than the use of the corresponding assembly instructions and\r
+ * they can be used as constant expressions e.g. to initialize objects having\r
+ * static storage duration, and like the corresponding assembly instructions\r
+ * when applied to non-constant expressions (values unknown at compile time), so\r
+ * they are more optimized than an assembly periphrasis. Hence, clz and ctz\r
+ * ensure a possible and optimized behavior for both constant and non-constant\r
+ * expressions.\r
+ */\r
+//! @{\r
+\r
+/*! \brief Counts the leading zero bits of the given value considered as a 32-bit integer.\r
+ *\r
+ * \param u Value of which to count the leading zero bits.\r
+ *\r
+ * \return The count of leading zero bits in \a u.\r
+ */\r
+#if (defined __GNUC__) || (defined __CC_ARM)\r
+# define clz(u) __builtin_clz(u)\r
+#elif (defined __ICCARM__)\r
+# define clz(u) __CLZ(u)\r
+#else\r
+# define clz(u) (((u) == 0) ? 32 : \\r
+ ((u) & (1ul << 31)) ? 0 : \\r
+ ((u) & (1ul << 30)) ? 1 : \\r
+ ((u) & (1ul << 29)) ? 2 : \\r
+ ((u) & (1ul << 28)) ? 3 : \\r
+ ((u) & (1ul << 27)) ? 4 : \\r
+ ((u) & (1ul << 26)) ? 5 : \\r
+ ((u) & (1ul << 25)) ? 6 : \\r
+ ((u) & (1ul << 24)) ? 7 : \\r
+ ((u) & (1ul << 23)) ? 8 : \\r
+ ((u) & (1ul << 22)) ? 9 : \\r
+ ((u) & (1ul << 21)) ? 10 : \\r
+ ((u) & (1ul << 20)) ? 11 : \\r
+ ((u) & (1ul << 19)) ? 12 : \\r
+ ((u) & (1ul << 18)) ? 13 : \\r
+ ((u) & (1ul << 17)) ? 14 : \\r
+ ((u) & (1ul << 16)) ? 15 : \\r
+ ((u) & (1ul << 15)) ? 16 : \\r
+ ((u) & (1ul << 14)) ? 17 : \\r
+ ((u) & (1ul << 13)) ? 18 : \\r
+ ((u) & (1ul << 12)) ? 19 : \\r
+ ((u) & (1ul << 11)) ? 20 : \\r
+ ((u) & (1ul << 10)) ? 21 : \\r
+ ((u) & (1ul << 9)) ? 22 : \\r
+ ((u) & (1ul << 8)) ? 23 : \\r
+ ((u) & (1ul << 7)) ? 24 : \\r
+ ((u) & (1ul << 6)) ? 25 : \\r
+ ((u) & (1ul << 5)) ? 26 : \\r
+ ((u) & (1ul << 4)) ? 27 : \\r
+ ((u) & (1ul << 3)) ? 28 : \\r
+ ((u) & (1ul << 2)) ? 29 : \\r
+ ((u) & (1ul << 1)) ? 30 : \\r
+ 31)\r
+#endif\r
+\r
+/*! \brief Counts the trailing zero bits of the given value considered as a 32-bit integer.\r
+ *\r
+ * \param u Value of which to count the trailing zero bits.\r
+ *\r
+ * \return The count of trailing zero bits in \a u.\r
+ */\r
+#if (defined __GNUC__) || (defined __CC_ARM)\r
+# define ctz(u) __builtin_ctz(u)\r
+#else\r
+# define ctz(u) ((u) & (1ul << 0) ? 0 : \\r
+ (u) & (1ul << 1) ? 1 : \\r
+ (u) & (1ul << 2) ? 2 : \\r
+ (u) & (1ul << 3) ? 3 : \\r
+ (u) & (1ul << 4) ? 4 : \\r
+ (u) & (1ul << 5) ? 5 : \\r
+ (u) & (1ul << 6) ? 6 : \\r
+ (u) & (1ul << 7) ? 7 : \\r
+ (u) & (1ul << 8) ? 8 : \\r
+ (u) & (1ul << 9) ? 9 : \\r
+ (u) & (1ul << 10) ? 10 : \\r
+ (u) & (1ul << 11) ? 11 : \\r
+ (u) & (1ul << 12) ? 12 : \\r
+ (u) & (1ul << 13) ? 13 : \\r
+ (u) & (1ul << 14) ? 14 : \\r
+ (u) & (1ul << 15) ? 15 : \\r
+ (u) & (1ul << 16) ? 16 : \\r
+ (u) & (1ul << 17) ? 17 : \\r
+ (u) & (1ul << 18) ? 18 : \\r
+ (u) & (1ul << 19) ? 19 : \\r
+ (u) & (1ul << 20) ? 20 : \\r
+ (u) & (1ul << 21) ? 21 : \\r
+ (u) & (1ul << 22) ? 22 : \\r
+ (u) & (1ul << 23) ? 23 : \\r
+ (u) & (1ul << 24) ? 24 : \\r
+ (u) & (1ul << 25) ? 25 : \\r
+ (u) & (1ul << 26) ? 26 : \\r
+ (u) & (1ul << 27) ? 27 : \\r
+ (u) & (1ul << 28) ? 28 : \\r
+ (u) & (1ul << 29) ? 29 : \\r
+ (u) & (1ul << 30) ? 30 : \\r
+ (u) & (1ul << 31) ? 31 : \\r
+ 32)\r
+#endif\r
+\r
+//! @}\r
+\r
+\r
+/*! \name Bit Reversing\r
+ */\r
+//! @{\r
+\r
+/*! \brief Reverses the bits of \a u8.\r
+ *\r
+ * \param u8 U8 of which to reverse the bits.\r
+ *\r
+ * \return Value resulting from \a u8 with reversed bits.\r
+ */\r
+#define bit_reverse8(u8) ((U8)(bit_reverse32((U8)(u8)) >> 24))\r
+\r
+/*! \brief Reverses the bits of \a u16.\r
+ *\r
+ * \param u16 U16 of which to reverse the bits.\r
+ *\r
+ * \return Value resulting from \a u16 with reversed bits.\r
+ */\r
+#define bit_reverse16(u16) ((U16)(bit_reverse32((U16)(u16)) >> 16))\r
+\r
+/*! \brief Reverses the bits of \a u32.\r
+ *\r
+ * \param u32 U32 of which to reverse the bits.\r
+ *\r
+ * \return Value resulting from \a u32 with reversed bits.\r
+ */\r
+#define bit_reverse32(u32) __RBIT(u32)\r
+\r
+/*! \brief Reverses the bits of \a u64.\r
+ *\r
+ * \param u64 U64 of which to reverse the bits.\r
+ *\r
+ * \return Value resulting from \a u64 with reversed bits.\r
+ */\r
+#define bit_reverse64(u64) ((U64)(((U64)bit_reverse32((U64)(u64) >> 32)) |\\r
+ ((U64)bit_reverse32((U64)(u64)) << 32)))\r
+\r
+//! @}\r
+\r
+\r
+/*! \name Alignment\r
+ */\r
+//! @{\r
+\r
+/*! \brief Tests alignment of the number \a val with the \a n boundary.\r
+ *\r
+ * \param val Input value.\r
+ * \param n Boundary.\r
+ *\r
+ * \return \c 1 if the number \a val is aligned with the \a n boundary, else \c 0.\r
+ */\r
+#define Test_align(val, n ) (!Tst_bits( val, (n) - 1 ) )\r
+\r
+/*! \brief Gets alignment of the number \a val with respect to the \a n boundary.\r
+ *\r
+ * \param val Input value.\r
+ * \param n Boundary.\r
+ *\r
+ * \return Alignment of the number \a val with respect to the \a n boundary.\r
+ */\r
+#define Get_align( val, n ) ( Rd_bits( val, (n) - 1 ) )\r
+\r
+/*! \brief Sets alignment of the lvalue number \a lval to \a alg with respect to the \a n boundary.\r
+ *\r
+ * \param lval Input/output lvalue.\r
+ * \param n Boundary.\r
+ * \param alg Alignment.\r
+ *\r
+ * \return New value of \a lval resulting from its alignment set to \a alg with respect to the \a n boundary.\r
+ */\r
+#define Set_align(lval, n, alg) ( Wr_bits(lval, (n) - 1, alg) )\r
+\r
+/*! \brief Aligns the number \a val with the upper \a n boundary.\r
+ *\r
+ * \param val Input value.\r
+ * \param n Boundary.\r
+ *\r
+ * \return Value resulting from the number \a val aligned with the upper \a n boundary.\r
+ */\r
+#define Align_up( val, n ) (((val) + ((n) - 1)) & ~((n) - 1))\r
+\r
+/*! \brief Aligns the number \a val with the lower \a n boundary.\r
+ *\r
+ * \param val Input value.\r
+ * \param n Boundary.\r
+ *\r
+ * \return Value resulting from the number \a val aligned with the lower \a n boundary.\r
+ */\r
+#define Align_down(val, n ) ( (val) & ~((n) - 1))\r
+\r
+//! @}\r
+\r
+\r
+/*! \name Mathematics\r
+ *\r
+ * The same considerations as for clz and ctz apply here but GCC does not\r
+ * provide built-in functions to access the assembly instructions abs, min and\r
+ * max and it does not produce them by itself in most cases, so two sets of\r
+ * macros are defined here:\r
+ * - Abs, Min and Max to apply to constant expressions (values known at\r
+ * compile time);\r
+ * - abs, min and max to apply to non-constant expressions (values unknown at\r
+ * compile time), abs is found in stdlib.h.\r
+ */\r
+//! @{\r
+\r
+/*! \brief Takes the absolute value of \a a.\r
+ *\r
+ * \param a Input value.\r
+ *\r
+ * \return Absolute value of \a a.\r
+ *\r
+ * \note More optimized if only used with values known at compile time.\r
+ */\r
+#define Abs(a) (((a) < 0 ) ? -(a) : (a))\r
+\r
+/*! \brief Takes the minimal value of \a a and \a b.\r
+ *\r
+ * \param a Input value.\r
+ * \param b Input value.\r
+ *\r
+ * \return Minimal value of \a a and \a b.\r
+ *\r
+ * \note More optimized if only used with values known at compile time.\r
+ */\r
+#define Min(a, b) (((a) < (b)) ? (a) : (b))\r
+\r
+/*! \brief Takes the maximal value of \a a and \a b.\r
+ *\r
+ * \param a Input value.\r
+ * \param b Input value.\r
+ *\r
+ * \return Maximal value of \a a and \a b.\r
+ *\r
+ * \note More optimized if only used with values known at compile time.\r
+ */\r
+#define Max(a, b) (((a) > (b)) ? (a) : (b))\r
+\r
+// abs() is already defined by stdlib.h\r
+\r
+/*! \brief Takes the minimal value of \a a and \a b.\r
+ *\r
+ * \param a Input value.\r
+ * \param b Input value.\r
+ *\r
+ * \return Minimal value of \a a and \a b.\r
+ *\r
+ * \note More optimized if only used with values unknown at compile time.\r
+ */\r
+#define min(a, b) Min(a, b)\r
+\r
+/*! \brief Takes the maximal value of \a a and \a b.\r
+ *\r
+ * \param a Input value.\r
+ * \param b Input value.\r
+ *\r
+ * \return Maximal value of \a a and \a b.\r
+ *\r
+ * \note More optimized if only used with values unknown at compile time.\r
+ */\r
+#define max(a, b) Max(a, b)\r
+\r
+//! @}\r
+\r
+\r
+/*! \brief Calls the routine at address \a addr.\r
+ *\r
+ * It generates a long call opcode.\r
+ *\r
+ * For example, `Long_call(0x80000000)' generates a software reset on a UC3 if\r
+ * it is invoked from the CPU supervisor mode.\r
+ *\r
+ * \param addr Address of the routine to call.\r
+ *\r
+ * \note It may be used as a long jump opcode in some special cases.\r
+ */\r
+#define Long_call(addr) ((*(void (*)(void))(addr))())\r
+\r
+\r
+/*! \name MCU Endianism Handling\r
+ * ARM is MCU little endianism.\r
+ */\r
+//! @{\r
+#define MSB(u16) (((U8 *)&(u16))[1]) //!< Most significant byte of \a u16.\r
+#define LSB(u16) (((U8 *)&(u16))[0]) //!< Least significant byte of \a u16.\r
+\r
+#define MSH(u32) (((U16 *)&(u32))[1]) //!< Most significant half-word of \a u32.\r
+#define LSH(u32) (((U16 *)&(u32))[0]) //!< Least significant half-word of \a u32.\r
+#define MSB0W(u32) (((U8 *)&(u32))[3]) //!< Most significant byte of 1st rank of \a u32.\r
+#define MSB1W(u32) (((U8 *)&(u32))[2]) //!< Most significant byte of 2nd rank of \a u32.\r
+#define MSB2W(u32) (((U8 *)&(u32))[1]) //!< Most significant byte of 3rd rank of \a u32.\r
+#define MSB3W(u32) (((U8 *)&(u32))[0]) //!< Most significant byte of 4th rank of \a u32.\r
+#define LSB3W(u32) MSB0W(u32) //!< Least significant byte of 4th rank of \a u32.\r
+#define LSB2W(u32) MSB1W(u32) //!< Least significant byte of 3rd rank of \a u32.\r
+#define LSB1W(u32) MSB2W(u32) //!< Least significant byte of 2nd rank of \a u32.\r
+#define LSB0W(u32) MSB3W(u32) //!< Least significant byte of 1st rank of \a u32.\r
+ \r
+#define MSW(u64) (((U32 *)&(u64))[1]) //!< Most significant word of \a u64.\r
+#define LSW(u64) (((U32 *)&(u64))[0]) //!< Least significant word of \a u64.\r
+#define MSH0(u64) (((U16 *)&(u64))[3]) //!< Most significant half-word of 1st rank of \a u64.\r
+#define MSH1(u64) (((U16 *)&(u64))[2]) //!< Most significant half-word of 2nd rank of \a u64.\r
+#define MSH2(u64) (((U16 *)&(u64))[1]) //!< Most significant half-word of 3rd rank of \a u64.\r
+#define MSH3(u64) (((U16 *)&(u64))[0]) //!< Most significant half-word of 4th rank of \a u64.\r
+#define LSH3(u64) MSH0(u64) //!< Least significant half-word of 4th rank of \a u64.\r
+#define LSH2(u64) MSH1(u64) //!< Least significant half-word of 3rd rank of \a u64.\r
+#define LSH1(u64) MSH2(u64) //!< Least significant half-word of 2nd rank of \a u64.\r
+#define LSH0(u64) MSH3(u64) //!< Least significant half-word of 1st rank of \a u64.\r
+#define MSB0D(u64) (((U8 *)&(u64))[7]) //!< Most significant byte of 1st rank of \a u64.\r
+#define MSB1D(u64) (((U8 *)&(u64))[6]) //!< Most significant byte of 2nd rank of \a u64.\r
+#define MSB2D(u64) (((U8 *)&(u64))[5]) //!< Most significant byte of 3rd rank of \a u64.\r
+#define MSB3D(u64) (((U8 *)&(u64))[4]) //!< Most significant byte of 4th rank of \a u64.\r
+#define MSB4D(u64) (((U8 *)&(u64))[3]) //!< Most significant byte of 5th rank of \a u64.\r
+#define MSB5D(u64) (((U8 *)&(u64))[2]) //!< Most significant byte of 6th rank of \a u64.\r
+#define MSB6D(u64) (((U8 *)&(u64))[1]) //!< Most significant byte of 7th rank of \a u64.\r
+#define MSB7D(u64) (((U8 *)&(u64))[0]) //!< Most significant byte of 8th rank of \a u64.\r
+#define LSB7D(u64) MSB0D(u64) //!< Least significant byte of 8th rank of \a u64.\r
+#define LSB6D(u64) MSB1D(u64) //!< Least significant byte of 7th rank of \a u64.\r
+#define LSB5D(u64) MSB2D(u64) //!< Least significant byte of 6th rank of \a u64.\r
+#define LSB4D(u64) MSB3D(u64) //!< Least significant byte of 5th rank of \a u64.\r
+#define LSB3D(u64) MSB4D(u64) //!< Least significant byte of 4th rank of \a u64.\r
+#define LSB2D(u64) MSB5D(u64) //!< Least significant byte of 3rd rank of \a u64.\r
+#define LSB1D(u64) MSB6D(u64) //!< Least significant byte of 2nd rank of \a u64.\r
+#define LSB0D(u64) MSB7D(u64) //!< Least significant byte of 1st rank of \a u64.\r
+\r
+#define BE16(x) Swap16(x)\r
+#define LE16(x) (x)\r
+\r
+#define le16_to_cpu(x) (x)\r
+#define cpu_to_le16(x) (x)\r
+#define LE16_TO_CPU(x) (x)\r
+#define CPU_TO_LE16(x) (x)\r
+\r
+#define be16_to_cpu(x) Swap16(x)\r
+#define cpu_to_be16(x) Swap16(x)\r
+#define BE16_TO_CPU(x) Swap16(x)\r
+#define CPU_TO_BE16(x) Swap16(x)\r
+\r
+#define le32_to_cpu(x) (x)\r
+#define cpu_to_le32(x) (x)\r
+#define LE32_TO_CPU(x) (x)\r
+#define CPU_TO_LE32(x) (x)\r
+\r
+#define be32_to_cpu(x) swap32(x)\r
+#define cpu_to_be32(x) swap32(x)\r
+#define BE32_TO_CPU(x) swap32(x)\r
+#define CPU_TO_BE32(x) swap32(x)\r
+//! @}\r
+\r
+\r
+/*! \name Endianism Conversion\r
+ *\r
+ * The same considerations as for clz and ctz apply here but GCC's\r
+ * __builtin_bswap_32 and __builtin_bswap_64 do not behave like macros when\r
+ * applied to constant expressions, so two sets of macros are defined here:\r
+ * - Swap16, Swap32 and Swap64 to apply to constant expressions (values known\r
+ * at compile time);\r
+ * - swap16, swap32 and swap64 to apply to non-constant expressions (values\r
+ * unknown at compile time).\r
+ */\r
+//! @{\r
+\r
+/*! \brief Toggles the endianism of \a u16 (by swapping its bytes).\r
+ *\r
+ * \param u16 U16 of which to toggle the endianism.\r
+ *\r
+ * \return Value resulting from \a u16 with toggled endianism.\r
+ *\r
+ * \note More optimized if only used with values known at compile time.\r
+ */\r
+#define Swap16(u16) ((U16)(((U16)(u16) >> 8) |\\r
+ ((U16)(u16) << 8)))\r
+\r
+/*! \brief Toggles the endianism of \a u32 (by swapping its bytes).\r
+ *\r
+ * \param u32 U32 of which to toggle the endianism.\r
+ *\r
+ * \return Value resulting from \a u32 with toggled endianism.\r
+ *\r
+ * \note More optimized if only used with values known at compile time.\r
+ */\r
+#define Swap32(u32) ((U32)(((U32)Swap16((U32)(u32) >> 16)) |\\r
+ ((U32)Swap16((U32)(u32)) << 16)))\r
+\r
+/*! \brief Toggles the endianism of \a u64 (by swapping its bytes).\r
+ *\r
+ * \param u64 U64 of which to toggle the endianism.\r
+ *\r
+ * \return Value resulting from \a u64 with toggled endianism.\r
+ *\r
+ * \note More optimized if only used with values known at compile time.\r
+ */\r
+#define Swap64(u64) ((U64)(((U64)Swap32((U64)(u64) >> 32)) |\\r
+ ((U64)Swap32((U64)(u64)) << 32)))\r
+\r
+/*! \brief Toggles the endianism of \a u16 (by swapping its bytes).\r
+ *\r
+ * \param u16 U16 of which to toggle the endianism.\r
+ *\r
+ * \return Value resulting from \a u16 with toggled endianism.\r
+ *\r
+ * \note More optimized if only used with values unknown at compile time.\r
+ */\r
+#define swap16(u16) Swap16(u16)\r
+\r
+/*! \brief Toggles the endianism of \a u32 (by swapping its bytes).\r
+ *\r
+ * \param u32 U32 of which to toggle the endianism.\r
+ *\r
+ * \return Value resulting from \a u32 with toggled endianism.\r
+ *\r
+ * \note More optimized if only used with values unknown at compile time.\r
+ */\r
+#if (defined __GNUC__)\r
+# define swap32(u32) ((U32)__builtin_bswap32((U32)(u32)))\r
+#else\r
+# define swap32(u32) Swap32(u32)\r
+#endif\r
+\r
+/*! \brief Toggles the endianism of \a u64 (by swapping its bytes).\r
+ *\r
+ * \param u64 U64 of which to toggle the endianism.\r
+ *\r
+ * \return Value resulting from \a u64 with toggled endianism.\r
+ *\r
+ * \note More optimized if only used with values unknown at compile time.\r
+ */\r
+#if (defined __GNUC__)\r
+# define swap64(u64) ((U64)__builtin_bswap64((U64)(u64)))\r
+#else\r
+# define swap64(u64) ((U64)(((U64)swap32((U64)(u64) >> 32)) |\\r
+ ((U64)swap32((U64)(u64)) << 32)))\r
+#endif\r
+\r
+//! @}\r
+\r
+\r
+/*! \name Target Abstraction\r
+ */\r
+//! @{\r
+\r
+#define _GLOBEXT_ extern //!< extern storage-class specifier.\r
+#define _CONST_TYPE_ const //!< const type qualifier.\r
+#define _MEM_TYPE_SLOW_ //!< Slow memory type.\r
+#define _MEM_TYPE_MEDFAST_ //!< Fairly fast memory type.\r
+#define _MEM_TYPE_FAST_ //!< Fast memory type.\r
+\r
+typedef U8 Byte; //!< 8-bit unsigned integer.\r
+\r
+#define memcmp_ram2ram memcmp //!< Target-specific memcmp of RAM to RAM.\r
+#define memcmp_code2ram memcmp //!< Target-specific memcmp of RAM to NVRAM.\r
+#define memcpy_ram2ram memcpy //!< Target-specific memcpy from RAM to RAM.\r
+#define memcpy_code2ram memcpy //!< Target-specific memcpy from NVRAM to RAM.\r
+\r
+#define LSB0(u32) LSB0W(u32) //!< Least significant byte of 1st rank of \a u32.\r
+#define LSB1(u32) LSB1W(u32) //!< Least significant byte of 2nd rank of \a u32.\r
+#define LSB2(u32) LSB2W(u32) //!< Least significant byte of 3rd rank of \a u32.\r
+#define LSB3(u32) LSB3W(u32) //!< Least significant byte of 4th rank of \a u32.\r
+#define MSB3(u32) MSB3W(u32) //!< Most significant byte of 4th rank of \a u32.\r
+#define MSB2(u32) MSB2W(u32) //!< Most significant byte of 3rd rank of \a u32.\r
+#define MSB1(u32) MSB1W(u32) //!< Most significant byte of 2nd rank of \a u32.\r
+#define MSB0(u32) MSB0W(u32) //!< Most significant byte of 1st rank of \a u32.\r
+\r
+//! @}\r
+\r
+/**\r
+ * \brief Calculate \f$ \left\lceil \frac{a}{b} \right\rceil \f$ using\r
+ * integer arithmetic.\r
+ *\r
+ * \param a An integer\r
+ * \param b Another integer\r
+ *\r
+ * \return (\a a / \a b) rounded up to the nearest integer.\r
+ */\r
+#define div_ceil(a, b) (((a) + (b) - 1) / (b))\r
+\r
+#endif // #ifndef __ASSEMBLY__\r
+\r
+\r
+#if defined(__ICCARM__)\r
+#define SHORTENUM __packed\r
+#elif defined(__GNUC__)\r
+#define SHORTENUM __attribute__((packed))\r
+#endif\r
+\r
+/* No operation */\r
+#if defined(__ICCARM__)\r
+#define nop() __no_operation()\r
+#elif defined(__GNUC__)\r
+#define nop() (__NOP())\r
+#endif\r
+\r
+#define FLASH_DECLARE(x) const x\r
+#define FLASH_EXTERN(x) extern const x\r
+#define PGM_READ_BYTE(x) *(x)\r
+#define PGM_READ_WORD(x) *(x)\r
+#define MEMCPY_ENDIAN memcpy\r
+#define PGM_READ_BLOCK(dst, src, len) memcpy((dst), (src), (len))\r
+\r
+/*Defines the Flash Storage for the request and response of MAC*/\r
+#define CMD_ID_OCTET (0)\r
+\r
+/* Converting of values from CPU endian to little endian. */\r
+#define CPU_ENDIAN_TO_LE16(x) (x)\r
+#define CPU_ENDIAN_TO_LE32(x) (x)\r
+#define CPU_ENDIAN_TO_LE64(x) (x)\r
+\r
+/* Converting of values from little endian to CPU endian. */\r
+#define LE16_TO_CPU_ENDIAN(x) (x)\r
+#define LE32_TO_CPU_ENDIAN(x) (x)\r
+#define LE64_TO_CPU_ENDIAN(x) (x)\r
+\r
+/* Converting of constants from little endian to CPU endian. */\r
+#define CLE16_TO_CPU_ENDIAN(x) (x)\r
+#define CLE32_TO_CPU_ENDIAN(x) (x)\r
+#define CLE64_TO_CPU_ENDIAN(x) (x)\r
+\r
+/* Converting of constants from CPU endian to little endian. */\r
+#define CCPU_ENDIAN_TO_LE16(x) (x)\r
+#define CCPU_ENDIAN_TO_LE32(x) (x)\r
+#define CCPU_ENDIAN_TO_LE64(x) (x)\r
+\r
+#define ADDR_COPY_DST_SRC_16(dst, src) ((dst) = (src))\r
+#define ADDR_COPY_DST_SRC_64(dst, src) ((dst) = (src))\r
+\r
+/**\r
+ * @brief Converts a 64-Bit value into a 8 Byte array\r
+ *\r
+ * @param[in] value 64-Bit value\r
+ * @param[out] data Pointer to the 8 Byte array to be updated with 64-Bit value\r
+ * @ingroup apiPalApi\r
+ */\r
+static inline void convert_64_bit_to_byte_array(uint64_t value, uint8_t *data)\r
+{\r
+ uint8_t val_index = 0;\r
+\r
+ while (val_index < 8)\r
+ {\r
+ data[val_index++] = value & 0xFF;\r
+ value = value >> 8;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Converts a 16-Bit value into a 2 Byte array\r
+ *\r
+ * @param[in] value 16-Bit value\r
+ * @param[out] data Pointer to the 2 Byte array to be updated with 16-Bit value\r
+ * @ingroup apiPalApi\r
+ */\r
+static inline void convert_16_bit_to_byte_array(uint16_t value, uint8_t *data)\r
+{\r
+ data[0] = value & 0xFF;\r
+ data[1] = (value >> 8) & 0xFF;\r
+}\r
+\r
+/* Converts a 16-Bit value into a 2 Byte array */\r
+static inline void convert_spec_16_bit_to_byte_array(uint16_t value, uint8_t *data)\r
+{\r
+ data[0] = value & 0xFF;\r
+ data[1] = (value >> 8) & 0xFF;\r
+}\r
+\r
+/* Converts a 16-Bit value into a 2 Byte array */\r
+static inline void convert_16_bit_to_byte_address(uint16_t value, uint8_t *data)\r
+{\r
+ data[0] = value & 0xFF;\r
+ data[1] = (value >> 8) & 0xFF;\r
+}\r
+\r
+/*\r
+ * @brief Converts a 2 Byte array into a 16-Bit value\r
+ *\r
+ * @param data Specifies the pointer to the 2 Byte array\r
+ *\r
+ * @return 16-Bit value\r
+ * @ingroup apiPalApi\r
+ */\r
+static inline uint16_t convert_byte_array_to_16_bit(uint8_t *data)\r
+{\r
+ return (data[0] | ((uint16_t)data[1] << 8));\r
+}\r
+\r
+/**\r
+ * @brief Converts a 8 Byte array into a 64-Bit value\r
+ *\r
+ * @param data Specifies the pointer to the 8 Byte array\r
+ *\r
+ * @return 64-Bit value\r
+ * @ingroup apiPalApi\r
+ */\r
+static inline uint64_t convert_byte_array_to_64_bit(uint8_t *data)\r
+{\r
+ union\r
+ {\r
+ uint64_t u64;\r
+ uint8_t u8[8];\r
+ } long_addr;\r
+\r
+ uint8_t val_index;\r
+\r
+ for (val_index = 0; val_index < 8; val_index++)\r
+ {\r
+ long_addr.u8[val_index] = *data++;\r
+ }\r
+\r
+ return long_addr.u64;\r
+}\r
+/**\r
+ * \}\r
+ */\r
+\r
+#endif /* UTILS_COMPILER_H */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief FPU support for SAM.\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _FPU_H_INCLUDED_\r
+#define _FPU_H_INCLUDED_\r
+\r
+#include <compiler.h>\r
+\r
+/** Address for ARM CPACR */\r
+#define ADDR_CPACR 0xE000ED88\r
+\r
+/** CPACR Register */\r
+#define REG_CPACR (*((volatile uint32_t *)ADDR_CPACR))\r
+\r
+/**\r
+ * Enable FPU\r
+ */\r
+__always_inline static void fpu_enable(void)\r
+{\r
+ irqflags_t flags;\r
+ flags = cpu_irq_save();\r
+ REG_CPACR |= (0xFu << 20);\r
+ __DSB();\r
+ __ISB();\r
+ cpu_irq_restore(flags);\r
+}\r
+\r
+/**\r
+ * Disable FPU\r
+ */\r
+__always_inline static void fpu_disable(void)\r
+{\r
+ irqflags_t flags;\r
+ flags = cpu_irq_save();\r
+ REG_CPACR &= ~(0xFu << 20);\r
+ __DSB();\r
+ __ISB();\r
+ cpu_irq_restore(flags);\r
+}\r
+\r
+/**\r
+ * Check if FPU is enabled\r
+ */\r
+__always_inline static bool fpu_is_enabled(void)\r
+{\r
+ return (REG_CPACR & (0xFu << 20));\r
+}\r
+\r
+#endif /* _FPU_H_INCLUDED_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Arch file for SAM.\r
+ *\r
+ * This file defines common SAM series.\r
+ *\r
+ * Copyright (c) 2011 - 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM_IO_\r
+#define _SAM_IO_\r
+\r
+/* SAM3 family */\r
+\r
+/* SAM3S series */\r
+#if (SAM3S)\r
+# if (SAM3S8 || SAM3SD8)\r
+# include "sam3s8.h"\r
+# else\r
+# include "sam3s.h"\r
+# endif\r
+#endif\r
+\r
+/* SAM3U series */\r
+#if (SAM3U)\r
+# include "sam3u.h"\r
+#endif\r
+\r
+/* SAM3N series */\r
+#if (SAM3N)\r
+# include "sam3n.h"\r
+#endif\r
+\r
+/* SAM3XA series */\r
+#if (SAM3XA)\r
+# include "sam3xa.h"\r
+#endif\r
+\r
+/* SAM4S series */\r
+#if (SAM4S)\r
+# include "sam4s.h"\r
+#endif\r
+\r
+/* SAM4L series */\r
+#if (SAM4L)\r
+# include "sam4l.h"\r
+#endif\r
+\r
+/* SAM4E series */\r
+#if (SAM4E)\r
+# include "sam4e.h"\r
+#endif\r
+\r
+/* SAM4N series */\r
+#if (SAM4N)\r
+# include "sam4n.h"\r
+#endif\r
+\r
+#endif /* _SAM_IO_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Flash Linker script for SAM.\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ * \r
+ * 1. Redistributions of source code must retain the above copyright notice, \r
+ * this list of conditions and the following disclaimer.\r
+ * \r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * \r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ * \r
+ * 4. This software may only be redistributed and used in connection with an \r
+ * Atmel microcontroller product.\r
+ * \r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")\r
+OUTPUT_ARCH(arm)\r
+SEARCH_DIR(.)\r
+\r
+/* Memory Spaces Definitions */\r
+MEMORY\r
+{\r
+ rom (rx) : ORIGIN = 0x00400000, LENGTH = 0x00100000\r
+ ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00020000\r
+}\r
+\r
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */\r
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x3000;\r
+\r
+SECTIONS\r
+{\r
+ .text :\r
+ {\r
+ . = ALIGN(4);\r
+ _sfixed = .;\r
+ KEEP(*(.vectors .vectors.*))\r
+ *(.text .text.* .gnu.linkonce.t.*)\r
+ *(.glue_7t) *(.glue_7)\r
+ *(.rodata .rodata* .gnu.linkonce.r.*)\r
+ *(.ARM.extab* .gnu.linkonce.armextab.*)\r
+\r
+ /* Support C constructors, and C destructors in both user code\r
+ and the C library. This also provides support for C++ code. */\r
+ . = ALIGN(4);\r
+ KEEP(*(.init))\r
+ . = ALIGN(4);\r
+ __preinit_array_start = .;\r
+ KEEP (*(.preinit_array))\r
+ __preinit_array_end = .;\r
+\r
+ . = ALIGN(4);\r
+ __init_array_start = .;\r
+ KEEP (*(SORT(.init_array.*)))\r
+ KEEP (*(.init_array))\r
+ __init_array_end = .;\r
+\r
+ . = ALIGN(0x4);\r
+ KEEP (*crtbegin.o(.ctors))\r
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\r
+ KEEP (*(SORT(.ctors.*)))\r
+ KEEP (*crtend.o(.ctors))\r
+\r
+ . = ALIGN(4);\r
+ KEEP(*(.fini))\r
+\r
+ . = ALIGN(4);\r
+ __fini_array_start = .;\r
+ KEEP (*(.fini_array))\r
+ KEEP (*(SORT(.fini_array.*)))\r
+ __fini_array_end = .;\r
+\r
+ KEEP (*crtbegin.o(.dtors))\r
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\r
+ KEEP (*(SORT(.dtors.*)))\r
+ KEEP (*crtend.o(.dtors))\r
+\r
+ . = ALIGN(4);\r
+ _efixed = .; /* End of text section */\r
+ } > rom\r
+\r
+ /* .ARM.exidx is sorted, so has to go in its own output section. */\r
+ PROVIDE_HIDDEN (__exidx_start = .);\r
+ .ARM.exidx :\r
+ {\r
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)\r
+ } > rom\r
+ PROVIDE_HIDDEN (__exidx_end = .);\r
+\r
+ . = ALIGN(4);\r
+ _etext = .;\r
+\r
+ .relocate : AT (_etext)\r
+ {\r
+ . = ALIGN(4);\r
+ _srelocate = .;\r
+ *(.ramfunc .ramfunc.*);\r
+ *(.data .data.*);\r
+ . = ALIGN(4);\r
+ _erelocate = .;\r
+ } > ram\r
+\r
+ /* .bss section which is used for uninitialized data */\r
+ .bss (NOLOAD) :\r
+ {\r
+ . = ALIGN(4);\r
+ _sbss = . ;\r
+ _szero = .;\r
+ *(.bss .bss.*)\r
+ *(COMMON)\r
+ . = ALIGN(4);\r
+ _ebss = . ;\r
+ _ezero = .;\r
+ } > ram\r
+\r
+ /* stack section */\r
+ .stack (NOLOAD):\r
+ {\r
+ . = ALIGN(8);\r
+ _sstack = .;\r
+ . = . + STACK_SIZE;\r
+ . = ALIGN(8);\r
+ _estack = .;\r
+ } > ram\r
+\r
+ . = ALIGN(4);\r
+ _end = . ;\r
+}\r
--- /dev/null
+# List of available make goals:\r
+#\r
+# all Default target, builds the project\r
+# clean Clean up the project\r
+# rebuild Rebuild the project\r
+# debug_flash Builds the project and debug in flash\r
+# debug_sram Builds the project and debug in sram\r
+#\r
+# doc Build the documentation\r
+# cleandoc Clean up the documentation\r
+# rebuilddoc Rebuild the documentation\r
+#\r
+# \file\r
+#\r
+# Copyright (c) 2011 - 2013 Atmel Corporation. All rights reserved.\r
+#\r
+# \asf_license_start\r
+#\r
+# \page License\r
+#\r
+# Redistribution and use in source and binary forms, with or without\r
+# modification, are permitted provided that the following conditions are met:\r
+#\r
+# 1. Redistributions of source code must retain the above copyright notice,\r
+# this list of conditions and the following disclaimer.\r
+#\r
+# 2. Redistributions in binary form must reproduce the above copyright notice,\r
+# this list of conditions and the following disclaimer in the documentation\r
+# and/or other materials provided with the distribution.\r
+#\r
+# 3. The name of Atmel may not be used to endorse or promote products derived\r
+# from this software without specific prior written permission.\r
+#\r
+# 4. This software may only be redistributed and used in connection with an\r
+# Atmel microcontroller product.\r
+#\r
+# THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+# WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+# EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+# ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+# OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+# HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+# STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+# POSSIBILITY OF SUCH DAMAGE.\r
+#\r
+# \asf_license_stop\r
+#\r
+\r
+# Include the config.mk file from the current working path, e.g., where the\r
+# user called make.\r
+include config.mk\r
+\r
+# Tool to use to generate documentation from the source code\r
+DOCGEN ?= doxygen\r
+\r
+# Look for source files relative to the top-level source directory\r
+VPATH := $(PRJ_PATH)\r
+\r
+# Output target file\r
+project_type := $(PROJECT_TYPE)\r
+\r
+# Output target file\r
+ifeq ($(project_type),flash)\r
+target := $(TARGET_FLASH)\r
+linker_script := $(PRJ_PATH)/$(LINKER_SCRIPT_FLASH)\r
+debug_script := $(PRJ_PATH)/$(DEBUG_SCRIPT_FLASH)\r
+else\r
+target := $(TARGET_SRAM)\r
+linker_script := $(PRJ_PATH)/$(LINKER_SCRIPT_SRAM)\r
+debug_script := $(PRJ_PATH)/$(DEBUG_SCRIPT_SRAM)\r
+endif\r
+\r
+# Output project name (target name minus suffix)\r
+project := $(basename $(target))\r
+\r
+# Output target file (typically ELF or static library)\r
+ifeq ($(suffix $(target)),.a)\r
+target_type := lib\r
+else\r
+ifeq ($(suffix $(target)),.elf)\r
+target_type := elf\r
+else\r
+$(error "Target type $(target_type) is not supported")\r
+endif\r
+endif\r
+\r
+# Allow override of operating system detection. The user can add OS=Linux or\r
+# OS=Windows on the command line to explicit set the host OS.\r
+#\r
+# This allows to work around broken uname utility on certain systems.\r
+ifdef OS\r
+ ifeq ($(strip $(OS)), Linux)\r
+ os_type := Linux\r
+ endif\r
+ ifeq ($(strip $(OS)), Windows)\r
+ os_type := windows32_64\r
+ endif\r
+endif\r
+\r
+os_type ?= $(strip $(shell uname))\r
+\r
+ifeq ($(os_type),windows32)\r
+os := Windows\r
+else\r
+ifeq ($(os_type),windows64)\r
+os := Windows\r
+else\r
+ifeq ($(os_type),windows32_64)\r
+os ?= Windows\r
+else\r
+ifeq ($(os_type),)\r
+os := Windows\r
+else\r
+# Default to Linux style operating system. Both Cygwin and mingw are fully\r
+# compatible (for this Makefile) with Linux.\r
+os := Linux\r
+endif\r
+endif\r
+endif\r
+endif\r
+\r
+# Output documentation directory and configuration file.\r
+docdir := ../doxygen/html\r
+doccfg := ../doxygen/doxyfile.doxygen\r
+\r
+CROSS ?= arm-none-eabi-\r
+AR := $(CROSS)ar\r
+AS := $(CROSS)as\r
+CC := $(CROSS)gcc\r
+CPP := $(CROSS)gcc -E\r
+CXX := $(CROSS)g++\r
+LD := $(CROSS)g++\r
+NM := $(CROSS)nm\r
+OBJCOPY := $(CROSS)objcopy\r
+OBJDUMP := $(CROSS)objdump\r
+SIZE := $(CROSS)size\r
+GDB := $(CROSS)gdb\r
+\r
+RM := rm\r
+ifeq ($(os),Windows)\r
+RMDIR := rmdir /S /Q\r
+else\r
+RMDIR := rmdir -p --ignore-fail-on-non-empty\r
+endif\r
+\r
+# On Windows, we need to override the shell to force the use of cmd.exe\r
+ifeq ($(os),Windows)\r
+SHELL := cmd\r
+endif\r
+\r
+# Strings for beautifying output\r
+MSG_CLEAN_FILES = "RM *.o *.d"\r
+MSG_CLEAN_DIRS = "RMDIR $(strip $(clean-dirs))"\r
+MSG_CLEAN_DOC = "RMDIR $(docdir)"\r
+MSG_MKDIR = "MKDIR $(dir $@)"\r
+\r
+MSG_INFO = "INFO "\r
+\r
+MSG_ARCHIVING = "AR $@"\r
+MSG_ASSEMBLING = "AS $@"\r
+MSG_BINARY_IMAGE = "OBJCOPY $@"\r
+MSG_COMPILING = "CC $@"\r
+MSG_COMPILING_CXX = "CXX $@"\r
+MSG_EXTENDED_LISTING = "OBJDUMP $@"\r
+MSG_IHEX_IMAGE = "OBJCOPY $@"\r
+MSG_LINKING = "LN $@"\r
+MSG_PREPROCESSING = "CPP $@"\r
+MSG_SIZE = "SIZE $@"\r
+MSG_SYMBOL_TABLE = "NM $@"\r
+\r
+MSG_GENERATING_DOC = "DOXYGEN $(docdir)"\r
+\r
+# Don't use make's built-in rules and variables\r
+MAKEFLAGS += -rR\r
+\r
+# Don't print 'Entering directory ...'\r
+MAKEFLAGS += --no-print-directory\r
+\r
+# Function for reversing the order of a list\r
+reverse = $(if $(1),$(call reverse,$(wordlist 2,$(words $(1)),$(1)))) $(firstword $(1))\r
+\r
+# Hide command output by default, but allow the user to override this\r
+# by adding V=1 on the command line.\r
+#\r
+# This is inspired by the Kbuild system used by the Linux kernel.\r
+ifdef V\r
+ ifeq ("$(origin V)", "command line")\r
+ VERBOSE = $(V)\r
+ endif\r
+endif\r
+ifndef VERBOSE\r
+ VERBOSE = 0\r
+endif\r
+\r
+ifeq ($(VERBOSE), 1)\r
+ Q =\r
+else\r
+ Q = @\r
+endif\r
+\r
+arflags-gnu-y := $(ARFLAGS)\r
+asflags-gnu-y := $(ASFLAGS)\r
+cflags-gnu-y := $(CFLAGS)\r
+cxxflags-gnu-y := $(CXXFLAGS)\r
+cppflags-gnu-y := $(CPPFLAGS)\r
+cpuflags-gnu-y :=\r
+dbgflags-gnu-y := $(DBGFLAGS)\r
+libflags-gnu-y := $(foreach LIB,$(LIBS),-l$(LIB))\r
+ldflags-gnu-y := $(LDFLAGS)\r
+flashflags-gnu-y :=\r
+clean-files :=\r
+clean-dirs :=\r
+\r
+clean-files += $(wildcard $(target) $(project).map)\r
+clean-files += $(wildcard $(project).hex $(project).bin)\r
+clean-files += $(wildcard $(project).lss $(project).sym)\r
+clean-files += $(wildcard $(build))\r
+\r
+# Use pipes instead of temporary files for communication between processes\r
+cflags-gnu-y += -pipe\r
+asflags-gnu-y += -pipe\r
+ldflags-gnu-y += -pipe\r
+\r
+# Archiver flags.\r
+arflags-gnu-y += rcs\r
+\r
+# Always enable warnings. And be very careful about implicit\r
+# declarations.\r
+cflags-gnu-y += -Wall -Wstrict-prototypes -Wmissing-prototypes\r
+cflags-gnu-y += -Werror-implicit-function-declaration\r
+cxxflags-gnu-y += -Wall\r
+# IAR doesn't allow arithmetic on void pointers, so warn about that.\r
+cflags-gnu-y += -Wpointer-arith\r
+cxxflags-gnu-y += -Wpointer-arith\r
+\r
+# Preprocessor flags.\r
+cppflags-gnu-y += $(foreach INC,$(addprefix $(PRJ_PATH)/,$(INC_PATH)),-I$(INC))\r
+asflags-gnu-y += $(foreach INC,$(addprefix $(PRJ_PATH)/,$(INC_PATH)),'-Wa,-I$(INC)')\r
+\r
+# CPU specific flags.\r
+cpuflags-gnu-y += -mcpu=$(ARCH) -mthumb -D=__$(PART)__\r
+\r
+# Dependency file flags.\r
+depflags = -MD -MP -MQ $@\r
+\r
+# Debug specific flags.\r
+ifdef BUILD_DEBUG_LEVEL\r
+dbgflags-gnu-y += -g$(BUILD_DEBUG_LEVEL)\r
+else\r
+dbgflags-gnu-y += -g3\r
+endif\r
+\r
+# Optimization specific flags.\r
+ifdef BUILD_OPTIMIZATION\r
+optflags-gnu-y = -O$(BUILD_OPTIMIZATION)\r
+else\r
+optflags-gnu-y = $(OPTIMIZATION)\r
+endif\r
+\r
+# Always preprocess assembler files.\r
+asflags-gnu-y += -x assembler-with-cpp\r
+# Compile C files using the GNU99 standard.\r
+cflags-gnu-y += -std=gnu99\r
+# Compile C++ files using the GNU++98 standard.\r
+cxxflags-gnu-y += -std=gnu++98\r
+\r
+# Don't use strict aliasing (very common in embedded applications).\r
+cflags-gnu-y += -fno-strict-aliasing\r
+cxxflags-gnu-y += -fno-strict-aliasing\r
+\r
+# Separate each function and data into its own separate section to allow\r
+# garbage collection of unused sections.\r
+cflags-gnu-y += -ffunction-sections -fdata-sections\r
+cxxflags-gnu-y += -ffunction-sections -fdata-sections\r
+\r
+# Various cflags.\r
+cflags-gnu-y += -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int\r
+cflags-gnu-y += -Wmain -Wparentheses\r
+cflags-gnu-y += -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused\r
+cflags-gnu-y += -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef\r
+cflags-gnu-y += -Wshadow -Wbad-function-cast -Wwrite-strings\r
+cflags-gnu-y += -Wsign-compare -Waggregate-return\r
+cflags-gnu-y += -Wmissing-declarations\r
+cflags-gnu-y += -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations\r
+cflags-gnu-y += -Wpacked -Wredundant-decls -Wnested-externs -Winline -Wlong-long\r
+cflags-gnu-y += -Wunreachable-code\r
+cflags-gnu-y += -Wcast-align\r
+cflags-gnu-y += --param max-inline-insns-single=500\r
+\r
+# Garbage collect unreferred sections when linking.\r
+ldflags-gnu-y += -Wl,--gc-sections\r
+\r
+# Use the linker script if provided by the project.\r
+ifneq ($(strip $(linker_script)),)\r
+ldflags-gnu-y += -Wl,-T $(linker_script)\r
+endif\r
+\r
+# Output a link map file and a cross reference table\r
+ldflags-gnu-y += -Wl,-Map=$(project).map,--cref\r
+\r
+# Add library search paths relative to the top level directory.\r
+ldflags-gnu-y += $(foreach _LIB_PATH,$(addprefix $(PRJ_PATH)/,$(LIB_PATH)),-L$(_LIB_PATH))\r
+\r
+a_flags = $(cpuflags-gnu-y) $(depflags) $(cppflags-gnu-y) $(asflags-gnu-y) -D__ASSEMBLY__\r
+c_flags = $(cpuflags-gnu-y) $(dbgflags-gnu-y) $(depflags) $(optflags-gnu-y) $(cppflags-gnu-y) $(cflags-gnu-y)\r
+cxx_flags= $(cpuflags-gnu-y) $(dbgflags-gnu-y) $(depflags) $(optflags-gnu-y) $(cppflags-gnu-y) $(cxxflags-gnu-y)\r
+l_flags = -Wl,--entry=Reset_Handler -Wl,--cref $(cpuflags-gnu-y) $(optflags-gnu-y) $(ldflags-gnu-y)\r
+ar_flags = $(arflags-gnu-y)\r
+\r
+# Source files list and part informations must already be included before\r
+# running this makefile\r
+\r
+# If a custom build directory is specified, use it -- force trailing / in directory name.\r
+ifdef BUILD_DIR\r
+ build-dir := $(dir $(BUILD_DIR))$(if $(notdir $(BUILD_DIR)),$(notdir $(BUILD_DIR))/)\r
+else\r
+ build-dir =\r
+endif\r
+\r
+# Create object files list from source files list.\r
+obj-y := $(addprefix $(build-dir), $(addsuffix .o,$(basename $(CSRCS) $(ASSRCS))))\r
+# Create dependency files list from source files list.\r
+dep-files := $(wildcard $(foreach f,$(obj-y),$(basename $(f)).d))\r
+\r
+clean-files += $(wildcard $(obj-y))\r
+clean-files += $(dep-files)\r
+\r
+clean-dirs += $(call reverse,$(sort $(wildcard $(dir $(obj-y)))))\r
+\r
+# Default target.\r
+.PHONY: all\r
+ifeq ($(project_type),all)\r
+all:\r
+ $(MAKE) all PROJECT_TYPE=flash\r
+ $(MAKE) all PROJECT_TYPE=sram\r
+else\r
+ifeq ($(target_type),lib)\r
+all: $(target) $(project).lss $(project).sym\r
+else\r
+ifeq ($(target_type),elf)\r
+all: $(target) $(project).lss $(project).sym $(project).hex $(project).bin\r
+endif\r
+endif\r
+endif\r
+\r
+# Clean up the project.\r
+.PHONY: clean\r
+clean:\r
+ @$(if $(strip $(clean-files)),echo $(MSG_CLEAN_FILES))\r
+ $(if $(strip $(clean-files)),$(Q)$(RM) $(clean-files),)\r
+ @$(if $(strip $(clean-dirs)),echo $(MSG_CLEAN_DIRS))\r
+# Remove created directories, and make sure we only remove existing\r
+# directories, since recursive rmdir might help us a bit on the way.\r
+ifeq ($(os),Windows)\r
+ $(Q)$(if $(strip $(clean-dirs)), \\r
+ $(RMDIR) $(strip $(subst /,\,$(clean-dirs))))\r
+else\r
+ $(Q)$(if $(strip $(clean-dirs)), \\r
+ for directory in $(strip $(clean-dirs)); do \\r
+ if [ -d "$$directory" ]; then \\r
+ $(RMDIR) $$directory; \\r
+ fi \\r
+ done \\r
+ )\r
+endif\r
+\r
+# Rebuild the project.\r
+.PHONY: rebuild\r
+rebuild: clean all\r
+\r
+# Debug the project in flash.\r
+.PHONY: debug_flash\r
+debug_flash: all\r
+ $(GDB) -x "$(PRJ_PATH)/$(DEBUG_SCRIPT_FLASH)" -ex "reset" -readnow -se $(TARGET_FLASH)\r
+\r
+# Debug the project in sram.\r
+.PHONY: debug_sram\r
+debug_sram: all\r
+ $(GDB) -x "$(PRJ_PATH)/$(DEBUG_SCRIPT_SRAM)" -ex "reset" -readnow -se $(TARGET_SRAM)\r
+\r
+.PHONY: objfiles\r
+objfiles: $(obj-y)\r
+\r
+# Create object files from C source files.\r
+$(build-dir)%.o: %.c $(MAKEFILE_PATH) config.mk\r
+ $(Q)test -d $(dir $@) || echo $(MSG_MKDIR)\r
+ifeq ($(os),Windows)\r
+ $(Q)test -d $(patsubst %/,%,$(dir $@)) || mkdir $(subst /,\,$(dir $@))\r
+else\r
+ $(Q)test -d $(dir $@) || mkdir -p $(dir $@)\r
+endif\r
+ @echo $(MSG_COMPILING)\r
+ $(Q)$(CC) $(c_flags) -c $< -o $@\r
+\r
+# Create object files from C++ source files.\r
+$(build-dir)%.o: %.cpp $(MAKEFILE_PATH) config.mk\r
+ $(Q)test -d $(dir $@) || echo $(MSG_MKDIR)\r
+ifeq ($(os),Windows)\r
+ $(Q)test -d $(patsubst %/,%,$(dir $@)) || mkdir $(subst /,\,$(dir $@))\r
+else\r
+ $(Q)test -d $(dir $@) || mkdir -p $(dir $@)\r
+endif\r
+ @echo $(MSG_COMPILING_CXX)\r
+ $(Q)$(CXX) $(cxx_flags) -c $< -o $@\r
+\r
+# Preprocess and assemble: create object files from assembler source files.\r
+$(build-dir)%.o: %.S $(MAKEFILE_PATH) config.mk\r
+ $(Q)test -d $(dir $@) || echo $(MSG_MKDIR)\r
+ifeq ($(os),Windows)\r
+ $(Q)test -d $(patsubst %/,%,$(dir $@)) || mkdir $(subst /,\,$(dir $@))\r
+else\r
+ $(Q)test -d $(dir $@) || mkdir -p $(dir $@)\r
+endif\r
+ @echo $(MSG_ASSEMBLING)\r
+ $(Q)$(CC) $(a_flags) -c $< -o $@\r
+\r
+# Include all dependency files to add depedency to all header files in use.\r
+include $(dep-files)\r
+\r
+ifeq ($(target_type),lib)\r
+# Archive object files into an archive\r
+$(target): $(MAKEFILE_PATH) config.mk $(obj-y)\r
+ @echo $(MSG_ARCHIVING)\r
+ $(Q)$(AR) $(ar_flags) $@ $(obj-y)\r
+ @echo $(MSG_SIZE)\r
+ $(Q)$(SIZE) -Bxt $@\r
+else\r
+ifeq ($(target_type),elf)\r
+# Link the object files into an ELF file. Also make sure the target is rebuilt\r
+# if the common Makefile.sam.in or project config.mk is changed.\r
+$(target): $(linker_script) $(MAKEFILE_PATH) config.mk $(obj-y)\r
+ @echo $(MSG_LINKING)\r
+ $(Q)$(LD) $(l_flags) $(obj-y) $(libflags-gnu-y) -o $@\r
+ @echo $(MSG_SIZE)\r
+ $(Q)$(SIZE) -Ax $@\r
+ $(Q)$(SIZE) -Bx $@\r
+endif\r
+endif\r
+\r
+# Create extended function listing from target output file.\r
+%.lss: $(target)\r
+ @echo $(MSG_EXTENDED_LISTING)\r
+ $(Q)$(OBJDUMP) -h -S $< > $@\r
+\r
+# Create symbol table from target output file.\r
+%.sym: $(target)\r
+ @echo $(MSG_SYMBOL_TABLE)\r
+ $(Q)$(NM) -n $< > $@\r
+\r
+# Create Intel HEX image from ELF output file.\r
+%.hex: $(target)\r
+ @echo $(MSG_IHEX_IMAGE)\r
+ $(Q)$(OBJCOPY) -O ihex $(flashflags-gnu-y) $< $@\r
+\r
+# Create binary image from ELF output file.\r
+%.bin: $(target)\r
+ @echo $(MSG_BINARY_IMAGE)\r
+ $(Q)$(OBJCOPY) -O binary $< $@\r
+\r
+# Provide information about the detected host operating system.\r
+.SECONDARY: info-os\r
+info-os:\r
+ @echo $(MSG_INFO)$(os) build host detected\r
+\r
+# Build Doxygen generated documentation.\r
+.PHONY: doc\r
+doc:\r
+ @echo $(MSG_GENERATING_DOC)\r
+ $(Q)cd $(dir $(doccfg)) && $(DOCGEN) $(notdir $(doccfg))\r
+\r
+# Clean Doxygen generated documentation.\r
+.PHONY: cleandoc\r
+cleandoc:\r
+ @$(if $(wildcard $(docdir)),echo $(MSG_CLEAN_DOC))\r
+ $(Q)$(if $(wildcard $(docdir)),$(RM) --recursive $(docdir))\r
+\r
+# Rebuild the Doxygen generated documentation.\r
+.PHONY: rebuilddoc\r
+rebuilddoc: cleandoc doc\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Preprocessor macro repeating utils.\r
+ *\r
+ * Copyright (c) 2010-2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _MREPEAT_H_\r
+#define _MREPEAT_H_\r
+\r
+/**\r
+ * \defgroup group_sam_utils_mrepeat Preprocessor - Macro Repeat\r
+ *\r
+ * \ingroup group_sam_utils\r
+ *\r
+ * \{\r
+ */\r
+\r
+#include "preprocessor.h"\r
+\r
+\r
+//! Maximal number of repetitions supported by MREPEAT.\r
+#define MREPEAT_LIMIT 256\r
+\r
+/*! \brief Macro repeat.\r
+ *\r
+ * This macro represents a horizontal repetition construct.\r
+ *\r
+ * \param count The number of repetitious calls to macro. Valid values range from 0 to MREPEAT_LIMIT.\r
+ * \param macro A binary operation of the form macro(n, data). This macro is expanded by MREPEAT with\r
+ * the current repetition number and the auxiliary data argument.\r
+ * \param data Auxiliary data passed to macro.\r
+ *\r
+ * \return <tt>macro(0, data) macro(1, data) ... macro(count - 1, data)</tt>\r
+ */\r
+#define MREPEAT(count, macro, data) TPASTE2(MREPEAT, count)(macro, data)\r
+\r
+#define MREPEAT0( macro, data)\r
+#define MREPEAT1( macro, data) MREPEAT0( macro, data) macro( 0, data)\r
+#define MREPEAT2( macro, data) MREPEAT1( macro, data) macro( 1, data)\r
+#define MREPEAT3( macro, data) MREPEAT2( macro, data) macro( 2, data)\r
+#define MREPEAT4( macro, data) MREPEAT3( macro, data) macro( 3, data)\r
+#define MREPEAT5( macro, data) MREPEAT4( macro, data) macro( 4, data)\r
+#define MREPEAT6( macro, data) MREPEAT5( macro, data) macro( 5, data)\r
+#define MREPEAT7( macro, data) MREPEAT6( macro, data) macro( 6, data)\r
+#define MREPEAT8( macro, data) MREPEAT7( macro, data) macro( 7, data)\r
+#define MREPEAT9( macro, data) MREPEAT8( macro, data) macro( 8, data)\r
+#define MREPEAT10( macro, data) MREPEAT9( macro, data) macro( 9, data)\r
+#define MREPEAT11( macro, data) MREPEAT10( macro, data) macro( 10, data)\r
+#define MREPEAT12( macro, data) MREPEAT11( macro, data) macro( 11, data)\r
+#define MREPEAT13( macro, data) MREPEAT12( macro, data) macro( 12, data)\r
+#define MREPEAT14( macro, data) MREPEAT13( macro, data) macro( 13, data)\r
+#define MREPEAT15( macro, data) MREPEAT14( macro, data) macro( 14, data)\r
+#define MREPEAT16( macro, data) MREPEAT15( macro, data) macro( 15, data)\r
+#define MREPEAT17( macro, data) MREPEAT16( macro, data) macro( 16, data)\r
+#define MREPEAT18( macro, data) MREPEAT17( macro, data) macro( 17, data)\r
+#define MREPEAT19( macro, data) MREPEAT18( macro, data) macro( 18, data)\r
+#define MREPEAT20( macro, data) MREPEAT19( macro, data) macro( 19, data)\r
+#define MREPEAT21( macro, data) MREPEAT20( macro, data) macro( 20, data)\r
+#define MREPEAT22( macro, data) MREPEAT21( macro, data) macro( 21, data)\r
+#define MREPEAT23( macro, data) MREPEAT22( macro, data) macro( 22, data)\r
+#define MREPEAT24( macro, data) MREPEAT23( macro, data) macro( 23, data)\r
+#define MREPEAT25( macro, data) MREPEAT24( macro, data) macro( 24, data)\r
+#define MREPEAT26( macro, data) MREPEAT25( macro, data) macro( 25, data)\r
+#define MREPEAT27( macro, data) MREPEAT26( macro, data) macro( 26, data)\r
+#define MREPEAT28( macro, data) MREPEAT27( macro, data) macro( 27, data)\r
+#define MREPEAT29( macro, data) MREPEAT28( macro, data) macro( 28, data)\r
+#define MREPEAT30( macro, data) MREPEAT29( macro, data) macro( 29, data)\r
+#define MREPEAT31( macro, data) MREPEAT30( macro, data) macro( 30, data)\r
+#define MREPEAT32( macro, data) MREPEAT31( macro, data) macro( 31, data)\r
+#define MREPEAT33( macro, data) MREPEAT32( macro, data) macro( 32, data)\r
+#define MREPEAT34( macro, data) MREPEAT33( macro, data) macro( 33, data)\r
+#define MREPEAT35( macro, data) MREPEAT34( macro, data) macro( 34, data)\r
+#define MREPEAT36( macro, data) MREPEAT35( macro, data) macro( 35, data)\r
+#define MREPEAT37( macro, data) MREPEAT36( macro, data) macro( 36, data)\r
+#define MREPEAT38( macro, data) MREPEAT37( macro, data) macro( 37, data)\r
+#define MREPEAT39( macro, data) MREPEAT38( macro, data) macro( 38, data)\r
+#define MREPEAT40( macro, data) MREPEAT39( macro, data) macro( 39, data)\r
+#define MREPEAT41( macro, data) MREPEAT40( macro, data) macro( 40, data)\r
+#define MREPEAT42( macro, data) MREPEAT41( macro, data) macro( 41, data)\r
+#define MREPEAT43( macro, data) MREPEAT42( macro, data) macro( 42, data)\r
+#define MREPEAT44( macro, data) MREPEAT43( macro, data) macro( 43, data)\r
+#define MREPEAT45( macro, data) MREPEAT44( macro, data) macro( 44, data)\r
+#define MREPEAT46( macro, data) MREPEAT45( macro, data) macro( 45, data)\r
+#define MREPEAT47( macro, data) MREPEAT46( macro, data) macro( 46, data)\r
+#define MREPEAT48( macro, data) MREPEAT47( macro, data) macro( 47, data)\r
+#define MREPEAT49( macro, data) MREPEAT48( macro, data) macro( 48, data)\r
+#define MREPEAT50( macro, data) MREPEAT49( macro, data) macro( 49, data)\r
+#define MREPEAT51( macro, data) MREPEAT50( macro, data) macro( 50, data)\r
+#define MREPEAT52( macro, data) MREPEAT51( macro, data) macro( 51, data)\r
+#define MREPEAT53( macro, data) MREPEAT52( macro, data) macro( 52, data)\r
+#define MREPEAT54( macro, data) MREPEAT53( macro, data) macro( 53, data)\r
+#define MREPEAT55( macro, data) MREPEAT54( macro, data) macro( 54, data)\r
+#define MREPEAT56( macro, data) MREPEAT55( macro, data) macro( 55, data)\r
+#define MREPEAT57( macro, data) MREPEAT56( macro, data) macro( 56, data)\r
+#define MREPEAT58( macro, data) MREPEAT57( macro, data) macro( 57, data)\r
+#define MREPEAT59( macro, data) MREPEAT58( macro, data) macro( 58, data)\r
+#define MREPEAT60( macro, data) MREPEAT59( macro, data) macro( 59, data)\r
+#define MREPEAT61( macro, data) MREPEAT60( macro, data) macro( 60, data)\r
+#define MREPEAT62( macro, data) MREPEAT61( macro, data) macro( 61, data)\r
+#define MREPEAT63( macro, data) MREPEAT62( macro, data) macro( 62, data)\r
+#define MREPEAT64( macro, data) MREPEAT63( macro, data) macro( 63, data)\r
+#define MREPEAT65( macro, data) MREPEAT64( macro, data) macro( 64, data)\r
+#define MREPEAT66( macro, data) MREPEAT65( macro, data) macro( 65, data)\r
+#define MREPEAT67( macro, data) MREPEAT66( macro, data) macro( 66, data)\r
+#define MREPEAT68( macro, data) MREPEAT67( macro, data) macro( 67, data)\r
+#define MREPEAT69( macro, data) MREPEAT68( macro, data) macro( 68, data)\r
+#define MREPEAT70( macro, data) MREPEAT69( macro, data) macro( 69, data)\r
+#define MREPEAT71( macro, data) MREPEAT70( macro, data) macro( 70, data)\r
+#define MREPEAT72( macro, data) MREPEAT71( macro, data) macro( 71, data)\r
+#define MREPEAT73( macro, data) MREPEAT72( macro, data) macro( 72, data)\r
+#define MREPEAT74( macro, data) MREPEAT73( macro, data) macro( 73, data)\r
+#define MREPEAT75( macro, data) MREPEAT74( macro, data) macro( 74, data)\r
+#define MREPEAT76( macro, data) MREPEAT75( macro, data) macro( 75, data)\r
+#define MREPEAT77( macro, data) MREPEAT76( macro, data) macro( 76, data)\r
+#define MREPEAT78( macro, data) MREPEAT77( macro, data) macro( 77, data)\r
+#define MREPEAT79( macro, data) MREPEAT78( macro, data) macro( 78, data)\r
+#define MREPEAT80( macro, data) MREPEAT79( macro, data) macro( 79, data)\r
+#define MREPEAT81( macro, data) MREPEAT80( macro, data) macro( 80, data)\r
+#define MREPEAT82( macro, data) MREPEAT81( macro, data) macro( 81, data)\r
+#define MREPEAT83( macro, data) MREPEAT82( macro, data) macro( 82, data)\r
+#define MREPEAT84( macro, data) MREPEAT83( macro, data) macro( 83, data)\r
+#define MREPEAT85( macro, data) MREPEAT84( macro, data) macro( 84, data)\r
+#define MREPEAT86( macro, data) MREPEAT85( macro, data) macro( 85, data)\r
+#define MREPEAT87( macro, data) MREPEAT86( macro, data) macro( 86, data)\r
+#define MREPEAT88( macro, data) MREPEAT87( macro, data) macro( 87, data)\r
+#define MREPEAT89( macro, data) MREPEAT88( macro, data) macro( 88, data)\r
+#define MREPEAT90( macro, data) MREPEAT89( macro, data) macro( 89, data)\r
+#define MREPEAT91( macro, data) MREPEAT90( macro, data) macro( 90, data)\r
+#define MREPEAT92( macro, data) MREPEAT91( macro, data) macro( 91, data)\r
+#define MREPEAT93( macro, data) MREPEAT92( macro, data) macro( 92, data)\r
+#define MREPEAT94( macro, data) MREPEAT93( macro, data) macro( 93, data)\r
+#define MREPEAT95( macro, data) MREPEAT94( macro, data) macro( 94, data)\r
+#define MREPEAT96( macro, data) MREPEAT95( macro, data) macro( 95, data)\r
+#define MREPEAT97( macro, data) MREPEAT96( macro, data) macro( 96, data)\r
+#define MREPEAT98( macro, data) MREPEAT97( macro, data) macro( 97, data)\r
+#define MREPEAT99( macro, data) MREPEAT98( macro, data) macro( 98, data)\r
+#define MREPEAT100(macro, data) MREPEAT99( macro, data) macro( 99, data)\r
+#define MREPEAT101(macro, data) MREPEAT100(macro, data) macro(100, data)\r
+#define MREPEAT102(macro, data) MREPEAT101(macro, data) macro(101, data)\r
+#define MREPEAT103(macro, data) MREPEAT102(macro, data) macro(102, data)\r
+#define MREPEAT104(macro, data) MREPEAT103(macro, data) macro(103, data)\r
+#define MREPEAT105(macro, data) MREPEAT104(macro, data) macro(104, data)\r
+#define MREPEAT106(macro, data) MREPEAT105(macro, data) macro(105, data)\r
+#define MREPEAT107(macro, data) MREPEAT106(macro, data) macro(106, data)\r
+#define MREPEAT108(macro, data) MREPEAT107(macro, data) macro(107, data)\r
+#define MREPEAT109(macro, data) MREPEAT108(macro, data) macro(108, data)\r
+#define MREPEAT110(macro, data) MREPEAT109(macro, data) macro(109, data)\r
+#define MREPEAT111(macro, data) MREPEAT110(macro, data) macro(110, data)\r
+#define MREPEAT112(macro, data) MREPEAT111(macro, data) macro(111, data)\r
+#define MREPEAT113(macro, data) MREPEAT112(macro, data) macro(112, data)\r
+#define MREPEAT114(macro, data) MREPEAT113(macro, data) macro(113, data)\r
+#define MREPEAT115(macro, data) MREPEAT114(macro, data) macro(114, data)\r
+#define MREPEAT116(macro, data) MREPEAT115(macro, data) macro(115, data)\r
+#define MREPEAT117(macro, data) MREPEAT116(macro, data) macro(116, data)\r
+#define MREPEAT118(macro, data) MREPEAT117(macro, data) macro(117, data)\r
+#define MREPEAT119(macro, data) MREPEAT118(macro, data) macro(118, data)\r
+#define MREPEAT120(macro, data) MREPEAT119(macro, data) macro(119, data)\r
+#define MREPEAT121(macro, data) MREPEAT120(macro, data) macro(120, data)\r
+#define MREPEAT122(macro, data) MREPEAT121(macro, data) macro(121, data)\r
+#define MREPEAT123(macro, data) MREPEAT122(macro, data) macro(122, data)\r
+#define MREPEAT124(macro, data) MREPEAT123(macro, data) macro(123, data)\r
+#define MREPEAT125(macro, data) MREPEAT124(macro, data) macro(124, data)\r
+#define MREPEAT126(macro, data) MREPEAT125(macro, data) macro(125, data)\r
+#define MREPEAT127(macro, data) MREPEAT126(macro, data) macro(126, data)\r
+#define MREPEAT128(macro, data) MREPEAT127(macro, data) macro(127, data)\r
+#define MREPEAT129(macro, data) MREPEAT128(macro, data) macro(128, data)\r
+#define MREPEAT130(macro, data) MREPEAT129(macro, data) macro(129, data)\r
+#define MREPEAT131(macro, data) MREPEAT130(macro, data) macro(130, data)\r
+#define MREPEAT132(macro, data) MREPEAT131(macro, data) macro(131, data)\r
+#define MREPEAT133(macro, data) MREPEAT132(macro, data) macro(132, data)\r
+#define MREPEAT134(macro, data) MREPEAT133(macro, data) macro(133, data)\r
+#define MREPEAT135(macro, data) MREPEAT134(macro, data) macro(134, data)\r
+#define MREPEAT136(macro, data) MREPEAT135(macro, data) macro(135, data)\r
+#define MREPEAT137(macro, data) MREPEAT136(macro, data) macro(136, data)\r
+#define MREPEAT138(macro, data) MREPEAT137(macro, data) macro(137, data)\r
+#define MREPEAT139(macro, data) MREPEAT138(macro, data) macro(138, data)\r
+#define MREPEAT140(macro, data) MREPEAT139(macro, data) macro(139, data)\r
+#define MREPEAT141(macro, data) MREPEAT140(macro, data) macro(140, data)\r
+#define MREPEAT142(macro, data) MREPEAT141(macro, data) macro(141, data)\r
+#define MREPEAT143(macro, data) MREPEAT142(macro, data) macro(142, data)\r
+#define MREPEAT144(macro, data) MREPEAT143(macro, data) macro(143, data)\r
+#define MREPEAT145(macro, data) MREPEAT144(macro, data) macro(144, data)\r
+#define MREPEAT146(macro, data) MREPEAT145(macro, data) macro(145, data)\r
+#define MREPEAT147(macro, data) MREPEAT146(macro, data) macro(146, data)\r
+#define MREPEAT148(macro, data) MREPEAT147(macro, data) macro(147, data)\r
+#define MREPEAT149(macro, data) MREPEAT148(macro, data) macro(148, data)\r
+#define MREPEAT150(macro, data) MREPEAT149(macro, data) macro(149, data)\r
+#define MREPEAT151(macro, data) MREPEAT150(macro, data) macro(150, data)\r
+#define MREPEAT152(macro, data) MREPEAT151(macro, data) macro(151, data)\r
+#define MREPEAT153(macro, data) MREPEAT152(macro, data) macro(152, data)\r
+#define MREPEAT154(macro, data) MREPEAT153(macro, data) macro(153, data)\r
+#define MREPEAT155(macro, data) MREPEAT154(macro, data) macro(154, data)\r
+#define MREPEAT156(macro, data) MREPEAT155(macro, data) macro(155, data)\r
+#define MREPEAT157(macro, data) MREPEAT156(macro, data) macro(156, data)\r
+#define MREPEAT158(macro, data) MREPEAT157(macro, data) macro(157, data)\r
+#define MREPEAT159(macro, data) MREPEAT158(macro, data) macro(158, data)\r
+#define MREPEAT160(macro, data) MREPEAT159(macro, data) macro(159, data)\r
+#define MREPEAT161(macro, data) MREPEAT160(macro, data) macro(160, data)\r
+#define MREPEAT162(macro, data) MREPEAT161(macro, data) macro(161, data)\r
+#define MREPEAT163(macro, data) MREPEAT162(macro, data) macro(162, data)\r
+#define MREPEAT164(macro, data) MREPEAT163(macro, data) macro(163, data)\r
+#define MREPEAT165(macro, data) MREPEAT164(macro, data) macro(164, data)\r
+#define MREPEAT166(macro, data) MREPEAT165(macro, data) macro(165, data)\r
+#define MREPEAT167(macro, data) MREPEAT166(macro, data) macro(166, data)\r
+#define MREPEAT168(macro, data) MREPEAT167(macro, data) macro(167, data)\r
+#define MREPEAT169(macro, data) MREPEAT168(macro, data) macro(168, data)\r
+#define MREPEAT170(macro, data) MREPEAT169(macro, data) macro(169, data)\r
+#define MREPEAT171(macro, data) MREPEAT170(macro, data) macro(170, data)\r
+#define MREPEAT172(macro, data) MREPEAT171(macro, data) macro(171, data)\r
+#define MREPEAT173(macro, data) MREPEAT172(macro, data) macro(172, data)\r
+#define MREPEAT174(macro, data) MREPEAT173(macro, data) macro(173, data)\r
+#define MREPEAT175(macro, data) MREPEAT174(macro, data) macro(174, data)\r
+#define MREPEAT176(macro, data) MREPEAT175(macro, data) macro(175, data)\r
+#define MREPEAT177(macro, data) MREPEAT176(macro, data) macro(176, data)\r
+#define MREPEAT178(macro, data) MREPEAT177(macro, data) macro(177, data)\r
+#define MREPEAT179(macro, data) MREPEAT178(macro, data) macro(178, data)\r
+#define MREPEAT180(macro, data) MREPEAT179(macro, data) macro(179, data)\r
+#define MREPEAT181(macro, data) MREPEAT180(macro, data) macro(180, data)\r
+#define MREPEAT182(macro, data) MREPEAT181(macro, data) macro(181, data)\r
+#define MREPEAT183(macro, data) MREPEAT182(macro, data) macro(182, data)\r
+#define MREPEAT184(macro, data) MREPEAT183(macro, data) macro(183, data)\r
+#define MREPEAT185(macro, data) MREPEAT184(macro, data) macro(184, data)\r
+#define MREPEAT186(macro, data) MREPEAT185(macro, data) macro(185, data)\r
+#define MREPEAT187(macro, data) MREPEAT186(macro, data) macro(186, data)\r
+#define MREPEAT188(macro, data) MREPEAT187(macro, data) macro(187, data)\r
+#define MREPEAT189(macro, data) MREPEAT188(macro, data) macro(188, data)\r
+#define MREPEAT190(macro, data) MREPEAT189(macro, data) macro(189, data)\r
+#define MREPEAT191(macro, data) MREPEAT190(macro, data) macro(190, data)\r
+#define MREPEAT192(macro, data) MREPEAT191(macro, data) macro(191, data)\r
+#define MREPEAT193(macro, data) MREPEAT192(macro, data) macro(192, data)\r
+#define MREPEAT194(macro, data) MREPEAT193(macro, data) macro(193, data)\r
+#define MREPEAT195(macro, data) MREPEAT194(macro, data) macro(194, data)\r
+#define MREPEAT196(macro, data) MREPEAT195(macro, data) macro(195, data)\r
+#define MREPEAT197(macro, data) MREPEAT196(macro, data) macro(196, data)\r
+#define MREPEAT198(macro, data) MREPEAT197(macro, data) macro(197, data)\r
+#define MREPEAT199(macro, data) MREPEAT198(macro, data) macro(198, data)\r
+#define MREPEAT200(macro, data) MREPEAT199(macro, data) macro(199, data)\r
+#define MREPEAT201(macro, data) MREPEAT200(macro, data) macro(200, data)\r
+#define MREPEAT202(macro, data) MREPEAT201(macro, data) macro(201, data)\r
+#define MREPEAT203(macro, data) MREPEAT202(macro, data) macro(202, data)\r
+#define MREPEAT204(macro, data) MREPEAT203(macro, data) macro(203, data)\r
+#define MREPEAT205(macro, data) MREPEAT204(macro, data) macro(204, data)\r
+#define MREPEAT206(macro, data) MREPEAT205(macro, data) macro(205, data)\r
+#define MREPEAT207(macro, data) MREPEAT206(macro, data) macro(206, data)\r
+#define MREPEAT208(macro, data) MREPEAT207(macro, data) macro(207, data)\r
+#define MREPEAT209(macro, data) MREPEAT208(macro, data) macro(208, data)\r
+#define MREPEAT210(macro, data) MREPEAT209(macro, data) macro(209, data)\r
+#define MREPEAT211(macro, data) MREPEAT210(macro, data) macro(210, data)\r
+#define MREPEAT212(macro, data) MREPEAT211(macro, data) macro(211, data)\r
+#define MREPEAT213(macro, data) MREPEAT212(macro, data) macro(212, data)\r
+#define MREPEAT214(macro, data) MREPEAT213(macro, data) macro(213, data)\r
+#define MREPEAT215(macro, data) MREPEAT214(macro, data) macro(214, data)\r
+#define MREPEAT216(macro, data) MREPEAT215(macro, data) macro(215, data)\r
+#define MREPEAT217(macro, data) MREPEAT216(macro, data) macro(216, data)\r
+#define MREPEAT218(macro, data) MREPEAT217(macro, data) macro(217, data)\r
+#define MREPEAT219(macro, data) MREPEAT218(macro, data) macro(218, data)\r
+#define MREPEAT220(macro, data) MREPEAT219(macro, data) macro(219, data)\r
+#define MREPEAT221(macro, data) MREPEAT220(macro, data) macro(220, data)\r
+#define MREPEAT222(macro, data) MREPEAT221(macro, data) macro(221, data)\r
+#define MREPEAT223(macro, data) MREPEAT222(macro, data) macro(222, data)\r
+#define MREPEAT224(macro, data) MREPEAT223(macro, data) macro(223, data)\r
+#define MREPEAT225(macro, data) MREPEAT224(macro, data) macro(224, data)\r
+#define MREPEAT226(macro, data) MREPEAT225(macro, data) macro(225, data)\r
+#define MREPEAT227(macro, data) MREPEAT226(macro, data) macro(226, data)\r
+#define MREPEAT228(macro, data) MREPEAT227(macro, data) macro(227, data)\r
+#define MREPEAT229(macro, data) MREPEAT228(macro, data) macro(228, data)\r
+#define MREPEAT230(macro, data) MREPEAT229(macro, data) macro(229, data)\r
+#define MREPEAT231(macro, data) MREPEAT230(macro, data) macro(230, data)\r
+#define MREPEAT232(macro, data) MREPEAT231(macro, data) macro(231, data)\r
+#define MREPEAT233(macro, data) MREPEAT232(macro, data) macro(232, data)\r
+#define MREPEAT234(macro, data) MREPEAT233(macro, data) macro(233, data)\r
+#define MREPEAT235(macro, data) MREPEAT234(macro, data) macro(234, data)\r
+#define MREPEAT236(macro, data) MREPEAT235(macro, data) macro(235, data)\r
+#define MREPEAT237(macro, data) MREPEAT236(macro, data) macro(236, data)\r
+#define MREPEAT238(macro, data) MREPEAT237(macro, data) macro(237, data)\r
+#define MREPEAT239(macro, data) MREPEAT238(macro, data) macro(238, data)\r
+#define MREPEAT240(macro, data) MREPEAT239(macro, data) macro(239, data)\r
+#define MREPEAT241(macro, data) MREPEAT240(macro, data) macro(240, data)\r
+#define MREPEAT242(macro, data) MREPEAT241(macro, data) macro(241, data)\r
+#define MREPEAT243(macro, data) MREPEAT242(macro, data) macro(242, data)\r
+#define MREPEAT244(macro, data) MREPEAT243(macro, data) macro(243, data)\r
+#define MREPEAT245(macro, data) MREPEAT244(macro, data) macro(244, data)\r
+#define MREPEAT246(macro, data) MREPEAT245(macro, data) macro(245, data)\r
+#define MREPEAT247(macro, data) MREPEAT246(macro, data) macro(246, data)\r
+#define MREPEAT248(macro, data) MREPEAT247(macro, data) macro(247, data)\r
+#define MREPEAT249(macro, data) MREPEAT248(macro, data) macro(248, data)\r
+#define MREPEAT250(macro, data) MREPEAT249(macro, data) macro(249, data)\r
+#define MREPEAT251(macro, data) MREPEAT250(macro, data) macro(250, data)\r
+#define MREPEAT252(macro, data) MREPEAT251(macro, data) macro(251, data)\r
+#define MREPEAT253(macro, data) MREPEAT252(macro, data) macro(252, data)\r
+#define MREPEAT254(macro, data) MREPEAT253(macro, data) macro(253, data)\r
+#define MREPEAT255(macro, data) MREPEAT254(macro, data) macro(254, data)\r
+#define MREPEAT256(macro, data) MREPEAT255(macro, data) macro(255, data)\r
+\r
+/**\r
+ * \}\r
+ */\r
+\r
+#endif // _MREPEAT_H_\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Preprocessor utils.\r
+ *\r
+ * Copyright (c) 2010-2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _PREPROCESSOR_H_\r
+#define _PREPROCESSOR_H_\r
+\r
+#include "tpaste.h"\r
+#include "stringz.h"\r
+#include "mrepeat.h"\r
+\r
+\r
+#endif // _PREPROCESSOR_H_\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Preprocessor stringizing utils.\r
+ *\r
+ * Copyright (c) 2010-2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _STRINGZ_H_\r
+#define _STRINGZ_H_\r
+\r
+/**\r
+ * \defgroup group_sam_utils_stringz Preprocessor - Stringize\r
+ *\r
+ * \ingroup group_sam_utils\r
+ *\r
+ * \{\r
+ */\r
+\r
+/*! \brief Stringize.\r
+ *\r
+ * Stringize a preprocessing token, this token being allowed to be \#defined.\r
+ *\r
+ * May be used only within macros with the token passed as an argument if the token is \#defined.\r
+ *\r
+ * For example, writing STRINGZ(PIN) within a macro \#defined by PIN_NAME(PIN)\r
+ * and invoked as PIN_NAME(PIN0) with PIN0 \#defined as A0 is equivalent to\r
+ * writing "A0".\r
+ */\r
+#define STRINGZ(x) #x\r
+\r
+/*! \brief Absolute stringize.\r
+ *\r
+ * Stringize a preprocessing token, this token being allowed to be \#defined.\r
+ *\r
+ * No restriction of use if the token is \#defined.\r
+ *\r
+ * For example, writing ASTRINGZ(PIN0) anywhere with PIN0 \#defined as A0 is\r
+ * equivalent to writing "A0".\r
+ */\r
+#define ASTRINGZ(x) STRINGZ(x)\r
+\r
+/**\r
+ * \}\r
+ */\r
+\r
+#endif // _STRINGZ_H_\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Preprocessor token pasting utils.\r
+ *\r
+ * Copyright (c) 2010-2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _TPASTE_H_\r
+#define _TPASTE_H_\r
+\r
+/**\r
+ * \defgroup group_sam_utils_tpaste Preprocessor - Token Paste\r
+ *\r
+ * \ingroup group_sam_utils\r
+ *\r
+ * \{\r
+ */\r
+\r
+/*! \name Token Paste\r
+ *\r
+ * Paste N preprocessing tokens together, these tokens being allowed to be \#defined.\r
+ *\r
+ * May be used only within macros with the tokens passed as arguments if the tokens are \#defined.\r
+ *\r
+ * For example, writing TPASTE2(U, WIDTH) within a macro \#defined by\r
+ * UTYPE(WIDTH) and invoked as UTYPE(UL_WIDTH) with UL_WIDTH \#defined as 32 is\r
+ * equivalent to writing U32.\r
+ */\r
+//! @{\r
+#define TPASTE2( a, b) a##b\r
+#define TPASTE3( a, b, c) a##b##c\r
+#define TPASTE4( a, b, c, d) a##b##c##d\r
+#define TPASTE5( a, b, c, d, e) a##b##c##d##e\r
+#define TPASTE6( a, b, c, d, e, f) a##b##c##d##e##f\r
+#define TPASTE7( a, b, c, d, e, f, g) a##b##c##d##e##f##g\r
+#define TPASTE8( a, b, c, d, e, f, g, h) a##b##c##d##e##f##g##h\r
+#define TPASTE9( a, b, c, d, e, f, g, h, i) a##b##c##d##e##f##g##h##i\r
+#define TPASTE10(a, b, c, d, e, f, g, h, i, j) a##b##c##d##e##f##g##h##i##j\r
+//! @}\r
+\r
+/*! \name Absolute Token Paste\r
+ *\r
+ * Paste N preprocessing tokens together, these tokens being allowed to be \#defined.\r
+ *\r
+ * No restriction of use if the tokens are \#defined.\r
+ *\r
+ * For example, writing ATPASTE2(U, UL_WIDTH) anywhere with UL_WIDTH \#defined\r
+ * as 32 is equivalent to writing U32.\r
+ */\r
+//! @{\r
+#define ATPASTE2( a, b) TPASTE2( a, b)\r
+#define ATPASTE3( a, b, c) TPASTE3( a, b, c)\r
+#define ATPASTE4( a, b, c, d) TPASTE4( a, b, c, d)\r
+#define ATPASTE5( a, b, c, d, e) TPASTE5( a, b, c, d, e)\r
+#define ATPASTE6( a, b, c, d, e, f) TPASTE6( a, b, c, d, e, f)\r
+#define ATPASTE7( a, b, c, d, e, f, g) TPASTE7( a, b, c, d, e, f, g)\r
+#define ATPASTE8( a, b, c, d, e, f, g, h) TPASTE8( a, b, c, d, e, f, g, h)\r
+#define ATPASTE9( a, b, c, d, e, f, g, h, i) TPASTE9( a, b, c, d, e, f, g, h, i)\r
+#define ATPASTE10(a, b, c, d, e, f, g, h, i, j) TPASTE10(a, b, c, d, e, f, g, h, i, j)\r
+//! @}\r
+\r
+/**\r
+ * \}\r
+ */\r
+\r
+#endif // _TPASTE_H_\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Status code definitions.\r
+ *\r
+ * This file defines various status codes returned by functions,\r
+ * indicating success or failure as well as what kind of failure.\r
+ *\r
+ * Copyright (c) 2011-2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef STATUS_CODES_H_INCLUDED\r
+#define STATUS_CODES_H_INCLUDED\r
+\r
+/* Note: this is a local workaround to avoid a pre-processor clash due to the\r
+ * lwIP macro ERR_TIMEOUT. */\r
+#if defined(__LWIP_ERR_H__) && defined(ERR_TIMEOUT)\r
+#if (ERR_TIMEOUT != -3)\r
+\r
+/* Internal check to make sure that the later restore of lwIP's ERR_TIMEOUT\r
+ * macro is set to the correct value. Note that it is highly improbable that\r
+ * this value ever changes in lwIP. */\r
+#error ASF developers: check lwip err.h new value for ERR_TIMEOUT\r
+#endif\r
+#undef ERR_TIMEOUT\r
+#endif\r
+\r
+/**\r
+ * Status code that may be returned by shell commands and protocol\r
+ * implementations.\r
+ *\r
+ * \note Any change to these status codes and the corresponding\r
+ * message strings is strictly forbidden. New codes can be added,\r
+ * however, but make sure that any message string tables are updated\r
+ * at the same time.\r
+ */\r
+enum status_code {\r
+ STATUS_OK = 0, //!< Success\r
+ STATUS_ERR_BUSY = 0x19,\r
+ STATUS_ERR_DENIED = 0x1C,\r
+ STATUS_ERR_TIMEOUT = 0x12,\r
+ ERR_IO_ERROR = -1, //!< I/O error\r
+ ERR_FLUSHED = -2, //!< Request flushed from queue\r
+ ERR_TIMEOUT = -3, //!< Operation timed out\r
+ ERR_BAD_DATA = -4, //!< Data integrity check failed\r
+ ERR_PROTOCOL = -5, //!< Protocol error\r
+ ERR_UNSUPPORTED_DEV = -6, //!< Unsupported device\r
+ ERR_NO_MEMORY = -7, //!< Insufficient memory\r
+ ERR_INVALID_ARG = -8, //!< Invalid argument\r
+ ERR_BAD_ADDRESS = -9, //!< Bad address\r
+ ERR_BUSY = -10, //!< Resource is busy\r
+ ERR_BAD_FORMAT = -11, //!< Data format not recognized\r
+ ERR_NO_TIMER = -12, //!< No timer available\r
+ ERR_TIMER_ALREADY_RUNNING = -13, //!< Timer already running\r
+ ERR_TIMER_NOT_RUNNING = -14, //!< Timer not running\r
+\r
+ /**\r
+ * \brief Operation in progress\r
+ *\r
+ * This status code is for driver-internal use when an operation\r
+ * is currently being performed.\r
+ *\r
+ * \note Drivers should never return this status code to any\r
+ * callers. It is strictly for internal use.\r
+ */\r
+ OPERATION_IN_PROGRESS = -128,\r
+};\r
+\r
+typedef enum status_code status_code_t;\r
+\r
+#if defined(__LWIP_ERR_H__)\r
+#define ERR_TIMEOUT -3\r
+#endif\r
+\r
+#endif /* STATUS_CODES_H_INCLUDED */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Syscalls for SAM (GCC).\r
+ *\r
+ * Copyright (c) 2011-2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#include <stdio.h>\r
+#include <stdarg.h>\r
+#include <sys/types.h>\r
+#include <sys/stat.h>\r
+\r
+/// @cond 0\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+/**INDENT-ON**/\r
+/// @endcond\r
+\r
+#undef errno\r
+extern int errno;\r
+extern int _end;\r
+\r
+extern caddr_t _sbrk(int incr);\r
+extern int link(char *old, char *new);\r
+extern int _close(int file);\r
+extern int _fstat(int file, struct stat *st);\r
+extern int _isatty(int file);\r
+extern int _lseek(int file, int ptr, int dir);\r
+extern void _exit(int status);\r
+extern void _kill(int pid, int sig);\r
+extern int _getpid(void);\r
+\r
+extern caddr_t _sbrk(int incr)\r
+{\r
+ static unsigned char *heap = NULL;\r
+ unsigned char *prev_heap;\r
+\r
+ if (heap == NULL) {\r
+ heap = (unsigned char *)&_end;\r
+ }\r
+ prev_heap = heap;\r
+\r
+ heap += incr;\r
+\r
+ return (caddr_t) prev_heap;\r
+}\r
+\r
+extern int link(char *old, char *new)\r
+{\r
+ ( void ) old;\r
+ ( void ) new;\r
+ return -1;\r
+}\r
+\r
+extern int _close(int file)\r
+{\r
+ ( void ) file;\r
+ return -1;\r
+}\r
+\r
+extern int _fstat(int file, struct stat *st)\r
+{\r
+ ( void ) file;\r
+ ( void ) st;\r
+ st->st_mode = S_IFCHR;\r
+\r
+ return 0;\r
+}\r
+\r
+extern int _isatty(int file)\r
+{\r
+ ( void ) file;\r
+ return 1;\r
+}\r
+\r
+extern int _lseek(int file, int ptr, int dir)\r
+{\r
+ ( void ) file;\r
+ ( void ) ptr;\r
+ ( void ) dir;\r
+ return 0;\r
+}\r
+\r
+extern void _exit(int status)\r
+{\r
+ printf("Exiting with status %d.\n", status);\r
+\r
+ for (;;);\r
+}\r
+\r
+extern void _kill(int pid, int sig)\r
+{\r
+ ( void ) pid;\r
+ ( void ) sig;\r
+ return;\r
+}\r
+\r
+extern int _getpid(void)\r
+{\r
+ return -1;\r
+}\r
+\r
+/// @cond 0\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+/**INDENT-ON**/\r
+/// @endcond\r
--- /dev/null
+/* ----------------------------------------------------------------------\r
+ * Copyright (C) 2010-2011 ARM Limited. All rights reserved.\r
+ *\r
+ * $Date: 15. July 2011\r
+ * $Revision: V1.0.10\r
+ *\r
+ * Project: CMSIS DSP Library\r
+ * Title: arm_math.h\r
+ *\r
+ * Description: Public header file for CMSIS DSP Library\r
+ *\r
+ * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\r
+ *\r
+ * Version 1.0.10 2011/7/15\r
+ * Big Endian support added and Merged M0 and M3/M4 Source code.\r
+ *\r
+ * Version 1.0.3 2010/11/29\r
+ * Re-organized the CMSIS folders and updated documentation.\r
+ *\r
+ * Version 1.0.2 2010/11/11\r
+ * Documentation updated.\r
+ *\r
+ * Version 1.0.1 2010/10/05\r
+ * Production release and review comments incorporated.\r
+ *\r
+ * Version 1.0.0 2010/09/20\r
+ * Production release and review comments incorporated.\r
+ * -------------------------------------------------------------------- */\r
+\r
+/**\r
+ \mainpage CMSIS DSP Software Library\r
+ *\r
+ * <b>Introduction</b>\r
+ *\r
+ * This user manual describes the CMSIS DSP software library,\r
+ * a suite of common signal processing functions for use on Cortex-M processor based devices.\r
+ *\r
+ * The library is divided into a number of modules each covering a specific category:\r
+ * - Basic math functions\r
+ * - Fast math functions\r
+ * - Complex math functions\r
+ * - Filters\r
+ * - Matrix functions\r
+ * - Transforms\r
+ * - Motor control functions\r
+ * - Statistical functions\r
+ * - Support functions\r
+ * - Interpolation functions\r
+ *\r
+ * The library has separate functions for operating on 8-bit integers, 16-bit integers,\r
+ * 32-bit integer and 32-bit floating-point values.\r
+ *\r
+ * <b>Processor Support</b>\r
+ *\r
+ * The library is completely written in C and is fully CMSIS compliant.\r
+ * High performance is achieved through maximum use of Cortex-M4 intrinsics.\r
+ *\r
+ * The supplied library source code also builds and runs on the Cortex-M3 and Cortex-M0 processor,\r
+ * with the DSP intrinsics being emulated through software.\r
+ *\r
+ *\r
+ * <b>Toolchain Support</b>\r
+ *\r
+ * The library has been developed and tested with MDK-ARM version 4.21.\r
+ * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly.\r
+ *\r
+ * <b>Using the Library</b>\r
+ *\r
+ * The library installer contains prebuilt versions of the libraries in the <code>Lib</code> folder.\r
+ * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4)\r
+ * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4)\r
+ * - arm_cortexM4l_math.lib (Little endian on Cortex-M4)\r
+ * - arm_cortexM4b_math.lib (Big endian on Cortex-M4)\r
+ * - arm_cortexM3l_math.lib (Little endian on Cortex-M3)\r
+ * - arm_cortexM3b_math.lib (Big endian on Cortex-M3)\r
+ * - arm_cortexM0l_math.lib (Little endian on Cortex-M0)\r
+ * - arm_cortexM0b_math.lib (Big endian on Cortex-M3)\r
+ *\r
+ * The library functions are declared in the public file <code>arm_math.h</code> which is placed in the <code>Include</code> folder.\r
+ * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single\r
+ * public header file <code>arm_math.h</code> for Cortex-M4/M3/M0 with little endian and big endian. Same header file will be used for floating point unit(FPU) variants.\r
+ * Define the appropriate pre processor MACRO ARM_MATH_CM4 or ARM_MATH_CM3 or\r
+ * ARM_MATH_CM0 depending on the target processor in the application.\r
+ *\r
+ * <b>Examples</b>\r
+ *\r
+ * The library ships with a number of examples which demonstrate how to use the library functions.\r
+ *\r
+ * <b>Building the Library</b>\r
+ *\r
+ * The library installer contains project files to re build libraries on MDK Tool chain in the <code>CMSIS\\DSP_Lib\\Source\\ARM</code> folder.\r
+ * - arm_cortexM0b_math.uvproj\r
+ * - arm_cortexM0l_math.uvproj\r
+ * - arm_cortexM3b_math.uvproj\r
+ * - arm_cortexM3l_math.uvproj\r
+ * - arm_cortexM4b_math.uvproj\r
+ * - arm_cortexM4l_math.uvproj\r
+ * - arm_cortexM4bf_math.uvproj\r
+ * - arm_cortexM4lf_math.uvproj\r
+ *\r
+ * Each library project have differant pre-processor macros.\r
+ *\r
+ * <b>ARM_MATH_CMx:</b>\r
+ * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target\r
+ * and ARM_MATH_CM0 for building library on cortex-M0 target.\r
+ *\r
+ * <b>ARM_MATH_BIG_ENDIAN:</b>\r
+ * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets.\r
+ *\r
+ * <b>ARM_MATH_MATRIX_CHECK:</b>\r
+ * Define macro for checking on the input and output sizes of matrices\r
+ *\r
+ * <b>ARM_MATH_ROUNDING:</b>\r
+ * Define macro for rounding on support functions\r
+ *\r
+ * <b>__FPU_PRESENT:</b>\r
+ * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries\r
+ *\r
+ *\r
+ * The project can be built by opening the appropriate project in MDK-ARM 4.21 chain and defining the optional pre processor MACROs detailed above.\r
+ *\r
+ * <b>Copyright Notice</b>\r
+ *\r
+ * Copyright (C) 2010 ARM Limited. All rights reserved.\r
+ */\r
+\r
+\r
+/**\r
+ * @defgroup groupMath Basic Math Functions\r
+ */\r
+\r
+/**\r
+ * @defgroup groupFastMath Fast Math Functions\r
+ * This set of functions provides a fast approximation to sine, cosine, and square root.\r
+ * As compared to most of the other functions in the CMSIS math library, the fast math functions\r
+ * operate on individual values and not arrays.\r
+ * There are separate functions for Q15, Q31, and floating-point data.\r
+ *\r
+ */\r
+\r
+/**\r
+ * @defgroup groupCmplxMath Complex Math Functions\r
+ * This set of functions operates on complex data vectors.\r
+ * The data in the complex arrays is stored in an interleaved fashion\r
+ * (real, imag, real, imag, ...).\r
+ * In the API functions, the number of samples in a complex array refers\r
+ * to the number of complex values; the array contains twice this number of\r
+ * real values.\r
+ */\r
+\r
+/**\r
+ * @defgroup groupFilters Filtering Functions\r
+ */\r
+\r
+/**\r
+ * @defgroup groupMatrix Matrix Functions\r
+ *\r
+ * This set of functions provides basic matrix math operations.\r
+ * The functions operate on matrix data structures. For example,\r
+ * the type\r
+ * definition for the floating-point matrix structure is shown\r
+ * below:\r
+ * <pre>\r
+ * typedef struct\r
+ * {\r
+ * uint16_t numRows; // number of rows of the matrix.\r
+ * uint16_t numCols; // number of columns of the matrix.\r
+ * float32_t *pData; // points to the data of the matrix.\r
+ * } arm_matrix_instance_f32;\r
+ * </pre>\r
+ * There are similar definitions for Q15 and Q31 data types.\r
+ *\r
+ * The structure specifies the size of the matrix and then points to\r
+ * an array of data. The array is of size <code>numRows X numCols</code>\r
+ * and the values are arranged in row order. That is, the\r
+ * matrix element (i, j) is stored at:\r
+ * <pre>\r
+ * pData[i*numCols + j]\r
+ * </pre>\r
+ *\r
+ * \par Init Functions\r
+ * There is an associated initialization function for each type of matrix\r
+ * data structure.\r
+ * The initialization function sets the values of the internal structure fields.\r
+ * Refer to the function <code>arm_mat_init_f32()</code>, <code>arm_mat_init_q31()</code>\r
+ * and <code>arm_mat_init_q15()</code> for floating-point, Q31 and Q15 types, respectively.\r
+ *\r
+ * \par\r
+ * Use of the initialization function is optional. However, if initialization function is used\r
+ * then the instance structure cannot be placed into a const data section.\r
+ * To place the instance structure in a const data\r
+ * section, manually initialize the data structure. For example:\r
+ * <pre>\r
+ * <code>arm_matrix_instance_f32 S = {nRows, nColumns, pData};</code>\r
+ * <code>arm_matrix_instance_q31 S = {nRows, nColumns, pData};</code>\r
+ * <code>arm_matrix_instance_q15 S = {nRows, nColumns, pData};</code>\r
+ * </pre>\r
+ * where <code>nRows</code> specifies the number of rows, <code>nColumns</code>\r
+ * specifies the number of columns, and <code>pData</code> points to the\r
+ * data array.\r
+ *\r
+ * \par Size Checking\r
+ * By default all of the matrix functions perform size checking on the input and\r
+ * output matrices. For example, the matrix addition function verifies that the\r
+ * two input matrices and the output matrix all have the same number of rows and\r
+ * columns. If the size check fails the functions return:\r
+ * <pre>\r
+ * ARM_MATH_SIZE_MISMATCH\r
+ * </pre>\r
+ * Otherwise the functions return\r
+ * <pre>\r
+ * ARM_MATH_SUCCESS\r
+ * </pre>\r
+ * There is some overhead associated with this matrix size checking.\r
+ * The matrix size checking is enabled via the \#define\r
+ * <pre>\r
+ * ARM_MATH_MATRIX_CHECK\r
+ * </pre>\r
+ * within the library project settings. By default this macro is defined\r
+ * and size checking is enabled. By changing the project settings and\r
+ * undefining this macro size checking is eliminated and the functions\r
+ * run a bit faster. With size checking disabled the functions always\r
+ * return <code>ARM_MATH_SUCCESS</code>.\r
+ */\r
+\r
+/**\r
+ * @defgroup groupTransforms Transform Functions\r
+ */\r
+\r
+/**\r
+ * @defgroup groupController Controller Functions\r
+ */\r
+\r
+/**\r
+ * @defgroup groupStats Statistics Functions\r
+ */\r
+/**\r
+ * @defgroup groupSupport Support Functions\r
+ */\r
+\r
+/**\r
+ * @defgroup groupInterpolation Interpolation Functions\r
+ * These functions perform 1- and 2-dimensional interpolation of data.\r
+ * Linear interpolation is used for 1-dimensional data and\r
+ * bilinear interpolation is used for 2-dimensional data.\r
+ */\r
+\r
+/**\r
+ * @defgroup groupExamples Examples\r
+ */\r
+#ifndef _ARM_MATH_H\r
+#define _ARM_MATH_H\r
+\r
+#define __CMSIS_GENERIC /* disable NVIC and Systick functions */\r
+\r
+#if defined (ARM_MATH_CM4)\r
+ #include "core_cm4.h"\r
+#elif defined (ARM_MATH_CM3)\r
+ #include "core_cm3.h"\r
+#elif defined (ARM_MATH_CM0)\r
+ #include "core_cm0.h"\r
+#else\r
+#include "ARMCM4.h"\r
+#warning "Define either ARM_MATH_CM4 OR ARM_MATH_CM3...By Default building on ARM_MATH_CM4....."\r
+#endif\r
+\r
+#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */\r
+#include "string.h"\r
+ #include "math.h"\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+\r
+ /**\r
+ * @brief Macros required for reciprocal calculation in Normalized LMS\r
+ */\r
+\r
+#define DELTA_Q31 (0x100)\r
+#define DELTA_Q15 0x5\r
+#define INDEX_MASK 0x0000003F\r
+#define PI 3.14159265358979f\r
+\r
+ /**\r
+ * @brief Macros required for SINE and COSINE Fast math approximations\r
+ */\r
+\r
+#define TABLE_SIZE 256\r
+#define TABLE_SPACING_Q31 0x800000\r
+#define TABLE_SPACING_Q15 0x80\r
+\r
+ /**\r
+ * @brief Macros required for SINE and COSINE Controller functions\r
+ */\r
+ /* 1.31(q31) Fixed value of 2/360 */\r
+ /* -1 to +1 is divided into 360 values so total spacing is (2/360) */\r
+#define INPUT_SPACING 0xB60B61\r
+\r
+\r
+ /**\r
+ * @brief Error status returned by some functions in the library.\r
+ */\r
+\r
+ typedef enum\r
+ {\r
+ ARM_MATH_SUCCESS = 0, /**< No error */\r
+ ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */\r
+ ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */\r
+ ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */\r
+ ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */\r
+ ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */\r
+ ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */\r
+ } arm_status;\r
+\r
+ /**\r
+ * @brief 8-bit fractional data type in 1.7 format.\r
+ */\r
+ typedef int8_t q7_t;\r
+\r
+ /**\r
+ * @brief 16-bit fractional data type in 1.15 format.\r
+ */\r
+ typedef int16_t q15_t;\r
+\r
+ /**\r
+ * @brief 32-bit fractional data type in 1.31 format.\r
+ */\r
+ typedef int32_t q31_t;\r
+\r
+ /**\r
+ * @brief 64-bit fractional data type in 1.63 format.\r
+ */\r
+ typedef int64_t q63_t;\r
+\r
+ /**\r
+ * @brief 32-bit floating-point type definition.\r
+ */\r
+ typedef float float32_t;\r
+\r
+ /**\r
+ * @brief 64-bit floating-point type definition.\r
+ */\r
+ typedef double float64_t;\r
+\r
+ /**\r
+ * @brief definition to read/write two 16 bit values.\r
+ */\r
+#define __SIMD32(addr) (*(int32_t **) & (addr))\r
+\r
+#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0)\r
+ /**\r
+ * @brief definition to pack two 16 bit values.\r
+ */\r
+#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \\r
+ (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) )\r
+\r
+#endif\r
+\r
+\r
+ /**\r
+ * @brief definition to pack four 8 bit values.\r
+ */\r
+#ifndef ARM_MATH_BIG_ENDIAN\r
+\r
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \\r
+ (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \\r
+ (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \\r
+ (((int32_t)(v3) << 24) & (int32_t)0xFF000000) )\r
+#else\r
+\r
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \\r
+ (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \\r
+ (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \\r
+ (((int32_t)(v0) << 24) & (int32_t)0xFF000000) )\r
+\r
+#endif\r
+\r
+\r
+ /**\r
+ * @brief Clips Q63 to Q31 values.\r
+ */\r
+ __STATIC_INLINE q31_t clip_q63_to_q31(\r
+ q63_t x)\r
+ {\r
+ return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?\r
+ ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x;\r
+ }\r
+\r
+ /**\r
+ * @brief Clips Q63 to Q15 values.\r
+ */\r
+ __STATIC_INLINE q15_t clip_q63_to_q15(\r
+ q63_t x)\r
+ {\r
+ return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?\r
+ ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15);\r
+ }\r
+\r
+ /**\r
+ * @brief Clips Q31 to Q7 values.\r
+ */\r
+ __STATIC_INLINE q7_t clip_q31_to_q7(\r
+ q31_t x)\r
+ {\r
+ return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ?\r
+ ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x;\r
+ }\r
+\r
+ /**\r
+ * @brief Clips Q31 to Q15 values.\r
+ */\r
+ __STATIC_INLINE q15_t clip_q31_to_q15(\r
+ q31_t x)\r
+ {\r
+ return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ?\r
+ ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x;\r
+ }\r
+\r
+ /**\r
+ * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format.\r
+ */\r
+\r
+ __STATIC_INLINE q63_t mult32x64(\r
+ q63_t x,\r
+ q31_t y)\r
+ {\r
+ return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) +\r
+ (((q63_t) (x >> 32) * y)));\r
+ }\r
+\r
+\r
+#if defined (ARM_MATH_CM0) && defined ( __CC_ARM )\r
+#define __CLZ __clz\r
+#endif\r
+\r
+#if defined (ARM_MATH_CM0) && defined ( __TASKING__ )\r
+/* No need to redefine __CLZ */\r
+#endif\r
+\r
+#if defined (ARM_MATH_CM0) && ((defined (__ICCARM__)) ||(defined (__GNUC__)) )\r
+\r
+ __STATIC_INLINE uint32_t __CLZ(q31_t data);\r
+\r
+\r
+ __STATIC_INLINE uint32_t __CLZ(q31_t data)\r
+ {\r
+ uint32_t count = 0;\r
+ uint32_t mask = 0x80000000;\r
+\r
+ while((data & mask) == 0)\r
+ {\r
+ count += 1u;\r
+ mask = mask >> 1u;\r
+ }\r
+\r
+ return(count);\r
+\r
+ }\r
+\r
+#endif\r
+\r
+ /**\r
+ * @brief Function to Calculates 1/in(reciprocal) value of Q31 Data type.\r
+ */\r
+\r
+ __STATIC_INLINE uint32_t arm_recip_q31(\r
+ q31_t in,\r
+ q31_t * dst,\r
+ q31_t * pRecipTable)\r
+ {\r
+\r
+ uint32_t out, tempVal;\r
+ uint32_t index, i;\r
+ uint32_t signBits;\r
+\r
+ if(in > 0)\r
+ {\r
+ signBits = __CLZ(in) - 1;\r
+ }\r
+ else\r
+ {\r
+ signBits = __CLZ(-in) - 1;\r
+ }\r
+\r
+ /* Convert input sample to 1.31 format */\r
+ in = in << signBits;\r
+\r
+ /* calculation of index for initial approximated Val */\r
+ index = (uint32_t) (in >> 24u);\r
+ index = (index & INDEX_MASK);\r
+\r
+ /* 1.31 with exp 1 */\r
+ out = pRecipTable[index];\r
+\r
+ /* calculation of reciprocal value */\r
+ /* running approximation for two iterations */\r
+ for (i = 0u; i < 2u; i++)\r
+ {\r
+ tempVal = (q31_t) (((q63_t) in * out) >> 31u);\r
+ tempVal = 0x7FFFFFFF - tempVal;\r
+ /* 1.31 with exp 1 */\r
+ //out = (q31_t) (((q63_t) out * tempVal) >> 30u);\r
+ out = (q31_t) clip_q63_to_q31(((q63_t) out * tempVal) >> 30u);\r
+ }\r
+\r
+ /* write output */\r
+ *dst = out;\r
+\r
+ /* return num of signbits of out = 1/in value */\r
+ return (signBits + 1u);\r
+\r
+ }\r
+\r
+ /**\r
+ * @brief Function to Calculates 1/in(reciprocal) value of Q15 Data type.\r
+ */\r
+ __STATIC_INLINE uint32_t arm_recip_q15(\r
+ q15_t in,\r
+ q15_t * dst,\r
+ q15_t * pRecipTable)\r
+ {\r
+\r
+ uint32_t out = 0, tempVal = 0;\r
+ uint32_t index = 0, i = 0;\r
+ uint32_t signBits = 0;\r
+\r
+ if(in > 0)\r
+ {\r
+ signBits = __CLZ(in) - 17;\r
+ }\r
+ else\r
+ {\r
+ signBits = __CLZ(-in) - 17;\r
+ }\r
+\r
+ /* Convert input sample to 1.15 format */\r
+ in = in << signBits;\r
+\r
+ /* calculation of index for initial approximated Val */\r
+ index = in >> 8;\r
+ index = (index & INDEX_MASK);\r
+\r
+ /* 1.15 with exp 1 */\r
+ out = pRecipTable[index];\r
+\r
+ /* calculation of reciprocal value */\r
+ /* running approximation for two iterations */\r
+ for (i = 0; i < 2; i++)\r
+ {\r
+ tempVal = (q15_t) (((q31_t) in * out) >> 15);\r
+ tempVal = 0x7FFF - tempVal;\r
+ /* 1.15 with exp 1 */\r
+ out = (q15_t) (((q31_t) out * tempVal) >> 14);\r
+ }\r
+\r
+ /* write output */\r
+ *dst = out;\r
+\r
+ /* return num of signbits of out = 1/in value */\r
+ return (signBits + 1);\r
+\r
+ }\r
+\r
+\r
+ /*\r
+ * @brief C custom defined intrinisic function for only M0 processors\r
+ */\r
+#if defined(ARM_MATH_CM0)\r
+\r
+ __STATIC_INLINE q31_t __SSAT(\r
+ q31_t x,\r
+ uint32_t y)\r
+ {\r
+ int32_t posMax, negMin;\r
+ uint32_t i;\r
+\r
+ posMax = 1;\r
+ for (i = 0; i < (y - 1); i++)\r
+ {\r
+ posMax = posMax * 2;\r
+ }\r
+\r
+ if(x > 0)\r
+ {\r
+ posMax = (posMax - 1);\r
+\r
+ if(x > posMax)\r
+ {\r
+ x = posMax;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ negMin = -posMax;\r
+\r
+ if(x < negMin)\r
+ {\r
+ x = negMin;\r
+ }\r
+ }\r
+ return (x);\r
+\r
+\r
+ }\r
+\r
+#endif /* end of ARM_MATH_CM0 */\r
+\r
+\r
+\r
+ /*\r
+ * @brief C custom defined intrinsic function for M3 and M0 processors\r
+ */\r
+#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0)\r
+\r
+ /*\r
+ * @brief C custom defined QADD8 for M3 and M0 processors\r
+ */\r
+ __STATIC_INLINE q31_t __QADD8(\r
+ q31_t x,\r
+ q31_t y)\r
+ {\r
+\r
+ q31_t sum;\r
+ q7_t r, s, t, u;\r
+\r
+ r = (char) x;\r
+ s = (char) y;\r
+\r
+ r = __SSAT((q31_t) (r + s), 8);\r
+ s = __SSAT(((q31_t) (((x << 16) >> 24) + ((y << 16) >> 24))), 8);\r
+ t = __SSAT(((q31_t) (((x << 8) >> 24) + ((y << 8) >> 24))), 8);\r
+ u = __SSAT(((q31_t) ((x >> 24) + (y >> 24))), 8);\r
+\r
+ sum = (((q31_t) u << 24) & 0xFF000000) | (((q31_t) t << 16) & 0x00FF0000) |\r
+ (((q31_t) s << 8) & 0x0000FF00) | (r & 0x000000FF);\r
+\r
+ return sum;\r
+\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined QSUB8 for M3 and M0 processors\r
+ */\r
+ __STATIC_INLINE q31_t __QSUB8(\r
+ q31_t x,\r
+ q31_t y)\r
+ {\r
+\r
+ q31_t sum;\r
+ q31_t r, s, t, u;\r
+\r
+ r = (char) x;\r
+ s = (char) y;\r
+\r
+ r = __SSAT((r - s), 8);\r
+ s = __SSAT(((q31_t) (((x << 16) >> 24) - ((y << 16) >> 24))), 8) << 8;\r
+ t = __SSAT(((q31_t) (((x << 8) >> 24) - ((y << 8) >> 24))), 8) << 16;\r
+ u = __SSAT(((q31_t) ((x >> 24) - (y >> 24))), 8) << 24;\r
+\r
+ sum =\r
+ (u & 0xFF000000) | (t & 0x00FF0000) | (s & 0x0000FF00) | (r & 0x000000FF);\r
+\r
+ return sum;\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined QADD16 for M3 and M0 processors\r
+ */\r
+\r
+ /*\r
+ * @brief C custom defined QADD16 for M3 and M0 processors\r
+ */\r
+ __STATIC_INLINE q31_t __QADD16(\r
+ q31_t x,\r
+ q31_t y)\r
+ {\r
+\r
+ q31_t sum;\r
+ q31_t r, s;\r
+\r
+ r = (short) x;\r
+ s = (short) y;\r
+\r
+ r = __SSAT(r + s, 16);\r
+ s = __SSAT(((q31_t) ((x >> 16) + (y >> 16))), 16) << 16;\r
+\r
+ sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);\r
+\r
+ return sum;\r
+\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined SHADD16 for M3 and M0 processors\r
+ */\r
+ __STATIC_INLINE q31_t __SHADD16(\r
+ q31_t x,\r
+ q31_t y)\r
+ {\r
+\r
+ q31_t sum;\r
+ q31_t r, s;\r
+\r
+ r = (short) x;\r
+ s = (short) y;\r
+\r
+ r = ((r >> 1) + (s >> 1));\r
+ s = ((q31_t) ((x >> 17) + (y >> 17))) << 16;\r
+\r
+ sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);\r
+\r
+ return sum;\r
+\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined QSUB16 for M3 and M0 processors\r
+ */\r
+ __STATIC_INLINE q31_t __QSUB16(\r
+ q31_t x,\r
+ q31_t y)\r
+ {\r
+\r
+ q31_t sum;\r
+ q31_t r, s;\r
+\r
+ r = (short) x;\r
+ s = (short) y;\r
+\r
+ r = __SSAT(r - s, 16);\r
+ s = __SSAT(((q31_t) ((x >> 16) - (y >> 16))), 16) << 16;\r
+\r
+ sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);\r
+\r
+ return sum;\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined SHSUB16 for M3 and M0 processors\r
+ */\r
+ __STATIC_INLINE q31_t __SHSUB16(\r
+ q31_t x,\r
+ q31_t y)\r
+ {\r
+\r
+ q31_t diff;\r
+ q31_t r, s;\r
+\r
+ r = (short) x;\r
+ s = (short) y;\r
+\r
+ r = ((r >> 1) - (s >> 1));\r
+ s = (((x >> 17) - (y >> 17)) << 16);\r
+\r
+ diff = (s & 0xFFFF0000) | (r & 0x0000FFFF);\r
+\r
+ return diff;\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined QASX for M3 and M0 processors\r
+ */\r
+ __STATIC_INLINE q31_t __QASX(\r
+ q31_t x,\r
+ q31_t y)\r
+ {\r
+\r
+ q31_t sum = 0;\r
+\r
+ sum = ((sum + clip_q31_to_q15((q31_t) ((short) (x >> 16) + (short) y))) << 16) +\r
+ clip_q31_to_q15((q31_t) ((short) x - (short) (y >> 16)));\r
+\r
+ return sum;\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined SHASX for M3 and M0 processors\r
+ */\r
+ __STATIC_INLINE q31_t __SHASX(\r
+ q31_t x,\r
+ q31_t y)\r
+ {\r
+\r
+ q31_t sum;\r
+ q31_t r, s;\r
+\r
+ r = (short) x;\r
+ s = (short) y;\r
+\r
+ r = ((r >> 1) - (y >> 17));\r
+ s = (((x >> 17) + (s >> 1)) << 16);\r
+\r
+ sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);\r
+\r
+ return sum;\r
+ }\r
+\r
+\r
+ /*\r
+ * @brief C custom defined QSAX for M3 and M0 processors\r
+ */\r
+ __STATIC_INLINE q31_t __QSAX(\r
+ q31_t x,\r
+ q31_t y)\r
+ {\r
+\r
+ q31_t sum = 0;\r
+\r
+ sum = ((sum + clip_q31_to_q15((q31_t) ((short) (x >> 16) - (short) y))) << 16) +\r
+ clip_q31_to_q15((q31_t) ((short) x + (short) (y >> 16)));\r
+\r
+ return sum;\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined SHSAX for M3 and M0 processors\r
+ */\r
+ __STATIC_INLINE q31_t __SHSAX(\r
+ q31_t x,\r
+ q31_t y)\r
+ {\r
+\r
+ q31_t sum;\r
+ q31_t r, s;\r
+\r
+ r = (short) x;\r
+ s = (short) y;\r
+\r
+ r = ((r >> 1) + (y >> 17));\r
+ s = (((x >> 17) - (s >> 1)) << 16);\r
+\r
+ sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);\r
+\r
+ return sum;\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined SMUSDX for M3 and M0 processors\r
+ */\r
+ __STATIC_INLINE q31_t __SMUSDX(\r
+ q31_t x,\r
+ q31_t y)\r
+ {\r
+\r
+ return ((q31_t)(((short) x * (short) (y >> 16)) -\r
+ ((short) (x >> 16) * (short) y)));\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined SMUADX for M3 and M0 processors\r
+ */\r
+ __STATIC_INLINE q31_t __SMUADX(\r
+ q31_t x,\r
+ q31_t y)\r
+ {\r
+\r
+ return ((q31_t)(((short) x * (short) (y >> 16)) +\r
+ ((short) (x >> 16) * (short) y)));\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined QADD for M3 and M0 processors\r
+ */\r
+ __STATIC_INLINE q31_t __QADD(\r
+ q31_t x,\r
+ q31_t y)\r
+ {\r
+ return clip_q63_to_q31((q63_t) x + y);\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined QSUB for M3 and M0 processors\r
+ */\r
+ __STATIC_INLINE q31_t __QSUB(\r
+ q31_t x,\r
+ q31_t y)\r
+ {\r
+ return clip_q63_to_q31((q63_t) x - y);\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined SMLAD for M3 and M0 processors\r
+ */\r
+ __STATIC_INLINE q31_t __SMLAD(\r
+ q31_t x,\r
+ q31_t y,\r
+ q31_t sum)\r
+ {\r
+\r
+ return (sum + ((short) (x >> 16) * (short) (y >> 16)) +\r
+ ((short) x * (short) y));\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined SMLADX for M3 and M0 processors\r
+ */\r
+ __STATIC_INLINE q31_t __SMLADX(\r
+ q31_t x,\r
+ q31_t y,\r
+ q31_t sum)\r
+ {\r
+\r
+ return (sum + ((short) (x >> 16) * (short) (y)) +\r
+ ((short) x * (short) (y >> 16)));\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined SMLSDX for M3 and M0 processors\r
+ */\r
+ __STATIC_INLINE q31_t __SMLSDX(\r
+ q31_t x,\r
+ q31_t y,\r
+ q31_t sum)\r
+ {\r
+\r
+ return (sum - ((short) (x >> 16) * (short) (y)) +\r
+ ((short) x * (short) (y >> 16)));\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined SMLALD for M3 and M0 processors\r
+ */\r
+ __STATIC_INLINE q63_t __SMLALD(\r
+ q31_t x,\r
+ q31_t y,\r
+ q63_t sum)\r
+ {\r
+\r
+ return (sum + ((short) (x >> 16) * (short) (y >> 16)) +\r
+ ((short) x * (short) y));\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined SMLALDX for M3 and M0 processors\r
+ */\r
+ __STATIC_INLINE q63_t __SMLALDX(\r
+ q31_t x,\r
+ q31_t y,\r
+ q63_t sum)\r
+ {\r
+\r
+ return (sum + ((short) (x >> 16) * (short) y)) +\r
+ ((short) x * (short) (y >> 16));\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined SMUAD for M3 and M0 processors\r
+ */\r
+ __STATIC_INLINE q31_t __SMUAD(\r
+ q31_t x,\r
+ q31_t y)\r
+ {\r
+\r
+ return (((x >> 16) * (y >> 16)) +\r
+ (((x << 16) >> 16) * ((y << 16) >> 16)));\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined SMUSD for M3 and M0 processors\r
+ */\r
+ __STATIC_INLINE q31_t __SMUSD(\r
+ q31_t x,\r
+ q31_t y)\r
+ {\r
+\r
+ return (-((x >> 16) * (y >> 16)) +\r
+ (((x << 16) >> 16) * ((y << 16) >> 16)));\r
+ }\r
+\r
+\r
+\r
+\r
+#endif /* (ARM_MATH_CM3) || defined (ARM_MATH_CM0) */\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the Q7 FIR filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */\r
+ q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
+ q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r
+ } arm_fir_instance_q7;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 FIR filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */\r
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r
+ } arm_fir_instance_q15;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 FIR filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */\r
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */\r
+ } arm_fir_instance_q31;\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point FIR filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */\r
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */\r
+ } arm_fir_instance_f32;\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the Q7 FIR filter.\r
+ * @param[in] *S points to an instance of the Q7 FIR filter structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+ void arm_fir_q7(\r
+ const arm_fir_instance_q7 * S,\r
+ q7_t * pSrc,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the Q7 FIR filter.\r
+ * @param[in,out] *S points to an instance of the Q7 FIR structure.\r
+ * @param[in] numTaps Number of filter coefficients in the filter.\r
+ * @param[in] *pCoeffs points to the filter coefficients.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @param[in] blockSize number of samples that are processed.\r
+ * @return none\r
+ */\r
+ void arm_fir_init_q7(\r
+ arm_fir_instance_q7 * S,\r
+ uint16_t numTaps,\r
+ q7_t * pCoeffs,\r
+ q7_t * pState,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the Q15 FIR filter.\r
+ * @param[in] *S points to an instance of the Q15 FIR structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+ void arm_fir_q15(\r
+ const arm_fir_instance_q15 * S,\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4.\r
+ * @param[in] *S points to an instance of the Q15 FIR filter structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+ void arm_fir_fast_q15(\r
+ const arm_fir_instance_q15 * S,\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Initialization function for the Q15 FIR filter.\r
+ * @param[in,out] *S points to an instance of the Q15 FIR filter structure.\r
+ * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4.\r
+ * @param[in] *pCoeffs points to the filter coefficients.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @param[in] blockSize number of samples that are processed at a time.\r
+ * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if\r
+ * <code>numTaps</code> is not a supported value.\r
+ */\r
+\r
+ arm_status arm_fir_init_q15(\r
+ arm_fir_instance_q15 * S,\r
+ uint16_t numTaps,\r
+ q15_t * pCoeffs,\r
+ q15_t * pState,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Processing function for the Q31 FIR filter.\r
+ * @param[in] *S points to an instance of the Q31 FIR filter structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+ void arm_fir_q31(\r
+ const arm_fir_instance_q31 * S,\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4.\r
+ * @param[in] *S points to an instance of the Q31 FIR structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+ void arm_fir_fast_q31(\r
+ const arm_fir_instance_q31 * S,\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Initialization function for the Q31 FIR filter.\r
+ * @param[in,out] *S points to an instance of the Q31 FIR structure.\r
+ * @param[in] numTaps Number of filter coefficients in the filter.\r
+ * @param[in] *pCoeffs points to the filter coefficients.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @param[in] blockSize number of samples that are processed at a time.\r
+ * @return none.\r
+ */\r
+ void arm_fir_init_q31(\r
+ arm_fir_instance_q31 * S,\r
+ uint16_t numTaps,\r
+ q31_t * pCoeffs,\r
+ q31_t * pState,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Processing function for the floating-point FIR filter.\r
+ * @param[in] *S points to an instance of the floating-point FIR structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+ void arm_fir_f32(\r
+ const arm_fir_instance_f32 * S,\r
+ float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Initialization function for the floating-point FIR filter.\r
+ * @param[in,out] *S points to an instance of the floating-point FIR filter structure.\r
+ * @param[in] numTaps Number of filter coefficients in the filter.\r
+ * @param[in] *pCoeffs points to the filter coefficients.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @param[in] blockSize number of samples that are processed at a time.\r
+ * @return none.\r
+ */\r
+ void arm_fir_init_f32(\r
+ arm_fir_instance_f32 * S,\r
+ uint16_t numTaps,\r
+ float32_t * pCoeffs,\r
+ float32_t * pState,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 Biquad cascade filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */\r
+ q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */\r
+ q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */\r
+ int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */\r
+\r
+ } arm_biquad_casd_df1_inst_q15;\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 Biquad cascade filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */\r
+ q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */\r
+ q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */\r
+ uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */\r
+\r
+ } arm_biquad_casd_df1_inst_q31;\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point Biquad cascade filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */\r
+ float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */\r
+ float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */\r
+\r
+\r
+ } arm_biquad_casd_df1_inst_f32;\r
+\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the Q15 Biquad cascade filter.\r
+ * @param[in] *S points to an instance of the Q15 Biquad cascade structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_biquad_cascade_df1_q15(\r
+ const arm_biquad_casd_df1_inst_q15 * S,\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Initialization function for the Q15 Biquad cascade filter.\r
+ * @param[in,out] *S points to an instance of the Q15 Biquad cascade structure.\r
+ * @param[in] numStages number of 2nd order stages in the filter.\r
+ * @param[in] *pCoeffs points to the filter coefficients.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format\r
+ * @return none\r
+ */\r
+\r
+ void arm_biquad_cascade_df1_init_q15(\r
+ arm_biquad_casd_df1_inst_q15 * S,\r
+ uint8_t numStages,\r
+ q15_t * pCoeffs,\r
+ q15_t * pState,\r
+ int8_t postShift);\r
+\r
+\r
+ /**\r
+ * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4.\r
+ * @param[in] *S points to an instance of the Q15 Biquad cascade structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_biquad_cascade_df1_fast_q15(\r
+ const arm_biquad_casd_df1_inst_q15 * S,\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the Q31 Biquad cascade filter\r
+ * @param[in] *S points to an instance of the Q31 Biquad cascade structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_biquad_cascade_df1_q31(\r
+ const arm_biquad_casd_df1_inst_q31 * S,\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4.\r
+ * @param[in] *S points to an instance of the Q31 Biquad cascade structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_biquad_cascade_df1_fast_q31(\r
+ const arm_biquad_casd_df1_inst_q31 * S,\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Initialization function for the Q31 Biquad cascade filter.\r
+ * @param[in,out] *S points to an instance of the Q31 Biquad cascade structure.\r
+ * @param[in] numStages number of 2nd order stages in the filter.\r
+ * @param[in] *pCoeffs points to the filter coefficients.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format\r
+ * @return none\r
+ */\r
+\r
+ void arm_biquad_cascade_df1_init_q31(\r
+ arm_biquad_casd_df1_inst_q31 * S,\r
+ uint8_t numStages,\r
+ q31_t * pCoeffs,\r
+ q31_t * pState,\r
+ int8_t postShift);\r
+\r
+ /**\r
+ * @brief Processing function for the floating-point Biquad cascade filter.\r
+ * @param[in] *S points to an instance of the floating-point Biquad cascade structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_biquad_cascade_df1_f32(\r
+ const arm_biquad_casd_df1_inst_f32 * S,\r
+ float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Initialization function for the floating-point Biquad cascade filter.\r
+ * @param[in,out] *S points to an instance of the floating-point Biquad cascade structure.\r
+ * @param[in] numStages number of 2nd order stages in the filter.\r
+ * @param[in] *pCoeffs points to the filter coefficients.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @return none\r
+ */\r
+\r
+ void arm_biquad_cascade_df1_init_f32(\r
+ arm_biquad_casd_df1_inst_f32 * S,\r
+ uint8_t numStages,\r
+ float32_t * pCoeffs,\r
+ float32_t * pState);\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point matrix structure.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t numRows; /**< number of rows of the matrix. */\r
+ uint16_t numCols; /**< number of columns of the matrix. */\r
+ float32_t *pData; /**< points to the data of the matrix. */\r
+ } arm_matrix_instance_f32;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 matrix structure.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t numRows; /**< number of rows of the matrix. */\r
+ uint16_t numCols; /**< number of columns of the matrix. */\r
+ q15_t *pData; /**< points to the data of the matrix. */\r
+\r
+ } arm_matrix_instance_q15;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 matrix structure.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t numRows; /**< number of rows of the matrix. */\r
+ uint16_t numCols; /**< number of columns of the matrix. */\r
+ q31_t *pData; /**< points to the data of the matrix. */\r
+\r
+ } arm_matrix_instance_q31;\r
+\r
+\r
+\r
+ /**\r
+ * @brief Floating-point matrix addition.\r
+ * @param[in] *pSrcA points to the first input matrix structure\r
+ * @param[in] *pSrcB points to the second input matrix structure\r
+ * @param[out] *pDst points to output matrix structure\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+\r
+ arm_status arm_mat_add_f32(\r
+ const arm_matrix_instance_f32 * pSrcA,\r
+ const arm_matrix_instance_f32 * pSrcB,\r
+ arm_matrix_instance_f32 * pDst);\r
+\r
+ /**\r
+ * @brief Q15 matrix addition.\r
+ * @param[in] *pSrcA points to the first input matrix structure\r
+ * @param[in] *pSrcB points to the second input matrix structure\r
+ * @param[out] *pDst points to output matrix structure\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+\r
+ arm_status arm_mat_add_q15(\r
+ const arm_matrix_instance_q15 * pSrcA,\r
+ const arm_matrix_instance_q15 * pSrcB,\r
+ arm_matrix_instance_q15 * pDst);\r
+\r
+ /**\r
+ * @brief Q31 matrix addition.\r
+ * @param[in] *pSrcA points to the first input matrix structure\r
+ * @param[in] *pSrcB points to the second input matrix structure\r
+ * @param[out] *pDst points to output matrix structure\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+\r
+ arm_status arm_mat_add_q31(\r
+ const arm_matrix_instance_q31 * pSrcA,\r
+ const arm_matrix_instance_q31 * pSrcB,\r
+ arm_matrix_instance_q31 * pDst);\r
+\r
+\r
+ /**\r
+ * @brief Floating-point matrix transpose.\r
+ * @param[in] *pSrc points to the input matrix\r
+ * @param[out] *pDst points to the output matrix\r
+ * @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>\r
+ * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+\r
+ arm_status arm_mat_trans_f32(\r
+ const arm_matrix_instance_f32 * pSrc,\r
+ arm_matrix_instance_f32 * pDst);\r
+\r
+\r
+ /**\r
+ * @brief Q15 matrix transpose.\r
+ * @param[in] *pSrc points to the input matrix\r
+ * @param[out] *pDst points to the output matrix\r
+ * @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>\r
+ * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+\r
+ arm_status arm_mat_trans_q15(\r
+ const arm_matrix_instance_q15 * pSrc,\r
+ arm_matrix_instance_q15 * pDst);\r
+\r
+ /**\r
+ * @brief Q31 matrix transpose.\r
+ * @param[in] *pSrc points to the input matrix\r
+ * @param[out] *pDst points to the output matrix\r
+ * @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>\r
+ * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+\r
+ arm_status arm_mat_trans_q31(\r
+ const arm_matrix_instance_q31 * pSrc,\r
+ arm_matrix_instance_q31 * pDst);\r
+\r
+\r
+ /**\r
+ * @brief Floating-point matrix multiplication\r
+ * @param[in] *pSrcA points to the first input matrix structure\r
+ * @param[in] *pSrcB points to the second input matrix structure\r
+ * @param[out] *pDst points to output matrix structure\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+\r
+ arm_status arm_mat_mult_f32(\r
+ const arm_matrix_instance_f32 * pSrcA,\r
+ const arm_matrix_instance_f32 * pSrcB,\r
+ arm_matrix_instance_f32 * pDst);\r
+\r
+ /**\r
+ * @brief Q15 matrix multiplication\r
+ * @param[in] *pSrcA points to the first input matrix structure\r
+ * @param[in] *pSrcB points to the second input matrix structure\r
+ * @param[out] *pDst points to output matrix structure\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+\r
+ arm_status arm_mat_mult_q15(\r
+ const arm_matrix_instance_q15 * pSrcA,\r
+ const arm_matrix_instance_q15 * pSrcB,\r
+ arm_matrix_instance_q15 * pDst,\r
+ q15_t * pState);\r
+\r
+ /**\r
+ * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4\r
+ * @param[in] *pSrcA points to the first input matrix structure\r
+ * @param[in] *pSrcB points to the second input matrix structure\r
+ * @param[out] *pDst points to output matrix structure\r
+ * @param[in] *pState points to the array for storing intermediate results\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+\r
+ arm_status arm_mat_mult_fast_q15(\r
+ const arm_matrix_instance_q15 * pSrcA,\r
+ const arm_matrix_instance_q15 * pSrcB,\r
+ arm_matrix_instance_q15 * pDst,\r
+ q15_t * pState);\r
+\r
+ /**\r
+ * @brief Q31 matrix multiplication\r
+ * @param[in] *pSrcA points to the first input matrix structure\r
+ * @param[in] *pSrcB points to the second input matrix structure\r
+ * @param[out] *pDst points to output matrix structure\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+\r
+ arm_status arm_mat_mult_q31(\r
+ const arm_matrix_instance_q31 * pSrcA,\r
+ const arm_matrix_instance_q31 * pSrcB,\r
+ arm_matrix_instance_q31 * pDst);\r
+\r
+ /**\r
+ * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4\r
+ * @param[in] *pSrcA points to the first input matrix structure\r
+ * @param[in] *pSrcB points to the second input matrix structure\r
+ * @param[out] *pDst points to output matrix structure\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+\r
+ arm_status arm_mat_mult_fast_q31(\r
+ const arm_matrix_instance_q31 * pSrcA,\r
+ const arm_matrix_instance_q31 * pSrcB,\r
+ arm_matrix_instance_q31 * pDst);\r
+\r
+\r
+ /**\r
+ * @brief Floating-point matrix subtraction\r
+ * @param[in] *pSrcA points to the first input matrix structure\r
+ * @param[in] *pSrcB points to the second input matrix structure\r
+ * @param[out] *pDst points to output matrix structure\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+\r
+ arm_status arm_mat_sub_f32(\r
+ const arm_matrix_instance_f32 * pSrcA,\r
+ const arm_matrix_instance_f32 * pSrcB,\r
+ arm_matrix_instance_f32 * pDst);\r
+\r
+ /**\r
+ * @brief Q15 matrix subtraction\r
+ * @param[in] *pSrcA points to the first input matrix structure\r
+ * @param[in] *pSrcB points to the second input matrix structure\r
+ * @param[out] *pDst points to output matrix structure\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+\r
+ arm_status arm_mat_sub_q15(\r
+ const arm_matrix_instance_q15 * pSrcA,\r
+ const arm_matrix_instance_q15 * pSrcB,\r
+ arm_matrix_instance_q15 * pDst);\r
+\r
+ /**\r
+ * @brief Q31 matrix subtraction\r
+ * @param[in] *pSrcA points to the first input matrix structure\r
+ * @param[in] *pSrcB points to the second input matrix structure\r
+ * @param[out] *pDst points to output matrix structure\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+\r
+ arm_status arm_mat_sub_q31(\r
+ const arm_matrix_instance_q31 * pSrcA,\r
+ const arm_matrix_instance_q31 * pSrcB,\r
+ arm_matrix_instance_q31 * pDst);\r
+\r
+ /**\r
+ * @brief Floating-point matrix scaling.\r
+ * @param[in] *pSrc points to the input matrix\r
+ * @param[in] scale scale factor\r
+ * @param[out] *pDst points to the output matrix\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+\r
+ arm_status arm_mat_scale_f32(\r
+ const arm_matrix_instance_f32 * pSrc,\r
+ float32_t scale,\r
+ arm_matrix_instance_f32 * pDst);\r
+\r
+ /**\r
+ * @brief Q15 matrix scaling.\r
+ * @param[in] *pSrc points to input matrix\r
+ * @param[in] scaleFract fractional portion of the scale factor\r
+ * @param[in] shift number of bits to shift the result by\r
+ * @param[out] *pDst points to output matrix\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+\r
+ arm_status arm_mat_scale_q15(\r
+ const arm_matrix_instance_q15 * pSrc,\r
+ q15_t scaleFract,\r
+ int32_t shift,\r
+ arm_matrix_instance_q15 * pDst);\r
+\r
+ /**\r
+ * @brief Q31 matrix scaling.\r
+ * @param[in] *pSrc points to input matrix\r
+ * @param[in] scaleFract fractional portion of the scale factor\r
+ * @param[in] shift number of bits to shift the result by\r
+ * @param[out] *pDst points to output matrix structure\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+\r
+ arm_status arm_mat_scale_q31(\r
+ const arm_matrix_instance_q31 * pSrc,\r
+ q31_t scaleFract,\r
+ int32_t shift,\r
+ arm_matrix_instance_q31 * pDst);\r
+\r
+\r
+ /**\r
+ * @brief Q31 matrix initialization.\r
+ * @param[in,out] *S points to an instance of the floating-point matrix structure.\r
+ * @param[in] nRows number of rows in the matrix.\r
+ * @param[in] nColumns number of columns in the matrix.\r
+ * @param[in] *pData points to the matrix data array.\r
+ * @return none\r
+ */\r
+\r
+ void arm_mat_init_q31(\r
+ arm_matrix_instance_q31 * S,\r
+ uint16_t nRows,\r
+ uint16_t nColumns,\r
+ q31_t *pData);\r
+\r
+ /**\r
+ * @brief Q15 matrix initialization.\r
+ * @param[in,out] *S points to an instance of the floating-point matrix structure.\r
+ * @param[in] nRows number of rows in the matrix.\r
+ * @param[in] nColumns number of columns in the matrix.\r
+ * @param[in] *pData points to the matrix data array.\r
+ * @return none\r
+ */\r
+\r
+ void arm_mat_init_q15(\r
+ arm_matrix_instance_q15 * S,\r
+ uint16_t nRows,\r
+ uint16_t nColumns,\r
+ q15_t *pData);\r
+\r
+ /**\r
+ * @brief Floating-point matrix initialization.\r
+ * @param[in,out] *S points to an instance of the floating-point matrix structure.\r
+ * @param[in] nRows number of rows in the matrix.\r
+ * @param[in] nColumns number of columns in the matrix.\r
+ * @param[in] *pData points to the matrix data array.\r
+ * @return none\r
+ */\r
+\r
+ void arm_mat_init_f32(\r
+ arm_matrix_instance_f32 * S,\r
+ uint16_t nRows,\r
+ uint16_t nColumns,\r
+ float32_t *pData);\r
+\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 PID Control.\r
+ */\r
+ typedef struct\r
+ {\r
+ q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */\r
+ #ifdef ARM_MATH_CM0\r
+ q15_t A1;\r
+ q15_t A2;\r
+ #else\r
+ q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/\r
+ #endif\r
+ q15_t state[3]; /**< The state array of length 3. */\r
+ q15_t Kp; /**< The proportional gain. */\r
+ q15_t Ki; /**< The integral gain. */\r
+ q15_t Kd; /**< The derivative gain. */\r
+ } arm_pid_instance_q15;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 PID Control.\r
+ */\r
+ typedef struct\r
+ {\r
+ q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */\r
+ q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */\r
+ q31_t A2; /**< The derived gain, A2 = Kd . */\r
+ q31_t state[3]; /**< The state array of length 3. */\r
+ q31_t Kp; /**< The proportional gain. */\r
+ q31_t Ki; /**< The integral gain. */\r
+ q31_t Kd; /**< The derivative gain. */\r
+\r
+ } arm_pid_instance_q31;\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point PID Control.\r
+ */\r
+ typedef struct\r
+ {\r
+ float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */\r
+ float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */\r
+ float32_t A2; /**< The derived gain, A2 = Kd . */\r
+ float32_t state[3]; /**< The state array of length 3. */\r
+ float32_t Kp; /**< The proportional gain. */\r
+ float32_t Ki; /**< The integral gain. */\r
+ float32_t Kd; /**< The derivative gain. */\r
+ } arm_pid_instance_f32;\r
+\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the floating-point PID Control.\r
+ * @param[in,out] *S points to an instance of the PID structure.\r
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.\r
+ * @return none.\r
+ */\r
+ void arm_pid_init_f32(\r
+ arm_pid_instance_f32 * S,\r
+ int32_t resetStateFlag);\r
+\r
+ /**\r
+ * @brief Reset function for the floating-point PID Control.\r
+ * @param[in,out] *S is an instance of the floating-point PID Control structure\r
+ * @return none\r
+ */\r
+ void arm_pid_reset_f32(\r
+ arm_pid_instance_f32 * S);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the Q31 PID Control.\r
+ * @param[in,out] *S points to an instance of the Q15 PID structure.\r
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.\r
+ * @return none.\r
+ */\r
+ void arm_pid_init_q31(\r
+ arm_pid_instance_q31 * S,\r
+ int32_t resetStateFlag);\r
+\r
+\r
+ /**\r
+ * @brief Reset function for the Q31 PID Control.\r
+ * @param[in,out] *S points to an instance of the Q31 PID Control structure\r
+ * @return none\r
+ */\r
+\r
+ void arm_pid_reset_q31(\r
+ arm_pid_instance_q31 * S);\r
+\r
+ /**\r
+ * @brief Initialization function for the Q15 PID Control.\r
+ * @param[in,out] *S points to an instance of the Q15 PID structure.\r
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.\r
+ * @return none.\r
+ */\r
+ void arm_pid_init_q15(\r
+ arm_pid_instance_q15 * S,\r
+ int32_t resetStateFlag);\r
+\r
+ /**\r
+ * @brief Reset function for the Q15 PID Control.\r
+ * @param[in,out] *S points to an instance of the q15 PID Control structure\r
+ * @return none\r
+ */\r
+ void arm_pid_reset_q15(\r
+ arm_pid_instance_q15 * S);\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point Linear Interpolate function.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint32_t nValues; /**< nValues */\r
+ float32_t x1; /**< x1 */\r
+ float32_t xSpacing; /**< xSpacing */\r
+ float32_t *pYData; /**< pointer to the table of Y values */\r
+ } arm_linear_interp_instance_f32;\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point bilinear interpolation function.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t numRows; /**< number of rows in the data table. */\r
+ uint16_t numCols; /**< number of columns in the data table. */\r
+ float32_t *pData; /**< points to the data table. */\r
+ } arm_bilinear_interp_instance_f32;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 bilinear interpolation function.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t numRows; /**< number of rows in the data table. */\r
+ uint16_t numCols; /**< number of columns in the data table. */\r
+ q31_t *pData; /**< points to the data table. */\r
+ } arm_bilinear_interp_instance_q31;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 bilinear interpolation function.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t numRows; /**< number of rows in the data table. */\r
+ uint16_t numCols; /**< number of columns in the data table. */\r
+ q15_t *pData; /**< points to the data table. */\r
+ } arm_bilinear_interp_instance_q15;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 bilinear interpolation function.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t numRows; /**< number of rows in the data table. */\r
+ uint16_t numCols; /**< number of columns in the data table. */\r
+ q7_t *pData; /**< points to the data table. */\r
+ } arm_bilinear_interp_instance_q7;\r
+\r
+\r
+ /**\r
+ * @brief Q7 vector multiplication.\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_mult_q7(\r
+ q7_t * pSrcA,\r
+ q7_t * pSrcB,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Q15 vector multiplication.\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_mult_q15(\r
+ q15_t * pSrcA,\r
+ q15_t * pSrcB,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Q31 vector multiplication.\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_mult_q31(\r
+ q31_t * pSrcA,\r
+ q31_t * pSrcB,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Floating-point vector multiplication.\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_mult_f32(\r
+ float32_t * pSrcA,\r
+ float32_t * pSrcB,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 CFFT/CIFFT function.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t fftLen; /**< length of the FFT. */\r
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */\r
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */\r
+ q15_t *pTwiddle; /**< points to the twiddle factor table. */\r
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */\r
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */\r
+ } arm_cfft_radix4_instance_q15;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 CFFT/CIFFT function.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t fftLen; /**< length of the FFT. */\r
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */\r
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */\r
+ q31_t *pTwiddle; /**< points to the twiddle factor table. */\r
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */\r
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */\r
+ } arm_cfft_radix4_instance_q31;\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point CFFT/CIFFT function.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t fftLen; /**< length of the FFT. */\r
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */\r
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */\r
+ float32_t *pTwiddle; /**< points to the twiddle factor table. */\r
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */\r
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */\r
+ float32_t onebyfftLen; /**< value of 1/fftLen. */\r
+ } arm_cfft_radix4_instance_f32;\r
+\r
+ /**\r
+ * @brief Processing function for the Q15 CFFT/CIFFT.\r
+ * @param[in] *S points to an instance of the Q15 CFFT/CIFFT structure.\r
+ * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cfft_radix4_q15(\r
+ const arm_cfft_radix4_instance_q15 * S,\r
+ q15_t * pSrc);\r
+\r
+ /**\r
+ * @brief Initialization function for the Q15 CFFT/CIFFT.\r
+ * @param[in,out] *S points to an instance of the Q15 CFFT/CIFFT structure.\r
+ * @param[in] fftLen length of the FFT.\r
+ * @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.\r
+ * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.\r
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLen</code> is not a supported value.\r
+ */\r
+\r
+ arm_status arm_cfft_radix4_init_q15(\r
+ arm_cfft_radix4_instance_q15 * S,\r
+ uint16_t fftLen,\r
+ uint8_t ifftFlag,\r
+ uint8_t bitReverseFlag);\r
+\r
+ /**\r
+ * @brief Processing function for the Q31 CFFT/CIFFT.\r
+ * @param[in] *S points to an instance of the Q31 CFFT/CIFFT structure.\r
+ * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cfft_radix4_q31(\r
+ const arm_cfft_radix4_instance_q31 * S,\r
+ q31_t * pSrc);\r
+\r
+ /**\r
+ * @brief Initialization function for the Q31 CFFT/CIFFT.\r
+ * @param[in,out] *S points to an instance of the Q31 CFFT/CIFFT structure.\r
+ * @param[in] fftLen length of the FFT.\r
+ * @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.\r
+ * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.\r
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLen</code> is not a supported value.\r
+ */\r
+\r
+ arm_status arm_cfft_radix4_init_q31(\r
+ arm_cfft_radix4_instance_q31 * S,\r
+ uint16_t fftLen,\r
+ uint8_t ifftFlag,\r
+ uint8_t bitReverseFlag);\r
+\r
+ /**\r
+ * @brief Processing function for the floating-point CFFT/CIFFT.\r
+ * @param[in] *S points to an instance of the floating-point CFFT/CIFFT structure.\r
+ * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cfft_radix4_f32(\r
+ const arm_cfft_radix4_instance_f32 * S,\r
+ float32_t * pSrc);\r
+\r
+ /**\r
+ * @brief Initialization function for the floating-point CFFT/CIFFT.\r
+ * @param[in,out] *S points to an instance of the floating-point CFFT/CIFFT structure.\r
+ * @param[in] fftLen length of the FFT.\r
+ * @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.\r
+ * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.\r
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLen</code> is not a supported value.\r
+ */\r
+\r
+ arm_status arm_cfft_radix4_init_f32(\r
+ arm_cfft_radix4_instance_f32 * S,\r
+ uint16_t fftLen,\r
+ uint8_t ifftFlag,\r
+ uint8_t bitReverseFlag);\r
+\r
+\r
+\r
+ /*----------------------------------------------------------------------\r
+ * Internal functions prototypes FFT function\r
+ ----------------------------------------------------------------------*/\r
+\r
+ /**\r
+ * @brief Core function for the floating-point CFFT butterfly process.\r
+ * @param[in, out] *pSrc points to the in-place buffer of floating-point data type.\r
+ * @param[in] fftLen length of the FFT.\r
+ * @param[in] *pCoef points to the twiddle coefficient buffer.\r
+ * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_radix4_butterfly_f32(\r
+ float32_t * pSrc,\r
+ uint16_t fftLen,\r
+ float32_t * pCoef,\r
+ uint16_t twidCoefModifier);\r
+\r
+ /**\r
+ * @brief Core function for the floating-point CIFFT butterfly process.\r
+ * @param[in, out] *pSrc points to the in-place buffer of floating-point data type.\r
+ * @param[in] fftLen length of the FFT.\r
+ * @param[in] *pCoef points to twiddle coefficient buffer.\r
+ * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.\r
+ * @param[in] onebyfftLen value of 1/fftLen.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_radix4_butterfly_inverse_f32(\r
+ float32_t * pSrc,\r
+ uint16_t fftLen,\r
+ float32_t * pCoef,\r
+ uint16_t twidCoefModifier,\r
+ float32_t onebyfftLen);\r
+\r
+ /**\r
+ * @brief In-place bit reversal function.\r
+ * @param[in, out] *pSrc points to the in-place buffer of floating-point data type.\r
+ * @param[in] fftSize length of the FFT.\r
+ * @param[in] bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table.\r
+ * @param[in] *pBitRevTab points to the bit reversal table.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_bitreversal_f32(\r
+ float32_t *pSrc,\r
+ uint16_t fftSize,\r
+ uint16_t bitRevFactor,\r
+ uint16_t *pBitRevTab);\r
+\r
+ /**\r
+ * @brief Core function for the Q31 CFFT butterfly process.\r
+ * @param[in, out] *pSrc points to the in-place buffer of Q31 data type.\r
+ * @param[in] fftLen length of the FFT.\r
+ * @param[in] *pCoef points to twiddle coefficient buffer.\r
+ * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_radix4_butterfly_q31(\r
+ q31_t *pSrc,\r
+ uint32_t fftLen,\r
+ q31_t *pCoef,\r
+ uint32_t twidCoefModifier);\r
+\r
+ /**\r
+ * @brief Core function for the Q31 CIFFT butterfly process.\r
+ * @param[in, out] *pSrc points to the in-place buffer of Q31 data type.\r
+ * @param[in] fftLen length of the FFT.\r
+ * @param[in] *pCoef points to twiddle coefficient buffer.\r
+ * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_radix4_butterfly_inverse_q31(\r
+ q31_t * pSrc,\r
+ uint32_t fftLen,\r
+ q31_t * pCoef,\r
+ uint32_t twidCoefModifier);\r
+\r
+ /**\r
+ * @brief In-place bit reversal function.\r
+ * @param[in, out] *pSrc points to the in-place buffer of Q31 data type.\r
+ * @param[in] fftLen length of the FFT.\r
+ * @param[in] bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table\r
+ * @param[in] *pBitRevTab points to bit reversal table.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_bitreversal_q31(\r
+ q31_t * pSrc,\r
+ uint32_t fftLen,\r
+ uint16_t bitRevFactor,\r
+ uint16_t *pBitRevTab);\r
+\r
+ /**\r
+ * @brief Core function for the Q15 CFFT butterfly process.\r
+ * @param[in, out] *pSrc16 points to the in-place buffer of Q15 data type.\r
+ * @param[in] fftLen length of the FFT.\r
+ * @param[in] *pCoef16 points to twiddle coefficient buffer.\r
+ * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_radix4_butterfly_q15(\r
+ q15_t *pSrc16,\r
+ uint32_t fftLen,\r
+ q15_t *pCoef16,\r
+ uint32_t twidCoefModifier);\r
+\r
+ /**\r
+ * @brief Core function for the Q15 CIFFT butterfly process.\r
+ * @param[in, out] *pSrc16 points to the in-place buffer of Q15 data type.\r
+ * @param[in] fftLen length of the FFT.\r
+ * @param[in] *pCoef16 points to twiddle coefficient buffer.\r
+ * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_radix4_butterfly_inverse_q15(\r
+ q15_t *pSrc16,\r
+ uint32_t fftLen,\r
+ q15_t *pCoef16,\r
+ uint32_t twidCoefModifier);\r
+\r
+ /**\r
+ * @brief In-place bit reversal function.\r
+ * @param[in, out] *pSrc points to the in-place buffer of Q15 data type.\r
+ * @param[in] fftLen length of the FFT.\r
+ * @param[in] bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table\r
+ * @param[in] *pBitRevTab points to bit reversal table.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_bitreversal_q15(\r
+ q15_t * pSrc,\r
+ uint32_t fftLen,\r
+ uint16_t bitRevFactor,\r
+ uint16_t *pBitRevTab);\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 RFFT/RIFFT function.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint32_t fftLenReal; /**< length of the real FFT. */\r
+ uint32_t fftLenBy2; /**< length of the complex FFT. */\r
+ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */\r
+ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */\r
+ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r
+ q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */\r
+ q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */\r
+ arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */\r
+ } arm_rfft_instance_q15;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 RFFT/RIFFT function.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint32_t fftLenReal; /**< length of the real FFT. */\r
+ uint32_t fftLenBy2; /**< length of the complex FFT. */\r
+ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */\r
+ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */\r
+ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r
+ q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */\r
+ q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */\r
+ arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */\r
+ } arm_rfft_instance_q31;\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point RFFT/RIFFT function.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint32_t fftLenReal; /**< length of the real FFT. */\r
+ uint16_t fftLenBy2; /**< length of the complex FFT. */\r
+ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */\r
+ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */\r
+ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r
+ float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */\r
+ float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */\r
+ arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */\r
+ } arm_rfft_instance_f32;\r
+\r
+ /**\r
+ * @brief Processing function for the Q15 RFFT/RIFFT.\r
+ * @param[in] *S points to an instance of the Q15 RFFT/RIFFT structure.\r
+ * @param[in] *pSrc points to the input buffer.\r
+ * @param[out] *pDst points to the output buffer.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_rfft_q15(\r
+ const arm_rfft_instance_q15 * S,\r
+ q15_t * pSrc,\r
+ q15_t * pDst);\r
+\r
+ /**\r
+ * @brief Initialization function for the Q15 RFFT/RIFFT.\r
+ * @param[in, out] *S points to an instance of the Q15 RFFT/RIFFT structure.\r
+ * @param[in] *S_CFFT points to an instance of the Q15 CFFT/CIFFT structure.\r
+ * @param[in] fftLenReal length of the FFT.\r
+ * @param[in] ifftFlagR flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform.\r
+ * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.\r
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported value.\r
+ */\r
+\r
+ arm_status arm_rfft_init_q15(\r
+ arm_rfft_instance_q15 * S,\r
+ arm_cfft_radix4_instance_q15 * S_CFFT,\r
+ uint32_t fftLenReal,\r
+ uint32_t ifftFlagR,\r
+ uint32_t bitReverseFlag);\r
+\r
+ /**\r
+ * @brief Processing function for the Q31 RFFT/RIFFT.\r
+ * @param[in] *S points to an instance of the Q31 RFFT/RIFFT structure.\r
+ * @param[in] *pSrc points to the input buffer.\r
+ * @param[out] *pDst points to the output buffer.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_rfft_q31(\r
+ const arm_rfft_instance_q31 * S,\r
+ q31_t * pSrc,\r
+ q31_t * pDst);\r
+\r
+ /**\r
+ * @brief Initialization function for the Q31 RFFT/RIFFT.\r
+ * @param[in, out] *S points to an instance of the Q31 RFFT/RIFFT structure.\r
+ * @param[in, out] *S_CFFT points to an instance of the Q31 CFFT/CIFFT structure.\r
+ * @param[in] fftLenReal length of the FFT.\r
+ * @param[in] ifftFlagR flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform.\r
+ * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.\r
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported value.\r
+ */\r
+\r
+ arm_status arm_rfft_init_q31(\r
+ arm_rfft_instance_q31 * S,\r
+ arm_cfft_radix4_instance_q31 * S_CFFT,\r
+ uint32_t fftLenReal,\r
+ uint32_t ifftFlagR,\r
+ uint32_t bitReverseFlag);\r
+\r
+ /**\r
+ * @brief Initialization function for the floating-point RFFT/RIFFT.\r
+ * @param[in,out] *S points to an instance of the floating-point RFFT/RIFFT structure.\r
+ * @param[in,out] *S_CFFT points to an instance of the floating-point CFFT/CIFFT structure.\r
+ * @param[in] fftLenReal length of the FFT.\r
+ * @param[in] ifftFlagR flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform.\r
+ * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.\r
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported value.\r
+ */\r
+\r
+ arm_status arm_rfft_init_f32(\r
+ arm_rfft_instance_f32 * S,\r
+ arm_cfft_radix4_instance_f32 * S_CFFT,\r
+ uint32_t fftLenReal,\r
+ uint32_t ifftFlagR,\r
+ uint32_t bitReverseFlag);\r
+\r
+ /**\r
+ * @brief Processing function for the floating-point RFFT/RIFFT.\r
+ * @param[in] *S points to an instance of the floating-point RFFT/RIFFT structure.\r
+ * @param[in] *pSrc points to the input buffer.\r
+ * @param[out] *pDst points to the output buffer.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_rfft_f32(\r
+ const arm_rfft_instance_f32 * S,\r
+ float32_t * pSrc,\r
+ float32_t * pDst);\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point DCT4/IDCT4 function.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t N; /**< length of the DCT4. */\r
+ uint16_t Nby2; /**< half of the length of the DCT4. */\r
+ float32_t normalize; /**< normalizing factor. */\r
+ float32_t *pTwiddle; /**< points to the twiddle factor table. */\r
+ float32_t *pCosFactor; /**< points to the cosFactor table. */\r
+ arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */\r
+ arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */\r
+ } arm_dct4_instance_f32;\r
+\r
+ /**\r
+ * @brief Initialization function for the floating-point DCT4/IDCT4.\r
+ * @param[in,out] *S points to an instance of floating-point DCT4/IDCT4 structure.\r
+ * @param[in] *S_RFFT points to an instance of floating-point RFFT/RIFFT structure.\r
+ * @param[in] *S_CFFT points to an instance of floating-point CFFT/CIFFT structure.\r
+ * @param[in] N length of the DCT4.\r
+ * @param[in] Nby2 half of the length of the DCT4.\r
+ * @param[in] normalize normalizing factor.\r
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported transform length.\r
+ */\r
+\r
+ arm_status arm_dct4_init_f32(\r
+ arm_dct4_instance_f32 * S,\r
+ arm_rfft_instance_f32 * S_RFFT,\r
+ arm_cfft_radix4_instance_f32 * S_CFFT,\r
+ uint16_t N,\r
+ uint16_t Nby2,\r
+ float32_t normalize);\r
+\r
+ /**\r
+ * @brief Processing function for the floating-point DCT4/IDCT4.\r
+ * @param[in] *S points to an instance of the floating-point DCT4/IDCT4 structure.\r
+ * @param[in] *pState points to state buffer.\r
+ * @param[in,out] *pInlineBuffer points to the in-place input and output buffer.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_dct4_f32(\r
+ const arm_dct4_instance_f32 * S,\r
+ float32_t * pState,\r
+ float32_t * pInlineBuffer);\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 DCT4/IDCT4 function.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t N; /**< length of the DCT4. */\r
+ uint16_t Nby2; /**< half of the length of the DCT4. */\r
+ q31_t normalize; /**< normalizing factor. */\r
+ q31_t *pTwiddle; /**< points to the twiddle factor table. */\r
+ q31_t *pCosFactor; /**< points to the cosFactor table. */\r
+ arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */\r
+ arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */\r
+ } arm_dct4_instance_q31;\r
+\r
+ /**\r
+ * @brief Initialization function for the Q31 DCT4/IDCT4.\r
+ * @param[in,out] *S points to an instance of Q31 DCT4/IDCT4 structure.\r
+ * @param[in] *S_RFFT points to an instance of Q31 RFFT/RIFFT structure\r
+ * @param[in] *S_CFFT points to an instance of Q31 CFFT/CIFFT structure\r
+ * @param[in] N length of the DCT4.\r
+ * @param[in] Nby2 half of the length of the DCT4.\r
+ * @param[in] normalize normalizing factor.\r
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.\r
+ */\r
+\r
+ arm_status arm_dct4_init_q31(\r
+ arm_dct4_instance_q31 * S,\r
+ arm_rfft_instance_q31 * S_RFFT,\r
+ arm_cfft_radix4_instance_q31 * S_CFFT,\r
+ uint16_t N,\r
+ uint16_t Nby2,\r
+ q31_t normalize);\r
+\r
+ /**\r
+ * @brief Processing function for the Q31 DCT4/IDCT4.\r
+ * @param[in] *S points to an instance of the Q31 DCT4 structure.\r
+ * @param[in] *pState points to state buffer.\r
+ * @param[in,out] *pInlineBuffer points to the in-place input and output buffer.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_dct4_q31(\r
+ const arm_dct4_instance_q31 * S,\r
+ q31_t * pState,\r
+ q31_t * pInlineBuffer);\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 DCT4/IDCT4 function.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t N; /**< length of the DCT4. */\r
+ uint16_t Nby2; /**< half of the length of the DCT4. */\r
+ q15_t normalize; /**< normalizing factor. */\r
+ q15_t *pTwiddle; /**< points to the twiddle factor table. */\r
+ q15_t *pCosFactor; /**< points to the cosFactor table. */\r
+ arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */\r
+ arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */\r
+ } arm_dct4_instance_q15;\r
+\r
+ /**\r
+ * @brief Initialization function for the Q15 DCT4/IDCT4.\r
+ * @param[in,out] *S points to an instance of Q15 DCT4/IDCT4 structure.\r
+ * @param[in] *S_RFFT points to an instance of Q15 RFFT/RIFFT structure.\r
+ * @param[in] *S_CFFT points to an instance of Q15 CFFT/CIFFT structure.\r
+ * @param[in] N length of the DCT4.\r
+ * @param[in] Nby2 half of the length of the DCT4.\r
+ * @param[in] normalize normalizing factor.\r
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.\r
+ */\r
+\r
+ arm_status arm_dct4_init_q15(\r
+ arm_dct4_instance_q15 * S,\r
+ arm_rfft_instance_q15 * S_RFFT,\r
+ arm_cfft_radix4_instance_q15 * S_CFFT,\r
+ uint16_t N,\r
+ uint16_t Nby2,\r
+ q15_t normalize);\r
+\r
+ /**\r
+ * @brief Processing function for the Q15 DCT4/IDCT4.\r
+ * @param[in] *S points to an instance of the Q15 DCT4 structure.\r
+ * @param[in] *pState points to state buffer.\r
+ * @param[in,out] *pInlineBuffer points to the in-place input and output buffer.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_dct4_q15(\r
+ const arm_dct4_instance_q15 * S,\r
+ q15_t * pState,\r
+ q15_t * pInlineBuffer);\r
+\r
+ /**\r
+ * @brief Floating-point vector addition.\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_add_f32(\r
+ float32_t * pSrcA,\r
+ float32_t * pSrcB,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Q7 vector addition.\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_add_q7(\r
+ q7_t * pSrcA,\r
+ q7_t * pSrcB,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Q15 vector addition.\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_add_q15(\r
+ q15_t * pSrcA,\r
+ q15_t * pSrcB,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Q31 vector addition.\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_add_q31(\r
+ q31_t * pSrcA,\r
+ q31_t * pSrcB,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Floating-point vector subtraction.\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_sub_f32(\r
+ float32_t * pSrcA,\r
+ float32_t * pSrcB,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Q7 vector subtraction.\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_sub_q7(\r
+ q7_t * pSrcA,\r
+ q7_t * pSrcB,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Q15 vector subtraction.\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_sub_q15(\r
+ q15_t * pSrcA,\r
+ q15_t * pSrcB,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Q31 vector subtraction.\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_sub_q31(\r
+ q31_t * pSrcA,\r
+ q31_t * pSrcB,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Multiplies a floating-point vector by a scalar.\r
+ * @param[in] *pSrc points to the input vector\r
+ * @param[in] scale scale factor to be applied\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_scale_f32(\r
+ float32_t * pSrc,\r
+ float32_t scale,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Multiplies a Q7 vector by a scalar.\r
+ * @param[in] *pSrc points to the input vector\r
+ * @param[in] scaleFract fractional portion of the scale value\r
+ * @param[in] shift number of bits to shift the result by\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_scale_q7(\r
+ q7_t * pSrc,\r
+ q7_t scaleFract,\r
+ int8_t shift,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Multiplies a Q15 vector by a scalar.\r
+ * @param[in] *pSrc points to the input vector\r
+ * @param[in] scaleFract fractional portion of the scale value\r
+ * @param[in] shift number of bits to shift the result by\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_scale_q15(\r
+ q15_t * pSrc,\r
+ q15_t scaleFract,\r
+ int8_t shift,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Multiplies a Q31 vector by a scalar.\r
+ * @param[in] *pSrc points to the input vector\r
+ * @param[in] scaleFract fractional portion of the scale value\r
+ * @param[in] shift number of bits to shift the result by\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_scale_q31(\r
+ q31_t * pSrc,\r
+ q31_t scaleFract,\r
+ int8_t shift,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Q7 vector absolute value.\r
+ * @param[in] *pSrc points to the input buffer\r
+ * @param[out] *pDst points to the output buffer\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_abs_q7(\r
+ q7_t * pSrc,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Floating-point vector absolute value.\r
+ * @param[in] *pSrc points to the input buffer\r
+ * @param[out] *pDst points to the output buffer\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_abs_f32(\r
+ float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Q15 vector absolute value.\r
+ * @param[in] *pSrc points to the input buffer\r
+ * @param[out] *pDst points to the output buffer\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_abs_q15(\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Q31 vector absolute value.\r
+ * @param[in] *pSrc points to the input buffer\r
+ * @param[out] *pDst points to the output buffer\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_abs_q31(\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Dot product of floating-point vectors.\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @param[out] *result output result returned here\r
+ * @return none.\r
+ */\r
+\r
+ void arm_dot_prod_f32(\r
+ float32_t * pSrcA,\r
+ float32_t * pSrcB,\r
+ uint32_t blockSize,\r
+ float32_t * result);\r
+\r
+ /**\r
+ * @brief Dot product of Q7 vectors.\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @param[out] *result output result returned here\r
+ * @return none.\r
+ */\r
+\r
+ void arm_dot_prod_q7(\r
+ q7_t * pSrcA,\r
+ q7_t * pSrcB,\r
+ uint32_t blockSize,\r
+ q31_t * result);\r
+\r
+ /**\r
+ * @brief Dot product of Q15 vectors.\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @param[out] *result output result returned here\r
+ * @return none.\r
+ */\r
+\r
+ void arm_dot_prod_q15(\r
+ q15_t * pSrcA,\r
+ q15_t * pSrcB,\r
+ uint32_t blockSize,\r
+ q63_t * result);\r
+\r
+ /**\r
+ * @brief Dot product of Q31 vectors.\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @param[out] *result output result returned here\r
+ * @return none.\r
+ */\r
+\r
+ void arm_dot_prod_q31(\r
+ q31_t * pSrcA,\r
+ q31_t * pSrcB,\r
+ uint32_t blockSize,\r
+ q63_t * result);\r
+\r
+ /**\r
+ * @brief Shifts the elements of a Q7 vector a specified number of bits.\r
+ * @param[in] *pSrc points to the input vector\r
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_shift_q7(\r
+ q7_t * pSrc,\r
+ int8_t shiftBits,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Shifts the elements of a Q15 vector a specified number of bits.\r
+ * @param[in] *pSrc points to the input vector\r
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_shift_q15(\r
+ q15_t * pSrc,\r
+ int8_t shiftBits,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Shifts the elements of a Q31 vector a specified number of bits.\r
+ * @param[in] *pSrc points to the input vector\r
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_shift_q31(\r
+ q31_t * pSrc,\r
+ int8_t shiftBits,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Adds a constant offset to a floating-point vector.\r
+ * @param[in] *pSrc points to the input vector\r
+ * @param[in] offset is the offset to be added\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_offset_f32(\r
+ float32_t * pSrc,\r
+ float32_t offset,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Adds a constant offset to a Q7 vector.\r
+ * @param[in] *pSrc points to the input vector\r
+ * @param[in] offset is the offset to be added\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_offset_q7(\r
+ q7_t * pSrc,\r
+ q7_t offset,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Adds a constant offset to a Q15 vector.\r
+ * @param[in] *pSrc points to the input vector\r
+ * @param[in] offset is the offset to be added\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_offset_q15(\r
+ q15_t * pSrc,\r
+ q15_t offset,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Adds a constant offset to a Q31 vector.\r
+ * @param[in] *pSrc points to the input vector\r
+ * @param[in] offset is the offset to be added\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_offset_q31(\r
+ q31_t * pSrc,\r
+ q31_t offset,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Negates the elements of a floating-point vector.\r
+ * @param[in] *pSrc points to the input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_negate_f32(\r
+ float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Negates the elements of a Q7 vector.\r
+ * @param[in] *pSrc points to the input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_negate_q7(\r
+ q7_t * pSrc,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Negates the elements of a Q15 vector.\r
+ * @param[in] *pSrc points to the input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_negate_q15(\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Negates the elements of a Q31 vector.\r
+ * @param[in] *pSrc points to the input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_negate_q31(\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+ /**\r
+ * @brief Copies the elements of a floating-point vector.\r
+ * @param[in] *pSrc input pointer\r
+ * @param[out] *pDst output pointer\r
+ * @param[in] blockSize number of samples to process\r
+ * @return none.\r
+ */\r
+ void arm_copy_f32(\r
+ float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Copies the elements of a Q7 vector.\r
+ * @param[in] *pSrc input pointer\r
+ * @param[out] *pDst output pointer\r
+ * @param[in] blockSize number of samples to process\r
+ * @return none.\r
+ */\r
+ void arm_copy_q7(\r
+ q7_t * pSrc,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Copies the elements of a Q15 vector.\r
+ * @param[in] *pSrc input pointer\r
+ * @param[out] *pDst output pointer\r
+ * @param[in] blockSize number of samples to process\r
+ * @return none.\r
+ */\r
+ void arm_copy_q15(\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Copies the elements of a Q31 vector.\r
+ * @param[in] *pSrc input pointer\r
+ * @param[out] *pDst output pointer\r
+ * @param[in] blockSize number of samples to process\r
+ * @return none.\r
+ */\r
+ void arm_copy_q31(\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+ /**\r
+ * @brief Fills a constant value into a floating-point vector.\r
+ * @param[in] value input value to be filled\r
+ * @param[out] *pDst output pointer\r
+ * @param[in] blockSize number of samples to process\r
+ * @return none.\r
+ */\r
+ void arm_fill_f32(\r
+ float32_t value,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Fills a constant value into a Q7 vector.\r
+ * @param[in] value input value to be filled\r
+ * @param[out] *pDst output pointer\r
+ * @param[in] blockSize number of samples to process\r
+ * @return none.\r
+ */\r
+ void arm_fill_q7(\r
+ q7_t value,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Fills a constant value into a Q15 vector.\r
+ * @param[in] value input value to be filled\r
+ * @param[out] *pDst output pointer\r
+ * @param[in] blockSize number of samples to process\r
+ * @return none.\r
+ */\r
+ void arm_fill_q15(\r
+ q15_t value,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Fills a constant value into a Q31 vector.\r
+ * @param[in] value input value to be filled\r
+ * @param[out] *pDst output pointer\r
+ * @param[in] blockSize number of samples to process\r
+ * @return none.\r
+ */\r
+ void arm_fill_q31(\r
+ q31_t value,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+/**\r
+ * @brief Convolution of floating-point sequences.\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_conv_f32(\r
+ float32_t * pSrcA,\r
+ uint32_t srcALen,\r
+ float32_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ float32_t * pDst);\r
+\r
+/**\r
+ * @brief Convolution of Q15 sequences.\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_conv_q15(\r
+ q15_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q15_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q15_t * pDst);\r
+\r
+ /**\r
+ * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_conv_fast_q15(\r
+ q15_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q15_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q15_t * pDst);\r
+\r
+ /**\r
+ * @brief Convolution of Q31 sequences.\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_conv_q31(\r
+ q31_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q31_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q31_t * pDst);\r
+\r
+ /**\r
+ * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_conv_fast_q31(\r
+ q31_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q31_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q31_t * pDst);\r
+\r
+ /**\r
+ * @brief Convolution of Q7 sequences.\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_conv_q7(\r
+ q7_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q7_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q7_t * pDst);\r
+\r
+ /**\r
+ * @brief Partial convolution of floating-point sequences.\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] firstIndex is the first output sample to start with.\r
+ * @param[in] numPoints is the number of output points to be computed.\r
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r
+ */\r
+\r
+ arm_status arm_conv_partial_f32(\r
+ float32_t * pSrcA,\r
+ uint32_t srcALen,\r
+ float32_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ float32_t * pDst,\r
+ uint32_t firstIndex,\r
+ uint32_t numPoints);\r
+\r
+ /**\r
+ * @brief Partial convolution of Q15 sequences.\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] firstIndex is the first output sample to start with.\r
+ * @param[in] numPoints is the number of output points to be computed.\r
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r
+ */\r
+\r
+ arm_status arm_conv_partial_q15(\r
+ q15_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q15_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q15_t * pDst,\r
+ uint32_t firstIndex,\r
+ uint32_t numPoints);\r
+\r
+ /**\r
+ * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] firstIndex is the first output sample to start with.\r
+ * @param[in] numPoints is the number of output points to be computed.\r
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r
+ */\r
+\r
+ arm_status arm_conv_partial_fast_q15(\r
+ q15_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q15_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q15_t * pDst,\r
+ uint32_t firstIndex,\r
+ uint32_t numPoints);\r
+\r
+ /**\r
+ * @brief Partial convolution of Q31 sequences.\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] firstIndex is the first output sample to start with.\r
+ * @param[in] numPoints is the number of output points to be computed.\r
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r
+ */\r
+\r
+ arm_status arm_conv_partial_q31(\r
+ q31_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q31_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q31_t * pDst,\r
+ uint32_t firstIndex,\r
+ uint32_t numPoints);\r
+\r
+\r
+ /**\r
+ * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] firstIndex is the first output sample to start with.\r
+ * @param[in] numPoints is the number of output points to be computed.\r
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r
+ */\r
+\r
+ arm_status arm_conv_partial_fast_q31(\r
+ q31_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q31_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q31_t * pDst,\r
+ uint32_t firstIndex,\r
+ uint32_t numPoints);\r
+\r
+ /**\r
+ * @brief Partial convolution of Q7 sequences.\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] firstIndex is the first output sample to start with.\r
+ * @param[in] numPoints is the number of output points to be computed.\r
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r
+ */\r
+\r
+ arm_status arm_conv_partial_q7(\r
+ q7_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q7_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q7_t * pDst,\r
+ uint32_t firstIndex,\r
+ uint32_t numPoints);\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 FIR decimator.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint8_t M; /**< decimation factor. */\r
+ uint16_t numTaps; /**< number of coefficients in the filter. */\r
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
+ } arm_fir_decimate_instance_q15;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 FIR decimator.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint8_t M; /**< decimation factor. */\r
+ uint16_t numTaps; /**< number of coefficients in the filter. */\r
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
+\r
+ } arm_fir_decimate_instance_q31;\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point FIR decimator.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint8_t M; /**< decimation factor. */\r
+ uint16_t numTaps; /**< number of coefficients in the filter. */\r
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
+\r
+ } arm_fir_decimate_instance_f32;\r
+\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the floating-point FIR decimator.\r
+ * @param[in] *S points to an instance of the floating-point FIR decimator structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return none\r
+ */\r
+\r
+ void arm_fir_decimate_f32(\r
+ const arm_fir_decimate_instance_f32 * S,\r
+ float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the floating-point FIR decimator.\r
+ * @param[in,out] *S points to an instance of the floating-point FIR decimator structure.\r
+ * @param[in] numTaps number of coefficients in the filter.\r
+ * @param[in] M decimation factor.\r
+ * @param[in] *pCoeffs points to the filter coefficients.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if\r
+ * <code>blockSize</code> is not a multiple of <code>M</code>.\r
+ */\r
+\r
+ arm_status arm_fir_decimate_init_f32(\r
+ arm_fir_decimate_instance_f32 * S,\r
+ uint16_t numTaps,\r
+ uint8_t M,\r
+ float32_t * pCoeffs,\r
+ float32_t * pState,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Processing function for the Q15 FIR decimator.\r
+ * @param[in] *S points to an instance of the Q15 FIR decimator structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return none\r
+ */\r
+\r
+ void arm_fir_decimate_q15(\r
+ const arm_fir_decimate_instance_q15 * S,\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.\r
+ * @param[in] *S points to an instance of the Q15 FIR decimator structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return none\r
+ */\r
+\r
+ void arm_fir_decimate_fast_q15(\r
+ const arm_fir_decimate_instance_q15 * S,\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the Q15 FIR decimator.\r
+ * @param[in,out] *S points to an instance of the Q15 FIR decimator structure.\r
+ * @param[in] numTaps number of coefficients in the filter.\r
+ * @param[in] M decimation factor.\r
+ * @param[in] *pCoeffs points to the filter coefficients.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if\r
+ * <code>blockSize</code> is not a multiple of <code>M</code>.\r
+ */\r
+\r
+ arm_status arm_fir_decimate_init_q15(\r
+ arm_fir_decimate_instance_q15 * S,\r
+ uint16_t numTaps,\r
+ uint8_t M,\r
+ q15_t * pCoeffs,\r
+ q15_t * pState,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Processing function for the Q31 FIR decimator.\r
+ * @param[in] *S points to an instance of the Q31 FIR decimator structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return none\r
+ */\r
+\r
+ void arm_fir_decimate_q31(\r
+ const arm_fir_decimate_instance_q31 * S,\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.\r
+ * @param[in] *S points to an instance of the Q31 FIR decimator structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return none\r
+ */\r
+\r
+ void arm_fir_decimate_fast_q31(\r
+ arm_fir_decimate_instance_q31 * S,\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the Q31 FIR decimator.\r
+ * @param[in,out] *S points to an instance of the Q31 FIR decimator structure.\r
+ * @param[in] numTaps number of coefficients in the filter.\r
+ * @param[in] M decimation factor.\r
+ * @param[in] *pCoeffs points to the filter coefficients.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if\r
+ * <code>blockSize</code> is not a multiple of <code>M</code>.\r
+ */\r
+\r
+ arm_status arm_fir_decimate_init_q31(\r
+ arm_fir_decimate_instance_q31 * S,\r
+ uint16_t numTaps,\r
+ uint8_t M,\r
+ q31_t * pCoeffs,\r
+ q31_t * pState,\r
+ uint32_t blockSize);\r
+\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 FIR interpolator.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint8_t L; /**< upsample factor. */\r
+ uint16_t phaseLength; /**< length of each polyphase filter component. */\r
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */\r
+ q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */\r
+ } arm_fir_interpolate_instance_q15;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 FIR interpolator.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint8_t L; /**< upsample factor. */\r
+ uint16_t phaseLength; /**< length of each polyphase filter component. */\r
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */\r
+ q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */\r
+ } arm_fir_interpolate_instance_q31;\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point FIR interpolator.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint8_t L; /**< upsample factor. */\r
+ uint16_t phaseLength; /**< length of each polyphase filter component. */\r
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */\r
+ float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */\r
+ } arm_fir_interpolate_instance_f32;\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the Q15 FIR interpolator.\r
+ * @param[in] *S points to an instance of the Q15 FIR interpolator structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data.\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_fir_interpolate_q15(\r
+ const arm_fir_interpolate_instance_q15 * S,\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the Q15 FIR interpolator.\r
+ * @param[in,out] *S points to an instance of the Q15 FIR interpolator structure.\r
+ * @param[in] L upsample factor.\r
+ * @param[in] numTaps number of filter coefficients in the filter.\r
+ * @param[in] *pCoeffs points to the filter coefficient buffer.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if\r
+ * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.\r
+ */\r
+\r
+ arm_status arm_fir_interpolate_init_q15(\r
+ arm_fir_interpolate_instance_q15 * S,\r
+ uint8_t L,\r
+ uint16_t numTaps,\r
+ q15_t * pCoeffs,\r
+ q15_t * pState,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Processing function for the Q31 FIR interpolator.\r
+ * @param[in] *S points to an instance of the Q15 FIR interpolator structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data.\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_fir_interpolate_q31(\r
+ const arm_fir_interpolate_instance_q31 * S,\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Initialization function for the Q31 FIR interpolator.\r
+ * @param[in,out] *S points to an instance of the Q31 FIR interpolator structure.\r
+ * @param[in] L upsample factor.\r
+ * @param[in] numTaps number of filter coefficients in the filter.\r
+ * @param[in] *pCoeffs points to the filter coefficient buffer.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if\r
+ * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.\r
+ */\r
+\r
+ arm_status arm_fir_interpolate_init_q31(\r
+ arm_fir_interpolate_instance_q31 * S,\r
+ uint8_t L,\r
+ uint16_t numTaps,\r
+ q31_t * pCoeffs,\r
+ q31_t * pState,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the floating-point FIR interpolator.\r
+ * @param[in] *S points to an instance of the floating-point FIR interpolator structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data.\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_fir_interpolate_f32(\r
+ const arm_fir_interpolate_instance_f32 * S,\r
+ float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Initialization function for the floating-point FIR interpolator.\r
+ * @param[in,out] *S points to an instance of the floating-point FIR interpolator structure.\r
+ * @param[in] L upsample factor.\r
+ * @param[in] numTaps number of filter coefficients in the filter.\r
+ * @param[in] *pCoeffs points to the filter coefficient buffer.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if\r
+ * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.\r
+ */\r
+\r
+ arm_status arm_fir_interpolate_init_f32(\r
+ arm_fir_interpolate_instance_f32 * S,\r
+ uint8_t L,\r
+ uint16_t numTaps,\r
+ float32_t * pCoeffs,\r
+ float32_t * pState,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Instance structure for the high precision Q31 Biquad cascade filter.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */\r
+ q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */\r
+ q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */\r
+ uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */\r
+\r
+ } arm_biquad_cas_df1_32x64_ins_q31;\r
+\r
+\r
+ /**\r
+ * @param[in] *S points to an instance of the high precision Q31 Biquad cascade filter structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_biquad_cas_df1_32x64_q31(\r
+ const arm_biquad_cas_df1_32x64_ins_q31 * S,\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @param[in,out] *S points to an instance of the high precision Q31 Biquad cascade filter structure.\r
+ * @param[in] numStages number of 2nd order stages in the filter.\r
+ * @param[in] *pCoeffs points to the filter coefficients.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format\r
+ * @return none\r
+ */\r
+\r
+ void arm_biquad_cas_df1_32x64_init_q31(\r
+ arm_biquad_cas_df1_32x64_ins_q31 * S,\r
+ uint8_t numStages,\r
+ q31_t * pCoeffs,\r
+ q63_t * pState,\r
+ uint8_t postShift);\r
+\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */\r
+ float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */\r
+ float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */\r
+ } arm_biquad_cascade_df2T_instance_f32;\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.\r
+ * @param[in] *S points to an instance of the filter data structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_biquad_cascade_df2T_f32(\r
+ const arm_biquad_cascade_df2T_instance_f32 * S,\r
+ float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.\r
+ * @param[in,out] *S points to an instance of the filter data structure.\r
+ * @param[in] numStages number of 2nd order stages in the filter.\r
+ * @param[in] *pCoeffs points to the filter coefficients.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @return none\r
+ */\r
+\r
+ void arm_biquad_cascade_df2T_init_f32(\r
+ arm_biquad_cascade_df2T_instance_f32 * S,\r
+ uint8_t numStages,\r
+ float32_t * pCoeffs,\r
+ float32_t * pState);\r
+\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 FIR lattice filter.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t numStages; /**< number of filter stages. */\r
+ q15_t *pState; /**< points to the state variable array. The array is of length numStages. */\r
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */\r
+ } arm_fir_lattice_instance_q15;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 FIR lattice filter.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t numStages; /**< number of filter stages. */\r
+ q31_t *pState; /**< points to the state variable array. The array is of length numStages. */\r
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */\r
+ } arm_fir_lattice_instance_q31;\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point FIR lattice filter.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t numStages; /**< number of filter stages. */\r
+ float32_t *pState; /**< points to the state variable array. The array is of length numStages. */\r
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */\r
+ } arm_fir_lattice_instance_f32;\r
+\r
+ /**\r
+ * @brief Initialization function for the Q15 FIR lattice filter.\r
+ * @param[in] *S points to an instance of the Q15 FIR lattice structure.\r
+ * @param[in] numStages number of filter stages.\r
+ * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages.\r
+ * @param[in] *pState points to the state buffer. The array is of length numStages.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_fir_lattice_init_q15(\r
+ arm_fir_lattice_instance_q15 * S,\r
+ uint16_t numStages,\r
+ q15_t * pCoeffs,\r
+ q15_t * pState);\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the Q15 FIR lattice filter.\r
+ * @param[in] *S points to an instance of the Q15 FIR lattice structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+ void arm_fir_lattice_q15(\r
+ const arm_fir_lattice_instance_q15 * S,\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Initialization function for the Q31 FIR lattice filter.\r
+ * @param[in] *S points to an instance of the Q31 FIR lattice structure.\r
+ * @param[in] numStages number of filter stages.\r
+ * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages.\r
+ * @param[in] *pState points to the state buffer. The array is of length numStages.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_fir_lattice_init_q31(\r
+ arm_fir_lattice_instance_q31 * S,\r
+ uint16_t numStages,\r
+ q31_t * pCoeffs,\r
+ q31_t * pState);\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the Q31 FIR lattice filter.\r
+ * @param[in] *S points to an instance of the Q31 FIR lattice structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_fir_lattice_q31(\r
+ const arm_fir_lattice_instance_q31 * S,\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+/**\r
+ * @brief Initialization function for the floating-point FIR lattice filter.\r
+ * @param[in] *S points to an instance of the floating-point FIR lattice structure.\r
+ * @param[in] numStages number of filter stages.\r
+ * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages.\r
+ * @param[in] *pState points to the state buffer. The array is of length numStages.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_fir_lattice_init_f32(\r
+ arm_fir_lattice_instance_f32 * S,\r
+ uint16_t numStages,\r
+ float32_t * pCoeffs,\r
+ float32_t * pState);\r
+\r
+ /**\r
+ * @brief Processing function for the floating-point FIR lattice filter.\r
+ * @param[in] *S points to an instance of the floating-point FIR lattice structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_fir_lattice_f32(\r
+ const arm_fir_lattice_instance_f32 * S,\r
+ float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 IIR lattice filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numStages; /**< number of stages in the filter. */\r
+ q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */\r
+ q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */\r
+ q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */\r
+ } arm_iir_lattice_instance_q15;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 IIR lattice filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numStages; /**< number of stages in the filter. */\r
+ q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */\r
+ q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */\r
+ q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */\r
+ } arm_iir_lattice_instance_q31;\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point IIR lattice filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numStages; /**< number of stages in the filter. */\r
+ float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */\r
+ float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */\r
+ float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */\r
+ } arm_iir_lattice_instance_f32;\r
+\r
+ /**\r
+ * @brief Processing function for the floating-point IIR lattice filter.\r
+ * @param[in] *S points to an instance of the floating-point IIR lattice structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_iir_lattice_f32(\r
+ const arm_iir_lattice_instance_f32 * S,\r
+ float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Initialization function for the floating-point IIR lattice filter.\r
+ * @param[in] *S points to an instance of the floating-point IIR lattice structure.\r
+ * @param[in] numStages number of stages in the filter.\r
+ * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages.\r
+ * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1.\r
+ * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize-1.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_iir_lattice_init_f32(\r
+ arm_iir_lattice_instance_f32 * S,\r
+ uint16_t numStages,\r
+ float32_t *pkCoeffs,\r
+ float32_t *pvCoeffs,\r
+ float32_t *pState,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the Q31 IIR lattice filter.\r
+ * @param[in] *S points to an instance of the Q31 IIR lattice structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_iir_lattice_q31(\r
+ const arm_iir_lattice_instance_q31 * S,\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the Q31 IIR lattice filter.\r
+ * @param[in] *S points to an instance of the Q31 IIR lattice structure.\r
+ * @param[in] numStages number of stages in the filter.\r
+ * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages.\r
+ * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1.\r
+ * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_iir_lattice_init_q31(\r
+ arm_iir_lattice_instance_q31 * S,\r
+ uint16_t numStages,\r
+ q31_t *pkCoeffs,\r
+ q31_t *pvCoeffs,\r
+ q31_t *pState,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the Q15 IIR lattice filter.\r
+ * @param[in] *S points to an instance of the Q15 IIR lattice structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_iir_lattice_q15(\r
+ const arm_iir_lattice_instance_q15 * S,\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+/**\r
+ * @brief Initialization function for the Q15 IIR lattice filter.\r
+ * @param[in] *S points to an instance of the fixed-point Q15 IIR lattice structure.\r
+ * @param[in] numStages number of stages in the filter.\r
+ * @param[in] *pkCoeffs points to reflection coefficient buffer. The array is of length numStages.\r
+ * @param[in] *pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1.\r
+ * @param[in] *pState points to state buffer. The array is of length numStages+blockSize.\r
+ * @param[in] blockSize number of samples to process per call.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_iir_lattice_init_q15(\r
+ arm_iir_lattice_instance_q15 * S,\r
+ uint16_t numStages,\r
+ q15_t *pkCoeffs,\r
+ q15_t *pvCoeffs,\r
+ q15_t *pState,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point LMS filter.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< number of coefficients in the filter. */\r
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */\r
+ float32_t mu; /**< step size that controls filter coefficient updates. */\r
+ } arm_lms_instance_f32;\r
+\r
+ /**\r
+ * @brief Processing function for floating-point LMS filter.\r
+ * @param[in] *S points to an instance of the floating-point LMS filter structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[in] *pRef points to the block of reference data.\r
+ * @param[out] *pOut points to the block of output data.\r
+ * @param[out] *pErr points to the block of error data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_lms_f32(\r
+ const arm_lms_instance_f32 * S,\r
+ float32_t * pSrc,\r
+ float32_t * pRef,\r
+ float32_t * pOut,\r
+ float32_t * pErr,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Initialization function for floating-point LMS filter.\r
+ * @param[in] *S points to an instance of the floating-point LMS filter structure.\r
+ * @param[in] numTaps number of filter coefficients.\r
+ * @param[in] *pCoeffs points to the coefficient buffer.\r
+ * @param[in] *pState points to state buffer.\r
+ * @param[in] mu step size that controls filter coefficient updates.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_lms_init_f32(\r
+ arm_lms_instance_f32 * S,\r
+ uint16_t numTaps,\r
+ float32_t * pCoeffs,\r
+ float32_t * pState,\r
+ float32_t mu,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 LMS filter.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< number of coefficients in the filter. */\r
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */\r
+ q15_t mu; /**< step size that controls filter coefficient updates. */\r
+ uint32_t postShift; /**< bit shift applied to coefficients. */\r
+ } arm_lms_instance_q15;\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the Q15 LMS filter.\r
+ * @param[in] *S points to an instance of the Q15 LMS filter structure.\r
+ * @param[in] numTaps number of filter coefficients.\r
+ * @param[in] *pCoeffs points to the coefficient buffer.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @param[in] mu step size that controls filter coefficient updates.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @param[in] postShift bit shift applied to coefficients.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_lms_init_q15(\r
+ arm_lms_instance_q15 * S,\r
+ uint16_t numTaps,\r
+ q15_t * pCoeffs,\r
+ q15_t * pState,\r
+ q15_t mu,\r
+ uint32_t blockSize,\r
+ uint32_t postShift);\r
+\r
+ /**\r
+ * @brief Processing function for Q15 LMS filter.\r
+ * @param[in] *S points to an instance of the Q15 LMS filter structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[in] *pRef points to the block of reference data.\r
+ * @param[out] *pOut points to the block of output data.\r
+ * @param[out] *pErr points to the block of error data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_lms_q15(\r
+ const arm_lms_instance_q15 * S,\r
+ q15_t * pSrc,\r
+ q15_t * pRef,\r
+ q15_t * pOut,\r
+ q15_t * pErr,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 LMS filter.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< number of coefficients in the filter. */\r
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */\r
+ q31_t mu; /**< step size that controls filter coefficient updates. */\r
+ uint32_t postShift; /**< bit shift applied to coefficients. */\r
+\r
+ } arm_lms_instance_q31;\r
+\r
+ /**\r
+ * @brief Processing function for Q31 LMS filter.\r
+ * @param[in] *S points to an instance of the Q15 LMS filter structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[in] *pRef points to the block of reference data.\r
+ * @param[out] *pOut points to the block of output data.\r
+ * @param[out] *pErr points to the block of error data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_lms_q31(\r
+ const arm_lms_instance_q31 * S,\r
+ q31_t * pSrc,\r
+ q31_t * pRef,\r
+ q31_t * pOut,\r
+ q31_t * pErr,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Initialization function for Q31 LMS filter.\r
+ * @param[in] *S points to an instance of the Q31 LMS filter structure.\r
+ * @param[in] numTaps number of filter coefficients.\r
+ * @param[in] *pCoeffs points to coefficient buffer.\r
+ * @param[in] *pState points to state buffer.\r
+ * @param[in] mu step size that controls filter coefficient updates.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @param[in] postShift bit shift applied to coefficients.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_lms_init_q31(\r
+ arm_lms_instance_q31 * S,\r
+ uint16_t numTaps,\r
+ q31_t *pCoeffs,\r
+ q31_t *pState,\r
+ q31_t mu,\r
+ uint32_t blockSize,\r
+ uint32_t postShift);\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point normalized LMS filter.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< number of coefficients in the filter. */\r
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */\r
+ float32_t mu; /**< step size that control filter coefficient updates. */\r
+ float32_t energy; /**< saves previous frame energy. */\r
+ float32_t x0; /**< saves previous input sample. */\r
+ } arm_lms_norm_instance_f32;\r
+\r
+ /**\r
+ * @brief Processing function for floating-point normalized LMS filter.\r
+ * @param[in] *S points to an instance of the floating-point normalized LMS filter structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[in] *pRef points to the block of reference data.\r
+ * @param[out] *pOut points to the block of output data.\r
+ * @param[out] *pErr points to the block of error data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_lms_norm_f32(\r
+ arm_lms_norm_instance_f32 * S,\r
+ float32_t * pSrc,\r
+ float32_t * pRef,\r
+ float32_t * pOut,\r
+ float32_t * pErr,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Initialization function for floating-point normalized LMS filter.\r
+ * @param[in] *S points to an instance of the floating-point LMS filter structure.\r
+ * @param[in] numTaps number of filter coefficients.\r
+ * @param[in] *pCoeffs points to coefficient buffer.\r
+ * @param[in] *pState points to state buffer.\r
+ * @param[in] mu step size that controls filter coefficient updates.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_lms_norm_init_f32(\r
+ arm_lms_norm_instance_f32 * S,\r
+ uint16_t numTaps,\r
+ float32_t * pCoeffs,\r
+ float32_t * pState,\r
+ float32_t mu,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 normalized LMS filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< number of coefficients in the filter. */\r
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */\r
+ q31_t mu; /**< step size that controls filter coefficient updates. */\r
+ uint8_t postShift; /**< bit shift applied to coefficients. */\r
+ q31_t *recipTable; /**< points to the reciprocal initial value table. */\r
+ q31_t energy; /**< saves previous frame energy. */\r
+ q31_t x0; /**< saves previous input sample. */\r
+ } arm_lms_norm_instance_q31;\r
+\r
+ /**\r
+ * @brief Processing function for Q31 normalized LMS filter.\r
+ * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[in] *pRef points to the block of reference data.\r
+ * @param[out] *pOut points to the block of output data.\r
+ * @param[out] *pErr points to the block of error data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_lms_norm_q31(\r
+ arm_lms_norm_instance_q31 * S,\r
+ q31_t * pSrc,\r
+ q31_t * pRef,\r
+ q31_t * pOut,\r
+ q31_t * pErr,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Initialization function for Q31 normalized LMS filter.\r
+ * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.\r
+ * @param[in] numTaps number of filter coefficients.\r
+ * @param[in] *pCoeffs points to coefficient buffer.\r
+ * @param[in] *pState points to state buffer.\r
+ * @param[in] mu step size that controls filter coefficient updates.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @param[in] postShift bit shift applied to coefficients.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_lms_norm_init_q31(\r
+ arm_lms_norm_instance_q31 * S,\r
+ uint16_t numTaps,\r
+ q31_t * pCoeffs,\r
+ q31_t * pState,\r
+ q31_t mu,\r
+ uint32_t blockSize,\r
+ uint8_t postShift);\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 normalized LMS filter.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< Number of coefficients in the filter. */\r
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */\r
+ q15_t mu; /**< step size that controls filter coefficient updates. */\r
+ uint8_t postShift; /**< bit shift applied to coefficients. */\r
+ q15_t *recipTable; /**< Points to the reciprocal initial value table. */\r
+ q15_t energy; /**< saves previous frame energy. */\r
+ q15_t x0; /**< saves previous input sample. */\r
+ } arm_lms_norm_instance_q15;\r
+\r
+ /**\r
+ * @brief Processing function for Q15 normalized LMS filter.\r
+ * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[in] *pRef points to the block of reference data.\r
+ * @param[out] *pOut points to the block of output data.\r
+ * @param[out] *pErr points to the block of error data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_lms_norm_q15(\r
+ arm_lms_norm_instance_q15 * S,\r
+ q15_t * pSrc,\r
+ q15_t * pRef,\r
+ q15_t * pOut,\r
+ q15_t * pErr,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for Q15 normalized LMS filter.\r
+ * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.\r
+ * @param[in] numTaps number of filter coefficients.\r
+ * @param[in] *pCoeffs points to coefficient buffer.\r
+ * @param[in] *pState points to state buffer.\r
+ * @param[in] mu step size that controls filter coefficient updates.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @param[in] postShift bit shift applied to coefficients.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_lms_norm_init_q15(\r
+ arm_lms_norm_instance_q15 * S,\r
+ uint16_t numTaps,\r
+ q15_t * pCoeffs,\r
+ q15_t * pState,\r
+ q15_t mu,\r
+ uint32_t blockSize,\r
+ uint8_t postShift);\r
+\r
+ /**\r
+ * @brief Correlation of floating-point sequences.\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_correlate_f32(\r
+ float32_t * pSrcA,\r
+ uint32_t srcALen,\r
+ float32_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ float32_t * pDst);\r
+\r
+ /**\r
+ * @brief Correlation of Q15 sequences.\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_correlate_q15(\r
+ q15_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q15_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q15_t * pDst);\r
+\r
+ /**\r
+ * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_correlate_fast_q15(\r
+ q15_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q15_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q15_t * pDst);\r
+\r
+ /**\r
+ * @brief Correlation of Q31 sequences.\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_correlate_q31(\r
+ q31_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q31_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q31_t * pDst);\r
+\r
+ /**\r
+ * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_correlate_fast_q31(\r
+ q31_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q31_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q31_t * pDst);\r
+\r
+ /**\r
+ * @brief Correlation of Q7 sequences.\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_correlate_q7(\r
+ q7_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q7_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q7_t * pDst);\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point sparse FIR filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< number of coefficients in the filter. */\r
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */\r
+ float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */\r
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */\r
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */\r
+ } arm_fir_sparse_instance_f32;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 sparse FIR filter.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< number of coefficients in the filter. */\r
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */\r
+ q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */\r
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */\r
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */\r
+ } arm_fir_sparse_instance_q31;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 sparse FIR filter.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< number of coefficients in the filter. */\r
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */\r
+ q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */\r
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */\r
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */\r
+ } arm_fir_sparse_instance_q15;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q7 sparse FIR filter.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< number of coefficients in the filter. */\r
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */\r
+ q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */\r
+ q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */\r
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */\r
+ } arm_fir_sparse_instance_q7;\r
+\r
+ /**\r
+ * @brief Processing function for the floating-point sparse FIR filter.\r
+ * @param[in] *S points to an instance of the floating-point sparse FIR structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] *pScratchIn points to a temporary buffer of size blockSize.\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_fir_sparse_f32(\r
+ arm_fir_sparse_instance_f32 * S,\r
+ float32_t * pSrc,\r
+ float32_t * pDst,\r
+ float32_t * pScratchIn,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Initialization function for the floating-point sparse FIR filter.\r
+ * @param[in,out] *S points to an instance of the floating-point sparse FIR structure.\r
+ * @param[in] numTaps number of nonzero coefficients in the filter.\r
+ * @param[in] *pCoeffs points to the array of filter coefficients.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @param[in] *pTapDelay points to the array of offset times.\r
+ * @param[in] maxDelay maximum offset time supported.\r
+ * @param[in] blockSize number of samples that will be processed per block.\r
+ * @return none\r
+ */\r
+\r
+ void arm_fir_sparse_init_f32(\r
+ arm_fir_sparse_instance_f32 * S,\r
+ uint16_t numTaps,\r
+ float32_t * pCoeffs,\r
+ float32_t * pState,\r
+ int32_t * pTapDelay,\r
+ uint16_t maxDelay,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Processing function for the Q31 sparse FIR filter.\r
+ * @param[in] *S points to an instance of the Q31 sparse FIR structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] *pScratchIn points to a temporary buffer of size blockSize.\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_fir_sparse_q31(\r
+ arm_fir_sparse_instance_q31 * S,\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ q31_t * pScratchIn,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Initialization function for the Q31 sparse FIR filter.\r
+ * @param[in,out] *S points to an instance of the Q31 sparse FIR structure.\r
+ * @param[in] numTaps number of nonzero coefficients in the filter.\r
+ * @param[in] *pCoeffs points to the array of filter coefficients.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @param[in] *pTapDelay points to the array of offset times.\r
+ * @param[in] maxDelay maximum offset time supported.\r
+ * @param[in] blockSize number of samples that will be processed per block.\r
+ * @return none\r
+ */\r
+\r
+ void arm_fir_sparse_init_q31(\r
+ arm_fir_sparse_instance_q31 * S,\r
+ uint16_t numTaps,\r
+ q31_t * pCoeffs,\r
+ q31_t * pState,\r
+ int32_t * pTapDelay,\r
+ uint16_t maxDelay,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Processing function for the Q15 sparse FIR filter.\r
+ * @param[in] *S points to an instance of the Q15 sparse FIR structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] *pScratchIn points to a temporary buffer of size blockSize.\r
+ * @param[in] *pScratchOut points to a temporary buffer of size blockSize.\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_fir_sparse_q15(\r
+ arm_fir_sparse_instance_q15 * S,\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ q15_t * pScratchIn,\r
+ q31_t * pScratchOut,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the Q15 sparse FIR filter.\r
+ * @param[in,out] *S points to an instance of the Q15 sparse FIR structure.\r
+ * @param[in] numTaps number of nonzero coefficients in the filter.\r
+ * @param[in] *pCoeffs points to the array of filter coefficients.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @param[in] *pTapDelay points to the array of offset times.\r
+ * @param[in] maxDelay maximum offset time supported.\r
+ * @param[in] blockSize number of samples that will be processed per block.\r
+ * @return none\r
+ */\r
+\r
+ void arm_fir_sparse_init_q15(\r
+ arm_fir_sparse_instance_q15 * S,\r
+ uint16_t numTaps,\r
+ q15_t * pCoeffs,\r
+ q15_t * pState,\r
+ int32_t * pTapDelay,\r
+ uint16_t maxDelay,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Processing function for the Q7 sparse FIR filter.\r
+ * @param[in] *S points to an instance of the Q7 sparse FIR structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] *pScratchIn points to a temporary buffer of size blockSize.\r
+ * @param[in] *pScratchOut points to a temporary buffer of size blockSize.\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_fir_sparse_q7(\r
+ arm_fir_sparse_instance_q7 * S,\r
+ q7_t * pSrc,\r
+ q7_t * pDst,\r
+ q7_t * pScratchIn,\r
+ q31_t * pScratchOut,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Initialization function for the Q7 sparse FIR filter.\r
+ * @param[in,out] *S points to an instance of the Q7 sparse FIR structure.\r
+ * @param[in] numTaps number of nonzero coefficients in the filter.\r
+ * @param[in] *pCoeffs points to the array of filter coefficients.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @param[in] *pTapDelay points to the array of offset times.\r
+ * @param[in] maxDelay maximum offset time supported.\r
+ * @param[in] blockSize number of samples that will be processed per block.\r
+ * @return none\r
+ */\r
+\r
+ void arm_fir_sparse_init_q7(\r
+ arm_fir_sparse_instance_q7 * S,\r
+ uint16_t numTaps,\r
+ q7_t * pCoeffs,\r
+ q7_t * pState,\r
+ int32_t *pTapDelay,\r
+ uint16_t maxDelay,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /*\r
+ * @brief Floating-point sin_cos function.\r
+ * @param[in] theta input value in degrees\r
+ * @param[out] *pSinVal points to the processed sine output.\r
+ * @param[out] *pCosVal points to the processed cos output.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_sin_cos_f32(\r
+ float32_t theta,\r
+ float32_t *pSinVal,\r
+ float32_t *pCcosVal);\r
+\r
+ /*\r
+ * @brief Q31 sin_cos function.\r
+ * @param[in] theta scaled input value in degrees\r
+ * @param[out] *pSinVal points to the processed sine output.\r
+ * @param[out] *pCosVal points to the processed cosine output.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_sin_cos_q31(\r
+ q31_t theta,\r
+ q31_t *pSinVal,\r
+ q31_t *pCosVal);\r
+\r
+\r
+ /**\r
+ * @brief Floating-point complex conjugate.\r
+ * @param[in] *pSrc points to the input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] numSamples number of complex samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cmplx_conj_f32(\r
+ float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t numSamples);\r
+\r
+ /**\r
+ * @brief Q31 complex conjugate.\r
+ * @param[in] *pSrc points to the input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] numSamples number of complex samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cmplx_conj_q31(\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t numSamples);\r
+\r
+ /**\r
+ * @brief Q15 complex conjugate.\r
+ * @param[in] *pSrc points to the input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] numSamples number of complex samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cmplx_conj_q15(\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t numSamples);\r
+\r
+\r
+\r
+ /**\r
+ * @brief Floating-point complex magnitude squared\r
+ * @param[in] *pSrc points to the complex input vector\r
+ * @param[out] *pDst points to the real output vector\r
+ * @param[in] numSamples number of complex samples in the input vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cmplx_mag_squared_f32(\r
+ float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t numSamples);\r
+\r
+ /**\r
+ * @brief Q31 complex magnitude squared\r
+ * @param[in] *pSrc points to the complex input vector\r
+ * @param[out] *pDst points to the real output vector\r
+ * @param[in] numSamples number of complex samples in the input vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cmplx_mag_squared_q31(\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t numSamples);\r
+\r
+ /**\r
+ * @brief Q15 complex magnitude squared\r
+ * @param[in] *pSrc points to the complex input vector\r
+ * @param[out] *pDst points to the real output vector\r
+ * @param[in] numSamples number of complex samples in the input vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cmplx_mag_squared_q15(\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t numSamples);\r
+\r
+\r
+ /**\r
+ * @ingroup groupController\r
+ */\r
+\r
+ /**\r
+ * @defgroup PID PID Motor Control\r
+ *\r
+ * A Proportional Integral Derivative (PID) controller is a generic feedback control\r
+ * loop mechanism widely used in industrial control systems.\r
+ * A PID controller is the most commonly used type of feedback controller.\r
+ *\r
+ * This set of functions implements (PID) controllers\r
+ * for Q15, Q31, and floating-point data types. The functions operate on a single sample\r
+ * of data and each call to the function returns a single processed value.\r
+ * <code>S</code> points to an instance of the PID control data structure. <code>in</code>\r
+ * is the input sample value. The functions return the output value.\r
+ *\r
+ * \par Algorithm:\r
+ * <pre>\r
+ * y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]\r
+ * A0 = Kp + Ki + Kd\r
+ * A1 = (-Kp ) - (2 * Kd )\r
+ * A2 = Kd </pre>\r
+ *\r
+ * \par\r
+ * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant\r
+ *\r
+ * \par\r
+ * \image html PID.gif "Proportional Integral Derivative Controller"\r
+ *\r
+ * \par\r
+ * The PID controller calculates an "error" value as the difference between\r
+ * the measured output and the reference input.\r
+ * The controller attempts to minimize the error by adjusting the process control inputs.\r
+ * The proportional value determines the reaction to the current error,\r
+ * the integral value determines the reaction based on the sum of recent errors,\r
+ * and the derivative value determines the reaction based on the rate at which the error has been changing.\r
+ *\r
+ * \par Instance Structure\r
+ * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure.\r
+ * A separate instance structure must be defined for each PID Controller.\r
+ * There are separate instance structure declarations for each of the 3 supported data types.\r
+ *\r
+ * \par Reset Functions\r
+ * There is also an associated reset function for each data type which clears the state array.\r
+ *\r
+ * \par Initialization Functions\r
+ * There is also an associated initialization function for each data type.\r
+ * The initialization function performs the following operations:\r
+ * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains.\r
+ * - Zeros out the values in the state buffer.\r
+ *\r
+ * \par\r
+ * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function.\r
+ *\r
+ * \par Fixed-Point Behavior\r
+ * Care must be taken when using the fixed-point versions of the PID Controller functions.\r
+ * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.\r
+ * Refer to the function specific documentation below for usage guidelines.\r
+ */\r
+\r
+ /**\r
+ * @addtogroup PID\r
+ * @{\r
+ */\r
+\r
+ /**\r
+ * @brief Process function for the floating-point PID Control.\r
+ * @param[in,out] *S is an instance of the floating-point PID Control structure\r
+ * @param[in] in input sample to process\r
+ * @return out processed output sample.\r
+ */\r
+\r
+\r
+ __STATIC_INLINE float32_t arm_pid_f32(\r
+ arm_pid_instance_f32 * S,\r
+ float32_t in)\r
+ {\r
+ float32_t out;\r
+\r
+ /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */\r
+ out = (S->A0 * in) +\r
+ (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]);\r
+\r
+ /* Update state */\r
+ S->state[1] = S->state[0];\r
+ S->state[0] = in;\r
+ S->state[2] = out;\r
+\r
+ /* return to application */\r
+ return (out);\r
+\r
+ }\r
+\r
+ /**\r
+ * @brief Process function for the Q31 PID Control.\r
+ * @param[in,out] *S points to an instance of the Q31 PID Control structure\r
+ * @param[in] in input sample to process\r
+ * @return out processed output sample.\r
+ *\r
+ * <b>Scaling and Overflow Behavior:</b>\r
+ * \par\r
+ * The function is implemented using an internal 64-bit accumulator.\r
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.\r
+ * Thus, if the accumulator result overflows it wraps around rather than clip.\r
+ * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions.\r
+ * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.\r
+ */\r
+\r
+ __STATIC_INLINE q31_t arm_pid_q31(\r
+ arm_pid_instance_q31 * S,\r
+ q31_t in)\r
+ {\r
+ q63_t acc;\r
+ q31_t out;\r
+\r
+ /* acc = A0 * x[n] */\r
+ acc = (q63_t) S->A0 * in;\r
+\r
+ /* acc += A1 * x[n-1] */\r
+ acc += (q63_t) S->A1 * S->state[0];\r
+\r
+ /* acc += A2 * x[n-2] */\r
+ acc += (q63_t) S->A2 * S->state[1];\r
+\r
+ /* convert output to 1.31 format to add y[n-1] */\r
+ out = (q31_t) (acc >> 31u);\r
+\r
+ /* out += y[n-1] */\r
+ out += S->state[2];\r
+\r
+ /* Update state */\r
+ S->state[1] = S->state[0];\r
+ S->state[0] = in;\r
+ S->state[2] = out;\r
+\r
+ /* return to application */\r
+ return (out);\r
+\r
+ }\r
+\r
+ /**\r
+ * @brief Process function for the Q15 PID Control.\r
+ * @param[in,out] *S points to an instance of the Q15 PID Control structure\r
+ * @param[in] in input sample to process\r
+ * @return out processed output sample.\r
+ *\r
+ * <b>Scaling and Overflow Behavior:</b>\r
+ * \par\r
+ * The function is implemented using a 64-bit internal accumulator.\r
+ * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result.\r
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.\r
+ * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.\r
+ * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.\r
+ * Lastly, the accumulator is saturated to yield a result in 1.15 format.\r
+ */\r
+\r
+ __STATIC_INLINE q15_t arm_pid_q15(\r
+ arm_pid_instance_q15 * S,\r
+ q15_t in)\r
+ {\r
+ q63_t acc;\r
+ q15_t out;\r
+\r
+ /* Implementation of PID controller */\r
+\r
+ #ifdef ARM_MATH_CM0\r
+\r
+ /* acc = A0 * x[n] */\r
+ acc = ((q31_t) S->A0 )* in ;\r
+\r
+ #else\r
+\r
+ /* acc = A0 * x[n] */\r
+ acc = (q31_t) __SMUAD(S->A0, in);\r
+\r
+ #endif\r
+\r
+ #ifdef ARM_MATH_CM0\r
+\r
+ /* acc += A1 * x[n-1] + A2 * x[n-2] */\r
+ acc += (q31_t) S->A1 * S->state[0] ;\r
+ acc += (q31_t) S->A2 * S->state[1] ;\r
+\r
+ #else\r
+\r
+ /* acc += A1 * x[n-1] + A2 * x[n-2] */\r
+ acc = __SMLALD(S->A1, (q31_t)__SIMD32(S->state), acc);\r
+\r
+ #endif\r
+\r
+ /* acc += y[n-1] */\r
+ acc += (q31_t) S->state[2] << 15;\r
+\r
+ /* saturate the output */\r
+ out = (q15_t) (__SSAT((acc >> 15), 16));\r
+\r
+ /* Update state */\r
+ S->state[1] = S->state[0];\r
+ S->state[0] = in;\r
+ S->state[2] = out;\r
+\r
+ /* return to application */\r
+ return (out);\r
+\r
+ }\r
+\r
+ /**\r
+ * @} end of PID group\r
+ */\r
+\r
+\r
+ /**\r
+ * @brief Floating-point matrix inverse.\r
+ * @param[in] *src points to the instance of the input floating-point matrix structure.\r
+ * @param[out] *dst points to the instance of the output floating-point matrix structure.\r
+ * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.\r
+ * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.\r
+ */\r
+\r
+ arm_status arm_mat_inverse_f32(\r
+ const arm_matrix_instance_f32 * src,\r
+ arm_matrix_instance_f32 * dst);\r
+\r
+\r
+\r
+ /**\r
+ * @ingroup groupController\r
+ */\r
+\r
+\r
+ /**\r
+ * @defgroup clarke Vector Clarke Transform\r
+ * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector.\r
+ * Generally the Clarke transform uses three-phase currents <code>Ia, Ib and Ic</code> to calculate currents\r
+ * in the two-phase orthogonal stator axis <code>Ialpha</code> and <code>Ibeta</code>.\r
+ * When <code>Ialpha</code> is superposed with <code>Ia</code> as shown in the figure below\r
+ * \image html clarke.gif Stator current space vector and its components in (a,b).\r
+ * and <code>Ia + Ib + Ic = 0</code>, in this condition <code>Ialpha</code> and <code>Ibeta</code>\r
+ * can be calculated using only <code>Ia</code> and <code>Ib</code>.\r
+ *\r
+ * The function operates on a single sample of data and each call to the function returns the processed output.\r
+ * The library provides separate functions for Q31 and floating-point data types.\r
+ * \par Algorithm\r
+ * \image html clarkeFormula.gif\r
+ * where <code>Ia</code> and <code>Ib</code> are the instantaneous stator phases and\r
+ * <code>pIalpha</code> and <code>pIbeta</code> are the two coordinates of time invariant vector.\r
+ * \par Fixed-Point Behavior\r
+ * Care must be taken when using the Q31 version of the Clarke transform.\r
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.\r
+ * Refer to the function specific documentation below for usage guidelines.\r
+ */\r
+\r
+ /**\r
+ * @addtogroup clarke\r
+ * @{\r
+ */\r
+\r
+ /**\r
+ *\r
+ * @brief Floating-point Clarke transform\r
+ * @param[in] Ia input three-phase coordinate <code>a</code>\r
+ * @param[in] Ib input three-phase coordinate <code>b</code>\r
+ * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha\r
+ * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta\r
+ * @return none.\r
+ */\r
+\r
+ __STATIC_INLINE void arm_clarke_f32(\r
+ float32_t Ia,\r
+ float32_t Ib,\r
+ float32_t * pIalpha,\r
+ float32_t * pIbeta)\r
+ {\r
+ /* Calculate pIalpha using the equation, pIalpha = Ia */\r
+ *pIalpha = Ia;\r
+\r
+ /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */\r
+ *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib);\r
+\r
+ }\r
+\r
+ /**\r
+ * @brief Clarke transform for Q31 version\r
+ * @param[in] Ia input three-phase coordinate <code>a</code>\r
+ * @param[in] Ib input three-phase coordinate <code>b</code>\r
+ * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha\r
+ * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta\r
+ * @return none.\r
+ *\r
+ * <b>Scaling and Overflow Behavior:</b>\r
+ * \par\r
+ * The function is implemented using an internal 32-bit accumulator.\r
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.\r
+ * There is saturation on the addition, hence there is no risk of overflow.\r
+ */\r
+\r
+ __STATIC_INLINE void arm_clarke_q31(\r
+ q31_t Ia,\r
+ q31_t Ib,\r
+ q31_t * pIalpha,\r
+ q31_t * pIbeta)\r
+ {\r
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */\r
+\r
+ /* Calculating pIalpha from Ia by equation pIalpha = Ia */\r
+ *pIalpha = Ia;\r
+\r
+ /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */\r
+ product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30);\r
+\r
+ /* Intermediate product is calculated by (2/sqrt(3) * Ib) */\r
+ product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30);\r
+\r
+ /* pIbeta is calculated by adding the intermediate products */\r
+ *pIbeta = __QADD(product1, product2);\r
+ }\r
+\r
+ /**\r
+ * @} end of clarke group\r
+ */\r
+\r
+ /**\r
+ * @brief Converts the elements of the Q7 vector to Q31 vector.\r
+ * @param[in] *pSrc input pointer\r
+ * @param[out] *pDst output pointer\r
+ * @param[in] blockSize number of samples to process\r
+ * @return none.\r
+ */\r
+ void arm_q7_to_q31(\r
+ q7_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+\r
+\r
+ /**\r
+ * @ingroup groupController\r
+ */\r
+\r
+ /**\r
+ * @defgroup inv_clarke Vector Inverse Clarke Transform\r
+ * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases.\r
+ *\r
+ * The function operates on a single sample of data and each call to the function returns the processed output.\r
+ * The library provides separate functions for Q31 and floating-point data types.\r
+ * \par Algorithm\r
+ * \image html clarkeInvFormula.gif\r
+ * where <code>pIa</code> and <code>pIb</code> are the instantaneous stator phases and\r
+ * <code>Ialpha</code> and <code>Ibeta</code> are the two coordinates of time invariant vector.\r
+ * \par Fixed-Point Behavior\r
+ * Care must be taken when using the Q31 version of the Clarke transform.\r
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.\r
+ * Refer to the function specific documentation below for usage guidelines.\r
+ */\r
+\r
+ /**\r
+ * @addtogroup inv_clarke\r
+ * @{\r
+ */\r
+\r
+ /**\r
+ * @brief Floating-point Inverse Clarke transform\r
+ * @param[in] Ialpha input two-phase orthogonal vector axis alpha\r
+ * @param[in] Ibeta input two-phase orthogonal vector axis beta\r
+ * @param[out] *pIa points to output three-phase coordinate <code>a</code>\r
+ * @param[out] *pIb points to output three-phase coordinate <code>b</code>\r
+ * @return none.\r
+ */\r
+\r
+\r
+ __STATIC_INLINE void arm_inv_clarke_f32(\r
+ float32_t Ialpha,\r
+ float32_t Ibeta,\r
+ float32_t * pIa,\r
+ float32_t * pIb)\r
+ {\r
+ /* Calculating pIa from Ialpha by equation pIa = Ialpha */\r
+ *pIa = Ialpha;\r
+\r
+ /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */\r
+ *pIb = -0.5 * Ialpha + (float32_t) 0.8660254039 *Ibeta;\r
+\r
+ }\r
+\r
+ /**\r
+ * @brief Inverse Clarke transform for Q31 version\r
+ * @param[in] Ialpha input two-phase orthogonal vector axis alpha\r
+ * @param[in] Ibeta input two-phase orthogonal vector axis beta\r
+ * @param[out] *pIa points to output three-phase coordinate <code>a</code>\r
+ * @param[out] *pIb points to output three-phase coordinate <code>b</code>\r
+ * @return none.\r
+ *\r
+ * <b>Scaling and Overflow Behavior:</b>\r
+ * \par\r
+ * The function is implemented using an internal 32-bit accumulator.\r
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.\r
+ * There is saturation on the subtraction, hence there is no risk of overflow.\r
+ */\r
+\r
+ __STATIC_INLINE void arm_inv_clarke_q31(\r
+ q31_t Ialpha,\r
+ q31_t Ibeta,\r
+ q31_t * pIa,\r
+ q31_t * pIb)\r
+ {\r
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */\r
+\r
+ /* Calculating pIa from Ialpha by equation pIa = Ialpha */\r
+ *pIa = Ialpha;\r
+\r
+ /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */\r
+ product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31);\r
+\r
+ /* Intermediate product is calculated by (1/sqrt(3) * pIb) */\r
+ product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31);\r
+\r
+ /* pIb is calculated by subtracting the products */\r
+ *pIb = __QSUB(product2, product1);\r
+\r
+ }\r
+\r
+ /**\r
+ * @} end of inv_clarke group\r
+ */\r
+\r
+ /**\r
+ * @brief Converts the elements of the Q7 vector to Q15 vector.\r
+ * @param[in] *pSrc input pointer\r
+ * @param[out] *pDst output pointer\r
+ * @param[in] blockSize number of samples to process\r
+ * @return none.\r
+ */\r
+ void arm_q7_to_q15(\r
+ q7_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+\r
+ /**\r
+ * @ingroup groupController\r
+ */\r
+\r
+ /**\r
+ * @defgroup park Vector Park Transform\r
+ *\r
+ * Forward Park transform converts the input two-coordinate vector to flux and torque components.\r
+ * The Park transform can be used to realize the transformation of the <code>Ialpha</code> and the <code>Ibeta</code> currents\r
+ * from the stationary to the moving reference frame and control the spatial relationship between\r
+ * the stator vector current and rotor flux vector.\r
+ * If we consider the d axis aligned with the rotor flux, the diagram below shows the\r
+ * current vector and the relationship from the two reference frames:\r
+ * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame"\r
+ *\r
+ * The function operates on a single sample of data and each call to the function returns the processed output.\r
+ * The library provides separate functions for Q31 and floating-point data types.\r
+ * \par Algorithm\r
+ * \image html parkFormula.gif\r
+ * where <code>Ialpha</code> and <code>Ibeta</code> are the stator vector components,\r
+ * <code>pId</code> and <code>pIq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the\r
+ * cosine and sine values of theta (rotor flux position).\r
+ * \par Fixed-Point Behavior\r
+ * Care must be taken when using the Q31 version of the Park transform.\r
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.\r
+ * Refer to the function specific documentation below for usage guidelines.\r
+ */\r
+\r
+ /**\r
+ * @addtogroup park\r
+ * @{\r
+ */\r
+\r
+ /**\r
+ * @brief Floating-point Park transform\r
+ * @param[in] Ialpha input two-phase vector coordinate alpha\r
+ * @param[in] Ibeta input two-phase vector coordinate beta\r
+ * @param[out] *pId points to output rotor reference frame d\r
+ * @param[out] *pIq points to output rotor reference frame q\r
+ * @param[in] sinVal sine value of rotation angle theta\r
+ * @param[in] cosVal cosine value of rotation angle theta\r
+ * @return none.\r
+ *\r
+ * The function implements the forward Park transform.\r
+ *\r
+ */\r
+\r
+ __STATIC_INLINE void arm_park_f32(\r
+ float32_t Ialpha,\r
+ float32_t Ibeta,\r
+ float32_t * pId,\r
+ float32_t * pIq,\r
+ float32_t sinVal,\r
+ float32_t cosVal)\r
+ {\r
+ /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */\r
+ *pId = Ialpha * cosVal + Ibeta * sinVal;\r
+\r
+ /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */\r
+ *pIq = -Ialpha * sinVal + Ibeta * cosVal;\r
+\r
+ }\r
+\r
+ /**\r
+ * @brief Park transform for Q31 version\r
+ * @param[in] Ialpha input two-phase vector coordinate alpha\r
+ * @param[in] Ibeta input two-phase vector coordinate beta\r
+ * @param[out] *pId points to output rotor reference frame d\r
+ * @param[out] *pIq points to output rotor reference frame q\r
+ * @param[in] sinVal sine value of rotation angle theta\r
+ * @param[in] cosVal cosine value of rotation angle theta\r
+ * @return none.\r
+ *\r
+ * <b>Scaling and Overflow Behavior:</b>\r
+ * \par\r
+ * The function is implemented using an internal 32-bit accumulator.\r
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.\r
+ * There is saturation on the addition and subtraction, hence there is no risk of overflow.\r
+ */\r
+\r
+\r
+ __STATIC_INLINE void arm_park_q31(\r
+ q31_t Ialpha,\r
+ q31_t Ibeta,\r
+ q31_t * pId,\r
+ q31_t * pIq,\r
+ q31_t sinVal,\r
+ q31_t cosVal)\r
+ {\r
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */\r
+ q31_t product3, product4; /* Temporary variables used to store intermediate results */\r
+\r
+ /* Intermediate product is calculated by (Ialpha * cosVal) */\r
+ product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31);\r
+\r
+ /* Intermediate product is calculated by (Ibeta * sinVal) */\r
+ product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31);\r
+\r
+\r
+ /* Intermediate product is calculated by (Ialpha * sinVal) */\r
+ product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31);\r
+\r
+ /* Intermediate product is calculated by (Ibeta * cosVal) */\r
+ product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31);\r
+\r
+ /* Calculate pId by adding the two intermediate products 1 and 2 */\r
+ *pId = __QADD(product1, product2);\r
+\r
+ /* Calculate pIq by subtracting the two intermediate products 3 from 4 */\r
+ *pIq = __QSUB(product4, product3);\r
+ }\r
+\r
+ /**\r
+ * @} end of park group\r
+ */\r
+\r
+ /**\r
+ * @brief Converts the elements of the Q7 vector to floating-point vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[out] *pDst is output pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @return none.\r
+ */\r
+ void arm_q7_to_float(\r
+ q7_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @ingroup groupController\r
+ */\r
+\r
+ /**\r
+ * @defgroup inv_park Vector Inverse Park transform\r
+ * Inverse Park transform converts the input flux and torque components to two-coordinate vector.\r
+ *\r
+ * The function operates on a single sample of data and each call to the function returns the processed output.\r
+ * The library provides separate functions for Q31 and floating-point data types.\r
+ * \par Algorithm\r
+ * \image html parkInvFormula.gif\r
+ * where <code>pIalpha</code> and <code>pIbeta</code> are the stator vector components,\r
+ * <code>Id</code> and <code>Iq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the\r
+ * cosine and sine values of theta (rotor flux position).\r
+ * \par Fixed-Point Behavior\r
+ * Care must be taken when using the Q31 version of the Park transform.\r
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.\r
+ * Refer to the function specific documentation below for usage guidelines.\r
+ */\r
+\r
+ /**\r
+ * @addtogroup inv_park\r
+ * @{\r
+ */\r
+\r
+ /**\r
+ * @brief Floating-point Inverse Park transform\r
+ * @param[in] Id input coordinate of rotor reference frame d\r
+ * @param[in] Iq input coordinate of rotor reference frame q\r
+ * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha\r
+ * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta\r
+ * @param[in] sinVal sine value of rotation angle theta\r
+ * @param[in] cosVal cosine value of rotation angle theta\r
+ * @return none.\r
+ */\r
+\r
+ __STATIC_INLINE void arm_inv_park_f32(\r
+ float32_t Id,\r
+ float32_t Iq,\r
+ float32_t * pIalpha,\r
+ float32_t * pIbeta,\r
+ float32_t sinVal,\r
+ float32_t cosVal)\r
+ {\r
+ /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */\r
+ *pIalpha = Id * cosVal - Iq * sinVal;\r
+\r
+ /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */\r
+ *pIbeta = Id * sinVal + Iq * cosVal;\r
+\r
+ }\r
+\r
+\r
+ /**\r
+ * @brief Inverse Park transform for Q31 version\r
+ * @param[in] Id input coordinate of rotor reference frame d\r
+ * @param[in] Iq input coordinate of rotor reference frame q\r
+ * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha\r
+ * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta\r
+ * @param[in] sinVal sine value of rotation angle theta\r
+ * @param[in] cosVal cosine value of rotation angle theta\r
+ * @return none.\r
+ *\r
+ * <b>Scaling and Overflow Behavior:</b>\r
+ * \par\r
+ * The function is implemented using an internal 32-bit accumulator.\r
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.\r
+ * There is saturation on the addition, hence there is no risk of overflow.\r
+ */\r
+\r
+\r
+ __STATIC_INLINE void arm_inv_park_q31(\r
+ q31_t Id,\r
+ q31_t Iq,\r
+ q31_t * pIalpha,\r
+ q31_t * pIbeta,\r
+ q31_t sinVal,\r
+ q31_t cosVal)\r
+ {\r
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */\r
+ q31_t product3, product4; /* Temporary variables used to store intermediate results */\r
+\r
+ /* Intermediate product is calculated by (Id * cosVal) */\r
+ product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31);\r
+\r
+ /* Intermediate product is calculated by (Iq * sinVal) */\r
+ product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31);\r
+\r
+\r
+ /* Intermediate product is calculated by (Id * sinVal) */\r
+ product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31);\r
+\r
+ /* Intermediate product is calculated by (Iq * cosVal) */\r
+ product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31);\r
+\r
+ /* Calculate pIalpha by using the two intermediate products 1 and 2 */\r
+ *pIalpha = __QSUB(product1, product2);\r
+\r
+ /* Calculate pIbeta by using the two intermediate products 3 and 4 */\r
+ *pIbeta = __QADD(product4, product3);\r
+\r
+ }\r
+\r
+ /**\r
+ * @} end of Inverse park group\r
+ */\r
+\r
+\r
+ /**\r
+ * @brief Converts the elements of the Q31 vector to floating-point vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[out] *pDst is output pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @return none.\r
+ */\r
+ void arm_q31_to_float(\r
+ q31_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @ingroup groupInterpolation\r
+ */\r
+\r
+ /**\r
+ * @defgroup LinearInterpolate Linear Interpolation\r
+ *\r
+ * Linear interpolation is a method of curve fitting using linear polynomials.\r
+ * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line\r
+ *\r
+ * \par\r
+ * \image html LinearInterp.gif "Linear interpolation"\r
+ *\r
+ * \par\r
+ * A Linear Interpolate function calculates an output value(y), for the input(x)\r
+ * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values)\r
+ *\r
+ * \par Algorithm:\r
+ * <pre>\r
+ * y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))\r
+ * where x0, x1 are nearest values of input x\r
+ * y0, y1 are nearest values to output y\r
+ * </pre>\r
+ *\r
+ * \par\r
+ * This set of functions implements Linear interpolation process\r
+ * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single\r
+ * sample of data and each call to the function returns a single processed value.\r
+ * <code>S</code> points to an instance of the Linear Interpolate function data structure.\r
+ * <code>x</code> is the input sample value. The functions returns the output value.\r
+ *\r
+ * \par\r
+ * if x is outside of the table boundary, Linear interpolation returns first value of the table\r
+ * if x is below input range and returns last value of table if x is above range.\r
+ */\r
+\r
+ /**\r
+ * @addtogroup LinearInterpolate\r
+ * @{\r
+ */\r
+\r
+ /**\r
+ * @brief Process function for the floating-point Linear Interpolation Function.\r
+ * @param[in,out] *S is an instance of the floating-point Linear Interpolation structure\r
+ * @param[in] x input sample to process\r
+ * @return y processed output sample.\r
+ *\r
+ */\r
+\r
+ __STATIC_INLINE float32_t arm_linear_interp_f32(\r
+ arm_linear_interp_instance_f32 * S,\r
+ float32_t x)\r
+ {\r
+\r
+ float32_t y;\r
+ float32_t x0, x1; /* Nearest input values */\r
+ float32_t y0, y1; /* Nearest output values */\r
+ float32_t xSpacing = S->xSpacing; /* spacing between input values */\r
+ int32_t i; /* Index variable */\r
+ float32_t *pYData = S->pYData; /* pointer to output table */\r
+\r
+ /* Calculation of index */\r
+ i = (x - S->x1) / xSpacing;\r
+\r
+ if(i < 0)\r
+ {\r
+ /* Iniatilize output for below specified range as least output value of table */\r
+ y = pYData[0];\r
+ }\r
+ else if(i >= S->nValues)\r
+ {\r
+ /* Iniatilize output for above specified range as last output value of table */\r
+ y = pYData[S->nValues-1];\r
+ }\r
+ else\r
+ {\r
+ /* Calculation of nearest input values */\r
+ x0 = S->x1 + i * xSpacing;\r
+ x1 = S->x1 + (i +1) * xSpacing;\r
+\r
+ /* Read of nearest output values */\r
+ y0 = pYData[i];\r
+ y1 = pYData[i + 1];\r
+\r
+ /* Calculation of output */\r
+ y = y0 + (x - x0) * ((y1 - y0)/(x1-x0));\r
+\r
+ }\r
+\r
+ /* returns output value */\r
+ return (y);\r
+ }\r
+\r
+ /**\r
+ *\r
+ * @brief Process function for the Q31 Linear Interpolation Function.\r
+ * @param[in] *pYData pointer to Q31 Linear Interpolation table\r
+ * @param[in] x input sample to process\r
+ * @param[in] nValues number of table values\r
+ * @return y processed output sample.\r
+ *\r
+ * \par\r
+ * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.\r
+ * This function can support maximum of table size 2^12.\r
+ *\r
+ */\r
+\r
+\r
+ __STATIC_INLINE q31_t arm_linear_interp_q31(q31_t *pYData,\r
+ q31_t x, uint32_t nValues)\r
+ {\r
+ q31_t y; /* output */\r
+ q31_t y0, y1; /* Nearest output values */\r
+ q31_t fract; /* fractional part */\r
+ int32_t index; /* Index to read nearest output values */\r
+\r
+ /* Input is in 12.20 format */\r
+ /* 12 bits for the table index */\r
+ /* Index value calculation */\r
+ index = ((x & 0xFFF00000) >> 20);\r
+\r
+ if(index >= (nValues - 1))\r
+ {\r
+ return(pYData[nValues - 1]);\r
+ }\r
+ else if(index < 0)\r
+ {\r
+ return(pYData[0]);\r
+ }\r
+ else\r
+ {\r
+\r
+ /* 20 bits for the fractional part */\r
+ /* shift left by 11 to keep fract in 1.31 format */\r
+ fract = (x & 0x000FFFFF) << 11;\r
+\r
+ /* Read two nearest output values from the index in 1.31(q31) format */\r
+ y0 = pYData[index];\r
+ y1 = pYData[index + 1u];\r
+\r
+ /* Calculation of y0 * (1-fract) and y is in 2.30 format */\r
+ y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32));\r
+\r
+ /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */\r
+ y += ((q31_t) (((q63_t) y1 * fract) >> 32));\r
+\r
+ /* Convert y to 1.31 format */\r
+ return (y << 1u);\r
+\r
+ }\r
+\r
+ }\r
+\r
+ /**\r
+ *\r
+ * @brief Process function for the Q15 Linear Interpolation Function.\r
+ * @param[in] *pYData pointer to Q15 Linear Interpolation table\r
+ * @param[in] x input sample to process\r
+ * @param[in] nValues number of table values\r
+ * @return y processed output sample.\r
+ *\r
+ * \par\r
+ * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.\r
+ * This function can support maximum of table size 2^12.\r
+ *\r
+ */\r
+\r
+\r
+ __STATIC_INLINE q15_t arm_linear_interp_q15(q15_t *pYData, q31_t x, uint32_t nValues)\r
+ {\r
+ q63_t y; /* output */\r
+ q15_t y0, y1; /* Nearest output values */\r
+ q31_t fract; /* fractional part */\r
+ int32_t index; /* Index to read nearest output values */\r
+\r
+ /* Input is in 12.20 format */\r
+ /* 12 bits for the table index */\r
+ /* Index value calculation */\r
+ index = ((x & 0xFFF00000) >> 20u);\r
+\r
+ if(index >= (nValues - 1))\r
+ {\r
+ return(pYData[nValues - 1]);\r
+ }\r
+ else if(index < 0)\r
+ {\r
+ return(pYData[0]);\r
+ }\r
+ else\r
+ {\r
+ /* 20 bits for the fractional part */\r
+ /* fract is in 12.20 format */\r
+ fract = (x & 0x000FFFFF);\r
+\r
+ /* Read two nearest output values from the index */\r
+ y0 = pYData[index];\r
+ y1 = pYData[index + 1u];\r
+\r
+ /* Calculation of y0 * (1-fract) and y is in 13.35 format */\r
+ y = ((q63_t) y0 * (0xFFFFF - fract));\r
+\r
+ /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */\r
+ y += ((q63_t) y1 * (fract));\r
+\r
+ /* convert y to 1.15 format */\r
+ return (y >> 20);\r
+ }\r
+\r
+\r
+ }\r
+\r
+ /**\r
+ *\r
+ * @brief Process function for the Q7 Linear Interpolation Function.\r
+ * @param[in] *pYData pointer to Q7 Linear Interpolation table\r
+ * @param[in] x input sample to process\r
+ * @param[in] nValues number of table values\r
+ * @return y processed output sample.\r
+ *\r
+ * \par\r
+ * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.\r
+ * This function can support maximum of table size 2^12.\r
+ */\r
+\r
+\r
+ __STATIC_INLINE q7_t arm_linear_interp_q7(q7_t *pYData, q31_t x, uint32_t nValues)\r
+ {\r
+ q31_t y; /* output */\r
+ q7_t y0, y1; /* Nearest output values */\r
+ q31_t fract; /* fractional part */\r
+ int32_t index; /* Index to read nearest output values */\r
+\r
+ /* Input is in 12.20 format */\r
+ /* 12 bits for the table index */\r
+ /* Index value calculation */\r
+ index = ((x & 0xFFF00000) >> 20u);\r
+\r
+\r
+ if(index >= (nValues - 1))\r
+ {\r
+ return(pYData[nValues - 1]);\r
+ }\r
+ else if(index < 0)\r
+ {\r
+ return(pYData[0]);\r
+ }\r
+ else\r
+ {\r
+\r
+ /* 20 bits for the fractional part */\r
+ /* fract is in 12.20 format */\r
+ fract = (x & 0x000FFFFF);\r
+\r
+ /* Read two nearest output values from the index and are in 1.7(q7) format */\r
+ y0 = pYData[index];\r
+ y1 = pYData[index + 1u];\r
+\r
+ /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */\r
+ y = ((y0 * (0xFFFFF - fract)));\r
+\r
+ /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */\r
+ y += (y1 * fract);\r
+\r
+ /* convert y to 1.7(q7) format */\r
+ return (y >> 20u);\r
+\r
+ }\r
+\r
+ }\r
+ /**\r
+ * @} end of LinearInterpolate group\r
+ */\r
+\r
+ /**\r
+ * @brief Fast approximation to the trigonometric sine function for floating-point data.\r
+ * @param[in] x input value in radians.\r
+ * @return sin(x).\r
+ */\r
+\r
+ float32_t arm_sin_f32(\r
+ float32_t x);\r
+\r
+ /**\r
+ * @brief Fast approximation to the trigonometric sine function for Q31 data.\r
+ * @param[in] x Scaled input value in radians.\r
+ * @return sin(x).\r
+ */\r
+\r
+ q31_t arm_sin_q31(\r
+ q31_t x);\r
+\r
+ /**\r
+ * @brief Fast approximation to the trigonometric sine function for Q15 data.\r
+ * @param[in] x Scaled input value in radians.\r
+ * @return sin(x).\r
+ */\r
+\r
+ q15_t arm_sin_q15(\r
+ q15_t x);\r
+\r
+ /**\r
+ * @brief Fast approximation to the trigonometric cosine function for floating-point data.\r
+ * @param[in] x input value in radians.\r
+ * @return cos(x).\r
+ */\r
+\r
+ float32_t arm_cos_f32(\r
+ float32_t x);\r
+\r
+ /**\r
+ * @brief Fast approximation to the trigonometric cosine function for Q31 data.\r
+ * @param[in] x Scaled input value in radians.\r
+ * @return cos(x).\r
+ */\r
+\r
+ q31_t arm_cos_q31(\r
+ q31_t x);\r
+\r
+ /**\r
+ * @brief Fast approximation to the trigonometric cosine function for Q15 data.\r
+ * @param[in] x Scaled input value in radians.\r
+ * @return cos(x).\r
+ */\r
+\r
+ q15_t arm_cos_q15(\r
+ q15_t x);\r
+\r
+\r
+ /**\r
+ * @ingroup groupFastMath\r
+ */\r
+\r
+\r
+ /**\r
+ * @defgroup SQRT Square Root\r
+ *\r
+ * Computes the square root of a number.\r
+ * There are separate functions for Q15, Q31, and floating-point data types.\r
+ * The square root function is computed using the Newton-Raphson algorithm.\r
+ * This is an iterative algorithm of the form:\r
+ * <pre>\r
+ * x1 = x0 - f(x0)/f'(x0)\r
+ * </pre>\r
+ * where <code>x1</code> is the current estimate,\r
+ * <code>x0</code> is the previous estimate and\r
+ * <code>f'(x0)</code> is the derivative of <code>f()</code> evaluated at <code>x0</code>.\r
+ * For the square root function, the algorithm reduces to:\r
+ * <pre>\r
+ * x0 = in/2 [initial guess]\r
+ * x1 = 1/2 * ( x0 + in / x0) [each iteration]\r
+ * </pre>\r
+ */\r
+\r
+\r
+ /**\r
+ * @addtogroup SQRT\r
+ * @{\r
+ */\r
+\r
+ /**\r
+ * @brief Floating-point square root function.\r
+ * @param[in] in input value.\r
+ * @param[out] *pOut square root of input value.\r
+ * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if\r
+ * <code>in</code> is negative value and returns zero output for negative values.\r
+ */\r
+\r
+ __STATIC_INLINE arm_status arm_sqrt_f32(\r
+ float32_t in, float32_t *pOut)\r
+ {\r
+ if(in > 0)\r
+ {\r
+\r
+// #if __FPU_USED\r
+ #if (__FPU_USED == 1) && defined ( __CC_ARM )\r
+ *pOut = __sqrtf(in);\r
+ #elif (__FPU_USED == 1) && defined ( __TMS_740 )\r
+ *pOut = __builtin_sqrtf(in);\r
+ #else\r
+ *pOut = sqrtf(in);\r
+ #endif\r
+\r
+ return (ARM_MATH_SUCCESS);\r
+ }\r
+ else\r
+ {\r
+ *pOut = 0.0f;\r
+ return (ARM_MATH_ARGUMENT_ERROR);\r
+ }\r
+\r
+ }\r
+\r
+\r
+ /**\r
+ * @brief Q31 square root function.\r
+ * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF.\r
+ * @param[out] *pOut square root of input value.\r
+ * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if\r
+ * <code>in</code> is negative value and returns zero output for negative values.\r
+ */\r
+ arm_status arm_sqrt_q31(\r
+ q31_t in, q31_t *pOut);\r
+\r
+ /**\r
+ * @brief Q15 square root function.\r
+ * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF.\r
+ * @param[out] *pOut square root of input value.\r
+ * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if\r
+ * <code>in</code> is negative value and returns zero output for negative values.\r
+ */\r
+ arm_status arm_sqrt_q15(\r
+ q15_t in, q15_t *pOut);\r
+\r
+ /**\r
+ * @} end of SQRT group\r
+ */\r
+\r
+\r
+\r
+\r
+\r
+\r
+ /**\r
+ * @brief floating-point Circular write function.\r
+ */\r
+\r
+ __STATIC_INLINE void arm_circularWrite_f32(\r
+ int32_t * circBuffer,\r
+ int32_t L,\r
+ uint16_t * writeOffset,\r
+ int32_t bufferInc,\r
+ const int32_t * src,\r
+ int32_t srcInc,\r
+ uint32_t blockSize)\r
+ {\r
+ uint32_t i = 0u;\r
+ int32_t wOffset;\r
+\r
+ /* Copy the value of Index pointer that points\r
+ * to the current location where the input samples to be copied */\r
+ wOffset = *writeOffset;\r
+\r
+ /* Loop over the blockSize */\r
+ i = blockSize;\r
+\r
+ while(i > 0u)\r
+ {\r
+ /* copy the input sample to the circular buffer */\r
+ circBuffer[wOffset] = *src;\r
+\r
+ /* Update the input pointer */\r
+ src += srcInc;\r
+\r
+ /* Circularly update wOffset. Watch out for positive and negative value */\r
+ wOffset += bufferInc;\r
+ if(wOffset >= L)\r
+ wOffset -= L;\r
+\r
+ /* Decrement the loop counter */\r
+ i--;\r
+ }\r
+\r
+ /* Update the index pointer */\r
+ *writeOffset = wOffset;\r
+ }\r
+\r
+\r
+\r
+ /**\r
+ * @brief floating-point Circular Read function.\r
+ */\r
+ __STATIC_INLINE void arm_circularRead_f32(\r
+ int32_t * circBuffer,\r
+ int32_t L,\r
+ int32_t * readOffset,\r
+ int32_t bufferInc,\r
+ int32_t * dst,\r
+ int32_t * dst_base,\r
+ int32_t dst_length,\r
+ int32_t dstInc,\r
+ uint32_t blockSize)\r
+ {\r
+ uint32_t i = 0u;\r
+ int32_t rOffset, dst_end;\r
+\r
+ /* Copy the value of Index pointer that points\r
+ * to the current location from where the input samples to be read */\r
+ rOffset = *readOffset;\r
+ dst_end = (int32_t) (dst_base + dst_length);\r
+\r
+ /* Loop over the blockSize */\r
+ i = blockSize;\r
+\r
+ while(i > 0u)\r
+ {\r
+ /* copy the sample from the circular buffer to the destination buffer */\r
+ *dst = circBuffer[rOffset];\r
+\r
+ /* Update the input pointer */\r
+ dst += dstInc;\r
+\r
+ if(dst == (int32_t *) dst_end)\r
+ {\r
+ dst = dst_base;\r
+ }\r
+\r
+ /* Circularly update rOffset. Watch out for positive and negative value */\r
+ rOffset += bufferInc;\r
+\r
+ if(rOffset >= L)\r
+ {\r
+ rOffset -= L;\r
+ }\r
+\r
+ /* Decrement the loop counter */\r
+ i--;\r
+ }\r
+\r
+ /* Update the index pointer */\r
+ *readOffset = rOffset;\r
+ }\r
+\r
+ /**\r
+ * @brief Q15 Circular write function.\r
+ */\r
+\r
+ __STATIC_INLINE void arm_circularWrite_q15(\r
+ q15_t * circBuffer,\r
+ int32_t L,\r
+ uint16_t * writeOffset,\r
+ int32_t bufferInc,\r
+ const q15_t * src,\r
+ int32_t srcInc,\r
+ uint32_t blockSize)\r
+ {\r
+ uint32_t i = 0u;\r
+ int32_t wOffset;\r
+\r
+ /* Copy the value of Index pointer that points\r
+ * to the current location where the input samples to be copied */\r
+ wOffset = *writeOffset;\r
+\r
+ /* Loop over the blockSize */\r
+ i = blockSize;\r
+\r
+ while(i > 0u)\r
+ {\r
+ /* copy the input sample to the circular buffer */\r
+ circBuffer[wOffset] = *src;\r
+\r
+ /* Update the input pointer */\r
+ src += srcInc;\r
+\r
+ /* Circularly update wOffset. Watch out for positive and negative value */\r
+ wOffset += bufferInc;\r
+ if(wOffset >= L)\r
+ wOffset -= L;\r
+\r
+ /* Decrement the loop counter */\r
+ i--;\r
+ }\r
+\r
+ /* Update the index pointer */\r
+ *writeOffset = wOffset;\r
+ }\r
+\r
+\r
+\r
+ /**\r
+ * @brief Q15 Circular Read function.\r
+ */\r
+ __STATIC_INLINE void arm_circularRead_q15(\r
+ q15_t * circBuffer,\r
+ int32_t L,\r
+ int32_t * readOffset,\r
+ int32_t bufferInc,\r
+ q15_t * dst,\r
+ q15_t * dst_base,\r
+ int32_t dst_length,\r
+ int32_t dstInc,\r
+ uint32_t blockSize)\r
+ {\r
+ uint32_t i = 0;\r
+ int32_t rOffset, dst_end;\r
+\r
+ /* Copy the value of Index pointer that points\r
+ * to the current location from where the input samples to be read */\r
+ rOffset = *readOffset;\r
+\r
+ dst_end = (int32_t) (dst_base + dst_length);\r
+\r
+ /* Loop over the blockSize */\r
+ i = blockSize;\r
+\r
+ while(i > 0u)\r
+ {\r
+ /* copy the sample from the circular buffer to the destination buffer */\r
+ *dst = circBuffer[rOffset];\r
+\r
+ /* Update the input pointer */\r
+ dst += dstInc;\r
+\r
+ if(dst == (q15_t *) dst_end)\r
+ {\r
+ dst = dst_base;\r
+ }\r
+\r
+ /* Circularly update wOffset. Watch out for positive and negative value */\r
+ rOffset += bufferInc;\r
+\r
+ if(rOffset >= L)\r
+ {\r
+ rOffset -= L;\r
+ }\r
+\r
+ /* Decrement the loop counter */\r
+ i--;\r
+ }\r
+\r
+ /* Update the index pointer */\r
+ *readOffset = rOffset;\r
+ }\r
+\r
+\r
+ /**\r
+ * @brief Q7 Circular write function.\r
+ */\r
+\r
+ __STATIC_INLINE void arm_circularWrite_q7(\r
+ q7_t * circBuffer,\r
+ int32_t L,\r
+ uint16_t * writeOffset,\r
+ int32_t bufferInc,\r
+ const q7_t * src,\r
+ int32_t srcInc,\r
+ uint32_t blockSize)\r
+ {\r
+ uint32_t i = 0u;\r
+ int32_t wOffset;\r
+\r
+ /* Copy the value of Index pointer that points\r
+ * to the current location where the input samples to be copied */\r
+ wOffset = *writeOffset;\r
+\r
+ /* Loop over the blockSize */\r
+ i = blockSize;\r
+\r
+ while(i > 0u)\r
+ {\r
+ /* copy the input sample to the circular buffer */\r
+ circBuffer[wOffset] = *src;\r
+\r
+ /* Update the input pointer */\r
+ src += srcInc;\r
+\r
+ /* Circularly update wOffset. Watch out for positive and negative value */\r
+ wOffset += bufferInc;\r
+ if(wOffset >= L)\r
+ wOffset -= L;\r
+\r
+ /* Decrement the loop counter */\r
+ i--;\r
+ }\r
+\r
+ /* Update the index pointer */\r
+ *writeOffset = wOffset;\r
+ }\r
+\r
+\r
+\r
+ /**\r
+ * @brief Q7 Circular Read function.\r
+ */\r
+ __STATIC_INLINE void arm_circularRead_q7(\r
+ q7_t * circBuffer,\r
+ int32_t L,\r
+ int32_t * readOffset,\r
+ int32_t bufferInc,\r
+ q7_t * dst,\r
+ q7_t * dst_base,\r
+ int32_t dst_length,\r
+ int32_t dstInc,\r
+ uint32_t blockSize)\r
+ {\r
+ uint32_t i = 0;\r
+ int32_t rOffset, dst_end;\r
+\r
+ /* Copy the value of Index pointer that points\r
+ * to the current location from where the input samples to be read */\r
+ rOffset = *readOffset;\r
+\r
+ dst_end = (int32_t) (dst_base + dst_length);\r
+\r
+ /* Loop over the blockSize */\r
+ i = blockSize;\r
+\r
+ while(i > 0u)\r
+ {\r
+ /* copy the sample from the circular buffer to the destination buffer */\r
+ *dst = circBuffer[rOffset];\r
+\r
+ /* Update the input pointer */\r
+ dst += dstInc;\r
+\r
+ if(dst == (q7_t *) dst_end)\r
+ {\r
+ dst = dst_base;\r
+ }\r
+\r
+ /* Circularly update rOffset. Watch out for positive and negative value */\r
+ rOffset += bufferInc;\r
+\r
+ if(rOffset >= L)\r
+ {\r
+ rOffset -= L;\r
+ }\r
+\r
+ /* Decrement the loop counter */\r
+ i--;\r
+ }\r
+\r
+ /* Update the index pointer */\r
+ *readOffset = rOffset;\r
+ }\r
+\r
+\r
+ /**\r
+ * @brief Sum of the squares of the elements of a Q31 vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output value.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_power_q31(\r
+ q31_t * pSrc,\r
+ uint32_t blockSize,\r
+ q63_t * pResult);\r
+\r
+ /**\r
+ * @brief Sum of the squares of the elements of a floating-point vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output value.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_power_f32(\r
+ float32_t * pSrc,\r
+ uint32_t blockSize,\r
+ float32_t * pResult);\r
+\r
+ /**\r
+ * @brief Sum of the squares of the elements of a Q15 vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output value.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_power_q15(\r
+ q15_t * pSrc,\r
+ uint32_t blockSize,\r
+ q63_t * pResult);\r
+\r
+ /**\r
+ * @brief Sum of the squares of the elements of a Q7 vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output value.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_power_q7(\r
+ q7_t * pSrc,\r
+ uint32_t blockSize,\r
+ q31_t * pResult);\r
+\r
+ /**\r
+ * @brief Mean value of a Q7 vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output value.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_mean_q7(\r
+ q7_t * pSrc,\r
+ uint32_t blockSize,\r
+ q7_t * pResult);\r
+\r
+ /**\r
+ * @brief Mean value of a Q15 vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output value.\r
+ * @return none.\r
+ */\r
+ void arm_mean_q15(\r
+ q15_t * pSrc,\r
+ uint32_t blockSize,\r
+ q15_t * pResult);\r
+\r
+ /**\r
+ * @brief Mean value of a Q31 vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output value.\r
+ * @return none.\r
+ */\r
+ void arm_mean_q31(\r
+ q31_t * pSrc,\r
+ uint32_t blockSize,\r
+ q31_t * pResult);\r
+\r
+ /**\r
+ * @brief Mean value of a floating-point vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output value.\r
+ * @return none.\r
+ */\r
+ void arm_mean_f32(\r
+ float32_t * pSrc,\r
+ uint32_t blockSize,\r
+ float32_t * pResult);\r
+\r
+ /**\r
+ * @brief Variance of the elements of a floating-point vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output value.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_var_f32(\r
+ float32_t * pSrc,\r
+ uint32_t blockSize,\r
+ float32_t * pResult);\r
+\r
+ /**\r
+ * @brief Variance of the elements of a Q31 vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output value.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_var_q31(\r
+ q31_t * pSrc,\r
+ uint32_t blockSize,\r
+ q63_t * pResult);\r
+\r
+ /**\r
+ * @brief Variance of the elements of a Q15 vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output value.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_var_q15(\r
+ q15_t * pSrc,\r
+ uint32_t blockSize,\r
+ q31_t * pResult);\r
+\r
+ /**\r
+ * @brief Root Mean Square of the elements of a floating-point vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output value.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_rms_f32(\r
+ float32_t * pSrc,\r
+ uint32_t blockSize,\r
+ float32_t * pResult);\r
+\r
+ /**\r
+ * @brief Root Mean Square of the elements of a Q31 vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output value.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_rms_q31(\r
+ q31_t * pSrc,\r
+ uint32_t blockSize,\r
+ q31_t * pResult);\r
+\r
+ /**\r
+ * @brief Root Mean Square of the elements of a Q15 vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output value.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_rms_q15(\r
+ q15_t * pSrc,\r
+ uint32_t blockSize,\r
+ q15_t * pResult);\r
+\r
+ /**\r
+ * @brief Standard deviation of the elements of a floating-point vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output value.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_std_f32(\r
+ float32_t * pSrc,\r
+ uint32_t blockSize,\r
+ float32_t * pResult);\r
+\r
+ /**\r
+ * @brief Standard deviation of the elements of a Q31 vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output value.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_std_q31(\r
+ q31_t * pSrc,\r
+ uint32_t blockSize,\r
+ q31_t * pResult);\r
+\r
+ /**\r
+ * @brief Standard deviation of the elements of a Q15 vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output value.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_std_q15(\r
+ q15_t * pSrc,\r
+ uint32_t blockSize,\r
+ q15_t * pResult);\r
+\r
+ /**\r
+ * @brief Floating-point complex magnitude\r
+ * @param[in] *pSrc points to the complex input vector\r
+ * @param[out] *pDst points to the real output vector\r
+ * @param[in] numSamples number of complex samples in the input vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cmplx_mag_f32(\r
+ float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t numSamples);\r
+\r
+ /**\r
+ * @brief Q31 complex magnitude\r
+ * @param[in] *pSrc points to the complex input vector\r
+ * @param[out] *pDst points to the real output vector\r
+ * @param[in] numSamples number of complex samples in the input vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cmplx_mag_q31(\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t numSamples);\r
+\r
+ /**\r
+ * @brief Q15 complex magnitude\r
+ * @param[in] *pSrc points to the complex input vector\r
+ * @param[out] *pDst points to the real output vector\r
+ * @param[in] numSamples number of complex samples in the input vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cmplx_mag_q15(\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t numSamples);\r
+\r
+ /**\r
+ * @brief Q15 complex dot product\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[in] numSamples number of complex samples in each vector\r
+ * @param[out] *realResult real part of the result returned here\r
+ * @param[out] *imagResult imaginary part of the result returned here\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cmplx_dot_prod_q15(\r
+ q15_t * pSrcA,\r
+ q15_t * pSrcB,\r
+ uint32_t numSamples,\r
+ q31_t * realResult,\r
+ q31_t * imagResult);\r
+\r
+ /**\r
+ * @brief Q31 complex dot product\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[in] numSamples number of complex samples in each vector\r
+ * @param[out] *realResult real part of the result returned here\r
+ * @param[out] *imagResult imaginary part of the result returned here\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cmplx_dot_prod_q31(\r
+ q31_t * pSrcA,\r
+ q31_t * pSrcB,\r
+ uint32_t numSamples,\r
+ q63_t * realResult,\r
+ q63_t * imagResult);\r
+\r
+ /**\r
+ * @brief Floating-point complex dot product\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[in] numSamples number of complex samples in each vector\r
+ * @param[out] *realResult real part of the result returned here\r
+ * @param[out] *imagResult imaginary part of the result returned here\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cmplx_dot_prod_f32(\r
+ float32_t * pSrcA,\r
+ float32_t * pSrcB,\r
+ uint32_t numSamples,\r
+ float32_t * realResult,\r
+ float32_t * imagResult);\r
+\r
+ /**\r
+ * @brief Q15 complex-by-real multiplication\r
+ * @param[in] *pSrcCmplx points to the complex input vector\r
+ * @param[in] *pSrcReal points to the real input vector\r
+ * @param[out] *pCmplxDst points to the complex output vector\r
+ * @param[in] numSamples number of samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cmplx_mult_real_q15(\r
+ q15_t * pSrcCmplx,\r
+ q15_t * pSrcReal,\r
+ q15_t * pCmplxDst,\r
+ uint32_t numSamples);\r
+\r
+ /**\r
+ * @brief Q31 complex-by-real multiplication\r
+ * @param[in] *pSrcCmplx points to the complex input vector\r
+ * @param[in] *pSrcReal points to the real input vector\r
+ * @param[out] *pCmplxDst points to the complex output vector\r
+ * @param[in] numSamples number of samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cmplx_mult_real_q31(\r
+ q31_t * pSrcCmplx,\r
+ q31_t * pSrcReal,\r
+ q31_t * pCmplxDst,\r
+ uint32_t numSamples);\r
+\r
+ /**\r
+ * @brief Floating-point complex-by-real multiplication\r
+ * @param[in] *pSrcCmplx points to the complex input vector\r
+ * @param[in] *pSrcReal points to the real input vector\r
+ * @param[out] *pCmplxDst points to the complex output vector\r
+ * @param[in] numSamples number of samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cmplx_mult_real_f32(\r
+ float32_t * pSrcCmplx,\r
+ float32_t * pSrcReal,\r
+ float32_t * pCmplxDst,\r
+ uint32_t numSamples);\r
+\r
+ /**\r
+ * @brief Minimum value of a Q7 vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *result is output pointer\r
+ * @param[in] index is the array index of the minimum value in the input buffer.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_min_q7(\r
+ q7_t * pSrc,\r
+ uint32_t blockSize,\r
+ q7_t * result,\r
+ uint32_t * index);\r
+\r
+ /**\r
+ * @brief Minimum value of a Q15 vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output pointer\r
+ * @param[in] *pIndex is the array index of the minimum value in the input buffer.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_min_q15(\r
+ q15_t * pSrc,\r
+ uint32_t blockSize,\r
+ q15_t * pResult,\r
+ uint32_t * pIndex);\r
+\r
+ /**\r
+ * @brief Minimum value of a Q31 vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output pointer\r
+ * @param[out] *pIndex is the array index of the minimum value in the input buffer.\r
+ * @return none.\r
+ */\r
+ void arm_min_q31(\r
+ q31_t * pSrc,\r
+ uint32_t blockSize,\r
+ q31_t * pResult,\r
+ uint32_t * pIndex);\r
+\r
+ /**\r
+ * @brief Minimum value of a floating-point vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output pointer\r
+ * @param[out] *pIndex is the array index of the minimum value in the input buffer.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_min_f32(\r
+ float32_t * pSrc,\r
+ uint32_t blockSize,\r
+ float32_t * pResult,\r
+ uint32_t * pIndex);\r
+\r
+/**\r
+ * @brief Maximum value of a Q7 vector.\r
+ * @param[in] *pSrc points to the input buffer\r
+ * @param[in] blockSize length of the input vector\r
+ * @param[out] *pResult maximum value returned here\r
+ * @param[out] *pIndex index of maximum value returned here\r
+ * @return none.\r
+ */\r
+\r
+ void arm_max_q7(\r
+ q7_t * pSrc,\r
+ uint32_t blockSize,\r
+ q7_t * pResult,\r
+ uint32_t * pIndex);\r
+\r
+/**\r
+ * @brief Maximum value of a Q15 vector.\r
+ * @param[in] *pSrc points to the input buffer\r
+ * @param[in] blockSize length of the input vector\r
+ * @param[out] *pResult maximum value returned here\r
+ * @param[out] *pIndex index of maximum value returned here\r
+ * @return none.\r
+ */\r
+\r
+ void arm_max_q15(\r
+ q15_t * pSrc,\r
+ uint32_t blockSize,\r
+ q15_t * pResult,\r
+ uint32_t * pIndex);\r
+\r
+/**\r
+ * @brief Maximum value of a Q31 vector.\r
+ * @param[in] *pSrc points to the input buffer\r
+ * @param[in] blockSize length of the input vector\r
+ * @param[out] *pResult maximum value returned here\r
+ * @param[out] *pIndex index of maximum value returned here\r
+ * @return none.\r
+ */\r
+\r
+ void arm_max_q31(\r
+ q31_t * pSrc,\r
+ uint32_t blockSize,\r
+ q31_t * pResult,\r
+ uint32_t * pIndex);\r
+\r
+/**\r
+ * @brief Maximum value of a floating-point vector.\r
+ * @param[in] *pSrc points to the input buffer\r
+ * @param[in] blockSize length of the input vector\r
+ * @param[out] *pResult maximum value returned here\r
+ * @param[out] *pIndex index of maximum value returned here\r
+ * @return none.\r
+ */\r
+\r
+ void arm_max_f32(\r
+ float32_t * pSrc,\r
+ uint32_t blockSize,\r
+ float32_t * pResult,\r
+ uint32_t * pIndex);\r
+\r
+ /**\r
+ * @brief Q15 complex-by-complex multiplication\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] numSamples number of complex samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cmplx_mult_cmplx_q15(\r
+ q15_t * pSrcA,\r
+ q15_t * pSrcB,\r
+ q15_t * pDst,\r
+ uint32_t numSamples);\r
+\r
+ /**\r
+ * @brief Q31 complex-by-complex multiplication\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] numSamples number of complex samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cmplx_mult_cmplx_q31(\r
+ q31_t * pSrcA,\r
+ q31_t * pSrcB,\r
+ q31_t * pDst,\r
+ uint32_t numSamples);\r
+\r
+ /**\r
+ * @brief Floating-point complex-by-complex multiplication\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] numSamples number of complex samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cmplx_mult_cmplx_f32(\r
+ float32_t * pSrcA,\r
+ float32_t * pSrcB,\r
+ float32_t * pDst,\r
+ uint32_t numSamples);\r
+\r
+ /**\r
+ * @brief Converts the elements of the floating-point vector to Q31 vector.\r
+ * @param[in] *pSrc points to the floating-point input vector\r
+ * @param[out] *pDst points to the Q31 output vector\r
+ * @param[in] blockSize length of the input vector\r
+ * @return none.\r
+ */\r
+ void arm_float_to_q31(\r
+ float32_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Converts the elements of the floating-point vector to Q15 vector.\r
+ * @param[in] *pSrc points to the floating-point input vector\r
+ * @param[out] *pDst points to the Q15 output vector\r
+ * @param[in] blockSize length of the input vector\r
+ * @return none\r
+ */\r
+ void arm_float_to_q15(\r
+ float32_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Converts the elements of the floating-point vector to Q7 vector.\r
+ * @param[in] *pSrc points to the floating-point input vector\r
+ * @param[out] *pDst points to the Q7 output vector\r
+ * @param[in] blockSize length of the input vector\r
+ * @return none\r
+ */\r
+ void arm_float_to_q7(\r
+ float32_t * pSrc,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Converts the elements of the Q31 vector to Q15 vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[out] *pDst is output pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @return none.\r
+ */\r
+ void arm_q31_to_q15(\r
+ q31_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Converts the elements of the Q31 vector to Q7 vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[out] *pDst is output pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @return none.\r
+ */\r
+ void arm_q31_to_q7(\r
+ q31_t * pSrc,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Converts the elements of the Q15 vector to floating-point vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[out] *pDst is output pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @return none.\r
+ */\r
+ void arm_q15_to_float(\r
+ q15_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Converts the elements of the Q15 vector to Q31 vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[out] *pDst is output pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @return none.\r
+ */\r
+ void arm_q15_to_q31(\r
+ q15_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Converts the elements of the Q15 vector to Q7 vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[out] *pDst is output pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @return none.\r
+ */\r
+ void arm_q15_to_q7(\r
+ q15_t * pSrc,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @ingroup groupInterpolation\r
+ */\r
+\r
+ /**\r
+ * @defgroup BilinearInterpolate Bilinear Interpolation\r
+ *\r
+ * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid.\r
+ * The underlying function <code>f(x, y)</code> is sampled on a regular grid and the interpolation process\r
+ * determines values between the grid points.\r
+ * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension.\r
+ * Bilinear interpolation is often used in image processing to rescale images.\r
+ * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types.\r
+ *\r
+ * <b>Algorithm</b>\r
+ * \par\r
+ * The instance structure used by the bilinear interpolation functions describes a two dimensional data table.\r
+ * For floating-point, the instance structure is defined as:\r
+ * <pre>\r
+ * typedef struct\r
+ * {\r
+ * uint16_t numRows;\r
+ * uint16_t numCols;\r
+ * float32_t *pData;\r
+ * } arm_bilinear_interp_instance_f32;\r
+ * </pre>\r
+ *\r
+ * \par\r
+ * where <code>numRows</code> specifies the number of rows in the table;\r
+ * <code>numCols</code> specifies the number of columns in the table;\r
+ * and <code>pData</code> points to an array of size <code>numRows*numCols</code> values.\r
+ * The data table <code>pTable</code> is organized in row order and the supplied data values fall on integer indexes.\r
+ * That is, table element (x,y) is located at <code>pTable[x + y*numCols]</code> where x and y are integers.\r
+ *\r
+ * \par\r
+ * Let <code>(x, y)</code> specify the desired interpolation point. Then define:\r
+ * <pre>\r
+ * XF = floor(x)\r
+ * YF = floor(y)\r
+ * </pre>\r
+ * \par\r
+ * The interpolated output point is computed as:\r
+ * <pre>\r
+ * f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))\r
+ * + f(XF+1, YF) * (x-XF)*(1-(y-YF))\r
+ * + f(XF, YF+1) * (1-(x-XF))*(y-YF)\r
+ * + f(XF+1, YF+1) * (x-XF)*(y-YF)\r
+ * </pre>\r
+ * Note that the coordinates (x, y) contain integer and fractional components.\r
+ * The integer components specify which portion of the table to use while the\r
+ * fractional components control the interpolation processor.\r
+ *\r
+ * \par\r
+ * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output.\r
+ */\r
+\r
+ /**\r
+ * @addtogroup BilinearInterpolate\r
+ * @{\r
+ */\r
+\r
+ /**\r
+ *\r
+ * @brief Floating-point bilinear interpolation.\r
+ * @param[in,out] *S points to an instance of the interpolation structure.\r
+ * @param[in] X interpolation coordinate.\r
+ * @param[in] Y interpolation coordinate.\r
+ * @return out interpolated value.\r
+ */\r
+\r
+\r
+ __STATIC_INLINE float32_t arm_bilinear_interp_f32(\r
+ const arm_bilinear_interp_instance_f32 * S,\r
+ float32_t X,\r
+ float32_t Y)\r
+ {\r
+ float32_t out;\r
+ float32_t f00, f01, f10, f11;\r
+ float32_t *pData = S->pData;\r
+ int32_t xIndex, yIndex, index;\r
+ float32_t xdiff, ydiff;\r
+ float32_t b1, b2, b3, b4;\r
+\r
+ xIndex = (int32_t) X;\r
+ yIndex = (int32_t) Y;\r
+\r
+ /* Care taken for table outside boundary */\r
+ /* Returns zero output when values are outside table boundary */\r
+ if(xIndex < 0 || xIndex > (S->numRows-1) || yIndex < 0 || yIndex > ( S->numCols-1))\r
+ {\r
+ return(0);\r
+ }\r
+\r
+ /* Calculation of index for two nearest points in X-direction */\r
+ index = (xIndex - 1) + (yIndex-1) * S->numCols ;\r
+\r
+\r
+ /* Read two nearest points in X-direction */\r
+ f00 = pData[index];\r
+ f01 = pData[index + 1];\r
+\r
+ /* Calculation of index for two nearest points in Y-direction */\r
+ index = (xIndex-1) + (yIndex) * S->numCols;\r
+\r
+\r
+ /* Read two nearest points in Y-direction */\r
+ f10 = pData[index];\r
+ f11 = pData[index + 1];\r
+\r
+ /* Calculation of intermediate values */\r
+ b1 = f00;\r
+ b2 = f01 - f00;\r
+ b3 = f10 - f00;\r
+ b4 = f00 - f01 - f10 + f11;\r
+\r
+ /* Calculation of fractional part in X */\r
+ xdiff = X - xIndex;\r
+\r
+ /* Calculation of fractional part in Y */\r
+ ydiff = Y - yIndex;\r
+\r
+ /* Calculation of bi-linear interpolated output */\r
+ out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff;\r
+\r
+ /* return to application */\r
+ return (out);\r
+\r
+ }\r
+\r
+ /**\r
+ *\r
+ * @brief Q31 bilinear interpolation.\r
+ * @param[in,out] *S points to an instance of the interpolation structure.\r
+ * @param[in] X interpolation coordinate in 12.20 format.\r
+ * @param[in] Y interpolation coordinate in 12.20 format.\r
+ * @return out interpolated value.\r
+ */\r
+\r
+ __STATIC_INLINE q31_t arm_bilinear_interp_q31(\r
+ arm_bilinear_interp_instance_q31 * S,\r
+ q31_t X,\r
+ q31_t Y)\r
+ {\r
+ q31_t out; /* Temporary output */\r
+ q31_t acc = 0; /* output */\r
+ q31_t xfract, yfract; /* X, Y fractional parts */\r
+ q31_t x1, x2, y1, y2; /* Nearest output values */\r
+ int32_t rI, cI; /* Row and column indices */\r
+ q31_t *pYData = S->pData; /* pointer to output table values */\r
+ uint32_t nCols = S->numCols; /* num of rows */\r
+\r
+\r
+ /* Input is in 12.20 format */\r
+ /* 12 bits for the table index */\r
+ /* Index value calculation */\r
+ rI = ((X & 0xFFF00000) >> 20u);\r
+\r
+ /* Input is in 12.20 format */\r
+ /* 12 bits for the table index */\r
+ /* Index value calculation */\r
+ cI = ((Y & 0xFFF00000) >> 20u);\r
+\r
+ /* Care taken for table outside boundary */\r
+ /* Returns zero output when values are outside table boundary */\r
+ if(rI < 0 || rI > (S->numRows-1) || cI < 0 || cI > ( S->numCols-1))\r
+ {\r
+ return(0);\r
+ }\r
+\r
+ /* 20 bits for the fractional part */\r
+ /* shift left xfract by 11 to keep 1.31 format */\r
+ xfract = (X & 0x000FFFFF) << 11u;\r
+\r
+ /* Read two nearest output values from the index */\r
+ x1 = pYData[(rI) + nCols * (cI)];\r
+ x2 = pYData[(rI) + nCols * (cI) + 1u];\r
+\r
+ /* 20 bits for the fractional part */\r
+ /* shift left yfract by 11 to keep 1.31 format */\r
+ yfract = (Y & 0x000FFFFF) << 11u;\r
+\r
+ /* Read two nearest output values from the index */\r
+ y1 = pYData[(rI) + nCols * (cI + 1)];\r
+ y2 = pYData[(rI) + nCols * (cI + 1) + 1u];\r
+\r
+ /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */\r
+ out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32));\r
+ acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32));\r
+\r
+ /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */\r
+ out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32));\r
+ acc += ((q31_t) ((q63_t) out * (xfract) >> 32));\r
+\r
+ /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */\r
+ out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32));\r
+ acc += ((q31_t) ((q63_t) out * (yfract) >> 32));\r
+\r
+ /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */\r
+ out = ((q31_t) ((q63_t) y2 * (xfract) >> 32));\r
+ acc += ((q31_t) ((q63_t) out * (yfract) >> 32));\r
+\r
+ /* Convert acc to 1.31(q31) format */\r
+ return (acc << 2u);\r
+\r
+ }\r
+\r
+ /**\r
+ * @brief Q15 bilinear interpolation.\r
+ * @param[in,out] *S points to an instance of the interpolation structure.\r
+ * @param[in] X interpolation coordinate in 12.20 format.\r
+ * @param[in] Y interpolation coordinate in 12.20 format.\r
+ * @return out interpolated value.\r
+ */\r
+\r
+ __STATIC_INLINE q15_t arm_bilinear_interp_q15(\r
+ arm_bilinear_interp_instance_q15 * S,\r
+ q31_t X,\r
+ q31_t Y)\r
+ {\r
+ q63_t acc = 0; /* output */\r
+ q31_t out; /* Temporary output */\r
+ q15_t x1, x2, y1, y2; /* Nearest output values */\r
+ q31_t xfract, yfract; /* X, Y fractional parts */\r
+ int32_t rI, cI; /* Row and column indices */\r
+ q15_t *pYData = S->pData; /* pointer to output table values */\r
+ uint32_t nCols = S->numCols; /* num of rows */\r
+\r
+ /* Input is in 12.20 format */\r
+ /* 12 bits for the table index */\r
+ /* Index value calculation */\r
+ rI = ((X & 0xFFF00000) >> 20);\r
+\r
+ /* Input is in 12.20 format */\r
+ /* 12 bits for the table index */\r
+ /* Index value calculation */\r
+ cI = ((Y & 0xFFF00000) >> 20);\r
+\r
+ /* Care taken for table outside boundary */\r
+ /* Returns zero output when values are outside table boundary */\r
+ if(rI < 0 || rI > (S->numRows-1) || cI < 0 || cI > ( S->numCols-1))\r
+ {\r
+ return(0);\r
+ }\r
+\r
+ /* 20 bits for the fractional part */\r
+ /* xfract should be in 12.20 format */\r
+ xfract = (X & 0x000FFFFF);\r
+\r
+ /* Read two nearest output values from the index */\r
+ x1 = pYData[(rI) + nCols * (cI)];\r
+ x2 = pYData[(rI) + nCols * (cI) + 1u];\r
+\r
+\r
+ /* 20 bits for the fractional part */\r
+ /* yfract should be in 12.20 format */\r
+ yfract = (Y & 0x000FFFFF);\r
+\r
+ /* Read two nearest output values from the index */\r
+ y1 = pYData[(rI) + nCols * (cI + 1)];\r
+ y2 = pYData[(rI) + nCols * (cI + 1) + 1u];\r
+\r
+ /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */\r
+\r
+ /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */\r
+ /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */\r
+ out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u);\r
+ acc = ((q63_t) out * (0xFFFFF - yfract));\r
+\r
+ /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */\r
+ out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u);\r
+ acc += ((q63_t) out * (xfract));\r
+\r
+ /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */\r
+ out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u);\r
+ acc += ((q63_t) out * (yfract));\r
+\r
+ /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */\r
+ out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u);\r
+ acc += ((q63_t) out * (yfract));\r
+\r
+ /* acc is in 13.51 format and down shift acc by 36 times */\r
+ /* Convert out to 1.15 format */\r
+ return (acc >> 36);\r
+\r
+ }\r
+\r
+ /**\r
+ * @brief Q7 bilinear interpolation.\r
+ * @param[in,out] *S points to an instance of the interpolation structure.\r
+ * @param[in] X interpolation coordinate in 12.20 format.\r
+ * @param[in] Y interpolation coordinate in 12.20 format.\r
+ * @return out interpolated value.\r
+ */\r
+\r
+ __STATIC_INLINE q7_t arm_bilinear_interp_q7(\r
+ arm_bilinear_interp_instance_q7 * S,\r
+ q31_t X,\r
+ q31_t Y)\r
+ {\r
+ q63_t acc = 0; /* output */\r
+ q31_t out; /* Temporary output */\r
+ q31_t xfract, yfract; /* X, Y fractional parts */\r
+ q7_t x1, x2, y1, y2; /* Nearest output values */\r
+ int32_t rI, cI; /* Row and column indices */\r
+ q7_t *pYData = S->pData; /* pointer to output table values */\r
+ uint32_t nCols = S->numCols; /* num of rows */\r
+\r
+ /* Input is in 12.20 format */\r
+ /* 12 bits for the table index */\r
+ /* Index value calculation */\r
+ rI = ((X & 0xFFF00000) >> 20);\r
+\r
+ /* Input is in 12.20 format */\r
+ /* 12 bits for the table index */\r
+ /* Index value calculation */\r
+ cI = ((Y & 0xFFF00000) >> 20);\r
+\r
+ /* Care taken for table outside boundary */\r
+ /* Returns zero output when values are outside table boundary */\r
+ if(rI < 0 || rI > (S->numRows-1) || cI < 0 || cI > ( S->numCols-1))\r
+ {\r
+ return(0);\r
+ }\r
+\r
+ /* 20 bits for the fractional part */\r
+ /* xfract should be in 12.20 format */\r
+ xfract = (X & 0x000FFFFF);\r
+\r
+ /* Read two nearest output values from the index */\r
+ x1 = pYData[(rI) + nCols * (cI)];\r
+ x2 = pYData[(rI) + nCols * (cI) + 1u];\r
+\r
+\r
+ /* 20 bits for the fractional part */\r
+ /* yfract should be in 12.20 format */\r
+ yfract = (Y & 0x000FFFFF);\r
+\r
+ /* Read two nearest output values from the index */\r
+ y1 = pYData[(rI) + nCols * (cI + 1)];\r
+ y2 = pYData[(rI) + nCols * (cI + 1) + 1u];\r
+\r
+ /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */\r
+ out = ((x1 * (0xFFFFF - xfract)));\r
+ acc = (((q63_t) out * (0xFFFFF - yfract)));\r
+\r
+ /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */\r
+ out = ((x2 * (0xFFFFF - yfract)));\r
+ acc += (((q63_t) out * (xfract)));\r
+\r
+ /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */\r
+ out = ((y1 * (0xFFFFF - xfract)));\r
+ acc += (((q63_t) out * (yfract)));\r
+\r
+ /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */\r
+ out = ((y2 * (yfract)));\r
+ acc += (((q63_t) out * (xfract)));\r
+\r
+ /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */\r
+ return (acc >> 40);\r
+\r
+ }\r
+\r
+ /**\r
+ * @} end of BilinearInterpolate group\r
+ */\r
+\r
+\r
+\r
+\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+\r
+#endif /* _ARM_MATH_H */\r
+\r
+\r
+/**\r
+ *\r
+ * End of file.\r
+ */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_cm4.h\r
+ * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File\r
+ * @version V3.00\r
+ * @date 03. February 2012\r
+ *\r
+ * @note\r
+ * Copyright (C) 2009-2012 ARM Limited. All rights reserved.\r
+ *\r
+ * @par\r
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M\r
+ * processor based microcontrollers. This file can be freely distributed\r
+ * within development tools that are supporting such ARM based processors.\r
+ *\r
+ * @par\r
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+ *\r
+ ******************************************************************************/\r
+#if defined ( __ICCARM__ )\r
+ #pragma system_include /* treat file as system include file for MISRA check */\r
+#endif\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+#ifndef __CORE_CM4_H_GENERIC\r
+#define __CORE_CM4_H_GENERIC\r
+\r
+/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions\r
+ CMSIS violates the following MISRA-C:2004 rules:\r
+ \r
+ \li Required Rule 8.5, object/function definition in header file.<br>\r
+ Function definitions in header files are used to allow 'inlining'. \r
+\r
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r
+ Unions are used for effective representation of core registers.\r
+ \r
+ \li Advisory Rule 19.7, Function-like macro defined.<br>\r
+ Function-like macros are used to allow more efficient code. \r
+ */\r
+\r
+\r
+/*******************************************************************************\r
+ * CMSIS definitions\r
+ ******************************************************************************/\r
+/** \ingroup Cortex_M4\r
+ @{\r
+ */\r
+\r
+/* CMSIS CM4 definitions */\r
+#define __CM4_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */\r
+#define __CM4_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */\r
+#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | \\r
+ __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */\r
+\r
+#define __CORTEX_M (0x04) /*!< Cortex-M Core */\r
+\r
+\r
+#if defined ( __CC_ARM )\r
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */\r
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */\r
+ #define __STATIC_INLINE static __inline\r
+\r
+#elif defined ( __ICCARM__ )\r
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */\r
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */\r
+ #define __STATIC_INLINE static inline\r
+\r
+#elif defined ( __TMS470__ )\r
+ #define __ASM __asm /*!< asm keyword for TI CCS Compiler */\r
+ #define __STATIC_INLINE static inline\r
+\r
+#elif defined ( __GNUC__ )\r
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */\r
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */\r
+ #define __STATIC_INLINE static inline\r
+\r
+#elif defined ( __TASKING__ )\r
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */\r
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */\r
+ #define __STATIC_INLINE static inline\r
+\r
+#endif\r
+\r
+/** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.\r
+*/\r
+#if defined ( __CC_ARM )\r
+ #if defined __TARGET_FPU_VFP\r
+ #if (__FPU_PRESENT == 1)\r
+ #define __FPU_USED 1\r
+ #else\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0\r
+ #endif\r
+\r
+#elif defined ( __ICCARM__ )\r
+ #if defined __ARMVFP__\r
+ #if (__FPU_PRESENT == 1)\r
+ #define __FPU_USED 1\r
+ #else\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0\r
+ #endif\r
+\r
+#elif defined ( __TMS470__ )\r
+ #if defined __TI_VFP_SUPPORT__\r
+ #if (__FPU_PRESENT == 1)\r
+ #define __FPU_USED 1\r
+ #else\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0\r
+ #endif\r
+\r
+#elif defined ( __GNUC__ )\r
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
+ #if (__FPU_PRESENT == 1)\r
+ #define __FPU_USED 1\r
+ #else\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0\r
+ #endif\r
+\r
+#elif defined ( __TASKING__ )\r
+ /* add preprocessor checks to define __FPU_USED */\r
+ #define __FPU_USED 0\r
+#endif\r
+\r
+#include <stdint.h> /* standard types definitions */\r
+#include <core_cmInstr.h> /* Core Instruction Access */\r
+#include <core_cmFunc.h> /* Core Function Access */\r
+#include <core_cm4_simd.h> /* Compiler specific SIMD Intrinsics */\r
+\r
+#endif /* __CORE_CM4_H_GENERIC */\r
+\r
+#ifndef __CMSIS_GENERIC\r
+\r
+#ifndef __CORE_CM4_H_DEPENDANT\r
+#define __CORE_CM4_H_DEPENDANT\r
+\r
+/* check device defines and use defaults */\r
+#if defined __CHECK_DEVICE_DEFINES\r
+ #ifndef __CM4_REV\r
+ #define __CM4_REV 0x0000\r
+ #warning "__CM4_REV not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __FPU_PRESENT\r
+ #define __FPU_PRESENT 0\r
+ #warning "__FPU_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __MPU_PRESENT\r
+ #define __MPU_PRESENT 0\r
+ #warning "__MPU_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __NVIC_PRIO_BITS\r
+ #define __NVIC_PRIO_BITS 4\r
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __Vendor_SysTickConfig\r
+ #define __Vendor_SysTickConfig 0\r
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
+ #endif\r
+#endif\r
+\r
+/* IO definitions (access restrictions to peripheral registers) */\r
+/**\r
+ \defgroup CMSIS_glob_defs CMSIS Global Defines\r
+ \r
+ <strong>IO Type Qualifiers</strong> are used\r
+ \li to specify the access to peripheral variables.\r
+ \li for automatic generation of peripheral register debug information.\r
+*/\r
+#ifdef __cplusplus\r
+ #define __I volatile /*!< Defines 'read only' permissions */\r
+#else\r
+ #define __I volatile const /*!< Defines 'read only' permissions */\r
+#endif\r
+#define __O volatile /*!< Defines 'write only' permissions */\r
+#define __IO volatile /*!< Defines 'read / write' permissions */\r
+\r
+/*@} end of group Cortex_M4 */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Register Abstraction\r
+ Core Register contain:\r
+ - Core Register\r
+ - Core NVIC Register\r
+ - Core SCB Register\r
+ - Core SysTick Register\r
+ - Core Debug Register\r
+ - Core MPU Register\r
+ - Core FPU Register\r
+ ******************************************************************************/\r
+/** \defgroup CMSIS_core_register Defines and Type Definitions\r
+ \brief Type definitions and defines for Cortex-M processor based devices.\r
+*/\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CORE Status and Control Registers\r
+ \brief Core Register type definitions.\r
+ @{\r
+ */\r
+\r
+/** \brief Union type to access the Application Program Status Register (APSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+#if (__CORTEX_M != 0x04)\r
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */\r
+#else\r
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */\r
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */\r
+#endif\r
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} APSR_Type;\r
+\r
+\r
+/** \brief Union type to access the Interrupt Program Status Register (IPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} IPSR_Type;\r
+\r
+\r
+/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+#if (__CORTEX_M != 0x04)\r
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */\r
+#else\r
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */\r
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */\r
+#endif\r
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */\r
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */\r
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} xPSR_Type;\r
+\r
+\r
+/** \brief Union type to access the Control Registers (CONTROL).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */\r
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */\r
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */\r
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} CONTROL_Type;\r
+\r
+/*@} end of group CMSIS_CORE */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)\r
+ \brief Type definitions for the NVIC Registers\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */\r
+ uint32_t RESERVED0[24];\r
+ __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */\r
+ uint32_t RSERVED1[24];\r
+ __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */\r
+ uint32_t RESERVED2[24];\r
+ __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */\r
+ uint32_t RESERVED3[24];\r
+ __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */\r
+ uint32_t RESERVED4[56];\r
+ __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */\r
+ uint32_t RESERVED5[644];\r
+ __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */\r
+} NVIC_Type;\r
+\r
+/* Software Triggered Interrupt Register Definitions */\r
+#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */\r
+#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */\r
+\r
+/*@} end of group CMSIS_NVIC */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCB System Control Block (SCB)\r
+ \brief Type definitions for the System Control Block Registers\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the System Control Block (SCB).\r
+ */\r
+typedef struct\r
+{\r
+ __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */\r
+ __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */\r
+ __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */\r
+ __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */\r
+ __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */\r
+ __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */\r
+ __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */\r
+ __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */\r
+ __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */\r
+ __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */\r
+ __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */\r
+ __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */\r
+ __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */\r
+ __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */\r
+ __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */\r
+ __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */\r
+ __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */\r
+ __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */\r
+ __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */\r
+ uint32_t RESERVED0[5];\r
+ __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */\r
+} SCB_Type;\r
+\r
+/* SCB CPUID Register Definitions */\r
+#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */\r
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */\r
+\r
+#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */\r
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */\r
+\r
+#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */\r
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */\r
+\r
+#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */\r
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */\r
+\r
+#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */\r
+#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */\r
+\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */\r
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */\r
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */\r
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */\r
+\r
+#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */\r
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */\r
+\r
+#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */\r
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */\r
+\r
+#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */\r
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */\r
+\r
+#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */\r
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */\r
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */\r
+\r
+#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */\r
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */\r
+\r
+#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */\r
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */\r
+\r
+/* SCB Vector Table Offset Register Definitions */\r
+#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */\r
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */\r
+\r
+/* SCB Application Interrupt and Reset Control Register Definitions */\r
+#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */\r
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */\r
+\r
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */\r
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
+\r
+#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */\r
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */\r
+\r
+#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */\r
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */\r
+\r
+#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */\r
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */\r
+\r
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
+\r
+#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */\r
+#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */\r
+\r
+/* SCB System Control Register Definitions */\r
+#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */\r
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */\r
+\r
+#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */\r
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */\r
+\r
+#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */\r
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */\r
+\r
+/* SCB Configuration Control Register Definitions */\r
+#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */\r
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */\r
+\r
+#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */\r
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */\r
+\r
+#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */\r
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */\r
+\r
+#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */\r
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */\r
+\r
+#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */\r
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */\r
+\r
+#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */\r
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */\r
+\r
+/* SCB System Handler Control and State Register Definitions */\r
+#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */\r
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */\r
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */\r
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */\r
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */\r
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */\r
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */\r
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */\r
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */\r
+\r
+#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */\r
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */\r
+\r
+#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */\r
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */\r
+\r
+#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */\r
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */\r
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */\r
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */\r
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */\r
+\r
+/* SCB Configurable Fault Status Registers Definitions */\r
+#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */\r
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */\r
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */\r
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\r
+\r
+/* SCB Hard Fault Status Registers Definitions */\r
+#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */\r
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */\r
+\r
+#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */\r
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */\r
+\r
+#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */\r
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */\r
+\r
+/* SCB Debug Fault Status Register Definitions */\r
+#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */\r
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */\r
+\r
+#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */\r
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */\r
+\r
+#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */\r
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */\r
+\r
+#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */\r
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */\r
+\r
+#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */\r
+#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */\r
+\r
+/*@} end of group CMSIS_SCB */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\r
+ \brief Type definitions for the System Control and ID Register not in the SCB\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the System Control and ID Register not in the SCB.\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t RESERVED0[1];\r
+ __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */\r
+ __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */\r
+} SCnSCB_Type;\r
+\r
+/* Interrupt Controller Type Register Definitions */\r
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */\r
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */\r
+\r
+/* Auxiliary Control Register Definitions */\r
+#define SCnSCB_ACTLR_DISOOFP_Pos 9 /*!< ACTLR: DISOOFP Position */\r
+#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */\r
+\r
+#define SCnSCB_ACTLR_DISFPCA_Pos 8 /*!< ACTLR: DISFPCA Position */\r
+#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */\r
+\r
+#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */\r
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */\r
+\r
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */\r
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */\r
+\r
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */\r
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */\r
+\r
+/*@} end of group CMSIS_SCnotSCB */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)\r
+ \brief Type definitions for the System Timer Registers.\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the System Timer (SysTick).\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */\r
+ __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */\r
+ __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */\r
+ __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */\r
+} SysTick_Type;\r
+\r
+/* SysTick Control / Status Register Definitions */\r
+#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */\r
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */\r
+\r
+#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */\r
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */\r
+\r
+#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */\r
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */\r
+\r
+#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */\r
+#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */\r
+\r
+/* SysTick Reload Register Definitions */\r
+#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */\r
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */\r
+\r
+/* SysTick Current Register Definitions */\r
+#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */\r
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */\r
+\r
+/* SysTick Calibration Register Definitions */\r
+#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */\r
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */\r
+\r
+#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */\r
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */\r
+\r
+#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */\r
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */\r
+\r
+/*@} end of group CMSIS_SysTick */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)\r
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).\r
+ */\r
+typedef struct\r
+{\r
+ __O union\r
+ {\r
+ __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */\r
+ __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */\r
+ __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */\r
+ } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */\r
+ uint32_t RESERVED0[864];\r
+ __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */\r
+ uint32_t RESERVED1[15];\r
+ __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */\r
+ uint32_t RESERVED2[15];\r
+ __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */\r
+} ITM_Type;\r
+\r
+/* ITM Trace Privilege Register Definitions */\r
+#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */\r
+#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */\r
+\r
+/* ITM Trace Control Register Definitions */\r
+#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */\r
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */\r
+\r
+#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */\r
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */\r
+\r
+#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */\r
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */\r
+\r
+#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */\r
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */\r
+\r
+#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */\r
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */\r
+\r
+#define ITM_TCR_TXENA_Pos 3 /*!< ITM TCR: TXENA Position */\r
+#define ITM_TCR_TXENA_Msk (1UL << ITM_TCR_TXENA_Pos) /*!< ITM TCR: TXENA Mask */\r
+\r
+#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */\r
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */\r
+\r
+#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */\r
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */\r
+\r
+#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */\r
+#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_ITM */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)\r
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */\r
+ __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */\r
+ __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */\r
+ __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */\r
+ __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */\r
+ __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */\r
+ __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */\r
+ __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */\r
+ __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */\r
+ __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */\r
+ __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */\r
+ uint32_t RESERVED0[1];\r
+ __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */\r
+ __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */\r
+ __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */\r
+ uint32_t RESERVED1[1];\r
+ __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */\r
+ __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */\r
+ __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */\r
+ uint32_t RESERVED2[1];\r
+ __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */\r
+ __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */\r
+ __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */\r
+} DWT_Type;\r
+\r
+/* DWT Control Register Definitions */\r
+#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */\r
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */\r
+\r
+#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */\r
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */\r
+\r
+#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */\r
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */\r
+\r
+#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */\r
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */\r
+\r
+#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */\r
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */\r
+\r
+#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */\r
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */\r
+\r
+#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */\r
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */\r
+\r
+#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */\r
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */\r
+\r
+#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */\r
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */\r
+\r
+#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */\r
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */\r
+\r
+#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */\r
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */\r
+\r
+#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */\r
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */\r
+\r
+#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */\r
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */\r
+\r
+#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */\r
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */\r
+\r
+#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */\r
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */\r
+\r
+#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */\r
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */\r
+\r
+#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */\r
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */\r
+\r
+#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */\r
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */\r
+\r
+/* DWT CPI Count Register Definitions */\r
+#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */\r
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */\r
+\r
+/* DWT Exception Overhead Count Register Definitions */\r
+#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */\r
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */\r
+\r
+/* DWT Sleep Count Register Definitions */\r
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */\r
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */\r
+\r
+/* DWT LSU Count Register Definitions */\r
+#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */\r
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */\r
+\r
+/* DWT Folded-instruction Count Register Definitions */\r
+#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */\r
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */\r
+\r
+/* DWT Comparator Mask Register Definitions */\r
+#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */\r
+#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */\r
+\r
+/* DWT Comparator Function Register Definitions */\r
+#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */\r
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */\r
+\r
+#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */\r
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */\r
+\r
+#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */\r
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */\r
+\r
+#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */\r
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */\r
+\r
+#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */\r
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */\r
+\r
+#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */\r
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */\r
+\r
+#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */\r
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */\r
+\r
+#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */\r
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */\r
+\r
+#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */\r
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_DWT */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)\r
+ \brief Type definitions for the Trace Port Interface (TPI)\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the Trace Port Interface Register (TPI).\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */\r
+ __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */\r
+ uint32_t RESERVED0[2];\r
+ __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */\r
+ uint32_t RESERVED1[55];\r
+ __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */\r
+ uint32_t RESERVED2[131];\r
+ __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */\r
+ __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */\r
+ __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */\r
+ uint32_t RESERVED3[759];\r
+ __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */\r
+ __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */\r
+ __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */\r
+ uint32_t RESERVED4[1];\r
+ __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */\r
+ __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */\r
+ __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */\r
+ uint32_t RESERVED5[39];\r
+ __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */\r
+ __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */\r
+ uint32_t RESERVED7[8];\r
+ __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */\r
+ __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */\r
+} TPI_Type;\r
+\r
+/* TPI Asynchronous Clock Prescaler Register Definitions */\r
+#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */\r
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */\r
+\r
+/* TPI Selected Pin Protocol Register Definitions */\r
+#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */\r
+#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */\r
+\r
+/* TPI Formatter and Flush Status Register Definitions */\r
+#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */\r
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */\r
+\r
+#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */\r
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */\r
+\r
+#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */\r
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */\r
+\r
+#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */\r
+#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */\r
+\r
+/* TPI Formatter and Flush Control Register Definitions */\r
+#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */\r
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */\r
+\r
+#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */\r
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */\r
+\r
+/* TPI TRIGGER Register Definitions */\r
+#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */\r
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */\r
+\r
+/* TPI Integration ETM Data Register Definitions (FIFO0) */\r
+#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */\r
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */\r
+\r
+#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */\r
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */\r
+\r
+#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */\r
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */\r
+\r
+#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */\r
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */\r
+\r
+#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */\r
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */\r
+\r
+#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */\r
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */\r
+\r
+#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */\r
+#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */\r
+\r
+/* TPI ITATBCTR2 Register Definitions */\r
+#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */\r
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */\r
+\r
+/* TPI Integration ITM Data Register Definitions (FIFO1) */\r
+#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */\r
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */\r
+\r
+#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */\r
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */\r
+\r
+#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */\r
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */\r
+\r
+#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */\r
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */\r
+\r
+#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */\r
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */\r
+\r
+#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */\r
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */\r
+\r
+#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */\r
+#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */\r
+\r
+/* TPI ITATBCTR0 Register Definitions */\r
+#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */\r
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */\r
+\r
+/* TPI Integration Mode Control Register Definitions */\r
+#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */\r
+#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */\r
+\r
+/* TPI DEVID Register Definitions */\r
+#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */\r
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */\r
+\r
+#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */\r
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */\r
+\r
+#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */\r
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */\r
+\r
+#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */\r
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */\r
+\r
+#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */\r
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */\r
+\r
+#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */\r
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */\r
+\r
+/* TPI DEVTYPE Register Definitions */\r
+#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */\r
+#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */\r
+\r
+#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */\r
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_TPI */\r
+\r
+\r
+#if (__MPU_PRESENT == 1)\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)\r
+ \brief Type definitions for the Memory Protection Unit (MPU)\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the Memory Protection Unit (MPU).\r
+ */\r
+typedef struct\r
+{\r
+ __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */\r
+ __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */\r
+ __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */\r
+ __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */\r
+ __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */\r
+ __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */\r
+ __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */\r
+ __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */\r
+ __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */\r
+ __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */\r
+ __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */\r
+} MPU_Type;\r
+\r
+/* MPU Type Register */\r
+#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */\r
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */\r
+\r
+#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */\r
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */\r
+\r
+#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */\r
+#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */\r
+\r
+/* MPU Control Register */\r
+#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */\r
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */\r
+\r
+#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */\r
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */\r
+\r
+#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */\r
+#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */\r
+\r
+/* MPU Region Number Register */\r
+#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */\r
+#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */\r
+\r
+/* MPU Region Base Address Register */\r
+#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */\r
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */\r
+\r
+#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */\r
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */\r
+\r
+#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */\r
+#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */\r
+\r
+/* MPU Region Attribute and Size Register */\r
+#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */\r
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */\r
+\r
+#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */\r
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */\r
+\r
+#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */\r
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */\r
+\r
+#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */\r
+#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */\r
+\r
+/*@} end of group CMSIS_MPU */\r
+#endif\r
+\r
+\r
+#if (__FPU_PRESENT == 1)\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)\r
+ \brief Type definitions for the Floating Point Unit (FPU)\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the Floating Point Unit (FPU).\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t RESERVED0[1];\r
+ __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */\r
+ __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */\r
+ __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */\r
+ __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */\r
+ __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */\r
+} FPU_Type;\r
+\r
+/* Floating-Point Context Control Register */\r
+#define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */\r
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */\r
+\r
+#define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */\r
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */\r
+\r
+#define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */\r
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */\r
+\r
+#define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */\r
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */\r
+\r
+#define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */\r
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */\r
+\r
+#define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */\r
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */\r
+\r
+#define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */\r
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */\r
+\r
+#define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */\r
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */\r
+\r
+#define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */\r
+#define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */\r
+\r
+/* Floating-Point Context Address Register */\r
+#define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */\r
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */\r
+\r
+/* Floating-Point Default Status Control Register */\r
+#define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */\r
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */\r
+\r
+#define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */\r
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */\r
+\r
+#define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */\r
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */\r
+\r
+#define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */\r
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */\r
+\r
+/* Media and FP Feature Register 0 */\r
+#define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */\r
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */\r
+\r
+#define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */\r
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */\r
+\r
+#define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */\r
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */\r
+\r
+#define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */\r
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */\r
+\r
+#define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */\r
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */\r
+\r
+#define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */\r
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */\r
+\r
+#define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */\r
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */\r
+\r
+#define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */\r
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */\r
+\r
+/* Media and FP Feature Register 1 */\r
+#define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */\r
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */\r
+\r
+#define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */\r
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */\r
+\r
+#define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */\r
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */\r
+\r
+#define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */\r
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */\r
+\r
+/*@} end of group CMSIS_FPU */\r
+#endif\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)\r
+ \brief Type definitions for the Core Debug Registers\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the Core Debug Register (CoreDebug).\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */\r
+ __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */\r
+ __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */\r
+ __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */\r
+} CoreDebug_Type;\r
+\r
+/* Debug Halting Control and Status Register */\r
+#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */\r
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */\r
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */\r
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */\r
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */\r
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */\r
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */\r
+\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\r
+\r
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */\r
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */\r
+\r
+#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */\r
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */\r
+\r
+#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */\r
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r
+\r
+/* Debug Core Register Selector Register */\r
+#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */\r
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */\r
+\r
+#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */\r
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */\r
+\r
+/* Debug Exception and Monitor Control Register */\r
+#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */\r
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */\r
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */\r
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */\r
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */\r
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */\r
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */\r
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */\r
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */\r
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */\r
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */\r
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */\r
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r
+\r
+/*@} end of group CMSIS_CoreDebug */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_core_base Core Definitions\r
+ \brief Definitions for base addresses, unions, and structures.\r
+ @{\r
+ */\r
+\r
+/* Memory mapping of Cortex-M4 Hardware */\r
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */\r
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */\r
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */\r
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */\r
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */\r
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */\r
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */\r
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */\r
+\r
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */\r
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */\r
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */\r
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */\r
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */\r
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */\r
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */\r
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */\r
+\r
+#if (__MPU_PRESENT == 1)\r
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */\r
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */\r
+#endif\r
+\r
+#if (__FPU_PRESENT == 1)\r
+ #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */\r
+ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */\r
+#endif\r
+\r
+/*@} */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Hardware Abstraction Layer\r
+ Core Function Interface contains:\r
+ - Core NVIC Functions\r
+ - Core SysTick Functions\r
+ - Core Debug Functions\r
+ - Core Register Access Functions\r
+ ******************************************************************************/\r
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r
+*/\r
+\r
+\r
+\r
+/* ########################## NVIC functions #################################### */\r
+/** \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions\r
+ \brief Functions that manage interrupts and exceptions via the NVIC.\r
+ @{\r
+ */\r
+\r
+/** \brief Set Priority Grouping\r
+\r
+ The function sets the priority grouping field using the required unlock sequence.\r
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\r
+ Only values from 0..7 are used.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
+\r
+ \param [in] PriorityGroup Priority grouping field.\r
+ */\r
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r
+{\r
+ uint32_t reg_value;\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */\r
+\r
+ reg_value = SCB->AIRCR; /* read old register configuration */\r
+ reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */\r
+ reg_value = (reg_value |\r
+ ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |\r
+ (PriorityGroupTmp << 8)); /* Insert write key and priorty group */\r
+ SCB->AIRCR = reg_value;\r
+}\r
+\r
+\r
+/** \brief Get Priority Grouping\r
+\r
+ The function reads the priority grouping field from the NVIC Interrupt Controller.\r
+\r
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)\r
+{\r
+ return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */\r
+}\r
+\r
+\r
+/** \brief Enable External Interrupt\r
+\r
+ The function enables a device-specific interrupt in the NVIC interrupt controller.\r
+\r
+ \param [in] IRQn External interrupt number. Value cannot be negative.\r
+ */\r
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)\r
+{\r
+/* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */\r
+ NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */\r
+}\r
+\r
+\r
+/** \brief Disable External Interrupt\r
+\r
+ The function disables a device-specific interrupt in the NVIC interrupt controller.\r
+\r
+ \param [in] IRQn External interrupt number. Value cannot be negative.\r
+ */\r
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */\r
+}\r
+\r
+\r
+/** \brief Get Pending Interrupt\r
+\r
+ The function reads the pending register in the NVIC and returns the pending bit\r
+ for the specified interrupt.\r
+\r
+ \param [in] IRQn Interrupt number.\r
+ \r
+ \return 0 Interrupt status is not pending.\r
+ \return 1 Interrupt status is pending.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */\r
+}\r
+\r
+\r
+/** \brief Set Pending Interrupt\r
+\r
+ The function sets the pending bit of an external interrupt.\r
+\r
+ \param [in] IRQn Interrupt number. Value cannot be negative.\r
+ */\r
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */\r
+}\r
+\r
+\r
+/** \brief Clear Pending Interrupt\r
+\r
+ The function clears the pending bit of an external interrupt.\r
+\r
+ \param [in] IRQn External interrupt number. Value cannot be negative.\r
+ */\r
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */\r
+}\r
+\r
+\r
+/** \brief Get Active Interrupt\r
+\r
+ The function reads the active register in NVIC and returns the active bit.\r
+ \r
+ \param [in] IRQn Interrupt number.\r
+ \r
+ \return 0 Interrupt status is not active.\r
+ \return 1 Interrupt status is active.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)\r
+{\r
+ return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */\r
+}\r
+\r
+\r
+/** \brief Set Interrupt Priority\r
+\r
+ The function sets the priority of an interrupt. \r
+\r
+ \note The priority cannot be set for every core interrupt.\r
+\r
+ \param [in] IRQn Interrupt number. \r
+ \param [in] priority Priority to set.\r
+ */\r
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
+{\r
+ if(IRQn < 0) {\r
+ SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */\r
+ else {\r
+ NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */\r
+}\r
+\r
+\r
+/** \brief Get Interrupt Priority\r
+\r
+ The function reads the priority of an interrupt. The interrupt\r
+ number can be positive to specify an external (device specific)\r
+ interrupt, or negative to specify an internal (core) interrupt.\r
+\r
+\r
+ \param [in] IRQn Interrupt number.\r
+ \return Interrupt Priority. Value is aligned automatically to the implemented\r
+ priority bits of the microcontroller.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)\r
+{\r
+\r
+ if(IRQn < 0) {\r
+ return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */\r
+ else {\r
+ return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */\r
+}\r
+\r
+\r
+/** \brief Encode Priority\r
+\r
+ The function encodes the priority for an interrupt with the given priority group,\r
+ preemptive priority value, and subpriority value.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.\r
+\r
+ \param [in] PriorityGroup Used priority group.\r
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).\r
+ \param [in] SubPriority Subpriority value (starting from 0).\r
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;\r
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;\r
+\r
+ return (\r
+ ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |\r
+ ((SubPriority & ((1 << (SubPriorityBits )) - 1)))\r
+ );\r
+}\r
+\r
+\r
+/** \brief Decode Priority\r
+\r
+ The function decodes an interrupt priority value with a given priority group to\r
+ preemptive priority value and subpriority value.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.\r
+\r
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().\r
+ \param [in] PriorityGroup Used priority group.\r
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).\r
+ \param [out] pSubPriority Subpriority value (starting from 0).\r
+ */\r
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;\r
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;\r
+\r
+ *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);\r
+ *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);\r
+}\r
+\r
+\r
+/** \brief System Reset\r
+\r
+ The function initiates a system reset request to reset the MCU.\r
+ */\r
+__STATIC_INLINE void NVIC_SystemReset(void)\r
+{\r
+ __DSB(); /* Ensure all outstanding memory accesses included\r
+ buffered write are completed before reset */\r
+ SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |\r
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\r
+ SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */\r
+ __DSB(); /* Ensure completion of memory access */\r
+ while(1); /* wait until reset */\r
+}\r
+\r
+/*@} end of CMSIS_Core_NVICFunctions */\r
+\r
+\r
+\r
+/* ################################## SysTick function ############################################ */\r
+/** \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r
+ \brief Functions that configure the System.\r
+ @{\r
+ */\r
+\r
+#if (__Vendor_SysTickConfig == 0)\r
+\r
+/** \brief System Tick Configuration\r
+\r
+ The function initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
+ Counter is in free running mode to generate periodic interrupts. \r
+\r
+ \param [in] ticks Number of ticks between two interrupts.\r
+ \r
+ \return 0 Function succeeded.\r
+ \return 1 Function failed.\r
+ \r
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the \r
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> \r
+ must contain a vendor-specific implementation of this function.\r
+\r
+ */\r
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
+{\r
+ if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */\r
+\r
+ SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */\r
+ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */\r
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_TICKINT_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ return (0); /* Function successful */\r
+}\r
+\r
+#endif\r
+\r
+/*@} end of CMSIS_Core_SysTickFunctions */\r
+\r
+\r
+\r
+/* ##################################### Debug In/Output function ########################################### */\r
+/** \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_core_DebugFunctions ITM Functions\r
+ \brief Functions that access the ITM debug interface.\r
+ @{\r
+ */\r
+\r
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */\r
+#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */\r
+\r
+\r
+/** \brief ITM Send Character\r
+\r
+ The function transmits a character via the ITM channel 0, and\r
+ \li Just returns when no debugger is connected that has booked the output.\r
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.\r
+\r
+ \param [in] ch Character to transmit.\r
+ \r
+ \returns Character to transmit.\r
+ */\r
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)\r
+{\r
+ if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */\r
+ (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */\r
+ {\r
+ while (ITM->PORT[0].u32 == 0);\r
+ ITM->PORT[0].u8 = (uint8_t) ch;\r
+ }\r
+ return (ch);\r
+}\r
+\r
+\r
+/** \brief ITM Receive Character\r
+\r
+ The function inputs a character via the external variable \ref ITM_RxBuffer.\r
+\r
+ \return Received character.\r
+ \return -1 No character pending.\r
+ */\r
+__STATIC_INLINE int32_t ITM_ReceiveChar (void) {\r
+ int32_t ch = -1; /* no character available */\r
+\r
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {\r
+ ch = ITM_RxBuffer;\r
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */\r
+ }\r
+\r
+ return (ch);\r
+}\r
+\r
+\r
+/** \brief ITM Check Character\r
+\r
+ The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.\r
+\r
+ \return 0 No character available.\r
+ \return 1 Character available.\r
+ */\r
+__STATIC_INLINE int32_t ITM_CheckChar (void) {\r
+\r
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {\r
+ return (0); /* no character available */\r
+ } else {\r
+ return (1); /* character available */\r
+ }\r
+}\r
+\r
+/*@} end of CMSIS_core_DebugFunctions */\r
+\r
+#endif /* __CORE_CM4_H_DEPENDANT */\r
+\r
+#endif /* __CMSIS_GENERIC */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_cm4_simd.h\r
+ * @brief CMSIS Cortex-M4 SIMD Header File\r
+ * @version V3.00\r
+ * @date 19. January 2012\r
+ *\r
+ * @note\r
+ * Copyright (C) 2010-2012 ARM Limited. All rights reserved.\r
+ *\r
+ * @par\r
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M \r
+ * processor based microcontrollers. This file can be freely distributed \r
+ * within development tools that are supporting such ARM based processors. \r
+ *\r
+ * @par\r
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+ *\r
+ ******************************************************************************/\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif \r
+\r
+#ifndef __CORE_CM4_SIMD_H\r
+#define __CORE_CM4_SIMD_H\r
+\r
+\r
+/*******************************************************************************\r
+ * Hardware Abstraction Layer\r
+ ******************************************************************************/\r
+\r
+\r
+/* ################### Compiler specific Intrinsics ########################### */\r
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics\r
+ Access to dedicated SIMD instructions\r
+ @{\r
+*/\r
+\r
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/\r
+/* ARM armcc specific functions */\r
+\r
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/\r
+#define __SADD8 __sadd8\r
+#define __QADD8 __qadd8\r
+#define __SHADD8 __shadd8\r
+#define __UADD8 __uadd8\r
+#define __UQADD8 __uqadd8\r
+#define __UHADD8 __uhadd8\r
+#define __SSUB8 __ssub8\r
+#define __QSUB8 __qsub8\r
+#define __SHSUB8 __shsub8\r
+#define __USUB8 __usub8\r
+#define __UQSUB8 __uqsub8\r
+#define __UHSUB8 __uhsub8\r
+#define __SADD16 __sadd16\r
+#define __QADD16 __qadd16\r
+#define __SHADD16 __shadd16\r
+#define __UADD16 __uadd16\r
+#define __UQADD16 __uqadd16\r
+#define __UHADD16 __uhadd16\r
+#define __SSUB16 __ssub16\r
+#define __QSUB16 __qsub16\r
+#define __SHSUB16 __shsub16\r
+#define __USUB16 __usub16\r
+#define __UQSUB16 __uqsub16\r
+#define __UHSUB16 __uhsub16\r
+#define __SASX __sasx\r
+#define __QASX __qasx\r
+#define __SHASX __shasx\r
+#define __UASX __uasx\r
+#define __UQASX __uqasx\r
+#define __UHASX __uhasx\r
+#define __SSAX __ssax\r
+#define __QSAX __qsax\r
+#define __SHSAX __shsax\r
+#define __USAX __usax\r
+#define __UQSAX __uqsax\r
+#define __UHSAX __uhsax\r
+#define __USAD8 __usad8\r
+#define __USADA8 __usada8\r
+#define __SSAT16 __ssat16\r
+#define __USAT16 __usat16\r
+#define __UXTB16 __uxtb16\r
+#define __UXTAB16 __uxtab16\r
+#define __SXTB16 __sxtb16\r
+#define __SXTAB16 __sxtab16\r
+#define __SMUAD __smuad\r
+#define __SMUADX __smuadx\r
+#define __SMLAD __smlad\r
+#define __SMLADX __smladx\r
+#define __SMLALD __smlald\r
+#define __SMLALDX __smlaldx\r
+#define __SMUSD __smusd\r
+#define __SMUSDX __smusdx\r
+#define __SMLSD __smlsd\r
+#define __SMLSDX __smlsdx\r
+#define __SMLSLD __smlsld\r
+#define __SMLSLDX __smlsldx\r
+#define __SEL __sel\r
+#define __QADD __qadd\r
+#define __QSUB __qsub\r
+\r
+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \\r
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )\r
+\r
+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \\r
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )\r
+\r
+\r
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/\r
+\r
+\r
+\r
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/\r
+/* IAR iccarm specific functions */\r
+\r
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/\r
+#include <cmsis_iar.h>\r
+\r
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/\r
+\r
+\r
+\r
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/\r
+/* TI CCS specific functions */\r
+\r
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/\r
+#include <cmsis_ccs.h>\r
+\r
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/\r
+\r
+\r
+\r
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/\r
+/* GNU gcc specific functions */\r
+\r
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+#define __SSAT16(ARG1,ARG2) \\r
+({ \\r
+ uint32_t __RES, __ARG1 = (ARG1); \\r
+ __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \\r
+ __RES; \\r
+ })\r
+ \r
+#define __USAT16(ARG1,ARG2) \\r
+({ \\r
+ uint32_t __RES, __ARG1 = (ARG1); \\r
+ __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \\r
+ __RES; \\r
+ })\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+#define __SMLALD(ARG1,ARG2,ARG3) \\r
+({ \\r
+ uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \\r
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \\r
+ (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \\r
+ })\r
+\r
+#define __SMLALDX(ARG1,ARG2,ARG3) \\r
+({ \\r
+ uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \\r
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \\r
+ (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \\r
+ })\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+#define __SMLSLD(ARG1,ARG2,ARG3) \\r
+({ \\r
+ uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \\r
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \\r
+ (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \\r
+ })\r
+\r
+#define __SMLSLDX(ARG1,ARG2,ARG3) \\r
+({ \\r
+ uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \\r
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \\r
+ (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \\r
+ })\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+#define __PKHBT(ARG1,ARG2,ARG3) \\r
+({ \\r
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \\r
+ __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \\r
+ __RES; \\r
+ })\r
+\r
+#define __PKHTB(ARG1,ARG2,ARG3) \\r
+({ \\r
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \\r
+ if (ARG3 == 0) \\r
+ __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \\r
+ else \\r
+ __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \\r
+ __RES; \\r
+ })\r
+\r
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/\r
+\r
+\r
+\r
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/\r
+/* TASKING carm specific functions */\r
+\r
+\r
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/\r
+/* not yet supported */\r
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/\r
+\r
+\r
+#endif\r
+\r
+/*@} end of group CMSIS_SIMD_intrinsics */\r
+\r
+\r
+#endif /* __CORE_CM4_SIMD_H */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_cmFunc.h\r
+ * @brief CMSIS Cortex-M Core Function Access Header File\r
+ * @version V3.00\r
+ * @date 19. January 2012\r
+ *\r
+ * @note\r
+ * Copyright (C) 2009-2012 ARM Limited. All rights reserved.\r
+ *\r
+ * @par\r
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M \r
+ * processor based microcontrollers. This file can be freely distributed \r
+ * within development tools that are supporting such ARM based processors. \r
+ *\r
+ * @par\r
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+ *\r
+ ******************************************************************************/\r
+\r
+#ifndef __CORE_CMFUNC_H\r
+#define __CORE_CMFUNC_H\r
+\r
+\r
+/* ########################### Core Function Access ########################### */\r
+/** \ingroup CMSIS_Core_FunctionInterface \r
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions\r
+ @{\r
+ */\r
+\r
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/\r
+/* ARM armcc specific functions */\r
+\r
+#if (__ARMCC_VERSION < 400677)\r
+ #error "Please use ARM Compiler Toolchain V4.0.677 or later!"\r
+#endif\r
+\r
+/* intrinsic void __enable_irq(); */\r
+/* intrinsic void __disable_irq(); */\r
+\r
+/** \brief Get Control Register\r
+\r
+ This function returns the content of the Control Register.\r
+\r
+ \return Control Register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_CONTROL(void)\r
+{\r
+ register uint32_t __regControl __ASM("control");\r
+ return(__regControl);\r
+}\r
+\r
+\r
+/** \brief Set Control Register\r
+\r
+ This function writes the given value to the Control Register.\r
+\r
+ \param [in] control Control Register value to set\r
+ */\r
+__STATIC_INLINE void __set_CONTROL(uint32_t control)\r
+{\r
+ register uint32_t __regControl __ASM("control");\r
+ __regControl = control;\r
+}\r
+\r
+\r
+/** \brief Get IPSR Register\r
+\r
+ This function returns the content of the IPSR Register.\r
+\r
+ \return IPSR Register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_IPSR(void)\r
+{\r
+ register uint32_t __regIPSR __ASM("ipsr");\r
+ return(__regIPSR);\r
+}\r
+\r
+\r
+/** \brief Get APSR Register\r
+\r
+ This function returns the content of the APSR Register.\r
+\r
+ \return APSR Register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_APSR(void)\r
+{\r
+ register uint32_t __regAPSR __ASM("apsr");\r
+ return(__regAPSR);\r
+}\r
+\r
+\r
+/** \brief Get xPSR Register\r
+\r
+ This function returns the content of the xPSR Register.\r
+\r
+ \return xPSR Register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_xPSR(void)\r
+{\r
+ register uint32_t __regXPSR __ASM("xpsr");\r
+ return(__regXPSR);\r
+}\r
+\r
+\r
+/** \brief Get Process Stack Pointer\r
+\r
+ This function returns the current value of the Process Stack Pointer (PSP).\r
+\r
+ \return PSP Register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_PSP(void)\r
+{\r
+ register uint32_t __regProcessStackPointer __ASM("psp");\r
+ return(__regProcessStackPointer);\r
+}\r
+\r
+\r
+/** \brief Set Process Stack Pointer\r
+\r
+ This function assigns the given value to the Process Stack Pointer (PSP).\r
+\r
+ \param [in] topOfProcStack Process Stack Pointer value to set\r
+ */\r
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)\r
+{\r
+ register uint32_t __regProcessStackPointer __ASM("psp");\r
+ __regProcessStackPointer = topOfProcStack;\r
+}\r
+\r
+\r
+/** \brief Get Main Stack Pointer\r
+\r
+ This function returns the current value of the Main Stack Pointer (MSP).\r
+\r
+ \return MSP Register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_MSP(void)\r
+{\r
+ register uint32_t __regMainStackPointer __ASM("msp");\r
+ return(__regMainStackPointer);\r
+}\r
+\r
+\r
+/** \brief Set Main Stack Pointer\r
+\r
+ This function assigns the given value to the Main Stack Pointer (MSP).\r
+\r
+ \param [in] topOfMainStack Main Stack Pointer value to set\r
+ */\r
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)\r
+{\r
+ register uint32_t __regMainStackPointer __ASM("msp");\r
+ __regMainStackPointer = topOfMainStack;\r
+}\r
+\r
+\r
+/** \brief Get Priority Mask\r
+\r
+ This function returns the current state of the priority mask bit from the Priority Mask Register.\r
+\r
+ \return Priority Mask value\r
+ */\r
+__STATIC_INLINE uint32_t __get_PRIMASK(void)\r
+{\r
+ register uint32_t __regPriMask __ASM("primask");\r
+ return(__regPriMask);\r
+}\r
+\r
+\r
+/** \brief Set Priority Mask\r
+\r
+ This function assigns the given value to the Priority Mask Register.\r
+\r
+ \param [in] priMask Priority Mask\r
+ */\r
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)\r
+{\r
+ register uint32_t __regPriMask __ASM("primask");\r
+ __regPriMask = (priMask);\r
+}\r
+ \r
+\r
+#if (__CORTEX_M >= 0x03)\r
+\r
+/** \brief Enable FIQ\r
+\r
+ This function enables FIQ interrupts by clearing the F-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+#define __enable_fault_irq __enable_fiq\r
+\r
+\r
+/** \brief Disable FIQ\r
+\r
+ This function disables FIQ interrupts by setting the F-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+#define __disable_fault_irq __disable_fiq\r
+\r
+\r
+/** \brief Get Base Priority\r
+\r
+ This function returns the current value of the Base Priority register.\r
+\r
+ \return Base Priority register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_BASEPRI(void)\r
+{\r
+ register uint32_t __regBasePri __ASM("basepri");\r
+ return(__regBasePri);\r
+}\r
+\r
+\r
+/** \brief Set Base Priority\r
+\r
+ This function assigns the given value to the Base Priority register.\r
+\r
+ \param [in] basePri Base Priority value to set\r
+ */\r
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)\r
+{\r
+ register uint32_t __regBasePri __ASM("basepri");\r
+ __regBasePri = (basePri & 0xff);\r
+}\r
+ \r
+\r
+/** \brief Get Fault Mask\r
+\r
+ This function returns the current value of the Fault Mask register.\r
+\r
+ \return Fault Mask register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)\r
+{\r
+ register uint32_t __regFaultMask __ASM("faultmask");\r
+ return(__regFaultMask);\r
+}\r
+\r
+\r
+/** \brief Set Fault Mask\r
+\r
+ This function assigns the given value to the Fault Mask register.\r
+\r
+ \param [in] faultMask Fault Mask value to set\r
+ */\r
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)\r
+{\r
+ register uint32_t __regFaultMask __ASM("faultmask");\r
+ __regFaultMask = (faultMask & (uint32_t)1);\r
+}\r
+\r
+#endif /* (__CORTEX_M >= 0x03) */\r
+\r
+\r
+#if (__CORTEX_M == 0x04)\r
+\r
+/** \brief Get FPSCR\r
+\r
+ This function returns the current value of the Floating Point Status/Control register.\r
+\r
+ \return Floating Point Status/Control register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_FPSCR(void)\r
+{\r
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\r
+ register uint32_t __regfpscr __ASM("fpscr");\r
+ return(__regfpscr);\r
+#else\r
+ return(0);\r
+#endif\r
+}\r
+\r
+\r
+/** \brief Set FPSCR\r
+\r
+ This function assigns the given value to the Floating Point Status/Control register.\r
+\r
+ \param [in] fpscr Floating Point Status/Control value to set\r
+ */\r
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)\r
+{\r
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\r
+ register uint32_t __regfpscr __ASM("fpscr");\r
+ __regfpscr = (fpscr);\r
+#endif\r
+}\r
+\r
+#endif /* (__CORTEX_M == 0x04) */\r
+\r
+\r
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/\r
+/* IAR iccarm specific functions */\r
+\r
+#include <cmsis_iar.h>\r
+\r
+\r
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/\r
+/* TI CCS specific functions */\r
+\r
+#include <cmsis_ccs.h>\r
+\r
+\r
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/\r
+/* GNU gcc specific functions */\r
+\r
+/** \brief Enable IRQ Interrupts\r
+\r
+ This function enables IRQ interrupts by clearing the I-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)\r
+{\r
+ __ASM volatile ("cpsie i");\r
+}\r
+\r
+\r
+/** \brief Disable IRQ Interrupts\r
+\r
+ This function disables IRQ interrupts by setting the I-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)\r
+{\r
+ __ASM volatile ("cpsid i");\r
+}\r
+\r
+\r
+/** \brief Get Control Register\r
+\r
+ This function returns the content of the Control Register.\r
+\r
+ \return Control Register value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, control" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Set Control Register\r
+\r
+ This function writes the given value to the Control Register.\r
+\r
+ \param [in] control Control Register value to set\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)\r
+{\r
+ __ASM volatile ("MSR control, %0" : : "r" (control) );\r
+}\r
+\r
+\r
+/** \brief Get IPSR Register\r
+\r
+ This function returns the content of the IPSR Register.\r
+\r
+ \return IPSR Register value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Get APSR Register\r
+\r
+ This function returns the content of the APSR Register.\r
+\r
+ \return APSR Register value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Get xPSR Register\r
+\r
+ This function returns the content of the xPSR Register.\r
+\r
+ \return xPSR Register value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Get Process Stack Pointer\r
+\r
+ This function returns the current value of the Process Stack Pointer (PSP).\r
+\r
+ \return PSP Register value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)\r
+{\r
+ register uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, psp\n" : "=r" (result) );\r
+ return(result);\r
+}\r
+ \r
+\r
+/** \brief Set Process Stack Pointer\r
+\r
+ This function assigns the given value to the Process Stack Pointer (PSP).\r
+\r
+ \param [in] topOfProcStack Process Stack Pointer value to set\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)\r
+{\r
+ __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) );\r
+}\r
+\r
+\r
+/** \brief Get Main Stack Pointer\r
+\r
+ This function returns the current value of the Main Stack Pointer (MSP).\r
+\r
+ \return MSP Register value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)\r
+{\r
+ register uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, msp\n" : "=r" (result) );\r
+ return(result);\r
+}\r
+ \r
+\r
+/** \brief Set Main Stack Pointer\r
+\r
+ This function assigns the given value to the Main Stack Pointer (MSP).\r
+\r
+ \param [in] topOfMainStack Main Stack Pointer value to set\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)\r
+{\r
+ __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) );\r
+}\r
+\r
+\r
+/** \brief Get Priority Mask\r
+\r
+ This function returns the current state of the priority mask bit from the Priority Mask Register.\r
+\r
+ \return Priority Mask value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Set Priority Mask\r
+\r
+ This function assigns the given value to the Priority Mask Register.\r
+\r
+ \param [in] priMask Priority Mask\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)\r
+{\r
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) );\r
+}\r
+ \r
+\r
+#if (__CORTEX_M >= 0x03)\r
+\r
+/** \brief Enable FIQ\r
+\r
+ This function enables FIQ interrupts by clearing the F-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)\r
+{\r
+ __ASM volatile ("cpsie f");\r
+}\r
+\r
+\r
+/** \brief Disable FIQ\r
+\r
+ This function disables FIQ interrupts by setting the F-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)\r
+{\r
+ __ASM volatile ("cpsid f");\r
+}\r
+\r
+\r
+/** \brief Get Base Priority\r
+\r
+ This function returns the current value of the Base Priority register.\r
+\r
+ \return Base Priority register value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Set Base Priority\r
+\r
+ This function assigns the given value to the Base Priority register.\r
+\r
+ \param [in] basePri Base Priority value to set\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)\r
+{\r
+ __ASM volatile ("MSR basepri, %0" : : "r" (value) );\r
+}\r
+\r
+\r
+/** \brief Get Fault Mask\r
+\r
+ This function returns the current value of the Fault Mask register.\r
+\r
+ \return Fault Mask register value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Set Fault Mask\r
+\r
+ This function assigns the given value to the Fault Mask register.\r
+\r
+ \param [in] faultMask Fault Mask value to set\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)\r
+{\r
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );\r
+}\r
+\r
+#endif /* (__CORTEX_M >= 0x03) */\r
+\r
+\r
+#if (__CORTEX_M == 0x04)\r
+\r
+/** \brief Get FPSCR\r
+\r
+ This function returns the current value of the Floating Point Status/Control register.\r
+\r
+ \return Floating Point Status/Control register value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)\r
+{\r
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );\r
+ return(result);\r
+#else\r
+ return(0);\r
+#endif\r
+}\r
+\r
+\r
+/** \brief Set FPSCR\r
+\r
+ This function assigns the given value to the Floating Point Status/Control register.\r
+\r
+ \param [in] fpscr Floating Point Status/Control value to set\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)\r
+{\r
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\r
+ __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) );\r
+#endif\r
+}\r
+\r
+#endif /* (__CORTEX_M == 0x04) */\r
+\r
+\r
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/\r
+/* TASKING carm specific functions */\r
+\r
+/*\r
+ * The CMSIS functions have been implemented as intrinsics in the compiler.\r
+ * Please use "carm -?i" to get an up to date list of all instrinsics,\r
+ * Including the CMSIS ones.\r
+ */\r
+\r
+#endif\r
+\r
+/*@} end of CMSIS_Core_RegAccFunctions */\r
+\r
+\r
+#endif /* __CORE_CMFUNC_H */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_cmInstr.h\r
+ * @brief CMSIS Cortex-M Core Instruction Access Header File\r
+ * @version V3.00\r
+ * @date 07. February 2012\r
+ *\r
+ * @note\r
+ * Copyright (C) 2009-2012 ARM Limited. All rights reserved.\r
+ *\r
+ * @par\r
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M\r
+ * processor based microcontrollers. This file can be freely distributed\r
+ * within development tools that are supporting such ARM based processors.\r
+ *\r
+ * @par\r
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+ *\r
+ ******************************************************************************/\r
+\r
+#ifndef __CORE_CMINSTR_H\r
+#define __CORE_CMINSTR_H\r
+\r
+\r
+/* ########################## Core Instruction Access ######################### */\r
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface\r
+ Access to dedicated instructions\r
+ @{\r
+*/\r
+\r
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/\r
+/* ARM armcc specific functions */\r
+\r
+#if (__ARMCC_VERSION < 400677)\r
+ #error "Please use ARM Compiler Toolchain V4.0.677 or later!"\r
+#endif\r
+\r
+\r
+/** \brief No Operation\r
+\r
+ No Operation does nothing. This instruction can be used for code alignment purposes.\r
+ */\r
+#define __NOP __nop\r
+\r
+\r
+/** \brief Wait For Interrupt\r
+\r
+ Wait For Interrupt is a hint instruction that suspends execution\r
+ until one of a number of events occurs.\r
+ */\r
+#define __WFI __wfi\r
+\r
+\r
+/** \brief Wait For Event\r
+\r
+ Wait For Event is a hint instruction that permits the processor to enter\r
+ a low-power state until one of a number of events occurs.\r
+ */\r
+#define __WFE __wfe\r
+\r
+\r
+/** \brief Send Event\r
+\r
+ Send Event is a hint instruction. It causes an event to be signaled to the CPU.\r
+ */\r
+#define __SEV __sev\r
+\r
+\r
+/** \brief Instruction Synchronization Barrier\r
+\r
+ Instruction Synchronization Barrier flushes the pipeline in the processor,\r
+ so that all instructions following the ISB are fetched from cache or\r
+ memory, after the instruction has been completed.\r
+ */\r
+#define __ISB() __isb(0xF)\r
+\r
+\r
+/** \brief Data Synchronization Barrier\r
+\r
+ This function acts as a special kind of Data Memory Barrier.\r
+ It completes when all explicit memory accesses before this instruction complete.\r
+ */\r
+#define __DSB() __dsb(0xF)\r
+\r
+\r
+/** \brief Data Memory Barrier\r
+\r
+ This function ensures the apparent order of the explicit memory operations before\r
+ and after the instruction, without ensuring their completion.\r
+ */\r
+#define __DMB() __dmb(0xF)\r
+\r
+\r
+/** \brief Reverse byte order (32 bit)\r
+\r
+ This function reverses the byte order in integer value.\r
+\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+#define __REV __rev\r
+\r
+\r
+/** \brief Reverse byte order (16 bit)\r
+\r
+ This function reverses the byte order in two unsigned short values.\r
+\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)\r
+{\r
+ rev16 r0, r0\r
+ bx lr\r
+}\r
+\r
+\r
+/** \brief Reverse byte order in signed short value\r
+\r
+ This function reverses the byte order in a signed short value with sign extension to integer.\r
+\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)\r
+{\r
+ revsh r0, r0\r
+ bx lr\r
+}\r
+\r
+\r
+/** \brief Rotate Right in unsigned value (32 bit)\r
+\r
+ This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.\r
+\r
+ \param [in] value Value to rotate\r
+ \param [in] value Number of Bits to rotate\r
+ \return Rotated value\r
+ */\r
+#define __ROR __ror\r
+\r
+\r
+#if (__CORTEX_M >= 0x03)\r
+\r
+/** \brief Reverse bit order of value\r
+\r
+ This function reverses the bit order of the given value.\r
+\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+#define __RBIT __rbit\r
+\r
+\r
+/** \brief LDR Exclusive (8 bit)\r
+\r
+ This function performs a exclusive LDR command for 8 bit value.\r
+\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint8_t at (*ptr)\r
+ */\r
+#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))\r
+\r
+\r
+/** \brief LDR Exclusive (16 bit)\r
+\r
+ This function performs a exclusive LDR command for 16 bit values.\r
+\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint16_t at (*ptr)\r
+ */\r
+#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))\r
+\r
+\r
+/** \brief LDR Exclusive (32 bit)\r
+\r
+ This function performs a exclusive LDR command for 32 bit values.\r
+\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint32_t at (*ptr)\r
+ */\r
+#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))\r
+\r
+\r
+/** \brief STR Exclusive (8 bit)\r
+\r
+ This function performs a exclusive STR command for 8 bit values.\r
+\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+#define __STREXB(value, ptr) __strex(value, ptr)\r
+\r
+\r
+/** \brief STR Exclusive (16 bit)\r
+\r
+ This function performs a exclusive STR command for 16 bit values.\r
+\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+#define __STREXH(value, ptr) __strex(value, ptr)\r
+\r
+\r
+/** \brief STR Exclusive (32 bit)\r
+\r
+ This function performs a exclusive STR command for 32 bit values.\r
+\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+#define __STREXW(value, ptr) __strex(value, ptr)\r
+\r
+\r
+/** \brief Remove the exclusive lock\r
+\r
+ This function removes the exclusive lock which is created by LDREX.\r
+\r
+ */\r
+#define __CLREX __clrex\r
+\r
+\r
+/** \brief Signed Saturate\r
+\r
+ This function saturates a signed value.\r
+\r
+ \param [in] value Value to be saturated\r
+ \param [in] sat Bit position to saturate to (1..32)\r
+ \return Saturated value\r
+ */\r
+#define __SSAT __ssat\r
+\r
+\r
+/** \brief Unsigned Saturate\r
+\r
+ This function saturates an unsigned value.\r
+\r
+ \param [in] value Value to be saturated\r
+ \param [in] sat Bit position to saturate to (0..31)\r
+ \return Saturated value\r
+ */\r
+#define __USAT __usat\r
+\r
+\r
+/** \brief Count leading zeros\r
+\r
+ This function counts the number of leading zeros of a data value.\r
+\r
+ \param [in] value Value to count the leading zeros\r
+ \return number of leading zeros in value\r
+ */\r
+#define __CLZ __clz\r
+\r
+#endif /* (__CORTEX_M >= 0x03) */\r
+\r
+\r
+\r
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/\r
+/* IAR iccarm specific functions */\r
+\r
+#include <cmsis_iar.h>\r
+\r
+\r
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/\r
+/* TI CCS specific functions */\r
+\r
+#include <cmsis_ccs.h>\r
+\r
+\r
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/\r
+/* GNU gcc specific functions */\r
+\r
+/** \brief No Operation\r
+\r
+ No Operation does nothing. This instruction can be used for code alignment purposes.\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)\r
+{\r
+ __ASM volatile ("nop");\r
+}\r
+\r
+\r
+/** \brief Wait For Interrupt\r
+\r
+ Wait For Interrupt is a hint instruction that suspends execution\r
+ until one of a number of events occurs.\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)\r
+{\r
+ __ASM volatile ("wfi");\r
+}\r
+\r
+\r
+/** \brief Wait For Event\r
+\r
+ Wait For Event is a hint instruction that permits the processor to enter\r
+ a low-power state until one of a number of events occurs.\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)\r
+{\r
+ __ASM volatile ("wfe");\r
+}\r
+\r
+\r
+/** \brief Send Event\r
+\r
+ Send Event is a hint instruction. It causes an event to be signaled to the CPU.\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)\r
+{\r
+ __ASM volatile ("sev");\r
+}\r
+\r
+\r
+/** \brief Instruction Synchronization Barrier\r
+\r
+ Instruction Synchronization Barrier flushes the pipeline in the processor,\r
+ so that all instructions following the ISB are fetched from cache or\r
+ memory, after the instruction has been completed.\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)\r
+{\r
+ __ASM volatile ("isb");\r
+}\r
+\r
+\r
+/** \brief Data Synchronization Barrier\r
+\r
+ This function acts as a special kind of Data Memory Barrier.\r
+ It completes when all explicit memory accesses before this instruction complete.\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)\r
+{\r
+ __ASM volatile ("dsb");\r
+}\r
+\r
+\r
+/** \brief Data Memory Barrier\r
+\r
+ This function ensures the apparent order of the explicit memory operations before\r
+ and after the instruction, without ensuring their completion.\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)\r
+{\r
+ __ASM volatile ("dmb");\r
+}\r
+\r
+\r
+/** \brief Reverse byte order (32 bit)\r
+\r
+ This function reverses the byte order in integer value.\r
+\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Reverse byte order (16 bit)\r
+\r
+ This function reverses the byte order in two unsigned short values.\r
+\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Reverse byte order in signed short value\r
+\r
+ This function reverses the byte order in a signed short value with sign extension to integer.\r
+\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Rotate Right in unsigned value (32 bit)\r
+\r
+ This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.\r
+\r
+ \param [in] value Value to rotate\r
+ \param [in] value Number of Bits to rotate\r
+ \return Rotated value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)\r
+{\r
+\r
+ __ASM volatile ("ror %0, %0, %1" : "+r" (op1) : "r" (op2) );\r
+ return(op1);\r
+}\r
+\r
+\r
+#if (__CORTEX_M >= 0x03)\r
+\r
+/** \brief Reverse bit order of value\r
+\r
+ This function reverses the bit order of the given value.\r
+\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief LDR Exclusive (8 bit)\r
+\r
+ This function performs a exclusive LDR command for 8 bit value.\r
+\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint8_t at (*ptr)\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)\r
+{\r
+ uint8_t result;\r
+\r
+ __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief LDR Exclusive (16 bit)\r
+\r
+ This function performs a exclusive LDR command for 16 bit values.\r
+\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint16_t at (*ptr)\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)\r
+{\r
+ uint16_t result;\r
+\r
+ __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief LDR Exclusive (32 bit)\r
+\r
+ This function performs a exclusive LDR command for 32 bit values.\r
+\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint32_t at (*ptr)\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief STR Exclusive (8 bit)\r
+\r
+ This function performs a exclusive STR command for 8 bit values.\r
+\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("strexb %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief STR Exclusive (16 bit)\r
+\r
+ This function performs a exclusive STR command for 16 bit values.\r
+\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("strexh %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief STR Exclusive (32 bit)\r
+\r
+ This function performs a exclusive STR command for 32 bit values.\r
+\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("strex %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Remove the exclusive lock\r
+\r
+ This function removes the exclusive lock which is created by LDREX.\r
+\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)\r
+{\r
+ __ASM volatile ("clrex");\r
+}\r
+\r
+\r
+/** \brief Signed Saturate\r
+\r
+ This function saturates a signed value.\r
+\r
+ \param [in] value Value to be saturated\r
+ \param [in] sat Bit position to saturate to (1..32)\r
+ \return Saturated value\r
+ */\r
+#define __SSAT(ARG1,ARG2) \\r
+({ \\r
+ uint32_t __RES, __ARG1 = (ARG1); \\r
+ __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \\r
+ __RES; \\r
+ })\r
+\r
+\r
+/** \brief Unsigned Saturate\r
+\r
+ This function saturates an unsigned value.\r
+\r
+ \param [in] value Value to be saturated\r
+ \param [in] sat Bit position to saturate to (0..31)\r
+ \return Saturated value\r
+ */\r
+#define __USAT(ARG1,ARG2) \\r
+({ \\r
+ uint32_t __RES, __ARG1 = (ARG1); \\r
+ __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \\r
+ __RES; \\r
+ })\r
+\r
+\r
+/** \brief Count leading zeros\r
+\r
+ This function counts the number of leading zeros of a data value.\r
+\r
+ \param [in] value Value to count the leading zeros\r
+ \return number of leading zeros in value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)\r
+{\r
+ uint8_t result;\r
+\r
+ __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );\r
+ return(result);\r
+}\r
+\r
+#endif /* (__CORTEX_M >= 0x03) */\r
+\r
+\r
+\r
+\r
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/\r
+/* TASKING carm specific functions */\r
+\r
+/*\r
+ * The CMSIS functions have been implemented as intrinsics in the compiler.\r
+ * Please use "carm -?i" to get an up to date list of all intrinsics,\r
+ * Including the CMSIS ones.\r
+ */\r
+\r
+#endif\r
+\r
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */\r
+\r
+#endif /* __CORE_CMINSTR_H */\r
--- /dev/null
+* -------------------------------------------------------------------\r
+* Copyright (C) 2011 ARM Limited. All rights reserved. \r
+* \r
+* Date: 11 October 2011 \r
+* Revision: V3.00 \r
+* \r
+* Project: Cortex Microcontroller Software Interface Standard (CMSIS)\r
+* Title: Release Note for CMSIS\r
+*\r
+* -------------------------------------------------------------------\r
+\r
+\r
+NOTE - Open the index.html file to access CMSIS documentation\r
+\r
+\r
+The Cortex Microcontroller Software Interface Standard (CMSIS) provides a single standard across all \r
+Cortex-Mx processor series vendors. It enables code re-use and code sharing across software projects \r
+and reduces time-to-market for new embedded applications.\r
+\r
+CMSIS is released under the terms of the end user license agreement ("CMSIS END USER LICENCE AGREEMENT.pdf").\r
+Any user of the software package is bound to the terms and conditions of the end user license agreement.\r
+\r
+\r
+You will find the following sub-directories:\r
+\r
+Documentation - Contains CMSIS documentation.\r
+ \r
+DSP_Lib - MDK project files, Examples and source files etc.. to build the \r
+ CMSIS DSP Software Library for Cortex-M0, Cortex-M3, Cortex-M4 processors.\r
+\r
+Include - CMSIS Core Support and CMSIS DSP Include Files.\r
+\r
+Lib - CMSIS DSP Libraries.\r
+\r
+RTOS - CMSIS RTOS API template header file.\r
+\r
+SVD - CMSIS SVD Schema files and Conversion Utility.\r
--- /dev/null
+END USER LICENCE AGREEMENT FOR THE CORTEX MICROCONTROLLER SOFTWARE INTERFACE\r
+STANDARD (CMSIS) SPECIFICATION AND SOFTWARE\r
+\r
+THIS END USER LICENCE AGREEMENT ("LICENCE") IS A LEGAL AGREEMENT BETWEEN YOU (EITHER A\r
+SINGLE INDIVIDUAL, OR SINGLE LEGAL ENTITY) AND ARM LIMITED ("ARM") FOR THE USE OF THE\r
+CMSIS SPECIFICATION, EXAMPLE CODE, DSP LIBRARY SPECIFICATION AND DSP LIBRARY\r
+IMPLEMENTATION AS SUCH TERMS ARE DEFINED BELOW (COLLECTIVELY, THE "ARM\r
+DELIVERABLES"). ARM IS ONLY WILLING TO LICENSE THE ARM DELIVERABLES TO YOU ON CONDITION\r
+THAT YOU ACCEPT ALL OF THE TERMS IN THIS LICENCE. BY CLICKING "I AGREE", OR BY INSTALLING\r
+OR OTHERWISE USING OR COPYING THE ARM DELIVERABLES YOU INDICATE THAT YOU AGREE TO\r
+BE BOUND BY ALL THE TERMS OF THIS LICENCE. IF YOU DO NOT AGREE TO THE TERMS OF THIS\r
+LICENCE, ARM IS UNWILLING TO LICENSE YOU TO USE THE ARM DELIVERABLES AND YOU MAY NOT\r
+INSTALL, USE OR COPY THE ARM DELIVERABLES.\r
+\r
+"CMSIS Specification" means any documentation and C programming language files defining the application\r
+programming interface, naming and coding conventions of the Cortex Microcontroller Software Interface\r
+Standard (CMSIS) as well as the System View Description (SVD) documentation and associated XML schema\r
+file. Notwithstanding the foregoing, "CMSIS Specification" shall not include (i) the implementation of other\r
+published specifications referenced in the CMSIS Specification; (ii) any enabling technologies that may be\r
+necessary to make or use any product or portion thereof that complies with the CMSIS Specification, but are not\r
+themselves expressly set forth in the CMSIS Specification (e.g. compiler front ends, code generators, back ends,\r
+libraries or other compiler, assembler or linker technologies; validation or debug software or hardware;\r
+applications, operating system or driver software; RISC architecture; processor microarchitecture); (iii)\r
+maskworks and physical layouts of integrated circuit designs; or (iv) RTL or other high level representations of\r
+integrated circuit designs.\r
+\r
+"DSP Library Implementation" means any C programming language source code implementing the functionality\r
+of the digital signal processor (DSP) algorithms and the application programming interface as defined in the DSP\r
+Library Specification. The DSP Library Implementation makes use of CMSIS application programming interface\r
+and therefore is targeted at Cortex-M class processors.\r
+\r
+"DSP Library Specification" means the DSP library documentation and C programming language file defining the\r
+application programming interface of the DSP Library Implementation. Notwithstanding the foregoing, "DSP\r
+Library Specification" shall not include (i) the implementation of other published specifications referenced in the\r
+DSP Library Specification; (ii) any enabling technologies that may be necessary to make or use any product or\r
+portion thereof that complies with the DSP Library Specification, but are not themselves expressly set forth in the\r
+DSP Library Specification (e.g. compiler front ends, code generators, back ends, libraries or other compiler,\r
+assembler or linker technologies; validation or debug software or hardware; applications, operating system or\r
+driver software; RISC architecture; processor microarchitecture); (iii) maskworks and physical layouts of\r
+integrated circuit designs; or (iv) RTL or other high level representations of integrated circuit designs.\r
+\r
+"Example Code" means any files in C, C++ or ARM assembly programming languages, associated project and\r
+configuration files that demonstrate the usage of the CMSIS Specification, the DSP Library Specification and the\r
+DSP Library Implementation, for microprocessors or device specific software applications that are for use with\r
+microprocessors.\r
+\r
+1. LICENCE GRANTS.\r
+\r
+1.1 ARM hereby grants to you, subject to the terms and conditions of this Licence, a non-exclusive, nontransferable\r
+licence, to;\r
+\r
+(i) use and copy the CMSIS Specification for the purpose of developing, having developed, manufacturing,\r
+having manufactured, offering to sell, selling, supplying or otherwise distributing products that comply with the\r
+CMSIS Specification, provided that you preserve any copyright notices which are included with, or in, the CMSIS\r
+Specification and provided that you do not use ARM's name, logo or trademarks to market such products;\r
+\r
+(ii) use, copy, and modify (solely to the extent necessary to incorporate the whole or any part of the DSP Library\r
+Specification into your documentation), the DSP Library Specification, for the purpose of developing, having\r
+developed, manufacturing, having manufactured, offering to sell, selling, supplying or otherwise distributing\r
+products that comply with the DSP Library Specification, and distribute and have distributed any documentation\r
+created by or for you that has been derived from the DSP Library Specification with such products, provided that\r
+you preserve any copyright notices which are included with, or in, the DSP Library Specification and provided that\r
+you do not use ARM's name, logo or trademarks to market such products;\r
+\r
+(iii) use, copy, modify and sublicense the Example Code solely for the purpose of developing, having developed,\r
+manufacturing, having manufactured, offering to sell, selling, supplying or otherwise distributing products that\r
+comply with either or both the CMSIS Specification and the DSP Library Specification, provided that you preserve\r
+any copyright notices which are included with, or in, the Example Code and that you do not use ARM's name,\r
+logo or trademarks to market such products;\r
+\r
+(iv) use, copy and modify (provided that the logical functionality and the application programming interface of the\r
+DSP Library Implementation are maintained) the DSP Library Implementation, solely for the purposes of\r
+developing; (a) software applications for use with microprocessors manufactured or simulated under licence from\r
+ARM ("Software Applications"); and (b) tools that are designed to develop software programs for use with\r
+microprocessors manufactured or simulated under licence from ARM ("Tools"); and\r
+\r
+(v) subject to clause 1.1(vi) below; (a) distribute and sublicense the use of the DSP Library Implementation\r
+(including any modified forms thereof created under Clause 1.1(iv) above) in binary or source format, solely as\r
+incorporated into Software Library Applications and Tools to third parties; and (b) sublicense to such third parties\r
+the right to use and copy the Tools for the purposes of developing and distribute software programs for use with\r
+microprocessors manufactured or simulated under licence from ARM.\r
+\r
+(vi) CONDITIONS ON REDISTRIBUTION: If you choose to redistribute the whole or any part of the DSP Library\r
+Implementation as incorporated into Software Library Applications or Tools, you agree to; (a) ensure that the\r
+DSP Library Implementation is licensed for use only as part of Software Library Applications and Tools and only\r
+for use with microprocessors manufactured or simulated under licence from ARM; (b) not to use ARM's name,\r
+logo or trademarks to market Software Applications and Tools; and (c) include valid copyright notices on\r
+Software Applications and Tools, and preserve any copyright notices which are included with, or in, the DSP\r
+Library Implementation.\r
+\r
+2. RESTRICTIONS ON USE OF THE ARM DELIVERABLES.\r
+\r
+PERMITTED USERS: The ARM Deliverables shall be used only by you (either a single individual, or single legal\r
+entity) your employees, or by your on-site bona fide sub-contractors for whose acts and omissions you hereby\r
+agree to be responsible to ARM for to the same extent as you are for your employees, and provided always that\r
+such sub-contractors; (i) are contractually obligated to use the ARM Deliverables only for your benefit, and (ii)\r
+agree to assign all their work product and any rights they create therein in the supply of such work to you.\r
+COPYRIGHT AND RESERVATION OF RIGHTS: The ARM Deliverables are owned by ARM or its licensors and\r
+are protected by copyright and other intellectual property laws and international treaties. The ARM Deliverables\r
+are licensed not sold. Except as expressly licensed herein, you acquire no right, title or interest in the ARM\r
+Deliverables or any intellectual property therein. In no event shall the licences granted herein be construed as\r
+granting you, expressly or by implication, estoppels or otherwise, a licence to use any ARM technology except\r
+the ARM Deliverables.\r
+\r
+3. SUPPORT.\r
+\r
+ARM is not obligated to support the ARM Deliverables but may do so entirely at ARM's discretion.\r
+\r
+4. NO WARRANTY\r
+\r
+YOU AGREE THAT THE ARM DELIVERABLES ARE LICENSED "AS IS", AND THAT ARM EXPRESSLY\r
+DISCLAIMS ALL REPRESENTATIONS, WARRANTIES, CONDITIONS OR OTHER TERMS, EXPRESS,\r
+IMPLIED OR STATUTORY, INCLUDING WITHOUT LIMITATION THE IMPLIED WARRANTIES OF NONINFRINGEMENT,\r
+SATISFACTORY QUALITY, AND FITNESS FOR A PARTICULAR PURPOSE. THE ARM\r
+DELIVERABLES MAY CONTAIN ERRORS. ARM RESERVES THE RIGHT TO INCORPORATE\r
+MODIFICATIONS TO THE ARM DELIVERABLES IN LATER REVISIONS OF THEM, AND TO MAKE\r
+IMPROVEMENTS OR CHANGES IN THE ARM DELIVERABLES AT ANY TIME.\r
+\r
+5. LIMITATION OF LIABILITY.\r
+\r
+THE MAXIMUM LIABILITY OF ARM TO YOU IN AGGREGATE FOR ALL CLAIMS MADE AGAINST ARM IN\r
+CONTRACT, TORT OR OTHERWISE UNDER OR IN CONNECTION WITH THE SUBJECT MATTER OF THIS\r
+LICENCE SHALL NOT EXCEED THE GREATER OF (I) THE TOTAL OF SUMS PAID BY YOU TO ARM (IF\r
+ANY) FOR THIS LICENCE AND (II) US$10.00. THE LIMITATIONS, EXCLUSIONS AND DISCLAIMERS IN\r
+THIS LICENCE SHALL APPLY TO THE MAXIMUM EXTENT ALLOWED BY APPLICABLE LAW.\r
+\r
+6. U.S. GOVERNMENT END USERS.\r
+US Government Restrictions: Use, duplication, reproduction, release, modification, disclosure or transfer of this\r
+commercial product and accompanying documentation is restricted in accordance with the terms of this Licence.\r
+\r
+7. TERM AND TERMINATION.\r
+\r
+7.1 This Licence shall remain in force until terminated in accordance with the terms of Clause 7.2 or Clause 7.3\r
+below.\r
+\r
+7.2 Without prejudice to any of its other rights if you are in breach of any of the terms and conditions of this\r
+Licence then ARM may terminate this Licence immediately upon giving written notice to you. You may terminate\r
+this Licence at any time.\r
+\r
+7.3 This Licence shall immediately terminate and shall be unavailable to you if you or any party affiliated to you\r
+asserts any patents against ARM, ARM affiliates, third parties who have a valid licence from ARM for the ARM\r
+Deliverables, or any customers or distributors of any of them based upon a claim that your (or your affiliate)\r
+patent is Necessary to implement the CMSIS Specification or DSP Library Specification. In this Licence; (i)\r
+"affiliate" means any entity controlling, controlled by or under common control with a party (in fact or in law, via\r
+voting securities, management control or otherwise) and "affiliated" shall be construed accordingly; (ii) "assert"\r
+means to allege infringement in legal or administrative proceedings, or proceedings before any other competent\r
+trade, arbitral or international authority; (iii) "Necessary" means with respect to any claims of any patent, those\r
+claims which, without the appropriate permission of the patent owner, will be infringed when implementing the\r
+CMSIS Specification or DSP Library Specification because no alternative, commercially reasonable, noninfringing\r
+way of implementing the CMSIS Specification or DSP Library Specification is known.\r
+\r
+7.4 Upon termination of this Licence, you shall stop using the ARM Deliverables and destroy all copies of the\r
+ARM Deliverables in your possession. The provisions of clauses 5, 6, 7, and 8 shall survive termination of this\r
+Licence.\r
+\r
+8. GENERAL.\r
+\r
+This Licence is governed by English Law. Except where ARM agrees otherwise in a written contract signed by\r
+you and ARM, this is the only agreement between you and ARM relating to the ARM Deliverables and it may only\r
+be modified by written agreement between you and ARM. Except as expressly agreed in writing, this Licence\r
+may not be modified by purchase orders, advertising or other representation by any person. If any clause or\r
+sentence in this Licence is held by a court of law to be illegal or unenforceable the remaining provisions of this\r
+Licence shall not be affected thereby. The failure by ARM to enforce any of the provisions of this Licence, unless\r
+waived in writing, shall not constitute a waiver of ARM's rights to enforce such provision or any other provision of\r
+this Licence in the future. This Licence may not be assigned without the prior written consent of ARM.\r
+\r
+ARM contract reference LEC-PRE-00489\r
--- /dev/null
+/*\r
+ FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. \r
+ All rights reserved\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that has become a de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly and support the FreeRTOS *\r
+ * project by purchasing a FreeRTOS tutorial book, reference *\r
+ * manual, or both from: http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ * Thank you! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+\r
+ >>! NOTE: The modification to the GPL is included to allow you to distribute\r
+ >>! a combined work that includes FreeRTOS without being obliged to provide\r
+ >>! the source code for proprietary components outside of the FreeRTOS\r
+ >>! kernel.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available from the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong?" *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
+ license and Real Time Engineers Ltd. contact details.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
+ Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+/* FreeRTOS includes. */\r
+#include "FreeRTOS.h"\r
+\r
+/* Utility functions to implement run time stats on Cortex-M CPUs. The collected\r
+run time data can be viewed through the CLI interface. See the following URL for\r
+more information on run time stats:\r
+http://www.freertos.org/rtos-run-time-stats.html */\r
+\r
+/* Addresses of registers in the Cortex-M debug hardware. */\r
+#define rtsDWT_CYCCNT ( *( ( unsigned long * ) 0xE0001004 ) )\r
+#define rtsDWT_CONTROL ( *( ( unsigned long * ) 0xE0001000 ) )\r
+#define rtsSCB_DEMCR ( *( ( unsigned long * ) 0xE000EDFC ) )\r
+#define rtsTRCENA_BIT ( 0x01000000UL )\r
+#define rtsCOUNTER_ENABLE_BIT ( 0x01UL )\r
+\r
+/* Simple shift divide for scaling to avoid an overflow occurring too soon. The\r
+number of bits to shift depends on the clock speed. */\r
+#define runtimeSLOWER_CLOCK_SPEEDS ( 70000000UL )\r
+#define runtimeSHIFT_13 13\r
+#define runtimeOVERFLOW_BIT_13 ( 1UL << ( 32UL - runtimeSHIFT_13 ) )\r
+#define runtimeSHIFT_14 14\r
+#define runtimeOVERFLOW_BIT_14 ( 1UL << ( 32UL - runtimeSHIFT_14 ) )\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void vConfigureTimerForRunTimeStats( void )\r
+{\r
+ /* Enable TRCENA. */\r
+ rtsSCB_DEMCR = rtsSCB_DEMCR | rtsTRCENA_BIT;\r
+\r
+ /* Reset counter. */\r
+ rtsDWT_CYCCNT = 0;\r
+\r
+ /* Enable counter. */\r
+ rtsDWT_CONTROL = rtsDWT_CONTROL | rtsCOUNTER_ENABLE_BIT;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+uint32_t ulGetRunTimeCounterValue( void )\r
+{\r
+static unsigned long ulLastCounterValue = 0UL, ulOverflows = 0;\r
+unsigned long ulValueNow;\r
+\r
+ ulValueNow = rtsDWT_CYCCNT;\r
+\r
+ /* Has the value overflowed since it was last read. */\r
+ if( ulValueNow < ulLastCounterValue )\r
+ {\r
+ ulOverflows++;\r
+ }\r
+ ulLastCounterValue = ulValueNow;\r
+\r
+ /* Cannot use configCPU_CLOCK_HZ directly as it may itself not be a constant\r
+ but instead map to a variable that holds the clock speed. */\r
+\r
+ /* There is no prescale on the counter, so simulate in software. */\r
+ if( configCPU_CLOCK_HZ < runtimeSLOWER_CLOCK_SPEEDS )\r
+ {\r
+ ulValueNow >>= runtimeSHIFT_13;\r
+ ulValueNow += ( runtimeOVERFLOW_BIT_13 * ulOverflows );\r
+ }\r
+ else\r
+ {\r
+ ulValueNow >>= runtimeSHIFT_14;\r
+ ulValueNow += ( runtimeOVERFLOW_BIT_14 * ulOverflows );\r
+ }\r
+\r
+ return ulValueNow;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Autogenerated API include file for the Atmel Software Framework (ASF)\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef ASF_H\r
+#define ASF_H\r
+\r
+/*\r
+ * This file includes all API header files for the selected drivers from ASF.\r
+ * Note: There might be duplicate includes required by more than one driver.\r
+ *\r
+ * The file is automatically generated and will be re-written when\r
+ * running the ASF driver selector tool. Any changes will be discarded.\r
+ */\r
+\r
+// From module: Common SAM compiler driver\r
+#include <compiler.h>\r
+#include <status_codes.h>\r
+\r
+// From module: Ethernet MAC (GMAC)\r
+#include <gmac.h>\r
+\r
+// From module: Ethernet Physical Transceiver (ksz8051mnl)\r
+#include <ethernet_phy.h>\r
+\r
+// From module: Generic board support\r
+#include <board.h>\r
+\r
+// From module: IOPORT - General purpose I/O service\r
+#include <ioport.h>\r
+\r
+// From module: Interrupt management - SAM implementation\r
+#include <interrupt.h>\r
+\r
+// From module: PMC - Power Management Controller\r
+#include <pmc.h>\r
+#include <sleep.h>\r
+\r
+// From module: Part identification macros\r
+#include <parts.h>\r
+\r
+// From module: SAM FPU driver\r
+#include <fpu.h>\r
+\r
+// From module: SAM4E EK LED support enabled\r
+#include <led.h>\r
+\r
+// From module: SAM4E startup code\r
+#include <exceptions.h>\r
+\r
+// From module: System Clock Control - SAM4E implementation\r
+#include <sysclk.h>\r
+\r
+#endif // ASF_H\r
--- /dev/null
+/*\r
+ FreeRTOS V7.5.3 - Copyright (C) 2013 Real Time Engineers Ltd. \r
+ All rights reserved\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that has become a de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly and support the FreeRTOS *\r
+ * project by purchasing a FreeRTOS tutorial book, reference *\r
+ * manual, or both from: http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ * Thank you! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+\r
+ >>! NOTE: The modification to the GPL is included to allow you to distribute\r
+ >>! a combined work that includes FreeRTOS without being obliged to provide\r
+ >>! the source code for proprietary components outside of the FreeRTOS\r
+ >>! kernel.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available from the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong?" *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
+ license and Real Time Engineers Ltd. contact details.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
+ Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+\r
+#ifndef FREERTOS_CONFIG_H\r
+#define FREERTOS_CONFIG_H\r
+\r
+/* Atmel library includes. */\r
+#include <asf.h>\r
+\r
+/*-----------------------------------------------------------\r
+ * Application specific definitions.\r
+ *\r
+ * These definitions should be adjusted for your particular hardware and\r
+ * application requirements.\r
+ *\r
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\r
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.\r
+ *\r
+ * See http://www.freertos.org/a00110.html.\r
+ *----------------------------------------------------------*/\r
+\r
+#define configUSE_PREEMPTION 1\r
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1\r
+#define configUSE_IDLE_HOOK 0\r
+#define configUSE_TICK_HOOK 0\r
+#define configCPU_CLOCK_HZ ( ( unsigned long ) CHIP_FREQ_CPU_MAX )\r
+#define configTICK_RATE_HZ ( 1000 )\r
+#define configMAX_PRIORITIES ( 5 )\r
+#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 130 )\r
+#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 22800 ) )\r
+#define configMAX_TASK_NAME_LEN ( 10 )\r
+#define configUSE_TRACE_FACILITY 1\r
+#define configUSE_16_BIT_TICKS 0\r
+#define configIDLE_SHOULD_YIELD 1\r
+#define configUSE_MUTEXES 1\r
+#define configQUEUE_REGISTRY_SIZE 8\r
+#define configCHECK_FOR_STACK_OVERFLOW 2\r
+#define configUSE_RECURSIVE_MUTEXES 1\r
+#define configUSE_MALLOC_FAILED_HOOK 1\r
+#define configUSE_APPLICATION_TASK_TAG 0\r
+#define configUSE_COUNTING_SEMAPHORES 1\r
+\r
+/* Run time stats gathering definitions. */\r
+void vConfigureTimerForRunTimeStats( void );\r
+uint32_t ulGetRunTimeCounterValue( void );\r
+#define configGENERATE_RUN_TIME_STATS 1\r
+#define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() vConfigureTimerForRunTimeStats()\r
+#define portGET_RUN_TIME_COUNTER_VALUE() ulGetRunTimeCounterValue()\r
+\r
+/* This demo makes use of one or more example stats formatting functions. These\r
+format the raw data provided by the uxTaskGetSystemState() function in to human\r
+readable ASCII form. See the notes in the implementation of vTaskList() within\r
+FreeRTOS/Source/tasks.c for limitations. */\r
+#define configUSE_STATS_FORMATTING_FUNCTIONS 1\r
+\r
+/* Co-routine definitions. */\r
+#define configUSE_CO_ROUTINES 0\r
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )\r
+\r
+/* Software timer definitions. */\r
+#define configUSE_TIMERS 1\r
+#define configTIMER_TASK_PRIORITY ( 2 )\r
+#define configTIMER_QUEUE_LENGTH 5\r
+#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE * 2 )\r
+\r
+/* Set the following definitions to 1 to include the API function, or zero\r
+to exclude the API function. */\r
+#define INCLUDE_vTaskPrioritySet 1\r
+#define INCLUDE_uxTaskPriorityGet 1\r
+#define INCLUDE_vTaskDelete 1\r
+#define INCLUDE_vTaskCleanUpResources 1\r
+#define INCLUDE_vTaskSuspend 1\r
+#define INCLUDE_vTaskDelayUntil 1\r
+#define INCLUDE_vTaskDelay 1\r
+\r
+/* Cortex-M specific definitions. */\r
+#ifdef __NVIC_PRIO_BITS\r
+ /* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */\r
+ #define configPRIO_BITS __NVIC_PRIO_BITS\r
+#else\r
+ #define configPRIO_BITS 4 /* 15 priority levels */\r
+#endif\r
+\r
+/* The lowest interrupt priority that can be used in a call to a "set priority"\r
+function. */\r
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 0xf\r
+\r
+/* The highest interrupt priority that can be used by any interrupt service\r
+routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL\r
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER\r
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */\r
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 5\r
+\r
+/* Interrupt priorities used by the kernel port layer itself. These are generic\r
+to all Cortex-M ports, and do not rely on any particular library functions. */\r
+#define configKERNEL_INTERRUPT_PRIORITY ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )\r
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!\r
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */\r
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )\r
+\r
+/* Normal assert() semantics without relying on the provision of an assert.h\r
+header file. */\r
+extern void vAssertCalled( uint32_t ulLine, const char *pcFile );\r
+#define configASSERT( x ) if( ( x ) == 0 ) vAssertCalled( __LINE__, __FILE__ )\r
+\r
+/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS\r
+standard names. */\r
+#define xPortPendSVHandler PendSV_Handler\r
+#define vPortSVCHandler SVC_Handler\r
+#define xPortSysTickHandler SysTick_Handler\r
+\r
+/* MAC address configuration. In a deployed production system this would\r
+probably be read from an EEPROM. In the demo it is just hard coded. Make sure\r
+each node on the network has a unique MAC address. */\r
+#define configMAC_ADDR0 0x00\r
+#define configMAC_ADDR1 0x11\r
+#define configMAC_ADDR2 0x22\r
+#define configMAC_ADDR3 0x33\r
+#define configMAC_ADDR4 0x44\r
+#define configMAC_ADDR5 0x45\r
+\r
+/* Default IP address configuration. Used in ipconfigUSE_DNS is set to 0, or\r
+ipconfigUSE_DNS is set to 1 but a DNS server cannot be contacted. */\r
+#define configIP_ADDR0 172\r
+#define configIP_ADDR1 25\r
+#define configIP_ADDR2 218\r
+#define configIP_ADDR3 200\r
+\r
+/* Default gateway IP address configuration. Used in ipconfigUSE_DNS is set to\r
+0, or ipconfigUSE_DNS is set to 1 but a DNS server cannot be contacted. */\r
+#define configGATEWAY_ADDR0 172\r
+#define configGATEWAY_ADDR1 25\r
+#define configGATEWAY_ADDR2 218\r
+#define configGATEWAY_ADDR3 1\r
+\r
+/* Default DNS server configuration. OpenDNS addresses are 208.67.222.222 and\r
+208.67.220.220. Used in ipconfigUSE_DNS is set to 0, or ipconfigUSE_DNS is set\r
+to 1 but a DNS server cannot be contacted.*/\r
+#define configDNS_SERVER_ADDR0 208\r
+#define configDNS_SERVER_ADDR1 67\r
+#define configDNS_SERVER_ADDR2 222\r
+#define configDNS_SERVER_ADDR3 222\r
+\r
+/* Default netmask configuration. Used in ipconfigUSE_DNS is set to 0, or\r
+ipconfigUSE_DNS is set to 1 but a DNS server cannot be contacted. */\r
+#define configNET_MASK0 255\r
+#define configNET_MASK1 255\r
+#define configNET_MASK2 255\r
+#define configNET_MASK3 0\r
+\r
+/* The priority used by the Ethernet MAC driver interrupt. */\r
+#define configMAC_INTERRUPT_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY )\r
+\r
+/* Dimensions a buffer that can be used by the FreeRTOS+CLI command\r
+interpreter. See the FreeRTOS+CLI documentation for more information:\r
+http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_CLI/ */\r
+#define configCOMMAND_INT_MAX_OUTPUT_SIZE 1024\r
+\r
+/* If configINCLUDE_DEMO_DEBUG_STATS is set to one, then a few basic IP trace\r
+macros are defined to gather some UDP stack statistics that can then be viewed\r
+through the CLI interface. */\r
+#define configINCLUDE_DEMO_DEBUG_STATS 1\r
+\r
+#endif /* FREERTOS_CONFIG_H */\r
+\r
--- /dev/null
+/*\r
+ * FreeRTOS+UDP V1.0.2 (C) 2013 Real Time Engineers ltd.\r
+ * All rights reserved\r
+ *\r
+ * This file is part of the FreeRTOS+UDP distribution. The FreeRTOS+UDP license\r
+ * terms are different to the FreeRTOS license terms.\r
+ *\r
+ * FreeRTOS+UDP uses a dual license model that allows the software to be used \r
+ * under a standard GPL open source license, or a commercial license. The \r
+ * standard GPL license (unlike the modified GPL license under which FreeRTOS \r
+ * itself is distributed) requires that all software statically linked with \r
+ * FreeRTOS+UDP is also distributed under the same GPL V2 license terms. \r
+ * Details of both license options follow:\r
+ *\r
+ * - Open source licensing -\r
+ * FreeRTOS+UDP is a free download and may be used, modified, evaluated and\r
+ * distributed without charge provided the user adheres to version two of the\r
+ * GNU General Public License (GPL) and does not remove the copyright notice or\r
+ * this text. The GPL V2 text is available on the gnu.org web site, and on the\r
+ * following URL: http://www.FreeRTOS.org/gpl-2.0.txt.\r
+ *\r
+ * - Commercial licensing -\r
+ * Businesses and individuals that for commercial or other reasons cannot comply\r
+ * with the terms of the GPL V2 license must obtain a commercial license before\r
+ * incorporating FreeRTOS+UDP into proprietary software for distribution in any\r
+ * form. Commercial licenses can be purchased from http://shop.freertos.org/udp\r
+ * and do not require any source files to be changed.\r
+ *\r
+ * FreeRTOS+UDP is distributed in the hope that it will be useful. You cannot\r
+ * use FreeRTOS+UDP unless you agree that you use the software 'as is'.\r
+ * FreeRTOS+UDP is provided WITHOUT ANY WARRANTY; without even the implied\r
+ * warranties of NON-INFRINGEMENT, MERCHANTABILITY or FITNESS FOR A PARTICULAR\r
+ * PURPOSE. Real Time Engineers Ltd. disclaims all conditions and terms, be they\r
+ * implied, expressed, or statutory.\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://www.FreeRTOS.org/udp\r
+ *\r
+ */\r
+\r
+/*****************************************************************************\r
+ *\r
+ * See the following URL for configuration information.\r
+ * http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_UDP/UDP_IP_Configuration.shtml\r
+ *\r
+ *****************************************************************************/\r
+\r
+#ifndef FREERTOS_IP_CONFIG_H\r
+#define FREERTOS_IP_CONFIG_H\r
+\r
+/* The IP stack executes it its own task (although any application task can make\r
+use of its services through the published sockets API). ipconfigUDP_TASK_PRIORITY\r
+sets the priority of the task that executes the IP stack. The priority is a\r
+standard FreeRTOS task priority so can take any value from 0 (the lowest\r
+priority) to (configMAX_PRIORITIES - 1) (the highest priority).\r
+configMAX_PRIORITIES is a standard FreeRTOS configuration parameter defined in\r
+FreeRTOSConfig.h, not FreeRTOSIPConfig.h. Consideration needs to be given as to\r
+the priority assigned to the task executing the IP stack relative to the\r
+priority assigned to tasks that use the IP stack. \r
+\r
+Note: If the application is started without the network cable plugged in then\r
+this should be set to the lowest priority - otherwise the Atmel ASF GMAC driver\r
+will poll the GMAC interface waiting for a connection to be established. The\r
+driver uses a very long timeout and no lower priority tasks will be able to\r
+execute during this time. This demo starts with the IP task running at the idle\r
+priority - then raises the priority of the IP task in the network event hook\r
+when a connection has been established. */\r
+#define ipconfigUDP_TASK_PRIORITY ( tskIDLE_PRIORITY )\r
+\r
+/* The size, in words (not bytes), of the stack allocated to the FreeRTOS+UDP\r
+task. This setting is less important when the FreeRTOS Win32 simulator is used\r
+as the Win32 simulator only stores a fixed amount of information on the task\r
+stack. FreeRTOS includes optional stack overflow detection, see:\r
+http://www.freertos.org/Stacks-and-stack-overflow-checking.html */\r
+#define ipconfigUDP_TASK_STACK_SIZE_WORDS ( configMINIMAL_STACK_SIZE * 2 )\r
+\r
+/* ipconfigRAND32() is called by the IP stack to generate a random number that\r
+is then used as a DHCP transaction number. Random number generation is performed\r
+via this macro to allow applications to use their own random number generation\r
+method. For example, it might be possible to generate a random number by\r
+sampling noise on an analogue input. */\r
+#define ipconfigRAND32() 1\r
+\r
+/* If ipconfigUSE_NETWORK_EVENT_HOOK is set to 1 then FreeRTOS+UDP will call the\r
+network event hook at the appropriate times. If ipconfigUSE_NETWORK_EVENT_HOOK\r
+is not set to 1 then the network event hook will never be called. See\r
+http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_UDP/API/vApplicationIPNetworkEventHook.shtml\r
+*/\r
+#define ipconfigUSE_NETWORK_EVENT_HOOK 1\r
+\r
+/* Sockets have a send block time attribute. If FreeRTOS_sendto() is called but\r
+a network buffer cannot be obtained then the calling task is held in the Blocked\r
+state (so other tasks can continue to executed) until either a network buffer\r
+becomes available or the send block time expires. If the send block time expires\r
+then the send operation is aborted. The maximum allowable send block time is\r
+capped to the value set by ipconfigMAX_SEND_BLOCK_TIME_TICKS. Capping the\r
+maximum allowable send block time prevents prevents a deadlock occurring when\r
+all the network buffers are in use and the tasks that process (and subsequently\r
+free) the network buffers are themselves blocked waiting for a network buffer.\r
+ipconfigMAX_SEND_BLOCK_TIME_TICKS is specified in RTOS ticks. A time in\r
+milliseconds can be converted to a time in ticks by dividing the time in\r
+milliseconds by portTICK_RATE_MS. */\r
+#define ipconfigMAX_SEND_BLOCK_TIME_TICKS ( 20 / portTICK_RATE_MS )\r
+\r
+/* If ipconfigUSE_DHCP is 1 then FreeRTOS+UDP will attempt to retrieve an IP\r
+address, netmask, DNS server address and gateway address from a DHCP server. If\r
+ipconfigUSE_DHCP is 0 then FreeRTOS+UDP will use a static IP address. The\r
+stack will revert to using the static IP address even when ipconfigUSE_DHCP is\r
+set to 1 if a valid configuration cannot be obtained from a DHCP server for any\r
+reason. The static configuration used is that passed into the stack by the\r
+FreeRTOS_IPInit() function call. */\r
+#define ipconfigUSE_DHCP 0\r
+\r
+/* When ipconfigUSE_DHCP is set to 1, DHCP requests will be sent out at\r
+increasing time intervals until either a reply is received from a DHCP server\r
+and accepted, or the interval between transmissions reaches\r
+ipconfigMAXIMUM_DISCOVER_TX_PERIOD. The IP stack will revert to using the\r
+static IP address passed as a parameter to FreeRTOS_IPInit() if the\r
+re-transmission time interval reaches ipconfigMAXIMUM_DISCOVER_TX_PERIOD without\r
+a DHCP reply being received. */\r
+#ifdef _WINDOWS_\r
+ /* The windows simulated time is not real time so the max delay is much\r
+ shorter. */\r
+ #define ipconfigMAXIMUM_DISCOVER_TX_PERIOD ( 999 / portTICK_RATE_MS )\r
+#else\r
+ #define ipconfigMAXIMUM_DISCOVER_TX_PERIOD ( 120000 / portTICK_RATE_MS )\r
+#endif /* _WINDOWS_ */\r
+\r
+/* The ARP cache is a table that maps IP addresses to MAC addresses. The IP\r
+stack can only send a UDP message to a remove IP address if it knowns the MAC\r
+address associated with the IP address, or the MAC address of the router used to\r
+contact the remote IP address. When a UDP message is received from a remote IP\r
+address the MAC address and IP address are added to the ARP cache. When a UDP\r
+message is sent to a remote IP address that does not already appear in the ARP\r
+cache then the UDP message is replaced by a ARP message that solicits the\r
+required MAC address information. ipconfigARP_CACHE_ENTRIES defines the maximum\r
+number of entries that can exist in the ARP table at any one time. */\r
+#define ipconfigARP_CACHE_ENTRIES 6\r
+\r
+/* ARP requests that do not result in an ARP response will be re-transmitted a\r
+maximum of ipconfigMAX_ARP_RETRANSMISSIONS times before the ARP request is\r
+aborted. */\r
+#define ipconfigMAX_ARP_RETRANSMISSIONS ( 5 )\r
+\r
+/* ipconfigMAX_ARP_AGE defines the maximum time between an entry in the ARP\r
+table being created or refreshed and the entry being removed because it is stale.\r
+New ARP requests are sent for ARP cache entries that are nearing their maximum\r
+age. ipconfigMAX_ARP_AGE is specified in tens of seconds, so a value of 150 is\r
+equal to 1500 seconds (or 25 minutes). */\r
+#define ipconfigMAX_ARP_AGE 150\r
+\r
+/* Implementing FreeRTOS_inet_addr() necessitates the use of string handling\r
+routines, which are relatively large. To save code space the full\r
+FreeRTOS_inet_addr() implementation is made optional, and a smaller and faster\r
+alternative called FreeRTOS_inet_addr_quick() is provided. FreeRTOS_inet_addr()\r
+takes an IP in decimal dot format (for example, "192.168.0.1") as its parameter.\r
+FreeRTOS_inet_addr_quick() takes an IP address as four separate numerical octets\r
+(for example, 192, 168, 0, 1) as its parameters. If\r
+ipconfigINCLUDE_FULL_INET_ADDR is set to 1 then both FreeRTOS_inet_addr() and\r
+FreeRTOS_indet_addr_quick() are available. If ipconfigINCLUDE_FULL_INET_ADDR is\r
+not set to 1 then only FreeRTOS_indet_addr_quick() is available. */\r
+#define ipconfigINCLUDE_FULL_INET_ADDR 1\r
+\r
+/* ipconfigNUM_NETWORK_BUFFERS defines the total number of network buffer that\r
+are available to the IP stack. The total number of network buffers is limited\r
+to ensure the total amount of RAM that can be consumed by the IP stack is capped\r
+to a pre-determinable value. */\r
+#define ipconfigNUM_NETWORK_BUFFERS 10\r
+\r
+/* A FreeRTOS queue is used to send events from application tasks to the IP\r
+stack. ipconfigEVENT_QUEUE_LENGTH sets the maximum number of events that can\r
+be queued for processing at any one time. The event queue must be a minimum of\r
+5 greater than the total number of network buffers. */\r
+#define ipconfigEVENT_QUEUE_LENGTH ( ipconfigNUM_NETWORK_BUFFERS + 5 )\r
+\r
+/* The address of a socket is the combination of its IP address and its port\r
+number. FreeRTOS_bind() is used to manually allocate a port number to a socket\r
+(to 'bind' the socket to a port), but manual binding is not normally necessary\r
+for client sockets (those sockets that initiate outgoing connections rather than\r
+wait for incoming connections on a known port number). If\r
+ipconfigALLOW_SOCKET_SEND_WITHOUT_BIND is set to 1 then calling\r
+FreeRTOS_sendto() on a socket that has not yet been bound will result in the IP\r
+stack automatically binding the socket to a port number from the range\r
+socketAUTO_PORT_ALLOCATION_START_NUMBER to 0xffff. If\r
+ipconfigALLOW_SOCKET_SEND_WITHOUT_BIND is set to 0 then calling FreeRTOS_sendto()\r
+on a socket that has not yet been bound will result in the send operation being\r
+aborted. */\r
+#define ipconfigALLOW_SOCKET_SEND_WITHOUT_BIND 1\r
+\r
+/* Defines the Time To Live (TTL) values used in outgoing UDP packets. */\r
+#define updconfigIP_TIME_TO_LIVE 128\r
+\r
+/* If ipconfigCAN_FRAGMENT_OUTGOING_PACKETS is set to 1 then UDP packets that\r
+contain more data than will fit in a single network frame will be fragmented\r
+across multiple IP packets. Also see the ipconfigNETWORK_MTU setting. If\r
+ipconfigCAN_FRAGMENT_OUTGOING_PACKETS is 1 then (ipconfigNETWORK_MTU - 28) must\r
+be divisible by 8. Setting ipconfigCAN_FRAGMENT_OUTGOING_PACKETS to 1 will\r
+increase both the code size and execution time. */\r
+#define ipconfigCAN_FRAGMENT_OUTGOING_PACKETS 0\r
+\r
+/* The MTU is the maximum number of bytes the payload of a network frame can\r
+contain. For normal Ethernet V2 frames the maximum MTU is 1500. Setting a\r
+lower value can save RAM, depending on the buffer management scheme used. If\r
+ipconfigCAN_FRAGMENT_OUTGOING_PACKETS is 1 then (ipconfigNETWORK_MTU - 28) must\r
+be divisible by 8. */\r
+#define ipconfigNETWORK_MTU 1200\r
+\r
+/* Set ipconfigUSE_DNS to 1 to include a basic DNS client/resolver. DNS is used\r
+through the FreeRTOS_gethostbyname() API function. */\r
+#define ipconfigUSE_DNS 1\r
+\r
+/* If ipconfigREPLY_TO_INCOMING_PINGS is set to 1 then the IP stack will\r
+generate replies to incoming ICMP echo (ping) requests. */\r
+#define ipconfigREPLY_TO_INCOMING_PINGS 1\r
+\r
+/* If ipconfigSUPPORT_OUTGOING_PINGS is set to 1 then the\r
+FreeRTOS_SendPingRequest() API function is available. */\r
+#define ipconfigSUPPORT_OUTGOING_PINGS 0\r
+\r
+/* If ipconfigSUPPORT_SELECT_FUNCTION is set to 1 then the FreeRTOS_select()\r
+(and associated) API function is available. */\r
+#define ipconfigSUPPORT_SELECT_FUNCTION 1\r
+\r
+/* Used for stack testing only, and must be implemented in the network\r
+interface. */\r
+#define updconfigLOOPBACK_ETHERNET_PACKETS 0\r
+\r
+/* If ipconfigFILTER_OUT_NON_ETHERNET_II_FRAMES is set to 1 then Ethernet frames\r
+that are not in Ethernet II format will be dropped. This option is included for\r
+potential future IP stack developments. */\r
+#define ipconfigFILTER_OUT_NON_ETHERNET_II_FRAMES 1\r
+\r
+/* If ipconfigETHERNET_DRIVER_FILTERS_FRAME_TYPES is set to 1 then it is the\r
+responsibility of the Ethernet interface to filter out packets that are of no\r
+interest. If the Ethernet interface does not implement this functionality, then\r
+set ipconfigETHERNET_DRIVER_FILTERS_FRAME_TYPES to 0 to have the IP stack\r
+perform the filtering instead (it is much less efficient for the stack to do it\r
+because the packet will already have been passed into the stack). If the\r
+Ethernet driver does all the necessary filtering in hardware then software\r
+filtering can be removed by using a value other than 1 or 0. */\r
+#define ipconfigETHERNET_DRIVER_FILTERS_FRAME_TYPES 0\r
+\r
+/* Set ipconfigFREERTOS_PLUS_NABTO to 1 to support the Nabto protocol, or 0 to\r
+exclude support for the Nabto protocol. If ipconfigFREERTOS_PLUS_NABTO is set\r
+to one then the project must build the Nabto source code (or reference a\r
+pre-build Nabto library. */\r
+#define ipconfigFREERTOS_PLUS_NABTO 0\r
+\r
+/* Sets the size of the stack used by the Nabto service task. The Nabto event\r
+handler executes in the context of the Nabto service task. If the event handler\r
+uses a lot of stack then it is possible the value set here will need to be\r
+increased. It is recommended to have FreeRTOS stack overflow checking turned\r
+on during development (see the configCHECK_FOR_STACK_OVERFLOW in \r
+FreeRTOSConfig.h and in the documentation. */\r
+#define ipconfigNABTO_TASK_STACK_SIZE ( configMINIMAL_STACK_SIZE * 2 )\r
+\r
+/* Sets the priority of the Nabto service task. This is a standard FreeRTOS\r
+task priority so can take values between 0 (the lowest priority) and\r
+configMAX_PRIORITIES - 1 (the highest priority). Also see the definition of\r
+ipconfigUDP_TASK_PRIORITY. This would normally be set to be either one higher\r
+or one lower than ipconfigUDP_TASK_PRIORITY, depending on the application. */\r
+#define ipconfigNABTO_TASK_PRIORITY ( ipconfigUDP_TASK_PRIORITY + 1 )\r
+\r
+/* The windows simulator cannot really simulate MAC interrupts, and needs to\r
+block occasionally to allow other tasks to run. */\r
+#ifdef _WINDOWS_\r
+ #define configWINDOWS_MAC_INTERRUPT_SIMULATOR_DELAY ( 3 / portTICK_RATE_MS )\r
+#endif\r
+\r
+/* The example IP trace macros are included here so the definitions are\r
+available in all the FreeRTOS+UDP source files. */\r
+#include "DemoIPTrace.h"\r
+\r
+#endif /* FREERTOS_IP_CONFIG_H */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief SAM4E-EK board configuration.\r
+ *\r
+ * Copyright (c) 2012-2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef CONF_BOARD_H_INCLUDED\r
+#define CONF_BOARD_H_INCLUDED\r
+\r
+/* Configure UART pins */\r
+//#define CONF_BOARD_UART_CONSOLE\r
+\r
+/* Enable ETH PHY: KSZ8051MNL feature */\r
+#define CONF_BOARD_KSZ8051MNL\r
+/*\r
+ * LED pins are not configured for PWM function here.\r
+ * Because those LED pins are enabled for PIO function by default.\r
+ * You can enable them according to application.\r
+ */\r
+/* Configure PWM LED0 pin */\r
+//#define CONF_BOARD_PWM_LED0\r
+\r
+/* Configure PWM LED1 pin */\r
+//#define CONF_BOARD_PWM_LED1\r
+\r
+/* Configure PWM LED2 pin */\r
+//#define CONF_BOARD_PWM_LED2\r
+\r
+/* Configure PWM LED3 pin */\r
+//#define CONF_BOARD_PWM_LED3\r
+\r
+/*\r
+ * USART pins are configured as basic serial port by default.\r
+ * You can enable other pins according application.\r
+ */\r
+/* Configure USART RXD pin */\r
+//#define CONF_BOARD_USART_RXD\r
+\r
+/* Configure USART TXD pin */\r
+//#define CONF_BOARD_USART_TXD\r
+\r
+/* Configure USART CTS pin */\r
+//#define CONF_BOARD_USART_CTS\r
+\r
+/* Configure USART RTS pin */\r
+//#define CONF_BOARD_USART_RTS\r
+\r
+/* Configure USART synchronous communication SCK pin */\r
+//#define CONF_BOARD_USART_SCK\r
+\r
+/* Configure ADM3312 enable pin */\r
+//#define CONF_BOARD_ADM3312_EN\r
+//#define CONF_BOARD_ADM3312_EN_DISABLE_AT_INIT\r
+\r
+#endif /* CONF_BOARD_H_INCLUDED */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief SAM4E clock configuration.\r
+ *\r
+ * Copyright (c) 2012-2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef CONF_CLOCK_H_INCLUDED\r
+#define CONF_CLOCK_H_INCLUDED\r
+\r
+// ===== System Clock (MCK) Source Options\r
+//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_SLCK_RC\r
+//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_SLCK_XTAL\r
+//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_SLCK_BYPASS\r
+//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_4M_RC\r
+//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_8M_RC\r
+//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_12M_RC\r
+//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_XTAL\r
+//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_BYPASS\r
+#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_PLLACK\r
+\r
+// ===== System Clock (MCK) Prescaler Options (Fmck = Fsys / (SYSCLK_PRES))\r
+//#define CONFIG_SYSCLK_PRES SYSCLK_PRES_1\r
+#define CONFIG_SYSCLK_PRES SYSCLK_PRES_2\r
+//#define CONFIG_SYSCLK_PRES SYSCLK_PRES_4\r
+//#define CONFIG_SYSCLK_PRES SYSCLK_PRES_8\r
+//#define CONFIG_SYSCLK_PRES SYSCLK_PRES_16\r
+//#define CONFIG_SYSCLK_PRES SYSCLK_PRES_32\r
+//#define CONFIG_SYSCLK_PRES SYSCLK_PRES_64\r
+//#define CONFIG_SYSCLK_PRES SYSCLK_PRES_3\r
+\r
+// ===== PLL0 (A) Options (Fpll = (Fclk * PLL_mul) / PLL_div)\r
+// Use mul and div effective values here.\r
+#define CONFIG_PLL0_SOURCE PLL_SRC_MAINCK_XTAL\r
+#define CONFIG_PLL0_MUL 16\r
+#define CONFIG_PLL0_DIV 1\r
+\r
+\r
+// ===== USB Clock Source Options (Fusb = FpllX / USB_div)\r
+// Use div effective value here.\r
+#define CONFIG_USBCLK_SOURCE USBCLK_SRC_PLL0\r
+#define CONFIG_USBCLK_DIV 2\r
+\r
+// ===== Target frequency (System clock)\r
+// - XTAL frequency: 12MHz\r
+// - System clock source: PLLA\r
+// - System clock prescaler: 2 (divided by 2)\r
+// - PLLA source: XTAL\r
+// - PLLA output: XTAL * 16 / 1\r
+// - System clock: 12 * 16 / 1 / 2 = 96MHz\r
+// ===== Target frequency (USB Clock)\r
+// - USB clock source: PLLA\r
+// - USB clock divider: 2 (divided by 2)\r
+// - PLLA output: XTAL * 16 / 2\r
+// - USB clock: 12 * 16 / 2 / 2 = 48MHz\r
+\r
+\r
+#endif /* CONF_CLOCK_H_INCLUDED */\r
--- /dev/null
+ /**\r
+ * \file\r
+ *\r
+ * \brief GMAC (Ethernet MAC) driver for SAM.\r
+ *\r
+ * Copyright (c) 2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef CONF_EMAC_H_INCLUDED\r
+#define CONF_EMAC_H_INCLUDED\r
+\r
+/// @cond 0\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+/**INDENT-ON**/\r
+/// @endcond\r
+\r
+#include "gmac.h"\r
+\r
+/** Number of buffer for RX */\r
+#define GMAC_RX_BUFFERS 16\r
+\r
+/** Number of buffer for TX */\r
+#define GMAC_TX_BUFFERS 8\r
+\r
+/** MAC PHY operation max retry count */\r
+#define MAC_PHY_RETRY_MAX 1000000\r
+\r
+/** MAC address definition. The MAC address must be unique on the network. */\r
+#define ETHERNET_CONF_ETHADDR0 0x00\r
+#define ETHERNET_CONF_ETHADDR1 0x04\r
+#define ETHERNET_CONF_ETHADDR2 0x25\r
+#define ETHERNET_CONF_ETHADDR3 0x1C\r
+#define ETHERNET_CONF_ETHADDR4 0xA0\r
+#define ETHERNET_CONF_ETHADDR5 0x02\r
+\r
+/** WAN Address: 192.168.0.2 */\r
+\r
+/* The IP address being used. */\r
+#define ETHERNET_CONF_IPADDR0 192\r
+#define ETHERNET_CONF_IPADDR1 168\r
+#define ETHERNET_CONF_IPADDR2 0\r
+#define ETHERNET_CONF_IPADDR3 2\r
+\r
+/** WAN gateway: 192.168.0.250 */\r
+\r
+/*! The gateway address being used. */\r
+#define ETHERNET_CONF_GATEWAY_ADDR0 192\r
+#define ETHERNET_CONF_GATEWAY_ADDR1 168\r
+#define ETHERNET_CONF_GATEWAY_ADDR2 0\r
+#define ETHERNET_CONF_GATEWAY_ADDR3 250\r
+\r
+/** The network mask being used. */\r
+#define ETHERNET_CONF_NET_MASK0 255\r
+#define ETHERNET_CONF_NET_MASK1 255\r
+#define ETHERNET_CONF_NET_MASK2 255\r
+#define ETHERNET_CONF_NET_MASK3 0\r
+\r
+/** Ethernet MII/RMII mode */\r
+#define ETH_PHY_MODE GMAC_PHY_MII\r
+\r
+/// @cond 0\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+/**INDENT-ON**/\r
+/// @endcond\r
+\r
+#endif /* CONF_EMAC_H_INCLUDED */\r
--- /dev/null
+/*\r
+ * FreeRTOS+FAT FS V1.0.0 (C) 2013 HCC Embedded\r
+ *\r
+ * FreeRTOS+FAT SL is an complementary component provided to Real Time Engineers\r
+ * Ltd. by HCC Embedded for use with FreeRTOS. It is not, in itself, part of\r
+ * the FreeRTOS kernel. FreeRTOS+FAT SL is licensed separately from FreeRTOS,\r
+ * and uses a different license to FreeRTOS. FreeRTOS+FAT SL uses a dual\r
+ * license model, information on which is provided below:\r
+ *\r
+ * - Open source licensing -\r
+ * FreeRTOS+FAT SL is a free download and may be used, modified and distributed\r
+ * without charge provided the user adheres to version two of the GNU General\r
+ * Public license (GPL) and does not remove the copyright notice or this text.\r
+ * The GPL V2 text is available on the gnu.org web site, and on the following\r
+ * URL: http://www.FreeRTOS.org/gpl-2.0.txt\r
+ *\r
+ * - Commercial licensing -\r
+ * Businesses and individuals who wish to incorporate FreeRTOS+FAT SL into\r
+ * proprietary software for redistribution in any form must first obtain a\r
+ * commercial license - and in-so-doing support the maintenance, support and\r
+ * further development of the FreeRTOS+FAT SL product. Commercial licenses can\r
+ * be obtained from http://shop.freertos.org and do not require any source files\r
+ * to be changed.\r
+ *\r
+ * FreeRTOS+FAT SL is distributed in the hope that it will be useful. You\r
+ * cannot use FreeRTOS+FAT SL unless you agree that you use the software 'as\r
+ * is'. FreeRTOS+FAT SL is provided WITHOUT ANY WARRANTY; without even the\r
+ * implied warranties of NON-INFRINGEMENT, MERCHANTABILITY or FITNESS FOR A\r
+ * PARTICULAR PURPOSE. Real Time Engineers Ltd. and HCC Embedded disclaims all\r
+ * conditions and terms, be they implied, expressed, or statutory.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://www.FreeRTOS.org/FreeRTOS-Plus\r
+ *\r
+ */\r
+\r
+#ifndef _CONFIG_FAT_SL_H\r
+#define _CONFIG_FAT_SL_H\r
+\r
+#include "../version/ver_fat_sl.h"\r
+#if VER_FAT_SL_MAJOR != 3 || VER_FAT_SL_MINOR != 2\r
+ #error Incompatible FAT_SL version number!\r
+#endif\r
+\r
+#include "../api/api_mdriver.h"\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+\r
+/**************************************************************************\r
+**\r
+** FAT SL user settings\r
+**\r
+**************************************************************************/\r
+#define F_SECTOR_SIZE 512u /* Disk sector size. */\r
+#define F_FS_THREAD_AWARE 1 /* Set to one if the file system will be access from more than one task. */\r
+#define F_MAXPATH 64 /* Maximum length a file name (including its full path) can be. */\r
+#define F_MAX_LOCK_WAIT_TICKS 20 /* The maximum number of RTOS ticks to wait when attempting to obtain a lock on the file system when F_FS_THREAD_AWARE is set to 1. */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* _CONFIG_FAT_SL_H */\r
+\r
--- /dev/null
+/*\r
+ * FreeRTOS+FAT FS V1.0.0 (C) 2013 HCC Embedded\r
+ *\r
+ * FreeRTOS+FAT SL is an complementary component provided to Real Time Engineers\r
+ * Ltd. by HCC Embedded for use with FreeRTOS. It is not, in itself, part of\r
+ * the FreeRTOS kernel. FreeRTOS+FAT SL is licensed separately from FreeRTOS,\r
+ * and uses a different license to FreeRTOS. FreeRTOS+FAT SL uses a dual\r
+ * license model, information on which is provided below:\r
+ *\r
+ * - Open source licensing -\r
+ * FreeRTOS+FAT SL is a free download and may be used, modified and distributed\r
+ * without charge provided the user adheres to version two of the GNU General\r
+ * Public license (GPL) and does not remove the copyright notice or this text.\r
+ * The GPL V2 text is available on the gnu.org web site, and on the following\r
+ * URL: http://www.FreeRTOS.org/gpl-2.0.txt\r
+ *\r
+ * - Commercial licensing -\r
+ * Businesses and individuals who wish to incorporate FreeRTOS+FAT SL into\r
+ * proprietary software for redistribution in any form must first obtain a\r
+ * commercial license - and in-so-doing support the maintenance, support and\r
+ * further development of the FreeRTOS+FAT SL product. Commercial licenses can\r
+ * be obtained from http://shop.freertos.org and do not require any source files\r
+ * to be changed.\r
+ *\r
+ * FreeRTOS+FAT SL is distributed in the hope that it will be useful. You\r
+ * cannot use FreeRTOS+FAT SL unless you agree that you use the software 'as\r
+ * is'. FreeRTOS+FAT SL is provided WITHOUT ANY WARRANTY; without even the\r
+ * implied warranties of NON-INFRINGEMENT, MERCHANTABILITY or FITNESS FOR A\r
+ * PARTICULAR PURPOSE. Real Time Engineers Ltd. and HCC Embedded disclaims all\r
+ * conditions and terms, be they implied, expressed, or statutory.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://www.FreeRTOS.org/FreeRTOS-Plus\r
+ *\r
+ */\r
+\r
+#ifndef _CONFIG_MDRIVER_RAM_H_\r
+#define _CONFIG_MDRIVER_RAM_H_\r
+\r
+#include "../version/ver_mdriver_ram.h"\r
+#if VER_MDRIVER_RAM_MAJOR != 1 || VER_MDRIVER_RAM_MINOR != 2\r
+ #error Incompatible MDRIVER_RAM version number!\r
+#endif\r
+\r
+#define MDRIVER_RAM_SECTOR_SIZE 512 /* Sector size */\r
+\r
+#define MDRIVER_RAM_VOLUME0_SIZE (28 * 1024) /* definition for size of ramdrive0 */\r
+\r
+#define MDRIVER_MEM_LONG_ACCESS 1 /* set this value to 1 if 32bit access available */\r
+\r
+#endif /* ifndef _CONFIG_MDRIVER_RAM_H_ */\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. \r
+ All rights reserved\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that has become a de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly and support the FreeRTOS *\r
+ * project by purchasing a FreeRTOS tutorial book, reference *\r
+ * manual, or both from: http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ * Thank you! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+\r
+ >>! NOTE: The modification to the GPL is included to allow you to distribute\r
+ >>! a combined work that includes FreeRTOS without being obliged to provide\r
+ >>! the source code for proprietary components outside of the FreeRTOS\r
+ >>! kernel.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available from the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong?" *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
+ license and Real Time Engineers Ltd. contact details.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
+ Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+/******************************************************************************\r
+ * This project provides two demo applications. A simple blinky style project,\r
+ * and a more comprehensive application that makes use of FreeRTOS+ add-on\r
+ * components. The mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting (defined in this \r
+ * file) is used to select between the two. The simply blinky demo is \r
+ * implemented and described in main_blinky.c. The more comprehensive demo \r
+ * application is implemented and described in main_full.c.\r
+ *\r
+ * This file implements the code that is not demo specific, including the\r
+ * hardware setup and FreeRTOS hook functions.\r
+ *\r
+ */\r
+\r
+/* Kernel includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Set mainCREATE_SIMPLE_BLINKY_DEMO_ONLY to one to run the simple blinky demo,\r
+or 0 to run the more comprehensive demo application that includes add-on \r
+components. */\r
+#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 0\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Set up the hardware ready to run this demo.\r
+ */\r
+static void prvSetupHardware( void );\r
+\r
+/*\r
+ * main_blinky() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1.\r
+ * main_full() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 0.\r
+ */\r
+extern void main_blinky( void );\r
+extern void main_full( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+int main( void )\r
+{\r
+ /* Prepare the hardware to run this demo. */\r
+ prvSetupHardware();\r
+\r
+ /* The mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting is described at the top\r
+ of this file. */\r
+ #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1\r
+ {\r
+ main_blinky();\r
+ }\r
+ #else\r
+ {\r
+ main_full();\r
+ }\r
+ #endif\r
+\r
+ return 0;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSetupHardware( void )\r
+{\r
+ /* Call the ASF initialisation functions. */\r
+ board_init();\r
+ sysclk_init();\r
+ pmc_enable_periph_clk( ID_GMAC );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationMallocFailedHook( void )\r
+{\r
+ /* vApplicationMallocFailedHook() will only be called if\r
+ configUSE_MALLOC_FAILED_HOOK is set to 1 in FreeRTOSConfig.h. It is a hook\r
+ function that will get called if a call to pvPortMalloc() fails.\r
+ pvPortMalloc() is called internally by the kernel whenever a task, queue,\r
+ timer or semaphore is created. It is also called by various parts of the\r
+ demo application. If heap_1.c or heap_2.c are used, then the size of the\r
+ heap available to pvPortMalloc() is defined by configTOTAL_HEAP_SIZE in\r
+ FreeRTOSConfig.h, and the xPortGetFreeHeapSize() API function can be used\r
+ to query the size of free heap space that remains (although it does not\r
+ provide information on how the remaining heap might be fragmented). */\r
+ taskDISABLE_INTERRUPTS();\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationIdleHook( void )\r
+{\r
+ /* vApplicationIdleHook() will only be called if configUSE_IDLE_HOOK is set\r
+ to 1 in FreeRTOSConfig.h. It will be called on each iteration of the idle\r
+ task. It is essential that code added to this hook function never attempts\r
+ to block in any way (for example, call xQueueReceive() with a block time\r
+ specified, or call vTaskDelay()). If the application makes use of the\r
+ vTaskDelete() API function (as this demo application does) then it is also\r
+ important that vApplicationIdleHook() is permitted to return to its calling\r
+ function, because it is the responsibility of the idle task to clean up\r
+ memory allocated by the kernel to any task that has since been deleted. */\r
+ \r
+ /* The simple blinky demo does not use the idle hook - the full demo does. */\r
+ #if( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 0 )\r
+ {\r
+ extern void vFullDemoIdleHook( void );\r
+ \r
+ vFullDemoIdleHook();\r
+ }\r
+ #endif\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationStackOverflowHook( xTaskHandle pxTask, signed char *pcTaskName )\r
+{\r
+ ( void ) pcTaskName;\r
+ ( void ) pxTask;\r
+\r
+ /* Run time stack overflow checking is performed if\r
+ configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook\r
+ function is called if a stack overflow is detected. */\r
+ taskDISABLE_INTERRUPTS();\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationTickHook( void )\r
+{\r
+ /* This function will be called by each tick interrupt if\r
+ configUSE_TICK_HOOK is set to 1 in FreeRTOSConfig.h. User code can be\r
+ added here, but the tick hook is called from an interrupt context, so\r
+ code must not attempt to block, and only the interrupt safe FreeRTOS API\r
+ functions can be used (those that end in FromISR()). */\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vAssertCalled( uint32_t ulLine, const char *pcFile )\r
+{\r
+/* The following two variables are just to ensure the parameters are not\r
+optimised away and therefore unavailable when viewed in the debugger. */\r
+volatile uint32_t ulLineNumber = ulLine, ulSetNoneZeroInDebuggerToReturn = 0;\r
+volatile const char * const pcFileName = pcFile;\r
+\r
+ taskENTER_CRITICAL();\r
+ while( ulSetNoneZeroInDebuggerToReturn == 0 )\r
+ {\r
+ /* If you want to set out of this function in the debugger to see the\r
+ assert() location then set ulSetNoneZeroInDebuggerToReturn to a non-zero\r
+ value. */\r
+ }\r
+ taskEXIT_CRITICAL();\r
+ \r
+ ( void ) pcFileName;\r
+ ( void ) ulLineNumber;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Provided to keep the linker happy. */\r
+void _exit_( int status )\r
+{\r
+ ( void ) status;\r
+ vAssertCalled( __LINE__, __FILE__ );\r
+ for( ;; );\r
+}\r
+\r
+int _read( void )\r
+{\r
+ return 0;\r
+}\r
+\r
+int _write( int x )\r
+{\r
+ ( void ) x;\r
+ return 0;\r
+}
\ No newline at end of file
--- /dev/null
+/*\r
+ FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. \r
+ All rights reserved\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that has become a de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly and support the FreeRTOS *\r
+ * project by purchasing a FreeRTOS tutorial book, reference *\r
+ * manual, or both from: http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ * Thank you! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+\r
+ >>! NOTE: The modification to the GPL is included to allow you to distribute\r
+ >>! a combined work that includes FreeRTOS without being obliged to provide\r
+ >>! the source code for proprietary components outside of the FreeRTOS\r
+ >>! kernel.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available from the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong?" *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
+ license and Real Time Engineers Ltd. contact details.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
+ Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+/******************************************************************************\r
+ * NOTE 1: This project provides two demo applications. A simple blinky style\r
+ * project, and a more comprehensive demo application that makes use of some\r
+ * add-on components. The mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c \r
+ * is used to select between the two. See the notes on using \r
+ * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY in main.c. This file implements the \r
+ * simply blinky style version.\r
+ *\r
+ * NOTE 2: This file only contains the source code that is specific to the\r
+ * basic demo. Generic functions, such FreeRTOS hook functions, and functions\r
+ * required to configure the hardware, are defined in main.c.\r
+ ******************************************************************************\r
+ *\r
+ * main_blinky() creates one queue, and two tasks and one software timer. It \r
+ * then starts the scheduler.\r
+ *\r
+ * The Queue Send Task:\r
+ * The queue send task is implemented by the prvQueueSendTask() function in\r
+ * this file. The task sits in a loop that sends a value to the queue every\r
+ * 200 milliseconds.\r
+ *\r
+ * The Queue Receive Task:\r
+ * The queue receive task is implemented by the prvQueueReceiveTask() function\r
+ * in this file. The task sits in a loop that blocks on the queue to wait for\r
+ * data to arrive (it does not use any CPU time while it is in the Blocked\r
+ * state), toggling an LED each time it receives the value sent by the queue\r
+ * send task. As the queue send task writes to the queue every 200 milliseconds\r
+ * the LED will toggle every 200 milliseconds.\r
+ */\r
+\r
+\r
+/* Kernel includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "queue.h"\r
+#include "timers.h"\r
+\r
+/* Priorities at which the tasks are created. */\r
+#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )\r
+\r
+/* The rate at which data is sent to the queue. The 200ms value is converted\r
+to ticks using the portTICK_RATE_MS constant. */\r
+#define mainQUEUE_SEND_FREQUENCY_MS ( 200 / portTICK_RATE_MS )\r
+\r
+/* The number of items the queue can hold. This is 1 as the receive task\r
+will remove items as they are added, meaning the send task should always find\r
+the queue empty. */\r
+#define mainQUEUE_LENGTH ( 1 )\r
+\r
+/* Values passed to the two tasks just to check the task parameter\r
+functionality. */\r
+#define mainQUEUE_SEND_PARAMETER ( 0x1111UL )\r
+#define mainQUEUE_RECEIVE_PARAMETER ( 0x22UL )\r
+\r
+/* The period of the blinky software timer. The period is specified in ms and\r
+converted to ticks using the portTICK_RATE_MS constant. */\r
+#define mainBLINKY_TIMER_PERIOD ( 50 / portTICK_RATE_MS )\r
+\r
+/* A block time of zero simply means "don't block". */\r
+#define mainDONT_BLOCK ( 0 )\r
+\r
+/* The LEDs toggled by the timer and queue receive task respectively. */\r
+#define mainTIMER_LED LED0_GPIO\r
+#define mainTASK_LED LED1_GPIO\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * The tasks as described in the comments at the top of this file.\r
+ */\r
+static void prvQueueReceiveTask( void *pvParameters );\r
+static void prvQueueSendTask( void *pvParameters );\r
+\r
+/*\r
+ * The callback function for the blinky software timer, as described at the top\r
+ * of this file.\r
+ */\r
+static void prvBlinkyTimerCallback( xTimerHandle xTimer );\r
+\r
+/*\r
+ * Called by main() to create the simply blinky style application if\r
+ * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1.\r
+ */\r
+void main_blinky( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The queue used by both tasks. */\r
+static xQueueHandle xQueue = NULL;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void main_blinky( void )\r
+{\r
+xTimerHandle xTimer;\r
+\r
+ /* Create the queue. */\r
+ xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( unsigned long ) );\r
+\r
+ if( xQueue != NULL )\r
+ {\r
+ /* Start the two tasks as described in the comments at the top of this\r
+ file. */\r
+ xTaskCreate( prvQueueReceiveTask, /* The function that implements the task. */\r
+ ( signed char * ) "Rx", /* The text name assigned to the task - for debug only as it is not used by the kernel. */\r
+ configMINIMAL_STACK_SIZE, /* The size of the stack to allocate to the task. */\r
+ ( void * ) mainQUEUE_RECEIVE_PARAMETER, /* The parameter passed to the task - just to check the functionality. */\r
+ mainQUEUE_RECEIVE_TASK_PRIORITY, /* The priority assigned to the task. */\r
+ NULL ); /* The task handle is not required, so NULL is passed. */\r
+\r
+ xTaskCreate( prvQueueSendTask, ( signed char * ) "TX", configMINIMAL_STACK_SIZE, ( void * ) mainQUEUE_SEND_PARAMETER, mainQUEUE_SEND_TASK_PRIORITY, NULL );\r
+\r
+ /* Create the blinky software timer as described at the top of this \r
+ file. */\r
+ xTimer = xTimerCreate( ( const signed char * ) "Blinky",/* A text name, purely to help debugging. */\r
+ ( mainBLINKY_TIMER_PERIOD ), /* The timer period. */\r
+ pdTRUE, /* This is an auto-reload timer, so xAutoReload is set to pdTRUE. */\r
+ ( void * ) 0, /* The ID is not used, so can be set to anything. */\r
+ prvBlinkyTimerCallback ); /* The callback function that inspects the status of all the other tasks. */\r
+\r
+ configASSERT( xTimer );\r
+\r
+ if( xTimer != NULL )\r
+ {\r
+ xTimerStart( xTimer, mainDONT_BLOCK );\r
+ }\r
+\r
+ /* Start the tasks and timer running. */\r
+ vTaskStartScheduler();\r
+ }\r
+\r
+ /* If all is well, the scheduler will now be running, and the following\r
+ line will never be reached. If the following line does execute, then\r
+ there was insufficient FreeRTOS heap memory available for the idle and/or\r
+ timer tasks to be created. See the memory management section on the\r
+ FreeRTOS web site for more details. */\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvQueueSendTask( void *pvParameters )\r
+{\r
+portTickType xNextWakeTime;\r
+const unsigned long ulValueToSend = 100UL;\r
+\r
+ /* Check the task parameter is as expected. */\r
+ configASSERT( ( ( unsigned long ) pvParameters ) == mainQUEUE_SEND_PARAMETER );\r
+\r
+ /* Initialise xNextWakeTime - this only needs to be done once. */\r
+ xNextWakeTime = xTaskGetTickCount();\r
+\r
+ for( ;; )\r
+ {\r
+ /* Place this task in the blocked state until it is time to run again.\r
+ The block time is specified in ticks, the constant used converts ticks\r
+ to ms. While in the Blocked state this task will not consume any CPU\r
+ time. */\r
+ vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS );\r
+\r
+ /* Send to the queue - causing the queue receive task to unblock and\r
+ toggle the LED. 0 is used as the block time so the sending operation\r
+ will not block - it shouldn't need to block as the queue should always\r
+ be empty at this point in the code. */\r
+ xQueueSend( xQueue, &ulValueToSend, 0U );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvQueueReceiveTask( void *pvParameters )\r
+{\r
+unsigned long ulReceivedValue;\r
+\r
+ /* Check the task parameter is as expected. */\r
+ configASSERT( ( ( unsigned long ) pvParameters ) == mainQUEUE_RECEIVE_PARAMETER );\r
+\r
+ for( ;; )\r
+ {\r
+ /* Wait until something arrives in the queue - this task will block\r
+ indefinitely provided INCLUDE_vTaskSuspend is set to 1 in\r
+ FreeRTOSConfig.h. */\r
+ xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY );\r
+\r
+ /* To get here something must have been received from the queue, but\r
+ is it the expected value? If it is, toggle the LED. */\r
+ if( ulReceivedValue == 100UL )\r
+ {\r
+ ioport_toggle_pin_level( mainTASK_LED );\r
+ ulReceivedValue = 0U;\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvBlinkyTimerCallback( xTimerHandle xTimer )\r
+{\r
+ /* Avoid compiler warnings. */\r
+ ( void ) xTimer;\r
+\r
+ /* This function is called when the blinky software time expires. All the\r
+ function does is toggle the LED. LED mainTIMER_LED should therefore toggle\r
+ with the period set by mainBLINKY_TIMER_PERIOD. */\r
+ ioport_toggle_pin_level( mainTIMER_LED );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. \r
+ All rights reserved\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that has become a de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly and support the FreeRTOS *\r
+ * project by purchasing a FreeRTOS tutorial book, reference *\r
+ * manual, or both from: http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ * Thank you! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+\r
+ >>! NOTE: The modification to the GPL is included to allow you to distribute\r
+ >>! a combined work that includes FreeRTOS without being obliged to provide\r
+ >>! the source code for proprietary components outside of the FreeRTOS\r
+ >>! kernel.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available from the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong?" *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
+ license and Real Time Engineers Ltd. contact details.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
+ Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+/* FreeRTOS includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "timers.h"\r
+\r
+/* FreeRTOS+UDP includes. */\r
+#include "FreeRTOS_UDP_IP.h"\r
+\r
+/* Demo application includes. */\r
+#include "UDPCommandInterpreter.h"\r
+\r
+/* Note: If the application is started without the network cable plugged in \r
+then ipconfigUDP_TASK_PRIORITY should be set to 0 in FreeRTOSIPConfig.h to\r
+ensure the IP task is created at the idle priority. This is because the Atmel \r
+ASF GMAC driver polls the GMAC looking for a connection, and doing so will \r
+prevent any lower priority tasks from executing. In this demo the IP task is \r
+started at the idle priority, then set to configMAX_PRIORITIES - 2 in the \r
+network event hook only after a connection has been established (when the event\r
+passed into the network event hook is eNetworkUp). */\r
+#define mainCONNECTED_IP_TASK_PRIORITY ( configMAX_PRIORITIES - 2 )\r
+#define mainDISCONNECTED_IP_TASK_PRIORITY ( tskIDLE_PRIORITY )\r
+\r
+/* UDP command server task parameters. */\r
+#define mainUDP_CLI_TASK_PRIORITY ( tskIDLE_PRIORITY )\r
+#define mainUDP_CLI_PORT_NUMBER ( 5001UL )\r
+#define mainUDP_CLI_TASK_STACK_SIZE ( configMINIMAL_STACK_SIZE * 2U )\r
+\r
+/* Simple toggles an LED to show the program is running. */\r
+static void prvFlashTimerCallback( xTimerHandle xTimer );\r
+\r
+/* Creates a set of sample files on a RAM disk. */\r
+extern void vCreateAndVerifySampleFiles( void );\r
+\r
+/*\r
+ * Register the generic commands that can be used with FreeRTOS+CLI.\r
+ */\r
+extern void vRegisterSampleCLICommands( void );\r
+\r
+/*\r
+ * Register the file system commands that can be used with FreeRTOS+CLI.\r
+ */\r
+extern void vRegisterFileSystemCLICommands( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The default IP and MAC address used by the demo. The address configuration\r
+defined here will be used if ipconfigUSE_DHCP is 0, or if ipconfigUSE_DHCP is\r
+1 but a DHCP server could not be contacted. See the online documentation for\r
+more information. */\r
+static const uint8_t ucIPAddress[ 4 ] = { configIP_ADDR0, configIP_ADDR1, configIP_ADDR2, configIP_ADDR3 };\r
+static const uint8_t ucNetMask[ 4 ] = { configNET_MASK0, configNET_MASK1, configNET_MASK2, configNET_MASK3 };\r
+static const uint8_t ucGatewayAddress[ 4 ] = { configGATEWAY_ADDR0, configGATEWAY_ADDR1, configGATEWAY_ADDR2, configGATEWAY_ADDR3 };\r
+static const uint8_t ucDNSServerAddress[ 4 ] = { configDNS_SERVER_ADDR0, configDNS_SERVER_ADDR1, configDNS_SERVER_ADDR2, configDNS_SERVER_ADDR3 };\r
+\r
+/* The MAC address used by the demo. In production units the MAC address would\r
+probably be read from flash memory or an EEPROM. Here it is just hard coded.\r
+Note each node on a network must have a unique MAC address. */\r
+const uint8_t ucMACAddress[ 6 ] = { configMAC_ADDR0, configMAC_ADDR1, configMAC_ADDR2, configMAC_ADDR3, configMAC_ADDR4, configMAC_ADDR5 };\r
+\r
+/*-----------------------------------------------------------*/\r
+int main_full( void )\r
+{\r
+xTimerHandle xFlashTimer;\r
+\r
+ /* If the file system is only going to be accessed from one task then\r
+ F_FS_THREAD_AWARE can be set to 0 and the set of example files are created\r
+ before the RTOS scheduler is started. If the file system is going to be\r
+ access from more than one task then F_FS_THREAD_AWARE must be set to 1 and\r
+ the set of sample files are created from the idle task hook function\r
+ vApplicationIdleHook() - which is defined in this file. */\r
+ #if( F_FS_THREAD_AWARE == 0 )\r
+ {\r
+ /* Initialise the drive and file system, then create a few example\r
+ files. The output from this function just goes to the stdout window,\r
+ allowing the output to be viewed when the UDP command console is not\r
+ connected. */\r
+ vCreateAndVerifySampleFiles();\r
+ }\r
+ #endif\r
+\r
+ /* Register generic commands with the FreeRTOS+CLI command interpreter. */\r
+ vRegisterSampleCLICommands();\r
+\r
+ /* Register file system related commands with the FreeRTOS+CLI command\r
+ interpreter. */\r
+ vRegisterFileSystemCLICommands();\r
+\r
+ /* Create the timer that just toggles an LED to indicate that the \r
+ application is running. */\r
+ xFlashTimer = xTimerCreate( ( const signed char * const ) "Flash", 200 / portTICK_RATE_MS, pdTRUE, NULL, prvFlashTimerCallback );\r
+ configASSERT( xFlashTimer );\r
+ \r
+ /* Start the timer. As the scheduler is not running a block time cannot be\r
+ used and is set to 0. */\r
+ xTimerStart( xFlashTimer, 0 );\r
+\r
+ /* Initialise the network interface. Tasks that use the network are\r
+ created in the network event hook when the network is connected and ready\r
+ for use. The address values passed in here are used if ipconfigUSE_DHCP is\r
+ set to 0, or if ipconfigUSE_DHCP is set to 1 but a DHCP server cannot be\r
+ contacted. The Nabto service task is created automatically if\r
+ ipconfigFREERTOS_PLUS_NABTO is set to 1 in FreeRTOSIPConfig.h. */\r
+ FreeRTOS_IPInit( ucIPAddress, ucNetMask, ucGatewayAddress, ucDNSServerAddress, ucMACAddress );\r
+\r
+ /* Start the scheduler itself. */\r
+ vTaskStartScheduler();\r
+\r
+ /* If all is well, the scheduler will now be running, and the following line\r
+ will never be reached. If the following line does execute, then there was\r
+ insufficient FreeRTOS heap memory available for the idle and/or timer tasks\r
+ to be created. See the memory management section on the FreeRTOS web site\r
+ for more details. */\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvFlashTimerCallback( xTimerHandle xTimer )\r
+{\r
+ /* The parameter is not used. */\r
+ ( void ) xTimer;\r
+ \r
+ /* Timer callback function that does nothing other than toggle an LED to\r
+ indicate that the application is still running. */\r
+ ioport_toggle_pin_level( LED0_GPIO );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Called by FreeRTOS+UDP when the network connects. */\r
+void vApplicationIPNetworkEventHook( eIPCallbackEvent_t eNetworkEvent )\r
+{\r
+static long lTasksAlreadyCreated = pdFALSE;\r
+\r
+ /* Note: If the application is started without the network cable plugged in\r
+ then ipconfigUDP_TASK_PRIORITY should be set to 0 in FreeRTOSIPConfig.h to\r
+ ensure the IP task is created at the idle priority. This is because the Atmel\r
+ ASF GMAC driver polls the GMAC looking for a connection, and doing so will\r
+ prevent any lower priority tasks from executing. In this demo the IP task is\r
+ started at the idle priority, then set to configMAX_PRIORITIES - 2 in the\r
+ network event hook only after a connection has been established (when the event\r
+ passed into the network event hook is eNetworkUp). */\r
+ if( eNetworkEvent == eNetworkUp )\r
+ {\r
+ vTaskPrioritySet( NULL, mainCONNECTED_IP_TASK_PRIORITY );\r
+\r
+ if( lTasksAlreadyCreated == pdFALSE )\r
+ { \r
+ /* Create the task that handles the CLI on a UDP port. The port number\r
+ is set using the configUDP_CLI_PORT_NUMBER setting in FreeRTOSConfig.h. */\r
+ vStartUDPCommandInterpreterTask( mainUDP_CLI_TASK_STACK_SIZE, mainUDP_CLI_PORT_NUMBER, mainUDP_CLI_TASK_PRIORITY );\r
+ }\r
+ }\r
+\r
+ if( eNetworkEvent == eNetworkDown )\r
+ {\r
+ vTaskPrioritySet( NULL, tskIDLE_PRIORITY );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vFullDemoIdleHook( void )\r
+{ \r
+ /* If the file system is only going to be accessed from one task then\r
+ F_FS_THREAD_AWARE can be set to 0 and the set of example files is created\r
+ before the RTOS scheduler is started. If the file system is going to be\r
+ access from more than one task then F_FS_THREAD_AWARE must be set to 1 and\r
+ the set of sample files are created from the idle task hook function. */\r
+ #if( F_FS_THREAD_AWARE == 1 )\r
+ {\r
+ static portBASE_TYPE xCreatedSampleFiles = pdFALSE;\r
+\r
+ /* Initialise the drive and file system, then create a few example\r
+ files. The output from this function just goes to the stdout window,\r
+ allowing the output to be viewed when the UDP command console is not\r
+ connected. */\r
+ if( xCreatedSampleFiles == pdFALSE )\r
+ {\r
+ vCreateAndVerifySampleFiles();\r
+ xCreatedSampleFiles = pdTRUE;\r
+ }\r
+ }\r
+ #endif\r
+}\r
+\r
+\r
+\r
+\r
--- /dev/null
+/*
+ Copyright 2001, 2002 Georges Menie (www.menie.org)
+ stdarg version contributed by Christian Ettinger
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU Lesser General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+*/
+
+/*
+ putchar is the only external dependency for this file,
+ if you have a working putchar, leave it commented out.
+ If not, uncomment the define below and
+ replace outbyte(c) by your own function call.
+
+#define putchar(c) outbyte(c)
+*/
+
+#include <stdarg.h>
+
+static void printchar(char **str, int c)
+{
+ extern int putchar(int c);
+
+ if (str) {
+ **str = c;
+ ++(*str);
+ }
+ else (void)putchar(c);
+}
+
+#define PAD_RIGHT 1
+#define PAD_ZERO 2
+
+static int prints(char **out, const char *string, int width, int pad)
+{
+ register int pc = 0, padchar = ' ';
+
+ if (width > 0) {
+ register int len = 0;
+ register const char *ptr;
+ for (ptr = string; *ptr; ++ptr) ++len;
+ if (len >= width) width = 0;
+ else width -= len;
+ if (pad & PAD_ZERO) padchar = '0';
+ }
+ if (!(pad & PAD_RIGHT)) {
+ for ( ; width > 0; --width) {
+ printchar (out, padchar);
+ ++pc;
+ }
+ }
+ for ( ; *string ; ++string) {
+ printchar (out, *string);
+ ++pc;
+ }
+ for ( ; width > 0; --width) {
+ printchar (out, padchar);
+ ++pc;
+ }
+
+ return pc;
+}
+
+/* the following should be enough for 32 bit int */
+#define PRINT_BUF_LEN 12
+
+static int printi(char **out, int i, int b, int sg, int width, int pad, int letbase)
+{
+ char print_buf[PRINT_BUF_LEN];
+ register char *s;
+ register int t, neg = 0, pc = 0;
+ register unsigned int u = i;
+
+ if (i == 0) {
+ print_buf[0] = '0';
+ print_buf[1] = '\0';
+ return prints (out, print_buf, width, pad);
+ }
+
+ if (sg && b == 10 && i < 0) {
+ neg = 1;
+ u = -i;
+ }
+
+ s = print_buf + PRINT_BUF_LEN-1;
+ *s = '\0';
+
+ while (u) {
+ t = u % b;
+ if( t >= 10 )
+ t += letbase - '0' - 10;
+ *--s = t + '0';
+ u /= b;
+ }
+
+ if (neg) {
+ if( width && (pad & PAD_ZERO) ) {
+ printchar (out, '-');
+ ++pc;
+ --width;
+ }
+ else {
+ *--s = '-';
+ }
+ }
+
+ return pc + prints (out, s, width, pad);
+}
+
+static int print( char **out, const char *format, va_list args )
+{
+ register int width, pad;
+ register int pc = 0;
+ char scr[2];\r
+\r
+ for (; *format != 0; ++format) {\r
+ if (*format == '%') {
+ ++format;
+ width = pad = 0;
+ if (*format == '\0') break;
+ if (*format == '%') goto out;
+ if (*format == '-') {
+ ++format;
+ pad = PAD_RIGHT;
+ }
+ while (*format == '0') {
+ ++format;
+ pad |= PAD_ZERO;
+ }
+ for ( ; *format >= '0' && *format <= '9'; ++format) {
+ width *= 10;
+ width += *format - '0';
+ }
+ if( *format == 's' ) {
+ register char *s = (char *)va_arg( args, int );
+ pc += prints (out, s?s:"(null)", width, pad);
+ continue;
+ }
+ if( *format == 'd' ) {
+ pc += printi (out, va_arg( args, int ), 10, 1, width, pad, 'a');
+ continue;
+ }
+ if( *format == 'x' ) {
+ pc += printi (out, va_arg( args, int ), 16, 0, width, pad, 'a');
+ continue;
+ }
+ if( *format == 'X' ) {
+ pc += printi (out, va_arg( args, int ), 16, 0, width, pad, 'A');
+ continue;
+ }
+ if( *format == 'u' ) {
+ pc += printi (out, va_arg( args, int ), 10, 0, width, pad, 'a');
+ continue;
+ }
+ if( *format == 'c' ) {
+ /* char are converted to int then pushed on the stack */
+ scr[0] = (char)va_arg( args, int );
+ scr[1] = '\0';
+ pc += prints (out, scr, width, pad);
+ continue;
+ }
+ }
+ else {
+ out:\r
+ printchar (out, *format);
+ ++pc;\r
+ }
+ }
+ if (out) **out = '\0';
+ va_end( args );
+ return pc;
+}
+
+int printf(const char *format, ...)
+{
+ va_list args;
+
+ va_start( args, format );
+ return print( 0, format, args );
+}
+
+int sprintf(char *out, const char *format, ...)
+{
+ va_list args;
+
+ va_start( args, format );
+ return print( &out, format, args );
+}
+\r
+\r
+int snprintf( char *buf, unsigned int count, const char *format, ... )\r
+{\r
+ va_list args;
+
+ ( void ) count;\r
+ \r
+ va_start( args, format );\r
+ return print( &buf, format, args );\r
+}\r
+\r
+
+#ifdef TEST_PRINTF
+int main(void)
+{
+ char *ptr = "Hello world!";
+ char *np = 0;
+ int i = 5;
+ unsigned int bs = sizeof(int)*8;
+ int mi;
+ char buf[80];
+
+ mi = (1 << (bs-1)) + 1;
+ printf("%s\n", ptr);
+ printf("printf test\n");
+ printf("%s is null pointer\n", np);
+ printf("%d = 5\n", i);
+ printf("%d = - max int\n", mi);
+ printf("char %c = 'a'\n", 'a');
+ printf("hex %x = ff\n", 0xff);
+ printf("hex %02x = 00\n", 0);
+ printf("signed %d = unsigned %u = hex %x\n", -3, -3, -3);
+ printf("%d %s(s)%", 0, "message");
+ printf("\n");
+ printf("%d %s(s) with %%\n", 0, "message");
+ sprintf(buf, "justif: \"%-10s\"\n", "left"); printf("%s", buf);
+ sprintf(buf, "justif: \"%10s\"\n", "right"); printf("%s", buf);
+ sprintf(buf, " 3: %04d zero padded\n", 3); printf("%s", buf);
+ sprintf(buf, " 3: %-4d left justif.\n", 3); printf("%s", buf);
+ sprintf(buf, " 3: %4d right justif.\n", 3); printf("%s", buf);
+ sprintf(buf, "-3: %04d zero padded\n", -3); printf("%s", buf);
+ sprintf(buf, "-3: %-4d left justif.\n", -3); printf("%s", buf);
+ sprintf(buf, "-3: %4d right justif.\n", -3); printf("%s", buf);
+
+ return 0;
+}
+
+/*
+ * if you compile this file with
+ * gcc -Wall $(YOUR_C_OPTIONS) -DTEST_PRINTF -c printf.c
+ * you will get a normal warning:
+ * printf.c:214: warning: spurious trailing `%' in format
+ * this line is testing an invalid % at the end of the format string.
+ *
+ * this should display (on 32bit int machine) :
+ *
+ * Hello world!
+ * printf test
+ * (null) is null pointer
+ * 5 = 5
+ * -2147483647 = - max int
+ * char a = 'a'
+ * hex ff = ff
+ * hex 00 = 00
+ * signed -3 = unsigned 4294967293 = hex fffffffd
+ * 0 message(s)
+ * 0 message(s) with %
+ * justif: "left "
+ * justif: " right"
+ * 3: 0003 zero padded
+ * 3: 3 left justif.
+ * 3: 3 right justif.
+ * -3: -003 zero padded
+ * -3: -3 left justif.
+ * -3: -3 right justif.
+ */
+
+#endif
+
+
projects / freertos / commitdiff